DL413_Rev_1_Motorola_Radio_RF_and_Video_Applications_1994 DL413 Rev 1 Motorola Radio RF And Video Applications 1994

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DL413/D
REV 1

Radio, RF
and Video
Applications

®

MOTOROLA

@

MOTOROLA

Radio, RF
and Video
Applications
All products are sold on Motorola's Terms & Conditions of Supply. In ordering a product covered by this document the Customer agrees to be bound
by those Terms & Conditions and nothing contained in this document constitutes or forms part of a contract (with the exception of the contents
of this Notice). A copy of Motorola's Terms & Conditions of Supply is available on request.

Motorola reserves the right to make changes without further notice to any products herein. MOlorola makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application
or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.
"Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals", must be validated for each customer
application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products
are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal
injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended
or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
are
registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

®

The Customer should ensure that it has the most up to date version of the document by contacting its local Motorola office. This document
supersedes any earlier documentation relating to the products referred to herein. The information contained in this document is current at the date

of publication. /I may subsequenlly be updated, revised or withdrawn.

Includes literature available at June 1994
All trademarks recognized.

© MOTOROLA INC.
All Rights Reserved
First Edition DL413/D, 1991
DL413/D Rev. 1, 1994
Printed in Great Britain by Tavistock Press (Bedford) Ltd. 5000 9/94

2

Preface

This compilation of Application Notes, Engineering Bulletins, Design Concepts,
etc. was originally published by the European Literature Centre of Motorola Ltd.
in Milton Keynes, England, and has subsequently gained worldwide acceptance.
Because of the worldwide popularity of the Application Manuals Series it is important for the reade r to take note of the followi ng:
The various Application Notes, Engineering Bulletins, Design Concepts, etc.
which are included were developed at Design Centres strategically located
throughout the global community and many. were originally written to support a
local need. Whilst the basic concepts of each of the publications included may
have broad global applicability, specific Motorola semiconductor parts may be
referred to that are currently available for limited distribution in a specific region
and may only be supported by the country of origin of the document in which it
is referenced.
Also included in the series for completeness and historical significance are
documents that may no longer be available individually because obsolete
devices are referenced or perhaps, simply, the original document is out of print.
Such items are markep in the Table of Contents, Cross Reference, Abstracts and
on the first page of the document with the letters 'HI' to indicate that these
documents are included for Historical Information only.
All the Application Notes, Engineering Bulletins, Design Concepts, etc. are
included to enhance the user's knowledge and understanding of Motorola's
products. However, before attempting to design-in a device referenced in this
Series, the user should contact the local Motorola supplier or sales office to
confirm product availability and if application support is available.
Thank you.

3

Other books In this series Include:
OL40810 Rev. 1

8-bit MCU Applications Manllal

OL40910 Rev. 1

16132-bit Applications Manual

OL41010 Rev. 1

Power Applications Manual

OL41110Rev.1

Communications Applications

OL41210 Rev. 1

Industrial Control Applications

OL41410

FET Applications Manual

4

Contents
page
Device Cross Reference ................................................................................................................................ 9
Abstracts of Applications Documents ....................................................................................................... 13
Applications Documents

AN438

300W, 88-108MHz Amplifier Using the TP1940 MOSFETs Push-Pull Transistor ................. 21

AN448
AN460

"FlOF" Teletext using M6805 Microcontrollers ....................................................................... 25
An RDS Decoder Using the MC68HC05EO ............................................................................ 61

AN463

68HC05KO Infra-Red Remote Control ................................................................................... 101

AN479

Universal Input Voltage Range Power Supply for High Resolution Monitors
with Multi-Sync Capability ..................................................................................................... 113

AN749

Broadband Transformers and Broadband Combining Techniques for RF ............. :.............. 125

AN756

Crystal Switching Methods for MC12060/MC12061 Oscillators ............................................ 135

AN790
AN879

Thermal Rating of RF Power Transistors .............................................................................. 139
Monomax: Application of the MC13001 Monochrome Television Integrated Circuit ............. 147

AN925
AN932

UHF Preamplifier Centers on Budget Dual-Gate GaAs FET ................................................. 159
Application of the MC1377 Colour Encoder .......................................................................... 165

AN1019

Decoding Using the TDA3330, with Emphasis on Cable In/Cable Out Operation ................ 177

AN1020

A High-Performance Video Amplifier for High Resolution CRT Applications ........................ 185

AN1021

A Hybrid Video Amplifier for High Resolution CRT Applications ........................................... 189

AN1022
AN1025

Mechanical and Thermal Considerations in Using RF Linear Hybrid Amplifiers ................... 193
Reliability Considerations in Design and Use of RF Integrated Circuits ............................... 197

AN1027

Reliability/Performance Aspects of CATV Amplifier Design .................................................. 205

AN1028

35/50 Watt Broadband (160-240MHz) Push-Pull TV Amplifier Band 111 ................................ 213

AN1029
AN1030

TV Transposers Band IV and V Po = 0.5W/l.0W ................................................................. 221
1W/2W Broadband TV Amplifier Band IV and V ................................................................... 229

AN1032

How load VSWR Affects Non-Linear Circuits ....................................................................... 237

AN1033

Match Impedances in Microwave Amplifiers ......................................................................... 241

AN1034
AN1037

Three Balun Designs for Push-Pull Amplifiers ...................................................................... 247
Solid State Power Amplifier, 300W FM, 88-1 08MHz ............................................................. 253

AN1039

470-860 MHz Broadband Amplifier 5W ................................................................................. 257

AN1040
AN1041
AN1044

Mounting Considerations for Power Semiconductors ........................................................... 263
Mounting Procedures for Very High Power RF Transistors .................................................. 283
The MC1378 -

AN1047

Electrical Characteristics of the CR2424 and CR2425 CRT Driver Hybrid Amplifiers .......... 299

A Monolithic Composite Video Synchronizer .............................................. 285

AN1061

Reflecting on Transmission Line Effects ............................................................................... 303

AN1080

External-Sync Power Supply with Universal Input Voltage Range for Monitors ................... 315

AN1092

Driving High Capacitance DRAMs in an ECl System ........................................................... 335

AN1106

Considerations in Using the MHW801 and MHW851 Series RF Power Modules ................ 339

AN1107

Understanding RF Data Sheet Parameters .......................................................................... 343

AN1122

Running the MC44802A Pll Circuit ..................................................................................... 359

AN1207

The MC145170 in Basic HF and VHF Oscillators ................................................................. 371

AN1306

Thermal Distortion in Video Amplifiers .................................................................................. 377

AN1401

Using SPICE to Analyze the Effects of Board layout on System Skew when
Designing with the MCI 0/1 00H640 Family of Clock Drivers ................................................. 383

AN1402

MCI 0/1 OOHoo Translator Family I/O SPICE Modelling Kit ................................................... 395

AN1404

ECLinPS Circuit Performance at Non-Standard VIH Levels ................................................. 411

AN1405

ECl Clock Distribution Techniques ....................................................................................... 419

5

Contents (continued)
EB27A

Get 300 Watts PEP Linear Across 2 to 30MHz from this Push-Pull Amplifier ...................... 427

EB29

The Common Emitter TO-39 and its Advantages ................................................................. 431

EB59

Predict Frequency Accuracy for MC12060 and MC12061 Crystal Oscillator Circuits ........... 433

EB77

A 60 Watt 225-400MHz Amplifier - 2N6439 ......................................................................... 437

EB89
EB90

A 1 Watt, 2.3GHz Amplifier ................................................................................................... 441
Low-Cost VHF Amplifier Has Broadband Performance ........................................................ 445

EB93

60 Watt VHF Amplifier Uses Splitting/Combining Techniques .......... , ................................... 451

EB107

Mounting Considerations for Motorola RF Power Modules ................................................... 457

EB411

A Dighal Video Prototyping System ....................................................................................... 461

Additional Information ............................................................................................................................... 471

6

Device Cross
Reference

7

8

Device Cross Reference
This quick-reference list indicates where specific
components are featured in applications documents
reproduced in this Manual.
MC44250 ................................... EB411
MC44602P2 .............................. AN479
MC44802A ................................ AN1122
MC145170 ................................. AN1207
MHW612 ................................... EB107
MHW613 ................................... EB107
MHW709 ................................... EB107
MHW710 ................................... EB107
MHW720 ................................... EB107
MHW801 ................................... AN1106
MHW808 ................................... EB107
MHW820 ................................... EB107
MHW851 ................................... AN1106
MJE18004 ................................. AN1080
MJH18010 ................................. AN479
MOC81 02 .................................. AN1 080
MRF141G .................................. AN1041
MRF151G .................................. AN1041
MRF153 .................................... AN1041
MRF154 .................................... AN1041
MRF155 .................................... AN1041
MRF175G .................................. AN1041
MRF176G .................................. AN1041
MRF227 .................................... EB29
MRF260 .................................... EB90
MRF262 .................................... EB90
MRF264 .................................... EB93
MRF422 .................................... EB27A
MRF430 .................................... AN1041
MRF966 .................................... AN925
MRF2001 .................................. EB89
MTP4N90 .................................. AN1 080
TDA3301 ................................... AN1044
TDA3330 ................................... AN1019
TP 1940 ...................................... AN438
TP9383 ...................................... AN 1037
TPV375 ..................................... AN1 028
TPV593 ..................................... AN1 039
TPV596 ..................................... AN1029
TPV597 ..................................... AN1 030
UC3842A ................................... AN1 080
UC3843A ................................... AN1080

2N6439 ...................................... EB77
CA2820 ..................................... AN1022
CR2424 ..................................... AN1021
............................................ AN1047
............................................ AN1306
CR2425 ..................................... AN1021
............................................ AN1047
LT1 001 ...................................... AN1 020
LT1817 ...................................... AN1020
LT1829 ...................................... AN1020
LT5839 ...................................... AN1020
MC10E111 ................................ AN1405
MC10E211 ................................ AN1405
MC10H60x ................................ AN1402
MC10H641 ................................ AN1405
MC10H64X ................................ AN1401
MC10H660 ................................ AN1092
MC68HC05B6 ........................... EB411
MC68HC05EO ........................... AN460
MC68HC05KO ........................... AN463
MC68HC05T7 ........................... AN448
MC68HC11E9 ........................... AN1122
MC100E111 .............................. AN1405
MC100E211 .............................. AN1405
MC100H60x .............................. AN1402
MC100H641 .............................. AN1405
MC100H64x .............................. AN1401
MC100H660 .............................. AN1092
MC1377 ..................................... AN932
............................................ AN1044
MC1378 ..................................... AN1044
MC1658 ..................................... AN1207
MC1723 ..................................... EB27A
M C3423 ..................................... AN 1080
MC12060 ................................... AN756
............................................ EB59
MC12061 ................................... AN756
............................................ EB59
MC13001 ................................... AN879
MC14576 ................................... EB411
MC44011 ................................... EB411
MC44200 ................................... EB411

9

10

Abstracts of
Applications
Documents

11

12

----.,-:------..,-~~I

Abstracts
interference on a mUlti-sync colour monitor. It uses a
low cost MC44602P2 current mode controller-designed
specifically for driving high voltage bipolar transistorswith an MJH1801 0 switch mode power transistor.

AN438
300W, 88-108MHz Amplifier Using the
TP1940 MOSFETs Push-Pull Transistor
Provides the design of an efficient 300W amplifier with
high power gain, compact physical layout and operation on a 50V power supply. It uses the TPt 940, a high
power, high gain, broadband push-pull Power MOSFET with low Reverse Transfer Capacitance. Includes
circuit, parts list, PCB artwork and component layout.

AN749
Broadband Transformers and
Broadband Combining Techniques for RF
This application note provides a number of practical
examples of broadband transformers for RF applications. It includes detailed design formulae and performance data, and discusses power combining techniques
that are useful in designing high power RF amplifiers.

AN448
"FLOF" Teletext using M6805
Microcontrollers
The "-1" members of Motorola's M68HC05 MCU family
provide a cost-effective method of adding On Screen
Display (OSD) to TVs and VCRs. This note describes
an example of Full Level One Feature (FLOF) Teletext
control software written forthe MC68HC05T7tocontroi
type 5243 Teletext chips. Around 3K bytes of ROM are
used, allowing the code to fit with tuning, OSD and
stereo functions into the 7.9Kbytesofthe MC68HC05T7.
The example software includes the Spanish implementation of Packet 26; Packet 26 allows for the substitution of specific characters for a particular country.

AN756
Crystal Switching Methods for MC12060/
MC12061 Oscillators
This report discusses methods of using diodes to select
series resonant crystals electronically. Circuit designs
suitable for use with crystal frequencies from 100kHz to
20MHz are developed, with emphasis on minimizing
frequency pulling. Although developed for use with the
MC12060 and MC 12061 integrated circuit crystal oscillators, the techniques will generally be useful in any
application where it is necessary to select electronically
one of a group of crystals with minimum disturbance to
the series resonant frequency of the selected crystal.

AN460
An RDS Decoder Using the
MC68HC05EO
The Radio Data System (RDS) adds digital data capability to VHF FM transmissions on band II (87.5 to
t 08MHz). The system is in use in the UK and in several
other European countries, and it is intended that it will
be adopted eventually by most of Western Europe; it is
defined by EBU Technical Document 3244. Information is transmitted in groups of four 26-bit blocks on a
supressed 57kHz sub-carrier. This note describes an
MC68HC05EO-based clocklradio application; it includes
a complete software listing.

AN463

AN790

Thermal Rating of RF Power Transistors

Reliability is of primary concern to most transistor
users. The degree of reliability achieved in practice is
controlled by the device user because he determines
environmental conditions and the stress levels applied.
Knowledge of the basic physical properties of the
materials, and the methods used to calculate thermal
resistance, will assist the user in transistor selection
and equipment design. This note clarifies and corrects
some long-standing industry-wide assumptions about
thermal resistance and high temperature derating.

68HC05KO Infra-Red Remote Control

In addition to the same CPU and registers as other
members of the M68HC05 family the MC68HC05KO
has a 15-stage multi-function timer and 10 bidirectional
1/0 lines. A mask option is available for software program mabie pull-downs on all the 1/0 pins; 4 of the pins
are capable of generating interrupts. It is ideally suited
for remote-control keyboard applications because the
pull-downs and the interrupt drivers on the port pins
allow keyboards to be built without any external components except the keys themselves. This application
makes use of many of the on-chip features to control a
TV infra-red remote control.

AN879
Monomax: Application of the MC13001
Monochrome Television Integrated Circuit
This application note presents a complete 12" black
and white line-operated television receiver including
artwork for the printed circuit board. It is intended to
provide a good starting point for the first-time user.
Some of the most common pitfalls are overcome and
the significance of component selections and locations
are discussed.

AN925
UHF Preamplifier Centers on Budget
Dual-Gate GaAs FET

AN479
Universal Input Voltage Range Power
Supply for High Resolution Monitors with
Multi-Sync Capability

The signal-to-noise ratio of a communications system
can be improved by increasing the power of the transmitter, increasing the gain of the antenna, or improving
the sensitivity of the receiver. A low-noise preamplifier
is an economical solution for receiver enhancement
and this note describes the design, construction and
performance of a 400-512MHz preamplifier using Motorola's dual-gate GaAs FET.

This note describes an easy-to-build, high performance,
low cost 1OOW flyback power supply, able to work on
any mains supply from 85Vac to 265Vac, and from
40Hz to 100Hz. It is automatically synchronised to the
horizontal scanning frequency for minimum screen

13

Abstracts (continued)
AN932
Application of the MC1377 Colour
Encoder

AN1025 Reliability Considerations In Design
and Use of RF Integrated Circuits

The MC1377 is and economical, high quality, RGB
encoderfor NTSC or PAL applications. It accepts RGB
and composite sync inputs, and delivers a 1V p-p
composite NTSC or PAL video output into a 750 load.
It can provide its own colour oscillator and burst gating,
or it can easily be driven from external sources. Performance virtually equal to high-cost studio equipment
is possible with common colour receiver components.

RF integrated circuits -located at strategic points in a
CATV system - feature prominently in the overall
reliability assessment. Low noise and distortion require
state-of-the-art transistor structures. Gold metallization,
thermal equilibrium and automated process control
have resulted in transistor lifetimes of over 100 years.
An overview of the physics of construction involved with
the die and interconnects is discussed, together with a
definition of major reliability terms and an introduction
to hardware and software microcircuit reliability tools.

AN1019 Decoding Using the TDA3330, with
Emphasis on Cable In/Cable Out Operation

AN1027 Reliability/Performance Aspects of
CA TV Amplifier DesIgn

The TDA3330 is a Composite Video to RGB Colour
Decoder originally intended for PAL and NTSC colour
TV receivers and monitors - so its data sheet concentrates on picture tube drive. This practical application
note supplements the data sheet by providing circuits
for video cable drive as used in video processing, frame
store and other specialized applications, and expands
on TDA3330 functional details. Includes PCB artwork
and layout of an evaluation board.

Discusses the reliability advantages offered by the RF
hybrid amplifier used in CATV applications. The active
part of the hybrid is the transistor - metallization,
ballasting and ruggedness are reliability-related factors
that must be considered by the device engineer when
designing a high performance CATV transistor. Vertical
and horizontal geometry and device distortion are per:
formance-related factors that must also be taken into
account. The relationship between these factors is
examined, and life test data is presented to illustrate the
advantages gained by careful device design.

AN1020 A High-Performance Video Amplifier for
High Resolution CRT Applications
This note describes a state-of-the-art video amplifier
making use of the superior performance characteristics
of Motorola CRT driver transistors. In particular, it
shows the high speed obtainable with low DC power
consumption. The circuit is insensitive to load variations and interconnect methods.

AN1028 35/50 Watt Broadband (160-240MHzj
Push-Pull TV Amplifier Band 11/
The main design aim for this broadband ultra-linear
push-pull amplifier was to keep the design as simple as
possible, in order to obtain the best performance from
the two TPV375 transistors and to minimise the cost. A
further target was to obtain the maximum gain by
reducing input matching circuit losses. Includes circuit,
background description, Smith charts and PCB layout.

AN1021 A Hybrid VIdeo Amplifier for High
Resolution CRT Applications
Many of the 1024 x 1024 and 1280 x 1024 pixe I, 64kHz
horizontal sweep rate CRTs used in CAD/CAM and
high resolution graphics applications have not realized
their potential performance because of the speed of
their video amplifiers. The CR2424 and CR2425 video
amplifiers are hybrid circuits designed for high resolution CRT applications. Theyfeature less than 2.9ns rise
and fall time for a 40V output swing, and provide a low
power dissipation solution to the problem.

AN1029 TV Transposers Band IV and V
Po = 0.5W/1.0W
Describes the performance of a470-860MHz broadband
ultra linear amplifier designed for use in band IV and V
TV transposers. The design is based on the TPV596,
and is intended to be as inexpensive and straightfor·
ward as possible: the load line is defined to provide the
correct match for peak power; VSWR at the collector is
less than 2:1; input matching is designed to provide flat
gain with decreasing frequency; and the design is
optimized with a CAD program.

AN1022 Mechanical and Thermal Considerations
In USing RF Linear Hybrid Amplifiers
Motorola's thin film hybrid amplifiers are medium power
(0.2W to 2.0W power output) broadband devices (1 to
1OOOMHz) that are biased in a class A mode for linear
operation. To ensure a proper electrical and mechanical interface with adequate RF and thermal characteristics, certain guidelines are presented here so that the
design engineer can obtain maximum electrical performance and the longest operating life.

AN1030 1W/2W Broadband TV Amplifier
BandlVand V
Describes thedesign and performance of a 470-860MHz
broadband linear amplifier for use in band IV and V TV
transposers, based on a TPV597 transistor. The design uses a reflection technique to achieve an insertion
loss of 6dB per octave with OdB for the highest frequency. Two amplifiers are connected together with

14

Abstracts (continued)
3dB quadrature hybrids to create a balanced amplifier
avoiding the inconvenience of needing a good match of
reflected power.

a pair of TP9383 transistors in push-pull configuration;
TP9383 is a double-diffused silicon epitaxial transistor
using gold metallization and diffused ballast resistors
for long operating life and ruggedness.

AN1032 How Load VSWR Affects Non-Linear
Circuits

AN1039

If your amplifiers pass lab tests but fail QC testing, the
testing environment - not the product - is most likely at
fault! Often the culprit is correlation oltest systems - RF
Correlation occurs only when target error limits are
adhered to on a continuous basis among two or more
testing stations. Such correlation is essential for nonlinear RF and microwave power amplifiers, whose
circuits are extremely sensitive to the impedance of
their loads. It is easy to compensate for the insertion
loss errors in an attenuator, but much more difficult to
compensate for load VSWR.

470-860 MHz Broadband Amplifier 5W

This note describes an ultra linear broadband (470860M Hz) amplifier developed for TV transposer applications. The amplifier incorporates two TPV593 transistors. Each transistor is used to build a separate
broadband amplifier which are combined with 3dB
hybrids. Includes circu it, parts list and PCB layout.

AN1040 Mounting Considerations for Power
Semiconductors
The operating environment is a vital factor in setting
current and power ratings of a semicond uctor device.
Reliability is increased considerably for relatively small
reductions in junction temperature. Faulty mounting
not only increases the thermal gradient between the
device and its heat sink, but can also cause mechanical
damage. This comprehensive note shows correct and
incorrect methods of mounting all types of discrete
packages, and discusses methods of thermal system
evaluation.

AN1033 Match Impedances in Microwave
Amplifiers
The key to successful solid-state microwave poweramplifier design is impedance matching. In any highfrequency power-amplifier design, improper impedance matching will degrade stability and reduce circuit
efficiency. At microwave frequencies, this consideration is even more critical, since the transistor's bondwire inductance and base-to-collector capacitance become significant elements in input/output impedance
network design. Includes table of characteristic impedance and velocity factor for various width/height ratios
and various materials.

AN1041 Mounting Procedures for Very High
Power RF Transistors
High power (200-600W) RF semiconductors such as
the MRFI53 ... and MRFI41G ... series dissipate an
abnormally large amount of heat within a small physical
area. Heat sink material, surface finish, mounting
screws, washers and screw torque are extremely importantfactors in ensuring reliability. This note explains
why.

AN1034 Three Balun Designs for Push-Pull
Amplifiers
Single RF power transistors seldom satisfy today's
design criteria; several devices must be coupled to
obtain the required amplifier output power. The pushpull technique is often chosen because it allows input
and output impedances to be connected in series for
RF operation. Balun-transformers provide the key to
push-pull design. This note develops three balun-transformers, culminating with a microstrip version. None of
the baluns was tuned nor were the parasitic elements
compensated. In this way, their deviation from their
theoretical performance could be evaluated more easily.

AN1044 The MC1378 - A Monolithic Composite
Video Synchronizer
The MC1378 provides an interface between a remote
composite colour video source and local RGB. On-chip
circuitry can lock a local computerto the remote source,
switching between local and remote signals to generate composite video overlays. This detailed note describes local and remote operation, picture-in-picture
applications and the design of test fixtures to help
system development. Printed circuit artwork for an
evaluation board is provided. The NTSC/PAL colour
encoder is similar to the MCI377, discussed in detail in
AN932.

AN1037 Solid State Power Amplifier,
300W FM, 88-108MHz
A solid state power amplifier in a high efficiency FM
transmitter can be made by operating a number of
building block amplifiers in parallel. This note describes
such a building block amplifier with high output power,
high gain, good collector efficiency and broadband (88108 MHz) frequency response. The design is simple,
reproducible and reliable, and is suitable for several
architectures. The amplifier has been developed using

AN1047 Electrical Characteristics of the CR2424
and CR2425 CRT Driver Hybrid Amplifiers
Describes the circuit and thermal characteristics of the
CR2424 and CR2425 CRT driver hybrid amplifiers, and
discusses three different methods of protecting against
damage by a tube arc. Provides details of bandwidth
and rise and fall times.

15

,'!

r

Abstracts (continued)
AN1061

Reflecting on Transmission Line Effects

AN1122

In recent years, microprocessors and digital logic have
seen substantial increases in line drive capability. The
fast rise and fall times of modern devices make an
understanding of trans mission lines and their effects on
system reliability a necessity. Includes a procedure for
assessing possible transmission line problems in practical designs.

Running the MC44B02A PLL Circuit

The MC44802A provides the Phase locked loop (Pll)
portion of a tuning circuit intended for TV, FM radio and
set-top converter applications up to 1.3GHz; a complete tuning circuit is formed by adding a Voltage
Controlled Oscillator (VCO) and mixer. The data sheet
recommends use of an MCU for sending the control
bytes that set the tuning frequency. This note describes
a serial (IIC) interface with an MC68HC11 E9 in a tuner
design - the information is sufficiently general to allow
almost any MCU to be used. Includes M68HC11 program listing.

AN10BO External-Sync Power Supply with
Universal Input Voltage Range for Monitors
As the resolution of colour monitors increases, the
performance and features of their power supplies becomes more critical. EMI/RFI generated by switching
power supplies can adversely affect resolution if switching frequency is not synchronised to horizontal scanning frequency. This 90W flyback switching supply
demonstrates the use of new high-performance devices in a low-cost design, and includes a new universal
input voltage adapter.

AN1207 The MC145170 in Basic HF and VHF
Oscillators
Frequency synthesisers such as the MC145170 use
digital dividers which are typically under MCU control.
Tuning in less than a millisecond can be achieved, and
the device can generate many frequencies from a
single reference source; the overall frequency capability
ranges from afew Hertzto 160MHz. Typical applications
include the carrier oscillator in transmitters, locaf
oscillator in receivers, cellular phones, and multiple
synchronised clocks in computers and other systems.

AN1092 Driving High Capacitance DRAMs in an
ECL System
In systems where speed and efficiency are of utmost
importance, designers often mix technologies to achieve
the right combination of speed, power, cost and processing capability. Motorola's Emitter Coupled logic (ECl)
makes it possible to operate up to 1GHz clock rates.
However, ECl speeds are not necessary in memory
that is not accessed every clock cycle - a large CMOS
DRAM is cheaper and uses less power and board
space than ECl memory. The MC1 OH/1 OOH660 4-bit
ECl-TTL Load Reducing DRAM Driver was designed
as a translator for such applications.

AN1306

Thermal Distortion in Video Amplifiers

Thermal distortion is a problem in many high resolution
video amplifiers. It occurs when there are instantaneous power changes in the transistor stages, and if the
problem remains uncompensated it leads to the visual
effect known as smearing. This note discusses what
smearing is, what causes thermal distortion, how to
measure it, and how to compensate for it.

AN1401 Using SPICE to Analyze the Effects
of Board Layout on System Skew when
Designing with the MC101100H640 Family
of Clock Drivers

AN1106 Considerations in Using the MHWB01
and MHWB51 Series RF Power Modules
The MHW801 and MHW851 series of power modules
are designed for use in cellular portable radios. A
considerable amount of applications information is included in the data sheet; this note provides additional
information concerning general electrical considerations, noise characteristics, gain control, circuit considerations and mounting.

Illustrates the complex influences of board layout on
the total skew of a system when designing with the
MC1 OH/1 OOH64x family of clock drivers. Discusses
transmission line theory and the various termination
techniques, and presents guidelines to assist designers in analyzing board layouts and loading schemes
using SPICE simulations to predict and minimise the
total skew of a system.

AN1107 Understanding RF Data Sheet
Parameters

AN1402 MC101100HOO Translator Family 110
SPICE Modelling Kit

The data sheet is often the only source of information
about the characteristics and capability of a product.
This is especially true of RF devices, which have many
unique specifications. It is therefore important that the
manufacturer and designer speak acommon language.
This paper reviews the significance of the quoted
values and highlights critical characteristics. Descriptions cover the procedures used to obtain impedance
and thermal data, the importance of test circuits, low
noise considerations and linearity requirements.

The difficulties of designing high-speed, controlledimpedance PC boards - and the expense of reworking
them - makes it essential for designers to model circuit
performance prior to committing to a layout. This note
provides sufficient information for basic SPICE analysis on the interconnect traces driving or being driven by
the 'H600, 'H601, 'H602, 'H603, 'H604, 'H605, 'H606
and 'H607 translator chips. It includes schematics of
the input, output and ESD structures, and package

16

Abstracts (continued)
models which may affect the waveforms. A SPICE
parameter set for the referenced devices is provided.

ICs, temperature and DC supply voltage to help the
designer to predict the amount of frequency pull in a
particular design.

AN1404 ECLinPS Circuit Performance at NonStandard VIH Levels

EB77
A 60 Watt 22S-400MHz Amplifier2N6439

When ECLinPS devices are interfaced to other technologies there may be times when the input voltages do
not meet the specification detailed in the ECLinPS data
book. This application note discusses the consequences of driving ECLinPS devices with an Input
Voltage HIGH level which is outside the specification.

AN140S

This bulletin describes a 60 watt, 28 volt broadband
amplifier covering the 225-400 MHz military communications band. The amplifier may be used singly as a 60
watt output stage in a 225-400 MHz transmitter; by
using two of these amplifiers combined with quadrature
couplers a 100 watt output amplifier stage may be
constructed. The circuit is designed to be driven from a
50 ohm source and work into a nominal 50 ohm load.

ECL Clock Distribution Techniques

Clock skew - the time difference between supposedly
simultaneous clock transitions within a system - is one
of the main factors limiting system performance at high
frequencies. If clock skew can be reduced, designers
can increase performance without using faster logic or
more complex and more expensive architectures.
Emitter Coupled Logic (ECL) technologies offer a
number of advantages over the CMOS and TTL alternatives; this note describes the advantages, the three
skew problem areas, and methods of clock distribution
to minimise skew.

EB89

A 1 Watt, 2_3GHz Amplifier

This S-band amplifier features simplicity and
repeatability, delivering 8dB minimum gain at 1 watt
output on a 24V supply. It uses an MRF2001 transistor
in a common base, class C configuration, and is tunable
from 2.25 to 2.35GHz. Applications include micowave
communications and other systems requiring medium
power, narrow band amplification. The Bulletin stresses
the importance of physical construction as well as
electrical design.

EB27A
Get 300 Watts PEP Linear Across 2 to
30MHz from. this Push-Pull Amplifier

EB90
Low-Cost VHF Amplifier Has Broadband
Performance

Includes circuit, PCB artwork and layout for a 300W
push-pull linear amplifier based on two MRF422s, designed to operate over the 2 to 30MHz band. An
MC1723 VOltage regulator is used as a bias supply.

This bulletin presents two VHF amplifier designs intended for FMor CWservice inthe 136-174 MHz band.
Bothfeaturethe Motorola MRF260 and MRF262 plastic
encased VHF transistors which are rated at 5.0 Wand
15 W power output respectively. The devices are packaged in a standard TO-220 silicone epoxy case with the
emitter wired to the metal tab and centre lead of the
device. This common emitter configuration results in
good RF performance, improved thermal conductivity,
and ease of mounting in an RF amplifier by connecting
the transistor mounting flange to RF and DC ground.

EB29
The Common Emitter TO-39 and its
Advantages
The Common EmitterTO-39 package differs from conventional TO-39s or TO-5s in that the emitter - not the
collector - is connected to the metal case. With NPN
transistors this configuration allows direct connection
of the can to RF and negative DC ground in many class
Band C circuits. There are two important advantag es:
by connecting the case to RF ground, emitter inductance is reduced and gain increased by 3 to 5 dB over
that of comparable, conventionally wired transistors.
And the case may be directly pressed, clipped, or
soldered to the heat sink with no effect on RF performance.

EB93
60 Watt VHF Amplifier Uses
Splitting/Combining Techniques
Proven combining techniques can be used to obtain
higher output power and added reliability at VHF.
Simple matching networks and power transistors with
moderate gain can produce performance comparable
to that of a single-stage amplifier with a larger, more
expensive device. Though not the ultimate answer, the
splitter/combiner method has distinct advantages over
designs that force transistors into a parallel configuration. This 60 W amplifier operates from 150 to 175 MHz
and features two low-cost MRF264 transistors. The
design uses a modified Wilkinson combiner technique
to produce 60W output with a drive level of 15W.

EBS9
Predict Frequency Accuracy for
MC12060 and MC12061 Crystal Oscillator
Circuits
Crystal oscillators are used to generate a precise and
highly stable signal. Such circuits typically provide this
signal at a frequency close to the resonant freq uency of
their crystal. However, circuit components and other
factors external to the crystal influence Its natural
resonance to some degree, an effect often referred to
as "pulling" or "warping". This bulletin discusses the
variation in crystal frequency as a function of different

17

Abstracts (continued)
EB107
Mounting Considerations for Motorola
RF Power Modules
The packaging used for Motorola RF Power Modules
consists of a copper flange on which the ceramic
substrates are soldered, and a non-conductive cover
which is either a snap-on design or attached by epoxy.
The substrates are either 96%Alumina, 95.5%Alumina,
or 99% Beryllium Oxide, and are attached to the copper
flange using lead-tin or indium based soft solders. This
bulletin discusses the mechanical factors that should
be considered when mounting these modules in equipment.

EB411

A Digital Video Proto typing System

This bulletin describes a Digital Video Prototyping
System (DVPS) developed using Motorola's latest multimediadevices, together with a PC-based Field Programmable Gate Array (FPGA) development system. It is
designed 10 provide a fast and effective means of
prototyping and demonstrating digital video processing
functions. A Reference Section lists datasheets and
user manuals containing deJailed descriptions and
information on the devices. The DVPS has been successfully used to implement two TV sub-systems,
namely a Picture-In-Picture Processor and a 4:3 to 16:9
Picture Processor, which are also described.

18

Applications
Documents

19

20

AN438
300W, 88-108MHz Amplifier using the
TP1940 MOSFETs Push-pull Transistor
By Georges Chambaudu
Motorola Semiconducteurs Bordeaux SA

INTRODUCTION
The TP1940 is a high power, high gain and broadband
device with low Reverse Transfer Capacitance, Crss '
It makes possible fully solid-state transmitters of
above 5 kW for FM broadcasts.

The 300 W amplifier described in this Application Note
has these features:

Like all M OS devices, it is susceptible to damage from
electrostatic discharge. Observe reasonable
precautions in handling and packaging it.

• Compact physical layout

• Operates from a 50 V supply
• High power gain
• High efficiency
Typical data. for the circuit in Figure 2 are given below.

FUNCTIONAL TESTS (V DD

= 50 V, Pout = 300 W, Idq = 2 x 200 mAl

Option 1 (with C9p and without C9s)
f (MHz)

GA (dB)

11

Option 2 (with C9s and without C9p)
GA (dB)

(%)

11

(%)

108

19.2

62

18.3

65.4

98

19.7

62.6

19.1

68

88

19.4

64

19.6

66.6

Note:
1. Bias increases counter-clockwise with R4.
2. Bias shown is set for 200 mA at 50 V.
3. A copper heat spreader must be mounted on, or laid on top of, a heat sink with thermal grease interface.
4. Drain efficiency can be increased by:
a. Lowering Drain Idle current (power gain will be reduced by 1-2 dB).
b. Increasing the value of feedback resistors R8 and R9. This will change the Gain-Frequency slope and
Input VSWR. The value of C1 must be raised.
5. In addition to the normal cooling of the units, some air flow is recommended over the top side of the amplifier
boards.

21

I

>

+

I-

::::>

a..

I::J

o

:;:'@'

c:c:

00

"';::;

-.;::;

a. a.
00
en "a.
"mm

--

00

Li..i

-l

(§
en
Figure 1. Component layout of 300 W amplifier

22

R3

-:p
C9s'

0UTPUT

e9p'

lC5

I

* see Table on page 1

R9

Cl

24pF Ceramic Chip

R5

C2

1OOOpF Ceramic Chip

R6

Thermistor, 1OKn at 25°C/2.5Kn at 75°C

R7

2Kn 1/2W

RB, R9

KDI Pyrofilm PPR515-20-3 or EMC Technologie

C3, Cl0,
Cll

O.lIJ.F Ceramic Chip

C4, C5

1OOOpF Ceramic Chip

6.B - B.2 Kn 1/4W (depending on FET gt5)

model 5310 or equivalent 100n

C7

5000pF Ceramic Chip

L1

10 turns AWG #16 enamelled Wire, 0.2" I.D.

CB

0.471lF Ceramic Chip or lower values in parallel
to reach the value indicated.

L2

Ferrite beads, 1.5 IlH Total

L3, L4

Lead lengths of RB and R9, 0.6" total.

C9p

ARCO 404, B-60pF or equivalent

C9s

ARCO 425, 40-200pF or equivalent

Note 1:

All ceramic capacitors of 5000pF or less
value are A TC type 100 or equivalent.

Note 2:

Rl

FET

TP1940

Tl

9:1 impedance ratio (input transformer)

In

25n, 0.062' 0.0. semi rigid co-ax., with
L = 2B mm, I = 11 mm (see Figure 3)

The Table on Page 1 shows the effect of
operating with C9p only or C9s only.

T2

4:1 impedance ratio (output transformer)
25n, 0.090' 0.0. semi rigid co-ax., with
L = 19 mm, I = 9 mm (see Figure 3)

lKn l/2W

(Tl transformer must be loaded with ferrite

R2

1.5Kn 1/2W

R3

1.5Kn2W

or other type ferrite cores, such as Fair-Rite

R4

1Kn Trimmer Potentiometer

Products Corporation E and I types 9467012002
and 9367021002 respectively)

toroids of suitable dimensions and lJ.i of 35-40,

Figure 2, 300 W, 88-108 MHz amplifier schematic and parts list

23

Centre

Tap

4:1

IMPEDANCE
RATIO

Figure 3. Constructional details of transformers

Epoxy glass 1'16'

Figure 4. Printed Circuit Board (not full size)

24

AN448

"FLOF" Teletext using M6805 Microcontrollers
By Peter Topping
MCU Applications
Motorola Ltd. East Kilbride

1. INTRODUCTION
The "r members of the MC68HCOS family of MCUs provide a convenient and cost effective method of adding
on-screen-display (OSD) to TVs and VCRs. As well as the 64-character OSD capability. they include 8 Kbytes of
ROM (adequate forTeletext. frequency-synthesis. stereo and OSD). 320 bytes of RAM. a 16-bit timer and 8 pulsewidth-modulated D/A converters. The MC68HCOST7 also includes IIC hardware and. by using a S6-pin package.
4 ports of I/O independent of the OSD. serial and D/A outputs. It is thus suitable for large full-feature chassis.
The MC68HCOST1 is in the middle of the price/performance range and includes most of the features of
the MC68HCOST7 but in a 40-pin package. This is achieved by sharing I/O with the other pin functions (SPI. OSD.
D/Al. Even if all these features are used. there is sufficient I/O for most applications.
The MC68HCOST2 is a 16K upgrade of the MC68HCOST1 and the MC68HCOST3 a 24K version with increased
RAM (S12 bytes) and enhanced OSD (112 characters and 2 rows of OSD buffer). The low cost MC68HCOST4
has S Kbytes of ROM and 96 bytes of RAM making it suitable in simpler (eg mono. non-Teletext) applications.
The T4 and T7 also include a 14-bit D/A converter to facilitate voltage synthesis tuning. There are EPROM (and
OTP) versions of the T3 (including T1 and T2 emulation). T4 and T7.
This application note describes an example of Teletext control software written for the MC68HCOST7 which
directly controls Teletext chips of the type S243. Spanish FLOF Teletext (leveI1.S) is handled using packet X/26.
If no CCT teletext chip is present on the IIC bus (as indicated by the lack of an acknowledge). all Teletext functions
are disabled in software. About 3Kbytes of ROM are used allowing the code to fit into the 7.9K bytes available
in an MC68HCOST7 along with tuning. OSD and stereo functions.
The software in the included listing has been written for the MC68HCOST7 but could. with a little modification,
be implemented on other M680S microcontrollers. A microcontroller without IIC hardware can be used as long
as additional software is included to facilitate the IIC bus using I/O pins. An example of IIC master I/O driven
software can be found in application note AN446.

2. "FLOF" TELETEXT FEATURES
Full Level One Feature (FLOF) Teletext utilises "ghost" packets to provide features in addition to those available
with the original CCT Teletext. The primary enhancement is the provision of a menu with a choice of four linked
pages selectable by the user with a single press of one of four coloured buttons on the remote control. The menu
itself is sent in the ghost page using packet 24 while the linked page numbers are contained in packet 27. In
addition to linked pages. packets 26 and 30 are used. Packet 26 allows for the substitution of selected characters
in the display by special characters specific to a particular country. This example application includes the Spanish
implementation of packet 26. The broadcast service data packet (8130) is used to get the initial (index) page for
each channel and to display station identification information.

25

"Ghost" packets handled
)(/24 :

The FLOF menu information contained in this page extension packet is transferred by the microcomputer to
row 24 ofthe display chapter. When links are disabled because there is no packet 27 (destination code 0) or when
bit 4 of byte 43 is 0, row 24 is blank.
)(/26 :

Optional handling of modes 1xxxx, 01111 and 00010 in accordance with the Spanish Teletext specification. All
the additional characters which are available in the 5243 CCT chip are handled. The feature can be disabled with
a hardware link on an I/O pin (see figure 1) so that the software can be used at level 1.0 in non-Spanish countries
also using packet 26.

><127:
This packet contains the linked page numbers for the red, green yellow, blue and index (black) keys. Bit 4 on the
link control byte (byte 43) is used to determine if these links are enabled (1) or disabled (0). When enabled, the
Spanish specification requires that bits 1, 2 and 3 be used to enable the green, yellow and blue links respectively.
This use of these bits is not defined in the World Teletext Specification. For this reason their use is selectable by
a hardware link (see figure 1). If these bits are not used. all links (if enabled by bit 4) will be taken from packet 27·
but will be automatically disabled if the broadcast links are default (FF3F7F) or invalid.

8/30:
The broadcast service packet is used to supply the index page number on exit from standby and (if teletext is not
stopped) after a channel change. Bytes 10-30 ofthis packet are displayed for 5 seconds on exit from standby and
(if teletext is not stopped) after a channel change.

3. IMPLEMENTATION
The software listing is in two parts. The first part contains the "idle"loop and IIC routines from the main 'TV control
part of the MC68HC05T7 application. The idle loop controls the timing of everything performed by the
microprocessor, scans the local keyboard, checks whether or not an IR command has been received, etc. It also
monitors the relevant flags in the Teletext chip and performs the tasks (eg fetching linked pages) which have to
be performed independently of requests for the user.
The second and main listing is the Teletext module itself. It contains all the subroutines required to carry out
automatic and user requested Teletext activity. Both modules use the same RAM allocation file (RAMT8.S05)
which is included in the listing of the Teletext module. This listing also includes a symbol cross-reference table.
Figure 1 shows a simplified circuit diagram ofthe application. Most of the MC68HC05TTs I/O is used for purposes
other that Teletext and is not shown in detail. Communication with the 5243 Teletext chip is via an IIC bus in which
the T7 is always the master. The function ofthe three I/O pins used forTeletext is described under "Ghost packets
handled" and "Inputs and Outputs".
A version of this Teletext software has been implemented on an MC68HC05C4 for use in a 'TV where the other
control functions were handled by a separate microcontroller. The signal from the IR pre-amp was fed into the
C4 which used Teletext commands to control a 5243 via a software IIC bus. Non-Teletext commands were regenerated by the C4 and sent to the other microcontroller. This arrangement allows Teletext to be added to a
chassis which was originally designed without considering Teletext.

26

O.S.D., Local keyboard,
Analogues, Standby, Mute,
Stereo, AV, etc.

5V
Contrast Reduction
Fast Blank

R

G
2 x4k7
I/O

2 x 22pf

~ ':'TOM
!1

I.R.
Pre-amp

OSC1

SCL

SCL

5243
SDA

SDA

BkxB
RAM
(eg.
MCM6264)

OSC2

MC68HC(7)05T7
PB3

TCAP

Picture
Control
5231

PB6

PB7

5V
Video

Figure 1. MC68HC(7)05T7 - Teletext application circuit

4. IDLE LOOP
In the example application the idle loop code is in the main TV control software module rather than in the teletext
module. Listing 1 shows the relevant parts of this module. The loop time is 12.BmS and it is at this rate that the
timing counters used by Teletext (CNT1 and CNT4) are incremented. The standby condition is checked first; if
the TV set is in standby then there is no IIC activity and hence no reading from, or writing to, the 5243. If the TV
has just exited from standby, as indicated by the flag 3,STAT2, then Teletext is initialised using the sub-routine
RESTRT. This sub-routine writes to the 5243's control and mode registers (R5, R6 and R7) and checks that the
IIC acknowledge is present. Ifthere was no acknowledge, as indicated by flag 6,STAT7, then no further Teletext
activity is attempted.
If an acknowledge is present. Teletext polling goes ahead, although it is suspended if there is a mute or time
display. A mute indicates that the channel has just been changed, or no channel is tuned. During time display,
all other Teletext activity is suspended. Re-initialisation using sub-routine START2 is performed if flag 7,STAT5
is set by a change of the tuned frequency.

27

Counter CNT4 is used to delay the transfer of packets 24 (page extension - FLOF menu), 27 (links), 26 (enhanced
display characters) and the control bits from row 25 (display page) after the initial arrival of a page. When row 24
is read the 5243 FOUN D fl~g is set to indicate that the arrival has been acted upon. If UPDATE is on then an update
indicator appears if the update control bit (C9) is set or if the sub-page has changed or if it is the first arrival of the
page. The update display is performed by the sub-routine ARRVD which clears the transient flags and enables
the required display, i.e. page no. in normal mode and the whole of row 0 in sub-page mode. Any boxed
information (eg sub-titles or newsflash) in the current page is also displayed. The last Teletext function performed
by the idle loop is the checking of the FOUND flag in the 5243. This is accessed via the IIC bus: it is on the last
(not displayed) row of the"di!\play page along with the current page and sup-page numbers and the control bits.
If there is a current Teletext transient (time, row 0 box or packet 8/30), the transient control branch from the idle
loop is executed. This routine checks to see if it is time to end the transient. If it is, the subroutine OSDLE is
executed. It resets transients for both the OSD generated by the MC68HC05T7 and Teletext. The sub-routine
RSTMD2 performs this function for Teletext. It is called from within the sub-routine OSDLE (not listed).

5. REMOTE CONTROL FUNCTIONS
TV;rxT
Toggle between TV & Teletext mode.

0-9
Number keys for entry of page and sub-page numbers
Red, Green, Yellow, Blue
Linked page access keys. The decoder stores four pages of text. These are the display page and the three pages
corresponding to the red, green and yellow links. The blue linked page is not acquired in advance. In the absence
of FLOF data or if the links are disabled by the control bit in packet 27, the red key is page+ 1 and the green key
page-l. Under these circumstances the requested page and the next three pages are acquired.
PC+/These keys always select page+ 1/page-l regardless of the availability of FLOF information. As with the red, green
and yellow keys, the page is displayed immediately if it is already in RAM.
INDEX
This key operates as an additional link with the difference that if the link is invalid the initial page from packet 8/
30 is selected.
SUB-PAGE/TIME
Text mode: Enter sub-page mode, (max. 3979). TV mode: Display time in top-right-hand corner for 5 seconds.
Pressing this key during a station identification display (packet 8/30 bytes 10-30) can be used to extend this display
beyond the five seconds it appears for, after a channel change.
STOP
Halt acquisition, "STOP" is displayed instead of page number. Press again to restart. If acquisition has been
stopped by partially entering a new page number then this key can be used to return to the original page.

28

MIX/NO-MIX
Toggle between Teletext and mixed display. Use of this key causes the display of the top status row for 5 seconds
if it is not being displayed because the current page is a newsflash or a sub-title. 5243 contrast reduction is enabled
in mixed mode.

FULL/TOP/BOT
Selects one of the three display formats. normal. top half enlarged. bottom half enlarged.

REVEAL
Reveal hidden text. toggle action.

UPDATE
Return to picture until a new version of the requested page arrives. When it arrives. its page no. is displayed in
the top-right-hand corner. the key operates in both TV and Teletext mode. set is put into TV mode. Any boxed
information (alarm clock. newsflash or sub-title) will be displayed. In sub-page mode the complete header is
displayed so that both page & sub-page numbers can be seen. Cancel update by entering Teletext mode and then
going back to TV mode by pressing the TVIText key twice.

6. TELETEXT SUBROUTINES

6a. Subroutines:

TVTX. UPDATE. DIGITO and GETIT

The Teletext module (listing 2) comprises various sub-routines which are used both by the idle loop and to perform
any Teletext actions initiated by commands from the IR remote control. They are described in the order in which
they appear in the listing.
TVTX is executed when the TV{TEXT button is pressed. Its function is to toggle between TV mode and Teletext
mode. The flag O.STAT indicates the current mode. This flag routes the microprocessor to execute eitherTXTOFF
or TXTON according to the current mode. TXTON checks that Teletext hardware is present and does nothing if
there has been no IIC acknowledge. If. however. a 5243 is present in the TV. it clears all transients (OSDLE) and
sets up the Teletext mode. It initialises the control registers (R5 and R6) to display text and background both in
and out of boxes. For newsflashes the set-up is text and background within boxes and picture outside. TXTOFF
also resets transients but forces TV mode and sync. Polling and updating continue as a background activity.
When the UPDATE key is pressed the update flag 4.STAT2 is set and TXTOFF executed so the TV is forced to
TV mode. If there is a current transient hold (eg time). the hold is cleared before TXTOFF is executed.
The number entry sub-routine DIG ITO branches to DIGITS in sub-page mode but otherwise accepts any number
key as a page number input. Three digits are required. the pointer PDP holding the current position (0. 1 or 2 for
hundreds. tens or units). During entry the flag 2.STAT is set to stop Teletext activity. The numbers have to be
written to the top-left-hand corner of the display page as well as saved in RAM. Once all three digits have been
entered the page is requested and page acquisition restarted.
The code at label GETIT makes this request afterfirst checking whether or notthe selected page has already been
requested (it could be the current display page or an already requested linked page). If it has. then a switch is made
to the chapter associated with the appropriate acquisition circuit and no new request is generated. If not. the new
request is made and the FOUND flag set.

29

6b. Subroutines:

Colours, INDEX, NPAGE and PPAGE

The four colour keys (Red, Green, Yellow and Blue) are primarily intended for selecting Teletext linked pages.
When pressed the chapter which corresponds to the appropriate acquisition circuit is selected for display. If links
are disabled (by the link control bit or because there is no packet 27), then the RED and GREEN keys select current
page + 1 and-1 respectively. This choice is taken according to the state offlag 3,STAT3 which reflects the condition
of the link control bit in packet 27. The code executed by RED, if links are not in use, is the same as that executed
by the" +" function (NPAGE) which always selects the next page. Similarly the alternative GREEN function
(PPAGE) is the same as for the "-" key. The YELLOW and BLUE keys do nothing under these circumstances. In
Spanish Teletext the GREEN, YELLOW and BLUE links can be individually inhibited, but the RED link is only
inhibited if all links are off.
The chapter associated with the selected page is displayed immediately if it has already been requested. This will
normally be the case if a linked page (red, green or yellow) has been selected. The code at label LPT is executed
if the page has already been requested. If not. a jump to CLRPD is performed. CLRPD is a label within DIGITO;
the code at CLRPD requests a new page just as if the page number had been entered manually. If the required
acquisition circuit is the one already current, then the "unstop" code is executed. This causes the green pagebeing-looked-for header to roll as though the page number had just been entered. This means that something can
be seen to happen in the case where the linked page differs only from the current page in its sub-page number.
Linked sub-pages are not fully supported in this implementation as they are rarely used by broadcasters and would
significantly increase the size of the software. When the chapter is changed the Teletext PBLF (page being looked
for) flag is checked. If it is low the FOUND flag is cleared. This forces the fetching of the links associated with
the new display page. If the page is not already in, this will automatically happen when it arrives so the FOUND
flag does not need to be cleared.
The BLUE (or cyan) key is different in that its page will not normally be immediately available (the four pages:
display, red, green and yellow occupy the four acquisition circuits and RAM chapters).
The INDEX (or black link) function is similar to BLUE except that if its link is not valid it defaults to the initial (index)
page number supplied by packet 8/30 (see sub-routine GIP).

6c, Subroutines:

LINK, GLP1, GLP2, SRCH, CHCK1 and NOTOKx

The sub-routine LINK allocates the three linked pages (RED, YELLOW and GREEN) to the three free acquisition
circuits (not in use by the display page). To do this it checks the page numbers in turn to see if they have already
been requested. If so they are left in their current acquisition circuit. If they have not already been requested the
page number is put into a LIFO. Only 0-9 are regarded as acceptable digits for page numbers; this is consistent
with the Spanish specification although the additional HEX numbers (A-F) may be used experimentally or by
Teletext page generators. Within this first loop the sub-routine GLP1 is used to get the linked page numbers from
packet 27, perform a decode of the Hamming encoded data and calculate the new magazine number (page
hundreds) if different from that of the display page. GLP1 uses sub-routine SRCH to check if the page has already
been requested. If there are no links, or if links are disabled, then displayed page + 1, +2 and +3 are requested.
The second loop in LINK allocates new page numbers to the remaining unused acquisition circuits. It uses GLP2
to clear the relevant chapters in the Teletext memory and make the new requests. Subroutine CHCK1 is used
to check whether or not an acquisition circuit is in use before it is loaded with a new page number from the LIFO.
This method of organising new page requests prevents unnecessary requests being made for pages already
requested. This is particularly important when links are disabled and pages are being requested using the "+"
or "-" functions. Under these circumstances when the page number is incremented (or decremented) only one
new page has to be requested (new display page+3)' while page, page+ 1 and page+2 do not need to change and
can be left in their current acquisition circuits.

30

NOTOK3 and NOTOK2 handle the RED and GREEN functions when links are disabled. They are disabled if the
link control bit (packet 27 bit 3, byte 43) is zero or if there is no packet 27. These subroutines respectively increment
and decrement the current page number (units and tens). The current magazine number (page hundreds) is
not affected.

6d. Subroutines:

ROW24. W2B. R2B. GCYI. CLINK and DECODE

ROW24 is used to transfer ghost row 20 (packet 24) into the display chapter. This has to be done via the IIC bus.
The loop reads two bytes via the IIC (sub-routine R2B) bus from the ghost page and writes it to the display page
(sub-routine W2B). The FOUND flag is then set to indicate that the arrival of the page has been recognised and
acted upon. This sub-routine is only called by the idle loop and is used along with the other sub-routines which
get information from the ghost page (CLINK, LINK and GET25).
R2B and W2B use IIC routines READ and SEND which are outwith the Teletext module. These subroutines will
differ according to the microprocessor in use. An MC68HC05C8 implementation would neet! to use I/O lines (see
reference for suitable software) while the MC68HC05T7 can use its IIC hardware. The routines used in this
example are included in the listing extract from the TV control software module (listing 1).
The sub-routine GCYI is used by LINK to store the data associated with the BLUE an INDEX links. As explained
above, these pages will not be acquired in advance, the page number only being sent to an acquisition circuit if
requested by an IR command.
CLINK fetches the link control byte from packet 27 if the destination code is OK and, after decoding the Hamming
encoded data, transfers the bits to STAT3.
The Hamming decode sub-routine DECODE corrects for single bit errors. This is done with in-line code using the
table HAM (at the end of listing 2) as this uses less ROM than an algorithmic method.

6e. Subroutines:

MIX. TRANx. TXTx. HOLD. and NOHOLD

The mixed display capability ofthe Teletext chip (5243) is toggled using an IR key which calls the sub-routine MIX.
When mixed mode is entered, interlaced broadcast sync. (312/313) is selected because the non-interlaced sync.
used for teletext is not suitable if a TV picture is present on the screen. This is set upvia the 5243 mode register R1.
The control registers R5 and R6 are updated to provide the mixed display.
When returning to a non-mixed display, the code at NOM IX is used to re-configure the control registers and to set
up a Teletext only 312/312 non-interlaced sync. This sync. reduces adjacent line flicker in a pure Teletext display.
The subroutine TRAN2 sets up a transient which retains a black background on the top row so that the page
number, time etc. can be seen clearly. This type of transient is also started if the page number or sub-page number
is being entered in mixed mode. Sub-routines TRAN 1, TRAN2 and TRAN3 are used to initialise the various
transient displays. These displays are cancelled as discussed above by actions taken within the idle loop controlled
by the free-running timer within the MC68HC05T7.
The TXTx sub-routines are used in conjunction with the IIC SEND routine to write to various sub-sets of the
registers within the 5243.
If the Teletext STOP function is requested by an IR command the routine HOLD is executed. This is a toggled
function when requested in this way. HOLD displays the word "STOP" in place of the page number and stops
the display acquisition circuit by clearing the 5243 HOLD flag accessed via its page request register R3.
NOHOLD is executed to restart the display acquisition circuit. It returns the page number to the top-left-hand
corner. If a new page number has been partially entered, a press of STOP (executing an UNHOLD) will allow a
return to the most recent page request. This takes only a single press as the start of the entry of a new page
number cause a HOLD. The completion of a page number entry (3 digits) causes a NOHOLD.

31

6f. Subroutines:

REVEAL. EXPTB and TIME

The REVEAL function causes any hidden display information to appear. It is controlled by a bit in the display mode
register (R71. The software example leaves any revealed information permanently displayed. If, however, it is
required that such information disappear when the page is updated (this may be better for a quiz pagel. then the
two commented out lines (80 and 81) in the idle loop should be enabled.
The display expand facility is controlled by another two bits in R7. The EXPTB sub-routine cycles through normal,
top-half double height and bottom-half double height.
The example application uses a single IR key (subroutine TIME) for both the display of the Teletext clock and the
entry into sub-page mode. IF the set is in TV mode then the time is displayed for 5 seconds. If the TV is in Text
mode then sub-page mode is selected. Sub-page number entry is described in the following section. When the
Teletext clock is requested it appears (boxed) at the top-right-hand corner. It is removed by the idle loop 5 seconds
after the last press of the time button. When the time is being displayed all other Teletext activity is stopped
using UCHOLD.

69, Subroutines:

DIGITS, SUBPG, GET25 and GET26

DIGITS is the sub-page version of DIGITO and uses similar code. More checks on the input data are required as
the four digits of the sub-page number have different maximum values. These maximums are 3 for thousands,
7 for the tens and 9 for the hundreds and units. These values reflect the sub-page number's original use as a time
(24hr formatl. For tens and thousands a keyed 8 becomes a 0 and a 9 becomes a 1 ; for thousands only 4, 5, 6
and 7 become 0, 1, 2 and 3 respectively.
The code at the label SETIT is the sub-page equivalent of GETIT, described above. It requests the new sub-page
and sets the FOUND flag.
The sub-routine SUBPG is called when the TIME (or clock) key is pressed (TV in Teletext model. It toggles
between normal mode and sub-page mode. When sub-page mode is entered the page number display (P-) is
replaced with * * * * to indicate the mode change and to prompt for the entry of a sub-page number. Once all four
digits have been entered the new sub-page is requested by SETIT. The code at the label RSTR is used to exit from
this mode back to the normal (page number) mode, restoring the page number display to the top-left-hand corner.
GET25 is used by the idle loop to get the information stored in row 25 of the display chapter. This row is not
displayed but contains various information used by the control microprocessor. The current page number,
magazine number, sub-page number, Teletext control bits and the FOUND and PBLF flags are available. GET25
gets the required information and stores it in the RAM of the MC68HC05T7.
At the end of this sub-routine the I/O line 7,portB is checked. If it is low, packet 26 is handled. If it is high, this
packet is disabled. This would be required if this application were to be used in a country other than Spain which
used packet 26. It would require to be switched off as the enhanced display feature uses different characters
depending on the country. In countries which do not use packet 26 (eg the UK) it does not matter whether or not
packet 26 is enabled.
If packet 26 is enabled, GET26 processes all packet 26 data present in the ghost page. The tables G2TAB, G3TAB
and CTAB contain the characters used to replace the character at the display location defined by each packet.

32

6h. Subroutines:

GIP, R24T and SR24T

The sub-routine GIP gets the initial (index) page from packet 8/30. It will be doing this as the set is brought
out of standby or just after a channel change. It may thus initially get a poor signal (or there may be no
Teletext) so it tries repeatedly until it finds a valid packet 8/30 format 1. If this is not found after 96 tries it
gives up and sets the flag 6,STAT2 to indicate that there is no packet 8/30 (or no Teletext). In this
circumstance it defaults to an index page number of 100.
R24T transfers bytes 10-30 ofthe broadcasting service data packet (8/30) into the display chapter. It is called once
a second for five seconds after power-on or a channel change. The data is transferred to row 0 of the display page
which can be displayed either at the bottom or, as in this example, the top of the screen. This transient display
is setup using the sub-routine SR24T ifTeletext is present. Ifthe flag 6,STAT2 has been set by GIP as described
above then SR24T does nothing. The transient display is terminated by code executed at the appropriate time
from within the idle loop.

7. INPUT AND OUTPUTS
Apart from the IIC bus, only three pins on the controlling microprocessor are relevant to Teletext. Two inputs
select the usage of packets 26 and 27 and one output can be used to control any hardware which requires to be
changed according to whether or not there is a iV picture currently being displayed. In many applications some
or all of these functions will not be required and could be eliminated from the software thus freeing up the pins
for other uses.

PB3)
This pin is active (high) during a pure (no-mixed, no-boxed) teletext display, otherwise it is low.

PB6)
When this pin is low, Spanish use of link control bits 1, 2 and 3 is enabled. When it is high, these bits are ignored.

PB7)
Packet 26 control. When low, packet 26 is enabled and handles all the Spanish alternate characters which are
available in the 5243. When PB7 is high, packet 26 is ignored.

8. REFERENCES
Application note AN446, MCM2814 Gang-programmer using an MC68HC05B6.

33

LISTING 1
30

31
32
33
3.
3S
36 00000000

Idle loop.

Od13fd

ILP

37 00000003 >3eOO
38 00000005 >3eOO
39 00000007 >3eOO

INC
INC
INC
JSR

40 00000009 >cdOOOO
41 OOOOOOOc 030104

BRCLR
BSET

42 DCOODCOf :>1600

43
44
45
46
47
48

00000011
00000013
00000016
00000018
0000001&
0000001c

ZOS!
>070009
>1700
>1500
>lfOD
>cdOOOO

49 DOOOOD1! >cdOOOO

50
51
52
53

00000022
00000025
00000028
0000002b

B....
FaN

BCLR
BCLR
JSR

ALRON

54 0000002e >0.0041

55 00000031 >06D03e
56 00000034 >Oc003b
57 00000037 >Of0005

0000003a
0000003c
DOOOOO3f
00000042

>HOD
>cdOOOO
>01001e
>bEiDa

62
63
64
65
66
67

00000044
00000046
00000048
0000004b
0000004e
00000051

a130
252a
>cdOOOO
>cdOOOO
>cdOOOO
>cdOOOO

NOUP
N024

LOA

81
00000070
00000072
00000075
0000007'

>3fOO
>04008b
>060088
>090085

BU)
JSR
JSR
JSR
JSR
BRCLR
BRCLR
BSR
BCLR
LOA
STA
LOA
STA

80
82
83
84
85
86
87
88

BRCLR
LOA
CMP

adEie

71 0000005c >1100
72 OOOOOOSe >bEiDa
73 00000060 >b700
74 00000062
a60.
75 00000064 >b700
76 00000066 a619
77 0000006. >edOOOO
7' 0000006b >010104
79 0000006e >1000

JSR
BRSET
BRSET
BRSET
BRSET
BRSET
BRSET
BRSET
BRCLR
BCLR
JSR

DNTRS

68 00000054 >090005
69 00000057 >ObOOOZ
70 0000005a

BRCLR
BCLR

>02004d
>02004&
>Oe0047
>040044

58
59
60
61

BRCLR

F1

..

OUTPUT COMPARE FLAG
TELETEXT TRANSIENT
P!OW 24 DElAY
MUTE TRANSIENT
KEYBOARD' TIMERS
STANDBY 'I
MAKE SURE FLAG AGREES
AND IDLE WITH NO lIC ACTIVITY
NO, JUST ON '1
YES, RESTART
CLEAR THIS FLAG ALSO '1
RE-INITIALISATION NOT NECESSARY

6,TSR, "
CNTl
CNT4
CNT5
KBD

l, PORTS, FaN
3,STAT2
Fl
3, STAT2,ALRON
3,STAT2
2,STAT2
7,STATS
RESTRT
VCRPOLL
l,STAT2,Fl
l,STAT4,Fl
6,STAT7,Fl
2,STAT2,Fl
S,STAT,Fl
3,STAT4,Fl
6,STAT4, Fl
7,STAT5,DNTRS
7,STAT5
START2
0,STAT2,N024
CNT4

POLL SCART LINES
REMOTE REPEATING 'I
LOCAL REPEATING ?
TELETEXT CHIP ON BUS 'I
SEARCH/STANDBY '1
TIME DISPLAY HOLD
TRANSIENT MUTE?
COINCIDENCE MUTE 'I
TO BE RE-ITIALISED ?
YES, CLEAR FLAG ,
RE-INITIALISE TELETEXT
PAUSE WHILE PACKET 24
(PAGE EXT.) ARRIVES

•••

Fl
CLINK
LINK
ROW24
GET2S
4, STAT2, NOUP
5,STAT2,NOUP

CHECK LINK CONTROL BYTE
FETCH LINKS
FETCH ROW 24 AND SET FOUNDB
GET ROW 2S , PACKET 26
UPDATE ENABLED 'I
DIFFERENCES 'I

ARRVD
0,STAT2
ACC

R'ta

COLUMN 8

(FOUNDB , PBLF)

R10

ROW

JSR

'2S
R2B

BRSET
8SET
BCLR

4, IOBUF+l,Fl
0, STAT2
5,R7

FOUNDB FLAG SET ?
NO, SO FETCH GHOST ROWS
KILL REVEAL

JSR
CLR

TXT2

BRSET
BRSET
BRCLR

CNT4
2, STAT2, ILP
3, STAT2, ILP
4,STAT,ILP

SEARCHING?
STANDBY?
TRANSIENT?

Transient control .

90

"92

93
94
95
96
97
98
99
00
01
02
03
04
05
06
07
08
09

0000007b
0000007d
0000007!
00000081
00000014
00000086
00000088
aOOOOO8a
aOOOOOld
0000008!
0000009::'
00000093

>b600
alSO
2403
>eeOOOO
>b600
a104
2603
>edOOOO
>3f00
>3aOO
2703
>ccOOOO

0000e096 >cdOOOO
00000099 >ccOOOO

NILP

NOTE

ONILP

LOA
CMP
BNS
JMP
LOA
CMP
BNE
JSR
eLR
DEC
BEO
JMP
JSR
JMP

CNTl

YES

taO
NILP

..

ILP

IS TIMER

R.

NOTE
R24T
CNTl
ONILP

IF PAGE 4 THEN IT'S
THE 8/30 TRANSIENT
CLEAR IS TIMER
DECREMENT SECONDS COUNTER
TRANSIENT FINISHED ?

ILP

NO

OSDLE

OSO TIMEOUT (INC RSTMD)

TMR

ILP

:0

End Teletext transients.
:2

Clear mode bits (channel mode>, 2-diqit
proq. no. entry etc.)

:J
:4

:s
:6
17
18
19
20
2:
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37

0000009c >010003
a000009! >edOOOO
000000a2 >1500

RSTMD
SOS2

000000a4
000000a6
000000a8
OOOOOOab
OOOOOOad
aaOOOOa!
OOOOOObl
000000b3
000000b6
OOOOOOb9
OOOOOObc
OOOOOObe
000000e1
000000e3
000000e5
000000e7

RSTMD2
RSTMD3

>1900
>1900
>Ob0011
>lbOO
a603
>b700
>b700
>cdOOOO
>040003
>cdOOOO
>1100
>000006
>b600
>b700
>3!00
>ecOOOO

BRCLR

0, STAT5, SOS2

JSR

RES

BCLR

2,STAT4

BCLR

4,STAT4
4,STAT
5,STAT,TXTR1
5,STAT
1$03

BCLR
BRCLR
BCLR
LOA
STA
STA
JSR

BRSET
JSR

TXTRl

TXTR2

BCLR
BRsET
LOA
STA
CLR
JMP

2-0IGIT Pr. No. ENTRY ?
YES, RESTORE DISP
MAKE SURE ITS PROGRAM MODE
RESET OSD TRANSIENT FLAG
RESET MAIN TRANsIENT FLAG
TIME HOLD?
YES, CLEAR IT

RS
R6

TXT2
2, STAT, TXTRl
NOTTH
O,R7
0, STAT, TXTR2
ACe

STOP TIME EXIT FLASH
OTHER HOLD?
NO, SO CLEAR HOLD

BOX OFF ROW 0
TELETEXT 'I

R'
R7

NO, ALL BOXES OFF

TXT2

YES

34

139
140
141
,.2

• • ft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

..

.................................. _-_ ............... _-- ...

,,.3

'

145 OOOOOOca >b600

146
147
148
149
150
lSI
152
153
154
lSS

OOOOOOcc
ODOOOOce
ODOOOOdO
OOOOOOd2
DCOODOd3
DCOODOd6
DeOODOd9
OOOOOOdb
DCOODOde
OOOOOOeO

156
157
158
159
160

000000.2 >b700
000000e4 a603
000000e6 >050002
aCOOOOd a602
OOOOOOeb >b700

>b700
>1900
>lbOO

"".VD

4!
>cdOODO
>OcDOOS

a606
>cdOOOO
a646

'"

ODOOOOfO
000000f2
000000f4
oooooon
oooooon
OOOOOOfa
OOQOOOfc

SPHD

>biOO

a610
>b700
aEi06
>b'OO
>b'OO
>3fOO
>edOOOO

NNF

RESTRT

OOOOOOff 013e03
00000102 >1cOO
00000104 81

CLM
JS'
BRSET
LDA
JS,
LDA
ST.
ST.
LDA
BRCLR
LOA
STA
JMP
LDA
STA
LD'
STA
STA
CL'
JS.

BRCLR
BSET

ACC

••

4.5r.... T

KILL TRANSIENTS

5.Sr....r

..
..••

BOXOOR

6, STAT. SPHD

SUB-PAGE MODE 1
NO, SHALL BOX

BOXOOF

1$46

1$03
2.C3,NNF
1$02

NEWSf'LASH ?
YES, NO ROW 0

.7
TXTZ

.,
••
••

1$10

BROADCAST SYNC.

.5

.7
TXT2

SWITCH PICTURE ON

O,MSR,ACI(OK
6,STAT7

ACKNOWLEDGE ?
NO, SET FLAG

'TS

00000105 >ceOOOO

ACKOK

JMP

INITXT

00000108 >b600
0000010a >b700
0000010e >1100
0000010e 81

'ES

LOA
STA

PROG
DISP
0, STATS

ABS

'TS

BCLR

YES, RESTORE PROG. HO.

•••••••• * ••• * •••••••••••••••••••••••••• **.* •••••••• *.* ••
IlC write.

.*.* •••• * ••••••••• * ••••• ****.* •• * •••• *.* •• *.* •••••• *.* ••
OOOOOlOf

ad23

1512
1513
194
195

00000111 >bfOO
00000113 >1100
00000115 >h600
0000011' ad2S

1517
198
1519
200
201
202
203
204
205
206
207
208
209
210
211
212
213
21'
215
216
217
218
219
220
221
222
223
224
225
226
227
228
22.

00000119 >bEiOO
00OOOl1b a180
0000Ol1d 2606
0000011f >b600
00000121 ad1b
00000123 >3cOO

,..

LDA
STA
BCLR

BCLR

Hi1 OOOOOOed >ccOOOO

,.2
,.3
164
165
1EiEi
lEi'
168
169
170
171
172
173
1'4
175
176
177
178
179
180
181
182
183
18'
185
18.
187
188
18.
,.0

1O.

Updated page hall arrived.

SEND

BS.

IlCSU

STX

DPNT
O,APDR

BCLR

lORBU

LOA
BS'

ADO.

LO'
CMP
BHE
LOA
BS'
INC

ADO.

00000125 >beOO
00000127
00000128 ad14
0000012a >3cOO
0000012c >3aOO
0000012e 26e9

LOX
LOA
BS'
INC
DEC
eNE

00000130
00000132
00000133

BCLR

f.

..

1b3b

SEND CHIP ADDRESS
STEREOTONE ?

1$80
lORB

SUBADR
SHIFT
SUBADR

YES, SO ENABLE AUTO
SUB-ADDRESS INCREMENTING

DPNT

DATA BUFFER POINTER

O,X

SHIFT
DPNT
W1

SEND DATA

WRBU

DONE?

S,MCR

STOP

HS'
FO'

IIC SET-UP
90 I(Hz
ENABLE lIC AS MASTER
TRANSMITTER & START

CLI
'TS

81

,b

SAVE X
SET-UP TO WRITE

SHIFT

00000134
00000135
0000013'
00000139
0000013b
0000013d

3f3c
3f3a
a6bO
b73b
8'

0000013e
00000140
00000143

b13d
Of3efd
81

SHIFT

00000144 adc9
00000146 a602
00000148 >cdOOOO

WRITE

IICSU

SEI
CLR
CLR
LOA
STA
.TS
STA

BRCLR

t$BO
HC'

HO'

7,HSR,

*

'TS
es.
LOA
JS,

SEND
'2
TPAU

WAIT lOms

35

(EEPROM WRITE)

no
23.
232
233
234
235
236
231
238
239
240
241
242
243
244
245
246
24.
248
249
250
251
2S2
253
254
255
256
257

IIC read.

0000014b
OOOOOHd
OOOOOH!
00000151
00000153
00000155
00000157

adOc
>b600
>b701
>b600
ala!
2602
>3cOO

00000159 add9
0000015b >1100
0000015d >b600
DDOOOIS! acl.cl.d
00000161 >b600
00000163 add9
00000165 1b3b

la3b
00000169 >1000
0000016b >b600
0000016d adc!
0000016! 193b
00000171
l63b
258 000001.3
b63d
25.
260
26'
262
263
264
265 00000175 Of3cfd
266 00000178 1b3b
267 0000017a b63d
268 0000017c >b700
269 0000017e 9a
270 OOOOOl7t 81
27.
272
273
274
275
276
277
278 00000180 3f3c
279 00000182 80

READ

READ'

BSR
LOA
STA
LDA
CMP
BNE
INC
BSR
BeLR
LDA
BSR
LDA
BSR

BeLR

00000167

BSET
BSET
LOA
BSR
BCLR

READ1
IOBUF
IOBUF+l
ADDR

#SAl

1M! ,

READ'

SUBADR
IICSU
O,ADDR

YES, NEXT SUB-ADDRESS
RII' -

SHIFT
SUBADR
SHIFT
S,MeR
S,MCR
O,ADDR

SEND SUB-ADDRESS
NO STOP BUT
A RESTART
SET BIT 0 FOR READ

ADDR

BSET
LOA

MDR

BRCLR
BSET

7,MSR,*
3,MCR

LOA
STA

MDR

CLR
RTl

t SUB-ADDRESS)

SEND CHIP-ADDRESS

IOBUF+l
7,MSR, *
5,MeR
MDR

IOBUF

RE-SEND CHIP ADDRESS
CHANGE TO RECEIVER
SWITCH OFF ACtc.
INITIATE RECEPTION
WAIT FOR IT
SECOND LAST SO SWITCH OFF ACtc.
GET FIRST BYTE
AND SAVE IT
NAIT FOR IT
LAST BYTE SO STOP
GET BYTE
AND SAVE IT

!IC interrupt.

MBINT
RETURN

0 ALWAYS WRITE

ADDR

SHIFT
4.MCR
3,MeR

BRCLR
BeLR
LDA
STA
CLI
RTS

GET FIRST BYTE
MOVE IT UP

MSR

36

LISTING 2
1

2
3

TV/Te!etext/OSD/Stereo program (MC68HCOST7).

•,

CCT Teletext control module (Spain).

•
••

Used with RANTa.50S, OST.50S ,

7

TMT7.505

'" This software vas developed by Motorola Ltd. for demonstration purposes.
'"

10

11
12

No liability can be accepted for its use in any specific application.
original software copyright Motorola - all rights reserved.

P. Topping

13
14
15

16
17

19th October' 90

,.

EXPORT
EXPORT
EXPORT

TIME, MIX, INDEX, HOLD. SR24T, START2, INITXT

21
22

EXPORT
EXPORT

CLINK, LINK, ROW24, GET2S, R2B, TXT2
R24 T, NOTTH, BOXOON, BOXOOF

IMPORT

SEND, READ, OSDLE, TPAU2

LIB

HAMT8.S0S

18

DIGITO,RED,GREEN, YELLOW, CYAN
NPAGE. PPAGE,REVEAL, EXPTB, UPDATE, TVTX, GIP

20

23

2.
2'

2'
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27

RAM allocation for OST.SOS,

Equates.

00000000
00000001
00000002
00000003
00000004
00000005
00000007
00000008
00000009
OOOOOOOa
OOOOOOOb
OOOOOOOc
OOOOOOOd
OOOOOOOe

00000012
00000013
00000014
00000015
00000016
00000017
00000018
00000019
0000001c
00000020
00000032

27 00000033

27
27
27
27

TXT7.S0S.

SECTION.S .RAM,COMM

27 00000006

27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27

TMT7.S0S ,

00000034
00000035
00000036
00000037

27
21 00000039
27 0000003a
27 Q000003b
27 0000003c

27 0000003d
27
27 0000003e

27 aOOOOD3!

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

$00
$01
$02
$03
$04
$05
$0'
$07

Port
Port
Port
Port
Port
Port
Port
Port

EQU
EQU
EQU

$08
$0'
$"

0/ A 0

LE03
"VOLU
CONT
BRILL
SATU
VOLU

EQU
EQU
EQU
EQU
EQU

$"
$08
sOC
$00
$OE

O/A 2
O/A 3
O/A 4

TCR
TSR

TDRH
TORL
MISC

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

$12
$13
$14
$15
$1'
$17
$18

".
$lC

Timer control register.
Timer status register.
Input capture register, high.
Input capture register, low.
Output compare register, high.
Output compare register. low.
Timer data register, high.
Timer data register, low.
Misc. register

OSD
CAS
C34
RAD
WCR
CCR
HPD

EQU
EQU
EQU
EQU
EQU
EQU
EQU

$20
$32
$33
$34
$35
$3'
$37

IB OSO data registers
Color' status register
Color 3/4 register
Row address' character size
Window/Column register
Column/color register
Horizontal position delay

MADR
FOR
MCR
MSR
MDR

EQ"
EQ"
EQU
EQ"
EQ"

$3.
$3A
$38
$3C
$30

TRl
TR2

EQU
EQU

$3E
$3F

PORTA
PORTB
PORTC
PORTD
DORA

DORB
DORC
OORD
LED1
LED2

ICRH
ICRL
OCRH
OCRL

O/A 1
D/A 2

0/11. S

A address
B
..
C
D
A data direction reg.
B"
..
..
C
D
STEREO LED
BILINGUAL LED
FM -1- NICAH LED
JPOB IN T1 EVB
JP09 IN T1 EVB
JPIO IN Tl EVB
JPll IN Tl EVB

O/A 6

Test 1, OSO/Timer/PLM
Test 2, EPROM

37

27
27
27

Teletext RAM allocation.

27
27
27
27 00000000

2700000001
2700000002
27 00000003

27 00000004
27 00000005
27 00000006

27 00000007
2700000008
27 00000009
27 DOOOOOOa
27 QOOOOOOb
27 OOOOOOOc

27 DOOOOOOd
27 QOOOOOOe

27 aCOODCOf
2700a00010
27 00000011
2700000012
2700000013
2700000014
27 00000015
27 00000016
2700000017
2700000020

2700000027
270Q00002a

27 D000002d
2700000030
2700000033
27 00000036

2700000039
27

DOOOD03a

27 D000003e
27 OOOOOO)!

2700000040
27000000-41
2700000042
27 00000046
27
27
27
27

SUB1
Rl
R2
R3
Cl
C2
c3
C4
C5
C6
SUB2
R4
R5
R6
R7
SUB3
R'
R'
RIO
Rll
PH
PT
PU
LIFO
PAGE
PAGO
PAGl
PAG2
PAG3
PAGC
PAGI
PDP
ACC
WACC
ADDR
DPNT
SUBADR
IOBUF
STAT2

RMB
mode register
page request address register
pilge req. data reg. col. 0 : mag.
..
..
....
1
pqt.
2
pqu.
3
ht.
4
hu.
S
mt.
6

RMB

RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB

display
display
display
display

RMB

RMB
RMB

RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB

active
active
active
active
2nd
3,d

chapter register
row register
column register
data register
..
..

4th

RMB

RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB

27
STAT3

(normal)
(news/sub)

LINKED PAGE No. LIFO BVFFER
PAGE No. INPUT BUFFER
ACO PAGE No.
ACl PAGE No.
AC2 PAGE No.
AC) PAGE No.
CYAN PAGE No.
INDEX PAGE No.
PAGE DIGIT POINTER
DISP, RED, GREEN, YELLOW AC. CIR.
WORKING ACC No.
lIC ADDRESS
lIC DATA POINTER FOR WRITE
IIC SUB-ADDRESS
IIC BUFFER, +2 , +3 RSRVD FOR PLL
0: ROW24 FETCH FLAG
1: REMOTE REPEATING
2: SEARCH/STANDBY IIC LOCK
3: STANDBY STATUS
4: UPDATE PENDING
5: DIFFERENCE FOUND
6: NO TELETEXT TRANSMISSION
7: MIXED

RMB
RMB

27

27
27
27 00000047

chapter register
control register
control register
mode register

RMB

0: CYAN
LINK ON
1: YELLOW LINK ON
2: GREEN LINK ON
3: LINKS/ROW24 ON

27

27
27
27
27
27

27
27
27

General RAM. allocation.

27

2700000048
27 00000049

PLLHI
PLLOW
WI

RMB
RMB
RMB

27 0000004b

W2

RMB

27 0000004c
27 OQOOQ04d

W3
COUNT
KOUNT
CNT
CNT!
eN!J
CNT4
CNTS

RMB
RMB
RMB
RMB
RMB
RMB
RM.B
RHB

27 00000054

TMR

RMB

2700000055
27
27

STAT

RHB

STAT4

RMB

PWR
PROG
CHAN
DISP
DISC
FTUNE
AVOL
BRIL

RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB

27

OOOQ004a

27 D000004e
27 QOOOOOH
27 00000050

27 00000051
27 00000052
27 00000053

PLL DIVIDE RATIO MSB
PLL DIVIDE RATIO LSB
WORKING
LOOP COUNTER
LOCAL KEYBOARD COUNTER
12.8mS (inc, free running)
12.8mS (inc, reset every IS during transient)
3.2S S (dec, automatic standby timeout)
12.8mS (cleared for row24 delay when page arrives)
12.8mS (inc, transient mute)
TRANSIENT DISPLAY SECONDS COUNTER
0: TV/TELETEXT
1: lIC R/W
2: HOLD
3: IR REPEAT INHIBIT
4: TRANSIENT DISPLAY ON
5: TIME HOLD
6: SUB-PAGE MODE
7: IR TASK PENDING
0: KEY FUNCTION PERFORMED
1: LOCAL REPEATING
2: pIc PROG
0, CHAN
3: MUTE (TRANSIENT)
4: OSD STATUS TRANSIENT
5: MUTE (BUTTON}
6: COINCIDENCE MUTE
7: SEARCH
$55 AT RESET, $AA NORMALLY
CURRENT PROGRAM NUMBER
CURRENT CHANNEL NUMBER
CURRENT DISPLAY NUMBER (PROGRAM)
CURRENT DISPLAY NUMBER (CHANNEL}
FINE TUNING REGISTER
VOLUME LEVEL
BRILLIANCE LEVEL
CODE OF PRESSED KEY (LOCAL)
LED DISPLAY RAM
IR INTERRUPT TEMP.

27

27
27

27
27

2700000056
27
27
27
27
27
27
27
27 00000057

2700000058
27 00000059
270000005a
27 OOOOOOSb
27 DOOOOOSc
27 OOOOOOSd
27 OOOOOOSe
27 OOOOOOSf
27
27 00000060
2700000061
2700000062
27 00000063
27 00000064
27 00000065
27 00000066
2700000067
27 00000068
27 00000069
27 0000006.1
27 0000006b

KEY

-NUMO
IRRAl
IRRA2
IRRA3
IRRA4
DIFFH
DIFFL
IRH
IRL
IRCODE
IRCNT
IRCMCT
OLOIR

"

RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB

"

"

IR TIME DIFFERENCE

"

"

IR CODE BIT
COLLECTION

38

"

27
27
27
27
27
27

RAM allocation for Stereoton.

27 0000006c

LBAL

RMB

27 0000006e

SHDKD

RKB

27
27
27
27
27
21
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27

0000006!

ABAV

RMB

00000070
00000071
00000072
00000073
00000014
00000075
00000076
00000077

..
LVL
LYO
HVL
HYO

RMB
RMB
RMB
RMB
RMB

TONE

RMB

RMB

'2

RMB

00000078

STATS

RMB

0:
1:
2:
3:
4:
5:
6:
7:

00000079

STAT6

RMB

0: AV MODE BIT a (O:TV. l:S-VHS)
1: AV MODE BIT 1 (2:SCRTl. 3:SCADT2)
2,
3,

.,

6: SCART INPUT f l
7: SCART INPUT '2

27 OOOOOOic
27 aOOOOOid

27 0000007.
27 DOOOOD?!

00000080
00000081
00000082
D0000083
00000084
00000085
00000086
00000087

27 00000088
27 00000089
27 OOOaDala

27 0000008b
27 aOOOOOle
27 ooaOOD8d
27 0000008e

~7

2-DIGIT PROGRAM ENTRY
ANY MUTE REQUIRED ?
OSD NAME TABLE
OSD DEFAULT pIc NUMBER
ANALOGUE eso ON
NAME-TABLE STANDARD
STANDARD CHANGED
RE-INITIALISE TE(.ETEXT

e,

27
27
27
27
27
27
27
27
27
27
27
27
27
27
27 0000001b

2?
27
21
27
27
21
27
27
27
27

Kl level
Loudspeaker left volume
Loudspeaker right volume
Headphone volume left
Headphone volume right
Tone variable (Bass/Treble)
Current m.atrix
K2 level

MATRIX

27 DOOaOOia

27
27
27
27
27
27
27
27

TEMPORARY MATRIX
Loudspeaker balance variable
SOUND MODE O:ST, l:DA, 2:DB, 3:w, 4:M. 5:FM
SCART SOUND MODE O:STER.EO. l:DlJAL ..... 2:DU.... L B

SHADMAT RMB

27 a000006d

ooooooa!
00000090
00000091
00000092

00000093
00000094
00000095
00000096
00000097
00000098

27
27 00000099
27 OOOaOaga

27
27 0000009b
27 0000009c

ST....T7

RMB

0: AV MODE CHANGE

1:
2:
.3:
4:
5:
6:
7:

FORCE FM SOUND
CS : TELETEXT NEWSFLASH
C6 : TELETEXT SUBTITLES
LANGUAGE .... /B (TV)
WIDE-PSEUDO
NO TELETEXT ....CKNOWLEDGE
POWER UP IN STANDBY

OSD RAH allocation.

RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB

ROW 1, colour 1/2 , outline enable
Row address , character size
Window colour , end column
ROW 2, colour 1/2 , outline enable
Row address' character size
Window colour, end column
ROW 3, colour 1/2 , outline enable
Row address' character size
Window colour, end column
ROW 4, colour 1/2 , outline enable
Row address' character size
window colour, end column
ROW 5, colour 1/2 , outline enable
Row address' character size
Window colour , end column
ROW 6, colour 1/2 , outline enable
Row address' character size
window colour , end column
ROW 7, colour 1/2 , outline enable
Row address' character size
Window colour' end column
ROW I, colour 1/2 , outline enable
Row address' character size
Window colour, end column

ROWl

RMB
RMB
RMB
RMB
RMB
RMB

CURRENT OSD ROW POINTER
ROW TABLE INDEX
CHARACTER FLASH ROW
CHAr ....CTER FLASH COLUMNS
WINDOW FLASH ROW
FIRST ROW No. (NAME TABLE)

ANAL
ANAF

RMB
RMB

CAS1
>AD1
CCRl
CAS2
>AD2
CCR2
C....S3
RAIl3
CCR3

c....se

RAIle

CCRe
CAS.
>AD'
CCR5
CAS.

RAD.

CCR6
CAS 7
RAD7
CCR7
C....SI
RAD'
CCRa
'oSDL
LIND
BROW
BCOL
WROW

TMP1
TMP2

RMB

27
27 OOOOOQ9d

27
27 000000&9
27 OOOOOObf
27
27
27 00000000

2.

29

ST....CK
SP
DRAM

RMB

12

UNUSED

RMB
RMB

22
1

2.3 BYTES USED FOR ST....CK
(l INTERRUPT AND 9 NESTED SUBS)

SECTION .RAH2, COHM
RMB
12.
SECTION .ROH2

39

(req 0)

(req 1)
(req 2)
(reg .3)
(req 4)
(reg 5)
(req 6)
(req 7)

..........................................................
.......................................,. ...................

31

32
33
3.
3'
3.
31
38
39
40
41
42
43

Teletext/TV .witchinq.

00000000
00000003
00000006
00000001
DODODOOb
OOOOOOOd
DeOODCO!

>000037
>OcOO74
>1000
>cdOOOO
.. 616
>blOD
>1900

TVTX
TXTON

44 00000011 >1900
45 00000013 >1fOO
46 00000015 >Obooas
47 00000011 >lbOO
48 000000101 >040003

BRCLR

49 DDODOOld >cdOOOD

SO 00000020

aicc

NOTT

Sl 00000022 >b70C
52 00000024 4646
53
54
55
56

00000026
00000028
0000002a
0000002c

>b700
>b600
>b700
>ccOOOO

58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75

OOOOOOH
00000032
00000034
00000037
0000003a
0000003e
0000003!
0000004.1
00000043
00000045
00000047
00000049
0000004b
0000004d
OOOOOOH
00000051
00000054
00000056

>OcOO48
>1800
>090003
>edOOOO
>1100
>cdOOOO
>1100
a610
>b700

78
79
80
81
82
83
84
8S
86
"
88
89
90
91
92
93
94
95

00000059
0000005b
OOOOOOSd
OOOOOOS!
00000061
00000063
00000065
00000067
00000069
0000006b
0000006d
0000006!
00000011
00000013
00000075
000000"17
00000079
0000007.
0000007))

"

7'
77

UPDATE

TXTorF
TXTOF

>1900
>lbOO
a603
>b700
>b700
>3f00
>cdOOOO
a602
>ccOOOO
>e602
a139
221b
a130
2517

.sr

TEST

>8601
a139
2211
a130
nOd
>e600
a137
2207
a130
2503
>b700
81

••
81

BRIET
BRSEl'
aSET
JS'
LDA
srA
BCLR
BeLR
BeLR

ABO
PANIC

BCLR
BRSET
Jsa
LDA
STA
LDA
srA
LOA
srA
JMP

BRSET

as..

BaCLR
JS'
BeLR

os.

BeLR
LDA
srA
BCLR
BeLR
LOA
SrA
srA
CLR
JS'
LDA
JMP
LOA
CMP
BHI
CMP
BLO
LOA
CMP
BHI
CMP
BLO
LDA
CMP
BHI
CMP
aLO
SrA

.ra

SEC
.rs

O. STAT, TXTOFF
6. STAT7, PANIC
0, STAT
OSDLE

"16

Rl

4, STAT
4,5T"12
7,STAT2
5, STAT, NOTT

TELETEXT CHIP ON BUS 1

TELETEXT MODE
CCT, 312/312 SYlfe
ENABLING GHOST ROWS
ABORT TRANSIENTS
KILL UPDATBS
NOT MIXED

5,IT"T
2, STAT. NOTT
NOTTR

uce

.S

1$46
R.
ACC

••

rlWl'

6, STAT7, PANIC
4,STAT2
4, STAT, TXTOFF
NOTTH
0, STAT
OSDLE
O.STAT
1$10

.1
4.ST"T
5, STAT
t$03

.,
.,••

TELETEXT CHIP 1
UPDATE ON
TRANSIENT HOLD 1
YES, RESTART
TV MODE
TV HODE

BROADCAST, 3121313 SYNC
ENABLING GHOST ROlfS
1dSORT TRANSIENTS
1dSORT TIME TIMEOUT
$06 FOR TRANSIENTS

TXT2

t2
SPM

PAGO+2.X
t$39
PANIC
t$30
PANIC
PAGO+l,X
ta39
PANIC
#$30
PANIC
PAGO,X
#$37
PANIC
t$30
PANIC
PAGE
OK, CARRY CLEAR
NOT OK. CARRY SET

40

97
90
99
100
101
102
104
105
106
107
108
109
110
111

Number entry routine!!.

ooa0007c
0000007f
00000082
00000084
00000086
00000089
0000008b
0000008e
00000090

112 00000092

>OdOOO)

>ccoaaa

DIGITO

>1700
>b600
>cdOOOO
aG04
>cdOOOO
>1400
>b600

6, STAT, DIGIT
DIGITS
3,R3
ACC
UP
f4
8SET
LOA

.,

2, STAT

tl6

a010

113 00000094 >beOO

HOLD DURING

LOO

114

00000096

2606

BNE

NOCH

NOT HUNDREDS SO DON'T CHANGE

115
116
117
118

00000098
0000009a

al07
2302
a008
ab30

CMP
BLS

NOCH

"to

YES, MORE THAN 7 ?
NO, SO DON'T CHANGE
YES, 8->0 , 9->1
CONVERT TO ASCI I

OOODOQ9c

000000ge

119 OOOOOOaO >e700
120 000000a2
a302
121 000000a4
270e

STA
CPX
BEQ
LOA

122 000000a6
123 000000a8

a62d
a301

124

2702

BEQ

125 OOOOOOac >b70l

STA

OOOOOOaa

LOA
STA
LOA

PAGE+1
PAGE+2
POP
DPGN
PDP
R4
RO
R9
t2
Rl0
'$50

LDA
STA
LDA
STA
LDA
STA
JSR
JSR
LDA

PAGE
PH
PAGE+l
PT
PAGE+2
PU
TXT38
TRANI
PDP

126 OOOOOOae >b70Z

>3eDa
2002
>3fOO
>b600
>b70Q
>3fOO
a602
>b700

127
128
129
130
131
132
133
134

OOOOOObO
OOOOOOb2
OOOOOOb4
OOOOOOb6
OOOOOOb8
OOOOOOba
OOOOOObc
ODQDOObe

135
136
137
138

OOOOOOcO
a650
OOOOOOc2 >h7QQ
OOOOOOc4 >b600
OOOOOOc6 >b7QO

DPGN

OOOOOOce
OOOOOOdO
000000d3
000000d6
OOOOOOdS
OOOOOOda
OOOOOOdc
OOOOOOdf
OOOOOOel

CLR
LOA
STA

UNITS
YES, SO CLEAR PDP
DASH
TENS 1
YES, SO LEAVE TENS
CLEAR TENS

ROW 0

COLUMN 2

R11

139 OOOOOOc8 >b601
140 aoaaGQca >b700
ODOOOOcc >b602

141
142
143
144
145
146
147
148
149
150
151
152
153

'$30
PAGE,X
f2
CLRPD
'$20
tl

>b700
>edOOOO
>edOOOO
>b600
269f
a606
>edOOOO
>b600
>b700

ABO

"
STA

154

PH

Get requested page.

155

156
157
158 000000e3
159 000000e6
160 000000e8
161 OOOOOOea
162 OOOOOOee
163 OOOOOOee
164 OOOOOOfO
165 000000f2
166 000000f4
167 000000f6
168 000000f8
169 OOOOOOfa
170 OOOOOOfe
171 OOOOOOfe
172 00000100
173 00000102
174 00000105
17500000108
176 0000010a
177

>edOOOO
2545
ad23
>b600
>e700
>b601
>e701
>b700
>b602
>e702
>b700
>b600
a018
>b700
>b600
>edOOOO
>cdOOOO
>1500
>ccOOOO

1"
179
OOOOOlOd >b600
190 OOOOOlOf
48
181 00000110 >bbOO
182 00000112
97
183 00000113
81
184
18500000114
48
186 00000115
48
187 00000116
48
18800000117
48
189 00000118 >b700
190 OOOOOlla
81

GETIT
BLO
BSR
STA
LOA
STA
STA
STA
STA
LDA
SUB
LOA
JSR

BCLR
JMP

SRCH
LPT2
PAGE
PAGO, X
PAGE+:
PAC,O+l,X
Cl
PAGE+2
PAGO+2,X
C2
PAGE
f$18
R3
R4
UP
TXT1
2, STAT
SFND

IS PAGE ALREADY eN ?
YES
DISPLAY CHAPTER
PAGE HUNDREDS
SAVE lN RAM
PAGE TENS
SAVE IN RAM
PAGE REQUEST TENS
PAGE UNITS
SAVE IN RAM
PAGE REQUEST UNITS
PAGE HUNDREDS

PAGE REQ:JEST HUNDRE:::S

REQUEST IT
RESET HOl..D fLAG
WRITE ONE TO fOt:N8

x2
x3

LSLA
LSLA
LSLA
R2

41

"2
"3
,.,
,.5

Red,

Green' Yellow keys.

19'

,'7
198

0000011'0 >3fOO

199 DOODalld >06000b
200
201 00000120 >cdOOOO
202 00000123 >cdOOOO
203 00000126

RED

CLR
BRSET

PDP
J, STAT3, RED2

NPAGE

JSR
JSR

BLO
JMP
LDA
BRA

INDXP
NOTOKJ
LPT
CLRPD
ACC+l
LPT

252c

204 00000128 >ccOOOO

205 0000012b >b601
206 0000012d 2025

RED2
LPT2

207
208 OOOOOI2! >3fOO
209 00000131 >06000b

GREEN

CLR
BRSET

PDP
J, STAT3, GLOK

PPAGE

JSR
JSR

INDXP
NOTOK2
LPT
CLRPD
6.PORTB. IGO
O.STAT3.ABC
ACC+2

LINKS ON '}
NO, SO FORCE AN INCREMENT
ALREADY REQUESTED 1
NO, GETIT

LINKS ON 1

210
211 00000134 >cdOQOO

212 00000137 >cdOOOO
213 OOOQ013a
2518
214 0000013c >ccOOOO
215 aOOOOD! OcOl03

216 00000142 >010061
217 00000145 >'0602
218 00000147 200'0
21'
220 00000149 >07Q05a

221 0000014c
222 OOOOOlH
223 00000152
224 00000154
22500000156
226 00000157
227 00000159
228 OOQOD15a
229 0000015d
230 OOOOOIS!
231 00000161
232 00000163
233 00000165
234 00000167
235 00000169
236 0000016c

OcOIO)
>030054
>b603
>'0700
48
>'0'000
97
>cdOOOO
2547
>b600
>'0100
2604
>1400
2009
>Od0003
>cdOOOO

BLO
JMP
GLOK
IGO
YELLOW

IG1
LPT

LPT

BRCLR
BRSET
BRCLR
LDA
STA
LSLA

3,STAT3.ABC
6,PORTB, IGI
l,STAT3,ABC
ACC+3

TAX
JSR
BCS

LOA
CMP
BNE
BSET

NTSAC
SKOSP

238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254

CARO
COK

>3fOO
>050003
>cdOOOO
a60!
>b700
>b600
>b700
>b700
>cdOOOO
>1500
>ccOOOO

BRA

ADD

237 COODOI6! >cdOOOO

00000172
00000174
00000177
0000017a
0000017c
0000017e
00000180
00000182
00000184
00000187
00000189

BFtSET
BRCLFt
LOA

NOTHLD

NO, SO FORCE A DECREMENT
ALREADY REQUESTED ?
NO, GETIT
GYC BITS ENABLED ?
GREEN LINK ON ?

LINKS ON 1
GYC BITS ENABLED '}
yELLOW LINKS ON '}

.3

X2
X3 FOR PAGE POINTER

.3

IS PAGE No. OK '2
IF NOT ABORT
ACC No
IF SAME ACC CCT
THEN FORCE UNSTOP

TEST

ABC
.3
ACC
NTSAC
2,STAT

BRA

CARO

BRCLR
JSR
JSR
CLR
BRCLR
JSR
LDA
STA
LOA
STA
STA
JSR
BCLR

6, STAT, SKOSP
OUTSP
RSTR
PDP
2, STAT. NOTHLD
NOHOLD
t$OF

JMP

SUB-PAGE MODE '}
YES, ABANDON IT
pUT PAGE No. BACK

C,

IF OLD PAGE ON HOLD
CANCEL HOLD
CORRUPT C6 FOR UPDATE

W3

R'
ACC
CHECK PBLF, IF HIGH DO NOTHING
IF LOW (PAGE FOUND) CLEAR FOUNDB
TO FORCE FETCHING OF LINKS.

CFND
2, STAT
TXT2

Index' Cyan Keys.

255
256 0000018c
257 0000018e
25800000191
259 00000193
260
261 00000196
262 00000199
263 0000019c
264 0000019f
265 OOOOOlal
266 000001a4
267 00000la6
26'
269 OOOOOla7
270 OOOOOla9
271 OOOOOlab
272 000001ad

aeO!
>cdOOOO
2414
>ccOOOO

INDEX

JMP

tIS
TEST
lAC
GIP

>07000d
Oc0103
>050007
aeOc
>edOOOO
2401
81

CYAN

BRCLR
BRSET
BRCLR

3.STATJ,ABC
6, PORTB. IG2
2, STAT3,ABC

IG2

LOX

ABC

JSR
BCC
RTS

274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295

00000lb!
00000Ib3
OOOOOIb5
00000lb?
000001b9
OOOOOlbb
OOOOOlbd
OOOOOlb!
000001e2
OOOOOlc4
000001c6
00000lc8
00000Ica
00000Icc
OOOOOlce
00000IdO
000001d2
OOOOOldS
OOOOOld?
00000ld9
OOOOOldb
OOOOOldd

>ldOO
>3!00
>e602
>b700
>b700
>e601
>b700
>b700
>e600
>b700
aOl8
>b?OO
>cdOOOO
>b600
>e?OO
>b600
>e701
>b600
>e702
>b600
>b?OO
>cdOOOO
a6S0
>b700
>3fOO
a602
>b700

297
298
299
300
301

000001d!
OOOOOlel
000001e4
OOOOOle?
00000Iea

>1500
>edOOOO
>cdOOOO
>edOOOO
>ecOOOO

273 DOOOOla!

2.'

lAC

CYOK

LOX
JSR
BCC

BCLR
CLR
LDA
STA
STA

LOA
STA
STA

LDA
STA
SUB
STA
JSR
LDA

STA
LDA
STA
LDA
STA
LDA
STA
JSR
LDA
STA
CLR
LDA
STA

BCLR
JSR
JSR
JSR

JMP

LINKS ON '2
GYC BITS ENABLED 7
CYAN LINK ON '}

"2

TEST
lAC

6, STAT
PDP
PAGO+2, X
PU
C2
PAGO+l,X
PT
C1
PAGO,X

RESET PAGE MODE

PH

.$18
R3
INDX
PH

PAGO,X
PT
PAGO+l,X
PU
PAGO+2,X
ACC

R'

UP

#$50

R11

R'
.2

R10
2.STAT
TXT38

RESET HOLD FLAG

TRAN1

DISPLAY TOP ROW
SET FOUNDB

SFND
TXT 1

42

303
304
30S
300
307
30.

Get linked page nos ,

309 DOOOOled >b6Da
310 DOOOOle! ab04

311
312
313
314
315
316
317
318
319

oaDeaUl
OOOOOlf3
ODOOOlf5
OOOOOlf7
OOOOOlf9
ODOOOlfb
QOOOOlfd
OaOOOlf!
00000201

LINJ(

>b700
>3iOO
a601
>b10D
a6ff
>b10I
>b702
>b703
>cdOOOO

ST>
CLR
LD>
STA
LD>
ST>
ST>
ST>
JSR
INC
LO>
ST>
BSR
BHS
LOX
STA

320 00000204 >3eDD
321 00000206 >b6QD

322 00000208 >b700
323 0000020a ad43
324 0000020c 2406
325 0000020e >beDa
326 00000210 >&100

327 00000212

BRA

2003

328 00000214 >cdOOOO

329 00000217 >b600
330 00000219 ab06
331 0000021b >b70D

NOTFND
NEXTC

332 0000021d >bEiDa
333 COODa2l! al03

334 00000221
33S

25e1

336 00000223 >cdOOOO
337 00000226 >3fOO

338 00000228

LD....
ADD

a604

339 0000022a >bIOC

JSR
LD ....

allocate to ....CC •.

CHAPTER
ADD 4 FOR GHOST ROWS

>CC

t4

R'

COUNT

H
.3
t$FF
ACC+l

....CC+2
ACC+3
INDXP
COUNT

LOOP ROUND RED.

GREEN " YELLOW

.3

RIO
GET LINKED PAGE No.
ALREADY IN RAM "2
YES, SAVE ACC No.
AG .... INST COLOUR

GLPI
NOTFND
COUNT
ACC.X
NEXTC
PUSH

NOT IN RAM, SO SAVE
PAGE NUMBER IN LIFO

.3

ADD

to

STA
LOA
CMP
BLO

N3
COUNT

NEXT LINJI;

t3

.... LL DONE "2

JSR
CLR
LD>
ST>

GCYI
MACC
COUNT

DEC
LOX
LOA
CMP
BHE
JSR
LO>
JSR
LOX
STA
JSR
JSR
LD....
CMP
BHI

COUNT
COUNT
ACC,X
#$FF
>LOC
PULL
WACC
CHCJI;l
COUNT
ACC,X
UP
GLP2
COUNT
#$01
LLOOP

LLOP
GET CYAN AND INDEX LINKS

t4

340
341
342
343
344

0000022c >3aOO
0000022e >beDa
00000230 >&600
00000232 alff

345 00000234

LLOOP

2612

346 00000236 >cdOOOO

34'1 00000239 >b60a
348 0000023b >cdOODO

349
350
351
352
353
354
355

0000023e
00000240
00000242
00000245
00000248
0000024a
0000024c

>beOO
>e700
>cdOOOO
>cdOOOO
>bEiOO
a101
22de

ALOe

IF STILL AN ACC AT SFF THEN
RECOVER PAGE No. FROM LIFO
ALREADY USED "2 IF SO INCREMENT

350
357 0000024e
358

81

RTS

35"
300

3.'

302
303
304
365
366
3Ei7
368
3fi9
370
371
372
373
374
375
376
377
378
379
380
381
3.2
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415

Fetch linked page' magazine nUJ'\\bers.

0000024f
00000251
00000253
00000255
00000258
0000025a
0000025d
0000025f
00000262
00000264
00000266
00000269
0000026b
0000026d
0000026!
00000272
00000274

>b600
a113
2203
>07006c
a610
>cdOOOO
>b601
>cdOOOO
>b700
>bfiOO
>cdOOOO
>b700
>bfiOO
>b700
>cdOOOO
>efiOO
>b700

GLPI

00000276
00000279
0000027c
0000027f
00000281
00000283
00000285
00000288
0000028b
0000028e
00000290
00000292
00000294
00000297
0000029a
0000029c
000002ge
000002aO

>cdOOOO
>070009
>000004
>1000
2002
>1100
>cdOOOO
>050009
>020004
>1200
2002
>1300
>070009
>040004
>1400
2002
>1500
>ccOOOO

R2BJ1

000002a3
000002a6
000002a8
000002ab
000002ad
000002af
000002b2
000002b4

>cdOOOO
>b601
>cdOOOO
>b700
>b600
>cdOOOO
>b700
20CO

R2BJ2

000002b6 >cdOOOO
000002b9 a018
000002bb >b700
000002bd afi04
000002bf >ccOOOO

NOTTH

COR

LO>
CMP
BHI
BRCLR
LOA
JSR
LOA
JSR
STA
LOA
JSR
STA
LOA
STA
JSR
LOA
STA
JSR
BRCLR
BRSET
BSET

BRA
HI
OKO

BCLR
JSR
BRCLR
BRSET
BSET

BRA
PTI
OKI

PUI
OK2

BCLR
BRCLR
BRSET
BSET
BRA
BCLR
JMP

JS'
LOA
JSR
STA
LOA
JSR
ST>

BRA
JSR
SUB
STA
LDA
JMP

RIO
t19

IF INDEX IGNORE LINK CONTROL

COR
3.ST.... Tl.NOTOK

HO
R2B
10BUF+l
DECODE

LINKS OK 1
YES, ROW 16 FOR LINKED PAGES
FETCH 2 LINK BYTES
DECODE UNITS

.2

IOBUF
DECODE
PT

DECODE TENS

.2
PU
INDX
PAGO.X
PH

CHECK FOR ZERO "]
FETCH CURRENT MAG.
PAGE HUNDREDS

RADIO
3. IOBUF.OJl;O
O.PH.Hl
O.PH
OKO
O.PH
RADIO
2. IOBUF,OJl;l
1.PH.PT1
1.PH
OKI
1.PH
3, IOBUF,OK2
2,PH,pul
2,PH
OK2
2.PH
SRCH
R2B
IOBUF+1
DECODE
PU
IOBUF
DECODE
PT
R2BJ1

MAG BIT ZERO OK "]
NO, SO TOGGLE

MAG BIT ONE OK ']
NO, SO TOGGLE

HAG BIT TWO OK ']
NO, SO TOGGLE

FETCH 2 LINK BYTES
DECODE UNITS
DECODE TENS

RELI

#$18
R3

#4
SPH

43

NO.

........................ ..... ....... "."" .............
,
."." .. " ..... .. .... .. .. ... "" .... "."."" ..............

41.
419
420
421
422
423
424
425
42'
427
42.
42'
430
431
432
433
434
435
436
43'
438
439

440
44:
442

443

4"
4<5
44'
44'

".
'"
1dOO
>edOOOO
>e600
>b100
>b602

Clee >ldOO
02tO >e600
C2f2 >b1CC
Olf4 >b6C2
02!"6

e2f?
C2f9
C2fb
Clfd
02f!"
030:
0303
0305
0307
0309
030b
030d
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72
73

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S3

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'"'"
".
'"
49'
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".
49'
588
50:

sn

503
S04
50S
506

0000330
0000332
0000334
0000336
0000338
0OO033a
OOOC33e
000033e
0000340
0000342
OC00344
0000346
0000348
OCC03';a
0OO034e
OOOG34e
00003S0

507
508 000003 5 ~

509
510
S11
S:l
S:3
514

CANCELL SUB-PAGE

PH

PAGEt2
PO

PAGEt2
1$39
NOV9
1$30
PO

PAGEt2
PAGEt1
PAGEt1
1$39
NOV9
t$30
PAGEt1
PAGEtl
PT
OK2

LOA
STA

4.

GLP2

6, STAT
PAGO,X

CANCEL SUB-PAGE

PH

LDA
DECA

PAGEt2

STA
STA
CM!'
BHS
LOA
STA
STA
DEC
LOA
eM!'
BHS
LDA
BRA

PO

>b60C
>b700
>e1C2
>b6CC
>b?OC
>e70:
>b6CO
>e7CO
aO:S
>b7CO

STA
LSRA
LSRA
LSRA
STA
LSRA
ADD
TAX
LDA
STA
STA
LDA
STA
STA
LDA
STA
SOB
STA

a309
221e
a6SQ
>b100
>b600
abGS
>b700
>3[00
a602
>b700
>b600
a:39
2206
>b60C
a:39
230:

CPX
BHI
LDA
STA
LOA
ADD
STA
CLR
LDA
STA
LDA
CM!'
6HI
LDA
CM!'
BLS

"

~s:

495

BCLR

>b70C
44
>bbOC

'"

493

NOTOK2

44

S:

.; 9~
~ 9:

NOV9A
NOV9

CM!'
BLS
LOA
STA
STA
INC
LDA
CM!'
BLS
LDA
STA
LDA

"44

P'

"2

"

INCA
STA

>b700
>b7C2
a:3C
24e9
a639
>b70C
>b702
>3aO:
>b601
aDO
24db
a639
2CdS

>b?OC

~ ~

'"

"

6, STAT
INOX
PAGO,X

PAGEtl
1$30
NOV9
t$39
PO

PAGEt2
PAGEtl
PAGEtl
t$30
NOV9
t$39
NOV9A

Request new linked page.

es
~

JSR
LDA
STA
LDA

"

"

• ••••••••••• * ....... * •••••••••• * •••• * ••••••••••••••••••••

415

~

BCLR

"

-1) links.

("

••• * ••• * •••• * ••••••••• * ...................................

4'6
t,

NOTOK3
NOTOK

4c

>b100
>bl0l
al39
2312
a630
>b100
>b102
>3eOl
>b601
a:39
2304
a63C
>b?Ol
>b6Cl
>b100
20b2

465

~

"

"

417

00000354
COOOO356
00C00359
0OOO035b
0000035e
00000361

'1
>cdOQOO
a606
>edOCOO
>1100
>edOOCC
>edOOOO
>eeOOOO

516 00000364
ae08
517 00000366 >e600
518 0000036S >e100
5.
2<1f9
81

C2

x2

C2

x3
X <- 3 x ACC No.

PO
C2

PAGO+2,X
P!
Cl

PAGOtl, X
PH

PAGO,X
U1S
R3
t9
ABORT

USO
Rl1

WACC
'$08

ACC

CLE.AR CHAPTER
INTO IIC

R.
R'

ROW 0

n

COLUMN 2

RlO
C2

'$39
ABORT
Cl

'$39
LOK

ABORT

TXT3
LDA
JSR
JSR
JSR
JMP
LOX
LOA
STA

PH,X
LIFO, X

BCLR

PUSH
PSHL

CLEAR CHAPTER
WAIT

"

TPAU2
3, R8
TX138
SFNo
TXTlL

515

51. 000OO36a
520 0000036b
521 0OOO036d

R2

FOR IT
~ON'T CLEAR THIS TIME
PDT PAGE. NUMBER IN CHAPTER
SET FOUND FLAG
AND REQUEST IT

..

oECX
BPL
RTS

44

523
52'
525
526
527
52.
529
530
531
532
533
534
535

."' ••••• ** ..................... "''''.** •••• ** ••••••••••••••••
I

..

0000036e >3fOO
00000370 >b600

SRCH

LOOPS

00000372
00000313 >bbOO
00000375
97

537 0000031c >e601
538 0000037e >blOO
539 00000380
2606
540 00000382 >e602
541 00000384 >blOO
542
543
544
545

00000386 270B
00000388 >3c:OO
OOQ0038a >b6QO
0000038c alD4
546 00000388
25eO
547

548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
57.
"9
580
581
582
583
584
585
586
587
588
58.
590
591
592
593
59.
595
596
597
598
599
600
601
602
603

00000390 >b600
00000392 alD4
00000394 81

60S
606
607
60B
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
62.
625
626
621
628
629
630
631

CLR
LOA
LSLA

ADD

00000376 >e600
00000378 >blOO
536 ODOOO37a
260c

60.

a page already in RAM 1

••••••••.••••••••••••••••.•••••.• "' .•..•••••.••••..•..• *.

FIN I

FNDZ

TAX
LOA
CMP
BHE
LOA
CMP
BNE
LOA
CMP
BEQ
INC
LOA
CMP
BLO
LOA
CMP
RTS

WAce
wAce
WAce
PAGD,X

PH
FIN!
PAGQ+l,X

PT
FIN!
PAGO+2,X

PU

.

FND2

wAce
WAce
LOOPS

WAce

IF MATCH THEN CHECK FOR

••

SUB-PAGE MATCH

(SHOULD

DISPLAY PAGE BE DIFFERENT)

•••••••• * •• ** ................ * .......... * .............................
Is Acequisition circuit in use '1

.......................... *." •• * .................. """ .... "".
00000395 >3eOO
00000397 Sf
00000398 >b600
0000039a >e100
000003ge 27f7
000003ge 5c
0000039f a304
000003a1 25f5
000003a3
81

SAM
CHCKI
CHC((2

000003a4
000003a6
000003a8
000003ab
000003ad
000003bO
000003b2

RADIO

>3eOO
>3eOO
>edOOOO
>b600
>edOOOO
>bfOO
81

001

INC
CLRX
LOA
CMP
BEQ
INCX
CPX
BLO
RTS
INC
INC
JSR
LOA
JSR
STX
RTS

WACC
WACC
ACC,X
SAM

..

CHCK2
RIO
RIO
R2BN9
IOBUF
DECODE
IOBUF

..... " •••• " •• " •••••••• " ••••• *.* ..... **.* ••• *.* ..... **"."**.
Transfer ghost row 20 to display row 24.
, Bet found flag.
**"*.""." ••• ,, ..........................
000003b3 >3fOO
000003b5 >b600
000003b7 ab04
000003b9 >b700
000003bb a614
0OOOO3bd ad5a

ROW24

MRE

CLR
LOA

ADD
STA
LOA
BSR

..

RIO
ACC

* ........................ * ......

CHAPTER
ADD 4 FOR GHOST ROWS

R'
.20
R2B

ROW 20

000003bf a620
OOOD03el >b700
000003e3 >b700
000003c5 >070008

LOA
STA
STA
BRCLR

t$20
Rll
PH
3,STAT3,BLANK

000003e8
000003ca
000003cc
000003ce
000003dO
000003d2
00OO03d4
000003d6
000003d8

>b601
>b700
>b600
>b700
>b600
>b700
a618
ad31
23db

LOA
STA
LOA
STA
LOA
STA
LOA
BSR
BLS

IOBUF+l
Rll
IOBUF
PH
ACC
R'
.2.
W2B
MRE

000003da
000003dc
000003de
000003eO
000003e2
000003e4
000003e6

>1800
a619
>b700
a608
>b700
a605
>ecOOOO

BSET
LOA
STA
LOA
STA
LOA
JMP

4.Rll
.25
R'

SET FOUND FLAG
WRITE IT
RON

RIO

COLUMN

JSR
BCS
BC:LR
BRA

CPBLf"
ABCF
4,Rll
SFND2

JSR
LOA
STA
LOA
STA
RTS

INDX
PAGO+1. X
PAGE+l
PAGO+2,X
PAGB+2

BLANK

SFND
SFND2

000003e9 >cdOOOO
000003ec 250f
000003ee >1900
00OO03!0 20ea

erND

000003f2
000003f5
000003f7
000003f9
000003fb
000003fd

INDXP

>edOOOO
>e601
>b701
>e602
>b702
81

000003fe Sf
000003f! >e600
00000401 >e700
00000403 5c
00000404 a309
00000406 25f7
00000408 81

ABCF

PULL
PLLL

CLRX
LOA
STA
INCX
CPX
BLO
RTS

SPACE
ROW24 ENABLED '1
YES, SO USE DATA

BACK TO
DISPLAY CHAPTER

ta
ts

TXT32

CLEAR FOUND FLAG

.

LIFO,X
PH,X
PLLL

45

."

. _ • • • fI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

• 34

R.ad and write .ubroutin•••

'3'
'3'
'37
• 3'
'3'

.
"

Cyan 6 Index link. , link control byte •

00000409
aOOOO40b
D000040d
00000410
00000412
00000414
00000416
00000411

>b700
a606
>cdOOOO
>3eOO
>3eOO
>b600

650
651
652
653
654
655
656
657
658
659
660
661
662

00000419
0OOOO41b
0000041d.
0OOOO41!
00000421
00000423
00000425
00000428
00000429
0000042.
0000042c
0000042e
00000430

>b700

00000435
00000437
00000439
0000043e
0000043.
00000441
00000443
00000445
00000448
0000044a

676 OOQOOUd
671 0000044!
678 00000451
6'9 00000453
680 00000455
681 00000457
682 00000459
683 0000045e
684 0000045.
685 00000460
686 00000462
U700000464
688 00000466
689 00000468
690 0000046a
691 0000046e
692 0000046e

.

,

a126
11
.a608

W2S

V,
R2S
R1BN9

>biOO
a604

>b700
>.eOO
>cdOOOO
.2
.2
a6Db

>b70a

a622
>b700
663 00000432 >coOOOO

READ22

665
666
667
668
669
670
671
672
673
674

a'll
>b700
>edOOOO
a640
>edOOOO
a6l!
>b700
>edOOOO
a650
>eeOOOO

GCYI

>b600
ab04
>b700
>3fOO
>3fOO
a610
>edOOOO
>b601
260.
&fi25
>b70a
a610
adbl
>b601
adOl
>bfOO

CLINK

".

."

....,.........,,,

81

. .3

700
'01
702
703
704

..
.
.,••

• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • iII • • • • • • • • • • • • • • • •

641
642
643
64.4
645
646
647
648

STA
LOA
JSR
INC
INC
LOA
CMP
Rn
STA
LOA
STA
LOA
STA
LOX
JSR
MUL
MUL
LOA
STA
LOA
STA
JMP
LOA
STA
JSR
LOA
JSR
LOA
STA
JSR
LOA
JMP
LDA
ADD
STA
CLR
CLR
LOA
JSR

LOA
SNE
LDA
STA
LOA
.SR
LOA
BSR
STX
RTS

ROIf2 •

TXTJ2

RiO
RiO
RiO
'3.

R'

ROIl

SUBJ

fSUB3
SEND22
DELAY TO SATISFY

."

lIC TIMING

SUBACR

'$22
ADOR
READ

."

CYAlI

.,0
GLPl

1$40
GLP2
INDEX

.31
Rl0
GLPl

USO
GLP2

..

ACC

RI
STAT3
Rl0

."

R2S

I08UF+1
NPl(27
tl7
Rl0

DESTINATION BYTE
IF HOT ZERO, NO PI(21
CHAIN CONTROL BYTE.

fl'

R2S

IOBUF+1
DECODS
STAT3

........................................................
........................................................
NPK27

Hamminq decode •

000004H >b700
00000471 Sf
00000472 >d60000
00000475 >b100
00000477 2732

DECODE

STA

TRA

LOA
CM!'
SEQ

HAM,X
Wl

00000479
0000047b
0000047e
00000480
00000482
00000484
00000487

>b700
>000004
>1000
2002
>1100
>edOOOO
2722

TRZE

STA

ZEl

seLR
JS.
SEQ

SUB2
0,sua2.ZE1
0, SUa2
ZIt1+2
0,SUa2

00000489
0000048e
0000048e
00000491
00000493
00000495
00000497
00000499

>d60000
>b700
>020004
>1200
2002
>1300
ad7a
2774

TROW

LOA
STA

OOOOOUb
000004ge
OOOOOhO
OOOOOhl
00000h5
00000h7
000004a9
OOOOOhb

>d60000
>b700
>040004
>1400
2002
>1500
ad68
2762

TRN

000004ad
000004bO
000004b2
000004b5
000004b7
000004b9
000004bb
0OOO04bd

>d60000
>b700
>060004
>1600
2002
>1700
ad56
2750

TRTH

Wl

CLRX
FNDJ

70'

706
707
708
709
710
711
712
7"

714
715
716
717
718
719
720
721

BRSET
aSET
BRA

BRIET
BSET
BRA

ONl

seLR
SSR
SEQ

SSUS

FNDJ
HAM,X

SUB2
1,SUB2,ON1
1,SUB2
ON1+2
1,SUB2

ssua

FNO

722

723
724
725
726
127
728
729
130

LOA
STA
BRSET

aSET
TWl

FNDJ

SRA
SCLR
BSR
SEQ

HAM,X

SUB2
2,5UB2.TW1
2,5UB2
TW1+2
2, SUB2
SSUB
FNO

731

732
733
734
735
736
737
738
739

LOA
STA

BRSET
THl

SSET
SRA
seL"
.SR
SEQ

HAM, X

SUB2
3,SUB2,1H1
3,SUB2
TK1+2
3,SUB2
SSUB
FNO

46

** .......... ***** .. ***** ... ******"'******* .. ** ••••••••• *** ••••••

741
742
743
744
745
740

More Hamming decode.

.............. "' ................ "........................... _.

147 OOD004bf >d60000
748 000004c2 >b700

TRFO

LOA
STA

HAM, X
SUa2

749 OOOD04c4 >080004
750 000004e7 >1800

BRSET
8SET

751 000004e9 2002
752 000004cb >1900

FOl

753 DODODted
ad44
273e
754 OOOOD4cf
755
756 000004dl >d6DOOO

B....
BCLR
BS'
BEQ

4,SUB2,FaI
4,SU82
F01+2
4,SU82
SSUB

TRFI

757 000004d4 >b10Q
758 000004d6 >OaOO04
759 000004d!J >laOO
760 DOOOD4db
2002

761 000004dd >lbDQ
762 0OOOO4df
763 000004e1
704

FIl

ad32

2720

165 000004e3 >d60000

TRSI

766 000004e6 >b70Q
767 000004e8 >000004

768
769
770
771
772

000004eb >lcOO
000004ed 2002
000004ef >ldOO
000004!l ad20
000004f3 271a

HAM, X
SU82

LDA
STA
BRSET

HAN,X
SUB2

BSET
BRA
SIl

FND

LOA
STA
BRSET
8SET
BRA
BeLR
BS'
BEQ

BCLR
BS'
BEQ

5.SUB2.FIl
5,5UB2
FIl+2
S,SUB2
SSUB
FND

6, SU82, SIl
6,SUB2
SI1+2
6,SUB2
SSUB
FND

773

774
775
776
771
778
779
780
781

000004f5
000004f8
000004fa
000004fd
000004ff
00000501
00000503
00000505

>d60000
>b700
>OeOO04
>leOO
2002
>lfOO
adOe
2708

TRSE

LOA
STA

BRSET
aSET
BRA
SEl

BCLR
BS.
BEQ

HAN,X

SUB2
7, SUB2, SEI
7,SUB2
SEl+2
7,SUB2
SSUB
FND

782

783
784
785
786
787
788

00000507
50
00000508 a30!
0000050a 2203
OOOOOSOc >eeOOOO
OOOOOSOf >d60000
00000512
81

INCX
CPX
BHI
JMP
LOA
'TS

78'

790 00000513 >b600
791 00000515 >bl00
792 00000517 81
793
794
795
790
,.7
,.8

NUM,X

.,

SUB2

....................................... * ..........................

Mix/nomix.

.* ••••••••••••.••••••••.•.••••••••••••.••••••••••••••.••.

,..
800
801
802
803
804
805
B06
807
808
809
810

LOA
CMP
RTS

f$OF
FND
TRA

00000518
0000051b
0000051d
000005lf
00000521
00000523
00000526
00000528
0000052a
0000052c
00OO052e

>OeOO15
>leOO
a610
>b700
a606
>edOOOO
a66e
>b700
a617
>b700
2015

MIX

00000530
00000532
00000534
00000536
00000538
0000053a
0000053e
0000053e

>lfOO
a616
>b70Q
a6ee
>b700
a646
>b700
2005

NOHIX

00000540
00000542
00000545
00000547
0000054a
0000054b
0000054e
00000550
00000552
00000554
00000556
00000558

a606
>edOOOO
a602
>edOOOO
4f
>edOOOO
>1800
ad15
a606
>b700
a60"l
>b700

TRANl

0000055a
0000055e
0000055e
00000560
00000562
00000564

a605
>b700
a604
>b700
>aeOO
>eeOOOO

TXT2

00000567
00000569
0000056b
0000056d
0000056f
00000571
00000573
00000515
00000577

a619
>b700
a606
>b700
>b600
>b700
>3fOO
a605
>eeOOOO

F.O

BRSET
BSET
LDA
STA
LDA
JS'
LDA
STA
LOA
STA
BRA

7, STAT2, NOMIX
7,STAT2
1$10

"

ALREADY MIXED ?
NO, SO MIX IT
BROADCAST, 312/313 SYNC
ENABLING GHOST ROWS

1$06
Noax
t$6E
'S

1$17

$46 FOR NOMIX FLASH/SUBT.

.0
TRAN2

811

812
813
814
815
816
817
818
819

BCLR
LDA
STA
LDA
STA
LDA
STA
BRA

7,STAT2
1$16

MIXED, SO NOMIX
CCT, 312/312 SYNC
ENABLING GHOST ROWS

.,

UCC
.5

#$46
.0
TRAN2

820

821
822
823
824
825
826
827
828
829
830
831
832

TRAN2

TRAN3

LDA
JS'
LOA
JS'
CLRA
JS'

aSET
BS'
LDA
STA
LDA
STA

833

834
835
836
837
838
839

LOA
STA
LOA
STA
LOX
JMP

840
841

842
843
844
845
846
847
848
849
850

LOA
STA
LDA
STA
LDA
STA
CL'
LDA
JMP

to

BOXOOF
t2
SPM

SET-UP SYNC

aOXOON
4,STAT
FORCE HEADER DISPLAY

F'O
to
TM>

58 TIMER

1$0"1
.7

ENABLE ALL BOXES

.,

DISPLAY 'CONTROL

tS

t4

SUB2
'SUB2
SEN022

..

.,5

FORCE DISPLAY OF HEADER

to

.10
ACC
.8

."

t5

TXT32

47

••••••••• " ••• ** •••••••••••••••••••••••••••••••••••••••••

852
85'

.,.

.

Hold.

855
856

"

** ••••••••••••••••••••••••••••••••••••••••••••••••••••••

858
859
.60
861
.62
86.3
'6'
.65
866
.67

0000057.1
0000057c
OOOaOS7f
00000581
00000583
00000585
00000588
OOOOOSBa
0OOOO58c

869
870
871
872
87'
87'
875
876
877

00000591
00000593
00000596
00000598

DaOQased

>3fOO
>040062
>1400
>b600
>b700
>cdOOOO
>3fOO
>ldOQ
Sf
ad2b

868 DODD ass! >b60a

."
."
880
881
882
88'

88'
.85
886
887
888

."
"0

HOLD

BRSET
SSET

UCHOLD

>b7QO
>cdOOOO
>3fOO
>1700
0000059.1 a604
0OOOO59c
adl!
OaOOO5ge 20ae
000005aO >OcOOOa

000005013 >.3fOO
000005.15 >3[00
OOOD05.17
OOODOSa9
OOOOOSab
OOOOOSad
OOOOOSaf
OOOOOSbl
OOOOOSb3
OOOOOSbS
OOOOOSb7

OOOOOSba
OOOOOSbe
892 OOOOOSbe
OOOOOSbf
00000Se1
00OOOSe3
896 OOOOOSeS
00000Se6
898 00000Se8
899 OOOOOSea
900 OOOOOSed
OOOOOSe!
902 OOOOOSd2
OOOOOSd4
'04 OCOOC5d7
905 OCOOOSd9
906 000005dc
907 000005de

..."'",
'"

."
.01

'"

'08

>3fOO
aGOf
:>b700
a60a
:>b700
a60l
:>b700
:>aeOO
:>eeOOOO
:>bfOO
:>3fOO

TXTl
TXTIL

SPM2
SPH

DISP8

ad07
:>b600
ab04

"

DISP4

910
91:
912
9:3
9:4
915 OeOOOSe! :>IS00
916 00000Se3 :>b600
OOOOOSeS :>b700
91. 00000Se7 >3fOO
919 OOOOOSeS aG02
920 000005eb >b700
91' 000005ed a650
922 000005ef :>b700
923 000005fl
adOb
91' 0000050 ad14
925 000005f5 >edOOOO
926 000005f8 >cdOOOO
927 000005fb >eeOOOO

DISPLAY CHAPTER

ROW 0

3,R3

HOLD

LOA
BSR
BRA

f4
SPH
TRAN'

WAS TXTl

BRSET
CLR
CLR
CLR
LOA
STA
LOA
STA
LOA
STA
LOX
JHP

6, STAT. SPM2
C3
C'
C5
tSOF
C6

STX
CLR
CLRA
BSR
LOA
ACO
TAX
LOA
STA
LOA
STA
LOA
STA
LOA
STA
LOA
STA
JHP

CORRUPT C6 SO THAT NEXT
ARRIVAL IS SEEN BY UPDATE

.,

OlD

Ol

SUB1
fSUBI
SEND22

.3

••

DISP4
.3
f4

f4
RlD
LHOLD, X
Rll
LHOLD+l,X
PH
LHOLD+2,X
PT
LHOLD+3, X
PV
TXT3

Nohold.

NOHOLD

n.

929 OOOOOSfe >b600
930 00000600 >cdOOOO
00000603 >edOOOO
932 00000606 >e600
933 00000608
81
00000609 >b700
0000060b a018
936 0000060d >b700
937 0000060f >e601
938 00000611 >b700
939 00000613 >b100
940 00000615 >e602
941 00000617 >b700
942 00000619 >b700
943 0000061b >ceOOOO

RELI

'"

'3'

REL2

'"

0000061e
00000620
00000622
00000624
00000626
00000628
0000062b
0000062e
00OO062f
'SO 00000630

ROW 0
RESET SUB-PAGE HODE

DISP8
ACC
R'
UP
R.

•••••••••••• * ••••••••••••••••••••••••••••••• ** ••••••••••

'"

945
946
947
948
949
950
951
952
953

PDP
2. STAT. NOHOLO
2, STAT
ACC
R'
UP
R'
6, STAT

••••••••••••••••••••••••••••••••• t ••••••••••••••••••••••

'"

'"

LOA
STA
JSR
CLR
BCLR
CLRX
BSR
LOA
STA
JSR

C'"
BCLR

4f

a604
:>b700
:>d60000
:>b700
:>d60001
:>b700
:>d60002
:>b700
:>d60003
:>b700
:>ccOOOO

CLR

>b600
:>b700
a609
>b700
a619
>cdOOOO

CPBLF

.,

>OaOlOl

"

81

HIGH

BCLR
LOA
STA
CLR
LOA
STA
LOA
STA
BS'
BS'
JSR
JSR
JHP

2,STAT
ACC
R'
R'

LOA
JSR
JSR
LOA
RTS
STA
SVB
STA
LOA
STA
STA
LOA
STA
STA
JHP

ACC
UP
INDX
PAGO,X

LOA
STA
LOA
STA
LOA
JSR
SEC
BRSET
CLC
RTS

ROW 0

t>

R10
1$50
Rll
RELl
REL2
TXT38
SFND
TRAN2

COLUMN 2

PH

fS1I
.3
PAGO+l,X
PT
Cl
PAGO+2, X
PU
C2
TXTl
ACC
R.
U
R10
'2S
'2B
S,IOBUF+l,HIGH

48

..••.......,"0

• ••••••••••••••••••• ** ••••••••••••••••••• ** •••• **** .... **

"7

Reveal.top/bottom. , clock .
••••••••••••••••••••••• " .......... "' ...................... **

962 00000631 >DaDOO4

963 00000634 >laDO
964 00000636 2016
965 00000638 >lbOO
966 000006301. 2012
967 0000063c >DiODOb

REVEAL

'EV

EXPTB

968 0000063! >090004
969 00000642 >1700
910 00000644 200B

BRSET

BSET
BRA
eeL.
BRA
BRCLR
SRCLR
BCLR
BRA
BSET
BRA

971 OOOOOU6 >1100
972 00000648
2004

80T

973 0000064a >1600

EXP

B5ET

974 0000064c >1900
915 0000064e >c:cOOOO

OUT

BCLR
JMP

S,Ri.REV
5.Ri
OUT

S,Ri
OUT

3.R?,EXP
4.RI,BOT
3,R?
OUT
",Ri
OUT
3,R?
",Ai

SINGLE HEIGHT
BOTTOM

TOP

TXTZ

.7.
971 00000651 >OcOOde

TIME

918 00000654 >010003
979 00000651 >ecOOOO

980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015

0000065a
0000065d
0000065f
00000661
00000664
00000666
00000668
00000669
0000066b
0000066d
0000066f
00000672
00000674
00000676
00000679
0000067b
0000067d
0000067f
00000682
00000684
00000686
00000687
00000689
0000068b
0000068d
0000068f
00000691
00000693
00000695
00000691
00000699
0000069b
0000069d
0000069f
000006a1
000006a3

>Oa0025
>b600
>b700
>cdOOOO
>1800
>laOO

CLOCK

BR5E'1'
LD.
S"
JS.

BSET
BSE'l'

Of

adlc
a61e
adle
>cdOOOO
a609
>b700
>cdOOOO
a646
>b700
>b700
>cdOOOO
a606
>b700
81
>b700
a620
200a
>b700
a60b
2004
>b700
460a
>b100
>b100
>b600
>b700
>3fOO
a606
>ccOOOO

BRSET
SRCtR
JMP

T.O

HOBX
BOXOON
BOXOOF
80X

CLM
BS'
LOA
BS.
JS,
LOA
S"
JS.
LOA
STA
STA
JS.
LOA
S"
.TS
S"
LOA
BRA
STA
LOA
BRA
STA
LD.
ST'
STA
LOA
STA
CL'
LD.
JMP

6.STAT7,HICH
0, ST1.T. CLOCK
SUBPG
5,5'1'AT,TAO

TELETEXT CHIP ?
TELETEXT MODE ?
YES
NO, TIME A.LREADY ON ?

ACC

••

UCHOLD

4.STAT
5,S'1'AT
NOax

BO
BOXOOH
F'O
#$09
07
TXT2
#$46

STOP FLASHES ON FIRST PRESS

.,
••
••

TXT2
TMR

.,0
.,0
.,0

#$20

80X

#$OB

BOX

#$OA
011

.••

PH

••••

TXT32

49

1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035

1036
1037
1038

1039
1040
1041
1042
1043
1044
1045
1046
1047
1048

1049
1050
1051
:.052
1053
1054
~055

Sub-page nUl'flber entry routine.

000006a6
000006a9
000006ab
000006ad
aa0006af
000006b1
000006b3
000006b5
000006b7
000006b9
000006bb
000006bc
000006be
000006cO
000006c2
000006e4
000006e6
000006e8
000006ea
000006ec
000006ee
000006dO
000006d2
000006d4
000006d6
000006d8
000006da
000006de
000006de
000006eO
000006e2
000006e4
000006e6
000006e7
000006e9
000006ec
000006ee
000006fO
000006f2
000006f4
000006[6
000006f8
000006fa
000006fe
000006fe
00000700
00000703
00000706
0 a 0007 D8
0000070a
OOOOOlOe
0000070f
00000711
000001:3
00000715

>edOOOO
>b600
a010
>beOa
2704
a302
260f
al07
2302
a008
5d
2606
al03
2302
a004
ab30
>e703
a303
2714
a62a
a3al
2706
a302
2704
>b704
>b705
>b706
>3eOO
2002
>3fOO
>b600
>bl00

DIGITS

500

THOU

SOCH

SORTD

HUN
SEN

SLRPD
SPGN

4f

1056
>b700
:057
:>edOOOO
1058
a602
1059
:>b700
:060
>b603
106:
>bl00
1062
>b604
1063
>bl00
1064
:>b605
:065
>b700
:066
>b606
1067
>bl00
1068
:>edOOOO
1069
>edOOOO
:070
>b600
~ all
2661
:072
a606
:073
>edoaoo
:074
>b603
1075
>bl00
:016
>b604
:077
>b70D
:078
:079
:080
:08:
:082
:083
:084
:085 000007:7 >b60:
:086 00000719 :>b700
:087 0000071b >b602
:088 eeOD071d >blQO
:089 OOOOOll! >b603
:C% 00000721 :>b700
:091 00000723 >b604
:092 00000725 >b700
:093 00000727 >b605
:094 00000729 >b70C
1095 0000072b >b606
1096 COOOa72d >blOO
:097
:098 0000072f >b600
:0990Q000731
a018
:100 00000733 >b700
1101 00000735 >b600
:102 00000737 >edOOOD
~ 103 0000073a :>cdOOOO
:104 000007Jd >1500
1105 00000l3f >ccOOOO
1106
1107 00000742 >b600
1108 00000744
al30
1109 00000746
2604
1110 00000748
a638
1111 0000074a >b700
1112
1113 0000074e a608
1114 0000074e >b700
1115 00000750
a608
1116 00000752 >b700
1117 00000754 >aeOO
1118
1119 00000756
a622
1120 00000758 :>b700
1121 0000075a :>ccOOOO
1122
1123 0000075d >b600
1124 0000075f >b70D
1125 00000761 >b600
1126 00000763 >cdOOOO
1127 00000766 a604
1128 00000768 >ccOOOO
1129 0000076b
81

JSO
LO.
SUB
LOX
BEQ
CPX
BNE
CMF
BLS
SUB
TSTX
BNE
CM?
BLS
SUB
ADD
ST.
CPX
BEQ
LO'
CPX
BEQ
CPX
BEQ
STA
ST.
STA
INC
B ....
CLO
LOA
STA
CLRA
ST.
JS.
LD,
ST.
LOA
STA
LOA
STA
LOA
ST.
LOA
STA
JS'
JSO
LOA
.NE
LOA
JSR
LOA
STA
LOA
ST.

TPSTP
W2

.,6

PDP
THOU

f2

.
."

SORTD

t7

THOUSANDS OR TENS
NO, SO DON'T CHANGE
YES, 8->() , 9->1
WAS
CPX to

SOCH

SORTD
MORE THAN 3 1
NO
YES, 4->0 TRRU 7->3
CONVERT TO ASCII

SORTD

.$30
PAGE+3, X

"

UNITS?
YES, SO CLEAR PDP
ASTERISK
HUNDREDS ?
YES, SO LEAVE HUNDREDS
TENS 1
YES, SO LEAVE TENS , HUNDREDS ?
CLEM HUNDREDS
CLEAR TENS
CLEM UNITS

SLRPO
ts2A

t!
HUN
Ol
SEN
PAGE+4
PAGE+5
PAGE+6
PDP
SPGN
PDP
ACC
O'

ROW 0
COLUMN 0

0'
BOXOON
.2

COLUMN 2

'10
PAGE+3

011
PAGE+4
PH
PAGE+5
PT
PAGE+6
PU
TXT3
TRAIl!
PDP
SSO

'6

NOaX
PAGE+3

011
PAGE+4
PH

Get requested sub-page.

SETIT

LOA
STA
LOA
ST.
LOA
STA
LOA
STA
LOA
ST.
LOA
ST.

PAGE+l
C!
PAGE+2
C2
PAGE+3
C3
PAGE+4
C'
PAGE+5

LOA
SUB
STA
LOA
JSO
JSO
BCLR
JM?

PAGE
ts18
.3
ACC
UP
TXTl
2,STAT
SFND

TX138

LOA
CM?
BNE
LOA
STA

PH
t$30
TXT3
ts38
PH

TXT3
TXT32

LOA
STA
LOA
STA
LOX

es

PAGEH'
C6

PAGE REQUEST HUNDREDS

REQUEST IT
NOHOLD
WR I TE ONE TO FOUND

....

.!

WRITE CCT RAM VIA I Ie

SUB3
fSUB3

SEND22

LOA
STA
JM?

t$22
ADD'
SEND

TPSTP

LOA
STA
LOA
JSO
LOA
JM?
OTS

PAGE
.3
ACC
UP

SSO

PAGE HUNDREDS

HOLD DURING
SUB-PAGE NUMBER
ENTRY

.

SPM

50

1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1161
1168
1169
1110
1171
1172
1113
1114
1115
1116
1111
1118
1119
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
119.3
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
121.3
1214
1215
1216
1211
1218
1219
1220
1221
1222
1223
1224
1225
1226
1221
1228
1229
1230
12.31
12.32
1233
1234
1235
1236
1231
1238
1239
1240
1241
1242
124.3
1244
1245

Sub (timed) pages.

0000076e
0000076f
00000771
00000773
00000775
00000778
0000077a
0000077e
0000077e
00000180
00000782
00000784
00000786
00000788
0000078a
0000078e
0000078e
00000790
00000792
00000794
00000796
00000798
0000079a

>Oe002e
>1eOO
adea
>3fOO
>cdOOOO
>e600
>b700
>e601
>b701
>e602
>b702
a62a
>b700
>b700
>b700
>b700
>b600
>b700
>3fOO
a602
>b700
adb2
>eeOOOO

SUBPG

0000019d
0000019f
000001a1
000001a4
000001a6
000001a9

adOd
>b600
>edOOOO
>1500
>edOOOO
>eeOOOO

OUTSP

000001ac
000001ae
000001bO
000001b2
000001b4
000001b1
000001b9
000001bb
000007bd
000001bf
000001e1
000001c3
000001c5
000007c1
000001c9
000001cb
000001ed
000007ef
000007d1
000007d.3
000007d5

>ldOO
>3fOO
a650
>b100
>cdOOOO
>e600
>b100
a018
>b100
>e601
>b100
>b100
>e602
>b700
>b100
>3fOO
a602
>b100
>b600
>b700
>ceOOOO

SRSET
SSET
BS'
CL.
JS.
LOA
STA
LOA
STA
LOA
STA
STA
STA
STA
LOA
STA
CL.
LOA
STA
BS.
JHP
BS.
LOA
JS.
BCLR
JS.
JHP
BCLR
CLR
LOA
STA
JS,
LOA
STA
SUB
STA
LOA
STA
STA
LOA
STA
STA
CLR
LOA
STA
LOA
STA
JHP

6, STAT, OUTSP
6,STAT
TPSTP
PDP
INDX
PAGO,X
PAGE
PAGO+l,X
PAGE+l
PAGO+2,X
PAGE+2
t$2A

.11

PH
PT
PU
ACC

...
.2

.10
TXT.3
T!WI1
ACC
UP
2, STAT
TXTI
T!WI1

RESET HOLD FLAG

6, STAT
PDP
1$50

.11

INDX
PAGO,X
PH
1$18
.3
PAGO+1,X
PT
C1
PAGO+2, X
PU
C2

••

..
f>

"'0
ACC
TXT38

Read in Row 25 information.

000007d8
000001da
000007de
000007de
000007eO
000001e2
000007e4
000007e7
000007e9
000007eb
000007ed
000007ef
000007fl
000001f3

>b600
>b100
>lbOO
a602
>b700
a619
>edOOOO
>b601
>bl00
2704
>laOO
>b700
>b600
>b100

000001f5
000007!?
000001f9
000001fb
000001fe
00000800
00000802
00000804
00000806
00000808
0000080a
0000080e
0000080e
00000810

a604
>b100
a619
>cdOOOO
>b601
>b100
2104
>laOO
>b100
>b600
>bl00
2104
>laOO
>b100

00000812
00000814
00000816
00000818
0000081a
0000081e
0000081e
00000820
00000822
00000825
00000821
0000082a
0000082e
0000082e
00000830
00000832
00000834

a40c
>1500
>1100
>baOO
>b100
a606
>b100
a619
>edOOOO
>1100
>0.30102
>1600
>b600
>bl00
2704
>laOO
>b100

00000836
00000839

Of 0101
81

GET25

LOA
STA
BCLR
LOA
STA
LOA
JS.
LOA
CHP
BEQ
BSET
STA

SM6

SM'

SM3

TRS

CGET26

LOA
STA
LOA
JS.
LOA
CHP
BEQ
SSET
STA
LOA
CHP
BEQ
BSET
STA
AND
BCLR
BCLR
ORA
STA
LOA
STA
LOA
JS.
BCLR
BRCLR
BSET
LOA
CMP
BEQ
SSET
STA
BRCLR
RTS

..

ACC
5,STAT2
'2

CLEAR DIFFERENCE FLAG
COLUMN 2 (MINUTES)

'25
.2B
IOBUF+l
C6
SM6
5,STAT2
C6
IOBUF
SUB2

'OW

010

MINUTES UNITS
MINUTES TENS" CelT 4

f4

COLUMN 4

(HOURS)

.,0
.25
.2B
IOBUF+l
C.
SM'
5,STAT2
C.
IOBUF
C3
SM3
5,STAT2
C3

'OW

HOURS UNITS

HOURS TENS " CBITS 5 " 6

t$OC
2,STAT7
3,STAT7
STAT7
STAT7
.6

SAVE CBITS 5 " 6 IN STAT7
CLEAR NEWSFLASH BI T
CLEAR SUBTITLE BIT
COLUMN 6

(CONTROL BITS)

010
'25
.2B
3,SUB2
1, IOBUF+ 1, TR5
3,SUB2
SUB2
C5
CGET26
5,STAT2
C5

ROW

7, PORTS, GET26

PACKET 26 ENABLED:

51

XFER CBIT8 (UPDATE)
TO BIT 3 OF MINUTES TENS
(REPLACING CBIT4 (ERASE)

1247
1248
1249
1250
1251
1252
1253
1254
lZ55
1256
l25'?
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1218
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
12119
1290
::.291
1292
1293
:294
1295
1296
:297
:29B
:299
:30C

........................................................
........................................................
Proce •• packet 26 info.

0000083a a6ff
0000083c >b700

GET26

LDA
STA

0000083e
00000840
00000842
00000844
00000846
00000848
00000844
0000084c
0000084e
00000850
00000852
00000855
00000857
0000085a
0000085c
0000085e
00000860

>3f01
>b600
ab04
>b'?OO
>b601
>b'?OO
>3cOO
>b600
alOe
2303
>ccOOOO
>b600
>cdOOOO
>b60!
>bl00
26de
>3aOl

LOOP26

CLR
LDA
>DD
STA
LDA
STA
INC
LDA

00000162
00000864
00000866
00000868
0000086a
0000086c
0000086e
00000870

>b600
ab04
>b700
>YeOl
>3cOl
>b601
>b700
a126

00000872
00000874
00000876
00000878
0000087a
0000087c
0000087f

230d
>3fOO
a6ff
>b700
>b600
>cdOOOO
20bd

00000811
00000883
00000886
00000888
OOOOOlla
aOOOOllc
OOOOOlle
06000890
00000892
:30:. 00000894
:302
:303 00000891
:3 O~ 00000199
:305 OCOOCB9b
:306 0000089d
:30"'1 OOOOOn!
:308 ooeOOBaO
:37:9 OOOOOBal
:3:0 OOOOOla3
:3:: OeOOOBa6
:3:2 OOOOOBaB
:3:3 OOOOOha
:3 :~ 00OOC8ac
:3:5
:3:6 OOOOOSae
:3:7 000008bO
:3:1 000008b2
:3:9
:320 OCOO08b~
:32: 00CCC8b6
:322
:323 000008b8
:32~ OOOOC8ba
:325 CCOCOBbc
:326 CCCC08be
:327 ~CCCClcO
:328 '::COCCBc2
:329

>b600
>cdOOOO
>b601
>b708
>b600
>b70'?
>3c01
>b60!
>b700
>cdOOOO

CMP

OKROW

LOOP62

BRA
NXTCH

LDA
JSO
LDA
STA
LDA
STA
INC
LDA
STA
JSR
LDA
STA
LDA
AND
LSRA
LSRA
STA
JSR
LDA
C....
B.O
BLO

""

>b702
>cdOOOO
>b605
a128
2106
250a

RW24

SUB
BRA
LDA

LlFO+!

••

LlFO+l

...
OlD

LIFO
LIFO
EN026

LIFO
02B

IOBU1"+1
LIFO

IS BYTE

LOOP2,

NO, TRY NEXT ROW

~ERO

,.

ACC
R'

LIFO+l
LIFO+l
LIFO+1
RlD

'38

PAST END OF ROW '1

NXTCH
YES. BLOW AWAY ROW

RlO
1$1"1"

CORRUPT SEQUENCE No.

Oil

LIFO
W2B

LOOP26

NEXT ROW

LIFO
GET 2 BYTES

R2.

IOBUF+1
LIFO+8
lOBUli'
LIFO+7
LIFO+l
LIFO+!
RIO

GET THIRD BYTE

R2BN9
IOBUF
LIFO+6
LIFO+7
f$7C
LIFO+2

SAVE MODE

E>: f06
>d60000
>b:06
270a
9!
ab07
97
a:Sb
23!:
g63
>0602
a40!"
>0103
275b
al04
2312
al08
2604
a003
2001

CLRX
TaNCH

BeLO
LDA
CMP
BEQ
TXA
>DD
TAlC
CMP
BLS

BRA
CHFND

LDA
AND
STA
BEO
CMP
BLS
CM!'
BNE
SUB
BRA

OK '1

LIFO+1

SKIP

LDA
CM!'
BEO

STILL l'ACnT 26 'l

OK"""

NOTROW

BRCLR

GHOST CHAPTER

O'

>b604
>b700
>b600
>bl00
>0605
>bl00

CCCCC8c~

START NEW ROW

ACC

>b704
20u

>09024:
:33: ~C:::C08c7 >b602
:332 C'::CCC8c9 a:10
:333 C~C:::C8cb 2775
:33';

LDA
>DD
STA
INC
INC
LDA
STA
CMP
BLS
CLR
LDA
STA
LDA
JSR

>b600
>b706
>b607
a47c

a028
2002
a61e

BLS
JM!'
LDA
JSR
LDA
CM!'
BNE
DEC

UFF
LIFO

7, LIFO+6
CTAB,X
LIFO+6
CHFND

,7

,.,
TRNCH
CHNF
LIFO+2
tsOF
LIFO+J
CHNY

...

NULL DJA.

GTT

NOTCF

t3
UOC

52

1358
1359
1360
1361
1362

1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1)73
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460

00000Sf5
al0b
OOOOOSr?
2702
00000Sf9 2049
OOOOOBfb 01005
ODOOOSfd >b703
000008ff
9f
00000900 >bb03
00000902
97
00000903 >d60000
00000906
203e

NOTCF

00000908 >b602
0000090a
a10f
0000090e 271e
0000090e 01102
00000910
263e

NOTO

00000912
00000914
00000915
00000918
000009101
0000091d
000009lf
00000921
00000922
00000923
00000925
00000928

G3BIT

BCLR
CLRX

TN32

LOA
BNE
JMF

000009201
0000092e
0000092d
00000930
00000932
00000935
00000937
00000939
000009301
0000093b
0000093d
00000940

>lf06

BEO
BRA
SUB
STA
TXA

5f

>d60000
2603
>eeOOOO
>bl06
2704

G32F

>lf06

G2BIT

5f

LOA
CMF
BEO
CMF

LIFO+2
'$OF
G28IT
'$02
END26
7, LIFO+6
GJTAS, X
STRM

LOOP 62
LIFO+6
G32F
TN32
G3TAB+l, X
GOTCH

BCLR
CLRX

7, LIFO+6
G2TAB, X
STMR

STMR
BEO

LOOP 62
LIFO+6
G23F

INCX
INCX
G23F

LOA
BRA

NULD
CHNF

BSET
LOA

TN23
G2TAB+l,X
GOTCH
7, LIFO+6
LIFO+6
R11

00000948
a605
000009401 >edOOOO
0000094d >ecOOOO
00000950

CTAS, X
GOTCH

TN23

5e
5e

00000942 >le06
00000944 >b606
00000946 >b700

LIFO+3

LOA
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5e
5e

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ts

ADD

BEO

20fO
>d60001
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>d60000
2603
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tll
CEDI
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ts
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END26
......................... "* •• " ............. " ••••••••••••••••••••••• "

Packet 26 character look-up table_

..... * ............ " ••••• " ••••••• *** •••• ** .................. * ... **
00000951
00000957
0000095d
00000963
00000969
0000096f
00000975
0000097b
00000981
00000987
0000098d

202021e02383
248426932740
289429a72aa2
2cbc2d5e2ebe
2f7630cb37c7
388a39a73aa2
3c823d8c3e89
3fe161f963e5
69fd6be66cfe
71f879fc7cff
7f7fOO

G2TAB

00000990
00000996

51815b8dSe8b
Sd8eSf2000

G3TAB

0000099b
000009a2
000009019
00OO09bO
000009b7
000009be
00000ge5
00OO0gec
000009d3
000009da
00000gel
00000ge8
DOOO0gef
000009f6

61eaebd2c59261
41flf041dS9b41
65egeede65db65
45f290454S4S45
696gedde69d469
4949f34949f449
6fe8eed8c6986f
4ff6f5d8d69c4f
75elefd975e275
5555f75555ge55
6e6e6e6ee86e6e
4e4e4e4ee74e4e
636363636363e3
434343434343d7

eTAB

OD0009fd
000009ff
00000a02
00000a04
00000a07
00000a09
OOOOOaOc
OOOOOaOe
00000a11
OOOOOa13
000000116
00000a18
OOOOOalb
OOOOOald

>3f05
>030702
>la05
>010702
>1805
>Od0802
>1605
>Ob0802
>1405
>090802
>1205
>050802
>1005
81

FCB
FeB
FCB
FeB
FeB
FeB
FeB
FeB
FCB
FCB
FCB

FCB
FeB
FeB
FeB
FeB
FeB
FCB
FeB

eLR

BRCLR
N032
BRCLR
SSET

NO'
N04
N02

$21,
$26,
$29,
$2D,
$30,
S39,
S3D,
$61,
S68,
579,
500

$EO,
$93,
SA7,
$5E,
$C8,
$A7,
$8C,
SF9,
$E6,
SFC,

$23,
$27,
$2A,
$2E,
S37,
S3A,
$3E,
$63,
$6C,
$7C,

$83
$40
$A2
$8E
SC7
SA2
$89
$E5
SFE
SFF

SSI, $81, $58, $80, SSC, $88
$50, SSE, $5F, 520, $00

FeB
FCB

N016

$20, $20,
$24, $84,
$28, $94,
$2C, $8C,
S2F, $76,
$38, $8A,
$3C, $82,
S3F, $El,
$69, SFO,
S71, SF8,
$7F ,S7F,

BSET
BRCLR
BRCLR
BSET

S61, $EA, 5-EB, S02, $C5, $92, $61
S41, $Fl, $FO, $41, $05, S98, $41
$65, SE9, $EC, $OC, $65, SOB, $65
545, $F?, $<)0, $45, $45, $45, S45
$69, S69, $EO, $OE, $69, $D4, S69
$49, S49, 5F3, $49, $49, $F4, 549
$6F, $C8, $EE, $08, $C6, 598, S6F
$4F, $F6, 5F5, 508, $D6, $9C, 54f
$75, $Cl, 5EF, $09, $75, $E2, 5":5
$55, $55, 5F7, $55, 555, $9E, $55
$6E, $6E, $6E, $6£, 5£8, $6E, 56!':
$4£, $4£, $4E, $4£, $S7, $4E, $~E
$63, $63, 563, 563, $63, 563, 5E3
$43,$43,$43,$43,$43,$43,5;::LIFO+5
1,LIFO+7,N032
5, LIFO+5
0,LIFO+7,N016
4, LIFO+5
6, LIFO+8, N08
3, LIFO+5
5, LIFO+S, N04
2, LIFO+5
4,LIFO+8,N02
1, LIFO+5
2, LIFO+8, NOI
0, LIFO+5

RTS

53

1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
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1489
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Fetch initial paq8 from 8/30 format 1.

............ * ................... **.* ...... *.**"* •• ,, •• * ... *.**** ...
OOOOOale
00000a20
00000a22
00000a24
00000a26
00000a28
00000a2b
00000.12d
OOOOOa2f
00000a31
00000.133
00000.135
00000a37
00000.139
00000a3e
00000a3e
00000.140
00000a43
00000.145
00000a47
00000.149
000OO.14b
OaOOOa4d
0000 Oa4 ~
00000.151
00000a54
OOOOOa56
00000a58
00000a5a
OCOOJa5e
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80008.162
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0::OOOa6c
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CN!4
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COR
COUNT
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IRCNT
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Symbol cross-reference
MATRIX
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MRE
HEXTC
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H016
N02
N032
NO.
NO.

NOBX
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57

READ

READ22
RED

RE::l2
RELl
RE:2
REV

REVEAL
ROWl
Row24
RS7
RS7R
RW24
SA.,

SSO
S:O
SE:
SEN
SEND
SEND22
s:::-r:
SFND
SFND2
SHADMAT

s::
S!.;:?
S!--C:J-

22p::

r

~
O.l~F

2
7
C
6
4

AS
A7

AD
07

OE

00

v••

fN

25 PB5

2x 10k

Vpp

A12

24 A9

PEl 42

1

~

eE-

All

A9 66

:~

P05

Vdd

PGM

20 CE

65

27 PB7

(+)

Iv,1

20 21 23
Peo PSI PS3

I~F~

RDS
Demodulator

VFD Module

.--- 0

=

-In.
1'"1

PC7

;;ff lOp

4.194MHz

PAO PA7 POO POI
37

11 ~ 836

35

P06 P07
2
1

~
lOOk

~

~

~
NOT USED (SEE TEXTI

2xl00k

q,

Sleep at Alam

Alarm Enobk
Alarm Outptl

Am< on OUlp'

SOFTWARE
The complete software is listed. The reset routine (START) sets up the I/O ports including the enabling of
some of the special functions available on port D. These signals (A 15, A 14, RNJ and the P02 clock) were
used during debug. The pins are not used in the final application. This also applies to all the port A pins which
are configured as outputs. External interrupts are enabled on positive edges so that the RDS clock can
interrupt the microprocessor when each data bit is available. Timer B runs as a real-time clock with interrupts
every 125 ms. Correct operation of this clock in the absence of an RDS signal requires that a 4.194 MHz
crystal be used (the trimmer on pin 6 should be adjusted for accurate timekeeping). Timer A's pre-scaler is
set up to divide by 64; this causes the idle loop to cycle at 64Hz. The reset routine also initialises the LCD
module (the display shows Mon 0 inv 00:00 until a valid group 4A is received). clears the RAM and calls a
subroutine (lNITD) to initialise the RAM locations used for displaying data.
Lines 114-118 and 193-208 are commented out as they are only relevant when de-bugging using the
EOBUG monitor (reference 2).
The idle loop (IDLE) regularly checks the local keyboard for a keypress, compares the current time with the
alarm time and performs other time-dependent functions related to the display modules and the sleep timer.
The keyboard software (KBD) scans the 4-key matrix for a keypress every 16ms. If the same key is held
pressed for 3 successive scans, it acts on this key function by calling the relevant subroutine (ALARM, .
ONOFF, SLEEP or RDS). This software also controls the repeat rate of the SLEEP and RDS keys. This rate
is set at 6Hz (after an initial 750ms delay) when the keys are used to change the alarm time and 1 Hz for
their normal function. The other keys do not repeat if held down. Table 4 shows the functions available in
each mode.
Table 4. Key functions
KEY

MODE
On/Off

Standby (Off)

Sleep

Alarm

-

mode normal (On)
mode alarm

Normal (On)
mode stndby (Off)

mode sleep (On)

Alarm OFF

Alarm ON

mode alarm ON

RT
PTY
PI
TA/TP
PIN(h)
PIN(d)
MJD
MS/DI
EON 1

mode alarm set-up
mode alarm OFF

Alarm SET UP

RDS

toggle hr/min

dec. hr/min

67

EON 11

inc. hr/min

The On/Off key uses the subroutine ONOFF to toggle between ON and standby. A port pin (3,PORTE) can
be used to control the power to the VHF radio and/or other external hardware. In standby rnode, with the
alarm disabled, the time and date are displayed. If the alarm is enabled, the alarm time is displayed. In the
ON mode the time is displayed along with the current RDS PS-name. Table 5 shows these display formats.
Table 5. Display formats
Display mode

Standby
(Off)
Normal
(On)
Alarm

Format

Alarm off
Alarm off, no CT
Alarm on
With RDS PS name
Without RDS
Alarm off
Alarm on

Thu 30 Apr 18:05
Mon o inv 0:00
0659 ALARM 18:05

RT
PTY
PI
TA&TP
PIN(hex)
PIN(decod)
MJD
MS&DI
EON
1
2

BBC Radio 4 .. ,.
News
PI code - C204
TP - 0 TA - 1
PIN no. - F480
30th at 18:00
MJ day - 48742
MIS M DI 15
BBC R3
92.10
BBC R.Sc 103.60
BBC Nwcl 96.00
BBC Scot 94.30
BBC Mtme 92.50
BBC Twed 93.50
BBC R5 909kHz
BBC Eng. 100.00
99.50
BBC R1
BBC R2
89.90

Sleep
RDS

3
4
5
6

7
8
9
10
11

BBC R4
--------

18:05
18:05

Alarm - OFF
Alarm - 6:59
sleep 60 min.

--------

The Alarm key calls the subroutine ALARM which displays the current alarm status. A second press
changes the alarm armed status. When the alarm is armed, the alarm time is displayed. In this mode the
On/Off key can be used to select either hours or minutes (indicated by flashing) and the Sleep and RDS
keys used to increment and decrement the settings. If the alarm has triggered then the first press of any
key cancels it. The alarm display has one of the two alarm formats shown in table 5 according to whether
or not the alarm is armed. As all the keys have a special function in the alarm mode the only way to exit
this mode is to wait for a timeout. If no keys are pressed for 5 seconds, the mode returns to normal.
The Sleep key controls the sleep timer. If the decoder is in the standby mode the first press of Sleep
switches it on and initialises the sleep time to 60 minutes. When the sleep timer is running, this is indicated
by a flashing decimal point in the right-most character of the display modules. Subsequent presses of the
Sleep key decrement the time remaining by 5 minutes. When the sleep time has elapsed, the decoder
returns to standby. In the alarm set-up mode this key decrements the alarm time.

68

The RDS key uses subroutine RDS to step through the various RDS data which can be displayed. Holding
down this key steps through the displays at 1Hz. The displays are RT (scrolling). PTY, PI. TNTP, PIN (hex),
PIN (decoded). MJD, MS/DI and EON (11 networks) as shown in table 5. In the alarm set-up mode this key
increments the alarm time.
The timer interrupt routine (TINTB) updates the RT scrolling pointers (DISP1 and DISP2). These pointers are
incremented regularly whether or not an RT display is active. In this way, the software can be easily
converted to using a 2-line LCD module in which the top line is the normal display of PS-name and time and
the lower line a permanent display of scrolling RT. The timer interrupt also decrements the sleep timer and
updates the RAM locations used to store hours, minutes, seconds and eighth-seconds. All RDS data
(except date and time) is cleared by this routine if no valid RDS data is detected for a period of 10 seconds.

SYNDROME AND CONFIDENCE
Hardware interrupts are vectored to jump to SDATA where serial data is received from the RDS
demodulator. The clock edge causes an interrupt and the first instruction reads the data into the carry bit
of the condition code register. The bit is shifted into a 4-byte RAM register and the matrix multiplication
performed. The state of flag O,STAT2, determines if the multiplication is to take place after every bit or only
after all 26 bits have arrived. The multiplication is performed using two EOR instructions for every bit (two
are required as the 1O-bit syndrome requires two bytes). As the top of the matrix (see figure 2) is the unity
matrix, the first 10 bits are transferred directly into the syndrome RAM locations (SYN). This, the omission
of any EOR #$00 instructions, the reordering of the bits and the use of the index register for temporary
storage help to reduce the length of inline code in this routine. The routine could be shortened by using a
loop but this would incur an unacceptable penalty in execution time. Microprocessors with two
accumulators would find this task a lot simpler and quicker but an MC68HC05EO, at half its maximum
speed, can easily perform the calculation in the required time.
After the multiplication has been performed the resultant 1Q-bit number is compared with the allowed
syndromes (see table 3). The variable LEV records the current block level. It is initially zero but incremented
each time a valid syndrome is found. When it is zero only syndrome A is accepted, if this is found then
syndrome B is expected 26 bits later so when LEV is one only syndrome B is accepted. If an invalid
syndrome is found LEV is cleared, the syndrome confioence level CONF is decremented and the interrupt
ended.
When a valid syndrome is found, CONF in increased by 4 and the 16 data bits saved in the relevant bytes
of TMPGRP. If the valid syndrome is type D then a complete group has been received and all 8 bytes are
transferred to the 8 RAM locations at GROUP. This double buffer means that the data in GROUP can be
used while interrupts are overwriting TMPGRP with new data.
The confidence level CONF is used to decide what should be done if the data becomes unreliable due to a
poor RF input to the receiver. When the first valid syndrome is found it is initialised to 42. Subsequent valid
syndromes increment it by four and invalid ones decrement it by 1. If CONF falls below 41, then it is
assumed that synchronisation has been lost and a bit-by-bit re-synchronisation is carried out. If it falls below
10, the signal is deemed unacceptable and the displays are re-initialised. The confidence level is not
incremented by the detection of a valid syndrome if it is higher than 56.

69

GROUPS HANDLED
If a complete group has been received the data can be processed. The buffering used would allow this to
be done outside the interrupt but in this case there is sufficient time to do it within the interrupt. The PI
code is checked to see if it has changed. If it has changed the displays are initialised. In an application using
the AF capability of RDS, more use would be made of the PI code.
Next PTY and TP are updated and the group type identified. Group types OA. DB, lA. 1B, 2A. 4A. l4A and
15B are handled. Table 6 shows the type of information contained in each group and table 7 shows the
detailed structure of the groups actually used.

Table 6, RDS Groups
Features

Group
All

0
1
2

3
4A
5
6
14
15B

PI, PTY, TP
TA. 01, MS, PS, AF
PIN
RT
ON (replaced by EON)
CT
TDC
INH
EON
TA. 01, MS

Group 0 & 158
As AF data is not handled, there is no difference in the treatment of groups OA and DB. PS data is extracted
and placed in RAM according to the address bits in block 2 (see table 7). TA, 01 and MS data are then read,
01 is sent a single bit at a time and uses the same address bits as the PS name to determine which of the
four bits is being updated. Groups of type 15B also contains all this switching information. They are used
to increase the repetition rate of this data but contain no PS or AF information.

Group 1
Group types 1A and 1B contain the same data except for the repetition of the PI code in type 1B. The PIN
data is recovered and saved in RAM. This is intended for future use to control external hardware, for
example a tape recorder. This would facilitate the unattended recording of a pre-selected program. At
present this application simply allows the display of PIN data both in its raw hexadecimal form and fully
decoded to day-of-month and time. Full use of PI N data would require continuously comparing the PIN dayof-month and time with the current day-of-month and time enabling an I/O pin to be switched when there
is a match.

Group2A
RT data from blocks 3 and 4 is written to RAM according to the address included in block 2. There are
four address bits and four ASCII encoded bytes giving the possibility of 64 characters. If the Text AlB flag
changes state, the RT area in RAM is cleared, indicating that the message has changed. Group 2B is not
handled as it is rarely, if ever, used.

70

Group 4A

Two of the more complex tasks to be performed are required by the CT calculations for group 4A. These
are for the local time difference and the conversion of the MJD number into a recognisable date.
The broadcast time is Universal Coordinated Time (UTC). effectively the same as GMT. Time differences
from UTC, including summer (daylight saving) time, are sent as an offset of up to +/- 12 hours in half-hour
increments.
The software includes 4-function, 9-digit integral BCD arithmetic which is used to decode the date from the
MJD number using the formulae:
Y'

intl(MJD-15078.2)/365.25)

M'

int[(MJD-14956.1-int{Y'x365.25})/306001)

Day

MJD-14956-int(Y'x365.25) int(M'x30.6001)

If M'=14 or M'=15,
then K=1;
else K=O
Year

y'+K

Month

M'-1-12K

Group 14A

This group contains EON data. A large amount of information can be sent using this group, and it can take
up to two minutes for all the data to arrive after the radio has been retuned. This application saves the PI
code, PS name and principal frequency of up to 11 networks although more networks, each with many
frequencies, and other data (e.g. PTY(ON). PIN(ON). TA(ON) etc.) may be sent. Table 5 shows the format
of the EON display. All the information shown is real data from the Black Hill transmitter in central Scotland.
Displays

The software drives both a parallel LCD module (based on an HD44780 driver with or without an HD441 00)
and a serial VFD module (based on an MSC7128 driver) io give a choice of display types. The displays show
the same data (within the limitations of their character ROMs).
The display routine (MOD) is executed in the idle loop if flag 3,STAT2 is set. It is set every 125ms by timer
B interrupts. If flag 4,STAT2 is set. the display is initialised, indicating no valid RDS data. The LCD module
is then updated with new data. Each time anything is written to the module, the subroutine WAIT is used
before the write is executed; this checks that the controller In the module is not busy. This is indicated by
a low on bit 7, so bit 7 on port C should have a pull-down resistor to satisfy this condition if an LCD module
is not being used.

71

Table 7.

bit(s)

Group 0 and
158

Group 1

~

Group 2A

Group 4A

Group 14A

PI
code

PI
code

PI
code

PI
code

PI
code

Block 3

Block 2

Block 1

15-12:
11 :
10:
9-5:
4:
3:
2:
1-0:

group no.
group type
TP flag
PTY code
TAflag
M/S bit
01 bit
PS/OI address

15-12:
11 :
10:
9-5:
4-0:

0001
group type
TP flag
PTY code
not used

chck 8

15-12:
11:
10:
9-5:
4:
3-0:

0010
0
TP flag
PTY code
text AlB flag
text address

chck 8

chck A

15-12:
11:
10:
9-5:
4-2:
1-0:

0100
0
TP flag
PTY code
not used
MJO (16-15)

chckA

15-12:
11:
10:
9-5:
4:
3-0:

1110
0
TP flag
PTY code
TP (On) flag
usage code

chck A

chck A

chck A

Block 4

use

------

---

AF
chck 8
(PI code in type 08 and 1581

not used
(PI code

In

type 18)

RT
2 ASCII characters

chck
C
or

C'

chck
C
or

C'

chck
C

CT

chck 8

15-1 : MJO (14-0)
0: hour (4)

PS name
(as block 2 for 158)

chck

0

PIN data
15-11 : day-of-month
10-6: hour
5-0: minute

RT
2 ASCII characters

chck

0

chck

0

CT
chck
C

15-12:
11-6:
5:
4-0:

hour (3-0)
minute (5-0)
offset sense
offset (4-0)

chck

0

EON information

chck B

'----

code: 0-3:
4:
5-9:
10-11 :
12-15:

PS
AF
AF (map)
not used
not imp.

chck
C

PI (On)

chck

0

The listing is shown for use with a divide by 8 multiplexing LCD module. This module will normally contain
an HD44780 and an HD441 00.

If a divide by 16 module (HD44780 only) is to be used then line 1294 should be replaced by line 1293 and
line 1371 commented out to include the execution of the code on lines 1379 to 1392.
The different display formats are selected by checking the various flags and the relevant routine executed.
The normal display permanently shows PS name and time. As the locations in RAM used for hours and
minutes contain binary numbers they are converted to BCD before being written to the relevant bytes in
DISP. Once all 16 bytes in DISP have been loaded, a loop is used to send the data to the LCD module.
The VFD routine sends the same data as is shown on the LCD module to the serial VFD module. The display
driver used has a different character set from the standard ASCII set used by the LCD module. The table
VTAB is used to convert ASCII data into the required character in the VFD module. The small table INITF is
used to send the required initialisation bytes to the VFD module. This module does not require a busy check
but does require a delay between successive bytes. This is satisfied by the wait loop within the serial
output loop VFDF.
Alarm functions
The alarm time can be entered as described above. If the alarm is enabled (alarm time displayed on first·
press of the ALARM key, and permanently displayed in standby mode) then, at the alarm time, the auxiliary
control line will go high. This can be used to control external hardware, for example to switch on the VHF
radio supplying the RDS data. If the auxiliary line is already high (decoder fully on or on via the sleep timer),
then it simply stays high. The operation of the sleep timer is not affected if bit 0 of port E is high. If this
I/O line is low at the alarm time, then the sleep timer is activated for an hour. This takes place whether the
decoder was previously on, off, or running the sleep timer, and has the effect of switching the auxiliary line
Iowan hour after the alarm time, regardless of its condition prior to the alarm.
At the alarm time the alarm output will also be activated (active low) as long as it is enabled by bit 1 of port
E being held low. This is intended to drive an alarm sounder. When this output is active, a press of any key
cancels it until the next alarm. This cancellation does not affect the auxiliary output.

REFERENCES
EBU Technical Document 3244, Specifications of the Radio Data System RDS for VHF/FM Sound
Broadcasting.
2 AN459, A Monitor for the MC68HC05EO

APPENDIX (listing) follows

73

0001
0002
0003
0004
0005
0006
0007
0008
00090000
00100001
00110002
00120003
0013 0004
00140005
00150006
00160007
00170008
00180009
0019 OODa
0020 OOOb
0021 DaDe
0022 OOOe
00230012
0024
00250009
0026
00270030
0028
00290030
00300039
00310042
0032 004b
0033 00~4
0034 OOSd
00350066
0036006f
00370C71
00380073
00390074
0040007'1
0041 0018
004200'19
0043 007a
0044 007e
00450086
0046008e
004700Sf
00480091
00490093
00500094
00510095
00520096
005)0098
00540099
0055 009a
0056009b
0057 00ge
0058 0090.
005900ge
0060009f
0061 OOaO
006200a1
0063 0032
0064 00a]
0065 00a4
0066 00a5
0067 00a6
0068 00a7
0069 00a8
0070 00a9
0071 OOan
0072 00at>
0013 OOac
0074 OOad
007S OOae
0076 OOaf
0077 OObO
0078 OObl
007900cl
0080
0081 OOd
0082
0083
0084
0085
0086
0087 OOca
0088
0089
0090
0091
0092
0093
0094 OOcb
0095
0096
0097
0098
0099
0100
0101
0102
0103 OOce
0104 ODed
010500[[
0106
01070100
0108
01090100
01100145

....................................................
HC0:,EO RfIS

De~xiE>r,

l~th F'elJn.JiUj'

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Check fo"[ syndrccnes A, B, ICli< ), lCi< IDA lEV O

8NE TRYB e BRS'" 3. 'n«FCRP. 2, TRYCD 11)A CMP 8NE CDA CMP SYNd BAA CDA eMP 8NE lIlA CMP BLeCK 3 'NPE A 1$5c "''''' SYN IS02 '" SYNd .sec BLlX:K 3 TYPE B "''''' ISO) SYN '"........................................................... "'" VALID Invalld syndroue nandlwg, check for blu:k 4 and save group cl;;t(l If valld .................................................... turV lEV RES1'ART AT BUX"K 1 "'" caw 141 CONFIDENCE 41 OR GREATffi BHS OCli< DEJ::C 1j,S1'AT2 BIT BY BIT S'(N[.RCloIE CHEL'K Oil' 010 eLR o

R FOR FOR FOR roR OOR 11)A STA InA STA TIed, block Js not used IN!lX ...;ROOP PI WDX GRUJP.l CCffi'ARE PI WITH I'REVIUJS 1'1+1 'El;) erYL lIlA grA lIlA STA GRalP PI JSR JSR CLRfX>j BS'" DIF'Frnrnr, SAVE N&I PI GRaJP .. l PI .. 1 CLTR 4, STAn CLEAR B.JN. TRANSIENTS AND INITIALISE DISPLAY DATA tp:iate PrY and TP All block 2£ Ul>ecL /lot block 4 (grp lSB) PrYL lIlA STA BRCLR BS'" BAA TPLI TPL BCLF IDA f<1R GRClJP.2 ITHPI 2, ITMPl. TPI..1 3.SJ'AT3 TPL 3. SfAT 3 GfCH 1. STAT] mITO WA GRCUP.3 AND I$OF BeLR GROJP2A PRCC4 104" 1050 eS64 b6 89 1051 eS66 a4 Of 1052 eS68 48 1053 1054 1055 1056 e569 48 e56a 97 e56b b6 e56d d7 1057 e570 b6 1058 eS72 d7 1059 eS75 b6 1060 eS77 d7 1061 e57a b6 1062 e57e d7 1063 e57f ee 9a 01 OS 9b 01 06 8e 01 07 8d 01 08 e6 18 !<::H GRWP 2A RT LSLA LSLA TAX WA srA lIlA srA lIlA rJrA illA rJrA ,'MP GRCfJP.4 RJ'.S.X GRUJP.S RT.6.X GRClJP+6 R!'+7.X GReJJP.7 RT.8.X 0l!Tl 83 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 lOBI 10B2 10B3 10S4 lOBS 1086 10B7 lOBS 10B9 1090 1091 1092 109). 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 Precess grOOJp 4A (CI') eS82 al 40 eSS4 27 03 eS86 ee e6 Ib PRF' SlA. MIN CLR SEC CLR TIl8 BSE'!' 6, STAT) ;.o;:xx5432 )()(xxS432 xxx:"4321 xxxS4321 xx543210 --543210 x 1 x 0 x x UPDATE KJV l..ocal time dlfferenee adJustment, lDCAL UlA [.SIA eSb7 48 eSb9 27 Se BE>;) e5ba 24 Bee n 1119 1120 1121 1122 112) 1124 eSbf e5cO eSc! eSc3 eScs eSe7 1125 eSc9 ,126 e5eb 1127 e5cd 1128 1129 eScf 1130 eSdO 1131 eSd2 E32 eSdJ 1133 eSd4 1134 eSd6 11J5 e5d8 1136 11j7 eSda. 1138 eSdc 1139 eSde 1140 eSeO 44 97 24 Oe b6 9b aO Ie 2a 04 ab 3e 3a 9c b7 9b 9f bO 43 4e 2a ab b7 3d 26 3d 26 llH e5e2 3a 1142 e5e4 3a 1143 eSe.6 3a :144 e5e8 20 eSt7 e5f':! e5 fb e5fd e5ff e(iOl e(i03 e604 e606 e608 e60a e60c e60e e610 e612 e614 e(i16 e6lS e61a eo NOTHN HOURS n! x 1/2 HOUR ", MIN YES 'lO SlfB'rRAC"T )0 KlturES LT60 .60 lNDERFLfW }\DD 00:: CUR AND SUBI'RAcr 1 HCUR LT60 srA MIN NCmlN TXA SUB BPL INCA 14 BPL 18 IIDD srA 76 08 75 02 74 75 76 2e TST TIl TT2 YES ? ADD 60 MIlVI'ES NEGATIVE HOJR (f'FSE'!' MUJJS ure HOURS W'l.CNG WAY rot.ND >Xl CQ>1PLE}!ENT AND JNCFrnENT t.NOClIE MSB WI LL UNDrnF'I.£W ? YES DECREMENT MS BIT D£Cru>!ENr MSB D£Cru>!ENr [.SB 00:: 00:: 00:: BPA ZOM srA fOS LSRA BRA l.SRA l.SPA [.SRA TAA Oe Ie 9b 3b 04 3c 9c 9b 9f bb 11.1 23 11.0 3c 26 3c 26 3c b7 13 Bee CDA ADJUSl'MENI' ? YES. POS IT IVE -: 00. NEGATIVE CU2 U53 :"1:'4 1155 ll.56 1157 1158 1159 1160 1161 1162 1163 1164 1165 116& 11&7 11&8 11&9 1170 1171 1172 1173 1174 1175 IS40 GRP' PRCC14 BEl;) 01 74 1111 e5b5 b6 8d 1112 1113 1114 1115 1116 1117 JMP Q'lP . Ml INC WR o

A lIDO ". """'., HOUR OFFS£1' ADD vrc HOURS CNE!lFtJ:>' ? YES, SUBTRAC'T 24 HOJRS AND ArlD A DAY ADOON EMJD+l APOON BMJD CUR I. SlAT2 c,'RCl)P HANDlED, CJ...E.IlJ< FLAG "" 84 ll77 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 119) 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 120S 1209 1210 1211 1212 1213 1214 1215 1216 1217 ~ ................ ...................................... ~ .................................................... PrOCei;.IO group 14 (Er:'tl). e61b al eO e61d 27 0) e6lf ee e6 e622 e624 e626 e629 e62b e62d e6)0 e6)2 )f be d6 bl 26 d6 bl 26 PR:C14 00> BEQ JMP b) 9S 9S 01 4S 8e 69 01 46 Bd 62 GRP14l1 [oPIL WX W' b6 a4 al 24 48 bb 97 b6 d7 b6 d7 20 Ern. X (''RWP.6 8NE NUfH C>!P El:.t'.LX GRClJP.7 ENE NOrH W' GRooP.) IS10 U)A 89 Of 04 10 ITMP1 ITMP1 C>!P AND e634 e6)6 e63S e6)a e63c e63d e6)f e640 e642 e645 e647 e64a ISEO GRPHA am WX ITMP1 Sf> FJJN.11,X !JXl< F'Cl<. PI CO[lE IN TABLE TP (CN), NOI' USEIl lDA AND GRClJP.) I$OF' PI COOE FUND C>!P 14 PS ? IlIlS NPS LSLA 9S ADD ITMP1 TAX Sa 01 47 Sb 01 4S ee ill. E'r' e64c al 04 e64e 26 )4 GRClJP.4 ECN.2,X GRooP.:' EON.), X lDA srA BRA cvr1 C>!P IlNE 'T'RYPIN e650 b6 8a SAVE 2 PS-N1\ME CHARAC"rERS " CRClJP.4 YES, METHOD A 121E! 1219 1220 1221 1222 122) 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 e652 e654 e656 e659 e65b e65d e660 e662 e664 e666 e669 e66b e66e al 26 d6 al 27 d6 al 26 a6 d7 b6 d7 20 fa la 01 51 ff 56 01 53 eM!' ff OIP ENE om E'r' W' E'r' 1250 ECN.14,X GROJPt5 E.U*.15,X e670 e672 e674 e676 e678 e67a e67d e67f e682 al 25 al 22 be d7 b6 d7 20 eO IlNE W' c>

BRA *TRYPI'Y TRYPIN e696 e698 e69a e69c e69f e6al e6a4 al 26 b6 d7 b6 d7 20 wrH e6a6 e6a8 e6aa e6ae e6ae e6bO b(; ab b7 al 27 ff 95 10 95 bO 03 cc e6 24 e6b3 13 e9 e6b5 80 ISOD TRYPIN GR(lJP.4 CMP BNE lllX lll. Sl'A ill. ITA BRA Oe 8e 01 45 8d 01 46 Od l$eF '224 rooLS 1249 =LS ITMPI EDN.12,X GRooP.:, EDNd3,X our2 illX srA ill. alOe 26 2b be 95 b6 Sa d7 01 4f b6 Bb d7 01 SO 20 1d EON.H,X BRA BIll e684 e6S6 e688 e6Sa e68e eMf e691 e694 l$eF cur2 OIP BCD CK!' TOOLS 1250 f>A JSR JSR LOA LOA JSR JSR illA JSR 4.SI'AT2.NXL lNITO 4.STAT2 WAIT ISOC CUXK WAlT IS,A 1$30 e6c9 e6eb e6ee e6d.1 e6d3 a6 )0 cd e:b 65 ..TCH IT SI'IINDBY ~ YES. SlEEP DISPLAY ~ NO. AI...ARM DISPLAY ~ NO. t>l.1RMAL STANDBY DISPLAY RDS DISPlAYS? PrY '(><1 n ~';t' ['!TAF " ENE N""t'IN: JSR BRA R:","1 O1P oS "''E 0<, O1P BNE JSR BRA JSR BRA ~)F':t:: i"W HEX N1.::N;: ~)F~ P:t-.: • [lIl.Y ANT' TIME RCW: 06 NKJD rKJI' ><1D P NHSD CMSD MIS!. Dr RG<1 DEn' PCWl "'ITS JS' BRA e735 O~ cb 05 e738 cd ea ee e7)b 20 Ob Sf cd 14 e6 al 26 a6 cd 5c a3 26 20 3. FORTE, TRYRT 2, SI'AT4. SLPO NPI BNE ens cd ea 25 e72b 20 Ib e748 e749 e74c e74e e7S0 e7S2 e754 e756 e759 e7Sa e75c e75e CUX"K lNE JSR BRA 20 e745 cd e9 WAIT 1$80 12 JSR B!1P CJ'<: JSR a: v4 26 OS cd e9 "'2 2C Jb e72d 05 c9 05 e730 cd e8 4a e733 20 13 AND CI..EAR FLAG JS' BRA 03 OS e9 Sa 4.l. eb 0] SHOJUl DISPALY BE.: INITIALISrn " YES. WIT NlWl BRCLR :<, STAT4.NRMD JSR B!< JSIl [f eM!' WAIT 2,FORJ'D DISP.X 1 SIT 02 2d eb 65 BN'E OOK LOA JSR CUXK MEr illA CO, SLEEP TIMER DISP[.AY ? R(W1 ~ITE u>\TA GET' A BYTE 1$2D SEND IT 1'0 MCUJLE 1NC~ 10 eb Ie ", .................................................... CPX 1M BAA DONE 1£D VF'D REMJVE F'OR I 16 LCD;; Adciltlonal blt& fc>r 116 J£D m::dules .................................................... enD e76] e765 e768 e769 e76c e76e e770 e772 e774 e776 e779 e77a e77c cd eb 6c a6 a8 cd eb 65 Sf 0:1 eb 6c 14 0) e6 b9 al [ f 26 02 a6 2d cd eb 65 Sc a3 08 26 eb LCD401 LCD" JSP illA JSR CCR>< JSR ctLCK BSEr 2. PORrO illA CMP BNE 001<2 ISAB 1i..l40 SEMI IT TO MC{JULE '~IT DISP+8.X OSIT vmrrE rYl-TA GET A BYTE LD>. C"" 1$2D JSR CUCK SEND IT TO MOflVLE .8 DONE' lNCX CPI. ENE "'''' 1 86 1394 1395 1396 1397 1398 1399 1400 1401 1402 140) 1404 1405 1406 1407 1408 1409 1410 1411 1412 14D 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 14)1 1432 1433 1434 1435 14)6 14)7 1438 1439 1440 1441 1442 1443 1444 e77e D 01 e7S0 10 01 e7S2 17 01 e784 e785 e788 e78a e78c e7ge 5f d6 bf ad a) 26 e790 e791 e793 e795 e797 e799 e79b e79d e7ge e7al e7a3 e7a5 Sf bf e6 al 26 a6 a4 97 d6 ad a) VFO DIS5 IllA srx BSR a7 W03 bi ff 02 2d 7f OA.TA ), roRTB CLCCK HIGH ? ENABlE u:w rnITF, X WJ VFDL SAVEINDE); SEND VFD SET -UP BYTES CPX n 00: DISS FNE IllA AND T"" IllA 00 ae 09 10 08 02 01 01 01 01 srx IllA CMP BSP r..a< ? 1, roRTB 0, roRTB l.ASf BYTE -: SEND 16 CHARJiCTER BYTES CLRJ( 26 ea ae 44 24 12 11 10 13 5a 26 ae Sa 26 be 5c BS'" CLRX e7 c5 a7 20 07 f5 e7a7 16 01 e7a9 11 01 e7ab 81 e7ac e7ae e7af e7bl e7bJ e7b5 .,,7b7 e7b9 e7ba e70c e7be e7bf e7el e7c3 e7c4 BeU< OCU< WJ SAVEINDD< DISP,X ISF'F' >rnFP IS2D 1$7F' ASCII VfAE,X NJ WAIT 200uS RESfORE nmEX INCX ras 81 e7cS aO Of bO 00 80 00 90 SAO. SOF'. $BO, INITF sao, S80. S00, $'10 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 ~476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 Nornal display (PS arrl t)JTte) e7cc e7ee e7dO e7d2 .,,7d4 e7d6 e7d9 e7dc a6 b7 b7 b7 a6 03 05 b7 20 bl ba e7de e7df e7el e7e3 e7e4 e7e6 5f e6 e7 5c a3 23 e7e8 e7ea e7ed e7ef .,,7f1 e7f3 e7f5 e7f7 e7f9 e7 fc e7fe e800 e802 e805 e807 e809 b6 9c eb 84 a) }O 26 02 ae 20 bf Cb b7 be b6 9b cd eb 84 NCru-ID cO :ie cb 05 99 02 cO INDICATE SlEEP TIMER RlNNIN:: BRCCR BRCCR IT STA TIP1 el b2 PSN,Y. MPS ~ISP+l be bf 20 99 02 3a GET PS NAME ,X n 07 f7 MPS OJ oj bf b7 a6 05 a6 b7 LI:l'< STA STA STA lllA wz "'IN LDA JSR CPX £WE WX STX srA CDA JSR srx srA CSIX b:l LDA BReW< 1$30 ONZ 1$20 DISPdO DISP.l1 MIN COCO DISP.13 DISP.t4 1$20 ax 11'A 2,TIl8, I$)A STA DISPd2 ras 81 GET TIME OJR COCD O. 5 Hz FLASH ING CO[£N Clear d15play tran51ent Elags e80a e80c e80e e810 e812 eS14 e816 e818 11 15 3f 17 Ib 1£ 15 81 cb c9 af cb cb cb cb CLTR ECLF cu;:1tR (1ISPLAY TRAN.SIEN'J' F'LAC OClJ< N;:l'J' RT DISPlJ>.Y CLR CL.EAf( RDS OCLR BeLR EClF EClJ< N:JT .r..LARM DISPLAY N:l'J' ALARM SET-ln' DISPLAY INT)f:." NCJr RDS DISPLAYS mr SL.EEP TIMER DISPLAY RrS 87 1!100 1!101 1!102 150) 1504 1505 1506 1507 1508 150' 1510 1511 1512 15ll 1514 1!115 1516 1517 1518 151' 1520 1521 1522 152) 1524 1525 1526 1527 1528 1529 .................................................... PrY display .................................................... e81' e8lb e81d e81f e820 e822 e82) e82S e827 ee2' aB2e e82e e8)0 e8)2 e8)' e8)6 e8)8 e8)a be Be 10 25 01 !If 0116 10 42 b7 a8 If a7 be 0118 d6 ec ae be 0117 e7 hI )c a8 )c 0117 b6 0117 0111 10 25 ed 81 BID ""'" PrY 11' .... WI LOA "".>' ID' IDA .... Pl'V'l'.' lDX WI INC INC .... WI o

Ir la 20 Ib b7 5t e6 e7 b2 bl """' Of f7 aB eO IDA "'" IIRCLR INC INC ",OS ,"Pl IDA o

ILPI BS'" BAA !ClJ> !IT' CUV: IDA "'. W:.( CPX IN£ ID. 5e a) 26 b6 b7 81 lDX CHI' "". "fA RrS DiSP2 RI'-1.X '$20 '" rmsp 5. S"l'AT2.F'SP DISPI DISP2 DISP2 .69 "'D4 "'"'" SPACE? YES. FIRSI' ct£ ? SlCIP THIS CH: "'. ENI"! CE' RT ElJFF'El"t 1-1:,. G£T NEXT CfiAAA(."I'El"t r..S7AT2 F!f.'Z; SP,t£.·E. SET F':..4G ... CCl'I'I' S.S'r'AT2 rvr A SPACE. CILAA F:.AG [,ISP.l.X DISP.X ""VE i>ES'T . lIS I:"PI LEPr eN: Pl.ACE DISP.!5 ArlD f'&l S;..:.;r.. CHARAC"I'E}! ~ ~HAf<. (WAS HOC2; .................................................... .................................................... Starldby display. e869 08 cb 4f e86e b6 73 eB6e e86£ 1568 e071 1569 e872 1570 e87~ 1571 eOn 1572 e87a 1573 eB7c 1574 eB7f 1575 e881 1576 e&BJ 1577 eB85 IS78 e887 1579 eBB9 15BO e88b 15Bl 88Bd 1582 e88t 158) e891 1584 e89) 1585 eB95 1586 e897 1587 e899 1588 889b 158' e8\1d 15\10 e89f 151ll e8aO 1592 e8a2 1!>9) e91') 1594 e8a5 15\15 e8a6 1596 e8a7 1597 e8a9 159B e8aa 1599 dad 1600 e8af 1601 e8b2 1602 e8b4 160) e8b7 1604 e9b9' 1~6'1 ID. CPX CUO< IDA MIS display. 1~)0 15)1 15)2 15)) 15)4 15)5 15)6 1537 1538 15)9 15.0 11)41 1542 154) 1544 IS45 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 155B 1559 1560 1561 1562 156) 1564 1565 1566 PI'YD ill) 48 hb 97 d6 b7 d6 b7 d6 b7 a6 b7 b7 b7 bf.. ab b7 b6 27 ab ab b7 be b6 27 \If ab 97 bE 9f 4B bb 97 d6 b7 d6 b7 d6 b7 20 "''''0 ec: 72 bl ec: 73 b2 ec: 74 b3 20 b4 b7 bb 72 )0 b6 71 02 10 20 I» 70 6f 04 ,,",..-r UlA I..SLA 1A.": IDA ST" IDA sr. ec: fIB b\l eo:: 89 b6I Id tiAy CF WiEI< sr. IDA sr. '~)O DISP.5 IDA IU< BOlO AD020 AOO "'. lllX IDA "'HZ ~: DISP.l .rc> ADD ""'20 [NAME. UU'1'JE.l.Y. "'"'.. IS10 1$20 DISP.. 4 IW'''' IM'H .m ""'z ADO 110 sr. wa l.SlA ... TXA ADO TAX eo:: 87 ~ D:SP ~NAME-02.X TAX be ~'. r!ISP.2 1$20 rJISP.) DISP.f., DISP.lO D".t4.1 WI Oa a8 ALARM AAJ£II ? LOA "'. TXA a.8 4.STA14.AUW\ 1('w ""0 71 l.C>' sr. IDA sr. U~ sr. BAA D1.7r: If' Zrn0 USE A SPACE iF NOI' MAKE ASC II KmH. LSD MJNl'H. MSD r-tlAME·j.X DISPo7 toIIlAM£-2.X t>lSP .. 8 1f"W(E-1, x DISP.9 "'''''' 88 1606 1607 1609 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 16JO 1631 1632 1633 1634 1635 1636 16)7 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 166.3 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 16B6 1687 168B 1689 1690 1691 1692 1693 1694 1695 1696 1697 169B 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1117 171B 1719 1720 .................................................... Stllndby (alann arnted~ diGplay .................................................... efibb eBbd e8cO e8c2 eBc4 eBc6 e8c9 e8cb e8cd e8ce e8dl e8dJ e8d4 e8d6 e8dB eBda e8dd eBdf e8el eBe) e8e5 e8e7 e8e9 e8ec eflee eBfO eB f2 e8f5 e8f7 e8f9 b6 cd bf b7 b6 cd bf b7 5f d6 e7 5c a3 23 b6 cd a3 26 ae bf b7 b6 cd bf b7 a6 05 a6 b7 81 ge eb 84 bl 1>2 9d eb 84 b3 b4 ALI> III CPX BLS illA BED 48 DWP PI PlNV SPLIT DISP>ll DISP>l2 PhI SPLIT mSf'.13 DISf'd4 JSR STX STA be W 90 eb 48 LOA JSR be srx bE Sf A RTS PUN ~ .... ... ....... .................................. ~ ~ " ~ ~ Alarm di5play .................................................... e9la e9lb e91e e920 e921 e923 e92:S e928 e92a e92c e92e eg31 e933 e935 e937 e939 e93b e93d e940 e942 e944 e947 e94a e94c e94f eg5l eg53 e.955 e.957 eg59 Sf d6 e7 5c a3 23 09 a6 b7 b6 cd a3 26 ae bE b7 b6 cd bE b7 Ob OS a6 Oc b7 b7 20 b7 b7 81 eb f2 bl ALl>ID ALOP CLRX YES tnA STA ALARMS. X DISP.X INC)( Of CP;'; BLS BRCLF tnA STA tnA f6 cb 31 }a W ge eb B4 30 02 20 bb be 9d eb 84 JSR CPY, EM: LDX nn STA U STA BRCLF BRCLR LIlA BRSOT STA D1SP.13 DISP,14 5,SI'AT4,A.r.,a"2 2,TH8,AJ.££2 IS20 s-rx be bf cb 12 99 Of 20 cb 06 be bf 04 U:> be 115 ALLW 4, SI'AT4,A'J;F2 1$3A DISP.12 "'. F'LASH Ml!VI'ES YEs. FLASH HClJRS AWe2 .. ~""'"'''''''''''''''''''''''''''''''''''''''''' TA 0. TP flagG dlSpl",y ............. ...................................... ~ e95a e95b e95e e960 e96l e963 e965 e967 e96a e96c e96f e971 5f d6 e7 Sc a3 23 a6 07 b7 05 b7 81 ec 12 bi O1TAP BLOP CLRX L['A '''fA TAPST, X DIS~'. X IN(~ Of f6 )1 ca 02 b7 ca 02 bE TPlL>< TAw.; CPX BLS LOA BRCLR STA BRCLR Sf A Ii ~, 841P IS:!1 3.S"I'AT).TPI..LW OISP .. 6 2.SJ'AT3,TAti:loJ DlSP.14 T1' FLAG HIGH YES. DIS1'l.A.Y TA FlA.G HIGH YES. OISPl.A,Y RrS 89 1122 1123 1124 1125 1726 1127 1128 1729 1730 1731 1732 17)) 1734 1735 1736 1737 1738 1139 1740 1741 1142 1743 1744 1745 1746 1747 1748 1749 1750 17S1 1752 1753 17S4 175S 1756 1757 1758 1759 1760 1761 1762 176) 1764 176S 1766 1767 1768 1769 1170 1771 1172 1773 1774 177S 1776 17,.., 1778 1779 1180 1181 1182 1183 1784 178S 1186 1787 1788 1789 1190 1191 1792 119) 1794 119S 1196 1797 1198 1199 1800 1801 1802 1803 1804 180S 1806 1807 1808 1809 1810 1811 1812 1813 1814 1915 1816 1917 1818 1819 U2» 1921 1822 182) 1824 182S 1826 1827 1&2& 1829 18)0 .................................................... PIN display£:. .................................................... e912 e973 e976 e978 e979 e97b e97d e97f e981 e984 e986 e988 e98a e98d e98f e991 Sf d6 e7 5e .3 23 b6 27 cd bf b7 b6 eel bf b7 81 e992 e993 e996 e998 e999 e99b e99d e99f e9a1 e9a2 e9a3 e9a4 e9a7 e9.9 e9ab e9ad e9af e9b1 e9b) e9bS e9b7 e9b9 e9bb e9bd e9bf e9el e9r:J e9d ege7 ege\l egeb eged e9cf e9dl e9d3 e9d5 e9d7 e9d9 e9db e9cH e9df e9eO ege1 e9e2 ege3 e9e6 e9eS e9ea e9ee e9ee e9 fl e9fl e9f5 Sf d6 e7 Se .3 23 b6 27 44 44 44 cd aJ 26 ae bf b7 a3 27 a1 26 a6 b7 a6 b7 al 26 a6 bl a6 ""])Il e<: 22 PLOP bl CUI>< 11\\ .,.. INC.. Of f6 91 10 b::I 92 eb 48 be bf e<: 32 b1 CPX m Bl.S IDA BEQ JS. PWP PIN PI_ SPLIT DISP.. U DISP.. 12 PIN. 1 SPLIT DISP.13 [lISP.14 .,.. .,.. eb 48 be ~'INSTI. l1lA JS. .,...,.. PIlON RrS OPlN2 PlDP' CL.RX .,.. lDA X DISP,>: PINST2.>: DISP.>: lNCX CPX Of f6 91 to eb 84 30 02 20 b3 b4 31 24 )1 08 73 bS 74 b6 32 »8 6e b!. 64 bi b6 al :n 26 08 a6 '72 b7 b5 a6 64 b7 b6 b6 91 a4 '07 be 92 58 49 S8 49 cd eb 84 bf btl b7 Ix: b6 92 a4 3f cd eb 84 bf be b7 bf 81 BLS lDA .." l.SRA l.SRA l.SRA JSR COC[l LOX ""'0 1$20 ..., Ol'RD 1531 =ST I. flISP.4 I, ~:SP.~, IS)2 tOl'RD 1530 !tIE sorA ASLX " JS, COCO roLA ASLX roLA sr. sr. LOA AND DISP.1Co IJ1SP.11 PIN. 1 IS3F' J£R COCD sr. mSP.1J [,ISP.14 sr, "',.. [lISP.2 DISP.) 1531 CMP LnA NC1rN[ tl!. PLON PIN PII'I'N HWR' MIW'I'£S Rr' .................................................... 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S7E.S7A $7E. $7E, $7£.$7£ S3F'. $70, $3£, S7D edde 00 01 ede2 04 05 ede6 08 09 edea 7e 7e 02 06 7d 7e 03 07 7e 7c .11 .11 I S" .11 1 0 \ 9 "OB ITB 8:' Oa Ob Dc Oe Of 10 12 13 14 t6 17 18 "'B K" edfe ee02 ee06 eeOa 19 la Ib Ie Id Ie If 20 21 22 23 7e 7e 7e 7e 7d Fe8 FeB FeB fI" eeOe ee12 ee16 ee1a 7a 27 2b 2f eele )) ee22 37 ee26 3b ee2a 7e .11 .ll Fe, 7e Od 11 15 25 29 2d 31 ,11 .11 IT, edee edf2 edf6 aHa 8 F J "" 26 2a. 2e 32 FeB FeB "'8 "'8 34 35 36 38 39 3a 3c 3d 7e 7e 7e 7e feB 24 28 2c 30 'll .ll N C ,,I "f : m 8:, v fl'B fl'8 , 0 7 C .ll 2248 2249 225G 2251 2252 2253 2254 225S 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2r2 2273 2274 2275 2276 t'klt:r.Y D:Vlde, n('r:~ h ".nd ye""r Ttar.sfer 0[ ocr· nUJTlUel-S i~:\ ee2e bE ae ee30 cd eE 86 ee33 ee35 ee37 eeJ9 ee3b 2277 ee3d 2278 ee3! 2279 ee41 2280 ee43 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 ee45 ee47 ee49 ee4b ee4d ee4f eeSl ee53 ee55 ee57 ee59 ee5b eeSd eeSf ee61 ee63 ee64 ee66 ee6B ee6a ee6c 3f bE bE a6 b7 aD a7 as 09 ac be ad bE a3 be Ole bE a4 be 013 e6 08 3<> <>3 be a4 eb 08 3a a4 bb ab ADD ~!ESTINATIW AT NU,\l :L..R ,;,"c:...'EJ', AD ",:,:tJrEP ~'A Wi illA C€C ~:X ArC DEC ",DIT,:t< O/UiFU...•.. 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CLEAR M.S DIGIT IN('REMEN'T WOOER FINISHED ? NE.\1' DIGIT "". Shlft ef64 eE66 ef69 ef6b ef6d ef6e ef6f eE71 ef7) enS ef76 ef78 b7 cd be e6 f7 5c b) 26 b6 f7 )a 81 a) ef 79 al 01 en9 ef7b end ef7e ef7! efBI efB) bf a6 5e 4a 26 bf 81 al 08 ef84 ef86 efBB ef8a efSc efBel efBe ef90 ef92 ef94 ae bf a6 b7 7f 5c 3a 26 be B1 )0 a5 09 ac Sf A JSR '''3 [1n WI 1.)0: MJVE ALL DIGITS uP UNE PLACE 1.(£0, .",~, l.S[ lDX illA Sf A =, a2 f8 aJ O. X CP;'; lE srx AXL W2 FITS CLQ CLRAS OR ae fa as UlX SI'X CDA srA OCR N,::, DIGITS S'I'.IIJ(J'IN::3 AT X CL£~ nn OCC ENE U" COlm -=-'k RTS 97 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 M..T[l - dly (It ..-k and ye,ol . ,""', (MJ[l+2}KJD7 (= WD-l) ::: 00'( (KJD-15078.2}J3652500) [001 ::: Y' ef95 ef97 ef99 ef9b efge afaO ae bf ae cd ae 5d ad 42 e[a3 efaS efa8 efaa efad efaf efb2 efb4 efb6 efb9 efbb ae 39 cd ee ae 39 cd ee ae 30 cd ef a6 07 b7 38 cd ef b6 <;3 b7 73 efM efbf e[c1 efc3 efc5 efc8 efca efod efdO efd3 efdS ae bf ae b[ MJOC cd Sd ad 30 ae [0 42 ee fa ef ad 66 ee ae cd cd cd bf ae 2546 e[d"! cd 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 efda cd fa 2558 efdd ae 5d 2559 efdf bf ad 2560 efel ae 42 2561 efe3 bf ae 2562 efe!> cd fa 2563 efe8 ae ]0 2564 efea. cd ee 2565 efed b[ ad 2566 efef ae 54 2567 eff1 bf ae 2568 eff] ae 42 2569 eftS cd ee 2570 eH8 cd fa 2571 effb cd ef 2572 eHe bf ad 2573 fOOO ae 42 2574 f002 cd _ 2575 f005 b6 49 2576 f007 b7 6f 2577 [009 b6 4a 2578 fOOb b7 70 2579 2580 fOOd cd fO 2581 f010 cd fa 2582 faD I:.f ad 258) f015 ae 39 2584 fa 17 cd ee 2585 fOla cd fa 2586 fOld bf ae 2587 fOlf ae )9 2588 f021 bf ad 2589 (02) cd ee 2590 [026 b[ ad 2591 [028 ae 42 2592 [02a b[ ae 2593 f02c cd fO 2594 f02f3f47 2595 fOll ae 54 2596 f033 cd ee 2597 fO)6 bf ae 2598 f038 ae 5d 2599 f03a bf ad 2600 [03e ae )0 2601 [03e cd ee 2602 [041 e6 04 2603 [043 b7 72 2604 f045 e6 0) 2605 f047 1:07 71 LDX S'l'X lD' ee 2e 5d cd [0 83 00m< TRA P ".- MTO TIOK KJD ill' IP-ND JS. 90 JS. 1DX JS. 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FOLLOWED BY A S12us PAUSE. 02cf 02d2 02d4 02d6 02d8 02da 01 a6 ad ad 10 81 e3 04 10 15 24 e3 sendl brclr Ida '$10 lastO bsr bsr burst datwt. bset O,dflag O,dflag, lastO check if last bit was zero burst if last bit was 1 32kHz pulse for Sl2us wait SUus set flag as 1 sent rts 110 0216 0217 0218 0219 0220 0221 0222 0223 02db ad 1 f 0224 Oldd 00 e2 04 0225 02eO a6 10 '* 'ro TRANSMIT A LOGIC '0' A S12us PAUSE IS FOLLOWED BY A 32kHz PULSE TRAIN FOR 512us. IF A LOOIC '1' FOLLOWS A '0' 'IO AVOID A PROCESSING '* DELAY 11" '* THE 32kHz IS CONTINUED FOR l024us sendO brset ld. bra 0226 02e2 20 02 0227 0228 0229 0230 0231 0232 0233 0234 0235 0236 0237 0238 0239 0240 0241 0242 02e4 02e6 02e8 02ea a6 20 ad 03 11 e3 81 datwt O,keyst3,nextl 1$10 datset wait S12us check if next bit is 1 single burst if 1 data set next I Ida *$20 double burst required datset bar belr rts burst O,dflag clear flag as a sent 32kHz pulse for S12us '* THE 32kHz PULSE TRAIN HAS A MARK 'ID SPACE RATIO OF 1 'IO 3 02eb 13 01 burst belr 02ed 21 fe 02ef 12 01 brn 02fl 0213 02f5 02f6 brn bset 21 fe 13 01 9d 4a belr 0244 02f9 20 fO 0245 02fb 81 0246 0247 endbur 0248 02fc a6 52 0249 02fe 4a 31 fl e1 dl bl 71 0302 0308 030e 0314 32 f2 e2 d2 b2 72 34 f4 e4 d4 b4 74 38 f8 e8 d8 b8 78 031a 0320 0326 032c 11 12 13 00 0332 BO portb 1 low portb 1 high 1, portb portb 1 low 39 3b 3a Oc 10 2e 2d 07 17 18 19 06 14 15 16 01 dec. beq bra rts decrement count end of burst ? endbur burst datwt Ida 1$52 loop deca bne rts loop keydat feb feb feb feb $31, $f!, $e1, $32, $f2, $e2, $34, $f4, $e4, $38, $f8, $e8, tvdat feb feb fcb feb $11, $3e, $39, $10, $17, $14 $12, $3d, $3b, $2e, $18, $15 $13, $3e, $3., $2d, $19, $16 $00, SOd, $Oe, $07, $06, $01 softin rti 02ff 26 fd 0301 81 3e 3d 3c ad 1, portb 1, portb nop 0243 02f? 27 02 0250 0251 0252 0253 0254 0255 0256 0257 0258 0259 0260 0261 0262 0263 0264 0265 0266 0267 0268 0269 0270 bsr 03fa org $3f. 03fa 02 18 OHe 03 32 03 fe 02 00 fdb fdb fdb presd softin start count to provide 512us delay after instruction times $d1, $b1, $71 $d2, $b2, $72 $d4, $b4, $7' $d8, $b8, $78 scan keybrd on int software interrupt resett 111 112 AN479 Universal Input Voltage Range Power Supply for High Resolution Monitors with Multi-sync Capability By J. P. BruniQuel, Integrated Circuits Application Lab., Motorola SA, Toulouse ABSTRACT This Application Note describes an easy to build, high performance, low cost 100W FLYBACK power supply, able to work on any mains supply from 85 Vac to 265 Vac, from 40 Hz to 100 Hz. It is automatically synchronised on the horizontal scanning frequency for minimum screen interference on a multi-sync colour monitor, thanks to the versatile, high performance, low cost current mode controller MC44602P2, associated with the state of the art switchmode power transistor MJH 1801 O. INTRODUCTION The MC44602 has been specifically designed to drive high voltage bipolar transistors. Its 1A source and 1.5A sink capability, with all the protection features associated with flyback power supplies, make it ideal for this kind of application. New multi-sync high resolution colour monitors have horizontal frequencies in the range of 31.5 kHz to 85 kHz. The switchmode power supply associated with these high resolution colour monitors must be synchronized to the horizontal frequency in order to reduce any EMI/RFI effects visible on the screen. An important feature for an off line power supply is that it can be automatically adapted to any mains voltage without any hardware adaptation. SPECIFICATION Universal input voltage: 85 Vac to 265 Vac, 40 Hz to 100 Hz Output voltages: 135V 87V 25V 16V 6.3V O.4A 0.2A 0.8A 0.3A 0.8A Output power: 1OOW Short circuit protection on all outputs Overload protection Minimum efficiency: 80% at full load Line regulation: ~ ± 1% Load regulation: ~± 1% External synchronisation: from 31 .5 kHz to 85 kHz Low overall cost. 113 TOPOLOGY AND MODE OF OPERATION CHOICE For multi output voltages at 100W output power, the best choice is the SINGLE ENDED FLYBACK TOPOLOGY. The best price/performance ratio is offered by a combination of a high performance current mode controller MC44602 and a MJH1801 0 switching planar power transistor. Depending on timebase frequency and mains voltage, the power supply works in either a discontinuous or a continuous current mode. Continuous current mode is for low mains voltage, and discontinuous current mode is for high mains voltage and low power. The continuous current mode at low mains voltage lowers the peak current (I Peak) on the transistor and as a consequence lowers the Vce sat. the Ibl and the losses. At high mains voltage the discontinuous current mode allows lower switch-on losses and lower stress on the high voltage output diode. When the output diode has to switch current, its losses are higher (Trr). The losses on the output diode depend on its current during conduction and current during switching. In discontinuous current mode there is no current in the diode at switch on. In continuous current mode there is always current in the diode at switch on and the Trr of the diode (switching losses) depends on this current. To accommodate a wide range of applications, the frequency of operation will be between 31.5 kHz and 85 kHz. The MC44602 has a separate synchronisation input which resets the oscillator when a 5V positive pulse is applied. Since the oscillator of the MC44602 is working at twice the output frequency, the power supply will be synchronised at half the horizontal scanning frequency resulting in less disturbance on the screen with the synchronisation occurring only every two lines. Another advantage is for the power transistor which results in fewer switching losses, as it works at half the scanning frequency. Switching losses are directly related to the switching frequency, since they are the same for each cycle. The higher the frequency, the greater the losses. A zener limits the input voltage to 4.7V on the sync. input. (See figure 1.) The synchronisation transformer is a toroidal bifilar core which receives the pulses from the time base of the monitor. The sync. pulse will have 5V amplitude and about 2 ~ width. The main noise source is the high di/dt occurring at switch off. The power supply works at half the scanning frequency, so the impact of that disturbance is divided by two. NOISE I TIME BASE ~----~<_/-----~ COLLEcroR CURRENT Figure 1 Switch off screen polution 114 TRANSFORMER DESIGN Since the transformer plays one of the most important parts in the performance of a flyback power supply, due to coupling and leakage inductance, the transformer was designed around a SMT47 multislots former and a B3 GETV 53.18.18. ferrite core from THOMSON OREGA. The feedback from the output voltage is magnetically realised by the auxiliary winding which performs good load, line and cross regulation, without the need for an optocoupler. This auxiliary winding has three main functions (see MC44602 data sheet): Self supply of the MC44602 Image of output voltage for regulation Image of output voltage for overload detection. Since the power supply will work from 85Vac to 265Vac, the minimum rectified voltage U is 85,t2=120V. To provide a safety margin in worst case conditions (low mains-high power). let us choose a minimum DC voltage U of 90V. The maximum DC voltage is 265,t2=375V. Assuming an 80% efficiency with an output power of 100 W, the input power Pin is 100/0.8=125W. The maximum primary current occurs at minimum voltage U and minimum switching frequency Fs which is 31.5 kHz/2 = 15.25 kHz. The transformer must be calculated for 15 kHz minimum frequency. Let us choose a maximum duty cycle of D= 0.4 for a minimum mains voltage, a minimum switching frequency and maximum power. Then Ip, the peak current in the transistor, becomes: A ferrite material with AL=460 nH/T can be chosen. The number of primary turns is: 115 TRANSFORMER CONSTRUCTION The technique used is the multi slot developed and widely used by OREGA THOMSON. Figures 2 and 3 depict the way to couple the different windings in order to achieve a high coupling; this ensures an acceptable magnetic feedback signal and a low leakage inductance. ;». ;».+. 13 53 35 ;+ ... 13 10 ;+ 1~ ... 7+' .. 3 ;». ~ 31 '~7 ~ 121 1 +VCC 1 1 1 GND+VAUX COll 22 1 +6.3V 1 ~ 31 1 111 GN1Jt.16\GN1Jt.25V GNDt-135+87 Figure 2 Multi slot winding Lp Primary winding split into 4 sections RS where: Xs = Xo 2 (~~) + and RS = 1 cs RO (RX~ )2 + 1 (For MCI2060); II (R3 + R! + RI9)} = R2+{R17 - 1 Xo = wCo FIGURE 3 - Diode Equivalent Circuits - Vn (R) JJ.F. Typical series resonant crystals in this frequency range exhibit equivalent Cx capacity values of 0.012 pF to 0.003 pF and the maximum series resistance specification for the MC12061 is 155 ohms. Again, the requirements of both items 1 and 2 above are met. (For MCI206I). 1 While one diode (or one diode pair in the case of Figure 1) is always forward biased, the remaining diodes are reverse biased to minimize their capacitance. This is accomplished with a single polarity supply by using pullup resistors (R12, R13, R14, R15, and R16) from the positive potential to each switch terminal. Therefore, the cathodes of the diodes corresponding to the unselected crystals are pulled up to approximately the supply voltage. Since one diode (or diode pair) is always selected, current is flowing through R17 continuously, causing a voltage drop. Therefore, the anodes of the unselected diodes will be negative with respect to their cathodes. When using a 5.0 volt supply, this reverse bias will be 1.6 volts for the MC12060 and 1.2 volts for the MC12061 crystal switching array. DECOUPLING UNSELECTED CRYSTALS Isolating unselected crystals is very important from the standpoint of minimizing frequency pull of the selected crystal, and insuring that the oscillator will lock on a new crystal frequency when switched from a previous one. The objective for decoupling unselected crystals. is to place a high impedance in series with them. The MSD7000 typically has 0.72 pF of shunt capacitance CD (refer to Figure 3) at VR = 1.6 volts, and the MPN3401 typically 0.75 pF at 1.2 volts of reverse bias. Since RO is extremely large for the reverse bias condition, the resulting diode .RS resistance will not be exceptionally large and Cs will approximately equal CD. This series capacitance is 30 to 300 times greater than typical values of equivalent crystal series resonant capacitance (CX). Therefore, the total series equivalent capacitance CSCX (CT = C C) decreases by only 3.2% to 0.33% reS + X spectively. This, combined with a low value for RS, maintains considerable coupling between the unselected crystal (s) and the oscillator. Thus, the oscillator may remain at the previous crystal frequency, or operate at some random frequency. To reduce this problem, a shunt resistor (Rl, R3, R5, R7, Rg) is added to each switching\cl.iode (Dl, D2, D3, D4, D5) in Figures 1 and 2. This shunt resistor establishes a new and lower value for RD in Figure 3, which results in a new RS value - much greater than the maximum allowable effective resistance specification for the MC12060tMC12061. Worst-case coupling effects occur at 2 MHz for the MC12060 and 20 MHz for the MC12061. Referring to Figure 3: assume CD is equal to 1 pF; this gives XD = 1 -2-- = 79.5 k ohms at 2 MHz, and 7.95 k ohms at 20 .nCD MHz. To maximize the series equivalent resistor (RS), the parallel resistor RD is made equal to the reactance XD at the highest operating frequency. For the MC12060, the values of RO = XD = 79.5 k ohms give RS = Xs = 39.7 k ohms. Since RS is now much greater than 4 k ohms, the unselected crystals will be virtually isolated ADDITIONAL CONSIDERATIONS A sufficient amount of forward current through the diode selecting the desired crystal is required to insure a low value for diode resistance RO (see Figure 3). This is important for two reasons: 1. To minimize the effects of diode capacity on the crystal's natural series resonant frequency. 2. To minimize the total effective external resistance between Pins 5 and 6 of the integrated circuit. From Figure 3 it is apparent that as RD is made smaller, Xs is decreased and Cs is increased. A large value for Cs relative to the crystal's equivalent series capacitance is required to satisfy item 1. The impedance of the MSD7000 diode with 0.45 mA of bias current has a typical value of 115 - 3° = 114.6j6 ohms at 100 kHz and 115 - 8° = 113.8-j16 ohms at 2 MHz; resulting Cs values are respectively 0.265 pF and 0.005 pF. Since typical series resonant crystals in this frequency range exhibit equivalent series capacitance values, CX, ranging from 0.024 pF to 0.012 pF, item 1 is satisfied. Also, since the equivalent series resistance of the diode is much less than the maximum effective resistance specification (4 k ohms) for the MC12060, item 2 is satisfied. For the MC12061 circuit, the diode forward bias current is 1.15 mAo This current is sufficient to keep the series impedance of the MPN3401 PIN diode low. At 2 MHz the impedance is nominally 22 - 28° = 19.4-j10 ohms and at 20 MHz 3.3 -37° = 2.6-j1.98 ohms. The resulting Cs values in this case are 0.008 JJ.F and 0.004 137 from the oscillator. This isolation will become greater with a decrease in frequency. Using the same formulas to determine the required RD and to calculate RS and Xs at 20 MHz for the MC12061 results in RD = XD = 7.95 k ohms, giving a new value ofRS = Xs = 3.97 k ohms. This value ofRS is much greater than 155 ohms, the maximum effective resistance specification for the MC12061. Therefore, the oscillator will now have sufficient isolation from the unselected crystals to prevent erratic performance. The values used for Rl, R3, R5, R7 and R9 are 82 k ohms, and 10 k ohms for Figures 1 and 2 respectively. as the total number of crystals to be switched is increased. However, by using the switching techniques shown in Figures 1 and 2, any frequency pulling in addition to that for a single crystal connected directly to Pins 5 and 6 (Le. pulling caused by the ICs alone) is negligible below approximately 1 MHz for the MC12060 and 15 MHz for the MC12061. Measurements of this additional pulling are summarized in Table 1. Typical frequency pulling values attributable to the ICs themselves are given in Table II. In this case the devices are operating with a single crystal connected directly to Pins 5 and 6 with no crystal switching circuits. The Table II values have been taken as a reference in establishing the pulling (noted in Table n caused by the switching networks. When using the crystal switching circuits, complete pulling from the crystal's series resonant frequency is obtained by algebraically adding the respective values in Tables I and II. For example, absolute crystal pulling for the five crystal switching system when selecting the nominal 1.0 MHz crystal is approximately - 0.0040 + 0.0031 = - 0.0009 percent. Similarly, absolute pulling for the 8.0 MHz crystal becomes - 0.004 + 0.0001 = - 0.0039 percent. Pulling effects of the switching circuits when selecting the 0.2 MHz crystal offset pulling caused by the IC to give approximately zero absolute crystal pull. When desirable, a trim capacitor can be added in series with the crystals and adjusted to pull the oscillator up in frequency. Several options are possible to reduce ac loading for both the MC12060 and MC12061 crystal switching circuits. Using a higher voltage supply for the bias networks will allow larger values of bias resistors to be used at the same diode current, resulting in reduced loading. Also, RF decoupling chokes may be added between resistors R2, R4, R6, RS, and RIO and capacitors C6 through CI0. Where frequency pulling is not as critical, L1 in Figure 1 may be eliminated. These options are left to the discretion of the user. OSCILLATOR AC LOADING Oscillator ac loading must be minimized to reduce frequency pulling and sine wave distortion. For the circuits shown in Figures 1 and 2 the ac loading is primarily attributable to the biasing networks for the five diodes (DI-D5). All bias elements contribute to an effective ac load, regardless of which crystal position is selected. This occurs because the RF signal is coupled through the parallel capacitance (Co) of the unselected crystals. Due to a greater sensitivity to ac loading of the MC12060, additional elements are used in the switching networks for this device. An RF choke, Ll, is incorporated to minimize the loading effects of the common bias resistor, R17. In addition, a modified approach is used to bias diodes Dl through D5. The networks (D6, R18) through (010, R22) are added to minimize ac loading and, at the same time, supply sufficient forward current with a 5-volt supply. One diode (01-D5) in the MSD7000 dual diode package is used to switch the crystal and the second diode (06-DI0) is used for reducing ac loading. R18 through R22 are essential to supply a small amount of current for reverse bias of diodes DI-D5 corresponding to the unselected crystals. Loading and therefore frequency pulling will be greater for higher frequency crystals and will increase TABLE I. Typical Frequency Pull In Percent Attributable to Crystal Switching Networks Device Nominal crystal frequency (MHz) One crystal (connected directly to Pins 5 and 6) Two crystal switching system Five crystal switching system 0.1 Ref. , , 0.2 Ref. MC12060 0.5 Ref. 1.0 Ref. 2.0 Ref. 2.5 Ref. MC12061 8.0 13.4 Ref. Ref. 20.0 Ref. +0.0005 +0.0006 +0.0035 -0.004 +0.0008 +0.0013 +0.0004 -0.005 +0.0005 +0.0006 +0.0031 -0.018 +0.0008 +0.0001 -0.0006 -0.023 'Less than one Hertz pull, measurement limited to resolution of test equipment. Device Nominal crystal frequency (MHz) Pull in percent TABLE II. Typical Frequency Pull In Percent for ICs Only MC12061 MC12060 0.1 1 0.2 1 0.5 1.0 2.0 2.5 1 8.0 1 13.4 1 20.0 , 1- 0.00051- 0.00121- 0.0040 1 -0.03 - 0.00021 - 0.004 1 - 0.01 1 -0.05 1 *Less than one Hertz pull, measurement limited to resolution of test equipment. 138 1 AN-790 THERMAL RATING OF RF POWER TRANSISTORS Prepared by Robert J. Johnsen Senior Staff Engineer and Technical Specialist in R F Design Group Reliability is of primary concern to many users of transistors. The degree of reliability achieved is controlled by the device user because he determines the stress levels applied by his circuit and environmental conditions. This application note will permit the device user to estimate transistor reliability from the circuit designer's point of view, namely power dissipation and case temperature. Introduction The temperature-dependent thermal properties of silicon and beryllium oxide have been measured and documented by many laboratories during the last twenty years. Only in rare cases has this information been disseminated by semiconductor device manufacturers to the users. The purpose of this note is to clarify and correct some long-standing industry-wide assumptions which have been commonly maintained about thermal resistance and high temperature derating. Most manufacturer's data sheets include a single thermal resistance number (ROJC) and use this number to calculate a linear derating constant out to some specified maximum junction temperature. The number cited on the data sheet was probably measured in the 2SoC to SOOC range, and assumed constant over the whole range of temperatures up to the maximum specified junction tem· perature. How often have you calculated a junction temperature from a data sheet, as TJ = TA + (0 JC)PD? Unfortunately, the thermal resistance of silicon increases by 80% from 2SoC to 200°C. The thermal resistance of BeO changes by 30%, if the case temperature goes from 2SoC to 100°C. Knowledge of the basic physical properties of the materials and the methods used to calculate and measure thermal resistance will assist the device user in transistor selection and equipment design. Temperature-Dependent Thermal Properties Of Silicon and 8eryllia J-. The temperature·dependent thermal conductivities of silicon and beryllium oxide are seen in Figures I through 3 and Table I. The temperature ranges are somewhat wider than are necessary for typical transistor operation, but are shown to emphasize the wide variation in thermal conductivities. Fulkerson et al 3 tabulate the values for thermal conductivity and resistivity of silicon from 1000K to 13S00K (see Table I), and they find that the thermal resistivity of silicon as a function of temperature can be estimated by a linear approximation over the temperature range shown. (400 - 660 0K) Ilk = -0.1171 + 2.9S4 X 10-3 T(OK) (I) (600 - IOS00K) Ilk = -0.9609 + 4.229 X 10-3 T (OK) (2) A similar least·square fit to Fulkerson's data over the range 200 to 700 0K, within 1%, is given by: (200 - 700 0K) Ilk = -0.2286 + 3.1683 X 10-3 T (OK) Similarly for beryllia, one can fit the data of Elston et al2 over the range of 200 to 800 0K, with equation (4). (200 - 800 0 K) Ilk = 1.943 X 10-S T (OK)1.7 NOTE: OK = (3) °c + 273. (4) where k is the thermal conductivity in units ofwatts/cmoK. 139 FIGURE I - Temperature Dependent Thermal Conductivity of Silicon (Ref. I) TABLE 1 - Smoothed Data for Thermal Conductivity and Resistivity of Silicon (Ref. 3) 100.------------------------, Smoothed ORNL Values T k (OK) (W cm-1 dog-I) W = 11k (cm deg W- I ) 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 1150 1200 1250 1300 1350 7.52 3.88 2.44 1.78 1.40 1.15 0.939 0.825 0.736 0.663 0.604 0.555 0.500 0.452 0.413 0.380 0.351 0.327 0.306 0.287 0.273 0.261 0.251 0.245 0.241 0.239 0.133 0.258 0.410 0.563 0.716 0.870 1.065 1.212 1.359 1.508 1.656 1.803 1.999 2.210 2.420 2.634 2.845 3.055 3.268 3.479 3.65 3.82 3.97 4.08 4.14 4.18 Pure 30 10 0.01 0.003 TEMPERATURE. "1( FIGURE 3 - Thermal Conductivity 2.3 2.2 2.1 2.0 1.9 FIGURE 2 - Thermal Conductivity of BeO (Ref. 2) 1.8 20 1.7 :g 1.6 '" 1.5 ~3C i ~ ... . 3.0 1.3 8 ;;J, 1.2 I 1.1 c 2.0 ~ 1.4 :::> 1.0 1.0 0.9 0.8 n6 0.5 0.4 0.8 • Silioon IRef.3) 0.7 0.3 0.6 0.2 0.5 0.4 0.1 0 200 400 800 1000 800 1200 TEMPERATURE 10 K) 1400 0.3 1800 TEMPERATURE, "C 140 Geometric Factors and Thermal Resistance Calculation The thermal resistance of most silicon RF transistors is controlled by the bulk properties of silicon and beryllium oxide, geometry of the heat generating (base) areas, and the temperature of the heat sink (case). The interfaces generally are well behaved and contribute little to the overall total thermal resistance if the device, die and package elements are assembled and handled properly. Die temperature calculations are performed in two steps. The first uses the method of Linsted and Surtey4 to calculate the temperature distribution of a die by using a double Fourier series solution to Laplace's equation. Figure 4 shows the device geometry and some of the boundary conditions. Equation (5) will calculate the temperature rise at any (x,y,z) point in the die, where A,B,C,D,F are die and heat·generating area boundaries. Q is the heat input in watts, and k is the thermal conduc· tivity of the material in watts/cmoK (Linsted's equation). T = - f{(CD)(z K F) AB ;...( + £. - --- K m'".' A + ;...( L.J - - m~l n~l resistivity. The calculated thermal resistance of the beryllia piece (from the previous section) is mathematically divided into fifty layers, each with 1/50 of the total BeO thermal resistance. The first layer at the bottom is assumed to have its temperature at the heat-sink ambient with its thermal resistance value corrected to the proper temperature using the equations for the temperaturedependent resistivity. The power flux through the first layer then leads to its temperature rise, and this new temperature determines the thermal resistivity value for the second layer. Its temperature rise is calculated, and so on, until the result for the top surface of the fiftieth layer gives the temperature rise above the ambient for the beryllia piece. The same method is used for the silicon die, using the beryllia top surface temperature as the starting pOint, and correcting the thermal resistance of each of fifty layers based upon the temperature of the layer directly Q)( 2BC ) e",:rrz/B (' , + Q)(2AD) e (' - exp [2n".(F -- n'".'B K nrz / A (m"'D) Z)/A))[. (lI".C) cos (1'-' '-:<)J exp [2m".(F - Z)/B)) . - - cos (m"'Y)J - - - [ sm -exp (2m".F/ B) B B + exp (2/1".F/..1) exp [2)"(F - Z»)) 1 + exp (2")'F) , SIn -- .1 (5) A + i: i:(- f{) (_4_) (1 'n~l n~l K ".'mn")' where ")" = ".' [ ( : ) ' + G)']. beneath it, until the top surface of the silicon die result gives the calculated die temperature for that particular case of ambient temperature and power dissipation. The results of these calculations indicate that the thermal resistance of a given device is not a constant number, but is a function of the dissipated power and the ambient (case) temperature. Another result is that the junction temperature of a device dissipating power will rise more than 10 C for a 10C rise in ambient temperature. because of the increase in thermal resistance. Figures 6 through 9 show the calculated thermal resistance and die temperature for several different devices as a function of ambient temperature and power dissipation. The Fourier series solutions are amenable to computer calculation and converge adequately within ten to twenty terms. Figure 5 shows the treatment of multiple base cell transistors. Lines of symmetry between adjacent base cells are considered to be adiabatic die boundaries as assumed by Lindsted. The power dissipated is assumed to be equally shared among the several base cells. The result of this calculation is the temperature rise of the silicon chip, assuming a constant thermal resistance for bulk silicon. The same model is used to calculate the temperature rise for the beryllia piece, using the silicon die area as the power dissipating area for the beryllia, again assuming the thermal resistance of the beryllia as a constant. The thermal resistances of the silicon die and the beryllia substrate are in series, so adding the above numbers gives a value for the thermal resistance of the device at a particular temperature and a power level low enough to avoid the effects of the temperature variations of the respective thermal resistances. The second step in the thermal resistance calculation takes into account the temperature-dependent thermal 141 FIGURE 4 - Modal for Heat Flow z Uniform Power Density Input to This Area No Heat Loss from Die Surfaces Except Bottom All Power Flows Dut the Bottom of the Chip Uniform Substrate at DoC FIGURE 5 - Array of Sa•• Ar.a. in a Silicon Oi. o o o o o 0-1[]-I-O -: I -r±-~ArtifiCial Boundary ~ By Symmetry I 1 0000 142 FIGURE 6 - Junction Temperature and Thermal Rasistance 85 a Function of Power Dissipated, Flange (Heat Sink} Temperature FIGURE 7 - Junction Temperature and Thermal Resistance as a Function of Power Dissipated, Flange (He.t Sink} Temperatur. 200,--------------------------------, 2OOr-r-~--r---------------------------, 19I1 180 170 1911 Goometry-6TH BeO Thickness - 60 mil Geometry-5NN BoO Thkknos, - 60 mil 180 - - - Thermal Resistance - - - Thermal Resistance - - - Junction Temperature 170 - - - Junction Temperature ~ ;0: z 0 ~ ~ ~ 9Il 80 70 60 60 50 50 40 40 30 30 20 20 10 10 0 °0~----~25~--.&----~----~---7.~--~~--~ 0 FIGURE 8 - Junction Temperatura and Thermal 25 FIGURE 9 - Junction Temperature and Thermal Aesistance as a Function of Power Dissipated, Flange (Heat Sink) Temperature Resistance as a Function of Power Dissipated, Flange (Heat Sink) Temperature 40or-----------------------------------, Geometry-1KF 380 360 340 320 BeO Thickness - 40 mil Geometry - 9Nl BoO Thicknes, - 60 mil ___ Thermal Resistance - - - Junction Temperature 200 100 0~0----~----~5~0~--~7~5----~----~~~~--~175 FLANGE (HEAT SINK) TEMPERATURE !OCI 143 Figures 10 through 12 are plots showing the correlation of measured to calculated temperature for several geometries. under various conditions of flange temperature (JOoC to ISaaC). supply Voltage. drive power, and Ex perimental Verification Of Calculated Die Temperature Actual temperature measurements are made with an infrared microscope. Barnes Eng. Co. Model RM:CA. This instrument uses an indium antimonide diode photo-detector at liquid nitrogen temperatures to measure the infrared radiance emitted from a 1.5 mil spot on the surface being examined. The IR radiance versus temperature curve is calibrated by measuring the radiance at various known temperatures monitored by a calibrated thermocouple while the device is heated by external means. An experimental calibration is necessary because the radiance output of the device at a given temperature is a function of the average emissivity in the area seen by the microscope. and this average emissivity is a function of the geometry and processing history of the device in question. The effective emissivity depends upon the relatil'e amounts of metal and silicon and the infrared transparency of the varying thicknesses of SiO:c glass in the tleld of view. The calibration data of radiance versus temperature can be least-squares curve fit to an equation of the fonn T = ~A)~R)b. where A and b are the fitted constants. and R the measured radiance. The del'ice is then powered up in its circuit. and the radiance data collected point-by-point around the surface ot' the silicon die. A computer program inputs the array of radiance data. calculates the actual temperature from the calibration equation. and prints a map of the temperature prot1le. as well as some statistical information about the temperature distribution. FIGURE 11 - Actual vs Calculated Die Temperatures Geometry-9NL BeD Thickness - 60 mil 400 • I Average Temperature Temperature Range - c ; ~ 250 200 '" li 150 100 400 CALCULATED DIE TEMPERATURE lOCI 144 output load magnitude and phase angles from 50 n to over 30: I VSWR. The calculated temepratures seem to be somewhat higher than measured at the higher power levels. The calculated temperatures are based on the calculated power dissipation, disregarding RF losses in the actual loads and circuits. MTBF as a function of power and ambient temperature. The temperature lines are valid for any combination of supply voltage, efficiency and drive power, by reading the power axis as power dissipated. The MTBF lines, because of the current dependence, have been constructed based upon the assumptions of l2.5-volt supply and 50% efficiency, so that the power axis should be interpreted as output power. It is possible to use the MTBF set of lines at other conditions. Enter the graphs by reading the power output parameter as power dissipated, and find the MTBF, then scale the MTBF by the ratio square of the 1'/ = 50% current to the actual current. Metal Migration and Mean Time to Failure The calculated/observed temperature agreements are seen to be close enough so that the calculated temperature can be used as the basis for reliability calculations of Mean Time Before Failure (MTBF) for metal migration based upc,n Black's5 work. MTBF = (cross section)3 ]2 . f(TO) MTBF (6) Equation (6) is the equation used for calculating metal migration lifetime, where the cross section refers to the conducting stripe dimensions in cm 2 , and] is the current in the stripe in amps. f(TO) is an Arrhenius function of the stripe material, having the form: =MTBF (from graph) X B

    are shown in Table 2. K is Boltzman's constant, and T is in degrees Kelvin. A series of graphs (Figures 13 through 16) have been constructed, one for each device, that present the results of the calculations of device temperature and Geometry - 6TH Metalization -large Crystal Glassed AI Finger Dimensions; Width - 0.5 mil Height-l.51' BeO Thickness - 60 mil Operating Conditions: Vee = 12.5 V ~ ~ (8 ) FIGURE 14 - Metal Migration - MTBF FIGURE 13 - Metal Migration - MTBF 1,000 1'/ = 50%) 2 ] actual TABLE 2 - Material Dependent Parameters Material f(TO) = B exp (-1>/KT) (I ('" Geometry - 5NN Metalizatlon-LargeCrystal Glassed AI 125'C Finger Dimensions: 50% Width-I.Omil Height-1.51' BeO Thickness - 60 mil 1,000 100 100 I '"~ " " in ~ ~ ~ 10 10 1.0 1.0 0.1 ;;"0---;;2=-5----;50':------;7~5--7,,00;;;------:-:::--;;=~:;::-'~--;; 0.1 :-0---;;2=-5---;;50':------!7=-5---::100::----:-:,2::-5---::150;:---:::175 CASE TEMPERATURE rCI CASE TEMPERATURE I'CI 145 FIGURE 15 - Metal Migration - MTBF FIG U R E 17 - Geometry Code to Standard Part Cross-Reference 125"C Geometry 12,5 Code AI AI lKF MRF421 MRF422 5NN MRF243 MRF453/A 1,000 28 AI Vcc(VII Metal MRF428A MRF316 MRF455/A MRF460 9NL 6TH MRF245 MRF463 MRF454/A MRF464/A MRF648 MRF317 MRF327 MRF328 100 \ 175'C To Scale Metal Migration MTBF From 12.5 V to Other Operating Voltages " 10 50 Au \ \2OO'C Keeping PD and 1'/ constant, then the current for 28 V operation compared with that for 12,5 V operation is given by: 112.5 X 12.5 = 128 X 28 1.0 112.5 28 ----128 12.5 G,ometlY-9Nl Metaliletion -l''1Ie Crystal Glassed AI Finger Dimensions: Width -1.0 mil H,ight-1.51' BeO Thielen... - 60 mil Operating Condilions: Vee ~ 12.5 V ,,~ From Black's5 equation: MTBFa 50% 0.1 =-0---!;25,------·-;50!::--~75;----;1+.00,-------;:12::-5--==~--''-:::! 1. 12 For like geometries, the ratio of the MTBF at 28 V to the MTBF at 12.5 V is: CASE TEMPERATURE I'CI FIGURE 16 - Metal Migration - MTBF 28 2 MTBF28 = MTBFI2.5 X 12.5 100,000 .---.---..--'T"--.-=;;--G-eom-etlY---1K-F----, M.talizetion -la'1l' CIY.I.I Glassed AI MTBF28 = MTBFI2.5 X 5.02 Finger Dimensions: Width-1.0mil Heighl -1.51' 10,000 Similarly, for 50 V operation: BeO Thickness - 40 mil Opereting Cond~ions: VCC ~ 12.5 V ,,~ 50% MTBF50=MTBFI2.5 X 16. Conclusion We have discussed the elements of thermal resistance and metal migration lifetime with particular attention paid to their variation with temperature as functions of power dissipation and ambient temperature. Graphical presentations of the results are included which should be useful to the device user who is interested in better reliability in his application. 1000 100 References 1. G. A. Slack, Journal of Applied PhYSiCS, 35, 3462, 1964. 2. J. Elston, J. DeGoer, and Z. Miliailovic, 1. Nucl., Mater., 11,333,334, 1964. 3. Fulkerson, Moore, Williams, Graves, and McElroy, Phys. Rev., 167,768-780. 4. Linsted and Surtey, IEEE Transactions on Electron Devices, ED-19, 42,1972. 5. Biack,Proc. IEEE, 57,1587,1969. 6. Hall, ECOM, DAAB07-7OC 0164, October 1971. 10 146 I AN·879 MONOMAX - APPLICATION OF THE MC13001 MONOCHROME TELEVISION INTEGRATED CIRCUIT Prepared by Ben Scott Technical Consultants: C.1. Tsui, Hong Kong Peter Bissmire, Geneva Lowell Kongable, Phoenix Mike McGinn, Tempe This application note presents a complete 12" black and white line-operated television receiver, including artwork for the printed circuit board. It is intended to provide a good starting point for the first-time user. Some of the most common pitfalls are overcome, and the significance of component selections and locations are discussed. The design has only 4 factory adjustments: H. Hold, Height, AGC Delay, and V. Linearity, and there are no alignments. Note that while this discusses MC13001 (525Iine, positive tuner AGC) there are also parts for 625 line and negative tuner AGC, in all combinations. INrRODUCTION pation. Special attention was given to ESD (electrostatic discharge) immunity on all pins. An extremely stable horizontal oscillator was devised_ Additional features which resulted from this design effort included: a completely integrated IF and detector with no detector tuning or external filtering components, an on-chip dc contrast control which permits remote location of the control without shielded cable, and fully black level clamped video with blanking and beam current limiting. The combination of system functions in the Monomax chip permitted some elegant solutions which would not have been practical or economically feasible in more conventional designs. It is. not the purpose of this AN to describe the overall Monomax chip in any greater detail than is required for understanding receiver design decisions. The reader is urged to obtain a copy of the MC13001 data sheet available from Motorola Literature Distribution or Linear Applications. It contains some of the basic Monomax has been on the market since mid-1981.1t was originally developed in a joint effort between Zenith and Motorola for the purpose of creating a high performance B&W.receiver. It was intended for all types of monochrome receivers, including the demand-ing portable and mobile applications, which require immunity to noise, "airplane flutter" and multi path signal conditions. Features suggested by these requirements included: noise filtering and cancelling, dualloop horizontal PLL, countdown vertical, and a flexible AGC system_ It was also required· that the resulting receivers be low in component and manufacturing cost. To meet this objective, effort was made to minimize external components (especially precision components) and adjustments; Above all, the receiver was to be reliable, so the chip was designed to operate at low voltage and low dissi- 147 FIGURE 1 - Simplified Block Diagram II~ + + FIGURE 2 - Monomax Functional Block Diagram 148 application information which will not be repeated in this note. Also recommended is a paper entitled "Monomax - An Approach to the One-Chip TV" by Gerald Lunn and Mike McGinn of Motorola. This can be obtained from the proceedings of the IEEE Chicago Spring Conference on Consumer Electronics, June, 1981, or from Linear Applications, Motorola. Monomax is not difficult to apply. A functional TV set is virtually assured on the first try. But as anyone closely associated with television design can attest, there are, in every new design, a number of small but objectional problems which stubbornly resist solution. The receiver described here does not represent the "last word", but it is pretty close to production quality, and it includes solutions to some of the most common beginner's problems. In the following text, an attempt will be made to explain component value choices and locations in terms of problems solved or behavior avoided, so that the future experimenter will be alerted. output. The audio output section is usually a Class B type, operated directly from 12 Vdc. An IC combining the sound IF, detector, and audio output is ideal in this architecture. TDA1190 is an example which fits well with Monomax. Figure 4 shows the basic power supply structure for the ac line operated type of design. This is the most economical and the most common approach for B&W television in most of the world, and it is the subject of much of this AN. Special thought was given to this type of set in the design of the MC13001 itself. Note that the horizontal oscillator and driver are supplied through high value resistors directly from the rectified power line dc (120 V). Only 4.0 mA are needed into Pin 18 to power the horizontal oscillator system. The balance of the horizontal circuit is also line operated so it is fully operable from the line supply. The horizontal section then produces the 12-14 Vdc for the rest of Mono max (50 mAl, and for the tuners, the sound IF, the vertical output, etc., about 150 mA in all. This method avoids the problem of developing 12 Vdc directly from the line; i.e., the waste of power in a linear approach, the extra components for a switch· mode dc-dc converter, or the cost of a line transformer. As in the previous example, the TDA1190 can be used for the entire sound system, but many designers prefer to use a Class A, line operated, discrete output stage, and one of the standard sound IF Idetector ICs, slich as MC1358, CA3065 or TBAI20. This removes the 12 V supply ripple caused by loud low-frequency audio passages, but costs a small audio output transformer. This is the approach presented in the complete receiver in this AN, but it could be easily changed to the single· chip sound system. THE BASIC DECISIONS/POWER SUPPLY One of the first considerations in a new TV design is whether the set is to be acldc (12 Vdc operable) or ac line only. Monomax fits well into either, and has been used in production designs of both types. Figure 3 shows the architecture of an acl dc type with all systems operated from 12 V dc. In this case, the horizontal output st.age is of the "boost" type, to minimize horizontal deflection current and make the yoke easier to manufacture. The flyback transformer contains auxiliary windings which provide supply voltages for the video output, picture tube grids, and vertical deflection. Sometimes the boost voltage of 20 to 30 Vdc is used as a power supply for the vertical To Audio Output Stage • Boost 10 H. Output 17 H. Driver 181--+--~-, + .I. .I. 0.01 MC13001 MONOMAX REXT(See Data Sheet) 19f--......---<~---- +8.0 V + I .I. 0.01 FIGURE 3 - Basic AC/DC Architecture 149 140 Vdc ~ To Audio Output I 120Vdc To Video Output 120 Vae ,...--+1-----<-. H.V. +12 V FIGURE 4 - Line Operated Architecture This means keeping color and sound subcarriers low enough to avoid 920 kHz beat generation in the detector, and yet not attenuating the sound so deeply that good sound quieting is irretrievably lost. A wellproven characteristic for achieving this goal is as shown in Figure 5, taken from tuner-mixer input to detector. Of this, some selectivity comes from the mixer-tuned circuits, but most of it is provided by the SAW filter. Table I shows some available types, data normalized to 0 dB picture carrier. The major difference is the depth of 41.25 MHz. In this regard, the Toshiba F1032U, Kyocera, and the muRata parts are best for B& W design. The mixer-tuned circuits will supply the It is important to use good bypass techniques on all power supplies, not only for low frequencies, but also for RF. It is critical in prevention of faint but objectional vertical lines in the picture, caused by horizontal deflection system waveforms getting into the supplies. Good high-frequency bypasses on Pins 18 and 19, with respect to Pin 16, are essential. THE IF The four stage IF in the MC13001 has 80 Ii V sensitivity, sufficient for excellent overall performance when used with an ordinary tuner and a conventional L/C input bandpass network. It is recommended that the input always be used differentially to reduce the possibility of feedback problems: The differential input capacitance decreases from its normal 5.0 pF, to about 2.0 pF, in the top 10 dB of gain-range of the IF. This can be used to narrow the input L/C filter, at very weak signals, to reduce overall detected noise, and improve picture lock. If a SAW (surface acoustic wave) filter is used, as in this AN, the above bandpass "walking" technique cannot be used. Furthermore, if a SAW filter is used, an additional fixed gain-preamplifier is needed to overcome the 20 to 25 dB loss thus imposed. Nevertheless, this approach has become increasingly popular with the introduction of low cost SAW filters, because it eliminates a crucial and time consuming production alignment. There is a steadily increasing supply of SAW filters in the marketplace, so some criteria for choosing the best one for the design are in order. Bear in mind that all of the video selectivity is concentrated in the tuner and the IF input filter in this design. In a B& W receiver, it is important to obtain a good compromise of picture and sound quality with a single selectivity channel. .10 - ---- - - ---- - -- - ---~-~---- -10 !g -20 l:l ~ - ----.- ~ -30 '" Adj. Pix -'0 Freq -MHz 40 42 43 44 4' 46 .7 FIGURE 6 - IF Bandpass Characteristic 150 48 TABLE 1 - Relative Response FI032B 39.75 Adjacent Picture 41.25 Sound 42.17 Color Peak 45.75 Picture 47.25 Adjacent Sound Insertion Loss -40 -12 +1.0 +4.0 0 -45 -18 Some Available SAW Filters Toshiba FI032U FI032V -48 -16 0 +4.0 0 -48 -19 additional slight amount of narrowing required. The F1032V part is too wide, and FI052 is too narrow. These are intended for color receiver architectures of different types. The SA W manufacturers loading recommendations should be adhered to closely to prevent ghosts (before and after the picture) caused by capacitive feed·through and/or "triple transit" reflections. At the input of the MC 13001, it is important to use good bypass capacitors on Pins 2, 4 and 6 with respect to Pin 1 of the MC13001. The best value was found to be a straight lead, low-inductance 0.02 "F disc ceramic for reducing the infamous channel 6 beat. Pickup in this area is also a possible source of vertical scan bars in the picture caused by horizontal sweep currents. It is desirable to keep the SAW filter close to Pins 1, 2, 4 and 6. See the PC board layout Figure 14, Also, the IF preamplifier must be kept compact and well grounded to prevent feedback and oscillation with the tuner. AGC The AGC system was implemented here essentially as described in the Data Sheet, including the AGC speed-up capacitor between Pins 9 and 10. This keeps the AGC airplane flutterresponse time fast, even when the signal is strong enough to move the AGC into the tuner control region. The RF AGC delay setting is one of only 4 factory adjustments. Ideally it should be made with a calibrated signal level, but acceptable results can be obtained with a strong off-the-air signal and a switch type attenuator. A discussion of this adjustment is contained in Appendix 1. -45 -6.5 0 +4.0 0 -47 -18 FI052 Kyocera KAF45MR-MA muRata SAF45MC 027 -40 -25 0 4.0 0 -40 -21 -37 -18 0 4.0 0 -42 -23 -37 -19 0 4.0 0 -38 -20 Remember that AGC loops have a large amount of gain, and fast AGC loops, with good airplane flutter performance, are especially vulnerable to deflection currents. Only a few millivolts on the AGC lines from stray fields or ground loops can cause a significant "bar" in the picture. Keep the tuner AGe lead away from yoke leads. The small bypass capacitor on Pin 11 further reduces this problem, and should be placed as close to the Me13001 as possible. Monomax was designed so that in the strong signal region, "above the delay", the IF gain is held constant while AGe acts upon the RF stage in the tuner. This means that a small amount ofIF AGe range may not be accessible in the normal implementation. Optimum setting of the delay pot keeps the RF section at maximum gain for RF signal levels of from <10 "V to 1.0 m Vrms , using 40 dB ofthe IF AGe range. The tuner is not likely to be able to provide more than 40-46 dB of additional AGe, which will accommodate signal levels up to approximately 200 mV rms . This is adequate for the Monopole antenna applications, but certainly doesn't offer a lot to spare. Above this level, the AGe system loses control, the receiver overloads and eventually falls out of sync. One way to improve this, and pick up the remaining 6.0 dB or so ofIF AGe capability, is to put a resistor from Pin 11 to Pin 10. The value of the resistor will be about 33 k for delay resistor values shown, but will have to be tailored to the particular tuner used. This can also be accomplished by a resistor from Pin 9 to Pin 10. This, in fact, is the only solution in parts providing negative tuner AGe. iii ;; 40 o i a:: z ~ 1.0 SIGNAL STRENGTH (mV) 1.0 200 SIGNAL STRENGTH (mV) FIGURE 7 - Modified AGC Curves (Rasistor from Pin 11 to Pin 10j FIGURE 6 - Monomax AGC Behavior 151 THE SYNC SEPARATORS Composite sync is stripped from noise-cancelled video in a peak detecting sync separator, as shown in Figure 2. The time constants for setting the slice level of the detector are connected at Pin 7. As always, there is the compromise between optimum noise immunity and tilting of the slice level during vertical interval. For best horizontal separation, a short time constant is required. There is also an AGC anti·lockup system which responds to the voltage at Pin 7. It also requires a short time constant. A second, longer time constant can be diode connected to the same pin, to prevent too much charge-up during the vertical interval. Composite sync is subsequently integrated internally and fed to another amplifier whose emitter is brought out at Pin 23. Satisfactory vertical sync can be obtained (internally) by simply connecting Pin 23 to a divider. Weak signal performance can be improved by using an RC network on Pin 23 to make the separation self compensating, as in the horizontal separator. Also AGC from Pin 9 can be fed to Pin 23 to improve airplane flutter vertical hold. 0.47 1 + -=- 8.2 k ::: (A) ORIGINAL CIRCUIT FLYBACKINPUT The only flyback pulse input to the MC13001 is at Pin 15. It takes care of keying the AGC, blanking the video output stage, and phase locking the horizontal system. The Pin 15 input is a base-emitter junction, with a reverse polarity diode for protection. The input requirement is for a negative-going pulse of 0.6 rnA, but it is best to choose a pulse voltage and series resistor to give about -2.0 rnA peak. This will make the effective width be the pulse width near its base. (B) NEW CIRCUIT FIGURE 8 - Horizontal Phase Detector The second horizontal phase detector compares the fly back output phase with that of the oscillator, and develops a proportional dc voltage, which is filtered at Pin 14. This dc voltage then sets the slice level on the oscillator ramp to produce the output timing desired. See Figure 9(a). Picture phasing can be adjusted slightly by a high value resistor on Pin 14 to +8.0 V or ground. A 220 k to +8.0 V will move the picture about 2.0 p's to the left. A 220 k to ground will move it 2.0 p's to the right. Another application of Pin 14 provides a method of changing the duty cycle of the horizontal output waveform from Pin 17. Normally, the desired waveform would be 50%. This has been assured in the MC13001 by operating the slicer at 31.5 kHz. This permits output phasing correction without changing duty cycle, as shown in Figure 9(a). In some receivers, when large amounts of dc power are drawn from the fly back, the "on" time of the horizontal output may have to be more than 50% of the cycle. This can be accommodated by feeding back some driver collector signal to the second phase detector filter, as shown in Figure 10. This imposes alternate slice levels and hence, the desired change of duty cycle. Some tentative values for a set configured like the one in this AN are given in Figure 10. This was not actually used in the final design, because it wasn't needed. It is supplied here as a reference for future designs having more power drain from the horizontal output. Bear in mind that the driver collector voltage would be much lower in the 12 Vdc receiver architecture mentioned earlier, requiring much different values to implement this idea. A practical limit of control by this technique is about a 60/40 duty cycle. The 0.001 capacitors on Pin 17 and the driver base are to "soften" waveform edges, to reduce their radiation into signal circuits. HORIZONTAL OSCILLATOR/ AFC Monomax contains a really unique group of features in this area: dual-loop; variable-loop-gain (bandwidth) on the first (sync) PLL; externally adj ustable phasing in the second PLL; simple flyback pulse input, requiring no ramp generation. These are described in detail in the data sheet, and will not be repeated here. Shown in Figure 8(a) are the first PLL components as presented in earlier publications, and in 8(b) a new variation which has been implemented in this receiver. This very simple change retains the dual time constant on the phase detector. The improvement is the 13 k/22 k divider which sets a 5.0 V point for the return of the longer time constant filter. Since 5.0 V is the reference level in the oscillator, it is also the operating voltage at Pin 12, and at Pin 13 when in-lock. The benefit, then, is that the 0.47 JLF doesn't have to charge up, so there's very little frequency pulling during power-up or powerdown. This reduces audible chirps and momentary stresses due to long cycles on the horizontal output device. Also the picture locks-in quickly, which is highly desirable with fast warm-up picture tubes. Note that the proper setting of the horizontal hold control occurs when no average current flows through the 390 k resistor, either to, or from, the oscillator. A simple alignment procedure is to set the average Pin 12 to Pin 13 voltage to zero by adjusting the hold control, when locked to a standard broadcast signal, using a high impedance voltmeter. 152 many customers like to have one, but also because it permits using a smaller coupling capacitor for the yoke. The smaller coupling capacitor saves money and reduces picture bounce, but introduces some curvature which must be compensated. Feedback to Pin 21 provides overall output stage linearization and prevention of deflection current change with temperature. It is also a handy place to feedback a variable parabolic waveshape for linearity control, as shown in Figure 11. OSC. /i Z1 /\ \ I Z1 \/, /\ \ \7i , / \ / Ramp ;?1 \ ) Pin 14 I \ I I " " I' , I " I Pin 17 } Output ;.---- J Vj (A) NORMAL APPLICATION. PHASING SHOWN AT TWO CONDITIONS I I , I I I , I uncompensated Yoke Current I I I I I I I I I I~____ .__Jr - ~ I mmfbk I Correction ~ linearity P1n17 I I ~ I : r . I (B) DRIVER COLLECTOR FEEDBACK TO PIN 14 I t FIGURE 9 - I I I Second Phase Detector Slicer I mal( fbk . \'G'V",\rt ",a' \~... I Signal at I I I : Control r I I I Compensated I Yoke Current I I I FIGURE 11 - Vertical Linearity Control MONOMAX 17 14 470 0.001 1 47 k r 820 001r to"" 'II~0.,,", THE SOUND SECTION The buffered video detector output at Pin 28 is a wideband signal used for sound take-off. A ceramic sound take-off filter and detector "tank" were chosen to eliminate alignment steps. The MC1358 is a popular, multi-sourced, FM IF, detector and dc volume control. It can be used with conventional L-C circuits or the ceramic devices shown here. The L-C application costs less in piece parts, but has a higher manufacturing cost in assembly and alignment. Keep in mind that a limiting IF produces a wide spectrum of 4.5 MHz harmonics. The sound IF grounds should be kept together and returned to Pin 1 by a single path as shown in the copper layout of Figure 14. Also it is a good idea to keep the input of the sound IF IC close to Pin 28 to reduce radiation of video IF harmonics, generated in the video detector, from getting back to the tuner or IF input. In the receiver described here, an ac volume control has been used. A potentiometer is placed between the MC1358 detector output, Pin 8, and the post amplifier input, Pin 14. The dc volume control, Pin 6, is grounded for maximum volume. If the volume control is to be mounted some distance away, and deflection pickup is likely, then the dc volume control could be the better choice. This can be done by ac coupling Pin 8 to Pin 10, and placing a variable 50 k pot from Pin 6 to ground. The disadvantage is that the control contour is less predictable in the dc control configuration. It is, nonetheless, a production proven method. a l.I. FIGURE 10- Driver Feedback For Extended Horizontal Output "On" Time THE VERTICAL SYSTEM Aside from all of the sophistication of the countdown vertical system within the Monomax chip, what remains to be accomplished outside of the device is fairly conventional. At Pin 20, there is an external capacitor, charged from a high voltage, to produce a good linear ramp. It is discharged within the chip, usually by vertical sync, but sometimes by the countdown circuit when sync is momentarily absent. It is important for the capacitor to be a good stable low ESR type and to be located close to Pin 20 and grounded as closely as possible to Pin 1 to avoid pickup ofhorizontal sweep which could hurt interlace. The approximately 1.5 V p _p waveform on Pin 20 is inverted and buffered to Pin 22 to drive the external output circuit. In the receiver design in this AN, a fairly conventional vertical output stage has been used. An optional linearity control has been added, because 153 tortion of high· frequency detail, due to excessive load· ing ofthe video driver. This can be reduced by adding a resistor between Pin 24 and the trap, and by return· ing the bottom of the trap to the video output stage emitter. The compromise chosen is shown in the full schematic. Again, it is good to keep these parts close to Pin 24 to reduce radiation of video detector products back to the tuner and IF front end. THE VIDEO OUTPUT Pin 24 provides up to 1.4 V, black·to·white video drive, black level clamped, with a widened and ampli· fied blanking pulse added. This is sufficient to drive a single stage common·emitter video output transistor. A dc voltage of 0 to 5.0 V applied to Pin 26, varies the black·to·white amplitude at Pin 24 from 1.4 V to 0.1 V without changing the absolute black level ofthe output voltage. Beam current limiting can also be used to control maximum brightness. This is accomplished by circuit shown in Figure 12. As beam current increases, the H.V. winding current flowing in the 39 k resistor, pulls the Pin 27 voltage down. When Pin 27 falls below about 1.0 V, the contrast begins to be reduced. This circuit was not used in the complete receiver in this AN, for reasons which will be explained shortly. The black level clamp capacitor on Pin 25 is usually shown connected to ground. It can also be connected to +8.0 V to cause the screen to be blanked for about 1 second after turn·on. This permits the scan systems to stabilize before the picture becomes visible. Note: If the brightness control design window is set too high, the raster may still be visible during start·up. There are several approaches to sound trapping in the video output stage: series tuned L·C from the video output base to ground; parallel tuned L·C in the video output emitter; or a ceramic shunt element in the video output base circuit. All of these can be detri· mental to picture quality, if not carefully done. The ceramic element is in keeping with the "no alignment" philosophy successfully implemented thus far, so there was a strong motivation to use it. However, shunt loading Pin 24, if too severe, causes considerable dis· The video output circuit can take many forms. Monomax was designed to accommodate full dc cou· piing, as described earlier. However, many TV design· ers, and users, don't like full dc coupling, because it sometimes seems to go too black, creating the suspicion that some information is hidden. Also, a directly coupled video output to picture tube cathode usually requires a negative voltage for at least one of the grids for proper set·up at high contrast settings. Finally, fully dc coupled designs are harder to protect from power·off flash or spot burn. For these reasons the receiver described in this AN was a partially dc coupled type. This puts the bright· ness control in the cathode circuit, removes the need for the brightness limiting configuration, and makes spot/flash prevention easier. (The diode and electro· lytic in Glare for this latter purpose). In the video output stage emitter, some dc set·up from the +12 V supply has been used to adjust the out· put dc level, to minimize overall dissipation. Also some additional vertical blanking has been fed through a diode, from the top of the vertical yoke. This blanking will be accomplished in the IC internally in later Monomax devices. 28 FIGURE 12 - Beam Current Limiting 154 means a horizontal (saddle) winding of about 3.4 mH and a vertical (toroid) winding of approximately 3.0 n, 10 mHo Numerous substitutions are available, but the above values must be adhered to for this set architecture. APPENDIX I - AGC DELAY ADJUSTMENT Ideally, a known antenna signal level of 1.0 mV (300 n balanced) or 500 p. V (75 n unbalanced) is supplied to the tuner input_ This signal level corresponds to the threshold of "snow" in the picture, for most receivers. With this signal level, the AGC delay pot is turned until the RF AGC voltage just begins to rise, and then is backed off slightly. The picture should be snow-free. If the RF AGC is permitted to rise, the picture will start to show some snow, which therefore represents less than optimum overall performance. If the setting is backed-off too much, the delay may be too large and mixer overload may occur at stronger signals. The correctness of this setting should be checked at weaker and stronger signals. At weaker signals, say 6.0 dB down, it should not be possible to improve the picture noise by resetting the RF Delay. At stronger signal, say 40 dB stronger, there should be neither snow or overload evident in the picture, although the distance between these two conditions, as a function of delay setting, may be very narrow. The AGC system should automatically avoid these troubles. It may be necessary to make a slight compromise to avoid overload, which may produce a slight amount of snow in the 1.0 mV picture. The above compromises can be achieved successfully without calibrated signals, with just a switch able attenuator and a strong signal. Starting at strong signal, note the available AGC Delay setting range between picture overload and snow. Using the switched attenuator, reduce the signal strength and make sure that neither problem appears. If necessary tweak the Delay, but don't move outside the original range. Eventually the picture will get snowy, but the control will only be able to make it snowier. Setting it to the optimum (just barely) should still be within tile noted range. Horizontal Output Transistor - The board was designed for a TO-3 type, such as a BU205, BU204, or MJ12003. A plastic TO-220 type MJE12007 will do the job with some mechanical revision. The important parameters are V(BR)CEX =1300 V and IC =2.0 A. A small amount of heat sinking, such as a U channel with 2 flags of 1 square inch each is recommended. A mica or Thermalloy isolator is suggested to reduce shock hazard to the experimenter. If an acldc design is contemplated, as referred to back in Figure 3, a lower voltage, higher current part like BU806 will be required for the horizontal output, along with a different yoke and ftyback. Vertical Output Transistors - It is possible to "get by" with a TO-92 complementary pair, such as MPS6560 and MPS6562, or the new, tall TO-92, MPSW01 and MPSW51. However, the author's opinion is that these operate too hot, with dissipation approaching 1 watt, each, worst case. Recommended alternatives include D40E 1 and D41E 1 in the TO-202, or TIP29 and TIP30 in TO-220. No heat sink is required. The devices need only V(BR)CEO = 30 V and good hFE at 1.0 A. Video Output Transistor - For the load value shown in this design, a case 152 uniwatt, such as MPSUlO, is best. The 300 V V(BR)CEO is not needed, but the device must be "small geometry"; i.e., high fT and low Ccb to preserve picture resol ution. A tall TO-92 or even an MPSA43, TO-92, can be used ifthe collector load is increased to 6.B k, but some picture quality will be lost. Audio Output Section - The transformer should be approximately 30: 1 turns ratio, capable of handling 1 watt into B.O n. The output transistor should be set up at about IQ = 12-14 mA, and should be capable of 1.5 W continuous dissipation. A TO-220 type MJE2360T, mounted on at least 3 square inches of aluminum is suggested. APPENDIX II - COMPONENT & CONSTRUCTION DETAILS In order to make the enclosed PC board pattern easy to use, the following components are recommended: Remember that these are pertinent to this design architecture and this specific design. Many variations are possible with a little redesign work. H. Driver Stage - In the prototype receiver, the available driver transformer had only about 12:1 turns ratio. This necessitated a large wattage dropping resistor to provide the rather low-voltage, high-current primary waveforms. It would be better to obtain a transformer of 30: 1 or so, to permit a more efficient driver stage. The 4.3 k/2.0 W resistor could then be reduced considerably. In either case a TO-92 driver, type MPSA42, is a good choice. Flyback - Gold Star Type 154-02BA with selfcontained H.V. rectifier. Certainly, substitution is possible, but very careful attention to pin-outs and taps is required. The primary is, of course, a 120 Vdc type, which corresponds to about BOO Vp _p positive pulse at Pin 2. Pin 3 is a negative going pulse of 35 V Pop and Pin 7 is a negative-going pulse of about 120 VPop' The H.V. terminal, which is internal in the above model, would be a positive going pulse of about 12 kVp_p' Very little flexibility can be permitted on these values. Be careful to watch pin-outs and horizontal polarity. SUMMARY: Figures 13 and 14 provide the copper pattern for the PC board and the component locations. Note that signal input circuits are compact and grounded near Pin 1. Subsequently these and all other circuits are connected to the central ground at Pin 16, without being interconnected beforehand. The full receiver schematic is given in Figure 15. Yoke -Gold Star Type 153-020A for 90° 12" 20 mm neck picture tube. It requires approximately 1.0 A p _p in both horizontal and vertical windings to give proper overscan in the 90° tube at 10-11 kV. This 155 ..... 01 m BRIGHTNESS CONTROL FIGURE 13 - Component Layout (not full size) H, YOKE ~ 0. 0. o o w [[ ::::J Cl u:: 157 . .~ w. ~ F~~';\A-: .. : ,a - I .,w 1~~7 t ,,- 1 .....~" ••• ,., tr ~ Lj .01 r If£ ~5 ...... en CD ''f'W FIGURE 15 - Complete Receiver Schematic AN925 UHF PREAMPLIFIER CENTERS ON BUDGET DUAL·GATE GaAs FET Prepared by Gary Barbari, Applications Engineer, RF Products and Steve Lazar, Principal Staff Engineer, Advanced RF GaAs Development* INTRODUCTION ating frequencies. Table 1 lists the required information for the MRF966. This note describes the design, construction and performance of a 400-512 MHz preamplifier utilizing Motorola's GaAs dual-gate field-effect-transistor. In two-way communications, the ability to receive a transmitted signal depends on the systems' signal-tonoise ratio (SIN). The SIN can be improved by increasing the output power of the transmitter; by increasing the gain of the antenna; or by improving the sensitivity of the receiver. The first two solutions could be quite expensive. A low noise preamplifier would be an economical solution for improving the receiver system noise figure. Parameter f = 400 MHz f = 450 MHz f = 500 MHz 511 521 512 522 fms fml NFmin dB 0.99 Lo 12' 1.60 L 165' 0.004 L83' 0.97 Lo7' 0.87 Lo 14' 0.8 Lo9' 0.9 0.98 Lo14' 1.59 L 163' 0.004 L84' 0.97 Lo8' 0.81 Lo20' 0.8 Lo 11' 0.9 0.98 Lo 15' 1.59 L162' 0.004 L85' 0.97 Lo9.4' 0.81 Lo 16' 0.76 Lo21' 1 TABLE 1 S-Parameter and NF Data @ VOS = 5 V, lOS = 10 mA DESIGN The main criteria in the selection of a transistor for a preamplifier is low noise figure coupled with sufficient gain to minimize the second stage contribution to the system noise figure. The Motorola MRF966 is a GaAs dual-gate field-effect transistor designed for UHF applications. Designing impedance transformation networks requires S-parameter and noise figure data at the oper- The MRF966 was matched by means of slug tuners to obtain the minimum noise figure. The optimum source (fms) and load (fm!) impedances were then measured on a network analyzer. The slug-tuned circuit used in this procedure is illustrated in Figure 1. V05 1--cF-->r-< RF Input ~,....--:::-----L.-=-....J >-To....:>H FIGURE 1 - NF Test Circuit 159 RF Output The network required to transform the optimum impedances to the required 50-ohm source and load was designed using a Smith Chart. The input matching network is shown in Figure 2. At the input of the preamplifier it is necessary to transform the 50-ohm input impedance to the optimum source reflection coefficient (fms). Taking the values from Table 1 for 450 MHz an input matching circuit can be designed using a series 450 n 50 C' +5.0 V FIGURE 2 - Input Matching Network A 0 . . . - - - - - - - - - 0 A' BO OB' CO 50 n Load Transformed by 9: 1 Transformer OC' #30 AWG Polythermaleze B A 450 n 50 FIGURE 3 - Output Matching Network FIGURE 4 - 160 n 9:1 Transformer n capacitance, shunt inductance, and shunt capacitance. Starting at the input of the device (rms), the shunt inductance moves the impedance to the value of 50 + j145 ohms (point A); (the shunt capacitor is used to fine tune the inductor along the constant admittance circle). Finally the series capacitance transforms point A to the desired 50 + jO ohms center (point B). The required reactance value for the three components can be obtained directly from the Smith Chart. From Figure 2 the shunt inductance moves the vector along the path to position A. This move requires an XL of 104.2 ohms. Therefore the shunt inductor has a value of 37 nH at 450 MHz. The shunt capacitor needs to be variable from 0.8-10 pF to accommodate variations between devices. The series capacitance rotates the input impedance from 50 + j145 ohms to the center of the chart (50 + jO) ohms at point B. Therefore, the required capacitive reactance is j2.9 or j145 ohms which leads to a value of 2.4 pF at 450 MHz. A variable capacitor (0.8-10 pF) will also be used here to fine tune the preamplifier for a specific frequency over the 400-512 MHz band. The output matching circuit could be designed using a shunt capacitor with a series inductor, but a more convenient matching technique involves a 9:1 transformer. This simple matching technique although not presenting the optimum load reflection coefficient (rLl to the MRF966 provides improved stability at the expense of slight gain reduction. The 50 ohm impedance of the load is transformed to a value of 450 + j150 (point C, Figure 3). The materials needed to construct the transformer are inexpensive and readily available. The lumped element form of the transformer and the winding procedure are shown in Figure 4. Source self-bias is used utilizing a 100 n resistor. The resistor will set the operating current at approximately 20 mAo Decoupling the source and Gate 2 is accomplished using 1000 pF and 56 pF chip caps. Gate 2 is positively biased using a simple voltage divider circuit. A low positive voltage on the gate will lower the noise figure and increase the power gain. The complete preamplifier schematic and the parts list are shown in Figure 5. J2 J1 RF INPUT t RF OUTPUT C1 1 C2 02 "::" "::" +7-15 V R2 R3 C1, C2 - 0.S-10 pF C3, C4, C7 - 1000 pF Chip Capacitor C5 - 56 pF Chip Capacitor C6 - 470 pF Chip Capacitor CS - 0.1 MFO Mylar C9 - 10 MFO Tantalum FTl - 1000 pF Feed Thru R1 - 150-0hm 0.125 Watt R2 -12-Kilohm 0.125 Watt R3 - 7.5-Kilohm 0.125 Watt Ll - 2 Turns No. 16 AWG 0.375" Diameter T1 - 4 Turns No. 30 AWG, Indiana General Core, F2062-1-01 U1 - MC7SL05 01,02 - 1N4001 01 - MRF966 Jl, J2 - SMA-Type Female Connectors B - Ferroxcu be Bead 56-590-65 FIGURE 5 - Schematic Diagram 161 Do same for the input shunt capacitor. Solder the 450 CONSTRUCTION n wire on the transformer (Wire A in Figure 4) directly The preamplifier is assembled on a 43 mm (1.7") x 38 mm (1.5") double-sided circuit board. The board material is 1.5 mm (0.062") Teflon-Fiberglass. A 1:1 photomaster of the top side of the board is shown in Figure 6. The under side of the board is used as a ground plane and the copper foil is not removed. A 0.2" clearance hole, centered between the device mounting tabs, is drilled to allow the MRF966 to fit flush with the pc board. This location is shown on the photomaster. The four sides of the board are wrapped with thin copper foil and then soldered on both sides. to the drain lead.' All of the components should be on the board. The preamplifier was built using "open chassis" construction as shown in Figures 8 and 9 from brass extrusion stock. This technique was chosen to allow visibility of the various components. SMA style connectors were utilized although other types are suitable at this frequency. Top of PCB FIGURE 6 - Pholomasler (nol full size) Handling precautions should be taken before mounting the MRF966. A grounding bracelet should be worn at all times when handling the device. A well grounded soldering iron should be used when soldering the FET. Before mounting, cut the gate, drain and source leads in half. Place the MRF966 (Figure 7) flush with the pc board (with marking face up) and solder the leads to the conductive tabs located on the board. Using tweezers, place the decoupling bypass chip capacitors as close to the device as possible. Installing the bias circuitry is very straightforward. The locations of the components are shown in Figure 8. Construction details of the 9: 1 transformer are shown in Figure 4. Solder the Coil (Ll) directly onto the Gate 1 lead and ground the other end. The placement of the coil depends upon the size and shape of the variable input capacitor (refer to Figure 8). FIGURE 8 TUNE-UP PROCEDURE Apply a voltage, between 7 and 15 volts, to the de input and check for 5 volts at the output of the voltage regulator and at the drain lead. Now adjust capacitors Cl and C2 for maximum gain. By using this maximum gain tuning procedure, a gain of about 20 dB with a noise figure of 0.8 dB at 450 MHz is obtained. To obtain a minimum noise figure (measured to be about 0.5 dB with an associated gain of 19 dB at 450 MHz) a commercial noise and gain analyzer is recommended, such as the HP8970A or Eaton 2075 Noise Figure Meters. With the noise analyzer in place, adjust Cl and C2 for best noise figure. The variable capacitors on the input of the preamplifier allow precise tuning at any frequency in the 400-512 MHz band. PERFORMANCE 1 2 3 4 ~ Drain ~ Source ~ Gale 1 Gate 2 ~ FIGURE 7 - The preamplifier was tuned for minimum noise figure at 430 MHz and 480 MHz using the HP8970A noise figure meter. The voltage was set at 12 V and the operating current was found to be approximately 20 rnA. The variable capacitors were adjusted to obtain a noise figure of 0.5 dB at 430 MHz and a value of 0.6 dB at 480 MHz. The gain at noise figure and noise figure optimum versus frequency curves are shown in Figures 10 and 11. Figure 12 shows the input and output return loss versus frequency for the preamplifier tuned at 430 MHz, while Figure 13 shows the same parameters at 480 MHz. Pin Configuration 162 A. Drill and tap for 4-40 screws. 3 places B. Drill and tap for 2-56 screws. 8 places C. Drill .125" hole. 2 places 4-A I.B3 0.03 II I -0.5 -.-- +B B+ 0.42 -<--t;------------~,.,...-J . f -0.25 .. ~ --0.17 :': -<'.c: I I 0.1 0.00 6 ,...... V 1 \ 4 2 \ /' 0 ......... I G ~p V i,\ '\ \ I'. 8 6 '" / NF - 390 410 L V 1\ 2.0 0 1.8 8 1.6 6 L I ,4 ~ ~ 14 1.2 :i! ~ 12 1,0 if ::::> ~ 0.6 i"l. '" '" ocl 0 / \t! z: 2 8 ~ <=JD... 6 0.86 \ ...-V -- "- I o . ~~-I 0.5 450 470 490 420 i2 g \. \ z: >- ~ -20 - 24 - 28 390 410 \ 430 2.0 GI .......... p 1.8 t"--. V I i'--, "'" N~ I /' - 4 ~ L I .2 I "- '" V ./ l'\ 1.0 £' w 0.8 ~ 0.6 z· 0.4 460 480 o 500 520 FIGURE 11 - Gain at Noise Figure and Optimum Noise Figure versus Frequency (Tuned @ 480 MHz) 0 ~ I -2 0 -2 4 450 470 -2 8 490 420 ~ ;5111 / '.L 11 \\ \\ /I i1 I I \ I 15221 \ I \ II ~ -I 6 ~ " (I '\. -I 2 440 460 480 500 f, FREQUENCY (dBI FIGURE 12 - Input and Output Return Loss versus Frequency (Preamp Tuned @ 430 MHz) FIGURE 13 - Input and Output Return Loss versus Frequency (Preamp Tuned @ 480 MHz) 163 520 164 AN932 APPLICATION OF THE MC1377 COLOR ENCODER by Ben Scott and Marty Bergan Linear I.e. Applications. Tempe. AZ The MC1377 is an economical, high quality, RGB encoder for NTSC or PAL applications. It accepts red, green, blue, and composite sync inputs and delivers IVpp composite ·NTSC or PAL video output into a 75 ohm load. It can provide its own color oscillator and burst gating, or it can be easily driven from external sources. Performance virtually equal to high cost studio equipment is possible with common color receiver components. The following note is intended to explain the operation of the device and guide the prospective user in selecting the optimum circuit for his needs. PREFACE Y = .59G + .30R + .11B R-Y = .70R - .59G - .11B B-Y = .89B - .59G - .30R Texts on the NTSC system will show that studio modulation is done on a different set of orthogonal axes called I and Q. Also they will point out that I is a somewhat wider bandwidth than Q. The MC1377 does not permit the circuit designer this refinement, but it should be noted that very few monitors or receivers contain any circuitry to process the unequal bandwidths. (This is the only compromise of standards in the MC1377 which cannot be circumvented by application means.) Rotation of the coordinate system from IIQ to (R-Y)/(B-Y) does not constitute any further compromise whatsoever, and it makes the encoding formulae for PAL and NTSC the same. It also aligns (B-Y) with the axis of the NTSC color burst, for internal circuit simplicity and system accuracy. Since this device has applications in color cameras, video games, video text and computer generated graphics, it may attract potential users who are skilled in computer architecture, but not familiar with the encoding of color television. Perhaps they have spent extensive hours viewing graphics on a full R, G, B wideband monitor. This preface is intended to caution that PAL or NTSC encoding, no matter how rigorously executed, will cause some degree of picture degradation. The process of encoding involves some bandwidth reduction, which means loss of high frequency detail, and it creates the possibility of spurious picture patterns, due to coding and decoding system limitations. The original standards were established about 25 years ago and will probably be in use for many years to come. It is not the objective here to detail these standards as many references l - 4 are available. Appendix A shows pictorially why some loss of information and detail is incurred. The MC1377 is capable of encoding NTSC and PAL to virtually studio standards. It also can be used for very low cost applications where appropriate, with some compromises to picture quality. It can readily drive the 750 input of a composite video monitor, or be used to drive a UHF or VHF modulator so that color television receivers can be used. REFERENCES 1. Donald G. Fink, Television Engineering Handbook, McGraw-Hill 1957. 2. Hazeltine Staff, Principles of Color Television, Wiley 1956. 3. Gerald Eastman, Television Systems Measurements, Tektronix 1969. 4. G. N. Patchett, Color Television, The PAL System, Norman Price 1976. CIRCUIT DESCRIPTION Figure 1 shows a block diagram of the color encoder. The three color inputs at Pins 3, 4, and 5 are matrixed to produce chrominance envelopes, (R-Y) and (B-Y), and luminance (- Y) by the standard NTSCIPAL formulae: 165 color bandpass transformer 8'>o-C""'/'v--, 1OOlsJ 0.1 4.43 0.1 12 MHz Composite Video Output 1 1 1 • a 001 I 51 k 8.2 V Composite Sync Input 15"F + + 15 "F R G 15 "F 1.2 k B '- ___ -.-___ delay line Inputs: 1.0 V p-p FIGURE 1 - BLOCK DIAGRAM AND APPLICATION CIRCUIT The (B-- Y) and (R- Y) signals drive two double balanced (double sideband suppressed carrier) modulators whose carriers are set at 0' and 90', respectively. In the NTSC mode, the outputs ofthese chroma modulators are added to produce composite chroma. Burst envelope or "burst flag" is applied to the (B--Y) modulator in the negative direction to produce a burst pulse at a reference angle of 180'. Composite chroma is amplified and buffered to Pin 13 (to permit external bandwidth control as desired) and is then fed back into the IC at Pin 10 to be combined with the luminance component. The luminance signal is also "looped out" from Pin 6 to Pin 8 to permit insertion of a delay line to match the delay incurred in the chroma channel due to bandwidth reduction. The passive components used in the chroma and luma channels are like those used in the most common implementation of color television receivers. In PAL mode, burst flag is driven into both modulators equally to produce a 225'/135' burst phase. The output phase, or polarity, of the (R- Y) modulator output is alternately switched from 90' to 270' on successive horizontal lines, before being combined with (B--Y), which remains at 0'. The switching of the modulator polarities for PAL mode is driven by the latching ramp generator through the PALINTSC control. This control allows PAL switching when Pin 20 is open, and stops when Pin 20 is grounded. The PAL phase can be detected at Pin 20 and controlled by means of external logic. The PAL phase can be reversed by sensing when Pin 20 is high and Pin' 1 is low, and momentarily pulling Pin 20 to ground with an external switch. The color subcarrier source for the modulators can be implemented by free running the on-chip crystal oscillator, or by external drive into Pin 17, or by a combination of both methods. The common collector Colpitts oscillator is completed by connecting a standard tv receiver color crystal and capacitor divider as shown. The oscillator is followed by a 90' phase shifter to provide the quadrature signal to the (R-Y) modulator. The direct oscillator output is taken as reference 0' and is fed directly to the (B--Y) modulator. The composite sync input at Pin 2 performs three important functions: it provides the timing (but not the amplitude) for the sync in the final output; it drives the black level clamps in the modulators and output amplifier; and it triggers the ramp generator at Pin 1, which produces burst envelope and PAL switching signal. The ramp generator at Pin 1 is a simple R - C type in which the pin is held low until the arrival of the leading edge of sync. The rising ramp function passes through two level sensors - the first one starts the burst pulse and the second stops it. Since the "early" part of the exponential function is used, the timing provided is relatively accurate from chip-to-chip and assembly-toassembly. Fixed components are usually adequate. The ramp continues to rise for more than '12 of the line in- 166 4. 4V t---- Limits for de coupled inputs (.1 1.0 V (p_pl (bl 100% Green Input (Pin 41 2.2 V 100% Red Input (Pin 31 1.0 V (p_pl (cl 1.0V(p_pl (dl terval, thereby inhibiting burst generation on "half interval" pulses on vertical front and back porches. Burst is also inhibited if sync is wider than the time required for the ramp to reach the sense levels, as is the case during vertical sync. The ramp method will produce burst on the vertical front and back "porches" at full line intervals. In most applications, this discrepancy from standards will not cause any problem. If it is objectionable, and if a proper burst envelope signal is available, then it can be injected into Pin 1 directly. Another method, suitable for either PAL or NTSC, will be described later. Inn n n W UUUL STANDARD INPUT LEVELS The signals into Pins 3, 4, and 5 should each be 1 Vpp for standard, fully saturated, color output levels as shown' in Figure 2. The levels are important because the IC will generate a predetermined 0.6 Vpp sync and 0.6 Vpp burst at the output, and it will need 1.0 Vpp input signals to produce the corresponding full luminance and chrominance amplitudes. The inputs are internally biased and present a 10 k input impedance. The 15/LF input coupling capacitors are sufficient to prevent tilt during the 50 or 60 Hz vertical period. Input signals can be dc coupled (to save the cost of the capacitors), provided that the signal levels are between 2.2 V and 4.4 V at all times. It is essential that the portion of each input which occurs during the sync interval represent black for that input, because it will be clamped to reference black in the color modulators and the output stage. A refinement such as a difference between black and blanking level must be incorporated in the RGB input signals if required. 100% Blue Input (Pin 51 5.0 Composite Output (Pin 91 4.0 3.0 (el B.2 Max 1.7 Min Sync 0.9 Max 0 -0.5 Min (fl II II II .. J I' I' -------------LJ- Input (Pin 21 THE SYNC INPUT As shown in Figure 2, the sync input can be varied over a wide latitude, but will require bias pull-up from most sync sources. The important requirements are that during the period between sync pulses, the voltage must be above 1.7 V and below the 8.2 V internal regulator. During sync, the voltage (negative going) must extend below + 0.9 V and should not exceed - 0.5 V (to prevent substrate leakage in the IC). For PAL operation, correctly serrated vertical sync is necessary to properly trigger the PAL divider. In NTSC mode, simplified "block" vertical sync can be used but the loss of proper horizontal timing may cause "top hook" or flag waving in some monitors. An interesting note is that composite video can be used directly as a sync signal, provided that it meets the sync input criteria. 10.5 Chroma Output (Pin 131 10.0 9.5 (91 4.35 Chroma Input (Pin 101 4.0 3.65 (hi 5.2h 4.3~ (i) ~ V- 2.St--"1 ~ 1 l..,..r""" 2.1 mE LATCHING RAMP (BURST FLAG) GENERATOR Luminance Output (Pin 61 The recommended application is to connect a close tolerance (5%) 0.001 J.tF' capacitor from Pin 1 to ground and a resistor of 51 k or 56 k from Pin 1 to the 8.2 V internally regulated supply (Pin 16). This will produce a burst pulse of 2.5 to 3.5 IJ.S in duration, as shown in Figure 3. As the ramp on Pin 1 rises toward the charging voltage of 8.2 V, it passes first through a burst "start threshold" at 1.0 V, then a "stop threshold" at 1.3 V, and finally a ramp reset threshold at 5.0 V. If the resistor is reduced to 43 k, the ramp will rise more quickly, producing a narrower and earlier burst pulse (starting about luminance Input (Pin 81 FIGURE 2 - SIGNAL VOLTAGES (Circuit Values of Figure 1) 167 ~5.0 ~ o >o.U E"O .. a: a:" ~ 1.3 1.0 0+=---¥~4--------------------4~~==~ ~U,',- L IPin2) o I I I I 5.58.5 Time IJLsl 50 63.5 FIGURE 3 - RAMP/BURST GATE GENERATOR 0.4 J.I.S after sync and only about 0.6 J.I.S wide). The burst will be wider and later if the resistor is raised to 62 k, but more importantly, the 5.0 V reset point may not be reached in one full line interval, resulting in loss of alternate burst pulses. . As mentioned earlier, the ramp method does produce burst at full line intervals on the vertical porches. This is not rigorously correct for studio applications. If external burst flag is available, a positive pulse of between 1.0 V and 1.3 V (absolute value) can be applied to Pin 1 in the NTSC mode. This approach must be handled carefully, because a square pulse smaller than 1.0 V will not trigger the burst generator, and a square pulse larger than 1.3 V will shut off the burst generator almost before it starts. This direct injection technique does not provide the ramp to operate the PAL flip-flop. Another method, suitable for either PAL nor NTSC, is shown in Figure 4. It requires a "vertical drive" pulse, starting at the leading edge of vertical blanking and as wide as the interval where burst is not wanted (usually 9 line intervals). The extra transistor and diodes in the circuit add an abrupt step at the beginning of each line ramp which inhibits burst generation. The oscillator drives the (B-Y) modulator and a voltage controlled phase shifter which produces an oscillator phase of90' ± 7' at the (R- Y) modulator. Ifit is necessary to adjust the angle to better accuracy, the circuit shown in Figure 6 can be used. Pulling Pin 19 up will increase the (R-Y) to (B- Y~ angle by about 0.25'/pA. Pulling Pin 19 down reduces the angle by the same sensitivity. The nominal Pin 19 voltage is about 6.3 V, so the 12 V supply is best for good control, even though it is unregulated. In most situations, the result of an error of 7' is very subtle to all but the most expert eye. For effective adjustment, the simplest approach is to apply RGB color bar inputs and use a vectorscope. A simple bar generator giving R, G and B outputs is shown in Appendix D. THE COLOR REFERENCE OSCILLATORIBUFFER RESIDUAL FEEDTHROUGH COMPONENTS As stated earlier in the general description, there is an on-board common collector Colpitts color reference oscillator with the transistor base at Pin 17 and the emitter at Pin 18. When used with a common low-cost tv crystal and capacitive divider, about 0.65 Vpp will be developed at Pin 17. The adjustment of oscillator frequency can be done with a series 30 pF trimmer capacitor over a total range of about 1.0 kHz. Oscillator frequency should be adjusted for each unit, keeping in mind that most monitors and receivers can pull in 1200 Hz. If an external color reference is to be used exclusively, it must be continuous. The components on Pins 17 and 18 can be removed, and the external source capacitively coupled into Pin 17. The amplitude at Pin 17 should be between 0.5 Vpp and 1.0 Vpp, either sine or square wave. As shown on the MC1377 data sheet (and in Figure 2 (d), the composite output at Pin 9 for fully saturated color bars is about 2.6 Vpp , output with full chroma on the largest bars (cyan and red) being 1. 7 Vpp. The typical device, due to imperfections in gain, matrixing, and modulator balance, will exhibit about 20 mV pp residual color subcarrier in both white and black. Both residuals can be reduced to less than 10 mVpp for the more exacting applications. The black imbalance is primarily in the modulators and can be nulled by sourcing or sinking small currents into clamp Pins 11 and 12 as shown in Figure 7. The nominal voltage on these pins is about 4.0 Vdc, so 8.2 V is capable of supplying a pull up source. (Pulling Pin 11 down is in the 0' direction, up is 180'. Pulling Pin 12 down is in the 90' direction, up is 270'.) It is also possible to do both; i.e., let the oscillator "free run" on its own crystal, and also be capable of being overridden from an external source. An extra coupling capacitor of 50 pF from the external source to Pin 17, and a signal of 1.0 Vpp was adequate with the limited experimentation attempted. VOLTAGE CONTROLLED 90' 168 +8.2 V 47 k °U - - - - -8.0 V 1-9H~ MC1377 47 k 2.2k Vertical - - Drive Pulse = FIGURE 4(_) - FIGURE 4(c) - = 6.8 k .001 51 k VERTICAL PERIOD BURST INHIBITOR STANDARD RAMP CIRCUIT FIGURE 4(8) - BURST INHIBITOR RAMP CIRCUIT INOTE FAINT RAMP CAUSED BY VERTICAL DRIVE PULSE) 169 o.e In ""'" ,. OIcOut 17 V --, 010 V 5.Ok 19 Deeoup ~" 71~l--+-+-+.JI . , - _...... ~r1-r+------ ~ ~. +~ T Go' R2J ~l915k t 02 1.211. AlA 1.011. A3 6.811. 013 2" Rll 22k R12 10k "7 A71 2" ~" RllS 10k - AOO '" R113 '" r-- Al14 20 R120 117 10k ~7108 "t-"'" Rll' 5.3k lo, ,".12 18k rJ. R12J J9k m fiGURE 5 - 170 Rl26 2111. R129~ lS II. ChI'OlNl Out 22k 27k R29 R33 R34 r ,..C;- T4~ ~c J:Tl J:' T48 220 '00 t..!:'" - L..---Yrns R127 27k R1JO R13l '.9k '4 k " I-t:~'~:h nl~ R'25 12.5k Rl63 10k '" R,S7 R147 22k 27k Rl37~'~ 15kTl'S ~R:~~ nl6 0'34 220 2';,'''12 "13 '''[MR ~ r " R., 10k " J= A-VCMimp 12 Chromlln 10 JO''0N0 ml R'" 10k R'S9 lOr. R52 'Ok ,,~ I L- I~~~ 220 R49 'Ok R45 R'" 4.7k R13S R124 12.5 J R44 22k n21 0'53 220 VI_Damp 7 R145 40k Uk R'Sl B.H ?"',9 ~}7'7k 470 470 Rl40 R14l R138 • Composite Video Out R'" 220 220 Rl39 "k 22k 16k 0'52 .,. , , _______________________________ r ~ Tl~ Rl55 R'.=,85 R1J2k R43 10k ~ n ~ R38 'Ok . ~ 4.7k v " ~ r - , R28 ,I 10k ~ I22k 1:1 pass circuit between Pins 13 and 10. For proper color level in the composite output, a mid-band insertion loss of3.0 dB is desired. The bandpass circuit shown in Figure I, using the TOKO fixed tuned transformer (see Appendix B) gives this result. One of many tv color IF bandpass circuits could also be used. When such a bandwidth reduction is inserted, the chroma is delayed by approximately 350 ns (as shown in Figure 8). This 350 ns delay results in a visible displacement of the color and black and white information on the final display. The solution is to place a delay line in the luminance path from Pins 6 to 8 to realign the two components. Again, a normal tv receiver delay line can be used. These delay lines are usually of 1.0 k to 1.5 k characteristic impedance, and the resistors at Pins 6 and 8 should be selected accordingly. A very compact, lumped constant delay line is available from TDK (see Appendix C for specifications). Some types of delay lines have very low impedances (approximately 100 ohms) and should not be used, due to drive and power dissipation requirements. In some applications, it may be possible to delete both the bandpass transformer and the delay line. For instance, when the RGB information itself is very low resolution, i.e., very narrow band (less than 1.5 MHz), no cross-talk would be generated in the encoder (see Figure 9). Keep in mind, however, that the standard monitor or receiver will still "see" an incorrect luminance sideband at X'. This points up the value of at least some chroma bandwidth reduction in the encoder. A simpler, lower cost bandpass circuit is shown in Figure 10(a). It provides the proper insertion loss, approximately ± 1.0 MHz bandwidth, and about 100 ns delay. The circuit shown in Figure lO(b) is even less costly, but has about 6.0 dB greater loss, provides very little bandwidth reduction except to remove the baseband feedthrough, and produces essentially no delay. Any direction of correction may be required from part to part. (Note that pulling Pin 11 up can produce a residual carrier on the horizontal back porch which is the same phase as burst, and can result in an almost normal color display even with burst not present.) +12 V ~--'--'1~~"il0k I 1.Q1 FIGURE 6 - ADJUSTING MODULATOR ANGLE +8.2 V 470 k 12}--....- - - - \ M - - -......~10 k 11}-~----~~~------~10k 470 k +8.2 V FIGURE 7 - NULLING RESIDUAL COLOR CARRIER IN BLACK LU~ I I Chroma: x c: 'iii FIGURE 8 ---+------... X (.:J 1.0 White carrier imbalance at the output can only be corrected by juggling the relative levels of R, G and B inputs for perfect balance. Standard devices are tested to be within 5% of balance at full saturation. Black balance should be adjusted first, because it affects all levels of gray scale equally. There is also usually some residual baseband video at the chroma output (Pin 13), which is most easily observed by disabling the color oscillator. Typical devices show 0.4 Vpp of residual luminance for saturated color bar inputs. This is not a major problem since Pin 13 is always coupled to Pin 10 through either a bandpass or a high pass filter, but it serves as a warning to pay proper attention to the coupling network. 2.0 3.0 3.58 4.0 5.0 la) ENCODER OUTPUT WITH LOW RESOLUTION INPUTS AND NO BANDPASS TRANSFORMER 1.0 2.0 3.0 3.58 4.0 5.0 Ib) STANDARD RECEIVER RESPONSE FIGURE 9 It will be left to the designer to decide which, if any, compromises are acceptable. Color bars viewed on a good monitor can be used to judge acceptability of step luminance/chrominance alignment and step edge transients, but signals containing the finest detail to be encountered in the system must also be examined before settling on a compromise. THE CHROMA COUPLING CIRCUITS Without going deeply into the subject, it is generally true that monitors and receivers have color IF 6.0 dB bandwidths of ±0.5 MHz. It is therefore recommended that the encoder should also limit the chroma bandwidth to approximately ± 0.5 MHz through insertion of a band- 172 0.001 0.001 Pin~f--'V\I'Ir--""'''''''--i~10 (a) Insertion Loss: 3.0 dB Bandwidth: :: 1.0 MHz Delay: ~ 100 nsec 56 pF ~ M~';;torl MC1377 = 1.0 k 0.001 FIGURE 11 Pino;;-if--'W'\r-......-.----:l~ 10 4.7 k (b) Insertion Loss: 9.0 dB Bandwidth: :: 2.0 MHz Delay: 0 printed circuit board will be even more effectively cooled. The MC1377 is designed to operate from an unregulated 10.8 to 13.2 volt dc power supply. Device current into Pin 14 with open output is typically 30 to 32 mAo .To provide a stable reference for the ramp generator and the video output, a high quality 8.2 V internal regulator is provided. The 8.2 V regulator can supply up to 10 mA for external uses, with an effective source impedance of less than 1.0 ohm. This regulator is convenient for a tracking dc reference for dc coupling the output to an RF modulator. Typical turn-on drift for the regulator is approximately + 35 m V over 1-2 minutes in otherwise stable ambient conditions. = FIGURE 10 - OPTIONAL CHROMA COUPLING CIRCUITS THE OUTPUT STAGE The output amplifier normally produces about 2.0 Vpp and is intended to be loaded with 150 ohms as shown in Figure 11. This provides about 1.0 Vpp into 75 ohms, an industry standard level (RS-343). In some cases the input to the monitor may be through a large coupling capacitor. If so, it is necessary to connect a 150 ohm resistor from Pin 9 to ground to provide a low impedance path to discharge the capacitor. The nominal average voltage at Pin 9 is over 4.0 volts. The 150 ohm dc load causes the current supply to rise another 30 rnA (to approximately 60 rnA total into Pin 14). Under this (normal) condition the total device dissipation is about 600 mW. The calculated worst case die temperature rise is 60'C, but the typical device in a test socket is only slightly warm to the touch at room temperature. The solid copper 20-Pin lead frame in a SUMMARY The preceding Application Note was intended to detail the application and basis of circuit choices for this versatile tv signal encoder. A complete MCI377 application with the MC1374 VHF modulator is shown in Figure 12. The internal schematic diagram of the MC1377 is provided in Figure 5. Iffurther assistance is needed, contact Motorola Linear and Military IC Division, Applications Engineering. 3.58 ':.J-__.....-f-ll" MC1374 4 MC1377 .001 r-~~f--+---lHI " defitvllne 14 75 " ® ..olar VIdeo 1'1219157 0.1 .01 ":" Audio 0"' bandpass transformer + 12IJdc J;'O .01 (see Appendix 81 FIGURE 12 - 173 APPLICATION WITH VHF MODULATOR APPENDIX A In full RGB systems, three information channels are wired from the signal source to the display to permit unimpaired image resolution. The detail reproduction of the system is limited only by the signal bandwidth and the capability of the color display device. Higher than normal sweep rates may be employed to add more lines within a vertical period. Three separate projection picture tubes can be used to eliminate the "shadow mask" limitations of a conventional color CRT. Figure (b) below shows the "baseband" components of a studio NTSC signal. As in the previous example, energy is concentrated at multiples of the horizontal sweep frequency. The system is further refined by precisely locating the color subcarrier midway between luminance spectral components. This places all color spectra between luminance spectra and can be accomplished in the MC1377 only if "full interlaced" external color reference and sync are applied. The individual components of luminance and color can then be separated by use of a comb filter in the monitor or receiver. This technique has not been widely used in consumer products, due to cost, but it is rapidly becoming less expensive and more common. The unequal bandwidths of I and Q cannot be implemented with the MC1377, first because I and Q axes are not used, and second, because outputs of the two color modulators are added before any bandwidth reduction is imposed. Most monitors and receivers compromise the "standard" quite a bit, by using responses as shown in Figure (c). Some crosstalk ofluminance information into chroma, and vice versa, is always present. The acceptability of the situation is enhanced by the suppression of the color carrier and the generally limited ability of the CRT to display information above 2.5 MHz. If the signal from the MC1377 is to be used primarily to drive conventional non-comb filtered monitors or receivers, it would be best to reduce the bandwidth at the MC1377 to that of Figure (c) to lessen crosstalk. Spectral Energy Is Always Concentrated At Horizontal Sweep Frequency Multiples Chroma Channel Red Gain ~-----..... L.uminance Channel I G~" ~111I"'lt'" I I Blue ~1I"nIIiT 1.0 I : l 1 2.0 1 3.0 :~ D 1.0 FIGURE FIGURE 13(c) - D n SPECTRA OF A FULL RGB SYSTEM 'feiIOIN . 8.8 - Q Luminance ~ .~ ~ " VI TYPICAL MONITORfTV -::;." (R-Y) ~ '&. (90°) 4-8 ...o 3.0 3.58 4.0 f(MHz) f(MHz) FIGURE 13(a) - 2.0 I I I "0 (7680) .~ " .. o " VI.Q VI " c \ Color Burst ~ \ \ (B-Y) 0° (180°) '" .€ "0 Q. E « g "0 >lillJWllWllIllli.ljl.UWllUillIoW a 1~ ~o ~o FIGURE 13(d) - COLOR VECTOR RELATIONSHIP. IfQ SYSTEM versus (R-Y)f(B-Y) SYSTEM SHOWING STANDARD COLORS f(MHz) FIGURE 13(b) - NTSC STANDARD SPECTRAL CONTENT 174 APPENDIXB A PROTOTYPE CHROMA BANDPASS TRANSFORMER TOKO SAMPLE NUMBER 186NNF-10284AG 0.7 mm Pin Diameter Toko America 5552 West Touhy Avenue Skokie, IL 60077 (312) 677-3640 Connection Diagram Bottom Viaw Unloaded a (Pin 1-3): 15 @ 2.5 MHz Inductance: 30/,H ± 10% @ 2.5 MHz Turns: 60 (each winding) Wire: #38 AWG (0.1 m/m) APPENDIX C A PROTOTYPE DELAY LINE TOK SAMPLE NUMBER OL122401D-1533 I' 1.26 Max 32.0 "I ---- '-' '-' '-' "Marking -~t---... 0.788 ± 0.08// 20.0 ± 2.0 I 0 ~ I- foil II b / T 0.93 Max 23.5 - ,O~,.~", ~: -=: .=°1="·~: :U; -_·1- j i -I; H + t ! 0.04 0.2 ± 5.0±1.0 y. 0.35 Max 9.0 """.00' 0.65 ±0.03 I 0 r--I f--~ I - ~ 0.08 Radius Max TDK Corporation of America 2.0 4711 Golf Road Skokie, IL 60076 (312) 679-8200 "MARKING: PART NUMBER, MANUFACTURER'S IDENTIFICATION, DATE CODE AND LEAD NUMBER. Item 1 Time Delay Specifications 400 ns ± 10% 2 Impedance 1200 Ohms ± 10% 3 Resistance Less Than 15 Ohms 4 Transient Response with 20 ns Rise-Time Input Pulse I-P_re_-S_h_o_o_t_:_10_0_IIo_M_a_x_ _ _ _ _ _ _ _ _ _ _ _ _--i Over-Shoot: 10% Max Rise-Time: 120 ns Max 5 Attenuation 3 dB Max at 6.0 MHz 175 APPENDIXD AN RGB PULSE GENERATOR BNC 4.7 "F 10 k 1S~.I'"-+""""""......-.t 10 k Composite Blinking 2.2 k +5.0 V Reg. MC74LS112A 3.3 k MC1455 112 MC74LS112A 0.1 ~ 2.2 k 0.1 14 ~ l1J 5 Q9'1--+......-I 3.3 k 750 pF 1.8 k 470 RGB PULSE GENERATOR TIMING DIAGRAM ~ (From Composite Blanking) 154 kHz Clock Blue Output Red Output ----,'------' Green Output ----,~------------~ 176 AN1019 NTSC Decoding Using the TDA3330, with Emphasis on Cable In/Cable Out Operation Prepared by Ben Scott and Khalid Shah Bipolar Analog Ie Division PREFACE THE SANDCASTLE INPUT The TDA3330 is a composite video to RGB Color Decoder originally intended for PAL and NTSC color TV receivers and monitors. The data sheet is oriented toward picture tube drive, rather than cable level outputs. This application note is intended to supplement the data sheet by providing circuits for video cable drive, such as used in video processing circuits, frame store, and other specialized applications, and to expand upon the functional details of the TDA3330. "Sandcastle" is a familiar term to European TV engineers. It is basically a 0 V baseline with a 4.0 V blanking pulse and a 10 V burst-gating pulse on top of it, as shown in 'Figure 1. Sometimes the expression "super sandcastie" is used, which means that composite blanking is present, i.e. vertical and horizontal blanking, in addition to the burst-gating pulse. Sometimes the vertical blanking is 2.5 V and the horizontal is 4.0 V, sometimes both are at 4.0 V. In the TDA3330, the blanking portion is only used to provide a blanking waveform at the blanking output, Pin 11, which is used to supply "extra" blanking in the picture tube driver application. Pin 11 is not used in other applications, so the blanking portions of the "sandcastle" are not required. For the "cable to cable" decoder, all that the TDA3330 really needs at Pin 15 is the burst-gate pulse. Pin 16 should be grounded. The burst-gate pulse has 3 functions: CIRCUIT CONSTRUCTION TECHNIQUES The best solution is a single or double sided PC board, such as shown in Figure 11, with as much ground plane as possible. The oscillator components at Pins 8 and 9 must be close to the pins. A low profile socket is acceptable for prototyping. Wirewrap is definitely not recommended. In most respects the part is not sensitive to layout, except for the oscillator, however, unwanted picture artifacts, beats and noise are much easier to control with a good ground plane layout. 1. Gating the color IF gain control (ACC) so that IF gain is adjusted to keep burst amplitude constant; 2. Setting the black level in the R, G, B outputs, and 3. Gating the color phase detector (APC) so that the VCO can be phase-locked to the burst. See the block diagram in Figure 2. MEASURING THE OSCILLATOR The oscillator amplitude at Pin 9 should be about 400 mV pp , measured with an ordinary 4.0 pF/10 Mil scope probe. Keep in mind that the oscillator frequency is 3.58 MHz and is part of a phase-locked loop with only a few hundred Hz pull-in range. The scope probe loading is enough to push the oscillator into or out of lock. It is recommended that Pin 9 be observed initially to ascertain that it is running, and then leave Pins 8 and 9 alone. A procedure for adjustment will be covered later. Of course, an output buffer (emitter follower) can be connected to Pin 9, permanently, and the Pin 9 tuning capacitor reduced accordingly. 10 40 I I I I I I I I - - BLANKING BASELINE ~ mJi ~.lllITnril i1 ~ Figure 1. Sandcastle 177 COMPOSITE VIDEO CO~6~~1TE o---.....- - l INPUT SANOCASTLE OR BURSTGATE INPUT LUMINANCE IYI INPUT 17 12 OUTPUT MATRIX CHROMA IF OUTPUT 13 OUTPUTS 14 Figure 2. Simplified Block Diagram for NTSC Mode It is important that the burst-gate pulse into Pin 15 be at least 8.0 V and timed correctly with respect to incoming video, as shown in Figure 3. If the gate pulse is too late or too wide it will still be present after the blanking has ended, leading to serious errors in black level, color level and VCO lock. The burst-gate pulse can sometimes be obtained from the same equipment that supplies the video, or it can be generated by a couple of one-shots and a sync separator; see Figure 4. Another method is to separate sync. Use a one-shot pulse stretcher to make an 8-8.5 !,-S wide pulse for Pin 15, and then put the separated sync into Pin 16. (Pin 16 could be called the "burstgate inhibit"). This will prevent the first part of the Pin 15 pulse from gating sync, which would upset the black level clamping function; see Figure 5. at maximum at 5.0 Vdc; the output is reduced 6.0 dB . when the control is 3.5 Vdc, and is reduced about 40 dB when the control voltage is 1.0 Vdc. BLANKING 1 . - - - - 1 1 1 / ' s - - -.....--I SYNC :::U:t 50~OI'S ~ THE LUMINANCE PATH The outputs at Pins 12, 13 and 14 are positive-going video, with the sync pulse almost completely' removed. The black level of the output remains constant as the contrast, saturation and hue are changed. The contrast control changes both luminance and chrominance together, so that, for example, output color bar waveforms maintain the same shape. The DC level of all outputs is moved by the brightness control, with no change in the peak to peak signal amplitude. The brightness control can change black level from 1.4 V to about 6.7 V as the control voltage on Pin 18 is raised from about 2.0 V to 5.0 Vdc. See Figure 6. The contrast control, Pin 19, is B.OV MIN - .----, 10-3.5/,s BURST·GATE WIOTH Figure 3. Burst-Gating 178 Idl COMP VIDEO VVIDEO ilCLAY + GATE WIDTH 5.0V o---.~:;:==~-----==::;----' I II /, :.A'" 1.7 k --U--;-SYNC 0.0039 I II ~DELAY II n i d i BURST· L...::.GATE ----.J -12Vo---.--~---.--~ BURST·GATING PULSE TO TOA3330 PIN 15 22k ',. MC3346 TRANSISTOR ARRAY Figure 4, Method of Obtaining Burst-Gate from Composite Video The maximum output voltage, black to white, is about 7 times greater than the black to white level at Pin 17. For a composite input signal of 1.0 V pp ' there is 0.5 Vpp at Pin 17, due to the delay line matching resistors. This is about 0.35 Vpp white to black and gives about 2.5 Vpp max at the outputs. The input to the total circuit can be doubled to 2.0 V pp ' which then yields about 5.0 Vpp at Pins 12, 13, and 14. However, note that any change in input amplitude requires readjustment of the saturation control for correct chromailuma proportion. This is because the luminance component directly follows the input, while the color component is almost unchanged ,', SYNC SEPARATOR due to the ACC of the color IF. Therefore, it is important to note that the TDA3330 can be ·set up to work with different levels of input, but it is not automatically compensated for input changes. Also note that at 5.0 Vpp out and max brightness (black level out 6.7 V) there will be clipping of the positive peaks. The upper limit for the output is about 10 V. Troubleshooting note: If a proper (positive) video signal is AC coupled into Pin 17, and a proper burst-gate is applied to Pin 15, there should be video out, regardless of any aspects of the color processing portions of the IC V'" J-H,-_S_TR_P~_i~_~_ER_.J:I----"" BUR;TO;l~E'~NPu T I TO PIN 16 'BURST·GATE INHIBIT INPUT VIDEO ~ ,v-o Ib' SYNC 'BV=rL Ie' STRETCHED o Figure 5. Alternate Method of Gating from Video 179 SYNC THE CHROMA PATH The chroma input is derived from the composite input by a simple 3.58 MHz single-tuned bandpass circuit with about ± 0.5 MHz (6 dB) bandwidth. The chroma portion of a color bar pattern should look like Figure 7. The circuit components recommended in our application circuit should yield about 100 mVpp of burst at Pin 22, but anything from 10-200 mVpp will work. The output of the chroma IF is at Pin 24, where the burst shculd be about 150 mVpp. There mayor may not be chroma present, depending on the contrast and saturation control settings. (Both controls have exactly the same effect at Pin 24, changing the picture chroma amplitude between the burst pulses.) GREEN OUTPUT PIN 13 - NORMAL BRIGHTNESS CHANGES BLACK LEVEL fROM 1 4 V TO 6.7 V WITHOUT CHANGING p.p CONTRAST CHANGES p.p AMPlITUOE WITHOUT MOVING BLACK LEVEL WHITE , ,,~vRE CHROMA IADJUSTABLE AMPlI'UDE' BLACK Figure 7. Chroma IF Output, Pin 24 Troubleshooting note: If there is 1.5 Vpp of burst at Pin 24, the burst-gating pulse is either too small or incorrectly positioned in time. The chroma IF output from Pin 24 is coupled to the chroma demodulators, Pins 4 and 5 by a small capacitor. (Note: 100 pF performs better than tr,e 1.0 nF on the data sheet; it reduces luminance component feedthrough.) Tweaking of demodulator balance to reduce residual chroma subcarrier in the outputs can be done at Pins 4 and 5 by the trimmer technique shown in Figure 8. This is a fine tuning which is usually not needed, but is available for the demanding application. U n wiWn nU nU B r--1>----l 24 RlIHliTI 1k C U T PIN '2 SATURATION TOO HIGH 56k ,OOk IV BLUE OUTPUT. PIN 12 HUE MISADJUSTED 47pF Figure 6. Some Normal and Other Waveforms Figure 8. Optional Tweak of Demodulator Balance 180 OUT OF LOCK - 600 mVpp IH+· 63.5", f.- HORIZO~TAL PERIOD Figure 9. veo Lock - Voltage at Pin 7 COLOR LOCKUP APPENDIX If the required chroma is present at Pins 4, 5 Isame as Pin 24). and if the oscillator is known to be running, then lockup is just a matter of adjusting the trimmer ori Pin 9. As noted earlier, the scope probe cannot be put on the oscillator for this adjustment. Instead, put the scope on the AFC filter, Pin 7. Waveforms as shown in Figure 9 will be observed as the trimmer is adjusted. Lock-in range is about 18-22 pF with the typical socket and PC board and ordinary IRadio Shack) 3.58 MHz TV crystal. Initial Setup Sequence for TDA3330 Evaluation Board After connecting a Composite Video Signal In and connecting the Sync, Red, Green and Blue outputs to an appropriate RGB monitor, follow the subsequent steps, in order, to adjust the 11 variable components to optimize performance of the RGB decoder: 1. Look at the signal out of the collector of the 2N4402 transistor. Adjust POT #9 so that the Composite Video Signal at this point is 1.0 Vpp. 2. Set POTS #2 and 3 to approximately the middle of their values Ii.e., 50 kfl). This helps in making the subsequent adjustments. BUFFERING THE OUTPUTS In order to be able to drive a cable, it is necessary to provide an output amplifier. The design shown in Figure 10 has two additional benefits: 3. POT #7 sets the Burst-Gate Width and POT #8 sets the Burst-Gate Delay relative to the Video Sync Signal. Use a dual input oscilloscope and look at the Video In signal and the Burst-Gate Signal at Pin 15 of the TDA3330. Adjust POT #8 so that the Burst-Gate Signal begins -·250 ns after the Sync Signal ends. Next adjust POT #7 so that the width of the Burst-Gate Signal is 3.5-4 IlS. Note: See Figure 3. 1. It provides an opportunity to reduce the residual 2nd harmonic ofthe color subcarrier 17.16 MHz) by means of a trap, and 2. It reduces the DC level another 0.7 Vdc at the emitter of the 2N4401, and an additional 2:1 reduction due to the 75 n series R into the 75 n cable. Therefore, the black level into the cable can be as low as 0.35 V, for the minimum brightness control setting. 4. Put the oscilloscope probe on Pin 7 of the TDA3330. Adjust the Variable Capacitor, connected to Pin 9, until the VCO is In Lock. This will happen when the trace signal drops from -650 mVpp to less than 100 mVpp. Try to make the signal as small as possible, possibly down to dc. (Make tilt flat) Note: See Figure 9. MISCELLANEOUS GREMLINS It has been reported from the field that the internally supplied NTSC mode switch current 113 in Figure 12 of the data sheet) is occasionally insufficient. This is characterized by a decoder which intermittently decodes and then "color kills." In the killed mode, Pin 3 is above 1.5 V and Pin 2 is below 0.7 V, which holds the saturation controllow loff). This can be fixed by putting 22 k from Pin 3 to VCC. This supplies additional current into Pin 3, causing an internal latch to pull Pin 3 low Ihave faith), and returns Pin 2 to an open state so it can be varied by the Saturation control. 5. Put the oscilloscope probe on Pin 17 of the TDA3330. Adjust the 10 IlH Variable Inductor to minimize Chroma Signal Feedthrough. 6. In order to fine tune chroma demodulator balance, remove the chroma signal from the Composite Video Signal In lor, alternatively, turn the Saturation POT all the way down). Look at the Red output on the oscilloscope and adjust POT #2 to minimize subcarrier from the V Signalli.e., R-V) input. Next look at the Blue signal and adjust POT #3 to minimize subcarrier from the U signal Ii.e., B-V) input. SUMMARY 7. POTS #1,4,5 and 6 can next be adjusted to optimize picture color quality. Suggestion for doing this is to set Saturation IPOT #1) and Brightness IPOT #5) to middle and then adjust Contrast IPOT #4 and Hue POT #6) till picture colors are approximately right. Next adjust POT's 1 and 5. Repeat the above sequence until satisfied with color quality of picture. The TDA3330 has a wide range of functional capability with relatively simple application circuitry lance understood). It is hoped that this paper will assist users in becoming familiar and satisfied with it. 181 I~v-----------------I r-------------~ I 0.1 I 1m I I ~ I !If_'~7:F 011 ~I I 39k 2 ,: kO I I 2N44_0_0_..... L I I I 470 4.7k I 10 k I I l~P~N~I~T AMP~E~ _ _ _ =-__ J I I I I 2.2k BURST·GATE & SYNC OUT GENERATOR ______ =-___ J 400ns OELAY LINE 12k ~ ~2k 12 Vdc 15 k B2 IBM 24 23 22 21 20 19 1B '7 'NOTE RED & GREEN OUTPUT CIRCUITS ARE IDENTICAL TO BLUE OUTPUT ORIVE CIRCUIT 16 -5Vcc 50k SATURATION II 10k TDA3330P 12 -12 Vdc 220k 33 r-----------, I ·12 Vdc I I I I I I I I I I I I I I I I I I ONBOARO 5 V REGULATOR 1000 1Bk ----..., I I ,J.l0,uF ) " I L____ _ l... ______ _ ., 47 1.Ok I I I NOTE: 5.0 V Regulator IS induded for convenience and for the SN74LS221N. If the TDA3330P is to be operated from unregulated 12 V, the controls should be operated from unregulated (tracking) 5.0 V. I ~ I ___________________ I L Figure 10. TDA3330 RGB NTSC Decoder Circuit 182 2N4401 75 150 BLUE OUTPUT 1 NOTES~ 1. For the 390 pF and the 22 pF capacitors in the 3.58 MHz and in the 7.16 MHz traps. silver mica capacitors should be used for better trap performance. '. 2, The board layout is for Toko part #BTKANS-9439HM . ...3. Board layout will accommodate a Toko or a TDK 400 ns delay line. 4. A.3.58 MHz crystal available through Radio Shack was used. Figure 11a. TDA3330P RGB NTSC Decoder Evaluation Board, Component Layout 183 1':' . i· ~:i 1 .. 11 ••. . " . . I ........ ... .. ........... -_ ... ..•,._.. .. ...- ...- -.....--- _..... ..... . ••• • '" ....... -~ .. . • _ • ••• IEI1Ii!lB • •• •••• • ~ I. I ~- .....- • ••• •• ........ ..I •• ••• 1.... - - - - - - - - - - - 4.000" I, -----------·~I Figure 11 c. TDA3330 RGB NTSC Decoder Evaluation Board, Bollomside (not full size) 184 Figure 11b. TDA3330 RGB NTSC Decoder Evaluation Board, Component Side (not full size) AN1020 A High-Performance Video Amplifier For High Resolution CRT Applications I. INTRODUCTION The emitter followers provide a combined output signal from a low Impedance, or "stiff" source. ThiS stiff source makes the entrre circuit Insensitive to load variations and to different methods of connect· ing the Video amplifier to the CRT. This application note describes the superior performance characteristics of Motorola CRT driver transistors in a state-of-the-art video amplifier. In particular, the high speed obtainable with low DC power consumption is shown. A circuit which is insensitive to load variations and interconnect methods is given. III. THE CIRCUIT A. The Input Circuit II. APPROACH The performance requirements for the amplifier are these: Voltage Gain Rise and fall times Output Overshoot Load capacitance Power supplies 20 3 nS 40 V p.p min. 5% max. 8 pF min. 60 V. 5 V. - 5 V The voltage gain IS obtained In a transconductance amplifier In the form of a common-emmer, common-base cascade CIrcuit. In this crrcuit the load capacitance is Isolated from the casco de by a set of complementary emitter ·followers. Thus, the capacitive loading on the cascode IS low. which allows operation at a moderate dissipation level. The emlller followers are biased at a Class "8" operating pOint. They conduct only dUring voltage tranSitions. while charging or discharging the CRT capacitance. ThiS operation IS Similar to the way highly effiCient C·MOS logic ICs functIOn Refer to the cirCUit diagram In Figure 1. A fast pulse generator is required for accurate performance data_ The Tektronix Model PG502 IS a good example of a pulse generator for optimum perlormance, versatility and p"ce considerations. The pulse generator has a rise time in the range of .8 ns and an output impedance of 50 ohms_ A minimum-loss L-pad IS used between the generator and the base of the driver transistor, Ot. The Impedance level at this pOint is designed to be 75 ohms. The voltage attenuation of the matching crrCUlt IS 0.64. B. The Cascode Circuit 1. The Common-emitter stage uses an LTlool transistor In a TO-39 package. The em mer current of 70 mA IS supplied from a - 5 V source via resistors .R4, and R5. For ac, only R4 at 15 ohms IS operative. R4 and the bUilt-in emmer-ballast resistor of 1.6 ohms, determine The transconductance of 01, which IS then 60 mAN. 80th the emitter current and the collector current of thiS stage follow the base voltage almost instantaneously. Computer simulation has shown that the transition times are less than 1 ns. The transconductance may be Increased during the transition times by adding the "peaking-network" R6, C2, C3. Adding thiS network is very much Irke adlustln9 the rise time in the probes of fast oscilloscopes. In the cascade circuit under discusSion the "peaking" network compensates lise time deterioration at the collector by speeding up the emitter current of Ot. ThiS procedure must be applied with moderation ~nce it may aHect the large-signal swing capability. The resistor, R6, should be equal to or larger than R4. The capacitor, C2, determines the length of time dw'ng which "peaking" occurs. The product of R6 and C2 is typically a few nanoseconds. The trimmer, C3, can be used for fine-tuning, but is usually not important and may be omitted. If there IS lead inductance associated With the path from the emitter of Ot through C3 to ground, use of C3 may cause ringing at high frequencies. 2. The common-base stage uses an LT1817 transistor In a TO 11 7 package. Since the transistor must dissipate continuously some two Watts of DC power, good heatsinklng IS mandatory_ The TO-117 package provides a hlghconductance thermal path to a heatsink or chaSSIS. At the same time, it adds only minimal capacitance to the Circuit. ·60V Figure 1. Circuit Diagram of Video Amplifier 185 Figure 2A. Rise Time at 10 V pop Figure 2B. Fall Time at 10 V pop Figure 2C. Rise Time at 40 V pop Figure 20. Fall Time at 40 V pop Figure 2E. 10 nsec Pixels 10 V pop Figure 2F. 10 nsec Pixels 40 V pop 186 The common base stage has near unily current gam and acts as an Impedance translormer, pro vldlng a current snurce at Its collector This cur rent charges the combmed collector capaCilances 01 D2, and the emlttel lollowers, OJ and 04, which add up to about 5 pf at the opera ling pOint. To this total one must add about one pf 01 stray capacitance A load or "pull up" resistor 01 430 ohms IS used at the collector 01 the common base transistor, OJ The rrse time at this pornt may be calculated to be tr " 35· 2 • P, • 430 • 6 pf 5 7 nS This value IS Improved by the addillon 01 a peaking COil 01 22jJH Theoretically, the rrse lime could be reduced by up to 40°'0 IWlthout overshoot I by optimizing the Inductance Due III the nonlinear nature 01 the capacitances 10 be compensated lor here, dlHerent ellects result lor flse and lall times ThiS situation requrres a com promise resulting III a practical Improvement 01 less than the theoretical transit Inn time Never theless, 3 ns tranSillon times are obtained at the collector 01 Il~ by means 01 the emlller peaking discussed earlier The lT1817 IS packaged In a common base con figuration ThiS means that the transistor base IS connected to two symmetllcal low Inductance base leads As IS well known, base lead Induc tance may cause Instabllilles In common base configurations To prevent thiS Irorn happening, base damping reSistors, Rand Ra, have been added The value 01 these resistors depends on the deVice bias pornt and the crrcult layout II oscilialions occur, they would be near a Glga hertz or higher and therelore may nOl be seen on anything but a sampling OSCilloscope They Will aHect flse times and output sWing capablll ty Instabilities may be eaSily detected WITh a spectrum analyzer connected to the Input lack 01 the Video amplifier Enough Signal will feed back through the collector capacitance 01 O' to reach the analyzer 3. The emitter·followers, (b and 0" are a complementary parr of tranSistors, lT1829 and lT5839, In TO·39 packages The transistors are biased to the threshhold 01 conduction by two diodes, 0I and 02 These diodes should be relatively large, slow rectll,er types, each pro vld,ng no more than 0 5V 01 bias wilh a lor ward diode current of 70mA The diodes have low, largely capaCItive Impedances at high Ire quencles, and should be connected with short leads between the bases 01 III and 04 The emiller followers prOVide temporary charging currents to the output CirCUit whenever the voltage across the load IS changed. In case of a display With high contrast and many tranSitions, the current In Q3 and 04 may become ap preclable, causing the transistors to heat up The elevated lunctlon temperature shilts the bias pOint Irom Class "B" In the drrectlon 01 "AB" II the emitters 01 these transistors were can nected drreClly. a DC component 01 current would lIow Irom the 50 V supply through the deVices III ground ThiS "pole current" would lur ther heat up the lunctlons and might lead 10 thermal lunaway In the WCUIt descrrbed, thiS Situation IS prevented Irom occurrrng through the use 01 the emitter stab,IrZlng reSistors Rill and RII USing CapacllOr, C4, prevents detefloratlon 01 the dynamiC operation 01 the weult A Simpler, more pflmltlve way to aVOid thermal problems. IS to use IlIlly one bias diode, or none at all DOing [hiS, however, has serra us eHects on the gray scale I,nearrty at mid range 4. The output circuit The lT1839 and lT5839 translslOrs have excellent peak current handlrng capabllrtles The" emitter currents react vrrtually Instantaneously 10 the base voltage Even when supplYing several hundred mlill amperes 01 peak charging current, the base to emitter gam holds up well It IS therelore pOSSible to drrve more elaborate load configura tlons than a bare capacrtance ThiS abllily may ease Interconnect problems The errcult described In figure i IS powertul enough to accommodate a piece 01 shielded cable between the CRT and the Video amplrller A tWin-lead line or a Single wrre connection may also be used Instead of the shielded cable The crrCUII IS nOl only able to drrve elaborate Interconnect networks, but also 10 handle substantially larger CRT capacitances Without slgnll,cant penalties In flse and fall trmes for Instance, thiS errcult IS capable of dflv 109 15 pf wrth 3 8 ns tranSition times In all cases, the presence 01 additional reactive crrCUI! elemems causes the output CIrCUit to have resonances which Will cause onglng or over shoots, rI the output errcult IS not properly damped To thiS end, a varrable reSistor, R12, IS Included In the CIrCUit When adlusted for crrtlcal damping, the wavelorm Will look smooth across the load capacilance In the demonstralion CliCUil, Iflg. 11, a 65 pf chip capacitor Simulates the CRT cathode capacrtance It IS connected across a speCial lack, which has been deSigned for the TektroOlx fET probe, Type 6201 Probe, lack and chip have a combined capacitance of 8pf The fET probe may be used In conJunclion wilh Tektronix sampling scopes or reaHlme scopes with band· Widths of 300 MHz or more. 187 One may be tempted to use slower Instruments, such as a 200 MHz type, and correct mathe· malically for the addlliOnal transition lime can tobuted by the scope We do not recommend thiS approach since slower scopes appear 10 produce wave shape distortions which lead to mISleading ose time values IV. AMPLIFIER PERFORMANCE figure 2 contatOs photographs showtOg ose and fall times at 10 V and 40 V peak to-peak sWing. Also shown are some response curves generated by the well known CIrCUit analYSIS program SPICE Careful modelling 01 the semiconductors used, according to the theory 01 Gummel and Poon, resulted In good agreement between computer and laboratory generated pertormance data. In addition, computer analYSIS olfers InSights, which cannot be obtained by practical measurements Shown III figure 3 are the superrmposed plots of the Input voltage at the base 01 01 and the output voltage across the CRT capacitance The second set 01 plots, figure 4, displays the collector current wave lorm 01 0 I and the combined emitter CliCUltS of the complementary set of emlller followers The collector current 01 01 shows clearly the effect 01 "peaking," rntroduced by the emitter CIrculi components, R6, C2 and CJ Note that under lull sWing condilions (40 V pp output I, the wavelorms are not qUile symmetflcal The effect on the tranSition times 01 the output voltage, however, IS mlOimal The example shown In both figures 3 and 4 cor responds to a pIXel time 01 IOns, which IS the practical mlOimum lor a system With 3 ns tranSillons. When operating conlinuously at thiS rate, approxImately 25mA 01 average current flows In each one 01 the emlller lollowers ThiS causes a Significant flse In case temperature for these deVices. It IS therefore recommended that clip-on heat radiators be used There IS no electocal penalty lor thiS measure, since the collectors are on ground potential Heatslnklng becomes absolutely mandatory If one explores the limits 01 the amplifier by operating at 100 MHz and beyond V. CONCLUSION An amplifier was developed which meets all needs of a high-resolution CRT monitor, While practical can· siderations played an Imponant pan In the CliCUil realizalion, the pflmary purpose was to demonstrate transistor capability It IS hoped that enough background Information was given to allow the reader 10 tailor hiS ClrCUil to hiS speCifiC needs. SPOOLED: 84·07·24.16:22 STARTED: 84·07·24.16:22. ON: AMIC BY: PSI LEGEND: 0: V 11001 LEGEND ':1I130Dl '.1111101) +:11'13, TIME VnOD) °1-------- 0.0000·01 1.5000+01 3.0000+01 +J-------- -1.5000.00 -7.5000·01 0.0000·01 TIME 4.5000+01 7500001 .- "(JODI 2.000001 1 0000·01 0.000001 1.0000·01 2.000001 ·/··_·---·0.0000·01 3.750102 1500002 1.125001 1.!iooO·Ol 6.0000-01 1.5000-00 , ... 1_ ,, ,• I I , , '-"r~~~: VOhage'ACrOSSICAT Calhode Capacitance .......... :1 .'lnpuIVoItage(Ql Basel ;1 .! ·1 .'.i '--- ,, "'r1', 15 15 ' , \ , ~ +-----i~40V--.;.....- 20 Emiller Curren! of PNPFoilower 20 Figure 3. Computer Generated Voltage Plots Figure 4. Computer Generated Current Waveforms 188 AN1021 A Hybrid Video Amplifier For High Resolution CRT Applications Motorola RF Devices has used their unique high frequency RF semiconductor capabilities and thin film hybrid expertise to produce a hybrid video amplifier with less than 2.9 ns rise and fall time for a 40 V output swing. This video amplifier provides a low power dissipation solution to a problem that has been limiting the performance of ultra high resolution CRT monitors: video amplifier speed. Many of the 1024 x 1024 and 1280 x 1024 pixel. 64 kHz horizontal sweep rate CRTs that are used in CAD/CAM and high resolution graphics applications have not realized their potential performance because of the speed of their video amplifiers. Video amplifiers with 3.5-4 ns rise and fall times ohen found in these high resolution CRTs do not provide optimum picture quality when the CRT has approximately 10 ns to energize each pixel. A slow video amp will produce dimmer vertical lines than horizontal lines or may force monitor designers to other compromises such as a slower sweep rate which may produce flicker, or lower cathode voltage which will produce a dimmer picture. The hybrid described here solves these problems. SUMMARY The Video Amplifiers, CR2424 and CR2425, are hybrid integrated circuits designed for high resolution CRT Video Amplifier applica· tions. They are capable of delivering 40 volts peak·to·peak output with overshoot typically less than 5% into an 8.5pf load. Typical 10·90% transition times are 2.6 nsec with a bandwidth of better than 130MHz. They have excellent gray·scale linearity, are dc coupled and do not reo quire an external load·resistor. CONSTRUCTION A_ Mechanical The amplifier is housed in a proven package, which consists of a plastic housing, attached to an aluminum heatsink. Dimensions and pin can· figurations are shown on the attached specifi· cation sheets. The circuit uses special silicon transistors mounted on heat spreaders on an alumina substrate with thin· film resistors and gold metalization The substrate is soldered to the heatsink. The heatsink is supplied in two versions, CA Low Profile which is designated CR2424, and a taller heatsmk version, CR2425. These two package styles are shown in Figure 1. The electrical characteristics of these two amplifiers are iden· tical. The heatsink style choice should be based on ease of mechanical Ielectrical interface. In both cases, the heatsink is at ground potential and should be attached directly to the chassis or ex· ternal heatsink for mechanical stability and heat conduction to ambient. This CR2424 hybrid driver can also be supplied in a hermetically sealed package. The hermetic version is designated CR2424H and can be screened to Mil Std 883 method 5008. B_ Electrical The Circuit uses bipolar silicon transistors in a two·stage feed·back amplifier configuration. The output is supplied by emitter· followers. Because of the complementary circuitry employed, there is no need for a load (or pull·upl resistor. CA low Profile The power consumption is typically 3.0 watts for average picture content and a maximum of 6.0W for 10ns continuous black to white transitions or worst case situations. The electrical pin connec· tions are shown in Figure 2. C_ Thermal Thermal analysis of an amplifier design is a very essential issue to ensure amplifier reliability. Heat is one of the most critical factors that deter· mines how long the amplifier operates. The ability to examine the CRT circuit thermally under operating conditions is absolutely necessary. The infrared microscanner was used for evaluation of the CRT hybrid amplifier from the standpoint of thermal resistance and operating temperature. With the heatsink temperature stabilized at 60°C, the maximum transistor junction temperature was measured at 108°C. This is a very safe value, especially for devices with all gold metalization as used here. The maximum temperature occurs when the output voltage is either at its lower or upper extreme. Under this condition the maximum power dissipation on the die will be approximately 1.6W. Thus, the thermal resistance can be calculated to be 30°C/W. Under normal operating conditions (normal operating conditions means an average picture contentl the hottest transistor will dissipate ap proximately 1W. Again, with the heatsink temperature stabilized at 60°C, the transistor Junction temperature will be 60 ° C + 30 ° C/W x 1W ~ 90°C. This is a very safe value for this kind of amplifier for a long life time. OUTPUT INPUT +Vcc CR2424 (CASE 714G-01, STYLE 11 Figure 2. Pin Configuration PIN CR2424 Figure 1. Package Types 189 APPLICATIONS A. Output Characteristics The hybrid is intended to be used as the final stage of very fast video circuits. Properly driven. it can produce continuously alternating 10 nsec pixels with 40 volts swing and excellent bright· ness. The nominal load·capacitance is 8.5pf. Other values may be accommodated. since the output voltage is supplied by a pair of emitter followers. and is fairly insensitive to changes in load capacitance. Often a wire connection of some length between the output of the module and the CRT cathode cannot be avoided. In this case a resonant circuit is formed. which may cause objectionable ringing or overshoot at its resonant frequency. To avoid this condition a damping resistor must be used in series with the lead inductance. For critical damping the value of this resistor becomes R· 2' if (11 A resistor is often desired at this position also for protection against arcing. In practice. the op· timum value of resistance may be determined ex· perimentally during the bread·boarding stage. Typical values are 50 to 100 ohms. The lead· inductance may be artificially increased by a few tenths of a microhenry to obtain a desired peak· ing effect. Any change in inductance will require readjustment of the damping resistance. as stated by Equation 111. A short piece of cable 175 or 93 ohm I or 300 ohm twin·lead. terminated by a capacitance. will act similar to an inductance in the frequency range involved. In this case a damping resistor must also be used. The output terminal of the hybrid is not short· circuit proof. Any resistance from this point to either ground or B+ should not be less than 600 ohms. B. Input and Transfer Characteristics The dc transfer characteristics of the module are shown in Figures 3. 4 and 5. It is seen from Figure 3 that. at dc. an input current swing of ± 6.25mA causes the output voltage to change by ± 20 volts. The next plot (see Figure 41 relates the input voltage. as measured at RF input port to the output voltage. The amplifier is phase·inverting. The ratio be· tween these voltages is approximately 13.5. From the above values. one may calculate a low frequency input impedance of '" 240 ohms at the RF input port. Figure 5 is a plot that relates the input voltage. as measured immediately at module terminal 1. to the output voltage. The ratio between these voltages is approximately 230. From the above values. one may calculate a low· frequency input impedance of '" 15 ohms at Pin 1. Pin 1 is an internal dc feedback node and thus. as we can see. has a low impedance looking in from the outside. Pin 1 must be fed from a series network made up of a resistor with a shunt capacitor for high frequency pre·emphasis. An appropriate input network is shown in Figure 7 and is included as part of the standard test fixturing. With the input terminal open. a dc level of approximately 1.4 volt exists at this point. Under this condition the module output voltage is approximately one·half of the supply voltage applied. biased at about 30mA. The collector lead must be by-passed for RF as close to the transistor as possible. For all common·collector (or common· basel circuits. a base resistor of "'20 ohms is recommended. It helps suppress spurious oscilla· tions. which may occur in the GHz range and are difficult to detect. Resistors Rl. R2 and R3. and capacitor C1 and coil Lt are adjustable for desired circuit gain and response. Typical values may be: Rl:::: 50Q R2 :::: 215Q Cl:::: 90pF R3:::: 50Q Lt:::: 50nH The pulse generator used should allow changing the dc level in order to set a quiescent bias point of about l.4V at the input of the module. GENERAL CONSIDERATIONS C. Frequency Response A. Test Circuit The test circuit used to evaluate the hybrid module is shown in Figure 7. The input is driven from a fast pulse generator. such as the Tektronix model PG502. It is important that the internal generator impedance is 50 ohms. It is also advisable to keep the cable length between the generator and the test circuit at a minimum; preferably only a barrel connector is used. Since the module is dc coupled. the input drive voltage must be adjusted such that the driving wave form is centered around 1.4 volts. If the pulse generator used should not allow the setting of the dc level. a biasing current. injected at module terminal 1. through a resistor of more than 1 kiloohm. may be applied in order to ad· just the desired quiescent point of the output voltage. The output is taken from terminal 9 with an ac· tive FET oscilloscope probe fitted with a 100:1 voltage divider. This probe adds 1.5pf to the load capacitance. bringing the total load capacitance to 8.5 pI. The input circuit contains a series resistor and capacitor in parallel. which is tuned for good response when driving with a 50 ohm pulse· generator. These components perform a RC "peaking" circuit. B. Practical Circuits The module is best driven from a low-impedance source. such as an emitter follower. The reader is invited to experiment with a circuit as shown in Figure 8. The driver transistor can be an LT2001. 190 In the literature and in many equipment specifica· tions frequency response and rise· times are often treated as having a fixed relationship. The equa· tion frequently quoted is t,[10-90%1 •. 35 f3dB 121 It can be shown that 121 indeed applies for the simple case of a single-pole R-C network. In reality. video amplifiers have much more complicated transfer functions. and the above equation holds true only in a very general way. In addition to the proper gain response. another' amplifier characteristic is of great importance. Since a symmetrical square wave consists of a fundamental frequency and odd harmonics thereof. the preservation of the phase·relationship between all frequency components. while passing through the amplifier. must be guaranteed. This requirement is tantamount to specifying a "linear· phase" response or. in other terms. a uniform delay. Amplifiers having constant group delay ex· hibit smooth. monotonically decreasing frequency· response curves. One must be wary of responses which show ripple or peaking at high frequencies. Although sometimes impressive in terms of band· width. such amplifiers often have poor transient response. Shown in Figure 6 is the sine-wave frequency response of the CR2424 in its test fixture with the input variables previously adjusted for best rise and fall times. The output voltage is 20V peak·to·peak. The sine·wave sig· nal generator has a 50 ohm internal impedance. The - 3dB point occurs at about 200MHz. For 40V output swings the - 3dB bandwidth is typically 145MHz. Actual, photographs of CR2424 output waveforms driving a 8.5 pf load are shown in Figure 9, 14 1.65 l 10 \ 1.6 "'- U c:i .= 1.7 CRT Hybrid Amplifier CR2424 12 2 0 -2 " ~ ~ U c:i ~ "- ~ -4 ............ ............... -8 -10 40 Vou, D.C. ............... " I 60 20 Vou, D.C. 0.0 0 Hy~rid AmPlifi.) CR2424 Vou, 20 Vp·p -r-. r- -I-...... -0.50 iii ~ 1 ~ t ~ r... .... 1--. ...... -1.50 ............ 1\ -2.00 1\ ~ Vou, D.C. 40 !\. -3.00 ......... \ -3.50 '" -4.00 60 o 20 40 60 80 100 120 140 Frequency IMHz} C2 C2 - 0.o1~1 Chip Cap OUTPUT 50Q R, R, - 0 - 500Q R, Typical - 215Q 160 180 Figure 6. Frequency Response of CR2424 Figure 4. Voltage Ratio at RF Input Port RF INPUT , -2.50 1 20 60 40 Figure 5. Voltage Ratio at Port 1 -1.0 0 ~ "\ 1.2 1 ......... .... 1.25 Figure 3. Output Voltage versus Input Current \ .............. 1.3 'r--.. CRT ............... 1.35 -6 20 1.45 ~ 1.4 ....... 1--. o 1.55 .5 !!. 1.5 CL - 7.0 pI • r1.5 pI Probe Cap. C, - 10-150pl C, TVPical = 90pl Vee - 60V Nominal Figure 8. Experimental Circuit Figure 7. Test Circuit 191 \ 200 192 AN1022 Mechanical and Thermal Considerations in Using RF Linear Hybrid Amplifiers Prepared by Don Feeney Motorola RF Devices One additional note of caution. DO NOT attempt to lap or file the heatsink of the hybrid amplifier. Not only does this void the warranty (considered "mishandling" by the manufacturer), but you can induce substrate cracking during the machining operation. If you need a shorter heatsink, consider the hermetic package option or the low profile package available on some models. Motorola RF linear hybrid amplifiers are shipped with a mounting surface flatness of :': .002". To improve heatsinking, thermal grease can be used. ABSTRACT Motorola's thin film hybrid amplifiers are medium power (0.2 W to 2.0 W power output) broadband devices (1 to 1000 MHz) that are biased in a class A mode for linear operation. To insure a proper electrical/mechanical interface with adequate RF/thermal characteristics, certain guidelines are presented for the design engineer to obtain maximum electrical performance and the longest operating life. THERMAL CONSIDERATIONS PRINTED CIRCUIT BOARD INTERFACE A question that often arises from engineers using our hybrid amplifiers is "What is the thermal impedance?" Thermal impedance (expressed as 0JC) is a very real and important parameter for the RF design engineer using discrete solid state devices. However, this term loses its meaning in a multistage hybrid amplifier. Each stage may be biased at different quiescent conditions resulting in different junction temperatures under a given set of environmental conditions. Additionally, hybrid circuit design engineers may speak of BJC referring to the thermal impedance of a single transistor die mounted on a hybrid circuit using their particular assembly processes. However, this term has no meaning to the customer using their product who can only compute the power consumption of the total amplifier. To avoid this confusion, Motorola RF Devices simply rates the maximum operating case temperature for their RF linear hybrid amplifiers. These amplifiers are designed so that under the worst case operating conditions, the maximum junction temperature of any of the transistor die will be below 150°C. This junction temperature correlates with our two years of accumulated reliability data which predicts an MTBF in excess of 142 years. All Motorola RF linear hybrid amplifiers are internally matched to a nominal characteristic impedance of 50 or 75 ohms, both at the input and the output. This not only reduces the external components normally required to match to these impedances in discrete designs, but it also simplifies the requirements for interfacing printed circuit board connections - for short path lengths, strip line width has little effect on RF performance. Motorola RF linear hybrid amplifiers feature .020" diameter gold plated pins' spaced at .100" centers. Nominal pin length is .460" (.375" for hermetic package).2 There is provision for a total of nine pins, but unused pins will be missing (refer to pin configuration diagram for the particular hybrid amplifier). Viewing the hybrid from the top, pin 1 is identified on the left. This is the RF input, usually transformer coupled. 3 The two adjacent pins are ground connections. The middle three pins are reserved for power supply connections. Positive polarity units have the power supply in pin located in the middle' Units designed to operate from a negative supply have the power supply connection offset one pin to the left to guard against inadvertent installation in an improper test fixture. The extreme right hand pin is the RF output, and the two adjacent pins are ground connections. All ground connections are internally connected to the flange, except as noted on the functional schematic (refer to particular data sheets). HEATSINK YOUR HYBRID Like all RF power devices, hybrid amplifiers require heatsinking for proper operation. How much heatsinking is necessary? As much as is required to maintain the case operating temperature at the maximum value under worst case ambient temperature and maximum supply voltage. The presence or absence of the RF signal is insignificant due to the class A bias conditions. Reducing the supply voltage will decrease the power consumption, but it will also decrease the linearity. Attach the hybrid amplifier directly to the chassis, to a module card sidewall, to a small baseplate, or to a mounting bracket that is connected to one of the above. But before you complete your design, verify that the maximum case (flange) temperature for the hybrid amplifier is within the manufacturer's specified limits under your worst case operating conditions. EXTERNAL COMPONENTS Although it is not specified as a requirement on the data sheets, it is usually good RF practice to add a low impedance RF bypass capacitor (e.g., 0.1 /LF chip capacitor) located near the power supply pin. Additional decoupling is normally not required. However, some Motorola RF linear hybrids require external chokes and capacitors for proper operation. 5 Chip capacitors are recommended. A broadband 30 /LH RF choke may be constructed by winding 30 turns of #36AWG magnet wire on a Ferroxcube 891 T050/4C4 core (alternate core is Indiana General PIN CF 12001). With an accompanying order of hybrid amplifiers, this choke may be procured through Motorola. 193 For Motorola hybrid amplifier model CA2820. the external chokes isolate the transistor from the power supply. Positioning of these chokes will have an effect on the high frequency end of the amplitude response. provisions for adapting this same test fixture for the low profile package. the bent pin option. and the hermetic package option are presented in Figures 8.9. and 10. Pin diameter for hermetic package is .018". These pins will mate with sockets manufactured by Amphenol (PIN 502-20071-572) and Barnes (PIN 027-01802). 3 Except for CA2820. which has an internal DC blocking capacitor at the input. 4 Except for CA2820 and CA2870. Refer to individual data sheets. 5 e.g. CA2820. CA2870 1 TEST FIXTURES 2 Figures 1 through 10 detail the assembly of standard test fix1ures for Motorola's line of RF linear hybrid amplifiers. Much of this mechanical information will prove useful to the engineer who is designing one of these units into his equipment. The details of the test fixture assembly for the CA2820 presented in Figure 7 apply to most of the standard RF linear hybrid amplifiers (just substitute PC boards. adjust pin spacing. and remove external components as required). Special 1.000.791 ..J..... I 033 DIA. 4 PLACES ,. STRIPLINE WIDTH .055 .116 DIA. 4 PLACES r---------"''''''..-----,1.000 .033 DIA .. _ ~ I + _ _ _ _ _ _ y~ACES(l:) " 791 .l~ _ _ _ 1. .640 -r--t---t___ STRIPLINE I-I'<-r-+--"""'; .400 WIDTH .120 116 DIA .. 4 PLACES 202.135 .015 L--.,.,+--'-.Lf-U+-+llj-I-4JJ..i-"t--t"-t'.r>"<:-'--+"'-~6 .000 ~ ~ M;o ~~~~~~~~~:!~~ .,...:.,...:.,...:.,...: . . '~SN ~ "' ... 0 0 NOTES: 1. All dimenSions In Inches. tolerance:!: .005. 2. Material IS double sided glass epoxy (Gl0). 1116" thickness. 1 oz. cooper, solder plated 3. TF.()6 used forCA2820 only. All other models use TF·03 Figure 1. PC Board Construction for Hybrid Amplifier Test Fixtures 194 DRILL '13 TAP THRU 6-32-UNC 2 PLACES ' " 1.500 '''-T31~2--"-+----I\l-~-- ---ct>-.656 -'-----L--+-__ - I --(9- - - .250 I ____ $ _____ $_ .313 '" I I ~~-----$-----$­ .250 .072 R. TVP. I -ER,- 1.500 i .250 DIA. C' BORE , !~ DRILL AND TAP 4 40, 4 PLACES .. ------,, NOTES: 1 All dimenSions In Inches, tolerance,,: 005 2 Malenalls 318 aluminum ! ; 1"".350-1 Figure 2. Heatsink Base Plate Construction for Hybrid Amplifier Test Fixture .150 ,~.115 r--515--1 .157---1 NOTES: , All dimenSions In Inches, tolerances:!: .005 2 Material IS aluminum r-.r"'--.+,,~ .156" DIA. TWO HOLES' Figure 3. Adapter for Hermetic Package to Standard Hybrid Amplifier Test Fixtures EI ~ I ------1.500----- 1---------1.75------- Figure 4, Adapter for Low Profile Package to Standard Hybrid Amplifier Test Fixtures ---..; i-- MILL SLOT .10 ..L 300 t III ----1.500----~-+t~6 , .065" (BELOW PIN) i;=r ~ I .156" DIA. TWO HOLES- :1-- -T i I - 1 1.75---------< IIII I! I AMPHENOL PIN US-625/U (50Q) TROPOMETER PIN UBJ·20(75Q) Figure S. Spacer for Bent Pin Package Option to Standard Hybrid Amplifier Test Fixtures Figure 6. Modifications to BNC Connector 195 EIGHT PIN SOCKETS AMPHENOl PIN 502·20071-512 BARNES PIN 027·018·02 SPACER (FIGURE 4) PIN SOCKETS SPACED AS REOUIRED AMPHENOl. PIN 502·20071·512 BARNES PtN 027'()18{)2 PRINTED CIRCUIT BOARD (FIGURE 1) o PAINTED CIRCUIT BOMD 1 ~ ~ ~ ~ ~ ~ ~ ~;~f8D ~O~D~::~N ~KETS (FtGURE I) FOUR SCREWS .. 40 THREAD 518 LENGTH dtJ FOUR SCREWS, 4·40 THREAD. Sl8" LENGTH TO PC BOARD SO THAT SOLOfR PIN SOCKETS TO PC IJ()ARD so THAT h SLOTTED SNe CONNECTORS (FIGURE 61 FOUR SPACERS. 00 LENGTH = 250 = 250 10 '" 116 = 180" t 005 TWO SLOTTED BN(; CONNECTORS (FIGURE 6) ~__'u'_ _ _ _ _ _ _ _-,I-,-[_~_-, ALUMI~y~U:S~ PLATE RF CHOKES TRW PIN 11 F 11294 II II FOUII SPACERS. 00 • LENGTH ,. 250" 250. 10 _ 116 TWO 0 luF CHIP CAPACITOAS usee PIN WOSOFH104AZ (or equlvalen1) ,---------------, ~~O~~~;~:~~'i~R8Qu'Va,en'l 0 I o MOUNTING HOLES FOR HYBRID AMPLIFIER 0 ~~~ SECURE WITH 6·32 ". o MOUNTING HOLES FOR HYBRID AMF'lIFIE.R SECURE WITH 1/0" 6·32 SCREWS SCREW NOTE: POSITION RF CHOKES AS REQUIRED FOR BEST HIGH FREQUENCY RESPONSE Figure 7. CA2820 Test Fixture Assembly (Case 714F-01) Figure 8. Text Fixture Assembly for Hybrid Amplifiers in Low Profile Package (Case 714G-01) TWO SCREWS 6 j2 THREAD ", LENGTH SPACER (FIGURE 5\ PIN SOCKETS SPACED AS REOIJIRE.D 4,,",P,...E. .... 0~ P.." =: ~ BARNES PIN 027'0'602 ~ T T []3 [] !i 000 0 000 W [] Ii ADAPTER (FIGURE 3) PIN SOCKETS AS REOUIRED AMPHENOL PIN 502·20071·572 BARNES PIN 027·016·02 PRINTED CIRCUIT BOARD (FIGURE 1) PRINTEC CIRCuiT BOARD IFIGURE' FOUR SCREWS ... •..0 THREAD. 518 LENGTH FOUR SCREWS 4 4C THREAD ", LENGTH SOLDER PIN SOCKETS TO PC BOARO SO THAT h.. 180":t: 005 TWO SLOnED eNC CONNECTORS IFIGURE 61 ii FOUR SPACERS 00 = 250 10 '" "6 LENGTH:::: 335 ALUMINUM BASE PLATE (FIGURE 21 II TWO SLOTTED BNG CONNECTORS (fiGURE 6) FOUR SPACERS. 00 ~ 250" 10 "" 116 LENGTH ,. 250" ALUMINUM BASE PLATE (fiGURE 2) SECURE ADAPTER WITH TWO HEX SCREWS. 6-32 THREAD. 5/8" LENGTH MOUNTING HOLES FOR HYBRID AMPLIFIER SECURE WITH 6·32 THREAD. 'A" L.ENGTH SOLDER PIN SOCKETS TO PC BOARO SO THAT d:::: '65 :t 005 (JD Figure 9. Text Fixture Assembly for Hybrid Amplifiers with Bent Pin Option (Case 714J-01) Figure 10. Test Fixture Assembly for Hybrid Amplifiers in Hermetic Package (Case 826-01) 196 AN1025 Reliability Considerations in Design and Use of RF Integrated Circuits Prepared by James Humphrey and George Luettgenau ABSTRACT DEFINITIONS Reliability is a major factor in the profitability of CATV Systems. R = Reliability Reliability is related to the probability that an item will perform a defined task satisfactorily for a specified length of time, when used for the purpose intended, and under conditions for which it was designed to operate. In spite of its proportionally low cost, the RF integrated circuit figures prominently in the overall reliability picture. This complex and important function is located at strategic points in the system. Failure Failure is a detected cessation of ability to perform a specified function within previously established limits in the area of interest. Fortunately, modern design and manufacturing technology, which draws extensively from resources generated by military and space activities, assures a degree of reliability which is compatible with the most stringent requirements. (a) (b) (c) (d) . Transistor chips are the most vital elements of the RF integrated circuit. Low noise and distortion require state-of-the-art transistor structures. Gold metallization, thermal equilibrium by means of diffused balancing resistors, as well as automated process control have resulted in transistor lifetimes of over 100 years. Dead on arrival Infant mortalities lifetime failure rates (random) End of life (wearout) MTBF (Mean Time Between Failures) The total measured operating time of a population of equipment, divided by the total number of failures within the population during the measured period of time. One of the inherent reliability advantages of IC's is the reduced number of interconnects. The full benefit of this characteristic is achieved through the use of gold conduction paths in conjunction with gold wire bonding. Perhaps the single most dangerous enemy of high reliability is excessive heat. Careful, computer-aided circuit design coupled with thermally sound, stress-free mechanical construction guarantee structural integrity and safe operating temperatures under all practical conditions. Infrared scanning helps verify the achievement of design goals. Average Llle The mean value for a normal distribution of lives, and generally, it applies to failures resulting from wearout. BASIC RELIABILITY EQUATION R = e-tlm = e-At Abuse or abnormal stresses may counteract the best of reliability. In order to avoid problems, the user must control the electrical, thermal, and mechanical environment surrounding the RF IC. Much progress in this respect has been made by the equipment industry. Where: R = Reliability or probability of success , = Mission time in hours . hours MTBF In hours = failures 1 A = Failure rate = MTBF INTRODUCTION Reliability considerations are becoming increasingly important in the operation of CATV Systems, requiring an absorption of military and aerospace reliability technology into the CATV business. Market surveys show a large number of MSO's and consultants consider reliability as a major item in equipment selection. failures hours SYSTEM RELIABILITY 1. When components are in series, failure of anyone of the components will result in failure of the system. A definition of major reliability terms is important along with an introduction to microcircuit reliability tools (both hardware and software). An overview discussion of PhYSics of Construction involved with the die and interconnects must be presented. Then: 197 RsYSlfM R, xR, xRJ x---R, An-STf.M A, +A, +AJ +---A .• 2. When the same components are in parallel (redundancy) neglecting, for simplicity, the decision-making device, the switchover function and the fail safe requirements: RsYSTEM RELIABILITY CURVE The following curve represents the typical condition of operational reliability. R, +R,-(R,R,) Infant Mortality Plus T;:'·"·· A= I Failure Rate I I ~ -~E-a-rly-"·*I _____ .J',__ " I Period -tl-..-.------ -~ ........' - - - - - - - - - - - - - - -........ Optimum Shipping Point RELIABILITY PREDICTION ALGORITHM n,. TlQ n, nM + + Point of Average Life As + A,A., + lA'TN'T (Substrate contribution) lAocNoc (Attached components contributions) APFnp, (Package contributions) Where: Ab (nT X Ttl: X TtQ X rtF X TtM) nT ~ BASE FAILURE RATE MODEL A, A, PART FAILURE RATE MODEL Ap A, I I ,...-----~Iw e a r : t - - : \ - - The military has put considerable money and time into the study of reliability. One very useful military document is Military Handbook 217B, Reliability Prediction of Electronic Equipment. This handbook shows how to develop failure rate predictions by the use of mathematical models based on years of data collection by military agencies. A discussion of the interaction of components in the model is very useful in gaining an understanding of the overall subject. Where: A, Wearout Plus Random Failures I I -_-J Specified Failure Rate I I --l Ap = .: I I :/ Failure ~",om"'"_'"" Part failures in failures per 10' hrs. Base failure rate Temperature adjustment factor Environmental adjustment factor Adjustment factor based on quality Adjustment factor for circuit function 0.8 for digital hybrids 1.0 for linear hybrids 1.1 for combination hybrids Adjustment factor for maturity of product Base failure rate in failures/ 10' hr. Failure rate due to the substrate and film processing Failure rate contributions due to network complexity and substrate area which includes: (a) Number of lead terminations (b) Number of film resistors (c) Number of discrete chip devices (d) Type of film (thin versus thick) The sum of the failure rates for each resistor as a function of the required resistance tolerance The sum of the attached device failure rates for semiconductors and capacitors The hybrid package failure adjusted to include material and style 198 Diffused Ballasting System (Only one emitter contact shown) PHYSICS OF CONSTRUCTION Following the enumeration and identification of symbols used in reliability algorithms, a discussion of the major microelectronic components with respect to their reliability contributions is in order: TRANSISTORS The transistor die is the heart of the hybrid amplifier. With four to eight devices per circuit, the transistor determines performance and is most critical to proper circuit op"ration. During the last few years users have witnessed major advances in the performance of linear broadband transistors. Often, efforts to improve one characteristic have adverse effects on other desirable features. For instance, distortion may be bettered by thinning the epitaxial collector region. This, however, leads to sensitivity to voltage transients and other abnormal operating conditions. Therefore, devices with outstanding performance in one area are prone to weakness in others. Computeraided device design coupled with' volume production and tight process controls have resulted in transistors in which all essential features are in proper balance. Metal Film Ballast Resistor High fT is generally recognized as an important factor in achieving wide bandwidth and uniform distortion characteristics. Gigahertz transistors, which are now being used, have very delicate patterns, involving micron and submicron tolerances. They also occupy sizable areas on the silicon wafer, since watt-sized powers have to be handled. It is only realistic to expect that all parts of the overall transistor structure are not perfectly alike, but rather resemble the parallel configuration of many, slightly differing, small devices, as shown in the figure. Ballast Resistors METAL MIGRATION Some time ago a serious failure mechanism, associated with GHz transistors, was discovered. The metallization stripes of such devices, as mentioned earlier, are only a few microns wide. The metal thickness is, because of fabrication limitations, of similar dimensions. Consequently. the current denSity in these stripes is quite high. often reading hundreds of thousands of amperes per cm' of cross·section. Under these circumstances. metal migration may occur. With such large numbers of elec· trons flowing in such crowded space. the probability of collisions with thermally activated metal ions is great. The ions are propelled in the direction of electron current flow causing, in the long run, the metal to move, forming hillocks, whiskers and voids. The lifetime of a transistor is a function of three things: the current density, the temperature, and the type and consistency of metal· lization. It is also apparent that the entire transistor geometry cannot be tightly thermally coupled within itself, therefore giving rise to the possibility of small sub-areas of the transistor assuming different values of temperature than others. This possible problem can be effectively combatted by adding emitter balancing resistors to the device. Ideally each emitter-site or finger should have its own resistor. This goal is easily realized in interdigitated structures. Film or diffused monolithic resistors may be used. From a process and reliability point of view, diffused resistors are preferred because they avoid the silicon-oxide barrier which has a very high thermal resistance. 199 Not much leeway exists in reducing the current density (unless Ir is sacrificed). Changing from aluminum to gold extends the life at least by an order of magnitude. At high temperatures the difference is even more pronounced. At 1 50"C, the time to metal failure for gold metallization microwave transistors is in excess of 1 0' hours = 114 years. While this number is quite comforting, one is not at liberty to treat the subject of transistor chip heatsinking too lightly. A proven method for removing heat while at the same time obtaining a solid mechanical mount, has been to employ a heatspreader between the silicon chip and the IC substrate. Automatic mounting stations are used to eutectic collet mount the chip to indexed leadframes. Tight control of pressure and scrub sequence result in defect free attachment. Although one may employ other methods of heatsinking, e.g. beryllium oxide substrates lor part of the circuit, the added mechanical complexity and the reduced freedom of optimal circuit layout presently outweight the minor advantages resulting from a reduction in transistor temperature. Comparing hybrid versus discrete techniques, one can show the following: 1. For each transistor used, a minimum of three interconnects corresponding to the solder joints at the PC board are eliminated. 2. For each capaCitor used, a minimum of two interconnects are eliminated. 3. For each film resistor used, a minimum of four interconnects are eliminated corresponding to the connection to the resistor body and the connection to the PC board. 4. Transformer interconnects will be the same for hybrid or discrete. The increase in interconnects in building 33dB of gain in discrete form over the same circuit in hybrid form is: Add due to transistors Add due to chip capaCitors Add due to resistors Add due to transformers Less due to hybrid jumpers Less due to active pins 24 12 100 0 -4 -5 127 Additional interconnects per 33dB function INTERCONNECTS One of the most important parts of hybrid circuits is the interconnect system. The ability to reduce the number, control the quality, and test them by screening complete functions, is one of the major advantages of hybrid circuits over more conventional approaches. Constant improvement in the mechanical and metallurgical systems have drastically improved reliability. MIL Handbook 217B also discusses the reduction in reliability of printed circuit boards as a direct multiple of the holes required. Eighty-one additional holes are involved in making one discrete amplifier. Having the interconnects made early in the manufacturing sequence, before the subsequent series of tests and inspections, has beneficial influence on end equipment reliability. An analysis of the schematic on the standard 33dB Hybrid Amplifier will illustrate the point: 33dB Gain Block F, F, c. C, Q, - 'JJ 2 1 R, R" R_ R, R" R" 5 T R, R,. R" 5 T, ':' II R. .:. R, R, R" ':' R" C'T ':' R. R" R" .:. " R" R" ':' RB G.T ':' R" C, C, R" Fe 200 II[: The complete functional system including interconnects is tested, screened and a.c. sampled many times before it even meets up with the PC board in the manufacturers subsystem. Advantages of Gold Bonding Compatible with gold die and substrate Strength stable with time/temperature Malleable - not subject to cracking Easier to control process Interconnects Die Disadvantages of Gold Bonding Heatspreader More expensive More deformation at bond foot Hard to form loops / Solder Jumper Bond Die Bond \ CapacItor Solder /I / Histogram of Gold Versus Aluminum Bond Strengths Pin COMPONENT MOUNT The transistor heatspreaders, chip capacitors and pin connections are soldered to the metallization pattern on the substrate surface. This process is completed in a tightly controlled solder reflow furnace. Number of Pulis Due to the fact that the units are processed in an inert atmosphere and thoroughly cleaned and inspected early in the production process, workmanship problems are greatly reduced. BONDS Wire bonding was a major reliability issue for years. Aluminum has been one of the most widely used bonding systems in the hybrid industry for many years. The main reason for this is that ultrasonic aluminum systems bond at room temperature and, hence, do not interfere with other hybrid assembly processes. Strength (Gram) Gold thermal compression ball bonding has been a reliable standard process in the semiconductor industry for years. However, the requirement for 300"C bonding temperatures have kept this technique out of most hybrids. The recent changeover to all gold hybrids prompted the development of a compatible low temperature gold wire bonding system which by far out-performs aluminum. Strength Versus Time on Gold Versus Aluminum Wire T = 150'C Advantages of Aluminum Bonds Low temperature process Compatible with AI die metal Low cost High speed Easy to loop (stiff) Strength Disadvantages of Aluminum Bonds Degrades with time/temperature Kirkendall voiding Intermetallic formation with gold Brittle and subject to cracks Difficult to screen Difficult to control Aluminum Time 201 (c) Where there has been an extended interruption in production or a change in line personnel (radical expansion). RELIABILITY ADJUSTMENT FACTORS Following is a discussion of the "n adjustment factors" in MIL Handbook 217B. These relate to the external influences on hybrid circuit reliability. The factor of 10 can be expected to apply until conditions and controls have stabilized. This period can extend for as much as 6 months of continuous production. TEMPERATURE ADJUSTMENT FACTOR n, Operating temperature is one of the most important factors in reliability. As can be seen by the curve shown, great reliability improvements can be obtained by lowering the case temperature. This maturity factor is extremely important. The industry has used over 400,000 CATV modules since the first module was shipped in 1970. Since that lime we have constantly improved and refined the IC. Optimum reliability is an evolutionary process depending on time, volume, defect analysis and feedback to fine tune the product and eliminate defects. Failure Rate Multiplier Due to Temperature The question is where does CATV fit Into this table. Mechanical and thermal casting designs are extremely important in protecting the RF IC from the external environment conditions. Still, Wide variations in system placement introduce a swing factor for environmental effects, which will cause n, for CATV to fall between 1.0 and 5.0. The user must strive to keep the components as close to laboratory zero as possible. 2 4 6 8 10 20 30 QUALITY ADJUSTMENT FACTOR nQ n, This is the adjustment factor based on the quality grade of the product. This factor modifies the reliability levels by the different quality levels specified in MIL STD 883, Test Methods and Procedures for Microelectronics. These levels take into account different screening levels, qualification levels and quality conformance inspection requirements for the specified class. This curve shows that a hybrid circuit, operating at a case temperature of 100"C; has four times the failure rate as the same circuit run at 50"C. ENVIRONMENTAL ADJUSTMENT FACTOR n, This adjustment factor is based on the service environmental conditions that the part will be exposed to during operation. no MIL STD 883 Class A MIL STD 883 Class B Vendor Equivalent Class B MIL STD 883 Class C Commercial with Screening Commercial (No Screening) n, , Environmental Factor Based on Environmental Service Conditions Environment Ground, Benign Symbol 0.5 1.0 5.0 30.0 50.0 75.0 n, GH 0.2 0.2 Space Flight S,. Ground Fixed G,. 1.0 Airborne, Inhabited 4.0 Naval, Sheltered A N, Ground, Mobile G" 4.0 Naval, Unsheltered N" 5.0 Airborne, Uninhabited A, 6.0 Missile, Launch M, 10.0 A study of the MIL STD 883 Quality Requirements allow a very important discussion of cost versus reliability. As could be expected the test, manpower, eqUipment, time and paperwork go up rapidly as the MIL STD Grade is increased. A relative plot of this relationship is shown below: 4.0 Cost Versus Reliability Increasing MATURITY ADJUSTMENT FACTOR n" Costs The failure rate predicted by this mechanical model can be expected to increase by a factor of (n .. = 10) under anyone of the following conditions: (a) New device in initial production. (b) Where major changes in design or processes have occurred. 202 CONCLUSIONS Many of the MIL Standard Military requirements seem unimportant in influencing CATV reliability. However, the cost versus reliability curve is real and the equipment supplier can make choices as to the type of reliability he is willing to pay for. • Many reliability tools are available today both in equipments for evaluation of reliability and in analytical tools such as MIL Handbook 217B for predictions of reliability. EQUIPMENT • Hybrid circuits offer massive reliability leverage due to: (a) Reduction of Interconnects (b) Ability to control quality by screening (c) Large volume of complex standard functions are easier to control It takes a massive capital investment in order to meet the manufacturing requirements for the CATV industry. The volume, quality and performance standards required have caused us to constantly reinvest for the future. Many of the invested dollars are for equipments for which the return on investment is subjective. • Case temperature is very important for reliability SCANNING ELECTRON MICROSCOPE • A monometallic system, i.e., gold die metallization and gold wire bonding are optimum for reliability. This instrument allows very high magnification of surface conditions not available with optical methods. Magnifications up to 100,000 times are possible with the SEM. DISPERSIVE X -RAY ANALYSIS • Reliability can be improved by adding quality cost to the module process. This increased cost may easily be returned due to the lower failure rate. This capability, which is a feature of the SEM, allows us to make a microprobe to determine the chemical· composition of a sample. This is accomplished by detection of secondary emission x-rays which possess characteristic energies. The relative quantity and location of elements may then be displayed on the CRT. The authors wish to thank AI Bird, TRW Systems Group, Redondo Beach, California, for his technical guidance. ACKNOWLEDGEMENTS VARIABLE FREQUENCY VIBRATION This is a destructive test which is performed for the purpose of determining the effect on component parts of vibration in the specified frequency range. REFERENCES 1. MIL Handbook 217B, Reliabifity Prediction of Electronic Equipment. 2. MIL Standard 883, Test Methods and Procedures for Microelectronics. 3. MIL Handbook 175, Microelectronic Device Data Handbook. 4. M. Flahie, "Reliability and MTF - The Long and Short of It," Microwaves, July 1972. 5. R. Y. Scapple and F.Z. Keister, "A Simplified Approach to Hybrid Thermal Design," Solid State Technology, October 1973. 6. J. R. Black, "Electromigration Failure Modes in Aluminum Metallization for Semiconductor Devices," Proceedings of the IEEE, Volume 57, Number 9, September 1 969. 7. C.M. Ryerson, S.L. Webster, F.G. Albright, "RADC Reliability Notebook Volume II," RADC-TR-67-108, September 1967. 8. George G. Luettgenau, "Microwave Power Transistors," International Microwave Conference, Stockholm, 1972. X-RAY This is a very valuable tool for detecting voids in solder or eutectic bonds. INFRARED MICROSCOPY The ability to examine a circuit thermally under operating conditions is absolutely necessary when designing a new product or testing a new process. The infrared microscanner is used for evaluation of new products from the standpoint of thermal resistance and operating temperature. Resolution of 0.0005 inch can be achieved. 203 204 AN1027 Reliability/Performance Aspects of CATV Amplifier Design Prepared by Michael D. McCombs ABSTRACT The reliability advantages to be offered by the RF hybrid amplifier as used in CATV applications are discussed. The active part of the hybrid amplifier is the transistor. Metallization, ballasting and ruggedness are reliability related factors that must be considered by the device engineer when designing a high performance CATV transistor. Vertical and horizontal geometry and device 'distortion mechanisms are performance related factors that must also be taken into account. The Interrelation between these factors is examined. Life test data is then presented to illustrate the advantages to be gained by careful device design. The ultimate test is to see how long a part operates in the field without failing. The best way to simulate this is by means of a life test. Life test data is Included as a means of demonstrating the results of a careful design. II. WHAT IS RELIABILITY One definition could be that reliability is something that can cost you money if you don't have it. The dictionary defines reliability as "the quality describing that which is dependable or honest." To build honest transistors and amplifiers is a noble concept but one which may be difficult to measure. So in the everyday sense. reliability is a somewhat abstract idea that is difficult to describe quantitatively. In engineering, however. reliability has an exact meaning. . I. INTRODUCTION The cable television system operator buys eqUipment which he knows has demonstrated a certain minimum level of performance, or In other words, equipment that meets his specifications. If he questions this performance he can run variOus electrical tests to check it "Reliability IS the probability of a device performing its purpose adequately for the period of time intended under the operating conditions encountered. '" When an amplifier is designed for a certain level of gain, it may happen in practice that the gain is less than that called out in the specification. In certain cases this may be acceptable if the amplifier turns out to be very reliable. However, another amplifier, which supplies the full gain with ease, may breakdown in operation because its components are being taxed to their limits. This is where reliability enters the picture. It is possible to achieve full performance and still have state-of-the-art reliability.' We said that reliability is the capability of equipment not to break down in operation, The measure of an equipment's reliability, then, is the frequency at which failures occur in time. A failure is a malfunction which causes the component to violate the requirement for adequate performance, The frequency of such failures is called the failure rate, The reciprocal of the failure rate is called the mean time between failures or MTBF. Another question that we would like to be able to answer is, how long will his equipment operate before it fails. costing him downtime and repair. This is the question of reliability and to understand this it is necessary to understand the factors that go into designing tor reliability. The primary building block of a reliable CATV amplifier is the RF integrated circuit. This concept possesses many advantages over the PC board discrete design including a reduced number of interconnects and the ability of the manufacturer to effectively test the system before delivery to the equipment manufacturer. Going one step further, the basic constituent of the integrated circuit is the transistor itself. It is in the design of this transistor that the ideals of high performance with reliability can be effectively realized. .l. Failure Rate 1 MTBF .l. 205 Referring to Figure 1 , it is seen that there are three basic types of failures; early, chance and wearout failures.' III. HYBRID CIRCUIT RELIABILITY Early failures occur early in the life of a component and result usually from poor manufacturing. These can be eliminated by a 'burn-in' process. The hybrid circuit is the heart of the CATV amplifier. This assembly must perform its duty while experiencing a variety of electrical and environmental extremes. If the hybrid circuit should fail, then the cost to the system operator is high. For this reason the hybrid circuit should be an extremely reliable piece of equipment. ADVANTAGES Wearout failures are a symptom of component aging. These types of failures can be eliminated by either replacing at regular intervals or by designing for longer life than the intended life of the equipment if the components are inaccessible. There are certain qualities of a hybrid circuit which make it an inherently reliable assembly. Chance failures occur at random intervals and are due to sudden stress accumulations beyond the design strength of the component. Since the other failure types are relalively easy to eliminate, performance reliability should be determined by the chance failures. One subtle advantage relates to the wear out life of components. Replacement of a hybrid circuit means replacing every amplifier component which resets the clock on the entire amplifier as far as mean life is concerned. Replacing a component in a discrete amplifier does not. All of the other discrete components continue to approach their wear out life. For chance failures only, reliability may be expressed by the exponential relationship R(I) = The metallization system of the hybrid is another advantage. The gold metallization which is used for interconnects on the hybrid circuit allows the deSigner to have the high conductivity of gold for use in tying together the various components of the circuit, while having the additional reliability advantage of a monometallic gold system in wire bonding from the transistor to the hybrid. Even though the hybrid circuit utilizes heat sinking to reduce heat buildup, any bi-metallic interface will be susceptible to failure due to intermetallic formation. These gold-aluminum intermetallics are more brittle than the parent metals, and they also are susceptible to void formation due to the faster diffusion of aluminum into gold compared with gold into aluminum (Kirkendall Effect). If a hybrid circuit is manufactured using die with aluminum metallization, it is certainly preferable to use aluminum for bonding. This is because the gold-aluminum interface will then occur on the substrate, away from the heat of the transistor. This is important since the formation of intermetallics, Au AI, or Au, AI, , is accelerated by temperature. However, these interfaces, even though they occur on the substrate, are nonetheless sensitive to weakening. Which intermetallic compound is formed depends on the amount of gold available in the bonding area. If the gold is thin then Au,AI, will be formed. If the gold is thicker then Au,AI, will be formed. The end result is the same; voiding and a weak bond which eventually lifts. The entire process can be accelerated by thermal cycling whereby cracks are formed in the brittle intermetallics.' Data presented later illustrates the comparison between failure rates due to bond lifts in aluminum and gold systems. e-At where A is the failure rate and t is a given operating time; t must never exceed the 'useful life' of the device. The derivation of this reliability expression is found in the Appendix. System failures are caused by component failures. When components can fail only because of chance. the system will fail only because of chance. The design engineer is responsible for the reliability which is characteristic of his equipment. If he desires to reduce the number of chance failures which occur during the useful life period of his equipment. he must keep several key points in mindS Early Wearout Failures Failures Chance Failures Burn-In Period Useful Life Period TB m = mean wearout life Tw m Operating Life_ Figure 1. Component Failure Rate as a Function of Age Another advantage which hybrids enjoy over discrete designs is the reduction of the number of interconnects. 1. Design components to accept overstress; the normal operating point should be well below rated values, including temperature. 2. Provide good packaging with 'adequate heat sinking. 3. Design with as few components and interconnects as possible. An interconnect is a potential failure point. Reduction of the number of these pOints will result in a more reliable system. A calculation of the additional interconnects required in a typical discrete amplifier over the hybrid equivalent shows an increase of 127 interconnects in the discrete version.' Figure 2 summarizes hybrid life test data. 206 So it is apparent that the hybrid structure is inherently more reliable than a discrete assembly. But the heart of the amplifier, be it hybrid or discrete, is the transistor. which is not so heavily doped so that the resistivity of this layer is higher than that of the substrate. It is the configuration of this 'epitaxial layer' that is very important to the performance of the device. It is this layer that will form the collector of the transistor. There are two parameters of the epi layer that can be specified by the engineer. One is the thickness and the other is the resistivity. The resistivity is chosen from operating voltage considerations. The transistor is intended for a specific purpose and presumably the voltage at which it will be operating is known. If the device will be biased at 20 volts in an amplifier, then the collector breakdown voltage of the transistor, BVcBo, should be higher than 20 volts to provide a safety cushion. The phenomenon that occurs in a well·designed transistor at breakdown is called avalanche. This occurs when a sufficiently high reverse voltage is placed across a p-n junction. A field is formed across this junction and carriers are accelerated across the field. When the applied voltage equals the avalanche voltage a multiplication effect occurs in which atomic bonds are broken and the junction breaks down. This is the collector breakdown voltage and it is proportional inversely to the doping level of the collector or . epi layer. By specifying epi material, then, the designer sets his voltage operating limit. Reliability Data at 95°C Case Temperature • MTBFWlth 90% 7,398,000 3 141 Years CA2200 Hybrid 984,000 4 CA2600 Hybrid 577,000 4 PI" Description Transistor Chip Unit Hours MTBF-Galn Accumulated Fill Confidence . r----- Product - ~---- 13 Years 221dB - Yrs ..------_.8 Years 264dB - Yrs Figure 2, Hybrid Circuit Life Test Data IV. RF TRANSISTOR DESIGN CONSIDERATIONS The performance which can be obtained from the amplifier is determined, in the end, by the transistor. Not only must the transistor provide performance, however, it must provide this performance for a reasonable length of time. If the transistor fails, then the hybrid fails and cost to the system operator is the result. When the transistor engineer "begins to design a device for use in CATV amplifiers, then, he is faced with two main requirements. The device must offer a certain level of performance and it must do its job reliably. We will now investigate the RF transistor and the considerations that go into its design. The other epi parameter of interest is the thickness of the layer. It has been found that epi thickness is closely tied in to both device reliability and performance. One parameter that is commonly. used to describe highfrequency transistors is fT. This is the gain-bandwidth product of the device or the frequency at which the common·emitter, short circuit current gain, h", equals unity. A high fT means to the circuit designer better wide band gain perfo"rmance. The fr frequency can be related to the phYSical device in terms of the various delay times throughout the transistor. If the delay that a carrier sees in traveling through a device is less than in another device, then the It for the device with the least delay is higher. The thickness of the epitaxial region is related directly to one of these delay times; namely the rscCTc time constant in the collector. The rsc is the collector series resistance and to reduce this value for a given resistivity, we must reduce the epi thickness. There is another advantage to be gained from reducing the epi thickness which relates to distortion performance. Figure 4 shows a comparison of intermodulation distortion performance between two CATV transistors. The tran· sistors are identical in all respects except that one . 1, Starting Material Modern transistors are built using what is called the planar technology. This name arises from the fact that all areas of the transistor are found on the planar surface of the Silicon wafer. Figure 3 illustrates a cross-section Emitter 60,-------------------------------- 70 Figure 3, Planar-Epitaxial Technology iii" ~ 80 0 of a typical transistor structure as built using the planar technology. The first job of the designer is to decide what starting material he wishes to use for his transistor. The starting material consists of a wafer of silicon, approximately 10 mils thick and typically 2 inches in diameter. This silicon has been grown in crystal form while introducing a large concentration of impurities. This substrate silicon, then, is very heavily 'doped' so that the resistivity is very low. On the surface of this low resistivity silicon wafer is then grown a layer of silicon ~ 90 100 10 100 1000 lc(mA) Figure 4. IMO Distortion Performance as a Function of EPI Thickness 207 device was built on epi material which was 50% thicker than the other. It is seen that the device which was built on thin epi material offers better distortion performance at higher current levels. The reason for this performance gain with thin epi is the fact that the maximum current density available in a device increases as the epi thickness is decreased. This occurs because of debiasing of the collector-base depletion region by the resistive epi region. The thin epi device, then, acts like a larger device at higher currents, resulting in better distortion performance at these higher levels. overlay and mesh configurations are used primarily for modern power transistors. High frequency devices are sensitive to parasitic capacitances and this favors the interdigitated design. Figure 5 is a representation of typical transistor configurations. The base area is dictated by the power Base Contact Thin epitaxial material appears to yield very good transistors for CATV applications. Unfortunately there is a negative side to the story. The fact is that as the epi material is made thinner and thinner to achieve good performance the transistor becomes more and more sensitive to voltage variations. With thin epi the ballasting effect of the collector resistor is lost and the transistor loses ruggedness. The designer. then. wants to choose an epitaxial material which is as thin as possible for performance yet which is thick enough to avoid complete depletion and provide some collector ballasting. Interdigitated ~ I I Base ~ntact [13-------------------GJ 2. Vertical Geometry Once the starting material is decided upon, then it must be insured that a process is available which will yield a high performance vertical geometry. The importance of high fT in the CATV transistor has been discussed. Another time constant which can be reduced in order to increase fT is the delay due to carrier movement through the base region. The relationship for this delay is [~~ Emitter Contact G------------------1!] tb I Wb' 2.43 Deb', (NB' INBC) This relationship describes the time required for carrier transit across the base region in terms of base width, Wb; diffusion co-efficient, Deb; and doping gradient, NB' and NBC. The point here is that this delay time varies directly as the square of the base width. A desirable goal then is to produce a transistor which has a narrow base width. The well understood diffusion process can be used to control this parameter to a point. However, as narrower base widths are sought, device yields go down due to non-uniformities which are inherent in the diffusion process. State-of-the-art base widths with good uniformity are possible, though, by taking advantage of ion implant technology for the formation of the device junco tions. Another advantage of implantation is that it makes possible steeper gradients in the emitter and base regions resulting in higher fields and shorter transit times in those areas. I I I Figure 5. Typical Transistor Configurations handling requirements of the transistor. There must be enough area available to dissipate the heat which is generated. The amount of current to be handled by the device will determine what the minimum emitter periphery is. This is because at higher bias levels and frequencies a large transverse voltage drop occurs in the active base region under the emitter. This will have a de· biasing effect on the central portion of the emitter· base junction caUSing most of the current to pass at the emitter edges. Since it is known how much current the 3, Horizontal Geometry One' more item must be considered before the CATV transistor is ready to be built. A mask set must be designed, or, in other words, it must be determined what the device will look like, physically. First, the basic device configuration must be decided upon. There are three transistor contact geometries in use; these are interdigitated, overlay, and mesh. The 208 device will be required to handle, it is possible to calculate the amount of emitter periphery necessary to safely handle this current. The task now is to pack this amount of emitter periphery into the smallest base area possible, thereby reducing collector-base junction capacitance. Two examples of possible interdigitated designs having equal emitter peripheries are shown in Figure 6. It is seen Ep SA = = Ep/BA 24 88 = 27 Figure 6. Ep/BA Comparison for Square vs Rectangular Base Configuration that slightly higher Ep/BA ratios are possible with a design which is square compared to one with a higher aspect ratio. The problem with the square configuration is that the long emitter fingers required will restJlt in considerable voltage drop along their length. The result is that part of the device is not being used and hot spots will develop. Not only will device performance be reduced, but it will soon fail because of overheating. The design with the higher aspect-ratio is desirable since the voltage drop problem is eliminated. Another advantage of this configuration is that it is inherently better able to dissipate heat since the cells are not so closely coupled as in the square configuration. This design also has a problem, however. Although the emitter fingers are now short enough, the active area of the device is now quite long. The middle portion of the device will tend to draw more current which is not efficient. The solution to this problem is to add ballast resistors between the emitter feeder arm and the emitter fingers. (See Figure 7.) The ballast resistors are thus in series with the emitter can· tact metallization. If an emitter·base junction site begins pulling more than its share of current the series resistance will cause a proportionate drop in the input voltage for that site, thus limiting the current and preventing failure. An important point is the type of ballast resistor used. Two types of resistor are popular, thin film or diffused. Thin film resistors are susceptible to microcracking and they also are faced with a high Figure 7. Ballast Resistor Configurations thermal barrier since they sit on top of the silicon dioxide barrier. Diffused resistors are more reliable since they avoid the oxide barrier and are not susceptible to . cracking. It is also desirable to reduce the contact spacing and the emitter contact widths of the transistor for two important reasons.' A narrow contact spacing will allow more emitter periphery to be placed within a given base area. This is good since we have seen that gain performance depends directly on the amount of periphery available for current handling. A narrow emitter stripe is desirable since the resistance of the base region, rb', varies directly as the emitter contact width and it is necessary to reduce the parasitic rb' as much as pas· sible for gain purposes. Incidentally, reduction of rb' is good for noise figure too Figure 8 illustrates the impact of emitter width on base resistance. 209 metallics and the wire bond failures that result. Figure 10 illustrates life test data that shows an increased failure rate due to bond failures in the aluminum·gold system. Life Test at 95°C Case Temperature Unit Part Description 1 Figure 8. Effect of Emitter Stripe Width on Base Resistance Hours Accumulated Wlr.Bond Fallur. No's Wlr.Bond Failur. Rate % 601 B, 200 Hybrids With Aluminum 30700ie 1,162,000 24 4.1 2200, 2600 Hybrids With Gold 30400ie 1,188,000 0 0 Figure 10. Wire Bond Failure Rates in Aluminum/Gold Life Test The last step in the construction of the transistor is the deposition of metallization so that contact can be made to the emitter and base regions. (See Figure g.) The type Electromigration Resistance It was shown earlier that it was desirable to achieve a high Ep/SA ratio so as to obtain maximum performance from a device. This was achieved by placing the tran· sistor contacts as close together as possible. The use of such tight contact geometry forces the use of very narrow metal fingers. The resulting high current densities can lead to reliability problems as a result of electro· migration. Electromigration is a phenomenon which occurs in metal films as a function of time, temperature, and current density. For any given temperature, a certain equilibrium concentration of vacancies exists in all metal films. Self diffusion of metal ions throughout the film arise due to the metal ions being thermally activated into adjacent vacancies. In the absence of any external forces, the metal ion diffusion will be isotropic and will result in no net accumulation or depletion of mass in any given site. In the presence of an electric field, however, the metal ions experience a force due to their charge, inducing an ionic flux toward the cathode end of the film. In addition, the conduction flow of electrons in the metal due to the electric field will cause electron scattering off the activated ions and impart momentum to them in· ducing an ionic flux toward the anodic end of the film. In good conductors, the momentum exchange force domi· nates the electrostatic force and results in a net mass transport toward the anodic end of the film. The resu~ is an open circuit in the metallization strip. This void for· mation is accelerated by high temperatures and current density.' Figure 9. Transistor Metallization of metal to be used is an important decision. The two metals that are low enough in conductivity that can be used for transistor metallization are gold and aluminum. Aluminum metallization has been used for years as a conductor for transistors. Its advantages are that it is a well·understood process, it offers a good silicon contact without any barrier metallization, and it is inexpensive. However, considering the micron contact geometry of the RF transistor and the fact that it will be mounted on a gold hybrid circuit, then the decision is considerably easier to make. For a CATV transistor, gold provides the following advantages over aluminum.' 1. Monometallic wire bonding system. 2. Electromigration resistance. 3. Low contact resistance with elimination of shorts due to silicon'metal alloying. 4. Corrosion resistance. 5. Oxide step coverage. Allows use of tighter contact geometries. Aluminum has exhibited a high susceptibility to electro· migration for current densities above 1 0" A/cm~ Such a current density is easily realized in state·of·the·art RF devices. For a given device geometry there are only two alternatives to allow reduction of the current density in a device. Either the operating level can be reduced or a metal can be selected which has a higher mass and actio vation energy. The operating level cannot be reduced without a sacrifice in performance. We can still keep high performance and reduce the current density by using gold metallization. At 200"C, experiments conducted on identical transistors with gold vs. aluminum metallization showed an improvement in mean life time of two orders of magnitude using gold. Monometallic Wire Bonding System As has been described, it is desirable to have an all·gold metal system for reasons of reliability. A monometallic system eliminates the formation of gold·aluminum inter· 210 Contact Resistance Step Coverage Gold cannot be used as a single layer metallization because of its relatively low silicon eutectic temperature and its poor adhesion to silicon and silicon dioxide A barrier layer must be employed to prevent gold diffusion into the silicon and this barrier metal must offer good adhesion to silicon, silicon dioxide, and gold. Such a barrier is offered by a system utilizing platinum silicide, titanium and tungsten. The platinum silicide forms a good ohmic contact with the silicon; the Ti/W provides the necessary diffusion barrier and offers good adhesion to SiC), and silicon. Gold offers tremendous improvements over aluminum in its ability to cover oxide steps without decrease in metal thickness or cracking. (See Figure 11.) Aluminum is deposited by means of evaporation in a vacuum where the mean free path of the aluminum particle is long. This means that equal coverage of all surfaces is impossible even if the target is rotated during evaporation. The plate-up gold system reduces step coverage problems to insignificance. Narrow Contact Geometries The RF transistor must have very fine horizontal geometry to achieve the performance required in a CATV system. With aluminum metallization these narrow finger widths are achieved by etching the aluminum to remove it. Such a process, if done very carefully, will at best result in fingers of uneven width which are susceptible to high current densities and the associated reliability problems. The gold system is capable of providing microwave geometries with insignificant variations in line widths. In fact, the geometry on present gold CATV devices is narrower than some low-noise microwave devices which are on the market today. Aluminum has historically offered good ohmic contact without the need for barrier metals. In RF devices, however, at current densities well below electromigration densities, a problem of formation of silicon/aluminum alloy is ever present resulting in emitter-base shorts. Any hot spot formation will result in an increased alloying nte and early failure. Corrosion Resistance Under biased conditions, in a humid atmosphere, gold has demonstrated a lifetime more than 3 times that of aluminum. The failure mode in aluminum is electromechanical corrosion and gold is insensitive to this phenomenon. Plated Gold Silicon Silicon Figure 11. Oxide Step Coverage V. SUMMARY 1 The CATV system operator IS Interested In performance with reliability in the amplifier eqUIpment he uses 2 The basic bUilding block of the CATV amplifier IS the hybrid CirCUit The hybrid amplifier offers reliability advantages over discrete designs Including gold Circuit metalhzatlon and a reduced number of Interconnects The heart of the hybrrd circuli IS the RF transistor 4 The design of a reliable transistor tor use In CATV amplifiers requires a knowledge of basIC design values plus the availability of state-ol-the-art processing Points to be considered Include startmg matenal vertical geometry honzontal geometry configuration metallization 5 Life tests show the improvements In reliability to be gained by carefullransistor design APPENDIX REFERENCES Denvatlon of reliability expresSion lor chance failures· R(O = e· At x·. Ilems IS conttnuously de· caYlng so Ihallhere are X Ilems al lime t the change of POpulallon In one Interval dt IS dX dt DIVided by Ihe total population X at t. thiS gives the negative rate at which the populaltOn changes at time I If an anginal population of .A=sQ<---.5!!=~ X X 1 dt ·Adt = dX X then Integratlng over the lime pertod being conSidered. t -JAdt = InX C = InX fnC o for t = O. X = Xo Then C = X t And X X. = e.t . JAdt If the rale of decay. A IS constant then X X. = e." ·AI Since X X IS probability of surVival for a decaYing popu· laltOn then R (I) = X X, = 211 e.~ ·A t , Mike Flahle Reliability and MTF - The Long and Short of It Microwaves. July 1972 2 James Humphrey and George Luettgenau Reliability ConSlderatIQ1s In DeSign and Use of RF Integrated CirCUits"· IEEE NCTE Conference. February 1976 3 Elhotl Phllofsky ··Deslgn Limits When USing Gold· Aluminum Bonds Motorola Inc Semiconductor Products DIVISion 4 R Flahle and M Weiss A Study of the Advantages of Gold Metallization In t~e Manufacture of Microwave TranSistors TRW Semiconductors Technical Note 5 Igor BazouSky Reliability Theory and Pracl!ce Prentice· Hall 1961 6 J R Black ··Electromlgratlon Failure Modes In Aluml· num Metallization for Semiconductor DeVices Proceedmgs of the IEEE Volume 57 Number 9 September 1969 212 AN1028 35/50 Watt Broadband (160-240 MHz) Push-Pull TV Amplifier Band III This note describes the performance of a broadband ultra linear push pull amplifier designed for service in band III TV transposers and transmitters. Devices used: two TPV 375. Basic amplifier specifications IMD (1) = - 51 dB at IMD(1)=-48dB V ce = 28 volts; Po = Pgain 35 W Po = 50 W Total = 4.4"A = 10 dB input VSWR at output VSWR' < < 1.6 1.5 (1) vision carrier - 8 dB. sound carrier - 7 dB. sideband signal - 16 dB. General design Consideration The principal aims were - employ a relatively simple solution permitting us to obtain the optimal performances from TWO TPV 375. - simplify the design and reduce the cost. The main consideration was to obtain the maximum output power with the best IMD over the band. To obtain this requirement the output match and losses must be the best possible in all the band. The second consideration was to obtain the maximum gain by reducing the input matching circuit losses to a minimum. These factors led us to choose matching circuits using quarter-wavelength transformers at the input and output which permit us to : - reduce the load and source impedances to low values with low losses - couple two transistors in a push pull configuration. Because the output and input transistor impedances are in series. due to the push-pull configuration. the required' transformation ratio is one half of that required for a single ended stage. The first approach for the circuit calculation was made from the input and output impedances given in the TPV375 data sheet and matched to the proper impedance levels using a Smith Chart. The element values were then optimized with the aid of "COMPACT» program. Amplifier Design The basic block diagram for the amplifier is shown in Figure 1 and the circuit schematic is shown in Figure 2. The input and output circuits are each composed of two networks: a quarter-wavelength transformer-balun and a matching network. The quarter-wavelength transformer impedances have been chosen to be easily built using microstrip technology. Input circuit The input circuit is shown in Figure 3 and the input impedances are shown in Smith Chart 1. The low transistor input impedances are transformed into higher impedances near the real axis by Capacitors FF. The (EE. DO) series elements and (CC. BB) parallel elements collapse the amplifier input impedances around 8.5 Since the devices can be considered in series at this point the impedance is doubled to 17 The quarterwavelength transformer balun (AA) completes the match to 50 n. n. n. The transformation ratio is 2.8 : 1. The maximum theoritical input VSWR is 1.80 : 1 and the maximum experimental VSWR is 1.60 : 1. Output circuit The output circuit is shown in Figure 4 and the output impedances on Smith Chart. II. Since the output impedances are higher than the input impedances. the output matching network is simpler and the quarter-wavelength transformer ratio is lower. The inductors aid the matching but primarily provide for good stability at the low frequencies. and are used for collector bias. The output quarter-wave-Iength transformer ratio is 1.6 : 1. The maximum theoretical VSWR is 1.16:1 and the maximum experimental VSWR is 1.44:1. 213 Amplifier Performances IMD versus output power: Figure 5 Input and output return loss and VSWR = Figure 6 Gain versus frequency: see Figure 7 1 dB gain point compression: 70 W Bias conditions: V co = 28 V; Total = 4.4 A. Technology and layout considerations The epoxy-Glass 1/16 inch (~r = 4.1) is used as board material except for the input and ouput transformers. The glass - Teflon 1/50 inch (~r = 2.55) is used for the transformers (see the details Figure 8). We have considered for a microstrip line that after W (Width) from the conductor strip edge the fields are negligible and we can size the ground conductor to be 3 W without perturbing the propagation. This kind of transformer has the following characteristics: - We can have any impedance values within realizable min-max limits. The vertical dimensions are small and the mechanical realibility is good. Good repeatibility. The bias circuits are included with RF circuits in order to give a compact amplifier: Figures 10 and 11 show the layouts and the Figure 12 the physical layout of the push-pull amplifier. Combined pairs of push-pull Amplifiers - In general several push-pull amplifiers are used for the final stage of the TV transmitter amplifiers. They can be combined by pair with quadrature combiners (see block diagram Figure 9). The advantage of using this kind of coupler is that the input and output VSWR become good (> 20 dB rtn. loss) in comparison with the relatively high original VSWR of the push-pull amplifier. General Conclusions Push pull techniques simplify the required circuitry and associated losses. The problems associated with 3 dB hybrids in cascade in parallel are required are minimized. insertion loss and imbalance - when four devices With additional effort both the input and output VSWR could be improved to 1.2 : 1. Good repeatability in production without variable components being required. I 1 INPUT 50 OHMS. OUTPUT 50 OHMS. l' r 1 Figure 1. Push-Pull Circuit 214 Vee VeE SO '36 LI 30 .... IN ~/4 al 50 ohm "7pF 240MHZ I· .x'4 at 240 MHZ 4OA. H· ,-, IOOpF t 47pF P: l'1.Ae .,200MHZ UK VI( " LI CIRCUIT DIAGRAM 470 LI .. 8 turn •. 10 6 mm I .. 8 mm. wire .6 mm LJ .. 2.5 turns. 10 6 mm I 3X» 330 -10mm.wire'mm SW Vee Figure 2. Circuit Diagram On the smith chart the impedances are represented by : ss AA I I L· DO CC L· FF EE L· Z, (01 (mm) (oFI Z, (01 (mm) (pFI Z, (01 (mm) (pFI Calc. value 30 313 13. 100 ".3 47 50 80.8 238 Empirical value 30 313 100 100 15.0 47 50 82.5 200 • L is given for t, "'" 1 Figure 3. Input Circuit 215 IMPEDANCE COORD....ATES- 50-OHM CHARACTERISTIC IMPEDANCE SMITH CHART I o I" •• ',' IRt:I"~'t' - VOL ". NO. I, ",'lO -Ill, I, .'''11lA1. RADIO COMPANY jl" SU, JAN ,''''''' Wlif Figure 4A. Input Circuit 216 to.CO_D. _lU, _10 . . 'OR""l·~ IMPEDANCE COORDINATES- SO-OHM CHARACTERISTIC IMPEOAHCE SMITH CHART II PARAMETERS '..Ir·"2 ,"i ~ "~' ',',' !, ',', 0, ~~-'r"""''''''''-"+'''''''''+'-++'H-+---;~;1'I§ a'~"""'~"'t---'1,'" 3'1 I a:: I ~, • I ~ I CENTER I OlfllllAL JlAUIO c:O .... AN' WIST Figure 4B. Output Circuit 217 COIICOIO, ..... fORM !l301-7.Z ".,.... 111 USA VSWR RETURN LOSS OdB IMo' PUSH·PULL VCE = 28V -SOdB liMO - VISION - 8dB - SIDE BAND - 16 dB -SOUND - 7dB -55dB / -60dB -65dB / / / V - 10dB - / - --........ ~ OUTPUT -20 PUSH·PULL TPV375 VCE = 28V fo = 225 MHz IC = 4.4 A 1.9 INPUT INPUT x TPV315 IC = UA 1.44 1.22 1.12 V -30 PO WER OUT 10 20 30 180 160 40 W PEAK SYNC Figure 5. IMD versus Output Power 220 200 15 10~------------------------~~--____-= PUSH· PULL VCE = 28V 180 TPV 375 IC = 4.4 A 200 240 MHz Figure 7. Low Level Gain versus Frequency 9 w at least to the matchIng circuits Short Circuit FREQUENCY IMHll Figure 6. Input and Output Return Loss versus Frequency dB 160 240 MHz epoxy·glass «. = 4.1 ;~.) a.) Quater Wavelength Balun = ; '.~m / b.) Equivalent Circuit Figure 8. 218 ••••• ClfCUlts TPV 375 push-pull input Quadrature combiner Quadrature combiner output TPV 375 push-pull Figure 9. Combined Pair of Push-Pull Amplifiers input input printed tra nstormer 100mm output printed transformer output Board material: epoxy·gJass; 1/16 inch; Er = 4.1 Figure 10. PC Board Layout (Not to Scale I input and output ground input strip (Zo = 30) output strip (Zo = 40) r 50 mm l Board material: glass teflon; 1/50 inch; Figure 11. PC Board Layout for Input and Output Quater-Wavelength Transformer (Not to Scalel 219 tr = 2.55 J J • Figure 12. 160-240 MHz Amplifier II J 0 BB On the smith chart the impedances are represented by : ~~Q fAA ~_cc---------, QI J AA I • L is given for Er = , :1° BB Z, (nH) (0) j CC L' (mm) Z, (Q) L' (mm) Calc. value 11.7 21.6 37.5 33 312.5 Empirical value 53.1 25.0 37.5 40 312.5 Figure 13. Output Circuit 220 AN1029 TV Transposers Band IV and V Po 0.5 W/1.0 W This note describes the performance of a broadband (470-860 MHz) ultra linear amplifier designed for service iri band IV and V TV transposers. Device used: TPV 596. Basic specs: I.M.D. Vce 60 dB max. at Po = 0.5 watts = 20 volts; Ic = 200 mA Pgain = 11.5 dB min. The approach used is intended to be straight forward and inexpensive as follows. 1) The load line be defined to provide the correct match for peak power (P. sync). 2) The VSWR at the collector be less than 2 : 1. 3) The input match be designed to provide flat gain with decreasing frequency. 4) Use computer aided design. 5) Use a three tone norm Pvision = Psound = Psideband = - 8 dB 7 dB 16 d8 6) Circuit realization to be a distributed design built upon teflon glass copper clad circuit boards. However the design will be analized using Er = 1.0. The input and output impedances were taken from the TPV596 data sheet and plotted on a smith chart. First consider the input. To have flat gain with an optimum collector load, the basic physics of a class «A» biased device defines a gain slope of - 6 dB/octave which must be compensated for. The band of interest is 470-860 MHz which is .915 octaves which implies that 5.25 dB of gain must be compensated for if the device is perfectly matched at 860 MHz. This means that a transmission less of 5.25 dB or a VSWR for 11.0:1 must be employed at 470 MHz. The input Z is converted to V on Smith Chart (I). The point at 860 MHz will intersect the constant conductance line equal to 1.0 (20 m U) if it is rotated 0.14 A using a 20 m U (500) transmission line. After this rotation a capacitive stub or chip capacitor is used to resonate the susceptance at 860 MHz; A capacitive stub or a chip capacitor equal to 16.7 pF can be used, and the result is shown on Smith chart (I). It is interesting to note that the VSWR vs frequency can be adjusted for gain flatness by selecting an optimum Zo for the capacitive stub. It is also obvious that the locus of impedances at the circuit input can vary between the locus of points defined by using a chip capacitor, and the imaginary axis by using a stub with Zo = ". Graph (II) is a plot of these results. Because infinite isolation doesn't exist between the output and input of any transistor, and because the required network is very simple, the input circuit will be optimized empirically. A computed aided circuit will be defined for the output only. It is also indicated that a combination chip capacitor and stub may provide the best results. The output circuit considerations were first determined using a Smith Chart approach. It must be clearly understood that computer optimization is only as good as the circuit configuration and associated computer instructions. The approach follows: Smith Chart (II) 1) The device output impedances are first converted to admittances and plotted as the conjugate (V load), 2) In order to allow easy collector lead soldering a Zo = 50 U. 3 mm long transmission line is used. Since the Smith chart is normalized to 20 m<> (50 n) we can rotate toward the load directly as the chart is configured. 3) Since the balance of the circuit used Vo = 10 mil (100 n) we next normalize the chart to 10 mii. 100 n transmission line was chosen as a good compromise between physical length requirements and ease of realization on Teflon Glass. 221 4) The next element. a shorted shunt transmission line less than )../4 in length reduces the imaginary part by moving each point of admittance along a line of constant conductance. The length was chosen to locale the lowest frequency point (400 MHz) near the real axis so that the locus of points would be more equally distributed about a 2.0 : 1 VSWR circle. 5) The resultant locus of points are then rotated with a 10 mi1 (100 0) transmission line to a degree which locates the admittance point of 860 MHz near the line of constant conductance equal to 2.0 on Smith Chart (II). This conductance is exactly equal to 20 m() since the chart is normalized to 10 mn. 6) The final step is to use a parallel resonant circuit which will reduce the imaginary pacts at both the upper and lower frequencies. The following approach was used to calculate the element values for the antiresonant circuit. By observation of the smith chart it was decided to place the 460 and 860 M Hz points on or just inside the 2.0 : 1 VSWR circle. It then follows that at f( = 460 MHz 1 W \ C - - - = -0.4 W\L at f2 = 860 MHz 1 W 2 C - - - = 1.7 W2 L The 2 equations with 2 unknows are solved with the following result. L =0.189nHy C = 496.11 pFd since we are normalized to 10 m(; Lactual = 0.189/.01 nH = 18.9 nHy Cactual = 496.11 x 0.1 pF = 4.96 pFd 7) The result is normalized to 20 m(j with the final result shown. Zo 100 50 0 Calc. Value 45.7 mm 3.78 mm Empirical Value 8.5 48.8 mm 1.5 mm TPV 596 Optimized Value 50 0 100 0 100 0 1000 3 mm 76.1 mm 29.3 mm 4.9 pF 50.4 mm 3 mm 98.8 mm 5.5 pF 61.6 mm 39.62 Graph (III) shows the various VSWR calculated compared to the theoretical best curve and the actual VSWR measured . . Graph (IV) shows the collector load VSWR for the calculated. optimized. and actual result. Graph (V) is a plot of the single ended amplifier results taken with a network analyzer. No component losses were considered for the theoretical and optimized analysis. The final circuit was also optimized empirically from 470-860 MHz using a network analyzer. The following results are a·summary of performance. bias conditions circuit configuration and recommended hybrid adaptation. 222 starting Imp. rotated Adm. final Adm. w/Chip Cap. final Adm. w/1 0 n Stub final Adm. w/50 n Stub 0----0 X X • b-------A Figure 1. Smith Chart (I) 223 • 0----0 starting Adm. 50 n rotation 100 n translation equiv. shunt Ind. 100 n rotation parallel L-C final Adm. 50 n translation •• lC Ie 0----0 11:. t;,. 8-----0 }I}I • Figure 2. Smith Chart (II) 224 • VSWR Transmission Loss IdB) 50,0 ,*,-0 /O.D Ideal Chip Cap. 30,0 /6,0 ,, ", 1'1.0 ,2,0 - Actual I!o.o 18,{) 9,0 10nStub 50 n Stub ,, 8,0 7,5 1.0 ,.s- ,, 6,0 , " ,, laO 5:5" , 5;0 9,5 g,o 8.5 e,O 'I,D ;r;S~O 3,> 6,S6,0 :1,0 S;5 ~" 'f.5 eo '1.0 ~5" ",0 t,O 0,9 t.,t; 0,8 o,?0,6 :Z,O Q6' 1,9 0." ',1 , 1,5 13 1.0 4tJO D·l o SOD roo 600 Frequencv (MHz) AN.50 Figure 3. Graph III - VSWR versus Frequency 225 900 Transmission Loss (dB) V.sWR 5,0 f!,S Preoptimization Postoptimization Measured '1,0 $,0 f,O 0,9 2,5 0,8 0,-=1 e.o 0,6 f,9 0,4 o,S- l,r 0,2 f,!J'.. t31 _______~~-------+~~==~:+-------~~------_+ ,0. ?OO 600 0 eoo 800 Frequency (MHz) Figure 4. Graph IV - VSWR versus Frequency 5,,- __ 522---Return Loss (dB) ---4- -- -" tI, I B U. II to , .. ..... ..... .... .... ------------------~., ", ,, , / 'I 'I I .1, \ 1 \ \ .~~. I ". I ( . I \ /,1 ')~1 \ I \ s .. " Figure 5. Graph V - _~ 1/1 .,t'" \ \1 0 .... -. \ ) a s .. ---- C, 1 , o _II _I) -IS I, -f' ".. -loo Frequency (MHz) 100 TPV596 Amplifier Performance versus Frequency 226 Sro Fr,,'t» Vt.,ASD 2nF IN tf01 1 '" IO~F ~ 5o.n. 1 ~ '0,,- 1 Class A VCE ~ 20 V - IC ~ 220 mA fa ~ 860 MHz - WAVELENGTH (Agi at 860 MHz (material: Glass teflon 'r ~ 2.55 - 1·16"1 Transistor - TPV596 Figure 6. Circuit Diagram for 470-860 MHz Amplifier 11..n. Figure 7. Class A Bias Circuit 227 TPV 596 BROADBAND AMPLIFIER FREQUENCY RANGE POWER OUTPUT AT : POWER GAIN INPUT RETURN LOSS" OUTPUT RETURN LOSS: VOLTAGE SUPPLY TOTAL CURRENT 470 MHz-860 MHz - 60 dB IMD· ~ 0.5 W 11.5 ~ G ~ 12.7dB < - 1 dB < - 11 dB - 23 V (VeE = 20 V) 220 mA "IMD : Vision: - 8 dB ; Sound carried: - 7 dB ; Side band: - 16 dB RECOMMENDED CONFIGURATION "INPUT RETURN LOSS This amplifier must be used by two connected together with two 3 dB quadrature hybrids to have a balance amplifier with a good input VSWR. IN 3 dB 3 dB Hybrid SOU Hybrid OUT 50 ~! "3 dB - 90 0 Hybrid coupler fram - ANAREN 10264-3 SAGE wireline 3 dB Hybrid 4450 900 IMD VS OUTPUT FOR A SINGLE STAGE VeE = 20 V-220 mA F = 860 MHz; Vision Pout (W) IMD (dB) = - 8 dB ; Sound Carrier 0.25W - 67 dB = - 7 dB; Sideband = - 16 dB 0.5W - 61 dB lW - 55 dB F = 860 MHz; IMD DIN 45004/B RL = 75 ohms 1.5 V/75 ohms 2 V/75 ohms IMD = - 66 dB IMD = - 60 dB 228 AN1030 1 W/2 W Broadband TV Amplifier Band IV and V This note describes the performance of a broadband (470-860 MHz) ultra linear amplifier designed for service in band IV and V TV transposers. Device used: TPV 597 Basic specifications IMD (1) = - 60 dB at Po = 1 W V ce 20 V; Ie = 440 mA PRain = 11.5 dB. (1) Vision carrier - 8 dB. sound carrier - 7 dB. sideband signal - 16 dB. General design considerations In general to obtain a flat gain for broadband amplifiers which use .ransistors with about variation per octave we can use two techniques: 6 dB power gain feedback technique (eg emitter resistor and a negative feedback with a selective circuit between the collector and the base). or reflect the input or the output power selectivly to have an insertion loss of 6 dB per octave .vith 0 dB for the highest frequency. (There is also another technique which uses a selective attenuator). With the feedback technique we can have a good input and output match. With the second technique we need to reflect the input power and have a good output match in order to obtain a good IMD. It means the input VSWR is very high for the low frequencies. The second solution is simpler than the first and if we use two amplifiers connected together with 3 dB quadrature hybrids to have a balanced amplifier this inconvenience disappears. We have chosen for this amplifier this second solution. For the larger broadband amplifier (eg 170-860 MHz) this solution must be rejected and the only acceptable solution is to use the feedback technique. Amplifier design The first approach fcr the circuit calculation was made by using the Smith Chart from the input and output impedances given in the TPV 597 data sheet to have. at the input. a reflected power so that the gain will be flat and at the output to obtain the best match possible. INPUT VSWR VERSUS FREQUENCY TO OBTAIN A FLAT GAIN: The power gain can be approximated by: G ~ Fmax (--F )2 Fmax is the frequency for which power gain drops to unity. The transmission loss due to the input reflection is: ~=1_[p[2 P is the reflection coefficient. To have Gx constant we must have: Gx ~ (~,;.. )2 [1-lp[2) = Gfl = GH is the gain at the highest frequency used (F II ) or [p[ ~ 1 + [p[ VSWR = - - - ~ 1-[p[ 229 (F;:x r Figure 1 shows the theoretical VSWR versus frequency with an insertion loss of 0 dB (implies p = 0) for 860 MHz. We have defined the input circuit from the TPV597 input impedance to have an input VSWR as close as possible to this curve, and have assumed that output circuit losses versus frequency is negligible. After we have calculated separately the input and the output circuits, we optimized some of the parameters by means of the global amplifier and the TPV597 S-parameters, with the COMPACT Program. RF equivalent circuit: Figure 2 Program: Figure 3 Calculated gain and empirical gain: Figure 4 Calculated and empirical input VSWR : Figure 5 Calculated and· empirical output VSWR : Figure 6 Amplifier Performance IMD versus output power: Figure 7A IMD versus frequency: Figure 7B Input return loss and VSWR : Figure 5 Output return loss and VSWR : Figure 6 Gain versus frequency: Figure 4 Bias conditions: Vee = 20 V; Ie = 440 mA Technology and layout considerations - The glass Teflon 1/16 inch (or = 2.55) is used as board material. This substrate is soldered to the heatsink to have a good contact and repeatable results. Figure 8 shows the circuit diagram and the bias circuit; Figure 9 shows the PC board layout. Combined - Transistor Stage In many instance the power output requirements of transposers exceed the capability of a single transistor, which forces the designer to use combinations of transistors. They can be combined by pair with quadrature combiners (See figure 10). Since quadrature combiners have the ability to channel the reflected power from the amplifier into the fourth port of the combiner it means the input and output VSWR become very low (VSWR < 1.2). The power gain is reduced due to the couplers insertion loss by 0.6 dB. Coupler imbalance should also be taken into account as causing some IMD degradation. Input VSWR 1+ /1 -(~)T/2 VSWR = ----...;...-1 ~. -11 -(~)T/ -0-. -1!1 From global amplifier and S-parameters A- - IJ.. -£:. Empirical VSWR 5 Frequency (MHz) loaD Soo '00 Figure 1. Input VSWR 230 cc aa AA Z, pF L (mm) pF (n) DD Z, FF en) L Z, (mm) (n) L (mm) Calc. value 4.5 50 32.0 29.3 25 14 50 72.2 Empirical value 4.7 50 45.4 10.0 25 14 50 34.9 GG Z, HH L (mm) Z, L (n) (n) (mm) Calc. value 110 28.4 45 14 5.1 Empirical value 110 27.9 45 1. 3.9 L are given for MET CAP TRL CAP 0ST AA AA BB CC DO TW0 EE SST FF TRL GG TRL HH CAP II SST JJ CAP KK CAX AA PRI AA END C: r = 1. JJ II Z, pF KK L (mm) pF 75 50 3.5 75 38.4 3.3 (n) Figure 2. RF Equivalent Circuit for Compact Program z:z. PA SE PA PA S1 PA SE SE SE PA PA KK SI -4.61 50 -41.64 - 25.39 25 14 1 50 50 - 63.43 1 110 28.44 1 45 14 1 - 5.134 75 49.98 -4.129 CIRCUIT DEFINITION 50 470 500 600 700 800 860 } FREQUENCY (MHz) END .92 .91 .93 .93 .92 .91 176 2.38 175 2.21 171 1.80 170 1.57 169 1.40 167 1.30 .033 31 .55 - 166 71 .034 33 .54 - 167 63 .037 34 .56 -170 59 .039 36 .59 -168 54 .043 38 .58 -165 52 .045 40 .58 - 166 72 POLAR S PARAMETERS FOR Twfli EE (TPV 597) END .5 0 100 1 12 100 100 2 12 OPTIMIZATION DATA END Figure 3. Compact Program 231 VARIABLES (-) GRADIENTS (1) : 4.51899 (2) : 32.0136 (3) : 29.2938 (4) : 72.2399 (5): 5.16145 (6) : 3.53445 ERR. F. = 7.809 (1) : (2): (3): (4): (5): (6) : - .894864 .704452E-Ol 2.69282 .287748 1.68585 .267730 HOW MANY ITERATIONS BEFORE NEXT STOP? O' RESULTS IN FINAL ANALYSIS. WANT INTERMEDIATE PRINTS (YES = l' NO = O)? TYPE TWO NUMBERS: (I. J) : 0 SEARCH INTERRUPTED. FINAL ANALYSIS FOllOWS: POLAR S-PARAMETERS IN FREa. Sll (MAGN <-' ...... --. - ...... '"7" '-<6-...' - ,. ...g ellc. vllue ------~ Em pirical value ~--.~. .J 10 dB I TPV 597 SINGLE STAGE Vep,. 20 V Ie = 440 mA 5 dB l I I.[ 470 500 600 ~ 700 Figure 4. Gain versus Frequency 232 BOO 880 101Hz Frequency (MHz) o dB 1'---'-1>_--. ~------~'-""""'-"""" - -........ ___ A-..... ...... ........ 3.5 -5dB TPV 597 SINGLE STAGE VeE:: 20 V - l~ = 440mA 10dB I \ _-------------.:._.......J \\ 19 '.41!:~ Calc. value \ - 15 dB 1.44 I:::----,=--------~---------~--------_r_----___j---+ Frequencv (MHz) 470 500 600 700 800 860 MHz Figure 5_ Calculated and Empirical Input Return Loss o dB OUTPUT VSWR TPV 597 SINGLE STAGE - 5 dB 35 1,,=440mA VCJ!. :: 20 V - 10 dB __ 1 y ...__- _ - -.!o-- - - -.~ - .-A- ----- 15dB , , ~.",,- 20dB / " \ \ , , \ \ 25 dB \ \ \ I / I \ -30 dB value ---1.44 I . \ - ~Calc. .)( ~-\ - .9 \\ / I I I \ I / ,,-- ..., ~ ( /1 ..----\/ . . _ ',/:// r" -'---i ..... ~ I I -', ;r/ / " Y / \ / \ T \ \ \ / \ \ \ 700 1.12 / ) \ \1 I / l I I I I -- ./ Frequency (MHz) 800 Figure 6. Calculated and Empirical Output Return Loss 233 Empirical value 1.22 ~ 55 IMD (dB) +---------------+-------------~------------_7y TPV 597 Single Stage VISION CARRIER SOUND CARRIER SIDEBAND -60 - 8 dB 7 d!l 16 dB +---------------+-------------~~------------4 VCE .65 +---____________1-7--__________-+__ 1,. F. 70 = 20 V = 440 mA = 860 MHz +-------~L-----+--------------I--------------_1 -75 +--------I--------I-------~___.... Pout (W) 0 1 0.5 Figure 7a. IMD versus Peak Synch Output IMD (dB) ---- -60 -~ i -65 ! SINGLE STAGE POUT SYNC .. 1W I 8dB- ---- - - - - - - VCE = 20 V VISION CARRIER SOUND CARRIER 7 dB I, = 440 mA SIDEBAND -16 dB I I I I I , -70 i I ! 1 l 700 Figure 7b. IMD versus Frequency 234 1.5 300t\. lOv v BIA"o--r---r---r---, . Lengths are given at Fo = 860 MHz (3.10. ) Ag = - - - - Fo.Jc..rr Glass teflon Er = 2.55, 1 16" board material. a) Circuit Diagram Vee 4.7 1K 1N4148 330 V81AS 4,7K 10nF b) Class A Bias Circuit Figure 8. Circuit Diagram and Bias Circuit 235 INPUT-- _OUTPUT 50 mm Board material: Glass Teflon; 1/16 inch; e:, = 2.55 Figure 9. PC Board Layout (Not to Scale) TPV 597 amplifier High input (low VSWR) Quadrature Quadrature VSWR combiner combiner High output (low VSWR) VSWR TPV 597 amplifier The 3 dB quadrature combiners can be supplied by: - ANAREN (10264-3) SAGE wireline (4450900) Figure 10. Two Broadband Amplifiers Combined with Quadrature Combiners 236 AN1032 How Load VSWR Affects Non-Linear Circuits Prepared by Don Murray RF Devices Division Lawndale, California pedance of their loads, either in test systems or equipment environments. It is easy to compen· sate for the insertion loss errors in an attenuator, but it is much more difficult to compensate for variations in the input impedance difference bet· ween attenuator pads, that IS, the load VSWR. tion of collector current and transistor die temperature. The theoretical approach will evaluate the changes in amplifier output power (Po) for a Reprinted from RF Design Magazine given change in load resistance (RL). For simplicity, let us assume the following H your amplifiers test out fine in the lab but hypothetical conditions, which are typical of fail DC testing, the testing environment Let's ex'amine RF correlation on both an empirical today's RF power transistors. not the product - is likely at fault. and theoretical level. Hypothetical conditions: VCC = 28V The empirical approach is shown in Table I, VCESAT = 1.5V where several test circuit loads (consisting of POUT = 50W series attenuators, directional couplers and RF Frequency - 1.0 GHz switches) were assembled. The insertion loss and Solving for load resistance: input impedance of each load string was Rl _ IVcc - VCESAT)' 702.25 7.Dm measured. Following this, the individual loads 2Po 100 were connected to a given test circuit containing a common base microwave power transistor. The Additionally, assume that a simple two·section power meter used was also a constant. impedance matching network matches the 7Q to Confident that both design and production pro· cedures are satisfactory, you begin series produc· Table I shows insertion loss, insertion loss correc· 50Q. Let this two·section match consist of two tion. But when the first units reach RF test. not tions, indicated RF power, and actual power data ).f4 wave transformers. of each load string. A maximum error of 0.52 dB one meets specification. Yet when you retrieve Given the conditions we have hypothesized, the was detected with a standard deviation of .19 the units, they test OK in the lab. dB. All these loads had a VSWR less than 1.1: 1 Rl of 7.02Q represents the collector load that will yield the best simultaneous satisfaction of at the frequency tested. A VSWR of 1.1: 1 is What's wrong with these amps? Probably device efficiency, device gain, gain transfer nothing. This scenario, in one form or another, is better than the published specifications of com· characteristics, and saturated power. all too common in the design and manufacture of mercially available attenuators, directional couplers, and RF switches from most leading non·linear RF circuitry. The culprit is correlation For minimum Q, with a 2 section match, the of test systems. A difference of .5 dB is enough manufacturers. A VSWR gf 1.5: 1 is a typical to fail units that are perfectly good, resulting in VSWR specification limit at 1.4 GHz. It must be transformation ratio of each section is Consider the following scenario: You're designing and implementing into production a broadband Class C power amplifier. During your design phase, you follow all the rules of science and also dig into your bag of electronic tricks to meet the design specification. Your design is fabricated and tested successfully in the lab. Twenty·five more units are built in the lab and they, too, test out fine. EMPIRICAL APPROACH unnecessary and expensive retesting or even reworking. Still worse, a half dB error will pass units that don't meet specs and never should be shipped. noted that many users will gladly pay an addi· tional nominal charge for components meeting a tighter VSWR spec. J 1144Q )Q ),4 long 50Q THEORETICAL APPROACH Such correlation errors will disrupt an even more The vehicle for the theoretical discussion is the important function, that of maintaining product well known expression: continuity. A device built in 1982 should perform IVcc - VCESAT!' the same as an identical model number device Po = 2Rl built in 1976. Another way of saying this is that a device tested in a 1982 test system should Where: Po = Power output produce the same results when tested in a 1976 Vcc = Collector supply voltage system. The key, of course, is RF correlation. VCESAT = Collector· Emitter saturation voltage What is RF correlation? Simply put. RF correia· Rl = Load resistance. tion occurs when target error limits are estab· lished and adhered to on a continuous basis This expression is valid for a narrow range of Rl 110% range maximum). Over a wider range of among two or more testing stations. Such cor· Rl, significant changes in VCESAT occur as a relation is essential to cost ·effect production of non·linear RF and microwave power amplifiers, function of Rl. Output power varies with the whose circuits are extremely sensitive to the im· square of VCESAT. VCESAT is a very strong func· 237 5O.,aQ .1.4 long }J ~2.67. ZO 1st section = 1/""'1""7)"'12-=.6:=71""'17::-) 11.44Q ZO 2nd section - V (7112.67)150) 3D.58Q ),/4 @ 1 GHz = 2.95" = .075m Table II shows the transformed impedance at the input of the matching network as a function of Table I, Microwave Load Substitution Study The vehicle used for this test was a production test fixture and correlation sampte #2 for the TRW MRA1417·6 broadhand, high·gain transistor. Measurements were taken at 1400 MHz with IIput power of 1 1W Load # I 1 2 3 4 5 6 7 8 Maasured Power Level Circuit Return Loss 1.IW 7.7W 7.6W 7.65W B.OW 7.2W 8.3W 7.75W 7.78W 35 dB 16 dB 15.5 dB 15.5 dB 15.5 dB 16 dB 15.2 dB 16.2 dB 16.8 dB Collector Current .51 A .5 A .51 A .51 A .505 A .51 A .505 A .503 A Delta Maasured Insertion Loss 30.03 30.03 39.66 39.68 39.B 30.16 39.78 39,73 39.7 Calibration Error dB dB dB dB dB dB dB dB dB +.03 +.03 -.44 -.32 -.20 +.16 +.22 -.27 -.30 dB dB dB dB dB dB dB dB dB Actual Power from Reference thru 7.75W 6.B7W 7.10W 7.63W 7.47W 7.89W 7.28W 7.26W calibration . Load Input Return Loss reference -40.2 -40.2 -30.5 +.38 dB - .07 dB -.16 dB +.08 d,B - .27 dB - .28 dB -34.1 -34.1 -30.1 -31.7 -32.7 -35,4 Impedance Angle Raal Imaginary 99.1 99.1 -77.5 -171.5 68.1 -128.0 -144.6 11.9 -111.9 49.8 49.8 50.6 50.4 50.7 51.1 47.9 49.0 49.1 + 1.0 + 1.0 -3.0 -2.0 -1.9 -3.0 -1.5 -2.4 -1.5 Largest Delta after calibration correction is 0.52 dB. Mean value of the measured power = 7.41 W, Standard Oeviation •. 34W • ,19 dB. Note: - 30 dB RETURN LOSS = e of 0.03 and VSWR of 1.06: 1. Table II. RL Effects on Output Power Transformed Load Resistance IQI Output Power IQI 45 6.30 55.73 Load Resistance IWI 46 6.44 54.52 47 6.58 53,36 6.72 48 Cumulative MB ~dB .095 .095 .093 .189 .091 .280 ,090 .370 .087 .457 .086 .543 .OB5 .628 ,083 ,710 .081 .791 .080 .B71 52.25 49 6.86 51.1B 50 7.00 50,16 51 7,14 49.18 52 7.28 48.23 53 7.42 47.32 54 7.56 46.45 55 7.70 45,60 BI Make a bad circuit look good. This analysis was done for a single frequency. The problem is compounded in a broadband environment by requirements for a good broad· band load impedance. TEST EQUIPMENT ACCURACY Test equipment manufacturers have produced some very impressive equipment in recent years; however. the accuracy of a well constructed system using the latest equipment available is generally considered to be no better than ± 3% . Considering the number of variables in RF testing and the magnitude of the task faced by the test equipment manufacturers. ± 3% is no small achievement. However. ± 3% is ±.13 dB. This ±.13 dB added to the ± .435 dB indicated earlier yields a total possible error magnitude of ± .565 dB. This adds up to a total possible error of ± 14% into a load with 1.1: 1 VSWR. The output power range of our amplifier is now 50W ± 7.05W. Maximum Delta dB Vs, VSWR VSWR Maximum ~dB 1.02 1.04 1.06 LOB 1.10 ,171±.0851 .341±,171 .51 1±.2551 .68 I± .341 .B7 1±.4351 various load impedances. Our example utilizes a real·to·real impedance match for convenience. The analysis also is appropriate for an imaginary·to· real match in that center of the VSWR circle at the input to the matching network will be rotated but won't change in magnitude from the data presented. Now we see how bad things can be. a few com· ments on reality are in order. CONCLUSION The data presented' in table represents the power variation into a load with a VSWR of 1.1: 1 relative to 50Q. The result is a power output of 50W ± 5.3W 1±.435 dBI. The total Delta is 10.3W I.B 7 dBI. This is enough to: AI Make a good circuit look bad. or. 238 The author believes that the correlation target for the test of RF power devices should be ± 0.2 dB. which we believe is the optimum tolerance for combining strict quality standards and the need for easy repeatability under series produc· tion conditions. If more than an occasional device fails this test. do not assume that the devices are at fault. Instead. first analyze the test circuit and then the test system to determine the reason for the additional error. Some suggestions on how to maintain a ± 0.2 dB correlation are shown in Table III. Table III. Notes Suggestions to the Maintenance of Correlation 1. Serialize and documenl all components lallenualors. 5. Be selective when using cables in lesl systems. For example, the MIL·C·ll specification for "RG" cable Iypes says Ihal RG·58 can have a characleristic im· pedance from 4B 10 52Q Imaximu VSWR of 1.04: 11 when lerminaled in a "perfect" 50Q load. directional couplers, power meters, detectors, etc.) of Ihe lesl syslem. Do nol dislurb Ihe syslem once calibration has boon performed. Calibrate the system once a month. 2. Require that loads have a calibration return loss ~-35 dB IVSWR of 1.05:11 in frequency band of 6. Be very seleclive when choosing RF switches. The VSWR of a mechanical switch will vary wilh lime. interest. 7. If possible, lerminale Ihe system wilh a 5DQ load 3. Dedicate test systems to specific circuits or rather than an attenuator. Load manufacturers need products. This is necessary for bOlh correlalion and product continuity. only consider Ihe VSWR of a load. However, for allenualor, tradeoffs must be made belween VSWR and frequencv response. Measure power and other performance parameters via calibrated directional couplers. 4. The placement of transistors in the test fixtures must be uniform. For instance, flanged transistors should be placed in Ihe lest fixtures wilh Ihe device pushed lowards collector load clrcuilry. The 0,2 dB target is an achievable target in broadband test systems. However, a constant awareness of the test system capabilities and potential problem areas is mandatory. RF correia· tion problems will never go away, but they can be made easier to handle. 239 240 AN1033 Match Impedances in Microwave Amplifiers and you're on the way to successful solid-state designs. Here's how to analyze input/output factors and to create a practical design. Prepared by Roger DeBloois The key to successful solid-state microwave power-amplifier design is impedance matching. In any high-frequency power-amplifier design, improper impedance matching will degrade stability and reduce circuit efficiency. At microwave frequencies, this consideration is even more critical, since the transistor's bond-wire inductance and base-to-collector capacitance become significant elements in input output impedance network design. In selecting a suitable transistor, therefore, keep in mind that the input and output impedances are critical along with power output, gain and efficiency. Unless the selected transistor is used at frequencies that are much lower than the maximum operating frequency, the input impedance is largely inductive with a small real part. The large inductance is due to bond wires that connect the transistor chip to the input lead of the package and to the common-element bond wires. The small real part of the input impedance is due to the large geometries required to generate high power at high frequencies; the base bulk resistance may be the predominant. part of the real input impedance. 1. In this output equivalent circuit, cap~citance Con is almost equal to the selected transistor's collector· to·base capacitance Cob' this capacitance as is physically practical and to provide the balance with high-quality chip capacitors. The first section of the impedance matching network is extremely important because it can degrade the stability of the amplifier if it is not well designed. Depending on the design frequency of the amplifier and the transistor selected, the resonated real impedance can range from less than 50 n to much higher. When it is below 50 n, an additional low-pass matching section can be conveniently added to achieve the required 50..n impedance at the input. The higher-impedance case presents a special problem if microstrip techniques are used to build the matching network. The problem occurs because the resonated impedance may be as high as 300 n. Reducing this to 50 n by use of a lowpass network configuration requires a seriestransmission line that will behave as an inductor. The rule of thumb is that the characteristic impedance of the transmission line must be at least twice the higher impedance before such behavior results. Examination of the accompanying table shows that characteristic impedance lines of greater than 100 n are very narrow. Narrow transmission lines (less than 0.01-inch wide) should be avoided wherever possible, because repeatability of width dimensions is poor. Also, the loss in a narrow line may become excessive. A better solution is to use a quarter-wave transmissionline transformer with a characteristic impedance Use microstrip stubs at input network The first and most important step in designing the input matching network for the selected device is to provide a shunt capacitance that will resonate the inductive component of the input impedance. This step forms the low-pass matching section of the network and should provide the smallest possible transformed impedance. To minimize the inductive component, the input and common-element lead lengths must be kept short. The resonating capacitance is generally best provided by a microstrip stub. In some cases the stub producing the required capacitance is so large that a practical circuit size cannot be realized. It is best then to distribute as much of 241 equal to the square root of the 50-!l impedance product: Z. ,,50 ZR~ = Make output bandwidth wider than input The output impedance of a microwave power transistor is usually defined as the conjugate of the load impedance required to achieve the device performance. A typical output equivalent circuit is shown in Fig. 1. The capacitance C",,, is nearly equal to the collector-base capacitance C"h specified for the selected transistor. L, is the inductance of the bond wires used to bridge from the collector metallization area to the package output lead, and L,.,,,,, represents the inductive effects of the common element bond wires. For correct operation of the transistor, the ultimate load impedance must be transformed to a real impedance across the current generator. This real impedance is determin~d by R - [Y", .y,,(sa_t>1~ L- 2P,)ut The load impedance presented to the package terminals will contain the real impedance at the current generator, transformed to a lower value by the low-pass L section formed by C,.,,, and the parasitic inductances L,. and L", .. Usually the reactive part of the load impedance is made inductive to tune out the residual capacitance of the device. The output matching network should be designed so it has greater bandwidth than the input matching network. Providing a good collector match, both above and below the design frequency, ensures that the input. power will be reflected before the collector VSWR rises to values that endanger the transistor. In this way the transistor is protected from off-frequency operation. The amount of additional bandwidth required for protection of the transistor depends on the ruggedness of the transistor used. The manufacturer's specifications for VSWR tolerance and input Q can be a guide for determining the bandwidth requirements of the input matching network. One technique for obtaining the required bandwidth is to resonate a portion of the capacitive reactance of the transistor output impedance with a shunt inductor. The shunt inductor cali also be used to feed the collector supply voltage to the transistor. Additional transformation may he obtained from a low-pass matching section. 2. With this typical microwave amplifier breadboard lay· out, the entire board can be soldered to a metal plate to provide a path for thermal cooling. By adjusting the amount of shunt inductance and rematching with the low-pass section, the designer can create a truly broadband output match. Don't overlook base and collector paths In addition to matching the device impedances, direct-current paths must be provided to the base and collector of the transistor. The collector path is provided by the shorted stub in the impedance-matching network. The base path requires the addition of a choke from the base to ground. The choke can he a lumped element or a distributed shorted stub of sufficient impedance to be negligible in the circuit. A quarter-wavelength stub is ideal. The narrowest practical line should he selected. In addition a dc blocking capacitor is required in the collector circuit. Also needed is a bypass capacitor to provide the proper ac shorting point for the inductive stub in the collector-matching network. Selection of a blocking capacitor is relatively straightforward. The capacitor should be chosen to provide low loss at the operating frequency while maintaining the capacitance at a value that inhibits low-frequency oscillation. The latter is caused by the series capacitor's tendency to display rising reactance with decreasing frequency. Blocking capacitors must be large enough to preserve coupling characteristics down to a fl'equency where the shunt-feed chokes can effec- 242 Microstrip Zo and velocity factor vs width-to-height (W/H) ratio. (Prepared by Don Schulz, Applications Engineer) Teflon Air W/H K = 1.0 Z. Vp z; Alumina Epoxy K = 2.55 Vp zo K = 4.25 Vp z. K - 9.6 Vp 0.362 0.630 168.425 1.000 110.683 0.657 87.986 0.522 60.977 0.695 161.878 1.000 106.258 0.656 84.414 0.521 58.441 0.361 0.766 155.370 1.000 101.865 0.656 80.870 0.521 55.927 0.360 0.844 148.909 1.000 97.509 0.655 77.360 0.520 53.440 0.359 0.931 142.506 1.000 93.199 0.654 73.888 0.518 50.985 0.358 1.026 136.171 1.000 88.941 0.653 70.463 0.517 48.566 0.357 1.131 129.916 1.000 84.745 0.652 67.090 0.516 46.187 0.356 0.354 1.247 123.753 1.000 80.616 0.651 63.775 0.515 43.853 1.375 117.692 1.000 76.565 0.E51 60.524 0.514 41.568 0.353 1.516 111. 746 1.000 72.597 0.650 57.345 0.513 39.337 0.352 1.672 105.926 1.000 68.721 0.649 54.243 0.512 37.164 0.351 1.843 100.242 1.000 64.944 0.648 51.223 0.511 35.053 0.350 2.032 94.706 1.000 61.273 0.647 48.291 0.510 33.007 0.349 2.240 89.327 1.000 57.714 0.646 45.451 0.509 31.030 0.347 2.470 84.115 1.000 54.271 0.645 42.709 0.508 29.123 0.346 2.723 79.076 1.000 50.951 0.644 40.066 0.507 27.289 0.345 3.002 74.218 1.000 47.757 0.643 37.527 0.506 25.531 0.344 3.310 69.546 1.000 44.692 0.643 35.094 0.505 23.849 0.343 3.649 65.065 1.000 41.759 0.642 32.768 0.504 22.244 0.342 4.023 60.779 1.000 38.959 0.641 30.550 0.503 20.716 0.341 4.435 56.689 1.000 36.292 0.640 28.440 0.502 19.266 0.340 4.890 52.796 1.000 33.760 0.639 26.439 0.501 17.892 0.339 5.391 49.100 1.000 31.360 0.639 24.544 0.500 16.594 0.338 5.944 45.600 1.000 29.091 0.638 22.755 0.499 15.370 0.337 6.553 42.291 1.000 26.952 0.637 21.069 0.498 14.218 0.336 7.224 39.173 1.000 24.938 0.637 19.485 0.497 13.138 0.335 7.965 36.233 1.000 23.047 0.636 17.998 0.497 12.125 0.335 8.781 33.484 1.000 21.275 0.635 16.606 0.496 11.179 0.334 9.6111 30.904 1.000 19.618 0.635 15.305 0.495 10.295 0.333 10.674 28.491 1.000 18.071 0.634 14.091 0.495 9.472 0.332 11.768 26.240 1.000 16.629 0.634 12.961 0.494 8.707 0.332 12.974 24.143 1.000 15.288 0.633 11.911 0.493 7.996 0.331 14.304 22.192 1.000 14.043 0.633 10.937 0.493 7.338 0.331 15.770 20.381 1.000 12.888 0.632 10.033 0.492 6.728 0.330 17.387 18.702 17.148 1.000 1.000 11.818 0.632 9.198 0.492 6.164 19.169 10.830 0.632 8.425 0.491 5.644 0.330 0.329 21.133 15.172 1.000 9.917 0.631 7.713 0.491 5.164 0.329 23.300 14.385 1.000 9.074 0.631 7.056 0.490 4.722 0.328 25.688 13.162 1.000 8.299 0.630 6.451 0.490 4.315 0.328 243 Table continued W/H 28.321 31.224 34.424 37.953 41.843 ·46.132 50.860 56.073 61.821 68.157 75.144 82.846 91.337 100.700 - Air 1.0 K Z. V, 1.000 12.036 1.000 10.999 10.047 1.000 9.172 1.000 8.370 1.000 7.634 1.000 6.960 1.000 6.343 1.000 5.779 1.000 5.264 1.000 4.792 1.000 4.362 1.000 3.969 1.000 3.611 1.000 Tetlo .. K - 2.55 Z. V, 7.585 0.630 6.929 0.630 6.326 0.630 0.629 5.773 5.266 0.629 4.801 0.629 4.376 0.629 3.987 0.629 3.632 0.628 0.628 3.307· 3.010 0.628 2.739 0.628 2.492 0.628 2.267 0.628 tively short the respective port to ground. Coupling capacitors should not be excessively large, or they may produce as much as I-dB 10" in gain with a corresponding decrease in efficiency in the case of collector coupling capacitors. The Q of the coupling capacitor determines the acceptable range of capacitance values and is generally inversely related to capacitance. Bypass capacitors are selected by analysis of the same considerations as those for blocking capacitors. A large bypass capacitor (tantalum or electrolytic), placed from the de feedpoint to ground, prevents tendencies toward low-frequency oscillation in the circuit. Also, it may be necessary to add smaller bypass capacitors to preserve stability over a wide range of frequencies. Epoxy K - 4.25 Vp Z. 5.894 0.490 0.489 5.383 0.489 4.914 4.483 0:489 0.489 4.089 0.488 3.727 3.397 0.488 0.488 3.094 0.488 2.818 0.487 2.566 0.487 2.335 0.487 2.125 0.487 1.933 0.487 1.758 Alumina K - 9.6 Z. V, 3.942 0.327 3.598 0.327 3.284 0.327 2.995 0.327 0.326 2.731 2.489 0.326 2.267 0.326 0.326 2.065 0.325 1.880 1.711 0.325 1.557 0.325 1.417 0.325 0.325 1.289 1.172 0.324 When plastic materials are used, it's a good practice to measure the material thickness and dielectric constant, because variations are common. In a recent test the dielectric constant of a sheet of epoxy fiberglass material was measured at 4.55 at 1 MHz and 4.25 at 500 MHz. If the manufacturer's value of 5.5 had been used for the design of matching- networks, considerable error would have rewlted. The physical dimensions of the matching circuitry may be calculated from the data in the table. The line lengths are scaled by the velocity factor, which is equal to Z. Z. in air for a constant width-to-height ratio, W H. The final design of a typical breadboard microwave amplifier is shown in Fig. 2. The ground areas on the top of the board are connected to the microstrip ground plane by 2-mil-thick foil wrapped around the edges of the board and the areas directly under the emitter lead~ of the transistor. The foil is secured to the top and bottom surfaces with solder. Plating: may be u,ed for production units. The entire board can bt' soldered to a metal plate to allow connedor mounting and to provide a thermal path for the heat generated by the tran,istor. Adjust for bandwidth and physical dimensions The circuit design may be adjusted quickly for bandwidth requirements through use of a computer optimization program such as Magic, offered by University Computing of Dallas, Tex. When that step is finished, electrical dimensions mllst be converipd to physical dimensions. At this point in the design sequence, the dielectric material must be chosen. Three commonI~' used mate.rials are Teflon fiberglass, epoxy fiberglass and alumina. Above 500 MHz, epoxy fiberglass exhibits too many losses to be a good choic.e. Teflon fiberglass ('an be used up to several gig-ahprtz: it has reasonable dielectric losses and is eas~' to pro(·ess. Alumina, a ceramic, offel-s a high rlielpetric constant, good dimensional consistency and small circuit geometry. The initial tune-up of the amplifier matching circuits can be t'xpedited by ll,e of a network analyzer and a precision load on the input or output connector. The circuit can be adj usted to match the nominal impedances "llpplied by the transistor manufacturer. Distributed stubs are purposely made longer than ne('essary and are adjusted to the correct length by trimming of the 244 with appropriate values indicated for the sample design is shown in Fig. 3. The input match is achieved when the input impedance is resonated with a capacitive susceptance of 0.18 mhos. This susceptance is realized by use of a pair of capacitive microstrip stubs. Each stub must exhibit a reactance of 2 x 1 '0.18 mhos. or 11.1 n. The length of the stub may be calculated by foil 011 the capacitive stubs. The inductive stub in the output network iR adjusted by positioning of the bypas~ capacitor along the stub and the adjacent ground plane. This procedure result.. in a load line that is fairly close to optimum. A transistor can now be inserted in the circuit and the collector matching network readj usted for maximum collector efficiency. Stub tuners are used to match the amplifier input impedance. so that only one variable at a time need be considered. Initially it may be necessary to operate the transistor at reduced collector \'oltage and power output to avoid ~xcessive stress. When maximum efficiency is obtained, the stub tuner is removed and the input network adjusted for minimum input VSWR. tan 0 For ease of adjustment, the length of the stubs should be less than 60 degrees. Because capacitive reactance is a tangential function. the reactive variations per unit length become increasingly severe past 60 degrees. It is better to decrease Z, rather than to use longer stubs to achieve higher capacitance. Therefore Z, ~ 1.732 X,. ~ 19.24 fl. Because it is easier to shorten a microstrip stub than to lengthen it. the Z, of 15 fl, for example, provides sufficient adjustment r~nge to accommodate device variations. The next step is to transform the resonated impedance to 50 fl. This is accomplished by a series-transmission line with a characteristic impedance of 50 fl. From Fig. 3. we see that the length of this line can be directly determined to be 0.062 wavelengths. or 22.3 degrees, long. A capacitive susceptance of 0.040 mhos completes the transformation. Again, a pair of capacitive stu bs will provide the susceptance. For ease of converting the design to microstrip dimensions, it is convenient to choose a Z" for the second stub that is equal to that selected for the first. Therefore: Now let's design an impedance-matching circuit Let's consider a practical example of a procedure for the design of impedance-matching circuitry. The sample circuit uses a TRW 2N5596 at 700 MHz as the active device. Specifications for the completed amplifier are: Z" Z,.", P,,,, Gp 7) . 50 fl. 50 fl. 20 'A'. 7 dB. 55""( minimum. Specifications for the TRW 2N5596 are: Po" 7) Gp Z" Z,,", = X, ~•. 20 W at 1 GHz, 55 c , minimum at 1 GHz. 5 dB minimum at 1 GHz. 2.5 + J4.0 at 700 MHz. 6.0 - J12.5 at 700 MHz. tan 0 In practice. the gain of a common-emitter amplifier decreases at a rate of 4 to 5 dB per octave. The 2N5596 at 700 MHz produces about 7 dB of gain. Therefore approximately 4 W of drive will be required to produce 20 W of output power. The collector efficiency can be expected to increase at the lower frequency. but it is difficult to estimate because it i~ a complex phenomenon. Manufacturers' curves of typical behavior are useful. Output power will not increase significantly with the decreased frequency. The efficiency-frequency relationship depends on device fT and ballasting. Heavily ballasted transistors tend to give increaspd efficiency as frequency is decreased. However, they level out at a lower efficiency than a non ballasted part because of I'R losses in ballast resistors. The average increase in efficiency as a result of de·· creasing frequency is about 20 I;. per octave. Values from 10 to 407< per octave have been measured. The initial phase of the design is best accomplished on an immittance chart. The chart Z" = 50 15 = 03 = x, ., or 0 = 16.7 degrees. In this case the length chosen is 20 degrees to allow for some adjustment. The output match is achieved by partial resonating of the device's output impedance with an inductive susceptance. While the amount of susceptance chosen is arbitrary at this point. the output network bandwidth is affected by the value. From Fig. 3. we can determine that 0.05 mhos is required for the first matching element. This susceptance is achieved by use of a shorted microstrip stub. The length of the stub may be calculated from the equation X, tan () co, Z,," If Z" of the stub is arbitrarily chosen to be 50 fl. 20 tan () = . 50 = 0.4, () = 21.8 degrees. Again. the stub is made somewhat longer because it can he adjusted by sliding the chip 245 capacitor (ac short) up or down the line length. The remaining transformation is achieved by a 50-11 series-transmission line of 0.15 wavelengths (54 degrees long) and a capacitive susceptance of 0.014 mhos. Selecting a pair of 50-ohm microstrip lines to provide the susceptance requires a stub length of X,. tan =2 x Z =-x': O~ti4 = 143 n. 50 = 143 = 0.350 = 19.3 degrees. A stub length of 25 degrees will provide an adequate allowance for adj ustment of the circuit. •• 3. The immittance chart, with values specified for the design example, indicates tne necessary inductive and 246 capacitive stubs. Impedance transformations are achiev· ed by 50·n series·transmission lines. AN1034 Three Balun Designs For Push-Pull Amplifiers S INGLE RF power transistors seldom satisfy today's design criteria; several devices in separate packal/:es! or in the same packal/:e (balanced, push-pull or dual transistors), must be coupled to obtain the required amplifier output power. Since highpower transistors have very low impedance, designers are challenged to match combined devices to a load. They often choose the push-pull technique because it allows the input and output impedances of transistors to be connected in series for RF operation. Balun-transformers provide the key to push-pull design, but they have not been as conspicuous in microwave circuits as at lower frequencies. Ferrite baluns' have been applied up to 30 MHz; others incorporating coaxial transmission lines operate in the 30-to-400-MHz range.' INPUT Til .. ,,· '::N~~':~ SllrOIlS OUH'UT '::N;~':: The success of these two balun types should prompt the microwave designer to ask if balun-transformers can be included in circuits for frequencies above 400 MHz. Theory and experimental results lead to the emphatic answer: yes! Not only will baluns function at microwave frequencies, but a special balun can be designed in microstrip form that avoids the inherent connection problems of coax. On the next six pages, you will observe the development of three balun-transformers-culminating with the microstrip version. None of the baluns was tuned nor were the parasitic elements compensated. In this way, the deviation of the experimental baluns from their theoretical performance could be evaluated more easily. The frequency limitations imposed by the parasitic elements also were observed more clearly. 1. A balun transforms a balanced system that Is symmetrical (with respect to ground) to an unbalanced system with one side grounded. Without balun-transformers, the minimum device impedance Ireal) that can be matched to 50 ohms with acceptable hand width and loss is approximately 0.5 ohms. The key to increasing the transistors' ~I output power is reducing this impedance ratio. Although 3-dB hybrid com hiners can double the maximum power output, they lower the matching ratio to only 50:1. Balun transfnrmers can reduce the original 100:1 ratio to 6.25:1 or less. The design offers other advantages: the baluns and associated matching circuits have greater bandwidth, lower losses, and reduced even-harmonic levels . OUTPUT .... lU ... ..... LANel UN .... l ... NCEI .,.,.ut fLOWVIWAI 2. Baluns are not free of disadvantages. Coupling a pair of push-pull amplifiers with 3-dB hybrids avoids (for four-transistor circuits) one of these: the higher broadband VSWRs of hal un-transformers. A second disadvantage, the lack of isolation between the two transistors in each ·;t";~(;:;rVi~fM~,&~~~.ampllpush-pull configuration, is outweighed by the advantages of the balun design in reducing the critical impedance ratio. 247 3. In this simple balun that uses a coaxial transmission line, the grounded outer conductor makes an unbalanced termination. and the floating end makes a balanced termination. Charge conservation requires that the currents on the center and the outer conductors maintain equal magnitudes and a ISO-degree phase relationship at any point along the line. By properly choosing the length and charac· teristic impedance, this balun can be designed to match de· vices to their loads. In the case shown, if 0A = 90 degrees, the matching condition is: l',,"A'. A Ulllfl I • • 1,""'.1'. fA,. B.n"I/P4>~1I ZA' = 2xRx50. 4 4. By adding a second coaxial line, the basic balun can be made perfectly symmetrical. In this symmetrical coaxial balun, the bandwidth (in terms of the input VSWR) is limited by the transformation ratio, 50/2R. and the leakages, which are represented by lines Band C. If ZA = 50 ohms and R = 25 ohms, the bar.dwidth is constrained only by the leakages. LINE A Z ..... 'A L1NEa.LINEC Z._IC_"._"C 5. The equivalent circuit lor the symmetrical balun shows the effect of the leakages (lines B and C) on its performance. A broadband balun can be obtained by using a relatively high characteristic impedance for these leakage lines. In theory, the construction of the baluns insures perfect balance. tR SYMMI'''leAl I"'UIN lOUIVALE"" 6. The symmetric balun's Input equivalent circuit further simplifies its configuration and allows the input VSWR to be calculated.' In this design, line A has a characteristic impedance of ZA =50 ohms, a length of LA = 1799 mils, and a dielectric constant (relative) of .,=2.10. For lines Band C, Z, = 30 ohms, 171799 mils, and '.rr = 2.23. -----=fl CUlcun LU I L=1799 , - - - - - - - - - - - - I "~::::5 LlNE ... ,t, Z" ... -lA' r l ... _IO LINE • • II L _2!! ......."" 1 •• _21" '•• =". I \""""-211_2 I / -~ rl------------------- ./ I ! FREQUENCY at.. THIOIUTICAL INPUT RESPONSI OF THE SVMMITllle BALUN tDESIGN 11 7. The theoretical Input VSWR has been calculated for 50-ohm values of ZA and 2R, and for two other sets of values for these parameters. The performance of an experimental balun will be compared with these theoretical results. \_--y-----" '--v-" IALUN COAlIIlAl Z!ir\UNIS MICIlOSTIII' ~ 'I LllilIE·SICT,OIl: CHEavSHIV IMPlDANCE LINEA Z .. _liO' .. L ... _11 •• MIL ...... 210 LlNII lINEC Z.=ZC-lO".L.=LC_11 •• MlL •..•"=ZZl LINEO LlNEO' ZO_za, .. LO_1S0 MIL •. · . . . . ZZl UNE f UNEE' ZI _.1 a".L E _ 4.4 .. ILI . •"_ 210 8. Two M16 line-section Chebyshev Impedance tr.anslormers match the experimental balun to a 50-ohm measurement system. The balun was tested from 0.6 to 1.5 GHz. LINE ~ 248 LINE F' Z,=20 3".L,=44' MIL •..• '-v-' LOAQ T:'~~:~~~~~" MICIIOSTIU,. "= 2 31 IXPIIIIMINTA .. COAXtAL I,sLUN IDE.IGN It WITH OUTPUT 1111,s"'.'OIllIlllII. 9. The measured phase difference and Insertion loss difference, which indicate the maximum unbalance for !:E : :~ =:4 the Design 1 experimental balun, are 3 degrees and 0.2 dB, respectively. ::c:: :=~ 01 07 G, 0' 10 II 12 11 ,. 10. The maximum VSWR mealured 'or the 'Irst dellgn II 1.5:1. Note the comparison between the calculated and measured response. The performance shown can be considered valid for amplifier applications up to an octave range. " '".QUINCY - GHI .. -----------'---,~""" .... :.:::::::....-~ 11. The second balun design adds two Identical coax lines to the simple balun just described. The I I '---'--v----' '--v------' FlIIST SICTlON I SICOfolO SICTlON I'~'·-·-··-·-·-"-··-'-'·-·-··-"-A-'--'-';-:.-:.-':-~.-~_::_:_:_:_:_:_:_'___" __"'_"_._"_"_'_'._'_"~"~AJ r :-[-. ®I I : inputs of the identical lines are connected in series to the output of the first balun. By putting their outputs in parallel, the final output becomes symmetrical. The output impedance is halved. 12. The equivalent circuit lor the Design 2 balun indicates that its bandwidth, in terms of input VSWR, is limited by the transformation ratios of the first and second sections and the leakages represented by lines B, C, E, and G. If the balun is designed with ZA = 50 ohms, and Zu = ZF = 25 ohms, and if the load, 2R, is set at 2x 6.25 ohms, all of the transmission lines will be connected to their characteristic impedances. In this case, the bandwidth will be limited by the leakage alone, and a broadband balun can be obtained by choosing lines B, C, E, and G with relatively high impedance and A/4 length for the center frequency. The balun achieves a transformation from 50 ohms to twice 6.25 ohms without causing a standing wave in the coaxial cables. /" '13 , '-../ 0' 13. The performance the Design 2 balun can be calculated using Its equivalent circuit. The calculated VSWR shows a response very close to the simple coaxial balun (Fig. 10) because the new second section has four times the bandwidth of the first section. This design and its two companions are intended to have octave bandwidths centered at 1.1 GHz, the central frequency used in distance measuring equipment (DME, 1.025 to 1.150 GHz) and tactical air navigation (TACAN, 0.960 to 1.215 GHz). For line A:ZA = 50 ohms, LA = 1799 mils, " = 2.10; lines B, C, E, and G: Z. = 30 ohms, L = 1799 mils, "ff = 2.23; lines E and F: Zo = 25 ohms, L = 1799 mils", = 2.10. 249 TI~'f)'Rri'("t1On ooluJI often used in the JI)()-ffl-I,rXJ MHz rangf'. '4 14. Two A/4 transformers match the experImental twosectIon coaxIal balun's 6.26ohm impedance to the 50-ohm load. Although these transformers drastically reduce the bandwidth (in terms of the VSWR), they don't affect the balance. SICONO /4 SfCTION fIllANa"oRMUI MICRO.TR'" LINEA ZIII::" 15. The measured phase dIfference and measured InsertIon loss dIfference are plotted for the two-sectIon coaxIal balun (Design 2). The maximum unbalances for these two measurementsoverthe octave bandwidth are 1 de~ree and 0.2 dB. 16. The calculated and measured values for the Input VSWR for the DesIgn 2 balun show close agreement between the experimental and predicted performances. This indicates that the parasitic inductors at the connections are negligible to at least 1.4 GHz. Moreover, the balun has excellent balance to 1.4 GHz and achieves the 4:1 transformation without causing a standing wave in the coaxial line. Despite the many excellent qualities of thE Design 1 and LA _ HI. MILS, ,ZI Zc-. UNE .. : LINE C Z. - LINED LINE' lO:: l , - 2!i1 .. LO- L,'. 179!1MILS." LINE' ~ ~ -. ZI . 2,- Zr;" 17 "r,L,: If': 1712 MILS. 'e"': 2)0 ' 'r IS . 'F·=----~=======11 --I "F : : I '" =. LINE' , - - - I- - - - '_ _- - - ' - - - - - - - - - ' - _ " - - - - " - - - - - - - ' - - - - - - ' _ ~ ,', , _ them to approximately 2 GHz. lOl,.lll-. LC":119SMILS"_H-ZZ:J LINE ELINE G ZE -. Z(l":' 30 '. LE ::.. LO -;. 1719 MilS. 'eM' 223 LINEH LINEH' ZH"',:ZH': ZitoLr,L H ;-; LH'=.IOMILS"_H-' 223 D~mits _eS_i_g_n_2_ba_l_u_n_s_,_th_e_n_ec_e_s_s_a_r,_'_c_oa_X_i_a_l_li_n_e_c_o_n_n_e_ct_i_on_. !: =~ ._=.".'~:'O ,, so:, . . . _ . , ./ ,, --'J . ,; i . . ~: : : ,-". :~ -.-~:J --------------;="" I~ 17. The problems associated wIth the previous coaxial baluns can be reduced or eliminated by using a balun that allows a microstrip coplanar arrangement of the input and output lines, which greatly simplifies the connections to the amplifier. This balun'consists of an input line, A, connected in series to three elements in the center of the halfwavelength cavity: a reactive open-circuit stub, B, and the Al4 output lines, C and D. ~.~ t .." d77 1 B. The equivalent circuit of the Design 3 coaxial version balun shows lines C and D connected to place their input signals in antiphase, thereby producing two antiphase signals at their outputs. Transmission line impedances and lengths are optimized to achieve the correct input/output transformation ratio and a good match across the desired bandwidth. If only one frequency or a narrow bandwidth is desired, and all lengths are A/4, the matching condition Z.'/50 = 2Z;/R, will occur. In this case, ZE (Z.=Z.) and Z. have no significance except for loss. rt ,;«':'f ~J. It/ ".00 / lel801 iJ· h '''' 250 0' 19. The coplanar arrangement Input and output lines can be accomplished with mlcrostrlp technol· ogy. The uppermost conductor plane contains input line A, output lines C and D, and the open stub B. Coupling between these lines is avoided by separating r"'" I L" ... p -1 ~----'/_-"-.'''-~ I " u ........ ili A -50 .\. ... _ ' ••• MIL'"eH_l10 LINI •• Z._ts- .L._1110MIL.".,,_2lJ LlNICC 2Z,_lSl, .. lr_nUMIL".H:2lJ LINIDD 22.,_500 •. lD_IS •• MIL. _,,_22l II~ 2X 11.50' '''PUT IQUIVALlNT CII.CUIT IDI15'Gfil 3 a.nu,. ) them by at least one line width. The middle conductor carries the ground plane for the lines. To avoid radiation loss, the center conductor must extend at least one line width to either side of the upper plane circuit line. The balun resonant cavity is formed by the region between the f,;'\ middle and the lower con\..:.:) ductor planes. A hole for the cavity is cut in the circuit fixture, filled with dielectric, and covered with the middle conductor plane. The end-to-end length of the cavity is nominally a half.wavelength at midband. To avoid disturbance of the field distribution, the cavity width must be at least three times the width of the middle conductor plane. The arms of the balun cavity are folded to produce two parallel and proximate output transmission lines. This configuration is more suited to coupling two t transistors than the oriL D,~t~;~~,c ginal layout in which the two outputs were on op· posite sides (Fig. 17). 20. The Input equivalent circuit 'or the mlcroBtrlp version the DeBlgn 3 balun allows its theoretical performance to be calculated. The design parameters shown provide a micros trip circuit that can be compared with the coaxial baluns of Design 1 and Design 2. Transmission line A and lines C and D are loaded by their characteristic impedances-in this case, 50 and 25 ohms. The cavity and the stub impose the principal frequency limitation. The impedances of these elements are dictated by the properties of the available dielectric substrates (glass-Teflon 0.020 and 0.0625 inches thick). 0' References 1. "35/50 Watt Broadband fl60-240 MHzl Push·Pull TV Amplifier Band III," 'l'RW Application Note. TRW RF Semiconductor! Calal !WAN 2. "150 W 28 MHz. 13.5 Note. TRW a.9,faJl; l~~~Cation N Catalog Note. on the TPM·4100 (100 W, 100 - 400 MHz); the t~~:= ftfo WW.l~d·~I~~~~ :~: TPV-5050 (SO W, UHF), available from TRW RF Semiconductors. . 4. The S. Gordon J. tbe circuit CT (ComMierowave ). L.u~hlin, fIllIQUINC., - aHI l THIOlillTlCAL IN"UT VSWIII OF MICRO'TIII" .ALUN IDISION 31 ~-----------------------.----~ "New ~~rJ:~-~:hec;E~ ~r::!lU!~,]!~ 21. The Input VSWR can be calculated based on the equivalent circuit 'or the mlcrostrlp balun. For a one-octave bandwidth, the input VSWR is lower than 1.75:1. This calculated performance is similar to that of the two previous balun designs. The design of the microstrip has theoretically perfect balance. ~~N[n~~hTf~6i.logy. Vol. 251 --~-----------------THREEBALUNSFORPUSH-PULLAMPS--------------------- 22. The equivalent circuit of the mlcro.trlp balun shows it during performance measurements with >./16 matching lines. The experimental model uses 18-mil glass-Teflon (" = 2.55) for the tap circuits and 62.5 mil glass-Teflon for the cavity. Balance properties were measured with a 50-ohm system, which was transformed to 25 ohms by the M16 linesection Chebyshev impedance transformers, which have a bandwidth r,:; rhru=~!,'"~~d::::~r~~:/h(Ju'. from 0.960 to 1.215 GHz. LINE A Z.. ~\I. LA .I 10 " " MilS..... LINEa Z. ZlIll,la I.,DMILI ..... 223 LINEr.LlNlf .IE .IF 17"1,1.. IF 1712MIL5.,_" LlNEC,LlNID .Ie LINI G, LINE" lG 20 2H LINE •• LINE J 2, zJ lINIK,lIN[l a" ZL Z5',L C 25". La A' III. 1:, ZO!lul" LO LH '."MllS.,.., '''<1 MltS.. .,. .I 33 223 :I 23 lJ . . . MILS'.n .I 07 Ll, •• :lMltS. eft 23' 23. The unbalance between output ports for a oneoctave bandwidth is shown in the measured 1.5degree maximum phase difference and 0.15-dB maximum insertion loss difference. 24. The central frequency Is 10 percent higher than expected, but response is ciose to the calculated values if relative frequency is considered. Ifthe output transformers and their effect on input VSWR are disregarded, an octave bandwidth with a maximum input VSWR of around 2.0:1 can be ohtained. The 100MHz shift between the two curves may be caused by the improper determination of the folded cavity's electrical length. Similar calculation inaccuracies m'ay arise from effects at the balun junction and from the electrical length of the stub. As in the calculated response, the experimental microstrip balun performs comparably to the two coaxial designs. 25. The similarity In the performance of the three balun designs within the considered frequency bands indicates that the parasitic elements do not significantly affect the theoretical properties. The frequency limit is higher than 1.5 GHz for all three. In the O.960-to-1.215-GHz bandwidth (TACAN and DME applications), each performed with satisfactory balance. The table compares the main characteristics of the balun designs. The phase differences (± 1.5 degrees) for all three baluns are similar to those experienced with the miniature 3-dB hybrid couplers that are normally used to combine transistors for microwave balanced amplifiers. But the insertion loss differences of the baluns are better-0.2 dB for a one-octave bandwidth compared with 0.5 dB. The physically simple microstrip balun eliminates the connection problem inherent in coaxial designs: physical variances that breed standing waves and unbalance. Microstripping the transmission lines allows a designer to choose any value of characteristic impedance of the lines. Consequently, the'microstrip balun is both more manageable and more controllable. Since the balun load impedance will vary with frequency, the best results will be obtained by simultaneously optimizing the balun parameters with those of the matching network. The transistor's internal prematching network must be considered.·· ,::~ r'U.(~ ~j ~~ ~ ~ \I~( - - - - - - - - - - - - - - - : = Performance of the Three Balun Designs Type of balun Balun Maximum experlloads, R mental unbalance (ohms) for one-octave bandwidth ~ U 70 I GAIN <::J ~ 80~ i!i co 60~ u t-- 110 f. FREQUENCY (MHz) Figure 4. Gain and Efficiency versus Frequency 50~ 8 # 256 AN1039 470-860 MHz Broadband Amplifier 5W 5 W UHF TV TRANSPOSER AMPLIFIER WITH TWO TPV 593 TRANSISTORS INTRODUCTION This application note describes an ultralinear broadband (470-860 MHz) amplifier, developed for TV transposer applications. The amplifier incorporates two TPV 593 transistors. Each transistor is used to build a separate broadband amplifier. The two identical amplifiers are later combined with 3 dB hybrids. The TPV 593 transistor has been developed for TV class A application. It incorporates gold metallization and diffused ballast resistors for ruggedness and linearity. Its DC current consumption is very low and makes it a good candidate for solar cell powered systems. Its basic specifications are: Vee ; 25 V G ; 9 dB at 860 MHz Ie ; 450 mA IMD ; -- 60 dB at 860 MHz and 2 W output The S parameters of the TPV 593 are given in the table below. POLAR S-PARAMETERS IN 50.0 OHM SYSTEM FREO. 470.00 650.00 860.00 Sll (MAGN ANGL) 0.93 0.93 0.92 170 165 162 S21 (MAGN ANGL) 1.50 63.0 1.06 50.0 0.79 38.0 S12 (MAGN ANGL) 0.040 0.050 0.056 257 50.0 54.0 54.0 S22 (MAGN ANGL) 0.55 0.60 0.65 -166 -169 -169 S21 dB - 3.52 0.51 2.00 K FACT 1.01 1.04 1.15 POLAR COORDINATES OF SIMULTANEOUS CONJUGATE MATCH F LOAD REFL. COEFF. MAGN. ANGLE SOURCE REFL. COEFF. MAGN. ANGLE MHz 470.0 650.0 860.0 0.99 0.97 0.95 0.91 0.83 0.79 -173 -16B - 165 Gmax dB 124 134 146 15.23 12.01 9.16 DESIGN CONSIDERATIONS Two identical single transistor class A amplifiers will be combined with 3 dB couplers. First the design of a single amplifier will be considered. From the analysis of the variation of the TPV 593 S21 parameter with the frequency it may be seen that there is a difference of 5.52 dB between 470 and 860 MHz. If a flat gain is required this gain slope has to be compensated. The compensation can be implemented in two ways: a) By placing a selective attenuator at the input of the transistor amplifier, with an insertion loss minimum at 860 MHz and which increases to 5.52 dB at 470 MHz. The insertion loss increase should compensate the transistor gain slope. b) By selective mismatch at the input of the transistor. The input circuit will provide impedance matching at 860 MHz, in order to get a gain as close as possible to the GA max. Frequency dependent mismatch will compensate the gain slope. At 470 MHz a VSWR as high as 11:1 will be necessary. It has been proved that impedance mismatch at the base terminal of a transistor power amplifier does not modify the linearity behavior of the device. As it was decided to combine two amplifiers with 3 dB couplers the method b) was selected. 50 ohms 3 dB hybrid couplers when used with two identical loads provide a good VSWR at the common terminal even if the loads differ from 50 ohms. The reflected energy is dissipated as the 50 ohms load connected to the fourth terminal of the coupler. The coupler behaves as a selective attenuator. Figure 1 shows the amplifier arrangement. The use of a 3 dB coupler to split the input signal makes almost compulsory the use of the same type of circuit at the output. IN SAGE WIRELINE 3dB Hybrid 1=70mm I I II I I II II x ( I It I I I I OUT Figure 1. Block Diagram of Amplifier The amplifier must be as. linear as possible over the complete UHF band. A transistor power amplifier usually requires impedance matching at the collector side for optimum intermodulation. Therefore the output circuitry has been designed for impedance matching all over the bands IV and V. 258 COMPONENTS PART LIST L, L, 65 line 50 line 50 line 7 turns L, 10 mr; : 5 mm wire C,-C, C, C,-C, C.-C, Variable Airtronic AT 7275 .. 8-4.5 pF 6.8 pF ATC 100A 10 pF ATC 100A 1 nF + 10 nF + 1/l + 10 /IF L, L, - 11 % g at 860 MHz 1.5 % gat 860 MHz 17 % g at 860 MHz ID 2 mm - Closely Wound - wire 5 mm 1 mm Board Material: 1/16" Teflon Fiberglass CIRCUIT DESCRIPTION The circuit of a simple amplifier is given in Figure 2. r-----~----_.------~-------- L3 fN VeE lOUT lnF Figure 2. Circuit Schematic 4,4Il 2 IV V suppl y c The input circuit consist of a three section low pass type matching network. To minimize power losses all the impedance transformations are made at a low Q level. Variable capacitor C1 is adjusted for optimum VSWR at 860 MHz. The tuning is straight forward and only a small retouch is necessary after the collector tuning. The very constant S22 of the TPV 593 transistor makes extremely simple to match the collector to a 50 ohms load. L8 tunes the output capacitance of the device and is determined for good matching at the low end of the band. Only one low pass section is necessary. Capacitor C5. variable. allows a good shaping of the output VSWR. Collector tuning should be done after tuning the input. 680 Il 4,7 K 2m The bias control circuitry is classical and is given in Figure 3. Figure 3. Class A Bias Circuit 259 CONSTRUCTIONAL DETAILS The printed circuit board lay-out of the complete amplifier is given in Figure 4. Considerate attention should be paid to the ground returns. Plated through holes have been used to ensure low emitter inductance. Wrapped foils ensure proper grounding of parallel capacitors and connectors. The couplers have been made with parallel wire cable. This solution is as inexpensive as a straight forward. 9 ~ r- t ;ei = ;z "i·.J~ ~ ._-/' f-! 4 W - - - - r - - - - - - - "---~ , . - - - - ::> ~ o S 0': Z I 12 t-jTr-- ~. _.. 18 I z I .... I I--~- = 470 MHz ~ 14 15 o -+- I-- ~ 10 -r- ~ u -~ '" z ::> 6 o i '"oZ 2 in --- 1 o t -t- 1--1-2 ~ ~ "7 V ~ 1 rf+- - --- t-- -- -- --_. :> Pin. INPUT POWER [WI Pout. VISION (WI f = 650 MHz it.. 18 ~ ffi ~ ~ 8 o'" 14 ::> "" I--~+-----,.-c-­ ::> ~ o 10 >- o z 121--+-+-+ ~ 1--'- V u ~ J ::> - r-+-----t - - x: . -Tl/r 10 I-- ~ 4 I---r--¥-- ~~-t I I L J.t_ 6 55 z ~ : I ~t} -tl- I I o in :> Pin. INPUT POWER IWI Pout. VISION (WI f = 860 MHz ! ~ 12 10 ~ ! I IJ I I I 1 ! 8 I 4 v· >::> ::> I o l/ .' .... ~...... J.-t- ~ ~ ---+-----r-- i I J I I I lL I I ~-~~r-~~~ ~ t--I-- --+--~lr, -+-t----t--t-~ 10 t--I--t---r- J 5 ./ - ----jf----t--r--t--r- t-~ 6 """"'~--+--J-rl-+-I -+--+J-_+---It- t--t-- ! ------t-~ I 18 t-14 I ! Il-+--j tt ---+--; 55 is '" 2 iii II :> Pout. VISION [WI Pin. INPUT POWER IWI NOTE: .1% of sound carrier (-7 dB) when vision carrier is switch ON/OFF 261 MEASUREMENTS The measurements results have been summarized in Table 2. Figure 5 shows the frequency response of the amplifier as well as the input and output match. Figure 6 displays the linearity (lMD test; -8, -16, -7 dB) of the amplifier. Static transfer curves are given in the Figures 7 and 8 that show also the vision to sound cross modulation of the amplifier. Table 2 TYPICAL RESULTS BANDWIDTH : 470 GAIN :87dBmln IMDOat 4W - 5 W 860 MHz - 58 dB 56 dB REF VISION REF 8 dB SIDEBAND REF - 16 dB 16 dB INPUT RETURN LOSS 17 dB OUTPUT RETURN LOSS: BIAS CONDITIONS - 7 dB IMD : SOUND 25 V 2 • 450 mA CONCLUSION A high performance amplifier has been described as an example of the possibilities offered to the designer by the TPV 593. In particular the amplifier combines excellent frequency response and linearity with high efficient use of the DC power. This circuit may be of interest for output stages of low power TV transposers or drivers of higher power units. 262 AN1040 Mounting Considerations for Power Semiconductors Prepared by Bill Roehr Staff Consultant, Motorola Semiconductor Sector TABLE OF CONTENTS Introduction . . . . . . . . . . . . . . . . . . . . . . 1 2 Mounting Surface Preparation . . . . . . . . . . . . Interface Decisions . . . . . . . . . . . . . . . . . . . . . . . . 3 Insulation Considerations . . . . . . . . . . . . . . . . . . . 4 7 Fastener and Hardware Characteristics .. Fastening Techniques . . . . . . . . . . . . . . 8 13 Free Air and Socket Mounting ....... . INTRODUCTION Current and power ratings of semiconductors are inseparably linked to their thermal environment. Except for lead-mounted parts used at low currents, a heat exchanger is required to prevent the junction temperature from exceeding its rated limit, thereby running the risk of a high failure rate. Furthermore, the semiconductor industry's field history indicated that the failure rate of most silicon semiconductors decreases approximately by onehalf for a decrease in junction temperature from 160'C to 135'C.(1) Guidelines for designers of military power supplies impose a 110'C limit upon junction temperature.!2) Proper mounting minimizes the temperature gradient between the semiconductor case and the heat exchanger. Most early life field failures of power semiconductors can be traced to faulty mounting procedures. With metal packaged devices, faulty mounting generally causes unnecessarily high junction temperature, resulting in reduced component lifetime, although mechanical damage has occurred on occasion from improperly mounting to a warped surface. With the widespread use of various plastic-packaged semiconductors, the prospect of mechanical damage is very Significant. Mechanical damage can impair the case moisture resistance or crack the semiconductor die. Connecting and Handling Terminals Cleaning Circuit Boards. . . . . . . . . . . . . . Thermal System Evaluation. . . . . . . . . . . Appendix A Thermal Resistance Concepts. Appendix B Measurement of Interface. . . . Appendix C Sources of Accessories. . . . . . Package Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . .. Figure 1 shows an example of doing nearly everything wrong. A tab mount TO-220 package is shown being used as a replacement for a TO-213AA (TO-66) part which was socket mounted. To use the socket, the leads are bentan operation which, if not properly done, can crack the package, break the internal bonding wires, or crack the die. The package is fastened with a sheet-metal screw through a 1/4" hole containing a fiber-insulating sleeve. The force used to tighten the screw tends to pull the package into the hole, possibly causing enough distortion to crack the die. In addition the contact area is small because of the area consumed by the large hole and the bowing of the package; the result is a much higher junction temperature than expected. If a rough heatsink surfa.ce and/or burrs around the hole were displayed in the illustration, most but not all poor mounting practices would be covered. PLASTIC BOOY (1) MIL·HANDBOOK - 2178. SECTION 2.2. (2) "Navy Power Supply Reliability - Design and Manufacturing Guidelines" NAVMAT P4855-1, Dec. 1982 NAVPUBFORCEN, 5801 Tabor Ave., Philadelphia, PA 19120. Cho- Therm is a registered trademark of Chromerics. Inc. Grafoil is a registered trademark of Union Carbide Figure 1. Extreme Case of Improperly Mounting Kapton is a registered trademark of E,!' Dupont Rubber-Due is a trademark of AAVID Engineering A Semiconductor (Distortion Exaggerated) Sil Pad is a trademark of Berquist Sync-Nut is a trademark of 1M Shakeproof Thermasil is a registered trademark and Thermafilm is a trademark of Thermalloy, Inc. ICePAK, Full Pak, POWERTAP and Thermopad are trademarks of Motorola, Inc. 263 14 16 16 17 18 19 20 In many situations the case of the semiconductor must be electrically isolated from its mounting surface. The isolation material is, to some extent, a thermal isolator as well, which raises junction operating temperatures. In addition, the possibility of arc-over problems is introduced if high voltages are present. Various regulating agencies also impose creepage distance specifications which further complicates design. Electrical isolation thus places additional demands upon the mounting procedure. Proper mounting procedures usually necessitate orderly attention to the following: 1. Preparing the mounting surface 2. Applying a thermal grease (if required) 3. Installing the insulator (if electrical isolation is desired) 4. Fastening the assembly 5. Connecting the terminals to the circuit TIR = TOTAL INDICATOR READING DEVICE MOUNTING AREA Figure 2. Surface Flatness Measurement tance. Tests conducted by Thermalloy using a copper TO-204 (TO-3) package with a typical 32-microinch finish, showed that heatsink finishes between 16 and 64 win caused less than ± 2.5% difference in interface thermal resistance when the voids and scratches were filled with a thermal joint compound.(3) Most commercially available cast or extruded heatsinks will require spotfacing when used in high-power applications. In general, milled or machined surfaces are satisfactory if prepared with tools in good working condition. In this note, mounting procedures are discussed in gen· eral terms for several generic classes of packages. As newer packages are developed, it is probable that they will fit into the generic classes discussed in this note. Unique requirements are given on data sheets pertaining to the particular package. The following classes are defined: Stud Mount Flange Mount Pressfit Plastic Body Mount Tab Mount Surface Mount Appendix A contains a brief review of thermal resis· tance concepts. Appendix B discusses measurement difficulties with interface thermal resistance tests. Appendix C indicates the type of accessories supplied by a number of manufacturers. Mounting Holes Mounting holes generally should only be large enough to allow clearance of the fastener. The larger thick flange type packages having mounting holes removed from the semiconductor die location, such as the TO-3, may successfully be used with larger holes to accommodate an insulating bushing, but many plastic encapsulated packages are intolerant of this condition. For these packages, a smaller screw size must be used such that the hole for the bushing does not exceed the hole in the package. Punched mounting holes have been a source oftrouble because if not properly done, the area around a punched hole is depressed in the process. This "crater" in the heatsink around the mounting hole can cause two prob· lems. The device can be damaged by distortion of the package as the mounting pressure attempts to conform it to the shape of the heatsink indentation, or the device may only bridge the crater and leave a significant per· centage of its heat-dissipating surface out of contact with the heatsink. The first effect may often be detected immediately by visual cracks in the package (if plastic). but usually an unnatural stress is imposed, which results in an early-life failure. The second effect results in hotter operation and is not manifested until much later. Although punched holes are seldom acceptable in the relatively thick material used for extruded aluminum heatsinks, several manufacturers are capable of properly utilizing the capabilities inherent in both fine-edge blanking or sheared-through holes when applied to sheet metal as commonly used for stamped heatsinks. The holes are pierced using Class A progressive dies mounted on four-post die sets equipped with proper pressure pads and holding fixtures. MOUNTING SURFACE PREPARATION In general, the heatsink mounting surface should have a flatness and finish comparable to that of the semiconductor package. In lower power applications, the heatsink surface is satisfactory if it appears flat against a straight edge and is free from deep scratches. In high-power applications, a more detailed examination of the surface is required. Mounting holes and surface treatment must also be considered. Surface Flatness Surface flatness is determined by comparing the var· iance in height (t.h) of the test specimen to that of a reference standard as indicated in Figure 2. Flatness is normally specified as a fraction of the Total Indicator Reading (TIR). The mounting surface flatness, i.e, t.h/TIR, if less than 4 mils per inch, normal for extruded aluminum, is satisfactory in most cases. Surface Finish Surface finish is the average of the deviations both above and below the mean value of surface height. For minimum interface resistance, a finish in the range of 50 to 60 microinches is satisfactory; a finer finish is costly to achieve and does not significantly lower contact resis- (3) Catalog #B7·HS·9 (19Bn page B, Thermelloy, Inc., P.O. Box Bl0B39, Dallas, Texas 75381-0839. 264 When mounting holes are drilled, a general practice with extruded aluminum, surface cleanup is important. Chamfers must be avoided because they reduce heat transfer surface and increase mounting stress. However, the edges must be broken to remove burrs which cause poor contact between device and heatsink and may puncture isolation material. very thin layer using a spatula or lintless brush, and wiped lightly to remove excess material. Some cyclic rotation of the package will help the compound spread evenly over the entire contact area. Some experimentation is necessary to determine the correct quantity; too little will not fill all the voids, while too much may permit some compound to remain between well mated metal surfaces where it will substantially increase the thermal resistance of the joint. To determine the correct amount, several semiconductor samples and heatsinks should be assembled with different amounts of grease applied evenly to one side of each mating surface. When the amount is correct a very small amount of grease should appear around the perimeter of each mating surface as the assembly is slowly torqued to the recommended value. Examination of a dismantled assembly should reveal even wetting across each mating surface. In production, assemblers should be trained to slowly apply the specified torque even though an excessive amount of grease appears at the edges of mating surfaces. Insufficient torque causes a significant increase in the thermal resistance of the interface. To prevent accumulation of airborne particulate matter, excess compound should be wiped away using a cloth moistened with acetone or alcohol. These solvents should not contact plastic-encapsulated devices, as they may enter the package and cause a leakage path or carry in substances which might attack the semiconductor chip. The silicone oil used in most greases has been found to evaporate from hot surfaces with time and become deposited on other cooler surfaces. Consequently, manufacturers must determine whether a microscopically thin coating of silicone oil on the entire assembly will pose any problems. It may be necessary to enclose components using grease. The newer synthetic base greases show far less tendency to migrate or creep than those made with a silicone oil base. However, their currently observed working temperature range are less, they are sl.ightly poorer on thermal conductivity and dielectric strength and their cost is higher. Data showing the effect of compounds on several package types under different mounting conditions is shown in Table 1. The rougher the surface, the more valuable the grease becomes in lowering contact resistance; therefore, when mica insulating washers are used, use of grease is generally mandatory. The joint compound also improves the breakdown rating of the insulator. Surface Treatment Many aluminum heatsinks are black-anodized to improve radiation ability and prevent corrosion. Anodizing results in significant electrical but negligible thermal insulation. It need only be removed from the mounting area when electrical contact is required. Heatsinks are also available which have a nickel plated copper insert under the semiconductor mounting area. No treatment of this surface is necessary. Another treated aluminum finish is iridite, or chromateacid dip, which offers low resistance because of its thin surface, yet has good electrical properties because it resists oxidation. It need only be cleaned of the oils and films that collect in the manufacture and storage of the sinks, a practice which should be applied to all heatsinks. For economy, paint is sometimes used for sinks; removal ofthe paint where the semiconductor is attached is usually required because of paint's high thermal resistance. However, when it is necessary to insulate the semiconductor package from the heatsink, hard anodized or painted surfaces allow an easy installation for low voltage applications. Some manufacturers will provide anodized or painted surfaces meeting specific insulation voltage requirements, usually up to 400 volts. It is also necessary that the su rface be free from all foreign material, film, and oxide (freshly bared aluminum forms an oxide layer in a few seconds). Immediately prior to assembly, it is a good practice to polish the mounting area with No. 000 steel wool, followed by an acetone or alcohol rinse. INTERFACE DECISIONS When any significant amount of power is being dissipated, something must be done to fill the air voids between mating surfaces in the thermal path. Otherwise the interface thermal resistance will be unnecessarily high and quite dependent upon the surface finishes. For several years, thermal joint compounds, often called grease, have been used in the interface. They have a resistivity of approximately 60'ClWlin whereas air has 1200'ClWlin. Since surfaces are highly pock-marked with minute voids, use of a compound makes a significant reduction in the interface thermal resistance of the joint. However, the grease causes a number of problems, as discussed in the following section. To avoid using grease, manufacturers have developed dry conductive and insulating pads to replace the more traditional materials. These pads are conformal and therefore partially fill voids when under pressure. Conductive Pads Because of the difficulty of assembly using grease and the evaporation problem, some equipment manufacturers will not, or cannot, use grease. To minimize the need for grease, several vendors offer dry conductive pads which approximate performance obtained with grease. Data for a greased bare joint and a joint using Grafoil, a dry graphite compound, is shown in the data of Figure 3. Grafoil is claimed to be a replacement for grease when no electrical isolation is required; the data indicates it does indeed perform as well as grease. Another conductive pad available from Aavid is called KON-DUX. It is made with a unique, grain oriented, flake-like structure (patent pending). Highly compressible, it becomes Thermal Compounds (Grease) Joint compounds are a formulation of fine zinc or other conductive particles in a silicone oil or other synthetic base fluid which maintains a grease-like consistency with time and temperature. Since some of these compounds do not spread well, they should be evenly applied in a 265 Table 1 Approximate Values for Interface Thermal Resistance Data from Measurements Performed in Motorola Applications Engineering Laboratory Dry interface values are subject to wide variation because of extreme dependence upon surface conditions. Unless otherwise noted the case temperature is monitored by a thermocouple located directly under the die reached through a hole in the heatsink. (See Appendix'B for a discussion of Interface Thermal Resistance Measurements.) Interface Thermal Resistance Package Type and Data JEOEC Outlines Description ("CIW) Test Torque In-Lb Dry Lubed Dry Lubed Type Metal-to-Metal With Insulator DO-203AA, TO-210AA TO-208AB 10-32 Stud 7/16" Hex 15 0.3 0.2 1.6 0.8 3 mil Mica DO-203AB, TO-210AC TO-208 1/4-28 Stud 11/16" Hex 25 0.2 0.1 0.8 0.6 5mil DO-208AA Pressfit, 112" - 0.15 0.1 - - - TO-204AA (TO-31 Diamond Flange 6 0.5 0.1 1.3 0.36 3 mil Mica TO-213AA (TO-66) Diamond Flange 6 1.5 0.5 2.3 0.9 2 mil TO-126. Thermopad 114" x 3/8" 6 2.0 1.3 4.3 3.3 2 mil TO-220AB Thermowatt 8 1.2 1.0 3.4 1.6 2 mil See Note Mica 1 Mica Mica 1,2 Mica NOTES. 1. See Figures 3 and 4 for additional data on TO 3 and TO 220 packages 2. Screw not insulated. See Figure 12. formed to the surface roughness of both the heatsink and semiconductor. Manufacturer's data shows it to provide an interface thermal resistance better than a metal interface with filled silicone grease. Similar dry conductive pads are available from other manufacturers. They are a fairly recent development; long term problems, if they exist, have not yet become evident. " such as mica, have a hard, markedly uneven surface. With many isolation materials reduction of interface thermal resistance of between 2 to 1 and 3 to 1 are typical when grease is used. Data obtained by Thermalloy, showing interface resistance for different insulators and torques applied to TO-204 (TO-3) and TO-220 packages, are shown in Figure 3, for bare and greased surfaces. Similar materials to those shown are available from several manufacturers. It is obvious that with some arrangements, the interface thermal resistance exceeds that of the semiconductor (junction to case). Referring to Figure 3, one may conclude that when high power is handled, beryllium oxide is unquestionably the best. However, it is an 'expensive choice. (It should not be cut or abraided, as the dust is highly toxic:) Thermafilm is a filled polyimidematerial which is used for isolation (variation of Kapton). It is a popular material for low power applications because of its low cost ability to withstand high temperatures, and ease of handling in contrast to mica which chips and flakes easily. A number of other insulating materials are also shown'. They cover a wide range of insulation resistance, thermal resistance and ease of handling. Mica has been widely used in the past because it offers high breakdown voltage and fairly low thermal resistance at a low cost but it certainly should be used with grease. Silicone rubber insulators have gained favor because they are somewhat conformal under pressure, Their abilityto fill in most ofthe metal voids atthe interface reduces the need for thermal grease. When first introduced, they suffered from cut-through after a few,years in service. The ones presently available have solved this problem by having imbedded pads of Kapton or fiberglass. By INSULATION CONSIDERATIONS Since most power semiconductors use are vertical device construction it is common to manufacture power semiconductors with the output electrode (anode, collector or drain) electrically common to the case; the problem of isolating this terminal from ground is a common one. For lowest overall thermal resistance, which is quite important when high power must be dissipated, it is best to isolate the entire heatsink/semiconductor structure from ground, rather than to use an insulator between the semiconductor and the heatsink. Heatsink isolation is not always possible, however, because of EMI requirements, safety reasons, instances where a chassis serves as a heatsink or where a heatsink is common to several nonisolated packages. In these situations insulators are used to isolate the individual components from the heatsink. Newer packages, such as the Motorola Full Pak and EMS modules, contain the electrical isolation material within, thereby saving the equi'pment manufacturer the burden of addressing the isolation problem. Insulator Thermal Resistance When an insulator is used, thermal grease is of greater importance than with a metal-to-metal contact, because two interfaces exist instead of one and some materials, 266 1 9 --- - f-"'- = 1 1 - 6 8 r - I 21 131 141 {ll Thermalfilm •. 002 (.05) thick. (2) Mica•. 003 (.08) thick. (3) Mica•. 002 (.05) thick. (4) Hard anodized •. 020 (.511 thick. f51 (5) Aluminum oxide•. 062 (, .57) thick. I-- 16) (6) Beryllium oxide•. 062 (1.57) thick. (7) Bare ioint - no finish. (8) Grafoil. .005 1.13) thick.o- 17) -Grafoil IS not an msulating material , 6 5 --::,- J 1 :--.. 1 181 0 4 MOUNTING SCREW TOROUE IIN-lBSI I 72 I I I - ,161 " MOuNTING SCREW TORQUE I 145 217 290 362 INTERFACE PRESSURE IpSI) 1 1 1 0 6 5 111 I I 435 72 '1~·l8SI I I I I I 145 217 290 362 435 INTERFACE PRESSURE 'ps" 3a. TO-204AA (TO-3) Without Thermal Grease 3b. TO-204AA (TO-3) With Thermal Grease 1 4 - 1 0 ---- ~- , 2 liNUS) 4 (1) Thermalfilm •. 022 (.05) thick 121 - I 31 14) (2) Mica •. 003 (.08) thick. (3) Mica, .002 (,05) thick. (4) Hard anodized •. 020 (.51) thick (5) Thermalsilli .. 009 (.23) thick. (6l Thermalsillll •. 006 {.15l thick. (7) Bare joint - no finish. (8) Grill.oil •. 005 (,13) thick" 101 ,~:(71 ·Grafoll IS not an insulating mater,al 1 5 4 MOUNTING SCREW TOROUE MOLJr"IITlf'.IG SCREW TORQuE IIN·LBSI I"HBS, 3c. TO-220 Without Thermal Grease 3d. TO-220 With Thermal Grease Figure 3. Interface Thermal Resistance for TO-204, TO-3 and TO-220 Packages using Different Insulating Materials as a Function of Mounting Screw Torque (Data Courtesy Thermalloy) Table 2. Thermal Resistance of Silicone Rubber Pads comparing Figures 3c and 3d, it can be noted that Thermasil, a filled silicone rubber, without grease, has about the same interface thermal resistance as greased mica for the TO-220 package. A number of manufacturers offer silicone rubber insulators. Table 2 shows measured performance of a number of these insulators under carefully controJled, nearly identical conditions. The interface thermal resistance extremes are over 2: 1 for the various materials. It is also clear that some of the insulators are much more tolerant than others of out-of-flat surfaces. Since the tests were performed, newer products have been introduced. The Bergquist K-10 pad, for example, is described as having about 2/3 the interface resistance of the Sil Pad 1000 which would place its performance close to the Chomerics 1671 pad. AAVID also offers an isolated pad caJled Manufacturer Product RIICS (a 3 Mils* RIICS Cn 7.5 Mils' Wakefield Bergquist Stockwell Rubber Bergquist Thermalloy Shin-Etsu Delta Pad 173-7 Sil Pad K-4 1867 Sil Pad 400-9 Thermalsil II TC-30AG 5il Pad 400·7 1674 Delta Pad 174-9 Sil Pad 1000 Thermal Wafers Thermalsil III 1671 .790 .752 .742 .735 .680 .664 .633 .592 .574 .529 .500 .440 .367 1.175 1.470 1.015 1.205 1.045 1.260 1.060 1.190 .755 .935 .990 1.035 .655 Bergquist Chomerics Wakefield Bergquist Ablestik Thermalloy Chomerics *Test Fixture DeViation from flat from Thermalloy EIR86-1010. 267 Rubber-Due, however it is only available vulcanized to a heatsink and therefore was not included in the comparison. Published data from AAVID shows ROCS below 0.3°CIW for pressures above 500 psi. However, surface flatness and other details are not specified so a comparison cannot be made with other data in this note. The thermal resistance of some silicone rubber insulators is sensitive to surface flatness when used under a fairly rigid base package. Data for a TO-204AA (TO-3) package insulated with Thermasil is shown on Figure 4. Observe that the "worst case" encountered (7.5 mils) yields results having about twice the thermal resistance of the "typical case" (3 mils), for the more conductive insulator. In order for Thermasil III to exceed the performance of greased mica, total surface flatness must be under 2 mils, a situation that requires spot finishing. The conclusions to be drawn from all this data is that some types of silicon rubber pads, mounted dry, will out perform the commonly used mica with grease. Cost may be a determining factor in making a selection. Insulation Resistance When using insulators, care must be taken to keep the mating surfaces clean. Small particles of foreign matter can puncture the insulation, rendering it useless or seriously lowering its dielectric strength. In addition, particularly when voltages higher than 300 V are encountered, problems with creepage may occur. Dust and other foreign material can shorten creepage distances significantly; so having a clean assembly area is important. Surface roughness and humidity also lower insulation resistance. Use of thermal grease usually raises the withstand voltage of the insulation system but excess must be removed to avoid collecting dust. Because of these factors, which are not amenable to analysis, hi-pot testing should be done on prototypes and a large margin of safety employed. 12 iVl ~ '-' t'j z ~ ~ ~ ;~>37"'><~ .01 NOM. I ce· I I- 0.0499 HEATSINK y ,~ + 0.001 DIA. Heat Sink Mounting RIVET \.. I ~lJ.-, ~~ijS0,fYINTIMATE CONTACT AREA COMPLETE KNURL CONTACT AREA ADDITIONAL ./ HEATSINK PLATE ~ THIN CHASSIS Thin-Chassis Mou nting \. + /_ ~h-CHASSIS The hole edge must be chamfered as shown to prevent shearing off the knurled edge of the case during press-in. The pressing force should be applied evenly on the shoulder ring to avoid tilting or canting of the case in the hole during the pressing operation. Also. the use of a thermal joint compound will be of considerable aid. The pressing force will vary from 250 to 1000 pounds, depending upon the heatsink material. Recommended hardnesses are: copper-less than 50 on the Rockwell F scale; aluminum-less than 65 on the Brinell scale. A heatsink as thin as 1 8" may be used, but the interface thermal resistance will increase in direct proportion to the contact area. A thin chassis requires the addition of a backup plate. INSULATOR TEFLON BUSHING _,et, ~ $_ cL> - INSULATOR Figure 8. Press-Fit Package FLAT STEEL WASHER /~'.) - ,,0 I ~_j - Flange Mount A large variety of parts fit into the flange mount cate· gory as shown in Figure 9. Few known mounting difficulties exist with the smaller flange mount packages, such as the TO-204 (TO-3). The rugged base and distance between die and mounting holes combine to make it extremely difficult to cause any warpage unless mounted on a surface which is badly bowed or unless one side is tightened excessively before the other screw is started. It is therefore good practice to alternate tightening of the screws so that pressure is evenly applied. After the screws are finger-tight the hardware should be torqued to its final specification in at least two sequential steps. A typical mounting installation for a popular flange type part is shown in Figure 10. Machine screws (preferred) self-tapping screws, eyelets, or rivets may be used to secure the package using guidelines in the previous section. "Fastener and Hardware Characteristics." The copper flange of the Energy Management Series (EMS) Modules is very thick. Consequently, the parts are rugged and indestructible for all practical purposes. No SOLDER TERMINAL CONICAL WASHER , ~ __ HEXNUT Figure 7. Isolating Hardware Used for a Non-Isolated Stud-Mount Package Press Fit For most applications, the press-fit case should be mounted according to the instructions shown in Figure 8. A special fixture meeting the necessary requirements must be used. 271 ~~ ~~~ ~ ~ ~ CASE 1. 3. 11 CASEl"-07 CASE ll'-09 CASE 3578-01 TO-204M (TO-3) 9a. TO-3 Variations CASE 215-02 9b. Plastic Power Tap CASE 316-01 CASE 373-01 CASEllI-II CASE 383-01 CASE 807-01 CASE 807A-Ol ........ CASE 814-01 CASE 81l-01 CASE 816-01 CASE 32BA-Ol CASE 808-01 CASE 333-03 CASE 809-01 CASE 319-04 (CS-ll) CASE 333A-Ol (MAAC PAC) CASE 336-03 CASE 361A-Ol CASE 368-01 (HOG PAC) CASE 813-01 CASE 337-0l CASE 819-01 CASE 744-02 9c. Energy Management Series (Isolated Base Plate) CASE 744A-Ol 9d. RF Stripline Isolated Output Opposed Emitter (SOE) Series Figure 9. A Large Array of Parts Fit into the Flange-Mount Classification special precautions are necessary when fastening these parts to a heatsink. Some packages specify a tightening procedure. For example, with the Power Tap package, Figure 9b, final torque should be applied first to the center position. The RF power modules (MHW series) are more sensitive to the flatness of the heatsink than other packages because a ceramic (BeO) substrate is attached to a relatively thin, fairly long, flange. The maximum allowable flange bending to avoid mechanical damage has been determined and presented in detail in EB107 "Mounting Considerations for Motorola RF Power Modules." Many of the parts can handle a combined heatsink and flange deviation from flat of 7 to 8 mils which is commonly available. Others must be held to 1.5 mils, which requires that the heatsink have nearly perfect flatness. Specific mounting recommendations are critical to RF devices in isolated packages because of the internal ceramic substrate. The large area Case 368-1 (HOG PAC) will be used to illustrate problem areas. It is more sen- sitive to proper mounting techniques than most other RF power devices. Although the data sheets contain information on recommended mounting procedures, experience indicates that they are often ignored. For example, the recommended maximum torque on the 4-40 mounting screws is 5 in/lbs. Spring and flat washers are recommended. 'Over torquing is a common problem. In some parts returned for failure analysis, indentions up to 10 mils deep in the mounting screw areas have been observed. Calculations indicate that the length of the flange increases in excess of two mils with a temperature change of 75°C. In such cases, if the mounting screw torque is excessive, the flange is prevented from expanding in length, instead it bends upwards in the mid-section, cracking the BeO and the die. A similar result can also occur during the initial mounting ofthe device if an excessive amount of thermal compound is applied. With sufficient torque, the thermal compound will squeeze out of the mounting hole areas, but will remain under the center 272 the washer is only important when the size of the mounting hole exceeds 0.140 inch (6-32 clearance). Larger holes are needed to accommodate the lower insulating bushing when the screw is electrically connected to the case; however, the holes should not be larger than necessary to provide hardware clearance and should never exceed a diameter of 0.250 inch. Flange distortion is also possible if excessive torque is used during mounting. A maximum torque of 8 inch-pounds is suggested when using a 6-32 screw. Care should be exercised to assure that the tool used to drive the mounting screw never comes in contact with the plastic body during the driving operation. Such contact can result in damage to the plastic body and internal device connections. To minimize this problem. Motorola TO-220 packages have a chamfer on one end. TO-220 packages of other manufacturers may need a spacer or combination spacer and isolation bushing to raise the screw head above the top surface of the plastic. The popular TO-220 Package and others of similar construction lift off the mounting surface as pressure is applied to one end. (See Appendix B, Figure Bl.) To counter this tendency, at least one hardware manufacturer offers a hard plastic cantilever beam which applies more even pressure on the tab.(6)In addition, it separates NO 6 SHEET METAL SCREWS POWER TRANSISTOR INSULATING BUSHING HEAT (6) Catalog, Edition 18, Aichco Plastic Company, 5825 N. TriPP Ave., Chicago, IL 60546. SOCKET I Figure 10. Hardware Used for a TO·204AA (TO·3) Flange Mount Part CASE 221 A·02 (TO-220ABI ofthe flange, deforming it. Deformations of 2-3 mils have been measured between the center and the ends under such conditions (enough to crack internal ceramic). Another problem arises because the thickness of the flange changes with temperature. For the 75°C temperature excursion mentioned, the increased amount is around 0.25 mils which results in further tightening of the mounting screws, thus increasing the effective torque from the initial value. With a decrease in temperature, the opposite effect occurs. Therefore thermal cycling not only causes risk of structural damage but often causes the assembly to loosen which raises the interface resistance. Use of compression hardware can eliminate this problem. CASE 314B (5 PIN TO-2201 221B·01 (TO·220ACI CASE 3140 CASE 339 , Tab Mount The tab mount class is composed of a wide array of packages as illustrated in Figure 11. Mounting considerations for all varieties are similar to that for the popular TO-220 package, whose suggested mounting arrangements and hardware are shown in Figure 12. The rectangular washer shown in Figure 12a is used to minimize distortion of the mounting flange; excessive distortion could cause damage to the semiconductor chip. Use of CASE 340-01 (TO·2181 CASE 387-01 (TO·254AAI CASE 388A-01 (TO·258AAI CASE 806·02 (ICePAKI Figure 11. Several Types of Tab-Mount Parts 273 I) Preferred Arrangement for Isollted or Non·isollted Mounting. Screw is It Semiconductor Case Potential. 6-32 Hardware is Used. ... Choose from Parts Listed Below. ~ _ &J2HEX HEAOSCREW Plastic Body Mount The Thermopad and Full Pak plastic power packages shown in Figure 13 are typical of packages in this group. They have been designed to feature minimum size with no compromise in thermal resistance. For the Thermopad (Case 77) parts this is accomplished by die-bonding the silicon chip on one side of a thin copper sheet; the opposite side is exposed as a mounting surface. The copper sheet has a hole for mounting; plastiC is molded enveloping the chip but leaving the mounting hole open. The low thermal resistance of this construction is obtained at the expense of a requirement that strict attention be paid to the mounting procedure. The Full Pak (Case 221C-01) is similar to a TO-220 except that the tab is encased in plastic. Because the mounting force is applied to plastic, the mounting procedure differs from a standard TO-220 and is similar to that of the Thermopad. Several types of fasteners may be used to secure these packages; machine screws, eyelets, or clips are preferred. With screws or eyelets, a conical washer should be used which applies the proper force to the package over a fairly wide range of deflection and distributes the force over a fairly large surface area. Screws should not be tightened with any type of air-driven torque gun or equipment which may cause high impact. Characteristics of a suitable conical washer is shown in Figure 5. Figwe 14 shows details of mounting Case 77 devices. Clip mounting is fast and requires minimum hardware, however, the clip must be properly chosen to insure that the proper mounting force is applied. When electrical isolation is required with screw mounting, a bushing inside the mounting hole will insure that the screw threads do not contact the metal base. The Full Pak, (Case 221C, 221D and 340B) permits the mounting procedure to be greatly simplified over that of a standard TO-220. As shown in Figure 15c, one properly chosen clip, inserted into two slotted holes in the heatsink, is all the hardware needed. Even though clip pressure is much lower than obtained with a screw, the thermal resistance is about the same for either method. This occurs because the clip bears directly on top of the die and holds the package flat while the screw causes the package to lift up somewhat under the die. (See Figure B1 of Appendix B.) The interface should consist of a layer of thermal grease or a highly conductive thermal pad. Of course, screw mounting shown in Figure 15b may also be used but a conical compression washer should be included. Both methods afford a major reduction in hardware as compared to the conventional mounting method with a TO-220 package which is shown in Figure 15a. b) Alternate Arrangement for Isolated Mounting when Screw must be at Heatsink Potential. 4-40 Hardware is Used. ... Use Parts Listed Below. .... PANORHE'HEAOSCREW I FLAT WASHER ==f==Y~ULAnNG BUSHING [,--.---:;::::J L-1.J 111 RECTANGULAR STEEL WASHER SEMICONOUCTOR 'Cj'~'A='====:::> SEMICONOUCTOR ,CASE 221. 221AJ , I 121RECTANGULAii INSULATOR 'CI==~========~ HEATSINK , 'c=J 2 BUSHING RECTANGULAR INSULATOR HEATSINK ~ '3,FLATWASHER ,4' CONICAL WASHER I '-\::llJ 6·32 HEX r-"UT i / '~----- COMPRESSION WASHER 4·4{I HEX NUT (1) Used with thin chassis and or large hole. (2) Used when isolation is required. (3) Required when nylon bushing is used. Figure 12. Mounting Arrangements for Tab Mount TO-220 the mounting screw from the metal tab. Tab mount parts may also be effectively mounted with clips as shown in Figure 15c. To obtain high pressure without cracking the case, a pressure spreader bar should be used under the clip. Interface thermal resistance with thecantilever beam or clips can be lower than with screw mounting. The ICePAK (Case 806-02) is basically an elongated TO-220 package with isolated chips. The mounting precautions for the TO-220 consequently apply. In addition, since two mounting screws are required, the alternate tightening procedure described for the flange mount package should be used. In situations where a tab mount package is making direct contact with the heatsink, an eyelet may be used, provided sharp blows or impact shock is avoided. CASE 77 (TO-225AA1 TO-1261 (THERMOPADI Figure 13_ Plastic BOdy-Mount Packages 274 l ~ ~ ~ \ HEAT SINK SURfACE /' ~~ MACHINE SCREW OR SHEET METAL SCREW COMPRESSION WASHER I !~ .---l-.. THERMOPAD PACKAGE "-.. INSULATING WASHER ~""" IOPTIONAl! " MACHINE OR SPEED NUT ~. 14a. Machine Screw Mounting 15a. Screw-Mounted TO-220 ~ ~COMPRESSIO~ 14b. Eyelet Mounting '" WASHER ~uT 15b. Screw-Mounted Full Pak 14c. Clips Figure 14. Recommended Mounting Arrangements for TO-225AA (TO-126) Thermopad Packages Surface Mount Although many of the tab mount parts have been surface mounted, special small footprint packages for mounting power semiconductors using surface mount assembly techniques have been developed. The DPAK, shown in Figure 16, for example, will accommodate a die up to 112 mils x 112 mils, and has a typical thermal resistance around 2°CIW junction to case. The thermal resis- 15c. Clip-Mounted Full Pak Figure 15. Mounting Arrangements for the Full Pak as Compared to a Conventional TO-220 275 tance values of the solder interface is well under l°CIW. The printed circuit board also serves as the heatsink. Standard Glass-Epoxy 2-ounce boards do not make very good heatsinks because the thin foil has a high thermal resistance. As Figure 17 shows, thermal resistance assymtotes to about 20°CIW at 10 square inches of board area, although a point of diminishing returns occurs at about 3 square inches. Boards are offered that have thick aluminum or copper substrates. A dielectric coating designed for low thermal resistance is overlayed with one or two ounce copper foil for the preparation of printed conductor traces. Tests run on such a product indicate that case to substrate thermal resistance is in the vicinity of l°CIW, exact values depending upon board type.(7) The substrate may be an effective heatsink itself, or it can be attached to a conventional finned heatsink for improved performance. Since DPAK and other surface mount packages are designed to be compatible with surface mount assembly techniques, no special precautions are needed other than to insure that maximum temperature/time profiles are not exceeded. ofthe various metal power packages are not designed to support the packages; their cases must be firmly supported to avoid the possibility of cracked seals around the leads. Many plastic packages may be supported by their leads in applications where high shock and vibration stresses are not encountered and where no heatsink is used. The leads should be as short as possible to increase vibration resistance and reduce thermal resistance. As a general practice however, it is better to support the package. A plastic support for the TO-220 Package and other similar types is offered by heatsink accessory vendors. In many situations, because its leads are fairly heavy, the CASE 77 (TO-22SAA) (TO-127) package has supported a small heatsink; however, no definitive data is available. When using a small heatsink, it is good practice to have the sink rigidly mounted such that the sink or the board is providing total support for the semiconductor. Two possible arrangements are shown in Figure 18. The arrangement of part (a) could be used with any plastic package, but the scheme of part (18b) is more practical r. HEATSINK "-~-1,/'1 TO-225M CASE 77 HEATSINK SURFACE , 'I CASE 369·03 / ~ CASE 369A·04 c." . Figure 16. Surface Mount D-PAK Parts CIRCUIT BOARD 100 ". " ,,/' TWIST LOCKS OR SOLOERABLE LEGS ~ 18a. Simple Plate, Vertically Mounted §O '" PCB. 1151N THICK I--GI0 FR4. 2 OUNCE EPOXY GLASS BOARD. "--DOUBLE SIDED 80 tj z ~ ~ ---+---'-'~ COMP,SYNC ~ + 5,6 k 11,0 /LF MC)4lS04 2 MC)4lS05 RIN'l' +-+--.......---,;Q) ROUT ~ l'50 PF* ::.a-'-"'W..-J LOCAlIREMOTE (al (bl GIN'l' t-.,--i-1r--i':P GOUT J:'50 ¢ "C>o-"-"'W..-J RGBI TTL TO RGB. 1 V ANALOG CONVERSION 390U Figure 7 shows a circuit to interface a TTL RGBI output personal computer to the RGB analog inputs of the MC1378. If the circuit is used with the values shown. no coupling capacitors are required to the RGB inputs of the MC1378. The + 5 volt supply to the 390 n resistors should be very clean to prevent interference on the encoded signal. IC4 is used to simulate 'brown' to be compatible with TTL display monitors. +-~~_--'~ BOUT "'o-''-'II'~ ~ 330°1,::,,'50pF ./' USING THE MC1378IN CONJUNCTION WITH THE TDA3301/3 FOR OVERLAYS IN BOTH RGB AND COMPOSITE VIDEO 1.25V Figure 8. Noninverting Buffer. Level Changer In some video applications both RGB overlay and com· posite video overlay are required, In these situations the MC1378 can be used as a time base locked to the remote source, not only for the graphics computer, but also for the color decoder. The burst gate output of the MC1378 appearing at pin 5 can be used to drive the sandcastle pulse input of the TDA3301/3 at pin 27, Because the output level of the MC1378 istoo lowto drive the TDA3301/3 directly, a small noninverting buffer is used, as shown in Figure 8, to ena· ble the burst gate pulse to exceed the required slice level at the TDA3301/3. A vertical pulse for the TDA3301/3 clamping system can be obtained at pin 38 ofthe MC1378 operating in the REMOTE MODE only when a valid video signal is applied. The vertical output must be inverted as shown in Figure 9, If a continuous vertical pulse is required so that the output clamps of the TDA3301/3 are always operating, a locked 50/60 Hz oscillator will have to be used. This could consist of a MC1455 type timer circuit. If a vertical pulse is produced by the microcomputer graphics source, it should be used instead. When in LOCAL MODE, an alternative source of vertical sync must be found to drive the TDA3301/3. The overlay fast video switches in the MC1378 and TDA3301/3 operate in the opposite sense to each other. Therefore an inverter must be used between pin 25 of the MC1378 and pin 23 of the TDA3301/3. The delay produced by the use of a delay line in the luminance path of the MC1378 must be compensated by using a similar delay in the overlay enable line as shown in Figure 10. The RGB inputs are essentially compatible between the MC1378 and the TDA3301l3, and can be connected as shown in Figure 11. r---"'~~ + 12 V TO PIN 27 OF TDA3301'3 12Vp·p BURST GATE -Jl FROM PIN 5 OF MC1378 4 Vp·p BURST GATE Figure 9. Vertical Output Inverter 1/6 SN74LS04 4Vp-p IREMOTE MODEl FROM PIN 38 OF Me1378 ~Jl 5 Vp·p TO PIN 28 OF TDA3301'3 Figurll 10. Overlay Input Inverter and Delay TO PIN 23 OF . - - - - - - - - - { ) TDA33013 FAST BLANKING 400 ns IOPT.) X>~Mr--=::::!,::!:!::=-......OTO 1,1k 291 ~k OVERLAY ENABLE PIN 15 OF MC1378 Figure 11. RGB Input Connection G-;:-i 10 IJ-F Figure 12. 3.58 MHz Chroma Trap + l!Wr.---10 IJ-H 0,1 r-<> 25 10IJ-F - TO TDA3301/3 TO 10 IJ-F 0,1 r-<>26 1 Vp·p MC1378 15~ (lSOn MAX 0,1 16~ lOIJ-F SOURCE Z, SEE ~ f----O 24 TOA3301I3 INPUTS DATA SHEETI R G B 14 COMPOSITE VIDEO INPUT 10 k 1.5 k 390~FIJOPF + PIN 37 = 1,8 k Figure 14. NTSC Components for TDA3301/3 for Coupling the Color I.F. to the Demodulators Figure 13. RGB Output Blanking Circuit (One of Three Required Shown) +12V POSITIVE COMPOSITE BLANKING 100 pf i+iiv-------~ TO TO GREEN CKT BLUE CKT r------- I f' 4 _ _ _ _ _ --1I I lN4148 I PIN 20 : RED OUT o-~~H__",,"t-'"VV'"'-~ I PIN 22 I RED fEEDBACK PIN3~~~N7 PIN 8 NON·ADJUSTABLE NTSC CONNECTION @ J. RED lVp-p IN75{J NOTE: Use monochrome signal with burst to set balance, with saturation I at nominal. I I NOTE: Set feedback pots and NOTE: The circuit shown within ~ brightness control for correct the dotted line must be duplicaL~~n~a!..o~~ _ _ _ _ _ _ _ ~d...!?~I~~~!!'.e~. __ Figure 15. MC1378 Subcarrier Notch Filter A 3,58 MHz chroma trap for the luminance input is shown in Figure 12. For more general information, see the TDA3301/3 data sheet. A circuit for blanking, filtering and driving a 75 n load with 1 V POp is shown in Figure 13, The 5 V composite blanking could be developed by using part of the circuit shown in Figure 4. Figure 14 shows a method for balancing the 3.58 MHz or 4.43 MHz demodulator leakage appearing at the RGB outputs. Normally this is not necessary, but for more exacting applications it may be required, 400 n, MC1378 100 n 1,1 k DELAY MC1378 PIN17 ~ PIN22 91 pF k 12 } 358 MHz '1 22IJ-H _ '1 FOR 443 MHz, _ C=68pF l = 18IJ-H = Figure 16. Improved Remote Video Input Isolation Circuit MC1378 SUBCARRIER NOTCH FILTER Cross color can cause annoying rainbow effects on fast luminance edges especially in noninterlaced pictures. Figure 15 shows a simple subcarrier notch filter in the luminance delay path of the MC1378 to remove some of the offending cross color artifacts at the expense of luminance bandwidth. The cross color problem can be especially bad when attempting to record on consumer type VCRs because on playback the chroma-horizontal interleaving becomes random, The notch method is equally effective on PAL or NTSC, +5V 10 k 22 k }-+_--'VV\O--_ IMPROVED REMOTE VIDEO INPUT ISOLATION CIRCUIT FROM lOCAU REMOTE at the composite video input. Typically, the cross talk is about -35 dB at 4.43 MHz and better at 3.58 MHz. Low frequencies are better than - 60 dB. The circuit shown in Figure 16 will improve the isolation in the LOCAL MODE by an additional - 20 dB. Because of certain limitations in the device and its packaging, the cross talk from remote composite video input to composite video output can be troublesome when operating in the LOCAL MODE with a video signal present 292 MC1378 NTSC LUMINANCE COMB FILTER To avoid loss of luminance bandwidth while removing color artifacts, a simple comb filter can be used in NTSC (see Figure 17). For 625 line PAL, a more complex arranagement has to be made which would be beyond the scope of this application note. The NTSC comb filter is only effective on interlaced color and horizontal signals. Noninterlaced signals could become worse with this arrangement. However, it may be possible to short the delay line input, pins 1 and 2, on noninterlaced signals. The amplitude and phase adjustments are made when a small amount (550 mVp-p) of 3.58 MHz subcarrier is added at the output of the 400 ns delay line. The two adjustments are trimmed for minimum subcarrier at pin 22. By using this technique, virtually all the cross color artifacts are removed without loss of luminance bandwidth. Figure 17. MC1378 NTSC Luminance Comb Filter (For Interlaced Video Only) +5V PHASE +5V 2.2 k 18 "H Uk 400 n, DELAY T MC1378 PIN 17 2N4402 0 50 PF 560 n 1.2 k SET FOR MIN. 3.58 MHz COMPONENT AT PIN 22. MC1378 PIN 22 '1. PHASE COIL TOKO TYPE 10k, BOBBIN: KAN(CI CORE: 03·0009 POT CORE: 04·0002 CASE: 06·0088·1 WIRE: 38G (0.1 mml 34 TURNS TOKO TKAN9436HM NTSC DECODER COMB FILTER FOR THE TDA3301/3 Figure 18 shows a circuit similar to Figure 17 to improve the luminance bandwidth by removing the 3.58 MHz notch in the luminance channel of the TDA3301/3. Again, this filter, as shown, is only applicable to NTSC. Both -15 "H '2. ULTRASONIC OELAY LINE GTE SYLVANIA SDL345 3.579545 MHz 63.556", OR PHILIPS/AMPEREX DL750 luminance and chrominance are combed of chroma and luma respectively to remove colored artifacts in interlaced video, The setup is accomplished by adjusting the amplitude and phase for minimum subcarrier at the luminance output. Figure 18. NTSC Decoder Comb Filter for the TDA3301/3 +12V TO CHROMA BANOPASS 2.2k PHASE '--~-1...drT--4b-__-:,18:!,,~H~'~1-+_..{ 2.2 k 5.6 k 1 Vp·p COMPOSITE VIDEO 22 "F 2N4402 TO LUMA INPUT C>-1 + 2.2 k ADJUST FOR NULL OF CHROMA IN LUMA CHANNEL. '1. PHASE COIL TOKO TYPE 10 k, BOBBIN: KAN(CI CORE: 03·0009 POT CORE: 04·0002 CASE: 06·0088·1 WIRE: 38G 10.1 mml 34 TURNS 293 '2. ULTRASONIC DELAY LINE GTE SYLVANIA SDL345 3.579545 MHz 63.556", Rgure 19. Carrier Balance of Color Modulators CARRIER BALANCE OF COLOR MODULATORS +5V Certain applications require perfect carrier balance of the color modulators. This is simply realized in Figure 19. The two 100 k potentiometers should be adjusted with a black signal for minimum subcarrier at the video output. MC1378 1M 100 k ~-"W"""--o PIN 12 R- YCARRIER BALANCE +5V MC1378 1M 100 k ~~'VV'v--o PIN 13 B-Y CARRIER BALANCE Figure 20. Printed Circuit Board Layout Component Side Pattern (not full size) Circuit Side Pattern (not full size) 294 Figure 21. Printed Circuit Board Components Layout RE @- G 'Taka H321 LNP-1436PBAB orTDK DL122401D-1533 Figure 22. Photo 295 0 MC1378 EXPECTED WAVEFORMS Local-O Volts, Remote-5 Volts 3 Vdc Approximate (See Application Note) 3 4 MHz, 200-300 mVp-p Sine Wave (Oscilloscope Probe will disturb the Horizontal PLL) 4 Distorted 4 MHz Signal 5 4 V, 4 /LS Wide Pulse Locked to Horizontal 6 NTSC-O V/PAL-Open 7 Ground 8 3.58 MHz/4.43 MHz 300-800 mVp-p Sine or Square Wave from RMI in Local Mode - Shows Beat Between Remote Signal and Local Subcarrier, but otherwise unimportant 10 14.32/17.73 MHz, 150-300 mVp-p Sinewave (Scope Probe will disturb PLL) 11 Distorted 14.32117.73 MHz Signal 12113 3.5 Vdc Approximate 14/15116 1 Vp-p RGB Color Signals, Low for Black, High for Color. All Blanking at Black Level both for Horizontal and Vertical. These are Analog Inputs, so any Noise on RGB will appear at the Output. 17 Inverted Luma Signal 1 Vp-p for 100% Color Bars (1.8 V White/2.8 V Black) 18 Chroma Output 3.5814.43 MHz with Harmonics, Burst 100 mVp-p, Chroma 300 mVp'p, 100% Color Bars (Approximate Amplitudes) 19 3.4 Vdc Approximate 20 Chroma Input 3.58/4.43 MHz, Burst 100 mVp-p, Chroma 300 mVp-p, 100% Color Bars (Approximate Amplitudes) 21 3.3 Vdc Approximate 22 Inverted Luma 0.5 Vp-p, 100% Color Bars (0.9 White/l.4 V Black) 23 3.5 Vdc Approximate 24 Remote Video Input 1 Vp-p, Negative SYNC 25 Overlay Enable Input; Low - Encoded RGB, High - Remote Signal Threshold = Approximately 1.4 V 26 Ground 27 Composite Video Output 28 VCC +5 Vdc 29 PAL Identification Pin (Not Used in NTSC) In PAL Stepped Waveform at Vertical Rate In NTSC DC 0.5 V 30 2.7 Vdc Approximate 31 DC 0.6 V with 100 mV Vertical Ripple When Color Unkilled, 4.2 Vdc Approximate When Color Killed 32/33 36 MHz 200 mVp-p. Difficult to Observe with Conventional Oscilloscope Probe because of Grounding Problems 34 Ground 35 Clock Output 36 MHz, Sinewave 300 mVp-p, Open Circuit Approximate. When used at Lower Frequencies the Output may become Bigger and Clipped. Also same Scope Problem as with 32/33 at 36 MHz 36 VCC +5 Vdc 37 2.2 Vdc Approximate (See Application Note) 38 Local Composite SYNC Input in LOCAL MODE TTL Negative Remote Vertical SYNC Output in REMOTE MODE TTL Negative 39 Composite SYNC TTL Output Negative 40 Horizontal SYNC Input TTL Negative Pin 1 2 296 APPENDIX DIRECTORY OF COMPONENT MANUFACTURERS California Crystal Laboratories (800) 333-9825 crystals Coil craft 1102 Silver Lake Road Cary, IL 60013 (312) 639-6400 coils Comtec (602) 526-4123 crystals Fox Electronics (813) 693-0099 crystals GTE Sylvania Electronic Components Division 2401 Reach Road Williamsport, PA 17701 (717) 326-6591 crystals, ultrasonic delay lines (for comb filter) International Crystals (405) 236-3741 crystals muRata-Erie 2200 Lake Park Drive Smyrna, GA 30080 Distributor - Time Electronics Distributor - Sterling Electronics (404) 436-1300 coils see local directory contact muRata for nearest location Phillips/Amperex Optoelectronics Division (401) 232-0500 ultrasonic delay lines (for comb filter) Standard Crystal Corporation (818) 443-2121 crystals TDK Corporation of America 1600 Feehanville Drive Mount Prospect, IL 60056 (312) 803-6100 400 ns delay lines Toko America Inc. 1250 Feehanville Drive Mount Prospect, IL 60056 Distributor - Digikey Distributor - Inductor Supply (312) 297-0070 coils, transformers, 400 ns delay lines (800) 344-4539 (800) 854-1881 (800) 472-8421 (from within California) MOTOROLA DOES NOT ENDORSE THE VENDORS LISTED. THIS IS A PARTIAL VENDOR LIST, AND NO LIABILITY IS ASSUMED FOR OMISSIONS OR ERRORS IN ADDRESS, PRODUCT LINE OR OTHER INFORMATION. 297 298 AN1047 Electrical Characteristics of the CR2424 and CR2425 CRT Driver Hybrid Amplifiers By Dan Brayton CRICUIT AND THERMAL DESCRIPTION OF CR2424 AND CR2425 CRT DRIVER HYBRID AMPLIFIERS Therefore. worse case junction temperature rise over case (flange I is 1.6 watts x 35"CIW = 56"C. The type of transistor used in Motorola CRT hybrid driver amplifiers is rated for operation up to 200"C. At 150"C junction temperatures. MTTF for an individual transistor chip is greater than 140 years. CIRCUIT DESCRIPTION The circuit of the CRT driver amplifiers consists of a pair of complementary common emitter Class A stages DC stacked across the 60 V supply. The "top" PNP device is connected as a current source at DC through mid frequencies; at high frequencies. the "current source" becomes active. This complementary Class A pair drives complementary Class B emitter followers. CRT HYBRID TUBE ARC SIMULATION A tube arc was simulated by electrostatic discharge equipment. A variable voltage source charges up a capacitor. THERMAL DESCRIPTION O------"\M.,....- -.... All four transistors (silicon bipolarl have identical horizontal geometries (active areasl. gold metallization and plasma nitride passivation. These transistors are each mounted on .055 x .055 inch gold plated copper heat spreaders which serve to maximize the heat flow from the transistor die through the alumina thin-film substrate to the aluminum flange (heatsink or casel that is soldered to the back side of the substrate. This structure results in a thermal resistance of 35"C/watt max (30"C/watt typical I for junction to case (flange) for each of the four active transistors. Junction temperatures can. therefore. be computed if the power dissipation for each transistor is known. The power dissipated in each transistor is a function of the amplifier operating conditions as listed in Table 1. R eRT HYBRID 10UTPUTI Figure 1. Electrostatic Discharge Simulator Then the energy inside the capacitor is discharged through a resistor to the CRT hybrid. Test conditions of R = 10 ohms and C = 150 pF were used. CASE 1. UNPROTECTED; The CRT hybrid failed at 2500 volts. Because output of the Electrostatic Discharge Simulator is connected to ground during charge period. a 0.01 J.LF DC blocking capacitor is used to prevent output of the CRT hybrid to ground. which could damage the hybrid. Table 1. Transistor Power Dissipation 0, 02 03 Oesignation Type Class of Operation <4 PNP A POIW) NPN A POIW) PNP B PoIW) NPN B POIW) Case Case Case Case Case I II III IV V 0.75 0.2 1.6 0.8 1.0 0.75 1.6 0.2 0.8 1.0 <0.1 <0.1 <0.1 0.2 1.6 <0.1 <0.1 <0.1 0.2 1.6 Case Case Case Case Case I No connection to input pin 1; output = 30 Vdc II Black level; output = 55 Vdc III White level; output = 5.0 Vdc IV sa wave input f ~ 60 Hz; output ~ 40 Vp_p V sa wave input 7.5 ns pixel; output ~ 40 Vp_p General conditions: VCC ~ 60 V; load ~ Vee ~ 60 V ~I 0.01 fLF 8.5 pF 299 ~'D'S' CASE 2. PROTECTION RESISTOR: A protection resistor of 47 n is connected between the E.O.S. and hybrid. The hybrid failed at 4500 volts. Again a 0.01 JLF blocking capacitor is used to prevent the hybrid discharging to ground. CASE 4. BYPASS CAPACITOR: A 0.1 /LF bypass capacitor was added along with diode and resistor. In this case, failure of the hybrid occurred at 15,000 volts. 0.1/L F VFAll ~ 15.000 V Figure 3. Circuit for Case 2 Figure 5. Circuit for Case 4 CASE 3. PROTECTION DIODE: A protection diode (lS583 Hitachi) was added. Failure of the hybrid occurred at 9500 volts. Electrical characteristics for this diode are listed in Table 2 below. CONCLUSION: Obviously the circuit in case 4" offered the best protection to the hybrid amplifier. The bypass capacitor and diode should be placed as close to hybrid Vee node as possible, and ground leads on the bypass capacitor and hybrid should be able to carry surge current to insure the best protection. NOTE: A diode, Oz, should be added if there is reason to believe that large negative surges may reach the video driver output port. PERFORMANCE CHARACTERISTICS Typical bandwidth and rise and fall times of the CRT driver are shown in Figures 6 through 10. Figure 4. Circuit for Case 3 Table 2. Characteristics of Protection Diode 1S583 MAXIMUM RATINGS (TA Item Unit Rating ~ 25'C) TJ VR(peak) VR IF(peak) 10 V V mA mA 'C 250 220 625 200 175 NOTE: JEDEC DO-35 Seahng condItIOn. ELECTRICAL CHARACTERISTICS (TA ~ 25'C) Limit Item Symbol Test Condition Unit Min ~ Forward Voltage VF IF Reverse Current IR VR Reverse Recovery Time trr IF RL ~ ~ 50 NOTE: Glass Sealing condition. 300 lOa mA ~ IR 220 V ~ 30 mA ~ 0.1 IR n, ire Max 1.0 V 1.0 p.A 80 ns Figure 60 Bandwidth versus Output Load, CL Vo = 20Vpop BW(MHzl 175 172 166 160 150 140 CL (pFI 6 8.5 10 12 15 18 180 170 - -....... ....... 150 ......... ox: 140 >- '" 0 ~ ~ 130 ~o 120 110 Output Swing (VI 50 40 30 20 10 " 2.4 ....... ~ V) i= "- ""- ~ 40 Vpop 0 « ~ ~ \ 12 14 ,/ V) DO '\. 16 1.7 1.8 ," " / I ~ ,OSL , \ - ...... 1\>( OSL z '\ 100 10 2.2 Overshoot (VI Leading Trailing 2.5 1.2 4.0 2.4 4.6 3.0 4.2 2.8 2.4 1.2 tl (nsl 2.4 2.0 1.9 ,.., . 1-....", "~X ~ :g tr (nsl 2.6 2.2 1.9 1.8 1.8 ~\ ~Vpop i"-. ~ Vo = 4OVpop BW(MHzl 145 145 140 130 120 100 2.6 160 ~ Figure 7, Rise and Fall Times and Overshoot versus Output Swing Voltage (Under Regular Operation Condition VCC = 60 V, Load = 8,5 pF) loB \ \ \ \ \ \ \ OST ,, ,, \ ~ OST \ \ \ , \ ~tr '\... ~ 20 lB 1.6 CL, OUTPUT LOAD (pFI 50 40 30 20 10 VIDEO OUTPUT SWING IVOLTS poPI Figure 8. Rise (tr ) and Fall (t,) Times versus Output Load, CL CL (pFI 6.0 pF 8.5 pF 10 pF 12 pF 15 pF 18 pF tr (nsl 1.8 2.2 2.4 2.6 2.8 3.1 t, (nsl 1.6 2.0 2.1 2.3 2.5 2.8 ~ ~ A. CL = 8.5 pF VCC = 70 V tr (nsl tl (nsl BW (MHzl Condition 2.0 1.8 147 40 V Swing 2.6 2.2 133 50 V Swing 2.7 2.5 111 55 V Swing B. CL = 15 pF VCC = 70 V -- ~ ty Figure 90 Rise and Fall Times and Bandwidth versus Loads I--l.---V t::==I-- tr (nsl tl (nsl BW(MHzl Condition 2.6 2.1 133 40 V Swing 3.5 2.5 105 50 V Swing 3.6 2.8 83 55 V Swing C. CL = 8,5 P VCC = 60 V VOUT = 40 V Swing (Standard Operating Conditionsl 10 12 14 16 lB CL, OUTPUT LOAD (pFI 301 tr (nsl tl (nsl BW (MHzl 2.5 2.0 142 2.50 Ts.5PF All standard test conditions, except add R. ¢' Figure 10. Rise and Fall Times versus Serial Output Resistance R (0) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 I , ! 1.8 1.9 2.2 2.3 2.5 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.7 4.8 5.0 5.4 5.6 ! j ! 1 J..'-~ I....' If 1, ",- ~ ,,,,,,," ....... ~J~I " tt (ns) 2.1 2.1 2.2 2.4 2.5 2.6 2.7 2.8 3.0 3.2 3.4 3.4 3.6 3.8 4.0 4.2 4.4 4.5 4.8 4.8 5.0 I ! i tr (ns) I I I If 1 o o 20 40 60 80 100 120 140 R. OUTPUT RESISTANCE (OJ Figure 1,1. 302 160 180 200 AN1061 Application Note REFLECTING ON TRANSMISSION LINE EFFECTS This application note describes introductory transmission line characterization, analysis, and application. Over the past couple of years, microprocessors and digital 16gic in general have seen substantial increases in line drive capability. This increase has fostered the current logic and microprocessor speeds readily available today. The relatively quick rise and fall time of today's digital devices makes an understanding of transmission lines and their el(ects on system reliability a necessity. TRANSMISSION LINE CHARACTERIZATION When discussing transmission lines one should reflect on the following definition. A transmission line is two or more conductors separated by some insulating medium, used to carry a signal. At first glance this seems rather trivial, but upon closer examination one finds a host of physical nuances which make the transmission line a sophistcated element to describe, among which are: 1. Line resistance present in any non-ideal conductor. 2. Line conductance ((1/R) = G) present in any non-ideal insulating medium resulting in leakage currents. 3. Line inductance present in any current carrying conductor undergoing a change in magnetic flux. 4. The line capacitance present between the two conductors separated by the insulating medium. Figure 1 shows the line under discussion. The circuit consists of two series elements (Z + L) and two shunt elements (C + G). Figure 1. TransmisSion Line Circuit Our discussion will be primarily concerned with C + L, because these elements are the frequency dependent components of the line (neglecting skin effect). For frequencies above approximately 100 kHz, Zo, the characteristic impedance of the line, is equal to the square root of UC and is independent of line length. The propagation constant (tpd) or time delay constant is the square root of L·C, and is a function of line length. Zo is of particular importance to our discussion because when you match this impedance to the load, you reduce the effects of transmission imparted to both the source and the load. 303 TRANSMISSION LINE REFLECTIONS Reflections on a line are caused by a mismatch in Impedance between the line and the load. If all the power delivered to the line is absorbed by the load then there will be no reflected power back at the source side of the line. This principle of power conservation is the cornerstone of this application note. Refer to Figure 2 as the equations are discussed. The equation describes the ratio of absorbed power to reflected power based on the ratio of line to load impedance. Zo TRANSMISSION LINE v==- IFigure 2. Transmission Line The current delivered to the load is IL = IINC -IRFL (incident current minus reflected current), while the load voltage is, VL", VINC + VRFL (incident voltage plus reflected voltage). We need to find an equation that relates incident voltage to reflected voltage. Therefore noting thatthe load current IL = (VF - VRFL)/Zo (incident voltage minus reflected voltage divided by the characteristic impedance) we can see the following relationship. VINC + VRFL ZL VINC-VRFL (1) Zo Solving for VI~RFL (2) (3) (4) This expression is called the load reflection coefficient (PL). Note a Ps also exists which relates the ratio of source impedance to line impedance. This expression is called the source reflection coefficient and is shown in Equation 5. 304 Ps = Zs-Zo (5) Zs+Zo One can see that there are three distinct possibilities which require inspection. First, the situation where the load impedance equals the line impedance (Zl = Zo) and Pl = 0 (no reflections - a properly terminated line); second, where the load impedance is greater than the line impedance (Zl > Zo) and Pl is positive, generating a reflection whose polarity matches that of the incident voltage, and, finally, where the load impedance is less than the line impedance and Pl is negative, generating a reflection whose polarity is opposite to that of the incident voltage. Let's take a closer look at the last two cases. Assume that Zl = 4Zo, and that the source impedance = line impedance. V = source voltage, and Vl = load voltage (see Figure 3). Pc Zl -Zo = 4Zo- Zo = 0.6 4Zo+Zo = ~+Zo Zo TRANSMISSION LINE v=- I- 1=0 Figure 3. Transmission Line Circuit wIth ZL =4 • Zo and Zs =Zo Thus at I = 0 a voltage wave of 1/2{V) (because Zs and Zo form a voltage divider on V) begins to travel down the line and arrives at Zl one tpc! or propagation delay laler. When the wave encounters the load impedance mismatch, a reflected wave equal in magnitude to (V/2tO.6 is reflected back toward Ihe source, and arrives althe source again one !pet later. This causes the voltage at the source to rise therefore creating Ihe classic overshoot condition. Since the source and line impedance are matched no further reflections are generated and the line has reached its steady state condition. See Figure 4. Figure 4. Voltage versus Time Plot of ZL 305 =4 • Zo and Zs =Zo The next scenario is when Zt. < 4J. For this case assume the following conditions. ZL = Zd4 and Zs = Zo. See Figure 5. .254J-4J Pc = .25Zo + 4J = -0.6 1 TRANSMISSION LIN Vs v==- I- t= 0 Figure 5. Transmission Line ClrcuH with ZL = Zo I 4 and Zs = Zo At time t = 0 a voltage wave equal in magnitude to 1I2V begins to travel down the line arriving at the load one delay time later. The impedance mismatch generates a reflected wave equal in magnitude to the reflected wave discussed in the first example, but opposite in polarity. At time 2tpd this wave reaches the source and sums with the existing voltage present from time t = 0 (V/2), reducing its value to Vs/5 or ((V/2)(-O.6) + V/2). This is the classic undershoot condition. See Figure 6. Figure 6. Voltage versus Time Plot of ZL = Zof4 and Zs =Zo At this point we need to 'reflect on one of the equations described earlier. The equation states that VL= VINe + VRFL · We can see this holds true as noted In the preceding examples, where VL and Vs either increased or decreased with corresponding mismatches in impedance. THE LATTICE DIAGRAM The lattice diagram permits a network to be checked quickly for balance (match). The diagram is essentially a two-line graph with corresponding source and load impedance, connected by a reflection diagonal with a period of 2tpd (twice the line delay time). This diagonal is used to represent the reflected voltage's magnitude. See Figure 7. 306 SOURCE VOLTAGE (Vs ) LOAD VOLTAGE (VJ Ps side Pt- side 1=0 1= I 1= 2 Vrfl 2 = I?; ·Vrfl l 1= 3 1= 4 elc. Figure 7. LaHlce Diagram The example below will illustrate the use of the lattice diagram. For the analysis assume the following circuit (see Figure 8 and 9). Zo =500 TRANSMISSION LINE RL =3.90 Figure 8. Transmission Line Circuit for Zs = 7.5 0, Zo = 50 0 and ZL = 3.9 0 307 Ps= 7.5-SO 7.5 +SO = -0.739 (Vs) 1=0 (Vd Vi 11 = 3900-50 L 3900 +SO = 0.974 = Vs = 1.74V 1= 1 ,VL = 3.43V Vs = 2.18V,1 = 2 1= 3 , VL = 0.97V Vs = loB6V,I =4 1=5, VL =2.73V Vs = 2.09V,1 = 6 1= 7 , VL = l.46V Vs = 1.93V,1 = B 1= 9 , VL = 2.37V Vs = 2.05V,1 = 10 1= 11.VL = lo72V Vs =1.96V,1 = 12 t= 13, VL = 2.1BV Vs =2.02V,1 = 14 Figure 9. Lattice Diagram for ZS = 7.5 n. Zo = 50 nand ZL = 3.9 n Transmission Line Types There are essentially IWO Iypes of transmission lines; the microstrip and the slripline. The microslrip is shown in Figure 10. It consists of a conduclorseparated from the ground plane on one side by a dieleclric. - - - - TRACE h - DIELECTRIC FIGURE 10. Mlcrostrlp Transmission Line 308 The characteristic impedance of a one ounce line configured as a microstrip on G-10 fiber glass is: Z 0= 8 7 . Ln(5.98h) JER+1.41 (0.8w+t) (6) = 0.0015 in. for 1 OZ copper = 0.0030 in. for 2 OZ copper h w = 0.062 in. for G-10 glass epoxy = design dependent (based on current handling requirements.) = 0.015 in. For our discussion, ER = 4.7-5.3 For this example, with ER = 4.7, Zo = 116.6 n The unloaded propagation delay t". = 1.017 jo.475ER+ 0.67 ns/ft = 173 ns/ft. The stripline is a conductor separated from ground on two sides by a dielectric (see Figure 11). b - GROUND PLANE - DIELECTRIC ••••a- GROUND PLANE Figure 11. Strlpllne Transmission Line The characteristic impedance of G-10 fiber glass board trace configured as a stripline is: ZO=~.Ln[ 4b ] IE; 067n (0.8w + h) (7) Using the same parameters as above we find that 1.017 IE; = 2.20 ns/ft 309 Zo 60 Q. The propagation delay Loaded Transmission Line Propagation Delay and Impedance As stated earlier the unloaded propagation of a microstrip line is: J tpel = 1.107 0.475ER + 0.67 ns/ft This delay increases with capacitive loading. The increase is equal to /1 + Co/Co where CD is the distributed capacitance and Co is the intrinsic capacitance of the line. Co is obtained from Figure 3-8 of Reference 1, or alternatively it can be calculated as Co = ~ /Zo. For the micro strip described above with thickness (h) of 0.062 in, and signal trace width of 0.015 in, Co = 15 pf. Assuming this line is loaded with five 10 pf loads the loaded propagation delay becomes: (1.73ns) J1 + 50/15 = 3/60 ns/ft The loaded line impedance Zo' = Zo/ /1 + CD/CO = 116.6/2.08 = 56 C. For the stripline discussed above there is a corresponding increase in tpel and Zo. The loaded propagation delay ~' = 2.2 /1 + 50/15 = 4.57 ns/ft, while the loaded impedance ZOo = 60//1 +50/15 = 28.8 C. It is apparent that capacitive loading increases the propagation delay of the line while decreasing its impedance. TRANSMISSION LINE TERMINATION No discussion about transmission lines would be complete without examining the techniques to properly terminate a line. Essentially there are three (3) methods which can be employed. They are: 1) Unterminated line (controlling board parameters to match line and load impedance). 2) Series termination. 3) Parallel termination. Unterminated Line Method This method involves controlling the length of the line such that any reflections caused by the load are absorbed by the rise and fall time, t, and tf of the driving gate. Forthis method to be effective the propagation delay (loaded delay) of the line must be short relative to t, and 1t. This allows the reflected wave to sum with the rising or falling driving gate waveform. If four times the propagation delay of the line is less than or equal to t, or~, then minimal ringing (overshoot, undershoot) will be observed. Specifications for t, and ~ for various logic families are readily available. Knowing these times one can set the maximum 310 line length such that the lines \pt' <= t,/4. For distributed loads that are stubbed, the length of the stub should be set to minimize any reflections. A t,lt..t' ratio greater than 8:1 should suffice. Series Termination In series termination a resistance is inserted between the driving gate output and the line. The combined output impedance of the driving gate plus the added series resistance is selected to equal the loaded impedance of the line. Since the input impedance of the driven gate is much greater than Zo, the line will ring. Basically this termination configuration will ring once and reach steady state within 2\pt'. End of line loading, (lumped loading) is the only method of loading that is recommended for this type of termination. This is because any distributed load onthe line "sees" a voltage equalto v/2 until steady state. This condition could violate the valid V1H or V1l specification of these gates. Clearly distributed loads are to be avoided. Receivers at the end of the line will not experience this condition, as the incident voltage and the reflected voltage add together to equal the load voltage (Vl ) one \pt' after the signal is asserted. Parallel Termination In the parallel termination method two resistors are placed at the end of the line. One resistor from the line to ground, and the other from the line to VCC. The parallel combination of these resistors is set to be equal to the loaded impedance of the line. For example, if Zo' of the line is equal to 50 n, then the parallel combination of both reSistors should equal 50 n. Note this method of termination requires more drive current. The driver selected must be able to handle the additional load placed upon it by the added parallel load. Also it is apparent that this method of termination consumes power even in the steady state, as an additional current path has been set up between Vee and ground. A PRACTICAL EXAMPLE Upon completing the paper design for our new project, we begin to peruse our schematics for possible transmission line problems. For the purposes of our discussion assume the following configuration: Vee 5 volts PC trace microstrip configuration, G-10 fiber glass, 1 oz copper, ER = 4.7, w = 0.015, t = 0.0015, h = 0.062 Logic family: Fast TIL (drive and receive side of line) Driving gate: F241 buffer tf + tr F241: 2 ns (for 50pf lumped load) Number of loads (FOS's): Configuration: 5 ( input capacitance = 5pf/load) (IlL = 600 1lB, IIH = 100 1lB) Distributed loads approximately every 2 in. for a total trace length of 10 in. 311 Procedure 1. Calculate the lines characteristic impedance (Zo). zo = same as example described earlier = 116 n. 2. Calculate unloaded propagation delay (tpd). tpd = 1.017/0.475ER +0.67 = 1.73 ns/ft 3. Calculate the lines intrinsic capacitance (Co). Co = VZo expressed as nf/ft Co = (1.73 nslft)/116 = 15pf/ft = 1.25 pflin. * 10 in. = 12.5 pf 4. Calculate the loaded line impedance (Zo') Zo' = 116/1.25/12.5 = 67 C 5. Calculate the lines loaded propagation delay (tpd') tpd' = 1.73/1 +25/12.5 tpd' = 3.0 ns/ft = 0.25 nS/in. * 10in. = 2.5 ns» t,/4 As described earlier, since the loaded propagation delay of the line exceeds t, 14, we will have to terminate the line. The loads are not lumped at the end of the line, they are distributed. As explained earlier, series termination cannot be used because of the possible threshold violations. For this example we will use parallel termination. The parallel resistor combination will be chosen to match the loaded impedance of the line. Noting the drive current of the F241 , (loL = 64 ma, IOH= 15 mal, we can set the source current resistor equal to: VOH (min)/((5*100 l1a) + IOH/2) = 2 V/8 ma = 250 n Note: Im/2 arbitrarily chosen. Value could be reduced if required. The sink current resistor part of this terminator is equal to 91 C. This results in a drive sink current equal to: (Number of Loads" IIH) + V - VoL (F241)/91 = 5"600 ~ + 5v - .55V/91 n = 52 ma Note: Weight the source side terminator such that both sink and source current specification are not violated. As shown the parallel combination of the terminating resistors is set equal to the loaded line impedance. See Figure 12. 312 Note: Gate spacing = 2 inches - Figure 12. Transmission Line - Example Since the line is now properly terminated, reflections will be minimized. In this example, the loads were not stUbbed. Had they been located on a stUb, an extra calculation would have had to been performed to ascertain the maximum permissible stub length. This calculation runs as follows: 1. Set t,lIpd' = 8.5 and solve for~' tpd' = 2 nsl8.5 = 235 ps 2. Solve for the maximum stub length (x) 235 ps = 1.73 ns/ft j 1 + 5 pf/(x)in./1.25 pf/in. 235 ps = 144 ps/in. ~ X tpd = 1.017 /0.475E R + 0.67 = 1.73 nslft = 2.42 in. REFERENCES 1. MECL System Design Handbook, Motorola Inc., 4th ed., 1988. 2. W. Sinnema; Electronic Transmission Technology, Prentice-Hall, Englewood Cliffs, New Jersey, 1979. 3. The Interface Handbook Line Drivers and Receivers Interface, Fairchild Semiconductor, 1st ed., 1975. 313 314 AN1080 External-Sync Power Supply with Universal Input Voltage Range for Monitors By S.K. Tong and K.T. Cheng ABSTRACT days, switching power supplies replace the linear regulators due to high efficiency and light weight. However, the EMI/RFI generated by switching power supplies has adverse effects on the resolution of high-definition color monitors (e.g. 800x600 or higher). Asynchronous switching noise beat with the horizontal scanning frequency of the color monitor, creating undesirable interferences and jitter on the screen. It affects the horizontal resolution of the high-definition color monitor because the random pulses generated by the asynchronous switching operation and also deflect the electron beams and blur their precisely controlled positions. Thus, the switching power supply for the high-definition monitors or TVs must be synchronous with the horizontal frequency. Recently, mUlti-sync color monitors became popular because they can adapt to several modes of computer displays. For examples, CGA, EGA and VGA display modes are used in IBM PCs. The three di'splay modes have different horizontal resolutions and scanning frequencies, ranging from 15.7 kHz to 31.5 kHz. Hence, the switching power supply developed in this note can be synchronize to the horizontal scanning frequencies of the mUlti-sync color monitor, as shown in Figure 1. It provides three d.c. outputs. The specifications are: This paper describes the design of a low-cost 90 W flyback switching power supply for a mUlti-sync color monitor. In order to minimize the screen interference from the switching noise, the power supply can be automatically synchronize at the fixed frequency of the horizontal scanning frequency (15 to 32 kHz) of the color monitor. The line and load regulations of the power supply are excellent. Also, a new universal input-voltage adaptor enables the power supply to operate at two input voltage ranges, 90-130 Vac or 180-260 Vac. It can minimize the ripple current requirement of the input bulk capacitors and the stresses on the power switch. The design demonstrates how to use recently introduced components in a low-cost power supply. The state-ofthe-art perforated emitter epi-collector bipolar power transistor MJE18004 and opto-isolator MOC8102 are utilized. 1. INTRODUCTION As the resolution of modern color display increases, the power supply for these high-definition monitors become critical in its features and performance. Nowa- MULTI,SYNC SIGNALS FROM COMPUTER IH & V SYNC RGB SIGNALS, AC LINE -5V ,FOR LOGIC ICsl POWER SUPPLY ·12 v ,AUX POWER' DEVELOPED IN THIS NOTE ·110 V EXT SYNC MULTI SYNC VIDEO PROCESSOR RGB DRIVERS & HV CIRCUIT H SYNC DC ISOLATION Figure 1. Block Diagram of Modern Multi-Sync Color Monitor 315 HIGH RESOLUTION MULTI-SYNCH COLOR DISPLAY Outputs + 110 V 0.7 A + 12 V 0.3 A +5V 0.2 A for HV, RGB drivers and deflection. for auxilary use. for logic ICs. Inputs 90-130 Vac or 180-260 Vac 4, the performance and further improvements of the power supply are discussed. In the last section, the con· clusions include a summary of the design of the power supply and the future developments of switching power converters suitable for multi·sync monitors. 50/60 Hz Power 90 W with overload protection 2. DESIGN OF THE FLYBACK POWER SUPPLY Conversion Efficiency Minimum 70% at full load 2.1 TOPOLOGY SELECTION Others External synchronization with d.c. isolation (15 kHz to 32 kHz) which are regarded power supply standards for modern color monitors. The two low·voltage outputs are obtained by post-regulators of the + 15 V and +8 V inputs. In Figure 2, the block diagram of the switching power supply, according to the specifications, is shown. Besides the input filter, it mainly consists of three parts - the rectification circuit, the universal input-voltage adaptor and the 90 W flyback converter. The universal input-voltage adaptor can automatically select the input·voltage range and controls the triac in order to provide the rectified d.c. voltage Vee in between 200 to 370 V. In 90-130 V range, the triac is continuously fired and the whole rectification circuit forms a voltage doubler. In 180-260 V range, the triac turns off and the rectification circuit works as normal. This design can significantly reduce the current ripples ofthe two smoothing capacitors, Cin, and the switching stresses on the power transistods) due to wide range of Vee. Some previous designs without the universal adaptor handle the full input-voltage range only by simple bridge rectification. The current ripple of the smoothing capacitors are usually several amperes for 90 W power converters. Furthermore, the output voltage ripple (at VCC) is generally higher for the same value of smoothing capacitors at low line. In section 2, the design of the flyback converter is reviewed, whereas the design of the universal inputvoltage adaptor is given in section 3. Then, in section The single-ended discontinuous-mode flyback topology is selected to perform the major power transfer from the rectified output (Vee) to the load. Advantages and disadvantages of this topology are: Advantages 1. It has smaller transformer size and output choke. The power density and cost of the power supply are lowered. 2. Current mode operation is excellent because the current waveform fed to the current mode controller is strictly triangular. It can improve the noise immunity of the current sensing circuit. 3. Single-pole roll-off characteristic of the power con· verter simplifies the design of feedback circuits. [1] 4. Simplified in design if single-ended configuration is used. 5. Good cross regulation. [1] 6. The working duty cycle can be greater than 50%. This is particularly important for mUlti-sync monitor power supply. 7. Lower cost than other topologies. Disadvantages 1. High RMS and peak transformer currents result in high losses in power switch, windings and voltage clamp. 2. The large air gap in the flyback transformer causes higher EMI/RFI and flux fringe. 3. Higher ripple current appearing in output capacitors produces greater output ripple voltage which may cause screen interference. The switching frequency of the power supply is designed in synchronization with the horizontal frequency. The adverse effect due to this point becomes less significant. -110 V 90-130 VAC DR 180·160 VAC 10.7 AI INPUT FILTER 90W FLYBACK CONVERTER E--,,-+--"'-~--'-I' _.c; __ /~¢ J M1 = VO 6 "; 10 1_ MTP'N90 '70 :F k Rs 0.18 , GND -8V IVai -110 RopD 1 Rx C, Rv "~ 'F Dop MOC8101 RE 03 1N3906 TL431CLP CONSTANT CURRENT SOURCE Figure Sa. Current-Mode Controller and Sync Circuit for MTP4N90 (MOSFET) 318 If the output ripple voltage is set to 1% of Va' i.e. 1 V, oVa -lOV lN4740A Vcc MOTOROLA UC3843A CS~~--4N~-----+ R, 028 r470PF = 1 = 0.5x5.13x18.2/C o (1101 Coll101 = 46.68 p.F However, the output ripple current 11.55 AI is so large that two or more capacitors are needed to be connected in parallel in orderto lower their individual ripple currents and the additional output ripple caused by ESR and ESL of the output capacitors. As a result, two of 22 p.F to 33 p.F capacitors each with maximum ripple current of 0.8 A are used in the power supply. Their maximum working voltage is 160 Vdc. The dummy resistors Rno, R15 and R8 are used to maintain minimum load currents of the three outputs. Rn 0 is set to 5.6 k!1 and dissipates 2 W. LC filter is cascaded with each output to lower the output ripple voltage. They are shown in Figure 8. The comer frequency for that at + 110 V output is about 6.2 kHz and the approximate output ripple voltage is, OTHERS ARE SAME AS IN FIGURE 5\dl 1/[1 + 115/6.2)4Jl/2 = 0.1684 V Ipeak·to-peak). Figure 5b. Current·Mode Controller and Sync Cir£uit for MJE18004 (Bipolar Junction Transistor) 2.4 SELECTION OF SWITCHING TRANSISTOR, SNUBBERS AND VOLTAGE CLAMP 2.3 DESIGN OF OUTPUT CIRCUITS The following paragraphs describe how to determine the values of output capacitors and to select output rectifiers as shown in Figure 3. The ultrafast recovery rec· tifier MUR140 is chosen for Dll0 due to its fast recovery time 175 nsl, reliability and low cost. The maximum reverse voltage of this diode is 110 + 370 n = 277 V, so 400 V device is selected. The average current of Dno is 0.7 A maximum. D15 and D8 are schottky diodes, MBR160 and 1N5819 respectively, because schottky rectifiers are more suitable for low voltage outputs. During td, the output voltage rises from its minimum value to its peak. !mill.1ill t] td V0- _ _ J-at [I pk I 1101 Co1 (1101 = l-c0(1101 [l pk(1101 t - 110 !mill.1ill 2 td t2] dt ~ Vo(mlnl . + Vo(minl It consists of a linearly increasing term and a convex parabolic curve. Thus, V olmaxl = __ 1_ Co lll01 [I pklll01 t _ !mill.1ill t2] _ 2 td t-td + Volminl - ! l pklll0l t d - 2 Co lll01 + V . olmlnl and output ripple voltage is, oVa = Vol maxi - Volminl _ ! Ipklll01 td - 2 Co lll01 Since the maximum inductor current Ip klll01 at 110 V rail is 5.13 A, and the output ripple voltage is maximum at f s = 15 kHz, td = ti = = 0.273 x 66.67 p.s = 18.2 p's idle time las shown in Figure 41 T - tc - td = 21.8 p.s 319 Two types of power switches are considered for the flyback power supply. They are TMOS power FETs, and the state-of·the·art perforated emitter bipolar transistors introduced in 1988. The new series of Motorola TMOS FETs simplifies the design of driving circuits and provides extremely fast switching transitions. These MOSFETs can operate in the MHz range. In this power supply, although the switching frequency is relatively low, it still provides several advantages such as simple drive circuit. less supply current for the MOS driver, fast switching times which result in less energy loss at switching transitions, and hence a smaller value of snubber capacitor Cl 11000 pF) is required. Since. the maximum drain voltage of Ml is near 850 V Isee later), and the peak drain current is 3.2 A, MTP4N90 is selected for M 1, with 4!1 rDSlon) [5J. Thus, the approximate conduction loss in Ml is [10.4/3)1/2 x 3.2J2 x 4 = 5.5 W at fs = 15 kHz, VCC = 200 V and full load. The power dissipation is well below the maximum power that can be dissipated by the device. To demonstrate the switching improvement of the newly introduced perforated-emitter BJT family, the design of the flyback power supply also provides an alternative for a new device. MJE18004 is chosen for Ml because its breakdown voltage VIBR)CES is above 1000 V, the continuous collector current is 5 A and its switching times are excellent for switchers below 70 kHz Itfi = 70 ns and tsi = 0.6 p.s at IC = 2 A. Ibl = 250 mA and VElEloff) = - 5 V) [6J. Anothertwo important features are its lower cost and power loss than the MOSFET. Its performance is quite different from the previous bipolar transistors. For the triple diffused power transistors, which are still widely used in Japan le.g. BU508). these devices face three major problems: long switching times, dispersion of device characteristics, and hFE degradations after several thousand operating hours. The epicollector technologies which MJE18004 uses, improve the switching speed and control of device characteristics. Since the emitter of BJT affects the device performance very much, various emitter structures have evolved. With Motorola SWITCHMOOE III, with hollow emitter structure, the speed and RBSOA improvements are accompanied by the increased die size (about' 25% of standard technology). For the perforated emitter structure, the emitter is interleaved by the base, thus, this increases the emitter perimeter to area ratio. That means higher speed switching transistor can be fabricated in a smaller die size. It improves the operating frequencies and lowers the cost. In Figure 3, a dissipated RC turn-off snubber is shown. Its function is to reduce the power loss of the transistor M, at turn-off by limiting the rising slope of VOS. It is also called the dV/dt limiter. When M, turns off, the inductor current begins to commutate from the power switch to the snubber capacitor C, through the diode 0, within tfi. The snubber capacitor slows down the increasing rate of VOS, so the VOS Is product area (during cross-over time) can be limited to certain acceptable value. This snubber is particularly important for the old and slow bipolar transistors. With the advents of TMOS FETs and perforated emitter bipolar power transistors, the snubber capacitance can be chosen to be as low as , 000 pF. As the current fall-time of power transistor given in data sheets includes the effect of transistor output capacitance (Cos s ), it is difficult to calculate an optimum value of C, which requires the fall-time information without the effect of Cos s [2].[3J. Theoretically, the charge stored in C, at turn-off should be completely dissipated in R, when the switch M, turns on. However, in the discontinuous-mode flyback power supply, it cannot always have that because severe stray oscillation which is caused by Lp and C, occurs when the energy stored in the magnetic core is completely discharged to the loads. This phenomenon is often seen in previous designs. Therefore, the resistor R, has another function that it acts as a damper for the Lp-C, resonant circuit. Then, a compromise between the two opposing operations should be considered. For a series LCR resonant circuit, the damping ratio can be used to control the envelope of the damped sinusoidal oscillation. From any standard text on linear control systems, Dampmg ratio = R, Ic, iL2 V p this period. Since the discontinuous-mode flyback converter has greater peak inductor current, the effect of leakage inductance can be the dominant source of power loss. As shown in Figure 3, a voltage clamp for the leakage'inductance limits the spike voltage to a designated value, Vspk. In [3]. it points out that voltage clamp is more effective than shunt snubber in limiting the spike Voltage. It is actually a boost converter with an input voltage of approximately nVo and the leakage inductance as switching inductor. From power relation, neglecting the minor effect of the shunt RC snubber, L3 Ipk 2 fs/2 + nVo tspk fs Ipk/2 = (Vspk - VCC)2!R2 for C2R2 » "/f s and from Faraday's law, Ipk L3/(V sp k - VCC - nV o ) = tspk where L3 = leakage inductance in primary side. On substitution, -21 L3 Ipk 2 fs [, + nVo ] Vspk-Vcc-nV o _ (Vspk- Vccl 2 (8) R2 Note that although the above result is similar to that shown in [3]. the leakage inductance which stores energy to be dissipated is merely L3, and the leakage inductances in the secondary side only come into effect between point A and B in Figure 4. The power loss due to L3 is essentially same for all switching frequencies because Ipk 2 fs is constant for same power level and VCC. At '5 kHz, the primary inductance was measured to be 0.15 mH with major secondary winding (110 V output) short-circuited at zero bias current. It is about one-tenth of Lp. So, L3 is equal to 0.15 mH!2 = 75 JLH. If the peak voltage of M 1 is limited to 850 V for MTP4N90, then, 0.5 x 75 JL x 3.2 2 x 15 k x [1 - 244 (850-370-244)J = (850 - 370)2R2 R2 = 19.67 kn (11.7 W) For MJE'8004, Vspk is limited to 950 V and R2 = 33.8 kn (9.95 Wi. Practical values of 20 kn (10 W) and 33 kn (10 W) are used for MTP4N90 and MJE18004, respectively. (7) 2.5 CONTROL, BASE DRIVE AND EXTERNAL SYNC CIRCUITS If the damping ratio is set to " no undershoot below VCC will result. The current-mode control IC selected is the UC3842A or UC3843A. For MOSFET, MTP4N90, UC3842A is used to provide sufficient gate voltage because it is operated at 20 V. The circuit configuration is shown in Figure 5(a). The maximum current-sense (CS) voltage on pin 3 of UC3842A is 0.9 V (minimum) [9J. Hence, the current sensing resistor Rs is 0.9/3.2 = 0.28 n with power dissipation less than 0.5 W. Three' n ('·4 W) and one 2.2 n (1 4 W) are connected in parallel to obtain the required resis· tance. A RC filter (' kn and 470 pF) is added to "kill" the voltage spikes. The corner frequency of the filter is 339 kHz. To be able to synchronize externally, the power supply must have a free-running frequency below 15 kHz. For the simplification of the design and operation of the oscil· lation in UC3842A. a constant current source I, is used instead of a resistor RT. Since the internal current source 12 in UC3842A provides a discharging current of 8.4 mA, Thus, , = 0.5 x R, x (,000pi,.66m),12 or R, = 2.58 kll In practice, a smaller value of R, will increase the discharge rate of C, at turn-on. So, a standard value of 2.4 kll is used. The maximum power dissipation of R, is equal to C, VCC(max)2 f s (max)!2 = 2.2 W, for complete discharge of C, during the conduction time of M,. But, due to the stray oscillation caused by C" Lp and R" the resistor R, should have a power dissipation of 3 W. Another RC snubber of '80 II and 470 pF used in the power supply is to damp the stray oscillation caused by the junction capacitance of 0110 and the leakage inductance [2J. In Figure 4, a high-voltage spike (point A) in VOS is caused by the discharge of leakage magnetic energy in the transformer. The time between A and B represents 320 immunity and stability. Since the output voltage of the error amplifier is from 1.4 (two diode drops) to 4.1 V (1.4 + 0.3 x 3) typically [9]. and Ve is equal to (5 - output voltage of EA), the voltage Ve across RopE is from 0.9 to 3.6V. In the past opto-couplers have suffered from current transfer ratio (CTR) degradation. The main cause for CTR degradation is the reduction in efficiency of the LED within the opto-coupler due to the increase in spacecharge recombination within the diode. Past industry LED burn-in data under accelerated conditions indicated that a 15% to 20% degradation after 1000 hours was not unusual. Of even more concern was the fact that the population also contained "fliers" units through infant mortality mechanisms eventually exhibited degradations approximately 50%. A typical percentage degradation is 40% after 10 5 hours normal operation at If = 25 mAo In 1987, Motorola's Optoelectronics Operation decided to resolve the industry-wide problem of LED light output degradation. They concentrated their efforts to improve and control certain critical LED wafer processing steps and eventually, 5000 hours of accelerated stress burn-in testing shows zero degradation. This means that low degradation characteristics are now achieveable not only on an average (mean) basis, but also that "fliers" can be eliminated. Therefore, the opto-isolator can be regarded as a low-cost, reliable, simple but high performance component to be used in future power supplies. Besides the zero degradation of CTR, the new MOC810X series optocoupler that are specifically designed for switching power supplies provides two additional features. Their specifications include tightly controlled window values of CTR. Also, each device's internal base connection has been eliminated, effectively minimizing the noise susceptibility problem. Noise is further minimized by coplanar die placement, which puts the LED and phototransistor endto-end, rather than one above the other. The result is a mere 0.2 pF coupled capacitance, which minimizes the amount of capacitively coupled noise that is injected by the optoisolator. MOC8102 is selected due to its moderate CTR (from 0:73 to 1.17 at IF = 10 mAl [111. Then, two extreme cases are considered. For the lowest If delivered by TL431, it should provide sufficient coupled current to develop a minimum voltage of 0.9 V on RopE. The operating current range of If is chosen to be 0.5 to 20 mAo For the highest limit ofthe selected If range, i.e. 20 mA, the value of RopE is 3.6 V/0.5 x 20 mAl = 360 0, if CTR is at the lowest value, i.e. 0.5 approximately. Then, nearly whole ranges of CTR and If are covered by the deSign with RopE equal to 360 O. The practical value for RopE is selected to be 390 O. For the determination of RopD, the maximum LED current is considered. Thus, the value of RopD is (8 - 1) V/20 mA = 350 O. A 330 f1 resistor is used in practice. The feedback point is directly taken from the positive terminal of the output capacitors Co (110). This point must be placed before the output LC filter because the filter forms an additional double-pole in the feedback loop. Since the internal reference voltage of TL431 is 2.5 V, the values of Rx and Ry (the voltage divider) are chosen to be Rx = 142 kfl and Ry = 3.3 kfl because, 110 Ry/(Rx + Ry) = 2.5 or Rx/Ry = 43 . the dead time t2 and switching frequency can be determined as follows. :~6andI2 11 = CT - 11 = CT :~6 12 - 11 t1 -11-=12 (12) 11) (9) T = t1 + t2 = 1/fs The hysteresis voltage of the oscillator is 1.6 V. The time periods t1 and t2 are the rise and fall times of the triangular waveforms (VCT). Due to the effect of leakage inductance, other parasitics and snubber circuits at fs = 32 kHz, the dead time t2 is set to 6-8 !JS. Then, if the freerunning frequency is assumed to be 12.5 kHz, t11T = 0.91, 12 - 11 -11- = 0.91 1 - 0.91 or 11 = 0.756 mA and CT = 0.036 /-,F The constant current source 11 is implemented u~ing a single PNP transistor 03. The current gain of 2N3906 is about 200. The current through RB1 and RB2 is assumed to be 20 x IB3, and the emitter voltage is set to 4 V since the peak voltage of VCT is 3 V. Then, we have, RE = 1/11 = 1.32 kO = 0.756 mAl200 and IB3 = 4 IJ-A. Since VB3 = 5 - 1 - 0.7 = 3.3 V, 5 x RB2/(RB1 + RB2) RB1/RB2 = = 3.3 0.515 RB1 = 20 kO and RB2 = 39 kO The practical values for RE and CT are 1.2 kO and 39 nF, and the free-running switching frequency is around 13 kHz. The constant current source 11 can be directly replaced by Motorola current regulating diode (1 N5294), which is a JFETwith gate-source short-circuited. The regulated output current is actually its saturation current lOSS at pinch-off. The external synchronization is achieved by the oneshot triggering circuit built around 02. It is active once when the falling edge of sync pulse appears. Then, a single high pulse of 2 to 3/-,s charges the timing capacitor CT through the charging resistor RC at a very fast rate (about 50-100 times the normal rate). The value of RC can be calculated by, (5 - 2.8 - 0.5) ! (100 x 0.756) = 47 0 The minimum voltage drop on RC is approximately 5 2.8 - 0.5 = 1.7 V because VCT swings between 1.2 to 2.8 V, with respect to ground [9]. and the saturation voltage of 02 is about 0.5 V. The choices of the input capacitance and BE resistance can vary the pulse period. The anti-parallel BE diode, 1 N4148 is to prevent the BE junction from possible avalanche breakdown if the amplitude of V sync is above 5 V. It is also possible to combine the sync circuit into the constant current source by injecting the sync signal into the base of the current source transistor. The feedback scheme is selected as follows. A voltage reference with comparator (linear error amplifier) TL431 detects and amplifies the error signal, and drives the LED of the opto-coupler MOC8102.. The gain of the error amplifier (EA) in UC3842A is set to unity for better noise 321 The gate drive circuit consists of a series 10 n resistor to minimize the "gate ring" problem. But for MJE18004, the base drive circuit is not as simple as that for MOSFET. It is shown in Figure 5(b). The supply voltage of the current-mode controller is lowered to 10 V in order to minimize the power loss in base drive circuit, and meanwhile, UC3843A is used instead of UC3842A, which has a lower ON threshold of supply voltage. Other functions are identical to UC3842A. The typical hFE value for MJE18004 is 14 [6], and thus, it is assumed that the minimum hFE value is 10 partly because of the tight control in manufacture. Then, the minimum base current IB is 3.2/10 = 0.32 A to maintain transistor saturation at full load. A slightly larger base current of 0.35 A is used practically. From [9], the voltage drop on the source output transistor of UC3843A is about 2 V at an output current of 0.35 A. And the value of VBE(sat) of MJE18004 is 0.95 V [6]. Therefore, the value of base resistor RB is, RB = (10 - 0.95 - 2)/0.35 = 20 n (1.2 W) The base drive capacitor CB can be determined by 11 (21TCSRB) '" f s (min)/2, i.e. CB = 1 J.LF. Note that the BE junction ofMJE18004 will not have avalanche breakdown because the breakdown voltage of BE junction is about 9 V. Other optimum base drive circuits can be found in [7] (e.g., how to use base inductor to improve the turnoff operation of power transistor). As shown in Figures 3 and 5, the primary control circuitry is self-supplied. The required power is delivered from the transformer winding NA through DA and RA. A zener diode of appropriate voltage rating is used to reg· ulate the supply voltage for IC1' For UC3842A and MTP4N90, the supply voltage is 20 V and the total supply current is about 20 to 50 mA. Thus, NA is chosen to be 18 turns to provide an extra 5 V for regulation. RA is set to 47 n. Th smoothing capacitor CA is for filtering, but an unobvious effect of its capacitance is on the start-up transients of the primary control circuitry. Since the cur· rent-mode controller UC3842A13843A has a voltage hysteresis in under-volt lockout, the capacitance of CA must be large enough to maintain the initial switching operations, i.e. the supply voltage must be kept above the lower threshold point, before the power can be fed from the transformer. The practical values of CA are 3.3 J.LF for UC3842A and 2200 J.LF for UC3843A. The much larger capacitance used in the latter case is due to the small hysteresis of the supply voltage of UC3843A and the rei· atively large base current. NA and RA for MJE18004 are 13 turns and 10 n (1 W) respectively. It is also possible to minimize the value of CA to several J.LF and to avoid long start time using a "kick" starter described in previous Motorola Application Notes. The "kick" starter is actually a NPN high voltage, small-power transistor connected as a simple voltage regulator for the control circuit. The reference voltage is derived from a zener diode biased by a resistor connected across + VCC and the base of the "kick" transistor. Its emitter is regarded as output of the regulator and its collector can be tied to + VCC. When the power supply is connected to a.c. mains, the "kick" starter charges CA above the start-up threshold of UC3842A13843A quickly. Then, the power for the control circuitry is fed from the auxiliary windings (NA), which raises the d.c. voltage at the emitter of the "kick" transistor, and the transistor will be turned off. Thus, the "kick" transistor conducts for a very short time and dissipates very small power. 2.6 CLOSING THE FEEDBACK LOOP After determination of almost all the component values and configurations for the flyback power supply, the last but not the least piece to design is the feedback loop. Figure 6(a) shows the gain-block diagram of the flyback power supply. The input of the system is the internal reference voltage in the TL431 , which is 2.5 V ± 1%, and is compared to the feedback signal. The H-block is purely FORWARD GAIN BLOCK IGI ERROR AMP Vref ·2.5V VOLTAGE DIVIDER IR, & Ryl Ho = 0.0227 Figure 6a. Approximate d.c. and Low-Frequency a.c. Model of the Flyback Power Supply 322 a voltage divider formed by Rx and Ry , thus the gain value in this block is 3.3/(142 + 3.3) = 0.0227 = Ho. The difference or error signal is then amplified by the error amplifier in TL431 , which is compensated externally. The compensation network is chosen to consist of an integrating capacitor Cf and a resistor Rf. Thus, we have, RopE = 390 n RopD = 330 D CTR = 1 (for MOC81 02) Rs = 0.28 D Lp = 1.66 mH, we have, IGol = 229 or 47.2 dB It is observed that a local feedback occurs in the TL431 output circuit and the LED of the opto-coupler. Its end effects are: 1. loop-gain enhancement by the additional block connected in parallel with A-block, i.e. 9/(111 Ho) = 3.57; 2. a proportional-integral (PI) controller resulted, instead of a pure integrator. The overall gain (transconductance) of the feedback error amplifier can be derived as follows. A=~ (10) SCfRf where s = Laplace transform operator Ow for sinusoidal analysis), Rf = RxRy/(Rx + Ry) = 3.23 kD. The capacitance value of Cf can be determined for overall stability of the power supply once when the forward gain G is known under the worst condition. The low-frequency a.c. model for the discontinuousmode current-injected flyback converter consists of a d.c. gain block cascaded with a single-pole roll-off network which has a pole frequency at 1/( nCoRL). where Co is the total output capacitance and RL is thetotalload resistance at Vo [1]. The equivalent maximum load resistance RL(max) is approximated by experimental measurements at no load, fs = 32 kHz and VCC = 200 V (for MTP4N90). The input current was measured to be 0.06 A and thus, RL(max) = 110 2/(200 x 0.06) = 1 kD iF = Vo (9/111) - Vo Ho A = [9/(111 Ho) -AI Ho Va (13) or iF/(H o Vol = 9/(111 Ho) - A where vo = a.c. component of Vo iF = a.c. component of IF (LED current). To simulate the equation (13). an additional block consisting of 9/(111 Ho) only is placed in Figure 6(a). The zero frequency of the error amplifier is, wf = 1/(3.57 CfRf) when IAI FQ,r the equivalent total output capacitance (for MTP4N90), the capacitances at three output circuits are lumped to + 110 V output, and by charge relation, = (14) 9/(111 Ho). After knowing all equivalent a.c. gains of the converter circuit, we can determine the value of Cf for optimum circuit dynamic performance. Since there is merely one Co = [(110 V) (66 ILF) + (15 V) (330 ILF) + (8 V) (470 1L)]110 V = 145ILF Ip Hence, the lowest corner frequency fp of the flyback power supply is approximately 2.2 Hz. If the ESR and ESL of the output capacitors are neglected, the G-block has a transfer function [1] as, G=G o (l-sWp) where Wp = 2rrfp = 13.8 rad s. = ~ Lp I 2 k2 f P ~ 10 Hz tr ~ 40 Hz r-... r--. ~40 --90 1000 Hz IIkl 001 V " s ~ or Vo = iLp RL fs Ipk ~~2Thus, Go = - (RopE/RopD) (CTR) JRL Lp fs 3 Rs 2 2.2 Hz II (11) The forward gain block G is subdivided into its individual elemental blocks in Figure 6(a). They are the resistor RopD which converts the output voltage of TL431 into the diode current for the LED of MOC8l 02, the non·linear CTR (0.65 to 4.5 from data sheet), the resistor RopE which generates a voltage Ve from the coupled current IC, the internal one-third divider of UC3842A13843A (the minus sign is due to the inverting configuration of the op amp), the current sensing resistor Rs which relates Vc to Ipk' and finally, the gain of the power stage which includes the signal pole. The d.c. gain of the power stage can be directly derived from the power relation. V0 2 RL ~ 100 II 1\ (12) The value of d.c. gain Go can be determined analytically by substituting parameters under worst case, i.e. fs = 32 kHz and RL = 1 kn (including +8 V and + 15 V rails). when the value of Go is highest. On substituting the known parameters. 13 5 Ilkl 001 1000 Hi Figure 6b. Bode Plot of the Flyback Converter at fs 32 kHz and No Load = 323 parameter that can be varied, i.e. Cf, and only one optimum condition (either gain or phase) can be satisfied, we set the minimum phase of the loop gain to -120° to guarantee the relative stability. That means Wf should be placed 30/45 = 0.667 decade beyond Wp or, Wf = 100 .667 Wp = 4.64 Wp = 64 radls diode lN5953A (1 W) is connected across the 110 V output rail. If abnormally high voltage (>150 V) continuously appears on this rail, the zener diode will be zapped to form a permanent short-circuit. Other better OVP circuits such as SCR crowbar circuit and 0 V shutdown circuit can be used with higher unit cost. Another option which may be required in the power supply is short-circuit (not just overload) protection. Since the fly back power converter is operated with current-mode control, it is inherently over-power protected. But, if the outputs are short-circuited, maximum power will be delivered to the low voltages with high output currents. Then, the output rectifiers and windings are likely to be' damaged. Short circuit protection is generally best installed in secondary output(s). Shutdown or foldback signal(s) can be fed to the UC3842A13843A by a Motorola optocoupler. To improve and control the start-up transients, a softstart circuit may be added to the current-mode controller. Typical example can be found in [91. because the down slope of the phase of the flyback converter gain is - 45°/decade and the PI controller has an initial phase shift of - 90°. Then, Cf = 1/[(3.23 k) (3.57) (64)1 = 1.355 p.F A practical value of 1.5 p.F is used. Plots for the overall loop gain of the power supply at fs = 32 kHz and minimum load is shown in Figure 6(b), with the following equations. A (f) = _1_ + _9_ = 206.4 + 3.57 SCfRf 111 Ho JW G=~ where Go = 229 Wp = 13.8 1 + slWp 3. UNIVERSAL INPUT-VOLTAGE ADAPTOR Ho = 0.0227 Gain (f) = 0.2 1091O I A' (f) x G x Hoi The universal input-voltage adaptor is used with bridge rectification circuit to provide a rather narrower range of rectified d.c. output voltage at either low or high range of input voltage, i.e. 90-130 Vac or 180-260 Vac. A simplified circuit block diagram has been shown in Figure 2, and the detailed circuits are shown in Figure 7(a) and (b). The voltage range selection is performed by an overvoltage detector and the adaptor is supplied from a charge pump circuit. At low range, the triac is fired continuously by the adaptor, and a voltage doubler is formed, while simple bridge rectification is retained at high range. The rectified output voltage (VCC) range is from 200 to 370 Vdc. Phase (f) = Arg[A' (f) x G xl HoI The unity gain bandwidth is about 40 Hz (at fT) and the phase margin is about 82°. But, the dominant value in the phase plot is its lowest value of - 128° at wf, where the gain is greater than 0 dB. It determines nearly all transient load responses. 2.7 OTHER OPTIONS Under normal circumstances, the output voltage should not exceed 150 V. But, as protection for the monitor circuits (it would generate X-ray if extremely high anode voltage appears). an optional high-voltage zener - VCC 1~5956A '~5956A 11'\ 90-130 VAC OR 180-260 VAC 10 IN4001 MTI T2 IN4735A 4K7 10k 62 V MC3423P 30k 1'00 IN4001 560k Figure 7a. Negative Gate (Triac) Current - 324 Preferred L - - - - - - O START UP . - - - - - - - - - -.......-.---..--- 200 V//lS) and hence, the overall system reliability [131. = 191 x R2/(Rl + R2) or Rl/R2 = 72.5 Rl = (2Vp) C = IT = (IT)I(2Vp) = 2.2 Mn and R2 = 30 kn. The internal constant current source (pin 4) can provide a time delay before tripping the "crowbar" SCR. It results in better noise immunity and controlled start-up transients of the adaptor. The practical values of the capacitor and resistor connected at pin 4 to ground are 50 nF and 560 kn, respectively, which has a time delay of approximate 650 !,-S. The output is connected, through a resistive divider, to a small-power SCR (MCR102 with IK(max) = O.S A). When the input voltage is detected to be above the trip point, the SCR is fired to shunt all the incoming current from the charge pump, and the triac will remain off. The MC3423 can operate from 4.5 V to 40 V of supply voltage [151. Hence, a 6.2 V zener diode is used to clamp the supply voltage of the crowbar senser to 6.2 + 0.7 = 7 V for stable operation. A 100 pF filtering capacitor for the sensing divider and a small-signal diode lN414S for clamping the input of MC3423 are also added in the circuit. HAZARDOUS RANGE FOR VOLTAGE DOUBLER Figure 7e. Worst Case Consideration for the Universal Input-Voltage Adaptor (Negative Gate Currentl 327 4x lN5398 r----------------------------, I 2A ~: ~~: i lo-~~--q ~~~~-< 9O-IJO VAC OR 180-260 VAC 50160 Hl 270k lW No---~~------~~~~ i ' - - - - - _ < > START·UP I I I E ~ THE DEM~~O~~-----------------J T1 MAC229AB ....... _________ ..J lN4001 r-~~-+~~------------~------~~~~~~ UNIVERSAL INPUT·VOlTAGE ADAPTOR 100"F 25V + 10k lN4735A 560k Vce 180 ..;..110 V ......--o 10.7 AI +-.r--rt~-.,....""",,-..,...- 20\ lK2 lN595JA IOPTIONAll '---~~~~-----+--+~_<>OV l' r-~~H-~~~'-~-----+_<>+15V O.l~ 10.JAI '-~~~~------+------+_<>ov r-~~~_~~vv~~~-+_<>+8V 10.2 AI '-~~~--~------+--+-+_<>OV 10 142\ I', 1\ ~470PF 0.28 0.5W JJO MOC8102 * 1~5 START·UP MJEI8004 ICI 0.28 FOR ICI RA CA DZ NA Start-up R2 MOSFET Bipolar MTP4N90 MJE18004 UC3842A 47 3,,325 V lN4747A 18T 20 V 20 k UC3843A 10 2200" 16 V lN4740A 13T 10 V 33 k (lOW) 3KJ 1°'0 Tl4J1ClP ____ J HEATS!NK Figure 8. Complete Circuit Schematics of 90 W Off-the-Line Power Supply 328 The determination of the capacitance of CG is determined as follows, with reference to Figure 7(e). At high line, high range, and 60 Hz, the average current I is maximum (53 mAl. All discussions below are referred to a falling edge and the consecutive rising edge of less than 1/4 cycle of input voltage, because the charge-pump capacitor C is discharging to the adaptor circuit during fall time and the crowbar senser cannot be tripped if Yin falls beyond + 200 V. If the supply voltage for MC3423 is just about 4.5 V, the crowbar sensing IC functions, and meanwhile, the instantaneous input voltage is at the trip point (200 V) and is going to the negative cycle, the gate capacitor CG must be large enough to delay the conduction of the triac before the input voltage rises again, i.e. at the negative peak. Assume that, for simplicity, the supply voltage of MC3423 rises to about 6.2 V (zener voltage) when the input voltage falls to - 200 V. Then, 4. PERFORMANCE OF THE FLYBACK POWER SUPPLY 4.1 COMPLETE CIRCUITRY Figure 8 shows the complete circuit schematic of the 90 W flyback power supply. The triac in the universal adaptor is negatively driven by the charge pump, since TOP VIEW C C N N L NC Figure 9a. Universal Input-Voltage Adaptor (+ IG) tx = charging time of the capacitor across the supply voltage of MC3423 TOP VIEW = 2 x sin -1 (200/367) 1 (2". x 60) = 3 ms = (6.2 - 4.5) V x (Capacitance value) 1 (53 - 6) mA or capacitance value = 100 /LF (connected across supply voltage of MC3423) But this capacitance is necessary to meet the ripple voltage requirement of the adaptor circuit. Afterwards, the zener diode (1 N4735A) conducts, and the two capacitors connected in parallel are needed to delay the remaining time ty before the input voltage rises from its negative peak again, within the same negative cycle. Therefore, ty = (16.67/4 - 3/2) ms = 0.7 V x (CG + 100) /LF/47 mA NC Figure 9b. Universallnput·Voltage Adaptor (-IG) since the threshold gate voltage of MAC229A8 is 0.7 V typically. CG = 79/LF A practical value of 100 /LF is used in Figure 8. Note that the discharging current of C at zero-crossing of input voltage is greater than the average value I. The time constant of the gate capacitance and gate resistor (1 kn) is 0.1 s, which is sufficient for resetting the triac between consecutive power-off and on. The 10 kn resistor is for discharge of the 100 /LF capacitor, and the corresponding time constant is 1 second. Time constants too long in the above design may result in failure of the universal inputvoltage adaptor if the power supply which was previously socketed in 110 V line is quickly plugged in 220 V line. It should be noted that two optional power zener diodes (1 N5956A) are connected across each bulk capacitor Cin because: 1. they can absorb short transient voltages (>200 V) on Cin, 2. they can prevent any failure of the universal inputvoltage adaptor from damaging the flyback converter and the two bulk capacitors. Although such failures are rare the consequences are to be avoided since failure of the line adaptor poses a safety hazard to the human beings (especially the eyes radiated by X·ray). Common-mode and differential-mode EMI/RFI filters are generally required for all switching power supplies. They are included in Figure 8, but are excluded in the DEMO board. N.B. VALUE, VALUE FOR fOR fET BIPOlAR UC3841A. UC3843A 1N3906, 1 MOTOROLA HK 1·8·89 Figure 9c. Main Board (for MTP4N90 & MJE18004) Figura 9. PCB and Componant Layouts (not full size) 329 TRANSFORMER CONSTRUCTION DIAGRAM BOnOMVIEW L,11101 N,I1101 = 77 AWG#11 lp = 1.5tol.75mH Np = 171 AWG #13 10iBI N,IBI = 7 AWG #16 • L,I151 N,I151 = 11 AWG #16 N,11101 . I PRIMARY·TO· SECONDARY • Np INSULATION ' I.1....-_ _ _ _---'-, NA LA NA = 18 AWG #16 If01 MTP4N9fl1 = 13 AWG #16 If01 MJE1BOO41 F 1F['"==~==-====1IN'IBI N,I151 CENTRE LIMB OF FERRITE CORE FERRITE CORE: TDK ETD·39 H7C4 BOBBIN: TDK PST·39 AIR GAP. 19 • 4mm APPROX. Figure' O. Flyback Transformer Construction 4.2 EXPERIMENTAL MEASUREMENTS AND RESULTS it is least sensitive to noise in this mode. Drive circuits for MTP4N90 and MJE18004 are also shown. Sometimes, it is unnecessary to have the universal input-voltage adaptor because the power supply may be used only at one range. Then, a modular approach for the adaptor can lower the system cost and can increase the flexibility of manufacture. The universal input·voltage adaptor board can be simply removed or unplugged from the power supply board without affecting the normal operation of the power supply, if the adaptor is not needed. Therefore, using this approach, the adaptor becomes optional. The printed circuit board and com· ponent layouts of the universal input-voltage adaptor(s) and the main board of power supply are shown in Figure 9. The construction diagram of the power transformer is shown in Figure 10. Table 1 lists all Motorola semiconductor components used in this power supply. D.C. measurements are summarized in Table 2. Line and load regulation are excellent (better than 0.5%) for the + 110 V output. Regulation for other two rails is within 10%, if the transformer is properly manufactured. Conversion efficiency, is close to the expected figure (70%), and the best one is 73.7% at 10 (110) = 0.7 A, fs = 15.7 kHz and VCC = 360 V for MTP4N90; whereas for the bipolar power transistor MJE18004, the best efficiency is 74.2% at 10 (110) = 0.7 A, fs = 15.7 kHz and VCC = 360 V. Although MJE18004 has lower conduction loss than MTP4N90, it has higher power losses in the base drive circuit and in the switching transitions. This is why MOSFETs can compete with advanced BJT even with higher conduction loss at relatively low switching frequency. The maximum ripple voltage at 110 V output is approximately 150 mV (peak·to-peak) which is less than 0.2% of the output voltage, as predicted in section 2.3. The power supply is observed to be stable over the entire range of load currents. The dynamic response is also satisfactory, with an overshoot of less than 8 V at fs = 15.7 kHz and VCC = 200 V, from half· load to full-load (see Figure 1). Also in Figure 12, the transient responses of the power supply are introduced for very large-signal disturbances - from no load to full-load. The overshoot is about 20 V and the undershoot is over 30 V, which is quite satisfactory. The overshoot can be further reduced by increasing the integrating capacitance Cf in the feedback loop. But, this will result in slower transient responses. Typical experimental switching waveforms are shown in Figure 11, at different load currents,·input voltages and switching frequencies. Also, Figure 13 shows the photo of the 90 W off-the-line power supply. Table ,. list of Motorola Semiconductor Components Part Numbers Qty. UC3842A (for MTP4N901 UC3843A (for MJE180041 MC3423P TL431CLP 1 1 1 1 Opto MOC8102 1 MOSFET MTP4N90 1 SCR MCR102 1 TRIAC MAC229A8 1 BJT MJE18004 2N3906 1 2 Rectifier 1N4001 1N5819 1N5398 MUR140 MUR180 MBR160 2 1 4 1 2 2 1N4735A 6.2 V 1N4740A 10 V (for MJE180041 1N4747A 20 V (for MTP4N901 1N5953A 150 V (optionall 1N5956A 200 V 1 1 1 1 2 IC Zener 5. CONCLUSION A low-cost 90 W flyback power supply with external synchronization and universal input-voltage adaptor for mUlti-sync color monitor has been discussed in detail. The power supply has excellent line and load regulation and is found to be suitable in the application of low-cost mUlti-sync color monitors or TVs. Also, it can operate at both a.c. mains, i.e. 90-130 V or 180-260 V, without greatly affecting the system cost and performance. 330 Table 2. Performance of 90 W Off-the-Line Flyback Power Supply MTP4N90 (MOSFET) (15 V) 0.2 0.5 0.7 V o (11DV) 110.1 110.0 109.9 109.9 109.9 110.1 110.0 110.0 110.0 109.9 110.1 110.0 110.0 0.7 0.7 110.0 110.0 16.24 16.23 (B.DV) 8.88 9.05 9.10 9.10 9.10 8.88 9.03 9.08 9.07 9.08 8.88 9.03 9.07 9.07 9.97 Efficiency 61.2 70.5 73.3 0.13 0.26 0.35 Vee 300 300 300 200 360 300 300 300 200 360 300 300 300 32.0 32.0 0.53 0.30 200 360 12.6 71.3 A V V V kHz A V % 10 (11DV) (15V) (8.DV) 14.41 14.65 14.82 8.82 9.00 9.11 0.7 0.7 Vo (110V) 110.8 110.7 110.6 110.6 110.6 Is 15.7 15.7 15.7 lin 0.12 0.26 0.35 Vee 300 300 300 Efficiency 14.73 14.83 9.06 9.11 15.7 15.7 0.54 0.29 200 360 71.7 74.2 0.2 0.5 0.7 110.8 110.8 110.7 14.44 14.70 14.78 8.83 9.02 9.09 25.0 25.0 25.0 0.13 0.27 0.36 300 300 300 56.8 68.4 71.8 0.7 0.7 110.7 110.7 14.77 14.78 9.08 9.09 25.0 25.0 0.53 0.30 200 360 73.1 71.8 0.2 0.5 0.7 110.8 110.8 110.7 14.43 14.68 14.75 8.83 9.01 9.07 32.0 32.0 32.0 0.13 0.27 0.36 300 300 300 56.5 68.4 71.8 0.7 0.7 110.7 110.7 14.75 14.75 9.07 9.08 32.0 32.0 0.54 0.30 200 360 71.8 71.8 A V V V kHz A V % 10 (11DV) 0.2 0.5 0.7 0.7 0.7 0.2 0.5 0.7 0.7 0.7 16.01 16.23 16.31 16.32 16.30 15.99 16.19 16.25 16.26 16.25 15.98 16.17 16.23 Is 15.7 15.7 15.7 lin 0.12 0.26 0.35 15.7 15.7 0.55 0.29 25.0 25.0 25.0 0.13 0.26 0.35 25.0 25.0 0.53 0.29 32.0 32.0 32.0 69.9 73.7 56.5 70.5 73.3 12.6 73.7 56.5 70.5 73.3 MJE18004 (Bipolar) 0.2 0.5 0.7 -1 ETPROBE H660 / 300pF 'J; Offset =1.912 Volts Delay = 16.0000 ns Delta V = 6.1250 Volts = 20.0 nsfdiv = 0.0000 Volts -\ - - - Ll- -- - - = 2.00 mVoltsJd,v Ch.4 TImebase Vmarkerl tor, the output will go all the way to each rail and will not discharge in a cycle time period. An example ofthis phenomena is shown in Figure 8. Vmarker2 = 6.1250 Volts Figure 8. When driving a resistive load it is seen on the chart in Figure 9 that the VOH level remains somewhat constant over IOH loads that are over the device rating. 3.8 3.7 \ \ 3.6 :I: \ \ ---... 93.5 3.4 3.3 3.2 o 20 -- As a precautionary note, if an output is being used without the series resistor and if it becomes shorted to ground while in a high state, it will source over 700 mA and in a short period of time the device will be destroyed. After the proper memory addresses are selected and the TIL data is transferred from memory the data is then translated back to ECl by use of a TTL to ECl translator such as a Motorola MC 1OH/I 00H600, 602 nine bit TIL to ECl translator or a MC10124 or MC10H124, 4 bit translator. CONCLUSION r-., 40 /VOH -r--60 IOH 80 - 100 Mixed technology systems are becoming very popular where system designers must optimize system performance while keeping overall system cosUpower in line. This application note described the MCI OH/I 00H600 4-BIT ECl-TIL lOAD REDUCING DRAM DRIVER and some application techniques that can result in an improvement in system performance and reliability. Figure 9. VOH versus IOH 338 AN1106 Considerations in Using The MHW801 and MHW851 Series RF Power Modules by Norm Dye and Mike Shields RF Products Division prevent low-level Impedances that result in signal feedback with consequent module instabilities. Remember that the back of the circuit substrate is ground and this is soldered to the module flange which then becomes the ground connection to external circuitry. Third, the board layout should be such that isolation of input lines from output lines is at least 50 dB. Normal use of the module is to amplify CW signals that are frequency modulated. The first two stages of the module are biased Class A; however, the last two stages are biased Class C. Significant distortion will result if the signal contains amplitude information, such as amplitude modulation. However, it is possible to operate the module in less than a CW condition. In a pulse mode of operation, any duty cycle up to 100% should create no problems provided the peak power does not exceed the rated CW output power of the module. Note, however, that case temperature can no longer be tied to die temperature by the same constant difference used for CW operation. The thermal time constant of the die is approximately 10 micro-seconds which says that for moderately long pulse trains with low duty cycles, die temperature could be much higher than that predicted from CW measurements. The modules have not been characterized for pulse power operation. It is to be assumed that greater than rated CW output power can be obtained from the module in a pulse mode of operation; however, this is not recommended without first consulting the factory because of concern for maximum voltage swings as well as maximum die temperature. INTRODUCTION The MHW801/851 Series of power modules are designed primarily for applications in cellular portable radios. The -1 module is frequency compatible with the American system called AMPS; the -2 module is frequency compatible with the European TACS system; the -3 module is frequency compatible with the Scandanavian system called NMT; and the -4 module is frequency compatible with the NTACS system in Japan. Other than frequency of operation, all models of the MHW801 and MHW851 are identical and meet the general electrical specifications set forth on the data sheet. The only difference in the MHW801 and MHW851 Series of modules is the flange design. In the case of the MHW801, the flange does not extend any appreciable distance beyond the PCB substrate/cap and it is intended that mounting to a heatsink will be accomplished by attaching the flange to the heatsink with solder. The MHW801 modules are considered to be surface mount modules. The MHW851 modules were introduced to offer similar modules with the more conventional method of mounting. The flange extends beyond the substrate/cap and attachment to a heatsink is intended to be by means of mounting screws. A significant amount of applications information is contained in the MHW801/MHW851 Series data sheet. Also included are a block diagram of the module and decoupling networks used in the test fixture; typical performance curves showing parameters such as VCont, efficiency, input VSWR and output power as functions of frequency; and output power and VCont as functions of temperature. GENERAL ELECTRICAL CONSIDERATIONS NOISE CHARACTERISTICS Modules are matched to an impedance of 50 ohms for both input and output. Thus their application in a SUb-system such as the transmitter portion of a portable radio is relatively straightforward. However, there are certain precautions that should be observed. First, it is important that DC inputs to the module be de-coupled by means of by-pass capacitors and/or chokes to prevent bias and power supply circuitry contributing to circuit instabilities (spurious oscillations). It is recommended that the module user pay careful attention to the decoupling information presented in the data sheet. Second, grounding of the module should be adequate to One parameter of power modules frequently not specified is noise. Most applications of power modules have been in radios where transmitting and receiving did not occur simultaneously. Today, cellular radios are duplexed, i.e, they are capable of transmitting and receiving at the same time. Thus radio manufacturers are concerned about the noise characteristics of the transmitter in the receive frequency band, which is normally 45 MHz above the transmit frequency. For this reason, Motorola has begun to characterize and guarantee noise performance of modules designed primarily for use in duplexed cellular radios. 339 The block diagram for noise measurements is shown in Figure 2. Several comments about the block diagram are in order. First, the signal source must be extremely low noise, as close to kTB noise as possible. The HP8614A signal generator uses a cavity oscillator and satisfies the requirement of low noise. On the other hand, a frequency synthesized source such as the HP8656 (or Wavetek 2520A) signal generator does not. If this type of signal generator is used to make noise measurements, it is necessary to add a bandpass filter which will reject any signals 45 MHz above the output frequency. Noise power for the MHW801/851 Series modules is guaranteed in a 30 kHz bandwidth, 45 MHz above fo . This is shown visually in Figure 1. Note that the noise is specified for two widely different temperatures and for rated output power only. A characteristic of the MHW801/851 Series modules is that the small signal (noise) gain of the amplifier is approximately 35 dB at rated output power but increases by as much as 3 dB as the control voltage (Veont) is decreased. POUI 11 TRANSMIT SIGNAL (806-940 MHz) / 30 kHz RECEIVE BAND /MAXIMUM NOISE POWER -::a5dBm-FREQUENCY Figure 1. Noise Power In Receive Band A. SIGNAL SOURCE B. 20 dB NARDA DIRECTIONAL COUPLER C. UNIT UNDER TEST D. 20 dB NARDA DIRECTIONAL COUPLER E. CIRCULATOR IN FREQ BAND OF OPERATION F. 50 OHM LOAD G. TELONIC FILTER H. TELONIC FILTER I. HP 71000 SPECTRUM ANALYZER J. HP POWER METER K. HP POWER METER L. 10 dB INTERNAL ATIEN. M. 6 dB PAD Figure 2. Block Diagram For Sideband Noise Measurement 340 Remember that any noise at the input of the MHWS01/S51 Series module is amplified by approximately 35 dB. This noise amplification should not be confused with internally generated noise which could be caused by a high stage noise figure or by regeneration in one of the module stages, neither of which is a factor in the MHWS01/S51 Series module design. Second, it is essential that the module be terminated in a circulator which will prevent out-of-band impedances of the subsequent RF network from affecting the stability (and, thus noise) of the module. Third, care must be taken to prevent the carrier frequency from saturating the input stages of the spectrum analyzer used to measure the noise level. Again, it is critical in accurate noise measurements to be certain that the sensitivity of the spectrum analyzer be at least 10 dB better than the noise level being measured. Normally to accomplish this it is necessary to reduce the resolution bandwidth (RBW) of the spectrum analyzer to 30 kHz and set the video filter to 100 Hz bandwidth. The manufacturer (Hewlett Packard) of the spectrum analyzer recommends a video bandwidth 100 times less than the RBW for best noise averaging. The filters, "H" and "G" (in Figure 2) are stagger tuned to obtain adequate selectivity for rejecting the carrier frequency at the input to the spectrum analyzer. Obviously a single filter can be used if it has a rejection level of approximately 60 dB, 45 MHz away from the bandpass of the filter. The actual rejection needed depends on whatever is required to prevent saturation of the spectrum analyzer by the carrier signal. istics, efficiency and harmonics will degrade at reduced output power. As output power is reduced, the class C stages of the module operate further and further from their optimum load line resulting in significantly poorer efficiency. As their operation approaches the more non-linear region of the transistor transfer function, noise will likely increase and harmonics will increase with respect to carrier power. Generally these degradations in performance are not serious because they are relative to carrier power level. For example, efficiency becomes much less at output power levels of 100 mW; but current drain is much lower than for the case of 2 watts of output power, so this is generally not considered a problem in radio applications. Other circuit considerations external to the module that are sometimes overlooked are source and load impedances. Note that the stability of the module is guaranteed only for source VSWR's of 3:1 and load VSWR's of 6:1. Frequently the load for the module is the transmit portion of a duplex filter. The out-of-band impedance presented by the filter can affect the stability of the module. The impedance reflected to the module depends on the length of transmission line between the module and the filter thereby causing line length to be an additional circuit consideration. It should be remembered that the MHWSOI/851 Series of modules are not unconditionally stable for all load and source impedances. Out-of-band impedances of filters result in Significantly high VSWR's at out-of-band frequencies. If these impedances are reflected to the module such that the module is terminated in impedances that lead to regions of instability, the module will oscillate. Input power to the module can vary from a low value of o mW to a recommended maximum of 3 mW. Input powers greater than 3 mW are not recommended because of the potential damage that might result from overdriving the two final class C stages in the module. Overdrive results in excessive power dissipation particularly for the simultaneous condition of maximum supply voltage of 7.5 volts. Overdriving the final Class C stages can also lead to circuit instabilities tlecause of changing impedances. Likewise, supply voltages greater than 7.5 volts should not be applied to the module for the same reasons of overdissipation and potential instabilities. GAIN CONTROL The data sheet recommends gain control by keeping input power at 0 dBm and varying the control voltage. Output power versus control voltage is shown in the typical characteristics of the data sheet. Gain control in the MHWS01/S51 Series module is obtained by controlling the bias to the Class A input stage as opposed to other modules that controls the voltage to Class C driver stages. The benefit of this method of control is significantly less contro'l current and a lower slope of the output power versus control voltage curve. It is possible to control output power from the module by controlling input power with the control voltage maintained at a fixed level (generally maximum). This is somewhat intuitive; however, a major benefit of this method for power out control may not be obvious. This benefit is the best noise performance of the module because the small Signal gain is approximately 3 dB less at high control voltage as compared to low control voltage. Other important factors such as stability, input VSWR, harmonics, efficiency and load mismatch are essentially unaffected by the method of output power control. MOUNTING CONSIDERATIONS GENERAL In mounting power modules, consideration must be given to heat dissipation and grounding. Motorola specifies the range of case temperatures over which the module will perform safely. The upper temperature is determined by thermal resistances between each die and the case with the guideline that die temperature will be maintained below 200°C, which is considered a safe temperature for silicon transistors. All the user has to do is provide sufficient heat sinking for the module to be certain that the flange of the module does not exceed the maximum operating temperature rating. The maximum power dissipated by the module can be determined by determining the maximum DC power OTHER CIRCUIT CONSIDERATIONS Performance of the module at less than rated output power is sometimes of significance in typical module applications. Regardless of output power control, the noise character- 341 input less the RF power output. Another way to determine the maximum power to be dissipated is to divide the rated output power by the minimum efficiency and then subtract the rated output power. Maximum power dissipation for either the MHWB01 or MHWB51 Series modules is 2.44 walls (2 Walls divided by .45 minus 2 Watts). This relatively small amount of power can normally be dissipated by minimal thermal contact between the flange of the module and the heatsink provided in the application. Calculations using the MHWB51 module attached to a heatsink only at the mounting screws indicate that the rise in flange temperature (at center of flange) above the temperature at the ends of the flange should not exceed lO°C. Grounding the module to external circuitry through mounting screws only should be adequate to prevent spurious oscillations provided the ground contact does not become excessively resistive as a result of nickel oxide forming on the nickel plated flange. Nickel oxide (unlike copper and silver oxide) is resistive and its formation can lead to intermittent ground paths between the module and external circuits. MHW801 Series MHWB01 modules are designed without "ears" on the flange. They should be attached to a heatsink with solder. When soldering, the primary consideration should be to prevent any part of the module flange from achieving a temperature greater than 165°C. A low temperature solder such as 52% In and 4B% Sn (along with "R" type flux) is recommended because this solder liquifies below 150°C. Keep in mind that the internal construction of the module has been achieved using 36% Sn, 62% Pb and 2% Ag solder which liquifies at 179-1BO°C. If the module flange is allowed to achieve a temperature greater than 165°C, serious mechanical damage could occur with consequent failure to function electrically being the end result. Also, as stated on the data sheet, do not permit the module to be immersed in a flux removal system. The part is not hermetically sealed, and liquids could penetrate into the circuitry with potentially disasterous results. MHW851 Series MHWB51 type modules have flanges with "ears" for allachmentto a heatsink by means of screws. The cutouts at each end of the flange will accommodate 4-40 screws and these should be torqued to an amount no greater than 2 to 3 inch-pounds. The use of thermal grease is not recommended for the MHWB51 Series module because the relatively low output power does not require intimate (thermal) contact of the flange surface to the heatsink. Use of thermal grease is permissible but care must be taken to prevent using an excessive amount. Since it is not needed, it is Motorola's recommendation that it not be used. Flatness of the heatsink when using MHWB51 's is much less critical than that required for higher power modules. Motorola recommends that the heatsink surface be flat to within + or - 0.003 inches, a dimension that should be relatively easy to allain. The MHWB01/B51 Series module is constructed with a printed circuit board substrate which negates the stringent requirements for bending that are placed on ceramic substrate modules. Motorola believes that the MHWB01/B51 Series module can be distorted as much as 0.020 inches either concave or convex without damage to the module. Because bending requirements are relaxed, it is also unnecessary to worry about tightening sequence as described in EB107 - "Mounting Considerations for Motorola RF Power Modules." This EB was written primarily for ceramic substrate modules and does not apply in total to printed circuit board substrate modules such as the MHWB01/B51 Series. 342 AN1107 Understanding RF Data Sheet Parameters by Norman E. Dye RF Products Division the transistor and on the other hand has breakdown voltages that permit the "gain at frequency" objectives to be met by the transistor. Mobile radios normally operate from a 12 volt source; portable radios use a lower voltage, typically 6 to 9 volts; avionics applications are commonly 28 volt supplies while base station and other ground applications such as medical electronics generally take advantage of the superior performance characteristics of high voltage deVices and operate with 24 to 50 volt supplies. In making a transistor, breakdown voltages are largely determined by material resistivity and junction depths (Figure 2). It is for these reasons that breakdown voltages are Intimately entwined with functional performance characteristics. Most product portfolios In the RF power transistor industry have families of transistors deSigned for use at specified supply voltages such as 7.5 volts, 12.5 volts, 28 volts and 50 volts. Leakage currents (defined as reverse biased Junction currents that occur prior to avalanche breakdown) are likely to be more varied in their speCification and also more Informative. Many transistors do not have leakage currents specified because they can result In excessive (and frequently unnecessary) wafer/die Yield losses. Leakage currents arise as a result of material defects, mask imperfections and/or undesired impurities that enter during wafer processing. Some sources of leakage currents are potential reliability problems; most are not. Leakage currents can be material related such as stacking faults and dislocations or they can be "pipes" created by mask defects and/or processing inadequacies. These sources result In leakage currents that are constant with time and if initially acceptable for a particular application will remain so. They do not pose long term reliability problems. On the other hand, leakage currents created by channels induced by mobile ionic contaminants In the oxide (primarily sodium) tend to change with time and can lead to Increases in leakage current that render the device useless for a specific application. Distinguishing between sources of leakage current can be difficult, which is one reason deVices for application in military environments require HTRB (high temperature reverse bias) and burn-in testing. However. even for commercial applications particularly where battery drain is critical or where bias considerations dictate limitations. it is essential that a leakage current limit be included In any complete device specification. INTRODUCTION Data sheets are often the sole source of information about the capability and characteristics of a product. This is particu· larly true of unique RF semiconductor devices that are used by equipment designers allover the world. Because the circuit designer often cannot talk directly with the factory, he relies on the data sheet for his device information. And for RF devices, many of the specifications are unique in them· selves. Thus it is important that the user and the manufactur· er of RF products speak a common language, i.e., what the semiconductor manufacturer says about his RF device is understood fully by the circuit designer. This paper reviews RF transistor and amplifier module parameters from maximum ratings to functional characteristics. It IS divided into 5 basic sections: 1) DC Specifications, 2) Power Transistors, 3) Low Power Transistors, 4) Power Modules and 5) Linear Modules. Comments are made about critical specifications, about how values are determined and what are their significance. A brief description of the procedures used to obtain impedance data and thermal data is set forth; the importance of test cirCUits is elaborated; and background Information is given to help understand low noise considerations and linearity requirements. DC SPECIFICATIONS BaSically RF transistors are characterized by two types of parameters: DC and functional. The "DC" specs consist (by definition) of breakdown voltages, leakage currents, hFE (DC beta) and capacitances, while the functional specs cover gain, ruggedness, noise figure, Zin and Zout, S'parameters, distortion, etc. Thermal characteristics do not fall cleanly into either category since thermal resistance and power dissipation can be either DC or AC. Thus, we will treat the spec of thermal resistance as a special specification and give it its own heading called "thermal characteristics." Figure 1 IS one page of a typical RF power data sheet showing DC and functional specs. A critical part of selecting a transistor is choosing one that has breakdown voltages compatible with the supply voltage available in an intended application. It is important that the design engineer select a transistor on the one hand that has breakdown voltages which will NOT be exceeded by the DC and RF voltages that appear across the various junctions of 343 ELECTRICAL CHARACTERISTICS (TC =25°C unless otherwise noted.) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS = 20 mAdc, IB = 0) =20 mAdc, VBE = 0) Emitter-Base Breakdown Voltage (IE = 5.0 mAdc, IC = 0) Collector-Emitter Breakdown Voltage (IC Collector-Emitter Breakdown Voltage (IC Collector Cutoff Current (VCE V(BR)CEO 16 - - V(BR)CES 36 - - Vdc V(BR)EBO 4.0 - - Vdc ICES - - 10 hFE 20 70 150 - Cob - 90 125 pF G pe 4.8 5.4 - dB Pin - 13 15 55 60 - = 15 Vdc, VBE =0, TC = 25°C) Vdc mAdc ON CHARACTERISTICS DC Current Gain (IC = 4.0 Adc, VCE = 5.0 Vdc) DYNAMIC CHARACTERISTICS Output Capacitance (VCB = 12.5 Vdc, IE =0, f = 1.0 MHz) FUNCTIONAL TESTS Common-Emitter Amplifier Power Gain (VCC = 12.5 Vdc. Pout = 45 W, Ic(Max) Input Power (VCC = 12.5 Vdc. Pout = 45 W. f = 470 Collector Efficiency (VCC = 12.5 Vdc. Pout = 45 W, Load Mismatch Stress (VCC = 16 Vdc, Pin = Note 1. f =5.8 Adc, f = 470 MHz) Watts MHz) Ic(Max) '1 =5.8 Adc, f = 470 MHz) No Degradation in Output Power ~,* = 470 MHz, VSWR =20:1, All Phase Angles) % Series Equivalent Input Impedance (VCC = 12.5 Vdc, Pout = 45 W. f = 470 MHz) Zin - 1.4+j4.0 - Ohms Senes Equivalent Output Impedance (VCC = 12.5 Vdc. Pout = 45 W. f = 470 MHz) ZOL* - 1.2+j2.8 - Ohms Notes , Pin'"' 50°0 of Drive ReqUirement for 45 W output @ 125 V • L,' = Mismatch stress factor the electrical cntenon established to venfy the deVice resistance to load mismatch failure. The mismatch stress test IS accomplished In the standard test fixture IFlgure 1) terminated In a 20 1 minimum load mismatch at all phase angles. Figure 1_ Typical DC and Functional Specifications ~oo --. 100 r-- 50 ..... 10 7 3 -xi ". ~20 - 5 PLANE JUNCTION 30 / ~~ ~ l~m -10 '" 1016 DOPING DENSITY CB (cm-3) Figure 2. The Effect of Curvature and Resistivity on Breakdown Voltage 344 DC parameters such as hFE and Cob (output capacitance) need little comment. Typically, for RF devices, hFE is relatively unimportant because the functional parameter of gain at the desired frequency of operation is specified. Note, though, that DC beta is related to AC beta (Figure 3). Functional gain will track DC beta particularly at lower RF frequencies. Generally RF device manufacturers do not like to have tight limits placed on hFE. Primarily the reasons that justify this position are: a} Lack of correlation with RF performance b} Difficulty in control in wafer processing c} Other device manufacturing constraints dictated by functional performance specs which preclude tight limits for hFE. A good rule of thumb for hFE is to set a maximum-to-minimum ratio of not less than 3 and not more than 4 with the minimum hFE value determined by an acceptable margin in functional gain. tL .9: 1.8 w ~ 1.6 ~ ~ C3 12 w ~ d:: 0.8 ~ 0.6 <5 0.4 u 0.2 {J u 1= 1 MHz 1.4 I\, 00 "- ............... 4 6 8 10 12 14 16 VCB, COLLECTOR-BASE VOLTAGE (Vdc) Figure 4. Junction Capacitance versus Voltage The value of V(BR}CEO is sometimes misunderstood. Its value can approach or even equal the supply voltage rating of the transistor. The question naturally arises as to how such a low voltage can be used in practical applications. First, V (BR}CEO is the breakdown voltage of the collector-base junction plus the forward drop across the base-emitter junction with the base open, and it is never encountered in amplifiers where the base is at or near the potential of the emitter. That is to say, most amplifiers have the base shorted or they use a low value of resistance such that the breakdown value of interest approaches V (BR}CES· Second, V (BR}CEO involves the current gain of the transistor and increases as frequency increases. Thus the value of V (BR}CEO at RF frequencies is always greater than the value at DC. The maximum rating for power dissipation (PD) is closely 40r---------------------------------, POWER GAIN 30 Hie ~ w 20 '" C3 w C> 10 °2~--~--~10~~--~~~~~~~~~· FREQUENCY, MEGACYCLES Figure 3. Beta versus Frequency associated with thermal resistance (IlJC). Actually maximum PD is in reality a fictitious number - a kind of figure of merit - because it is based on the assumption that case tempera- Output capacitance is an excellent measure of comparison of device size (base area) provided the majority of output capacitance is created by the base-collector junction and not parasitic capacitance ariSing from bond pads and other top metal of the die. Remember that junction capacitance will vary with voltage (Figure 4) while parasitic capacitance will not vary. Also, in comparing devices, one should note the voltage at which a given capacitance is specified. No industry standard exists. The preferred voltage at Motorola is the transistor VCC rating, i.e., 12.5 volts for 12.5 volt transistors and 28 volts for 28 volt transistors, etc. ture is maintained at 25'C. However, providing everyone arrives at the value in a similar manner, the rating of maximum PD is a useful tool with which to compare devices. The rating begins with a determination of thermal resistance - die to case. Knowing HJC and assuming a maximum die temperature, one can easily determine maximum PD (based on the previously stated case temperature of 25'C). Measuring IlJC is normally done by monitoring case temperature (T C) of the device while it operates at or near rated output power (PO) in an RF circuit. The die temperature (T J) is measured simultaneously using an infra-red microscope (see Figure 6) which has a spot size resolution as small as 1 mil in diameter. Normally several readings are taken over the surface of the die and an average value is used to specify TJ. It is true that temperatures over a die will vary typically MAXIMUM RATINGS and THERMAL CHARACTERISTICS Maximum ratings (shown for a typical RF power transistor in Figure 5) tend to be the most frequently misunderstood group of device specifications. Ratings for maximum junction voltages are straight forward and simply reflect the minimum values set forth in the DC specs for breakdown voltages. If the device in question meets the specified minimum breakdown voltages, then voltages less than the minimum will not cause junctions to reach reverse bias breakdown with the potentially destructive current levels that can result. 10-20'C. A poorly designed die (improper ballasting) could result in hot spot (worst case) temperatures that vary 40-50'C. Likewise, poor die bonds (see Figure 7) can result in hot spots but these are not normal characteristics of a properly designed and assembled transistor die. 345 MRF650 The RF Line NPN Silicon RF Power Transistor 50 WATTS. 512 MHz RF POWER TRANSISTOR NPN SILICON · .. designed for 12.5 Volt Volt UHF large-signal amplifier applications in industrial and commercial FM equipment operating to 520 MHz. • Guaranteed 440, 470, 512 MHz 12.5 Volt Characteristics Output Power; 50 Watts Minimum Gain; 5.2 dB @ 440, 470 MHz Efficiency; 55% @ 440, 470 MHz IRL; 10dB • Characterized with Series Equivalent Large-Signal Impedance Parameters from 400 to 520 MHz • • • • • Built-In Matching Network for Broadband Operation Triple Ion Implanted for More Consi.stent Characteristics Implanted Emitter Ballast Resistors Silicon Nitride Passivated 100% Tested for Load Mismatch Stress at all Phase Angles with 20: 1 VSWR @ 15.5 Vdc, 2.0 dB Overdrive CASE 316-01 MAXIMUM RATINGS Symbol Value Collector-Emitter Voltage VCEO t6.5 Vdc Collector-Emitter Voltage VCES 38 Vdc Emitter-Base Voltage VEBO 4.0 Vdc IC 12 Adc 135 0.77 Watts Tstg ---65 to +150 'C Symbol Max Unit RfjJC 1.3 'CIW Rating Collector-Current - Continuous Po Total Device Dissipation @ T C = 25'C Derate above 25'C Storage Temperature Range Unit wrc THERMAL CHARACTERISTICS Characteristic Thermal Resistance, Junction to Case Figure 5. Maximum Ratings of a Typical RF Power Transistor both surements described in the preceding paragraphs, or for the OC and RF - one can calculate 8JC from the formula 8JC ; (TJ - TC)/(Pin - PO)· Typical values for an RF power By measuring T C and TJ along with Po and Pin - case illustrated, a value of BJC ; 1.25'C/W. Now a few words are in order about die temperature. Reliability considerations dictate a safe value for an all Au transistor might be TJ ; 130'C; TC; 50'C; VCC ; 12.5 V; IC ; 12 A; Pin (RF) = 10 W; Po (RF) ; 50 W. Thus 8JC (gold) system (die top metal and wire) to be 200'C. Once ; (130 - 50)/(10 + {12.5 x 12} - 30) ; 80/80 ; 1'C/W. Several reasons dictate a conservative value be placed TJ max is determined, along with a value for 8JC, maximum Po is simply on 8JC. First, thermal resistance increases with temperature Po (max) ; (TJ (max) - 25'C)/8JC· (and we realize Tc = 25'C is NOT realistic). Second, TJ is not a worst case number. And, third, by using a conservative Specifying maximum Po for TC ; 25'C leads to the necessity to derate maximum Po for any value of TC above value of 8JC, a realistic value is determined for maximum 25'C. The derating factor is simply the reciprocal of BJC! Maximum col/ector current (lC) is probably the most subjective maximum rating on the transistor data sheets. It has PO. Generally, Motorola's practice is to publish 8JC numbers approximately 25% higher than that determined by the mea- 346 ty, temperature and type of metal. At Motorola, MTBF is generally set at >7 years and maximum die temperature at 200 o e. For plastic packaged transistors, maximum TJ is set at 150o e. The resulting current density along with a knowledge of the die geometry and top metal thickness and material allows the determination of Ie max for the device. It is up to the transistor manufacturer to specify an Ie max based on which of the two limitations (die, wire) is paramount. It is recommended that the circuit design engineer consult the semiconductor manufacturer for additional information if Ie max is o! any concern in his specific use of the transistor. Storage temperature is another maximum rating that is frequently not given the attention it deserves. A range of -55°e to 200 0 e has become more or less an industry standard. And for the single metal, hermetic packaged type Figure 6. Equipment Used To Measure Ole Temperature of device, the upper limit of 200 0 e creates no reliability problems. However, a lower high temperture limitation exists for plastic encapsulated or epoxy sealed devices. These should not be subjected to temperatures above 150 0 e to prevent deterioration of the plastic material. POWER TRANSISTORS Functional Characteristics The selection of a power transistor usually involves choosing one for a frequency of operation, a level of output power, a desired gain, a voltage of operation and preferred package configuration consistent with circuit construction techniques. Functional characteristics of an RF power transistor are by necessity tied to a specific test circuit (an example is shown in Figure 8). Without specifying a circuit, the functional parameters of gain, reflected power, efficiency - even ruggedness - hold little meaning. Furthermore, most test circuits used by RF transistor manufacturers today (even those used to characterize devices) are designed mechanically to allow for easy insertion and removal of the device under test (O.U.T.). This mechanical restriction sometimes limits achievable device performance which explains why performance by users frequently exceeds that indicated in data sheet curves. On the other hand, a circuit used to characterize a device is usually narrow band and tunable. This results in higher gain than attainable in a broadband circuit. Unless otherwise stated, it can be assumed that characterization data such as Po vs frequency is generated on a point-by-point basis by tuning a narrow band circuit across a band of frequencies and, thus, represents what can be achieved at a specific frequency of interest provided the circuit presents optimum source and load impedances to the O.U.T. Broadband, fixed tuned test circuits are the most desirable for testing functional performance of an RF transistor. Fixed tuned is particularly important In assuring everyone - the manufacturer and the user - of product consistency, i.e .. that devices manufactured tpmorrow will be identical to devices manufactured today. Tunable, narrow band circuits have led to the necessity for device users and device manufacturers to resort to the use of "correlation units" to assure product consistency over Figure 7. An Example of Incomplete Die Attach been, and is, determined in a number of ways each leading to different maximum values. Actually, the only valid maxi· mum current limitations in an RF transistor have to do with the current handling ability of the wires or the die. However, power dissipation ratings may restrict current to values far below what should be the maximum rating. Unfortunately, many older transistors had their maximum current rating determined by dividing maximum Po by collector voltage (or be V (BR)eEO for added safety) but this is not a fundamental maximum current limitation of the part. Many lower frequency parts have relatively gross top metal on the transistor die, i.e., wide metal runners and the "weak current link" in the part is the current handling capability of the emitter wires (for common emitter parts). The current handling ability of wire (various sizes and material) is well known; thus the maximum current rating may be limited by the number, size and material used for emitter wires. Most modern, high frequency transistors are die limited because of high current densities resulting from very small current carrying conductors and these densities can lead to metal migration and premature failure. The determination of Ie max for these types of transistors results from use of Black's equation for metal migration which determines a mean time between failures (MTBF) based on current densi· 347 coefficient is set at a magnitude of unity while its phase angle is varied through all possible values from 0 degrees to 360 degrees. Many 12 volt (land mobile) transistors are routinely given this test at Motorola Semiconductors by means of a test station similar to the one shown in Figure 9. Figure 8. Typical RF Power Test Circuit a period of time. Fixed tuned circuits minimize (if not eliminate) the requirements for correlation and in so doing tend to compensate for the increased constraints they place on the device manufacturer. On the other hand, manufacturers like tunable test circuits because their use allows adjustments that can compensate for variations in die fabrication and/or device assembly. Unfortunately gain is normally less in a broadband circuit that it is in a narrow band circuit, and this fact frequently forces transistor manufacturers to use narrow band circuits to make their product have sufficient attraction when compared with other similar devices made by competitors. This is called "specsmanship." One compromise for the transistor manufacturer is to use narrow band circuits with all tuning adjustments "locked" in place. For all of the above reasons, then, in comparing functional parameters of two or more devices, the data sheet reader should observe carefully the test circuit in which specific parameter limits are guaranteed. For RF power transistors, the parameter of ruggedness takes on considerable importance. Ruggedness is the characteristic of a transistor to withstand extreme mismatch conditions in operation (which causes large amounts of output power to be "dumped back" into the transistor) without altering its performance capability or reliability. Many circuit environments particularly portable and mobile radios have limited control over the impedance presented to the power amplifier by an antenna, at least for some duration of time. In portables, the antenna may be placed against a metal surface; in mobiles, perhaps the antenna is broken off or inadvertently disconnected from the radio. Today's RF power transistor must be able to survive such load mismatches without any effect on subsequent operation. A truly realistic possibility for mobile radio transistors (although not a normal situation) is the condition whereby an RF power device "sees" a worst case load mismatch (an open circuit. any phase angle) along with maximum Vee AND greater than normal input drive - all at the same time. Thus the ultimate test for ruggedness is to subject a transistor to a test wherein Pin (RF) is increased up to 50% above that value necessary to create rated PO; Vee is increased about 25% (12.5 V to 16 V for mobile transistors) AND then the load reflection Figure 9. A Typical Functional Test Station Ruggedness specifications come in many forms (or guises). Many older devices (and even some newer ones) simply have NO ruggedness spec. Others are said to be "capable of' withstanding load mismatches. Still others are guaranteed to withstand load mismatches of 2:1 VSWR to x:1 VSWR at rated output power. A few truly rugged transistors are guaranteed to withstand 30:1 VSWR at all phase angles (for all practical purposes 30:1 VSWR is the same as x:1 VSWR) with both over voltage and over drive. Once again it is up to the user to match his circuit requirements against device specifications. Then as if the whole subject of ruggedness is not sufficiently confusing, the semiconductor manufacture slips in the ultimate "muddy the water" condition in stating what constitutes passing the ruggedness test. The words generally say that after the ruggedness test the D.U.T. "shall have no degradation in output power." A better phrase would be "no measurable change in output power." But even this is not the best. Unfortunately the D.U.T. can be "damaged" by the ruggedness test and still have "no degradation in output power." Today's RF power transistors consist of up to 1K or more low power transistors connected in parallel. Emitter resistors are placed in series with groups of these transistors in order to better control power sharing throughout the transistor die. It is well known by semiconductor manufacturers that a high percentage of an RF power transistor die (say up to 25-30%) can be destroyed with the transistor still able to deliver rated power at rated gain, at least for some period of time. If a ruggedness test destroys a high percentage of cells in a transistor, then it is likely that a 2nd ruggedness test (by the manufacturer or by the user while in his circuit) would result in additional damage leading to premature device failure. A more scientific measurement of "passing" or "failing" a ruggedness test is called tNRE - 348 the change in emitter resistance before and after the ruggedness test. VRE is determined to a large extent by the net value of emitter resistance in the transistor die. Thus if cells are destroyed, emitter resistance will change with a resultant change in Vre. Changes as small as 1% are readily detectable, with 5% or less normally considered an acceptable limit. Today's more sophisticated device specifications for RF power transistors use this criteria to determine "success" or "failure" in ruggedness testing. A circuit designer must know the input/output characteristics of the RF power transistor(s) he has selected in order to design a circuit that "matches" the transistor over the frequency band of operation. Data sheets provide this information in the form of large signal impedance parameters, Zin and Zout (commonly referred to as ZOL*). Normally, these are stated as a function of frequency and are plotted on a Smith Chart and/or given in tabular form. It should be noted that Zin and Zout apply only for a specified set of operating conditions, i.e., PO, VCC and frequency. Both Zin and Zout of a device are determined in a similar way, i.e., place the D.U.T. in a tunable circuit and tune both input and output circuit elements to achieve maximum gain for the desired set of operating conditions. At maximum gain, D.U.T. impedances will be the conjugate of the input and output network impedances. Thus, terminate the input and output ports of the test circuit, remove the device and measure Z looking from the device - first, toward the input to obtain the conjugate of Zin and, second, toward the output to obtain ZOL which is the output load required to achieve maximum PO· A network analyzer is used in the actual measurement process to determine the complex reflection coefficient of the circuit using, typically, the edge of the package as a plane of reference. A typical measurement setup is shown in Figure 10. Figure 11 shows the special fixture used to obtain the short circuit reference while Figure 12 illustrates the adapter which allows the circuit impedance to be measured from the edge of the package. Figure 11. Short Circuit Reference Fixture Figure 12. Adapter Used To Measure Circuit Impedance From Package aided design programs to design Land C matching networks for his particular application. The entire impedance measuring process is somewhat laborious and time consuming since it must be repeated for each frequency of interest. Note that the frequency range permitted for characterization is that over which the circuit will tune. For other frequencies, additional test circuits must be designed and constructed, which explains why it is some· times difficult to get a semiconductor manufacturer to supply impedance data for special conditions of operation such as different frequencies, different power levels or different oper· ating voltages. LOW POWER TRANSISTORS Functional Characteristics Most semiconductor manufacturers characterize low pow· er RF transistors for linear amplifier and/or low noise amplifier applications. Selecting a proper low power transistor involves choosing one having an adequate current rating. in the "right" package and with gain and noise figure capability that meets the requirements of the intended application. One of the most useful means of specifying a linear device is by means of scattering parameters, commonly referred to as S-Parameters which are in reality voltage reflection and Figure 10. The HP Network Analyzer Once the circuit designer knows ZIN and ZOL* of the transistor as a function of frequency, he can use computer 349 transmission coefficients when the device is embedded into a 50 ohm system. See Figure 13. IS111. the magnitude of the input reflection coefficient is directly related to input VSWR by the equation VSWR = (1 + IS111) I (1 - IS111). Likewise, IS221, the magnitude of the output reflection coefficient is directly related to output VSWR. IS21 12 , which is the square of the magnitude of the input-to-output transfer function, is also the power gain of the device. It is referred to on data sheets as "Insertion Gain." Note, however, that IS2112 is the power gain of the device when the source and load impedances are 50 ohms. An improvement in gain can always be acheived by matching the device's input and output impedances (which are almost always different from 50 ohms) to 50 ohms by means of matching networks. The larger ttie linear device, the lower the impedances and the greater is the need to use matching networks to achieve useful gain. INPUT Zo .. A1 A2 LINEAR TWO·PORT 81 • .. 82 21 1---------- REFERENCE PLANES S11 INPUT REFLECTION COEFFICIENT = S22 • OUTPUT REFLECTION COEFFICIENT = IS21 j2 • FORWARD TRANSDUCER GAIN = IS1212 • REVERSE TRANSDUCER GAIN = :: :~ :~ :~ Figure 13, Two-Port S-Parameter Definitions Another gain specification shown on low power data sheets is called "Associated Gain." The symbol used for Associated Gain is "GNF." It is simply the gain of the device when matched for minimum noise figure. Yet another gain term is shown on some data sheets and it is called "Maximum Unilateral Gain." It's symbol is GU max. As you might expect, GU max is the gain achievable by the transistor when the input and output are conjugately matched for maximum power transfer (and S12 = 0.). One can derive a value for GU max using scattering parameters: GU max = IS2112 I {(1 - IS1112 (1 - IS2212)}. Simply stated, this is the 50 ohm gain increased by a factor which represents matching the input and increased again by a factor which represents matching the output. Many RF low power transistors are used as low noise amplifiers which has led to several transistor data sheet parameters related to noise figure. NFmin is defined as the minimum noise figure that can be achieved with the transistor. To achieve this NF requires source impedance matching which is usually different from that required to achieve maximum gain. The design of a low noise amplifier, then, is always a compromise between gain and NF. A useful tool to aid in this compromise is a Smith Chart plot of constant gain and Noise Figure contours which can be drawn for specific operating conditions - typically bias and frequency. A typical Smith Chart plot showing constant gain and NF contours is shown in Figure 14. These contours are circles which are either totally or partially complete within the confines of the Smith Chart. If the gain circles are contained entirely within the Smith Chart, then the device is unconditionally stable. If portions of the gain circles are outside the Smith Chart, then the device is considered to be "conditionally stable" and the device designer must concern himself with instabilities, particularly outside the normal frequency range of operation. If the data sheet includes Noise Parameters, a value will be given for the optimum input reflection coefficient to achieve minimum noise figure. Its symbol is to or sometimes fopt, But remember if you match this value of input reflection coefficient you are likely to have far less gain than is achievable by the transistor. The input reflection coefficient for maximum gain is normally called fMS, while the output reflection coefficient for maximum gain is normally called fML· Another important noise parameter is noise resistance which is given the symbol Rn and is expressed in ohms. Sometimes in tabular form, you may see this value normalized to 50 ohms in which case it is designated rn. The significance of rn can be seen in the formula below which determines noise figure NF of a transistor for any source reflection coefficient f s if the three noise parameters - 350 +j50 +j250 +j250 +j500 +j500 -j500 -1500 -j250 -j50 -j250 veE =6 V Ie =3 rnA veE = 6 V Ie =3 rnA -j50 f= 4000 MHz f= 2000 MHz (A) F = 2 GHz ~ - AREA OF INSTABILITY (8) F = 4 GHz Figure 14. Gain & Noise Figure Contours (the NFmin circle being a point); thus, by choosing different values of NF one can plot a series of noise circles on the Smith Chart. Incidentally, rn can be measured by measuring NFmin, rn and r 0 (the source resistance for minimum noise figure) - are known. Typical noise parameters taken from the MRF942 data sheet are shown in Figure 15. , (MHz) GNF (dB) 3 1000 2000 4000 1.3 2.0 2.9 15 1000 2000 4000 2.1 2.7 4.3 IC (rnA) 6 and applying the equation stated MRF942 NFmin (dB) VCE (Vdc) rs = 0 noise figure for above. NF = NFmin + {4rn Irs - r 012} / {(I - Ifs12) 11 + r 012}. The locus of points for a given NF turns out to be a circle ro RN (MAG, AN G) (ohms) NFSO Q (dB) 16 11 B.O 36 L 94 .37 L -145 .50 L -134 17.5 15.5 21.5 1.7 26 4.3 19 14 9.0 .25 L 150 .26 L -173 .48 L -96 13 16.5 47 2.6 3.1 5.4 Figure 15. Typical Noise Parameters A parameter found on most RF low power data sheets is commonly called the current gain-bandwidth product. It's - things which are more difficult to achieve In making an RF transistor. The complete RF low power transistor data sheet will symbol is fT' Sometimes it is referred to as the cutoff frequency because it is generally thought to be the product of low frequency current gain and the frequency at which the current gain becomes unity. While this is not precisely true (see Figure 16), it is close enough for practical purposes. And it include a plot of fT versus collector current. Such a curve (as shown in Figure 17) will increase with current. flatten and then begin to decrease as IC increases thereby revealing useful information about the optimum current with which to achieve maximum device gain. Another group of characteristics associated with linear (or Class "A") transistors has to do with the degree to which the device is linear. Most common are terms such as "Po. 1 dB Gain Compression Point" aQd "3rd Order Intercept Point (or ITO as it is sometimes called)." More will be said about is true that fT is an excellent figure-of-merit which becomes useful in comparing devices for gain and noise figure capability. High values of It are normally required to achieve higher gain at higher frequencies, other factors being equal. To the device designer, high fT mean decreased spacings between emitter and base diffusions and it means shallower diffusions 351 EXTRAPOLATED GAIN I ~ 1dBGAIN COMPRESSION POINT Ihfell----""'-- ....- - - - hfeo ~ / - - - hfeol.2 -------f--I I hfeol2 _~ 2.0 1.0 I I I I I I fB 2fB -------r-t-_______ I-_L __ +-== f SLOPE REGION 1\ MAGNITUDE OF SMALL·SIGNAL COMMON· EMITTER (CEI SHORT·CIRCUIT (SCI CURRENT GAIN, hfe WHERE Ihfel LOW·FREQUENCY VALUE OF hIe 3 dB CUTOFF FREQUENCY FOR CE, SC CURRENT GAIN hleo IB INPUT POWER IN dBm IT TRANSITION FREQUENCY =Ihlel • fMEAS WHERE fMEAS. =F~EQUENCY OF MEASUREMENT (NOTE: 2 -Ihfel s 11 = Figure 18. Linear Gain and 1 dB Compression Point ~I high end of dynamic range is the limit imposed by "gain compression." 2 FREQUENCY AT WHICH Ihlel =1 Figure 16. Small Signal Current Gain versus Frequency LINEAR MODULES - 10 -;:;- :I: f2. >- t.> ::::> 0 0 0: ....... C1. :I: >0 V ~ z '"-" \ ./ 0 Z ;;: V V ./ IVC~ = ~V I I 3 5 7 10 20 I 30 40 Functional Characteristics Let's turn now to amplifiers and examine some specifications encountered that are unique to specific applications. Amplifiers intended for cable television applications are selected to have the desired gain and distortion characteristics compatible with the cable network requirements. They are linear amplifiers consisting of 2 or more stages of gain each using a push-pull cascade configuration. Remember that a cascade stage is one consisting of 2 transistors in which a common emitter stage drives a common base stage. A basic circuit configuration is shown in Figure 19. Most operate from a standard voltage of 24 volts and are packaged in an industry standard configuration shown in Figure 20. Because they are used to "boost" the RF signals that have been attenuated by the losses in long lengths of coaxial cable (the losses of which increase with frequency), their gain characteristics as a function of frequency are very important. These are defined by the specifications of "slope" and "flatness" over the frequency band of interest. Slope is defined simply as the difference in gain at the high and low end of the frequency band of the amplifier. Flatness, on the other hand, is defined as the deviation (at any frequency in the band) from an ideal gain which is determined theoretically by- a universal cable loss function. Motorola normally measures the peak-to-valley .(high-to-Iow) variations in gain across the frequency band, but specifies the flatness as a "plus, minus" quantity because it is assumed that cable television system designers have the capability of adjusting overall gain level. The frequency band requirements of a CATV amplifier are determined by the number of channels used in the CATV system. Each channel requires 6 MHz bandwidth (to handle conventional color TV signals). Currently available models in the industry have bandwidths extending from 40 to 550 MHz and will accommodate up to 77 channels, the center I IC, COLLECTOR CURRENT (mAl Figure 17, Gain·Bandwidth Product versus Collector Current non·linearities and distortion measurements in the section about Linear Amplifiers; however, suffice it to be said now that "Po, 1 dB Gain Compression Point" is simply the output power at which the input power has a gain associated with it that is 1 dB less than the low power gain. In other words, the device is beginning to go into "saturation" which is a condition where increases in input power fail to realize increases in output power. The concept of gain compression is illustrated in Figure 18. The importance of the "1 dB Gain Compression Point" is that this is generally accepted as the limit of non-linearity that is tolerable in a "linear" amplifier and leads one to the dynamic range of the low power amplifier. On the low end of dynamic range is the limit imposed by noise, and on the 352 JII~ conSidering the first three terms, i.e., make the assumption we can write F(x) = C1X + C2x2 + C3x3, where F is the output signal and x is the input signal. Cl, C2 and C3 are constants that represent the transfer function (gain) for the first, second and third order terms. II~ Figure 19. Basic CATV Amplifier PIN, INPUT POWER (WADSI Figure 21. Transfer Function for Typical Transistor Figure 20. Standard CATV Package (Case 714-04) Now consider a relatively simple input signal consisting of 3 frequencies each having a constant amplitude A. (In the case of CATV amplifiers, there could be 50-60 channels each having a carrier frequency and associated modulation fre· quencies spread over a bandwidth approaching 6 MHz.) The frequencies of which are determined by industry standard frequency allocations. Because CATV amplifiers must amplify TV signals and they must handle many channels simultaneously, these amplifiers must be extremely linear. The more linear, the less distortion that is added to the signal and, thus, the better is the quality of the TV picture being viewed. Distortion is generally specified in 3 conventional ways - 2nd Order Interrnodulation Distortion (IMD), Cross Modulation Distortion (XMD) and Composite Triple Beat (CTB). In order to better understand what these terms mean, a few words need to be said about distortion in general First, let's consider a perfectly linear amplifier. The output signal is exactly the same as the input except for a constant gain factor. Unfortunately, transistor amplifiers are, even under the best of circumstances, not perfectly linear. If one were to write a transfer function for a transistor amplifier, a typical input-output curve for which is shown in Figure 21, he would find the region near zero to be one best represented by "squared" terms, i.e., the output is proportional to the square of the input. And the region near saturation, i.e., where the amplifier produces less incremental output for incremen· tal increases in input is best represented by "cubed" terms, i.e., the output is proportional to the cube of the input. A mathematically rigorous analysis of the transfer function of an amplifier would include an infinite number of higher order terms. However, an excellent approximation is obtained by input signal x then equals ACOS")lt + AcoS'''2t + AcoSOJ3t. If we apply this input signal to the transfer function and calculate F(x), we will find many terms involving x, x 2 and x3 . The "x" terms represent the "perfect", linear amplification of the input signal. Terms involving x2 when analyzed on a frequency basis result in signal components at two times the frequencies of fl, f2 and f3. Also created by x2 terms are signal components at sums and difference frequencies of all combinations of fl, f2 and f3. These are called 2nd order intermodulation components. Likewise, the terms involving x3 result in frequency components at three times the frequen· cies of fl ' f2 and f3. And there are also frequency components at sum and difference frequencies ( these are called 3rd order IMD). But in addition there are frequency compo· nents at fl +,- f2 +,- f3. These are called "triple beat"' terms. And this is not all! A close examination reveals additional amplitude components at the original frequencies of fl' f2 and f3. These terms can both "enhance" gain (expansion) or "reduce" gain (compression). The amplitude of these expansion and compression terms are such that we can divide the group of terms into two categories - "self-expan· sion/compression" and "cross-expansion/compression." Self'expansion/compression terms have amplitudes determined by the amplitude of a single frequency while cross·expansion/compression terms have amplitudes determined by the amplitudes of two frequencies. A summary of the terms that exist in this "simple" example is given in Table 1. 353 Table 1. 40 Terms in Output for Three Frequency Signal at Input FIRST ORDER COMPONENTS klA cos a + klB cosb + klC cosc 20 COMMENTS Linear Amplification SECOND ORDER DISTORTION COMPONENTS k2A2/2 + k2B2/2 + k2C2/2 . 3 DC components i k2AB cos(a+.-b) + k2AC cos(a+.-c) + 6 Sum & Difference Beats k2BC cos(b+.-c) k2A2/2 cos2a + k2B2/2 cos2b + k2C 2/2coS2C a: w ~ 3·2nd Harmonic Component 5 THIRD ORDER DISTORTION COMPONENTS k3A3/4 cos3(a) + k3B3/4 c053(b) + 3-3rd Harmonic Component, k3C3/4 cos3(c) o ~ 3k3A2B/4 c05(2a+.-b) + 3k3A2C/4 cos(2a+.-c) + 3k3B2A/4 cos(2b+.-a) + 3k3B2C/4 cos(2b+.-c) + 3k3C2A/4 c05(2e+.-a) + 3k3C2B/4 eos(2e+.-b) 12 Intermodulation Beats 3k3ABC/2 cos(a+.-b+.-c) 4 Triple Beat Components 3k3A3/4 cos (a) + 3k3B3/4 cos (b) + 3k3C3/4 cos (c) 3 Self Compression (k3 is +) or Self Expansion (k3 is -) -20 -40 ~ 0..0 -60 -ao -100 --'---.----r---,----,---,---,-90 -70 -50 -30 -10 +10 PIN, INPUT POWER IdBm) Figure 22_ Amplifier Response Curves 3k3AB2/2 cos (a) + 3k3AC2/2 eos(a) + 6 Cross Compression (k3 is 3k3BA2/2 cos (b) + 3k3BC2/2 cos (b) + or Cross Expansion (k3 is-) 3k3CA2/2 eos(e) + 3k3CB2/2 eos(e) distortion is -40 dBc and the signal level is -10 dBm; then the 2nd order intercept point is 40 dB above -10 dBm or +30 dBm. Note in Figure 22 that +30 dBm is the value of output signal at which the fundamental and 2nd order response lines cross. The beauty of the concept of "intercept point" is that once you know the intercept point, you can determine the value of distortion for any signal level provided you are in a region of operation governed by the mathematical relationships stated, which typically means IMD's greater than 60 dB below the carrier. Likewise to determine 3rd order intercept point, one must measure 3rd order distortion at a known signal level. Then take half the value of the distortion (expressed in dBc) and add to the signal level. For example, if the Signal level is +10 dBm and the 3rd order distortion is -40 dBc, the 3rd order intercept point is the same as the 2nd order intercept point or 10 dBm + 20 dB = 30 dBm. Both 2nd order and 3rd order intercept points are illustrated in Figure 22 using the values assumed in the preceding examples. Note, also, that in general the intercept point for 2nd and 3rd order distortion will have the same value unless circuits are used that suppress even-order spurious responses, etc. However, even in this situation the concept of intercept point is still valid; the slopes of the responses are still I, 2 and 3 respectively and all that needs to be done is to specify a 2nd order intercept point different from the 3rd order intercept point. With this background information, let's turn to specific distortion specifications listed on many RF linear amplifier data sheets. If the amplifiers are for use in cable television distribution systems, as previously stated, it is common practice to specify Second Order Intermodulation Distortion, Cross Modulation Distortion and Composite Triple Beat. We will examine these one at a time. First, consider Second Order Intermodulation Distortion (IMD). Remember these are Before going into an explanation of the tests performed on linear amplifiers such as CATV amplifiers. it is appropriate to review a concept called "intercept point." It can be shown mathematically that 2nd order distortion products have amplitudes that are directly proportional to the square of the input signal level. while 3rd order distortion products have amplitudes that are proportional to the cube of the input signal level. Hence, it can be concluded that a plot of each response on a log-log scale (or dB/dB scale) will be a straight line with a slope corresponding to the order of the response. Fundamental responses will have a slope of 1, the 2nd order responses will have a slope of 2 and the 3rd order responses a slope of 3. Note that the difference between fundamental and 2nd order is a slope of 1 and between fundamental and 3rd order is a slope of 2. That is to say, for 2nd order distortion, a 1 dB change in signal level results in a 1 dB change in 2nd order distortion; however, a 1 dB change in signal level results in a 2 dB change in 3rd order distortion. This is shown graphically in Figure 22. Using the curves of Figure 22, if the output level is 0 dBm, 2nd order distortion is at -30 dBc and 3rd order distortion is at -60 dBc. If we change the output level to -10 dBm, then 2nd order distortion should improve to -40 dBc (-50dBm) but 3rd order distortion will improve to --80 dBc (-90 dBm). Thus we see that a 10 dB decrease in signal has improved 2nd order distortion by 10 dB and 3rd order distortion has improved by 20 dB. Now for "intercept point." We define the "intercept point" as the point on the plot of fundamental response and 2nd (or 3rd) order response where the two straight lines intercept each other. It is also that value of signal (hypothetical) at which the level of distortion would equal the initial signal level. For example, if at our point of measurement, the 2nd order 354 unwanted signals created by the sums and differences of any two frequencies present in the amplifier. IMD is normally specified at a given signal output level and involves 3 channels ~ two for input frequencies and one to measure the resulting distortion frequency. The channel combinations are standardized in the industry but selected in a manner that typically gives a worst case condition for the 2nd order distortion results. An actual measurement consists of creating output signals (unmodulated) in the first two channels listed and looking for the distortion products that appear in the 3rd channel. If one wishes to predict the 2nd order IMD that would occur if the signals were stronger (or weaker), it is only necessary to remember the 1:1 relationship that led to a 2nd Order Intercept Point. In other words, if the specification guarantees an IMD of -68 dB Max. for a Vout = +46 dBmV per channel, then one would expect an IMD of -64 dB Max for a Vout = +50 dBmV per channel, etc, Cross Modulation Distortion (XMD) is a result of the cross-compression and cross-expansion terms generated by the third order non-linearity in the amplifier's input-output transfer function. In general, the XMD test is a measurement of the presence of modulation on an unmodulated carner caused by the distortion contribution of a large number of modulated carriers. The actual measurement consists of modulating each carrier with 100% square wave modulation at 15.75 kHz. Then the modulation is removed from one channel and the presence of residual modulation is measured with an amplitude modulation (AM) detector such as the commercially available Matrix RX12 distortion analyzer. Power levels and frequency relationships present in the XMD test are shown in Figure 23. /' '"w :;: Cl. f- => Cl. f- => r o II eom ----~ Figure 27. External Factors Affecting Stability Efficiency is becoming an increasingly important specification particularly in modules for portable radio applications. The correct way to specify efficiency is to divide the net increase in RF power (output power minus input power) by the total DC power consumed by the module. It is generally specified at rated output power because efficiency will decrease when the module is operated af lower power levels. Be careful that the specification includes the current supplied for biaSing and for stages other than the output stage. Overlooking these currents (and the DC power they use) results in an artifically high value for module efficiency. Most power module data sheets include a curve of output power versus temperature. Some modules specify this "power slump" in terms of a minimum power output at a stated maximum temperature; others state the maximum permissible decrease in power (in dB) referenced to rated power output. It is important to note the temperature range and the other conditions applied to the specification before passing judgement on this specification. Generally power modules·, like linear modules, do not have thermal resistance specified from die to heatsink. For multiple stage modules, there would need to be a specific thermal Functional Characteristics Power modules are generally used to amplify the transmit signals in a 2-way radio to the desired level for radiation by the antenna. They consist of several stages of amplification (usually common emitter, Class C except for some low level stages that are Class A) combined in a hybrid integrated assembly with nominally 50 ohm RF input and output impedances. Selection of a module involves choosing one having the proper operating voltage, frequency range, output power, 356 resistance from heatsink to each die. Thermal design of the module will take care of internal temperature rises provided the user adheres to the maximum rating attached to the operating case temperature range. This is an extremely important specification, particularly at the high temperature end because of two factors. First, exceeding the maximum case temperature can result in die temperatures that exceed +4 0 E '"os a: w +3 0 ak MH~~=B20MHZ -J,.. T f-I = 0.. >- :::> 0.. >- +2 0 S -- Vsl = BV Vs3 = 12.5 V :::> 0 0..0 -= ---= Pin = 1 mW +1 0 r 2 temperatures as low as 125'C. Again, the power to be dissipated can be determined by considering the RF output power and the minimum efficiency of the module. For example, for the MHW607, output power is 7 watts and input power is 1 mW; efficiency is 40% minimum. Thus the DC power input must be 7/0.4 =17.5 watts. It follows that power dissipation would be 17.5-7 = 10.5 watts worst case. Storage temperature maximum values are also important as a result of the melting temperatures of solder used in assembly of the modules. Another factor is the epoxy seal used to attach the cover to the flange. It is a material similar to that used in attaching caps for discrete transistors and, as stated earlier, is known to deteriorate at temperatures -- II (/ ;;: 0 200'C. This, in turn, will lead as a minimum to decreased operating life and as a maximum to catastrophic failure as a result of thermal runaway destroying the die. Second, hybrid modules have components that are normally attached to a circuit board and the circuit board attached to the flange with a low temperature solder which may become liquid at - r f-f-- 3 4 5 6 7 B VConl, GAIN CONTROL VOLTAGE (Vdcl 10 ICONT. -130 mA@VCONT. = 9 V Figure 2B. Output Power versus Gain Control Voltage I I I Pin=1 mW vsI = vs2 = vs3 = 6 V ./'" U;. 7' ~ /' _f=B50MHz BOO _ 920 AV greater than 150'C. Modules designed for use in cellular radios require wide dynamic range control of output power. Most modules provide for gain control by adjusting the gain of one (or two) stages by means of· changing the voltage applied to that stage(s). Usually the control is to vary the collector voltage applied to an intermediate stage. A maximum voltage is stated on the data sheet to limit the control voltage to a safe value. This form of gain control is quite sensitive to small changes in control voltage as is evidenced by viewing the output power versus control voltage curves provided for the user (an example is shown in Figure 28). An alternative control procedure which uses much less current is to vary the base-to-emitter voltage of the input stages (which are generally class A) as illustrated in Figure 29. This is of particular significance in portables because of the power dissipated in the control network external to the module. While not stated on most data sheets, it is always possible to control the output power of the module by controlling the RF input signal. Normally this is done by means of a PIN diode attenuator. Controlling the RF input signal allows the module to operate at optimum gain conditions regardless of output power. Under these conditions, the module will produce less sideband noise, particularly for srnall values of output power, when compared to the situation that arises from gain control by gain reduction within the module. Noise produced by a power module becomes significant in a duplexed radio in the frequency band of the received signal (see Figure 30). A specification becoming more prominent, therefore, in power modules is one that controls the maximum noise power in a specified frequency band a given 7{: 00 I 2 3 4 VConl, GAIN CONTROL VOLTAGE (Vdcl ICONT. -100 ~lA @ VCONT. = 4 V Figure 29. Output Power versus Control Voltage distance from the transmit frequency. Caution must be taken in making measurements of noise power. Because the levels are generally very low (--85 dBm), one must be assured of a frequency source driving the module that has extremely low noise. Any noise on the input signal is amplified by the module and cannot be discerned from noise generated within the' module. Another precaution is to be sure that the noise floor of the spectrum analyzer used to measure the noise power is at least 10 dB below the level to be measured. DATA SHEETS OF THE FUTURE World class data sheets in the next few years will tend to provide more and more information about characteristics of the RF device; information that will be directly applicable by the engineer in using the device. Semiconductor manufacturers such as Motorola will provide statistical data about parameters showing mean values and sigma deviations. For discrete devices, there will be additional data for computer aided circuit design such as SPICE constants. The use of typical values will become more widespread; and, the availability of statistical data and the major efforts to make more consistent products (six-sigma quality) will increase the usefulness of these values. 357 SUMMARY POUT 33dBm 11 TRANSMIT SIGNAL (806-940MHz) o / 4 5 MHz ~85dBm 30KHz RECEIVE BAND MAXIMUM NOISE POWER -- FREQUENCY Figure 30. Noise Power in Receive Band Understanding data sheet specifications and what they mean can be a major asset to the circuit designer as he goes about selecting and using RF semiconductors for his specific application. This paper has emphasized some unique data sheet parameters of RF transistors and amplifiers and has explained what these mean from the semiconductor manufacturer's point-of-view. It is hoped this effort will help the circuit engineer make his selection and use of RF semiconductors more efficient and effective. The RF transistor and the amplifiers made with RF transistors are unusually complex semiconductor products and difficult to fully characterize. Not all information about RF device characteristics has been explained in this paper. Nor can all be covered in a data sheet. The circuit design engineer should contact the device manufacturer for more detailed information whenever it is appropriate. Most if not all current manufacturers of RF transistors and amplifiers have extensive applications support for the express purpose of assisting the circuit designer whenever and wherever assistance is needed. 358 AN1122 Running the MC44802A PLL Circuit Prepared by Paul Brownlee/Linear Applications Bipolar Analog IC Division INTRODUCTION The MC44802A is the PLL portion of a tuning circuit intended for applications involving television, FM radio, and Set-Top converters up to 1.3 GHz. Coupled with a VCO and mixer, a complete tuning circuit can be formed. The tuning frequency is controlled through an MCU serial interface (12C). As noted in the MC44802A data sheet, an MCU is recommended for sending the serial control bytes. This application note describes combining an MC68HCll E9 with an MC44802A in a tuner design. The information is sufficiently general however, that most any MCU could be used for this function. Those with a limited background in the use and programming of MCUs will find the information adequately detailed to permit a thorough understanding. - 12C interface for MCU control. Selectable +8 prescaler and a 15-bit divider accept frequencies up to 1.3 GHz. Programmable reference divider. Phaselfrequency comparator output can be set to high impedance for disabling. Op amp provides direct tuning voltage output (0.3 V to 30 V). Seven programmable output buffers (10 mA, 12 V) for band switching, etc. Output options for 62.5 kHz, reference frequency and the programmable divider which are useful for system debugging. Figure 1 shows a simplified block diagram of the MC44802A. The 12C Bus receiver is a central block that controls the HF prescaler, 15-bit divider, the oscillator (typ. 4.0 MHz crystal) reference divider, and the output buffers. A Look at the MC44802A The MC44802A is manufactured using Motorola's high density bipolar MOSAIC process. It features: VCC1 Progr. Relerence Divider 1953 Hz 3906 Hz 7812 Hz 15625 Hz Phase Comparalor Figure 1. MC44802A Simplified Block Diagram 359 17 The 12C Bus transfer is initiated by a master and acknowledged by a slave device. Each slave is assigned a unique address, allowing multiple 12C devices to be connected to a single bus. An example of a data transfer is shown in Figure 2. The 12C (Inter-Integrated Circuit) Bus required by the MC44802 is a serial transfer process using two wires for data and clock (SDA - serial data, SCL - serial clock). Each tOLE SDA START r--' \ I I I 1flJi\ :~ MI' ADDRESS I I I I 8 L ADDRESS BITS I I I I SCL ADX DATA ACK uf*\,-__~: .!, ,;-AL_BYT- -,; STOP ~ _ _ _-+-,r : I I I ACK DATA I ACK L_-' Figure 2. Complete Data Transfer Process Referring to Figure 2: Idle - When there are no transfers taking place on the bus, SDA and SCL idle high. Start - A master initiates a data transfer by pulling SDA low while maintaining SCL in the high state. At this time all slave devices on the bus are listening for their address. Address - The first byte is senllo select a slave device(s). Slaves that have read and write capabilities have a unique address for each. Upon completion of an address transmission, the master must leave the data line high and create the ACK clock pulse. The slave device is to acknowledge by pulling the data line to a stable low state before the end of the ACK pulse. From this point until a Stop Condition is generated, only the.selected slave(s) device is active. Data - The transfer continues with data bytes sent in the same manner as the address byte. An acknowledge is required at the end of each byte (except the last one). The master indicates the last data byte by sending the acknowledge (low) bit rather than leaving SDA high for slave acknowledge. Stop - The master creates a Stop Condition by sending SCL high followed by a low-to-high SDA transition. This leaves the bus back in the idle state. If a required acknowledge bit is not received for any reason, the master terminates the transfer and generates a Stop Condition. The Microcontroller The MCU chosen for an 12C data transfer must have a serial port with the following characteristics: - Two-lines, clock and data, with open drain (collector) outputs - 8-bit transfer buffer - An 12C interface or 1/0 serial lines capable of emulating 12C protocol (Idle, StarVStop conditions and ACK pulse). Suitable microcontroller examples are the MC68HCll or MC68HC05 families. A SAMPLE SYSTEM Overview The remainder of this application note is devoted to describing a sample MC44802A system. From a high level view this system is simple (see Figure 3). Whenever the push button is pressed the circuit responds by changing the tuning frequency, and provides a display indicating the frequency. The following paragraphs describe this system which was built and tested to demonstrate the functionality of the MC44802A. Included are descriptions of each segment of this system - PLL tuning circuit, MCU control, user interface and LED displays. A Pushbutton Switch Circuit Interrupt U Latch A MCU II Irc Bus '5 V L-. SDA PLL SCL .~ 3-Digit Frequency Display Figure 3. Simplified Block Diagram of the Video Frequency Controller 360 PLL Tuning Circuit Implementation The MC44802A works with an MC1648 voltage controlled oscillator (VCO) to form a Phase-Locked Loop (see Figure 4). The MC1648 requires an external parallel tank circuit consisting of an inductor (L) and capacitors (Cv and Cx). Varactor diodes (Cv) are used in this case to provide a voltage variable capacitance for the VCO. The MC1648 may be operated from a +5.0 or -5.2 Vdc supply, depending upon system requirements (+5.0 V in this case). Its maximum frequency is typically 225 MHz. The VCO output is connected through a capacitor to the phase detector input of the MC44802A. With the feedback network (G(s)) the MC44802A produces a stable vOltage input to the tank circuit. A general purpose open collector output buffer (B2, Pin 9) is used in this application to switch a capacitor (Cx) in and out of the tank circuit. When that output buffer is switched low (by writing a "1" to it), the pin diode (Dl) conducts making Cx part of the tank circuit (Cx//(Cv/2)). When the output buffer is open Dl does not conduct, thereby presenting a high impedance to Cx, making it ineffective. The tank circuit's capacitance is then Cv/2. 1 r - - -.......-~10 14 MC1648 VCO +-__......_--J'-j 12 Fosc 0.1 ~F r------------------,I I G(s) 47 nF I I I I _ _ _ _ _ _ _ _22_k _ _ I I I _JI 22 k ~ +33 V _~ >'-_...v:tu=n_e__- ++_-_-_-_-_-_- ...._-_-_-_-_--j-ll :sJ--d4802A PLL 2 +5.0 V I :~ I 1.0 of 1.0 nF >---+--....,.---,--1 14 , I I I I 0.1 ~F I Band I Switching L _ _ _ _ _ _ _ _ _ _ _ _ _ _ -'I 16 15 4.0 MHz 2.0 k r --.., I 12C I I Bus I I 1: l_ 12pF I _ _ ...I ~ seL SOA Figure 4. Sample PLL Tuning Clrcuil 12C Data a CA - Chip Address Configuration data is sent by the MCU to the MC44802A 12C Bus Interface in five bytes as shown in Figure 5. Communication of the data is covered in the section describing MCU Implementation. R2 Rl RO B2 Bl BO N14 N13 N12 NIl Nl0 N9 N8 CO - Control Info. BA - Band Info. FM - Frequency Info. 0 FL - Frequency Info. N7 N6 N5 N4 N3 N2 Nl Figure 5. MC44802A j2C Byte Definitions 361 a NO Referring to Figure 5: CA - 12C chip address for the MC44802A, $C2 (fixed internally). CO- Sets up the 4.0 MHz oscillator divider ratio (R1, RO), prescaler (P), test outputs (R2, R3) and phase comparator output state (R2, R6, T) according to Figure 6. BA - Each band buller (Pins 7-13) can be setto active low by writing a 1 to it. FM, FL - These two bytes set the tuning frequency. Their relationship with frequency (at Pin 4) depends on whether or notthe prescaler is enabled, and the setting olthe reference division ratio: N = Fout x Divider ratio Rl RO Divider Ratio 0 0 I 1 0 I 0 2048 1024 512 256 or: N = -""'-'----c:-Fcrystal x 8 P Prescaler 0 1 Enabled Bypassed R2 R3 Pin 10 Pin 11 0 0 1 1 0 1 0 1 - - (prescaler disabled) Fcrystal Fout x Divider ratio 1 62.5 kHz F (ref) A hexadecimal representation of N at FM and FL sets the tuning frequency (Fout). Per Figure 5. the address is sent and followed by CO, BA andlor FM. FL. Control and frequency byte pairs are distinguished in the first bit (1 for control, 0 for frequency). Therefore, it is not necessary to always send 5 bytes. A data transfer could consist of CA-CO-BA, or CA-FM-FL. The following example describes the five hex control bytes required to instruct the circuit to tune to VHF Channel 2 (101 MHz): 1) $C2(11000010) - This isthe MC44802A address. The first byte of all MC44802A transmissions must be $C2. 2) $88(10001 000)-R2, R6andTare setto OOOto indicate normal operation. P=O enables the internal prescaler. R1, RO=OO sets the divider ratio to 2048 which gives the greatest frequency resolution in the < 512 MHz region. R3 is optionally set high to output a 62.5 kHz test signal at Pin 10 (B4). 3) $04 (0000 0100) - Sets band buller B2 (Pin 9) high thereby disabling Cx. 4) and 5) $1940 (0001 1001,01000000) - With the given prescaler and divider values, the frequency is defined by N = Fout115,625 Hz. For 101 MHz: 101 MHz = 6464 15,625 Hz which is represented in hex by $19 40. FBY2 - (prescaler enabled) R2 R6 T 0 0 a a a 0 0 1 1 1 1 1 1 a a 1 1 1 a 1 0 1 0 1 - Phase Comparator Output State Normal Operation Off (High Impedance) High Low Normal Operation Off (High Impedance) Normal Operation Off (High Impedance) Figure 6_ CO Bit Specifications FM FL $02 $06 $08 SOC $12 $19 $19 $80 $40 $CO $80 $CO $00 $40 Fout{MHz) Display FM 10 25 35 50 75 100 101 (ch2) None None None None 075 090 CO2 $IA $IC $IE $20 $25 $2A $32 FL Fout{MHz) Dlsplal $CO $40 $CO $40 $80 $80 $00 107 (ch3) 113 (ch4) 123 (ch5) 129 (chS) 150 170 200 C03 C04 C05 COS 150 170 None P.O. RO.R1-0 Figure 7_ Sample Frequency Control Bytes N Note that this is not a unique solution to getting 101 MHzout of the circuit since a dillerent combination of prescaler setting, divider ratio and N could be used. Figure 7 shows a table offrequency control bytes (FM, FL) used in this application note. In all cases the internal prescaler is enabled, and the divider ratio is 2048. sample MC44802A interface to this MCU. A full listing of the code is included in the Appendix. An HC1'1 program is written without line numbers. The code shown is the 'program.lst' ver. sion created by the assembler which inserts the line numbers and machine code. Pin Descriptions Note that only the HC 11 pins used in this exercise are shown in Figure 8. Many olthe I/O pins can be configured fordillerent functions throughout the. execution of a program. This is noted by pins labeled name1/name2. The names in bold indicate the functions used. They will be referred to by their functional name from here forward and are briefly explained below. Refer to the Appendix for code lines. IC3 - (Input Capture 3) is an edge triggered interrupt pin that can be configured for rising, falling, or both edges. It is configured to respond to rising edges (code lines 70 and 71). Ali controller output changes are initiated at this pin. MCU Implementation The Motorola MC68HC11 E9 has the required characteristics for generating 12C transfers. It is equipped with parallel and serial 110 ports, timers, a pulse accumulator, an AID converter system and expansion capability for multiple MPU systems. Each of these functions must be set-up and activated in user-programmed software to be part of the system. This allows the user to be concerned with only applicable functions. What follows are hardware and software descriptions for the 362 ~ I I I 1 59 +5.0 Vdc I 60 57 58 SS 25 I Pushbutton Switch I PAO/IC3 I----u- 22 MCU MC68HC11E9 PD3/MOSI 23 STRB I--- SDA MC44802A PLL 6 24 27 •••• 30 - '( PD2/MISO 34 PA71 OC1 +30 Vdc 2.4 k I-- ...... ...... PD4/SCK SCL 35·····42 PA41 OC4 PB71 A15 ...... . ..... +5.0V PBOI AS ~ ~ut FO 2.4 k 3·Digit Frequency Display Figure 8. MCU Implementation SPI (Serial Peripheral Interface) Pins: MOSI- (Master Out Slave In) is the serial output line used for 12C data communication with the PLL chip. The con· troller is configured as the master device in this exercise. This line is referred to as PORT D, bit 3 when the SPI is disabled (the SPI is enabled only during a serial transfer). It is essential that this be configured as an open drain out· put (an external pullup is used) when programming the SPI Control Register (SPCR, code lines 122-123). This allows the slave device (the PLL) to acknowledge by pulling the data line low. MISO - (Master In Slave Out) is a serial input line to the controller. Tied to MOSI, it forms a bi-directional data port permitting the MCU to read the acknowledge pulse. SCK - is the clock line in the 12C protocol. It is referred to as PORT D, bit 4 when the SPI is disabled. SS - is a slave select line that must be tied high (inactive) to set the MCU as the master. Software Description The software is written in two functional blocks - a main program and an interrupt service routine (ISR). The main program sets up the MCU ports and control registers. It then goes into a low power stopped state until an interrupt is initiated. The interrupt service routine creates the required serial and parallel output signals, and then returns control to the main program which waits for another interrupt. The interrupt structure provides flexibility for expansion of this system. Other functions can be easily added to the main program without affecting performance of the serial interface. But for this exercise, the main program is kept simple. It sets up memory address references (lines 20-38), parallel Port A (lines 46-48), parallel Port B (line 51) and the interrupt control (lines 66-73). The main program then goes into its low power wait state. It does nothing until control is transferred to the ISR. An ISR flow diagram is included as Figure 10 for clarification. The following program was written under the assumption that eventually the system will be run as a stand alone. Thus, the serial bytes pertaining to tuning requirements must be stored in the MCU EEPROM. To avoid program modification each time such requirements change, data space has been allocated for this function beginning at location B700. The program requires a specific data format while maintaining application flexibility. The first requested transfer will output bytes starting at location B700. Transmission continues until a null data byte ($00) is encountered (which is not outputted). The two bytes following contain the display information. Transmissions of this format should follow consecutively as desired with another null after the last display value. 'The program will then reset the Port A Pins: PA7- is a general 1/0 pin. It must be configured as input or output depending on the desired function. It is configured here as an output (code lines 46-48) to drive a bit in the seven segment display (in conjunction with PA6-PA4). PA6 to PA4 - are fixed direction output pins also used for the seven segment displays. Port B Pins: PB7 to PBD - are fixed direction output pins used for the seven segment displays. STRB - is an enable line that provides an active low pulse each time new data is written to Port B. This is used to latch data into the display decoders. 363 data pointer to 8700. Figure 9 shows the frequency data space for the sample system. It contains bytes for various frequencies from 75 MHz to 170 MHz. 8and switching is done between the 90 MHz and 101 MHz (VHF Channel 2) frequency values. 8700> c2 88 0412 cO 00 Of 75 c21610 00 Of 90 c2 88 8710> 0119 40 00 cf 02 c21a cO 00 cf 03 c21c 40 00 8720> cf 04 c21e cO 00 cf 05 c2 20 40 00 cf 06 c2 25 8730> 80 00 11 50 c2 2a 80 00 11 70 00 If If If If If Note that this example contains two five-byte transmissions and the remainder are three-byte transmissions. Three-byte transmissions are useful as unchanged control, and band information need not be repeated. The displays will cycle through '075', '090', 'C02', 'C03', 'C04', 'COS', 'C06', 'ISO', and '170' which is a mix of frequency (in MHz) and VHF channel displays. The lower four-bits of the first display value (set to f) are ignored since they are unconnected. Figure 9. Sample System Control Data No Reset Pointer to Top of Data Space Pulse Figure 10.ISR Flow Diagram 364 Figure 11 is a picture of the first byte of a transmission (the PLL address). Note that the start condition is generated at the scope trigger point and the bit stream 11000010 ($C2) is clocked in on rising edges. After the eighth clock pulse, the data line is released by the MCU and quickly acknowledged (pulled low) by the PLL chip. Refer back to Figure 2. high when the button is released. The cross-coupled NAND gates eliminate the effect of switch bounce. r-----------------,I I IC3 I I I I I I I I I t;,Vl = 4.96 V t;,V2 = 0.40 V ~ ___ ~ _____________ J Figure 13. Pushbutton Interrupt Circuit This will provide a clean low-going pulse to trigger one of the controller's edge-sensitive interrupts (IC3). IC3 is programmed to respond to the rising edge of the pulse to facilitate further debouncing in software. 2V 5V PEAKDET 20 ~s Frequency/Channel Display Implementation Tek The display is implemented using three seven-segment (common cathode) LEDs. They are driven by parallel ports (A and B) of the controller in the ISA. These ports send the display information to the hexadecimal-to-seven segment decoders (MCI4495-1). The STRB output from the controller is pulsed low each time data is written to Port B and is used to latch the decoders. Display information is programmed in data space as shown in Figure 9. Outputs are done in the ISR to Port A (lines 147-148) and then to Port B (lines 150-151), and are done in this order because a write to Port B causes the STRB decoder enable pulse. Figure 14 shows the frequency display circuit. The MC14495-1 is a hexadecimal-to-seven segment Latch/ Decoder Driver. It is an improved version of the MC14495 with CMOS input levels and decreased propagation delays. This permits them to be operated directly from the limited duration pulse (STRB) generated by the MCU. The MC14495-1 has internal series output resistors (typically 290 il) allowing direct co·nnection to a common cathode LED display. Figure 11. PLL Address Transmission If the PLL were not responding, the data line would have remained high ratherthan looking like aspike. This acknowledge is clocked in and the next byte is ready for transmission. Figure 12 illustrates this by showing a full three-byte transmission that updates the PLL tuning frequency. t;,Vl = O.OB V t;,V2 = 0.20 V SUMMARY 2V 5V PEAKDET 0.1 ms This application note should serve as a reference for using an MC44802A for various tuning applications. It is not intended as a replacement for the MC44802A Data Sheet nor the MC68HC11 Reference Manual. Its intention is to help bring these tools together to build a working system. Tek Figure 12. Three Byte Data Transmission Interrupt Circuitry Implementation Bibliography The interrupt circuit (Figure 13) is designed as a simple debounced momentary pushbutton switch. The switch must have a normally open (N/O) and a normally closed (N/C) contact. The output of the circuit is normally at VCC (+5.0 V). When the button is pushed the output goes low. It comes back (1) (2) (3) (4) (5) 365 MC44802A Data Sheet MC1648 Data Sheet M68HCll E9 Data Sheet M68HCll EVBU/ADI MC14495-1 Data Sheet STRB PA7 PA6 PAS PM PB7 PB6 PBS PB4 PB3 PB2 PBl PBO --- I - - -- - ------ - - -r------- r-- -- -- -- , r 0 10 L.7 LE C 9 B A 5 6 MC14495-1 ,,- 10 -7 A B 6 9 S MC14495·1 7{' ~ 0 L.. .,7 10 9 A B C 6 S MC14495·1 LE LE 7,f ~C C 0 I-I c,_, -, * c,= 71' _____________________________________ J Figure 14. Three Digit Display Circuit APPENDIX 1 - Microprogramming Basics/ Program Listing The M68HCll EVBU (Universal Evaluation Board) pro· vides a friendly environment for developing an HCll system. Programming is a three step process which includes writing software, assembling it, and downloading it to the MCU. sembler. This program will generate the necessary object code and, if desired, a listing file. The object file (xxxx.list) is then downloaded into the HC1l: program. list - listing file, program.s19 - file to be downloaded. Writing/Modifying Software Software should be created as a text file (e.g., pro· gram.asm) following the format of HCll assembly com.· mands. Full description of each command can be found in the M68HC 11 Reference Manual. Program Assembly Once a program has been written, it is run through an as· Downloading/Debugging Performance of the software and hardware should be evaluated with the help of a personal computer (Macintosh or a PC compatible) and a terminal emulation package such as Freeterm or Kermit. This program allows communication between the EVBU and computer. 366 APPENDIX 2 0001 0002 0003 0004 0005 0006 0007 0008 0009 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 00200000 00210004 00220002 00230026 00240008 00250028 0026002a 00270029 00280009 00290022 00300023 0031 0021 0032 00330000 00340001 0035 00360000 003700e2 003800e3 0039 0040 0041 0042 b600 0043 b600 ce 10 00 0044 0045 0046 b603 a6 26 0047 b605 8a 80 0048 b607 a7 26 0049 0050 0051 b609 ld 02 ff 0052 0053 0054 b60c 86 af 0055 b60e a7 00 0056 b61 086 bc Program Listing • Motorola SPS - Bipolar Analog IC Division • Written by Paul Brownlee • • • • • This M68HCll code provides control bytes to operate an MC44802A (Motorola PLL Tuning Circuit) via 12C protocol The bytes are to be determined by the user and placed in memory starting with location B700 (see technical data sheet for control byte information). • • • • • • • • Communication is achieved using the HC 11 's Synchronous Serial Peripheral Interlace (SPI) to generate both the clock.and data signals. The main program is a short monitor loop. Output is implemented as an interrupt service routine for the edge triggered interrupt IC3. Thus, the location to the routine, B640, must be entered in user RAM as a jump destination for the IC3 service routine. The interrupt can then be implemented as a simple debounced switch. • REFERENCED TO X-OFFSET ($1000) PORTA EQU $00 PORTB EQU $04 PIOC EQU $02 EQU $26 PACTL PORTO EQU $08 EQU $28 SPCR EQU $2A SPDR EQU $29 SPSR DDRD EQU $09 EQU $22 TMSKI TFLGl EQU $23 TCTL2 EQU $21 • REFERENCED TO Y-OFFSET (STARTS DATA EQU $00 NEXTO EQU $01 • REFERENCED TO 0000 YSTOR EQU $0000 IC3JMP EQU $E2 $E3 IC3JMPl EQU PORT A DATA REGISTER PORT B DATA REGISTER PARALLEL 1/0 CONTROL PULSE ACC CNTRL REG (PORT A) PORT D DATA REGISTER SPI CONTROL REGISTER SPI DATA REGISTER SPI STATUS REGISTER PORT D DATA DIRECTION REGISTER REGISTER FOR INPUT CAPTURE ENABLE REGISTER FOR INPUT CAPTURE STATUS REGISTER FOR INPUT CAPTURE CONTROL AT $B700) DATA SPACE (REL DATA POINTER) NEXT DATA BYTE POINTER RAM LOC FOR CONTROL DATA THE LOCATION FOR IC3 JUMP INST LOC. TO PLACE THE JMP ADX ••••••••••••••••••••••••••• MAIN PROGRAM ••••••••••••••••••••••••••• ORG $B600 LDX #$1000 • PORT A SET-UP (FOR HIGH LDAA ORAA STAA • BASE FOR CONTROL REGISTERS ORDER 7 SEG DISPLAY OUTPUT) PACTL,X • SET PORTA, BIT 7 TO #$80 • AN OUTPUT PORT PACTL,X • PORT B SET-UP (FOR 2 LOW ORDER 7 SEG DISPLAY OUTPUTS) BCLR PIOC,X $FF • SIMPLE HANDSHAKE MODE • TEST OUTPUTS LDAA STAA LDAA #$AF PORTA,X #$BC 367 • PUT AN 'A' IN THE HIGH • HEX DIGIT • AND A 'BC' IN THE LOW APPENDIX 2 0057 b612a7 04 0058 0059 b614 18 ce b7 00 0060 b618 18 df 00 0061 0062 0063 b61b 8e 00 If 0064 0065 0066 b61e 86 7e 0067 b620 97 e2 0068 b622 ce b6 40 0069 b625 dd e3 0070 b627 86 01 0071 b629 a7 21 0072 b62b 1e 22 01 0073 b62e Oe 0074 0075 0076 b621 0077 b621 01 0078 b630 el 0079 b631 20 Ie 0080 0081 0082 0083 0084 b640 0085 0086 b640 0087 b640 86 64 0088 b642 18 ee 03 e8 0089 b646 18 09 0090 b648 26 Ie 0091 b64a 4a 0092 b64b 26 15 0093 0094 b64d 18 de 00 0095 b650 Ie 0810 0096 0097 0098 0099 0100 0101 0102 0103 b653 0104 b65318 e6 00 0105 b6561d 28 40 0106 b6591e 08 08 0107 b65e 8638 0108 b65e a7 09 0109 b660 el c2 0110 b662 26 03 0111 Program Listing (continued) STAA PORTB,X • FOR LED DISPLAYS LDY STY #$B700 YSTOR • SET MEMORY POINTER • INITIALIZE USER STACK POINTER LDS #$FF • STACK STARTS AT $FF WHICH • INTERRUPT PREPARATIONS LDA #$7E STAA IC3JMP LDD #$B640 STD IC3JMPI LDAA #$01 STAA TCTL2,X BSET TMSKI ,X $01 CLI • • • • • • • • • MAIN PROGRAM DO NOTHING LOOP MONITOR EOU NOP STOP BRA MONITOR SIT HERE AND DO NOTHING UNTIL • SAVE POWER IN STANDBY MODE • INTERRUPT OPCODE FOR JMP INST LOADED INTO RAM SET THE JUMP LOCATION FOR THE INT SERVICE ROUTINE INPUT CAPTURE (IC3) SET FOR RISING EDGE ENABLE THE IC3 ENABLE ALL NON-MASKED INTERRUPTS ........................... INTERRUPT SERVICE ROUTINE ........................... ORG $B640 START OUTERD DELAY LDAA LDY DEY BNE DECA BNE • DELAY FOR SOFTWARE DELAY • DEBOUNCING OF • INTERRUPT CIRCUIT OUTERD LDY BSET • • • • • EOU #100 #1000 YSTOR PORTD,X $10 • LOAD POINTER • SET D BIT 4 HIGH (IDLE) THE REMAINING LOOP IS EXECUTED AS MANY TIMES AS THERE ARE BYTES TO BE OUTPUTTED. IT STARTS AT B700 (OR WHEREVER IT LEFT OFF ON PREVIOUS INTERRUPT HANDLED) AND OUTPUTS UNTIL A NULL BYTE (00) IS FOUND (00 IS NOT OUTPUTTED). THE NEXT TWO BYTES ARE DISPLAYED AND THE POINTER UPDATED. LOOP EOU DATA,Y SPCR,X$40 PORTD,X$08 #$38 DDRD,X #$C2 NOSTART LDAB BCLR BSET LDAA STAA CMPB BNE • (IF FIRST DATA BYTE) 0112 368 • • • • LOAD THE PRESENT BYTE DISABLE SPI SET D BIT 3 HIGH (IDLE) SS=I, SCK=MOSI=1 • CHECK DATA TO SEE IF A • START CONDITION IS REO APPENDIX 2 0113 0114 0115 0116 0117 0118 0119 b664 0120 b664 ld 08 08 0121 b667 0122 b667 86 73 0123 b669 a7 28 0124 b66b lc 08 08 0125 b66e e7 2a 0126 b670 a6 29 0127 b672 2a fc 0128 0129 b674 ld 08 10 0130 b677 a6 28 0131 b679 84 bf 0132 b67b a7 28 0133 0134 b67d 18 6d 01 0135 b680 26 3a 0136 0137 b6821d 08 08 0138 b6851c 0810 0139 b688 21 f8 0140 b68a ld 08 10 0141 b68d lc0810 0142 b690 lc 08 08 0143 0144 b69318 08 0145 b69518 08 0146 b697 ld 02 II 0147 b69a 18 a6 00 0148 b69d a7 00 0149 b69f 18 08 0150 b6al 18 a6 00 0151 b6a4 a7 04 0152 0153 b6a618 08 0154 b6a818 df 00 0155 b6ab 18 6d 00 0156 b6ae 2607 0157 b6bO 18 ce b7 00 0158 b6b418 df 00 0159 0160 b6b7 86 01 0161 b6b9 a7 23 0162 b6bb 3b 0163 0164 0165 0166 b6bc lc 0810 0167 b6bf a6 08 0168 b6cl 8404 0169 b6c3 26 09 0170 b6c5 21 f5 • • • • • Program Listing (continued) This se~ment transfers a byte from the HCll's SPI to the I C peripheral. Upon Entry, data is in Acc B, w_start is the entry point for sending a start bit. nostart is the entry point for transferring data without a start condition, W_START WAIT LO_ACK SETPTR MODATA HI_ACK BCLR NOSTART LDAA STAA BSET STAB LDAA BPL EQU PORTD,X$08 EQU #$73 SPCR,X PORTD,X$08 SPDR,X SPSR,X WAIT • • • • • • ENABLE SPI (SPE=l); MASTER CPOL=CPHA=O; BITRATE=CLKl32 RETURN PD3 TO IDLE STATE WRITE DATA WAIT FOR END OF XMISSION IF NOT, WAIT BCLR LDAA ANDA STAA PORTD,X$10 SPCR,X #$BF SPCR,X • • • • LEAVE SCLK (PD4) LOW CREATE ACK PULSE CLEAR SPE, DISABLE SPI CAUSES PD4 (SDA) TO GO HIGH TST BNE NEXTD,Y HI_ACK • TEST NEXT BYTE, IF<> 0 • SLAVE GENRTS ACK (LOW) BCLR BSET BRN BCLR BSET BSET PORTD,X$08 PORTD,X $10 LO_ACK PORTD,X$10 PORTD,X $10 PORTD,X$08 • • • • • • ELSE, CLEAR ACK BIT GEN ACK CLOCK INSURE PULSE WIDTH CLOCK LOW GEN STOP CONDITION PNT TO FREQ VALU SIMPLE HANDSHAKE MODE LOAD MSB OF FREQ VAL AND OUTPUT IT MOVE POINTER LOAD 2LS DIGITS AND OUTPUT THOSE POINT TO NEXT GROUP SAVE NEW POINTER CHECK FOR LAST GROUP IF NOT, KEEP YSTOR ELSE RESET POINTER TO TOP OF DATA • START CONDITION INY INY BCLR LDAA STAA INY LDAA STAA DATA,Y PORTB,X • • • • • • • INY STY TST BNE LDY STY YSTOR DATA,Y MODATA #$B700 YSTOR • • • • • • PIOC,X $11 DATA,Y PORTA,X LDAA STAA RTI #$01 TFLG1,X BSET LDAA ANDA BNE BRN PORTD,X $10 PORTD,X #$04 ERROR HI_ACK 369 • CLEAR INTERRUPT • STOP SERVICE OF OUTPUT • • • • • GENERATE ACK CLOCK CHECK FOR SLAVE ACK BEING A LOW BIT 3 IF NOT, BRANCH TO ERROR ENl:?URE CLK PULSE WIDTH APPENDIX 2 0171 b6c7 1d 08 10 0172 b6ca 1808 0173 b6cc 20 85 0174 0175 b6ce 86 ee 0176 b6dO a7 00 0177 b6d2 a7 04 0178 b6d4 7e b6 bO 0179 0180 ERROR Program Listing (continued) PORTD,X $10 BClR INY BRA LOOP lDAA STAA STAA JMP #$EE PORTA,X PORTB,C SETPTR 370 • BClR 4, PORTO • POINT TO NEXT DATA BYTE • • • • PRINT OUT AN 'EEE' TO INDICATE THAT THE SLAVE DIDN'T ACK END XMISSION ATTEMPT AN1207 The MC145170 in Basic HF and VHF Oscillators Prepared by: David Babin and Mark Clark Phase-locked loop (PLL) frequency synthesizers are commonly found in communication gear today. The carrier oscillator in a transmitter and local oscillator (LO) in a receiver are where PLL frequency synthesizers are utilized. In some cellular phones, a synthesizer can also be used to generate 90 MHz for an offset loop. In addition, synthesizers can be used in computers and other digital systems to create different clocks which are synchronized to a master clock. The MC145170 is available to address some of these applications. The frequency capability of the MC145170 is very broad - from a few hertz to 160 MHz. . before being fed to other sections of the radio. The VCM output can be directly used in computers and other digital equipment. The output.of a VCO or VCM is typically buffered, as shown. As shown in Figure 2, the MC145170 contains a reference oscillator, reference counter (R Counter), VCONCM counter (N Counter), and phase detector. A more detailed block diagram is shown in the data sheet. HF SYNTHESIZER The basic information required for designing a stable high.frequency PLL frequency synthesizer is the frequencies required, tuning resolution, lock time, and overshoot. Forthe example design of Figure 3, the frequencies needed are 9.20 MHz to 12.19 MHz. The resolution (usually the same as the frequency steps or channel spacing) is 230 kHz. The lock time is 8 ms and a maximum overshoot of approximately 15% is targeted. For purposes of this example, lock is considered to be when the frequency is within about 1% of the final value. ADVANTAGES Frequency synthesizers, such as the MC 145170, use digital dividers which can be placed under MCU control. Usually, all that is required to change frequencies is to change the divide ratio of the N Counter. Tuning in less than a millisecond is achievable. The MC145170 can generate many frequencies based on the accuracy of a single reference source. For example, the reference can be a low-cost basic crystal oscillator or a temperature-compensated crystal oscillator (TCXO). Therefore, high tuning accuracies can be achieved. Boosting of the reference frequency by 100x or more is achievable. HF SYNTHESIZER LOW-PASS FILTER In this design, assume a square wave output is acceptable. To generate a square wave, a MC1658 VCM chip is chosen. Per the transfer characteristic given in the data sheet, the MC 1658 transfer function, KVCM, is approximately 1 x 108 radians/ second/volt. The loading presented by the MC1658 control input is large; the maximum input current is 350 ~A. Therefore, an active low-pass filter is used so that loading does not affect the filter's response. See Figure 3. In the filter, a 2N7002 FET is chosen because it has very high transconductance (80 mmhos) and low input leakage (100 nA). ELEMENTS IN THE LOOP The components used in the PLL frequency synthesizer of Figure 1 are the MC145170 PLL chip, low-pass filter, and voltage-controlled oscillator (VCO). Sometimes a voltagecontrolled multivibrator (VCM) is used in place of the VCO. The output of a VCM is a square wave and is usually integrated DIVIDE VALUE REFERENCE OSCILLATOR REFERENCE OSCILLATOR TO LOW·PASS FILTER FROM VCONCM MULTIPLYING VALUE Figure 1. PLL Frequency Synthesizer Figure 2. Detail of the MC145170 371 +5V PLL FREQUENCY SYNTHESIZER R2 2.4kn LOW-PASS FILTER 16 +5V +5V 1.5 kil BIAS VCM 16 47 pF 0.01 J.!F 0.01 J.!F PDout MC145170 .:.~ MCI656 -= 0.01 J.!F lMn lMn -= 0.01 J.!F 0.01 J.!F OUTPUT PULLDOWN 510n LOW-PASS FILTER BUFFER/FILTER -= Figure 3. HF Synthesizer In order to calculate the average divide value for the N Counter, follow this procedure. First, determine the average frequency; this is (12.19 + 9.2)/2 = 10.695 MHz or approximately 10.7 MHz. Next, divide this frequency by the resolution: 10.7 MHzl230 kHz = about 47. Next, reference application note AN535 (see book OL 130/0 Rev 1). The active filter chosen takes the form shown in Figure 9 of the application note. This filter is used with the single-ended phase detector output of the MC145170, POout. The phase detector associated with POout has a gain K(J) = VOO/4". For a supply of 5 V, this is 5/4" = 0.398 V/rad. The system's step response is shown in Figure 4. To achieve about 15% overshoot, a damping factor of 0.8 is used. This causes frequency to settle to within 1% at ront = 5.5. The information up to this point is as follows. fref = 230 kHz fVCM = 9.2 to 12.19 MHz; the average is 10.7 MHz, average N = 47 power supply = 5 V for the phase detector KVCM = 1 x 108 rad/sN overshoot = approximately 15%, yields a damping factor = 0.8 lock time t = 8 ms settling to within 1%, ront = 5.5 Ko or Kp = 0.398 V/rad. From the application note, equation 61, ron = 5.5/t = 5.5/0.008 = 687.5 rad/s. Equation 59 is Rl C= (Kp Kv)/ron 2 N = (0.398 x 1 x 108 )/687.52 x 47 = 1.79 Equation 59 is used because of the high-gain FET. Next, the capacitor C is picked to be 1 J.!F. Therefore, R 1 = 1.79/C which is 1.79 Mil. The standard value of 1.8 Mil is used for Rl. Equation 63 is R2 = (2~)/C ron = (2 x 0.8)/(1 x 10-6 x 687.5) I.B ~;0.1 1.7 /0.3 Ir r\ 0.4 ,/"' K: 0.5 r< r0 0.6 0.7 1.5 1.4 >- u z W ::l 1.3 0 1.2 a: 1.1 ::l Q. I- ::l 0 cw N O.B :::J :;; 0.7 z 0.6 "'a:0" Bo 0.5 '" r----\ / '/-: t--- ~ r-£ 1 1.0 0.9 /"\ / ~~ w LL I- /0.2 / 1\ 1.6 -f ~ l o.B'1 1.0 2.0 "'\\- V-//'1/ VI \'--... II \ I----' \ \ / 0.4 0.3 0.2 0.1 o 1.0 2.0 3.04.0 5.0 6.0 7.0 B.O 9.0 10 11 12 13 14 "'nt Figure 4. Type 2 Second Order Step Response HF SYNTHESIZER PROGRAMMING Programming the MC145170 is straightforward. The three registers may be programmed in a byte-oriented fashion. The registers retain their values as long as power is applied. Thus, usually both the C and R Registers are programmed just once, right after power up. =2.33 kil. A standard value for R2 of 2.4 kil is utilized. 372 The C Register, which configures the device, is programmed with $CO (1 byte). This sets the phase detector to the proper polarity and activates PDout. This also turns off the unused outputs. The phase detector polarity is determined by the filter and the VCM. For this example, the MC1658 data sheet shows that a higher voltage level is needed if speed is to be increased. However, the low-pass filter inverts the signal from the phase detector (due to the active element configuration). Therefore, the programming of the polarity for the phase detector means that the POL bit must be a "1." The R Register is programmed for a divide value that results in the proper frequency althe phase detector reference input. In this case, 230 kHz is needed. Therefore, with the 4.6 MHz source shown in Figure 3, the R Register needs a value of $000014 (3 bytes, 20 in decimal). The N Register determines the frequency tuned. Tuning 9.2 MHz requires the proper value for N to multiply up the reference of 230 kHz to 9.2 MHz. This is 40 decimal. For 12.19 MHz, the value is 53 decimal. To tune over the range, change the value in the N Register within the range of 40 to 53 with a 2-byte transfer. Table 1 shows the possible frequencies. VHF SYNTHESIZER The MC145170 may be used in VHF designs, also. The range for this next example is 140 to 160 MHz in 100 kHz increments. VHF SYNTHESIZER LOW-PASS FILTER To illustrate design with the doubled-ended phase detector, the R and v outputs are used. This requires an operational amplifier, as shown in Figure 5. From the design guidelines shown in the MC145170 data sheet, the following equations are used: Ol =JKlpKVCO n NC Rl damping factor (1) (2) where, from the data sheet, the equation for the DATA IN +5V +5V 20 nH 2 x MV2115 R14 10k!} MCl648 1000pF I I ~~OPF Figure 5. VHF Synthesizer midpoints to ground to further filter the reference sidebands. The value of Cc is chosen so that the corner frequency of this added network does not significantly affect the original loop bandwidth wB. The rule of thumb for an initial value is Cc = 4/( Rl WRC), where wRC is the filter cutoff frequency. A good value is to choose wRC to be lOx WB, so as to not significantly impact the original filter. series with the rest of the circuit) is much smaller than C5 and can therefore be neglected for this calculation. As above, let WRC = 257,600 rad/s be the cutoff of this filter. Rl was previously chosen to be 10 kn. Therefore, C5 = _ _ 1_= _ _ _1_ __ wRCR14 (257,600)(10 kn) = 388 pF ~ (11) 390 pF (8) = 12,566)1+(2)(0.707)2+ h+(4)(0.707)2+ (4)(0.707)4 THE VARACTOR = 25,760 rad/s The MV2115 was selected for its tuning ratio of 2.6 to 1. The capacitance can be changed from 49.1 pF to 127.7 pF over a reverse bias swing of 2 to 30 volts. Contact your Motorola representative for information regarding the MV2115 varactor diode. For example, three parameters are considered. CT = Nominal capacitance CR = Capacitance ratio fR = Frequency ratio WRC = 10 wB = (10)(25,760) = 257,600 rad/s CC=_4_= 4 RlwRC (11.23 kn)(257,600 rad/s) = 1383 pF ~ (9) (10) 1500 pF There is also a filter formed at the input to the VCO. Again, this should be selected to ensure that it does not significantly affect the loop bandwidth. For this example, the filter is dominated by R14 with C5. The capacitance of the varactors (in CR= Cvmin = (Vmllx)P Cvmax· Vmin where P = the capacitance exponent 374 (12) Therefore, GR f max =2.6(~)P (13) log(2.6) = plog(15) (14) P = log(2.6)/log(15) = 0.3528 (15) 100 pF = (~\0.3528 (16) 4 V) (22) The frequency ratio is 1.5 to 1 and is impacted by the tuning range of the MV2115 varactor diode used in the tank circuit. Therefore, the required range of 140 to 160 MHz is not limited by this VCO design. A pc board should be used to obtain favorable results with this VHF circuit. The lead lengths in the tank Circuit should be kept short to minimize parasitic inductance. The length of the trace from the VGO output to the PLL input should be kept as short as possible. In addition, use of surface-mount components is recommended to help minimize strays. Using the nominal capacitance of 100 pF at 4 volts: Gvmax 1 = 173 MHz 21t[(19.9 nH)(42.2 pF)]0.5 VHF SYNTHESIZER PROGRAMMING 100 pF = 1.382 Gvmax Again, programming the three registers of the MG145170 is straightforward. Also, usually both the C and the R Registers are programmed only once, after power up. The C Register configures the device and is programmed with $00 (1 byte). This sets the phase detector to the correct polarity and activates the R and V outputs while turning off the other outputs. Like the HF oscillator, the phase detector polarity is determined by how the filter is hooked up and the VCO. The R Register is programmed for a divide value that delivers the proper frequency at the phase detector reference input. In this case, 100 kHz is needed. Therefore, with the 1 MHz crystal shown, the R Register needs a value of $OOOOOA (3 bytes, 10 in decimal). The N Register determines the frequency tuned. To tune 140 MHz, the value required for N to multiply up the reference of 100 kHz to 140 MHz is 1400 decimal. For 160 MHz, the value is 1600 decimal. To tune over the range, simply change the value in the N Register with a 2-byte transfer. Solving for Gvmax: 100 pF = 72.4 pF 1.382 Solving for Gvmin: 2.6= Gvmin 49.1 pF (17) Gvmin = (2.6)(49.1 pF) Gvmin = 127.7 pF THEVCO For convenience, the MG1648 VGO is selected. The tuning range of the VGO may be calculated as fmax = (Gdmax + Gs )0.5 fmin (Gdmin + Cs )0.5 ADVANCED CONSIDERATIONS (18) The circuit of Figure 5 may not function at very-high temperature. The reason is that the MG145170 is guaranteed to a maximum frequency of 160 MHz at 85°G. Therefore, there is no margin for overshoot (reference Figure 4) at high temperature. There are two possible solutions: (1) maintain the ambienttemperature at less than 60 o e, or (2) limit the tuning to less than 160 MHz. Operational amplifiers are usually too noisy for critical applications. Therefore, if an active element is required in the integrator, one or more discrete transistors are utilized. These may be FETs or bipolar devices. However, active filter elements are not needed if the veo loading is not severe, such as is encountered with most discrete veo designs. Because active elements add noise, some performance parameters are improved ifthey are not used. On the other hand, an active filter can be used to scale up the veo control voltage. For example, to tune a wide range, the control voltage may have to range up to 10 V. For a 5 V PLL output, this would be scaled by 2x via use of active elements. Some applications have requirements that must be met in the areas of phase noise and reference suppression. These parameters are in conflict with fast lock times. That is, as lock times are reduced, reference suppression becomes more difficult. Both reference suppression and phase noise are advanced areas that are covered in several publications. As an example, consider that the VCO input voltage range for the above VHF loop was merely picked to be 8 V. Advanced where fmin= 1 21t[L(Cdmax + Cs )]0.5 (19) As shown in Figure 8 of the data sheet, the VCO tank circuit is comprised of two varactors and an inductor. Typically, a single varactor might be used in either a series or parallel configuration. However, the second varactor has a two-fold purpose. First, if the 10 kQ isolating impedance is left in place, the varactors add in series for a smaller capacitance. Second, the added varactor acts to eliminate distortion due to the tank voltage changing. Therefore, with the two varactors in series, Gdmax' = Gdmaxl2. The shunt capacitance (input plus external capacitance) is symbolized by Cs . Therefore, solving for the inductance: L= 1 19.9 nH (27tfmin)2(Cdmax' + Cs ) = 20 nH (20) The Q of the inductor should be more than 100 for best performance. fmin 1 = 135 MHz 21t[(19.9 nH)(69.85 pF)]0.5 (21) 375 techniques demand a trade off between this voltage range and the spectral purity of the VCO output. This is because the lower the control voltage range, the more sensitive the VCO is to noise coming into its control input. A VCO IC may not offer enough performance for some applications. Therefore, the VCO may have to be designed from discrete components. Figure 6 shows the performance of the VHF Oscillator prototype on a spectrum analyzer. Note that the reference sidebands appear at 100 kHz as expected, and are 50 dB down. REFERENCES CMOS Application-Specific Standard ICs, book OL130/0, Motorola, 1990, MC145170 data sheet and AN535 application note. I 1\ I \ J \ (\ H I 100 kHz / .NJ!N' \ ~ CENTER =150 MHz, SPAN =250 kHz Figure 6. VHF Oscillator Performance 376 1\ ),\ I 100 kHz AN1306 Thermal Distortion In Video Amplifiers Prepared by: Curtis Gong Motorola RF Products Division Torrance, CA ABSTRACT signal, and can be explained using Figure 2. Notice after the transition from black to white (from high voltage to low voltage), the video signal is below the specified white level. This signal shows up on the display as a section "brighter" than white. The signal does eventually settle to the white level; but until it does, the display will appear brighter than it should be. Thermal distortion is a problem in many high resolution video amplifiers. Thermal distortion occurs when there are instantaneous power changes in the transistor stages. If the problem goes uncompensated, it leads to a visual el(ect known as smearing. This Application Note will discuss what smearing is, what causes thermal distortion, how to measure it and how to compensate the problem. WHAT CAUSES THERMAL DISTORTION? The transistors of a video amplifier are often subject to large instantaneous power changes because of the large voltage swings, particularly on transitions from black to white. These power changes cause changes in the transistor's junction temperature. Due to the transistor's thermal time constant, which is the amount of time it takes something to heat up or cool down, the transistor can't change temperature fast enough. It is this thermal time constant and the fact that VSE of a transistor changes with temperature, - 2 mV/oC, that causes thermal distortion. WHAT IS SMEARING? Smearing is best explained by using an example. Smearing, or ghosting, is most noticeable when a black block is displayed on an all white background. Referring to Figure 1, both Sections a. and b. should be the same brightness. When there is a smearing problem, Section b. will be brighter than Section a. This problem is related to the droop of the video a. BLACK - - - " T - - - - - - - - - - - - - - - LEVEL _______ ______ a. Figure 1. WHITE ~-=-------- Figure 2. 377 LEVEL Figure 3 shows a simple example that can be used to explain the thermal distortion concept. In the ideal case. where VBE does not change with temperature. there is a power swing of 107 mW across the transistor. Using the 107 mW and a thermal resistance of 30°CIW. we can see how this power swing affects the output in the real case. (A change in power of 107 mW would create about the normal junction temperature TE a change of ±1.6°C.) Notice on the plot of TJ. that the junction temperature does not change instantaneously. This is a result of the thermal time constant. Using - 2 mV/oC. we can calculate VBE; from there we can calculate VE. IE. and YO. This example clearly shows the distortion of the square wave. Ideal Case VIN (VOLTS) 40 +60 V 1K P(mW) VO(VOLTS) Vo 891 30 784 20 VSE 10 VE (VOLTS) .4 .3 Real Case TJ (OC) VSE(VOLTS) 1.1 .7032 VE (VOLTS) .4032 .3968 IE (mA) VO(VOLTS) 30.32 29.68 40.32 20.32 19.68 .3032 .2968'--_ _ _ _ _ _ __ Figure 3. 378 HOW TO COMPENSATE THE PROBLEM less than 100 mV is generally acceptable. Flatness of 50 mV - 100 mV for a 40 V swing is very difficult to measure. The effect of thermal distortion can be compensated. The Motorola CR2424 is used as an example to show some of the compensation techniques that can be utilized. The output waveform, when there is a distortion problem, appears as a signal with excessive mid and high frequency gain. The signal would be flat if this excessive gain were eliminated. One way of doing this is to use a series RC network as feedback from the output to the input. The CR2424 has an internal compensation network which noticeably improves the flatness. Unfortunately, this is only a first order compensation network and doesn't eliminate all problems. The flatness can be further improved by adding an external compensation net- There is no real standard on how small the distortion must be. Several years ago a 1% flatness was acceptable (400 mV for a 40 V swing). On today's high resolution displays, this is clearly unacceptable. A flatness of 200 mV for a 40 V swing will cause noticeable smearing problems. Some designers believe a 50 mV flatness is required, but anything work consisting of a 150 pF capacitor and a 200 kQ resistor. Figure 4 shows the flatness of the CR2424 without the internal compensation network while Figure 5 shows the flatness with the internal network. Note the considerable improvement in the flatness of the output waveform when the complete CR2424, including its internal compensation network, is used. Figure 4. CR2424 Without Compensation Figure 5. CR2424 With Internal Compensation MEASURING THE DISTORTION Making an accurate measurement of the distortion can be difficult. The oscilloscope must have enough vertical offset to enable the edge to be viewed with a reasonable scale. Often, flatness measurements in the 100 mV to 200 mV range must be measured on a 1 VolVdiv scale. In this case, the accuracy is not good. Another issue that must be considered is scope performance at maximum offsets. When a scope is operating at a maximum offset, it may introduce some of its own distortion. Check with the manufacturer. 379 Figure 6 shows the effect of an external compensation network. The improvement may seem small, but it can be seen on the CRT. Additional external compensation networks may be added to further improve the flatness. In oscilloscopes, where flatness is very important, as many as ten networks are used. is not flat. This can be seen in Figures 5 and 6. On the display, this problem shows up as a gray area right after the transition from black to white. This is a frequency response issue and can be corrected by adding an additional input peaking network. Figure 7 shows the circuit and a photo of the actual waveform. There is another flatness issue. The first 0.511s of the pulse - A2 I 'e DC v I~ 1-- - - - + - - ~' 008 V 11_ -~~- --1 1- -,- --,I --: - - .:-:.-=I r --= :-:..-=- -~-=-'--; -I 1- I _ I V 1 - --I - - - - --, I :-;.-~-- ~ -I- I - -I -~ -- - --- I --- + -I---L - -- --- - ----J -- - 1u<:::. 1 1 1V I I ~ - I - 1_ 1 1 Ll~ 1 150pF 200K 150 pF 200K 14 pF 20K 50 215 Figure 7. CR2424 With Modified Input Network Figure 6. CR2424 With External Compensation 380 When using the external compensation network techniques as previously described, there are several precautions that must be taken. The first precaution is that thermal distortion is dependent on signal swing. The distortion improves with smaller signal swings because the power may want to adjust the compensation network (by changing the capacitor) to optimize the flatness at a different contrast level (voltage swing) on the display. Another area of precaution is the 215 Q input peaking resistor. Since the CR2424 is a feedback amplifier, the gain is determined by the input peaking resistor and the feedback network. The previously mentioned compensation networks changes are less. The 200 kQ and 150 pF RC compensation network was optimized for a 40 V signal swing. For smaller signal swings, the compensation network tends to overcompensate causing the flatness to slope in the opposite direction, i.e., the smearing would appear darker than white instead of brighter than white. In this case, the CRT designer were optimized for a 215 Q input resistor. If the resistor was changed, the CR2424 would have a different gain and the compensation networks would no longer be optimized. 381 382 AN1401 I Using SPICE to Analyze the Effects of Board Layout on System Skew When Designing With the MC10/100H640 Family of Clock Drivers Prepared by Debbie Beckwith Eel Applications Engineering This application note illustrates the complexities of board layout influences on the total skew of a system when designing with the MC10Hl100H64x family of clock drivers. Transmission line theory and the various termination techniques are discussed. The note also presents guidelines to assist designers in analyzing their board layouts and loading schemes using SPICE simulations to predict and minimize the total skew of a system. 383 Using SPICE to Analyze the Effects of Board Layout on System Skew When Designing With the H640 Family of Clock Drivers Objective will concentrate on illustrating the relationship of capacitive loading versus propagation delay and the relationships dependence on board layout and termination technique. Capacitive loading refers to both "device output loading" and '1ransmission line loading." When the interconnect line is short (less than 4.5") the capacitive loading is seen by the output of the driving device and the propagation delay can be predicted by assuming a lumped load at the output of the device. This is referred to as "device output loading." However, when the line length exceeds 4.5", the capacitive loading is seen by the transmission line as opposed to the output device. This will be referred to as '1ransmission line loading." For the case of "transmission line loading," propagation delay predictions must be based on the T pd versus Cl relationship derived for a desired line length and termination technique. The propagation delay versus Cl characteristics of an IC and a transmission line are different, therefore it is not enough to simply ensure equal Cl'S on all clock paths to minimize skew. The results of this note are applicable to the entire H64x series of ECL/TIl translating devices, although only the output section of the H641 is modeled as the driving section of the analysis circuit. The ESD protection circuitry and "package" model circuitry were inCluded on the output of the driving device and the input of the receiving device to more accurately model real in-line circuits. The "package" model circuitry simulates the effects of the device packaging. In all cases, the input clock to the analysis circuit is a 25 MHz ECl level input (+ 3. 15 V to +4.15 V) with 1 ns rise and fall times. Propagation delay is measured from the 50% level of the input clock to the 1.5 V level of the TIL output at the receiving gate. The objective of this note is to illustrate the complexities of board layout influences on the total skew of a system when designing with the H64x series of clock distribution chips. The note will present some guidelines to assist designers in using SPICE to analyze their board layouts and loading schemes to predict and minimize the total skew of a system. The MC10H/100H64x series of devices are ECL/TIl translating clock drivers designed for systems requiring very low skew clock distribution. Skew is most often specified in terms of "Output to Output" skew and "Part to Part" skew. "Output to Output" skew refers to the maximum variation in propagation delay between similar paths of a single device. "Part to Part" skew refers to the maximum propagation delay difference between similar paths on different devices being driven by the same inputs. The H64x series' skew specifications are specified based on equal capacitive loading of all outputs. Since skew is a measurement of propagation delay, and propagation delay is dependent on capacitive loading, optimum skew performance can only be achieved when all outputs are loaded equally. In many designs the clock will need to be routed to a number of receiving gates at different locations in the system. For the system deSigner, skew measured at these destinations is a foremost concern. Skew between receiving gates is a measurement of the maximum variation in propagation delay between the driving gate and each receiving gate. This implies that the designer must not only be concerned with "Output to Output" and "Part to Part" skew, but also with the propagation delay along each path of the signal. Propagation delay is a function of supply voltage, ambient temperature, and capacitive loading (CU. Since propagation delay is dependent on supply voltage, which can vary significantly from board to board, skew between ICs on a single board will be much tighter than skew between ICs on different boards. This illustrates the advantage of placing ICs with tight skew requirements on the same power plane. Assuming that a common power plane is used and that the temperature gradient over the board is minimal, the supply voltage and ambient temperature will affect the propagation delay of all outputs in relatively the same manner, and thus should have minimal effect on skew. Propagation delay due to capacitive loading, however, may vary from output to output; significantly affecting skew. This variation is due to the dependence of capacitive loading on board layout, termination technique, and fanout. To realize minimal skew at the receiving gates, the deSigners goal is to design for equal propagation delays on all paths carrying the clock signal. The remainder of this note Transmission Line Concepts 1,2,3 For high speed systems, the interactions between wiring and circuitry are most easily determined by treating the interconnections as transmission lines. A brief and simplified review of transmission line theory and termination techniques will be presented before discussing the effects of termination techniques on propagation delay. For a more detailed ·discussion of Transmission Line Theory, refer to The Motorola MEClTM System Design Handbook.1 Characteristic Impedance: The conductors (interconnect trace and the AC ground plane) that interconnect a pair of Circuits have distributed series inductance and distributed capacitance between them, and thus constitute a transmission line. When these distributed parameters are constant over a length of line, the line is said to have a characteristic 384 impedance, ZOo Zo is the ratio of transient voltage to transient current passing by a point on the line when a signal change occurs. The relationship between the distributed parameters, characteristic impedance, and transient voltage and current is expressed as: VII =ZO =j (LO/CO) = of the receiving gate is large relative to the line characteristic impedance, therefore: PL is approximately equal to 1. A large positive reflection occurs resulting in overshoot. The reflected signal reaches point A at time 2TO, and a large negative reflection results because the output impedance of the driver gate is much less than the characteristic impedance of the line. In this case the reflection coefficient is negative. The signal is re-reflected back toward the load arriving at 3TO, resulting in undershoot at point B. The impetus in restricting interconnect lengths is to minimize the effects of overshoot and undershoot. A handy rule of thumb is: to limit the undershoot to 15% of the voltage swing, the two way line delay should be less than the rise time of the pulse. Thus the maximum length can be determined using the following equation: Eq2.1 = where Lo inductance per unit length and Co capacitance per unit length. ZO is expressed in Ohms, Lo in Henries, and Co in Farads. Propagation Velocity: Propagation velocity can also be expressed in terms of Co and Lo: v = 11 j (Lo/CO) Eq2.2 PL = (RT - ZO)/(RS - Zo) where: Eq 2.4 Lmax < tRI (2*Tpd) Termination and Reflection: When a signal travels down a transmission line, if the terminating resistance (RT) matches the line impedance, the ratio of voltage to current traveling along the line is matched by the ratio of voltage to current which must prevail at AT. From the viewpoint of the driving device, no adjustment of output current is required. If the line is not terminated in its characteristic impedance the signal propagating down the line is partially reflected back to the source. The magnitude of the reflected voltage signal is governed by the load reflection coefficient, PL: = where: = L Line Length, tR Rise Time Tpd '" Propagation delay I unit length Zo=500HMS TO=1.8ns Vi-D-~VO UNTERMINATEO TRANSMISSION UNE Figure 2.1a. Block Diagram of Unterminated Line Maximum open line lengths for the ECL/TTL translator were derived from SPICE simulations for 10 and 20 pF loads, a maximum overshoot of 40%, and a maximum undershoot of 20%. Simulation results indicate for a 50 ohm line driving a 10 pF load, a stub length of less than 5 inches (assuming T pd 0.18 ns/inch) will limit the overshoot to less than 40%, and the undershoot to within 20% of the logic swing. When the load is increased to 20 pF the maximum line length is 4.5 inches. The results are shown in Figures 2.1 band 2.1 C. To minimize undershoot the series termination or parallel AC termination technique should be used. Eq 2.3 RS = Source Impedance ZO = Characteristic Impedance of the line The reflected signal continues to be reflected between the source and load impedances and is attenuated with each passage over the transmission line. The output response appears as a damped oscillation asymptotically approaching the steady state value. This phenomena is referred to as ringing. Ringing has an adverse affect on noise margin. To minimize ringing, three basic termination techniques are available: = CLK 1. Minimizing Unterminated Line Length 2. Series Termination 3. Parallel AC Termination n '.. -11 •. Untermlnated Lines Figure 2.1 a illustrates an unterminated transmission line. Since the reflection coefficient at the load is of opposite polarity to that at the source, the signal will be reflected back and forth over the transmission line with the polarity changing after each reflection from the source impedance. Thus, steps appear at the input to the receiving gate. When the driver gate delivers a full TTL swing, the signal propagates from point A arriving at point B a time TO later. At point B, the signal is reflected as a function of PL. The input impedance '.J. ·0.987V ...... " -!" . . . x. CLKB --- _ _ _ _ _ _ .J g: I 1/ I 2'UNE --00 -- ~ - . II . , I I I 5'UNE ~. ~' 10" UNE ·2 o 20 TIME 40 Figure 2.1 b. H64x Driving a 10 pF Load over an Unterminated Line 385 , ... - - - ---t-I I o J - - - -- ,\ ---1./ Z 4.5" UNE: ~.98 4.8" UNE: -1.01 V 'b impedance of the driving device was obtained by extracting the VOL versus IOL and the VOH versus IOH curves (refer to Figures 2.2b and 2.2c). The output impedance of the device is equal to the slope of the curves, which can be calculated to be approximately 8 n. This value was verified using SPICE simulations. Rser, in Figure 2.2a was varied from to 0 to 50 0 in to 0 increments and the signal was monitored at the input to the receiving gate (refer to Figure 2.2d). Minimal undershoot and overshoot occurred when the resistance of the output driving circuit was assumed to be 10 O. This value closely agrees with the B 0 value measured in the lab. So, the value of Rser should be set to (Zo-tO)O for a matched series termination. Series termination is useful when the interconnect lengths are long or impedance discontinuities exist on the line. Another advantage of using series termination is that the signal travels down the line at half amplitude, minimizing problems associated with crosstalk and EM Radiation. The drawbacks of this technique are twofold. First, is the possibility of a two step signal appearing when the driven inputs are far from the end of the transmission line. Second, series termination has limited use in TTL interconnect schemes due to the voltage drop across Rser in the low state. Any voltage drop across Rser will reduce noise margin (NM) at the receiver. This is illustrated below by calculating the NML of a TTL driver/receiver pair, using data book values of IlL, VOL and VIL· ,- ------ ...", / J ' - 5.0" UNE: -1.04 V 20 40 nME Figure 2.1c. H64x Driving a 20 pF load over an Unterminated line Series Termination Series damping is a technique in which a termination resistance is placed between the driver and the transmission line with no termination resistance placed at the receiving end of the line. Series termination, illustrated in Figure 2.2a, ZO=500HMS TO= 1.8ns Vi~~VO ser DB L-/ NML ~ VOL max - [VIL max + IlL (Rsed] ~ 0.8 V - [0.5 V + 0.4 mA (40 0)] ~ 0.284 V TTL: SERIES TERMINATED TRANSMISSION UNE Figure 2.2a. Block Diagram of Series Terminated line However, when driving CMOS inputs, which pull very little input current, very little NM is lost due to the series termination resistor. Thus, series termination is a viable termination technique when driving CMOS gates. is a special case of series damping in which the sum of the termination resistor (Rser) and the output impedance of the gate (RO) is equal to the line characteristic impedance, resulting in minimum undershoot and overshoot. Rser+ RO ~ Zo Eq2.5 SWEEP VOLTAGE versus 10l With series termination, when the output of the driver gate switches, a change in voltage, delta V, occurs at the input to the transmission line: l1V ~ Vin' (ZO)/(Rser + RO + ZO) ..- Eq 2.6 §. -' 5; For a matched series termination: Rser + RO ~ ZO, thus 11 V ~ Vin/2. So an incident wave of half amplitude travels down the transmission line. Since the transmission line is unterminated at the receiving end, the reflection coefficient of the load is approximately unity; therefore causing the voltage to double at tlW receiving end. When the reflected wave arrives at the source it is completely absorbed by the series resistor since the impedance matches the characteristic impedance of the transmission line. The output 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 0 0.5 SWEEP VOLTAGE (V) Figure 2.2b. VOL versus IOl for H64x Series 386 DERIVATION OF T pel versus CL RELATIONSHIPS · SWEEP VOLTAGE V8ISUS 10H Once the designer has chosen a termination technique, the relationship of T pd versus CL for the specific application should be derived. It is suggested that the derivation be performed through simulations using the H64x Clock Driver 110 Spice Model Kit. A guideline for deriving the relationships, T pd versus CL is presented through examples for each termination technique discussed. In deriving the relationships necessary to predict propagation delay a reference for T pd is established by finding the propagation delay of the H641 's output driving circuit. To measure T pd of the output driving gate using SPICE, the analysis circuit shown in Figure 3.1 is used. 4.5 :E w 4 Cl ~ 0 > "w 3.5 r-- --.. t-. ~ 2.5 o 25 10 15 20 OUTPUT HIGH (rnA) 30 Figure 2.2c. YOH versus IOH for H64x Series RW j30n CLK IJ ~ / ser=10n - Vin Translator Output Circuitry r- ESDand Package Model Circuitry TIL Input Gate Circuitry ru CLK Rsar=400 Rser= SOO / L I:}, ~ Asar= 400 -..J ECLtoTIL r-- I 4.15V 3.15V - I bI _I\, \.. -3 so R- 25 H641 DRIVING 1 GATE OVER VERY SHORT UNE I-- Figure 3.1. Simulation Block Diagram I-75 TIME In this circuit, the output driving gate is driving one gate over a very short line (<< 1"). When the interconnect line length is this short the SPICE "transmission line" model is not needed to Simulate the interconnect line; and the propagation delay due to the interconnect line length can be assumed to be negligible. The propagation delay is measured from the 50% voltage level of the input signal to the 1.5 V level of the TTL output; and can be expressed as follows: Figure 2.2d. Series Terminated Transmission Line Output for Rser 10, 30, 40, and 50 n = Parallel AC Termination Parallel AC Termination, shown in Figure 2.3, should be used when the ability to drive distributed loads or when driving heavy DC TTL loads is required. Unlike series termination, the parallel AC termination scheme features an undistorted waveform along the full length of the line. In parallel AC termination, the receiving end is terminated to a voltage through a resistor (RT) in series with a capacitance (CT). The value of RT is equal to the line characteristic impedance. As a rule of thumb CT = 10'TD/ZO, where TO is the delay of the transmission line. When the termination resistance matches the line impedance, no reflection occurs because all the energy is absorbed by the termination. The parallel AC termination scheme consumes no DC current with outputs in either state. T pd(model) = Tpd(output gate) +,1 T pd(1 gate load) Eq 3.1 Through a SPICE simulation Tpd(model) was measured to be 2.76 ns. Rewriting the equation above to solve for Tpd(output gate), the equation becomes: Tpd(output gate) = 2.76 ns -,1 T pd(1 gate load)' '-D-rri:"'b-" Eq 3.2 To solve for T pd(output gate), the T pd due to the capacitive loading of 1 gate is needed. This relationship will also be very useful in finding propagation delay contributed by fanout. By using the same circuit as above and incrementing the number of receiving gate inputs, measurements of T pd are taken for each increment in the number of receiving gates in order to develop a relationship between Fanout versus Propagation Delay (,1 Tpd/,1# of Gates). '6 CT PARALLEL AC TERMINATEO TRANSMISSION UNE Figure 2.3. Block Diagram: Parallel AC Termination 387 The following measurements were taken: determine this relationship, the circuit in Figure 3.1 was modified by adding a load capacitor in parallel with the receiving gate, the value of the load capacitor was varied and measurements of the propagation delay taken for each value of Cl. The data is summarized and shown in a plot in Table 3.2 and Figure 3.3a, respectively. Table 3.1 , of Galea Tpd L-H(ns) Tpd H-L(ns) 1 2 4 6 8 15 2.76 2.82 2.93 3.02 3.15 3.99 2.88 3.02 3.2 3.46 3.64 4.01 Table 3.2 CL (pF) Tpd L-H (n8) Tpd H-L (ns) 0 10 20 30 40 50 70 2.76 2.98 3.19 3.39 3.52 3.75 4.07 2.88 3.34 3.76 3.99 4.18 4.35 4.66 and plotted below: 4.5 Tpd H·L 4 .:?- . /V 3.5 ,/ V 3 2.5 1 ~~ ...-f4 .......-Z T~H~L / / Tpd L·H V- o 10 i-' ~ f-"'"" 15 FANOUT i I-- - ..... f-"'"" ;'" ~ l- ~ l~ l- i-" - If Tpd L·H Figure 3.2. Fanout versus T pd for a "Short Line" 2 ~ (Tpd) / gate =0.057 nsf gate. 10 20 30 40 50 60 70 Figure 3.3a. CL versus Propagation Delay for Short Line From this data the change in propagation delay with respect to the change in Cl was calculated and the sensitivity of the output driver to capacitive loading for an unterminated "short'" line was found to be 0.02 ns/pF. The capacitive load (Cl) per gate can be calculated by taking the ratio of delay/gate to delay/Cl. Eq3.3 T pd (output) can be calculated by substituting this data into Eq. 3.2. T pd(output gate) = 2.76 ns - 0.057 ns = 2.7 ns o Cload The value of ~(Tpd)/ ~(# of gates) can be calculated by finding the slope of the Fanout versus T pd curve. From Figure 3.2, ~(Tpd)/~(# of gates) can be measured to be, approximately: Eq 3.4 Cl/gate = (0.057 nsigate)/(0.02 ns/pF) = 2.85 pF/gate Eq 3.5 Note, T pd (output gate)isnotthepropagationdelayoftheH64x, but, merely the propagation delay of the output circuitry common to all of the H64x series. This value and the values derived in the following T pd versus Cl curves should not be used as actual values of propagation delay for the H64x series and are derived here only as a reference on which to base the effects of line length, fanout, and termination technique on the propagation delay of the H64x devices. In real system designs, it will not always be realizable for the designer to have equal line lengths and fanout on each output. In attempting to achieve symmetrical loading on each output the designer will need to compensate for unsymmetrical loading by either adding line length or capacitive loads on appropriate lines. If the designer knows the skew between two paths, a relationship between capacitive loading and propagation delay is needed to determine the capacitive load needed for compensation. To When board layout constraints demand that line lengths exceed 4.5", the effects of capacitive loading are no longer seen at the output of the gate (output loading) but instead are seen by the line (transmission line loading). SPICE simulations of Output gate Delay versus Line length are shown in Figure 3.3b. Notice that for line lengths less than 4.5" the Output gate Delay increases linearly as the line length (or capacitive load) increases. For line lengths greater than 4.5" the Delay curve sharply rolls off and approaches a constant value. The rolloff occurs when the output gate no longer sees the capacitive load at the end of the transmission line. The output gate sees only the '"load'" of the transmission line and thus, T pd approaches a constant value. So, for accurate simulations of T pd versus Cl when lines are greater than 4.5", the line should be modeled as 388 in Table 3.3 along with the measurements taken for a transmission line with Zo = 75 ohms: a transmission line and the effect of capacitive loading on propagation delay re-evaluated. Table 3.3 2.5 2.3 Tpd (nsl, Zo = 50 Tpd (nsl, Zo = 75 0 10 20 30 40 50 4.3 4.71 5.03 5.31 5.56 5.B 6.02 6.22 6.B2 4.27 4.79 5.2 5.55 5.86 6.16 6.44 6.71 7.45 I---; i.!""50pFL AD'\ 2. 1 I \ ". 1.9 Y - 1.7 I---; ~25pFLOA[ 1.5 1.3 CL(pFI \ 60 I-- 1T0pF OAl 70 100 1.1 0.9 *Note: T pd includes the 1.8 ns delay of the transmission line. o 4 6 8 10 t2 UNE LENGTH (In) Plotting Cl versus Tpd, the relationship is shown in Figure 3.5. Figure 3.3b. Tpd versus Line Length Using the SPICE model of a transmission line, three termination techniques will be examined. The transmission line model chosen for this exercise is available in the SPICE simulator and assumes a propagation delay of 0.18 nslinch. Relationships between line length and termination technique will be developed along with relationships between propagation delay and capacitive loading for each termination type. ,V ., ,..V Tpd L·H 75 ~ .Y ..-V ...... ~ V ,.. V 1" I Tpd L·H 50 ~~ CASE 1: UNTERMINATED TRANSMISSION LINE 4 o 20 ·1 40 I 60 80 100 CL (pF) The analysis circuit, in Figure 3.1, was modified by inserting a transmission line between the output driving circuit and the receiving gate circuit. A capacitor, Cl, was hung in parallel with the receiving gate. (Refer to Figure 3.4). Figure 3.5. CL versus T pd for Untermlnated Line A comparison between Figure 3.3a and Figure 3.5 shows that output loading versus transmission line loading produces a nonlinear change in the T pd versus Cl curves. This implies that, for line lengths> 4.5" the designer should use the Tpd versus Cl curve which corresponds to transmission line loading, for predicting propagation delay. Figure 3.5 shows Tpd versus Cl curves for unterminated transmission lines with Zo of 50 0 and 75 o. Notice, the Ll Tpdf LlCl increases as Zo increases. This is due to the fact C0500 > C0750· This demonstrates an advantage of using lines with lower ZO° Zo= 50 OHMS, Td =1.8 ns ,...----, EClto TTL Translator Output Circuitry ESD and Package Model Circuttry ESDand Package Model Circuitry TTL Input Gate Circuitry ru CLK 4.15V 3.15V - UNTERMINATED TRANSMISSION UNE CASE 2: SERIES TERMINATED TRANSMISSION LINE Figure 3.4. SPICE Model for Unterminated Line The analysis circuit, in Figure 3.4, was modified by inserting a series resistor between the output driving circuit and the transmission line. A capacitor, Cl, was hung in parallel with the receiving gate. The resulting Circuit is shown in Figure 3.6. To determine a relationship between Tpd versus Cl for the Unterminated transmission line, the capacitive load was varied and measurements of propagation delay at the load were taken for each value of Cl. The results are tabulated 389 Cload versus Tpd FOR MATCHED SERIES TERMINATED UNE 11 Zo =500HMS, Td = 1.8ns ECLtoTIL Translator Output Circuitry ESDand Package Model Circuitry ESDand Package Model Circuitry 7Z. ./ ./. ~ SERIES TERMINATED UNE ~ Figure 3.6. Simulation Circuit: Series Terminated Line 4 First, Zo was set to a common value of 50 ohms and the line length was set to 10", which translates to a line delay, TO, of 1.8 ns. With CL set to 0 pF and measuring the propagation delay at the output of the transmission line, the accuracy of the transmission line model's TO can be confirmed by comparing this measurement to the measured vlaue of Tpd at the input of the transmission line. The equation for the measured TO is: Eq 3.6 TO = Tpdout - Tpdin· Plugging measured values into this equation for the above circuit: TO = 4.69 ns- 2.9 ns = 1.79 ns Table 3.4 CL(pF) T pd (ns), Zo = 50 Tpd (ns), Zo = 75 0 10 20 30 40 50 60 70 100 4.7 5.24 5.7 6.08 6.45 6.82 7.18 7.53 8.57 4.7 5.44 6.08 6.62 7.11 7.62 8.1 8.6 9.97 20 -" 1/ l...oo'" 1/ .- K f-'""' Tpd H-LSO r 40 -"""'Tpd L-H 50 60 I 100 60 Comparing these results to the results obtained for an unterminated line, it can be observed that the Tpd versus CL relationship is not only affected by line length, but also, by the termination technique chosen by the designer. Using series termination produces a significant decrease in undershoot and overshoot. The tradeoff is an increase in li Tpd/liCL. Notice, even when the gate is unloaded, the series terminated line is slower than the unterminated line. CASE 3: PARALLEL AC TERMINATION WITH LUMPED LOAD The original circuit was modified by inserting a transmission line between the output driving circuit and the receiving gate circuit. The circuit is shown in Figure 3.8. For Parallel AC Termination the matching network is a shunt resistor (RT) in series with a capacitor (CT) to ground, placed at the output of the transmission line. From transmission line theory, the Parallel AC Termination technique requires that the resistance of RT match the characteristic impedance of the transmission line (ZO) for optimum performance (minimum undershoot and overshoot and minimum propagation delay). Also as a rule of thumb the optimum CT can be calculated as, CT = 10*TO/Zo, where TD = the delay of the transmission line and Zo is the characteristic impedance of the transmission line. Zo = SO OHMS, Td = 1.8ns Yin Plotting CL versus T pd, refer to Figure 3.7, the relationship between CL and T pd is found to be a linear equation, when the termination is matched, that can be expressed as follows: =ZO* CL + TO + delay of output circuit o .- ~ Figure 3.7. CL versus T pd: Series Terminated Line -Note: T pd includes the 1.8 ns delay of the transmission line. Tpd -- ~~ I:iIII'" -- ..... I--"'"-J....-'" Ctoad Eq3.7 and we see it is very close to the predicted delay of (0.18 nslinch)" to inches = 1.8 ns. To determine a relationship between Tpd versus CL for matched series termination, the capacitive load was varied and measurements of propagation delay at the load were taken for each value of CL. The results are tabulated below along with the measurements taken for a transmission line with Zo = 75 ohms: TpdH-L?9 _I ..1. TpdL-H CL~ ru CLK 4.15V 3.15V - 10 TIL Input Gate Circuitry ECLto TIL Translator Output Circuijry ESDand Package Model Circuitry ESD and Package Model Circuitry TIL Input Gate Circuijry ru CLK 4.1SV 3.ISV - Eq 3.8 PARALLEL AC TERMINATION WITH WMPED LOAD slope: Zo y·intercept: TO + delay of output circuit Figure 3.8. Simulation Circuit: Parallel AC Termination 390 With Zo set to 50 ohms and TO set to 1.8 ns, RT and were calculated as 50 ohms and 360 pF, respectively. CL was varied and propagation delay measurements recorded at each value of CL. Next, Zo was set to 75 ohms and TO to 1.8 ns. Values of AT and CT were recalculated for these conditions and set to 75 ohms and 240 pF, respectively. Again CL was varied and propagation delay monitored. The results are tabulated in Table 3.5. overshoot, however, it causes a positive linear shift in the T pd versus CL curve. Series termination caused an increase in aTpdf aCL of approximately 0.01 ns/pF for a transmission line with a Zo of 50 As a result, propagation delays for series terminated lines quickly pass those of Paraliel AC terminated lines as capacitive load is increased. The tradeoff in choosing Paraliel AC termination over series termination is that Paraliel AC termination requires an extra capacitor, CT, in each matching network. Comparing the Tpd versus CL curves for Zo = 50 0 and 75 0 in Figure 3.9 it is seen that, as was the case in the other examples, the aTpdf aCL increases as Zo increases. Cr n. Table 3.5 CL (pF) T pel (ns), 0 5 10 15 20 25 30 35 40 45 50 55 60 70 100 Zo = 50 Tpel (ns), Zo = 75 4.86 5.01 5.17 5.32 5.47 5.63 5.75 5.88 6.00 6.14 6.26 6.38 6.50 6.61 6.85 7.54 5.32 CASE 4: PARALLEL AC TERMINATION WITH DISTRIBUTED LOAD 5.73 6.06 The original circuit was modified by inserting three separate transmission lines between the output driving circuit and the receiving gate circuit. The sum of the time delay of the three transmission lines being 1.8 ns, to be consistent with the data taken for the other termination techniques. C\lpacitive loads are placed at the end of each transmission line. The paraliel AC matching network is placed at the end of the last transmission line. The circuit is shown in Figure 3.10. 6.4 6.71 6.95 7.28 8.03 *Note: T pd includes the 1.8 ns delay of the transmission line. Plotting CL versus T pd results in the relationship shown in Figure 3.9. Zo = 50 OHMS, Td = 1.8 ns ECLtoTIL Translator Output Circuilry I T~L'HJ5 I ..".;- ........:::: ~ ~'r" 4 ~ 20 ..... i.,...--' ..,. ........ i.,...--'- ....... ~, I PARALLEL AC TERMINATION WITH DISTRIBUTED LOAD Tpd L·H 50 I o ESDand Package Model Circuilry ESDand Package Model Circuilry 40 Figure 3.10. Simulation Circuit: Parallel AC Termination I 80 80 100 <:toad Table 3.6 Figure 3.9. CL versus T pel: Parallel AC Termination A comparison of the results of the Paraliel AC termination scheme versus the unterminated scheme illustrates almost no increase in aTpdfaCL. However, the propagation delay for a Paraliel AC terminated line driving a 0 pF load is greater than that for an unterminated line or a series terminated line driving 0 pF. So, choosing Paraliel AC termination over an unterminated line significantly decreases undershoot and CL (pF) Tpel L·H(ns) 0 15 25 30 45 60 90 5.01 5.35 5.54 5.68 5.98 6.29 6.84 -Note: Tpd includes the 1.8 ns delay of the transmission line. 391 TIL Input Gate Circu~ry \,Ji ", .,/ V 4 ~ ,./" V ,., ,./" ~ /~H.L o -", determining the relationship, Tpd versus T D for each termination technique when CL = 0, the designer could determine the y-intercept of that termination techniques' ''Tpd versus CL" curve for a desired line length. V I-- Tpd versus UNE LENGTH FOR DIFFERENT TERMINATIONS I pd I 40 20 60 80 Cload Figure 3.11. CL versus T pd: Oistributed Load: Parallel AC Termination 2L-____ Tpd L·H versus CLOAD FOR MATCHED SERIES TERMINATION 10 TD=2.7ns 1,\ 1-- ..... i-"" 3 o ........ ..... 20 - ~ ", ", i-""" - TD= 1.8ns ,., -- o 40 ..... K 80 ~ ______L __ _ _ ___O 1 Td (ns) By setting the capacitive load to 0 pF for each type of termination, and varying the line length only; this type of relationship is established. The results are shown in Figure 3.13. Once the designer knows the length of the transmission line and the termination technique, a "T pd versus Line Length" chart can be used to determine the y-intercept of the appropriate termination schemes' "Tpd versus CL" curve. Note, these values have been derived using only the output section of the H641 driving the input section of the H645. Therefore these propagation delay values are not representative of actual delays of the H64x and are derived here only to show the relationship of T pd versus TD. It is suggested that the designer derive the T pd versus TD curve with CL =0 pF for their specific application, using the "H64x Clock Driver I/O Spice Model Kit." \ .TD=~.9nsl_ 60 ______ Figure 3.13. (Cld versus Tpd) versus Termination Technique >- ~ 100 Cload (pF) Figure 3.12. (T pd versus CLl versus TO for Series Termination With Zo set to 50 ohms and TD set to 1.B ns. Using the equations above RT and CT were calculated as 50 Q and 360 pF, respectively. Total CL was varied and propagation delay measurements recorded at each value of CL. The results are tabulated in Table 3.6. Plotting CL versus T pd gives the relationship shown in Figure 3.11. Data has now been derived for the relationship between capacitive loading versus propagation delay for the following termination techniques: unterminated transmission lines, series termination, and parallel AC termination. To generalize these results for any interconnect line length, the relationship of (CL versus T pd) versus Line Length must be evaluated. Using the series termination circuit configuration, the delay (line length) of the transmission line is varied from TD = 0.9 ns to TD = 1.B ns to TD = 2.7 ns. At each line length setting a "CL versus T pd" curve was extracted. The results are summarized in the plot, Figure 3.12. Notice, changing the length of the transmission line merely causes a vertical shift of the Series Terminations' "T pd versus CL" curve. This will be found true for the unterminated and the parallel AC termination schemes as well. So, by Summary The MC10H/100H64x series ECLITTL translating clock drivers are ideal devices for systems requiring very low skew clock distribution. Optimum skew performance from the H64x series requires equal capacitive loading on each output. To minimize skew in a system not only requires minimal "output to output" skew and "part to part" skew, but also requires equal propagation delay along all paths carrying the clock signal. Perhaps the most accurate technique of obtaining equal propagation delay along all paths is to add trace to the lines with shorter propagation delays. However, this is a trial and error method and does not always provide a feasible solution due to size constraints of the board. Another technique of obtaining equal propagation delays on each path is to add capacitive loading on paths with shorter propagation delays. This method requires an understanding 392 of Tpd versus CL relationships. As shown in this note, T pd versus CL relationships are dependent on line length, termination technique, and the characteristic impedance of the transmission line. If line lengths are less than 4.S", propagation delay can be predicted by assuming a lumped capacitive load at the output of the driving device. When lines exceed 4.S" the capacitive load is no longer seen by the output driving device, but is instead seen by the transmission line. A different Tpd versus CL relationship exists for the transmission line than the output device. The transmission line Tpd versus CL relationship is dependent on termination technique and line characteristic impedance. The dependence on termination technique is important at line lengths greater than 4.S" because at these lengths undershoot becomes significant enough (20% of logic swing for a 20 pF load) to necessitate some sort of termination scheme to minimize its adverse effects. Relationships of Tpd versus CL were derived and compared for three termination schemes: the unterminated line, the series terminated line, ana the parallel AC terminated line. All Tpd versus CL curves were derived for transmission lines with TD = 1.8 ns and Zo = SO nand 7S n. For all three termination schemes, increasing the characteristic impedance of the transmission line produces an increase in the 6 Tpdf 6CL relationship. Of the three termination techniques the unterminated line had the smallest 6 Tpdf 6CL, followed by parallel AC termination, and finally series termination. The tradeoff in choosing terminated lines versus unterminated lines is, of course, minimized undershoot for an increase in 6Tpdf6CL. The tradeoff in choosing parallel AC termination versus series termination is an increase in the number of parts for a decrease in 6 T pdf 6CL. Since the values in this note have been derived for the specific case of the output section of the H641 driving the input section of an H64S, the values of propagation delay are not representative of actual delays of the H64x series of devices. Also, due to SPICE simulator limitations of accuracy, delays are not exact and should be used to predict relative differences only. For these reasons, the designer is encouraged to use the "H64x Clock Driver I/O Spice Model Kit" to derive the relationships necessary to predict and minimize skew for their particular system. To obtain the "H64x Clock Driver I/O Spice Model Kit" contact a Motorola representative. References 1Motorola MECL System Design Handbook, second edition, Motorola Inc., 1983. Stock Code HB20SRlfD. 2Motorola ECLinPSTM Data Book, Motorola Inc., 1991. Stock Code DL140R1fD. 3Fairchild FAST Applications Handbook. Fairchild Semiconductor Corporation, 1987. 393 394 AN1402 I MC1 0/1 00H600 Translator Family I/O SPICE Modelling Kit Prepared by Debbie Beckwith Eel Applications Engineering This application note provides the SPICE information necessary to accurately model system interconnect situations for designs which utilize the translator circuits of the MC 1OH600 family. The note includes information ontheH600, H601, H602, H603, H604, H605, H606and H607 translators. 395 MC1 0/1 00H600 Translator Family I/O SPICE Modelling Kit Objective ESD protection circuitry and package models. The devices shown in shaded boxes on the 1/0 buffer schematics are modelled by the subcircuits illustrated on the appropriate subcircuit schematic sheet. This hieracrchical method of schematic representation is used to help simplify and clarify the buff8f schematics. With the difficulty in designing highspeed controlled impedance PC boards and the expense of reworking those boards the ability to model circuit behavior prior to committing to a board layout is essential for high speed logic designers. The purpose of this document is to provide the user with enough information to perform basic SPICE model analysis on the interconnect traces being driven or driving the H600, H601, H602, H603, H604, H605, H606 or H607 translator chips. The packet includes schematics of the input and output structures as well as ESD protection structures and package models which may affect the waveshape of the input and output waveforms. Internal bias regulators and logic circuitry are not included as they have little impact on the 1/0 characteristics of the device and add a significant amount of time to the standard simulation analysis. In addition a SPICE parameter set for the devices referenced in the schematics is provided. The remainder of this document will introduce the various input and output stages for the H60x translators as well as the other structures which affect the 1/0 characteristics of these devices. The H600 and H602 utilize the same output buffer. This buffer is represented by the H600 Output schematic of Figure 6. These devices are dual supply devices which means they require +5V, -5.2V and ground supplies. The A and AN inputs should be driven differentially with the HIGH level at VCC - O.85V and the lOW level equal to VCC -1.25V and the Band BN inputs should be driven differentially with a voltage swing from -2.0V to -2.4V Notice the ESD protection circuitry on the output, this circuitry is represented by the FPS009E schematic of Figure 15. The H601 is also a dual supply device, however, both the input and output buffers are represented by one structure as shown in the H601 1/0 Schematic of Figure 7. The H601 requires a single ended input, IN which should be driven from VCC-O.9to VCC-1.75V Notice the "ECl in Pad Cell" on the input, this circuitry is represented by the "ECl Input Pad Cell" schematic of Figure 15, and includes the 50KQ input pull down resistor and the ESD protection circuity for the ECl input. The same ESD structure is used on the output buffer section of the H601 1/0 Structure as is used on the H600 output buffer. The H601 1/0 buffer also requires one bias supply, CBIAS, and differential tritstate buffer inputs, TRI and TRIB. The CBIAS input should be set at 1.1V, while the TRI and TRIB inputs should be driven by the "H601 ECl Input" structure of Figure 3. Schematic Overview There are ten basic schematics which can be used to represent all of the 1/0 for the H60x family of translator chips. A single TTL input structure can be used to represent all of the TTL inputs, with the exception of the H606s "ClKT" input, which should be modeled using the "H606 TTL Input" structure. All of the ECl inputs can be represented by a single ECl input structure, with the exception of the H601s "data" inputs, the H601 s ECl "TRI" and "TRIB" inputs and the H602s "EClST" input, which should be modeled using the "H601 1/0 Gate" structure, the "H601 ECl Input" structure and the "H602 ECl Input" structure, respectively. Six different output buffers represent all of the output buffers for the H60x series of translators. The rest of the schematics provided represent subcircuit schematics for the above mentioned 1/0 buffers, The H603 Output gate is represented by the schematic of Figure 8. The IN and INB inputs should be driven differentially with voltage swings of VCC to VCC - 0.85V The CBIAS input should be forced to 1.1 V and the ENA input should be driven from VCC - 0.85 to VCC - 10.85V. The H603 again uses the same ESD protection scheme as the H600. Table 1. Device Type Input Cross Reference Part Type Eel Inputs TTL Inputs H600 EClST TTlST, 00-08 H601 va None H606 TTL Inputs H602 Eel Inputs H601 Eel Inputs None None None H601 None TTLOE 00-08 None None EClOE H602 lEN, RESET 00-08 None None None None H603 All Inputs None None None None None H604 RESET, ClK, ClKN ClKT, DO-OS None None None None H605 All Inputs None None None None None H606 ClK,ClKN,RESET None None ClKT, DO-OS None None H607 All Inputs None None None None None 396 The H604 and H606 utilize the same output buffer. This buffer is represented by the "H604 Output Schematic" of Figure 11. The IN and INB inputs should be driven differentially with voltage swings from VCC - 0.B5 to VCC -10.B5V. Note, the ESD protection circuitry is the same as the H600. Table 2. Input and Bias Levels Schematic Figure 12 represents the schematic for the output buffer utilized by the H605. The IN and INB inputs should be driven differentially from VCC - 0.B5 to VCC -1 0.B5V, while CBIAS is forced to 1.lV. Again, the same ESD protection scheme is used as on the H600. The H607 output buffer is represented by the schematic of Figure 13. The IN and INB inputs should be driven differentially from VCC to VCC - 1.BV. The ESD protection circuitry is the same. Two input structures can represent most of the inputs forthe H60x family of translators, one for TIL inputs and one for ECl inputs. The exceptions were discussed previously and the various inputs and appropriate input models are summarized in Table 1. For the dual supply devices with ECl inputs the VCC and the VEE on the typical ECl input gates should be tied to ground and -5.2V respectively. All input pins should have both a package model and ESD protection circuitry connected to them. For TIL inputs the ESD protection circuitry is represented by the FPS009E schematic of Figure 15. For ECl inputs the ESD protection circuitry is represented along with a 50KQ input pull down resistor as part of the "ECl in Pad Cell" represented in Figure 15. The "Package Model" of Figure 15 is self explanatory, the parasitic values provided are worst case numbers. The package capacitance combines with the parasitic transistor capacitance of the input device and the ESD circuitry to comprise the load capacitance of the input. The various input buffer ESD circuits are outlined in Figure 15, notice that the ECl inputs utilize a different structure than the TIL inputs and outputs. The typical ECl input schematic represents a single ended ECl input, the VBB reference should be tied to VCC - 1.3V and the VCS bias should be tied to VEE + 1.3V. To simulate a differential ECl input one simply connects the complimentary input to the "VBB" side of the input gate along with an associated ESD and package model. The differential input does not use the VBB switching reference. Input Level Eel Input VBB Ves Vee-1.3V VEE + 1.3V H600, H602 Output AlAN BlBN Ves Vee - O.85V to Vee -1.25V Vee - 2.0V to Vee - 2.4V VEE + 1.3V H60l110 IN eBIAS TRlfTRIB Ves VBB Vee - O.85V to Vee - 1.85V 1.W -2.W to -2.5V VEE + 1.3V Vee -1.3V H603 Output INIINB ENA Ves VBBP eBIAS Vee to Vee - O.85V Vee - O.85V to Vee - 1.85V VEE + 1.3V Vee- 2.W 1.lV H605 Output INIINB eBIAS Ves Vee - O.85V to Vee - 1.29V 1.W VEE + 1.3V H604, H606 Output Ves VEE + 1.3V H6070utput IN/INB Vee to Vee - O.85V Handling Power Supplies It is important to properly apply the power supply voltages to accurately model these Circuits. This section will explain the power supply terminology used on the I/O buffer schematics and how to properly apply these supplies with the appropriate package model. Table 3. Power Pin Descriptions Power For all of the input and output buffer schematics the resistors should NOT be simulated as simple SPICE resistors. Because these resistors are realized by a diffusion step in wafer processing there are parasitic capacitances associated with each. The subcircuit schematic is shown for the resistors in the "Resistor Model" schematic of Figure 15. The value of each subcircuit resistor is one half the value given on the top level schematic and the parasitic capacitance is modelled by a diode back biased to VCC. Also note that the resistor temperature coefficient (TC) values for both the resistor subcircuit and the resistors in the device subcircuits are provided. For modelling at nominal temperatures only, these TC's can be omitted. If however modelling will be performed at the temperature extremes the TC information should be included. . Description EVee EVee is the most positive supply for the Eel input gate (+5V for the H607 and ground for H60D-H606) VEE VEE is the most negative supply for an Eel gate. For the H607 it is equal to ground, for the H600-H606 it is equal to -5.2V TVeel Internal Vee for TTL Circuitry GNDI Internal ground for TTL Circuitry Table 3 lists the voltage supplies referenced on the I/O schematics along with a description of each. The key to properly simulating these power supplies is in the application of the package model. Because the output buffers, to a varying degree, share VCC and ground pins, adjustments need to be made to get a more accurate model if all of the outputs are not simulated at the same time. If for example a single output is to be simulated the package model for the TVCCI and TGNDI supplies should be scaled based on the number of outputs which normally share the supplies. If the Simulated output normally shares its supplies with two other outputs the package inductance would be tripled to simulate the same inductive glitch seen on the power pin in an actual application. The capacitive value for the package model is not as critical and thus can be left alone. This method will allow users to more accurately model an output behavior without resorting to Table 2 is provided to summarize the various internal voltage swings and bias levels required to run the appropriate SPICE simulations. 397 more accurately model an output behavior without resorting to more complicated and lengthy simulations. The internal power and ground pins are all powered through a single pin and are basically static, as a result no adjustments are needed for the package models on these supplies. Table 4 outlines the internal power distribution for the H60x translators, this information can be used to determine the scaling factors for the package inductance for the output buffers. To use the table simply identify the output in question and divide the number of outputs in the group by the number of power pins for that group, this will give the multiplication factor for the inductance. be to manipulate the generic netlists. If, however the netlists are desired or questions arise about the contents of this document the user can contact an ECl applications engineer for assistance. Table 4. Power Pin versus Outputs Part Type Number 01 Outputs Number TVCC Number TGND N/A H600 9 3 H60l 9 2 3 Summary H602 9 3 N/A The information included in this kit should provide the user with all of the information necessary to do SPICE level system interconnect modelling. The schematic information provided in this document is available in nellist form through EMAil or an IBM or Macintosh disk. However with today's advanced design tools it will probably be a simpler task to enter the schematics in a good schematic capture package than it will H603 9 2 3 H604 12 3 N/A H605 6 2 2 H606 3 3 N/A H607 6 2 2 398 PKG ~cc~-----------r---------------'r-----~ OUTI I------If---o CUTIB VBB V~-E~~----------------E-~~-C R6 9000 VEE Figure 1. Typical Eel Input Gate Nl FPSOO1 'P~ 1- OSI GRSOOI AX 2 TC = 4.45E-4, 2.78E-6 REP1 15.2 1----0 OUT REXT 13.7 ~2 R4 225Cl Figure 2. Typical TTL Input Gate 399 .~ Dl DSUBSOOI PKG EVCC D--..,.---.--------------.---...., 1 - - - - + - 0 OUll! OUT Figure 3. H691 ECl Input Gate PKG EVCCD------.-----------"""'T---...., 1----:..-+--0 OUll! OUT Figure 4. H602 ECl Input Gate 400 Rl 2fcO Nl FPSOO1 ~r OSI GRSOOI RX r-------r--+----~DO~ 2 TC = 4.45E-4. 2.78E-8 REP! 15.2 REXT 13.7 N2 TGNDI Figure 5. H606 TTL Input Gate PKG ~CC e>-----------,---------------,----------, RCl1 272.70 AD-------·C ~D-------------------~~------~ BD-------------------~ BN~--------------------------._+_------~ Figure 6. H600, H602 Output Gate 401 '-----.J...--..::.:..::.::.:J=--..L-----~--~--~--~--L--~--~---"""'~----L-~ Figure 13. H607 Output Gate 406 N1 N5 N1 OSl WNOS QPSl14 RT 5.4 OSl OPSl14 N2 TC = 4.45E·4, 2.78E-S 01 OSUBSl14 02 OSUB2N05 01 OSUB1N05 QPNN05M -=- -=- N3 -=- N2 TC = 4.45E-4, 2.78E-S N4 N1 N1 OSl GRSOO3 RX 2 R4 7.89 TC = 4.45E-4, 2.78E-S REPI 15.3 N2 FPSOO3 01 OSUB139 TC = 4.45M, 2.78U REXT 22.9 -=- N3 01 OSUBSOO3 -=- N2 N1 N1 R1 23.4 R1 19.1 N2 N2 01 OSUB025 N3 01 OSUB025X N3 -=- N1 Rl 19.5 N2Q---'-----f.. 01 OSUB1OB N3 -=- Figure 14. H607 Output Subcircuits 407 -=- AS 7ID RPKGl INIO...-r:-:=-~Mri-'D OUT RPKG3 0.20 RP 5OkO 1-A.N\r---D INT Package Model (2S-lead PlCC) ECl Input Pad Cell Nl POS VCCI Rl 4.97 DSI ... 01 RES·DIOOE GROO9E RIA SPICEPAR/2 ~ V 01 N 2 Q - - + - - - - . [~ , PNOO9E I ,II. TC= 431.6U, 8.97U 01 -~DSUB009E R1B SPICEPAR/2 NEG TC= 4.45E·4, 2.7BE·6 -= FPS009EX Resistor Model Figure 15. Miscellaneous Subcircults SPICE Parameter List TTL Subcircuit Models .MODEL GRS001 D (IS=4.27E-14 RS=53 N=1.044 TI=10PS CJO=54FF VJ=.4 M=.33 + EG=.69 XTI=3 FC=.5 BV=30) .MODEL DSUBS001 D (IS=1E-16 RS=O N=1TIt=500PS + CJO=87FF VJ=.51 M=.24 + EG=1.115 XTI=3 FC=.5 BV=35) + (CJO=203FF VJ=.51 M=.24) .MODEL DSUB1 N05 D .MODEL DSUB2N05 D (CJO=388FF VJ=.51 M=.24) .MODEL PNN05A NPN (IS=1.662E-17 BF=70 NF=1.008 VAF=30 IKF=10A + ISE=O NE=1 BR=5 NR=1 XCJC=.1 VAR=100 + IKR=. 7125MA ISC=1.803E-16 NC=1 RB=656.7 RBM=218 + RE=O RC=91.62 + CJE=86.47FF VJE=.9 MJE=.4 + CJC=58.32FF VJC=.53 MJC=.37 + TF=40P XTF=O VTF=100 ITF=3.89MA PTF=O + TR=200P XTB=1.51 EG=1.115 XTI=5 FC=O.5) .MODEL PNN05B NPN (IS=1.583E-16 BF=70 NF=1.008 VAF=30 IKF=1 OA + ISE=O NE=1 BR=5 NR=1 XCJC=.1 VAR=100 IKR=6.78MA ISC=1.717E-15 NC=1 RB=77.29 RBM=31.25 + RE=O RC=9.61 + CJE=751.6FF VJE=.9 MJE=.4 + CJC=445.2FF VJC=.53 MJC=.37 + TF=40P XTF=O VTF=100 ITF=37.1MA PTF=O + TR=200P XTB=1.51 EG=1.115 XTI=5 FC=O.5) + 408 .MODEL WN05 D (IS=1.0578E-12 RS=37.6 N=1.044 TT=10PS + CJO=141. 75FF VJ=.4 M=.33 + EG=.69 XTI=3 FC=.5 BV=30) .MODEL DSUBS114 D (IS=1E-16 RS=O N=1 TT=500PS + CJO=2.75PF VJ=.51 M=.24 + EG=1.115 XTI=3 FC=.5 BV=35) .MODEL QPS114 D (IS=2.52E-12 RS=1.35 N=1.044 TT=10PS + CJO=2.1PF VJ=.4 M=.33 + EG=.69 XTI=3 FC=.5 BV=30) (CJO=284FF VJ=.51 M=.24) .MODEL DSUB025X D .MODEL PN025X NPN (IS=4.32E-17 BF=113 NF=1.008 VAF=30 IKF=10A + ISE=O NE=1 BR=5 NR=1 XCJC=.1 VAR=100 + IKR=10.85MA ISC=4.68E-16 NC=1 RB=175 RBM=65 + RE=O RC=35.2 + CJE=193FF VJE=.9 MJE=.4 + CJC=158FF VJC=.53 MJC=.37 + TF=40P XTF=O VTF=100 ITF=5.7MA PTF=O + TR=200P XTB=1.51 EG=1.115 XTI=5 FC=0.5) .MODEL FP025X D (IS=1.08E-13 RS=48.3 N=1.044 TT=10PS + CJO=90FF VJ=.4 M=.33 + EG=.69 XTI=3 FC=.5 BV=30) (CJO=284FF VJ=.51 M=.24) .MODEL DSUB025 D .MODEL PN025 NPN (IS=2.45E-17 BF=113 NF=1.008 VAF=30 IKF=10A + ISE=O NE=1 BR=5 NR=1 XCJC=.1 VAR=100 + IKR=1MA ISC=2.66E-16 NC=1 RB=193 RBM=89 + RE=O RC=62 + CJE=123FF VJE=.9 MJE=.4 + CJC=108FF VJC=.53 MJC=.37 TF=40P XTF=O VTF=1 00 ITF=5.7MA PTF=O + + TR=200P XTB=1.51 EG=1.115 XTI=5 FC=0.5) (IS=1.4E-13 RS=52 N=1.044 TT=10PS .MODEL FP025 D + CJO=117FFVJ=.4 M=.33 + EG=.69 XTI=3 FC=.5 BV=30) .MODEL DSUB139 D (CJO=2.12PF VJ=.51 M=.24) .MODEL PN139 NPN (IS=1.03E-16 BF=113 NF=1.008 VAF=30 IKF=10A + ISE=O NE=1 BR=5 NR=1 XCJC=.1 VAR=100 IKR=4.4MA ISC=1.22E-16 NC=1 RB=117 RBM=47 + RE=O RC=8,41 + CJE=493FF VJE=.9 MJE=,4 + CJC=244FF VJC=.53 MJC=.37 + + TF=40P XTF=O VTF=100 ITF=96.7MA PTF=O + TR=200P XTB=1.51 EG=1.115 XTI=5 FC=0.5) (IS=7E-14 RS=10 N=1.044 TT=10PS .MODEL GR139 D CJO=88FF VJ=.4 M=.33 + EG=.69 XTI=3 FC=.5 BV=30) (IS=4.27E-14 RS=53 N=1.044 TT=10PS .MODEL GRS003 D + CJO=54FF VJ=.4 M=.33 + EG=.69 XTI=3 FC=.5 BV=30) (IS=1E-16 RS=O N=1 TT=500PS .MODEL DSUBS003 D + CJO=127FF VJ=.51 M=.24 + EG=1.115 XTI=3 FC=.5 BV=35) .MODEL DSUB009E D (CJO=106FF VJ=.51 M=.24) .MODEL PN009E NPN (IS=3.92E-16 BF=113 NF=1.008 VAF=30 IKF=10A + ISE=O NE=1 BR=5 NR=1 XCJC=.1 VAR=100 + IKR=.3MA ISC=4.25E-15 NC=1 RB=185 RBM=39 + RE=O RC=3.9 + CJE=1.37PF VJE=.9 MJE=.4 + CJC=609FF VJC=.53 MJC=.37 + TF=40P XTF=O VTF=100 ITF=1.64MA PTF=O + TR=200P XTB=1.51 EG=1.115 XTI=5 FC=O.5) .MODEL GR009E D (IS=5.4E-13 RS=9.57 N=1.044 TT=10PS + CJO=683FF VJ=.4 M=.33 + EG=.69 XTI=3 FC=.5 BV=30) 409 .MODEl DSUB108 D (CJ0=163FF VJ=.S1 M=.24) .MODElPN108 NPN (IS=1.7SE-17 BF=113 NF=1.008 VAF=30 IKF=10A + ISE=O NE=1 BR=S NR=1 XCJC=.1 VAR=100 + IKR=.7SMA ISC=1.9E-16 NC=1 RB=638.8 RBM=222 + RE=O RC=87 + CJE=90.6FF VJE=.9 MJE=.4 CJC=SO.3FF VJC=.53 MJC=.37 + + TF=40P XTF=O VTF=1 00 ITF=4.1 MA PTF=O + TR=200p XTB=1.51 EG=1.115 XTI=5 FC=0.5) .MODEl W108 D (IS=5.1E-13 RS=58.8 N=1.044 TI=10PS + CJO=68.3FF VJ=.4 M=.33 + EG=.69 XTI=3 FC=.5 BV=30) Eel Transistor Models .MODEl TOSI1 NPN IS=21.18E-18 BF=112 BR=5.108 RE=1.S33 IKF=.0213 VAF=41.8 + + ISE=250E-18 RB=52.7 RBM=O IRB=O IKR=53E-S VAR=3.766 + ISC=9S.62E-18EG=1.11 RC=26.33 NC=1.141 NR=.997 + CJE=67.7E-15 VJE=1.037 MJE=.5718 NF=1.000 XTI=4.7 + CJC=99.SE-15 VJC=.603 MJC=.266 NE=2.000 XTB=1.15 + CJS=152E-15 VJS=.50S2 MJS=.346S TR=9.92E-9 PTF=20 + TF=35E-12 XTF=2.25 VTF=1.67 ITF=.00808 XCJC=.069 FC=.8 .MODEl TPNP2 PNP + IS=7.69E-17 BF=5 BR=1 RB=164 RC=56 CJE=.086E-12 + CJC=1.4E-12 .MODEl T0811 NPN + IS=33.33E-18 BF=114.5 BR=2.029 RE=1.333 IKF=.0336 VAF=42.7 ISE=1.0E-15 RB=56.6 RBM=O IRB=O IKR=.115 VAR=3.665 + + ISC=184.7E-18 EG=1.11 RC=22.86 NC=1.085 NR=.995 + CJE=99.3E-15 VJE=1.037 MJE=.5718 NF=1.000 XTI=4.7 + CJC=124.4E-15VJC=.603 MJC=.266 NE=2.000 XTB=1.15 + CJS=170.4E-15 VJS=.5052 MJS=.3465 TR=9.92E-9 PTF=40 + TF=3SE-12 XTF=2.25 VTF=1.67 ITF=.00808 XCJC=.089 FC=.8 .MODEl T12B1 NPN + IS=5.7E-17 BF=113 BR=1.116 RE=1.25 IKF=.0828 VAF=4 + ISE=2.4E-15 RB=170 RBM=170 IRB=1.7E-3 IKR=.27 VAR=3.6 ISC=1.01E-16 EG=1.11 RC=13.3 NC=1.028 NR=1.019 XTI=3 + + CJE=15E-15 VJE=.658 MJE=.273 NF=1.000 + CJC=27e-15 VJC=.603 MJC=.369 NE=2.000 + CJS=101E-15 VJS=.429 MJS=.259 TR=5E-9 + TF=39E-12 XTFf=3 VTF=1.4 ITF=.008 XCJC=.620 FC=.005 .MODEl T5406 NPN + IS=3.3E-16 BF=113 RB=86.6 BR=5 + RC=23.6 RE=.833 CJE=.495E-12 CJC=.722E-12 CJS=.576E-12 Resistor Diode Model .MODEl RES-DIODE D (IS=1E-16 TI=1NS VJ=.759V M=.333 CJO=50FF) 410 AN1404 I ECLinPSTM Circuit Performance at Non-Standard VIH Levels Prepared by Todd Pearson Eel Applications Engineering This application note explains the consequences of driving an ECUnPS device with an input voltage HIGH level (VIH) which does not me9t the maximum voltage specified in the ECUnPS Databook. 411 ECLinPS Circuit Performance at Non-Standard VIH Levels Introduction VIHmax and the ECLlnPS Family When interfacing ECLinPS devices to various other technologies times arise where the the input voltages do not meet the specification limits outlined in the ECLinPS data book. The purpose of this document is to explain the consequences of driving an ECLinPS device with an input voltage HIGH level (VIH) which does not meet the maximum voltage specijied in the ECLinPS Oatabook. As previously mentioned the MOSAIC III'" process allows for ECLinPS devices to operate at VIHmax levels somewhat higher than those specijied in the databook, however the exact value of VIH for which saturation problems will occur varies from device to device and even among different inputs for a given device. This variation is a result olthe different input configurations used on the various inputs of ECLinPS devices. The results outlined in this document should not be viewed as guarantees by Motorola but rather as representative information from which the reader can base design decisions. It is up to the reader to assess the risks of implementing the non-standard interface and deciding ij that level of risk is acceptable for the system design. Motorola's guarantee on VIH will continue to be the specification standards established for the 10HTM and 100K ECl technologies. The easiest way to define an acceptable VIHmax for each device in the family is to define at what point the input transistor will saturate and specify for each input what the worst case input transistor collector voltage will be. With this information designers will be able to determine on a part by part, input by input basis what input voltage levels will be acceptable fortheir application. Simulation Results Overview The input saturation phenomenon was characterized through SPICE simulations and the results will be reported in the following text. For simplicity of simulation a buffer similar to the E122 was used; Since the outputs of this buffer drive off chip, the VIHmax performance of this structure will be worse than the typical input structure. Both a 100K and a 10H style buffer were analyzed to note any discrepancies between the two standards. As expected the simulation results showed no difference in the saturation susceptibility of a 100K versus a 1OH style buffer. Therefore the simulation results of only the 1OOK style buffer will be presented to minimize redundancy of information. The upper end of the VIH spec of an ECLinPS, or any other ECl, input is limited by saturation affects of the input 1ransistor. Figure 1 below illustrates a typical ECl input (excluding pulldown resistors and ESO structures); the structure is a basic differential amplijier configuration. With a logic HIGH level asserted at the input the collector of that transistor will be pulled down below 1he VCC rail by the gate current passing through the collector load resistor. The voltage at the collector of the input transistor (VC) will be dependent on the gate current and the size of the collector load resistor associated with the input gate. The following text will referto Figures 4-8 in the appendix of this document. Figures 4-8 are graphical plots of the input and output waveforms of an E122 style buffer (structure similar to that of Figure 1) for various VIH levels. V(in) represents the input voltage while V(q) and V(qb) represent the output voltages. The V(vbb) line was included for measurement purposes only and will be ignored. Vee Figure 4 represents the "standard" operation of the device as a standard VIH input was used. Note that in this condition the propagation delays measure in the 215-225ps range and the IINH was 42.51JA. The IINH of this device is simply a measure of the base current of the input transistor when that transistor is conducting current. We will be monitoring both of these conditions as well as any degradation in the output waveforms as a sign of the input transistor becoming saturated. As can be seen in Figures 5 and 6 none of the parameters change for VIH levels of up to -O.4V. With a collector voltage, VC, of .... t.OV these VIH'S correspond to a collector base forward bias of 600mV. As the VIH of the input moves closer to V CC, Figures 7 and 8, three phenomena start to occur: the IINH increases, the delays increase and signijicant changes occur to the output low level of the OB pin. Figure 1. Typical ECLlnPS Input Structure As the input VIH increases towards VCC the collector base junction olthe input transistor becomes forward biased; as this forward bias condition increases the transistor will move into the saturation region. The value of VCB at which the transistor begins to saturate is process dependent and will vary from logic family to logic family. Fortunately the MOSAIC III process used to implement the ECLinPS family incorporates a deep n+ collector doping. This deep collector helps to mitigate the effects of saturation of transistors by requiring a larger collector-base forward bias to enter the saturation region. In Figure 7 the IINH of the input transistor has more than doubled from the "standard" level. This increase in base current leads to an increase in the VOL level as the collector 412 belorethey are led into the differential ampl~ier input gate. The switching relerence is also shifted down by one diode drop to remain centered in the input swing. Obviously this input structure will represent the "best case" in the area 01 extended VIHmax performance. In lact this type 01 input structure will allow lor input vo~ages even several hundred millivo~s above the VCC rail. This characteristic makes these type devices ideal lor interfacing with dillerential oscillators whose outputs lack any DC ollset. In the emitterlollower structure the limiting lactor will be the saturation 01 the emitter lollower device whose collector is at VCC. From the previous simulation results this would suggest a maximum VIH 01 +O.6V. current must reduce to maintain the constant emitter current. As the collector current reduces, the IR drop across the collector load resistor reduces, thus raising the VOL level on the OB output. A~hough the VOL level has shifted the overall propagation delay has remained essentially unchanged. Finally, when the input is switched all the way up to Vec the VOL level no longer remains in spec as the input base current has jumped to almost 1ma and there has been sign~icant degradation in the high-low propagation delay. ~ is apparent that lor this condition an E122 style buller will not perform adequately lor most systems. From this inlormation it can be concluded that lor a collector-base lorward bias 01 S600mV there will be no adverse conditions on the performance 01 the device. The perfor