DZ51 00_Assembly_Instructions_DPS_8000_Mar87 00 Assembly Instructions DPS 8000 Mar87
DZ51-00_Assembly_Instructions_DPS_8000_Mar87 DZ51-00_Assembly_Instructions_DPS_8000_Mar87
User Manual: DZ51-00_Assembly_Instructions_DPS_8000_Mar87
Open the PDF directly: View PDF 
.
Page Count: 1010
| Download | |
| Open PDF In Browser | View PDF |
LARGE SYSTEMS
ASSEMBLY
INSTRUCTIONS
'C
DPS8000
Bull
•
GCOS8
ASSEMBLY
INSTRUCTIONS
DPS8000
SUBJECT
Description of the Assembly Instructions for the DPS 8000
Information System.
SOFTWARE SUPPORTED
GCOS 8 Software Release 2500
DATE
March 1987
Worldwide
Infonnation
ORDER NUMBER
Systems
DZ51-00
Bull
~
PREFACE
""~'
This manual contains information that enables the user to code programs in
symbolic machine language which is then translated into binary machine
instructions.
This manual is directed to users who are experienced in coding within the
environment of a large-scale computer installation. Considerable knowledge and
practical experience is required in the use of address modification with
indirection, hardware indicators, fault interrupts and recovery routines, macro
operations, pseudo-operations, and other features normally encountered in a
large computer with a flexible instruction repertoire under control of a master
executive program. It is assumed that the user is familiar with the two's
complement number system.
This manual includes the processor capabilities, modes of operation, detailed
descriptions of machine instructions, virtual memory addressing, paging, and
the representation of data. It should prove useful to programmers who are
responsible for analyzing conditions that cause system failures.
In this document, multiple vertical braces and brackets should be assumed to be a
single brace or bracket; for example:
{ }
{ }
{ }
represents
{ }
]
[ ]
[ ]
[
and
represents [
]
BULL DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILlTY AND FITNESS FOR A
PARTICULAR PURPOSE AND MAKES NO EXPRESS WARRANTIES EXCEPI' AS MAY BE STATED
IN ITS WRITTEN AGREEMENT WITH AND FOR ITS CUSTOMER. IN NO EVENT IS BULL
LIABLE TO ANYONE FOR ANY INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES.
THE INFORMATION AND SPECIFICATIONS INTmS DOCUMENT ARE SUBJECT TO CHANGE
WITHOUT NOTICE. CONSULT YOUR BULL MARKETING REPRESENTATIVE FOR PRODUCT
OR SERVICEAVAILABILITY.
Copyright © Bull HN Information Systems Inc., 1987, 1990
All Rights Reserved
File No.: IV13, 1313
DZ51-OO
LISTING AND CORRECTING
DOCUMENTS
The Problem Analysis Solution System (PASS) data base is an online tool that provides direct
communications between Bull software development organizations and Bull customers.
Documentation-related transactions available to customers via PASS include those which:
•
Generate a list of all software documents published for the current Software Release.
•
Prepare Software Technical Action Requests (STARs) regarding documentation
discrepancies.
Logon procedures for these functions and procedures for using PASS can be obtained by contacting
the Bull Technical Assistance Center (TAC).
DOCUMENT LISTING
A list of all GeOS 8 System software documents published for this Software Release and available
through the Bull CSO Marketing and Sales Order Entry (telephone 1-800-343-6665) can be
displayed via the NEWS facility of PASS. The document lists are available via the PASS meeting
SWDOC_AVAILABILITY.
DOCUMENTATION CORRECTIONS
Customers can submit documentation error reports via the PASS online STAR Maker facility.
Responses to STARs, as well as other documentation changes, also are contained on PASS.
(Documentation corrections contained on PASS may apply to prior Software Releases as well as to
the current Software Release.)
In addition, corrections to documents will be entered on the PASS data base. Query PASS
periodically to determine if any corrections exist. Corrections documented on PASS, if applicable
to the next release of the software, will be incorporated in to the next update of the manual.
iii/iv
DZ51-OO
/'
"\
(
CDNTBN'l'S
Page
SECTION 1 INTRODUCTION ••••••••••••••••••••••••••••••••••••••••••••••
1-1
Processor Features •••••••••••••••••••••••••••••••••••••••••••••••••••
Pipeline Architecture Of The DPS 8000 ••••••••••••••••••••••••••••••
Faults And Interrupts ••••••••••••••••••••••••••••••••••••••••••••••
Connect/Interrupt Mechanism ••••••••••••••••••••••••••••••••••••••••
Online Processor Tests •••••••••••••••••••••••••••••••••••••••••••••
Operator Modes •••••••••••••••••••••••••••••••••••
Processor Modes Of Operation •••••••••••••••••••
Non-Extended/Extended Modes ••••••••••••••••••••
Memory Addressing Modes ••••••••••••••••••••••••
Virtual Memory Paging ••••••••••••••••••••••••
Absolute Mode ••••••••••••••••••••••••••••••••
Reserved Memory Space ••••••••••••••••••••••••••••••••••••••••••••••••
Interval Timer •••••••••••••••••••••••••••••••••••••••••••••••••••••••
1-1
1-2
1-2
1-3
1-4
1-4
1-4
1-6
1-7
1-7
1-8
1-8
1-8
SECTION 2 REPRESENTATION OF DATA •••••••••••••••• • • • • • • • • • • • • • • • i
2-1
··..................
.................. ..
··..................
..
..................
·.................. .
••••
Formats ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
(
position Numbering •••••••••••••••••••••••••••••••••••••••••••••••••••
The Machine Word •••••••••••••••••••••••••••••••••••••••••••••••••••••
Character-Strings ••••••••••••••••••••••••••••••••••••••••••••••••••••
Character Positions ••••••••••••••••••••••••••••••••••••••••••••••••
Bit Positions ••••••••••••••••••••••••••••••••••••••••••••••••••••••
Li terals .••..•••..•..•••••••.••.••..••...•.••••••••••••••••.•••••••••
Binary Numbers •••••••••••••••••••••••••••••••••••••••••••••••••••••••
Fixed-Point Numbers ••••••••••••••••••••••••••••••••••••••••••••••••
Floating-Point Numbers •••••••••••••••••••••••••••••••••••••••••••••
Hexadecimal Floating-Point Numbers •••••••••••••••••••••••••••••••••
Quadruple-Precision Numbers ••••••••••••••••••••••••••••••••••••••••
Normalized Binary Floating-Point Numbers •••••••••••••••••••••••••••
Binary Representation Of Fractional Values •••••••••••••••••••••••••
Decimal Numbers ••••••••••••••••••••••••••••••••••••••••••••••••••••••
Decimal Data Character Codes •••••••••••••••••••••••••••••••••••••••
Floating-Point Decimal Numbers •••••••••••••••••••••••••••••••••••••
Decimal Number Ranges ••••••••••••••••••••••••••••••••••••••••••••••
2-1
2-1
2-1
2-2
2-2
2-3
2-3
2-3
2-3
2-5
2-5
2-6
2-7
2-8
2-8
2-9
2-10
2-11
SECTION 3 MEMORY ORGANIZATION •••••••••••••••••••••••••••••••••••••••
3-1
Virtual Memory •••••••••••••••••••••••••••••••••••••••••••••••••••••••
Working Spaces •••••••••••••••••••••••••••••••••••••••••••••••••••••
Page. Tables ••••••••••••••••••••••••••••••••••••••••••••••••••••••••
:Domalns ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
3-1
3-2
3-2
3-3
3-4
3-6
Segments •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
Deser i ptors ••••••••••••'••••••••••••••••••••••••••••••••••••••••••••
(
v
DZ51-00
OOICi15lr.l"S (cent)
",,
Page
Standard Descriptor ••••••••••••••••••••••••••••••••••••••••••••••
Standard Descriptor With Working Space Number ••••••••••••••••••••
Supe:r Deser i ptor •••••••••••••.••••••••••••••••••••••••••••••••• ~ ...
Supe:r Descriptor With Working Space Number •••••••••••••••••••••••
Extended Descriptor ••••••••••••••••••••••••••••••••••••••••••••••
Extended De~criptor With Working Space Number ••••••••••••••••••••
Entry Descrlptor •••••••••••••••••••••••••••••••••••••••••••••••••
DyDamlC Ll°nk°lng Descrlptor •••••••••••••••••••••••••••••••••••••••
Shrinking ••••••••••••••••••••••••••••••••••••••••••••••••••••••••
o
0
SECTION 4 PROCESSOR ACCESSIBLE
R~STERS
••••••••••••••••••••••••••••
Accumulator Register (A) •••••••••••••••••••••••••••••••••••••••••••••
Quotient Register (Q) ••••••••••••••••••••••••••••••••••••••••••••••••
Accumulator-Quotient Register (AQ) •••••••••••••••••••••••••••••••••••
EXponent Register (E) ••••••••••••••••••••••••••••••••••••••••••••••••
Exponent-Accumulator-Quotient Register (EAQ) •••••••••••••••••••••••••
I..ow Operand Register (LOR) •••••••••••••••••••••••••••••••••••••••••••
Index Registers (xn) •••••••••••••••••••••••••••••••••••••••••••••••••
General Index Registers (GXn) ••••••••••••••••••••••••••••••••••••••••
Indicator Register (IR) ••••••••••••••••••••••••••••••••••••••••••••••
Timer Register (TR) ••••••••••••••••••••••••••••••••••••••••••••••••••
Instruction Counter (Ie) •••••••••••••••••••••••••••••••••••••••••••••
Address Registers (ARn) ••••••••••••••••••••••••••••••••••••••••••••••
Linkage Segment Register (LSR) •••••••••••••••••••••••••••••••••••••••
Instruction Segment Register (ISR) •••••••••••••••••••••••••••••••••••
Segment Descriptor Registers (DRn) •••••••••••••••••••••••••••••••••••
Segment Identity Registers (SEG[Dn) ••••••••••••••••••••••••••••••••••
Instruction Segment Identity Register - S~D(IS) ••••••••••••••••••••
Pointer Registers (PR) •••••••••••••••••••••••••••••••••••••••••••••••
Option Register (OR) •••••••••••••••••••••••••••••••••••••••••••••••••
calendar Clock Register (eCR) ••••••••••••••••••••••••••••••••••••••••
Working Space Registers (WSRn) •••••••••••••••••••••••••••••••••••••••
safe Store Register (SSR) ••••••••••••••••••••••••••••••••••••••••••••
Stack Control Register (SCR) •••••••••••••••••••••••••••••••••••••••••
Argument Stack Register {ASR) ••••••••••••••••••••••••••••••••••••••••
Parameter Segment Register (PSR) •••••••••••••••••••••••••••••••••••••
High Water Mark Register (HWMR) ••••••••••••••••••••••••••••••••••••••
Data Stack Descriptor Register (DSDR) ••••••••••••••••••••••••••••••••
Data Stack Address Register (DSAR) •••••••••••••••••••••••••••••••••••
Page Directory Base Register (PDBR) ••••••••••••••••••••••••••••••••••
O>U Moo.e Register (MR.) •••••.••••••••••••••••••••••••••••••••••••••••••
cache Mode Register (CMR), Lockup Fault Register (LUF} •••••••••••••••
Configuration Register (PORT ASSIGNMENT) (CR) ••••••••••••••••••••••••
Address Trap Register (ATR) ••••••••••••••••••••••••••••••••••••••••••
Virtual Address Trap Register (VATR) •••••••••••••••••••••••••••••••••
3-8
3-10
3-11
3-12
3-12
3-13
3-14
3-15
3-16
4-1
4-3
4-4
4-4
4-5
4-5
4-6
4-6
4-7
4-8
4-12
4-13
4-13
4-15
4-15
4-16
4-17
4-18
4-19
4-19
4-20
4-21
4-21
4-22
4-23
4-23
4-24
4-25
4-25
4-26
4-26
4-28
4-30
4-32
4-33
_/J
"-
,
vi
DZS1-00
"
"
/
CDlft'BIITS (cxm.t)
Page
Reserve Memory Base Register (RMBR) ••••••••••••••••••••••••••••••••••
SCU Fault Register (SCUFR) ••••••••••••••••••••••••••••••••••••••••••.
Syndrome Register (SYR) •••.••••••••••••••••••••.••••••••••••••••••••.
SCU Configuration Register (SCUCR) •••••••••••••••••••••••••••••••••••
SCU History Register bits are added to each word pair
before the words are stored. When words are requested from a memory unit, the
EDAC bits are read from memory, verified, and removed before sending the word
pair to the processor.
The processor
processing of
memory, their
pair of words
has many built-in features for efficient transferring and
pairs of words. When a pair of words is transferred to or from
addresses are an even number and the next higher odd number. A
is arranged as follows.
2-1
DZ51-00
o
3 3
5 6
7
A Pair of Machine Words
Even Addresss
Odd Address
In an instruction intended for handling pairs of machine words, either of the
two addresses may be used as the effective address (y). Thus,
If Y is even, the pair of locations (Y, Y+l) is accessed. If Y is odd, the
pair of locations (Y-l, y) is accessed. The term "Y-pair"· is used for each
pair of addresses. Preferred coding practice refers to the even address; the
GMAP assembler issues a warning diagnostic if Y is odd in an instruction
intended for handling pairs of machine words.
Cllaracter Positions
Alphanumeric data is represented by 9-bit, 6-bit, or 4-bit characters. A
machine word contains either four, six, or eight characters, respectively.
character positions within the word are as follows:
The
9-Bit Character (Bytes):
o0
8 9
0
0
0
I
2 2
6 7
1 1
7 8
1
I
2
I
3 <--- Bit positions
5
within word
1<--- Byte
positions
within word
3
I
6-Bit Characters:
o0
0
0
I
1 1
1 2
5 6
0
I
1
I
2 2
3 4
1 1
7 8
2
3
I
I
2 3
9 0
4
I
3
5
5
I
4-Bit Characters (Packed Decimal):
o0
o1
H
o0
001
890
4 5
0
I
1
H
1 1
3 4
2
I
2 2
.2 3
111
789
3
H
4
I
222
678
5
H
3 3
1 2
6
I
3
5
7
I
The Z represents the bit value 0; other numbers in the fields represent the
character positions.
~.\
~
2-2
DZ51-00
Bit Positions
(
Bit positions within a character are as follows:
101112131
4-bit character
1011121314151
6-bit character
9-bit character
Thus, both bit and character positions increase from left to right as in normal
reading.
LI'l'BRALS
For information on literals refer to the GODS B OS GMAP User's Guide.
Bl NARY NtJMBBR.S
Fixed-Point Nwabers
Binary fixed-point numbers are represented with half-word, single-word, and
double-word precision as shown below.
Representation
Precision
o
1
7
o
tUpper Half
/
Half-word
/
\
\
1
3
B
5
\Lower Half
o
3
5
o
Single-word
o
o
3 3
5 6
7
1
~~~e- .I______~=---~~------------~I------~~~~------------~I
Even Address
Odd Address
2-3
DZ51-00
Instructions can be divided into two groups according to the way in which) the
operand is interpreted: the "logic" group and the "algebraic" group.
For logic operations, operands and results are regarded as unsigned, positive
binary numbers. In the case of addition and subtraction, the occurrence of an
overflow is indicated by the carry out of the most significant (leftmost) bit
position:
1. Addition
- If the carry out of the leftmost bit position equals 1
(Carry indicator ON), the sum is above the range.
2. Subtraction
- If the carry out of the leftmost bit position equals 0
(Carry indicator OFF), the difference is below the range.
In the case of comparisons, the zero and carry indicators show the relation.
For algebraic operations, operands and results are regarded as signed binary
numbers, and the leftmost bit is used as a sign' bit (aO being plus and 1
minus). When the sign is positive, all the bits represent the real value of the
number; when the sign is negative, they represent the two's complement of the
real value of the number.
In the case of addition and subtraction, the occurrence of an overflow is
indicated by the carries into and out of the leftmost bit position (the sign
position). If the carry into the leftmost bit position does not equal the carry
out of that position, then overflow has occurred. If overflow has been detected
and if the sign bit equals 0, the result is below range; if with overflow the
sign bit equals 1, the result is above range.
In integral arithmetic, the location of the decimal point is assumed to the
right of the least significant bit positionr that is, depending on the
precision, to the right of bit position 35 or 71 (17 for upper half-word).
The number ranges for the various·cases of precision, interpretation, and
arithmetic are given in Table 2-1.
Table 2-1.
Ranges Of Fixed-Point Numbers
Precision
Interpretation Arittmetic
Algebraic
Hal f_ord
YO ... 17)
Single-Word
(A.O,Y)
Double-Word
(AO,Y-pair)
_217~~{217_1)
-2 3S~~(2 3S_ 1 )
-2 71~'-(2 71_ 1 )
-1~'-(1-2-17)
-1~~( 1-2 -3S)
-1~'-( 1-2 -71)
Integral
0~'-{2 18_ 1 )
0~'-(2 36_1)
0"",-(2 72 _ 1 )
Fraet ional
O~,-( 1-2 -18)
O~,-( 1-2 -36)
O~~( 1_2-72 )
Integral
Fractional
(Xn,
Logic
2-4
-
DZ51-00
Ploating-Point Numbers
( '.'
Floa~iI,lg-point numbers are represented with single-word and double-word
preclslon. The upper 8 bits represent the integral exponent to the base 2 in
two's complement form, and the lower 28 or 64 bits represent the fractional
mantissa in two's complement form.
The format for a floating-point number is:
assumed
point
o0 0
7 8 9
~radix
0 0
0 1
Single-Word
Precision:
"
o0
o1
Double-Word
Precision:
C
Exponent ><
Mantlssa
>
assumed
-radix point
o0 0
7 8 9
S
<
= sign
S
S
<
where S
3
5
7
1
S
Exponent ><
Mantlssa
>
bit
Before performing binary floating-point additions or subtractions, the processor
aligns the number that has the smaller exponent. To maintain accuracy, the
lowest permissible exponent of -128, together with the mantissa of zero, has
been defined as the machine representation of the number zero (which has no
unique floating-point representation). Whenever a floating-point operation
yields an untruncated resultant mantissa equal to zero (71 bits plus sign
because of extended precision), the exponent is automatically set to -128.
Hexadecimal Ploating-Point Numbers
The hexadecimal option may be used in floating-point operations to declare
hexadecimal constants, either explicitly or by default. The term hexadecimal
refers to a floating-point format where the mantissa is a binary number, while
the exponent represents a power of 16 (2**4). The mantissa is shifted by the
number of places for 4-bit groups as required by the exponent.
The hexadecimal floating-point mode is enabled only when bit 32 of the Indicator
Register is set to 1 and bit 33 of the mode register is set to 1. After the
hexadecimal floating-point mode is requested, the user controls the
floating-point mode via the Indicator Register. If the bit 32 of the Indicator
Register is not set to 1, the floating-point mode will be binary.
(
2-5
DZ51-00
Quadruple-Precision lumbers
The data format used in quadruple-precision arithmetic is illustrated below.
Notice that the format of data to be used in an operation is somewhat different
from that of data to be stored after the operation.
The format for data when an operand in main memory is used as arithmetic data:
y-pair
Y+2 pair
\1
I
o 0 0
7 7
1 2
078
1\
4
8 8
3 4
3
\\\\\\\\
MU
EO
0
7 0
\\\\\\\\
63 0\\\\\11 0
ML
59
Ignored
The format for data when the result is stored in main memory is as follows:
o0
0
0
7 8
10EU,Io
1
4
3
7 7 788 8
1 2 903 4
3
5
NO
ML
63 1oEL,1 0031
I
1-
o is
591
set
o The data in memory must reside on a double-word boundary.
o The four words of data may span two pages.
The registers E, AQ, and LOR are used for quadruple-precision arithmetic.
format for data used as operation data is as follows:
E
I-V
000
078
0
LOR
AQ
\1
1\
7 7 7 8
1 2 9 0
MU
EO
9 9
5
1
1 2
\\\\ \\\\\\\\
\\\\ \\\\\\\\
ML
63 0\\7 0\\\\\11 0
7 0
The
59
Ignored
The contents of EAQ and LOR following an operation is as follows:
1
5
7 7 7 8 889 9
000
1 2
9 0
781 2
MU
ML
1------- 0 is set
2-6
J
DZ5I-00
Field Values
EU
Exponent
Mil
High Order Mantissa
EL
ED -15 (residue)
ML
Low-order mantissa
Quadruple-precision value N = (MU
+
ML)16ED
The quadruple-precision instructions operate with the exponent as a hexadecimal
exponent regardless of the value of bit 32 of the indicator register (IR).
Normalized Binary Floating-Point Humbers
For normalized binary floating-point numbers, the binary point is placed at the
left of the most significant bit of the mantissa (to the right of the sign bit).
Numbers are normalized by shifting the mantissa left (and correspondingly
adjusting the exponent) until no leading zeros are present in the mantissa for
positive numbers, or until no leading Ones are present in the mantissa for
negative numbers. The vacated bit positions on the right are zero-filled.
The number ranges resulting from the various cases of precision, normalization,
and sign are given in Table 2-2.
(
Table 2-2.
Ranges Of Binary Floating-Point Numbers
Sign
S.ingle Precision
Positive _2:129~(1_2-27)2127
NOFn'ICII i zed
Double Precision
2129~(1_2-63)2'27
Negot ive (_1+2-26 )2-129~2127 (_1+2-62)2-'29~2127
Positive
2-1SS~( 1_2-27)2127
2-191~(1_2-63 )2 127
UnnoFn'ICII i zed
Negot ;ve
_T1S5~2127
_T1SS~_2127
NOTE: The floating-point number zero is not included in the table.
2-7
DZ5l-00
Binary Representation Of Fractional Values
A decimal fraction of a given number of digits cannot necessarily be represented
exactly by a binary fraction of any finite number of bits. Consider, for
example, the value 115, which is represented in decimal notation as 0.2. Trying
to represent it by a four-bit binary fraction, one obtains (.0011)2 or 3/16:
with eight bits, one obtains (.00110011)2 or 51/256. In fact, the exact value
must be written as
(0.2)10
= (0.0011)2 •••
which means that the bit pattern 0011 in the binary expansion keeps repeating
indef ini tely. I f the decimal value 0.2 is converted to a binary expansion of 71
bits and then converted back, the one-digit result would be 0.1, quite different
from 0.2. The four-digit result would be 0.1999, which is almost (but not
quite) equal to 0.2. If computations were involved instead of only conversions,
the imprecision in the decimal result could be propagated.
Various adjustments can be made to binary fractional values to make exact
decimal results highly probable. One may use binary integer notation to
represent all values, whether integral or fractional, but this may make
multiplication or division of an operand by a power of 10 necessary in the
course of a computation.
DDMAL NUMBERS
Scaled decimal numbers that are used directly in hardware arithmetic commands
are expressed as decimal digits in either the 4-bit or 9-bit character format.
They are expressed as unsigned numbers or as signed numbers using a separate
sign character.
r '\
,,
",,->
2-8
DZ51-00
Decimal data utilizes the following formats:
(
o0
aa
aa1
111
1 1
2 2
222
333
222
3
Packed Decimal (4-bi t )
00
001
.1:~1_1_____
111
8~1_:.IO______
0_____
7.1:~1~9_____
1 _____
6~1_:.IB______
2_____
3 _____51
ASCII/EBCDIC (9-bit)
Z represents unused bit positions.
Dec:iJIal Data Character Codes
During arithmetic operations, decimal digits and signs are checked by the
hardware as 4-bit data (the 4 least significant bits from a 9-bit numeric).
The following interpretations are made:
(
Bit Pattern for
Character
0000
0001
0010
0011
0100
0101
0110
0111
0100
1001
1010
1011
1100
1101
1110
1111
Interpreted as
Illegal Procedure
(IPR) if
a
1
2
3
4
found where
descriptor
specifies sign
5
6
7
8
9
+
+
+
-
+
+
found where
descriptor
specifies
digits
(
2-9
DZ5l-00
The following codes (9-bit zones are created by prefixing binary 00010) are
generated for output signs; the octal values are:
Plus
4-bit
9-bit
14(13)
053
Minus
15
055
For several numeric instructions, a sign value of 13 can be optionally
generated.
Floating-Point DeciEl Numbers
The format for a floating-point decimal number expressed in 9-bit characters is:
I
8-bi t
I SIGN 1 ,0n •• . ,02 1 10 '
10 0
101
EXPONENT
I
where: SIGN can start at any legal 9-bi t character boundary
In 4-bit character notation, there are four fonmats for floating-point
decimal numbers:
4-Bit
10 0
0
EXPO
'"-_ _ _ _.Even character boundary, odd' of digits. (I of digits .. n+1)
4
'"-_ _ _ _Odd charoc ter boundary,
The a-bit exponent field, which now spans two character positions, is
interpreted the same as in 9-bi t character mode. The other two formats are
formed with n+l even. This effectively exchanges the two exponent
representations in the formats shown.
!/c\
~~_/
2-10
DZ51-00
Decillal Humber Ranges
(
The number ranges for decimal numbers are:
1. Fixed-point unsigned integer:
Range = 0 ••• 1063
2. Fixed-point signed integer:
Range
= :!:
1062
3. Floating-point (implicitly signed):
a. 9-bit format range - :!: 1061
* 10+127 -128
b. 4-bit format range - :!: 1060
* 10+127 -128
c. Zero
= :!:O *
10+127 -128
(
2-11
DZ51-00
"',,
/.
I"
\
~,/
(
SIC'l'ION 3
The Central Processing Units (CPUs) access the main memory through the System
Control Unit (SCU). Similarly, the Input/Output Multiplexer (INK) also accesses _
memory through the SCU. As a component, the SCU is a passive system element,
responding to requests from active units, the O'Us and the IMXs. This large,
memory-oriented system architecture, permits both CPU and INK functions to
execute asynchronously and concurrently. The functions of read, store,
interprocessor communication, etc., are provided by the SCU.
Increased system throughput is achieved by operating the SCU and associated
memory units on a 72-bit parallel basis. This corresponds to two single-word
instructions, two data words, or one double-precision fixed-point or
floating-point number.
Systems with more than one system controller provide an increased effective
information rate, since each system controller operates independently and its
functions can be overlapped with those of other system controllers •
(
. Additional overlap is provided by memory interlacing. Each DPS 8000 SCU
operates with full memory unit interlacing, in 8-word block increments, to
reduce the possibility of the same memory unit being accessed in succession.
VIRTUAL MEMORY
Virtual memory (VM) provides an extremely large, directly addressable memory
space (2**43 bytes) and a complement of registers and instructions to manage
virtual address space. The VM space is divided into a number of working
spaces. The working spaces are further divided into variable sizes called
"segments". A segment within a working space is described by a "segment
descriptor", which has a base relative to the origin of the working space and a
bound relative to the base, together with control information. Thus, for all
memory references, virtual memory addresses are prepared relative to a
particular working space and to a particular segment base within the working
space. These virtual memory addresses are then mapped to real memory addresses
by paging mechanisms.
3-1
DZ5l-00
To access (generate a memory address for) an area of VM, a process (used here to
mean the smallest working unit of software) must have a segment descriptor that
"frames" the particular segment of VM and that.gives the desired permission for
using this segment of VM (Le., Read permission, Write permission, or Execute
permission). A process cannot create a segment descriptor, nor change the base
and bound to access an area of VM not enclosed by the area originally "framed",
nor increase the permissions field. Therefore, a process is limited to
accessing only those areas of VM described b¥ segment descriptors that are
available to the process.
The hardware environment for the virtual memory is composed of four elements 1 :
working spaces, domains, segments, and pages. .The working spaces and pages are
physical elements, whereas the segments and domains are logical elements. These
elements are treated as separate components ·of the virtual memory but must be
interpreted in the context of the whole environment, since they are closely
related in their interaction with each other.
Working Spaces
The virtual memory is divided into 512 (0 through 511) working spaces (WS) of
2**34 bytes, each of which is divided into fixed-length pages. These pages are
used for memory management and have a fixed size of 1024 words (4096 bytes)
each. Working space numbers (WSN) used to generate a particular virtual memory
address are obtained frOm one of eight working space registers (WSR) or a
segment descriptor register (DRn).
Page Tables
Each working space has an associated page table that identifies the real memory
allocation. The page table or section table for each working space is located
in real memory by a pointer that resides in the working space page table
directory (WSPTD). The directory has 512 entries and the pointer to the
directory is stored in the page directory base register (PDBR). Directory
entries are either pointers to page tables or pointers to section tables. The
section table (SCT) consists of up to 4K words called page table base words
(PBW) that allow page tables to be divided and distributed throughout the
memory. These pointers and tables can only be altered in the Privileged Master
mode.
The virtual address has three components: a working space number (WSN), a page
number, and a page byte number (commonly called an offset). The virtual address
is automatically transformed to a real address by the hardware.
1. Historically, discussion of virtual memory included reference to working
space quarters, described in this manual as working spaces. The working
space quarter concept is not used by any software implementation;
therefore, no further mention of working space quarters occurs in this
manual. The hardware has not been changed.
3-2
DZSI-OO
Domains
Another logical element of the virtual environment is the domain. A domain is
the particular subset of virtual memory that currently can be accessed by a
process. It is defined initially by the collection of descriptors contained
within the linkage segment (the segment described by the contents of the LSR).
The domain is a flexible and temporary range of operation that may encompass
several noncontiguous segments in one or more working spaces (see Figure 3-1).
Two or more domains may interact by including the same segment descriptor. Each
domain contains exactly one linkage segment to define the domain. A change of
domain implies a change of linkage segment and vice versa.
Descriptors for
the domain may also be in descriptor segments described in the linkage segment,
in descriptor registers, or in the parameter segment.
WSN Y
-- -- ----\
\
> Page 0
/
/
\
\
Segment d
> Page 1
/
/
\
\
- - - - - - - - \/
> Page 2
/
\
> Page 3
Segment e
- --- - - --
Figure 3-1.
/
/
Domain Of Noncontiguous Segments
3-3
DZ51-00
Also associated with the process are the safe store stack and the data stack
segments. The safe store stack is always used (except for GClJMB and PClJMB) in
a change of domain, but a new domain mayor may not choose to access a different
portion of the data stack segment. It does not have access to that portion used
by the calling domain.
Normally, a change of domain is accomplished through a succession of operations
that are associated with the ICLIMB instruction. Starting with two separate
domains, which for convenience are referred to as calling domain and called
domain, the entry descriptor accessed in the calling domain describes the
called-domain linkage segment and identifies a specific initial instruction in
an instruction segment described in that linkage segment. The contents of the
calling domain's registers (LSR, ASR, PSR, and DSAR), as well as those of any
other registers specified by the type of entry descriptor, are safe stored.
The change-of-domain
instruction indicates whether there are parameters
The arguments may be either vectors or
descriptors. (Refer to discussion of LDDn instruction in section 8.) If the
arguments are vectors, descriptors are prepared using the vectors and stored to
form a parameter segment for the called domain.
CLIMB
and the number of arguments.
The source of the list of vectors or descriptors is given as the contents of
pointer register zero. (Descriptor register zero identifies the segment in
which the list occurs and indicates whether vectors or descriptors are listed.
Address register zero gives the offset in that segment of the list.) On
change-of-domain return (OClJMB), the contents of the calling-domain's domain
registers and any other register contents that were safe stored are restored.
Segments
.,,- j
Another division of the working space is the segment. Each segment is a logical
entity of variable length and may be as small as one byte or as large as 232
bytes. Consequently, a segment may reside on a portion of a page or span
several pages. (Refer to Figure 3-2). Segments are described with two-word
(72-bit) segment descriptors. When a virtual address is generated, the segment
descriptor is located in the segment descriptor register. segments in virtual
memory are specified with a base value which is relative to the origin of the
WS, and a bound which is relative to the base.
3-4
DZ5l-00
Working Space
(
/
/
Page 0
<
<--Segment a
\
<-Segment b
\
/
\
/
Page 1
\
<
\
\
/
--------->
/
Page 2
<
Segment c
\
\
/
---------/
/
Page 3
<
/
\
\
----------
Figure 3-2.
(
Layout Of segments On Pages
To understand the relationship between pages and segments, it is necessary to
understand the structure of a working space. The combination of a working space
number and offset within the related working space is called a virtual address.
Pages of lK size are ordered sequentially b¥ virtual page number within a
working space. Each page is represented b¥ a page table word (P'l'W) that points
to a real page, if that page is in memory.
A segment is a logical sequence of virtual addresses, starting from a base and
of a size equal to the bound of that segment. The base and bound of a segment
are contained in a system protected, two-word structure called a segment
descriptor. A segment may be small, contained anywhere within a page, or it may
span multiple pages, irrespective of page boundaries.
A segment is characterized by its elements and the form of access to these
elements, which can be Execute, Read, or Write. Segments are classified either
as descriptor segments or operand segments. The descriptor segments that
contain valid descriptors as part of their contents may be used as linkage,
parameter, argument, or safe store segments; whereas the operand segments may be
instruction-only, data-only, instruction and data segments, or data stack
segments as illustrated in the following diagram.
(
3-5
DZ5l-00
,/
Seljp'l"ent
L inkage Parcmeter Arg&ment Safe Store
Seljp'l"en t Se.".n t
Segnen t
Se9'lln t
(LS)
(PS)
(AS)
(55)
Instruct ion
Se.".nt
( IS)
Data
Dato Stock
Se9'llnt
(OS)
Se.,.,.nt
(DSS)
A segment of either class may also be loaded into one of the eight operand
descriptor registers (DRg).
Descriptors
A descriptor consists of a 72-bit word-pair and locates a segment in virtual
memory. When the processor hardware obtains a descriptor from memory, the
processor assumes that the descriptor begins on an even-word boundary and
ignores the least significant bit of the virtual word address. If a descriptor
is stored from a register, the processor hardware stores on an even-word
boundary.
To allow a process to have access to a segment, a copy of the descriptor must be
obtained to locate the segment in virtual memory. Also, the descriptor
delimits, through a set of flags, what forms of access to the segment are
available.
Twelve types of descriptors are available. Those segments containing
instructions, data, or a combination of both are commonly called operand
segments .and have descriptors that are either type 0, 2, 4, 6, 12, or 14 to
indicate operand storage. The segments containing only descriptors !! can access both operand segments and segment
descriptor segments because LDDn performs different operations with each
access. These instructions indirectly access segment descriptors through
operand segments. The safe store stack contains data other than segment
descriptors. However, it is specified· with type 1 or 3 segment
descriptors. The safe store stack does not contain operand data and
cannot be accessed except with Privileged Master Mode. Using this mode,
the segment descriptor for the safe store stack can be obtained and
converted to a type 0 or 2 segment descriptor. (Refer to the LDI>!!
instruction description in Section 8.)
STANDARD DBSClUP'l'OR
The format of the standard descriptor is:
o
1 2
9 0
o
2 2
3 3
8 9
125
Flags
Bound
20
WSR
9
3
4
Even
Word
36
Word
Type
3
Base
Odd
Bound -
A
20-bit field that is the maximum valid byte address within the
segment; bits 0-17 are the word address and bits 18-19 are the
9-bit byte address. The bound is relative to the base. A zero
bound indicates a I-byte segment if bit 27 is 1.
Flags -
A 9-bit field that describes the access privileges as well as other
control information associated with the descriptor:
1(- -\
I~_j
3-8
DZ5l-00
C
Bit
Flag
Code
20
R
Meaning
Read
a
1
21
W
Write
a
1
22
S
1
C
Write not allowed
Write allowed
Store by STDn
a
23
Read not allowed
Read allowed
Descriptor may not be stored in a type 1 or 3
segment by the STDn instruction.
Descriptor may be stored in a type 1 or 3
segment by the STDn instruction.
cache Use Control
Not used by
24
x
a
E
a
P
1
B
o
A
o
-
Bound not valid; segment empty.
Bound field maximum valid address.
Available segment
1
WSR
Privileged Master mode not required for
execution
Privileged Master mode required for execution
Bound valid
1
28
Execute not allowed
Execute allowed
privilege
a
27
NS Mode
ES Mode
Execute
1
26
8000
NS/ES Mode (when in I SR; otherwise ignored)
1
25
DPS
Segment not available; references not allowed.
Segment available; references allowed.
A 3-bit field that specifies which of the eight working space
registers to use with this descriptor. The working space register
supplies the working space number (WSN).
(3-9
DZ5l-00
Type
-
Base -
A 4-bit field that defines the descriptor type.
standard descriptors are:
The two types for
Type
= 0 The descriptor "frames" instruction/operand space.
Type
=1
The descriptor "frames" an address space containing
descriptors.
A 36-bit virtual byte address that is relative to the working space
defined in the WSR. Bits 0-33 are a 34-bit word address and bits
34-35 represent a 9-bit byte within the word.
STANDARD DBSCRIP'l'OR WI'l'B liORKIlfG SPACE JfUJIBBR
The format of the standard descriptor with working space number (WSN) is:
o
o
1 2
9 0
Bound
20
2 2
2 3
Flags
3
3 3
1 2
WSN
3
5
4
Even
Word
36
Odd
Word
Type
9
Base
This format is the same as that for the standard descriptor except that the
flags field has been truncated to allow the descriptor to contain the actual
working space number rather than point to a working space register. The three
flag bits are the same as the corresponding flag bits of the standard
descriptor. The state of the truncated flags is assumed as follows:
Flags -
1. Execute not allowed (HE)
2.
Not privileged
(NP)
3. Bound valid (B)
4. Segment available (A)
WSN
-
The actual working space number.
Type
-
A 4-bit field that defines the descriptor type.
standard descriptors witn WSN are:
The two types for
Type = 2
The descriptor "frames" operand space.
Type = 3
The descriptor "frames" an address space containing
descriptors.
3-10
DZ5l-00
/ "'.
SUPER DESCRI PTOR
Super-descriptors may be used to define large segments. The definitions of the
flags WSR WSN, and type fields of the super-descriptor are the same as those
of the standard descriptor. The base and bound fields are automatically
extended on the right to a length of 36 bits. The base is extended with zeros
and the bound is extended wi th ones.
I
I
Therefore, a super descriptor with base, location, and bound of zero describes
a segment that begins at location zero of a working space and extends 2**26
bytes (16 million words). A super descriptor with a base of 1, and location of
zero, and a bound of 3 describes a segment that starts at location 2**26 and
extends 2**28 bytes (64 million words).
The format of the super descriptor is:
o1
o
o
1 2
9 0
9 0
2 2
89·
Flags
Bound
Base
10
10
9
3 3
12
3
5
WSR Type
3
4
Location
Odd
36
(
Even
Word
Word
10-bit virtual address (unit 2**26 bytes) within a working
space. The 10-bit base is converted to a 36-bit base /
4-2
DZ51-00
(
(1)
These registers are not separate physical assemblies but are
combinations of their constituent registers.
(2)
The pointer registers are not distinct physical registers but are a
collective group of registers (DRn, ARg, S~Dn).
(3)
These registers exist in the system controller. However, because
they may be read and/or written with processor instructions, they
have been included in this tablE.
In the descriptions that follow, the diagrams given for register formats do not
imply that a physical assembly possessing the pictured bit pattern actually
exists. The diagram is a graphic representation of the form of the register
data as it appears in memory when the register contents are stored or how data
bits must be assembled for loading into the register.
I f the diagrams contain the character "x" or "0", the value of the bit in the
position shown is irrelevant to the register. Bits pictured as "x" are not
changed in the receiving cell when the register is stored. Bits pictured as "0"
are set to 0 in the receiving cell when the register is stored. Neither "x"
bits nor "0" bits are loaded into the register. If fields contain the "I"
character, the field is not used.
NOTE: Following descriptions of all of the programmable registers, the registers
used only in Privileged Master Mode are described.
(
ACCUMULA'l'OR RE;I S'l'ER (A)
Format: 36 bits
1 1
7 8
0
0
A-Upper
I
18
Figure 4-1.
I
3
5
A-Lower
18
I
Accumulator Register (A) Format
Description:
A 36-bit physical register
Function:
In fixed-point instructions, holds operands and results.
In floating-point instructions, holds the most significant part of the
mantissa and the result.
4-3
DZ51-00
In shifting instructions, holds original data and shifted results.
In address preparation, may hold two logically independent offsets, A-upper
and A-lower, or an extended range bit- or character-string length.
QUOTI BH'l' lUG S'l'ER (Q)
Format:
36 bits
o
1 1
Q-Upper
3
Q-Lower
18
Figure 4-2.
18
Quotient Register registers
Function:
In fixed-point binary instructions, holds double-precision operands and
results.
In floating-point instructions, holds the mantissa and the result.
In shifting instructions, holds original data and shifted results.
EXPOlIBNT RB:;I S'l'BR (E)
Format:
B bits
o
0 0
3
zeros
B
2B
Figure 4-4.
Exponent Register (E) Format
Description:
An
B-bit physical register
Function:
In floating-point instructions, holds the exponent.
Format:
0
0
I
BO bits
o0
(E)
Exponent
7
7 0
(AQ)
I
8
Mantissa
Figure 4-5.
1
72
I
Exponent-Accumulator-Quotient Register (EAQ) Format
(
4-5
DZ51-00
Description:
A combination of the exponent (E), accumulator (A), and quotient
registers. Although the combined register has a total of 80 bits, only 72
are involved in transfers to and from main memory. The low-order 8 bits are
discarded on store and zero-filled on load (that is, Q-register bits 28-35
are zero on load; bits 64-71 of the AQ Register are ignored). See
"Floating-Point Arithmetic I~tructions" in Section 7.
Function:
In floating-point instructions, holds operands and results.
IDW OPBRARD R!GIS'l'BR (LOR)
Format:
°°
72 bits
00
70
7 0
:,1r.::0:....-_ _- - - - - - - - - - - : : 1 : . , -
I~~ ~ ~ ~ ~ ~~R~~S~.: ~ ~ ~ ~ ~ I
7
Low Operand Register
I
6~4~----------------------~7~2
8
Figure 4-6.
Low Operand Register Format
D e s c r i p t i o n : / ' '\
The lower operand register (LOR) functions in combination with the exponent
(E), accumulator (A), and quotient (Q> registers in quadruple-precision
floating-point operations.
Function:
The 72-bit lower operand register is used for the lower mantissa of
quadruple-precision (four words) with floating-point operations.
INDEX R!GISTERS ( len)
Format:
18
bits each (NS Mode)
o
1
7
18
Figure 4-7.
Index Register (Xn) Format
4-6
DZ5l-00
Description:
(
Eight IB-bit physical registers numbered 0 through 7. Index register data
may occupy the position of either an upper or lower IB-bit half-word operand.
Function:
In fixed-point binary instructions, hold half-word operands and results.
In address preparation, hold bit, character, or word offsets or hold extended
range bit- or character-string lengths.
GENERAL I HDEK RJGS'l'ERS (GXn)
Format:
36 bits (ES Mode)
Figure 4-B.
General Index Registers
(GXn)
Format
Descript ion:
Eight 36-bit physical registers numbered 0 through 7 used in ES mode only.
General register data may occupy the entire 36-bit operand.
Function:
May be used as a data operand register with fixed-point operations: however,
in the ES mode, GXn registers may be used as the single-precision operand
register.
In address preparation, hold bit, character, or word offsets or hold extended
range bit- or character-string lengths.
4-7
DZ51-00
I lID! CA'J.'OR JUG STER (I R )
Format:
18 bits
i
o
o
111 2 2 2 2 2 2 2 2 2 2 3 3 3 3
3
5
7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
xxxxxxxxxxxxxxxxxx a b c d e f 9 h i j k
1 mn p
18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 4-9.
r'
q
3
Indicator Register (IR) Format
Description:
An assemblage of 15 indicator flags from various units of the processor. The
data occupies the position of a lower l8-bit half-word operand. When
interpreted as data, a bit value of 1 corresponds to the ON state of the
indicator; a bit value of 0 corresponds to the OFF state.
Function:
The functions of the individual indicator bits follow.
Key
Indicator name
Action
a
Zero
This indicator is set ON whenever the output of
the main binary adder consists entirely of zero
bits for binary or shifting instructions or the
output of the decimal adder consists entirely of
zero digits for decimal instructions; otherwise,
it is set OFF.
b
Negative
This indicator is set ON whenever the output of
bit 0 of the main binary adder has value 1 for
binary or shifting instructions or the sign
character of the result of a decimal instruction
is the negative sign character; otherwise, it is
set OFF.
c
carry
This indicator is set ON for any of the following
conditions; otherwise, it is set OFF.
(1) If a bit propagates leftward out of bit 0 of
the main binary adder for any binary or
left-shifting instruction.
'\
,,-,./J
"
4-8
DZ51-00
Key
Indicator name
(
(
Action
(2)
If Ivaluell <= Ivalue21 for a decimal numeric
comparison instruction.
(3)
If charl <= char2 for a decimal alphanumeric
comparison instruction.
d
Overflow
This indicator is set ON if the arithmetic range
of a register is exceeded in a fixed-point binary
instruction or if the target string of a decimal
numeric instruction is too small to hold the
integral part of the result. It remains ON until
reset by the Transfer On Overflow (rov)
instruction or reset by some other instruction
that loads the IR. The event that sets this
indicator ON may also cause an overflow fault.
(see overflow mask indicator below.)
e
Exponent
overflow
This indicator is set ON if the exponent of the
result of a floating-point binary or decimal
numeric instruction is greater than +127. It
remains ON until reset by the Transfer On Exponent
Overflow ('l'EX) instruction or reset by some other
instruction that loads the IR. The event that
sets this indicator ON may also cause an overflow
fault. (see overflow mask indicator below.)
f
Exponent
underflow
This indicator is set ON if the exponent of the
result of a floating-point binary or decimal
numeric instruction is less than -128. It remains
ON until reset by the Transfer On Exponent
Underflow (TEU) instruction or reset by some other
instruction that loads the IR. The event that sets
this indicator ON may also cause an overflow
fault. (See overflow mask indicator.)
(
4-9
DZ5l-00
Key
Indicator name
g
Overflow mask
Action
This indicator is set to ON or OFF only by the
RET, and CLI MB instructions. When set ON , it
inhibits the generation of the fault for those
events that normally cause an overflow fault.
When the overflow mask is ON, no overflow fault is
generated if either the overflow or the exponent
overflow indicator is set to ON status. When the
overflow mask is set OFF, an overflow fault is
generated if either the overflow or the exponent
overflow indicator is set to ON status. If the
overflow mask indicator is set OFF after an
overflow event, an overflow fault does not occur
even though the indicator for that event is still
set ON. The state of the overflow mask indicator
does not affect the setting, testing, or storing
of any other indicator, nor does it affect the
overflow fault caused by the truncation indicator.
WI,
h
Tally runout
This indicator is set OFF at initialization of any
tallying operation. It is then set ON for any of
the following conditions:
(1)
I f any Repeat instruction terminates because
of tally runout.
(2)
If a Repeat Link (RPL) instruction terminates
because of a zero 1 ink address (NS mode
only) •
(3) I f a tally exhaust is detected for an
Indirect then Tally modifier. The
instruction is executed whether or not tally
runout occurs.
(4)
i
Parity error
I f a string scanning instruction reaches the
end of the string without finding a match
concHtion.
This indicator is set by the hardware when a
parity error occurs on an access to memory. It can
be set with the WI and STI instructions.
The
indicator is set OFF only by instructions that
load the IR.
r"~,
I
,;
"--/
4-10
DZ51-00
'
I
Key
Indicator name
Action
j
Parity mask
This indicator is set ON or OFF only by the LOI,
RET, and CLI ME instructions. When it is set ON,
it inhibits the generation of the parity fault for
all events that set the parity error indicator
even when a MEMSYS fault condition is detected.
If the parity mask indicator is set OFF
after a parity error event, a parity fault does
not occur even though the parity error indicator
may still be set ON. The state of the parity mask
indicator does not affect the loading, testing, or
storing of any other indicator.
k
Master mode
This indicator is set ON for an interrupt
acceptance, a fault acceptance, a PMME instruction
execution, and the execution of an OCLlMB
instruction (when the master mode bit of the
indicator register to be restored is ON). This
indicator is reset to OFF following the execution
of a TSS, RET (with operand bit 28=0), 0CLl MB
(when the master mcxie bit of the 1R to be restored
is OFF), or an 1eLI MB instruction (when the second
word bit 19=0).
1
Truncation
This indicator is affected only by multiword
instructions. It is set to ON during string
instructions when the source string length is
greater than the destination string length, and
set to OFF when the reverse is true. For decimal
arithmetic instructions, it is set to ON when
there are no rounding specifications and the
lowest digit, or more of the result is truncated,
and set to OFF when the reverse is true. When the
highest nonzero digit is lost, the Overflow
Indicator is set ON.
m
Multiword
instruction
interrupt
This indicator is set OFF by the execution of the
SPL instruction and by the end of execution of all
multiword instructions, and is set ON by the
events described below. The indicator has meaning
only when determining the proper restart sequence
for an interrupted multiword instruction.
(
This indicator is set:
When any fault or interrupt occurs during the
execution of a multiword instruction (except
CLIMB) :
(
4-11
-_._. __ ..-
...
_- ...•- ...-
....
~~~
DZ51-00
Key
Indicator name
Action
The ON state of this indicator is used during the
CLIMB (after a fault or interrupt) instruction,
for example, to save the pointers and lengths data
in order to resume the instruction.
Re$erved for future use
n
Hex mode
p
This indicator is set ON or OFF only by the
instructions that load the IR.
NOTE: When set ON with bit 33 of the CPU mode
register set ON, the floating-point
instructions are executed in the hexadecimal
exponent mode.
Reserved for future use
q
TI MER RlG: S'1'ER ('l'R)
Format:
27 bits
o
223
675
Timer value
,/
Figure 4-10.
Timer Register
(TR)
Format
Description:
27-bit settable, free-running clock. The value decrements at a rate of
512 kHz. Its range is 1.953125 microseconds to approximately 4.37 minutes.
A
4-12
DZ51-00
Function:
The TR may be loaded with any convenient value with the Load Timer Register
(LOT) instruction. When the value next passes through zero, a timer runout
fault is signalled. If the processor is in Slave mode with interrupts not
inhibited or is stopped at an uninhibited Delay Until Interrupt Signal (DIS)
instruction, the fault occurs immediately. If the processor is in Master or
Privileged Master mode or has interrupts inhibited, the fault is delayed
until the processor returns to Slave mode or st.ops at an uninhibited DIS
instruct ion.
I HS'i'RDC."i'I ON CDtJH'l'BR (I C)
Format:
18 bits
a
Instruction address
Figure 4-11.
Instruction Counter (IC) Format
Description:
An
(
1S-bit physical register
Function:
Holds the address of the current instruction being executed. The IC is
incremented by 1 by the control unit for the sequential execution of
single-word instructions or by the appropriate amount (2, 3, or 4) for
multiword instructions. The content of the IC is changed by a
transfer-of-control instruction or by a fault or interrupt.
A description of faults and interrupts is contained in Section 6.
ADDRESS RKiI S'l'ERS (AR.n)
Format:
24 bi ts each (NS Mode)
a
a
1 2
1 1
7 8 9
-Word
I
18
Figure 4-12.
la..rl
2
2
a
3
Bit
4
I
Address Register (AR!!) Format (NS Mode)
4-13
DZ51-00
Description:
Eight 24-bit physical registers numbered 0 through 7 that are associated
with the segment descriptor registers (DRn) and that allow address
modification on a word, character, or bit basis
Function:
The address registers provide address modification to the word, byte, and
bit level:
Word - 18 bits (0-17): a word offset within the segment described by the
associated segment descriptor register
Char -
2 bits; designates one of the four 9-bit characters (bytes) of which
the word is composed
Bit - 4 bits; designates one of the 9 bits within the character
Format:
36 bits each
(ES
Mode)
o
2 3 3 3
3
9 0 1
5
2
Word
Figure 4-13.
Address Register
(ARB)
Format (ES Mode)
Description:
Eight 36-bit physical registers numbered 0 through 7 that are associated with
the segment descriptor registers (DRn) and that allow addressing on a word,
character, or bit basis
Function:
In ES mode, each address register is extended to 36 bits. The ~ is as given
in two's complement form, with bit 0 as sign bit. In the effective address
generation, bit 0 is extended 4 bits to the left.
Word - 29 bits (1-29); a word offset within the segment described by the
associated segment descriptor register
Char - 2 bits; designates one of the four 9-bit characters (bytes) of
which the word is composed
Bit - 4 bits: designates one of the 9 bits within the character
4-14
DZ51-00
LI HKAGE SlGIEN'l' RPm STER (LSR )
(
Format:
72 bits
a
a
2 2
8 9
1 2
9 0
Bound
Flags
20
3 3
1 2
WSR
9
3
5
Type=l
4
3
Base
36
Figure 4-14.
Evenword
Oddword
Linkage Segment Register (LSR) Format
Description:
A 72-bit register that holds a type 1 standard descriptor that describes the
linkage segment of the current domain of the currently executing process
Function:
The linkage segment register is loaded only by executing a ClJMB
instruction. The linkage segment register may be stored by transferring the .
contents of the LSR to an segment descriptor register (DRn) and then storing
DRn. When the bound field of the LSR is loaded, bits 0-6 are forced to zero
and bits 17-19 are forced to 111. Thus, the size of the linkage segment is
effectively limited to 1024 descriptors.
I NS'l'RUC'l'ION SEX;MENT RPm S'l'ER (I SR)
Format:
72 bits
o
o
1 2
9 0
Bound
2 2
3 3
8 9
1 2
Flags
20
WSR
9
3
3
5
'l'ype=0
4
Base
36
Figure 4-15.
Evenword
Oddword
Instruction segment Register (ISR) Format
Description:
72-bit register that holds a type 0 standard descriptor that describes the
current instruction segment for the current domain of the currently
executing process.
A
(
4-15
DZ51-00
Function:
The instruction segment register may not be loaded or stored directly. The
register is loaded during the execution of a ClJMB or transfer instruction
with bit 29 ON. The lSR may be stored indirectly by moving its contents to
an segment descriptor register (DRn) and then storing DRn. If bit 29 of an
instruction word is zero or the AR bit in the MF field of a multiword
instruction is zero, the instruction segment register is used in forming the
virtual address of the operand. The base and bound values placed in the
lSR are constrained; the 5 least-significant bits of the base field must be
zero and the 5 least-significant bits of the bound field must be ones.
S1!9IBR'l' DESCRIP'l'OR JUG S'lBRS (DRn)
Format:
72 bits each
Description:
Eight 72-bit registers that hold segment descriptors that describe address
space contained within the current domain of the currently executing
process. The format of the descriptors is in accordance with the content of
the type fields; type fields 0, 2, 4, 6, 12, and 14 are used for operand
segments and type fields 1 and 3 are used for descriptor segments.
Function:
Instructions are available for loading and storing the segment descriptor
registers and for modifying their contents. A segment descriptor register
is invoked for virtual operand address development when bit 29 of the
instruction is 1; address bits 0, 1, and 2 specify which of the combined
segment descriptor register (DRn) and address register n (ARB) is to be
used. Each of these eight segment descriptor registers is associated with a
corresponding address register. For example, an AR3 modification refers to
the segment whose descriptor is the contents of DR3.. For multiword
instructions, the use of ARB and the associated DRn is specified by the AR
bit in theMF field. Refer to "Multiword Modification Field" in Section 5.
4-16
DZ5l-00
SlGmNT
(
IDENTI TY RPa STBRS (SlGDn)
Format:
12 bits each
000
D
Figure 4-16.
segment Identity Register (SEGID!!) Format
Description:
Eight 12-bit registers that have a one-to-one correspondence with the
segment descriptor registers (DR!!). The segment identity registers point to
the source of the descriptor in the DRn.
Function:
The SEGIDn registers are loaded concurrently with the related descriptor
registers (DRn). The S and D field codes used in these registers indicate
the origin of the descriptor (S = segment, D = descriptor offset).
When S
= 0:
The D field indicates the location of the segment descriptor loaded into
the ORn.
For D = 1760 through 1777 (octal), the selected register is copied into
the DR!!.
D = 1760
D = 1761
D = 1762
D = 1763
D = 1764
D = 1765
o = 1766
o = 1767
D = 1770
o = 1771
o = 1772
D = 1773
D = 1774
o = 1775
D = 1776
o = 1777
Undefined
The segment descriptor type field is changed. *
Instruction Segment Register (ISR)
Data Stack Descriptor Register (OSOR)
safe Store Register (SSR)
Linkage Segment Register (LSR)
Argument Stack Register (ASR)
Parameter Segment Register (PSR)
DRO, Descriptor Register 0 }
DRl, Descriptor Register 1 }
DR2, Descriptor Register 2 }
DR3, Descriptor Register 3 } self-Identifying
DR4, Descriptor Register 4 }
OR5, Descriptor Register 5 }
OR6, Descriptor Register 6 }
OR7, Descriptor Register 7 }
* When S = 0 with D = 1761, 1763, and 1764, a Command fault occurs
unless the CPU is in the Privileged Master mode.
(
4-17
- OZ51-00
When S = a with D = 1761 in the Privileged Master Mode and the type of
the segment descriptor in the DRn is T = 1 or 3, this segment
descriptor type is changed to a or 2, respectively. ~Dn is set to
be self-identifying. No fault occurs and no operation is performed
with the LODn instruction, when the type in the DR!! is not T = 1 or 3.
For D = 0000 through 1757 (octal), the descriptor in DR!! was loaded from
the 'parameter segment and D was the index to the desired descriptor.
When S
=2
The descriptor DRn was loaded from the argument stack using
to the descriptor.
When S
=1
D
as the index
or 3
The descriptor in ORo was loaded from the linkage segment using
index to the descriptor.
D
as the
INSTRUCl'ION S!GMBH'l' IDBNTI'.l'Y RlGS'l'BR - SlGD(IS)
Format: 12 bits
000
1
D
Figure 4-17.
Instruction Segment Identity Register - SEGID(IS) Format
Description:
A 12-bit register that is associated with the instruction segment register
(lSR) in the same manner that a ~D!! register is associated with an
segment descriptor register (DRn). This register points to the source of
the descriptor in the ISR.
Function:
The instruction segment identity register may not be loaded or stored
directly: it is loaded with the identity of the source of the descriptor
when a transfer or OJMB instruction loads the Instruction Segment Register
(lSR). The Sand D field codes used in these registers indicate the origin
of the descriptor. see SEGIDn description.
4-18
DZ51-00
POI HTER RPmSTERS (PR)
(
Format: A collective grouping of registers
Description:
Eight "convenience" logical combinations of registers
Function:
The pointer registers are not physical registers but are convenient terms
used to refer to segment descriptor register (DRn), segment identity
register (SEGIDn), and address register (ARn) utilized as a collective
register.
A 2-bit register that controls the clearing of data stack space and
bypassing the safe store portion o~ an inward ClJMB (IClJMB) instruction.
Bit 18 is the Data Stack Clear Flag (DSCF) and bit 19 is the safe Store
Bypass Flag (SSBF).
Function:
The option register is loaded with the Load Option Register (LDQ)
instruction and stored with the Store Option Register (STO) instruction.
4-19
DZ51-:00
CALBHDAR o.ocK RlGS'l'ER
Format:
(CCR)
52 bits
0 1 2
0 9 0
1111111111111111111111111111111111111
1111111111111111111111111111111111111
1111111111111111111111111111111111111
3
5
Clock Upper
16
7
3
1
Clock Lower
36
Figure 4-19.
calendar Clock Register (CCR) Format
Description:
A 52-bit register that holds a calendar clock with a resolution of one micro
second
Function:
The CCR register provides a means for setting and reading the calendar
clock. The CCR is set by using the SSCR 04 instruction and read by using
the RSCR 04 instruction. (Refer to the individual descriptions of these
instructions in section 8).
,~'\
~
"-
(
'-'/
4-20
DZ51-00
NOTE: '!'BE POLLOWI HG REm S'l'ERS CAB BE
(
~BI)
ONLY I Ii PRIVI I..!IiED IIAS"l'BR MODE.
WORKING SPACE REXiIS'l'ERS (WSRn)
Format:
9 bits each
0
8
0
0
Working Space Number
I
Figure 4-20.
91
Working Space Register (WSRg) Format
Description:
Eight 9-bit registers located in the virtual unit, each of which holds a
working space (WS) number that is used to form a virtual address
Function:
A working space register is referred to by the WSR field of a descriptor.
The LOWS and STWS instructions are used to load and store the working space
registers, respectively. To execute these two instructions, the processor
must be in Privileged Master mode. When the processor is initialized and
cleared, working space register 0 is set to all zeros. The working space
registers provide the means for sharing and isolating working spaces.
SAFE STORE REXiI S'l'BR (SSR)
Format:
72 bits
o
o
1 2
9 0
2 2
2 2
2 3
8 9
Flags
~1 WSR
3 3
1 2
---Ir _9 --_3
Bound
20
Flags
WSN
3
3
9
3
5
Type=1
4
~3-
4
Base
36
Figure 4-21.
safe Store Register (SSR) Format
(
4-21
DZS1-00
Description:
A 72-bit register located in the virtual unit that holds either a Type 1 or
3 standard descriptor that describes the safe store stack of the current
process. Note that the format for a Type 3 descriptor differs in that the
Flags field is truncated at bit 22 to allow the descriptor to contain the
actual working space number (WSN) rather than point to a Working Space
Register (WSR).
Function:
The safe store register describes the safe store stack of the current
process. The safe store register is loaded and stored with the Privileged
Master mode instructions LOSS and STSS. A 2-bit hardware stack control
register (SCR) is associated with the safe store register. The Stack
Control Register (SCR) content determines the size of the safe store frame.
(Refer to SCR below.)
STACK roNnOL Rl!m S'l'ER (SCR)
Format: 2 bits (internal)
Description:
An
internal register that controls the size of the safe store frame
Function:
The SCR is initialized by execution of the Privileged Master mode
instruction LOSS. This register contains the code indicating the size of
the last safe store frame as shown in the table below. (Refer to the
discussion of the safe Store Register (SSR).)
SCR safe Store Stack Size
00
01
11
10
-
16
24
64
80
words
words
words
words
(Bit values are binary.)
4-22
DZ51-00
ARGUIIEN'l' STACK RPm S'l'BR (ASR)
(
Format:
72 bits
o
o
1 2
9 0
Bound
2 2
3 3
1 2
8 9
Flags
20
Type=1
4
WSR
9
3
5
3
Base
36
Figure 4-22.
Evenword
Oddword
Argument Stack Register (ASR) Format
Description:
A 72-bit register that holds a type 1 standard descriptor that describes (or
frames) the argument stack of the current domain of the currently executing
process
Function:
Instructions are provided for loading (Privileged Master mode) and storing
the argument stack register. The argument stack register is .utilized by and
may have its contents changed by the hardware during the execution of a save
Descriptor Register (SDRn) or CLIMB instruction.
When the bound field of
the ASR is loaded, bits 0-6 are forced to zero: if flag-bit 27 = 1 (bound
valid), bits 17-19 are forced to 111. Thus, the size of the argument stack
is effectively limited to 1024 descriptors.
PARAME'l'BR SlGIENT RPm S'l'BR (PSR)
Format:
72 bits
o
o
1 2
2 2
9 0
8 9
Flags
Bound
20
3 3
1 2
WSR
9
3
3
5
Type=1
4
Base
36
Figure 4-23.
Parameter Segment Register
(PSR)
Evenword
Oddword
Format
(
4-23
DZ51-00
Description:
A 72-bit register that holds a type 1 standard descriptor that frames the
parameter segment of the current domain of the currently executing process
Function:
Instructions are provided for loading 1<
tm
3
4
(tm)
and tag designator (td),
3
5
>
<----tag fie1d,---'--->
where:
tm specifies one of four possible modification types: Register (R),
Register Then Indirect (RI), Indirect Then Register (IR), and Indirect
Then Tally (IT).
td specifies the activity for each modification type:
1. When tm = R, RI, or IR, td is called the register designator and
generally specifies the register to be used in indexing.
2. When tm = IT, td is called the tally designator and specifies the
tallying in detail.
The following table shows the valid assembler mnemonics for address
modification and their relationship to the classes R, RI, IR, and IT.
td
00
00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
17
tm=OO
R
tm=Ol
RI
Blank
*
N*
AU*
QU*
N
AU
QU
DU
IC
AL
QL
DL
0
1
2
3
4
5
6
7
IC*
AL*
QL*
0*
1*
2*
3*
4*
5*
6*
7*
tm=ll
IR
tm=lO
IT
*N
*AU
*QU
*DU
*IC
*AL
*QL
*DL
*0
*1
*2
*3
*4
*5
*6
*7
F
5-2
SD
SCR
Cl
I
SC
AD
DI
DIe
1D
IOC
DZ5l-00
"l'ypeS Of
(
Address Modification
The four basic modification types, their mnemonic substitutions as used in the
variable field of the program statement, and their binary forms are as follows:
Modification
Type
Variable
Field
Binary
Forms
3
0
3 3
3
1 2
5
Itm I
R
RI
(
IR
IT
BETA, (R)
BETA, (R)*
BETA,*(R)
BETA, (T)
Example
3
3 3
0
1 2
I 0 0 11
td
I
3
5
1
o 11
3
3 3
3
0
1 2
5
I 0 11 1
0 1
01
3
3 3
3
0
1 2
5
I 111
1 1 1
11
3
3 3
3
0
1 2
5
I1 01 1
0
1 01
BETA,S
BETA, 2*
BETA, *7
BETA,SC
The parentheses enclosing R and T indicate that substitutions should be made by
the user for Rand T as explained under the separate discussions of R, IR, RI,
and IT modification below. Binary equivalents of the substitution are used in
the tIn subfield.
RB'iI S"l'BR
(R )
The processor performs register address modification whenever an R-type
variation is coded. The assembler places binary zeros in both positions of the
tm subfield of the instruction. Accordingly, 1 of 16 variations under R are
performed by the processor, depending upon bit configurations generated by the
assembler, and placed in the designator subfield (td) of the general
instruction. The 16 variations, their mnemonic substitutions used on the
assembler coding sheet, the td field binary forms presented to the processor,
and the effective address Y generated by the processor are indicated below.
5-3
DZ51-00
R modification allows for the use of the instruction address field as the
operand. This is called direct operand address modification, of which there
are two types: Direct Upper (DU) and Direct Lower (DL). With the DU variation,
the address field of the instruction serves as bit positions 0-17 of the
operand and zeros serve as bit positions 18-35 of the operand. With the DL
variation, the address field of the instruction serves as bit positions 18-35
of the operand and zeros serve as bit positions 0-17 of the operand.
IC modification should only be used with an absolute operand. A relative
operand that has IC modification is flagged with a possible relocation error
(R) by the assembler.
Mnemonic
Substitution
Binary
Form
(td field)
Effective
Address
(R)=XO
0
1000
Y-y+C(XO)
=Xl
1
1001
Y=y+C(X1}
=X2
2
1010
Y-y+C(X2}
=X3
3
1011
Y=y+C(X3)
=X4
4
1100
Y=y+C(X4)
=X5
5
1101
Y=y+C(X5)
=X6
6
1110
Y-y+C(X6}
=X7
7
1111
Y=y+C(X7)
=A
AU
0001
Y=y+C(A)
AL
0101
Y=y+C(A)
QU
0010
Y=y+C(Q)
=Q
QL
0110
Y=y+C(Q)
18-35
=IC
IC
0100
Y=y+cOC)
direct upper
DU
0011
Bits 0-17 of operand = y;
Modification
variation
0-17
=A
18-35
=Q
0-17
0-17
18-35
0-17
18-35
bits 18-35 of operand = 0
direct lower
DL
=None
Blank or N
=Any symbolic Any defined
index register symbol 1
0111
0000
Bits 0-17 of operand
= 0;
bits 18-35 of operand
=y
Y=y
1. Symbol must be defined as one of the index registers by using an applicable
pseudo-operation (EQU or BOOL).
5-4
DZ5l-00
The following examples show how R-type modification variations are entered
and how they affect effective addresses.
f
EXAMPLES:
16
EAXO
LDA
1
B,O
Y=B+~
LDA
LOA
=2,DL
C,A!.
Y=C+2
EAQ
LDA
3
M,QU
Y-M+3
1
8
16
Address
(4)
ABC
LDA
-2,IC
Y=ABC-2
(5)
XYZ
LDA
*,DU
operand
(1)
(2)
(3)
(6)
(7 )
(
Effective
Address
8
1
EAX7
LDA
1,7
Y=ABC+1
LDA
2,DL
operand
LOA
B
Y=B
(9)
LDA
B,N
Y-B
(10)
EAX
LDA
ALPHA, 10
C,ALPHA'
2
Y=C+10
~U
=XYZ, operand
=0
18-35
0-17
=O,operand
=2
18-35
ABC
(8)
ALPHA
0-17
Coding examples of R-type modification follow:
0
(R)
=N
ALPHA
LDA
ADRES1,N
is equivalent to
ALPHA LDA
ADRES1
No address modification results; ADRESl is the effective operand.
5-5
DZ5l-00
o (R)
= X!} where n = 0 to 7
ALPHA
ADRES2,5
LOA
X5 contains the value 2.
ADRES2 DEC
12
OCT
7777
OCT
123456765432
ADRES2+2 becomes the effective address and its contents (octal
123456765432) are loaded into the A-register.
A-register
X5
Before
773412315026
000002
After
l23456765432
000002
o (R)
= AU,
ALPHA
AL, QU, QL
LOA
ADRES3,QU
Bits 0-17 of the Q-register contain the value 3.
ADRES3 DEC
10
OCT
12
OCT
14
OCT
16
ADRES3+3 becomes the effective address and its contents (octal 16) are
loaded into the A-register.
A-register
Q-register
Before
123456765432
000003
123456
After
000000000016
000003
123456
5-6
DZ51-00
o (R) = DU,DL
ALPHA
ADRES4,DU
LDA
There is no memory access to obtain modification of ADRES4. The address
represented by the symbol ADRES4 is placed in bits 0-17 of the
A-register; bits 18-35 are filled with zeros.
ADRES4 OCT
10
(assume ADRES4 is at location 001002 octal)
Before
10 0 0 0 0 0 0 0 0 0 1 6
After
10 0 1 0 0 2 0 0 0 0 0 0
A simple program segment, the movement of 50 words from ABC to XYZ, may help
illustrate the power of address modification.
Without Address Modification
1
(
8
START LOXl
LOA
STA
LOA
ASA
ASA
ADLXl
CMPX1
TNC
With Address Modification
8
16
1
=OB17,DU
START LOX1
LOA
STA
ABC
XYZ
=lB17
START+1
START+2
=lBl7
=50Bl7
START+l
ADLXl
CMPXl
TNC
16
O,DU
ABC, 1
XYZ,l
1,DU
50,DU
START+1
JUG: S'1'BR THEN I JmIREC'l' (RI )
Register Then Indirect address modification is a combination in which both
indexing (register modification) and indirect addressing are performed. For
indexing modification under Rl, the mnemonic substitutions for R are the same
as those given under the discussion of register (R) modification with the
exception that DU and DL are invalid for RI usage. For indirect addressing
(I), the processor interprets the contents of the operand address associated
with the original instruction or with an indirect word.
(
5-7
DZ5l-00
Under RI modification, the effective address Y is found by first performing the
specified register modification on the operand address of the instruction; the
result of this R modification under Rl is the address of an indirect word which
is then retrieved. (Refer to Figure 5-1.)
r-".
\"0"/
After the indirect word has been accessed from memory and decoded, the
processor carries out the address modification specified by this indirect
word. If the indirect word specifies Rl, IR, or IT modification (any type
specifying indirection), the indirect sequence is continued. When an indirect
word is found that specifies R modification, the processor performs R
modification, using the register specified by the td field of this
last-encountered indirect word and the address field of the same word, to form
the effective address Y.
.
The variations DU and DL of register modification (R), when used with Register
Then Indirect modification (RI), cause an Illegal Procedure (IPR) fault.
To refer to an indirect word from the instruction itself without including
register modification of the operand address, the "no modification" variation
should be specified; under RI modification, this is indicated by placing only
an asterisk (*) in the tag position.
The following examples illustrate the use of RI modification, including the use
of (R) c N (no register modification). The asterisk appearing in the modifier
subfield is the assembler symbol for I (Indirect). The acidress-subfield,
single-symbol expressions shown are not intended as realistic coding examples,
but to show the relation between operand addresses, indirect addressing, and
register modification.
---~
EXAMPLES:
"-,
Modification
1
(1)
Z
(2 )
Z
(3 )
Effective
Address
(RI )
ycB+2
16
EAA
1
EAXl
STA
ORG
ARG
2
Z,AU*
Z+l
B,l
(R)
EAQ
MPY
3
Z,*
(RI )
ARG
B,QU
(R)
EAX3
EAX5
3
5
Z,*
(RI )
STQ
Z
Type
8
ARG
ORG
ARG
ORG
ZERO
Y=B+3
Y=M
(RI )
B,5*
B+5
C,3*
C+3
M
(RI )
(R)
5-8
DZ51-00
.
...,
Coding examples of RI modification follow:
(
o
(RI)
= N*
ALPHA
LDA
ADRESl,N*
is equivalent to
ALPHA
LDA
ADRESl,*
The indirect word at ADRESI is obtained; if this indirect word
specifies further indirect modification, the process continues
until an indirect word is obtained with (R) modification.
o
(RI) = (Xn)'"
ALPHA
where
n =0
EAX5
EAX2
5
2
LDA
ADRES2,5*
to 7
The indirect word at ADRES2+5 is obtained. If the indirect word at
this location is
LDQ
ADRES3, 2
the effective address is ADRES3+2.
rHDlu:T THBH RGSTBR (rR)
Indirect Then Register address modification is a combination in which both
indirect addressing and indexing (register modification) are performed. IR
modification is not a simple inverse of RI; several important differences
exist.
Under IR modification, the processor first fetches an indirect word from the
memory location specified by the address field y of the machine instruction;
the C(R) of IR are safe stored for use in making the final index modification
to develop the effective address Y.
Next, the address modification, if any, specified by this first indirect word
is examined. If this modification is again IR, another indirect word is
retrieved from storage immediately; and the new C(R) are safe stored, replacing
the previously safe stored C(R). If an IR loop develops, the above process
continues, each new C(R) replacing the previously safe stored C(R), until a
type other than IR is encountered in the sequence.
5-9
DZ5l-00
If the indirect sequence produces an RI indirect word, the R-type modificatioi.
is performed immediately to form another address; but the I of this RI treats
the contents of the address as an indirect word. The chain then continues with
the C(R) of the last IR still safe stored, awaiting final use. At this point
the new indirect word might specify IR-type modification, possibly renewing the
IR loop noted above; or it might initiate an RI loop. In the latter case, when
this loop is broken, the remaining modification type is R or IT.
When either R or IT is encountered, it is treated as type R, where R is the
last safe stored C(R) of an IR modification. At this point the safe stored
C(R} is combined with the y of the indirect word that produced R or IT, and the
effective address Y is developed.
If an indirect modification without register modification is desired, the "no
modification" variation (N) of register modification should be specified in the
instruction. This normally will be entered on coding sheets as *N in the
modifier part of the variable field. (The entry * alone is equivalent to N*
under RI modification and must be used in that way.)
EXAMPLE 1:
(IR) = *N
ALPHA
LDA
ADRES1,*N
The indirect word at ADRESl is obtained.
location is:
AnRESl
LDQ
If the indirect word at this
ADRES2
the effective address is ADRES2
EXAMPLE 2:
IR and then R or IT
(IR) = *(XB)
ALPHA
where B = 0 to 7
EAX5
15
LDA
ADRES1,*5
The indirect word at ADRESl is obtained.
ADRESl
LDQ
ADRES2, (R)
LDQ
ADRES2, (T)
I f the indirect word is:
or
AnRESl
the effective address is ADRES2+15
5-10
DZ51-00
EKAMPLE 3:
(
I R and then
Rl
(IR) = *(Xn)
where n =
o to
EAX5
16
EAX2
17
ALPHA
LDA
ADRES1,*5
ADRES1
LDQ
ADRES2,2*
LOA
ADRES4
7
( in ADRES2+17)
the effective address is ADRES4+16
EXAMPLE 4:
IR and then IR
(IR)
= *(Xn)
where n
=0
EAX5
18
EAX3
19
ALPHA
LOA
ADRES1, *5
ADRESI
LOA
ADRES2,*3
ADRES2 LDA
to 7
ADRES3
the effective address is ADRES3+19
The following examples illustrate the use of IR-type modification, intermixed
with Rand RI types, under the several conditions noted above.
EXAMPLES:
1
(1)
z
Type
Effective
Address
1,DL
Z,*QL
(IR)
Y=M+l
M
(R)
8
16
LDQ
LDA
ARG
Modi! ication
(
5-11
DZ51-00
Modification
1
8
16
ABC
EAX3
EAX5
LDA
2
3
Z,*3
ARG
ORG
ARG
B,5*
B+3
C,IC
(2)
Z
(3)
EAX3
EAX5
EAQ
(4,)
""-
(IR)
(R)
4,
(IR)
ARG
ARG
ARG
B,*5
C,*QU
N,7
(IR)
(IR)
(R)
EAX3
8
9,DL
Z,*DL
{IR}
LOA
Y=C+2
(RI )
LOA
LDQ
Effective
Address
"
5
6
7
Z,*3
EAX7
Z
B
C
Tvoe
Y=M+6
C(A}18-35)=M
Z
(5)
Z
(6)
Z
ARG
ORG
ARG
B,3*
B+8
N,QL
(R)
LOA
LOA
10,DL
Z,*AL
{IR}
ARG
B,AD
(IT)
EAX3
LOA
11
Z,*N
(lR)
ARG
B,3
(R)
{RI }
5-12
..",-~.
Y=B+10
Y-B
DZ51-00
1
(
(7)
Z
B
(8)
Z
B
(9)
X
B
Z
Modification
8
16
EAX5
LDA
12
Z,*N
(IR)
ARG
ARG
B,*5
M,DU
(IR)
(R)
EAX5
LDA
13
Z,*
(RI )
ARG
ARG
B,*5
M,DU
(IR)
(R)
EAX1
LDA
14
X,*
(RI )
ARG
ARG
B,*l
Z,ID
A,lO
(IR)
(IT)
(IT)
TALLY
Type
Effective
Address
Y=M+13
Y=Z+14
IRDIRD' THBN TALLY (IT)
I ndirect Then Tally address modification is a combination in which both
indirect addressing and automatic incrementing/decrementing of fields in the
indirect word are performed as hardware features, thus relieving the user of
these responsibilities. The automatic tallying and other functions of IT
modification allow processing of tabular data in memory, provide a means for
working upon character data, and allow termination on user-selectable numeric
tally conditions. When tally runout occurs, bit 25 in the indicator register
is set. I f an unassigned IT tag is used, an Illegal Procedure (IPR) fault
occurs.
The variations under IT modification are summarized below. The mnemonic
substitution for IT is ('1'): the designator I for indirect addressing in IT is
not represented. (Note that one of the substitutions forTis I.)
(
5-13
DZ51-00
variation
Binary
Mnemonic
Form
Substitution (td Field)
Effect on Processor and Indirect
(Tally) Word for Each Reference
Fault
F
0000
None. A Fault Tag fault is
generated. The indirect word is
not examined.
Character indirect
CI
1000
None. Applies to TALLY, TALLYB.
sequence character
SC
1010
Obtain the operand address from the
tally word: then add 1 to the
character position value in the tag
field and subtract 1 fran the tally
count field; add 1 to the address
field and set the character
position value to zero when the
character position crosses a word
boundary. Applies to TALLY,
TALLYB.
sequence character
reversed
SCR
0101
Subtract 1 from the character
position value in the tag field and
add 1 to the tally count field;
subtract 1 from the address field
and set the character position
value to 3 (TALLYB) or 5 (TALLY)
when the character position crosses
a word boundary. Then obtain the
operand address from the tally
word. Applies to TALLY, TALLYB.
Indirect
I
1001
None. The operand address is the
word to which the tally word
address field refers. Applies to
all tally pseudo-operations.
Increment address,
decrement tally
ID
1110
Obtain the operand address fran
the tally word; add 1 to the
address field and subtract 1 from
the tally count field. Applies to
all tally pseudo-operations.
Decrement address,
increment tally
DI
1100
Subtract 1 from the address
field, add 1 to the tally count
field, and then obtain the operand
address from the tally word.
Applies to all tally
pseudo-operations.
5-14
DZ5l-00
variation
(
Binary
Mnemonic
Form
Substitution (td Field)
Effect on Processor and Indirect
(Tally) Word for Each Reference
Increment address,
decrement tally,
and continue
IOC
1111
Obtain the operand address from the
tally word, add 1 to the address
field, and subtract 1 from the
tally count field. Additional
address modification will be
performed as specif ied by the tag
field. Applies to TALLYC. Results
in IPR fault in ES mcxie.
Decrement address,
increment tally,
and continue
DIC
1101
Subtract 1 from the address field,
add 1 to the tally count field, and
then obtain the operand address
from the tally word. Additional
address modification will be
performed as specif ied by the tag
field. Applies to TALLYC. Results
in IPR fault in FS mcxie.
Add delta
AD
1011
Obtain the operand address from the
tally word, add an increment to the
address field, and subtract 1 from
the tally count field. Applies to
TALLYD.
Subtract delta
SD
0100
Subtract an increment from the
address field, add 1 to the tally
count field, and then obtain the
operand address from the tally
word. Applies to TALLYD.
(
(
5-15
DZS1-00
I ndirect Word Format
The location of the indirect word is specified by the address field (y) of the
instruction or previous indirect word (IDC or DIC). IT modification causes the
indirect word to be fetched and interpreted as specified by the td subfield of the
instruction or previous indirect word that referred to the indirect word.
The format of the indirect word .is shown in Figure 5-l.
1 1
7 8
0
0
y
I
2 3
9 0
Tally
I
Figure 5-1.
I
3
5
Tag
I
Indirect Word Format
where:
y
- address field
Tally - tally field
Tag
(ignored except for tally modification)
- tag field
Depending upon the prior tally designator, the tag field for the indirect word is
used in one of the following ways:
Tag Field
Tally Designators
3
3
3
3
3
1
2
3
4
Ignored
I,DI,ID,F
td
DI C, I DC , I R, RI
CI ,SC,SCR
AD,SD
3
o
o
cf
Delta
where:
tm
- tag modifier
(.~
~.j
5-16
DZ5l-00
(
td
- tag designator
tb
- character size indicator (O=6-bit, 1=9-bit)
cf
- character position field
Delta - delta field (Size of increment)
Variations Under IT Modification
Fault (T) = F variation.
The Fault variation enables the user to force
program transfers to operating system routines or to corrective routines dur~ng
the execution of an address modification sequence by causing a Fault Tag
fault. (This will usually indicate some abnormal condition for which the user
desires protection.)
Character Indirect (T) = CI variation.
The Character Indirect (CI) variation
allows operations on the A register or Q register where repeated reference to a
single character in memory is required. The character size field (tb) of the
indirect word specifies the character size.
For this variation, the effective address is the address field of the CI
indirect word obtained via the tentative operand address of the instruction or
preceding indirect word that specified the Cl variation. The character
positi~n field (cf) of the indirect word is used to specify the character to be
involved in the operation.
(
This variation is similar to the sc variation except that no incrementing or
decrementing of the address, tally, or character position is performed.
EXAMPLES:
6-bit char. addressing
Z
TALLY
B, ,4
1
8
16
LDA
ADDR,Cl
TALLY
ADD, ,3
6-bit char. addressing
ADD, ,3
9-bit char. addressing
(2)
ADDR
or
ADDR
TALLYB
5-17
DZ5l-00
The effective address is ADD. The character in character position 3 is
loaded into the A-register in character position 5 for 6-bit characters or
into position 3 for 9-bit characters. The remainder of the A-register is
loaded with all zero bits.
.
sequence Character (T) = SC variation.
The Sequence Character (SC)
variation is provided for sequential access to 6-bit or 9-bit characters.
The character size field (tb) of the indirect word is used to specify the
character size. Processor instructions that do not allow SC operations are
so indicated in the individual instruction descriptions. The operand
address is obtained from the address field of the indirect word referenced
by the word containing the SC tag.
Characters are operated on in sequence from left to right within the machine
The character position field (cf) of the indirect word is used to
specify the character position to be involved in the operation. The Tally
Runout indicator is set when the tally field of the indirect word reaches
O.
word.
EXAMPLE:
1
A
8
16
LDA
A,SC
TALLY
TABLE,70,4
TABLE BSS
32
6-bit char. addressing
13
in which 70 is the count and 4 designates the character position of the
tally start.
For register loads using the SC variation, a character is· fetched from the
indicated position of the memory location and is written into the lower end
of the register; the remaining bits of the register are set to zero. For
stores under the SC variation, a character is fetched from the lower end of
the register and written into the indicated position in the memory
location; the remaining character positions in the memory location remain
unchanged.
The tally field of the indirect word is used to count the number of times a
reference is made to a character. Each time an SC reference is made to the
indirect word, the tally is decremented by 1, and the character position is
incremented by 1 to specify the next character position. The tally runout
indicator is set when the tally reaches O. When character position 5 (for
6-bit characters) or 3 (for 9-bit characters) is incremented, it is changed
to position 0 and the address field of the indirect word is incremented by
1. All incrementing and decrementing are done after the effective address
has been provided for the current instruction execution. The effect of
successive references using SC modification is shown in the following
examples.
5-18
DZ5l-00
EXAMPLES:
(
1
Z
B
Effective
Address
Character
Position
Reference
8
16
LDA
Z,SC
B
0
1
TALLY
B,80,0
14
B
1
2
B
B+1
5
0
6
7
B+!!
0
6!!+1
BSS
The Tally Runout indicator
is set on the 80th reference.
1
8
16
ADD1
LDA
ADDR,SC
TTF
ADDl
TALLY
ADD,12,3
(6-bit characters)
ADDR
TALLYB ADD, 12,3
(9-bit characters)
ADD
BSS
ADDR
(
or
4
The first effective address is ADD. The character in character position 3
is loaded into the A-register in position 5 (for 6-bit characters) or into
position 3 (for 9-bit characters). The second reference will load ADD
character 4 (if 6-bit) or ADD+l character 0 (if 9-bit), etc. The tally is
decremented from 12 to O. The destination in the A-register does not
change.
Seouence Character Reverse (T) = SCR Variation.
The SCR variation is the
reverse of se. The character position is decremented h¥ 1 and the tally is
incremented by 1 before the indirect word address field and character
position are used as the operand character address. When the character
position attempts to go negative, it is set to the maximum value (3 or 5)
and the address is decremented by 1.
Indirect (T) =I Variation.
The Indirect (I) variation of IT modification
is, in effect, a subset of the ID and DI variations described below in that
all three -- I, ID, and DI - make use of one indirect word in order to
refer to the operand. The I variation is functionally unique, however, in
that the indirect word accessed by an instruction remains unaltered; no
5-19
DZ51-00
incrementing/decrementing of the address field or tallyoccurs. Since the
tag field of the indirect word under I is not interrogated, this word will
always terminate the indirect chain.
/,r-
The following differences in the coding and the effects of *, *N, and I
should be observed:
1. Rl modif ication is coded as R* for all cases, excluding R=N.
For R=N under RI, the modifier subfield can be written as N* or as *
alone, according to preference.
When N* or just * is coded, the assembler generates a machine word
with octal 20 in bit positions 30-35: octal 20 causes the processor to
add 0 to the address field y of the word containing the N* or * and
then to access the indirect word at memory location y.
2. 1R modification is coded as *R for all cases, including R=N.
For R=N under 1R, the modifier subfield must be written as *N.
When *N is coded, the assembler generates octal 60 in bit positions
30-35 of the associated machine word: octal 60 causes the processor to
(1) retrieve the indirect word at the location (y) specified by the
machine word, and (2) effectively safe store zeros (for possible final
index modification of the last indirect word).
3. IT modification is coded using only a variation designator (I, ID, DI,
SC, SCR, a, AD, 50 , F, I DC, or D1 C): that is, no aster isk (*) is
written. Thus, a written IT address modification appears as ALPH,DI:
BETA,AD; etc.
For the variation I under IT, the assembler generates a machine word
with octal 51 in bit positions 30-35: 51 causes the processor to
examine one, and only one, indirect word to be retrieved from memory
to obtain the effective address Y.
EXAMPLE:
1
Z
8
16
Modification
Type
EAX5
LDA
1
Z,I
(IT)
ARG
B,*5
(IR)
Effective
Address
Y=B
The ID variation
Increment Address, Decrement Tally (T) = ID variation.
under IT modification provides automatic (hardware) incrementing or
decrementing of an indirect word that is best used for processing tabular
operands (data located at consecutive memory addresses). The indirect word
always terminates the indirect chain.
5-20
DZ51-00
/' ""
In the ID variation, the effective address is the address field of the
indirect word obtained via the tentative operand address of the instruction
or preceding indirect word, whichever specified the ID variation. Each time
such a reference is made to the indirect word, the address field of the
indirect word is incremented by 1 and the tally portion of the indirect word
is decremented by 1. The incrementing and decrementing are performed after
the effective address is provided for the instruction operation. When the
tally reaches zero, the Tally Runout indicator is set.
EXAMPLES:
Modification
1
Z
B
8
16
Type
LDA
Z,ID
(IT)
TALLY
BSS
B,12
12
word addressing
Effective
Address
B
1
B+l
2
•
The Tally Runout indicator is
set on the 12th reference.
1
8
ADRESl LDA
TTF
(
Reference
B+!!
!!+l
16
ADRES2,ID
ADRESl
ADRES2 TALLY
ADRES3, 10 word addressing
ADRES3 BSS
10
The first effective address is AORES3; the second is ADRES3 plus 1, etc. The
tally is decremented from 10 to zero. The TTF instruction checks the Tally
Runout indicator. If the tally is not zero, transfer is made to ADRESl. If
the tally is zero, processing continues with the instruction following TTF.
Without the TTF instruction, only one effective address is obtained.
Decrement Address, Increment Tally ('1') + DI variation.
The DI variation
under IT modification provides automatic (hardware) incrementing and
decrementing of an indirect word that is best used for processing tabular
operands (data located at consecutive memory addresses). The indirect word
always terminates the indirect chain.
In the DI variation, the effective address is the modified address field (1
less than the value before modification) of the indirect word obtained via
the tentative operand address of the instruction or preceding indirect word,
whichever specified the D1 variation. Each time a DI reference is made to
the indirect word, the address field of the indirect word is decremented by
1 and the tally portion is incremented by l. When the tally is incremented
from 7777 to 0, the tally runout indicator is set. The incrementing and
decrementing are performed prior to providing the effective address for the
current instruction operation.
5-21
DZ5l-00
EXAMPLES:
8
16
LDA
Z,DI
z
TALLY
B,-18
B
BFS
1
.
18
Modification
Type
(IT)
word addressing
ADRESI LDA
TTF
.
ADRES2 TALLY
ADRES3 BFS
16
B-1
1
B-2
2
i-'"
I
:
\'~,./
B-a
•
Modification
8
Reference
•
The Tally Runout indicator
is set on the 18th reference~
there, the 12-bit tally field
in the indirect word overflows
and becomes all zeros.
1
Effective
Address
Type
Effective
Address
Reference
ADRES2,DI
ADRESl
ADRES3,-10 word addressing
10
The first effective address is ADRES3 -1; the second is ADRES3 -2: etc.
tally increases from -10 to O.
The
Increment Address, Decrement Tally, and Continue (T) = IOC variation. The
IOC variation under IT modification functions in a manner similar to the ID
variation except that, in addition to automatic incrementing/decrementing,
it permits the user to continue the indirect chain in obtaining the
instruction operand. Where the ID variation is useful for processing
tabular data, the IOC variation permits processing of scattered data by a
table of indirect pointers. More specifically, the ID portion of this
variation provides the ability to sequentially step through a table and the
C portion (continuation) allows indirection through the tabular items. The
tabular items may be data pointers, subroutine pointers, or .a transfer
vector.
The address and tally fields are used as described under the ID variation.
The tag field uses the set of instruction address modification variations
under the following restrictions: no variation is permitted that requires an
indexing modification in the IOC cycle since the indexing adder is in use by
the tally phase of the operation. Thus, permissible variations are any
allowable form of IT or IRi but if RI or R is used, R must equal N.
(r'~
"
.
\,-,j
5-22
DZ5l-00
EXAMPLES:
(
1
Z
B
Modification
Type
Effective
Address
8
16
LOA
Z,IOC
X
1
TALLYC
ARG
ARG
ARG
B,10,I
Y
Z
2
3
X
Y
Z
Reference
The Tally Runout indicator is set on the 10th reference.
1
8
ADRES1 LOA
TTF
16
32
ADRES2,IOC
ADRESI
ADRES2 TALLYC ADRES3,4,*
ADRES3 ARG
AD1
AD2
ARG
AD3
ARG
ARG
AD4
word addressing and indirect
AD1 is the first effective address, AD2 is the second, AD3 is the third, and
AD4 is the fourth.
(
Decrement Address, Increment Tally, and Continue (T) = DIC variation.
The
DIC variation under IT modification perfonns in much the same way as the DI
variation except that, in addition to automatic decrementing or
incrementing, it pennits the user to continue the indirect chain in
obtaining an instruction operand. The continuation function of DIC operates
in the same manner and under the same restrictions as IOC except that (1) it
increments in the reverse direction, and (2) decrementing/incrementing is
performed prior to obtaining the-effective address from the tally word.
(Refer to the first example under IOC; work from the bottom of the table to
the top.) DIC is especially useful in processing last-in, first-out lists.
SOme examples follow:
1
Z
B
Modification
8
16
LOA
Z,DIC
(IT)
TALLYC
ARG
ARG
ARG
B,-10,I
Z
(IT)
Type
X
Y
Effective
Address
Y
X
Z
Reference
1
2
3
NULL
(
5-23
DZ51-00
Assuming an initial tally of -10, the Tally Runout indicator is set on the
lOth reference; there, the 12-bit tally field in the indirect word overflows
and becomes all zeros.
EXAMPLES:
8
1
ADRESl LDA
TTF
32
16
ADRES2,DIC
ADRESl
ADRES2 TALLYC ADRES3 , -4, *N
AD4,*
ARG
ARG
AD3
AD2,*N
ARG
ADl,*N
ARG
ADRES3 BSS
1
ADI
ARG
ARG
ARG
AD2
AD4
word addressing and indirect
A
B
C
is the first effective address, B is the second, AD3 is the third, and C
is the fourth.
A
Add Delta (T) = AD variation.
The Add Delta (AD) variation is provided
for programmingsi tuations where tabular data to be processed is stored at
equally spaced locations, such as data items, each occupying two or more
consecutive memory addresses. It functions in a manner similar to the ID
variation, but the incrementing (delta) of the address field is selectable
by the user.
Each time such a reference is made to the indirect word, the address field
of the indirect word is increased by delta and the tally portion of the
indirect word is decremented by 1. The addition of delta and decrementing
are done after the effective address is provided for the instruction
operation.
The following examples show the effect of successive references using AD
modification:
Modification
1
78
LDAQ
Z
ETALLY
B
EBSS
16
Z,AD
Type
(IT)
B,20,2
40
The Tally Runout indicator
is set on the 20th reference.
5-24
Effective
Address
Reference
B
1
B+2
B+4
2
3
.
B+2n
•
Jl+l
DZ51-00
1
ADRESl
32
16
78
LDAQ
TTF
ADRES2, AD
ADRESl
.
ADRES2 ET ALLYD ADRES3, 10 , 2
ADRES3 EBSS
20
word addressing with DELTA
The first effective address is ADRES3; the second is ADRES3';.2.
decreases from 10 to O.
The tally
Subtract Delta (T) = SO Variation.
The Subtract Delta (SO) variation is
useful in processing tabular data in a manner similar to the AD variation
except that the table can easily be scanned from back to front using a
programmer-specified increment. The effective address from the indirect
word is decreased by delta and the tally is increased by 1 each time an SO
reference is made to the indirect word. This is done before supplying the
operand address to the current instruction, making the SO variation
analogous to the DI variation.
Address Modification OCtal Codes
Address modification and 2-digit octal codes for each type of modification are
listed in Table 5-1.
Table 5-1.
(
Address Modification Octal Codes
LOW ORDER OCTAL DIGIT
o
1
2
3
4
5
6
7
H
0
N
AU
QU
DU
IC
AL
QL
DL
I
G
H
1
0
1
2
3
4
5
6
7
0
R
2
N*
AU*
QU*
IC*
AL*
QL*
3
0*
1*
2*
4*
5*
6*
7*
4
F
SO
SCR
5
CI
I
SC
AD
DI
DIC
ID
IOC
D
I
6
*N
*AU
*QU
*DU
*IC
*AL
QL
*DL
G
I
T
7
*0
*1
*2
*3
*4
*5
*6
*7
D
E
R
0
C
T
A
L
(,-
3*
5-25
DZ5l-00
Address Modification Flowchart
The process of address modification is illustrated in flowchart form in Figure
5-2. Address register modification is not included in this example.
Foult Rout i "-
Re •• o".er fie,
"0"-. Modi fy
odd,e.. wr th
loved '89. to
obtoln effective
ope,ond odd, •• ,
Add contellh of
,e9i,te' ,pecified
by td to oDerond
odd,.as toa to t
.ftectiye odd' e.,
Y.
Reg. it unci to
_dify oPe,otld
oddr." to obtoin
.ffectlve odd' •••
of indirect wo,d.
G
P.,form inc,ew.nt
in9/dec,ementing.
Get i"di,ect word
ond e.omine reg.
Pe,form other IT
Wodificotionl (I.
ID.Di
.SC.S~.CI.
PD, SO).
Obtain
indirect w.,d.
Obtain eftective
odd,en from
Indirect word.
Figure 5-2.
E.. cdutive
in.truct ion
Address Modification Flowchart
5-26
DZ51-00
\
"-
,
,./
Floatable Code
(
Program statements may be written in floatable code. Such statements may then
be executed from any location in memory without relocation at load time.
Floatable code is created by use of instruction counter (I C) modification in
all references to locations within a program. Thus, to transfer to location
SYM, the following statement can be written:
TRA
SYM-*,IC
or
TRA
SYM,$
The assembler accepts the currency symbol <$> as a valid IC register
designator. The following tag fields in a machine instruction are permitted:
Mnemonic
Octal COde
$
04
$*
24
The assembler computes the difference between the value of the address location
argument of the variable field and the current location as the content of the
address field of the instruction word. The IC is then supplied for
modification. *$ is illegal and will be assembled as *IC.
(
NOTE: The FLOAT pseudo-operation or $ modification does not apply when used
with SYMREF symbols or within the range of a BLOCK pseudo-operation.
Address Modification With Address Registers
Address registers
+
y field, bit 3
16K Offset Range
I256K
field, bit 3 = 1
=0
I
Coding Examples:
1. LDQ
4,N,2
Effective Address
2. LDQ
= 4 + C(AR2)0-17
-4,N,2
Effective Address
= -4
+
bits 0-17 of C(AR2)
MULTlWORD ADDRESS MODIFlCATlOH
The general format of a multiword instruction is shown in Figure 5-5.
Memory
Loc. 0
o
2 2
8 9
1 1
o
7 8
variable Field
OP CODE
I
3
5
NFl
Instruction
Word
1
Operand Descriptor 1 or Indirect Word
Descriptor 1
2
Operand Descriptor 2 or Indirect Word
Descriptor 2
3
Operand Descriptor 3 or Indirect Word
Descriptor 3
Figure 5-5.
Mu1tiword Instruction Format
5-30
DZ5l-00
where:
(
Variable Field -
Contains additional information concerning the operation
to be performed, depending on the particular instruction.
When descriptors 2 and 3 are present, most instructions
provide a corresponding MF2 (bits 11-17) and MF3 (bits
2-8) within the variable field to describe the address
modification to be performed on these operands when
present. Exceptions to this are the CMPCI', MVT, SCD, SCDR,
SCM, SCMR, TCT, and TCTR instructions.
OP CODE
-
The 10-bit operation code field; octal representation
consists of three octal digits corresponding to bit
positions 18-26 and a 1 for bit position 27.
I
-
The program interrupt inhibit bit
NFl
-
Modification field 1 (NFl) describes address modification
that is to be performed for descriptor 1.
MULTItDU> MODIFICATION FIELD
Each modification field (NF) contained in a mu1tiword instruction is a 7-bit
field specifying address modification to be performed on the operand
descriptors. The modification field is interpreted as follows:
5 through 8 < - bits (MF3)
2
3
4
11
12
13
14 through 17
29
30
31
32 through 35 < - bits (NFl)
I I I I
AR
RL
ID
<-
rum
bits (MF2)
1<--
""--~1~-1=-"""-~1""""--------4~<--
AR -
subf ield
number of bits
Address Register Specifier
0- No address register used.
1- Bits 0-2 of the operand descriptor address field specify the
address register to be used in computing the effective address of
the operand. Bits 0 - 2 also specify the operand descriptor
register that defines the segment containing the operand.
(
5-31
DZ5l-00
RL -
Register or Length
0- Operand length is specified in the N field (bits 32-35) of the
operand descriptor.
1- Length of operand is contained in the register that is specified by
code in the N field (bits 32-35) of the operand descriptor, in the
machine format of REG (the coding format is different).
ID -
Indirect Operand Des=riptor
0- The operand descriptor follows the instruction word in its
. sequential memory location.
1- The operand descriptor location contains an indirect word that
points to the operand descriptor. Only one level of indirection is
allowed.
REG
- Address modification register selection for R-type modification of
the operand descriptor address field. The REG codes are
approximately the same as the single-word modifications. In
addition, for indirect string length specification (RL = 1), the N
field codes are similar to the REG field. A comparison of these
codes is shown in Table 5-2.
5-32
DZ5l-00
('\
Table 5-2.
(
Register Codes
REG In
Indirect
Word When
(2)
ID = 1
Bits 32-35
Of N When
RL = 1
td Field
Of
Octal
Code
REG
In MF
0000
None
None
0001
AU
AU
AU
AU
0010
QU
QU
QU
QU
0011
DU
0100
IC
IC
0101
A (3)
0110
0111
(l)
I
IPR Fault
IPR Fault
Tag
None
IPR Fault
DU
IPR Fault
IC
A (3)
A (3)
AL
Q (3)
Q (3)
Q (3)
QL
IPR Fault
IPR Fault
IPR Fault
DL
1000
XO
XO
XO
XO
1001
Xl
Xl
Xl
Xl
1010
X2
X2
X2
X2
1011
X3
X3
X3
X3
1100
X4
X4
X4
X4
1101
X5
X5
X5
X5
1110
X6
X6
X6
X6
1111
X7
X7
X7
X7
(1)
Register content is interpreted as a character or bit index. For an
alphanumeric descriptor, this index is the number of 9-bit, 6-bit,
or 4-bit characters, depending upon the data type specified in the
descriptor. For a numeric descriptor, it is the number of 9-bit or
4-bit characters, also dependent upon the data type specified. For a
bit descriptor, it is the number of bits.
(2)
Register contents are interpreted as a word index.
(
5-33
----.-.---.--~-~~--~~~----
DZ51-00
Table 5-2 cont. Register Codes
(3)
The A- and Q-registers provide for indexing by a number greater than
2**18-1. When the A or Q register is specified, the number of
right-justified bits for indexing depends on the type of unit
reference specified in the operand referring to the A- or
Q-register, as follows:
~.
j"
18 bits for full';'word (36-bit) operations
21 bits for 9-bit and 6-bit character operations
22 bits for 4-bit character operations
24 bits for bit operations
All addressing is modulo addressing. For example, when software desires to
index backwards by N words, it indexes forward by 2**l8-N words. This same
method is also used in character and bit indexing.
No. of UnitslWord
Unit
No. to Effectively yield -N
Word
1
2**18 - N
9-bit
4
4 * 2**18 - N
(2**20 - N)
4-bit
8
8 * 2**18 - N
(2**21 - N)
6-bit
6
6 * 2**18 - N
1 bit
36
36 * 2**18 - N
'\
For I-bit and 6-bit, 4-bit, and 9-bit characters, A and Q can be
respectively loaded with 36,DU; 6,DU: 8,DU; or 4,DU: and N can then be
subtracted.
The index register designations may be specified by a symbol defined by the user
to have a value in the octal range of 0, 1, ••• ,7 (or 10, 11, ••• ,17 when the RL
usage is in a descriptor that does not immediately follow the multiword
instruction - an indirect descriptor).
Example:
1 .
8
16
XA
BOOL
17
(0,1),(0,1)
MLR
ADSC9 A,O,XA
ADSC9 B,O,XA
is used to specify a move of the number of characters specified by the current
value of index register 7.
5-34
DZ51-00
Similarly,
(
-
1
LA
8
16
MLR
ARG
ADSC9
<0,1,1),(0,1)
LA
B,O,XA
ADSC9
A,O,XA
provides for the sending address of the move to be specified indirectly in the
word labeled LA.
As a precautionary measure, all index register symbols should be defined with
octal values in the range 10, 11, ••• ,17, since the assembler uses only the
low-order 3 bits in all contexts except the indirect descriptor where the symbol
cannot be identified from context as an index register designation.
The content of the IC is always interpreted as a word address when used in
address modification. During the entire execution of a multiword instruction,
the IC points to the instruction word. Thus, if Ie address modification is
involved with a descriptor word, the instruction word address is used.
Specifying DU or DL type address modification in the REG field of an indirect
operand descriptor is illegal and causes an IPR fault.
(
DU address modification is legal for MF2 of the SCO, SCOR, SCM, and SCMR
instructions; for all other instructions, an IPR fault occurs.
Operand Descriptors
The operand descriptors describe the data to be used in the operation and provide
the basic address for obtaining the .data from memory. A unique operand descriptor
format is required for each of the three data types: bit string, alphanumeric,
and numeric. The operand descriptor machine formats are as shown in Figures 5-6,
5-7, and 5-8.
BIT STRI HG OPERAND D!SCRIPl'OR
111 2
000
023
y
Figure 5-6.
2 2
3
N
Bit String Operand Descriptor Format
5-35
DZ5l-00
Coding format for the bit string descriptor, BDSC, is:
BDSC - Bi t descriptor
1
"\
8
16
BDSC
LOCSYM,N,c,b,AM
ALPJWfDMBRIC OPBIWID DESClUPl'ORS
1 1
7 8
000
023
2 2 222
0 1 234
y
3
N
Figure 5-7.
Alphanumeric Operand Descriptor Format
Goding formats for the alphanumeric descriptors are:
ADSC9 - ASCII alphanumeric descriptor
1
8
16
ADSC9
LOCSYM, CN , N,AM
ADSC9 sets the TA field for 9-bit ASCII characters.
ADSC6 - Bel alphanumeric descriptor
1
8
16
ADSC6
LOCSYM, CN ,N ,AM
ADSC6 sets the TA field for 6-bit Bel characters.
ADSC4 - Packed decimal alphanumeric descriptor
1
8
ADSC4
16
LOCSYM, CN, N,AM
ADSC4 sets the TA field for 4-bit packed decimal characters.
(
\
5-36
DZ51-00
/"
".....
I
-/
-~
HUMBRIC OPERAHD DESCRIPTORS
1 1 2 2 2 2 2
000
2 3
3
y
Figure 5-S.
Numeric Operand Descriptor Format
Coding formats for the numeric descriptors are:
NDSC9 - ASClI numeric descriptor
1
8
16
NDSC9
LOCSYM,CN,N,S,SF,AM
NDSC9 sets the TN field for 9-bit ASCII characters.
NDSC4 - Packed decimal numeric descriptor
1
(
B
16
NDSC4
LOCSYM,CN,N,S,SF,AM
NOSC4 sets the TN field for 4-bit packed decimal characters.
The legend for the machine and coding formats of the descriptors is as follows:
y
=
starting data word address
18 bits (0-17) if address register not specified in MY; 15 bits (3-17)
if address register specified in MY, with bit 3 extended;
15 bits (3-17) if address register specified in NF, with bit 3 extended
(i.e., if bit 3 is zero, bits 0-2 are also considered to be zero; if bit
3 is 1, bits 0-2 are also considered to be 1s).
c
=
starting character position within a word of 9-bit characters.
Code
. Char.
00
01
10
11
0
1
2
3
(
5-37
DZ51-00
b
=
starting bit position within a 9-bit character.
Code
Bit
Code
Bit
0000
0001
0010
0011
0100
0
1
0101
0110
0111
1000
5
2
3
All other combinations of
these 4 bits are illegal
codes and will cause an I PR
fault.
6
7
8
=
either the number of characters or bits in the data string if RL = a in
MF: or a 4-bit code (bits 32-35) that specifies a register (see Table
5-2) that contains the number of characters or bits if RL = 1 in MF
CN
=
starting character number within the data word specified by the starting
data word address. Legal codes for the CN depends on the data type as
shown below. Coding entry is by the character shown under CN
Character.
Data
CN
Legal
9-bit
a
1
2
3
000
010
100
110
6-bit
a
1
2
3
4
5
000
001
010
all
100
101
a
1
2
3
000
001
010
all
100
101
110
111
4-bit
Character
4
5
6
7
TA
=
Codes
Illegal
Codes
001
all
101
111
110
III
/
00
01
10
11
Data
~
9-bit
6-bit
4-bit
Illegal - causes IPR fault
5-38
...
"
Address Register Number
(if bit 29 specifies address register
register modification)
Address Register Modification
Specifier
Figure 5-9.
I ndirect Word Format
The AR and REG fields are identical in function to the corresponding modification
fields in the instruction word, except that the register content specified by the
REG field of an indirect word is interpreted as word index only.
Indirect words can be generated with the ARG pseudo-operation as follows:
1
8
16
ARG
LOCSYM, RM, AM
where:
LOCSYM - address
RM - register modification
AM - address register modification
for example:
1
8
16
ARG
DFPRSS, ,4
/--',
~~-//
5-40
DZ51-00
OPERAND DESCRIPTOR ADDRESS PREPARATION
(
A flowchart of the operations involved in operand descriptor address preparation
is shown in Figure 5-10. The chart depicts the address preparation for operand
descriptor 1 of a multiword instruction as described by modification field 1
(MFl). A similar type address preparation would be carried out for each operand
descriptor as specified by its MF code. A detailed description of the flowchart
follows:
1. The multiword
in~truction
is obtained from memory.
2. The indirect' (ID) bit of NFl is queried to determine if the descriptor for
operand 1 is present or is an indirect word.
3. This step is reached only if an indirect word was in the operand descriptor
location. Address modification for the indirect word is now performed. If
the AR bit of the indirect word is 1, address register modification step 4
is performed.
4. The y field of the indirect word is added to the contents of the specified
address register.
5. A check is now made to determine if the REG field of the indirect word
specifies that a register type modification be performed.
6. The indirect address as modified by the address register is now modified by
the contents of the specified register, producing the effective address of
the operand descriptor.
7. The operand descriptor is obtained from the location determined by the
generated effective address in item 6.
8. Modification of the operand descriptor address begins. This step is reached
directly from 2 if no indirection is involved. The AR bit of NFl is checked
to determine if address register modification is specified.
9. Address register modification is performed on the operand descriptor as
described under "Address Modification with Address Registers" above. The
character and bit positions of the specified address register are used in
one of two ways depending upon the type of operand descriptor (i.e.,
whether the type is a bit string descriptor or a numeric or alphanumeric
descriptor).
10. The REG field of MFI is checked for a legal code. If DU is specified in the
REG field of NF2 in one of the four multiword instructions (SCO, SCDR, SCM,
or SCMR) for which DU is legal, the CN field is ignored and the character
or characters are arranged within the 18 bits of the word address portion
of the operand descriptor.
11. The count contained in the register specified by the REG field code is
appropriately converted and added to the operand address.
12. The operand is retrieved from the calculated effective address location.
(
5-41
~
DZSl-OO
Fetch
Instruction
fran
~r)'
No
Ves
Ves
Ves
Mod if)' 'I of
Operand
Mod i f,/ '/ of
Indi rect Word
wi th AR
Descriptor
by AR
No
No
Modify '/ of
Modi f,/ )' of
Indi rect Word
wi th REC
Operand
Descriptor
wi th REC
Fetch Oper.
Fetch
Operand fran
Descriptor
fr an Memo r )'
Memor)'
@
Figure 5-10.
Flowchart For Operand Descriptor Address Preparation
i
\~
5-42
DZ5l-00
Operand descriptor address preparation is illustrated in the flowchart of Figure
5-10. Procedures for the preparation of bit string addresses and
alphanumeric/numeric addresses follow.
Bit String Address Preparation
o0
2 3
0
0
1 1 122
3:
1<
y, c, and b fields
of descriptor with bit
3 of y extended
y
+
1 1 122
0
0
7 8
9 0
3
I I
WORD
I
contents of address
CHAR2
BIT 4 register specified by
..L.-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _18
:;.;::;..o.'----=....._ _--.... bits 0, 1, 2, of Y
1
yields
1 1 1 2
7 8 9 0
0
0
I
~
y
B
181
...
2
3
21
modified descriptor
I address
41
where:
Y
= WORD
c
= CHAR + c
+ Y
B = BIT + b
l. If (BIT + b) exceeds 8, a carry is generated to character position C and B
= (BIT + b) -9:
BIT
b
BIT
+
b
=
7
= 5
= 12,
carry 1 to C and B = 12 -9
=3
2. If (CHAR + c + carry from B) exceeds 3, a carry is generated to the word
address and C = (CHAR + c + carry from B) -4:
CHAR
=
2
c = 3
carry + 1
= 6, carry 1 to word address and
C = 6 -4 = 2
(
5-43
DZ51-00
First the data type designator (TA for alphanumeric, TN for numeric) is checked to
determine the character size. If the data is in 9-bit characters, then the
descriptor address and CN fields can be added directly to the address register
contents as follows:
000 0
(-"
'
\~
2
1 1
1
7 8
9 0
y al1d CN fields of the
numeric or alphanumeric
descriptor, bit 3
extended
y
+
o
111
7 8
9
contents of WORD " CHAR
positions of address
register designated by
bits 0, 1, 2 of Y
WORD
yields
o
1 1
7 8
WORD
+
Y
1
9
modified character
address
Bits 20-23 of the address register are ignored. CHAR is added to bits 18 and 19
of CN. Bit 20 of the descriptor is zero and is not used. If CHAR + CN is
greater than 3, a carry is generated to WORD + Y and CHAR + CN = (CHAR + CN)
-4.
If the data is in 4- or 6-bit characters, the 9-bit character representation
contained in the CHAR and BIT portions of the specified address register is
interpreted to determine the corresponding 4- or 6-bit character position
within the memory word. Translation to a 4-bit character location can be
accomplished as follows:
C = 2 (CHAR)
[(BIT
+
If CHAR
BIT
= 7,
then
1
+
= 3 and
C = 2(3) +
If CHAR
= 3 and
then C = 2(3)
=7
BIT
+
4)/9 truncated ]
0
= 4,
=6
I,:
\\_- ../
5-44
DZ5l-00
"
Translation to a 6-bit character location can be accomplished as follows:
9 (CHAR)
(
C
=
+
BIT
(truncated)
6
= 3 and BIT = 7,
If CHAR
then C
=
9 (3) + 7
6
=5
The remainder of 4 which represents the bit position within character position
5 is ignored. This means forcing the address register to point to the next
lower character boundary.
The address modification can now take place.
000 0
1 1
2
7 B
y and CN fields of the
numeric or alphanumeric
descriptor, bit 3 extended
y
+
o
1 1
2
1 1
2
WORD
contents of WORD position
of address register indicated by bits 0,1,2 of y
CAR is the char. location translated from
CHAR and BIT of address
register
yields
o
WORD + Y
For 4-bit character mode, if CN + CAR is greater than 7, a carry is generated
to WORD + Y and CN + CAR = (CN + CAR) -B.
For 6-bit character mode, a carry is generated to WORD + Y when CN + CAR is
greater than 5 and eN + CAR = (CN + CAR) -6.
In the next step of operand descriptor address preparation, as indicated in
item 10 in the flowchart of Figure 5-10, the REG field is checked for a legal
code. If DU is specified in the REG field of MF2 in one of the four multiword
instructions (SCO, SCDR, SCM, or SCMR) for which DU is legal, the CN field is
ignored and the character or characters are arranged within the lB bits of the
word address portion of the operand descriptor as follows:
(
5-45
--""'·'---'"'"-_'"·0-
DZ5l-00
Operand descriptor word address field (y)
o0
o
Character type (TA)
1
7
9-bit characters
CHAR 1
CHAR 0
o
0 0
6-bit characters
ignored
CHAR 1
o0
1
7
1 1
0 0
0 0
1
4-bit characters
ignored
Where only one character is involved (SCM, SCMR), only character 0 is used.
In step 11, in the flowchart of Figure 5-10, the count contained in the
register specified by the REG field code is appropriately converted and added
to the operand address. The count conversion required depends upon the type of
data.
Bit Operations.
The bit count contained in the register is effectively
divided by 36 to give a word count (WO) with a bit remainder (BR). Dividing
the bit remainder by 9 gives a character count with a bit remainder. Thus
the original bit count (BC) is converted to a word count, 9-bit character
count (ee) and bit remainder, and is in proper form to add to the bit
operand address. An example of the effective conversion is shown below:
bit count from register/36
BR/9
8, BIT = 8 is assumed.
Every specification of an index register (Xn) is interpreted as specifying a
36-bit GXn. An AL/QL specification in the register modification (R modification,
REG modification, N when RL = 1) specifies the 36-bit A/Q registers. Any AU/QU
specification results in an IPR fault. When GXn is used in the R modification of
a basic instruction (single-word instruction), bits 2 through 35 are treated as a
word address.
When GX/A/Q is used in the REG modification of a multiword instruction, bits 0
through 35 are treated as the number of characters specified by the bit number in
the data descriptor.
(
Because effective address generation in ES mode involves sign extension, an
instruction such as LOA LOCSYM causes a Bound fault if LOCSYM is greater than or
equal to l28K words, regardless of the instruction segment bound.
5-51
DZ51-00
EXAMPLES:
Effective
Address
1
8
16
EAX2
AWDX
STZ
2
1,2,3
B,2,3
(X2=2)
AR3 = 31010
Y = B+5
(2)
EAX3
AWDX
LDA
1
2,3,1
B, ,1
(X3=1)
AR1=31010
Y=B+3
(3)
AWDX
EAX4
STA
4,,3
B
1,4,3
AR3=41010
X4= address of B
Y=B+5
(4)
EAX4
AWDX
STA
B
0,4,2
2,,2
AR2= address of B
Y=B+2
(1)
rag Field Modification
In a basic instruction (single-word instruction), a tag field modification is
performed after the AR modification. The tag field format follows:
Instruction - > 30 31 32
35
bi ts
""'1=-tm-----r""1----tdOO::O---~...,.
tag field
The interpretation of a tag field and the accompanying modification method are
the same as in the NS mode except that the address modification by the register
A/Q/GXn/IC is altered as illustrated below. This applies to generation of the
following:
an operand address in R modification
(tm
= 00)
an indirect word address in RI modification
(tm
= 01)
an operand address in IR modification (tm = 10)
The following should be noted with AlQ/GXn modification:
1. EA (effective address) may be represented as Y.
2. The
GXn
specification code is identical to the XB specification code •.
3. The AlQ specification code is identical to the AL/QL specification code.
4.
An
AU/QU specification results in an IPR fault.
".---
~'"
(~~
5-52
DZ5l-00
EXAMPLES:
(
1
Effective
Address
8
16
EAX2
LOA
1
B,2
Y=B+1
LDQ
LOA
=3,DL
B,QL
Y=B+3
ARG
ARG
ORG
ARG
ORG
B
A,2*
A+5
B,5*
B+1
R-Type
(1)
(2)
RI-Type
Z
A"
.
(1)
(2)
(3)
EAX2
LOA
1
Z,2*
Y=B+1
EAX1
STQ
0
Z,l*
Y=B
EAX2
STA
3
Z,2*
Y=A+5
8
16
Effective
Address
LDQ
LDA
3,DL
Z,*QL
Y=B+4
ORG
B+1
EAX4
EAX5
STA
3
6
C,*4
ARG
ORG
B,*5
Z+3
IR-Type
1
(1)
Z
(2)
C
B
Y=Z+9
5-53
DZ51-00
Effective
Address
16
8
1
---,\
(3)
x
EAXl
3
LDQ
X,*l
ORG
B+5
/
Y=B+8
When IC modification is specified, effective address development is as follows:
33 34
0
AR
39
341 B21 BITJ
Word Value
I
+ y
36
•
+
16 bits
/
\
0
00------
0
I
IC
=
.
0
EA (y)
17
•
lsi
•
•
•
•
33 34
I
Effective Address
carry ignored
•
341 B21
36
•
•
39
BI\I
'\
,,--/j
The contents of the instruction counter extended on the left with 16 bits
zero-filled is added to the contents of AR + y.
EXAMPLFS:
1
8
Effective
Address
16
I C added to AR
(1 )
AWDX
AWDX
AWDX
TRA
0,QL,3
1,QL,4
2,QL,2
TEST
TEST
0,$,4
0,$,2
Y=IC+AR3
Y=IC+AR4
Y=IC+AR2
AWDX
LDA
1,AL,2
2,$,2
Y=IC+AR2
SZN
TZE
TN!
(2)
5-54
DZ51-00
When DU/DL modification is specified, effective address modification interprets
the operand data as follows:
(
For DU
17 18
0
AR+y(16-33)
1
18
35
I00------------1~ I
For DL
o1
10 __01
~
35
2
~
AR+y
________________________________________
I
bit
positions
~~<-AR+y
33
0
EXAMPLES:
1
8
Effective
Address
16
Compare .GX1 to AR3
(1)
(
EAX1
A
CMPX
1,DL,3
GX1 = address of A
Load AU with contents of AR2
(2)
EAX3
B
AWDX
LDA
0,3,2
0,DU,2
AR2=address of B
Operand Descriptor Modification
When REG modification is specified in the MF field of a multiword instruction,
it is processed as follows.
When AlQ/GXn is specified
The 36 bits of A/Q/GXn are used as the character number which is the
character address.
An AU/QU specification results in an IPR fault.
5-55
DZ51-00
EXAMPLES:
1
(1)
This moves the string "SOURCE" to the first six characters
of TO. The contents of X3 act as an offset into the source text.
LDX3
=ll,DL
MLR
ADSC9
( , , , 3 ) , , 040
FROM,1,6
TO,0,6
ASCI I
BSS
9, THIS I S THE SOURCE TEXT
2
ADSC9
FROM
TO
(2)
Effective
Address
16
S
The string "LE " is moved to XB, starting at the third
character of XB. The Q register can be used in the same way.
LDA
•
XA
XB
=4,DL
MLR
ADSC9
ADSC9
(",A),(",,),040
XA,0,3
XB,2,3
ASCII
5,SAMPLE TEXT TO MOVE
BSS
3
When IC is specified in the REG modification, it is treated as an
lS-bit word address.
EXAMPLES:
1
S
Effective
Address
16
The string "HIS IS" is moved to Y, beginning with the
first character.
x
Y
EAX3
Y
AWDX
0,3,2
MLR
ADSC9
ADSC9
ASCII
(",IC),(1",),040
3,1,6
0,0,6,2
4, THIS IS THE TEXT
BSS
2
AR2=address of Y
5-56
DZ51-00
When OU/OL is specified
OL - An IPR fault occurs.
(
OU - Permitted only in the SCO, SCDR, SCM, and SCMR
instructions.
The effective address (EA(y» generated by the operand
descriptor is treated as follows.
Bits 16 through 33 of the effective address (EA(y» are
interpreted as character data according to its data format (TA
or TN field of the descriptor).
o
15 16
\\\\\\\\\\\\\\\\\\\\\\\
\\\\\\\\\\\\\\\\\\\\\\\
\\\\\\\\\\\\\\\\\\\\\16
o
\\\\\\\\\\\\\\\\\\\\\16
o
(
33 34 35
CharO
CharI
9
15 16
\\\\\\\\\\\\\\\\\\\\\\\
\\\\\\\\\\\\\\\\\\\\\\\
24 25
21 22
CharO
6
27 28
\\\\\
\\\\\
9 \\\\\
35
\\\\\\\\\\\\\
CharI \\\\\\\\\\\\\
6 \\\\\\\\\\\\\
15 16 17 20 21 24 25
4
6-bit
characters
35
\\\\\\\\\\\\\\\\\\\\\\\ \\
\\\\\\\\\\\\\\\\
\\\\\\\\\\\\\\\\\\\\\\\ \\ CharO CharI \\\\\\\\\\\\\\\\
\\\\\\\\\\\\\\\\\\\\\16 \1
9-bit
characters
4 \\\\\\\\\\\\\\11
4-bit
character
For the SCM or SCMR instructions, only CHARO indicated in the diagrams is
used. The shaded portions are ignored during effective address
generation.
ADDRESS DEVELOPMENT
virtual Memory Addressing
Virtual memory provides the processor with a virtual memory capability, consisting
of a directly addressable virtual space of 2**43 bytes and the mechanisms for
translating this virtual memory address to a real memory address. Memory paging is
an integral part of the translation process for this conversion. An absolute
addressing mode that allows bypassing the translation process is also provided.
When the processor is operating in the absolute addressing mode, the virtual memory
address and the real memory address are the same.
5-57
DZ5l-00
To provide for virtual memory management, assignment, and control, the 2**43 byte
virtual memory space is divided into smaller units called working spaces, and
segments.
o Working Spaces (WS)
The 2**43 bytes of virtual memory space are divided into 512 2**34-byte
working spaces (WS). WS numbers used to generate a particular virtual memory
address are obtained from one of the eight WS registers or a segment
descriptor register (DRn). The WS number is represented in a segment
descriptor register either by the content ofa specified WSR or by a 9-bit
WSN field.
o Segments
A segment is part of a working space and may be as small as one byte or as
large as 2**32 bytes for an extended segment. (GCOS disallows the use of
contiguous working spaces for a single segment.) Thus, unlike the fixed size
of a WS, a segment size is variable. Segments are described by a 72-bit
descriptor.
When a virtual address is generated, the descriptor (more commonly referred
to as the segment descriptor) is contained in a register such as the
instruction segment register (ISR).
For operands, the descriptor may be
contained in other segment descriptor registers. The area of virtual memory
constituting a segment is "framed" by the segment descriptor by defining a
base value relative to the base of the WS and a bound value relative to the
base of the segment. _
Virtual memory affects memory address development for both instructions and
operands in Privileged Master, Master and Slave modes of operation.
OPERAHD ADDRESS PROCEDURE
In the first phase of address generation, the effective address (EA) of the operand
is generated as previously described for effective address generation. The EA is
that address obtained after all register modification and indirect processing has
taken place. It is an 18-bit word, 20-bit byte, or 24-bit bit address in the NS
mode, and a 3D-bit word, 32-bit byte, or 36-bit bit address in the ES mode.
After the EA has been formed, the processor hardware forms the virtual memory
address of the operand using the base, bound, and WS values from 1 of .9 segment
descriptors. If bit 29 of the instruction for which the operand address is being
prepared is zero, then the operand resides in the instruction segment and the base,
bound, and WS from the instruction segment register (ISR) are used to form the
virtual address of the operand: if bit 29 of the instruction is 1, then descriptor
register B (DRB) specified by bits 0, 1, and 2 of the address field of the
instruction is used. Note that specifying DRB constitutes specifying ~ and vice
versa.
5-58
DZ51-DD
When indirect EA development is involved, the following rules apply:
a. When ORn and ARg are involved (instruction bit 29 = 1), ARg is applied only
to the first address in a chain of indirect addresses. However, the base,
bound, and WS from ORn are applied to each memory reference in the indirect
chain.
(
b. When no DRn/ARn is specified (instruction bit 29 = 0), the base, bound, and
WS of the ISR are applied to each memory reference in an indirect chain.
c. A word in an indirect chain cannot specify a ORne
d.
I
XEC or XED1 instruction does not constitute an indirect chain; therefore,
the instruction executed may specify a different ORn than the XEC/XED
instruction, or no ORn. If the instruction executed by the XEC/XED does not
specify a ORn, the base, bound, and WS from the ISR are used to form the
virtual address of the operand.
An
HSTRUC'lIOH ADDRESS PROCBDURE
Virtual addresses for instructions are always formed using the value in the
instruction counter (Ie) and the base, bound, and WS from the ISR.
Virtual Address Generation Per HS Mcxle
For all memory accesses, a virtual address must be generated. The mechanics of
generating the virtual memory address depend on whether the involved segment
descriptor is a standard descriptor or a super descriptor. Thus, the procedure
described below for generating the operand virtual address with a standard
descriptor also applies to virtual address generation for accessing the
instruction, argument, parameter, and linkage segments (the registers holding the
descriptors that define these segments may only contain standard descriptors).
1. XED executes in NS mode only.
5-59
-------------,,-
---~~-
DZ51-00
STAJlDARD D&SCJUP.rOR HS MODE
The method of forming an operand virtual address with a standard descriptor is
shown in Figure 5-11. If instruction bit 29=0, the ISR is used~ if bit 29=1, then
DRn is used.
o
17 18 20 23
IO~ ~ ~Ol, ______
EF~~~
181 B21 BI~I
r -______ ,I.
+
----->------,-----
>--(-)
•
Bound Fault If
carry Is
Generated
<-
·
o
33 34 35
SEX;MENT BASE
FROM DRn OR I SR
·
341 B2
··
·•
··
·
·•
···
·
Bits 0 and 1
0 2
saved to Make
<-WSN Access
2
Control
Cleck
0
33 34 35
EA +
BASE
341 B2
··
··
·•
··
··
··
·· ··
·.OR.·
· ·
· ·
678
7 2
··
8·9
0
EFFECTIVE
WORD ADDRESS
WORKING WI THI N WORK! NG SPACE B BIT
SPACE 9
32 2
4
where:
·•
··
··
•
··
•
···
•
·•
1
.
Bound Cleek
I
If EA(O-19) > Bound
then Bound Fault
Occurs
<-Relative Virtual
Address
·
·
··
·
··
··
40 42 ·43 46·
WSN
··
·
.
Resulting
<-Virtual Address
B - page byte
WSN - working space number
Figure 5-11.
Virtual Address Generation Using Standard Descriptor (NS Mode)
5-60
DZ51-00
The bound check is applied to the effective address at the byte level. The bound
check is shown for byte or bit instructions; the checks for single-word or
multiword instructions require inclusion of the base in upper- and lower-bound
algori thIns.
If a carry is generated when the EA is added to the base, an out-of-bound situation
exists, resulting in a Bound fault.
The effective WSN is formed by ORing the low-order two bits of the working space
number with bits 0 and 1 of the sum of EA + BASE.
The bit address from the EA becomes the bit address of the virtual address.
SUPER DESClUPl'OR RS MODE
The method of forming an operand virtual address with a super descriptor is shown
in Figure 5-12.
(
5-61
DZ51-00
Io~ ~ ~ -_-=_=_=
o
17 19 20 23 0
_"="0T'1,~EFFECT~AD~D~RES=I~~E~--1";"8-r1~B;"'2':;:I~BI~~~1
+
·.0
1- -
. .
I
o
Fault I f
DR Bound
33. 35.
.LOCATION FROM DRn
B21
I
Bound
19 20
33
·
35.
•
<--~I____~
___
T_IO_N__
+_EA
____~3~4.I_B~2~1
·'---1-+
========::.:/
.-"':.-~=;!~:---r
1
-
carry Is
Generated
35.
DRn BASE
•
·
•
•
•
Bits 0 and 1
•
33 35 •
• 01 2
saved to Make
•
-,-·_-
•
>>-------( -)
+
o·
33
•
Bounds Check
of EA
35
B
34 2
SEGMENT BASE FROM DRn
•
·•
··
Bound FIt If
• carry Is
OUt of Bound
• Generated
··
··
··
Bi ts 0-1 012
<-Re1ative Virtual Address
Effective Address + Base B
Sa ved to
Make WSN
2
32
2
··
Access
·
·
·
·
Control
•
· ••
eck
·· ··· ··•
·• OR.
· ·•
·· ·· ··
·
678
0
·· ·· ··
WSN
·· ·· ··
7 2
•
··
·· ··
·
40 41 43 46
8 9
0
·• ··
•
··
•
·• ··
33 35
·• Bound Fault If
(
•
•
Ch
. -
EFFECTIVE
WORKING
WORD ADDRESS WI THI N
SPACE 9
WORKI NG SPACE
where:
B
32
2
<-Resulting
Virtual Address
BIT
4
B - page byte
WSN - working space number
Figure 5-13.
Virtual Address Generation Using Extended Segment Descriptor
(NS Mode)
5-63
- DZ51-00
Virtual Address Generation Par ES Mode
In the ES mode, a 36-bit effective address is added to a segment descriptor to
generate a virtual address. The method used for generation of virtual addresses
differs depending upon whether the related segment descriptor is a standard segment
descriptor or an extended segment descriptor. Super descriptors must not be used
for address generation in ES m~e as any attempt to do so results in an IPR fault.
S'J.'ABDARD DESClUPTOR IS MODE
The method of forming an operand virtual address with a standard descriptor in ES
mode is shown in Figure 5-14. If instruction bit 29=0, the ISR is used; if bit
29=1, then DRn is used.
5-64
DZ51-00
o
33
35 36
39
EFFECTIVE ADDRESS
.\-------------------------------/.
. . ..
I----->------------>
---(-)
+
o
SEGMENT BASE
FROM DRn OR 1 SR
• carry is
• Generated
Bi ts 0-1
Malte WSN
2
saved to
Access
Control
Check
(
0
Effective Address
+
·
··
B
2
•
•
•
··
·•
··
··
··
··
40 41 43
··
·
··
•
··
··
·
2
··
8·9
EFFECTIVE
WORD ADDRESS WI THI N
WORKING
WORKI NG SPACE
SPACE 9
where:
2
32
WSN
0
34
Base
·· ··
·· OR.·
· ·
· ·
678
7
35
B
·· ·•
•
•
·• ··
·· ·•
33 35
·• Bound Fault If
···
o1
33
B
32
2
Bounds Check
of EA
··
Bound Flt.If
··
Out of Bound
··
··
<-Relative Virtual Address
···
·
··
··
·
·
·
···
46
<-Resulting
Virtual Address
BIT
4
B - page byte
WSN - working space number
Figure 5-14.
Virtual Address Generation Using Standard Descriptor (ES Mode)
EXTENDED SlGmNT DESCRIP'l'OR ES MODE
The method of forming an operand virtual address with an extended segment
descriptor (T = 12) is shown in Figure 5-15. It is the same as that using a
standard segment descriptor except in the bound check.
5-65
DZ51-00
o
33
.\-
34
35
B
2
39
I I BIT41.
-I .
1-->>-------->--·-------( -)
+
o·
•
33
SEGMENT BASE
FROM DRn
B
34
• carry Is
• Generated
0
··
•
o1
Effective Address + Base
2
32
WSN
2
··
8 ·9
0
EFFECTIVE
WORKING
SPACE
where:
B
2
·· ·•
·· ··
·· ·•
··· ··•
·· ·•
·· ··
40 42 43
·• ··
·• OR.·
·· ·•
678
7
2
·· ·•
·· ••
·• ••
33 · 35 ·
·• Bound Fault I f
Bi ts 0-1
saved to
Malte WSN
Access
Control
Check
·
35
WORD ADDRESS WI THI N
WORKING SPACE
9
B
32
2
Bounds Check
of EA
··
•
·•
Bound FIt If
OUt of Bound
··
··
•
<-Relative Virtual Address
··
•
··
•
··
··
··
··
46
<-Resulting
Virtual Address
BIT
4
B - page byte
WSN - working space number
Figure 5-15.
Virtual Address Generation Using Extended Segment Descriptor
(ES Mode)
5-66
DZ5l-00
Absolute Addressing Mode
(
Virtual memory provides an absolute addressing mode. When the processor uses the
absolute addressing mode, a virtual address is generated. However, the virtual
address is not mapped to a real address; it is used as the real address with a
maximum size limitation of 2**28 words (256 megabytes).
The processor utilizes the absolute addressing mode when the referenced working
space regi~ter or descriptor (with working space number) contains WSN = O. In
these cases, the upper two bits of the segment base are not OR' ed with the
working space number. The absolute address mode is fully set by the direct value
of the WSN.
To use the absolute addresing mode, the CPU must be in Privileged Master Mode.
If these conditions are not satisfied, a Command fault occurs when an attempt is
made to reference working space zero. The housekeeping bit is assumed ON when
working space zero is referenced.
When the processor is in the absolute addressing mode, address preparation
proceeds as in normal virtual address development. (Refer to Figure 5-16.)
o0
o
o
1 1
4
2
2 3
8 9
4
6
EFFECTI VE
EFFEC'1'I VE
WORK! NG SPACE
WORD ADDRESS
WORKING
SPACE
9
B
30
4
4
/
/\
\
\
Bits 9 - 12 are
ignored
/
\ Used as a 3D-bit absolute byte address of real
memory for the operating system. However,
paging is performed by the hardware.
Figure 5-16.
/
Effective Absolute Address
5-67
DZ51-00
Paging
After generation of a virtual address, an address translation process for mapping
a virtual memory address to a real memory address is performed by paging, in
order to create a real memory address for accessing the real memory.
Paging does not differ between the NS or ES mode.
ADDRESS 'l'RAHSLA'l'ION PROCESS
Memory paging is an integral part of the address translation process for mapping
a virtual memory address to a real memory address. Each of the 512 working
spaces is supported by one page table or one section table (SCI'). The working
space page table directory (WSPTD) is a 512-word table, indexed by a 9-bit WSN.
A WSPTD entry contains the real memory address of a page table or section table.
The section table consists of up to 4K words called page table base words (PBW).
Each PBW def ines the real memory address of a page table. When paging is
performed using section tables, PBWs cause the page table to be divided into 1K
blocks and allow them to be distributed throughout memory.
PAGE TABLE DIRl!C1'ORY WORD PORHA'l'
The format of the page table directory word is given in Figure 5-17.
o
o
1 1 1 2 222 2
7 8 9 0 1 234
2 3
3
9 0
5
R
PT/SCT Base
Q p
(MODI024W)
I
'1' F
2 1 1 1 U
18
__Type
PT/SC'I' SIZE
12
I ~ND
of PT
_Present
Bits 24-29
-ignored
_WS Access Control
Figure 5-17.
Page Table Directory Word (PTDW) Format
5-68
DZ5l-00
Bits
Description
0-17
The modulo 1024 base address (real memory address) of a page table
(PT) or a section table (SCT).
18,19
Provide a hardware method to force the isolation of the loiS. When
one or more loiS is allocated to a process, software will record in
these bit positions of the associated PTDW, the relative WSN within
the set of up to four possible numbers. These bits are used to
check the WSN at translation from a virtual memory address to a
real memory address. An SCL2 fault occurs if the check. fails.
20
= 0,
the PT/SCT is not present.
occurs. )
= 1,
the PT/SCT is present.
21
Ignored
22
o=
1
(A
missing working space fault
indicates a dense PT.
= indicates
an SCT.
23
Reserved for future use.
24-35
The size of the PT/SCT.
o For a dense page table, bits 24 to 35 indicate the modulo 64
size of the PT.
(
o For a section table, bits 30 to 35 indicate the modulo 64 size
of the SCT. Bits 24-29 are ignored.
o If bits 30 to 35 are zero, the size of 64 words is assumed.
PAGE TABLE BASE WORD FORMAT
The format of the page table base word is given in Figure 5-18.
o
1 1
PT Base
(MOD1024W)
Figure 5-18.
2 2 2 2
3 3
1 2
3
5
RFU
Page Table Base Word (PBW) Format
5-69
DZ5l-00
Description
0-17
Indicate the modulo 1024 base address (real memory address) of a
dense page table.
18,19
Reserved for future use.
. = 0, the PT is not present.
occurs. )
= 1, the PT is present.
20
(A missing working space fault
21,22
Must be zero.
23 to 31
Reserved for future use.
32 to 35
Define the modulo 64 size of a dense page table.
64 words is assumed.
If 0, the size of
PAGE TABLE WORD PORIIAT
The format of the page table word is given in Figure 5-19.
o
1
o
1
7 8
PAGE ADDRESS (MOD 1024)
18
Figure 5-19.
2 2 2 3
7 8 9 0
RESERVED FOR
SOFTWARE 10
3
5
RHO
CONTROL
2
FIELD
6
Page Table Word (P'l'W) Format
Description
0-17
The page modulo 1024 base address (real memory address).
18-27
Reserved for software use and may not be altered by the hardware.
28,29
Reserved for hardware use and may be changed by the hardware.
Control Field:
30
31
- Processor page present/missing bit
= 0, page is not in memory (missing)
= 1, page is in memory {present}
- Write control bit
= 0, page can not be written
= 1, page can be written
5-70
J
}
J
I
nterpreted only
by processor
J Bit 31 is
} interpreted by
J processor and
J
lOP
DZS1-00
Control Field:
(
32
- Housekeeping bit
= 0, nonhousekeeping page
= 1, housekeeping page
}
} Interpreted only by processor
}
33
- lOP page present/missing bit
= 0, page is not in memory (missing)
= 1, page is in memory (present)
34
- Page modified bit
= 0, page was not modified
= 1, page was modified
35
- Page access bit
= 0, page was not accessed
= 1, page was accessed
} Not inter} preted by
} processor
}
} Interpreted only by processor
]
}
} Interpreted only by processor
}
When the processor accesses the page table word (PTW), the hardware checks bit
30. If bit 30 = 0, a Missing Page fault occurs and no other faults that might
be caused by the page table word are checked. Refer to the discussion of "Page
Table Word Control Field Faults" in Section 6.
Note that the processor and the lOP have separate
page. Thus, during I/O, a page may be present to
processor or vice-versa. When a page is accessed
is accessed in main memory by hardware, bit 35 of
hardware.
bits to indicate a missing
the lOP but missing to the
by the processor, and the PTW
the PTW is set to 1 by the
When a write occurs to a page, and the modified bit in the page table word in
associative memory is 0, this bit is set to 1 and bits 34 and 35 of the page
table word in main memory are set to 1 by the hardware.
Note that if a write occurs to a page, and the modified bit in the page table
word in associative memory is 1, no changes are made to the page bits. SOftware
may have reset the page access bit, -bit 35, to zero. This bit remains zero
under this condition.
NAPPI NG THE VIRTUAL ADDRESS TO A REAL ADDRESS
If a prior memory reference to the same page has already mapped that page to
real memory, and if that mapping is still present in the associative memory of
the processor, then the mapping is accomplished by concatenating the Word field
of the virtual address to the modulo 1024 real address of the page, to produce
the real addres~ for the memory reference. Otherwise, the mapping proceeds by
locating and obtaining the Page Table Directory Word (PTDW).
If the PTDW indicates that the page table is not present (PTDW.P=O), then the
mapping is not completed, and a Missing Working Space fault is generated. If
the page table is present (PTDW.P=l) but PTDW.Q¢l, bits 0-1 of the relative
virtual address are compared and if they are not equal, then the mapping is not
completed, and a Class 2 Security Fault is generated.
5-71
DZ51-00
DENSE PAGE TABLE
When a dense page table is used, the CPU interprets the virtual address as shown
in Figure 5-20.
o0
8 9
o
0
EFFPX:TIVE
WSN
o1
PAGE NUMBER
I
9
444
0 2 3
3 3
1 1
2 3
WORD
18
4
Figure 5-20.
10
4
6
B BIT
,;
2
Virtual Address
Description
0-8
Working space to be accessed.
9-12
Ignored
13-30
Page number is used as an offset or index into the PT for this
WSN, for locating the P'l'W. The page number is relative to the PT
base address (real memory address) which comes from the PTDW.
31-40
Determines which word wi thin the 1024-word page is being
addressed.
41-46
Byte and bit positions within the word, if applicable.
LOCA'l'IHG '!'BE PAGE TABLE DIRll:"l'ORY WORD
The Page Directory Base Register (PDBR) contains the modulo 512 word address of
the Working Space Page Table Directory (WSPTD). Figure 5-21 shows how the
hardware uses the effective WS number from the virtual .address as an offset into
the WSPTD to obtain the Page Table Directory Word (PTDW) for address translation
using a dense page table.
Figures 5-21, 5-22, 5-23, and 5-24 illustrate virtual to real mapping using a
dense page table. I n Figure 5-21 below, the dense page table base address in the
P'l'DW is modulo 1024 words. PTW bits 0 to 17 are the modulo 1024W page start
address.
5-72
DZ51-00
o
18 Mod
~-=~---->
9-bi t WSN#
WSPTD
Page table base
(Mod l024W) PT
-..,.----->
+------t
--->
Paoe Base
(MOd 1024W)
PTDW
Paae
lS-bit Page# --->
PTW
=
(All addresses
are real)
=
Word within
Addressed
the page
-> ......-,;=-:;;;.......,.---+
Word
1KW
Figure 5-21. Address Mapping Using A Dense Page Table
(
In Figure 5-22, the PDBR indicates the base (mod 512 words)of the 512-word
WSPTD. The 9-bit effective WS number is combined with the 19 bits from the PDBR
to generate the real memory address to access the WSPTD. The PTDW includes the
real memory address (mod 1024 words) of the page table. The PT entry location is
determined by the 18-bit page number of the virtual address. The PTW includes
the real memory address (mod 1024 words) of the page. The 10-bit word address
field of the virtual address is combined with the lS-bit real memory address of
the page to generate a 2S-bit real memory word address. This generation is
illustrated in Figures 5-22, 5-23, and 5-24.
o
I
lS
Real memory address
from PDBR
19
0
I
S
rI-:E~f=-=f~ec-t~i:-v-e-~I
WSN
o
1
91
27
PTDW Word Address
Figure 5-22. PTDW Address
5-73
DZ5l-00
Virtual to real mapping through a Dense PT is shown in Figure 5-23.
The PTDW contains the base address (0 modulo 1024W) of the PT. The address of
the PTW is equal to the base address plus the lB-bit page number. The mapping of
the virtual address to the real address is completed when the PTW is obtained.
The mapping is then saved by the hardware in the associative memory. The PTW
contains the real address (0 modulo 1024) of the page. The 10-bit word field of
the virtual address is concatenated with the page real address to form the real
word address.
o
P'l' BASE
ADDRESS
·.0
·o
0
FROM
2
7 8
7
18
I ~----OlQ I
·
o·
3.
+
1 1
2 3
lB-BIT
-0
2
4
\-
---
17
---I.
I
•
>-
3
5
PT BOUND FROIf
PTDW (MOD 64) 1 - 1
12
6
PAGE # FROM
VI RTUAL ADDRESS
13
• (carry Ignored)
·•
·•0
PTDW
1 1
:
I
•
--->-(-)
· ·•
··
·
•
•
•
2•
7•
•0
PTW ADDRESS
28
···
•
SIZE CHECK
I
I f page size >
PT Bound/l1lllll then
a bound fault occurs
Figure 5-23.
PTW Address
5-74
DZ5l-00
o
o
(
1
7
PAGE ADDRESS FROM PTW
Bits 0 to 17
4
3
o
1
Real address
from PTW
WORD PART OF
VIRTUAL ADDRESS
Bits 31-40 10
18
2
7
0
0
WORD ADDRESS I N REAL MEMORY
28
Figure 5-24.
Word Address
The section table allows the page table for a working space to be fragmented
into sections. The PTDW specifies the base of the section table, which
contains up to 4K of page table base words (PBW), each of which defines a page
table for a section. When a section table (seT) is specified by the PTDW, the
virtual address is interpreted as shown in Figure 5-25:
o
0
EF'F'&:TI VE
o0
8 9
2 2
SECTION
WSN
NUMBER
12
9
Figure 5-25.
444
2 3
3 3
o1
o1
PAGE
0
WORD
NUMBER
10
4
6
B BIT
10 2
4
Virtual Address
Description
0-8
Working space to be accessed
9-20
Section number. An offset of the SCT base for accessing the PBW
in the SCI'. The SC number is a value relative to the seT base
indicated by the PTDW.
21-30
Page number is used as an offset or index into the PT for this
WSN, for locating the PTW. The page number is relative to the
PT base address (real memory address) indicated by the PBW.
31-40
Determines which word within the 1024-word page is being
addressed
41-46
Byte and bit positions within the word, if applicable
5-75
DZ51-00
Figure 5-26 illustrates virtual to real mapping when using a section table.
o
18 Mod
EI_51~_>
WSPTD
Section table base
(Mod 1024W) SCT
SCT
Page Base
(Mod l024W)
>
9-bit WSN
----->
PTDW
PI'
12-bit SCI
-
-->
Page Base
(Mod l024K)
>4---=:.P.::B;:.:.W_...
=
Max.
=
4KW
Paae
->
lO-bit Page# -->
PTW
All addresses
are real
Max. lKW
Addr'sed
->
Figure 5-26.
Word
Address Mapping Using A Section Table
5-76
DZ51-00
Development of a word address from a section table is illustrated in Figures 5-27,
5-28, and 5-29.
o
1 1
2
787
I
0 SCT BASE ADDRESS FROM PTDW
o
16 bits
\
/
T9~
·
...
2.
________________~0~.
3
SCI FROM
0----------0
SC'l' SIZE
FROM P'l'W
VI RTUAL ADDRESS
(carry 1 gnored )
3
5
0
1
12
6
\---------/
I
. ·
·
2
7· ·
· ··
28 I ·
·
1
6
----->~---------->---(-)
o
PBW WORD ADDRESS
SIZE CHECK
If SC#>SC'l' Bound/Illllll
then a Bound Fl t. occurs
(
Figure 5-27.
5-77
PBW Address
DZ5l-00
··
·•
··
·
o
11
·.0
·o
1 1
2
7 8
7
----0 101
PT BASE ADDRESS FROM PBW
1 2
7 1
- ----
0
-
3
+
o
PAGE # FROM
0
VI RTUAL ADDRESS
18
(carry Ignored)
10
\-
·•
I
.0
.0
3
2
3
5
PT
SIZE
FROM 11
PBW 4
1
6
··
··
•
··
I.
.- - - - ( - }I
- 2.
7.
PTW WORD ADDRESS
28
SIZE CHECK
If PG#>PT Sizelll11111
then a Bound fault
occurs
Figure 5-28.
o
0
..
•0
1
7
PAGE ADDRESS FROM PTW
(Bits 2-17)
18
PTW Address
3
4
1
0
WORD PART OF
VI RTUAL ADDRESS
(Bits 31-40) 10
.
•
2•
7•
•0
WORD ADDRESS I N REAL MEMORY
28
Figure 5-29.
Word Address
5-78
DZ51-00
ASSOCIATIVE MEMORY
After a virtual address has been mapped to a
page table word information is stored in the
way that a subsequent reference to this page
format of the data stored by an SCPR 16 from
Figure 5-30.
o
real address as described earlier,
associative memory (AM) in such a
can be mapped in one step. The
the associative memory is shown in
1 1
Page Number
Figure 5-30.
3 3 3 333
Zeros
Page Table Word Associative Memory (P'l'WAM) Format
Description
0-17
The first 17 bits hold the page number
18-30
Zeros
31-35
Page control bits:
W- write
H - housekeeping
M - modified
P - parity on PTWAM storage
(
5-79
DZ5l-00
When an operand virtual address is mapped from an associative
memory entry and the operation modifies the page, the hardware
checks the modi fied (M) control bit. 1 f the Mbit in the AM
entry is OFF, the processor turns the Mbit of the AM entry ON,
ref etches the page table word for this AM entry from main
memory, and turns the M control bi t in the page table word ON.
The access bit in the page table word is also set ON at this
time, since it may have been turned OFF by the software. 1 f the
Mbit of the AM entry is ON at the beginning of the mapping, no
change is required.
The associative memory is arranged in 64 rows by 2 columns. Each intersection
of a row and a column contains a 35-bit entry like the one shown above.
Page table directory words from associative memory are stored b¥ SCPR 16 with
the following format.
o0
o
2 2 2 2 223 3 3 3 3 3
RVA (Bits 2-17)
WSN
Figure 5-31.
Associative Memory Directory Word
Bits
Description
0-8
Working space number
9-24
Real virtual address (RVA) bits 2-17
25
When set
26
When set = 1 indicates full; 0 indicates empty
27
Round robin counter
=1
indicates parity error
o = level
1 =
28
0
level 1
Status of level A
o = ON
1 =
29
OFF
Status of level B
o=
ON
1 = OFF
30
When set = 1 indicates enable associative memory
;'
/'
5-80
DZ5l-00
(
The PTWAM directory word is obtained from the directory with its contents
placed into the A register by the Store Central Processor Register instruction
SCPR with tag = 17. The word is loaded from the A register and put into the
PTWAM directory by the Load Central Processor Register (LCPR) instruction.
Both of these instructions must be used in Privileged ~ter mode.
The PTWAM has two levels, A and B, and 64 columns from a total of 128 entries.
The LCPR ,17 instruction causes the following A-register bits to be loaded into
the directory word pointed to by the effective address:
o
-->
Full/empty bit
C(A)27 --> Round robin counter (RRO)
C(A)28 --> Level A set OFF
D(A)29 -> Level
B
set OFF
The PTWAM has only one full/empty(F/E) bit. When FIE = 1, both Level A and
Level B are full. When FIE = 0, the round robin counter (RRO) specifies
whether or not Level A is full. A typical operation sequence following
execution of LCPR 17 specifies the full/empty states as follows:
(
FIE
RRO
Level A
Level
1
o
o
o
Empty
Empty
1
Full
Empty
2
1
o
Full
Full
3
1
1
Full
Full
4
1
o
Full
Full
B
When a new address not contained in the associative memory has been mapped and
the associative memory is full, the new entry replaces the older entry in the
row (using the RRO algorithm).
The associative memory may be disabled (any further comparisons or matches are
ignored) by:
a. Executing a CAMP instruction with effective address bits 16-17
= 1.
b. Encountering an address compare of two or more columns in one of the 64
rows.
If one of the levels is OFF, the entry is still made in that level
corresponding to the state of the RRO counter. On a subsequent PTW search, the
OFF state of the level is recognized and a match is not permitted.
5-81
DZ5l-00
The associative memory is cleared whenever the following occurs:
a. The processor is manually initialized.
b. The processor is enabled, and the CAMP instruction is executed with
effective addrss bits 16-17 equal to 00, 10, or 11. If EA bits 16-17 =
01, the associative memory is disabled but not cleared.
c. The processor is disabled, and the CAMP instruction is executed with
effective address bits 16-17 = 10.
d. The processor is disabled, and the Load Page Table Directory Base
Register (LPDBR) instruction is executed.
CACHE KBNORY
A description of the visible portion of cache memory control follows. cache
directory data is returned to the A register on the instruction SCPR 15 from
the entry selected by the effective address.
1 1 111 1 1 1 2 2 2 2 222 2 2 2 3 3 3 3 3 3
2 3 456 7 8 9 0 123 456 7 890 123 4 5
Real Memory Address
III
III
III
I
I
I
Figure 5-32.
III
III
III
IIIIIIIII
IIIIIIIII
IIIIIIIII
cache Directory Word
Description
0-12
Most significant 13 bits of the real memory address
13-14
Not used
15
Parity on bits 0-9 of the real memory address
16
cache block fulliempty bit (normal mode)
NOTE: When certain cache blocks are used by PATROL, these blocks are
set to empty prior to normal use by the CPU.
17
Selected level parity error
18
Cache enable bit (1 = enable)
19
cache block fulliempty bit (PATROL mode)
20
Unused
21
cache enabled for instruction fetch (1
22
Parity on bits 10-12 of the real memory address
23
cache to register flag (1
= enabled)
= ON)
5-82
DZ51-00
(
Bits
Description
24-25
Level 0,1 ON when = 1
26-27
Unused
28
Least recently used (LRU) register
29-33
Unused
34-34
Lockup fault register
Address Truncation
The instruction set contains instructions that operate on words, double-words,
9-bit bytes, 6-bit characters, 4-bit characters, and bits. Instructions and
indirect and tally words that specify 6- or 9-bit characters are considered
word instructions. In accessing the operand, the full byte level virtual
address is determined. The address is then truncated in accordance with the
address type of the instruction, and the access is also in accordance with the
type of instruction.
.
exception to this procedure applies to the 8-word instructions, such as LREG
and SREX;. The effective address is truncated to a modulo 8 word address prior
to adding the base. Following the addition of the base, the virtual address is
then truncated to a double-word address.
An
The user is responsible for ascertaining correctness of operation of an
instruction as influenced by such address truncation.
Bounds Checking
Virtual memory allows specifying the base~ bound of a segment to the 9-bit
byte level, enabling a finer level of 'security control. Because the processor
interfaces with word-oriented main memories, certain restrictions are also
imposed to minimize the impact on performance and hardware complexity. The
size of a segment described by a super descriptor is modulo 2**26 bytes;
therefore, the bounds checking is always the same: BOUND (lower extended with
26 one bits) ~ LOCATION + EFFECTIVE ADDRESS. The following information applies
only to standard descriptors and extended descriptors.
(
5-83
DZ5l-00
WORD AHD DOtJBLE-WORD OPERATIONS
Word, double-word, or a succession of word accesses as in the LREG and SREG
instructions are made to real memory word or double-word boundaries. Segments
that begin or end on byte or word positions and that do not correspond to word
or double-word boundaries may be accessed by word or double-ward instructions.
The processor adds the 2-bit byte position held in an address register (if
selected) to the byte position of the base before truncating the final virtual
address to point to a word or double-word. If this truncation results in the
virtual address dropping below the base value, a lower bound check will declare
an out-of-bounds condition in this case and a Bound fault occurs.
Thus, the
first word or double-word of a segment may be accessed with word-oriented
instructions only when the word or double-word is entirely within the segment.
Half-word accesses, such as the LXLn instruction, are treated as word accesses
in both the lower-and upper-bounds check. If a segment begins in the middle of
a word, the LXLn and SXLn instructions cannot be used to access the lower
half-word. I f the segment ends in the middle of a word, the LDXB, STXn, LXLn,
ADX!!, etc., instructions cannot be used to access the upper half-word.
The STCA, STCQ, STBA, and STBQ instructions store 6-bit or 9-bit characters
into characterlbyte locations within a word. These are considered as word
accesses and require the entire word to be within the segment.
Indirect and tally words that specify characterlbyte locations are considered
as addressing words that must be fully contained in the segment. The virtual
address is truncated to the next lowest word boundary (i.e., the character
position in the base is not added to the character position held in the
indirect and tally word).
NOTE: This information is included to provide a warning for users of the
operating system and user software. If segments are "shrunk" (see the
LDDn and CLIMB instructions), and the byte portion of the virtual base is
changed, a word or double-word access to the new segment may be truncated
to a different location within the segment.
All instruction segments must begin at a 0 modulo 8 location and end at a 7
modulo 8 location. Any transfer or CLIMB instruction that attempts to load the
instruction segment register must specify a segment base whose 5
least-significant bits are Os, and a segment bound whose five least-significant
bits are Is. This condition allows the processor to access blocks of eight
words fo:- LPL, SPL, LREG, SREG, LAREG, and SAREG instructions with the
assurance that if the first word is on an assigned page and is within the
segment boundary, the other words will also be so located.
All descriptors loaded into the SSR, PSR, LSR, ASR , or DSDR registers must
begin and end on double-word boundaries (the three least-significant bits of
the base are Os and the three least-significant bits of the bound are Is).
5-84
DZ5l-00
BYTE OPBRATI OMS
(
For all 9-bit and 4-bit character operations using multiword instructions, the
upper-bound check is made at the 9-bit byte level. A lower-bound check is not
required since the effective address is always greater than or equal to zero.
For all 6-bit character operations using multiword instructions, the boundary
checking is on a double-word basis, meaning that a double-word containing any
6-bit character of the operand must be fully in bounds. If access is attempted
to a segment with a base or bound not on a double-word boundary, a Bound fault
is generated.
mT
S'l'RI1f~
AND TABLE OF 'l'RAKSLATE IRS'rRUC'l'IOIf
Multiword bit string instructions and the index table of the translate
instructions (MVT, TCT, and 'l'CTR) have double-word bound checking applied.
Thus, a double-word that includes any part of these operands must be fully in
bounds. If access is attempted to a segment that has a base or bound not on a
double-word boundary, a Bound fault is generated.
00UIfD CBK:K B'JUATIOIfS
The address truncation procedure described previously forces bounds checking to
vary depending upon the type of instruction specified. The resulting three
upper-bound and lower-bound checks are listed in Table 5-3. A Bound fault is
generated if the bound checks are violated.
5-85
DZ51-00
Table 5-3.
Instruction
Double-Word
(includes bit
string and 6bit character
instructions)
Single-Word
Byte
(includes
9-bit byte,
4-bit byte)
Bound Check Equations
Bound Check
111l~
Upper
(BASE
+
EA)0-32I
Lower
(BASE
+
EA)0-32 I 1000~ BASE
Upper
(BASE
+
EA)o-33 I III
~
BASE
Lower
(BASE
+
EA)0-33I 100
~
BASE
EA 0-19
~
BOUND
Upper
Lower
BASE
+
BOUND
+
BOUND
Always satisfied
The base, bound, and effective address (EA) addresses represented in the bound
check equations are for 9-bit bytes. For 4-bit byte and bit instructions, the
effective address represents the 9-bit byte in which these small quantities are
contained. The single- and double-word bound check equations include the
effect of address truncation: the truncated address is then extended to the
largest byte contained therein for the upper-bound check and to the lowest byte
for the lower-bound check. The byte checks refer to the byte accessed; in
multibyte instructions such as NU, the access checks are applied to each byte.
Physical accesses, which may be larger than those corresponding to a given
instruction (and which therefore may include bytes not contained in the
segment), are not bound checked beyond the byte range corresponding to the
instruction.
5-86
DZ5l-00
SBCrIOH 6
FAULTS AIID IIITBRRDP'I'S
Faults and interrupts both result in an interruption of normal sequential
processing, but there is a difference in how they originate. Generally, faults
are caused by events or conditions that are internal to the processor; but
interrupts are caused by events or conditions that are external to the
processor. Faults and interrupts enable the processor to respond promptly when
conditions occur that require system attention.
DESCRIPfiON OF FAULTS AIm INTERRUPTS
When the processor responds to a fault, interrupt, or special systems entry
(PMME), the ICLINE version of the CLIMB instruction is executed. Because this is
an inter-domain transfer of control, an entry descriptor is required; the entry
descriptor is obtained from a fixed memory location •. The interrupt, fault,
special systems entry, and Backup fault entry descriptor locations (in real
memory) are as follows:
(
Location (octal)
30-31
32-33
34-35
40-41
Entry Descriptor
Interrupt
Fault
Special systems entry
Backup fault
FAULT PROCEDURES
When a fault occurs, the processor generates the appropriate fault code and
executes the ICLIMB version of the CLIMB instruction. During the safe store part
of the rCLINE, the generated fault code is stored along with a flag to indicate
that the safe store frame is the result of the occurrence of a fault (bit 11 of
word 5 is set to 0).
If the fault occurred during a multiword instruction, the pointer and length
registers will be saved in the safe store frame.
The second word of the "wired-in" ICLINE instruction is assumed as described for
interrupts. (Refer to "Interrupt Procedure" later in this section.)
6-1
DZSl-OO
If an entry descriptor is not found in the fixed fault vector location or if
another fault should occur (e.g., a parity error) while the processor is
attempting to ClJMB to the fault handler, the processo~ attempts to obtain an
entry descriptor from the Backup fault vector location. If this second location
does not contain an entry descriptor, the processor enters the HALT state. If
the second fault occurs prior to the transfer of control to the new domain at the
end of the ICIJMB, then the safe store frame will overlay the original frame
(wi th the same information execpt, for fault code). I f the second fault occurs
during the transfer of domains, such as a page fault when obtaining the next
instruction, then a second frame is filled specifying the new domain and the
fault code of the type fault that caused the backup condition.
The processor is placed in the Privileged Master
"wired-in" ICIJMB instruction. Upon exiting the
the Privileged Master mode if flag bit 26 of the
(ISR) is 1. If flag bit 26 of the new ISR is 0,
mode.
mode for the execution of the
ICLIMB, the processor remains in
new instruction segment register
the processor cycles to Master
FAULT PRIORITY
Faults are organized into five groups to establish priority for the recognition
of a specific fault when two or more faults occur at the same time in different
groups. (Refer to Table 6-1.)
Only one fault within a priority group can be active at anyone time. If two or
more faults occur concurrently within a priority group, only the fault that
occurs first through normal program sequence is recognized.
FAULT RB:OGHITION
Processor-detected faults can be categorized in several ways. Table 6-1 lists
the faults in order of the octal fault code, shows the priority assigned by the
processor, and lists the priority group number.
Faults in Groups I and II cause the operations in the processor to terminate
unconditionally.
Faults in Group V are recognized under the same conditions that program
interrupts are recognized. Faults in Group V have priority over program
interrupts and also can be inhibited from recognition by engaging the inhibit bit
in the instruction word.
6-2
DZSl-OO
Table 6-1.
(
(
(
Processor Faults By Fault Code
Fault Code
Octal
Code
00001
02
Bound (BND)
00010
04
Master mode entry
00011
06
00100
Fault Name
Priority
Group
9
IV
10
IV
Fault tag (FTAG)
13
IV
10
Timer runout (TRO)
23
V
00101
12
Command (CND)
8
IV
00110
14
Derail (DRL)
11
IV
00111
16
Lockup
4
II
01000
20
Connect (CON)
22
v
01001
22
Parity
7
IV
01010
24
Illegal procedure
12
IV
01011
26
Operation not completed (ONC)
3
II
01101
32
Overflow (OVF)
6
III
01110
34
Divide check (DIV)
5
III
01111
36
Execute (EXF)
2
I
10000
40
Security class, 1
10001
42
10010
(MME)
(LUF)
(PAR)
(IPR)
(SCLl)
14
IV
Dynamic linking (DYN)
15
IV
44
Missing segment (MSG)
16
IV
10011
46
Missing working space (MWS)
17
IV
10100
50
Missing page (MPG)
18
IV
10101
52
Security class 2
19
IV
10110
54
Address trap (AnT)
21
IV
(See NOTE)
--
Safe store stack (SSSF)
20
IV
(SCL2)
NOTE: The safe store stack overflow fault has no fault code because it may occur
with any other fault. If a safe store stack fault occurs, the fault code
is contained in bits 12-16 of safe store stack frame word 5.
(Refer to
Figures 8-7 and 8-8 for a description of the safe store stack).
6-3
DZ51-00
FAULT CA'l')g)RI ES
('~",
There are four general categories of faults:
'~ .. ~/
1. Instruction-generated faults
2. Program-generated faults
3. Virtual memory-generated faults
4. Hardware-generated faults
Instruction-Generated Paul ts
An instruction generated fault can be traced to the execution of a particular
instruction. It may be an operating system service request or an illegally
coded instruction. The instruction-generated faults are the following.
1. Master Mode Entry (MNE)
A
Master Mode Entry instruction was executed.
2. Derail (DRL)
A Derail instruction was executed.
3. Fault Tag
A fault tag address modifier (F) was recognized. Fault tag is a
variation of the Indirect then Tally modification. Indirect cycles
terminate upon recognition of F, and the operation is not completed. The
tag field (bits 30-35) of the instruction or indirect word is set to 40
(octal) to cause the Fault Tag fault.
4. Connect (CON)
The processor received a signal from a system controller indicating that
some processor in the system executed a CIOC instruction directed to this
processor.
5. Illegal Procedure (IPR)
The attempted execution of an illegal instruction sequence or
modification generates an IPR fault. The attempted execution of a legal
Master mode instruction in the Slave mode causes a Command (eND) fault.
The attempted execution of any of the unassigned instruction operation
codes generates an Illegal Procedure fault.
An IPR fault occurs for any register specification that contains a tag
defined as illegal.
6-4
DZ51-00
fault occurs when an attempt is made to repeat any multiword
instruction with the use of the RPT, RPD, or RPL instructions 1 or to XEC
or XED2 any mu1tiword instruction. (An XEC instruction may point to a
multiword instruction; however, the descriptors for the multiword
instruction must be stored in memory immediately following the XEC
instruction.)
An IPR
(
An IPR
fault occurs for:
a. any attempt to address through a descriptor of type T
12-15 by any instruction
= 7,
10, or
b. any attempt to address through a descriptor of type T
by any instruction other than ClJMB
= 5,
8, 9, or 11
c. any attempt to address through a descriptor of type T
instruction other than ClJMB, LDDn, or STDn
=1
d. any attempt to address through a descriptor of type T
or 11 for vectors by the LDD or ClJMB instruction
= 1,
or 3 by any
3, 5, 8, 9,
An IPR fault occurs when a CLIMB instruction is passing parameters (E =
1, ORO = 0, 2, 4, or 6) and attempts to use a vector that has S and D
fields = 00, 1760 (octal) or 00, 1761 (octal) or V = 10 binary.
An IPR fault occurs when a LD~ instruction attempts to use a vector that
has Sand 0 fields = 00, 1760 (octal), or V = 10 binary.
fault occurs when a LDp!! instruction attempts to use an operand
that has Sand 0 fields = 00, 1760 (octal).
An IPR
An
IPR fault occurs when the Sand D fields of a CLlMB instruction have S
and D = 1761, or 1763 through 1767 (octal).
= 00
An IPR fault occurs if the LOOn or CLIMB instruction specifies a shrink
operation (normal or data stack) of a descriptor with T = 5 or 7-15.
An IPR fault occurs during a CLlMB instruction when a valid entry
descriptor does not refer to a standard descriptor (T = O).
fault occurs if the OCLIMB version of the CLIMB instruction is
specified and the safe Store Bypass Flag is zero.
An IPR
IPR fault occurs during a CLIMB instruction that either was initiated
by a fault or interrupt or encounters the special systems entry and the
descriptor accessed from the fixed location is not T = 5, 8, 9, or 11.
An
1. RPT, RPO, RPL execute in NS mode only.
2. XED executes in NS mode only.
6-5
DZ5l-00
IPR fault occurs during the CLIMB instruction when the descriptor
referenced by the S and D fields is not T = 0, 1, 2, 3, 8, 9, or 11.
Also, if this descriptor has T = 1 or 3, it must refer to a descriptor
with T = 5, 8, 9, or 11 or the fault will occur.
An
IPR fault occurs during a Load Safe Store Register (LDSS) instruction
if the descriptor to be loaded into the safe store register register
An
(SSR):
a. does not have
T =
1 or 3
b. has T = 1, but does not have flag bits 20, 21, 27, and 28
bits 25 and 26 = a
c. has T = 3 but does not have flag bits 20 and 21
=1
and flag
=1
d. bas a base that is not modulo-2 words (bits 33-35 are not equal to
000)
An IPR fault occurs during the Load Data Stack Descriptor Register
(LDDSD) instruction if the descriptor to be loaded into the data stack
descriptor register (DSDR):
a. does not have
T
=0
b. bas a base that is not modulo-2 words (bits 33-35 are not equal to
000)
c. has a bound that is not 7 modu1o-8 bytes (bits 17-19 are not equal to
111)·
d. has flag bit 22 (store)
'-- /
=1
An IPR fault occurs during the Load Extended Address n (LD~)
instruction if the descriptor to be loaded does not have T = 4 or 6
(super descriptor).
IPR fault occurs during the Load Argument Stack Register (LDAS) and
Load Parameter Segment Register (LDPS) instruction if the descriptor to
be loaded:
An
a. does not have T = 1
b. has a base that is not modu1o-2 words (bits 33-35 are not equal to
000)
c. has flag bit 27 equal to 1 and a bound that is not 7 modulo-8 bytes
(bits 17-19 are not equal to 111)
An IPR fault occurs when an unconditional transfer (TRA, TSXn), or a
satisfied conditional transfer (TNZ, TPL, etc.) attempts to load a
descriptor into the instruction segment register (ISR) that either does
not have type T = a or does not have a modulo-8 word base and bound. If
this fault is detected, the ISR is not changed.
?,
I
~-j
6-6
DZ51-00
IPR fault occurs in the ClJMB instruction when a standard descriptor
(T = 0) that is to become a new ISR descriptor does not have a modulo-B
word base and bound. This fault occurs before the domain register are
changed.
An
f
Progru-Generated Faults
The program-generated faults occur through some action under the control of
either the process itself or the operating system. There are four major
categories of program generated faults, each of which has several
subcategories:
1. Arithmetic Faults
a. Overflow (OVF). An Arithmetic overflow, exponent overflow, or
exponent underflow has been generated. The generation of this fault
is inhibited when the overflow mask is in the masked state.
Subsequent clearing of the overflow mask to the unmasked state does
not generate this fault from previously set indicators. The Overflow
fault mask state does not affect the setting, testing, or storing of
indicators.
For the automatic fault on truncation, the procesor executes the
Overflow fault. Note that the overflow mask bit (indicator register)
does not affect automatic fault on truncation.
b. Divide Check (DIV). A Divide Check fault is generated when the actual
division cannot be carried out for one of the reasons specified below:
1) DIV instruction - if the dividend equals -2**35 and the divisor
equals zero or minus 1
2) DVF instruction - if the absolute value of the dividend is greater
than or equal to the absolute value of the
divisor or if the divisor equals zero
3) FDV, FDI, DFDV - if the mantissa of the divisor equals
DFDI instr's.
zero
4) DV2D, DV3D
instructions
- if the divisor equals zero or if the
quotient is to be stored in scaled format and the
calculated length required for the quotient is
greater than 63.
2. Elapsed Time Interval Faults
a. Timer Runout (TRO). This fault is generated when the count in the
timer register reaches zero and cycles to minus 1. If the processor
is in Privileged Master mode, the recognition of this fault will be
delayed until the processor returns to the Master or Slave mode. This
delay does not inhibit the counting in the timer register. (Refer to
the Disconnect (DIS) instruction in Section B for the exception to
this action.)
6-7
DZ51-00
b. Lockup (LUF). The processor remains inhibited for greater than the
lockup time. Examples of this condition are the coding TRA * or the
continuous use of the inhibit bit.
I
Master mode lockup time is set at 128 milliseconds and Slave mode
lockup time is specified by the lockup fault register as seen in the
settings below. These times can be loaded in Privileged Master mode
using the Load Central Processor Register (LCPR) instruction with the
register specified in the tag field.
Settings of the Lockup fault register are as follows:
Bits 34-35 Milliseconds
8.0
16.0
32.0
64.0
00
01
10
11
c. Operation Not Completed (ONC) This fault is generated due to one of
the following conditions:
1) No system controller is attached to the processor for the address
specified.
2)
Operation is not completed. An ONC fault can be generated by
disabling the SCU ports via program control while the program is
being executed.
NOTE: A ONe fault can also be generated by hardware malfunction.
3. Command Faults
a. Attempted execution of instructions requiring Privileged Master mode
when the processor is not in Privileged Master mode.
b. Attempted use of working space register zero in Slave mode, or attempt
access to working space zero when the processor is not in the
Privileged Master mode.
c. Used a vector in Master mode or Slave mode with an LDDn or LDPn
instruction that specifies S = 00 and D = 1761, 1763, or 1764 (octal)
.(type change, DSDR or SSR).
d. A connect instruction addressed to a halted or disabled port. An
entry is made in the port's connect queue even though the port is
halted or disabled.
NOTES:
1. A fault or interrupt places the processor in the
Privileged Master mode for the execution of the "wired-in"
IClJMB instruction.
f a ClJMB instruction specifies the special system entry
version (PMME), this fault is not checked for the access
of the new lSR.
2. I
6-8
DZ5l-00
/'
-
I
4. Bound
{
(BND)
This fault is generated when:
a. No physical memory exists for the effective address.
b. An address is outside the segment boundary.
c. An attempt is made to use absolute addressing or dense paging with a
relative virtual address ~ 2**28 words.
d. An attempt is made to access the contents of an empty segment (flag
bit 27 = 0) of a type T = 0, 1, or 4 segment.
NOTES:
1. When "pushing" descriptors on the argument segment during
the execution of the SDRn or ClJMB instruction, the fault
does not occur if flag bit 27=0 but does occur if ASR
bound plus 8 bytes> 8192 bytes (2K words).
2. If this fault occurs for any version of the ClJMB
instruction, it is generated when the new descriptor for
the instruction segment register (ISR) is obtained.
e. An attempt is made to access the contents of a type T
segment and:
= 0,
1, 2, or 3
1) The upper or lower bound is exceeded.
(
2) The addition of the base and the effective address fields produces
a carry.
f.
An attempt is made to access the contents of a type T
and:
= 4 or
6 segment
1) The bound field is exceeded.
2) The addition of either the location and effective address fields or
the location, effective address, and base fields produces a carry.
g. The E field equals 1 during the execution of the ClJMB instruction,
descriptor register 0 contains a T = 1 descriptor (parameters are
framed by descriptor register 0), and P+1 > DRO bound, or DRO flag bit
27 = 0 (bound not valid).
h. Boundary violations occur in the shrink operation as indicated in the
description of the LDDn instruction in section S, or when preparing
descriptors during a CLIMB instruction.
i. An attempt is made to execute a multiword instruCtion that specifies
6-bit or bit string data in a segment whose base or bound is not
modulo-2 words.
(
6-9
DZSI-00
virtual Memorv-Generated Faults
Virtual memory-generated faults are:
1. Security FaulL, Class 1 (SCLl) occurs as follows:
a. Upon an attempt to obtain instructions via a sequential instruction
fetch, an unconditional transfer, a satisfied conditional transfer, or
a CLIMB instruction in one of the illegal processor modes specified in
Table 6-2.
Table 6-2.
Bit Status
Processor Modes
Privileged
Master Mode
Master
Mode
Slave
Mode
Illegal
Combinations(l)
Master Mode bit in
indicator register (IR)
ON
ON
OFF
ON
OFF OFF OFF
Privileged bit in
instruction segment
register
ON
OFF
OFF
ON
ON
Housekeeping bit 32 in
page table word (PTW)
for the instruction(2)
ON
ON
OFF OFF
OFF ON
OFF
ON
OFF ON
(I)
Results in a Security Fault, Class 1
(2)
The housekeeping bit is assumed to be ON when working space zero
is referenced and the processor addresses real memory directly.
{There is no page table from which to retrieve the housekeeping
bit. }
b. Upon attempt to modify a housekeeping page of a type T = 0, 2, 4, or 6
segment in Master mode
Housekeeping pages of type T = 1 or 3 segments may be modified in
Master mode under the following conditions:
1) CLIMB instruction - safe store and push parameters on the argument
stack
2) SDRn instruction - Push to the argument stack
3) STDn instruction - If instruction bit 29
= 1 and
DRm is T
=1
or 3
c. Upon an attempt to access or modify a housekeeping page of a type T =
0, 2, 2, 4, 6 segment in Slave mode.
/
6-10
DZ51-00
(
NOTE: When a CLIMB instruction is executed in Slave mode and it
invokes the special systems entry (PMME), the Security fault,
class 1 occurs if E = 1, DRO = 0, 2, 4, or 6, and a housekeeping
page is accessed.
This condition cannot occur for the SDRn instruction but occurs for
the LDPn, LDDn, CLIMB, and STDn instructions as follows:
1)
LDPn - operand accass
2)
LDDn - vector access (es) and data stack clear
3)
CLI MB - vector access (es) and the access for the second word of the
instruction If the system entry (PMME) is invoked, the fault
detection is not overwritten.
4) STDn - instruction bit 29
= 1;
DRm type T
= 0,
2, 4, or 6
d. Upon an attempt to access or alter a nonhousekeeping page of a type
= 1, 3, 8, 9, or 11 segment
T
This condition only occurs for the LDDn, LDp!!, CLIMB, SDRn, and STDn
instructions. Any other reference to a type T = 1 or 3 segment causes
an IPR fault. The conditions under which the Security Fault, class 1,
can occur are:
LDDn or LDp!! - accesses of descriptor from parameter segment
(S = 00, D < 1760), argument segment (S = 10), or
linkage segment (S = -1 or 11)
= 1,
DRm is type T
=1
LDI>!!
- instruction bit 29
or 3
CLIMB
- accesses to obtain the new LSR and ISR descriptors
- accesses for safe store or restore
- accesses to the parameter, argument, or linkage
segments for descriptors to be passed
- accesses to the argument segment to store parameters
=1
STDn
- instruction bit 29
and DRm is type T
STRn
- write to argument segment
= 1 or
3
2. Dynamic Linking Fault (DYN)
A Dynamic Linking fault occurs if the S, D field of a programmed CLIMB
(CALL, LTRAS, LTRAD) points to a dynamic linking descriptor (T = 5), or
to an indirect descriptor (T = 1 or 3) which points to a dynamic linking
descriptor. Any attempt by any other instruction to address through a
dynamic linking descriptor causes an IPR fault.
(
6-11
DZ51-00
3. Missing Segment Fault (MSG)
A Missing Segment fault is generated when an attempt is made to access
memory using a segment descriptor whose flag bit 28 equals zero. This
condition can occur only with descriptor types T = 0, 1, or 4.
4. Missing Working Space Fault (MWS)
A Missing Working Space fault is generated during virtual to real memory
mapping when the word obtained from the working space page table
directory has bit 20 (page table or section table missing/present) equal
to zero.
5. Missing Page Fault (MPG)
A Missing Page fault is generated during virtual to real memory mapping
when the page table word has bit 30 (page missing/present) equal to zero
When a Missing Page fault occurs, the processor stores an appropriate
value in FRTRY to indicate whether or not the fault is recoverable if
software supplies the missing page and returns to the program.
o = Missing
1
= Missing
Page fault is not recoverable
Page fault is recoverable
Word 5, bit 0 of the safe store frame is defined as the retry flag
(FRTRY). FRTRY has a defined value only when a Missing Page fault
occurs. The value of FRTRY is undefined for all other faults.
When a Missing Page fault occurs, the processor stores an appropriate
value in FRTRY to indicate whether or not the fault is recoverable if
software supplies the missing page and returns to the program.
o = Missing
Page fault is recoverable
1 = Missing Page fault is not recoverable
Recoverable means that if the faulting instruction did not modify the
instruction being executed or any of its string descriptors, and if
software pages in the missing page updates the PTW and OCLIMBs, then
execution is resumed exactly as if the fault had not occurred, except for
the time delay.
The only reasons for which the processor sets FRTRY = 1 (not recoverable)
in the safe store frame are:
1) Occurrence of a Missing Page fault while executing an RPT, RPD, or
RPL instruction l •
2) Occurrence of a Missing Page fault while executing an instruction
pointed to by an XEC or XED2 instruction
fi~
~)
1. RPT, RPD, RPL execute in NS mode only.
2. XED executes in NS mode only.
6-12
'\
DZ5l-00
3) Occurrence of a Missing Page fault during an indirect and tally
operation
Before the EIS numeric, MVE, DTB, or BTD instructions execute, all pages
containing parts of the operands and pages in which the results are to be
stored must be in memory concurrently. Thus, in processing a Missing
Page fault on one of these instructions, the paging software should not
remove one of the pages referenced by the instruction; otherwise, upon
return to the instruction, another Missing Page fault will occur.
6. security Fault, Class 2 (SQ.2)
A security Fault, class 2, is generated for the following field
violations on descriptors and page table words:
a. In a segment descriptor, if an attempt is made to violate flag bits
20, 21, 22, or 25 (read, write, store, or execute) as follows:
1)
An
2)
attempt is made to alter (write) a segment whose flag bit 21 =
0, except when pushing descriptors on the argument stack during the
CLIMB or SDRn instructions
attempt is made to read any type of data (except instructions
for execution and for the I SR in the eLI MB instruction) from a
segment whose descriptor has flag bit 20 = 0 (read not allowed)
An
= 1 or 3 segments
using the STDn instruction and the descriptor being stored does not
have store permission (bit 18 of an entry descriptor with type T =
8, 9, or 11; bit 22 for all other descriptor types)
3) An attempt is made to store data into type T
attempt is made to execute a transfer instruction to a segment
in which the execute control flag (bit 25) does not equal 1. This
fault is also detected in the CLIMB instruction when the new ISR is
obtained before any registers have changed
4) An
b. In a page table word, if an attempt is made to violate flag bit 31
(write control)
A Security fault, class 2, is generated when bits 18 and 19 (working
space access control) of the page table directory word do not match bits
o and 1 of the 36-bit relative virtual address (attempt to violate
working space).
This fault is also generated during the execution of the OClJMB version
of the eLI ME instruction if the data being loaded from the safe store
frame is incorrect as follows:
a. The descriptor to be loaded into the ISR does not have the following
format:
1) Type field T
=0
2) Flag field bits 25, 27, and 28
6-13
=1
DZ51-00
3) Base field
= 0 modulo-32 bytes
4) Bound field. = 31 modulo-32 bytes
'b. The descriptors to be loaded into the PSR and ASR do not have the
following format:
1)
Type
field T - 1
2) Base = 0 modulo-8 bytes
3) Bound
= 7 modulo-8
bytes when flag bit 27 = 1
c. The descriptor to be loaded into the LSR does not have the following
format:
1) Type field T
=1
2) Flags field bits 20, 23, 27, and 28
26 = O.
3) Base field
=0
= 1,
and bits 21, 24, 25, and
module-8 bytes
4) Bound field = 7 modulo-8 bytes
A Security Fault, class 2, is generated on intersegment transfers when
flag bit 25 = 0 in the descriptor for the target segment.
7. safe Store Stack Fault (SSSF)
The safe Store Stack fault occurs to report to the operating system that
the safe store stack has only one or two 64-word or BO-word frames
remaining. Two different conditions cause a safe Store fault.
a. If the safe store stack overflow occurs as a result of a CIJMB
instruction, two frames are stored:
1)
The first frame is the normal calling domain frame without the
overflow flag set.
2) The second frame is set up to return control to the first
instruction of the called domain.
The overflow flag is set. Control passes to the fault processor via
the entry descriptor at real memory address 32-33 (octal).
()
"'--6-14
DZ5l-00
The ha~dware detects a safe store overflow condition by assuming a
worst case condition -- two full frames must remain available after a
normal, successful CLIMB, or overflow will be reported. Thus, if in
the NS mode the SSR bound -< 191 words ~
3 bytes (allows three more 64-word frames)
safe store overflow occurs.
I f the processor is in
<
239 words
~
ES
mode, the formula for the
SSR
bound is
3 bytes (allows three more BO-word frames)
b. While generating the safe store frame, the hardware updates the SSR
base and bound to determine whether a Safe Store Stack fault should be
indicated in the safe store frame together with the original fault or
interrupt. If the fault or interrupt exhausts the safe store stack,
the frame is stored with the safe store overflow flag set to 1 in word
5 bit 10. The original fault code or interrupt cell number is stored
in word 5, bits 12-16. Control is passed through the entry vector at
real memory address 32-33 (octal) to the fault processor. (The safe
Store Stack fault is not executed: a separate safe store stack frame
is not stored.) The SSR points to the current stack frame
7-8
DZ51-00
ADDRESS REGI STER I NSTRUCTI ONS
ADDRESS REGI STER I NSTRUC'I'I ONS
(
ADDRESS RBGI S'I'ER I RSTRUCTI ORS
This set of instructions provides the capability for using address registers to
manipulate the address portion of numeric and alphanumeric descriptors. I f an
address register is to be used in address preparation, its usage is specified
in the instruction word. All single-word instructions, to which address
modification is applicable, have essentially the same machine instruction word
format which hardware interprets differently depending on whether the processor
is in the NS or the ES mode. (Refer to Section S.)
000
023
1 1
2 2
7 8
7 8 901 2
2 3 3 3
LOCSYM
TIn
OP CODE
01 SPLACEMENT (y)
AR#I
Figure 7-1.
AR#
-
LOCSYM
-
I
3
S
Td
AR
TAG
Single-word Instruction With Address Modification
One of eight address registers (0-7)
Represents either address of operand or displacement from a
base
IS-bit displacement from the address register address
(two's complement: values from -16,384 to +16,383)
DI SPLACEMENT
(y)
OP CODE
-
A 10-bit operation code field
I
-
Program interrupt inhibit bit
AR
-
If bit 29 is 1, an address register is to be used and is
specified by bits 0, 1, and 2 of the y field. If bit 29 is
0, no address register is used.
TAG
-
Tag field that controls all other address modification. If
an address register is used on an instruction with indirect
addressing, it is applied only on the fetch of the indirect
word.
tag modifier
Td - tag designator
TIn -
7-9
DZ51-00
ADDRESS REG! STER I NSTRUCTI ONS
ADDRESS REGI STER I NSTRUCTI ONS
Address Register Load
LARn
LAREG
Load Address Register n
Load Address Registers
76n (1)
463 (1)
Address Register Store
SARn
SAREG
Store Address Register n
Store Address Registers
74n (1)
443 (1)
AI.ter Address Register Contents
This set of instructions provides the capability for replacing, incrementing,
and decrementing the contents of an address register on either a word,
character, or bit address basis. The operation is register-to-register, with
no memory fetch involved.
The special instructions have the same instruction format:
0
0
0
2
o0
I I51
AR#
1 1
7 8
3 4
I
y
Figure 7-2.
2 2 2 3 3 3
7 8 9 0 1 2
OP CODE
IIH mzl
3
5
DR
I
Alter Address Register Contents
AR#
Selects address register to be altered.
S
Sign bit. (Refer to section 5 for differences betwen NS and ES
modes. )
y
A word displacement (no character or bit position included) used
along with the contents specified in the DR field to alter the
contents of the specified address register. Bit 3 provides negative
(two's complement) or positive word displacement.
OP CODE -
10-bit operation code field.
I
Program interrupt inhibit bit.
AR
Address register bit.
7-10
DZ5l-00
.j
ADDRESS REG! STER I NSTRUCTI ONS
ADDRESS REGI STER I NSTRUCl'I ONS
(
If bit 29 = 1, the sum of the DR (in characters, words, or bits)
and the y field (in words) are added to or subtracted from the
contents of the ARspecified in bits 0-2.
If bit 29 = 0, the above described sum or its two's complement is
loaded into the AR for addition or subtraction, respectively.
I f the mnemonic is coded with
forced to zero.
:x (for example, AWDX} , bi t 29 is
MBZ
Bits 30-31 must be zero.
DR
Displacement register. Specifies which register contains the
displacement value. The register codes and register lengths are
the same as those used in MF fields except that IC modification is .
illegal. (Refer to Table 5-2.) (Refer to "Multiword Modification
Field" in this section.).
The operations for adding a value to the contents of an address register
proceed as with effective operand address preparation from an operand
descriptor, with the final results being stored in the specified address
register.
The subtract operation differs only in that the contents of the register
specified by the code in the DR field are first added to the y field. This
result is then subtracted from the actual contents of the address register or
from the implied zero contents and the result is placed in the address
register. The codes for DU, DL, and IC are illegal for the DR field and cause
an IPR fault.
The indicators are unaffected by these instructions.
(l)
A4BD(X)
A6BD(X)
A9BD(X)
ABD(X)
AWO(X)
S4BD(X)
502
501
500
503
507
522
S6BD(X)
521 (l)
S9BD(X)
520 (1)
SBD(X)
SWO(X)
523 (1)
527 (l)
(1)
(1)
(1)
(1)
(l)
Add 4-Bit Displacement to Address Register
Add 6-Bit Displacement to Address Register
Add 9-Bit Displacement to Address Register
Add Bit Displacement to Address Register
Add Word Displacement to Address Register
Subtract 4-Bit Displacement from Address
Register
Subtract 6-Bit Displacement from Address
Register
Subtract 9-Bit Displacement from Address
Register
Subtract Bit Displacement from Address Register
Subtract Word Displacement from Address Register
(
7-11
DZ5l-00
ADDRESS
ADDRESS REG! STER I NSTRUCTI ONS
REG! STER
I NSTRUCTI ONS
Special Address Register Instructions
Special instructions provide use of address registers to manipulate the address
portion of numeric and alphanumeric operand descriptors. These instructions
may be used only in the NS mode. If an attempt is made to execute these
instructions in the ES mode, an IPR fault occurs.
These special instructions have the following instruction format:
o
y
Figure 7-3.
AARn
ARAn
ARNn
NARn
222 3 3 3
1 1
56n
54n
64n
66n
(1)
(1)
(1)
(1)
3
OP CODE
special Address Register Instructions
Alphanumeric Descriptor to ARn
ARn to Alphanumeric Descriptor
ARn to Numeric Descriptor
Numeric Descriptor to ARn
7-12
DZ5l-00
BOOLEAN OPERATIONS
BOOLEAN OPERATIONS
(
BCX>LEAH OPERATION I NSTRUC'l'IOlfS
The logical operations AND, OR, and EXCLUSIVE OR are permitted between storage
and the index registers, A- and Q-registers, and the AQ-register. These
instructions use th~ single-word instruction format.
Boolean Expressions
A Boolean expression is defined similarly to an algebraic expression except
that the operators *, I, +, and - are interpreted as Boolean operators. 'l'wo
types of boolean expressions are defined below:
1. The expression that appears in the variable field of a BOOL
pseudo-operation uses Boolean operators.
2. The expression that appears in the octal subfield of the variable field
of a VFD pseudo-operation uses Boolean operators.
Evaluation Of Boolean Expressions
(
A Boolean expression is evaluated following the same procedure used for an
algebraic expression except that the operators are interpreted as Boolean.
I n a Boolean express ion, the operators +, -, *, and I have Boolean meanings,
rather than their normal arithmetic meanings, as follows:
Operator
+
Meaning
Definition
OR, inclusive OR,
union
o + 0 =0
o+ 1 = 1
1 + 0 =1
1 + 1 =1
EXCLUSI VE OR
symmetric difference
oo-
=0
=1
0 =1
0
1
1 1 - 1
7-13
=0
DZ51-00
BOOLEAN OPERATIONS
BOOLEAN OPERATIONS
Meaning
Operator
Definition
AND, intersection
*
0
1
0
1
1 == 1
1
one's complement,
complement, NOT
I
=0
o*
o*
10
11
*
*
==
0
=0
== 1
== a
Although I is a unary operation involving only one term, by convention AlB is
taken to mean A*/B. This is not regarded as an error by the assembler. Thus,
the table for I as a two-term operation is:
010 = a
Oil = a
1/0 = 1
III == 0
and other conventions are:
+A
-A
*A
= A+ = A
= A- = A
= A* = 0
(possible error, operand missing)
AI = Ala = A
Boolean AND
ANA
ANAQ
ANQ
ANSA
ANSQ
ANSXn
ANXn
375
377
376
355
356
34n
36n
(0)
(0)
(0)
(0)
(0)
(0)
(0)
AND
AND
AND
AND
AND
AND
AND
to
to
to
to
to
to
to
A-Register
AQ-Register
Q-Register
Storage from A-Register
Storage from Q-Register
Storage from Index Register n
Index Register n
7-14
DZ51-00
BOOLEAN OPERATIONS
(
BOOLEAN OPERATIONS
Boolean OR
ORA
OUQ
ORQ
ORSA
ORSQ
ORSXn
ORXn
275
277
276
255
256
24n
26n
(0)
(0)
(0)
(0)
(0)
(0)
(0)
OR
OR
OR
OR
OR
OR
OR
to
to
to
to
to
to
to
A-Register
AQ-Register
Q-Register
Storage from A-Register
Storage from Q-Register
Storage from Index Register n
Index Register n
Boolean EXCLUSIVE OR
ERA
ERAQ
ERQ
ERSA
ERSQ
ERSXn
ERXn
(
--
675
677
676
655
656
64n
66n
(0)
(0)
(0)
(0)
(0)
(0)
(0)
EXCLUSIVE
EXCLUSIVE
EXCLUSIVE
EXCLUSIVE
EXCLUSIVE
EXCLUSIVE
EXCLUSIVE
OR
OR
OR
OR
OR
OR
OR
to
to
to
to
to
to
to
A-Register
AQ-Register
Q-Register
Storage with A-Register
Storage with Q-Register
Storage with Index Register n
Index Register n
Boolean CDMPARATIVE AND
CANA
CANAQ
CANQ
CANXn
315
317
316
30n
(0)
(0)
(0)
(0)
Comparative
Comparative
Comparative
Comparative
AND
AND
AND
AND
with
with
with
with
Comparative
Comparative
Comparative
Comparative
NOT
NOT
NOT
NOT
AND
AND
AND
AND
A-Register
AQ-Register
Q-Register
Index Register n
Boolean CDMPARATIVE HOT AND
CNAA
CNAAQ
CNAQ
CNAXn
215
217
216
20n
(0)
(0)
(0)
(0)
with
with
with
with
A-Register AQ-Register
Q-Register
Index Register n
(
7-15
DZ51-00
FI XED POI NT I NSTRUCTI ONS
FI XED POI NT I NSTRUCTI ONS
,f'
\,
I
,)
FIXED-POI 1fT I RS'l'RUCTI ONS
Data
lIoYement Load
635
636
62n
335
337
336
32n
235
034
237
634
236
032
22n
073
72n
EAA
EAQ
EAXn
LCA
LCAQ
LCQ
LCXn
LDA
LDAC
LDAQ
LDI
LD;2
LDQC
LDXn
LREG
LXI..n
Data
(0)
(0)
(0)
(0 )
(0 )
(0)
(0)
(0)
(0 )
(0)
(0 )
(0)
(0)
(0 )
(0)
(0 )
Effective Address to A-Register
Effective Address to Q-Register
Effective Address to Index Register n
Load Complement into A-Register
Load Complement into AQ-Register
Load Complement into Q-Register
Load Complement into Index Register n
Load A-Register
Load A-Register and Clear
Load AQ-Register
Load Indicator Register
Load Q-Register
Load Q-Register and Clear
Load Index Register n from Upper
Load Registers
Load I ndex Register. n from Lower
Movement Store
SBAR
SREG
STA
STAC
STACQ
STAQ
STBA
STBQ
STCl
STC2
STCA
STCQ
STI
STQ
STT
STXn
STZ
SXLn
550 (0)
753 (0)
755 (0)
354(0)
654 (0)
757 (0)
551 (O)
552 (0)
554 {O}
750 (0)
751 (0)
752 (0)
754 (0)
756 to}
454 (0)
74n (0)
450 (0)
44n (O)
/
Store
Store
Store
Store
Store
Store
Store
Store
Store
Store
Store
Store
Store
Store
Store
Store
Store
Store
"'----
Base Address Register
Registers
A-Register
A Conditional
A Conditional on Q
AQ-Register
9-bit Bytes of A-Register
9-bit Bytes of Q-Register
Instruction Counter Plus 1
I nstruction Counter Plus 2
6-bit Characters of A-Register
6-bit Characters of Q-Register
Indicator Register
Q-Register
Timer Register
Index Register n in Upper
Zero
I ndex Register n in Lower
7-16
DZ51-00
,
/'
FI XED-POI NT I NSTRUCl'I ONS
FI XED-POI NT I NSTRUCl'I ONS
(
Data
ALR
ALS
ARL
ARS
LLR
LLS
LRL
LRS
QLR
QLS
QRL
QRS
Movement Shift
775
735
771
731
777
737
773
733
776
736
772
732
(0)
(0)
(0)
(0)
(0)
(0 )
(0 )
CO)
CO)
(0)
(0)
CO)
A-Register Left Rotate
A-Register Left Shift
A-Register Right Logical Shift
A-Register Right Shift
Long Left Rotate
Long Left Shift
Long Right Logical Shift
Long Right Shift
Q-Register Left Rotate
Q-Register Left Shift
Q-Register Right Logical Shift
Q-Register Right Shift
Fixed-Point Addition
if
ADA
ADAQ
ADL
ADLA
ADLAQ
ADLQ
ADLXn
ADO
ADxn
AOS
ASA
ASQ
ASxn
AWCA
AWCQ
075
077
033
035
037
036
02n
076
06n
054
055
056
04n
071
072
(0)
CO)
(0)
(0)
(0)
(0)
(O )
(0)
(0)
: SN is set OFF if positive, ON if negative. If all
digits are zero, the data is assumed positive and the SN flag is set
OFF, even when the sign is negative.
Z
Zero flag: initially set ON and set OFF whenever a sending string
character that is not decimal zero is moved into the receiving string.
BZ Blank-when-zero flag; initially set OFF and set ON by either the ENF or
SES micro operation. If, at the completion of a move (Ll exhausted),
both the Z and BZ flags are ON, the receiving string is filled with
character 1 of the edit insertion table.
(
(
7-43
DZ51-00
MICRO OPERATIONS
MICRO OPERATIONS
CRT
Change Table
10001 .1
EXPLANATION:
The edit insertion table is replaced by the string of eight
9-bit characters immediately following the CRT micro operation.
FLAGS:
None affected
NOTE:
C{!F) is not interpreted for this operation.
ENF
EXPLANATION:
End
Floating Suppression
00010
Bit 0 of IF (IFO) specifies the nature of the floating
suppression.
Bit 1 of IF (IF1) specifies if blank when zero option is used.
For IFO
=0
(end floating-sign operation):
If ES is OFF and SN is OFF, then edit insertion table entry 3
is moved to the receiving field and ES is set ON.
If ES is OFF and SN is ON, then edit insertion table entry 4
is moved to the receiving field and ES is set ON.
If ES is ON, no action is taken.
For 1FO
=1
(end floating currency symbol operation):
If ES is OFF, then edit insertion table entry 5 is moved to
the receiving field and ES is set ON.
If ES is ON, no action is taken.
For IFl = 1 (blank when zero): the BZ flag is set ON.
For IFl
FLAGS:
= a (no
blank when zero): no action is taken.
(Flags not listed are not affected)
ES - I f OFF, then set ON
BZ - If bit 1 of C{IF)
= 1,
7-44
then set ON; otherwise, unchanged
DZ51-00
MICRO OPERATIONS
MICRO OPERATIONS
IGN
EXPLANATION:
Ignore SOurce Characters
01100
IF specifies the number of characters to be ignored, where IF
o specifies 16 characters.
=
The next IF characters in the source data field are ignored and
the sending tally is reduced accordingly.
FLAGS:
INSA
(
None affected
Insert Asterisk on Suppression
01001
EXPLANATION:
same as INSB except that if ES is OFF, then edit insertion table
entry 2 is moved to the receiving field.
FLAGS:
None affected
NOTE:
If C(IF) = 9-15, an IPR fault occurs.
7-45
DZSI-OO
MItRO OPERATIONS
MICRO OPERATIONS
INSB
EXPLANATION:
Insert Blank on Suppression
01000 ]
IF specifies which edit insertion table entry is inserted.
If IF = 0, the 9 bits immediately following the INSB micro
operation are treated as a 9-bit character (not a MOP) and are
moved or skipped according to ES:
1 f ES
is OFF, then edit insertion table entry 1 is moved to
the receiving field. If IF = 0, then the next 9 bits are also
skipped. If IF is not 0, the next 9 bits are treated as a
MOP.
If ES is ON and IF = 0, then the 9-bit character immediately
following the INSB micro-instruction is moved to the
receiving field.
If ES is ON and IF F- 0, then IF specifies which edit
insertion table entry (1-8) is to be moved to the receiving
field.
FLAGS:
None affected
NOTE:
If C(IF)
INSM
EXPLANATION:
= 9-15,
an IPR fault occurs.
Insert Table Entry One Multiple
00001
IF specifies the number of receiving characters affected, where
IF = 0 specifies 16 characters.
Edit insertion table entry 1 is moved to the next IF (1-16)
receiving field characters.
FLAGS:
None affected
7-46
DZ51-00
MICRO OPERATIONS
MICRO OPERATIONS
(
INSN
EXPLANATION:
Insert On Negative
01010
IF specifies which edit insertion table entry is inserted. If
IF = 0, the 9 bits immediately following the INSN micro
operation are treated as a 9-bit character (not a MOP) and are
moved or skipped according to SN:
If SN is OFF, then edit insertion table entry 1 is moved to the
receiving field. If IF = 0, then the next 9 bits are also
skipped. If IF is not 0, the next 9 bits are treated as a MOP.
If SN is ON and IF = 0, then the 9-bit character immediately
following the INSN micro-instruction is moved to the receiving
field.
If SN is ON and IF # 0, then IF specifies which edit insertion
table entry (1-8) is to be moved to the receiving field.
(
FLAGS:
None affected
NOTE:
If C{IF)
INSP
(
= 9-15,
an IPR fault occurs.
Insert On positive
01011
EXPLANATION:
Same as INSN except that the responses for the SN values are
reversed.
FLAGS:
None affected
NOTE:
If C{IF)
= 9-15,
an IPR fault occurs.
.....
7-47
DZ51-00
MICRO OPERATIONS
MICRO OPERATIONS
LTE
EXPLANATION:
Load Table Entry
10000
IF specifies the edit insertion table entry to be replaced.
The edit insertion table entry specified by IF is replaced by
the 9-bit character immediately following the LTE micro
instruction.
FLAGS:
None affected
NOTE:
If C(IF) =
MFLC
EXPLANATION:
a or
C(IF) = 9-15, an Illegal Procedure fault occurs.
Move with Floating Currency Symbol Insertion
00111
IF specifies the number of characters of the sending field upon
which the operation is performed, where IF = 0 specifies 16
characters.
Starting with the next available sending field character, the
next IF characters are individually fetched and the following
conditional actions occur:
If ES is OFF and the character is zero, edit insertion table
entry 1 is moved to the receiving field in place of the
character.
If ES is OFF and the character is not zero, then edit
insertion table entry 5 is moved to the receiving field, the
character is also moved to the receiving field, and ES is set
ON.
If ES is ON, the character is moved to the receiving field.
7-48
DZ51-00
(
MICRO OPERATIONS
MICRO OPERATIONS
The number of characters placed in the receiving field is
data-dependent. If the entire sending field is zero, IF
characters are placed in the receiving field. However, if the
sending field contains a nonzero character, IF+l characters (the
insertion character plus the characters from the sending field)
are placed in the receiving field.
An IPR fault occurs when the sending field is exhausted before
the receiving field is filled. In order to provide space in the
receiving field for an inserted currency symbol, the receiving
field must have a string length one character longer than the
sending field.
When the sending field is all zeros, no
currency symbol is inserted by the MFLC micro operation and the
receiving field is not filled when the sending field is
exhausted. The user should provide an ENF (ENF,l2) micro
operation after a MFLC micro operation that has as its character
count the number of characters in the sending field. The ENF
micro operation is engaged only when the MFLC micro operation
fails to fill the receiving field; then, it supplies a currency
symbol to fill the receiving field and blanks out the entire
field.
FLAGS:
(Flags not listed are not affected)
ES -
NOTE:
If OFF and any of C{Y) is less than decimal zero, then ON;
otherwise, unchanged
Since the number of characters moved to the receiving string is
data-dependent, a possible IPR fault may be avoided by ensuring
that the Z and BZ flags are ON.
(
7-49
DZS1-00
MICRO OPERATIONS
MICRO OPERATIONS
Move with Floating Sign Insertion
EXPLANATION:
00110
IF specifies the number of characters of the sending field upon
which the operation is performed, where IF = 0 specifies 16
characters.
Starting with the next available sending field character, the
next IF characters are individually fetched and the following
conditional actions occur:
If ES is OFF and the character is zero, edit insertion table
entry 1 is moved to the receiving field in place of the
character.
If ES is OFF, the character is not zero, and SN is OFF: then
edit insertion table entry 3 is moved to the receiving
field. The character is also moved to the receiving field,
and ES is set ON.
If ES is OFF, the character is nonzero, and SN is ON; edit
insertion table entry 4 is moved to the receiving field; the
character is also moved to the receiving field, and ES is set
ON.
If ES is ON, the character is moved to the receiving field.
7-50
DZ51-00
/
(
MICRO OPERATIONS
MICRO OPERATIONS
The number of characters placed in the receiving field is
data-dependent. If the entire sending field is zero, IF
characters are placed in the receiving field. However, if the
sending field contains a nonzero character, IF+l characters (the
insertion character plus the characters from the sending field)
are placed in the receiving field.
IPR fault occurs when the sending field is exhausted before
the receiving field is filled. In order to provide space in the
receiving field for an inserted sign, the receiving field must
have a string length one character longer than the sending
field. When the sending field is all zeros, no sign is inserted
by the MFLS micro operation and the receiving field is not
filled when the sending field is exhausted. The user should
provide an ENF (ENF,4) micro operation after a MFLS micro
operation that has as its character count the number of
characters in the sending field. The ENF micro operation is
engaged only when the MFLS micro operation fails to fill the
receiving field: then, it supplies a sign character to fill the
receiving field and blanks out the entire field.
An
FLAGS:
(
(Flags not listed are not affected)
ES -
NOTE:
If OFF and. any of C{Y) is less than decimal zero, then ON;
otherwise, unchanged
Since the number of charact~rs moved to the receiving string is
data-dependent, a possible Illegal Procedure fault may be
avoided by ensuring that the Z and BZ flags are ON.
7-51
DZ51-00
MICRO OPERATIONS
MORS
EXPLANATION:
MICRO OPERATIONS
Move and OR Sign
01111
IF specifies the number of characters of the sending field upon
which the operation is performed, where IF = 0 specifies 16
characters.
Starting with the next available sending field character, the
next IF characters are individually fetched and the following
conditional actions occur:
If SN is OFF, the next I F characters in the source data field
are moved to the receiving data field and, during the move,
edit insertion table entry 3 is ORed to each character.
If SN is ON, the next IF characters in the source data field
are moved to the receiving data field and, during the move,
edit insertion table entry 4 is ORed to each character.
MORS can be used to generate a negative overpunch for a
receiving field to be used later as a sending field.
FLAGS:
None affected
7-52
DZSI-OO
(
MI CRO OPERATIONS
MICRO OPERATIONS
Move and Set Sign
EXPLANATION:
01110
IF specifies the number of characters of the sending field upon
which the operation is performed, where IF = 0 specifies 16
characters.
For MVE, starting with the next available sending field
character, the next IF characters are individually fetched and
the following conditional actions occur:
Starting with the first character during the move, a
comparative AND is made first with edit insertion table entry
3. I f the result is nonzero, the first character and the
rest of the characters are moved without further comparative
ANDs. If the result is zero, a comparative AND is made
between the character being moved and edit insertion table
entry 4 If that result is nonzero, the SN indicator is set
ON (indicating negative) and the first character and the rest
of the characters are moved without further comparative
ANDs. If the result is zero, the second character is treated
like the first. This continues until one of the comparative
AND results is nonzero or until all characters are moved.
(
For MVNE and MVNEX instructions, the sign (SN) flag is already
set and IF characters are moved to the destination field (MSES
is equivalent to the MVC instruction).
FLAGS:
(Flags not listed are not affected)
SN -
If edit insertion table entry 4 is found in C(Y-l), then ON:
otherwise, unchanged
(
7-53
DZ5l-00
MICRO OPERATIONS
MICRO OPERATIONS
Move SOurce Characters
MVC
EXPLANATION:
01101
IF specifies the number of characters to be moved, where IF
specifies 16 characters.
=0
The next I F characters in the source data field are moved to the.
receiving data field.
FLAGS:
None affected
Move with Zero Suppression and Asterisk
Replacement
MVZA
EXPLANATION:
00101
same as MVZB except that:
If ES is OFF and the character is zero, then edit insertion
table entry 2 is moved to the receiving field.
FLAGS:
(Flags not listed are not affected)
ES -
If OFF and any ofC(Y) is less than decimal zero, then ON;
otherwise, unchanged
7-54
DZ5l-00
./
(
MICRO OPERATIONS
MICRO OPERATIONS
Move with Zero Suppression and Blank Replacement
EXPLANATION:
00100
IF specifies the number of characters of the sending field upon
which the operation is performed, where IF = a specifies 16
characters.
Starting with the next available sending field character, the
next IF characters are individually fetched and the following
conditional actions occur:
If ES is OFF and the character is zero, then edit insertion
table entry 1 is moved to the receiving field in place of the
character.
If ES is OFF and the character is not zero, then the
character is moved to the receiving field and ES is set ON.
If ES is ON, the character is moved to the receiving field.
(
FLAGS:
(Flags not listed are not affected)
ES -
If OFF and any of C(Y) is less than decimal zero, then
ON; otherwise, unchanged
(
7-55
DZ51-00
M1 CRO OPERATIONS
MICRO OPERATIONS
Set Ene Suppression
SES
EXPLANATION:
Bit
0
00011
of IF UFO) specifies the setting of the
ES
switch.
Bit 1 of IF (IF1) specifies the setting of the b1ank-when-zero
option.
the
ES
flag is set OFF.
IF IFO
= 0,
= 1,
the
ES
flag is set ON.
If IF1
= 1,
the BZ flag is set ON.
If IFl
= 0,
no action is taken.
If IFO
FLAGS:
(Flags not listed are not affected)
ES -
Set by this micro operation
BZ -
If bit 1 of C(IF)
= 1,
7-56
then ON; otherwise, unchanged
DZ51-00
MICRO OPERATIONS
MICRO OPERATIONS
Micro Operation COde Assignment Map
Operation code assignments for the micro operations are shown in Table 7-6.
Dashes (---) indicate an unassigned code. Unassigned codes cause an Illegal
Procedure fault.
Table 7-6.
\B2 B3 B4
\
000
Micro Operation COde Assignment Map
001
010
011
100
101
110
111
-IHSB
IHSM
IHSA
ENF
INSN
SES
IHSP
MVZB
MVZA
MFLS
MFLC
IGN
MVC
MORS
LTE
MSES
CRT
\
BO Bl
00
01
10
11
\
-- --- -- --- --- ---- --- -- ---- -- ---
Terminating Micro Operations
The micro-operation sequence is terminated normally when the receiving string
length is exhausted. The micro-operation sequence is terminated abnormally
(with an IPR fault) if an attempt is made to move from an exhausted sending
string or to use an exhausted MOP string.
MICRO OPERATIONS EXAMPLES:
1
8
MVNE
. NOSC4
ADSC9
ADSC6
USE
MOPLST MI CROP
MICROP
MICROP
USE
MVNE
NDSC4
ADSC9
ADSC6
MVNE
NOSC4
ADSC9
ADSC6
16
32
EPACK,5,11,2
PIC S9(10)
MOPLST,0,9
PRTOUT+3,0,12 PIC Z(7).999DETOUR
(LTE,l},lH ,(MVZB,7),(SES,8)
(INSB),lH.,(MVC,3),(INSN)
1H-,(LTE,1},18 ,(MVZB,2),(MVC,1)
FPACK,5,11,2
MOPLST,0,9
PRTOUT+6,0,12
PIC
S9(10)
PIC
Z(7} .999-
SEQPAK,5,3,3
MOPLST+2,1,4
PRTOUT+1,3,3
PIC
999
PIC
ZZ9
7-57
DZ5l-00
VIRTUAL MEMORY INSTRUCTIONS
VIRTUAL MEMORY INSTRUCTIONS
VIRTUAL MEMORY INSTRUCT! ONS
These instructions support segmentation and paging in the virtual memory
environment. Except in the case of the CLIMB instruction, the format of these
instructions is the same as the other single-word instructions.
Descriptor Register Instructions
These instructions provide the capability of loading or storing a descriptor
register (DRB) with a new descriptor or modifying the descriptor currently
contained in DRn. The LODn instruction has a direct load option and a vector
option.
LODn
SDRn
STDn
67n (l)
lln (l)
OSn (1)
Load Descriptor Register n
save Descriptor Register n
Store Descriptor Register n
Pointer Register Instructions
LDPn
STPn
EPPRn
LDEAn
47n
4Sn
63n
61n
(l)
(1)
(1)
(1)
Load Pointer Register n
Store Pointer n
Effective Pointer to Pointer Register n
Load Extended Address n
,
\
Domain Transfer (CLIMB)
The ClJMB domain transfer instruction provides the software with a hardware
mechanism for transferring control from one software function to another with a
high level of software security. This 2-word instruction, described in detail
in Section 8, has four versions which perform the functions of call, return,
and co-routine invocations for intra- and inter-instruction segments and intraand inter-domain references.
.
CLIMB
713 (1)
Domain Transfer
7-58
DZSl-OO
PRJ VI LEGED I NSTRUCTI ONS
PRIVILEGED INSTRUCTIONS
PRIVI I..lGm I NSTRUCl'I ONS
Privileged instructions are executed in Privileged Master mcxie.
conditions must be met before the instructions can be executed:
Three
1. The master mcxie bit in the indicator register must be ON.
2. The privileged bit in the instruction segment register must be ON.
3. The housekeeping bit in the page table word for the page containing the
instruction must be ON; if the processor is in the working space zero
addressing mode, this bit is assumed ON.
If any of the above conditions does not exist upon the attempted execution of a .
privileged instruction, a Command fault occurs.
CLEAR ASSOCIATIVE MEMORY PAGES
532 (1)
(
Clear Associative Memory Pages
CLEAR CACHE
CCAC
all (1)
Clear cache
RB:;I S'l'BR LOAD
LDAS
LDDSA
LDDSD
LDPS
LDSS
LDWS
LPDBR
770
170
571
771
773
772
171
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Load
Load
Load
Load
Load
Load
Load
Argument Stack Register
Data Stack Address Register
Data Stack Descriptor Register
Parameter Segment Register
safe Store Register
Working Space Registers
Page Table Directory Base Register
7-59
DZ51-00
PRI VI LEGED I NSTRUCTI ONS
PRIVILEGED INSTRUCTIONS
Rm;I S'tBR S'l'ORE
SPDBR
STAS
STDSA
STDSD
STPDW
STPS
STPTW
STSS
STWS
151
750
150
551
155
751
157
753
752
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Store
Store
Store
Store
Store
Store
Store
Store
Store
Page Table Directory Base Register
Argument Stack Register
Data Stack Address Register
Data Stack Descriptor Register
PTWAM Directory Word
Parameter Segment Register
PTWAM Register
safe Store Register
Working Space Registers
MEMORY CDNTROL
LIMR
RIMR
SYS'l'BM
CIOC
DIS
LCON
LCPR
LDAT
LDT
LRMB
RCW
RICHR
RIW
RMID
RMR
RPAT
RRES
RSCR
SCPR
SICHR
SIW
SMID
SMR
SSCR
STTA
STTD
553 (0)
233 (0)
Load I nterrupt Mask Register
Read I nterrupt Mask Register
CDNTROL
015
616
016
674
336
637
712
250
156
412
273
270
611
231
413
452
154
451
272
271
057
553
550
(0)
(0)
(0)
(0)
(1)
(0)
(0)
(0)
(1)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(1)
(0)
(0)
(0)
(0)
(1)
(1)
Connect I nput/OUtput Olannel
Delay Until Interrupt Signal
Load Connect Table
Load Central Processor Register
Load Address Trap Register
Load Timer Register
Load Reserve Memory Base
Read Connect Word Pair
Restart IC History Register
Read Interrupt Word Pair
Read Memory ID Register
Read Memory Register
Run PATROL
Read Reserved Memory
Read System Control Register
Store Central Processor Register
Store IC History Register
Set Interrupt Word Pair
Set Memory ID Register
Set Memory Register
Set System Control Register
Store Test Address Registers
Store Test Descriptor Registers
7-60
/
DZ51-00
(
ALL MODE I NSTRUCTI ONS
ALL MODE I NSTRUCTI ONS
ALL MODE I KSTRUC'l'IOKS
All mode instructions may be executed in any processor mode.
EPAT
PAS
RSW
412 (1)
176 (1)
231 (0)
Effective Pointer and Address to Test
Pop Argument Stack
Read Processor Model Characteristics
(
7-61
DZ51-00
ES MODE I NSTRUCTI ONS
~
ES MODE I NSTRUCTI ONS
MODE I HS'I'RUC'l'IONS
ES mode instructions are valid only in the ES mode (ISR bit 24=1). AN IPR
fault occurs if an attempt is made to ~xecute these instructions in the NS
mode. Although these instructions are generated by some compilers in this
release, they are not supported by the GMAP assembler.
Except for the AARn, NARn, ARAn, and ARN instructions, all instructions are
valid in the ES mode. An IPR fault occurs if an attempt is made to execute
these four instructions in the ES mode.
Register-to-Register Instructions
Register to Register instructions known as "RR" type instructions are valid
only in the ES mode. An attempt to execute these instructions in the NS mode
results in an IPR fault. RR type instructions permit movement, arithmetic
operation, and shift of fixed-point data using the GXn, A and Q registers. An
attempt to execute any RR type instruction by the RPT, RPD, or RPL instructions
results in an IPR fault.
RR TYPE I HS'I'RUC'l'ION FORMAT
0
0
o0
1 1
o1
3 4
I I
Rl
~
NU
I
(J)
1 1
222
3 3
7 B
7 B 9
1 2
I
7-62
OP CODE
III
MBZ
3
5
I I
R2
DZ51-00
."\,,-~-
./
(
ES
MODE I NSTRUCTI ONS
ES MODE I NSTRUCTI ONS
Description
0-3
Rl
specifies a code indicating a register to be the
destination of the result. The allowable codes follow:
Register Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Result
IPR
IPR
IPR
IPR
IPR
A
Q
IPR
GXO
GX1
GX2
GX3
GX4
GX5
GX6
GX7
Should be set to O.
NU
Not used.
11-17
J
Used only in a shift instruction. Specifies the shift
number (immediate value). Must be 0 in all but shift
instructions.
18-27
OP
Operation code
28
I
Interrupt inhibit bit
29-31
MBZ
Must be zero or an IPR fault occurs
32-35
R2
Specifies a code that indicates a source register.
codes for this register are the same as for Rl.
4
-10
7-63
The
DZ51-00
ES MODE I NSTRUCTI ONS
NOTES:
ES MODE I NSTRUCTI ONS
1. Specifying a register code of 0000 in a shift instruction does
not result in an IPR fault.
2. If a register pair appears in an instruction specification, the
two registers are handled as linked. The list below indicates
the register codes to be assocciated with the register pair.
Register Code Result
0000
0001
0010
0011
0100
0101
0110
0111
100x
101x
110x
111x
IPR
IPR
IPR
IPR
IPR
A, Q
A, Q
I~R
GXO I
GX2 I
GX4 I
GX6,
GX1
GX3
GX5
GX7
where x means this bit is ignored by the hardware.
MOVEMEH'l' AND ARI TBME'l'I C I NSTRUCTI OKS
ADLR
ADRR
ANRR
CMRR
435 (1)
DVRR
ERRR
434 (1)
535 (1)
534 (1)
533 (1)
537 (1)
LDCR
431
LDDR
LDPR
LDRR
MPRR
MPRS
ORRR
433 (1)
SBLR
SBRR
437 (1)
432
(1)
(1)
430 (1)
530 (1)
531 (1)
536
(1)
436 (1)
Add Logical to Register
Add Register to Register
AND Register to Register
Compare Register to Register
Divide Register to Register
Exclusive OR Register to Register
Load Complement to Register
Load Double Register to Register
Load Positive Register to Register
Load Register to Register
Multiply Register-Pair to Register
Multiply Register-Single to Register
OR Register to Register
Subtract Logical to Register
Subtract Register to Register
7-64
DZ5l-00
(
ES MODE I NSTRUCTI ONS
sm P'T
GLLS
GLRL
GLRS
GLS
GRL
GRS
ES MODE I NSTRUCTI ONS
I HSTRUC'l'I OKS
466
465
464
462
461
460
(1)
(1)
(1)
(1)
(1)
(1)
GXn
GXn
GXn
GXn
GXn
GXn
Long Left Shift
Long Right Logic
Long Right Shift
Left Shift
Right Logic
Right Shift
Fixed-Point Instructions
The fixed-point instructions concern movement and arithmetic operations on data
in the GXn registers and memory. These instructions are valid only in the ES
mode. An attempt to execute these instructions in the NS mode results in an IPR
fault.
GLDD
GSTD
MPX
32n (1)
14n (1)
04n (1)
Load Double to GXn ( n = 0,2,4,6>
Store Double ·from GXn (n = 0,2,4,6)
Multiply GXn (n = 0,1, ••• ,7)
(
7-65
DZ51-00
TRANSFER I NSTRUCTI ONS
TRANSFER I NSTRUCTI ONS
TRANSFER I NS'I'RUCTI ONS
The program transfer instructions permit conditional and unconditional
transfers. TSXn also permits the instruction counter to be stored in index
registers xo through X7 COnditional transfers on zero, plus, and carry also
have the corollary transfers nonzero, minus, and no carry. The transfers on
overflows and underflows are made to maskable fault routines. If the normal
fault routine is masked, transfer is optional. As described in the individual
descriptions in Section 8, the ISR and S~D(IS) are affected by transfer of
control instructions.
Conditional Transfer
TEO
TEU
TMI
TMOZ
TNC
TNZ
TOV
TPL
TPNZ
TRC
TRCTn
TRTF
TRTN
TTF
TTN
TZE
614
615
604
604
602
601
617
605
605
603
54n
601
600
607
606
600
(0)
(0)
(0)
(1)
(0 )
(0)
(0)
(0)
(1)
(O)
(1 )
(1)
(1)
(o)
(1)
(0)
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
on
on
on
on
on
on
on
on
on
on
on
on
on
on
Trans.f~r on
Transfer on
Exponent Overflow
Exponent Underflow
Minus
Minus or Zero
No carry
Nonzero
Overflow
Plus
Plus and Nonzero
carry
Count
Truncation Indicator OFF
Truncation Indicator ON
Tally Runout Indicator OFF
Tally Runout Indicator ON
Zero
unconditional Transfer
RET
TRA
TSS
TSXn
630
710
715
70n
(0 )
(0)
(0)
(0)
Return
Transfer Unconditionally
Transfer after Setting Slave
Transfer and Set Index Register n
7-66
DZ51-00
(
MISCELLANEOUS INSTRUCTIONS
Ml ~LLANEOUS I NSTRUCTI ONS
Xl SCEI..I..AHmUS I HS'l'RUC'l'I ONS
Option Register Instructions
LOO
STO
172 (1)
152 (1)
Load Option Register
Store Option Register
Binary-'1'o-1O> Conversion
The Binary to Binary-Ceded-Decimal (BCD) instruction converts the magnitude of
a 33-bit or smaller binary number to its decimal equivalent in BCD form. The
conversion is made automatically, one decimal digit per instruction execution,
using previously stored conversion constants. The BCD form of the converted
number is readily available for further operations.
BCD
505 (0)
Binary-to-BCD Convert
Execute Instructions
(
The Execute and Execute Double (XEC and XED) instructions allow remote
instructions to be executed singly or in pairs. (XED executes only in NS
mode.) A program will continue sequentially after the XEC or XED instructions
are executed, as long as the referenced instructions do not alter the
instruction counter. If a referenced instruction affects the instruction
counter, a program transfer occurs.
XEC
XED
716 (0)
717 (0)
Execute
Execute Double
GraV-TO-B inary-Gonvers ion
The Gray-to-Binary (GTB) instruction converts a 36-bit word containing data in the
Gray code (for example, coded analog information from an analog-to-digital input
device) to its binary equivalent in only one execution of the instruction. This
instruction enhances the use of the information system in real-time applications,
such as telemetry. (This instruction executes in NS mode only.)
GTB
774 (0)
Gray-to-Binary Convert
Programmed Fault
DRL
NNE
002 (0)
001 (0)
Derail
Master Mode Entry
7-67
DZ5l-00
MI SCELLANEOUS I NSTRUCTI ONS
MI SCELLANEOUS I NSTRUCTI ONS
No Operation
NOP
PULS1
PULS2
SYNC
011 (0)
012 (0)
013 (0)
014 (0)
No Operation
Pulse One
Pulse Two
Gate Synchronize
Repeat Instructions
The RPT and RPD instructions permit execution of the next one or two
instructions a selected number of times according to program requirements; they
are especially useful for operating upon sequential lists in memory. (The
repeat instructions execute only in NS mode.) For example, if RPT is used with
any of several compare instructions to search a list, termination occurs when a
"hit" is made according to conditions specified in the RPT instruction. The
"hit" causes transfer to the next sequential instruction.
RPT
560 (0)
500 (0)
520 (0)
Pointer
And
LPL
467 (1)
447 (1)
RPD
RPL
SPL
Repeat Double
Repeat Link
Repeat
Length Instructions
Load Pointer and Length
Store Pointer and Length
7-68
DZ5l-00
CODING LIMITATIONS
COOl NG LI MI TATI ONS
CDDIBG LIMITATIONS
Supplementary specification items and notes relating to the software that
operates in the DPS 8000 is provided below.
1. Result of Fault Detection in the MLR/MRL instruction
When an SCLI/SCL2/BND fault is detectd in the MLR/MRL instruction, the
last several words (up to four words) preceding the fault may not be
stored into memory.
2. Tally Runout Indicator
If any instruction involving a tally word causes the tally count to be
zero and sets the tally runout indicator to OFF, and a page fault
subsequently occurs in this execution of this instruction, the value
of the tally runout indicator in the safe store frame will represent
the state of the indicator prior to the instructions. This permits
the instruction to be retried. The value of the tally runout in the
indicator register will indicate OFF.
3. Interrupt and Fault Entry Descriptor Locations
The software-visible, fixed absolute memory locations for the
interrupt and fault entry descriptors are defined by firmware values.
These locations may be altered corresponding to the ECS firmware
loaded into a CPU.
The current entry descriptor locations are as follows:
Entry Descriptors
Word Location
Interrupt
308 - 318
Fault
328 - 338
System Entry (PMME)
348 - 358
Backup Fault
408 - 418
The word location range available for these entry descriptors is
0-778.
(
7-69
DZ5l-00
CODING LIMITATIONS
CODING LIMITATIONS
4. Timer Related Instructions
Instructions which store the timer register affect this value because
the timer is stopped for one cycle. These instructions are
STT
CLIMB
DIS when PATROL is enabled
I
./
7-70
DZ51-00
(
SICrIOH 8
MACHI HE I NSTRUC'l'ION DESCRIPTIONS
FORMAT OF I NS'l'RUC'l'I ON DBSCRI PTI ON
Each instruction in the repertoire is described in this section.
descriptions are presented in the formats shown below.
The
The format for all instructions except vector instructions follows:
I
MNEMONIC
INSTRUCTION NAME
OPCODE
FORMAT:
Figure or figure reference
COD! NG FORMAT:
Text
PROCESSOR MODE:
Text
SUMMARY:
Text and/or bit transfer equations
EXPLANATION:
Text
ILLEGAL ADDRESS
MODI F! CATIONS:
Text
I LLEGAL REPEATS:
Text
INDICATORS:
Text and/or logic statements
NOTE:
Text
EXAMPLE(S):
I f applicable
Line 1: MNEMONIC, INSTRUCTION NAME, OPCODE
This line has three parts that contain the following:
1. MNEMONIC -- The mnemonic code for the operation field of the assembler
statement. The assembler recognizes this character string value and maps
it into the appropriate binary pattern when generating the actual object
code.
8-1
DZ51-00
)
2. INSTRUCTION NAME -- The name of the machine instruction from which the
mnemonic was derived.
3. OPCODE -- The octal value of the operation code for the instruction. A 0
or a 1 in parentheses following an octal code indicates whether bit 27
(opcode extension bit) of the instruction word is OFF or ON.
Line 2:
FORMAT
The layout and definition of the subfields of the instruction word or words
either as a figure or as a reference to a figure.
Line 3: CODING FORMAT
The format to be used in coding the instruction.
Line 4:
OPERATING MODES
The modes in which the processor should be to execute the instruction.
to Sectionl, "Operating Modes".)
Line
5:
(Refer
SUMMARY
The change in the state of the processor affected by the execution of the
instruction described in a short, symbolic form. If reference is made to the
state of an indicator, it is the state of the indicator before the instruction
is executed.
Line 6:
EXPLANATION
In instances where more details are needed than supplied in a concise summary,
this section describes how the operation functions.
Line 7:
ILLEGAL ADDRESS MODIFICATIONS
A list of those modifiers that cannot be used with the instruction.
Procedure fault occurs when illegal address modification is used.
Line 8:
A
An Illegal
ILLEGAL REPEATS
list of the repeat instructions that cannot be used with the instruction.
Line 9:
ILLEGAL EXECUTES
A list of operations or conditions that are prohibited with the instruction.
8-2
DZSl-OO
Line 10: INDICATORS
A list of only those indicators whose state can be changed by the execution of
the instruction. In most cases, a condition for setting ON as well as one for
setting OFF is stated. If only one of the two is stated, then the indicator
remains unchanged if the condition is not met. Unless stated otherwise, the
conditions refer to the contents of registers existing after instruction
execution.
Line 11:
NOTES
\
Notes regarding specific conditions, faults, and exceptions that affect the
operation of the instruction upon the data.
Line 12:
I
EXAMPLES
Any coding examples, if required for clarity.
ABBREVIATI ONS AND SYMBOLS
The following abbreviations and symbols are used in the descriptions of the
machine operations.
(
Symbol
Meaning
AM
Address register modification
AND
The Boolean connective AND
ARn
Address register
b
The original bit position within a 9-bit character
BOLR
Boolean results (4 bits). The BOLR field is used in bit string
operations. The bits specify the resultant octal value for four
combinations of two input sources.
:(BOLR):
A Boolean operation defined by the BOLR field
c
The original character position within a data word of 9-bit
characters
C{
The contents of ( ).
n specifier
in operand descriptor (n
= 0,
1, ••• ,7)
C(string l} represents the contents of string
1
C(R}
The complete contents of register R
C(R} i
The contents of bit i of register R
C{R)i-j
The contents of bits i through j of register R
(.
8-3
DZ5l-00
j
Symbol
Meaning
CN
The original character number within the data word referred to by
the original data word address
CS
Character set definition, EBCDIC (0) or ASCII (1)
DR
Displacement register (bits 32-35)
F
Bit value specifier (0 or 1) for bit string fill. Used when
combining/comparing a short bit string with a long bit string to
make the shorter string appear to be the same length as the longer
string.
FILL
A character used when moving or comparing a short string of
characters to a longer string to make the short string appear to be
the same length as the longer string. (See note under MASK.)
GKn
General Index Registers 0,1, ••• 7 (ES Mode only)
I
Program interrupt inhibit bit
ID
Indirect operand descriptor indicator
L
The actual length of the character or bit string, as determined by
the register or length (RL) bit in the modification field and by N
LOCSYM
A symbol representing either the address of the operand or the
displacement from a base
MASK
Bit pattern used in an instruction word. Each 1 bit in the mask
causes that bit position in the two characters not to enter into
the comparison (coded as octal digits).
.
NOTE: FILL and MASK are 9-bit fields. When using 6- or 4-bit
characters, the character must be right-justified in the
9-bit field.
MBZ
Must be zero
MFn
Modification field n describing address modification to be
performed in operand descriptor n:
MFl
MF2
MF3
= modification field 1 (bits 29-35)
= modification
specified
= modification
field 2 (bits 11-17), if operand descriptor 2 is
field 3 (bits 2-8), if operand descriptor 3 is
specified
N
Either the number of characters or bits in the data string or a
4-bit code (bits 32-35) that specifies a register that contains the
number of characters or bits. (See Labove.)
8-4
DZ5l-00
(
Symbol
Meaning
n
Register designation for those instructions that require a register
specification to determine operation code.
NS
If 0, there is no effect upon the operation of the instruction.
If 1, there is no effect upon the instruction unless TN = 0 and SX
= 00 or 11, in which case (output is supposed to be overpunched
sign) the appropriate ~verpunched sign character will not be placed
in the specified field. Instead, the appropriate numeric (0-9)
character will be placed in the specified field, independent of
whether the calculated sign would have been plus or minus. This
results in a no sign output. For other values of TN and SX, the NS
bit is ignored. This procedure applies to both EBO>IC and ASOI.
This usage of NS is not to be confused with NS used for Normal
segmentation mode.
OP CODE
Operation code field
OR
The Boolean connective OR (symbol
P
V)
If P = 0, positive signed 4-bit results are stored with octal 14 as
the plus sign
If P = 1, positive signed 4-bit results are stored with octal 13 as
the plus sign
R1,R2
General index registers, specified in ES mode only for register to
register instructions
R'1
The ith bit, character, or byte position of R
Ri-j
Bit, character, or byte positions i through j of R
RD
Rounding numeric indicator flag:
If RD = 0, no rounding takes place
If RD = 1, rounding takes place as the final operation: the stored
result is incremented by 1 at the least significant
character if the most significant character of the
truncated part is 5 or more
REG
Address modification register selection for R-type modification of
the operand descriptor address field
RI
Distance between elements of vector data in vector operations
RL
Register or length indicator
RM
Register modification
RN
The register that holds the number of elements of vector data in
vector operations
S
Sign and decimal type
8-5
DZ5l-00
j
Symbol
Meanina
SF
Scaling factor
SX
Sign and scaling
T
Truncation fault enable indicator:
If T
If T
= 0,
= 1,
the truncation fault is disabled
the truncation fault is enabled
TA
A code that defines the type of alphanumeric character used in the
data
TAG
Tag field used to control address modification (bits 30-35)
TN
A code that defines which type of numeric character is used in the
data
TR
Timer register
VA
Virtual address
Xn
Index Registers (0,1, ••• 7)
XOR
The Boolean connective EXECLUSIVE OR
y
A
29
15-bit displacement from the address register address (with bit
= 1) or 18-bit address (with bit 29 = 0)
Y
The effective word address (18 bits for NS mode and 34-bits for ES
mode) to the word level of the designated instruction
Y-pair
A symbol denoting that the effective address Y designates a pair of
main memory locations (72 bits) with successive addresses, the
smaller address being even. When Y is even, it designates the pair
(Y, Y+l); when Y is odd, it designates the pair (Y-l, y). The main
memory location with the smaller (even) address contains the most
significant part of a double-word operand or the first of a pair of
instructions.
.
YC
The effective address for character data
YCB
The effective address for bit string data
Z
The temporary pseudo-result of a nonstore comparison operation
-->
Replace(s)
..
Is compared with •
C(R) :: C(Y) means
C(R) - C«Y)-->C(Z), C(R) and C(Y)
unchanged invisible result C(Z) sets
zero, negative and carry indicator as
indicated in the instruction descriptions
(~,
I
\..
;"
"--.--,'"
8-6
DZ51-00
Symbol
(
Meaning
Not equal
Sigma sign indicates summary.
>
CDMMON ATTRI BOTES OF I KS'l'RUC'l'IOKS
Illegal Modification
If an illegal modifier is used with any instruction, an illegal procedure fault
with a subcode class of illegal modifier occurs.
Parity Indicator
The parity indicator is turned ON at the end of a main memory access that has
incorrect parity.
I KS'l'RUC'l'ION WORD FORMATS
Single-Word Instructions
(
The single-word instruction format is displayed in Figure 8-1.
o 000
o1 2 3
LOCSYM
AR# S
7 8
3
5
Td
I AR
LOCSYM
1
3 3
1 2
9 0
Tm
OP CODE
TAG
Figure 8-1.
CODING FORMATS:
2 2 2 3
1 1
7 8
8
Single-Word Instruction Format
16
32
OPCODE LOCSYM,RM,AM
OPCODEn LOCSYM,RM,AM
OPCODE n,LOCSYM,RM,AM
8-7
Cn = 0,1, ••• ,7)
DZ51-00
EXAMPLES:
AB
LDA
AB,X3,AR2
Instruction with no index
involved
LDXl
AB,X3,AR2
Format 1: instruction
with index involved
LDX
1,AB,X3,AR2
Format 2: instruction
with index involved
OCT
o
= 1.
AR#
-
Address register number, if bit 29
S
-
Sign bit, if bit 29
LOCSYM
-
Address field: bits 0-17 or bits 3-17, depending on the state of
bit 29
= 1.
OP CODE -
10-bit operation code field stated as a 3-digit octal number
followed by the content of bit 27 (0 or 1) in parentheses
I
-
Program interrupt inhibit bit
AR
-
Address register bit. If bit 29 = 1, use address register
specified in bits 0, 1, and 2 of Y field for address modification.
Bit 3 (sign) is then extended to bits 0, 1, and 2. If bit 29 = 0,
no address register modification is performed.
TAG
-
Tag field: used to control address modification.
Tm Td -
(Bits 30-31) Type of address modification.
(Bits 32-35) Index Register or modification variation
designator
The Repeat (RPT), Repeat Double (RPD) , and Repeat Link (RPL) machine
instructions and variations of these instructions use special formats and have
special tally, terminate, repeat, and other conditions associated with them.
(The repeat instructions execute in NS mode only.) There is no address
modification for the Repeat instructions. Address modifications for the
repeated instructions are limited to Rand RI with designators specifying
Xl, ••• ,X7/GXl, ••• ,GX7. XO/GXO is used to control terminate conditions and
tally. Address Register (AR) modification is also permitted.
The Character Move and Translate instructions (MTR and MTM) use a variation of
the single-word instruction format in which two registers are specified.
Indirect words, used for address modification, have the same general format as
the instruction words; however, the fields are used in a somewhat different
way.
8-8
DZSl-OO
Nulti word I nstruct ions
(
Alphanumeric, numeric, and bit string multiword instructions have the general
machine format described in Figure 8-2.
o 0 011
58901
000
012
F
MF3 or
P
MF2 or
FILL
0
111
478
I
D
REG
MFI
FILL
OP CODE
T R
~ I~ I~
222 3 3 3 3
789 0 1 2 5
~ I~ I~ I REG
I
~ I~ I~ IREG
The number of words and fields within the descriptor words will vary by
instruction, but use the following general format.
o
17 18
35
Operand Descriptor or Indirect Pointer to
Operand Descriptor 1
Operand Descriptor or Indirect Pointer to
_______________~ra!!d_~s£riPior ~ ____________ _
Operand Descriptor or Indirect Pointer to
.
_______________~ra!!d_~s£rmor J ____________ _
Figure 8-2.
Multiword Instruction Format
The fields in the instruction word are defined below. The data fields in the
operand descriptor words and the indirect word are discussed in detail in
Section 5 under Operand Descriptors and additional detail including coding
formats, is provided in Section 7 under Multiword Instructions.
F
-
Bit value specifier for bit string fill
P
-
Plus sign indicator (octal 13 or 14)
FILL
-
Fill character specifier
T
-
Truncation fault enable indicator
RD
-
Rounding indicator
MFI
-
Modification field 1 (bits 29-35) denotes address modiflcation to
be performed for operand descriptor 1. (see "Multi word Modification
Field" in Section 7.)
MF2
-
Bits 11-17 describe address modification to be performed on this
operand for operand descriptor 2
8-9
DZ51-00
MF3
-
Bits 2-8 describe address modification to be performed on this
operand for operand descriptor 3
OP CODE -
10-bit operation code field. Octal representation consisting of
three octal digits followed by the content of bit 27 (1) in
parentheses.
I
-
Program interrupt inhibit bit
AR
-
Address register indicator
RL
-
Register containing length indicator
ID
-
Indirect operand descriptor indicator
REG
-
Type of register modification (A, AU,
Q, QU,
IC, DU,
XB/GXg)
Address Register Special Arithmetic Instructions
These instructions provide the capability for replacing, adding to, or
subtracting from the contents of an address register on either a word,
character, or bit address basis. The operation is register-to-register, with
no memory fetch involved.
The special arithmetic instructions have the format shown in Figure 8-3:
/
000
Figure 8-3.
333
3
OP CODE
y
Address Register Special Arithmetic
Instruction Format
Selects address register to be altered
AR#
S
222
1 1
-
Sign bit
y
Used as a word displacement (no character or bit position included)
along with the contents specified in the DR field to alter the
contents of the specified address register. Bit 3 provides
negative or positive word displacement.
OP CODE -
lO-bit operation code field. Octal representation consisting of
three octal digits followed by the content of bit 27 (1) in
parentheses.
I
-
Program interrupt inhibit bit
8-10
DZ51-00
AR
-
Address register bit. If bit 29 = 1, the sum of the DR (in
characters, words, or bits) and the y field (in words) are added to
or subtracted from the contents of the AR specified in bits 0-2. If
bit 29 = 0, the described sum or its two's complement is loaded
into the AR for addition or subtraction, respectively. If the
mnemonic is coded with X (for example, AWDX), bit 29 is forced to
zero.
MHZ
-
Bits 30-31 must be zero. The operand length is contained in the
register specified by DR.
(
Displacement register. Specifies which register contains the
displacement value. The register codes and register lengths are
the same as those used in MF fields except that IC modification is
illegal.
DR
The operations for adding a value to the contents of an address register
proceed identically as with effective operand address preparation from an
operand descriptor, with the final results stored in the specified address
register. The subtract operation differs only in that the contents of the
register specified by the code in the DR field are first added to the y field.
This result is then subtracted from the actual contents of the address register
or from the implied zero contents and the result is placed in the address
register. The codes for DU, DL, and IC are illegal for the DR field and cause
an IPR fault.
No indicators are affected by these instructions.
Character Move To/From Register Instructions
Two instructions permit moves of one, two, three, or four 9-bit characters from
a memory location to a register or from a register to memory. These
instructions have the format shown in Figure 8-4.
o
1°
1 1
3
2 2 2
Not Used
Figure 8-4.
RECR
1 1
-
Character Move To/From Register Instruction Format
Specifies the register to which characters are moved (MTR), or from
which characters are moved (MTM). (Refer to MTR/MTM instructions.)
OP CODE -
10-bit operation code field. Octal representation consisting of
three octal digits followed by the content of bit 27 (1) in
parentheses.
I
Program interrupt inhibit bit
-
(~
8-11
DZ51-00
AR
-
Address register indicator
RL
-
This field is ignored
ID
-
Indirect operand descriptor indicator
REG
-
Type of register modification (A, AU, Q, QU, IC, DU, xnJGXn)
These instructions move one, two, three, or four 9-oit characters from (MTR) or
to (MTM) a memory location to or from a register specified by the RECR field.
Register-to-Register I DStructions
Register to Register instructions known as "RR type instructions are valid
only in the ES mode. An attempt to execute these instructions in the NS mode
results in an IPR fault. RR type instructions permit movement, arithmetic
operation, and shift of fixed-point data using the GXn, A and Q registers. An
attempt to execute any RR type instruction by the RPT, RPD, or RPL instructions
results in an IPR fault. The format for register to register instructions is
shown in Figure 8-5.
It
a aa
a 34
I
Rl
I
a1
NU
I
Figure 8-5.
222
789
1 1
7 8
1 1
(J)
I
OP CODE
3 3
1 2
3
5
II I I R2 I
MBZ
.
Register To Register Instruction Format
Bits Field DescriQtion
a - 3 Rl
A code indicating a register to be the destination of the
result. The allowable codes follow:
Register Code Result
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
IPR
IPR
IPR
IPR
IPR
A
Q
IPR
GXO
GX1
GX2
GX3
GX4
GX5
GX6
GX7
8-12
,/
DZ5l-00
'~~
~'\
,
(
4
-10
NU
Not used.
Should be set to O.
11-17 J
Used only in a shift instruction. Specifies the shift number
(immediate value). Must be 0 in all but shift instructions.
18-27 OP
Operation code
28
Interrupt inhibit bit
I
29-31 MHZ
Must be zero or an IPR fault occurs
32-35 R2
A code indicating the source register.
register are the same as for Rl.
NOTES:
1. Specifying a register code of 0000 in a shift instruction
does not result in an IPR fault.
The codes for this
2. If a register pair appears in an instruction specification,
the two registers are handled as linked. The list below
indicates the register codes to be assocciated with the
register pair.
Register Code Result
(
0000
0001
0010
0011
0100
0101
0110
0111
100x
101x
110x
l11x
IPR
IPR
IPR
IPR
IPR
A, Q
A, Q
IPR
GXO,
GX2,
GX4,
GX6,
GXl
GX3
GX5
GX7
where x means this bit is ignored by the hardware.
8-13
DZ51-00
I NS'l'RUCTI ON REPER'l'OI RE
The processor interprets a 10-bit field of the instruction word as the operation
code. This field size yields 1024 possible instructions codes of which over half
are implemented.
Detailed on the following pages are the processor instructions and operation codes
sorted alphabetically on the mnemonic by function.
8-14
DZ51-00
!
/
A4BD
A4BDX
A4BD
A4BDX
A4BD
A4BDX
FORMAT:
CODING FORMAT:
Add 4-Bit Displacement to Address Register
502 (1)
Special arithmetic instruction format (see Figure 8-3)
1
8
{A4BD )
{A4BDX)
16
word displacement,R,AR
When the mnemonic is coded with an "X" (A4BDX), bit 29 is
forced to zero.
OPERATING MODES:
Any
EXPLANATION:
NS Mode
The count of 4-bit characters contained in the register
specified by the DR field is effectively divided by 8,
producing a word count and a character count. The word count
is added to the y field (bit 3 extended).
If bit 29 = 0, this sum replaces bits 0-17 of the specified
AR, with the character count (from the divide) translated
into bit string representation and replacing bits 18-23 of
AR.
If bit 29 = 1, the sum of the word count (from the divide)
and y field is added to bits 0-17 of the specified AR. The
CHAR and BIT portions (bits l8-23) of the specified AR are
forced to point to a 4-bit character boundary in bit string
representation. The resulting character count is added to
the character count from the divide operation, with the
result being translated back into bit string representation.
These formed values for the WORD, CHAR, and BIT fields are
stored in bits 0-23 of the specified AR. With this addition,
carry from the CHAR field is transferred to the WORD field.
ES Mode
The count of 4-bit characters contained in the register
specified by the DR field is effectively divided by 8,
producing a word count and a character count. The word count
is added to the y field (bit 3 extended).
8-15
DZ51-00
A4BD
A4BDX
A4BD
A4BDX
If bit 29 = 0, this sum replaces bits 0-29 of the specified
AR, with the character count (from the divide) translated
into bit string representation and replacing bits 30-35 of
AR.
IF bit 29 = 1, the sum of the word count (from the divide)
and y field is added to bits 0-29 of the specified AR. The
CHAR and BIT portions (bits 30-35) of the specified AR are
forced to point to a 4-bit character boundary. The resulting
character count is added to the character count from the
divide operation, with the result translated back into bit
string representation. These formed values for the WORD,
CHAR, and BIT fields are stored in bits 0-35 of the specified
AR. With this addition, carry from the CHAR field is
transferred to the WORD field.
Effectively, the two bit string representations are added and
the result is translated back to a format allowing 2 bits to
represent the characters and 4 bits to represent bits. Any
overflow of the 2 bits increments the address field and the
4-bit field is handled as mod-9. Any overflow of the 2-bit
field increments the character (2-bit) field.
ILLEGAL ADDRESS
MODIFICATIONS:
When DU, DL, and IC are specified in the DR.
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
8
16
EAX3
A4BDX
A4BD
9
2,3,5
0,3,5
AR5 octal contents AR5 octal contents -
0 0 0 0 0 3 0 5
0 0 0 0 0 4 2 0
EAX4
A4BDX
EAX5
A4BD
6
0,4,3
AR3 octal contents -
0 0 0 0 0 0 6 0
AR3 octal contents -
0 0 00 0 5 6 5
9
4,5,3
8-16
DZ51-00
A6BD
A6BDX
A6BD
A6BDX
A6BD
A6BDX
FORMAT:
CODING FORMAT:
Add 6-Bit Displacement to Address Register
501
(1)
Special arithmetic instruction format (see Figure 8-3)
1
8
16
{A6BD }
{A6BDX} word disp1acement,R,AR
When the mnemonic is coded with an X (A6BDX), bit 29 is
forced to zero.
OPERATING MODES:
Any
EXPLANATION:
NS Mode
The count of 6-bit characters contained in the register
specified by the DR field is effectively divided by 6,
producing a word count anp a character count. The word count
is added to the y field (bit 3 extended).
If bit 29 = 0, this sum replaces bits 0-17 of the specified
AR, with the character count (from the divide) being
translated into bit string representation and replacing bits
18-23 of AR.
If bit 29 = 1, the sum of the word count (from the divide)
and y field is added to bits 0-17 of the specified AR. The
CHAR and BIT portions (bits 18-23) of the specified AR are
forced to point to a 6-bit character boundary. The resulting
6-bit character count is added to the character count from
the divide operation, with the result being translated back
into bit string representation. These formed values for the
WORD, CHAR, and BIT fields are stored in bits 0-23 of the
specified AR. With this addition, carry from the CHAR field
(when carry + character count> 5) is transferred to the WORD
field.
8-17
DZ5l-00
i
A6BD
A6BDX
A6BD
A6BDX
ES Mode
The count of 6-bit characters contained in the register
specified by the DR field is effectively divided by 6,
producing a word count and a character count. The word count
is added to the y field (bit 3 extended).
If bit 29 = 0, this sum replaces bits 0-29 of the specified
AR, with the character count (from the divide) translated
into bit string representation and replacing bits 30-35 of
AR.
If bit 29 = 1, the sum of the word count (from the divide>
and y field is added to bits 0-29 of the specified AR. The
CHAR and BIT portions (bits 30-35) of the specified AR are
forced to point to a 6-bit character boundary. The resulting
6-bit character count is added to the character count from
the divide operation, with the result translated back into
bit string representation. These formed values for the WORD,
CHAR, and BIT fields are stored in bits 0-35 of the specified
AR. With this addition, carry from the CHAR field (when
carry + character count> 5) is transferred to the WORD
field.
I LLEGAL ADDRESS
MODIFICATIONS:
When DU, DL, or IC are specified in DR.
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None Affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modification is used.
EXAMPLES:
1-
(Applies to NS mode only)
8
16
32
EAX2
A6BDX
A6BD
8
3,2,6
2,2,6
AR6 octal contents
AR6 octal contents
-
EAX4
A6BDX
A6BD
15
0,4,7
2,4,7
AR7 octal contents
AR7 octal contents
- o 000
- o 000
8-18
- o 000 0 423
o0
000 746
0 2 4 0
0 7 0 0
DZ5l-00
A9BD
A9BDX
A9BD
A9BDX
A9BD
A9BDX
FORMAT:
CODING FORMAT:
Add 9-Bit Displacement to Address Register
SOD (1)
Special arithmetic instruction format (see Figure 8-3)
1
8
16
{A9BD }
{A9BDX} word displacement,R,AR
When the mnemonic is coded with an X (A9BDX), bit 29 is forced to
zero.
(/
OPERATING MODES:
Any
EXPLANATION:
NS Mode
The count of 9-bit characters contained in the register specified
by the DR field is effectively divided by 4, producing a word
count and a character count. This word count is then added to
the y field (bit 3 extended).
If bit 29 = 0, the resulting sum of the word addresses and the
character count (from the divide operation) replaces bits 0-19 of
the specified AR.
If bit 29 = 1, the resulting sum of the word addresses is added
to bits 0-17 of the specified AR and the character count (from
the divide operation) is added to bits 18-19 of C(AR). These
results are then stored in bits 0-19 of the specified AR. In
either case, bits 20-23 of the specified AR are zeroed. carry is
transferred from bit 18 to bit 17 with this addition.
ES Mode
The count of 9-bit characters contained in the register specified
by the DR field is effectively divided by 4, producing a word
count and a character count. This word count is then added to
the y field (bit 3 extended).
If bit 29 = 0, the resulting sum of the word addresses and the
character count (from the divide operation) replaces bits 0-31 of
the specified AR.
(
8-19
DZ51-00
A9BD
A9BDX
A9BD
A9BDX
If bit 29 = 1, the resulting sum of the word addresses is
added to bits 0-29 of the specified AR and the character
count (from the divide operation) is added to bits 30-31 of
C(AR). These results are then stored in bits 0-31 of the
specified AR. In either case, bits 32-35 of the specified AR
are zeroed. carry is transferred from bit 30 to bit 29 with
this addition.
I LLEGAL ADDRESS
MODIFICATIONS:
When DU, DL, or IC are specified in the DR.
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modification is used.
(Applies to NS mode only)
EXAMPLES:
1
8
16
32
!AX1
A9BDX
A9BD
6
2,1,2
2,,2
AR2 octal contents
AR2 octal contents
-
EAX2
A9BDX
A9BD
15
4,2,6
0,2,6
AR6 octal contents
AR6 octal contents
-
8-20
-
o0
o0
0 0 0 34 0
0 0 054 0
- o0
0 007 6 0
0 0 1 340
o0
DZ51-00
(-
AARn
AARn
Alphanumeric Descriptor To Address Register !!
FORMAT:
56!! (1)
Single-word instruction format (see Figure 8-1)
CODI NG FORMAT:
1
8
MR.!!
16
LOCSYM, RM, AM
OPERATI NG MODES:
Any
SUMMARY:
For n = 0, 1, ••• or 7 as determined by op code
C(Y)0-17 --> C(ARn)0-17
C(Y)18-20 translated C(ARn)18-23
EXPLANATION:
The alphanumeric descriptor is fetched from the computed
effective address Y. The TA field, bits 21 and 22, is examined
to determine the type of data described. If the TA code
indicates 9-bit character data, bits 18 and 19 of the descriptor
CN field go to the corresponding bit positions of AR!! and zeros
fill bits 20-23 of ARn. If the TA code indicates 6- or 4-bit
character data, the descriptor CN field is appropriately
translated into bit string representation and goes to bits 18-23
of AR!!. In all cases, the word portion of the fetched descriptor
is placed in the word portion (bits 0-17) of ARn.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
ILLEGAL EXECUTES: If this instruction is executed in ES mode.
INDICATORS:
None affected
NOTES:
1. An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used or if the descriptor
TA field contains code 11.
(
8-21
DZ5l-00
AARn
AARn
2.
A:::, IPR fault occurs if descriptor CN field contains xxl for
TA = 00, or llx for TA = 01.
3.
An
IPR fault occurs if an attempt is made to execute this
instruction in the ES mode.
EXAMPLES: (Applies to NS mode only)
1
DESCR
8
16
32
AAR4
DESCR
load data string address into AR4
memory contents in octal
ADSC9
FLD1, 3 , 1
.
001023600001 - descriptor
AR4 octal contents - 0 0 1 0 2 3 6 0
8-22
DZS1-00
(
ABD
ABD
ABDX
ABDX
Add Bit Displacement to Address Register
ABD
ABDX
(1)
special arithmetic instruction format (see Figure 8-3).
FORMAT:
COOl NG
503
FORMAT:
8
1
16
{ABD }
{ABDX} word displacement,RM,AR
When the mnemonic is coded with an X (ABDX) , bit 29 is forced to
zero.
(
OPERATING MODES:
Any
EXPLANATION:
NS
Mode
The bit string count in the register specified in the DR field is
divided by 36. The quotient is taken as the word count and the
remainder is taken as the bit count. The word count is added to
the y field for which bit 3 of the instruction word is extended
and the sum is taken.
If bit 29=0, the sum is loaded into bits 0-17 of the specified
AR, and the character portion and the bit portion of the
remainder are loaded into bits 18-23 of the specified AR.
If bit 29=1, the sum is added to bits 0-17 of the specified AR.
The CHAR and BIT fields (bits 18-23) of the specified AR are
added to the character portion and the bit portion of the
remainder. WORD, CHAR and BIT fields generated in this manner
are loaded into bits 0-23 of the specified AR. with this
addition, carry from the BIT field (bit 20) and the CHAR field
(bit 18) is transferred (when BIT field >8, CHAR field >3).
8-23
DZSl-OO
ABD
ABDX
ABO
ABDX
ES Mode
The bit string count in the register specified in the DR
field is divided by 36. The quotient is taken as the word
count and the remainder is taken as the bit count. The word
count is added to the y field for which bit 3 of the
instruction word is extended and the sum is taken.
If bit 29=0, the sum is loaded into bits 0-29 of the
specified AR, and the character portion and the bit portion
of the remainder are loaded into bits 30-35 of the specified
AR.
If bit 29=1, the sum is added to the sign extended value of
bits 0-29 of the specified AR. The CHAR and BIT fields (bits
30-35) of the specified AR are added to the character portion
and the bit portion of the remainder. WORD, CHAR, and BIT
fields generated in this manner are loaded into bits 0-35 of
the specified AR. with this addition, carry from the BIT
field (bit 30) and the CHAR field (bit 32) is transferred
(when BIT field >8, CHAR field >3).
I LLEGAL ADDRESS
MODIFICATIONS:
When DU, DL, or Ie are specified in the DR
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
EXAMPLES:
1
(Applies to NS mode only)
8
16
32
EAX6
ABDX
ABD
85
7,6,2
2,6,2
AR2 octal contents AR2 octal contents -
0 0 0 0 1 1 2 4
0 00 0 1 5 5 0
EAXI
EAX2
ABDK
ABD
74
30
4,1,3
0,2,3
AR3 octal contents AR3 octal contents -
0 0 0 0 0 6 0 2
0 0 0 0 0 6 6 5
8-24
DZ51-00
(
AD2D
AD2D
202 (1)
Add Using Two Decimal Operands
AD2D
FORMAT:
o0
o1
001
890
1 1
7 8
1
1
0
a
Code
222
789
202(1)
MF2
Iploo------------OITIRDI
Op
II I
I
1 1 2 2
780 1
0
2
222
234
3
5 "
MF1
I
2 3
9 0
3
5
Y1
CN1 TN1 Sl
(
o
a
SF1
N1
Y1
AR#
1 1 2 2
780 1
0
2
222
234
2 3
9 0
3
5
Y2
CN2 TN2 S2
AR#
CODING FORMAT:
Y2
SF2
N2
..
1
8
16
AD2D
MF1),(MF2),RD,P,T
LOCSYM,CN,N,S,SF,AM
LOCSYM,CN,N,S,SF,AM
NOSCn
NOSCn
(Refer to Section 7 under Mu1tiword Instructions for
description of Multiword Modification Field.)
OPERATI NG MODES:
Any
8-25
DZ51-00
AD2D
AD2D
C(string 2)
SUMMARY:
+
(string 1)
-->
C(string 2)
Same as AD3D, except that the sum is stored using YC2, TN2,
S2 and, if S2 indicates a scaled format, SF2.
ILLEGAL ADDRESS
MODI FI CATl ONS :
DU, DL for MF1 and MF2
ILLEGAL REPEATS:
RPT, RPD, RPL
I
ND! CATORS:
Same as for AD3D
NOTES:
1. All notes for AD3D apply also to AD2D.
2. Illegal Procedure fault same as for MVN.
3.
An I llega1 Procedure fault occurs if illegal address
modification or an illegal repeat is used.
EXAMPLES:
1
FLDl
FLD2
FLDl
FLD2
8
16
32
AD2D
NDSC4
NDSC9
USE
EDEC
EDEC
USE
, , , ,1
FLDl,O,8,2,-2
FLD2,O,6
CONST.
8P123456+
6A+1E+2
with truncation enable option
FL01 addend operand descriptor
FLD2 addend operand descriptor
memory contents
o 1 2 3 456 +
+0 0 0 1 2
+ 1 3 3 4 0 (Sum) (truncation fault)
AD2D
NDSC9
NDSC4
USE
EDEC
EDEC
USE
, , ,1
FLD1,O,4
FLD2,1,7,2,-4
CONST.
with plus sign octal 13 option
FL01 addend operand descriptor
FLD2 addend operand descriptor
memory contents
+9 9 0
o 1 2 3 456 +
o 1 1 3 4 56+ (Sum) (overflow fault)
41\+99.
8Pl23456+
8-26
DZ5l-00
".
AD2D
AD2D
EXAMPLE
1
~~TH
ADDRESS MODIFICATION:
8
16
EAXl
1
EAX7
EAX4
AWDX
AD2D
NDSC4
NDSC9
FLDl
USE
EDEe
EDEe
FLD2
I NDSC2 NDSC9
USE
32
load character modifier into Xl
7
load FLDl length into X7
FLDl
load FLDl address into X4
0,4,4
put FLDl address into AR4
(l,l"Xl),(,,1),l,1 rounding and plus sign options
0"X7,2,-2,4
FLDl operand descriptor (FLDl,1,7,2,-2)
INDSC2
pointer to FLD2 indirect operand descriptor
CONST.
8P1234508A+9876E+2
FLD2,0,8
memory contents
1 2 3 4 5
+
9 8 7 6 2
FLD2 indirect operand descriptor
+ 9 8 6 3 6 6
(Sum)
° °°
°-
°
(
8-27
DZ5l-00
AD2DX
AD2DX
Add Using Two Decimal Operands Extended
AD2DX
242
(1)
FORMAT:
000
0011
1 1
242(1)
MF2
o
o
222
Op COde
1 122
7 801
0
2
3
NFl
222
234
2 3
9 0
3
5
Y1
CN1 TN2 SX1
AR#
SF1
N1
Y1
o
o
1 122
7 801
222
234
2 3
9 0
3
5
Y2
CN2 TN2 SX2
AR#
CODING FORMAT:
SF2
N2
Y2
1
8
16
AD2DX
(MF1),(MF2),RD,CS,T,NS
LOCSYM,CN,N,SX,SF ,AM
LOCSYM,CN,N,SX,SF,AM
NOSen
NOSCn
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
OPERATING MODES:
Any
SUMMARY:
C(string 2}
+
C(string 1) --> C(string 2)
8-28
DZ51-00
AD2DX
AD2DX
EXPLANATION:
The decimal number of data type TNl, sign and decimal type SXl,
and starting location YCl, is added to the decimal number of
data type TN2, sign and decimal type SX2, and starting location
YC2. The sum is stored starting in location YC2 as a d~cimal
number of data type TN2 and sign and decimal type SX2.
o If SX2 indicates a fixed-point format, the results are
stored using scale factor SF2, which causes leading or
trailing zeros (4 bits - 0000, 9 bits - 000110000) to be
supplied and/or most significant digit overflow or least
significant digit truncation to occur.
o If SX2 indicates a floating-point format, the result is
right-justified to preserve the most significant nonzero
digits even if this causes least significant truncation.
(
o The character set is defined by CS. Placement of an
overpunched sign in the output is controlled by NS. (Refer
to the introductory pages of this section for definition of
NS.) If RD is 1, rounding takes place prior to storage.
Provided that strings 1 and 2 are not overlapped, the
contents of the decimal number that starts in location YCl
remains unchanged.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MFl and MF2
I LLEGAL REPEATS:
RPT, RPD, RPL
I
NDI CATORS :
Zero
- If result equals zero, then ONi otherwise, OFF
Negative
- If result is negative, then ONi otherwise, OFF
Truncation - If in the preparation of the final result, one
or more least significant digits (zero or
nonzero) are lost and rounding is not
specified, then ON; otherwise (i.e., no least
significant digits lost or rounding specified),
OFF.
Overflow
Exponent
Overflow
- If data is lost in most significant positions,
then ONi otherwise, unchanged
- If exponent of floating point result> 127,
then ON; otherwise, unchanged
8-29
DZ5l-00
AD2DX
AD2DX
Exponent
Underflow
NOTES:
If exponent of floating point result
then ON; otherwise, unchanged
< - 128,
1. Truncation fault occurs if the truncation indicator is
set and the truncation fault enable
(T) bit
is a
1.
2. Illegal procedure faults occur when
a. DU or DL modification in NFl or MF2.
b. The sign and numeric digits contains an unpermitted
code.
c. Though the operand descriptor indicates the presence
of a sign or exponent, the value of Nl or N2 does not
contain the number of characters required for the sign
and exponent (when at least one digit is required).
d.
An
illegal repeat is used.
3. Independent of the data type being used, either packed
decimal or 9-bit numeric, floating point or fixed-point,
significant digits of the result may be lost if the
result field as defined by the result descriptor is not
large enough to contain the calculated result after it
has been aligned.
4. If an illegal digit or sign is detected, part or all of
the receiving field may be changed before the IPR fault
occurs.
5. All notes for AD3D apply to AD2DX.
6. Refer to the specifications on MVNX for information on
coding of overpunched signs.
7.
An Illegal Procedure fault occurs if illegal address
modification is used.
8-30
DZ5l-00
(
AD3D
AD3D
Add Using Three Decimal Operands
AD3D
222 (1)
FORMAT:
1+1
0
0
1 1
7 8
001 1
890 1
000
012
MF3
HRDI
MF2
0
2
222
789
Op Code
I
222(1)
1 1 2 2
7 801
222
234
H
3
5
MFl
2 3
9 0
I
3
5
Yl
CNl TNl Sl
Nl
Yl
AR#
(
SFl
o
o
1 122
780 1
222
234
2 3
3
5
9 0
Y2
CN2 TN2 S2
Y2
AR#
o
o
2
N2
..
1 1 2 2
780 1
0
SF2
222
234
2 3
3
5
9 0
Y3
CN3 TN3 S3
AR#
SF3
N3
Y3
8-31
DZ51-00
AD3D
AD3D
CODING FORMAT:
The AD3D instruction is coded as follows:
1
8
16
AD3D
NOSCD
NOSCD
NOSCD
(MF1),(MF2),(MF3),RD,P,T
LOCSYM,CN,N,S,SF,AM
LOCSYM,CN ,N,S,SF,AM
LOCSYM,CN,N,S,SF,AM
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
OPERATI NG MODES:
Any
SUMMARY:
C(string 2)
EXPLANATION:
The decimal number of data type TNl, sign and decimal type
Sl, and starting location yel, is added to the decimal number
of data type TN2, sign and decimal type S2, and starting
location YC2. The sum is stored starting in location YC3 as
a decimal number of data type TN3 and sign and decimal type
S3.
+
C(string 1)--> C(string 3)
If S3 indicates a fixed-point format, the results are stored
using scale factor SF3, which causes leading or trailing
zeros (4 bits - 0000, 9 bits - 000110000) to be supplied
and/or most significant digit overflow or least significant
digit truncation to occur.
\
If S3 indicates a floating-point format, the result is
right-justified to preserve the most significant nonzero
digits even if this causes least significant truncation.
If P = 1, positive signed 4-bit results are stored using
octal 13 as the plus sign. If P = 0, positive signed 4-bit
results are stored with octal 14 as the plus sign. If RD is
1, rounding takes place prior to storage.
Provided that strings 1, 2, and 3 are not overlapped, the
contents of the decimal numbers that start in locations YCl
and YC2 remai~ unchanged.
The zero indicator is set when the decimal number is zero; it
does not indicate the case in which all bits are zero.
j
8-32
DZ51-00
AD3D
AD3D
If the result is given by a fixed-point, operations are
performed by justifying the scaling factors (SFl, SF2, and
SF3) of the operands 1, 2, and 3 as follows:
If SFl
>
SF2
SFI > SF2 >= SF3 --> Justify to SF2
SF3 > SFl > SF2 --> Justify to SFl
SFI >= SF3 > SFl --> Justify to SF3 - I
If SF2 > SFl
SF2 > SFl >= SF3 --> Justify to SFl
SF3 > SF2 > SFl --> Justify to SF2
SF2 >= SF3 > SFl --> Justify to SF3 - 1
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MF1, MF2, and MF3
I LLEGAL REPEATS:
INDICATORS:
RPT ,RPD, RPL
Zero
-
If result equals zero, then ON: otherwise, OFF
-
If result is negative, then ON: otherwise, OFF
Truncation -
If, in the preparation of the final result,
one or more least significant digits (zero or
nonzero) are lost and rounding is not
specified, then ON. Otherwise (i.e., no least
significant digits lost or rounding is
specified), OFF
Negative
Exponent
Overflow
If exponent of floating-point result is > 127,
then ON; otherwise, unchanged
Exponent
Underflow
Overflow
If exponent of floating point result < - 128,
then ON: otherwise, unchanged
-
If data is lost in most significant positions,
then ON: otherwise, unchanged
8-33
DZS1-OO
AD3D
AD3D
1. Truncation fault occurs if the Truncation indicator is set
and the truncation fault enable (T) bit is 1.
NOTES:
2. Illegal procedure faults occur when
a. DU or DL modification in NFl or NF2.
b. The sign and numeric digits contains an unpermitted
code.
c. Though the operand descriptor indicates the presence
of a sign or exponent, the value of Nl or N2
does not contain the number of characters required
for the sign and exponent (when at least one digit
is required).
3. Independent of the data type being used (either packed
decimal or 9-bit numeric floating-point or scaled)
significant digits in the result may be lost if:
a. The difference between the scaling factors (exponents)
of the source operands is large enough to cause the
expected length of the intermediate result to exceed 63
digits after decimal point alignment of source
operands, followed by addition.
b. The result field as defined by the result descriptor is
not large enough to contain the calculated result after
it has been aligned.
4. If an illegal digit or sign is detected, part or all of
the receiving field may be changed before the IPR fault
occurs.
EXAMPLES:
1
8
AD3D
FLDl
FLD2
FLD3
NOSC9
NOSe9
NOSC4
USE
EDEC
EDEC
BSS
USE
16
32
, , ,1, 1
with rounding and plus sign options
FLDl addend operand descriptor
FLD2 addend operand descriptor
operand descriptor for sum field
memory contents
FLD1,0,4,3,-2
FLD2,0,8,2,-2
FLD3,2,6,1
CONST.
4Al234
8A65432l+
1
1 2 3 4
0654321+
x.x+06556
(Sum )
instruction fault?
8-34
no
DZ5l-00
\, ~j
(
AD3D
AD3D
EXAMPLE v,TI TH ADDRESS MODI n CATl ON:
1
FLDl
FLD2
FLD3
DFLD3
32
8
16
EAX2
EAX6
EAX4
AWDX
AD3D
NDSC9
NDSC4
ARC
USE
EDEC
EDEC
BSS
NDSC4
USE
2
load character modifier into X2
6
load FLDI length into X6
FLDI
load FLDI address into X4
0,4,4
put FLDI address into AR4
(1),(,l"X2),{,,1),1,1
0,0,4,
FLDl operand descriptor (FLD1,0,4,0)
FLD2"X6,3,-2 FLD2 operand descriptor (FLD2,2,6,3,-2)
DFLD3
pointer to FLD3 operand descriptor
CONST.
memory contents
4A-12E+2
- 122
8P123456
00123456
xxx+0346
(Sum)
1
FLD3,3,5,1,-1 FLD3 sum operand descriptor
instruction fault?
no
(
8-35
DZ51-00
AD3DX
AD3DX
Add using Three Decimal Operands Extended
AD3DX
262 (1)
FORMAT:
0 o 0
012
IcsH
0
0
MF3
HRDI
0
2
MF2
222
789
Op Code
I
262(1)
1 1 2 2
222
234
7 8 0 1
Y1
CN1 TN1 SXI
II I
3
NFl
2 3
9 0
SF1
3
5
N1
Y1
AR#
o
o
1 1
7 8
001 1
890 1
1 122
7 801
0
2
222
234
2 3
9 0
3
5
Y2
CN2 TN2 SX2
N2
Y2
AR#
o
o
SF2
1 1 2 2
780 1
0
2
222
234
2 3
9 0
3
5
Y3
CN3 TN3 SX3
AR#
SF3
N3
Y3
8-36
DZ51-00
AD3DX
AD3DX
CODING FORMAT:
1
8
16
AD3DX
NOSCn
NOSen
(MF1),(MF2),(MF3),RD,CS,T,NS
LOCSYM,CN ,N ,SX,SF,AM
LOCSYM,CN ,N ,SX,SF,AM
LOCSYM,CN,N ,SX,SF ,AM
NDSCn
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
OPERATl NG MODES:
Any
SUMMARY:
C(string 2)
EXPLANATION:
The decimal number of data type TNI, sign and decimal type
SKI, and starting location yel, is added to the decimal
number of data type TN2, sign and decimal type SX2, and
starting location YC2. The sum is stored starting in
location YC3 as a decimal number of data type TN3 and sign
and decimal type SX3.
+
C(string 1) --> C(string 3)
If SX3 indicates a fixed-point format, the results are stored
using scale factor SF3, which causes leading or trailing
zeros (4 bits - 0000, 9 bits - 000110000) to be supplied
and/or most significant digit overflow or least significant
digit truncation to occur.
If SX3 indicates a floating-point format, the result is
right-justified to preserve the most significant nonzero
digits even if this-causes least significant truncation. The
character set is defined by CS. Placement of overpunched
sign in the output is controlled by NS. (Refer to the
introductory pages of this section for definition of NS.) If
RD is 1, rounding takes place prior to storage. Provided
that strings 1, 2, and 3 are not overlapped, the contents of
the decimal numbers that start in locations YCI and YC2 .
remain unchanged.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MF1, MF2 and MF3
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
Zero
-
If result equals zero, then ON: otherwise, OFF
Negative
-
If result is negative, then ON: otherwise, OFF
(
8-37
DZ51-00
AD3DX
AD3DX
Truncation -
If, in the preparation of the final result,
one or more least significant digits (zero or
nonzero) are lost and rounding is not
specified, then ON. Otherwise (i.e., no least
significant digits lost or rounding
specified) OFF.
I
Overflow
-
If data is lost in most significant positions,
then ON ~ otherwise, unchanged.
Exponent
Overflow
-
If exponent of floating-point result> 127,
then ON ~ otherwise, unchanged.
Exponent
Underflow
NOTES:
If exponent of floating point result < - 128,
then ON; otherwise, unchanged
1. Truncation fault occurs if the truncation indicator is set
and the truncation fault enable (T) bit equals l.
2. Illegal procedure faults occur when:
a. DU or DL modification in NFl or MF2.
b. The sign and numeric digits contains an unpermitted
code.
c. Though the operand descriptor indicates the presence
of a sign or exponent, the value of Nl or N2
does not contain the number of characters required
for the sign and exponent (when at least one digit
is required).
3. Independently of the data type being used (either packed
decimal or 9-bit numeric, floating-point or scaled)
significant digits of the result may be lost if the result
field as defined by the result descriptor is not large
enough to contain the actual calculated result after it
has been aligned.
4. If an illegal digit or sign is detected, part or all of
the receiving field may be changed before the IPR fault
occurs.
5. For coding of overpunched signs, refer to MVNX.
6.
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
8-38
DZ51-00
ADA
ADA
(
Add to A-Register
075 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(A) + C(Y)
I LLEGAL ADDRESS
MODI FI CATIONS:
None
I LLEGAL REPEATS:
None
INDICATORS:
Zero
-
-->
C(A)i C(Y) unchanged
If C(A)
= 0,
= 1,
then ON; otherwise, OFF
Negative -
If C(A)O
Overflow -
I f range of A is exceeded, then ON
carry
If a carry out of bit of C(A) is generated,
then ON; otherwise, OFF
-
I
then ON; otherwise, OFF
°
8-39
DZ51-00
ADAQ
ADAQ
ADAQ
Add to AQ-Register
077 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Any
SUMMARY:
C(AQ) + C(Y-pair) -> C(AQ): C(Y-pair) unchanged
I LLEGAL ADDRESS
MODI PI CATl ONS:
DU, DL, CI, SC I SCR
I LLEGAL REPEATS:
None
INDICATORS:
zero
= 0,
If C(AQ)
= 1,
then ON: otherwise, OFF
Negative -
If C{AQ)O
Overflow -
If range of AQ is exceeded, then ON
carry
NOTE:
-
-
then ON: otherwise, OFF
If a carry out of bit 0 of C(AQ) is generated,
then ON; otherwise, OFF
An Illegal Procedure fault occurs if an illegal address
modification is used.
8-40
DZ5l-00
(
ADE
}.DE
ADE
Add to Exponent Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Any
SUMMARY:
C(E) + C(Y)O-7 --> C(E)
I LLEGAL ADDRESS
MODIFICATIONS:
a, SC, SCR
ILLEGAL REPEATS:
None
I NDI CATORS:
Zero
-
Set OFF
Negative
-
Set OFF
Exponent
Overflow
-
If exponent is > +127, then ON
Exponent
Underflow
NOTES:
415 (0)
If exponent of floating point result < - 128,
then ON; otherwise, unchanged
1. An Illegal Procedure fault occurs if illegal address
modification is used.
2. All data is handled as 0 when DL modification is
specified in the NS mode.
8-41
DZ51-00
ADL
ADL
ADL
Add Low to AQ-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C{AQ)
+
C(Y, right-adjusted) --> C(AQ)
This instruction forms the following 72-bit number:
o
o
3 3
5 6
7
C(Y)
I C(y)O------------C(y)Oi
The lower half (bits 36 through 71) is C(Y). The bits in the
upper half (bits 0 through 35) are equal to the C(Y) sign bit
(C(Y)O)' This value is added to the AQ. If a carry is
generated from Q as a result of this addition, it is passed
on to A.
ILLEGAL ADDRESS
MODIFICATIONS:
CI, SC, SCR
I LLEGAL REPEATS:
None
INDICATORS:
Zero
= 0, then
If C(AQ)
= 1,
ONi
otherwise, OFF
Negative -
If C(AQ)O
Overflow -
I f range of AQ is exceeded, then ON
Carry
NOTE:
-
-
then ON: otherwise, OFF
If a carry out of bit 0 of C(AQ) is generated,
then ONi otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modification is used.
8-42
DZS1-00
(
ADLA
ADLA
ADLA
Add Logical to A-Register
035 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(A) + C(Y) --> C(A): C(Y) unchanged
EXPLANATION:
This in~truction is identical to ADA with the exception that
the overflow indicator is not affected and an Overflow fault
does not occur. Operands and results are treated as
unsigned, positive binary integers.
ILLEGAL ADDRESS
MODIFICATIONS:
None
I LLEGAL REPEATS:
None
INDICATORS:
Zero
-
If C(A) = 0, then ON: otherwise, OFF
= 1,
Negative -
If C(A)O
carry
If a carry out of bit 0 of C(A) is generated,
then ON: otherwise, OFF. When the carry
indicator is ON, the range of A has been
exceeded.
.
-
then
ONi
otherwise, OFF
(
8-43
DZ51-00
ADLAQ
ADLAQ
ADLAQ
Add Logical to AQ-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(AQ)
+
037 (0)
C(Y-pair) -> C(AQ); C(Y-pair) unchanged
This instruction is identical to ADAQ except that the
overflow indicator is not affected and an overflow fault does
not occur. Operands and results are treated as unsigned,
positive binary integers.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI I SC, SCR
I LLEGAL REPEATS:
None
I NDI CATORS:
Zero
-
Negative -
If C(AQ) = 0, then ONi otherwise, OFF
'\
If C(AQ)O = 1, then ON; otherwise, OFF
/
carry
NOTE:
-
If a carry out of bit 0 of C(AQ) is generated,
then ON; otherwise, OFF. When the carry
indicator is ON, the range of AQ has been
exceeded.
An Illegal Procedure fault occurs if illegal address
modification is used.
8-44
DZ5l-00
ADLQ
ADLQ
ADLQ
(
Add Logical to Q-Register
036 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C
C(Q); C(Y) unchanged
If C(Q) = 0, then ON; otherwise, OFF
If C(Q)o = 1, then ON; otherwise, OFF
If a carry out of bit 0 of C(Q) is generated,
then ON; otherwise, OFF. When the carry
indicator is ON, the range of Q has been
exceeded.
8-45
DZ5l-00
ADLR
ADLR
ADLR
Add Logical Register to Register
435
(1)
FORMAT:
1 1
7 8
000
Not Used
CODING FORMAT:
1
I
8
16
ADLR
Rl, ,R2
OPERATING MODES:
Executes in ES mode only
SUMMARY:
Rl, R2
C(Rl)
= 0,
+
222 3 3
789 1 2
OP CODE
II I I
NEZ
3
5
R2
I
1, 2, 3, 4, 5, 6, 7, A, Q
C(R2)
ILLEGAL ADDRESS
MODIFlCATIONS:
None.
I LLEGAL REPEATS:
RPT, RPD, RPL
-> C(Rl); C(R2) unchanged
The address modification is not executed.
I LLEGAL EXECUTES: Execution in NS mode
I NDl CATORS:
NOTES:
Zero
-
= 0,
If C(Rl)
= 1,
then ON; otherwise, OFF
Negative -
If C(Rl)O
carry
If a carry out of bit 0 of C(Rl) is generated, then
ON; otherwise, OFF.
1.
-
then ON; otherwise, OFF
IPR fault occurs if illegal repeats are executed or if the
instruction is executed in NS mode.
An
2. Refer to Register to Register Instructions in section 7 for a
description of the fields in the instruction word.
8-46
DZ51-00
(
ADLXn
ADLXn
ADLXn
Add Logical to Index Register !!
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
For n
= 0,1 ••• ,
C(X!!)
+
7 as determined by op code
C(Y)O-17 -> C(X!!); C(Y) unchanged
ES Mode
For n = 0,1 ••• , 7 as determined by op code
C(GXn) + C(Y)
EXPLANATION:
(
-> C(GXn); C(Y) unchanged
This instruction is identical to ADX!! with the exception that
the overflow indicator is not affected and an Overflow fault
does not occur. Operands and results are treated as
unsigned, positive binary integers.
ILLEGAL ADDRESS
MODIFICATIONS:
CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL of ADLXO
I NDI CATORS:
Zero
NOTES:
-
If C(X!!)/(GXn) = 0, then ON: otherwise, OFF
= 1,
Negative -
If C(Xn)/{GXn)o
carry
If a carry out of bit 0 of C(Xn)/(GX!!) is
generated, then ON: otherwise, OFF. When the
carry indicator is ON, the range of Xn/GXn been
exceeded
-
1. All data is handled as
for the NS mode.
a when
then ON: otherwise, OFF
DL modification is specified
2. An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
(
8-47
DZSl-OO
ADO
ADQ
ADO
Add to Q-Register
076 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C Co
Overflow -
I f range of Q is exceeded, then ON
carry
If a carry out of bit 0 of C C(R1): C(R2) unchanged
The address modification is not executed.
ILLEGAL EXECUTES: Execution in NS mod,e
I NDI CATORS:
Zero
If C(R1)
= 0, then ON: otherwise, OFF
Negative -
If C(R1)0 = 1, then ON: otherwise, OFF
Overflow -
If the range of R1 is exceeded, ON.
carry
NOTES:
-
1.
-
If a carry out of bit 0 of C(R1) is generated,
then ON: otherwise, OFF.
I PR fault occurs if illegal repeats are executed or if
the instruction is executed in NS mode.
An
2. Refer to Register to Register Instructions in Section 7
for a description of the fields in the instruction word.
8-49
DZ51-00
ADXn
ADXn
Add to Index Register n
06n 10)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Any
SUMMARY:
NS Mode
For n
= 0,
C(Xn)
+
1 ••• , or 7 as determined by op code
C(Y)0-17--> C(Xn}: C(Y) unchanged
ES Mode
For n
= 0,
C(GXn)
+
1 ••• , or 7 as determined by op code
C(y)--> C(GXn): C(Y) unchanged
I LLEGAL ADDRESS
MODIFICATIONS:
CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL of ADXO
I
NDI CATORS:
NOTES:
Zero
-
If C(Xn)/(GXn)
/
= 0,
= 1,
then ON: otherwise, OFF
Negative -
If C(Xn)/(GXn)o
then ON: otherwise, OFF
Overflow -
I
carry
If a carry out of bit 0 of C(~/GXn) is
generated, then ON: otherwise, OFF
f range of Xn/GXn is exceeded, then ON
1. All data is handled as 0 when DL modification is specified
in the NS mode.
2. An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
8-50
DZ5l-00
(
ALR
ALR
ALR
A-Register Left Rotate
775 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
EXPLANATION:
NS Mode
Rotate C(A) left the number of positions indicated by bits
11-17 of Y (Y modulo 128); enter each bit leaving bit
position 0 in bit position 35.
ES
Mode
Rotate C(A) left the number of positions indicated by bits
27-33 of Y (y modulo 128): enter each bit leaving bit
position zero in bit position 35.
(
The rotate count in the instruction must be a decimal
number. To "right-rotate" n bits, use ALR 36-n.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL,
ILLEGAL REPEATS:
RPL
I NDI CATORS:
Zero -
a, SC,
If C(A)
Negative NOTE:
SCR
= 0,
If C(A)O
then ON: otherwise, OFF
= 1,
then ON; otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
8-51
DZ51-00
ALS
ALS
ALS
A-Register Left Shift
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
EXPLANATION:
NS Mode
735 (0)
Shift C(A) left the number of positions indicated by bits
11-17 of Y (y modulo 128); fill vacated positions with zeros.
ES Mode
Shift C(A) left the number of positions indicated by bits
27-33 of Y (y modulo 128); fill vacated positions with zero.
The shift count in the instruction must be a decimal number.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, a, SC,
I LLEGAL REPEATS:
RPL
INDICATORS:
Zero
-
Negative carry
NOTE:
-
SCR
-"
= 0, then ON; otherwise, OFF
C(A)O = 1, then ON; otherwise, OFF
If C(A)
If
If C(A}O changes during the shift, then ON;
otherwise, OFF. When the carry indicator is ON,
the algebraic range of A has been exceeded.
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
8-52
DZ51-00
(
ANA
ANA
ANA
AND to A-Register
375 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
For i
=0
to 35, C(A)i AND C(Y)i --> C(A)i:
C(Y) unchanged
I LLEGAL ADDRESS
MODI FI CATIONS:
None
I LLEGAL REPEATS:
None
I NDI CATORS :
Zero
-
Negative -
If C(A)
If C(A)O
= 0,
= 1,
8-53
then ON; otherwise, OFF
then ON; otherwise, OFF
DZ51-00
ANAQ
ANAQ
ANAQ
377 (0)
AND to AQ-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
For i
=0
to 71, C(AQ)i AND C(Y-pair)i --> C(AQ)i:
C(Y-pair) unchanged
LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
None
I NDI CATORS:
Zero
I
-
Negative NOTE:
= 0, then ON: otherwise, OFF
C(AQ)O = 1, then ON; otherwise, OFF
If C(AQ)
If
An Illegal Procedure fault occurs if illegal address
modification is used.
8-54
)
DZ5l-00
ANQ
ANQ
ANQ
AND to Q-Register
376 <0>
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
For i
ILLEGAL ADDRESS
MODIFICATIONS:
None
I LLEGAL REPEATS:
None
INDICATORS:
Zero
=0
-
Negative -
to 35, Ci AND C(Y)i
-->
C(Q>i:
= 0, then ON: otherwise, OFF
CO = 1, then ON: otherwise, OFF
If C
C(Rl)I
i
= 0,
3
5
II I MHZ I R2 I
1, 2, ••• , 35
C( R2) unchanged
ILLEGAL ADDRESS
MODIFICATIONS:
None.
I LLEGAL REPEATS:
RPT, RPD, RPL
The address modification is not executed.
ILLEGAL EXECUTES: Execution in NS mode
I NDI CA'l'ORS:
Zero
-
Negative NOTES:
1.
If C(R1) = 0, then ON; otherwise, OFF
If C(Rl)O
= 1,
then ON; otherwise, OFF
IPR fault occurs if illegal repeats are executed or if
the instruction is executed in ItS mode.
An
2. Refer to Register to Register Instructions in Sectiqn 7
for a description of the fields in the instruction word.
8-56
DZ51-00
ANSA
ANSA
.1
AND
ANSA
355 (0)
Single-word instruction format (see Figure 8-1)
FORMAT:
OPERATl NG
to Storage from A-Register
MODES:
SUMMARY:
Any
For i
=0
to 35, C(A)i AND C(Y)i --> C(Y)i:
C(A) unchanged
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPL
I NDI CATORS:
zero
-
Negative -
(
NOTE:
If C(Y) = 0, then ON: otherwise, OFF
If C(Y)O
= 1,
then ON: otherwise, OFF
An I llegal Procedure fault occurs if illegal address
modification or if an illegal repeat is used.
(~
8-57
DZ51-00
ANSQ
ANSQ
ANSQ
AND to Storage from Q-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY
For i = 0 to 35, C(Q)i AND C(Y)i --> C(Y)i;
356 (0)
C(Q) unchanged
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL,
I LLEGAL REPEATS:
RPL
I NDI CA'I'ORS :
Zero
a,
SC, SCR
-
If C(Y)
Negative NOTE:
If C(Y)o
= 0,
= 1,
then ON; otherwise, OFF
then ON: otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
8-58
DZ51-00
.~\
(
ANSXn
ANSXn
AND to Storage from Index Register
n
FORMAT:
Single-word instruction fonnat (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
For n
For i
= 0, 1, ••• , 7 as determined
= 0 to 17, C(Xn)i AND C(Y)i
34n (0)
by op code
--> C(Y)i:
C(Xn} and C{Y)18-35 unchanged
ES Mode
For n
For i
= 0, 1, ••• , 7 as determined by op code
= 0 to 35, C(GXn}i AND C(Y)i --> C(Y)i;
C(GXn ) is unchanged.
(
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPL, RPT, or RPD of ANSXO
I NDI CATORS:
NS Mode
Zero
-
Negative -
If bits C(Y}0-17
If C(Y}O
= 1,
= 0,
then ON; otherwise, OFF
then ON; otherwise, OFF
ES Mode
. Zero
-
Negative NOTE:
= 0, then ON; otherwise, OFF
C(Y)O = 1, then ON; otherwise, OFF.
If C(Y)
If
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
(
8-59
DZ51-00
ANXn
ANXn
'", . .J
AND to 1ndex 'Reg ister n
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATl NG MODES:
Any
SUMMARY:
NS Mode
For n
= 0,
.j
36n(O)
1, ••• , or 7 as determined by op code
For i = 0 to 17, C C(Xn)i
ES
Mode
For n
For i
I LLEGAL ADDRESS
= 0, 1, ••• , or 7 as determined by op code
= 0 to 35, C(GXn)i AND C(Y)i --> C(GX)i
MODIFICATIONS:
CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL of ANXO
I NDI CATeRS:
NS Mode
zero
-
Negative -
;'
If C(Xn) = 0, then ON; otherwise, OFF
If C C(Y)
I LLEGAL ADDRESS
MODI Fl CATIONS:
DU, DL, CI,
I LLEGAL REPEATS:
RPL
I NDI CATORS:
Zero
NOTE:
SCR
If C(Y)
= 0,
= 1,
then ON; otherwise, OFF
Negative -
If C(Y)O
Overflow -
If range of Y is exceeded, then ON
carry
(
-
st,
-
then ON; otherwise, OFF
If a carry out of bit 0 of C(Y) is generated,
then ON; otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
8-61
DZ51-00
ARAn
ARAn
Address Register n to Alphanumeric Descriptor
FORMAT:
Single-word instruction format (see Figure 8-1)
CODI NG FORMAT:
1
OPERATI NG MODES:
Any
SUMMARY:
For n
8
16
ARA!!
LOCSYM, RM, AM
= 0,
1, ••• , or 7 as determined by op code
C(ARn)0-17 --> C(Y)0-17
/trans1ated\
C(ARn)18-23 > C(Y)18-20
C(Y)21-35 unchanged
EXPLANATION:
This instruction is the converse of AARn. The alphanumeric
descriptor is fetched from the computed effective address Y.
The TA field code is examined to determine the type of data.
Bits 18-23 of ARn are appropriately translated and replace
bits 18-20 of the descriptor, and the word address (0-17) of
ARn replaces bits 0-17. The updated descriptor is then
stored back into location Y.
I LLEGAL ADDRESS
MODI F1 CATIONS:
DU, DL, CI, SC, 50
I LLEGAL REPEATS:
RPD, RPT, RPL
I LLEGAL EXECUTES: Execut ion in ES mode
I NDI CATORS :
None
NOTES:
1. An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used, or if the
descriptor TA field contains code 11.
2. AN IPR fault occurs if an attempt is made to execute this
instruction in the ES mode.
8-62
DZ51-00
f
ARAn
ARAn
EXAMPLE:
1
8
16
32
ARA6
DESCR
AR6 octal contents - 5 0 1 0 2 4 0 7
, ,4
memory contents in octal
5 0 1 0 2 4 0 0 0 0 0 4 - DESCR after
DESCR ADSC9
(
8-63
DZ51-00
ARL
ARL
ARL
A-Register Right Logical Shift
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
771 (0)
Shift C(A) right the number of positions indicated by bits
11-17 of Y (y modulo 128); fill vacated positions with zeros
ES
Mode
Shift C(A) right the number of positions indicated by bits
27-33 of Y (y modulo 128); fill vacated positions with zeros.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPL
I NDI CATORS :
Zero
\
-
Negative NOTES:
= 0, then ON; otherwise, OFF
C(A)O = 1, then ON; otherwise, OFF
If C(A}
If
1. The shift count in the instruction must be a decimal
number.
2.
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
8-64
DZ5l-00
ARNn
ARNn
Address Register
FORMAT:
CODING FORMAT:
n to Numeric Descriptor
Single-word instruction format (see Figure 8-1)
1
OPERATING MODES:
Any
SUMMARY:
For n
8
16
ARNn
LOCSYM, RM, AM
= 0,1, ••• ,7
as determined by op code
C{ARn)0-17 --> C(Y}0-17
/trans1ated\
C(ARn)18-23
---------->
C(Y)18-20
Bits 21-35 of C(Y) unchanged
(
EXPLANATION:
This instruction is the converse of NARD. The numeric
descriptor is fetched from the computed-effective address Y
and the TN field bit is examined. Bits 0-17 of ARn replace
the descriptor bits 0-17. Bits 18-23 of ARn are
appropriately translated and replace bits 18-20 of the
descriptor. The updated descriptor is then stored back in
location Y.
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
ILLEGAL EXECUTES: Execution in NS mode
I NDI CATORS :
None affected
NOTES:
1. An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
2. An IPR fault occurs if an attempt is made to execute this
instruction in ES mode.
(
8-65
DZ51-00
ARS
ARS
j
A-Register Right Shift
ARS
731 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Any
SUMMARY:
NS Mode
Shift C(A) right the number of positions indicated by bits
11-17 of Y (y modulo 128): fill vacated positions with bit 0
of C(A).
ES
Mode
Shift C(A) right the number of positions indicated by bits
27-33 of Y (y modulo 128): fill vacated positions with bit 0
of C(A).
I LLEGAL ADDRESS
MODI FI CATIONS:
ILLEGAL
REPEATS:
INDICATORS:
DU, DL, CI, SC, SCR
RPL
Zero
-
Negative NOTES:
If C(A)
= 0,
then ON; otherwise, OFF
If C(A)O = 1, then ON; otherwise, OFF
1. The shift count in the instruction must be a decimal
number.
2.
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
8-66
DZS1-00
(
ASA
ASA
ASA
Add To Storage From A-Register
055 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(A) + C(Y) -> C(y); C(A)
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPL
I NDI CATORS:
Zero
-
If
C(Y)
Negative -
If
C(Y)O
Overflow -
I f range of Y is exceeded, then ON
carry
NOTE:
= 0,
unchanged
-
= 1,
then ON: otherwise, OFF
then ON; otherwise, OFF
If a carry out of bit 0 of
then ON: otherwise, OFF
C(Y)
is generated,
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
(~
8-67
DZ5l-00
ASQ
ASQ
ASQ
Add To Storage From Q-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C C(Y); C C(Y)0-17: C(Xn) and C(Y)lB-35 unchanged
ES Mode
For n
= 0,1, ••• ,7
as determined b¥ op code
C(GXn) + C(y} -> C(Y); C(GXn) unchanged
(
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL of ASXO
INDICATORS:
NS
Mode
Zero
-
If C(Y)0-17 = 0, then ON; otherwise, OFF
Negative -
If C(Y)O = 1, then ON: otherwise, OFF
Overflow -
If range of YO-17 is exceeded, then ON
Carry
If a carry out of bit 0 of C(Y) is generated,
then ON; otherwise, OFF
-
('
B-69
DZ5l-00
ASXn
ASXn
I NDI CATORS:
ES Mode
Zero
NOTE:
-
If C(Y) = 0, then ON; otherwise, OFF
= 1,
Negative -
If C(Y}O
Overflow -
If range of Y is exceeded, then ON
carry
If a carry out of bit 0 of C(Y) is generated,
then ON; otherwise, OFF
-
then ON; otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
,/
8-70
DZ51-00
"\
(
AWCA
AWCA
AWCA
071 (O)
Add with Carry to A-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
If carry indicator is OFF, then C(A)
C(y) unchanged
If carry indicator is ON, then C(A)
C(A): C(Y) unchanged
EXPLANATION:
+
+
C(Y) --> C(A):
C(Y)
+
00 ••• 01 -->
This instruction operates similarly to the ADA instruction
except that if the carry indicator is ON prior to the
execution of the instruction, a 1 is added to the least
significant position of the A-register.
This instruction is intended for use with mu1tiword precision
binary arithmetic and for calculating checksums. The
positive 1 added when the carry indicator is ON represents
the carry from the next less significant word of the
multiword addition.
(
I LLEGAL ADDRESS
MODI FI CATIONS:
None
I LLEGAL REPEATS:
None
I NDI CATORS:
Zero
-
If C(A) = 0, then ON: otherwise, OFF
Negative -
If C(A)O = 1, then ON; otherwise, OFF
Overflow -
I
carry
If a carry out of bit 0 of C(A) is generated,
then ON: otherwise, OFF
-
f range of A is exceeded, then ON
8-71
DZ51-00
Awe}.
AWCA
(Checksum calculation)
EXAMPLE:
1
8
16
LDI
LDA
EAX2
EAX3
RPDA
=11324,DL
INCARD
INCARD+2
=0
22,1
0,2
0,3
INCAAD+l
ADLA
AWCA
CMPA
TNZ
ERROR
LDI
=0500000,DL
32
8-72
DZ51-00
(
AWCQ
AWCQ
AWCQ
Add with carry to Q-Register
072 (0)
FORMAT:
Single-word instruction format
+
C(Q>;
00 ••• 01 --> C
= 0,
= 1,
then ON; otherwise, OFF
Negative -
If C(Q)O
Overflow -
I f range of Q is exceeded, then ON
carry
If a carry out of QO is generated, then ON;
otherwise, OFF
-
8-73
then ON; otherwise, OFF
DZ5l-00
AWCQ
AWCQ
(Triple-precision Binary Fixed-point Addition)
EXAMPLE:
1
8
16
32
STI
LXLO
ANXO
STXO
LDA
ORSA
LDI
C
save overflow and overflow mask
LDQ
ADLQ
STQ
LDQ
REST
AWCQ
STQ
STI
LDA
ANA
ORA
STA
LDI
LDQ
C
=OO44000,DU
REST
=lB24,DL
set overflow mask ON
C
C
A+2
B+2
C+2
A+l
B+l
C+l
add low-order bits
C
restore overflow and overflow mask
add intermediate bits
=0733777,DL
C
**,DL
C
C
A
AWCQ
B
STQ
C
add high-order bits
~,
8-74
DZ51-00
;/
(
AWD
AWDX
AWD
AWDX
AWD
AWDX
FORMAT:
CODING FORMAT:
Add Word Displacement to Address Register
507
(1)
Special arithmetic instruction format (see Figure B-3)
16
8
1
{AWD }
{AWDX}
word displacement,R,AR
When the mnemonic is coded with X (AWDX), bit 29 is forced to
zero.
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
If bit 29
= 0:
If bit 29 = 1:
y + C(DR} --> ARnO-17
C(ARn)0-17 + y + C(DR) --> ARnO-17
In either case, zeros --> ARn1B-23
ES
Mode
If bit 29 = 0:
If bit 29
= 1:
[(se)y + C(DR)]6-35 --> C(AR)0-29
[(se)C(ARn)
C(AR)0-29
+
(se)y
+
C(DR)]6-35 -->
(se) indicates sign extension.
In either case, zeros --> ARn30-35
EXPLANATION:
NS Mode
The y field (with bit 3 extended) is added to the contents of
the register specified by the code in the DR field. Then, if
bit 29 = 0, this value replaces bits 0-17 of the AR specified
by bits 0-2 of the y field. If bit 29 = 1, this value is
added to bits 0-17 of the specified AR and the resulting sum
is stored in bits 0-17 of the specified AR. In either case,
bits 18-23 of the specified AR are zeroed.
(
8-75
DZ51-00
AWD
AWDX
AWD
AWDX
ES Mode
The y field (with bit 3 extended) is added to the contents of
the register specified by the code in the DR field. Then, if
bit 29 = 0, this value replaces bits 0-29 of the AR specified
by bits 0-2 of the y field. If bit 29 = 1, this value is
added to the sign extended value of the specified AR bits
0-29 and the sum loaded into the specified AR bits 0-29. In
either case, bits 30-35 of the specified AR are zeroed.
ADDRESS
MODIFICATIONS:
DU, DL, and Ic specified in DR
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
I LLEGAL
EXAMPLES:
(Example applies to NS mode only)
32
1
8
16
FLDl
BOOL
20100
FLPl
0,4,7
2,,7
X4 octal contents
AR7 octal contents AR7 octal contents -
10000
FLD2
512
0,2,4
1,3,4
X2 octal contents
X3 octal contents
AR4 octal contents AR4 octal contents -
./
EAX4
AWDX
AVID
FLD2
. BOOL
EAX2
EAX3
AWDX
AVID
- o2 0 1 0 0
-
-
8-76
020 1 0 0 0 0
o2 0 1 0 2 0 0
010
001
010
011
0 0 0
000
0 0 0 0 0
001 0 0
DZ5l-00
(
BCD
BCD
BCD
Binary-to-BCD Convert
505 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Any
SUMMARY:
Shift C(A) left 3 positions;
IC(A)I / C(Y} --> 4-bit quotient;
C(A) - ( C(Y) * quotient) --> remainder
1
Shift C C(Q)30-31
4-bit quotient --> C C(A)
EXPLANATION:
(
The BCD instruction carries out one step of an algorithm for
the conversion of a binary number to the equivalent
binary-coded decimal, which requires the repeated short
division of the binary number or last remainder by a 36-bit
constant from memory.
ci
= 8i *
10n- i (for i
= 1,
2, ••• ),
with n being defined by 10n-1 ~ I number
~ 10n- 1
For base K other than 10:
ci
= 8i *
Kn-l, where Kn-1 ~ I number
I
~ Kn-1.
One 6-bit character is produced each time the BCD instruction
is executed. The character produced represents a decimal
digit from 0 to 9.
(
The BCD instruction converts the magnitude of the contents of
the accumulator to the binary-coded decimal equivalent. The
method employed is to effectively divide a number by a
constant, place the result in bits 30-35 of the quotient
register, and leave the remainder in the accumulator. The
execution of the BCD instruction allows the user to convert a
binary number to BCD, one digit at a time, with each digit
coming from the high-order part of the number. The address
of the BCD instruction refers to a constant to be used in the
division; a different constant is needed for each digit. In
the process of the conversion, the number in the accumulator
is shifted left three positions. The quotient register is
shifted left six positions before the new digit is stored.
8-77
DZ51-00
BCD
BCD
The values in Table 8-1 are the conversion constants to be used
with the binary-to-BCD instruction. Each vertical column
represents the set of constants to be used depending on the
initial value of the binary number to be converted to its decimal
equivalent. The instruction is executed once per digit, using
the constant appropriate to the conversion step with each
execution.
alternate use of the table for conversion involves the use of
the constants in the row corresponding to conversion step 1. If,
after each conversion, the contents of the accumulator are
shifted right three positions, the constants in the conversion
step 1 row may be used one at a time in order of decreasing value
until the conversion is complete.
An
Table 8-1.
Starting
Range
-10
of
10
Binary-to-BCD COnversion COnstants
+1->
10 10 -1
C(AR)
-10
9
_10 8 +1 ->
+1->
10 8 -1
10 9 -1
,
-10 +1 ->
10 '_1
... /
1
8 ' )( 10 9
8 • 10 8
8 • 10 7
8 • 10 6
2
8 2 )( 10 8
8 2 • 10 7
8 2 )( 10 6
82
Conversion
3
8 3 x 10 7
8 3 • 10 6
8 3 • 10 5
8 3 x 10 4
Step
4
8 4 • 10 6
8 4 x 10 5
84
• 10 4
84
5
8 5 x 10 5
8 5 • 10 4
85
• 10 3
8 5 )( 10 2
6
8 6 x 10 4
8 6 • 10 3
8 6 x 10 2
8 6 x '0
'
7
8 7 • 10 3
87
8 7 x 10 '
8'
It
10 2
x 10 5
It
10 3
;
8
8 8 x 10 2
88 • 10 1
9
8 9 x 10 '
89
10
88
8 '0
8-78
DZ5l-00
(
BCD
BCD
Table 8-1 (cont). Binary-To-BCD Conversion Constants
_10 6 +1 ->
10 6 -1
-10 5 +1 ->
_10 4 +1
->
10 3 _1
10 4 -1
10 5 -1
_10 3 +1 ->
-10 ' +, ->
10 2 _1
8 ' x 10 5
8 x 10 4
8 x 10 3
8 x 10 2
8 x 10 '
8 2 x 10 4
8 2 • 10 3
8 2 x 10 2
8 2 x 10'
82
8 3 x 10 3
8 3 x 10 2
8 3 x 10'
83
8 4 x 10 2
8 4 • 10 '
84
8 5 x 10 '
85
-10 ' +1
->
10' -1
8
86
I LLEGAL ADDRESS
MODI FI CATIONS:
CI, SC, SCR
ILLEGAL REPEATS:
RPL
I NDI CATORS:
Zero
-
Negative NOTES:
If C(A)
= 0,
then ON; otherwise, OFF
If prior to execution bit 0 of C(A) = 1, then ON;
otherwise, OFF
1. The largest number that can be converted with the BCD
instruction is that represented by 33 bits.
2. A 6-bit character is generated in the Q-register each time
this instruction is executed.
3. The generated character represents one digit of the values
0-9.
4. One full 36-bit word cannot be directly converted by the
BCD instruction.
5. An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
8-79
DZ5l-00
BCD
BCD
EXAMPLE:
1
8
16
LOA
LDQ
BCD
BCD
=15,DL
O,DL
=80,DL
=64,DL
8-80
DZ51-00
BTD
BTD
BTD
Binary-to-Decima1 Convert
301 (1)
FORMAT:
I pi
0
0
1 1
7 8
1 1
o1
0 0
0 1
0---------0
I
MF2
1 1
7 8
Yl
II I
1 1
7 8
1 1
o1
Y2
CODING FORMAT:
3
5
Nl
N0
1
0
222 2 2
0 1 234
N S2
2
Yl
2 3
3
5
N2
0------ 0
00
1
8
B10
NDSC9
NDSCg
R1
9 0
T
CN2
I
MFl
00
0
2
AR#
3
5
2 3
9 0
o1
Y1
AR#
o
2 2
2 2 2
7 8 9
T
CNI
o
301(1)
I
1 1
o1
0
2
Op Code
R2
16
(MF1),(MF2),P
LOCSYM, CN , N, , , AM
LOCSYM,CN,N,S"AM
(Refer to Section 7 under Mu1tiword Instructions for description
of Multiword Modification Field.)
(
8-81
DZ51-00
BTD
BTD
OPERATING MODES:
Any
SUMMARY:
converted
C(string 1) ---------> C(string 2)
EXPLANATION:
The two's complement binary integer starting at location YC1
is converted into a signed string of decimal characters of
data type TN2, sign and decimal type 52 (52 = 00 is
illegal), and scale factor 0: and is stored,
right-justified, as a string of length L2 starting at
location YC2. If the string generated is longer than L2,
the high-order excess is truncated and the overflow
indicator is set. If strings 1 and 2 are not overlapped,
the contents of string 1 remain unchanged. The length of
string 1 (Ll) is given as the number of 9-bit segments that
make up the string. L1 is equal to or is less than B.
Thus, the binary string to be converted can be 9, 1B, 27,
36, 45, 54, 63, or 72 bits long. CN1 designates a 9-bit
character boundary. If P=1, positive signed 4-bit results
are stored using octal 13 as the plus sign. If P=O,
positive signed 4-bit results are stored with octal 14 as
the plus sign.
ILLEGAL ADDRESS
MODI FI CATI ON5:
DU, DL for NFl and MF2
ILLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
Zero
NOTES:
-
If the result is zero, then ON: otherwise, OFF
Negative -
If the resultant sign is negative, then ON;
otherwise, OFF
Overflow -
If L2 is less than the length of the string
generated, then .ON; otherwise, unchanged
1. An Illegal Procedure fault occurs if DU or DL
modification is used for NFl or MF2 or if an illegal
repeat is used.
2.
IPR fault occurs if L1 is less than 1 or greater than
B, if CN1 does not contain a legal code, if 52 = 00, or
if N2 is not large enough to specify at least one digit
excluding sign.
An
8-82
DZ51-00
(
BTD
BTD
EXAMPLES:
1
8
BTD
NDSC9
NDSC9
USE
FLDI
DEC
FLD2
BSS
USE
BTD
NDSC9
NDSC9
USE
FLDl
FLD2
DEC
BSS
USE
16
32
FLDl,2,2
FLD2,0,4,1
CONST.
-512
binary operand descriptor
decimal operand descriptor
memory contents in octal
7 7 7 7 7 7 7 7 7 000
o 5 5 0 6 5 0 610 6 2
any indicators set?
negative
1
FLDl,3,1
FLD2,1,3,2
CONST.
255
1
binary operand descriptor
decimal operand descriptor
memory contents in octal
o 0 0 000 0 0 0 3 7 7
o 0 0 0 6 506 5 0 5 3
any indicators set?
overflow
(
8-83
DZ51-00
CAMP
CAMP
Clear Associative Memory Pages
532 (1)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode.
EXPLANATION:
This instruction provides the capability to set the PTWAM ON
or OFF, to clear the entire PTWAM, and to selectively clear
the PTWAM. The instructions options are based on the
instruction word tag, the effective address bits 16, and 17,
and the ON/OFF state of the PTWAM.
When the instruction tag = 00 the following is executed
within the CPU that is executing the instruction.
o When PTWAM is ON
If EA16,17
= 00
or 10, the PTWAM is cleared.
If EA16 17 = 01, the PTWAM is set OFF:
the PTWAM is not cleared.
If EA16,17
= 11,
the PTWAM is not affected.
o When PTWAM is OFF
If EA16 17 = 10, the PTWAM is cleared:
the PTWAM is set ON.
If EA16,17
= 00,
01, or 11, the PTWAM is not affected.
When the instruction word tag = 01 a selective clear is done
within the processor that executes this instruction according
to the contents of the A and Q registers.
8-84
DZ51-00
(
CAMP
CAMP
0
0
C(A)
I
2 3
9 0
I VA(25-30) I
Reserved for Hardware Use
0
0
C Connect
Word 1
Abs. Addr. YO-27//0028-35 ---> Connect Word 2
C(A)O-8
C(A)9-17
C(A)l8-35
=
=
=
a control field
unused
a logical channel number and a table entry
When C{A)18-35
EXPLANATION:
= 0-7,
the logical channel number field
= O.
A double-word write to the designated control SCU occurs.
The SCU stores the double-word in the port connect queue and
informs the receiving port. The double-word is formed from
the contents of the CPU A register, an entry in the CPU
scratch pad, and the developed absolute address. The scratch
pad content known as the connect table, consists of twelve
12-bit entries. The connect table is created external to
software at initialization time.
The connect table entries are selected based on the contents
of A18-35 as follows.
C(A)lS-35
0-3
4
5
6
7
8-135
136-263
264-391
392-519
Recv'g
Unit
Log. Chan. No.
Unused
CPU-O
CPU-1
CPU-2
CPU-3
IMX-O
IMX-l
IMX-2
IMX-3
N/A
N/A
N/A
N/A
N/A
0-127
0-127
0-127
0-127
Table Entry
Number
4-7
8
9
10
11
0
1
2
3
// ""
~-j
8-92
DZ5l-00
(
croc
croc
The connect table entries are located in the PATROL half of
scratch pad memory at locations 74-77. A secondary connect
table is located at 0-3 and is used to support system
component reconfiguI·ation. These entries define the
following:
SCU PORT
-
Port and queue number of the unit that is to
receive the connect
IMX ID
-
Used by the central systems software
ID
-
Reserved for the central systems software
-
Valid connect word; 1
SYS
VALID
= valid.
The four primary entry words contain three 12-bit scratch
entries in bits 0-11, 12-23, and 24-35. The format of the
scratch pad data follows:
o
o
o
0
2 3
o
o
'0
4
5
6
1
2
1
4 5
1
6
1
7
222
2
2
1
o
0
7 8
1
1
1
e
1 2
9 0
2
3
3
3 3
3
SYS
3
1
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL,
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
cr,
1
1
2
ID
4
SC, SCR
8-93
DZ5l-00
CIOC
CIOC
NOTES:
1.
An IPR fault occurs if the use of this instruction is
attempted by a processor in the Slave mode or Master mode.
2.
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
3. If the VAlJD bit in the connect table entry does not equal
1, a Command fault occurs.
4. The developed absolute address points to a 24-word mail
box in main memory beginning at a 0 mod 8 address. The
entire mailbox must reside within the same page. The
first 8 words of this mailbox contain the basic
information needed to execute the I/O, including a List
Pointer Word (LPW) that points to the relative address of
a Data Control Word (OCW) list. The new list is located
in main memory. The mailbox also provides four different
base addresses or Pointer Words (PTW) and related
size/bounds information to be applied to the address
fields of the various control words during address
develoipment by the IMX. There may also be an optional
"link word" to another mailbox.
Upon termination of any I/O, the IMX stores the
termination status word, DeW residue information, LPW
residue, word counts, and extended status in the same
24-word mailbox. Table 8-6 illustrates the format of the
standard mailbox for an indirect channel.
8-94
DZ5l-00
" /
(
CIOC
CIOC
Word 0
1
2
3
4
5
6
7
8
9
10
11
o
Pointer
Pointer
Pointer
Pointer
Size 0
Size 2
to
to
to
to
PTW
PTW
PTW
PTW
17 18
List or
List or
List or
List or
35
Base
Base
Base
Base
I
I
Address
Address
Address
Address
Size
Size
0
1
2
3
1
3
Channel Link Word
LPW
Subsystem Status Word
LPW Residue
LPW Used to Fetch Last I DCW
DCW Residue
Data Count Since Last IDCW
Data Count for Total 1/0
12
13
14 1111////////////1/////////////////////////////////////////////
15 //////////////////////////////////////////////////////////////
16
17
18
Extended Status
19
20
21
(
22
23
Figure 8-6.
Standard I/O Mailbox
8-95
DZ5l-00
CLIMB
CLIMB
Domain Transfer
CLIMB
I
713
(1)
FORMAT:
1 1
7 8
0
0
Op
222 3
789 0
IrH
713(1)
ADDRESS
I
Code
1
o1
o0
o1
H
p
2 2
3 4
C
UNUSED
1
1
5
TAG
1
First Word
1 1
7 8
9 0
3
1
2 2
3
5 6
5
sl
D
second Word
1
The first word has the standard single-word instruction format (see Figure
8-1). The second word of the CLIMB instruction contains four control fields: C
(actually made up of two fields, C22-23 , and C18-19), E and P, and Sand D.
Bits 10-17 and 20-21 are not interpreted.
OPERAT! NG
MODES:
EXPLANATION:
Any
This instruction has four variations and performs functions
of call, return, and common routine calls both within the
same instruction segment and to a different instruction
segment and also within the same domain and to a different
domain reference.
The instruction word bit 28 (interrupt inhibit bit) does not
accept interrupt for three of the four functions whether it
is set to zero or to one. Bit 28 determines acceptance of
interrupt for the other function.
The AR bit (bit 29) specifies whether or not the address
register is to be used for generation of effective
addresses. The tag field is also for address generation.
8-96
DZS1-00
CLIMB
CLIMB
versions of the CLIMB instruction include:
Mnemonic
Meaning
IClJMB
(Inward CLIMB - CALL)
call another procedure which
may reside in another domain
OCLIMB
(Outward CLIMB -
Return to calling domain
RET)
GCLIMB
(Lateral Transfer -
LTRAS)
Transfer to another procedure
with passed arguments and
parameters which may reside in
another domain
PCLIMB
Transfer to another procedure
(Lateral Transfer - LTRAD) which may be in another domain
PMME
(System Entry CLI MB)
(
Privileged Master mode entry
(This is a form of Inward
CLIMB. )
The four control fields of the second word are defined as
follows:
C22,23
Instruction version
This field determines one of the five (counting PMME)
versions of the instruction to be executed:
00:
Inward CLIMB (ICLIMB) Version - functions as a CALL,
( i •e., a procedure invokes another procedure to .
accomplish a task and expects return of control from
that other procedure.) Additional descriptors may be
passed in a new parameter segment~ an empty argument
segment is created and placed in the argument stack.
The processor state is saved (safe stored) if the SSF
flag of the option register = 1. If S,D = 0,1760, this
is the PMME version (system Entry). If S,D F 0,1760,
this is the ICLIMB version.
01:
OUtward CLIMB (OCLIMB) Version (RET) - functions as a
return to the caller. The processor state is restored
to the last safe store frame.
8-97
DZ51-00
CLIMB
CLIMB
10:
Lateral Transfer with same Parameter and Argument
Segments (LTRAS). This version functions as an
unconditional transfer, giving the cal lee the same
visibility as the caller. The processor state is not
saved. LTRAS is also called GCLIMB.
11:
Lateral Transfer with new Parameter and Argument
Segments (LTRAD). This version functions the same as
the CALL version, except that the processor state is
not saved. LTRAD is also called PCLIMB.
The terms inward, outward, and lateral refer to use of the
stack segments. Inward means push the safe store frame on
the safe store stack (saving the present processor state),
frame a new parameter segment (PS), and open a new (empty)
argument segment (AS). OUtward means pop the safe store
frame off the safe store stack (restoring the former
processor state) and return PSR, ASR, LSR, ISR, IC, IR,
SEGID(IS), DSAR, and, if specified, ARO-AR7, SEGI DO-SEGI D7 ,
DRO-DR7, XO-X7, A, Q, E, and the Pointer/Length registers to
their prior settings. Lateral means leave the safe store
stack unchanged. The LTRAS version (10) keeps the PSR and
ASR unchanged, while the LTRAD version (11) activates new PSR
and ASR values in the same manner as an Inward CU ME.
C18
XO/GXO Control
For a CALL, LTRAS, or LTRAD, the C18 bit allows the caller
to load the effective address of the CLIMB instruction into
XO/GXO if C18 = 1 and if an entry descriptor is referenced
during execution of the CLIMB. For a RET, only the condition
C18 = 1 is required to load XO/GXO with the effective address
of the CLI ME. If C18 = 0, XO/GXO is not loaded, regardless
of CU ME vers ion.
If the mode changes during a CLIMB (CALL, LTRAS, and LTRAD)
the contents of XO or GXO are changed at the end of the
CU MB to track each other. If bit 18 of the C field of the
CLIMB instruction equals zero, or if the CUMB was not an
inter-domain transfer (an entry descriptor was not accessed)
the register modifications are as follows:
I
Mode Change
NS
to
ES
Register Load
o ->
C(GXO)O-17
C(XO) ---> C(GXO)1B-35
ES
to
NS
C(GXO)1835
8-98
--->
C(XO)
DZ5l-00
CUMB
CLIMB
If bit 18 of the C field equals 1 and the CUMB is a domain
transfer, the effective address specified by the CUMB is
loaded into Xo or GXO.
Register Load
Mode
NS to NS
BAO-17 - > C(XO)
ES to NS
BA16-33 - > C(XO)
NS to ES
o --->
C{GXOO>0-17
BAO-17 - > C(GXO )18-35
ES
to
ES
o --->
C{GXO>O-l
BAO-33 ---> C(GX)2-35
The XO or GXO loading is also done for a RETURN CUMB.
(
In any CLIMB or RETURN CLIMB instruction in which the mode
changes and the loading of Xn or GXn, (n = 1-7), is not
specified, the contents of these registers are undefined.
o C19, Slave Mode
For a CALL, LTRAS, or LTRAD, the C19 bit allows Slave mode to
For an RET, C19 is ignored. If the CLIMB is the
result of a fault interrupt, or invokes the System Entry
(PMME), the C19 bit is overridden, and the Master Mode
indicator is set.
be set.
Otherwise, for CALL, LTRAS, or LTRAD
if C19 = 0; 0 --->C(IR)28
if C19 = 1; no change to C(IR)28
If a CALL, LTRAS, or LTRAD attempts to transfer to a
privileged segment (flag bit 26 = 1) and C19 = 0, an SCL1 or
Security Fault, class 1 occurs.
8-99
DZ51-00
'
CLIMB
CLIMB
o E and P Argument Passing
The E and P fields are interpreted only for the ICLIMB
(CALL) and PCLIMB (LTRAD) versions of the CLIMB
instruction.
If E = 1, P+l descriptors are passed to the called
routine. These descriptors are either prepared (shrunk
and pushed onto the argument stack) by the instruction, or
found in a descriptor segment, depending on the contents
preset by the caller in ORO. When ORO refers to an operand
segment, a vector list is interpreted by the instruction
to prepare descriptors: when ORO refers to a descriptor
segment, the descriptors are in the segment. In both
cases, the PSR is loaded with a type 1 descriptor, framing
the P+l descriptors of parameters (or one parameter, if
the P field is zero).
If E = 0, no parameters are passed.
ignored.
The P field is
In both cases, the ASR is updated in such a way that it
locates the next available even-word location of the
descriptor stack. The bound field is set to zero. The
flag bit 27 is set to zero to indicate an empty segment.
Details related to the PSR and the ASR are provided later
in the CLIMB discussion.
The E and P fields are not interpreted for the RET and
LTRAS versions of the CLlMB instruction.
o S, D Field
For CALL, LTRAS, or LTRAD, this field indicates the origin
(SEGlD) of the the descriptor that determines the
destination of the CLIMB, or that the CLIMB is a System
Entry (PMME).
For the outward climb (RET), this field is ignored.
Instruction Variations
CLIMB variations determined by the settings in bits 22 and 23 of the
C field are described below. When the CLIMB instruction is executed,
a number of checks must be performed before the CPU state is altered.
8-100
DZ51-00
(
CLIMB
CLIMB
Inward CLIMB (CALL/ICLIMB) C field bits 22 and 23
= 00
1. The Sand D fields are interpreted in the same manner as the
Sand D fields of the vector in the LDDg instruction, except
that, in this instance, the values S = 0 and D = 1760 (octal)
define a PMME. If S = 0 and D = 1761 or 1763-1767 (octal), an
IPR fault occurs.
a. When S = 0, D = 17608, a special system entry is started
at the same level as fault and interrupt. Hardware
obtains the segment descriptor (this must be an Entry
Descriptor) from a fixed memory location. The Master Mode
indicator is always set to ON and the C field bit 19 is
ignored. After the entry descriptor is obtained from the
fixed memory location, execution of the CLIMB instruction
is continued as when a normal entry descriptor is
obtained. When there is no entry descriptor in the fixed
memory location, an IPR fault occurs.
b. If the CLIMB is a result of a fault or interrupt, this is
an interdomain transfer, requiring an entry descriptor,
which is obtained from locations in the operating system
as follows:
Interrupt: 30-31 octal
Fault:
32-33 octal
PMME:
34-35 octal
2. The CLIMB instruction Sand D fields are used to access the
specified segment descriptor segment or register and obtain
the segment descriptor. The referenced descriptor must be
one of the following types in order to continue execution of
the CLIMB instruction:
o Standard Descriptor (T
= 0)
o Descriptor Segment Descriptor (T
o Entry Descriptor (T
= 8,
=1
or 3)
9, or 11)
If the CLIMB instruction is a result of an interrupt, the
processor will attempt to obtain an entry descriptor from the
operating system location 30-31 (octal).
(
8-101
DZ5l-00
CLIMB
CLIMB
If the CLIMB instruction has not yet been linked to one of
the preceding descriptors, the obtained descriptor may be a
dynamic linking descriptor (T = 5). In this case, the CLIMB
instruction is terminated and a Dynamic Linking fault is
generated. All other descriptor types (T = 2, 4, 6, 7, 10,
or 12-15) terminate the CLIMB instruction and cause an IPR
fault.
Given a descriptor segment descriptor, an entry descriptor,
or a standard descriptor, the activity varies as follows:
a. Standard Descriptor' (T=O)
When the descriptor referenced by the S and D fields is a
standard descriptor, the CLIMB instruction is an
intradomain transfer and the linkage segment register is
not changed.
The obtained descriptor becomes the new instruction
segment descriptor. Flag bits 25, 27, and 28 are checked
and must be 1; otherwise, an appropriate fault occurs.
The base and bound are checked for modulo 32 bytes; if the
test fails, an IPR fault occurs.
b. Descriptor Segment Descriptor (T = 1 or 3)
When a type 1 or 3 descriptor is referenced by the Sand D
fields of the CLIMB instruction, the base of the type 1 or
3 descriptor is used as a pointer to an entry descriptor.
Flag bits 20, 27, and 28 must be 1 and the bound field
must be >= 7 bytes; otherwise, a Bound fault occurs. If
the obtained descriptor is not an entry descriptor nor a
dynamic linking descriptor, an IPR fault occurs.
If a dynamic linking descriptor is obtained, a Dynamic
Linking fault occurs.
c. Entry Descriptor (T = 8, 9, or 11)
When an entry descriptor is referenced by the S and D
fields of the CLIMB instruction (either directly or
indirectly), the CLIMB instruction is an interdomain
transfer. Entry descriptors may be of type T = 8, 9, or
11. The type of entry descriptor determines how much data
(register contents) will be safe stored, and how the
renewal of the pointer register will be processed.
(
8-102
DZ51-00
/
(
CLIMB
CLIMB
Using the entry descriptor, the new instruction segment
descriptor is obtained from the new linkage segment
described by the entry descriptor. The new linkage
segment is assumed to be present in real memory, because
the entry descriptor does not have a flags field to
indicate this, and the hardware attempts to obtain the new
instruction segment descriptor.
The obtained instruction segment descriptor must be a
standard descriptor with T = 0 and flag bits 25, 27, and
28 must be 1. If flag bit 25 is 0, a Security Fault,
Class 2 occurs: if flag bit 28 = 0, a Missing Segment
fault occurs: if flag bit 27 = 0, an STR fault occurs.
The hardware also checks the base and bound of the new
instruction segment descriptor for modulo 32 bytes; if the
test fails, the instruction terminates in an IPR fault.
If T is not 0, an IPR fault occurs.
3.
(
A
new parameter segment is prepared as described below.
The E bit of the second word of the ClJMB instruction is
checked. If the E bit = 0, the segment descriptor is not
passed (no parameter segment is prepared) and the operation
proceeds to the safe store.
If the E bit = 1, the segment descriptor is passed. The
operation that follows depends upon the type of the segment
descriptor in DRO. An IPR fault occurs if the type for this
segment is 3, 5, 7-11, 13 or 15.
a. Descriptor Type in DRO
=1
If the descriptor type contained in DRO is 1, the
descriptors to be passed as parameters have already been
prepared and are the last P+1 descriptors in this
descriptor segment. Thus, the hardware does not prepare
any descriptors but frames these last P+l descriptors with
the parameter segment register. I n this case, hardware
performs a bound check and if P + 111 > DRO, a bound fault
occurs.
b. Descriptor Type in DRO
= 0,
2, 4, 6, 12, or 14
If the descriptor type contained in DRO is 0, 2, 4, 6, 12,
or 14, the hardware prepares descriptors. The vector list
is located by pointer register zero (i.e., ARO and DRO
combined). The descriptor identified by the S and D
fields of each vector is obtained, prepared exactly as
described in the definition of the LDDn instruction, and
placed in the next available location In the argument
8-103
DZ51-00
CLIMB
CLIMB
segment as described in the defini~ion of the SDRn
instruction. This procedure is continued until all P+1
descriptors have been prepared and placed in the argument
segment. various faults may occur during this operation
as described in the definitions of the LDDn and SDRn
instructions. Note that a vector with an S-and D field of
S = 0, D = 1760 or 1761 (octal) causes an IPR fault: S and
D field values of S = 0, D = 1763 or 1764 (octal) require
that the processor be in Privileged Master mode (as
described in LDDn), which in this case refers to the
processor mode at the beginning of the CIJMB instruction.
If a vector specifies that a data stack descriptor is to
be formed and the associated bit in the option register
specifies that the stack space is to be cleared, the CLIMB
instruction performs the clear function.
If several data stack shrinks are specified, the second
and subsequent data stack shrink operations are performed
using the previously changed new value of the data stack
address register (DGAR).
4. Safe Store Operation
The safe store operation differs depending upon the type of
the segment descriptor referenced with the ICIJMB Sand D
fields. The size of the generated safe store frame and the
stored data is determined by the referenced segment
descriptor. The SSR base indicates the starting address of
the last frame of the stored data prior to this CIJMB. The
size of the last frame must therefore be added to the SSR
base before the new frame is stored. In relation to the SSR,
a 2-bit hardware control register, called the stack control
register (SCR) is used. The SCR contains a code indicating
the size of the last frame placed in the safe store
stack. (The SCR, is initialized to 112 or 102 (binary) when
the LDSS instruction is executed.} (Refer to details for the
LDSS instruction.) The following displays the flow of safe
store operation. When the safe store bypass flag (option
register bit 19) is ON (zero), safe store is bypassed and
processing proceeds to change the register contents as
described under Loading the Registers.
8-104
DZ51-00
CLIMB
CLIMB
a. The SSR base is increased, and the bound decreased, as
follows based on the SCR content.
SCR
SSR Base
SSR Bound
002
+16 words
-16 words
01 2
+24 words
-24 words
10 2
+80 words
-80 words
112
+64 words
-64 words
The SSR base indicates the start of the newly generated
safe store frame as a result of this operation.
NOTE: When hardware adds the SSR base, no check is
performed to check for carry. SOftware must ensure
that the base value initially loaded into the SSR is
not at the end of the working space.
(
A safe store stack fault occurs in conjunction with a
Inward (programmed) climb instruction, or in conjunction
with the wired-in CLIMB instruction that results from a
fault or interrupt. This fault indicates that the safe
store stack has only one or two 64-word frames remaining.
After completing the safe store on a Inward CLIMB (SSR
base and bound have been updat~), if the SSR bound < 239
+ 3 bytes, the hardware will not access the instruction
pointed bo by the new ISR and Ie, but will execute the
safe Store Stack fault. This causes another safe store
stack frame to be stored. This frame will contain the
"transferred to" domain registers from the inward CLIMB.
Word 5, bit 10 (SSSF) will be set to 1 and the fault code
in bits 12-16 of word 5 will be set to 00000.
When executing a fault or interrupt CLIMB, the hardware
updates the SSR base and bound while generating the safe
store frame, to determine whether a Safe Store Stack fault
should be indicated in the safe store frame with the
original fault or interrupt. If the SSR bound < 239 words
+ 3 bytes, the hardware will set word 5, bit 10 (SSSF) = 1
and leave the original fault code or interrupt cell number
in word 5, bits 12-16. The safestore Stack fault will not
be executed; a separate safestore stack frame will not be
stored.
8-105
DZ5l-00
CLIMB
CLIMB
NOTE: The operating system software must monitor word 5, bit
10 (SSSF) in each fault or interrupt frame in the safe
store stack and to initiate appropriate action whenever
this bit = 1.
b. The SCR content is saved in the new safe store frame.
c. The new SCR value is determined as follows, with the lower
two bits of the type field (T) of the first word of the
last segment descriptor referenced by the ClJMB
instruction S and D fields, and the value of bit 24 of the
ISR prior to the start of the CLIMB instruction.
T Field ISR Bit 24 SCR
o or
8
0 or 1
002
9
0 or 1
012
11
0
112
11
1
102
d. The amount of stored data (register content) is determined
by the SCR value at this time (as described in item c
above). The value of the SCR at this time is determined
by the type of segment descriptor referenced by this CLIMB
instruction and the ISR bit 24). As illustrated in
Figures 8-7 and 8-8, 16, 24, 64, or 80 words are stored in
accordance with the SCR content.
When the frame size is 64 or 80 words, the actual number
of words stored may depend on the state of the indicator
register bit 30 (multiword instruction interrupt or
fault). The processor hardware sets IR bit 30 = 1 when a
multiword EIS instruction is interrupted or faulted. IR
bit 30 may also be set to 1 by the operating system
software. The actual number of words stored when the
frame size is 64 words is 48 words, unless IR bit 30 = 1,
in which case 52 words are stored. When 52 words are
stored, the pointer and length registers are included in
the 64-word frame starting at word 48. Word 4, bit 30 is
stored as a 1, and then IR bit 30 is set to 0, as though
an SPL instruction had been executed.
e. Since the SCR is created by the hardware on the ICLIMB,
the mode and SCR should be consistent on the RETURN
CLIMB.
If software modifies the SCR content of the safe
store frame such that the mode, NS or ES, is inconsistent
with the safe store frame size, an IPR fault will occur.
8-106
DZ51-00
',,_ . ./
CLIMB
CLIMB
(11
o
01 00 <-SCR
0/1 0/1 <-ISR Bit 24
191Extended Fault Reaister
HWMR
0
•
CPU Fault Reqister
1
2
Imaae of Faultina Instruction
1
6
3 //////////////////////////////////////////////////
151////
IC
IR
4
18
6
2
SEGID 12
5 *11*21/////1*31*41 *5 10 RHUICP#ISCRI
1//////////////1
DSAR
EWSN# 9
W
6 17
4
7
Relative Virtual Address
0
r 8 - 9
ISR
W
0
d 10 - 11
ASR
r
s 12 - 13
LSR
d
PSR
• 14 - 15
16
ARO
SEGIDO
s
to
to
AR7
SEGID7
23
24
ORO
to
DR7
39
Xl
40
XO
41
X2
X3
42
X4
X5
43
X6
X7
44
A
45
0
J//////////////////////////////////////
46 8
E
1//////////
47 27
Timer Reqister
48
Mid-instruction Interrupt Data
(Stored on~y if IR bit 30 = 1)
51
52 //////////////////////////////////////////////////
54 - 55
LOR
56 //////////////////////////////////////////////////
·· ·· ·
•
··
•
•
· ·
•
•
•
·· ·
···
•
· ··
·
4·
8
·
W
0
r
d
s
··
•
6·
4
W
0
r
Octal
o
1
2
3
4
5
6
7
10-11
12-13
14-15
16-17
20
27
30
..
47
50
51
52
53
54
55
56
57
60
65
66-67
70
//////////////////////////////////////////////////
//////////////////////////////////////////////////
63 ////////////////////////////////////////////////// 77
d
s
Figure 8-7.
*1:
*2:
*3:
*4:
*5:
safe Store Stack Format - NS Mode
Fault Retry Flag - bit 1
Fault Tally Flag - bit 2
safe Store Stack Fault Flag - bit 9
Fault/Interrupt - bit 10
a = fault
1 = interrupt
Fault/Interrupt Code - bits 11-17
8-107
DZSl-OO
CLIMB
CLIMB
'\
10
1
···
·,
··
·•
···
··
··
·
··
·
·
··
01 00 <-SCR
Oil Oil <-ISR Bi 24
19JExtended Fault Reqister
HWMR
0
CPU
Fault
Reqister
1
•
•
Imaae of Fau1tina Instruction
1
2
•
3
11111111111111111////1/1111/111111111/1111/1/11/11
6
•
IR
4
Ie
15/1/11
181
2
5
*11*21111111*31*41
*5
10IRHUICP#ISCRI
SEGID
12
•
DSAR
111111111/111111 EWSN# 9
4
W
6 17
7
Relative Virtual Address
0
ISR
r 8- 9
W
d 10 - 11
ASR
0
r
s12-13
LSR
PSR
d
• 14 - 15
16 00000000000000000000000000000000000
SEGIDO
s
00000000000000000000000000000000000
to
SEGID7
00000000000000000000000000000000000
23 00000000000000000000000000000000000
24
DRO
· ·
·
·
···
39
40
41
42
43
44
45
46
47
48
51
52
54 - 55
56
8
0
·
W
0
r
d
s
··
·
·
··
··
Octal
0
1
2
3
4
5
6
7
10-11
12-13
14-15
16-17
20
27
30
to
DR7
47
50
51
52
53
A
54
55
Q
8
E
111111111111111111111111111111111111/11 56
27
Timer Reqister
11111111111 57
Mid-instruction Interrupt Data
60
(Stored on1v if IR bit 30 = 1)
11111111111111111111111111111111111111111111111111 65
LOR
66-67
GXO
70
1111111111111111111111111111111111111/111111111111
11/1111111111111111111/1111/1111/111111111/1111111
111111111111/111111111111111111111111/1111/1111111
111111111111111111111111111/11111111111111/1111111
to
GX7
ARO
63
64
77
100
to
71
AR7
107
72 111111111111111111111111111111111111//11/1/1111111 110
II/IIIIIIII//Reserved for Future Usel/IIIIII/I/III
79 11111111111111111/11111111111111111111111111111111 117
·•
•
·
Figure 8-8.
*1:
*2:
*3:
"'--j
safe Store Stack Format - ES Mode
Fault Retry Flag - bit 1
Fault Tally Flag - bit 2
SSSF Flag - bit 9
*4:
*5:
8-108
Fau1tlInterrupt - bit 10
o = fault 1 = interrupt
FaultlInterrupt COde - bits 11-17
DZ5l-00
'"
ruMB
CLIMB
SOme of the fields shown in Figures 8-7 and 8-8 are stored
only with a CLIMB instruction executed by hardware in
response to faults or interrupts, and are meaningless when
using the ~rogrammed ClJME instruction.
The following discussion explains the contents of the safe
store stack as illustrated in Figures 8-7 and 8-8.
Word 0
Bits 0-19
High Water Mark Register (HWMR) stored. The content
of the HWMR is the value in the register when the
ClJ ME instruct ion started.
Bits 20 to 35 Extended Fault Register
Word 1:
Upon occurrence of a fault, the CPU fault register
Word 2:
(
Upon occurrence of a fault, the image of the
faulting instruction
Word 3:
Reserved for hardware use
Word 4:
Bits 0 to 17
The instruction counter (IC) value is stored as
follows:
IC = IC + 2
Refer to section 6 for the description of the value
stored when a fault or interrupt occurs.
Bits 18 to 32
Indicator register (IR) contents.
Bits 33 to 35 Not used.
Word 5:
Bits 0 to 9, 18, 19
8-109
DZ5l-00
CLIMB
CLIMB
\.
Reserved for hardware use. When an interrupt or a
Connect, Timer Runout, Shutdown, or Missing Page
fault occurs, a 1 is stored in word 5, bit 9 to
indicate the· recoverable type. When other faults
occur, a 0 is stored in word 5, bit 9~
Bit 10
SSF (safe Store Stack fault flag).
6 for description of faults.
Refer to Section
Bit 11 to 17
These bits are meaningful only when faults or
interrupts occur. (Refer to Section 6, Faults and
Interrupts for details.)
Bits 19 to 20
CPU
number
Bits 22, 23
Stack Control Register
Bits 24 to 35
(SCR)
SEGIDOS)
Word 6:
Bits 0 to 16
The value stored here is the DSAR content when the
CLIMB instruction started.
Bits 17 to 26
Reserved for hardware use.
Bits 27 to 35
When a Missing Page fault occurs, the hardware
stores the effective working space number of the
virtual address which caused the fault. It is not
used in other cases.
Word 7:
When a missing page fault occurs, the hardware
stores the relative virtual address which caused the
fault. It is not used in other cases.
8-110
DZSI-OO
.. ~
(-
CLIMB
CLIMB
Words 8-47, 54-71:
As illustrated in Figure 8-7 for NS mode and Figure
8-8 for ES mode, the hardware stores register
contents. These contents consist solely of values
at the beginning of the CLIMB instruction. In
particular, when a segment descriptor is pushed onto
the argument stack during execution of the CLIMB
instruction, the safe stored ASR bound value is that
before the push operation.
When SCR = 10, bits 0 to 23 of the words 16 - 23,
are all zero, and the values of words 40 to 43 are
undefined.
When the ISR bit 24 immediately before the CLIMB
instruction equals 1 with the 24-word stack, bits 0
to 23 of words 16 to 23 are all zero.
Words 48-53:
(
Hardware stores information for restart of
instruction execution only in response to faults and
interrupts.
The information stored in this area is normally the
content of the pointers and lengths register when a
fault or interrupt occurs during execution of an
interruptible multiword instruction (when saved with
the IR bit. 30 set to ON). Even when the IR bit 30
is not set to ON, information is stored in this
area, for example, for a Missing Page fault. The
content of this area must not be changed by
software.
When software does not specify type T = 11 as the
entry descriptor for a fault or interrupt, the
system cannot return correctly.
Words 72-79:
Reserved for future used.
5. Loading the Registers
After the state is saved in the safe store stack, the
registers are changed as described below.
(
8-111
DZ51-00
CLIMB
CLIMB
a. Loading the Instruction Segment Register (ISR)
For an intradomain transfer, the standard descriptor
referenced by the Sand 0 fields of the instruction is
placed in the ISR. If the Sand D fields referenced a DRQ
(177n), then SEGIOn -> SEGIO(IS); otherwise, S and 0
--> SEGID(IS).
For an interdomain transfer, the descriptor pointed to by
the ISEGNO field of the entry descriptor is loaded into
the ISR. SEGID(IS) is set to S = 3, D = ISEGNO.
b. Loading the Instruction Counter
(Ie)
For an intradomain transfer, an effective address is
formed using the address field of the CLIMB instruction
and applying the indicated AR and/or tag field
modification. This 18-bit effective address is placed in
the instruction counter.
c. Loading the Linkage Segment Register
(LSR)
For an intradomain transfer, the linkage segment does not
change.
For an interdomain transfer, a standard descriptor from
the entry descriptor is placed in the LSR as follows:
o Base = Linkage base (LBASE) with zeros in the 10 most
significant bit positions
o Size = Linkage bound (LBOUND) extended with three 1
bits on the right and with zeros in the 7 most
significant bit positions
o WSR
o T
= WSR
(working space register)
=1
o Flags - Bits 20, 22, 23, 27, and 28 = 1
Bits 21, 24, 25, and 26 = 0
For an interdomain transfer, the 1S-bit entry location
contained in the entry descriptor is placed in the
instruction counter.
d. Argument Stack Register (ASR) and Parameter Segment
Register (PSR Generation
When E bit = 0 (pass no parameters) or when E bit
(pass parameters) and ORO type T = 1
8-112
=1
DZ51-00
(
CLIMB
CLIMB
o The new PSR is generated as follows.
10001
19
11111
8 11
11111
35
ASR Base
+
0
I
ASR Bound
0
I
P
=
0
I
I
New PSR Base
7 8
0
10------01
16 19
11111
P
o The new ASR base is generated as follows. (The new ASR
generation is independent of ASR flag bit 27.)
(
o When C(HWMR) = 0
ASR base -> New ASR base
o When C(HWMR) ':F 0
Araument Seqment
(AS )
ASR Base
+
=
10001
11111
--+<---------..I.I__-=La=s: :. t: :. . !.AS=. .;A~d:.: d:!r. : e:.: : s: :.s_ ___L.::::=~
11111
4 -_ _ _ _
\
+
Double-word
boundary
\
Bound fault
>OCcurs with
carry
\
=
=
\
\
\
\
=
Next avail.
\-1. __-:.:.:::.!:.....!!:::.:.:.-!:::.:::.:::-_
_1':::":::":::..L1 double-word
New ASR Base
000 word location
8-113
DZ5l-00
CLIMB
CLIMB
The new ASR bound and flat bit 27 are set to O.
When E bit = 1 (pass parameters) and ORO type
6, 12, or 14
= 0,
2, 4,
o The segment descriptor described with the PSR is
prepared by hardware as with the last P + 1 segment
descriptors in the argument segment as follows.
,,
,,
,,
Ar·aument
ASR Base
searnent (AS)
\
\
\
\
ASR Bound
HWMR
---->\
---------->
<--New PSR base
is set here
"\
j
P+l
<-New PSR bound
, is set here
\
--------
'New ASR base is set so as
to indicate next available
double-word location
o The descriptors to be framed by the PSR are the last
P+l descriptors in the descriptor segment pointed to by
ORO.
8-114
DZ51-00
CLIMB
CLIMB
The new PSR base is generated as follows.
o When COMm)
=a
ASR base -> new PSR base
o When C(HWMR) # a
ASR Base
10001'
Bound
+
a
19
I~~~~~I
11111
HWMR
+
fault
occurs
with
carry
=
a
35
New PSR Base
10001
The new PSR base shown above works as the start address in
the area where the segment descriptor is prepared as a
parameter.
8-115
DZ51-00
CLIMB
CLIMB
o The new PSR base is set to the value DRO base
bound - P as shown below.
o
+
DRO
32 35
DRO Base
10001
+
0
19
I
DRO Bound
11111
0
I
o
11
8
P
11111
=
35
New
PSR
Base
10001
The new PSR bound is generated as follows.
o
100---------01
19
16
7 8
11111
P
"
o The new base and bound values formed are loaded into
the PSR, framing the last P+1 descriptors of the
segment. Bits 20-35 of the first word of DRO (flags
field, WSR or WSN field, and T field) are copied to
the corresponding bit positions of the PSR.
The new ASR base is generated as follows:
o When C(HWMR) = 0
ASR
10001'
Base
o
+
11
I -----------------------------------------
Bound
fault
occurs
with
carry
-I~I/
=
o
35
New ASR Base
8-116
10001
DZ51-00
/
(
CLIMB
CLIMB
o When C{HWMR)
~
0
ASR
10001'
Base
+
o
19
+
Bound
fault
occurs
with
carry
I ~--------------------------------------o-I~I
---------------------o
35
10001
New ASR Base
The new ASR bound and flag bit 27 are set to O.
Independent of the E bit setting and DRO type, the HWMR is
set to o.
EXAMPLE:
This example illustrates how the HWMR protects the program
descriptors from one program from being accessed by
another program.
1. Program A
stores four
descriptors
on the argument
stack (SDRn)
~
______~__~ <-------------ASR Base
A - Dl
/------- Bound
/
A - D2
/
/
A - D3
/
/
A - D4
~
/
__________~ <-I <---------HWMR
(
8-117
DZ51-00
CLIMB
CLIMB
2. Executes an LDDn to copy the ASR to DRn
3. Executes a PAS ......-_ _ _~-..,.. <-------ASR Base
instr. to modify
A - Dl
/ - Bound
the ASR bound
/
A - D2
/
01-----.."....---1-
A -
D3
A - D4
4. calls program B
<--------/
..L..-_ _ _ _ _......
<----HWMR
-r---A::--_~D=-:l:-----r-
< - - - - ASR Base
/ -- Bound (Prog • A)
/
A - D2
/
+-----~~--~ <-------/
A - D3
A -
D4
<--ASR Base/Bound/HWMR
(Prog. B)
5. Program B
stores three
descriptors
on the
argument stack
A - Dl
A - D2
A - D3
<------------ASR Base
/-- Bound (Prog. A)
/
<---- ---I
/
A - D4
B - DI
<---
- - - ASR Base
/----- Bound (Prog. B)
/
B - D2
/
/
B - D3
/
<-I <----- HWMR
8-118
DZ51-00
CLIMB
CLIMB
6. Return to Program A
ORn Base------->
Bound
A - 01
<-------------ASR
Base
/ - Bound (Prog. A)
/
\
A - D2
\
/
<-----/
\
A - D3
\
\
A - D4
\
\-->
B - Dl
<---------HWMR
B - D2
B - D3
Because the HWMR remembers the highest level reached in
the argument stack by an individual program, and uses it
to generate the ASR base for a new program, there can be
no overlap of descriptors in the argument stack. Security
cannot be violated.
e. Loading the Pointer Registers
If type 11 entry descriptor was referenced by the Sand D
fields of the IClJMB instruction, all pointer registers
are set to the value of the target IS as follows:
ISR
-->
DRO through DR7
SEGI D (I S)
->
SEGI DO through SEGI 07
00 •••• 0
-->
ARO through AR7
NOTE: When the entry descriptor type is other than T = 11,
the pointer register content remains unchanged.
However, unless the ISR is copied into the DRn with
the ICLIMB instruction altering the ISR bit 24, the
content of ARn, and SEGIDn is undefined.
f. Loading Xa/GXo
o If bit 18 of the C field of a ClJMB instruction is 1
and the operation is an interdomain transfer, the load
is as follows.
8-119
DZ51-00
CLIMB
CLIMB
Old ISR
Bit 24
New ISR
Bit 24
XO
0
0
*C(XO> <-YO-17
0
1
*Undefined
(meaningless)
1
0
C(XO> <--Yl6-33
1
1
Undefined
(meaningless)
GXO
Undefined
(meaningless)
C(GXO>0-17 <-- 0
C(GXO>l8-35 <-- YO-17
**Undefined
(meaningless)
**C(GXO)o-l <-- 0
C(GXO)2-35 <-- YO-33
o If xo is to be stored in the safe store stack, the content
of XO at the start of a CLIMB instruction is stored.
o If GXO is to be stored in the safe store stack, the
content of GXO at the start of a CLIMB instruction is
stored.
o If bits 18 of the C field of a CLIMB instruction is 0, or
the operation is not an interdomain transfer, the load is
as shown below.
Old ISR
Bit 24
New ISR
Bit 24
XO
0
0
0
1
Unchanaed
Unchanged
(meaningless)
1
0
C(XO)<-- C(GXO>l8-35
1
1
Unchanged
(meaninaless)
GXO
Unchanged
(meaninaless)
C(GXO)0-17 <- 0
C(GXO>l8-35 <- C(XO)
Unchanged
(meaningless)
Unchanaed
The above table also applies to the fault/interrupt CLIMB.
8-120
DZ51-00
(
CLIMB
CLIMB
NOTE: When the CLIMB instruction alters bit 24 of the ISR, the
content of XI-X7/GXI-GX7 is undefined.
6. Settina Mode Indicators for System Entry CLIMB
When the CLIMB is a system entry (PMME) where S = 0 and D =
1760 (octal), the Master mode indicator is set to ON. If it
is not a system entry and bit 19 of the C field equals 0, the
processor is set to Slave mode and the Master mode indicator
is set to OFF. If it is neither, the mode remains
unchanged. When this CLIMB is executed as a response to a
fault or an interrupt, the Master mode indicator is always
set to ON.
Outward CLIMB (RET/OCLIMB) C Field Bits 22 and 23
= 01
1. In the OCLIMB version of the CLIMB instruction, a return
occurs according to the last frame stored in the safe store
stack.
2. The E, P, S, and D fields, and bits 19, 20, and 21 of the C
field are ignored.
(
3. The data stack clear flag (DSCF) of the option register is
checked. When DSCF = 1, the data stack area used with the
procedure executing the outword CLIMB is cleared. The
cleared area is shown by shading in the diagram below.
DSDR
Base
\
\
\
~~~~~~~~~~<--DSAR
value restored with OC1JMB
11111111111111111/// \
1111111111/11/1/1111
Cleared area
111111111/111/111/1/
1111111111111/1111/1 I
<--DSAR value when this OCLIMB started
\
I
\
Bound \
\
\
\
\
\~----------------~
o In this case, a security fault, class 1 occurs if the DSAR
at the start of the CLIMB is less than the restored DSAR.
(
o If a missing page fault occurs while the data stack is
being cleared, the hardware saves the state at the time
the fault occurred. When the operating system loads this
missing page and returns to the executing procedure, the
clearing of the data stack area is re-executed correctly.
8-121
DZSl-OO
CLIMB
CLIMB
4. When an OClJMB starts, the SCR value determines the number of
registers allowed. Registers are restored with the SCR
content indicated in the list below.
IPR fault occurs if the option register safe store bypass
flag (SSBF) is ON at the time.
An
When the SCR
restored:
= 00
(binary), the following registers are
Instruction Counter (IC)
Indicator Register (IR)
Stack Control Register
(SCR)
Instruction Segment Identity Register -
~D(IS)
Data Stack Address Register (DSAR)
Instruction Segment Register (ISR)
Linkage Segment Register
Argument Stack Register
(LSR)
(ASR)
Parameter Segment Register (PSR)
When SCR = 01 (binary), all the registers that meet the
checks for SCR = 00 (binary) are restored, plus AR 0-7 and
SEGID 0-7.
When SCR = 10 or 11 (binary), the registers for SCR = 01
(binary), the DRO-DR7, XO-X7/GXO-GX7, A, Q, E, and LOR are
restored. When word 5, bit 9 of the safe store stack is 1,
the pointers and lengths register and the fault recovery
information are restored.
In all cases, the processor number and the timer register are
not restored.
8-122
DZ51-00
(
CLIMB
CLIMB
5. The base and bound values of the safe store register (SSR)
are adjusted according to the new values placed in the SCR
from the safe store stack as follows:
Base
SSR Bound
00
-16 words
+16 words
01
-24 words
+24 words
10
-80 words
+80 words
11
-64 words
+64 words
SCR(bin.)
6. Loading DRO-DR7
When an OClJMB uses 16 or 24 words for the safe store stack
(i.e., the old SCR value = 00 or 01) and then transfers to
Slave mode, the new ISR value is loaded into ORO-OR7.
7. Loading XO/GXO
(
When the OCLIMB instruction C field bit 18 = 1, the effective
address specified with the instruction, in accordance with
bit 24 of the ISR restored from the safe store stack, is
loaded into XO/GXO. (Refer to table for loading XO/GXO when
bit 18 = 1 under ICLIMB.)
When the OClJMB instruction C field bit 18 = 0, with a
64-word or 80-word safe store stack, the safe store stack
content is restored into XO/GXO. with other than a 64-word
or 80-word safe store stack, the content of XO/GXO is
determined as shown in the table for loading XO/GXO when bit
18 = 0 under the ICLIMB discussion.
NOTE: When the contents of XI-X7/GXI-GX7, ARn, and SEGIDn are
not restored with the OClJMB instruction that alters
bit 24 of the ISR, those contents are undefined.
8. The IC is restored from the safe store stack as follows:
From NS or ES to NS or ES mode
Word 40-17 --> C(IC)0-17
The HWMR is restored from word 00-19
(
8-123
DZ51-00
CLIMB
CLIMB
9. Control is passed to the instruction indicated by the IC and
ISR.
10. When the indicator register is restored (with the value
stored in the safe store stack), the Master mode bit may be
set to ON.
11. Outward CLIMB is interruptible during execution when the
following conditions are satisfied.
o The option register data stack clear flag (DSCF)
o The interrupt inhibit bit
the instruction).
=0
= l.
(bit 28 of the first word of
o If the interrupt inhibit bit = 1, interrupt is not
permitted for this instruction during execution.
Interpretation of bit 28 is only valid at the time of
outward CLIMB. With the other three CLIMB variations,
interrupt is not accepted during execution and the value
of bit 28 is not affected by execution of the instruction.
o The procedure executing this outward CLIMB used the data
stack area.
If there is no area to be cleared (i.e., if the restored
DSAR value is equal to the current DSAR value) despite the
above two conditions being satisfied, this OCLIMB is not
interruptible during execution.
When the OCLIMB is being executed and the above three
conditions are satisfied, the processor samples interrupt
at suitable times and responds to any interrupt received,
to ensure that a Lockup fault does not occur while the
data stack is being cleared. At response to the
interrupt, the processor saves the current state in the
safe store stack and the interrupted OCLIMB is re-executed
normally. The clear operation is restarted correctly from
the point at which it was interrupted.
8-124
DZ51-00
«
CLIMB
CLIMB
Lateral Transfer (LTRAS/GCLIMB) C Field Bits 22 and 23 = 10
In the GClJMB version of the ClJMB instruction, the safe store
register and the parameter segment register remain unchanged.
Also, the base and bound of the argument stack register remain
unchanged. The HWMR is not stored in the safe store stack.
1. The bit in the E field is not interpreted and the SCR remains
unchanged.
2. The GCLIMB may be an inter- or intradomain transfer that is
determined by the descriptor referenced in the S and D
fields. This version functions as the IClJMB, except as
indicated. since the state of the processor is not saved,
control cannot return to an instruction executing the GCLIMB.
3. Because the processor state is not Saved, the procedure
executing the GCLIMB cannot return correctly with an OCLIMB.
c:
If the descriptor referenced by the Sand D fields of the GCLIMB
instruction is a type 11 descriptor, the pointer registers are
set to the state of the target instruction segment. When the
type is not 11, the pointer register remains unchanged. If T is
not 11 when the GCLIMB instruction is altering bit 24 of the
ISR, the pointer registers are undefined.
Lateral Transfer (PCLIMB/LTRAD) C Field Bits 22 and 23
= 11
The execution of the PCLIMB version is identical with that of
ICLIMB, except for the following:
1. The CPU state is not saved in the safe store stack.
2. The HWMR is not saved in the safe store stack.
3. The SCR remains unchanged.
8-125
DZ51-00
CLIMB
CLIMB
If the descriptor referenced by the Sand D fields is a type 11
descriptor, the pointer registers are set to the state of the
target instruction segment. When the type is not 11, the
pointer register remains unchanged. If T is not 11 when the
PCLIMB instruction is altering bit 24 of the ISR, the pointer
registers are undefined.
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
I LLEX;AL EXECUTES: XEC
or XED
I NDI CATORS:
Master Mode - See notes below and discussion of "C19, Slave
Mode" in earlier pages of the CLIMB explanation.
NOTES:
1. Any of the following conditions cause an IPR fault:
o If illegal repeats or executes precede modifications
o If illegal address modification is used
o I f the base and bound fields of the instruction segment
descriptor are not modulo 32 bytes, of if flag bit 27 =
1 (bound valid) and the bound is not 31 modulo 32 bytes
o If the Sand D fields are S = 0 and D = 1760 or 1761
(octal), and the descriptor from the system entry
location is not an entry descriptor
o If the descriptor referenced in the Sand D fields is
not a standard, entry, or dynamic linking descriptor (T
= 0, 5, 8, 9, or 11)
o If the type of the descriptor referenced with the Sand
D fields is T = 1 or 3, and the segment descriptor
obtained from this descriptor is not an entry or
dynamic linking descriptor
o If the Sand D fields of the vector or the CLIMB
instruction are S = 0 and D = 1761 (octal)
o If the transfer destination ISO type T is not 0
8-126
DZ51-00
\,
j
(
CLIMB
CLIMB
o If a normal or extended shrink is specified for a
segment descriptor placed in the address segment and
the pushed segment descriptor type is illegal (T = 5, 7
to 11, 13, 15)
o If a Return Climb is specified and the safe store
bypass flag in the Option Register = 0
o If E = 1 and DRO contains a descriptor of type T
5, or 7-11, 13, or 15
= 3,
o If the Sand D fields of the vector are S = 0 and D =
1760 (octal)
2. A Command fault may occur as follows.
o If the Sand D fields of the vector are S = 0 and D =
1763 or 1764 (octal) and the processor is not in
Privileged Master mode
o If WS 0 is specified and the processor is not in the
Privileged Master mode
(
o If WSR 0 is specified and the processor is in Slave
mode (except during the access for the ISO when the
system entry (PMME) is specified)
3.
A
Bound fault may occur as follows:
o If in the ICLINB version of the instruction, field E =
1, DRO type = 1, and (p + 1) is greater than the DRO
bound
o If the transfer destination ISO flag (bit 27) of the
instruction segment descriptor is 0 (empty segment)
o I f a carry occurs in forming a new argument stack
register (ASR) or parameter segment register (PSR)
base
o If an access for a vector or a descriptor exceeds the
upper or lower bounds of the specified segment, or if
the bound is not valid (flag bit 27 = 0), or if there
is an attempt to address the argument (for the push)
and the temporary ASR bound + 1 byte > 8192 bytes
(
8-127
DZ51-00
CLIMB
CLIMB
o If on an access to memory an associative memory error
occurs
4. A Security Fault, Class 1 may occur as follows.
o If the ISD flag bit 26 = 1 (Privileged mode) and the
processor is in Slave mode and the ClJMB did not result
from a fault, interrupt, or system entry (PMME)
o If, at the end of the CLIMB, ISR flag bit 26 = 1
(Privileged) and either indicator register bit 28 = 0
(Slave) or a nonhousekeeping page is accessed for the
next instruction
o If at the end of the CLIMB, indicator register bit 28
o (Slave) and a housekeeping page is accessed for a
vector
o
5.
A
=
f the page to be accessed is a nonhousekeeping page
(PTW flag bit 32 = 0)
I
Security Fault, Class 2 may occur as follows:
o I f flag bit 25 of the instruction segment descriptor is
o (no execute permission)
o If read flag bit 20 of the descriptor = 0 for any
access to a segment for a vector or descriptor (but not
ASR)
o I f a working space violation occurs
o If the specified page (for the push to ASR) does not
have write permission
NOTE: In the SDRg instruction, the ASR needs neither write
nor store permission.
6. A Missing Segment fault occurs if flag bit 28 of the
descriptor = 0 for any access to the ASR, or to a segment
for a vector or descriptor.
7. A Missing Page fault occurs for any access to the ASR, or
to a segment for a vector or descriptor, if flag bit 30 of
the PTW for the accessed page = O.
8-128
DZ51-00
/
CLIMB
CLIMB
8. A Missing Space fault occurs for any access to the ASR, or
to a segment for a vector or descriptor, if bit 20 of the
PTDW = O.
9. A Safe Store Stack fault occurs if the SSR bound < 239
words + 3 bytes as a result of the SSR update adjustment.
10. When the access of the 150 from the LSD formed from the
entry descriptor, the same fault checks are made as listed
above, except that if the CLIMB resulted from a fault,
interrupt, or system entry (PMME), the WS = and WSR 0
Command fault checks are not made. (The entry descriptor
does not contain flag bits 20, or 27.)
SUMMARY OF CLI MB I NSTRUCTI ON FORMAT:
o0
1 1
7 8
0
023
II
(
Op
I
ADDRESS
Code
2 2 2 2 3
6 7 8 9 0
I+H
713(1)
First Word
o1
o0
o1
1 1 1 2 2 2 2 222
7 8 9 o 1 2 3 456
9 0
H
P
3
6
I
UNUSED
I~I ~:
Second Word
I~ I I
S
3
5
I
TAG
3
5
D
7
2
I
The control fields are defined as follows:
E
= 0
-
No parameters are passed
E
= 1
-
Pass P+l parameters (ICLIMB, PCLIMB only)
P
= N-l -
Number (minus 1) of descriptions or vectors to pass
if E = 1
XO/GXO
= 0
-
CLIMB will not affect XO/GXO.
XO/GXO
=1
-
If entry descriptor (T = 8, 9, or 11) is referenced
or OCLI MB is executed, XO/GXO is loaded with the
effective address designated by the address tag and
AR fields of the CLIMB instruction.
(
8-129
DZ51-00
CLIMB
CLIMB
(\
\
)
"""------_/
SSLV
= 0
-
set Slave mode
SLV
=1
-
Do not change Master mode indicator
TYP
= 00
-
ICLIMB (or PMME)
TYP
= 01
-
OCLI MB
TYP
= 10
-
GCLIMB (LTRAS) - Transfer with same ASR and PSR.
= 11
-
PCLIMB (LTRAD) - Transfer with new ASR and PSR.
TYP
Do
not save processor state.
Do
not save processor state.
S, D
-
Target SEGI D
CODING FORMAT:
Coding of a CLIMB varies with the version of the ClJMB
instruction being executed.
The following list contains each of the five versions of the
CLIMB instruction with their respective fields, which are
defined below. The underlined fields are required; all
others are optional.
ICLIMB - entry, count, effective address, flags
PCLIMB - entry, count, effective address, flags
GCLIMB - entry, effective address, flags
OCLIMB - effective address
PMME
- effective address, count, flags
The fields in the CLJMB instruction are described below:
entry
- Name of an entry or a 12-bit number (SEGID) that
identifies a descriptor specifying a new linkage
segment and instruction segment or the same
linkage segment and an instruction segment.
8-130
DZ51-00
\.~
(
CLIMB
CLIMB
count
- Decimal expression representing a value in the
range 0 <= count <= 512. This value indicates
the number of parameters or descriptors (one for
each argument) pointed to by PRO. The fir-st of
these is at the location indicated by pointer
register zero. A value of zero means that no
arguments, and consequently no vectors or
descriptors, are present. If no value is given,
zero is assumed.
effective - The effective address may include a tag
address
pointer designation. When this occurs, the field
must be enclosed by parentheses; e.g., (address,
tag) or (address, tag, pointer). The effective
address is used to establish the next instruction
location, but only when the entry identifies a
descriptor that does not specify a linkage
segment. The effective address is a requirement
only for the PMME version to designate the Master
mode entry.
(
If the entry identifies a descriptor that
specifies a linkage segment (entry descriptor),
index register 0 may be loaded with the effective
address. If the entry identifies a descriptor
that does not specify a linkage segment (standard
descriptor), this address is added to the base of
the instruction segment (described in the
descriptor) to establish the next instruction
location and may be loaded in index register O.
If bit 18 of field C is zero or this address is
omitted, the content of the effective address
field is not loaded in index register O. Note
that an explicit zero is required to load index
register 0 with a zero, since a null field
prevents register loading.
MASTER - Sets bit 19 of the second word
No flags are used for the OCLIMa version.
NOTE: PMME is synonymous with ICLINB with 17608 coded in the
entry field.
(
8-131
DZ51-00
CLIMB
CLIMB
flags
EAXO
- Sets bit 18 of the second word
The keyword BAKO indicates that the
effective address field is to be loaded
in index register 0 or general index
register o.
NEAXO - Clears bit 18 of the second word
SLAVE - Clears bit 19 of the second word (for
PMME, bit 18 of the second word is
forced on, bit 19 is ignored by the
hardware)
The keyword SLAVE indicates that the
processor will enter Slave mode upon
change of domain. If this field is
omitted, the mode is not changed, except
for the PMME version which is always set
to Privileged Master mode.
f both keywords are needed, the field
must be enclosed by parentheses with a
comma separating the keywords: (e.g.,
BAKO, SLAVE).
I
EXAMPLES:
1
*
8
16
INHIB
OFF
32
ICLIMB
ODDF . NULL
NEPRl LDD
SDR
LDD
SDR
LDD
SDR
LDD
MLR
PO,DSTKS
PO
Pl,ODRSH
Pl
Pl,IALPS
Pl
Pl,ISRS
(1),(1)
shrink data stack (64 words)
shrink safe store
ISR,ASR,LSR,PSR
ISR (R,W)
copy safe store frame to data stack
O,O,256,P.SSR
O,O,256,PO
PO,.ASR,DL
copy ASR to PO
LDP
climb exception procedure
ICLIMB .DR+4,3"SLAVE
l8/,09/7l3,l/l,l/O,l/O,6/M.
VFD
1/l,9/3-1,8/0,l/.N,l/.O,2/0,2/0,12/.DR+4
VFD
ADSC9
ADSC9
*
*
j
8-132
DZ5l-00
(
CLIMB
CLIMB
1
8
16
32
GCLI MB/I eLI MB
*
INHIB
TRVCEL NULL
ON
NOP
EPPRO
2,IC
,DL
1,IC
TRA
.CRTRV+12, ,P.CR
EPPRO
EPPRO
1,IC
2,IC
1,IC
TRA
.CRTRV+14"P.CR
TRA
TRA
.TROPN (system domain only)
.TROPN none (system domain only)
.TROPN all (slave domain)
**,DL
.TRPUT (system domain)
TPUTSY- •• DISP"P7
NOP
, DL
* . TROPN all macros removed
,DL
NOP
.TROPN extension
TRVC03 GCLIMB **,TOPNG
lS/TOPNG,09/713,1/1,1/O,1/0,6/M.
*
VFD
1/O,9/0,S/O,1/.N,1/.O,2/0,2/2,12/**
*
VFD
LDD6
DP.OTE"P.SSL
.TROPN all for slave domain extension
ICLIMB .DR6
lS/,09/7l3,1/1,1/O,1/O,6/M.
*
VFD
1/O,9/0,S/O,1/.N,1/.O,2/0,2/0,12/.DR6
*
VFD
0, ,PO
TRA
TRVCOI LDP7
TRA
(
S-133
DZSl-OO
CMG
CMG
CMG
I
Compare Magnitude
405 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
IC(A)I :: IC(y)l: C(A), C(Y) unchanged
EXPLANATION:
This instruction compares the magnitude of signed algebraic
numbers. For example, if -1 and +1 are compared, they are
considered equal and the zero indicator is set ON.
I LLEGAL ADDRESS
MODI FI CATIONS:
None
I LLEGAL REPEATS:
None
I NDI CATORS:
Zero
Negative
0
1
0
0
0
1
Relationship
C(A)
C(A)
C(A)
8-134
C(Y)
C(y)
=
< C(y)
>
, . ."".
DZ51-00
(
CMK
CMK
CMK
211
Compare Masked
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
For i = 0 to 35,
C(Z)i
= C(Q)i
(0)
AND [C(A)i XOR C(Y)i]
C(A), C(Q), C(Y) unchanged
EXPLANATION:
This instruction compares the corresponding bit positions in
C(A) and C(Y) to determine whether they are equal or not.
Bits for which the corresponding bit of Q is I are masked and
not compared.
The zero indicator is set ON if the comparison is successful
for all bit positions:
if for all i = 0,1, ••• ,35
either C(A)i = C(Y)i
or
C(Q)i = 1 is established.
otherwise, the zero indicator is set OFF.
(
The negative indicator is set ON if the comparison is
unsuccessful for bit position 0:
if for C(A)O # C(Y)O
and
C(Q)O = 0
otherwise, the negative indicator is set OFF.
ILLEGAL ADDRESS
MODI FI CATIONS:
None
I LLEGAL REPEATS:
None
INDICATORS:
Zero -
If C(Z) = 0, then ON: otherwise, OFF
Negative -
If bit 0 of C(Z)
8-135
= 1,
then ON; otherwise, OFF
DZ51-00
CMK
CMK
EXAMPLE:
In the following example, the comparison is equal after
execution of CMK, and the TZE exit is taken. Only the 2s in
NUMBER and DATA are compared; all other bits are masked by Is
in the Q-register.
1
MASK
8
16
LDQ
MASK
LDA
CMK
TZE
NUMBER
DATA
OCT
777777777707
300333333326
666666666625
NUMBER OCT
DATA OCT
OUT
/
8-136
DZ5l-00
CMPA
CMPA
Compare with A-Register
CMPA
Single-word instruction format (see Figure 8-1)
FORMAT:
OPERATI NG
115 (0)
MODES:
SUMMARY:
Any
C(A) :: C(Y); C(A) and C(Y) unchanged
I LLEGAL ADDRESS
MODI FI CATIONS:
None
I LLEGAL REPEATS:
None
INDICATORS:
Algebraic comparison (Signed Binary Operands)
Zero Negative
o
o
1
o
o
carry
o
o
o
1
1
o
1
1.
1
o
Re1at ionsh i P _---.:S::;.:i:.;::gna:::
. C(A) > C(Y) C(A)0=O,C(Y)1=1
C{A) > C{Y}\
C{A) = C(Y) >C(A)O=C(Y)o
C{A) < C(Y)/
C(A) < C(Y) C(A)O=1,C(Y)0=O
Logical comparison (Unsigned positive Binary Operands)
carry
o
1
o
1
1
o
8-137
Relationship
C(A) > C{Y)
C(A) = C(Y)
C(A) < C(Y)
DZ5l-00
CMPAQ
CMPAQ
CMPAQ
Compare with AQ-Register
117 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Any
SUMMARY:
C(AQ) :: C(Y-pair); C(AQ) and C(Y-pair) unchanged
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
None
INDICATORS:
Algebraic comparison (Signed Binary Operands)
zero Negative carry
o
o
1
o
o
o
o
o
1
1
1
1
1
Sign
Relationship
o
C(AQ)
C(AQ)
C{AQ)
C(AQ)
C(AQ)
o
> C(Y)
> C(Y)\
C(AQ)O=O,C{Y-pr)O=l
= C(Y) >C(AQ)o=C(Y-pr)O
< C(Y)/
< C(Y) C(AQ)O=l,C(Y-pr)O=O
Logical comparison (Unsigned Positive Binary Operands)
carry
o
1
o
NOTE:
1
1
o
Relationship
C(AQ) > C(Y-pr)
C(AQ) = C(Y-pr)
C(AQ) < C(Y-pr)
An Illegal Procedure fault occurs if illegal address
modification is used.
8-138
DZSI-OO
CMPB
CMPB
(
CMPB
Compare Bit Strings
FORMAT:
a
0
a
1 1
1 1
a1
1
I FI 0---------------0 I
066 (1)
Op
Code
7 8
MF2
a a0
a 23
066(1)
I
a aa
NFl
3
2
0
1 1 1 2 2 2
7 8
9
a
3
5
R1
3
2
3 4
3
5
N2
C2 B2
Y2
I
N1
Y2
CODING FORMAT:
I I
0-------
Y1
023
AR#
I
5
1 1 1 2 2 2
7 8 9 0 3 4
C1 B1
(
3
7 8 9
Y1
AR#
2 2 2
0-------------0
R2
The CMPB instruction is coded as follows:
1
8
16
CMPB
BDSC
BDSC
(NF1),(MF2),F
LOCSYM,N,C,B,AM
LOCSYM,N,C,B,AM
(Refer to section 7 under Multiword Instructions for
description of Multiword Modification Field.)
(
OPERATI NG MODES:
Any
SUMMARY:
C(string 1) :: C(string 2)
...
8-139
DZ51-00
CMPB
CMPB
EXPLANATION:
I LLEGAL ADDRESS
The string of bits starting at location YCBl is logically
compared with the string of bits starting at location YCB2
until an inequality is found or until the larger tally (Ll or
L2) is exhausted. If Ll is not equal to L2, th~ fill bit (F)
is used to pad the least significant bits of the shorter
string. The contents of both strings remain unchanged.
MODIFICATIONS:
DU, DL for NFl and MF2
I LLEGAL REPEATS:
RPT, RPD, RPL
Carry
I NDI CA'l'ORS:
NOTES:
Relationship
o
o
C(string 1) < C(string 2)
1
1
C(string 1)
o
1
C(string 1) > C(string 2)
= C(string
2)
1. If L1 or L2 = 0, both the Zero and carry indicators are
turned ON, but no Illegal Procedure fault occurs.
2. An Illegal Procedure fault occurs if DU or DL
modifications are used for NFl or NF2 or if an illegal
repeat is used.
I",
8-140
DZ51-00
(
CMPB
CMPB
EXAMPLES:
1
8
CMPB
BDSC
BDSC
TRC
USE
FLD1
FLD2
OCT
OCT
32
, ,I
FLD1,4S,O,O
FLD2,48
EQU.GR
CONST.
0,777000000000
0,777000000000
fill bit 1 option
FLDl operand descriptor
FLD2 operand descriptor
FLD1 equal/greater than FLD2
bits compared (octal representation)
o 0 000 0 0 0 0 0 0 0 7 7 7 7
o 000 0 0 0 0 0 0 0 0 777 0
Result - FLD1 > FLD2
FLD1,36,O,O
FLD2,19,l,3
EQUAL
FLD1GR
FLD1LS
CONST.
18/-1
12/0,19/-1
no options
FLD1 operand descriptor
FLD2 operand descriptor
FLD1 = FLD2
FLD1 > FLD2
FLD1 < FLD2
bits compared (octal representation)
7 7 777 7 0 0 0 000
7 7 777 7 400 000
Result - FLD1 < FLD2
USE
CMPB
BDSC
BDSC
TZE
TRC
TRA
FLD1
FLD2
16
USE
VFD
VFD
USE
EXAMPLE WITH ADDRESS MODIFICATION:
1
8
EAX2
EAX6
EAX4
AWDX
CMPB
BDSC
ARG
TZE
USE
FLD1 VFD
FLD2 VFD
INDSCR BDSC
USE
32
16
12
6
FLD1
0,4,4
(l,l"X2},(,,1)
O,X6,O,O,4
INDSCR
EQUAL
CONST.
12/0,6/1
24/0,6/1
FLD2,9,2,6
load FLD1's bit modifier into X2
load FLD1's length into X6
load FLD1's address into X4
put FLD1's address into AR4
with modification
FLD1 operand descriptor
pointer to FLD2's indirect descriptor
FLD1 = FLD2
bits compared
memory contents
7 7 0
000077000000
7 7 0
000000007700
FLD2 indirect operand descriptor
Result - FLD1 = FLD2
(
8-141
DZS1-00
106
Compare Alphanumeric Character Strings
CMPC
(1)
FORMAT:
o
(
0 0
8 9
FILL
1
0
1 1
7 8
1
1
0
0
I
I I
MF2
Code
2
3
2
Y1
0
0--
Y1
a aa
1 1 2 2
7 8 a1
023
0
2 2
R1
3
2
3 4
3
5
N2
Y2
CODING FORMAT:
3
5
N1
CNl TAl
AR
MF1
1 1 2 2 222
7 8 o 1 234
2 3
AR
3
106(1)
I
000
o
Op
CN2
Y2
0-----------------0
R2
The CMPC instruction is coded as follows:
1
8
16
CMPC
AD5Cn
ADSCn
LOCSYM,CN ,N ,AM
LOCSYM,CN IN,AM
(MFl ) (MF2 ) ,FI LL
I
(Refer to Section 7 under Mu1tiword Instructions for
description of Mu1tiword Modification Field.)
8-142
DZ51-00
/
(
CMPC
CMPC
OPERATI NG MODES:
Any
SUMMARY:
C(string 1) :: C(string 2)
EXPLANATION:
starting at location yel, the string of alphanumeric
characters of type TAl is logically compared with the string
of alphanumeric characters of assumed type TAl that starts at
location YC2 until either an inequality is found or until thelarger tally (Ll or L2) is exhausted. If Ll is not equal to
L2, the FILL character is used to pad the least significant
characters of the shorter string. The contents of both
strings remain unchanged. Bits 21-23 of descriptor 2 are not
interpreted.
Bits 0-8 are compared for the FILL character to be used to
pad the least significant characters of the shorter string.
If a character string is a 6- or 4-bit character, zeros are
inserted at the left of each to produce 9-bit characters for
comparison.
I LLEGAL ADDRESS
(
MODIFICATIONS:
DU, DL for MFI and MF2
I LLEGAL REPEATS:
RPT, RPD, RPL
Carry
I NDI CATORS:
NOTES:
Relation
o
o
C(string 1) < C(string 2)
1
1
C(string 1)
o
1
C(string 1) > C(string 2)
= C(string
2)
1. An Illegal Procedure fault occurs if DU or DL modification
is used for MF1 or MF2 and if there are illegal repeats.
2. If Ll or L2 = 0, the zero and carry indicators are
affected as illustrated under Indicators.
('
8-143
DZ51-00
CMPC
CMPC
EXAMPLE:
1
8
CMPC
16
32
, ,020
compare with blank fill
field 1 operand descriptor
field 2 operand descriptor
both fields equal
field 1 greater
field 1 less
characters compared
ADSC6
ADSC6
FLOl,O,6
FL02,4,4
TZE
D;JUAL
TRC
FLOIGR
NULL
USE
CONST.
FLOI Bel
l,ABCJ)
FLD2
Bel
ABCDlSiS
ABCDiSiS
2, XXXXABCDXXXX
Result - FLOI
USE
8-144
=
FL02
DZ51-00
CMPCT
CMPCT
Compare Characters and Translate
CMPCI'
166
(1)
FORMAT:
1 1
7 8
0 1 1
8 9 o1
0
0
0
I
FILL
IdlH
I
166(1)
Y1
CN1
H
3
5
I
NFl
TAllO
3
5
N1
Y1
AR#
o
o
222
789
1 1 222 2 2
7 8 0 1 2 3 4
0
2
0
0
NF2
Op COde
1 1 2 2 2 2 2
7801234
0
2
3
5
Y2
CN2
AR#
0
0
N2
Y2
o
1 1 2 2 2 2 2
7801234
o
22333
89012
3
5
Y3
0----------------0 AR 0--0
AR#
REG
Y3
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
(
8-145
DZ51-00
CMPCT
CMPCT
OPERATl NG MODES:
Any
EXPLANATION:
Starting at lOcation YCl, the string of alphanumeric
characters of type TAl is logically compared with the string
of alphanumeric characters of assumed type TAl that starts at
location YC2, until either an inequality is found or until
the larger tally (L1 or L2) is exhausted.
If an inequality is found, the next action depends on d1 and
d2. If dl and d2 = 0 then both characters are
transliterated and the resulting characters compared. This
is accomplished as follows.
I
The character from the string starting at YCl and the
character from the string starting at YC2 are each used as an
index to a table of 9-bit characters starting at location
Y3. The two characters thus taken from the table are
compared, the indicators set as indicated below, and the
instruction terminates. For the case dl = d2 = 1, no
transliteration takes place: the indicators are set according
to the way the two original characters compared. When dl F
d2, one character is translated and the other is not, and
then the two characters are compared. For example, if dl = 1
and d2 = 0, the character from the string starting at YC2 is
transliterated (as described above> and compared with the
character from the string starting at YCl and the indicators
are set accordingly.
Note that a 9-bit compare is always made. If dl F d2 and the
nontranslated character is a 4- or 6-bit character, then the
upper bit positions of the character are zero-filled for the
9-bit compare.
If Ll F L2, fill characters are used to fill the low-order
character positions of the shorter string. The contents of
both strings remain unchanged.
The transliteration table must begin at a word boundary at
character position O. The index,' which is expressed by the
number of 9-bit characters, is added to the starting word
address of the table. The beginning address of the table is
calculated in the same manner as is any normal address
modification. However, the computed address is used as word
address, with character position ignored, and the index is
added to this word address as a 9-bit character number.
Refer to the MVT instruction specifications for details on
generating the transliteration table address when address
register modification is specified.
/"',
I
""'.--/
8-146
DZ51-00
CMPCT
CMPCT
ILLEGAL ADDRESS
NODI Fl CATIONS:
DU, DL for NFl or MF2
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
Let Cl = C(last char from string 1, translated if dl =
Let C2 = C(last char from string 2, translated if d2 =
carry
o
1
o
NOTES:
o
1
1
0)
0>
Relationship
Cl < C2
Cl = C2
Cl > C2
1. When L1 or L2 = 0, the zero and carry indicators are still
affected as indicated in the above table. If L1=L2=O, both
the zero and carry indicators are turned ON.
2. A 9-bit character (zero-filled as appropriate) and/or the
full 9 bits of the table entry are used in all
comparisons.
3. The CMPCT instruction is intended for comparisons in
situations where the character collating sequence is
different from the sequence of character codes.
4. If L1 < L2, and type TAl is 4- or 6-bit, the low-order 4
or 6 bits of the 9-bit FILL character in the instruction
are defined as a table index, respectively.
5.
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
(
8-147
DZ5l-00
CMPN
CMPN
Compare Numer ic
CMPN
303
(1)
FORMAT:
1
0
0
0
1
1
1 1
I 0--------------0
0
0
Op
Code
2
8
7 8
MF2
303{l)
I
o0
1 1
7 8
2 3
3
5
MFl
I
I I
2 2 222
1 234
0
I
2
3
9
5
Yl
CNl TNl Sl
SFl
Nl
Yl
AR#
1 1 2 2 222
7 8 0 1 234
000
023
2
9
3
5
Y2
CN2 TN2 52
N2
Y2
AR#
CODING
SF2
The CMPN instruction is coded as follows:
1
8
16
CMPN
( MF1 ) , (MF2)
LOCSYM,CN,N,S,SF,AM
LOCSYM,CN,N,S,SF,AM
NDSC!!
NDSC!!
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
OPERA'!'I NG MODES:
Any
8-148
DZSI-OO
(
CMPN
CMPN
SUMMARY:
C(string 2) :: C(string 1)
EXPLANATION:
Starting at location YC1, the decimal number of data type TNl
and sign and decimal type Sl is algebraically compared with
the decimal number of data type TN2 and sign and decimal type
S2 that starts at location YC2. The comparison effectively
subtracts number 1 from number 2. Zeros (4 bits - 0000) are
used to pad the integral and fractional parts of the shorter
field. Both nUr:lbers remain unchanged.
ILLEGAL ADDRESS
MODI FI CAT! ONS:
DU, DL for MF1 and MF2
ILLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS :
Zero
a
a
1
a
a
Zero
Carry
Relationshi12
a
C(number 1)
C{number 1)
C(number 1)
1
0
NOTES:
Relationshi12
1
a
(
N~ative
1
1
C(number 1) > C(number 2)
C(number 1) = C(number 2)
C(number 1) < C(number 2)
>
=
<
C(number 2)
C(number 2)
C(number 2)
1. An IPR fault occurs if any character (least four bits)
other than 0000 - 1001 is detected where digits are
defined, or any character (least four bits) other than
1010 - 1111 is detected where the sign is defined by the
numeric descriptor.
2. An IPR fault occurs if the values for the number of
characters (Ni) of the data descriptors are not large
enough to hold the number of characters required for the
specified sign and/or exponent, plus at least one digit.
3. An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
8-149
DZSI-OO
CMPN
CMPN
r-'"
~-,)
EXAMPLES:
1
8
CMPN
NDSC4
NDSC4
TZE
FLDl
FLD2
TM!
TNC
USE
EDEe
EDEe
USE
CMPN
NDSC9
NDSC4
FLDl
FLD2
16
FLD1,O,8,1,-2
FLD2,O,8,O
EQUAL
LESS
ABS.LT
CONST.
8P-12345
8P-123.45
TZE
TN!
FLD1,2,2,3
FLD2,O,8,2,-3
EQUAL
LESS
TRA
GREATER
USE
EDEe
EDEe
USE
CONST.
4AOOl2
8Pl2000+
32
no modification
FLDl operand descriptor
FLD2 operand descriptor
FLD2 = FLDl
FLD2 < FLOl
IFLD21 < IFLD11
numbers compared
- 0 0 123 4 5
- 0 0 1 2 3 4 5
Result - FLD2 = FLDl
no modification
FLDl operand descriptor
FLD2 operand descriptor
FLD2 = FLDl
FLD2 < FLDl
FLD2 > FLDl
numbers compared
+ 0 0 1 2 0 0 0
+ 0 012 0 0 0
Result - FLD2 = FLDl
j
EXAMPLE WI TH ADDRESS MODI FI CATION:
1
8
16
32
EAX2
EAX6
EAX4
AWDX
CMPN
NDSC4
ARG
2
6
FLDl
0,4,4
(1,l"X2),(,,1)
O,O,X6,3,-3,4
FLD2.I
EQUAL
MORE
LESS
CONST.
8P123456
8Pl23456+
FLD2,O,8,2,-2
load character modifier into X2
load FLDl length into X6
load FLD1 address into X4
put FLDl address into AR4
with address modification
FLDl operand descriptor (FLDl,2,6,3,-3)
pointer to FLD2 operand descriptor
FLD2 = FLDl
FLD2 > FLDl
FLD2 < FLDl
numbers compared
+ 0 0 1 2 345 6
+ 0 1 2 3 456 0
TZE
TPL
TRA
USE
FLD1 EDEe
FLD2 EDEe
FLD2.I NDSC4
USE
Result - FLD2 > FLDl
-""
8-150
DZ51-00
(-
CMPNX
CMPNX
CMPNX
Compare Numeric Extended
343 (1)
FORMAT:
1 1
o1
0 0 0
0 1 2
H
1 1
7 8
MF2
01 00-------------00 1
0
0
Op
1 1
7 8
222
3
789
5
II I
343(1)
I
0
2
Code
2 2 222
1 234
0
MF1
I
2 3
3
9 0
5
Yl
CN1 TN1 SX1
N1
Yl
AR#
o
o
SF1
1 1
7 8
0
2
Y2
AR#
CODING FORMAT:
2 2 222
0 1 234
CN2 TN2 SX2
2 3
3
5
9 0
SF2
N2
Y2
1
8
16
CMPNX
NDsCn
NDSCn
LOCSYM, CN ,N ,SX , SF ,AM
LOCSYM, CN ,N ,SX, SF ,AM
(MFI ) , (MF2) ,CS
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
OPERATI NG MODES:
Any
SUMMARY:
C(string 1) :: C(string 2)
8-151
DZS1-OO
CMPNX
CMPNX
EXPLANATION:
Starting at location YC1, the decimal number of data type TNl
and sign and decimal type SKl is ~lgebraically compared with
the decimal number of data type TN2 and sign and decimal type
SK2 that starts at location YC2. The comparison effectively
subtracts number 1 from number 2. Zeros (4 bits - 0000) are
used to pad the integral and fractional parts of the shorter
field. Both numbers remain unchanged.
The character set is defined by CS (EBCDIC/ASClI).
ADDRESS
MODIFICATIONS:
I LLEGAL
I LLEGAL
REPEATS:
I NDI CATORS :
DU , DL for NFl or .MF2
RPT I RPD I RPL
~
Negative
0
1
0
1
0
0
Carry
0
1
NOTES:
RelationshiQ
C(number I} > C(number 2)
C(number 1) = C(number 2}
C(number 1) < C(number 2)
RelationshiQ
/
IC(number 1) I > IC(number 2) I
C(number 1) ~ C(number 2)
/'
1. An IPR fault occurs if any character (least four bits)
other than 0000 - 1001 is detected where digits are
defined, or if any character (least four bits) other than
1010 - 1111 is detected where the sign is defined by the
numeric descriptor.
2. An IPR fault occurs if the values for the number of
characters (Ni) of the data descriptors are not large
enough to hold the number of characters required for the
specified sign and/or exponent, plus at least one digit.
3. Refer to the specifications on MVNX for information on
coding of overpunched signs.
4. An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
8-152
"'\
DZ5l-00
I
(
CMPQ
CMPQ
CMPQ
Compare with Q-Register
116 (0)
FORMAT:
single-word instruction format (see Figure 8-1)
OPERATING MODES:
Any
SUMMARY:
C(Q) :: C(Y); C(Q) and C(Y) unchanged
ILLEGAL ADDRESS
MODI FI CATIONS:
None
I LLEGAL REPEATS:
None
INDICATORS:
Algebraic comparison (Signed Binary Operands)
Relationship
Zero Negat i ve Carry
o
o
1
o
o
o
o
o
o
1
1
1
1
1
C(Q)
C(Q)
C(Q)
C(Q)
C(Q)
o
> C(Y)
> C(Y)\
Sign
C(Q)o=0,C(Y)0=1
= C(Y) > C(Q)o=C(Y)o
< C(Y)/
< C(Y)
C(Q)O=1,C(Y)0=0
Logical comparison (Unsigned Positive Binary Operands)
Relationship
o
1
o
1
1
o
C(Q) > C(Y)
C(Q> = C(Y)
C(Q) < C(Y)
(
8-153
DZ5l-00
CMPXn
CMPXn
II
Compare with Index Register !!
FORMAT:
single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
10!!
(0)
For n = 0,1, ••• , or 7 as determined by op code
C(Xn) :: C(Y)0-17: C(Xn) and C(Y) unchanged
ES Mode
For n = O,l, ••• ,or 7 as determined by op code
C(GXn) :: C(Y): C(GXn) and C(Y) unchanged
ILLEGAL ADDRESS
MODI Fl CATl ONS :
CI, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL of CMPXO
I NDI CATeRS:
Algebraic (signed binary) comparison:
NS Mode
Zero Negative carry Relationship
o
o
1
o
o
o
o
o
o
C(Xn)
C(Xn)
C(Xn)
C(Xn)
C(Xn)
1
1
o
1
1
1
Sign
> C(Y)0-17 C(Xn)O=O,C(Y)O=l
> C(Y)O-17\
= C(Y)0-17 >C(Xn)O=C(Y)O
C(Y)O-171
< C(Y)O-17 C(Xn)O=l,C(Y)O=O
<
ES Mode
Zero N~ative carry Relationship
0
0
1
0
0
0
0
0
1
1
0
1
1
0
1
C(GXn)
C(GXn)
C(GXn)
C(GXn)
C(GXn)
8-154
C(Y)
C(Y)
= C(Y)
< C(Y)
< C(Y)
>
>
Sign
C(GXn)O=O,C(Y)O=l
\
>e(GXn)o=C(Y)O
I
C(GXn)O=l,C(Y)O=O
DZSI-00
(
CMPXn
CMPXn
Logical comparison (Unsigned Positive Binary Operands)
NS Mode
Zero
0
1
0
ES Mode
Zero
1
1
0
Relationship
C(Xn) > C{Y)O-17
C(Xn) = C{Y)O-17
C(Xn) < C(Y)O-17
carry
Relationship
1
1
1
0
0
C(GXn) > C(y)
C(GXn) = C(Y)
C(GXn) < C(Y)
0
NOTES:
carry
l. When DL modification is specified in the NS Mode I it is
executed with all zeros for data.
2.
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
(
(
8-155
DZ5l-00
CMRR
CMRR
Compare Register to Register
CMRR
534 (1)
FORMAT:
a
a
1 1
7 8
Not Used
CODING FORMAT:
1
I
OP CODE
222
789
3 3
1 2
II I
I
MBZ
3
5
R2
I
16
8
R1, ,R2
CMRR
OPERATING MODES:
Executes in
SUMMARY:
Rl, R2, = 0, 1, 2, 3, 4, 5, 6, 7, A, Q
ES
mode only
C(R1) : : C(R2)
C(R1), C(R2) unchanged
EXPLANATION:
C(R1) is compared with C(R2) and the indicators are set as
indicated below.
ILLEGAL ADDRESS
MODIFICATIONS
None.
I LLEGAL REPEATS:
RPT, RPD, RPL
The address modification is not executed.
ILLEGAL EXECUTES: Execution in NS mode
INDICATORS:
Algebraic (signed fixed-point) Comparison
Zero
N~ative
0
0
0
0
1
a
0
0
1
i
carry
a
1
1
0
1
8-156
RelationshiQ
C(Rl)
C(Rl)
C(Rl)
C(Rl)
C(Rl)
Sign
> C(R2)
> C(R2)
C(Rl)O=O, C(R2)O=1
< C(R2)
< C(R2)
I
= C(R2)
\
>
C(Rl)0=C(R2)o
C(Rl)O=l, C(R2)O=O
DZ51-00
(
CMRR
CMRR
Logic (unsigned fixed-point) Comparison
o
1
o
NOTES:
Carry
Relationship
o
C(R1) < C(R2)
C(Rl) = C(R2)
C(Rl) > C(R2)
1
1
1. An IPR fault occurs if illegal repeats are executed or if the
instruction is executed in NS mode.
2. Refer to Register to Register Instructions in Section 7 for a
description of the fields in the instruction word.
8-157
DZ5l-00
CNAA
CNAA
CNAA
Comparative NOT AND with A-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NGMODES:
Any
SUMMARY:
For i
C(Q)
ILLEGAL ADDRESS
MODIFICATIONS:
None
I LLEGAL REPEATS:
None
I NDI CATORS:
Zero
=0
~nd
to 35, C(Z)i
= C(A)i
I
215 {OJ
AND C(Y)i
C(Y) unchanged
-
Negative -
= 0, then ON; otherwise, OFF
CCZ)O = 1, then ON; otherwise, OFF
If cCZ)
If
8-158
DZ51-00
(
CNAAQ
CNAAQ
CNAAQ
Comparative NOT AND with AQ-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
For i
=0
to 71, C(Z)i
= C(AQ)i
217 (0)
AND C(Y-pair)i
C(AQ) and C(Y-pair) unchanged
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC,
ILLEGAL REPEATS:
None
I NDI CATORS:
Zero
-
Negative NOTE:
(
SCR
= 0, then ON; otherwise, OFF
If C(Z)
If C(Z)O
= 1,
then ON; otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modification is used.
8-159
DZ51-00
CNAQ
CNAQ
CNAQ
Comparative NOT AND with Q-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY
For i
I LLEGAL ADDRESS
MODIFICATIONS:
None
I LLEGAL REPEATS:
None
I NDI CATORS :
Zero
=0
-
to 35, C(Z)i
= C(Q)i
216 (0)
AND C(Y)i
= 0, then ONi otherwise, OFF
C(Z)O = 1, thenONi otherwise, OFF
If C(Z)
Negative - I f
8-160
DZ51-00
(
CNAXn
CNAXn
Comparati ve NOT AND with I ndex Register
n
FORMAT:
single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
For n
20n (0)
= O,l, ••• ,or 7 as determined by op code
= 0 to 17, C(Z)i = C(Xn)i AND C(Y)i
For i
C(Xn) and C(y) unchanged
ES Mode
For n
= O,l, ••• ,or
7 as determined by op code
For i = 0 to 35, C(Z)i = C(GXn)i AND C(Y)i
C(GXn) and C(y) unchanged
(
ILLEGAL ADDRESS
MODIFICATIONS:
CI,
ILLEGAL REPEATS:
RPT, RPD, RPL of CNAXO
INDICATORS:
Zero
SC, SO
-
Negative NOTES:
If C(Z)
If C(Z)o
= 0,
= 1,
then ON: otherwise, OFF
then ON: otherwise, OFF
1. DL modification is flagged illegal but executes with all
zeros for data.
2.
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
(
8-161
DZ51-00
CSL
CSL
060 (l)
Combine Bit Strings Left
CSL
FORMAT:
o0
0 0
0 0 I
I
I I
Op
Code
2 2
060(1)
MF2
o 00
3
2
Y1
B1
0-------
Y1
2 3
Y2
CODING FORMAT:
C2
Y2
RI
0
I I 2 2 222
7 8 0 I 234
000
AR#
3
5
NI
CI
o
NFl
I 1 2 2 222
7 8 0 I 234
023
AR#
3
3
5
3
2
N2
B2
0--------0
R2
The CSL instruction is coded as follows:
1
8
16
CSL
BDSC
BDSC
(MF1),(MF2),BOLR,F,T
LOCSYM,N,C,B,AM
LOCSYM,N,C,B,AM
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
8-162
DZS1-00
CSL
CSL
OPERATING MODES:
Any
SUMMARY:
C(string 1) : (BOLR) : C(string 2) --> C(string 2)
EXPLANATION:
The string of bits starting at location YCBl is evaluated,
bit by bit, with the string starting at location YCB2 and the
appropriate bit from the BOLR control field is placed into
each corresponding bit of the string starting at location
YCB2. If Ll is greater than L2, the least significant L1-L2
bits of string 1 are truncated and the Truncation indicator
is set. If L1 is less than L2, the fill bit (F) is used as
the L2-L1 least significant bits of string 1. The contents
of string 1 remain unchanged.
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL for MFl and MF2
ILLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS :
Zero
If all the resultant bits generated are zero,
then ON if L2=0 and L1 ~ 0; otherwise, OFF
Truncation -
If L1 is > L2, then ON; otherwise, OFF
If Ll>O and L2=O, then ON. If Ll=L2=O, then
OFF.
NOTES:
1. An Illegal Procedure fault occurs if illegal address
modification is used or if an illegal repeat is used.
2. An IPR fault does not occur even when Ll = 0 or L2 = O.
In this case, the zero and truncation indicators are
affected.
8-163
DZS1-00
CSL
eSL
EXAMPLES:
8
FLD1
FLD2
32
REM
BITS 0-17 OF F102 FORCED ON
CSL
,,07,,1
"ORING" with truncation enable option
BDSC F101,24,1,3 F101 operand descriptor
BDSC F102,18,0,0 F102 operand descriptor
USE
CONST
memory contents in octal
VFD
12/0,18/-1,6/0
00007 7 7 7 7 7 0 0
10A
0,2
0 0 0 0 0 0 2 3 5 01 2
USE
7 7 7 7 7 7 2 3 5 0 1 2 (Resu1 t )
REM
CSL
BDSC
BDSC
USE
FLD2
16
DEC
USE
BITS 18-35 OF
, ,06,1.
,0
FLD2,18,2,0
CONST.
o
FLD2 INVERTED
exclusive OR with fill bit 1 option
F101 operand descriptor
F102 operand descriptor
memory contents in octal
000000000000
o 0 0 0 0 0 7 7 7 7 7 7 (Result)
EXAMPLE -'."'1 TH ADDRESS MODI FI CATION:
1
FLD2
8
16
32
EAX6
12
load char and bit address modifier into X6
EAX7
54
load FLD2 length into X7
EAX4
F102
load F102 address into X4
AWDX
0,4,4
put FLD2 address into AR4
CSL
(,,1),00,(1,1,,6),00 clear operation with address
2,4
modification ARG
pointer to FLD1 indirect operand descriptor
BDse
0,X7",4
FLD2 operand descriptor (FLD2,54,1,3)
USE
CONST.
memory contents in octal
VFD
36/-1,36/-1 777777777777 777777777777
BDSe,O
F101 operand descriptor (control field zeros)
USE
777700000000 000000000077 (Result)
8-164
DZ51-00
(
..
CSR
CSR
Combine Bit Strings Right
CSR
061 (1)
FORMAT:
o0
o1
o0
4 5
1 1
7 8
001 1
890 1
Heeee ImLR 1+ 1
MF2
Op
2
8
060(1 )
1
0 o0
0 2 3
Code
3
2
3
5
B1
Y1
0----------0
1 1 2 2 222
7 8 0 1 234
000
023
R1
3
2
Y2
3
5
N2
C2
CODING FORMAT:
1
NI
CI
AR#
MF1
1 1 2 2 222
7 8 o I 234
YI
AR#
H
3
5
Y2
B2
0-------0
R2
The CSR instruction is coded as follows:
1
8
16
CSR
BDSC
BDSC
(MF1),(MF2),BOLR,F,T
LOCSYM,N,C,B,AM
LOCSYM,N,C,B,AM
(Refer to Section 7 under Multiword Instructions for description
of Multiword Modification Field.)
OPERAT! NG MODES:
Any
SUMMARY:
C(string 1)
(BOLR)
C(string 2) --> C(string 2)
(
8-165
DZ51-00
CSR
CSR
EXPLANATION:
This instruction operates the same as CSL except that the
starting locations are YCBl + (Ll-l) and YCB2 + (L2-l) and
the evaluation is from right to left (least to most
significant bits). Any truncation or fill is of most
significant bits.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL for NFl and MF2
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
same as for CSL
NOTES:
1. An Illegal Procedure fault occurs if illegal address
modification is used or if an illegal repeat is used.
2. An IPR fault does not occur even when Ll = 0 or L2 = O.
In this case, the zero and trunctaion indicators are
affected.
EXAMPLES:
1
8
16
32
CSR
, ,14, ,1
FLDl,18,2,0
FLI>2,12,O,O
CONST.
444444
0
invert with truncation fault enable option
FLDl operand descriptor
FLI>2 operand descriptor
memory contents in octal
000000444444
333300000000 (Result)
truncation
BDse
BDse
USE
FLDl
FLD2
OCT
DEe
USE
CSR
FLD2
BDse
BDse
USE
BSS
USE
,,17
force ones operation
FL01 operand descriptor
,0
FLI>2,36,O,O
CONST.
FLD2 operand descriptor
memory contents in octal
1
77777 7 7 7 7 777
(Result)
none
8-166
DZ5l-00
'-
"_./
CWL
CWL
CWL
Compare with Limits
111 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(Y) :: closed (algebraic) interval [C(A), C(Q)] and
(algebraic comparison) C(Y) :: C(Q)
C(y), C(A), C(Q) are unchanged
EXPLANATION:
(
This instruction tests the algebraic value of C(Y) to
determine if it is within the range of algebraic values
bounded by C(A) and C(Q). The indicators are then set to
reflect the result. This instruction is not recommended for
logical (unsigned) comparisons.
I LLEGAL ADDRESS
MODIFICATIONS:
None
I LLEGAL REPEATS:
None
I NDI CATORS:
Zero
N~ative
-
If C(Y) is contained in the closed interval
[C(A), C(Q)] i.e., either C(A) ~ C(Y) ~ C(Q) or
C(A) ~ C(Y) ~ C(Q), then ON; otherwise, OFF
carry
0
0
0
1
1
1
0
1
Relationshil2
Sign
C(Q) > C(Y) C(Q)o
C C(EAQ):
C{Y-pair) unchanged
I LLEGAL ADDRESS
MODIFICATIONS:
OU, DL,
ILLEGAL REPEATS:
None
I NDI CATORS:
Zero
a,
SC, SCR
= 0, then ON: otherwise, OFF
C(AQ)O = 1, then ON; otherwise, OFF
- If C{AQ)
Negative - If
Exponent
Overflow - If exponent is > +127, then ON
Exponent
Underflow - If exponent of floating point result < - 128,
then ON
carry
NOTES:
- If a carry out of bit 0 ofC(AQ) is generated,
then ON; otherwise, OFF
1. The definition of normalization is located under the
description of the FNO instruction.
2. When indicator bit 32 = 1 and the hex permission flag = 1,
the floating-point alignment and normalization are
hexadecimal. Otherwise, the floating-point alignment and
normalization are binary. The hex permission flag is CPU
mode register, bit 33.
3. An Illegal Procedure fault occurs if illegal address
modification is used.
8-168
DZS1.... OO
DFCMG
DFCMG
DFCMG
Double-Precision Floating COmpare Magnitude
FORMAT:
single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
IC(E,AQO-63>I :: IC(Y-pair)l; magnitude comparison
427 (0)
C(EAQ ), C(Y-pa ir) unchanged
EXPLANATION:
This comparison is executed as follows:
1. Compare C(E) :: C(Y)0-7, select
exponent, and shift its mantissa
the difference of the exponents.
equals or exceeds 72, the number
is defined as zero.
the number with the lower
right as many places as
If the number of shifts
with the lower exponent
2. Compare the absolute values of the mantissas and set the
indicators accordingly.
The DFCMG instruction is identical to the DFCMP instruction
except that the magnitudes of the mantissas are compared
instead of the algebraic values.
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
None
INDICATORS:
Zero
NOTES:
N~ative
0
1
0
0
0
1
Relationshi:Q
C(E,AQO-63)
C(E,AQO-63)
C(E,AQO-63)
> C(Y-pair)
=
<
C(Y-pair)
C(Y-pair)
1. When indicator bit 32 = 1 and hex permission flag = 1, the
floating-point alignment is hexadecimal. Otherwise, the
floating-point alignment is binary. The hex permission
flag is CPU mode register, bit 33.
2. An Illegal Procedure fault occurs if illegal address
modification is used.
(8-169
DZS1-00
DFCMP
DFCMP
DFCMP
Double-Precision Floating COmpare
517 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(E,AQO-63) :: C(Y-pair); C(EAQ), C(Y-pair) unchanged
EXPLANATION:
This comparison is executed as follows:
a. Compare C(E) :: C(Y)O-7, select
exponent, and shift its mantissa
the difference of the exponents.
equals or exceeds 72, the number
is defined as zero.
the number with the lower
right as many places as
If the number of shifts
with the lower exponent
b. Compare the mantissas and set the indicators accordingly.
The DFCMP instruction is identical to the FCMP instruction
except for the precision of the mantissas actually compared.
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
None
INDICATORS:
Zero
NOTES:
Negative
"
Relationshi:Q
0
0
IC(E,AQO-63) I > IC(Y-pair) I
1
0
IC(E,AQO-63) I
0
1
IC(E,AQO-63) I < IC(Y-pair) I
1. When indicator bit
the floating-point
the floating-point
permission flag is
= IC(Y-pair)I
32 = 1 and the hex permission flag = 1,
alignment is hexadecimal. Otherwise,
alignment is binary. The hex
Mode register, bit 33.
2. An Illegal Procedure fault occurs if illegal address
modification is used.
8-170
DZ51-00
(
DFDI
DFDl
DFDI
Double-Precision Floating Divide Inverted
527 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(Y-pair) / C(EAQ) -> C(EAQ): C(Y-pair) unchanged
EXPLANATION:
If AQ64-7l is not = 0 and AO = 0, a 1 is added to AQ63. zero is
moved to AQ64-7l, unconditionally. AQO-63 is then used as the
divisor mantissa. The 8-bit dividend exponent and 72-bit
mantissa are placed in working registers. The dividend mantissa
is shifted right, and the dividend exponent is increased
accordingly until: IDividend mantissa I < IC(AQ)0-631. When
such a shift occurs, significant bits from the dividend may be
lost.
C(AQ)0-63 is used as the divisor mantissa. 64 bits of quotient
mantissa are placed in AQO-63. Zeros are placed in AQ64-7l.
(
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, Cl, SC, SCR
ILLEGAL REPEATS:
None
When Division Occurs
When No Division Occurs
Zero
If C(A) = 0, then ON:
otherwise, OFF
If divisor mantissa =0,
then ON: otherwise, OFF
Negative
If C{AQ)O = 1, then
ONi otherwise, OFF
If dividend < 0, then
ON: otherwise, OFF
I NDI CATORS :
Exponent
Overflow
Exponent
Underflow
If quotient exponent
is > +127, then ON
If exponent of floating
point result < - 128, then ON
(
8-171
DZ5l-00
DroI
DroI
NOTES:
1. When indicator bit 32 = 1 and the hex permission flag = 1,
the floating-point alignment and normalization are
hexadecimal. Otherwise, the floating-point alignment and
normalization are binary. The hex permission flag is Hode
register bit 33.
2. If the divisor mantissa C(AQ) is zero, the division does
not take place. Instead, a Divide Check fault occurs and
all registers remain unchanged. The dividend and divisor
are not normalized by the hardware prior to division.
3. An Illegal Procedure fault occurs if illegal address
modification is used.
/
8-172
DZSl-OO
DFDV
DFDV
DFDV
Double-Precision Floating Divide
567 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(EAQ) I C(Y-pair) -> C(EAQ); C(Y-pair) unchanged
EXPLANATION:
C(AQ)0-7l are used by this instruction. If the divisor
mantissa C(Y-pair)8-7l is zero, then the division does not
take place. Instead, a Divide Check fault occurs. The
divisor C(Y) remains unchanged, C(AQ) contains the dividend
magnitude in absolute, and the Negative indicator reflects
the dividend sign. Dividend and divisor are not normalized
by the hardware prior to division.
The dividend mantissa C(AQ) is shifted right and the dividend
exponent is increased accordingly until
IC(AQ)o-63I < IC(y-pair)8- 7t' with zero filli.
C(E) - C{Y-pair)O-7 --> C E)
When such a shift occurs, significant bits from the dividend
may be lost. 64 bits of the quotient mantissa are placed in
AQO-63. Zeros are placed in AQ64-7l.
When the divisor mantissa is a, division is not executed and
a Divide Check fault occurs. The absolute value of the
dividend is loaded into AQ, and the Negative indicator is set
in accordance with the sign of the dividend.
Refer to the FDV instruction for details of the method of
shifting the dividend.
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
None
(
8-173
DZ51-00
DFDV
DFDV
When Division Occurs
When No Division Occurs
Zero
If C(A) = 0, then ON;
otherwise, OFF
If divisor mantissa =0,
then ON: otherwise, OFF
Negative
If C(AQ)O
I NDI CATORS :
= 1,
then
If dividend < 0,
then ON: otherwise, OFF
ON: otherwise, OFF
Exponent
Overflow
Exponent
Underflow
NOTES:
If quotient exponent
is > +127, then ON
If exponent of floating
point result < - 128, then ON
1. When indicator bit 32=1 and the hex permission flag = 1,
the floating-point alignment and normalization are
hexadecimal. Otherwise, the floating-point alignment and
normalization are binary. The hex permission flag is Mode
register bit 33.
2.
An Illegal Procedure fault occurs if illegal address
modification is used.
8-174
DZSI-00
(
DFLD
DFLD
DFLD
Double-Precision Floating Load
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(Y-pair), 00 ••• 0 --> C(EAQ); C(Y-pair) unchanged
433 C(E)
C(Y-pair)S-71 --> C(AQ)0-63
00 ••• 0 --> C(AQ)64-71
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
None
I NDI CATORS:
zero
-
Negative NOTE:
= 0,
If C(AQ)
If C(AQ)O
= 1,
then ON; otherwise, OFF
then ON; otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modification is used.
8-175
DZ5l-00
DFLP
DFLP
DFLP
Double-Precision F10C1ting Load Positive
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
IC(Y-pair)l, normalized --> Z
532 (0)
ZO-7 --> C(E)
ZS-71 --> C(AQ)0-63
00 ••• 0 --> C(AQ)64-71
EKPLANATION:
The memory operand C(Y) is processed as double-precision
floating-point data. The absolute value of this data is
normalized and its exponent, mantissa (bits 8-71), and 0 are
loaded into C(E), C(AQ)O-63, and C(AQ)64-7l, respectively.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
None
I NDI CATORS:
Zero
-
If C(AQ)
Negative
-
If C(AQ)O = 1, then ON; otherwise, OFF
Exponent
Overflow
-
I f exponent > +127, then ON.
Exponent
Underflow
-
If exponent of floating point result < - 128,
then ON
NOTE:
= 0,
then ON; otherwise, OFF
Illegal Procedure fault occurs if illegal address
modification is used.
An
8-176
DZ51-00
DFMP
DFMP
DFMP
Double-Precision Floating Multiply
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
[C(EAQ) * C(Y-pair}]
C(Y-pair) unchanged
EXPLANATION:
This multiplication is executed as follows:
463 (0)
normalized --> C(EAQ}i
C(E) + C(Y-pair)0-7 --> C(E}.
C(AQ) * C(Y-pair}S-71 results in a 134-bit product plus
sign. This sign plus the leading 71 bits are loaded into the
AQ. C(EAQ} normalized --> C(EAQ).
The definition of normalization is located under the
description of the FNO instruction.
(
ILLEGAL ADDRESS
MODIFICATIONS:
I
LLEGAL REPEATS:
I NDI CATORS:
NOTES:
DU, DL, CI, SC, SCR
None
= 0, then ON; otherwise, OFF
C(AQ)O = 1, then ON; otherwise, OFF
Zero
-
If C(AQ)
Negative
-
If
Exponent
Overflow
-
If exponent> +127, then ON
Exponent
Underflow
-
If exponent of floating point result < - 128,
then ON
1. When indicator bit 32 = 1 and the hex permission flag = 1,
floating-point alignment and normalization are
hexadecimal. Otherwise, the floating-point alignment and
normalization are binary. The hex permission flag is Mode
register bit 33.
2. An Illegal Procedure fault occurs if illegal address
modification is used.
(
8-177
DZS1-OO
DFRD
DFRD
DFRD
Double-Precision Floating Round
473 (0)
FORMAT:
single-word instruction format (see Figure 8-1)
OPERA'l'I KG MODES:
Any
SUMMARY:
C(EAQ) rounded to 64 bits and normalized --> C(EAQ)
EXPLANATION:
A true round is performed on C(EAQ) to reduce the mantissa of the
floating-point number to 64 bits. The exponent is set to -128 if
the rounded mantissa = O.
This instruction is identical with FRO except that the rounding
constant is added to bits 65-71 and the results are rounded to 64
bits of precision. Bits 64-71 of C(AQ) are replaced by zeros.
The definition of normalization is located under the description
of the FNO instruction.
I LLEGAL ADDRESS
MODI FI CAT! ONS :
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
None
INDICATORS
Zero
-
If C(AQ)
Negative
-
If C(AQ)O
Exponent
Overflow
-
If exponent> +127, then ON
EXponent
Underflow
-
If exponent of floating point result < - 128, then
ON
NOTES:
= 0,
= 1,
then ON: otherwise, OFF
then ON; otherwise, OFF
1. When indicator bit 32 = 1 and the hex permission flag = 1, the
floating-point alignment and normalization are hexadecimal.
Otherwise, the floating-point alignment and normalization are
binary. The hex permission flag is mode register bit 33.
2.
An Illegal Procedure fault occurs if illegal address
modification is used.
8-178
DZ5l-00
(
DFSB
DFSB
DFSB
Double-Precision Floating Subtract
577 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
[C(EAQ) - C(Y-pair)]
C(Y-pair) unchanged
EXPLANATION:
The definition of normalization is located under the
description of the FNO instruction.
LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
None
INDICATORS
Zero
-
If C(AQ)
Negative
-
If
Exponent
Overflow
-
If exponent> +127, then ON
Exponent
Underflow
-
If exponent of floating point result < - 128,
then ON
carry
-
If a carry out of bit 0 of C(AQ) is generated,
then ON; otherwise, OFF
normalized -> C(EAQ):
I
NOTES:
= 0, then ON; otherwise, OFF
C(AQ)O = 1, then ON; otherwise, OFF
1. When indicator bit 32 = 1 and the hex permission flag = 1,
the floating-point alignment and normalization are
hexadecimal. Otherwise, the floating-point alignment and
normalization are binary. The hex permission flag is mode
register bit 33.
2. An Illegal Procedure fault occurs if illegal address
modification is used.
(
8-179
DZS1-OO
DFSBI
DFSBI
DFSBI
Double-Precision Floating Subtract Inverted
467 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Any
SUMMARY:
[C(Y-pair) - C(EAQ)]
C(Y-pair) unchanged
EXPLAHATION:
The two's complement of the subtrahend is first taken and the
smaller value is then right shifted to equalize it. The
shifted portion is truncated and the addition is executed.
After addition, the sum is normalized and the 72 bits of the
mantissa are loaded into AQ.
normalized -> C(EAQ):
The order of execution of the operation conforms to that of
the DFSB instruction. Normalization is defined under FNO.
I LLEGAL ADDRESS
·MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
None
I NDI CATeRS
Zero
-
If C(AQ)
Negative
-
If C(AQ)O
Exponent
Overflow
-
I f exponent is > +127, then ON
Exponent
Underflow
-
If exponent of floating point result < - 128,
then ON
carry
-
If a carry out of bit 0 of C(AQ) is generated,
then ON; otherwise, OFF
NOTE:
= 0,
= 1,
then ON; otherwise, OFF
then ON; otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modification is used.
8-180
DZSI-OO
DFST
DFST
DFST
Double-Precision Floating Store
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(E) --> C(Y-pair)0-7
457 (0)
C(AQ)0-63 --> C(Y-pair)8-71
C(EAQ) unchanged
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, a, SC, SCR
I LLEGAL REPEATS:
RPL
I NDI CATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
(
8-181
DZ51-00
DFSTR
DFSTR
DFSTR
Double-Precision Floating Store Rounded
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(EAQ)0-7l rounded, normalized --> C(Y-pair):
472 (0)
C(EAQ) unchanged
EXPLANATION:
This instruction performs a true round on C(EAQ) to 64 bits
of precision in C(AQ). The result is normalized and stored
in the Y-pair •. C(EAQ) is unchanged. The exponent is stored
as -128 if the rounded mantissa = o. (See the FRO
instruction for the definition of true round.)
Except for precision, this instruction is identical with the
FSTR instruction.
The definition of normalization is located under the
description of the FNO instruction.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPL
I NDI CATORS:
Zero
-
If C(Y-pair) = floating-point zero, then ON:
otherwise, OFF
Negative
-
If C(Y-pair)a
Exponent
Overflow
-
If exponent> +127, then ON
Exponent
Underflow
-
If exponent of floating point result
then ON
8-182
= 1,
then ON: otherwise, OFF
< -
128,
DZS1-OO
(
DFSTR
DFSTR
NOTES:
1. When indicator bit 32 = 1 and the hex permission flag = 1,
the floating-point alignment and normalization are
hexadecimal. Otherwise, the floating-point alignment and
normalization are binary. The hex permission flag is Mode
register bit 33.
2.
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
(
8-183
DZ51-00
DIS
DIS
DIS
Delay Until Interrupt Signal
616 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Executes in NS mode only with Privileged Master mode
SUMMARY:
No operation takes place other if enabled, PATROL is
invoked. The processor does not continue with the next
instruction, but waits for a program interrupt signal. When
an interrupt occurs, PATROL is stopped.
ILLEGAL ADDRESS
MODIFICATIONS:
None. Modification is performed, including modification of
any indirect words specified. However, the effective address
has no effect on the operation, including the final value of
the instruction counter.
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1. The inhibit bit in this instruction only affects the
recognition of a Timer Runout (TRO) fault as follows:
o Inhibit ON delays the recognition of a TRO. until the
processor enters Slave mode.
o Inhibit OFF allows the TRO to interrupt the DIS state
For all other faults and interrupts, the inhibit bit is
ignored.
2. A Command fault occurs if execution is attempted in Slave
or Master mode.
3. An IPR fault occurs if this instruction is used in the ES
mode.
8-184
DZ5l-00
(
DIV
DIV
DIV
Divide Integer
506 (0)
FORMAT:
Single-word instruction format C(Q), right-adjusted
integral remainder --> C(A), right-adjusted
C(y) unchanged
EXPLANATION:
C(Q) and C(Y) are considered as 36-bit integers (including
sign). The integer quotient of C remains
unchanged, C contains the jividend magnitude, and the
Negative indicator reflects the dividend sign, and C(A) is set
to zero.
T
8-186
DZ51-00
/
(
DRL
DRL
DRL
Dera il Fault
002 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES
Any
EXPLANATION:
DRL generates a Derail fault, which causes the processor to
switch to Privileged Master mode and execute an Inward CLIMB
instruction using the entry descriptor obtained from the word
pair in memory locations 32 and 33 octal.
If the safestore bypass flag in the option register = 1, a
safestore frame is generated. The size of this safestore
frame is determined by the type of the entry descriptor. The
occurrence of the DRL fault is indicated in the safestore
frame by a code of 00110 in bits 12-16 of word 5.
The wired-in CLIMB instruction functions as though the second
word of the CLIMB instruction had the following
characteristics:
(
E
=0
C18
C19
C22-23
S, D
No parameters
Do not load XO
No effect. Turn Master Mode indicator ON.
Inward CLI MB
No effect
=a
The entry descriptor specifies a descriptor to be ob~ined
from the linkage segment for loading into the instruction
segment register (ISR). The entry descriptor also specifies
the value to be loaded into the instruction counter (ID).
The processor is placed in Privileged Master mode for the
execution of the wired-in CLIMB. Upon completion of the
CLIMB, the processor remains in Privileged Master mode if
flag bit 26 of the new ISR = 1 (privileged): otherwise, the
processor changes to Master Mode.
ILLEGAL ADDRESS
MODIFICATIONS:
Not executed
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
Master Mode - ON
(
8-187
DZ5l-00
DTB
DTB
Decima1-to-Binary Convert
DTB
305
(1)
FORMAT:
1 1
o1
0
0
I
0
-----0
I
7 8
MF2
0 o0
0 2 3
2 2 222
7 8 0 1 234
3
5
II
NFl
I
2 3
9 0
Yl
Nl
R1
00
1 1 2 2
233
7 8
902
Y2
0 1
CN2 0--------------0
Y2
I
3
5
3
2
CNl TNl Sl 0 - - - - - 0
023
COOl NG FORMAT:
305(1)
1 1
000
AR#
2 2 2
8 9
7
I
Y1
AR#
Op. Code
1 1
3
5
N2
00
R2
The DTB instruction is coded as follows:
1
8
16
DTB
NDsCn
NDSeS
(NFl) , (MF2)
LOCSYM,CN,N,S"AM
LOCSYM,CN,N",AM
(Refer to Section 7 under Mu1tiword Instructions for description
of Mu1tiword Modification Field.)
OPERATI NG MODES:
Any
8-188
DZ5l-00
,/
(-
DTB
DTB
converted
SUMMARY:
C(string 1)
-------> C(string 2)
The string of decimal characters of data type TNl, sign and
decimal type S1 (S1 = 00 is illegal), and scale factor 0 that
starts at YC1 is converted into a two's complement binary
integer and stored, right-justified, as a character string of
length L2, starting at location YC2. If the string generated
is longer than 12, the high-order excess is truncated and the
overflow indicator is set. CN2 is given in the 9-bit
character format with legal codes of 000, 010, 100, and 110.
If string 1 contains more than 32, when the generated binary
string is longer than L2, the upper bits are truncated and
the overflow indicator is set.
CN2 specifies the value for the 9-bit character format, the
correct codes being 000, 010, 100, or 110. L2 specifies the
length of .the stored binary value in 9-bit units, and must be
equal to or less than 8. The length of the stored binary
value is 9, 18, 27, 36, 45, 54, 63, or 72 bits.
Provided that string 1 and string 2 are not overlapped, the
contents of string 1 remain unchanged.
(
I LLEGAL ADDRESS
MODI FI CATIONS:
I
LLEGAL REPEATS:
I NDI CATORS :
DU, DL for MF1 and MF2
RPT, RPD, RPL
Zero
-
If all the resultant bits generated are zero,
then ON; otherwise, OFF
Negative -
If the resultant sign is negative, then ON:
otherwise, OFF
Overflow -
If L2 is less than the number of 9-bit segments
generated, then ON; otherwise, unchanged
8-189
DZ51-00
DTB
DTB
NOTES:
1. An Illegal Procedure fault occurs for the following
reasons:
o If
DU
or DL modifications are used for NFl or
MF2
o If L2 is less than 1 or > 8
o If CN2 does not contain a legal code
o If Sl = 00
o If illegal digit or sign is detected in string 1
o If Nl is not large enough to specify the number of
characters required for the specified sign and/or
exponent, plus at least one digit
2. An IPR fault occurs if illegal address modification is
specified or if an illegal repeat is used.
3. If string 1 has the value -2**(9*L2-l), the result is zero
and the overflow indicator is turned ON.
4. If string 1 contains more than 22 significant digits, an
incorrect result is produced and the overflow indicator is
turned ON.
5. If the binary result is longer than L2 9-bit characters,
the most significant nontruncated bit is forced to agree
with the result sign.
8-190
DZ5l,:",00
\
~. .-/
f
DTB
DTB
EXAMPLES:
1
FLD1
FLD2
8
DTB
NDSC4
NDSC9
USE
EDEC
BSS
16
32
FLD1,3,5,2
FLD2,O,4
CONST.
8P12341
decimal operand descriptor
binary operand descriptor
memory contents in octal
o0 0 0 0 1 0 4 3 1 1 5
7 7 7 7 7 7 7 7 545 6 (Result)
any indicators set? negative
USE
FLD1
FLD2
(
FDL1
FLD2
FLD1
FLD2
DTB
NDSC9
NDSC9
USE
EDEC
BSS
USE
FLD1,O,22,3
decimal operand descriptor
FLD2,O,8
binary operand descriptor
memory contents
CONST.
22A2361183241434822606847 (maximum decimal value)
377777777777777777777777 (Result)
2
any indicators set? none
DTB
NDSC4
NDSC9
USE
EDEC
DEC
USE
FLD1,3,3,3
FLD2,2,2
CONST.
8P51200
-1
decimal operand descriptor
binary operand descriptor
memory contents in octal
000 0 0 502 200 0
7 7 7 777 0 0 1 000
any indicators set? none
DTB
NDSC9
NDSC9
USE
EDEC
DEC
USE
FLD1,O,4,3
FLD2,3,1
CONST.
4AlO23
0
decimal operand descriptor
binary operand descriptor
memory contents in octal
061 060 062 063
o0 0 0 0 0 0 0 0 7 7 7
any indicators set? overflow
(
8-191
DZ51-00
DTB
DTB
EXAMPLE WITH ADDRESS MODIFICATION:
1
8
16
32
EAXO
°2
FLD2
load FLD character modifier into xo
load FLD2 length into X4
load FLD2 address modifier into X7
put FLD2 address modifier into AR4
with modification
pointer to FLDl indirect descriptor
binary FLD2 descriptor (FLD2,0,2)
zeros was the result
negative result
high-order bit truncated
memory contents in octal
3 250 220
0
7 7 7 0 0 0 1 1 1 1 1 1
decimal operand descriptor
any indicators set? negative
EAX2
EAX7
AWDX
DTB
ARG
NDSC9
TZE
TMI
TOV
FLD1
FLD2
USE
EDEC
OCT
NDSC4
USE
0,7,4
(,,1),(1,1,,0)
1,,4
0"X2",4
*+3
*+2
*+1
CONST.
4PL-512
111111
FLD1,0,4,1
°°° °
('--\
......
8-192
DZ51-00
,/
(
DUFA
DUFA
DUFA
Double-Precision Unnormalized Floating Add
437 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
[C(EAQ) + C(Y-pair)]
C(Y-pair) unchanged
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
None
I NDI CATORS :
Zero
-
If C(AQ)
Negative
-
If
Exponent
Overflow
-
If exponent is > +127, then ON
Exponent
Underflow
-
If exponent of floating point result < - 128,
then ON
carry
-
If a carry out of bit 0 of C(AQ) is generated,
then ON; otherwise, OFF
(
NOTES:
not normalized --> C(EAQ)
= 0, then ON; otherwise, OFF
C(AQ)O = 1, then ON; otherwise, OFF
1. When indicator bit
the floating-point
the floating-point
permission flag is
32 = 1 and the hex permission flag = 1,
alignment is hexadecimal. Otherwise,
alignment is binary. The hex
Mode register bit 33.
2. An Illegal Procedure fault occurs if illegal address
modification is used.
8-193
DZ51-00
DUFM
DUFM
DUFM
Double-Precision Unnormalized Floating Multiply
423 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
[C(EAQ) * C(Y-pair)]
C(Y-pair) unchanged
EXPLANATI ON:
This multiplication is executed like the DFMP instruction, except
that the final normalization is performed only if both factor
mantissas are • -1.00 ••• 0.
not normalized
-->
C(EAQ)
Except for the precision of the mantissa of the operand from main
memory, the DUFM instruction is identical to the UFN instruction.
I LLBGAL ADDRESS
MODIFICATIONS:
DU, DL, a,
I LLBGAL REPEATS:
None
I NDI CATORS:
Zero
-
SC, SCR
= 0,
If C(AQ)
Negative -
If C(AQ)O
Exponent
OVerflow -
1f
= 1,
then ON; otherwise, OFF
then ON: otherwise, OFF
exponent is > +127, then ON
Exponent
Underflow- If exponent of floating point result < - 128, then ON
NOTES:
= 1 the the hex permission flag = 1, the
floating-point alignment and normalization are hexadecimal.
Otherwise, the floating-point alignment and normalization are
binary. The hex permission flag is Mode register bit 33.
1. When indicator bit 32
2. An Illegal Procedure fault occurs if illegal address
modification is used.
8-194
DZSI-00
(
DUFS
DUFS
DUFS
Double-Precision Unnormalized Floating Subtract
537 (0)
FORMAT:
single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
[C(EAQ) - C(Y-pair)]
C(y -pa i r) unchanged
EXPLANATION:
The two's complement of the subtrahend is first taken and the
smaller value is then right-shifted to equalize it. The
portion shifted out is truncated and addition is executed.
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
None
I NDI CATORS:
Zero
not normalized -> C(EAQ)
= 0, then ON; otherwise, OFF
C(AQ)O = 1, then ON; otherwise, OFF
- If C(AQ)
Negative - If
Exponent
Overflow - If exponent is > +127, then ON
Exponent
Underflow - If exponent of floating point result < - 128,
then ON" .
carry
NOTES:
- If a carry out of bit 0 of C(AQ) is generated,
then ON: otherwise, OFF
1. When indicator bit
the floating-point
the floating-point
permission flag is
32 = 1 and the hex permission flag = 1,
alignment is hexadecimal. Otherwise,
alignment is binary. The hex .
Mode register bit 33.
2. An Illegal Procedure fault occurs if illegal address
modification is used.
8-195
DZSI-OO
DV2D
DV2D
FORMAT:
Divide Using Two Decimal Operands
DV2D
o0
o1
1 1
o1
Ipl 0- - - - - - - - 01~1
0
0
1 1
7 8
MF2
I
207 (1)
Op Code
222
789
H
207(1)
1 1 2 2 2 2 2
7 8 0 1 2 3 4
0
2
3
MF1
2
9
3
5
Yl
CN1 TN1 Sl
SF1
N1
Yl
o
o
1 1 2 2 2 2 2
7 8 0 1 234
0
2
Y2
CN2 TN2 S2
2
9
SF2
3
5
N2
Y2
COD! NG FORMAT:
The DV2D instruction is coded as follows:
1
8
16
DV2D
NOSCn
NOSCn
(MF1),(MF2),RD,P
LOCSYM,CN,N ,S,SF,AM
LOCSYM,CN,N,S,SF,AM
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
OPERATI NG MODES:
Any
8-196
DZ51-00
(
DV2D
DV2D
SUMMARY:
C(string 2) / C(string 1) --> C(string 2)
EXPLANATION:
same as for DV3D except that the quotient is sto~ed using
YC2, TN2, S2 and, if S2 indicates a scaled format, SF2.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MFl and MF2
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
same as for DV3D
NOTE:
The notes of DV3D apply.
EXAMPLES:
1
FLDl
FLD2
8
16
32
DV2D
NDSC4
NDSC4
USE
FLD1,4,4,2,-4
FLD2,0,8,0
divisor operand descriptor
dividend operand descriptor
memory contents
0002+
+08642 +0
+43210 +3
(Quotient)
EDEC
EDEC
CONST.
8P2+
8P+8642EO
USE
DV2D
NDSC9
NDSC4
USE
FLDl
FLD2
EDEC
EDEC
USE
*
, ,1
FLD1,0,4,1,-3
FLD2,O,8,1,-2
CONST.
4A+5
8P+1234
with rounding option
divisor operand descriptor
dividend operand descriptor
memory contents
+ 005
+0001234
+0246800
(Quotient)
indicators on? none
8-197
DZ51-00
DV2DX
DV2DX
DV2DX
Divide Using Two Decimal Operands Extended
247 (1)
FORMA'l':
o
0
0
1 1
1 1
Code
222
247(1)
MF2
o
o
Op
1 1
7 8
0
2
2 2
0 1
3
NFl
222
234
2 3
3
5
9 0
Y1
CN1
SFl
Nl
Y1
AR#
o
o
TN1 SX1
1 1
7 8
0
2
2 2
0 1
222
234
2 3
3
5
9 0
Y2
CN2 TN2 SX2
AR#
COD!NG FORMAT:
SF2
N2
Y2
1
B
16
DV2DX
NDSCn
NDSCn
(MF1),(NF2),RD,CS,NS
LOCSYM, CN , N, SX, SF , AM
LOCSYM, CN , N, SX, SF , AM
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
OPERATI NG MODES:
Any
8-198
DZ51-00
DV2DX
DV2DX
SUMMARY:
C(string 2) / C(string 1) --> C(string 2)
EXPLANATION:
Same as for Dv3DX except that the quotient is stored using
YC2, TN2, Sx2 and, if SX2 indicates a scaled format, SF2.
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL for MFl or MF2
I LLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
Same as for Dv3D
NOTES:
1. Notes of Dv3D apply.
2.
See WNX for information about coding of overpunched
signs.
(
(
8-199
DZS1-OO
DV3D
DV3D
Divide Using Three Decimal Operands
DV3D
227
(1)
FORMAT:
001 1
890 1
000
012
1+1
0
0
HRDI
MF3
1 1
7 8
MF2
Code
222
789
II I
227(1)
I
1 1
7 8
0
2
Op
2 2
o1
2 2 2
234
3
5
NFl
2 3
9 0
I
3
5
Y2
CN2 TN2 S2
N2
Y2
AR#
o
o
SF2
1 1
7 8
0
2
Y3
AR#
CODI NG FORMAT:
CN3
2 2
0 1
222
234
TN3 S3
2 3
9 0
SF3
3
5
N3
Y3
The DV3D instruction is coded as follows:
1
8
16
DV3D
NOSC,!!
NOSC,!!
NOSC,!!
(MF1),(NF2),(MF3),RD,P
LOCSYM,CN,N,S,SF,AM
LOCSYM,CN,N ,S,SF,AM
LOCSYM,CN,N ,S,SF ,AM
(Refer to Section 7 under Multiword Instructions for
description of Mu1tiword Modification Field.)
8-200
DZ51-00
«
DV3D
Dv3D
OPERATI NG MODES:
Any
SUMMARY:
C(string 2) / C(string 1)
EXPLANATION:
The decimal number of data type TNl, sign and decimal type
S1, and starting location YC1, is divided into the decimal
number of data type TN2, sign and decimal type S2, and
starting location YC2. The quotient is stored starting in
location YC3 as a decimal number of data type TN3 and sign
and decimal type S3.
-->
C(string 3)
If S3 indicates a fixed-point format, the quotient is stored
using scale factor SF3, which may cause leading or trailing
zeros (4 bits - 0000, 9 bits - 000110000) to be supplied
and/or most-significant-digit overflow or
least-significant-digit truncation to occur.
If S3 indicates a floating-point format, the quotient is
right-justified to preserve the most significant nonzero
digits; this may cause least-significant-digit truncation.
(
If P=l, positive signed 4-bit results are stored using octal
13 as the plus sign. If P=O, positive signed 4-bit results
are stored with octal 14 as the plus sign.
If RD is a 1, the quotient is rounded prior to storage.
Provided that strings 1, 2, and 3 are not overlapped, the
contents of the decimal numbers that start in locations YC1
and YC2 remain unch?~ged.
The divide operation stops when the number of required digits
have been formed or, in the case where rounding is specified
(RD = 1), when the required number of quotient digits plus 1
have been formed. In fixed-point operations or
floating-point operations where the quotient is stored in
fixed-point format, the required number of quotient digits is
determined as follows:
When the quotient descriptor specifies that the quotient
is to be stored in fixed-point format, the necessary
number of quotient digits to form is calculated as
follows:
#QD
= (LD-#LZD+l)-(LDR-#LZR}+(ED-EDR-EQ)
(
8-201
DZ5l-00
DV3D
DV3D
where:
#LZD = number of leading zeros in dividend
#QD = number of quotient digits to form
LD
= length of dividend
LDR = length of divisor
#LZR = number of leading zeros in divisor
ED
= exponent of dividend
EDR
= exponent
EQ
= scale factor for quotient
of divisor
The hardware performs this calculation prior to beginning
the divide operation and, if #QD > 63, the divide
operation does not take place; a Divide Check fault
occurs. If #QD<=O, then zero is stored.
In a floating-point divide operation, the required number
of quotient digits is determined as follows. With the
divisor greater than the dividend, a leading zero is
generated in the quotient. The leading zero counts as one
of the generated output digits. For example, if 4-digit
output accuracy is specified and the above relationship
exists between the divisor and the dividend, only 3-digit
accuracy will be attained. Under this condition, it would
be necessary to specify a 5-digit output to achieve
4-digit accuracy.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MFl, MF2, and MF3
I LLEGAL REPEATS:
RPT, RPD, RPL
8-202
DZ51-00
(
DV3D
DV3D
I NDI CATORS :
Zero
-
If result equals zero, then ON: otherwise, OFF
Negative
-
If result is negative, then ON; otherwise, OFF
Exponent
Overflow
-
If exponent of floating-point result is
then ON
Exponent
Underflow
-
If exponent of floating point result
then ON
Overflow
-
If fixed-point integer overflow, then ON;
otherwise, unchanged
Truncation NOTES:
1.
An
>
< -
127,
128,
If the least significant digits are truncated
without rounding, then ON; otherwise, OFF
Illegal Procedure fault occurs if:
o DU or DL modification is specified for NFl or NF2.
:(
o Any character (least four bits) other than 0000 - 1001
is detected where digits are defined, or any character
(least four bits) other than 1010 - 1111 is detected
where the sign is defined by the numeric descriptor.
o The values for the number of characters (N1 or N2) of
the data descriptors are not large enough to hold the
number of characters required for the specified sign
and/or exponent, plus at least one digit.
2. A Divide Check fault occurs under either of the following
two conditions.
o I f the divisor equals zero.
starting at YC1.
The divisor is the number
o If 53 specifies that the quotient be stored in scaled
format and the calculated lerigth required for the
quotient is greater than 63 (refer to length
requirements above).
3. If an illegal digit or sign is detected, the receive field
is not changed before the IPR fault occurs.
8-203
DZSI-OO
DV3D
DV3D
./
EXAMPLE:
1
FLD1
FLD2
FLD3
EXAMPLE WI TH
B
16
32
DV3D
NDSC9
NDSC4
NDSC4
USE
!DEC
!DEC
BSS
USE
" ,1,1
FLD1,1,3,2,-2
FLD2,0,9,0
FLD3,2,6,1,-1
CONST.
4A29P-B76543E-3
with rounding and plus sign options
divisor operand descriptor
dividend operand descriptor
quotient operand descriptor
memory contents
002-B76543-3
xx+3B272
(Quotient)
instruction fault? overflow
1
ADDRESS MODI FI CATION:
1
options
(FLD1,2,2,3,-2)
(FLD2,0,B,0)
FLD1
FLD2
FLD3
32
B
16
EAX2
EAX7
EAX4
AWDX
DV3D
load character modifier into X2
2
load FLD2 length into X7
B
FLD1
load FL01 address into X4
0,4,4
put FLD1 address into AR4
(1" ,2), (,1), (, ,1) ,1,1 with address modification
NDSC9
0,0,2,3,-2,4
divisor operand descriptor
NDSC9
FLD2,0,X7,0
dividend operand descriptor
ARG
2,2,4
pointer to quotient operand descriptor
USE
!DEC
!DEC
BSS
NDSC4
USE
CONST.
4A2
BA+B76543E-3
1
FLD3,1,7,1,-1
memory contents
0002
+B76543-3
x+438272
quotient operand descriptor
instruction fault?
none
B-204
DZ51-00
DV3DX
DV3DX
Divide Using Three Decimal Operands Extended
DV3DX
267 (1)
FORMAT:
IcsH
0
0
1 1
7 8
1 1
0 0 0
0 1 2
o1
I
MF3
I
MF2
0
1 1 2 2
2
7
8 0 1
Op Code
222
789
227(1)
II I
22:2
:2 3 4
2 3
9 0
3
5
I
MFl
3
5
Yl
CNl TN1 SXl
o
o
Nl
Yl
AR#
(
SFl
1 1 2 2
7 801
0
2
222
234
:2 3
9 0
3
5
Y:2
CN:2 TN2 SX:2
N2
Y2
AR#
o
o
SF2
1 1 2 2
7 801
0
:2
222
234
2 3
9 0
3
5
Y3
CN3 TN3 SX3
AR#
CODING FORMAT:
SF3
N3
Y3
1
8
16
DV3DX (MF1),(MF:2),(MF3),RD,CS,NS
NDSCn LOCSYM,CN,N,SX;SF,AM
NDsCn LOCSYM,CN,N,SX,SF,AM
NDSCn LOCSYM, CN , N, SX, SF ,AM
(
8-205
DZ5l-00
DV3DX
DV3DX
(Refer to Section 7 under Multiword Instructions for
description of Nultiword Modification Field.)
OPERATI NG MODES:
Any
SUMMARY:
C(string 2) I C(string 1) --> C(string 3)
EXPLANATION:
The decimal number of data type TN1, sign and decimal type
SXl, and starting location YCl, is divided into the decimal
number of data type TN2, sign and decimal type SX2, and
starting location YC2. The quotient is stored starting in
location YC3 as a decimal number of data type TN3 and sign
and decimal type SX3.
If SX3 indicates a fixed-point format, the quotient is stored
using scale factor SF3, which may cause leading or trailing
zeros (4 bits - 0000, 9 bits - 000110000) to be supplied,
most-significant-digit overflow, or least-significant-digit
truncation.
If SX3 indicates a floating-point format, the quotient is
right-justified to preserve the most-significant nonzero
digits; this may cause least-significant-digit truncation.
The character set is defined by CS (EBCDIC/ASClI). Placement
of overpunched sign in the output is controlled by NS.
(Refer to the introductory pages of this section for
definition of the NS field.) If RD is 1, the quotient is
rounded prior to storage. The contents of the decimal
numbers that start in locations YCl and YC2 remain unchanged.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MFl, MF2, or MF3
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
same as for DV3D.
8-206
DZ51-00
(
DV3DX
DV3DX
NOTES:
1. Explanation of the divide operation in the DV3D
description apply.
2. A divide check fault occurs under either of the following
two conditions:
o If the divisor (the number starting at YC1) equals
zero.
o If SX3 specifies that the quotient be stored in
fixed-point format and the calculated length required
for the quotient is greater than 63 (see Note 2 of
DV3D).
3. Refer to specifications on MVNX for information about
coding of overpunched signs.
4. IPR fault conditions are the same as for DV3D.
(
f
8-207
DZSI-OO
DVF
DVF
DVF
Divide Fraction
507 (0)
FORMAT:
single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(AQ) I C(Y)
fractional quotient --> C(A), left-adjusted
fractional remainder --> C(Q), left-adjusted
C(y) unchanged
EKPLANATION:
This instruction divides a 7l-bit fractional dividend
(including sign) by a 36-bit fractional divisor (including
sign) to form a 36-bit fractional quotient (including sign)
and a 36-bit fractional remainder (including sign). Bit 35
of the remainder corresponds to bit 70 of the dividend. The
remainder sign is equal to the dividend sign unless the
remainder is zero. Bit 71 of C(AQ) is not used.
7 7
0 1
0 0
0 1
I51
,
'
Ixl
dividend
C(AQ)
/'
I
o
0
3
divisor
C(Y)
yielding:
o
3
0
quotient
o
0
3
remainder
C(A)
C=
Idivisorl
or if the divisor = 0,
division does not take place. Instead, a Divide Check fault
occurs, C(Y) remains unchanged, C(AQ) contains the dividend
magnitude as an absolute value, and the negative indicator
reflects the dividend sign.
ADDRESS
MODIFICATIONS:
None
I LLEGAL REPEATS:
None
I LLEGAL
INDICATORS:
zero
If division takes place:
If no division takes place:
If C(A) = 0, then ON:
otherwise, OFF
If divisor = 0, then ON:
otherwise, OFF
Negative If C(A)O = 1, then ON;
otherwise, OFF
If dividend < 0, then ON:
otherwise, OFF
(
8-209
DZ51-00
DVRR
DVRR
Divide Register by Register
DVRR
533
(1)
FORMAT:
o
1 1
0 0
Not Used
CODING FORMAT:
1
8
16
DVRR
R1"R2
Executes in ES mode only
SUMMARY:
When "register pair" is implied
= 0,
3
OP CODE
OPERATING MODES:
Rl, R2
22233
2, 4, 6, AQ
otherwise
Rl, R2
= 0,
1, 2, 3, 4, 5, 6, 7, A, Q
Quotient of C(Rl-odd) / C(R2) --> C(R1-odd)
Remainder of C(Rl-odd) / C(R2) --> C(R1-even)
C(R2) unchanged
EXPLANATION:
A register pair is specified in R1. The content of the
odd-numbered register, or Q if AQ is specified, is divided by
C(R2). The resulting quotient is loaded into Rl-odd and the
remainder into Rl-even.
I LLEGAL ADDRESS
MODIFICATIONS:
None.
ILLEGAL REPEATS:
RPT, RPD, RPL
The address modification is not executed.
ILLEGAL EXECUTES: Execution in NS mode
8-210
DZS1-OO
(
DVRR
DVRR
If division takes place:
I NDI CATORS :
Zero
If C(Rl-odd) = 0, then ON; If divisor = 0, then ON;
otherwise, OFF
otherwise, OFF
Negative If C(Rl-odd)O = 1,
then ON; otherwise, OFF
NOTES:
If no division takes place:
If dividend < 0, then ON;
otherwise, OFF
1. An IPR fault occurs if illegal repeats are executed or if
the instruction is executed in NS mode.
2. Refer to Register to Register Instructions in Section 7
for a description of the fields in the instruction word.
3. Both the dividend and divisor are regarded as a 36-bit
signed integer. The sign of the remainder is the same as
that of the dividend unless the remainder is O.
4. A Divide Check fault occurs in the following cases:
o Dividend
o Divisor
= -2 35
=0
and divisor
+ -1
In these cases, the instruction is not executed. C(R2)
remains unchanged, C(Rl-odd) takes the absolute value of
the dividend, and C(Rl-even) is O. If the dividend is
-2 35 , then -2 35 is loaded into Rl-odd.
(
8-211
DZSI-OO
BAA
BAA
BAA
Effective Address to A-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERA'l'I NG MODES:
Any
SUMMARY:
NS mode
635 (0)
Y --> C(A)O-17
0 ••• 0 --> C(A)18-35: C(Y) unchanged
ES
mode
00 --> C(A)O-l
YO-33 --> C(A)2-35; C(Y) unchanged
EXPLANATION:
This instruction permits inter-register data movement. The
data source is specified by the address modification and the
data destination by the operation code of the instruction.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL
ILLEGAL REPEATS:
RPL
I NDI CA'l'ORS:
Zero
-
Negative NOTES:
= 0, then ON; otherwise, OFF
C(A)O = 1, then ON: otherwise, OFF
If C(A)
If
1. An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
2. In the
OFF.
ES
mode, the negative indicator is always set to
/
8-212
DZ51-00
EAQ
EAQ
EAQ
Effective Address to Q-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
636 (0)
Y -> C(Q)O-17i
00 ••• 0 --> C(Q)18-3Si C(Y) unchanged
ES Mode
00 ••• 0 --> C(Q}O-l
YO-33 -->C(Q)2-3S)
EXPLANATION:
This instruction permits inter-register data movement. The
data source is specified by the address modification and the
data destination by the operation code of the instruction.
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL
ILLEGAL REPEATS:
RPL
I NOI CATORS:
Zero
-
Negative NOTES:
If C(Q)"
If C(Q)O
= 0,
then ONi otherwise, OFF
= 1,
then ONi otherwise, OFF
1. An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
2. In the ES mode, the negative indicator is always set to
OFF.
8-213
DZSI-OO
EAXn
EAXn
Effective Address to Index Register n
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
For n
= 0,1, ••• ,7
YO-33
-->
ES
62n (O)
as determined by opcode
(Xn); C(Y) unchanged
Mode
For n
= 0,1, ••• ,7
as determined by opcode
00 --> C(GKn) 0-1
YO-33 --> C( GKn)2-35
EXPLANATION:
This instruction permits inter-register data movement. The
data source is specified by the address modification and the
data destination by the operation code of the instruction.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL
I LLEGAL REPEATS:
RPT, RPD, or RPL of EAXO
I NDI CATORS:
Zero
-
Negative NOTES:
= 0, then ON: otherwise, OFF
C(xn/GKn)o = 1, then ON: otherwise, OFF
If C(Xn/GKn)
If
1. An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
2. In the ES mode, the negative indicator is always set to
OFF.
8-214
DZ51-00
(
EPAT
EPAT
EPAT
Effective Pointer and Address to Test
412
(1)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
EXPLANATION:
This instruction tests the virtual address to real memory address
mapping function of the hardware. Addresses are generated in the
normal sequence and stored in four special test registers instead
of accessing memory.
Real memory addressl-27
-->
C(Test Reg 0)0-26
Effective WSN
-->
C(Test Reg 0)27-35
Relative Virtual address
-->
C(Test Reg 1)0-35
C(DR}effective
--> C(Test Reg 2,3)
The high-order real address bit is not placed in the test
register.
(
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
None affected
NOTES:
l. Illegal address modifications and illegal repeats cause an IPR
fault.
2. This instruction is only intended for use with Test and
Diagnosis (T&D) programs.
8-215
DZ5l-00
EPPRn
EPPRn
Effective Pointer to Pointer Register
n
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
This set of eight instructions generates an effective address
(EA) and loads it into the pointer register (ARn, SEGaDn,
DRn).
NS Mode
If instruction bit 29
=0
then
SEGID{IS)
-> SEGIDn
C{ISR)
--> C(DRn)
If instruction bit 29
forming EA, then
=1
and indirection is not used in
Effective address (EA)
-->C(AR)O-23
Effective SEGID
->C(SEGIDn)
Effective DR
->C(DRn)
If instruction bit 29
EA, then
= 1 and
indirection is used in forming
EAO-17
-->C(ARn)O-17
O••• 0
-->C(ARn)18-23
SEGIDm
->SEGIDn
C(DRm)
-->DRn
8-216
DZ51-00
(
EPPRn
EPPRn
ES Mode
If instruction bit 29
->C(AR)O-29
EA34-39
->C(AR)30-35
Effecti ve SEGI D
->C(SEGIDn)
Effective DR
-->C(DRn)
=1
and indirection is not used in
EA4-39
->C(AR)0-35
SEGIDm
->SEGIDn
C(DRm)
->C(DRn)
If instruction bit 29
EA, then
EXPLANATION:
then
EA4-33
If instruction bit 29
forming EA, then
(
= 0,
=1
and indirection is used in forming
EA4-33
->C(ARn)0-29
EA34-39=O
->C( ARn 30-35
SEGIDm
->SEGIDn
C(DRm)
->C(DRn)
If the instruction bit 29 = 0, AR is not used for generation
of the effective address and the ARn byte and bit portions
are set to zero.
When the instruction bit 29 = 0, the generated operand
address is in the instruction segment. The ISR and SEGID(IS)
content are loaded into DRn and SEGIDn, respectively.
If the instruction bit 29 = 1, the Address Register ARm
specified with bits 0, 1, and 2 of the in~truction word are
used to generate the effective address. Provided that
indirect modification is not specified, the ARn byte and bit
portions are preserved during computation of the effective
address and loaded into the byte and bit portions of the
corresponding ARn. If indirect modification is specified,
zero is loaded into the ARn byte and bit portions.
8-217
DZ51-00
EPPRn
EPPRn
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTE:
An IPR fault occurs if illegal address modification or
illegal repeats are used.
EXAMPLE:
1
8
16
32
ADO
=3HOBI,OC
file codef ile
read permissions
allocate file command block
allocate file
ORQ
EPPRO
PPME
ALCPRF
ALPRMF,2
VEC
.ISR,NAME,NAMEX,(R,W,S)
.ISR,CBUFF,CBUFFX,(R,W,S)
BCI
4
ALEPRF VEe
NAME
=0400000,DL
NAMEX EQU
CBUFF BSS
CBUFFX EQU
*-NAME
355
*-CBUFF
8-218
DZ5l-00
ERA
ERA
EXCLUSIVE OR to A-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
For i
=0
675 (0)
to 35, C(A)i XOR C(Y)i --> C(A)ii
C(y) unchanged
ILLEGAL ADDRESS
MODIFICATIONS:
None
I LLEGAL REPEATS:
None
I NDI CATORS :
Zero
-
Negative -
= 0, then ONi otherwise, OFF
C(A}O = 1, then ON: otherwise, OFF
If C(A}
If
8-219
DZ51-00
ERAQ
ERAQ
ERAQ
EXCLUSIVE OR to AQ-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATl NG MODES:
Any
SUMMARY:
For i = 0 to 71, C(AQ)i XOR C(Y-pair)i --> C(AQ)ii
C(Y-pair) unchanged
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL,
I LLEGAL REPEATS:
None
I NDI CATORS:
Zero
a, SC, SCR
-
Negative NOTE:
677 (0)
= 0, then ON; otherwise, OFF
C(AQ)O = 1, then ONi otherwise, OFF
If C(AQ)
If
An Illegal Procedure fault occurs if illegal address
modification is used.
8-220
DZ51-00
ERQ
ERQ
ERO
EXCLUSIVE OR to Q-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
For i = 0 to 35, C(Q)i XOR C(Y)i --> C(Q)i:
C(y) unchanged
I LLEGAL ADDRESS
MODIFICATIONS:
None
ILLEGAL REPEATS:
None
I NDI CATORS :
Zero
-
Negative -
If C(Q)
If C{Q)O
= 0,
676 (0)
then ON: otherwise, OFF
= 1, then ON: otherwise, OFF
8-221
DZ5l-00
ERRR
ERRR
ERRR
EXCLUSIVE OR Register to Register
537 (1)
FORMAT:
1 1
7 8
000
Not Used
CODING FORMAT:
1
OP CODE
I
8
16
ERRR
Rl, ,R2
OPERATING MODES:
Executes in ES mode only.
SUMMARY:
Rl, R2
= 0,
222 3 3
789 1 2
3
5
H I I
MBZ
R2
1, 2, 3, 4, 5, 6, 7, A, Q
C(Rl)i XOR C(R2)i
-->
C(Rl)I
i
= 0,
1, 2, ••• ,35
C(R2) unchanged
I LLEGAL ADDRESS
MODIFICATIONS:
None.
ILLEGAL REPEATS:
RPT, RPD, RPL
The address modification is not executed.
ILLEGAL EXECUTES: Execution in NS mode
I NDI CATORS :
Zero
-
Negative NOTES:
= 0, then ON; otherwise, OFF
C(Rl)O = 1, then ON; otherwise, OFF
If C(Rl)
If
1. An IPR fault occurs if illegal repeats are executed or if
the instruction is executed in NS mode.
2. Refer to "Register to Register Instructions" in Section 7
for a description of the fields in the instruction word.
8-222
DZ51-00
ERSA
ERSA
ERSA
EXCLUSIVE OR to Storage with A-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
For i = 0 to 35, C(A)i XOR C(Y)i --> C(Y)i;
C(A) unchanged
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPL
INDICATORS:
Zero
-
Negative NOTES:
655 (0)
If C(Y) = 0, then ON; otherwise, OFF
If C{Y)O
= 1,
then ON; otherwise, OFF
1. An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
2. See Examples under ERA.
(-'8-223
DZ51-00
ERSQ
ERSQ
ERSQ
EXCLUSIVE OR to Storage with Q-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
For i = 0 to 35, C(Q)i XOR C(Y)i --> C(Y}i;
C(Q) unchanged
I LLEGAL ADDRESS
MODI Fl CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPL
I NDI CATeRS:
zero
If C(Y) = 0, then ON: otherwise, OFF
Negative
NOTE:
EXAMPLE:
656 (0)
-
If C(Y)O
= 1,
then ON: otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
1
8
16
LDQ
ERSQ
FLAG
=l,DL
* If bit 35 of FLAG is ON, then set to zero
,
\
8-224
DZ51-00
ERSXn
ERSXn
EXCLUSIVE OR to Storage with Index Register n
FORMAT:
single-word instruction format (see Figure 8-l)
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
For n
= 0,1, ••• ,7
64n (O)
as determined by op code
For i = 0 to 17, C(Xn}i XOR C(Y)i --> C(Y)i;
C(Xn) and C(Y)18-35 unchanged
ES Mode
For n
For i
= 0,1, ••• ,7 as determined by
= 0 to 35, C(GXn)i XOR C(Y)i
op code
-->
C{Y)i;
C(GXn ) is unchanged
(
I LLEGAL ADDRESS
MODI Fl CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, or RPL of ERSXO
I NDI CATORS:
NS Mode
Zero
-
If C(Y)0-17
Negative
-
If C(Y)O
Zero
-
If C(Y)
Negative
-
If
= 0,
= 1,
then ON; otherwise, OFF
then ON; otherwise, OFF
ES Mode
NOTE:
= 0, then ON; otherwise, OFF
C(Y)O = 1, then ON; otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
(
8-225
DZSI-OO
ERXn
ERXn
EXCLUSI VE OR to Index Register g
66g (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
For n
For i
= O,l, ••• ,or 7 as
= 0 to 17, C(Xn)i
determined by op code
XOR C(Y)i --> C(Xn)i:
C(Y) unchanged
ES Mode
For n
For i
= O,l, ••• ,or 7 as determined
= 0 to 35, C(GXn)i XOR C(Y)i
by op code
--> C(GXn)ii
C(y) unchanged
ILLEGAL ADDRESS
MODI F1 CATIONS:
CI, SC I SCR
I LLEGAL REPEATS:
RPT, RPD, RPL of ERXO
I NDI CATORS:
NS Mode
Zero
-
If C(Xg) = 0, then ON: otherwise, OFF
Negative
-
If C(xg)O
Zero
-
If C(GXg)
Negative
-
If
ES
NOTES:
= 1,
then ON; otherwise, OFF
Mode
= 0, then ON: otherwise, OFF
C(GXg)O = 1, then ON; otherwise, OFF
1. DL modification is flagged illegal but executes with all
zeros for data.
2. An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
8-226
DZ5l-00
FAD
FAD
FAD
475 (0)
Floating Add
FORMAT:
single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
[C(EAQ)
ILLEGAL ADDRESS
MODIFICATIONS:
CI,
I LLEGAL REPEATS:
None
I NDI CATORS :
Zero
-
If
Negative
-
If
Exponent
Overflow
-
If exponent is > +127, then ON
Exponent
Underflow
-
If exponent of floating point result < - 128,
then ON
Carry
-
If a carry out of bit 0 of
then ON; otherwise, OFF
NOTES:
+
normalized ->
C(Y)]
C(EAQ); C(Y)
unchanged
se, SCR
= 0, then ON; otherwise, OFF
C(AQ)O = 1, then ON; otherwise, OFF
C(AQ)
C(AQ)
is generated,
1. When indicator bit 32 = 1 and the hex permission flag = 1,
the floating-point alignment and normalization are
hexadecimal. Otherwise, the floating-point alignment and
normalization are binary. ,The hex permission flag is Mode
register bit 33.
2~
See the FNO instruction for a definition of normalization.
3. An Illegal Procedure fault occurs if illegal address
modification is used.
(
8-227
DZ51-00
FCMG
FCMG
FCMG
Floating Compare Magnitude
425 (a)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
IC(E,AQO-27)I :: IC(y)l; magnitude comparison;
C{EAQ), C{Y) unchanged.
EXPLANATION:
This comparison is executed as follows:
1. Compare C{E) :: C{Y)O-7, select the number with the lower
exponent, and shift its mantissa right by the number of
places (binary or hex) determined by the difference of the
exponents. If the number of shifts equals or exceeds 72,
the number with the lower exponent is defined as zero.
2. Compare the absolute values of the mantissas and set the
indicators accordingly.
The FCMG instruction is identical to the FCMP instruction
except that the magnitudes of the mantissas are comparedinstead of the algebraic values.
ILLEGAL ADDRESS
NODI FI CATIONS:
a, SC, SCR
ILLEGAL REPEATS:
None
INDICATORS:
Zero
NOTES:
N~ative
RelationshiQ
0
0
IC(E,AQO-27I > IC(Y) I
1
0
IC(E,AQO-27I
0
1
IC(E,AQO-27I < IC(Y) I
=
IC(Y) I
1. When indicator bit 32 = 1 and the hex permission flag = 1,
the floating-point alignment is hexadecimal. Otherwise,
the floating-point alignment is binary. The hex
permission flag is Mode register bit 33.
2.
Illegal Procedure fault occurs if illegal address
modification is used.
An
8-228
DZ5l-00
<.
FCMP
FCMP
FCMP
Floating Compare
515 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(E,AQO-27):: C(Y); algebraic comparison
EXPLANATION:
This comparison is executed as follows:
1. Compare C(E) :: C(Y)Q-7, select the number with the lower
exponent, and shift lts mantissa right by the number of
places (binary or hex) determined by the difference of the
exponents. If the number of shifts equals or exceeds 72,the number with the lower exponent is defined as zero.
2. Compare the mantissas and set the indicators accordingly.
(
I LLEGAL ADDRESS
MODIFICATIONS:
CI, SC, SCR
I LLEGAL REPEATS:
None
I NDI CATORS:
zero
NOTES:
N~ative
Relationshi~
0
0
C(E,AQO-27 > C(Y)
1
0
C(E,AQO-27
= C(Y)
0
1
C(E,AQO-27
<
1. When indicator bit
the floating-point
the floating-point
permission flag is
C{Y)
32 = 1 and the hex permission flag = 1,
alignment is hexadecimal. Otherwise,
alignment is binary. The hex
Mode register bit 33.
2. An Illegal Procedure fault occurs if illegal address
modification is used.
8-229
DZSI-OO
FOr
FOr
FDr
Floating Divide Inverted
525 (O)
FORMAT:
Single-word instruction format (see Figure 8-l)
OPERATI NG MODES:
Any
SUMMARY:
C(Y} / C(EAQ} --> C(EA}: 00 ••• 0
contents of C(Y) unchanged
EXPLANATION:
The dividend mantissa is shifted right and the dividend
exponent is increased accordingly until:
-->
C(Q);
IDividend mantissa I < IC(AQO-27)I
When such a shift occurs, only zeros from the dividend will be
lost.
C(AQ)0-27
is used as the divisor mantissa.
36 bits of quotient mantissa are placed in A.
If AQ28-71 is not equal to 0 and AO = 0, then 1 is added to
AQ27. 0 --> AQ28-7l unconditionally. AQO-27 is then used as
the divisor mantissa. The 8-bit dividend exponent and 72-bit
mantissa are placed in working registers.
ILLEGAL ADDRESS
MODIFICATIONS:
CI, SC, SCR
I LLEGAL REPEATS:
None
I NDI CATORS:
Zero
-
Negative Exponent
Overflow -
If division occurs:
If no division occurs:
If C(A) = 0, then ON;
otherwise, OFF
If divisor mantissa = 0,
then ON: otherwise, OFF
If C(A)O = 1, then
ON: otherwise, OFF
If dividend < 0, then
ON: otherwise, OFF
If exponent is > +127,
then ON
Exponent
Underflow- If exponent of floating
point result < - 128, then ON
8-230
DZ51-00
FDr
FDr
NOTES:
1. When indicator bit 32 = 1 and the hex permission flag = 1,
the floating-point alignment and normalization are
hexadecimal. Otherwise, the floating-point alignment and
normalization are binary. The hex permission flag is Mode
register bit 33.
2. If the divisor mantissa C(AQ) is zero, division does not
take place. Instead, a Divide Check fault occurs and all
registers remain unchanged.
Dividend and divisor are not
normalized by the hardware prior to division.
3. An Illegal Procedure fault occurs if illegal address
modification is used.
(
8-231
DZ51-00
FDV
FDV
Floating Divide
FDV
565 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(EAQ) / C(Y) --> C(EA); 00 ••• 0 --> C(Q); C(Y) unchanged
EXPLANATION:
This division is executed as follows:
The dividend mantissa C(AQ) is shifted right and the
dividend exponent C(E) is increased accordingly until
IC(AQ}0-271 < IC(Y}8-35 with zero filll
When such a shift occurs, significant bits from the dividend
may be lost.
Dividend and divisor are not normalized by the hardware
prior to division.
36
bits of quotient mantissa are placed in A.
ILLEGAL ADDRESS
MODIFICATIONS:
CI, SC, SCR
ILLEGAL REPEATS:
None
I NDI CATORS :
Zero
-
Negative Exponent
Overflow -
If division occurs:
If no division occurs:
If C(A) = 0, then ON;
otherwise, OFF
If divisor mantissa = 0,
then ON: otherwise, OFF
If C(A)O = 1, then
ON; otherwise, OFF
If dividend < 0, then
ON; otherwise, OFF
If exponent is > +127,
then ON
Exponent
Underflow- If exponent of floating
point result < - 128, then ON
8-232
DZ51-00
FDV
FDV
NOTES:
1. When indicator bit 32 = 1 and the hex permission flag = 1,
the floating-point alignment and normalization are
hexadecimal. Otherwise, the floating-point alignment and
normalization are binary. The hex permission flag is Mode
register bit 33.
2. If the divisor mantissa (bits 8-35 of C(Y» is zero,
division does not take place. Instead, a Divide Check
fault occurs. The divisor C(Y) remains unchanged, C(AQ)
contains the dividend's magnitude as an absolute value,
and the negative indicator reflects the dividend's sign.
3.
An Illegal Procedure fault occurs if illegal address
modification is used.
(
8-233
DZ51-00
FLD
FLD
FLO
Floating Load
431 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
CCY>O-7 --> C(E)
C(Y)8-35 --> C(AQ)0-27
I LLEGAL ADDRESS
MODI PI CATIONS:
a,
I LLEGAL REPEATS:
None
I NDI CATORS :
Zero
-
If C(AQ)
Negative
-
If C(AQ)O
NOTE:
SC, SCR
= 0,
= 1,
then ONi otherwise, OFF
then ONi otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modification is used.
8-234
j
DZS1-00
(
FLP
FLP
FLP
Floating Load Positive
530 (0)
FORMAT:
single-word instruction format (see Figure 8-1)
OPERATING MODES:
Any
SUMMARY:
IC(y) I,
normal ized -> Z
ZO-7 --> C(E)
Z8-35 -> C(AQ)0-27
00 ••• 0 --> C(AQ)28-7l
EXPLANATION:
(
The memory operand C(Y) is processed as single-precision
floating-point data. The absolute value of this data is
normalized and its exponent, mantissa (bits 8-35) and 0 are
loaded into C(E), C(AQ)0-27 and C(AQ)28-7l, respectively.
I LLEGAL ADDRESS
MODI FI CATIONS:
CI, SC, SCR
I LLEGAL REPEATS:
None
INDICATORS:
Zero
-
= 0,
then ON; otherwise, OFF
= 1, then ON; otherwise, OFF
Negative -
If C(AQ)O
Exponent
Overflow -
If exponent> +127, then ON
Exponent
Underflow
NOTE:
If C(AQ)
If exponent of floating point result < - 128, then
ON
An Illegal Procedure fault occurs if illegal address
modification is used.
(
8-235
DZSI-OO
FMP
FMP
I
Floating Multiply
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Any
SUMMARY:
[C(EAQ) * C(Y)]
EXPLANATION:
This multiplication is executed as follows:
461 (0)
normalized -> C(EAQ); C(Y) unchanged
C(E) + C(Y)0-7 --> C(E)
C(AQ) * C(Y)8-35 results in a 98-bit product plus sign,
the leading 71 bits plus sign of which --> C(AQ).
C(EAQ) normalized --> C(EAQ ) •
The definition of normalization is located under the
description of the FNO instruction.
"\
I LLEGAL ADDRESS
MODIFICATIONS:
CI, SC, SCR
I LLEGAL REPEATS:
None
I NDl CATORS:
Zero
-
If C(AQ)
Negative
-
If C(AQ)O
Exponent
Overflow
-
I f exponent is > +127, then ON
Exponent
Underflow
-
If exponent of floating point result < - 128,
then ON
NOTES:
= 0,
= 1,
then ON; otherwise, OFF
then ON; otherwise, OFF
1. When indicator bit 32 = 1 and the hex permission flag = 1,
the floating-point alignment and normalization are
hexadecimal. Otherwise, the floating-point alignment and
normalization are binary. The hex permission flag is Mode
register bit 33.
2.
An Illegal Procedure fault occurs if illegal address
modification is used.
8-236
DZ5l-00
FNEG
FNEG
FNEG
Floating Negate
513 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
-C (EAQ) normal ized -> C(EAQ)
EXPLANATION:
This instruction changes the number in C(EAQ) to its
normalized negative (if C(AQ) ~ 0). The operation is
executed by first forming the two's complement of C(AQ), and
then normalizing C(EAQ).
Even if C(EAQ) is already normalized, an exponent overflow
can still occur, namely when C(E) = +127 and C(AQ) = -100 ••• 0
(the two's complement representation for the decimal value
-1.0).
(
The definition of normalization is located under the
description of the FHO instruction.
ILLEGAL ADDRESS
MODI FI CATIONS:
None
I LLEGAL REPEATS:
RPL
I NDI CATORS:
Zero
-
If C(AQ)
Negative
-
If
Exponent
Overflow
-
I f exponent is > +127, then ON
Exponent
Underflow
-
If exponent of floating point result < - 128,
then ON
NOTES:
= 0, then ON; otherwise, OFF
C(AQ}O = 1, then ON; otherwise, OFF
1. When indicator bit 32 = 1 and the hex permission flag = 1,
the floating-point alignment and normalization are
hexadecimal. Otherwise, the floating-point alignment and
normalization are binary. The hex permission flag is Mode
register bit 33.
2. An Illegal Procedure fault occurs if an illegal repeat is
used.
(
8-237
DZ5l-00
FNO
FNO
FNO
573 (0)
Floating Normalize
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(EAQ) normalized -> C(EAQ)
EXPLANATION:
The instruction normalizes the number in C(EAQ). If the
overflow indicator is ON, the number in EAQ is normalized one
place to the right: the sign bit 0 of C(AQ) is then inverted
to reconstitute the actual sign. The Overflow indicator is
set OFF.
A normalized floating binary number is defined as one whose
mantissa lies in the interval (0.5, 1.0) such that
0.5
~
IC(AQ)I
<
1.0
which, in turn, requires that C(AQ)O F C(AQ)l
A normalized floating hexadecimal number is defined as one
whose mantissa lies in the interval (0.0625,1.0) such that
0.0625
~
IC(AQ)I < 1.0
which, in turn, requires that
if C(AQ)O = 0, then C(AQ)1-4 F 0000, and
if C(AQ)O = 1, then C(AQ)1-4 F 1111
Normalization is performed by shifting C(AQ)1-7l to the left
(one place if binary, four places if hex) and reducing C(E)
by 1, repeatedly, until the conditions for C(AQ)O and C(AQ)l
or C(AQ)1-4 are met. Bits shifted out of AQ1 are lost.
If C(AQ)=O, then C(E) is set to -128 and the zero indicator
is set ON.
8-238
DZ51-00
(
FNO
FNO
This instruction can be used to correct overflows that occur
with fixed-point numbers:
1
8
16
TOV
1,IC
M
LDAQ
ADAQ
LDE
FNO
N
=71B25,DU
will normalize C(M-pair) + C(N-pair) correctly, whether or
not the addition caused an overflow (assuming overflow masked
or successful recovery from Overflow fault).
I LLEGAL ADDRESS
MODI FI CATIONS:
None
I LLEGAL REPEATS:
None
I NDI CATORS:
Zero
-
If C(AQ) = 0, then ON; otherwise, OFF
Negative
-
If C(AQ)O = 1, then ON; otherwise, OFF
Exponent
Overflow
-
If exponent is > +127, then ON
Exponent
Underflow
-
If exponent of floating point result < - 128,
then ON
Overflow
-
Set OFF
(
NOTE:
When indicator bit 32 = 1 and the hex permission flat = 1,
the floating-point alignment and normalization are
heXadecimal. Otherwise, the floating-point alignment and
normalization are binary. The hex permission flat is Mode
register bit 33.
(
8-239
DZ51-00
FRD
FRD
FRD
. Floating Round
471 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(EAQ) rounded to 28 mantissa bits and normalized -> C(EAQ)
EXPLANATION:
This instruction performs a true round of C(EAQ) to a
precision of 28 bits in C(AQ). The result is then normalized
and restored to the EAQ registers. A true round means that
the same rounding operation applied to a number of the same
magnitude and with an opposite sign would result in a sum of
the two rounded numbers of exactly zero.
The rounding operation is performed as follows:
a. A constant (all 1s) is added to bits 29-71 of the
mantissa.
b. If the number being rounded is positive, a carry is
inserted into the least significant bit position of the
adder.
c. If the number being rounded is negative, the carry is not
inserted.
d. Bits 28-71 of C(AQ) are replaced by zeros.
If the mantissa overflows upon rounding, it is shifted right
one place and a corresponding correction is made to the
exponent.
If the mantissa does not overflow and is nonzero upon
rounding, normalization is performed.
If the resultant mantissa is all zeros, the exponent is
forced to -128 and the zero indicator is set.
If the exponent resulting from the operation is greater than
+127, the exponent overflow indicator is set.
The definition of normalization is located under the
description of the FNO instruction.
('
I
''''--../
8-240
DZ5l-00
:
FRD
FRD
ILLEGAL ADDRESS
MODI FI CATIONS:
None
ILLEGAL REPEATS:
RPL
I NDI CATORS:
Zero
-
If C(AQ)
Negative
-
If
Exponent
Overflow
-
If exponent is > +127, then ON
NOTES:
= zero, then ON; otherwise, OFF
C(AQ)O = 1, then ON; otherwise, OFF
= 1 and the hex permission flag = 1,
the floating-point alignment and normalization are
hexadecimal. Otherwise, the floating-point alignment and
normalization are binary. The hex permission flat is Mode
register bit 33.
1. When indicator bit 32
2. An Illegal Proceduree fault occurs if an illegal repeat is
used.
(
8-241
DZSl-OO
FSB
FSB
FSB
Floating Subtract
575 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
[C(EAQ) - C{Y)]
EXPLANATION:
The two's complement of the subtrahend is first taken and the
smaller value is then right-shifted to equalize it. The
shifted portion is truncated and the addition is executed.
The definition of normalization is located under the
description of the FNO instruction.
normalized -> C(EAQ); C(Y) unchanged
ILLEGAL ADDRESS
MODI FI CATIONS:
CI, SC, SCR
I LLEGAL REPEATS:
None
I NDI CATORS:
Zero
-
If C{AQ}
Negative
-
If
Exponent
Overflow
-
If exponent is > +127, then ON
Exponent
Underflow
-
If exponent of floating point result < - 128,
then ON
carry
-
If a carry out of bit 0 of C(AQ) is generated,
then ON; otherwise, OFF
NOTES:
= 0, then ON; otherwise, OFF
C(AQ)O = 1, then ON; otherwise, OFF
,
)
1. When indicator bit 32 = 1 and the hex permission flat = 1,
the floating-point alignment and normalization are
hexadecimal. Otherwise, the floating-point alignment and
normalization are binary. The hex permission flat is Mode
register bit 33.
2. An Illegal Procedure fault occurs if illegal address
modification is used.
8-242
DZSI-00
FSBI
FSBI
FSBI
Floating Subtract Inverted
465 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
[C (Y) - C(EAQ ) ] normalized -> C(EAQ ); C(y) unchanged
EXPLANATION:
The two's complement of the subtrahend is first taken and the
smaller value is then right-shifted to equalize it. The
shifted portion is truncated and the addition is executed.
After addition, the sum is normalized and the 72 bits of the
mantissa are loaded into AQ.
The order of execution of the operation conforms to that of
the FSB instruction. Normalization is defined under FNO.
(
I LLEGAL ADDRESS
MODI FI CATIONS:
CI, SC, SCR
I LLEGAL REPEATS:
None
I NDI CATeRS:
Zero
-
If C(AQ)
Negative
-
If
Exponent
Overflow
-
I f exponent is > +127, then ON
Exponent
Underflow
carry
NOTE:
= 0, then ON; otherwise, OFF
C(AQ)O = 1, then ON; otherwise, OFF
If exponent of floating point result < - 128,
then ON
-
If a carry out of bit 0 of C(AQ) is generated,
then ON; otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modification is used.
(
8-243
DZ5l-00
FST
FST
PST
Floating Store
455 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(E) --> C(Y)O-7
C(A)O-27 --> C(Y)8-35
C(E), C(A) unchanged
I LLEGAL ADDRESS
MODI FI CAT! ONS:
DU, DL, CI, SC, SCR
I LLEXiAL REPEATS:
RPL
INDICATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
8-244
DZ5l-00
FSTR
FSTR
FSTR
Floating Store Rounded
470 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(EAQ) rounded and normalized -> C(Y); C(EAQ) unchanged
EXPLANATION:
This instruction performs a true round of C(EAQ) to a
precision of 28 bits in C(AQ). The result is then normalized
and stored in Y. A true round means that the same rounding
operation applied to a number of the same magnitude and
opposite sign would result in a sum of the two rounded
numbers of exactly zero.
Upon completion of the rounding and normalization, the
exponent and truncated mantissa are stored as follows:
a. Exponent in bits 0-7 of C(Y)
Bits 0-27 of mantissa in bits 8-35 of C(Y)
(
b. If the resultant mantissa bits 0-27 are all zero, the
exponent is forced to -128 and the zero indicator is set
(floating-point zero).
The rounding and normalization operation of this instruction
is identical with FRO.
The definition of normalization is located under the
description of the FNO instruction.
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPL
I NDI CATORS:
zero
-
If C(Y) = floating-point zero, then ON;
otherwise, OFF
Negative
-
If C(Y)8 = 1, then ON; otherwise, OFF
Exponent
Overflow
-
If exponent is > +127, then ON
(
8-245
DZ51-00
FSTR
FSTR
Exponent
Underflow
NOTES:
-
If exponent of floating point result < - 128,
then ON
1. When indicator bit 32 = 1 and hex permission flag = 1, the
floating-point alignment and normalization are
hexadecimal. Otherwise, the floating-point alignment and
normalization are binary. The hex permission flat is Mode
register bit 33.
2. An Illegal Procedure fault occurs if illegal address
modification or an ill~al repeat is used.
8-246
DZSl-OO
FSZN
FSZN
(
FSZN
Floating Set zero and Negative Indicators
from Storage
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
Test C(Y); C(Y) unchanged
I LLEGAL ADDRESS
MODIFICATIONS:
CI, SC, SCR
ILLEGAL REPEATS:
None
I NDI CATORS:
Zero
(
N~ative
(
(O)
I
I
Relationshi12
0
0
Mantissa C(Y)8-35 > 0
1
0
Mantissa C(Y)8-35
0
1
Mantissa C(Y)8-35 < 0
(bit 8 of C(Y)
NOTE:
430
=0
= l}
Illegal Procedure fault occurs if illegal address
modification is used.
An
-,
8-247
DZ5l-00
FTR
FTR
P'TR
Floating Truncate Fraction
474 (o)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(EAQ)
EXPLANATION:
This instruction truncates the fraction part of the
floating-point data of C(EAQ} to obtain an integer. The
result is normalized and stored into C(EAQ}. A proper
truncation to an integer is such that truncating the
fractional parts of two numbers with the same absolute and
different sign and adding the results produces O.
ADDRESS
MODIFICATIONS:
! LLEGAL
!
LlJX,;AL REPEATS:
INDICATORS:
NOTE:
fraction-truncated and normalized --> C(EAQ}
None. The address modification does not affect instruction
operations, but the modification is executed.
RPL
= 0, then ON; otherwise, OFF
C(AQ)O = 1, then ON; otherwise, OFF
zero
-
If C(AQ)
Negative
-
If
An Illegal Procedure fault occurs if an illegal repeat is
used.
8-248
DZSI-OO
(.
GLDD
GLDD
GLDD
FORMAT:
CODI NG FORMAT:
32n
Load Double to GXn
(1)
Single-word instruction format (see Figure 8-1)
1
8
16
GLDD
n,Y,R,AM
OPERATING MODES:
Only ES mode.
SUMMARY:
C(Y-pair) -> C(GXn-pair)
EXPLANATION:
C(Y-pair) is loaded into the GXn-pair specified by bits 24-26
of the op code. The contents of bits 24-26(n) of the op code
determines the load destination of the GXn-pair as follows:
n (octal)
GXn-pair
GXO,
GX2,
GX4,
GX6,
0
2
4
6
(
I LLEGAL ADDRESS
MODI FI CATIONS:
ILLEGAL REPEATS:
DU, DL, 0, SC,
GXl
GX3
GX5
GX7
SCR
The same GXn used as an address modification register in an
RPL.
ILLEGAL EXECUTES: Execution in NS mode.
INDICATORS :
NOTES:
Zero
-
If C(GXn-pair) = 0, then ON; otherwise, OFF
Negative
-
If C(GXn-pair) 0
= 1,
then ON; otherwise, OFF
1. An IPR fault occurs if illegal address modifications or
repeats are used or if this instruction is executed in the
NS mode.
2. An IPR fault occurs if N = 1, 3, 5, or, 7.
8-249
DZ5l-00
GLLS
GLLS
/
GXn Long Left Shift
GLLS
466 (1)
FORMAT:
Not Used
8
16
GLLS
Rl,J,R2
OPERATI NG MODES:
Only ES mode
SUMMARY:
Rl
= 0,
3
OP CODE
J
1
COOl NG FORMAT:
22233
1 1
1 1
000
2, 4, 6, AQ
C(RI-pair) is shifted left.
are filled with zeros.
Vacated positions in C(Rl-pair)
The number of bits to be shifted is given by the following:
EXPLANATION:
28 29
0
C(R2)
./
35
I
I
.
+
17.
11
J
I
///////////////////////////////////////
///////////////////////////////////////
///////////////////////////////////////
Shift Number
J is added to C(R2)29-35 and the low-order 7 bits of the sum
specify the shift number.
8-250
DZ51-00
GLLS
GLLS
If the R2 field is 0000, the addition of C(R2) and J is not
performed and the value of J specifies the shift number.
LlJlXiAL ADDRESS
MODIFICATIONS:
None.
ILLEGAL REPEATS:
RPT, RPD, RPL
I
The address modification is not executed.
ILLEXiAL EXECUTES: Execution in NS mode
I NDI CATORS :
Zero
-
Negative carry
NOTES:
-
= 0,
If C(Rl)
If C(Rl)O
= 1,
then ON: otherwise, OFF
then ON; otherwise, OFF
If a carry out of bit 0 of C(R1) is generated,
then ON; otherwise, OFF.
1. An IPR fault occurs if illegal repeats are executed or if
the instruction is executed in NS mode.
2. Refer to "Register to Register Instructions" in Section 7
for a description of the fields in the instruction word.
(
(
8-251
DZ5l-00
GLRL
GLRL
GXn Long Right Logic
GLRL
465 (1)
FORMAT:
o
0 0
OP CODE
J
1
COOl NG FORMAT:
8
16
GLRL
R1,J,R2
OPERATING MODES:
Only ES mode
SUMMARY:
Rl
= 0,
22233
78912
1 1
1 1
III MBZI
3
5
R21
2, 4, 6, AQ
C(RI-pair) is shifted right.
are filled with zeros.
vacated positions in C(RI-pair)
The number of bits to be shifted is given by the following:
EXPLANATION:
C{R2)
~IO_____________________________2_8~12_9
___________
3_5~1
+
J
//////////f////////////////////////////
///////////////////////////////////////
///////////////////////////////////////
Shift Number
J is added to C{R2}29-35 and the low-order 7 bits of the sum
specify the shift number.
8-252
DZ5l-00
(
GLRL
GLRL
If the R2 field is 0000, the addition of C(R2) and J is not
performed and the value of J specifies the shift number.
I LLEGAL ADDRESS
MODIFICATIONS:
None.
The address modification is not executed.
I LLEGAL REPEATS:
RPT, RPD, RPL
I LLEGAL EXECUTES: Execution in NS mode
I NDI CATORS :
zero
-
Negative NOTES:
= 0, then ON: otherwise, OFF
C(Rl)O = 1, then ON: otherwise, OFF
If C(Rl)
If
1. An IPR fault occurs if illegal repeats are executed or if
the instruction is executed in NS mode.
2. Refer to "Register to Register Instructions- in Section 7
for a description of the fields in the instruction word.
(
8-253
DZ51-00
GLRS
GLRS
464
(1)
22233
3
GXn Long Right Shift
GLRS
FORMAT:
a
0 0
1 1
1 1
OP CODE
J
CODING FORMAT:
1
8
GLRS
OPERATING MODES:
Only ES mode.
SUMMARY:
Rl
= 0,
16
Rl,J,R2
2, 4, 6, AQ
C(RI-pair) is shifted right. Vacated positions in
C(RI-pair) are filled with bits equal to bit 0 of
C(RI-pair) •
The number of bits to be shifted is given by the following:
EXPLANATION:
a
C(R2)
28 29
35
I
I
.
+
11
17.
J
I
///////////////////////////////////////
///////////////////////////////////////
///////////////////////////////////////
8-254
Shift Number
DZ5l-00
GLRS
GLRS
J is added to C(R2)29-35 and the low-order 7 bits of the sum
specify the shift number.
If the R2 field is 0000, the addition 0: C(R2) and J is not
performed and the value of J specifies the shift number.
I LLEX;AL ADDRESS
MODIFICATIONS:
None.
1 LLEXiAL REPEATS:
RPT, RPD, RPL
The address modification is not executed.
ILLEGAL EXECUTES: Execution in NS mode
I NDI CATORS:
Zero
-
Negative NOTES:
If C(R1) = 0, then ON; otherwise, OFF
If C(R1)0
= 1,
then ON; otherwise, OFF
1. An IPR fault occurs if illegal repeats are executed or if the
instruction is executed in NS mode.
2. Refer to "Register to Register Instructions" in Section 7_for
a description of the fields in the instruction word.
(
(
8-255
DZ51-00
GLS
GLS
462
GXn Left Shift
GLS
(1)
FORMAT:
o
0 0
1 1
1 1
J
CODING FORMAT:
1
16
GLS
Rl,J,R2
Only ES mode.
SUMMARY:
Rl
= 0,
3
OP CODE
8
OPERATING MODES:
22233
1, 2, 3, 4, 5, 6, 7, A, Q
C(Rl) is shifted left.
with zeros.
Vacated positions in C(Rl) are filled
The number of bits to be shifted is given by the following:
EXPLANATION:
28 29
0
C(R2)
/
35
I
I
.
+
17.
11
I
J
///////////////////////////////////////
///////////////////////////////////////
///////////////////////////////////////
Shift Number
is added to C(R2)29-35 and the low-order 7 bits of the sum
specify the shift number.
J
8-256
DZ5l-00
(
GLS
GLS
If the R2 field is 0000, the addition of C(R2) and J is not
performed and the value of J specifies the shift number.
I LLEGAL ADDRESS
MODIFICATIONS:
None.
The address modification is not executed.
I LLEGAL REPEATS:
RPT, RPD, RPL
ILLEGAL EXECUTES: Execution in NS mode
I NDI CATORS :
NOTES:
Zero
-
If C(Rl)
= 0,
thenONi otherwise, OFF
Negative -
If C(Rl)O = 1, then ONi otherwise, OFF
carry
If a carry out of bit 0 of C(Rl) is generated,
then ON; otherwise, OFF.
-
1. An IPR fault occurs if illegal repeats are executed or if
the instruction is executed in NS mode.
2. Refer to "Register to Register Instructions" in Section 7
for a description of the fields in the instruction word.
(
8-257
DZ5l-00
GRL
GRL
GXn Right Logic
GRL
FORMAT:
o
0 0
22233
1 1
1 1
OP CODE
J
CODI NG
FORMAT:
8
1
GRL
OPERATING MODES:
Only ES mode.
SUMMARY:
R1
= 0,
3
16
R:j.,J,R2
1, 2, 3, 4, 5, 6, 7, A, Q
C(R1) is shifted right.
with zeros.
Vacated positions in C(R1) are filled
The number of bits to be shifted is given by the following:
EXPLANATION:
28 29
C(R2)
35
~I
.IO____________________________ ____________
..11
~I
.
+
17.
I
J
///////////////////////////////////////
///////////////////////////////////////
///////////////////////////////////////
I
Shift Number
J is added to C(R2)29-35 and the low-order 7 bits of the sum
specify the shift number.
\
8-258
DZ5l-00
',,-
(
GRL
GRL
If the R2 field is 0000, the addition of C(R2) and J is not
performed and the value of J specifies the shift number.
I LLEGAL ADDRESS
MODIFICATIONS:
None.
ILLEGAL REPEATS:
RPT, RPD, RPL
The address modification is not executed.
ILLEGAL EXECUTES: Execution in NS mode
I NDI CATORS:
Zero
-
Negative NOTES:
= 0, then ON; otherwise, OFF
C(Rl)O = 1, then ON; otherwise, OFF
If C(Rl)
If
1. An IPR fault occurs if illegal repeats are executed or if
the instruction is executed in NS mode.
2. Refer to "Register to Register Instructions" in Section 7
for a description of the fields in the instruction word.
(
8-259
DZSI-00
GRS
GRS
GKn Right Shift
GRS
460 (1)
FORMAT:
o
0 0
1 1
Not Used
CODING FORMAT:
8
16
GRS
R1,J,R2
OPERATI NG MODES:
Only ES mode.
SUMMARY:
R1
= 0,
3
OP CODE
J
1
22233
1 1
1, 2, 3, 4, 5, 6, 7, A, Q
C(R1) is shifted right. Vacated positions in C(Rl) are
filled with bits equal to bit 0 of C(Rl) •.
The number of bits to be shifted is given by the following:
EXPLANATION:
28 29
C(R2)
~IO____________________________~I____________~I
..11
35
.
+
17.
I
J
///////////////////////////////////////
///////////////////////////////////////
//1111//////////1/////1/////////1//////
I
Shift Number
J is added to C(R2)29-35 and the low-order 7 bits of the sum
specify the shift number.
If the R2 field is 0000, the addition of C(R2) and J is not
performed and the value of J specifies the shift number.
8-260
DZ5l-00
GRS
GRS
ILLEGAL ADDRESS
MODIFICATIONS:
None.
ILLEGAL RE?EATS:
RPT, RPD, RPL
The
addr~ss
modification is not executed.
ILLEGAL EKECUTES: Execution in NS mode
I NDI CATORS:
Zero
-
Negative NOTES:
= 0, then ON; otherwise, OFF
C(Rl}O = 1, then ON; otherwise, OFF
If C(Rl)
If
1. An IPR fault occurs if illegal repeats are executed or if
the instruction is executed in NS mode.
2. Refer to Register to Register Instructions in Section 7
for a description of the fields in the instruction word.
(
8-261
DZSI-OO
GSTD
GSTD
FORMAT:
CODI NG FORMAT:
GSTD
Store Double from GXn
14n (0)
Single-word instruction format (see Figure 8-1)
8
16
GSTD
n,Y,R,AM
1
OPERATI NG MODES:
Only
SUMMARY:
C(GXn-pair) --> C(Y-pair)
EXPLANATION:
The content of the GXn-pair specified -by bits 24-26 of the op
code is stored in the memory location of Y-pair. The
GXn-pair whose contents are to be stored is specified as
follows:
ES
mode.
n (octal)
GXn-pair
o
GXO,
GX2,
GX4,
GX6,
2
4
6
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPL
GXl
GX3
GX5
GX7
\
ILLEGAL EXECUTES: Execution in NS mode.
I NDI CATeRS:
None affected.
NOTE:
An IPR fault occurs if illegal address modifications or
repeats are used or if this instruction is executed in the NS
mode.
'\
8-262
DZ5l-00
I
GTB
GTB
G'l'B
Gray-to-Binary Convert
774 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
NS mode only
SUMMARY:
C(A) is converted from Gray code to a 36-bit binary number
EXPLANATION:
This conversion is defined by the following algorithm in
which Rand S denote the contents of bit position i of the A
register before and after the conversion:
So
Sl
= RO
= (RO
where:
AND Si-l) OR (Ri AND Si-l)
= 1, ••• ,35.
i
Gray code is a method of transmitting numeric code
cyclically, one bit at a time, to eliminate transmission
errors and is defined as follows:
(
a. A positional binary notation for numbers in which any two
sequential numbers whose difference is 1 are represented
by expressions that are the same except in one place or
column, and in that place or column differ by only one
unit.
b. A type of cyclic unit-distance binary code evolved from
the 4-word, 2-bit unit distance code (00, 01, 11, 10)
according to the following rule:
To construct an (n+1)-bit reflected binary code from an
n-bit reflected binary code, write the n-bit code twice
in sequence, first in forward and then in reverse
sequence of code words. Prefix an extra bit to each
word, assigning the value a to the forward version and
the value 1 to the backward version of the n-bit code.
(
I LLEGAL ADDRESS
MODI FI CATIONS:
None
ILLEGAL REPEATS:
RPL
INDICATORS:
Zero
-
If C(A)
Negative
-
If
NOTE:
= 0, then ON; otherwise, OFF
C(A}O = 1, then ON; otherwise, OFF
Illegal Procedure fault occurs if an illegal repeat is
used.
An
8-263
DZ51-00
LARn
LARn
76n (1)
Load Address Register n
LARn
Single-word instruction format (see Figure 8-1)
FORMAT:
CODING FORMAT:
1
OPERATl NG MODES:
Any
SUMMARY:
NS Mode
8
16
LARn
LOCSYM, RM, AR
For n=0,1, ••• ,7 as determined by op code
C(Y)0-23 --> C(ARn); C(Y) unchanged
ES
Mode
For n=0,1, ••• ,7 as determined by op code
C(Y) -> C(ARn); C(Y) unchanged
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, Cl, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
EXAMPLE:
1
ADDR
8
16
32
LAR7
ADDR
load bits 0-23 of address into AR7
BOSC
512,,8,8
o0 1
o0 1
*CONTENTS OF J..R7 AFTER:
8-264
0 0 0 7 0 0 0 0 0 memory contents
0 007 0
DZ51-00
(
LAREG
LAREG
Load Address Registers
FORMAT:
CODIIJG FORMAT:
463 (1)
Single-word instruction format (see Figure 8-1)
1
OPERATI NG NODES:
Any
SUMMARY:
NS Node
8
16
LAREG
LOCSYM,R,AR
C(Y,Y+1, ••• ,Y+7)O-23 --> C(ARO,ARl, ••• ,AR7)
ES Node
C(Y,Y+l, ••• ,Y+7) --> C(ARO,AR1, ••• ,AR7)
EXPLANATION:
(
ILLEGAL ADDRESS
MODI FI CATIONS:
I
LLEGAL REPEATS:
The hardware assumes that the lower 3 bits of address Y = 000
and the 8 words beginning from the 8-word boundary are
accessed. No check is performed to determine whether the
lower 3 bits of Y = 000. Location Y must be forced to a
multiple of 8 by entering an 8 in column 7 of the statement
that defines Y, or by using the EIGHT pseudo-operation.
DU, DL, CI, SC, SCR
RPT, RPD, RPL
INDICATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-265
DZ5l-00
LAREG
LAREG
EXAMPLE:
1
8
16
32
LAREG
REGW
load ARO ••• AR7 from REGW ••• REGW+7
EIGHT
REGW
DEC
0,0,0,0,0,0,0,0
*
* Result is that all address Registers are
* cleared.
8-266
DZ51-00
LCA
LCA
(
Load Complement into A-Register
It
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
-C(Y) --> C(A); C(Y) unchanged
EXPLANATION:
This instruction changes the
while moving it from Y to A.
forming the two's complement
overflow condition exists if
335 (0)
number to its negative (if # 0)
The operation is executed by
of the string of 36 bits. An
C(Y) = 2**35.
I LLEGAL ADDRESS
MODI FI CATIONS:
None
I LLEGAL REPEATS:
None
INDICATORS:
Zero
-
If C(A)
Negative
-
If C(A)O = 1, then ON; otherwise, OFF
Overflow
-
I f range of A is exceeded, then ON
= 0,
8-267
then ON; otherwise, OFF
DZ51-00
LCAQ
LCAQ
LCAQ
Load Complement into AQ-Register
337 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
-C(Y-pair) --> (AQ)i C(Y-pair) unchanged
EXPLANATION:
This instruction changes the number to its negative (if ~ 0)
while moving it from Y-pair to AQ. The operation is executed
by forming the two's complement of the string of 72 bits. An
overflow condition exists if C(Y)-pair) = -2**71.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
None
I NDI CATORS:
Zero
-
If C(AQ)
Negative
-
If C(AQ)O
Overflow
-
I f range of AQ is exceeded, then ON
NOTE:
= 0,
= 1,
then ONi otherwise, OFF
then ONi otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modifications are used.
8-268
DZS1-00
LeON
LeON
LCON
Load Connect Table
016 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode
SUMMARY:
C(Y, Y+l, Y+2, Y+3
-->C(Connect Table)
C(Y+4, Y+5, Y+5, Y+7) -->(Secondary Connect Table)
EXPLANATION:
The connect table is located in the CPU scratch pad memory at
locations 74-77. The secondary connect table is at locations
0-3. (Refer to the description of CIOC in this section.)
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, and SCR
ILLEGAL REPEATS:
RPD, RPL, and RPT
I ND! CATORS:
None affected
NOTES:
1. An IPR fault occurs if this instruction is executed in
Slave or Master mode.
2.
IPR fault occurs if illegal address modification or an
illegal repeat is used.
An
3. The SCPR tag 07 instruction stores the connect table.
8-269
DZ51-00
LCPR
LCPR
LCPR
Load Central Processor Register
674 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master Mode
SUMMARY:
The operation has several forms depending upon the tag field:
C(Y)
-->C(CPU Register)
Operand
-->C(CPU Register)
C(A)
-->C(PTWAM)
Tag
C(Y) Bits
CPU Register
02
18, 21, 23-25 -->cache Mode Register
34-35
-->Lockup Fault Register
04
0-35
-->CPU Mode Register
11
0-17
-->Port Configuration Register
12
5-35
-->Real Address Trap Register
13
33-35
-->CPU Number Register
14
0-35
-->virtual Address Trap Register
Tag
Operand
03
0-35 = O••• O}
59-99= O••• O}
-->History Registers
07
0-35 = 1. •• l}
59-99= 1. •• l}
-->History Registers
CPU Register
(Refer to Section 4 for register format.)
8-270
DZ51-00
LCPR
LCPR
(
The following tag loads the contents of the PTWAM directory
from the A-register. The entry location is specified by the
Y address field in the instruction.
EXPLANATION:
Tag
Column
Row
17
Yll-16
Y17
C(A) Bits
28,29
Entry
PTWAM
DirectorY
This instruction provides the capability to load the Central Processor registers. The registers are selected by the
instruction tag field. The operation has several forms as
indicated under summary.
For LCPR Tag 02, cache is flushed when bit 18 is set to the
enable state and when a cache mode changes from disable to
enable. If an enable condition corresponding to bits 21, 24,
and 25 requires a cache flush, software must manipulate bit
18 to cause a cache flush.
For LCPR tag 17, if bit 29 is ON, C(AR) is added to the Y
field and the sum forms the entry select. The full virtual
address development is not used.
The real and virtual address trap values are also loaded into
processor scratch pad at locations 66,67.
I LLEGAL ADDRESS
MODIFICATIONS:
None.
I LLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS :
None
NOTES:
1. Attempted execution of LCPR in the Slave or Master mode
results in a Command fault.
2.
Tag field defines function.
An Illegal Procedure fault occurs if an illegal tag field
or an illegal repeat is used.
3. See the SCPR instruction for selecting the central
processor registers to be set.
(
8-271
DZ51-00
LeQ
LCQ
LeQ
336 (0)
Load Complement into Q-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
-C(Y) --> C(Q>; C(Y) unchanged
EXPLANATION:
This instruction changes the number to its negative value = -2**35.
F 0) while moving it from Y to Q.
ILLEGAL ADDRESS
MODI PI CATIONS:
None
I LLEGAL REPEATS:
None
INDICATORS:
Zero
-
Negative
- If
Overflow
-
EXAMPLE:
1
= 0, then ON: otherwise, OFF
Co = 1, then ON: otherwise, OFF
If C (Xn); C(Y) unchanged
ES Mode
For n=O,l •••• or 7 as determined by opcode
-C(y) -> (GXn): C(Y) unchanged
EXPLANATION:
(
I LLEGAL ADDRESS
This instruction changes the number to its negative value (if
# 0) while moving it from bits 0-17 of Y to Xn or from Y to
GXn. The operation is executed by forming the two's
complement of the string of 18 bits.
MODI FI CATIONS:
CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, or RPL of LOCO
INDICATORS:
Zero
-
If C(Xn/GXn)
Negative
-
I f C(Xn/GXn) 0 = 1, then ON; otherwise, OFF
Overflow
-
I f range of X!!/GX!! is exceeded, then ON
NOTES:
= 0,
then ON; otherwise, OFF
1. In the NS mode, if DL modificatiion is used, the hardware
executes with all zeros for data.
2.
Illegal Procedure fault occurs if illegal address
modification or illegal repeats are used.
An
8-273
DZ51-00
LDA
LDA
LDA
Load A-Register
235 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(Y) --> C(A); C(Y) unchanged
I LLEGAL ADDRESS
MODI FI CATIONS:·
None
I LLEGAL REPEATS:
None
I NDI CATeRS:
zero
-
If C(A)
Negative
-
If C(A)O = 1, then ON; otherwise, OFF
= 0,
8-274
then ON; otherwise, OFF
DZ51-00
(
LDAC
LDAC
LDAC
034 (0)
Load A-Register and Clear
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(Y) --> C(A): 0 ••• 0 --> C(Y)
EXPLANATION:
This instruction is used for a gating operation in multiple
CPU systems. Execution of the next instruction is delayed
until the cache-flush request applied to all CPUs has
completed.
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
None
INDICATORS:
Zero
-
If C(A)
Negative
-
If C(A)O
NOTE:
= 0,
= 1,
then ON: otherwise, OFF
then ON; otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modification is used.
(
8-275
DZ51-00
LDA.Q
LDAQ
LDAQ
Load AQ-Register
237 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(Y-pair) --> C(AQ): C(Y-pair) unchanged
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, 'SC, SCR
I LLEGAL REPEATS:
None
I NDI CATORS:
Zero
-
If C(AQ)
Negative
-
If
NOTE:
= 0, then ON; otherwise, OFF
C(AQ)O = 1, then ON; otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modification is used.
j
8-276
DZ51-00
(
LDAS
LDAS
LDAS
Load Argument Stack Register
770 (I)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode
SUMMARY:
C(Y-pair} --> C(ASR}; C(Y-pair) unchanged
EXPLANATION:
A descriptor is fetched from even/odd memory locations Y and
Y+l and the following checks are performed on the descriptor:
a.
Type
field T
= 1.
b. Base and bound are modulo 2 words (the three least
significant bits of base must be zeros; the three least
significant bits of bound must be ones if flag bit 27 is
l) •
If these conditions are met, the descriptor is loaded into
the argument stack register (ASR) and, in addition, the bound
is loaded into the High Water Mark Register (HWMR). During
ASR loading, bits 0-6 of the ASR bound field are forced to
zero by the processor instead of being loaded from the memory
operand. If flag bit 27 of the operand descriptor is zero,
the entire bound field is forced to zero, regardless of any
value the operand descriptor bound field may contain, and the
bound check is bypassed.
(
(Refer to the description of the PAS instruction for further
information concerning the HWMR.)
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, 0, sc, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
8-277
DZ5l-00
WAS
WAS
1. Any of the following conditions cause an IPR fault:
NOTES:
o Illegal address modifications
o Illegal repeats
o segment descriptor type field T is not 1
o If the base and bound limits of the operand descriptor
are not modulo 2 words.
o If flag bit 27 = 1 (bound valid) and the bound is not
modulo two words
2. If the processor is in Slave or Master mode, the execution
of ·this instruction causes an Command fault.
EXAMPLE:
1
8
ROUTINE
CALLING
POST
RDSPRG EQU
WP
WP
WDSA
WAS
WPS
TRA
*
*
16
32
TO LOAD REGISTERS - ASR, PSR, DSAR
TSX Z,RDSPRG
LOST PO, Z
*
*safestore frame access
PO,.SSR,DL
*change type
PO, .CTYP ,DL
*DSAR
.WDSAR"PO
•WASR, , PO
*ASR
•WPSR, , PO
*PSR
,Z
*OK
8-278
DZ51-00
LDCR
LDCR
LOCR
Load Complement Register from Register
431 (1)
FORMAT:
1 1
7 8
000
Not Used
CODING FORMAT:
1
I
8
16
LOCR
R1, ,R2
22233
78912
OP CODE
OPERATING MODES:
Executes in ES mode only.
SUMMARY:
Rl, R2 = 0, 1, 2, 3, 4, 5, 6, 7, A, Q
III HBZI
3
5
R2
I
-C(R2) --> C(Rl)
C(R2) unchanged
(
ILLEGAL ADDRESS
MODIFICATIONS:
None.
ILI&;AL REPEATS:
RPT, RPD, RPL
The address modification is not executed.
I LLEGAL EXECUTES: Execution in NS mode
I NDI CATORS:
NOTES:
Zero
-
If C(Rl) = 0, then ON; otherwise, OFF
Negative -
If C(Rl)O
Overflow -
I
= 1,
then ON; otherwise, OFF
f the range of Rl is exceeded, ON.
1. An IPR fault occurs if illegal repeats are executed or if
the instruction is executed in NS mode.
2. Refer to Register to Register Instructions in Section 7
for a description of the fields in the instruction word.
(
8-279
DZ51-00
LDDn
LDDn
/
LDI>!!
Load Descriptor Register n
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
EXPLANATION:
This set of eight instructions provides the capability of
loading a descriptor register (DRg) with a new descriptor or
modifying the descriptor currently contained in DRg. The
segment type referenced by the generated address determines
the function to be executed.
In this discussion, DRn represents the specified descriptor,
whereas, DRm represents the descriptor register indicated by
the y field that is used to load a new segment descriptor.
When the instruction word bit 29 = 1 and the descriptor
register specified by bits 0, 1, and 2 of the y field
includes a type T = 1 or 3 segment descriptor, the segment
descriptor is loaded into the DRn from the segment descriptor
segment specified by DRm.
When the instruction word bit 29 = 1 and the type for the
segment descriptor in DRm is T = 0, 2, 4, 6, 12, or 14, or
when the instruction word bit 29 = 0, a vector operation is
performed.
Descriptions of the two types of operations follow. An IPR
fault occurs when DRm includes a type T = 7 - 11, 13, or 15
segment descriptor.
Instruction Word Bit 29
= 1;
DRm Type T
=1
or 3
The segment descriptor from the segment descriptor segment
indicated by DRm is loaded into DRn. When the effective
address is generated, only R type modification and DU/DL
modification are permitted. The effective address is the
offset from the segment descriptor segment indicated by DRm.
The segment descriptor from the even/odd location indicated
by this address is loaded into DRn and the same checks are
performed as for any normal memory reference.
o A check is made to determine whether a segment is present
and whether read is permitted.
8-280
DZ51-00
LDDn
LDDn
(
o A bound check is made.
The housekeeping bit for that page must be ON because the
segment descriptor segment is referenced. If it is OFF, the
instruction execution is terminated and a Secur i ty Fault, Class
1 occurs. The housekeeping page access for access of the
segment descriptor is not dependent upon the CPU mode; it may
also be executed in Slave mode.
The ARg and
follows:
S~Dg
which correspond to the DRn are affected as
o ARg is set to zero.
o SEGIDg is set to be self-identifying, i.e., S
Instruction Word Bit 29
= 0;
ORrn Type
T
= 0,
= 0,
2, 4,
0
= 177n.
12, or 14
6,
The memory operand vector, consisting of one or two double-words
determines the operation to be performed by the instruction.
When this vector is obtained from memory, all address
modification is permitted except for DU, OL, SC, SCR, and CI.
1. VECTOR FORMAT
a. Vector for Standard Segment Descriptor, Super segment
Descriptor
o
1 2
9 0
o
SIZE
Y
V
FLAG
333
345
\\\ \
\
\\\ I
\\\ >2-Word
20
9
20
\\\
Vector
0
\\\ S
\\\ 2 10
/
>4-Word
\\\\\\\\\\\\\\\\\\\\\\\\\\
Vector
\\\\\\\\\\\\\\\\\\\\\\\\\\
BASE ADDER
Y+l
SUBSCRIPT
Y+2
20
Y+3
2
9
5
I
\\\\\\\\\\\\\\\\\\\\\\\\\\
\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
8-281
/
DZ51-00
LDDn
LDDn
The contents of bits 29-33 (the V field) determine the
function to be performed as follows. (XXX for bits
indicates that these bits are ignored.)
V = OOXXX Copy: 2-word vector
Copy (load) the selected segment descriptor into
DRn. SEGIDn is set to indicate the location from
which the segment descriptor was obtained~ ARn is
set to zero.
V
= OlXXX Normal Shrink: 2-word vector
Shrink the selected segment descriptor and load it
into DRn. SEDIDn is set to indicate DRn~ ARn is set
to zero.
V = 10000 Extended Shrink:
V =
4-word vector
10001 Special Extended Shrink:
4-word vector
Shrink the selected segment descriptor with the
4-word vector and load it into DRn. SE(rrDn is set
to indicate DRn~ ARn is set to zero. (Refer to
details below for difference between Extended Shrink
and special Extended Shrink.)
V
= llXXX Data Stack Shrink: 2-word vector
Use DSDR and DSAR to generate the data stack segment
descriptor~ load this segment descriptor into DRn.
DSAR is updated and ARn is set to zero. SE(rrD is
set to indicate DRn.
//----,,\
!
\...j
8-282
DZ5l-00
LDDn
LDDn
(
b. Vector for Extended Segment Descriptor
o
1 2
9 0
o
9
20
Y+l
V
FLAG
SIZE
Y
\\\\\\\\\\\\\\\\\\\\\\\ \\\
\\\\\\\\\\\\\\\\\\\\\\\ \\\ S
20\\\\\\\\\\\\\\\\\\\\\ \\\ 2 10
Y+2
BASE ADDER
Y+3
SUBSCRIPT
333
345
2
9
5
\\\ \
\\\
\\\
D
>4-Word
Vector
/
The contents of bits 29 - 33 determine the function to
be performed with the format illustrated above as
follows:
V = 10100 Normal Shrink with Type Change
Shrink the selected segment descriptor (T = 12 or l4)
and change to a Standard Segment Descriptor. S~Dn
is set to indicate DRn: ARn is set to zero.
V = 10101 Normal Shrink with No Type Change
Shrink the selected segment.descriptor (T = 12 or
14). SEGlDn is set to indicate DRn: ARn is set to
zero.
V = 10110 Extended Shrink with Type Change
Shrink the selected segment descriptor (T = 12 or
14), by using a subscript, and change to a Standard
Segment Descriptor. SEGIDn is set to indicate DRn:
ARn is set to zero.
V = 10111 Extended Shrink with No Type Change
Shrink the selected segment descriptor (T = 12 or 14)
by using a subscript. SEGIDn is set to indicate DRn;
ARn is set to zero.
(
8-283
DZ5l-00
LDDn
LDDn
v = 10010 Normal Base Shrink with No
Type
Change
Shrink the base of a selected segment descriptor (T
= 0, 2, 12, 14) and reduce the bound by as much as
the base shrinkage. The type remains unchanged,
SEGID is set to indicate DRn: ARn is set to zero.
v
= 10011
Extended Base Shrink with No
Type
Change
The same as the normal base shrink, except that the·
subscript is used. SEGIDn is set to indicate DR!!
and ARn is set to zero.
2. SHRI NK FOR STANDARD AND SUPER SEGMENT DESOOPTORS
a.
V =
00>00( Copy
(bits indicated by
X
ignored)
The Sand D fields of the vector indicate the
location of the segment descriptor to be loaded into
DRn. Definition of these two fields follows.
= 0:
D = 0000
When S
For
through 1757 (octal), the descriptor is
loaded from the parameter segment and D is used as
an index to the desired descriptor. The value in D
is the number of the descriptor to be loaded and can
be treated as a modulo 8 byte index; that is, D can
be converted to a byte address by appending three
zeros as the three least-significant bits.
"
D is bound checked against the PSR (parameter
Segment Register) bound field. If D > PSR bound, a
Bound fault occurs. IF D <= PSR bound, D is added
to the PSR base and is used as the segment
descriptor address. This address is used to obtain
the segment descriptor which is then loaded into
DRn.
./
8-284
DZ5l-00
"
LDDn
LDDn
For D = 1760 through 1777 (octal), the descriptors
referenced by S, D are contained in selected
registers and copied to the DRg.
D = 1760
D = 1761
D = 1762
D = 1763
D = 1764
D = 1765
D = 1766
D = 1767
D = 1770
D = 1771
D = 1772
D = 1773
D = 1774
D = 1775
D = 1776
D = 1777
(
Undefined, IPR fault
Change Descriptor Type Field in DRn·
Instruction segment Register (ISR)
Data Stack Descriptor Register (DSDR)
Safe Store Register (SSR)
Linkage Segment Register (LSR)
Argument Stack Register (ASR)
Parameter segment Register (PSR)
DRO, Descriptor Register 0
DRl, Descriptor Register 1
DR2, Descriptor Register 2
DR3, Descriptor Register 3
DR4, Descriptor Register 4
DRS, Descriptor Register 5
DR6, Descriptor Register 6
DR7, Descriptor Register 7
NOTE: When S = 0 with D = 1761 (octal) and the
processor is in the Privileged Master mode, if
the descriptor contained in DRg is type 1 or
3, the type is changed to 0 or 2,
respecti vely. SEGIDn is set to be
self-identifying. However, if the descriptor
is not type 1 or 3, no fault occurs and no
operation is performed.
When S = 0 with D = 1761, 1763, or 1764
(octal), a command fault occurs unless the CPU
is in the Privileged Master mode.
When
S = 2
The Dth descriptor of the current argument segment
is selected. A relative byte offset is formed by
extending the D field by 3 zeros. D is
bound-checked against the ASR bound field. If D >
the ASR bound, a bound fault occurs. 1 f D <= the
bound, D is added to the ASR base, and the segment
descriptor is obtained with this address and then
loaded into DRn.
(
8-285
DZ51-00
LDDn
LDDn
When 5 = 1 or 3
The Dg descriptor of the current linkage segment is
selected. A relative byte offset is formed by
extending the 0 field by three zeros. 0 is
bound-checked against the LSR bound field. If D >
bound. a Bound fault occurs. If 0 <= the bound , 0
is added to the LSR base, and the segment descriptor
is obtained with this address and then loaded into
ORne
For all values of 5, the loading of D~ affects the
gth address register (ARn) and the nth segment
identity register (SEGrrDg) as follows:
o ARg is set to zero.
o I f DRn was loaded from another OR or the
instruction segment register (ISR), the
associated segment identity content is
transferred to SEGrrDn; otherwise, SEGlDn is set
to the 5 and D value-contained in the vector.
When 5 = 0 and D = 1761 (octal), SEGlDn is set to
be self-identifying.
o If an IPR or an Bound fault occurs, DRn, ARg, and
5EGlDg are not changed.
b. V = OlXXX Normal Shrink
When bits 29 and 30 of the first word in the vector are
01, the specified segment descriptor is obtained, the
shrink operation is performed, and the descriptor is
then loaded into DRn a§ with copy. When S = 0 and D =
1761 (octal) in the Privileged Master mode, the segment
descriptors for type T = 1 or 3 are changed to T = 0 or
2, respectively. The shrink operation is then
performed.
In order to perform the shrink operation, the segment
descriptors indicated by 5 and D must be Standard or
Super Segment descriptors. An IPR fault occurs if T =
5 or 7 - 15. If a fault, such as a Bound fault, occurs
during the shrink operation, D~, SEGrrDn, and ARn are
not changed.
/'
8-286
DZ5l-00
..
"
(
LDDn
LDDn
Standard Seament Descriptors
with standard segment descriptors, the shrink operation
is performed as follows.
o The vector BASE ADDER and SIZE fields are the relative
values for the selected segment descriptor base and
bound fields. The following check is performed for
these values.
BASE ADDER + SI ZE <= bound
' ___Bound fault occurs with carry.
A Bound fault occurs when the sum of the BASE ADDER
and SIZE exceeds the bound or when carry occurs with
this addition. Flag bit 27 is not checked.
o When the check is terminated, a new base and bound are
generated.
New Base = old base
+
BASE ADDER
'_Bound fault occurs with carry.
New Bound
= size
The new base and bound are loaded into DRn.
o The vector flag field indicates the attributes given
to the segment. I t is combined with the flag field
of the selected segment descriptor to generate a new
flag field. The permission conditions for these new
flags are such that they are not increased from the
previous conditions (i.e., a bit-by-bit logical AND
operation of two flag fields takes place). A fault
does not occur even if the vector permission
conditions are greater than those for the segment
descriptors. The result produced by the combination
of these two flag fields is loaded into the DRg flag
field. As the type T = 2 or 3 segment descriptor
flag field are three bits in lengtli, the AND
operation is performed for these three bits and the
corresponding three bits from the vector.
The corresponding ARn is set to zero.
8-287
DZSl-OO
LDDn
LODn
SEGlDn is set to be self-identifying (ORn); for
example, when this instruction references OR3
(LDD#), S~03 is set as follows:
17738
Two Bits
Ten Bits
Super segment Descriptors
When shrink operation is performed for a super segment
descriptor, a standard segment descriptor is
generated. Type T = 4 super segment descriptor becomes
type T = 0 standard segment descriptor, and type T = 6
super segment descriptor becomes type T = 2 standard
segment descriptor.
The shrink operation is performed as follows:
o A check is performed to determine whether the
following expression is satisfied.
L
Location + (BASE ADDER + SIZE)
<=
bound
'_NO fault with carry
Bound fault occurs with carry
Flag bit 27 is not checked.
I f this check is passed, a new base and bound are
generated.
New base = base + (location + BASE ADDER)
' ___Bound fault occurs
with carry
___Bound fault occurs with carry
The processing is described in the diagram that
follows relative to the base and bound fields of the
selected descriptor.
8-288
DZ51-00
LDDn
LDDn
(
Location (selected segment Descriptor)
9.
35.
.16
+
·
·
··
•0
··
··
·
+
Base (Selected
segment
Descriotor)
··
9·.
.o
19
·
BASE ADDER (From Vector)
.0
·
·•
··
·•
··
35.
New Segment Descriptor Base
(
The new bound = SIZE. The new base and size field from
the vector are loaded in the base and bound field of
DRn·
The new flags field is fomed in the same manner as for
the standard descriptor. SEGrrDn is set as for the
standard descriptor shrink; ARn is zero-filled.
c. V = 10000 Extended Shrink
For extended shrink operations, the same conditions which
exists for normal shrink operations must be satisfied. If
a fault occurs during a shrink operation, DRn, ARn, and
SEG[Dn remain unchanged.
Standard Segment Descriptors
A 4-word vector subscript (SCPT) is used when the new
segment descriptor base and bound are generated.
(
8-289
DZ5l-00
LDDn
LDDn
o The following check is performed.
(BASE ADDER
+
SCPT)
(SI ZE - SCPT)
+
<=
bound
I_Bound fault occurs
with borrow
_Bound fault occurs with carry
_carry is ignored: a negative value is
permi t ted as the BASE ADDER (i. e., a
very large positive value).
o If this check is passed, a new base and bound are
generated.
New base
= base
+
(BASE ADDER + SCPT)
I_carry is ignored.
__Bound fault occurs with carry.
New bound
= SIZE
- SCPT
I_Bound fault occurs with borrow •.
The new base and bound are loaded into DRn.
As described in the discussion on normal shrink of a
standard segment descriptor, a new flag field is
generated. SEGIDn and ARn are set in the same way.
Super Segment Descriptors
The SCPT field is used as described in the discussion
on standard segment descriptors.
The following check is performed.
/
8-290
DZS1-00
,
LDDn
LDDn
Location
+
(BASE ADDER
+
ACPT)
+
(SIZE - SCPT)
<=
bound
I_Bound fault
occurs with
borrow.
__carry transferred to
the location field.
_carry is ignored.
_Bound fault occurs with carry.
If this check is passed, a new base and bound are
generated.
New Base = base + (location + (BASE ADDER +
SCPT»
I_carry is
ignored.
Bound fault occurs with
carry.
_Bound fault occurs with carry.
New bound
= SIZE
-
SCPT
' __Bound fault occurs with borrow.
The new base and bound are loaded into DRn.
o
new flag field is generated as with a standard
segment descriptor.
A
o DRg type T is set as follows.
1) If old T
= 4,
then new T = 0
2) If old T
= 6,
then new T = 2.
o The corresponding ARg is set to zero.
o
is set to be self-identifying (DRg). The
flag bit 27 of the selected segment descriptor is
not checked.
S~Dn
(
8-291
DZ5l-00
LDDn
LDDn
d. v = 10001 Special Extended Shrink
The differences between the special extended shrink and
the extended shrink (v = 10000> are as follows.
If the type T of the fetched segment descriptor is not
equal to 0, 1, 2, or 3, an IPR fault occurs. The SIZE
field (bits 0 - 17) of the vector is ignored, and the
following check is made.
BASE ADDER + SCPT <=
old bound
I_carry is ignored.
A
new base and bound are created as follows.
New base
= old
base -
(BASE ADDER + SCPT)
I_carry is ignored
Bound fault occurs if a borrow
-is generated.
New bound = old bound -
(BASE ADDER + SCPT)
I_carry is ignored
Bound fault occurs if a borrow
-is generated.
8-292
DZ5l-00
LDDn
LDDn
e. v
= llXXX
Data Stack Shrink
When bits 29 and 30 of the first word in the vector are
11, the instruction performs the data stack shrink
operation. The second word in the vector is ignored.
DSDR, OSAR, and the SIZE and flag field of the first
word in the vector are used to generate the new segment
descriptor.
o The value in the SIZE field of the vector is checked
to determine whether the area between the location
currently specified by the OSAR and the value
specified by the OSDR bound is equal or greater than
the SIZE field. The lower three bits of the vector
SIZE field are set to 1 to indicate an even-word
boundary (i.e., it is rounded to a double-word
expression as the OSAR always specifies an even-word
boundary.) DSAR + SIZE (rounded-up) <= DSDR bound
is then checked. I f the left portion of this
expression exceeds the OSDR bound, or if carry
occurs as a result of the addition to the left, a
Bound fault is generated. In this case ORB, ARB,
and SEGIOB are not changed.
o I f this check is passed, the OSAR content is added
to the OSDR base and a new base is generated. If
carry occurs, a bound fault occurs and the register
content is not changed.
o The new base (OSAR + OSDR base) is then loaded into
the ORn base field and the vector SIZE (before
rounding) is loaded into the ORn bound field.
o The new flag field values are generated from the
vector flag field and the DSDR flag field following
the same method as that described for normal shrink
of standard segment descriptors.
o The content of the DSDR Wand T fields are moved to
the ORn Wand T fields.
o The corresponding ARn is set to zero.
o SEGIDB is set to be self-identifying (ORn), as with
normal shrink.
8-293
OZSl-00
LDDn
LDDn
o The following value is loaded into DSAR.
New DSAR
= DSAR
+
SIZE (rounded-up)
+
1 (byte)
wraparound is not permitted for the DSAR, a bound
faul t occurs if carry occurs with the above
addition.
As
3. SHR1 NK FOR EXTENDED
SEGMENT DESCR1 PTORS
a. V = 10100 Normal Shrink with
Type
Change
The segment descriptor indicated by the S, D fields of
a vector is fetched in the same way as by the copy
function. I f the type T of the fetched segment
descriptor is not 12 or 14, an IPR fault occurs. For a
valid segment descriptor, the shrink operation is
performed as follows.
o The following check is made.
12 bits
BASE ADDER + SIZE <= bound (ll ••••••••• l)
I f the sum of the BASE ADDER and SIZE exceeds the
value obtained by extending the bound of the fetched
segment descriptor 12 "1" bits to the right, or if
the addition produces a carry from the most
significant bit, a bound fault occurs.
)
/
o After this check, a new base and bound are created.
New base
= old
base
+ BASE
ADDER
I_Bound fault occurs if carry
is generated.
New bound
o
A
= SIZE
new flag field is created in the same way as for
V = OlXXX normal shrink.
o A new type T is set as follows.
If old T
= 12,
then new T
= O.
If old T = 14, then new T = 2.
(' '\
\_--_/
8-294
DZ5l-00
LDDn
LDDn
o
S~Dn
and ARn are set in the same way as for normal
shrink.
b. v
= 10101
Normal Shrink with No Type Change
The segment descriptor indicated by the S, D fields of
a vector is obtained in the same way as for the copy
function. An IPR fault occurs if the type T of the
fetched segment descriptor is not 12 or 14. For a
valid descriptor, the shrink operation is performed as
follows.
12 bits
BASE ADDER + (SIZE OO ••••••• O+base lower-order 12 bits)
12 bits
<= bound 11 •••••••• 1
where the base denotes the value of the base field of
the fetched segment descriptor.
First, the sum of the value obtained by extending the
SIZE 12 bits to the right and the low-order 12 bits of
the base is obtained. I f this sum plus the BASE ADDER
exceeds the value obtained by extending the bound of
the descriptor 12 bits to the right, or if a carry is
generated by the addition, a Bound fault occurs.
o After the check, a new base and bound are created.
New base = old base + BASE ADDER
LBound fault occurs if carry
is generated.
New bound = SIZE
o SEG[Dn and ARn are set in the same way as for normal
shrink.
-
8-295
DZ51-00
LDDn
LDDn
c. V = 10110 Extended
S~rink
with Type Change
The segment descriptor indicated by the S, D fields of a
vector is obtained in the same way as for the copy
function. An 1PR fault occurs if the type T of the
fetched segment descriptor is not 12 or 14. For a valid
segment descriptor, the shrink operation is performed as
follows.
o The following checks are made on the BASE ADDER and
SIZE fields of the vector.
12 bits
(BASE ADDER + SCPT) + (SI ZE - SCPT) <= bound 1l. ..••• l
'_Bound fault occurs if '.
a borrow is generated.
Bound fault occurs if
-a carry is generated
_carry is ignored.
o After the check, a new base and bound are created.
New base = old base
+
(BASE AnDEER
+
SCPT)
'_carry is
ignored.
_Bound fault occurs if a carry
is generated.
New bound
= S1 ZE
- sePT
I_Bound fault occurs if a borrow
is generated.
o A new flag field is created in the same way as for a
normal shrink (v = OlXXX).
o A new type is set as follows.
If old T
= 12,
then new T = O.
IF old T
= 14,
then new T
= 2.
o SEGIDn and ARn are set in the same way as for a normal
shrink.
-
8-296
DZ51-00
)
/'
LDDr;
LDDn
d. v
= 10111
Extended Shrink with No Type Change
The segment descriptor indicated by the S, D fields of a
vector is obtained as for the copy function. An IPR
fault occurs if the type T of the fetched segment
descriptor is not 12 or 14. For a valid descriptor the
shrink operation is performed as follows.
o The following check is made on the BASE ADDER and
SIZE fields of the vector.
(BASE ADDER
+
+
SCPT)
I__carry is ignored.
12 bits
[(SIZE 00 •••••••• 0
+
base low-order 12 bits)-SCPT]
Bound fault occurs iL I
a borrow is generated.
I
__Bound fault occurs if a carry is generated.
<=
12 bits
bound 11 •••••••• 1
First, the sum of the value obtained by extending
SIZE 12 bits to the right and the low-order 12 bits
of the base of the fetched segment descriptor is
obtained. The difference between this sum and SCPT
is obtained. The difference is added to the sum of
the BASE ADDER and SCPT.
second, this sum is compared to the value obtained by
extending the bound of the fetched descriptor 12 bits
to the right. This operation is illustrated as
follows.
8-297
DZ5l-00
LDDn
LDDn
4b
1___
3...1.110:0(
B_AS_E_AD_D_ER
___
SIZE
0000
BOUND
11 •• 1
+
+
=
=
o
19 12b
0
35 .:r-0_ _ _ _ _ _ _ _....;3~5
BASE ADDER + SCPT
SIZE 00 ••• 0 +
I
Alcarry is
BASEl2b1
(- )
ignored
\
1
\
\
\
o
\
\
\
SCPT
=
35
(SIZE 00 ••• 0 + BASE12b
-SCPT
\
\
I f borrow, Bound fault occurs
\
\
\1
+
BASE ADDER + SCPT
31
=
(SIZE 00 ••• 0 + BASEl2b
---->
- SCPT + (BASE ADDER -+
SCPT)
BOUND
CHECK
If a carry is generated, Bound fault occurs.
o After the check, a new base and bound are created.
8-298
DZ51-00
(
LDDn
LDDn
New base = old base
+ (BASE ADDER + SCPT)
I_carry
is
ignored.
I_BoUnd fault occurs if a carry
is generated.
New bound
12 bits
11 •••••••• 1
- (old baselow-order 12 bits
+ BASE ADDERlow order 12 bits}
- SCPT]4-23
= [{SIZE
I_Bound fault occurs if a borrow
is generated.
The following illustrates locating the new bound.
8-299
DZ5l-00
LDDn
LDDn
_____~1*2
(-)
SCPT
=
2_3-"-:12:-4_~r
Ignored ___ >.....1O--:-_______
I
.
I f borrow I _ I .
Bound f a u l t .
occurs.
0
1
.\
I
. --r...l gnored
•
19
NEW BOUND
I
*1:
(Old base + BASE ADDR)low-order 12 bits
12 bits
*2:
SIZE 11 •••••••• 1 - (old base + BASE ADDER)low 12 bits
Flag fields are handled as a normal shrink.
o A new type T is the same as the original (old) type T.
o SEGIDn and ARn are set in the same way as for normal
shrink.
-
8-300
DZ51-00
(
LDDn
LDDn
e. v
= 10010
Normal Base Shrink with No
Type
Change
The segment descriptor indicated by the S, D fields-of a
vector is obtained in the same way as for the copy
function. An IPR fault occurs if the type T of the
fetched segment descriptor is not 0, 2, 12, -or 14.
The SIZE field of the vector is ignored in the
processing for a valid descriptor illustrated below.
o The following check is made on the BASE ADDER of the
vector.
16 bits
BASE ADDER <= 00 ••••••••• 0 bound
If the condition in the abgve check is not met, a
Bound fault occurs.
o After the check, a new base and bound are created as
follows.
New base
= old base
(
+ BASE
ADDER
'_Bound fault occurs
is generated.
16 bits
New bound
o
= [00 ••••••••••• 0 bound
- BASE ADDER]l6-35
new flag field is created the same as for a normal
shrink (v = OlXXX).
A
o A new type T is the same as the original (old) type
T.
o SEGJDn and ARn are set in the same way as for a
normal shrink.
For a segment descriptor with T = 12 or 14, the shrink
operation is performed as follows.
(
8-301
DZ51-00
LDOn
LDDn
o The following check is made on BASE ADDER of the
vector.
4 bits
12 bits
BASE ADDER+baselow-ord 12 bit~=OOOO bound 11 •••• 11
I_Bound fault occurs if a
carry is generated.
where the low-order 12 bits of base are the low-order
12-bits of the base field of the fetched segment
descriptor.
If the above condition is not met, a Bound fault occurs.
o After the check, a new base and bound are created as
follows.
New base = old base + BASE ADDER
1__ Bound fault occurs if a carry is
generated.
4 bits
12 bits
New bound = [(0000 old bound 11 ••••••• 1
- old base low-order 12 bits)
- BASE ADDER]4-23
o A new flag field is created in the same way as for a
normal shrink (v = OlXXX).
o The new type T is the same as the original (old) type
T.
o SEGIDn and ARn are set in the same way as for the
normal shrink.
f. v
= 10011
Extended Base Shrink with No Type Change
The segment descriptor indicated by the S, D fields of a
vector is located in the same way as for the copy
function. An IPR fault occurs if the type T of the
fetched descriptor is not 0, 2, 12, or 14.
/"
I
8-302
DZ51-00
'~
LDDn
LDDn
The SIZE field of the vector is ignored in the processing
described below.
For a segment descriptor with T = 0 or 2, the shrink
operation is performed as follows.
o The following check is made on the BASE ADDER and the
SCPT of the vector.
BASE ADDER
+
16 bits
SCPT<= 00 •••••••••• 0 bound
I_carry is ignored.
If these conditions are not met, a Bound fault occurs.
o After the check, a new base and bound are created as
follows.
New base
= old
base
+
(BASE ADDER
+ sePT)
I_carry is ignored.
Bound fault occurs if a carry
-is generated.
16 bits
New bound = 00 •••••••••• 0 bound - (BASE ADDER
SCPT)l6-35
+
carry is ignored._1
new flag field is created in the same way as for a
normal shrink (v = OlXXX).
A
The new type
T.
T
is the same as the original (old) type
SEGIDn and ARn are set in the same way as for normal
shrink.
For a segment descriptor with T = 12 or 14, the shrink
operation is performed as follows.
o The following check is made on the BASE ADDER and
SUBSCRI PT (SCPT) of the vector.
8-303
DZ51-00
LDDn
LDDn
(BASE ADDER
+
SCPT)
base low-order 12 bits
+
I_Bound fault occurs if a carry
is generated.
is ignored.
_Carry
4 bits
12 bits
<= 0000 bound 11 •••••••• 1
below. )
* (Referred to by NOTE
Where the base low-order 12 bits are the low-order 12
bits of the base field of the fetched segment
descriptor. If this condition is not met, a bound
fault occurs.
o After the check, a new base and bound are created as
follows.
New base
= old
base
+
(BASE ADDER
+
SCPT)
I_carry is ignored.
Bound fault occurs if a carry
-is generated.
4 bits
New bound
12 bits
old bound 11 •••••••• 1
old base low-order 12 bits)
- (BASE ADDER + SCPT)] 4-23
= [(0000
I_carry is ignored.
Bound fault occurs if a borrow is
-generated.
NOTE:
o
A
o
A
This Bound fault will never occur
if the starred (*) check condition
above has been met.
new flag field is created in the same way as for a
normal shrink (v = OlXXX).
new type T is the same as the original type T.
o SEGIDn and ARn are set in the same way as for a normal
shrink.
-
8-304
DZ51-00
LODn
LODn
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, IR, RI, IT, CI, SC, SCR (See NOTES for explanation.)
I LLEGAL
RPT, RPD, RPL
REPEATS:
INDICATORS:
None affected
NOTES:
1. Illegal Procedure (IPR) Faults can be caused by any of the
following conditions:
a. Modifications RI, IR, IT, DU, and DL when the DRm
segment descriptor type T = 1 or 3
b. Modifications DU, DL, CI, SC, SCR when the DRm segment
descriptor type T = 0, 2, 4, 6, 12, or 14
c. Illegal repeats
d. Vector fields S
= 0 and D = 1760
(octal)
e. If vector bits 29 and 30 are 01 or 10 and descriptor
obtained is type T=5 or 7-15
f. If a carry occurs when a T = 4 or 6 super descriptor is
loaded into DRn, and it is converted by hardware to a
standard segment descriptor. (Refer to description of
"Super Descriptors" in Section 3.>
g. When instruction word bit 29 = 1 and DRm segment
descriptor is type T = 5 or 7-11, 13, 15
2. Command Faults can be caused by any of the following
conditions:
a. If the CPU is not in Privileged Master mode, when S
and D = 1761, 1763, or 1764 (octal)
=0
b. If the CPU is not in Privileged Master mode, when bits
29 and 30 of the first word in the vector do not
specify data stack shrink (v = llXXX) and the vector S
and D fields specify DSDR
.
NOTE: When CPU is in the Privileged Master mode, the
segment descriptor from DSDR is used to execute
the specified operation. In this instance, DSDR
and DSAR remain unchanged.
8-305
DZ51-00
LDDn
LDDn
"r'-\
j
3. Bound Faults can be caused by any of the following
conditions:
a. When S = 0 and D > PSR bound
b. When S = 2 and D > ASR bound
c. When S = 1 or 3 and D >
l.SR
bound
d. When BASE ADDER + vector SIZE> DRn bound with shrink
operation for standard descriptors
e. When DRn location + vector BASE ADDER + vector SIZE >
DRn bound with shrink operation for super descriptors
f. When an illegal carry or borrow occurs while a base and
bound are generated, while a size check is performed,
or while a new DSAR is generated
g. In addition, general fault conditions also apply when
segment descriptors and page tables are accessed.
These conditions are noted in the individual vector
procedures descriptions.
4. Security Fault, Class 1 can be caused by the following
condition:
a. If the housekeeping bit of the page which includes the
selected descriptor is OFF when a descriptor is loaded
with the LDD instruction -
8-306
DZSl-OO
~
\,
\
LDDn
LDDn
EXAMPLES:
Direct Load:
1
8
16
32
LDDO
0,,7
Load ORO from location zero
of descriptor segment
framed by DR7 1770 -> SEGIDO
zeros --> ARO
8
16
32
LDDO
CPYDR7
Copy DR7 into DRO 1777-->SEGIDO
zeros-->ARO
Copy:
1
.
CRYDR7 CVEC
.DR7
Normal Shrink:
1
(
8
16
LDDO
BUFVEC
BUFFER BSS
BUFLEN EQU
BUFVEC VEC
(--
32
320
*-BUFFER
. I SR, BUFFER, BUFLEN , READ
.
8-307
DZ51-00
LDDR
LDDR
',,-
433 (1)
Load Double Register to Register Pair
LDDR
FORMAT:
o
1 1
7 B
0 0
I
Not Used
CODI NG
FORMAT:
1
222 3 3
7 B9 1 2
B
16
LDDR
Rl, ,R2
OPERATI NG MODES:
Executes in ES mode only
SUMMARY:
Rl, R2, = 0, 2, 4, 6, AQ
OP CODE
3
5
III I I
MHZ
R2
C(R2-pair) --> C(Rl-pair)
C(R2) unchanged
/
ILLEGAL ADDRESS
MODIFICATIONS:
None.
ILLEGAL REPEATS:
RPT, RPD, RPL
The address modification is not executed.
ILLEGAL EXECUTES: Execution in NS mode
I NDI CATORS:
zero
-
Negative NOTES:
If C(Rl-pair)
If C(Rl-pair)O
= 0,
= 1,
then ON: otherwise, OFF
then ON; otherwise, OFF
1. An IPR fault occurs if illegal repeats are executed or if
the instruction is executed in NS mode.
2. Refer to Register to Register Instructions in Section 7
for a description of the fields in the instruction word.
B-30B
DZ51-00
LDDSA
LDDSA
Load Data Stack Address Register
LDDSA
170 (1)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master Mode
SUMMARY:
Bits 0-16 of C(Y) -> C(DSAR)
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
'None affected
NOTES:
1. The DSAR is a 17-bit register that holds an even-word
address.
2.
IPR fault occurs if illegal address modifications and
illegal repeats are executed.
An
3. If the processor is not in the Privileged Master mode, the
execution of this instruction causes a Command fault.
EXAMPLE:
1
8
16
LDP
P,PSH,SD.PSH,DL
P,PSH,.CTYP,DL
PH.ADS"P.PSH
TEMP, ,P.DSR
TEMP, ,P.DSR
LDP
LDDSD
STZ
LDDSA
(
8-309
DZ51-00
LDDSD
LDDSD
LDDSD
Load Data Stack Descriptor Register
571 (1)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master Mode
SUMMARY:
C(Y-pair) --> C(DSDR)
EXPLANATION:
The double-word memory operand is fetched from even and odd
memory locations Y and Y+l. The operand must be in standard
descriptor format with a type field of T = O. The lower
three bits of the base of this segment descriptor must be
zero (i.e., the descriptor in the DSDR specifies the segment
beginning from the boundary of an even word). The flag bit
22 must be zero.
When these conditions are met, the obtained descriptor is
loaded into the DSDR. If one or more of the above conditions
are not met, an IPR fault occurs and the DSDR content remains
unchanged.
The lower three bits of the descriptor bound field should all
be ones to ensure that the area specified with the DSDR is a
multiple of word pairs. Hardware does not check these three
bits.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1. Any of the following conditions causes an IPR fault (the
DSDR remains unchanged):
a. Illegal address modification
b. Illegal repeats
c. If type field T is not equal to O.
d. If the base is not modulo 2 words.
e. If the descriptor flag bit 22 is not = O.
8-310
DZ5l-00
(
LDDSD
LDDSD
-
2. If the processor is Master or Slave mode, the execution of
this instruction causes a Command fault.
EXAMPLE:
8
16
EKP
LDP
LDD
LDP
STA
LDD
LDAS
LDPS
LDDSD
LDDSA
LDSS
PO,SD.PSH,DL
PO ,PH. USL, ,PO
PO , •crY? , DL
UL.ISR+1, ,PO
S.ISR+1,QU,P4
P1,S.ISR,QU,P3 P1 = sub-dispatch I SR
S.APR, ,P4
load special registers
S.APR, ,P4
S.DSR, ,P4
SBDH
.KLSDS,PN*,P.KL load SSR for sub-disp by processor number
STX6
SXL3
LDD
LCQ
ANSQ
.KLPRG,7,P.KL
.KLPRG,7,P.KL
P2,S.ENT,QU,P3
=0204020,DL
.QFST,3,P6
ADLA
(
32
1
set processor flags for sub-disp
P2 = entry descriptor to climb with
clear fault status bits
(
8-311
DZ51-00
WE
WE
WE
Load Exponent Register
411 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(Y)0-7 -> C(E);
I LLEGAL ADDRESS
MODI FI CATl ONS:
CI, SC, SCR
I LLEGAL REPEATS:
None
I NDI CATORS:
Zero
-
setOFF
Negative
-
setOFF
NOTE:
C(Y)
unchanged
An Illegal Procedure fault occurs if illegal address
modification is used.
8-312
DZ5l-00
(
LDEAn
LDEAn
Load Extended Address n
(
61n (1)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(Y) -->
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
I NDI CA'TORS :
None affected
NOTES:
1. This set of eight instructions enables the loading of the
location field of a descriptor register (DRn) from memory
address Y. The DR!! must contain a super descriptor (type
field T must be 4 or 6): otherwise, an IPR fault occurs.
location field of Descriptor Register (DR!!)
2. If T = 4 or 6, if a carry occurs when creating the base (DRn
base+location field) or, if a borrow occurs when creating the
bound (DRn bound-location field), an IPR fault occurs.
3. Any of the following conditions causes an IPR fault:
a. Illegal address modifications·
b. Illegal repeats
c. If descriptor type field T of DRn is not 4 or 6
8-313
DZ5l-00
EXAMPLE:
1
MSCN7
8
NULL
EAX2
CMPX2
TZE
LDA
ANA
AOS
CMPA
TZE
16
1,2
4,DU
ESCN
• KLMSZ, , KLS
=0777777,DL
ADDRS
ADDRS
ESCN
LDEA
LDA
RMS,SUPAD
ASA
TRA
SUPAD
1K*4,DL
MSCN2
32
is defective memory table full?
yes
no
isolate real memory size
advance page number
is this page the last?
yes
loading location field of super descriptor
adjust byte
next page scan
8-314
DZ51-00
(
LDI
LDI
LDI
Load I ndicator Register
634 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(Y)18-32 --> C(IR); C(Y) unchanged
EXPLANATION:
The relation between bit positions of C(Y) and the indicators
is as follows:
Bit Position
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33-35
Indicator (or Mask)
Zero
Negative
carry
Overflow
Exponent overflow
Exponent underflow
Overflow mask
Tally runout
Parity error
Parity mask
Master mode
Truncation
Multiword instruction interrupt
Reserved for exponent underflow mask
Hexadecimal mode
Undefined
ILLEGAL ADDRESS
MODI FI CATIONS:
CI, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
Master mode (IR bit 28) not affected
All others: If corresponding bit in C(Y)
OFF
= 1,
then ON; otherwise,
(
8-315
DZ5l-00
LDI
LDI
NOTES:
1. The Tally Runout indicator reflects bit 25 of C(Y)
regardless of what address modification is performed on
the LDI instruction for tally operations.
2. Master Mode cannot be changed by the LO! instruct ion.
Overflow Fault does not occur when the overflow
indicator, exponent overflow indicator, or exponent
underflow indicator is set ON via the LDI instruction,
even if the overflow mask indicator is OFF.
3.
An
4.
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is uSed.
5. Hexadecimal mode is controlled by bit 32 of the IR and
bit 33 of the mode register.
6. The parity mask, bit 27, masks
errors and internal CPU parity
Slave mode, only SCU interface
The test mode register control
internal parity errors.
8-316
SCU interface parity
errors in Master mode. In
parity errors are masked.
can be used to mask
DZ5l-00
(
LDO
LDO
LDO
Load Option Register
FORMAT:
Single-word instruction format (see Figure 8-1).
OPERATING MODES:
Any.
EXPLANATION:
When the CPU is in Privileged Master mode:
172
(1)
See Explanation below.
Data Stack Clear Flag (DSCF) is loaded from C(Y)18.
DSCF controls memory clear operation when data stack
shrink is executed with the CLIMB instruction.
o = do
1
not clear
= clear
safe Store Bypass Flag (SSBF) is loaded from C(Y)19.
SSBF controls ICLIMB safe store bypass.
o = bypass safe store
= perform safe store
1
If the CPU is in Master or Slave mode, DSCF and SSBF are
unchanged.
I LLEGAL ADDRESS
MODI FI CATIONS:
CI,
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1. Although this instruction is legal in all processor modes,
SC, SCR
the setting of the two flag bits occurs only in Privileged
Master mode.
2. An IPR fault occurs if illegal address modification or
illegal repeats are executed.3l9
8-317
DZ5l-00
LOO
LOO
EXAMPLE:
16
32
1
8
*
LOAD SAFE STORE REGISTER AND OPTION REGISTER; Privileged Master
SLVSS
LOSS
LOO
cross
TRA
MSFRM
CPNOSS
LOSS
LOO
=0200000,DL
=0400000,DL
mode only
SSBF ON
DSCF ON
8-318
DZ51-00
(
LDPn
LDPn
Load Pointer Register
n
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
EXPLANATION:
This set of eight instructions is similar to the LODg
instruction with the copy option; however, no vector is
required and ARn may be loaded with a value other than all
zeros.
Processing for these instructions differs between
modes.
NS
NS
and
ES
Mode
If DU or DL modifications are not used
C(Y)0-23 --> C(ARn)
C(descriptor specified by S, D) --> C(DRn)
or the DRn type field
is changed.
C(Y)24-35
interpreted as S,D field
If DU modification is used
YO-17 -->
C(ARn)0-17
00 ••• 0 --> C(ARn)18-23
00 ••• 0
interpreted as S,D field
If DL modification is used
00 ••• 0 -->
C(ARn)0-17
YO-5 -->
C(ARn)18-23
Y6-l7
interpreted as S,D field
8-319
DZ51-00
LDPn
LDPn
ES Mode
If DU or DL modifications are not used
C(Y)0-35 --> C(ARn)
C(descriptor specified by S, D) --> C{DRn)
or the DRn type field
is changed.
C{Y+l)O-ll
interpreted as S,D field
C(Y+l)12-35
ignored
If DU modification is used
Y16-33
-->
C{ARn)0-17
00 ••• 0
-->
C{ARn)18-35
00 ••• 0
interpreted as S,D field
If DL modification is used
YO-2l
-->
.C{AR)14-35
00 ••• 0
-->
C(ARn)0-13
Y22-33
interpreted as Sand D
In both the NS and ES modes, interpretation of the S and D
fields and the corresponding operation is the same as that
for the LDDn instruction vector Sand D fields specified by
the copy function. The descriptor is loaded into DRn.
(When S = 0 and D = 1761, the type in DRn is changed; the
value described with the LDDn instruction copy function is
loaded into SEGIDn.)
The Sand D fields of the pointer locate the descriptor to be
loaded into DRn as follows:
8-320
DZ51-00
LDPn
LDPn
(
When S = 0:
For D = 0000 through 1757 (octal) and D <= PSR bound, the
descriptor is loaded from the ~\Tameter segment and D is used
as an index to the desired descriptor. The value in D is the
number of the descriptor to be loaded and can be treated as a
modulo 8 index; that is, D can be converted to a byte address
by appending three zeros as the three least significant bits. For D = 1760 through 1777 (octal), the descriptors referenced
by S, D are contained in selected registers and copied to
DRg.
D = 1760
D = 1761
D = 1762
D = 1763
D = 1764
D = 1765
D = 1766
D = 1767
D = 1770
D = 1771
D = 1772
D = 1773
D = 1774
D = 1775
D = 1776
D = 1777
Undefined, IPR fault
Change Descriptor Type Field in DRn
Instruction Segment Register (ISR)
Data Stack Descriptor Register (DSDR)
safe Store Register (SSR)
Linkage Segment Register (LSR)
Argument Stack Register (ASR)
Parameter Segment Register (PSR)
DRO, Descriptor Register 0
DR1, Descriptor Register 1
DR2, Descriptor Register 2
DR3, Descriptor Register 3
DR4, Descriptor Register 4
DRS, Descriptor Register 5
DR6, Descriptor Register 6
DR7, Descriptor Register 7
NOTE: when D = 1761 (octal) and the processor is in
Privileged Master mode, if the descriptor contained
in DRg is type 1 or 3, the type is changed to 0 or
2, respectively; however, if the descriptor is not
type 1 or 3, no change is made and no fault occurs.
When S
= 2:
The Dg descriptor of the current argument segment is
selected. A relative byte offset is formed by extending the
D field by 3 zeros.
(
..
8-321
DZ51-00
LDPn
LDPn
When S = 1 or 3:
The Dn descriptor of the current linkage segment is selected.
A relative byte offset is formed by extending the D field by
3 zeros.
For all values of S, the loading of DRg affects the nth
address register (ARn) and the nth segment identity register
(S~Dn) as follows:
a. ARn is set to zero.
b. If DRn was loaded from another DR or the instruction
segment register (lSR), the associated segment identity
content is transferred to S~Dn; otherwise, s~Dn is set
to the S and D value contained in the poin~er.
c. If an IPR or Bound fault occurs, DRg, ARn, and SEGIDn are
not changed.
The segment descriptor (SD) compare funtionality increases
the averrage speed of this instruction in both NS and ES
modes. A comparison is made between the SD number of the
instruction and the SD number in the SEGIDn register. If a
match occurs, the memory access for the descriptor and the
descriptor register load is bypassed, because the match
indicates that the descriptor register is already correctly
loaded. The address register level load is independent of a
match.
The compare is not done if SD - 00,1760 to 00,1777.
A compare flag is provided for each descriptor register. All
flags are set OFF, disallowing compares by instructions which
can store descriptors, change characteristics of virtual
spac, or change mode to slave. No provision is made for
broadcasting this action to other processors within these
instructions.
8-322
DZ5l-00
\, /
LDPn
LDPn
(
The instructions which set these flags off follow.
ICLIMB
LTRAS
LTRAD
OCLIMB
LDAS
LDPS
LDWS
LPDBR
PAS
STDn if DRm type
= 1,3
RET
TSS
Flag n is set ON by execution of LDPn.
In addition, the instruction, SPCF, turns the flags OFF.
The compare function is enabled or disabled under control of
the CPU mode registers bits 24 and 25. Bit 24 enables
compares in Slave mode: bit 25 enables compare in Master and
Privileged Master modes. (Two controls are provided to allow
the GODS 8 software flexibility in removing code which would
cause erroneous SD number matches.)
I LLEGAL ADDRESS
MODI FI CATIONS:
CI, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
None affected
NOTES:
1.
An
2.
An
IPR fault occurs if bit 29=1 and the operand segment is
not type T = 0, 2, 4, or 6.
Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
3. A Command fault occurs as with the LDDn instruction copy
function.
4. Other faults occur as with the LDDn copy function.
(8-323
DZ51-00
LOPn
LDPn
EXAMPLE:
1
8
'l'PUTEX SZN
TZE
32
TRAPTR
test for trap in use
no trap enabled
trapping -- get location (ensuring that
address register has offset and
descriptor is type 0) of cell to be
monitored in AR via P6: mask it for
desired pattern, and compare it with bad
value
LOP6
TRAPOK
TRAPTR
SAR6
TRAPCT
LDP6
TRAPCT
LOA
ANA
0, ,P6
TRAPMK
TRAPVL
CMPA
TZE
TRAPOK LOP6
*
16
TRA
GOTCHA
SD.SSA,DL
0,4
trap has sprung
reload P.SSA (here if no/OK trap)
TRA monitor if monitor active
exit
8-324
DZ51-00
(
LDPR
LDPR
LDPR
Load Positive Register to Register
432 (1)
FORMAT:
1 1
000
Not Used
CODI NG FORMAT:
1
22233
3
OP CODE
8
16
LDPR
Rl, ,R2
OPERATING MODES:
Executes only in ES mode.
SUMMARY:
Rl, R2 : 0, 1, 2, 3, 4, 5, 6, 7, A, Q
IC(R2)1 --> C(Rl)
C(R2) unchanged
ILLEGAL ADDRESS
MODIFICATIONS:
None.
ILLEGAL REPEATS:
RPT, RPD, RPL
The address modification is not executed.
ILLEGAL EXECUTES: Execution in NS mode
I NDI CATORS:
Zero
-
Negative NOTES:
If C(Rl)
= 0,
then ON; otherwise, OFF
Set to OFF
l. An IPR fault occurs if illegal repeats are executed or if
the instruction is executed in NS mode.
2. Refer to Register to Register Instructions in Section 7
for a description of the fields in the instruction word.
(
8-325
DZ51-00
LDPS
LDPS
LDPS
Load Parameter Segment Register
771 (l)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode
SUMMARY:
C('!l-pair} --> C(PSR): C(Y-pair) unchanged
EXPLANATION:
The descriptor is fetched from even/odd memory locations Y
and Y+l. The hardware performs the following checks on the
descriptor.
o
Type
field must have a value of T
= 1.
o Base must be 0 modulo B bytes.
o If flag bit 27
bytes.
=1
(bound valid), bound must be 7 modulo 8
If these conditions are met, the descriptor is loaded into
PSR. During PSR load, PSR bound field bits 0-6 are forced to
zero by the hardware rather than being loaded from the memory
operand. Also, if flag bit 27 of the operand descriptor is
equal to zero, the entire bound field of the PSR is forced to
zero, independent of any value the operand descriptor bound
field may contain, and the bound check is bypassed.
This instruction is identical with LDAS, except that it loads
the parameter segment register (PSR) instead of the argument
stack register (ASR).
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
8-326
DZS1-00
)
LDPS
LDPS
1. Any of the following conditions cause an IPR fault:
NOTES:
a. Illegal. address modifications
b. Illegal repeats
c. Descriptor type field T is not 1
d. If the base and bound limits of the operand descriptor
are not modulo 2 words (only when flag bit 27 = 1).
2. If the processor is in Master or Slave mode, the execution
of this instruction causes a Command fault.
EXAMPLE:
1
8
16
32
LDP
P.SSR, .SSR,DL
LDP
LDAS
LDPS
P.SSR, .CTYP ,DL
(Load descriptor of fault
frame in safe store stack)
(Change to type 0>
(Restore ASR from safe store)
(Restore PSR from safe store)
.WASR, ,P.SSR
.WPSR, ,P.SSR
(
8-327
DZ5l-00
LDQ
LDQ
LDQ
Load Q-Register
236 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(Y) --> C(Q); C(Y) unchanged
I LLEGAL ADDRESS
MODI FI CATIONS:
None
ILLEGAL REPEATS:
None
I NDI CATORS:
Zero
-
If C C(Rl)
(
C(R2) unchanged
I LLEGAL ADDRESS
MODIFICATIONS:
None.
I LLEGAL REPEATS:
RPT, RPD RPL
The address modification is not executed.
I
ILLEGAL EXECUTES: Execution in NS mode
I NDI CATORS:
Zero
-
Negative NOTES:
If C(Rl) = 0, .then ON; otherwise, OFF
If C(Rl)O
= 1,
then ON: otherwise, OFF
1. An IPR fault occurs if illegal repeats are executed or if
the instruction is executed in NS mode.
2. Refer to Register to Register Instructions in Section 7
for a description of the fields in the instruction word.
(
8-329
DZ5l-00
LOSS
LOSS
LDSS
773
Load safe Store Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERA'l'1 NG MODES:
Pr i vileged Master Mode
SUMMARY:
C(Y)O-35
-->
(1)
C(SSR)O-35
C(Y+l)O-32 --> C(SSR)36-68
000
EXPLANATION:
-->
C(SSR)69-7l
The operand is fetched from even and odd memory locations Y
and Y+l. The operand must be a standard descriptor with type
T = 1 or 3. The following checks are performed on the
descriptor:
a. For T = 1, flag bits 20, 21, 27, and 28
25 and 26 = O.
b. For T
= 3,
flag bits 20 and 21
= 1 and
flag bits
= 1.
If these conditions are met, the descriptor is loaded into
the safe store register (SSR). The lower three bits of the
SSR base are forcibly set to zero. If one or more of the
above conditions is not satisfied, the instruction is
terminated and an IPR fault is generated. In this case, the
SSR remains unchanged.
Each successful execution of LOSS initializes the 2-bit stack
control register (SCR) as follows. (The SCR is associated
with the SSR and contains a code that denotes the size of the
last frame on the stack.)
If C(Y+l)34 35 = 00/01/11, then 11 --> C(SCR)
(size'of save store frame = 64 words)
If C(Y+1)34 35 = 10, then 10 --> C(SCR)
(size'of save store frame = 80 words)
(Refer to safe Store Stack in discussion of ClJMB
instruction. )
8-330
DZ5l-00
,7
I
LDSS
LDSS
(
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL,
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1. Any of the following conditions causes an IPR fault:
a, SC, SCR
a. Illegal address modification
b. Illegal repeats
c. If T is not equal to 1 nor 3.
d. If either the flag bit or the base checks fail.
2. If the processor is not in Master or Slave mode, the
execution of this instruction causes a Command fault.
EXAMPLE:
1
8
16
FANY
STZ
LDXO
.SVFLT, ,P.SSA
.ST2CS, ,P.SSA
TZE
NEPRA
STSS
LDAQ
ADLAQ
STAQ
.STEMP+6"P.SSA
. LDSS
LDP
LDXO
STXO
TRA
32
Not type 2 critical
SSRXX
.STEMP+6"P.SSA backup safe store to prior frame
.STEMP+6"P.SSA
.STEMP+6"P.SSA
PO,.SSR,DL
=0377001,DU
.WREGS, ,PO
RETOUT
(
8-331
DZ5l-00
LOT
LOT
LOT
Load Timer Register
637 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode
SUMMARY:
C(Y)0-26 -> C(TR); C(Y) unchanged
I LL!X;AL ADDRESS
MODI FI CATI ONS :
Cl, SC, SCR
ILL!X;AL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1. The use of this instruction in the Master or Slave mode
causes a Command fault.
2. An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
/\
8-332
DZ51-00
(
LOWS
LOWS
LDWS
772
Load Working.Space Registers
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode
SUMMARY:
When EA17 (NS Mode) or EA33 (ES Mode)
C(Y)O-8
-->
C(WSRO)
C(Y)9-17
-->
C(WSR1)
(1)
=0
C(Y)18-26 --> C(WSR2)
C(Y)27-35 --> C(WSR3)
When EA17 (NS Mode) or EA33 (ES Mode)
(
C(Y)O-8
-->
C(WSR4)
C(Y)9-17
-->
C(WSR5)
=1
C(Y)18-26 --> C(WSR6)
C(Y)27-35 --> C(WSR7)
EXPLANATION:
The contents of memory location Y replace the contents of
working space registers (WSRs) 0, 1, 2, and 3 or WSR 4, 5, 6,
and 7 based on the value of bit 17 (NS mode) or 33 (ES mode)
of the effective address.
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
(
8-333
DZ51-00
LDWS
LDWS
1.
NOTES:
\.
IPR fault occurs if illegal address modification or
illegal repeats are used.
An
2. If the processor is not in the Privileged Master mode, the
execution of this instruction causes a COmmand fault.
3. If the LDWS instruction is used to change the contents of
the WSR that is currently the WSR for the instruction
segment, then the LOWS must be followed immediately by a
TRA *+1 to ensure that the new contents of the WSR take
effect immediately.
EXAMPLE:
32
1
8
16
WS03
WS47
EVEN
VFD
VFD.
9/001, 9/001, 9/013, 9/27
9/45, 9/45, 9/63, 9/510
LDWS
LDWS
WS03
WS47
Load WSR 0-3 from EVEN word
Load WSR 4-7 from Odd word
8-334
DZ51-00
\
(
LDXn
LDXn
Load Index Register n from Upper
Single-word instruction format (see Figure 8-1)
FORMAT:
OPERATI NG
22n (O)
MODES:
SUMMARY:
Any
NS
Mode
For n
= 0,1, ••• ,7
as determined by op code
C(Y}0-17 --> C(Xn): C(Y) unchanged
ES Mode
For n
= 0,1, ••• ,7
as determined by op code
C(Y)0-35 --> C(GXn): C(Y) unchanged
ILLEGAL ADDRESS
MODI FI CATIONS:
CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD,
I NDI CATORS:
Zero
-
If C(Xn/GXn)
Negative
-
If C(Xn/GXn)o = 1, then ON: otherwise, OFF
NOTES:
or
RPL of LDXO
= 0,
then ON: otherwise, OFF
1. DL modification executes with all zeros for data in the NS
mode.
2.
Illegal Procedure fault occurs if illegal address
modification or illegal repeats are used.
An
(
8-335
DZSI-OO
LIMR
LIMR
LIMR
FORMAT:
553
Load I nterrupt Mask Register
(0)
single-word instruction format (see Figure 8-1)
OPERATING MODES: Privileged Master mode
SUMMARY:
C(A)O-7 -->
Port interrupt level masks: 1 enables
interrrupts
C(A)8
-->
All mask, conditionally as described in
Explanation below: 1 enables interrupts
C(A)9
-->
Port connect mask: 1 enables connects
C(A)lO
-->
All mask load control
C(A), C(Y) --> Unchanged
EXPLANATION:
The SCU is selected by the control SCU bit.
configuration register in Section 4.)
(Refer to SCU
The operation of the All mask control is as follows:
C(A)lO
C(A)8
x
1
1 --> All mask
o
o
o
All mask is unchanged
1
The effective address
o -->
(y)
All mask
is not used by the LIMR instruction.
Orily masks associated with the issuing port are loaded.
The all mask bit is a single. mask, associated with all ports.
All masks are set to enable interrupts and connects at
initialization.
Processor behavior on the next and all other instructions
following the execution of LIMR is consistent with the mask
setting indicated by the LIMR.
8-336
DZ51-00
LIMR
LIMR
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, C1, SC, SCR
ILLEGAL REPEATS: RPT, RPD, RPL
I NDI CATORS:
None affected
NOTES:
1. Prior to executing this instruction, the SCU must be
"selected" by using the LCPR instruction to set or reset
bi t 22 in the CPU mode register.
2. The use of this instruction in other than Privileged Master
mode causes an IPR fault.
3.
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
(
8-337
,
-----~-~.-----
....
~
--
-.-.-----.-~------
.. --..,
~--
.. ---
-
-._-._.' ,_...
~--
DZ51-00
LLR
LLR
777 (0)
Long Left Rotate
LLR
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
EXPLANATION:
Rotate C(AQ) left by the number of positions indicated by
bits 11-17 of Y (y modulo 128) (NS mode) or Y27-33 (ES
mode). Enter each bit leaving bit position 0 of AQ in bit
position 71 of AQ.
I LLEGAL ADDRESS
MODIFICATIONS:
I LLEGAL
REPEATS:
INDICATORS:
NOTES:
DU, DL, CI, SC, SCR
RPL
= 0, then ON: otherwise, OFF
C(AQ)O = 1, then ON: otherwise, OFF
Zero
-
If C(AQ)
Negative
-
If
1. The rotate count comes from the value of Y.
"right-rotate" n bits, use LLR 72-n.
To
2. An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
\~
8-338
DZ5l-00
LLS
LLS
(
LLS
737 (0)
Long Left Shift
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
Shift C(AQ) left by the number of positions indicated by bits
11-17 of Y (y modulo 128) (NS mode) or Y27-33 (ES mode): fill
vacated positions with zeros.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPL
I NDI CATORS:
Zero
-
If C(A}
Negative
-
If C(A)O
carry
-
If bit a of C(AQ) changes during the shift,
then ON: otherwise OFF.
NOTES:
= 0,
= 1,
then ON: otherwise, OFF
then ON: otherwise, OFF
1. The shift count in the instruction must be a decimal
number.
2. An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
(
8-339
DZ51-00
LPDBR
LPDBR
LPDBR
Load Page Table Directory Base Register
171 (1»
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode
SUMMARY:
C(Y)0-18 --> C(PDBR)
EXPLANATION:
The contents of bits 0-18 of Yare loaded into the 19-bit
PDBR. Associative memory (AM) is cleared, if it is enabled,
and C(Y) is unchanged.
(Mod 512)
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1. An IPR fault occurs when illegal address modifications or
illegal repeats are used.
/
2. If the processor is in Master or Slave mode, the execution
of this instruction causes a Command fault.
8-340
DZ5l-00
(
LPL
LPL
LPL
FORMAT:
COOl NG FORMAT:
467
Load Pointers and Lengths
Single-word instruction format (see Figure 8-1)
1
8
LPL
16
LOCSYM, R,AM
OPERATI NG MODES:
Any
SUMMARY:
C(Y}, C(Y+l}, ••• ,C(Y+5) --> C(P&L)
C(Y+6), C(Y+7)
EXPLANATION:
(
(1)
-->
C(LOR}
Pointer and length storage (P&L) is used by hardware to store
control information to continue execution after an
interruptible multiword instruction has been interrupted
during execution. The low operand register (LOR) is a
register used with quadruple-precision instructions.
The location of Y must be a multiple of 8. A fault does not
occur when the lower 3 bits of Yare not 000. Forpurposes
of execution, the hardware forces these bits to 000 (modulo
8) •
In the LPL instruction, the contents of the eight words
beginning at location Yare stored into scratch pad memory.
(Refer to SPL for a description of the contents of these
words. )
(
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, RI, IR, IT
I LLEGAL REPEATS:
RPT, RPD, RPL
I ND! CATORS:
None affected
NOTES:
1. An I llegal Procedure fault occurs if illegal address
modifications or illegal repeats are used. The contents
of the pointer and lengths storage is changed when the
illegal execution of RPT, RPD, RPL, XEC, XED, and indirect
modification IT occurs.
2. The pointer and length storage is used to recover from an
interrupt or a Missing Page fault. Because the content
depends upon hardware, the software must not change the
contents of the pointer and lengths storage.
8-341
DZ51-00
LREG
LREG
!.REG
Load Registers
073
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
ES
0-17
18-35
0-17
18-35
0-17
18-35
0-17
18-35
0-35
0-35
0-7
of
of
of
of
of
of
of
of
of
of
of
C(Y)
C(Y)
C(Y+l)
C(Y+l)
C(Y+2)
C(Y+2)
C(Y+3)
C(Y+3)
C(Y+4)
C(Y+5)
C(Y+6)
-->
-->
-->
-->
-->
-->
-->
-->
-->
-->
-->
(O)J
C(XO)
C(Xl)
C(X2)
C(X3)
C(X4)
C(X5)
C(X6)
C(X7)
C{A)
C(Q)
C(E)
Mode
C(Y)
--> C(XO)
C(Y+I) --> C(XI)
C(Y+2) --> C(X2)
C(Y+3) --> C(X3)
C(Y+4) --> C(X4}
C(Y+5) --> C(X5)
C(Y+6) --> C(X6)
C(Y+7) --> C(X7)
C(Y+8) --> C(A)
C{Y+9) --> C(Q)
Bits 0-7 of C(Y+IO) --> C(E)
EXPLANATION:
Memory (location y) is accessed on a double-word boundary by
setting the lower three bits of the effective address Y to
zero, adding a base address to it, and truncating the
least-significant word address bit.
8-342
DZ51-00
LREG
LREG
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL,
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
Q,
SC, SCR
modifications or illegal repeats are used.
(
(
8-343
DZ5l-00
LRL
LRL
LRL
Long Right Logical Shift
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
EXPLANATI ON:
NS Mode
773 (0)
Shift C(AQ) right by the number of positions indicated by
bits 11-17 of Y (y modulo 128): fill vacated positions with
zeros.
ES
Mode
Shift C(AQ) right by the number of positions indicated by
bits 27-33 of Y (y modulo 128); fill vacated positions with
zeros.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPL
I NDI CATORS:
Zero
-
If C(AQ)
Negative
-
If
NOTES:
= 0, then ON: otherwise, OFF
C(AQ)O = 1, then ON; otherwise, OFF
1. The shift count in the instruction must be a decimal
number.
2.
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-344
DZ51-00
LRMB
LRMB
(
Load Reserve.Memory Base
(
712 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode
SUMMARY:
C(Y)
EXPLANATION:
This instruction places the contents of the effective address
into the Reserve Memory Base Register (RMBR). The RMBR is
located in the PATROL half of processor scratch pad memory at
location 73. Initialization firmware sets RMBR to zero.
GODS software sets the RMBR to zero when the processor is
released as required by the CAMP instruction. (Refer to RMBR
in Section 4.)
-->
C(RMBR)
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, a, SC, SCR
ILLEGAL REPEATS:
RPD, RPL, and RPT
INDICATORS:
None affected
NOTES:
1.
An IPR fault occurs if execution is attempted in Master or
Slave mode.
2.
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
(
8-345
DZ51-00
LRS
LRS
~~__~__~____Lo__n_g_R_i_9_h_t_S_h_i_ft____~__________________~__7_3_3__(0_>__•
FORMAT: .
Single-word instruction format (see Figure 8-1>
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
Shift C(AQ) right by the number of positions indicated by
bits 11-17 of Y (y modulo 128): fill vacated positions with
the content of bit 0 of C(AQ).
ES
Mode
Shift C(AQ) right by the number of positions indicated by
bits 27-35 of Y (y modulo 128): fill vacated positions with
the content of bit 0 of (AQ).
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPL
INDICATORS:
Zero
-
If C(AQ)
Negative
-
If C(AQ)O
NOTES:
= 0,
= 1,
then ON: otherwise, OFF
then ONi otherwise, OFF
1. The shift count in the instruction must be a decimal
number.
2.
Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
An
8-346
DZ51-00
(
LXLn
LKLn
Load Index Register g from Lower
72n (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
For n
= 0,1, ••• ,7
as determined by op code
C(Y)l8-35 --> C(Xg): C(Y) unchanged
ES Mode
For n
= 0,1 •••• ,7
as determined by op code
C(Y)18-35 with sign extended --> C(GXg): C(Y) unchanged
Bit 18 of C(Y) is extended to bits 0-17 and loaded into GXn.
C
ILLEGAL ADDRESS
MODIFICATIONS:
CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, or RPL of LKLO·
I ND! CATORS:
Zero
-
If C(Xg/GXn}
Negative
-
If C(Xg/GXn}0
NOTES:
= 0,
= 1,
then ON: otherwise, OFF
then ON: otherwise, OFF
1. DU modification executes with all zeros for data.
2.
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
(
8-347
DZ5l-00
MLR
MLR
\""
Move Alphanumeric Left to Right
MLR
100 (1)
FORMAT:
a a
a
8 9
FILL
a
a
1
1
1
a
a
IT I I
1 1
7 8
MF2
Op
I
0 a
2 3
Code
2
8
100(1}
I
1 1 2 2 222
7 8 o 1 234
Y1
CN1 TAl 0
AR#
3
2
3
5
N1
R1
a aa
1122222
7 B 0 1 234
Y2
CN2 TA2
CODI NG FORMAT:
NFl
Yl
023
AR#
I I
3
3
3
2
5
N2
\----
0
Y2
R2
The MLR instruction is coded as follows:
1
B
16
(NFl), (MF2) ,FILL, T
LOCSYM,CN,N,AM
LOCSYM,CN,N,AM
(Refer to Section 7 under Mu1tiword Instructions for description
of Mu1tiword Modification Field.)
OPERATI NG MODES:
Any
SUMMARY:
C(string 1) --> C(string 2)
8-348
DZ51-00
MLR
MLR
EXPLANATION:
Starting at location yel, the alphanumeric characters of data
type TAl of string 1 replace, from left to right, the
alphanumeric characters of data typeTA2 of string 2 that
starts at location YC2. If TAl and TA2 differ, each
character has high-order truncation or zero-fill, as
appropriate.
If Ll is greater than L2, the least significant (Ll-L2)
characters are not moved and the Truncation indicator is
set. If Ll is less than L2, bits 0-8, 3-8, or 5-8 of the
FILL character (depending on TA2) are inserted as the least
significant (L2-Ll) characters. If Ll is less than L2, bit 0
of C(FILL) = 1, TAl = 01, and TA2 = 10 (6-4 move); the
hardware looks for a 6-bit overpunched sign. If a negative
overpunch sign is found, a negative sign (octal 15) is
inserted as the last FILL character. If a negative overpunch
sign is not found, a positive sign (octal 14) is inserted as
the last FI LL character.
L2 = 0 does not necessarily mean that the instruction
functions as a no-op, because the Truncation indicator may be
affected.
The contents of string 1 remain unchanged except in cases of
string overlap.
MFI and MF2 (Multiword Modification Fields) are 7-bit fields
specifying address modifications to be performed on the
operand descriptors. They are broken into four subfields
represented as (bitl, bit2, bit3, Index-register) in the
instruction. They may be coded as follows:
If bitl = 0
bitl = 1
No address register is used
The address register is defined in the
operand descriptor address field (e.g.,
ADSC9 ,,, AR )
If bit2
==
0
Operand length is specified in the N
field of the operand descriptor (e.g.,
ADSC6 , ,24, )
bit2
=1
Operand length is contained in the
register specified by the code in the N
field of the operand descriptor (e.g.,
ADSC4 , ,X4, )
(
8-349
DZ5l-00
MLR
MLR
If bit3
=0
The operand descriptor follows the
instruction word in its memory location.
bit3
=1
The operand descriptor location
following the instruction in memory
points to the operand descriptor.
Index-register
The address modification register is
defined as 0, 1, 2, 3, 4, 5, 6, 7, AU,
QU, A, or Q.
See "Multiword Modification Field" and "Alphanumeric Operand
Descriptors" in Section 5, and "Alphanumeric Instructions"
under "Multiword Instructions" in Section 7 for additional
information.
For speed, the MLR and MRL instructions operate 6n four
double-words at a time. This mode of operation does not
cause a problem when moving between either nonoverlapped
strings or between any normal combination of any length
overlapped strings. (In the latter case, software must
choose between MLR and MRL to ensure that the overlapped
sending characters are moved before they are moved into
because they are also receiving characters.) This mode of
operation can cause a problem when MLR or MRL is used to
replicate a pattern across a string.
For example, one procedure used to replicate a pattern of K
characters across a string of L characters is to
o store the K characters into character positions 1 through
K of the string
o move" a string of length L - K and starting position 1 to
the same length string starting at position K + 1. In
this way, the last L - K sending characters are created
"on the fly".
The mode of operating on four double-words at a time does not
allow this creation "on the fly" for K less than four
double-words of characters (when K starts on a word boundary
or is less than eight double-words of characters and does not
start on a word boundary).
8-350
DZ5l-00
MLR
MLR
(
To replicate a pattern between two characters and four
double-words of characters, additional instructions must be
used to initialize the first four double-words -of the string
of L characters. To replicate a I-character pattern (most
common application), a simple move with fill from a
zero-length string can be used. (See examples below.)
ILLEGAL ADDRFSS
MODIFICATIONS:
DU, DL for MFI and NF2
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
Truncation - If Ll is > L2, then ON; otherwise, OFF
NOTE:
An Illegal Procedure fault occurs if DU or DL modification is
used for NFl or MF2 or if illegal repeats are used. A
Truncation fault occurs if the Truncation indicator is set
and the truncation fault enable (T) bit is a 1. A fault does
not occur even when L2 = 0. L2 = does not mean NOP; the
truncation indicator may be affected.
°
EXAMPLES:
1
FLDI
FLD2
8
16
32
MLR
ADSC6
ADSC6
USE
,,20
FLDl, ,12
FLD2,4,l4
CONST.
2, ABCDEFGHI JKL
3
move with blank fill
sending descriptor
receiving descriptor
memory contents
, ,400
FLDl,3,9
FLD2,6,lO
CONST.
move with sign captured
sending descriptor
receiving descriptor
BCI
BSS
USE
MLR
ADSC6
ADSC4
USE
xxxxABCDEFGHIJ~
(Result)
FLOI
BCl
2,~l2345678R
FLD2
BSS
USE
2
xxxxxxl23456789-
1
8
16
32
MLR
ADSC9
ADSC9
(1,O,O,),(",QU) move 24 words from P.IOQ to A+QU bytes.
0,0,24,P.IOQ
A, ,24
(Result)
(
8-351
DZ51-00
MME
MME
NNE
Master Mode Entry Fault
001 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERA'l'I NG MODES:
Any
EXPLANATION:
This instruction generates a MNE fault which causes the
processor to switch to Privileged Master mode and to execute
an Inward CLIMB using the entry descriptor from the word pair
in memory locations 32 and 33 (octal).
If the safe store bypass flag in the option register = 1, a
safe store frame is generated. The size of this safestore
frame is determined by the type of the entry descriptor. A
code of 00010 in bits 12-16 of word 5 in the safe store frame
indicates the occurrence of the MME fault.
The wired-in CLIMB instruction functions as though the second
word of the CLIMB instruction had the following
characteristics:
E= 0
C18
C19
C22-23
S, D
No parameters
Do not load XO
No effect. Turn Master mode indicator
ON.
= 0 Inward CLI MB
No effect
The entry descriptor specifies a descriptor to be obtained
from the linkage segment for loading into the instruction
segment register (ISR). The entry descriptor also specifies
the value to be loaded into the instruction counter (ID).
The processor is placed in Privileged Master mode for the
execution of the wired-in CLIMB. Upon completion of the
CLI MB the processor remains in Privileged Master mode if
flag bit 26 of the new ISR = 1 (privileged); otherwise, the
processor changes to Master mode.
I
8-352
DZSl-OO
MNE
MME
I LLEGAL ADDRESS
MODIFICATIONS:
Not executed. CI, SC, SCR generate an illegal condition that
causes the history registers to be locked if mode register
bit 31 = 1. No IPR fault occurs because the MME fault has
higher priority.
I LLEGAL REPEATS:
RPT I RPD I RPL
I NDI CATeRS:
Master mode - ON
NOTE:
An
IPR fault occurs if an illegal repeat is used.
(
8-353
DZ51-00
MP2D
MP2D
Multiply Using Two Decimal Operands
MP2D
206 (l)
FORMAT:
0 0
0 1
001 1
890 1
1 1
Iploo--+H
0
0
I
MF2
1 1
0
2
7 8
Yl
CNl
Code
206(1)
2 2
o1
222
789
5
II
222
234
TNl Sl
3
MFl
2 3
9 0
SFl
I
3
5
Nl
Yl
AR#
o
o
Op
7 8
1 1
0
2
7 8
Y2
AR#
CODING FORMAT:
CN2
2 2
0 1
222
234
TN2 S2
2 3
3
9 0
SF2
5
N2
Y2
The MP2D instruction is coded as follows:
1
8
16
MP2D
NDSCn
NDSCn
(MF1),(MF2),RD,P,T
LOCSYM,CN,N,S,SF,AM
LOCSYM,CN,N,S,SF,AM
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
8-354
DZ51-00
(
MP2D
MP2D
OPERATI NG MODES:
Any
SUMMARY:
C(string 2) *·C(string 1) --> C(string 2)
EXPLANATION:
Same as for MP3D except that the product is stored using YC2,
TN2, S2 and, if S2 indicates a scaled format, SF2.
I LLl!X7AL ADDRESS
MODIFICATIONS:
DU, DL for NFl and MF2
I LLEGAL REPEATS:
RPT L RPD, RPL
I NDI CATORS:
Zero
-
If result equals zero, then ON; otherwise, OFF
Negative
-
If result is negative, then ON; otherwise, OFF
Truncation -
If, in the preparation of the final result,
one or more least significant digits (zero or
nonzero) are lost and rounding is not
specified, then ON. Otherwise (i.e., no least
significant digits lost or rounding is
specified), OFF
Exponent
Overflow
-
Exponent
Underflow
Overflow
NOTES:
If exponent of floating-point result is > 127,
then ON; otherwise, unchanged
If exponent of floating-point result is <
-128, then ON; otherwise, unchanged
-
If data is lost in most significant positions
then ON; otherwise, unchanged
1. A Truncation fault occurs if the Truncation indicator is
set and the truncation fault enable (T) bit is a 1.
2.
An
Illegal Procedure fault OCcurs if:
a. Illegal address modification is specified for NFl or
MF2, or illegal repeats are used.
b.
character (least four bits) other than 0000 - 1001
is detected where digits are defined, or any character
(least four bits) other than 1010 - 1111 is detected
where the sign is defined by the numeric descriptor.
Any
(
8-355
DZ51-00
MP2D
MP2D
\"
The values for the number of characters (Nl or N2) of
the data descriptors are not large enough to hold the
number of characters required for the specified sign
and/or exponent, plu~ at least one digit.
3. If an illegal digit or sign is detected, part or all of
the receive field may be changed before the IPR fault
occurs.
EXAMPLES:
1
FLDl
FLD2
8
16
, ,1,1
MP2D
NDSC9 FLDl,0,4,2,-3
NDSC4 . FLD2, 0,8,1,-2
CONST.
USE
4A2+
EDEC
8P+l234567
EDEC
USE
rounding and plus sign options
multiplier operand descriptor
multiplicand operand descriptor
memory contents
o 02+
+1234567
+0002469 (Product)
indicators on? none
,,1
FLD1,0,8,3,-2
FLD2,0,8
CONST.
8P10
8P+123.45
rounding option
multiplier operand descriptor
multiplicand operand descriptor
memory contents
00000010
+12345-2
+12345-3
(Product)
' indicators on? none
*
FLDl
FLD2
*
32
MP2D
NDSC4
NDSC4
USE
EDEe
EDEC
USE
8-356
"-
DZ51-00
-
(
MP2DX
MP2DX
MP2DX
246
Multiply Using Two Decimal Operands Extended
(1)
FORMAT:
0 o 0
0 1 2
o0
I
890
I
I 1
7 8
1
MF2
Icslasloo---------OINIRDI
0
0
I 1
7 8
0
2
Yl
o
o
CNI
246(1)
2 2
o1
222
789
MFI
!xl
222
234
TNI SXl
3
5
2 3
9 0
SFI
I
3
5
Nl
Yl
AR#
,:
I
Op Code
1 1
0
2
7 8
2 2
0 1
222
234
2 3
9 0
3
5
Y2
CN2
AR#
CODING FORMAT:
TN2 SX2
SF2
N2
Y2
1
8
16
MP2DX (MFl},(MF2),RD,CS,T,NS
NOSen LOCSYM,CN,N,SX,SF,AM
NDSCn LOCSYM, CN , N, SX, SF , AM
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
(
8-357
DZ5l-00
MP2DX
MP2DX
OPERATI NG MODES:
Any
SUMMARY:
C(string 2) * C(string 1) --> C(string 2)
EXPLANATION:
same as for MP3DX except that the product is stored using
YC2, TN2, SX2 and, if SX2 indicates a scaled fonnat, SF2.
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL
ILLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATeRS:
same as for MP2D.
NOTES:
1. Notes of MP3D apply.
for NFl or NF2
2. See MVNX for information about coding of overpunched
signs.
',,-
8-358
DZ5l-00
/
(
MP3D
MP3D
226 (1)
Multiply Using Three Decimal Operands
MP3D
FORMAT:
o0 1 1
890 1
0 0 0
0 1 2
Ip 0 I
1
0
0
HRDI
MF3
1 1
7 8
MF2
I
1 1
7 8
0
2
Op Code
226(1)
2 2
o1
222
789
3
5
H
222
234
MFl
2 3
9 0
I
3
5
Yl
CN1
!(
SF1
Nl
Y1
AR#
o
o
TNl Sl
1 1
7 8
0
2
2 2
0 1
222
234
2 3
9 0
3
5
Y2
CN2
SF2
N2
Y2
AR#
o
o
TN2 S2
1 1
7 8
0
2
2 2
0 1
222
234
2 3
9 0
3
6
Y3
CN3
AR#
CODI NG FORMAT:
TN3 S3
SF3
N3
Y3
The MP3D instruction is coded as follows:
1
8
16
MP3D
(MFl), (MF2), (MF3),RD,P,T
LOCSYM , CN , N, S, SF , AM
LOCSYM,CN,N,S,SF,AM
LOCSYM ,CN , N, S, SF , AM
NOSC!!
NOSC!!
NOse!!
8-359
DZ51-:00
MP3D
MP3D
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
OPERATI NG MODES:
Any
SUMMARY:
C(string 2) * C(string 1) --> C(string 3)
EXPLANATION:
The decimal number of ~ta type TN2, sign and decimal type
S2, and starting location YC2, is multiplied by the decimal
number of data type TN1, sign and decimal type Sl, and
starting location YC1. The product is stored starting in
location YC3 as a decimal number of data type TN3 and sign
and decimal type S3.
If S3 indicates a fixed-point format, the results are stored
using SF3, which may cause leading or trailing zeros (4 bits
- 0000, 9 bits - 000110000) to be supplied and/or
most-significant digit overflow or least-significant digit
truncation to occur •.
If S3 indicates a floating-point format, the result is
right-justified to preserve the most significant nonzero
digits even if this causes least significant truncation. In
this case, the most-significant-digit of the mantissa (except
for the sign digit) is set to a number digit other than O.
If P=l, positive signed 4-bit results are stored using octal
13 as the plus sign. If P=O, positive signed 4-bit results
are stored with octal 14 as the plus sign. If RD is a 1,
rounding takes place prior to storage.
Provided that string 1, string 2, and string 3 are not
overlapped, the contents of strings 1 and 2 remain unchanged.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MF1, MF2,· and MF3
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
Zero
-
If result equals zero, then ON; otherwise, OFF
Negative
-
If result is negative, then ON; otherwise, OFF
8-360
DZ51-00
MP3D
MP3D
(
Truncation -
NOTES:
If, in the preparation of the final result,
one or more least-significant digits (zero or
nonzero) are lost and rounding is not
specified, then ON; otherwise (i.e., no
least-significant digits lost or rounding
specified), OFF
Exponent
Overflow
-
If exponent of floating-point result is > 127,
then ON; otherwise, unchanged
Exponent
Underflow
-
If exponent of floating-point result is <
-128, then ON; otherwise, unchanged
Overflow
-
If data is lost in most-significant positions,
then ON; otherwise, unchanged
1. A Truncation fault occurs if the Truncation indicator is
set and the truncation fault enable
(T)
bit is a 1.
2. An Illegal Procedure fault occurs if:
a. DU or DL modification is specified for NFl, MF2, or
MF3, or if illegal repeats are used.
b. Any character (least four bits) other than 0000 - 1001
is detected where digits are defined, or any character
(least four bits) other than 1010 - 1111 is detected
where the sign is defined by the numeric descriptor.
c. The values for the number of characters (Hl or H2) of
the data descriptors are not large enough to hold the
number of characters required for the specified sign
and/or exponent, plus at least one digit.
3. If an illegal digit or sign is detected, part or all of
the receive field may be changed before the IPR fault
occurs.
8-361
DZ51-00
MP3D
MP3D
EXAMPLES:
1
FLDl
FLD2
FLD3
8
16
32
MP3D
NDSC4
NDSC4
NDSC9
USE
, , ,1
FLDl,6,2,2
FLD2,0,8,1,-3
FLD3,1,7,1,-2
CONST.
8P5+
8P+1234567
2
with rounding option
multiplier operand descriptor
multiplicand operand descriptor
product operand descriptor
memory contents
0000005+
+1234567
+617284
(Product)
indicators on? none
EDEC
EDEC
BSS
USE
MP3D
NDSC4
NDSC4
NDSC4
USE
FLDl
FLD2
FDL3
*
EDEC
EDEC
EDEC
USE
, , , ,1
FLD1,0,2,3,-2
FLD2,0,8,1,-3
FLD3,1,7
CONST.
2PL25
8P-1234567
8P+0
multiplier operand descriptor
multiplicand operand descriptor
product operand descriptor
memory contents
25000000
-1234567
+-3086-1
(Product)
instruction fault? no
indicators on? truncation and negative
\,
8-362
DZ5l-00
..
../
MP3DX
MP3DX
Multiply Using Three Decimal Operands Extended
MP3DX
266 (1)
FORMAT:
HRDI
MF3
o
o
1 1
7 8
001 1
890 1
000
MF2
I
1 1
7 8
0
2
Op Code
222
789
II I
266(1)
2 2
o1
222
234
3
MF1
2 3
9 0
3
5
Yl
CNl
SF1
Nl
Yl
AR.#
o
o
TNI SXl
1 1
7 8
0
2
2 2
0 1
222
234
2 3
3
5
9 0
Y2
CN2
SF2
N2
Y2
AR.#
o
o
TN2 SX2
1 1
7 8
0
2
2 2
0 1
222
234
2 3
9 0
3
5
Y3
CN3
AR.#
CODI NG FORMAT:
TN3 SX3
SF3
N3
Y3
1
8
16
MP3DX
NDSCn
NDSCn
NDSCn
(MF1), (MF2), (MF3),RD,CS,T,NS
LOCSYM,CN,N,SX,SF,AM
LOCSYM,CN,N,SX,SF,AM
LOCSYM,CN,N,SX,SF,AM
8-363
DZ51-00
MP3DX
MP3DX
)
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
OPERATING MODES:
Any
SUMMARY:
C(string 2} * C(string 1) --> C(string 3)
EXPLANATION:
The decimal number of data type TN2, sign and decimal type
S2, and starting location YC2, is multiplied by the decimal
number of data type TNl, sign and decimal type Sl, and
starting location YC1. The product is stored starting in
location YC3 as a decimal number of data type TN3 and sign
and decimal type S3.
If SX3 indicates a fixed-point format, the results are stored
using SF3, which may cause leading or trailing zeros (4 bits
- 0000, 9 bits - 000110000) to be supplied and/or
most-significant-digit overflow or least-significant-digit
truncation to occur.
If SX3 indicates a floating-point format, the result is
right-justified to preserve the most-significant-nonzero
digits even if this causes least-significant truncation. In
this case, the most-significant digit of the mantissa (except
for the sign digit) is set to a number digit other than O.
The character set is defined by CS. Placement of over
punched sign in the output is controlled by NS. (Refer to
introductory pages of this section for definition of NS.) If
RD is 1, rounding takes place prior to storage.
Provided that string 1, string 2, and string 3 are not
overlapped, the contents of strings 1 and 2 remain unchanged.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MFl, MF2
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
Same as for MP3D.
NOTES:
1. Notes of MP3D apply.
2. See MVNX for information about coding of overpunched
signs.
8-364
DZ5l-00
(
MPF
MPF
MPF
401 (0)
Multiply Fraction
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Any
SUMMARY:
C(A) * C(Y) --> C(AQ), left justified: C(Y) unchanged
EXPLANATION:
This instruction multiplies two 36-bit fractional factors
(including sign) to form a 7l-bit fractional product
(including sign). The product is stored in AQ,
left-justified. Bit 71 of C(AQ) is filled with a zero bit.
Overflow can occur only when A and Y both
exceeds the range of the AQ-register.
o
o
3
0
factor
(
= -1
and the result
0
3
factor
*
C(A)
C(Y)
yielding:
o
0
7 7
product
C(AQ)
ILLEGAL ADDRESS
MODI FI CATIONS:
CI, SC, SCR
I LLEGAL REPEATS:
None
INDICATORS:
zero
-
If C(AQ)
Negative
-
If bit 0 of C(AQ)
Overflow
-
I f range of AQ is exceeded, then ON
NOTE:
= 0, .then ON; otherwise, OFF
= 1,
then ON; otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modification is used.
(
8-365
- - --------
----
DZ5l-00
MPRR
MPRR
Multiply Register Pair by Register
530 (1)
FORMAT:
1 1
000
22233
OP CODE
Not Used
CODING FORMAT:
1
3
8
16
MPRR
Rl, ,R2
OPERATING MODES:
Executes only in ES mode.
SUMMARY:
for Rl-odd Rl: 1, 3, 5, 7, Q
for Rl-pair Rl: 0, 2, 4, 6, A
C(Rl-odd) x C(R2)
--> C(Rl-pair)
C(R2) unchanged
EXPLANATION
register pair is specified in Rl. The product of the
content of the odd-numbered register (Q if A,Q specified) and
that of R2 is taken and the result is loaded, right-justified
into the Rl-pair.
A
x
C{Rl-odd)
C(R2)
71
0
Product
S S
C(Rl-pau)
8-366
DZ51-00
MPRR
MPRR
I LLEGAL ADDRESS
MODIFICATIONS:
None.
ILLEGAL REPEATS:
RPT, RPD, RPL
ILLEGAL
The address modification is not executed.
EXECUTES: Execution in NS mode
INDICATORS:
Zero
-
Negative NOTES:
If C(Rl-pair) = 0, then ON: otherwise, OFF
If C(Rl-pair)O
= 1,
then ON: otherwise, OFF
1. An IPR fault occurs if illegal repeats are executed or if
the instruction is executed in NS mode.
2. Refer to "Register to Register Instructions" in Section 7
for a description of the fields in the instruction word.
8-367
DZ5l-00
MPRS
MPRS
MPRS
Multiply Single Register by Register
531 (l)
FORMAT:
1 1
000
Not Used
CODING FORMAT:
1
3
OP CODE
8
16
MPRS
R1, ,R2
OPERATING MODES:
Executes in ES mode only
SUMMARY:
R1, R2
= 0,
22233
1, 2, 3, 4, 5, 6, 7, A, Q
C(R1) x C(R2)
-->
C(R1)
C(R2} unchanged
EXPLANATION
The product of the content of Rl and R2 is taken. The
low-order 36 bits of the result are loaded into R1.
In;:~~iatel:1
34,:1
\,_________ _--------1.
I
Truncated
(TR bits>
Resultant C(R1)
8-368
DZ51-00
MPRS
MPRS
(
The multiplication is performed on the two's complement data
to obtain 7l-bit two's complement data as an intermediate
result. The low-order 36 bits of this intermediate result
are loaded into Rl.
I LLEGAL ADDRESS
MODIFICATIONS:
None.
I LLEGAL REPEATS:
RPT, RPD, RPL
The address modification is not executed.
ILLEGAL EXECUTES: Execution in NS mode
INDICATORS:
Zero
-
Negative NOTES:
If the intermediate result is 0, then ON;
otherwise OFF
If the intermediate result)O is 1, then ON,
otherwise, OFF
1. An IPR fault occurs if illegal repeats are executed or if
the instruction is executed in NS mode.
2. Refer to "Register to Register Instructions" in Section 7
for a description of the fields in the instruction word.
3. No overflow check for the final result is performed;
therefore, the Zero and Negative indicators are set by the
state of the intermediate result.
(
8-369
DZ51-00
MPX
MPX
MPX
FORMAT:
CODING FORMAT:
Multiply GXn
Single-word instruction format (see Figure 8-1)
1
8
16
MPX
n,Y,R,AM
OPERATING MODES:
Executes in ES mode only
SUMMARY:
C(GXn} x C(Y) --> GXn
EXPLANATION:
The product of the content of GXn and that of the one word at
memory location Y is taken. The low-order 36 bits of the
resul t is loaded into GXn •
C(Y)
Intermediate
result
\.----------~----------
The multiplication is performed on the two's complement data
to obtain 71-bit two's complement data as an intermediate
result. The low-order 36 bits of this intermediate result
are loaded into the GXn.
8-370
DZ5l-00
(
MPX
MPX
ILLEGAL ADDRESS
MODI FI CATIONS:
0,
I LLEGAL REPEATS:
None
SC, SCR
ILLEGAL EXECUTES: If the instruction is executed in NS mode
I NDI CATORS:
NOTES:
Zero
If the intermediate result is 0, then ON;
otherwise OFF.
Negative
If the C(AQ}, right justified; C(Y) unchanged
EXPLANATION:
This instruction multiplies two 36-bit integral factors
(including sign) to form a 7l-bit integral product (including
sign). The product is stored in AQ, right-justified. Bit 0
of C(AQ) is filled with an "extended sign" bit.
0
0
3
5
0
1
I 51
factor
0
I
C(A)
3
5
0
0 1
*
I 51
factor
I
C(Y)
yielding:
/
0 0 0
0 1 2
7
7
0 1
I 51 51
product
C(AQ)
I 01
When (-2**35) * (-2**35) = +2**70, bit 1 of AQ is used to
represent the product rather than the sign and no overflow
occurs.
I LLEGAL ADDRESS
MODIFICATIONS:
CI, SC, SCR
I LLEGAL REPEATS:
None
INDICATORS:
Zero
-
If C(AQ)
Negative
-
If bit 0 of C(AQ) = 1, then ON; otherwise, OFF
NOTE:
= 0,
then ON; otherwise, OFF
Illegal Procedure fault occurs if illegal address
modification is used.
An
8-372
DZ5l-00
MRL
MRL
Move Alphanumeric Right to Left
101 (1)
FORMAT:
o0 1 1
890 1
o
FILL
1+1
1 1
7 8
MF2
Op Code
1
101(1)
023
Yl
CNI TAl 0
AR#
3
5
Nl
Rl
1 1 2 2 222
7 8 0 1 234
023
Y2
CODING FORMAT:
3
2
Yl
000
AR#
NFl
1 1 2 2 222
7 8 o 1 234
000
3 _
2
CN2 TA2 0
3
3
2
5
N2
Y2
R2
The MRL instruction is coded as follows:
1
8
16
MRL
(NFl), (MF2),FILL,T
LOCSYN,CN,N,AM
LOCSYN, CN , N,AM
ADSCg
ADSCg
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
OPERAT! NG NODES:
Any
SUMMARY:
C(string 1) --> C(string 2)
8-373
DZ51-00
MRL
MRL
EXPLANATION:
This instruction is identical with MLR except that the
starting locations are YCI + (Ll-l) and YC2 + (L2-1) and the
movement is from right to left (from least-significant
character towar.d most-significant character). Consequently,
any truncation or fill is of the most-significant characters.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL for NFl and MF2
I LLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
Truncation -
NOTES:
1. An Illegal Procedure fault occurs if illegal address
modification or illegal repeats are used.
If Ll is > L2, then ON; otherwise, OFF
2. A Truncation fault occurs if the Truncation indicator is
set and the truncation fault enable (T) bit is a 1.
3. Refer to Note 3 of the MLR instruction for information on
string replication.
4. L2 = 0 does not necessarily mean that the instruction
functions is a no-op because the truncation indicator may·
be affected.
EXAMPLE:
1
FLDl
FLD2
FLDl
FLD2
8
16
32
MRL
ADSC6
ADSC6
USE
,,20
FLD1,,12
FLD2,4,14
CONST.
2,ABCDEFGHIJKL
move with blank fill
sending descriptor
receiving descriptor
memory contents
BSS
USE
3
xxxxti~ABCDEFGHIJKL
MRL
ADSC6
ADSC4
USE
Bel
BSS
USE
, ,400
FLD1,3,9
FLD2,4,12
CONST.
move with sign and fill
sending descriptor
receiving descriptor
memory contents
BCI
(Result)
2,~~~12345678R
2
xxxx-00123456789
8-374
(Result)
DZ51-00
' -.._
j
(
MTM
MTM
MTM
365
Move to Memory
(1)
FORMAT:
o
1 1
3 4
I
1 1
7 8
RECR
Y
I
2 2 2 2
o1 2 3
CN
I lsi
222
789
!xl
3
5
MFl
I
3
3
3
5
ILI
The MTM instruction is coded as follows:
1
8
16
MTM
(MF1) ,RECR
Y,CN,L, ,AM
SDSCn
EXPLANATION:
Code
365(1)
I
1 1
7 8
000
CODING FORMAT:
Op
This instruction moves one, two, three, or four 9-bit characters
into memory from the register specified in the RECR field of the
instruction. MTM is the inverse of MTR.
The move from the register into memory is done from right to left
beginning at YCN + (L-l). (L must be 0-4.)
The setting of the B field shown in the descriptor diagram above,
is determined by the contents of the n in SDSCn. (A 9 in the n
field sets B = 0; an 8 sets B = 1.) This setting determines the
functions of the move operation as follows.
o If B = 0
The 9-bit characters are fetched at once from the
specified register and moved into memory without
modification.
8-375
-----.~~~.
DZ5l-00
MTM
MTM
o
8-bits (1 byte) are fetched from the specified
register and 0 is concatenated to the
most-significant bit position to form a 9-bit
character. Then the character is moved to
memory. Up to L characters can be moved.
If B = 1
An A, Q, or
RECR field.
XO-X7, GXO-GX7
register may be specified in the
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL specified in MF
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1. Refer to "Character Move To/From Register Instructions" in
section 7 for a description of the fields in the operand
descriptor (SDSC).
2.
An
IPR fault occurs under the following conditions.
o If RECR specifies
hold 2 bytes.)
XO-X7
and L > 2.
o I f RECR spec if ies A or Q or
GX-GX7
(XO-X7
can only
and L > 4.
o If illegal address modifications or illegal repeats are
used.
3. The RL bit of the MF field is ignored. The character
length must be specified in the L field of the operand
descriptor.
4. When L = 0, the MTMinstruction functions as a NOP.
5. Refer to Explanation under the MTR instruction for the
codes allowed in the RECR field.
8-376
DZSI-00
(
MTR
MTR
Move to Register
361 (1)
FORMAT:
o
1
4
0
1
o
1 1
7 8
1 1
7 8
0
Y
I
222
7 8 9 .
II I
3
5
NFl
2 2 2 2
012 3
CN
1;181
33
2 3
0-----------------0
I
3
5
IL I
The MTR instruction is coded as follows:
1
EXPLANATION:
Code
361(1)
I RECR I
Hot Used
CODING FORMAT:
Op
8
16
MTR
SDSCn
(MF1),RECR
Y,CN,L,SE,AM
This instruction moves one, two, three, or four 9-bit characters
from the memory location beginning at YCN + (L-1) to a register
specified by the RECR field (bits 14-17) of the instruction
word. MTR is the inverse of MTM.
The moved characters are right-justified in the specified
register.
The setting of the B field shown in the descriptor diagram above,
is determined by the contents of the n in SDSCn. (SOSC9 sets B =
0: SDSC8 sets B = I.> The SE field is specified by the user.
These settings determine the character positioning functions of
the move operation as follows.
o If
B
=0
The 9-bit
specified
less than
specified
character
follows.
characters from memory are moved to the
register without modification. If L is
the character size capacity of the
register, the vacant high-order
positions of the register are filled as
DZ51-00
8-377
~~~
.
-~---.---------
----------- -------
--- --------
MTR
MTR
SE
=0
The remaining character positions are filled
with O.
SE
=1
Bi t 0 of the last character moved is regarded
as a sign and the value of this bit is
extended to fill the remaining character
positions of the register.
o If B = 1
Bit 0 of each 9-bit character moved from
memory is removed and the resulting 8-bit
bytes are moved in a right-justified string
into the specified register. The SE field
affects the result of the move as follows.
SE = 0
The remaining bit positions of the specified
register are filled with O.
SE = 1
Bit 0 of the last 8-bit byte moved to the
specified register is extended to fill the
remaining high-order bits of the register.
A, Q, or XO-X7 I GXO-GX7 register may be specified in the
RECR field. The code of these registers is the same as for
An
the register code specified in the REG portion of the MF
field. An invalid specification results in an IPR fault.
The RECR codes are displayed below.
Register
RECR Code
(NS Mode)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
8-378
(BS Mode)
IPR
IPR
A
A
Q
Q
IPR
IPR
IPR
IPR
IPR
IPR
IPR
IPR
IPR
IPR
XO
Xl
X2
X3
X4
X5
X6
X7
GXO
GX1
GX2
GX3
GX4
GX5
GX6
GX7
DZ51-00
\.~j
MTR
MTR
The number of characters to be moved is specified in the L
field of the operand descriptor.
I LLEX;AL ADDRESS
MODIFICATIONS:
DU, DL specified in MF
ILLEGAL REPEATS:
RPT, RPD, RPL
I
NDI CATORS:
NOTES:
Zero
-
ON if C(register)
Negative
-
ON if bit
OFF.
= 0;
otherwise, OFF.
°of C(register) =
1; otherwise,
1. Refer to "Character Move To/From Register Instructions" in
Section 7 for a description of the fields in the operand
descriptor (SOSC).
2.
An
IPR fault occurs under the following conditions.
o If RECR specifies XO-X7 and L
hold 2 bytes.)
> 2.
(XO-X7 can only
o If RECR specifies A or Q or GX-GX7 and L > 4.
'0
If illegal address modifications or illegal repeats are
used.
2. The RL bit of the MF field is ignored. The character
length must be specified in the L field of the operand
descriptor.
3. If L = 0, the contents of the receiving register is set to
0, the Zero indicator to ON, and the Negative indicator to
OFF.
8-379
DZ51-00
MVE
MVE
Move Alphanumeric Edited
MVE
020 (1)
FORMAT:
a011
890 1
aa a
o1 2
00
1 1
NF3
1 1
7 8
I
NF2
1+1
a a0
Yl
CNl TAl
2 3
9
a
3
2
3
5
Nl
not
interpreted
1 1 2 2 2 2 2
7 8 a1 2 3 4
CN2 TA2
a
233
9 a 2
3
5
N2
not
interpreted
Y2
R2
1 1 222 2 2
7 8 a1 2 3 4
000
023
Y3
CODING FORMAT:
I
NFl
Rl
Y2
AR#
3
5
III
020(1)
a
222
789
Yl
000
023
AR#
Code
1 1 2 2 2 2 2
7 8 o 1 234
0 2 3
AR#
Op
CN3 TA3 a
233
9 a 2
not
interpreted
Y3
3
5
N3
R3
The MVE instruction is coded as follows:
1
8
16
MVE
ADSCn
ADSC9
ADSCn
(MF1),(MF2),(MF3)
LOCSYM,CN,N,AM
LOCSYM,CN ,·N,AM
LOCSYM,CN,N,AM
8-380
DZ5l-00
(
MVE
MVE
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
OPERATI NG MODES:
Any
SUMMARY:
string 2 control
C(string 1)
EXPLANATION:
----------> C(string 3)
Starting at location YC1, the string of alphanumeric
characters of data type TAl is moved to the string of
alphanumeric characters of data type TA3 starting at location
YC3. The move is under control of the micro operation
sequence of length 12 and type TA2 = 00 that starts at
location YC2. (Refer to "Micro Operations" in this section.)
Maximum allowable length for Ll, L2, and L3 is 63: they are
not checked for length greater than 63. Only the rightmost
six bits (30-3S) are interpreted for length. Likewise, when
a register is specified as containing the length, only the
rightmost six bits of the register are interpreted.
The operation stops when L3 is exhausted.
The result is unpredictable when strings are overlapped.
The contents of the alphanumeric character string that starts
at YCI and the micro operation sequence that starts at YC2
remain unchanged.
On the processor, L3 = 0 is the normal termination: thus, at
the start of the instruction, if L3 = 0 and there are no
faults (see Note), no operation is performed and the
instruction terminates normally, independently of whether Ll
or L2 equals zero, because the hardware does not access these
fields when L3 = O.
1 LLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MFl, MF2, and MF3
1 LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
8-381
-_._---_._._-.---
-..
---~.~~.
DZS1-OO
MVE
MVE
NOTE:
1.
Illegal Procedure fault occurs under the following
conditions.
An
o If illegal address modification is used
o I f illegal repeats are used.
o If an illegal mirco operation is executed.
o If TA2 is not = O.
= O.
o If an attempt is made to access string 2 when L2
2. Refer to "Micro Operations for Edit Instructions" in
Section 7.
\
8-382
DZ5l-00
'--
.
-~-./
MVE
MVE
C(string 2)
8-385
DZ51-00
MVN
MVN
EXPLANATION:
starting at location YC1, the decimal number of data type TNl
and sign and decimal type Sl is moved, properly scaled, to
the decimal number of data type TN2 and sign and decimal type
S2 that starts at location YC2.
If S2 indicates a fixed-point format, the results are stored
as L2 digits using scale factor SF2, and thereby may cause
most-significant-digit overflow and/or
least-significant-digit truncation.
If P = 1, positive signed 4-bit results are stored using
octal 13 as the plus sign. Rounding is legal for both
fixed-point and floating-point formats. If P = 0, positive
signed 4-bit results are stored using octal 14 as the plus
sign.
Provided that string 1 and string 2 are not overlapped, the
contents of the decimal number that starts in location YCl
remain unchanged.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MFl and MF2
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
Zero
-
If result equals zero, then ON; otherwise, OFF
Negative
-
If result is negative, then ON: otherwise, OFF
j
Truncation -
NOTES:
If least significant truncation without
rounding, then ON; otherwise, OFF
Exponent
Overflow
-
If exponent of floating-point result is > 127,
then ON; otherwise, unchanged
Exponent
Underflow
-
If exponent of floating-point result is <
-128, then ON; otherwise, unchanged
Overflow
-
If fixed point integer overflow, then ON:
otherwise, unchanged.
1. Truncation fault occurs if the truncation indicator is set
and the truncation fault enable (T) bit is 1.
8-386
DZ51-00
.-
MVN
MVN
(
2.
An
Illegal Procedure fault occurs if:
0
Illegal address modification is specified or illegal
repeat is used.
0
Any character (least four bits) other than 0000 - 1001
is detected where digits are defined, or any character
(least four bits) other than 1010 - 1111 is detected
where the sign is defined by the numeric descriptor.
0
The values for the number of characters (Nl or N2) of
the data descriptors are not large enough to hold the
number of characters required for the specified sign
and/or exponent, plus at least one digit.
3. Refer to Explanation of the MLR instruction for
information on string replication.
4. If an illegal digit or sign is detected, part or all of
the receive field may be changed before the IPR fault
occurs.
EXAMPLES:
I(
1
FLDl
FLD2
FLDl
FLD2
8
16
32
MVN
NDSC4
NDSC4
USE
IDEC
IDEe
USE
, ,1
FLD1,0,8,2,-3
FLD2,l,7,1,-2
CONST.
8P1234567+
8PO
with rounding option
sending field operand descriptor
receiving field operand descriptor
memory contents
1 2 3 456 7 +
o + 1 2 3 457 (Result)
no indicators set ON
MVN
NDSC9
NDSC4
USE
IDEC
BSS
USE
, , , ,1
FLDl,3,9,2,-2
FLD2,0,8,O
CONST.
l2A123456781
with truncation fault enable option
sending field operand descriptor
receiving field operand descriptor
memory contents
o 0 0 1 2 3 4 567 8 - 1 2 3 4 5 + 1 (Result)
negative and truncation set ON
8-387
DZSl-OO
MVN
MVN
EXAMPLE WI TH ADDRESS MOD! FI CAT! ON:
1
16
EAX1
EAX2
EAX7
EAX4
AWDX
NVN
1
load character address into Xl
2
load address modifier into X2
7
load FLD1 length into X7
FLD1
load FLDl address into X4
0,4,4
put FLD1 address into AR4
(1,1,,1),(,,1),1,1 - with rounding and plus sign options
0"X7,2,-2,4
FLD1's operand descriptor (FLD1,1,7,2,-2)
NDSC9
FLD1
FLD2
32
8
ARG
USE
EDEe
EDEe
NDSC4
USE
FLD2+1
CONST.
8Al23456+
8PO
FLD2,2,6,3,-2
pointer to indirect operand descriptor
memory contents
o1 2 3 4 5 6 +
o 0 0 0 1 2 3 5 (Result)
recg. field indirect operand descriptor
no indicators set ON
8-388
DZ51-00
Y1
N1
CN1
AR#
TN1 Sl
not
interpreted
Y1
R1
1 1
7 8
000
023
222
0 1 2
3
2 2
4
TA2
0
233
9 0
2
Y2
N2
CN2
AR#
not
interpreted
Y2
R2
1 1 222 2 2
7 8 0 1 2 3 4
000
023
233
9 0
2
Y3
CODING FORMAT:
3
5
N3
CN3
AR#
3
5
TA3
0
not
interpreted
Y3
R3
The MVNE instruction is coded as follows:
1
8
16
MVNE
NDSCn
ADSC9
ADSCn
(MFl),(MF2),(MF3)
LOCSYM,CN,N,S"AM
LOCSYM,CN,N,AM
LOCSYM,CN,N,AM
(
8-389
DZ5l-00
!NNE
!NNE
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
OPERATI NG MODES:
Any
SUMMARY:
string 2 control
C(string 1) .
. ---> (string 3)
EXPLANATION:
Starting at location YC1, the string of numeric characters of
data type TNl is moved to the string of alphanumeric
characters of data type TA3 starting at location YC3. The
move is under control of the micro-operation sequence of
length L2 and type TA2 = 00 that starts at location YC2.
(Refer to "Micro Operations" in this section).
Maximum allowable length for Ll, L2, and L3 is 63; they are
not checked for length greater than 63. Only the rightmost 6
bits (30-35) are interpreted for length. Likewise when a
register is specified as containing the length, only the
rightmost 6 bits of the register are interpreted.
The operation stops when L3 is exhausted.
The results are not guaranteed when strings are overlapped.
The sign and decimal type of the sending field is given by
51. The contents of the numeric character string that starts
at YCl and the micro-operation sequence that starts at YC2
remain unchanged.
On the processor, L3 = 0 is the normal termination; thus, at
the start of the instruction, if L3 = a and there are no
faults (see Note 1), no operation is performed and the
instruction terminates normally, independently of whether L1
or L2 equals zero, because the hardware does not access these
fields when L3 = O.
ILLEGAL ADDRESS
MODIFICATIONS:
I
LLEGAL REPEATS:
I NDI CATORS:
OU, OL for MF1, MF2, and MF3
RPT, RPD, RPL
None affected
8-390
OZ51-00
(
MVNE
MVNE
NOTES:
1.
Illegal Procedure fault occurs under the following
conditions.
An
o If illegal address modification is used
o I f illegal repeats are used
o I f an illegal micro operation is used
o If TA2 is not = 0
o If an attempt is made to access string 2 when L2
=0
2. Refer to Micro Operations for Edit Instructions in Section
7.
8-391
DZ51-00
MVNE
EXAMPLES:
1
8
16
32
with ($) float and (.) inserted
FLDl,0,10,2
sending field operand descriptor
FLD2,0,14
micro-op string operand descriptor
FLD3,0,12
receiving field operand descriptor
CONST.
memory contents in ASCI I characters
10A300405000300405-00
EDEC
MICROP (CHT,0),8HM*+-$,.0,(MFLC,7),(ENF,8),(INSB,7)
MICROP (MVC,2) , (I NSN , 4) memory contents in BCD characters
MVNE
NOSC9
ADSC9
ADSC6
USE
FLOl
FL02
FL03
BSS
2
~ ~ ~
$ 3 004 • 05-
(Result)
USE
with (*) protection and (.) insertion
FLDl,0,8,2
sending field operand descriptor
FLD2,0,6
micro-op string operand descriptor
FLD3,0,12
receiving field operand descriptor
CONST.
memory contents in packed decimal
8P250509025059EDEC
MICROP (MVZA,5),(SES,8),(INSA,7),{MVC,2)
MICROP (INSN,4), (INSM,3)
memory contents in ASCII characters
BSS
3
* 2 5 5 • 9 - ~ ~ ~ (Result)
USE
MVNE
NOSC4
ADSC9
ADSC9
USE
FLOl
FL02
*
FL03
° °
MVNE
NDSC4
ADSC9
ADSC6
MVT
ADSC6
ADSC9
6PACK,3,5,1
MOPS,0,6
PRTOUT,0,4
+1234 ----> 1234
. -1234 ----> 123M
PRTOUT,0,4
APRINT,0,4
TABLE
ARG
CONST.
USE
MOPS MICROP (MVC,3), (LTE,3),10000, (LTE,4),10040,(MORS,1)
2,01234567
OX
TABLE ASCII
Al8/89,18/0,36/0 lX
VFD
0,0
2X
OCT
0,0
3X
OCT
2, JKLMNOP
4X
UASCI
U18/QR,18/0,36/0 5X
VFD
0,0
6X
OCT
0,0
7X
OCT
USE
8-392
DZ51-00
./
(
MVNEX
MVNEX
Move Numeric Edited Extended
MVNEK
004
(1)
FORMAT:
o0 1 1
890 1
000
012
I
E
I
0
0
1 1
7 8
I 001
MF3
I
MF2
Op
Code
004(1)
222
789
H
1 1 222 2 2
7 8 0 1 2 3 4
0
2
3 -
NFl
3
0
3
5
Y1
CN1 TN1 SX1
Y1
AR#
(
o
o
1 1 222 2 2
7 801 2 3 4
0
2
Y2
CN2 TA2 0
N1
3
3
o
not
interpreted
5
N2
Y2
AR#
o
o
not
interpreted
1 1 222 2 2
7 B 012 3 4
0
2
Y3
3
not
interpreted
5
N3
Y3
AR#
COD! NG
CN3 TA3 0
3
o
FORMAT:
1
8
16
MVNEX
(MF1),(MF2),(MF3),E
LOCSYM,CN,N,S"AM
LOCSYM, CN , N, AM
LOCSYM,CN,N,AM
NDSCn
ADSC9
NOSCn
8-393
DZ51-00
MVNEX
MVNEX
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
OPERATI NG MODES: Any
string 2 control
C(string
SUMMARY:
EXPLANATION:
1)
------->
(string 3)
The function of this instruction is similar to the MVNE
instruction, but with the added capability of initializing an
edit insertion table. (see Table 7-2). A 2-bit code entered
in field E (bits 0 and 1) specifies the character set
associated with the edit insertion table as follows.
E-Bits 0 and 1
00
01
10
.11
EBCDIC
BCD
ASCII
Illegal, IPR fault
TNI determines whether the input data is unpacked (0) or
packed (I). TA3 determines the character size (9, 6, or 4
bits) of the output data. It is the user's responsibility to
make TA3 consistent with bits 0 and 1 of the instruction. S
determines the location of the sign of the input data
(leading, trailing, overpunched, separate). Refer to the
Explanation for MVNE for additional information.
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL for MFl, MF2, and MF3
ILLEGAL REPEATS: RPT, RPD, RPL
I NDI CATORS:
None affected
NOTES:
1. Notes for MVNE apply to MVNEX.
2.
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
3. Refer to "Micro Operations for Edit Instructions" in
Section 7.
8-394
DZ51-00
(
MVNX
MVNX
MVNX
Move Numeric Extended
340 (1)
FORMAT:
000
1 1
0 011
MF2
o
o
340(1)
1 1 2 2
780 1
0
2
Y1
MF1
222
2 3
234
9 0
CN1 TN1 SX1
3
SF1
3
5
N1
Y1
AR#
o
o
222
Op Code
1 1 2 2
780 1
0
2
Y2
AR#
CODING FORMAT:
222
2 3
9 0
234
CN2 TN2 SX2
SF2
3
5
N2
Y2
1
8
16
WNX
NDSCn
NDSCn
(MF1 ) , (MF2) , RD , C:S, T, NS
LOCSYM , CN , N, SX ,SF, AM
LOCSYM, CN , N,SX, SF, AM
(Refer to Section 7 under Multiword Instructions for description
of Multiword Modification Field.)
OPERATI NG MODES:
Any
(
8-395
DZ51-00
MVNX
MVNX
SUMMARY:
C(string 1)
EXPLANATION:
Starting at location YC1, the decimal number of data type TNl
and sign and decimal type SXl is moved, properly scaled, to
the decimal number of data type TN2 and sign and decimal type
SX2 that starts at location YC2.
-->
C(string 2)
The character set is defined by CS (EBCDIC/ASCII). Placement
of an overpunched sign in the output is controlled by NS.
(Refer to the definition of the NS field in the beginning of
Section 8.)
If SX2 indicates a fixed-point format, the result is stored
as L2 digits using scale factor SF2, and thereby may cause
most-significant-digit overflow and/or
least-significant-digit truncation.
Rounding is legal for both floating and scaled formats. The
contents of the decimal number that starts in location YCl
remain unchanged.
The SX field is interpreted as follows:
TN
= 0:
Unpacked data (9 bits)
SX
TN
00:
01:
10:
11:
LS*, OVP*, scaled
LS, separate, scaled
TS*, separate, scaled
TS, OVP, scaled
= 1:
Packed data (4 bits)
SX
00:
01:
10:
11:
LS, separate, floating-point
LS, separate, scaled
TS, separate, scaled
No sign, scaled
* LS •••• Leading sign
OVP. •• Overpunched
TS •••• Trailing sign
Bits 0 and 1 of the instruction word are interpreted as
follows:
8-396
DZ51-00
MVNX
MVNX
(
Bit 0 of instruction word: Specifies the character set.
=0:
=1:
EBCDIC data (but not the strict EBCDIC sign)
ASCII data (but not the strict ASCII sign)
Bit 1 of instruction word: Specifies no-sign output.
=0:
=1:
The instruction execution is not affected.
The sign character in the receive field where the
result is to be placed is affected as follows:
If the operand descriptor of the receive field contains
TN = 0 and SX = 00 or 11 (indicating that output is an
overpunched sign), the overpunched sign is not placed
in the specified field. Instead, an appropriate
decimal number (0-9) is placed in the receive field
irrespective of whether the sign of the calculated
result is positive or negative. This is a no-sign
output.
For values of SX and TN, bit 1 is ignored.
applies both to EBCDIC and ASCII.
This
The hardware recognizes an implied plus sign on input data.
For unpacked data (TN=O) with indicated overpunched sign (SXl
= 00 or 11), if the hardware does not find a plus or minus
overpunched sign character in the overpunched sign character
position, the hardware checks for a numeric digit (0-9). The
zone bits are not included in the check; only the lower-order
4 bits are checked. If this check indicates a numeric digit
from the appropriate character set, the hardware accepts the
digit and assumes the sign to be plus. Oth~rwise an IPR
fault is generated.
Table 8-2 shows the character codes for ASCII and EBCDIC
overpunched signs.
(
8-397
DZS1-00
MVNX
MVNX
Table 8-2.
Character Codes For ASCI 1 and EBCD! C Overpunched Signs
card Punch Normal
Interp.
Code
Ovrpnch ASCII
Interp. Code
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
060
061
062
063
064
065
066
067
070
071
360
361
362
363
364
365
366
367
370
371
12
space
12-0
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
+
space
+0
+0
+0
+1
+2
+3
+4
+5
+6
+7
+8
+9
053
040
173
101
102
103
104
105
106
107
110
111
NA
NA
300
301
302
303
304
305
306
307
310
311
-0
-0
-0
-1
-2
-3
-4
-5
-6
-7
-8
-9
055
136
175
112
113
114
115
116
117
120
121
122
NA
NA
320
321
322
323
324
325
326
327
330
331
11
11-0 (GBCD)
11-0 (ASCII )
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
{
A
B
C
D
E
F
G
H
I
1\
}
J
K
L
M
N
0
p
Q
R
8-398
EBCDIC
Code
/
DZ51-00
MVNX
MVNX
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL for MFl or MF2
ILLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
zero
-
If result is zero, then
Negative
-
If result is negative, then
NOTES:
ON~
otherwise, OFF
ON~
otherwise, OFF
Truncation -
If least-significant truncation without
rounding, then ON~ otherwise, OFF
Overflow
-
If fixed-point integer overflow, then
otherwise, unchanged
Exponent
Overflow
-
If exponent of floating-point result> 127,
then ON~ otherwise, unchanged
Exponent
Underflow
-
If exponent of floating-point result
then ON~ otherwise, unchanged
ON~
<
-128,
1. A Truncation fault occurs if the truncation indicator is
set and the truncation fault enable bit (T) is a 1.
2. An IPR fault occurs if any character (least four bits)
other than 0000 - 1001 is detected where digits are
defined, or any character (least four bits) other than
1010 - 1111 is detected where the sign is defined by the
numeric descriptor.
3. An IPR fault occurs if the values for the number of
characters (Nl or N2) of the data descriptors are not
large enough to hold the number of characters required for
the specified sign and/or exponent, plus at least one
digit.
4. An IPR fault occurs illegal address modifications or
illegal repeats are used.
5. Refer to Note 3 of MLR for information on string
replication.
6. If an illegal digit or sign is detected, part or all of
the receive field may be changed before the IPR fault
occurs.
(
8-399
DZ51-00
MVT
Move Alphanumeric with Translation
MVT
160
(1)
FORMAT:
o0
0
0
1
FILL
1 1
7 8
1 1
o1
8 9
MF2
1+1
Op. Code
160(1)
1
0 o0
0 2 3
3
5
H
1 1 2 2 222
7 8 o 1 234
CNl TAl
NFl
3
2
Yl
AR#
222
789
3
5
Nl
0
Yl
00---------0
1 1 2 2 222
7 8 0 1 234
000
023
1
Y2
Rl
3
3
2
5
N2
CN2 TA2 0
AR#
Y2
00-------0
1 1 2 2 222
7 8 0 1 234
000
023
Y3
2 2 333
8 9 012
CODING FORMAT:
5
00
REG
Y3
The MVT instruction is coded as follows:
1
8
16
MVT
ADSCn
ADSCn
(MF1),(MF2),FILL,T
LOCSYM, CN ,N , AM
LOCSYM, CN , N, AM
TABLE, REG, AM
ARG
OPERATI NG MODES:
3
A
00-------------0 R
AR#
R2
kny
8-400
DZ51-00
MVT
MVT
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
EXPLANATION:
starting at location YC1, the alphanumeric characters of data
type TAl are used as an index to a table of contiguous 9-bit
characters that start at location Y3 (character position 0).
The octal code of the character of string-l is used as an
index to string-3. The indexed 9-bit characters (or
right-justified 4- or 6-bit characters) of string-3 replace
the contents of string 2, starting at location YC2. If TAl
and TA2 are dissimilar, each character will have higb-order
truncation. If Ll is less than L2, the FILL character (the
entire 9 bits) is used as the index to the table to replace
the L2-Ll least significant characters of string 2. The
contents of string 1 remain unchanged except in cases of
string overlap. When the 9-bit character translate table and
the string are overlapped, the result is unpredictable.
L2 = 0 does not necessarily mean that the instruction
functions as a NOP because the truncation indicator may be
affected.
If Ll < L2, and type TAl is 4 or 6-bit, the low-order 4 or 6
bits of the fill character (9-bit) in the instruction word
are defined as a table index.
The translation table must begin at a word boundary at
character position O. The index (expressed by the number of
9-bit characters) is added to the starting word address of
the table. It is computed in the same way as for normal
address modification: however, the computed address is then
used as a word address (with character position ignored).
The index is added to this word address as a 9-bit number.
The translation table length is determined by the highest
possible index character octal value that may be found in the
indexing data string. The table is always indexed in 9-bit
increments, regardless of the data type being moved. The
9-bit character represented in the table must be the same
data type as the receiving field. (See Examples for MVT.)
When address register modification is specified, the
translation table address is generated as follows.
(8-401
DZ5l-00
MVT
MVT
1<-1
y
Operand descriptor
y field
+
WORD
CHAR
Address Register
WORD and CHAR
+
WB
CB
Segment descriptor
BASE
\/
W=y+WORD+WB
CHAR
+CB
.
Addition result. If a
carry occurs as result
of CHAR+CB, it is transferred to word portion •
The above character position is then forcibly set to
O.
The translage table
start address
W
+
Iw
Ic
Index (9-bit character
number)
Ic
Word address
W+ Iw
\/
W+ Iw
\
I Specifies
content of
I table
translate
used
>
Olaracter
position Ic
/
When index register modification is specified, the content of
that register is added to the word portion.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MF1, MF2, and REG field for Y3
I LLEGAL REPEATS:
RPT, RPD, RPL
8-402
DZ5l-00
MVT
MVT
(
I NDI CATORS :
Truncation - If Ll is > L2, then ON; otherwise, OFF
NOTES:
l. An Illegal.Procedure fault occurs if illegal address
modification or illegal repeats are executed.
2. A Truncation fault occurs if the truncation indicator is
set and the truncation fault enable (T) bit is a 1.
3. Refer to Explanation of the MLR instruction for
information on string replication.
EXAMPLES:
1
8
16
32
MVT
ADSC6
ADSC4
,,52
FLDl,4,7
FLD2,O,8
TABLE
CONST.
2,kSkSkSkSkS123456
1
with fill index a minus
indexing operand descriptor
receiving operand descriptor
pointer to 4-bit table
memory contents
202020202001020304050620
0123456- (Result)
ARG
USE
FLDI BCl
FLD2 BSS
TABLE NULL
(
000001002003,004005006007
010011017017,017017017017
000017017017,017017017017
017017017017,017017017017
017017017017,017017017017
017017015017,017017017017
014017017017,017017017017
017017017017,017017017017
3X
4X
5X
6X
7X
BSS
FLD3,,8
FLD4,,8
TAB
CONST.
022064126317
1
(Result)
NULL
OCT
OCT
000001002003,004005006007
010011014014,014015014014
OCT
OCT
OCT
OCT
OCT
OCT
OCT
OCT
".
USE
MVT
ADSC4
ADSC4
ARG
USE
F103
FLD4
TAB
OCT
123456++
022064126314
OX
IX
2X
USE
8-403
---------_._-_.
--.'-"'--~'-
-------
DZ51-00
MVT
MVT
1
8
16
MVT
,,040
blank fill
FLDl,0,18
FLD2,0,20
TABLE9
pointer to translation table
CONST.
3,TTYMESSAGE201
ADSC6
ADSC9
ARG
USE
BCI
FLDI
FLD2 ass
TABLE9 EDI TP
UASCI
UASCI
UASCI
UASCI
UASCI
UASCI
UASCI
UASCI
EDITP
USE
32
5
SAVE, ON
2,01234567
2,89[#@:>?
OX
2, ~ABCDEFG
2,Hl'.](<\
2X
3X
2,AJKLMNOP
4X
IX
2,QR-$*)i'
5X
2,/STUVWX
6X
2,YZ_,%="!
7X
RESTORE
NOTE: The translation table length in the above example is determined by
the highest octal value for the characters of the indexing string
(Field 1). The characters in the above translation table are
represented in 9-bit ASCII code, the same data type as the
receiving field (Field 2). Also, the table is 64 characters in
length, in direct relation to the BCD character set (highest value
octal 77).
8-404
DZ5l-00
/
(
NARn
NARn
NARn
FORMAT:
CODING FORMAT:
Numeric Descriptor to Address Register n
66n (1) )
Single-word instruction format (see Figure 8-1)
1
8
16
NARn
LOCSYM,RM,AM
OPERATING MODES:
Execution in NS mode only
SUMMARY:
For n
= O,l, ••• ,or
7 as determined by op code
C(Y)0-17 --> C(ARn)0-17
translated
C(Y)18-20
EXPLANATION:
---------> C(ARn)18-23i
C(Y) unchanged
The numeric descriptor is fetched from the computed effective
address Y and the TN bit is examined. If TN = 0 (9-bit
characters), bits 18 and 19 of the CN field go to the
corresponding positions of ARn and zeros fill bits 20-23 of
ARn. If TN = 1, the 4-bit character contained in the CN
field, is converted to bit string representation and placed
in bits 18-23 of ARn. In either case, the descriptor word
address field (0-17) goes to bits 0-17 of ARn.
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1. An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
2.
IPR occurs if an attempt is made to execute this
instruction in the ES mode.
An
8-405
DZ5l-00
NARn
NARn
EXAMPLES:
1
DESCR
.,..
8
16
32
NAR2
DESCR
load data string address into AR2
FLDl,7,8,3,2
o3
o3
.
NDSC4
2 4 2 6 7 7 0 2 1 0 - descriptor
2 4 2 6 6 5
- result in AR2
'''\
8-406
DZ51-00
NEG
NEG
NEG
Negate (A-Register)
531 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
-C(A)
EXPLANATION:
This instruction changes the number in A to its negative (if
~ 0).
The operation is executed by forming the two's
complement of the string of 36 bits.
-->
C(A} if C(A)
~
0
I LLEGAL ADDRESS
MODI FI CATIONS:
None
I LLEGAL REPEATS:
RPL
I NDI CATORS :
Zero
-
If C(A)
= 0,
then ON; otherwise, OFF
Negative
- If C(A)O
= 1,
then ON: otherwise, OFF
Overflow
- I f range of A is exceeded, then ON
NOTE:
An Illegal Procedure fault occurs when an illegal repeat is
used.
(
8-407
DZ5l-00
NEGL
NEGL
NEGL
Negate Long (AQ-Register)
533 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY
- C(AQ) --> C(AQ) if C(AQ) F 0
EXPLANATION:
This instruction changes the number in AQ to its negative (if
F 0). The operation is executed by forming the two's
complement of the string of 72 bits.
LLEGAL ADDRESS
MODI FI CATIONS:
None
ILLEGAL REPEATS:
RPL
I NDI CATORS:
Zero
-
If C(AQ)
Negative
-
If C(AQ)O
Overflow
-
I f range of AQ is exceeded, then ON
I
NOTE:
= 0,
= 1,
then
then
ONi
ONi
otherwise, OFF
otherwise, OFF
An Illegal Procedure fault occurs when an illegal repeat is
used.
8-408
DZ51-00
(
NOP
NOP
NOP
(
No Operation·
011 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Any
SUMMARY:
No operation takes place; the effective address is always
prepared.
EXPLANATION:
No operation takes place but address preparation is performed
according to the specified modifier, if any. If modification·
other than DU or DL is used, the generated addresses may
cause faults.
ILLEGAL ADDRESS
MODIFICATIONS:
None
ILLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
The use of Indirect then Tally modifiers ID, DI, IDe, DIC,
SCR, or SC changes the address and tally fields of the
referenced indirect words; the Tally Runout indicator may be
set ON.
NOTES:
1. An Illegal Procedure fault occurs when an illegal repeat
is used.
2. Because address preparation takes place, modification may
result in a Bounds fault.
8-409
DZ51-00
ORA
ORA
ORA
OR to A-Register
275 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
For i
= 0 to
35,
C(A)i OR C(Y)i --> C(A)i; C(Y) unchanged
LLEGAL ADDRESS
MODIFICATIONS:
None
ILLEGAL REPEATS:
None
I NDI CATeRS:
Zero
-
If C(A)
Negative
-
If C(A)O
I
= 0,
= 1,
8-410
then ON: otherwise, OFF
then ON: otherwise, OFF
DZ51-00
ORAQ
OUQ
OUQ
OR to AQ-Register
277 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
For i
=0
to 71,
C(AQ)i OR C(Y-pair)i --> C(AQ)i: C(Y-pair) unchanged
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
None
I NDI CATORS:
Zero
-
If C(AQ)
Negative
-
If C(AQ)O
NOTE:
(
= 0,
= 1,
then ON; otherwise, OFF
then ON: otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modification is used.
(
8-411
DZ51-00
ORQ
ORQ
ORQ
OR to Q-Register
276 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
For i
= 0 to
35,
C(Q)i OR C(Y)i --> C(Q>i; C(Y) unchanged
I LLEGAL ADDRESS
MODI FI CATIONS:
None
I LLEGAL REPEATS:
None
I NDI CATORS:
Zero
-
If C(Q>
Negative
-
If
= 0, then ON; otherwise, OFF
C(Q)O = 1, then ON; otherwise, OFF
8-412
DZ51-00
ORRR
ORRR
ORRR
OR Register to Register
536
(1)
FORMAT:
1 1
000
Not Used
CODI NG FORMAT:
1
OP CODE
8
16
ORRR
Rl, ,R2
OPERATING MODES:
Executes in ES mode only
SUMMARY:
Rl, R2
= 0,
1, 2, 3, 4, 5, 6, 7, A, Q
C(Rl)i OR C(R2)i
(
--> C(Rl)I
i
= 0,1,2, ••• ,35
C(R2) unchanged
I LLEGAL ADDRESS
MODIFICATIONS:
None.
ILLEGAL REPEATS:
RPT, RPD, RPL
The address modification is not executed.
ILLEGAL EXECUTES: Execution in NS mode
I NDI CATORS :
Zero
-
Negative NOTES:
If C(Rl) = 0, then ON; otherwise, OFF
If C(R1)0
= 1,
then ON; otherwise, OFF
1. An IPR fault occurs if illegal repeats are executed or if the
instruction is executed in NS mode.
2. Refer to "Register to Register Instructions" in Section 7 for
a description of the fields in the instruction word.
8-413
DZ51-00
ORSA
ORSA
/
ORSA
OR to Storage from A-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
For
1
255 (0)
= 0 to 35,
C(A)i OR C(Y)i --> C(Y)i; C(A) unchanged
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPL
I NDI CATORS:
Zero
-
If C(Y)
Negative
-
If
NOTE:
= 0, then ONi otherwise, OFF
C(Y)o = 1, then ONi otherwise, OFF
Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
An
8-414
\ . " ~/'
DZ51-00
(
ORSQ
ORSQ
ORSQ
OR to Storage from Q-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
For i =
a to
C(Y)i~
C C(Y)i
C(Xn} and C(Y)18-35 unchanged
ES Mode
For n = O,l, ••• ,or 7 as determined by op code
For i
=0
to 35, C(GXn)i OR C(Y)i --> C(Y)i;
C(GXn) unchanged
',,--
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, or RPL of ORSXO
I NDI CATORS:
NS Mode
= 0,
zero
-
If C(Y)0-17
Negative
-
If C(Y)O
Zero
-
If C(Y)
Negative
-
If C(Y)O = 1, then OFF; otherwise, OFF
= 1,
then ON; otherwise, OFF
then ON; otherwise, OFF
ES Mode
NOTE:
~
0, then ON; otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-416
DZ5l-00
ORXn
ORXn
(
OR to Index Register g
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES
Any
SUMMARY:
NS Mode
26g (0)
For n=O,l, ••• ,or 7 as determined by op code
For i = 0 to 17, C(Xn)i OR C(Y)i --> C(Xn)i;
C(y) unchanged
ES Mode
For n=O,l, ••• ,or 7 as determined by op code
For i = 0 to 35, C(GXn)i OR C(Y)i --> C(GXn)i;
C(y) unchanged
I LLEGAL ADDRESS
MODI FI CATI ONS:
CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, or RPL of ORXO
INDICATORS:
Zero
-
If C(Xn/GXn) = 0, then ON; otherwise, OFF
Negative
-
If C(XN/GXn)O = 1, then ON; otherwise, OFF
NOTES:
1. DL modification is flagged illegal but executes with all
zeros for data.
2. An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-417
DZ51-00
PAS
PAS
PAS
Pop Argument Stack
176 (1)
FORMAT:
Single-word instruction format (see Figure B-1)
OPERATI NG MODES:
Any
SUMMARY:
Modifies bound field of the argument stack register (ASR).
EXPLANATION:
This instruction provides a means of modifying the bound
field of the ASR. The l-word operand is obtained from memory
location Y. The memory operand has the following format:
o
o
1 1
6 7
2 2
6 7
3
5
IIIIIIIII 0 IIIIIIII
IIIIIIIII or IIIIIIII
IIIIIIIII 1 IIIIIIII
SIZE
If ASR flag bit 27 = 0 nothing occurs. The argument segment
is empty and the instruction terminates.
If ASR flag bit 27 = 1, the instruction proceeds. The SIZE
field is the number of descriptors to be framed, minus 1
(i.e., the number of double-word memory locations).
The descriptor SIZE field is converted to number of bytes by
appending three 1-bits as the least-significant bits,
producing a 20-bit byte size (SIZE-bytes). Accordingly, a
memory operand SIZE field of zero means frame one
descriptor. using the 20-bit SIZE-bytes, the instruction
proceeds as follows (shaded area is ignored):
II memory operand bit 27 = 0, ASR flag bit 27 and ASR bound
field are set to zero and the instruction terminates.
If memory operand bit 27 = 1, the SIZE-bytes is compared to
the bound field of the ASR as follows:
o If SIZE-bytes < Bound, then SIZE-bytes replaces
contents of ASR Bound field.
o I f SIZE-bytes
>=
Bound, then ASR remains unchanged.
B-41B
DZ51-00
-"
!
/'
PAS
PAS
(
o C(HWMR) is unchanged for all cases.
oBits 17-26 and 28-35 of the operand are ignored by the
hardware.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, 0, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTE:
An
IPR fault occurs if illegal address modifications or
illegal repeats are executed.
EXAMPLE:
16
32
INHIB
SVPTRI STAS
SDR
STP
TRA
ON
SAVEl
Pl,O
Pl,SAVll
0,5
store argument stack
save descriptor register 1
store pointer to descriptor register 1
RTPTRI NULL
LOP
PAS
TRA
Pl,SAVll
SAVEl
0,5
locates and restores descriptor register 1
restores argument stack
1.
(
8
(
8-419
DZ51-00
PULSl
PULSl
PULSl
012 (0)
Pulse One
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERA'l'l NG MODES:
Any
SUMMARY:
No operation takes place
EXPLANATION:
The PULSl instruction is identical to the NOP instruction
except that it causes certain unique external hardware
monitoring synchronization signals to appear in the processor
logic circuitry.
ILLEGAL ADDRESS
MODI FI CATIONS:
None
I LLEGAL REPEATS:
RPT,
INDICATORS:
The use of Indirect then Tally modifiers ID, DI, IOC, DIe,
SCR, or SC changes the address and tally fields of the
referenced indirect words; the Tally Runout indicator may be
set ON.
NOTES:
1. An Illegal Procedure fault occurs when illegal repeats are
RPD, RPL
used.
2. This instruction is for use only in external hardware
monitoring equipment and not in normal coding.
8-420
DZSl-OO
(
PULS2
PULS2
PULS2
Pulse Two
013 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
No operation takes place
EXPLANATION:
The PULS2 instruction is identical to the NOP instruction
except that it causes certain unique external hardware
monitoring synchronization signals to appear in the processor
logic circuitry.
.
ILLEGAL ADDRESS
MODI FI CATIONS:
None
I LLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
The use of Indirect then Tally modifiers ID, DI, IOC, DIC,
SCR, or SC changes the address and tally fields of the
referenced indirect words: the Tally Runout indicator may be
set ON.
NOTES:
1. An Illegal Procedure fault occurs when illegal repeats are
. used.
2. This instruction is for use only in external hardware
monitoring equipment and not in normal coding.
(
8-421
DZ51-00
QFAD
QFAD
QFAD
Quadruple-Precision Floating Add
476 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
[C(EAQ, LOR) + C(Y 4 words)] normalized -> C(EAQ, LOR)
EXPLANATION:
The exponent underflow indicator is not set when the
low-order exponent (EL) is in underflow (Eu-15 < -128). At
this time, the correct value + 256 is loaded into EL and the
correct value into the low-order mantissa (ML - LOR8-71).
When the mantissa (both the high-order and the low-order
portions) of the operation result is 0, then -128 is loaded
into EU and EL.
When the low-order mantissa, but not the high-order mantissa,
of the operation result = 0, then -128 is loaded into EL.
In any other case, EU -15 is loaded into EL.
In quadruple-precision arithmetic operations, an additional
digit (4 bits) called a guard digit, is assumed next to the
low-order position. An operation is performed in which the
intermediate result that includes the guard digit is
normalized. The high-order 124 bits are loaded into the EAQ
and LOR registers.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, SC, SCR, CI
I LLEGAL REPEATS:
RPT, RPD, RPL
8-422
DZ5l-00
QFAD
QFAD
I NDI CATORS :
NOTE:
Zero
-
If [C(AQ)O-63, C(LOR)8-71] = O,then ON;
otherwise, OFF
Negative
-
If C(A)O = 1, then ON: otherwise OFF
Exponent
Overflow
-
If exponent> +127, then ON
Exponent
Underflow
-
If exponent < -128, then ON
Illegal Procedure fault occurs when illegal address
modifications or illegal repeats are used.
An
(
(
8-423
DZ51-00
QFLD
QFLD
I
.
,,~/
QFLD
I
Quadruple-Precision Floating Load
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
[C(Y 4 words) --> C(EAQ, LOR)
432 C(E)
Bits 8-71 of C(Y 4 words) --> Bits 0-63 of C(AQ)
00 ••••• 0 --> bits 64-71 of C(AQ)
Bits 72-143 of C(Y 4 words) --> C(LOR)
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, SC, SCR, Cl
I LLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
Zero
-
If [C(AQ)0-71, C(LOR)l2-71'] = 0 ,then ON;
otherwise OFF
Negative
-
If C(A)O
NOTE:
= 1,
then ON; otherwise OFF
Illegal Procedure fault occurs when illegal address
modifications or illegal repeats are used.
An
8-424
DZ5l-00
QFMP
QFMP
462 (0)
Quadruple-Precision Floating Multiply
QFMP
FORMAT:
Single-word instruction format (see Figure 8-1).
OPERATI NG MODES:
Any
SUMMARY:
[C (EAQ,
EXPLANATION:
The exponent underflow indicator is not set when the
low-order exponent (EL) is in underflow (EU-1S < -128). At
this time, the correct value + 256 is loaded into EL and the
correct value into the low-order mantissa (ML - LOR8-7l).
LOR) x
C (y
4 words)] normal ized ->
C( EAQ,
LOR)
When the mantissa (both the high-order and the low-order
portions) of the operation result is 0, then -128 is loaded
into EU and EL'
When the low-order mantissa, but not the high-order mantissa,
of the operation result = 0, then -128 is loaded into EL.
In any other case, EU -15 is loaded into EL.
In quadruple-precision arithmetic operations, an additional
digit (4 bits), called a guard digit, is assumed next to the
low-order position. An operation is performed in which the
intermediate result which includes the guard digit are
normalized. The high-order 124 bits are loaded into the EAQ
and LOR registers.
I LLEGAL ADDRESS
NODI FI CATIONS:
DU, DL, SC, SCR, CI
ILLEGAL REPEATS:
RPT, RPD, RPL
(
8-425
_.
----------~--------~
. . . . -.
~~
DZS1-OO
QFMP
QFMP
I NDI CATORS:
NOTE:
= a,then
Zero
-
If [C(AQ)O-63, C(LOR)S-71]
otherwise, OFF
Negative
-
If C(A)O
Exponent
Overflow
-
If exponent> +127, then ON
Exponent
Underflow
-
If exponent < - 128, then ON
= 1,
ON;
then ON; otherwise OFF
An Illegal Procedure fault occurs when illegal address
modifications or illegal repeats are used.
8-426
DZ51-0a
QFSB
(
QFSB
Quadruple-Precision Floating Subtract
576
(0)
FORMAT:
Single-word instruction format (see Figure 8-1).
OPERATI NG MODES:
Any
SUMMARY:
[C (EAQ,
EXPLANATION:
The exponent underflow indicator is not set when the
low-order exponent (EL) is in underflow (EU-15 < -128). At
this time, the correct value + 256 is loaded into EL and the
correct value into the low-order mantissa (ML - LOR8-71).
LOR) - C(y 4 words») normalized -> C(EAQ, LOR)
~~en
the mantissa (both the high-order and the low-order
portions) of the operation result is 0, then -128 is loaded
into EU and EL.
When the low-order mantissa, but not the high-order mantissa,
of the operation result = 0, then -128 is loaded into EL.
In any other case, EU -15 is loaded into EL.
In quadruple-precision arithmetic operations, an additional
digit (4 bits), called a guard digit, is assumed next to the
low-order position. An operation is performed in which the
intermediate result that includes the guard digit is
normalized. The high-order 124 bits are loaded into the EAQ
and LOR registers.
During the operation, a two's complement of the subtrahend is
justified and added.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, SC, SCR, C!
1LLEGAL REPEATS:
RPT, RPD, RPL
8-427
QFSB
QFSB
/
I ND! CATORS:
NOTE:
Zero
-
If [C(AQ)O-63, C(LOR)S-71] =0 ,then ON;
otherwise, OFF
Negative
-
If C(A)O
Exponent
Overflow
-
I f exponent > +127, then ON
Exponent
Underflow
-
If exponent < - 128, then ON
= 1,
then ON: otherwise, OFF
An Illegal Procedure fault occurs when illegal address
modifications or illegal repeats are used.
8-428
DZ51-00
QFST
QFST
QFST
Quadruple-Precision Floating Store
FORMAT:
single-word instruction format (see Figure 8-1).
PROCEDURE MODE:
Any
SUMMARY:
[C(EAQ, LOR} --> C(Y 4 words}] normalized
453 (O)
C(E} --> bits 0-7 of C(Y 4 words)
Bits 0-63 pf C(AQ) --> bits 8-71 of C(Y 4 words)
Bits 64-71 of C(AQ) are ignored
C(LOR} --> bits 72-143 of C(Y 4 words)
(
ILLl!XiAL ADDRESS
MODI FI CATIONS:
DU, DL, SC, SCR, CI
I LLl!XiAL REPEATS:
RPT, RPD, RPL
I NDr CATORS :
None affected
NOTE:
An Illegal Procedure fault occurs when illegal address
modifications or illegal repeats are used.
8-429
DZ51-00
QFSTR
QFSTR
QFSTR
Quadruple-Precision Floating Store Rounded
FORMAT:
single-word instruction format (see Figure 8-1)
PROCEDURE MODE:
Any
SUMMARY:
[Bits 0-63 of C(AQ), bits 12-71 of C(LOR)] rounded,
normalized --> C(Y-pair)
EXPLANATION:
Arithmetic operation procedure
[C(AQ)O~63
466 (0)
+ carry] normalized --> C(Y-pair)
If C(AQ, LOR) is positive then carry
=0
If C(AQ, LOR) is negative;
if C(LOR}13-71
= 0,
if C(LOR)13-71
~
then carry
0, then carry
=0
= C(LOR}12
Using the above processing, positive and. negative data with
an equal absolute value are rounded to glve values with equal
absolute value.
If the mantissa of the result
in C(Y-pair)0-7.
=0
by rounding, -128 is stored
ILLEGAL ADDRESS
MODI PI CATIONS:
DU, DL, SC, SCR, CI
ILLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
zero
-
If C(Y-pair)8-71
otherwise, OFF
Negative
-
If C(Y-pair)a
Exponent
Overflow
-
If exponent> +127, then ON
Exponent
Underflow
-
If exponent < -128, then ON
NOTE:
= O,then
= 1,then
ONi
ON; otherwise, OFF
An Illegal Procedure fault occurs when illegal address
modifications or illegal repeats are used.
8-430
DZ51-00
\,,-j
QLR
QLR
QLR
'.(
"
Q-Register Left Rotate
776 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
EXPLANATION:
Rotate C(Q) left by the number of positions indicated by bits
11-17 (NS mode) or 27-33 (ES mode) of Y (y modulo 128).
Enter each bit leaving bit position 0 of Q into bit position
35 of Q.
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPL
INDICATORS:
Zero
-
If CO changes during the shift, then ON;
otherwise, OFF. When the carry indicator is
ON, the algebraic range of Q.has been exceeded.
NOTE:
= 0, then ON; otherwise, OFF
CO = 1, then ON; otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-432
DZ5l-00
I
QRL
QRL
QRL
(
Q-Register Right Logical Shift
772 (0)
FORMAT:
single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
EXPLANATION:
Shift C right by the number of positions indicated by bits
11-17 or 27-33 (ES mode) of Y (y modulo 128). Fill vacated
positions with bit 0 of C(Q). The shift count in the
instruction must be a decimal number.
I LLEGAL ADDRESS·
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPL
INDICATORS:
zero
-
If C(Q)
Negative
-
If
NOTE:
= 0, then ON; otherwise, OFF
C(Q)O = I, then ON; otherwise, OFF
Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
./
An
8-434
DZ51-00
,
QSMP
QSMP
QSMP
Quadruple-Precision Floating Multiply
with Double-Precision Operands
460 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATl NG MODES:
Any
SUMMARY:
[C(EAQ) x C(Y 4 words)] normalized --> C(EAQ, LOR)
EXPLANATION:
The exponent underflow indicator is not set when the
low-order exponent (EL) is in underflow (EU-15 < -128). At
this time, the correct value + 256 is loaded into EL and the
correct value into the low-order mantissa (ML - LOR8-71).
When the mantissa (both the high-order and the low-order
portions) of the operation result is 0, then -128 is loaded
into EU and EL.
When the low-order mantissa, but not the high-order mantissa,
of the operation result = 0, then -128 is loaded into EL.
(
In any other case, EU -15 is loaded into EL.
In quadruple-precision arithmetic operations, an additional
digit (4 bits), called a guard digit, is assumed next to the
low-order position. An operation is performed in which the
intermediate result which includes the guard digit are
normalized. The high-order 124 bits are loaded into the EAQ
and LOR registers.
The 72 bits of C(AQ)0-71 are used for the mantissa of the
multiplicand.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, SC, SCR, CI
ILLEGAL REPEATS:
RPT, RPD, RPL
8-435
DZ51-00
QSMP
QSMP
I NDI CATORS:
NOTE:
Zero
-
If [C(AQ)O-63, CO.QR)8-7l1 = O,then ON:
otherwise, OFF
Negative
-
If C(A)O
Exponent
OVerflow
-
I
Exponent
Underflow
-
I f
= 1,
then ON; otherwise, OFF
f exponent > +127, then ON
exponent < - 128, then ON
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-436
DZ51-00
(
RCW
RCW
Read Connect Word Pair
250 (O)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode
SUMMARY:
C (Connect
Queue Entry)
->
C (AQ)
If the queue is empty
o -->
C(AQ)
The SCU selected is the control SCU.
(
EXPLANATION;
The SCU is selected by the control SCU bit.
configuration register in Section4.)
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, 0,
ILLEGAL REPEATS:
RPD, RPL, and RPT
I NDI CATORS:
zero
-
Negative NOTES:
(Refer to SCU
If C(A) = 0, then ON; otherwise, OFF
If C(A)O = 1, then ON; otherwise, OFF
1.
An Illegal Procedure fault occurs' if illegal address
modification or an illegal repeat is used.
2.
An
IPR fault occurs if this instruction is executed in
Master or Slave modes.
3. The SCU connect masks are not applied.
4. Bound checks on the address are not made.
8-437
DZ51-00
RET
RET
IRFr
630 (0)
Return
~--------~--------------------------------------------~--------~
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(Y)0-17 --> C(IC)
C(Y)18-32 --> C(IR)
C(Y)33-35 are ignored
C(Y) unchanged
EXPLANATION:
This instruction loads the content of the location specified
by y into the instruction counter and indicator register with
bit 29 = O. The RET instruction does not load the
instruction segment register (ISR) and the SEGID(IS). The
return is then within the current instruction segment. The
RET instruction may be thought of as an 101 instruction
followed by a transfer to the location specified by C(Y)0-17.
The relation between the bit positions of C(Y) and the
indicators is as follows:
C{Y) Bit Position
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33-35
Indicator (or Mask)
zero
Negative
carry
Overflow
Exponent overflow
Exponent underflow
Overflow mask
Tally runout
Parity error
Parity mask
Master mode
Truncation
Multiword instruction interrupt
Reserved for exponent underflow mask
Hexadecimal exponent mode
000
8-438
DZ5l-00
RET
RET
(
With unconditional transfer of control instructions, bit 29 of
the instruction word affects the operation as follows:
o When bit 29 of the instruction word = 0, the ISR and
SEGID(IS) are not affected. An IPR fault does not occur.
o When bit 29 of the instruction word = 1, and if any form
of indirect addressing is specified in the tag field, then
the base, bound, and working space from DR!! (not the ISR)
are used in developing the addresses of indirect words.
When the transfer instruction attempts to load the ISR, the
ISR bit 24 (NS/ES mode specification bit) cannot be altered.
If bit 24 of the ISR before execution of the transter does not
equal to bit 24 of the segment descriptor from the DRg, an IPR
fault occurs. The ISR bit can be altered only with the CLIMB
instruction.
(
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, a, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
Master mode - If C(Y)28 is 1, then no change: otherwise, OFF
All other
indicators
NOTES:
- If corresponding bit in C(Y)
otherwise, OFF
is 1,
then ON;
1.
Overflow Fault does not occur when the overflow
indicator, exponent overflow indicator, or exponent
underflow indicator is set ON via the RET instruction, even
if the Overflow Mask Indicator is OFF.
2.
An
An
Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
(
8-439
DZSl-OO
RET
RET
3. A Security Fault, Class 2 occurs if instruction bit 29=1
and the instruction attempts to load the ISR from a
descriptor for which flag bit 25=0.
4. A Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 27=0.
5. A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 28=0.
8-440
DZS1-00
(
R1MR
RIMR
RIMR
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Privileged Master mode
SUMMARY:
Port interrupt level masks --> C(A)0-7
All mask
-->
C(A)8
Port connect mask
-->
C(A)9
0 ••• 0
(
233 (0)
Read Interrupt Mask Register
-->
C(A)10-35
EXPLANATION:
This instruction reads the masks in the SCU corresponding to
the issuing port; the All Mask is also read.
ILLEGAL ADDRESS
MODI F1 CATIONS:
DU DL, a, SC, and SCR
I
I
LLEGAL REPEATS:
RPT, RPD, RPL
I
ND1 CATORS:
None affected
NOTES:
1. The SCU is selected by the control SCU bit.
2. An IPR fault occurs when an attempt is made to execute
this instruction in Slave or Master mode.
3. An Illegal Procedure fault occurs if illegal address
modification or an illegal repeats are used.
8-441
DZ5l-00
RIW
RIW
/'
Read I nterrupt Word Pair
RIW
412 CO)
FORMAT:
single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode
SUMMARY:
I
f an unmasked interupt queue in the SCU has an entry then,
C(Word Pair from queue) --> C(AQ)
I f no unmasked queue has an entry then,
0 •.• 0
EXPLANATION:
-->
C(AQ)
If any unmasked interrupt queue in the control S:U has an
entry, then the contents of the entry from the interrupt queue
are moved into the AQ register. The entry from the
interrupt queue contains the level number. If there is no
unmasked queue from an entry, then zeros are moved into the AQ
register.
The SCU interrupt-connect mask register (ICMR) allows masking
of each port's interrupts and connects. Queues are maintained
in the SCU for each of the eight interrupt levels. The queues
are circular, first-in/first-out priority. No CPU address
information is used.
I LLEGAL ADDRESS
MODIFICATION:
DU,
I LLEGAL REPEATS:
RPD, RPL,
INDICATORS:
Zero
-
If C(A)
Negative
-
If
NOTES:
DL,
1.
An
2.
An
CI
RPT
= 0, then ON; otherwise OFF
C(A)O = 1, then ON; otherwise OFF
IPR fault occurs if this instruction is executed in
Master or Slave mode.
IPR fault occurs if illegal address modification or an
illegal repeat is used.
3. Bound checks on the address are not made.
8-442
DZSl-OO
\
)
RMID
RMID
RMID
Read Memory ID Register
273 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode
SUMMARY:
C(Memory ID Register)
EXPLANATION:
This instruction provides program access to the memory ID
register. SCU selection is based on the Control SCU bit (22)
in the CPU mode register.
-->
C(AQ)
Address development is followed
select the correct memory unit.
that is selected by the address
physical ID or logical ID based
configuration register.
and transferred to the SCU to
The physical memory unit
is dependent upon the SCU's
on the setting of the SCU
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, 0, SC, SCR
ILLEGAL REPEATS:
RPD, RPL, RPT
INDICATORS:
None affected
NOTES:
1. An IPR fault occurs if execution is attempted in the Slave
or Master mode.
2. An IPR fault occurs if illegal address modification or an
illegal repeat is used.
(
8-443
DZ5l-00
RMR
RMR
RMR
Read Memory Register
270 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode
SUMMARY:
C(Memory Status Register)
-->
C(AQ)
0 ••• 0 --> C(Memory Status Register)
EXPLANATION:
This instruction provides program access to the memory status
register. This register consists of 8 bits (40-47) in a
72-bit register. (Refer to "Memory Error Status Register" in
Section 4.) SCU selection is based on the control SCU bit in
the CPU mode register.
Address development is followed and transferred to the SCU to
select the memory unit. The memory unit is selected by
physical ID or logical ID based on the setting of the SCU
configuration register.
I
/
/
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, 0, sc, SCR
ILLEGAL REPEATS:
RPD, RPL, RPT
INDICATORS:
None affected
NOTES:
1.
An IPR fault occurs if execution is attempted in the Slave
or Master mode.
2.
An
IPR fault occurs if illegal address modification or an
illegal repeat is used.
8-444
DZ51-00
(
RPAT
RPAT
RPAT
611 (0)
Run PATROL
FORMAT:
single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode and Master mode; NS mode only
EXPLANATION:
This instruction operates like the DIS instruction. When
PATROL is enabled, a full cycle of all test pages is run.
The sampling for interrupts at completion of each test page
is not done. Upon completion of the full cycle, the CPU
returns to the execution of the next instruction.
When PATROL is disabled, no operation takes place.
continues with the next instruction.
I LLEGAL ADDRESS
MODIFICATIONS:
(
I LLEGAL REPEATS:
I
NDI CATeRS:
NOTES:
The
CPU
None. Modification is performed, including modification of
any indirect words specified. However, the effective address
has no effect on the operation, including the final value of
the instruction counter.
RPT, RPD, RPL
None affected
1. A Command fault occurs if execution is attempted in the
Slave or Master modes.
2.
IPR fault occurs if this instruction is executed in ES
mode.
3.
An
An
IPR fault occurs if illegal repeats are executed.
(8-445
DZ51-00
RPD
RPD
RPD
Repeat Double
560 (0)
FORMAT:
1 1
000 0 1 1
TERM. CONDo
Op
Code
2 2 223
3
560(0)
OPERATING MODES:
Executes in NS mode only
CODI NG FORMAT:
RPD N,I,kl,k2, ••• ,k7. (A=B=C=l.) The command generated by
the assembler from this format will cause the two
instructions immediately following the RPD instruction to be
iterated N times and the effective addresses of those two
instructions to be incremented by the value I for each of N
iterations. The meaning of the termination conditions of
kl,k2, ••• ,k7 are the same as for the RPT instruction. Since
the repeat-double must fall in an odd location, the assembler
will force this condition and a NOP instruction is used for a
filler when needed.
RPDX ,I. (A=B=C=O.) This instruction operates just as the
RPD instruction with the exception that A,B,N and the
conditions for termination are loaded by the user into index
register zero.
RPDA N,I,kl,k2, ••• ,k7. (A=C=l. B=O.) This instruction
operates just as the RPD instruction with the exception that
only the effective address of the first instruction following
the RPDA instruction will be incremented by the value of I
for each of N iterations.
RPDB N,I,kl,k2, ••• ,k7. (A=O. B=C=l.) This instruction
operates just as the RPD instruction with the exception that
only the effective address of the second instruction
following the RPDB instruction will be incremented by the
value I for each of N iterations.
EXPLANATION:
The instructions from the next Y-pair are fetched and saved
in the processor; they are executed repeatedly until a
specified termination condition is met.
8-446
DZ51-00
RPD
RPD
1. The RPD instruction must be stored in an odd memory
location except when accessed via the XEC or XED
instructions. In this case, the RPD instruction can be
either even or odd, but the XEC or XED instruction must be
in an odd memory location.
2. If C = 0, the tally and terminate conditions are loaded
from XO/GXO.
NS Mode
Tally, terminate condition
= C(XO)0-17
ES Mode
Tally, terminate condition
C(GXO)0-17 unchanged
= C(GXO)18-35
3. If C = 1, then bits 0-17 of the RPD instruction are loaded
into XO/GXO.
NS Mode
Bits 0-17 of the RPD instruction --> C(XO/GXO)
ES Mode
Bits 0-17 of the RPD instruction --> C(GXO>18-35
00 •••• 0 --> C(GXO)0-17
4. The terminate condition(s) and tally from Xo control the
repetition for the instructions following the RPD
instruction. An initial tally of zero is interpreted as
256. A fault also causes an exit from the cycle.
5. The repetition cycle consists of the following steps:
a. Execute the pair of repeated instructions.
b. C(XO)0-7 - 1 --> bits 0-7 of C(XO)
or C(GXO)l8-25 - 1 --> C(GXO)l8-25
c. If a terminate condition is met, set the Tally Runout
indicator OFF and exit.
(
8-447
DZ5l-00
RPD
RPD
d. If bits 0-7 of C(XO) or bits 18-25 of C(GXO) = 0, set
the Tally Runout indicator ON and exit.
e. If conditions in c. or d. are not met, go to a.
6. Many instructions cannot be repeated. If an instruction
cannot be repeated, an illegal repeat causes on IPR fault
to occur. Refer to the individual instruction
descriptions to determine whether or not a particular
instruction can be repeated.
7. Address modification for the pair of repeated instructions
is as follows.
For each of the two repeated instructions, only the
modifiers Rand RI and only the designators specifying
Xl, ••• ,X7/GX1, ••• ,GX7 are permitted. Address register
modification is also permitted. All other modifier
designations result in an IPR fault.
When the effective address for R modification is Y, and
when the indirect word address for RI modification is
YI, the address is determined as follows.
a. When
AR
modification is not indicated (bit 29 =
0)
o For the first execution of each of the two repeated
instructions:
Y + C(R) --> Yl or YIl
Y1 or YI1 --> C(R)
o For any subsequent execution of the two repeated
instructions:
For the first instruction of the pair
If A=l, then DELTA
+
C(R) --> Yn or YIn
Yn or YIn --> C(R)
If A=O, then C(R) --> Yn or YIn' where n>l
For the second instruction of the pair
If B=l, then DELTA + C(R) --> Yn or YIn:
Yn or YIn --> C(R)
8-448
DZ51-00
RPD
RPD
(
If B=O, then C(R) --> Yn or YIn' where n>l
b. When AR modification is indicated (bit 29 = 1)
a
For the first execution of each of the two repeated
instructions:
(se)Y
+
C(R)
(se)Y
+
C(R) --> C(R)
+
C(ARm) -> Y1 or Yll
(se) is the extended address with bit 3 of y.
ARm is the address register m selected by
instruction bits 0, 1, 2.
o For any subsequent execution of the two repeated
instructions:
For the first instruction of the pair
(
If A=l, then DELTA + C(R) + C(ARm) --> Yn or
YIn;
DELTA
+
C(R) --> C(R)
If A=O, then C(R)
+
C(AR) --> Yn or YIn
For the second instruction of the pair
If B=l, then DELTA + C(R) + C(ARm) -> Yn or
Yl n
DELTA + C(R) --> C(R)
If B=O, then C(R) + C(ARm) -> Yn or Yl n
A and B are the contents of the XO bits 8 and 9 or
the GXO bits 26 and 27.
(
8-449
DZ51-00
RPD
RPD
When RI modification is specified in the repeated
instruction, indirect reference is performed only
once for each repeat. The tag field of the indirect
word is ignored and processed as R modification (R =
N) •
8. The Exit Conditions:
exit is made from the repeat cycle if one of the
terminate conditions exists or if tally = 0 after the
execution of the odd instruction of the repeated pair.
Also, an exit is made when a fault occurs.
An
The program-controlled exit conditions are:
a. Tally = 0
b. Terminate Conditions:
The bit configuration in bit positions 11-17 of the RPD
instruction defines the terminate conditions. If more
than one condition is specified, the repeat terminates
if anyone of the specified conditions is met.
The carry, negative, and zero indicators each use two
bits, one for the OFF condition and one for ON. A zero
in both positions for one indicator causes this
indicator to be ignored as a terminate condition. A 1
in both positions causes an exit after the first
execution of the repeated instruction pair.
Bit
17 = 0:
Ignore all overflows. The respective
overflow indicator is not set ON, and
an Overflow fault does not occur.
Bit
17
= 1:
Process overflows. If overflow mask
indicator is ON when an overflow
occurs, then exit from the repetition
cycle. If the overflow mask indicator
is OFF when an overflow occurs, then
an Overflow fault occurs.
8-450
.DZ5l-00
/i
(
RPD
RPD
Bit
16
Bit
15
Bit
14
Bit
13
= 1:
= 1:
= 1:
= 1:
Bit
12
= 1: Terminate if zero indicator
Bit
11
= 1:
Terminate if carry indicator is OFF.
Terminate if carry indicator is ON.
Terminate if negative indicator is OFF.
Terminate if negative indicator ON.
OFF.
Terminate if zero indicator ON.
c. Overflow Fault:
If bit 17 = 1 and an overflow occurs with the overflow
mask indicator OFF, an Overflow fault occurs and an
exit is made from the repetition cycle after the
execution of the current instruction when the fault
processor returns control.
A non-program-controlled exit from the repetition cycle
occurs if any fault other than an Overflow occurs. If
any fault (Overflow, Divide Check, Parity error on
indirect word or operand fetch, etc.) occurs on the
even instruction, the odd instruction will not be
executed.
9. Status at termination of repeat
Bits 0-7 of C(XO} or bits 18-25 of C(GXO} contain the
tally residue (i.e., the number of repeats remaining until
a tally runout would have occurred). The terminate
conditions in bits 11-17 remain unchanged.
If the exit was due to tally = 0 or a terminate condition,
the Xn/GXn specified by the designator of each of the two
repeated instructions will contain either:
a. The contents of the designated Xg/GXn after the last
execution of the repeated pair plus the DELTA
associated with each instruction, as A or B, the DELTA
designators (bits 8 and 9 of XO) = 1, or
8-451
DZ5l-00
RPD
RPD
b. The contents of the designated Xg/GKg after the last
execution of the repeated pair if A or B, respectively,
is zero.
10. When XOO-7/GK018-25 contain zeros and the terminate
condition is not satisfied, the tally runout indicator set
to ON: otherwise, it is set to OFF.
I LLEGAL ADDRESS
MODIFICATIONS:
None. Address modification is not executed.
ignored.
Bit 29 is
ILL]!X;AL REPEATS:
RPT, RPD, RPL
INDICATORS:
The RPD instruction itself does not affect any of the
indicators. However, the execution of the repeated
instructions may affect indicators. The repeat mode entered
as a result of the instruction affects the Tally Runout
indicator.
NOTES:
1.
repeat-double of instructions that have long execution
times may cause a Lockup fault (LUF) if the time involved
is greater than the lockup time interval, which may be 2,
4, 8, or 16 milliseconds.
A
2. The repeated instruction must be modified by an index
register.
3. The following conditions cause an IPR fault to occur.
o If illegal repeats are used.
o If the repeated instruction uses
XO/~O.
o If R or RI modification is attempted with the repeated
instruction with other than Xl-X7/GKl-GX7.
o If the RPD instruction (or the XEC instruction
accessing the RPD instruction) is not at an odd
location.
'\,
)
8-452
DZ5l-00
(
RPD
RPD
If the exit was due to a fault, the Xn/GXn specified by
the designator of each of the two repeated instructions
may contain either:
a. The contents of the designated xn/GXn when the fault
occurred plus the DELTA associated with each
instruction A and B = 1, or
b. The contents of the designated Xn/GXn when the fault
occurred.
EXAMPLE:
I
8
16
EAX6
EAX7
FROM
TO
100,2
0,6
0,7
RPD
,
LDAQ
STAQ
EVEN
FROM
TO
BSS
BSS
200
200
8-453
DZ51-00
RPL
RPL
500(0)
Repeat Link
RPL
FORMAT:
o
0 0 011
1 1
TERM.
Op
Code
2 2 2 2 3
3
500(0)
CONDo
OPERATING MODES:
Executes in NS mode only
CODING FORMAT:
RPL N,kl,k2, ••• ,k7. (C = 1.) This format causes the
instruction immediately following the RPL instruction to be
repeated N times or until one of the conditions specified in
kl, ••• ,k7 is satisfied, or until the link address of zero is
detected. The range of N is 0-255. If N = 0, the instruction
will be iterated 256 times. If N is greater than 255, the
instruction will cause an error flag (A) to be printed on the
assembly listing. The fields kl, k2, ••• , k7 mayor may not
be present. They represent conditions for termination which,
when needed, are declared by the conditional transfer
instructions TMI, TNC, TNZ, TOV, TPL, TRC, and TZE. These
instructions affect the termination condition bits in
position 11-17 of the Repeat instruction.
octal number can be used rather than the transfer
instructions to denote termination conditions. Thus, if the
field for kl, k2, ••• , k7 is found to be numeric, it will be
interpreted as octal, and the low-order 7 bits will be ORed
into bit positions 11-17 of the Repeat instruction. The
variable field scan is terminated with the octal field.
An
RPLX (C = O). This instruction operates just as the RPL
instruction except that N and the conditions for termination
are loaded by the user into index register zero.
EXPLANATION:
The next instruction is executed either a specified number of
times until a specified termination condition is met, or
until the link address of zero is detected.
8-454
DZ5l-00
(
RPL
RPL
1. If C = 0, the tally and terminate conditions are those
loaded from XO/GXO.
NS Mode
Tally, terminate condition
= C(XO)O-17
ES Mode
Tally, terminate condition
= C(GKO)18-35
C(GKO )0-:-17 is unchanged
2. If C
= 1,
then bits 0-17 of the RPL instruction--> C(XO)/(GKO)
NS Mode
Bits 0-17 of the RPD instruction --> C(XO/GKO)
ES Mode
Bits 0-17 of the RPD instruction --> (GKO)18-35
(
00 ••• 0 --> C(GXO)0-17'
3. The terminate condition(s) and tally from XO control the
repetition for the instruction following the RPL
instruction. An initial tally of zero is interpreted as
256. A fault also causes an exit from" the cycle.
4. The repetition cycle consists of the following steps:
a. Execute the repeated instruction.
b. C bits 0-7 of C(XO)
or C(GXO}18-25 -1 --. > C(GKO)18-35'
c. If a terminate condition is met, set the Tally Runout
indicator OFF and exit.
d. If bits 0-7 of C(XO) or bits 18-25 of C(GXO} = 0, or
the link address bits 0-17 of C(Y) = 0 and no terminate
condition is met, set the Tally Runout indicator ON and
exit.
(
e. If conditions in c. or d. are not met, the effective
address C(Y} is used as a link address to determine the
C(Y) to be used in the next iteration. Go to a.
8-455
DZ51-00
RPL
RPL
5. Many instructions cannot be repeat-linked. I f an
instruction cannot be repeated, an illegal repeat causes
an IPR fault to occur. Refer to the individual
instruction descriptions to determine whether or not a
particular instruction can be repeated.
6. Address modification for the repeated instruction is as
follows.
Only address register (AR) modification and R modification
specifying Xl-X7/GX1-GX7 are permitted for repeated
instructions.
R modification is valid only for the first execution of
the repeated instruction, AR modification is valid for all
executions.
The effective address is generated as follows.
a. When
AR
modification is not indicated (bit
29 =
0)
o For the first execution of the repeated instruction
Yl
= yl
+
Yl
-->
C(R)
C(R)
o For each successive execution of the repeated
instruction
Yn
= C(Yn-l)O-17
Yn --> C(R)
8-456
(when YnO-17 does not contain zeros)
DZ51-00
RPL
RPL
b. When AR modification is indicated (bit 29
= 1)
o For the first execution of the repeated
instruction
Y1 = (se)y
(se)y
+
+
C(R)
C(ARm)
+
C(R) --> C(R)
(se)y is the extended address with bit 3 of y.
is the address register m selected by
instructions bits 0, 1, 2.
ARm
o For each successive execution of the repeated
instruction
Yn = C(Yn-1)0-l7
+
C(AR)
C(Yn-l)0-17 --> C(R)
when YnO-17 does not contain zeros
The effective address Y is the address of the next
list word. The lower portion of the list word
contains the operand to be used for this execution
of the repeated instruction.
The operand is handled in one of the following
formats.
Bits 0-17:
00 ••• 0
Bits 18-35: C{Y)18-35 for single-precision (1
word)
or as
Bits 0-17:
00 ••• 0
Bits 18-71: C{Y}18-71 for double precision (2
words)
The upper 18 bits of the list word contain the link
address; that is, the address of the next successive
list word, and thus the effective address for the
next successive execution of the repeated
instruction.
8-457
DZ51-00
RPL
RPL
/
7. Repeat Exit Conditions:
exit is made from the repeat cycle if one of the
terminate conditions exists or if tally = 0 or link
address = 0 after the execution of the repeated
instruction. Also, an exit is made when a fault occurs.
An
The program-controlled exit conditions are:
a. Tally = 0
b. Link Address
=0
c. Terminate Conditions:
The bit configuration in bit positions 11-17 of the RPL
instruction defines the terminate conditions. If more
than one condition is specified, the repeat terminates
if any of the specified conditions is met.
The carry, negative, and zero indicators each use two
bits, one for the OFF condition and one for ON. A zero
in both positions for one indicator causes this
indicator to be ignored as a terminate condition. A 1
in both positions causes an exit after the first
execution of the repeated instruction.
Bit
17
= 0:
Ignore all overflows. The respective
overflow indicator is not set ON, and
an Overflow fault does not occur.
Bit
17
= 1:
Process overflows. If the overflow
mask indicator is ON when an overflow
occurs, exit from the repetition
cycle. If the overflow mask indicator
is OFF when an overflow occurs, then
an Overflow fault occurs.
Bit
16
Terminate if carry indicator is OFF.
Bit
15
= 1:
= 1:
Bit
14
= 1:
Terminate if negative indicator is
OFF.
Bit
13
= 1:
Terminate if negative indicator is
ON.
Terminate if carry indicator is ON.
8-458
DZ51-00
""\
RPL
RPL
(
= 1:
Bit
12
Bit
11 = 1:
Terminate if zero indicator is OFF.
Terminate if zero indicator is ON.
d. Overflow Fault:
If bit 17 = 1 and an overflow occurs with the overflow
mask indicator OFF, an Overflow fault occurs and an
exit is made from the repetition cycle when the fault
processor returns control.
A non-program-controlled exit from the repetition cycle
occurs if any fault other than an Overflow occurs
(Divide Check, Parity error on indirect word or operand
fetch, etc.).
8. Status at termination of repeat
Bits 0-7 of C(XO) or bits 18-25 of C(GXO) contain the
tally residue (i.e., the number of repeats remaining until
a tally runout would have occurred). The terminate
conditions in bits X01l-17/GX029-35 remain unchanged.
The Xn/GXn specified by the designator of the repeated
instruction contains the address of the list word that
contains:
a. In its lower-half, the operand used in the last
execution of the repeated instruction
b. In its upper-half, the address of the next list word.
9. When XOO-7/GX018-25 contain zeros, or when the link
address {Y)0-17 contains zeros, and the terminate
condition is not satisfied, the Tally runout indicator is
set to ON; otherwise, it is set to OFF.
10.
ILLEGAL ADDRESS
MODIFICATIONS:
I
LLEGAL REPEATS:
exit will not occur if the effective address is 0 for
the first execution of the linked instruction. This
address specifies the location of the first word in the
link table and is not interpreted as a link address.
An
None. Address modification is not executed.
ignored.
Bits 29-35 are
RPT, RPD, RPL
(
8-459
DZ5l-00
RPL
RPL
I NDI CATeRS :
TheRPL instruction itself does not affect any of the
indicators. However, the execution of the repeated
instruction may affect the indicators. The repeat mode
entered as a result of the instruction affects the tally
runout indicator.
NOTES:
1. The repeated instruction must be modified by an index
register.
2. The following conditions cause an Illegal Procedure fault.
o I f illegal repeats are used.
o If the repeated instruction uses
xo/mw.
o If other than AR or R modification is attempted with
the repeated instruction.
o If R modification other than Xl-X7/GX1-GX7 is attempted
with the repeated instruction.
EXAMPLE:
S
16
EAX7
A
LDQ
CMK
=0777777,DU
=3HIDD,DL
S,TZE
0,7
TNZ
ERROR
A
VFD
lS/B,H1S/IDA
B
VFD
lS/C,H1S/IDB
C
VFD
lS/D,H1S/IOC
D
VFD
lS/E,H1S/IDD
E
VFD
lS/O,H1S/IDE
1
LDA
RPL
S-460
DZS1-00
RPT
RPT
(
520
Repeat
RPT
(O)]
FORMAT:
o
1 1
7 8
0 0 011
TERM. CONDo
(
I
Op
Code
520(0)
2 222 3
6 7 890
II II
DELTA
3
5
I
OPERATING MODES:
Executes in NS mode only
CODING FORMAT:
RPT N,I,kl,k2, ••• ,k7. (Bit C=l.) The command generated by
the assembler from this format will cause the instruction
immediately following the RPT instruction to be iterated N
times and that instruction's effective address to be
incremented by the value I for each of N iterations. The
range for N is 0-255. If N = 0, the instruction will be
iterated 256 times. If N is greater than 256, the instruction
will cause an error flag (A) to be printed on the assembly
listing. The fields kl,k2, ••• k7 mayor may not be present.
They represent conditions for termination which, when needed,
are declared by the conditional transfer instructions TMI,
TNC, TNZ, TOV, TPL, TRC, and TZE. These instructions affect
the termination condition bits in positions 11-17 of the
Repeat instruction. See discussion of terminate conditions
below.
In addition, an octal number can be used rather than the
transfer instructions to denote termination conditions.
Thus, if the field for kl,k2 ••• ,k7 is found to be numeric, it
will be interpreted as octal and the low-order 7 bits will be
ORed into bit positions 11-17 of the Repeat instruction. The
variable-field scan will be terminated with the octal field.
RPTX ,I (Bit C = 0). This instruction operates just as the
RPT instruction with the exception that N and the conditions
for termination are loaded by the user into bit positions 0-7
and 11-17, respectively, of index register zero (instead of
being embedded in the instruction).
<:
8-461
DZ51-00
RPT
RPT
EXPLANATION:
The next instruction is executed either a specified number of
times or until a specified termination condition is met.
1. If C = 0, the tally and terminate conditions are those
loaded from XO/GXO.
NS Mode
Tally, terminate condition
= C(XO)0-17
ES Mode
Tally, terminate condition
= C(GXO)18-35
C(GXO)0-17 unchanged
2. If C = 1, then bits 0-17 of the RPT instruction are loaded
into C(XO)/(GXO}.
NS Mode
Bits 0-17 of the
RPT
instruction --> C(XO/GXO)
ES Mode
Bits 0-17 of the RPT instruction --> (GXO)18-35
00--0 --> C(GXO)0-17
3. The terminate condition(s) and tally from XO control the
repetition for the instruction following the RPT
instruction. An initial tally of zero is interpreted as
256. A fault also causes an exit from the cycle.
4. The repetition cycle consists of the following steps:
a. Execute the repeat instruction.
b. C(XO)0-7 - 1 --> bits 0-7 of C(XO)
or C(GXO)18-25 - 1 --> C(GXO)18-25
c. If a terminate condition is met, set the tally runout
indicator OFF and exit.
d. If bits 0-7 of C(XO) or bits 18-25 of C(GXO)
the tally runout indicator ON and exit.
= 0,
set
e. If conditions in c. or d. are not met, go to a.
8-462
DZ51-00
RPT
RPT
(
5. Many instructions cannot be repeated. For such
instruc~ions, an illegal repeat causes an IPR fault to
occur. Refer to the individual instruction descriptions
to determine whether or not a particular instruction can
be repeated.
6. Address modification for the repeated instruction is as
follows.
For the repeated instruction, only the modifiers Rand RI
and only the designators specifying Xl, ••• ,X7/GXl, ••• ,GX7
are permitted. Address register modification is also
permitted.
All other modifier designations result in an IPR fault.
When the effective address for R modification is Y, and
when the indirect word address for RI modification is YI,
the address are determined as follows.
When AR modification is not indicated (bit 29 = 0)
a. For the first execution of the repeated instruction:
(/
Y + C(R) --> Yl or YIl
Yl or YIl --> C(R)
b. For each successive execution of the repeated
instruction
DELTA
+
C(R) --> Yn or YIn
Yn or YIn --> C(R)
DELTA is bits 30 to 35 of the RPT instruction.
(_.
8-463
DZ51-00
RPT
RPT
When AR modification is indicated (bit 29 = 1)
a. For the first execution of the repeated instruction
(se)Y + C(R) + C(ARm) --> Yl or Y1l
(se)Y + C(R) --> C(R)
(se) is the extended address with bit 3 of y.
ARm is the address register m selected by instruction
bits 0, 1, 2.
b. For any subsequent execution of the the repeated
instruction
DELTA + C(R) + C{ARm) --> Yn or YIn
DELTA + C(R) --> C(R)
When RI modification is specified in the repeated
instruction, indirect reference is performed only once
for each repeat. The tag field of the indirect word is
ignored and processed as R modification (R = N).
7. Repeat Exit Conditions:
An exit is made from the repeat cycle if one of the
terminate conditions exists or if tally = 0 after the
execution of the odd instruction of the repeated pair.
Also, an exit is made when a fault occurs.
The program-controlled exit conditions are:
a. Tally
=0
8-464
DZ5l-00
RPT
RPT
(
b. Terminate Conditions:
The bit configuration in bit positions 11-17 of the RPT
instruction defines the terminate conditions. If more
than one condition is specified, the repeat terminates if
any of the specified conditions is met.
The carry, negative, and zero indicators each use two
bits, one for the OFF condition and one for ON. A zero
in both positions for one indicator causes this indicator
to be ignored as a terminate condition. A 1 in both
positions causes an exit after the first execution of the
repeated instruction pair.
(
Bit
17
= 0:
Ignore all overflows. The respective
overflow indicator is not set ON, and
an Overflow fault does not occur.
Bit
17
= 1:
Process overflows. If the overflow
mask indicator is ON when an overflow
occurs, exit from the repetition cycle.
I f the overflow mask indicator is OFF
when an overflow occurs, an Overflow
fault occurs.
Bit
16 = 1: Terminate if carry indicator is OFF.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
= 1:
= 1:
= 1:
= 1:
= 1:
Terminate if carry indicator is ON.
Terminate if negative indicator is OFF.
Terminate if negative indicator is ON.
Terminate if zero indicator is OFF.
Terminate if zero indicator is ON.
c. Overflow Fault:
If bit 17 = 1 and an overflow occurs with the Overflow
Mask indicator OFF, an Overflow fault occurs and an
exit is made from the repetition cycle when the fault
processor returns control.
A non-program-controlled exit from the repetition cycle
occurs if any fault other than Overflow occurs.
8-465
DZ5l-00
RPT
RPT
8. Status at termination of repeat
Bits 0-7 of C(XO) or bits 18-25 of C(GXO) contain the
tally residue
C(SCU Register)
In VMS Privileged Master mode,. if both SCU ports are enabled
and the least-significant bit of the effective address (word
address) is 1, the control SCU bit is temporarily changed to
permit selection of the non-control SCU. (Reference section 4
for CPU configuration register and ASR control.) The control
SCU bit is then reset to its original value.
Real Memory Address:
0 ••• 21
Bits
22-24
25-27
Function
X ••• X
0
X
Not used
X ••• X
1
X
Configuration
X ••• X
2
X
Fault
X ••• X
3
X
History
X ••• X
4
X
calendar Clock
X ••• X
5
X
Not used
X ••• X
6
X
Syndrome
X ••• X
7
X
Not used
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, 0, SC, SCR
I LLEGAL REPEATS:
RPD, RPL, RPT
INDICATORS:
None affected
",
8-468
DZ51-00
RSCR
RSCR
(
NOTES:
1. A Command fault occurs if address bits 22-24 are 0, 5, or 7
(octal).
2. A Command fault occurs if execution is attempted in Slave
or Master mode.
3. The SCU registers are defined in Section 4.
4. Bits 25-27 of the configuration register are the SCU port
number. These bits must be zero in an SSCR instruction, in
order that a subsequent RSCR instruction returns the port
number; otherwise, the OR of bits 25-27 and the port number
are returned.
5.
IPR fault occurs if illegal address modification or
illegal repeats are executed.
An
8-469
DZ5l-00
RSW
RSW
RSW
231 (0)
Read Processor Model Characteristics
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUHMARY:
C(model char.)
0 ••• 0
-> C(A)
->
C(A)0-3
Processor type --> C(A)4-6 (DPS 8000 type
= 101)
Test Mode Register Bit 13 (Transfer Trace Mode) -> C(A)30
1 = enable
Performance submodel type --> C(A)31-32
CPU Number
EXPLANATION:
-->
C(A)33-35
This instruction reads system model characteristics previously
set by the firmware and loads them into the A register.
The submodel field is interpreted as follows:
C(A)31-32
Performance
00
1,5
01
2.3
10
3.0
11
Undefined
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, Rt, IR, IT
ILLEGAL REPEATS:
None
I NDI CATORS:
None affected
NOTES:
1. Address development occurs but has no effect on the
execution of this instruction.
2. Additional model characteristics may be defined by the
firmware.
I
3. An IPR fault occurs if illegal address modification is
executed.
8-470
DZS1-00
j
S4BD
S4BDX
S4BD
S4BDX
S4BD
S4BDX
Subtract 4-Bit Displacement from Address Register
522 (1)
special arithmetic instruction format (see Figure 8-3)
FORMAT:
CODI NG FORMAT:
1
16
8
{S4BD 1
{s4BDxl word displacement,R,AR
OPERATI NG MODES:
Any
EXPLANATION:
Description is the same as for A4BD except that y and C(DR)
are added and the sum is subtracted from the content of ARn.
When the mnemonic is cOded with an X (S4BDX), bit 29 is
forced to O. If bit 29 is 0, the content of ARn is assumed
as o.
(
ILLEGAL ADDRESS
MODIFICATIONS:
If DU, DL, or Ie are specified in DR.
ILLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
EXAMPLES:
1
Applies to
~S
mode only
8
16
32
EAX3
S4BDX
S4BD
10
2,3,4
0,3,4
AR4 octal contents
AR4 octal contents
-
7777746 0
77777 340
EAX6
S4BDX
S4BD
7
3,6,2
0,6,2
AR2 octal contents
AR2 octal contents
-
77777 405
77777 320
(
8-471
DZ5l-00
S6BD
SGBDX
S6BD
S6BDX
/
S6BD
S6BDX
Subtract 6-Bit Displacement from Address Register
521 (1)
Special arithmetic instruction format (see Figure 8-3)
FORMAT:
CODI NG FORMAT:
8
1
16
{S6BD }
{S6BDX} word displacement,R,AR
OPERATI NG MODES:
Any
EXPLANATION:
Description is the same as for A6BD except that y and C(DR)
are added and the sum is subtracted from the content of ARn.
When the mnemonic is coded with an X (S6BDX), bit 29 is
forced to zero. If bit 29 is 0, the content of ARn is
assumed as O.
-
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, or IC specified in DR.
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTE:
An I Hega1 Procedure fault occurs if illegal address
modifications or illegal repeats are used.
,
,~
EXAMPLES:
1
Applies to NS mode only
8
16
32
EAX5
SGBDX
S6BD
14
0,5,2
2,5,2
AR2 octal contents
AR2 octal contents
--
7 7 7 7 7 546
7 7 7 7 7 1 2 3
EAX6
SGBDX
SGBD
5
1,6,7
0,6,7
AR7 octal contents
AR7 octal contents
--
7 7 7 7 7 6 0 5
7 7 777 523
8-472
DZ51-00
(
S9BD
S9BDX
S9BD
S9BDX
I
II
:i
11
I'
I
S9BD
S9BDX
Subtract 9-Bit Displacement from Address Register
520 (1)
Special arithmetic instruction format (see Figure 8-3)
FORMAT:
CODING FORMAT:
8
1
16
{S9BD }
{S9BDX} word displacement,R,AR
OPERATI NG MODES:
Any
SUMMARY:
Description is the same as for A9BD except that y and C(DR)
are added and the sum is subtracted from the content of ARn.
When the mnemonic is coded with an X (S9BDX), bit 29 is
forced to zero. If bit 29 is 0, the content of ARn is
assumed as O.
-
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, or I C sped tied in DR.
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
EXAMPLES:
1
Applies to NS mode only
8
16
32
EAX7
S9BDX
S9BD
9
1,7,5
1,,5
AR5 octal contents
AR5 octal contents
-
7777746 0
77777 360
EAX2
S9BDX
S9BD
7
2,2,6
0,2,6
AR6 octal contents
AR6 octal contents
-
7 7 7 7 7 420
777 7 7 2 4 0
8-473
DZ5l-00
SARn
SARn
Store Address Register
n
Single-word instruction format (see Figure 8-1)
FORMAT:
CODING FORMAT:
1
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
8
16
SAR£
LOCSYM,R,AM
For n=0,1, •• ,7 as determined by op code
C(ARn) --> C(Y)0-23: C(Y)24-3S, C(ARn) unchanged
ES
Mode
For n=0,1, •• ,7 as determined by op code
C(ARn) -> C(Y), C(ARn) unchanged
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPT, "RPD, RPL
INDICATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
EXAMPLES:
1
Applies to NS mode only
8
16
32
SARS
ADDRWS
o0
1 7 5 0 2 7 ARS contents
1
o0
1 7 5 0 2 7 x x x x memory after
ADDRWS BSS
8-474
DZSl-OO
(
SAREG
SAREG
Store Address Registers
SAREG
Single-word instruction format (see Figure 8-1)
FORMAT:
CODI NG FORMAT:
1
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
8
16
SAREG
LOCSYM,R,AR
C(ARO,ARl, ••• ,AR7) --> C(Y,Y+l, ••• ,Y+7)O-23
Zeros --> C(Y,Y+l, ••• ,Y+7)24-35
ES Mode
C(ARO,ARl, ••• ,AR7) --> C{Y,Y+l, ••• ,Y+7)
The lower 3 bits of Yare assumed as 000 and the 8 words
beginning from the 8-word boundary are accessed for storage.
No check is performed to determine whether the lower 3 bits
of Yare actually 000.
EXPLANATION:
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
EXAMPLE:
1
8
16
SAREG
REGWS
EIGHT
REGWS BSS
32
8
8-475
DZ51-00
SB2D
SB2D
Subtract Using Two Decimal Operands
SB2D
203 (1)
FORMAT:
00
1 1
0011
Op
Code
222
3
203(1)
MF2
a a
a 2
1 1
7 8
2 2
a1
MFl
222
2 3
234
3
9 0
5
Yl
CNl
a
Sl
SFl
Nl
Yl
AR#
a
TNl
1 1
7 8
0
2
2 2
0 1
222
2 3
9 0
234
3
5
Y2
CN2
AR#
CaDI NG FORMAT:
TN2 S2
SF2
N2
Y2
The SB2D instruction is coded as follows:
1
8
16
SB2D
NDSC!!
NDSC!!
(MF1),(MF2),RD,P,T
LOCSYM,CN,N,S,SF,AM
LOCSYM,CN,N,S,SF,AM
(Refer to Section 7 under Multiword Instructions for description
of Multiword Modification Field.)
OPERATI NG MODES:
Any
8-476
DZ51-00
SB2D
SB2D
SUMMARY:
C(string 2) - C(string 1)
EXPLANATION:
same as SB3D except that the difference is stored using YC2,
TN2, S2, and, if S2 indicates a scaled format, SF2.
-->
C(string 2)
The zero indicator is set when the decimal number is zero; it
does not indicate that all bits are zeros.
Refer to AD3D, for a description of justifying the scaling
factors.
Independent of the data type being used (either packed
decimal or 9-bit numeric; floating-point or scaled)
significant digits in the result may be lost if:
1. The difference between the scaling factors (exponents) of
the source operands is large enough to cause the expected
length of the intermediate result to exceed 63 digits
after decimal-point alignment of source operands, followed
by subtraction.
2. The result field as defined by the result descriptor is
not large enough to contain the calculated result after it
has been aligned.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MFI and MF2
I LLEGAL REPEATS:
RPT,
RPD, RPL
I NDI CATORS:
Zero
-
If result equals zero, then ON; otherwise, OFF
Negative
-
If result is negative, then ON; otherwise, OFF
Truncation -
Exponent
Overflow
(-
If, in the preparation of the final result,
one or more least significant digits (zero or
nonzero) are lost and rounding is not
specified, then ON; otherwise (i.e., no least
significant digits lost or rounding is
specified), OFF
If exponent of floating-point result is > 127,
then ON; otherwise, unchanged
/
8-477
DZSI-OO
SB2D
SB2D
Exponent
Underflow
-
If exponent of floating-point result is <
-128, then ON: otherwise, unchanged
Overflow
-
Iff ixed-point in':eger, or internal register
overflow, then ON ~ otherwise, unchanged
1. Truncation fault same as for AD3D.
NOTES:
2. Illegal Procedure fault same as for MVN.
3. If an illegal digit or sign is detected, part or all of
the receiving field may be changed before the IPR fault
occurs.
EXAMPLES:
Applies to NS mode only
1
FLD1
FLD2
FLD1
FLD2
8
16
32
SB2D
NDSC4
NDSC9
USE
, ,1
FLDl,O,4,2,-3
FLD2,O,8
CONST.
4P125+
8A+6543.2l
with rounding option
subtrahend operand descriptor
minuend operand descriptor
memory contents
125 +
+ 6 5 4 3 2 1 -2
+ 6 5 4 3 0 9 -2 (Result)
SB2D
NDSC4
NDSC9
USE
, , ,1
FLD1,0,8,3,-4
FLD2,0,8,3,-2
CONST.
with truncation enable option
subtrahend operand descriptor
minuend operand descriptor
memory contents
EDEC
EDEC
8P12345678
8A8765432l
EDEC
EDEC
USE
USE
*INSTRUCTION FAULT?
YES
12345678
87654321
87530864
WHAT KIND?
8-478
/'
"--
(Result)
truncation fault
DZ51-00
SB2DX
SB2DX
(
SB2DX
243
Subtract Using Two Decimal Operands Extended
(1)
FORMAT:
1 1
7 8
1 1
o1
0 0 0
0 1 2
MF2
Icslxsloo------------ool
0
0
1 1
7 8
0
2
Yl
CNl
243(1)
2 2
o1
222
789
5
H
222
234
TNl SXl
3
NFl
2 3
9 0
SFl
I
3
5
Nl
Yl
AR#
o
o
I
Op Code
1 1
7 8
0
2
2 2
0 1
222
234
2 3
3
5
9 0
Y2
CN2
AR#
CODl NG FORMAT:
TN2 SX2
SF2
N2
Y2
1
8
16
SB2DX (MF1),(MF2),RD,CS,T,NS
NDSCn LOCSYM, CN , N, SX , SF, AM
NDSCn LOCSYM,CN,N,SX,SF ,AM .
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
8-479
DZ51-00
SB2DX
SB2DX
\~" J
OPERATl NG MODES:
Any
SUMMARY:
C(string2) -
EXPLANATION:
same as for SB3DX except that the difference is stored using
YC2, TN2, SX2 and, if SX2 indicates a scaled format, SF2.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL for NFl or MF2
I LLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
same as for AD3DX
NOTES:
1. All notes for AD3DX apply to SBZDX.
~(stringl) -->
C(string2)
2. See MVNX for information about coding of overpunched
signs.
8-480
DZ5l-00
SB3D
SB3D
-
If
,;
Subtract Using Three Decimal Operands
SB3D
223 (1)
FORMAT:
0
a
o0
1 2
Ip
H
0
0
0
2
001 1
890 1
HRDI
MF3
1 1
7 8
MF2
Op
222
789
Code
I
223(1)
1 122
7 801
222
234
II I
3
5
MF1
2 3
9 0
I
3
5
Y1
CN1 TNI Sl
a
o
SF1
N1
Y1
AR#
(
I
it
1 122
7 801
0
2
222
234
2 3
9 0
3
5
Y2
CN2 TN2 S2
N2
Y2
AR#
o
o
SF2
1 122
7 801
0
2
222
234
2 3
9 0
3
5
Y3
CN3 TN3 S3
AR#
CODI NG FORMAT:
SF3
N3
Y3
The SB3D instruction is coded as follows:
1
8
16
SB3D
NDSCn
NDSCn
NDSCn
(MF1),(MF2),(MF3),RD,P,T
LOCSYM,CN,N,S,SF,AM
LOCSYM,CN,N,S,SF,AM
LOCSYM,CN,N,S,SF,AM
(
8-481
DZS1-00
SB3D
SB3D
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
OPERATI NG MODES:
lmy
SUMMARY:
C(string 2) - C(string 1) --> C(string 3)
The decimal number of data type TN1, sign and decimal type
Sl, and starting location YC1, is subtracted from the decimal
number of data type TN2, sign and decimal type S2, and
starting location YC2. The difference is stored starting in
location YC3 as a decimal number of data type TN3 and sign
and decimal type S3.
If S3 indicates a fixed-point format, the results are stored
using scale factor SF3, which may cause leading or trailing
zeros (4 bits - 0000, 9 bits - 000110000) to be supplied
and/or most-significant-digit overflow or
least-significant-digit truncation to occur.
If S3 indicates a floating-point format, the result is
right-justified to preserve the most significant nonzero
digits even if this causes least-significant truncation.
If P=1, positive signed 4-bit results are stored using octal
13 as the plus sign. If P=O, positive signed 4-bit resu1ts_
are stored with octal 14 as the plus sign. If RD is a 1,
rounding takes place prior to storage.
Provided that strings 1, 2, and 3 are not overlapped, the
contents of the decimal numbers that start in locations YCl
and YC2 remain unchanged.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MFl, MF2, and MF3
I LLEGAL REPEATS:
RPT,
INDICATORS:
same as for SB2D
NOTES:
1. Truncation fault same as for AD3D.
RPD, RPL
2. Illegal Procedure fault same as for MVN.
3. The zero indicator is set when the decimal number is zero.
)
8-482
DZSl-OO
SB3D
SB3D
(
4. Independent of the data type being used (either packed
decimal or 9-bit numeric; floating-point or scaled)
significant digits in the result may be lost if:
a. The difference between the scaling factors (exponents)
of the source operands is large enough to cause the
expected length of the intermediate result to exceed 63
digits after decimal-point alignment of source
operands, followed by subtraction
b. The result field as defined by the result descriptor is
not large enough to contain the calculated result after
it has been aligned
5. If an illegal digit or sign is detected, part or all of
the receiving field may be changed before the IPR fault
occurs.
EXAMPLES: Applies to NS mode only
1
FLOl
FLD2
FLD3
1
FLDl
FLD2
FLD3
8
16
32
SB3D
NDSC4
NDSC4
NDSC9
USE
EDEe
EDEC
BSS
USE
, , ,1
FLD1,O,4,2
FLD2,O,4,l
FLD3,3,5
CONST.
4P1234P-123
2
with rounding option
subtrahend operand descriptor
minuend operand descriptor
operand descriptor for result field
memory contents
123-123
X X X + 0 0 0 +127
(Result)
zero indicator ON
8
16
32
SB3D
NDSC9
NDSCS
NDSC4
USE
EDEe
EDEC
BSS
USE
FLD1,O,8
FLD2,O,8
FLD3,O,8,l,-2
CONST.
8A-123456E-3
8A-987654E-3
with truncation enable option
subtrahend operand descriptor
minuend operand descriptor
result operand descriptor
memory contents
- 1 2 3 4 5 6 -3
- 9 8 7 6 5 4 -3
-0086419 (Result)
indicators on? - negative and truncation
1
8-483
DZ5l-00
SB3DX
SB3DX
263
Subtract Using Three Decimal Operands Extended
SB3DX
(1)
FORMAT:
0 o 0
0 1 2
HHSI
0
1 1
o1
1 1
7 8
I
MF3
I
MF2
1 1
7 8
0
2
0
Op Code
263(1)
2 2
o1
222
789
3
5
III
222
234
MFI
2 3
9 0
I
3
5
Yl
CNl
SFI
Nl
Yl
AR#
o
o
TNI SXl
1 1
7 8
0
2
2 2
0 1
222
234
2 3
9 0
3
5
Y2
CN2
SF2
N2
Yl
AR#
o
o
TN2 SX2
1 1
0
2
7 8
2 2
0 1
222
234
2 3
9 0
3
5
Y3
CN3
AR#
CODING FORMAT:
TN3 SX3
SF3
N3
Y3
1
8
16
SB3DX (MF1),(MF2),(MF3),RD,CS,T,NS
NDSCn LOCSYM, CN , N,SX, SF, AM
NDSCn LOCSYM,CN,N,SX,SF,AM
NDSCn LOCSYM, CN , N, SX, SF , AM
8-484
DZ51-00
SB3DX
SB3DX
(
I
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
I
I
OPERATI NG MODES:
Any
SUMMARY:
C(string 2) - C(string 1) --> C(string 3)
EXPLANATION:
The decimal number of data type TN1, sign and decimal type
SXl, and starting location YC1, is subtracted from the
decimal number of data type TN2, sign and decimal type SX2,
and starting location YC2. The difference is stored starting
in location YC3 as a decimal number of data type TN3 and a
sign and decimal type SX3.
!
I
If SX3 indicates a fixed-point format, the difference is
stored using scale factor SF3, which may cause leading or
trailing zeros (4 bits - 0000, 9 bits - 000110000) to be
supplied and/or most-significant-digit overflow or
least-significant-digit truncation to occur.
If SX3 indicates a floating-point format, the result is
right-justified to preserve the most-significant-nonzero
digits even if this causes least-significant truncation. The
character set is defined by CS. Placement of overpunched
sign in the output is controlled by NS. (Refer to definition
of NS in introductory pages of this section.)
(
If
RD
= 1,
rounding takes place prior to storage.
Provided strings 1, 2, and 3 are not overlapped, the contents
of the decimal numbers that start in locations YC1 and YC2
remain unchanged.
ILLEGAL ADDRESS
MODIFICATIONS:
I
LLEGAL REPEATS:
I
DU, DL for NFl, MF2, or MF3
RPT, RPD, RPL
I NOI CATORS:
Same as for AD3D
NOTES:
1. All notes for AD3D apply to SB3DX.
2. See MVNX for information about coding of overpunched
signs.
(
8-485
DZ5l-00
SBA
SBA
/
SBA
Subtract from A-Register
175 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(A) - C(Y) -> C(A); C(Y) unchanged
I LLEGAL ADDRESS
MODI FI CATIONS:
None
I LLEGAL REPEATS:
None
I
NDI CATORS:
Zero
-
If C(A) = 0, then ON; otherwise, OFF
Negative
-
If C(A)O
Overflow
-
I f range of A is exceeded, then ON
carry
-
If a carry out of bit 0 of C(A) is generated,
then ON: otherwise, OFF
= 1,
8-486
then ON: otherwise, OFF
DZ51-00
SBAQ
SBAQ
SBAQ
Subtract from AQ-Register
177 (0)
I
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(AQ) - C(Y-pair) --> C(AQ): C(Y-pair) unchanged
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, a, SC, SCR
I LLEGAL REPEATS:
None
I NDI CATORS :
Zero
-
If C(AQ) = 0, then ONi otherwise, OFF
Negative
-
If C(AQ)O
Overflow
-
I f range of AQ is exceeded, then ON
carry
-
If a carry out of bit 0 of C(AQ) is generated,
then ON: otherwise, OFF
NOTE:
= 1,
then ON: otherwise, OFF
Illegal Procedure fault occurs if illegal address
modification is used.
An
(~/
8-487
DZ51-00
SBAR
SBAR
'\
/
SBAR
Store Base Address Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(BAR)
->
550 (0)
C(Y)0-17
C(Y)18-35 unchanges
EXPLANATION:
The relationship between C(Y) and the BAR follows.
Bits
Interpretation
0-7
Base Address/l024
8
Not used
9-16
(Unrelocated Address Limit)/I024
17
Not used
"\
The base address is a zero modulo 1024 word address that is
the first valid address allocated to the slave program. The
unrelocated address limit is a zero modulo 1024 word address
that is the first invalid address relative, relative to the
base address, beyond the memory space allocated to the slave
program. (The unrelocated address limit/l024 is also the
quantity of 1024-word blocks allocated to the slave program.)
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, sea
I LLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
None
NOTE:
An I llegal Procedure fault occurs if illegal address
modifications or illegal repeats are executed.
8-488
DZ51-00
(
SBD
SBDX
SBD
SBDX
SBD
Subtract Bit Displacement from Address Register
SBDX
523 (l)
Special arithmetic instruction format (see Figure 8-3)
FORMAT:
CODING FORMAT:
8
1
{SDB }
{SBDXl
16
word displacement,R,AR
OPERATI NG MODES:
Any
EXPLANATION:
Description is the same as for ABD except that y and C(DR)
are added and the sum is subtracted from the AR.
When the mnemonic is coded with an X (SBDX), bit 29 is forced
to zero. If bit 29 is 0, the content of ARn is assumed as O.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, and IC specified in DR.
I LLEGAL REPEATS:
RPT RPD RPL
INDICATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
EXAMPLES:
1
I
I
Applies to NS mode only
8
16
32
EAXI
48
2,1,6
0,1,6
AR6 octal contents AR6 octal contents -
7 7 7 7 7 4 4 6
7 7 7 7 7 3 2 3
75
1,2,3
0,2,3
AR2 octal contents AR2 octal contents -
7 7 7 7 7 4 6 6
7 7 7 7 7 2 6 3
SBDX
SBD
EAX2
SBDX
SBD
('
8-489
DZ51-00
SBL]..
SBLA
/~\
/
SBLA
Subtract Logical from A-Register
135
(0)
I
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(A) - C(Y) -> C(A): C(Y) unchanged
EXPLANATION:
This instruction is identical to SBA except that the overflow
indicator is not affected and an Overflow fault does not
occur. Operands and results are treated as unsigned,
positive binary integers.
ILLEGAL ADDRESS
MODI FI CATIONS:
None
ILLEGAL REPEATS:
None
INDICATORS:
Zero
-
Negative
carry
If
-
= 0, then ON; otherwise, OFF
C(A)O = 1, then ON; otherwise, OFF
If C(A)
If a carry out of bit 0 of C(A) is generated,
then ON: otherwise, OFF. When the carry
indicator is OFF, the range of A has been
exceeded.
8-490
DZ51-00
(
SBLAQ
SBLAQ
SBLAQ
Subtract Logical from AQ-Register
137 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(AQ) - C(Y-pair) -> C(AQ); C(Y-pair) unchanged
EXPLANATION:
This instruction is identical to SBAQ except that the
overflow indicator is not affected and an Overflow fault does
not occur. Operands and results are treated as unsigned,
positive binary integers.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
None
INDICATORS:
Zero
-
If C(AQ)
Negative
-
If C(AQ)O
carry
-
If a carry out of bit 0 of C(AQ) is generated,
then ON; otherwise, OFF. When the carry
indicator is OFF, the range of AQ has been
exceeded.
NOTE:
= 0,
= 1,
then ON: otherwise, OFF
then ON; otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modification is used.
8-491
DZ51-00
SBLQ
SBLQ
SBLQ
Subtract Logical from Q-Register
136 (O)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Any
SUMMARY:
C(Q} - C(Y) --> C(Q}; C(Y} unchanged
EXPLANATION:
This instruction is identical to SBQ except that the overflow
indicator is not affected and an Overflow fault does not
occur. Operands and results are treated as unsigned,
positive binary integers.
I LLEGAL ADDRESS
MODI FI CATIONS:
None
I LLEGAL REPEATS:
None
I NDl CATORS:
Zero
-
If C(Q)
Negative
-
If C(Q)o
carry
= 0,
= 1,
then ON; otherwise, OFF
then ON; otherwise, OFF
If a carry out of bit 0 of C(Q) is generated,
then ON; otherwise, OFF. When the carry
indicator is OFF, the range of Q has been
exceeded.
8-492
DZ5l-00
j
(
SBLR
SBLR
SBLR
Subtract Logical Register from Register
437 (1)
FORMAT:
Not Used
CODING FORMAT:
222333,
1 1
000
1
OP CODE
8
16
SBa
R1, ,R2
OPERATING MODES:
Executes in ES mode only.
SUMMARY:
R1, R2
= 0,
1, 2, 3, 4, 5, 6, 7, A, Q
C(R1) - C(R2) --> C(R1}
C(R2) unchanged
ILLEGAL ADDRESS
MODIFICATIONS:
None.
I LLEGAL REPEATS:
RPT, RPD, RPL
The address modification is not executed.
ILLEGAL EKECUTES: Execution in NS mode
INDICATORS:
NOTES:
Zero
-
= 0, then ON; otherwise, OFF
C(R1}O = 1, then ON; otherwise, OFF
If C(R1}
Negative -
If
carry
If a carry out of bit 0 of C(R1) is generated,
then ON; otherwise, OFF
-
1. An I PR fault occurs if illegal repeats are executed or if
the instruction is executed in NS mode.
2. Refer to Register to Register Instructions in Section 7
for a description of the fields in the instruction word.
(
8-493
DZS1-00
SBLXn
SBLXn
Subtract Logical from Index Register n
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
NS
12!! (0)
Mode
For n
= 0,1, ••• ,
or 7 as determined by op code
C(Xn) - C(Y>0-17 --> C(Xn): C(Y} unchanged
ES Mode
For n
= 0,1, ••• ,
or 7 as determined by op code
C(GXn) - C(Y) --> C(GXn); C(Y} unchanged
EXPLANATION:
This instruction is identical to SBXn except that the
overflow indicator is not affected and an Overflow fault does
not occur. Operands and results are treated as unsigned,
positive binary integers.
ILLEGAL ADDRESS
MODIFICATIONS:
a,
ILLEGAL REPEATS:
RPT, RPD, RPL of SBLXO
I NDI CATeRS:
Zero
-
If C(Xn/GXg)
Negative
-
If C(Xn/GXn)o
carry
-
If a carry out of bit 0 of C(Xn/GXn) is
generated, then ON; otherwise, OFF
NOTES:
SC, SCR
= 0,
= 1,
then ON; otherwise, OFF
then ON; otherwise, OFF
1. If DL modification is specified in the NS mode, all data
is processed as O.
2.
Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
An
I
/'
8-494
DZ51-00
SSO
SBO
I
;
I
I
SBQ
subtract from Q-Register
176 (0)
FORMA'!':
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Any
SUMMARY:
C C is generated,
then ON; otherwise, OFF
= 0,
then ON: otherwise, OFF
= 1, then ON; otherwise, OFF
(
8-495
DZ51-00
I
SBRR
SBRR
/
SBRR
Subtract Register from Register
436 (1)
FORMAT:
000
Not Used
CODING FORMAT:
22233
1 1
1
OP CODE
8
16
SBRR
R1, ,R2
OPERATING MODES:
Executes in ES mode only.
SUMMARY:
R1, R2
= 0,
3
1, 2, 3, 4, 5, 6, 7, A, Q
C(R1) - C(R2)
--> C(R1)
C(R2) unchanged
I LLEGAL ADDRESS
MODIFICATIONS:
None.
ILLEGAL REPEATS:
RPT, RPD, RPL
/
The address modification is not executed.
ILLEGAL EXECUTES: Execution in NS mode
I NDI CATORS :
NOTES:
Zero
-
If C(R1) = 0, then ON; otherwise, OFF
= 1,
Negative -
If C(R1)0
Overflow -
If the range of R1 is exceeded, ON
carry
If a carry out of bit 0 of C(R1) is generated, then
ON; otherwise, OFF
1.
-
then ON; otherwise, OFF
IPR fault occurs if illegal repeats are executed or if the
instruction is executed in NS mode.
An
2. Refer to "Register to Register Instructions" in Section 7 for
a description of the fields in the instruction word.
,/
8-496
DZ51-00
SBXn
SBXn
,
II
Subtract from I ndex Register n
FORMAT:
single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
For n
= 0,
16n iO}
1, ••• ,7 as determined by op code
C(Xn) - C(Y)0-17 --> C(Xn): C(Y) unchanged
ES Mode
For n
= 0,
1, ••• ,7 as determined by op code
C(GXn) - C(Y) -> C(GXn): C(Y) unchanged
I LLEGAL ADDRESS
MODI FI CATIONS:
a,
I LLEGAL REPEATS:
RPT, RPD I RPL of SBXO
INDICATORS:
Zero
-
I f C (Xn/GXn) = 0 I then ON; otherwise I OFF
Negative
-
If C(XnGXn)o = 1, then ON; otherwise, OFF
Overflow
-
If range of Xn/GXn is exceeded, then ON
carry
-
If a carry out of bit 0 of C(xnGXn) is
generated, then ON: otherwise, OFF
NOTES:
SC, SCR
1. If DL modification is specified in the NS mode, all data
is processed as O.
2.
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
(~
8-497
DZ51-00
SCD
SCD
sa>
Scan Characters Double
120 (1)
FORMAT:
1 1
7 8
1 1
o1
0
0
MF2
1 00- - -0 1
I
0 o0
0 2 3
Code
3
5
H
120(1)
NFl
1 1 2 2 222
7 8 0 1 234
2 3
3
5
N1
00---------0
000
I
2 3 3
9 0 2
CNl TAl 0
Y1
AR#
222
789
1 1 2 2 222
7 8 o 1 234
Y1
o
Op
R1
233
902
3
5
Y2
CN2
Y2
AR#
o
o
not
interpreted
1 1 2 2 222
7 8 0 1 234
0 0
2 3
2 2 333
8 9 012
3
5
Y3
00---------------0 AR 00
AR#
CODING FORMAT:
REG
Y3
The SCD instruction is coded as follows:
1
8
16
SCD
ADSC!!
ADSCn
(MFl ) , (NF2)
ARG
LOCSYM, CN , N, AM
LOCSYM , CN I I AM
LOCSYM, RM I AM
8-498
DZ5l-00
(
SCD
SCD
(Refer to Section 7 under Mu1tiword Instructions for
description of Mu1tiword Modification Field.)
I
II
11
~ ..
I
OPERATI NG MODES:
Any
EXPLANATION:
When N1 = 0 or 1, starting at location YC1, L1-1 concatenated
pairs of type TAl characters are compared with the two
assumed type TAl characters that are either stored in
location YC2 and YC2 + 1 or contained in bits 0-7, bits 0-11,
or; when the REG field of MF2 specifies DU modification, bits
0-17 of the address field of operand descriptor 2.
The compare continues until an identical match is found or
until the Ll-1 tally is exhausted. A count of compares is
kept and for each unsuccessful match the count is incremented
by 1. When a match is found or the tally is exhausted, the
compare count is stored in bits 12-35 of Y3 and bits 0-11 of
Y3 are zeroed.
(
I
I LLEGAL ADDRESS
MODIFICATIONS:
DU, OL for MF1 or the Y3 REG field; OL for MF2
ILLEGAL REPEATS:
RPT, RPO, RPL
I NDI CATORS:
Tally
NOTES:
1. The RL bit in the MF2 field is not used.
-
If the tally (L1-1) is exhausted without a
successful match, then ON; otherwise, OFF
2. An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
(
8-499
OZ51-00
SeD
SCD
EXAMPLES:
1
8
seD
FLD1
FLD2
FLD3
1
16
32
ADSC6
ADSC6
ZERO
TTF
USE
BCI
BCI
BSS
USE
FLD1, ,6
FLD2,3
FLD3
8
16
HAVEl
CONST.
1,123456
1,654321
1
32
seD
ADSC6
ADSC6
DATA, ,24
COMPmm2
ARG
COUNT
*
*
DATA
BCI
BCI
COUNT BSS
COMP BCI
with no options
scanned string operand descriptor
character pair operand descriptor
FLD3 operand descriptor pointer
match found - tally runout OFF
characters compared
123456
32
unmatched count - 5
Result - no match found
with no options
24 characters fetched from lower DATA
in units of 2 chars. and compared with
HH.
when HH found in DATA, count stored as
binary number before HH detection and
instruction terminated.
.
2, AABBCCDDEEFF
2, GGHHIIJJKKLL
COUNT countains decimal 14
1
1,HH
8-500
DZ51-00
SCD
SCD
EXAMPLE WI TH ADDRESS MODI FI CATION:
1
16
EAX5
EAX7
EAX4
5
load 5 into X5
7
load 7 into X7
FLDl
load FLDl address into X4
0,4,4
put FLDl address into AR4
(l,l"S),(",DU) - with address modification
0,0,X7,4
FLOl operand pointer (FLD1+l,l,7)
AlB/45
FLD2 operand
FLD3
pointer to count FL03
*+2
no match found
match found
CONST.
characters compared
000001234567
l2Al234567
unmatched count - 3
o
Result - match found on 4th pair
AWOX
seD
ADSC9
FLD2
VFD
ARG
TTN
NULL
USE
FLDl
FLD3
32
B
EDEC
DEC
USE
(
8-501
DZ51-00
SCDR
SCDR
SCDR
Scan Characters Double in Reverse
FORMAT:
same as Scan Characters Double
CODING FORMAT:
The SCDR instruction is coded as follows:
1
8
16
SCDR
ADSCn
ADSen
(NFl), (NF2)
ARG
(SCI»
format
LOCSYM,CN,N,AM
LOCSYM, CN , ,AM
LOCSYM, RM, AM
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
OPERATI NG MODES:
Any
EXPLANATION:
same as for SCD except that start is at location YCl +
(L1-1) and pairs are scanned in reverse to location YC1.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MF1 or the Y3 REG field; DL for MF2
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS :
Tally
NOTES:
1. The RL bit in the MF2 field is not used.
2.
-
./
If the tally (L1-l) is exhausted without a
successful match, then ON; otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
"\
8-502
DZ51-00
SCDR
SCDR
(
EXAMPLES:
1
8
16
32
SCDR
ADSC9
,(",DU)
FLDl,0,8
U18/AB
FLD3
HAVEl
CONST.
2,ABCDE
1
DU modification of FLD2 operand descriptor
scanned string operand descriptor
FLD2 character pair - A B
pointer count word
match found - tally runout OFF
characters compared
A,B,C,D,E,l!\,l!\,l!\
unmatched count - 6
Result - match found on 7th pair
VFD
FLDI
FLD3
ARG
TTF
USE
UASCl
BSS
USE
EXAMPLE WI TH ADDRESS MODI FI CATION:
1
8
16
KO
K7
EQU
EQU
EAX2
EAX3
AWDX
SCDR
ADSC4
EDEC
ARG
TTN
NULL
USE
EDEe
BSS
USE
°17
ie
FLDI
FLD3
FLD1
0,3,4
( 1 , , , 2 ) , ( , , , DU )
0,KO,K7,4
2PL23
FLD3
OOPS
CONST.
8P123456
1
32
load FLD1 address into X3
put FLDI address into AR4
- with address modification
FLDI operand descriptor (FLO 1,1,7)
FLD2 operand descriptor pointer
pointer to count word
no match - tally runout ON
match found
characters compared
0123456 VS 23
unmatched count - 3
Result - match found on 4th pair
(
8-503
DZ51-00
SCM
SCM
SCM
124
Scan with Mask
(1)
FORMAT:
o
o0 1 1
890 1
1+1
1 1
7 8
I
MF2
Code
222
789
Y1
CN1 TAl
MF1
2 3 3
9 0 2
3
5
H1
0
Y1
00--
-0
1 1 2 2 222
7 8 0 1 234
000
023
3
H
120(1)
1 1 2 2 222
7 8 o 1 234
000
023
AR#
Op
R1
233
902
3
5
Y2
CN2
AR#
Y2
1 1 2 2 222
7 8 0 1 234
000
023
Y3
AR#
CODING FORMAT:
not
interpreted
2 2 333
8 9 012
00--------------------0 AR 00
3
5
REG
Y3
The SCM instruction is coded as follows:
1
8
16
SCM
(MF1), (MF2) ,MASK
LOCSYM, CN, N, AM
LOCSYM, CN , ,AM
LOCSYM, RM, AM
ADSQ!
ADSCn
ARG
8-504
DZ51-00
SCM
SCM
(
I
II
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
'1
",
i'l
I~
I~
OPERATI NG MODES:
Any
EXPLANATION:
Starting at location YC1, the Ll type TAl characters are
masked and compared with the assumed type TAl character
contained either in location YC2 or in bits 0-8 or 0-5 of the
address field of operand descriptor 2 (when the REG field of
MF2 specifies DU modification). The mask is right-justified
in bit positions 0-8 of the instruction word. Each bit
position of the mask that is a 1 prevents that bit position
in the two characters from· entering into the compare.
The masked compare operation continues until either a match
is found or the tally (Ll) is exhausted. For each
unsuccessful match, a count is incremented by 1. When a
match is found or when the Ll tally runs out, this count is
stored right-justified in bits 12-35 of location Y3 and bits
0-11 of Y3 are zeroed. The contents of location YC2 and the
source string remain unchanged. The RL bit of the MF2 field
is not used.
(
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MFl or Y3 REG field; DL for MF2
ILLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATeRS:
Tally
NOTES:
1. If Ll = 0, zero is stored in Y3 (bits 12-35) and the tally
indicator is affected.
-
If the tally (Ll) is exhausted without a
successful match, then ON; otherwise, OFF
2. If Ll ~ 0 and a match is found in the first character,
zero is stored in Y3 (bits 12-35) and the tally indicator
is set to OFF.
3.
Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
An
(
8-505
DZ51-00
i
1
SCM
SC~
(-\
~
EXAMPLES:
1
8
16
32
SCM
ADS:9
ADSC9
ARG
TTF
,,76O
FLD1,0,4
FLD2,3
FLD3
GOT .IT
mask to eliminate zone bits
character string operand descriptor
compare character operand descriptor
pointer to unmatched count word
match found
no match - tal1yrunout ON
octal representation of scanned characters
141 142 143 144 (before masking)
001 002 003 004
(after masking)
octal representation of compare character
064 (before masking)
004 {after masking}
unmatched compare count - 3
Result - match found on 4th character
NULL
FLD1
USE
ASCII
CONST.
l,ABCD
FLD2
FLD3
ASCII
BSS
USE
1,0004
1
SCM
ADSC4
EDEC
ARG
TTF
, ( , , , DU)
FLD1,3,5
8PL-l
FLD3
GOT .IT
NULL
FLD1
FLD3
EXAMPLE
~~TH
1
USE
EDEC
BSS
USE
CONST.
8P-1234
1
DU type REG modifier on FLD2
character string operand descriptor
FLD2's compare character pointer to unmatched count word
match found
no match - tally runout ON
character scanned
0,1,2,3,4
unmatched compare count - 5
Result - no match found
ADDRESS MODIFICATION:
32
8
16
EAXl
EAX2
1
load FLD2 character modifier into Xl
2
load FLDl character modifier into X2
FLDl
load FLDl address into X4
0,4,4
put FLD1 address into AR4
(1,1,1,2), (1, ,1,1) ,010 with all options
INOSC1
pointer to FLDl indirect descriptor
INDSC2
pointer to FLD2 indirect descriptor
FLD3
pointer to unmatched count word
oy
no match - tally runout ON
CONST.
character compared
8PL4321
2 1
4P0987
1
1
unmatched compare count - 1
0"X2,4
FLDl operand descriptor (FLD1,2,2)
FLD2,0
FLD2 operand descriptor (FLD2,l)
Result - match found on 2nd character
EAX4
AWDX
SCM
ARG
ARG
ARG
TTN
USE
FLD1 EDEC
FLD2 EDEC
FLD3 BSS
I NOSCl ADSC4
I NOSC2 ADSC9'
USE
8-506
DZ5l-00
/
(
SCMR
SCMR
SCMR
Scan with Mask in Reverse
FORMAT:
same as Scan with Mask (saO format
CODI NG FORMAT:
The SCMR instruction is coded as follows:
1
SCMR
ADSCn.
ADSCn.
ARG
125 (1)
16
8
(MFl),(MF2),MASK
LOCSYM,CN,N,AM
LOCSYM, CN , , AM
LOCSYM, RM, AM
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
OPERATI NG MODES:
Any
EXPLANATION:
same as SCM except starts at location YCl + (Ll-l) and
progresses toward location YC1.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MFl or the Y3 REG; DL for MF2
ILLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
Tally
NOTES:
1. If Ll = 0, zer9 is stored in Y3 (bits 12-35) and the tally
indicator is affected.
-
If the tally (Ll) is exhausted without a
successful match, then ONi otherwise, OFF
2. If Ll > 0 and a match is found in the first character,
zero is stored in Y3 (bits 12-35) and the tally indicator
is set to OFF.
3. The RL bit of the MF2 field is not used.
4. An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
(
8-507
DZ5l-00
SCMR
SCMR
EXAMPLES:
1
8
16
32
SCMR
,(",DU),760
FLDl,0,6
1P4
FLD3
*+2
DU type register modification with mask
character string operand descriptor
FLD2 t s compare character - 4
pointer to unmatched count word
match found
no match - tally runout ON
characters scanned
6,5,4,3,2,1
unmatched count - 3
Result - match found on 4th character
ADSC4
EDEC
ARG
TTF
NULL
FLD1
FLD3
USE
EDEC
DEC
USE
CONST.
8PL6543210
EXAMPLE WI TH ADDRESS MODI FI CATION:
1
FLD1
FLD3
FLD2
8
16
32
EAX6
EAX2
EAX4
AWDX
SCMR
ARG
ADSC4
ARG
TTN
TRA
USE
EDEC
DEC
ADSC4
EDEC
USE
6
2
FLD1
0,4,4
(1,1,1,2),,760
FLD3+1
FLD2,0
FLD3
OUCH
load FLD1 length into X6
load character modifier into X2
load FLD1 address into X4
put FLDl address into AR4
with all options
pointer to FLD1 indirect descriptor
pointer to compare character
pointer to unmatched count word
no match - tally runout ON
match found
characters compared
2,3,4,5,6,unmatched compare count - 4
FLD1 operand descriptor(FLD 1,2,6)
FLD2 compare character 3
Result - match found on 5th compare
WHEW
CONST.
8P01234560
0, ,X6, 4
4PL3
8-508
DZ51-00
/
"
(
SCPR
SCPR
SCPR
Store Central Processor Register
452 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode
SUMMARY:
C(CPU Reg.)
EXPLANATION:
This instruction selects CPU registers based upon the
instruction's tag field, and stores them in memory or loads
them into the A register
-->
C(Y-pair}, or
C(Y-Block 4), or
C(A), or
C(Y, Y+l, ••• Y+7)
The tags and register/operand stored are as follows:
Octal
~
(
Register/Operand
01
Fault Register
0 ..•. 0
03
Extended Fault Register
O•••• 0
06
CPU Mode Register
C(Y-Pair) Bits
0-35
36-71
0-7
8-71
Lockup Fault Register
0-35
36-53
54-61
62-69
70-71
10
Reserve Memory Base
0 ..•• 0
0-35
36-71
11
Port Configuration Register
0 ..•• 0
0-17
18-71
12
Address Trap Register
0-30
31-71
O•••• 0
cache Mode Register
O•••• 0
o..•. 0
(
8-509
DZ51-00
SCPR
SCPR
j
Octal
~
C(Y-Pair) Bits
Register/Operand
0-32
33-35
36-71
0 •••• 0
CPU Number Register
13
0 •••• 0
14
Virtual Address Trap Register
0 •••• 0
0-35
36-71
C(Y-Block) 4 Bits
History Register
20
0-35
36-58
59-71
72-79
80-107
108-143
0 •••• 0
History Register
O• ••• 0
History Register
0 •••• 0
C(Y,Y+1, ••• Y+7) Bits
Connect Table,
secondary Connect Table
07
0-143
144-287
The following tags load the contents of the cache
directory, PTWAM directory and PTWAM registers into the
A-register. The entry location is specified by the Y
address field in the instruction.
I
Tag
Ent~ Select
Column Level
15
Y3-14 Y2
cache Directory
0-35
16
Yll-16 Y17
P'l'WAM Register
0-35
17
Yll-16 Y17
PTWAM Directory
0-35
Ent~
ILLEGAL ADDRESS
MODIFICATIONS:
Tag field defines the operation.
I LLEGAL REPEATS:
RPD, RPL RPT
INDICATORS:
None affected
CCA} Bits
I
8-510
DZ51-00
,,_/
(
S~R
S~R
I"
II
NOTES:
1. A Command fault occurs if execution is attempted in Slave
or Master mode.
2. For SCPR tags 15, 16, and 17, if bit 29 is ON, C(AR) is
added to the Y field and the sum forms the entry select
value. The full virtual address development is not used.
3. The address trap register values are read from scratch
pad locations 66, 67 rather than from the register
itself.
4.
IPR fault occurs if illegal tag fields or illegal
repeats are executed.
An
(
(
8-511
DZ5l-00
I~
I
!
SDRn
SDRn
save Descriptor Register
~
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(DRn) -> Argument Stack (AS)
Argument stack bound
S~Dn
EXPLANATION:
HWMR
-->
(Refer to Explanation
item 4.)
is set to indicate the stored segment descriptor.
This instruction stores the descriptor from DRn in the next
available location of the argument stack, and adjusts the
argument stack bound and high water mark register (HWMR).
The y field of this instruction is not interpreted by the
hardware. No address bound checks are made. The argument
segment is the operand segment.
The instructions are executed as follows.
1. The following checks are performed.
a. The ASR (Argument Stack Register) flag bit 28 is
checked. If it is zero, the argument segment is not
present, a Missing Segment fault occurs, and the
instruction is terminated.
b. If the ASR bound + 8
generated.
~
8192 bytes, a BND fault is
2. If the conditions described under (1) are satisfied,
execution continues. It generates the effective byte
address indicating the next available double-word location
on the AS. The ASR flag bit 27 is then checked.
a. If the ASR flag bit 27 = 0, the argument segment is
empty. The ASR base indicates the first double-word
location.
b. If the ASR flag bit 27 = 1, ASR bound + base
executed to generate a virtual address.
+
1 is
NOTE: The descriptor is stored relative to the argmuent
stack bound. The HWMR does not influence this
storage location. (Refer to the description of the
ClJMB instruction for more information on the HWMR.)
8-512
DZSI-OO
(
SDRn
SDRn
3. After the DRn content has been stored in AS, the following
operations are executed and the instruction is completed.
If ASR bit 27 = 1, 8 is added to the ASR bound field.
It indicates that the new segment has been stored and
the segment size has increased.
If ASR bit 27 = 0, the argument segment indicates that
it was empty when the instruction was begun. The bound
field is then set to seven bytes to indicate that a
segment descriptor has been stored. The ASR flag bit
27 is set to 1 to indicate that this segment is no
longer empty.
b. SEGIDn is set to indicate the location in which the
segment descriptor is stored.
For example, if the ASR bound field is 117 (octal)
bytes (= 80 bytes = 20 words = 10 double-words) after 8
is added, S~Dn is set as follows.
S
D
2
9
.
.
Indicates the tenth segment
descriptor
Indicates the argument segment
4. The HWMR is set to indicate the maximum ASR bound
following any sequence of SDRn and PAS instructions.
I f the new ASR bound > C( HWMR), then the new ASR
bound --> C(HWMR).
I LLEGAL ADDRESS
MODIFICATIONS
DU, DL, RI, IR, IT
8-513
j
1,
a. The ASR flag bit 27 is checked.
(
\•
DZ51-00
SDRn
SDRn
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1. A Missing Working Space, Missing Segment, or Missing Page
fault may occur.
2. If a save is attempted to a nonhousekeeping page, a
security Fault, Class 1 occurs.
3.
BND fault occurs if the ASR bound + 1 byte
(before the ASR is updated).
An
4. A Security Fault, Class
violation is attempted,
have write permission.
required to have either
5.
~
8192 bytes
2 fault occurs if a working space
or if the specified page does not
The descriptor itself is not
write or store permission.
An Illegal Procedure fault occurs if illegal address
modification or illegal repeats are used.
8-514
DZ5l-00
SIW
SIW
SIW
t
451
Set Interrupt Word Pair
forma~
(0)
FORMAT:
Single-word instruction
OPERATING MODES:
Privileged Master mode
SUMMARY:
C(AQ)
EXPLANATION:
A double-word write occurs to the designated control SCU.
The SCU stores the double word in the level interrupt queue
and informs all of the receiving ports. The SCU looks at
bits 27-30 of the data to determine the interrupt queue
level. The eight queues are circular, first-in/first-out,
with queue lengths of 256 word pairs per port. If the queue
level number exceeds 256, a bit is set in the SCU fault
register.
-->
(see Figure 8-1)
C(Interrupt Queue)0-7l
ILLEGAL ADDRESS
MODI FI CATI ONS :
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPD, RPL, RPT
INDICATORS:
None affected
NOTES:
1. Prior to executing this instruction, the SCU must be
"selected" by using the LCPR instruction to set or reset
bit 22 in the CPU mode register.
2. An IPR fault occurs if illegal address modification or an
illegal repeat is used.
3. An IPR fault occurs if execution is attempted in Slave or
Master mode.
(
8-515
DZ5l-00
SMID
SMID
smD
Set Memory 1D Register
272 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERA'l'ING MODES:
Privileged Master mode
SUMMARY:
C(AQ)
EXPLANATION:
This instruction sets the memory 1D registers. The physical
memory unit that is selected by the address is dependent upon
the SCU' s physical 1D or logical 1D based on the setting of
the SCU configuration register.
->
C(Memory 1D Register)
ILLPX;AL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPD, RPL, RPT
INDICATORS:
None Affected
NOTES:
1.
scu
2.
An
3.
An IPR fault occurs if execution is attempted in Slave or
Master mode.
selection is based upon the control SCU bit in the CPU
mode register.
IPR fault occurs if illegal address modification or an
illegal repeat is executed.
8-516
DZ51-00
(
SMR
SMR
SMR
Set Memory Register
271 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode
SUMMARY:
C(AQ) inverted --> C(Memory Status Register)
EXPLANATION:
This instruction provides a means of setting the memory
status registers. SCU selection is based upon the control
SCU bit in the CPU mode register.
Address development is followed and transferred to the SCU to
select the memory unit. The physical memory unit that is
selected by the address is dependent upon the SCU's physical
ID or logical ID based on the setting of the SCU
configuration register.
LLEGAL ADDRESS
MODI Fl CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPD, RPL, RPT
I NDI CATORS :
None affected
NOTES:
1. An IPR fault occurs if illegal address modification or an
I
(
illegal repeat.is used.
2.
IPR fault occurs if execution is attempted in Slave or
Master mode.
An
3. The contents of the AQ register are inverted (one's
complement).
8-517
DZ5l-00
SPCF
SPCF
SPCF
set Pointer Compare Flags Off
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
1 -->
SD
251 (l)
I
Compare F1agn
where n = 0, 1, ••• 7
EXPLANATION:
This instruction provides a means to turn segment descriptor
(SD) compare flags OFF, and to inhibit the compare.
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPT,
INDICATORS:
None
NOTE:
Disabled by GODS
RPD, RPL
8-518
DZS1-OO
SPDBR
SPDBR
~
I
SPDBR
Store Page Table Directory Base Register
lSl
(1)
I
I
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode
SUMMARY:
C(PDBR)
00 ••• 0
-->
C(Y)0-18 (Mod S12)
--> C{Y)19-3S
C(PDBR) unchanged
EXPLANATION:
The PDBR content is stored in bit 0-18 of location Y. Zero
is stored in C(Y)19-3S. The PDBR content remains unchanged.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
None affected
NOTES:
1. An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
2. A Command fault occurs if execution of this instruction is
attempted in Slave or Master Mode.
(
8-Sl9
DZSl-OO
SPL
SPL
FORMAT:
CODI NG FORMAT:
SPL
Store Pointers and Lengths
447 (1)
Single-word instruction format (see Figure 8-1)
1
8
16
SPL
LOCSYM,R,AR
OPERATI NG MODES:
Any
SUMMARY:
C(Pointer and Length storage) --> C(Y), C(Y+1), ••• C(Y+S)
C(LOR} --> C(Y+6), C(Y+7)
EXPLANATION:
The pointers and lengths storage are used by hardware to
store control information when an interruptible mu1tiword
instruction is interrupted during execution. These registers
enable hardware to resume processing an interrupted
instruction after a return from servicing the interrupt.
Y must be a multiple of 8. However, a fault does not occur
when the lower 3 bits of Yare not 000. For purposes of
execution, the hardware forces these bits to 000 (modulo 8).
/
The format of the eight words is the same as words 48 through
55 of the safe Store Stack format (see Figures 8-7 and 8-8
under CLIMB). The contents of the first four words depend
upon whether the multiword instruction is alphanumeric or bit
string.
For an SPL execution, the eight words are stored into scratch
pad memory and the first flag is set or reset.
The format of the first four words follows.
,
" ' - __ J
8-520
DZ5l-00
,
(
SPL
SPL
II
35
012
I~J ~
10------
-
- --- -
_.. --
-
-0
Ll (Riqht-;ustified zero f HIed on left)
L2 (Riqht-justified zero f HIed on left)
Not Used
where
First Flag
F
If = 1, indicates the start of a
multiword instruction execution
for which the data from the
instruction operands is used.
If = 0, if bit 30 in the indicator
register is = 1, and, if the next
instruction is an EIS instruction,
the P&L data stored in scratch pad
memory is used. (Refer to
Indicator Register, Section 4.)
(
L
Length
Indicator
If = 0, only the length in
Ll is valid
.
If = 1, only the length in L2 is
valid
The firmware uses this bit to
determine whether Ll or L2
contains the valid length.
The length of Ll and 12 varies
depending upon whether NS or ES
mode are being used. For NS mode
alphanumeric, the length is 21
bits for 4- and 6-bit characters
and 20 bits for 9-bit characters.
For ES mode the maximum length is
36 bits.
8-521
t
II11
Alphnumeric Instructions
F
i
DZ51-00
SPL
SPL
Sign
Negative
SN
This indicator is used only if
the interrupted instruction is an
MLR in which a 6- or4-bit move is
being done. (Refer to Explanation
under description of MRL for use
of overpunch sign on 6-4 moves.)
Bit String Instructions
o
Temporary
Effective Address
Temporary
Effective Address
Ll
17 18
(Ri~ht-iustified
35
111111111111111111111111
111111111111111111111111
111111111111111111111111
111111111111111111111111
zero-filled on left)
L2 (Richt-iustified zero-filled on left)
The fi~st effective address relates to Ll: the
second effective address relates to L2.
The length of Ll and L2 varies, depending upon
whether NS or ES mode are being used. For NS mode,
the length is 24 bits for bit strings. For ES mode
the maximum length is 36 bits.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, Rl, IR, IT
ILLEGAL REPEATS:
RPT, RPD, RPL
ILLEGAL
EXECUTIONS:
XEC, XED
INDICATORS:
Multiword Instruction Interrupt indicator (bit 3D), reset to
OFF
8-522
DZ51-00
/
(
SPL
SPL
NOTES:
1.
An Illegal Procedure fault occurs if illegal address
modifications, illegal repeats, or illegal executions are
used.
2. The content of the pointer and length storage is changed
if RPT, RPD, RPL, XEC, or XED or indirect modification
(I T) are executed.
3. The SPL instruction is normally only used by routines that
process interrupts.
4. After an interrupt, the SPL must be executed before any
multiword instruction to avoid destruction of the pointer
and length information.
(
8-523
DZ51-00
SREG
SREG
SREG
Store Registers
753 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Any
SUMMARY:
NS Mode
The registers are stored as follows:
C(XO)
C(Xl)
C(X2)
C(X3)
C(X4)
C(XS)
C(X6)
C(X7)
C(A)
C(Q)
C(E)
C(TR)
-->
-->
-->
-->
-->
-->
-->
-->
-->
-->
-->
-->
C(Y)0-l7
C(Y)lS-35
C(Y+l)0-l7
C(Y+l)l8-35
C(Y+2}0-17
C(Y+2)l8-35
C(Y+3)0-17
C(Y+3)l8-35
C(Y+4)0-35
C(Y+5)0-35
C(Y+6)0-7i 0 ••• 0 --> C(Y+6)S-35
C(Y+7)0-26i 0 ••• 0 --> C(Y+7)27-35
/
ES Mode
The registers are stored as follows:
C(GXO)
C(GX1)
C(GX2)
C(GX3)
C(GX4)
C(GX5)
C(GX6)
C(GX7)
C(A)
C(Q)
C(E)
C(TR)
-> C(Y)
C(Y+l)
C(Y+2)
C(Y+3)
C(Y+4)
C(Y+5)
C(Y+6)
C(Y+7)
C(Y+8)
C(Y+9)
-> C(Y+10)0-7i 0 ••• 0 --> C(Y+IO)8-35
--> C(Y+ll): 0 ••• 0 --> C(Y+ll)27-35
-->
-->
-->
-->
-->
-->
-->
->
-->
In both NS and ES modes the register content remains
unchanged.
8-524
DZ51-00
SREG
SREG
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1. Location Y must be forced to a multiple of 8 by entering
an 8 in column 7 of the statement that defines Y, or by
means of the EIGHT pseudo-operation.
2.
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
(-
8-525
DZ51-00
SSA
SSA
55A
Subtract Stored from A-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C{A) - C(Y) -> C(Y); C(A) unchanged
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPL
I
NDI CATORS:
NOTE:
155 (C)
= 0, then ON; otherwise, OFF
C(Y)O = 1, then ON: otherwise, OFF
Zero
-
If C(Y)
Negative
-
If
Overflow
-
I f range of C(Y) is exceeded, then ON
carry
-
If a carry out of bit 0 of C(Y) is generated,
then ON; otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-526
DZ5l-00
(
SSCR
Set System Controller Register
057 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode
SUMMARY:
C(AQ}
EXPLANATION:
This instruction provides program access to all system
controller registers. SCU selection is based upon the control
SCU bit in the CPU mode register. Address development is
followed, and is transferred to the SCU to select the general
register.
-->
C(SCU Register)
In VMS Privileged Master mode, if both SCU ports are enabled
and the least-significant bit of the effective address (word
address) is 1, the control SCU bit is temporarily changed to
permit selection of the non-control SCU. (Reference Section 4
for CPU configuration register and ASR control.) The control
SCU bit is then reset to its original value.
(
(
SSCR
SSCR
Real Memory:
0 ••• 21
Bits
22-24
25-27
Function
X ••• X
0
X
Not used
X ••• x
1
X
Configuration
x••• x
2
X
Not used
x ••• x
3
X
Not used
x ••• X
4
X
calendar Clock
X ••• x
5
X
Not used
x ••• x
6
X
Not used
x•.• X
7
X
Not used
I LLEGAL ADDRESS
MODI Fl CATIONS:
DU, DL, CI, SC,
I LLEGAL REPEATS:
RPD, RPL, RPT
INDICATORS:
None affected
SCR
8-527
DZ51-00
SSCR
SSCR
NOTES:
l.
A Command fault occurs if address bits 22-24 are 0, 2, 3,
5, 6, or 7 (octal).
2. A Command fault occurs if execution is attempted in Slave
or Master mode.
3. The SCU registers are defined in Section 4.
4. Bits 25-27 of the configuration register are the SCU port
number. These bits must hazero in an SSCR instruction,
in order that a subsequent RSCR instruction returns the
port number: otherwise bits 25-27 are OR'ed with the port
number returned.
5.
IPR fault occurs if illegal address modification or
illegal repeats are executed.
An
/"
8-528
DZ51-00
(
SSQ
SSQ
SSQ
Subtract Stored from Q-Register
FORMAT:
OPERATI NG MODES:
Single-word instruction format (see Figure 8-1)
Any
SUMMARY:
C(Q) - c(y) --> C(y): C unchanged
I LLEGAL ADDRESS
a, SC,
156 (0)
I
"I'
I
DU, DL,
I LLEGAL REPEATS:
RPL
I NDI CATORS:
Zero
-
If C(Y)
Negative
-
If
Overflow
-
If range of C(Y) is exceeded, then ON
carry
-
If a carry out of bit 0 of C(Y) is generated,
then ON; otherwise, OFF
SCR.
= 0, then ON: otherwise, OFF
C(Y)o = 1, then ON: otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
(
8-529
I
i
MODIFICATIONS:
NOTE:
:.
DZ51-00
ssXn
SSXn
Subtract Stored from I ndex Register n
FORMAT:
Single-word instruction format (see Figure B-1)
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
For n
= 0,1, ••• ,7
l4n (0)
as determined by op code
C{Xn) - C(Y)0-17 --> C(Y)0-17; C(Xn) unchanged
ES Mode
For n
= 0,1, ••• ,7
as determined by op code
C(GXn) - C(Y} -> C(Y); C(GXn) unchanged
LLEGAL ADDRESS
MODIFICATIONS:
DU, DL,
ILLEGAL REPEATS:
RPT, RPD, or RPL of SSXO
I
I
NDI CATORS:
0,
SC, sea
NS Mode
Zero
-
If C(y)0-17 = 0, then ON; otherwise, OFF
Negative
-
If C(Y)O
Overflow
-
If range of C(Y) is exceeded, then ON
carry
-
If a carry out of bit 0 of C(Y) is generated,
then ON; otherwise, OFF
Zero
-
If C(Y)
Negative
-
If C(Y}O = 1, then ON: otherwise, OFF
Overflow
-
If range of C(Y) is exceeded, then ON
carry
-
If a carry out of bit 0 of C(Y) is generated,
then ON: otherwise, OFF
= 1,
then ON; otherwise, OFF
ES Mode
NOTE:
= 0,
then ON; otherwise, OFF
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-530
DZ5l-00
(
STA
STA
STA
Store A-Register
755 (0)
FORMAT:
single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(A) -> C(Y): C(A) unchanged
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL
ILLEGAL REPEATS:
RPL
I NDI CATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
(
8-531
DZ51-00
STAC
STAC
STAC
Store A Conditional
354 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
If C(Y) = 0, C(A)
EXPLANATION:
This instruction issues a read-lock, write-unlock sequence to
memory. cache is bypassed; if a cache hit occurs and the
conditional test is satisfied, the cache block is updated.
-->
C(Y)
If write does not occur, the next command to memory from the
same processor port performs unlock.
.
Execution of STAC is delayed until all outstanding stores to
memory from the processor have been completed.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPL
I NDI CATORS:
Zero
NOTE:
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
-
If initial C(Y)
8-532
= 0,
then ON; otherwise, OFF
DZ51-00
(
STACQ
STACQ
STACQ
Store A Conditional on Q
654 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
If C(Y} = C(Q), C(A) --> C(Y)
If C(Y) # C(Q), C(Y) is unchanged
EXPLANATION:
This instruction issues a read-lock, write-unlock sequence.
cache is bypassed; if a cache hit occurs and the conditional
test is satisfied, the cache block is updated.
If write does not occur, the next command to memory from the
same processor port.performs unlock.
Execution of STACQ is delayed until all outstanding stores to
memory from the processor have been completed.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, 0, SC, SCR
ILLEGAL REPEATS:
RPL
INDICATORS:
Zero
NOTE:
An
-
If initial C(Y)
OFF
= C(Q),
then ON; otherwise,
Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
(
8-533
DZ5l-00
STAQ
STAQ
STAQ
757 (0)
Store AQ-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(AQ) --> C(Y-pair); C(AQ) unchanged
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL,
I LLEGAL REPEATS:
RPL
I NDI CATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
a,
SC, SCR
8-534
DZSI-00
STAS
STAS
Store Argument Stack Register
STAS
750 (1)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(ASR) -> C(Y-pair): C(ASR) unchanged
EXPLANATION:
The execution of this instruction causes the current contents
of the argument stack register (ASR) to be stored in even and
odd memory locations Y and Y+l. The contents of the ASR
remain unchanged.
I LLEX7AL ADDRESS
MODIFICATIONS:
DU, DL, a, SC, SCR
I LLEX7AL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
EXAMPLE:
1
8
16
STAS
SDR
STP
SDR
STP
SVASR
PO
PO,SVPO
PI
Pl,SVPl
LOP
LOP
PAS
PO,SVPO
Pl,SVPl
SVASR
.
8-535
DZ5l-00
STBA
STBA
Store 9-bit Bytes of A-Register
STBA
551 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
9-bit bytes of C(A) -> corresponding characters of C(Y); the
byte positions affected are specified in the tag field; C(A)
is unchanged.
EXPLANATION:
Binary ones in the tag field specify the byte positions of A
and Y affected as indicated in the diagram below. The tag
field is entered as one 2-digit octal number. Bit positions
34 and 35 are ignored.
Tag
Field
-\
9-Bit Byte
positions' of
A and Y
I LLEGAL ADDRESS
o
o0
1 1
2 2
3
6 7
8 9
7 8
5
0
Character Character Character Character
2
1
0
3
MODIFICATIONS:
The tag field cannot be used for address modification.
modification is permitted.
I LLEGAL REPEATS:
RPT RPD RPL
INDICATORS:
None affected
NOTE:
An
EXAMPLE:
The instruction
I
AR
I
Illegal Procedure fault occurs if an illegal repeat is
used.
STBA
LOC,04
moves byte 3 of C(A) to the corresponding byte position of
C(LOC) <04 octal = 000100 binary). All other byte positions
of C(LOC) are unaffected.
8-536
DZ51-00
(
STBQ
STBQ
Store 9-bit Bytes of Q-Register
STBQ
552 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
9-bit bytes of C(Q> --> corresponding bytes of C(Y); the byte
positions affected are specified in the tag field; C(Q) is
unchanged
EXPLANATION:
Binary ones in the tag field specify the byte positions of Q
and Y affected as indicated in the diagram below. The tag
field is entered as one 2-digit octal number. Bit positions
34 and 35 are ignored.
Tag
Field
(
6-Bit Char.
positions of
A and Y
I LLEGAL ADDRESS
MODIFICATIONS:
1 1
aa
2 2
3
7 8
6 7
8 9
5
Character Character Character Character
1
2
a
3
a
a
The TAG field cannot be used for address modification.
modification is permitted.
AR
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if an illegal repeat is
used.
EXAMPLE:
The instruction STBQ LOC,04 moves byte 3 of C{Q) to the
corresponding byte position of C(LOC) (04 octal = 000100
binary). All other byte positions of C(LOC) are unaffected.
(
8-537
DZ51-00
STCI
STCI
STCl
Store Instruction Counter Plus 1
554 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATl NG MODES:
Any
SUMMARY:
C(IC) + 1 --> C(Y); C(IR) --> C(Y)18-32; 000 --> C(Y)33-35;
C(IC), C(IR) unchanged
EXPLANATION:
The relation between bit positions of C(Y) and the indicators
is as follows:
Bit Position
Indicator
18
19
20
zero
Negative
.21
Overflow
Exponent overflow
Exponent underflow
Overflow mask
Tally runout
Parity error
Parity mask
Master mode
Truncation
Multiword instruction interrupt
Exponent underflow mask
Hexadecimal exponent mode
000
22
23
24
25
26
27
28
29
30
31
32
33-35
carry
The ON state corresponds to a 1 bit; the OFF state
corresponds to a 0 bit. Bit 25 of C(Y) will contain the
state of the Tally Runout indicator prior to address
modification of the STCI instruction (for tally operations).
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, a, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-538
DZ5l-00
(
STC2
STC2
STC2
Store Instruction Counter Plus 2
750 (0)
FORMAT:
single-word instruction format _(see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C{IC)
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL,
I LLEGAL REPEATS:
RPT, RPD, RPL
I NDICA'l'ORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
+
2 --> C(Y)0-17i C(Y)18-35, C(IC) unchanged
a, SC,
SCR
(
8-539
DZ5l-00
STCA
STCA
STCA
Store 6-bit Characters of A-Register
751 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
6-bit characters of C(A) --> corresponding characters of C(Y);
the character positions affected are specified in the tag
field; C{A) is unchanged
EXPLANATION:
Binary (l) bits in the tag field specify the affected A and Y .
character locations as follows. The TAG field is entered as
one 2-digit octal number. (See Example below.)
Tag
Field
o
o0
1 1
2 2
2 3
3
1 2
5 6
3 4
9 0
6-Bit Char.
0
5
Positions of Character Character Character Character Character Character
1
2
0
3
4
A and Y
5
The CPU reads one word from memory, embeds a character
specified in the CPU into the word, and writes this word back
in memory. Therefore, while the CPU reads a word and writes
it, the word's content can be lost if another CPU writes the
same word. To prevent multiprocessor contention, gating is
necessary.
j'
8-540
DZ51-00
(
STCA
STCA
I LLEGAL ADDRESS
MODIFICATIONS:
No modification except AR allowed.
I LLEGAI J REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1. The tag field cannot be used for address modification.
AR
modification is permitted.
2.
EXAMPLE:
An Illegal Procedure fault occurs if illegal repeats are
used.
The instruction STCA LOC,07 moves characters 3, 4, and 5 of
C(A) to corresponding character positions of C(LOC) (07 octal
= 000111 binary). Character positions 0, 1, and 2 of C(LOC)
are unaffected.
8-541
DZ51-00
STCQ
STCQ
STCQ
Store 6-bit Characters of Q-Register
752 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
6-bit characters of C(Q> -> corresponding characters of
C(Y): the character positions affected are specified in the
tag field.
EXPLANATION:
Binary (1) bits in the tag field specify the affected Q and Y
character locations as follows. The tag field is entered as
one 2-digit octal number. (See Example below.)
Tag
Field
1 1
1 1
o
o0
2 2
2 3
3
7 8
1 2
3 4
5 6
9 0
5
6-Bit Char.
0
positions of Character Character Character Character Character Character
1
2
3
4
0
A and Y
5
The CPU reads one word from memory, embeds a character
specified in the CPU into the word. and writes this word back
in memory. Therefore, while the CPU reads a word and writes
it, it is possible that the word's content can be lost if
another CPU writes the same word. To prevent multiprocessor
contention, gating is necessary.
8-542
DZ51-00
STCQ
STCQ
(
ILLEGAL ADDRESS
MODIFICATIONS:
No modification except AR allowed.
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1. The tag field cannot be used for address modification.
AR
modification is permitted.
2. An lllegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
EXAMPLE:
The instruction STCQ LOe,07 moves characters 3, 4, and 5 of
C(Q) to corresponding character positions of C(LOe) (07 octal
= 000111 binary). Character positions 0, 1, and 2 of C(LOC)
are unaffected.
(
(.
8-543
DZ5l-00
STDn
STDn
Store Descriptor Register n
05n (1)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(DRn) --> C(Y),C(Y+1): C(ORn) unchanged
EXPLANATION:
This instruction stores the ORn content in an even/odd
location of the segment descriptor segment or the operand
segment.
If instruction bit 29
instruction segment.
=0
then C(DRn) --> C(Y-pair) in the
If instruction bit 29 = 1 and ORm descriptor type T = 1,3 (m
is selected by instruction bits 0,1,2) then C(DRn) -->
C(Y-pair) of descriptor segment.
NOTE: ORn store permission is required.
If instruction bit 29 = 1 and ORm descriptor type T = 0, 2,
4, 6, 12, 14 then C(DRn) --> C(Y-pair) in the operand
segment.
NOTE: ORn store permission is not required.
To summarize the differences in processing performed due to
the differing types of segment descriptors:
o If the ORn segment descriptor is stored in a segment
descriptor segment (T = 1 or 3), the page must be a
housekeeping page (PTW bit 32 must = 1). When all other
conditions (e.g., write permission) are satisfied, the
segment descriptor is stored, irrespective of the CPU
mode.
o I f an attempt is made to store in the operand segment, the
write operation for the housekeeping page is dependent
upon the CPU mode as the store flag is not examined by
hardware.
8-544
DZ51-00
STDn
ILLEGAL ADDRESS
MODIFICATIONS:
STDn
If the DRm type T = 1 or 3, only R type modification is
permitted. An IPR fault occurs if DU, DL, Rl, IR, or IT is
specified.
If the DRm type T = 0, 2, 4, 6, 12, or 14, an IPR fault
occurs when DU, DL, SC, SCR, or CI is specified.
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1.
An Illegal Procedure fault occurs when illegal address
modification or an illegal repeat is used.
2. If DRn does not have store permission (bit 18 for T = 8,
9, 11: bit 22 for all other types), an SCL2 fault occurs.
3. If DRm page is not housekeeping, an seLl fault occurs.
4. If DRm segment or page does not have write permission, an
SCL2 fault occurs.
(
5. If processor is in Master or Slave mode and DRm page is
housekeeping, an SCLl fault occurs.
6. If DRm segment or page does not have write permission, an
SCL2 fault occurs.
= 1 and DRm descriptor type T = 5 or
7-11, 13, 15, an IPR fault occurs.
7. If instruction bit 29
8-545
DZ5l-00
STDSA
STDSA
Store Data Stack Address Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master mode
SUMMARY:
C(DSAR) -> C(Y)0-16
/
150 (1)
00 ••• 0 --> C(Y)17-35
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, a, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1.
IPR fault occurs if illegal address modifications or
illegal repeats are used.
An
2. A Command fault occurs if this instruction is executed in
Slave or Master mode.
EXAMPLE:
1
78
STDSO
STDSA
LOXO
16
SVREG
SVREG+2
SVREG+2
ADLXO
NWPS,DU
CMPXO
SVREG
TPNZ
NOGOOD
P.DS,DSVEe
LOD
SVREG 8BSS
DSVEC NEe
8
NWDS, (ALL)
,/
8-546
DZ51-00
--,\
(
STDSD
Store Data Stack Descriptor Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Privileged Master mode
SUMMARY:
C(DSDR) --> C(Y-pair); C(DSDR) unchanged
I LLEGAL ADDRESS
(
STDSD
STDSD
551 (1)
MODI FI CATIONS:
DU, DL, a, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATeRS:
None affected
NOTES:
1. An IPR fault occurs if illegal address modifications or
illegal repeats are used.
2. A Command fault occurs if this instruction executed in
Slave or Master mode.
8-547
DZ51-00
STE
STE
STE
456 (0)
Store Exponent Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(E) -->
C(Y)0-7~
00 •••• 0 -->
C(Y)8-17~
C(Y)18-35, C(E) unchanged
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS: . RPL
I NDI CATeRS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modification or illegal repeats are used.
8-548
DZ5l-00
STI
STI
C(Y)18-32
754 (0)
00 ••• 0--> C(Y)33-35i
C(Y)0-171 C{IR) unchanged
EXPLANATION:
The content of the indicator register is stored in C(Y)18-32
after address modification. The value stored in C(Y)25 is
the Tally Runout status before address modification. The
relation between bit positions of C(Y) and indicators is as
follows:
Bit Location
(
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33-35
Indicator
Zero
Negative
carry
Overflow
Exponent overflow
Exponent underflow
Overflow mask
Tally runout
Parity error
Parity mask
Master mode
Truncation
Multiword instruction interrupt
Reserved for exponent underflow mask
Hexadecimal exponent mode
000
The ON state corresponds to a 1 bit; the OFF state to a 0
bit.
(
8-549
DZ51-00
STI
STI
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, 0, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
None affected
NOTE:
An Illegal Procedure .fault occurs if illegal address
modifications or illegal repeats are used.
8-550
DZ5l-00
(
STO
STO
STO
Store Option Register
152 (1)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(DSCF) --> bit 18 of C(Y)
C(SSBF) --> bit 19 of C(Y)
00 ••• 0
EXPLANATION:
(
-->
remaining
34
bits of C(Y)
This instruction stores the two flag bits of the option
register in memory.
DSCF
Data stack clear flag
o = do not clear
1 = clear
SSBF
safe store bypass flag
o = bypass safe store dur ing I CLl MB
1 = perform safe store during ICLIMB
I LLEGAL ADDRESS
MODIFICATIONS:
DU DL, CI
I LLEGAL REPEATS:
RPT, RPD RPL
INDICATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
I
I
SC, SCR
I
8-551
DZ51-00
STO
STO
EXAMPLES:
1
8
ORNCHE BOOL
MPOR EQU
LDO
S10
STO
LDA
ERSA
TRA
•
*SAVE VIRTUAL
STREG NULL
STWS
STWS
SPDBR
STO
SZN
16
32
4000
*CRCF bit of option register
*
.SORSV, ,P.SSA
.CRORR,PN,P.CR *set with CRCF ON
.CRORS,PN ,P.CR
ORNCHE,DL
•CRORS, PN P. CR *reset CRCF to OFF
X.RED+1
I
UNIT REGISTERS
REG+12
REG+13
REG+40
REG+41
SSFALT+. WID
safe store frame saved?
8-552
DZ51-00
STPn
STPn
Store Pointer n
45n (1)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
C(ARn) --> C(Y)0-23
C(SEGIDn) --> C(Y)24-35
ES Mode
C(ARn) --> C(Y)
C(SEGIDn) --> C(Y+l)O-ll
'00 ••• 0
(
EXPLANATION:
-->
C(Y+l)12-35
These instructions store the address register (ARn) and the
associated segment identity register, (SEGIDn), in memory.
The contents of the registers remain unchanged.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, a, SC, SCR
ILLEGAL REPEATS:
RPT, RPD,
INDICATORS:
None affected
NOTE:
An
RPL
Illegal Procedure fault occurs if illegal address
modification or an illegal repeat is used.
8-553
DZ5l-00
STPn
STPn
EXAMPLE:
1
8
16
32
NEPR
EPPR
PO,FANY
error handler
STP
10P
10P
100
100
10A
PO,.SVFLT"P.SSA
PO,.PS,OL
Pl,.SSR,OL
PO,O"PO
Pl,.WLSR"Pl
0, ,PO
=020160,OL
FANY
store pointer 0
old argument segment
safe store
get argument 0
get original linkage segment
get EPPA pointer
test null descriptor
CNAA
TZE
/
8-554
OZ51-00
STPDW
STPDW
STPDW
Store PTWAM Directory Word
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master Mode
SUMMARY:
C(PTWAM DirectorY)n -> C(Y)00-29
00 ••• 0
-> C(Y)30-35
where: n
EXPLANATION:
(
= Yll-17
155 (1)
Yll-16 specifies row
Y17 specifies column of
associative memory
The contents of the PTWAM directory word n are stored in
memory location Y bits 00-29; zeros are stored in bits 30-35.
Bits 00-26 represent the combination of working space number
and virtual address that is stored in the directory word for
future association. Bits 28 and 29 specify the round robin
counter for the row in which this directory word is stored in
the AM. Bit 27 = 1 specifies that the row in which this
directory word is stored is full.
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
l. The PTWAM is 64 rows by 2 columns.
Bits 25-30 of the
virtual address select a row. Thus, the two entries in
each row have the same six least-significant bits.
2. This instruction functions whether the PTWAM is ON or OFF.
(Refer to the CAMP instruction.>
3. The STPDW instruction inhibits the CPU from carrying out
the execute interrupt procedure when the STPDW instruction
is executed from an odd memory location, even though the
interrupt condition is present and waiting for execution.
4. An IPR fault occurs if illegal address modifications or
illegal repeats are used.
5. A Command fault occurs if this instruction is executed in
Slave or Master mode.
8-555
DZ5l-00
STPS
STPS
Store Parameter Segment Register
STPS
751 (1)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(PSR) -> C(Y, Y+l}
EXPLANATION:
This instruction stores the current contents of the parameter
segment register (PSR) in even and odd memory locations Y and
Y+l. The contents of the PSR remain unchanged.
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTE:
An
IPR fault occurs if illegal address modifications or
illegal repeats are used.
(PMME processing>
EXAMPLE:
1
"
8
16
32
STPS
LOA
.STEMP, ,P.SSA
•STEMP "P •SSA
STASH PSR
CANA
.FBT27,DL
ANY
TZE
LOP
NOPARM
Pl, .PS
o,DL+YES,
PARAMETERS?
NO,XFER
8-556
GET FIRST
DZ5l-00
I
/
STPTW
STPTW
Store PTWAM Register
157 (1)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master Mode
SUMMARY:
C(PTWAM)n --> C(Y)00-35
where: n
EXPLANATION:
= Yll-17
Yll-16 specifies row
Y17 specifies column of
associative memory
The contents of the PTWAM word n are stored in memory location
Y. The absolute memory address (mod 1024) of the referenced
page is stored in bits 4-17. Bits 0-3 and 18-29 are stored as
zeros. Bits 30-35 are the hardware control field bits in the
PTW (bits 30 and 35 are stored as ones).
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS :
None affected
NOTES:
1. The PTWAM is 64 rows by 2 columns. Bits 25-30 of the
virtual address select a row. Thus, the two entries in
each row have the same six least-significant bits.
2. This instruction functions whether the PTWAM is ON or OFF.
(Refer to the CAMP instruction.)
3. The STPTW instruction inhibits the CPU from carrying out
the execute interrupt procedure when the STPTW instruction
is executed from an odd memory location, even though the
interrupt condition is present and waiting for execution.
4. An IPR fault occurs if illegal address modifications or
illegal repeats are used.
5. A Command fault occurs if this instruction is executed in
Slave or Master mode.
(
8-557
DZ51-00
STQ
STQ
STQ
Store Q-Register
756 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(Q> -> C(Y): C unchanged
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL
ILLEGAL REPEATS:
RPL
I NDI CATeRS:
None affected
NOTE:
An IPR fault occurs if illegal address modifications or an
illegal repeats are used.
8-558
DZ5l-00
(
STSS
STSS
STSS
Store safe Store Register
FORMAT:
Single-word instruction format (see Figure B-1)
OPERATING MODES:
Privileged Master mode
SUMMARY:
C(SSR)O-35 --> C(Y)O-35
753 (1)
C(SSR)36-69 --> C(Y+l)0-33
The following value is stored in C{Y+l)34,35 in accordance
with the SCR value.
If C(SCR)
= 00101/11
11 --> C(Y+l)34,35
If C(SCR)
(
(64-word frame)
= 10
10 --> C(Y+l)34,35
ILLEGAL ADDRESS
MODIFICATIONS:
DU , DL, CI, SC, SCR
ILLEGAL REPEATS:
RPT RPD, RPL
INDICATORS:
None affected
NOTES:
1.
(80-word frame)
I
An Illegal Procedure fault occurs when illegal address
modification or an illegal repeat is used.
2. A Command fault occurs if the processor is in Slave or
Master mode and this instruction is executed.
8-559
DZ51-00
STSS
STSS
EXAMPLES:
1
8
SOVTE NULL
LOP
LOP
STSS
LOA
ADA
ORA
STA
SBA
EAX2
LDQ
QRL
ADO
CMPQ
EAX2
SBA
ALS
STA
LOP
LOP
LOP
LXLO
LDAQ
STAQ
STSS
LOA
ANA
ORA
STA.
LDD
16
32
PO,SD.PSH,DL
PO,.CTYP,DL
.SSSR"P.SSA
.SSSR+1"P.SSA
1K*4,DL
-07777,DL
.SVFLT+1"P.SSA
192*4,DL
1,3
PH.SS, ,PO
16
PH.SS+1"PO
.SVFLT+1, ,P.SSA
copy push segment descriptor to PO
change push descriptor type
store SSR
SSR base
+ 1K words
adjust page bound
save it
.SSSR+1"P.SSA
16
.SVFLT+1"P.SSA
P1,SD.DGS,DL
PO,SD.DGS,DL
PO,.CTYP,DL
POINT,7
O,O,PO
.SSSR, ,P.SSA
O,O,PO
O,O,PO
=0177777,DL
.SVFLT+1"P.SSA
O,O,PO
P2,0,O,P1
get new bound
a
original SSR bound + base
get max virtual address for safe store
store new bound
load DGS segment descriptor
change type GDS descriptor
store current contents
store SSR to generate page load segment
set new bound
load new safe store descriptor
8-560
DZ51-00
STT
STT
STT
Store Timer Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(TR)
454 (0)
-> C(Y)0-26
00 ••• 0 --> C(Y}27-35
(
ILLEGAL ADDRESS
MODIFICATIONS:
DU , DL, CI
ILLEGAL REPEATS:
RPT I RPD I RPL
I NDI CATeRS:
None affected
NOTES:
1. Bit 26 has a significance of 1/512 millisecond.
I
SC, SCR
2. An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
(
8-561
DZ51-00
STTA
STTA
STTA
Store Test Address Registers
553 (I)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master Mode
SUMMARY:
C{Test Register 0,1)
EXPLANATION:
Contents of test registers 0 and 1 are stored in even/odd
memory locations Y and Y+l. Contents of test registers
remain unchanged.
-->
C(Y-pair)
This instruction inhibits the processor from carrying out the
execute interrupt procedure when the STTA is executed from an
odd memory location, even though the interrupt condition is
present and waiting for execution.
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
I NOI CATORS:
None affected
NOTES:
1.
An Illegal 'Procedure Fault occurs if illegal address
modification or illegal repeats are executed.
2. A Command fault occurs if execution is attempted in Master
or Slave mode.
8-562
DZ51-00
(
STTD
STTD
S'l"l'D
Store Test Descriptor Registers
550 (1)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master Mode
SUMMARY:
C(Test Register 0,1) --> C(Y-pair)
EXPLANATION:
Contents of test registers 2 and 3 are stored in even/odd
memory locations Y and Y+l. Contents of test registers
remain unchanged.
This instruction inhibits the processor from carrying out the
execute interrupt procedure when the STTD is executed from an
odd memory location, even though the interrupt condition is
present and waiting for execution.
(.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC t SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1. An Illegal Procedure Fault occurs if illegal address
modification or illegal repeats are executed.
2. A Command fault occurs if execution is attempted in Master
or Slave mode.
(
8-563
DZ51-00
STWS
STWS
STWS
Store Working Space Registers
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Privileged Master Mode
SUMMARY:
When EA17 (NS Mode) or EA33 (ES Mode) = 0
C(WSRO)
->
C(Y)O-8
C(WSR1)
->
C(Y)9-17
C(WSR2)
-->
C(Y)18-26
C(WSR3)
-->
C(Y)27-35
752 (1)
When EA17 (NS Mode) or EA33 (ES Mode)= 1
EXPLANATION:
C(WSR4)
->
C(Y)O-8
C(WSR5)
->
C(Y)9-17
C(WSR6)
-->
C(Y)18-26
C(WSR7)
-->
C(Y)27-35
The contents of WSRO to WSR3, or WSR4 to WSR7 are stored in
memory location Y, in accordance with the setting of the
EA17/EA33 value.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
8-564
DZ51-00
STWS
STWS
1. An Illegal Procedure fault occurs if illegal address
NOTES:
modification or an illegal repeat is used.
2. A Command fault occurs if the processor is in Slave or
Master mode and this instruction is executed.
EXAMPLE:
1
8
TODES NULL
STWS
STWS
16
32
WSR
WSR+l
store WSR 0-3
store WSR 4-7, store contents
EVEN
WSR
BSS
2
(
(
8-565
DZ51-00
STXn
STXn
Store Index Register B in Upper
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Any
SUMMARY:
NS Mode
For n
c
74n (0)
0,1, ••• ,7 as determined by op code
C(XB) --> C(Y)O-17
C(Y)18-35 unchanged
ES Mode
For n
I
c
0,1, ••• ,7 as determined by op code
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, Cl, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, or RPL of STXO
INDICATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-566
DZ5l-00
(
STZ
STZ
STZ
Store Zero
450 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
00 ••• 0 --> C(Y)
I LLEGAL ADDRESS
MODI PI CATIONS:
DU, DL
I LLEGAL REPEATS:
RPL
I NDI CATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-567
DZ51-00
SWCA
SWCA
SWCA
Subtract with carry from A-Register
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
If carry indicator is ON
171 (0)
C(A) - C(Y) --> C(A)
C (y) unchanged
I f carry indicator is OFF
C(A) - C(y) - 00 ••• 1 --> C{A)
CCy) unchanged
EXPLANATION:
This instruction is identical to SBA except that, when the
carry indicator is OFF at the beginning of the instruction, a
positive 1 is subtracted from the least-significant position.
This instruction is intended for use with multiword-precision
arithmetic. Thus, the summary above can be reworded as
follows:
If carry indicator is ON, then C(A) + one's complement of
C(y) + 00 ••• 1 --> C(A)
If carry indicator is OFF, then CCA) + one's complement of
C(y) -> CCA)
The positive 1 is added when ON represents the carry from the
next less-significant part of the multiword subtraction.
ILLEGAL ADDRESS
MODIFICATIONS:
None
I LLEGAL REPEATS:
None
8-568
DZ51-00
SWCA
SWCA
I NDI CA'l'ORS :
= 0,
Zero
-
If C(A)
then ON; otherwise, OFF
Negative
-
If C(A)O = 1, then ON: otherwise, OFF
Overflow
-
I f range of A is exceeded, then ON
carry
-
If a carry out of bit 0 of C(A) is generated,
then ON: otherwise, OFF
(.
(
8-569
DZ51-00
SWCQ
SWCQ
SWCQ
Subtract with carry from Q-Register
172 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
If carry indicator is ON
C(Q> - C(Y> --> C(Q>
C(y > unchanged
If carry indicator is OFF
C(Q) - C C
C(y > unchanged
EXPLANATION:
This instruction is identical to SBQ except that, when the
carry indicator is OFF at the beginning of the instruction, a
positive 1 is subtracted from the least-significant position.
This instruction is intended for multiword-precision
arithmetic. Thus, the summary above can be reworded as
follows:
If carry indicator is ON, then C
C(Y> + 00 ••• 1 --> C
+
one's complement of
If carry indicator is OFF, then C + one's complement of
C(Y> --> C(Q>
The positive 1 is added when ON represents the carry from the
next less-significant part of the multiword subtraction.
ILLEGAL ADDRESS
MODI FI CATl ONS:
None
I LLEGAL REPEATS:
None
8-570
DZ51-00
(
SWCQ
SWCQ
Zero
-
Negative
- If C(Q>O = 1, then ONi otherwise, OFF
Overflow
-
carry
- If a carry out of bit 0 of C is generated,
INDICATORS:
If C = 0, then ON: otherwise, OFF
If range of Q is exceeded, then ON
then ONi otherwise, OFF
(Triple-precision binary fixed-point subtraction)
EXAMPLE:
1
8
16
32
STI
LDA
ORSA
LDI
C
=lB24,DL
C
C
A+2
B+2
C+2
A+l
B+1
C+l
C
=0733777,DL
C
C
A
B
C
set overflow mask ON
LDQ
SBLQ
STQ
LDQ
SWCQ
STQ
STI
LDA
ANSA
LDI
LDQ
SWCQ
STQ
(
A
B
C
DEC
DEC
BSS
subtract low-order bits
subtract intermediate bits
set overflow and overflow mask OFF
subtract high-order bits
9,8,7
6,5,4
3
(
8-571
DZ5l-00
SWD
SWDX
SWD
SWDX
S~
SWDX
Subtract Word Displacement from Address Register
FORMAT:
CODING FORMAT:
527
(1)
Special arithmetic instruction format (see Figure 8-3)
1
16
8
{SWD}
{SWDX}
word displacement,R,AR
When the mnemonic is coded with X (AWDX), bit 29 is forced to
zero.
OPERATI NG MODES:
Any
SUMMARY:
If bit 29 = 1:
If bit 29
= 0:
C(ARn)0-17 -(y
- y
+
+
C(DR»
-->
ARnO-17
C(DR) --> ARnO-17
In either case, 00 ••• 0 --> ARn18-23
EXPLANATION:
The y field (with bit 3 extended) is added to the contents of
the register specified by the code in the DR field. Then, if
bit 29 = 0, this value replaces bits 0-17 of the AR specified
by bits 0-2 of the y field. If bit 29 = 1, this value is
subtracted from bits 0-17 of the specified AR and the result
is stored in bits 0-17 of the specified AR. In either case,
bits 18-23 of the specified AR are zeroed.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, or Ie specified in DR
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTE:
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-572
DZ5l-00
/
(
SWD
SWDX
SWD
SWDX
EXAMPLE:
1
Applies to NS mode only
8
16
EAX5
SWDX
SWD
2
2,5,4
0,5,4
AR4 octal contents
AR4 octal contents
-
7 7 7 7 7 4 0 0
7 7 7 7 7 2 0 0
EAX4
SWDX
SWD
1
4,4,7
1,4,7
AR7 octal contents AR7 octal contents -
7 7 7 7 7 3 0 0
7 7 7 7 7 1 0 0
(
8-573
DZ51-00
SXLn
SXLn
Store Index Register
n in
Lower
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
44n (0)
For N=0,1, ••• ,7 as determined by op code
C(Xn) --> C(Y)18-35
C(Y)O-17 unchanged
ES Mode
For N=0,1, ••• ,7 as determined by op code
C( GXn 18-35) --> C(Y)18-35
C(Y)O-17 unchanged
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, or RPL of SXLO
INDICATORS:
None affected
NOTE:
An
Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-574
DZ5l-00
(
SYNC
SYNC
SYNC
Gate Synchronize
014 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
EXPLANATION:
This instruction operates as a NOP; no operation takes place.
I LLEX;AL ADDRESS
MODIFICATION:
Address modifications are performed, but have no effect on
the operation.
ILLEX;AL REPEATS:
RPD, RPL, RPT
INDICATORS:
Address modifications cause defined changes to address and
tally. The tally runout indicator may be set ON as a result.
NOTE:
An
IPR fault occurs if an illegal repeat is executed.
8-575
DZ5l-00
SZN
SZN
SZN
Set Zero and Negative Indicators from Storage
234 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATl NG MODES:
Any
EXPLANATION:
C(Y) is tested and the indicators are set in accordance with
the result
I LLEGAL ADDRESS
MODIFICATIONS:
None
I LLEGAL REPEATS:
None
I NDI CATORS:
Zero
-
If C(Z)
Negative
-
If
Negative
o
1
o
o
o
1
= 0, then ON: otherwise, OFF
C 0
Number C(Y) = 0
Number C(Y) < 0
8-576
DZ5l-00
(
SZNC
SZNC
SZNC
Set zero and Negative Indicators from Storage
and Clear
214 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
EXPLANATION:
This instruction provides test-and-set operation, required
for setting and releasing locks, or for closing and opening
gates. C(Y) is tested and the indicators are set in
accordance with the result. C(Y) is then zeroed.
This instruction is used for a gating operation in multiple
CPU systems. Execution of the next instruction is delayed
until the cache-flush request applied to all CPUs has
completed.
I LLEGAL ADDRESS
(
MODIFICATIONS:
DU, DL,
I LLEGAL REPEATS:
None
I NDI CATORS :
Zero
- If C(Z)
Negative
- If C(Z)O = 1, then ON; otherwise, OFF
NOTE:
0,
SC, SCR
zero
N~ative
0
1
0
0
0
1
= 0,
then ON; otherwise, OFF
Relationshi12
Number C(Y) > 0
Number C(Y) = 0
Number C{Y) < 0
An Illegal Procedure fault occurs if illegal address
modification is used.
(
8-577
DZ5l-00
SZTL
SZTL
Set Zero and Truncation Indicators with Bit
Strings Left
SZTL
064 (1)
FORMAT:
o0
o1
000
4 5
o 011
1 1
7 8
8 901
HDDDD IBOLR 1+1
MF2
Op
2
8
064(1)
1
0 o0
0 2 3
Code
1 1 1 2
7 8 9 0
AR#
3
3
2
5
0----------------0
1 1 1 2
7 8
2 2
3 4
9 0
Y2
C2
CODING FORMAT:
1
N1
B1
Y1
000
023
AR#
NFl
2 2
3 4
Y1
C1
H
3
5
3
2
3
5
N2
B2
Y2
0-------------0
1
R1
8
16
SZTL
BDSC
BDSC
(NFl), (MF2),BOLR,F,T
LOCSYM,N,C,B,AM
LOCSYM,N,C,B,AM
R2
(Refer to Section 7 under Nultiword Instructions for description
of Multiword Modification Field.)
OPERATING MODES:
Any
SUMMARY:
C(string 1) : (BOLR) : C(string 2)
8-578
DZ5l-00
SZTL
SZTL
(
The string of bits starting at location YCBl is evaluated,
bit by bit, with the string starting at location YCB2 until
either the resultant bit from the BOLR field is a 1 or until
L2 is exhausted. If U is greater than 12, the Truncation
indicator is set.
EXPLANATION:
If Ll is less than L2, the fill bit (F) is used as the L2-L1
least-significant bits of string 1. The contents of both
strings remain unchanged.
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL for MFl and MF2
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
Zero
-
Truncation NOTES:
(
If all the resultant bits generated are zero,
then ON; otherwise, OFF
If Ll is > 12, then ON; otherwise, OFF
1. An Illegal Procedure fault occurs when illegal address
modification or illegal repeats are used.
2. An IPR fault does not occur even when Ll = 0 or L2 = O. In
this case, the zero and truncation indicators are affected.
(
8-579
DZ5l-00
SZTL
SZTL
EXAMPLES:
1
8
16
32
SZTL
Bose
Bose
, ,6
FLDl,36,O,O
FLD2,35,O,1
ALLOFF
TRUNe
CONST.
-1
-1
exclusive OR operation
FLDI operand descriptor
FLD2 operand descriptor
zero indicator ON
truncation indicator ON
memory contents in octal
777777777777
777777777777
indicators set? - zero and truncation
TZE
FLOI
FLD2
TRTN
USE
OEC
OEC
USE
LDI
LDX7
STI
SZTL
Bose
Bose
TNZ
FL01
FLD2
USE
BSS
OEC
USE
O,OL
-l,OU
FLDI
,,1
FLDl,1,2,1
FLD2,1,2,1
190N
eONST.
1
IB19
load negative value into X7
store processor indicators
AND operation
FLDI operand descriptor
FLD2 operand descriptor
not zero - negative indicator ON
memory contents in octal
x x x x x x 2 0 0 0 0 0
o 0 0 0 0 020 0 0 0 0
indicators set? - none
8-580
"'-.
OZ51-00
SZTR
SZTR
Set zero and Truncation Indicators with Bit
Strings Right
SZTR
065 (1)
FORMAT:
o0 o0
o1 4 5
Hoooa
0
0
001
B9 0
IBOLR
1 1
7 B
1
1
1+ I
Op
I
MF2
o0
Code
III 2
NFl
2
3
0
Yl
Cl
AR#
3
2
5
Rl
0-------0
III 2
2
789
3
0
3
2
Y2
3
5
N2
C2
B2
0---
Y2
COD! NG FORMAT:
3
Nl
Bl
Yl
000
023
AR#
3
065(1)
789
2 3
2
1
8
16
SZTR
BDSC
BDSC
(MFl),(NF2),BOLR,F,T
LOCSYM,N,C,B,AM
LOCSYN,N,C,B,AM
0
R2
(Refer to Section 7 under Multiword Instructions for description
of Multiword Modification Field.)
OPERATI NG MODES:
Any
SUMMARY:
C(string 1)
(BOLR)
C(string 2)
8-581
DZ51-00
SZTR
SZTR
EXPLANATION:
same as for SZTL except that starting locations are YCBl +
(Ll-l) and YCB2 + (L2-1) and the evaluation is from right to
left (least-significant bit to most significant bit). Any
fill (used in comparison) is of most-significant bits.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MF1 and MF2
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
same as for SZTL
NOTE:
Notes for SZTR are the same as for SZTL.
EXAMPLES:
1
8
16
32
SZTR
,,3,1
FLD1,1,2,1
0,1
190N
eONST.
1B19
evaluate FLD1 as is (move)
FLDl operand descriptor (bit 19)
FLD2 operand descriptor
BOSC
BOse
TNZ
USE
F101 DEC
USE
101
LDX7
STI
SZTR
F10l
1,14
USE
FLD1,1,2,0
0,1
l80N
CONST.
BSS
1
BOSC
BDSe
TZE
F10l
O,DL
O,DU
USE
memory contents in octal
o0 0 0 0 0 2 0 0 0 0 0
indicators set? - none
clear processor indicators
load zeros into X7
store processor indicators
invert
FLDl operand descriptor (bit 18)
FLD2 operand descriptor
zero indicator ON
memory contents in octal
xxxxxx400000
indicators set? zero
8-582
DZ5l-00
(
TCT
TCT
164
Test Character and Translate
TCT
(1)
FORMAT:
o0
o1
000
4 5
0
1
oa1
890
1 1
7 8
1
1
Op
-01
---------
0 o0
0 2 3
Code
164(1)
35
MF1
3
2
3
5
Nl
CNl
(
!xl
1 1 2 2 222
7 8 o 1 234
Y1
AR#
2
8
TAl 0
Y1
0------0
1 1
000
023
7 8
R1
22333
89012
3
5
Y2
0---AR#
-----0 AR 00
REG2
Y2
1 1
000
023
7 8
22333
89012
3
5
Y3
0----AR#
CODING FORMAT:
(
---0 AR 00
REG3
Y3
1
8
16
TCT
ADSCn
ARG
ARG
(MF1)
LOCSYM,CN,N,AM
LOCSYM, RM, AM
LOCSYM, RM, AM
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
8-583
DZ51-00
TeI'
TCT
OPERATI NG MODES:
Any
EXPLANATION:
Starting at location Yel, each type TAl character is used as
an index to a table of 9-bit characters that starts at
location Y2. If the table entry is zero, a counter is
incremented by 1.
The operation terminates if a nonzero table entry is found or
if the tally (Ll) is exhausted. At the conclusion of the
instruction, the counter contents are stored right-justified
in bits 12-35 of Y3. The last accessed table entry is placed
in bits 0-8 of Y3. Zeros are placed in bits 9-11 of Y3.
Except in cases of string overlap, the contents of the source
field and the table remain unchanged. (Refer to Explanation
under MVT.)
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL for NFl, REG2, REG3
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
Tally - If the tally (Ll) is exhausted and table entry is
zero, then ON; otherwise, OFF
NOTES:
1. If Nl=O, zero is stored in Y3 (bits 12-35) and the tally
indicator is affected.
2. If Nl>O and a match is found in the first character, zero
is stored in Y3 (bits 12-35) and the tally indicator is
not affected.
3. An Illegal procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-584
DZ51-00
TCT
TCT
EXAMPLE:
1
16
32
BCl
FLD1,0,12
TABLE
FLD3
FOUND
CONST.
2, 1234567890#
BSS
1
no modification
indexing string operand descriptor
pointer to table
pointer to character and count word
nonzero character found
memory contents
200102030405060710110013 (octal)
character and count - 020000000013
8
TCT
ADSC6
ARG
ARG
TTF
USE
FLD1
FLD3
TABLE OCT
OCT
OCT
USE
NOTE:
Octal
1 2 3 456 7
Index
000000000000,000000000000 OX
000000020020,020020020020 IX
000000000000
2X
Result - nonzero character found
o
The highest possible value in FLD1 is an octal 20, a "blank".
EXAMPLE WI TH ADDRESS MODI FI CATION:
1
8
16
X6
BOOL
EAX2
EAX3
EAX6
AWDX
TCT
ARG
ARG
ARG
TTF
NULL
USE
16
2
FLDl
6
0,3,7
{1,1,1,2}
INDSCR
TABLE
FLD3
*+2
FLD1 ASOl
FLD3 BSS
INDSCR ADSC9
TABLE BSS
OCT
OCT
USE
NOTE:
32
CONST.
2,
put 2 into X2
put FLDl address into X3
put FLD1 length into X6
put FLD1 address into AR7
with all modification options
pointer indirect operand descriptor
pointer to table
pointer to FLD3
nonzero found
tally runout ON
memory contents
1234;5
040040061062063064073065 (octal)
character and count 040000000004
0,0,x6,7
indexing FLDl operand descriptor
(FLD1,2,6)
generate 60 (octal) table characters
12
000000000000,000000000000 (060-067)
000000000040
(070-073)
Result - nonzero found
1
,
The highest possible value in FLDl is an octal 073, a "."
8-585
.
DZ5l-00
TCTR
TCTR
Test Character and Translate in Reverse
TCTR
165 (I)
Same as Test Character and Translate (TCT) format
FORMAT:
COD! NG FORMAT:
1
8
16
TCTR
ADSCn
(MF1)
LOCSYM,CN,N,AM
LOCSYM, RM, AM
LOCSYM, RM, AM
ARG
ARG
(Refer to Section 7 under Multiword Instructions for
description of Multiword Modification Field.)
OPERATI NG MODES:
Any
EXPLANATION:
Same as TCT except start at location YC1 + (L1-1) and
progress toward YC1.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL for MF1,
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
Tally - If the tally (L1) is exhausted and table entry is
zero, then ON; otherwise, OFF
NOTE:
Notes for TCTR are the same as for TCT.
REG2~
REG3
EXAMPLE:
1
8
16
TCTR
ADSC4
ARG
ARG
FLD1
FLD3
TTF
NULL
USE
EDEC
BSS
FLD1,6,10
TABLE
FLD3
*+2
CONST.
l6P1234567890
1
32
no modification
indexing string operand descriptor
pointer to table
pointer to character and count word
nonzero found
nonzero not found - tally runout ON
memory contents
0000001234567890
character and count 000000000012 (octal)
TABLE OCT
0,0
OCT
000000014014,000000014014
*Highest possible value (in 4-bit field) in FLDl is octal 17
USE
Result - no illegal character found
8-586
DZ5l-00
(-
TEO
TEO
TOO
FORMAT:
CODING FORMAT:
Transfer on Exponent Overflow
614 (0)
single-word instruction format (see Figure 8-1)
1
OPERATING MODES:
Any
SUMMARY:
NS
8
16
TEO
LOCSYM, RM, AM
Mode
If exponent overflow indicator ON, then Y --> C(IC)
If exponent overflow indicator ON and instruction bit 29=1
then
n
= YO-2
C(DRn) --> C(ISR); C(SEGIDn -> C(SEGID(IS»
ES Mode
If exponent overflow indicator ON, then Y16-33 --> C(IC)
If exponent overflow indicator ON and instruction bit 29=1
then
n
= YO-2
C(DRn) -> C(ISR); C(SEGIDn -> C(SEGID(IS»
EXPLANATION:
with conditional transfer instructions, if the transfer
condi tion is not satisfied (transfer does not occur), the I SR
and the SEGID(IS) are not changed. When transfer occurs, bit
29 of the instruction word affects the operation as follows:
o When bit 29 of the instruction word
SEGI D(I S) are not changed.
= 0,
the ISR and
o When bit 29 of the instruction word = 1, the DRn selected
with bits 0, 1, 2, and the corresponding SEGIDn~ are
loaded into the ISR and SEGID(IS). The transfer in this
case, is the transfer to another segment.
I
(
8-587
DZ51-00
TEO
TEO
/
If instruction bit 29=1, and if any form of indirect
addressing is specified in the tag field, then the base,
bound, and working space from DR!! (not the I SR) are used in
developing the addresses of indirect words.
When the transfer instruction attempts to load the ISR, the
ISR bit 24 (NS/ES mode specification bit) cannot be altered.
If bit 24 of the ISR before execution of the transfer is not
equal to bit 24 of the segment descriptor from the DRn, an
IPR fault occurs. The ISR bit can be altered only with the
eLI MB instruction.
I LLEGAL ADDRESS
MODI FI CATl ONS :
DU, DL I CI,
I LLEGAL REPEATS:
RPT ,RPD, RPL
lNDlCA1ORS:
Exponent Overflow - Set OFF
NOTES:
1. An IPR fault occurs if instruction bit 29=1 and the
sc, SCR
instruction attempts to load the ISR from a descriptor
that is not type T=O; or has a base that is not 0 modulo
32 bytes; or has a bound that is not 31 modulo 32 bytes.
2. A Security Fault, class 2 occurs if instruction bit 29=1
and the instruction attempts to load the ISR from a
descriptor for which flag bit 25=0.
3.
A Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the lSR from a descriptor
for which flag bit 27=0.
4.
A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the lSR from a descriptor
for which flag bit 28=0.
5.
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
,/
8-588
DZ51-00
(
TEU
TEU
TEO
FORMAT:
CODI NG FORMAT:
Transfer on Exponent Underflow
615 (0)
Single-word instruction format (see Figure 8-1)
1
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
8
16
TEU
lOCSYM,RM, AM
If exponent underflow indicator ON, then Y --> C(IC)
If exponent underflow indicator ON and instruction bit 29=1
then
n
= YO-2
C(DRn) --> C(ISR): C(SEGIDn) --> C(SEGID(IS»
ES Mode
If exponent underflow indicator ON, then Y16-33 --> C(IC)
If exponent underflow indicator ON and instruction bit 29=1
then
n
= YO-2
C(DRn} --> C(ISR}; C(SEGIDn) --> C(SEGID(IS»
EXPLANATION:
with conditional transfer instructions, if the transfer
condition is not satisfied (transfer does not occur), the ISR
and the SEGID(IS) are not changed. When transfer occurs, bit
29 of the instruction word affects the operation as follows:
o When bit 29 of the instruction word
SEGI D(I S) are not changed.
= 0,
the ISR and
o When bit 29 of the instruction word = 1, the DRn selected
with bits 0, 1, 2, and the corresponding SEGIDn, are
loaded into the ISR and SEGID(IS). The transfer, in this
case, is the transfer to another segment.
(
8-589
DZ51-00
TEV
TEV
/
If instruction bit 29=1, and if any form of indirect
addressing is specified in the tag field, then the base,
bound, and working space from DRn (not the ISR) are used in
developing the addresses of indirect words.
When the transfer instruction attempts to load the ISR, the
ISR bit 24 (NS/ES mode specification bit) cannot be altered.
If bit 24 of the I SR before execution of the transfer is not
equal to bit 24 of the segment descriptor from the DRB, an
IPR fault occurs. The ISR bit can be altered only with the
CLIMB instruction.
I LLPX;AL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
ILLPXiAL REPEATS:
RPT, RPD, RPL
INDICATORS:
Exponent Underflow - Set OFF
NOTES:
1.
IPR fault occurs if instruction bit 29=1 and the
instruction attempts to load the ISR from a descriptor
that is not type T=O; or has a base that is not 0 modulo
32 bytes; or has a bound that is not 31 modulo 32 bytes.
An
2. A Security Fault, class 2 occurs if instruction bit 29=1
and the instruction attempts to load the ISR from a
descriptor for which flag bit 25=0.
3. A Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 27=0.
4. A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 28=0.
5.
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-590
DZ51-00
(
TMI
TMI
TMI
FORMAT:
CODING FORMAT:
Transfer on Minus
604 (0)
Single-word instruction format (see Figure 8-1)
1
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
8
16
TMI
LOCSYM,RM,AM
If negative indicator ON, then Y --> C(IC)
If negative indicator ON and instruction bit 29=1 then
n
= YO-2
C(DRn) -> C(ISR): C(SEGIDn) --> C(SEGID(IS»
(
ES Mode
If negative indicator ON, then Y16-33 _> C(IC)
If negative indicator ON and instruction bit 29=1 then
n
= YO-2
C(DRn) -> C(ISR): C(SEGIDn) -> C(SEGIDUS»
EXPLANATION:
With conditional transfer instructions, if the transfer
condition is not satisfied (transfer does not occur), the ISR
and the SEGIDCIs) are not changed. When transfer occurs, bit
29 of the instruction word affects the operation as follows:
o When bit 29 of the instruction word = 0, the ISR and
SEGI D(IS) are not changed.
o When bit 29 of the instruction word = 1, the DRn selected
with bits 0, 1, 2, and the corresponding SEGIDn; are
loaded into the ISR and SEGID(IS). The transfer, in this
case, is the transfer to another segment.
(
8-591
DZ51-00
TMI
TID
If instruction bit 29=1, and if any form of indirect
addressing is specified in the tag field, then the base,
bound, and working space from DR!! (not the I SR) are used in
developing the addresses of indirect words.
When the transfer instruction attempts to load the ISR, the
ISR bit 24 (NS/ES mode specification bit) cannot be altered.
If bit 24 of the ISR before execution of the transfer is not
equal to bit 24 of the segment descriptor from the DR!!, an
IPR fault occurs. The ISR bit can be altered only with the
CLIMB instruction.
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1.
An
2.
A Security Fault, class 2 occurs if instruction bit 29=1
and the instruction attempts to load the ISR from a
descriptor for which flag bit 25=0.
IPR fault occurs if instruction bit 29=1 and the
instruction attempts to load the ISR from a descriptor
that is not type T=O: or has a base that is not 0 modulo
32 bytes; or has a bound that is not 31 modulo 32 bytes.
3. A Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the I SR from a descriptor
for which flag bit 27=0.
4. A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 28=0.
5.
An I llegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-592
DZ5l-00
TMOZ
TMOZ
TMOZ
FORMAT:
CODI NG FORMAT:
Transfer on Minus or Zero
604 (1)
Single-word instruction format (see Figure 8-1)
1
OPERATI NG MODES:
Any
SUMMMARY:
NS Mode
8
16
TMOZ
LOCSYM,RM,AM
If negative indicator ON or Zero indicator ON, then
Y --> C(IC)
If negative indicator ON or Zero indicator ON; and instruction
bit 29=1 then
n = YO-2
C(DRn) --> C(ISR); C(SEGIDn) -> C(SEGID(IS»
ES Mode
If negative indicator ON or Zero indicator ON, then
Y16-33 --> C(IC)
If negative indicator ON or Zero indicator ONi and instruction
bit 29=1 then
n = YO-2
C(DRn) --> C(ISR); C(SEGIDn) -> C(SEGID(IS»
EXPLANATION:
With conditional transfer instructions, if the transfer
condition is not satisfied (transfer does not occur), the ISR
and the SEGID(IS) are not changed. When transfer occurs, bit
29 of the instruction word affects the operation as follows:
o When bit 29 of the instruction word
SEGID(IS) are not changed.
= 0,
the ISR and
(
8-593
DZ51-00
TMOZ
TMOZ
''"-
/
o When bit 29 of the instruction word = 1, the DRn selected
with bits 0, 1, 2, and the corresponding SEGIDn, are
loaded into the ISR and SEGID(IS). The transfer, in this
case, is the transfer to another segment.
If instruction bit 29=1, and if any form of indirect
addressing is specified in the tag field, then the base,
bound, and working space from DR!! (not the ISR) are used in
developing the addresses of indirect words.
When the transfer instruction attempts to load the ISR, the
ISR bit 24 (NS/ES mode specification bit) cannot be altered.
If bit 24 of the ISR before execution of the transfer is not
equal to bit 24 of the segment descriptor from the DRn, an
!PR fault occurs. The ISR bit can be altered only with the
CLIMB instruction.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATeRS:
None affected
NOTES:
1.
IPR fault occurs if instruction bit 29=1 and the
instruction attempts to load the ISR from a descriptor
that is not type T=O; or has a base that is not 0 modulo
32 bytes; or has a bound that is not 31 modulo 32 bytes.
An
2. A Security Fault, Class 2 occurs if instruction bit 29=1
and the instruction attempts to load the ISR from a
descriptor for which flag bit 25=0.
3. A Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 27=0.
4. A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 28=0.
5.
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-594
DZ51-00
'"
/
TMOZ
TMCZ
EXAMPLES:
1
8
16
LeQ
TMOZ
2,DL
NOPLUS
32
transfer on minus or zero
plus routine
NULL
*DID TRANSFER OCCUR?
YES
TO WHAT LOCATION?
NOPLUS
(
8-595
DZ51-00
TNC
TNC
THC
FORMAT:
CODING FORMAT:
Transfer on No carry
602 (0)
Single-word instruction format (see Figure 8-1)
1
OPERA'l'I NG NODES:
Any
SUNMARY:
NS
8
16
TNC
LOCSYN,RM,AM
Node
If carry indicator OFF, then Y --> C(IC}
If carry indicator OFF and instruction bit 29=1 then
n
= YO-2
C(DRn) --> C(ISR}: C(SEGIDn} -->
C(S~D(IS)}
ES Node
If carry indicator'OFF, then Y16-33 --> C(IC)
If carry indicator OFF and instruction bit 29=1 then
n
= YO-2
C(DRn) -> C(ISR}:
EXPLANATION:
C(S~Dn}
->
C(S~D(IS)}
with conditional transfer instructions, if the transfer
condition is not satisfied (transfer does not occur), the ISR
and the ~D(IS} are not changed. When transfer occurs, bit
29 of the instruction word affects the operation as follows:
o When bit 29 of the instruction word
SEGID(IS} are not changed.
= 0,
the ISR and
o When bit 29 of the instruction word = 1, the DRn selected
with bits 0, 1, 2, and the corresponding SEGIDn:- are
loaded into the ISR and SEGID(IS). The transfer, in this
case, is the transfer to another segment.
8-596
DZ51-00
(~
TNC
TNC
If instruction bit 29=1, and if any form of indirect
addressing is specified in the tag field, then the base,
bound, and working space from DRn (not the ISR) are used in
developing the addresses of indirect words.
When the transfer instruction attempts to load the I SR, the
ISR bit 24 (NS/ES mode specification bit) cannot be altered.
If bit 24 of the ISR before execution of the transfer is not equal to bit 24 of the segment descriptor from the DRB, an
IPR fault occurs. The ISR bit can be altered only with the
CLIMB instruction.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1.
IPR fault occurs if instruction bit 29=1 and the
instruction attempts to load the I SR from a descriptor
that is not type T=O: or has a base that is not 0 modulo
32 bytes; or has a bound that is not 31 modulo 32 bytes.
An
2. A Security Fault, Class 2 occurs if instruction bit 29=1
and the instruction attempts to load the ISR from a
descriptor for which flag bit 25=0.
3. A Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 27=0.
4. A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 28=0.
5.
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
(
8-597
DZ5l-00
TNZ
TNZ
-/'
TNZ
FORMAT:
CODI NG FORMAT:
601 (0)
Transfer on Nonzero
Single-word instruction format (see Figure 8-1)
1
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
8
16
TNZ
LOCSYM ,Rl-1, AM
If zero indicator OFF, then Y --> C(IC)
If zero indicator OFF and instruction bit 29=1 then
n
= YO-2
C(DRn) --> C(ISR)i C(SEGIDn) --> C(SEGID(IS»
ES Mode
If zero indicator OFF, then Y16-33 --> C(IC)
If zero indicator OFF and instruction bit 29=1 then
n
= YO-2
C(DRn) -> C(ISR)i C(SEGIDn) -> C(SEGID(IS»
EXPLANATION:
With conditional transfer instructions, if the transfer
condition is not satisfied (transfer does not occur), the ISR
and the SEGID(IS) are not changed. When transfer occurs, bit
29 of the instruction word affects the operation as follows:
o When bit 29 of the instruction word
S~D(IS) are not changed.
= 0,
the ISR and
o When bit 29 of the instruction word = 1, the DRn selected
with bits 0, 1, 2, and the corresponding SEGIDB, are
loaded into the ISR and SEGID(IS). The transfer, in this
case, is the transfer to another segment.
8-598
DZ51-00
TNZ
TNZ
If instruction bit 29=1, and if any form of indirect
addressing is specified in the tag field, then the base,
bound, and working space from DRn (not the ISR) are used in
developing the addresses of indirect words.
When the transfer instruction attempts to load the ISR, the
ISR bit 24 (NS/ES mode specification bit) cannot be altered.
If bit 24 of the ISR before execution of the transfer is not
equal to bit 24 of the segment descriptor from the DRB, an
IPR fault occurs. The ISR bit can be altered only with the
ClJMB instruction.
ILLEGAL ADDRESS
('
MODIFICATIONS:
DU, DL, CI, SC,
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1.
S~
IPR fault occurs if instruction bit 29=1 and the
instruction attempts to load the ISR from a descriptor
that is not type T=O; or has a base that is not 0 modulo
32 bytes; or has a bound that is not 31 modulo 32 bytes.
An
2. A security Fault, Class 2 occurs if instruction bit 29=1
and the instruction attempts to load the ISR from a
descriptor for which flag bit 25=0.
3. A Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 27=0.
4. A Missing segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 28=0.
5.
An I llegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-599
DZ51-00
TOV
TOV
Transfer on Overflow
TOV
Single-word instruction format (see Figure 8-1)
FORMAT:
CODI NG
617 (0)
FORMAT:
1
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
8
16
TOV
LOCSYM, RM, AM
If overflow indicator ON, then Y --> C(IC)
If overflow indicator ON and instruction bit 29=1 then
n = YO-2
C(DRn) -> C(ISR); C(SEGIDn) -> C(SEGID(IS»
ES
Mode
If overflow indicator ON, then Y16-33 -> C(IC)
If overflow indicator ON and
n
inst~uction
bit 29=1 then
=YO-2
C(DRn) --> C(ISR)i C C(SEGID(IS»
EXPLANATION:
With conditional transfer instructions, if the transfer
condition is not satisfied (transfer does not occur), the ISR
and the SEGID(IS) are not changed. When transfer occurs, bit
29 of the instruction word affects the operation as follows:
o When bit 29 of the instruction word
SEGI D(I S) are not changed.
= 0,
the ISR and
o When bit 29 of the instruction word = 1, the DRn selected
with bits 0, 1, 2, and the corresponding ~Dn~ are
loaded into the ISR and SEGID(IS). The transfer, in this
case, is the transfer to another segment.
8-600
DZ51-00
(
TOV
TOV
If instruction bit 29=1, and if any form of indirect
addressing is specified in the tag field, then the base,
bound, and working space from DR!! (not the ISR) are used in
developing the addresses of indirect words.
When the transfer instruction attempts to load the ISR, the
ISR bit 24 (NS/ES mode specification bit) cannot be altered.
If bit 24 of the ISR before execution of the transfer is not
equal to bit 24 of the segment descriptor from the DRg, an
IPR fault occurs. The ISR bit can be altered only with the
ClJMB instruction.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL,
ILLEGAL REPEATS:
RPT ,RPD, RPL
INDICATORS:
Overflow - Set OFF
NOTES:
1. An IPR fault occurs if instruction bit 29=1 and the
instruction attempts to load the ISR from a descriptor
that is not type T=O; or has a base that is not 0 modulo
32 bytes; or has a bound that is not 31 modulo 32 bytes.
a,
SC, SCR
2.
A Security Fault, Class 2 occurs if instruction bit 29=1
and the instruction attempts to load the ISR from a
descriptor for which flag bit 25=0.
3.
A
Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 27=0.
4. A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag ·bit 28=0.
5. An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
(
8-601
DZ5l-00
TPL
TPL
I
TPL
FORMAT:
CODI NG FORMAT:
Transfer on Plus
/
605 (0)
Single-word instruction format (see Figure 8-1)
1
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
8
16
TPL
LOCSYM, RM, AM
If negative indicator OFF,. then Y --> C(IC)
If negative indicator OFF and instruction bit 29=1 then
n
= YO-2
C(DRn) --> C(ISR): C(SEGIDn) --> C(SEGID(IS»
ES Mode
If negative indicator OFF, then Y16-33 --> C(IC)
If negative indicator OFF and instruction bit 29=1 then
n
= YO-2
C(DRn) --> C(ISR): C(SEGIDn) --> C(SEGID(IS»
EXPLANATION:
With conditional transfer instructions, if the transfer
condition is not satisfied (transfer does not occur), the ISR
and the SEGID(IS) are not changed. When transfer occurs, bit
29 of the instruction word affects the operation as follows:
o When bit 29 of the instruction word = 0, the ISR and
SEGID(IS) are not changed.
o When bit 29 of the instruction word = 1, the DRn selected
with bits 0, 1, 2, and the corresponding SEGIDn~ are
loaded into the ISR and SEGID(IS). The transfer, in this
case, is the transfer to another segment.
(j
8-602
DZ5l-00
TPL
TPL
If instruction bit 29=1, and if any form of indirect
addressing is specified in the tag field, then the base,
bound, and working space from DRn (not the ISR) are used in
developing the addresses of indirect words.
When the transfer instruction attempts to load the I SR, the
ISR bit 24 (NS/ES mode specification bit) cannot be altered.
If bit 24 of the ISR before execution of the transfer is not
equal to bit 24 of the segment descriptor from the DRn, an
IPR fault occurs. The ISR bit can be altered only with the
CLIMB instruction.
ILLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT RPD RPL
INDICATORS:
None affected
NOTES:
1.
An
2.
A Security Fault, Class 2 occurs if instruction bit 29=1
and the instruction attempts to load the ISR from a
descriptor for which flag bit 25=0.
I
I
IPR fault occurs if instruction bi~ 29=1 and the
instruction attempts to load the ISR from a descriptor
that is not type T=O; or has a base that is not 0 modulo
32 bytes; or has a bound that is not 31 modulo 32 bytes.
3. A Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 27=0.
4. A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 28=0.
5.
(
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
---.
8-603
DZ5l-00
TPNZ
TPNZ
TPNZ
FORMAT:
CODI NG FORMAT:
Transfer on Plus and Nonzero
605
(1)
Single-word instruction format (see Figure 8-1)
1
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
8
16
TPNZ
LOCSYM, RM, AM
If negative indicator OFF and Zero indicator OFF, then
Y --> c(Ic)
If negative indicator OFF and Zero indicator OFF
and instruction bit 29=1 then
n = YO-2
C(DRn) -> C(ISR); C(SEGIDn) --> C(SEGID(IS»
ES Mode
If negative indicator OFF and Zero indicator OFF, then
Y16-33 --> C(IC)
If negative indicator OFF and Zero indicator OFF
and instruction bit 29=1 then
n
= YO-2
C(DRn) --> C(ISR}; C(SEGIDn) --> C(SEGID(IS»
EXPLANATION:
with conditional transfer instructions, if the transfer
condition is not satisfied (transfer does not occur), the ISR
and the SEGID(IS) are not changed. When transfer occurs, bit
29 of the instruction word affects the operation as follows:
o When bit 29 of the instruction word = 0, the ISR and
SEGID(IS) are not changed.
8-604
DZ51-00
-"
\
(
TPNZ
TPNZ
o When bit 29 of the instruction word = 1, the DRn selected
with bits 0, 1, 2, and the corresponding SEGaD~~ are
loaded into the ISR and SEGID(IS). The transfer, in this
case, is the transfer to another segment.
If instruction bit 29=1, and if any form of indirect
addressing is specified in the tag field, then the base,
bound, and working space from DR!! (not the ISR) are used in
developing the addresses of indirect words.
When the transfer instruction attempts to load the ISR, the
ISR bit 24 (NS/ES mode specification bit) cannot be altered.
If bit 24 of the ISR before execution of the transfer is not
equal to bit 24 of the segment descriptor from the DR~, an
IPR fault occurs. The ISR bit can be altered only with the
CLIMB instruction.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, a, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1.
IPR fault occurs if instruction bit 29=1 and the
instruction attempts to load the ISR from a descriptor
that is not type T=O: or has a base that is not 0 modulo
32 bytes: or has a bound that is not 31 modulo 32 bytes.
An
2. A Security Fault, Class 2 occurs if instruction bit 29=1
and the instruction attempts to load the ISR from a
descriptor for which flag bit 25=0.
3. A Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 27=0.
4. A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 28=0.
5.
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
(
8-605
DZ5l-00
TPNZ
TPNZ
/~-\
-,_
J
EXAMPLES:
1
8
16
32
EAX5
EAX6
AWDX
LDA
TPNZ
NULL
6
PLUSRT
0,6,6
5,DL
0,5,6
load address modifier into X5
load transfer address into X6
put transfer address into AR6
load +5 into A-register
transfer on plus and nonzero
zero and negative routine
*DI D TRANSFER OCCUR?
EAX2
LDX?
TPNZ
NULL
YES
PLUSRT+6
load address modifier into X2
load +4 into X?
transfer on plus and nonzero
zero and negative routine
3
4,DU
TRANS, 2
"'DID TRANSFER OCCUR?
TO WHAT LOCATION?
YES
TO WHAT
LOCATION?
TRANS+3
/
8-606
DZ51-00
I
(
TRA
TRA
TRA
FORMAT:
CODI NG FORMAT:
Transfer Unconditionally
710 (0)
Single-word instruction format (see Figure 8-1)
1
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
8
16
TRA
LOCSYM, RM, AM
Y --> C(IC)
If instruction bit 29=1 then
n
= YO-2
C(DRn) --> C(ISR); C(SEGIDn) --> C(SEGID(IS»
ES Mode
Y16-33 --> C(IC)
If instruction bit 29=1 then
n
= YO-2
C(DRn) -> C(ISR); C(SEGIDn) --> C(SEGID(IS»
EXPLANATION:
With unconditional transfer of control instructions, bit 29
of the instruction word affects the operation as follows:
a When bit 29 of the instruction word = 0, the ISR and
SEGID(IS) are not affected. An IPR fault does not occur.
a When bit 29 of the instruction word = 1, the DRn selected
with bits 0, 1, 2, and the corresponding SEGIDn~ are
loaded into the ISR and SEGID(IS). The transfer in this
case is the transfer to another segment.
If instruction bit 29=1, and if any form of indirect
addressing is specified in the tag field, then the base,
bound, and working space from DR!! (not the ISR) are used in
developing the addresses of indirect words.
8-607
DZ51-00
TRA
TRA
When the transfer instruction attempts to load the ISR, the
ISR bit 24 (NS/ES mode specification bit) cannot be altered.
If bit 24 of the ISR before execution of the transfer is not
equal to bit 24 of the segment descriptor from the DRn, an
IPR fault occurs. The ISR bit can be altered only with the
CLI MB instruction.
LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
None affected
NOTES:
1.
I
IPR fault occurs if instruction bit 29=1 and the
instruction attempts to load the ISR from a descriptor
that is not type 1=0; or has a base that is not 0 modulo
32 bytes; or has a bound that is not 31 modulo 32 bytes.
An
2. A Security Fault, Class 2 occurs if instruction bit 29=1
and the instruction attempts to load the ISR from a
descriptor for which flag bit 25=0.
3. A Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 27=0.
4. A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag-bit 28=0.
5.
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-608
DZ51-00
TRC
TRC
TRC
FORMAT:
CODI NG FORMAT:
Transfer on carry
603 (0)
Single-word instruction format (see Figure 8-1)
1
OPERATI NG NODES:
My
SUMMARY:
NS
8
16
TRC
LOCSYN, RN, AN
Mode
If carry indicator ON, then Y --> C(IC)
If carry indicator ON and instruction bit 29=1 then
n
= YO-2
C(DRn) --> C(ISR); C(SEGIDn) --> C(SEGIDUS»
ES Node
If carry indicator ON, then Y16-33 --> C(IC)
If carry indicator ON and instruction bit 29=1 then
n
= YO-2
C(DRn) --> C(ISR); C(SEGIDn) -> C(SEGID(IS»
EXPLANATION:
With conditional transfer instructions, if the transfer
condition is not satisfied (transfer does not occur), the ISR
and the SEGID(IS) are not changed. When transfer occurs, bit
29 of the instruction word affects the operation as follows:
o When bit 29 of the instruction word = 0, the ISR and
SEGID(IS) are not changed.
o When bit 29 of the instruction word = 1, the DRn selected
with bits a, 1, 2, and the corresponding SEGIDg; are
loaded into the ISR and SEGID(IS). The transfer, in this
case, is the transfer to another segment.
8-609
DZ51-00
TRC
TRC
If instruction bit 29=1, and if any form of indirect addressing
is specified in the tag field, then the base, bound, and working
space from DR!! (not the ISR) are used in developing the
addresse:s of indirect words.
When the transfer instruction attempts to load the ISR, the ISR
bit 24 (NS/ES mode specification bit) cannot be altered. If bit
24 of the ISR before execution of the transfer is not equal to
bit 24 of the segment descriptor from the DR!!, an IPR fault
occurs. The ISR bit can be altered only with the CLIMB
instruction.
I LLEGAL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1. An IPR fault occurs if instruction bit 29=1 and the
instruction attempts to load the ISR from a descriptor that
is not type T=O: or has a base that is not 0 modulo 32 bytes:
or has a bound that is not 31 modulo 32 bytes.
2. A Security Fault, Class 2 occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 25=0.
3. A Store or Bound fault occurs if instruction bit 29=1 and the
instruction attempts to load the ISR from a descriptor for
which flag bit 27=0.
4. A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 28=0.
5. An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-610
DZSI-OO
TRCTn
TRCTn
TRC'l'n
FORMAT:
CODI NG FORMAT:
Transfer on COunt n
54n (0)
Single-word instruction format (see Figure 8-1)
1
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
8
16
TRCTn
LOCSYM, RM, AM
For n = 0,1 ••• ,7 as determined by op code
If zero indicator OFF and negative indicator ON
then C(Xn) - 1 --> C(Xn)
If C(Xn) # 0, Y --> C(IC)
(/
If zero indicator OFF and negative indicator ON
and instruction bit 29=1 then
m = YO-2
C(DRm) --> C(ISR); C(SEGIDm) --> C(SEGID(IS»
ES Mode
For n
= 0,1 ••• ,7 as determined by op code
If zero indicator OFF and negative indicator ON
then C(GXn) - 1 --> C(Xn)
IF C(GXn) # 0, Y16-33 --> C(IC)
If zero indicator OFF and negative indicator ON
and instruction bit 29=1 then
m = YO-2
C(DRm) --> C(ISR); C(SEGIDm) --> C(SEGID(IS»
8-611
DZ51-00
TRTCn
TRTCn
EXPLANATION:
A 1 is subtracted from the content of Xn/GXn and the result is
loaded into Xn/GXn. Unless the content of the result in Xn/GXn
is zero, control is transferred to the location specified by the
y field. If the result is 0, the next instruction is executed.
With conditional transfer' instructions, if the transfer condition
is not satisfied (transfer does not occur), the ISR and the
SEGID{IS) are not changed. When transfer occurs, bit 29 of the
instruction word affects the operation as follows:
o When bit 29 of the instruction word = 0, the ISR and SEGID(IS)
are not changed.
o When bit 29 of the instruction word = 1, the DRm selected with
bits 0, 1, 2, and the corresponding S~Dm, are loaded into'
the ISR and SEGID{S). The transfer, in this case, is the
transfer to another segment.
If instruction bit 29=1, and if any form of indirect addressing
is specified in the tag field, then the base, bound, and working
space from DRm (not the ISR) are used in developing the addresses
of indirect words.
When the transfer instruction attempts to load the ISR, the ISR
bit 24 (NS/ES mode specification bit) cannot be altered. If bit
24 of the ISR before execution of the transfer is not equal to
bit 24 of the segment descriptor from the DRm, an IPR fault
occurs. The ISR bit can be altered only with the CLIMB
instruction.
LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, Cl, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
I
I LLEGAL EXECUTES: XEC, XED
I NDI CATORS:
Zero
Negative
NOTES:
-
If C(Xn/GXn) = 0, then ON; otherwise, OFF
If C(Xn/GXn) = 1, then ON; otherwise, OFF
1. An IPR fault occurs if instruction bit 29=1 and the
instruction attempts to load the ISR from a descriptor that is
not type T=O; or has a base that is not 0 modulo 32 bytes; or
has a bound that is not 31 modulo 32 bytes.
2. A Security Fault, Class 2 occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor for
which flag bit 25=0.
8-612
DZ51-00
(
TRTCn
TRTCn
3. A Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 27=0.
4. A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 28=0.
5.
An Illegal Procedure fault occurs if illegal address
modifications, illegal repeats, or illegal executes are
used.
EXAMPLE:
1
A
(
8
16
LDXO
10,DU
32
LDA
TRTCO
A
8-613
DZ51-00
TRTF
TRTF
TRTF
FORMAT:
CODI NG FORMAT:
Transfer on Truncation I ndicator OFF
601 (1)
Single-word instruction format (see Figure 8-1)
1
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
8
16
TRTF
LOCSYM, RN, AN
If truncation indicator OFF, then Y --> C(IC)
If truncation indicator OFF and instruction bit 29=1 then
n = YO-2
C(DRn) -> C(ISR) i C(SEGIDn) --> C(SEGID(IS»
ES Mode
If truncation indicator OFF, then Y16-33IC)
If truncation indicator OFF and instruction bit 29=1 then
n
= YO-2
C(DRn) --> C(ISR)i
EXPLANATION:
C(~Dn)
--> C{SEGID(IS»
with conditional transfer instructions, if the transfer
condition is not satisfied (transfer does not occur), the ISR
and the SEGID(IS) are not changed. When transfer occurs, bit
29 of the instruction word affects the operation as follows:
o When bit 29 of the instruction word = 0, the ISR and
SEGID(IS) are not changed.
o When bit 29 of the instruction word = 1, the DRn selected
with bits 0, 1, 2, and the corresponding SEGIDg~ are
loaded into the ISR and SEGID(S). The transfer, in this
case, is the transfer to another segment.
8-614
DZ51-00
TRTF
TRTF
If instruction bit 29=1, and if any form of indirect
addressing is specified in the tag field, then the base,
bound, and working space from DR!! (not the I SR) are used in
developing the addresses of indirect words.
When the transfer instruction attempts to load the ISR, the
ISR bit 24 (NS/ES mode specification bit) cannot be altered.
If bit 24 of the ISR before execution of the transfer is not
equal to bit 24 of the segment descriptor from the DRn, an
IPR fault occurs. The ISR bit can be altered only with the
CLI ME instruction.
(
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, 0, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1.
IPR fault occurs if instruction bit 29=1 and the
instruction attempts to load the ISR from a descriptor
that is not type T=O; or has a base that is not 0 modulo
32 bytes; or has a bound that is not 31 modulo 32 bytes.
An
2. A Security Fault, Class 2 occurs if instruction bit 29=1
and the instruction attempts to load the ISR from a
descriptor for which flag bit 25=0.
3. A Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 27=0.
4. A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 28=0.
5. An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
(
8-615
DZ51-00
TRTF
TRTF
EXAMPLE:
1
8
16
32
FLDl,O,4
FLD2,O,4
NTRUNC
move alphanumeric left to right
sending operand descriptor
receiving operand descriptor
truncation indicator OFF
MLR
ADSC9
ADSC4
TRTF
NULL
*
*
*Did transfer to NTRUNC occur?
YES
*State of truncation indicator after?
OFF
8-616
DZ51-00
(
TRTN
TRTN
TRTN
FORMAT:
CODING FORMAT:
600
Transfer on Truncation Indicator ON
(1)
Single-word instruction format (see Figure a-I)
1
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
8
16
TRTN
LOCSYM,RM,AM
If truncation indicator ON, then Y --> C(IC)
If truncation indicator ON and instruction bit 29=1 then
n = YO-2
C(DRn) --> C(ISR); C(SEGIDn) -> C(SEGID(IS»
(
ES Mode
If truncation indicator ON, then Y16-33 --> C{IC)
If truncation indicator ON and instruction bit 29=1 then
n
= YO-2
C(DRn) -> C{ISR); C(SEGlDn) -> C(SEGlD(IS»
EXPLANATION:
with conditional transfer instructions, if the transfer
condition is not satisfied (transfer does not occur), the ISR
and the SEGID(IS} are not changed. When transfer occurs, bit
29 of the instruction word affects the operation as follows:
o When bit 29 of the instruction word
SEGID(IS) are not changed.
= 0,
the ISR and
o When bit 29 of the instruction word = 1, the DRn selected
with bits 0, 1, 2, and the corresponding SEGlDn: are
loaded into the ISR and SEGlD(S). The transfer, in this
case, is the transfer to another segment.
8-617
DZ51-00
TRTN
TRTN
If instruction bit 29=1, and if any form of indirect
addressing is specified in the tag field, then the base,
bound, and working space from DR!! (not the I SR) are used in
developing the addresses of indirect words.
When the transfer instruction attempts to load the ISR, the
ISR bit 24 (NS/ES mode specification bit) cannot be altered.
If bit 24 of the ISR before execution of the transfer is not
equal to bit 24 of the segment descriptor from the DRn, an IPR
fault occurs. The ISR bit can be altered only with the CLIMB
instruction.
I LLEX;AL ADDRESS
MODI Fl CATIONS:
DU, DL, Cl, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATeRS:
Truncation - I f ON, it is turned OFF
NOTES:
1.
IPR fault occurs if instruction bit 29=1 and the
instruction attempts to load the ISR from a descriptor that
is not type T=O; or has a base that is not 0 modulo 32
bytes; or has a bound that is not 31 modulo 32 bytes.
An
2. A Security Fault, Class 2 occurs if instruction bit 29=1
and the instruction attempts to load the ISR from a
descriptor for which flag bit 25=0.
.
-. /
3. A Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 27=0.
4. A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 28=0.
5.
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
-'
8-618
DZ5l-00
/
(
TRTN
TRTN
EXAMPLE:
1
8
MLR
ADSC4
ADSC6
TRTN
TRA
16
32
FLDl,O,8
FLD2,O,6
TRUNC
TRUNC+6
move alphanumeric left to right
sending operand descriptor
receiving operand descriptor
truncation indicator ON
truncation indicator OFF
*To where was transfer?
TRUNC
*State of truncation indicator after?
MLR
ADSC9
ADSC4
TRTN
NULL
FLD1,O,8
FLD2,O,4
TRUNC
OFF
move alphanumeric left to right
sending operand descriptor
receiving operand descriptor
truncation indicator ON
no truncation routine
*Did transfer of control occur?
yes
*State of truncation indicator after?
where to?
TRUNC
OFF
(
8-619
DZS1-OO
TSS
TSS
TSS
FORMAT:
CODI NG FORMAT:
Transfer After Setting Slave
715 (0)
Single-word instruction format (see Figure 8-1)
1
OPERA'!'I NG MODES:
Any
SUMMARY:
NS Mode
8
16
TSS
LOCSYM,RM,AM
Y -> C(IC)
If instruction bit 29=1 then
n =
YO-2
C(DRn) -> C(ISR); C(SEGIDn) --> C(SEGID(IS»
ES Mode
Y16-33 --> C(IC)
If instruction bit 29=1 then
n
= YO-2
C(DRn) --> C(ISR); C(SEGIDn) --> C{SEGID(IS»
EXPLANATION:
All outstanding memory requests are checked for completion
before the Master Mode indicator is reset on the TSS
instruction.
with unconditional transfer of control instructions, bit 29
of the instruction word affects the operation as follows:
o When bit 29 of the instruction word = 0, the ISR and
SEGID(IS) are not affected. An IPR fault does not occur
even when bit 29 of the TSS instruction word is o.
o When bit 29 of the instruction word = 1, the DRn selected
with bits 0, 1, 2, and the corresponding SEGI~, are
loaded into the ISR and SEGID(IS). The transfer, in this
case, is the transfer to another segment.
8-620
DZ51-00
TSS
TSS
If instruction bit 29=1, and if any form of indirect
addressing is specified in the tag field, then the base,
bound, and working space from DR!! (not the ISR) are used in
developing the addresses of indirect words.
When the transfer instruction attempts to load the ISR, the
ISR bit 24 (NS/ES mode specification bit) cannot be altered.
If bit 24 of the ISR before execution of the transfer is not
equal to bit 24 of the segment descriptor from the DRB, an
IPR fault occurs. The ISR bit can be altered only with the
ClJMB instruction.
(
I LLEX;AL ADDRESS
MODIFICATIONS:
DU, DL, CI, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
I NDI CATORS:
Master Mode - Set OFF
NOTES:
1.
IPR fault occurs if instruction bit 29=1 and the
instruction attempts to load the ISR from a descriptor
that is not type T=O; or has a base that is not 0 modulo
32 bytes; or has a bound that is not 31 modulo 32 bytes.
An
2. A Security Fault, Class 2 occurs if instruction bit 29=1
and the instruction attempts to load the ISR from a
descriptor for which flag bit 25=0.
3. A Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 27=0.
4. A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 28=0.
5.
Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
An
(
8-621
DZ51-00
TSS
TSS
6. For a fault that occurs as a result of execution of a TSS
instruction in Master mode, the state of bit 28 (Master
Mode indicator) in the copy of the indicator register
stored in the safe store frame is as follows:
o If IPR or Fault Tag fault, caused by the tag field in
the instruction or indirect word, then IR28 = 1.
o If Bound fault, caused by attempt to access an indirect
word, then IR28 = 1.
o I f Bound fault, caused by attempt to access the target
location then IR28 = 1.
7. Use of the TSS instruction does not change the contents of
the DR or AR registers which may have been set by previous
Master Mode Entry (MNE/PMME) and/or user code.
8-622
DZ51-00
(
...
TSXn
TSXn
Transfer and Set I ndex Register n
FORMAT:
CODI NG FORMAT:
70n C(Xn); Y --> C{IC)
If instruction bit 29=1 then
n
(
= YO-2
C(DRn) --> C(!SR); C(SEGlDn) -> C(SEGlD(rS»
ES Mode
For n
= 0,1, ••• ,7
as determined by op code
00 ••• 0--> C(GXn)O-17
c(rc) + 0 ••• 01 --> C(GXn)18-35;
(no transfer of a carry from bit 18 of GXn to high-order bit)
Y16-33 --> C(IC)
If instruction bit 29=1 then
n
= YO-2
C(DRn) --> C(ISR); C(SEGlDn) --> C(SEGlD{IS»
(
8-623
DZ51-00
TSXn
TSXn
EXPLANATION:
with unconditional transfer of control instructions, bit 29
of the instruction word affects the operation as follows:
o When bit 29 of the instruction word = 0, the ISR and
SEGID(IS) are not affected. An IPR fault does not occur.
o When bit 29 of the instruction word = 1, the DRn selected
with bits 0, 1, 2, and the corresponding SEGIDn~ are
loaded into the ISR and SEGID(IS). The transfer, in this
case, is the transfer to another segment.
If instruction bit 29=1, and if any form of indirect
addressing is specified in the tag field, then the base,
bound, and working space from DRB (not the ISR) are used in
developing the addresses of indirect words.
When the transfer instruction attempts to load the ISR, the
ISR bit 24 (NS/ES mode specification bit) cannot be altered.
If bit 24 of the ISR before execution of the transfer is not
equal to bit 24 of the segment descriptor from the D~, an
IPR fault occurs. The ISR bit can be altered only with the
CLI MB instruct ion.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL,
I LLEGAL REPEATS:
RPT,
INDICATORS:
None affected
NOTES:
1. An IPR fault occurs if instruction bit 29=1 and the
CI, SC, SCR
RPD, RPL
instruction attempts to load the ISR from a descriptor
that is not type T=O; or has a base that is not 0 modulo
32 bytes; or has a bound that is not 31 modulo 32 bytes.
2. A Security Fault, Class 2 occurs if instruction bit 29=1
and the instruction attempts to load the ISR from a
descriptor for which flag bit 25=0.
3. A'Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the I SR from a descriptor
for which flag bit 27=0.
4. A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 28=0.
5. An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-624
DZ5l-00
TTF
TTF
TTF
Transfer on Tally Runout Indicator OFF
607 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
CODING FORMAT:
1
OPERATI NG MODES:
Any
SUMMARY:
NS
8
16
TTF
LOCSYM,RM,AM
Mode
If tally runout indicator OFF, then Y --> C(IC)
If tally runout indicator OFF and instruction bit 29=1 then
n
= YO-2
C(DRn) --> C(ISR); C(SEGIDn) --> C(SEGID(IS»
(
ES Mode
If tally runout indicator OFF, then Y16-33 --> C(IC)
If tally runout indicator OFF and instruction bit 29=1 then
n
= YO-2
C(DRn) --> C(ISR): C(SEGIDn) --> C(SEGID(IS»
EXPLANATION:
With conditional transfer instructions, if the transfer
condition is not satisfied (transfer does not occur), the ISR
and the SEGID(IS) are not changed. When transfer occurs, bit
29 of the instruction word affects the operation as follows:
o When bit 29 of the instruction word
SEGI D(I S) are not changed.
= 0,
the ISR and
o When bit 29 of the instruction word = 1, the DRn selected
with bits 0, 1, 2, and the corresponding SEGIDn~ are
loaded into the ISR and SEGID(S). The transfer, in this
case, is the transfer to another segment.
(-'
8-625
DZ51-00
TTF
TTF
If instruction bit 29=1, and if any form of indirect
addressing is specified in the tag field, then the base,
bound, and working space from DR!! (not the ISR) are used in
developing the addresses of indirect words.
When the transfer instruction attempts to load the I SR, the
ISR bit 24 (NS/ES mode specification bit) cannot be altered.
If bit 24 of the ISR before execution of the transfer is not
equal to bit 24 of the segment descriptor from the DRn, an
IPR fault occurs. The ISR bit can be altered only with the
ClJMB instruction.
LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPT,
INDICATORS:
None affected
NOTES:
1. An IPR fault occurs if instruction bit 29=1 and the
instruction attempts to load the ISR from a descriptor
that is not type T=O: or has a base that is not 0 modulo
32 bytes: or has a bound that is not 31 modulo 32 bytes.
I
RPD, RPL
2. A Security Fault, Class 2 occurs if instruction bit 29=1
and the instruction attempts to load the ISR from a
descriptor for which flag bit 25=0.
3. A Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 27=0.
4. A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 2B=0.
5. An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
I
\
,
~j
B-626
DZ51-00
(
..
TTN
TTN
TTN
606 (l)
Transfer on Tally Runout Indicator ON
FORMAT:
Single-word instruction format (see Figure 8-1)
CODI NG FORMAT:
The TTN instruction is coded as follows:
1
OPERATING MODES:
Any
SUMMARY:
NS Mode
8
16
TTN
LOCSYM,RM,AM
If tally runout indicator ON, then
Y -->
C(IC)
If tally runout indicator ON and instruction bit 29=1 then
n
(
= YO-2
C(DRn) -> C(ISR): C(SEGIDn} -> C(SEGID(IS»
ES Mode
If tally runout indicator ON, then Y16-33 -> C(IC)
If tally runout indicator ON and instruction bit 29=1 then
n
= YO-2
C(DRn) -'> C(ISR); C(SEGIDn) --> C(SEGID(IS»
EXPLANATION:
with conditional transfer instructions, if the transfer
condition is not satisfied (transfer does not occur), the ISR
and the SEGID(IS) are not changed. When transfer occurs, bit
29 of the instruction word affects the operation as follows:
o When bit 29 of the instruction word = 0, the ISR and
SEGID(IS) are not changed.
o When bit 29 of the instruction word = 1, the DRn selected
with bits 0, 1, 2, and the corresponding SEGIDg~ are
loaded into the ISR and SEGID(S). The transfer, in this
case, is the transfer to another segment.
8-627
DZ5l-00
TTN
If instruction bit 29=1, and if any form of indirect addressing
is specified in the tag field, then the base, bound, and working
space from D~ (not the ISR) are used in developing the
addresses of indirect words.
When the transfer instruction attempts to load the ISR, the ISR
bit 24 (NS/ES mode specification bit) cannot be altered. If bit
24 of the ISR before execution of the transfer is not equal to
bit 24 of the segment descriptor from the DRg, an IPR fault
occurs. The ISR bit can be altered only with the CLIMB
instruction.
ILLEGAL ADDRESS
MODIFICATIONS:
DU, DL, a, SC, SCR
I LLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
None affected
NOTES:
1.
2.
IPR fault occurs if instruction bit 29=1 and the
instruction attempts to load the ISR from a descriptor that
is not type T=O; or has a base that is not 0 modulo 32 bytes;
or has a bound that is not 31 modulo 32 bytes.
An
Security Fault, Class 2 occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 25=0.
A
3. A Store or Bound fault occurs if instruction bit 29=1 and the
instruction attempts to load the ISR from a descriptor for
which flag bit 27=0.
4.
A
Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 28=0.
5.
An
Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
8-628
DZ5l-00
/'
-\
\,- )
(
TTN
TTN
EXAMPLES:
1
8
16
32
F101,0,12
TABLE
F103
NMATCH
test character and translate
indexing string operand descriptor
pointer to table
operand pointer to count word
tally runout ON - nonzero entry
tally runout OFF
TO
ADSC6
ARG
ARG
TTN
NULL
USE
TABLE OCT
FLD1 BCI
BSS
F103
USE
CONST.
,,20020,020020020020,0
2, 1234567890#
1
*Did transfer occur?
no
TCT
TTN
F101,0,8
TABLE
F103
CHAROK
TRA
ERROR
ADSC4
ARG
ARG
USE
TABLE OCT
F10l
OCT
USE
test character and translate
indexing string operand descriptor
pointer to table
pointer to character and count word
tally runout ON
tally runout OFF
CONST.
,,14014,14014
022064126317
*To what location was transfer made?
8-629
ERROR
DZ51-00
TZE
TZE
TZE
FORMAT:
CODING FORMAT:
Transfer on Zero
600 (0)
Single-word instruction format (see Figure 8-1)
1
OPERATI NG MODES:
Any
SUMMARY:
NS Mode
8
16
TZE
LOCSYM,RM,AM
If zero indicator ON, then Y --> C(IC)
If zero indicator ON and instruction bit 29=1 then
n
= YO-2
C(DRn)
ES
~->
C(ISR); C(SEGIDn) --> C(SEGID(IS»
Mode
If zero indicator ON, then Y16-33 --> C(IC)
If zero indicator ON and instruction bit 29=1 then
n
= YO-2
C(DRn) -> C(ISR); C(SEGIDn) -> C(SEGID(IS»
EXPLANATION:
With conditional transfer instructions, if the transfer
condition is not satisfied (transfer does not occur), the ISR
and the SEGID(IS) are not changed. When transfer occurs, bit
29 of the instruction word affects the operation as follows:
o When bit 29 of the instruction word
SEGI D(I S) are not changed.
= 0,
the ISR and
o When bit 29 of the instruction word = 1, the DRn selected
with bits 0, 1, 2, and the corresponding SEGIDn~ are
loaded into the ISR and SEGID(S). The transfer, in this
case, is the transfer to another segment.
8-630
DZ5l-00
TZE
TZE
If instruction bit 29=1, and if any form of indirect
addressing is specified in the tag field, then the base,
bound, and working space from DR!! (not the ISR) are used in
developing the addresses of indirect words.
When the transfer instruction attempts to load the ISR, the
ISR bit 24 (NS/ES mode specification bit) cannot be altered.
If bit 24 of the ISR before execution of the transfer is not
equal to bit 24 of the segment descriptor from the DRg, an
IPR fault occurs. The ISR bit can be altered only with the
ClJMB instruction.
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, 0 ,
ILLEX;AL REPEATS:
RPT, RPD, RPL
NOTES:
1.
SC, SCR
IPR fault occurs if instruction bit 29=1 and the
instruction attempts to load the ISR from a descriptor
that is not type T=O; or has a base that is not 0 modulo
32 bytes; or has a bound that is not 31 modulo 32 bytes.
An
2. A Security Fault, Class 2 occurs if instruction bit 29=1
and the instruction attempts to load the ISR from a
descriptor for which flag bit 25=0.
3. A Store or Bound fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 27=0.
4. A Missing Segment fault occurs if instruction bit 29=1 and
the instruction attempts to load the ISR from a descriptor
for which flag bit 28=0.
5.
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
(~
8-631
DZ51-00
UFA.
UFA
UFA
Unnormalized Floating Add
435 CO)
FORMAT:
single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
[C(EAQ) + C(Y)]
I LLEGAL ADDRESS
MODIFICATIONS:
CI, SC, SCR
I LLEGAL REPEATS:
None
INDICATORS:
Zero
-
If C(AQ)
Negative
-
If
Exponent
Overflow
-
If exponent is > +127, then ON
Exponent
Underflow
-
If exponent is < -128, then ON
Carry
-
If a carry out of bit 0 of C(AQ) is generated,
then ON; otherwise, OFF
NOTES:
not normalized --> C(EAQ)
= 0, then ON; otherwise OFF
C(AQ)O = 1, then ON; otherwise OFF
1. When indicator "blt 32=1, the floating-point alignment is
hexadecimal. Otherwise, the floating-point alignment is
binary.
2. An Illegal Procedure fault occurs if illegal address
modification is used.
8-632
DZS1-00
(
UFA
UFA
(Convert from floating to fixed)
EXAMPLE:
1
8
FIXIT
MACRO
INE
FLD
FCMP
TMI
NOP
FCMP
TMI
UFA
lHE
STQ
ENDM
FIXIT
16
#1, '.EAQ. ' ,1
#1
-Ol10400,DU
2,IC
,F
=OlO7000,DU
02,IC
=71B25,DU
#2, '.QR. ' ,1
#2
FIXIT
X,I
32
2**35
-2**35
l=X
8-633
DZ51-00
UFM
UFM
UFM
Unnormalized Floating Multiply
421 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERA'1'I NG MODES:
Any
SUMMARY:
[C(EAQ) * C(Y)]
EXPLANATION:
This multiplication is executed like the FMP instruction
except that the final normalization is performed only if both
factor mantissas are = - 1.00 ••• 0. The definition of
normalization is located under the description of the FNO
instruction.
not normalized --> C(EAQ)
ILLEGAL ADDRESS
MODI FI CAT1 ONS:
a, SC, SCR
I LLEGAL REPEATS:
None
1NDI CATORS :
Zero
-
If C(AQ)
Negative
-
If C(AQ)O
Exponent
Overflow
-
If exponent is > +127, then ON
Exponent
Underflow
-
I f exponent is
NOTES:
= 0,
= 1,
then ON; otherwise, OFF
then ON; otherwise, OFF
<
-128, then ON
1. When indicator bit 32=1, the floating-point alignment and
normalization is hexadecimal. Otherwise, the
floating-point alignment and normalization are binary.
2.
An Illegal Procedure fault occurs if illegal address
modification is used.
8-634
DZ51-00
(/
UFS
UFS
UFS
Unnormalized Floating Subtract
535 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
[C(EAQ) - C(Y)l
EXPLANATION:
The two's complement of the subtrahend is first taken and the
smaller value is then right-shifted to equalize it. The
shifted-out portion is truncated and addition is executed.
not normalized --> C(EAQ)
ILLEGAL ADDRESS
MODI FI CATIONS:
CI, SC, SCR
I LLEGAL REPEATS:
None
INDICATORS:
Zero
-
If C(AQ)
Negative
-
If C(AQ)O
Exponent
Overflow
-
If exponent is > +127, then ON
Exponent
Underflow
-
If exponent is < -128, then ON
carry
-
If a carry out of bit 0 of C(AQ} is generated,
then ON; otherwise, OFF
(- ~
NOTES:
= 0,
= I,
then ON; otherwise, OFF
then ON; otherwise, OFF
1. When indicator bit 32=1, the floating-point alignment is
hexadecimal. Otherwise, the floating-point alignment is
binary.
2. An Illegal Procedure fault occurs if illegal address
modification is used.
8-635
DZ5l-00
UFTR
UFTR
UFTR
Unnormalized Floating Truncate Fraction
434 (0)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
C(EAQ)
EXPLANATION:
This instruction truncates the fraction part of the
floating-point data of C(EAQ) to obtain an integer. The
result is unnormalized and stored into C(EAQ). A proper
truncation to an integer is such that truncating the fraction
parts of two numbers with the same absolute and different
sign and adding the results produces O.
I LLEGAL ADDRESS
fraction-truncated --> C(EAQ)
MODIFICATIONS:
None. The address modification does not affect instruction
operations, but the modification is executed.
I LLEGAL REPEATS:
RPL
I NDI CATORS:
Zero
Negative
NOTE:
If C(AQ)
-
= 0,
then ON; otherwise, OFF
If C(AQ)O = 1, then ON: otherwise, OFF
An Illegal Procedure fault occurs if an illegal repeat is
used.
8-636
DZ51-00
(
XEC
XEC
XEC
716 (0)
Execute
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATI NG MODES:
Any
SUMMARY:
Obtain and execute the instruction stored at memory location Y.
EXPLANATION:
The next instruction to be executed is obtained from C(IC)+l.
This is the instruction located in memory immediately following
the location containing the XEC instruction. This does not
apply if the execution of the instruction obtained from
location Y changes the content of the IC.
To execute a repeat instruction with the XEC instruction, the
XEC must reside at an odd location. The instructions to be
repeated using the RPT, RPD, or RPL instructions must
immediately follow the XEC instruction.
With the exceptions noted in Note 1, an XEC instruction may
point to a multiword instruction. However, the descriptors for
the multiword instruction must be stored immediately following
the XEC instruction. The next instruction to be executed is
obtained from C(IC)+n+l, where n is the number of descriptors
for the multiword instruction.
(
If IC modification is used with the instruction being executed,
the value of IC will be the same as the location of the XEC
instruction.
I LLEGAL ADDRESS
MODI FI CATIONS:
DU, DL, CI, SC, SCR
ILLEGAL REPEATS:
RPT, RPD, RPL
INDICATORS:
The XEC instruction itself does not affect any indicator.
However, the execution of the instruction from Y may affect
indicators.
NOTES:
1. An Illegal Procedure fault occurs if illegal address
modification or illegal repeats are used when the XEC
instruction is executing an SPL, LPL, CLIMB, or TRCTn
2.'An Illegal Procedure fault occurs if a CLIMB is executed via
an XEC instruction.
8-637
DZ5l-00
XEC
XEC
EXAMPLE:
1
8
16
REM
REM
XEC
USE
DOlT
ADO
SBQ
USE
XEC
USE
BRANCH NOP
AOS
TRA
TRA
TRA
OOIT,7
SMARTS
FF
FF
BRANCH-l,6
32
X7 has value 0 or 1
X6 has value 1, 2, 3, 4 or 5
add or subtract
5-way branch
YERHED
FLAG2
.53
.54
WRAPUP
USE
8-638
DZ5l-00
(
~
KED
XED
...
XED
Execute Double
717 CO)
FORMAT:
Single-word instruction format (see Figure 8-1)
OPERATING MODES:
Executes in NS mode only
SUMMARY:
Obtain and execute the two instructions stored at the memory
Y-pair locations (must be even and next odd location).
EXPLANATION:
The first instruction obtained from Y-pair must not alter the
memory location from which the second instruction is
obtained, and must not be another KED instruction.
If the first instruction obtained from Y-pair alters the
contents of the instruction counter, this transfer of control
is effective immediately, and the second instruction of the
pair is not executed.
After execution of the two instructions obtained from the
Y-pair, the next instruction to be executed is obtained from
C(IC)+l. This location immediately follows the XED
instruction. This does not apply if the execution of the two
instructions obtained from the y-pair alters the content of
the IC.
To Execute Double (XED) the RPD instruction, the RPD must be
the second instruction at an odd-numbered address. When RPD
is at the odd-numbered address of the pair, the XED
instruction must be at an odd location. In this case, the
repeated instructions are those that immediately follow the
XED instruction. If RPD is specified within a sequence of
XEDs, the original and all subsequent XEDs in the sequence
must be in odd locations.
When repeat instructions RPT or RPL are executed with an XED
instruction and the first instruction specified by the XED
resides an an even-numbered location, the repeated
instruction is that immediately following the RPT or RPL.
When the RPT or RPL instruction resides at an odd-numbered
address, the repeated instruction is that immediately
following the XED instruction.
8-639
DZ51-00
XED
XED
With the exceptions noted in Note 1, multiword instructions
are executed with the XED instruction. The multiword
instruction (second instruction) must be located at an
odd-numbered address. I fit is not, an I PR fault occurs.
The data descriptors for this multiword instruction
immediately follow the XED instruction.
If IC modification is used with either of the instructions
being executed, the value of IC will be the same as the
location of the XED instruction.
I LLEGAL ADDRESS
MODI PI CATIONS:
DU, DL, CI, SC, SCR
I LI.J!XiAL REPEATS:
RPT, RPD, RPL
INDICATORS:
The XED instruction itself does not affect any indicator.
However, the execution of the two instructions from Y-pair
may affect indicators.
NOTES:
1.
An
IPR fault occurs if XED instruction is used with SPL,
or TRCTn.
LPL, CLI MB,
2. When multiword instructions other than those indicated in
Note 1 are executed with an XED instruction, the multiword
instruction must be located at an odd-numbered address
(second instruction). If it is not, an IPR fault occurs.
The data descriptors for this multiword instruction are
those immediately following the XED instruction as
indicated below:
-- XED
Descriptor-l \
Descriptor-2 > as for an SB3D instruction
Descriptor-3 /
--> LDA
SB3D
3.
An Illegal Procedure fault occurs if illegal address
modifications or illegal repeats are used.
4.
An Illegal Procedure fault occurs if execution is
attempted in ES mode.
8-640
DZ51-00
/"
-........\
XED
XED
EXAMPLES:
1
8
REM
XED
16
ENTRY, 7
32
X7 0 = 0,2,4, or 6
EVEN
ENTRY NULL
STC1
SAVEl
TRA
FIRST
STC1
SAVE2
TRA
SECOND
STC1
STC1
SAVE3
THIRD
SAVE4
TRA
FOURTH
TRA
(
8-641
DZS1-00
APPENDIX A
OPBRATI ON CODE MAPS
The operation code maps for the processor are shown in in Tables A-l and A-2.
The operation codes are separated into sections: the first section lists
operation codes with bit 27 = 0 and the second section with bit 27 = 1.
...
(
~
..
'
A-l
DZ51-00
Table A-1.
\ Lower
\3 bits
Operation Code Map (Bit 27
= 0)
S
0
1
2
ADLXO
MME
NOP
ADLX1
DRL
PULS1
ADLX2
3
4
SYNC
ADLX4
LDAC
ASX4
AOS
ADX4
6
7
\
\
\
Upper\
6 bits\
\
00
01
02
03
04
05
06
07
10
11
12
ASXO
ASX1
ASX2
PULS2
ADLX3
ADL
ASX3
ADXO
ADX1
AWCA
ADX2
AWCQ
ADX3
LREG
CMPXO
CMPX1
CMPX2
CMPX3
CMPX4
LDQC
CWL
SBLXO
SBLX1
SBLX2
SBLX3
SBLX4
SSXO
SSX1
SSX2
SSX3
SSX4
SBXO
SBX1
SWCA
SBX2
SWCQ
SBX3
SBX4
20
21
22
23
24
25
26
27
CNAXO
CNAX1
CMK
LDX1
RSW
ORSX1
CNAX2
CNAX3
LDX2
WRES
ORSX2
LDX3
RIMR
ORSX3
CNAX4
SZNC
LDX4
ORX1
SMR
ORX2
SMID
ORX3
RMID
ORX4
30
31
32
33
34
35
36
37
CANXO
CANX1
CANX2
CANX3
CANX4
LOW
LCX1
LCX2
LCX3
LCX4
ANSXO
ANSX1
ANSX2
ANSX3
ANXO
ANX1
ANX2
ANX3
ANSX4
STAC
ANX4
13
14
15
16
17
LDXO
ORSXO
RCW
ORXO
RMR
A-2
SZN
ORSX4
DOC
LCON
ADLX6
ADLQ
ASX6
ADLXS
ADLA
ASXS
ASA
ADX5
ADA
ADX6
ADO
CMPX5
CMPA
SBLXS
SBLA
SSX5
SSA
SBX5
SBA
CMPX6
CMPQ
SBLX6
SBLQ
SSX6
SSQ
SBX6
SBQ
CMPX7
CMPAQ
SBLX7
SBLAQ
SSX7
CNAXS
CNAA
LDXS
LDA
ORSX5
ORSA
ORXS
ORA
CNAX6
CNAQ
LDX6
·CNAX7
CNAAQ
LDX7
LDAQ
ORSX7
CANXS
CANA
LCXS
LCA
ANSX5
ANSA
ANXS
ANA
ASQ
LDQ
ORSX6
ORSQ
ORX6
ORQ
CANX6
CANQ
LCX6
LCQ
ANSX6
ANSQ
ANX6
ANQ
ADLX7
ADLAQ
ASX7
SSCR
ADX7
ADAQ
SBX7
SBAQ
ORX7
ORAQ
CANX7
CANAQ
LCX7
LCAQ
ANSX7
ANX7
ANAQ
DZ51-00
Table A-I (cont).
\ Lower
\3 bits
a
I
2
Operation Code Map (Bit 27 = 0)
3
4
5
6
7
\
\
\
Upper\
6 bits\
\
40
41
42
43
44
45
46
47
MPF
LDE
UFM
FSZN
SXLO
STZ
QSMP
FSTR
50
51
52
53
54
55
56
57
RPL
60
61
62
63
64
65
66
67
TZE
70
71
72
73
74
75
76
77
TSXO
RPT
FLP
TRCTO
SBAR
RPD
FLO
SXLI
SIW
FMP
FRO
MPY
RIW
SCPR
QFLO
SXL2
SFR
QFMP
DFSTR
CMG
ADE
RSCR
DUFM
DFLO
SXL3
QPST
DFMP
DFRO
FCMG
UFTR
SXL4
STT
FTR
FNEG
BCD
FCMP
NEGL
UFS
DFLP
TRCT2
STBQ
TRCT3
UMR
TNZ
RPAT
EAXI
TNC
TRC
EAX2
EAX3
ERSXI
ERSX2
ERSX3
RET
ERSXO
ERXO
ERXI
TSX1
STCA
ARt
QRL
LXLI
ARS
STXO
STC2
ERX2
TSX2
LRMB
LXL2
QRS
STX2
STCQ
TRA
LXLO
SXL6
STE
QFSTR
QFAD
TRCT4
STC1
STX1
ERX3
TSX3
LXL3
TMI
TEO
EAX4
LDI
ERSX4
STACQ
ERX4
LCPR
TSX4
LXL4
TRCT5
FDV
FSB
TPL
TEO
EAX5
EAA
ERSX5
ERSA
ERX5
ERA
TSX5
TSS
LXL5
ALS
LRS
SREG
STX4
STI
STX5
STA
LRL
GTB
ALR
STX3
A-3
DFCMG
DUFA
SXL7
DPST
DFSBI
DFAD
TRCT6
DVF
DFCMP
DFDI
DUFS
TRCT7
QFSB
DFDV
DFSB
DIV
FDI
NEG
TRCTI
STBA
FNO
EAXO
UFA
SXL5
PST
FSBI
FAD
DIS
EAX6
EAQ
ERSX6
TTF
TOV
EAX7
LOT
ERSX7
ERSQ
ERX6
ERQ
ERX7
ERAQ
TSX6
TSX7
XEC
XED
LXL6
QLS
STX6
STQ
LXL7
LLS
STX7
STAQ
QLR
LLR
DZ51-00
Table A-2.
\ Lower
\3 bits
0
1
Operation Code Map (Bit 27
2
3
= 1)
5
6
7
MPX4
STD4
MPXS
S105
MPX7
STD7
SZTL
SZTR
MPX6
S106
CMPB
SDR4
SCM
SDRS
SDR6
4
\
\
\
Upper\
6 bits\
\
00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
17
MVNEX
MVE
MPXO
S100
MPX1
STD1
CSL
CSR
MVNE
MPX2
STD2
MPX3
STD3
CMPC
MLR
MRL
SDRO
SCD
SDR1
SCDR
GSTDO
S10SA
SPDBR
STO
LPDBR
LDO
SDR2
SDR3
sam
GS104
GS102
TC'l'
MVT
LDDSA
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37
CCAe
GSTD6
TCTR
AD2D
SB2D
MP2D
DV2D
AD3D
SB3D
MP3D
DV3D
AD2DX
SB2DX
MP2DX
DV2DX
AD3DX
SB3DX
MP3DX
DV3DX
GLDD6
GLDD4
GLDD2
MVNX
DTB
CMPN
B10
GLDDO
CMPC'l'
PAS
SPCF
MVN
SDR7
CMPNX
M'l'M
MTR
A-4
DZ51-00
)
Table A-2 (cont).
\ Lower
\3 bits
0
1
2
Operation Code Map (Bit 27 = 1)
3
4
5
6
7
ADRR
ADLR
SBRR
SBLR
SPL
STP7
LPL
LOP7
\
\
\
Upper\
6 bits\
\
40
41
42
43
EPAT
LDCR
LDPR
45
46
47
STPO
STPI
STP2
LDDR
SAREG
STP3
STP4
STP5
STP6
GRS
GRL
GIS
LAREG
GLRS
GLRL
GLLS
LDPO
LDPI
LDP2
LDP3
LOP4
LOPS
LOP6
50
51
52
53
54
55
56
57
A9BD
A6BD
A4DB
ABD
S9BD
MPRR
ARAO
STTD
MRO
S6BD
S4BD
MPRS
CAMP
ARA1
STDSD
AAR1
LODSD
ARA2
AAR2
SBD
DVRR
ARA3
STTA
AAR3
TRTN
LOEAO
TRTF
LOEAl
LOEA2
EPPRO
ARNO
EPPR1
ARN1
NARO
LDDO
NARI
LDD1
LDRR
44
(
60
61
62
63
64
65
66
67
70
71
72
73
74
75
76
77
AWD
SWD
ARA5
ORRR
ARA6
ARA7
AAR4
MRS
MR6
AAR7
LOW
TMOZ
LOEA4
TPNZ
LOEA5
TTN
LOEA6
LDEA7
EPPR2
ARN2
EPPR3
ARN3
EPPR4
ARN4
EPPR5
ARNS
EPPR6
ARN6
EPPR7
ARN7
NAR2
LDD2
NAR3
LDD3
NAR4
LOD4
NARS
LDD5
NAR6
LDnG
NRA7
LOD7
SAR4
SAR5
SAR6
SAR7
LAR4
LARS
LAR6
LAR7
CMRR
ANRR
ARA4
ERRR
CLIMB
SARO
STAS
LARO
LDAS
SARI
STPS
LARI
LDPS
SAR2
STWS
LAR2
LOWS
SAR3
STSS
LAR3
LDSS
A-5
DZ51-00
APPENDIX B
OBSOLETE IHS'l'RUCl'IOH CDDES
This appendix lists instruction mnemonic codes which have either (1) been
obsoleted by new instructions or (2) been deleted from the DPS 8000 instruction
repertoire.
All hardware instructions pointed out with an (*) are not supported by the GMAP
software. Use of these opcodes are only valid in ES mode.
1. GMAP instructions which replace former instructions yielding the same opcode.
Valid DPS 8000 Instruction
Former Usage
* AHRR 535(1) AND Register to Register
CAMSl Clear Associative Memory
Segment
CAMP 532(1) Clear Associative Mem. Paged
CAMP2 Clear Associative Memory
Pages
* CMRR 534(1) Compare Register to Register
CAMSO Clear Associative Memory
Segment
* DVRR 533(1) Divide Register
CAMP3 Clear Associative Memory
Pages
by Register
SSCR 057 ( 0) set System Controller Reg.
LeCL Load calendar Clock
LIMR 553(0) Load Interrupt Mask Register
SMCM Set Memory COntinuous Mask
Reg.
LCPR 674(0) Load Central Processor Reg.
LLUF Load Lockup Fault Register
* MPPR 530(1) Multiply Reg. Pair
by Reg
* MPRS 531(1) Multiply Reg. by Reg
CAMPO Clear Associative Memory
Pages
CAMPl Clear Associative Memory
Pages
RSCR 413(0) Read System Controller Reg
RCCL Read calendar Clock
RI MR 233 ( 0) Read I nterrupt Mask Reg.
RMCM Read Memory Controller Mask
Reg.
B-1
DZ5l-00
Valid DPS 8000 Instruction
Former Usage
231 (0) Read Processor Model
Characteristics
RSW
RRES
Read Reserved Memory
--
/
"
/
SCPR 452 (0) Store CPU Register
SFR Store Fault Registers
SIW 451(0) set Interrupt Word Pair
SMIC set Memory Controller
Interrupt Cells
2. The GMAP instructions in the following list are not valid for DPS 8000 and
if executed result in an IPR fault.
ABSA 212(0)
CCAC0376(1)
CCAa 377 (1)
LBAR
230(0)
572(0)
WAB 374(1)
WAT 336(1)
LDCB
375(1)
LDFB 314(1)
LDHB 334(1)
LDBC 337(1)
LFR
316(1)
LGCOS
356(1)
LBFER 317(1)
LBPT
335(1)
LBTR
315(1)
LMBA
570(0)
LMBB 571(0)
LMSD
354(1)
LVMS 355(1)
MLDA 235(1}
MLDAQ 237(1)
MLDQ 236(1)
MMF
MR.F
360(1)
MSTA 755(1)
MSTAQ 757(1)
MSTQ 756(1)
saER
157(O}
5MBA 555(0)
5MBB 556(0)
STAC 354(0)
STBZ
157(0)
STTA 553{1}
STTD 550(1)
TTFS
524(0)
TTTL 522(0)
TTTU
LBER
TTEZ
B-2
364(1)
521(0)
523(0)
DZ51-00
/
'\
,--j
~\
~,
~
UNIFIED CHARACTER SET - ASCII SEQUENCE
MGTE
SVPeat.
HAft!
ASCII
CtlOE
t8 8
ESCDIC
CODE
t8 8
GeCD
CODE
t8 8
HBCD
CODE
t8 •
ASCII/E.CDIC
CARD CODE
GeCD
CARD
CtlOE
HBCD
CARD
CtlOE
-------------------------.------------------------------------------------------------------------------------------NUL Hu"
00 000
00 000
'I" lI7
'E lI' '2-0-'·.·.
StlH I,.,., 0' Heeding .
ot 00'
Ot 00'
IE lI. '2""
'I" lI7
II
II
II
f(
......
:t
3
3
3
:t
3
:t
3
3
3
3
et
3
3
3
3
3.8
It
3
3
3
3
:t
.3
3
3
3
3
3
Snt
£TIC
EtlT
ENG
ACK
BEL
SS
liT
LI"
VT
FI"
CR
SO
SI
OU
DC'
DCIt
DC3
DC4
HIIK
.VH
ETI
CAH
Eft
SUI
ESC
IFS
letS
IRS
IUS
I.' •
f.' •
I
2
7
•
••
7
I,.,., 0' T... t.
Ind 0' T... t.
End 0' T,..no~l.olon
E"qulr.,
Ackno,",Iedge
1.11 (Audible Signel)
leekopee.
Horlzon,.1 Tab (~unch C.rd Skip)
Line I".ed
V.,.'lc.' Tabul."on
I"o,.~ F.ed
C.,.,.le. . R.t.u,.n
Shlf, 0U't
Ihlf' In
De,. L I.. Eoc..,.
Device Con,,.ol I
Devlc. Con,,.ol I
Devlc. Cont.rol 3
D.vlc. Con,,.ol 4 (S,op)
Ho. .t.lv. Ackno,",Iodg.
SlInchronouo Idle
End 0' T,.ena~laoion I.ock
C.nce'
End 0' ....,,,....
Suba,It.U'te
Eac4Ipo
1"1 'e Sapor.'er
troup Soper.t.er
R.cord Sop.,..'or
Unl' Sop.,..,o,.
epeee. BI ...
E.. c'~.'lon '01", (ASCII)
Doubl. Guo'.
HUIIIbor • I an
00' I.r SIgn
r.,.cen' Sign
A"'PO,.o.nd
ApoOt.ropho
Le', ,.,..n,hool.
Rlgh, ,.,..n,hoala
Aa,.rlo'"
~Iuo
Co_
Hyph.". "In_
~."Iod
{:3
U1
I-'
I
oo
I
.I.ah
02
Oll
04
08
O.
07
O.
O.
OA
OS
DC
00
DE
0 ..
.0
11
.1
tll
.4
'8
,.
17
,.
,.
.A
'1
'0
'0
IE
,,.
10
.,
22
III
14
I.
I.
27
2.
I.
IA
18
IC
10
2E
2F
002
003
004
008
008
007
Oto
0"
0,2
Ot3
0'4
0'8
0'.
0.7
020
021
022
023
024
028
028
Of7
030
0"
03f
0"
034
038
Oll.
031
040
04'
04f
0411
044
048
04.
047
0.0
0.1
082
083
084
088
08.
087
02
03
37
20
2E
2F
,.
08
28
OS
DC
00
OE
OF
.0
11
.2
13
3C
3D
32
2.
•8
002
003
087
085
088
087
02.
008
048
0'3
0'4
0'8
01.
0"
020
02'
022
02:1
074
018
082
04.
030
I I 0"
3F 011
17 041
'C 034
'0 Oll8
t! 03.
tl" 031
40 'DO
41" " ,
7,. '17
7B '73
. . 133
.C "'4
.0 120
70 1,.
40 "8
.0 .38
8C "4
4E II.
88 183
80! '40
48 113
81 141
I .. 37
II" 37
II" 37
IF 37
I" 37
IF 37
tl" :t7
'I" lI7
'I" :t7
'I" 37
'I" :t7
II" lI7
.F 31
'1" 31
'1" n
'1" lI1
'1" 37
II" 37
II" lI7
'I" 37
'I"n
'1" 31
II" 31
'1" :t1
'I" lI7
'I" :t1
'I" 31
II" 31
II" lI1
'I" 31
10 20
01 lIl" 77
3E 7.
OS 'li
2a 1J:I
3C
IA
I,.
.0
20
2C
30
:t8
2A
18
31
74
32
87
3.
.8
84
.0
13
82
33
81
'E ,.
lI.
IE 3t
tE 3.
IE 38
'E :t.
IE :t.
IE :t.
IE 3t
'E :t.
IE lI.
'E lI.
.E 3.
.E 3t
.E lI.
.E lI.
• E 3t
IE 3.
,E 3.
.E 3.
IE 3t
.E lI.
.E :t.
.E 3t
1l3t
'E "
'E 3t
IE lI.
,E lI.
IE :t.
00 ,.
" liD 78
10 .8
fA 82
n 83
'0 lI8
OF 17
OA II
3C 74
'C lI4
2C 84
10 10
:t8 13
20 40
lB 33
31 81
II[
t2'2"
'2-:t·.
7"
O·S·.·.
0'8-8-.
0'7'8"
tl·.·.
'2'8-'
0-8-'
'2-3-.·.
'2-4'.-'
'2-8'.-'
12-.-'-'
12-1-'-'
.2-11-.·.·.
11-'"
I.-It- •
"'3-'
4-.·.
8-'"
1-'
0-.·.
!I
.. -.-.
~
11"-.,,
7"-'
0-1-.
11'4-'"
"'8-."
... .,... .....
" ....
,,-.'t-7-.·.
BI."
'2-7"
7-'
lI-'
It'3-'
0-4-'
12
.-.
'2-8"
'1-5"
11-4-'
'2-8-.
0-3-8
11
12-3-'
0-1
0'1-'
0"-.
lI-.
"'3-'
0-4"
'I
1"7-'
'1-.-'
0-.-'
11'f-'
"-3-'
'2-.-'
7-'
1-'
0-4-'
11-8'. 'f-4"
11-4'8 "'4-'
111-01( 'I)
'2-0
0-3-. 0-3-'
11
(11'0)(1"
12-lI-' '2-3-'
0-'
0-'
H
~
n
A'CII
COD!
18
NAME
HGT!
•
SYPeat.
..
E!IC~OI C
CODE
Ie
GeCO
caDE
,
•
..co
CaD!
Ie •
ASCII,9COIC
CARD caDE
GeCO
CARD
CODE
teeD
CARD
eaDE
--------------------------------------------------------------------------------------------------------------------0
3D 010
I
,.
,
•
••
t
7
J
(
,•
)
7
2.t •
A
B
C
D
Colon
'_I·Co'on
Lo•• Then
Equel
Gr_tor Then
QUe.tlon Mark
At Sign
,
n
£
I
N
•
H
I
J
It
L
""
G
I"
0
I'
I
T
U
v
"X
y
2
• ,
I
2
241' J
• .
Lo,t Brockot
Rovorao S'ant
Rlgh~
BrllCko~
Clrc~'lo"
Underline
Aceont
I
,
J
•
_
31 0.1
32 Ge2
33 0.3
34 0.4
31' oe8
3.088
37 081
38 010
31 011
3A 072
311 013
3C 014
3D 078
3E 078
3F 071
40 100
.. I 101
.. I 102
43 103
4 .. 104
48 IDe
4e 101
.. , 101
... 110
... 111
.. A 112
..II 11 3
"C 114
.. D lH'
.. E III
.. F It7
80 110
II 121
82 122
83 123
8 .. 12..
81 III
I I 121
87 127
81 130
I,. 131
8A 131
88 133
ee 134
eo 138
BE 138
8F 137
'0
'1
'2
'3
'4
F8
F.
"
F8
FI
1A
8E
4C
7!
IE
8F
1C
CI
C2
C3
C4
ee
CI
C7
e.
C'
01
D2
D3
D4
08
01
01
01
O'
!2
!3
E"
Ee
!I
£1
£1
EI
. . ."
, EO
1 8A
8F_ .0
310
"I
"2
383
"4
38'
".
381
370
371
172
138
114
118
188
HI?
174
301
302
303
30..
:J08
301
301
310
311
321
322
323
32..
328
321
321
330
331
342
3 .. 3
344
3 .. '
341
'41
380
3151
112
:'40
13a
'37
1815
00
01
02
03
04
08
oe
01
O'
01
OD
2E
11
3D
DE
OF
OC
11
11
13
I"
"
1.
17
"
Ie
II
22
23
24
28
28
27
2.
2.
31
00
01
02
03
04
08
08
01
'0
11
18
88
38
78
18
17
14
al
II!
23
24
28
2.
27
30
31
.. I
.. 2
.. 3
.. 4
..8
.. I
.. 7
10
"
.2
3:J 83
34 . .
38 18
I
,
J
t
•
01 01
02 02
03 03
04 0 ..
08 08
O' 08
01 01
O' 10
01 11
OC , ..
lA 32
30 10
0813
DE "
'F 37
3A 72
11 21
la 22
13 23
14 24
II 21
" 21
17 27
" 30
II 31
11 .. 1
22 .. 1
13 .. 3
2.. 4 ..
2. ...
21 .. I
27 .. ,
28 10
II 81
32 12
33 13
3 .. 14
3S 18
.. " ..
"37 81
,.
3.
OA
'F
Ie
aD
3"
00 00
10
71
12
37
341
410
72
37 11
3e 10
3t 71
I: :IF 77
, 2E 8.
I IF 87
IE 38
3E 7.
0
1
a
3
°,
..
•..
•7
••
•
I
2"
II·.·.
12-.. ••
I·.
0-'-'
0-7-8
4-'
12-1
12-a
12-3
12-..
12-'
12-.
12-7
12-.
12-e
" -1
11-1
II .,
II ...
II"
11-1
11-7
II·.
"-1
0-1
0-3
0-"
0-1
0-'
0-1
o-e
0-.
12-2-'
0-1-'
11-2-e
"·7-e
0-8-e
3
I
I
7
I
8-.
II·.·.
12-1-'
0-.·.
0
I
•
,..
3
•
.•
7
t
..
12-2-.
•••
3-'
,., •••
....
1-.
12-1
12-'
11-3
12-..
12-1
11-.
12-7
11-.
la·.
" -1
11'3
II· ..
(12HII-Ot
0-2-.
II-I
11-1
12-3
12-"
1t·1
It·.
It-7
II·.
12-t
"U·I.,
"-1 11-3
11-...
11-'
11-'
11-. 11-1
11-' 11-7
II·.
II·.
II·e
o·a
0-'
0-..
0-8
0-1
0-7
0'1
0"
1-1
l1-e
0-1
0-3
0-"
0-'
0-1
0-7
o·e
o·t
0-7-.
11-.·.
I.· .. •• (11)(11-0)
II '0
12-8-'
0-2-e 0·.·.
tt·,·.
~
111
I-'
I
0
0
"
'.
j
/\
;
/
/
~:
~,
(~
'
,
NaT!
IIYHlIeL
NAHI!
ASCII
CODE
18
•
.,.08. ,', .......0,
,.. ,....
.,".7 ,,1.....,,7
mtDlc
CODE
18
•
_CD
COOl!
18 8
teCD
CODE
18 8
ASCII/mCDIC
CARD CODE
GeCD
CARD
CODE
teCD
CARD
CODE
,--------------------------------------------------------------------------------------------------------------------'.t _
Grevo Accont
'.' b
'I.'
. ' cd
..
'3 ' .. 3
' ,
' •• 0
'.' D
' ••
'. t
'.'
'.'
' ••
, . '110
,. 'III
'A 1112
h
I
J
k
I
8Ct 'III
I
"..'
'.'
'"
'.' n
.0
.E
,F
70
'.' 0
'.' p
'.' q
'.t r
n
I
W
.
'71 " '
'.'
'.' t
I.' u
'.' v
'.' w
...
'. I
'.'
' ~,
1.2
Ie
2,' :
127 )
'.3 ~
3
DEL
Noto.
Lo't Broco
Brokon Vortlc.1 Line
"Ight Broco
Tilde
o.I.to
~
I-'
I
o
o
.72
73
7..
711
71
77
71
7.
7A
7B
7C
70
7E
'.2
'83
II..
,.S
II.
,.7
170
171
'72
173
17..
178
17.
7r: '77
17'
'0'
202
203
20..
205
20'
207
210
21 I
221
222
223
2U
225
228
227
230
231
242
2.. 3
2....
24"
2...
2.. 7
2110
2S1
300
'S'
320
2.. '
007
'F 37
""
1222
," .. 23
2..
Ie 2"
,. 2.
17 27
II '0
""
21 .. ,
22 .. 2
23 .. ,
2.. .. ..
."2.27 ...8.."7
2t '0
II .,
32 .2
:1:1 83
:I.....
,,, ."
:til . .
37
:I.
3.
o 00
'F
t 20
'F
'F
t7
70
71
00
37
..0
37
37
'E 3.
""
12"
," .. 2'
2..
'8 2"
,. 2.
17 27
,. '0
""
.1 "I
" .. 2
2' .. ,
2.. .. ..
28 .. "
28 "t
27 .. 7
2t 110
IItI
32 . ,
,:I".....••
33 . ,
3. . .
:17 t7
31 70
31 71
• '0 20
'I! ,.
- 20 "0
'E :til
'I! :til
,-t
12-0- ,
'2-0-'
'2-0-'
'2-0-"
'2-0-8
12-0-'
'2-0-7
'2-0-t
12-0-'
,a-H-'
12- II-a
"-11-3
ta-II-"
12-" -II
ta- I1-t
"-11-7
II!- II-t
12- H-'
"-0-'
"-0-3
"-0-"
"-0-"
"-0-'
" -0-7
'I-O-t
1'-0-'
12-0
12-' ,
-0
," , -0-'
12-7-'
'2-7-t
If-'
'2-2
'2-3
'2-"
'2-11
'2-'
'2-7
l2-t
'2-'
II -I
"II -a
-3
II - ..
-8
"II -t
II -7
II -t
II -I
0-'
0-3
0-4
0-'
0-'
0-7
0-'
0-'
0
12-1-1
11-0
'2-7-'
'2-t-t
12-'
'2-2
12-'
'2-"
'2-8
'2-'
12-7
If-t
12-'
11-'
" -a
" -3
II - ..
II -II
II-t
11-7
II -t
II-I
0-'
0-3
0-"
0-'
0-1
0-1
o-t
0-'
"2-0HII'
'2-'-1
CH -OH " '
'2-'-'
,. FrOlll mCDIC or A.CII to HeCD or _CD th'. ,. _ one_w_~corro.pondonco.
I. ,se do"no. tho.o ASCI' code. o. vorloblo 'or notlono' u.ogo.
3. SInco thoro I. no corro.pondlng'choroctor _ do'ou't choroctor I • •ub.t'tutod hero,
38 Cocto"Ca) 'or teCD end 37 Cocto"C\' 'or GeCO •
... In HeCD tho code '7 Coctol' !!lOy ropro.ont "2 or I
,. TH occuplo. tho • .-0 po.ltlon o. DC3. TH I. on E8CDIC control choroctor
whl'o DC' I. on ASCI' control choroctor.
e. Tho Intornol ond punchod cord codo• • hown 'or teCD ond GeCD oro 'or copltol _Iph~t'co.
7. Thoro oro tvo teeD cord code .ot. CHaCDI ond HeCD2'. tho dlf'erenco being tho cord punch ropro._tet'en
'or
~nd C-'. ond 'or C"
Ond CI'. For tho HeCDI .ot C., ond C-' oro
ropro.ontod with punch codo. '2-0 Ond "-0. whl'o C" ond CI' oro ropre.entod b~ 12 Ond 1'.
For thO HBCD2 .ot C., ond C-' oro repre.ented wIth punch code. I' ond 11,
whIle I" ond I" oro repre.ented by 12-0 ond 11-0 .
•. Tho.o oro E8CDIC control choroctor. ond ore not defined In thO ASCII .tenderd .
•. IBM do'ine. the.e E8CDIC code. o. notlon.l olphebetlc eNtend.r •.
c.,
U1
11111
I'"
'''7
ItO
7.
.,
.2
83
...
.,
II
87
,.
••
"
.2
.3
...
.S
..
.7
..
.,
A2
A:I
A..
AS
A8
A7
A8
AI
CO
.A
DO
A'
07
UNIFIED CHARACTER SET - EBCDIC SEQUENCE
NeTE
SVPWlOL
HAPfI!
mCDIC
COD£
18 8
ASCII
COOl!
18 I
nco
COol!
"I
HltCD
COD£
18 I
ASCll/mCDIC
CARD CODl!:
nco
CARD
cool!
HltCD
CARD
COOl!
--------------------------------------------------------------------------------------------------------------------NUL Nu"
00000
00000
II! :tl 11-0-1-1-'
" 37
St.rt 0' HeedIng
01 001
01 001
IE :tl 12-1-'
n
I
p
3
3
:t
$
:t,1
:t
3,1
:t
$
:t,1
3, a
3
:t
:t
:t
3
3
:t
:t
$,8
3.1
S ••
3
3,1
3
:t
3.1
S.I
3
3
3
3
3.'
:t.S
:t,.
3
:t,.
3
3
S
3
3
3,'
3,.
3
3
3
:t
~H
STI<
I!TI<
I"F
"T
LC
DEL
GI!
RL'
SI1M
VT
"soCR
SI
DLE
DCI
DC2
TM
RES
"'8S
IL
CAN
EM
CC
CUI
IfS
lOS
IRS
IUS
OS
SOS
FS
8VI"
L'
ETa
ESC
8M
CUI
ENa
ACK
BEL
.tert of T.lCt
End
TelCt
I"unch 0"
Horlzonte' Teb
Low_ C••e
Delete
Orephlc I!ec.Reveree LIne Feild
Stert
Menuel He. . . . .
Vertlcel Teb
Forlll Feild
Cerrl . . . Return
Sl:>lft Out
Shift In
Oete Link I!eo_e
Device Control I
DevIce Control I
Tepe Merk
Re.tore
New LIne
8eckepece
Idle
Cenee'
End
MIld I UIII
Cureor Contro'
CuetOlller Uee 1
Interchenge 'Ile leperator
Interchange GrouP Seperetor
Intercheng. Record Seperetor
Interchenge Unit Seperetor
DIg" Select
Stert
Slgnl'lcence
"eld Seper.tor
UNOEFI NED CODES
8¥Pe••
Line Feild
End
Tren.IIII •• Ion 810ck
Eecepe
UNDEFINED CODl!:S
UND£FINED coon
S.t "ode
Cu.tOlll.r U.. 2
UNOEF I NED CODES
I!nqulr)'
Aokn_tedge
8e"
0'
0'
0'
0'
0'
02
03
04
08
os
07
01
O'
01'
oe
OC
00
OE
OF
10
11
II
13
14
111
la
17
11
It
lA
III
IC
10
II!
"
20
2'
22
23
R4
28
2.
27
2.
21
2/\
n
2C
20
2E
2F
002
003
004
008
00.
007
010
OIl
012
013
014
018
01S
011
020
021
022
023
024
028
021
021
030
031
032
033
034
0311
03e
037
040
041
042
043
044
048
04.
041
080
081
082
08:t
084
088
08S
087
02 002
0$ 003
.e 234
0.011
•• 20S
7F 111
. , t27
10 2111
8£ 2'.
011 013
DC 014
00 018
DE D'S
OF 011
10 020
II 021
12 022
13 02:1
.0 235
a8 208
01 010
17 207
II 030
" 031
II 222
.F 217
IC 034
10 038
IE 038
IF 037
10 200
" 101
.2 202
13 R03
.4 204
OA 012
17 027
18 033
•• 110
•• 211
./\ 212
." 213
.C 214
08 008
08 008
07 001
~
U1
.....
" 31
l' 31
"
"
I'
"
"
I'
.,
l'
"
"
'I'
.,
"
IF
I'
I'
:t1
:t1
31
:t1
:t7
37
:t7
:t1
:t1
:t7
31
37
:t1
:t7
31
37
'I' 37
I' :t1
" 37
I' :t1
" 37
I' 37
I' :t1
"
l'
I'
l'
I'
"IF
'I'
l'
"
:t1
:t7
31
37
S7
37
37
37
37
:t1
" :t1
:t1
l'
"
"
"
l'
l'
'I'
'I'
IF
IF
I'
:t1
37
37
37
37
37
37
:t7
37
37
IE
IE
It
IE
IE
IE
IE
'E
IE
'E
1£
'I!
11
II!
II!
IE
II!
II!
11
II!
IE
II!
IE
IE
IE
IE
IE
IE
IE
IE
'E
IE
IE
'E
IE
IE
IE
IE
'E
IE
'E
'E
IE
'E
IE
IE
:tl
3_
:t_
:t_
:t.
31
31
:la
3a
:t_
38
3_
3a
3e
3e
:te
:tS
3e
3_
3e
31
3e
3e
3e
3e
38
38
:te
3S
3S
3.
:te
:tS
3S
3.
3.
:t.
:ts
"
:t.
3.
"3.
3.
3.
38
12-2-.
'2-:t-.
12-4-1
12-8-'
12-1-'
12-7-'
12-1-'
'1-1-1-.
11-2"1-'
12-3-1-'
12-4-1-.
12-.-_-'
12-8-'-'
12-1-S·'
12-11-1-.·.
" -1-.
'1-1-.
" -So,
"·4-.
"-11-.
1'-S-1
11-1-1
11-1-.
11-1-1-'
1'-1-1-'
ll-S-I-'
11-4-1-'
11-11-1-'
I.-e·I-'
"-7-S-'
"-0-1-.·'
0-1-.
0-2-'
0-3-'
0-4-.
0-8-'
O-S-'
0-7-'
0-1-'
0-1-1-'
0-1-.·.
0-3-.-'
0-4-1-'
0-8-1-'
0-8-.-.
0-7-8'.
I
0
0
)
"
/J
\,
NOTE:
SYMBOl.
________ 4
3
3
3
3
3,'
3,'
3,1
3
3
3
3
3,1
3
3
3
3
n
I
tn
SYN
PM
RS
UC
I!OT
CU3
DC4
NAI(
SUB
3
3
3
3
3
3
3
3
:I
•
~
7
•,
,
·
e
C
a
3
3
3
3
3
•
3
3
"7S I
2,S •
•I
t='
N
tn
~
I
0
0
~
/~
~
NAM:
!eCDIC
CODIt
. ..
,. •
ASOII
COD!
3D
"
32
33
3..
10 liD
II 221
Ie 021
13 223
I .. 22..
lIS 225
Ie 22e
0.. 00..
I. 230
II 23'
IA 232
18 233
'4 02"
'" 02B
.E
238
'A 032
10 0"0
AD 2.. 0
A, 241
AI 242
A3 2"3
A" 2....
AB 2.. 1S
A. 2"8
A1 2.. ,
AI 2BO
BII 133
2E ose
3C 01"
21 0"0
18 083
21 0.. ,
tID".
AI 2BI
AA 252
A8 1153
AC IB"
AD IBIS
AE 2'8
A,. 2B1
80 180
.1 2.,
BO 131S
14 044
2A OBI
II OBI
3B 013
SE 138
IJBCD
CODE
, •
,
HBCD
CODE
,e •
ASCII/E8CDIC
CARD CODE
'I!
II!
IE
'E
'E
'E
'E
'E
'2-"-0-'-1-'
1-'
t-I
3-'
GBCD
CARD
COD!
teCD
CARD
CODE
8'e"
8'."
1-'
'1-'-1
It-I-S
It-e-I
'2-0
0-1-1
II
0-7-'
12-'-'
,,- •
0-4-1
(12-0J ClIJ
o-e-I
7-.
11-4-1
11-'-.
,,-,,-.
"-8-.
'I -1-.
11-0
"""1-0'
11-3-.
11-4-.
It-.. -.
It-I-I
12-.-1
____________________________________________________________________________________________________________
UNDIt,.INED CODES
UNDE,.INED CODES
Synchronou. Idle
UND!FINED CODES
Punch On
"eeder Stop
Upper Ce.e
End of Trene_l.elon
UNDE,.I N!D cobn
UNDEFINED CODES
UNDE,.INED CODES
Cu.t_er U.. 3
DevIce Control 4
Negetlve Acknowledge
UNDEFINED CODES
&ub.tltute
Spece, "Ie,.
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
Cente SIgn
PerIod, Decl_e' PoInt
Le.e Then
Left Perentheel.
P'u. SIgn
Loglce' OR
A"'Per.end
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFIN!D COD!S
UNDEFINED COOES
EMcI.-etlon PoInt E8CDIC
Doller SIgn
Aeterl.k
RIght Perenthe.l.
S.-I-Colon
Loglc.' Not
31'
3e
31
"
3t
3A
38
3C
3D
3E
3F
"0
'"
'"
"3
" ..
"B
...
'"
...
DID
De,
oe2
083
oe..
oe8
Dee
0.,
010
011
012
013
014
01"
011
011
100
101
101
'03
'0"
'08
'0.
'01
"0
... ",
" "A 112
"8 .13
"C0 ""
..
Its
"E 1'"
"F
'"
eo .10
" .21
BI It I
83 123
"" II..
'B lIB
B. II.
B1 117
B•• 30
'8
'"
BA 132
811
8C
8D
e!
"F
'33
'34
"8
13.
137
,,,.t .... ""31
,,.
,,.
, ..
,,.
I ..
, ..
,,.
IF
,,.
,,.
,,.
31
31
31
31
31
31
31
31
31
31
31
,,.,,. "31
'0
,,.
, ..
,,.
1,.
,,.
,,.
, ..
, ..
, ..
OA
'8
•E
lD
30
CI 3F
.A
IF
, ..
,,.
, ..
1,.
,,.
,,.
,,.
10
31
31
31
31
31
37
:11
31
31
'I
33
3"
3B
eo
71
:12
31
31
31
31
31
31
31
31
,IC. "'4
t
18
IC
10
2E
20
83
'4
BIS
".
.0
IE
'I!
'E
'E
'E
,.
,.
,.
38
,.
3e
38
3.
31
3.
3.
38
38
31
'E
OD
IE
'E
'E
IE
'E
"
I"
3.
3.
3'
38
38
lit
lit , .
lit"
'E 38
n: 38
'E 38
" 3F
11
.8 33
3D 10
3C
'"
10 20
R 30 1e
OF 17
IE 3.
IE 3.
IE 38
IE 3.
IE 3.
'E 3.
IE 38
IE 3.
IE 38
IF 81
211 83
2C B"
'C 3"
'A 32
IE 38
.-.-.
..
eo'
1-'
'-S
1-1-'
I-I'.
3-1-.
4-t-S
"-I-S
.-1-'
1-.-.
8'e"
'I-O-I-S
'I-O-I-S
'1-0-3-S
1t-0-4-8
'2-0-8-S
'1-0-8-S
'1-0-7-S
'I-O-S-'
'1-'-8
'1-1-8
'1-3-'
'1-4-S
It-e-.
It-I-'
11-1-1
It
It-It -1-S
'1-\1-1-'
'1-11-3-.
11-11-"-.
1t-\1-e-1
1t-11-1-'
'I-It-1-'
It-" -.-.
11-1-.
"-1-1
'1-'-1
"-"-1
l1-B-.
11-.-1
11-1-.
I
..,T!
'BCDIC
CODE
NAM
HI
•
AS.II
CODE
•
oeCD
COD!
HeCD
CODE
18.
ASCI JlEBCDIC
CARD CODE
oeCD
CARD
CODE
""CD
CARD
CODE
20 ..0
3...
.E 3.
.E 36
.E 36
'E 3.
'E 3.
'E 3.
.E 38
.E 36
IE 3.
38 73
10 38
3E 7.
DE I.
IF 31
IE 38
,E 38
'E 38
'E 38
IE 3t
IE 3t
.E 3t
.E 3t
.E 3.
IE 3t
OC , ..
2A 8'
3A 12
OA I'
0813
20 '"
IE 31
11 2t
12 22
.3 t3
.4 24
.11 211
18 28
11 21
18 30
1831
IE 31
IE 3e
IE 38
IE 36
IE 3•
IE '"
11
0-1
"-0-1-1
"-0-3-1
11-0-4-1
"-0-8-1
'1-0-'-1
11-0-7-1
"-0-6-1
0-' -t
11
0-'
CII-0ttlt)
0-'
'1-1-1
0-3-t
0-4-t
O-I-t
t-t
7-'
12-t-t
0-3-t
11-8-t
O-t-.
t-.
112H.I-0'
"
-------------------------------------.------.----------------------------------------------------------------.------7
I'1lnuo Slon, Hyphon
.0 .40
8Y""CIl.
,
3
3
3
3
3
3
:I
:I
:I
i
;
n
I
CJ'\
7
3
3
3
3
3
3
3
3
3
3
,
2,1 •
2,' •
I
•
:I
Slooh
UNDEFINED CODES
UNDEFINED CODES
UNDEF I NED CODES
UNDEF I NED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
VorUce' LIne
C_
P.rcent Ston
Underocoro
Grootor Thon Slon
Quoot'on "'ork
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
Greve Accont.
Colon
NUlllbor SIgn
At Slon
Pr ,_, Apootropho
!quel Slon
Quot.etlo" "'ark.
UNDEFINED CODES
I,' e
I,' b
I,' c
',t d
• ,e e
I,'
f
I.' 0
1.' h
I,' I
,
3
3
3
3
3
UNDEFINED
UNDEFINED
UNDEFINED
UNDEFINED
UNDEFINED
UNDEFINED
COD!I
CODES
CODES
CODES
CODES
CODES
••• 41
.2· '42
. , 143
64 144
68 '40
6. '48
67 .41
ee "'0
al "'.
.A .82
6B 183
6C 184
60 "'8
aE '8e
.F .87
70 ,eo
11 181
72 182
73 183
74 114
78 188
18 ,ee
17 ,.,
16 '70
7. ''72
"
1A
,. 113
1C 114
70 118
7!: .78
71" .77
10 200
" 201
82 202
83 203
... 204
a8 208
a. 20.
., 207
a. 210
. . 211
.A 212
ea 213
ec 214
aD 218
.E 218
• F 2'7
20
2F
82
83
84
88
86
87
8a
8.
1C
2C
28
8F
3E
3F
BA
BB
80
80
8E
81"
CO
CI
C2
10
3A
23
40
21
3D
22
C3
'"~
088
081
262
263
264
268
26.
281
270
21.
174
084
048
137
018
077
272
213
214
218
27.
277
300
301
302
'40
012
043
100
041
078
042
303
IA t2
3...
'1" 31
'1" 37
II" 37
'1" 37
'I" 37
'1" 37
'1" 37
'1" 37
'1" 37
38 73
3C 7..
• 3A 12
DE 18
01" 17
II" 37
'1" 37
'I" 37
'I" 37
II" 37
II" 31
'1" 37
'I" 37
'1" 37
, .. 37
00
'"
08 13
OC 14
21" 11
3D 78
3! 78
IF 37
It
"
t2 '.42
12 22
""
13 .43
.4 .44
.8 148
••• 4.
t1 .41
.e 180
e. 304
""
C4
C8 308
C. 308
C7 307
C' 310
C' 311
~
....I
(J"I
0
0
\
)
1323
14
18
1.
11
18
II
IF
IF
II"
'1"
IF
IF
24
28
2t
27
30
31
:J1
31
31
37
31
37
II-tt
0-3-t
0-4-'
0-8-'
0-'-'
0-7-'
'2-11-0
12-11-0-' -I
12-11-0-1-1
'2-" -0-3-1
12- 11-0-4-1
11-"-0-1-1
11-" -0-1-1
'2-tl-0-7-1
• 2- 11-0-t-1
'-I
1-'
3-'
4-'
I-t
.-.
7-'
12-0-1-'
12-0-1
12-0-1
'2-0-3
"-0-4
'2-0-8
'2-0-t
11-0-7
12-0-'
IZ-O-'
12-0-2-1
12-0-3-e
12-0-4-'
12-0-11-'
12-0-'-'
12-0-7-'
12-7-' 11-1-'
4-t
0-'
'1-2-'
3-'
0-2-'
'1-7-' 2-'
0-8-' 3-'
0-'-' 1'-8-'
..
-.
11-1
12-1
12-3
'2-4
'2-8
'2-'
'2-7
12-t
12-1
11-1
12-1
11-'
'2-4
11-8
12-'
12-1
12-t
11-'
......
;
\
~,
'
NeTI!
SYI'I80L
!8CDIC
C"DE
18 8
NAMI!
Asdll
C"DE
18 8
/..-.."
OBCD
CODE
18 8
. .CD
COOl!
18 8
ASCII/!8CDIC
CARD CODI!
OBCD
CARD
C(JDE
. .CD
CARD
C(JOE
---------------------------------------------------------------------------------------------------------------------
It
I,' J
"e k
UNDEFINED C"DES
',. I
I,e
I,'
1,.
I,'
I,'
I,e
3
:t
3
3
:t
3
:t
n
I
-...J
1,'
I,'
I,'
I,'
l,e
1, e
I,'
I,'
3
3
It
3
It
3
It
t:1
lJ1
I-'
I
a
a
0
p
q
r
UHDI!FINED
UNDEF I NED
UND!FINED
UNDEFINED
UNDEFINED
UNDEFINED
UNDEFINED
It
It
N
III
"
3
3
3
3
3
3
3
3
3
3
3
3
3
3
CODES
CODES
CODES
C(JDES
C(JDES
CODES
C(JDES
Tilde
•
,
U
v
v
Ie
W'
.:
UNDEFINED
UNDEFINED
UNDEFINED
UNDEF I NED
UNDEFINED
UNDEFINED
UNDEF I NED
UNDEFINED
UNDEF. NED
UNDEFINED
UNDEFINED
UNDEF I NED
UNDEF I NED
UNDEF I NED
UNDEF I NED
UNDEFINED
UNDEFINED
UND!FINED
UNDEFINED
UNDEFINED
UNDEFINED
UNDEFINED
C"OE8
C(JDE.
C"DES
C"CIE.
CODE.
CODES
C"DES
CODES
C"DES
C"DES
C"DES
C"CIES
CODES
CODES
CODES
C"DES
C"DES
C"DES
C"DES
C"DES
C"DES
C"DES
.0
11
.2
13
...
.e
•e
11
..
II
.A
18
.C
.0
'I!
'1'
AO
AI
A2
A3
A..
Ae
Ae
A1
Aa
AI
AA
A8
AC
AD
AE
AI'
80
81
82
8:t
8..
8e
8.
81
81
8.
8A
88
lie
80
8E
III'
220
221
122
22:t
22..
228
22e
221
230
231
232
233
23..
238
238
231
240
241
2.2
2.3
2....
24.,
2.e
2.. ,
280
lei
1112
283
284
288
2811
187
2110
1.1
2112
2113
2114
2e8
21111
2111
210
211
212
213
21..
218
218
211
CA
eA
e8
ec
eo
eE
eF
10
11
12
C8
tt
CD
CE
CF
DO
D.
1E
1:t
:t12
le2
1113
III ..
11111
11111
1111
leo
'"
182
313
314
31 e
31e
:t11
320
321
11e
183
,.. ".
,., Ie.,
18 lee
n le1
71 110
71 171
1A 112
02 322
D:t 323
0.. 32.
Oil 325
011 328
01 321
DI :t:to
O. :t31
OA 332
DB :t33
DC 33..
DO :t:te
DI! 3311
OF 331
EO 3 .. 0
E I 3.. I
EI :t.. 2
E:t :t.. 3
E.. :t4"
E8 :t .. s
Ell 3411
E1 341
IF :t1
21 .. 1
21 42
23 43
24 ....
211 48
2e ...
21 .. ,
2.80
21 81
I I' :t1
"I' :t1
:t1
I' :t1
IF :t1
I' :t1
IF :t1
I' 31
32.,
:t:t e3
3.. e.
38 a.,
:te ee
:t1 81
:te
:tt
IF
tF
IF
IF
'I'
'I'
'I'
.,
IF
IF
10
11
37
37
:t:t
3..
3e
3a
:t1
:t1
:te
:tt
IE
II!
II!
IE
31
'I!
:t1
:t1
:t1
31
:t7
31
"IF :t1
37
IF
IF
I'
I'
IF
I'
IF
I'
l'
.F
II!
21
22
23
2..
25
2e
21
2.
2.
IE
II!
II!
II!
II!
IE
II!
IE
32
37
:t7
31
31
:t1
31
:t1
31
31
31
II!
II!
IE
IE
IE
II!
U:
IE
IE
IE
IE
IE
IE
IE
IE
IE
IE
3.
.. I
.. 2
.. :t
.. ..
.. e
...
41
80
el
:t.
:t.
:te
3e
:te
:te
:te
3e
e2
.3
• ..
e8
.e
e7
10
71
:te
:te
3'
31
31
311
:te
:te
:te
:t.
:tl
311
311
311
311
3.
311
311
311
311
311
311
12-11-1-'
12-11-1
12-1I-a
'2- 11-3
12-11-"
12-II-e
12-1 - •
12-" -1
12-11-'
12-11-'
12-11·2-'
I!·" -3-'
1!-I1-"-'
12-I1-e-.
12·" -e-a
12-11-1-a
11-0-1-'
11-0· I
11-0-'
11-0·3
11-0-4
" ·0-8
11-0-'
11-0-7
II-o-a
" -0-'
It-0-2-'
11-0-3·'
11-0-.. ••
'I-o·e·.
" -0·.·.
11·0·7-11
11·11-0-1-1
12·11-0· ,
12-II·0·!
12-" -D-3
12-" -0-"
12·" ·0-8
12-" -0-11
12-" -0-7
12-11·0·'
12-11-0-'
12-11-0-2-'
12-II-O-:t-'
12-" -0-"-'
12-11-0-8-11
12- II -o-e-I
12-11-0-7-1
" -1
11-2
1I-:t
"II-a
-1
11-'
11-1
11-.
II-:t
II -..
l1-e
11-'
" -1
12·7·.
o-a
0-3
0-4
o-e
0-'
0-7
0-'
0-'
,,-.·a
0-1
0·3
0· ..
o-e
0-,'
0-1
0-'
0-'
11-"
l1-e
...
" -. "" -
...,TE
Syl't!lClL
EBCDIC
CODE
18 8
NAHE
ASt:1 I
CODE
18 8
"CD
COOlE
18 8
HeCD
CODE
18 8
ASCI JlEBCDIC
CARD CODE
"CD
CARD
CODE
teCD
CARD
CODE
--------------------------------------------------------------------------------------------------------------------Open I no Brece
•
A
B
C
0
E
P'
,
II
H
I
3
3
3
3
3
1,1 I
UNDEF I HIED CODES
UNOIEFI NED CCIOES
UNDEFI NED COOES
UNDEFlm:O CODES
UNDEFINED CODES
UNDEFINED CODES
C\oelna Brece
.J
K
L
H
N
n
I
CD
,.
CI
Q
3
3
3
3
3
3
3
R
,
UNDIEF I HIED coon
UNDEFINIED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
UNDEFINED CODES
Reveree SIen~
UNDEFINED CODES
S
T
U
!3
E4
IES
Ell
1E7
y
W
M
y
,,
,,
3
3
~
U1
2
CO
CI
C2
C3
C..
C8
C8
C7
C8
C.
CA
Cit
CC
CO
CIE
CF
DO
01
02
03
0 ..
011
D.
07
D.
D.
DA
DB
DC
00
DIE
Of'"
\ EO
El
lEI
U
UNDEFINIED
UNDEFINED
UNDEFINED
UNDEFINED
UNDEFINED
UNDEFINED
COOIES
COOES
CODES
CODES
CODES
CODES
U
EA
£8
Ee
lEO
:tOO
:t01
:t02
303
30"
308
308
307
310
311
"2
3"
" ..
318
31.
317
320
321
322
323
32"
32S
328
327
330
331
332
333
33"
33S
338
331
3 .. 0
34.
342
3"3
3 ....
34e
3...
3 .. 7
3eO
"
"
382
3e3
3e..
311e
!E 388
IEF 387
7B
41
42
4:t
....
.. 8
.. 8
.. 7
.. 8
...
Ell
U
EA
IEB
EC
lEO
70
.. A
.. B
"C
.. 0
.. E
4,.
eo
e1
S2
IEIE
IEF
FO
F'
,.2
P'3
\ SC
'F
S3
S"
liS
Sll
e7
el
ee
eA
F..
Fe
F8
F1
F.
F.
17:t
101
102
10:t
10..
108
108
107
110
III
3eo
3e1
382
383
38"
3""
1711
112
113
, ...
1111
11.
117
120
121
122
3S.
387
3.0
381
382
3.3
13..
237
tl3
12"
lIa
'28
127
130
131
"2
, ...
38e
3••
387
310
371
o 00
11
12
"
1"
18
18
17
00
'I
22
23
2"
28
28
17
It :to
I. 31
1F 37
I,. 37
IF 37
I,. 37
I,. :t7
I,. 37
t 20 .. 0
21 "I
22 .. 2
23 "3
2.. 4..
211 ..a
2... 8
27 .. 7
21 eo
28 SI
I,. 31
I,. 31
I,. 31
,,. 31
,,. 31
I,. 37
\ 'F 31
.,. 37
32 et
33 t3
3.. I"
3' 'S
38 ••
37 87
38 70
3. 11
IF 31
IF 31
IF 37
IF 37
'F 37
.F 37
• 10 20
11 21
12 22
13 23
, .. 2..
"' 28
1.
28
17 27
II 30
1831
1IE 3.
:Ie
'E :Ie
IE 3.
IE 3.
11E 38
- 20 .. 0
21 '"
22 .. 2
23 .. 3
'E
12-0
12-1
12-2
12-3
12-"
12-8
12-.
12-7
II-t
12-.
12-0-2-t-t
'2-0-'-t-t
12-0-.. -.-t
tI-0-a-8-.
tI-0-.-8-.
12-0-7-8-.
11-0
II - I
11-2
" -3
lI-e
11-.
11-1
11-1
,...... " -..
2S
2.
27
28
2.
IE
11E
IE
IE
"S
"8
.. 7
eo
SI
3.
38
31
3.
38
3.
8.
38
.2
11E
.IE
, 2E
lIE
32
33 t3
.
,..'5 .,.
38 .1
37 81
38 70
3811
IE
.IE
.E
IE
IE
IE
3.
38
3.
38
38
38
11-.
12-11-'-t-'
12-"-3-'-'
12-11-"-'-.
, 2-11-S-'-.
'2-'1-8-1-.
12-It-7-.-.
0-2-8
" -O-I-t
0-2
0-'
0-4
o-e
o-e
0-7
O-AI
0-.
1'-0-1-'-'
11-0-'-t-'
1'-0-.. -t-'
It -O-II-t-t
1'-0-8-1·'
'1-0-7-8-'
0
12-1
12-2
12-:t
12-"
12-e
12-.
12-7
12-t
12-.
(12-0H 11'
12-1
12-2
12-3
tI-..
12-e
12-.
12-7
12-t
12-.
11-0
11-'
H -I
" -3
11-"
11-.
11-.
" -7
" -I
.11-0)(11)
H -,
H -I
" -3
H-"
11-.
"
-.
11-'
11-7
II -t
H-.
11-7-' It-.-t
0-'
0-'
0-"
0-'
o-e
0-7
O-t
0-.
0-1
0-3
0-"
0-'
o-e
0-7
o-t
0-'
~
I
0
0
('
\
"
./
./
~TI!:
NAMP:
SYI180l
0
e•
3
•
••
8
8
7
3
3
3
3
3
3
[Ill
No~e.
n
I
~
~
U1
I-'
I
o
o
..-...
d"iii',
.~
long Ver~Icel Herk
UNOE'" NED CODES
UNOE'" NED CODES
UNDE'" NED CODES
UNDEFINED CODES
Elah~ One.
!8COIC
CODE
18 II
Alltll
CODE
III II
08CO
CODE
18 8
HaCO
CODE
111 II
ASCII/E8CDIC
CARD CODE
08CD
CARD
CODE
. .CD
CARD
I'D 3110
1'1 381
1'2 382
1'3 3113
I'.3U
1'8 388
1'8 388
'7 387
I'. 370
'1 371
I'A 372
'8 313
I'C 374
I'D 318
I'E 378
1'1' 377
30 080
00
01
02
03
O.
08
08
07
O'
01
I'
.,.
.,.
11'
'1'
'1'
00
01
02
03
04
Oll
08
07
O'
01
IE
'E
'E
.E
'E
IE
0
0
0
31
32
33
34
38
38
37
3.
31
FA
1'8
I'C
I'D
FE
1'1'
081
082
083
084
088
086
087
070
071
372
313
314
31"
318
377
00
01
02
03
O.
08
08
07
10
11
37
37
37
31
37
37
00
01
02
03
O.
Oll
08
07
10
11
38
38
31
31
38
38
I
2
3
4
8
8
7
••
le-l'-O-I-II-'
'2-11-0-'-11-'
'2-1'-0-.-'-'
12-n -0-8-'-'
12-1'-0-1-'-'
12-1'-0-7-'-1
e•
3
4
8
I
7
••
coot!:
I
e
3
4
It
I
7
•
1
.: I'rOM [8CDIC or ASOII ~o HaCD or -BeCD ~hl. I. e one-wev corre.pondence.
2. ISO de'ln•• ~h••• ASCII cod•• e. v.rl.ble 'or ne~lonel u •• ge.
3. SInce ~here I. no corre.pondlng ch.r.c~er e de'eul~ cherecter I • • ub.tl~uted here:
38 loc~el'(~' for HeCD end 31 (octel'I\' 'or 08CD.
•. In HaCD ~he code '" (octell mev repre.ent 1/2 or I
8. TM occuple. the .eme po. It Ion e. DC3.
TH I. en E8CDIC control cheracter
while DC3 I. en ASCII control cherecter .
•. The Internel end punched cerd code • • hown 'or HaCD end 08CD ere 'or cepltel elphebe~lc••
7. There ere two HaCO cerd code .et. CHaCDI end HeCD21, ~he dl"erence being the cerd punch repre.entetlon
'or 1+' end I-I, end for ITI end III.
I'or ~he HeCOI .e~ 1+' end 1-' ere
repre.ented with punch code. 12-0 end "-0, while IT' end (I) ere repre.ented bV .2 end ••.
I'or the HeCD2 .e~ 1+1 end 1-' ere repre.en~ed wl~h punch code. 12 end 11,
whIle '" end (!I ere repre.en~ed bV 12-0 end II-D .
•. The.e ere EBCDIC con~rol cherecter. end ere not,de'lned In the ASCII .tenderd .
•. IBM de'lne. ~he.e EBCDIC code. e. netlonel .Iph.betlc .M~ender •.
UNIFIED CHARACTER SET - GBCD SEQUENCE
HClrr
SVI18tn.
G8CO
CtlDE
18 8
NAME
HBcd
Ctlot
18 8
ASCII
CtlOE
18 8
E8COIC
CtlDE
18 II
IJ8CD
CARD
CtlDE
HBCD
CARD
CODE
ASCII/EBCDIC
CARD ccmE
------------------------------------------------------------------------------------------------------------ ---------
,
,.•
0
e
•
•
••
7
8
t
.,
)
7
Lett .r""'e~
NUlllber SID...
A~ SIO'"
Colon
Greeter Then
Que.~lo... Mark
Spece, 81 ....11.
A
•
.
C
D
n
I
It
I-'
0
G
H
I
a
4,7
c
"
t
Al!lper ••nd
".rlod
RIOh~ 8reck.~
Lef~ ".r.nthe.l.
L... Tha"
Rev.r •• St .... ~
Upward Arrow
J
K
L
".,N
,.
Q
R
7
••
J
~
Hyphan, .. I nus
Dot tar lID...
A.~.rl.k
RIOh~ Par."~ha.l.
I_I-Coto ...
Apoatrophe
,
t
00
01
02
03
04
08
De
07
O'
O.
OA
08
OC
00
OE
OF
10
11
12
13
14
18
III
17
III
I.
lA
18
'C
10
It
00
01
02
03
04
08
De
07
10
11
12
13
14
18
1.
17
20
21
22
23
24
28
28
27
30
31
32
33
34
38
311
, ... 37
20 40
II 41
22 4.
23 43
24 44
t8 48
2. 4 •
27 47
2880
28 III
IA 82
28 e3
2C 114
20 1111
2E 1111
2F 87
~
f
00
01
02
03
04
08
08
07
De
00
01
02
03
04
08
08
07
10
31'"
2A
3A
OC
OE
IF
00
11
It
13
14
'"
18
17
18
I.
OF
18
21"
3C
30
77
82
72
14
1.
37
18
II
22
23
24
28
2e
27
30
31
17
33
87
14
.0
811
38
41
42
43
44
48
4.
47
80
81
40
113
114
34
32
12
o.
2£
IE
tl
22
23
24
28
28
27
28
28
20
28
2C
lC
lA
OA
11
'0
31
32
3'
34
'"
3.
37
"
3.
88
23
40
3A
3E
3 ..
to
41
.. ,
43
44
48
4.
.. 7
411
48
211
2t
80
.11
3C
, 8C
• 8E
4A
48
4C
40
4t
4F
80
81
82
20
24
2A
211
38
27
oeo
081
082
083
084
oln,
088
0.7
070
071
133
043
100
072
07e
077
040
101
lot
103
10..
10e
10.
101
110
III
0411
0811
'38
080
074
134
1311
112
113
114
118
111
117
120
121
122
0811
044
0112
081
073
047
FO
Fl
F2
F'
F4
1'"11
1'"8
1'"7
1'".
....
, 4A
78
7C
7A
eE
eF
40
Cl
CI
C3
C4
C8
ce
C1
CII
C.
80
4.
8A
40
4C
, EO
8F
DI
Ot
03
D4
Oil
De
07
0'
011
80
118
IIC
80
5!
70
'80
381
382
383
384
365
388
387
370
371
112
173
'74
172
11'.
1117
100
301
30t
303
304
308
30e
301
310
31 I
120
1'3
132
118
114
340
137
321
321
323
324
328
328
327
330
331
140
133
134
1311
138
175
,
.
,
•
•7
•7
8
t-II'
3-11
4-11
e-II
e-.
7-.
8t.,.,
It-I
1'-t
12-3
12-4
1.-e
12-'
11-7
12-11
12-.
12
11-3-8
12-4-11
12-8-11
12-'-'
11-7-11
11-0
11 -1
11-t
11-3
11 -4
l1-e
11-'
11-7
II-II
II-II
11
'1-3-'
11-4-11
11-11-11
II-II-II
11-7-11
8
0-7-11
11-2-11
0-1-11
4-11
II-II
CltlClt-OJ
"-II
'-11
o-e-II
0-7-11
.lenk
.lenk
0
t
3
e
•
0
3
4
e
•
It-I
11-1
It-3
12-"
11-8
1.-'
11-1
1.-'
12-.
7·11
'2-3-11
(11)111-0)
0-4-11
8-'
11-11-'
12-11-11
11 -1
,
0
•
3
4
e
•7
••12-2-8
:J-II
12-1
12-t
11-3
12-"
12-e
It-.
11-1
I.-II
It-8
It
11-3-11
II-I-II
12-8-'
U!-4-.
0-2-11
11-7-11
11-1
l1-t
11-3
11-3
11-4
11-"
11-8
l1-e
II-II
" -II
11-7
11-7
11-11
11 -II
11-.
11-11
"'-0)(11) 11
11-3-e
11-3-'
11-4-11
11-4-'
12-4-'
'1-8-11
12-2-11
11-.-11
2-11
e-II
11-'
01
I-'
I
0
0
'"
/
;,"--'\
tmTE
GeCO
CODE
18 8
NAME
SYt180l
......
Hecl)
COD6
18 8
/"..,..
ASCII
CODE
18 8
EeCOIC
CODE
18 8
IJ8CO
CARD
CODE
HBCO
CARD
CODE
ASCII/BCOIC
CARD CODE
,--------------------------------------------------------------------------------------------------------------------+
I
S
T
U
"'U.
SI •• h
V
W
II
..,
.
l
,
•
Not ••
n
I
I-'
I-'
l.ft A,.,.ow
C_.
p.,.c.nt SIgn
Equ.I
Ooubl. Ouot.
Exclam.tlon "oInt CASCIII
30 80
31 .1
32 82
33 83
3 .....
38 .8
38 8'
37 .7
3' 70
38 71
.. 3,. 12
38 73
3C 7"
30 78
3E 7e
3F 77
10 20
31 .1
32 .2
33 .3
3 .....
38 .8
38 8'
37 87
3. 70
38 71
3E 7.
38 73
10 3"
08 13
20 88
.. 30 78
'0,.
CO,.,.••
'0,.
'0,.
r.
~
I
o
o
083
2F 081
83 In
84 12 ..
""
S.
'"
S8
S8
"A
SF
2C
2"
30
22
CI 21
128
12'
127
130
131
132
137
0""
0 .. "
0711
0 .. 2
04'
4E
.1
E2
E3
E..
E"
E.
E7
E.
U
.0
'8
'C
7E
7F
4F
'"
141
3 .. 2
3"3
3 ....
3 .. 8
3 .. '
3 .. ,
3"0
3"1
IS"
1"3
HI"
17.
177
1"
12-0
0-1
0-2
0-3
0-"
0-8
0-.
0-'
0-1
0-1
0-2-1
0-3-e
0-"-.
0-8-1
o-e-e
0-7-.
'12-01'121
0- I
0-2
0-3
0-"
0-8
0-.
0-7
0-1
0-1
o-e-I
0-3-e
12-8-1
3-a
II-e-I
o-e-.
12-e-8
0-1
0-2
0-3
0-"
0-8
o-e
0-'
0-1
0-1
0-"-1
0-3-1
0-"-.
e-I
7-8
12-'-.
1. F"~ EeCOIC or ASCII to HBCO or GeCO thl. I • • on.-w.v corr •• pond.nc•.
I. ISO d.' In•• the •• ASCII cod• • • • v.,.Iebl. fo,. n.tlon.' u •• ge.
3. Slnc. th.,.. I. no
pondlng ch.,.ect.,. • de'.ult ch.,..ct.,. I • • ub.tltuted he,.e:
38 Cocte'Icdl
HeCO end 37 (oct.'I(\I for GBCO.
... In HeCO tho cod. e7 (octell Mev ,..p,. ••• nt 1/2 0,. I
e. TH occupl •• the .am. po. It Ion •• DC:).
TH I • •n EBCDIC control cherect.r
whll.OC3 I • •n ASCII control ch.,..ct.,..
I. The Int.,.n.' .nd punch.d c.rd cod• • • hown
HBCO .nd tJeCO er. 'or ceplt.1 elphebetlc •.
1. Th.,. • •,.. two HeCO c.,.d cod• • • t . CHBCDI .nd HBC02l, the dl".,..nc. b.lng the c.,.d punch repr •••nt.tlon
C+I .nd (-I, .nd
('I .nd (II.
Fo,. the HeCOl •• t (+1 .nd (-I .,..
rep,. ••• nt.d with punch cod•• 12-0 .nd 11-0, whll. ('I .nd (II er. rep,. ••• nted bV 12 .nd II.
Fo,. tho HBC02 •• t (+1 .nd (-I
,..p,. ••• nt.d with punch cod•• 12 .nd 1',
whll. (tl .nd (!I .,.. r.pr ••• nt.d by 12-0.nd 11-0.
e. Th••• •
EBCDIC control ch.,..ct.,. • •nd .,.. not d.'ln.d In the ASCII .t.nd.,.d .
•. IBH d.' In•• tho . . EBCDIC cod• • • • n.tlon.I .Iph.b.tlc .Mt.nd.,. •.
'0,.
U1
f-J
n
.r.
UNIFIED CHARACTER SET - BBeD SEQUENCE
HaTE
SYMBOL
sectl
coot
•• e
HeCO
CODE
NAP'IE
•• e
ASCII
CODE
I. e
E8COIC
CODE
•• •
HeCD
CARD
CODE
seco
CARD
CODE
ASCII/BCOIC
CARD CODE
--------------------------------------------------------------------------------------------------------------------00 00
01 01
0202
03 03
04 04
00 00
08 O.
01 01
O. 10
01 "
OA 11
08 13
OC 14
00 18
OE 18
OF 11
10 20
11 21
II 22
13 23
14 2.
III 20
18 28
11 R1
18 30
IS 31
I,. 32
0
1
a
3
4
e
a
1
•S
•·
~
7
•,.•
•
Apo.~"ophe
Ique'
Colon
Spltee, 81e. .
Gree~er Then
Ah!per.end
,.Iu.
C
n
I
......
0
E
F
N
II
H
I
1_I'Coion
,.."Iod
)
•,
IS
7
1
, . 33
IUah~ "_.n~he.l.
"."c.n~ Sign
elo••d 80M
Que.~ I on "'rk
Hyphen, "Inu.
J
K
L
",.
N
D
Q
R
•8
•
f
4,7 I
~
U1
Nwober Sign
Ooller SIgn
A.~.rl.k
Double Quo~e
No~ Equel
EMcl.~.~lon Poln~
(E8COIC)
Ie
10
IE
IF
20
21
22
13
24
2e
28
27
2.
21
2A
28
2C
20
f 2E
I 2F
34
3e
3.
31
40
41
42
43
44
4e
.e
.,
80
el
82
e3
84
81'
oe
01
t
00 00
01 01
02 02
03 03
04 04
OS o.
O. 0.
01 01
O. 10
01 11
2F e1
30 111
00 18
10 20
01 18
1A3I
30 .0
11 21
11 22
13 23
14 2.
10 til
•• 2.
11 27
1. 30
It 'I
2E "
18 33
20 88
3C 14
20 40
OF 11
2A e2
21 41
t2 U
23 .3
24 44
211 4e
2. 48
21 41
2. 80
2S el
08
2&
2C
3E
\ IF
J IC
"
83
8.
,.
31
..
30
31
32
33
34
3S
3.
31
3.
3S
21
30
3A
20
Itt
t.
28
41
.2
.3
•4
40
4.
41
••
4S
31
2t
2S
2e
• 8E
3F
20
4A
48
4C
40
4t
4'
eo
el
e2
23
2.
2A
22
\ SC
J SO
oeo
0.,
0.2
083
084
08e
088
0.,
010
011
041
0111
012
040
01.
04.
003
101
102
102
104
108
108
107
110
III
013
08S
081
o.e
138
011
oee
III
113
" ..
118
11.
1t1
120
121
122
043
0 ••
082
0.2
13.
13S
FO
Fl
F2
'3
F4
F.
F8
F1
F.
FS
10
71
7A
40
.E
00
4E
Cl
C2
C3
C4
CO
C'
C1
C'
CS
8E
48
'0
ae
8F
8F
.0
01
02
03
04
De
O.
01
08
Ot
18
ee
.SC
7F
\ EO
I SA
3.0
3.,
3.2
3.3
384
38S
3 ••
381
310
311
l1e
118
112
100
18.
120
118
301
302
303
30•
3011
30.
301
310
311
"e
113
138
le4
131
187
140
321
322
323
32.
318
328
321
330
331
173
133
13.
117
3.0
132
0
1
2
3
0
•
a
3
..
..
.
••
••
e
a
7
It
a
7
•
S
t· • .
3-.
....
0""
81."
1-.
'12'01,1t1
12-1
12'2
12'3
12'4
II-e
12-a
12-7
11"
12-S
12'2-1
12'3"
12'4"
12'8-'
12-8-.
Cl21 Cl2-0I
,11-0IClIl
" -1
11'2
11'3
11-4
" -e
11'1
11-.
l1-a
11-2-'
11-3-'
11-.·.
11-0-.
ll-e-8
111111'-0)
12'0
1.'1
11'1
12-3
11'4
12'&
12-a
12-1
12"
II'S
II-e·,
11'3"
11-8-.
0-4-.
"-0
7-t
II
11 .,
11-a
11'3
11'4
11'8
l1-e
11-7
11'.
l1'S
3'.
11-3"
11'.-.
0-.·.
12-7-.
12-.-.
"
-.
e
a
1
11-1,' e·.
e·.
.1 . . .
•••
0
1
I
3
•••
11
•••
2-.
.,enk
0-.· •
11
••••••
1.-1
II-a
12-3
11'4
lZ"
12'.
12-7
Ilr-.
lI-S
"-S"
11'3"
11'8"
0'4-.
11-7-.
0-7"
"
" -1
11'2
11-3
"'4
11-8
11-.
11-7
11-.
l1-S
3-a
11,3-.
11-.·.
7'.
0-2-t
I'-2-t
I-'
I
0
0
r-"
\"
""'-
/)
',.
........:
Ntln
(
I
•
L...
Th.n
SI •• h
T
U
V
W
)(
Y
Z
•,
C
CR
•
ko~ ••
I
I-'
W
C_.
A~
C,.edl~
I
<:)
<:)
81an
C.nt. SIan
,. ",.OM
3.
4.
II.
tHlcll
ASCII
PlICDI C
CODE
18 8
16 8
18
16
I.
30
31
32
33
34
3e
3"
31
38
38
3A
38
3C
R 30
3E
.. 31'
80
81
82
83
84
8e
88
81
10
11
12
13
14
111
78
71
coot:
IE
31
32
33
34
3e
3"
31
38
38
DC
38
10
3F"
.3A
[ OA
38
81
82
83
"4
"e
"8
81
10
71
14
73
3e
11
12
12
ceDE
3e
2..
e3
e4
88
118
81
118
118
8A
40
2C
2"
CI 21
8
014
oe1
123
124
12e
12"
121
130
131
132
100
0114
0110
041
_ II.. 131
[ e8 133
.,
8
4C 114
141
[2 342
~3 343
~4 344
E8 3415
E8 34"
E7 341
E8 380
U 381
7C 114
88 1113
40 1111
41' 111
_ eo 11111
~ "A 112
HeCD
CARD
oeco
8-8
0-1
0-2
0-3
0-4
0-8
12-8-8
0-1
0-1
0-3
0-4
0-11
0-8
0-1
0-1
0-.
4-"
0-3-"
12-11-"
0-1-1
0-2-e
2-1
CODE
o-e
0-7
0-1
0-.
0-2-.
0-3-8
0-4-"
0-8-'
0-8-'
0-1-e
CARD
CODE
ASCII/PlICDI C
CARD CCO~
12-4-1
0-1
0-1
0-3
0-4
0-8
0-'
0-7
0-'
0-.
4-'
0-3-8
11-8-1
12-7-8
0-8-"
12-2-1
EBCDIC or A8CII ~o HeCD or oeco thl. I • • one-w.v corr ••pond.nc•.
~he •• ASCII cod•••• v.rl.bl. 'or n.tlon.1 u ••a •.
Slnc. ~h.r. I. no corr •• pondlna ch.r.ct.r • d.'.ul~ ch.ract.r I • • ub.tltuted her.:
38 10ct.,)ID) 'or HeCO .nd 37 loc~.')I') for 08CD.
In HltCD the cod. e1 10ct.11 ~v r.pr ••• nt 1/2 or I
TM occupl •• ~h• •em. po. It Ion •• DC3.
TM I • •n EBCDIC control chereet.r
whll.DC3 I • •n ASCII control ch.r.ct.r .
Th. Int.rnel .nd punched c.rd cod• • • how" for HeCD .nd 08CO . r . for ceplt.1 .,phebe~lc•.
Th.r • •r. two HeCO c.,.d co bits 2-1
BLANK
Insert Blank on Suppression 7-46
Move with Zero Suppression and Blank
Replacement 7-55
BLANK-WHEN-ZERO
Blank-when-zero flag
BOLR
BOLR 7-34
BOLR control field
7-43
BOOLEAN
Boolean Expressions 7-13
Boolean Operation Instruc~ions 7-13
Boolean Operations 7-2
Boolean operations 7-34
Evaluation of Boolean Expressions
7-13
BOUND
Bound 3-8
Bound address 3-11
Bound Check Equations 5-85
bound field 8-277
bound value 5-58
Bounds Checking 5-83
Locating New Bound for Shrink 8-300
modifying the bound field 8-418
BOUND FAULTS
Bound Faults 8-306
BTD
BTD 8-81
BUFFER
buffer instructions 1-1
Translation look-aside buffer
5-71
BYPASS
Safe Store Bypass Flag (SSBF)
4-19
BYTE
byte checks 5-86
Byte Operations 5-85
byte positions 8-536, 8-537
BYTES
9-Bit Bytes 2-2
Store 9-bit Bytes of A-Register
8-536
Store 9-bit Bytes of Q-Register
8-537
CACHE
Clear cache 8-91
CONTROL 5-82
CALENDAR
calendar Clock Register
4-20
8-163
CAMP
BOOL
BOOL 7-13
CAMP 8-84
i-7
DZ5l-00
CANA
CANA 8-87
CANAQ
CANAQ 8-88
CANQ
CANQ 8-89
CANXN
CANXn
8-90
CARRY
Add with Carry to A-Register 8-71
Add with Carry to Q-Register 8-73
Carry 4-8
Carry indicator 2-4
Subtract with Carry from A-Register
8-568
Subtract with Carry from Q-Register
8-570
Transfer On Carry 8-609
Transfer On No Carry 8-596
CATEGORIES
Fault Categories
6-4
CC
Calendar ClocK Register
4-20
CENTRAL
Load Central Processor Register
8-270
5-59
CHANGE
Change Table 7-44
CHANNEL
Connect I/O Channel
CHARACTER-MOVE
Character Move to/from Register
Instructions 7-28
Descriptor for Character Move
Instructions 7-29
CHARACTER! STI CS
Read Processor Model Characteristics
8-470
CCAC
CCAC 8-91
CHAIN
indirect chain
CHARACTER (cont )
Character Indirect (0) variation
5-17
Character Move To/From Register.
Instructions 8-11
Character Operations 5-48
Character Positions 2-2
character positions 8-543
Character-Strings 2-2
Compare Alphanumeric Character
Strings 8-142
Decimal Data Character Codes 2-9
Sequence character 5-14
Sequence Character (SC) variation
5-18
Sequence character reverse 5-14
Sequence Character Reverse (T) 5-19
Test Character and Translate 8-583
CHARACTERS
4-Bit Characters 2-2
6-Bit Characters 2-2
6-bit characters 5-19
Compare Characters and Translate
8-145
Ignore Source Characters 7-45
Move SOurce Characters 7-54
Scan Characters Double 8-498
Scan Characters Double in Reverse
8-502
Store 6-bit Characters of A-Register
8-540
Store 6-bit Characters of Q-Register
8-542
8-92
CHARACTER
Alphanumeric Character Number (CN)
Codes 7-27
character codes for ASCII and EBCDIC
overpunched sign 8-397
Character indirect 5-14
CHT
CHT 7-44
o
Character Indirect (0) variation
5-17
o 5-14
C1 variation 5-17
i-8
DZ51-00
aoc
CMPNX
CMPNX
CIOC 8-92
CIRCUITRY
processor logic circuitry
8-421
CLEAP
Clear Associative Memory Pages 8-84
Clear cache 8-91
Data Stack Clear Flag (DSCF) 4-19
Load A-Register and Clear 8-275
Set Zero and Negative Indicators
from Storage and Clear 8-577
CLIMB
CLIMB 3-7, 4-15, 4-23, 4-24, 4-26,
8-96
Climb five versions fields 8-130
Domain Transfer (CLIMB) 7-58
ICLIMB (Inward CLIMB) - 00 8-101
Inward CLIMB Interrupts 6-24
OCLIMB (Outward CLIMB) - 01 8-121
Outward CLIMB 8-121
(
.•
CMPO
CMPQ
CMPXN
CMPXn
8-151
8-153
8-15'
CMRR
CMRR 8-156
CN
Alphanumeric Character Number (CN)
Codes 7-27
CNAA
CNAA 8-158
CNAAQ
CNAAQ 8-159
C),AQ
CNAQ 8-160
CLOCK
Calendar Clock Register 4-20
free running clock 4-12
CNAXN
CNAXn
CMG
CMG 8-134
CODE
FLOATABLE CODE 5-27
CMK
CMK 8-135
CODES
ADDRESS MODIFICATION OCTAL CODES
5-25
Alphanumeric Character Number (CN)
Codes 7-27
Alphanumeric Data Type (TA) Codes
7-27
character codes for ASClI and EBCDIC
overpunched sign 8-397
Decimal Data Character Codes 2-9
Micro Operation Code Assignment Map
7-57
mnemonic code 8-1
octal value of the operation code
8-2
Operation Code Map (Bit 27 = 0) A-2
Operation Code Map (Bit 27 = 1) A-4
Processor Faults By Fault Code 6-3
Register Codes 5·33
System Controller Illegal Action
Codes 4-36
CMPA
CMPA 8-137
CMPAQ
CMPAQ 8-138
CMPB
CMPB 8-139
CMPC
CMPC 8-142
CMPer
CMPCT
8-145
CMPN
CMPN 8-148
i-9
8-161
DZ51-00
COMBINE
Combine Bit Strings Left 8-162
Combine Bit Strings Right 8-165
COMMAND
Command Faults
8-305
COMPARATIVE
Comparative AND with A-Register
8-87
Comparative AND with AQ-Register
8-88
Comparative AND with Index Register
n 8-90
Comparative AND with Q-Register
8-89
Comparative NOT AND with A-Register
8-158
Comparative NOT AND with AQ-Register
8-159
Comparative NOT AND with Index
Register n 8-161
Comparative NOT AND with Q-Register
8-160
COMPARE
Compare Alphanumeric Character
Strings 8-142
Compare Bit Strings 8-139
Compare Characters and Translate
8-145
Compare Magnitude 8-134
Compare Masked 8-135
Compare Numeric 8-148
Compare Numeric Extended 8-151
Compare Register to Register 8-156
Compare with A-Register 8-137
Compare with AQ 8-138
Compare with Index Register n 8-154
Compare with Limits 8-167
Compare with Q-Register 8-153
Comparison Operations 7-2
Data Comparison 7-7
Double-Precision Floating Compare
8-170
Double-Precision Floating Compare
Magnitude 8-169
Floating Compare 8-229
Floating Compare Magnitude 8-228
Set Pointer Compare Flags Off 8-518
COMPLEMENT
Load Complement into A-Register
8-267
Load Complement intoAQ-Register
8-268
Load Complement into Index Register
n 8-273
Load Complement into Q-Register
8-272
Load Complement Register from
Register 8-279
CONFIGURATION
Configuration Register Port
Assignment 4-30
SCU Configuration Register 4-47
CONNECT
Connect I/O Channel 8-92
Load Connect Table Register 8-269
Read Connect Word Pair 8-437
CONSTANTS
conversion constants 8-78
CONTINUE
Decrement Address, Increment Tally,
and Continue 5-23
Decrement Address, Increment Tally,
and Continue (T) 5-21
Increment Address, Decrement Tally,
and Continue 5-22
CONTROL
Stack Control Register (SCR)
4-22
CONTROLLER
Read System Controller Register
8-468
Set System Controller Register
8-527
System Controller Illegal Action
Codes 4-36, 4-38
SYSTEM CONTROLLER INTERRUPTS 6-23
CONVERSION
Binary to Decimal Convert 8-81
Binary-To-BCD Conversion 7-67
Binary-to-BCD Convert 8-77
conversion constants 8-78
Conversion instructions 7-6
conversions between binary and
decimal numbers 7-36
i-10
DZ5l-00
<-"
CONVERSION (cont)
Data Conversion InstTuctions 7-36
Decimal to Binary Convert 8-188
Radix conversion 7-7
COpy
Copy 8-284
copy option 8-319
COUNT
Transfer On Count
8-611
COUNTER
I NSTRUCTI ON COUNTER (I C) 4-13
Store Instruction Counter Plus 1
8-538
Store Instruction Counter Plus 2
8-539
CPU
CPU Mode Register 4-26, 4-28
CPU Number Register 4-34
CPU SCU IMX 3-1
CSL
CSL
(/
8-162
CSR
CSR 8-165
CURRENCY
Move with Floating Currency Symbol
Insertion 7-48
OiL
CWL 8-167
DATA
Alphanumeric Data Type (TA) Codes
7-27
Data Comparison 7-7
Data Conversion Instructions '7-36
Data Manipulation 7-7
Data Movement 7-7
Data Movement Instructions 7-2
Data Shifting Instructions 7-3
DATA STACK ADDRESS REGISTER (DSAR)
4-25
Data Stack Clear Flag (DSCF) 4-19
DATA STACK DESCRIPTOR REGISTER
(DSDR) 4-25
Decimal Data Character Codes 2-9
double-precision data 2-1
DATA (cont)
Load Data Stack Address Register
8-309
Load Data Stack Descriptor Register
8-310
processing of scattered data 5-22
processing of tabular data 5-13
single-precision data 2-1
Store Data Stack Address Register
8-546
Store Data Stack Descriptor Register
. 8-547
DECIMAL
Add Using Three Decimal Operands
8-31
Add Using Three Decimal Operands
Extended 8-36
Add Using Two Decimal Operands 8-25
Add Using Two Decimal Operands
Extended 8-28
ADSC4 - Packed decimal alphanumeric
descriptor 5-36
Binary to Decimal Convert 8-81
conversions between binary and
decimal numbers 7-36
Decimal Arithmetic 7-7
Decimal Data Character Codes 2-9
Decimal Number Ranges 2-11
Decimal Numbers 2-8
Decimal to Binary Convert 8-188
Divide Using Three Decimal Operands
8-200
Divide Using Three Decimal Operands
Extended 8-205
Divide Using Two Decimal Operands
8-196
Divide Using Two Decimal Operands
Extended 8-198
Floating-Point Decimal Numbers 2-10
Multiply Using Three Decimal
Operands 8-359
Multiply Using Three Decimal
Operands Extended 8-363
Multiply Using Two Decimal Operands
8-354
Multiply Using Two Decimal Operands
Extended 8-357
NDSC4 - Packed decimal numeric
descriptor 5-37
Packed Decimal 2-2
Packed Decimal (4-bit) 2-9
i-11
DZ5l-00
DECIMAL (cont)
Subtract Using Three Decimal
Operands 8-481
Subtract Using Three Decimal
Operands Extended 8-484
Subtract Using Two Decimal Operands
8-476
Subtract Using Two Decimal Operands
Extended 8-479
DECREMENT
Decrement address 5-14
Decrement Address, Increment Tally
(T) 5-21
Decrement Address, Increment Tally,
and Continue 5-23
Decrement Address, Increment Tally,
and Continue (T) 5-21
Increment address decrement tally
5-14
Increment Address, Decrement Tally
(T) 5-20
Increment address, decrement tally,
and continue 5-15
Increment Address, Decrement Tally,
and Continue 5-22
DELAY
Delay Until Interrupt Signal
8-184
DELTA
Add Delta (AD) variation 5-24
Subtract delta 5-15
Subtract Delta (SO) variation 5-25
DENSE
Dense Page Table 5-72
DERAIL
Derail
8-187
DESCRIPTOR
Address Register n to Alphanumeric
Descriptor 8-62
Address Register n to Numeric
Descriptor 8-65
ADSC4 - Packed decimal alphanumeric
descriptor 5-36
ADSC6 - BCI alphanumeric descriptor
5-36
ADSC9 - ASCII alphanumeric
descriptor 5-36
DESCRIPTOR (cont)
Alphanume~ic Descriptor To Address
Register n 8-21
ALPHANUMERI C OPERAND DESCRI PTOR
FORMAT 7-26
Alphanumeric Operand Descriptors
5-36
BOSC - Bit descriptor - 5-36
Bit String Operand Descriptor 5-35
BI T STRI NG OPERAND DESCRI PTOR FORMAT
7-35
DATA STACK DESCRIPTOR REGISTER
(DSDR) 4-25
Descriptor for Character Move
Instructions 7-29
DESCRI PTOR REGI STER I NSTRUCTI ONS
7-58
Descriptor Segment Descriptor 8-101
descriptor storage 3-6
Descriptor Types 3-8
Descriptors 3-6
Dynamic Linking Descriptor 3-15
Entry Descriptor 3-14, 8-101
Extended Descriptor 3-12
Extended Descriptor With Working
Space Number 3-13
ID - Indirect Operand Descriptor
5-32, 7-24
Load Data Stack Descriptor Register
8-310
Load Descriptor Register n 8-280
NDSC4 - Packed decimal numeric
descriptor 5-37
NDSC9 - ASCII numeric descriptor
5-37
Numeric Descriptor to Address
Register n 8-405
NUMERIC OPERAND DESCRIPTOR FORMAT
7-31
Numeric Operand Descriptors 5-37
Operand Descriptor Address
Preparation 5-41
OPERAND DESCRI PTOR I NDI RECT POI NTER
FORMAT 7-25
Operand Descriptor Modification (ES)
5-55
Operand Descriptors 5-35
Operand Descriptors and Indirect
Pointers 7-25
Save Descriptor Register n 8-512
segment descriptor 3-1, 5-58
SEGMENT DESCRI PTOR REGI STERS (DRn)
4-16
i-12
DZ51-00
DESCRIPTOR (cont)
SEGMENTS 3-6
Shrunken Descriptor 3-16
Standard Descriptor 3-8, 5-60,
8-101
standard descriptor 8-330
Standard Descriptor (ES) 5-64
Standard Descriptor With Working
Space Number 3-10
Store Data Stack Descriptor Register
8-547
Store Descriptor Register n 8-544
Super Descriptor 3-11
Super Descriptor With Working Space
Number 3-12
Vector for Standard Descriptor,
Super Descriptor 8-281
Virtual Address Generation, Super
Descriptor 5-61
DESCRI PTOR REGI STERS
Store Test Descriptor Registers
8-563
DESCRI PTORS
Shrink for Extended Descriptors
8-294
Shrink for Standard and Super
Descriptors 8-284
DESIGNATOR
register designator 5-2
tag designator (td) 5-2
tally designator 5-2
Tally Designators 5-16
DFLP
D~·p
• l."l
8-176
DFMP
DFMP 8-177
DFRD
DFRD 8-178
DFSB
DFSB 8-179
DFSBI
DFSBI
8-180
DFST
DFST 8-181
DFSTR
DFSTR 8-182
DI
DI 5-14
DI Variation
DIC
DIC Variation
5-21
5-23
DIRECT
direct operand address modification
5-4
NS Direct Lower (DL) 5-4
NS Direct Upper (DU) 5-4
DFDV
DFDV 8-173
DIRECTORY
Load Page Table Directory Base
Register 8-340
Locating the page table directory
word 5-72
Page Directory Base Register (PDBR)
1-7
PAGE DIRECTORY BASE REGISTER (PDBR)
4-26
page table directory 3-2
Page Table Directory Word 5-72
Page Table Directory Word (PTDW)
Format 5-68
Store Page Table Directory Base
Register 8-519
Store PTWAM Directory Word 8-555
DFLD
DFLD 8-175
DIS
DIS 4-13, 8-184
DFAD
DFAD 8-168
DFCMG
DFCMG
8-169
DFCMP
DFCMP 8-170
DFDI
DFDI
8-171
i-13
DZ51-00
DI SPLACEMENT
Add 4-Bit Displacement To Address
Register 8-15
Add 6-Bit Displacement To Address
Register 8-17
Add 9-Bit Displacement to Address
Register 8-19
Add Bit Displacement To Address
Register 8-23
Add Word Displacement To Address
Register 8-75
Displacement register 8-11
Subtract 4-Bit Displacement from
Address Register 8-471
Subtract 6-Bit Displacement from
Address Register 8-472
Subtract 9-Bit Displacement from
Address Register 8-473
Subtract Bit Displacement from
Address Register 8-489
Subtract Word Displacement from
Address Register 8-572
DIV
DIV 8-185
DIVIDE
Divide Fraction 8-208
Divide Integer 8-185
Divide Register by Register 8-210
Divide Using Three Decimal Operands
8-200
Divide Using Three Decimal Operands
Extended 8-205
Divide using Two Decimal Operands
8-196
Divide Using Two Decimal Operands
Extended 8-198
Double-Precision Floating Divide
8-173
Double-Precision Floating Divide
Inverted 8-171
Floating Divide 8-232
Floating Divide Inverted 8-230
DIVISION
division
7-3
DL
NS Direct Lower (DL;
DOMAIN
domain registers
3-4
5-4
DOMlJ N ( cont )
Domain Transfer 8-96
Domain Transfer (ClJMB) 7-58
Domains 3-3
interdomain references 8-97
OOUBLE
Execute Double 8-639
Load Double Register to Register
Pair 8-308
Load Double to GKn 8-249
Repeat Double 8-446
Scan Characters Double 8-498
Scan Characters Double in Reverse
8-502
Store Double from GXn 8-262
DOUBLE PREClSION OPERANDS
Quadruple-Precision Floating
Multiply with Double-Precision
Operands 8-435
DOUBLE-PRECISION
double-precision data 2-1
Double-Precision Floating Add 8-168
Double-Precision Floating Compare
8-170
Double-Precision Floating Compare
Magnitude 8-169
Double-Precision Floating Divide
8-173
Double-Precision Floating Divide
Inverted 8-171
Double-Precision Floating Load
8-175
Double-Precision Floating Load
Positive 8-176
Double-Precision Floating Multiply
8-177
Double-Precision Floating Round
8-178
Double-Precision Floating Store
8-181
Double-Precision Floating Store
Rounded 8-182
Double-Precision Floating Subtract
8-179
Double-Precision Floating Subtract
Inverted 8-180
Double-Precision Unnorma1ized
Floating Add 8-193
Double-Precision Unnormalized
Floating Multiply 8-194
i-14
DZ5l-00
DV2DX
DV2DX
DOUBLE-PRECISION (cant)
Double-Precision Unnormalized
Floating Subtract 8-195
DOUBLE-WORD
Word and Double-Word Operations
5-84
DR
8-198
DV3D
DV3D 8-200
DV3DX
DV3DX
8-205
DVF
DVF 8-208
DR 8-11
DRL
DRL 8-187
DVRR
DVRR
DRn
DRn 4-17
Loading DRn 8-123
SEGMENT DESCRI PTOR REGI STERS (DRn)
4-16
8-210
DYNAMIC
Dynamic Linking Descriptor
E
EXPONENT REG! STER (E)
DSAR
DATA STACK ADDRESS REGISTER (DSAR)
4-25
DSCF
Data Stack Clear Flag (DSCF)
DSDR
DATA STACK DESCRIPTOR REGISTER
(DSDR) 4-25
4-19
8-188
EAA 8-212
EAQ
EAQ 8-213
EXPONENT ACCUMULATOR QUOTIENT
REGI STER (EAQ) 4-5
EAXN
5-4
DU/DL
DU/DL Modification (ES)
DUFA
DUFA 8-193
DUFM
DUFM
8-194
DUFS
DUFS
8-195
DV2D
DV2D
8-196
8-214
EBCDIC
character codes for ASCII and EBCDI C
overpunched sign 8-397
DU
NS Direct Upper (DU)
4-5
EM
EAXn
DTB
DTB
3-15
5-55
EDAC
EDAC (Error Detection and
Correction) bits 2-1
EDIT
ALPHANUMERI C EDI T (MVE) 7-41
Edit Flags 7-42
Edit Insertion Table 7-39
Edited Move Micro Operations 7-6
MICRO OPERATIONS FOR EDIT
INSTRUCTIONS MVE AND MVNE 7-38
Move Alphanumeric Edited 8-380
Move Numeric Edited 8-389
Move Numeric Edited Extended 8-393
NUMERI C EDI T (MVNE And MVNEX) 7-40
(/
i-15
DZ51-00
EFFECTIVE
Effective Address Generation 5-52
Effective Address to A-Register
8-212
Effective Address to Index Register
n
ERSA
ERSA 8-223
8-214
Effective Address to Q-Register
8-213
Effective Address to Register
Instructions 7-3
Effective Pointer and Address to
Test 8-215
Effective Pointer To Pointer
Register n 8-216
ERSQ
ERSQ 8-224
ERSXN
ERSXn
ERXN
ERXn
8-225
8-226
ES
EIGHT
EIGHT 8-265, 8-341, 8-343, 8-525
END
End Floating Suppression 7-44
End suppression flag 7-42
ENF
ENF
ERRR
ERRR 8-222
7-44
ENTRY
Entry Descriptor 3-14, 8-101
Entry Location 3-14
Insert Table Entry One Multiple
7-46
Master Mode Entry 8-352
EPAT
EPAT 8-215
EPPRN
EPPRn 8-216
EQUATIONS
Bound Check Equations
EXCLUSIVE
Exclusive OR
8-222
EXCLUSIVE OR
EXCLUSIVE OR
EXCLUSIVE OR
8-226
EXCLUSIVE OR
EXCLUSIVE OR
A-Register
EXCLUSIVE OR
Register n
EXCLUSIVE OR
Q-Register
5-85
ERA
ERA 8-219
ERAQ
ERAQ 8-220
ERQ
ERQ 8-221
ERROR
Memory Error Status Register
parity error 4-10
DU/DL Modification (ES) 5-55
Effective Address Generation 5-51
ES A/Q/GXn Modification 5-52
ES Address Modification with AR
5-50
ES Address Modification with no AR
5-49
ES Instruction Address Field 5-49
ES Mode Address Generation 5-49
ES Mode Instructions 7-62
IC Modification ES 5-54
NS ES Segmentation Modes 5-1
Operand Descriptor Modification (ES)
5-55
Standard Descriptor (BS) 5-64
Tag Field Modification ES 5-52
Virtual Address Generation (ES)
5-64
4-51
Register to Register
to A-Register 8-219
to AQ-Register. 8-220
to Index Register n
to Q-Register 8-221
to Storage with
8-223
to Storage with Index
8-225
to Storage with
8-224
EXECUTE
Execute (XEC) 8-637
Execute Double 8-639
i-16
DZ51-00
EXECUTE (con t )
Execute Instructions
EXPANSION
binary expansion
F
7-67
2-8
EXPONENT
Add to Exponent Register 8-41
exponent 2-5
EXPONENT ACCUMULATOR QUOTI ENT
REG! STER (EAQ) 4-5
Exponent overflow 4-9
EXPONENT REGI STER (E) 4-5
Exponent underflow 4-9
hexadecimal exponent mode 4-12
Load Exponent Register 8-312
Store Exponent Register 8-548
Transfer On Exponent Overflow 8-587
Transfer On Exponent Underflow
8-589
EXPRESSIONS
Boolean Expressions 7-13
Evaluation of Boolean Expressions
7-13
EXTENDED
Add Using Three Decimal Operands
Extended 8-36
Add Using Two Decimal Operands
Extended 8-28
Compare Numeric Extended 8-151
Divide Using Three Decimal Operands
Extended 8-205
Divide Using Two Decimal Operands
Extended 8-198
Extended Descriptor 3-12
Extended Descriptor With Working
Space Number 3-13
Extended Fault Register 4-40
Load Extended Address n 8-313
Move Numeric Edited Extended 8-393
Move Numeric Extended 8-395
Multiply Using Three Decimal
Operands Extended 8-363
Multiply Using Two Decimal Operands
Extended 8-357
Shrink for Extended Descriptors
8-294
Subtract Using Three Decimal
Operands Extended 8-484
Subtract Using Two Decimal Operands
Extended 8-479
F Variation
5-17
FACTOR
scaling factor
Scaling factor
5-39, 8-34
7-32
FAD
FAD 8-227
FAULT
Extended Fault Register 4-40
Fault categories 6-4
Fault Priority 6-2
Fault Procedures 6-1
Fault Recognition 6-2
FAULT REGISTER FORMAT 4-36
Fault trap 5-14
Fault variation 5-17
Missing Page fault 5-71
SCU FAULT REGISTER 4-44
FAULTS
Command Faults 8-305
Faults And Interrupts 1-2
Hardware-Generated Faults 6-16
IC Values Stored on Faults and
Interrupts 6-25
Illegal Procedure (IPR) Faults
8-305
Instruction-Generated Faults 6-4
Miscellaneous Faults 6-18
Mode Faults 6-17
Processor Faults By Fault Code 6-3
Program-Generated Faults 6-7
Virtual Memory-Generated Faults
6-10
FCMG
FCMG 8-228
FCMP
FCMP
FDI
FDI
8-229
8-230
FDV
FDV 8-232
FIELD
BOLR control field
bound field 8-277
8-163
(
i-17
DZS1-OO
FIELD (cant)
ES Instruction Address Field 5-49
flags field 3-8, 3-10, 3-11, 3-12
modifying the bound field 8-418
Mu1tiword Modification Field 5-31,
7-24
Tag Field 5-2
Tag Field Modification ES 5-52
FI XED-POI NT
Fixed-Point Arithmetic Instructions
7-3
FIXED-POINT INSTRUcrlONS 7-16
Fixed-point Instructions 7-65
Fixed-Point Numbers 2-3
Ranges Of Fixed-Point Numbers 2-4
FLAG
Blank-when-zero flag 7-43
Data Stack Clear Flag (DSCF) 4-19
Edit Flags 7-42
End suppression flag 7-42
flags field 3-8, 3-10, 3-11, 3-12
Safe Store Bypass Flag (SSBF) 4-19
Sign flag 7-43
Zero flag 7-43
FLAGS
Set Pointer Compare Flags Off
8-518
FLD
FLD 8-234
FLOATABLE
FLOATABLE CODE 5-27
FLOATING
Double-Precision Floating
Double-Precision Floating
8-170
Double-Precision Floating
Magnitude 8-169
Double-Precision Floating
8-173
Double-Precision Floating
Inverted 8-171
Double-Precision Floating
8-175
Double-Precision Floating
Positive 8-176
Double-Precision Floating
8-177
Add 8-168
Compare
Compare
Divide
Divide
Load
Load
~!ultiply
FLOATING (cont)
Double-Precision Floating Round
8-178
Double-Precision Floating Store
8-181
Double-Precision Floating Store
Rounded 8-182
Double-Precision Floating Subtract
8-179
Double-Precision Floating Subtract
Inverted 8-180
Double-Precis ion Unnormal ized
Floating Add 8-193
Double-Precision Unnormalized
Floating Multiply 8-194
Double-Precision Unnormalized
Floating Subtract 8-195
End Floating Suppression 7-44
Floating Add 8-227
Floating Compare 8-229
Floating Compare Magnitude 8-228
Floating Divide 8-232
Floating Divide Inverted 8-230
Floating Load 8-234
Floating Load Positive 8-235
Floating Multiply 8-236
Floating Negate 8-237
Floating Normalize 8-238
Floating Round 8-240
Floating Set Zero and Negative
Indicators from Storage 8-247
Floating Store 8-244
Floating Store Rounded 8-245
Floating Subtract 8-242
Floating Subtract Inverted 8-243
Floating Truncate Fraction 8-248
Move with Floating Currency Symbol
Insertion 7-48
Move with Floating Sign Insertion
7-50
Quadruple-Floating Add 8-422
Quadruple-Floating Load 8-424
Quadruple-Precision Floating
Multiply 8-425
Quadruple-Precision Floating
Multiply with Double-Precision
Operands 8-435
Quadruple-Precision Floating Store
8-429
Quadruple-Precision Floating Store
Rounded 8-430
Quadruple-Precision Floating
Subtract 8-427
i-18
DZ51-00
FLOATING (cant)
Unnormalized Floating
Unnormalized Floating
8-634
Unnormalized Floating
8-635
Unnormalized Floating
Fraction 8-636
FORMAT (cant)
Page Table Base Word (PBW) Format
5-69
Page Table Directory Word (PTDW)
Format 5-68
Page Table Word (PTW) Format 5-70
Add 8-632
Multiply
Subtract
Truncate
FORMATS
Bit Formats
FLOATING-POINT
Floating-Point Arithmetic
Instructions 7-4
Floating-Point Decimal Numbers 2-10
FLOATING-POINT INSTRUCTIONS 7-20
Floating-point Numbers 2-5
Hexadecimal Floating-Point Numbers
2-5
Normalized Floating-Point Numbers
2-7
Quadruple-Precision Floating-Point
Instructions 7-4
Ranges of Binary Floating-Point
Numbers 2-7
FLOWCHART
Address Modification Flowchart
FLP
FLP
5-26
2-1
FOUR-STAGE
Four-stage pipeline 1-2
FRACTION
Divide Fraction 8-208
Floating Truncate Fraction 8-248
Multiply Fraction 8-365
Unnormalized Floating Truncate
Fraction 8-636
FRACTIONAL
Binary Representation of Fractional
Values 2-8
fractional mantissa 2-5
FRAMED
framed stack space 8-104
8-235
FRD
FRD 8-240
8-236
FREE
free running clock
Ft.fl'
FMP
FNEG
FNEG
8-237
FNO
FNO 8-238
FORMAT
ALPHANUMERIC OPERAND DESCRIPTOR
FORMAT 7-26
BIT STRING OPERAND DESCRIPTOR FORMAT
7-35
FAULT REGISTER FORMAT 4-36
FORMAT OF INSTRUCTION DESCRIPTION
8-1
Indirect Word Format 5-16
INSTRUCTION WORD FORMATS 8-7
NUMERIC OPERAND DESCRIPTOR FORMAT
7-31
OPERAND DESCRI PTOR I NDI RECT POI NTER
FORMAT 7-25
4-12
FSB
FSB 8-242
FSBI
FSBI
8-243
FST
FST 8-244
FSTR
FSTR 8-245
FSZN
FSZN 8-247
FTR
FTR 8-248, 8-636
i-19
DZ5l-00
GATE
Gate Synchronize 8-575
GSTD
GSTD 8-262
GCLIMB
GCLIMB 8-125
GCLIMB (Lateral Transfer LTRAS) - 10
8-125
GTB
GTB 8-263
GENERAL
General Description· 3-1
GENERAL INDEX REGI STERS
General Index Registers (GXn)
4-7
GENERATED
Hardware-Generated Faults 6-16
Instruction-Generated Faults 6-4
Program-Generated Faults 6-7
Virtual Memory-Generated Faults
6-10
GENERATION
Effective Address Generation 5-51
ES Mode Address Generation 5-49
NS Mode Address Generation 5-1
Virtual Address Generation (ES)
5-64
Virtual Address Generation, Super
Descriptor 5-61
GLDD
GLDD 8-249
HARDWARE
hardware rounding option 7-7
Hardware-Generated Faults 6-16
HEXADECl MAL
hexadecimal exponent mode 4-12
Hexadecimal Floating-Point Numbers
2-5
HIGH
(HWMR) 4-24
High Water Mark Register
8-109
HISTORY
History Register 4-49
History Registers 4-41
GLLS
GLLS 8-250
HOUSEKEEPING
housekeeping bit 7-59
housekeeping pages 3-7
GLRL
GLRL 8-252
GLRS
GLRS
GXN
General Index Registers (GXn) 4-7
Gr.n Left Shift 8-256
GXn Long Left Shift 8-250
GXn Long Right Logic 8-252
GXn Long Right Shift 8-254
GXn Register In R Modification 5-50
GXn Right Logic 8-258
GXn Right Shift 8-260
Load Double to GXn 8-249
Multiply GXn 8-370
Store Double from GXn 8-262
8-254
I
5-14
I Variation 5-19
Indirect (I) variation 5-19
I
GLS
GLS 8-256
GRAY-To-BINARY
Gray-to-B i nary
GRL
GRL 8-258
GRS
GRS 8-260
7-67, 8-263
I/O
Connect I/O Channel
8-92
IC
IC Modification ES 5-54
IC Values Stored on Faults and
Interrupts 6-25
INSTRUCTION COUNTER (Ie> 4-13
i-20
DZ5l-00
IC
4-17
Set System Controller Register
8-527
Special Address Register
Instructions 7-12
stack control register (SCR) 4-22,
8-330
Stack Control Register (SCR) 4-22
Store Address Register n 8-474
Store Address Registers 8-475
Store Argument Stack Register 8-535
Store Base Address Register 8-488
Store Data Stack Address Register
8-546
Store Data Stack Descriptor Register
8-547
Store Descriptor Register n 8-544
Store Exponent Register 8-548
Store Index Register n in Lower
8-574
Store Index Register n in Upper
8-566
Store Indicator Register 8-549
Store Option Register 8-551
Store Page Table Directory Base
Register 8-519
Store Parameter Segment Register
8-556
Store PTWAM Register 8-557
Store Registers 8-524
Store safe Store Register 8-559
Store Timer Register 8-561
Store Working Space Registers .8-564
Subtract 4-Bit Displacement from
Address Register 8-471
Subtract 6-Bit Displacement from
Address Register 8-472
Subtract 9-Bit Displacement from
Address Register 8-473
Subtract Bit Displacement from
Address Register 8-489
Subtract from Index Register n
8-497
Subtract Logical from Index Register
n 8-494
i-37
DZ51-00
REGI STER (cont)
Subtract Logical Register from
Register 8-493
Subtract Register from Register
8-496
Subtract Stored from Index Register
n 8-530
Subtract Word Displacement from
Address Register 8-572
Syndrome Register 4-46
TI MER REGI STER (TR) 4-12
Transfer And Set Index Register n
8-623
Virtual Address Trap Register 4-33
working space register 3-14
working space registers 3-9
WORK! NG SPACE REGI STERS (WSRn) 4-21
REPLICATE
replicate a pattern across a string
8-350
RESERVE
Load Reserve Memory Base 8-345
Reserve Memory Base Register 4-43
RESERVED
Reserved memory space 1-8
RET
RET
4-11, 4-16, 8-438
RETURN
Return 8-438
REVERSE
REGI STER BY REG! STER
Divide Register by Register
Scan Characters Double in Reverse
8-502
Scan with Mask in Reverse 8-507
Sequence character reverse 5-14
Sequence Character Reverse (T) 5-19
Test Character and Translate in
Reverse 8-586
8-210
REGI STER FROM REGI STER
Load Complement Register from
Register 8-279
Load Register from Register 8-329
REGISTER TO REGISTER
Add Logical Register to Register
8-46
AND Register to Register 8-56
Compare Register to Register 8-156
Exclusive OR Register to Register
8-222
Load Double Register to Register
Pair 8-308
Load Positive Register to Register
8-325
RI
NS REGISTER THEN INDIRECT (RI) 5-7
Register then Indirect (RI) 5-1
RIGHT
GXn
GXn
GXn
GXn
RIMR
RIMR
Long Right Logic 8-252
Long Right Shift 8-254
Right Logic 8-258
Right Shift 8-260
8-441
REGISTER-To-REGISTER
Register to register Instructions
7-62, 8-12
RIW
RIW 8-442
REGISTERS
History Registers
RL
RL - Register or Length 5-32, 7-24
4-41
RELATIVE
Location relative to base 3-11
RMID
RMID 8-443
REPEAT
Repeat 8-461
Repeat Double 8-446
Repeat Instructions 7-68
Repeat Link 8-454
RMR
RMR 8-444
ROTATE
A-Register Left Rotate
i-38
8-51
DZ51-00
ROTATE (cont)
Long Left Rotate 8-338
Q-Register Left Rotate 8-431
ROUND
true round
S4BD(X)
S4BD(X)
8-471
S6BD(X)
S6BD ex)
8-472
S9BD(X)
S9BD(X)
8-473
8-182, 8-240, 8-245
ROUNDED
Quadruple-Precision Floating Store
Rounded 8-430
SAFE
Load safe Store Register
ROUNDING
hardware rounding option 7-7
rounding operation 8-240
8-330
Bypass Flag (SSBF) 4-19
Operation 8-104
REG! STER (SSR) 4-21
Stack Format 8-107,
RPAT
RPAT 8-445
safe Store
safe Store
SAFE STORE
safe Store
8-108
Store safe
RPD
RPD 8-446
SAREG
SAREG 8-475
RPDA
RPDA 8-446
SARN
SARn 8-474
RPDB
RPDB
8-446
SAVE
Save Descriptor Register n 8-512
RPDX
RPDX
8-446
SB2D
SB2D 8-476
RPL
RPL 4-10, 8-454
SB2DX
SB2DX
RPT
RPT 8-461
SB3D
SB3D 8-481
RSCR
RSCR
SB3DX
SB3DX
RSW
RSW
8-468
8~470
Store Register
8-559
8-479
8-484
SBA
SBA 8-486
RUN
Run PATROL 8-445
SBAQ
SBAQ 8-487
RUNOUT
Tally runout 4-10
Transfer on Tally Runout Indicator
OFF 8-625
Transfer an Tally Runout Indicator
ON 8-627
SBAR
SBAR 8-488
SBD
SBD 8-489
SBLA
SBLA 8-490
i-39
DZ5l-OO
SBLAQ
SBLAQ 8-491
SCR
SCR 5-14
SCR variation 5-19
stack control register (SCR)
8-330
Stack Control Register (SCR)
SBLQ
SBLQ 8-492
SBLR
SBLR 8-493
4-22,
4-22
scu
3-1
History Register 4-49
SCU Configuration Register 4-47
SCU FAULT REGISTER 4-44
CPU SCU 1M}{
SBLXN
SBLXn 8-494
SBQ
SBQ 8-495
SD
SD 5-15
SD variation 5-25
Subtract Delta (SD) variation
SBRR
SBRR 8-496
SBXN
SBXn
SDRN
SDRn
8-497
SC
SC 5-14
SC Variation 5-18
Sequence Character (SC) variation
5-18
SCALING
scaling factor
Scaling factor
5-39, 8-34
7-32
SCAN
Scan Characters Double 8-498
Scan Characters Double in Reverse
8-502
Scan with Mask 8-504
Scan with Mask in Reverse 8-507
SCD
SCD
8-498
SCDR
SCDR
8-502
SCM
SCM
8-504
SCMR
SCMR 8-507
SCPR
SCPR
5-25
4-23, 8-512
SECOND-LEVEL
second-level indexing 5-27
Second-Level Indexing 7-8
SECTION
Section Table 5-75
SEGID
I NSTRUCTI ON SEGMENT I DENTI TY
REGISTER - SEGID (IS) 4-18
SEG!DN
SEGMENT I DENTI TY REGI STERS
4-17
(sn;r Dn )
SEGMENT
Descriptor Segment Descriptor 8-101
I NSTRUCTI ON SEGMENT REG! STER (I SR )
4-15
LI NKAGE SEGMENT REGI STER (LSR) 4-15
Load Parameter Segment Register
8-326
segment base 3-1
segment descriptor 3-1, 5-58
SEG~!ENT DESCRI PTOR REG! STERS (DRn)
4-16
SEGMENT I DENTI TY REG! STERS (SEG! Dn )
4-17
Store Parameter Segment Register
8-556
8-509
i-40
DZ5l-00
(-
SEGMENTS
Layout of Segments on Pages 3-5
Operand Segments 3-6
Segments 5-58
Segments division of working space
3-4
SHIFT (cont)
Q-Register Left Shift 8-432
Q-Register Right Logical Shift
8-433
Q-Register Right Shift 8-434
SEQUENCE
Sequence
Sequence
5-18
Sequence
Sequence
SHRINK
Locating New Bound for Shrink 8-300
Shrink for Extended Descriptors
8-294
Shrink for Standard and Super
Descriptors 8-284
Shrink Operation 8-297
Shrunken Descriptor 3-16
character 5-14
Character (SC) variation
character reverse 5-14
Character Reverse (T) 5-19
SES
SES 7-56
('-
SET
Floating Set Zero and Negative
Indicators from Storage 8-247
Move and Set Sign 7-53
Set Interrupt Word Pair 8-515
set Memory ID Register 8-516
set Memory Register 8-517
Set Pointer Compare Flags Off 8-518
Set System Controller Register
8-527
Set zero and Negative Indicators
from Storage 8-576
Set Zero and Negative Indicators
from Storage and Clear 8-577
Set Zero and Truncation Indicators
with Bit Strings Left 8-578
Set zero and Truncation Indicators
with Bit Strings Right 8-581
Transfer And Set Index Register n
8-623
SET END SUPPRESSSION
Set End Suppression 7-56
SHRINKING
Shrinking 3-16
SIGN
sign and magnitude operands 7-30
Sign flag 7-43
SI NGLE REG! STER
Multiply Single Register by Register
8-368
SINGLE-PRECISION
single-precision data 2-1
SINGLE-WORD
Single-Word Address Modification
5-27
SINGLE-WORD INSTRUCTIONS 7-1
Single-Word Instructions 8-7
SIW
SIW 8-515
SLAVE
Slave mode 1-4
Transfer After Setting Slave 8-620
SHIFT
A-Register Left Shift 8-52
A-Register Right Logical Shift 8-64
A-Register Right Shift 8-66
Data Shifting Instructions 7-3
GXn Left Shift 8-256
GXn Long Left Shift 8-250
GXn Long Right Shift 8-254
GXn Right Shift 8-260
Long Left Shift 8-339
Long Right Logical Shift 8-344
Long Right Shift 8-346
SMID
SMID 8-516
SMR
SMR
8-517
SOURCE
Ignore Source Characters 7-45
Move Source Characters 7-54
i-4l
DZ51-00
SPACE
Base working space address 3-10
framed stack space 8-104
Load Working Space Registers 8-333
Standard Descriptor With Working
Space Number 3-10
Store Working Space Registers 8-564
Super Descriptor With Working.Space
Number 3-12
Working Space 0 1-8.
working space number (WSN) 3-2
working space register 3-14
working space registers 3-9
WORKING SPACE REGISTERS (WSRn) 4-21
working spaces 3-1
Working Spaces 5-58
Working Spaces and Pages 3-2
SPCF
SPCF
8-518
SPDBR
SPDBR 8-519
SPEC! AL-ADDRESS
Special Address Register
Instructions 7-12
SPECIFIER
Address Register Specifier 5-31,
7-24
SPL
SPL 8-520
SSA
SSA 8-526
SSCR
SSCR 8-527
SSQ
SSQ 8-529
STA
STA 8-531
STAC
STAC 8-532
STACK
ARGUMENT STACK REG! STER (ASR) 4-23
DATA STACK ADDRESS REGISTER (DSAR)
4-25
Data Stack Clear Flag (DSCF) 4-19
DATA STACK DESCRIPTOR REGISTER
(DSDR) 4-25
framed stack space 8-104
Load Argument Stack Register 8-277
Load Data Stack Address Register
8-309
Load Data Stack Descriptor Register
8-310
PARAMETER STACK REG! STER (PSR) 4-23
Pop Argument Stack 8-418
stack control register (SCR) 4-22,
8-330
Stack Control Register (SCR) 4-22
Store Argument Stack Register 6-535
Store Data Stack Address Register
8-546
Store Data Stack Descriptor Register
8-547
STACQ
STACQ 8-533
SREG
SREG 5-84, 8-524
SSBF
safe Store Bypass Flag (SSBF)
SSXN
SSXn 8-530
4-19
STANDARD
Shrink for Standard and Super
Descriptors 8-284
Standard Descriptor 3-8, 5-60,
8-101
standard descriptor 8-330
Standard Descriptor (ES) 5-64
Standard Descriptor With Working
Space Number 3-10
Vector for Standard Descriptor,
Super Descriptor 8-281
STAQ
STAQ 8-534
SSR
SAFE STORE REG! STER (SSR ) 4-21
STAS
STAS 8-535
i-42
DZ51-00
(-
STATUS
Memory Error Status Register
4-51
STBA
STBA 8-536
STBQ
STBQ 8-537
STC1
STCl 8-538
STC2
STC2 8-539
STCA
STCA 8-540
STCQ
STCQ 8-542
STDN
STDn 8-544
STDSA
STDSA 8-546
STDSD
STDsn 8-547
STE
STE 8-548
STI
STI
8-549
STO
STO 4-19, 8-551
STORAGE
Add One to Storage 8-61
Add To Storage From A-Register 8-67
Add To Storage From Index Register n
8-69
Add To Storage Frorn Q-Register 8-68
AND to Storage from A-Register 8-57
AND to Storage frorn Index Register n
8-59
AND to Storage from Q-Register 8-58
descriptor storage 3-6
EXCLUSIVE OR to Storage with
A-Register 8-223
STORAGE (cont)
EXCLUSIVE OR to Storage with Index
Register n 8-225
EXCLUSIVE OR to Storage with
Q-Register 8-224
Floating Set Zero and Negative
Indicators frorn Storage 8-247
operand storage 3-6
OR to Storage from A-Register 8-414
OR to Storage from Index Register n
8-416
OR to Storagefrorn Q-Register 8-415
Set Zero and Negative Indicators
from Storage 8-576
Set Zero and Negative Indicators
from Storage and Clear 8-577
STORE
Double-Precision Floating Store
8-181
Double-Precision Floating Store
Rounded 8-182
Floating Store 8-244
Floating Store Rounded 8-245
Load Safe Store Register 8-330
Quadruple-Precision Floating Store
8-429
Quadruple-Precision Floating Store
Rounded 8-430
safe Store Bypass Flag (SSBF) 4-19
safe Store Operation 8-104
SAFE STORE REGI STER (SSR ) 4-21
safe Store Stack Format 8-107,
8-108
Store 6-bit Characters of A-Register
8-540
Store 6-bit Characters of Q-Register
8-542
Store 9-bit Bytes of A-Register
8-536
Store 9-bit Bytes of Q-Register
8-537
Store A Conditional 8-532
Store A Conditional on Q 8-533
Store A-Register 8-531
Store Address Register n 8-474
Store Address Registers 8-475
Store AQ-Register 8-534
Store Argument Stack Register 8-535
Store Base Address Register 8-488
Store Data Stack Address Register
8-546
(
i-43
DZ51-00
STORE (cont)
Store Data Stack Descriptor Register
8-547
Store Descriptor Register n 8-544
Store Double from GXn 8-262
Store Exponent Register 8-548
Store Index Register n in Lower
8-574
Store Index Register n in Upper
8-566
Store Indicator Register 8-549
Store Instruction Counter Plus 1
8-538
Store Instruction Counter Plus 2
8-539
Store Option Register 8-551
Store Page Table Directory Base
Register 8-519
Store Parameter Segment Register
8-556
Store Pointer n 8-553
Store Pointers and Lengths 8-520
Store PTWAM Directory Word 8-555
Store PTWAM Register 8-557
Store Q-Register 8-558
Store Registers 8-524
Store safe Store Register 8-559
Store Test Address Registers 8-562
Store Test Descriptor Registers
8-563
Store Timer Register 8-561
Store Working Space Registers 8-564
Store Zero 8-567
Subtract Stored from A-Register
8-526
Subtract Stored from Index Register
n 8-530
Subtract Stored from Q-Register
8-529
STQ
STQ 8-558
STRING
BIT STRING ADDRESS PREPARATION 5-43
Bit string instructions 7-6
Bit String Instructions 7-34
Bit String Operand Descriptor 5-35
BIT STRING OPERAND DESCRIPTOR FORMAT
7-35
Bit Strings and Index Table of
Translate Instruction 5-85
Character-S~rings 2-2
Combine Bit Strings Left 8-162
Combine Bit Strings Right 8-165
Compare Alphanumeric Character
Strings 8-142
Compare Bit Strings 8-139
replicate a pattern across a string
8-350
Set Zero and Truncation Indicators
with Bit Strings Left 8-578
Set Zero and Truncation Indicators
with Bit Strings Right 8-581
STSS
STSS 4-22, 8-559
STT
STT 8-561
STTA
STTA 8-562
STTD
STTD 8-563
STWS
STWS 4-21, 8-564
STPDW
STPDW 8-555
STXN
STXn 8-566
STPN
STPn 8-553
STZ
STZ
STPS
STPS 8-556
SUBTRACT
Double-Precision Floating Subtract
8-179
Double-Precision Floating Subtract
Inverted 8-180
Double-Precision Unnormalized
Floating Subtract 8-195
STPTW
STPTW 8-557
i-44
8-567
DZSl-OO
(
(
SUBTRACT (can t )
Floating Subtract 8-242
Floating Subtract Inverted 8-243
Quadruple-Precision Floating
Subtract 8-'27
Subtract 4-Bit Displacement from
Address Register 8-471
Subtract 6-Bit Displacement from
Address Register 8-472
Subtract 9-Bit Displacement from
Address Register 8-473
Subtract Bit Displacement from
Address Register 8-489
Subtract delta 5-15
Subtract Delta (SO) variation 5-25
Subtract from A-Register 8-486
. Subtract from AQ-Register 8-487
Subtract from Index Register n
8-497
Subtract from Q-Register 8-495
Subtract Logical from A-Register
8-490
Subtract Logical from AQ-Register
8-491
Subtract Logical from I ndex Register
n 8-494
Subtract Logical from Q-Register
8-492
Subtract Logical Register from
Register 8-493
Subtract Register from Register
8-496
Subtract Stored from A-Register
8-526
Subtract Stored from Index Register
n 8-530
Subtract Stored from Q-Register
8-529
Subtract Using Three Decimal
Operands 8-481
Subtract Using Three Decimal
Operands Extended 8-484
Subtract Using Two Decimal Operands
8-476
Subtract Using Two Decimal Operands
Extended 8-479
Subtract with Carry from A-Register
8-568
Subtract with carry from Q-Register
8-570
Subtract Word Displacement from
Address Register 8-572
SUBTRACT (cant)
Unnormalized Floating Subtract
8-635
SUPER
Shrink for Standard and Super
Descriptors 8-284
Super Descriptor 3-11
Super Descriptor With Working Space
Number 3-12
Vector for Standard Descriptor,
Super Descriptor 8-281
Virtual Address Generation, Super
Descriptor 5-61
SUPPRESSION
End Floating Suppression 7-44
End suppression flag 7-42
Insert Asterisk on Suppression 7-45
Insert Blank on Suppression 7-46
Move with Zero Suppression and
Asterisk Replacement 7-54
Move with Zero Suppression and Blank
Replacement 7-55
SWCA
SWCA 8-568
SWCQ
SWCQ 8-570
SWD(X)
SWD(X)
8-572
SXLN
SXLn 8-574
SYMBOLS
ABBREVIATIONS AND SYMBOLS 8-3
index register symbols 5-35
Move with Floating Currency Symbol
Insertion 7-48
SYNC
SYNC 8-575
SYNCHRONIZE
Gate Synchronize 8-575
SYNDROM
Syndrome Register
i-45
4-46
DZ51-00
SYR
Syndrome Register
4-46
SYSTElJ.
Read System Controller Register
8-468
Set System Controller Register
8-527
System Controller Illegal Action
COdes 4-36, 4-38
SYSTEM CONTROLLER INTERRUPTS 6-23
SZN
SZN
TABLE (cont)
page table directory 3-2
Page Table Directory Word 5-72
Page Table Directory Word (PTDW)
Format. 5-68
Page Table Word (PTW) Format 5-70
Section Table 5-75
Store Page Table Directory Base
Register 8-519
translation table length 8-401
TABLES
Page Tables 3-2
8-576
TABULAR
processing of tabular data 5-13
processing tabular operands 5-20
SZNC
SZNC 8-577
TAG
asterisk placed in the tag 5-8
tag designator (td) 5-2
Tag Field 5-2
Tag Field Modification ES 5-52
tag modifier (tm) 5-2
SZTL
SZTL 8-578
SZTR
'SZTR 8-581
T
Decrement Address,
(T) 5-21
Decrement Address,
and Continue (T)
Increment Address,
(T) 5-20
Sequence Character
TA
Increment Tally
Increment Tally,
5-21
Decrement Tally
Reverse (T)
5-19
Alphanumeric Data Type (TA) Codes
7-27
TABLE
Bit Strings and Index Table of
Translate Instruction 5-85
Change Table 7-44
Dense Page Table 5-72
Edit Insertion Table 7-39
Insert Table Entry One Multiple
7-46
Load Connect Table Register 8-269
Load Page Table Directory Base
Register 8-340
Load Table Entry 7-48
Locating the page table directory
word 5-72
Page Table Base Word (PBW) Format
5-69
TALLY
Decrement Address, Increment Tally
(T) 5-21
Decrement Address, Increment Tally,
and Continue 5-23
Decrement Address, Increment Tally,
and Continue (T) 5-21
Increment address decrement tally
5-14
Increment Address, Decrement Tally
(T) 5-20
Increment address, decrement tally,
and continue 5-15
Increment Address, Decrement Tally,
and Continue 5-22
increment tally 5-14
Indirect Then Tally (IT) 5-1
NS Indirect Then Tally (IT) 5-13
TALLY 5-14
tally designator 5-2
Tally Designators 5-16
Tally runout 4-10
Transfer on Tally Runout Indicator
OFF 8-625
Transfer On Tally Runout Indicator
ON 8-627
i-46
DZ51-00
('
TALLYB
TALLYB 5-14
TPL
TPL 8-602
TALLYD
TALLYD 5-15
TPNZ
TPl-o'Z 8-604
TCT
TCT 8-583
TR
TCTR
TCTR 8-586
TRA
TD
TI MER REGI STER
TRA
4-12
8-607
TRANSFER
tag designator (td)
5-2
TEO
TEO 4-9, 8-587
TEST
Store Test Address Registers 8-562
Store Test Descriptor Registers
8-563
Test Character and Translate 8-583
Test Character and Translate in
Reverse 8-586
TEU
TEO 4-9, 8-589
C"
(TR)
TIMER
Interval Timer 1-8
Load Timer Register 8-332
Store Timer Register 8-561
T1 MER REGI STER (TR ) 4-12
'I'M
tag modifier (tm)
TMI
'I'M!
8-591
TMOZ
TMOZ 8-593
TNC
TNC 8-596
TNZ
TNZ 8-598
TOV
TOV 8-600
5-2
Domain Transfer 8-96
Domain Transfer (ClJMB) 7-58
GCLIMB (Lateral Transfer LTRAS) - 10
8-125
Lateral Transfer - LTRAS 8-125
Transfer After setting Slave 8-620
Transfer And Set Index Register n
8-623
Transfer Instructions 7-66
Transfer On Garry 8-609
Transfer On Count 8-611
Transfer On Exponent Overflow 8-587
Transfer On Exponent Underflow
8-589
Transfer On Minus 8-591
Transfer On Minus Or Zero 8-593
Transfer On No carry 8-596
Transfer on Nonzero 8-598
Transfer On Overflow 8-600
Transfer On Plus 8-602
Transfer On Plus And Nonzero 8-604
Transfer on Tally Runout Indicator
OFF 8-625
Transfer On Tally Runout Indicator
ON 8-627
Transfer On Truncation Indicator OFF
8-614
Transfer On Truncation Indicator ON
8-617
Tra~sfer On Zero 8-630
Transfer Unconditionally 8-607
TRANSLATE
Bit Strings and Index Table of
Translate Instruction 5-85
Compare Characters and Translate
8-145
Test Character and Translate 8-583
Test Character and Translate in
Reverse 8-586
(i-47
DZ5l-00
TRANSLATION
address translation 5-68
Address Translation Process 5-68
Move Alphanumeric with Translation
8-400
Translation look-aside buffer 5-71
translation table length 8-401
TRANSLI TERATION
transliteration
TTF
TTF 8-625
TTN
TTN
8-627
TYPE
Alphanumeric Data Type (TA) Codes
7-27
7-7
'l'ZE
TZE
TRAP
Address Trap Register 4-32
Virtual Address Trap Register
4-33
TRC
TRC 8-609
UNDERFLOW
Exponent underflow 4-9
Transfer on Exponent Underflow
8-589
TRTN
TRTN 8-617
UNNORt·~ALI ZED
8-182, 8-240, 8-245
TRUNCATE
Floating Truncate Fraction 8-248
Unnormalized Floating Truncate
Fraction 8-636
TRUNCATION
Address Truncation 5-83
Set Zero and Truncation Indicators
with Bit Strings Left 8-578
Set Zero and Truncation Indicators
with Bit Strings Right 8-581
Transfer On Truncation Indicator OFF
8-614
Transfer On Truncation Indicator ON
8-617
TSS
TSS 4-11, 8-620
TSXN
TSXn 8-623
8-634
UFS
UFS 8-635
TRTF
TRTF 8-614
TRUE ROUND
true round
UFA
UFA 8-632
UFM
UFM
TRCTn
TRCTn 8-611
8-630
Unnormalized Floating Truncate
Fraction 8-636
UPPER
Load Index Register n from Upper
8-335
NS Direct Upper (OU) 5-4
Store Index Register n in Upper
8-566
UPPER-BOUND
upper-bound check
5-85
VALID
valid mnemonics for address
modification 5-2
VALUE
base value 5-58
Binary ~epresentation of Fractional
Values 2-8
bound value 5-58
octal value of the operation code
8-2
i-48
DZ5l-00
(
(
VALUES
IC Values Stored on Faults and
Interrupts 6-25
VIRTUAL (cont)
Virtual Memory-Generated Faults
6-10
VARIATION
AD Variation 5-24
Add Delta (AD) variation 5-24
Character Indirect (CI) variation
5-17
CI Variation 5-17
DI Variation 5-21
DIC Variation 5-23
F Variation 5-17
Fault variation 5-17
I Variation 5-19
ID Variation 5-20
ID variation 5-21
IOC Variation 5-22
Indirect (I) variation 5-19
SC Variation 5-18
SCR variation 5-19
SO Variation 5-25
Sequence Character (SC) variation
5-18
Subtract Delta (SD) variation 5-25
variations under IT modification
5-13
variations Under IT t·iodif ication
5-17
WATER
(HWMR) 4-24
High Water Mark Register 8-109
VECTOR
Vector for Standard Descriptor,
Super Descriptor 8-281
vectors 3-4
VFD
VFD 7-13
VIRTUAL
Mapping The Virtual Address To A
Real Address 5-71
Virtual address 3-2
Virtual Address 5-72
Virtual Address Generation (ES)
5-64
Virtual Address Generation (NS)
5-59
Virtual Address Generation, Super
Descriptor 5-61
Virtual Address Trap Register 4-33
Virtual Memory 3-1
Virtual Memory Addressing 5-57
Virtual Memory Instructions 7-58
WORD
Indirect Word 5-40
Indirect Word Format 5-16
INSTRUCTION WORD FORMATS 8-7
Locating the page table directory
word 5-72
Machine Word 2-1
Page Table Base Word (PBW) Format
5-69
Page Table Directory Word 5-72
Page Table Directory Word (PTDW)
Format 5-68
Page Table Word (PTW) Format 5-70
Store PTWAM Directory Word 8-555
Subtract Word Displacement from
Address Register 8-572
word address 5-35
Word and Double-Word Operations
5-84
WORD PAIR
Read Connect Word Pair 8-437
Read Interrupt Word Pair 8-442
Set Interrupt Word Pair 8-515
WORKING
Base working space address 3-10
Load Working Space Registers 8-333
Standard Descriptor With Working
Space Number 3-10
Store working Space Registers 8-564
Super Descriptor With working Space
Number 3-12
Working Space 0 1-8
working space number (WSN) 3-2
working space register 3-14
working space registers 3-9
WORKING SPACE REGISTERS (WSRn) 4-21
working spaces 3-1
Working Spaces 5-58
Working Spaces and Pages 3-2
WSN
Extended Descriptor With Working
Space Number 3-13
(
i-49
DZ51-00
\
WSN (cont)
working space number (WSN)
WSN 5-68
3-2
WSPTD
WSPTD 5-68, 5-72
WSR
WSR 3-9
WSRN
WORKING SPACE REGISTERS (WSRn)
4-21
XO/GXO
XO/GXO Loading Xn/GXn 8-123
XEC
XEC 8-637
XED
XED 8-639
XN
! NDEX REG! STERS (Xn)
Y-PAIR
Y-pair
4-6
2-2
ZERO
Floating Set Zero and Negative
Indicators from Storage 8-247
Move with Zero Suppression and
Asterisk Replacement 7-54
Move with Zero Suppression and Blank
Replacement 7-55
Set Zero and Negative Indicators
from Storage 8-576
Set Zero and Negative Indicators
from Storage and Clear 8-577
Set Zero and Truncation Indicators
with Bit Strings Left 8-578
Set Zero and Truncation Indicators
with Bit Strings Right 8-581
Store Zero 8-567
Transfer On Minus Or Zero 8-593
Transfer On Zero 8-630
Working Space 0 1-8
Zero flag 7-43
\1.
i-50
DZ51-00
(
(
• ..
'
67 A2
DZ51-00
".
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2018:03:05 16:49-08:00 Modify Date : 2018:03:05 17:35:14-08:00 Metadata Date : 2018:03:05 17:35:14-08:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:2987f9fc-9458-5741-8314-14e8d175e590 Instance ID : uuid:244a9042-3c09-1140-984f-b04b88a0bb83 Page Layout : SinglePage Page Mode : UseNone Page Count : 1010EXIF Metadata provided by EXIF.tools