Digital_Computer_Interfacing_Accessories_and_Logic_Handbook_CIA1_1978 79 Digital Computer Interfacing Accessories And Logic Handbook CIA1 1978

Digital_Computer_Interfacing_Accessories_and_Logic_Handbook_CIA1_1978-79 Digital_Computer_Interfacing_Accessories_and_Logic_Handbook_CIA1_1978-79

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computer
in~adng
•

accessones
and logic haldbook

CIA 1

1978-79

GENERAL INFORMATION
INTRODUCTION TO INTERFACING-DIGITAL NOMENCLATUREMODULE DIMENSIONS

MINICOMPUTER INTERFACING MODULES
pop-a, PDP-II SERIES COMPUTERSINTERFACING SELECTOR GUIDE

MICROCOMPUTER INTERFACING MODULES
LSI-11 SERIE$ COMPUTERSINTERFACING SELECTOR GUIDE

GENERAL PURPOSE LOGIC & CONTROL MODULES
M-SERIES, A-SERIES, K SERIES-FOR INTERFACING, COMMUNICATIONS,
AND SPECIAL APPLICATIONS

CABINETS AND PARTS
SYSTEM ENCLOSURES, MOUNTING HARDWARE,
CONNECTORS, POWER SUPPLIES, OTHER DESIGN AIDS

CABLES
COMPLETE ASSEMBLIES AND PARTS

ABOUT DIGITAL
HISTORY
PRODUCTS

-ALPHANUMERICAL PRODUCT IND~
HOW TO ORDER,
WARRANTEE

\

ii

~D~DDmD

com~

interr:acilg

•
accessones
and logic haldbook

1978-79
CIA 1
•

prepared
by
logic products
digtalequipment corporation

. l

iii

Copyright© 19?5 by Digital Equipment Corporation
Digital Equipment Corporation makes no representation that the interconnection of its modular circuits
in the manner described herein will not infringe on
exlsting or futur~ patent rJghts. Nor do the descriptions contained herein imply the granting of licenses
to make, use, or sell equipment constructed in accordance herewith_
The information in this document is subject to change
without notice, and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any
errors that may appear in this document.

FLIP CHIP, UNIBUS and OMNIBUS are
trademarks of Digital Equipment Corporation,
Maynard, Massachusetts.

iv

FOREWORD ............................................................................................ .

vii

GENERAL INFORMATION ..........................................................................
Logic Products for Computer Interfacing .................... ..................
Related Literature ......................................... ...................................
Basic Hardware Nomenclature ..........................................................
Module Contact Finger and Module Connector Block
Contact Identification ................................................................
Module Cleaning ........................................................:.......................
Special Signals and Abbreviations ....................... .............................

I

1
2

3
5
10

11

MINICOMPUTER INTERFACING MODULES ............................................. 17
PDP-8 FAMILY OMNIBUS Interfacing Principles ............................. ,.. 18
OMNIBUS-Related Interface Modules (with Selector Guide).... 22
PDP-11 FAMILY UNIBUS 'Interfacing Principles ............................... 46
UNIBUS-Related Interface Modules (with Selector,Guide) ........ 49
TRADITIONAL MODULES ............................... , .................................. 120

·~g~~~IN~~.~~~~.I.~~.~.. :::::::::::::::::::~.::::::::::::::::::::::::::::::::::::::::: ~~~

PDP-15 ....................................................................................... 122
DECKits .......................................................; ............................ 123

,.

.

MICROCOMPUTER INTERFACING MODULES .............................................
lSI-II Family .....................................................................................
LSI-ll Interface Modules (with Selector Gutde) ..............................
LSI-II CHIPKITS ..............................................................................
CHIPKIT Applications Note ............................ :,..................................

126
126
129
164
166

GENERAL PURPOSE LOGIC AND CONTROL MODULES ............................
M SERIES ..............................................\ ...........................................
General Characteristics ............................................................
Operating Characteristics ..........................................................
Module Index ......................................................... ~.................
A SERIES ..........................................................................................
K 'SERIES ..........................................................................................

226
227
227
228
235
377
394

CABINETS AND PARTS .............................................................................;
Cabinets and Cabinet Accessories ....................................................
Module System Enclosures and Expansion Mounting Boxes ............
Power Supplies ..................................................................................
19-inch Rack Mounting Panels ..........................................................
Four-Slot System Units ... " ...............................................................
Nine-Slot System Units ....................................................................
Module Connector Blocks ................................................................
Blank Module Boards ........................................................................
Collage Module Boards ....................................................................
Module Extender Boards ........................ : .........................................
Wire Wrappable Modules ....
.. .........................

398

v

399

414
422
429
431
433 .
439
441
443

444
445

Wire Wrappable Tools & Accessories ................................................
Integrated Circuit Sockets ................................................................
Module Handles, Module Handle Extenders, and Module Holders ..
Bus Strips ............................................................................:-:-:-:-:-.........
Patch Cords ........ '.............................................-............................. ,. ..

454
456
456
457
458

CABLES .................................................................................................... 396
Cable Assemblies .............................................................................. 396
Cable Accessories .............................................................................. 398
ABOUT DIGITAL EQUIPMENT CORPORATION .......................................... 482

History .............................................................................................. 482
General Information ................................................ , ......................... 483
Digital Products ................................................................................ 485
WARRANTY

.............................................................................................. 487

HOW TO ORDER ... : ........... :........................................................................ 488
ALPHANUMERICAL PRODUCT INDEX ...................................................... 489

,/

,/

vi

This .Computer, Interfacing Accessories and Logic Handbook is your guide to -'
the most extensive line of products offered by Digital Equipment Corporation
for implementing logic designs. Whether you need a connector block or a
cable, a general·purpose logic module or a complete interfal?e, a computer
expansion box ora cabinet for an entire system--<:heck this handbook first.
If you already knOw the part number of the product you need, the Index at
the back is the best place to start. Otherwise go to the relevant cnapter.
The major new products featured in this edition are the CHIPKIT series of
integrated circuits. CHIPKITS allow exceptionally easy implementation of your ,
interface designs for LSI·II microcomputers, and we have included an extensive applications note .in !his handbook.
The largest single portion of this handbook describes our M series of TTL
modules .. This line ranges from basic logic gates through complete digital
subsystems that make extensive use of MSI and LSI circuitry. New in this
edition are the M7800 and M7860 asynchronous serial interfaces for the
PDP-ll series UNIBUS. ,
Also featured in this handbook are the K series of high noise-immunity industrial-control modules, the A series: of analog-related modules, and the W
series of wire-wrappablemodules, collage modules, and blank modules;
The products in this handbook, including the mounting hardware, cables,
and cabinets described in the last two chapters, allow you to design and
construct systems small or large, that are neat, modular, and compatiblewith a minimum of lost time and effort.
If you need unique functions that you don't find covered in this handbook,
contact your local DIGITAL sales office. The hardware product you need may
be avai/abte as a non-standard item, or could be provided by our Custom
Module Products Group or Custom Enclosures Products Group. These groups
can design, manufacture, and test not only modules, but also the hardware,
accessories, and enclosures to make a complete system.

vii

.-,

Aworldwide staff of DIGITAL sales engineers is prepared to respond to your
technical and commercial needs! 'From a backlog of logic system design experience, DIGITAL may have a detailed solution' to your application or inter.
face requirement.
A separate price supplement booklet is available for varioaa countries.
Please address any comments on this handbook, or inquirie.s cC?ncerning
special services, to:
Digital Equipment Corporation
Logic Products Sales Support, MKI-2/E 13
Merrimack, NH 03054

DIRECT SALES\eATALOG
We would also like to dife«;t your. attention to the latest concept in
purchasing computer-related equipment-the DIGITAL Direct Sales
Catalog. By ordering products directly through the Catalog, you
may save substantial dollars. Many of the items (terminals, microcomputers, interface modules, hardware/accessories, etc.) in this
Handbook are now available for purchasing through the Catalog.
To· find out if this Catalog program can benefit you, mail in now.
the post card attached elesewhere in this book. The Catalog program is applicable to ordering and shipping points in the U.S.A.
only.

viii

GENERAL INFORMATION
INTRODUCTION TO INTERFACIN---!..!_~AN~~::::

INITIALIZE H [iJAU2

I PART OF

M~S10)

I
FUNCTION NAMES

F'----a~L
~_----<(]UP

L
ON H
t=-----IENABLE H

I PART OF M236)

C~TINH

Figure 13

Signal and Function Names

Digital Equipment Corporation uses standard terminology to name signal
lines to aid the reader in determining their active state. Either an H or L
follows the signal name mnemonic, separated by a space. This letter indicates the asserted (true) state of the signal. An H means the signal is asserted when HIGH (+3 V) and an L means the signal is asserted when LOW
(0 V). For example, a UNIBUS data line is called BUS 000 L and a grant
line is called BUS BG4 H.
On the logic diagrams of many computer interfacing modules in this handbook, signal names peculiar to one computer, such as the PDP-II, appear
as an example of typical usage. Signal names may be changed to those of
another computer or interfacing device if logically appropriate.
Function names ap~ear inside the blocks of functional modules.· They identify the function of input or output signals. The user may add his own signal
names.
Abbreviations
Abbreviations used in signal and function names in this handbook are defined in Table 1.

14

Table I-Abbreviations

ALTN
AMPL

~

!

"

DEFINITION

ABBREVIATIONS

Alternate

.

Amplifier

ANLG

Analog

BPS

Bits Per Second

CAP

Capacitor

CLR

Clear

CMPR

Compare

COM

Common

CONT

Control

CVRSN

Conversion

DAC

Digital to Analog Converter

EXT

External

,/

GND

Ground

H

High (TIL + 2.0 to +5.0 V Logic Level)

INIT

Initiaiize

INT,INTR

Interrupt

INTL

Internal

L

Low (TIL 0.0 to 0.8 V Logic Level)

OUT

Output

P.I.

Program Interrupt

POT

Potentiometer

PRGM

Program.

REF

Reference

RTN

Return

SER

Serial

S.H.

Sample and Hold

TRIG

Trigger

15

•
-I

*

\

16
(

1

MINICOMPUTER INTERFACING MODULES
PDP·a, PDp·ll SERIES COMPUTERSINTERFACING SELECTOR GUIDE

,-

I

•

17

~

SERIES MODULES FOR
COMPUTER INTERFACING

INTRODUCTION
Design and support of interfaces for PDP computers is a major function of
M Series modules. This edition of the Logic Handbook emphasizes a collection "of modules for interfacing to the following processors:
INTRODUCTION
Design and support of interfaces for PDP computers is a major function of
M Series modules. This edition of the handbook emphasizes a collection of
moduesfor interfacing to the following processors:
-POP-8 Family
• PDP-8/A, 8/E, 8/F, 8/M (OMNIBUS)
-PDP-II Family

I

This section consists of -a separate subsection for each processor. Within
each subsection, there is a brief overview of interfacing theory, an Interface
Selector chart. and individual descriptions of related modules.

PDp·8 FAMILY COMPUTER INTERFACING
The PDP-8 family of computers remains the undisputed leader in the minicomputer industry with over 20,000 installations to date. Since its inception
in 1964, the POP-B has been continually improved. Each model has become
more powerful, more efficient, and faster. At the same time, system cost and
size have been reduced to less than 25 percent of original figures. More importantly, these improvements have been made without sacrificing software
and hardware compatibility. Programs written for the earliest PDP-8 can be
run on the newest POP-8; peripheral devices that operated with earlier PDP-8s
can be made to operate with the latest PDP-B.
This section contains hardware interfacing information and related I/O module descriptions for all POP-8 models listed.
-.oMNIBUS-POP-8/A, 8/E, 8/F, 8/M
The non-OMNIBUS-related modules are contained in the Traditional Modules
section.

PDP·8/A, 8/E, 8/F, 81M (OMNIBUS) Interfacing
,
This subsection consists of general interfacing information for the POP-8/ A,
8/E, 8/F, and 8/M- processors, followed by detailed .descriptions of related
modules.
General OMNIBUS Interfacing PrinCiples
The POP-8/ A, B/E, 8/F, and 8/M are the newest 12-bit word length processors offered by DIGITAl. These processors utilize the OMNIBUS concept for
transferring commands and-signals among modules within a system.
Physically, the OMNIBUS is an etched board with rows of module connectors
soldered to the board. The pin assignment is the same on all connectors. The
OMNIBUS consists of 96 signals which feed to 96 pins on the connectors.
The user is generally only concerned with those signals that control data
transfers, address memory, or contain the data to be transferred. However,
the additional signals, such as timing, are readily available on the OMNIBUS
to accommoda/te any tailor-made requirement in the event that the user
18

\ .

should design and build his own interface module. A single OMNIBUS assembly accommodates 20 PDP·S/A, S/E,. S/F, or S/M ·modules.
The OMNIBUS bus structure employs bidirectional data and control lines plus
a few undirectional control signals. Each bus line is a matched and terminated transmission line that must be received and driven with devices designed
for that specific application. All M Series modules designed for interconne~·
tions to the OMNIBUS employ special high·impedance bus driver and bus
receiver circuits appropriate for such bus lines. All drivers (identified by a
"0" in· the logic symbol) are open·collector gates that control the bus through
a wired-OR connection. All receivers (identified by the "R" in the logic symbol) are high-impedance gates that present a minimum of loading to the bus
line. A module may have unused bus driver or bus receiver circuits that can be
used with TTL devices, provided the following loading rules are observed:
Receiver Loading: The bus receiver input presents two TTL unit loads (in the

High state) to a TIL output and has a normal fan·out of 10.
Driver Sink Capability: The open'collector bus drivers are capable of sinking
at least 50 mA, with a collector voltage of 0.8 volts or less. The collector
voltage, when not sinking curreJlt, must be less than +6 volts. Leakage current (in the H~gh state) js less than 25 p.A. The input of a bus driver presents
a singre TTL unit load to a TTL output.
There are three types of data transfer: programmed data transfers, program
interrupt transfers, and direct memory access transfers. Programmed data
transfer is the easiest and most direct method of handling data I/O. Program
interrupt transfers provide an extension of programmed I/O capabilities by
allowing the peripheral device to initiate a data transfer. The data break sys·
tern uses direct memory access for applications involving the fastest data
transfer rates.
Table 1 lists and describes the signals on the OMNIBUS-related processors
that are used for programmed and interrupt I/O control. More complete de·
scriptions for these and data break transfer signals are contained in the
SMAll COMPUTER HAN DBOOK.
.

Table 1.

OMNIBUS 1/0 Signal-Summary

SIGNAL

DEFINITION

MDO-ll

Contains the device select code for an I/O instruction. Bits
3-S contain the device select code; bits 9-11 specify the
operation sel.act code within that device.

I/O PAUSE L

Asserted /by the processor when the instruction is an I/O instruction (6XXXs).

TP3H

TP3H is normally used to clock data into the output buffer
of an output interface.

INTERNAL
I/OL

INTERNAL I/O is asserted by the interface to indicate to the
processor that the selected device is not on the Extelnal
I/O Bus.

19

Table 1. (OMNIBUS 1/0 Signal Summary (Continued)
DEFINITION

SIGNAL
DATAO-ll

Clines
CO, Cl, C2

The 12 DATA lines called DATA BUS serve as a bidirectional
bus for both input and output data between the AC register
in the processor and the interface buffer register_
• Signals CO, Cl, C2 are asserted by the interface during I/O
instructions to notify the processor whether data is to be
placed onto the DATA BUS or received from the DATA BUS
by the processor.

INT RQST L

INT RQST is the- method by which the device signals the
processor that it must be serviced. The proceS,$or will then
branch to a subroutine which issues a skip lOT to each
device to idrntify the one that is interrupting.

SKIP L

Asserted by the interface as the result of a skip lOT if an
interrupt is being requested. Used to identify the interrupting device by causing the processor to skip the next instruction.
•

BUS
STROBE L

BUS STROBE is used to loa~ the AC and PC registers_ Unless special I/O operations are being perlormed, the designer of an interface need not concern himself with BUS
STROBE.

NOT LAST
XFER L

A ground level on this line indicates to the processor that
the next BUS STROBE does not terminate the I/O transaction. Typical I/O tranfers will not use this signal.

RUN L

When low, RUN indicates that the machine is executing instructions. Can be used to notify an interface -that the
processor has stopped.
-

TSI L
TS2 l
TS3 L

TS4 l
TPI
TP2
TP3
TP4

H
H
H
H

INITIALIZE H

These are the internal machine cycle time states and time
pulses. Each time state precedes its corresponding time
pulse. Time states are always 200 ns or more in duration,
and change 50 ns after the leading edge of the time pul~~.
Time pulses are 100-ns positive-going pulses. The exact
spacing of the timing pulses is a function of fast or slow
cycle. Only TP3H is used in the typical interface.
INITIALIZE is a positive-going 600-ns pulse used to clear
AC, LINK, and flags in peripherals. It is generated when
power IS first applied to the processor, by the Clear key on
the console and by lOT 6007.

The following is a brief summary of the basic sequence of I/O transactions
for programmed data transfers and interrupt data transfers. This information
is provided here as a keneral reference aid; detailed descriptions are contained in the SMALL COMPUTER HANDBOOK and MINIPROCESSOR HAND-

BOOK.
20

For programmed data transfers, the computer p'rogral1) issues an input!
output instruction to, first, select the desired peripheral and, second, direct
the peripheral to generate certain operating control., signals called lOTs. The
input/output instructions are transmitted to the peripheral via the MD
(Memory Data) lines 00 through 11. Each peripheral contains circuitry that
monitors the MD lines. MD03 through MDOB carry a device selection code
which is unique for each peripheral. Lines Mf>09 through MDII carry com:
mand operate signals that the selected peripheral must translate into one of
eight lOT functions for that device. Signal I/O PAUSE is also generated by
the processor at this time. I/O PAUSE notifies all peripherals that the MD
lines contain an I/O instruction. Note that the interface does not have to
monitor MD lines 0-2 to detect a 6". I/O PAUSE occurs after the MD lines
have settled and is used to actually gate the device select and the operation
codes into the interface.
The lOT functions vary depending upon the type of peripheral but genera ny,
they consist of sampling and clearing status flags and reading, loading, and
clearing data buffers. For data inputs into the processor, the interface bus
drivers are enabled by the appropriate lOT. For data outputs from the processor, the lOT is gated with TP3 H and the resulting signa~ is used to load
the desired output register. The Control lines (CO, CI, C2) must be configured by the device interface during an I/O instruction to notify the processor of the type of transfer that will occur between the device and the
processor. These lines control the data path within the processor and determine if data is to be placed onto the data lines (output) or received from
the data lines (input). The INTERNAL I/O signal must also be generated to
notify the processor that an extended cycle is not needed.
The interrupt facility is a more efficient method of I/O transfer. This method
includes all of the above elements of programmed data transfers except the
time of transfer. Instead of waiting for the processor to check the- peripheral, the peripheral signals the processor that it has data to be serviced by
asserting the INT RQST line. The processor interrupt system detects the INT
RQST signal and enters a subroutil)e to determine the identity of the requesting device by sending an I/O instruction to each peripheral which causes the
SKIP line to be asserted if the peripheral is asserting the interrupt signal.
When this identity has been established, a servicing subroutine causes the
peripheral to enter a normal programmed data transfer sequence.

21

PDp·8 OMNIBUS-RELATED INTERFACING MODULES
Table 2 summarizes the interfaces and related modules that are described in
detail on the following pages.

Although each interfacing problem is likely to have some unique aspects, the
steps to follow in general are:

1. Determine your interfacing requirements.
2. Match these requirements against the products listed in Table 2, then read
the detailed descriptions.
'3. Select suitable products if any are listed. If no listed products meet your
requirements, contact your DIGITAL Field Sales office to find if any other
DIGITAL products can perform the needed functions.
4. Add the power and mounting space requirements of all modules to be'
'employed, and note the cables needed plus any prerequisites and restrictions that apply.
5. From the appropriate sections of this Handbook and the Hardware/ Accessories Catalog, select the cables, power supplies, and mounting hardware
to complete your system.
If you need technical assistance with any product in this Handbook, feel free
to catl DIGITAL's toll-free Hot Line, 8:30AM to 5:00PM Eastern time, 800-258·
1710. From New Hampshire locations or places outside the United States, call
Merrimack, 603-884-6660.

22

<

/
Table 2

N
W

DEVICE OR FUNCTION

MODULE
OR
OPTION

2-word parallel input interface

DR8-ED

1-word parallel input interface

M1703

2-word parallel output interface

M1705

Interface foundation module

M1709

Wlre·wrappable module, no sockets
Wire·wrappable module, with sockets

W966
.,W967

Interface Selector Guide--PDP-8 OMNIBUS
LOGIC
H'BOOK
PAGE'

POWER
+5V
AMPS1

MODULE
SIZE
L H'WI

1.5

"E Q S

.555

1.15

.830+

CABLE
REQ'D

1

BC04Z,
BC07D, or
BC08R

E Q S

BC04Z,
BC07D, or
BC08R

E Q S

BC04Z,
BC07D, or
BC08R

EQ9

1

E Q S
EQ S

(

COMMENTS

BC04Z,
BCOlD, or
BCO&R

Can accept user ICs with up to 40 pins

BC04Z,
BC07D, or
BC08R

Can accept up to 42 14- or 16'pin user ICs

NOTES:
1. + means current required by user logic must be added to figure shown.
2. Module sizes are given as Length, Height, and W~dth, as defined in General Information.

i

'.

PDP-8/A,

DRS-ED
2-WORD INPUT ,INTERFACE

8/E, 8/F or

/JIM

OMNr-

BUS
M SERIES

Length: Extended
Height: Quad
Width: Single

,,/

DESCRIPTION
The DRS-ED is a complete, general purpose input interfCH:e used to transfer two independent 12-bit, parallel data words from a user's peripheral device to a PDP-S computer system as shown on Figure L It is directly compatible with the OMNIBUS of a PDP-S/A, 8/E, 8/F, or 8/M and is designed
for installation in any available OMNIBUS slot except 1, 2, and 3 of a POPS/A.
The DRS-ED consists of a device selector and lOT decoder logic, interrupt
request and skip control, and two 12-bit Data Buffer Registers (DBRs)-one
for each data word, and two independent Control and Status Registers (CSRs).
One CSR is assigned to each input data word and provides status and control informati~n during word transfers.
Two control and two status lines between the user's device and the module
permit the establishment of a handshake routine to efficiently control the
data transfers.
All input data, status and control Signals from the user's device are diode
protected for TTL operation. The Data Buffer Registers provide input latching capability for the 12 data lines from each device.
24

12 BIT WORD
DEVICE A
STATUS CONTROL

12 BIT WORD
DEVICE 8

A

.1\..
vi'
-1'\,

~
OR8-ED
INPUT
INTERFACE

-v-

STATUS & CONTROL

Figure 1

,~

MD .UNES

12 BIT DATA IN

~

~

~~
IS)

DATA OUT

Z

~

0

CONTROL

DRS-ED Interface

Two independent device select circuits are included on the module, one associated with each device. Each circuit contains six Dual In-Line Package
(DIP) switches to allow the selection of a device address from the full complement of OMNIBUS device addresses. These switches facilitate the installation of the module by eliminating the need to solder or remove jumper
leads for device address selection.
,

The DRS-ED is designed for user application and requires a minimum of external hardware to implement into a PDP-S system. Two 40-pin connectors
are conveniently mounted near the edge of the board to permit either one or
two devices to be easily connected using BC08R or BC04Z flat cable assemblies available from DIGITAL. These cables have mating connectors premounted and can be supplied in any required length.
The interlace module occupies one slot in the OMNIBUS or expander and is
quad-height, extended-length, single-width board.
FUNCTIONS
The main elements of the DR8-ED input interlace and the data control and
status signal flow are shown on the block diagram. The module provides the
complete interlace logic necessary for the efficient transfer of data from a
user's device to the PDP-S OMNIBUS.
.'
DATA BUFFER REGISTERS
Each of the two OBRs latch 12 bits of data from a user's device when the
Data Ready signal is generated. The data is also latched into the DBR by
the lOT command from the PDP-S that reacts in the data word. Input data is
not required to be held by the device for the entire transfer operation, thereby
permitting faster data transfers.
CONTROL STATUS REGISTERS
Each CSR is a 12-bit register used to supply control and status information
to the user's device and to provide controf and status indicators of the user's
device and interface to the processor. The CSR also includes input latching
for ·-four extra data bits to allow the DRS-ED to' interface with devices of up
to 16 bits without the need of external multiplexing.

25

.

FROM
USER'S
DEVICE B

A lOT COMMANDS
FROM
. lOT
DECODER
DATA READY IN A

~).

{
B

lOT COMMANDS
OEV

~A______
A lOT COMMANDS I FROM lOT
DECODER
~=:::'J.

STATUS OUT A
USER'S
DEVICE
A

\

"I
CSR

Po

DATA ACCEPTED OUT Po

MUX

.A

~

8 DATA 05 8

1\

I FROM
BUS
RECEIVERS

~~~~~------~----------r--------r----"

~

iTATUS OUT 8

L-.-

~ATA READY

IN 8 , TO INTERRUPT CONTROL

~ 8 DATA OS 8 1I1~~g~vBEuis

'~-A-I-O-T~CO~M~M~AN~D~S--~--­

.ABUS

TO INTERRUPT
CONTROL AND CSR',

BMD 03 - 08
{

B lOT COMMANDS

.A

J

~'

II OATAOS8 II

'TO INTERRUPT
CONTROL AND CSR',

Figure 2

DATA 05 B II

m~

8MD 09 -II

TO CSR'.

",MD03-11

I/l

RECEIVERS

DRS-ED Functional Block Diagram

-...-.I!"-lNU

I

~ '7

DATA/CSR MULTIPLEXER
The DatalCSR multiplexer is controlled by the commands from the lOT decoder to select either 12 bits of data from a DBR or 12 bits of status and
control information from a CSR. When- addressed by the processor or when
an interrupt request is asserted, the selected output of the multiplexer is
transferred to the processor through the bus drivers.
INTERRUPT CONTROL/SKIP LOGIC
The interrupt control logic produces an interrupt request to inform the
processor that information is ready for transfer. The interrupt request signal
is generated by the Data Ready signal when the user's device has data for
transfer. The status of the Skip Flag is sampled by the processor during the
interrupt routine to identify the interrupting device.
..
lOT DECODER
The lOT decoder logic produces eight lOT commands associated with each
device address. Device A or B is s~lected by the decoded output of the device selector, and the function to be performed is determined by the three
Buffered Memory Data bits (BMD) from the bus receivers. The following list
describes the functions available for each 'device.
lOT

o

1
2
3
4
S
6
7

FUNCTION
Conditionally controls the Status Out signal depending on the state of
data bit 05.
Sets the Interrupt Enable flag.
Resets the Interrupt Enable flag.
Transfers the status word to the PDP-8 accumulator.
Conditionally contro,ls the Data Accepted Enable signal depending on
the state of data bit 11.
Clears all flags .(Sets the Data Accepted Enable Flag.)
Transfers the device word to the PDP-8.
.
Tests the status of the DR-8ED Interrupt Request (SKIP lOT).

SWI'(CHABtE DEVICE SELECTION
The DR8-ED. module contains two DIP switch banks used to conveniently
select a device address for each 12-bit word. Six of the seven rocker switches
on each bank provide the capability of selecting a unique address of 00 8 -77 8
by setting the switches to a specified configuration. The remaining switch in
each bank controls the setting of the interrupt request flag associated with
each device. The interrupt request flags are set by either the leading or
trailind edge of the Data Ready signal as determined by the switch position.
INTERFACE SIGNALS
OMNIBUS Signals-The input and output data, status and control signals
conform to OMNIBUS signal specifications described in the PDP-8/E, PDP81M, and PDP-8/F Small Computer Handbook published by Digital Equipment Corporation. The DR8-ED module presents no more than one bus driver
and/or receiver on any OMNIBUS signal line.
DEVICE SIGNALg.....;.Data and Control Signals are transferred between ,devices
and interface by two cables that attach to connectors J1 and J2. The location of the connectors is shown on Figure 3. Table 1 lists the pin assignments
of each connector and signal loading and driving capability.

\
27

OFF ON
-1

DEVICE A

-4

ADDRESS
SWITCHES

/

,

-2
-3
-5

-6
-7

FF ON,
-1

-2
-3

DEVICE B

ADDRESS
SWITCHES

-4
-5

-6

-7

Figure 3

DRS-ED Connector and Sw;tch Locattons

1

'Table I
*J1 and J2
Connector Pin
B
0

F

J
L
N
R
T
Z

68
DO
FF

JJ
LL
NN
RR
V
X
TT

W

Signal Name
STAT 15 H
STAT 14 H
STAT 13 H
STAT 12 H
IN 0 H
IN 1 H
IN 2 H
IN 3 H
IN4H
IN 5 H
IN6 H
IN 7 H
INSH
IN 9H
IN 10 H
IN 11 H
STATUS OUT L
STATUS IN L
DATA ACCEPTED OUT L
DATA READY IN L

TTL Unit Load

}

4 (each)

2 (each)

20 (driving)
5
20 (driving)
5

·Remaining pins on J1 and J2 connect to logic GND on DRS-ED.
28

Four TTL-compatible signal lines connect between the interface module and
each external device and can be used to establish a handshake routine for
efficient control of the data transfers. Two lines from the CSR provide a
Data Accepted handshake signal and a user defined status output bit to the
user's device. A single line to the i~terrupt control logic produces an interrupt request when data is ready for transfer, and a status line to the Data/
CSR multiplexer from the user's device provides user-defined status information for transfer to the OMNIBUS.
CABLE ASSEMBLY TYPE5--Several device cable assemblies are available
from DIGITAL for use with theDR8-ED. Table 2 lists some of the recom- ,
mended cable types and the lengths available.
Table 2

CabJe No.

Connectors

Type

SC07D-XX

H856 to open end

Two 20-conductor
ribbon
Shielded flat

SC08R-XX
SC04Z-XX

,

Recommended Cable Assemblies

, H856 to H856
H856 to open end

Shielded flat

Standard
lengths (ft)
10,15,25
1, 6, 10, 12, 20,
25,50,75,100
6,10,15,25,50

GENERAL SPECIFICATIONS
Input Data .
Two parallel 12-bit data lines from a device
Configuration:'
OMNIBUS Signals:
Operating
Temperature:
Relative Humidity:
Size:

Power:

. Presents a maximum of one bus driver and/or one
bus receiver on an OMNIBUS line.
5°C (41°F) to 50°C (122°F)
10% to 90%, without condensation
Quad height-10.5 in. (26.67 cm); single width0.5 in. (1.27 cm); extended length-8.5 in. (21.59
cm)
+5V +5% at 1.5 A nominal

29

PDP-8/E,8/M
OMNIBUS

. M1703
OMNIBUS INPUT INTERFACE
Length: Extended
Height: Quad
Width: Single

M SERIES

\\

•

CABLE
CO!lNECTOR

BUS

RECEIVER
AND
DEVICE
SELECTION
DECODER

RD DONE L
DEVICE
SEL

BUS RECEIVER

D8

AND

OPERATION
DECODER

~
\

011

CLI
CO

CI

CEI

CHI

CSt

CPI

CAl

INIT

M1703
12-BlT WORD 8/E

BUS INTERFACE

Volts

+5

GND

Power
mA (max.)

555

Pins

AA2, BA2, CA2
AC2, BCI, BC2, CCI, CC2, DCI, DC2-ANI,AN2, BNI, BN2,CNI, CN2, DNI, DN2
ATl, AT2, BTl, BT2, CTl, CT2, OTl, OT2
AFI, AF2, BFI, BF2, CFl, CF2, DFl, DF2

30

8

•
8

~

1

DESCRIPTION
•
The M1703 provides, on a single quad-height moduJe, a complete. selfcontained interface that will input 12 bits of parallel TTL-level data to the
PDP-8/A, 8/F, 8/E or 8/M OMNIBUS, under interrupt or programmed I/O
control. The fy11703 plugs directly into the OMNIBUS connector assembly,
and the external device plugs into a 40-pin flat cable connector on the
module itself. The module includes a device selector, an operation decoder,
'flags, and all control logic needed to request interrupt and respond to programmed I/O commands on the OMNIBUS. Command codes assigned to this

module include:
ENABLE AND DISABfE INTERRUPT
CLEAR FLAGS
SKIP IF DEVICE FLAG SET .
READ DATA
A device selection code of ,14 (octal) is assigned to this module but the
code can be"'changed by moving wire jumpers.
F-UNCTIONS
Device Selection Decoder: The device is addressed through this decoder
when 110 PAUSE is asserted and the octal device code for the decoder is
received through . The decoder output asserts the INT. 1/0 line
and enables the operation decoder.
Operation Decoder: The select bits (MOOg. 10 and 11) determine the type of
operation to be performed when the operation decoder is enabled by the
device selection decoder.
DATA <00:11>: Data from the external device is applied to the bus drivers
on these lines. A READ DATA command enables the' bus drivers and asserts CO and Cl. thereby entering the data into ACO-U via corresponding
OMNIBUS data lines.
READ RQST: When the external device is ready to input stable data, it applies a logic LOW for at least 50 ns on this control line, to set the OtVICE
FLAG. READ DONE goes HIGH within 60 ns after READ RSQT goes LOW.
DEVICE FLAG: After being set by a LOW on the RD ~QST !'ine, Jhis flag
initiates an interrupt request (if INTERRUPT is enabled). This flag is sensed
by the SKIP control line.
INTERRUPT RQST: When this line is asserted by the DEVICE FLAG, an interrupt request is sent to the computer which responds by executing a JMSO
~instruction .
INTERRUPT ENABLE: This flip-flop is set to enable and cleared to disable the
interrupt request function.
SKIP Control Line: If the device flag is set, the instruction SKIP ON DEVICE
FLAG asserts the SKIP line, incrementing the contents of the computer's
program counter.
READ DONE: This line stays HIGH as long as the DEVICE FLAG is set, and
signals the end of a data transfer by going LOW after the end of a RD DATA'
pulse.
ChaRging the Device Code:' The device'selection decoder is preset for a
device code of 14.,Qctal. However, split lugs on this module permit the code
to be changed by the user to any octal number from oe to 77. To obtain the
31

desired octal number, jumper the split lug pairs that select the binary equivalent of the device catte, as shown below: '
10

9

s

7

8

s

11

12

t

2

s s

4

3

s

5

6

I II I II
s s

s s

s

~

S

A. PHYSICAL LAYOUT OF SPLIT LUGS
(SHOWING JUMPERS FOR DEVICE ~ODE 14 OCTAL)

ADD
JUMPER
AT:

DEVICE CODE

8

z2

aO

'

21 2 0 22 2'

tJ

BIT= 1

I

3

5

7

9

BIT=O

2

4

6

8

10 12

11

EXAMPLE
o
2

0
4

1
5

1
7

0
10

0
12

BINARY EQUlv. OF 14 OCTAL CODE
REQUIRED JUMPERS

B. DETERMINING JUMPERS FOR NEW CODE ASSIGNMENTS

lOT INSTRUCTION ASSIGNMENTS
Octal
Code

Instruction

6140

Disable Interrupt

Clears the INTERRUPT ENABLE flag to disable the INT RQST line

6141

Enable tnterrupt

Sets the INTERRUPT ENABLE flag to en~
the INT RQST line

6142

Clear Flags

Clears the DEVICE FLAG, asserts READ DONE
and clears INTERRUPT ENABLE flag

6143

Ski p-if Device
~Iag Set

Asserts the SKIP line if the DEVICE FLAG.is
set. The computer responds by incrementing
the program counter so that the next instruction is skipped.

6144

Read Data

Transfers input data bits <00:11> to
 through the OMNIBUS data
lines. Also clears the DEVICE FLAG, allowing
the RD DON E output to go LOW when the
data transfer is complete.

- Purpose

SPECIFICATIONS
Propagation Time:
FROM
LOW on
RD RQST input

I

ns (max.)

TO

RD DONE
going HIGH

32

60

M1705
OMNIBUS OUTPUT INTERFACE

OMNIBUS
M SERIES
\

Len~h:\Extended

Volts

Height: Quad
Width: Single

+5

GND

Power

mA (max.)

1.1SA

Pins
AA2, BA2, CA2
All pins F, T, N, AC2, BCl,
BC2, CCl, CC2, DCl, DC2

~

~
~

.,~

~a
i

~

"-

"

(

'\

33

(

J21'"

DEFINITI9N
Address Lines. The 18 address lines are used by the master
device to select the slave (a unique memory or device register address) with which it will communicate.
Lines A <17:01> specify a unique 17-bit word and AOO
"ecifies the byte being referenced.
Peripheral devices are normally assigned an address from
within the bus address allocations from 760000-777777
(program addresses, 160000-177777).

i -.:::. All through AOO

46

illclllsiv~.

DEFINITION

0<15:00>

Data Lines. The 16 data lines are used to transfer informa·
tion between bus master and slave.

C <1:0>

Control Lines. These two bus signals are coded by the master device to control the slave in one of four possible data
transfer operations.
Cl

CO

Operation

0
0

0
1
0
1

DATI-Data. in
DATIP-Data In, Pause
DATO-Data Out
DA)"OB-Data Out, Byte

1
1

MSYN

Master Synchronization. A control signal used by the master
to indicate to the slave that address and control information
is present.

- SSYN

Slave SynchronizatiQn. The slave's response to the master
(response to MSYN).
Parity Bit Low (PA) and Parity Bit High (PB). These signalsare for devices on the UNIBUS that use parity checks. PB
is the paritx. line for the high-order byte (on D <15:08»
and PA is the parity line for the low-order byte (D <07:00>).-.-

PA, PB

PA and PB are generated by a slave and received by a master. They indicate
parity error in a device_ The slave negates PA and asserts PB to indicate a
parity error pn a DATI/P; PA and PB both negated indicates no parity error.
PA asserted and PB asserted or negated are conditions reserved for future
use. P~ and PB are not defined in a DATO transactioD. PA and PB may be
used by the bus master's parity error logic.
The following table is a summary of the possible combinations of the parity
error indicators_
PA

o
o
1

PB

0

no error in a slave in DATI/P

1

error in slave in DATI/P
reserved

x

The protocol for PA and PB is the same as that for 0<15:00>.
BR <7:4>

Bus Request Lines. These four bus signals are used by peripheral devices to request control of the bus.

BG <7:4>

Bus Grant Lines. These signals are the processor's response
to a bus request. They are asserted only at the end of instruction execution, and in accordance with the priority determination.

47

SIGNAL

DEFINITION

NPR

Non-Processor Request. This signal is a bus· request from a
peripheral device to the processor, u~ually for a DMA transfer.

NPG

Non-Processor Grant. This signal is the processor's response
to an NPR. It occurs at the end of a bus cycle.

SACK

Selection Acknowledge. SACK is asserted by a bus-requesting
device that has received a bus grant. Bus control pflsses to
this device when the current- bus master completes its operation.

tNTR

Interrupt. This signal is asserted by a peripheral device once
it has become the bus master to start a program interrupt
in the processor.

BBSY

Bus Busy. This signal is asserted bi the master device to
indicate bus is being used.

INIT

Initialization. This signal is asserted by the processor when
power is first applied, when the START key on the console is
depressed, when a. RESET instruction is executed, or when
the power fail sequence occurs. INIT may also be used to
. clear and initialize peripheral devices by means of the RESET
instruction.

AC LO

AC Line Low. This signal starts the power fail trap sequence,
and may also be used in peripheral devices to terminate
operations in preparation for power loss.

DC LO

DC Line Low. This signal remains' cleared as long as a/l dc
voltages are within specified limits. If an out-at-voltage condition occurs, DC LO is asserted by the power supply.

Figure 1.

UNIBUS Connections
48

•

PDp·11 UNIBUS-RELATED INTERFACING MODULES
Table 2 summarizes the interfaces a'nd related modules that are described in
detail on the following pages or in the DIGITAL Direct Sales Catalog where
noted.
Although each interfacing problem is likely to have some unique aspects, the
steps to follow in general are:

1. Determine your interfacing requirements.
2. Match these requirements against the products listed in Table 2, then read
the detailed descriptions.
3. S~lect. suitable products if any are listed. If no listed products meet your
requirements, contact your DIGITAL Field Sales office to find if any other
DIGITAL products can perform the needed functions.
4. Add the power and mounting space requirements of all modules to be employed, and note the cables needed plus and prerequisites and restrictj.9ns
that apply.
5. From the appropriate sections of this Handbook and the Hardwarel Accessories Catalog, select the cables, power supplies, and mounting hardware
to complete your system.
If you need technical assistance with any product in this Handbook, feel free
to call DIGITAL's toll-free Hot line, 8:30AM to 5:00PM Eastern time, 800-2581710. From New Hampshire locations or places outside the United States, call
Merrimack, 603-884-6660.

49

~

T.ble 2

DEVICE OR FUNCTION

(J1

0

MODULE
OR
OPTION

Interf.ce Selector

LOGIC
H'BOOK
PAGE'

Gu~·l1

POWER
MODULE
BUS
SIZE
+5Y
AMPS' LOADS L H W'

UNIBUS

CABLE
REQ'D

FITS
SPC
SLOn

COMMENTS

EIA RS232C serial devices, e.I.:
lA35 printer
LA36 printer terminal
LAl80 printar
LSl20 printer terminal
VT52 CRT terminal
VT55 CRT tarminal

M7800

1.8

E Q S

BC05C·25

yes

Also requires -15V@.15A. +15V@!016A.
One of four standard crys~als must be
specified at time of order. For complete
option, s. . OLll-WB.

20 mA current loop serial
devices, e.I.:
LA3S printer
LA36 printer terminal
LAI80 printer
VT50 CRT terminal
'VTS2 CRT terminal
VTS5 CRT terminal

M7800

1.8

E Q S

10·8360

yes

Also requires -15V@.lSA. +lSY@.016A.
One of four standard crystals must ba
. specified at time of order. For complete
option, s.. DLU·WA.

General 20 mA serial asynchronous
I/O interface

Dlll·WA

2.0

E Q S

70·8360-1
supplied

yes

Also requires -ISV@.15A, +ISV@.05A.
Crystal must be specified at time of order.

General EIA RS232C serial
asynchronous I/O interface

Dlll·WB

2~0

E Q S

BCOSC·25
supplied

yes

Also requires -ISV@.15A, +ISV@.OSA.
Crystal must be specified at time of order.

AID or D/A interface, 16-channel

ARll

5 max

E H S

BClll·20

yes

May not be pluued into a modified
UNIBUS slot.

2·word parallel input interface

DRll-L

1.5

EQS

yes

Possible cables: BC07A. ·70, ·8R, or -4Z.

2-word parallel output Interface

DRll·M

1.5

E Q S

yes

l·word parallel input/output
. interface

M7860

1.5

E Q S

yes

1.6

I.

Instrument remote-c:ontrol interface

M1623

E Q S \

.~eclal

Instrument deta input interface

M1621

.77

E Q S

special

I6-blt relay output Interface

Ml801

1.16

E Q S

Direct Memory Access (DMA)
interface

ORll·B

3.3

sys. unit

OMA interface OECklt

KlTll·O

3.3

sys. unit

.,,--

Table 2

DEVICE OR fUNCTION

MODULE
OR
OPTION

Interface Selector Gulcl&-PDP-U UNIBUS (Cont.)
LOGIC
H'IIOOK
PAGE'

POWER
MODULE
SIZE
BUS
+5Y
AMPS' LOADS L H W'

CABLE
REO'D

fiTS
SPC
SLOn

COMMENTS

yes

H.as space for approx. 25 user IC.

UNIBlIS' INTERFACE BUILDING
BLOCKS;

U'I
t-O

~ I

BC07A or
BC08R

Intartace foundation module

MI710

.79+

Address selector module

MI05

.338

E S S

yes

Bldl,..:tlonal bus interlaclnl lata
modul.

M1500

.300

E S S

no
no

E Q S

But Input intertBcinl driver module

M1501

.300

E S S

Bus output interlaclnl driver module

M1502

.750

ED S

Bus Request (BR)/Direct Memory
Access (oMII) interrupt control
module

M7821

.725

E S S

oMA word count/bus address
module

M795

.600

E05
E S 5

Master control module

M796

.180

Bus driver module

M783

.070

E 5 5

Bus drlvar module, non·invertlnl

M798

.320

S 5 5

Bus recelv'r module

M784

.200

E S 5

Bus transceiver module

M785

.600

E S 5

Kit of ten oEC8640 bus receiver IC.

956

Kit of ten oEC8881 bus ,driver IC.

957

Wire·wrappable modules:
Hex·hellhl, no IC sockets
Hex·hei.hI, 84 16·pln IC sockets
Qued-hellht, no IC sockets
Quad·heilhl, 54 16-pin IC
sockets
Oouble-helBht, no IC sockets
oouble-heIBht. 24 16-pin IC
sockets

H
H
Q
Q

Not recommended' for n_ desll"s.

yes

no

'W9500
W9503
W9501
W9504

E
E
E
E

S
S
5
5

yes
yes
yes
yes

W9502
W9505

E05
ED S

yes
yes

NOTtS.
1. + meens current required by user 10I1c muat be added to filur. shown.
2. Module sizes .ere liven as Lenllh, Hellht. and WIdth, as defined In Gene,., Information.
3. OSC
Direct· 5al.. Cat.,OI.

=

,
/'

52

DRII-L
2-WORD

UNIBUS
M SERIES

INPUT INTERFACE OPTION·
Length: Extended
Height: Quad
Width: Single
J

~

16 BIT WORD

V'

DEVICE A
STATUS/CONTROL

16 BIT WORD
DEVICE B

~

DRll-L
INPUT
INTERFACE

~
~

\

ADDRESS

16 BIT DATA
.

~

vl3

I\.

VECTOR ADDRESS)

-V

~

5

CONTROL

STATUS/CONTROL

-.

Figure 1

DRll-L Interface

DESCRIPTION
,
The DRII-L is a complete, self-contained input interface used to transfer
two independent 16-bit, parallel data words from a user's pe'ripheral device
to the PDP-ll computer system as shown on Figure 1.
It is directly compatible with the PDP-ll UNIBUS and is designed for installation into anyone of the available Small Peripheral Controller slots (SPC)
of a BBU-M, DOll-A, or DDll-B System Interfacing Unit and the PDP-ll
processor unit.
The DRll-L consists of address selection logic, interrupt control and priority
level select logic, two Data Buffer Registers (DBRs), one for each word, and
two 'independent Control/Status Registers (CSRs). One' CSR is assigned to
each input data word and provides status and control information during a
word transferTwo control and two status lines between the user's device and the interface permit the establishment of a handshake routine to efficiently control
the data transfers.
The input signal lines are TTL-compatible with high threshold receiver inputs
and built-in hysteresis for both high and low threshold, providing substantial
noise immunity. Input data lines are diode-clamped to +5 V and ground.
Control lines from the user's device are diode-clamped to ground and pulled
up to +5 V by a resistor.
A" address selection, interrupt priority selection, and vector address selection is performed using Dual Inline Package (DIP) switches mounted on the

53

module. These switches facilitate the installation of the module by eliminating
the need for soldering or rem~ving jump~r leads for address and vector selec·
tion.
The DRll·L is designed for user applications and requires a minimum of
external hardware to implement into the PDP·ll system. Two 40'pin con·
nectors are conveniently mounted near the edge of the board. These con·
nectors permit either4' one or two external devices to be easily connected
using BC08R or BC07D flat cables available from DIGITAL. These cables have
the mating connectors premounted"and are supplied in any specified len.gth.
The interface module occupies one SPC slot and is a quad·height, extended·
length, single-widthrnodule.
FUNCTIONS
"
DRll·L ELEMENTS AND SIGNAL FLOW
The main elements of the DRll-L interface module and the data, control,
and status signal' flow are shown on Figure 3. The module provides the com·
plete interface logic necessary to allow the efficient transfer of data from
user's device to the UNIBUS.
"\
CONTROL/STATUS REGISTERS
Each CSR is a I6-bit register used to supply control and status information
to the user's device and to provid!,,,control and status indicators of the user's
device and interface to the processor. Each CSR is byte- orword·addressable.DATA BUFFER REGISTER
Each DBR is used to store 16 bits of data from a device. The contents of
the DBR are transferred to the processor under program control as a I6·bit
data word or 8-bit byte. When addressed by the processor or when an in·
terrupt request is asserted, the device data is latched into the DBR. Input
data is not required to be held by the device for the entire transfer opera·
tion, thereby permitting faster data transfers.
DATA/CSR MULTIPLEXER
The multiplexer is controlled by the decoded device address and selects
either 16 bits of data from a DBR or 16 bits of st~tus and control information from a CSR for transfer to the UNIBUS. The selected output of the
multiplexer is transferred to the processor under program control through
the UN ISUS transceivers.
ADDRESS SELECTION LOGIC
The address selection logic decodes the addresses associated with each
CSR and DBR and speCifies the direction of data transfer.
INTERRUPT CONTROL LOGIC
The interupt control logic requests bus mastership on one of the four bus
request lines of the UNleUS, produces the interrupt request, and specifies
the vector addresses of the interrupt routine pointers located in memory.

54

FROM TRANSCEIVERS

STAT~S

Iii'

DATA

.,c

....

L

~

"
lTA I N A ' "
c..BlIS.

LOW BYTE)

"-

(HIGH BYTE)

}I--------

---v

lOW BYTE)

__

0"

__ __

s~~~

(')
~

CSR CONTROL BITS

-

B

~~~!~~

(HIGH BYTE)

...DATA READY 1:N B

(LOW BYTE)

l""L-A-TC-H-B--i

~~

~ECEIV~
"'1F.fK'......
!' (A_rJl
.....
-B,..,', ~~ HIGH8\'
16 BITS
,.I.~ ---B

l

E (LOW BYTE1

j

.

U

I

...
)

16 BITS

V

B.l

"2

_ /

....

V
f-)
"- 1-----16 BITS

U I

W ...-J'\
r-vl

(HIGH BYTE)
-------

_
U
N

1/1.
f\.

I'\..
D <)5,00) )

~

IV

f-- (LOW BYTE)
E ~EC1

6

i ROST •

.

TO

INTE~UP\:~~L 1
L06n

4

ENABLE

...-L-'--- A

K

A

(HIGH8YTE)~
16 BITS

:~~E~~

------(L,.OW BYTE)

TRANSCEIVERS

(LOW BYTEl

~

~LL

LATcH B

r
- TO CSR Aa B
g~=TROL
TS

MUX
HIGH BYTE

CSR STATUS) 4

DB'R""I

.....

.

1
~RB

DATA ACCEPTED OUT B

0

I I\.
~)
0

--------v
~ ~

rv/

CONTROL

t-=='-"'FROM ADDRESS SELECTOR
LOAD 0

16 BITS
FROM TRANSCEIVERS
STATUS OUT 8

m

3

DI

16 )"ITS

_

!.

~

~

hl
n

on

CONTROL

,FROM CSR B --,R"",Q"",S,-,-T-...=B-w

_ ....._~

:::J

OQ

Lfr~~ A

I

_

:::J

INTERRUPT Itt UXI '

UL~ArrTBCH[AA~-~--~

~ ~tHlGHv
RECE~VERS
--yI' r--';:-~

,

c

iii'

r----L--.--J

Ito

~

fsR STATUS

(LOW BYTE)

."
(')

i.
RQST A

(HIGH BYTE)

A

;0

....
O·

ACC£PT~n OUT A

USER'S
DEVICE

0

U1
tit

1

CSR A

DATA READY IN A

CD

to;"'
r

..

OUT A
STATUS IN A

."

I\)

CSR CONTROL BITS

TO CSR A

LOAD 0 ' .

<17, 00)

-.....

CONTROL

~~

Page 56 does not exist in original

Page 57 does not exist in original

Page 58 does not exist in original

Page 59 does not exist in original

SWITCH PROGRAMMMABlE FUNCTIONS
The DRll-L module contains two DIP switch ,banks used to conveniently
select the device address, the vector address, and the priority level of the
interrupt requests.
Vector Address- The vector address of the interrupt routine pointer located
SwitChes
in memory is selected by six of the switches, allowing vectors up to 7748 to be specified.
Priority LevelSwitches

Two switches are provided to select one of the four Bus
Request pr-iority level$ (BR4 through BR7) .of the UNIBUS.

Device Address-The address· of the device is assigned with ten switches,
Switches
allowing the module address to be rocated within the upper
4K address block dedicated to peripherals and user's devices.

M7864
J2

J1

PRIORITY LEVEL
AND INTERRUPT
VECTOR ADDRESS
SELECTION SWITCHES

012345678

DEVICE ADDRESS
SELEOION SWITCHES

?II r 1tl f;l
F

2 ,1
\

'

2 3 4 5 6 7 8 9 10

~I"I""II
F

',.

Figure 3

DRII-L Connector and Switch Locations

INTERFACE SIGNALS
UNIBUS Signals-The input and output data, control, and status signals
conform to the UNIBUS signal specificationsoutltned in the PDP-ll Peripherals Handbook published by Digital Equipment Corporation. The DRll-L
module presents no more than one unit load on any UNIBUS signal line.

60

-

\.

..

'.

..

,

DEVICE SIGNALS-Data and control signals are transferred between the devices and interface by two. cables that attach to connecto'rs Jl and J2. The
location of the connectors on the module is shown on Figure 3. Table 1 lists
the pin assignments of each connector and the signal drive or loading specification.
Table 1
Device Connector Signals

• Jl and J2
Connector
Pin

B

o
F

J

L
N
R
T
V
X
Z

BB
DO

FF
JJ

LL
NN
RR
TT
VV

Signal Name
DATA IN 15 H
DATA IN 14 H
DATA IN 13 H
, DATA IN 12 H
. DATA IN 11 H
I DATA IN 10 H
DATA IN 09 H
DATA IN 08 H
STATUS OUT L
STATUS IN"DATA IN 07 H
DATA IN 06 H
DATA IN 05 H
DATA IN 04 H
DATA IN 03 H
DATA IN 02 H
DATA IN 01 H
DATA IN 00 H
. DATA ACCEPTED OUT B L
DA'TA READY IN B L

TTL
Unit Load

2 (each)

35 (driving)

-5

2 (each)

• 35 (driving)
5

• Remaining pins of Jl and J2 connect to Ipgic GND on DR11-L.
Four lines provide TTL-compatible signals between each CSR an dthe external
device and can be used to establish a handshake routine for positive-control
data transfers. Two lines can be used for status information to and from
the processor, and two lines provide controlling information for data transfers utilizing p'rogram interrupts.- The 8-bit byte or 16-bit data word from the
device to the interface is supplied by the 16 Data In lines.
CABLE ASSEMBLIES-Several cable assemblies are available from DIGITAL
for use with the DR11-L module. Table 2 lists some of the recommended
cable types and standard lengths available.

61

..----

Table 2

Cable No.

Connectors*

Type

BC07A XX
BC07D-XX
BC08R-XX

H856 to open end
H856 to open end
H856 to H856

20-twisted pair
2, 20 conductor ribbon
Shielded flat

BC04Z-XX

H856 to open end

Shielded flat

Standard
Lengths (ft.)
10,15,25
10,15,25
1, 6, 10, 12, 20,
25,50, 75, 100
6,10,15,25,50

* The H856 connects directly to the DRll-L
GENERAL SPECIFICATIONS '"
Input Data
Two parallel 16-bit data lines from a device.
Configuration

UNIBUS Signals
Operating Temperature
Relative Humidity
Size

Presents a maximum of one unit load on a
UNIBUS line.
5°C (41°F) to 50°C (122°F)
10% to 90%, without condensation
Quad height-10.5 in. (26.67 em); single width0.5 in. (1.27 em); extended length-8.5 in.
(21.59 em)

Power

+5 V ±5% at 1.5 A nominal

DRll-L

62

DRII-M
2-WORD

UNIBUS

OUTPUT INTERFACE OPTION

M SERIES

Length: Extended'
Height: Quad
Width: Single

~

,

-

~TERRUPT CONTROL

16 BIT DATA

""

<:

16 BIT DATA

)

ADDRESS

-V

~

)v

DEVICE A

STATUS/CONTROl
DR11-M
OUTPUT
INTERFACE
OPTION

16 BIT DATA

)

DEVICE 8

STATUS/CONTROl

Figure 1

DRll-M Interface

DESCRIPTION
The DRll-M is a complete, self-contained output interface used to transfer
two independent 16-bit, parallel data words from the PDP-II computer system to a user's peripheral device. It is directly compatible with the PDP-ll
UNIBUS and is designed for installation into one of the available Small Peripheral Controller slots (SPCs) of a BBll-M, DOll-A, DDll-B System Interfacing
Unit or into the PDP-ll processor unit.
The DRll-M consists of address selection logiC, interrupt control and priority
level select logic, two Data Buffer Registers (DBRs), one for each word, and
two independent Control/Status Registers (CSRs).
Each register is word or byte addressable, and the register contents can be
read back into the processor under program control, allowing the-full range
of PDP-11 instructions to be used. Two control an-a two status lines between
the user's device and the interface permit the establishment of a handshake
routine to efficiently control the transfer of data.
Data, status, and control signals from the interface to the user's device are
supplied from open collector output drivers capable of sinking 32 rnA of load
current. Each output is connected to +5 V through a pull-up resistor. This
feature allows a variety of user devices to be directly connected to the
interface withou! the need of external line drivers and discrete components.
All address selection, interrupt priority selection, and vector address selection
is l1erformed using Dual In· line Package (DIP) switches mounted on the
module. These switches facilitate the installation of the module by eliminating

63

the need for priority plugs and soldering or removing jumper leads for ad·
dress and vector selection. .
The DRll·M is designed for user applications and requires a minimum of
external hardware to implement into the PDP 11 system. Two 40·pin con·
nectors are conveniently mounted near the edge of the board. These connec·
tors permit either one or two external devices to be easily connected using
BC08R or BC04Z flat cables available from DIGITAL. These cables have the
mating connectors premounted and are supplied in any specified length.
The interface module occupies one SPC slot and is a quaJ.height, extended·
length, single·width module.
FUNCTIONS
DRll·M ELEMENTS AND SIGNAL FLOW
The main elements of the DRll-M interface module and the data, control, and
status signal flow are shown on Figure 2. The module provides the complete interface logic necessary to allow the efficient transfer of data from the
UNIBUS to a user's device.
CONTROL/STATUS REGISTERS
Each CSR is a I6-bit register used to supply control and status information
to the user's device and to provide control and status indicators of the user's
device and interface to the processor. Each CSR is byte· or word·addressable.
DATA BUFFER REGISTERS
Each DBR is used to store 16 bits of data for transfer to the device. The
DBR is a read/write register allowing the full range of PDP-II instructions
to be used.
DATA/CSR MULTIPLEXER
The multiplexer is controlled by the decoded device address and selects
either 16 bits of data from a DBR or 16 bits of status and control information from a CSR for transfer to the UNIBUS .. The selected output of the
multiplexer is transferred to the processor under program control through
the UNIBUS transceivers.
ADDRESS SELECTION LOGIC
The address selection logiC decodes the addresses associated with each CSR
and DBR and specifies the direction of data transfer.
INTERRUPT CONTROL LOGIC
The interrupt control logic requests bus mastership on one of the four bus
request lines of the UNIBUS, produces the interrupt request, and specifies
the vector addresses of the interrupt routine pOinters located in memory.

64

-

I'
RQST A

AI
( 0 < 08' 02

'"

.."

o"Q"
t::

>

....

~ --------

INTERRUPT
CONTROL

ICONTROL

ROST B

~

I\)

...

", ,'

DATA ACCEPTED IN A
DATA READY aliT A

(LOW BYTE)

.~
LOAD 0 ADDRESS

I

h

16 BITS (CSR CONTROL BITS OR DBR BITS)

....
....

o

3:

U

MUX

~
B

.."
t::

U
S.A

::J

.....
(")

K

0"

::J

...
0<15 DO) )

!..

Y

HIGH BYTE)-

~

TRANS _
CElilERS

,Al-

'-r-.I'---

K

(LOW BYTE

.A

16 BITS

•

- - - - - I-

"I

"

0"
(")
ENABLE

I

£ii"

61"l--

V-

SELECT

_

OJ

3

....
A < 17·00) )

LOAD 0
LOAD 2

V

ADDRESS
SELECTOR
CONTROL

,

;,

_

TO CSR

ADDRESS
SELECTOR

r

~

CSR STATUS

_

CSR B

-

r--

TO
INTERRUPT

RQST B

(HIGH BYTE)

CONTROL

-------

STATUS IN e
STATUS OUTB

(LOW 8YTE)

T'

_

L--..V

LOAD 4
LOAD 6

V

(LOW BYTE)

.

DATA ACCEPTED IN 8
DATA READY OUT B

~~~~~~

~

A

TO DBR A

, !V'

'"

IPl~~,,9.PH )

~'~
'LOAD 2 FROM
-

LOW BYTE),.-

OQ

(LOW BYTE)

A DRIVERS
....
(HIGH BYTE)
16 BITS) - - - - - - - -

'

V'

4~

I]J
;1{:"

16 BITS

DBR A
(HIGH BYTE)
--------

2 '-

(HIGH BYTE)
-------

c

r--vI

I

DEVICE
A

SELECTOR'

C

0\

I

STATUS OUT A

' '. '"· uc ' '.
CSR STATUS

:::0

U'I

STATUS IN A
CSR A
(HIGH BYTE)

16 BITS

B
OBR B
(HIGH BYTE)
-------(LOW BYTE)

16 BITS

B DRIVERS
.... (HIGH BYTE)
)
------

V

(LOW BYTE)

-

I...

r '----

IS:AT~.?.¥,e

')

SWITCH PROGRAMMABLE FUNCTIONS
The DfH I·M module contains two DIP switch banks used to conveniently
select the device address, the vector address, and the priority level of the
interrupt requests.

Vector Address
SwitchesPriority Level
SwitchesDevice Address
Switches-

The vector address of the interrupt routine pointer 10·
cated in memory is selected by six of the DIP switches,
allowing vectors of up to 7748 to be specified.
Two switches are provided to select one of the four Bus
Request priority levels (BR4 through BR7) of the
UNIBUS.
'
The address of the device is assigned with ten switches,
allowing the module address to be located within the
upper 4K address block dedicated to _peripherals_ and
user's devices.

M786S

PRIORITY LEVEL
AND INTERRUPT
VECTOR ADDRESS
SELECTION SWITCHES

Jl

DeVICE ADDRESS
SELECTION SWITCHES

J2,.

212345678

~I"I""
F

N12345678910

~II"""II
F

Figure 3

DRll·M Coonectors and Switch Locations.

INTERFACE SIGNALS
UNIBUS SIGNALS--The input and output data, control, and status signals con·
. form to the UNIBUS signal specifications outlined in the PDP·l1 Peripherals
Handbook published by Digital Equipment _Corporation. The DRll"M module
presents no more than one unit load on any UNIBUS signal line.

66

DEVICE SIGNALS-Data and control signals are transferred' between the devices and interface by two cables that attach to connectors J1 and J2. Theloca·
tion of the' connectors on the module is shown on Figure 3. Table 1 lists the
pin assignments of each connector and the signal drive or loading capability.
Table 1
Device Connector Signals

• Jl and J2

,/

Connector
Pin

Signal Name

B

DATA OUT 1:> H
H
DATA OUT
DATA OUT 13 H
DATA OUT 12 H
DATA OUT 11 H
DATA OUT 10 H
DATA OUT 09 H
DATA OUT 08 H
STATUS IN L
STATUS OUT L
DATA OUT 07 H
DATA OUT 06 H
DATA.DUT 05 H
DATA OUT 04 H
DATA OUT 03 H
DATA OUT 02 H
DATA OUT01 H
DATA OUT 00 H
DATA ACCEPTED IN L
DATA READY OUT L

o
F

J
L

N
R
T
V

X
Z

BB
DD
FF

. JJ
LL

NN
RR
TT

VV
*Rem~ning

TTL
Unit Load

l'

20 (each)

5
20

20 (each)

5
20

pins on J1 and J2 connect to logic GND on DR11·M.

Four lines provide TTL-compatible signals between each CSR and the external device and can be used to establish a handshake routine for positivecontrol data transfers. Twp lines can be used for status information... to
and from the processor, and two lines provide contrOlling information for
data transfer utilizing program interrupts. The 8-bit byte or 16-bit data word
. from· the interface tQ the device is supplied by the 16 Data Out lines.
CABLE ASSEMBLlES--Several cable assemblies are available from DIGITAL for
use with the DRll-module. Table 2 lists some of the recommended cable
types and lengths available.
Table 2
Recommended Cable Assemblies
Cable No.

Connectors·

Type

Standard Lengths (ft.)

BC07A-XX
BC07D-XX

H856 to open end
H856 to open. end

10,15,25
10,15,25

BC08R-XX

tJ856 to H856

20·twisted pair
2, 20 conductor
ribbon
Shielded flat

BC04Z-XX

H856 to open end

Shielded flat

*The H856 connects directly to the DR11-M.
67

1, 6, 10, 12, 20,
25, 50, 75, 100
6,10,15,25,50

GENERAL SPECIFICATIONS

Output Data
Configuration

Two parallel 16-bit data lines to a device providing
TTL-compatible levels.
., . ;

UNIBUS Signals

Presents a maxrmum of one unit load on a UNIBUS
line.
.

Operating Temperature

5°C(41°F) to 50°C(122°F)

Relative Humidity

10% to 90%. ,without condensation
Quad h~ight-l0.5 in. (26.67 em); single width0.5 in. (1.27 em); extended length--8.5 in.-(21.59
cm)
.

Size
/'

Power

!

-

{

+5V±5% at 1.5 A ~ominal

DRll-M

68

PDP-II

MIOS·

I.

ADDRESS SELECTOR

UN.IBUS
M SERIES

Length: Extended
Height: Single
Width: Single
SSYN INHIBIT
BUS MSYN

BUS SSYN-:-L

J1 B

TEST POINT

L25

SELECT 0 H

S2

SELECT 2 H

T2

SELECT 4 H

R2

SELECT6 H

S1

BUS

au

12

0

'0

to

§0

11

10

(f)
(f)

9
8
7
6
5
4
3

au
a:

tO

0
0

 as follows: A <17:13>
defines the section of the address map that is assigned to peripheral devices
and must all be asserted. A <12.03> are determined by jumpers on the
card.

69

~

When the jumper is "in"ihe selector will look for a zero in the binary equivalent of the register address on that address line. A02 and AOI are decoded
to provide one of the four SELECT outputs. AOO is for byte control.
Signals for gating control are determined by d'ecoding AOO, CI, and CO. The
signals obtained are: IN, OUT LOW, and OUT HIGH.
Instruction*
DATI or DATIP
DATa
DATOB with AOO
- DATOB with AOO

Corresponding MI05 Output
IN
OUT HIGH and OUT LOW
OUT LOW
OUl;" HIGH

=0

=1

·DATI, DATa, DATOB, DATIP are not PDP-ll instructions. They are names gWen to'the
various C-line combinations which are automatically configured by the processor for
each instruction.
'

IN is used to gate data from a device register onto the bus. OUT LOW is
used to gate 0 <07:00> from the bus into the low byte of a device register.
OUT HIGH is used to gate 0 <15:08> into tb.e...high byte of a device register.
With respect to the bus master, the MI05 is actually the "slave" in the relationship when a data transfer occurs on the UNIBUS.
SSYN is asserted whenever it sees its address being referenced and MSYN
is asserted. SSYN is negated when MSYN is negated. There is an approximate
100 nsec delay between receiving MSYN and the assertion of SSYN to allow
for decoding. Additional capacitance carr be added to the delay circuit to increase this time, if desired. A practical maximum is a 1000 pf ca~acitor
which will produce approximately 400 nsec of delay. If a longer delay is
needed, the SSYN INHIBIT line can be grounded, which will prevent SSYN
from being issued at all from the MI05. The SSYN signal would then be
generated from another source after the desired delay. SSYN INHIBIT can
be left open when not used.
EXT GND is used for testing purposes and should be tied to ground in
normal operation.

•

70

UNIBUS

M783
UNIBUS DRIVERS

M SERIES

Length: Extended
Height: Single
Width: Single

:
:
:
~V2
:

1 Bl

~J1

.~

~L2

~
~
~

1 J2

/

1 Nl

~S1

1 R2

1 VI

-

~ =CONNECTS TO UNIBUS

..

0= BUS DRIVERS

Volts

+5
GND

Power

mA ---------+-_

M1!1OI.

BUS INPUT INrERflilCE

Volts

+5
GND

Power
mA (max.)

300

Pins
A2

C2. T1

84

VI

"

The M1501 contains 16 bus driver$'for interfacing parallel input data to the
PDP-II UNIBUS. The module incluct~S)wo control flags that can be used for
interrupt request and enable. Data-"inputs from an external device enter a
40-pin flat cable connector mounted on the module itself. All inputs are
diode-clamp~d to ground and +5 volts.
APPLICATIONS
_
Up to four MI50I modules (64 bits) can be controlled by one MI05 Address
Setector module, one M7821 Interrupt Control module, and one M1500 Bus
Gates module.
FUNCTIONS
Input from Cable: Data is gated from the input connector to the bus when
both enabling inputs (K2, J2) are HIGH.

Send/Receive Control Signal: Two additional lines are provided from the
cable connector (Pins X and Z) to the module to allow communications between the device and the computer.
\..~

Flags: A request flag (RQ) and a request enable flag (RQE) are included on
the M1501. Both flags can be cleared on start-up directly from the PDP-ll
INITIALIZE bus line through pin. Fl. Both flag clock inputs are transition sensitive. The data input to each flag is buffered by a bus receiver; thus, status
data can be entered directly from a bus line if desired. -The request enable
flag clock input responds to a HIGH going transition. The request flag has
an input that is sensitive to a LOW going transition and an input that is sensitive to a HIGH going transition. (Whichever input is not used should be
connected to the proper logic level to unassert it.) The user is given the
maximum degree of freedom to use the request enable flag as a 0 flop or as
an RS flop because all inputs are accessible.
The output of each flag is fully buffered (not shown in diagram) to protect
the flag data as well as to provide high output drive.
SPECIFICATlONS
Propagation Time:
ns (max.)

FROM

TO

40-Pin Connector
Inputs

Bus Data Outputs

50

Flag Clock Inputs

Flag Outputs

75

85

M1502
BUS OUTPUT INTERFACE
Length: Extended
He'ig,ht: Double

Width: . Single

UNIBUS
~ SERIES

Power
Volts

+5
GND

mA (max.)

750

Pins
A2

C2, T1

The M1502 is a versatile buffered output interface for up to 16 data bits,
arranged in two 8-bit bytes. The module accepts data from the UNIBUS Data
lines and stores it in a 16-bit register. Outputs are supplied both to a 40-pin
flat ribbon connector and to the backplane. Open-collector output drivers
with pull-up resistors are 1'ncluded on the module. Three flip-flops with type
, D as well as type RS inputs are provided as flags or synchronizing devices.
APPLICATIONS
Although intended for parallel data output this module may be used to drive
indicators or small-relays provided the voltage and current limits are not'
exceeded.

Up to four MI502 modules (64 bits) can be controlled by one MI05 Address
Selector module, one M7821 Interrupt Control module, and one M 1500 Bus
Gates module.
FUNCTIONS
Input from Bus: Data is loaded from the bus to the storage register on a
positive transition of the loading inputs (AB1 and AA1), which load~ the
upper and lower bytes respectively providing the enabling input (AMI) is
high.
.

Flags: Three edge-triggered flip-flops are provided. Two of the flags may be
triggered by either negative or positive transitions; these supply buffered
drive to 40-pin connector outputs. The third flag is triggered by positive-going
transitions only. This flag provides an output to the blackplane only.
All flags have separate reset inputs and may also be cleared by a common
reset line. The set and reset functions occur on logic HIGH levels. Unused
inputs should be connected to a logic level that will unassert them. Spare bus
drivers are also provided.
Spare Lines: Two additional lines are provided between the cable connector
- and the module for additional communication bstween the module and the
external device. These lines are diode protected against voltage over shoot
below -0.75 volts or above +5.75 volts.
SPECIFICATIONS

Propagation Time:
TO

FROM

ns (max.)

BUS DATA Input

40-Pin Output

100

FLAG CLOCK Input

40-Pin Output

150

FLAG SET or CLEAR Input

Backplane Output

100

86

'

~I~

g
J--r---+---L--~ ffi

~I--~II--'/

~

III

a

I

V

I

I
I

1
I

I'

ANI

ALt

AR2

AU

B

p-______________~~=v~t B
2 AT2

tAUt
M1!102
BUS OUTPUT INTERFACE

87

"output

Drive: Oututs to the 40-pin connector are supplied by open-collector
high-voltage drivers. Resistors (l~ ohm) included on the module provide
pull-up or current sinking for up to 20 TTL unit loads. If the supplied resistors
are removed, the output stages will sink up to 40 mA at logic LOW and will
withstand a HIGH level of up to +30 volts. These outputs may therefore be
used to drive many types of indicators and even relays. However, if inductive loads are driven, diodes should be wired across each load to bypass
inductive kickback.

c

··1

88

::EJ:r-'CD
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DESCRIPTION
The Ml710 UNIBUS@ Interface_Foundation Module is a general-purpose board
that provides for the construction of custom interface designs using integrated circuits (lCs). The MI7IO lets users build their own interfaces between a wide variety of peripheral equipment and any PDP-ll processor. All
, essential UNIBUS logic, such as device address selection, interrupt circuitry,
and bus receivers and drivers, is provided on the lower portion of the module.
The remainder of the board contains IC mounting pads with wire-wrappable
pins for custom logic designs. These pads accommodate combinations of all
common type of DIP (dual-in-line-package) integrated circuits with up to 40
pins.
The Ml710 is a versatile module, ideal for any type of application. The end
user, such as a universit{ laboratory familiar with ICs, will appreciate both the
capabilities and cost-effectiveness of the module; noadditio~al mounting
panel or power supply is required. These features, coupled with the fact that
the MI710 is capable of automatic wir'e wrapping, also should prove valuable
to the 'Original Equipment Manufacturer (OEM) who requires many custom
interfaces. And, in all cases, the module is easily adaptable to accommodate
any changes in interface design.
The M1710 plugs into any Small PeripheratController (SPC) slot of a DECkit11-M Instrument Interface or 0011 Peripheral Mounting Panel. Additionally, it may be used in a system unit such as the BBll-A. Connection to user
equipment is made via a cable connector mounted on the M1710 module.

FEATURES
, • "Do-it-yourself" interfacing.
•
•
•
•
•
•
•
•
•

•
•

Complete single-card interface. _
Plugs directly into Small Peripheral Controller (SPC) slot.
Can be used with DECkit11-M Instrument Interface Kit.
Saves hardware and building costs.
Preassembled/pretested UNIBUS circuitry eliminates need to build the required bus interfacing functions.
Wire-wrappable interconnections-compact, 30-gauge· wiring used for all
IC lead interconnections.
I/O connection directly to module board-standard 40-conductor cables
available.
All accessories and tools available.
Accepts, all common Dual-in-line Packages (DIPs); mounts up to 16 of the
14- or 16-pin type plus a mUlti-use pad set that mounts two 40-pin types,
three 24-pin types, four 14- or 16-pin types, or combinations of the~e:
-Additional bus driver and bus receiver, ICs available--special high-impedance devices: DEC 8881, DEC 8640.
Includes source of +3 V--convenient for tying unused TTL inputs high, etc.

91

APPLICATIONS
Since more and more devices are becoming available in DIP form, quite complex systems can be built?n the M1710. Some typical applications include~
• Multiword input and/or output.
• Programmable instrument interfaces.
• Interprocessor buffers.
• Custom peripheral controllerS.'

/

• I nteriaci ng of:
Microprocessors
A/D converters
Multiplexers
Counters
Shift registers
ROM and RAM memories
Arithmetic logic units
Programmable logic arrays (PLA)

FUNCTIONSThe MI710 can b,edivided into four functional sections: address selector,/
logic, bus request .6gic, data bus interface, and miscellaneous logic.
Address Selector "logic
The address selector logic provides gating signals for up to 16 full 16·bit
device registers; Addresses which can be chosen by the user range from
760000 8 to 777777 8 • The basic M17IO address selection is similar in function to the MI05 Address Selector Module. The input signals for the address
selector logic consist of: 18 address lines BUS A; two bus control
lines, BUS C; and a master synchronization lines, BUS MSYN. The address selector decodes the 18-bit address on lines BUS A; receives
MSYN and issues SSYN.
Bus Request logic
The MI710 contains the circuitrY requ-jred to make a bus request and gain
control of the bus at either the NPR level or at one of the BR levels. The
module also includes circuitry required for transferring a vector address during an interrupt operation.
Data Bus. Interface
The MI710 contains standard UNIBUS receivers which provide a buffered bus
signal output for each of the 16 data lines OUT 00 H through OUT 15 H.
Output drive capability of these receivers is seven TTL unit load,S.
The module also includes 16 bus drivers which drive data lines IN 00 H
through IN 15 H. Input loading to each driver is one standard TTL load. All
16 drivers have two common gate line enables (DRIVER ENABLE I and
DRIVER ENABLE 2) which require a logic Low for assertion. Each enable rep,resents four TIL unit loads.
Miscellaneous logic
",
The following additional circuitry is also provided on the. MI710:
• Inverted and noninverted buffered initialize outputs (pins 58 and 59) capable of driving 28 and 30 TTL unit loads respectively.
• A general-purpose flip-flop with all input and output pins available for wire
wrap (pins 51 through 57).
'
• A +3-volt sourc~ (in 50) capable of drivin~ 30 TTL unit loads.
92

UNIBUS

M1801
16-BIT RELAY
OUTPUT INTERFACE

M SERIES

Length: Extended
Height: Quad
Width: Single

Volts

t~D

Power
mA (max.)

Pins

A2

1450

C2. T1

tim ....

IN M"" . .
IEL t:

.
IUS Dt5 Lr:"IA02
IUS D'"

.US 013
..... 01.

~us

~(ii.

em

AU

AF2

~m.A1t2

085 L

BUS De4 L

m
AP2

e ....

BUS [)IJ3 L TAT2

aus

082 l

8U$ 011 L

r.;..U2
iii-..

r.t. AS2

Olrf LOW ti

..... e01

BVSINrr l

00- ....,

'--

~

SELfJHff}-BFl

~

hi'}-______~---~s.~.eU"~N--~

eN'

SWITCH
FILTER

IK

:~

i
"'801
16-BITRElA'r'
OUTPUT INTER''''E

93

-ill •• T A

The M1801 is a PDP·ll interface module containing the bus receivers, relay
drivers, and control logic needed to program 16 isolated single' pole relay contacts. The relay contact outputs are available, at two 40-pin cable connectors
mount~d on the module.
"APPLICATIONS
For interfacing to the PDP-Il, the MI801 must be used with the MI05 Address Selector (or equivalent). The MI05 decodes the UNIBUS address lines
and causes transfer of information through the MI80l under program control. Interrupt,circuity is also built into the Ml80l and can be used in con·
junction with the M7821 or equivalent. An example of a typical PDp·Il interface is shown in the MI623 description.
FUNCTIONS
Registers: The MI80! contains two 8-bit read-write registers, both interfaced
to the computer bus data lines by bus receivers. Data from the computer is
clocked into the registers by strobing signals derived. from an MI05. The
registers have read-back capability for PDP-ll instructions that require a
DATlp·DATO sequence. The user has the'option of strobing a single 16-bit
word or two S-bit bytes. A logic HIGH (binary ONE) loaded into a register b'it
activates the corresponding relay output. Each relay output ha.!i a jumper
and split lugs which aI/ow the user to insert contact filter circuits.'·

Data Strobe Outputs: 'Either of the register·loading irwut pulses will trigger the
two DATA STROBE output circuits. One of these outputs is a transistor driver
circuit capable of sinking 100 mA (clamped to +5 volts). If jumper W54 is
removed, the user can switch up to 20 volts' at this. output.
The second DATA STROBE circuit contains a one-shot which drives a- relay
to provide a momentary contact closure. The one·shot has an internal potentiometer for pulse-width adjustment from 5 to 20 ms. External capacitance
can be added to split lugs on the module to increase the contact closure
time. Jumpers (W56 and W55) are provided which allow the user to choose
whether the relay output will be energized on a HIGH or LOW logic level.
Both DATA STROBE outputs are available at the 40'pin connector.
READY Relay and Level Inputs: When the interfaced device has received data,
it can signal the MISOI that it is ready for another transfer by either energizing the READY relay or by applying a TTL low signal at pin TT of the
edge connector Jl. The relay has a 5·volt coil rating and pulls in at 4.2 volts.
A jumper (W52) and split lugs are provided for users who want to add a
voltage divider circuit.
'
The signal on pin IT must be in the form of a HIGH-to·LOW transition: must
be HIGH for min. of 4 ms then go LOW for min. of 8 ms. Contact filtering.
(6.8 ms min.) is provided for either READY input to prevent false triggering
due to contact bounce. The switch filter output sets the INTERRUPT flag, the
output of which can be used to request an interrupt. Therefore, continuous
\ interrupts can be made at 12 ms intervals. This timing relationship is shown
in the foltowing figure.

PIN

I
I

TT!
I

--c

4MS
',SETUP
TIME

I

I

I

i l,----

f

I1-6.8MS~1.2MSI
I
l.I

I

I

I
I
14----8 Ms---.......I
I INTERRUPT REQUEST
I
I

TIME

94

Flags: The INTERRUPT flag can be set by the READY signal from the external
equipment. Interrupt capability is enabled by a second flag, INTERRUPT ENABLE, which can be set under program control. Both the INTERRUPT and
INTERRUPT ENABLE flags can be appHed to an M782I (or equivalent) for
computer interrupt. The INTERRUPT flag is cleared by the register-loading
signals from the MI05; both flags are always cleared by computer power-ups.
Register Preset JUlmpers: Each register bit on the M!80! has a jumper which
causes that particular bit to clear on power-on. If the user wishes to have a
particular bit set on power-on, he must remove the jumper provided and
install the particular jumper which sets that bit. Care should be taken to insure that both the set and clear jumpers are not inserted simultaneously.

DATA
Bit
000
·001
002
003
D04
005
006
007
008
009
010
011
012
013
014
015

-Jumper
to CLEAR
WI
W3
W5
W7
W9
WII
W13
W15
WI7
W19
W21
W23
W31
W29'
W27
W25

Jumper
to SET
W2
W4
W6
W8
WIO
W12
WI4
WI6
WI8
W20
W22
W24
W32
W30
W28
W26

Status Gates: Status gates on the MI801 give the programmer the ability to
check the states of hte INTERRUPT and INTERRUPT ENABLE flags. These
gates are. software-enabled through the address selector (MI05).
CAUTION
When the high output voltage or current capabilities of the MISOI are used,
the MISOI should be shielded from all computer circuitry.
SPECIFICATIONS
Relay Contact Ratings:

Voltage:
Current:
Power:
Insulation resistance:

100 V ma~
0.5 A max.
10 W max. resisttve load
1,000 megohms
'

Data Strobe Output:
Current Sinking:
Voltage:

100 mA max.
20 V max.

95

<

PDP-II
UNIBUS

M7821

INTERRUPt CONTROL MODULE

M SERIES

Length: Extended
Height: Single
Width: Single
A CLEAR H

A REQUEST I H

R1
1 r-:.:...--~-----,

I

U2
u - _ - - t _ -- --t B BUS A BR l

A REQUEST 2 H

A MASTER

n-_--I_.....;N-'-I--110 A MASTER l

CONTROL

A BG IN H
A BG OUT H
A SACK ENBL L
BUS SSYN l

J2

- - - - - - - - ·n_ _.-~°-'-ll B BUS B8SYl
~----(]

_________ JJ""'"----T.;..:2'-fB

BUS SACKL

B REQUEST 1 H
B REQUEST 2 H
B BG IN H

B El

B BG OUT H

B Al

B MASTER
CONTROL

n----t---'-P1--1

B BUS B BR L

D-_ _-.:..:S2~1O 8 MASTER L
W9

BUS NPR l

B CLEAR H

veCTOR 81T2 H

~---a---OO

B Jl

1 SI

1 t-=0;.;;2_----I --------~-

JUMPER
FOR"I"
NO
JUMf!ER
FOR "0"

6W3O-0wi0-6WsO-0wi0-0wi0-6WaO--

BUS 002 L
BUS 003 L

BUS 004 l
Fl

F2
HI

Kl
MI

A START INTR l

VECTOR
CONTROL

B START INTR l

Volts

+5

GND

Power
mA (max.)
550

96

Pins
A2

e2. T1

. BUS DOS L
BUS 006 l

The M7821 Iflterrupt Control Module is used with the interface logic of a
device in the PDP-ll systems. The M7821 allows one or two devices that
request an interrupt to gain access to the UNIBUS and become bus master
for one Qr more data transfers. It also provides a vector control circuit to
enable the selection of an address in memory at which the device subroutine
is stored.
The module consists of an A Master Control, BMaster Control, and Vector
Control logic. Either of the two master control circuits can be used to generate a Non-Processor Request (NPR) for direct data transfers to memory
(OMA) or~ a Bus Request (BR) which interrupts the current processor program. The A Master Control, however, is normally used for generating the
NPR and the B Master Control for the BR. When used as a DMA control, the
A Master Control has the ability to perform a tfJrst' mode block transfer
which allows more than one data cycle to be performed each time the device
becomes bus master.
The B Master Control contains logic which can be implemented to allow
the monitoring of the bus NPR line: This capability permits an NPR initiated
by a device to be honored under certain conditions and the device to gain
access to the bus even though a BR from another device has occurred prior
to the NPR. A jumper lead can be removed from the module to disable this
feature if the B half is used for NPR transfers.
The sequence of interrupt control signals between the M7821 and processor
is similar for both the NPR and BR; however, an interrupt signal and vector
address is generated after the device becomes master during a BR. The
interrupt signal halts the operating program in the processor and the vector
address specifies a location in memory where the starting address of the
interrupt status routine and a status word is stored.

FUNCTION
The interrupt request generated by a device is received as a High level on
either A REQUEST 1 or B REQUEST 1 input. The associated A REQUEST 2
and B REQUEST 2 inputs must be enabled with a High level to generate a
bus request. A non-processor request is initiated by the A Master Control
and the BUS A BR output is wired to the NPR bus line. The BUS A BR output
becomes Low during the request interval. The proce~or responds to the
NPRby issuing a high level to the A BG IN input. The A Master control
issues&- Low BUS SACK signal to the processor to acknowledge the A BG IN
signal and the BUS BBSY signal is asserted Low as soon as the current bus
master releases control of the bus to indicate the requesting device is bus
ma~e~
.
Normally, the BUS SACK Signal is returned to a High level after BBSY becomes Low. If more than one data transfer (bus cycle) is required during
the period that the device is bus master, the A SACK ENBL input can be
connected to a level which remains High until just before the last bus cycle
of the burst transfer is started. This level will prevent the processor from
issuing a bus grant requesting device until the data transfers have been
completed. This insures that the bus will be given to the highest priority
requesting device at the end of the burst.
A bus request (BR) is issued by the B Master Control in a similar manner
as the NPR. The BUS 8 BR output of the B Mastel' Control connects to the
assigned bus request priority line, BR4 through BR7. After the A Master
Control issues a Low to the BtJS BBSY line, the vector'logic issues a tow
BUS INTR signal to the bus interrupt line and transmits the vector address,

97

as preset by the jumper leads W2 through W7, to the data bus lines BUS
003 through DOS. The data from the device which initiated the interrupt
request is transferred to memory after the BUS BBSY -has been issue.d by
the processor.

APPLICATION
The following diagram shows a typical wiring configuration of the M7S21
module. An interrupt request can be initiated from Device A to the A Master
Control or by Device B to--+he B Master Control. The outputs of both master
controls can be wired together as shown and connected to the BUS BR4
line; therefore, an interrupt request from either Device A or B will initiate a
bus request at the same priority level. The A SACK ENBL input is ~onnected
to ground indicating that only one data transfer will be performed each time
the device becomes bus tnaster. The bus grant (A BG OUT) connects to the
bus grant (B BG IN) where both master controls are connected to the same
priority level of bus requests (BUS B~4).

M7821
DEVICE A

A IIEOlEST 1

A REOOEST2

J.

lA CLEAR

MASTER
CONTROL
A

A BG IN

GUS SSYN
DEVICE B

8 REQUEST 1
8 REQUEST 2

r-< ------r-------

I

~

8

BUS BBSY
BUS SACK

,-

't~

BUS! BR
VECTOR BIT 2

-----A--

aus

INTI

BUS 002

88GOUT

~--

BUS 003

P---I- -&MASTER

~-.

BUS 004

~

W9

--6"""b

;

AIIG oUr

MASTER
CONTROl

B BCiIN
BUS NPR

BUS Blt4

W4

~---

,8 CLEA

BUS DOS

W6

A

STARTI~

\

-

-=:::l

~---

BUS D06

W7
6().--

B START INTR

AINTR DONI:

aus 007

B INTROONE

TYPICAL M7821 APPLICATION
All jumpers W2 through W7 are connected on the Vector Control section of
the module. The A MASTER output connects to the VECTOR 2 input of the
Vector Control circuit. When the A Master Control section of 'the, module
becomes bus master, the A MASTER output will be low and the resulting
vector address on lines BUS 002 through BUS DOS will contain an octal 370.
If the B Master Control is selected, the A MASTER output will be high, producing a vector address of an octal 374. The A MASTER output and the
B MASTER output connect to the START INTR inputs of the Vector Control

98

or gate to initiate the interrupt request on the BUS INTR - line. When the
data transfer is complete, the INT DONE output of the Vector Control will
clear the appropriate master control section previously selected.
WIRING CONFIGURATION
During a BR, the vector address is specified by the information on lines
BUS D02through BUS 008. The address format is indicated below: ~

DATA BUS LlNES-

008

007

JUMPERS

006

DOS 004 003

002 001

000

ADDRESS BITS

WZ

DOZ·

W3

003
004
005
006
007

W4

WS
W6

W7

008

W8

• CONTROLLED BY VECTOR
BIT 2, INPUT

When a jumper is present between tHe designated lugs W3 through W8 on
the module, a logic ONE will result and when the jumper is removed, a logic
ZERO will be present on the corresponding vector address bit. With jumper
W2 instalted, the state of address bit 002 is determined by the logic level
present on the VECTOR BIT 2 input.
Jtlmper W9 is installed dur~ng manufacturing and must be removed when
used with early PDP-lI/IS and PDP-11/20 withciut the KHll option.
M7821 SIGNALS

Inputs

(X

= A or B Master Controls)

X REQUEST 1 H,
X REQUEST 2 H

Both signals must be asserted High to initiate a
BR or NPRand remain High until the requesting
device is through being bus master. Lowering either
of these lines will cause BBSY to be removed. Prior
to a new bus request, one signal must become Low
before being reasserted.

X BG IN H

Asserted High by the processor in response to a
request when the requesting device has the highest
~ori~
:

. X SACK ENBL L

Connect to ground (Low) when only one data
transfer by a device will be performed each time
the device becomes bus master. When a burst
mode block transfer is done,' this line should be
held High until just before the last transfer of the
block.

99

BUS NPR L

With jumper W9'connected, a low on the BUS NPR
line from the processor will prevent the B Master
Control from transferring a bus grant to another
requesting device. Remove this jumper if this section is used for an NPR device.

X CLEAR H

A High transition causes the associated master
control to remove the BUS BBSY signal and terminate bus mastership.

V.ECTOR BIT 2 H

A High input specifies an octal 4 in the least significantdigit of the vector address. A low specifies
an 'octal O.
.

X START INT L

A low transitio'n initiates an interrupt by loading
the vector address onto the UNIBUS and producing
a (Low) BUS INTR signal.

Outputs

BUS X BR L

Asserted low when X REQUEST 1 and X R'EQIlfEST
2 are asserted to indicate that a device has initiated aBR or NPR. Connect to desired UNIBUS BR
orNPR line.

X BG OUT H

Asserted High ta transmit the bus grant to the
next device on the same priority level.

BUS SACK L

Asserted Low to acknowledge to the processor, that
the requesting device has ~eceived the grant si'gnal
and is prepared. to become the bus master when
the current master releases the BUS BBSY signa.!.

BUS BBSY L

Asserted low to indicate that the requesting device is bus master.
,.;

X MASTER L

Asserted Low when the associated master control
has become bus master.
.

\

X INT DONE H

Asserted High at the completion of the interrupt
(when BUS SSYN is received).

BUS D02-D08L

Specifies the vector address to the UNIBUS.

BUS INTR L

Asserted Low by the requesting device after it has
become bus master to notify the processor that
the data lines contain a vector address.

100

DECkit11-D

This kit is designed specifically,for the PDP-ll owner who requires high I/O
data transfer rates. Full I6-bit data words can be transferred between the
PDP-ll memory and an external device at UNIBUS speeds. See Figure
The DECkit11-D interface kit is physically and electronically compatible with
all PDP-II Family computers.
Parallel digital data is cabled directly to and from the interface kit; no ,additional logic or hardware is required to handle TTL-compatible data. External
devices, such as lab instruments, mass storage units, displays, pre-processors, and other CPUs can communicate conveniently with the PDP-ll
memory_
The prewired backplane include~five unused module slots that can be used
for custom logic such as level ,shifters and counters. Even modules for
simple proceSSing logic can be utilized in these unused slots. Figure 2 is
a module utilization diagram of a DECkit1I-O.
OECkitll-O is valuable to the OEM and the end-user. The predesigned interface con~ept frees the system designer from the complex problems usually
\ associated with UNIBUS interfacing and the ,end-user has available the flex-'
ibility and speed of the UNIBUS for data transfers .

•

101

SPECIFICATIONS
Transfer Types:

Direct Memory Access (DMA) via NPR programmed
control

pata input to
PDP-II memory:

..

"

"\.

Data output from
PDP-II memory:

16-bit word
Parallel
TTL-compatible
Up to 100 ft I/O cable
Up to % million words/second*

/

16-bit word
Parallel
TTL-compatible, high-drive capability
Up to 100 ft I/O cable
_
Up to 2/5 million words/second*

Control and Status:

I6-bit Control and Status Register (CSR)
Handshaking control signalsData Available Out
Data Available In
Data Accepted Out
Data Accepted In
last Transfer
External Overflow
Status signals-Function/Out Status/ In

Interrupts:

Word ·count overflow }
"
./Non. existent memory
Set by Priority Interrupt
.Plug; shipped at level 5.
External overflow
Input demand
.
Interrupt enable/disable-CSR bit 06
.

Register assignments:

Word Count Register (WCR) 76xxxO**
Bus Address Register (BAR) 76xxx2* *
Control and Status Register (CSR) 76xxx4**
Data Buffer Register (OBR) 76xxx6'" '"

I/O connection:

Several stranded cables available (BCOBR, BCOBS)

Power:

+5V, ±5% @ 3 A; normally availalile from system
power supplies

Size:

One system un it

Weight:

4% pounds (approximately)

....

* Depending on memory and other options chosen.
** User-selectable addresses.

102

,,'

-'")

0(15:001

~

DMA
OUTPUT

-

V

V

A (17:001

l-

"

8US
ADDRESS

_t t t

CO

SELECT UNES

I
I LOAD

I L

Cl

LAST TRANSFER

I

MSYIII

~

.

0(15:001

~

~

~

DMA
CONTROL

V

DATA AVAILA8LE OUT

WCR
8AR
CSR

DATA ACCEPTED IN
USER'S

1/0

XOF

A (t7:ool

DEVICE

STATUS
OATA AVAILABLE IN

NPR
IIIPG

DATA ACCEPTED OUT

l

8RS

CiliA REOUEST

-

865
INT

,,-

REAO

INTERRUPT
CONTROL

A

K...,

I

FIilCT

SSYN

o (OB :021

1NT REQUEST

vt

0115:001

~

A

K....

DMA
INPUT

16-BITS

'----

• A17 and A16 are not used for data transfers. This implies
that only the first 32K of a PDP-ll memory may be addressed.
Fi~ure

1

DECkit11·D

B~ock

Diagram

Row

·A
Slot
04
03

UNIBUS OlJ-T

.

G772
POWER

02

01

8

-

o

F

E
SPARE
I

M796
M7821

UNIBUS IN

Figure 2.

c

M7219
M205

Ml16

M660

M9100

M113

1 M112

M1502

DECkit11·D Module Utilization Diagram (Pin Side)

103

, If mounting space is available in the existing PDP-II processor mounting box,
the DECkit can be installed there and jumpered to the existing panels by a
UNIBUS Connector Module, M920. Power is supplied from the processor
power supply, or from an additional H720 C or 0 Power Supply.
If the Interface Kit is installed in a separate mounting rack, the UNIIBUS is
extended to that rack with a BCIIA cable. This cable is available in various
standard lengths from 2 ft to 35 ft.
Input/Output Cables
Type
BCOSR-XXI
BC04Z-XXI
BC07A-XXI
BC07D-XXI

Connectors
HS56 to
HS56 to
HS56 to
HS56 to

Notes: 1. XX is length in feet
2. HS56 is a female connector

DECkit11-D
104

HS562
open-ended 2
open-ended2
open-ended 2

INTEGRATED CIRCUITS (ICs)
Two, 956 and 957, special ICs are available from Digital Equipment Corporation_
DEC8640 Unibus Receiver Ie (Quad 2-lnput NOR Gates)-956
The 956 is a package of ten 14-pin, dual-in-line package (DIP) DEC8640*
integrated circuits (ICs). Each IC comprises four 2-input NOR gates. Each
gate performs the Boolean function X
A
B. The DEC8640 gates are
especially suitable as Unibus receivers because of their high impedance
characteristics and, hence, minimal loading on the bus.

= +

These NOR gates are described in detail in the HARDWARE/ACCESSORIES
CATALOG published by Digital Equipment Corporation.
.
DEC8881-1 Unibus Driver IC (Quad 2-lnput NAND Gates)-957
The 957 is a package often 14-pin, dual-in-line package (DIP) DEC8881-1
integrated circuits (ICs). Each Ie comprises four 2-input NAND gates. Each
gate performs the Boolean function X
AB. The DEC8881-1 ICs are especially suitable as Unibus drivers because of their capability to sink 70 mA
with a ~ollector volt~ge of less than 0.8 v.

=

These NAND gates are described in detail in the HARDWARE/ACCESSORIES
CATALOG published by Digital Equipment Corporation.
*DEC8640 IC replaces DEC380 IC.

105

/

106

M7800
SINGLE ASYNCHRONOUS
SERIAL LINE INTERFACES
Length: Extended
Height: Quad
Width: Single

PDP·II

UNIBUS
M SERIES

-...,

DESCRIPTION
The M7800 is a highly·versatile single asynchronous serial line interface
module. It formats and controls the transfer of data between the paraUel
PDp·ll UNIBUS and serial external devices. The module can be configured to
interface with either 20 rnA current loop devices (e.g., models LT33 and LT35
Teletypewriter, LA36 DECWRITER, display terminals) or EIA RS·232-C devices
(e.g., EIA terminals or modems). The interface operates in either full or half
duplex mode and performs serial-to-parallel and parallel-to-serial conversion
of the transmitted data. When receiving data, the interface converts an asynchronous serial character from an external device into the parallel character
required for transfer to the UNIBUS. This parallel character can then be
gated through the bus to memory, a processor register, or some other device.
When transmitting data, a parallel character from the bus is converted to a
serial line for transmission to the external device. The two data transfer
units (receiver and transmitter) are independent and capable of simultaneous
two-way communication. The receiver and transmitter each operate through
a control and status register for command and monitoring functions, and a
data buffer register for storing data prior to transfer to the bus or the external
device.
The module is directly compatible with the PDP-ll UNIBUS and is designed
for installation into anyone of the available Small Peripheral Controller
slots of the BBll-M, DOll-A or DDll-B Interfacing Unit and the PDP-II
processor unit. It represents one unit load on the UNIBUS.
Configuration of the M7800 for a specific device involves selection of an
appropriate crystal, addition of an appropriate cable, and making certain
jumper selections on the module. A 40-pin BERG connector is mounted on
the edge of the module for connection to the external device. Data rates of
~6.7 Baud to 9600 Baud can be handled, and jumper changes <;an provide
for 5, 6, 7, or 8 data bits, even, odd, or no parity, and 1, 1.5, or 2 stop bits.
A full description of module configuration is given in DLll Asynchronous Line
Interface U$er's Manual, Dcicument EK-OLlI-OP-OOl, available from your local
sales office.
.

FUNCTION
The serial-to-parallel and parallel-to-serial conversion of the device data is
performed by a Universal Asynchronous Receiver Transmitter (UART). The
UART is a 40-pin dual-in-line package and includes the Circuits to double
buffer the characters in and out, select the character length and stop code
configuration, and indicate status information pertaining to each character.
Receiver
The receiver section performs serial-to-parallel conversion of the g-Ievel
codes. Each charecler appears· right justified in the Receiver Data Buffer
Register (RBU!), stripped of start, stop, and parity bits.

107

A complete character is formed in the UART and is transferred to the Receiver Data Buffer Register (RBUF) at the time the center of the first stop
bit is sampled. At that time, the Receiver Done Bit (Bit 7) is set in the
Receiver Status Register (RCSR). If the Receiver Interrupt Enable Bit (Bit 6)
is also set in RCSR, an interrupt request is generated. The BR level is set by
jumper plug. BR4 is standard.
The program the.!1 reads the RBUF. The character appears right justified in
bits 7·0 of RBUF, stripped of start, stop, and parity. The program has a full
character time to remove the completed-character from RBUF before the
next character.
Transmitter
The transmitter section performs parallel to serial conversion -of data sup_~ plied to it from the UNIBUS. The character length and stop code are the same
as for the receiver section. The transmitter section is also fully double
buffered. Any time the Transmitter Ready Bit (bit 7) is set in the Transmitter
Status Register (XCSR), the program may load the low-order eight bits of the
Transmitted Data Buffer Register (XBUF) with a right justified data character.
The Transmitter Ready Bit will be set any time the XBUF is available, whether
or not a character is currently being transmitted. This is a result of the
double buffering. If a character is not currently being transmitted and XBUF
is empty, the program may provide two characters in succession (within less
than OMe character time) to the transmitter.
..
As the first character is loaded, it is immediately transferred to the serializer
register internal to the UART, and the Transmitter Ready Bit (bit 7) in XCSR
is set again. If the Transmitter Interrupt Enable Bit (bit 6) is -set in XCSR, an
interrupt request will be generated any time the Transmitter Ready Bit (bit
7) is set. The BR level for the transmitter is the same as for the receiver.
The transmitter .supplies the start bit and the proper .number of stop bits.
Some Typical Applications
Figure 1 is a block diagram of an M7800 module configured to interface with
-a Teletype, while Figure 2 shows the module working with an EtA communications modem such as the .Bell Model 103 or 202.

\
108

M7800

.(

~D<11:00>

~.

=OI>.:;J::"======:::;,I
I

1--=::::;:=p::"::R"::L::LE::L
D~ .....
L--_-+.
f=s~~~~s=t

:

8aSY

.~
CONTROL

"'.
18R-~
SACK
.INTR

INTERRUPT
LOGIC

f

."----

J:-

l

I
I
I

....
o

ROR ENS_

/

on

i
~

~

,
I
I
I

I
20 .."
INTERFACE
CIRCUITS

TELETYPE
UNIT

I
I

I

.J

I
~

0<07'00>

J

I1_ _ _ _
IUS'

RECEIVEIIS

7

Figure 1 Block Diagram of M7800
Configured for 20 mA Current loop Device
I

_

M7800

PARALLEL DATA

>

XMlT
STATUS
eaSY
SSYN
SACK

ReVIt

STATUS

EItaOR
8ITS

r----

(!

~Tf

......
o

i

~

A<11:00>
C

DATASET

IW,r

L ___ _

D<15:0 >

Figure 2 Block Diagram of M7800
Configured for EIA R5-232-C Device

Data Rates
The. M7800 can operate over a wide range of standard data rates. The general range is determined by the crystal, which must be spectfied at the time
of order. The specific rate, which can be different for receive and transmit if
desired, is selected by the user via two rotary switches on the module. Table
1 lists the Baud rates available with the various crystals and switch settings.
Table .1
Switch
Position

Baud Rates with Standard Crystals

Crystal #1
(844.B kHz)
18·10245·01

1
2
3
4
5
6
7
8
9*

36.7
55
110
220
440
880
1320
1760

Crystal #2
(1.03296 MHz)
18·05501·06

44.8
67.3
134.5
269
538
1076
1614
2152

Crystal #3
Crystal #4
(1.152 MHz) (4.60B MHz)
18·05501·05

18-05501·07

50
75

200
300
600

150
300

1200

600

2400

1200

4800
7200
9600

1800

2400

10*
*These SWitch positions are for external clOCk inputs -and do not tap off the crystal oscillator.
NOTE: The baud rates .in italics are the most commonly used.

PROGRAMMING
The interface between a program running in the PDp·l1 processor and the
M7BOO is via four device registers: Receiver Status Register (RCSR); Receiver
Data Buffer Register (RBUF); Transmitter Status Register (XCSR); and Transmitter Data Buffer Register (XBUF). Each register is assigned an IS-bit memory address, and may be read from or written into using any processor instruction which references these addresses, with a few exceptions.
Detailed information on programming is contained in the DLll Asynchronous
Line Interface Users Manual, EK-DL11-0P·OOl, and in the Paper-Tape Software Programming Handbook, DEC-II-XPTSA-A·D.

...

III

GENERAL SPECIFICATIONS

Consists of one quad module, extended length, single
width.
Full or half duplex under program control.
Asynchronous, serial by bit. One start bit. One, 1.5, or
two stop bits selectable by user. Even, odd, or no
parity.
A one (1) presented by the program to any bit in the
Transmitted Data Register will c,ause a Marking (logicall) condition to appear on the Transmitted Data
lead during the corresponding bit interval. A zero (0)
presented by the program wiIJ cause a Spacing (Iogi- cal 0) condition to appear. A Marking condition on
the Received Data lead during any data bit sampling
interval will be presented to the- program as a one (1)
in the Received Data"'"' Register, and a Spacing condition will be presented as a zero (0).

Mechanical:
Operating Mode:
Data Format:

Order of Bit
Transmission: -

Low order bit first.

Distortion:

The M7800 receiver will operate properly in the presence of 40% space·to-mark or mark-to-space distortion between any two received data bits, and up to
± 4.5%, long-term speed distortion, provided the
data format contains at least one and one-half stop
units. If the data format contains only one stop unit,
the speed tolerance is ± 4%. The M7800 transmitter
operates with less than 3% bit-to· bit or long-term distortion.
One M7800 presents one unit load to the PDP-II
UNIBUS.
M7800 provides a 20 mA' active current loop for both
send and receive leads for connection to local teleprinters such as the DIGITAL LA30-C and Teletype
Models 33 and 35, and displays such as DIGITAL VT05
Terminal. It, by alternate selection of jumpers, provides a voltage level interface whose signal levels conform to Electronic Industries Association Standard
RS-232·C and CCITT Recommendation V.24.
The M7800 requires 1.8 amps of
5v., .05 amps of
I5v., and .15 a!1lps of -I5v.

~

Bus Loading:
Electrical
Interface:

Power
Requirements:

+

+

112

/

M7860
I-WORD INPUT/OUTPUT DEVICE
INTERFACE-

UNIBUS
M SERI~S

Length: Extended
Height: Quad
Width: Single
DESCRIPTION
The M7860 is a general-purpose interface between the PDP-II UNIBUS and
a user's peripheral. The" M7860 provides the logic and buffer register necessary for program-controlled parallel transfers of I6-bit data between a PDP-II
System and an external device as shown on Figure 1.
It is directly compatible with the PDP-ll UNIBUS and is designed for instal·
lation into anyone of the available Small "Peripheral Controller slots (SPC)
of a DOll-A, DDll-B or DDll-D System Interfacing Unit and the PDP·ll
processor unit.
All data and control signals between the M7860 interface and device are TIL
compatible.
The interface also includes status and control bits that may be controlled by
either the program or the external device for command, monitoring, and
interrupt functions.
The M7860 interface module consists of three functional sections: address
selection logic, interrupt control logic, and device interface lOgic.
The address selection logic determines if the interface has been selected for
use, which register is to be used, if a word or byte operation is to be performed, and what type of transfer (input or output) is to be performed.
The interrupt control logic permits the interface to gain bus control and perform interrupts to specific vector addresses. The interrupt enable bits are
under program control; the interrupt bits \ are under control of the user's
device;
The M7860 interface logic consists of three registers: control and status,
input buffer, and output buffer. Operation is initialized under program control
by addressing the M7860 to specify the register and the type of operation
to be performed.
The M7860 is designed for user applications and requires a minimum of
external hardware to implement into the PDP-II system. Two 4O-pin connectors are conveniently mounted near the edge of the board. These connectors permit the external device to be easily connected using BC08R or
BC04Z flat cables available from DIGITAL. These cables have the mating
connectors premounted and are supplied in any specified length.
The interface module occupies one SPC slot and is a quad-height, extended
length, single-width module.

113

,
Ollll-C I M78601 INl'UTIOUTPUT IlEVICE INTERFACE

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~

USY

SSYN

~
LOGIC

11£0 A (/NT AI
11£0 , (lNT II
.IE A
IE I

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INTR

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....
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f I
I

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.i~1s

I r--I

lr
DllWIIS

I r-l ~

1

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IlEQUfST

A

lEQUEST •

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'IWA 11611fS1

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~

!ELeelO
SELECT 2

A(J1:00>
ADDRESS

Cl0

MSYN
SSYN

"-

SELeCTION
lOGIC

SElECT.
OUT HIGH
OUT It:Ni
IN

-

esao
rO:I.

OCI05

GATING
CONTROl

'---

I

0100

~~ HOROVIUl

1f
-, r

W

,

-..

USER
DEVICE
lOGIC

!lEGISTEII AND
CONTROl lOGIC

'?

M7860 Block Diagram

r"'/

/

/

~

vi
J\.

16 BIT DATA

16 81T DATA

.1'ITERRLPT/CONTROl
en

ADDRESS

~

~

./

CD

Z
~

A

DRll-C
INPUT / OUTPUT
!'ITfRfACE

STATUS/CONTROL

V'

K "'6 BIT DATA

~

"'STATUS/CONTROL

-"
-V

USER'S
DEVICE

16 BIT DATA

••4

V
Figure 1

M7860 Interface

FUNCTION
If an output operation is specified, information from the UNIBUS is stored
in a I6-bit register. Once this register has been loaded under program control (e.g., MOV RO, OUTBUF), the outputs are available to the device until
the register .is loaded with new data from the bus. The register can also be
read onto the bus. Upon transfer of data to the buffer register, a NEW DATA
READY control signal is supplied to indicate to the user's device that data
has been loaded by means of a DATa or DATOS bus cycle and is read by
means of a DATI or DATIP bus cycle.
~hen an ihput operation is specified, the M7860 provides 16 lines of input
to UNIBUS transmitters. This permits data from the user's device to be read
onto the bus. A control Signal, DATA TRANSMITTED, informs the device that
the input lines have been read. The input lines, which are not buffered, can
be read by a DATI bus cycle (e.g;, MOV INSUF, RO).

The control and status register provides six bits that can be used to control
and monitor user functions. Two of these bits are interrupt enable (INT ENS)
bits under control of the program. Two bits (REQ A and B) are under direct
control of the user's device and can only be read by the program. These bits
can be used either to initiate interrupt requests or to provide flags that can
be monitored by the program. The remaining two bits (CSRO and CSRl) are
read/write bits that can be controlled by the program to provide command
or monitoring functions. In the mtlntenance mode, they are also used to
check operation of the interface.
An optional maintenance cable, BC08R·l, permits checking of the M7860
logic by loading the input buffer from the output buffer rather than from the
user's device. Thus, a word from the bus is loaded into the output register
and the same word appears when reading the input buffer, provided the interface is functioning properly.
The M7860 can also be used as an interprocessor buffer (IPB) to allow two
PDP-1I processors to transfer data between each other. In this case, one
M7860 connected to each. processor bus and the two M7860s are cabled
together, thereby permitting the two processors to communicate.

115

-

Output Buffer Register (DROUTBUF)-address selectable by user

~~LI

IS

o

_________________OO_T_~_T_O_M_A_W_F_FE_R

________________~

The output buffer is a I6-bit read/writ~ register that may be read or loaded
from the UNIBUS. Information from the bus is loaded into this register under
program control. At the time of loading, a pulsed signal (NEW DATA READY)
is generated to inform the user's device Wat the register has been loaded.
The trailing edge of the positive pulse should be used to allc;>w the data to be
loaded and settle on the user's input lines. Data from the buffer is transmitted
to the user's device on the data OUT lines by means of a DATO or DATOB
t>us cycle.
The contents 'Of the output b~ffer register may be read at any time by means
of a DATI or DATIP bus cycle. During the read operation, the output of the
buffer is fed directly to the bus data lines.
Whenever the maintenance cable is used, the data from the output buffer
is also applied to the input buffer register. This permits checking operation
of the interfate logic. The DROUTBUF is cleared by INIT.

,In"put Buffer Register (DRINBUF)-address selectable by user
o

IS

ORINIUf
167771,

L__~___________

INI'U
__T_~_rA_IIUFFEtI
_ _ _ _ _ _ _-,>-_ _....."

..

I"

The input buffer is a I6·bit read-only register that receives data from the
user's device for transmission to the UNIBUS. Information to be read is
provided by the user's device on the data IN signal lines. Because the input
buffer consists of gating logic rather than a flip-flop register, the data IN
lines must be held until read onto the bus. The register is read by a DATI
sequence and the data is transmitted on the UNIBUS, for transfer to the
processor or some other device. W!'ten the input lines are read during a
DATI sequence, a pulsed signal (DATA TRANSMITTED) is sent to th~ user's
device to inform it that the transfer has been completed. The trailinged,ge
of the positive·going pulse indicates that this transfer is completed.
Whenever the maintenance cable is -used, the input buffer register receives
data from the output buffer register rather than from the user's device. This
permits checking of the interface logic by loading a word from the bus into
the output register and verifying that the same word appears in the input
buffer.

Control and Status Register (DRCSR)-address selectable by user
IS

7

11.

6

.s

I -

0

~~ILUO_._I~________________1~7~f. . .I~I_:~I_l_:~I______~lc_~~I~a_:.....1
116

The control and status register is used to enable interrupt logic and to provide user-defined cO!11mand and status functions for the external device.

/

Two REQ4EST bits; which are under device control, may be'used to provide
device status indications, or may be used to initiate interrupts when used /
with associated 'tNT ENB (interrupt enable) bits which are under program
control. Two other bits (CSRO and CSR!) are controlled from the UNIBUS
and serve as command bits.
Although the REQUEST and CSR bits can be used for any function the user
desires, standard PDP-I! intEfrface conventions attempt to allocate bit 15
for error conditions and bit 7 for ready indications and both of these bits can
generate interrupt requests. In addition, bit 0 is normally used for start or
go commands.
INTERFACE SIGNALS
UNIBUS SIGNALS-The input and output data control, and status signals con·
form to the UNIBUS signal specifications outlined in the PDP·II PeripheJa/s
Handbook published by Digital Equipment Corporation. The M7860 _module
presents no more than one unit load on any UNIBUS signal line.
DEVICE SIGNALS-Data and control signals are transferred between the de·
vices and interface by two cables that attach to connectors Jl and J2" The
location of the connectors on the module is shown on Figure 2. Table 1 lists
the pin assignments of each connector and the signal drive or loading capa·

6ffity.

Figure 2

Connector Locations

.117

Table 1
Input and Output Signals
Inputs
Signal
INOO
INOI
IN02
IN03
IN04
IN05
lN06
IN07
IN08
IN09
IN!O
INII
IN12
IN13 IN14
IN15
REQA
REQ B

Connector

Pin*

Signal

IT

OUTOO
OUTOI
OUT02
OUT03
,OUT04
OUT05
OUT06
OUT07
OUT08
Jl
OUT09
OUTlO
OUTII
OUT12
OUT13
OUT14
OUT15
NEW DATA DRY··
DATA TRANS**
CSRO
CSRI
}Jl
INIT
INIT
J2

LL

H
BB

KK
HH
EE
CC

J2

Z

y
W

,V

U
P
N
M
LL
S

Jl
J2

,
Outputs
Connector

}

Pin
C

K
NN
U
L
·N

R
T
W

x.

Z
AA
BS
- FF'

HH

JJ .

W
C
K
DO
P
/
RR, ~N

*Remaining pins on Jl and J2 are connected to logic GND on M7860.
**Pulse signals, approximately 400-ns wide. Width can be changed by user.

\..

CABLE ASSEM BLlE5--Severa I cable assemblies are available from DIGITAL
for use with the M7860 module. Table 2 lists some of the recommended cable
types and lengths available. Maximum allowable cable length for the M7860
is 25 feet.

Table 2

Cable No.

Connectors

Type

Standard
Lengths (ft.)

SC07A-XX
BC07D-XX
BC08R-XX
SC04Z-XX

H856 to
H856 to
H856 to
H856 to

20-twisted pair
2, 20 conductor ribbon
Shielded flat
Shielded flat

10,15,25
10,15,25
1,6,10,12,20,25
6,10,15,25

open end
open end
H856
open end

118

GENERAL SPECifiCATIONS
Device Data
Inputloutput levels:
(user interface)

(

\

=

logic 1
+3 V
10gicO= OV

Data Inputs:

I6-bit word from the external device
One standard TIL unit load; diode protection
clamps to ground and +5V

Data Outputs:

I6-bit word from the UNIBUS. Either a full
word or an 8-bit byte (either, high or low)
may be loaded from the ~us~'
NEW DATA READY--drives 30 units, positive
pulse, 400-ns wide -Unless width changed by
an external capacitor.
DATA TRANSMITIED--drives 30 unit loads,
positive pulse, 4oo-ns wide unless width,
changed by an external capacitor.
INIT (initialize)~ommon signal on both connectors driven by one 30 unit road driver.·

UNIBUS Interface
Interrupt vector addresses:
Priority level:
Bus loading:

floating, 2 needed for each M7860, selectable
by user
BR5 (may be changed)
1 bus load

Mechanical
Mounting:
'. Size:

Input Current:

1 SPC slot
quad module
I.5Aat +5V
(no current need~d at -I5V)

The M1860 is also available with the BC08R-I maintenance cable and appli.
cable documentation as the DRII-C.

119

TRADITIONAL. MODULES
The modules described briefly in this section have been, for the most part,
superseded by other products in this H~ndbook_ They are presented here
for reference purposes; detailed descriptions are contained in earlier editions
of the Logic Handbook. Wherever possible, DIGITAL stocks and supports
these older modules but, because of parts availability problems caused by
state-of-the-art changes, some items may no longer be in production. Before
ordering any of these modules, always check with the Logic Products Sales
ordering any of these modules, always check with Logic Products Sales Support at DIGITAL Equipment Corporation, MKI-2/EI3, Merrimack, NH 03054.

PDP-8 Non OMNIBUS
POSITIVE BUS
MlOl Bus Data Interface
The MI0! contains fifteen, two-input TTL NAND gates with input ground
clamps arranged for convenient data strobing from the PDPSI I or POP8/l
positive bus.
Ml03 Device Selector
The MI03 is used to decode the six device bits transmitted in complement
pairs on t~e positive bus of the PDP-8/1 and PDP-8/l. _
MI07 Devi~elector
The MI07 is a device selector which, by the use of extended decoding of the
8MB lines 9 through 11, will provide seven discrete lOT pulses.
Ml08 Flag Module
Ifhe MI08 contains three general-purpose clocked flip-flops for use in flag
applications in 1/0 interfaces, etc. Gating is provided so that the flags can be
individually set or gated to the program in'terrupt inputs of a positive-bus
PDP-8 computer.
M623 Bus Driver
The M623 c,ontains 12 two-input AND gate bus drivers for convenient driving
of the positive input bus of either the PDP-8/1 or PDP-8/l. The output consists of an open collector NPN transistor.
M624 Bus Driver
The M624 contains 15 bus drivers intended for convenient 'driving of the positive input b4S of either the PDP-8/1 or PDP-81L.
M730 Bus Interface
The M730 interface module provides extremely flexible interface control logic
to connect devices, systems, and instruments tq the output half of the programmed 1/ a transfer bus of either a POP8/1 or a P0P81 L positive bus computer.
M732 Bus Interface
The M732 interface module prov.ides extremely flexible interface control
logic to connect devices, systems, and instruments to the input half of the
programmed 1/0 transfer bus of either a positive bus' PDPSII or PDPS/l
computer_

120

M734 I/O Bus Input Multiplexer
. ,
The M734 is a three-word' multiplexer used for strobing 12-bit words .on a
positive voltage input- bus, usually the input of the PDP-8/1 or the PDP-8/L.
Device selector gating is provided. The data outputs of the M734 Multiplexer
consist of open collector NPN transistors which allow these outputs to be
directly connected to the bus.
M735 I/O Bus Transfer Register
The M735 provides one 12-bit input bus driver and one 12-bit output buffer
register for input and output data transfers on the positive I/O bus of either
a" PDP8/1 or a PDP8/L. Device selector gating plus additional signal lines pro, vide the flexibility necessary for a complete interface with the exception of
flag sense signals. Use of the M735 is not restricted to a computer, as .t can
be used in many systems to provide reception and transmission of data over
cables.
M736 Priority Interrupt Module
_
The M736 is used in conjunction with the POPS/lor 8/l to provide the
capability of assigning..priorities to various I/O devices connected to the I/O
bus of the computer. The M736 can be used to assign priorities for one thru
four external devices.
M737 I2~Bit Bus Receiver Interface .
The M737 was designed primarily to receive and store in a buffer register
twelve parallel data bits from the positive bus of the PDP-8/1 or PDP-8/L.
M738 Counter/Buffer Interface
,The M738 provides a 12-bit binary up-counter that can be read to the positive external I/O bus of a PDP-8/1 or PDP-8/l. The counter can,be cleared
or present to a starting value by a jam transfer from an external device. When
a count enable flag is set, the counter operates as an up-counter in response
to external clock pulses. The content of the counter can be strobed to the
I/O bus through data gates under program control.
M907 Diode Clamp Connector
" ,
The M907 is used to provide proper undershoot ground clc~rrips for:' devices
receiving PDP-8/1 and PDP-8/l positive. I/O bus signals that are not so
,protected.
NEGATIVE BUS
MOS1 Positive-to-Negative Logic level Converter
The M051 contains twelve level converters that can be used to shift M and
K Series logic levels to negative logic levels of ground and -3 volts.
- MIOO Bus Data Interface
The M100 Bus Data Interface contains fifteen circuits for convenient reception of data from the PDP-8, PDP-8/1 negative voltage bus. It is pin compatible with the M 101 Positive Bus Data In:terfa,ce.
'M102~Device Selector
..
The M102 is used to decode the six device address bits' transmitted in complementary pairs on the negative 8MB bus of the PDP-8, PDP-8/L The outputs of the M102 are compatible with M Series TTL logic. The MI02 is pin
compatible with the MI03 Positive bus device selector with the exception of
the address inputs.
'

121

M5.()2 Hlgh·Speed Negative Input Converter,
(,,
contains two non-inverting high·speed signal converters which in- - - terface standard negative (-3 volts and ground) logic levels or pulses with
M and K Series positive logic modules.
'

Th~ M502

M506 Medium-Speed Negative Input Converter
The M506 contains six noninverting signal converters which can be used to
interface the negative logic levels or pulses of duration greater than 100 ns
to M and K Series positive logic levels of +3 volts and ground.
M632 Positive In/Negative Out Bus Driver
The M632 contains eight two-input AND gate bus 'CIrivers for convenient'
driving of the negative bus of the PDP-8/1 or PDP·8/L.

M633 Negative Bus Driver
The M633 contains 12 bus drivers intended for convenient driving o'f the
negative bus of the PDP·S, PDp.-8/1. Each driver consists ,of an open collector
PNP transistor. It is pin'compatible with the M623 positive voltage bus
driver.
..
M650 Negative Output Converter
J
The M650 contains three non inverting signal converters which can be used
to interface the positive logic levels or pulses (of' duration greater ~han
100 ns) of K and M Series to digital negative logic levels of -3 volts and
ground.
M652 Negative Output Converter
.
The M652 contains two noninverting high-speed signal converters which can
be used to interface the positive logic levels or pulses of the K and M Series
to digital negative logic levels of -3 volts and ground.

PDP·l1 MODULES
M1621 DVM Data Input Interface
The Ml621 is a PDP-ll interface module containing all the bus drivers and
control logic needed to input TTL-level information from several types of
digital ~pltmeters and multimeters. All inputs from the instruments enter a
40-pin cabte connector mounted on the module.
M1623 Instrument Remote'Control Interface
The M1623 is a PDP-ll interface module containing the bus receivers and
control logic needed to remotely program several types of digital voltmeters
and programmable power supplies. All outputs to the instrument are through_
a 40'pin cable connector mounted on the module.
PDP-I5-.MODULES
./

M500 Negative In/Positive Out Receiver
The -M500 module is used to convert negative input signals to positive
output signals. Each card contains eight converters and is pin compatible
with the PDP-I5 positive receiver card (M510).

M510 I/O Bus Receiver
The M5IO is a positive input/output receiver card for use with the PDp·15.
It contains 8 high-impedance input circuits of at least 27K ohms and input
switching thresholds of about +1.5 V.
122

M622 B-Bit Positive 1/0 Bus Driver
The M622 contains 8 two-input AND gate bus drivers for convenient driving
of the positive input bus of the PDP-15. The output consists of an open
col/ector NPN transistor.

DECkits
DECkitll-H
The DECkit1I-H, when fully configured, is capable of reading four I6-bit words
from a peripheral device into a PDP-II. It is also capable of writing four j,6bit words, or eight 8-bit bytes, from a PDP-ll to a pellipheral device. Each
input word is supplied with an interrupt capability to signal the processor
that the word should be read.

123

\
124

MICROCOMPUTER -INTERFACING MODULES
LSI·ll SERIES COMPUTERSINTERFACING SELECTOR GUIDE

125

~
~-

"

M_IC_R_O_C_O~M~P_U_T_ER

______

______

~I~

This section describes the general characteristics of the LSI-11 Microcomputer-the newest in the popular DIGITAL PDP-ll computer family. Additional literature providing detailed information is available from your nearest
DIGITAL sales office.
LSI technology enables DIGITAL to put an N-channel MOS central processor,
4096 (4K)~word random-access 'memory (RAM), vectored automatic interrupt
logic, real-time clocl'<. input, and auto program start up logic, on one 8.5-by10-inch printed-circuit board. On one board you get a versatile microcomputer-centraI processor, memory, and input/ output bus port-micro in size
and price, but mini in computing performance.

. "" Features:
• A large, flexible instruction repertoire, incwding the 400-plus instructions
of the basic PDP-II/40.
• A simplified, application-oriented bus structure for maximum ease in handling I/O and memory operations.
• Software and hardware training classes.
• Complete documentation, including user's programming, and maintenance
manuals, Microcomputer handbook, product and option bulletins, configuration and installation' guides.
•
•
•
•
•

Off-the-shelf, plug-in interfaces.
\ '
Off-the-shelf, plug-in core, RAM, and/ or PROM/ ROM expansion ni"emories.
Resident firmware debugging techniques and ASCII console routines.
Operating system development on standard PDP-U/35, 11/40 or LSI-l1.
The unmatched resources of the DECU.S user's library for PDP-II application programs.

These tools give you complete flexibility in developing hardware and software. You can use the LSI·II in its final, dedicated environment to -optimize
your system design under actual operating conditions or take advantage of
the power, flexibility, and high-level programming languages available with
large PDP-1l/40 computers to reduce the time to develop your operating
system.
PROCESSORS
Microcomputer module KDll·F
The I6-bit central processor functions are contained in four silicon gate Nchannel metal oxide semiconductor (MOS), large-scale integration (LSf), integrated circuit chips. These chips provide all instructions, decoding, bus
control, and arithmetic/logic unit functions of the processor. The central
processor contains eight general registers which can serve as accumulators,
index registers, autoincrement/autodecrement registers, or stack pOinters.

4096-by-16 read/write MOS semiconductor memory is contained on the
microcomputer module. This memory is composed of LSI dynamic randomaccess memory (RAM) chips that require little operating power, provide fast
126

access time, and are refreshed automatically by the processor's microcode,
which is transparent to the user. A memory register on the KDll-F module
-addresses all onboard memory plus LSI-ll bus-compatible expanston memory up t032K words or 64K bytes.
Multiplexed parallel I/O bus port ·DMA operation. The LSI-ll bus is a high·
speed, 38-line parallel bus containing data, address, cOntrol and synchronization lines. Sixteen lines are used for time multiplexing of data and addresses.
All data and control lines are bidirectional, asynchronous, open-collector
lines capable of providing a maximum parallel data transfer rate of 833K
words per second under direct memory access operation.
Powerful PDp·IIJ40 basic instruction set. More than 400 powerful instructions make up the LSI-U's extensive basic instruction set. There are no
separate memory, I/O or accumulator instructions. Thus the user can mani. pulate data in peripheral device registers a~ flexibly as in memory registers.
The basic operation code uses both single- and double-operand instructions_
for words or bytes, making it possible to perform such operations as adding,
subtracting, or moving two operands in one step. This can reduce the number of instructions needed for many routines by as much as two-thirds. Much
of the LSI-ll's operating flexibility and processi~ power are derived from
its wide variety of addressing techniques. AddressTng can be direct, indirect,
'autoincrement, autodecrement, byte or word, indexing and stack-addressing.-'
This flexibility means the LSI-ll can deal with data in the most -efficient manner. The general registers can be used interchangeably as stack pointers, accumulators, and index registers. Address modification can be done directly in
the general registers.
Extended instruction and floating·point instruction options provide fixed-point
multiplicatioh, division, and multiple shifting in single-precision arithmetic as
well as floating-point addition, subtraction, multiplication and division.
Single·level, vectored, automatic priority interrupt provides for user-implementation of a priority-s,tructured I/O interrupt system. Devices electrically closest
to the microcomputer module receive highest priority, for either DMA or
programmed I/O transfers. (DMA devices have a higher priority than programmed I/O devices). This structure allows nesting of interrupts to as
many levels as there are devices connected to the LSI-ll bus. Upon receipt
of an interrupt grant, the device directs the processor to an interrupt vector
location which contains the starting address of the- device interrupt service
routine and the new processor status word.
Real·time clock input signal line functions as an external interrupt line. When
connected to a frequency source, it can serve as a real-time processor interrupt. A jumper on the microcomputer module enables or disables this highest
priority interrupt function.
Asynchronous operation of all system modules permits each to fUnction at
its highest possible speed.
Power fail/autostart provides jumper-selective restart through a power-up
vector, a defined location, or an octal debugging technique (DDT) micro~ode.

ODT/ASCII console routine/bootstrap all are resident in microcode to provide
automatic entry into the debugging mode, replacement of conventional programmets' panel lights and switches with any terminal device generating stan.,--

127

dard ASCII codes, and the ability to automatically commence operation
through resident bootstrap routines.
8.5-by-IO inch board contains all of these features.

~

Microcomputer module KDII-J
Contains all the same features as the KD11-F except that it utilizes a 4K x
16 core memory. This microcomputer is contained on two B.5" x 10" boards .
. Microcomputer module KD1I·R
Contains all "the same features as the KDll-F except that Random Access
Memory (RAM) size is increased to 16K. This microcomputer is contain~d on
two 8.5" x 10" boards.
EXPANSION MEMORY MODULES
4K dynamic random-access. memory-:-MSVll-B is a dual-size (B.5-by-5-inch)
read/write memory module utiltzing dynamic MOS semiconductor memory
devices. The module capacity is 4096 words of 16· bits, with memory-select
circuitry for operation on 4K address boundaries. Dynamic memory refresh
is performed automatically every 1.67 milliseconds by microcode on' the
microcomputer module.
16K dynamic MOS memc#Y-MSVI1-CD is a quad-size (B.5-by-l0-inch) read!
write memory module with 16K words of 16 bits each. This module features
4K dynamic MOS technology, internal refresh, 4K bank memory addresses,
and 750 nanosecond cycle time with 390 nanosecond access time. There
are no special power requirements and memory -eontents can be protected
in the event of a power loss by user-implemented battery back-up power
source.
4K programmable read-only memory-MRV1I-AA is a dual-size (B.5·b)ll6-inch)
field programmable, read-orily module utilizing either 256 x 4 .or 512 x 4
fusible-link semiconductor devices. The module's maximum capacity is 2048
or 4096 words 16 bits (depending' upon which device is used), and is expandable in 256- or 512-word increments. This module is configured with 32;
sockets for mounting memory IC devices of the user's choice. PROM chips
can be supplied as an option. A pin-compatible masked ROM chips is available for volume applications so that the lowest possible cost can be achieved.
Board·mounted jumpers enable selection of the module's address.

4K core memory module-MMVll-A is a quad-size (8.5-by-l0-inch) core,
read/write memory module containing 4096 words of 16 bits, with memory
address selection circuitry for starting operation on any 4K boundary. Core
memory provides non-volatile read/write storage for applications requiring
protection against power losses.

128

LSI-ll INTERFACING MODULES
Table 1 summarizes the interfaces and related modules that are described in
detail on the following pages or in the DIGITAL Direct Sales Catalog where
noted.
Although each interfacing problem is likely to have some unique aspects, the
steps to follow in general are:

1. Determine your interfacing requirements. .
2. Match these requirements against the products listed in Table 1, then read
the detailed descriptions.
3. Select suitable products if any are nsted~ If no listed products meet your
requirements, contact your DIGITAL Field Sales office to find if any ottier
~IGITAL products can perform the needed functions.
4. Add the power, and mounting space requirements of al\ modules to be
employed, and note the cables needed plus any prerequisites and restrictions that apply.
5. From the appropriate sections of this Handbook and the Hardware/ Accessori~s Catalog, select the cables, power supplies, and mounting hardware
toO complete your system.
If you need technical assistance with any product in this Handbook, feel free
to call DIGITAL's toll-free Hot Line, 8:30AM to 5:00 PM Eastern time, 800-2581710. From New Hampshire locations or places outside the United States, call
Merrimack, 603-884-6660.
.

129

Tabl.1

DEVICE OR FUNCTION

CABLE
REQ'O

1.6

.25

2.48

ED S

BC05C

20 mA current loop serial devices. e.g.:
LA35 printer
LA36 printer terminal
LA180 printer

DLVll

1.6

.25

2.48

ED S

BC05M

DLVll-E

1.0

.2

1.65

ED S

BC05C

COMMENTS

/

Modem

./

'\,

DLVll

~~g g:~ !:;:;::~::

0

DC MODULE
LOGIC POWER POWER AC
SIZE
H'BOOK
BUS BUS
+12V
+5V
AMPS' AMPS LOAO LOAD L H W2
PAGE'

EIA RS232C serial devices. e.g.:
LA35 printer
LA36 printer terminal
LA180 printer
LS120 printer terminal
VT52 CRT terminal
VT55 CRT terminal

VT55 CRT terminal

....
e»

MODULE
OR
OPTION

Interface Selector Guld6-LSI-ll BUS

A/D converter. 16-channel

ADVll-A

2.0

.45

3.25

E Q S

BC04Z

D/A converter. 4-channel

AAVll-A

2.0

.45

1.91

EQS

BC04Z

Power fail/line time clock generator
Same. with 120-ohm termination
resistor

KPVll-A
KPVll-B

.56

1.63

ED S

70-08612

Real time clock. crystal controlled

KWVll-A

1.75

3.41

EQS

BC08R

I-word parallel input interface
I·word parallel output interface
l·word parallel Input/output interface

DRVll

2.80

ED S

BC070

IEEE 488/1975 instrument bus

IBVU-A

1.77

ED S

.90

1.5

.01

Supports EIA slenals for
modem .

Cable listed Is for use witl}
console front panel. 24V
transformer required.

Has separate input and output
channels.

BNllA·04 Cable BN01A·04 must be
ordered for each Instrument
beyond the first.

suppll~

I"

Interface foundation module

DRVll·P

1+

2.08

EQS

Can accept up to about 50
BC04Z.
BC07D. or user ICs.
BC08R

Direct Memory Access (OMA) Interface

DRVll·B

1.9

3.30

E Q S

BC04Z

.

Table 1

DEVICE OR FUNCTION

....
W'
....

MODULE
OR
oniON

Interface Selector Gulde-LSl·ll BUS (cOnt.)
LOGIC POWER POWER AC
DC
H'BOOK
+5V
+l2V BUS BUS
PAGE"
AMPS' AMPS LOAD LOAD

M'~Z~LE
L...H W"

CABLE
REQ'D

COMMENTS

Desll'ner's prol'ram control CHIPKIT

DCKll·AC

.74+

EDS

BC07D·I0
supplied

Desil'ner's DMA CHIPKIT

DCKll-AD

1.22+

ED S

BC07D·I0 CHECK WITH LOGIC PROD·
supplIed UCTS SALES SUPPORT
BEFORE ORDERINGI

Wlr.wrapp.ble modules:
Qua'd·hell'ht, no IC sockets
Qu.d.heil'ht, 58 16·pln IC sockets
Double-hell'ht, no IC sockets
Double-hel.ht, 25 16·pln IC
sockets

W9511
W9514
W9512
W9515

E Q S
E Q S
ED S
EDS

NOTES:

,1. + means current required by user IOllc must be added to tipre shown.
2. Module sizes lire liven as Lena'th, Hellht, and Width, 8S defined in General Information.
a. DSC DIrect Sale. Catalo••

=

,.

~

INTERFACING MODULES
Serial line unit-DLVll is a universal asynchronous receiver/transmitter
serial interface module for use between the LSI-ll bus and serial devices_ It
is a dual-size (8.5-by-5-inch) module with the following features:
• Either optically isolated 20mA current loop or EIA interface.
• Selectable baud rates: 50, 75, 110, 134.5, 150, 200, 300, 600, 1200,
1800, 2400, 4800, 9600.
• Jumper-selectable stop bits and data bits.
• LSI·ll bus interface and control logic for interrupt processing and vectored
addressing of interrupt service routines.
/
132

11

• Interrupt priority determined by electrical position along the LSI-ll bus.
• Controll status register ·(CSR). compatible with PDP-II software routines.
CSRs and receiver data buffer registers directly accessed via processor instructions.
.
• Plug, signal, and program compatible with PDP-II DL II-C.
Parallel line unit-DRV11 is a general-purpose, I6-bit parallel interface between the LSI-ll' bus and the user's peripheral device. It is a dual-size (S.5by-5-inch) module with the following features:
• 16 diode-clamped data input lines.
• 16 latched output lines.
• 16-bit word or S-bit byte data transfers.
• Complete device address decoding user-assigned.
• LSI-ll bus in;tfrface and control logic for interrupt processing and vectored
addressing of interrupt service routines.
.
• Interrupt priority determined by electrical position along .the LSI-ll bus.
• Control/status registers (CSR) compatible with PDP-ll software routines.
CSR and receiver data buffer registers directly accessed via processor instructions.
• Plug, signal. and program compatible with PDP-ll DRll-C.
• FOUf control Unes available to the peripheral device for output data ready,
output data accepted, input data ready, and input data accepted logic
operation~.

• Can be used with TTL or DTL logic-compatible devices.
• Maximum data transfer rate of 90K words per second under program control.
• Maximum drive capability of 25 feet of cable ..
Digital-to-Aanalog Converter-AAV11-A
The AAVll-A is a four-channel digital-to-analog converter that allows the user
a wide variety of output voltage ranges that are jumper selectable. Each 12bit D/ A converter has its own holding register which can be separately addressed and can be written and read in either word or byte format.
AAV11-A Specifications
Packaging
Number of 0/ A converters
Digital input
Digital storage
Output voltage range
(jumper selected)
Resolution
Gain accuracy
Gain temperature cOElfficient
,
I
Offset temperature' coefficient

one quad (10%" x 8.5") module
4
12 bits (binary encoded for unipolar mode;
offset binary encoded for ~ipolar mode)
read-write, word or byte operable, single
buffered
± 2.56V, ± 5.12V, ± 10.24V bipolar, OV
'- to
5.12V, /
OV to + 10.24V unipolar
12 bits (1 part in 4096)
adjustable (factory set for bipolar ± 5.12V)
10 ppm per degree C, max....

+

20 ppm' of full scale degree C, ma',C;

133

± % LSB max. non·linearity
± % LSB ~monptonic

linearityl
Output impedance

1 ohm max.

Drive capability
Slew; ng speed
Power requirements

± 6 mA max. per converter

Bus load

5V micro sec.
5V ± 5% @ 1.5A
12V ± 5% @ O.4A

== 1

Analog-to-Digital Converter-ADVI1-A
The ADVll-A is a 12-bit analog-to-digital converter with built-in multiplexer
and sample-and-hold that allows the user the availability of 16 channels of
AID single-ended or 8 quasi-differential inputs and will convert an analog
.
voltage from ±5.12V full·scale bipolar.
The ADV11-A features a buffer register that allows data from one conversion
to be transferred to the processor after a subsequent conversion begins. This
buffering optimizes the throughput rate of the converter, enabling the
ADV11-A to run at 25 KHz* throughput to memory. The auto-zeroing technique-another feature-uses a patented design that measures the sampled
signal with respect to the offset of its own internal circuitry and thus effectively cancels out its own offset error contributions to the measurement.
There are also three built-in signals for self-testing; they may be connected
through a wrap-around BERG connector to any channel. The test signals
are two d.c. levels, and one bipolar triangular waveform. The bipolar triangular
wave can be used with diagnostic software to produce a data base for extremely thorough and precise analog linearity testing.

ADVI1-A Specifications
Packaging
Input voltage range
Resolution
Number of channels
Input impedence
Input bias current
Temperature stability
Throughput
Data acquisition time
Power consumption
Bus load

=1

one quad (10%" x 8.5") module

.± 5.12V bipolar (full scale)
12 bits (1 part in 4096)
16 siRglc~-ended, or
8 quasi-differential
.
100 megohms minimum
100 nA, maximum
gain == 5ppm per degree C
linearity == 2ppm of full-scale range per degree C
25 KHz*
40 micro sec ..
5V d.c. ± 5% @ 1.75A
12V d.c. ± 5% @ 350 mA

+
+

, *Using an LSI-ll system under optimum programming and DMA refresh.
Real Time Clock-KWVI1-A
The KWVl1-A is a programmable real-time clock that offers the..user several
methods for measuring and. counting intervals or events from 1 micro sEtcond
to 650 seconds. It can also be used to synchrOnize external equipment to the
processor. The KWVll-A is a 16-bit clock that will operate in one of four

134

programmable modes and can be selected to operate at one of five crystalcontrolled frequencies.
,-

KWVll A Specifications
Packaging

one quad (100/8';

Programmable modes

single interval,Jepeated interval external
event timing, external event timing from zero
base.

,~

Crystal controlled frequency
Accuracy
Power requirements

X

8.5") module

1 MHz, 100 KHz, 10 KHz, 100 Hz frequency
0.01%

+ 5V d.c. ±

-+

5% @ 1.75 amps
12V d.c. ± 5% @ 10 rnA

Bus load_= 1

NOTE
Detailed ,descriptions for LSI-II options for DMA,
power fail line clock generator, and LSI-ll bus
foundation module are included at-the end of
this Microcomputer section.

HARDWARE/ ACCESSORIES
Backplane Options
Two backplane op~ions are available: the H9270 and the DDVll-B. The
H9270 is a four-by-four slot LSI-.ll bus-structured backplanel card guide assembly. It can accept the process'Ol:' module and up to six options. Power is
applied to the backplane via a screw-terminal block located on one end of
the assembly.
The DDVll-B"is an expanded version of the standard LSI-l1 backplane (the
H9270) for use when additional LSI-ll option module space and/or custom
wire wrap space is required. A nine-by-four slot section of this backplane is
LSI-ll bus-structured and will accept the processor module, up to 15 option
modules, and one TEVl1 bus terminator module. An additional nine-by-two
slot section of the backplane is provided with power connections (+5 Vdc,
±12 Vdc, and ground), only; wire wrap pins allow the user to interconnect
the slots with appropriate signals.
An optional card cage, type H0341, is available for use with the DDVll-B
backplane. It provides physical protection to modules and serves as a card
guide. The card cage completely surrounds the DDVll-B on the module side
of the backplane.
Expander Box H909-C
The H909-C expander box provides -a most convenient means for expanding
the LSI-ll system: Each box includes the card guide and space for the
DDV11-B and the pdWer supply_

NOTE
Detailed descriptions of the .above items (DDV11Band H909·C) are contained in the HARDWARE/ POWER SUPPLIES section of this Handbook.
Bus Accessory Options
Several LSI-II bus accessory options are available for bus expansion, bus
135

termination, DMA refresh, bootstrap ROM, and combinations of the preceding.
A summary of ~he options is provided below:
System Functions

Includes

Module No.

M9400-YA Module

REVII-A

120 D bus terminator, DMA refresh,
bootstrap ROM.

REVll-C

M9400-YC Module

DMA refresh, bootstrap ROM.

TEV-l1

M9400-YB Module

120

n bus terminator.

BCVIA-XX

Two BC05L-XX
-cables, one
M9400-YD module,
and one M9401
module.

Bus expansion: two expansion cables
and two backplane connector modules (M9400-YD and M9401). Normally u~ed for' expansion from
second to third backplane in 3-backplane systems. (A TEVll or REVll-A
120 D terminQtor must be installed
in the last device slot in backplane
3.)

BCVIB-XX

Two BC05L-XX
cables, one
M9400-YE module,
and one M9401
module.

Bus expansion: 250 D terminator
(M9400-YE), two expansion cables,
backplane connector (M940I). Normally used for expansion from first
to second backplane in 2 or 3
backplane systems.

,NOTE
The -XX in BCVIA-XX and BCVIS-XX options denotes cable lengths. Options are available with
cable lengths of 2, 4, 6, and 10 ft. For example, ...
BCVIA-06 includes two 6-ft cables. When the
BCVIA and BCVIB options are used in a three
backplane system their lengths should differ by
4 ft. so that any transients will occur on the
cables a-nd not on the backplane. - - -

a

The REVll-A and -REVll-C options contain programs stored in the ROM.
These programs include processor and memory diagnostics, bootstrap programs for the RVl1 floppy disk system, and absolute loader programs for
paper tape readers.
TEVll (or REVll-A), BCVlA, and BCVl B options are used for system expansion in multiple backplane systems. In addition, the REVll-A or TEVl1 can
be used to terminate the DDVll-B backplane (require~when more than six
\
option modules are installed on the backplane)~.

I

LSI·II SOFTWARE
The LSI-II software consists of a paper tape software (QJVI0-AB) operating ,
package available with the LSI-ll ,as a basic utility package and an Editor,
which allows the user to create and modify ASCII source files to be used
as input to other system programs; an Assembler, which allows the user to
translate assembly language programs into executable machine-coded pro'grams; a Loader, which allows the user to input programs and data from
various media into the machine; an On-line Debugging Technique (ODT)
Package, which allows the user to debug assembled and linked programs; an
136 \

Input/Outpu( Executive, which allows the user to control the flow of data to
and from devices under program control.
LSI-II Systems Software include a paper tape software operating package,
a variety of operation systems, programming languages, diagnostic software,
paper tape software and special software options.
Real-Time Operating System RT-ll
RT-ll is a floppy disk based, single-user, foreground/background system
that can support a real-time job execution in the foreground and an interactive or batch program development job in the background. It is a high performance system which combines fast, on-line access with high level programming language capabilities and user-beneficial features such as stack
processing and vectored interrupts.
Resource-Sharing Operating System RSX-IIS
RSX-llS is an execute-only operating system designed to provide the most
efficient resource-sharing environment for multiple real-time.--atUvities without a mass storage device. This operating system features multi-programming, priority scheduling, contingency exist, and power-fail shut-down and
auto-restart.
RT-ll Programming Languages
MACRO-II, the assembler, provides full macro programming capabilities in
systems with 8K of memory. It has facilities for maintaining and using a
macro library and performing conditional assembly.
Multi-user BASIC is a fast incremental compiler developed by DIGITAL using
a conversational programming language developed at Dartmouth. It Qr.9vides
on-fine time-shared access to the LSI-l1. Sev~ral users simultaneously can
develop programs, enter and retrieve data, examine files, and communicate.
It is one of the easier programming aids to master, yet it offers extremely
sophisticated techniques for complex manipulations and efficient problem~
solving.
FORTRAN-IV is an updated, improved version of a. widely accepted scientific
problem-solving language and compiler, contained in 8K words of memory.
It can be used to perform integer, real and double precision operations.
Both program execu.tion and compilation is much faster using this version.
Input and output can be accessed directly, and all RT-ll monitor functions
are completely accessible through callable subroutines. Object programs are
put out in run time format without any intermediate assembly.

PROM Formatter QJVII-CB
This software generates formatted tape from which a PROM chip can be
blasted.
LSI-II Paper Tape Diagnostics ZJVOI-RB
These tapes test the pro<;essor, exercise the memory, isolate problem modules and exercise the I/O devices.

137

DRVll·B Direct Memory Access
(DMA) Interface

LSI-II
M SERIES

Length: Extend'ed
Height: Quad
Width: Single
~

16 - OUTPUT DATA BITS

1\

K

......

READ't'

16-DATA/ADDRESS BITS

J

CYCLE REQUEST

\I)

DRVll-B
DMA
INTERFACE

it

FUNCTION

USER'S
110
D'EVICE

I.........

STATUS BITS

."

-'

BUSY
CONTROL. BlfS

BUS CONTROL
J

16-INPUT DATA 81TS

,

Figure 1. DRVII-B Interface Diagram

DESCRIPTION
The DRVll-B is a general .purpose Direct Memory Access (DMA) interface
used to transfer data directly between the LSI-ll system memory and an I/O
device as shown on Figure 1. The interface is programmed by the processor
to move variable length blocks of I6-bit data words to or from specified locations in, memory by means of the LSI-ll bus. Once programmed, no processor intervention is required. The DRVII-B can transfer up to 250K, 16bit words per second and is capable of operating in burst modes, with byte
addressing. The control structure also allows read-modify-restore operations.

The interface consists of five registers: Word Count Register (WCR), Bus
Address Register (BAR), Control Status Register (CSR), In'put Data Buffer
Register (IDBR), and Output Data Buffer Register (OOBR). The module also
includes bus transceivers and logic for interrupt requests, address control
and protocol, and DMA requests.
The DRVll-B contains one switch bank used to assign an appropriate device
address to the DMA interface and one switch bank to select an interrupt vector address in the LSI-ll memory where the DMA routine is stored.

138

4>

DMA INTERFACE

I---llli-1

INC ENB H /

~L

lwe INC ENB

BU"
TRANSCEIVERS

AT

ID

I'"
a!
C")

~~
u.... ,
;[

~
....

8U~.IYT
"'Q'..
8aft

I

BIAK"

I

t

USER'S
1/0
DEVICE

L---

ERROR!DAIS!
NEXloA14'
L..... ATTEN (DAI3

VECTOR
ADDRESS
SaEOOR

~

H

\OUTPIlT MtAOO-!5 OUT H :~

AlA

DEVICE
ADDRESS
SELECTOR

w

MAINT~

~S~1109
CiCLfjDA08!
REAOY~

PIE (OA061

l.

READY H

fNCT1.2.3 H

CONTROL
STATUS
REGISTER
(CSRI

ATTEN H
STATUS A.B.C H
CYCLE REQUEST H

=MD16.17

INTERRUPT
LOGIC

:::i
~

t----

1

~
GO (OAOOI

~H

I

IN
BDOUT L
BDMR L
BSACK L '
BDMGO L

mtVT
"'iOMGfL

BIrnIIL

v

BSYNC L

.I

AOO H

T Ali.

I
i - - - - - - - - - - . . J - c8::T~OL
LOGIC

.'

-

CO H

IN H

Two 40-pin connectors, mounted near the edge of the module, facilitate the
connection of the I/O device with the DMA, using any two of several cable
assemblies available from DIGITAl. The module may be inserted into any
available slot of the LSI-II backplane or backplane extenders according to the
rules and restrictions, as described in the LSI-ll, PDP-ll/03 User's Manual.

REGISTERS
Each of the five registers can be addressed by the processor. The IDBR and
ODBR' are assigned the same address, and are read-only and write-only,
respectively.
The register bit format and functions are described as follo~s.

Word Count Register (WCR)
ADDRESS

I

o

15

READ/WRITE

·xxxxo . l..l'---=--_-'-_-_-_~'-_-_-_L...::~)'r_..._-_--'=-._ __-_L.._-_-_....
_-~.::.--'-_-_-

_~-

_.L._-_-_
...._-_-_-'_-_-_-

_L.._-.. . ,---'.

_-_-'-_-_-_-'_c-_-_-

16 BITS COUNTER

* All

logic' "ones" decoded by bus
master to assert BBS7 L signal

The WCR is a 16-bit read/write counter which is loaded by the program with
the two's complement of the number of words or bytes to be transferred
at one time between memory and the I/O device. At the end of each transfer, the WCR is incremented. When the count becomes zero (all 16 bits
0),
the DMA generates an interrupt request. The cohtents of the WCR can be
monitored by the processor program.

=

Bus Address Register (BAR)
15

14

12

9

11

o·

6

I.

AOORESS

·xxxx2

• •

0-1 8

I .

• •

•

I

'-----..-------'-----..------- '-----..-------'-----..------- '-----..------. 0-78

0-7
8

0-7
8

0-7
8

0-7
8

*AII logic "ones" decoded by bus
master to assert BBS7 L signal

The BAR is a IS-bit read/write register used to generate the bus address
which specifies the location to or from which data is to be transferred. The
register is incremented after each transfer. It will increment across 32~
boundary lines via the extended address bits in the control status register.
Bus address bit 00 is driven by t~e user device.

Control and Status Register (CSR)
15

14

13

12

11

10

9

6

3

• All logic "ones" decoded by bus
master to assert BBS7 L signal

The GSR contains 16 bits of~nformation used to c,9ntrol the function and
monitor the status of the DMA transfers. The information in the CSR can be
modified or read by the processor program in either S-bit bytes or 16-bit
words. Table 1 lists and defines each of the· 16 bits.
140

BIT

15

14

13
12

11
10

09

08
07

06

05"

04
03

02
01
00

Table 1
NAME
Error
(Read Only)

Control Status Register Bit Description
DESCRIPTION
1. Indicates a special condition.
a. NEX (bit 14)
b. ATTN (bit 13)
2. Sets READY (bit 7) and causes interrupt
if IE (bit 6) is set.
3. Cleared by removing the special condition.
a':'NEX is cleared by writing to zero.
b. ATTN is cleared by the user device.
NEX
1. Non existent memory indicates that as bus
(Read/Write Zero)
master, the DRVll-B did not receive
BRPLY or that a DAlIO cycle was not completed.
2. Sets Error (bit 15).
3. Cleared 'bY INIT or ~ writing to zero.
1. Indicates the state of the ATTN user signal.
ATTN
(Read Only)
2. Sets Error (bit 15).
MAINT
1. Maintenance bit used with Diagnostic Pro(Read/Write)
gram.
1. Device Status bits that indicate the state
STAT
(Read AOnly) )
of the DSTAT A, B, and C user signals.
STATB
2. Set and cleared by user control only.
(Read Only)
STATC
(Read Only)
CYCL
1. Cycle is used to prime a DMA bus cycle.
(Read/Write)
1. Indicates that the DRVII-B is able to acREADY
}
(Read Only)
cept a new command. Requests an interrupt if IE (bit 06) is set.
2. Set by INIT.
IE
1. Enables interrupts to occur when READY· .
(Read/Write)
(bit 07) is set.
2. Cleared by INIT.
XAD 17
EXTENDED Address bit 17, cleared by INIT.
(Read/Write)
XAD 16
EXTENDED Address bit 16, cleared by INIT.
(Read/Write)
1. Three bits made available to the user deFNCT 3
)
(Read/Write)
vice. User defined.
FNCT 2
2. Cleared by init.
(Read/Write)
FNCT 1
(Read/Write)
GO
1. Causes "NOT READY" to be sent to the
(W~ite Only)
user device indicating a command has
been issued. Clears READY (bit 07).
Enables DMA transfers.
141

Input Data Buffer Register (IDBR)
8

15

• ADDRESS
·XXXX6

I __
~.

o

7

,!t 8 BIT IDW BYTE
L-~__J-~~-L__~~__~__~-L_ _~~_ _~_ _~~~

8 BIT HIGH BYTE '

\~----------------------~~----------------------~
16 BIT DEVICE INPUT DATA WORD

-All logic "ones" decoded by bus
master to assert BBS7 L signal

The IDBR is used for read-only operations. Data is loaded into the register by
the user's device: The data may be read from the IDBR as a 16-bit word, an
S-bit high byte or an S-bit low byte. Transfers are usually via DATO or DATOB
DMA bus cycles. The register input connects to J2 mounted on the module.
Output Data Buffer Register (ODBR)
o·

15

ADDRESS
·XXXX6

8 81T LOW BYTE

8 BIT HIGH 8YTE

16 BIT DATA WORD

·AII logic "ones" decoded by bus
master to assert BBS7 L signal

The ODBR is used during write-only operations. Data from the LSI-ll bus is
loaded into the register ur.1er program control and read from the register by
the user's device. The register ..can be loaded with a 16-bit data word or with
an S-bit high byte, or as an B-bit low byte. Transfers are usually via DATI or
DATIO DMA bus cycles. The output of the register connects to Jl on the
module.
' . ,
DEVICE AND VECTOR ADDRESS SELECTION
The address of the DRVll-B interface and the interrupt vector address in
memory is selected by the position of the switches in switch bank 51 and
52, respectively. The location of the switches on the module is shown on
Figure 2. The switches are set to the OFF position (open) to select a zero
bit in the address format and the ON posftion ,(closed) to select a one.
Device Address Format
The DRVll~B decodes four address, one for each of the registers listed:
Register

Octal Address

WCR

*XXXXO
*XXXX2
*XXXX4
*XXXX6

BAR
C5R

DBR

o

('\

~c:J~
1 2 3 4 5 6 78 9 10

~c:J

0000000000

\

DEVICE ADDRESS

12345678

00000000
»

VECTOR ADDRESS

Figure 2

Connector and Switch Locations

Normally, the addresses assigned to the DMA start at 7724108 and progress
upward. Switches 51-1 through 51-10 select the base address as indicated
by the X portion of the octal code and the individual registers are decoded
by the DMA interface. The,relationship between the address format and the
switches are shown on Figure 3.
.

I I
'------''------''------''------' '-----'
6 OR 78

0 - 78

0 - 78

0 - 78

REGISTER 5elECT--.J
ByrE CONTROL

• • All lOGIC"ONES" DECODED BY PROCESSOR
AS BBS7-l SIGNAL

Figure 3

.

Device Adtlress Switch (51) Selection·

143

Interrupt Vector Address Selection
The interrupt vector addresses for the LSI·ll systems are allocated memo
ory locations from 0.7748. The recommended location "'-assigned to the
DRYll-B is 1248 • Switches S2-1 through ~2-8 are used to select the octal
address and the relationship between the switches and address format is
shown on Figure 4.
09

08

06

05

03

02

IS2-'ls2-2,s2-3,S2-41~2-5,52-6 ,52- 7 152-8 ,

00
.,',

•

I

~~~

o OR I

0-78

0-78

OOR4i1

• =PRE ASSIGNED AS ZERO

Figure 4

Interrupt Vector Address Switch (S2) Selection

FUNCTIONS'
The DRVll.'8 interface ooerates as both a slave and master device. Prior to
becoming bus master, all Data Transfers Out (DATa) or Data Transfer In
(DATI) are in respect to the processor. Once DMA is granted bus mastership
by the processor, all data transfers are in respect to the DMA.
DMA operation is initialized under progr-am control by: .(1) loading the WCR
with the two'~ complement of the number of words to be transferred; (2)
loading the BA"R with the first address to or from which data is to be transferred; (3) loading the CSR with the desi~ed function bits. After the interface
is initialized, data transfers are under control of the DMA logic.

Program Control Tran$.fers
Data transfers may be performed under program control by addressing the
IDBR or ODBR and reading or writing data.
DMA Control Transfers
DMA input (DATI) or output (DATO) data transfers occur when the processor
clears READY. For a DATO cycle (DRVll-B to memory transfer), the user's
I/O device presets the CONTROL BITS [word count increment enable (WC
INC ENB), bus address increment enable (BA INC ENS), CI, CO, AOO~ and
ATTN], and asserts CYCLE REQUEST to gain use of the LSI-ll bus. When
CYCLE REQUEST is asserted, input data is latched into the input DBR, the
CONTROL BITS are latched into the QRVll-B DMA control, and BUSY goes
low. A DATI cycle-memory to DRVll-8 transfer-is handled in a similar
manner, except that the output data is latched into the output DBR at \he
end of the bus cycle.

When the DRVll-B becomes bus master, a DATO 'or DATI cycle is performed
directly to or from the LSI-ll memory location specified by the BAR. At the
end of each cycle, the WCR and BAR are incremented and BUSY goes high
while READY remains low. A second DATa or DATI cycle is performed when
the user's I/O device again asserts CYCLE REQUEST. DMA transfers will
continue until the WCR increments to zero, at which time READY goes high
and the DRVll-B generates an interrupt (if interrupt enable is set) to the
LSI-ll processor.
If burst mode is selected (SINGLE CYCLE low), only one CYCLE REQUEST
is required for the complete transfer of the specified number of data words.

144

DEVICE CABLES AND SIGNALS
Data, status and control signals are transferred between the user's I/O device
and DMA by an input and an output cable assembly. The input cable attaches
to connector J2 and the output cable attaches to connector Jl as shown on
Ffgure 2. Table 2 and 3 list the connector pin and designations for each
signal. Table 4 lists several recommended cable .assemblies that are available from DIGITAL in the lengths indicated. The H856 female connector mates
with either Jl or J2 on the DRVll-B. To order cable assemblies in lengths
not listed, contact a DIGITAL sales office.
GENERAL SPECIFICATIONS
Module Size
Quad-height, single-width, extended-length
__
_
_
Dimensions
8lh in. l, 10lh in. H, lh in. W(21.6 cm L, 26.7 cm H, 1.27 cm W)
Weight
o

13 oz. (370 gr.)

User I/O COrinections
Two 40-pin connectors
Table 2

Input Connector Signals

J2·
Connector Pin_
'B
D
F

J-

~}
N
R
T
V
D~

FF

JJ

lL
NN

RR
IT
VV
CC

EE
HH

KK

MM
pp
S5
UU

•

signai Name

Unit L-oads

BUSY H
ATTN H
AOO -H
BA INC ENS H

10 (drive)
1
1
1

FNCT 3 H

10 (drive)

o-

CO 4
FNCT 2 H
Cl H
FNCT 1 H
08 IN" H
09 IN H
10 IN H
11 IN H
12 IN H
13.. IN H
14 IN H
15 IN H
07 IN H06 IN H
05 IN H
04 IN H
03 IN H
02 IN H
01' IN H
00 IN H

1
10 (drive)
1
10 (drive)

}
1

·AII remaining pins connect in common to logic ground by board etch .

145

/

Table 3

Output· Connector Signals

Jl·

een..r_Pln

Sigmtl Name

B'

CYCLE REQUEST H
INIT V2 H
INI H
WC INC ENB H
SINGLE CYCLE H
STATUS A
READY H
STATUS B

0
F

J

K
l
N
R

~}
DO
'F
JJ

STATUS C

II

_N·
Rft
11'
W
CC

E£
HH
KK
MM
pp
S5
UU

III

Unit Loads

..

DB
09
10
11
12
13
14
15
07
06
05
04
03
02
01
00

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

1

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

All remaining pins cORnect in common to logic

1
10 (drive)
10 (drive)
1
1
1
10 (drive)
1·

10 (drive)

~und

by board etch.

,.

HAVE YOU SEEN THE DIRECT SALES CATALOG?
For USA customers, DIGITAL's Direct Sales Catalog puts the world of computers and computer-related accessories as close to you as your telephone or
mail box. All of the microcomputer products described in the Logic Handbook
are offered through the Direct Sales Catafog. and most are available for immediate shipment. To get your free copy, call toll-free, 8:30 AM to 5:00 PM
Eastern time, 800-258-1710.
From New Hampshire locations, or places outside the continental U.S., call
Merrimack, 603-884-6660.

, 146

Table 4

~ommended

Cable Assembl~es

Cable No.

Connectors

Type

Standard Lengths (ft.}

BC07D-XX
BC08R-XX
BC04Z-XX

H856 to open end 2,20 conductor ribbon 10, IS, 25
H856 to H856
Shielded flat
1,6, 10, 12,20,25,50
H856 to open end Shielded flat
6, 10, IS, 25, 50

Mounting Requirements
Plugs directly into LSI·l1 backplane or LSI-l1 expansion backplane.
Eled:rical
Logic Power Requirements:

+5 V ±5% @ 1.9 A (nominal)

LSt·ll Bus Loading
Presents one (1) bus load
User Loading
Input Data Li nes:

1 TTL unit load each
HIGH = logic one
LOW = logic zero

Input Control Lines:

1 TTL unit load each
HIGH = logic one
LOW = logic zero

Output Data Lines:

~O TTL unit loads (drive) each
HIGH = logic one
LOW = logic zero

0utput Control lines:

10 TTL unit loads (drive) each

HIGH= logic one
LOW = logic zero

Module Type
M7950 '
Operational'
Transfer Mode:

DMA or program-controlled without interrupts

Data Transfer«-

Up to 250,000 16-bitwords per second

Environmental
Temperature:
Relative Humidity:

Storage: ,_40° to 66°C (-40° to 150°F)
Operating: 5° to 50°C (41 ° to 122~F)
10% to 95% non-condensing

147

/

· .

lSI-II

DRVI1-P

BUS FOUNDATION MODULE

M SERIES

Length: Extended
Height: Quad
Width: Single
DRVll- P
FOUNDATION
MODULE

r-----,

I
16-DATA/ADDRESS BITS

-

"'"

BUS
J
TRANS- J
CEIVERS I

I
J

~

USER

STATUS/CONTROL

-- - --I DESIGN
I lOGIC

USERS
I/O.DEVICE

I

'"

BUS CONTROL LINES

"'"

BUS

I

CONTROL I
LOGIC

I
J

I

I

Figure 1.

Typicaf DRV11-P Interface

DESCRIPTION
The DRVll-P is a versatile wtre wrap module that contains the bus interface
logic for operation with the [SI-11 or PDP-ll/03 system and provides adequate board area for mounting and connecting integrated circuits (IC's) or
discrete components. Because the bus interface logic is included, the module can be efficiently configured by the· user to satisfy a variety of device
interface logic applications.
A 40-pin connector, conveniently mounted at the board edge, facilitates the
connection to a device through several cable assembly types available from
DIGITAL.
Except for the bus interface connections, all signals and voltages' are ter-minated to wire wrap pins for user connections. The bus control logic is
provided with wire wrap test points for monitoring the internal signals. The
test points are spaced at 0.1 in. (.254 cm) between pins to· allow a 40-pin
connector to be inserted over the wire ~ pins for automated test functions.
Approximately 2/3 of the surface area on the module consists of platedthrough holes, each connected to a wire wrap pin. The user-can mount three
different types of dual-in-line Ie's or a variety of discrete components into
the holes and connect the proper voltages and signals by wire wrapping
leads on theboard.
.
The DRVll-P module can be inserted into anyone of the available interface
option locations of the [SI-ll, PDP-ll/03 backplane, or backplane extender
unit. The module occupies four vertical slots. Refer to the [SI-11, PDP-ll/03
User's Manual for detailed installation information.

148

I
LSI-ll BUS FOUNDATION MQ.,DlJLE

1""':!!:,,'" K."'''' .... ~

DATA/ADDRESS IBDALOOL - BDALlSLT

z

;:

~
~

DEVICE DATA DOOH- DISH

+3V
SOURCE

-

3«
~

BBS7 L

+JV
SOURCE

-

0
0

I'"
."

~

~
0
0
«
0<
Q

BDOUT L
BSYNC L
BOIN L
BWTBT ~
RIIPIV

~I

~~
~
~~
0<

l!i!<>'

-=- -

,~
ii:

~

....-.. J
0<

~~

l!i!a..
§:

I

PROTOCOL
CONTROL
LOGIC

~

."

VECTOR H

U

SEL DEVOL
SEL DEV 2 L
SEL OEV 4L
SEL DEV 6 L
INWD L
OUT HB L
OU LB L

r

~

~Z

_

l:;!iI:
~

II[
«

INTERRUPT
CONTROL
LOGIC
ENB
,UK AH

•

~~~

It

I

r-

,Z

-

~'"

l!i!~

i

-

~

-=-

."

Z
""-

INL
--c: ..~~~

Lf>o.llilT O.Jj"

CLKBH

~----

.Z

-

l:;!ii:l:;!ii:

RQSTA H
ENB DATA AH
RQST B H
ENB DATA BH
VEC RQST B H
IN
ENRA ST H
ENB 8 ST H

~

~o:

CS~?TS ~Ih
i", I."
AD~e"
'-.rVDJ- 7

BOMGO L
BOMGI L

r--

~'"
·z

IlSTAT S/CONTROL BITS

VECTOR

BIRQ L
BIAKO L
81NIT
BIAK

1

ENB H

DEVICE
ADDRESS
COMPARATOR

"

lrl

~

DOOH-D02H

:x:

..

~i

II>

00"-''''"

[

~

.--

--

,--.,

li.!

~

WIRE WRAP PINS
USER IC/<:OMPONENT MOUNTING AREA

149

-

I

--------~

TO USER'S
DeVICE
CABLE

FUNCTIONS
The DRV11-P contains 16 bus transceivers, device selection and vector
address generation logic, 'interrupt control, and control and status register
functions. The device data inputs and outputs of the bus transceivers and the
device control signals are made available to user to complement control of
up to four 16-bit registers.
Address Selection logic
The address selection logic consists of a device address comparator and the
protocol control logic. Up to four discrete addresses are made available
with the existing logic on the DRV11-P and can be assigned to data registers,
status and control registers, or word counters. By adding additional IC's, the
user can increase the total number of addresses available. The main address
of the DRVll-P is selected by monitoring the BBS7.bus line and decoding
the address information 003-012 from the bus. The main device address
is assigned by the configuration of jumper leads (A03-A08) attached to wire
wrap pins. When the selected and input bus addresses are the same, the
device address comparatory provides an ENB H level to the protocol control
logic. The protocol control logic receives bus signals and address bits 001·
002 to assert one of the four available output lines-SEL DEV 00, SEL OEV
2L, S'EL DEV 4L, and SEL DEV 6L. In addition, the protocol control logic
provides output signals to specify word or byte transfers.
Table 1 lists and defines the function of the control signals required or
available for the user logic.

Table 1
Signal
SEL DEV
SEL DEV
SEL OEV
SEL DEV

Protocol Control logic Signals
Function

OL
2L
4L
6L

Select Device 0 through 4-0ne of four lines asserted by
decoding the device address and available to select one
of four user word registers.
"

OUT LB l
OUT HB L

Out Low Byte, Out High Byte--:-Used to load (write) data
into low byte (8 bits) or high byte (8 bits) or both bYtes
(16 bits) of the selected word register.

IN WD L

In Word-Used to gate (read) data from the selected
word register to the bus. I

The format for the device address se.lection is shown on Figure 2. A logic
one_is specified when no jumper. lead is installed between the appropriate
wire wrap pin from A3-A12. A logic zero is specified when a jumper lead is
installed.

Figure 2.

De:,ice Address Selection

- 150

Interrupt Control Logic
The interrupt control provides the circuits necessary to allow a program'interrupt transaction between the lSI-II and device. Two interrupt channels
(A and B) are available to the user with channel A assigned the highest
priority. Table 2 lists and defines the user available signals associated with
the interrupt oontrvl logic.
Table 2
Signal
RQST A H

ENB DATA A H

ENB elK A

ENB A ST H
RQST B H
ENB DATA B H
ENB ClK B
ENB B ST H

Interrupt Control Logic Signals

Function
Interrupt Request A-Asserted by device logi~ and sets
the channel A Interrupt Request flip-flop when the
channel A Interrupt Enable flip-flop is set.
Interrupt Enable A Data-Asserted by device logir. and
sets the channel A Interrupt Enable flip-flop when the
ENB ClK A signal is asserted.
Interrupt Enable A Clock-Asserted by device logic to
cause the channel A Interrupt Enable flip-flop to be
set when ENB DATA A signal is asserted.
.
Interrupt Enable A Status-Indicates the status of the
channel A Interrupt Enable flip-flop.
Jqterrupt Request B-Same as RQST A H signal except
controls channel B interrupts.
Interrupt Enable B Data-Same as 'ENB DATA A H
signal except controls channel B interrupts.
Interrupt Enable B Clock-Same as ENB ClK A signal
except controls channel B interrupts.
Interrupt Enabl~ B Status-Same as ENB A STH except controls channel B interrupts.
.

VECTOR H

Interrupt· Vector Gate-Used by device logic to gate
vector address onto the bus and to generate B 'RPlY
signal.
-

VEC RQST B H

Vector Request-Asserted by device logic to specify
that channel A vector address is require\d; negated to
specify channel B vector address is required.

INIT 0 L

Initialize Out-Buffered B INIT l signal from bus used
for general initialization.

Vector Address and CSR Logic
The vector address logic is used in .conjunction with the interrupt control
logiC to generate a vector address on bus lines BDAL OOL-BOAL 07. The
vector address is specified by the user and selected by installing jumper leads
between wire wrap pins on the M7948 module. The addresses available are
from 000 8 to 3748 , The vector address range can be increased from 000 8 to
7748 with additional log«: and wiring.
When the VECTOR H signal is asserted as a result of a ~evice interrupt request, the vector address is placed on the bus lines.
Wi!e wrap pins V3 through V7 are used to assign the vector address. A
jumper lead installed selects a logic "zero" address bit for its associated
line and no lead selects a logic "one" address bit according to the format
on Figure 3.

151

)

BOAL L

I

07

V7

06
I

05

V6·1 Vs

~
0-3 8

03
I

V4

I

V3

I

02

011

00
I

•

I

•

I

'----.-----''----.-----'
0-78

0 OR 48

*: PRESET BY M7948 TO 0 81T

Figure 3.

Vector Address Select Format

Bit BDAL 02 L can be connected to the device interrupt request signal RQST
A signal to specify a separate vector address for channel A and channel ~.
Status and control information can be multiplexed through the same logic
used to generate the vector address. Up to eight status and control bits can
be assigned by the user and transferred to bus lines BDAL 00 L·BDAL 07 L.
The information can be gated onto the bus lines using a select level generated by the address decoding logic.
COMPONENT MOUNTING AREA
Twelve vertical areas (A-L) are available on the. M7948 module for mounting
integrated circuits or discrete components as shown on Figure 4. Each area
has a double row of wire wrap pins that connect to an associated plated
through hole located at 0.1 in. (.254 cm) vertical spacing. Area A is for
multi-use and is capable of accepting IC's with pin centers at 0.3 in. (.762
cm), 0.4 in. (1.01 cm) or 0.6 in. (1.52 cm). Area K will also accept IC's with
pin centers at 0.3 in. or 0.4 in. All remaining areas will only accept IC's with
pin centers at 0.3 in.
Table 3 lists the total number of IC's with 0.3 in. spacing that can be mounted
in the user areas of the module, A through L.
Table 3

fC MOUNTING

IC Type

Total Number

14 pin
16 pin
18-pin
20 pin

60
52
44
44

Connector Wire Wrap Pins
The 36 contact pins in row C and 0 at the edge of the module connect to a
double row of wire wrap pins. These two rows are made available to the user
for connecting signals and voltages from the backplane to the user installed
logic circuits. The following pins of row C and 0 are normally dedicated to
+5V and GND.

152

0

~

0

~OUNTING

IC

AREA A

i~

,.

..,

~

IC MOUNTING

~REA

8

IC MOUNTING AREA C

n

ITEST

Ie MOUNTING

AREA 0

IC MOUNTING

AREA E

I

CONNECTOR PINS

I

~

~

ITO

I

EIS .

E13

IC MOUNTING AREA F

E16

IC WOUNTING AREA G

I

Ie MOUNTING AREA'H

I TEST CONNECTOR

I CJICJ CEO

ETO

--E7

I TEST
»

/,- D

I

PINS

E4

I

~

~

CONNECTOR PINS
ES

II

'=
::E
~
::E

Ie MOUNTI NG AREA
I

IC MOUNTING AREA
J

I
E6

I

K

'"~

~

."

'=

~

Ie MOUNTING AREA

~

~
n

"-

~

IC MOUNTING AREA L
El

, Figure 4

DO DO
DRVll·P Component MountingLocations

The user can- connect the power to the IC or components using the row C
and row 0 wire wrap pins.

+5V

CA2, DA2

GND

CJl, CMl, CTI
OJ1, OMl, OTI

CC2, DC2

153

Device Signa's
Input and output data, status and control signals can be transferred between
the device and the DRVll-P module using anyone of several cable assemblies listed on Table 4 and available from DIGITAL One end of each cable
is terminated with a 40-pin female connector which mates with the 40-pin
male connector J1 mounted on the M7948 module. The pins of J1 cOf\nect
to the user installed logic through a series of wire wrap pins.
\
Table 4

Recommended Cable Assemblies

Cable No.

Connectors

Type

BC07D-XX

H856 to open end

BC08R-XX

H856 to

2. 20 conductor
ribbon
Shielded flat

BC04Z-XX

H856 to open end

H85~

Shielded flat

10,15,25
1, 6, 10, 12, 20,
25,50,75,100
6,10,15,25,50

GENERAL SPECIFICATIONS
Bus Input loading: "
Presents a maximum of one unit load on the
lSI-ll bus.
Operatirtg Temperature:
5°C (41°F) to 50°C (122°F)
10% to 90%, without condensation
Relative Humidity:
+5
V at 1.0 A Emax); user logic not included
Power:
10.5 in. (26.67 cm)
Quad heightSize
Single width0.5 in. ( 1.27 cm)
Extended iength- 8.5 in. (21.59 cm)
OPTIONAL EQUIPMENT
Integrated Circuits (ICs)
Two special ICs are available from Digital Equipment Corporation for use in
configuring custom interlaces with the DRVll-P.
DEC8640 Bus Receiver IC (Quad 2-lnput NOR Gates)~956
•
The 956 is a package of ten 14-pin, dual-in·line package (DIP) DEC8640·
in"tegrated circuits (lCs). Each IC comprises four 2-input NOR gates. Each
A + B. The DEC8640 gates are
gate performs the Boolean function X
especially suitable as Unibus or lSI-ll bus receivers because of their high
impedance characteristics and, hence, minimal loading on the bu~.

=

These NOR gates are described in detail in the HARDWARE! ACCESSORIES
CATALOG published by Digital.Equipment Corporation.

DEC8881·1 Bus Driver IC (Quad 2-lnput NAND Gates)-957
The 957 is a package often 14-pin, dual-in-line package (DIP) DES8881-1
integrated circuits (ICs). Each IC comprises four 2 input NAND gates. Each
gate performs the Boolean function X
AB. The DES8881-1 ICs are especially suitable as Unibus or lSI-ll bus drivers b.ecause of their capability to
sink 70 mA with a collector voltage of less than 0.8 V.

=

These NAND gates are described in detail in the HARDWARE/ ACCESSORIES
CATALOG published by Digital Equipment Corporation.
• DEC8640 IC replaces DEC380 IC.

154

KPVII-A Power Fail/Line
Time Clock Generator

LSI-II
M SERIES

Length: Extended
Height: Double
Width: Single
DESCRIPTION
The KPVll-A Module (M8016) is an lSI-l1 power fail/restore signal sequence
and line time clock (lTC) generator. (See Figure 1). It is compatible with all
lSI-ll component systems and lSI-l1 backplane options. The KPVll·A is
designed for instaUation in any lSI-ll bus-structured backplane or remote
installation· (not installed in a backplane) via an optional cable which connects the option to the lSI-II backplane. An optional console panel (DEC
Part No. 54-11808) is available for manual control of l TC and power signal
generation and display of DC power on/off status and processor run/halt
state.
FEATURES
Automatic generation of BPOK and BDCOK power-up/power-down signal sequence.
Automatic program restoration and starting when used with non-volatile memory and appropriate software routin~s.
The built-In line time clock is program compatible with the KWll·l. The
KPVII-A is factory-configured for linEt clocK Status (lKS) register address an.d
operations.
'
/ Line time clock time reference can be provided by a signal source (user
supplied) other than the power line_
Can be installed in the lSI-It backplane or mounted remotely. An optional
cable connects the KPVll-A to the LSI-ll backplane when mounted remotely.
Expandable with the 54-11808 console panel option.

HAVE YOU SEEN THE DIRECT SALES CATALOG?
For USA customers, DIGITAL's Direct Sales Catalog puts the world of computers and computer-related accessories as close to you as your telephone or
mail box. All of the microcomputer products described in the logic Handbook
are offered through the Direct Sales Catalog, and most are available forimmediate shipment. To get your free copy, call toll-free, 8:30 AM to 5:00 PM
EasterQ time, 800-258-1710.
From New Hampshire locations, or places oytside -the continental U.S., call
Merrimack, 603,884-6660.

..

155

KPVll-A
(M8016!

LSI-11
SYSTEM
COMPONENTS
(PROCESSOR,
MEMORY,
PERIPHERAL
INTERFACE
MODULES,
, ETC.)

BBS? L
BSYNC
BOIN L
BOOUT
BINIT
BEVNT

L
L
L
L

POWER
SIGNAL
SEQUENCE
CKT

r
REMOTE
REMOTE
SIGNAL
DC ONI
~ONNECTOR
OFF
(OPTIONAL)

Figure 1

KPVII-A System Interface

CONFIGURING LTC JUMPERS
LTC jumpers are located on the M8016 module as shown in Figure 2 and
are factory-configured for programmable operation with the LKS register
address (177546) as shown in Figure 3. Normally, it will not ~ necessary to
reconfigure LTC jumpers; however, it is possible to alter LTC operation as
Usted below and the LKS deviee address as shown in Figure 3.

Jumper
W12

W13

W~4

W15

Installed

Removed

Enable manual control or·
continuous LTC interrupt request operation. Do not install when W13 is installed.
*LTC interrupt requests can
be·.enabled and disabled by
program. Do not install when
W12 is installed.
*Console (optional) LTC ON/
OFF switch enabled.
'" LTC signal occurs at the
power line frequency.

*Disable continuous or manual
operation.

• Factory-jumper:ed configuration.

156

LTC interrupt requests canriot be program controlled.

Console LTC ON/OFF switch·
disabled.
LTe frequency is determined
by an external source via EXT
TIME REF ~tched pad on
module.

EX CL
REM DC
+i2V

o
WI4

JI

+5V
GND

W15

W12

WI1

• = MAY USE 4-40 HARDWARE

Figure 2

KPVll·A Jumper, Connector, and Pad Locations

157 .

, BIT

~~r---r---r---r---r---r---~~~~~--~--~--~--~--~--'-~PREFERRED
ADDRESS
I - -__~--~--~.._.l-T"'"".I-.._.l-_r_.l-.._.L..-_r_..I.-.,__..I.-.,__..I.-.,__..l-.,__..I.....--..l---..I.....---J (1775461

BANK 1 ADDRESS
(BSS1 L ASSERl'EO)
AODESS JUMPER WI

W2

I

I

I

I

Figure 3

W3

W4

I

1

I

I

W5

I·

I

W6

1

R

W1

I

I

KPVll·A Device Address

KPVll·A MODULE
BACKPLANE

W8

1

t

W9

1

R

Wl0

/.

I

R FACTORy JUMPER CONFIGURATION
t • INSTALLED ·'1'
F! • REMOVED' '0'

(~KS'Register)

Jumpers

INSTALLATlO~

The KPVll-A module can be installed in any LSI·II structured backplane,
such as the H9270 and DDVII-B.

REMOTE LOCATION
Mounting holes are provided in the KPVII-A module for remote location installation. (See Figure 4 for mounting details)

4 EACH 4-40 PAN-HEAQ SCREW'5.lOCt(WASHERS.
FI.AT WASHERSITYPICAl)

0$6(:1n

(7I"S2inJ

4 [ACH 1.02c:1ft '1/4)
LONG (MINIMUM. SPACERS

--0

(4 PLACES)

Figure 4

KPVII·A Remote Installation

NOTE
Program control of the LTe function is not possible when remote installation is used, However,
manual control is available using the optional
control panel.

158
j

The KPVll-A is electr,cally connected to the lSI-II bus using an optional
signal cable, (DEC Part No. 70-12754).' This cable is inserted into the 10 pin
connector on H9270 or DDV11-B backplane. (See Figure 4).
The +5V and +12VDC voltage sense input must be provided by the user
when the KPV11-A is not installed in the lSI-II backplane. Figure 2 illustrates
the location of etched pads provided for the purpose of voltage connection
to .the module.
Power Sense Connection
The user is required to supply the 24Vac center tapped, 50 or 60Hz input
voltage necessary to produce the DC oper~tion voltage for the option. In
addition, this voltage provides the 50 or 60Hz reference for the LTC function,
and is the power fail monitor signa~ for the power signal sequence circuit.
, Illustrated in Figure 2 is the location of three tabs on the KPVII-A module
provided for voltage conne~tion.
CONSOLE PANEL
Electrical connections ~tween the KPV11-A and the console panel are made
via 16-pin dual-in-line integrated circuit sockets· located on each' assembly.
The electrical connection between the sockets is made using a signal/power
cabre (DEC Part No. 70-S8612).

In addition to the LTC ON/OFF and RUN/ENABLE switch functions, the 'Console panel includes a DC ON/OFF switch. This switch, when in the OFF
position, disables BoeOK Hand BPOK H signal generation. If, desired, this
switch can- also control the DC On/Off state of the user's power supply if it
is capable of being controlled py a T2l Signal.
Use of External Time Reference
The KPV11-A normally uses the 50 or 60Hz input (via the three power tabs
on the module) for LTC signal generation. However, an external TTL logiccompatible frequency source may be used for producing LTC signals at frequencies other than the power line frequency. An etched pad is provided
for this purpose on the KPVII-A module.
LTC PROGRAMMING
The lSI-II program communicates with the LTC function via the lKS register
(Figure 5) contained in the KPVll-A logic circuits. The lKS register's'device ad~ess is normally configured to 177546 for system software compatibility.
KCSR (177546)

-.,.--r---r--~-_r_-~;;.....,......;..._r_~.---.....-...._-....____r_-...,....;;.;;....,

r--"5...,..-_-

BIT

(READ/WRITE BIT)
MONITOR
SET TO "I" BY LINE FREQUENCY CLOCK
SIGNAL, CLEARED BY PROGRAM.
(RfAD/WRITE [CLEAR-ONLY) BIT)

Figure 5

Une Time Clock Status Register (lKS)

LTC interrupts, when enabled (lKS bit 06 = I), occur as an interrupt request (bus ·Iow assertion) on tl)e BEVNT, l Signal line. This causes the processor to execute a service routine via vector address 100. Memory location
100 must contain the PC (starting address) for the l Te service routine;
159

similarly, memory location 102 must contain the PS (processor status word)
for the service routine. As with a/l "external" interrupts, the LSI-ll processor will recognize the LTC interrupt request only when the current PS bit
07 is cleared. When PS bit 07 == I, external interrupts, including the LTC ,interrupt, are ignored. The LTC interrupt has highest priority of all external
interrupts and does not require a vector address bus transfer. An interrupt
request via the BEVNT L bus signal line, as previously stated, always results
in access to the service routine via vector address 190.
CONSOLE OPERATION
The con'sole panel option* controls and indicators are shown in Figure 6
and described below:

Control I
Indicator
DC ON

Type

Function

LED indicator

Illuminates when the DC ON/OFF toggle
switch is set on ON and proper dc output voltages are being produced by the
user's Rower supply and sensed by the
KPVll-A.

I

RUN

LED indicator

Spare

LED indicator

DC ON/OFF

Two-positlon
toggle switch

ENABLE/
HALT

Two-position,
toggle switch

LTC
ON/OFF

Two-position
toggle switch

If either the +5 V or +12 V output
from the power supply is Low, the DC ON
indicator will not Uluminate.
Illuminates when the LSI-ll processor is
,in the run state (see ENABlE/HALn.
When set on ON, enables the dc outputs
of the user's power supply (if connected
for this function--see instructions for
installing the console panel). The DC ON
indicator will illuminate if the dc output
voltages are of proper values.
When set to OFF, the power supply de
outputs are disabled and the DC ON indicator is extinguished.
When set to ENABLE, the 8 HALT L line
to the processor is not asserted and the
processor is in the run-enable mode
(RUN indicator is illuminated only when
. the processor is executing a ·program).
When set to HALT, the B HALT L line is
asserted. The processor' halts program
execution and executes console ODT
microcode. The RUN indicator is extin.guished.
When set to ON, enables KPVll·A generation of LTC interrupts.
When set to OFF, disables LTC interrupts
(W14 must be installed).

• When used in conjunction with the KPVll·A.

160

Figure 6

Console Panel, and Interconnection Cables

SPECIFICATION
Environmental
Operating temperature*:
Relative humidity:

5°C to 50°C (40°F to 122°F)
10% to 95% (no condensation)

* When operating at the maximum temperature (50°C or 122°F), air flow
must maintain the inlet to outlet air temperature rise across the module
to 7°C (12.5°F) maximum.
Electrical
Power requirements:
AC Ii ne voltage
monitor input:
DC operating power:

24 Vac with grounded center tap ±10%, 200 mA
+5 V ±5%, 560 rnA

Options
Model/Part No.
54-11808
~ 70-11656
70-12754-2F
70-08612-4 A

Description
Console
Console
Remote
Console

panel (PC assembly)
bezel
signal cable
signal/power cable

161

Power Signal Sequence Timing

•

~'----

AC INPUT

-lO-IOm.1-

I

BPOt( H

--....j

2-6m.

I--

I

BOCOK H

POWER SUPPLY
DC OUtPUT
VOLTAGES _ _~--'

T

POWER-UP
SEQUENCE

POWER-DOWN
SEQuENCE

Figure 7

Power Signal Sequence Timing

,

.J

HLT L

+5 V

DC PWR ON H

.~

N.C.

S SPARE 3

DC ON H

LTC 0lIl H

GNO

GND

N.C.

N.C.

N.C.

N.C.

N.C.

~.-.

N.C.

/

+5V

JI

B POf( H

B EVENT L

S SPARE 3

N.C.

GND.

SlPARE

SPARE

N.C.

DeDf( H

SHALT L

/

Figure 8 Remote Console (Jl)
and Backplane Sequel (J2) Connectors
162

KPVII-B POWER, FAIL/LINE
TIME CLOCK
GENERATOR/TERMINATOR

LSI·II
M SERIES

Length: Extended
Height:. Double
Width: Single

DESCRIPTION
The KPVll-B_ Module (M8016-YB) is identical to the KPVll-A except that
the -B includes 1200 (nominal) bus termination resistors. Bus terminations
are used when expanding the bus beyond the minimum system configuration
(8 single H9270 Backplane). Having the termination resistors on this module
rathelr than on a separate one optimizes use of bus slots, saving valuable
space.
\
Note that in order to use the bus-termination feature, this option must be
installed in the backplane. Mounting the module off the backplane leaves
the termination resistors out of the circuit.

163

DESIGNERS KITS
FOR CUSTOM INTERFACES

lSI-II
CHIFKITS

DCKll-AC CHIPKIT includes 6 LSI Ie chips, a wire wrappable board,
and an interface cable.

The DCKII series of proprietary LSI integrated circuits, developed by DIGITAL
for its own use, is now available to LSI-II users. These ICs, available in sets
called CHIPKITS, make design of LSI-l1 bus interfaces easier than ever. Prior
to these kits, a designer of custom LSI-l1 program control or Direct Memory
Access (DMA) interfaces l1ad two alternatives: modify a standard product or..
design from scratch. Now there is a third choice that will be the best in most
cases-the CHIPKIT. The kits contain the ICs needed to build the foundation
of nearly any LSI-ll interface, and are available either with or without a
DIGITAL wire wrappable board and plug-in cable. For volume users, the individual ICs are available in tubes of 18 of one type. <
The CH IPKITS minimize the chip count required to implement bus circuitry.
This permits the designer to build an interface foundation on the doubleheight wire wrappable board provided, and still have ample room left for his
special circuitry. The comparatively small chip count results in backplane
space savings, increased system reliability, lower system cost, and a greater
opportunity for value to be added by the CHIPKIT customer to the finished
product.
The CHIPKITS in this program are:

164

DCKll-AC

-Designers Program Control Bus Interface CHIPKIT, consisting
of:
DC003 Interrupt Chip
1
DC004 Protocol Chip
1
DC005 Transceiver/Address Decoder/Vector Select-Chips
4
W9512 Double-height, extended-length, wire wrappable
1
module
BC07D-10 ten-foot, 40-conductor plug-in cable
1
Program Control Bus Interface CHIPKIT, conSisting of the six
chips of the above DCKll-AC, but no module or cable.

These kits are ideal for building the foundations of program control bus interfaces to the LSI-ll. They are functionally similar to the DRVII·P Bus Foundation Module, an assembled, ready-to-use option described elsewhere in this
handbook.
DCKll-AD

Designers DMA Bus Interface CHIPKIT, consisting of:
1·
DC003 Interrupt Chip
1
DC004 Protocol Chip
4
De005 Transceiver/Address Decoder/Vector Select Chips
2
DC006 Word Count/Bus Address Chip~
1
OC010 DMA Control Chip
'\
1
W95I2 Double-height, extended-length, wire wrappable
module
BC07D·IO ten·foot, 40-conductor plug-in cable
I

DCKII-AB

DMA Bus Interface CHIPKIT, conSisting of the nine chips of the
above DCKll-AD, but no module or cable.

These kits are ideal for building the foundations of DMA bus interfaces to the
LSI-II. They are functionally, similar to the DRVI1-B General Purpose DMA
Interface Module, an assembled, ready-to-use option described elsewhere in
this handbook.

..

(

IMPORTANT NOTE ON DMA CHIPKITSThe two DMA Bus Interface CHJPKITS, DCKIIAB and OCKI1-AD, are new products being developed by DIGITAL, and are undergoing final
~pplications testing and review as of the publication date of this handbook-July, 1978. Production quantities are expected about 'October,
1978. If you have a serious interest in using
these CHIPKITS, contact us for the latest word
on availability. Write DIGITAL, Logic Products
Sales Support, MK 1-2/E13, Merrimack, NH
03054, or call us at the telephone number below.

Detailed speCifications of the CHIPKIT components, together with applications suggestions, are in the CHIPKIT Preliminary Applications Note which
follows.
Additional Information
learn more about CHIPKIT applications, pricing, etc., call DlGITAL's tollfree Hot Line, 8:30 AM to 5:00 PM Eastern time: 800-258-1710. From New
Hampshire locations, or places outside the continental United States, call
Merrimack, 603-884-6660.

10

165

LSI·11

CHIPKIT APPLICATIONS NOTE
(PRELIMINARY)

CHIPKITS

":~'.

~t

;

....,.-~

This Applications Note contains desciptions, specifications, and circuit diagrams for the five integrated circuits available'in CHIPKITS for use in LSI-II
bus interfaces. The bus receiver and bus driver chips usually used with the
LSI-ll are also covered, and the W9512 wire wrappable module included with
the designers kits is described.

Bus Receivers and Bus Drivers
The- equivalent circuits of LSI-ll bus·compatible drivers and receivers are
shown in Figure 1. To perform the receiver and driver functions, DIGITAL
Equipment Corporation uses two monolithic integrated circuits with the characteristics listed in Table 1. A typical bus driver circuit is shown in Figure 2.
Note that 8641 quad transceivers can be used, combining LSI-ll bus receiver
and driver functions in a single package. Bus receiver (8640), bus driver
(8881), and bus transceivers (8641) are shown in Figures 3, 4, and 5, respectively. IC 8640 is listed in this handbook as Type 956, and Ie 8881 is
listed as Type 957.

~

+3:V1

IN

~

C1

OUT'R1 = 120K. MIN
R2 = 20K. MIN
C1 = 10pF MAX

_ R2

Figure 1

Ef
C2

-;-R3

l
TRANSMIl'TER OFF (LOGICAL 0)
R3 = 120K.MIN
.
C2 = 10pF.MAX
TRANSMITTER ON (LOGICAL 1)
R3 = 11 OHMS. MAX
= 10 pF. MAX

c2

Bus Driver and Receiver Equivalent Circuits

+5V

TYPICAL BUS DRIVER
1'-3307

Figure 2

Typical Bus Driver Circuit

-

-

--- -------------

J

2

1

GNO

3

4

5

7

6

CP-'27.

Figure 3

8640 Quad 2-lnput NOR Gates
(Bus Receiver)

vce
14

13

Figure 4

12

11

9

10

8

8881 Quad 2-lnput NAND Gate
(Bus Driver)
16

BUS 1

2

15

DATA OUT 1 .3

14

DATA IN

13

BUS 2

12

DATA IN 2

11

DATA OUT 2

10

ENABLE A
GROUND

Vee
BUS 4
DATA IN 4
DATA OUT 4
BUS 3
DATA IN 3
DATA OUT 3
ENABLE B

ENABLE A
ENABLE B

Figure 5

8641 Quad Unified Bus Transceiver
(Bus Receiver/Driver)
167

Table 1

LSI-11 Bus Driver. Receiver. Transceiver
Characteristics

Device

Characteristic

Sym

Specifications

Notes

Receiver
(8640)
(8641)

Input high voltage
Input low voltage
Input current at 3.8 V
Input current at 0 V
Output high voltage
Output high current
Output low voltage
Output low current
Propagation delay to
high state
Propagation delay to
low state
I nput high voltage
I nput low voltage
Input high current
Input low Gurrent
Output low voltage
70mA sink
Output high leakage
current at 3.5 V
Propagation delay to
low state
Propagation delay to
high state

V,H
V,L
"H
',L
VOH
VOH
VOL
'OL

1.7 V min
1.3 V max
80j.tA max
10 IJ.A max
2.4 V min
(16 TIL loads)
0.4 V max
(16 TTL loads)
10 ns min
35 ns max
10 ns min
35 ns max
2.0V min
0.8 V max
60j.tA max
-2.0 rnA max
0.8 Vmax

1
1
1.3
1.3
2
2.3
2
2.3
4.5

6
6
1

IOH

25 j.tA max

1.3

TPDL

25ns max

1.5

TPDH

35 ns max

1.5

,
Driver
(8881) (8641 )

•

T~DH

TPDL
; V,H
V,L
I'H
I,L
VOL

1.5

NOTES

1. This is a critical parameter for use on the 1/0 bus.
All other parameters are shown for reference only.
2. This is equivalent to being capable of driving 16
unit loads of standard 7400 series TTL integrated
circuits.
:
3. Current flow is defined as positive if into the terminal.
4. Conditions of loaa are 390 g to +5 V and 1.6 kg
in parallel with 15 pF to ground for 10 ns min and
50 pF for 35 ns max.
5. Times are measured from 1.5 V level on input to
1.5 V level on output.
6. This is equivalent to 1.25 standard TTL unit loading of input.

Bus receivers and drivers should be well grounded and use Vee to
ground bypass capa.citors. These gates should be located as close as
practical to the module fing!3rs which plug into the backplane and all
etch runs to the bus should be kept as short as possible. Attention to
-these cautions should yield a module design with minimum bus loading
(capacitance).

168

Brief

SpeCificati~ns

of CHIPKIT Integrated Circuits

Absolute Maximum Ratings:
Supply Voltage (Vee)
+7V
Operating Temp. (Ta) +32°F to +158°F (O°C to +70°C)
Storage Temp. (Ts)
_75 to +257°F (-60°C to +125°C)
0

Recommended Operating Conditions:
Supply Voltage (Vcc)
4.75V (Min), 5.0V (Norm), 5.25V (Max)
Supply Current (Vcc)
DC003: 140 mA (Max)
DC004, DC005: 120 rnA (Max)
DCe06: 160 rnA (Max)
OC010: 160 rnA (Max)
Free Air Temperature +32°F to +158°F (O°C to +70°C)
Relative Humidity
10% to 95%, noncondensing
Physical Dimensions:
DC003, .18~pin
DC004, . 20-pi n .
De005, 20-pin
DC006, 20-pin
DCOIO, 20-pin
W9512 Wire
Wrappable Module
SC07D-I0 Cable

0;3/1 center
0.3" center
0.3/1 center
0.3/1 center
0.3" center
Double height, extended length, single width.
10/, 40-conductor ribbon cable, with 40-pin (female)
mating connector (H856) installed on one end only;
prestripped on qther end.

Detailed Ispecifications, circuit diagrams, pin/signal descriptions, and timing
diagrams for each Ie follow in this Application Note.

169

DC003 Interrupt Logic
The interrupt chip is an 1 8-pin. 0.762 cm center X 2.349 cm long (max)
(0.3 in center X 0.925 in long) dual-in-line-package (DIP) device that
provides the circuits to perform an interrupt transaction in a computer
system that uses a daisy-chain type of arbitration scheme. The device is
used in peripheral interfaces to provide two interrupt channels labeled
"A" and "S," with the A section at a higher priority than the S section.
Sus signals use high-impedance input circuits or high-current open collector outputs, which allow the device to directly attach to the computer
system bus. Maximum current required from the Vee supply is 140 mAo

Figure 6 is a simplified logic diagram of the DC003 IC. Figure 7
shows the timing for the "A" interrupt section. while Figure 8 shows
the timing for both "A" and "S" interrupt sections. Table 2 describes
the signals and pins of the DC003 by pin and Signal name.

DC004 Protocol Logic
The protocol chip is in a 20-pin. 0.7'62 cm center X 2.74 cm long (0.3 in
center X 1.08 in long) DIP device that functions as a register selector.
providing the signals to control data flow into and out of up to four word
registers (eight bytes). Bus Signals can directly attach to the device because receivers and drivers are provided on the chip. An RC delay circuit
is provided to slow the response of the peripheral interface to data transfer request$. The circuit is designed such that if tight tolerance is not
required, then only'~an external 1 K ± 20 percent resistor is necessary.
External RCs can be added to vary the delay. Maximum current requ'ired
from the Vee supply is 120 mA.

Figure 9 is a simplified logic diagram of the DC004 IC. Signal timing'
with respect to different loads is shown in Table 3 and in Figure 10.
Figure 11 shows the loading for the test conditions in Table 3. Signal and pin definitions for the DC004 are ptesented in Table 4.

DC006 .Transceiver Logic
The 4-bit transceiver is a 20-pin. 0.762 cm center X 2.74 cm long (0.3
in center X 1.08 in long) DIP. low-power Schottky device; its primary
use is in peripheral device interfaces to function as a bidirectional buffer
between a data bus and peripheral device logic bus. It also includes a
comparison circuit for device address selection and a, constant generator
for interrupt vector address generation. The bus 1/0 port provides highimpedance inputs and higf'l-drive (70 mA) open collector outputs to
allow direct connection to a computer data bus structure. On the peripheral device side, 'a bidirectional part is also provided. with standard TTL
inputs and 20 mA, tri-state drivers. Data on this port is the logical inversion of the data on the bus side.
170

.'"

VCC

...

..

r---~----------------------------------~------------~------------------------------IENAST H

R~TAH--~---r---+------~

VECTOR H
VECRQSTB H
BOIN L

ENADATA H
ENACLK H

INITO L

ENAOATAH

BINIT L
BLAKO L
BLAKI L
BIRQ L

ENACLK H
ENBCLK H
ENBOATAH
ENBST H
RQSTB H .

GND
BIAKI L

....
.....,
....

VCC
RQSTAH
ENAST H

CI
)0

SINIT L

BIAKO L

)")0

80IN L

BIRQ L

~----------------------------~-+--+-------~----~----~-----ENBSTH

VECTOR H
ENSDATA H

ENSCLK H

VECRQSTB H

..---11----+----''--110
VCC

RQSTO H -------+----------~

lK

L-__________________L-__________________

~L_

_ _ _ _ _ L_ _ _ _ _ _ _ _ _ _

~

____________

~INlroL

Ie-On)

Figure 6

DCOO3 Simplified Logic Diagram

BINIT L

INITO L

I

~991300:

~MINI

!'
-=:rEJ
~

:

7~5r+I------------------------------------------

,

I
I
I
I

ENA DATA H

-\,
ENA ClK H

30MIN-i

Fl
n
r-F-------------.L-...-____-.--___
~----------------~

I

~-----------------

,~

ENA ST H

7-30 -..;

ROSTA H

IS- 6S

BIRO l

BDIN l

--.J-j \.-.: t:= 20-90
~

-------'1 :

BIAKI L

'

I

U

35 MIN--!

,.....--------,
~----~

I

I·

35 MIN--:
I

: r:--:+-,~

VECTOR H _ _ _ _ _ _ _ _ _1_0-_45_.....
~I'_Ir-:

I:::.---J
1:
-+-:---'r-;_______
"

',-_'_0-_4_5______

__________________________
BIAKO L

+'~

12-55--:

I

~--------

~

12-55

NOTE:
T imlS Qre in nanoseconds

Figure 7

DC003" A" Interrupt Section Timing Diagram

Table 2
Pin

Signal

De003 Pin/Signal Descriptions
Group

Descriptio~

VECTOR H

Interrupt Vector Gating. This signal should
be used to gate the appropriate vector address -onto the bus and to form the bus
signal called BRPLY L.

2

VEC ROSTB H

Vector Request "B." When asserted. indicates ROST "B" service vector address
is required. When unasserted. indicates
AOST "A" service vector address is required. VECTOR H is the gating signal for
the entire vector address; VEC ROST B H
is normally bit 2 of the vector address.

3

BDIN L

III

Bus Data In. This signal. generated by the
processor BDIN. always precedes a BIAK
signal.

172

Table 2
Pin

Signal

DC003 Pin/Signal Descriptions (Cont)
Group

Description

4

INITO L

5

BINIT L

HI

Bus Initialize. When assEtrted, this signal
brings all driven lines to their unasserted
state (except INITO L).

6

BIAKO L

II

Bus' Interrupt Acknowledge (Oud. This
signal is the daisy-chained signal that is
passed by all devices not requesting interrupt service (see BIAKI L). Once passed
by a device, it must remain passed until' a
new BIAKI L is generated.

7

BIAKI L

III

Bus Interrupt Acknowledge (In). This signal is the processor's response to BIRO L
true. This signal is daisy-chained such that
the first requesting device blocks the signal propagation while non-requesting devices pass the signal on as BIAKO L to the
next device in the ch'ain. The leading edge
of BIAKI L causes BIRQ L to be unasserted bv the reQuestinQ device.

S

BIRO L

II

Asynchronous Bus Interrupt Request. This
signal is from a device needing interrupt
service. The request is generated by
false to tru~ transition of the ROST signal
along with the associated true interrupt
enable signal. The request is removed after the acceptan.ce of the BD IN L signal
and on the leading edge of the BIAKI L
signal or the removal of the associated interrupt enable or the removal of the asso\
ciated request signal.

Initiali2e Out. This is the buffered BINIT L
signal used in the device interface for general initialization.

a

10

17

11
16

REOSlB H III
- REQSTA H III

ENB ST H
ENA ST H

Device Interrupt Request. WheR-aSserted
with the enable "A" flip-flop asserted, will
cause the assertion of BIRO L on the bus.
This signal line normally remains asserted
until the request is se.rviced.
Interrupt Enable "A" Status. This signal
indicates the state of the interrupt enable
"A" internal flip-flop which is controlled
by the signal line ENA DATA H and the
ENA eLK H clock line.
173

Table2
Pin

DCOO3 Pin/Signal Descr-iptioni (Cont)

Signal

Group Description

15

ENS DATAH
ENA DATA H

Interrupt Enable "A" Data. The level on
this line. in conjunction with the ENA ClK
H signal. determines the state of the internal interrupt enable "A" flip-flop. The output of this flip-flop is monitored by the
ENA ST H signal.

13
14

ENS elK H
ENA ClK H

Interrupt Enable "A" Clock. When asserted (on the positive edge). interrupt enable "A" flip-flop assumes the state of the
ENA DATA H ~ignal line.

12

BINIT L

~ 1~2 !

INITO l

~

,
7-~5

I

'

,~I~---------------------------,2- 50

I

I

:

:

I

EN9 DATA H

I

I
ENe elK H

30 MIN

--l flL.-------------------

--l',--------------------F
I

ENE! ST H

7- 30

BIRO l

'ROST~/I

'5-

65~

r:o.-___________--I-+I----IF20-90

:

I

I

:

-~----~

I

ENA DATA H

;
~O

ENA ClK H

J

MIN""';

RL..,________-+-_ _ _ __

ENA ST H

I

ROSTA H

BOIN L

____________________
BIAKI l

~,

~~

35 MIN --.:

~

I

~
: I

35 MIN ---.:

I:::.-l
Lr-b

: r+,
i1
"L,..IO_-4_5_ _ _'_O-_45+\-1....

VECTOR H _ _ _ _ _-.,._ _ _ _ _'_0-_4.....
5i1
....

I

: 1....10_-4_5 _ _
,

L_.rt-J ....

VECROSTB H _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _'_S"--l6SL::J

~

NOTE,
T1m., or, in I"tOno,.conds

Figure 8

DC003 "A" and "B" Interrupt Sections
Timing Diagrams

174

Table 3

Signal

........,
CJI

Pin 18
Connection
RX
1K ± 5%
330 n ± 5%
15 pF ± 5%

=

DC004 Signal Timing vs

With
Respect
to
Signal

I

Otit~ut

Output Being
Asserted (ns)
Max
Min

Loading
Output Being
Negated (ns)
Min \ Max

Fig. 10
Reference

SEL (0.2.4.6) L
(Load B)

BSYNC L
(load B)

15

40

5

30

T5.T6

OUTLB L
(Load B)

BDOUT L
(Load B)

5

30

5

30

T9. T10

OUTHB L
(Load B)

OBOUT l
(Load B)

5

30

5

20

T9,T10

INWD L(load A)

BDIN L
(Load B)

5

30

5

30

Tl1.T12

BRPLY L
(load A)

OUTLB L
(Load B)

20

60

-10

45

T13.T14

BRPLY L
(Load A)

OUTHB L
(Load B)

20

60

-10 \. 45

T13. T14

BRPLY L
(load A)

INWOL
(Load B)

20

60

-10

45

T13.T14

BRPLY L
(Load A)

VECTOR H

30

70

0

45

-T13.T14

, Tabfe 3

Pin 18
Connection
AX = ~.64K

,

....
.....,
0\

CX

±

Output Being
.Negated (ns)
Min
Max

OUTLB L
(Load B)

300

400

-10

45

T13. T141

OUTHB L
(Load B)

300

400

-10

45

T13.T14

BAPLY L
(Load A)

INWDL
(Load B)

300

400

-10

45

T13.T14

BAPLY L
(Load A)

VECTOR H

330

430

0

45

T13. T14

OUTLB L

10

50

10

50

T15.T16

OUTHB L

10

50

10

50

T15.T16

INWDL,

10

50

10

50

T15. T16

VECTOR H

10

50

10

50

T15.T16

:BAPLY L
(load A)
1% ~APLY L
(Load A)

= 220 pF ± 1%

With
Respect
to
Signal

Output Being
Asserted (ns)
Min
Max

Signal
."

DC004 Sig"!al Timing vs Outp,ut Loading (Cont)

Pin 18
AXCXH
Connection
RXCX H
RX = 330 Q ± 5%
C = 15 pF ± 5% AXCXH
RXCXH

Fig. 10
Reference

/

Tabl&4
Pin

Signal

DCOO4 Pin/Signal Descriptions

Group

VECTOR H

Description
Vector. This input causes BRPlY l to be
generated through the delay circuit. Independent of BSYNC land ENB H.

2
3
4

BDAl2 l
BDAl1 l
BDAlO l

"
,...-"
II

Bus Data Address lines. These signals are
latched at the assert edge of BSYNC l.
lines 2 and 1 are decoded for the select
outputs; IJne 0 is used for byte selection.

5

BWTBT l

II

Bus Write/Byte. While the BDOUT l input
is asserted. this signal indicates a byte or
word operation: Asserted
byte. unasserted = word. Decoded with BDOUT l
and latched BDAlO l to form OUTlB l
and OUTHB l.

=

6

BSYNC L

"

Bus Synchronize. At the assert edge of
this signal. address information is trapped
in four latches. While unasserted. disables
all outputs except the vector· term of
BRPLY L.

7

BDIN l

JI

sUs Oata In. This is a strobing signal to
effect a data input transaction. Generates
INWD land BRPLY l through the delay
circuit and INWO l.

8

Bf3PlY l

III

Bus Reply. This signal is generated
through an RC delay by VECTOR H, and
strobed by BDIN l or BOOUT l. and
BSYNC l and latched ENB H.

9

BOOUT l

II

Bus Data Out. This is a strobing signal to
effect a data output transaction. Decoded
with BWTBT Land BDALO to form·
OUTlS land OUTH B l. Generates
BRPlY l through the delay circuit.

11

,12
13

INWD l

In Word Used to gate (read) data from a
selected register onto the data bus. Enabled by BSYNC l and strobed by BDIN l.

OUTLB.-L
OUTHB l

Out low Byte, Out High Byte. Used to
load (write) data into the lower. higher. or
both bytes of a selected register. Enabled
by BSYNC l and decode of BWTBT land
latched BDAlO l. and strobed by BCOUT
l
(

177

Table·4
Pin

Signa'

DC004 Pin/Signal Descriptions (Cont)
Group

SElO l

14
15
16

17

SEL2 L
SEL4 L
SEL6 L

18

RXCX

·19

ENS H

Description
Select lines. One of these four signals is
true as a function of BDAL2 Land BDAL 1
L if ENB H is asserted at the assert edge
of BSYNC L. They indicate that a word
register has been selected for a data
transaction. These signals never become
asserted except at the assertion of BSYNC
L (then only if ENB H is asserted at that
time) and once asserted. are no.t unasserted until BSYNC L becomes unasserted.

III

External Resistor Capacitor Node. This
node is provided to vary the delay between the BDIN L. SDOUT L. and VECTOR H inputs and BRPLY L output. The
external resistor should be tied to Vee and
the capacitor to ground. As an output. it is
the logical inversion of SRPLY L.
~nable. This signal is latched at the asserted edge of BSYNC L and is used to
enable the 'select outputs and the address
term of BRPLY L.
VECTOR H
BDAL2 L
BDALI L
BDALD L

BWTBT L
BSYNC L

BOI.,.. L
BRPLY L

BOOUT L

GNO

BDAll L

---~-;

SEL 6 L

DECODER

SEl4 L
BDAll L

----+--1

SEL 2 L
SEL 0 L

BOAlD l - - - _ + _ - 1

) 0 - - - - - - QuI Nil
) 0 - - - " ' : ' - our LB L

BWTBT L
r---~--RXCX

H

BRPlY L
L -_ _ _ _ _ _ _ _ _ _ _ _ _ VECTORH

BDOUT L

BOIN L

)----t=======£:P---------------INWDL
Figure 9

DC004,Simplified Logic Diagram
178

,

BOAL (Z.I.Ol L

ENB

~Z5 MINlz5MIN~

H~~~N!~fN~

!

BSYNC L

SEL (0.2,4,61 L

BWBTL%%~
I

BOOUT L

15 MIN._

I

~r-~

___

,~

OUTHB L
OUTLB L

----------r'......,
T9r

BOIN L

==!Tt'~

--:

'-

--:: rTlO

,
I

Iq

I·

:

INWO L

I
I

~TI2F

I

-!mb

8RF'L.Y L

I
I

,

!1~F2.4V

-:
:

I

,.
I

I

VECTOR H

.~
I,
... '~

I

I

-imr-

R. C. H

it

Ij~
~

M_IN_':1~:~._______

'5__

I

---1 1==
T16

TIME REQUIRED TO DISCHARGE R. C. FROM ANY CONDITION ASSERTED' 150.,

NOTE:

Tl",., a" In nano •• condl
"- 454'

Figure 10

DC004 Timing .Diagram

Vee

Vce

OU~~~~~

Vee

2eon
FROM
OUTPUT

200pF

1_

OIOOE-

1'5"

.!!

LOAD A

LOAD

F0777

B
II -4349

Figure 11

DCOO4 'loading Configurations for Table 5
179

Three address "jumper" inputs are used to compare against three bua_
inputs to generate the signal MATCH. The MATCH output is open collector, which allows the output of several transceivers to be wire-AN Oed
to form ~ composite address match signal. The address jumpers can also
be put into a third logical state that disables jumpers for "don't care"
address bits. In addition to the three address jumper inputs, a fourth
high-impedance input line is used to enable/disable the MATCH output.

Three vector jumper Inputs are used to generate a _constant that can be
passed- to the computer bus. The three inputs directly drive three of the
bus lines, overriding the action of.the control lines.

Two control signals are decoded to give three optional states: receive
data, transmit data~ and disable.

MaXimum current required from the

Vee supply is 120 mA.

Figure 12 is a simplified logic diagram of the DC005 IC. Timing for the
various functions is shown in Figure 5-13. Signal and pin definitions for
the DC005 are presented in Table 5-5.

Table 6
Pin

Signal

12
11
9

BUS(3:0) l
BUSO
BUSt
BUS2
BUS3

8
18
17
7

6

DAT(3:0) H
DATO
DAT1
DAT2
OAT3

DCOO6 Pin/Signal Descriptions '

Group

II
II
~~II

II

Description

Bus Data. This set of four lines constitutes
the bus side of the transceiver. Open collector outputs; high-impedance inputs.

low = 1.
Peripheral Device Data. These four tristate lines carry the inverted received qata
from BUS (3:0) when the transceiver is in '
the receive mode. When in transmit data
mode, the data carried on these lines is
passed inverted to BUS (3:0). When in the
disabled mOde. these lines go open (HI-Z).
High = 1.

'.

180

Table 5

DCOO5 Pin/Signal Descriptions (Cont)

Pin

Signal

Group

14
15
16

JV(3: 1) H
JV1
JV2
JV3

V
V
V

13

MENS L

II

Match Enable. A low on this line will enable the Match output. A high will force
Match low, overriding the match circuit.

MATCH H

'"

Address Match. When BUS (3: 1) match
with the state ofJA (3: 1) and MENB Lis
low, this output is open; otherwise it is
low.

3

1
2
19

JA(3: 1) L
JA1 L
JA2 L
JA3 L

Description
Vector Jumpers. These inputs. with internal pull-down resistors, directly drive BUS
(3: 1). A low or open on the jumper pJn will
cause an open condition on the corresponding bus pin if XMIT H is low. A high
\ will cause a one (tow) to be transmitted on
the bus pin. Note that BUSO L is not controlled by any jumper input.

Address Jumpers. A strap to ground on
these inputs will allow a match to occur
with a one (low) on the corresponding
BUS line: an open will allow a match with
a zero (high): a strap to VCC will disconnect th~ corresponding address bit
from the cOf11parisoh

IV
IV
IV

'l'.

5
4

XMITH
REC H

Control Inputs. These lines control the operation of the transceive1 as follows.

-

REC

XMIT

o

Q

f~~O

,

1

----'F-'1

1\,
'1)'
10<

DISABLE: BUS. DATopen

XM/T DATA: OAT -.. BUS
RECEIVE: BUS -.. OAT
RECEIVE: BUS--.. OAT

To avoid tri-state' 'signal overlap conditions. an internal circuit delays the change
of modes between XMIT DATA and RECEIVE mode and delays tri-state drivers
on the OAT lines from enabling. This action is independent ofthe DISABLE mode.

181

V~

JA1 l

20

JA2 l

19 JA3 l

MATCH H 3

18 DATO H

REC H

'.7 DAn H

16 JV3 H

XM'T H
DAT3H

15 JV2 H

DAT2 H

14 JV1 H
13

BUS3l
BUS2l

_9

GND

MENB L

12

BUSO L .

11

BUS1 L

DATO

H

JV1

H

DAn

H

JV2

H

DAT2

H

JV3

H

DAn

H

BUSO

BUS1

JA1

BUS2

JA2

r_----------------~r_------_+~~----~=---~-T-

>-........-t-"T'""

BUS3

JA3

~----------------~====:l~~_r--------------r_--

MENe

MATCH H

-r------------,-,

XMIT

H

REC

H ...,........

----------------------------1.-'
IC·OCOO5

Figure 12

DCOO5 Simplied logic Diagram
182

TRANSIo'IT DATA TO SUS

--11

X MI T H ________

REC H (GROUND)

I- 5 TO 30nl

-I

-I

1-5 TO 30nl

-------------------------------------------------I

BUS L - OUTPUT

I

,-

~--5-T-0-2-5n-"-~~l__~~----::~r-~~--5-T-0-2-5-nl---r----__

OAT

__________
H-INPUT _ _ _ _---'

c:=

J

•

RECEIVE DATA FROM SUS (SUS INITIALLY HIGH)
XMIT H (GROUND)

REC H

OAT H - OUTPUT
BUS L-INPuT

-------------------------------------------I
I-- 0 TO 30nl
- .~r,...r-------------'---i'-------8 TO 3Dnl
-------r-----;LI___________.......
_

J

----------:;j-i

I- 0 TO 30nl

--I

HiZ

HZ

c:=
____

RECEIVE DATA FROM BUS (BUS INITIALLY LOW)
XiUT H (GRoUND)

REC H

I

------~

~

~8

..j
BUS L - INPUT

I

I-- 0 TO 3Dn.

HiZ~

OAT H - OUTPUT

-.j

1-0 TO 3On.
HiZ

TO 30nl

r==

1

------------------~

VECTOR TRANSFER TO SUS
JV H

d

----------l

BUS L - OUTPUT

I
--t

I-- ?On. MAX
1

F·20

nSMA
X

ADDRESS DECODING

X

BUS l. - INPUT

MATCH H

________

F:: 10 TO 4On.
X

~--~---------J

1

MENQ .L

I

-1

I- 5 TO 40n.

1 klo

RECEIVE MODE LOGIC DELAY
XMIT'H

REC H

DAT(3:0) H

(OUTPU:~

I

------1'"""
- -_ _ _

1-40 TO 90n.

~-,----------.JI

I

Figure 13

De005 Timing Diagram
183

TO 40nl

Dcooe Word Count/Bus Address Logic
The wo·rd count/bus address (WC/BA) chip is a 20-pin. 0.7S2 cm center
X 2.74 cm long (0.3 in center X 1.0S in long) DIP. low-power Schottky
device. Its primary use is in DMA peripheral device interfaces. This IC is
designed to connect to the tri-state side of the DC005 transceiver. The
DCOOS has two S-bit binary up-counters. one for the word (byte) count
and another for bus address. Two DCOOS ICs may be cascaded to
increase register implementation.
The chip is controlled by the address latch protocol chip. (DC004). the
DMA chip (DC010). and a minimum of ancillary logic. 80th counters
may be cleared simultaneously. Each counter is separately loaded by LD
and the corresponding select line from the protocol chip. Each counter is
incremented separately. The WC counter (word byte count) is always
incremented by one; the A counter (bus address) may be incremented by
one or two for byte or word addressing. respectively.
Data from the DCOOS IC is placed on the tri-state bus via internal tristate drivers. Each counter is separately read by R 0 and the corresponding select line.
Figure 14 is a block diagram of the OC006 IC while Figure 15 iilustrates a sil1'lplifiedlogic diagram. Figures 16 and 17 illustrate input
and output voltage waveforms: FJgure 18 shows the timing diagram of
the OCOD6 while the setup time and pulse width switching characteristics are presented in Tables Sand 7. The OCOOS pin/Signal description is presented in Table s.

Table 8
/'

Setup Time and Pulse Width Switching Characteristics·

Time

Description

Signal

t3
t5
t6
t7
t8
t, ,
t14
t'5
t'6
t'8
t21
t24
t25

PtrlSe width (min)
Setup time
Setup time
Pulse width (min)
Setup time
Clock pulse width (min)
Setup time
Setup time
Clock pulse width (min)
Setup time
Setup time
Clock off time (min)
Data hold time

S-C to S-A
O/F (7:0) to LO
S-Cto LD
LD
S-C toRD
CLK-C (HI)
S-C to S-A
S-A to RD
ClK-A (HI)
CNT1 A to CLK-A
RD to RD-A
ClK-A. ClK-CLD to DATA IN

Min
//

·Vee

=- 5.0

±

0.25 V.

184

50ns
10 ns
10 ns
90ns
20ns
40ns
20ns
10 ns
40ns
45 ns
15 ns
40ns
·20ns

TRUTH TABLES
WHERE
L
H

X

= TTl LOW
= TTL HIGH
= DON'T CARE
= HIGH IMPEDANCE
= HIGH TO LOW TRANSITION
READ CONTROL
OUTPUTS

INPUTS
LD - H
RD-A
L
L
L
L
L
H
H

H

RD
L
L
L
L
H
L
L
L
L
H

H

H

H
H

H

H

H

H

S-A

SoC

D/F<70>

L
L

L
H
L

CLEAR A&C AND READ C
A<70>
C<70>

H

MAX-A
S-A

H

H

X

X

Z

12BD/F

L
L

L

CLEAR A&C AND READ A
A<70>
A<70>
A<70>
CLEAR A&C AND READ A
A<70>
A<7.0>
'A<70>

64D/F

H

L
H
L

H

H
L
L
H
H

H

L
H

Z

32D/F

16D/F

9 DIF

GND

WRITE CONTROL'
INPUTS
RD - A = L, RD = H
S-A
LD
L
I
L
I
H
I
H
X
H,
L
H
L
H
H
-

SoC
L
H
L
H
L
H
L

FUNCTION
"ILLEGAL
LOADA<70>
LOAD C<70>
WC/BA NOT SELECTED
CLEAR BOTH COUNTERS
LOADING DISABLED
LOADING DISABLED

• ILLEGAL CONDITION BECAUSE A LOAD OPERATION AND A CLEAR
OPERATION IS ATTEMPTED SIMULTANEOUSLY

MAX-C

CNTlA

0-+------+-+--..

CLK-A

0-+------+-+--..

LD(}-+----t

S-A

SOC
READ
CONTROL
LOGIC
RD-A o-t-------i
RD (}-+---~

Figure 14

De006 Truth Table, Logic Diagram, and
Simplified Block Diagram
"
185

LOOOSA

ClK-A l

SoC L

~MAX-AH

C1CNTlA H MA:J

CNTIA l

00

t

01
02

~CLKAL

g~1

g:

ClR H

SlOO9A

~

I

l.,~"

A COUNTER 07
8 BIT BINARY
I
UP COUNTER

- - ..

f

-I

f f

X>-<]

~1280/FH

X>-<]

~640/FH

LOA H

1------1

320/F H

O/F (0:7)
RO L
169/F H
RO-A H
80fF H

.....
00

en

~

II

m

C COUNTER
8 BIT BINARY
UP COUNTER
lO l

1 cr-"'\.
I

1LOC

Cl H
..

8?
g~

H

04
CLK·C H

~

OClKC l

.

07

i}oo"

_

I. __ .

- J

)()-(] -

"""

20fF H

~1

OfF H

CLR H
MAXC L

,i
O/Fto;7)

Figure'15

DCOOa Simplifi~d Logic Diagram

MAX-C H

\'---

l-H
OUTPUT VOLTAGE
WAVEFORM IN
PHASE

15V

15V
OUTPUT VOLTAGE
WAVEFORM OUT OF
PHASE

~

H-L

PULSE CONDITIONS FOR DELAY MEASUREMENTS

Figure 16

OUTPUT

Input Voltage Wavefor~

--

~L~:a;l~~L~~.3_V

______

....Jf-+~~ ____

3V

-OV

WAVEFORM 1
(SEE NOTE 11
---l--VOL
IHzt

WAVEFORM 2
(SEE NOTE 21

05V

-----.. .\ ---F~::
f ~

1 5V

SlAND
S2 CLOSEO

LOAD A LOAD CIRCUIT FOR
TRI-STATE OUTPUTS

/
NOTES
WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE
OUTPUT IS LOW EXCEPT WHEN DISABLED BY THE OUTPUT CONTROL
WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE
OUTPUT IS HIGH EXCEPT WHEN DISABLED BY THE OUTPUT CONTROL

Figure 17

Outputs Voltage Waveforms (Tri-State)

, 187

/

Table 7

Propagation
Delay (ns)
Max
Min

Input Signal
Polarity
Name

Output Signal
Polarity
Name

Test
Conditions

S-C
S-A

H-L
H-L

O/F (7:0)

Load A
RO-A=4V
(C Counter)

15

t:z.

S-C
S-A

H-L
H-L

O/F (7:0)

X-L

Load A
RO-A=4 V
(A Counter)

15

80

t4

RD

L-H

O/F (7:0)

D/F (7:0)-Z

Load A

10

30

t9

RD

H-L

O/F (7:0)

Z-O/F (7:0)

Load A

34

80

t,o

CLK-C

H-L

O/F 1

L-H

Load A

18

55

t'2.
t'9

CLK-C
CLK-A

L-H

MAX-C
MAX-A

L-H

Load B

10

30

Time
t,

....

Switching Characteristics *

~

• Loads are presented in Figure 10.

"

X-L

80
,I

\

Table 7

....
00

CD

Switching Characteristics· (Cont)

Time

Input Signal
Polarity
Name

Output Signal
Name
Polarity

Test
Conditions

Propagation
Deray (ns)
Mint
Max

t'3

CLK-C

H-L

MAX-C

H'-L

Load B

10

30

t17

CLK-A

H-L

DfF2

L-H

Load A

18

55

t20

CLK-A

H-L

MAX-A

H-L

Load B

10

30

t22

RD-A

L-H

OfF (7:0)

Z-L
Z-H

Load A
Load A

10
10

30
30

t23

RD-A

H-L

OfF (7:0)

L-Z
H-Z

Load A
Load A

8

25
25

• Loads are presented in Figure 10.

(

/

8

Table 8

DCOO8Pin/Signal. aescriptions
Description -

Signal

Group

6

CNT1A

I

3

CLK-A

Clock A Counter (TTL Input). This clock
signal increments the A counter on its
negative edge. The counter is incremented
by one or two. depending on CNT1 A.
CNT1 A and LO must be stable while CLKA is high.

16

CLK-C

Clock C Counter (TIL Input). This clock
signal increments the C counter by one on
its negative edge. LO must be stable while
CLK-C is high.

S-A

Select A Counter (TIL Input). This signal
allows the selection of the A counter according tQ/the truth tables (Figure 5-14).

Pin

«

"

2

Count A Counter by 1 (TTL Input}. This
signal controls the least significant bit of
the A counter. When CNT1A is low. the A
counter increm,ents by one. When high.
the LSB is prevented from toggling. hence
the counter increments by two. When two
counters are cascaded. CNT 1A on the
high-order counter should be grounded.

~

19

S-C .

4

RO-A

Read A Counter (TIL Input). This signal
allows the selection of the A counter according to the truth tables (Figure 5-14).

5

RO

Read (TIL Input). This signal allows the
read operation to take place according to
the truth tables (Figure 5-14).

18

LO

Load (TIL Input). When this signal goes
through a high-to-Iow transition. the load
operation is allowed to take place according to the truth tables (Figure 5-14). No
data changes permitted while LO is low.

·1

Select C Counter (TIL 'Input). This signal
allows the selection of the C counter according to the truth tables (Figure 5-14).

190

f

Table 8

DCOO8 Pin/Signal Descriptions (Cont)
Group

Pin

Signal

7-9

OfF (7:0)

11-15

17

Description
Data Bus (Bidirectional, Tri-State OutputsmL Inputs). These eight bidirectional
lines are used to carry data in and out of
the selected counter.

MAX-A

Maximum A Count (TIL Output). This signal is generated by ANDmg CLK-A and ..
. the maximum count condition of counter
A (count 376 when counting by 2 or
count 377 when counting by 1).

MAX-C

Maximum C Count (TIL Output). This sig-)
nal is generated by ANDing CLK-Cand
the maximum count conditions of counter
C (count 377).

,c

1DfF
2D/F

S-A

RD
LD
CLK-C

~--------~~--~

eLK-A

-"

CNTlA

~------~----------~------------~

RO-A

-t------,I------M~~---------_+_+----~

MAX-C

-t--------~~~----~

MAX-A

-t-------~~---------------------------~

CLEAR

LOAD

Figure "18

DeOO6 Timing Diagram

191

DC010 Direct Memory Access Logic
The direct memory access (D,MA) chip is a 20-pin, 0.762 cm center X
2.74 cm long (0.3 in center X 1.08 in long) DIP, low-power Schottky
device, foJ. primary use in DMA peripheral device interfaces using the
LSI--l1 bus.
"
This device provides the logic to perform the handshaking operations
. required to request and to gain control of the system bus. On"ce bus
mastership has been established, the DCO 10 generates the required signals to perform a DIN, DOUT, or DATIO transfer as specified by control
lines to the chip. The DCO 10 IC has a control line that will allow multiple
transfers or only four transfers to take place before giving up bus mastership.
Figure 19 is a simplified logic diagram of the DC010 IC. The logic
symbols and truth table are presented in Figure 20 and the DC01 0
voltage waveforms are shown in Figure 21. Table· 9 describes the
signals and pins of the DCO 10 by pin and signal name. Figures 22
through 25 show the timing for the DC010 while the setup time and
pulse width specifications are listed in Table 10. The switching characteristics are presented in Table 11.
(MASTER

1------/MiMA!AsmTE~RRUL)=====1C>__BOMR L

so H I - - - - - ' o - ,
REO H _ _ _-.J,._---!

,APlY S'D H I - - - - - - a

BDMGI

I

L----+----t---~--\.

(MASTeR ENA) _ _ _ MASTfR H

D-------t+---BDMGO

XH-'---_IENO HI
eNT4 H - - - - I - - - - r - . . .

(MASTER ENA)

TMOUT H---'-+-'--+-------'----+'--I...-./
DATIN L -.---~-a--...
!--------------TSyNC H
P-------------DATEN l

DATIO L _ _ _

-'--_~~_Q

(E~CYCle HI

IINIT HI

RPLV L

elK L

ENA)I-=±==~=====a~
H'-=

(MASTER
ASVNC

lEND

u-i===============i====-_---.J
Figure 19

OC010 Simplified Logic Diagram

192

Table 9
Pin

13

Signal

DC010 Pin/Signal Descriptions

Group

Description·

REO H

Request (TTL Input). A high on this signal
initiates the bus request transaction. A
low allows the termination of bus mastership to take place.

SOMGI L

OMA Grant Input (HI-Z Input). A low on --this signal allows bus mastership to be established if a bus request was pending
(REO
high); otherwise. this signal is delayed and output as BDMGO.

=

16

CNT 4 H

Count Four (TTL Output). A high on this
signal allows a maximum of four transfers
to take place before giving up bus mastership. A low disables this feature and an
unlimited transfer will take place as long
as REO is high. If left. open, this pin will
assume a high state.

14

TMOUT H

Time-Out (TTL Input/Open Collector Output). This 1/0 pin is low while SACK H is
high. It goes into high impedance when
SACK H is low. When driven low it prevents the assertion of BOMR; when
driven high it allows the assertion of
BOMR to take place if SOMA has been
negated due to the 4-maximum transfer
condition. An RC network may be used on
this pin t6 delay the assertion- of SOMR.

3

DATIN L

2

DATIO L

I

Data In (TTL Input). This signal allows the
selection of the type of transfers to take
place according to the truth table (Figure
5-20).
Data In/Out (TTL Input). This signal allows
the selection of the type of transfer to take
place according to the truth- table (Figure
5-20). During a DATIO transfer. this signal must be toggled in order to allow the
completion of the output portion of the
1/0 transfer.:....
If left open, this pin will assume a high
state.

• Refer to Figures 22 through 25_
r

193

Table 9
Pin

Signal

12

RSYNC

DC010 Pin/Signal Descriptions (Cont)
Description •

Group

Receive Synchronize (TTL Input). This signal allows the device to become master
according to the following relationship:
ASYNC L • RPLY"L • SACK H
MASTER

17

CLK L

15

RPLY H

=

Clock" (TTL Input). This clock signal is used
to generate all transfer timing sequences.
/
Reply (TTL Input). This signal is used to
enable or disable the free clock signal according to the truth table (Figure 5-20).
This signal also allows the device to become master according to ~he following
relationship:
RSYNC L • RPLY L • SACK H
MASTER

=

Initialize (TTL Input). This Signal is used to
initialize the chip to the state where REO
is needed to start a bus request transac" tion. When I N IT is low, the following signals are negated~ SOMRL, MASTER H,
OATENL. AORENL. SYNCH, OINH.
OOUTH.

19

INIT L

11

SOMR L

OMA Request (Open Collector Output). A
low on this signal indicates that the device
is requesting bus mastership. This output
may be tied directly to the bus.

9

MASTER H

Master (TTL Output). A high" on this signal
indicates that the device has bus mastership and a transfer sequence is in progress.

8

BOMGO L

DMA Grant Output (Open Collector Output). This signal is the delayed version of
BOMGI if no request is pending; otherwise. it is not asserted. This output may
be tied directly to the bus.

• Refer to Figures 22 through 25.

194

Table 9
Pin

7

Signal

DC010 Pin/Signai Descriptions (Cont)
Description •

Group

TSYNC H '

Transmit Synchronize (TTL Output). This
signal is asserted by the device to indicate
that a transfer is in progress.
.

18

DATEN .l

Data Enable (TTL Output). This signal is
asserted to indicate that data may be
placed on the bus.

4

AD,.EN H

Address Enable (TIL Output). This signal
is asserted to indicate that an address
may be placed on the bus.

6

DIN H

Data In (TIL Output). This signal is asserted to indicate that the bus master device is ready to accept data.

5

DOUT H

Data Out (TTL Output). This signal is as. serted to indicate that the bus master de,,:
vice has output valid data.

• Refer to Figures 22 through 25,'

Table 10 Setup Time and Pulse Width
Switching Characteristics·
Time

Description

Signal

t,
t4
ts
ts
t12
t13
t14
t'8
t28
t2s

Pulsew,idth (min)
Setup time
Setup tim,e
Setup time
Pulse width (min)
Pulse width (min)
Setup time
Setup time
Setup time
Setup time
Setup time
Pulse width

t3)
t32.

Setup time
Pulse width (min)

35 ns
INIT
INITto REO,
25 ns
35 ns
BDMR to BDMGI
Ons
BDMR to BDMGI
elK (low)
.60ns
elK (high)
.60ns
35 ns'
REO to elK
DIN to RPlY
·Ons
DATIN. DATIO to eLK 60ns
RPlY to elK·
30ns
RPlY to DATIO
35 ns
DATIO
30 ns 1 clock
period
DATIO to elK
65 ns
REO
35 ns

tn
t24~

·vee = 5.0 ±

0.25 V

195

Min Max

REQH

VCC

TRUTH TABLE

OAT/OL

INln

DATIN L

DATEN l

WHERE

CLK H

L
H

= TTL

X

= DON'T CARE

= TTL

LOW
HIGH

CNT4H
RPLY L
TMOUTH
BOMGOL

INPUTS
DATIN

DATIO

TRANSFER
TYPE

X

L
H
H

DATIO
DIN
DOUT

BDMGIL

BSACK

RSYNCH

G~D

L
H

BDMR L

Figure 20

DC010 Logic SyrnbollTruth Table

INPUT

OUTPUT IN
PHASE

1.SV

OUTPUT OUT
OF PHASE
I

PULSE CONDITIONS FOR DELAY MEASUREMENTS

Figure 21

DC010 Voltage Waveforms

elK

+_+-______

RSYNCHlL._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

RP~~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~___~_~--------I

REO H _ _ _ _ _ _ _ _ _ _ _~I

1

_________________________~~_;t.~

I

SOMRl

I

--r- I
rBOMql~
I

I

!

I.

I

I,
I~I------------------I !. I

1...-1.--1

I
I

~

1-1.-1

r--,- - - : - - - - - - - ; \

'---':'---t~

80MGO~L-------;

'

t-- I,

~

;-1- , - - - - - - -

I

!I

,

I

1--17----1
I

0TMOUT H i

I

t

~t,.

I

,

I

i

~~I-~I~-------

____~I~~--------------I ,

MASTER~~~______________________~~----~,----------~i~·,
AOREN H

il':Fr----------

I

--I l • t--,--________-:-l__________________

INITl~1
~--------~.~I

i·

'WITH NO RC NETWORK CONNECTED

Figure 22

DC010 Timing Diagram, 0 MA Request/Grant

196

~J1.JL.rL=

CLK

,4>

REOH....J.

TMOUT

1,*,

1

1

I

-;-'~
'-

11':::,I I ±, 'n-J-» 1
I
1

1

'"

I
I

1

-J--lF

I

ADREN_H_--,-I....;.,_,,_,
I

DATEN L

1

,

I

I.,'

1 )'

i~ 1

I'I

1 ~
1I,.

-l~t"I'

I, " '

1

~

1-

1

1

!--!I"I-r-_ __
,I
,

I

1 "

1

TSYNC H
DIN H

RPLY H

'VIASTER H

Figure 23

DCOlO Timing Diagram (Sheet 1 of 2)

/

ClK

.JLJ1.nSUU1,J1JLJ""LJl.JLJlSUlJL.
I

I ,

DATIN L

~

-I 1-'"

DATIO.:J

I

REQ H '

"I'll

ADREN~

I';

I

_

I .,

1
I

"
,I
I HI,
I

I

;:

I II

I

I,,,

1

II

I

I It

I

II

I
I

,I

1
1

i

I
I

I i Ii '
I - 1
r- ", II
1-

f-

I ./

I
1",
1

\I

II"jr.:-

I
I
I
I

~'.

I

i

1
_ _ _ _ _ _ _t_"_-i--;~

RPLY H

\

;

,I

I

'

,
I

:

I

I

I

~III;--_~_
/-113

1

.
....,

1-120

"

r

III'-_ _ _~.

I"-,r- 1

-

I'M:,

-\"'1-

'''4 r-r----------

DATEN L

L-..,,'" J~

CNT4 H

"

" ..., 1-

1
"

./

MASTER H

OCCURS ONE CLOCK CYCLE AFTER THE NEGATION OF Dour

Figure 23

I

I
1"4',.....,1-'-------I
I-IL'"
I,~,-,
I. --.,_ _ _ _ _ _ __

DOUT _H_ _ _ _ _ _ _~I---'I!

I"

::

I

I

----~

NOTE

.

'

1

1"1
SYNCH

I

I

I

I

--"- I r-'"

I

.,

OC010 Timing Diagram (Sheet 2 of 2)
197

ClK

~~J4Jl.J1J1JU1Jl,JlJlJl
I

I
REO H

'~t,oll

III
I
I

DAllal::;] 1-1"

'It

I

I

I ))

I

I .~JlI
I II I -.I t- I "

I

I

I

IL,

I

--iI-I,.,

-1/-'"

AOREN~

I

I

II

I

'f~

______--7-_~I~)'~/_',_I---~1),~
DATEN l
I'
,-, ~}.'J'
I"-I/- '., I
I ~~,
TSYNC H_ _ _ _- - "
I'
I I
DIN H

_____I~I",
~r!! 1-I ~I'.

I
I
I,
I., I
,

I 1/

'II
)J
I

1-1 /-1"
I

RPlY H

----:--~,J

~,

DOUl H

--------i),~~----~)>--I1-, _ _ _t_1J_-I~(L

Figure 24

I It

I

I

I
I

I
I

I
I

')1

I

,

I

II"-ll-I I
I
IJTI
1" I
I , I
I I]0-l~
I
I

lit

4~,
~~

NOTE '" OCCURS ONE CLOCK CYCLE AFTER NEGATION OF

I

If'
I
I

1"-11-1
1
"

1II1
I I

IH I ' It I

'I
~~

I

_.-.j~,,,
1:*1 I-t~.
4,,,-,_ __

Dour

DC010 Timing Diagram (DATIO-Multiple Transfer)

END OF 4TH
TRANSFER
ClK
REO H

DATENl----~--~»~-------ttt~--~-------------

~

It

BDMR l
TMOUT L

1-'"

f~

---~--I~---;''''''

-+1-:1--,-,.----------I

I

I

----,

CLK
REO H

,e

CNT4 H

END L

MASTER H

~11-'- - - - - f . ) . I - - - - - - '
II

BOMR l

TMOUlL _ _ _ _ _ --;..---~
BOMGI L

Figure 25

DC010 Timing Diagram (Time-Out)

198

Table 11

Input Signal .

~

~

Switching Characteristics

Output Signal

Propagation
Delay (ns)

Time

Name

Polarity

Name

Polarity

Test
Conditions

Min

t2
t3
ts
h
ta
tl1
t,S
t'6
t17
t'9
t20
t21
t23
t2s
t26

BDMGI
BDM'}f
REO
BDMGI
BDMGI
ClK
ClK
CLK
ClK
CLK
ClK
ClK
ClK
CLK

H-L
L-H
L-H
H-l
H-l
H-l
H-l
H-l
H-l
H-l
H-l
H-L
H-l
H-L
H-l

BOMGO
BDMGO

H-L
L-H
H-L
H-L
L-H
L-H
l-H
H-l
L-H
H-L
H-L
L-H
l-H
H-L
H-L.

Load A
Load A
Load A
Load A
Load A
Load B
Load B
Load B
Load B
load B
Load B
Load B
load.B
Load B
Load B

95
20
25
85
117
15
18
20
18
18
18
30
cSO
20
.20

.

Cl~

BDM~

rM.OUT
BDMR
ADREN
SYNC
ADREN
DIN /
DIN \
SYNC
TMOUT
DOUr
Dour
DATEN

T'1 represents the first time AOREN is asserted.
t33 represents the subsequent times that ADREN is asserted.
tThese propagation delays meet the following requirements.
. tJ~-t27 ..; 20 ns
t,s-tte < 10 ns
t23-t26 .; 45 n8
t'5-t17 < 10 ns
ta-t3B ~ 27 ns
t'8-t28 < 10 ns

Max

220
60
70
230
306
60
60t
65t
60t
60
60
90
\ 175
65t
65t

"

Table 11

Switching Characteristics (Cont)

!'
Time
t31
t27
t33 •
I\)

o
o

t~5
t36
t37
t38

Input Signal
Polarity
Name
RPLY
CLK
CLK
TMOUT
BoMGI
CLK
RSYNC
or REPLY

H-L
H-L
H-L
L-H
H-L
H-L
H-L

Output Signal
Name
Polarity

Test
Conditions

DATEN
DATEN
AoREN
BoMR
MASTER
MASTER
MASTER

Load
Load
Load
Load
Load

H-L
L-H
L-H
H-L
L-H
H-L
L-H

B
B
B
B
B
Lo~d B
Load B

Propagation
Delay (ns)
Min,.-, Max

20
20
18
20
90
18
10

65
65t
60
75
242
66
58

·tlt represents the first time ADREN is asserted.
t33

represents the subsequent times that ADREN is asserted.

tThese prop~gation delays meet the following requirements.
t1s-t1e __ 10 ns
t2S-t27
20 ns
t1s-tl7 < 10 ns
t23-he < 45 ns
t1e-he < 10 ns
te-t3e ;> 27 ns

<

J

Specifications
DC003 Electrical Characteristics
DCOO3 TTL (Non-Bus) Interface
(Specification Group I - TTL Input and Output Pins)
Parameter
Name

Requirements
Svmbol

High-level input
voltage

V,H

low-level input
voltage

V,L

,Input clamp voltage

VI

Vee
4.75 V
II
'-18 mA

High-level output

VOH

Vee
4.75 V
10
-1 mA

Low-level output
voltage

VOL

Vee
4.75 V
10
20 mA

Input current: at
maximum input
voltage

I,

Vee
5.25 V
VI == 6.5 V

High-level input
current

IIH

Vee
5.26 V
V,
2.7 V2

Low-leveJ input
current

'lL

Vee
5.26 V
V,
0.5 V3

Short-circuit output current

lOS

Supply current

ICC

volta~e

.../

Conditions 1

Min

Max

2.0

=

=

=

=

=

V

0.8

V

,....1.2

V

2.7

=

V

0.5

=

=
=

=

-0.55 mA

211H

= 100 J.LA at pins 12 and 15.
= -2.0 rnA at pins

= 0° to

JJ.A

,#

-40

= 5.25 V

'Ambient operating temperature (TA)
specified.
311L

mA

60,..,.

='5.25 V4,5

VCC

V

=

Vee

/

Unit

-100 rnA
140

+ 70° 'e

rnA

unless otherwise

12 and 16.

4Not more than one output shall be shorted at a time and duration shall
not exceed 1 second.
5Does riot apply to pin 4.

201

DC003 BUI Driver
(Specification Group II - Open Collector)
Parameter
Name

R84uirements
Symbol

Output reverse
current

lOR

Low-revel output
voltage

VOL

1Ambient

Conditions'
Vee
VOH

Min'

= 4.75 V

= 3.5 V '
Vee = 4.75 V"ISINK = 70mA
ISINK = 16 mA

operating temperature (TA) = 0 0 to

+70~

Max

Unit

25

J.LA

0.8
0.5

V
V

e unless otherwise

specified.

DC003 Bus Receiver
(Specification Group III - High Input Z)
~

Requirements

Parameters
Symbol

Name

Conditions'

= 4.75 V

High-level input
voltage

VIH

Vee
Vee

= 5.25 V

LOW-level input
voltage

VIL

Vee
Vee

= 4.75 V'
= 5.25 V

Input cla":,p
voltage

VI

High-level input
current

IIH

Low-level input
current

1 Ambient

specified.

,

=

Vee
4.75 V
II
-18 mA
II
+18'mA
(pins 10 and
17 only)

=

IlL

V
V
1.30
1.47

V
V
\.

=

40

IJ.A

=

40

J.LA

=

-10

J.l.A

=

-10

J.LA

VI
OV
Vee
0 V
(Do not do for
pins 10 and 17)
Vee
5.25 V

operating temperature (TA)

1.53
1.70

Unit

V
V

VI
3.8 V
Vee
0 V
(Do not do for
pins 10 and17)
Vee
5.25 V

=

Max

-1.2
6.25

=

=

Min

=

202

O? to +70 0 e unless otherwise

DCOO4 Elec~rical C,haracteristics

(/

TTL (Non-Bus) Interface
(Specification Group I - TTL Input and Output Pins)
Parameter
Name

Requirements
Symbol

Conditions'

Min

Max

Unit

I
High-level inpot
voltage

V,H

Low-level input
voltage

V,L

Input clamp
voltage

V,

Vee
4.75 V
'I = -18 rnA

High-level output
voltage

VOH

Vee = 4.75 V
10 = -1 rnA

Low-level output
voltage

VOL

Vee = 4.75 V
10 = 20 rnA

Input current at
maximum input
voltage

I,

Vec = 5.25 V
V, = 5.5 V2

High-level input·
", current

IIH

Vec = 5.25 V
VI \= 2.7 V2

50

Low-level input
current

III

Vec = 5.25 V
V,
0.5 V

-0.70 rnA

Short-circuit
output current

lOS

VCe = 5.25 V3

Supply current

ICC

Vee = 5.25 V

2.0

=

V

0.8

V

-1.2

V

/

"

~

2.7
0.5

V
rnA

=

=

V

-40

#LA

-100

rnA

120

rnA

Ambient operating temperature (TA)
0 0 to + 70 0 e unless otherwise
specified.
2Limits for pin 19 are:
'I
1.40 mA; IIH
-2.25 mA min, -·3.85 mA max.
IlL = -4.5 inA min, -800 mA max.
3Not more than one output shall be shorted at a time and the duration
shall not exceed 1 second.
1

=

=

203

DC004 Bus Receiver
(Specification Group'" - High Input Z)
Requirements

Parameter
Symbol

Name-

\

Conditions'

Min

=

1.53
1.70

Max

Unit
V
V

High-level input
voltage

V,H

Vee
4.75 V Vee = 5.25 V

Low-level input
voltage

V,L

Vee
Vee

= 5.25 V

= 4.75 V

1.30
1.47

V
V

Input clamp
voltage

V,

Vee = 4.75 V
" = -18 mA

-1.2

V

High-level input
current

IIH

VI = 3.8 V
Vee = O,V
Vee
5.25 V

40
40

Jl.A
Jl.A

Low-level input
current

IlL

VI = OV
Vee= 0 V
Vee = 5.25 V

-10
-10

Jl.A
Jl.A

1Ambient

=

operating temperature (TA) = 0°

t~

t 70°

e unless otherwise

speci~

fied.

/

DC004 Bus Driver
(Specification Group III - Open Collector)
Parameter
Name

Requirements
Symbol

Output reverse
current

'OH

Low-level output
voltage

VOL

Conditions'

= 4.75 V
= 3.5 V
Vee = 4.75 V
70mA3

Vee
VOH

'SINK

-I SINK
'SINK

lAmbient operating temperature (T.,J
cified.

=

'-

=

16 mA3
15 ,,",4

Min

Max

Unit

25 2

j£A

0.8

V

0.5

V

0.5

V

= 0° to 70° C unless otherwise spe/

265 j£A for pin 18 (RXeX H).
3Applies to Pin 18 BUS RPLY only.
4Applies to, Pin 18 RXCX only.

204

~

DCOO6 Electrical Characteristics
De006 TTL (Non-Bus) Interface
(Specification Group I - TTL Input and Output Pins)
Requirements

Parameter
Name

~

Symbol

High-level input
voltage

VIH

Low-level input
voltage

VIL

Input clamp voltage

VI

Conditions'

Min

Max

2

'<-,

Vee = 4.75 V

II

= -18 mA

Unit
V

0.8

V

-1.2

V

High-level output
voltage

VOH

Vee = 4.75 V
10= -1 rnA

Low-level output
voltage

VOL

Vee = 4.75 V
10 = 20 rnA

Input 'current at
maximum input
voltage!

I,

Vee = 5.25 V
VI = 5.5 V

High-level input
current

IIH

Vee = 5.25 V
V, = 2.7 V
REe
XMIT

100
50

#LA
#LA

_ Vee = 5.25 V
VI = 0.5 V
REe
XMIT

-2.2
-1.1

rnA
rnA

-100

mA

120

mA

Low-level input
current

Short-circuit output
current
Supply current
Off state (highimpedance state)
output current
(OAT pins only)

III

Vee

lOS
ICC

to

f\

= 5.25 V2

Vee = 5.25 V

(OFF) Vee'= 5.25 V
VI = 3.65 V
VI = 0.5 V

3.65

V

0.5

V
rnA

-40

100
#LA
-0.36 rnA

Ambient operating temperature (TA) = 0° to + 70 0 e unless otherwise specified.
2Not more than one output shall be shorted at a time and the duration shall not
, exceed 1 second.
1

205

OC006 Bus Receiver
(Specification Group II - High Input Z)
Requirements

Parameter
Symbol

Name
High-level input
voltage

VIH

Low-level input
voltage

VIL

Input clamp
voltage

VI

High-level input
current (includes
open-collector
leakage on bus
pins)

IIH

MENB

Conditions'

Min

= 4.75 V
= 5.25 V
Vee = 4.75 V
Vee = 5.25 V
II = -18 mA
Vee = 4.75 V
VI = 3.8 V /

1.53
1.70

Vee
Vee

Vee

Low-level input
current

III

Unit
V
V

1.30
1.47

V
V

-1.2

V

40

40
65
65

p.A
p.A
p.A
p.A

-10
-10

p.A
p.A

/

Vee
BUS

Max

=0 V
= 5.25 V
=0 V
= 5.25 V

Vee
Vee
VI
0.5 V
Vee = 0 V
Vee
5.25 V

=

=
'Ambient operating temperature (TA) = 0

0

to +70 0 e unless otherwise speci-

fied.

DCOO5 Bus Driver
(Specification Group III -Open Collector)
Parameter
Name

Requirements
Symbol

Conditiona'

= 4.75 V
= 5.25 V

High-level output
current (reverse
9u,rrent - match
output onlv2

IOH

Vee
VOH

Low-level output
voltage

VOL

Vee
4.75 V
ISINK
a-mA
(Match)
ISINK
70 mA
(Bus)
ISINK
16 mA
(Bus)

=
=
=
=

Min

Max

Unit'

25

p.A

0.5

V

0.8

V

0.5

V

Ambient operating temperature (TA) = 0 0 to + 70 0 e unless otherwise specified.
2For bus pins. see "H under specification gr,up II.
1

206

DCOO6 (Specific~tion Group IV - Ternary'State Inputs)
Requirements

Parameter
Name

1

Symbol

low-level input
voltage

VIL

High-level input
voltage

VIH

Open circuit input
voltage

VOP

Min

Conditions'

Max

Unit

0.3

V

4.75

2

.4.75-.:..::....---

RECH

TRPLYH
INWo H

I
I
I

r------·----------1
NON-EXISTENT ADDRESS TIME-OUT

I

I
CSRWHB

+5V

f
16

INIT H

+3 V

R15

.".

+5

1000 pI

15K

(TOS+INITlH

CSRWHB
DATA 15

L __
Figure30

__-l
Typical Application (Miscellaneous logic)

(Sheet 2 of 3)

219

r=~~~~----~--------l

I
I
I
II
I
I
\--

I

BRPL Y/AF2
TRPLY
RPLY H

BDIN

LlA~2

TDIN
RDIN

I
I

I
I
I
I

TSYNC

I
I

1

I
I

__

BDOUT/AE2
TDOUT H

~

8641/E20

I'
I
r.

MASTER H

-I

I
DATN H

I
I

I

INWDL
INWD H

I

J_
WCNTO L

8641/E2

-I

I
I
I

I

. L ________________ J
Figure 30

Typical Application (Miscellaneous Logic)
(Sheet 3 of 3)

220

The DCOOS transceiver receive/transmit control determines the state of
the DC005 transceivers on Figure 26. Normally, the transceivers are in
the receive state to accept device addresses from the LSI-11 bus. When
REC H is asserted (high), XMIT is negated (low). XMIT is asserted (high)
when transferring data to the LSI-11 bus (T DOUT. DATEN. and ADREN
are high; TRPLY. INWD are low). REC is asserted (high) when receiving
data' from the LSI-11 bus (TDOUT. DATEN. and ADREN are low;
TRPLY. INWD are high).
The control/status register (CSR) (Figure 29. sheet 2) has six active
bits and is a read/write register comprised of 74LS367 tri-state drivers
and flip-flops which are part of other logic circuits shown on
Figura
29. sheet 1. and Figure 30. sheet 3. Figure 31 shows the CSR
format. The CSR bits are described in Table 12.

UNUSED

13

UNUSED

09

INTERRUPT
ENABLE
FOR BIT 15

04

USER
TRANSFER
REQUEST

BUS TIME-OUT
(NON-EXISTENT
ADDRESS)

00

INTERRUPT
ENABLE
FOR BIT 7

BLOCK TRANSFER
COMPLETE
(WORD COUNT
OVERFLOW)
DOUT;DIN
1/0

Figure 31

Control/Status Register (CSR) Format

The quad transceivers (8641) supplement the DC005 transc~ivers for
interfacing to the LSI-11 bus. In this particular application. the 8641 s
are permanently enabled by grounding pins 7 and 9. -

Table 12
Bit
01 }
00
0203
04
- 05

!

Name

CSR Bit Descriptions
Description

Unused

DOUT/DIN

'When on a 1. indicate a DOUT
cycle; when ona 0,' indicate a DIN
cycle.

221

,
Table 12

CSR Bit Descriptions (Cont)

Bit

Name

Description

06

Interrupt 'enable for bit
7

07

Block transfer cOr1)plete

This bit must be set (1) to enable
the-word count overflow; interrupt
at the end of a block transfer. When
on a O. the interrupt is inhibited.
This bit sets ( 1) when· the " word
count register overflows. providing
bit 06 is set.

OS

User transfer request

09
10
11
12
13

}

The user's device must set (1) this
bit to make a bus request and transfer data. User REQ L (J1-PP) must
be driven low (0) to set bit OS. This
bit is alwavs read as a zero. This is
an example for test purposes.

j

Unused

14

Interrupt enable for bit
15

This bit must be set (1) to enable
the bus time-out interrupt. When on
a O. the interrupt is inhibited.

15

Bus time-out

This bit sets (1 ) when a slave on the
LSI-11 bus does not respond with
BRPlY within lOllS after being addressed. Bit 14 must be set (1) to
enable the bus time-out interrupt.

Wire Wrappable Module W9512

The W9512 module will accept a variety of IC package types and discrete
components. The printed circuit on each board connects the a,ppropriate
edge connector pins to the Vcc plane on Side 2 of the board and the ground
plane (GNO) on Side 1. The remaining edge connector pins terminate to a
double row of wire wrap 'pins for user designated functions. Each module
also includes a premounted 40-pin male cable connector to a~ow an interface cable to be' attached to the module logic. The pins of the cable connector are also terminated to a double row of wire wrap pins. Each board
contains insulated standoffs to maintain the required clearance between
adjacent modules and prevent shorting of wire wrap pins. The wire wrap
pins and components are mounted on Side 2 of each module. The majority
of the r~ws of predrilled holes accept IC packages with pin spacings of 0.3''':
However, a universal area on the W9512 module is the area which accepts
Ie packages with standard pin spacings of 0.3", 0.4" and 0.6".
222

Total IC capacity on the .wire wrap 'module
27 16-pin IC's, 524-pin IC's, 3 40-pin IC's.

IS

as -follows: 32 14-pin IC's or

These capacities allow one pair of holes between each DIP for mounting additional decoupling capacitors. The Wg512 module is supplied without IC
sockets. IC sockets available through the handbook are the 954 (14-16 pins),
the 961 (24 pins) and the 962 (40 pins).

W9512 wire wrappable board is quipped with 40-pin male
interface connector.

IMPORTANT NOTE ON DMA CHIPKITS
The two DMA Bus Interface CHIPKITS, DCKll-AB and DCKll-AD, are new
products be.ng developed by DIGITAL, and are undergoiQg final applications
testing and review as of the publication date of this handbook-July, 1978.
Production quantities are expected about October, 1978. If you .have a
serious interest in using these CHIPKITS, contact us fOr the latest word on
availability. Write DIGITAL, Logic Products Sales Support, MKl-2/E13, Merrimack, NH 03054, or call us on our toll-free Hot Line, 8:30 AM to 5:00 PM
Eastern time: 800-258-1710. From New Hampshire locations or places outside the continental U.S., call 603-884-6660 .

.223

/

.

224.

GENERAL PURPOSE LOGIC & CONTROL MODULES
M-SER/ES, A-SERIES, K-SERIES-FOR INTERFACING, COMMUNICATIONS,
AND SPECIAL APPLICATIONS

225

GENERAL PURPOSE
LOGIC AND
CONTROL MODULES
This section describes the computer industry's most extensive line of general·
purpose logic modules-modules used in DIGITAL's products and modules
used by thousands of customers for computer interfacing, instrumentation,
data gathering, and control. The module descriptions are organized into three
main subsections: M Series, A Series, and K Series.
M Series high~speed monolithic integrated circuit logic modules employ TTL
(tranSistor-transistor logic) circuits which provide high speed, high fanout,
large capacitance drive capability, and excellent noise margins.
In addition to the reduced cost of integrated circuits, DIGITAL's advanced
manufacturing methods and computer-controlled module testing have resulted in considerable production cost savings, reflected in the low price of all
OM Series modules.
A Series analog modules support the M Series by providing a two-way translation between continually varying real-world voltage measurements and the
digital realm of control and computation.
K-Series industrial control modules offer exceptional immunity to electrical
noise. In typical process-control applications, inputs are from limit switches,
photocells, or(the like; outputs are to control motor starters, relays, solenoids,
or lamps. K-Series modules have many advantages over electromechanical
control devices, and can also connect to a computer if a suitable high-speed
TTL interface is used.
'-

The associated hardware for these general purpose modules, such as module
connector blocks, mounting panels, cabinets, and power supplies, is summarized elsewhere in this handbook and described in detail in the Hardware/
Accessories Catalog, also published by DIGITAL.

226

,

M SERIES
GENERAL CHARACTERISTICS
M Series high-speed, monolithic integrated circuit logic modules employ TIL
(transistor-transistor logic) integrated circuits which provide high speed,
high fan out, large capacitance drive capability and excellent noise margins.
The M Series includes a full digital system complement of ba'sic modules
which are designed with sufficient margin for reliable system operation at
frequencies up to 6 MHz. Specific modules may be operated at frequencies
up to 10 MHz. The integrated circuits are dual in-li,ne packages.

-

-

The M Series printed circuit boards are identi.:al in size to the standard
FLIP cHrpTM modules. The printed circuit board is double-sided providing
36-pins in a single height- module. Mounting panel~ and 36-pin sockets are
available for use with M Series modules. Additional information concerning
applicable hardware may be found in the Cabinets & Parts section of this
handbook as well as the Hardware/Accessories Catalog published by DIGITAL.

227

OPERATING CHARACTERISTICS
Power Supply Voltage:

? Volts ±

5%

Operating Temperature Range: o--Q to 70°C
Speed: M Series integrated circuit modules are rated for operation in a system environment at frequencies up to 6 MHz_ Specific modules may be operated at higher frequencies as indicated by the individual module speCifications.

LOGIC LEVELS AND NOISE MARGIN
A gate input will recognize 0.0 vo~s to 0.8 volts as logical LO and 2.0 volts
to 5.0 volts will be recognized as a logical HI. An output is between 0.0 volts
and 0.4 volts in the 10gicaf..LO condition. The logical HI output condition is
. between 2.4 volts and S.C} volts. f,igure 1 shows diagrammatically the acceptable transistor-transistor logic levels_ The worst case noise margin is 400
millivolts,that is, an output would have to make at least a 400 millivolt excursion to cause an input which is cCimnected to it to go into the ind~termined
voltage region_ For instance if an output were at 0.4 volts (worst case logical
LO) there would have to be a
400 mv swing in voltage to cause inputs
connected to it to go into their indetermined region.

+

Input and Output Loading: The input loading and output drive capability of
M Series modules are specified in terms of a specific number of unit loads.
Typically the input loading is one unit, however certain modules may contain
. inputs which wtll present greater than one unit load_ The typical M Series
module output will supply 10 unit loads of input loading. However, certain
module outputs will deviate from a 10 unit load capability and provide more
or less drive:Always refer to the individual module specif{cations to ascertain actual loading figures.
Unit Load: In the logic 0 state, one unit load requires that the driver be able
to sink 1.6 milliamps (maximum) from' the load's. input circuit while maintaining an output voltage of equa.l to or less than +0.4 volts. In the logic 1
state, one unit load requires that the driver supply a leakage current 40
microamps (maximum) while maintaining an output voltage of equal to or
greater than +2.4 volts.

.228

Figure 1

logic levels

NAND Logic Symbol: Logic symbo1ogy used to describe M Series modules is
based on widely accepted standards. Logic symbols and a truth table for the
NAND gate are shown in Figure 2.

A~OUTPUT
B~A'B

A

~.

OJTPUT.

B~A+B

Figure 2

A

B

OUTPUT

L

L

H

L

H

H

H

L

H

H

H

L

NAND Gate Logic Symbol and Truth Table

The first symbol is visually more effective in applications where two nigh in·
puts are ANDed to produce a low output. The second symbol better repre·
sents an application where low inputs are ORed to produce a .high output.

229

NAND GATE FLlP~FLOPS
RS Flip-Flop: A basic Reset/Set flip-flop can be constructed by connecting
two NAND gates as shown in Figure"3.

PREVIOUS
STATE

SET---a

I

\

L
H
L
H
H

o

RESET--~

L
L
H

INPUT
CONDITION

RESULT

0

SET

RESET

1

0

H
L
H

L
H

H

H

L
H

L

H

L
H
H

L
H

LH

H

NO CHANGE
NO CHANGE
NO CHANGE

L

NO CHANGE

H

L

L

H*

H*

L

L

L

H*

" H*

H

l

"'Ambiguous state: In practice the input that"stays low longest will assume
control.
Figure 3

RESET/SET NAND Gate Flip-Flop

CLOCKED NAND GATE FLIP-FLOPS
The Reset-Set flip-flop can be clock-synchronized by the addit!on of a twoinput NAND gate to both the set and the reset inputs. (See Figure 4_) One
of the inputs of each NAND ;s tied to a common clock or trigger line.
SET

CLOCK

o
RESET

Figure 4 Clocked NAN D Gate Flip-Flop

A change of state is inhibited imti1 a positive clock pulse is applied. The
ambiguous case will result if both the set and ,reset inputs are high when the
clock pulse occurs.
M SERIES GENERAL-PURPOSE FLIP-FLOPS
Two types of genera I.-purpose flip-flops are available in the M Series, both of
which have built-in protection against the ambiguous state characteristic of
NAND gate flip-flops.

230'

o
LOGIC SYMBOL

Figure 5
o Type Flip-Flop: The first of these is the 0 type flip-flop shown in Figure 5.
A low to. high transition at the C input causes the 1 output to assume the
state that the 0 input was at the time of transition. The 0 output will always
'assume the opposite state. In this way, the 0 flip-flop will store the signal
level at the 0 input- since subsequent changes at the 0 input will not affect
the flip·flop's state until the C input is again clocked with a low to high
transition. When the 1 output is high and the 0 output is low, the flip-flop is
said to be set. When the 1 output is low and the 0 output is high, the flipflop is said to be reset or cleared. The D flip-flop can be direct set by applying a low level or pulse to the S input. Likewise, it can be direct reset by
applying a low level or pulse to the R input. Signals at the Sand R inputs
will override those at the. C and 0 inputs.

o

type flip-flops are especially suited to buffer register, s,hift register and
binary ripple counter applications. Note that 0 type devices trigger on the _
leading (or positive going) edge of the clock pulse. Once the clock has passed
threshold, changes on the D input will not affect the state of the flip-fiop,.
uMASTER-SLAVE J-K FLIP-FLOP"
The two unique features of a J-K flip-flop are: A) a clock pulse will not cause •
any transition in the flip·flop if neither the J nor the K inputs are high during
the clock pulse, and B) if both the J and the K inputs are high during the
clock pulse, the flip-flop will complement (change states). There is no indeterminate condition in the operation of a J-K flip-flop.

A word of caution ·is in order concerning the clock input. The J and K inputs
must not be allowed to change states when the clock line is high, as the output will complement on the negative going voltage transition of the clock. It
is for this reason that the clock line must be kept low until it is desired to
transfer information into the flip-flop and no change in the states of the J
and K inputs should be allowed when the clock line is high.
The J-K flip-flops used are master-slave devices which transfer information
to the outputs on the trailing (negative going. voltage) edge of the clock
pulse. The J-K flip-flop consists of two flip-flop circuits, a master flip-flop
and a slave flip-flop. The information which is present at the J and K inputs
when the leading edge threshold is passed and during the clock high will be
passed to the master flip-flop (The J and K inputs must not change after the
leading edge threshold has been passed). At the end of the clock pulse when
the threshold of the clock is passed during the trailing (negative going
voltage) edge, the information present in the master flip-flop is passed to
the slave flip-flop. If the J input is enabled and the K input is disabled prior

231

to and during the clock pulse, the flip-flop will go to the "1" condition when
the trailing edge of the clock occurs. If the K input is eltabled-and the J input
is disabled prior to and during the clock pulse, the flip-flop will go to the
. "0" condition when the trailing edge of the clock pulse occurs. If both the
J and K inputs are enabled prior to and during the clock pulse, the flip-flop
will complement when the trailing edge of the clock pulse occurs. If both the
J and K inputs are disabled prior to and during the clock pulse, the flip-flop
will remain in whatever condition existed prior'to the clock pulse when the
trailing edge of the clock pulse occurs.

s
--~c..Il
----I K

01----

,

R

Figure 6. Master·Slave J-K Flip·Flop

Figure 7 is a truth table for the J·K flip-flop showing all eight possible initial
conditions.

INITIAL CONDITIONS
OUTPUTS
INPUTS

FINAL CONDITIONS
OUTPUTS

1

0

J

K

1

0

L
L
L
L
H

H
H
H
H
L
L
L
L

L
L
H
H
L
L

L
H
L
H
L

H
H
L
L
L

H

L
L
H
H
H
L

H

L

H

H

H

L

L
H

H
H
H

H

Figure 7. Master-Slave J-K Flip-Flop Truth Table

232

,

UNUSED INPUTS (GATES AND FLIP.FLOPS)
Since the input of a TTL device is an emitter of a multiple-emitter transistor,
care must be exercised when an input is not to be used for logic signals.
These emitters provide excellent coupling into the driving portions of the
circuit when left unconnected.

i

To insure maximum noise immunity, it is necessary to connect these inputs
to either ground or to a source of L,

mA (max.)

160

Pins

A2
C2, T1

The M133 provides general-purl?ose high-speed NAND gating.

252

GATES

M135
8 3·INPUT NAND GATES

M SERIES

Length: Standard
Height: Single
Width: Single

)

1
.3 El

•

f1

1.3_
1.3 HI

-,

:
__

.Dl

@)

)

I )
..
: - - t -_ _)

@]

.M2

[ill

@]

.NI~

)

.52

• UI@]

)

VI @]
.,2

~Pl

~,.;..:~_

.H2

Volts

+5
GND

Power
mA (max.)

100

Pins
A2

C2.T1

The'M135 module consists of eight high-speed, 3-input, positive logic NAND
gates.
SPECIFICATIONS
Maximum propagation delay to a logic HIGH or LOW is 10 ns.

253

GATES

MI37
"SIX 4 INPUT NAND GATES
Length: Standard
Width: Single
Height: Single

Volts

+5V

GND

Power

mA (max.) .
lOOmA

Pins

A2

C2, T1

The M137 Module consists of six high-speed, 4-input positive logic NAND
gates.
Maximum propagation delay to a logic High or Low is 10 ns.

254-

'M139
3 8·INPUT NAND GATES

GATES
M SERIES

Length: Standard
Height: Single
Width: SillJle

-,-

Volts

+5
GND

Power

mA(max.)

50

Pins
A2

C2, T1

The M139 module consists of three high-speed, a-input, positive logic NAND
gates. Pins Uland VI provide two separate logic HIGH sources (+3 V,) each
capable of holding up to 50 unused M Series inputs HIGH.
SPECIFICATIONS
Maximum propagation delay to a logic HIGH or LOW is 10 ns.

255

GATES

M141
NAND/OR GATES

I

Length: Standard
Height: Single
Width: Single

+IIV

HiV

+IIV

UK

I.!5K

Volts

"

B

0

0

A=B

1

1

A8

A=B

A>B

12-BIT MAGNITUDE

COMPARATOR

A<8

A=B

A B, A
8 orA < 8 will be
high to indicate the relative magnitude of the two binary input words.

=

The M168 Comparator may be cascaded to compare longer words. The outputs T2, U2, and V2 should be connected to the corresponding inputs of the
next comparator which are AI, B1, and C1 respeCtively. The inputs of the
first comparator must all be made a logical "I",
The propagation delay time from Data (A and B) to outputs is 48 nsec typical
and 72 nsec maximum for one unit.
When cascading the total typical time is 48 nsec plus 36 nsec per additional
unit.- The total_ maximum time is 72 nsec plus 54 nsec per additional unit.

267

INPUTS

A=B

A>8

OUTPUTS

AB A=B

Data

AB

1

0

o·

1

0

0

1

0

0

1

0

()

A=B
AB
A=B
AB
A=B
\
Ao ~:: Dt---[>o -

0200

K200

~::

. DI---[)o -

5200

*=50mA ItRIVE
Volts

Power
mA (max.)

+5

71

GND

Pins

A2

C2

The M660 Cable Driver consists of three NAND gate circuits each of which
will drive a lOO-ohm terminated cable with -M Series levels or pulses of duration greater than 100 ns. The output is not open-collector. It is a discrete
transistor totem pole configuration similar to an Ie gate providing high current drive in both the high and low directions.
SPECIFICATIONS
Outputs: Can sink 50 rnA at a logic LOW, and can ~ource 50 rnA at a logic

HIGH.

l

318

MUlTI-

M671

VIBRATORS

M TO K CONVERTER
(ONE-SHOT)

M SERIES

Length: Standard
Height: Single
Width: Single

• Will DRIVE 9 M SERIES LOADS'OR -15 K SERIES LOADS

Volts

Power
mA (max.)

+5

112

GND

Pins

A2

C2

The M671 M Series to K Series Converter contains four pulse stretching circuits which can convert an M Series input pulse of duration exceeding 50 ns
-to complementary K Series output pulses of 10 to 15 "'s.
FUNCTIONS
Triggering: When the ENABLE input is HIGH, the delay is triggered by the
negative-going edge of the trigger input pulse:

319 _

•

---U-U-INPUT

~

~OUTMS
This circuit is insensitive to input transitions during its timeout period as
shown in the example above.
Increasing Output Pulse Width: Non-electrolytic capacitors can be connected
to the split. lugs provided in each circuit if. K Series output pulse widths
longer than 15 iJ.S are desired. Pujses of up to 40 seconds are possible using
this technique. When capacitance is added, the output pulse width is increased by 6400 C seconds where C is the capacitance added in- farads.
Precautions: Unused inputs should be connected,o logic levels that will hold
them in their unasserted states. Unused inputs that would be asserted High
should be grounded. Unused inputs that would be asserted Low should be
connected to a source of logic High. Also refer to "Unused Inputs" in the
alphabetical index.
-

"'
/SPECIFICATIONS
/ Output drive: Each output is capable of driving a 15 rnA load.

320

M706
TELETYPE RECEIVER

COMMUNICATIONS
M SERIES

Length: Standard
Height: Double
Width: Si~gle.

a

DEVICE
SELECTOR
CODE
XV

/

ENABLE OS 1 t-A",-Pl'-11---t_ _ _

READER ON 1 t-AV
....Z=-o--tr-_ _ _ _-t-_ _ _-Q

1--_ _ _ _ _ _--I---t..,S=L=Z;10 REAOER

ax '1i~ 3 rAN~1---;--------1
SRI

PIN CONNECTIONS:
FOR 5 OR 8 BIT CODE
5 BIT-AMZ TO AJZ
ARI TO GND
TO ARI
AJ2 TO AKI

a BIT-AMZ

FOR STOP TIME
tOUNITS-EPZ TO BTZ
BRZ TO BU2
1.5UNITS-BP2 TO 851
.
BR2 TOSU2
2.0 UNITS-SP2 TO BTZ
BRZ TO SVZ
MUST SE
CONNECTED

SHIFT
REGISTER D-------f--I~=-=-f

BTZ
SUI

*=THIS OUTPUT CAN DRIVE A·
20mA LOAD TO.0.1 VOLTS

Volts

+5

GND

Power
rnA (max.)

4.00

Pins
AA2, BA2
AC2, ATl, BC2, BTl

NOTE: Refer to the M7390 module description

321

as a possible substitute for the M706.

The M706 Teletype Rec~iver is a serfal-to-parallel teletype code ~onverter self
-contained on a double height module. This module includes all of the serialto-parallel conversion, buffering, gating, and timing (e~cluding only an external
clock)necessary to transfer information in an asynchronous manner between
a serial data line or teletype device and a parallel binary device.' Either a
5-bit serial charac,er consisting of 7.0, 7.5, or 8.0 units or an 8-!>it serial
chara.cter of 10.0, '10.5, or 11.9 units can be assembled into parallel form
by the M706 through the use of different pin connections on the module.
When· conversion is complete, the start and stop bits accompanyi(lg the serial
character are removed. The serial character is expected to be received with
the start bit first, followed by bits 1 through 8 in that order, and completed
by the stop bits. Coincident with reception of the center of bit eight, the
Flag output goes low indicating that a new..character is ready for transmission
into the parallel device. The parallel data is available at the Bit 1 through
Bit 8 outputs until the beginning Clf the start bit of a new serial character as
received on the serial input. See the timing diagram of Figure 1 for additional
information.

In

addition to the above listed features, the M706 includes the necessary

~Dgic to-provide -rejection of spurious start bits I~ss than one-half unit long,

and tfalf-duplex system operation in conjunction with the M707. Device
selector gating is also provided so that this module can be used on the
positive 110 bus of either the PDP8/ I or the PDP8! L. .
Inputs: All inputs present one TTL unit load except where noted. When input
pulses are required, they must have a width of 50 nsec or greater.

fr~qUency

Clock: The clock
must be e'ht times the serial input bit rate
(baud rate). This input can be either pulses or a square wave. Input loading
on the clock line is three unit loads.
Enable: This input when brought to ground will inhibit reception of new characters. It can be grou.d any time during character reception, but returned
high only between the time the Flag output goes to ground and a new char*ter start bit is received at'the serial input. When not used this input should
b'e tiec;f to a source of +3 Volts.
I/O CJear: A high level or positive pulse at -this input clears the J;lag and
initializes the state of the control; When not used, or during reception, this
input should be.at ground.
Code Select Inputs: When a positive AND condition occurs at these inputs
the following signals can assume their normal control functions-Flag Strobe,
Read Buffer, and Cle3'f Flag 1. Frequently these inputs might be used to
multiplex receiver modules when a signal like -Read Buffer is common to
many modules. The inputs can also be used for device Selector inliuts when
the M706 is used on the positive 110 bus of the POP8/ I or POP81 L. The code
select inputs must be present at least 50 nsec prior to any of the three
signals that they enable. If it i~desired to bypass the code select inputs,
they can be left open and the Enable D.S. line tied to ground.
Clear Flag l:A high level or positive pulse at this input white
inputs are all high, will clear the Flag. When not used, this
grounded. Propagation delay from input rise until the Flag
maximum of 100 nsec. The Flag cannot be set if this input

322

the code select
line should be
is cleared is a
is held high.

-

.

·

Clear F,ag 2: A high leve! or positive pulse at this input, independent of the~
state of the code select ~nputs, will clear the Flag. All other characteristics
~reidentical to those of Clear Flag 1.
Flag Strobe: If the Flag is set, and the code select- inputs are all high, a
positive pulse at this input will generate a negative going pulse at the Strobed
Flag output. Propagation delay from the strobe ---~------r--'~~~IO~AG
+5V

A81
ECHO 8 F

:::!!-._.-+-------+----+----4(1

120.0

PtNCONN~S;

5 OR 8 BIT CODE

BIT I

5BIT-AKI TO AJI
8BIT-AKI TOAK2

BIT2

Foro~ T~ TO BRZ

BIT 3

BIT 4

BIT 5

SHIFT

F"~__t-------__I REGISTER

1.5UNITS-8N2 TO BPI
2.0 UNlTS-BN2 TO 8Nt

BIT 6

8IT7

Alii
MUST BE

CONNECTED ALI
~

I FA",.SI:........,,--il-_ _ _ _ _ _ _ _ _ _- - I

Volts

t~D

Power
mA (max.)
375

NOTE: Refer to the M7390 module description as

326

Pins
A2

C2, T1

a possible substitute

for the M707.

The. M707 Teletype Transmitter is a parallel-to-serial teletype code converter
self contained on a double height module_ This module includes all of the
parallel-to-serial conversion, buffering, gating, and timing (excluding only an
external clock) necessary tot ransfer information in an asynchronous manner
betw~en a parallel. binary device and a serial data line or teletype device.
Either a 5--bit or an S-bit parallel character can be assembled into a 7.0,
7.5, or S.O unit serial character or a 10.0, 10.5, or 11.0 unit serial character
by the M707 through the use of different pin connections on the module.
When conversion is complete, the necessary start bit and selected stop bits
(1.0, 1.5, or 2.0 units) have been added to the priginal parallel character
and transmitted over the serial line. The serial character is transmitted with
the start blt first, followed by bits 1 through 8 in that order, and completed
by the stop bits. Coincident with the stop bit being put on the serial line,
the Flag output goes low indicating that the previous character has been
transmitted and a new parallel character can be loaded into the M707. Transmission of this new character will not occur until the stop bits from the
previous character are completed. See the timing diagram of Figure 1 for
additional information.
In addition to the above listed features, the M707 includes the necessary
gating so that it can be used in a half-duplex system with theM706. Device
selector gating is also provided so that this module can be used on the
positive bus of either the PDP8/ I or the POPS/ L.
Inputs:

All inputs present one TTL unit load with the exception of the Clock
input which presents ten unit loads.- Where the use of input pulses
is required, they must have width of 50 nsec or greater.

Clock:

The clock frequency must be twice the serial output bit rate. This
input can be either pulses or a square wave.

Bits 1 through 8: A high level at these inputs is reflected as a logic 1 or mark
in the serial output. When a 5-bit code is used, bit inputs I through 5 should
contain the parallel data, bit 6 should be considered as an Enable, and bits
7, S and Enable should-be grounded.
Enable: This
multiplexing.
transmission
for scanning
+3 Volts.

input provides the control flexibility necessary for transmitter
When grounded during a Load Buffer pulse, this input prevents
of a character. It can be driven from the output of an MI61
purposes or in t~e case of a single transmitter, simply tied to

Wait: '_f 'this input is grouncted prior to the stop bits of a transmitted character, it wili hold transmission of a succeeding character until it is brought
to a high level. A ground on this line will not prevent a new ct:iaracter from
being loaded into the shift register. This line is normally connected to Active
(0) on a M706 in half duplex two wire systems. When not used, this line
should be tied to +3 Volts.
Code Select Inputs: When a positive AND condition occurs at these inputs
the following signals can assume their normal control functions-Flag Strobe,
Load Buffer, and'Clear Flag!. Frequently these inputs might be used to
multiplex transmitter modules when signals like Load Buffer are common
to many modules. These inputs can also be used for device selector inputs
when the M707 is used on the positive bus of the POPS/I or POPSI L. The

327

at

, code select inputs must be present
least 50 nsec prior to any of the three
signals that they enable. If it is desired to by-pass the code select inputs,
they can be left open and the Enable DS line tied to ground.·
'
Clear Flag 1: A high level or positive pulse at this input while the code select
inputs ar~ all high, will clear the Flag. When not used, this line should be
grounded. Propagation delay from input rise until the Flag is cleared at the
Flag output is a maximum of 100 nsec. The Flag cannot be set if this input
is held at logic 1.

:

J

Clear Flag 2: A low level or negative pulse at this input will clear the Flag.
When not used this input should be tied to +3 Volts; The Flag will remain
cleared if this input is grounded. Propagation from input fall to Flag .output
rise is a maximum of 80 nsec. If it is desired to clear the flag on a load
buffer pulse, Clear Flag 2 can be tied to pin ARI of the module.
Flag Strobe: If the Flag is set, and the code select inputs are all high, a
positive pulse at this input will generate a negative going pulse at the Strobed
Flag output. Propagation delay from the strobe to output is a maximum of
30nsec.
1/0 Clear: A high level or positive pulse at this input clears the Flag, clears
the shift register and initializes the state of the control. This signal is not
necessary if the first serial character. transmitted after power turn-on need
not be correct. When not used, or during transmission, this input should be
at ground.

Load Buffer: A high level or positive pulse at this input while the code select
inputs are all high will load the shift register buffer with the character to be
transmitted. If the Enable input is· high when this input occurs, transmission
will begin as soon as the stop bits from the previous character are counted
out. If a level is used, it must be returned to ground within on~ bit time
(twice the period of the clock).
Outputs: All outputs pres~nt TTL logic levels except the serial output driv~r
which is an open collector PNP transistor with emitter returned to +5 Volts.
serial Output: This open collector 'PNP transistor output can drive 20 mA into
any load returned toa voltage between +4 Volts and -15 Volts. A logical
output or mark is +5 Volts and a logical 0 or space is an .open circuit. If
inductive loads are driven by this output, diode protection must be provided
by connecting the cathode of a high speed silicon diode to the output and
the diode anode to the coil supply voltage.
Line: This output can drive ten TTL unit loads and presents the serial output
signal with a logical 1 as +3 Volts and logical 0 as ground.
ACtive: During the time period from the occurrence of the serial start bit and
the beginning of the stop bits, this output is high. This signal is often used
in half duplex systems to obtain special control signals. Output drive is ~ight
TTL unit loads.
:328

Flag: This output falls from +3 Volts to ground at the beginning of the stop
bits driving a characte.r transmission. The M707 can now be reloaded and
the Flag cleared (set to +3 Volts). This output can drive "ten TTL unit loads.
Strobed Flag: This output is the NAND realization of the inverted Flag output
and Flag Strobe. Output drive is t~n TTL unit loads.
+3 Volts: Pin BJI can drive ten TTL unit loads at a +3 Volts level.

+5 Volts at 375 rnA .. (max.)

Power:

Size: ~tandard, double. height, single width FLIP CHIP module.

It)

0

+
a:

w
OLL
etLL

o=>
..JCD

It)

+

0

..J

0

+

0

It)

+

0

It)

+

w

~

0

0

It)

"-

>

~

0
et

w

c)

:J

..J

Z

.329

et
LL

0

It)

+
a:(\J
etc)

wet
..J..J'

OLL

0

GATES

MII03
TWO-INPUT AND GATES

M SERIES

Length: Standard
Height: Single
Width: Single

A1

L1

~

~
.
~
~
H1
~
,

.

C1

N1,O

81 .

1 M

•

D1

F1

1 E1

'0

~
P1

02

F2

1

E

1

J1

_

S1 10

'0

1 R1

0

~

-S2f101

~

~

_V2c:l

.

K1

~

~

+3V

Volts

+5
GND

Power

mA (max.)

Pins

80.

A2
C2,Tl

The Mll03 contains ten 2-input AND gates. Unused inputs on any gate must
be returned to a source of logic HIGH for maximum noise immunity. Two
pins are provided (UI and VI) as a source of +3 volts for this purpose.
APPLICATIONS
• Positive AND or negative OR gating

330

, . . . . - - - - - - - -... t.

GATES

Ml125
EXCLUSIVE OR GATES

M SERIES

Length: Standard
Height: Single
Width:· Single

1

~
~

~_Clr,;:;)

1
1 Ml

~

~_FllV\l

1

~

Nl

2.~-

1

N2

10

10

~_SllV\l

~_F2=

~

~

~_Klr.;;,

~

~

~

~
~

~-~

_S2JV\1

~

(IJR-JL/~

~

~

Power

Volts

+5V

mA (max.)

Pins
A2

100.

Cl, T1

GND,

The M1125 Module consists of ten 2-input exclusive OR gates and two +3
Vdc voltage divider sources. Each module circuit performs the X-OR function (A-e
'A-B) according to the following truth table. Gate output is high
when inputs are not the same.

+

TRUTH TABLE
INPUTS

L

OUTPUTS

L

L

'L

H

H

H

L

H

H

H

L

SPECIFICATIONS
Typical propagation delay time of the M1l25 is 12 ns.
~
331
J

Ml131
2-INPUT OPEN COLLECTOR
NAND GATE

GATES
M SERIES

Len.,gth: Standard
Height: Single
Width: Single

~
~~

~
11

NI •

I Ml

.

l2

~ ~
~
P2.
~ ~
~ ~
Dl

•...

N2 •

fl •

1 M2'

1 El

1

1
.- 1 Rl

•

51 •
.

1'

1.
I Jl

52 •

Kl. '.

) R2

-

H2 . . .
K2 •
IJ2

T2

V2 •

,

1 U2

• In the logic low state, the"output of this module will sink up to 16 mA per driver.

Volts

+5

GND

The
and
and
is a

Power
mA (max.)
71

Pins
A2

C2, T1

M1131 module consists of ten high-speed, 2·input NAND gate circuits
a +3 Vdc source. Each of the NAND gates has an open collector output
the outputs can be paralleled for a wired OR function. Each gate input
1- unit load and each unparalleled output will drive up to 10 unit loads.

APPLICATIONS
Logic gating. Wired·OR multiplexing
SPECIFICATIONS
-Typical gate propagation delay time is 10 ns.

332

GATES

M1307 ,r<'
FOUR-INPUT AND GATES

M SERIES

Length: Standard
Height: Single
Width: Single

"\

+3V

Volts

+5

GND

I :

Power
mA (max.)
100

~::

Pins
A2

C2, T1

The M1307 contains six high speed 4-input AND gates. Unused inputs on any
gate must be returned to a source of logic HIGH for maximum noise immunity. Two pins are provided (Ul and VI) as a source of +3 volts for this
purpose.
APPLICATIONS
• Positive AND,or negative OR gating l

,
333

"-

M1701

MULTIPLEXERS

...,

DATA SELECTOR

M SERIES

Length: Standard
H~ght:

<'

Single

Width:
,L1
HI
H2

so

J2

ICO}
lCl

K2

lC2

L2
Kl

SI
..,.. (MSB~

tlSB)

SELECT

"
DATA
INPUTS

lY

F2 10

2Y

02 10

IY

P2 10

2Y

10

lC3
STROBE 1

DUAL
MUX 1
OUTPUTS

E2
01
El
Fl
Jl

'CO} DATA

2Cl
2C2

INPUTS

2C3
STROBE 2

VI
Rl

R2
S2
U2
V2
UI

so

ICO}
1Cl
DATA
IC2

51
(MSB)

{lSBI

SELECT

INPUTS

1C3
STROBE I

DUAL
MUX 2
OUTPUTS

N2
MI
NI
PI
SI

'2Cl
CO} DATA
2C2

INPUTS

2C3
STROBE 2

Nolts

/

ct~D

Power
mA (max.)
110

334

,"
Pins
A2

C2.T1

The M1701 Data Selector contains two independent dual 4-line to 2-line
multiplexers on a single-height module. Each dual multiplexer has two groups
of DATA INPUTS, two STROBES, two OUTPUTS and common SELECT inputs.
An OUTPUT becomes active for a DATA INPUT when the DATA INPUT is
addressed by the SELECT lines and the corresponding STROBE brought LOW.
APPLICATIONS
• Multiplexing for parallel-to-serial conversion
• Timesharing
• Sampling
TRUTH TABLE
FUNCTIONS
SELECT
SI ~

DATA INPUTS
C3 C2 Cl CO

X

X

X

X

LL
L
L
H
H
H

L
L
H
H
L
L
H

X
X
X
X
X
X
L

H

H

H

X
X
X
X
L
H
X
X

X

=

X
-X
X

OUTPUT-V

H

L
L
H
L
H
L
H

X
L
H
X

L
H
X
X
X
X

STROBE

L
L
L

X

L

X
X
X
X

L
L

L

L

L

H

irrelevant _

PROPAGATION DELAY TIMES
PARAMETERf[

\

lltPLH
tPHL

FROM
(INPUT)

TO
(OUTPUT)

MAX UNIT

tPLH

Data

ns

Data

Y
'y

25

tPHL

30

ns

tPLH

Address

Y

40

ns

tPHL

Address

Y

40

ns

tPLH

Strobe

Y

35

ns

.tPHL

Strobe

Y

30

ns

= propagation delay time, Low-to-High-Ievel output.
= propagation delay time, High-to-Low-Ievel output.

335

\

MULTIPLEXERS

M1713
16-LINE TO- I-LINE

DATA SELECTOR

M SERIES

./

Length: Standard
Height: Single
Width: Single

S2

0

T2
M1

2

Nt

3

PI

4

R1

5

S1

6

L1

7

F1
_/

DATA
INPUTS

8

Ht

9

J,

10

Kt

W

11

M2

12

L2

13

K2

14

E2

15

N2-·
J2

O(MSB)

C

H2

B

F2

A(LSB)

Volts

t~D

Power
mA(max.)

70

336

Pins
A2

C2.T1

P2 10

The M1713 modl,lle is a l-of-16 data selector/multiplexer. The binary code
on inputs A-O defines which of the 16 data inputs will be connected to the
output when STROBE is Low. Its operation is described by the following
TRUTH TABLE:

OUTPUT

INPUTS

°x

A

C

STROBE

1

0,

X

0,

0, I D.

D.

D.

0,

D.

D.

X

X

X

X

X

X

X

X

D.

X

X

0

X

X

0

X

X ~

X

X

X

X

X

X

0
y'

X

X •
X
X

.X
X
X

. X

X

X

X

X

x

x

~

X

x'

X
X

X x

L

X

H

.-1(

X
X

X

X

X

X

x

x

X

X

·1

0

1

0
0-

o
0

~

x

X

X

X _

X

X

X

X

X

X

X

x
x

X

X

X

x

x

x

X

x
x

x

x

X

X

X

x

x

x

X

• X

X

X

X

TO:
Outpu, W
Output W
Output W

337

H
H

X

xZ

H

X

X

L

X

X

H

X

X

0

X

X

X

L

X

H

X
H
L

X

H

x

x

x

X

x

x

0

x

X

X

= 50 ns (max)
= 40 ns (max)
= 30 ns (max)

>

X
X

x

High or Low

H

x

x

SPECIFICATIONS

Propagation Delay
FROM:
I.nput A, e, C, 0
STROBE
DO through 015

X
X

x
x
X

=

X
X

L
H

X

x
x

X

x

X
When used to indicate an input condition, X

X

H

x
x

X

X

,x x
.~ x

x

X

X

x
x

X

X

X

0
0

X

X

X

X

0

x

x

X

X
X

X

1

x

X

X

x

H

X

X

X

X

L

X

x
X

H

X

X

X

X

H

H

X

x

W

0"

X
X

x· x

x

X

X

X

x

0 ..

X

X

X

X

Do>

X

0

X

X

Do>

X

X

x

0"

X ! X
X

x

0"
X

X

H

x 'x

x

'X

L

X

X

0

H

X
X

--.J

M2001
DUAL 4~BIT TRI·STATE REGIST..ERS

FLIP-FLOPS
M SERIES

Length: ' Standard
Height: Single
Width:·' Single

OUTPUT
CONTROL

DI>.TA IN

,Dl>.rl>.

ENABLE

DATA IN

OUTPUTS

CLEAR

II)
(2)

(14)

(9)
E2

(10)

(13)

(SAME AS EI)

!)
(12)
III)
(is)

Volts

+5

GND

Power
mA (max.)
200

1

8:::
+3V

Pins
A2

C2,Tl

338

UI

40

The M2001 ·rs·a dual, 4-bit register module- conststing of D-type fl~p-flops
and input and output gating. Eacl:! of the module outputs contains a tristate circuit ca~able of driving low-impedance, high-capacitance loads without the use of pull-up- or interface components. The third state of the output
is a high-impedance state and is_selectable by logic levels to the input of
the module. This state effectively d[sconnects the register outputs from the
bus when no 'information transfer is required. Up to 128 of these outputs '
can becon~ected together in a wired-OR configuration.
Data is entered- into' each D-type 'flip-tl0R from an associated - DATA IN line
and is controlled by the DATA ENABLE gate. When both DATA ENABLE inputs
are LQw;- the information on the data lihes will be entered into the respective
flip-flop on the next positive transition of the clock (CK) input.

,

.

-

The Q output from each flip-flop is inverted and controlled by the tri-state
driver amplifier. Where either or both input to the output control gate is a
High logic level, the outputs of the module are disabled to the high-impedance state; however, the sequential operation of the flip-flops are not
affected.
When.the CLEAR input to the logic element is 'High, each assoCiated flip-flop.
is held inth~ res'rt conditi.on, and the module outputs .will remain' in the
I Low state.
FUNCTION TABLE
DATA 'ENABLE
DATA IN

CLOCK

CLEAR

1

2·

L
H

L to H
L to H

L
L

L
L

X
X
X
X

X

L
L
H
L
L
L

X
X
H

X
X
X

X

H

L
L to H
L to H

.. OUTPUT
L
H
L
Qo
Qo
Qo
I

=

L
Low level (steady)
H..= High level (steady)'
L to H
Low to high level transition
X = Irrelevant of any input including transition
Qo = Level of module output before steady state
inp!Jt conditions were established.

=

---~

APPLICATIONS
Provides a total of eight bits of data storage and outputs to interface directly
to system ~us. All input and output Signals are through edge board connector.
FUNCTION
Refer to Function Table for input and output signal and level requirements.
SPECIFICATIONS Input Voltage - 4.5 Vdc (min.},r 5.2 Vdc (max.)
Input Current - 7~.O rnA (max.)
High Level Output Current - 5;2 rnA (max.)
Low Level Output Current - 16 rnA (max.)

339

SHIFTI
STORAGE
REGISTERS

M2500
DUAL 64 WORD X 4 BIT FIRST-IN
FIRST-OUT SERIAL MEMORY

M SERIES

Length: Standard
Height: Single
Width: Single

INPUT
READY
SHIFT
IN
MASTER
RESET

I SHiff
OUT
OUTPUT
READY

U2
S2

...

E2

R2

(SAME AS El)

P2

SI

INPUT I VI
READY
V2
SHIFT IN 1

M:ESJ~

I

RI

I SHIFT
OUT
OUTPUT
READY

M2

Volts

Power
mA (max.)

-12

23

+5

GND

100

Pins

A2

Kl, Ul

C2, T1

.
The M2500 Module provides storage for 64 4-bit words in each of two memory elements. The words are stored and read asynchronously on a firstword-in, first-word-out basis. By series coupling the two memory elements,
the total storage capacity can be increased to 128 4-bjt words. The two
memory elements can also be paralleled, using external logic, to form storag~
for 64 a-bit words.

340

FUNCTION
The first 4-bit word is entered into the mlnory register by initiating a High
SHIFT IN pulse when the INPUT READY signal from the memory is High.
With no data word previousty stored in the first location of memory, the
INPUT READY signal will be High. As the word enters the first memory location, the INPUT READY signal becomes Low and remains Low until the SHIFT
IN pulse is brought Low. The Low transition of the SHIFT IN pulse transfers
the first 4:bit word into the second memory location, and the INPUT READY
signal again becomes High. The internal control logic then sequences the
word to the first-out or. 64th memory location which causes the OUTPUT
READY signal to become High. This indicates that the first word entered is
available to be read at the output. The second 4-bit word -can then be entered
into memory and is automatically stacked at the output. To read a word from
memory and shift the next word to the output, a High SHIFT OUT pulse is
. required and causes the previously High OUTPUT READY signal to become
Low. The data is shifted out by the trailing edge of the SHIFT OUT pulse
when the OUTPUT READY signal is Low. The next 4-bit word is then automatic~"y shifted to the 64th location causing the OUTPUT READY signal to again
become High. When all locations are empty, OUTPUT READY will remain Low.
When all the memory locations are full, the INPUT READY signal is held Low
until a word is read, resulting in a vacant location.
APPLICATIONS
The M2500 can be used as a synchronous or asynchronous serial storage .
device or as a buffer unit for data communication between devices operatingat different data rates. The M2500 can be serial connected to increase the
total number of 4-bit memory locations or connected in parallel to extend
the word lengths. Both data and control inputs and outputs are direct TTL
and DTL compatible.
.

-.

FUNCTION
The following input/output diagrams indicate the timing relationships and
logic levels required to write into'or read data from memory.
~

INPUT TIMING

SHIFT

1.SV

IN

OV

DATA IN

(Do-OJ)·

/

341

OUTPUT TIMING

OUTPUT 1.SV'---fREADY OV

tl R+ (Input Ready HIGH Time)
tiC (Input Ready LOW Time)
tOY+ (Control Overlap HIGH T~me)
tOSI (Data Input Stable Time)
tDD (Data Input Delay Time)
toR+ (Output Ready HIGH Time)

300 ns (typ.)
300

100
400
25
300
. 450
75

toc (Output Ready LOW Time)
tDl''- (Data Hold Time)

ns (typ.)
ns
ns
ns
ns
ns
ns

-

(min.)
(min.)
(min.)
(typ.)
(typ.)
(min.)

NOTES:.
tlR+ is referenced to the positive going edge of IR or SI, whichever occurs
later.
tiC is referenced to the negative going edge of IR or SI, whichever occurs
later.
toD is referenced to the positive going edge of IR or SI, whichever occurs
later.
tOY+ is referenced to the positive going edge of IR or SI, whichever occurs
later. Control signals include Input Ready, Shift In, Output Ready, and
Shift Out.
Data must be stable for tSOI or tlR+, whichever is shorter.
Input data must remain stable during timing window tSOI. Both SI and IR
must be HIGH for tOY+"";tOR+ is referenced to the positive 'going\ edge of OR or SOl whichever
occurs later.
toc is referenced to the negative going edge of OR or SO, whichever'
occurs later.
.
tDH is referenced to the' negative going edge of OR or SO, whichever
occurs later.
toV+ is referenced to the positive going edge of IR or SI, whichever
occurs later.
Both SO and OR must be HIGH for tOY+.
342

Inputs
SHIFT IN

A High on this input causes INPUT READY to go Low'
and data to the shifted into the memory. Data will begin to shift to the last empty location when this input
is brought Low again. Minimum pulse width is 100 ns.
Data must be valid within 25 ns after SHIFT IN goes
High.~ SHIFT IN must only be brought High when INPUT READY is High. Minimum Low time for SHIFT IN
is 100 n~.

DO-D3

Data inputs. Data must be valid within 25 ns after
SHIFT IN goes High and should remain valid for at
least 400 ns.

SHIFT OUT

A High on this input initiates the output shifting process. Data will remain valid until 70 ns after both
SHIFT OUT and OUTPUT READY have gone Low. Minimum pulse width is 100 ns. SHIFT OUT must remain
Low for at least 100 ns.

MASTER RESET

Resets memory control logic.

Outputs
INPUT'READY

Indicates when data' may be loaded into the memory.
Goes Low 300 ns (typ) after the leading edge of
SHI.P' IN and goes High again when the next data
word may be loaded. INPUT READY remains Low when
the memory is full.

OUTPUT READY

Indicptes when data is valid at the output of the
memory. OUTPUT READY goes··Low 300 ns (typ) after
the leading edge cif SHIFT OUT and goes High again
when the next word has been shifted to the output.
OUTPUT READY remains Low when the memory, is
empty.

Qo-Q3

Data outputs. Data is valid at the outputs whenever
OUTPUT READY is High, even if SH 1FT OUT is Low.
Data will change 75 ns after- OUTPUT READY goes
Low. Typical propagation time from input to output of
an empty memory is 10 p.S.

343

MULTI·
VIBRATORS

,I

M3020
DUAL DELAY MUlTIVIBRATORS

M SERIES

L2

..,~D~1------;1 c
L:J
270pF

~Hl

1~;~jg~o~PF~-~

r;l Jl
t..:J
r;l El

l.....,;c-==-,8~_ _---.

J

.033",F
j-.:;C;;.-6-::--::_ _ _ _ _~

C14

~.330.lJF

.. Fl

22PF

El
F2 10

Q

GJNl
0I-S_1_ _-;

C1S

1-'-'-'------....

22PF

E3

T2

10

(SAME AS El)

• R2

• USED TO SELECT OUTPUT
PUtSE WIDTH (see TABLE)

~+5V

Volts

+5V

GND

~
344

. Power
rnA (max.)

144

Pins
A2
e2, T1

The M3020 Module contains two monostable multivibrators, each of which is
activated by the output of a Schmitt Trigger circuit. A low input tranSition
on anyone of the three inputs to the Schmitt Trigger circuit produces a
positive output pulse and triggers the multivibrator. Minimum duration of a
low pulse is 50 ns. The Schmitt Trigger input provides hysteresis which pre·
vents the multivibrator from being triggered erroneously by noise signals at
the input.
When activated, the multivibrator produces a positive pulse at the output.
The width of the pulse is variable from 50 ns to 40 sec -and is selected by
the external connections to capacitors mounted on the M3020 and by the
variable Vcc available.
The delay time is adjustable from 50 ns to 7.5 ms using the internal capaci·
tors and can be extended by adding an external capacitor.
APPLICATIONS
• 'rime delays
• Variable width pulses
FUNCTIONS
Delay Range: The basic DELAY RANGE is determined by an internal 22 pF
capacitor. The delay range may pe increased by selection of additional· capacitance either by connecting various module pins (See Table) or by the addition .of external capacitance between pins L2 and F1 or between pins 52 and
Rl. Potentiometers mounted on the module can be connected for fine delay
adjustments within each range or an external resistance may be used between
pins E2 or R2 and +5 Volts. If an external resistor is used, the resistance
should be limited to 40,000 ohms.

Delay Range
50
500
5
50
1500

ns -750 ns
ns -7.5 p'S
p'S -75 p'S
p's - 750 p's
p's -7.5 ms

Capacitor
Value
(Internal)
22
270
3300
.033
.33

pF
pF
pF
p.F
p.F

Interconnections
Required
Delay E1
None
01-- L2
Hl-L2
Jl-L2
El-L2

Delay E3
None
Nl-S2
"'51- S2
Ul-S2
Pl.-S2

Adjustable Delays: Connect pins 02 to E2 for delay i and V2 to R2 for delay
2 in order to add the potentiometers. NOTE: If the potentiometer or afl\.external resistor is not used pins E2 and R2 must be connected to +5 volts
(pin A2).
PRECAUTIONS
Care should be exercised in the selection of external capacitors
low leakage as leakage will affect the time delay.

to assure

SPECIFICATIONS
Trigger Input Fall Time: Must be less than 400 ns
Recovery Time: Defined as the time all inputs must remain HIGH before any
input goes LOW to trigger the delay
1. Without external capacitance: 30 ns min.
2. With external capacitance: 300 C ns min. where C is in nanofarads
345

......
CLOCK

M4050

Crystal Controlled Clock

M SERIES

length: Extended
Height: Single
Width: Single

M4050 MODULE

Q

-

5KH1- 5MHI
CRYSTAL CONTROLLED
CLOCK

W7

Volts
+5V

W8

Power
rnA

80

GND

10

Q

'.
W6

02

W9

Pins

A2
C2

DESCRIPTION
The M4050 is a crystal controlled clock module that provides both positive·
or negative-Iiloing 80 ns pulses at a frequency range from 5 KHz to 5 MHz.
(An M4050-YA module variation is also available and provides an output pulse
width of 3.9 .us.) The module has a series of jumper leads mounted between
split lugs on the board which can be removed to select four frequency ranges.
Once the proper range has been selected, the output olock frequency is determined by a plug-in crystal. The module can be effectively used in applications requiring accurate pulses at stable frequencies.
FUNCTIONS
The D2 and E2 outputs of the M4050 are supplied from a monostable multibibrator. The pulses at 02 and E2 are positive and negative 80 ns pulses,
respectively.

Frequency Range Selection
Jumpers WI through W9, shown on Figure 1, are used to determine the frequency range of the output. The specific frequency is then determined by
choice of a plug-in crystal, either one of the three offered by DIGITAL or
one supplied by the user. Table 1 lists the jumper configuration for the four
frequency ranges.

346

J"ABLE 1
JUMPERS
Frequency
Range

IN

OUT

5 KHz - 38 KHz
38 KHz - 500 KHz
500 KHz -1 MHz
IMHz-5MHz

WI-W8
WI-W6
W3-W6
W5,W6

W9
W7 and W8
WI, W2, W7, W8
WI - W4, W7, W8

Output Selection
Jumper WI0, shown on Figure I, can be removed to disconnect the negativegoing pulse output from the multivibrator to pin E2 of the module.
"-

Ordering Information
The M4050 is available with any of the three standard crystals listed below.
Be sure to list the crystal part number desired when ordering. Standard
crystals:
1.333 MHz
2.0
MHz
5.0
MHz

Part
Part
Part

#
#
#

18-5501-02
18-5501-09
18-5501-.08

COMPONENT SIDE

.-.sW10
~ws

S--SW3
...... W1
....... W7
W9. . . . . .....sW8

CRYSTAL
Y1

Figure 1

M4050 Jumper Lead Locations

GEtERAL SPECIFICATIONS
Frequency:
Range: 5 KHz - 5 MHz
Stability: 0.01 % of specified value between O°C and +55°C.
Power Requirements: +5V at 80 mA (max.)
Temperature Range: O°C to +55°C

/

\

/

- .....

347

M5864
OPTIC ISOLATOR INPUT MODULE

ISOLATION I
LEVEL
CONVERSION
M SERIES

PART OF M.5864

r

M5864 Optic Isolator Input Module

348

!'ART Of MSI64

M5864 Optic Isolator Input Module (c.ont.)

349

The M5864 Optic Isolator Input Module is used to electrically isolate and/or
convert signal levels between peripheral devices and a TTL-compatible interface of a processor or controller system. The M5864 can effectively be
used in any application where signal conversion or voltage isolation is required.
-

-J

The module contains 20 optically-coupled circuits, each of which provides
signal isolation between the input and output of the module. The data signals
transferred through each of the module circuits are opti~lIy-coupled to provide a maximum of 1500 V isolation between the current'loop and the TTL
logic. Eighteen input circuits accept levels from current-producing devices
and convert these signals to TTL-compatible levels. The current-receiving
inputs are protected against reverse voltage conditions by a diode shunted
across the LED in each optic coupler. The conduction of the LED controls
the conduction of the associated phototransistor also in the optic coupler.
Two output circuits accept TTL-compatible levels from the interface and control the conduction of the floating transistor outputs. Each transistor output
is capable of switching 8 mA of current.
Signals are transferred to and from the module through the module pins and
backplane wiring or through cable assemblies that attach to the two 4'O-pin
connectors located near the edge of the module. The module input and output circuits can be disconnected from the backplane of a system by removing jumper leads that are installed on the module board. This allows the
module to be plugged into computer busses and other prewired backplanes for convenient mounting. Power and ground to the mO,dule will still
be maintained through the module pins and backplane wiring.
350

Each signal pin on the 40-pin cable connector (J2) has an associated ground
pin to enable proper shielding of the TTL levels_
The M5864 is a double-height, standard-length module and occupies two
slots when inserted into a standard DIGITAL connector block.

FEATURES

• Complete electrical isolation betwee-n inputs and outputs ..
• Signal transfer to and from module through module pins and backplane wiring or through cable and connectors.
• Floating transistor outputs,

reverse:voltag~

protected.

• Capable of isolating 16 data and 4 control lines.
• Device input voltages adjustable by adding resistors on board.
-.. Standard DIGITAL power and ground pin configuration.
GENERAL SPECIFICATIONS
The- input to each of the optically isolated input circuits is the opto-isolator
LED. A forward current of over 8 rnA (30 rnA max) will turn the LED on.
The output of each input circuit is a standard TTL ga~e with a fanout of 10.

The input to each of the optically isolated output circuis is the opto-isolator
LED which is pulled up on the module to +5 volts through a resistor. This
input is TTL compatible and represents 10 unit loads. The output of each
output circuit wiHdrive one TTL load.
18--Jriput Circuits
Input (Jl)
Q-2mA
8-30 rnA

TTL Output (J2)
HIGH (-400 rnA at 2.4 V)
lOW (16 rnA at .4 V)

2-Output Circuits
Input (J2) (TTL Compatible)
HIGH (100 p.A at 4-7 V)
LOW (-16 rnA at 0.4 V)
• Maximum collector·emitter voltage

Optic Isolators
Cond.ition
turn-on
turn-off

== 30

Output (Jl)
50 nA (max) at 10 V*
1.6 rnA (min) at 0.5 V
V

Hfe
15 p's (max)
15 p's (max)

Size

Double height-5.l87 in. (13.17 cm)
Single width--0.5 (1.27 cm)
Extended length--8.~--in. (21.59 cm)

Power
Operating
Temperature
Relative
Humidity

+5 V ±5% at 340 rnA {max)

10% to 95%, without condensation

351

Diode Current
16 rnA
o rnA

-

COMMUNI·
CATIONS

M5960
20 rnA Active Current loop Interface
Length: Extended
Height: Single
Width: Single R+ •

M SERIES

M5960 MODULE
K2

47
WI

R-

• J2

T+

• T2

T-

• R2

R+

• FI

47

81 10

RECEIVER

'L'2.2

47

• H2

T+

• I

T-

• M2

VI

S2 2

•

HI 10

47
W2(

R-

TRANSMITTER
47

47

:> '
RECEIV~R

~r-2.2

47
U2

TRANSMITTER

2

47
(

R+

• NI

47

WJ>
-(
R-

• PI

T+

•

T-

·

R+

• JI

47

01 10

RECEIVER

~L'_2.2

47
L1

V2

TRANSMITTER
MI

)

• E2

·

47

RECEIVER

KI 10

,[=;2.2,

I
51

47

_ (!}L2

47

+

-

47

W4~

.

2

47

TRANSMITTER

RI

2

Power
Volts

mA (max.)

Pins

+5V
-15V

320
200

A2"

GND

352

82
C2

DESCRIPTION
The M5960- is a communications interface module used to convert 20 mA
current loop information into TTL logic levels (receiver) and TTL logic levels
into 20 mA current loop information (transmitter). The module is suitable
for driving and sensing data on long current loop cables between the terminal
and mOdule at high baud rates. The M5960 consists of four differential current loop receiver circuits and four differential transmitter circuits, each
capable of converting the serial data between terminal and logic system and
allowing full duplex operation. The M5960 occupies a single vertical slot in an
H803 con nector block.
APPLICATION
Figure 1 is a typical application diagram showing four passive devices connected to fhe 20 mA current loops. Both the receiver and transmitter circuits
can supply 20 mA of current to a total line/load resistance of up to 500 ohms.

TTL DATA
(SERIAL)
TTl (IN)
TTL (OUT)
TTL (IN)
TTL(OUT)

TTL

INTERFACE

I
I

.
ACTIVE

I CONVERTERS
M5960

20mA
CURRENT
lOOPS
(SERIAL)

TRAN/REC 1

------TRANS/REC2

J

.

.

J

PASSIVE
TERMINAL

I

PASSIVE
TERMINAL

I

PASSIVE
TERMINAL

J

PASSIVE
TERMINAL

I

---~----

TTL (IN)
TTl (OUn
-

TRANS/REC 3

--------

TTLIIN)
TTl (OUTI

TRANS/REC4

J

Figure 1 . TypicalM5960 Application Diagram
RECEIVERS
Each of the four receiver Circuits consists of a differential current source
Circuit which senses the current flow in a passive terminal such as a teletypewriter keyboard or the collector of an optical isolator network. Jumpers'
WI-W4 shown on Figure 2 connect a capacitor across the 20 mA input
circuit to provide high noise immunity at standard TTY data transmission
rates of 110 bau(t When used in applications requiring rates greater than
110 baud, the appropriate jumpers can be removed.

When current flow above approximately 10 mA is sensed at the 20 mA receiver circuit (R+ and R-), a ,lOW TTL output is produced. Current flow below
approximately 10 mA results in a high TTL logic level at the output. 'Each
receiver output is capable of driving 10 TTL unit loads.
TRANSMITTERS
Each of the four transmitter circuits provides a 20 rnA current source used
to drive a teletypewriter printer or similar passive ,device. The transmitter
circuits receive TTL-compatible levels at the input to \ control the 20 mA current at the output (+ T and - T). A low TTL level produces a 20 mA current
flow at the output terminals to activate a relay or Light Emitting Diode (LED)

353

in an optical isolator network. A high TTL level at the input inhibits' the 20
rnA current from flowing at the output, and disables a relay or LED con·
nected to the current loop circuit.

GENERAL SPECIFICATIONS
Receivers:
Input Current
15 mA (and over)
""
5 rnA (and under)
Transmis$ion Rate:
TTL Drive:

, Output TTL
Low Level
High Level
9600 baud (max) ,

10 unit loads

COMPONENT SIDE
.......eWl

...... W2
t9"'-$W3
~W4

Figure 2
Transmitters:
Input TTL
Low Level
High Level
Transmission Rate:
TTL Sink:
Power Requirements:
+5 Vdc
-15 Vdc
Operating Temperature:

M5960 Jumper Lead Locations

Output Current
20 rnA (max)
o mA (approx.)
9600 baud (max)
2 unit loads

320 mA (max)
200 mA (max)
5°C to 6CtC, non-condensing

354

ISOLATIONI
LEVEL
CONVERSION

M6865
OPTIC ISOLATOR OUTPUT MODULE

"-__--;==========================~=M=SERIES
PART Of 1016865

RI

W4

• ACI

W7

W9

• An •

Wl2

- AHI

W20

+

AMl •

W31

_ 802

WU

• 8Jl

W4S

- 8M2 •

WII

• ALI •

- AV2 •

W47

W42

_ BN2

• BtU

- BL2

M6865 Optic Isolator Output Module
355

PART OF MI>81>S

M6865 Optic Isolator Output Module (cant.)

356

INTRODUCTION
The M6865 Optic Isolator Output Module is used to electrically isolate and/or
convert the signal levels between peripheral devices and a TTL-compatible
interface of a processor or controller system. The M6865 can effectively be
used in any application where conversion or isolation is required .
. The module contains 20 optically-coupled circuits, each of which provides ac
or dc signal isolation between the inputs and outputs of the module. The
data signals transferred through each of the module circuits are opticallycoupled to provide a maximum of 1500 V isolation bj:!tween the current loop
and the TTL logic. Eighteen output circuits accept TTL-compatible levels from
the interface to control the conduction of the 18 floating transistors in the
optic couplers. Each of the transistor outputs is capable of switching 1.6 mA
of current. Two input circuits receive controlling signals from current-producing devices and convert these signals to TTL-compatible levels. Each of
the two input circuits is protected against reverse voltage conditions by
diodes which are shunted across the input terminals.
Signals are transferred to or from the module through the module pins and
backplane wiring or through cable assembies that attach to two 40-pin connectors conveniently mounted near the edge of the module board. This allows
the module to be inserted into computer busses and other prewired backplanes for convenient mounting. The module input and output circuits can
be easily disconnected from the backplane of a system' unit by removing the
jumper leads that are installed on the module board.
Each signal pin on the 40-pin cable connector (Jl) has an associated ground
pin to enable proper shielding of the TTL levels.

357

The M6865 is a double· height, extended·length module and occupies two
slots when inserted into a standard DIGITAL connector block.
FEATURES
• Complete electrical isolation between inputs and outputs.

• Signal transfer to and from module through module pins and back·
plane wiring or through cable and connectors.
• Floating transistor outputs, reverse voltage protected.
• Capable of isolating 16 data and 4 control lines.
• Device input voltages adjustable by adding resistors on board._
• Standard DIGITAL power and ground pin configuration.
GENERAL SPECIFICATIONS

The input of each of the two optically isolated input circuits is to a LED. A
forward current of 8 rnA (30 rnA max) will activ.ate the LED and cause the
transistor to conduct. The· output of each input circuit is a TTL level with a
fanout capability of 10 unit loads.
The input of each of ' the 18 optically isolated out~t circuits is to a LED
which is pulled up to +5 V through a resistor. These inputs are TTL com·
patable and represent 10 unit loads. Each output is capable of driving one
unit load.
I

'

\

2-lnput Circuits
Input (Jl)

TTL Output
HIGH (-400 p.Aat 2.4 V)
LOW (16 rnA at .4 V)

~2mA
~30 rnA

18-0utput Circuits
TTL Input (J2)
HIGH (100 p.A at 4·7 V)
LOW (·16. rnA at 0.4 V)

Output (Jl)
50 nA (max) at 10 V*
1.6 rnA (~in) at 0.5 V

*Maximum colieCtor·emitter voltage=30 V

Optic Isolators
Condition
turn·on
turn·off

Time
15 p's (max)
15 p's (max)

Diode Current
16mA
OmA

Size

Double height-5.187 in. (13.17 cm)
Single width-o.5 in. (1.27 cm)
Extended length--8.5 in. (21.59 cm)

Power

+5 V ±5% at 340 rnA (max).

Operating
Temperature
Relative
Humidity

10% tc? 95%, without condensation

358

M7390
ASYNCHRONOUS TRANSCEIVER

COMMUNICATIONS
M SERIES

Length: Extended
Height: Double
Width: Single

OUTH
CUTL
ECHO

L (NOTE 2)

INH

~
~
3!:

t

*

R04 L

..J

le

Transmitter Control Signals:
TBMT
ECO

Transmitter Buffer Empty
End of Character

Error .control and other Signals:
NP
POE
SWE
-CS
NB1, NB2
SB
XR
•
RESET
RCLK
TCLK

No Parity
Parity Odd or Even
Status Word Enable
Control Strobe
Number of Bits in data word
Number of Stop Bits (1 or 2)
External Reset (clears all registers)
Negative pulse used for clearing module during
power-up.
Receiver Clock Input
Transmitter"Clock Input

PRECAUTIONS

1. El'A and current loop connections are available on an S-pin 1VlATE-N-LO~
connector located in the handle position on the B half of the board.
2.

Provision is made to power this module from either -15 or -12 volts
dc. Do not use both simultaneously.

3.

Current loop input and d'utput circuits must not have· more than 35 volts
peak applied or greater than 100 mA current flow.

4. The M7390 contains an MaS LSI chip. Care must be taken in proper
handling and grounding of the module ~o prevent damage to the MaS
chip.
5. The +10 volt dc supply is ·required only if the EIA level converters are
used, or if the module is going to be used as a current source.

6.

If the M7390 is used as a current source, 20 mA additional current must
be supplied by-the -15 volt and the +10 volt power supplies.

361

SPECIFICATIONS
Data Format: Asynchronous, serial by bit, least significant bit first.
Input/Output Level (~erial):

1. EIA RS·232C: Binary 1
2. Current Loop:

= -3 to -25 volts dc

= +3 to +25 volts dc
Mark (Binary 1) = 20 to 100 rnA current flow

Binary 0

Space (Binary 0)
3. TTL: Binary 1
Binary 0

=

=

<3 rnA current flow

HIGH

= LOW

Data Rates: (TTY Mode) 110, 150/300 Baud
(EIA Mode) 110, 150, 300, 600, 1200, 2400, and 4800 Baud.
Character Format: One start, 5, 6, 7, 8 data, parity (if requested), one or
two stop bits.
Clock Frequencies (kHz): 1.76,2.4,4.8,9.6, 19.2,38.4, 76 r8
Input/Output Levels (Parallel): All TTL compatible.

,

/

..
362

DRY CONTACT FILTERS

PULSE
SHAPING

K580, K581
220

Length: Single
Height:· Single
Width: Single

SOWER
LUGS

SOLDER
LUGS

·Should be followed by a
Schmitt trigger circuit for
TTL logic.

K581

K5SC?

.... IIA A A_~~NTACT
---.JWIJV VVVLOUNCE

OUTPUT

~

m
1
J'50UF
Typical K580 circuit

363

These filters convert signals- from dry or WIPing contacts to logic levels.
Primarily they are used with gold contacts such as encapsulated reed limit
switches, thumbwheel switches, and the like. Those push-buttons or· slide
switches that provide good wiping action will also operate reliably with these
filters.
Schmitt Triggers should be used on the outputs of both the K580 and K581
when they are used for one shot or timer inputs.
Access to K580 and K581 inputs is by solder lugs only. Strain relief holes
are provided in the board (near handle) for a 9-wire cable. The avoidance of
contact connectors on the logic wiring panel combined with heavy filtering
guarantees noise isolation and protects modules by preventing accidental
short circuits. Below is a summary of other characteristics.

Output for
Time Delay
Contact Closed on Closure

Contact
Current

Contact
Voltage

KS80

22ma

See Table

high

10msec

30msec

KS81

22ma

SV

low

20msec

20msec

Time Delay
on Opening

(Time delay figures above.JUe nominal, and assume connection to the input
of a standard gate such as K113 or K123.)

The contact curr,ent for the K581 comes from the logic supply, making it very
important to assure freedom from accidental high voltages on K581 inputs
which could damage many logic modules by getting through to the system
power supply. This hazard is not present with the K580, which uses an external source of +10 volts or ~~ The table below shows how, external
dropping resistors may be added to provide higher voltage operation.

TABLE OF K580 VOLTAGE DROPPING
CONTACT
SUPPLY
VOLTAGE
Dropping
Resistance
Dissipation

10

0

-

12

82n

15

2200

24

28

~ESISTANCES

48

90

100

120

6200 8200 1.8KO 3.6Kfl 3.9Kfl 4.7KO

0.05W O.l1W 0.3W O.4W 0.8SW 1.8W ~.OW

,-

2.SW

When using dropping resistors and higher voltage supplies, total tolerance of
resistors and supply should be ± lO%- to insure high levels between +4 V
and +6 V at the logic. Also observe that a handful of dropping resistors in
90 V or 120 V systems may dissipate more power than the entire logic system, and must be located so as not to cause excessive temperature rise in
the logic system.

364

Note that these 'circuits may not be paralleled to obtain the wired QR or
wired AND function, and that fanout is limited to 2 milliampers in order to
maintain the low (zero) output voltage within normal specifications. Fanout
to ordinary logic gates and diode expanders may be raised to 4 milliampers
if some noise and. contact bounce rejection can be traded off; but hysteresis
inputs may not switch properly. if" the logic zero is allowed to rise much
above +0.5 V.
.
Looking at the component side of both the K580 and K851, the solder lug
connections are numbered 1 to 9 from pin end to handle end.

K580

K581

365

ISOLATED AC SWITCHES
K616

LOGIC
AMPLIFIERS
\

Lengtt1: Single
Height: Double
Width: Triple

SUPPLY

2
LOAD

//

3
SUPPLY

4
LOAD

//

5
SUPPLY

6
LOAD

//

--t..

7
SUPPLY

8

//

9
SUPPLY'
RETURN

10

(S) NOT

USED

Power
Volts

+5

rnA (max.)
100

GND

Pins

AAl
AA2
Ael
AC2

366
.-~

The K616 isolated ac switch module contains four isolated 120 Vac .TRIAC
output circuits. Each output is fused and bas a light·emitting diode to indicate when the output is ON. The fuses can be changed frOm the,-t'erminal
strip side of the module without removing field wiring or removing the module
from the system. The K724 Interface Shell can be used to provide suitable
mounting for the K616.
'
The K616 contains a 10-terminal nylon terminal strip with 3/8 spacing 'between terminals. The terminal strip meets NEMA and JIC specifications regarding barrier height and voltage breakdown. It has captive screws with wire
clamps to accept 2-14 AWG wires and is color coded red for ac. Each terminal is marked according to its function: Supply (LINE), Switched Output
(~) AC Return (NEUT), and Chassis Ground (GND).
SPECIFICATIONS
Output Turn On Time:

MIN:
MAX:

1 p'S
50 P.s

Output Turn Off Time:

11hycle of ac line maximum. (Turns off when output current goes through zero after removal of
input)
-

Output Voltage:

12-140 V RMS AC, 50-400 Hz

Output Current:

0.030-5.0 ARMS AC

Output VA:

500 VA maximum per output, not to exceed 1000
VA for all -four circuits.

Output Surge Current:

20 A for 1 cycle of AC line

Output Off State
Leakage Current:

0.005 A maximum

Output Off State d.v / dt:

Output will withstand a voltage change of at least
100 V/ p's without turning on.

Output Indicator Light:

The LED indicator will indicate the presence of
80-140 Vac at the output terminal. It will be off
if the output is off, or the fuse is- open.

Fuse Protection:

5 A continuous Littlefuse type 275005

Temperature Range:

O°C to 70°C

Power Requirement:

+5 Vdc ± 10% @ 100 mA MAX 70 mA TYP

367

DC' DRIVER

LOGIC
AMPLIFIERS

K652

Length: Single
Height: Double
Width: Triple

OUTPUT

TERMINALS

L...----~1'f

POSITIVE

SIDE OF

LOAD SUPPLY
/

Volts
5V

GND

Power
mA (max.)

*

Pins
AA2
BA2
AC2
BC2

'" 10 mA with all circt,Jits off
160 mA additional per circuiton

K652 DC DRIVER
The K652 DC driver has four circuits each of which can deHver up to 2.5
amperes at u'p to 55 volts. Like the K578, K614, K656 and' other modules,
this unit has built-in clamp-type terminals for wires up to size 14. It can b4!
mounted in the K724 interface shell, but does not have neon indicators
across the output terminals as other .shell mounted modules.
The positive s..ide of the load supply should be connected to protect output
transistors from damage due to turn-off transients. See the application section for further DC driver information.
Terminals 2, 4, 6 and 8 must be connected directly to the negative terminal
of the load power supply or damage to the llJodule will result from high
currents.

368

I

DC DRIVERS f

LOGIC
AMPLIFIERS

K657

Length: Single
Height: Double
Width: Triple

OUTPUT
TERMINALS

5

7

9

POSITIVE
SIDE OF

LOAD SUPPLY
~

Volts

+5V

Power
mA (max.)

*

GND

Pins
AA2
AC2

* 88

mA with all outputs off
130 mA with all outputs on.

The K657 DC Driver module contains four 250 Vdc drivers. 'Each circuit. of
this driver can switch to ground up to 1.0A at up to 250V
The outputs
will switch to ground whenever both AND gate inputs are high (logic
, 1).

369

\

DC DRIVER

-LOGIC
AMPLIFIERS

K658

DC
DRIVER

~-+--------~~~~

3

OUTPUT
TERMINALS

~-+--------~~~~

5

~-+--------~~~~

7

~8
L...----:-------'{"IIIW 9
Volts

+5

GND

.

Power
mA (max.)

Pins
AA2
AC2

POSITIVE
SIDE OF
LOAD SUPPLY

·IOmA with all outputs off
350mA additional per circuit on.

K658 4 AMP DRIVER .
Each circuit of this versatile driver can deliver up to 4 amperes at up to 125
volts. This module has integral clamp-type terminals and neon indicator
lamps. (Lamps are effective only at 90 volts ~nd above.) This driver module
is designed to be used with K724 interface shells. Positive side of load supply must be connected to protect output transistors from damage during
turnoff transient.
Terminals 2, 4. 6 and 8 must be connected directly to the negative terminal
of the load power supply or damage to the module will result from high
currents.

,

370

I'

5-DIGIT DISPLAY

LOGIC
AMPLIFIERS

K675

I

. . - - - - - +5VDC
r - - - - GND
}SPARE
MINUS SIGN OIGIT 1

25 PIN CABLE CONNECTOR

BCD TO 7 SEGMENT
DECODER DRIVERS

The K675 is a 5-digit display module designed to be panel mounted. Five
digits of 7-segment LED readouts are housed in a plastic bezel with a lucite
window which can be mounted through a panel cutout. The display is connected to the logic backplane wiring by a 10 foot, 25-conductor cable
(BC14F) and a double height cable connector module, K783. Five digits of
BCD-coded data, presented to the K783, will be displayed by the K675."
A blanking feature to suppress zeroes to the left of the last non-zero digit
is controlled by a wire jumper on the display module. The display is pre-·
enabled for blanking but can be disabled by removing a wire jumper. If disabled, the K675 will display all BCD digits, including zeroes.
A decimal point is located to the left of each digit and can be controlled by
jumpers W2 through W6. Removing a jumper will extinguish the corresponding decimal point.
Digit 1 can be used for a minus sign when displaying 4-digit negative nurn.
bers. When the minu~ sign is used, digit 1 is not available for displaying
otl)er numbers. The minus sign is illumiAated by groundng pin 20 directly,
or with a NAND gate or inverter.

371

~_:_:O_;_;_~_:_:+s,_T_H_RU____________,

·

1

Till
.980

.900

~L-~

-J

~

____~____~$
-1.460--

1--1.545 - - - - - - . e j
t - - - - - " ' - - - 2.920

'

.'

1-------- 3.090 --------.1
Panel Cutout Dimensions
DIS PLAY SEGMENTS

o

f,7/

e,-,c

b

7'
SOI2·1730n731

DECIMAL

BCD INPUTS

8421 \

VALUE,

o0 0

0

I 1 1 1 1 1 0

0 1

0110000

o0

1 0

1. 1 0 1 1 0 1

o0

1 1

1 1 1 1 0 0 1

o1

0 0

o1

o

1 0 1

o

1 1

1

1 0 0 1 1

1 0 1 1 0 1 1

o0

0

1 1 1 1 1

1 1

1 1 1 0 0 0 0

1 0 0 0

1111111

1 0 '0 11

FONT

Ibedel,

o0

o1
9

SEGMENT OUTPUTS

1 1 1 0 0 1 1

:.:
,

u

,

:J

b

-,,

'_:

~'--4-~r+4---~---+4-+4~+_--~--~~

10
- ... ---

"
12

i

1 0 1 0

0 0 0 1 1 Ole

4---+--+-I----t----+-~._++_+__+--_+------__I

o0

1 0 1 1

1 1 0 0 1

~----~~~+---~--~~~~+-~~----~

-

13

ill

I

14

15

~

00

"

o0

1 1 1 0 0
"

1 1 0 1

1 0 0 1 0 1 1

1 1 1 0

o0

1 1 1 1

0000000

0 1 1 1 1

NOTE:

372

'-

,-

I-

1 = Segment ON
0= Segment OFF

W960
MSI MODULE BOARD

Iffr"ff~~
=tt +-.
I~
==tt
14

AI
81
Cl

ICt~:

r:r-

MISCELLA·
NEOUS

Kl

L1

MI
NI

.

1111(- ~

P.t

RI-'
51

:'~~
1~

01

1

17

E1
Fl

.

1

HI
Jl

U1

~

-~

VI

7
6
5
4

IC2

120

02
E2

F2
H2
J2
K2
L2

3

.

-

.:

1
9'--- 8
7

---r5
1

+5V,A2~C2

12
13
14
15

GNO,C2~
NO TES:
1. Capacitors Cl Gnd C2 10 be supplied
and InltaUed, Gnd .aluel to be determIned by Uler.

16

IC3

:I
.4

3

-

2
1

M2
NZ

P2
R2
52
T2
U2

V2

2. Inlegrated circulII ICI and/or IC2 or IC3 to
b. IUpplied and Inltolled by ...,.

...........
The W960 MSI Module Board is a single-height, standard length module
board that can accommodate either two 14- or 16-pin dual-in:line package
.(DIP) integrated circuits (ICs) or one 24-pin DIP IC, either with or without
sockets. All Ie pin plated·through hole locations are identified with their
associated board contact finger and are all brought out to the board contact fingers via printed circuit etching, as shown on the schematic diagram.

373

W964

MISCELLA·
NEOUS

UNIVERSAL TERMINATOR BOARD
PADS TO
CONTACT
FINGERS

COMMON
TIE POINTS

+5V

GND Rl R2 R6 R5 R3 R4

A2
+5V
Rl
Bl
R2
C2,n
GNO
R3
01

R5

Et

R6
~

TO OTHER CIRCUITS
ASSOCIATED WITH
THE OTHER (25) I/O
SIGNAL CONTACT
FINGERS

/
JUMPER

(+5V TO
COMMON
TIE POINTS'

VUTSRPNMLKJHFEDCBA
NOTES:
1. All PC etch not shown; of that shown, side I etch
shown with solid lines and side 2 etch shown with
dashed lines.
2. Resistance values to be determined by user.
3. Resistors to be supplied by.user.
4. Pull-up/terminotlon network schematic diagram
shows three typical networks (to contact fingers Bl,OI, and Et>

W964 Component Layout Diagram
and Pull-Up Termination Schematic Diagram
\

374

The W964 Universal Terminator Board is asing/e-height, standard length
module. It is an etched and drilled module that can be used for mounting
user-selected and user-supplied discrete components to provide a variety of
termination or voltage source circuits for up to 28 signal pins. Each signal
pin can have two components connected to ground and one component connected to +5 volts. Any discrete component can be mounted on the W964
if the physical size is approximately the size of a I/4-W resistor or disk
capacitor. Three typical pull-up/termination network circuits are illustrated
on the component layout and schematic diagram.
The 28 contact fingers (signal pins) that can be used for I/O signals are BI,
01, fI, Fl, HI, JI, KI, LI, MI, NI, PI, RI., SI, 02, E2, F2, H2, J2, K2, L2,
M2, N2, P2, R2, S2, T2, U2, and V2. The pads associated with the cont~
fingers are identified on the boards to facilitate mounting the discrete components. Contact fingers A2 and 82* are dedicated to voltage. Contact fingers
C2 and Tl are dedicated to ground.

'" In many systems, contact finger 82 is bused to -15 V.

375

G772

MISCELLA·
NEOUS

POWER· CONNECTOR

TheG772 is a single-width, single-height, short-length board used to connect
power to a backplane assembly such as a BBll or 0011.
G772 Typical Connector Assignments
G772
r---

Al
A2
81

-ISV
+ISV

82
CI
C2
01
02
EI
E2
FI
F2
HI
H2
JI
J2
KI

·WI-OC LOW
W2- AC LOW

K2
LI
L2
MI
M2
.NI
N2
PI
P2
_RI
R2
51
_52

-25V

l

LTCL

T

W2
WI

:T1

~-

AC LOL
DC LOL

T2

/

Ul
U2

VI
V2

--

+8V
_L-

376

MULTI-

A123
FOUR-INPUT MULTIPLEXERLength: Standard
Height: Single
Width: Single

A R

A S,

A T

A U

0'ANALOG SIGN,IILS
(00 NOT CONNECT 10
LOGIC LEVELS)

Volts

Power
rnA (max.)

+10
+5

18
45

-20

50

GND

377

Pins

02
A2
'C2, Tl
E2

PLEXERS
A SERIES

The A123 Multiplexer provides 4 gated analog switches that are controlled
by logic levels of OV and' +3V. The modul~ is equivalent to a single-pole,
4-position switch, since one output terminal of each MOS FET switch is tied
together. If all three digital inputs of a circuit are at +3V (or not connected)
the two output terminals are connected together. If any digital input is at OV,
the switch terminals are disconnected. Two switches should not be on at
the same time., The analog switch can handle signals between +lOVand
-10v, with currents up to 1 rnA.
The positive power supply must be between +5V and' +15V, and at least
equal to or greater than the most positive excursion of the analog signal. ,
The negative power supply must be between -5 and ,-20v, and at least 10
Volts more negative than the most negative excvrsion of the analog signal.
The voltage difference between the two supplies must not be more than 30V.

SPECIFICATIONS
Digital Inputs
Logic ONE:
Logic ZERO:
Input loading:

+2.4v to +5.0V
O.Ov to +0.8V
0.5 mAo at OVolts

Analog Signal
Voltage range:
Current (max.):

+lOvto -lOv
1 mA

Output Switch
On resistance, max.:
On offset:
Off leakage, 'capacitance:'
Turn on delay, max.:
Turn off delay, max.:

1000 ohms
o Volts
lO,nA,lO pF
0.2. J.tsec
0.5 ,",sec

378
/

A126
8 CHANNEL HIGH IMPEDANCE
MULTIPLEXER

MULTIPLEXERS
A SERIES

Length: Standard
Height: Double
Width: Single

CH 0 EN
BT2
BF1

BR2
PRIORITY
DECODER

BN2

BF2. -

BL2

AV1

9

AO-

9 Al
9

BJ2
AU2
AT2
CH 7 EN

CH 0 IN

A BU2

CH 1 IN

A

CH 2 IN

A BP2

52

CH 3 IN
CH 4 IN
CH 5 IN
CH b IN
CH 7 IN

,/

Volts

Power
ro~ (max.)

*GND
·GND

12
LOGIC
ANALOG

+5V±5%
+15V±5%
-15V±5%

17

·Analog GND must be connected to LOGIC GND

379

Pins
AA2

AD1, AD2
AE1, AE2
AC2, ATl

AFl, AF2

9 MUX
EN

The A126 is an eight-channel, high-impedance multiplexer module with each
channel controlled by an associated enable input_ The conduction or nonconduction of each channel is controlled by FETs and the channel outputs
are connected together to a common terminal. Each channel is capable of
switching bipolar (± 12 V) analog signals and is protected against random
switching in the event of overvoltage and power down or loss of power conditions_

FUNCTIONS
The enable inputs, associated with each channel, are priority encoded to
ensure that only one channel is connected to the output at a time_ Therefore,
more than one Channel enable input can be asserted at one time_ Channel
o is the highest priority and channel 7, the lowest priority. The enable signals
required are TTL or DTL compatible levels. Three TTL outputs are provided for
identifying the selected channel, and one TTL multiplexer enable output indicates that one of the eight channels has been selected. The selected channel
number is specified by an octal code on lines AO-A2.

APp,LlCATIONS
The A126 can be used to multiplex up to eight signals from the analog inputs into buffer amplifiers or circuits with a minimum input impedance of 10
megohms.

SPECIFICATIONS
Analog Inputs:
CHO (IN) - CH7 (IN)
Voltage Range
Impedance (ON)
Analog switch turn-on
Analog switch turn-off
Analog switch current
JumperW1

8 single-ended channel inputs
±15 V (max.)
1040 ohms ± 10%
1.0 p'sec (max.)
0.5 p'sec (max.)
2_0 mA (max.)
(Not for customer use)

TTL Input Signals'
CHO (EN) - CH7 (EN)
Input Voltage

8 enable inputs associated with each channel
Low (enable) - 0.8 V (max.)
(disable) - 2.0 V (max.)

Hig~

TTL Output Signals
AO-A2

A 3 bit code identifying the channel that is
currently enabled.

MUX EN

Asserted low whenever one or more channels
is enabled .

.380

TRUTH TABLE
. ,"-

TTL ENABLE INPUTS

I

~
....

/

CHO

CHI

CH2

CH3

CH4

CH5

CH6

CH7

MUX
EN

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

OUTPUTS
Analog
Channel .

A2

Al

AO

H

Ii

H

H

NONE

L

L

H

H

H

7

L

X

L

H

H.

L

6

X

H·\

H

H

H

L

X

L

H

-L

H

5

H

Hi

H

H

L

X

X

'X

L

H

L

L

4

H

H

H

L

X

X

X

X

L

L

H

H

3

H

H/

L

X

X

X

X

X

L

L

H

L

2

L

L

L

H

1

L

L

L

L

0

H

-

.

H

L

X

X

X

X

X

X

L

X

X

X

X

X

X

X

H ::: High Level.

L::: Low Level

X

= Either High or Low

't.

I

AMPLIFIERS

A207

OPERATIONAL AMPLIFIER

A SERIES

Length: Standard
Height: Single
,Width: Single
tin

~
K

<> -'.'1'-::7
R ","

cs. :"\'"

AUX.

T

INPUTS

~~~~,'
I

-0- .',',',. ~ -...

-

:~ .',',',

I '
I
I

<>-----\,\,',.----r-U

:

o-~----",,\,.- ---.!.-I
H

GUARD

\

:
I

r--,

,

l __",,\,.~ _"t",. ...
I

:

GAIN

0----___+

BAL 1K

-INPUTS
(INVERTING) °NO-fE:O::2=::O-....!--ooof

"

V

''''-'~'
+INPUT P
(NON-INV.~ 0 - - - - - - 1

.

">-+--0 OUTPUT

E
-15V

F
ANALOG GND

Volts

+15

GNO

-15

Power
mA (max.)
6
ANALOG

10

Pins

02
F2
E2

NOTE 1. Mounting holes are provided on the module so that input and feedback
components can .be added. Components shown with dashed lines are not
included with the module.
NOTE 2. This jumper comes with the module. It may be removed to suit circuit requirements.
NOTE 3. Pins L& M can be connected together to improve settling time, but parameters such as drift and open loop gain are degraded.

The A207 is an economical Operational Amplifier featuring fast settling time
(5 ....s to within 10 mv), making it especially suited for use with Analog-toDigital Converters. The A207 can be used for buffering, scale-changing, offsetting, and other data-conditioning functions required with AID Converters.
All other normal operational amplifier· configurations can be achieved with
the A207.
382

The A207 is supplied with a zero balance potentiometer. Provisions are made
on the board for the mounting of input and feedback components, including
a gain trim potentiometer. The A207 is pin-compatible with the A200 Operational Amptlfier.

SPECIFICATIONS-At 25°C, unless noted otherwise.
Pins L & M Differences with Pins
Connected L & M Not Connected
Settling-Time·
Within 10 mV, 10V step input, typ:
Within 10 mY, 10V step input, max:
Within 1 mV, 10V step input, max:

3 J.Lsec
5 ",sec
7 I-tsec

F~uency

Response
Dc open loop gain, 670 ohm load .. min:
Unity gain, small signal, min:
Full output voltage, min:
Slewing rate, min:
Overload recovery, max:

\

100,000

15,000
3 MHz
50 kHz

3.5v/",sec
8 ",sec

output
Voltage, max:
Current, max:

±10V
±15mA

Input Voltage
Input-voltage range, max:
Differential voltage, max:
Common mode rejection, min:

±10V
±lOV
10,000

Input Impedance
Between inputs, min:
Common mode, min:

100 k ohms
5 M ohms

Input Offset
Avg. voltage drift vs. temp, max:
Initial current offset, max:
Avg. current drift vs. temp, max:
Temperature Range

"-

, 60 ",V/oC
0.5 ,,,,A
5 nArC
O°C to +60°C

*Gain of 1. inverting or non-inverting configuration.

383

6 J.Lsec
8 J.LSec
10 I-tsec

30 ",V/oC

DIGITAL TO
ANALOG

A619

IO-BIT Df A CONVERTER
SINGLE BUFFERED

A SERIES

Length: Standard
Height: Double
Width: Double

NOTE:

LOGIC AND ANALOG

. GROUNDS MUST BE
TIED TOGETHER AT
SOME POINT IN THE
SYSTEM.

BINARY WEIGHTED NETWORK

----,

0 BP •
EXT

+V REF

Volts

Power
.
mA.(max.)

+15
+5

25**
135

-10.06·

60

GND
• GND
-15
-15

LOGIC
ANALOG

35--

50

r-INiiI +V REF
I ~ --~--..J\NIr---...,

I
I
IL. _ _ _ -..:... _ _ _ _ ...JI

Pins
BV2
AA2
AC2
BT2
BR2
BU2
AB2

• ref .
•• plus output loading

The A6l9 Digital to Analog Conv~rter (DAC) is complete with a 10-bit buffer
register, level converter, a precision divider network, and a current summing
amplifier capable of driving external loads up to 10 rnA. The reference voltage
is externally supplied for greater efficiency and optimum scale factor matching in multi-channel applications. The module is double width (1 ") in the B
connector half.
The A619 DAC output voltage is bi-polar. Binary numbers are represented
as shown (right justified) in Table 1:

384

TABLE 1
Analog Output (Standard)
Binary Input

A619

-5V -2.5V

0000 8
0400 8
10008
14008

OVo-lts

+2.5V·
+5V

17778

A619 SPECIFICATIONS
OUTPUT:
Voltage:
Current:
Impedance:
Settling Time:
(Full scale step-, resistive load)
(Full scale step{, 1000 pf)
Resolution:
'
Linearity:
Zero Offset:
Temperature Coefficient:
Temperature Range:

r

±5 volts
10 mAo (max)
<0.1 ohm
<5.0,",s
<10.0/Ls
1 part in 1024
±0.05% of full scale
±5 mY. (max)
<0.2 mV/oC
o to 50°C

INPUT
Level: 1 TTL Unit Load
Pulse:
(positive)
Input loading: 20 TTL Unit load
Rise and Fall Time:
Width:
Rate:
Timing:

20 to 100 nsec
>50 ns
106 Hz max.

Data lines must be seltled 40 ns before the /'LOAD DAC" pulse (transition) occurs.

385

REFERENCE
SOURCES

A704

REFERENCE SUPPLY

A SERIES

Length: Standard
Height: Double
Width: Single

/

REGULATOR

.
-15V

ABZ

-SENSE

-~
OUTPUT

UNREG.
INPUT
/

+SENSE

GND

V.olts

Power
mA (max.)

GND

ANALOG

250

TI
~

AEZ,L
...
ATZ ....

T
I

I
I

I
-15·

_ AV2

Aczl

Pins
AB2
AC2

• plus or n"linus 2 volts

. The A704 Reference Supply converts an ordinary -15 volt logic supply
voltage into a precisely adjustable regulated -10 volt reference source for
AIO and 01 A converters of up. to 13 binary bits.
FUNCTIONS
Remote Sensing: The input to the regulating circuits of the A704 is connected at sense terminals AT (+) and AV (-). Connection from these points
to the load voltage at the most critical location provides maximum regulation
at a selected point in a distributed or remote load.'
-"

When the sense terminals are connected to the load at a relatively distant
location, a capacitor of approximately 100 .uF should be connected across the
load at the sensing point.
Preloading: The supply may be preloaded to ground or -15 volts to change
the amount of current available in either direction. For driving DEC Digital/
Analog Converter modules, -125 mA maximum can be obtained by connecting a 270-ohm plus or minus 5%, one-watt resistor from the reference output (pin AE2) to ground (pin AC2).

,

386

SPECIFICATIONS
Input.!ower

-15V

:""-,

Use:

See text for sensing and preloading

Output:

-10V,

Current:

-90 to +40 rnA

Regulation:

0.1 mV. no load to full load

Temperature
Coefficient:

1 mV/8 hrs
1 mV115 to 35 degrees C
4 mV/0 to 50 degrees C

Pea k-to-Pea k
Ripple:

0.1 mV

Adjustment
Resolution:

0.01 mV

Output
Impedance:

0.0025 ohms

I
387 '

ANALOG TO
DIGITAL
,'-

A866

HIGH-SPEED 12-BIT
BIPOLAR AID CONVERTER

A SERIES

length: Standard
Height: Double

Width:

Single

BT

ANALOG INPUT
MSB

Bl

82
83

ANALOG GND

B4

.85
86

DATA OUT

B7

B8

89
810
B11

+5
LSB

B12

BUSY
EOC PULSE

)

DONE
CLOCK

Power
Volts

mA

Pjns

300
75
40

AAI, AA2, BAI, BA2
ADI, AD2
AEI, AE2
ACI, AC2, ATl, BCI, BC2, BTl

(nominal)

+5V±10%
+15V±3%
-15V±3%
LOGIC GND

The A866 is a 12-bit general purpose analog-to-digital converter module
which uses the successive approximation technique. The A866 is. designed
to accept unipolar or bipolar single-ended analog voltage as input and tonvert it to a 12-bit TTL-compatible, coded digital output. The coded digital'
output is parallel data and is available for application to a computer, terminal, display, or other logic device.

388

The selection of unipolar or bipolar and voltage range of the analog input
is determined by jumper leads mounted on the module circuit board. The
module has factory-installed jumpers that permit its use with bipelar, 10-volt
full-scale extended-range inputs. By changing the jumper configuration, the
user can select bipolar or unipolar, 5-volt or 10-volt full scale extended or
nonextended input ranges.
.
The extended range is particularly useful when the output data is used in
computations because the LSB is easily expressed as an integer submultiple
of the full scale; Le., full scale/2000 ,o rather than full scal~/2048,o for a
bipolar configured module and full scale/4000 , o rather than full scale/4096,o
for a unipolar configured model. Therefore, less rounding-off error occurs
during the computations. In addition, extended range provides some overscale input capability; Le., +0.2350 Volt and -0.2400 Volt (+10.2350 Volts
and -10.2400 Volts full overscale inputs) for a bipolar configured module
and +0.2375 Volt (+10.2375 Volts full overscale inputs) for a unipolar configured module. The coded output is 12-bit binary and two's complement
using the MSB output and the MSB output respectively.
The A866 can be used wherever fast, accurate analog-to-digital conversions
are required.
Th~ high input impedance (100 megohms) at the analog inputs minimizes
the signal source loading, and the fast conversion time permits an encoding
rate at the output of 16,000 conversions per second.

The digital output data, the output control and status signals, and the input
control signals are all TTL-compatible.
.

APPLICATIONS

The A866 Analog-to-Digital Module is suitable for use in scientific and industrial research applications. It provides fast, accurate analog~to-digital conversion from transducers, bridges, or similar instrumentation.
The A866 Module has factory-installed jumpers that permit its use· with
bipolar, 10-volt full scale extended range inputs where a change of 5.0
millivolts at the input corresponds to a change of 1 LSB at the ou'l1>ut. The
A866 Module may be reconfigured with jumpers by the user so that it will
accept analog inputs of any of the following:

bipolar;t 10-Volt full scale extended range
bipolar ± 10-Volt full scale nonextended range
bipolar ± 5-Volt full scale extended range
bipolar ± 5-Volt full scale nonextended range
unipolar + 10-Volt full scale extended range
unipolar
10-Volt full scale nonextended range
unipolar
5.volt full scale extended range
unipolar
5-Volt full scale nonextended range

+
+
+

389

Table I
Bipolar ± 10 Volt Full Scale, Extended Range
Analog Input Output Code Conversion Chart
Analog
Voltage
Input
+10.2350 V
+10.2300 V
+10.0000 V
+ 7.5000 V
+ 5.0000 V
+ 2.5000V
+ 0.0050 V
0.0000 V
- 0.0050 V
- 2.5000 V
- 5.0000V
- 7.5000V
-10.0000 V
-lQ.2350 V
-10.2400 V

Two's Complement
Output Code'"
Base 10

Base 8

Scale

2046
2000
1500
1000
500
1
0
1
- 500
-1000
-1500
-2000
-2047
-2048

3777
3776
3720
2734
1750
0764
0001
0000
7777
7014
6030
5044
·4060
4001
4000

+Full Overscale
+Full Overscale - 1 LSB
+Full Scale
+%, F.S.
+lh F.S.
+% F.S.
+1 LSB
Zero
-I LSB
-l,4F.S.
-lh F.S.
'_3,4 F.S.
-Full Scale
-Full Overscate - 1 lSB
-Full Overscale

2047

~

Note: When an A866 module is jumpered to accept ±5 Volt full scale inputs, the inputs are exactly lh of the input value shown in the above
table.
• USing MSB output.

390

.. Table II
Bipolar ± 10 Volt Full Scale, Non-extended Range
Analog Input to Output Code Conversion Chart
Two's Complement
Output Code"" ""

Analog
Voltage
Input
,

+10.0000 V
+ 9.9951*V
+ 7.5000 V
+ 5.0000 V
+ 2.5000 V
0.0048*V
0.0000 V
- 0.OO48*V
- 2.5000 V
- 5.0000 V
- 7.5000 V
- 9.9951*V
-10.0000 V

+

Base 10

Base 8

Not
Valid
2047
1536
1024
512
1
0
1
- 512
-1024
-1536
-2047
-2048

Not
Valid
3777
3000
2000
1000
0001
0000
7777
7000
6000
5000
4001
4000

Scale
+Full-Scale
+F.S. - 1 LSB
+3A F.S.
+%
+%
+1 LSB
Zero
-ILSB
-%F.S.
-~ F.S.
_3,4 F.S.
..... F.S.-l LSB
-Full Scale

Note: When an A866 module is jumpered to accept ± 5 Volt full scale inputs, the inputs are exactly % of the input values shown in the above
table.
• Rounded off value.

- ! ..* Using MSB output.

/

391

SPECIFICATIONS
Analog Input
Type of Input
Impedance
Input Bias Current
Overvoltage Limit
Perturbations
Encoding Process
Technique
Quantizing Resolution
Encoding Word Time
Encoding Word Rate
Code

Single-ended
>100 megohms
6 nanoamperes, (max.)
± 18 volts, (max.)
The encoding process does not cause
noise at the inptJt
Successive approximation
1 part in 4095 of full range
15 microseconds, max. (includes
·Op·Amp settling time)
64,000 conversions/second, min.
Binary and 2's complement (using
MSB and complement of MSB)

Measurement Accuracy Uncertainty at 23°C
Warm-up Time
3 minutes
Absolute (Ref. to NBS STDS)
± 1 LSB at full scale, max.
Stability
Overall Tempco
Tempco of Clock Period
Long Term

±"1/20 LSBrC, max.
±0.1 percentrC, max.
± 1/2 LSB/6 mos., max.

Sensitivity to Power Supply Voltage Changes
0.002% % V, max., from dc to 1 MHz
For the ± 15 Volt Supply
0.0003% % V, max., from dc to 1
For the ±5 Volt Supply
,
MHz

FUNCTIONS
Analog Inputs
The single-ended dc analog input will accept unipolar or bipolar voltage with
a maximum amplitude of 10 V.
Control Inputs
A high to low level change on either of the two ST CONY inputs when the
CONY EN input is. high or a low to high transition on either of the two CONY
EN inputs when the ST CONY input is low will start the conversion process.
Data Outputs
The data outputs are 12 parallel bits plus the complement of B1 (MSB).
Bit B12 is the LSB. Th"e output code is ftvailable in a binary format when
'the Bl output is used and in two's complement when B1 output is used. The
outputs are TIL-compatible levels.

392

Status Outputs
Three outputs a{e provided to indicate the status of the conversion process.
The BUSY output" becomes high, and remains high while the conversion
process is active. The BUSY output becomes low 50 ns after the data is
available at the output and remains low until the next command to start
the conversion.
The DONE output is the complement of the BUSY level.
The EOC PULSE output becomes a high level for 450 ±50 ns after the DONE
output level goes high.
. .
",

The CLOCK output is a series of 50 ns pulses (min.) generated when the
A866 Module is performing an analog-to-digital conversion.
Detailed information on the module is available on the A866 AID Converter
Module (12-Bit, 15-Microseco'nd) \data sheet available from Logic Products
Sales, Support, Accessories & Supplies Group, DIGITAL, MKl-2/E13, Merrimack, NH 03054.

393

/

K SERIES
K-Series modules are briefly described below. Detailed descriptions are contained in previous editions of the Logic Handbook. and can· also be supplied
by Logic Products Sales Support at DIGITAL Equipment Corporation,
MKI-2/E13, Merrimack, NH 03054.

K003, K012, K026, K028 Gate Expanders
These inexpensive gate expanders offer great logic flexibility and versatility
without a proliferation of module types. It must be und~rstood that these
gate expanders are merely expansions for other K Series gates and can
never be used as separate AND or OR functions.
Kl13, K123, K124 logic Gates
Together with the K003, KOI2, K026 or K028 expanders, these gates perform
any desired logic function, including AND. OR. AND/OR. NAND. NOR, ex-·
elusive OR, and wired AND ..
K134 Inverters
This module contains four inverters with AND expansion capability and an
inhibit inpuf. It may also be AND expanded by K003 Gate Expanders.
K135 Inverters
This module is designed for use in applications that require inverters with
OR expandability. Four inverter' circuits with OR expansion capability and
as common enable pin are contained on the modu'le.
K138 Inverters
.
The Kl38 contains eight inverter circuits that can be used to invert other K
Series outputs to obtain both High (+5V) ~nd Low (OV) levels.
K161 Binary-to Octal Decoder
Three-bit binary numbers at the input to this module will be, decoded into
eight one·at·a-tj me outputs.
K174 Digital Comparator
This module determines which of two 4·bit binary or one digit BCD quantities
is larger or smaller.
K201 Flip-Flop
This superslow memory simplifies sequencing of machine motions, and finds
other applications where the ultimate in noise isolation is needed and speed
is no problem. Its 1 KHz maximum repetition rate makes this flip-flop noticeably more resistant to e>Etremely noisy surroundings than faster types.
K202 Flip-Flop
This module performs shifting, complementing, counting, and other functions
that are beyond the capabilities of simple set-reset flip-flOps built up from
logic gates.
K206 Flip-Flop Register
The 4-bit, set-reset flip-flop register can be used to buffer input signals, to
store one BCD digit, or as a simple 4-bit memory.
K207 Flip-FJops
The K207 is a 4-bit, set-reset flip-flop buffer which can be used to manipulate
or store data.

394

K~lO Counter The K210is a binary or BCD -counter that can be wjred to return to zero
after any number of input·cycles,.from 2 to 6.

K211 Programmable Divider
The K211 is a binary counter that can be wired to produce a high to low
output transition after any number of input cycles from 2 to 16, Count-up
occurs on the high to low transition of the count gate output.
K220 Four-Bit BCD/Binafy Up/Down Counter
The K220 Counter module provides all the circuitry necessary for binary
and binary coded decimal up counting, down counting, presetting and clearing.- This module is useful in many digital position readout and feedback
applications ..
K230 Shift Register
The K230 consists of a 4-bit shift register with a serial data input. Data at
the input is shifted left with each high-to-Iow transition at the shift input
gate.
K265 Reed Relay Drivers
. The K265 has drive circuits for customer mounted relays. Up to five relays
with F0'tm A contacts can be mounted on the single height card. A logic 1
.at each input energizes the retay to provide isolated contact outputs for special interfacing applications.
K281 Fixed Memory
This module is a diode board containing eight 4-bit words which can be
used to construct read-only memories. Codes are stored by cutting out diodes
where zeros are desired.
K282 Diode Memory
_
The K282 is a diode matrix module which initially contains eight 16-bit words.
K302 Dual Timers
The K302 module contains two ~ndependent timer circuits. Each circuit provides three delay ranges: Range one: 0.01 to 0.3 seconds; Range two: 0.1 to
3.0 seconds; Range three: 1.0 to 30 seconds.
K303 On/Off Delays
The K303 can be used for either an ON or OFF delay with a range of 10
p,s to 30 seconds or can be interconnected to form a clock with a period
covering the same range.
K323 One-Shots
This module contains three one-shots that provide output pulse widths from
10 p,s to 30 seconds with either fixed or adjustable delays.
K371, K373, K374, K375", K376, K378 Timer Controls
Calibrated controls for timers, one-shots, and clocks are available in several
ranges:
K371 Clock Control, 200 Hz to 6 KHz
K373 Clock Control, 20 Hz to 600 Hz
K374 Calibrated Timer Control, 0.01 sec. to 0.3 sec.
K375 Clock Control, 2 Hz to 60 Hz
K376 Calibrated Timer Control, 0.1 sec. to 3 sec.
K378 Calibrated Timer Control, 1 sec. to 30 sec.

All of the above controls mount on the K303 and K323 modules.
395

(

K501 Schmitt Trigger
The K501 can be u~ed with the K580 or K581 to provid,e simultaneous true
and complementary signals with full K series drive. Built in hysteresis ~nd
slowed outputs insure reliab~e operation in noisy signal environments.
K990 Timer Component Board
The K990 ts:-a predriJled etched module_for mounting up to six RC networks
for K303 or K323 timer controls.
K579 Isolated AC Inpuf Connecters
The K579 is used to convert 120 VAC inputs to 0 and
5 Vdc logic levels.
The module has eight transformer-isolated Schmitt trigger circuits that provide contact bounce rejection and cause a
5V output when 120 VAC is
applied to the corresponding input. Each input has an LED indicator to indicate when voltage.is present.

+

+

K-to-M, M-to-K Converters
Module M 521 converts from K-series signal levels to M-series. and Module
M 671 converts from M to K. Both are described elsewhere in this Handbook .

..

/

396

-/

\
CABINETS )\ND PARTS
SYSTEM ENCLOSURES, MOUNTING HARDWARE,
CONNECTORS, POWER SUPPLIES, OTHER DESIGN AIDS

I

397

CABINETS AND PARTS
This section is organized into several subgroups as follows:
1.
2.
3.
4.
5.
6.

Cabinets and Cabinet Accessories
Module System Enclosures
Power Supplies
19-1nch Mounting Panels
Four-Slot System Units
Nine-Slot System Units

7. Module Connector Blocks
8.
9.
10.
11.
'12.
13.

Blank Module Boards
Collage Module Boards
Module Extender Boards
Wire Wrappable Module Boards
Wire Wrapping Tools and Accessories
Integrated Circuit Sockets

14. Module Handles, Handle Extenders" and Module Holders
15. Bus Strips, Patch Cords and Accessories

CATALOG SALES
Now, many of the items described in this section are available
at substantial savings through the DIGITAL Direct Sales .Catalog:
Send for your own free copy of the Catalog by filling out the post
card included in this Handbook.

398

H960 SERIES EQUIPMENT CABINETS
This section describes DIGITAL's '''standard'' and "short" size basic equipment cabinets. Two additions to the cabinet line, the H984-S and
H9800-A, are described following this section. The standard and short models
accept panels or equipment designed to mount in standard 19-inch (48.26
cm) electronics cabinets or racks. Basic color of these cabinets is black. Gray
is used for end panels and the border of the cover panels.
The ,cabinets can be placed individually or attached to form a multibay configuration. The accessories and hardware available include front and rear
doors, panel mounting door frames and door skins, end panels, bezel and
logo panels, blower fans, and power controllers'.
Standard Size Cabinets and Accessories
Five basic cabinet configurations (H960-BC, H960-BD, H960-CA, H961-A,
H961-AA) are available in the standard size cabinet series. The H961-A, -M
are intended primarily for add-on configurations. The standard size cabinet is
71.5 in. (181.61 cm) high and provides 63.0 in. (160.0 cm) of vertical mounting space at the front; an additional 63.0 in. of mounting space is available
at the rear of the cabinet. These cabinets are configured to meet the requirements of most customer applications.
All standard size cabinets are configured around the basic H950-AA Cabinet
Frame. These cabinet frames are drilled with 0.25-in. (O.64-cm) diamete~
holes at standard EIA spacings to accommodate equipment, panels, or devices which are designed to mount in standard 19-in. (48.26-cm) electronics
cabinets or racks. Some of the cabinets contain an 861-A, 861-B, or 861-C
Power Controller for distribution and control of the main power to the equipment installed. Six of the cabinet configurations include a rear mounting
panel door frame, which is also drilled with 0.25-in. (O.64-cm) diameter holes
at standard EIA spacings; this mounting panel door frame allows the equipment and devices mounted on.it to be swung out for maintenance or adjustment. Optional accessories as specified by the customer can be added to
any of the available configurations. The parts and accessories included with
each of the four standard size cabinet configurations are listed in Table I,
which also lists the optional accessories that are available for use with these
cabinets. All cabinets are completely assembled before shipment.
Figure 1 illustrates a typically configured standard size cabinet front. Figure
2 illustrates the installation of typical accessories on a standard size cabinet
frame, and Table 2 identifies and describes these accessories. Complete
descriptions of the H950-AA Cabinet Frame and the accessories for standard
size cabinet frames are contained in the HARDWARE/ACCESSORIES CATAlOG published by Digital Equipment Corporation.

399

Table 1
Standard Cabinets
H960·BC, H960·BD, H960·CA, H961·A, H961·AA .
/

Q

to) C
lD lD ~

6

\D

Q\

i

Q\

::z: ::z:

c ~.

0 .!t .!t
\D \D \D
Q\

Q\

l: l:

Q\

::z:
Description

Catalog No.
1

1 1 1 1

1

1

1

1 1

1

1

H950-BA
H950-CA
1. H950-0A
1

H950-EA

1 1

H950-FA
H950-HA
H950-HC
H950-HD
H950-HF
H950-HG
H950-HH
H950-HK
H950-JA

1 1 1 1 1
5

5 5 6

1 1 1 1 1
2
1

2 2
1

1

1 1 1 1 1
1

1 1

1

1
1 1

1

1 1

H950-AA

1

H950-LA
H950-LB
H950-PA
H950-QA
H950-SA
H952-AA
H952-BA
H952-CA
H952-CB
H952-GA
H950-G
H952-HA
74-06782
74-06793
12-09154
12-09703
861-A
861-B
861-C
861-0
861-E

Cabinet Frame, 19 in. wide, 69 in_ high, 25
in. deep
Full Door (RH) (front or rear mounting)
Full Door (LH) (front or rear mounting)
Mounting Panel Door Frame (RH) (rear mounting)
Mounting Panel Door Frame (LH), (rear mounting)
Mounting Panel Door Skin
Short Door (covers 21 in. mounting space)
Short Door (covers 26 1,4 in. mounting space)
Short Door (covers 31% in. mounting space)
Short Door (covers 42 in. mounting space)
Short Door (covers 471,4 in. mounting space)
Short Door (covers 52% in_ mounting space)
Short Door (covers 63 in. mounting space)
Short Door (covers 21 in_ mounting space)
(used with H952-BA installed)
Logo Frame Panel (aluminum)
Logo Frame Panel (plastic)
5% in. Bezel Cover Panel
10 112 in. Bezel Cover Panel
Filter (for H952-BA or H952-CA)
End Panel (require 2 per ca6inet)
Stabilizer Feet (pair)
Fan Assembly (top mounted) (115 Vac)
Fan Assembly (top mounted) (230 Vac)
Filter Strip Set (front and rear) (joining two
cabinets)
Cabinet Table
Free-Standing Table
\
Kickplate (use with H952-BA)
Kickplate
Drawer Mounting Slides
Drawer Mounting Slides (tilt)
Power Controller (90-130 Vac, two phase)
Power Controller (180-270 Vac, single phase)
Power Controller (90-135 Vac, Single phase)
Power Controller (90-130 Vac, three phase)
Power Controller (180-270 Vac, three phase)

400

Table 2
Standard Cabinet Frame H9So-AA and Accessories
Figure

2
Item Part No.
1
1
2
2
3
4
5
5
6
7
8
8
9
10
11
12
12
12

-I"

H950-DA
H950-EA
H950-BA
H950-CA
H950-SA
74-06706
H952-CA
H952-CB
H952-AA
H952GA
H950-LB
H950-LA
H950-PA
H950-QA
H950-G
H950-HA
H950-HC
H950-HD

12 H950-HF
12 H950-HG
12 H950-HH
12 H950-HK
13 - H952-FA
14 74-06782
14 -,74-06793
15 H952-BA
16 H952-EA
17 74-11606
18 H950-AA

Description
Mounting Panel Door Frame (right hanging)
Mounting Panel Door Frame (left hanging)
Door, Front or Rear Mounting (right hanging)
Door, Front or Rear Mounting (left hanging)
Air Filter
Fan, Cover Plate
Fan Assembly (115 Vac)
Fan Assembly (230 Vac)
End Panel (left or right side)
Filler Strip Set (front or rear)
Frame Panel (plastic)
Frame Panel (aluminum)
Bezel Cover Panel, 5.25 in. (13.34 cm)
Bezel Cover Panel, 10.50 in. (26.67 cm)
Tabletop Assembly
._
Short Door, covers 21.00 in. (53.34 cm) mounting space
Short Door, covers 26.25 in. (66.68 cm) mounting space
Short Door, covers 31.50 in. (80.01 cm) mountirg space
Short Door, covers 42.00 in. (106.68. cm) mounting space 1
Short Door, covers 47.25 in. (102.02 cm) mounting space
Short Door, covers 52.50 in. (133.35 cm) moun~ing space
Short Door, covers 63.00 in. (160.02 cm) mounting space
L.eveler Set (4)
Kickplate (used with H952-BA stabilizer feet)
Kickplate
Stabilizer Feet (pair)
Caster Set (4)
Bottom Screen
Frame, 19.00 in. (48.26 cm) wide, 69.00 in. (175.26 cm)
high, 25.00 in. (63.50 cm) deep

401

(

\.
H9!10-LA
LOGO FRAME PANEL

r---

1

H9!10-QA
COVER PANEL

I
I

H9!10-PA
'COVER PANEL
H950-PA
COVER PANEL

10.5

~7)
!I.25
( 13.34)

I~
I ~)
5.25

H950-QA
PANEL

COV~

6 3.0
(16 0.02)
TOTAL
IIIOU NTING
S PACE

(10.5)
( 26.67)

H950-QA
COVER PANEL

l

H950-HA
SHORT DOOR

B

7406782
KICI(PLATE

21.0

(53.34)

t=

J

Centimet.,. in par.nth••••

Figure 1. Typical Standard Cabinet Front Cover Panel
and Short Door Configuration

402

(

Figure 2. H950-AA Standard Cabinet Frame
and Accessories

403

,I

Front view of H950-AA frame
with optional side panels, logo,
fan, etc.

Rear view of H950·AA frame.

404

//

How to Order a Standard Size Cabinet Assembly
Determine if one of the five basic cabinet assembly configurations (H960-BC,
H960-BD, H960-C.oA, H961-A, H961-AA, will fulfill your requirements by referring to Table 1 and comparing th~ items that comprise each configuration.
If one of these basic configurations will satisfy your requirements, you can
order the completely assembled cabinet by specifying that cabinet assembly
number; e.g., H960-BC, H960-BD, H960-CA, H961-A, H961-AA. In addition to
the accessories included in the eight configurations, optional accessories are
available, e.g., short doors, a cabinet table, and drawer mounting slides.
If one of the basic configurations will not fulfill your requirements, you can
"build up" and order a cabinet that will suit your specific requirements by
ordering an H950-AA standard size frame and the accessories (by specific
part nUQ1bers) that you require. The frame and the accessories that you select
will be shipped completely assembled .

•

Short Size Cabinet and Accessories
The short size cabinet (H967-BA or H967-BB) is 50.0 in. (127.0 cm) tall and
provides 42.0 in. (106.7 cm) of vertical mounting space at the front; an additional 42.0 in. (l06.7 cm) of mounting space is available at the rear of the
cabinet.
Figure 3 illustrates a typically configured short size cabinet front. Figure 4
illustrates the installation of typical accessories on a short size cabinet frame,
and Table 4 identifies and describes these accessories. Complete descriptions Qf the H957-AA Cabinet Frarrne and the accessories for short size cabinet frames are contained in the HARDWARE/ACCESSORIES CATALOG published by Digital Equipment Corporation.
This short size cabinet is configured around the basic H957-AA Cabinet
Frame. These cabinet frames are drilled with 0.25-in. (O.64-cm) diameter
holes at standard EIA spacings to accommodate equipment, panels, or devices that are designed to mount in standard 19-in. (48_26-cm) electronics
cabinets or racks. Optional accessories as specified by the customer can be
added; table 3 lists the parts and accessories included. Table 3 also lists the
optional accessories that are available for use with these cabinets_ All
cabinets are completely assembled before shipment.

405

Table 3
Short Cabinet, H967·BA and H967·BB
CD
CD

Ii;

C;
"\0 0 \ en X
7:

,
Catalog No.

1 1

H957-AA

1 1

H957-BA
H957-CA
H957-DA
H952-HA
H970-BA
H970-CA
H950-HA
H950-HC
H950-HD
H950-HF·
H950-JA

1 1

1 1

1 1
1 1

H950-PA
H950-QA
H952-BA
H950-G
H957-FA
H957-FB
H957-GA

Description
Cabinet Frame, 19 in. wide, 47-8/16 in. high, 25
in. deep
Full Door (RH) (rear mounting)
Full Door (LH) (rear mounting)
:Mounting Panel Door Frame (RH)
Free-Standing Table
Free-Standing Table
Free-Standing Table
Short Door (covers 21 in. mounting space)
Short Door (covers 261,4 in. mounting space)
Short Door (covers 31 y ..,
Power Supply, +5 V @ 7 A (mounts on
H034 casting, not included)
"

H909·BA General Purpose Logic Box'

DEC Part No.
12-10945
74-09459 (left)
74-09449 (right)
H034
H934-CB
BBll-B
H726·B

>

The H909-BA General Purpose Logic Box is the .same as the H909·A except
that it is equipped with an H755 Power Suppy and BC05H Power Control.
The H755 provides +15 Vdc @ 2 A, -15 Vdc @ 2 A, and +5 Vdc
@ 13 A. The BC05H consists of a line cord and circuit breaker.

417

K724 INTERFACE SHELL
The K724 Interface Shefl provides the connectors and the mechanical support for self-contained interface modules' K650, K652, and K658. Up to two
K650, K652, or K658 modules may be installed, with eight module sockets
remaining for decoding or gating modules. The limit of two DC, Driver mod- \.
ules is due to the fact that they cannot be reverse(j in their connector
sockets.
Convenient wiring channels are obtained between units if they are mounted
on 12" centers vertically and 6" centers horizontally. This way a total of up
to 32 input converters and 16 output converters fit in one square foot of
panel space, along with up to 16 logic modules.
The K724 provides only logic power and ground connections between all but
two sockets. It is primarily intended for very simple logic systems or for large
systems where all input and output logic levels are connected to a separate
logic unit by connector cables.

..
419.

EXPANSION MOUNTING BOX -

BAII-ES
I

The BAll-ES Expansion Mounting Box is a steel enclosure that is designed
to house up to six four-slot or three nine-slot system units and an H720-E
Power Supply. The BAll-ES enclosure cO!,1sists of a chassis with brackets for
mounting the system units and power supply; four side-mounted fans forI
forced air cooling; a removable top cover; two 12-09703 Tilting Chassis Slides;
and an H950·QA Cover Panel. Included with the mounting box is an 8.5-ft.
external I/O UNIBUS flat cable (BCllA-SF) used with PDP-II Systems. An
Internal power cable is contained within the box; the power cable distributes
dc power and power signals from the power supply to each of the BBll System Units installed. An access hole at the rear of the box provides clearance
for the receptacles and controls on the H720-E Power Supply. The BAII-ES
is 16.75W by 23.25D by IO.50 It H, excluding the cover panel ~nd slides".
The BAll-ES can be installed in any electronics cabinet or rack equipped with
19" mounting rails (front and rear) drilled at standard EIA spacings. The
BAII-ES attaches to the cabinet frame by the two tilt slides mounted on each
side of the unit. The tilt slides enable" the unit to be pulled from UTe cabinet
and tilted to facilitate servicing the system units or power supply.

SAll-ES

420

BAll·KE
BAll·KF

EXPANSION MOUNTING BOX -

BAII-KE, BAII-KF

The BAII-KE and -KF Expansion Mounting Boxes are steel enclosures designed
to house up to five single system units or the equivalent in a mix of single
and double system units. Up to 16 hex and 6 quad module circuit boards
could be accommodated. The H765 power system is included, which supplies
multiple voltages to the circuit boards and can deliver up to 660 watts dc.
The BAll-KE is for 115V operation, while the -KF is for 230V. Otherwise, the
two are identical.
The BAll-KE and -KF chassis are 17.12"W by 25"0 by 10.44"H with slides
and power system but without cover panel. They can be installed in any electronics cabinet or rack equipped with 19" mounting rails (front and rear)
drilled at sfandard EIA spacings. The units attach to the cabinet frame by
the two tilt slides (included) which allow horizontal, 45°, and 90 0 positions
(with front panel facing up). An H950-QA Cover Panel and UNIBUS cable are
also included. The units are Underwriters Laboratories (UL) listed.
The H765 Power System contains two fans' which also cool the modules by
drawing air from front to rear. 'The entire Power System can be swung away
from the main chassis for maintenance. Power outputs, through individual
regulator modules are as follows:
two H744 regulators
one H745 regulator
one H745 regulator

one 54-11086 regulator

+5V @25A (each)
-15V@10A
+20V@ SA
-5V @ 1A plus the current from
the +20V output up to
a total of SA for both
+15V@ 4A
421

POWER SUPPLrtS, PQWER CONTROLLERS,
AND STEP·DOWN TRANSFORMERS
The electrical and mechanical features of a complete line of power supplies,
power controllers', a step-down transformer, and power supply accessories
are summarized in the following tables and paragraphs. These items are
described in detail in the HARDWARE/ACCESSORIES CATALOG published by
Digital Equipment Corporation. The following three paragraphs and tables
summarize the power supplies according to their usual use. The fourth
paragraph and table summarizes the power controllers and a step-down
transformer. Power supply accessories are summarized in the fifth paragraph
and table.
+5 Vdc POSITIVE LOGIC POWER SUPPLIES
These +5 Vdc positive logic power supplies are designed to provide Vee
(+5 Vdc) to the integrated circuits mounted on modules used in logic systems and interfaces. Many small systems and most interfaces comprise
M-series gating, multiplexing, bus receivers, and bus transmitter modules
that require only. a Vcc..power supply. The power supplies summarized in this
table are ideal for these applications because of such features as overvoltage
and short circuit protection, remote sensing, and input voltage ranges.

422

+5 Vdc positivi Logic

~
I\)

Part No.

Input Specs

Output Specs

H716

120 Vac
240 Vac
(47-63 Hz)

+5 Vdc @ 4.0 A,
3 % regulation
-15 Vdc @ 1.5 A,
5% regulation

H726-B

120/240 Vac
(47-500 Hz)

w

. +5 Vdc @ 7.0 A,
1 % regulation

I"

pow~r Supplies
Dimensions

Features

5.25 in. long X 4.125 in.
high X 12.00 in. deep
(13.34 X 10.48 X 30.48 cm)

Floating output
Short circuit proof
Overvoltage protection for
+5 Vdc output

16.50 in. long X 2.23 in.
high X 6.25 in. deep
(41.91 X 5.66 X 15.88 cm)

Floati ng output
Short circuit proof
Overvoltage protection

SY~M

POWER SUPPLIES
.
System power supplies are designed to provide Vee (+ 5 Vdc) and reference
voltages to an entire system or to a large interface when spare power is not
available from the system supply. The power supplies summarized in this
table are ideal for these applications because of their high current output
capabilities and voltage output ranges.

System Power Supplies_

Part No.

Input
Specs

/

Output Specs

Features

H720-E
(BAll-ES
Mounting Box)

120 Vac,
47-63 Hz

+5 V @ 22 A
-15 V @ 10 A
+8 V (avg) @ 1.5 A
-22 V @ 1.5 A

Input frequency monitor
Ac and dc low power
detection
Overvoltage and overcurrent protection

H720·F
(Same as
H720-E)

240 Vac
47-63 Hz

Same as H720-E

Same as H720-E

H740-D*
19-in. (48.26 cm)
panel-mounted

115 Vacl
230 Vac,
47-63 Hz

+5 V @ 17 A
-15 V @ 5 A
+15 V @ 1.0 A

Ac frequency monitor
Ac and dc low voltaEle
detection

-

I

'" requires a BC05H for 115 Vac_; a BC05J for 230 Vac

H755 POWER SUPPLY
The H755 is a versatile system power supply that provides outputs of +5 Vdc
@ 13 A and ±15 Vdc @ 2 A. In addition, the H755 generates an AC La
output when the line voltage drops below 10 percent of its specified value;
a DC La output when dc out is insufficient to supply the load; and an LTC
line Frequency Signal which is available for time measurement purposes.
Included on the H755 are a fan and a thermostatic switch on the heat sink
which provide overheat protection by opening the ac line at 220°F ±5°.

(

424

ALL RES.
ARE sw 5%

+=I\)
tTl

H755 POWER SUPPLY

\\

"
\
\

SPECIFICATIONS
+5 Vdc: ,~

4.75 to 5.25 Vdcat 0-13 A
Overvoltage protection at 7 Vdc maximum (5.7 Vdc minimum) is a crowbar with a fuse.
Current protection is a ,15 A fuse and a 16 A fold back.
Regulation-line regulation of 1 % or 50 mV, load regulation of 2% from no load to full load; maximum ripple is
50 mV Pop.

±15 Vdc:

±1 % minimum at 2 A.
Current protection-3 A fuse and foldba"'ck.
Reg'ulation-.03% and less than 5 mV pop ripple.
Voltage sensing-remote, two wire per output.
Full load !?tep change recovery: <50 p.S.

DC LO, AC LO:

Rest state-25 p.A (max) @ 3.5 V
Asserted-.8 V (max) @ 50 rnA
Load Impedance-390n in parallel with .001

p.f

to +5 V

Line Frequency This signal is a square wave with a period at line freSignal (LTC):
quency, a pulse height of 3.5 V, and a base line at .4 V
maximum at 16,mA sink current.
~

Mechanical Dimensions
16 3,4 inches (42.54 cm)
4 % inches (12.26 cm)

Length:
Width:
Height:

5 1,4 inches (13.33 cm)

Signal Sequence
103-127 VAC

POWER ON/OFF
+5V
+5 V OUTPUT

/
+3.SV

I

DC LO L

J
AC LO L

+3.5 V

~I
~!,';~I-

'I~I
--=-6MS

, -

-426
\..

MIN.
1

'.

Related Products

DEC Part No.
BC05H·6
BC05J·6
H909·A
"12·09351·15
12·09378·01

Function'
Provides 115 Vac input to an H755; six·foot power
F?rovides 230 Vac input to an H755; six·foot power
Logic enclosure; accommodates an H755 supply
other logic.
Cable Connector Housing (male); connects to DC
put receptacle (J9)
Pins for connector housing 12·09351·15

cord
cord
and
out·

The above products are described elsewhere in this section.

DC OUTPUT
(J9 UNDERNEATH
REMOVABLE P.c.
SOARD)

H755

427

POWER CONTROLLER AND STEP-DOWN TRANSFORMER
A power controller and a power transformer are summarized in this- table.
The power controller is ideal-for distributing ac power within a system; the
power transformer is ideal for stepping down commercial power to "115 Vac
for use within a system.

-.

Power Controllers and Step-Down Transformer
Part
No.

Input Specs

Output Specs

Features

90-130 Vac,2 phase,
16 A/pole

90-130 Vac at 12 A
(each ac outlet)

Local or remote control
Four switched, dual
receptacles

"180·270 Vac, single
phase, 16 A/pole

180-270 Vac at 12 A
(each ac outlet)

Two unswitched, dual
receptacles

90-130 Vac, single
phase, 24 A/ pole

90-130 Vac at 12 A
(each ac outlet)

19-in. (48.26-cm)
mounti ng-rail
mounted

90-130 Vac, three
24A

90-130 Vac

86l-E

180-270 Vac, three·
phase, 24A

180-270 Vac at 12 A

19-in. mounting-rail
mounted

HJ22

115; 189, 200 217,
230,245 Vac

115 Vac at 4.0 A

19-in. (48.26-cm)
panel-mounted

861-A

861-8
861-C

861-0

'~1>f1ase,

at 12 A

19-in. mounting-rail
mounted

Power Supply Accessories
Part No.

Use

BC05H-6

Line set designed to connect 115
Vac input to Power Supply H740-0

115 Vac
6-ft. O.:.8-m) power cord

BC05J-6

Line set designed to connect 230
Vac inp~t to Power Supply H740-0

230
6-ft. (1.8-m) power cord

H322

Distribution panel designed to provide general-purpose signal, power,
and ground distribution from one or
more devices to one or more
devices.

Fits 19-in. (48.26-cm) rack.
Two 40-pin H854 and two
9-pin 12-09350-09 connectors and nine 10-screw terminal strip~.

Specifications

428

NINETEEN-INCH (48.26-cm) ELECTRONICS RACK
MOUNTING PANELS
Mounting panels are designed to provide mounting space for module connector blocks and are usually used to expand a logic system. They are designed to mount in'standard 19-in. (48.26-cm) electronics racks or cabinets.
One (H020) of these mounting panels is a bare frame for mounting module
connector blocks, some (H91l-J, H91l-K, H91l-R, H91l-S, K943-R, and '
K943-S) are equipped with connector blocks and are prebused for power and
ground, others (H916 and H917) are equipped with connector blocks and a
power supply and are prebused for power and ground, and one (H914) is a
frame that is equipped with connector blocks but is not bused or wired for
power or ground.
The following table summarizes the mounting panels; individual detailed descriptions of these mounting panels are 'contained in the HARDWAREI ACCESSORIES CATALOG published by Digital Equipment Corporation.

\ !

.

,.

429

19-1n. Reek Meunting Panels
Part Number

Description

H020

Bla'nk mounting panel that accommodates eight connector
blocks; mounts in a standard 19-in. (48.26-cm) electronics
rack.

H911-J

H020 equipped with eight H803 connector blocks to accommodate 64 single-height or 32 double-height, standardlength modules; bused for power and ground.

H911-K

Same as H911-J except wired and bused for power and
ground.

H911-S

Same as H911-K except accommodates extended-length
~
modules.

H914

H020 equipped with eight H808 connector blocks to accommodate 32 single-height or 16 double-height, standardlength modules_

H916

H020 equipped with an 'H716 Power Supply and six H803
connector blocks to accommodate 48 single-height or 24
double-height, standard-length modules; bused for power
and ground.

K943-FP

H020 equipped with eight' H800F connector blocks to accommodate 64 single-height or 32 double-height modules
with contact fingers on only one side; bused for power and
ground. Connector blocks ~quipped with solder-fork pinsfor 24 AWG wire. (Formerly designated K943-R.)

K943-WP

Same as K943-FP except equipped with eight H800W connector bloCkS that have wire wrap pins for 24 AWG wire.
(Formerly deSignated K943-S.)

430

Typical System L!nit Mounted On Casting Plate.

H9271 FOUR-BY-FOUR SLOT SYSTEM UNIT
The H927I is a general purpose, four wide:by-quad height system unit
, mounted within an jntegral card cage assembly. Physically, the H927I is
identical to the H9270 LSI-l1 backplane/card·' cage assembly with the exception that the LSI-II etched board bus structure and power connector are
omitted. This leaves the H927I free to be used as a general purpose system
unit for non-standard LSI-l1 configurations or for virtually any other application requiring a compact, easily mountable logic rack. The system unit is
manufactured and machined in such a way as to facilitate mounting in any
plane or axes.

The H927I consists of two H863 slotted connector blocks placed end to end
for the mounting of four quad height, eight double height, or sixteen single
height modules or any combination of the above totaling sixteen single slots_
The blocks are mounted within a recta'ngular steel frame allowing easy access
to the pin side of the blocks for wire wrapping, and the card cage surrounds
the module insertion side of the logic rack.

432

J

\

H9271

NINE-SLOT SYSTEM UNITS
Nine-slot system units, like four-slot system units, are designed to provide
mounting sockets (slots) for logic system modules. They, too, are designed
to mount in the various module system enclosures offered by Digital Equipment Corporation. Nine-slot system units accept up to six four-slot and
three one·slot module connector blocks mounted in three groups (one fourslot, one one-slot, and one four-slot module) mounted end-to-end. Since
each of the module connector blocks used with these system units has two
rows of slots, a fully complemented nine-slot system unit provides mounting
facilities for 54 single-height, 27 double·height, or nine quad-height and 16
single- (or eight double-) height modules.
The" following table summarizes three nine·slot system units; individual descriptions of these system units are contained in the HARDWARE/ ACCESSORIES CATALOG published by Digital Equipment Corporation. Descriptions
for the new LSI-ll compatible system -unit and the DDll-D UNIBUS system
unit follow this table.

433

"
Nine-Slot
System Units
Part Number
BBll-B

Description
H034 equipped with six H863 and three H8030 connector
to accommodate 54 single-height modules, 27
double-height modules, or nine quad-height and eight
double- (or 16 single-) height modules; prewired for UNIBUS, power, and ground. Used for general UNIBUS interfacing.
bloc~s

H034

Blank nine-slot system, unit that can accommodate six
H863 and three H8030 connector blocks; mounts in various module system enclosures.

H934-CB

Same as BBll-B except not prewired for UNIBUS, power,
or ground.

DDVII-B NINE-BY-SIX SLOT LSI-II SYSTEM UNIT

DDVII-B

The DDVll-B is an expanded version of the standard LSI-ll backplane for
use when either more dedicated LSI-ll compatible logic space or non-LSI-ll
compatible space for various other special purpose logic modules or both
is required. A nine-by-four slot section (36 individual module slots) of this
system unit is prebused specifically for LSI-II bus signal, power and ground
connections. The remaining nine-by-two slot section (18 slots) is provided
with +5 Vdc and-12 Vdc power connections only; this leaves the remaining pins free for use with any special logic modules to be used in conjunction with the LSI-ll family of modules arid bus requirements .
./ "

434

Physically, the DDVll·B consists of an H034 system unit mounting frame,
six H863 and three H8030 connector blocks, and the etched board bus
structure necessary for signal routing. The etched board completely overlays
the entire pin side of all connector blocks and. is recessed sufficiently to
allow wire wrapping on those same pins with 30 AWG wire. Detailed descrip·
tions of the fr.:.ame and connector blocks are found in their respective sec·
tions of this Handbook and in the Hardware/ Accessories Catalog.
An optional card cage, type H0341, is also available to provide protection·
against physical damage to modules and to serve as a logic card guide. This
card cage completely surrounds the slot side of the system unit and is shown
in the photograph.
A. module slot assignment diagram is detailed jn Figure 1 as viewed from
the slot or module insertion side of the system unU.

DDVl1·B with H0341 Card Ass'y.

Rows E and F contain the 18 user-defined slots with power and ground con·
nections provided.
Rows A, B; C, and D are dedicated to the LSI·l1 bus. Any module meeting
the LSI·l1 bus specifications may be used in this portion of the DDVll-B.
Slot number 1 in Rows A, B, C, and D is reserved for the LSI·Il processor
module. The position numbers indicate the bus grant wiring scheme with
respect to the processor module. The bus grant signals propagate through
the slot locations in the position order shown in Figure I until they reach
the requesting device. Any blank slots must be jumpered to provide bus
grant signal continuity or it is recommended that unused locations occur
only in the highest position numbered locations.
Bus Terminator-An additional 120 ohms of termination is required after
six unit loads on each bus line as shown.
435

.

r.

250.0.

I

I

ONE
UNIT
IDAD

ONE
UNIT
IDAD

1

1

ONE
UNIT
LOAD

ONE
UNIT
LOAD

120.0.

+

+
\.

,3.4V

-=

-

)

" LOADS
15 UNIT

-=

-

3.4V

.

TERM

PROCESSOR

The TEV11 module provides the necessary 120 ohm bus terminators and
should be installed into the next unused slot after the last module or into
slot 9, row card C and D to maintain proper bus termination.
,..
The backplane pin assignments of the DDVll·B are listed on Table 1.
If a system enclosure is required for the DDV11-D4- an H909-C enclosure is
available. and was specifically designed for mounting the DDVll·B. The system unit has topped mounting holes to facilitate installation in the H909-C
enclosure. The H909-C is described in this handbook and has space allocated
for the installation of a power source.

/

436

Ol'-~-I

"TI

QQ'

c:

(D

....
c
c

....<
':"'
CD

-

POSITION 2

III

03- +-[

POSITION 3

II

POSITION 6

II :

POSITION 5

o;;: 06--/-C

POSITION 10

III

POSITION 9

07--1-1

POSITION II

III

POSITION 12

+-I

POSITION 14

II

04-

08 -

-i-S

- P6SiTiON15--

09-+{ .
1tOW_

3:

--- - J

--J

c- -----

p6s~

c----

ILI_ _ _ _ _ _ _ _ _ _ _---'

lie -

POSITION I

III...[_ _ _ _ _ _ _ _ _ _ _ _~

~

1:=
_______ _

~ ILr===
_ _ _ _ _ _ _ _ _ _ _ _~

III

POSITiONlJII

II

----I

=:=J I c

POSITION 16

"

r- ._.

.I

- -------..

A

0

~

0.

'"

(i)

W

PROCESSOR

02-~-C

USER DEFINED SLOTS
MODULE INSERTION SIDE

c:

en

a
):III
III

QQ'
:::J

MODULE (COMPONENTS MOUNTED ON OPPOSITE SIDE)

3(D
:::J
t+

C

;'

<:::: _____

OQ

'"

I»

RIDGE NEXT
MOWLE
KEYING

CUTOUT ____

MODULE KEYING RIDGES

3

'11

. TO FRAME

["

Q.

Ic{

n

H034 MOUNTING FRAME
--------

11111

A

1111 1111

--------------------

&

1111 III

C

1111 1111

0

III 111

E

1111111111'
WIRE WRAP

F

PINS?

/11111

Table 1.
SIDE
'ROW
A

BSPARE 1

BAD 17

E

+12
BOOUT L

F

BRPLY L

H

J

BOIN L
BSYNC L

K

BWTBT L

L
M
N

0

~

w

00

A&C

+5
-12
GNO

B
C

'.

1

2
A&C

DDVII-B Backplane Pin Assignments

BSPARE 2 \
BAD 16

2
B&O

1

2

1

2

1

B&O

E

E

F

F

BOCOK H

+5
-12
GNO
BLANK

BLANK
BLANK
BLANK

+5
-12
GNO
BLANK

BLANK

BPOKH
SSPARE 4
SSPARE 5

BLANK

r

4

+5
-12
GNO
+12
BOAL 2 L

BLANK

BLANK
BLANK
BLANK

SSPARE 6

BLANK

BLANK

BLANK

BOAL 3 L

SSPARE 7

BLANK

BLANK

BLANK

BLANK

SSPARE 8
GNO

BLANK

BLANK
BLANK

BLANK

BLANK

GNO

BOAL4 L
BOAL 5 L

BLANK

BLANK

MSPARE A

BOAL 6 L

BIRQ L

MSPARE A

BOAL 7 L

MSPARE B
MSPARE B

BLANK
BLANK

BIAK I L
BIAK 0 L

GNO

BOAL8 L

GNO

BLANK

BLANK

BLANK

BLANK

BOMR L

BOAL 9 L

BSACK L

BLANK

BLANK

BLANK

'BLANK

SSPARE 1
SSPARE 2'
SSPARE 3

BLANK

BLANK
BLANK

i

BLANK

BLANK

BLANK

'BLANK

P

BBS7 L

BHALT L

BOAL 10 L

BSPARE 6

BLANK

~BLANK

BLANK

BLANK

R

BOMGIL

BREFL

BOAt 11 L

BEVNT L

BLANK

BLANK

BLANK

BLANK

S

BOMG 0 L
BINIT L

PSPARE 3

BOAL 12 L

BLANK

BLANK

BLANK

BLANK

GNO

BOAL 13 L

PSPARE 4
GNO

BLANK

BLANK

BLANK

BLANK

BOAL 0 L

PSPARE 1

PSPARE 2

BLANK
BLANK

BLANK

+58

BLANK
BLANK

BLANK

BOAL 1 L

BOAL 14 L
BOAL 15 L

BLANK

BLANK

T
U
V

+5

MODULE CONNECTOR BLOCKS
Digital Equipment Corporation offers a variety of module connector blocks
to suit the requirements of almost any logic system. Most M-series systems
use H803, 30 AWG, wire wrap blocks for modules with contact fingers on
both sides. However, a system requiring 24 AWG interconnections, or using
a large number of type 913 Patch Cords, might use H80S Connector Blocks
because of the wider spacing of the connector pins. A system using K-series
and certain A-series modules (Le., contact fingers on only one side) can
use H800 Connector Blocks. Connector blocks with slotted ends should
generally be used in systems where the modules are quad height or larger.
The following table summarizes the module connector blocks; individual detailed descriptions of these module connector blocks are contained in the
HARDWARE/ACCESSORIES CATALOG published by Digital Equipment Cor• poration.

439

BLANK MODULE BOARDS
Blank module boards provide a convenient method of breadboarding (mounting)' experimental or prototype circuits, and they provide a low-cost method
oj producing limited runs of production modules with special circuitry.
They are completely compatible with the standard module mounting blocks
summarized elsewhere in this publication .and described, in detail in the
HARDWARE! ACCESSORIES CATALOG published by Digital Equipment Corporation. These glass epoxy, blank module boards have etched and goldplated contact fingers and all have handles attached. The attached handles
are stamped with their Digital Equipment Corporation identification number
("part number). The handles on copper-clad boards are attached with reusable
nylon hardware. Blank handle 937, described elsewhere in this publication,
is available; this blank handle can be user-titled and is, therefore, particularly
useful for identifying user-etched, copper-clad module boards- for limited
production runs.

Blank module boards are available in three basic forms: plain, p~rforated,
and copper-clad. The following table lists and describes the blank module
boards that are available.
/
Plain- blank module boards provide complete flexibility in the placement of
components since they are not perforated (predrilled), and they permit easy
changes to the circuitry since etching is not required. Component connections
are made via hook-up wire. Plain blank boards are, therefore, ideal for experimental' or prototype modules because they permit easy changes to the
Circuitry and nearly unlimited- component placement, and yet they provide
stability and security for the circuits and components. All sizes are available,
and all have etched and gold-plated contact fingers.
Perforated blank module boards provide nearly the same advantage as plain
blank module boards except they are predrilled with 0.052-in. (0.132-cm)
diameter holes spaced 0.1 in. (0.254 cm) center-to-center horizontally and
vertically. This eliminates the need for user drilling and only Slightly reduces
the choices of component placement. 1\11 sizes are available, and all have
etched and gold-plated contact fingers.
Copper-clad blank module boarqs provide a method of producing limited runs
of modules with special circuitry and components. A complete selection of
copper-clad blank module boards is available: some may be user-etched on
both sides and others may be user-etched on one side. All sizes are available,
and all have et~hed and gold-plated contact fingers.
These blank module boards are described in the following table; each of
these blank module boards is described in detail in the HARDWARE/ ACCESSORIES CATALOG.

441

Blank Module Boards

Part No.

Type

Contact
Fingers

W939

Plain

36

Single·
height,
extended
length

Bare board with 36 feed·
through eyelets.
Printed circuit etching from
the eyelets to the' contact fingers.

W970

Plain

36

Single·
height,
standard
length-

Bare board with 36 platedthrough holes in the printed
circuit etching to the contact
fingers. -

W971

Plain

72

Double·
height,
standard
length

Same as W970 except doubleheight and has 72 platedthrough holes and two handles.

W972

Copper·
clad

36

Single·
height,
standard
length

Coppef-clad on both Sides.

W9720

Copper·
clad-

36

Single·
height,
extended
rength

Same as W972 except extended length.

W9721

Copper·
clad

72

Doubleheight, extended
length

Same as W9720 except dou·
__ ble-height and has -two attached handles.

W9722

Copper·
clad

144

Quadheight,
extended
length

Same as W9720 except quad~
height and has four attached
handles.

W973

Copper·
clad

72

Doubleheight,standard
length

Same as W972 except doubleheight.

W974

Perforated

36

Singleheight,
standard
length

Perforated board, with - 36
plated-through holes in the
printed circuit etching to the
COFttact fingers.

Double·
height,
standard
length

Same as W974 except doubleheight and has 72 - platedthrough holes and two handles.

"
W975

Perforated

72

Size

442

Description

Blank Module Boards (Cont)

Part No.

Type

Contact
Fingers

W990

Plain

18

Singleheight,
standard
len~

Bare board with 18 split·lug
terminals. Printed circuit etch·
ing from the split-lugs to the
contact fingers. This board
has contact fingers on one
side only.

W991

Plain

36

Double·
.height,
standard
. length

Same as W990 except double·
height and has 36 split·lug
terminals and two handles.

W992

Copper·
clad

18

Single-'
height,
standard
length

Same as W9A;. except copperclad on one side only and has
contact fingers on one side
only.

W993

Copperclad

36

Double·
height,
standard
length

Same as W973 except copperclad on one side only and has
contact fingers on one side
()nly.

W998

Perforated

18

Singleheight,
standard
length

Same as W974 except has 18
plated-through holes and has
contact fingers on one side
only.
'

W999

Perforated

36

Doubleheight,
standard
length

Same as W975 except has 36
plated-through holes and has
contact fingers on one side
only.

Size

Description

COLLAGE MODULE BOARDS
Collage module boards provide a convenient, low-cost method of prodUCing
prototype or limited runs of production modules with special Circuitry that
uses 14- or 16-pin dual-in-line package (DIP) integrated circuits (ICs), with
or without wire wrap sockets and/or solder sockets. Collage module boards
are completely compatible with the standard module mounting blocks summarized elsewhere in this publication and described in detail in the HARDWARE/ACCESSORIES CATALOG published by Digital Equipment Corporation.
These glass epoxy modules have +5 Vdc power and ground bused (printed
circuit etch tracks) to plated-through holes at each Ie location to facilitate
connection of Vee and ground to the appropriate IC pin.

These collage module boards are described in the following table; each of
these collage module boards is described in detail in the HARDWARE/ ACCESSORIES CATALOG.
443

Collage Module Boards
Contact

Description

Part No.

Fingers

Size

W968

144

Quad-height,
extended length

Accommodates up to seventy-two 14or 16-pin DIP les with or without wire
wrap sockets and/or solder sockets.

W969

72

Double-height,
-extended length

Same as W968 except accommodates
361es.

W979

72

Double-height,
standard length

Same as W968 except accommodates
18 les.

MODULE EXTENDER BOARDS

__
Module extender boards are usually used to extend system modules for test
and/or maintenance. Module extender boards permit access to the system
module circuits and components without breaking the electrical connections
between the system module and the backplane or mounting panel wiring.
Extended length module extender boards should be used when the system
comprises extended length system modules. Double~height and quad-height
module extender boards should be used when the system module to be extended is. double or quad-- high; however, two single-height module extender
boards could be used to extend a double-height system module, or two
double-height (or four single-height) module extender boards could be used
to extend a quad-height system module. The following table describes the
module extender boards. The board contact fingers connect directly to the
connector socket pins on a 1:1 basis except as noted in the "Description"
column of the table.

444

Module Extender Boards
Part No.

Contact
Fingers

W900

72

Double·
height,
extended
length

Used in systems comprising extended length
modules to extend a double·height,72~pin
module with +5 Vdc power at contact fin~
gers AA2 and BA2 and with ground at. coritact fingers AC2, BC2, AT1, and BTl, i.e.,
most double·height M:series modules. This
is a multilayer module: layer 2 is the ground
plane an'd layer 3 is the +5 Vdc ,power
plane.

W980

18

Single·
height,
standard
length

Used in systems comprising standard length
modules to extend a single-height, IS-pin
(one side only) module, Le., most A·, K-,
and W·series modules. None of the contact
fingers are interconnected.
.

W982

36

Single·
height,
standard
length

Used in systems comprising standard length
modules to extend a si ngle·height, 36·pin
module, i.e., single·height M-series modules.
None of the contact fingers are interconnected.

W983

72

Double~

Used in systems comprising standard length
modules to extend a double· height, 72-pin
module, i.e., double·height M·series modules. None of the contact fingers are interconnected.

Description

Size
;,

height,
standard
length
W984

72

Double·
height,
extended
length

The same as W983 except the W984 is an
extended length module extender board and
should be used to extend a system module
located beside one, or between two, ex·
tended length modules.

W987

144

Quad·
height,
extended
length

The same as W984 except the W987 is a
quad-height module extender board and
should be used to extend quad· height (144pin) modules.

WIRE WRAPPABLE MODULE BOARDS
Wire wrappable modules provide a convenient, low·cost method of producing
prototype or limited runs of production modules with special circuitry that
utilizes, mainly, dual-in-line package (DIP) integrated c;ircuits (lCs). They
are completely compatible with the standard module mounting blocks sum·
marized elsewhere in this production and described in detail in the HARDWARE/ACCESSORIES CATALOG published by Digital Equipment Corporation.
This section describe'; the new additions to the wire wrap line: the W9500
series and the W9301 and W9302 modules. Further information regarding
these new items can be obtained by contacting logic Products Sales Support.
Accessories & SuppUes Group, DIGITAL, Merrimack, NH 03054.

445

In addition, a brief overview of DIGITAL's tra- ,
ditional wire wrappable modules is provided. These earlier boards are described in detail in the Hardware! Accessories Catalog published by DIGITAL.
W9500 SERIES
WIRE WRAPPABLE MODULES

.'

QESCRIPTION
The W9500 series of wire wrappable modules enable a user to easily configure
special interface logic for the-LSI-ll computer systems and small peripheral
controner (SPC) logic for the PDp·ll computer system. In addition, these
modules are suitable for any system requirements and consists of double,
quad, and hex height sizes. Each module is available with or without premounted Dual-ln·Line packages (DIP) low profile socket_

•

The ten module types included in the W9500 series are listed with a d~cription and preassigned power and ground pin connections in Table 1. Refer to
the General Information section of this handbook for detailed information
relating to module size dimension and edge connector pin coding.
The W9500 Series modules will accept a variety of IC package types and discrete components. The printed circuit on each board connects the appropriate
edge connector pins to the Vcc plane on side 1 of the board and the ground
plane (GND) on side 2. The remaining edge connector pins terminate to a
double row of wire wrap pins for user designated functions. Each of the
modules also Lncludes a 40 pin male· cable connector to allow an interface
cable to be attached to the module logic. The pins of the cable connector
ar~ also terminated to a double row of wire-wrap pins. The quad and hex
height modules are provided with a space where a 40 pin cable connector
(labelled J·2) can be. inserted by the user. When a connector is not required,
additional Ie packages can be installed. Each board contains insulated standoffs. to maintain the required clearance between adjacent modules and prevent
shorting of wire wrap pins.
The wire wrap pins and components are mounted on side 1 of each module.
Rows of predrilled holes accept IC packages with pin spaCings of 0.3 in.
(0.76 cm) 0.4 in. (1.01 cm) and 0.6 in. (1.52 cm). Universal areas on the
W9500 series ITl{)dules are the areas which accept IC packages with standard
pin spacings. These areas have four rows of predrilled /holes spaced at 0.3,
0.4, and 0.6 inches. The W950b hex height module also contains three areas
which can ~ept IC packages with 0.3 and 0.4 inch spacing.

'.

446·

Table 1
Module Type
W9500

W9503
W9501

W9500 Series Modules

Description _

Power & Ground
Connections

Hex height, extended length, single
width module with extractor bracket.
No DIP sockets included. One 40 pin
male cable connector mounted on
board and space for additional 40
pin connector provided.

Vcc-AA2, BA2; CA2
DA2, EA2, FA2

Same as W9500 except with 84 premounted, DIP sockets.
Quad height, extended length, single
width module with flip chip handles.
No DIP sockets included. One 40 pin
male cable connector premounted
on board and space for additional 40
pin connector provided.

Same as W9500

GND-ATI, BTl, CTI
DTI, ETI, FTI, AC2
BC2, CC2, DC2, EC2,
FC2

Vcc-AA2, BA2, CA2,
DA2
GND-ATI, BTI,CTI,
DTI, AC2, BC2, CC2,

DC2

W9504

Same as W9501 except with 54 DIP
sockets premounted.

Same as W9501

W9502

Double height, extended length,
single width module with flip chip
handles. No DIP sockets included.
OnE! 40 pin male cable connector
premounted on board.
Same as W9502 except with 24 premounted DIP sockets.

Vcc-AA2, BA2

W9505

GND-ATI, BTl,'AC2,
BC2
It,

S.me as W9502 "

Quad height, extended length, single
width module with extractor handle.
No DIP sockets included. One 40 pin
male cable connector premounted
on board and space for additional 40
pin connector provided.
'

Vcc~AA2,

W9514

Same as W9511 except with 58 premounted DIP sockets.

Same as W9511

W9512

Double height, extended length,
single widVl module with flip chip
handle. No DIP sockets included.
One 40 pin male connector premounted on board.

Vcc-AA2, BA2

Same as W9512 except with 25 ptemounted DIP sockets.

Same as W9512

W9511

W9515

447

\

BAl, '.CA2,

DA2
GND-ATl; BTI,CTI,
OT1, AC2, BC2, CC2,

DC2

GND-ATl, BTl, AC2,
BC2
-

LSI-11 Compatible Modules
The LSI·l1 compdtihTe modules consist of quad height and double height·
modules. Two LSI·ll compatible modules are avaflable without DIP sockets.
The total IC compliment of 14 or 16 pin DIPS th.at can be installed are listed
on Tabre 2. This table allows one pair of holes between each IC package for
mounting additional decoupling capacitors.
Table 2

LSI·II Compatible Modules (no sockets)
IC Capacity (Total)

Module Type
14 Pin

16 Pin

24 Pin

40 Pin

72
32

61
27

5
5

3
3

W9511
W9512

Two LSI·l1 compatible modules are available with premounted 16 pin DIP
sockets. One pair
holes is provided between each DIP socket for mounting
additional decoupling capaCitors. The total number of sockets mounted on
the board is listed on Table 3.

at

- Table 3

it

Module Type

16 Pin: DIP Sockets

W9514
W9515

58
25

SPC Compatible Modules
The sma" peripheral controller (SPC) compatible modules consist of a hex
height, quad height and double height boards.
Three boards are available without DIP sockets.
The total IC compliment of 14 or 16 pin DIP's is listed on Table· 4. This table
allows one pair of holes for mounting additional decoupling capacitors be·
tween each IC package.
Table 4

SPC Compatible Modules '(no sockets)

IC Capacity (Total)
Module Type
W9500
W9501W9502

14 Pin

16 Pin

24 Pi·n

40 Pin

128
72
40

114
61
38

10
5
5

6
3

I

3

Three boards are available with premounted 16 pin DIP sockets. The total
number of sockets mounted on the modules is listed on Table 5.
One pair of holes is allowed betweeh each DIP socket and can be used to
mount additional decoupling capacitors.

448

Table 5

SPC Compatible Modules (16 pin sockets)

Module Type

16 Pin DIP Sockets

W9503
W9504
W9505

)

449

84
54
24

W9301 HI·DENSITY
WIRE WRAPPABLE MODULE

W9301

DESCRIPTION
The W9301 is a quad height, extended length, double wide, wire wrappable
module suitable for user designed logic interface applications. The module
accepts a variety of dual-in-line (DIP) integrated circuits (IC's) or discrete'
components which can be mounted to the module without the use of solder.
The component or IC leads insert into specially designed socket terminals
which have' a wire wrap pin on the opposite end. The electrical interconnection of the wire wrap pins can be performed manually or by using automated
wire wrapping techniques.
The W9301 board has four rows of 36 gold-plated contacts (18 contacts on
each side of each row)_ Each contact is connected to a wire wrap pin by the
board etch_ A ground plane is etched on side 1 of the module and power
(Vcc) plane is etched on side 2_ Contact pin A2 of each of the four rows directly connects to the power plane, and contact pins C2 and Tl directly connect to the ground plane.
A total of 68 decoupling capacitors are provided premounted between Vcc and
GND at each main IC location. The module occupies 2 slots of a standard
DIGITAL system unit.

450

A 40 pin connector is mounted at the edge of the module to facilitate the attachment of a device cable assembly_

Wire Wrap Terminals
All wire-wrap terminals on side 2 of the module are located on a grid of 0.1
in. (0.254 cm) spacing to facilitate automatic point-to-point wire wrapplj:Jg
equipment. The connections to the pins are made using #30 gauge solid
conductor insulated wire.
Total IC Complement
Up to 79 IC equivalents (14- or 16-pill DIP) can be mounted on the module.
Areas are provided on the board for mounting DIP's with a center spacing of
0.3 in. (0.78 cm) 0.4 in. (1.0 cm) or 0.6 in. (1.5 cm). Table 1 lists the ac·
ceptable IC types and pin spacing.

i

Table 1

W9301 Ie TYPES
Center Spacing (in.)

Total Pins

1~

16 } _ _ _ _ _ _ _ _ _ _ _ 0.3
18
20
22 _ _ _ _ _ _ _ _ _ _ _ _ 0.4

~: 1
40

0.6

r

./

The W9301 module has three pin configuration areas assigned to 16·pin, 24
and 40 pin IC's. The 16 pin area consists of three rows of socket terminals
and will accept a total of 47 IC's of the 8, 14, or 16 pin type and having a
lead spacing of 0.3 in. The 24 pin area will accept a total of 10 IC's with up
to 24 pins per IC, and having a lead spacing of 0.3, 0.4, or 0.6 in. The 40 pin
area will accept a total of 11 IC's with up to 40 leads per IC and having a lead
spacing of 0.6 in. or a total of 22 IC's with up to 16 leads per IC and having
, a lead spacing of 0.3 in.

451

I

W9302 HI-DENSITY
WIRE WRAPPABLE MODULE

W9302

DESCRIPTION
The W9302 is a hex height, extended length, double wide, wire wrappable
module suitable for user designed logic interface applications. The module
accepts a variety of dual-in-line (DIP) integrated circuits (IC's) or discrete
components which can be mounted to the module without the use of solder.
The component or IC leads insert into specially designed socket terminals
which have a wire wrap pin on the opposite end. The electrical interconnection of the wire wrap pins can be performed manually or by using automated
wire wrapping techniques.

The W9302 board has six rows of 36 gold-plated contacts (18 contacts on
each side of each row). Each ,contact is connected to a wire wrap pin by the
board etch. A ground plane is etched on side 1 of the module and power (Vcc)
plane is etched on side 2. Contact pin A2 of each of the six rows directly connects to the power plane, and contact pins C2 and Tl directly connect to the
ground plane.
'
A total of 97 decoupling capacitors are provided premounted between Vcc
and GND at each main IC location. The module occupies two slots in a standard DIGITAL system unit.

452
\

Two 40 pin connectors are mounted at the edge of the module to facilitate
the attachment of device cable assemblies.
Wire Wrap Terminals
All wire wrap terminals on side 2 of the module are located on a grid of 0.1 in.
(0.254 cm) spacing to facilitate automatic point-to·point wire wrapping equipment. The connections, to the pins are made using #30 gauge solid conductor insulated wire.
Total IC Complement
Up to 114 IC equivalents (14· or 16-pin DIP's) can be mounted on the module.
Areas are provided on the board for mounting DIP's with a center spacing of
0.3 in. (0.78 cm) 0.4 in. (1.0 cm) or 0.6 in. (1.5 cm). Table 1 lists the ac·
ceptable IC types and pin spacing.

Table 1

W9302 IC TYPES
Center Spacing (in_>

Total Pins

1: }
16

______________________

18
20
22 _____________

~0.3

~O.4

28 } _ _ _ _ _ _ _ _ _ _~O.6
24
40

The W9302 module has three pin configuration areas assigned to 16-pin, 24pin and 40-pin IC's. The 16 pin area consists of three rows of socket terminals
and will accept a total of 65 IC's of the 8, 14, or 16 pin type and having a
lead spacing of 0.3 in. The 24 pin area will accept a total of 15 IC's' with up
to 24 pins per IC, and having a lead spacing of 0.3, 0.4, or 0.6 in_ The 40.pin
area will accept a total of 17 IC's with up to 40 leads per IC and having a lead
spacing of 0.6 in. or a total of 34 IC's with up to 16 leads per IC t!'~, having
.
:
\
a lead spacing of 0.3 in.

453

Wire Wrappable Modules

Part No.

Contact
Fingers

W940

144

Quadheight,
extended
length

Accommodates up to fifty 14- or 16-pin
DIP ICs with or without sockets. (Sockets
not included.)

W941

72

Doubleheight,
extended
length

Same as W940 except accommodates up
to twenty-five 14- or 16-pin DIP ICs with
or without sockets. (Sockets not included.)

W942

144

Quadheight,
extended
length

Same as W940 except equipped with 50
low-profile, I6-pin DIP IC sockets.

W943

72

Doubleheight,
extended
length

Same as W941 except equipped with 25
low-profile, 16-pin DIP IC sockets.

W950

144

Quad~

Accommodates up to thirty. 14- or 16-pin
DIP ICs and up to eight 24-pin DIP ICs
with or without sockets. (Sockets not
included.)

I

height,
extended
length

~

Description

Size

W951

72

Doubleheight,
extended
length

Same as W950 e"'Ccept accommodates up
to fifteen 14- or I6-pin DIP ICs and up to
four 24-pin DIP ICs with or without sockets. (Sockets not included.) The four
24-pin locations can also accommodate
four 14- or 16-pin ICs instead" of the
24-pin ICs.

W952

144

Quadheight, extended
, length

Same as W950 except equipped with 30
low-profile, 16-pin DIP IC sockets and
.
eight 24·pin DIP IC sockets.

W953

72

Doubleheight, .
extended
length

Same as W951 except equipped with 15
low-profile, H)-pin DIP IC sockets and
four 24-pin DIP IC sockets.

WIRE WRAPPING TOOLS AND ACCESSORIES
Wire wrapping provides positive, uniform electrical connections faster and
more economically than solder connections. Digital Equipment Corporation
has a complete line of tools and accessories for wire wrapping ~II of the
wire wrappable module connector blOCKS and all of the wire wrappable module boards summarized elsewhere in this publication and described in detail
in the HA.RDWARE/ACCESSORIES CATALOG published by Digital Equipment
Corporation.
454

Pistol-Grip Wire Wrapping Tool Klt-H810(24), H810-A, H810-B
The HSIO(24) Pistol-Grip Wire Wrapping Tool Kit provides a pistol-grip
mechanical wire wrapping tool. and a sleeve and bit of the proper size to
wrap 24 AWG wire wrap wire. ;
The HSIO-A is the' same as the HSI0(24) except the sleeve and' bit are the
proper size for wrapping 30 AWG wire wrap wire.
The HSIO-B is a combination of HSIO(24) and HSIO-A. HSIO-B provides a
pistol-grip mechanical wire wrapping tool and the bits and sleeves of the t
proper sizes for wrapping 24 AWG or 30 AWG wire wrap wire.
Battery-Powered Wire Wrap Gun-H810-C, H810-D
The HSIO-C, HSIO-D, and HSIO-E battery-powered wire' wrap guns are
equipped with rechargeable, nickel-cadmium batteries. The), do not require
ac connection while in use. Their ease of operation reduces user-fatigue and
provides uniform wire wrap connections.
The HSIO-e battery-powered wire wrap gun is supplied with a bit and sleeve
for wrapping 24 AWG wire wrap wire.
The HSIO-D is supplied with a bit and sleeve for wrapping 30 AWG wire
wrap wire.
HSl3 bits and HSl4 sleeves can be used with .any of these battery-powered
wire wrap guns_
Hand Wire Wrapping Tool-H811(24), H811-A
The HSll(24) and HSl1-A hand wire wrapping tools are especially useful for
service and repair applications. They can also be used for producing limited
numbers of prototype modules.
HSll(24) is designed for 24 AWG wire wrap wire, and the HSll-A is designed for 30 AytG wire wrap wire.
Hand Wire Unwrapping Tool-H812(24); H812-A
The HS12(24) and HSI2-A hand unwr~pping tools are ideal for unwrapping
wire strapped terminals.
The HS12(24) is designed for unwrapping 24 AWG wire, and the H812-A is
designed for unwrapping 30 AWG wire.
Bit for Battery-Powered Wire Wrap Gun-H813(24), H813-A
The HSI3(24) and HS13-A bits are replacement bits for battery-powered
wire-:wrap guns HSIO-C, HSIO-D.
The HS13(24) is designed for 24 AWG wire, and the HSI3-A is designed
for 30 AWG wire.
Sleeve"for Battery-Powered Wire Wrap Gun-H814(24), H814-A
The HSI4(24) and HS14-A sleeves are replacement sleeves for batterypowered wire wrap guns HSJ.D-C, HSIO·D.
The HS14(24) is designed for 24 AWG wire ,and the H814-A is designed for
30 AWG wire.

--

455

'\

INTEGRATED CIRCUIT (IC) SOCKETS
IC Sockets-954, 961, 962
These integrated circuit (IC) sockets provide low-cost, reliable production
packaging of 14 or 16-pin, 24-pin, and 40-pin dual-in-line pacKage (DIP) integrated circuits (I:s). These low-profile IC sockets are especially useful for
limited-production runs of special, user-designed circuitry using the blank or
wire wrappable module boards (described in this sectien), which are aVaflable without factory-installed IC socke~.
The 954 accepts 14- or 16-pin, ICs; 10 sockets/package.
The 961 accepts 24-pin ICs; 5 sockets/package.
The 962 accepts 40-pin ICs; 5 sockets/package.
MODULE HANDLES, MODULE HANDLE EXTENDERS,
AND MODULE HOLDERS
Module Handle-937
The 937 '(90-08337-08) is a package containing 25 blank, gray module
handles and t~e eyelets to attacl} them to modules. These blank handles
are generally user-attached to prototype or limited-production run modules
that utilize blank copper-clad or wire wrappable modules. The blank handles
provide a convenient method of identifying the prototype or limited-production run modules because the user can put his own identification on the
handle. The handles are compatible with the handles of all Digital Equipment
Corporation standard A-, K-, M-, and W-series modules. They have two 0;128in. (0.325-cm) diameter mounting holes spaced 2.00 in. (5.08 cm)' centerto-center.

Module Handle Extender-H850
The H850 Module Handle Extender mounts over the handle of a single-height,
single-I~ngth module and physically extends the length to make a singlelength module congruous with extended length modules. The H850, in addition to making removal and insertion of single-length modules easjer when
the system predominantly utilizes extended length modules, adds to the appearance of the system by making the modules the same length.
The H850 is manufactured from durable, U.L. Standard No; 94 recognized
material and is sized to fit over Digital Equipment Corporation's standard
module-handle. It is sold in lots of ten.

Module Holder Clips--H852, H853
The H852 and H853 Module Holders are used to maintain rigidity of the
modules in a system. Each module holder fits oveT the top (handle end) -of
modules of the same length in adjacent slots of a system unit. The H852,
a ribbed type holder, fits between handles of modules in the same connector
block; the H853, a nonribbed type holder, fits between the handles of modules in adjacent (end-to-end) connector blocks. For example, on quad-high
modules, an H852 fits between handles 1 and 2, an H853 fits between
handles 2 and 3, and an H852 fits between handles 3 and 4.

The H852 and H853 are manufactured from durable plastiC material that is
nonconductive. They are sold in Jots of 25 each.

456

Hold-Down Bracket 12-10711-02
The 12-10711-02 module hold-down brcy:ket serves as a mechanical combination handle and hold-down bracket fbr Hex-size modules when used with
the appropriate cards guides such as an H0341. This bracket can also be
used as a hold-down bracket for LSI-ll compatible modules (quad-size) but
must be modified as shown in the accompanying drawing. Eyelets for attachment to the module are included.
.

LSI-II HOLDOWN 12-10711-02
1. CUT BRACKET AT POINTS DESIGNATED ON DRAWING BELOW.
2. DISCARD CENTER SECTION liB".
3. MOUNT SECTIONS "A" AND "C" ON BOARD AS DESIRED.

CUT AT THESE
POINTS

BUS STRIPS

Bus Strips-932, 933, 939
•Bus strips 932, 933, and 939 provide a convenient method of interconnect-ing all wire wrap pins in a system that are assigned identical control Signals,
power, or ground. These bus strips are flat, narrow cond-uctors with holes
that correspond to the connector block pin siz~ and spacing. When a bus
strip is placed over the pins and soldered to each, it will interconnect all of
the pins with the same pin number for as many module slots as desired.
After the modules have been selected and the slots of the mounting panel
have been assigned to the modules, identical control signal, power, and
ground pins can be bused with the bus strips.
Bus strip 932 can be used to bus systems using H800 Module Connector
Blocks. Bus strip 933 can be used to bus systems using H803, H8030, and
H863 Module Connector Blocks. Bus strip 939 can be used to bus systems
using H808 Module Connector Blocks. Modul,e connector blocks are summarized elsewhere in this publication and are described in detail in the
HARDWARE/ACCESSORIES CATALOG published by Digital Equipment Corporation.
Length:

932 - 13.5 in. (39.4 cm)
933 - 21.5 in. (54.6 cm)
939 ---.,. 21.5 in. (54.6 cm)
457

PATCH CORDS AND ACCESSORIES
Grip-Cllp Connectors for Slip-on Patch Cords-H820, H821
.
The H820 and H821 grip,clip connectors are identical to the connectors used
on each end of 913 and 915 patch cords, respectively. These grip clips
permit the fabrication of patch cord~ of any length.
H820 grip,clip connectors accept 24 to 20 AWG wire; they slip on wire wrap
terminals that are sized for 24 AWG wire wrap wire, 0.031 by 0.062 in.
(0.079 by 0.158 cm). H821 grip·clip connectors accept 30 to 24 AWG wire;
they slip on wire wrap terminals that are sized for 30 AWG wire wrap wire,
0.025 in. (0.064 cm) square.
H820 and H821 grip·clip connectors are shipped in quantities of 1000 of
one size.
Patch Cords-9I3, 915
The 913 and 915 patch cords provide slip·on connections at the wire wrap
pins of FlIp·CHIP modules and module connector blocks. They are ideal for
breadboarding prototype modules and making temporary or semipermanent
jumpers at a system backplane. They are available in 11 color·coded lengths
from 2 to 64 inches (5.04 to 162.56 cm).
Patch cord 913 is 24 AWG strandeq wire with IPVC insulation, and is equipped
on each end with an H820 grip-clip connector;' H820 connectors fit on wire
wrap pins that are sized for 24 AWG wire wrap wire, 0.031 by 0.062 in.
(0.079 by 0.158 cm).
Patch cord 915 is 26 AWG stranded (7/34) with ,PVC insulation, and is
equipped on each end with an H821 grip-clip connector; H821 connectors fit
on wire wrap pins that are sized for 30 AWG wire wrap wire, 0.025 in. (0.064
cm) square.
Patch cords 913 and 915 are available in quantities af 100 of the same
length and same gauge, and in qu~ntities of 100 of assorted lengths and
the same gauge. The following chart lists the part ·number, length, and color
code for 913 and 915 patch cords.
Part Number
26AWG

24AWG

915-2
915-3
915.4
915-6
915-8
915-12
915·16
915-24
915-32
915-48
915-64
915-AF

913-2
913-3
913-4
913-6
913-8 913-12
913-16
913-24
913-32
913-48
913-64913-AF

Length in Inches
(Centimeters)

Color

(5:08)
(7.62)
(10.16)
(15.24)
(20.32)
(30.48)
(40.64)
(60.96)
(81.28)
(121.92)
64 (162.56)
Assorted *

BRN
BRN/WHT
RED
RED/WHT
ORN
ORN/WHT
VEL
YEL/WHT
GRN
GRN/WHT
BLU
Assorted

2
3
4
6
8
12
16
24
32
48

"-

* 913-AF and 915-AF comprise the following assorted patch cords: 30BRNI
WHT (-3); 25 RED/WHT (-6); 25 ORN (-8); 10 VEL/WHT (-24); 5 GRN
(-32); and 5 BLU (-64).
.

\

458

I

When ordering, please specify part number 913 or 915 and the appropriate
dash number.

Power Patch Cord-914-7, 914-19
The 914 power patch cords provide interconnections between power supplies
and mounting panels that are equipped with Faston @ terminals, series
250. The 914 power patch cord is stranded wire with IPVC insulation and
is equipped on each end-with Faston receptacles, series 250. Power patch
cord 914 is available in lwo lengths-7 inches and 19 inches (18 cm and
48 cm)-and is available in packages of ten of the same length. The 914-7
is a package of ten 7·inch (l8-cm) patch cords. The 914-19 is a package
of ten 19-inch (48-cm) patch cords.

@

Faston is a trademark of AMP, Inc.

Daisy Chain-917-2.5
The 917 daisy chain is a continuous length of stranded insulated wire on a
reel with 250 gold-plated and insulated terminals crimped at 2.5-in. (6.4-cm)
intervals. A prototype system is easily and quickly hand patched when the 917
daisy chain is used.
.
The terrilinals are designed to fit on module connector blocks that have wire
wrap pins sized for wrapping with 30 AWG wire [0.025/0.026 in. (0.0641
0.066 cm) square] e.g., module connector blocks HS03, HS030, H807, and
H863, summarized elsewhere in ,this publication and described in detail in
the HARDWAREI ACCESSORIES CATALOG published by Digital Equipment Corporation.
The dependable 911 daisy chain push-on terminals are easily removed from
the connector block wire wrap terminals; this provides an ideal wiring technique in systems where unwiring and rewiring for changing system require·
ments are essential. If an additional lead is ever required on a wire wrap
terminal, a 915 patch cord can be used; a 915 patch cord can be placed on
the terminal after the wire wrap connection and before the 917 termination.
The 917-2.5 daisy chain has 250 terminals at 2.5-in. (6.4-cm) intervals.

459

I

/

-

-

460

CABLES
COMPLETE ASSEMBLIES AND PARTS

461

Digital offers a complete and comprehensive line of pre-assembled cable assemblies compatible with most computer products offered_
In addition, Digital also offers a complete line of cable accessories and parts
for users who wish to construct their own cables_ \.
This CABLE section is divided into two subsectiQns:

1. Cables (assembled)
2. Cable Accessories (raw cabling, connectors)
The pre-assembled cables subsection represents a listing of the most popular
cable types and the most popular lengths available.
The other subsection describes cable components such a~ terminators, connectcrs, raw cable, and related cable- accessories.
Many of the cables supplied by DIGITAL are also available in non-standard
custom lengths. For information on price and delivery either call your nearest
sales office or Logic Products Sales Support, Accessories ~ Supplies Group,
DIGITAL, MKl-2/E13, Merrimack, NH 03054.

CABLE WARRANTY NOTE
All standard and custom length cables are guaranteed against defects in material and workmanship for a period of 90 days from date of
shipment.
Digital Equipment Corporation neither expresses or implies that custom length cables will
\ function satisfactorily if the electrical performance specification (e.g., drive length) for the application is exceeded.
\

)

- t
462

DESCRIPTION
(Principal Use)

\ CABLE TYPE
BCOIR-25
BCOIV-25
BC04Z-06
BC04Z-10
BC04Z-25
BC05C-25
BC05C-50
BC05D-I0
BC05D-25
BC05H-06
BC05J-06
BC05M-2C
BC05M-04
BC06R-06
'BC06R-H)
BC06R-25
BC06R-50
BC06S-10
BC06S-25
BC06S-40
SC07A-I0
BC07A-15
BC07A-25
BC07B-I0
BC07B-25
BC07D-I0
BC07f):t5
BC070-25
BC08A-03
BCOSA-05
BC08A-IO
BCOSJ-06
BCOSJ-I0
BCOSM-OM
'BCOSR-Ol
BCOBR-03
BC08R-06
BeOBR-I0
BCOBR-20
BCOBR-25
BCOSR-50
BCllA-02
BCllA-05
BeIIA-IO
Be11A-15
- BCIIA-25
BCIIA-8F
BCI1K-25
'BCllS-25

MULTI-USE

M970 TO RS232
12-5886 TO 12-5885
H856 TO OPEN
H856 TO OPEN
H856 TO OPEN
H856 TO RS232-M
H856 TO RS232-M
RS232-M TO RS232-F
RS232-M TO RS232-F
ACINPUT BOX H400-A ~
AC INPUT BOX H400-B
12-9340 TO H856
12-9340 TO HS56
H855 TO HS55
HS55 TO HS55
HS55 TO HS55
H855 TO H855
12-11591 TO,12-11591
12-11591 TO 12-11591
12-11591 TO 12-11591
H856 TO OPEN
HS56 TO OPEN
HS56 TO OPEN
HS56 TO QPEN
HS56 TO OPEN
HS56 TO OPEN
HS56 TO OPEN
H856 TO OPEN
M904 TO M904
M904 TO M904
M904TOM904
HS56TO M953
HB56 TO M953
HS59 TO HS59
HS56 TO HS56

MULTI-USE
'MULTI-USE
MULTI-USE, UNIBUS

HS56 TO HS56
HS56 TO HS56
M929 TO M919

MULTI-USE, UNIBUS
ORll-C
MULTI-USE

M9~9 TO M919
HS56 TO OPEN
H856 TO HS56

M970 PLU S BC05C-Z5
EIA DATA~CABLE
MULTI-USE
MULTI-USE
MULTI-USE
DLII CABLE
DL11 CABLE
MULTI-USE'
MULTI-USE
60 HZ LINE CORD
50 HZ LINE CORD
TTY CABLE
' TTY CABLE
MASs--euS (FLAT)
MASS BUS (FLAT)
MASS BUS (FLAT)
MASS BUS (F~T)
MASS BUS - P1
-. 52
...,

-.

.

-0 S1

-0 T2
-.
....,
V2

+5V

A2
The M910 module contains eighteen 68-ohm resistors tied to a common +5
volt bus .
. APPLICATIONS
This module is intended to be used with the M909 to form half of the biasing
circuit used in the driving network of the M622.

478

CABLE CLAMPS
Cable clamps provide strain relief where a cable enters a cable connector.
Cable clamps are availablJ! for both flat and round cables.

Cable Clamp-12-09764

.

The 12-09764 cable clamp can be used with flat cable up to 4.562 in. (11.587
cm) wide. Two 0.128-in. (0.325-cm) diameter mounting holes are spaced
4.750 in. (12.065 cm) center-to-center to align with holes on the cable
connector; nylon mounting hardware (No.4 screw and nut) i~ recommended.

Cable Clamp-12-09925

The 12~09925 cable clamp can be used with module c,onnector block H807
and a round cable. An H807 connector block and a round cable provide a
convenient method of terminating a single-height module at a remote location. The 12-09925 cable clamp protects the solder connections of the cable
and the connector pins; it also prevents excessive strain on the cable when
the module is inserted into or removed from the module connector. The
12-09925 will accommodate cables from 0.290 in. (0.737 cm) to 0.390 in.
(0.813 cm) in diameter.
The body of the .12-09925 is equipped with two 6-32 threaded inserts so
that the cover of the 12-09925 can be secured to the body.
.

Cable Clamp-940
The 940 cable clamp can be used with flat cable up to 1.75 in. (4.45 cm)
wide. The cable slot is 0.080 in. (0.203 cm) deep. Two 0.128-in. (0.325-cm)
diameter mounting holes are spaced 2.000 in. (5.080 cm) center-to-center to
align with holes on the cable connector; nylon mounting hardware (No. 4
screw and nut) is recommended.

Cable Clamp-941

.

The 941 cable clamp can be used with round cable that is 0.281 to 0.438 in.
(0.714 to 1.113 cm) in diameter. The 941 cable clamp can also be used
where cables require strain relief at the entry point to panels and cabinets.
Two 0.136-in. (0.345-cm) diameter mounting holes are spaced 2.000 in.
(5.080 cm) center-to-center to align with holes on the cable connector, panel,
or cabinet; nylon mounting hardware (No.4 screw and nut) is recommended.

,

479

(

480

I

'-..

ABOUT DIGITAL
HISTORY
PRODUCTS

481

In approximately 21 years, DIGITAL EQUIPMEN"Tt CORPORATION has grown
from three employees and one floor of production space in a converted
woolen mill, to a major international corporation. DIGITAL now employs more
than 38,000. Our products are manufactured worldwide, and are sold and
serviced from customer support centers in the United States, Canada, Japan,
Australia and several European cQ.untries.
We produce a wide variety of computer and control products ranging from
logic modules to large time sharing computer systems. In addition to those
logic modules and associated equipment detailed in. this handbook, DIGITAL
also manufactures 12·, 16·, 18· and 36-bit computers, peripheral devices,
special systems, accessories, programmable controllers and a wide variety
of software.
DIGITAL first began manufacturing computer-related equipment in 1957
when we introduced a line of solid state logic modules. These were initialty
used to test and build other manufacturers' electronic equipment. The logic
module product lines have been continually broadened, and DIGITAL now
ranks as the world's largest manufacturing supplier of digital logic modules,
producing more than three million per year.
Our first computer, the PDP-1 was introduced over a decade ago, selling for
$120,000 while competitive machines were priced over $1 million. Ever since
the PDP-I, DIGITAL has specialized in on-line, real-time computers.
The PDP-5, introduced in 1963, was the first truly. small computer. The
PDP-8 series, the PDP-5 successor announced in 1965, is one of the most
popular and successful families of computers ever produced.
The PDP-l1 sixteen-bit computer also ranks as the industry leader of
medium-sized systems.
.
DIGITAL ,is a leading force in small computers, but it also has been a pacesetter in other parts of the industry. For example, one ofe the first time
sharing systems ever built incorporated a PDP-I. DIGITAL introduced the
first large-scale, commercially available tinfe sharing system in 1965-the
PDP-6. Its successor, the DECsystem-lO, can do more at a price well under
$1 million than competitive systems costing several times as much.
In industry, DIGITAL computers provide ,engineers with a powerful control
and testing tool. They control blast furnaces and open hearths, monitor slab
mills and finishing mills, and control and monitor a variety of machine tools,
transfer and material handling equipment. DIGITAL computers can be found
482

controlling a busy section of the' New Jersey Turnpike and providing typesetting and copy production for many newspapers and publishing firms_
In science, our computers have cut the researchers experiment time with
'direct, on-line data reduction. DIGITAL computers control and monitor powerful nuclear reactors, control X-ray diffractometers, analyze nuclear spectroscopy data, and assisted in the analysis of lunar rock samples. TheY" are
used extensively in environmental research and pollution control.
In virtually all DIGiTAL computer installations, DIGITAL solid state logic is
used for interfacing or control application.

GENERAL INFORMATION
FINANCIAL RESULTS (Fiscal Year)
Total Sales (in millions)
1977
$1,058.6

Net Income (in millions)
1977
$108.5

DIGITAL EQUIPMENT CORPORATION

DIGITAL COMPUTER SPECIAL
SYSTEMS FACILITIES
JAPAN
Tokyo
NEW HAMPSHIRE
Nashua
SWEDEN
Solna (Stockholm)
UNITED KINGDOM
Reading

AUSTRALIA
Sydney- "
CALIFORNIA
Santa Ana
. CANADA
Kanata (Ottawa)
FRANCE
Annecy
GERMANY
Munich

483

DIGITAL MANUFACTURING FACILITIES
Springfield_
We&.tboro
Westfield
Westminster
NEW HAMPSHIRE
Derry
Nashua
Salem
NEW MEXICO
Albuquerque
PUERTO .RICO
AguadilJa
San German
SCOTLAND
Ayr
TAIWAN
VERMONT
South Burlington

ARIZONA
Phoenix
CALIFORNIA
Mountain View
CANADA
Kanata
COLORADO
-Colorado Springs '
HONG KONG
IRELAND
Galway
MAINE
Augusta
MASSACHUSEITS .
Acton
Marlborough
Maynard
Natick
DIGITAL TRAINING CENTERS
AUSTRALIA

CORPORATE HEADQUARTERS
Digital Equipment Corporation
Maynard, Massachusetts 01754
Telephone:
Metropolitan Boston: 646-8600
Elsewhere: (617) 897-5111
TWX: 710·347-0212
Cable: Digital Mayn.
Telex: 94-8457

Sydn~y

CAl!IFORNIA
Sunnyvale
CANADA
Kanata (Ottawa)
DISTRICT OF COLUMBIA
Washington (Lanham, Md.)
FRANCE
Ro'ngis (Paris)
GERMANY
Munich
ILLINOIS .
ROiling Meadows (Chicago)
ITALY
Milan
JAPAN
Tokyo
MASSACH USETTS
Marlborough
Maynard
NETHERLANDS
Utrecht
NEW YORK
New York City
SPAIN
.
·Madrid
SWEDEN
Solna
SWITZERLAND
Zurich
UNITED KINGDOM
Reading

EUROPEAN HEADQUARTERS
Digital Equipment Corporation
International (Europe)
12, avenue des Morgines
Case Postale 510
1213 Petit-Lancy 1
Geneva, Switzerland
Teler>hone: (022) 93 33 11
CANADIAN HEADQUARTERS
Digital Equipment of Canada, Ltd.
100 Herzberg Road
Kanata, OntariO,. Canada .
Telephone: (613) 592-5111
TWX: 610·562-8732

TOTAL EMPLOYEES .......... 38,000

484

GENERAL DEsCRIPTION OF DIGITAL PRODUCTS
(Excluding those discussed in this Handbook)
'.
COMPUTERS
PDP·8E, PDP-8F, PDP-8M, PDP-81 A, the lower cost successors to the PDP-S/ I
and PDP-S/L. They are the outgrowth of the largest concentration of mini_ computer engineering, programming and user expertise in the world. Among
the PDP-S/E features are: a unique internal bus system called OMNIBUSTM,
which allows the user to plug memory and processor options into any available slot location; the availability of 256 words of read only or read/write
memory; a 1.2 microsecond memory cycle time; the use of TTL integrated
circuitry with medium scale integration; expansion to 32,768 12-bit words;
low cost mass storage expansion with DECdisk, DECtape, or the DECcassette.
PDP-11 A family of expandable general purpose computers with 4,096 I6-bit
words of standard core memory. Memory cycJe time is 1.2 microseconds.
Machine uses integrated circuitry and has some medium-scale integration in
central processor. Models are P_DP-ll/03, 04, 34, 45, 55, 60, and 70.

VAX-ll/780 A compatible upward extension of the PDP-ll family, this computer features a 32-bit word lengt~, a large virtual-memory operating system,
and a very extensive instruction set especially suited for efticient high-level
language programs.
PDP-12 Laboratory computer system capable of executing PDP-8 and L1NC-S
programs. It has basic 4,096·word core memory. Each word is 12 bits in
length. Basic laboratory system includes interactive graphics capability, magnetic tape storage, A/D converter, and prewired, real·time clock.
PDP-1S A medium-scale series with an IS-bit word lehgth, available in 5 com·
plete software operating systems and 8 applications packages.
DECSYSTEM-20 Family of outstandingly low-cost medium-scale mainframes
with 36-bit word length, fully software-compatible with each other and with
the rest of the Digital mainframe line. Models are 2020, 2040, 2050, and
2060.
DECSYSTEM-10 General purpose 36-bit word large computer that will handle
up to 63 time'sharing users simultaneously with batch and real-time jobs at
the same time.
COMPUTER-BASED SYSTEMS
,
Industrial Products. Digital's industrial computer systems are based on
PDP-8 and PDP-ll processors and encompass a range of power and capability. Products designed specifically for the industrial user include programmable controllers, environmental computer enclosures industrial control subsystems and power demand control equipment.
Business Systems. Digital's business-oriented computer systems, called DEC
DATASYSTEMS, are based on the PDP-S and PDP-ll minicomputer families
and configured with appropriate terminals and storage devices. They function ~s complete stand-alone data-handling systems or as intelligent terminals
in a large network. A new addition is the VT78 DECstation, the company's
lowest-priced full computer system.
Education Products. These systems include a variety of applications software
and vary from small stand-alone single-user systems to large, multi-user
4S5

tirnt'!sharing configurations capable of handling computer-aided instruction
as well as administrative data processing.
\
Data Communications. The data communications capability of the computer
is enhanced by the special products-data handlers, front-end preprocessors,
data loggers, modems-as well as the software and services of Digital's
DECcomm group.
Laboratory Data Products include the DECgraphic·U series of interactive,
starld-alone computer·based graphics systems, DEClab-U' laboratory data
handling systems, the Gamma·U, designed for use in nuclear medicine,
MUMPS-ll data base management system for the hospital environment,
PHA-ll pulse height analysis systems designed specifically for nuclear and
x·ray spectroscopy in low·energy physics and radiochemistry applications, and
the POL programmable data logger, all. easy·to·use laboratory data acquisition
system.
Computerized Typesetting. Computer·based systems for setting type, includ·
ing justification and hyphenation, text storage and editing, classified ad handling and related business applications, are available in a range of size and
capability-Typeset-8, Typeset-11, Typeset-10-dependi ng on the Digital
computer system.
Word Processing. Digital's family of video-display word processing products
includes both stand·alone and multi-termirial, shared-logic systems. They can
interact with PDP-ll·based systems also.
Original Equipment Manufacturing. Digital serves the OEM with a complete
range of products and services designed to enhance the capability and profit·
ability of both the manufacturer and the end user.
Components. The same quality comppnents found in Digital products are
available to the high-volume user, in quantity, without the normal Digital
supporting services.
Peripherals. Digital qffers a wide range of peripheral equipment and acces- .
sory devices for the computer user. Among them: analog/digital converters,
display and plotting equipment, drums and disks, magnetic tape equipment,
card, equipment, lineprinters.
Graphic Systems. Digital's GT series interactive graphic terminal systems
function as complete stand-alone graphics systems or as part of a larger
system configuration.
Special Systems. Digital maintains a special systems group with the capability to custom·build hardware and software systems to fulfill specific applications.
Software. A comprehensive selection of software complements Digital hard·
ware. Assemblers, debugging routines, editors, monitors, floating point pack·
ages, mathematical routines, and diagnostic programs are availabJe, as are
conversational, interpretive languages developed for use in specific application areas.
.
Supplies and Accessories. Digital also prqvides power supplies, cabinetry,
mounting hardware, tape, tape reels, storage racks, teleprinter ribbOn and
paper.

j

486

~

WARRANTY
A.

All Products (except Software) listed in this Handbook are warranted as
stated below for a period of ninety (90) days from date of initial delivery,
except that the warranty period for W, M, K, and A Series modules is one
(1) year.

B. All Products (except Software) are warranted against defects in m~terial
and workmanship under normal and proper use and in their original unmodified condition for the period set forth in Clause A- above. If found
defective by DIGITAL within the terms of this warranty, DIGITAL's sole
obligation shall be to repair or replace (at its option) the defective Product." If DIGITAL determines that the Product is nc;)'f defective within the
terms of this warranty, Customer shall pay all costs of handling and
return transportation. All replaced Products become the property of
DIGITAL. As a condition of this warranty, Customer must obtain a DIGITAL
Return Authorization Number, and must return all Products, transportation prepaid and insured, to:
"
Digital Equipment Corporation
Logic Products Services
Repair Section
Cotton Road
Nashua, NH 03"061
C. Transportation charges for the return to Customer shall be paid by
DIGITAL within the contiguous United States only. These warranties outside the contiguous United States are limited to repair or replacement
omy and exclude all costs of shipping, Customs clearance, and other related charges.
D. Premium methods of shipment are available at customer expense and
will be used only when specifically requested: DIGITAL maintains a factory repair service for customer convenience and will repair.equipment
beyond the warranty at then current prices as long as repair components
are available.
.
E.

EXCEPT FOR THE EXPRESS WARRANTIES STATED ABOVE, DlGlfAL DISCLAIMS ALL WARRANTIES ON PRODUCTS, INCLUDING ALL IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS; and the stated express warranties are in lieu of all obligations or liabilities on the part of
DIGITAL for damages, including but not limited to special, indirect, or
consequential damages arising out of or in connection with the use or
performance of the Products.

487

!

-'"
HOW-TO-ORDER
All products describe~ in this Handbook can be ordered by telephone, TELEX,
TWX, or mailed to your local DIGITAL sales office. When placing an order,
please provide specific information regarding part number full description,
quantity, ship-to and bill-to addresses. Please state on your purchase order
that "DIGITAL's Standard Terms & Conditions govern this order.'" Prices
are listed in the Price Supplement booklet, and do not include applicable
state and local taxes or shipping charges.
Also, by using the DIGITAL Direct Sales Catalog, you can order direct from
the factory" and realize significant savings on many items in this Handbook.
Order your copy of the Direct Sales Catalog by filling in the postcard attached
in this Handbook, or call toll·free 8:30 AM to 5:00 PM Eastern time 800-2581710. From New Hampshire locations or places outside the continental U.S.,
603-884-6660.
MINIMUM ORDER SIZE
A minimum order size of $35 is required. Customers will be billed the full
$35 for orders not meeting the minimum size.
CANCELLATION POLICY
All orders placed with Logic Products and scheduled for shipment, if cancelled
by customer in whole or: in part, are subject to a cancellation charge if cancelled before or after the scheduled shipping date. The cancellation charge
is $25 for any cancellation within sixty (60) days of the scheduled delivery
date. Custom variations are considered non-cancellable after the order is
,acknowledged.

488

ALPtiANUMERICAL PRODUCT INDEX
HOW TO ORDER,
WARRANTEE

489

TYPE

TITLE

861-B

Power Controller (180-270 Vac,
Single-Phase) ... ................... ..... .............
Power Controller (90·135 Vac,
Single·Phase) ....................... ................
Power Controller (90-135 Vac,
Three-Phase) .........................................
Power Controller (180-270 Vac,
Three·Phase) ..........................................
Patch Cords, 24 AWG (100/pkg) ...............

861-C
861-0
861-E
913- (all dash
items)
914-7
914-19
915- (all dash
items) :
91'7-2.5
932
933
937
939
940
941
954
956
957
961
962
12-09154
12·09224
12-09340·00
12·09340-01
12-09350- (all
dash items)
12-09351· (all
dash items)
12-09703
12-09764
12·09925
12-10331-0
12-10711-02
12-10945
12·11386
54·11808
70-08360
70·08612-4A
70-11212·25
70·11212·50
70·11212-AO

Page

7-lnch Power Patch Cord (10/pkg) ............
19-1nch Power Patch Cord (lO/pkg) ..........
Patch Cord~, 26 AWG (lOO/pkg) ................

428
428
428
428
458
45~

459
458

Daisy Chain, Clip every 2.5" .... ................
Bus Strip (5/pkg) .. ...................... ..............
Bus Strip ...................................................
Blank Module Handle (25/pkg) ...... ...........
Bus Strip (6/pkg) ........ ............................
Cable Clamp (25/pkg) .... ..........................
Cable Clamp (25/pkg) ...............................
Solder IC Sockets (lO/pkg) .......... ........ ......
OEC8640 UNIBUS Receiver IC
(Quad 2-lnput NOR Gate) ........ ...... .......
DEC8881-l UNIBUS Driver IC
(Quad 2-lnput NAND Gate) ....................
24-Pin IC Sockets (5/pkg) ..........................
40-Pin IC Sockets (5/pkg) ..........................
Drawer Mounting Slides (pair) ..................
Latch ..........................................................
8-Pin Cable Connector (Female)
Housing (2/pkg) ............................
8-Pin Cable Connector (Male)
Housing (2/pkg) ...................... .............
Cable Connector (Female) Housing .... pkg.

459
457
457
455
457
477
477
455

Cable Connector (Male) Housing ...... pkg.

471

Drawer Mounting Slides, Tilt (pair) ............
Cable Clamp (5/pkg) ..................................
Cable Clamp (4/pkg) ................................. ~5" Blower for H909·C ................................
Module Hold-Down Bracket....... .................
Chassis Slides (Pair) ..................................
Thick Latch ...................... :.........................
Console Panel............................................
Cable, used with OU1 ..............................
Console Signal/Power Cable ......................
Cable, used with LPll ..............................
Cable, used with LP11 ...............................,
Cable, used with LPll .............................. \

400
477
477
416
457
414
410
161
463
161
463
463
463

490

106
106
455
455
400
410
471
471
471

TYPE
70-11656
70-12438-0
70-12438-1'
70-12754-2F
74-06706
74-06782
74-06793
74-07789
74-09449
74-09459
74-09819
74-17440
90-06990
90-07786
90-08887
91-05740
91-07688
A123
A126
A207
A619
A704
A866
AAVll-A
ADVll-A
BAI1-ES
BAll-KE
BA11-KF
BBll
BBll-A
BB1l-B
BCOIR-25
BCOIV-25
BC04Z-10
BC05C-2S
BC05C-SO
BC05D-I0
BCOSD-25
BCOSH-6
BCOSJ-6
BC06R-06
BC06R-10
BC06R-25
BC06R-50
BC06S-10
BC06S-25
BC06S-40
BC07A-IO

Page

TITLE

161
Console Bezel .. ". ,
412
Blower Fan for H984-BA (11S Vac) .'
412
Blower Fan for H984-BB (230 Vac) "".
161
Remote Signal Cable " .. ,..
401
Fan, Cover Plate ..
400
Kickplate (use with H952-BA) ....
400
Kickplate
' ......... ,....
410
Spacer ...... ,:,
417
Bracket for Chassis Slides (right) .
417
Bracket for ChassiS Slides (left)
410
Key-Lock Strike Plate .... "".
.." .... " .....
412
Blank Connector Panel for H984-B """ .. "
411
Cabinet Door Ground Strap" " ............ ..
Tinnerman Clip Nut and Phillips Pan
410
Head Scr:~lIection
,...... bag
410
Cabinet Frame Ground Strap ........
464
Wire Wrapping Wire, 30 AWG ,
464
Wire Wrapping Wire, 24 AWG ... " ........... ,,"
4-lnput Multiplexer .. ".",,:;. ,,, .. ,, .. ,,,, .. ,,.,,, ) 377
8-Channel High Impedance Multiplexer ... ,
379
382
Operational Amplifier ."." .. " " ",,"" """'"''
384
'lO-Bit D/A Converter, Single Buffered " .. "
386
Reference Supply"" .. """ .. ".:""" .. "" .. ".".
388
High-Speed 12-Bit Bipolar AID Converter"
133
LSI-ll DIA Converter """"""""" ..... ",,:,,"
134
LSI-ll AID Converter "".""""" .. """""".,
420
Expansion. Mounting Box ""."".""""" ... "",
421
;' Expansion Mounting Box """ ... " .. " .. """ .. ",
421
Expansion Mounting Box """""""",, ..... ,,,,.
431
4-Slot System Interfacing Unit ...... " .. "",,"
431
4-Slot System Interfacing Unit .. " .. " .. " .. ""
434
9-Slot System Interfacing Unit .. "".,,, ... ,,,,.
463
M970 plus--1t'BCOSC-2S ~ .. "" ... """ .. " .. "" ... .
463
EIA Data Cable .... ".""" ...... ,'"""" ..... " ..... .
40-Conductor Flat Mylar Cable ................. .
463
2S-Conductor Round Cable, 2S ft_ .. , ......... ,.
463
2S-Conductor Round Cable, 50 ft ... " .. "."",
463
463
2S-Conductor Round Cable """""""''''''''''
2S-Conductor Round Cable .... """ .. " .. " ... ".
463
Line Cord Set, 60 Hz """" ..... " .... ".,, .. ,,",,"
463
463
Line Cord Set, SO Hz "''''''''''''''''''''''''''''''''
Mass Bus (Flat) .... "" .. "." .... """".",,",,",, ..
463
Mass Bus (Flat) ......................................... .
463
463
Mass Bus (Flat) .... " ..... " ....... """ ........... ,, ...
Mass Bus (Flat) ......................................... .
463
463
Mass Bus (Round) ... """"" .. """.""""""""
Mass Bus (Round) ... """"."".",,"".,,."." ... .
463
Mass Bus (Round) .... " ... """" ...... ,,.: ........ .
463
20-TWP Round Cable ... " ... "" .... "."",,,,,,,,,,,
463

491

TYPE

TITLE

SC05M-2C
BC05M-4
BC07A-15
BC07A-25
BC07S-10
SC07B-25
SC07D-IO
BC07D-I5
SC07D-25
BCOSA-03
BCOSA-05
BCOSA-IO
BCOSJ-IO
BCOSJ-I5
BCOSM-OM
BCOSR-Ol
BCOSR-06
SC08R-08
BC08R-IO
BCOSR-12
BCOSR-20
BCOSR-25
BCOSR-50
BCOBR-60
BCOSR-AO
BCllA-02
BCIIA-05
BCIIA-SF
BCllA-IO
BCllA-I5
SCllA-20
BCIIA-25
BCIIA-35
BCllA-50
BCllK-25

TTY Cable ................................................. .
TTY Cable ................................................ .
20-TWP Round Cable ............................... .
20-TWP Round Cable ............................... .
ll-TWP Round Cable ............................... .
ll-TWP Round Cable ............................... .
Two 20-Conductor Ribbon Cables ............. .
Two 20-Conductor Ribbon Cables ............. .
Two 20-Conduetor Ribbon Cables .. :.......... .
Multi-Purpose Cable ................................. .
Multi-Purpose Cable ................................. .
Multi-Purpose Cable ................................. .
40-Conductor F'lat Mylar Cable ................. .
40-Conductor Flat Mylar Cable ................. .
Cable with HS59..Q..HS59 .~ ......................... .
40-Conductor Flat Mylar Cable ................. .
40-Conductor Flat Mylar Cable ........... ,..... .
40-Conductor Flat Mylar Cable ................. .
40-Conductor Flat Mylar Cable ................. .
40-Conductor Flat Mylar Cable ................. .
40-Conductor Flat Mylar Cable ................. .
40-Conductor Flat Mylar Cable ................. .
40-ConductorFlat Mylar Cable ................. .
40-Conductor Flat Mylar Cable ................. .
40-Conductor Ilat Mylar Cable ................ ..
Two 60-Conductor Flat Mylar Cables ....... .
Two 60-Conductor Flat Mylar Cables ....... .
Two 60-Conductor Flat Mylar Cables ....... ,
Two 60-Conductor Flat Mylar Cables ....... .
Two 6O-Conductor Flat Mylar Cables ....... .
Two 60-Conductor Flat Mylar Cables ....... .
Two 60-Conductor Flat Mylar Cables ....... .
Two 60-Conductor Flat Mylar Cables ....... .
Two 60-Conductor Flat Mylar Cables ..
20-TWP Round Cable (Used with DRVll)
25 feet .................... \ .............................. .
HS56-to-HS56. 36-Conductor Round ....... .
H856-to-H85.6. 36-Conductor Round ....... .
LSI-ll Jumper Cable Assembly. 2 feet ..... .
LSI-ll Jumper Cable Assembly. 4 feet ..... .
lSI-ll Jumper Cable Assembly. 6 feet ..... .
lSI-ll Jumper Cable Assembly. 10 feet ... .
lSI-ll Jumper Cable/Terminator Assembly.
2 feet ....
. ...................................... .
lSI-ll Jumper Cable/Terminator Assembly.
4,feet ............... . .................................. .
lSI-II Jumper Cable/Terminator Assembly.
6 feet ..................................................... .
lSI-II Jumper Cable/Terminator Assembly.
10 feet ................................................... .
Program Control CHIPKIT Chips ..... .
DMA CHIPKIT Chips ............................. .

BCIIS-50
BCIIS-AO'BCVIA-02
BCVIA-04
BCVIA-06
B0VIA-IO
BCVIB-02
BCVIB-04
BCVIB-06
BCVIS-IO
DCKll-AA
DCKll-AB

Page

492

463
463
463 •

463

463

463
463
463
463

463
463
463

463
463
463
463
463
463

463
463

463
463
463

463
463
463

463
463

463
463
463
463

463
463

463
464
464
136
136

136
136

136
136

136
136
164
164

TYPE

TITLE

DCK11-AC
DCKll·AD
DDVll-B
DECkitll-D
DECkitll-H

Program Control CHIPKlt, Complete ........
DMA CHIPKIT, Complete ......................... ...
LSI-ll 9x6 Backplane Assembly................
PDP-ll Direct Memory Access Interface..
PDP-II I/O Interface (4 Words In/4 Words
Out) ........................................................
LSI-ll Serial Interface Unit ........................
2·Word OMNIBUS Input Interface ..............
2-Word Input-UNIBUS Interface ................
2-Word Output UNIBUS Interface ..............
LSI·ll Parallel Interface Unit ....................
Direct Memory Access Interface foc.lSt-ll
LSI-ll Interface Foundation Module ..........
Power Control Board .:................................
Connector Block Mounting Frame ............
4-Slot System Unit Mounting Frame..........
9·Slot System Unit Mounting Frame ..........
Vertical System Unit Mounting Frame ......
Distribution Panel ......................................
Power Supply (+5 Vdc,-15 Vdc) ............
Power Supply (+5 Vdc,-15 Vdc, +B Vdc,
,-22 Vdc) ..............................................
Power Supply (+5 Vdc,-15 Vdc, +B Vdc,
,-22 Vdc) ..............................................
Step·Down Transformer ............................
Power Supply <+5 Vdc) ......................... .-..
Power Supply (+5 Vdc,-15 Vdc, +15 Vdc)
Power Supply (+5 Vdc, ±15 Vdc) ............
Connector Block (144·Pin) ...... ..................
Connector Block (lB-Pin) ..........................
Connector Block (2BB-Pin) ........................
Connector Block (36-Pin) ..........................
Connector Block (144-Pin) ....... .......... .......
Pistol--Grip Wire Wrapping Tool Kit for 24
AWG Wire ............................................. ;..
Pistol-Grip Wire Wrapping Tool Kit for 30
AWG Wire ..............................................
Pistol-Grip Wire Wrapping Tool Kit for 24
or 30 AWG Wire ......... .............................
Battery-PoWered Wire Wrap Gun with Bit
and Sleeve for 24 AWG Wire ..................
Battery-Powered Wire Wrap Gun with Bit
and Sleeve for 30 AWG Wire ..................
Hand Wire Wrapping Tool for 24 AWG Wire
Hand Wire Wrapping Tool for 30 AWG Wire
Hand Wire Unwrapping Tool for 24 AWG
Wire ........................................................
Hand Wire Unwrapping Tool for 30 AWG
Wire ........................................................
Wire Wrap Gun Bit for 24 AWG Wire, ..........
Wire Wrap Gun Bit for 30 AWG Wire ..........

DLVII
DRS-ED
DRI1-L
DRll·M
DRVll
DRVll-B
DRVll-P
G772
H020
H033
H034
H035
H322
H7l6
H720-E
H720-F
H722
H726-B
H740-D
H755
HBOO-W
HB02
H803
HS07
HS08
HS10(24)
HB10-A
HB10-B
HBIO-C
HSI0-D
HSll(24)
HBll-A
HB12(24)
HB12-A
HB13(24)
H813-A

Page

493

164
164
434
101
123
132
24
53
63
133
13B
14B
376
430
431
434
414
42S
423
424
424
42B
423
424
424
440
440
440
440
440
455
455
455
455
455
455
455
455
455
455
455

TYPE
H814(24)
H814-A
H820
H821
H850
H851
H852
H853
H854
H856
H863
H909-A
H909-BA
H909-C
H91l-J
H91l-K
H91l-SH914
H916
H933-C
H933-CA
H933-CB
H934-CB
H950-AA
H950-BA
H950-CA
H950-DA
H950-EA
H950-FA
H950-G
H950-HA
H950-HC
H950-HD
H950-HF
H950-H~

H950-HH
H950-HK
H950-JA
H950-LA
H950-LB
H950-PA

Page

TITLE

Wire Wrap Gun Sleeve for 24 AWG Wire ... .
Wire Wrap Gun Sleeve for 30 AWG Wire .. ..
Grip Clip Connectors for 24 AWG Wire
(1000/pkg)
.................. r .•.•.
Grip Clip Connectors for 30 AWG Wire
(1000/pkg) ...................... '" .......... ..
Module Handle Extender ................. .
Edge Connector ...................................... .
Module Holder (25/pkg) .......................... ..
Module Holder (25/pkg) .......
.. ............ .
I/O Connector (40-Pin Male) Board Mount
I/O Connector (40-Pin Female) Cable
Mount ................................................... .
Connector Block (288-'Pin)
............... .
General Purpose A Logic Box .................. .
General Purpose Logic Box with Power
Supply .......... ~ ...................................... .
General Purpose Logic Box ........ ..
Mounting Panel.......... .. ........................ ..
Mounting Panel . . . . . . . . . . . . .......... ..
Mounting Panel ............
.. ................. .
Mounting Panel .................................... .
Mounting Panel
...... _.................... ..
4-Slot System Unit ................... .
4-Slot System Unit ..................... .
4-Slot System Unit ................ .
9-Slot System Unit ............... .
Cabinet Frame (Standard Size) ................ ..
Full Door (RH) (Front or Rear Mounting) ..
Full Door (LH) (Front or Rear Mounting) .
Mounting Panel Door Frame (RH) (Rear
Mounting) ........ : ................. .
Mounting Panel Door Frame (LH) (Rear
Mounting) .......................................... ~ .. .
Mounting Panel Door Skin .... .
Cabinet Table
.................................. .
Short Door (Covers 21 in. Mounting Space)
Short Door (Covers 26-1/4 in. Mounting
Space) ...............
.. .................... ..
Short Door (Covers 31-1/2 in. Mounting
Space)
............................... ..
Short Door (Covers 42 in. Mounting Space)
Short Door (Covers 47-1/4)n. Mounting
Space)...... .................. .
Short Door (Covers 52-1/2 in. Mounting
Space) ............... ..............
. ............ ..
. Short Door (Covers 63 in. Mounting Space)
Short Door (Cpvers 21 in. Mounting Space)
(used with H952-BA installed)
logo Frame Panel (Aluminum) ..
Logo Frame Panel (Plastic) .................. .
Bezel Cover Panel (5-1/2 in.) ................. .
494

455
455
458
458
456
472
456
456
472

472
440
- 417
417
415
420
420

420
420
420
431
431
431

434
400
400
400
400
400
400
400

400
400
400
400

400
400
'400
400

400
400

400

TYPE

TITLE

Page

H950·QA
H950·SA
H952·AA '
H952·BA
H952-CA
H952-CB
H952·GA

Bezel Cover Panel (10·1/2 in.) ....
Air Filter (for H952-BA or H952-CA) ......... .
End Panel (require 2 per cabinet) ..........,.
Stabilizer Feet (Pair) .................... : ............ .
Fan Assembly (Top Mounted) (115 Vac) ..
Fan Assembly (Top Mounted) (250 Vac) ..
Filler Strip Set (Front and Rear) (Joining
Two Cabinets)..
. ............... .
Free-Standing Table ................................. .
Cabinet Frame (Short Size) ........................ .
Full Door (RH) (Rear Mounting) ............... .
Full Door (LH) (Rear Mounting) ............... .
Mounting Panel Door Frame (RH) ....... .
End Panel (R end) ......................... .
End Panel (L end) .................................... ..
Filler Strip Set (Top, Front, and Rear)
(Joining Two Cabinets) ....................... ..
Fan Assembly (Front or Rear Mounting) .. ..
Bottom Cover Plate ....... .
Logo Frame Panel ..................... ..
Filter (for H957-HA) .. ....
. ............... .
Cabinet Assembly (Standard Size)
Cabinet Assembly (Standard Si:!e) .... ~.
Cabinet Assembly (Standard Size)
Cabinet Assembly (Standard Size) ....... ..
Cabinet Assembly (Short Size) ............... .
Low-Profile Cabinet, 115 Vac .. ..
Low-Profile Cabinet, 230 Vac ................ ..
Bracket Set to Mount H909-C .................. .
General Purpose Systems Desk ............. .
Card Cage Assembly ................................ ..
Connector Block (72-P,in) ... .
4x4 Backplane Assembly for LSI-11 ......... .
4x4 General Purpose Backplane ............. .
Gate Expander .................................. ..
Gate Expander ..................... .
Gate Expa nder ..................... , .. .

400
400
. 400
400
400
400

H952·HA
H957·AA
H957·BA
H9?7·CA
H957·DA
H957-FA
H957-FB
H957-GA
. H957·HA
H957·JA
H957·LA
H957-SA
H960-BC
H960-CA
--H961-A
H961-AA
H967·BA
H984·BA
H984·BB
H984-CA
H9800-A
H0341
H8030
H9270
H9271
~K003

K012
K026
K028
K1l3
K123
K124
K134
K135
K138
Kl~1

K174
K201
K202
K206
K207
K210
K211

?:::rt~~;a~:~:::::::::::::::::::::::::.:: :

Non-Inverting Gate ................. .
AND/OR Gate .............. ..
Inverters ...................................... .
Inverters ........ '" ........................... .
Inverters .......
............ .
Binary-to·Octal Decoder
Digital Comparator ........................... _... .
Flip-Flop
............... .
Flip-Flop
............. .
Flip-Flop Register .................. .
Flip-Flop .............. .
Counter ...
. ............ .
Programmable Divider ... .
495

400
400
406
406
406
406
406
406
406
406
406
406
406

400
400
400
400
406
406
406
416
413
434
440
135
432

394
394
394
394
394
394
394
394

394
394
394
394
394

394
395 395
395
395

..

I

TYPE

TITLE

K220
K230
K265
K281
K282
K302
K303
K323
K371
K373
K374

l.!p/Oown Counter' ................................... :..
Shift Register ............................................
Reed Relay Driver .....................................
Fixed Memory ............................................
Diode Memory ............................................
Dual Timers ................................................
Timer ..........................................................
One-Shots ......................... '" . .. ... . .. .. ...........
Clock Control, 200 Hz to 6 KHz ............... ;
Clock Control, 20 Hz to 600 Hz ................
Calibrated Timer Control, 0.01 sec to 0.3
sec ..........................................................
Clock Control, 2 Hz to 60 Hz ....................
Calibrated Timer Control, 0.1 sec to 3 sec
Calibrated Timer Control, I sec to 30 sec
Schmitt Triggers ........................................
Isolated AC Input Converters ... ................
Dry Contact Fi Iters ....................................
Dry Contact Filters ....................................
Isolated AC Switches ................................
DC Driver .......... , ................ ,...... ,.. .. .. ...... .. .
DC Driver .. ,........ ' ......... ,... ...... .... .. ... ... ... ....
DC Driver ........... '.' .. .... .. .. .. ............ .... .. .. .....
5-Digit Display ... :........................................
Interface Shell ............................................
Mounting Panel ............... ~...........................
Mounting Panel..........................................
Timer Component Board ............................
Microcomputer Module System with 4K'
RAM .. ; .......... :..........................................
Microcomputer Module System with 4K
Core ........................................................
Microcomputer Module System with 16K
RAM ..............,:.........................................
LSI-ll Power Fa'il/LTC Generator ..............
LSI-ll Power Fail/LTC Generator/
Terminator ............................................
LSI-II Real Time Clock......................... .....
LogiC HIGH Source ....................................
Solenoid Driver ..........................................
50 mA Indicator Driver ..............................
Positive to Negative Logic Level Converter
Solenoid Driver ............. :............................
Bus Data Interface ....................................
Bus Data Interface ....................................
Device Selector ..........................................
Device Selector ..........................................
Address Selector ........................................
Device Selector ....................... :..................
F.lag Module ..............................................
Inverter ............................... '" ...... ... ...........
NOR Gates ..................................................

K375
K376
K378
K501
K579
K580
K58I
K616
K652
K657
K658
K675
K724
K943-FP
K943-WP
K990
KDll-F
.KDll-J
KDll-R
KPVll-A
KPVll-B

\.

KWVll-A
M002
M040
M050
M051
M060
MI00
MI0l
MI02
MI03
MI05
MI07
MI08
Mlll
M112

Page

496

•

395
395
395
395
395
395
395
395
395
395
395
395
395
395
396
396
363
363
366
368
369
370
371
419
430
430
397
126
128
128
155
163
134
239
240
242
121
243
121
120
121
120
69
120
120
245
246

TYPE
MIl3
MIl5
M116
MIl7
M119
M121
M133
M135
M137
M139
M141
MI55
M159
M161
MI62
M163
MI65
MI68
MI91
M202
M203
M204
M205
M206
M207
M230
M236
M237
M238 \
M239
M245
M246
M248
M306
M310
M401
M403
.M404
M405
M500
M501
M502
M506
M510
M521
M594
M598
M602
M611

. Page

TITLE

NAND Gates ............................................. .
NAND Gates ............................................. .
Six 4-lnput NOR Gates ............................. .
NAND Gates ........................................... .
NAND Gates ............ : ................................ .
ANDIOR Gates ......................................... .
2-lnput NAND Gate .................................. ..
Qight 3-lnput NAND Gates ...................... ..
Six 4-lnput NAND Gates .......................... ..
Three 8-lnput NAND Gates ....................... .
NAND/OR GATES ..................................... .
4-Line to 16-Line Decoder ......................... .
Arithmetic/Logic Unit ............................... .
Binary-to-Octal/Decimal Decoder ............. .
Parity Circuit .............................................. .
Dual Binary-to-Decimal Decoder ........... ..... .
8 Buffers .................................................... .
12-Bit Magnitude Comparator ........... ........ .
ALU Look-Ahead Logic ............................. .
Triple J-K Flip-Flop .................................... .
8 R/S Flip-Flops ...................................... ..
General Purpose Buffer and Counter ....... .
General Purpose Flip-Flops ........................ .
General Purpose Flip-Flops ...................... ..
General Purpose Flip-Flops ...................... ..
Binary-to-BCD and BCD-to-Binary
Converter ............................................... .
12-Bit Binary Up/Down Counter .............. ..
3-Digit BCD Up/Down Counter ................. .
Dual 4-Bit Binary Synchronous Up/Down
Counter ......................... .-...................... ..
Three 4-Bit Counter/ijegister ................... .
Dual 4-Bit Shift Register .......................... ..
5 D-Type Flip-Flops ................................... .
\ Dual 4-Bit Multipurpose Shift Register ..... .
Integrating One-Shot ................................. .
Delay Line ................... , ............................ ..
Variable Clock ........................................... .
RC Multivibrator Clock ............................. .
Cry.stal Clock ............................................. .
Crystal Clock 5 KHz to 10 MHz ............... .
Negative Input/Positive Output Receiver ..
Schmitt Trigger .................................. : ...... .
High-Speed Negative Input Converter ....... .
Medium-Speed Negative Input Converter ..
I/O Bus Receiver ..................................... .
K-to-M Converter .............................. .
EIA/CCITT Level Converter ....................... .
I-Channel Transmit/Receive' Optic-Coupled
Current Isolator ................. ,................... .
Pulse Amplifier ............ .......................... ..
High-Speed Power Inverter ............... .
497

247
247
250
247
247
251
252
253
254
255
256
257
258
261
263

264
266
267
269
272
273
274

275
276
278
280
283
285
287
289
291
293
295
297
299
300
302
304
305
122
306
122
122
122
308
309
312
314
315

TYPE
M617
M622
M623
M624
M627
M632
M633
M650
M652
M660
M671
M706
M707
M730
M732
M734
M735
M737
M738
M783
M784
M785
M795
M796
M798
M901
M903
M904
M906
M907
M908
M909
M910
M912
M917
M918
M920
M922
M927
M930
-M933
M935
M943
M953
M954
M955
M957
M971
M973
M975
M976
M981

. Page

TITLE

4-lnput Power NAND Gate ......................... .
8-Bit Positive Input/Output Bus Driver .. ..
Bus Driver ................................................. .
Bus Driver ................................................. .
NAN D Power Amplifier ............................ ..
Positive Input/Negative Owtput Bus Driver
Negative Bus Driver ................................ ..
Negative Output Converter ... :: .................. .
Negative Output Converter ...................... ..
Positive Level Cable Driver ...................... ..
M-to-K Converter ...................................... ..
Teletype Receiver ..................................... .
Teletype Transmitter ................................. .
Bus Interface ............................................ ..
Bus Interface ............................................. .
I/O Bus Input Multiplexer ........................ ..
110 Bus Transfer Register ......................... .
12-Bit Bus Receiver Interface ................... .
Counter·Buffer Interface ........................... .
UNIBUS Drivers ....................................... .
UNIBUS Receivers ..................................... .
UNIBUS Transceiver ......................, .......... .
Word Count and Bus Address Modu'le ...... ..
UNIBUS Master Control .......................... ..
UNIBUS Drivers ...................................... ..
Flat Mylar Cable Connector ...................... ..
Flat Mylar Cable Connector ....................... .
Flat Coaxial Cable Connector .................. ..
Cable Terminator .................................... ..
Diode Clamp Connector .......................... ..
Flat Ribbon Cable Connector .................... ..
Terminator ................................................ ..
Terminator ................................................. .
Round Coaxial (TWP) Cable Connector .... ..
Flat Coaxial Cable Connector .................. :.
Flat Mylar Cable Connector .................... ..
U,NIBUS Jumper Module .......................... ..
Flat Mylar Cable Connector .................... ..
Round Coaxial (TWP) Cable Connector ... :..
UNIBUS Terminator Module' ... ;................ ..
Flat Ribbon Cable Connector .................. ..
OMNIBUS Jumper Module ...................... ..
Flat Mylar Cable Connector ...................... ..
Flat Shielded Cable Connector ................ ..
Flat Shielded Cable Cpnnector ................ ..
Flat Shielded Cable Connector ................ ..
Flat Ribbon Cable Connector .................. ..
Cable Connector ...................................... ..
TTY Cable Connector ... : .......................... ..
Flip Chip to H854 Adapter ...................... ..
UNIBUS Cable Connector ........................ ..
Internal UNIBUS Terminator Module ...... ..
498

316
123{
120
120
317
122
122
122
122
318
319
321
326
120
120
121
121
121
121
71
72
73
'74
77
80
467
467

468
475
121
465
477
478

468
468
467

470
467

468

470
468

470
467
469
469
469

465
47.3.

473
473
465

470

TYPE
Mll03
- M1l25
M1l31
M1307
M1500
M1501
M1502
M1621
M1623
M1701
. M1703
M1705
M1709
M1710
M1713

M1801
M2001
M2500
M3020
'M4Q50
M5864
M5960
M6865
M7390
M7800
M7821
M7860
M9100
'M9970
MMVll-A
MRVII-AA
MSVll-B
MSV11-CD
QJV10-CB
REV11-A
REV11-C
TEV11
WOll
W021
W023
W024
W027
W028
W033
W900
W930
W940
W941
W942
-W943

Page

TITLE
2-lnput AND Gates ................................... .
Exclusive-OR Gates .....-.............................. .
2-lnput Open-Collector NAND Gates ......... .
4-lnput AND Gates .................................... .
Bidirectional Bus Interfacing Gates ......... .
Bus Input Interface ................... : ............... .
Bus Output Interface .......................... _...... .
DVM Data ,Input Interface ........................ .
Instrument Remote Control Interface ....... .
Data Selector ....................... " .................. .
OMNIBUS Input Interface ......................... .
OMNIBUS Output Interface ....................... .
OMNIBUS Interface Foundation Module ... .
UNIBUS Interface Foundation Module ..... .
16-line-to-l-line Data Selector ............... .
16-Bit Relay Output Interface ................... .
Dual 4-Bit Tri-State Registers ................... .
Dual 64-Word x 4-Bit FIFO Memory ......... .
Dual Delay Multivibrators ......................... .
Crystal Clock ............................................. .
Optic Isolator, Input ................................. .
20 Mil to DEC Converter ......................... .
Optic Isolator, Output ............................... .
Asynchronous Transceiver ....................... .
Single Asynchronous Serial line Interface
Interrupt Control Module ........................... .
I-Word Input/Output Device Interface ..... .
Adapter (H854-to-H854) Connector ......... .
H854-to-Backplane Adapter ..................... .
4Kx16 Core Memory ... '.............................. .
PROM/ROM Memory Unit ....................... .
4Kx16 RAM ............................................... .
16Kx16 lSI-ll MOS Memory .................. ..
lSI-ll Paper Tape Software Package ...... ..
LSI-ll ,Refresh/Bootstrap/Diagnostic/
. Terminator Option ................................ ..
lSI-l1_ Refresh/ Bootstrap/ Diagnostic/
Option ................................................... .
lSI-ll Terminator Module ....................... :
Flat Ribbon Cable Connector .................. ..
Flat Ribbon Cable Connector ................... .
Flat Ribbon Cable Connector .................. ..
Round Coaxial (TWP) Cable Connector .... ..
Flat Ribbon Cable Connector .................. ..
Round Coaxial (TWP) Cable Connector .... ..
Flat Mylar Cable Connector ..................... .
Module Extender Board .......................... ..
Blank Module ........................................... .
Wire Wrappable Module .......................... ..
Wire Wrappable Module ........................... .
Wire Wrappable Module with Sockets ....... .
Wire Wrappable Module with Sockets ...... ..
·499

330
331
332
333
82

84
86
122
122
334
30
33
38
89
336

93
338
340
344
346
348
352
355
359
107
96
113
472
474
128
128
128
128
136
136
136
136
465
466
466
468
466

468
467
445
442
454

454
454
454

.

Page

TYPE

TITLE

W950
W951
W952
W953
W960
W964
W966
W967
W968
W969
W970
W971
W972
W973
W974
W975
W979
W980
W982
W983
W984
W987
W990
W991

Wire Wrappable Module .......................... ..
Wire Wrappable Module ........................... .
Wire Wrappable Module with Sockets ....... .
Wire Wrappable Module with Sockets ....... .
MSI Module Board ................................... .
Universal Terminator Board ..................... .
OMNIBUS Wire WraQ Module ................... .
OMNIBUS Wire Wrap Module with Sockets
Collage Module Board ............................. .
Collage Module Board ............................. .
Blank Module ........................................... .
Blank Module ........................................... .
Blank Module, Copper-Clad on Both Sides
Blank Module, Copper-Clad on Both Sides
Blank Module, Perforated ........................ ..
Blank Module, Perforated ........................ ..
Collage Module Board ........... :................... .
Module Extender Board ........................... .
Module Extender Board .......................... ..
Module Extender Board ....................... '.... .
Module Extender Board .......................... ..
Quad Module Extender Beard ................... .
Blank Module ........................................... .
Blank Module ........................................... .
Blank Module, Copper-Clad on One Sides .,
Blank Module, Copper-Clad on One Side .,
Blank Module, Perforated ........................ ..
Blank .Module, Perforated ........................ ..
Wire Wrap Module, Quad ................~ ........ ..
Wire Wrap Module, Hex .......................... ..
Wire Wrap Module, Hex, SPC .....................
Wire Wrap Module, Quad, SPC .... .
Wire Wrap Module, Double, SPC ............... .
Wire Wrap Module, Hex, SPC .............. :... ..
Wire Wrap Module, Quad, SPC ................ ..
Wire Wrap Module, Double, SPC ............... .
Wire Wrap Module, Quad, LSI-l1 ........... .
Wire Wrap Module, Double, LSI-l1 ........... .
Wire Wrap Module, Quad, LSI-ll ...... : ........ .
Wire Wrap Module, Double, LSi-II .......... ..
Blank Module, Copper-Clad on Both Sides
Blank Module, Copper-Clad on Both Sides
Blank Module, Copper-Clad on Both Sides

W992
W993
W998
W999
W9301
W9302
W9500
W9501

W9502
W9§03
W9504
W9505
W9511
W9512
W95I4
W9515
W9720
W972I
W9722

500
/

454
454
454
454
373
374
42
44

444
444
442
442
442
442
442
442

444
445
445
445
445
445
443
443
~443

443
443

443
450
452
447
447

447
447
447
447
447
447
447
447
442
442
442

NOTES

;

NOTES

I.

NOTES

c

--"

NOTES

NOTES

.

"

\

NOTES

.j

•

I.

t

mamalla
DIGITAL EQUIPMENT CORPORATION, Corporate Headquarters: Maynard,
Massachusetts 01754, Telephone (617) 897-5111 -SALES AND SERVICE
OFFICES; UNITED STATES-ALABAMA, Birmingham and Huntsville.
ARIZONA, Phoenix and Tucson. CALIFORNIA, los Angeles, Oakland, Sacramento, San Diego, San Francisco, Santa Ana, Santa Barbara, Santa Clara,
Sunnyvale. COLORADO, D.nver • CONNECTICUT, Fairfield and Meriden.
DISTRICT OF COLUMBIA, washington, D.C. (Lanham, MD) • FLORIDA, Miami,
Orlando, Tampa. GEORGIA, Atlanta. HAWAII, Honolulu • ILLINOIS, Chicago,
Peoria, Rolling Meadows .,NDIANA,lndianapolis • IOWA, Bettendorf.
KENTUCKY, Louisville • LOUISIANA, New Orleans. MASSACHUSETTS,
Springfield and Waltham • MICHIGAN, Detroit. MINNESOTA, Minneapolis.
MISSOURI, Kansas City and St. Louis. NEBRASKA, Omaha. NEW HAMPSHIRE, Manchester • NEW JERSEY, Cherry Hill, Fairfield, Princeton, Somerset. NEW MEXICO, Albuquerque. NEW YORK, Albany, Buffalo, Long Island,
Manhattan, Rochesler, Syracuse • NORTH CAROLINA, Charlotte and Durham/Chapel Hill • OHIO, CinCinnati, Cleveland, Columbus, Dayton. OKLAHOMA, Tulsa. OREGON, Portland. PENNSYLVANIA, Harrisburg, Philadelphia (Blue Bell), Pittsburgh. RHODE ISLAND, Providence. SOUTH
CAROLINA, Columbia • TENNESSEE, Knoxville and Nashville • TEXAS,
Austin, Dallas, EI Paso, Houston. UTAH, Salt Lake City. VI RGINIA, Richmond
• WASHINGTON, Seattle. WEST VIRGINIA, Charleston. WISCONSIN, Milwaukee. INTERNATIONAL-ARGENTINA, Buenos Aires. AUSTRALIA,
Adelaide, Brisbane, Canberra, Melbourne, Perth, Sydney. AUSTRIA, Vienna
• BELGIUM, Brussels. BOLIVIA, La Paz. BRAZIL, Rio-de Janeiro and Sao
Paulo • CANADA, Calgary, Edmonton, Halifax, London, Montreal, Ottawa,
Toronto, Vancouver, Winnipeg. CHILE, Santiago. DENMARK, Copenhagen
• EGYPTCA.R.E.), Cairo. FINLAND, Espoo. FRANCE, Lyon, Paris, Puteaux •.
HONG KONG. INDIA, Bombay. INDONESIA, Djakarta • IRAN, Tehran •
IRELAND, Dublin. ISRAEL, Tel Aviv. ITALY, Milan, Rome, Turin. JAPAN,
Osaka and Tokyo • MALAYSIA, Kuala Lumpur • MEXICO, Mexico City •
NETHERLANDS, Amstelveen, Rijswijk, Utrecht. NEW ZEALAND, Auckland
and Christchurch. NORTHERN IRELAND, Belfast. NORWAY, Oslo.
PUERTO RICO, San Juan. SINGAPORE. SOUTH KOREA, Seoul • SPAIN,
Madrid • SWEDEN, Gothenburg and Stockholm. SWITZERLAND, Geneva
and Zurich • TAIWAN, Taipei • UNITED KINGDOM, Birmingham, Bristol,
EaJing, EpSOm, Edinburgh, Leeds, Leicester, London, Manchester, Reading •
VENEZUELA, Caracas. WEST GERMANY, Berlin, Cologne, Frankfurt, Hamburg, Hannover, Munich, Nurnberg, Stuttgart. YUGOSLAVIA, Belgrade and
Ljubljana •

., .....
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