Digital_Microcomputer_Interfaces_Handbook_1980 Digital Microcomputer Interfaces Handbook 1980
Digital_Microcomputer_Interfaces_Handbook_1980 Digital_Microcomputer_Interfaces_Handbook_1980
User Manual: Digital_Microcomputer_Interfaces_Handbook_1980
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DIGITAL facility, Marlboro, Massachusetts
CORPORATE PROFILE
Digital Equipment Corporation designs. manufactures , sells and services computers and associated peripheral equipment, and related
software and supplies. The Company's products are used world-wide
in a wide variety of applications and programs , includ ing scientific
research , computation , communications , education , data analysis, industrial control, timesharing, commercial data processing, word processing, health care, instrumentation , engineering and simulation.
· microcomputer
inter~aces handbook
mamall!a .
Copyrlght© 1981 Digital Equipment Corporation.
All Rights Reserved.
Digital Equipment Corporation makes no rep'resentation that the Interconnection of its products in the manner described herein will not
infringe on existing or future patent rights, nor do the descriptions
contained herein imply the granting of license to make, use, or sell
equipment constructed in accordance with this description.
The information in this document is subject to change without notice
and should not be construed as a commitment by Digital Equipment
Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear In this manual.
DEC, DECnet, DECsystem-10, DECSYSTEM-20, DECtape,
DECUS, DECwriter, DIBOL, Digital logo, lAs, MASSBUS, OMNIBUS,
PDP, PDT, RSTS, RSX, SBI, UNIBUS, VAX, VMS, VT
are trademarks of
Digital Equipment Corporation
This handbook was designed, produced, and typeset
by DIGITAL's New Products Marketing
using an In-house text-processing system
operating on a DECSYSTEM-20.
ii
CONTENTS
PART 1 INTRODUCTION
GENERAL .................................................... 1
LSI-11 FAMILY CHARACTERISTICS ............................ 1
SPECiFiCATIONS .............................................. 4
DESCRIPTION OF OPTION CATEGORIES ........................ 5
CONFIGURATION ............................•............... 25
PART 2 LSI-11 BUS INTERFACE DESCRIPTIONS
AAV11-A 4-Channel 12-Bit D/ A Converter ...................... 33
ADV11-A Analog to Digital Converter ............................ 45
BA 11-M Expansion Box ........................................ 67
BA11-N Mounting Box ........................................ 74
BA11-VA Expansion Mounting Box ............................ 83
BDV11 Diagnostic, Bootstrap, Terminator ...................... 86
DCK11-AA, -AC Program Transfer Interface .................... 114
DCK11-AB, AD Direct Memory Access Interface ................ 134
DDV11-B Backplane ........................................ 159
DLV11 Serial Line Unit. ....................................... 165
DLV11-E Asynchronous Line Interface ........................ 180
DLV11-F Asynchronous Line Interface ........................ 201
DLV11-J Four Asynchronous Serial Interfaces .................. 221
DLV11-KA EIA to 20 mA Converter ............................ 251
DRV11 Parallel Line Unit ...................................... 261
DRV11-B Direct Memory Access Interface ...................... 282
DRV11-J High-Density Parallel Interface ........................ 306
DRV11-P LSI-11 Bus Foundation Module ...................... 310
DUV11 Line Interface ........................................ 335
DZV11 Asynchronous Multiplexer .............................. 357
H780 Power Supply ................................ '.......... 385
H909C General Purpose Logic Enclosure ...................... 420
H984 Series Cabinets ........................................ 422
H9270 Backplane ............................................ 425
H9273-A Backplane .......................................... 431
H9281 Backplane ............................................ 435
H9800-A Cabinet ............................................ 441
IBV11-A Instrument Bus Interface .............................. 443
KPV11-A,-B,-C Power-Fail/Line-Time Clock/Terminator ........ 465
KWV11-A Programmable Real-Time Clock .................... 488
LAV11 Printer Option ........................................ 510
LPV11 Printer Option .........................., .............. 517
iii
REV11-A Terminator, REV11-C DMA Refresh, Bootstrap ........ 538
RKV11-D RK05 Disk Drive Controller .......................... 547
RLV11 RL01 Disk Drive Controller ............................ 563
RXV11 Floppy Disk Option .................................... 592
RXV21 Floppy Disk Option .................................... 608
TEV11 Terminator .......................................... 629
TU58 Cartridge Tape Drive .................................... 630
VK170-CA Serial Video Module ................................ 669
W9500 Series High-Density Wire-Wrappable Modules .......... 685
APPENDIX A
ASSIGNMENT OF
ADDRESSES AND VECTORS········ ... · .... 690
APPENDIX B
LSI-11 BUS SIGNALS .. ...................... 708
APPENDIX C
NOMENCLATURE FOR CIRCUIT
SCHEMATICS ······························719
APPENDIX D
ASYNCHRONOUS SERIAL LINE UNIT (SLU)
COMPARISONS ............................ 721
APPENDIX E
COMPARISON OF DATA TRANSMISSION
TECHNIQUES .............................. 729
APPENDIX F
INTEGRATED CIRCUITS .................... 732
APPENDIX G
CABLING SUMMARY ...................... 735
iv
v
INTRODUCTION
GENERAL
This handbook is a reference guide for the interface and peripheral
hardware options that can be installed on the LSI-11 bus. It includes
descriptions, specifications, configuration information, programming
information as applicable to the options, and functional theory. Because the hardware options described in this handbook are designed
to interface with a processor via the LSI-11 bus, the user should be
familiar with the contents of the appropriate processor handbook.
The handbook is organized into two parts. Part '1 contains general
information about microcomputer interfaces; Part 2 contains description of the interface options in alphanumeric sequence.
Digital Equipment Corporation designs and manufactures the options
described in this handbook. The general design criterion was to provide maximum system throughput for options when installed on the
LSI-l1 bus. LSI-11 bus-compatible processors, interfaces, and peripherals are designed to work together, providing a broad spectrum of
system-compatible hardware options. The memory and peripheral
devices can be used with various LSI-11 bus configuration; the system
can later be expanded or modified to meet new system requirements.
This hardware flexibility, when coupled with DIGITAL software and
support, provides a single source for all present and future microcomputer processing needs.
LSI-11
LSI-11
pheral
LSI-11
FAMILY CHARACTERISTICS
bus systems include various processors, memory and peridevice options, and software. Some of the characteristics of the
bus systems are:
• Low-cost powerful components for integration into any small- or
medium-sized computer system.
• Direct addreSSing of all memory locations ·and peripheral device
registers.
• Efficient processing ·of a-bit bytes (characters) without the need to
rotate, swap, or mask.
• Asynchronous bus operation that allows system components to run
at their highest possible speed; replacement with faster devices
means faster operation without other hardware or software
changes.
• A module component design that provides ease and flexibility In
configuring systems.
INTRODUCTION
• Inherent direct "memory access capabilities for high data rate devices.
• A bus structure that provides position-dependent priority for peripheral device interfaces connected to the 1/0 bus.
• Vectored interrupts that allow service routine entry without device
polling.
Processors
The processor is connected to the LSI-11 bus (backplane) as a subsystem that executes programs and arbitrates usage of the LSI-11 bus
for peripherals. It contains multiple, high-speed, general-purpose registers that can be used as accumulators, address pointers, index
registers, and other specialized functions. The processor can perform
data transfers directly between peripheral input/output (1/0) devices
and memory without disturbing the processor registers. Data transfers
include both 16-bit word and 8-bit byte data.
LSI-11 Bus
System components, including the processor, memory, and peripherals, are interconnected and communicate with each other via the LSI11 bus. The form of communication is the same for all devices on the
bus; instructions that communicate with memory can communicate
with peripheral devices. Each device, including memory locations and
peripheral device registers, is assigned an Individual byte or word
address on the LSI-11 bus.
The LSI-11 bus supports 18-bit addresses. However, processors and
peripherals having a 16-bit addressing capability are completely PDP11 hardware- and software-compatible within the 16-blt limitation. By
PDP-11 convention, all peripheral device addresses are located within
the upper 4K address space in the system, whether 16-blt or 18-blt
addresses are used. This 4K address space is called the I/O page or
"bank 7."
Whenever the I/O page is addressed, the processor must assert the
BBS7 L bus Signal. All peripheral devices use this signal line during
addressing rather than decoding address bits <15:13> or <17:13>.
An active (asserted) BBS7 L Signal will always indicate an address in
the I/O page, enabling peripheral device addressing.
Peripheral device addresses within the I/O page are decoded by each
peripheral device. Each peripheral device will include one or more
"device register(s)." These registers can be accessed under program
2
INTRODUCTION
control in exactly the same manner as memory locations. Unique addresses within the 110 page are encoded on address bits <12 :00>.
NOTE
Address bits, for the purpose of this discussion, are
logical states present on LSI-11 bus signal lines
BOAL <17:00> L during the addressing portion of a
bus cycle.
Refer to the appropriate processor handbook for a complete description of bus transactions, Including bus cycles, addressing, etc.
Device Registers
All peripheral devices are defined by one or more device registers that
are addressed as part of the main memory. These registers are generally designated control and status registers.
Control and status registers (CSRs) contain all the necessary Information to establish communications with the device. Some devices will
require fewer than 16 status bits, while other devices could require
more than 16 bits and therefore will require additional registers. The
bits of the CSR have predetermined assigned functions. Typical bit
functions include Interrupt enable, error, done or ready, and enabled.
Data buffer registers (OBRs) are for temporarily storing data to be
transferred Into and out of the processor. The number and type of data
registers is a function of the Individual peripheral device requirements.
Interrupts
Interrupts allow devices to obtain processor service when they are
"ready" for service, or "done" with a specific operation. The Interrupt
structure allows the processor to execute other programs while one or
more peripherals are "busy." When a peripheral requires service It
requests an interrupt. The processor completes execution of the
present instruction, saves PC and PS words on the stack, and acknowledges the interrupt. The highest priority peripheral device currently requesting Interrupt service responds by Inputting Its Interrupt
vector address to the processor. The processor uses this vector address as a pOinter to two memory locations containing the PC (starting
address) and PS for the peripheral device Interrupt service routine.
Program control is transferred from the interrupted program to the
routine associated with the requesting peripheral device. Note that no
device polling is required, since the Interrupt vector Is unique for that
3
INTRODUCTION
device. Once the device service routine execution has been completed, control is returned either to the previously Interrupted program or
to another peripheral device requesting Interrupt service.
Memory Address
Memory addresses are generally limited to the address space other
than the I/O page. However, the I/O page can contain read-only
memory (ROM) for disk bootstraps, paper tape loaders, diagnostics,
etc. or read/write memory for DMA buffers. The system designer must
use care in assigning memory addresses within the I/O page to avoid
conflicts with peripheral device addresses used for actual system
hardware, or addresses that system software may attempt to access
for peripheral devices not actually Installed In the system. See Appendix A for the standard assignments of the addresses In the I/O page.
SPECIFICATIONS
All the LSI-11 bus modules will operate under the following conditions:
Temperature
Humidity
to 60 0 C (41 0 to 1400 F)
10 to 95% (no condensation)
50
When operating at the maximum outlet temperature (60 0 Cor 1400 F).
adequate air flow must be maintained to control the Inlet to outlet
temperature rise across the modules to 50 C (9 0 F) maximum. The air
flow should be directed to flow across the modules.
All the Individual module specifications are Included In the detailed
descriptions of the peripheral or option. A summary of the module
characteristics Is provided In Table 2; these characteristics are defined as follows:
1. The option designation Is the alphanumerical code assigned to
the option.
2. The module number Is the number assigned to the Interface modules that are connected to the LSI-11 bus. This number Is printed
on the module handle and can be used as a quick reference to
determine what specific options are Installed In any system. The
module numbers are listed numerically In Table 3 so that the ~ser
can identify the options Installed by using the module numbers.
3. The module description Identifies the category of the option.
4. The power requirements specify the power by the option when
connected to the bus backplane. These requirements are used to
determine the total power supply loading within a single system.
4
INTRODUCTION
5.
6.
The bus loads for ac and dc loading are provided so that the user
can calculate the total ac and dc loading for any system.
The Interface modules are standarlzed as either a double or a
quad and all are extended length. The double size module is 13.2
cm (5.2 in.) high, 22.8 cm (8.9 in.) long, and 1.27 cm (0.5 In.) wide.
The quad size module is 26.5 cm (10.5 In.) hi'gh, 22.8 cm (8.9 in.)
long, and 1.27 cm (0.5 in.) wide (Figure 1).
DESCRIPTION OF OPTION CATEGORIES
The LSI-11 bus peripherals and options are classified into general
categories that pertain to their performance and function. This listing
Indicates the wide span of equipment capability available to the user
Interface Options
AAV11-A
The AAV11-A Is a 4-channel, 12-bit dlgital-to-analog
converter module that Includes control and interfacing circuits. It has four 01 A converters, a dc-dc
converter that provides power to the analog circuits,
and a precision voltage reference. Each channel has
its own holding register that can be addressed separately and provides 12 bits of resolution. Bits 0, 1, 2,
and 3 of the fourth holding register are brought out
to the 110 connector so that they can be used as a 4bit digital output register.
ADV11-A
The ADV11-A Is a 12-bit successive approximation
analog-to-digital converter that samples analog data
at specified rates and stores the digital equivalent
value for processing. The multiplexer can accommodate up to 16 single-ended or 8 quasi-differential
inputs. The converter uses a patented auto-zeroing
design that measures the sampled data with respect
to its own offset and therefore cancels out its own
offset error.
Exte,rnal event inputs can originate at the user's
equipment or from the Schmitt trigger output of the
KWV11-A clock. Three reference signals are provided for self-testing any channel input. These signals
consist of two dc levels and one bipolar triangular
waveform. This output can be used with DIGITAL
diagnostic software to produce a data base for extremely precise analog linearity testing.
5
INTRODUCTION
DRV11
The DRV11 Is a parallel interface module that Is used
to interconnect the LSI-11 bus with general-purpose,
parallel line TTL or DTL devices. It allows programcontrolled data transfers at rates up to 40K words
per second and uses LSI-11 bus Interface and controllogic to generate interrupts and process vector
handling. The data are handled by 16 dlodeclamped input lines and 16 latched output lines.
There are two 40-pin connectors on the module for
user interface applications.
DRV11-B
The DRV11-B is an interface module that uses direct
memory access (DMA) to transfer data directly
between the system memory and an I/O device. The
interface is programmed by the processor to move
variable length blocks of 8- or 16-blt data words to or
from specified locations in the system memory.
Once programmed, there is no processor Intervention required. The module can transfer up to 250K
16-bit words per second in the single-cycle mode
and up to 500K 16-bit words per second in the burst
mode. It also allows read-modify-restore operations.
DRV11-J
Sixty-four input/output data lines are now available
on a double-height module for the LSI-11 12, LSI11/23, PDP-11 103, and PDP-11 123. The DRV11-J also includes an advanced interrupt structure with bit
interruptability up to 16 lines, programmable interrupt vectors, and program selection of fixed or rotating interrupt priority within the DRV11-J. The
DRV11-J's bit interrupts for real-time response
make it especially useful for sensor 1/0 applications.
It can also be used as a general-purpose interface to
custom devices, and two DRV11-Js can be connected back-to-back as a link between two LSI~11 buses.
DRV11-P
The DRV11-P is a foundation wire-wrap interface
module with a 40-pin 1/0 connector. Approximately
25 percent of the module is occupied by bus transceivers, interrupt vector generation logic, device
comparator logic, protocolloglc,'and interrupt logic.
The remaining 75 percent is for user applications;
this portion has plated-through holes for securing
6
INTRODUCTION
les and wire-wrap pins for Interconnecting the user's
curcuits. The plated-through holes can accept 6-, 8-,
14-,18-,20-,22-,24-, and 40-pln dual-In-line
Integrated circuits or discrete components.
IBV11-A
The IBV11-A Is an Interface module that Interconnects the LSI-11 bus with the instrument bus described In IEEE standard 4881975, "Digital Interface
for Programmable Instrumentation." The IBV11-A
makes a processor-controlled programmable instrument system possible. The module can accommodate up to 15 IEEE-488 devices and Is PDP-11
software-compatible.
KWV11-A
The KWV11-A Is a programmable real-time
clock/counter that provides a means of determining
time intervals or counting events. It can be used to
generate interrupts to the processor at predetermined intervals or establish timing between Input
and output events. It can also Initialize the ADV11-A
analog-to-dlgltal converter by a clock counter overflow or by firing a Schmitt trigger. The clock counter
has a resolution of 16 bits and can be driven by any
one of five crystal-controlled frequencies (100 Hz to
1 MHz), from a line frequency Input, or from a
Schmitt trigger fired by an external Input. The module can operate In any of four programmable modes:
single interval, repeated Interval, external event timing, and external event timing from zero base.
Communications Options
DLV11
The DLV11 is a serial line unit (SLU) that interfaces
with asynchronous serial I/O devices. The module
has jumper-selectable baud rates (50-9600) and serial word format that includes the number of stop
bits, number of data bits, and even, odd, or no parity
bit. The DL V11 can support 20 rnA current loop Interfaces or EIA "data leads only" interfaces.
DLV11-E
The DL V11-E is an asynchronous line interface
module that interconnects the LSI-11 bus to standard serial communications lines. The module receives serial data, converts it to parallel data, and
7
INTRODUCTION
transfers It to the LSI-11 bus. Also, It accepts parallel
data from the LSI-11 bus, converts It to serial data,
and transmits It to the peripheral device. The module
has jumper-selectable or software-selectable baud
rates (50-19,200), and Jumper-selectable data bit
formats. The DL V11-E offers full modem control for
EIA/CCITT Interfaces.
DLV11-F
The DL V11-F Is an asynchronous line Interface module that interconnects the LSI-11 bus to several types
of standard serial communications lines. The module receives serial data, converts It to parallel data,
and transfers It to the LSI-11 bus. It also' accepts
parallel data from the LSI-11 bus, converts It to serial
data, and transmits It to the peripheral device. The
module has jumper-selectable or software-selectable baud rates (50-19,200) and jumper-selectable
data bits. The DL V11-F supports either 20 rnA current loop or EIA standard lines, but does not Include
modem control.
DLV11-J
The DL V11-J contains four Independent asynchronous serial line channels used to Interface peripheral
devices to the LSI-11 bus. Each channel transmits
and receives data from the peripheral device over
EIA data leads (lines that do not use a control line).
The module can be used with 20 mA current loop
devices if a DL V11-KA adapter Is used. The DLV11-J
has jumper-selectable baud rates from 150 to 39.4 K
baud.
DUV11
The DUV11 synchronous line Interface module establishes a data communication line between the LSI11 bus and a Bell 201 synchronous modem or equivalent. The module is fully programmable with
.respect to sync characters, character length (to to 8
bits). and parity selection. The receiver logic accepts
serial data for the LSI-11 bus. The transmitter logic
converts the parallel LSI-11 bus data Into serial data
for the transmission line. The interface logic converts
the TTL logic levels to the EIA voltage levels required
by the Bell 201 modems and also controls the modem for half-duplex or full-duplex operation.
8
INTRODUCTION
OZV11
The OZV11 is an asynchronous mu1tiplexer interface
module that interconnects the LSI-11 bus with up to
four asynchronous serial data communications
channels. The module provides EIA interface voltage
levels and data set control to permit dial-up (autoanswer) options with full-duplex modems such as
Bell models 103, 113, 212, or equivalent. The DZV11
does not support half-duplex operations or the secondary transmit and receive operations available In
some modems such as Bell 202. The OZV11 has applications in data concentration and collection systems where front-end systems interface to a host
computer and for use in a cluster controller for terminal applications.
Expansion Memories (For detailed memory descriptions,
see the Microcomputer Processor Handbook)
MMV11-A
The MMV11-A is a 4K x 16-bit core memory option
that provides nonvolatile read/write storage. The
memory can be configured by bank addressing
switches. The module is limited to LSI-11 bus backplanes that contain the LSI-11 bus In both the A/B
bus and the C/O slots.
MRV11-AA
The MRV11-AA is a read-only memory module on
which the user can install fusible link, programmable, read-only memory (PROM) chips or masked
read-only memory (ROM) chips. The user selects the
address space of the memory by configuring removable jumper wires.
MRV11-BA
The MRV11-BA is a read-only memory module that
uses ultraviolet (UV) erasable, programmable, readonly memory (EPROM) integrated circuits. The module also contains a 256 x 16-bit random access
memory (RAM) that can be used as a "scratchpad"
or "stack" by the system. software.
MRV11-C
The MRV11-C is a flexible, high-density ROM module used with the LSI-11 bus. The module contains
sixteen 24-pin sockets which accept a variety of
user-supplied ROM chips. It will accept masked
ROMS, fusible link PROMs, and ultraviolet erasable
9
INTRODUCTION
PROMs. It accepts several densities of ROM chips
up to and including 4K X 8 chips. Using these highdensity chips gives the module a total capacity of
64K bytes. The contents of the module can be accessed in one of two ways-either directly or window-mapped. Direct access provides total random
access to a" ROM locations on the module. Windowmapping provides two 2K-byte windows in memory
address space to access 2K-byte segments of the
ROM array. The segments that are viewed through
each window can be varied under program control.
MSV11-B
The MSV11-B is a 4K x 16-bit dynamic MaS
read/write memory module. The user can select the
memory addresses of the module by configuring removable jumpers. The memory refresh must be controlled by external bus signals.
MSV11-CD
The MSV11-CD is a 16K X 16-bit dynamic MaS
read/write memory module. Refresh Is automatically
performed by the module but It can be disabled if the
user wishes to use the LSI-11 bus refresh signals.
This memory module can be configured to operate
in the battery backup mode. The user can configure
the memory addresses by selecting switch settings.
MSV11-D,-E
The MSV11-D module has either 8K, 16K, or 32K X
16 bits of MaS memory. The MSV11-E Is the same
as the MSV11-D except that It has an 18-bit word
that generates and detects byte parity for each word.
The modules have an on-board memory refresh and
perform the necessary LSI-11 bus cycles. The memory addressing is selectable by the user by configuring switch settings. The module can use a battery
backup system to preserve data when primary
power is lost.
MXV11-A
The MXV11-A Is a dual height multifunction option
module for the LSI-11, LSI-11 /2 or LSI-11 /23. It contains a read/write memory, provisions for read-only
memory, two asynchronous serial line interfaces and
a 60 Hz clock signal derived from a crystal oscillator.
Read/write memory Is supplied with either 8K or 32K
bytes (4K or 16K words). Two 24-pln sockets are
10
INTRODUCTION
provided for +5 Vread-only memories. 1K X 8, 2K x
8, or 4K X 8 ROMS may be used. The sockets may
also be used for 256 words of bootstrap code. The
two asynchronous serial lines transmit and receive
EIA-423 signal levels from 150 baud to 38.4K baud.
20 mA active or passive current loop operation at
110 baud may be obtained with the DLV11-KA EIA to
20 mA converter option. The serial lines will not support the reader run function of the DLV11-KA option.
The serial lines provide error Indicator bits for overrun error, frame error, and parity error, but do not
have modem controls. Serial line 1 may be configured to respond to a break signal. The serial lines
have signal level Interrupt logic and should be
placed after multi-level devices on an LSI-11/23 system. Serial line 1 may be used as a console port, or,
along with serial line 0, may be used with any of
several standard types of serial communication devices. The 60 Hz clock signal can be selected by a
wirewrap Jumper to provide line-time clock Interrupts on the bus.
Peripherals
LAV11
The LAV11 option consists of an LA 180 DECprlnter,
an interface module, and a BC11 S-25 Interface cable. The interface module provides Interconnection
between the LA 180 DECprlnter and the LSI-11 bus.
The module outputs ASCII characters to the printer
and monitors various printer operations that require
operator control.
LPV11
The LPV11 printer option consists of an Interface
module, an Interface cable, and either an LP05 or
LA 180 line printer. The Interface module provides
programmed control of data transfers and provides
printer strobe signals appropriate for either printer.
The LA 180 DECprlnter Is a high-speed printer that
prints 180 characters per second and the LP05
printer can print 240 or 300 lines per minute, depending on which model Is selected.
11
INTRODUCTION
RKV11-0
The RKV11-0 option consists of an RK05 disk drive
controller, an LSI-11 bus Interface module, and an
RK05J disk drive. The RK05 disk drive controHer can
be used with up to eight RK05J disk drive units to
form a mass memory storage system that contains
up to 21 M bytes of storage. The RKV11-D system Is
block-oriented but is capable of transferring from 1
to 218 consecutive data words without reinitiation or
processor Intervention. The data transfers occur
from the RKV11-D to the system memory by direct
memory access (DMA) and operate at maximum bus
bandwidth. The system can use either RK05J or
RK05F disk drives and the controller can be mounted In a standard 48.3 cm (19 In.) cabinet.
RLV11
The RLV11 option interfaces the LSI-11 bus with an
RL01 disk drive controller and an RL01 disk drive
assembly. The controller can only be used In an
H9273-A type backplane which Incorporates an LSI11 bus in slots A and B, with an Interboard bus In
slots C and D. The controller can Interface up to four
RL01 disk drives for a complete system of 21 M bytes
of storage. The RL01 disk drive Is a random access,
mass storage system that stores data in fixed length
blocks on a preformatted disk cartridge. Each drive
can store up to 5.24 million bytes and the complete
system can store u~ 21 million bytes. The RLV11
transfers data using direct memory access (DMA)
techniques; this allows data t.r~nsfers without processor Intervention and at busjbandwldth speed.
RXV11
The RXV11 option consists of an interface module,
cable assembly, and either a single or dual drive
RX01 floppy disk. This option is a random access
mass storage device that stores data in fixed-length
blocks on a preformatted flexible diskette. Each
diskette can store and retrieve up to 256K, 8-bit
bytes of data. The RXV11 system Is rack mountable
in the standard 48.3 cm (19 In.) cabinet.
RXV21
The RXV21 floppy disk option Is a random access
mass memory device that stores data In fixed-length
blocks on a preformatted, flexible diskette. Each
12
INTRODUCTION
diskette can store and retrieve up to 512K 8-bit bytes
of data. The RXV21 system is rack-mountable and
consists of an Interface module, an interface cable,
and either a single or dual RX02 floppy disk drive.
The interface module converts the RX02 1/0 bus to
the LSI-11 bus structure. It controls the RX02 interrupts to the processor, decodes device addresses
for register selection, and handles the data interchange between the RX02 and the processor via
DMA transfers. Power for the Interface module is
supplied by the LSI-11 bus.
TU58
The TU58 Is a low-cost intelligent mass memory device that offers random access to block-formatted
data on pocket-size cartridge media. It is Ideal as a
small computer systems device, as inexpensive archive mass storage, or as a software update distribution medium. A dual drive TU58 offers 512 Kb of
storage space, making it one of the lowest cost complete mass storage su bsystems available. For
mounting flexibility, the TU58 Is offered both as a
component level subsystem and as a fully powered
5%" rack-mount subsystem.
VK170-CA
The VK170 module forms an integral part of a terminal. The module accepts serial ASCII encoded data
to be stored in a refresh memory to generate a display for a video monitor. The VK170 also accepts
parallel data from a keyboard (on strobe demand) to
generate serial ASCII output. The VK170 is an extended-length, double-height, single-width board.
Mounting holes are provided for stand-off mounting
via handle rivets and two holes located near the
module fingers.
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INTRODUCTION
Backplanes
The four backplane options available for the LSI-11 bus are presented
in the following paragraphs.
H9270
A 4 X 4 (four rows of four slots each) backplane with
card guide assembly. LSI-11 bus in rows A-B and CD. Accepts 8 double-height modules or 4 quadheight modules or combinations of both.
H9273-A
A 9 X 4 (nine rows of four slots each) backplane with
card guide assembly. LSI-11 bus in rows A-B only.
Special interconnect bus in rows C-D.A ccepts double-height or quad-height modules.
H9281
A 2-slot backplane available In 4-, 8-, or 12-slot options. Accepts double-height modules only.
DDV11-B
A 9 X 6 (nine rows of six slots each) backplane. LSI11 bus in rows A-B and C-D. Rows E-F are unbussed
except for +5V and ground. Accepts 18 doubleheight or 9 quad-height modules or combinations of
both.
Enclosures
H909-C
A 13.3 cm (5.25 in.) high, 48.3 cm (19 In.) wide enclosure which can be mounted in a 48.3 cm (19 In.) rack
or as a stand-alone. Accommodates the DDV11-B
backplane or a 9 X 6 system mounting unit or
houses non-standard mounting arrangement. Includes cooling fan, cord guide, cable restraints, front
bezel, and connector block.
BA11-M
A 8.9 cm (3.5 in.) high, 48.3 cm (19 in.) wide expansion box which can be mounted in 48.3 cm (19 in.)
rack. Includes H9270 backplane, H780 power supply, blank front panel or bezel, and cooling fan.
BA11-N
A 13.2 cm (5.19 in.) high, 48.3 cm (19In.) wide
mounting box which can be mounted in a 48.3 cm
(19 in.) rack. Includes H9273-A backplane, H786
power supply, H403-A ac input panel, blank front
panel or bezel, and cooling fan.
14
INTRODUCTION
BA11-VA
The BA 11-VA Is a small form-factor package providIng mounting space and power for four LSI-11 /2 or
LSI-11 /23 family modules. This package, plus the
high functionality of DIGITAL's microcomputer products, allows LSI-11 microcomputer applications to
be implemented within a space smaller than that required for many 8-blt systems.
Cabinets
H984-B
A low-profile cabinet with four casters. Provides
mounting space for standard 48.3 cm (19 in.) panels
and enclosures In rack at front or rear. Includes distribution panel (115 Vac, 230 Vac)
H9800-A
A low-profile system desk with casters. Provides
mounting space for standard 48.3 cm (19 In.) panels
and enclosures. Includes distribution panel (115
Vac, 230 Vac)
Power Supplies
H780
Provides +5V ±4%, 18 A (max) and + 12V ± 3%, 3.5
A (max) at 110 Vac and features line-time clock, and
power-fail/automatic restart. Available primary
power of 115 or 230 Vac and with or without master
and slave console .
.Cables and Connectors
Various preassembled cables in different lengths are
available for use with interface and communications
options. See Appendix C for commonly used cables.
Wlre-Wrappable Modules
W9500 Series: LSI-11 Bus-Compatible Wlre-Wrappable Modules
(W9511, W9512, W9514 AND W9515) - The LSI-11 bus-compatible
wire-wrappable modules consist of quad-height and double-height
modules. Two LSI-11 bus-compatible modules are available without
DIP sockets.
W9511
Quad-height, extended-length, single-width
module with extractor handle. No DIP sockets included. One 40-pin male cable connector premounted on board and space for
additional 40-pln connector provided.
15
INTRODUCTION
Power and ground connections are
V-AA2, BA2, CA2, DA2
GND-AT1, BT1, CT1, DT1, AC2, BC2, CC2,
DC2
W9514
Same as W9511 except with 58 pre-mounted DIP sockets.
Power and ground connections are the
same as W9511
W9512
Double-height, extended-length, singlewidth module with Flip-Chip handle. No DIP
sockets Included. One 40-pln male connector premounted on board.
Power and ground connections are
GND-AT1, BT1,AC2, BC2
W9515
Same as W9512 except with 25 pre-mounted 01 P sockets.
Power and ground connections are the
same as W9512
Integrated Circuits
DCK11-AA, The DCK11-AA and -AC CHIPKITs provide the logic
necessary for a program transfer interface to the
AC
LSI-11 bus. The DCK11-AA kit contains one DC003
Interrupt Chip, one DC004 Protocol Chip, and four
DC005 Transceiver/Address Decoder/Vector Select
Chips. The DCK11-AC kit contains previous chips
plus one W9512 double-height, extended length,
high-density wire-wrappable module and one
BC07D-10 ten-foot, 40-connector plug-in cable.
DCK11-AB, AD
The DCK11-AB and -AD CHIPKITs provide the logic
necessary for a Direct Memory Access (DMA) interface to the LSI-11 bus. The DCK 11-AB. The DCK 11AB kit contains one DC003 Interrupt Chip, one
. DC004 Protocol Chip, four DC005 Transceiver/Address Decoder/Vector Select Chips, two
DC006 Word Count/Bus Address Chips, and one
DC010 DMA Control Chip. The DCK11-AD kit contains the previous chips plus one W9512 doubleheight, extended-length, high-density wire-wrappa16.
INTRODVCTION
ble module and one BC07D-10 ten-foot, 40-connector plug-in cable. DMA applications use the same
chips as program control interfaces, plus two
DC006s for word or byte address counters and a
DC010 DMA buscontrollC.
Miscellaneous Options
BDV11
The BDV11 module has 2K words of read-only memory (ROM) that contains diagnostic and bootstrap
programs. These programs are user-selectable by
setting dip switches. The diagnostic programs will
test the processor, the memory, and the user's console. The bootstrap programs can boot most LSI-11
peripheral devices. The module also has 120-ohm
bus terminator circuits.
The user can add up to 16K of read-only memory
(ROM) and up to 2K words of erasable programmable ROM (EPROM) on the module. This 18K
words of additional memory can be used with no
Increase in the amount of 1/0 address space.
KPV11-A, -B,
-C
The KPV11-A module generates power-up and
power-down sequences, monitors for a power-fall
condition, and generates the line-time clock (LTC)
function. The KPV11-B Is the same as the "A" except
that it provides 120-ohm termination circuits. The
KPV11-C Is the same as the "A" except that It provides 220-ohm termination circuits. The module can
be Installed on any backplane or remotely installed
via an optional cable.
REV11-A, -C
The REV11-C module has a bootstrap ROM and
direct memory access (DMA) refresh circuits. The
REV11-A is Identical to the REV11-C except It has
additional 120-ohm termination circuits.
TEV11
!"
The TEV11 Is a bus terminator module that provides'
120-ohm bus termination circuits.
17
Table 1
Option
Deslg.
Module
No(s).
AAV11-A
A6001
ADV11-A
A012
Module Specifications
Power Requirements
Bus Loads*
+5V
±5%
+ 12V
±3%
AC(Max)
4-channel,12-blt
01 A converter
1.5A
0.4A
1.9
Quad
16-channel, 12-blt
2.0A
0.45 A
3.25
Quad
1.6A
0.07 A
2.0
Quad
Description
DC
Size
AID converter
BDV11
MB012
.....
Q)
DDV11-B
DLV11
M7940
DLV11-E
MBOH
DLV11-F
DLV11-J
Bootstrap,
terminator,
diagnostic
6 x 9 backplane
Asynchronous serial
line Interface
Z
.....
::D
0
C
C
0
1.0A
0.18A
6.4
2.5
Asynchronous line
Interface
1.0 A
0.1BA
1.6
Double
MB02B
Asynchronous line
Interface
1.0A
0.1BA
2.2
Double
MB043
4 asynchronous
serial Interfaces
1.0A
0.25 A
Double
n
:::!
0
Z
Double
* These ac load figures were measured using standard TOR (time domain reflectometry) techniques. The conversion factor Is 9.35 pF/ac
load. These numbers are nominal values which will tend to vary from module to module due to normal tolerances of components used In
the manufacturing of the product.
Table 1
Option
Oeslg.
Module
No(s).
Description
Module Specifications
Power Requirements
+12V
+5V
±5%
±3%
Bus Loads·
AC(Max)
DC
Size
DRV11
M7941
Parallel line unit
interface
0.9A
1.4
Double
DRV11-8
M7950
DMA Interface
1.9A
3.3
Quad
DRV11-J
M8049
64-lIne parallel 1/0
1.6A
1.8A
2.0
Double
2.1
Quad
DRV11-P
M7948
Foundation
module
1.0A
+ user logic
DUV11
M7951
Synchronous serial
line interface
0.86 A
0.32
1.00
Quad
DZV11
M7957
Asynchronous
line Interface
1.15A
0.39 A
3.95
Quad
-"
(0
H9270
4 X 4 backplane
5.1
0
H9273
4 x 9 backplane
2.6
0
H9281A
2 x 4 backplane
1.3
0
H92818
2 x 8 backplane
2.4
0
....::DZ
0
C
C
,n
:!
0
Z
* These ac load figures were measured using standard TOR (time domain reflectometry) techniques. The conversion factor is 9.35 pF/ac
load. These numbers are nominal values which will tend to vary from module to module due to normal tolerances of components used In
the manufacturing of the product.
Table 1
Option
Deslg.
Module
No(s).
Power Requirements
Bus Loads·
+5V
±5%
AC(Max)
DC
3.6
0
+ 12V
±3%
2 X 12 backplane
H9281C
I\)
Description
Module Specifications
IBV11-A
M7954
Instrument bus
Interface
0.8 A,
KD11-F
M7264
LSI-11 CPU with
4KRAM
1.8A
KD11-H
M7264-YA
LSI-11 CPU
without RAM
KD11-HA
M7270
KDF-11
Size
-Z
1.9
Double
0.8A
2.4
Quad
1.6A
0.25A
2.4
Quad
LSI-11/2 CPU
1.0A
0.22A
1.7
Doubl~
n-I
M8186
LSI-11/23 CPU
2.0A
0.2A
2.0
KPV11-A
M8016
Power-faillllnetime clock
0.56 A
1.63
Double
Double
0
Z
KPV11-B
M8016-YB
Power-fall/llnetime clock/120 n
bus terminator
0.56 A
1.63
Double
0
-I
::D
0
C
C
-
* These ac load figures were measured using standard TOR (time domain reflectometry) techniques. The conversion factor is 9.35 pF/ac
load. These numbers are nominal values which will tend to vary from module to module due to normal tolerances of components used in
the manufacturing of the product.
Table 1
Option'
Deslg.
KPV11-C
I\)
Module
No(s).
MS016-YC
Module Specifications
Power Requirements
Description
Power-fall/llnetime clock/220 n
bus terminator
+5V
±5%
+ 12V
±3%
0.56 A
Bus Loads*
AC(Max)
DC
Size
1.63
Double
3.4
Quad
KUV-11
MS01S
WCSmodule
3.0A
KWV11-A
M7952
Programmable
real-time clock
1.75A
LAV11
M7949
LA 1S0 line printer
Interface
O.SA
1.S
Double
0
LPV11
MS027
LA1S0/LP05
printer Interface
O.SA
1.4
Double
n
MMV11-A
G653
4KX 16 core
memory
(standby current)
(operating current)
~
MRV11-AA
M7942
4K X 16 read-only
memory (less
PROM Integrated
circuits)
Quad
0.01A
1.91
3.0A
7.0A
0.4AA
2
Quads
Z
-I
::D
0
C
~
0
Z
0.2A
0.6A
1.8
Double
* These ac load figures were measured using standard TOR (time domain reflectometry) techniques. The conversion factor Is 9.35 pF/ac
load. These numbers are nominal values which will tend to vary from module to module due to normal tolerances of components used in
the manufacturing of the product.
Table 1
Option
Deslg.
MRV11-BA
Module
No(s).
MS021
I\;)
I\;)
Description
Module Specifications
Power Requirements
Bus Loads·
+5V
±5%
AC(Max)
(with 32512 X 4
PROM Integrated
clrcuts)
(MRV11-AC)
2.SA
UVPROMRAM (less PROM
Integrated circuits)
O.5SA
(with 81KXS
PROM Integrated
circuits)
(MRV11-BC)
0.62 A
+12V
±3%
DC
Size
-....
Z
0.34 A
2.8
Double
:II
0
C
C
n
O.5A
....
(5
Z
MRV11-C
M8048
PROM/ROM module
O.SA
MSVll-B
M7944
4K X 16 read/write
MOSmemory
0.6A
MSVll-CD
M7955-YD
16K X 16 read/write
MOSmemory
1.1 A
2.0
Double
0.54 A
1.9
Double
0.54 A
2.3
Quad
• These ac load figures were measured using standard TOR (time domain reflectometry) techniques. The conversion factor Is 9.35 pF/ac
load. These numbers are nominal values which will tend to vary from module to module due to normal tolerances of components used in
the manufacturing of the product.
Table 1
Option
Deslg.
I\J
w
Module
No(s).
Description
Module Specifications
Power Requirements
Bus Loads*
+5V
:5%
+12V
:3%
AC(Max)
DC
Size
MSV11-D
MS044
4K/16K/32K
MOSmemory
1.7 A
0.34 A
2.0
Double
MSV11-E
MS045
4K/16K/32K
MOSmemory
2.0A
0.41 A
2.0
Double
MXV11-A
MS047
Multifunction module
1.2A
0.1A
2.0
REV11-A
M9400-YA
120 n terminator,
DMA refresh,
bootstrap ROM
1.6A
2.2
2
Double
Double
REV11-C
M9400~YC
DMA refresh,
bootstrap
1.6A
2.2
Double
RKV11-D
M7269
LSI-11 Bus control
for RKV11-D
1.SA
1.9
Double
RLV11
MS013
MS014
RL01 disk
drive
6.5A
3.2
2 Quads
1.0A
-...Z
::II
0
0
C
n
:::!.
0
Z
* These ac load figures were measured using standard TOR (time domain reflectometry) techniques. The conversion factor Is 9.35 pF/ac
load. These numbers are nominal values which will tend to vary from modute to module due to normal tolerances of components used In
the manufacturing of the product.
Table 1
Option
Deslg.
Module
No(s).
Module Specifications
Power Requirements
Description
+ 5V
+ 12V
±5%
±3%
Bus Loads·
AC(Max)
DC
Size
RXV11
M7946
RX01 interface
1.5A
1.8
Double
RXV21
N8029
Double density
floppy Interface
1.1A
2.0
Doublel
TEV11
M9400-YB
120 n terminator
0.5A
0
Serial/cartridge
cassette
0.75
Appr.
1.2A max
Serial video module
1.2A
0.15
TU58
0
Double
VK170
CAM7142
~
:II
0
I\J
.:=.
-Z
Double
C
C
n
::!
0
z
*
These ac load figures were measured using standard TOR (time domain reflectometry) techniques. The conversion factor is 9.35 pF/ac
load. These numbers are nominal values which will tend to vary from module to module due to normal tolerances of components used in
the manufacturing of the product.
INTRODUCTION
CONFIGURATION
The LSI-11 bus permits a unified addressing structure in which controllstatus and data registers for peripheral devices are directly addressed as memory locations. All operations on these registers, such
as transferring informaton to or from them or manipulating data within
them, are performed by normal memory address instructions. The use
of memory address instructions on peripheral device registers greatly
Increases the flexibility of input/output communications.
Addresses
All the options except memories have at least one control and status
register and may have several data registers. Each register Is assigned
an address through which the option can communicate with the processor. The upper 4K of memory address space is reserved for the
processor and external input/output (110) registers. The user can select any address (Appendix A) In the range of 160000 through 177776
and assign it to the option interface module. The modules are
configured to the desired address by selecting dip switches, connecting or disconnecting wire-wrap pins, or installing or removing wired
jumpers on the module.
25
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I*ENSIDIIS DENDTED II\' • AIlE FOR
MAX USEA8.£ CIRQIJT AREA,
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219
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lOTOPCWIWIIL£
8.M! OI0(£XT LOTH)
5.50!.DfO (STD LOTH)
061
fOlD
7451,.
(DUlllH)
~
a.430~·010
(EXT.LGTIl)
"'~
-1
- - - ---+
+
1_
10.312 •
(QUAD. HIlT)
--~I--~
I
- :
'.958.
(StD, LIllH)
:l
I
:
I
:
I
!
:
I
:
I
:
I
I:
I
Figure 1
Module Dimensions
1
:.J
~
*J~ ~:
~~a75
~w.L:I ~;,..
z
....
:D
o
C
C
n
::!
o
z
INTRODUCTION
Control and Status Registers
The general form for the control and status registers, shown In Figure
2, does not necessarily apply to every device, but Is presented as a
guide.
15
12
11
10
8
7
6
5
4
o
3
T
T
ERRORS
DONE
OR
READY
INTERRUPT
ENABLE
BUSY
Figure ~
DEVICE
FUNCTION
ENABLE
Control and Status Registers
Many devices require less than 16 status bits. Other devices will require more than 16 and therefore will require additional status and
control registers.
The bits in the control and status registers are generally assigned as
described below.
Typical Control and Status Register
Bit: 15-12 Name: Errors
Function: Generally there Is an Individual bit associated with a specific error. When more bits are required for errors, they can be obtained by expanding the error section In the word or by using another
status word. Generally bit 15 Is the Inclusive-OR of all other error bits
(If there Is more than one). Most devices will have "hard" error
conditions which will cause an Interrupt If bit 61s set. Some may also
have "soft" errors (warning types) which do not cause Immediate Interrupts.
Bit: 11
Name: Busy
Function: Set to indicate that a device operation Is being performed.
Bit: 10-8 Name: Unit Select
Function: Some peripheral systems have more than one device per
control. For example, a disk system can have multiple surfaces per
control and an analog-to-dlgltal converter can have multiple channels.
The unit bits select the proper surface or channel.
27
INTRODUCTION
Bit: 7
Name: Done or Ready
Function: The register ~an contain a done bit, a ready bit or a donebusy pair of bits, depending on the device. These bits are set and
cleared by the peripheral device, but may be queried by the program
to determine the availability of the device.
Bit: 6
Name: Interrupt Enable
Function: Set by the program to allow an interrupt to occur as a
result of a function done or error condition.
Bit: 5-4
Name: Memory Extension
Function: Allows devices to use a full 18 bits to specify addresses on
the bus.
Bit: 3-1
Name: Device Function Bits
Function: Specifies the operation that a device Is to perform.
Bit: 0
Name: Enable
Function: Set to enable the device to perform an operation.
Data Buffer Registers
The data buffer register Is used for temporarily storing data to be
transferred into or out of the computer. The number and type of data
registers is a function of the device.
Interrupts
Interrupts are requests, made by peripheral devices, which cause the
processor to temporarily suspend Its present (background) program
execution to service the requesting device. Each device that Is capable
of requesting an Interrupt must have a user-supplied service routine
that is automatically entered when the processor acknowledges the
Interrupt request. After completing the service routine execution, program control Is returned to the Interrupted program. This type of operation Is especially useful for the slower peripheral devices.
A device can Interrupt the processor only when Interrupts are enabled
and services Interrupts only when the appropriate PSW bits are
cleared. Device priority Is highest for devices electrically closest to the
processor along the bus. Any device that can Interrupt the processor
can also Interrupt the service routine execution of a lower priority
device if the processor's priority Is set during the execution; hence,
Interrupt nesting to any level Is possible with this Interrupt structure.
Each device normally contains a control/status register (eSR), which
Includes an interrupt enable bit. A program must set this bit before an
Interrupt can be generated by the device.
28
INTRODUCTION
Interrupt Vectors
An interrupt vector associated with each device is hard-wired into the
devices's interface/controllogic. This vector Is an address pOinter that
is transmitted to the processor duing the interrupt acknowledge sequence, allowing automatic entry into the service routine without device polling. The user can select an interrupt vector from the range of
000 to 777 for any interrupting options. The module can be configured
to the desired interrupt vector by either selecting dip switches, connecting or disconnecting wire-wrap pins, or installing or removing.
wired jumpers on the module.
29
I
I
I
31'
AAV11-A
AAV11-A 4-CHANNEL 12-BIT D/A CONVERTER
GENERAL
The AAV11-A is a 4-channel, digital-to-analog converter module that
includes control and interfacing circuits. It has four 0/ A converters, a
dc-dc converter that provides power to the analog circuits, and a
precision voltage reference. Each channel has Its own holding register
that can be addressed separately and provides 12 bits of resolution.
These registers can be written and read, using either word or byte
format. In addition, bits 0, 1, 2, and 3 of the fourth holding register are
brought out to the I/O connector so they can be used as a 4-bit digital
output register.
FEATURES
• Four 12-bit digital input channels, binary encoded for either unipolar
mode or bipolar mode.
• Jumper-selected output ranges and modes:
Bipolar mode ±2.56 V, ±5.12 V, ±10.24 V
Unipolar mode 0 to +5.12 V, 0 to +10.24 V
• One part in 4096 resolution
• 5V / itS slew rate
• ±5 mA drive capability per converter
SPECIFICATIONS
Identification
A6001
Size
Quad
Power
+5.0 Vdc ±5% at 1.5 A
+ 12.0 Vdc ±3% at 0.4 A
Bus loads
AC
1.9
1.0
DC
Resolution
12-bits (1 part in 4096)
Number of 0/A converters
4
Digital input
12-bits (binary encoded for unipolar mode; offset binary encoded for bipolar mode)
Digital storage
Read/write, word or byte operable, single buffered
33
AAV11-A
Output voltage range
(jumper selected)
±2.S6 V, ±S.12 V, ±10.24 V bipolar, 0 V to +S.12 V, 0 V to +10.24
V unipolar
Gain accuracy
Adjuatable (factory set for bipolar
±S.12 V)
Gain temperature coefficient
10 PPM per °C, max.
Offset temperature coefficient
20 PPM of full scale range per °C,
max.
Linearity
± 1f2 LSB max, non-linearity
Oifferentiallinearity
± 1f2 LSB, monotonic
Output impedance
1 ohm max.
Drive capability
±6 mA max. per converter
Slewing speed
S V/Jls
Rise and settling time (to 0.1 % of
final value)
4 JlS (8 JlS wth SOOO pF load in
parallel with 1 kO
DESCRIPTION
General
The function of the AAV11-A module is to convert digital data input to
an analog de voltage output that is representative of the input. This Is
accomplished by the bus interface, the control logic, and the Of A
converter functions as shown in Figure 1.
34
----raU;"C;TROL
I
I
~
~-,,-"
I
LL~-J
I
t...-"1IW
..
IJ
~/I__ .
L... _ _ _ _ _ _ _ _
(.)
I
I
BSYNC L. BDOUT L. BDIN L. BWTBT L
L ______ _ .-II
U'I
'------,I
.~
r;;"'AC 1 a 2
I (SAME AS DAC01
IL ___ _
......<
I
~
j.
-1.-
L ______________
~
READ DAC 3 H
11-00
READ OAC 3 L
T T
WROAC3H
I,!!T
I
Figure 1
AAV11-ABlockDlagram
~/i
U!;~
I
I
; I
I
'%
L ______ ~---:J
AAV11·A
Bus Interface
The logic associated with the bus Interface section maintains proper
communications protocol between the processor lSI-11 bus and the
AAV1 1-A. This logic generates and monitors the bus signals Involved
during data transfers between the processor and the AAV11-A,
permitting the AA V11-A to recognize when it Is being addressed by
the processor (address defined by setting on the address switch pack)
to accept Input data from the processor, and to output data to the
processor.
Control Logic
The AA V11-A has no control/status register. The four digltal-to-analog
converters continually generate voltages at their outputs that reflect
whatever digital values have most recently been written Into their respective holding registers. The role of the control logic Is to make the
necessary discriminations between requests to change the state of the
holding registers (I.e., to write Into the holding registers), and requests
to put the holding register contents onto the BD lines where they can
be picked up through the transceivers by the processor.
DACs 0,1, and 2
Dlgital-to-analog conversion functions are performed In each of the
four AAV11-A channels by Identical circuits:
• a holding register which stores the digital value output by the processor
• a dlgltal-to-analog converter (DAC) proper which generates a current that Is a function of the holding register value and of the
modellevel jumper conditions
• an amplifier that translates the current Into a proportional voltage,
provides a low output Impedance for the channel, and permits adjustment of signal offset
DAC3
DAC 3 Is Identical to DACs 0, 1, and 2 except that holding register bits
0-3 are routed to the 110 connector as well as to the DAC. This arrangement permits these bits to be routed to external equipment that
requires binary control signals at programmable Intervals. Control data In these bit pOSitions affects any 12-blt 01 A conversion that they
coincide with, but since they Involve the least significant bits of the
word, the worst-case error Is less than 0.5 percent. Consequently,
DAC 3 can be used as a 12-blt DAC or as an 8-blt DAC plus four output
bits for CRT IntenSify, Store, Non-Store, Erase, etc.
36
AAV11-A
CONFIGURATION
General
This section describes how the user can configure the module to function within his system by setting dip switches (Figure 2) to obtain the
desired device address. The voltage range for each 01 A converter
(OAC O-OAC 3) can be configured independently by installing or
removing the designated jumpers (Figure 2) associated with a specific
01 A converter. This section also describes how to connect external
devices to the module. The standard factory addresses for the
registers are listed in Table 1.
Table 1
Standard Addresses
Register
Mnemonic
Address
Holding 0
Holding 1
Holding 2
Holding 3
OACO
OAC1
OAC2
OAC3
170440
170442
170444
170446
37
AAV11-A
OAC0
c
JI
1
OAC I
DO
I
Rl
(OFFFETI
OAC 0
DO DODD
~34
Ri
(GAIN) (OFFSET)
II
0---0 0---0
W4
we
~5
Oo-CI
W9
i\
II
Ris
\37 (GAIN)
(GAINHGAIN) (OFFSET0-
II
OAC I
~ ~.!!1- ~
W6
OAC3
OAC2
OAC 2
~..!!!.!...
RO:C(O:FST
.!!!.. ~
0----.0 0----.0
WI3
WI4
WI7
WI6
MODE I LEVEL STRAPS
BIT 3
\
BIT"
SI
/
c=J
(ADDRESS)
Figure 2
AAV11-A Connectors, Switches, and Jumpers
Device Registers
The device registers can be configured to respond to any address
within the range 170000 to 177777. Each register address does not
have to be individually set. The DAC 0 register address is selectable
and the last digit will be zero. The remaining registers will use addresses 17XXX2, 17XXX4, and 17XXX6 for DAC 1, DAC 2, and DAC 3
registers, respectively. The factory-configured device address is
170440 as shown in Figure 3. The word formats for the DAC registers
are described in Table 2. Note that all device registers are always a
sequence of four consecutive even locations. There is no vector used
for this module.
D/A Converter Range and Mode
The range and mode (bipolar or unipolar) voltages can be selected by
the user inserting or removing jumpers as shown in Figure 2. Four
jumpers are associated with each D/A converter. The module is facto~
38
AAV11-A
ry-configured for -5.12 to +5.12 V bipolar operation. The jumper
configuations for the bipolar mode ranges are shown In Table 3; the
unipolar ranges are shown in Table 4.
I :', :4, ',' , :' 1~ 1"I : 171 : 1:'17, : 1: 1"I"I"I~~..
I I II I I I I I
+ * + + +L ! ! i
I I I I I I I I I' I
STANDARD ADDRESS
CONFIGURATION
OFF
(1704401
~~~RESS
SWITCH
9
OFF
OFF
ON
OFF
OFF
ON
OFF
8
7
8
8
4
3
2
OFF
LOGICAL 1 ~ ON
LOGICAL 0 DOFF
MR·0866
Figure 3
Table 2
Address Selection
DAC Word Formats
Bit
DACO, DAC1, DAC2
DAC3
15-12
11
10
9
8
7
6
Not used
Binary 11
Binary 10
Binary 9
Binary 8
Binary 7
Binary 6
Binary 5
Binary 4
Binary 3
Binary 2
Binary 1
Binary 0
Not used
Binary 11
Binary 10
Binary 9
Binary 8
Binary 7
Binary 5
Binary 5
Binary 4
Binary 3/Control 3
Binary 2/Control2
Binary 1/Control1
Binary O/Control 0
5
4
3
2
1
o
39
AAV11-A
Table 3
Jumper Configurations for Bipolar Operation
±2.S6V
±S.12V
±10.24 V
IN
OUT
IN
IN
IN
OUT
OUT
IN
OUT
IN
OUT
IN
IN
OUT
IN
IN
IN
OUT
OUT
IN
OUT
IN
OUT
IN
IN
OUT
IN
IN
IN
OUT
OUT
IN
OUT
IN
OUT
IN
IN
OUT
IN
IN
IN
OUT
OUT
IN
OUT
IN
OUT
IN
DAC1
W3
W4
W5
we
DAC2
W7
W8
W9
W10
DAC3
W11
W12
W13
W14
DAC4
W15
W16
W17
W18
40
AAV11-A
Table 4
Jumper Configurations for Unipolar Operation
OV-+S.12V
OV-+10.24V
DAC1
W3
W4
W5
W6
IN
IN
OUT
OUT
OUT
OUT
DAC2
W7
W8
W9
W10
IN
IN
OUT
OUT
OUT
OUT
DAC3
W11
W12
W13
W14
IN
IN
OUT
OUT
OUT
OUT
DAC4
W15
W16
W17
W18
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
J1 Output Connections
Analog output devices such as oscilloscopes may be either grounded
or floating. If the oscilloscope Is grounded, either through Its power
plug or through contact between Its chassis and a grounded cabinet,
the oscilloscope ground should not be connected to any of the AAV11A ground pins. Doing so may result In a ground loop which will adversely affect oscilloscope control results as well as ADV11-A operation (if used). If the OSCilloscope Is floating, Its ground should be con41
AAV11-A
nected to the AAV11-A logic ground, J1 pins L, N, R, or T. Note that the
foregoing assumes that the LSI-11 power suppy ground is connected
to power line (earth) ground. If continuity checks reveal no such
connection, attach a length of 12-gauge wire between the power supply ground and a convenient point associated with earth ground.
Oscilloscope X and Y inputs may be either differential or single-ended.
Differential inputs should be driven as in Figure 4.
J1
M
w
AA
CC
EE
OAC I HQ GNo
oAC 2 HQ GNo
OAC 3 HQ GNO
-15V TEST
+15V TEST
OAC 0 HQ GNo
HH
KK
MM
DO
BIT 3 OUT
FF
BIT 2 OUT
JJ
BIT lOUT
LL
BIT 0 OUT
NN
oAC 3 OUT
PP
SS
RR
UU
VV
TT
oAC 2 OUT
oAC lOUT
OAC 0 OUT
BOARO SlOE
Figure 4
Connection to Oscilloscope with Differential Input
When oscilloscopes with single-ended Inputs are Involved, the AAV11A analog grounds (pins UU and H_H) are not used. The return path for
X and Y signal currents Is through ground for a grounded oscilloscope
or through logic ground (pins L, N, R, or T) for a floating oscilloscope.
Since the grounded, single-ended oscilloscope receives an input voltage which Is the sum of the AAV11-A output and the ground difference
voltage between the oscilloscope and the AAV11-A, noise and line
frequency er~ors may be minimized by plugging the oscilloscope Into
an ac socket as close as possibie to the LSI-11 system. Running single-ended oscilloscopes in a floating configuration will eliminate noise
42
AAV11·A
and line frequency errors which are due to ground voltage differences.
The effect of magnetic coupling into the oscilloscope Input lines can
be minimized for a differential-Input oscilloscope by running the
AAV11-A output and its return line In a twisted pair. No benefit Is
derived from a twisted pair with a single-ended oscilloscope Input.
The effect of electrostatic coupling Into the oscilloscope Input lines
can be minimized by shielding the Input lines from AAV11-A to the
oscilloscope. The shield should be connected to ground at one end
only. Grounding the shield at both ends may result in a ground loop
which will adversely affect oscilloscope control results and any
ADV11-A AID operations (If used).
Careful selection of cabling is essential. The 0/A outputs are capable
of driving a maximum of 5000 pF. Output Impedance is 1 ohm. Output
current limit is 5 rnA.
Optional Equipment
Figure 5 iIIustrat~s the H854 40-pin connector pin aSSignments for
user outputs. These pins may be connected to the optional H322 distribution panel for convenient user access via an optional BC08R
cable. The optional BC04Z is available for applications which require
an unterminated cable. One end is terminated with an H856 connector
that mates with the H854 connector on the AA V11-A module. The
other end is an unterminated ribbon cable. The BC04Z cable is available in lengths of 3.05 m (10 ft), 4.5 m (15 ft), and 7.6 m (25 ft).
PROGRAMMING
All four OAC holding registers are automatically set to zero on system
initialization. This produces -:-5.12 V at the OAC outputs when the
mode/level jumpers are connected as delivered from the factory. Any
holding register value remains In effect until changed by· the processor
in response to a program instruction. Coding to the 0/A converters is
offset binary for bipolar operation and straight binary for unipolar
operation. Offset binary defines 0 as maximum negative voltage, midpoint (I.e., 4000, for the 12-blt AAV11-A) as 0 V, and all1s (7777,) as
maximum positive voltage. These relationships are Illustrated In Table
5.
43
AAV11-A
AAVII-A
OSCILLOSCOPE
II:
1'--':,
X OUT (PIN VVI
,-, _ _---"-X=IN---+-I
II--I---'A""-NA~LOG~GR~OU:!!!JND~(!:.!!PIN~U~UI~r--'--:-_?:-:
X RETURN
z
ii:
*I--r-~~:=~~:=~~~~~-D(-PIN-H-H-I--~~~~~·<~--Y-R-E~LU~~:~~
Figure 5
Table 5
J1 Connector Pin Assignments
AA V11-A Dlgltal-to-Analog Converslons*
, Unipolar
Bipolar
Input
Code
(octal)
±2.56 V
(volts)
±5.12V
(volts)
OVto
±10.24 V +5.12V
(volts)
(volts)
OVto
+10.24 V
(volts)
0000
0001
3777**
4000
4001
7777
-2.5'6
-2.55875
-0.00125
0.0
+0.00125
+2.55875
-5.12
-5.1175
-0.0025
0.0'
+0.0025
+5.1175
-10.24
-10.235
-0.005
0.0
+0.005
+10.235
+0.0
+0.025
+5.1175
+5.12
+5.1225
+10.2375
+0.0
+0.00125
+2.55875
+2.56
+2.56125
+5.11875
* Offset binary for bipolar, straight binary for unipolar operating modes. Conversions may be made between 2's complement signed binary and offset
binary numbers by subtracting 4000. from the 2's complement number (or
adding 4000. to the offset binary number) and using only the low-order 12
bits of the result.
** Note that In all ranges, actual maximum positive voltage output Is 1 LSB less
than nominal maximum positive output.
44
ADV11-A
ADV11-A ANALOG TO DIGITAL CONVERTER
GENERAL
The ADV11-A is a 12-bit successive approximation analog-to-digital
converter that samples analog data at specified rates and stores the
digital equivalent value for processing. A multiplexer section can accommodate up to 16 single-ended or 8 quasi-differential inputs. The
converter section uses a patented auto-zeroing design that measures
the sample data with respect to its own circuitry offset and therefore
cancels out its own offset error.
AID conversions are Initiated by program command, clock overflow,
or external events. The program control Is determined by the control
and status register (CSR). The clock overflow command Is supplied by
the KWV11-A option. External event inputs can originate at the user's
eqUipment or from the Schmitt trigger output on the KWV11-A clock.
The digital data output Is routed through a buffer register to the bus,
from which it can be transferred into memory. This buffer optimizes
the throughput rate of the converter.
Three reference signals are provided for self-testing on any channel
input: two dc levels and one bipolar triangular waveform. This output
can be used with DIG IT AL diagnostic software to produce a data base
for extremely thorough and preCise analog linearity testing.
FEATURES
•
•
•
•
•
16-channel multiplexer
Sample-and-hold functions
Auto-zeroing technique
Buffered data output
Self-testing features
SPECIFICATIONS
Identification
A012
Type
Quad
Power
+5 Vdc ±5% at 2.0 A
+12 Vdc ±3% at 450 mA
Bus Loads
AC
DC
3.25
1
45
ADV11-A
Inputs
Analog input protection
Fusible resistor guaranteed to
open at ±85 V within 6.25 seconds. Guaranteed not to open
from -25 V to +20 V at the input
Overload affects no components
other than the fusible resistor on
the overloaded channel; no other
channels are affected.
Logic input protection
Fusible resistor guaranteed to
open at ±25 V within 6.25 seconds. Guaranteed not to open
from -4 V to +9 V at the input.
Analog input full scale range
(FSR)
10.24 V bipolar (-5.12 V to
+5.12 V)
Analog inpul.dynamic resistance
(Vin ::s;; 5.12 V)
100 Mn minimum
Analog input bias current
( Vin ::s;; 5.12 V)
50 nA, maximum
Logic input voltages
Low = 0.0 to +0.7 V
High = +2 V to +5 V
Logic input currents
Low = -6.8 rnA at 0 V
High = +1.3 rnA at +5 V
Logic input riselfall time
400 ns maximum
Coding
AID Converter
Resolution
12 bits, binary weighted (2.5 mV
nominal)
Format
Parallel offset binary, right
justified
Input Voltage
+FS-1 LSB
o
-FS
Output Code
7777
4000
o
46
ADV11-A
(FS = 5.12 V;
1 LSB = 2.5 mV)
Vernier DIA
Resolution
8 bits, binary weighted
Format
Offset binary encoded
Input Code
377
200
o
Approximate
Offset Voltage
+2.5 AID LSB (+6.4 mV)
o
-2.5 AID LSB (-6.4 mV)
Performance
Gain error
Adjustable to zero
Offset error
Adjustable to zero
Differential linearity
No skipped states; no states wider than 2 LSB. 99% of state
widths ± 1h LSB
Integral linearity
± 1 LSB, maximum non-linearity
(referenced to end p-olnts)
Temperature coefficients
Gain = 6 PPM per °C
Linearity = 2 PPM of full-scale
range per °C
Offset = 7.5 PPM of full-scale
range per °C
Noise
Module = 0.4 LSB rms; 2 LSB
peak
System = 0.5 LSB rms; 2 LSB
peak
Warm-up time
5 minutes, maximum
Tlmlng_
External start
Low level pulse, 50 ns minimum
to 10 ,.,.s maximum; conversion
starts on leading edge
47
ADV11-A
Synchronization
OtoT
Conversion time
16 T (T
Transition interval
(reacquisition interval between
end of conversion or channel
change and start of new conversion)
9
= Clock period = 2 "s)
"s
Test Signals
The ADV11-A provides three output voltages for test purposes:
1. Positive dc level, +4.4 V (±15%)
2. Negative dc level, -4.4 V (±15%)
3. Triangular wave, 15 Hz nominal (±15%)
DESCRIPTION
General
The function of the ADV11-A module Is to convert analog Input data to
a 12-bit digital word that is representative of the Input. This Is done by
the channel selection, control logic, AID converter, and bus Interface
functions as shown In Figure 1.
48
~H:;N~ ;;L~T~ - - - . .
I
I
I
I
I
I
LOW CHANNEL
SELECT
ENA~~~f1
__
.L
AUTO-ZERO
~
II
r,--------------------,I
I • A-D CONVERSION
I
I~D~
I
r---l
~
COMP H
~
I
I
I
I
I
I
I
I
I
________ .JI
"""'_
rcONTROL - - - - - --,
.
,
LOW
<0
CHANNEL
SELECT
HIGH
CHANNEL
SELECT
:fr!ENABLE
MISC.
CONTROL
LOGIC
ENABLE
CAOZC L
HOLD
CNTL
VECTOR H
I
I
I
I
I
I
I
I
I
I
BUS MONITORS CONTROL-l..IIIIES
Figure 1
ADV11-A Functional Block Diagram
:.c
<
:.-•
......
ADV11·A
Channel Selection
Channel selection is accomplished under program control by two 8channel multiplexers and is a function of the data asserted in bits 8
through 11 of the control/status register (CSR). Each of the 16 analog
input channels is routed to the single output channel through aMOS
field-effect transistor which acts as a normally open switch. During the
sample interval, the data pattern in CSR bits 8 through 11 selects one
of these transistors and causes it to change from a condition of nearly
infinite resistance (1 GU or more) to one of very low resistance (1000 U
or less). Since in the selected state the transistor conducts current
within the ±5.12 V limits equally well in both directions, it now functions as a closed switch, effectively routing to the output line whatever
analog signal is connected to its input.
AID Conversion
AID conversion can be initiated in three ways: under program control,
on overflow from the KWV11-A real-time clock, or on external input.
When a conversion is completed or the control program writes a multiplexer address into the CSR, the control logic initiates the transition
interval, a delay of about 9 P.s to allow the multiplexer adequate selection and settling time and to permit a valid representation of the signal
level to be established in the sample circuit. If no AID start signal has
occurred by the time the transition interval has elapsed, the sample
circuit merely follows the signal transmitted to it through the selected
multiplexer channel and waits for an AID start signal. When an AID
start signal occurs-or at the end of the transition interval if AID start
was previously generated by the writing of the CSR GO bit-the
sample-and-hold circuits are switched to hold, sustaining the sampled
. level for the next step. The multiplexer output is then set to its hold
condition, Le., to ground if the single-ended (SE) input is set low for
single-ended measurement, or to the second differential input (return
line) if the SE input is not set low. Note that if an external or clock start
signal occurs during the transition interval, conversion starts immediately, without waiting for the transition interval to be completed. Bit 15
of the CSR (AID Error) is set, however, and an interrupt is generated if
Bit 14 (Error Interrupt Enable) is set-alerting the program that conversions are occurring too fast and are consequently liable to be in
error.
Under normal conditions, it is not until the transition interval is complete that the measurement process is begun. The successive approxilTfation register (SAR) is cycled through 13 states by the clock. In the
first state, its output code involves only the most significant bit (MSB)
of the 12-bit SAR word. This output code causes the feedback digltal50
ADV11-A
to-analog converter to generate an output equivalent to that produced
by the hold circuits in response to a sample voltage of O. The digltal-toanalog converter output is summed with that produced by the hold
circuits and with that coming from the grounded multiplexer output
(single-ended mode) or from the second differential input (quasldifferential mode). If the current from the summing mode is negative,
the first approximation was too low, and the comparator signals the
SAR to maintain the state of bit 11 and repeat the process with bit 10. If
the current from the summing mode is positive, the first approximation
is too high, and the SAR changes the state of bit 11 before cycling to
the second approximation. This process continues until all 12 bits in
the word have been set, tested, and if necessary, changed. The 13th
state (end of conversion, or EOC) indicates that the meas·urement is
complete and that the SAR now contains an offset binary equivalent of
the sampled voltage and may therefore be transferred to the processor. EOC causes the sample-and-hold circuits to return to the sample
mode and to reset the SAR, preventing further SAR activity until the
occurrence of the next hold condition.
.
Note that because the reference point against which the sample voltage is compared is at the output of the multiplexer itself rather than
internal to the sample-and-hold circuits, all offset voltages generated
by the intervening circuits are common to both sample-and-hold conditions and are therefore cancelled out of any measurement. In slngleended mode, grounding the multiplexer output (and thereby establishing this reference pOint) is identified as auto-zeroing the
converter.
Bus Interface
In addition to stopping the SAR clock and re-establishing the sample
mode, the end-of-conversion signal also initiates the process that
causes the SAR data to be transferred to the processor. Since this
operation takes a finite amount of time which would interfere with
subsequent measuring operations, the SAR data is first transferred to
a holding device, the data buffer register (DBR) where it will remain
until the processor can be notified to read the conversion data for
processing. In the meantime, the channel selection and A/D conversion circuits can begin the next measurement as dictated by control/status register (eSR) bit conditions controlled by the processor.
Included in the ADV11-A interface is an extension of the DBR designed to accept a-bit write information from the bus data/address
lines. This buffer permits programmed setting of the vernier DAC. Also
included are transceivers that connect the bidirectional bus data lines
to the LSI-11 bus data/address lines. Associated with these transceiv-
51
ADV11-A
ers are switches that let device and vector addresses be assigned to
any given ADV11-A.
Control Logic
As the above discussion suggests, a large number of signals must be
precisely orchestrated each time the ADV11-A executes a conversion.
The control logic contains an assortment of gates, latches, read-only
memories, and timing circuits designed to ensure that 1) multiplexer
channels are properly selected, 2) sample durations are of adequate
length, 3) conversions are not initiated during uncompleted previous
conversions. In general, the user need not attend to any but the most
elementary details of the conversion process, e.g., making necessary
connections to the system and writing control programs that make
appropriate use of the eSA.
CONFIGURATION
General
This section describes how the user can configure the module to
function within his system by setting dip switches Sl and S2 (Figure 2)
to obtain the desired device address and interrupt vector as described
in Table 1. When a jumper wire Is Inserted between the lugs, the
single-ended Inputs (16 channels) are selected. When the wire Is removed, quasi-differential inputs are selected.
52
ADV11-A
SINGLE-ENDED
JUMPER LUGS
n
i~LBO~K
~r-
L---C~~~:1 00
OFFSET..I
ADJ
Figure 2
P
\ . GAIN
ADJ
ADDRESS
BIT 2]SWITCHES[BIT 3
.
S
OVERFLOW
SI
IN)
S2
BIT8 TAB S
o
VECTOR
(EXTER'JAL START!
SWITCHES
BIT 11
ADV11-A Connectors and Switches
Table 1
Standard Assignments
Description
Mnemonic
Registers
Control and Status
Data Buffer
DBR
CSR
Interrupt Vectors
Conversion Complete
Error
53
First
Module
Address
Second
Module
Address
170400
170402
170420
170422
400
404
410
414
ADV11-A
Registers
The control and status register (eSR) address can be selected in the
range of 170000 to 177774 by using the S2 dip switch as shown in
Figure 3. Switch S2 is factory-set at 170400, which Is the recommended address as illustrated in Figure 3. The functions of the eSR bits are
shown In Figure 4 and detailed in Table 2.
CSR ADDRESS FORMAT
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
111111111010101110101010101010101
I , I I I I I I I I
STANDARD ADDRESS
CONFIGURATION
OFF OFF OFF ON OFF OFF OFF OFF OFF OFF
!!!!!!!!!!
(170400)'
CSR ADDRESS
SWITCH (S2)
Figure 3
I10
9
B
7
6
5
4 3
2
1I
eSR Switch-Selectable Address
ERR
AD
DONE
INT ENA
Figure 4
eLK
START
ENA
eSR Bit Format
54
ID
ENA
NOT USED
ADV11-A
Table 2
CSR Bit Functions
Bit
Description
15
AID Error (Read/Wrlte)-The AID Error bit may be
program set or cleared and Is cleared by asserting
BINIT L. It is set by any of the following conditions:
1. Attempting an external or clock start during the
transition Interval.
2. Attempting any star:t during a conversion In
progress.
3. Failing to read the result of a previous conversion before the end of the current conversion.
14
Error Interrupt Enable (Read/Wrlte)-When set, enables a program interrupt upon an error condition
(AID Error). Interrupt is generated whenever bits 14
and 15 are set, regardless of which was set first.
13-12
Not used.
11-8
Multiplexer Address (Read/Wrlte)-Contains the
number of the current analog Input channel being
addressed.
7
AID Done (Read)-Set at the completion of a conversion when the data buffer Is updated. Cleared
when the data buffer Is read by asserting BINIT L. If
enabled, interrupts are requested simultaneously by
both bits 7 and 15; bit 7 has the higher prl.orlty.
6
Done Interrupt Enable (Read/Wrlte)-When set, enables a program Interrupt at the completion of a conversion (AID Done). Interrupt Is generated when bit 7
and bit 6 are both set regardless of sequence.
5
Clock .Start Enable (Read/Wrlte)-When set, enables conversions to be Initiated by an overflow from
the clock option.
4
External Start Enable (Read/Wrlte)-When ·set,
enables conversions to be Initiated by an external
signal or through a Schmitt trigger from the clock
option.
55
ADV11-A
Table 2
CSR Bit Functions (Cont)
Bit
Description
3
10 Enable (Read/Wrlte)-When set, causes bit 12 of
the data buffer register to be loaded to 1 at the end
of any conversion.
2
Maintenance (Read/Write)-When set, loads all bits
of the converted data output equal to multiplexer
address LSB (bit 8) at the completion of the next
conversion. Cleared by asserting BINIT L. Used for
all Os·and all 1s = test of AID conversion logic.
1
Not used
o
AID Start (Read/Write)-lnltlates a conversion when
set. Cleared at the completion of the conversion and
by asserting BINIT L.
The data buffer register (DBR) address will be the next even address
following the selected eSR address. This address has two separate
DBR registers: one read-only and the other write-only. The functions
of the register bits are shown in Figure 5 and described In Table 3.
I
'T' " 'T' "
1
1
1
'-y--
1
.
VERNIER D/A (WRITE)
MSB
I " ~ I~ " I~ "
~ ~
M
1
MSB
1
1
•
ID
CONVERTED DATA (READ)
Figure 5
LSB
DBR Bit Format
56
1
I'
00
1
I
LSB
ADV11-A
Table 3
DBR Bit Functions
Bit
Function
Read-Only
15-13
Not used. Should read as o.
12
10-When 10 Enable (bit 3) of the eSR has been set,
DBR bit 12 will be set to 1 at the end of the conversion.
11-0
Converted Data-These bits contain the results of
the last AID conversion.
Write-Only
15-8
7-0
Not used.
Vernier 01 A-These bits provide a programmed offset to the converted value (scaled 1 01 A LSB = 1/50
AID LSB). The hardware initializes this value to 200 a
(mid-range). Values greater than 200a make this input voltage appear more positive.
Vector Interrupt
The AID conversion complete interrupt vector is set by dip switch S1
(Figure 2). Any address in the range of OOOa to 777 a can be selected by
the user. The switch is factory-configured for 4008 , the recommended
vector, as shown in Figure 6. The error interrupt vector will be four
words higher than the AID conversion complete interrupt vector.
57
ADV11·A
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
101010101010101110101010101010101
I I I I I I
STANDARD VECTOR
CONFIGURATION
(4001
VECTOR
SWITCH
(SII
ON
OFF OFF OFF OFF OFF
! i ! !! !
I
B
Figure 6
.7
6
5
4
3
2
1
1
•
Interrupt Vector
Mode Control
The ADV11-A .is equipped with the jumper lugs (Figure 2) that permit
changing the operating mode from quasi-differential (no connection)
to single-ended (jumper installed). The single-ended mode can also
be selected by connecting H854 connector pin C to logic ground. This
alternative is provided to permit convenient external mode selection in
installations that require frequent alteration between one mode and
the other.
Analog Input Interfacing
Single-Ended Mode - Single-ended analog input signals for the
ADV11-A may be of two types, grounded and floating. A grounded
input is one whose level is referenced to the ground of the instrument
that is producing it, as illustrated in Figure 7. Since the instrument may
be located at a distance from the computer, there may be some voltage difference between the instrument ground and the computer
ground. The voltage seen by the ADV11-A will be the sum of the
undesired ground difference voltage and the desired instrument signal voltage. In cases where such differences are encounte.red, they
can be minimized by plugging the instrument into an ac outlet as close
as possible to that providing power to the computer. Do not run a wire
from user's ground to the ADV11-A analog ground. Such a wire can
cause ground loop currents which affect results not only on the input
channel in question, but also on other channels.
58
ADV11·A
r;.;;11-:-; - - - - - - - ...,
I
ruSTR·;SOOR~ ~.;;G;'
I
I
I
I
I
SIGNAL
MUX
ADVl1-A
GROUND
L ______ .JI
USER'S
GROUNO
I
I
I
I
I
I
I
I
I
_...J
COMPUTER
GROUND
Figure 7' Single-Ended Input Referenced to User's Ground
A floating input is one whose signal voltage is developed with respect
to .. a point not connected to ground, as illustrated in Figure 8. The
identifying characteristic of a floating source is that connecting the
signal return to the ADV11-A ground does not result in a current path
between the ADV11-A ground and the instrument ground.
Note that the return of a floating input must be connected to one of the
ADV11-A's analog ground terminals. Ground pOints may be shared
among channels, as illustrated by the battery-powered sources in the
figure.
59
ADV11-A
1---------1
FLOATING SOURCE
CHAN 00
CHAN 01
CHAN 02
CHAN 03
CHAN 04
LOW
MUX
CHAN 05
CHAN 06
CHAN 07
CHAN 10
CHAN"
CHAN 12
CHAN 13
INSTRUMENT WITH
ISOLATION TRANSFORMER AND
FLOATING SECONDARY
HIGH
MUX
CHAN 14
1
CHAN 15
CHAN 16
CHAN 11
HO GROUND
L ___ ...,,- ____
COMPUTER _
Figure 8
G~D_.:...
Floating ADV11-A Input Signals
Quasi-Differential Mode - The "quasi" prefix in "quasi-differential"
can best be explained by reviewing a true differential operation. A true
differential input involves two signal lines connected to a differential
amplifier so that the output of the device is a function of the instantaneous difference between the voltages on the two signal lines. One
advantage of such a configuration is illustrated in Figure 9.
Figure 9A assumes a single-ended generating device that produces a
signal, V s with respect to its ground and is situated sufficiently far
enough away from the receiving device for a significant noise voltage,
V n' to be developed in the power distribution ground lines. The result
is that, at any given instant, the differential amplifier in the receiving
device sees both the signal voltage and the noise voltage. Its output,
Vo, is a function of V s + V n and is in error with respect to Vsalone.
60
ADV11-A
GENERATING
RECEIVING DEVICE
DEVICE
r----l
I
r----l
I
1 V,
I
I
I
I
'V V.
1
Vo
I
L ____ J
Vn
-
-
-
-
-
~~}- -
-
-
- -
(VO,vt + V n )
o. SINGLE-ENDED MODE
GENERATING DEVICE
r----l
1
Vo
I
1 11 1
1
I ____ J
L
-
-
-
L___ J
-
-
Vn
,-,
-I'V~
'-'
-
-
-
-
-
b. TRUE DIFFERENTIAL MODE (V. -V, tVn-V.)
Figure 9
Single-Ended vs. True Differential Input Modes
Figure 98 illustrates the same device connected in true differential
mode. The same noise voltage exists in the power distribution ground
system, except the generating device ground is connected directly to
the negative input of the receiving differential amplifier. Because the
instantaneous noise voltage is common to both the + and - inputs, it
is cancelled out of the final amplifier output. Vo now provides a valid
representation of V salone.
Figure 10 illustrates the ADV11-A operating in the quasi-differential
mode.
The major contrast between true differential operation as described
above and the operation of the ADV11-A In differential mode is that in
the latter, the two sides of the signal are not simultaneously input to a
differential amplifier. Rather, their difference is established by a sequential operation that first samples the voltage at one of the two
inputs and then, holding this value fixed, in effect subtracts it from the
61
ADV11-A
voltage at the second input. For near dc conditions, this procedure
produces a result like that of true differential operation (Le., the output
is a function of the difference between the two input voltages, and
common mode voltages are cancelled out).
Because of a significant time lapse, however, between taking the sample and completing the final approximation, a possibility for error is
introduced by the ADV11-A that increases as a function of common
mode signal frequency. The result is that the common mode rejection
ratio, while essentially infinite at dc, rolls off for ac signals, and is about
40 dB at 60 Hz line frequency. Also,.because the holding action of the
sample-and-hold circuit is, in effect, only on the first (non-inverting,
signal) input, but not on .the second (inverting, return) input, the
voltage rate of change on the second input should be kept below 25
mV /rms. This is the ·slope that results in a quarter-LSB change during
the conversion interval. Such a rate of change corresponds to 125 mV
peak-to-peak at 60 Hz line frequency. This dynamic response difference between the two inputs requires distinguishing the ADV11-A's
differential mode from true differential operation. Hence the term
"quasi-differential."
r~~R~N~~i
I
I
I
I
L_
r--------------~----------COMPUTER GROUND
FOR de CONDITIONS;
Va·
v,~v2
.(V~+vn.
-lin· v,
FOR at CONDITIONS.
Va' II, "1) - V2 (12 ) • v, (t ,)
+[
Yn ( " ) - Vn (12). ]
NOTE
Sol.d sWitch PO!III.oos indicate sample atote r',l.dotted positions Indicote hold "ole ('2'
Figure 10
ADV11-A Quasi-differential Mode
62
ADV11-A
Installation Precautions
As a preliminary step, confirm that the computer power supply ground
is connected to power line (earth) ground. If continuity checks reveal
no such connection, attach a length of 12-gauge wire between the
power supply ground and a convenient point associated with earth
ground.
Twisted Pair Input Lines - The effects of magnetic coupling on the
input signals may be reduced for floating single-ended or differ~ntlal
inputs by twisting the signal and return lines in the input cable. If the
inductive pickup voltages of the two leads match, the net effect seen at
the ADV11-A input is zero. Use of twisted pairs has no effect with a
single-ended non-floating signal (referenced to ground at the instrumentend).
Shielded Input Lines - The effects of electrostatic coupling on the
input signals may be reduced by shielding the signal wires. This is
especially important if the instrument or transducer has high source
impedance. To prevent the shield from carrying current and thus developing ground loop voltages within the ADV11-A, connect it to
ground at the instrument end only.
Allowing for Input Settling with High Source Impedance - All solidstate multiplexers inject a small amount of charge into their input lines
when changing channels. This causes a transient error voltage that is
discharged by the source impedance of the input signal. The ADV11-A
has this characteristic, and also injects a small charge into the selected input line at the end of each conversion when the auto-zero switch
is turned off. After any channel change and after any conversion, the
ADV11-A's control allows a 9-~s Interval (Identified as the transition
interval) during which conversions cannot start without generating error conditions. Normally, this is sufficient time for the input transient to
settle out.
More time may be needed, however, when the multiplexer is switching
into an input channel with high source impedance, particularly when
large amounts of shunt capacitance exist in the interconnecting cables. Avoid products with source Impedance/cable shunt capaCitance
greater than 1 ~s whenever conversions are to be made at maximum
rate with less than 112 LSB error. This means that cable shunt capacitance for a 1000 r! source should not exceed 1000 pF (103 X 10-9 =
10-6 ), that shunt capacitance for a 100 {} source should not exceed
0.01 ~F (10 2 X 10- a = 10- 8 ), etc. Assuming twisted pair cable
capaCitance of 50 pFlfoot, these constraints translate Into a maximum
63
ADV11-A
run of 20 feet from a 1000 n souce, 200 feet from a 100 n source, etc.
Note that these values are consistent with good practice for avoiding
noise pickup in long cable runs. Note also that settling errors can be
eliminated by increasing the time between conversions or incorporating a software delay between channel changes and program start
commands.
Connections
Figure 11 illustrates the location of user connectors and switches on
the component side of the ADV11-A board.
Analog input signals are input to the ADV11-A through the 40-pin
connector. Pin assignments for the connector are shown in Figure 11.
The proper H856-to-H856 cable is the Be08R; The proper H856 to
prepared open-ended cable is the BC04Z.
EXT START L
RAMP
ANALOG GND
- 4.5\1
ANALOG GND
.,5\1 TEST _t--'S=St--<>
uu
TT
\1\1
CH 17
-CH 07
CH X7
CH 16
-CH 06
CH X6
CH 15
-CH 05
CH X5
CH 14
-CH 04
CH X4
CH 07
+CH 07
CH 07
CH 06
CH 06
+CH 06
CH 05
+CH 05
CH 05
CH 04
+CH 04
CH 04
CH 13
-CH 03
CH X3
CH 12
- CH 02
CH X2
CH II
- CH 01
CH XI
CH 10
-CH 00
CH XO
CH 03
+CH 03
CH 03
CH 02
.CH 02
CH 02
CH 01
+CH 01
CH 01
CH 00
+CH 00
CH 00
SINGLE
ENDED
01 FFERENTI AL
H322
NOMENCLATURE
BOARD SIDE
Figure 11
ADV11-A 40-Pin Connector Pin Assignments
Distribution Panel - Figure 12 shows an H322 distribution panel that
Is connected on the rear to the ADV11-A Berg connector and on the
front provides easily Identifiable and conveniently accessible barrier
64
ADV11·A
strip connections for user apparatus. Each H322 accommodates two
ADV11-As or one ADV11-A and one other single-connector device.
Note that the H323-B potentiometer box may not be used with the
ADV11-A.
External and Clock Starts - The external start signal line, pin B of the
40-pin connector or TAB S (Figures 2 and 11), is a TTL-compatible
input that presents five unit loads (8.0 mA) to any driving output. Con-.
versions start on the high-to-Iow transitions of this signal.
Figure 12
H322 Distribution Panel
In most cases, the external start signal will be produced by a grounded
(non-floating) pulse generator or logiC circuitry located in a grounded
instrument. The return path for the external start signal will be through
the power line ground system. For this reason, ground differences
between source and computer should be minimized to prevent spurious start pulses due to ground noise. In no case should a separate
return line be run between grounded source and the computer
ground. Only with floating devices should return lines be run between
source logic ground and logic ground pins on the ADV11-A 40-pin
connector. External devices that require buffering can be interfaced to
the ADV11-A through Schmitt trigger 1 of the KWV11-A clock (STI).
Connection is made by means of a DEC 70-10771 type jumper to TAB
S (Figure 2) of the ADV11-A.
Conversions that must be initiated by time intervals or on every nth
external event may be triggered from the KWV11-A through a DEC 70-
65
ADV11-A
10771 type jumper connected from the clock output tab (ClK) to the
ADV11-A clock overflow tab (C).
PROGRAMMING
The following programming example reads 1008 AID conversions
from channel 9 into locations 4000 8 -4176 8 and halts.
STAP-T:
LOOP,
CL~
aAOSP
'Jr')V
.4000,PO
INC'
~1(lV
iaA(lSIo
UOSR
LOOP
IllADSP
lalCeR,CPO).
C'~P
RO,'4200
t''JE
LOOP
TST~
BPL
I'vC
,etEAP AID STATuS PEGISTEP
UP F'l PST ADDi ElUHER P~GISTffl AOCPE.SS
,srI
"'ALT
ADSP'
ADBPI
17041)0
170402
.E"'D
STA~T
* Starting a subsequent conversion before moving data from a previous con-
version is recommended only with systems equipped with non-processor
memory refresh. Without this capability. data will be lost occasionally by
CPU memory refresh intervening between the INC and MOV commands. In
general. non-processor memory refresh is essential to realizing the full potential of the ADV11-A.
66
BA11·M
BA11·M EXPANSION BOX
GENERAL
The BA 11-M expansion box provides a convenient means for expanding LSI-11 bus systems. Each expansion box includes an H9270 LSI11 bus-structured backplane and an H780 power supply system
mounted in an enclosure with a blank front panel.
The BA 11-M Is shown In Figure 1. Mechanical and mounting details
are shown in Figures 2 and 3.
FEATURES
• Provides power and cooling for LSI-11 Bus options
• Accepts quad or double height modules
• Eight double-height (four quad) LSI-11 Bus slots available for options
• LSI-1 ~ Bus power sequencing signals provided by the power supply
• LSI-11 Bus line frequency clock signal provided by power supply
• LSI-11 Bus backplane compatible with LSI-11, LSI-11/2 and LSI11/23 processors, memories, and Interface modules
• Rack-mountable in standard RETMA 19" wide rack
• UC listed; eSA certified
SPECIFICATIONS
Dimensions (including bezel)
Width
Height
Depth
Without mounting brackets
With mounting brackets
48.3 cm (19 in)
8.9 cm (3.5 In)
34.3 cm (13.5 In)
38.1 cm (15.0 in)
Shipping Weight
18.1 kg (40 Ib)
50 to 50 0 C (41 0 to 122 0 F)
Operating temperature·
Operating humidity
10% to 95% with a maximum wet
bulb temperature of 32 0 C (90 0 F)
and a minimum dew point of 2 0 e
(36 0 F)
* The maximum allowable operating temperature Is based on operation at sea
level, i.e., at 760 mmHg (29.92 InHg); maximum allowable operating temperature will be reduced by a factor of 1.8 0 C/1000 m (1.0 0 F/1000 ft) for
operation at higher altitude sites.
67
BA11-M
AC input power
100-127 Vrms, 50 ±1 Hz or 60 ±1
Hz, 400 W maximum, or
200-254 Vrms, 50 ± 1 Hz or 60 ± 1
Hz, 400 W maximum
DC output power
+5 Vdc ±3%, 0-18 A load (static
and dynamic)
+ 12 Vdc ±3%, 0-3.5 A load (static and dynamic)
Maximum output power: 120 W
(total)
Recommended circuit breaker
rating
15 A and 115 Vac or at 230 Vac
DESCRIPTION
The BA 11-M is a rack-mounted enclosure that provides power and
cooling for eight double (four quad) LSI-11 Bus module slots. It accepts either double or quad size modules. Modules are accessible
from the front of the box. A cable area is provided for routing I/O
cables from the modules to the rear of the box where a cable clamp
allows cables to be strain-relieved before leaving the box. An AC
ON/OFF switch and line cord are located at the rear of the box. Two of
the eight slots for double size modules are normally used for cabling
and termination, which leaves six bus slots available for options. Note
that multi-board options that require the special backplane interconnection on connections card 0 (i.e., RLV11) are not accommodated by
this expansion box. The BA 11-M Is available in two line voltage variations: 115V and 230V. Each version accommodates either 60 Hz or 450
Hz line frequency.
CONFIGURATION
When installing an expansion box to expand from a single to a dual
backplane system, the BCV1 B bus expansion option and TEV11 bus
terminator option (or equivalent) must be used. Install the BCV1 B
modules and cables as shown In Figure 4. The terminator must be
installed in the option location In the last box. When Installing the
BCV1 B cable set, disregard any "This side up" labels that may be on
the BC05L cables. Ensure that the red line on each cable is toward the
center of both modules and that J1 on each board is connected to J1
on the second board and similarly J2 on both boards. Ensure that the
cables have no twists. Carefully fold excess cable as shown In Figure
68
BA11-M
4. Figure 5 illustrates proper installation of the BCV1 Band TEV11
options.
When expanding from a second to a third backplane, the BCV1 A bus
expansion option is required, in addition to the items required for
expansion to the second backplane.
NOTE
BCV1 A and BCV1 B cables must differ in length by
121.92 cm (4 ft) (minimum).
The completed installation for a 3-backplane system using the BCV1A
option is shown in Figure 5. In addition to this option, the BCV1 B
option is required to connect the first backplane to the second backplane; a 120 n bus termination is required in the last option slot In the
third backplane.
Figure 1
BA 11-M Expansion Box
69
BA11-M
14-----...8 em 117.625 i n l - - - - - t...,
T
~================~J:I
8.9 em
'~~~~l.-~---------~:;:-----------~J
34)em
"3.6 inl
,-
POWER SUPPLY
AIR
AIR
~
FRONT
PROCESSOR
MEMORY AND
DEVICES
"·&207
Figure 2
BA11-M Assembly Unit
70
BA11-M
-z: -.: :.:::.. . . 1-1-i~
1
FRONT VIEW
0
0
0.14 em
IUIInI
Ulem
11.7I1n1
0
0
T
-- -
13.6inl
8.9an
0
0
0
0
0
0
o
o
o
I
~i·~-----------I::'~n,--------------~
(0.371inl
C)
f 71
L4=~C)
________________________
O.9&cm
I
8.8cm ••• em
'15 Iftl 11
nl
FRONT OF BOX I PANEL REMOVEOI
c.....l!
(~~':i
I...
48.3cm
·------------119.
0 ml
-'-----------J
.~[!:.= = = =-(;';-: O- inl= = = :~ ='
Figure 3
BA 11-M Cabinet Mounting
71
~ci~-:::,
"·&206
SYSTEM BACKPLANE
M~EOOJZJJ
......,
I\)
M~Ol17I71
/
i
4
23
5
6
8
7
I
J~
~DER
FRONT SIDE
BOX
~
@
Jl
m
CABLE SET
BCVIB
J2
M9401
FRONT SIDE
MA-2003
Figure 4
BA 11-M Expansion Box Interconnections (two-backplane
system)
~
~
~
s:•
BA11-M
CPU
2
1
3
4
11/03
I 6
2-BOX
SYSTEM
IBCV1B.06\
BAtt·ME, MF
EXPANDER BOX
(TERMINATOR
REQUIRED
TEV",
REV11-A, OR BDV11-AA)
6
8
1
9
10
12
11
2
CPU
1
3
4
11103
6
IBCV1B·061
6
3-BOX
SYSTEM
8
1
9
10
BAtt·ME, MF
EXPANDER BOXES
(TERMINATOR
REQUIRED
TEV1"
REVll·A, OR BDVll-AA)
11
.IBCV1A-l01
12
14
13
16
16
18
11
NOTES
1.' INCLUDED IN 8CV1B BUS EXPANSION OPTION. (CABLES ARE AVAILABLE IN 2,4,6. OR
12 FT LENGTHS.!
2.
INCLUDED IN BCV1A BUS EXPANSION OPTION. (CABLES ARE AVAILABLE IN 2,4,6, OR
12 FT LENGTHS.)
3.
INCLUDED IN TEV11 8US TERMINATOR OPTION.
4.
THE LSI-11 BUS IN RESTRICTED TO 16 OPTIONS, MAXIMUM. THESE OPTION SLOTS WOULD
ONL Y BE USED WHEN PREVIOUS OPTION(S) OCCUPY MORE THAN 1 OPTION LOCATION.
5.
BCV1A AND BCV1B EXPANSION CABLES MUST DIFFER IN LENGTt-I BY 4 FT (MIN).
MA·_
Figure 5
BCV1A Installation
73
BA11-N
BA11-N MOUNTING BOX
GENERAL
The BA 11-N mounting box is designed to be used as a mounting box
or as an expander box for an LSI-11 bus-based system. Each mounting box (Figure 1) includes an H9273 backplane assembly, an H786
power supply, and an H403-A ac input panel mounted in an enclosure
with a blank front panel (BA 11-NE, NF) or bezel assembly (PDP11/03-LC,-LD).
FEATURES
• Nine slots for double or quad size modules
• Powerful and reliable 240-watt switching power supply, which is
both voltage- and frequency-Independent
•
•
•
•
•
•
•
Module cooling
Designed to meet small system applications
Modular deSign for ease of servicing
LSI-11 bus power sequencing signals provided by power supply
Line frequency signal provided by power supply
Unique backplane interconnection for custom multi-board options
LSI-11 bus backplane-compatible with LSI-11, LSI-11/2 and LSI11/23 processors, memories, and interface modules
• Rack-mountable in standard RETMA 19" wide rack
• UL listed, CSA certified and complies with VDE and lEe requirements
SPECIFICATIONS
Tables 1 and 2 show BA 11-NE and BA 11-NF mounting box specifications, including the H786 power supply.
Dimensions (including bezel)
Width
Height
Depth
Without mounting brackets
With mounting brackets
48.3 cm (19 in)
13.2 cm (5.19 in)
57.8 cm (22.7 in)
67.96 cm (26.75 In)
Weight (without modules)
20 kg (44Ib)
74
BA11-N
Operating temperatures·
50 to 50 0 C (41 0 to 122 0 F)
Operating humidity
10% to 95%, with a maximum wet
bulb temperature of 32 0 C (90 0 F)
and a minimum dew point of 2 0 C
(36 0 F)
Input voltage
BA11-NE
BA11-NF
115 Vac
230Vac
Input current**
BA11-NE
BA11-NF
12Amax
6Amax
Circuit breaker rating
15 A at 115 Vac or 230 Vac
• The maximum allowable operating temperature Is based on operation at sea
level, i.e., at 760 mmHg (29.92 InHg); maximum allowable operating temperature will be reduced by a factor of 1.8 0 Cl1000 m (1.0 0 F/1000 ft) for
operation at higher altitude sites.
•• Input current consists of that used by the BA 11-N, itself, plus whatever current is supplied via the convenience ac outlet (J3) to an expander box; the
total current must be less than the maximum specified.
DESCRIPTION
The H9273 backplane assembly consists of a backplane, a card frame
assembly, and two cooling fans. The H9273 9-slot backplane
assembly will accept nine LSI-11 bus double-height or quad-height
modules (except for MMV11-A 4K X 16 core memory modules). The
PDP-11/03-LC and the SA 11-NE operate on 115 V and the PDP11/03-LD and the BA11-NF operate on 230 V. Mechanical and mounting details are shown in Figure 2.
75
8A11-N
'''illS
.un "ssu••",
Pl/llllfEO Cll/CUlf .0"1/0
Figure 1 SA 11-N Major Assemblies
L
57 B crn - - - 1
I ACINPur
---1~7,"1~
1
IS !9'n'
-L
ir==:::::::::::::::::::::::::::::::::::~1
132cm
PANEl
AIR
AIR
8ACI(PLANE
ASSEMBLY
Figure
2
SA ll-NE and SA ll-NF Assembly Unit
76
BA11-N
The ac input box, power supply, and H9273 logic assembly are attached to the logic box base. The power supply assembly is hinged to
the base and can be swung open to expose the internal components;
with little effort, the entire assembly can be removed from the base
and replaced. lSI-11 bus modules are inserted in the backplane from
the rear of the box through an access door that is equipped with strain
reliefs for lSI-11 bus and communications cables.
When the unit is to be mounted in an equipment rack, the logic box
cover is attached to the rack with mounting hardware. The logic box
base slides into the mounted cover and a spring-button assembly
engages to prevent the base from being accidentally pulled out of the
cover.
Table 1
Item
Specification
Current rating
5.5 A at 115 Vrms
2.7 A at 230 Vrms
Inrush current
100 A peak, for 1h cycle at 128
Vrms or 256 Vrms
Apparent power
630 VA
Power factor
The ratio of input power to apparent power shall be greater than
0.6 at full load and low input voltage
Output power
+5 Vdc ±250 mV at 22 A
(A minimum of 2 A of +5 Vdc
power must be drawn to ensure
that the + 12 Vdc supply regulates properly)
+12 Vdc ±600 mV at 11 A
Power-up/power-down characteristics
Static performance
Power-up
BOCOK H goes high; 75 Vac
BPOK H goes high; 90 Vac
BPOK H goes low; 80 Vac
BOCOK H goes low; 75 Vac
Power-down
77
BA11·N
Table 1
BA11-N Power Supply Specifications (Cont)
Item
Specification
Dynamic performance
Power-up
3 msec (min) from dc power within specification or to BOCOK H
asserted
70 msec (min) from BOCOK H asserted to BPOK H asserted
4 msec (min) from ac power off to
BPOK H negated
4 msec (min) from BPOK H negated to BOCOK H negated
5 ~sec (min) from BOCOK H negated to dc power as of specifications
Power-down
CONFIGURATION
The procedure for mounting the BA 11-N mounting box in an
equipment rack is presented below.
Installing the Logic Box Cover - The logic box cover is mounted in
the equipment rack as shown In Figure 3.
1. When the unit Is shipped, the logic box cover is held to the base
by four screws (these are used only in non-rack-mounted applications), and a single shipping screw, which, for safety, must be in
place whenever the unit is moved or shipped. First, remove the
four screws that attach the cover to the base. Then open the rear
door and remove the shipping screw.
2. A safety locking device is found on the right side of the unit (when
looking at the front). This device, a spring-button assembly, is
attached to the side of the ac input box. When the unit is closed,
the button on this assembly fits into the rear hole of two holes in
the right side of the cover. This mechanical interlock can be overridden by pushing the button in from the outside of the cover
while, at the same time, pulling the logic box base to get the
button past the hole. The base can then be pulled out of the cover
to its extended position; at this position, the button pops into the
front of the two holes, preventing the base from being inadvertently pulled entirely out of the cover. Open the base to the extended
position and then release the button from the front hole. Slowly
78
BA11·N
pull the base entirely out of the cover and set the base out of the
way.
Attach the Tlnnerman nuts to the cabinet uprights In eight places.
Mount the cover to the front cabinet uprights using four pan head
screws (10-32 X 0.62Ig) and four No. 810ckwashers.
Attach the two support brackets to the cover using four Phillips
pan head screws (8.32 X 0.38Ig) and four No.8 lockwashers.
Attach the support brackets to the rear cabinet uprights using four
Phillips pan head screws (10-32 X 0.62 Ig) and four No. 10 flat
washers.
Slide the unit Into the cover. It will be held In place by the sprlngbutton assembly. To slide the unit forward again It will be necessary to release this spring button.
If the system Is to be moved or shipped, the shipping screw must
be replaced.
3.
4.
5.
6.
7.
8.
/~
CAB UPRIGHTS
REF
1
/ 2910TV II REF
136CM
12600 INI REF
/
//
<
~ 1210TY21
~'"
41.6CM
~~
~
"."'.'"~
_ _ 373CM
11.471NI
~) IOTV 81 REF
Figure 3
SA11-NE and SA 11-NF Cover Mounting Dimensions
79
BA11-N
Installing the Logic Box Base In the Cover - Set the rear of the logic
box base on the support flanges of the cover and slide the base in until
the spring-button assembly engages In the extended position. Take
care not to pinch the cables while sliding the base in. Release the
spring-button and push the base all the way in until it engages In the
closed pOSition. Take the following steps to complete the installation.
NOTE
The base being installed is either the main base, i.e.,
the one containing the CPU, or an expander base
(two expander boxes can be added). Modify the
following instructions to suit the kind of base you are
installing, e.g., if there is a blank front panel, skip the
first half of step 1.
1.
2.
3.
4.
Put the AUX switch in the front panel in the OFF position; put the
ON/OFF switch on the ac input box in the OFF position.
When the AUX switch on the front panel is in the ON pOSition, the
two wires of the power controller cable are common. Connect the
free end of the cable to the input circuit of the power controller so
that the AUX switch controls the application of primary power to
the controller. Keep the AUX switch in the OFF position.
Loosen the cable strain reliefs and open the rear door of the box
to install the LSI-11 bus expansion cable assemblies. Two cable
assemblies are used. Table 3 describes the assemblies and tells
where to insert the assembly modules. (Figure 4 illustrates module plac_ement.) When inserting the modules, make sure the connectors are on top.
Close the rear door; bring the bus cables out under the left strain
relief and the communcations cables out under the right strain
relief. Adjust the strain reliefs so that the cables are held firmly but
are not pinched or crushed. Secure the strain reliefs and the rear
door. Make sure the cables will not bind when the base is pulled
out to the extended position.
80
BA11-N
Table 2
LSI·11 Bus Expansion Cable Assemblies
Assembly
Assembly
Composition
BCV1B-XX
Two BC05L-XX
cables
BCV1A-XX
Insert Modules In
One M9400-YE module
Slots A and B of the
first open row after all
other LSI-11 bus options have been
installed in the main
box.
One M9401 module
Slots A and B of row 1
of expander box 1
Two BC05L-XX
cables
One M9400-YO
module
Slots A and B of the
first open row after all
other LSI-11 bus options have been installed in expander
box 1
One M9401 module
Slots A and B of row 1
of expander box 2
NOTE
"-X" in the cable assembly number denotes length,
which can be 60.96,121.92,182.88, or 304.80 cm (2,
4, 6, or 10 ft). (Each cable of an assembly is the same
length.) When both assemblies are used In a system
(boxes), the lengths must differ by 121.92 cm (4 ft).
To facilitate servicing. the BCV1 B cables should be
182.88 cm (6 ft) long, while the BCV1A cables should
be 304.80 cm (10 ft) long.
81
BA11-N
CPU
321 H
BDAL <0 15> L
Q)
Q)
oCOOS
TRANSCEIVERI.
U,",L ...... v
·1
'OJ' n
BBS7 L
ROM
ADDRESS
SELECTION
LOGIC
IA<10'14> H
A H
SEL4 L
REG L
INWDL
SEL2 L
REG LlH
XMITH
OUTLB/HB L
DAL H
L:
SEL8 L
REG L
OUT LB L
SEL4L
REG L
OUTLB L
Figure 1
ROM
SOCKETS
58<12> L
5E<1 2> L
5T<1 2>
SP<1 8> L
8EVNT L
DAL6H
DATA
SELECTOR
BDV11 Block Diagram
m
c
<
.....
.....
BDV11
Control
The control logic consists of a DC004 protocol chip (Chapter 5) and an
82523 PROM. The control logic is enabled by the address match signal from the transceiver logic. The PROM monitors some of the DAL
lines and the address match signal and generates an enable signal for
the DC004 chip whenever any of the assigned bus addresses (173000
to 173777) is placed on the BDAL lines. The DC004 chip generates all
the protocol signals used with the LSI-11 bus to allow data transfers.
The control logic also generates the control signals for the read/write
register's ROM address selection and the ROM socket selection logic.
The bus control signals are defined in the appropriate processor
handbook.
Read/Wrlte Registers
The read/write register logic consists of two 8-bit universal shift registers. When the registers are being read, the control logic asserts XMIT
H and the Information on the DAL lines is the data within the shift
registers. When the registers are to be written Into, the XMIT signal is
negated and the registers are placed into a load condition. The registers are clocked and the information on the DAL lines is loaded Into
the registers as data. The registers are cleared when power is turned
on or when the system is booted.
ROM Address Selection
The ROM address selection logic uses the contents of the PCR register and the LSI-11 bus address to determine the address of the BDV11
ROM locations. Each ROM has 2048 10 addresses available. The logic
selects the high byte of the PCR register If bit 8 of the LSI-11 bus is one
and selects the low byte If bit 8 is a zero. The selected byte Is shifted to
the right one bit and used as the high byte of the BDV11 address. The
low byte of the LSI-11 bus address Is shifted one bit to the right and
used as the low byte of the BDV11 address. The complete BDV11
ROM address is formatted by using a combination of the high and low
bytes generated. Table 10 is a listing of how the PCR contents and the
LSI-11 bus addresses are used to generate ROM addresses.
Socket Selection
The socket (or ROM) selection logic (Figure 2) consists of two decoders (E30 and E35) that provide the outputs used to select the high byte
and low byte sockets. The user can program A10 Hand A14 H Inputs
to these decoders by selecting jumper wires W1-W4 and W9-W12 to
determine the configuration designation described In Table 2. The
89
BDV11
SB1 Land SB2 L outputs are used to select the 4K of
diagnostic/bootstrap DIGITAL programs. The SE1 Land SE2 L outputs are used to select the 2K words of user PROM. The SP1 L to spa
L outputs are used to select the additional 16K words of user ROM.
+5V
A14 L
Gl
W3
A14 H
SP8 L
SP7 L
SP6 L
74S138
SP6 L
E36
SP4 L
All H
A
SPa L
A12 H
SP2 L
Al0 H
SPI l
A13 H
W12
28
2YO
2A
2Y2
SEI l
2Y3
SE2 L
2Yl
74LS139
E30
lYO
S81 L
18
lY1
S82 L
lA
lY3
lY2
lG
W9
Wl0
74S138 TRUTH TABLE
Gl
H
G2
L
C
B
A
OUT LOW
l
L
L
YO (SP6 LI
L
l
H
Yl (SP7ll
l
H
l
Y2 (SP6 LI
l
H
H
Y3 (SP5ll
H
L
L
74LS139 TRUTH TABLE (EACH HALF)
G
L
Y4 (SP4 LI
H
l
H
Y5 (SP3ll
H
H
L
YB (SP2 LI
H
H "H
Y7 (SPI LI
Figure 2
A
L
L
YO(SB1 LI
L
H
Y1 (SB2 LI
H
L
Y2 (SEl LI
H
H
Y3 (SE2 LI
Socket Selection Logic
90
OUT LOW
B
BDV11
ROM Address
The ROM address logic uses the socket select logic outputs and address lines AO to A10 to select the desired address. The diagnostic/bootstrap ROMs are enabled by SB 1 Land SB2 L and are addressed-e by AO to A10. The user EPROMs are enabled by SE1 Land
SE2 L and are addressed by AO to A9. The user ROM sockets are
enabled by SP1 L to spa L and addressed ~y AO to A9. The output
data from the ROMs is sent to the data selector logic.
Data Selector
The data selector receives data from the ROMs and the registers of the
BOV11. This data is stored until the ol:Jfputs are enabled by XMIT. The
data is then gated to the OALO-15 bus lines where it is transferred to
the LSI-11 bus by the transceiver and control logic.
Display
The display logic consists of four flip-flops and four LEOs. The
contents of the display register (address 177524) are gated into the
flip-flops and the outputs light the display LED indicators. The pattern
of the display indicates to the user the type of program error when a
failure occurs.
Power-up
The power-up logic includes the ENABLE/HALT switch and the RESTART switch. In normal operation, the ENABLE/HALT switch is in the
ENABLE position. When the switch is placed in the HALT position, the
bus signal BHAL T L is asserted. The processor enters the halt mode
and responds to the console OOT commands. To resume processor
operation, the user must set the switch to ENABLE and enter a up"
command from the console.
The REST ART switch must be cycled to reboot the system. When the
switch is cycled, a capacitor is charged to disable the bus BOCOK H
signal and OCNOK L is asserted to initialize the BOV11 registers.
When the capacitor discharges, the BOCOK H signal is enabled, the
processor carries out a power-up sequence, and normal operation is
resumed.
BVENT
The BVENT logic uses a switch located in E21 that lets the user control
the LTC function. When the switch is open; the bus BVENT L signal
can be controlled by the LTC signal generated in the LSI-11 bus power
supply. When the switch is closed, the BVENT L signal can be controlled by the program.
91
BDV11
CONFIGURATION
General
The BDV11 is factory-configured (Group A in Table 2) by DIGITAL to
let the user expand the diagnostic and bootstrap programs by adding
2K words of EPROM and 16K words of ROM/EPROM memory. The
user can modify the configuration for his own software requirements.
Thirteen jumper wires are located on the module as shown in Figure 3
and identified in Table 1. Eight are used for selecting sockets, and five
are used to accommodate various types of memory chips. The switches used to select programs are listed In the Programming section
below.
Socket Selection
The socket selection logic is controlled by jumpers W1-W4 and W9W12, which can be configured in seven different ways, as shown in
Table 2. Group A assigns the PCR pages and socket selections.
Groups B-G let the user choose where to begin program execution,
such as having the processor execute Instructions directly from a system ROM or EPROM when power Is turned ON, rather than from the
diagnostic/bootstrap ROM.
Table 1
Selectable Jumpers
Jumper
W1
W2
Function
Socket selection
Socket selection
Socket selection
Socket selection
Chip selection
Chip selection
Chip selection
Chip selection
Socket selection
Socket selection
Socket selection
Socket selection
Chip selection
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
92
BDV11
I
tr
8M
EM
EM
8M
01'"
~M
.
~i
1M
tAl
o
93
Table 2
High Byte
Socket
Memory Configuration
Low Byte
Socket
Configuration
Designation
ROM
Address
PCR
Page
Selection
Signal
A
0-2K
4K-6K
16K-18K
20K-22K
0-17
40-57
200-217
240-257
SB1 L
SB1L
SB1L
SB1 L
2K-14K
6K-8K
18K-20K
22K-24K
20-37
60-77
220-237
260-277
SB2L
SB2L
SB2L
SB2L
4K-5K
0-1K
20K-21K
16K-17K
40-47
0-7
240-247
200-207
SE1
SE1
SE1
SE1
5K-6K
1K-2K
21K-22K
17K-18K
50-57
10-17
250-257
210-217
SE2L
SE2L
SE2L
SE2L
4K Diagnostic/Bootstrap (DIGITAL)
E53
(2)
E48
(1)
B
C
0
<0
~
E58
(4)
E44
(3)
A
B
C
0
2K User EPROM
E57
(3)
E40
(1 )
A
B
C
0
E52
(4)
E36
(2)
A
B
C
0
L
L
L
L
III
0
<
~
~
Table 2
High Byte
Socket
Memory Configuration (Cont)
Low Byte
Socket
Configuration
Designation
16K User ROM
ES4
(2)
_
E49
(1 )
A
E
F
G
<.0
0'1
ES9
(4)
E45
(3)
A
E
F
G
E60
(6)
E41
(5)
A
E
F
G
ES5
(8)
E37
(7)
A
E
F
G
PCR
Page
ROM
Address
..
-
- - -
--
Selection
Signal
--
16K-18K
16K-17K
0-2K
0-1K
200-217
200-207
0-17
0-7
SP8L
SP8L
SP8L
SP8L
18K-20K
18K-19K
2K-4K
2K-3K
220-237
220-227
20-37
20-27
SP7L
SP7L
SP7L
SP7L
20K-22K
18K-19K
4K-6K
4K-5K
240-257
240-247
40-57
40-47
SP6L
SP6L
SP6L
SP6L
22K-24K
22K-23K
6K-8K
6K-7K
260-277
260-267
60-77
60-67
SP5L
SP5L
SP5L
SPSL
m
C
<
...&
...&
Table 2
Memory Configuration
Low Byte
Socket
Configuration
Designation
ROM
Address
peR
Page
Selection
Signal
E51
(10)
E38
(9)
A
24K-26K
17K-18K
8K-10K
1K-2K
300-317
210-217
100-117
10-17
SP4L
SP4L
SP4L
SP4L
E47
(12)
E42
(11 )
26K-28K
19K-20K
10K-12K
3K-4K
320-337
230-237
120-137
30-37
SP3L
SP3L
SP3L
SP3L
E43
(14)
E46
(13)
28K-30K
21K-22K
12K-14K
5K-6K
340-357
250-257
140-157
50-57
SP2L
SP2L
SP2L
SP2L
E39
(16)
E50
(15)
30K-32K
23K-24K
14K-16K
7K-8K
360-377
270-277
160-177
70-77
SP1 L
SP1 L
SP1 L
SP1L
High Byte
Socket
16K User ROM (cont)
E
F
G
III
<.0
a>
A
E
F
G
A
E
F
G
A
E
F
G
C
<
~
~
BDV11
NOTE
The parenthetical numbers In the socket colums Indicate the order for installing each ROM.
Memory Configuration
The user can change the configuration of the SOV11 memory structure by using socket selection jumpers Wt-W4 and W9-W12; the standard configuration is designated "A" In Table 2. This table also
indicates the installation order for the PROM/ROM chips. The S, C, 0,
E, F, and G configurations show as alternate ways the user can map
the ROM memory. Details about selecting a configuration using the
socket selection jumpers are shown below.
Configuration
Designation W1
A
B
C
0
E
F
G
R
X
X
X
I
R
I
Socket Selection Jumpers·
W2
W3
W4
W9
W10 W11
W12
I
X
X
X
R
I
R
I
X
X
X
I
R
R
R
X
X
X
R
I
I
I
I
R
R
X
X
X
R
R
I
I
X
X
X
I
R
I
R
X
X'
X
R
I
R
I
X
X
X
* I = Installed, R = Removed, X = Irrelevant
Chip Selection
The system ROM sockets can be occupied by either 2K ROMs or 1K
ROMs. The ROM socket .Iogic uses jumpers W5-W8 and W13 to select
the type of ROM that can be used on the BOV11. Table 3 shows
jumper configurations and the type of ROM or PROM used with these
configurations.
Control Registers
The BOV11 module has five hardware registers that are softwareaddressable. These registers are assigned Individual addresses that
cannot be changed or modified. The registers are described in the
following paragraphs; their deSignations and addresses are listed in
Table 4.
97
BDV11
Page Control Register (PCR) - This register is word- or byte-addressable and can be read or written. The peR is a 16-bit register that
consists of two 8-bit bytes. The low byte consists of bits 0-7 and the
high byte consists of bits 8-15. When the low byte of the peR is equal
to page 6, then bus addresses 173000-173777 accesses the 128 ROM
locations in the block '1400-1577. When a bus address falls in this
range, the logic considers only the low byte of the peR. However, if the
bus address is in the range 173400-173777, only the high byte of the
PCR is used to select the ROM location.
Table 3
Chip Selection Jumpers
Jumpers Inserted 1
ROM Type
W5
27082
27163
8316E4
8316E5
R
R
W6
W7
we
W13
I
R
I
I
R
I
R
I
R
R
R
I
R
R
R
R
NOTES
1. I = Inserted; R = Removed.
2. CB2 and DB2 must be supplied with external -5 V power.
3. Use only +5 Vdc type components.
4. Chip select signals must be programmed as follows:
5.
CS1
CS2
CS3
LOW
LOW
LOW
Chip select signals must be programmed as follows:
CS1
LOW
CS2
LOW
CS3
HIGH
98
BDV11
Table 4
Standard Assignments
Register
Readl
Write
Size
Address
Page Control
Read/Write
Configuration *
Display*
BEVNT*
R/W
R/W
R
W
W
16 bits
16 bits
12 bits
4 bits
1 bit
177520
177522
177524
177524
177546
*
Dual-purpose register.
Table 5 relates the PCR contents to the peR page for pages 0-17. If the
peR is loaded with data 000400, the peR low byte contains data 000,
while the high byte contains data 001. The peR bytes can be loaded
separately. To select ROM locations 1600-1777, for instance, one need
only load the peR high byte with page 7; thus, the high byte contains
007, while the low byte ·can contain anything. Table 6 lists the PCR
contents for the remaining peR pages.
Read/Wrlte Register - This register is used as a maintenance register for the diagnostic programs. The register is cleared when power is
turned on or when the RESTART switch is activated.
Configuration Register - This 12-bit read-only register is used to
select for execution diagnostics or bootstrap programs for maintenance and system configuration. Bits 0-11 of the register are set by
switches E15-1 through E15-8 and E21-1 through E21-4. These
switches are associated with BDAL(0:11 )L, when an individual switch
is closed (on), the corresponding BDAL signal is low (1).
Display Register - This 4-bit register is used for program control of
the diagnostic LED display. When bits 0-3 of the register are set, then
the corresponding LEOs are off. The register is cleared by turning
power ON or by activating the RESTART switch.
99
BDV11
TableS
PCRPage
0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
PCR Contents/Page Relationship, Pages 0-17
PCR Contents
PCR High Byte PCR Low Byte
(Bits 15-8)
(Bits 7-0)
000400
001
000
001402
003
002
002404
005
004
003406
007
006
004410
011
010
005412
013
012
006414
015
014
007416
017
016
Table 6
Pages 20-57, 200-377
Page
Contents
Page
Contents
20,21
22,23
24,25
26,27
30,31
32,33
34,35
36,37
010420
011422
012424
013426
014430
015432
016434
017436
260,261
262,263
264,265
266,267
270,271
272,273
274,275
276,277
130660
131662
132664
133666
134670
135672
136674
137676
40,41
42,43
020440
021442
300,301
302,303
140700
141702
100
BDV11
Table 6
Page
Pages 20-57, 200-377 (Cont)
Contents
Page
Contents
44,45
46,47
50,51
52,53
54,55
56,57
022444
023446
024450
025452
026454
027456
304,305
306,307
310,311
312,313
314,315
316,317
142704
143706
144710
145712
146714
147716
200,201
202,203
204,205
206,207
210,211
212,213
214,215
216,217
100600
101602
102604
103606
104610
105612
106614
107616
320,321
322,323
324,325
326,327
330,331
332,333
334,335
336,337
150720
151722
152724
153726
154730
155732
156734
157736
220,221
222,223
224,225
226,227
230,231
232,233
234,235
236,237
110620
111622
112624
113626
114630
115632
116634
117636
340,341
342,343
344,345
346,347
350,351
352,353
354,355
356,357
160740
161742
162744
163746
164750
165752
166754
167756
240,241
242,243
244,245
246,247
250,251
252,253
254,255
256,257
120640
121642
122644
123646
124650
125652
126654
127656
360,361
362,363
364,365
366,367
370,371
372,373
374,375
376,377
170760
171762
172764
173766
174770
175772
176774
177776
BEVNT Register - Setting bit 6 (100 8) removes the clamp from
BEVNT, thus enabling the line-time clock. Under program control, the
user can clamp the BEVNT line low (thus stopping the line-time clock).
Opening the BEVNT switch disconnects this function. The register Is
cleared (disabling the line-time clock) when the power is turned ON or
when the REST ART switch is activated.
101
BDV11
PROGRAMMING
General
The BOV11 contains dip switches that let the user select diagnostic
and bootstrap programs for execution. Four LEOs indicate when a
program fails. A green LED monitors the + 12 Vdc and +5 Vdc and is
lit when power is ON. A HALT!ENABLE switch and a RESTART switch
let the user start and stop the processor. The switches and LEOs are
shown in Figure 4.
DO 0
00000
0102030604
OFF
ON
~
_2
_3
_4
_5
_6
_7
_8
OFF
ON
~
_2
_3
_4
_5
E2l
(DIAGNOSTIC/800TSTRAP
SWITCHES. BEVNT SWITCH)
Figure 4
E15
(DIAGN OSTIC/BOOTSTRAP
SWITCHES)
BOV11 Switches and Indicators
Diagnostic/Bootstrap Switches
Dip switch units E15 and E21 let the user select diagnostic programs
and! or a bootstrap program. Switches A 1-A8 represent switches 1-8
102
BDV11
of E15, and switches 81-84 represent switches 1-4 of E21. The programs selected by these switches are listed below. These 12 switches
make up the configuration register that can be read at address
177524.
Switches A 1-A4 are defined as follows:
A1
A2
A3
A4
A4
ON
ON
ON
ON
OFF
Execute CPU test upon power-up or restart.
Execute memory test upon power-up or restart.
OECnet boot-A4, 5, 6, and 7 are arguments.
Console test and dialogue (A3 OFF).
Turnkey boot dispatched by switch setting (A3 OFF).
OECnet boot arguments are:
Boot*
A4
AS
A6
DUV11
DLV11,;,E
DLV11-F
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
. A7
OFF
OFF
ON
All boots other than the OECnet boots above are controlled by the bit
patterns in switches A5 through AS and 81 (shown in Table 7) or, if the
console test is selected, by mnemonic and unit number. The console
test prompts with
xx
START?
where xx is the decimal multiple of 1024 words of RAM found in the
system when sized from 0 up in 1024-word Increments. The first word
of each 1024-word segment is read and then written back into itself.
Allowed responses are a 2-character mnemonic with a 1-digit octal
unit number or one of two special single character mnemonics. The
response must be followed by a RETURN. The special single-character mnemonics are:
y
Use switch settings to determine boot device
N
Halt-enter microcode OOT
= 175610; DLV11-F eSR
no devices from 160010 to 160036.
* DLV11-E eSR
103
= 176500; DUV11 eSR = 160040 if
BDV11
Table 7
Mnemonic
OKn; n<8
OLn; n<4
OXn; n<2
OYn; n<2
AS
A6
A7
AS
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
On
Off
Dlagnostlc/Boostrap Switch Selection
=1
=0
104
Program
Selected 1
Loop on test
RKV11 Boot
RLV11 Boot
RXV11 Boot
RXV21 Boot
ROM Boot2
BDV11
1.
2.
All unused patterns or mnemonics will default to ROM boot if
switch 82, 83, or 84 is on.
The ROM boot uses switches 82, 83, and 84 to dispatch as follows:
82
83
84
ROM
1
X
1
X
X
1
Extended diagnostic
2708
Program ROM
o
o
where X
o
= Irrevelant
.If an unrecognized mnemonic or switch setting (A5 through 81) is
encountered, 82, 83, and 84 are checked for the presence of additional ROM. If present, the ROM boot is invoked. The mnemonic's first
character is placed in the high byte location of 2. 80th characters are
converted to uppercase with bit 7 cleared. Location 0 is loaded with
the binary unit number. If an unrecognized switch setting is encountered instead, a copy of the switches is placed in location 2 with bit 15
set.
If no additional ROM exists, the switch-checking routine will halt or the
mnemonic routine will reprompt.
The above features let the user implement additional features or boots
in additional ROMs without changing to the base ROMs. If the
additional ROM encounters an unrecognized mnemonic, it should
load address 173000 into the PC, which will restart the 80V11 base
ROM and reprompt.
Diagnostic Lights
When a failure occurs in a diagnostic test or in a bootstrap program,
the diagnostic light display indicates the area of the failure as shown in
Table 8. A failure causes the error to be indicated by the display and
an error halt instruction is carried out by the processor. When entering
the halt mode, the processor outputs the PC address at the time of the
error on the console terminal. (The actual error address is one word
les~ than the terminal printout.) In the halt mode, the processor responds to console OOT commands and the operator can troubleshoot
the error. Table 9 lists the possible address and the cause of some
errors.
105
BDV11
BEVNT L Switch
Contact 5 of dip-socket switch E21 is the BEVNT L switch. When the
switch is off (open), the LSI-11 bus BEVNT L signal can be controlled
by the power supply-generated LTC signal. When the switch is on
(closed), the LTC function is program-controlled, i.e., a single-bit,
write-only register in the logic (address 177546, bit 6) clamps BEVNT L
low when the register is cleared. (The register is automatically cleared
when the power is turned on or when the RESTART switch is cycled.)
Power OK LED
This green LED is lit when the +12 Vdc supply voltage is greater than
+10 V and the +5 Vdc supply voltage is greater than +4 V for normal
operating conditions. The + 12 Vdc voltage and the +5 Vdc voltage
can be measured at the tip jacks as indicated below. (Both J2 and J3
have a 560-ohm resistor in series to prevent damage from a short
circuit; use at least a 20,000 ohm/V meter to measure the voltage.)
Jack
J1
J2
J3
Color
Black
Red
Purple
Voltage
Ground
+5 Vdc
+12 Vdc
HALT/ENABLE Switch
When this switch is in the ENABLE position, the processor can operate
program control. If the switch is placed in the HALT position, the
processor enters the halt mode and responds to console OOT commands. While in the halt mode, the processor can execute single instructions for system maintenance. Program control is reestablished
by returning the switch to the ENABLE position and entering a lip"
command at the console terminal (providing the contents of register
R7 were not changed). Refer to the appropriate processor handbook
for a description of console OOT command usage.
106
BDV11
Table 8
Diagnostic LED Error Display (D1-D4)*
D4
Bit 3
D3
Bit 2
D2
Bit1
D1
BltO
Comments*
(Type of Error)
On
On
On
On
Off
Off
Off
On
Off
Off
On
Off
Off
Off
Off
On
On
Off
On
Off
Off
Off
On
On
Off
On
On
Off
Off
On
On
On
On
Off
Off
Off
On
On
Off
Off
Off
On
On
Off
System hung; halt switch on
or power-up mode wrong.
CPU, fault, or configuration
error.
Memory error; R1 points to bad
location.
Console SLU will not transmit.
Waiting for response from
operator.
Load device fault.
Secondary boot incorrect
(location 0 not a NOP).
DEC net waiting for response
from host.
DEC net; received done flag
set.
DECnet; message received.
ROM bootstrap error.
.. The light pattern indicates the corresponding test is in progress or failed.
Some tests retry (DECnet) and others will halt the CPU (CPU, memory, nonDECnet boots).
Table 9
List of Error Halts
Address
of Error
Cause of Error
173022
Memory error 1. Write address into itself.
173040
SLU switch selection incorrect. Error in switches.
173046
SLU error. CSR address for selected device. Check
CSR for selected device in floating CSR address
area.
107
BDV11
Table 9
Address
of Error
List of Error Halts (Cant)
Cause of Error
173050
CP1 error. RO contains address of error.
173052
Memory error 2. Data test fai/ed.
173106
Memory error 3. Write and read bytes failed.
173202
ROM loader error. Checksum on data block.
173240
CP4 error. RO contains address of error.
173366
ROM loader error. Checksum on address block.
173402
ROM loader error. Jump address is odd.
173532
RL device error.
173634
CPU error 3. RO pOints to cause of error.
173642
In console terminal test, a "no" typed.
173656
RK device error.
173656
Switch mode halt. Match was not made with switches.
173670
Console terminal test. No done flag.
173706
CPU error 2. RO pOints to cause of error.
173712
RX device error.
RESTART Switch
When the RESTART switch is cycled, i.e., moved from one side to the
other and back, the CPU automatically carries out a power-up sequence. Thus, for maintenance purposes, the system can be rebooted
at any time.
Addressing ROM on the BDV11 module
A block of 256 LSI-11 bus addresses is reserved to address the ROM
locations on the BDV11 module. This block resides in the upper 4K
address bank (28K-32K), which is normally used for peripheral-device
addressing, and consists of byte addresses 173000-173776.
108
BDV11
All 2048 locations in a selected 2K ROM (or 1024 locations in a 1K
ROM) can be addressed by justthese 256 bus addresses. The logic
includes a page control register (peR) at bus address 177520; the
contents of this read/write register determine which specific ROM
location is accessed when one of the 256 bus addresses is placed on
the BDAL lines. The peR is loaded with "page" information, i.e., the
peR contents point to 1 of 16 (or 1 of 8) 128-word pages in the selected ROM (16 pages X 128 words = 2048 words). For example, if the
peR contents represent pages 0 and 1, then bus addresses 173000173776 access ROM locations 0000-0377; if the peR contents represent pages 10 and 11, then bus addresses 173000-173776 access
ROM locations 2000-2377. Table 10 relates bus addresses, peR
pages, and ROM locations.
At the top of each column of peR pages in Table 10 appear two circuit
component designations; column 1, for example, is headed by
E53/E48. These designations represent the ROMs and EPROMs that
one might find on a BDV11 module. For instance, the BDV11 is supplied with 2K words of diagnostic ROM. The ROM inserted in socket
XE53 supplies the high byte (bits 8-15) of these 2K words, while the
ROM inserted in socket XE48 supplies the low byte (bits 0-7). To access the BDV11 diagnostic ROM locations, the user must load the peR
with the pages in column 1; thus, when 12 and 13, for example, are
loaded into the peR, diagnostic ROM locations 2400-2777 can be
addressed by the LSI-11 BDAL signals. Another variation of the
BDV11 could have 1K-word EPROMs inserted in sockets XE57 -XE40
(E57 supplies the high byte, while E40 supplies the low byte). To access these EPROM locations, the user would load the peR with pages
in column 3; thus, with 44 and 45 in the peR, EPROM locations 10001377 are accessible.
109
Table 10
BDV11 Bus Address/PCR Pages
PCRPages
ROM
Location
Bus Address
Accessed
......
......
0
E53/ E58/ E57/ E52/ E54/ E59/ E60/ E55/ E51/ E47/ E43/ E39/
E48
E44 E40 E36 E49 E45 E41
E37 E38 E42 E46 E50
173000-173376
0000-0177
173400-173777
0200-0377
0
20
40
50
200 220 240 260 300 320 340
360
1
21
41
51
201
341
361
173000-173376
0400-0577
173400-173777
0600-0777
2
22
42
52
202 222 242 262 302 322 342
362
3
23
43
53
203 223 243 263 303 323 343
363
173000-173376
1000-1177
173400-173777
1200-1377
4
24
44
54
204 224 244 264 304 324 344
364
5
25
45
55
205 225 245 265 305 325 345
365
173000-173376
1400-1577
173400-173777
1600-1777
6
26
46
56
206 226 246 266 306 326 346
366
7
27
47
57
207 227 247 267 307 327 347
367
221
241
261
301
321
III
C
<
.....
.....
Table 10 BDV11 Bus Address/PCR Pages (Cont)
PCRPages
ROM
Location
Bus Address
Accessed
10
30
210 230 250 270 310 330 350
370
11
31
211 231
251 271 311 331 351
371
173000-173376
2400-2577
173400-173777
2600-2777
12
32
212 232 252 272 312 332 352
372
m
13
33
213 233 253 273 313 333 353
373
<
...a.
173000-173376
3000-3177
173400-173777
3200-3377
14
34
214 234 254 274 314 334 354
374
15
35
215 235 255 275 315 335 355
375
16
36
216 236 256 276 316 336 356
376
17
37
217 237 257 277 317 337 357
377
173000-173376
2000-2177
173400-173777
2200-2377
~
~
E53/ E58/ E57/ E52/ E54/ E59/ E60/ E55/ E51/ E47/ E43/ E39/
E48 E44 E40 E36 E49 E45 E41 E37 E38 E42 E46 E50
173000-173376
3400-3577
173400-173777
3600-3777
C
...a.
BDV11
As Table 10 implies, the PCR pages are assigned to specific module
ROM sockets. Furthermore, the sockets ,are assigned specific kinds of
ROMs, as Table 11 indicates, e.g., the diagnostic/bootstrap ROM can
occupy only sockets XE53 and XE48. Thus, a specific ROM can be
addressed only when the PCR contains the page or pages assigned to
the socket that the ROM occupies. For example, if 2K-word ROMs are
inserted in sockets E39 and E50, they can be addressed only when the
PCR contains pages 360-377. The page/socket assignments indicated
in Table 10 apply to the BDV11 module shipped by DIGITAL. There are
eight locations on the BDV11 printed circuit board in which jumpers
are inserted selectively to achieve these assignments. The user can
change the factory arrangement of these jumpers to cause the CPU to
execute instructions directly from a ROM or EPROM of the user's
choice when power is turned on, rather than from the diagnostic
ROMs.
Table 11
Functions of ROM Sockets
Sockets
ROM
Function
Sockets
ROM
Function
XE53/XE48
2K Diagnostic/Bootstrap
XE47/XE42
2KSystem
ROM
XE58/XE44
2K Diagnostic/
Bootstrap
(reserved for
DIGITAL)
XE51/XE38
2KSystem
ROM
XE57/XE40
1KEPROM
XE55/XE37
2KSystem
ROM
XE52/XE36
1KEPROM
XE60/XE41
2KSystem
ROM
XE39/XE50
2KSystem
ROM
XE59/XE45
2KSystem
ROM
XE43/XE46
2KSystem
ROM
XE54/XE49
2KSystem
ROM'
112
BDV11
Loading ROM Into RAM
A utility is provided in the BDV11 firmware which loads user programs
from ROM to RAM at specified (and possibly scattered) addresses and
transfers control to a specified address. This allows a programmer to
write a program (to be stored in ROM) without knowing the BDV11
mapping hardware or having to "ROMize" the program. This utility
loads the DIGITAL-reserved space, the 2K EPROM, or the 16K
ROM/EPROM areas. The utility uses the four highest words of RAM
( <30K) as scratch space.
The format is a modified version of absolute loader paper tape format.
\ The standard format consists of sequential blocks, organized by byte,
as follows:
1 BYTE
oBYTE
BCl
BCH
ADL
ADH
. DATA
CKB
This indicates start of block.
Required.
Low-order eight bits of byte count.
High-order eight bits of byte count.
Low-order eight bits of load address.
High-order eight bits of load address.
Sequential bytes of data.
Checksum byte.
These frames are repeated as required until a starting address block
is encountered. This is Indicated by a byte count of six, which is too
short to allow a data field. The load address of this block is used as the
starting address.
The format skips every 255th and 256th location in the ROM pattern.
These locations are filled with checking information which allows
DIGITAL diagnostics to determine whether the ROMs are good and
Inserted in the correct socket.
The ROMs should be inserted as Indicated by the ROM address chart.
The user program may be patched by changing only the last ROM of a
set and by adding a new data block(s) before the starting address
block. This block will overlay previously loaded data.
Executing ROMs In the I/O Page
ROMs may be executed In the I/O page provided their starting address is between 173016 and 173376. The next page lists a program
which executes In the I/O page. It uses the ROM loader but supplies
only a starting address block. It must start In the window between
173000 and 173376 Since the ROM boot Is executing out of the other
window. It Is the programmer's responsibility to properly map the upper window and then manage all remapping.
113
DCK11-AA,-AC
DCK11·AA, ·AC PROGRAM TRANSFER INTERFACE
GENERAL
The OCK11-AA and -AC CHIPKITs provide the logic necessary for a
program transfer Interface to the LSI-11 bus.
The DCK11·AA kit contains:
1-0C003 Interrupt Chip
1-0C004 Protocol Chip
4-0C005 Transceiver/Address Decoder/Vector Select Chips
The DCK11·AC kit contains the above chips plus:
1-W9512 double-height, extended-length, high-density wlre-wrappable module
1... BC070-10 ten-foot, 40-conductor plug-In cable
Figure 1 shows a schematic of the program control CHIPKIT part of a
user's Interface.
FEATURES
DC003 Interrupt Logic IC Features
• Two Interrupts (A & B) per OC003
• Interrupt enable flip-flop on the IC
• Enable flip-flop outputs available to the user
• Interrupts Initially disabled by BUS INIT
.- VECTOR output to the OC005s to gate the Interrupt Vector address
directly onto the lSI-11 bus
• Interrupt B generates the second LSB of vector address directly
(VECRQST B H)
• BUS INIT buffered and made available to the user (INITO L)
• Contains logic for LSI-11 bus "daisy-chained" Interrupts
DC004 Protocol Logic IC Features
• Device selection features
Four register select lines (SEL 6 L, SEL 4 L, SEL 2 L, SEL 0 L)
High and low byte output select lines (OUTHB L, OUTLB L)
Input select line (INWO L)
Enable Input from higher level decode (ENB H)
• Bus functions
Bus reply generated for device addresses and for Interrupts
(BRPLY l)
Ability to vary bus reply response by adding an RC network
provided (RXCX H)
114
DCK11-AA,-AC
DCOOS Bus Transceiver IC Features
• Four bits per IC
• Three bits of address selection logic Included on the chip
• LSI-11 bus drivers and receivers
Drivers-open collector with 70 mA sink capability.
Receiver-55 /LA Input loading. (BUS 0-3L)
• Internal3-state bus drivers and receivers
Drlvers-20 mA sink
Receivers-standard TTL (OAT 0-3 H)
• Address selection
Enab.le input ~or use with a higher level decoded Input (MENB L)
Address bits may be excluded from comparison by tying them
to VCC (JA(3:1)L)
• Interrupt Vector
Vector address bits "ORed" directly onto LSI-11 bus (JV(3:1 )H)
SPECIFICATIONS
For complete Electrical Specifications refer to EJ 17475. A summary of
the more Important specifications follow the pin/signal descriptions
for indlvlduallCs.
DC003 Pin/Signal Descriptions
Pin
2
Signal
Description
VECTORH
Interrupt Vector Gating. This signal should
be used to gate the appropriate vector address onto the bus and to form the bus signal called BRPLY L. Type: TTL-OUTPUT
VECRQSTB H
Vector Request "B." When asserted, Indicates RQST "B" service vector address Is
required. When unasserted, Indicates
RQST "A" service vector address Is required. VECTOR H Is the gating signal for
the entire vector address; VECRQSTB H Is
normally bit 2 of the vector address. Type:
TTL-OUTPUT
115
DCK11-AA, -AC
DC003 PlnlSlgnal Descriptions (Cont)
Pin
Signal
Description
3
BDINl
Bus Data In. This 'slgnal, generated by the
processor BDIN, always precedes a BIAK
signal. Type: BUS-INPUT
4
INITOl
Initialize Out. This Is the buffered BINIT l
signal used In the device Interface for generallnltlallzatlon. Type: OPEN COLLECTOR
WITH 1K PUll UP - OUTPUT
5
BINITL
Bus Initialize. When asserted, this signal
brings all driven lines to their unasserted
state (except INITO L). Type: BUS-INPUT
6
BIAKO L
Bus Interrupt Acknowledge (Out). This slgnails the daisy-chained signal that Is
passed by all devices not requesting Interrupt service (see BIAKI L). Once passed by
a device, It must remain passed until a new
BIAKI l Is generated. Type: BUS-OUTPUT
7
BIAKIL
Bus Interrupt Acknowledge (In). This signal
Is the processor's response to BIRO L true.
This signal Is daisy-chained such that the
first requesting device blocks the signal
propagation while non-requesting devices
pass the signal on as BIAKO l to the next
device In the chain. The leading edge of
BIAKI L causes BIRO L to be unasserted by
the requesting device.
Type: BUS-INPUT
8
BIROL
Bus Interrupt Request. This signal Is generated when this device needs to Interrupt the
processor. The request Is generated by a
false to true transition of the ROST signal .
along with the associated true Interrupt enable signal. The request Is removed after
the acceptance of the BDIN L signal and on
the leading edge of the BIAKI L signal or the
removal of the associated request signal.
Type: BUS-OUTPUT
116
DCK11-AA, -AC
DC003 Pin/Signal Descriptions (Cont)
Pin
Signal
Description
10
17
RaSTB H
RaSTA H
Device Interrupt Request. When asserted
with the enable flip-flop set, will cause the
assertion of BIRa l on the bus. This signal
line normally remains asserted until the request Is serviced. Type: BUS-INPUT
11
16
ENBST H
ENAST H
Interrupt Enable Status. This slgnallndlcates the state of the Interrupt enable Internal flip-flop which Is controlled by the signal
ENX (where X Is either A or B) DATA H, and
the ENX (where X Is either A or B) ClK H
clock line. Type: TTL-OUTPUT
12
15
ENBDATA H
ENADATA H
Interrupt Enable Data. The level on this line,
In conjunction with the ENX (where X Is either A or B) ClK H signal, determines the
state of the Internal Interrupt enable flipflop. The output of this flip-flop Is monitored
by the ENX (where X Is either A or B) ST H
signal. Type: TTL-INPUT
13
14
ENBClKH
ENAClKH
Interrupt Enable Clock. When asserted (on
the positive edge), Interrupt enable flip-flop
assumes the state of the ENX (where X Is
either A or B) DATA H, slgn81l1ne. Type:
TTL-INPUT
Summary of Electrical Specifications for DC003
Ambient Temperatures
O°C to 70°C
TTL Input
High-level Input current
50ILA max.
IIH(V=2.7V)
low-level input current
I IdV 1=0.5V)
-.55 mA max.
exceptions
Pins 12 & 15 ENX DATA H
IIH 100 ILA max.
IlL = -2.0 mA max.
=
117
DCK11-AA, -AC
TIL Outputs
High-level output voltage
V OH (10 = -1 mA max.)
2.7Vmln.
Low-level output voltage
V Ol (10= 20 mA max.)
0.5Vmax.
Bus (HI Z) Input and (open collector) outputs.
Bus Inputs
40#LA max.
High-level Input current
I IH (V I = 3.8V)
Low-level Input current
III (V 1= OV)
Bus Outputs
O.8Vmax.
Low-level output voltage
V lO (I sink = 70 mA max.)
DC004 Pin/Signal Descriptions
Signal
Description
VECTORH
Vector. This Input causes BRPLY L to be
generated through the delay circuit. Independent of BSYNC Land ENB H. Type:
TTL-INPUT
2
3
4
BDAL2 L
BDAL1L
BDALO L
Bus Data Address Lines. These signals are
latched at the assert edge of BSYNC L.
Lines 2 and 1 are decoded for the select
outputs; line 0 Is used for byte selection.
Type: BUS-INPUTS
5
BWTBTL
Bus Write/Byte. While the BDOUT L input is
asserted, this signal indicates a byte or
word operation: asserted = byte, unasserted = word. Decoded with BDOUT Land
latched!BDALO L to form OUlLB Land
OUTHB L. Type: BUS-INPUT
Pin
118
DCK11-AA, -AC
DC004 Pin/Signal Descriptions (Cont)
Pin
Signal
Description
6
BSYNCL
Bus Synchronize. At the assert edge of this
signal, address Information Is trapped In
four latches. While unasserted, disables all
outputs except the vector term of BRPLY L.
Type: BUS-INPUT
7
BDINL
Bus Data In. This Is a strobing signal to effect a data Input transaction. Generates
INWD Land BRPLY L through the delay circuit and INWD L. Type: BUS-INPUT
8
BRPLY L
Bus Reply. This signal Is generated through
an RC delay by VECTOR H, or BDIN L, or
BDOUT L and the AND of BSYNC Land
latched ENB H. Type: BUS-OUTPUT
9
BDOUTL
Bus Data Out. This Is a strobing signal to
effect a data output transaction. Decoded
with BWTBT Land BDALO to form OUTLB L
and OUTHB L. Generates BRPLY L through
the delay circuit. Type: BUS-INPUT
11
INWDL
In Word. Used to gate (read) data from a
selected register onto the data bus. Enabled by BSYNC L and strobed by BDIN L.
Type: TTL-OUTPUT
12
13
OUTLB L
OUTHB L
Out Low Byte. Out High Byte. Used to load
(write) data into the lower, higher, or both
bytes of a selected register. Enabled by
BSYNC L and decode of BWTBT Land
latched BDALi) L, and strobed by BDOUT L.
Type: TTL-OUTPUT
14
15
16
17
SELOL
SEL2L
SEL4L
SEL6L
Select Lines. One of these four signals is
true as a function of BDAL2 Land BDAL 1 L
If ENB H Is asserted at the asserted edge of
BSYNC L. They Indicate that a word register
has been selected for a data transaction.
These signals never become asserted except at the assertion of BSYNC L (then only
119
DCK11-AA, -AC
DC004 Pin/Signal Descriptions (Cont)
Pin
Signal
Description
If ENB H Is asserted at that time) and once
asserted, are not unasserted until BSYNC L
becomes unasserted. Type: TTL-OUTPUT
18
RXCXH
External Resistor Capacitor Node. This
node Is provided to vary the delay between
the BDIN L, BOOUT L, or VECTOR H Inputs
and BRPLY L output. The external resistor
should be tied to V cc and the capacl~or to
ground. As an output, It Is the logical inversion of BRPLY L. Type: OPEN-COLLECTOR OUTPUT
19
ENBH
Enable. This signal Is latched at the asserted edge of BSYNC L and Is used to enable
the select outputs and the address term of
BRPLY L. Type: TTL-INPUT WITH 8500
PULL UP
Summary of Electrical Specifications for DC004
Ambient Temperatures
TTL Inputs
High level input current
I IH (V I = 2.7V)
501LAmax.
Low level input current
I IL (V I = 0.5V)
-.70 rnA max.
Pin 19 ENB H
Exceptions
IIH = -3.85 rnA max.
IlL
= -8.0 rnA max.
TTL Outputs
High Level output voltage
V OH (I 0 = -1 rnA)
2.7Vmin.
Low level output voltage
V OL (I 0 = 20 rnA)
0.5Vmax.
Bus (HI- Z) Inputs and (Open Collector) Outputs
Bus inputs
120
DCK11-AA, -AC
High level Input current
I IH (V I = 3.8V)
40 ",A max.
low level Input current
IlL (V 1= OV)
-10",A max.
Bus Outputs
low level output voltage
V LO (I sink = 70 rnA)
0.8Vmax.
Deoos Pin/Signal Descriptions
Pin
Signal
Description
12
11
9
8
BUS(3:0) l
BUSOl
BUS1L
BUS2L
BUS3L
Bus Data. This set of four lines constitutes
the bus side of the transceiver. Open collector outputs; high-Impedance Inputs. low=
1. Type: BUS-INPUTIOUTPUT
18
17
7
6
DAT(3:0) H
DATOH
DAT1 H
DAT2H
DAT3H
Peripheral Device Data. These four trl-state
lines carry the Inverted received data from
BUS (3:0) when the transceiver Is In the receive mode. When In transmit data mode,
the data carried on these lines are passed
Inverted to BUS (3:0). When In the disabled
mode, these lines go open (HI-Z). High = 1.
Type: TTL-INPUTS
16
JV(3:1) H
JV1 H
JV2H
JV3H
Vector Jumpers. These Inputs, with Internal
pull-down reSistors, directly drive BUS
(3:1). A low or open on the Jumper pin will
cause an open condition on the corresponding bus pin If XMIT H Is low. A high will
cause a one (low) to be transmitted on the
bus pin. Note that BUSO L Is not controlled
by any jumper Input. TYPE: TTL-INPUT
WITH PULL DOWN
13
MENBl
Match Enable. A low on this line will enable
the Match output. A high will force MATCH
low, overriding the MATCH circuit. TYPE:
BUS-INPUT
14
15
121
DCK11-AA, -AC
DCOOS Pin/Signal Descriptions (Cont)
Pin
Signal
Descriptions
3
MATCHH
Address Match. When BUS (3:1) match with
the state of JA (3:1) and MENB L Is low, this
output Is open; otherwise It Is low. TYPE:
BUS-OUTPUT
1
2
19
JA(3:1) L
JA1 L
JA2L
JA3L
Address Jumpers. A strap to ground on
these Inputs will allow a match to occur with
a 1 (low) on the corresponding BUS line; an
open will allow a match with a 0 (high); a
strap to V cc will disconnect the corresponding address bit from the comparison.
TYPE: TERNARY-INPUT (SEE TEXT)
S
4
XMITH
RECH
Control Inputs. These lines control the operation of the transceiver as follows:
.
REC
o
o
1
1
XMIT
o
1
DISABLE:BUS,DAT open
XMIT DATA:DAT~BUS
1
RECEIVE:BUS~DAT
o
RECEIVE:BUS~DAT
To avoid 3-state signal overlap conditions.
an Internal circuit delays the change of
modes between XMIT DATA and RECEIVE
mode and delays 3-state drivers on the OAT
lines from enabling. This action Is Independent of the DISABLE mode.
Summary of Electrical Specifications for DCOOS
Ambient Temperatures O°C to 70°C
TTL Inputs
High level input current
I IH (V I = 2.7V)
REC H Pin4
100p.Amax.
XMITHPinS
SOp.Amax.
Low level input current
I IL (V I = O.SV)
122
DCK11-AA, -AC
REC H Pin 4
-2.2 mA max.
XMIT H Pin 5
-1.1 mA max.
TTL Outputs
High Level output voltage V OH (10 = -1
MA)
Low level output voltage V OL (10 = 20 mA)
3.65V min.
0.5V max.
Bus (HI-Z) Inputs an,! (Open Collector) Outputs
Bus Inputs
High level Input current 65 IJ-A max.
IIH (V I = 3.8V)
Low level input current
IlL (V I = 0.5V)
Bus Outputs
low level output voltage V LO (I sink = 70
mA)
-10 IJ-A max.
0.8V max.
DESCRIPTION
PROGRAM CONTROL CHIPKIT APPLICATION
In Figure 1, the transceivers (four DC005s) provide data lines DO
through 015 to reflect the state of the bus lines BDAL 0-15, when REC
H Is asserted, and to drive the BDAl lines when XMIT Is asserted.
Address and Interrupt vector Information for Interrupt request and
device selection Is also provided by the DC005. The device address Is
set up using Input lines A3 through A12, while the Interrupt vector
address Is set up using Input lines V3 through V8.
When the address lines (JA Inputs on DC005s) match the state of the
associated BDAL lines, the MATCH output will float high such that all
DC005s will let ENB H on the DC004 be asserted, thus enabling the
DC004 to look for proper synchronlzln"g signals from the bus. Once
these synchronizing Signals (BDIN, BDOUT, BSYNC, and BWTBT) are
present, the OC004 generates the control signals (INWO, OUTHB,
OUTlB, and SEl 0, 2, 4, 6) for the user's device.
The protocol logic (DC004) functions as a register selector to provide
123
DCK11-AA, -AC
the signals necessary to control data flow Into and out of the user's
registers. When the proper device address has been decoded by the
device address comparator (all OC005s), the MATCH outputs let the
ENBH Input go high, thus enabling the OC004 protocol logic. Address
bits 001 Hand 002 H are decoded by the protocol logic, producing
one of the SEl outputs, while bit DO and BWTBT are decoded for
output word/byte selection (OUTHB l, OUTlB l). The device select
line (SEl 0, 2, 4, 6) and word/byte select lines (INWO l, OUTHB l,
OUTlB l) are used by the user's logic. Each SEl output Is used to
select one of four user's registers, and the word/byte lines are used to
determine the type of transfer (word or byte) to or from these registers.
Either BDIN l or BDOUT l, depending ·on the type of bus cycle, will
Initiate a delay whose value is dependent on the time constant of the
RC network connected to pin RXCX H of the DC004. The end of this
delay will initiate a reply to the CPU Indicating that the address has
been received.
The Interrupt logic (DCOO3) performs an Interrupt transaction. Twochannels (A and B) are provided for generating two Interrupt requests,
with channel A having the highest priority. The Interrupt enable flipflop within the lnterrupt logic must first be set when the user's device Is
to Interrupt the lSI-11. This Is accomplished by asserting (logic H) the
ENX DATA * line and then clocking the enabled flip-flop by asserting
the ENX ClK* line. With the Interrupt enable flip-flop set, the user's
device may then make an Interrupt request by asserting (logic H)
RQSTX*. When RQST Is asserted and the Interrupt enable flip-flop Is
set, the Interrupt logic asserts BIRQ l to the bus which Initiates the bus
"handshake" operation. This operation terminates with the generation
of the vector address by the DC005 under the control of the DC003,
and it's signals VECTOR Hand VECRQSTB H.
The Interrupt logic available to- the user Indicates the status of the
interrupt logic enable flip-flops. Each line Is asserted (logic H) when
the appropriate Interrupt enable flip-flop Is set. These status lines can
function as part of the user's control status register (CSR). The
VECRQSTB H line Is asserted (logiC H) when the device connected to.
channel B has been granted use of the bus for Interrupt vector transfer
operation. When VECRQSTB H Is unasserted (logic l), the user's device connected to channel A of the tnterrupt logic has been granted
use of the bus. The INITO L output from the Interrupt logic can be used
to initialize the user's toglc.
*
x may be either A or B depending on which half of the Interrupt logic Is being
enabled.
124
DCK11-AA, -AC
--II
DOUllLlf------+--IDlO
::men --:
~2
~
ovo·
I:.
DO
DO"~~
lVl!Jt-h ·sv
1Vl1!t!.."!. tJV'iTr----
-::j.L
=
1
- _
Al2 L
on
oW 1100u"
2'~
__ _
2
-,
'
NOTE:
CLOSE SWITCH FOR ONE
OPEN SWITCH FOR ZERO
Figure 1
DCK11 Bus Interface Typical Application
125
DCK11-AA, -AC
DC0031nterrupt Logic (DEC #19-12730-00)
The interrupt chip Is an 18-pln, 0.762 cm center x 2.349 cm long (max)
(0.3 in. center X 0.925 In. long) dual-in-line-package (DIP) device that
provides the circuits to perform an Interrupt transaction In a computer
system that uses a daisy-chain type of arbitration scheme. The device
Is used In peripheral Interfaces to provide two Interrupt channels labeled UA" and uB," with the A section at a higher priority than the B
section. Bus signals use high-Impedance Input circuits or high-current
open collector outputs, which allow the device to directly attach to the
computer system bus. Maximum current required from the Vee supply Is 140 mAo
Figure 2 is a simplified logic diagram of the DC003 IC. Table 1 describes the signals and pins of the DC003 by pin and signal name.
Figure 2
DC003 Simplified Logic Diagram
126
DCK11-AA, -AC
DC004 Protocol Logic (DEC # 19-12729-00)
The protocol chip Is In a 20-pln 0.762 cm center X 2.74 cm long (0.3 In.
center X 1.08 In. long) DIP device that functions as a register selector,
providing the signals to control the data flow Into and out of up to four
word registers (eight bytes). Bus signals can directly attach to the
device because receivers and drivers are provided on the chip. However, the OC004 Is now ordinarily used with the user's three-state bus
to limit Bus loading. An RC delay circuit Is provided to slow the response of the peripheral Interface to data transfer requests. The circuit Is designed such that If tight tolerance Is not required, then only an
external 1K ±20 percent resistor Is necessary. External RCs can be
added to vary the delay. Maximum current required from the Vee
supply Is 120 mAo
Figure 3 is a simplified logiC diagram of the OC004 IC. Signals and pin
definitions for the OC004 are presented In Tabl.~ 2.
NOTE
The pin names shown In this diagram are for the
situation where the OC004 Is connected to the Internal 3-state bus of the OC005s, not connected directly
to the LSI-11 bus.
-"
vee
_1M
S£LOL
S£L2L
aorNL
BIIPLY L
BDOUT L
GIlD
aWTBT L
1
8
BEL4 L
SEL8L
OUTLS L
to
GUTKB L
llllWDL
---cI>-li-==---j---J
Figure 3
OC004 Simplified Logic Diagram
127
DCK11-AA, -AC
Deoos Transceiver Logic (DEC # 19-13040)
The 4-bit transceiver Is a 20-pln, 0.762 cm center x 2.74 cm long (0.3
in. center X 1.08 in. long) DIP, low-power Schottky device; Its primary
use is in peripheral device interfaces to function as a bidirectional
buffer between a data bus and peripheral device logic bus. It also
includes a comparison circuit for device address selection and a
constant generator for interrupt vector address generation. The bus
I/O port provides high-Impedance Inputs and high drive (70 mA)open
collector outputs to allow direct connection to a computer data bus
structure. On the peripheral device side, a bidirectional port Is also
provided, with standard TTL Inputs and 20 rnA, trl-state drivers. Data
on this port are the logical Inversion of the data on the bus side.
Three address "jumper" Inputs are used to compare against three bus
inputs to generate the signal MATCH. The MATCH output is open
collector, which allows the output of several transceivers to be wlreANDed to form a composite address match signal. The address jumpers can also be put Into a third logical state that disables jumpers for
"don't care" address bits. In addition to the three address jumper
inputs, a fourth high-Impedance Input line Is used to enable/disable
the MATCH output.
Three vector jumper Inputs are used to generate a constant that can
be passed to the computer bus. The three Inputs directly drive three of
the bus lines, overriding the action of the control lines.
Two control signals are decoded to give three optional states: receive
data, transmit data, and disable.
Maximum current required from the Vee supply is 120 mAo
Figure 4 is a simplified logic diagram of the DC005IC. Signal and pin
definitions for the DC005 are presented In Table 3.
128
DCK11-AA, -AC
20 Vee
JA' L
JA2 L
'9 JA3 L
'8 DATO H
MATCH H 3
REC H
DAT2H
7
'7 DATI H
'6 .tV3H
15 JVa H
JV,tt
BUS3 L
8
i3
BU52 L
9
la BUSO L
IIMITH
DAT3H
GND
DCDD5
,4
n
'0
MENSL
BUSI L
DATO
H
8USO
~--------------------~(1~:r=i==~Jr
>--"--+-r
BUS'
·~
8U52
____________+-____
DATI
H
~(l~:r~==r:rN2
~""""~r
L
JVI
DATZ
H
.lA2
l-------------~------~Clt::7_t==~rN3
~........t---,r
BUS3
JA3
MENB
___________.!::=::lJ1r---------,-
DAT3
H
H
MATCH H
liMIT
REC
IC·DCOO5
Figure 4
DC005 Simplified Logic Diagram
CONFIGURATION
The drawings on the following pages show sample circuits that may be
helpful in applying the CHIPKITS.
129
DCK11-AA, -AC
OUTPUT
REGISTER
USER
Deoos'S
(aUS
TRANSCEIVERS)
INPUT
(3-STATE
DRIVERS)
OPTIONAL
INPUT
REGISTER
r------,
i
:
, - - - / /'-----1 Q
1
D~USER
~
I
1
I
L ____ .J
Figure 5
Data Path Flow Diagram
OUTPUT REGISTER HIGH BYTE
3-STATE
DRIVERS
~~~:~~ --f--+----l0
>---+--'--- TO
Q
USER
C
74LS374
FROM (OUTHB
OCOO4
SELX
WRITE OUTPUT
REGISTER
HIGH BYTE
L
OUTPUT REGISTER LOW BYTE
3-STATE
DRIVERS
~MO~ROiis'-~--+---1 0
Q
">--I---.t--- TO USER
C
74LS374
FROM OUllB
SELX
OCOO4
L
L
Figure 6
WRITE OUTPUT
REGISTER
HIGH BYTE
Example of Output Register
130
DCK11-AA, -AC
lOW BYTE
TO De005
INTERNAL BUS
(lOW ORDER
8 BITS)
8
3-STATE
DRIVERS
----r---;-",
~---4Q
STROBE
~--FROM
USER
FROM
DC004
74lS374
READ DATA
LOW BYTE l
74lS32
INWD L - - - - < 1
'"
SElX l - - - o Q
Figure 7. Example of Input Register (BYTE)
LOW BYTE REGISTER
8
r
3-STATE
DRIVERS
---IJe---+-c;;. 1 - - - - 4 Q
~
o I--+-~f--~
FROM
USER
tC~t-
74lS374
TO De005
INTERNAL
BUS
HIGH BYTE REGISTER
3-STATE
DRIVERS
D~~~f-j8_ _ FROM
,
ole
USER
r--~
STROBE
74 LS374
74lS32
FROM (INWO l ~
READ DATA
OC004 SElX L --:-;-----DATN L
H
~_+___.--'iRMI4~+5 V
:~~~ ~
12
15 RPLY H
'DISCRETIONARY WIRING
H = 4 XFERS MAX.
L = BURST MODE
Cl
~IBOpf
Figure 4
Typical Application (DC006, DC010, Output Delay, and
Input Drives)
(Sheet 1 of 2)
146
DCK11-AB, -AD
>"'-------------------.----oATA1S
.------------------+.~---OATAI4
.-----------------.j...j..,~-- OATA13
.---------------+J..h..---
OATA12
. - - - - - - - - - - - - - - - I + f . + , - - OATA11
. - - - - - - - - - - - - - - + - I + I - h - - OATA10
.---------------++~I-h--OATM
.------------~4+~I-h-OATM
Jl
3 CLKA
II
OUTH8 L
SELOL
SEL2 L
INWDL
' : CLKC
18 CNTIA
2 LO
195-A
S 5-C
4:~.A
:~
1280/F ::
19
IA
8 D4
D5 12
Q4 9
H
K
3 01
QI
008
7
Q8
:~~~~1~3-....L~-I+1-!,~4 DB
~:: ~
160fFI-JI~2---4++-~1~3 OS
BO/F 11
40/F
:
~~:~
17
~ ~~= ~
! ~~
WCNT~N~T L
E27
DC006
1
~: ~
2
5
OUT1S
OUT14
OUT13
OUTI2
OUTII
OUT10
OUTS
OUTS
I
CLR E28
74LS273
CLK
CHANH8
11
74LS387
OATA7
OATA6
OATAS
DATA4
DATA3
DATA2
DATAl
OATAO
IN 5
1~
+3V
OUTLS L
SELO L
SEL2 L
AOREN H
15
128 OfF
64 OfF 14
13
32 OfF
12
160fF
II
SOfF
9
4 OfF
8
20fF
7
I OfF
I
MAX·A
17
MAX·C
E23
0C006
CLKA
6 CLKC
18 CNTIA
2 LO
195-A
65-C
4 RO
RO·A
INIT L
18 DB
17 07
14 06
13
06
B
04
7 03
4 02
3 01
CLR
08
07
06
06
Q4
Q3
02
01
Jl
19 I U
OUT7
16 W
OUT6
16 Y
12 AA OUT6
OUT4
9 CC OUT3
6 EE
OUT2
5 HH oun
2 KK
OUTO
E24
74LS273
CLK
11
CHANLB
IN I
IN 0
Figure 4
Typical Application (DC006, DC010, Output Delay, and
Input Drives)
(Sheet 2 of 2)
147
DCK11-AB, -AD
User devices Initiate bus requests by driving the set Input of the request flip-flop (E10) low. This asserts REO to the DC010 and generates
BDMR L to the LSI-11 bus. When the DC010 becomes bus master, It
asserts ADREN H to the DC006 bus address registers. ADREN H allows the bus address registers to place the address of the slave (memory) onto the Internal bus and, via the DCOOS transceivers, onto the
LSI-11 bus. The request flip-flop (E10) remains set until the DC006
word count overfows to zero (WCNTO). WCNTO then resets the request
flip-flop.
Two DC006 word count/bus address register ICs are used to provide
16 bits each of word count and bus address. The least significant bits
of the word count and bus address register and register C Is the word
count register. Both registers can be read or written under program
control from the LSI-11 bus. Registers are selected by:
SELOL
• Read bus address reglsterINWDL
• Write high byte of bus address register
SELOL
OUTHBL
• Write low byte of bus address register
SELOL
OUTLBL
SEL2L
INWDL
• Read word count register
• Write high byte of word count register
SEL2L
OUTHB L
• Write low byte of word count register
SEL2L
OUTLBL
The bus address register Is Incremented by two for word transfers. To
accomplish the Increment by two, the CNT1 A Input to the most significant DC006 (E23) must be high, and the CNT1A Input to the most
significant DC006 (E27) must be grounded. Clocking for DC006 E23 Is
provided by the transition of the ADREN H line from the DC01 O. When
bus address register DC006 E23 overflows, MAX-A goes high, thus
clocking the DC006 E27 bus address register.
148
DCK11-AB, -AD
The word count register Is Incremented by one each time a word Is
transferred. Initially, the word count register Is loaded under program
control, with the 2's complement of the number of words to be
. transferred. As words are transferred, the word count register is incremented toward zero. When DC006 E23 overflows, MAX-C goes high.
MAX-C clocks the DC006 E27 word count register until DC006 E27
overflows. When E27 overflows, WCNTO H Is generated; WCNTO H
then resets the request flip-flop (E10), thus terminating data transfers.
During DMA data transactions Input data from the DATI bus cycle Is
placed on the Internal 3-state bus via the DC005 transceivers and Is
applied to he 74LS273 (E28 and E24) output buffers. These buffers are
then clocked by CHANHB and CHANLB, thus placing the data on the
16 OUT lines to the user's device.
For output data transfers (DATO), the user's device places data on the
16 IN lines to the 74LS367 3-state drivers. The drivers are enabled by
DATEX L, which Is asserted during a DATO cycle. The data passes
through the drivers, Is applied to the Internal 3-state bus and, via the
DC005 transceivers, to the LSI-11 bus.
Miscellaneous Logic
Miscellaneous logic Is shown In Figure 5. This logic Includes CSR,
output buffer and Input driver control, non-existent address time-out,
DC005 transceiver receive/transmit control, the control/status register
(CSR), additional transceivers (8641 s), and the liB" request flip-flop.
The CSR, output buffers, and Input driver control receive INWD L,
OUTHB L, OUTLB L, SEL 4 L, SEL 6 L, DATN H, and DIN H. These
signals are gated to produce enable signals for the CSR, the output
buffers, and the Input drivers. CSR RD Is produced by INWD Land
SEL 4 L to enable the CSR data (DATA 5 through DATA 14) (Figure 5,
sheet 1) to pass through the 74LS367 3-state drivers and onto the LSI11 bus via the DC005 transceivers. OUTHB L, OUTLB L, SEL 4 L, and
MRPLY L produce either CSRWHB L or CSRWLB L for writing bit 6 of
the CSR (74LS74 E10 on Figure 3, sheet 1), or for clocking the liB"
request flip-flop. DATEX L enables the 74LS367 3-state Input drivers
(Figure 5, sheet 1) during an IIlnput" cycle. The CHANHB and CHANLB
signals clock the 74LS273 output buffers during an "output" cycle.
When bytes are transferred, OUTHB L, MRPLY Land SEL 6 L enable
the high byte (CHANHB L asserted), while OUTLB L, MRPLY and SEL
6 L enable the low byte (CHANLB L). Both bytes are simultaneously
transferred (word transfer) when DIN H Is negated.
149
DCK11-AB, -AD
The non-existent address time-out provides a 10 P.s time-out in the
event that a non-existent address Is requested on the LSI-11 bus during a DMA operation. This prevents hanging-up the LS-11 bus for
periods longer than 10 p.s. When the DC010 becomes bus master,
ADREN H Is asserted and cocks the 10 p's one-shot (ES). Normally
RPL Y L from the LSI-11 bus goes low and the one-shot Is cleared.
However, if RPLY L is high (no response from slave), the one-shot
times out and cocks the 74LS74 flip-flop (E9). The flip-flop Is set,
generating (TOS + INIT) L; this signal Is applied to the DC010 (Figure
4, sheet 1) clearing the Internal synchronization circuit and releasing
the LSI-11 bus. The signal (TOS + INIT) H resets the request flip-flop
(E10). The 74LS74 flip-flop (E9) can be set and reset with CSRW HB
and DATA 15 (CSR bus time-out). This flip-flop Is automatically reset
during power-uD.
r ;;;:-O;;U;;;;F;;.~T-;;IV;'; C;';;R~ -
I
I
I
I
I
3
6
INWD l
8
;;;ts7e;-'
. .C;;;R~T;;;;S
(CSR) READ LOGIC
I
I
I
14~:m
ROSTA H
2
3
E1g
OATAI6
OUTHB l ------'."'-"'--...
I
MRPLV L
ENAST H 4
E19
5
DATA14
5
a
OUTHBl
I
I
I
OUTLBL
SPARES
rB~a;;T ;::F~
- - - - - -1
weN TO L
9
L
ATIN
I
I
I
II
E'G
74LS14
CSRWLB 11 C
11 C
Figure 5
I
SPARES
____
~
INIT L
~
IL _ _ _ _ _ _ _ _ _ _
~
CSRWLB
Typical Application (Miscellaneous Logic)
(Sheet 1 of 3)
150
DCK11-AB, -AD
r - - - - - - - - - · - - - - - - - ,I
I
I
I
I
r>-:.:....-I ~~H
I
I
DC005 TRANSCEIVERS REClXMIT CONTROL
DATN H
ADREN H
RECH
I
TRPLY H
I
INWDH
~----------·------i
NON-EXISTENT ADDRESS TIME-OUT
CSRWHB
+6V
f
16
INI H
INIT L 6
E16Xl~------I
74LS04
+3V
R16
""
+6
L _ _ _ _ _ _ _ _· _ _ _ _ _ _ _ _
Figure 5
Typical Application (Miscellaneous Logic)
(Sheet 2 of 3)
151
~
DCK11-AB, -AD
r;;:; ::O;:N;;V;';; - - - - - - - -- -- -- --,
BRPlY l./AF2
TRPLY
RPlYH
BOIN UAH2
TOIN
4
ROIN
TSYNC
TOOUT H .
BB41/El
MASTER H
8841/E2
L _ _ --- _ _ _ _ _ _ _ _ _ _ _ _ J
Figure 5
Typical Application (Miscellaneous Logic)
(Sheet 3 of 3)
152
DCK11-AB, -AD
The DC005 transceiver receive/transmit control determines the state
of the DC005 trancelvers. Normally, the transceivers are In the receive
state to accept device addresses from the LSI-11 bus. When REC H is
asserted (high), XMIT is negated (low). XMIT Is asserted (high) when
transferring data to the LSI-11 bus (TDOUT, DATEN, and ADREN are
high; TRPLY, .INWD are lOw). REC Is asserted (high) when receiving
data from the LSI-11 bus (TDOUT, DATEN, and ADREN are low;
TRPLY, INWD are high).
The control/status register (CSR) (Figure 5, sheet 1) has six active bits
and is a read/write register comprised of 74LS367 3-state drivers and
flip-flops which are part of other logic circuits shown In Figure 3, sheet
1, and Figure 5, sheet 2. Figure 6 shows the CSR format. The CSR bits
are described in Table 1.
UNUSED
13
INTERRUPT
ENABLE
FOR BIT 15
BUS TlME·OUT
(NON·EXISTENT
ADDRESS)
UNUSED
09
04
USER
TRANSFER
REQUEST
00
INTERRUPT
ENABLE
FOR BIT 7
BLOCK TRANSFER
COMPLETE
(WORD COUNT
OVERFLOW)
TRANSFER D(RECTION
SELECT BIT
DATO/DATI
1/0
Figure 6
Control/Status Register (CSR) Format
The quad transceivers (8641) shown In Figure 3 sheet 3, supplement
the DC005 transceivers for interfacing to the LSI-11 bus. In this particular application, the 864 ~ s are permanently enabled by grounding
pins 7 and 9.
153
DCK11-AB, -AD
CSR Bit Descriptions
Bit
Name
00
Unused
01
Description
02
03
04
05
DATO/DATI
06
Interrupt enable
for bit 7
07
Block transfer
complete
This bit sets (1) when the word
count register overflows, providing bit 06 Is set.
08
User transfer
request
The user's device must set (1)
this bit to make a bus request
and transfer data. User REa L
(J1-PP) must be driven low (0)
to set bit 08. This bit is always
read as a zero. This is an example for test purposes.
09
10
11
12
13
Unused
14
Interrupt enable
for bit 15
15
Bus time-out
When set to a 1, indicates a
DA TO cycle; when set to a 0,
indicates DATI bus cycle.
This bit must be set (1) to enable the word count overflow
interrupt at the end of a. block
transfer. When set to 0, the interrupt is Inhibited.
This bit must be set (1) to
enable the bus time-out interrupt. When set to a 0, the Interrupt is inhibited.
This bit sets (1) when a slave
on the LSI-11 bus does not respond with BRPLY within 10 JlS
after being addressed. Bit 14
must be set (1) to enable the
bus time-out Interrupt.
154
DCK11-AB, -AD
CNTlA D-+--~-+--'"
CLK·A D-+--~-+--'"
LD
WRITE
CONTROL
LOGIC
S·A
S·C
READ
CONTROL
LOGIC
RD·A 0 + - - - 1
RDO+---I
Figure 7
DC006 Simplified BloCk Diagram
DCD06 WORD COUNT/BUS ADDRESS LOGIC (DEC # 19-14035)
The word count/bus address (WC/BA) chip Is a 20-pln, 0.762 cm
center x 2.74 cm long (0.3 In. center x 1.08 In. long) DIP, low-power
Schottky device. Its primary use is In DMA peripheral device Interfaces. This IC is designed to connect to the 3-state side of theDC005
transceiver. The DC006 has two 8-blt binary up-counters, one for the
word (byte) count and another for bus address. Two DC006 ICs may e
cascaded to increase register implementation.
The chip is controlled by the address latch protocol chip (DC004), the
DMA chip (DC010), and a minimum of ancillary logic. Both counters
may be cleared simultaneously. Each counter Is separately loaded by
LD and the corresponding select line from the protocol chip. Each
counter is incremented separately. The WC counter (word byte
counter) Is always incremented by one; the A counter (bus address)
may be Incremented by one or two for byte or word addressing, respectively.
Data from the DC006 ICls placed on the 3-state bus via Internal 3state drivers. Each counter is separately read by RD and the corresponding select line.
155
DCK11-AB, -AD
Figure 7 Is a block diagram of the DCOOa IC while Figure Sillustrates a
slmpllf·led logic diagram. The DCOOa pin/signal description Is presented In Table 2.
x .. DON'T CARE
TRUTH TABLES
WHERE:
L
H
Z
,
- TTL LOW
.. TTL HIGH
.. HIGH IMPEDANCE
.. HIGH TO LOW TRANSITION
READ CONTROL
INPUTS
LD-H
RD
L
L
L
L
H
L
L
L
L
H
H
H
H
RD-A
L
L
L
L
L
H
H
H
H
H
H
H
H
OUTPUTS
S-A
S-C
D/F<7:0>
L
L
H
H
L
H
L
H
CLEAR AIIC AND READ C
A<7:0>
C<7:0>
X
X
Z
Z
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
CLEAR AIIC AND READ A
A<7:0>
A<7:0>
A<7:0>
CLEAR AIIC AND READ A
A<7:0>
A<7:0>
A<7:0>
WRITE CONTROL
RD-A=
INPUTS
,RD = H
S-A
LD
L
~
L
H
~
H
H
L
H
L
H
H
,
x
FUNCTION
S-C
L
H
L
H
L
H
L
'IUEGAL
LOADA<7:0>
LOADC<7:0>
WClBA NOT SELECTED
CLEAR BOTH COUNTERS
LOADING DISABLED
LOADING DISABLED
'ILLEGAL CONDITION BECAUSE A LOAD OPERATION AND A CLEAR
OPERATION IS ATTEMPTED SIMULTANEOUSLY. RESULT OF THIS
OPERATION IS TO CLEAR BOTH COUNTERS.
:L~': :--T_____________-d:~:AL HMAXA~ i]A '071
041
CLAH
S·C L - : - T - - - - - - r - - < c r " " " ' \
S·A L--;-------'I-I,-----+--a___.
051
A COUNTER
B BIT BINARY
g~
I
gy
I
uP COUNTER
RD L
RD.A H
C COUNTER
B 81T BINARY
uP COUNTER
LDL~------~---~~~
02 1
l
LDC
~: C.071
CLK.C H--T-----------I-----dCLKC LOlli
07
H
I
eLA H
MAXC L I - - - - - - - - - - d
-----o FUHI
Figure'S DCOOa Simplified Logic Diagram
156
MAX-C H
DCK11-AB, -AD
DC010 DIRECT MEMORY ACCESS LOGIC (DEC #19-14038)
The Direct Memory Access (DMA) chip Is a 20-pln, 0.762 cm center X
2.74 cm long (0.3 In. center X 1.08 In. long) DIP, low-power Schottky
device for primary use In DMA peripheral device interfaces using the
LSI-11 bus.
This device provides the logic to perform the handshaking operations
req~lred to request and to gain 'control of the system bus. Once bus
mastership has been established, the DC010 generates the required
signals to perform a DATI, DATO, or DATIO transfer as specified by
control lines to the chip. The DC010 IC has a control line that will allow
multiple transfers or only four transfers to take place before giving up
bus mastership.
Figure 9 Is a simplified logic diagram of the DC010 IC. The logic symbols and truth table are presented In Figure 10. Table 3 describes the
signals and pins of the DC010 by pin and signal name.
(MASTER 6'0
HI---rotec
tion against physical damage to modules and to serve as a card guide.
The card cage completely surrounds the slot side of the system unit
and Is shown In Figure 1. The DDV11-B can be mounted In the H909-C
enclosure.
NOTE
The H909-C Includes the H0341 card guide.
Figure 1
DDV11-B with H0341 Card Assembly
159
DDV11-B
CONFIGURATION
Module Slot Assignments
Figure 2 shows the slot location assignments of the DDV11-S. Rows A.
S, C, and 0 are dedicated to the LSI-11 bus. Any module which conforms to the LSI-11 bus specifications may be used in this portion of
the DDV11-B. The position numbers indicate the bus grant wiring
scheme with respect to the processor module. The bus grant signals
propagate through the slot locations in the position order shown in
Figure 2 until they reach the requesting device. Any unused slots must
be jumpered to provide bus grant signal continuity or it is recommended that unused locations occur only in the highest position
numbered locations.
Rows E and F contain the 18 user-defined slots with power and ground
connections provided.
Equipment Supplied
The DDV11-B option consists of the following items:
Six H863 connector blocks
Three H8030 connector blocks
Etched board bus structure
Installation
The DDV11-B can be mounted on panels or chassis using standard
hardware. The overall dimensions of the unit are shown in Figure 3.
The H034 mounting frame of the DDV11-B is provided with tapped
holes and clearance holes to enable the attachment of the system unit.
H0341 Card Assembly Mounting
The card assembly provides nylon guides which help to guide and
support the modules installed in the system unit. The H0341 card
assembly is supplied with the hardware necessary to mount to the
H034 mounting frame. Figure 4 shows the method of assembly. Two
screws (item 2) and two washers (item 1) are inserted through the
clearance holes of the PC board and H034 mounting frame and into
the two threaded inserts on each bracket of the card assembly.
160
DDV11-B
POWER
TERMINAL
BLOCK
1- .~
PROCESSOR
2-
~
POSITION 3
3-
~
POSITION 4
4-
~
POSITION 7
6-
-~
POSITION 8
6-
~
7-
~
POSITION 12
8-
~
POSITION 15
I
POSITION 14
9-
~
POSITION 16
I
POSITION 17
POSITION 11
PROCESSOR OR OPTION 1
I
I
I
I
I
I
I
OPTION POSITION 2
POSITION 6
POSITION 8
POSITION 9
POSITION 10
POSITION 13
A
:
0
MODULE INSERTION SIDE
USER DEFINED SLOTS
MODULE ICOMPONENTS MOUNTED ON OPPOSITE SIOEI
'<'\cI" . .i
BACKPLANE
!-_ _--' ""-_ _......._ _---' ""-_ _---!,
:
IIII=~I=_=::.....I=n!lI"nl l =I IL. I~=~=_=~: : !m: !: : I I=1I=O=::::!II;:II=II.....I=_=~=_=_=m!!:~I=III=F=;:!l;ld
IIIILlJU==A=::::!:!:::....
7
WIRE WRAP PINS
\
TERMINAL STRIP
POWER SIGNAL PINS
Figure 2
DDV11-8 Module Installation and Slot Assignments
161
DDV11·B
POWER SIGNAL PINS
BHALT L
DCOK
H~L
N. C.
SPARE-f::0
N.C.T~I
L I'
1.75 IN
(4.5
PI
16.52 IN (42.0 CM)
1 [__1E__ ;~::~T:_~;~ __ j
BEVNT L
: __ )j
BPOK H
PIN A01A1
ETCHED CIRCUIT BOARD
Itt
I~!m
III. ----------------------------------,
111111\ 1111'.
I
~.-------17.0
I
IN (43.18 CM)----------J·
JUMPER
STRAP
~~~-------------------~
T
~
I
I
:
~ ;~:~M~~~E
I
I
22.07
(8.69)
Figure 3
H0341
CLEARANCE
OUTLINE
6 32 X 0.25 (0.64)
MOUNTING HOLES
(6 TOTAL)
DDV11-B Power Wiring and Dimensions
162
GND
)C
. .'V',
,
\ SRUN L
DDV11-B
H03;RD CAGE ASSEMBLY
H034 SYSTEM UNIT MOUNTING FRAME
BACKPLANE
PC BOARD
TH READE D ---L--~-i+-+f.l
INSERTS
DD11V-B SYSTEM UNIT
Figure 4
H0341 Card Assembly Installation
DC Power and Power Signal Connections
DC power is supplied to the modules in the DDV11-B through the
backplane PC board. The power and ground leads from the external
source connect to the 7-position terminal board mounted on the edge
of the PC board as shown in Figure 3. Any suitable connector terminals, solder or crimp style, may be attached to the power supply leads
and inserted under the terminal strip screws. A jumper tab is mounted
between the two +5 V screws and between the two ground (GND)
screws on the terminal board. The total current capability of the
DDV11-B and the wire size required are as follows:
Terminal
+12V
+5V
+5V
+5B
GND
GND
-12V
Jumped
Current
(Max)
20A
40A
Wire Size
(AWG)
14
14
Jumped
20A
40A
14
20A
Figure 5 identifies the power signal pins which are located at the opposite end of the backplane PC board from the power terminal strip. A
mating female connector (DIGITAL PIN 12-11206-02 or 3M PIN 34733) can be inserted over the pins and used to connect the external
signals to the backplane.
163
Backplane Pin Assignments
Table 1, lists the backplane pin assignments for the LSI-11 bus signals and dc power and ground connections
on the DDV11-B backplane. .
Table 1
-L
0'>
~
DDV11-B Backplane Pin Assignments
Side
2
A&C
1
A&C
2
Row
B&D
1
BaD
2
E
E
2
F
1
F
A
B
C
D
E
F
H
+5V
-12V
GND
+12V
BDOUT L
BRLPY L
BDINL
BSYNC L
BWTBT L
BIRQL
BIAKIL
BIAKO L
BBS7L
BDMG 1 L
BDMGOL
BINITL
BDALO L
BDAL1L
BSPARE1
BSPARE2
BDAL17L
BDAL16L
SSPARE1
SSPARE2
SSPARE3
GND
MSPAREA
MSPAREA
GND
BDMRL
BHALT L
BREFL
PSPARE3
GND
+12B
+SB
+SV
-12V
GND
+12V
BDAL2L
BDAL3L
BDAL4L
BDALSL
BDAL6L
BDAL7L
BDAL8 L
BDAL9L
BDAL 10 L
BDAL 11 L
BDAL12L
BDAL13 L
BDAL14 L
BDAL1S L
BDCOKH
BPOKH
SSPARE4
SSPARES
SSPARE6
SSPARE7
SSPARE8
GND
MSPAREB
MSPARE B
GND
BSACKL
BSPARE6
BeVNTL
PSPARE4
GND
PSPARE2
+5
+SV
-12V
GND
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
GND
BLANK
BLANK
+SV
-12V
GND
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
GND
BLANK
BLANK
J
K
L
M
N
P
R
S
T
U
V
1
C
C
<
..A.
..A.
•
aI
DLV11
DLV11 SERIAL LINE UNIT
SPECIFICATIONS
Identification
M7940
Size
Double
Power"
+5.0 Vdc ± 5% at 1.0 A (1.6 A
max)
+12.0 Vdc ± 3% at 0.18 A (0.25 A
max)
Bus loads
AC
DC
2.5
1.0
CONFIGURATION
General
The user can select the register address, parity, number of data bits,
number of stop bits, baud rate, and type of serial interface. The descriptions of the registers and their standard factory addresses are
listed in Table 1. Available jumpers are shown in Figure 1 and their
applications are listed in Table 2.
Table 1
Standard Addresses
Register
Mnemonic
Receiver control status
Receiver data buffer
Transmit control/status
Transmit data buffer
Standard vectors
RCSR
RBUF
XCSR
XBUF
RCSR
XCSR
165
Console
177560
177562
177564
177566
060
064
Second
Module
176500
176502
176504
176506
300
304
DLV11
TPl
O-N'"
a:: a:: a:: a::
i
La.La.ILu..
IIII
•• J __
,'T-,
TP2
6
>_NCD
1&.1 CD CD II)CL
Il.ZZNZ
IIIII
IIIII
CP-IBOI
Figure 1
DLV11 Jumper Locations
166
DLV11
Table 2 DLV11 SLU Factory Jumper Configuration
Jumper
Jumper
Designation
State·
Function Implemented
A3
A4
AS
A6
A7
A8
A9
A10
A11
A12
I
R
R
R
I
V3
V4
V5
V6
V7
I
R
R
I
I
This jumper arrangement Implements
the Interrupt vector: 60 for received data
and 64 for transmitted data.
NP
2SB
NB2
NB1
R
R
R
No parity
Two stop bits
Eight data bits
R
PEV
FEH
EIA
I
I
FRO
FR1
FR2
FR3
R
R
R
R
R
R
* R
X=
X=
X=
X=
0, RCSR address
2, Receive data register address
4, XCSR address
6, Transmit data register address
Even parity If NP Installed
Halt on framing error
12 V EIA operation enabled
R
R
110 baud rate selected
R
R
CL1
CL2
CL3
CL4
This arrangement of jumpers A3 through
A 12 Implements the octal device address 17756X, which Is the assigned address for the console device SLU. The
least significant digit is hardwired on the
module to address the four SLU device
registers as follows:
20 rnA current loop active receiver and
transmitter selected
I
II
Jumpered with 180 ohm resistors
I
= removed, I = Installed
167
DLV11
Addresses
Addresses for the DLV11 can range from 1600008 through 17777X8 •
The least significant three bits (only bits 1 and 2 are used; bit 0 Is
ignOred) address the desired register in the DLV11, as described In
Table 1.
Address bits 3 through 12 are jumper-selected as shown In Figure 2.
Since each DLV11 module has four registers, each requires four addresses. Addresses 177560-177566 are reserved for the DLV11 used
with the console peripheral device. Additional DLV11 modules should
be assigned addresses from 176500 through 176670, allowing up to 30
additional DL V11 modules to be addressed.
BDAl
BITS .-1:.::.5- , - - - - - - - . - - - - - - - r - . : : . . . . - - - . : . . . - - - - r - - - - " " " " T " " " - - - - - - . . : O ' - ,
11 I 1 I 1 I
xl
ADDRESS JUMPERS:
INSTAllED -0
REMOVED'" 1
Figure 2
RANGEIII160000e -177176,
CSR Address Selection
Word Format
The word format for the Receiver Control/Status Register (RCSR) is
detailed in Figure 3 and Is described in Table 3.
RECEIVER
INTERRUPT
ENABLE
(READ/WRITE)
MR-Q80l5
Figure 3
Receiver Control/Status Register (RCSR)
168
DLV11
Table 3
ReSR Word Format
Bit
Function
15
Dataset Status - Set when CARRIER or CLEAR TO
SEND and DATA SET READY signals are asserted
by an EIA device. Read-only bit.
14-8
Not used. Read as O.
7
Receiver Done - Set when an entire character has
been received and Is ready for input to the processor. This bit is automatically cleared when RBUF is
addressed or when the BDCOK H signal goes false
(low). A receiver interrupt is enabled by the DLV11
when this bit is set and receiver interrupt is enabled
(bit 6 is also set). Read-only bit.
6
Interrupt Enable - Set under program control to
generate a receiver interrupt request when a character is ready for input to the processor (bit 7 is set).
Cleared under program control or by the BINIT signal. Read/write bit.
5-1
Not used. Read as O.
o
Reader Enable - Set by program control to advance
the paper tape reader on a teletypewriter device to
input a new character. Automatically cleared by the
new character's start bit. Write-only bit.
The receiver data buffer register (RBUF) word format is shown in
Figure 4 and described in Table 4.
I
~
(NOT USEDl
DATA AND PARITY
(5- 7 BIT DATA IS RIGHT JUSTIFIED. PARITY IS BIT 7.
NO PARITY BIT IS PRESENT WHEN a-BIT DATA IS USED.l
Figure 4 . Receiver Data Buffer Register (RBUF)
169
DLV11
Table 4
RBUF Word Format
Bit
Function
15-8
Not used. Read as O.
7-0
Contains five to eight data bits in. a right-justified
format. MSB is the optional parity bit. Read-only bits.
The transmit control/status register (XCSR) word format is shown .in
Figure 5 and described in Table 5.
XCSR
TRANSMIT
INTERRUPT
ENABLE
(READ/WRITE)
Figure 5
Transmitter Control/Status Register (XCSR)
Table 5
XCSR Word Format
Bit
Function
15-8
Not used. Read as O.
7
Transmit Ready - Set when XBUF is empty and can
accept another character for transmission. It is also
set during the power-up sequence by the BOCOK H
signal. Automatically cleared when XBUF is loaded.
When transmitter interrupt is enabled (bit 6 also set),
an interrupt request is asserted by the OLV11 when
this bit is set. Read-only bit.
6
Interrupt Enable - Set under program control to
generate a transmitter interrupt request when the
OL V11 is ready to accept a character for
170
DLV11
Table 6
XCSR Word Format (Cont)
Function
Bit
transmission. Reset under program control or by the
BINIT signal. Read/write bit.
5-1
Not used. Read as O.
o
Break - Set or reset under program control. When
set, a continuous space level Is transmitted. BINIT
resets this bit. Read/write bit.
The transmit data buffer register (XBUF) word format is shown in
Figure 6 and described in Table 6.
15
(NOT USEDI
Figure 6
DATA
Transmitter Data Buffer Register (XBUF)
Table 6
XBUF Word Format
Bit
Function
15-8
Not used.
7-0
Contains five to eight right-justified data bits. Loaded under program control for serial transmission to a
device. Write-only bits.
Interrupt Vectors
Vectors can range from 0 through 37X8 • Vectors 60 and 64 are reserved for the console peripheral device. Additional DLV11 modules
should be assigned vectors following any DRV11 modules installed in
171
DLV11
the system starting at 300. Vector bits 3 through 7 are selectable by the
user to form the address as described in Figure 7. The factory configuration will set the receiver Interrupt vector for 060 and the transmitter
Interrupt vector will be set at 064.
BDAL
BITS
15
I I
0
0
o
I0
I
0
I
0
I
0
I
0
0
1I
~
~ 1 L
VECTOR JUMPERS'
INSTALLED·O
REMOVED '1
Figure 7
> ,
I
o
I
O' RECEIVER
I • TRANSMITTER
RANGE '0- 374,
Interrupt Vector
UART Operation
The UART operation Is programmed by using jumpers NP, 28B, NB1,
NB2, and PEV as shown below.
Number of Data Bits
NB1
5
Installed
Removed
6
7
Installed
Removed
8
NB2
Installed
Installed
Removed
Removed
Number of Stop Bits Transmitted
28B installed = One stop bit
28B removed = Two stop bits
Parity Transmitted
NP removed = No parity bit
NP and PEV installed = Odd parity
NP installed and PEV removed = Even parity
.
Baud Rate Selection
Baud rate is programmed via jumpers FRO through FR3 as shown In
Table 7.
172
DLV11
Table 7
Baud Rate
FR3
Baud Rate Selection
FR2
FR1
FRO
50
R
75
R
R
R
R
110
R
134.5
150
R
R
200
300
R
R
600
R
R
R
R
R
R
R
R
1200
R
R
1800
R
R
2400
R
2400
R
4800
R
9600
R
R
R
R
R
External
(via pin BH1)
NOTE:
I = Installed
R
X
X = Irrelevant
173
R = Removed
DLV11
EIA Interface
EIA drivers are enabled when jumper EIA is installed. This jumper
applies -12V to th_e EIA driver chip. It should be removed during 20
rnA current loop operation.
20 rnA Current Loop Interface
Jumpers CL 1 through CL4 are associated 'wlth 20 rnA current loop
interface operation. Remove or Install CL 1 and CL4 jumpers and CL2
and CL3 180 ohm resistors for the desired function as described below.
The active current loop jumper configuration is shown in Figures 8 and
9.
Transmit:
CL4.jumper Installed
CL3 resistor installed
Receive:
CL 1 jumper installed
CL2 resistor installed
USE BC05M CABLE
c(
H
UJ
o
o
11-3924
Figure 8
20 rnA Active Current Loop Jumper Configuration
174
DLV11
.
.=-,-,-..:.c..;..;.;..;,..,;,;.;,._ _ _..,;;J-<'
S fo( '-T7~--+(+-:------'~-<' :3
( ~ SERIAL IN-
L.....::.:=...;,..,:,..:c...:.=:..::....=.::..:..:..:...+-< H
+-'-.:..::....::=:..:.:...:=....:..:..:...;_«
ZOmA DATA OUT
I
::
I
:I :I
+-,
::
E
~:
KK
(
I
I
I
I
(
/
Figure 9
I
I
I
I
..I
I
I
I
I
I
I
I
I
I
~~~-¥~---~EE
I
I
I
CLI
L.I
C
C
__--o---o------''-«AA
I
I
I
I
;
I
I
I
ACTIVE RECEIVE
CURRENT LOOP
MODE ENABLE
SERIAL 2~mA DEVICE
BC05M CABL~ ASSEMBLY
DLV!! SERIAL LINE UNIT CIRCUITS
I
( 2 ~ SERIAL OUT-
I
I
I
I
I
I
~ I
I~
+
I
I~ 5
-
I
I
I'
•
I
SERIAL OUT+
~:~~~~:_
I
4
,-,
I -'
6
~READER
•
I
I "'
7
~ SER!AL
·· ..
: .
•
I
I
I
I /
~ENABLE+
IN+
Active 20 mA Current Loop Interface
The passive current loop jumper configuration is shown In Figures 10
and 11.
Transmit:
CL4 jumper removed
CL3 resistor removed
Receive:
CL 1 jumper removed
CL2 resistor removed
The DLV11 is supplied with jumpers CL 1 through CL4 wired for the
active transmit. active receive mode (Figure 9). When In this mode.
serial current limiting to 23 mA Is provided by resistors (one each for
transmit and receive functions) connected to the +12V source. Note
that when module power Is removed. the 20 mA transmit optical
coupler closes the serial loop (active or passive mode). When the
DLV11 Is used In the passive 20 mA mode (Figure 11). the serial device
must produce the 20 mA current. Current limiting must be provided
for transmit and receive currents In the serial device.
175
DLV11
DLVII SERIAL LINE UNIT CIRCUITS
(PASSIVE RECEIV~ AND TRANSMIT!
JI
r---~---------,~
S (
P2
,-.
I
/
I
I
I
H
SI H -I-::T'='TL""S""'E:-::;R::-:IAC:-L---'~ E
DATA IN
:=p
" I
SO H
-
-
~I
-'0---.--( AA
I
I
I
::±=U
P
"
I
I
vv
I
7
I
~ SERIAL
IN - }-15V
5 ~ SERIAL OUT-
/
"
+5V
S
SERIAL
DATA IN
/
I "'
I
"
I
I
A
I
I
I
I
II
SERIAL
DATA OUT
(
I
I
I
I
I
+5V
I
" I
I
- I 2v ---'INIo------r---"IIYr_r-<. EE
"' I
I
Figure 10
SERIAL 20mA DEVICE
PI
I
~~-+---------.~
.
.
BC05M CABLE ASSY
I
4 ~ READER ENABLE-
I
I
I
<
I
6 ~ READER ENABLE +
CP-180e
Passive 20 rnA Current Loop Interface
USE BC05M CABLE
o
~1---_-----,1 ~ Hi
0
D
-y-6-
0 \ 00
ct
1-1
I&J
o
o
11-3851
Figure 11
20 mA Passive Current Loop Jumper Configuration
Framing Error Halt
A framing error halt allows entry to console microcode directly from
the console device by pressing the BREAK key, producing a framing
error. A framing error occurs when the received character has no valid
stop bit. This error condition is detected by the UART. FEH is factory176
DLV11
Installed, causing the assertion of BHALT L when the framing error is
detected. The processor then executes console microcode.
Installation
Prior to installing the DLV11 on the backplane, first establish the desired priority level to determine the backplane slot In which the module will be installed. Then, check that jumpers are removed or installed
as described for your application. Connection to the peripheral device
is via an optional data interface cable. Cables are listed below.
Application
EIA Interface
20 mA Current Loop
Cable Type·
BC01V-X or BC05C-X Moden:" Cable
BCOSM-X Cable Assembly
• The -X in the cable number denotes length in feet, as follows: -1, -6, -10, -20,
-25. Fo"r example, a 10-ft EIA interface cable would be ordered as BC05C-1 O.
Interfacing with 20 mA Current Loop Devices
When interfacing with 20 mA current loop devices, the BC05M cable
assembly provides the correct connections to the 40-pln connector on
the DLV11. The peripheral device end of the cable is terminated with a
Mate-'N'-Lok connector.
The complete Interface circuit provided by the BCOSM cable and the
associated DLV11 jumpers is shown in Figure 10.
NOTE
When the DLV11 is used with teletypewriter devices,
a 0.005 p.F capacitor must be Installed between split
lugs TP1 and TP2.
After configuring the module jumpers and installing the proper Interface cable, the DLV11 can be installed in the backplane.
Interfacing with EIA-Compatlble Devices
When interfacing with EIA devices, the BC01 V or BC05C modem cable
provides the correct connection to the 40-pln connector on the DLV11.
The peripheral device end of the cable Is terminated with a Cinch
DB25P connector that is pin-compatible with Bell 103 or 113 modems.
Connector pinning and signal levels conform to EIA specification RS232C. The complete EIA Interface circuit Is shown in Figure 12; jumpers are shown in Figure 13.
177
DLV11
OPTIONAL HARDWARE
Cables
BCOSM
BCOSC
20 rnA; H8S6 to Mate-'N'-Lok female
EIA; H8S6 to Cinch 25-pin male.
MODEM CABLE
DLVII SERIAL LINE UNIT CIRCUITS
J'
V
(I
DO (
J
i
(I
REQUEST TO SEND
DATA TERMINAL READY
RECEIVED DATA
I
EIA INTERFACE
(CINC," DB25PI
( 4
fr-
( 3 + BB
I
I
I
I
I
::b
EIA/TTL RCVD DATA
TTL SERIAL DATA IN
SI
I
I
+'2V
EIA TRANS DATA
F (
I
I
I
EIA TRANS DATA
ENABLE JUMPER
+3V
TO CSR
SELECTION
AND GATING
r.
I
I
I
TRANSMITTED DATA
T
(I
( Z (
I
I
I
I
<2~
CARRIER
CLEAR TO SEND
DATA SET READY
I
f-I-
CF
(5f-i
CB
( 8
C
I
(I
I
~:'
UU
Figure 12
(25+
I
PROTECTIVE GROUND
I
PROTECTIVE GROUND
I
SIGNAL GROUND
I
I
(6~ cc
I
BUSY
BA
I
ctBB(i
I
CA
( 2 0 + CD
I
I
I
,+
f-L7
AA
AB
SIGNAL GROUND
EIA Interface
USE BCOIV OR Bcose CABLE
I
11-3925
Figure 13
EIA Jumper Configuration
178
DLV11
Connectors
H85S
Cinch DB25S
Mate-'N'-Lok (male)
Mate-'N'-Lok (male)
Mate-'N'-Lok (female)
Mate-'N'_-Lok (female)
Miscellaneous
BC05F
BC03P
H312A
To module
To BC05C
12-09340-01 connector
12-09378-01 contacts
12-09340-00 connector
12-09379-01 contacts
20 mA extension cable
(Mate-'N'-Lok to Mate-'N'-Lok)
Null modem Cable
(female Cinch to female Cinch)
Null modem
179
DLV11·E
DLV11-E ASYNCHRONOUS LINE INTERFACE
GENERAL
The DLV11-E is an asynchronous line interface module that interfaces
the LSI-11 bus to any of several types of serial communications lines.
The module receives serial data from peripheral devices, assembles it
into parallel data, and transfers it to the LSI-11 bus. It accepts data
from the LSI-11 bus, converts it into serial data, and transmits it to the
peripheral devices. The DL V11-E offers full modem control and EIAtype interface.
FEATURES
• Jumper- or program-selectable, crystal-controlled baud rates: 50,
75, 110, 134.5, 150, 300, 600, 1200, 1800, 2000, 2400, 3600, 4800,
7200, 9600, and 19,200. Split transmit and receive baud rates are
possible.
• Provisions for user-supplied external clock Inputs for baud rate control.
• Jumper-selectable data bit formats.
• LSI-11 bus Interface and control logic for interrupt processing and
vectored addressing of interrupt service routines.
• Full modem control (Bell 103, 113, 202C, 2020, and 212-compatible).
SPECIFICATIONS
Identification
M8017
Size
Double
Power
+5.0 Vdc ±5% at 1.0A
+12.0Vdc ±3%atO.18A
Bus loads
AC
1.6
1.0
DC
180
DLV11-E.
DESCRIPTION
General
Major functions contained on the DLV11-E are shown In Figure 1.
Communications between the processor and the DLV11-E are executed via programmed 1/0 operations or interrupt-driven routines.
Bus Interface
The bus Interface circuit signal lines consist of data moving between
the LSI-11 bus and the module's internal tri-state bus. It decodes the
device address and produces an address match (MATCH H) signal
and it places interrupt vectors on the LSI-11 bus. The bus interface
receives from the LSI:..11 bus unless it is switched to transmit to the
LSI- n bus. The Interrupt logic can cause the bus Interface to transmit
either a transmitter or receiver interrupt vector and the 1/0 control
logic can cause the bus interface to transmit to or receive data from
the LSI-11 bus.
The bus Interface receives LSI-11 bus lines BDALOO L through
BDAL 15 L and places them on the module's trl-state bus. If BBS7 L Is
asserted, the .circuit decodes BDAL03 L through BDAL 12 L and asserts MATCH H. Jumpers A3-A 12 are configured to allow the option to
respond to specific device register addresses. Jumpers V3-Va select
the options' interrupt vector.
1/0 Control Logic
When the 1/0 control logic receives MATCH H from the bus interface,
it decodes tri-state bus lines DATOO H through DAT02 H and selects
the addressed device register. The 1/0 control logic exchanges bus
control signals with the processor to perform input and output data
transfers.
181
~~
I
QRCUIT
5----:- n!
!~E ~~~ ~=TlllANCl!b
'"
BUS
INTERFACE
~
~
8BS. .
THRII.sTATliBUS
DATOC>'O.
~
'"
....... L
DIiYICE
ADDREss
DECOOaR
QIlIIBRATOR
~
~~~
CONTAOUSTATUS
AIOISTIA
i.
a
.....RI
.\3-A12
VECTOR.
~
_TOI.
"'v
¥ECTOA.
VEc:RGOTII.
IIS'tIOCL
1/0 CONTROL
IIIOTBTL
LOGIC
......VL
~L
BOil"
BlRDL
BIAI
...J
pa
0
C\I
Q)
~
~s~~;!:
111111
II
I" IIIII
N .. OGlCD .... UlItI.1'I
:::l
1~
C)
iL:
c---s
:(:(:(ccccccc
~B
H
11-5172
187
OLV11-E
BDAl
orr,)
DB
~'
07
111111
BBS7 l
oHU
N
C
.,
o
~
IIIIII
IH' Is Ii I
IA12= LJA9==A10
A11
-AS
A4:......:: V8
" -A3
V4~V3
PB:"""': BP1
AA1=AB1
Figure 2
DLV11-F Jumper Locations
<
~
~
•
"'II
DLV11-F
Table 2
DLV11·F Jumper Definitions
NOTE
Jumpers are inserted to enable the function they
control except for those jumpers which indicate negation (such as "-8" and "E"). Negated jumpers are
removed to enable the functions they control.
Jumper
Function
A3-A12
These jumpers correspond to bits 3 through 12 of
the address word. When inserted, they cause the
bus interface to check for a true condition on the
corresponding address bit.
V3-V8
Used to generate the vector during an interrupt
transaction. Each inserted jumper asserts the corresponding vector bit on the L51-11 bus.
RO-R3
Receiver and transmitter baud rate select jumpers
during common speed operation.
Receiver-only baud rate select jumpers during split
speed operation, as defined in Table 3.
TO-T3
Transmitter baud rate select jumpers during split
speed operation.
Both receiver and transmitter baud rate if maintenance mode Is entered during split speed operation,
as defined in Table 3.
BG
Jumper is inserted to enable break generation.
P
Jumper is inserted for operation with parity.
E
Receiver checks for appropriate parity and transmitter inserts appropriate parity.
1,2
These jumpers select the desired number of data
bits, as defined in Table 4.
PB
Jumper is inserted to enable the programmable
baud rate capability.
C,C1
These jumpers are inserted for common speed operation. (Note that 5 and 51 must be removed when
C and C1 are inserted.)
208
DLV11-F
S,S1
Inserted for split speed operation. (Note that C and
C1 must be removed when Sand S1 are inserted.)
H
This jumper is inserted to assert 8HALT L when a
framing error is received, except when the maIntenance bit is set. This places the processor in the halt
mode.
8,-8
Jumper 8 is inserted to negate BOCOK H when a
break signal or framing error is received, except
when the maintenance bit is set. This causes the
processor to reboot. (Jumper -B must be removed
when 8 is inserted.)
1A,2A,3A
These three jumpers are Inserted to make the 20 mA
current loop receiver active. (Jumpers 1P and 2P
must be removed when 1A, 2A, and 3A are inserted.)
1P,2P
These Jumpers are inserted to make the 20 mA current loop receiver passive. (Jumpers 1A, 2A, and 3A
must be removed when 1P and 2P are installed.)
4A,5A
Inserted to make the 20 rnA current loop transmitter
active. (Jumpers 3P and 4P must be removed when
4A and 5A are inserted.)
3P,4P
Inserted to make the 20 rnA current loop transmitter
passive. (Jumpers 4A and 5A must be removed
when 3P and 4P are inserted.)
EF
Jumper is removed to enable the error flags to be
read in the high byte of the receiver buffer.
M,M1
These are test jumpers used during the manufacture
of the module. They are not defined for field use.
209
DLV11-F
BDAl
BITS 1""""'-"5'--r_ _ _ _'--r_ _ _ _'--r...:.DB;;......_0;;.;.7_ _~----~---.=;OO::..,
I'
I
I
I
I
I
I
I
I
I
"---....-----J
BBS7 l
-I(L)
o
Ci
I
I
I~
:.,,~,~,~. , : ~ ~ ~J
I
I
I
I
!
I
I
R
INSTAllED - I
REMOVED -0
~ : ~~~~V:I~TER }
~ : g::A BUFFER }
~ : ~?G~ :~~~
}------'
RANGE' 1600008 - 177776 8
Figure 3' DLVll-F Addressing
BDAl
BITS
I
0
00
OB
15
0
I I
0
0
0
I I I I I I
0
0
R
R
I ~
SELECTED BY USER.
ASSERTED BY INTERRUPT ~
LOGIC CIRCUIT.
R
I
! l
I
R
I ~I L
I I
0
O· RECEIVER
I • TRANSMITTER
~
VECTOR JUMPERS:
INSTALLED-,
REMOVED-O
Figure 4
I I
0
CONTROLLED BY INTERRUPT
lOGIC CIRCUIT.
RANGE - 0-7748
DL Vll-F Interrupt Vectors
Baud Rate Selection
The DL Vll-F allows the user to configure jumpers TO-T3 and RO-R3
for the transmit baud rate and the receiver baud rate as shown in
Table 3.
Data Bit Selection
The number of data bits transmitted or received by the DLVll-F is
user-selectable by installing or removing jumpers 1 and 2. The specific number of data bits as controlled by the configuration of jumpers 1
and 2 is shown In Table 4.
210
DLV11-F
Table 3
Program Control
Receive Jumpers
Transmit Jumpers
DLV11-F Baud Rate Selection
Bit
14
R2
T2 .
Bit
15
R3
T3
I
I
I
I
R
R
R
R
I
I
I
R
I
I
I
I
R
R
R
R
R
R
R
R
R
R
R
Bit
13
R1
T1
Bit
12
RO
TO
Bit
11*
Baud
Rate
I
I
I
R
R
R
R
I
I
R
50
75
110··
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
R
R
I
I
I
I
I
R
I
R
R
R
R
I
I
R
R
R
R
I
I
I
I = Jumper ins~rted = program bit cleared
R = Jumper removed = program bit set
* Bit 11 of the XCSR (write-only bit) must be set in order to select a new baud
rate under program control. Also. jumper PB must be Inserted to enable
baud rate s~lectlon under program control.
** When configured for 110 baud. the UART is set for two stop bits.
Table 4 . DLV11-F Data Bit Selection
Jumpers
2
Number of Data Bits
1
5
R
R
R
6
7
R
211 :
8
DLV11·F
Factory Configuration
The user can reconfigure any of the jumpers to make the module meet
his requirements. The factory configuration, as shipped, Is shown in
Table 5 to assist the user In determining what changes are needed.
Table 5
DLV11-F Factory Jumper Configuration
Jumper
Designation
Jumper
State
A3
A4
A5
A6
A7
Aa
A9
A10
A11
A12
R
I
I
I
R
I
I
I
I
I
Function Implemented
Jumpers A3 through A 12 Implement device address 17756X. The least slgnlflcant octal digit Is hardwired on the module to address the four device registers
as follows:
X=
RCSR
X=
RBUF
X=
XCSR
X=6
0
2
4
XBUF
V3
V4
V5
V6
V7
va
R
I
I
R
R
R
This jumper selection Implements Interrupt vector 608for receiver Interrupts
and 648 for transmitter Interrupts.
RO
R1
R2
R3
I
R
I
I
The module Is configured to receive at
110-baud.
TO
T1
T2
T3
I
R
R
R
The transmitter is-configured for 9600
baud if split speed operation Is used.
BG
Break generation Is enabled.
212
DLV11-F
P
R
Parity bit is disabled.
E
R
Parity type is not applicable when P is
removed
1
2
R
R
Operation with eight data bits per character.
PB
R
Programmable baud rate function disabled.
C
C1
I
I
Common speed operation enabled.
S
S1
R
R
Split speed operation disabled.
H
Halt on framing error enabled.
B
-B
R
I
Boot on framing error disabled.
1A
2A
3A
1P
2P
I
I
I
R
R
The 20 rnA current loop receiver is configured as an active receiver.
4A
5A
3P
4P
I
I
R
R
The 20 rnA current loop transmitter is
configured for active operation.
EF
Error flags are disabled.
MT
R
Maintenance bit disabled.
M
M1
R
R
Factory test jumpers. Not defined for
field use.
Registers
The word format for the DLV11-F RCSR is shown in Figure 5 and
functionally described in Table 6.
Figure 5
DLV11-F RCSR Word Format
213
DLV11·F
Table 6 DLV11-F RCSR Bit Assignments
Bit: 15-12
Name: Not used
Description: Reserved for future use.
Bit: 11
Name: RCVR ACT
Description: (Receiver Active)
When set, this bit indicates that the DL V11-F interface receiver is active. The bit is set at the center of the start bit, which is the beginning of
the input serial data from the device and is .cleared by the leading edge
ofRDONEH.
Read-only bit; cleared by INIT or by RCVR DONE (bit 7).
Bit: 10-8
Name: Not used
Description: Reserved for future use.
Bit: 7
Name: RCVR DONE
Description: (Receiver Done)
This bit is set when an entire character has been received and is ready
for transfer to the processor. When set, initiates an interrupt sequence
provided RCVR INT ENB (bit 6) is also set.
Read-only bit.
Bit: 6
Name: RCVR INT ENB
Description: (Receiver Interrupt Enable)
When set, allows an interrupt sequence to start when RCVR DONE (bit
7) sets.
Read/write bit; cleared by INIT.
Bit: 5-1
Name: Not used
Description: Reserved for future use.
Bit: 0
Name: RDR ENB
Description: (Reader Enable)
When set, this bit advances the paper tape reader in DIGITAL-modified TTY units (L T33-C, LT35-A, C) and clears the RCVR DONE bit (bit
7).
This bit is cleared at the middle of the start bit, which is the beginning
of the serial input from an external device. Also cleared by INIT.
Write-only bit.
NOTE
INIT
= LSI-11 bus BINIT signal assertion.
The word format for the DL V11-F RBUF register is shown in Figure 6
and functionally described in Table 7.
214
DLV11-F
14
13
12
II
10
09
08
07
RESERVED
Figure 6
Table 7
06
05
04
03
02
01
00
RECEIVED DATA BITS
DLV11-F RBUF Word Format
DLV11-F RBUF Bit Assignments
Bit: 15
Name: ERROR
Description: Used to indicate that an error condition is pres9nt. This
bit is the logical OR of OR ERR, FR ERR, and P ERR (bits 14,13, and
12, respectively). Whenever one of these bits is set, it causes bit 15 to
set. This bit is not connected to the interrupt logic.
Read-only bit; cleared by removing the error-producing condition.
NOTE
Error indications remain present until the next character is received, at which time the error bits are
updated. INIT clears the error bits.
Bit: 14
Name: OR ERR
Description: (Overron Error)
When set, indicates that reading of the previously received character
was not completed (RCVR DONE not cleared) prior to receiving a new
character.
Read-only bit. Cleared by INIT.
Bit: 13
Name: FR ERR
Description: (Framing Error)
When set, indicates that the character that was read had no valid stop
bit.
Read-only bit. Cleared by INIT.
Bit: 12
Name: P ERR
Description: (Parity Error)
When set, indicates that the parity received does not agree with the
expected parity. This bit is always 0 if no parity Is selected.
Read-only bit. Cleared by INIT.
Bit: 11-8
Name: Not used
Description: Reserved for future use.
Bit: 7-0
Name: RECEIVED DATA BITS
Description: Holds the character just read. If less than eight bits are
215
DLV11-F
selected, then the buffer Is right-justified into the least significant bit
positions. In this case, the higher unused bit or bits are read as Os.
Read-only bits; not cleared by INIT.
NOTE
INIT
= LSI-11 bus BINIT signal assertion.
The word format for the OLV11-F XCSR register is shown in Figure 7
and functionally described in Table 8.
14
13
II
10
Figure 7
Table 8
09
08
07
06
00
OLV11-F XCSR Word Format
DLV11-F XCSR Bit Assignments
Bit: 15-12
Name: PBR SEL
Description: (Programmable Baud Rate Enable)
When set, these bits choose a baud rate from 50-9600 baud. See
Table 3.
Write-only bits.
Bit: 11
Name: PBR ENB
Description: (Programmable Baud Rate Enable)
This bit must be set in order to select a new baud rate indicated by bits
12 to 15.
Write-only bits.
Bit: 10-8
Name: Not used
Description: Reserved for future use.
Bit: 7
Name: XMIT ROY
Description: (Transmitter Ready)
This bit is set when the transmitter buffer (XBUF) can accept another
character. When set, it initiates an interrupt sequence provided XMIT
INT ENB (bit 6) is also set.
Bit: 6
Name: XMIT INT ENB
Description: (Transmitter Interrupt Enable)
When set, allows an interrupt sequence to start when XMIT ROY (bit 7)
is set.
Read/write bit; cleared by INIT. (See Note.)
216
DLV11·F
Bit: 5-3
Name: Not used
Description: Reserved for future use.
Bit: 2
Name: MAINT
Description: Used for maintenance function. When set, connects the
transmitter serial output to the receiver serial input while disconnecting the external device from the receiver serial input. It also forces the
receiver to run at transmitter baud rate speed when common speed
operation is enabled.
Read/write bit; cleared by INIT.
Bit: 1
Name: Not used
Description: Reserved for future use.
Bit: 0
Name: BREAK
Description: When set, transmits a continuous space to the external
device.
Read/write bit; cleared by INIT.
NOTe
When clearing an Interrupt enable bit, first set the
appropriate processor status word bit = 1. After the
interrupt enable bit at the module is cleared, the
processor may be returned to its normal priority.
The word format for the DLV11-F XBUF register is shown in Figure 8
and functionally described in Table 9.
08
Hi
07
Figure 8
Table 9
00
TRANSMITTER DATA BUFFER
RESERVED
DLV11-F XBUF Word Format
11·6166
DLV11-F XBUF Bit Assignments
Bit: 15-8
Name: Not Used
Description: Not defined. Not necessarily read as Os.
Bit: 7-0
Name: TRANSMITTER DATA BUFFER
Description: Holds the character to be transferred to the external
device. If fewer than eight bits are used, the character must be loaded
so it is right-justified into the least significant bits.
Write-only bits. Not necessarily read as Os.
217
DLV11·F
I nstallatlo n
Before installing the DL V11-F on the backplane, first establish the
desired priority level tq determine in which backplane slot to Install the
module. Then ensure that the module configuration jumpers are configured correctly for your application. Connection to the ,peripheral
device is via an optional data interface cable. Cables are listed below.
Application
EIA Interface
20 mA Current Loop
Cable Type·
BC01V-X or BC05C-X Modem Cable
BC05M-X Cable Assembly
Interfacing EIA-Compatlble Devices
The DL V11-F supports only the data leads of EIA-compatible devices.
It uses a BC05C modem cable to interface devices such as the Teletype® Model 37 Teletypewriter and the Bell Data Set Model 103 (in
auto mode). The DLV11-F's EIA "data leads only" interface circuit is
shown in Figure 9 and the jumpers are shown in Figure 1.
*
x = Length in feet. Standard length Is 25 feet.
®
Teletype is a registered trademark of Teletype Corporation.
BCOI v-x or BC05C
MODEM. CABLE
DLVI1-F
rE
I
V)
I
I
-=
I REQUEST TO SEND
•
I
. C)
I FORCE
DO)
I
I DATA
I
I
I
I
I
I
BUSY
•
TERMINAL READ~
E}>+ )
XBUF
F •
I
~ J)
I TRANSMITTED DATA
I
•
I
I RECEIVED DATA
•
~I
~
• ~ '" ""'CO"
~,,lJ
Figure 9
EIA Data Leads Only Interface
Interfacing 20 mA Current Loop Devices with the DLV11-F
When interfacing with 20 mA current loop devices, the BC05M cable
assembly provides the correct connections to the 40-pin connector on
the DLV11-F. The peripheral device end of the cable is terminated with
218
DLV11-F
a Mate-N-Lok connector that is pin-compatible with all DIGITAL 20 mA
serial interface terminals.
The interface circuits provided by the BC05M cable and the associated DLV11-F jumpers are shown in Figures 9, 10and 11.
NOTE
When the DLV11-F is used with teletypewriter devices, a 0.005#lF capacitor mus·t be installed (see
DLVll.F
BCD5MCABLE
Figure 1).
+5V
+12V
PART OF
ACTIVE
TRANSMITTER
Jl
14A1
~AA)
SERIAL
OUT 1+1
.
13P},
,,
,
\
XBUF
I
J
J
I
TRANSMIT
DATA
,/
,14P1
ISAI
KK)
SERIAL
DUTH
PART OF
ACTIVE
TRANSMITTER
•
.ODJ Iuert- solid-liDS 3U11pers.
1.
4.l Bid Sa. to ooDtiSure
tor aoUve tralL8lllitter.
+5V
2. lIl8e1!t:. dot'ted-11ll8 3wap81'!8
1ao aiD.in oompat1bllit,:
with DLV11 whan ooDtigur..
iDs tor passive transmitter.
DATOOH
REGISTER SELECT
L..-_ _ _ _ _ _ _~ pp )
tr------~) EE)
READER
RUN 1+1 ..
READER
RUNH •
11.4933
·12V
Figure 10
20 mA Transmitter and Reader Run Circuits
219
DLV11·F
+5V
+t2V
(tAl
FOR TTY
ONLY
2AI
n
13A)
'='
Jt
K
>-r- (+1
S
>-r-1-I
I
I
I SERIAL
DATA IN
I
I
I
I
I
I
I
20mA RECEIVED DATA
I
I
RBUF
Figure 11
TTL SERIAL DATA IN
Active Receive 20 rnA Current Loop
+5V
ItPI Jt
.----o--o---.-~ K}-,....- I + I
I
I
I SERIAL
<----o(2_Po()l-+~ S
FOR TTY
ONLY
DATA IN
>-+- 1-1
I
I
I
I
I
I
20mA/TTL RECEIVED DATA
RBUF
TTL SERIAL DATA IN
I
I
H
~
E~
20mA INTERLOCK
J
11-4911
Figure 12
Passive Receive 20 rnA Current Loop
220
DLV11-J
DLV11-J FOUR ASYNCHRONOUS
SERIAL INTERFACES
GENERAL
The DLV11-J is a 4-channel asynchronous serial line unit used to
interface peripheral equipment to an LSI-11 bus. The interface transmits and receives data from the peripheral device over Electronics
Industry Association (EIA) "data leads only" lines which do not use
control lines. The module can be used with 20 mA current loop devices (with "reader-run" capabilities) when the DLV11-KA option is
installed. With a DLV11-J interface, the processor can communicate
with a local terminal such as a console teleprinter, a remote terminal
via data sets and private line, or another local or remote processor.
FEATURES
• Four independent, full-duplex, asynchronous serial line interfaces to
the LSI-11 bus on one double-height module.
• Each channel independently configured for:
1. EIA RS-232C, RS-422, RS-423
2. Baud Rates: 150,300,600,1200,2400,4800,9600, 19.2K, 38.4K
and external
3. Variable character format:
7 or 8 data bits;
1 or 2 stop bits;
odd, even or no parity
4. Support for data leads only: MODEMS (Bell type: 103, 113)
• One channel configurable as computer console device interface,
including halt or boot on received break.
• 8.9 in. X 5.2 in. (22.8cm x 13.2cm) module
• 20 mA current loop and 110 baud capability optionally added using
the EIA to 20 mA converter (DLV11-KA).
• The DLV11-KA provides: (Figure 1)
1. Single line EIA to 20 mA converter unit and 3 ft. (.91 m) cable for
connection to DLV11-J.
2. A program-controlled, reader advance function for DIGITALmodified ASR33 teletypes.
3. A 110 baud rate generator.
4. Choice of active or passive operation.
5. Operation up to 9600 baud.
6. Cable drive capability up to 4000 feet.
221
DLV11·J
SPECIFICATIONS
Identification
M8043
Size
Double
Power
+5 V ±5% at 1.0 A
+12 V ±3% at 0.25 A
Bus Loading
1
1
AC
DC
DESCRIPTION
General
The DLV11-J module Is aesigned to interface peripheral devices that
transmit and receive asynchronous serial data over EIA-compatible
data lines or 20 mA current loops to the parallel LSI-11 bus. When
configured, the module transmits and receives the specified EIA signal
levels on the receive and transmit data lines of the cable. Also, the
module constantly asserts the data-terminal-ready signal.
When configured for 20 mA current loop operation (DLV11-KA option
installed), the DL V11-J can support devices which contain programcontrolled paper tape readers (such as DIGITAL's LT33 Teletypewriters or the ASR33 Teletypewriter with the LT33 modification kit.)
During operation, the module is required to convert data from parallel
to serial and serial to parallel. To accomplish this, a universal asynchronous receiver/transmitter (UART) is employed. When performing
this conversion, the UART must also alter the speed and character
format for the data (to meet user-selected parameters). In addition,
the UART creates error bits to allow the programmer to check data
transmission for errors. A block diagram of the DLV11-J module is
shown in Figure 1.
UART Operation
The DLV11-J module is equipped with four universal asynchronous
receiver/transmitters, one for each channel. The UART chip is capable
of parallel data transfers with the computer and serial data transfers
with the peripheral device. User-selectable jumpers determine the
character format used during transmission. The jumpers select:
7 or 8 data bits
1 or 2 stop bits
Parity or no parity
Even or odd parity
222
DLV11-J
The receiver section performs serial-to-parallel conversion of data
which will always appear right-justified in the receive data buffer. The
start, stop, and parity bits are removed and error flags appended to
the transmission as It enters the receive buffer. The error flags, when
set, will not interrupt operation, but they are available to the programmer when reading the RBUF.
.g
..c..
>
u
li
"u
N
'0
'I""
CD
CD
.
-
.
-
.c
~
E
...as
i
is
~
()
0
iii
...,
I
'I""
'I""
>
..J
C
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...
CD
:::J
0)
ill
..
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c
223
BIAKI
BIAKO
BIRO
BINIT
J2
REC
XMIT
BOCOK
FEJ
SHALT
JJ
I\)
I\)
~
M
CD
GND~
REC
GND~
GND~
GND~
---.!!:!!.l
IBMU
GND
GND
GND
GND
GND
IBTl)
IBel)
IAL2I
§GN
D
+5V
CHARGE
PUMP
-12V
+12V
+5V~
+5V~
+5V~
IAD2)
I
BAUD
RATE
GENERATOR
+12V
+12 f
NOTES
DETAilED SCHEMATICS MAY BE ORDERED
USING PRINT SET ORDER NUMBER MPOO586.
-B~_ _-+-_~_ _ _ _ _~-+-_2 (
XMT DATA
RCV DATA
RCV DATA GRD
)-2_ __
GRD
7
T------------~----(
GRD
r--'W--_____________ --¥-_l_(
!;hield
Important:
Attach to chassis
at entry point.
Figure 8
BC20N-05 "Null Modem" Cable
PROGRAMMING
The DLV11-J contains a bank of sixteen (16) contiguous registers that
may be positioned from 1600008 to 1777778 In address space by wire
wrap jumpers. Four registers are provided for each of the four SLU
channels.
The format of these registers is shown In Figure 1.
Similarly. the DLV11-J has a bank of eight contiguous Interrupt vectors that may be positioned In vector space from 0008 to 3778 by
jumpers. Two vectors (receive and transmit) are provided for each of
the four channels.
NOTE
One channel may be separately configured as the
computer console device (177560-6 8, vectors 60 and
64) provided the module base address Is 1765008,
1765408 or 1775008,
To software. the DLV11-J appears to be four Independent serial line
units similar to four single-channel DLV11s.
249
DLV11·KA
DLV11-KA EIA TO 20 MA CONVERTE·R
GENERAL
The DLV11-KA option consists of the DLV11-KB EIA-to-20 rnA
converter unit and a BC21 A-03 EIA Interface cable. This option Is
designed to allow 20 rnA current loop capability to be added to a
standard RS-232 EIA serial line unit Interface module, such as the
DLV11-J. The DLV11-KB Is a small enclosed box·wlth two connectors,
one (2 x 5 pin Berg) for the EIA/TTL signals from the Interface module
and the other (standard DIGITAL 20 rnA connector 8-pln Mate-N-Lok)
for the 20 mA signals to 20 mA peripherals using standard DIGITAL 20
rnA cabling.
FEATURES
• EIA RS-232 to 20 rnA converter (XMT data)
• 20 rnA to EIA RS-232 converter (RCVR data)
• A program-contrOlled, one character at a time reader advance function for DIGITAL-modified ASR-33 Teletypes
• A 110 baud rate generator
• Optical Isolation
• Choice of active or passive operation
• Operates up to 9600 baud rate
• Drive capability up to 4000 feet of cable
* Teletype Is a registered trademark of Teletype Corporation.
SPECIFICATIONS
Size:
13.3cm (5.25 In.) long
11.4cm (4.5 In.) wide
2.64cm (1.04 In.) high
Power:
+ 12.0 Vdc ±5% at 0.275 A max
20 mA Transmitter
Switch Is passive and optically Isolated and goes to "mark" state when
power Is turned off (passive mode).
Minimum
Typical
Maximum
Open circuit voltage
(of circuit being driven)
8.0V
40V
Voltage drop marking
0.5V
2.0V
251
DLV11-KA
Spacing current
0.4 rnA
1.SmA
Marking current
20 rnA
Rise and fall time
2 itS
6 itS
10 itS
Waveform distortion
oitS
7 Jl,S
15 itS
Constant current sink
(active mode)
20 rnA
24 rnA
2SmA
SOmA
When the transmitter Is active, the maximum cable loop resistance
plus receiver equivalent resistance (at 20 rnA) is 600 ohms.
20 mA Receiver
Receiver Is passive and optically Isolated.
Minimum
Typical
Maximum
Voltage drop marking
0.4V
1.35V
2.4V
Spacing current
0.0 rnA
6mA
Marking current
16mA
SOmA
Waveform distortion
oitS
7 itS
15 itS
Constant current load
(active mode)
20mA
24 rnA
2SmA
When the receiver Is active, the maximum cable loop resistance plus
transmitter equivalent resistance (at 20 rnA) Is 600 ohms.
Temperature
Storage temperature range:
-40 0 C to 66 0 C (-40 0 F to 151 0
F)
Before operating a module which
Is at a temperature beyond the
operating range, that module
must first be brought to an environment within the operating
range and then allowed to stabilIze for a reasonable length of time
(five or more minutes, depending
on air Circulation).
50 Ct060° C(41° Fto 1400 F)
Operating temperature range:
Derate the maximum operating
temperaure by 0.5 0 C (1 0 F) for
each 1000 feet of altitude above
SOOOfe~t.
252
DLV11-KA
Relative Humidity:
10% to 95%, noncondenslng
Altitude:
Up to 50,000 feet (90 mm mercury)
Environment:
Air must be noncaustlc
DESCRIPTION
The DLV11-KA contains the following functional circuits (Figure 1):
EIA-to-20 rnA converter, 20 mA-to-EIA converter, reader run, 110
baud rate generator, current sources and current sinks, a +5 Vdc
generator and a -12 Vdc charge pump. These circuits are selected by
the user to operate In a desired configuration.
EIA·to·20 mA
The circuit accepts a standard EIA RS-232 signal to an EIA receiver
and then provides optical Isolation before It activates a passive 20 mA
switch. When the EIA Input Is In the "mark" condition (less than -3V),
the switch Is on. When the EIA Input Is In the "space" condition (greater than +3V), the switch Is off. The user can select passive or active
operation by using jumpers as described In the Configuration section.
The current source Is provided by a 180 ohm resistor connected to the
+ 12 Vdc and the current sink Is provided by a 24 mA current-limited
load to -12 Vdc.
20 mA·to·EIA
The circuit receives a 20 rnA signal In a passive 20 mA detector. The
signal Is optically Isolated and then generates a standard EIA RS-232
output. With the 20 rnA current signal flowing Into the 20 rnA detector,
the EIA output Is In the "mark" state (less than -3V). With the 20 mA
current off, the EIA output Is In the "space" state (greater than +3 V).
The current source Is provided by a 180 ohm resistor connected to the
+12 Vdc and the current sink Is provided by a 24 mA current-limited
load to -12 Vdc. When using this circuit with an ASR-33 Teletype, the
user should Install the noise suppression capacitor.
Reader Run
The reader run circuit receives a TTL pulse to set a flip-flop. This flipflop enables the relay drive circuit that drives the reader run relay In a
DIGITAL-modified ASR-33 Teletype. The Teletype reader will advance
to the next character and Initiate Its transmission down the line. A
delay circuit Is used to reset the fllp·flop In the middle of the start bit
and therefore disable the reader run circuits. When the first character
has been received, the flip-flop may again be set to advance to the
next character for Its transmission. When used with the DLV11·J Inter-
253
DLV11·KA
face module, the circuit ailows only one character to be transmitted by
the Teletype each time a 1 Is written into the reader enable bit of the
RCS register.
NOTe
For proper operation of Teletype ASR-33 with
DIGITAL-supplied paper tape software, the SLU
should be configured for eight data bits, two stop
bits, and no parity. The Teletype models can be
LT33-DC, LT33-DD, LT33-DE, or an ASR-33 Teletype with the LT33-MB modification kit Installed.
110 Baud Rate Generator
A 614.4 kHz crystal oscillator frequency Is divided by 352 (by 11 and
32) to produce a 110 baud UART clock at 1760 Hz (16 x 110). This
signal Is sent back to the SLU module through the BC21A-03 cable.
+5 Vdc Generator
The +5 Vdc voltage Is generated by a zener diode that drops the +12
Vdc power to +5 Vdc and Is for internal use only.
-12 Vdc Charge Pump
The -12 Vdc charge pump uses the output of the 614.4 kHz crystalcontrolled clock that Is amplified and then rectified to produce the -12
Vdc reference voltage.
254
DLV11-KA
lS0n
+12V
Jl (EIA)
I J2 (20mA)
I CURRENT
CURRENT
SOURCE
EIA
RS·232
RECEIVER
WI
: a
W2
20mA
SWITCH
OPTICAL
ISOLATION
W3
:
W5
~
D
W4
,4mA
I
~ CURRENT I
SINK
lS0n
+12 V
-12 VDC
CURRENT
SOURCE
EIA OUT
3
W6
: a
W7
EIA
RS232
DRIVER
20mA
DETECTOR
WS
:
IOUT+
I
(5
I
I CURRENT
IOUTI (2
I
II
I
:
I CURRENT
liN +
I
(7
I CURRENT
liN I
(3
W'"f' :
24mA
I
• CURRENT I
SINK
I
-12 VDC
READER
PULSE
I
I
I
I READER'
6
~12
VDC
110 BAUD
OUTPUT
10 >--+-Q-C>----i
Figure 1
DLV11-KA Functional Block Diagram
255
DLV11-KA
CONFIGURATION
The DL V11-KA requires the configuration of eleven jumper wire connections and one capacitor connection. The locations of these jumpers are shown In Figure 2 and their functions are listed In Table 1.
Current Loop Definition
In simplest terms, the current In a circuit loop which extends from the
sender to the receiver Is switched on and off to represent some particular format for serial transmission of binary data. Besides the actual
current path (wire), the following other three functions are required In
every current loop:
3. Current detector
1. Current source 2. Switch
The switch has to be located In the transmitter, and the current
detector has to be located In the receiver. However, the current source
may be located In either the sender or receiver. The function that
includes the current source Is designated active and the one without It
passive. Only one passive and one active function are allowed In a
current loop: never two active or two passive functions (Figure 3). In
order to minimize ground differential noise coupling Into data leads,
the transmitter and receiver at one end of the line should be either
both active or both passive, not mixed. Also, It Is usually better to
configure the computer (master computer) as active and the terminal
(slave computer) as passive.
110 Baud Rate Generator
This circuit provides a 16 x 110 (1760 Hz), TTL level, crystal-controlled
clock to be sent back to the serial line unit module in order to add 110
baud rate capability to the module. A solderable jumper (W11) Is provided in order to select or deselect this function.
J1
0--011
O--<>C
60--0
0--01
70--0
O--OB
, L - - - . . . . . . j 90--0
0--03
r-----,---' 4 ~5
20--0
0--0 10
NOTE:
THE NUMBER 2 INDICATES THAT
IT IS THE W2 JUMPER WIRE.
Figure 2
MR·2240
DLV11-KA Jumper Locations
256
DLV11-KA
DLV11-K~Jumper
Table 1
Function
Configurations
Jumper In
W7,W9
W6, wa, W10
W2,W4
W1,W3,W5
W11
Passive 20 rnA Receiver
Active 20 rnA Recelver*
Passive 20 rnA Transmitter
Active 20 rnA Transmltter*
110 Baud Enabled*
110 Baud Disabled
Noise Suppression
Jumper Out
W6,Wa,W10
W7,W9
W1,V'3,W5
W2,W4
W11
* Factory configuration.
PASSIVE RECEIVER
ACTIVE TRANSMITTER
CURRENT
SOURCE
XMIT
+
1
T
..:
~
REC
-
I
CURRENT
DETECTOR
l RCVR
J
RECEIVED
DATA
I
XMIT
I
_ _ _ _ _ _ _ _ ..JI
20MA
LOOP
I
,
.A'_
-
IN TERFAC E
CABLE
REC
-
+
TRANSMITTED
DATA
ACTIVE RECEIVER
RECEIVED
DATA
--------~
I
-
1
T
I
I
CURRENT
DETECTOR
PASSIVE TRANSMITTER
I
I
XMIT
R!C
-
,.
1,L _
r
..:
REC
-
CURRENT
SOURCE
Figure 3
20MA
LOOP
XMTR
"
XMIT
+
Standard Current Loop Interface
257
TRA NSMITTED
OAT A
DLV11·KA
Noise Suppression Capacitor
The DLV11-KA can be used with a DIGITAL-modified ASR-33 Teletype
and requires the user to Install a 0.047 p.F capacitor for noise suppression. This capacitor is installed across the position designated "C" as
shown In Figure 2.
Installation
The DL V11-KA option can be installed in a system that requires conversion from EIA RS-232 standard to a 20 mA current loop. The
DLV11-KA option consists of a DLV11-KB converter box and a
BC21A-03 Interface cable as shown in Figure 4. The BC21A-031s a 0.9
m (3 ft.) cable that interconnects the DLV11-KB to a EIA SLU Interface
module. The smaller connector (2 x S pin) connects to the SLU module and the larger connector (2 X 7 pin) connects to the DLV11-KB
box. Keying is provided on both connectors, and cable retention Is
provided by locking pins on the SLU connector. To disengage, pull
back on the connector shell and the connector will slide free. However,
if the cable is pulled, the locking pins will hold the connector firmly In
place. A BCOSF-XX cable can be used to connect the DLV11-KB
converter box to DIGITAL 20 mA terminals Including the DIGITALmodified ASR-33 Teletype. External mounting dimensions for the
DLV11-KB box are shown In Figure S.
Cabling
Cables other than the DIGITAL BCOSF-XX can be used when Installing
the DLV11-KA option. However,' any other cable must conform to the
following parameters In order to meet the baud rate versus cable
length specification described In Table 2.
1. Resistance-not more than 30 ohms/1000 ft. (not less than 22
AWG)
2. CapaCitance to ground-not more than SO pF/ft.
3. CapaCitance wlre-to-wire-not more than 3S pF/ft.
The BCOSF-XX cable meets the above requirements. If the user desires to use shielded cable, the shield should be grounded to the
chassis at entry point and not to the DLV11-KB converter box. The
user can fabricate custom cables for the 20 mA Interface by using
DIGITAL connectors and pins.
Baud Rate
The DLV11-KA option will operate up to a maximum of 9600 baud,
provided that the interface module can accommodate these rates.
258
DLV11·KA
However, the maximum operational baud rate Is also limited by the
length of cable. Table 2 provides maximum recommended cable
lengths for the specific baud rates. These recommendations are conservative and will yield satisfactory operation for almost all appllca..
tlons. exceeding these guidelines should be done only after reviewing
the DLV11-KA specificatiOns, the severity of the operating environment, and the error rate that can be tolerated.
DlVll-KA OPTION
BC21A-03
CABLE
BC05F·XX
CABLE
(NCI
+12 VDC
P2
PI
10 )~-:--------« 1
SIG GND
9 )
EIA OUT
8)
EIA SlU
INTERFACE
MODULE
SUCH ASTHE
DlVll-J
SIG GND
7)
5 )
2 (
( 3
3 (
KEY
I READER PlS
EIA IN
3 )
1 )
( 5
~6
DlVll·KB
EIAT020mA
CQNVERTER
BOX
5(
6 (
I
I
2)
4 (
(4
I
6~
4 )
( 2
SIG GND
I
1 (
SIG GND
t
7 (
(8
8 (
CllN READER CLOUT +
READER +
MATE 'N'lOK
CONN
(10
t
T020mA
DEVICE
2 X 5 PIN
BERG CONN
o
0
J2 MATE 'N' lOK
CONNECTOR
Jl BERG
CONNECTOR
DLV11-KA Typical Installation
259
(NCI
t
( 9
KEY
INOPINI
Flgure4
ClOUT-
ClIN+
( 7
110BAUD
2 x 5 PIN
AMP CONN
I
DLV11-KA
ffii
~
~
J2
J1
lB~+
-----,....I
I.t------3.S0----__. . . .
L082--t. . .
NOTE:
COMPATIBLE WITH RETMA RACK SPACING.
Figure 5
Table 2
DLV11-KA Mounting Dimensions
Baud Rate vs. Cable Length
Baud Rate
Max Cable Length
9600
30 m (100 ft.)
4800
76 m (250 ft.)
2400
152 m (500 ft.)
1200
305
600
m (1000 ft.)
610 m (2000 ft.)
300
1220 m (4000 ft.)
110
1220 m (4000 ft.)
260
DRV11
DRV11 PARALLEL LINE UNIT
GENERAL
The DRV11 is a general-purpose interface unit used for connecting
parallel line TTL or DTL devices to the LSI-11 bus over up to 7.6 m (25
ft) of cable. It permits program-controlled data transfers at rates up to
40K words per second and provides LSI-11 bus interface and control
logic for interrupt processing and vector generation. Data is handled
by 16 diode-clamped input lines and 16 latched output lines. The
device address is user-assigned and control/status registers (eSR)
and data registers are compatible with PDP-11 software routines.
FEATURES
• 16 diode-clamped data input lines
• 16 latched output lines
• 16-bit word or a-bit byte programmed data transfers
• User-assigned device address decoding
• LSI-11 bus interface and control logic for interrupt processing. and·
vector generation
• Interrupt priority determined by electrical position along the LSI-11
bus
• Control/status registers (eSR) and data registers that are compatible with PDP-11 software routines
.
• Four control lines to the peripheral device for NEW DATA RDY,
DATA TRANS, REO A, and REO B
• Logic-compatible with TTL and DTL devices
• Program-controlled data transfer rate of 40K words per second
(maximum)
SPECIFICATIONS
Identification
M7941
Size
Double
Power
5.0 Vdc ±5% at 0.9 A
Bus Loads
AC
De
1.4
1.0
DESCRIPTION
General
Major functions contained on the DRV11 module are shown in Figure
1. Communications between the processor and the DRV11 are execut261
DRV11
ed via programmed 1/0 operations or interrupt-driven routines.
~
~
BIROL
BIAKIL
BIAKOL
BDAL 0-15 L
i
~
-I
BDALO-I5L
DROUTBUF
1
OUT O-I!!
J INTERRUPT
'[NT I'"NA A
INT ENB B
LOGIC
DRCSR
l
II
,.:!.!
REO A
CSRI
NEW OATA RDY
[~
J2
BBS7L
BSYNCL
BDAL 0-15 L
BWTBT L
BDIN L
BDOUTL
BRPLY L
BINITL
BINIT
ADDRESS
AND 1/0
CONTROL
LOGIC
TO I FROM
USER
DEVICE
LOGIC
r=
REO B
CSRO
DATA TRANS
I
BDAL 0-\5 L
I
"'V
Figure 1
DRINBUF
L
IN 0-15
I
-
DRV11 Parallel Line Unit
The DRV11 is capable of storing one 16-blt output word or two 8-bit
output bytes in DROUTBUF. The stored data (OUTO-15 H) Is routed to
the user's device via an optional I/O cable connected to J1. Any programmed operation that loads a byte or a word In DROUTBUF causes
a NEW DATA ROY H signal to be generated, Informing the user's
device of the operation.
Input data (DRINBUF) is gated onto the BDAL bus during a DATI bus
cycle. All 16 bits are placed on the bus simultaneously; however, when
the processor is involved in an 8-blt byte operation, It uses only the
high or low byte. When the data is taken by the processor, a DATA
TRANS H pulse is sent to the user's device to inform the device of the
transfer.
Addressing
When addressing a peripheral device Interface such as the DRV11, the
processor places an address on BDALO-15 L, which Is received and
distributed as BRDO-15 H in the DRV11. The address Is In the upper
4K (28-32K) address space. On the leading edge of BSYNC L, the
address decoder decodes the address selected by Jumpers A3-A 12
and sets the device selected flip-flop (not shown); the active flip-flop
output Is the ME signal, which enables function selection and 110
control logic operation. At the same time, function selection logic
stores address bits BRDO-2.
262
DRV11
NOTE
When addressed, the DRV11 always responds to eIther BDIN L or BDOUT L by asserting BRPLY L (L =
assertion).
Function Selection
Function selection and I/O control logic monitors the ME signal and
bus signals BDIN L, BDOUT L, and BWTBT L. It responds by generating appropriate select signals which control Internal data gating. NEW
DATA ROY H or DATA TRANS H output signals for the user's device,
and the BRPLY L bus signal which Informs the processor that the
DRV11 has responded to the programmed I/O operation. Since the
DRV11 appears to the processor as three addressable registers
(DRCSR, DROUTBUF, and DRINBUF) that can be Involved In either
word or byte transfers, the three low-order address bits stored during
the addressing portion of the bus cycle are used for function selection.
The select signals relative to 1/0 bus control signals and address bits
0-2 are listed In Table 1.
Function selection Is performed by a ROM located at E15 on the
DRV11. The Inputs to this ROM consist of the address bits and other
LSI-11 bus signals as shown at the top of Table 1. This table shows the
functions performed by the ROM outputs for a specific Input condition.
For example, when the output buffer Is addressed by the processor,
the last octal digit Is decoded by the ROM to provide the SEl21N Land
the RPL Y L signals. The RPLY L signal Is delayed and becomes the
BRPLY L signal. The SEL21N L signal Is used by the DRV11 logic to
enable the contents of the output buffer register to be placed on the
data lines of the LSI-11 bus so that the processor can read the data.
NEW DATA READY H is active for the duration of BDOUT L when In a
DROUTBUF write operation. This signal Is normally active for 350 ns.
However, by adding an optional capacitor In the BRPLY L portion of
the circuit, the leading edge of BRPLY Is delayed, effectively Increasing the duration of the NEW DATA ROY H pulse; adding the capacitor
also increases the DATA TRANS H pulse width by approximately the
same amount.
DATA TRANS H Is active for the duration of BDIN L when In a DRINBUF read operation. This signal Is normally active for 1150 ns. The
time, however, can be extended by adding the optional capacitor to
the BRPLY L portion of the circuit as previously described.
263
Table 1
DRV11 Device Function Decoding
Programmed
Operation
0-2
BWTBTL
During
Data
Transfer
WriteDRCSR
0
0
0
1
H
H
L
L
DATO
DATOB
ReadDRCSR
0
0
L
H
DATI or
DATIO
SELOIN L
Write
DROUTBUF
Word
2
0
H
L
DATO
SEL20UT
(W+ HB)L.
SEL20UT
(W + LB) L. and
NEW DATA
READYH
Stored
Device
Addr. Bits
BDINL
BDOUTL
Bus Cycle
Type
Select
Signals
SELOOUTI
N
~
Low Byte
2
H
L
DATOB
SEL20UT
(W + LB)L
and
NEW DATA
READYH
High Byte
3
H
L
DATOB
SEL20UT
(W + HB)L
and
NEW DATA
READYH
Read
DROUTBUF
Read
DRINBUF
2
0
L
H
SEL21N L
4
0
L
H
DATI or
DATIO
DATI
SEL41N Land
DATATRANSH
e
<
:II
~
~
DRV11
Read Data Multiplexer
The read data multiplexer selects the proper data and places them on
the BDAL bus when the processor Inputs DRCSR, DROUTBUF or interrupt vectors; DRINBUF contents are gated onto the bus separately.
The select signals (previously described) and VECTOR H, produced
by the interrupt logic, control read data selection.
DRCSR Functions
The control/status register (DRCSR) has separate functions. Four of
the six significant DRCSR bits can be Involved in either write or read
operations. The remaining two bits,· 7 and 15, are read-only bits that
are controlled by the external device via the REO A H and REO B H
signals, respectively. The four read/write bits are stored in the 4-bit
CSR latch. They represent CSRO and CSR1 (DRCSR bits 0 and 1,
respectively), which can be used to simulate interrupt requests when
used with an optional maintenance cable. INT ENB A and INT ENB B
(bits 6 and 5, respectively) enable interrupt logic operation. Note that
CSRO and CSR1 are available to the user's device for any user application.
DRINBUF Input Data Transfer
DRINBUF is an addressable 16-bit read-only register that receives
data from the user's device for transmission to the LSI-11 bus. Data to
be read are provided by the user's device on the INO-15 H signal lines.
Since the input buffer consists of gating logic rather than a flip-slop
register, the user's device must hold the data on the lines until the data
Input transaction has been completed.
The input data are read during a DATI sequence while bus drivers are
enabled by the SEL41N L signal. The DATA TRANS pulse that is sent to
the user's device by the function select logic informs the device of the
transaction. Input data can be removed on the trailing edge of this
pulse.
DROUTBUF Output Data Transfer
DROUTBUF comprises two a-bit latches, enabling either 16-bit word
or a-bit byte output transfers. Two SEL2 signals function as clock
signals for the latches. When In a DATO bus cycle, both signals clock
data from the internal BRDO-15 H bus Into the latches. However, when
in a DATOe cycle, only one signal clocks data into an a-bit latch, as
determined by address bit 0 previously stored during the addressing
portion of the bus cycle.
265
DRV11
The NEW DATA ROY H pulse generated by the function select logic is
sent to the user's device to inform the device of the data transaction.
The data can be input to the device on the trailing edge of this pulse.
Interrupts
The DRV11 contains LSI-11 bus-compatible interrupt logic that allows
the user's device to generate Interrupt requests. Two independent
interrupt request signals (REO A H and REO B H) are capable of
requesting processor service via separate interrupt vectors. In
addition, DRCSR contains two interrupt enable bits (INT EN A and INT
EN B, bits 6 and 5, respectively), which independently enable or disable interrupt requests. REO A and REO B status can be read by the
processor in DRCSR bits 7 and 15, respectively. Since separate interrupt vectors are provided for each request, one of the requests could
be used to imply that device data is re~dy for input and the remaining
request could be used to imply that the device is ready to accept new
data.
An interrupt sequence is generated when a DRCSR INT EN bit (A or B)
is set and its respective REO signal is asserted by the device. The
processor responds (if its PS bit 7 is not set) by asserting BDIN L; this
enables the device requesting the interrupt to place its vector on the
BDAL bus when the interrupt request is acknowledged. The processor
then asserts BIAKO L, acknowledging the interrupt request. The
DRV11 receives BIAKI L and the interrupt logic generates VECTOR H,
which gates the jumper-addressed vector information through the
read data multiplexer and bus drivers and onto the LSI-11 bus. The
processor then proceeds to service the interrupt request.
Maintenance Mode
The maintenance mode allows the user to check DRV11 operation by
installing an optional BC08R cable between connectors J1 and J2.
This maintenance cable allows the contents of the output buffer
DROUTBUF to be read during a DRINBUF DATI bus cycle. In addition,
interrupts can be simulated by using DRCSR bits CSRO and CSR1.
CSR1 is routed via the cable directly to rhe REO B H input and CSRO is
routed to the REO A H input. By setting or clearing INT EN A, INT EN B,
and CSRO and CSR1 bits in the DRCSR register, a maintenance program can test the interrupt faCility.
Initialization
BIN IT L is received by. a bus driver, inverted, and distributed to DRV11
logic to initialize the device interface. The buffered initialize signal is
266
DRV11
available to the user's device via the AINIT Hand BINIT H signal lines.
DRV11 logic functions cleared by the BINIT signal Include DROUTBUF, DRCSR (bits 0, 1, 5, and 6), and Interrupt logic.
CONFIGURATION
The following paragraphs describe how the user can configure the
module by inserting or removing jumpers (Figure 2) so that it will
function within his system. The jumpers, listed In Table 2, indicate the
factory configuration when shipped.
c
u
c
U
J1
J2
r
V~~R~U;P;-S - ,
I V4
I
I
-va I
-
I
I
I
I
I V3 -v61
L ___ =-=-V~
i ADDREsS'JuMPERs- i
I
I
I
I
A3A4-
~g==
_A9
-AIO
=m
SLl
'.I
SL2
0---1r--<»
I
I
I
I
OPTIONAL EXTERNAL
CAPACITOR
A7LA.!=-::
_____ -I
Figure 2
DRV11 Jumper Locations
267
DRV11
Table 2
DRV11 PLU Factory Jumper Configuration
Jumper
Designation
Jumper
State
A3
A4
A5
A6
A7
R
R
AS
R
A9
A10
A11
A12
R
R
I
V3
V4
V5
V6
V7
* R
R
R
R
R
I
I
I
R
R
Function Implemented
This arrangement of jumpers A3 through
A 12 assigns the device address 16777X
to the PLU. This address Is the starting
address of a reserved block In memory
bank 7 which is recommeded for user
device address assignments. The least
significant digit X is hardwired on the
module to Implement the three PLU device addresses as follows:
X= 0
X= 2
X=4
DRCSR address
Output buffer address
Input buffer address
This factory-installed jumper configuration implements the two interrupt vector
addresses 300 and 304 for use as defined by application requirements.
= Removed, I = Installed
Device Address
Addresses for the DRV11 can range from 16000X through 17777X.
The three least significant bits are predetermined for the other DRV11
registers as shown in Table 3 and Figure 3. Addresses within 177560
to 177566 are reserved for the console device and should not be used
for the DRV11.
268
DRV11
Table 3
Description
Standard Asslgnements
Mnemonic
Readl
Write
Second
First
Module Module
Address Address
Register
Control and
Status
Output Buffer
Input Buffer
DRCSR
R/W
167770
167760
DROUTBUF
DRINBUF
R/W
R
167772
167774
167762
167764
Interrupt
Request A
Request 8
REQA
REQ8
300
304
310
314
J :5
I1 I I l
I
I
"71.......L..~--;-~--I....-;-"~~~~~.......I.-;-t=====;-·I.LBYTE SELECT
t=:=BB::S7=L==:7'
·\lLI
~
C
~
:;
:
~
:
~
:
~
L I · h IQhbyI818-,51
\
ADDRESS JUMPERS:
INSTALLED '0
REMOVED '1
Figure 3
~;~~;T:y~e(O-7)
OOX' ORCSR
01 x • OROUTBUF
10X'DRINBUF
\I X • NO RESPONSE
DRV11 Device Address Selection
Jumpers for bits 3 through 12 are installed or removed to produce the
16-bit address word shown in Figure 3. The appropriate jumpers are
removed to produce logical 1 bits, and installed to produce logical 0
bits.
Vectors
The two vectors are selected within the range of 000 to 374 by using
jumpers V3 to V7. Vector bits 3 through 7 are selected by the user to
form the vector as described in Figure 4. The factory configuration
sets the interrupt vector for 300 as shown in Table 3 and Figure 4.
269
DRV11
15
I I
0
0
o
I
0
I
0
0
I
0
\
! 1J
h
VECTOR JUMPERS:
INSTALLED'O
REMOVED • I
Figure 4
1L
(DRCSR-151
REOUEST! NG DEVICE
O' REO A
I -REO B
DRV11 Interrupt Vector
Registers
The word format for the control and status register (DRCSR) is shown
in Figure 5 and described in Table 4.
"R-OSIO
Figure 5
Table 4
DRCSR Word Format
DRCSR Word Formats
Bit: 15
Name: Request B.
Function: This bit is under control of the user's device and may be
used to initiate an interrupt sequence or to generate a flag that may be
tested by the program.
When used as an interrupt request, it is asserted by the external device and initiates an interrupt provided the INT ENB B bit (bit 5) is also
set. When used as a flag, this bit can be read by the program to
monitor external device status.
When the maintenance cable is used, the state of this bit is dependent
on the state of CSR1 (bit 1). This permits checking Interface operation
by loading a 0 or 1 into CSR1 and then verifying that Request B is the
same value.
Read-only bit. Cleared by INIT when In maintenance mode.
270
DRV11
Bit: 14-8 Name: Not used.
Function: Read as O.
Bit: 7
Name: Request A.
Function: Performs the same function as Request B (bit 15) except
that an interrupt Is generated only If INT ENB A (bit 6) Is also set.
When the maintenance cable Is used, the state of Request A Is Identical to that of CSRO (bit 0).
Read-only bit. Cleared by INIT when In maintenance mode.
Bit: 6
Name: INT ENB A.
Function: Interrupt enable bit. When set, allows an Interrupt request
to be generated, provided Request A (bit 7) becomes set.
Bit: 5
Name: INT ENB B.
Function: Interrupt enable bit. When set, allows an Interrupt sequence to be initiated, provided Request B (bit 15) becomes set.
Bit: 4-2
Name: Not used.
Function: Read as O.
Bit: 1
Name: CSR1.
Function: This bit can be loaded or read (under program control)
and can be used for a user-defined command to the device (appears
only on connector number 1).
When the maintenance cable is used, setting or clearing this it causes
an identical state in bit 15 (request B). This permits checking operation
of bit 15 which cannot be loaded by the program.
Can be loaded or read by the program (read/write bit). Cleared by
INIT.
Bit: 0
Name: CSRO.
Function: Performs the same functions as CSR1 (bit 1) but appears
only on connector number 2.
When the maintenance cable Is used, the state of this bit controls the
state of bit 7 (Request A).
Read/write bit; cleared by INIT
271
DRV11
The word format for the transmit output buffer (DROUTBUF) is shown
in Figure 6 and defined in Table 5.
D
15
DRDUTBUF
1
I~==========~======~~~~
DATA OUT
(READ/WRITE)
Figure 6
DROUTBUF Word Format
Table 5
DROUTBUF Word Format
Bit: 15-0 Name: Output Data Buffer.
Function: Contains a full 16-bit word or one or two 8-blt bytes; high
byte = 15-8; low byte = 7-0.
Loading is accomplished under a program-controlled DATO or DATOB bus cycle. It can be read under a program-controlled DATI cycle.
The word format for the receiver input buffer (DRINBUF) is shown in
Figure 7 and defined In Table 6.
o
15
DRINBUF
,: 1=":::I============::::::===============::l
DATA IN
(READ ONLY)
Figure 7
DRINBUF Word Format
Table 6
DRINBUF Word Format
Bit: 15-0 Name: Input Data Buffer.
Function: Contains a full 16-blt word or one or two 8-blts bytes. The
entire 16-bit word Is read under a program-controlled DATI bus cycle.
272
DRV11
Installation
Prior to installing the DRV11 on the backplane, first establish the
desired priority level for the backplane slot installaton. Check that
proper device address vector jumpers are Installed. The DRV11 can
then be installed on the backplane. Connection to the user's device is
via optional cables.
Interfacing to the User's Device
Interfacing the DRV11 to the user's device is via the two board-mounted H854 40-pin male connectors. Pins are located as shown in Figure
8. Signal pin assjgnments for input interface J2 (connector number 2)
and output interface J1 (connector number 1) are listed in Table 7.
Optional cables and connectors for use with the DRV11 Include:
BCOBR-01-Maintenance cable; 40-conductor flat with H856 connectors on each end.
BC07D-X*-Signal cable; two 20-conductor ribbon cables with a single H856 connector on one end; remaining end is terminated by the
user. Available in lengths of 3,4.6, and 7.6 m (10,15, and 25 ft).
* The -X in the cable number denotes length In feet, -10, -12, -20. For example,
a 10-ft BC07D cable would be ordered as BC07D-10.
BC04Z-X*-Flat 40-conductor signal cable with a single H856 connector on one end; remaining end is terminated by the user. Available in
lengths of 3,4.6, and 7.6 m (10, 15, and 25 ft).
BCV11-X*-Flat, 40-conductor, twisted pair cable with a single H856
connector on one end. The remaining end is connected by the user.
Available in lengths of 1.5, 3, 4.6, 6.1, and 7.6 m (5, 10, 15, 20, and 25
ft).
HB56-Socket, 40-pin female, for user-fabricated cables.
When using the BC07D cable, connect the free end of the ribbon
cables using the wiring data contained in Table 8.
273
DRV11
HIIS4
CONNECTOR
Figure 8
J1 or J2 Connector Pin Locations
* The -X In the cable number denotes length In feet, -10, -12, -20. For example,
a 10-ft BC07D cable would be ordered as BC07D-1 O.
274
DRV11
Table 7
DRV11 Input and Output Signal Pins
Outputs
Inputs
Signal
Connector Pin
INOO
IN01
IN02
IN03
IN04
IN05
IN06
IN07
INOS
IN09
IN10
IN11
IN12
IN13
IN14
IN15
REQB
DATA
TRANS
eSRO
INIT
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
J2
TableS
TT
LL
H,E
BB
KK
HH
EE
ee
Z
Y
W
V
U
P
N
M
S
e
K
RR,NN
Connector Pin
Signal
OUTOO
OUT01
OUT02
OUT03
OUT04
OUT05
OUT06
OUT07
OUTOS
OUT09
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
REQA
NEW DATA
ROY
CSR1
INIT
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
J1
C
LL
VV
J1
J1
DO
P
K
NN
U
L
N
R
T
W
X
Z
AA
BB
FF
HH
JJ
BC07D Signal Cable Connections
Cable 1 (connector pins B-VV)
Cable 2 (connector pins A-UU)
Wire
J1
J2
J1
J2
Color
Pins
Pins
Signal
Signal
Signal
Signal
blk
B
open
open
A
open
open
brn
0
open
open
e
OUTOO
DATA
TRANS
red
F
open
open
E
open
IN02
275
DRV11
Table 8
BC07D Signal Cable Connections (Cont)
Cable 1 (connector pins B-VV)
Cable 2 (connector pins A-UU)
Wire
J1
J2
J2
J1
Color
Pins
Signal
Signal
Pins
Signal
Signal
orn
J
GND
GND
H
open
IN02
yel
L
OUT04
GND
K
OUT01
CSRO
grn
N
OUT05
IN14
M
GND
IN15
blu
R
OUT06
GND
P
INIT
IN13
vio
T
OUT07
GND
S
GND
REQB
gry
V
GND
IN11
U
OUT03
IN12
wht
X
OUT09
GND
W
OUT08
IN10
blk
Z
OUT10
IN08
Y
GND
IN09
brn
BB
OUT12
IN03
AA
OUT11
GND
red
DO
CSR1
GND
CC
GND
IN07
orn
FF
OUT13
open
EE
GND
IN06
yel
JJ
OUT15
GND
HH
OUT14
IN05
grn
LL
REQA
IN01
KK
GND
IN04
blu
NN
OUT02
INIT
MM
GND
GND
vio
RR
OUT02
INIT
pp
GND
GND
gry
TT
open
INOO
SS
GND
GND
wht
VV
NEW
DATA
ROY
open
UU
GND
GND
276
DRV11
Table 9
BCOaR Maintenance Cable Signal Connection
J1
J2
Pin
Name
VV
UU
TT
SS
RR
PP
NN
MM
LL
KK
JJ
HH
FF
EE
DO
CC
BB
AA
Z
y
X
W
V
U
T
S
R
P
N
M
L
K
J
Name
Pin
OPEN
GND
INOO
GND
INITH
GND
INIT
GND
IN01
IN04
GND
IN05
OPEN
IN06
GND
IN07
IN03
GND
INOS
IN09
GND
IN10
IN11
IN12
GND
REQB
GND
IN13
IN14
IN15
GND
CSRO
GND
A
B
C
0
E
F
HH
J
K
L
M
N
P
R
S
T
U
V
W
X
y
Z
AA
BB
CC
DO
EE
FF
HH
JJ
KK
LL
MM
277
OPEN
OPEN
OUTOO
OPEN
OPEN
OPEN
OPEN
GND
OUT01
OUT04
GND
OUT05
INITH
OUT06
GND
OUT07
OUT03
GND
OUTOS
OUT09
GND
OUT10
OUT11
OUT12
GND
CSR1
GND
OUT13
OUT14
OUT15
GND
REQA
GND
DRV11
Table 9
BCOaR Maintenance Cable Signal Connection (Cont)
J1
J2
Pin
H
F
E
0
C
B
A
Name
IN02
OPEN
IN02
OPEN
DATATRAN5·
OPEN
OPEN
Pin
NN
PP
RR
55
TT
UU
VV
Name
OUT02
GND
OUT02
GND
OPEN
GND
NEW DATA ROY
Output Data Interface
The output interface is the 16-bit buffer (DROUTBUF). It can be either
loaded or read under program control. When loaded by a DATO or
DATOB bus cycle, the NEW DATA ROY H pulse is generated to inform
the user's device of the data transfer. The trailing edge of this positivegoing pulse should be used to strobe the data into the user's device in
order to allow data to settle on the interface cable. The system initialize
signal (BINIT L) will clear DROUTBUF.
All output signals are TTL levels capable of driving eight unit loads
except for the following:
New Data Ready = 10 unit loads
Data Transmitted = 30 unit loads
INIT (Initialize) = 10 units per connector
Input Data Interface
The input interface is the 16-bit DRINBUF read-only register, made up
of gated bus drivers that transfer data from the user's device onto the
L51-11 bus under program control. DRINBUF is not capable of storing
data; hence the user must keep input data on the IN lines until read by
the processor. When read, the DRV11 generates a positive-going OATA TRANS H pulse which informs the user's device that the data has
been accepted. The trailing edge of the pulse Indicates that the input
transfer has been completed.
All input signals are one standard TTL unit load; Inputs are protected
by diode clamps to ground and +5 V.
278
DRV11
Request Flags
Two signal lines (REO A H and REO B H) can be asserted by the user's
device as flags in the DRCSR word. REO B Is available via connector
number 2, and it can be read in DRCSR bit 15. REO A is available via
connector number 1, and It can be read in DRCSR bit 7. Two DRCSR
interrupt enable bits, INT ENB A (bit 6) and INT ENB B (bit 5), allow
automatic generation of an Jnterrupt request when their respective
REO A or REO B signals are asserted. Interrupt enable bits can be set
or reset under program control.
In a typical application, REO A and REO B are generated by request
flip-flops in the user's device. The user's request flip-flop must be set
when servicing is required and must be cleared by the trailing edge of
NEW DATA ROY or DATA TRANS when the appropriate data transaction has been completed.
This timing Is shown in Figure 9. The logic required by the user to
implement this is shown in Figure 10. The logic consists of a flip-flop
that is set by the User Request pulse, which indicates that the user's
device Is requesting a transfer. The flip-flop is reset by the trailing
edge of the NEW DATA ROY signal or the DATA TRANS signal.
DROUTBUF
(OUT00: OUn5) a,e set/,eset
by Ihe DRY 11 unde, canl,al 01
Ihe 11103
(data-I)
~:,::
----------X ________ ~d!!a.:.0~
(data-I)
I
I
I
I
NEW DATA READY
Pulsed by DRVI1 when the
III 03 w"I.s data to the DRYl1
.,," ,n",
a300ns
,""..J
REQUEST A
( bil 6) Inlerrupt Enable A
Set by user to allow Interrupt-dr.ven
data tranafer
I
WAIT FOR A RESPONSE TO
THE INTERRUPT REQUEST
Sol by us., when ready la, new dolo
from 11103; ,es.t!!t1!!!! upon
t,ailinQ edQe 01 NEW DATA READY
DRCSR
lj",. . . .,.,.""""
J
DRCSR
III
....
~
V
DATA FLOW_
<:...
..)
~
/I
'Ii
>'
I
......
/I
k::
DATIO - -
""
V
Figure 3
/
MEMORY
PROCESSOR
DMA DATIOIDATI Data Flow Diagram
lines and asserts BSYNC. Memory decodes and latches the address.
The DRV11-B then removes the address from the BDAL lines and
asserts BDIN. Input data is now placed on the BDAL lines by the
memory and the memory asserts BRPLY. The input data is accepted
by the DRV11-B and BDIN is negated. Memory negates BRPLY and
the DRV11-B negates BSACK and BSYNC to terminate the bus cycle
and release the bus. The output data bits for the user's 1/0 device are
stored in the DRV11-B output data buffer register. These bits can be
read by the user's device at the low-to-high transition of BUSY.
At the end of the first transfer, the DRV11-B WCR and BAR are incremented, BUSY goes high and READY remains low. The user's device
can initiate another DATI or DATIO cycle by again setting CYCLE
REQUEST. DMA transfers to the user's device can continue until the
WCR increments to zero and causes an interrupt request to be
generated.
DMA Transfers
The DRV11-B interface is designed for DMA transfers which the user
can accomplish in several ways. DMA transfers are always set up by
the processor when it loads the BAR and WCR and sets the READY bit.
The user then has the option of initiating transfers either by program
control (setting the GO bit in the CSR) or by the user device asserting
CYCLE REQUEST for 1 p,s minimum.
286
DRV11-B
Type of I/O to be Performed - The user has the option of selecting
DATI, DATO~ DATOB, or DATIO bus cycles by asserting CO and C1 per
Table 6. Note that if byte transfers are being performed, the byte
address bit (AOO) must be manipulated by the user. (Refer to the
section entitled "Word or Byte Transfers.")
Burst Mode vs. Single Cycle DMA - Single cycle DMA allows the
asynchronous transfer of data to or from the user's device. Each time
the user's device Is ready for a transfer, the user asserts CYCLE REQUEST for 1 Ils. A DMA cycle Is requested from the LSI-11 bus, and
when the bus is granted to the DRV11-B, the BUSY line is asserted to
inform the user that a data transfer is underway. The user must set up
input data when CYCLE REQUEST is asserted, and hold It valid until
the next assertion of CYCLE REQUEST. The user must strobe output
data out of the DRV11-B on the rising edge o( BUSY. The data will be
valid 250 ns minimum before the rising edge of BUSY. (Figures 12 and
13 are detailed timing diagrams.)
Burst mode DMA allows synchronous transfer of data between a
user's device and the DRV11-B. Once a DMA sequence is started
(either by the user or by the processor), data will be transferred at a
synchronous rate of 500K words per second. One data word will be
transferred every 2 IlS. The user must strobe data out of the DRV11-B
into the user's device on the rising edge of BUSY. The data to be
transferred to the DRV11-B must be set up when the READY line goes
low (for the first data transfer) or on the rising edge of BUSY (for
subsequent data transfers). (Figures 14 and 15 are detailed timing
diagrams.)
Word or Byte Transfers - The DRV11-B can transfer words or bytes
to memory. Transfers from memory are always on a word basis; if only
one byte is required, the unused bytes are disregarded. To transfer
data on a byte basis to memory, the following operations must be
performed:
1. AOO must be manipulated by the user to address the proper byte
in memory.
2. The byte to be transferred to memory must be input in its proper
position in the input word, i.e., if AOO is 1, the byte to be input must
be on the input lines IN 8 H through IN 15 H (high byte being
transferred) .
3. we INC EN Hand BA INC EN H must be asserted during the write
cycle of the first byte of each word to inhibit the BAR and WCR
from incrementing.
287
DRV11-B
LOADWCK
\l
LOADSAR
1
INT ENABLE _ _ _ _ _....
;8MkMINE~h\I....._ _ _ _X,,"_ _ _
CYCLETvnl ~/~J\
X
..-J
X
' -_ _ _ _- '
V-
...._ _ _ _" -
1
'WC INC ENABLE
SA INC ENABLE
, ' - -_ _- - J
'AOO
'SINGLECYCLE~
'CYCLE REO
"BUSY
I
'DATA FROM USER
DEVICE TO DRV11·9
{IF DATOIB!) _ _ _ _ _ _ _........
1
1
1
I .
I
I
1
I
!x'-___k~___1''----~
t
""""------I
I
"UATAfri\JI'ORV"B=r+~W
"FWA~~~~~,~~M'N
\rT~
\ri~W
Jt:tMIN
JtrMIN
LOW BYTE
"INPUT LINE FADM
USERS DEVICE
WORD TRANSfERS
~
~
HIGH BYTE
BYTE TRANSFERS
··OUTPUT LINE
TD USERS
DEVICE
Figure 4
DRV11-B Timing: Single Cycle, Asynchronous, UserInitiated
288
DAV11-B
LOADWCR
'V
LOAD BAR
...J/
INT ENABLE _ _ _ _ _
x
"CDC'
~~~---....
IDETERMINES
CYCLE TYPE, _
....._ _ _- J
X'-------'x~_>C
\~----I/
·we INC ENABLE
SA INC ENABLE
)
"ADO
·SINGLE CYCLE
""READY
"CYCLE REO
..'iUSi
LOWBVTE
-INPUT LINE FROM
USERS DEVICE
WORD TRANSFERS
HIGH BYTE
BYTE TRANSFERS
""OUTPUT LONE
TO USERS
DEVICE
Figure 5
DRV11-B Timing: Single Cycle, Asynchronous, ProgramInitiated
289
DRV11-B
LnADWCR
'1
LOAD BAR
tNT ENABLE _ _ _ _ _- ' ,
X
~~,",_ _ _---'
IDETERMINES
"CDC'
CYCLE TYPE I _
X
' -_ _ _- '
X
"-_ _ _ __'
"-_ _ __
>C
\'--_ _--J/
·we INC ENABLE
SA INC ENABLE
·SINGlE CYCLE
"CYCLE REO
'.iUsY
·OATA FROM USER
DEVICE TO DRV11 8
!IF DATD(BI!
"INPUT LINE FROM
NOH T
TH,SPULSfWIOHtP{RIOOt$EOUAL 10
THE TIME B(TWffNCUNS£CUlIVE ASMR
rOUSERS
DEVICE
"NPUT UATA
MUST BE STAIlLE
TIOfl.,SOF HSVNCOtl.l THE l!lot 118U5
WHILl THIS IS UtPt,I\lUfr.tT ON MlMUR'I'
REPLY TIMES THE NOMINAL VAlUf IS
THE WIDTH OF THISF'ULSf ISDUfRMINED
HY THE WIDTH OF eRPl Y ON THE lSI 11
dUS WHilE THIS IS DEPENDENT ON THE
MEMORy REPL Y TIME. IT IS NOMINALLY
2OOI\JS
",S
Figure 6
DRV11-B Timing: Burst Mode, User-Initiated
290
DRV11·B
LOADWCR
lOAD BAA
\J
___--'I
x
"mc,
~.&r------~
IDETERMINES
CYCLE TYPEI ~_.L.l.~:"':",",",,",,-,",,-,",,-~
X
~. _ _ _ _ _- J
8A INC ENABLE
\
"SINGLE CYCLE
)
(
·we INC ENABLE
""BuSY
X
/
>C
{
!
CAUSED BY SETTING
CYCLE REOUEST
BIT
"DATA FROM USER
DEVICE TO DRVl 1·8
IIF DATDIBIi
~.L.l.~:...£...<:"':"~,",,-CJ
I
"OATA FROM QRVll·B
TO USER DEVICE
IIF DATI DR DATIOI
~260
I
I
I
I
I
)Ft:~-+""260=---"')R=260
NS
"--_M",,,IN:....-_.J
NS
MIN
H
NS
MIN
I
HIGH BYTE
WORD TRANSFERS
"INPUT LINE FROM
USER DeVICE
""OUTPUT LINE
TO USERS
DEVICE
···INPUTDATA
MUST BE STABLE
Figure 7
NOTE,
THIS PULSE WIDTH PERIOD IS EQUAL TO
THE TIME BETWEEN CONSECUTIVE ASSER
TIONSOF BSYNC ON THE LSJ·l1 Bus.
WHILE THIS IS DEPENDENT ON MEMORY
REPLY TIMES. THE NOMINAL VALue IS
2pS.
BYTE TRANSFERS
NOTE 2
THE WIDTH OF THIS PULSE IS DETERMINED
BY THE WIDTH OF BRPLYON THE LSI·II
BUS. WHILE THIS IS DEPENDENT ON THE
MEMORY REPLY TIME. IT IS NOMINALLY
2tIONs.
DRV11-B Timing: Burst Mode, Program Initiated
291
DRV11-B
Miscellaneous Signals - Four sets of signals exist to perform handshaking and status exchange between the processor and the user's
device. They are:
STA TUS A, B, C-These three TTL lines are used to Input status to the
DRV11-B from the user's device.
FUNCT 1, 2, 3-These three TTL lines are used to output status from
the DRV11-B to the user's device.
INIT, INIT V2-INIT is asserted when the LSI-11 bus INIT signal Is
asserted. INIT V2 is asserted either when the LSI-11 bus INIT is asserted or when FUNCT 2 Is a 1.
A TTN-ATTN terminates a DMA transfer. This sets the READY bit and
causes an interrupt (if the interrupt enable bit has been set).
292
DRV11-B
CONFIGURATION
General
The interface consists of five registers (Table 1): word count register
(WCR). bus address register (BAR). control/status register (CSR).
input data buffer register (IDBR). and output data buffer register
(ODBR). The module also includes bus transceivers and logic for Interrupt requests. address control and protocol. and DMA requests.
Table 1
Standard Addresses
Description
Mnemonic
Read/
Write
Address
Register
Word Count
Bus Address
Control/Status
Input Data Buffer
Output Data Buffer
WCR
BAR
CSR
IDBR
ODBR
R/W
R/W
R/W
R
W
172410
172412
172414
172416
172416
Interrupt
Interrupt Vector
124
The DRV11-B contains two switch packs. one to assign an appropriate
device address to the DMA Interface and one to select an interrupt
vector.
The address of both the DRV11-B interface and the Interrupt vector is
selected by the position of the switches in switch pack 82 and 81.
respectively. The location of the switches on the module is shown in
Figure 1. The switches are set to the OFF position (open) to select a
zero bit and the ON position (closed) to select a one.
Device Address Format
The DRV11-B decodes four addresses. one for each of the registers
listed:
Register
Octal Address
WCR
BAR
CSR
DBR
1XXXXO
1XXXX2
1XXXX4
1XXXX6
293
DRV11-B
Jl
DEVICE ADDRESS
SELECTION SWITCHES
VECTOR ADDRESS
SELECTION SWITCHES
J2
.
-GI
-
-0
It - 4156
Figure 8
DRV11- 8 Connector and Switch Locations
Normally. the addresses assigned to the DMA start at 7724108 and
progress upward. Switches S2-1 through S2-10 select the base address as indicated by the X portion of the octal code; the individual
registers are decoded by the DMA interface. The relationship between
the address format and the switches is shown in Figure ,.2.
14
13
I 1,
1
15
1
12
11
10
09
08
07
06
05
04
I I I IoI I I I I I
1
o
1
1
0
0
0
0
03
02
01
00
1
X
Ix
x
I
I I I I I I I I I I
ON
SWITCH
\
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
ON
I I I I I I I I I I
.
1
2
3
OPEN ZERO = OFF
CLOSED = ONE = ON
0
4
5
6
7
8
9
10
SWITCH S2
Figure 9 Device Add ress Switch S2 Selection
Interrupt Vector Selection
The interrupt vectors for the LSI-11 systems are allocated from 0-7748.
The recommended vector assigned to the DRV11-8 is 1248 . Switches
S1-1 through S1-8 are used to select the vector. The relationship
between the switches and the vector format is shown in Figure 3.
294
DRV11-B
15
14
13
12
11
10
09
08
0
0
0
0
0
0
0
0
07
06
05
04
03
02
I I I I I I I I I l' I l' I l' I
SWITCH
0
00
0
I I I I I I
I I I I I I I I
I I
OPEN ~ ZERO = OFF
CLOSED = ONE = ON
0
01
OFF
OFF
OFF
1
2
3
ON
OFF
ON
OFF
ON
4
5
6
7
8
SWITCH SI
Figure 10
Interrupt Vector Switch S1 Selection
Registers
Each of the five registers can be addressed by the processor. The
IDBR and ODBR are assigned the same address and are read-only
and write-only, respe~tlvely.
Word Count Register (WCR) - The WCR (Figure 4) is a 16-bit
read/write counter which is loaded by the program with the 2's complement of the number of words or bytes to be transferred at one time
between memory and the 110 device. At the end of each transfer, the
WCR is incremented. When the count becomes zero (all 16 bits = 0),
the DMA generates an interrupt request. The contents of the WCR can
be monitored by the processor program.
ADDRESS
I
xxxxxo .
15
00
READIWRITE
~==~~~==~~====~~~~
16 81T COUNTER
Figure 11 Word Count Register
Bus Address Register (BAR) - The BAR (Figure 5) is a 16-bit
read/write register used to generate the bus address which specifies
the location to or from which data is to be transferred. The register is
incremented after each transfer. It will increment across 32K boundary
lines via the extended address bits in the controllstatus register. Bus
address bit 0 is driven by the user device.
Control and Status Register (CSR) - The CSR (Figure 6) contains 16
bits of information used to control the function and monitor the status
of the DMA transfers. The information in the CSR can be modified or
read by the processor program in either a-bit bytes or 16-bit words.
Table 2 lists and defines each of the 16 bits.
295
DRV11-B
ADDRESS
XXXXX2
I
15
14
12
11
0-7,
0-1,
..I
.
0-7,
0-7,
0-7,
Figure 12 Bus Address Register
ADDRESS
XXXXX4
I
15
14
~~~
13
__
12
~~
11
__
10
~~
9
__
~~
__
L-~~~~~
__
~~~
Figure 13 Control/Status Register
Table 2
DRV11-B Control/Status Register Bit Description
Bit: 15
Name: Error
Description: (Read-only)
Indicates a special condition
NEX (bit 14)
ATTN (bit 13)
Sets READY (bit 7) and causes interrupt if IE (bit 6) is set.
Cleared by removing the special condition.
NEX is cleared by writing to zero.
ATTN is cleared by the user device.
Bit: 14
Name: NEX
Description: (Read/Write zero)
Nonexistent memory indicates that as bus master, the DRV11-8 did
not recieve BRPL Y or that a DATIO cycle was not completed.
Sets error (bit 15).
Cleared by INIT or by writing to zero.
Bit: 13
Name: ATTN
Description: (Read-only)
Indicates the state of the ATTN user signal.
Sets error (bit 15).
Bit: 12
Name: MAl NT
Description: (Read/Write)
Maintenance bit used with diagnostic program.
296
DRV11-B
Bit: 11
Name: STAT A
Description: (Read-only)
Device status bit that indicates the state of the DSTAT A, B, and C,
user signals.
Set and cleared by user control only.
Bit: 10
Name: STAT B
Description: (Read-only)
Device status bit that indicates the state of the DST AT A, 8, and C user
si,gnals.
Set and cleared by user control only.
Bit: 9
Name: STAT C
Description: (Read-only)
Device status bit that indicates the state of the DSTAT A, B, and C user
signals.
Set and cleared by user control only.
B~8
Name: CYCl
Description: (Read/Write)
Cycle is used to prime a DMA bus cycle.
Bit: 7
Name: READY
Description: (Read-only)
Indicates that the DRV11-B is able to accept a new command. Requests an interrupt if IE (bit 6) is set.
Set by INIT.
Bit: 6
Name: IE
Description: (Read/Write)
Enables interrupts to occur when,READY (bit 7) is set.
Cleared by INIT.
Bit: 5
Name: XAD 17
Description: (Read/Write)
Extended access b~t 17; cleared by INIT.
Bit: 4
Name: XAD 16
Description: (Read/Write)
Extended address bit 16; cleared by INIT.
B~3
Name: FNCT3
Description: (Read/Write)
One of three bits made available to the user device. User defined.
Cleared by INIT.
297
DRV11·B
Bit: 2
Name: FNCT 2
Description: (Read/Write)
One of three bits made available to the user device. User defined.
Cleared by INIT.
Bit: 1
Name: FNCT 1
Description: (Read/Write)
One of three bits made available to the user device. User defined.
Cleared by INIT.
Bit: 0
Name: GO
Description: (Write-only)
Causes "NOT READY" to be sent to the user device indicating a command has been issued. Clears READY (bit 7). Enables DMA transfers.
Input Data Buffer Register (lDBR) - The IDBR (Figure 7) is used for
read-only operations. Data is loaded into the register by the user's
device. The data may be read from the IDBR as a 16-bit word, an 8-bit
high byte or an 8-bit low byte. Transfers are usually via DATa or
DATOB DMA bus cycles. The register input connects to J2 mounted
.
on the module.
I
15
ADDRESS
XXXXX6
8 BIT LOW 8YTE
8 BIT HIGH BYTE
~~~--~~~~,--~~--~~--~~~--~~--~~
,
16 BIT DEVICE INPUT DATA WORD
Figure 14 Input Data Buffer Register
Output Data Buffer Register (ODBR) - The ODBR (Figure 8) is used
during write-only operations. Data from the LSI-11 bus is loaded into
the register under program control and read from the register by the
user's device. The register can be loaded with a 16-bit data word or
with an 8-bit high byte or an 8-blt low byte. Transfers are usually via
DATI or DATIO DMA bus cycles. The output of the register connects to
J1 on the module.
I
15
ADDRESS
XXXXX6
8 81T HIGH 8YTE
8 81T LOW BYTE
~~~--~~--~~--~~--~~~--~~--~~~
16 BIT DATA WORD
Figure 15
Output Data Buffer
298
DRV11-B
PROGRAMMING
General
The DRV11-B interface operates as both a slave and a master device.
Prior to becoming bus master, all data transfers out (DATa) or data
transfers in (DATI) are in respect to the processor. Once the DRV11-B
is granted bus mastership by the processor, all data transfers are in
respect to the DRV11-B.
DMA operation is initialized under program control by loading the
WCR with the 2's complement of the number of words to be transferred, loading the BAR with the first address to or from which data is
to be transferred, or loading the eSR with the desired function bits.
After the interface is initialized, data transfers ae under control of the
DMAlogic.
Program Control Transfers
Data transfers may be performed under program control byaddressing the IDBR or ODBR and reading or writing data.
DMA Control Transfers
DMA Input (DATI) or output (DATa) data transfers occur when the
processor clears READY. For a DATa cycle (DRV11-B to memory
transfer), the user's I/O device presets the control bits [word count
increment enable (We INC ENB), bus address Increment enable (BA
INC ENB), C1, CO, AOO, and ATTN], and asserts CYCLE REQUEST to
gain use of the LSI-11 bus. When CYCLE REQUEST is asserted, input
data is latched into the input DBR, the control bits are latched into the
DRV11-B DMA control and BUS goes low. A DATI cycle-memory to
DRV11-B transfer-is handled In a similar manner, except that the
output data is latched into the output DBR at the end of the bus cycle.
When the DRV11-B becomes bus master, a DATa or DATI cycle is
performed directly to or from the memory location specified by the
BAR. At the end of each cycle, the WCR and BAR are Incremented and
BUSY goes high while READY remains low. A second DATa or DATI
cycle Is 'performed when the user's I/O device again asserts CYCLE
REQUEST. DMA transfers will continue until the WCR increments to
zero, at which time READY goes high and the DRV11-B generates an
interrupt (if interrupt enable is set) to the processor.
If burst mode is selected (SINGLE CYCLE low), only one CYCLE
REQUEST Is required for the complete transfer of the specified number of data words.
Device Cables and Signals
Data, status, and control signals are transferred between the user's
299
I/O device and DMA by an input and an output cable assembly. The
input cable attaches to connector J2 and the output cable attaches to
connector J1. Tables 3 and 4 list the connector pin and designations
for each signal. Table S lists several recommended cable assemblies
that are available from DIGITAL in the lengths indicated. The H8S6
female con nector mates with either J 1 or J2 on the DRVll-B. To order
cable assemblies in lengths not listed, contact a DIGITAL sales office.
Cables up to lS.2 m (SO ft) maximum may be used.
Table 3
J2*
Connector Pin
B
D
F
J
~}
N
R
T
V
DD
FF
JJ
LL
NN
RR
TT
VV
CC
EE
HH
KK
MM
pp
55
UU
DRV11-B Input Connector Signals
Signal Name
Unit Loads
BU5YH
ATTNH
AOOH
BAINCENBH
10 (drive)
1
FNCT3H
COH
FNCT2H
C1H
FNCT 1 H
081NH
091NH
10lN H
lllN H
121N H
131N H
141N H
lSIN H
071NH
061NH
OSINH
041NH
031NH
021NH
OliN H
OOINH
10 (drive)
1
10 (drive)
1
10 (drive)
1
1
1
• All remaining pins connect in common to logic ground by board etch.
300
DRV11-B
Table 4
J1*
Connector Pin
B
0
F
J
K
L
N
R
~}
DO
FF
JJ
LL
NN
RR
TT
VV
CC
EE
HH
KK
MM
pp
SS
UU
DRV11·B Output Connector Signals
Signal Name
CYCLE REQUEST H
INITV2H
READYH
WCINCENBH
SINGLE CYCLE H
STATUS A
INITH
STATUS B
STATUSC
OBOUT H
090UTH
100UTH
11 OUT H
120UTH
130UTH
140UTH
150UTH
070UTH
060UTH
050UTH
040UTH
030UTH
020UTH
01 OUT H
OOOUTH
Unit Loads
1
10 (drive)
10 (drive)
1
1
1
10 (drive)
1
1
10 (drive)
* All remaining pins connect in common to the logic ground by board etch.
301
DRV11-B
Table 5
Recommended Cable Assemblies
Cable No. Connectors
Type
BC07D-XX HB56 to open end
10,15,15
2,20 conductor
ribbon
BCOBR-XX HB56 to HB56
Shielded flat
BC04Z-XX HB56 to open end
6,10,15,25,50
Table 6
Standard Lengths (ft)
1,6,10,12,20,25,50
Shielded flat
DRV11-B Interface Connector Signals
Mnemonic
Description
00 OUT -15 OUT
16 TTL data output lines from the DRV11-B.
One = high
OOIN -151N
16 TTL data input lines from the user's device. One = high
STATUS A, B, C
Three TTL status input lines from the user's
device. The function of these lines is deti ned by the user.
FUNCT 1,2,3
Three TTL output lines to the user's device.
The function of these lines is defined by the
user.
INIT
One TTL output line; used to initialized the
user's device.
INITV2
One TTL output line; present when INIT is
asserted or when FUNCT 2 is written to a
one. Used for interprocessor buffer applications.
AOO
One TTL input line from the user's device.
This line is normally high for word transfers.
During byte transfers this line controls address bit 00.
302
DRV11·B
Table 6
DRV11-B Interface Connector Signals
Mnemonic
Description
BUSY
One TTL output line to the user's device.
BUSY Is low when the DRV11-B DMA
control logic is requesting control of the
LSI-11 bus or when a DMA cycle Is in progress. A low-to-high transition indicates end
of cycle.
READY
One TTL output line to the user's device.
When the READY line goes low, DMA transfers may be initiated by the user's device.
CO,C1
Two TTL input lines from the user's device.
These lines control the LSI-11 bus cycle for
DMA transfers. CO, C1 codes for the four (4)
possible bus cycles as listed below:
Bus Cycle
DATI
DATIO
DATO
DATOB
SINGLE CYCLE
CO
0
1
0
1
C1
0
0
1
1
One TTL input line from the user's device.
This line is internally pulled high for normal
DMA transfers. For burst mode operation,
SINGLE CYCLE is driven low by the user's
device.
CAUTION: When SINGLE CYCLE is driven
low, total system operation is affected because the LSI-11 bus becomes dedicated to
the DMA device and other devices cannot
use the bus.
WCINCENB
One TTL input line from the user's device.
This line is normally high to enable incrementing the DRV11-B word counter. Low
inhibits incrementing.
BAINCENB
One TTL input line from the user's device.
This line is normally high to enable incrementing the bus address counter. Low inhibits incrementing.
303
DRV11-B
Table 6
DRV11-B Interface Connector Signals (Cont)
Mnemonic
Description
CYCLE REQUEST
One TTL Input line from the user's device. A
low-to-hlgh transition of this line initiates a
DMA request.
ATTN
One TTL input line from the user's device.
This line Is driven high to terminate DMA
transfers, to set READY, and to request an
interrupt If the interrupt enable bit is set.
As bus master, the DRV11-B performs a DATO or DATOB bus cycle by
placing the memory address on BDAL lines, asserting BWTBT, and
then asserting BSYNC. The memory decodes the address, then the
DRV11-B removes the address from the BDAL lines, negates BWTBT
(BWTBT will remain active for a DATOB), places the user's input data
on the BDAL lines and asserts BDOUT. Memory receives the data and
asserts BRPLY. In response to BRPLY, the DRV11-B negates BDOUT
and then removes the user's input data from the BDAL lines. Memory
now negates BRPL Y, the bus cycle is terminated, and the bus released
when the DRV11-B negates BSACK and BSYNC.
At the end of the first transfer, the DRV11-B WCR and BAR are incremented, BUSY goes high, and READY remains low. With BUSY high
and READY low, the user's I/O device can initiate another DATO or
DATOB cycle by again asserting CYCLE REQUEST.1f the interrupt
enable is set, DMA transfers can continue until the WCR increments to
zero and generates an Interrupt request.When the WCR increments to
zero, READY goes high, and the DRV11-B generates an interrupt request (if the interrupt circuits are enabled). The processor responds to
the interrupt request (BIRQ) by asserting BDIN followed by BIAKI
(interrupt acknowledge). BIAKI is received by the DRV11-B and in
response places a vector address on the BDAL lines, asserts BRPLY,
and negates BIRQ. The processor receives the vector address and
negates BOIN and BIAKI. The ORV11-B now negates BRPL Y, while the
processor exits from the main program and enters a service program
for the DRV11-B via the vector address.
Interrupt requests from the ORV11-B occur for the following condi ..
tions:
1. When the WCR increments to zero-this is a normal interrupt at
the end of a designated number of transfers.
304
DRV11·B
2.
3.
When the user's 1/0 device asserts ATTN-this is a special condition interrupt which may be defined by the user to override the
WCR.
When a nonexistent memory location is addressed by the DRV118-this special condition Interrupt is produced when no 8RPLY is
received from the memory.
System Memory to User's Device Transfers (DATIO or DATI)
DMA transfers from the memory to the user's 110 device occur in a
manner similar to that described for user's 1/0 device to memory
transfers. Figure 11 illustrates the data flow for a DMA DATIO or DATI
cycle. Under program control, the DRV11-8 WCR (Figure 9) is loaded
with a count equal to the number of transfers, while the BAR is loaded
with the starting address from which the first word will come; the CSR
Is set for transfers.
With the CSR set, READY goes low and the user's 1/0 device conditions the CO, C1 lines (Table 6) for a DATI or a DATIO, conditions the
WC INC EN8, BA INC EN8, ATTN, SINGLE CYCLE (high for normal
DMA transfers) signals, and asserts CYCLE REQUEST.
305
DRV11-J
HIGH DENSITY PARALLEL INTERFACE
GENERAL
Sixty-four Input/output data lines are now available on a doubleheight module for the LSI-11/2, LSI-11/23, PDP-11/03, and PDP11/23. The DRVll-J also Includes an advanced Interrupt structure
with bit interruptabillty up to 16 lines, programmable interrupt vectors,
and program selection of fixed or rotating Interrupt priority within the
DRVll-J.
The DRVll-J's bit Interrupts for real-time response make It especially
useful for sensor I/O applications. It can also be used as a generalpurpose interface to custom devices, and two DRV11-Js can be connected back-to-back as a link between two LSI-ll buses.
FEATURES
• 64 tri-state bidirectional input/output lines organized as four 16-blt
ports, A through D.
• Data line direction selectable under program control for each 16-blt
port.
• Transitions on each of the 16 lines of Port A can generate unique
interrupt vectors (bit Interrupts). This means high-priority Inputs get
serviced by the CPU much faster.
• Transitions on the USER RPL Y lines of each port can generate
unique interrupt vectors (I/O Interrupts). This means less processor
overhead. By selecting this feature, bit Interrupts are reduced to 12.
• Double-height module: 22.Bcm X 13.2cm (B.9In. X 5.2 In.)
• Drive up to 25 feet of shielded cable, 6 feet of unshielded flat or
round cable.
• Four external control lines per port: USER ROY, USER RPL Y,
DRVll-J ROY, and DRVll-J RPL Y.
• Interrupt vectors (fixed or rotating priority) are set under program
control. This eliminates the need for jumper-defined vectors.
• Latched outputs, PNP-Schmltt-trlgger inputs.
SPECIFICATIONS
MB049
Identification
Power
+5V±5% 1.6A typical, 1.BA maximum
Bus Loading:
2 ac loads, 1 dc load
306
DRV11·J
Data Buffer Trl-State Outputs:
V OL = 0.5V @ I OL = 8 rnA
V OL = 0.4V @ I OL = 4 rnA
V OH = 2.4 V @ I OH = - 2.6 rnA
Data Buffer Inputs:
IlL = -0.2 rnA @ V IL = 0.4V
I IH = 20 #lA @ V IH = 2.7V
Protocol Signal Trl-State Outputs:
V OL = 0.55V @ I OL = 64 rnA
V OH = 2.4V @ I OH = -15 rnA
Protocol Signal Inputs:
Termination: 120 ohms
IlL = -2.7 mA@ V IL = .5V
I IH = 80 #lA @ V IH = 2.7V
Environmental:
Storage temperature: -40°C to +60°C
Operating temperature: +5°C to +60°C
Adequate airflow must limit the inlet to outlet temperature rise to 10°C
(5°C if inlet air is 55°C).
NOTE
Derate maximum operating temperature by 1.BoC
for each 1000 meters of altitude above sea level.
Humidity: 10% to 90%, non-condensing
Size
Double-height module:
13.2cm (5.2in.) wide
22.Bcm (B.9in.) long
Cabling:
BC05W-xx-Shielded cable with 50-pin connectors at both ends.
Available in 3.0 and 7.5 meter (10 and 25 foot) lengths.
DESCRIPTION
Detailed information about the DRV11-J is supplied with the module.
307
DRV11-J
PROGRAMMING
The DRV11-J is programmed through eight contiguous directly addressable registers, which may be positioned to start from 7600008
through 777760 8 in address space by stake pin jumpers. There are
four Control Status Registers and four Data Buffers.
The Registers are:
Control Status Register A
Data Buffer Register A
Control Status Register B
Data Buffer Register B
Control Status Register C
Data Buffer Register C
Control Status Register D
Data Buffer Register D
(CSRA)
(DBRA)
(CSRB)
(DBRB)
(CSRC)
(DBRC)
(CSRD)
(DBRD)
7XXXXOa
7XXXX28
7XXXX4 8
7XXXX68
7XXX108
7XXX12 8
7XXX14 8
7XXX16 8
XXXX is jumper-selectable between 6000 8 to 7776 8 in a modulus of
16 and factory-setto 6416 8 (CSRA = 7641608).
The format of these registers is shown in Figure 1.
Unlike other LSI-11 interface modules, the DRV11-J uses two sets of
eight internal registers to control interrupts. The first set of registers Is
controlled through CSRA and CSRB and Is responsible for interrupts
generated in bits 0-7 of Port A. The second set of registers Is controlled through CSRC and CSRD and is responsible for either bits 8-15
of Port A or, when 110 interrupts are selected, the four USER RPLY
lines and bits 8-11 of Port A (see Figure 1).
IRR
ISR
IMR
ACR
Interrupt Request Register
Interrupt Service Register
Interrupt Mask Register
Auto Clear Register
Status Register
Mode Register
Com mand Register
Byte Count
Vector Address Memory
Interrupt vectors are stored in Vector Address Memory. Vector addresses can be set from 0 to 17748 and must be loaded on power-up.
To provide for dynamic changing of interrupt subroutines, vectors are
programmable. Four vectors are available for each of the sixteen Interrupts.
308
DRV11-J
v
read as zeros
DIRECTION
PORTA
(READ/WRITE)
CSRB
Locallon = device address + 4
IS
14
13
12
11
10
INTERRUPT CONTROL
STATUS/COMMAND· B LINES
(READ/WRITE)
• Nol reset by blnll
• Reset
• Manipulate Internal registers
• Interrupt Request Register
• Interrupt Mask Reglsler
· I nterrupt Service Register
• Mode Regisler
• Read Status Register
• Preselect Internal memory lor
reading/wriling through CSRB
• Vector Address Memory
• Interrupt Request Register
·tnterrupt Mask Register
• Interrupt Service Register
• Auto Clear Register
o
9
UJER'------.,y
READY
(R:AD
ONLY)
I
12
11
INTERRUPT CONTROL DATA
(READ/WRITE)
DtRECTION
PORTB
(READIWRITE)
read as zeros
CSRC
Localion = device address + B
IS
14
13
]
y
NOT USED
• As preselected in CSRA
10
t,-o_:_o_:_0..,.'_0_o_:_o. . .J I l~___--.~__~)
NOT ~SED
USER
READY
DIRECTIONPORT C
(READ/WRITE)
read as zeros
(R~AD
INTERRUp1cONTROL
STATUS/COMMAND· Bllnes
(READ/WRITE)
• SameasCSRA
ONLY)
CSRD
Location =devlce address + 12
IS
14
13
12
11
0
~
I \~________,yr-______~J I
RUES:~y
o
NOT USED
~----------~
DIRECTIONPORT 0
read as zeros
__----------~
INTERRUPT CONTROL DATA· Bllnes
(READ/WRITE)
(READ
ONLY)
• As preselected In CSRC
DBRA. DBRB. DBRC. DBRD
Locallon = device address =+2. +6 . .-10. +14respecllvely
IS
14
13
12
11
10
9
,
\
y
INPUT DATA (when READ)
OUTPUT DATA (when WRITE)
Figure 1
Register Format
309
DRV11-P
DRV11-P LSI-11 BUS FOUNDATION MODULE
GENERAL
The DRV11-P Is an LSI-11 bus-compatible foundation wire-wrap Interface module. Approximately one-quarter of the module Is occupied by
bus transceivers, Interrupt vector generator logic, and a 40-pin I/O
connector. The remaining three-quarters of the module Is for user
application and has plated-through holes to accept ICs and wire-wrap
pins (WP) for interconnecting the user's circuits. The plated-through
holes can accept 6-,8-, 14-, 16-, 18-,20-,22-,24-, and 40-pln dual-inline ICs or Ie sockets in various mounting areas of the module, or
discrete components can be Inserted Into the plated-though holes.
The DRV11-P can be Inserted into anyone of the available interface
option locations of any LSI-11 bus.
FEATURES
• An easy-to-use foundation module for custom interface applications.
• Factory-Installed LSI-11 bus-compatible Interface circuits.
• Device and interrupt vector that can be configured by the user.
• Compact-occupies only two device locations on the bus.
• Can accommQdate up to 50 integrated circuits making up the user's
device logic.
• Wire-wrap pins are provided for all signals.
• All user control signal lines are TTL-compatible.
SPECIFICATIONS
M7948
Identification
Size
Quad
Power
5.0 Vdc ±5% at 1.0 A
Bus Loads
AC
DC
2.1
1 (plus user's logic)
DESCRIPTION
General
The DRV11-P contains 16 bus transceivers, device selection and interrupt vector generation logic, Interrupt control, and control and status
register functions. The device data Inputs and outputs of the bus
310
DRV11·P
transceivers and the device control signals are made available to the
user to complement control of up to four 16-blt registers.
Address Selection Logic
The address selection logic consists of a device address comparator
and the protocol control logic. Up to four discrete addresses are made
available with the existing logic on the ORV11-P and can be assigned
to data registers, status and control registers, or word counters. By
adding additional ICs, the user can increase the total number of addresses available. The main address of the ORV11-P is selected by
monitoring the BBS7 bus line and decoding address Information 003012 from the bus. The main device address is assigned by the configuration of 'jumper leads (A03-A08) attached to wire-wrap pins. When
the selected and Input bus addresses are the same, the device address comparator provides an ENB H level to the protocol control
logic. The proto"col control 'logic receives bus signals and address bits
001 and 002 to assert one of the four available output lines: SEL OEV
OL, SEL OEV 2L, SEL OEV 4L, and SEL OEV SL. In addition, the protocol control logic provides output signals to specify word or byte
transfers.
Table 1 lists and defines the function of the control signals required or
available for the user logic.
Table 1
DRV11-P Protocol Control Logic Signals
Signal
Function
SELOEVOL
SEL OEV 2 L
SELOEV4L
SELOEV6L
Select device 0 through 4. One of four lines asserted
by decoding the device address and available to select one of four user word registers.
OUT LB L
OUTHB L
Out low byte, out high byte. Used to load (write) data
Into low byte (8 bits) or high byte (8 bits) or both
bytes (16 bits) of the selected word register.
INWOL
In word. Used to gate (read) data from the selected
word register to the bus.
The format for the device address selection Is shown In Figure 2. A
logical 1 is specified when no Jumper lead Is Installed between the
appropriate wire-wrap pin from A3-A 12. A logical 0 is specified when a
jumper lead is Installed.
311
DRV11-P
Interrupt Control Logic
The interrupt control provides the circuits necessary to allow a program Interrupt transaction between the bus and device. Two interrupt
channels (A and B) are available to the user, with channel A assigned
to the highest priority. Table 2 lists and defines the user-available
signals associated with the interrupt controlloglc.
Table 2
DRV11-P Interrupt Control Logic Signals
Signal
Function
RQSTAH
Interrupt Request A. Asserted by device logic and
sets the channel A Interrupt request flip-flop when
the channel A interrupt enable flip-flop Is set.
ENB DATA A
H
Interrupt Enable A Data. Asserted by ~evlce logic
and sets the channel A Interrupt enable flip-flop
when the ENB CLK A signal is asserted.
ENBCLKA
Interrupt Enable A Clock. Asserted by device logic to
cause the channel A Interrupt enable flip-flop to be
set when ENB DATA A signal is asserted.
ENBASTH
Interrupt Enable A Status. Indicates the status of the
channel A interrupt enable flip-flop.
RQSTBH
Interrupt Request B. Same as RQST A H signal except controls channel B Interrupts.
ENB DATA B
Interrupt Enable B Data. Same as ENB DATA A H
signal except controls channel B Interrupts.
H
ENBCLKB
Interrupt Enable B Clock. Same as ENB eLK A signal
except controls channel B Interrupts.
ENBBSTH
Interrupt Enable B Status. Same as ENB A ST H
except controls channel B Interrupts.
VECTORH
Interrupt Vector Gate. Used by device logic to gate
vector address onto the bus and to generate BRPL Y
signal.
VECRQSTH
Vector Request. Asserted by device logic to specify
that channel A vector address Is required; negated
to specify channel B vector address Is required.
INITOL
Initialize Out. Buffered BINIT L signal from bus used
for general Initialization.
312
DRV11-P
Device Address Comparator
The device address comparator (Figure 1, sheet 1) receives address
bits D03 H-D12 H from the bus transceivers and compares these bits
to the device address assignment bits (A03-A 12) wired by the user on
the DRV11-P module. If the two addresses compare, an ENS H signal
Is applied to the protocol logic. The device address comparator logic
Is designed around two type 8136 ICs. The user's device address Is
selected by means of wire-wrap pins. Wire-wrapping a device address
pin to a ground pin makes that device address bit a zero. Device
address bits which are to be ones are left unwrapped. These bits will
be pulled up to +5V (one state) via resistors on the module.
313
INPUT
DATAIADDRES~S
LINES
OUTPUT DATA/AODRESS LINES
16 BUS DATA/ADDRESS LINES (BDAL filL - "L)
WP77
(BBS7 H)
INDO H
IN 01 H
IN 02 H
IN 03 H
IN D4 H
IN 05 H
;!;N Q!i H
IN 07 !!
IN Q8 !!
IN 09!!
IN 10 H
IN It H
IN 12 !!
IN 13 !!
DWP60
WP96
WP80
WP57
DWP99
WPlt9
WP98
WPltB
DWPlt3
WP92
WPS9
wPloa
WP86
WP82
J:J~~_--D WPI02
t5_"'~ . ,., WPIOI
:I:
~:~
0
a
g%1
....
~WPI06
~WP61
gl ('tf6i~)
~
:8 ::il~
~WPI07
~WP88
WPIO
(DDI L)
%
~
o
~WPI4
~WPI7
~WP79
~Wpa7
N
WP31
(ENBH)
o
o
o
o
o
o
o
o
o
o
~:y ~
:8 :~~~9
~wpa5
~WP84
~WP83
.!l..!.U!.....- WP81
BWTBT
BDOUT
BDIN
BSYNC
TRANS
TRANS
TRANS
TRANS
L
L
L
L
SEL
SEL
SEL
SEL
BRPLY L
ENB
ENB
ENB
ENB
DEY
DEY
DEY
DEY
B L
AL
CL
QL
0 L
2 L
4 L
6 L
IN WD L
OUT HB L
O~UT LB L_
WPI2
(RXCX)
Figure 1
DRV11-P Block Diagram (Sheet 1 of 2)
0
0
0
0
WPIOO
WPI20
WP94
WP95
'0 WP3!1
'0 WP34
'0 WP33
-0 WP32
-0 WPI6
.0 WP36
-""' WP37
C
:II
<
•
"1J
~
~
o
B"
MUX
LINES
a
}
...
"~~Tnn
B VECTOR ADDRESS liNES (BDAl OOL - 071
"
"
WP38
(BIRO II
WP25
(BIAKO l I
;:J
;:J
WP97
(VEC ENS HI
U
"A"
MUX
LINES
W4
}
W¥9
BINIT L
VECTOR H
BIRO l
BIAKO L
~
TO
SPARE ENS 11)
SHEET 'SPMIE_ENB_'
S::~:'
.1
IN L
ENR CLK
ROST
ENR DATA
ENB ClK
'ENR pATA
...I.
01
•
INIT
11) L
WP9
(IAKI LI
BUKI L
WP39
(BOMGO LI
1
WPIB
IINIT 11) LI
WP5B
... WP59
INVERTER
A
A
A
B
S
H
H
H
H
H
a
2J
<
.....
.....
DWP6
0 WP22
0 WP24
WP26
0 WP27
0
.!!9.!I...!...! WP2B
•
"a
ENS SST H 'DWPB
VEC ROST B H .0 WP21
ENB A ST H .0 WP41
WPI9
(INIT 0 HI
Ir-LSI-i'i'" BUs SLOTSca 0 - - - - - - - - ,
BDMGO l l ,
I""'"
I .... BOMGO L
BUKO L
CS2
.,
CN2
:>
I :>
I =
W3
=
WI
3 BIAKI L
I 3 BOMGI L
IL_______________
CR2
'CM2
(I)
W2
ROMGI L
0
INTERRUPT
lOGIC
(,.)
I
WP3~
WP73
WP75
WP76
WP74
ID
·1 RE~~ISJ
WP40
(BDMGI HI
---0
ID
I-..
-v
Figure 1
DRV11-P Block Diagram (Sheet 2 of 2)
I
I
I
II
J
+3V
+3V
SOURCE
+3V
DRV11·P
Bus Transceivers
Referring to Figure 1, sheet 1, data output lines 000 through 015
reflect the state of the bus DBAL lines and will contain address and
data information for any bus transfer, regardless of the device Involved. Output data are usually clocked Into a register for use by the
interface or a peripheral since the length of time that the data are
available on the bus during the bus cycle is very short. The device
address comparator and the protocol logic determine If the data currently on the 000-015 lines are Intended for the DRV11-P.
Input data present at the INOO-IN15 lines will be applied to the bus
when the TRANS ENB A, B, C, and 0 lines are asserted low. These
lines are asserted by the protocol logic to gate data onto the bus at the
proper time during a bus cycle when the data are addressed by the
processor. The SEL DEV and IN WD lines would be driven by the
protocol logic to select a user's register. The bus transceivers consist
of four type 8641 ICs.
Protocol Logic
The protocol logic (Figure 1, sheet 1) functions as a register selector,
providing the signals necessary to control data flow Into and out of up
to four user registers (eight bytes). Designed around a special
DIGITAL IC (DC004), the protocol logic operates as follows: when the
proper device address has been decoded by the device address comparator, ENB H goes high, and Is applied to a latch In the protocol
logic. Address bits 001 Hand 002 H are decoded by the protocol
logic, producing one of the SEL DEV outputs, while bit 000 Hand
BWTBT are decoded for output word/byte selection (OUT HB L, OUT
LB L). The device select lines (SEL DEV OL, 2L, 4L, 6L) and word/byte
select lines (IN WD L, OUT HB L, OUT LB L) are for user application
and are available at wire-wrap pins (WP). Table 3 lists and defines the
wire-wrap pins associated with the protocol logic. Generally, each
OEV SEL output is used to select one of four user's registers, and the
word/byte lines are used to determine the type of transfer (word or
byte) to or from these registers. The active state of the user's lines
from the protocol logic is a low assertion and the lines are TTL-compatible. The OEV SEL lines can sink up to 20 mAo Split lugs are provided on the DRV11-P to accommodate C37. This capacitor may be installed by the user to vary the delay between BOIN L, BOOUT L, and
VECTOR H inputs and the BRPL Y output.
The BRPL Y L signal is normally I~sued within 85 ns (max.) of receiving
either BDIN Lor BDOUT L, depending on the bus cycle. If the user's
interface requires more time before ending the bus cycle, the BRPLY L
316
DRV11-P
signal can be delayed up to a maximum of 10 J.l.S by adding capacitor
C37 across the split lugs in the BRPlY delay circuit.
The BRPlY l signal is also Issued as the result of a signal on the
VECTOR H input. This is used when transmitting the vector during an
interrupt sequence.
Interrupt Logic
The interrupt logic (Figure 1, sheet 2) performs an interrupt transaction that uses the daisy-chain type arbitration scheme to assign
priorities to peripheral devices. The DRV11-P Interrupt logic has two
channels (A and B) for generating two Interrupt requests. Channel A
has higher priority than channel B. If a user's device wants control of
the lSI-11 bus, the Interrupt enable flip-flop within the Interrupt logic
must first be set. This is accomplished by asserting (logical 1) the ENB
DATA line and then clocking the enable flip-flop by asserting (positive
transition) the ENB ClK line. With the interrupt enable flip-flop set, the
user's device may then make a bus request by asserting (logical 1)
RQST. When RQST Is asserted, and If the Interrupt enable flip-flop is
set, the interrupt logic asserts (logical 0) BIRQ l, thus making a bus
request. When the' request Is granted, the processor asserts (logical 0)
BDIN l (Figure 1, sheet 1), which is applied to the interrupt logic as IN
l (Figure 1, sheet 2). IN l causes the interrupt logic to assert (logical 1)
VECTOR H, which is applied to the vector generator. A vector is thus
placed on the lSI-11 bus to Indicate the starting address of the service
routine for the user's device which made the bus request.
As mentioned previously, two interrupt request channels (A and B) are
contained within the interrupt logic. These channels can be used to
service two user devices. However, because channel A has a higher
priority than channel B, fast peripheral devices which cannot recover
data if not serviced promptly should use channel A.
There are three status lines from the DRV11-P interrupt logic available
to the user. These are: ENB B ST H, ENB A ST H, and VEC RQST B H.
ENB B ST Hand ENB A ST H indicate the status of the interrupt logic
interrupt enable flip-flops. Each line is asserted (logical 1) when the
appropriate enable flip-flop is set. The VEC RQST B line is asserted
(logical 1) when the user's device connected to channel B has been
granted use of the bus. When VEC RQST B Is unasserted (logical 0),
the user's device connected to channel A of the interrupt logic has
been granted use of the bus. These status lines can function as part of
the user's control and status register (CSR), which can be constructed
on the DRV11-P module. Additionally, the INIT 0 and INIT 0 H outputs
from the interrupt logic can be used to initialize the user's logic.
317
DRV11-P
Interrupt Vector Generator
The interrupt vector generator (Figure 1, sheet 2) produces a vector
which pOints to a location in memory containing the address of a
service routine for the user's device-requesting interrupt service. The
interrupt vector is selected by the user by means of wire-wrap pins on
the DRV11-P. Vector bits V3 through V7 are hard-wired by the user for
either logical 1s or Os. Wire-wrapping an interrupt vector pin to a
ground pin makes that vector bit a O. Vector bits which are to be 1s are
left unwrapped. These bits will be pulled up to +5V ("one" state) via
resistors on the DRV11-P. When VECTOR H from the interrupt logic
goes high (logical 1), eight vector bits are gated onto the LSI-11 bus. It
should be noted that the user can generally select the state of only six
of the eight vector bits. The remaining bits, VOO and V01, are preset by
the DRV11-P vector generator. With this arrangement, the user can
select an interrupt vector in the normal user range of 0 to 3748 , However, by adding one gate to the interrupt vector generator encode
logic, the user can accommodate nine bits in the vector and thus
extend the interrupt to 774 8 ,
The interrupt vector generator is primarily designed around two type
74157 multiplexer ICs. Each 74157 has two separate 4-bit inputs which
are multiplexed. Thus, both 74157s can accommodate two 8-bit bytes,
one of which is used for vector generation. This leaves one spare 8-bit
input for user application. The spare input can be used to gate onto
the bus the lower byte of the user's eSR on the DRV11-P. The data on
the spare input can be gated to the LSI-11 bus by driving both SPARE
ENB 0 and SPARE ENB 1 inputs low (logical 0). This is best accomplished by using one of the SEL DEV lines from the protocol logic
(Figure 1, sheet 1) along with the IN WD line. The actual use of the
spare inputs is at the user's discretion, but SPARE ENB 0 and SPARE
ENB 1 should not be permanently held low as this could affect the
interrupt vector. If not used, these inputs should be connected to the
+3V source.
Interrupt Vector Selection
As manufactured, the DRV11-P can generate vectors in the range
from 0-374 8 , However, by adding one gate to the DRV11-P vector
generation logic, the user can extend the vector to 774 8 , The user
selects the interrupt vector by means of wire-wrap pins on the DRV11P module.
Figure 4 shows the vector select format and presents the wire-wrap
pin-to-bit relationship for vector selection. Bits to be decoded as zero
318
DRV11-P
bits in the interrupt vector are wire-wrapped to ground wire-wrap pins.
Bits to be decoded as one bits are left unwrapped, as these bits are
pulled up to the one state.
It is recommended that WPS (vector bit 2) be wrapped to WP21 (VEC
RQST B H). This will automatically decode the least significant bit of
the interrupt vector as a 0 or a 4. When the VECTOR H signal is issued
as a result of the B half of the interrupt logic becoming bus master, the
VEC RQST B H (WPS) signal is also issued, changing bit 2 of the
interrupt vector, thus presenting a different vector for interrupt B.
The VEC RQST B H line can be thought of as a one-bit code indicating
which half of the interrupt logic is bus master. When bit 2 of the interrupt vector is a zero, the A half is bus master; a one indicates that the B
half is master.
Bus Receivers
All lSI-11 bus data and control lines are fully buffered on the DRV11-P
module. Buffering for the data and address lines (BDAl) is accomplished by the bus transceivers. Bus control lines (BWTBT, BDOUT,
BDIN, BSYNC, BBSY, BIAKI, and BDMGI) are buffered on the DRV11P with type 8640 bus receivers. These receivers are high-impedance
receivers with the following input levels:
High = 1.7 V min.
low = 1.3 V max.
The receivers have standard TTL-compatible outputs which are made
available (for most bus signals) to the user by means of wire-wrap
pins.
+3V Source
There are two +3V wire-wrap pins on the DRV11-P module. These
pins provide a source of +3V for pulling up unused TTL inputs. Each
+3V source is capable of driving up to 13 TTL unit loads. The +3V
sources are derived from resistor dividers placed across the +SV logic
source.
Wire-Wrap Pins
There are 112 user I/O lines and 122 wire-wrap pins (not counting the
40 pins for the I/O connector and the 70 pins for C and D module
fingers) for user applications. The locations and functions of these
pins are described in detail in Table S.
319
DRV11-P
CONFIGURATION
General
The DRV11-P (Figure 2) is a versatile wire-wrap module that contains
interface logic for operation with the LSI-11 bus and provides adequate board area for mounting and connecting Integrated circuits
(ICs) or discrete components. Because the bus Interface logic is included, the module can be efficiently configured by the user to satisfy
a variety of device Interface logic applications.
A 40-pin connector mounted at the board edge connects to a device
cable assembly types available from DIGITAL.
t~roug~ several
Except for the bus Interface connections, all signals and voltages are
terminated to wire-wrap pins for user connections. The bus control
logic is provided with wire-wrap test points for monitoring the Internal
signals. The test pOints are spaced at 0.254 cm (0.1 In.) between pins
to let 40-pin .connectors, be inserted over the wire-wrap pins for automated test functions.
Approximately two-thirds of the surface area on the module consists
of plated-through holes, each connected to a wire-wrap pin. The user
can mount three different types of dual-In-line les or a variety of discrete components into the holes and connect the proper voltages and
signals by wire-wrapping leads on the board.
Device Address Selection
The DRV11-P will respond to up to four consecutive addresses In the
bank 7 area (addresses between 1600008 and 1777768 ). The register
addresses are sequential by even numbers and are as follows.
Register
1
2
3
4
BBS7
1
1
1
1
The user selects a base ending In zero
register by means of wire-wrap pins on
module decodes this base address and
dresses are then properly decoded by
received from the LSI-11 bus.
320
Octal Address
16XXXO
16XXX2
16XXX4
16XXX6
for assignment to the first
the DRV11-P module. The
the remaining register adthe DRV11-P as they are
..SVWllf-WWPlN
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LM
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REMOVE TO DlSABU
YfCTOI ADDUSSING
(SUTEXn
W
II ;-H--U--}H ~.. 8 ~ JL 8 B
~~to~~~~~;~o . \
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UNUSEJ)GAR
INPUTS, ETC •
CD
::
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+3VWlRE-W&A,PPIN
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USEiwtRE-WW
PINS (WI'I
NUMBtUDFIlQM
I tHROUGH 120
:to:'MD lEG. ......",ZIl.:::m1I
;;,..... ;:.;: i~;;;;4 ~i;~:m;:;: i~;~i.i
IlAl 100 kHz (noise
Noise
is super-imposed on ripple)
±0.05%
Interaction due to + 12V
+12V Output
Total Regulation
Line Regulation
Load Regulation
Stability
12V ±3%
±0.25%
±0.5%
0.1 %/1 000 hours
(See Thermal Drift Note 2)
0.025%/OC above 25°C
386
H780
Ripple
Dynamic Load Regulation
Noise
Interaction due to +5V
Overvoltage Protection
+SV
.
+12V
Adjustments
+SVOutput
+12V Output
Controls
Rear Panel
Front Console
(Master only)
Console Indicators
3S0 mVp-p (1%forf <3 kHz)
±0.8%
dl/dt = 0.5 A ~sec
f 100 kHz (noise
is super-imposed on ripple)
±0.02%
6.3V nominal
S.6SV min
6.8Vmax
1SVnominai
13.6Vmln
16.5V max
4.0SV-6.8V
Guarantee Range 4.SS-S.6SV
10.6V-16.5V
Guarantee range 11.7-13.6V
AC ON/OFF switch
DC ON/OFF switch
HALT/ENABLE switch
LC ON/OFF switch
DC ON
RUN (Master)
SPARE (Master only)
Backplane Signals
BPOKH
BDCOKH
BEVNT L
Transmitted
BHALTL
SHRUN L
Received (Master only)
Mechanical
Cooling
Two self-contained fans provide 0.7140 m3/min (30 ft3/mln) air flow.
387
H780
Size
13.97 cm w X 8.43 cm h X 37.15 cm I
(5-1/2 in w X 3-1/3 in h X 14-5/8 in I)
Weight
5.90 kg (13Ib)
Environmental
Temperature
Ambient
Storage
50 to 50 0 C (41 0 to 122 0 F)
-40 0 to +70 0 C (-40 0 to +158 0 F)
Humidity
90% maximum without condensation
NOTES
1. Operation from ac lines below 100V may cause the power supply
to overheat because of decreased air flow from the cooling fans.
2. These parameters apply after 5 minutes of warmup and are measured with an averaging meter at the processor backplane terminal block under system loading.
DESCRIPTION
General
Six H780 power supply options are available for use in LSI-11 bus
systems. Individual model numbers determine combinations of 115 or
230 Vac (nominal) primary power and selection of master console,
slave console, or no console. Models are listed below.
Model No.
Input Power
Console
Description
Figure
H780-C
H780-D
H780-H
H780-J
H780-K
H780-L
115V
230V
115V
230V
115V
230V
None
None
Master
Master
Slave
Slave
1
1
2
2
3
3
H780
The H780 master console contains RUN and DC ON indicators for
monitoring the processor states, as well as DC ON/DC OFF, LTC
ON/OFF, and ENABLE/HALT switches for contrOlling the processor.
The slave console contains only a DC ON indicator for monitoring the
status of the slave power supply.
388
H780
In addition to producing dc operating voltages (+5V, 18 A and +12V,
3.5 A) for system components, the H780 power supply automatically
sequences BPOK and BOCOK bus signals for proper powerup/power-down operation. The power supply can be used as a standalone unit or it can be used with a backplane. Built-in cooling fans
provide forced air cooling for the H780, and, when mounted to an
H9270 backplane, also provide cooling for the system modules
mounted in the backplane. High-frequency, low-voltage switching regulators and a multiplexing scheme provide control of overcurrent,
overvoltage, slow voltage buildup, low line voltage, and short-circuit
protection.
Figure 1
H780-C and -0 Power Supplies
Figure 2
H780-H and -J Power Supplies
389
H780
~/r
"
;/
',f/
Figure 3
H780-K and -L Power Supplies
Figure 4 is a block diagram of the H780 power supply. AC line voltage
is applied to the two cooling fans and to the power transformer. The
transformer has dual primary windings to meet U.S. and European
power requirements. A single secondary winding generates a
stepped-down ac voltage which is rectified and filtered to produce 26
Vdc (nominal) unregulated. The unregulated 26 Vdc is applied to two
3-terminal regulators which produce -15V and +5V for the H780 internal circuits. Unregulated 26 Vdc is also applied to +5V and + 12V
high-frequency, high-efficiency switching regulators. The outputs of
the +5V and + 12V switching regulators supply operating power to the
backplane. Each switching regulator circuit is designed for good frequency stability, high noise rejection levels, and. excellent load and
line regulation. An L-C output filter and a fast-recovery diode are used
in each switching regulator circuit. The +5V switching regulator operates at a frequency from 7 kHz to 12 kHz, while the +12V switching
regulator operates from 8 kHz to 14 kHz. Both switching regulator
circuits are protected, from overvoltage, overcurrent, and short-circuit
outputs. In addition, failsafe short-circuit startup is provided, along
with protection against a short between the +5V and + 12V outputs.
Logic signal generation circuits within the H780 provide for proper
power sequencing of the processor, as well as the generation of the
line-time clock (BEVNT L) and power supply status signals. H780-H
and -J options are supplied with a console which contains RUN and
DC ON indicators for monitoring the processor and power supply
390
H780
states, as well as DC ON/DC OFF, LTC ON/OFF, and ENABLE/HALT
switches for controlling the system. The H780-K and -L options have a
console which contains only a DC ON indicator. H780-C and -0 options have no console panel.
Figure 4
H780 Power Supply Block Diagram
Unregulated Voltage and Local Power Circuits - Unregulated
voltage and local power circuits provide operating dc power for power
supply logic and control circuits, and dc power for the +5V and + 12V
regulator circuits. These circuits are shown in Figure 5. AC power is
supplied to the H780 via an ac input plug and cable. A toggle switch
mounted on the rear of the H780 applies ac power to the power supply. Normally, this switch remains in the ON position, allowing ac
power to be controlled by power distribution and control circuits external to the H780. Primary circuit overload protection is provided by a
fuse mounted on the rear of the H780.
391
H780
F1
AC
ON/OFF
PW R
PR~(~~t~{~f:ANXFIMI~R-'t- r- - -'
:
FAN
"~~-------~~~
-----?
ACV TO
} LOGIC SIGNAL
GENERATION CKTS
+5VA
j230vAAiMARv POWERCONNECTiONS- - - -.....,
I
I
Ft
I
-tSV
PWR
j~~AN
i
II
AC
ON/OFF
XFMR
230V
~
:
-.
:
FAN
I _______________
./
L
_
Figure 5
Unregulated Voltage and Local DC Power Circuits
Primary power circuits are factory-wired for 115 Vac (H780-C, -H, -K)
or 230 Vac (H780-D, -J, -L) operation. Power transformer primary
windings and the two fans operate directly from the switched ac
power.
A single center-tapped secondary winding supplies power for regula-
tor circuits and internal circuit operation. Conventional full-wave rectifiers and a -15V, 3-terminal regulator IC provide regulated voltage for
interna'i distribution. The rectifiers also provide unregulated +30V (+V
UNREG) for internal distribution and regulator operation. A 3-terminal
regulator integrated circuit provides 5V +5 A power for H780 logic and
control circuits. The +5V and +12V regulators use the same,V UNREG
voltage for regulation and distribution to the processor modules. AC
voltage from one side of the transformer secondary is also routed to
the line-time clock (LTC) circuit, which generates a BEVNT L bus
signal for a line-time clock processor interrupt. When used with a 60
Hz line frequency, the interrupt occurs at 16.667 msec intervals; a 50
Hz line frequency will produce interrupts at 20 msec intervals.
+5V and +12V Switching Regulator Circuits - Both +5V and +12V
regulator circuits receive the +V UNREG input power. The +5V and
+ 12V regulator circuits are identical except for component values.
Hence, only the basic +5V regulator is described in detail.
392
H780
The basic regulator is a switching regulator which operates at approximately 10kHz. The main controlling element is a 3-terminal regulator
which operates at approximately the regulated output voltage level.
Basic regulator circuits are shown in Figure 6. Note that the ground
terminal of the 3-terminal regulator is connected to a circuit that allows
adjustment of the terminal voltage over a -0.7V to + 1.5V range.
Hence, the 3-terminal regulator output in the +5V regulator circuit can
range from 4.3V to 6.8V (approx).
Fl
PASS
SWITCH
CURRENT
SENSE
~
+V UN REG.
+ 5V
FREE
WHEELING
DIODE
~
TO OVERLOAO
AND
SHORT-CIRCUIT
PROTECTION
CKT
RIB
R33
+5VADJ
(FACTORY -AOJ I
CIOI_
-15V
-O.7V
07
Figure 6
Basic Regulator Circuit
Normal switching regulator operation is accomplished when the control transistor is turned on. Forward-bias for the control transistor is
supplied via R14. It Is turned off only during fault conditions (overcurrent or shorted output voltage) or when the input ac line voltage is
below specifications. Its emitter supplies unregulated voltage to the 3terminal regulator. At less than 50 rnA regulator output current (approximately), the 3-terminal regulator supplies the output voltage.
However, as load current through the 3-terminal regulator is increased
beyond this value, the voltage drop across R27 and forward-biases the
driver transistor. The pass switch transistor then turns on and applies
the +V UNREG to L2. The output.capacitor then charges toward the
393
H780
+SV value, current limited by the inductance of L2. When the output
voltage rises to the 3-terminal regulator regulation voltage, the 3-terminal regulator turns off; current through R27 stops, and the driver
transistor is not forward-biased. Hence, the driver and pass switch
transistors cut off. The energy stored in L2 continues to charge the
capacitor bank slightly beyond the designed output voltage via the
free-wheeling diode and the current sense resistor. Once the inductor's stored energy is spent, the load discharges the output capacitor
'until the output voltage drops below the 3-terminal regulator's regulation voltage. At that pOint, current through R27 increases and turns on
the driver and pass switch transistors, and the cycle repeats. Note that
as the load is increased, the pass switch must remain on longer in
order to charge the output capacitor to the regulated voltage value.
This process repeats at a 7-12 kHz rate, producing the switching regulator operation.
Switching losses in the pass switch transistor are minimized by the
snubber network. This network operates during the "off" switching
transient (as the pass switch is biased-off) by contrOlling the rate of
increasing collector to emitter voltage as collector current decreases.
The control transistor is turned off during a fault condition by overload
and short-circuit protection circuits. When a fault condition is
detected, the control transistor's base voltage drops to nearly OV,
causing it to cut off. When cut off, operating voltage is removed from
the 3-terminal regulator and R27 current is 0, disabling the switching
regulator circuit.
Overload and Short-Circuit Protection Circuits - Each H7S0 dc output is overload and short-circuit protected. When in an overload condition, excessive power supply current is sensed, causing both switching regulators to go off and then cycle on and off at a low-frequency
rate (approximately 7.S Hz) until the overload is removed. Each time
. the power supply cycles on, the circuit checks for the overload condition. If the load current returns to normal, the 10 kHz switching
regulator operation resumes.
Overcurrent sensing circuits for +S and +12 Vdc outputs are identical
except for component values. A SV power supply overcurrent condition results in an increased voltage drop across the current sense
resistor (Figure 7), forward-biasing the current sense transistor. (During normal operation, this transistor is not forward-biased.) Current
sense transistor collector (OS) voltage then drops from near + V UNREG to the +SV regulator output value; this voltage, which is less than
394
H780
the + 13.8V reference applied to current limit comparator's Inverting
input, is diode-coupled to the comparator's non-inverting input, causing the comparator's output to go low; the diode coupling provides an
OR logic function for both the +5V and +12V overcurrent fault
conditions. The comparator's low output signal triggers the 50 #,sec
one-shot, whose OVERCURRENT L pulse output triggers the 135
msec one-shot and sets the Current limit flip-flop. The OVERCURRENT L pulse is also ORed with the POWER OFF L signal. turning on
the +5V and + 12V hold-off transistors. Both switching regulators are
then disabled. The high 135 msec one-shot output pulse Is ANDed
with the Current limit flip-flop output. turning on +5V and + 12V extended hold-off transistors. Hold-off signals remain in this state and
inhibit switching regulator operation for the 135 msec pulse duration.
At the end of this time. the 135 msec one-shot resets. terminating the
delayed hold-off sig nals, and triggers the 2 msec one-shot. Its active
low output resets the Current Limit flip-flop and clears the 135 msec
one-shot for 2 msec. allowing the regulator pass switch transistors to
operate for 2 msec (minimum). At the end of this time. the 135 msec
one-shot is again enabled (the clear Input goes high) and a new overcurrent cycle is enabled. If the overload is removed, normal operation
resumes; otherwise. the overload causes a new overload condition to
occur and the cycle repeats. as described above.
.
LOW FREQ CKT
R20
FROM +t2V
CU~~~~~ --\4----1
TRANSISTOR
Figure 7
Overload and Short-Circuit Protection Circuits
395
H780
Switching regulator operation is suspended when the operator places
the ·DC ON/OFF switch in the OFF position. Logic signal generation
circuits respond by Immediately asserting BPOK H low to initiate a
processor power-fail sequence. After a 5-10 msec "pseudo delay,"
POWER OFF L is asserted low. This low signal Is wire-ORed with
OVERCURRENT L, inhibiting the switching regulator operation, and dc
power is removed from the backplane.
+ 6 V and + 12 V Crowbar Circuits - Crowbar circuits are
connected across both + 5 V and + 12 V power supply outputs for overvoltage protection. An overvoltage condition could occur if + 12 V and
+5 V outputs shorted together. or if a driver or switch transistor becomes shorted. When shorted to a higher voltage source. the crowbar
fires. shorting the supply voltage that is protected to ground (de return).
In this condition. the ov.erload and short-circuit protection circuits
respond by limiting the duty cycle of the switch transistor until the overvoltage source is removed. Howttver. when the o\,ervoltage is caused by
a shorted driver or switch transistor. short-circuit protection is
ineffective. and the excessive current caused by the crowbar circuit firing
will blow the regulator's fuse (F1 for + 5 V or F2 for + 12 V) ..
The crowbar circuit for the + 5 V output is shown in Figure.8.
It
comprises a 5.6 zener diode 09. diode 08. programmable unijunction
transistor a9 and silicon-controlled rectifier a 15. a 15. R19. 08. and 09
supply the 6.1 Vdc (approx) crowbar reference (threshold) voltage to the
gate of a9 via R21. a9 is normally off and its cathode supplies aO· V
gate input to a 1 5. An overvoltage will present a significantly higher
voltage to the anode of a9 (connected directly to + 5 V) than to its gate
(clamped by 08 and 09 to approximately 6.1 V). This triggers a9 and its
cathode voltage rises to the anode potential. a 1 5 then fires and shorts
(crowbars) the supply output. The circuit remains in this condition until
the overvoltage is removed (a 1 5 current goes to zero) and either the
power supply switch transistor is off. due to short-circuit protection. or
the regulator's de fuse opens. Capacitor C7 decouples the gate of a7 to
prevent noise on· + 5 V from activating the crowbar.
SWI
TCH~~~
-r--rO-9-'--O'~"
l·!'::'::T::-'9-r-"6-.':-2-'C-7
REGULATOR
OUTPUT
09
5.6Y
O.5Y
08
R23
---'----'-----r----'-----L-
Figure 8
~¥N (GNOI
Crowbar Circuit
396
H780
The + 12 V crowbar circuit functions in a similar manner. However, the
unijunction gate reference voltage for this power supply is approximately
13.5 V.
Logic Signal Generation Circuits - Logic signal generation
circuits produce LSI-11 bus signals for power-normal/power-fail and
line-time clock interrupt functions and processor Run-Enable/Halt mode.
The RUN indicator circuit monitors the SRUN L backplane (nonbused)
signal and provides an active display when the processor is in the Run
mode. BPOK Hand BOCOK H indicate power status. When both are
high, power to the LSI-11 bus is normal and no power-fail condition is
pending. However, if primary power goes abnormally low (or is removed)
for more than 16.5 ms, BPOK H goes low and initiat~s a power-fail
processor interrupt. If the power-fail condition continues for more than
an additional 4 ms, a "pseudo delay" circuit causes BOCOK H to go low.
The circuit also causes the overload and short-circuit protection circuit to
inhibit + 5 V and + 12 V control transistors; normal output voltages are
available for 50 #LS (minimum) after BOCOK H goes low (depending on
the loading of the dc output voltages). The DC ON/OFF switch simulates
an AC ON/OFF operation by turning swit~hing regulators on or off without turning system primary power off. A normal power-up/power-down
sequence is produced by this circuit. The line-time clock circuit produces
a processor interrupt at the power line frequency (either 50 or 60 Hz).
The circuit simply asserts the B EVNT L line at the line frequency.
DC voltage monitor circuits respond to both + 5 V and + 12 V power
supply outputs. A +2.5 V reference at the voltage comparator's noninverting input is established by + 5 A and a voltage divider comprised of
A25 and R3, as shown in Figure 9.
Voltages are sensed at the
anodes of diodes 017 and 035.
The sensed voltage to the voltage comparator's inverting input is normally 5 V, causing the comparator's output to go low. The low signal
(lrward-biases DC ON panel indicator driver transistor 010, producing a
DC ON indication, and reverse-biases the BOCOK H FET bus driver 06.
As a result, 06 cuts off, and its source voltage rises to +5 V, producing
the active BOCOK H signal.
When either (or both) power supply output is 0 V, the voltage at the
voltage comparator's inverting input is less than the +2.5 V reference.
Hence, the comparator's output goes high, turning off the DC ON
indicator and allowing 06 to conduct. 06 asserts the BOCOK H Signal
low, indicating that a dc power-fail condition exists. When normal power
is restored, as during the power-up sequence, C37 charges via R50.
When the C37 voltage exceeds the +2.5 V reference, the comparator's
output then goes low (normal).
397
H780
VOL TAGE
+i:·,
1
~-- BDCOK
SENSE II\IPUTS
~
.~A
on
OJ'
"
HA
01
."
029
0.0
,.---- ---."
AC Lv H
DC LO H
D2~
021
r;.A-;T~;-Co;.;;L;-
-
I
I
I ~~:~~:;';' DC ON
I1. _ _ _ _ _
." 0'_ _ _ -'
POWEO OFF L
+5A
,
+5A
I
TO OVERLOAD AND
>----'-+SHORT-CIRCUIT
PROTECTION CKTS
I
I
L _______ .JI
r.--------------------.
I
I
PART
I
.~A
OF CONSOLE
+'V
RUN
D~'
I
I
,
I
,,
SRUN L --',L-.l-_4)_.q-",
+,A
I
I
SHALT L
." HALT
CHALT H
L ____________________
,
Figure 9
~
Logic Signal Generation Circuits
AC voltage monitor circuits include an ac low comparator. a 16.5 ms
delay. and a BPOK H bus driver circuit. which is enabled only when
BOCOK H is in the active (dc voltage normal) state. Rectifiers 02 and 03
produce positive-going dc voltage pulses at twice the ac line frequency.
R32. R12. and C1 produce nominal +3.9 V (peak) normal line voltage
398
H780
pulses which are coupled to the non inverting input of the ac low comparator via R48. R8 and R9 produce a +2.5 V reference for the comparator's inverting input. The comparator's normal output is a series of
pulses occurring at twice the ac power line frequency. Each positivegoing leading edge retriggers the 16.5 ms one-shot. keeping it in the set
state. The 16.5 ms one-shot output is diode-ORed with OCOK L via
diodes 025 and 023 and PWR OFF H via 024. Normally, the three
signals are low and 011 remains cut off. In this condition, C4 charges to
+3.125 V via R36 and R38. This signal is then applied to the power OK
comparator's inverting input via R24. Since the noninverting input is
referenced to +2.5 V by voltage divider R5 and R6, the comparator's
output goes low, biasing off FET 05. 05's source voltage then rises
toward + 5 V via R46, producing the active B PO K H s!gnal. PO\l\"erup/power-down sequence timing is shown in Figure 10 .
AC INPUT
I
I
BPOK H
rBOCOKH
DC OUTPUT
VOLTAGES
-
70 .... CMINI-!
l,,-.
.
~~
, 1 . ,.,.,
~---'I--
~
~~
I
I
\--3-IOmo
~I'- - - - P O W E R u P - - - -.....i4I
..- - - - - P O W E R
Figure 10
-_'\--
DOWN
------'~
Power-Up/Power-Oown Sequence
A power failure is first detected when the pulsating dc voltage at th~ ac
low comparator's noninverting input is less than + 2.5 V (peak). The
comparator's output then remains low, allowing the 16.5 ms one-shot to
go out of the retrigger mode. The one-shot resets 16.5 ms after tt,e
leading edge of the last valid ac voltage alternation: the 16.5 ms delay is
equivalent to a full line cycle (two-alternate) failure. The high one-shot
output is then coupled via 023 to the base of 11, forward-biasing it.
a
a 11
conducts and rapidly discharges C4: R36 limits peak discharge
current.
The low voltage thus produced is less than the + 2.5 V reference at the
power OK comparator's input. and its output goes high. 05 then conducts and asserts the BPOK H signal low (power fail). The AC LO H
399
H780
signal produced by the 16.5 ms one-shot is coupled via 034 to C39 on
the inverting input of AC OK comparator E5. When C39's voltage rises
above 2.5 V. the comparator's output goes low, turning off the DC ON
indicator, negating BOCOK via the dc voltage monitor circuit, and turning off the regulator circuits by asserting POWER OFF L via 027.
When normal power is restored. the 16.5 ms one-shot returns to the
retrigger (set) mode. AC LO H goes low and enables the dc voltage
monitor and regulator circuits. The low AC LO H signal also removes
forward bias from the base of a 11, cutting it off. Its collector voltage
then rises as C4 charges at a relatively slow rate. R38 controls the
charging rate of C4 and ensures that ac voltage and dc output voltages
are normal for approximately 100 ms (70 ms minimum) before BPOK H
goes high.
The DC ON/OFF switch simulates a power failure when it is placed in
the 0 FF position. Cross-coupled inverters provide switch debounce protect on and a low (false) DC ON H signal is produced. This signal is
inverted to produce a high PWR OFF H signal that is coupled via 026 to
the "pseudo delay" circuit. causing a power-fail sequence to occur. and
to a 11 via R53 and 024. causing BPOK H to go low (power-fail
indication). After a 5-10 ms (approx) "pseudo delay," C13's voltage
rises above the dc off voltage comparator's +2.5 V reference (noninverting) input. The comparator's outpyt goes low. asserting POWER
OFF L low and turning off the switch'ing regulators. When the DC
ON/OFF switch is returned to the ON position, PWR OFF H goes low,
rapidly discharging C13. POWER OFF L then goes high and switching
regulator operation resumes. Approximately 100 ms later, BPOK H goes
high and normal processor operation is enabled. DC ON/OFF circuit timing is shown in Figure 11.
DC
ON
ON/OFF
SWITCH OFF
BPOK H
BDCOK H
DC OUTPUTS
It-o- - - D C OFF ----.+.1--.- - - D C ON -----t-I
Figure 11
DC ON/OFF Circuit Timing
400
H780
BEVNT L is the bused EVENT line which is normally used for line-time
clock interrupts. 04 is cut off and 01 is forward-biased during negative
alternations of the ac line. producing low-active BEVNT L signals. 01
clips negative alternations and limits 04's reverse-bias to emitter voltage. The LTC ON/OFF switch must be in the ON position for BEVNT L
signal generation. When the LTC function is not desired. the LTC switch
is set to the OFF position; CSPARE2 goes low. 01 remains cut off. and
BEVNT L remains passive (high).
The RUN indicator is illuminated whenever the processor is executing
programs. SRUN L. a nonbused backplane signal. is a series of pulses
which occur at 3-5 #lS intervals whenever the processor is in the Run
mode. The pulses trigg~r a 200 ms one-shot on each SRUN L pulse
leading edge. keeping it in the retrigger mode. Its high RUN H output
signal is then inverted. producing a low signal that turns on the RUN
indicator. When the processor is in the Halt mode. SRUN L pulses cease
and the 200 ms one-shot resets after the 200 ms delay. The RUN
indicator turns off. indicating the Halt mode.
The HALT/ENABLE switch allows the operator to manually assert the
BHALT L signal low. causing the processor to execute console OOT
microcode. When in the ENABLE position. BHALT L is not asserted. and
the Run mode is enabled. Cross-coupled inverters provide a switch
debounce function.
H780-C. -D. -H. -J. -K. -L Installation
Installation of an H780 power supply consists of inspecting the unit.
connecting a suitable dc power cord. setting up the +5 and + 12 Vdc
outputs. and connecting the power supply to the system.
Differences Between 116 Vae and 230 Vae Power Supplies - The main differences between the 115 Vac H780 power supplies
(H780-C. -H. and ~K) and the 230 Vac H780 power supplies (H780-0.
-J. and -L) are the ac input jumper configuration on the power supply
terminal block (TB 1). the fuse rating (115 Vac supplies are equipped
with a 5 A fast-blow fuse; the 230 Vac supplies have a 2.5 A fast-blow
fuse)' and the power line RFI filter which is used only on the ?30 Vac
supplies. Power supplies factory-wired for 115 Vac operation (H780-C.
-H. and -K) can be rewired for 230 Vac operation by reconfiguring the
jumpers on TB 1. However. European users of 115 Vac supplies should
not rewire the H780-C. -H or -K for 230 Vac operation as these supplies
will not meet the EMI requirements of VOE N-12. On the other hand. the
230 Vac supplies (H780-0. -J. and -L) can be rewired for 115 Vac and
used in European countries as well as the U.S. AC wiring configurations
for the H780 power supplies.
401
H780
Space Requirements - The H780 power supply occupies a
space 13.97 cm wide X 8.43 cm high X 37.15 cm long (5-1/2 in wide
X 3-1/3 in high X 14-5/8 in long). Space should be available to the rear
of the supply to gain access to the AC ON/OFF toggle switch. H780-H,
-J, -K and -l options should be installed to allow for unobstructed viewing and use of the power supply console.
Input Power Requirements - The user's ac power source
must be capable of providing 340 W (full load) of ac power at 50 ± 1 Hz
or 60 ± 1 Hz. No ac power cord is supplied with the H780 options: it is
the user's responsibility to provide the proper line cord and ac plug for
his particular application.
Cable Requirements - Three interface cables are supplied
with the H780 options to connect the H780 console to the power supply
and to connect the H780 to the system backplane:
Cable
Digital Part No.
DC output cable (connects dc to
backplane)
70-11 584-0-0
Power supply status cable (logic cable)
(connects logic signals to backplane)
70-11411-0K-0
Power supply console cable (connects console
to H780)
70-08612-0M-0
Refer to the SA 11-N description for multiple backplane interconnection
information.
In addition, if the user is controlling an H780 slave power supply (H780K or -L) from an H780 master (H780-H or -J). the interface cable between the master and slave is the user's responsibility. This cable can be
constructed from 12-conductor ribbon cable and two 16-pin, IC-type
male connectors (3M part number 3416). The master/slave cable can be
ordered from the nearest Digital Equipment Corporation Sales Office
Cable lengths and part numbers are listed in Table 1.
Installation Procedure - After unpacking the H780 from the
shipping container, inspect the unit and report any damage to the nearest Digital Equipment Corporation Sales Office. Inspect for the following:
1. Damage to the chassis or printed circuit boards
402
H780
Table 1
Master/Slave Interface Cables
Length
DIGITAL
Part No.
10.2 cm (4 in)
15cm (6 in)
22.9 cm (9 in)
27.5 cm (11 in)
35.6 cm (14 in)
45.7 cm (18 in)
124 cm (49 in)
61.0 cm (2 ft)
1.83m (6ft)
3.05m (10ft)
70-08612-00
70-08612-0F
70-08612-0K
70-08612-0M
70-08612-1 B
70-08612-1 F
70-08612-4A
70-08612-02
70-08612-6A
70-08612-10
2. Loose or broken components
3. Damage to the console on the H780-H, -J, -K, or -L
4. Free rotation of the blades on the cooling fans
5. Proper amperage fuse (2.5 A fast-blow for H780-0, -J, and -L; 5 A
fast-blow for H780-C, -H, and -K)
6. Proper seating of the fuse
7. Proper seating of the console cable connectors (H780-H, -J, -K, and
-L)
8. The presence of the shield covering the terminal block at the rear of
the H780.
Connecting AC Une Cord - The H780 power supplies are equipped
with a terminal block (Figure 12 ) at the rear. Jumpers on this terminal
block configure the supply for 115 Vac or 230 Vac operation
while two of the terminal block screws provide a means of
connecting ac input power to the H780. A suitable length of No. 16
AWG. 3-conductor, stranded power cord is to be connected to the terminal block as shown in Figure 12 (for H780-C, -H, and -K supplies), or
Figure 14
(for H780-0, -J, and -L supplies). The jumpers shown in
Figures 13 and 14 are factory-installed. However, the jumper configuration can be altered by the user to change the ac input from 115 V
to 230 V for the H780-C, -H, and -K. or from 230 V to 115 V for the
H780-0, -J, and -L. European users are advised not to operate an H780C, -H, or -K power supply on a 230 Vac line as these supplies are not
403
H780
AC POWER CORD
CABLE CLAMP
AC LINE
FUSE IF1)
CHASSIS GROUND
SCREW
ACTERMINAL
BLOCK
ITBlI
8115-1
Figure 12
AC Terminal Block at Rear of H780
BLACK
WHITE
GREEN
1
':"
0
CHASSIS
GROUND
TERMINAL
BLOCK
(TBII
CP 2401
Figure 13
H780-C. -H. and -K (115 Vac)
AC Terminal Block Wiring Configuration
404
H780
BROWN
}
_-----....:;B-L-.UE:.--
230 VAC
GREEN/YELLDW
1
-=
CHASSIS
GROUND
TERMINAL BLOCK
(TBI)
(P·2408
Figure 14
H7S0-D. -J. and -L (230 Vac) AC Terminal
Block Wiring Configuration
equipped with a RFI line filter. When installing the ac line cord. remove
the plastic shield covering the terminal block (Figure 12 ). Terminals
should be crimped or soldered to the power cord wires. Connect the ac
phase wires to the terminal block (Figures 13 and 14 ) and connect
the ac ground wire to the H7S0 chassis using the Phillips head screw to
the right of the terminal block (Figure 12 ). This screw also provides a
ground for the RFI filter in the H7S0-D. -J. and -L supplies by means of a
green/yellow wire. Make sure this wire is reconnected to ground when
replacing the screw. Be sure to replace the plastic shield over the terminal block after completing the wiring. Route the power cord to the top of
the H7S0 chassis and secure it to the chassis with a suitable strain relief.
as shown in Figure 12 . The upper right screw at the rear of the H 7 SO
chassis can be used to anchor a cable clamp. The free end of the power
cord should be terminated with a connector which is suitable for the
user's requirements.
H780-C and H780-0 Stand-Alone Operation - If an H7S0-C or -0
power supply is to be used as a stand-alone supply. a 510
1/4 W
resistor must be installed between J2-2 and J2-9 on the power supply
printed circuit board (Figure 15 ). The 510 n resistor provides a pull-up
level to an internal power supply gate. thus enabling the + 5 V and + 12
V outputs. This resistor is not required for the H7S0-K or -L slave supplies. nor is the resistor required for the H7S0-H and -J supplies. The
resistor can be installed by bending its leads and inserting them into
socket J2. or by soldering the resistor across pins 2 and 9 of a 16-pin
DIP. IC-type male connector. Pinning for the J2 enable plug is shown in
Figure 16 .
n.
405
H780
J2
J1
Figure 15
Locations of J 1 and J2 on Power Supply Board
4
5
6
7
8
(~'2409
Figure 16
H780-C and -0 Enable Plug
Initial Power Turn-On - Before connecting the dc output of the H780
to a system. verify the dc output voltages by performing the following
procedure.
1. If. the H780 is a slave supply (or an H780-C. -0). either connect cable
J2 REMOTE of the slave H 780 (or J2 on the power supply PC board
of H780-C. -0) to the J2 REMOTE connector on the H780 master
supply or install a 510
114 W resistor into the slave.
n
406
H780
2. Connect the H780 to a suitable ac power source.
3. Set the H780 AC ON/OFF switch (Figure 12
the H780 should operate.
) to ON. The fans in
4. On H780-H and -J options. set the console DC ON/OFF switch (Figure 25 ) to ON. The DC ON indicator should light. (For master-slave
operation. the DC ON/OFF switch and DC ON indicator are located
on the user's master supply. The DC ON indicator on the slave should
also light.)
5. Using a DVM. measure the + 5 and + 12 Vdc outputs at J4 (Figures
20 and 21 ) on the H780 PC board (side 2). The + 5 V output
should not be greater than + 5.15 V and the + 12 V output should not
exceed + 12.36 V.
6. Set the master console DC ON/OFF switch to the OFF position.
7. Set the AC ON/OFF switch to the OFF position.
8. Unplug the ac power cord and connect the H780 system.
Mounting an H780 to an H9270 Backplane - The H780 power supply
is designed to be mounted to the LSI-11 H9270 backplane. Four holes
on the left side of the H780 are equipped with No. 8-32 threaded bosses
(Figure 17 ). These holes mate with four holes in the right side of the
H9270 backplane frame. Four No. 8-32 X 1/2 inch screws are inserted
!hrough the H9270 backplane holes and are threaded into the H780
power supply. The H9270 backplane and the H780 power supply thus
become one assembly (Figure 18 ). Figure 17 shows the location of
the four mounting holes in the H780. The two screws securing the frontchassis partition must be removed. These screws are to be replaced with
longer screws (1/2 in) when attaching the H780 to the H9270.
Connecting an H780 to an H9270 Backplane'- The H780 power
supply is connected to the H9270 by means of two cables. These cables
are supplied with the H780. One of these cables is a 25.4 cm (10 in)
logic signal cable (DIGITAL part number 70-11411-0K-0). which connects from J1 on the power supply board (Figure 15 ) to connector
pins on the H9270 printed circuit board (Figure 19 ). Either end of this
cable can be connected to the power supply or the backplane. The other
cable is a 30.5 cm (12 in) dc output cable (part number 70-11584-0-0).
This cable is terminated at one end with a keyed. 12-pin connector
which mates with J4 on side 2 of the H 780 power supply board. Figure
20
shows the location of J4; Figure 21 shows J4 pinning. The
remaining end of the dc output cable is terminated with a 6-lug connector strip which is connected to the H9270 backplane terminal block.
407
H780
# 8-32 THREADED HOLES
FOR MOUNTING H9270
Figure 17
REMOVE THESE SCREWS
Left Side of H780 Showing H9270 Mounting Holes
8115--12
Figure 18
H780 Mounted to H9270 Backplane
408
H780
J4 12-PIN CONNECTOR
(SIDE 2 OF PC BOARD)
H7BO POWER SUPPLY
AC LINE CORD
EJ
CONSOLE
SIGNAL/POWER
CABLE (\\.n,)
\ ~-~!....-+-+-"""'''''''r-T-r----
.!.!!!.~
,
2
3
4
5
6
7
8
9
10
:"0 -
BPOIC H
BEvNT L
SRUN L
(ICEY)
GROUND
Cl3 l
CS3 L
SPARE
BHALT L
DCOIC H
3
4
5
6
7
B
+~A
DCONH
SRUN l
iiEVNfi
9
10
1\
,2
13
GROUND
Cll
CS3
15
' 16
SPARE
,4
+!IA
SPAflE
SPARE
GROUND
GROUND
DC OK LED H
SPARE
B HALT L
-e;- BOCOK H
L~~:::LTL
""""==
·----.u+5VB
,
2
(70- 08612 - OM -0 I
H9270 BACKPLANE REAR VIEW
(P, C, BOARD SIDE 2)
SRUN L
BPOIC H
GND
TERMIlIIAL BLOCK
Figure 19
H780 to H9270 Backplane Connections
J4
DC OUTPUT
CONNECTOR
Figure 20
Location of H780 DC Output Connector (J4)
409
H780
J4
PIN NO.
12
+12VRETURN
CONNECTOR
11 - - - +12V OUTPUT
KEY WAYS (61
:0 -------I
8
+5V RETURN
:~
=1
3
+5V OUTPUT
2~
NOTE
VIEWED FROM BOTTOM OF
POWER SUPPLY PC. BOARD
CP-2410
Figure 21
Pinning for H7BO DC Output Connector (J4)
as shown in Figure 19. When connecting the 6-lug connector strip to
the H9270 backplane. make sure that the spade lug connectors ~re
facing up. Figure 22 shows the dc OlAtput cable connected to J4 of the
H7 BO. The H TBO logic signal and dc output cables are routed toward the
rear of the power supply and exit from the supply chassis next to the
H9270 backplane terminal block.
H7BO-H. -J. -K. and -l power supplies have a console that is attached to
the H7BO and connected to the supply by means of a console
signal/power cable (part number 70-0B612-0M-O). This cable is factory-installed from J2 on the power supply board (Figure 15 ) to J1 on
the console PC board (Figures 1t9 and23).
H780 Master-Slave Connection - An H7BO-H or -J power supply can
be used as a master supply to control an H7BO-K or -L slave supply. This
master-slave arrangement allows the user to power up/power down system expander backplane logic from the master supply console. The slave
supply is connected to the master supply by means of the J2 (REMOTE)
connector on the master supply console printed circuit board. and J2
(REMOTE) or J3 on the slave power supply console printed circuit board.
The interconnecting cable is the user's responsibility. Two 16-pin. ICtype male connectors and a suitable length of 16-conductor cable (preferably ribbon type) can be used to construct the interconnecting cable.
410
H780
Figure 23 shows the console printed circuit boards and the locations
of the J1 (SUPPLY), J2 (REMOTE). and J3 connectors. J1 is always
connected to J2 of the power supply printed circuit board (Figure 19 )
by the console signal/power cable (part number 70-08612-0M-0) which
is factory-installed. Pinning for J2 (REMOTE) on the console printed circuit board is shown in Figure ·24. Pinning for J2 on the power supply
printed circuit board is indicated in Figure 19.
Connector J3 (Figure 23 ) provides the means of interconnecting boxes
in a multiple backplane system. This connector parallels connector J2. so
a 'user can connect J2 on the slave BA 11-M to J2 on the master
PDP11/03 using the cable supplied with the first BA 11-M expansion
box. and can connect J3 on the first slave SA 11-M to J2 on the second
slave BA 11-M using the cable supplied with the second BA 11-M.
The slave console boards in the early model power supplies did not
contain connector J3, Th.erefore. a single cable containing three DIP
plugs (BC03Y -16) should be purchased to interconnect boxes in a multiple backplane system. Each 01 P plug is inserted into connector J2 on
each box.
81' ....
Figure 22
H780 DC Output Connector (J4)
with Mating DC Output Cable (70-11584-0-0)
411
H780
J1 (SUPPL V) CONNECTED TO J2 ON
POWER SUPPL V P.C. BOARD OF MASTER
J2 (REMOTE) CONNECTED TO J2 (REMOTE)
ON SLAVE SUPPLV INDICATOR P.C. BOARD
- a. H780-H and -J (Master)
•
8115-2
•
••
•
·t
_
-..~'-- ,mr"',
•
b. H 780-K and -L (Slave)
Figure 23
H780 Master-Slave Connections
412
t
H780
16
15
14
13
12
11
10
9
2345678
J2 (REMOTEI
PIN
2
4
6
SIGNAL
PIN SIGNAL
NO CONNECTION
9
NO CONNECTION
DCONH
10
SPARE 3
NO CONNECTION
11
SPARE4
SPARE 2
12
SPARE 6
GROUND
13
GROUND
Cl3 L
14
DCOKH
CS3l
16
SPARE 8
SPARE 1
18
NO CONNECTION
CP·Z411
Figure 24
Pinning for J2 (REMOTE) on
Console Printed Circuit Board
Console Controls and Indicators - The H780-H or -J master
console has three LED indicators and three 2-position toggle switches.
One of the LED indicators is a spare indicator. Circuitry to drive this
indicator is included on the console printed circuit board for user application. The console on the H780-K and -L slave supplies has only one
LED indicator. DC ON. Figure 25 shows the H780 console controls
and indicators; they are described in Table 2
. Additionally. the rear
panel of the H780 contains an AC ON/OFF toggle switch and an ac line
fuse (Figure 12).
+12 V and +6 V Adjustment Procedure - The H780 power
supply is factory-adjusted to produce + 12 V and + 5 V outputs within
the operating tolerance of the system. The adjustment procedures presented allow the user to trim the dc outputs of the H780 to meet his·
particular needs. One adjustment is provided for the
12 V output.
while two adjustments (one for the output voltage and one for the
switching regulator frequency) are provided for the +5 V. Figure 26
shows the location of the adjustments. A DVM. an oscilloscope. and a
small screwdriver are required. Power supply loading is provided by the
LSI- 1 1 bus or processor.
+
413
H780
Table 2
H780 Controls and Indicators
Controll
Indicator
Type
Function
DC ON
LED indicator
Illuminates when the DC
ON/OFF toggle switch is set to
ON and proper dc output voltages are being produced by the
H780.
If either the + 5 or + 12 V output
from the H780 is faulty. the DC
ON indicator will not illuminate.
This is the only indicator on the
H780-K and -L slave supplies.
RUN
LED indicator
Illuminates when the processor
is in the run state (see ENABLE/HALT).
SPARE
LED indicator
Not used by the H780 or processor. The H 780 contains circuitry
for driving this indicator for user
applications.
DC ON/OFF
Two-position
toggle switch
When set to ON. enables the dc
outputs of the H780. The DC ON
indicator will illuminate if the
H780 dc output voltages are of
proper values. If a slave supply is
connected to a master. the slave
DC ON indicator will light if the
slave dc output voltages are of
proper value.
When set to OFF. the dc outputs
from the H780 are disabled and
the DC ON indicator is extinguished. If a slave supply is
connected to a master. the slave
DC ON indicator will also extinguish.
414
H780
Table 2
Cantrall
Indicator
ENABLE/HALT
H780 Controls and Indicators (Cant)
Type
Function
Two-position
toggle switch
When set to ENAB LE. the B
HALT L line from the H780 to
the processor is not asserted and
the 'processor is in the Run mode
(RUN indicator illuminated).
When set to HALT. the B HALT L
line is asserted. allowing the processor to execute console ODT
microcode (RUN indicator extinguished).
LTC ON/OFF
When set to ON. enables the
generation of the line-time clock
( LTC) B EVNT L signal by the
H780.
Two-position
toggle switch
When set to OFF. disables the
H780 line time clock.
AC ON/OFF
(rear panel)
When set to ON. applies ac
power to the H780.
Two-position
toggle switch
When set to OFF. removes ac
power from the H780.
FUSE (rear panel)
5 A or 2.5 A
fast-blow
Protects H780 from excessive
current. H780-C. -H. and -K use
a 5 A fuse. H780-D. -J. and -L
use a 2.5 A fuse.
415
H780
SPARE INDICATOR
Figure 25
Console Controls and Indicators
416
H780
+12 V OUTPUT
ADJUST (R87)
CCW - INCREASE
CW - DECREASE
+5V FREQUENCY
ADJUST (R69)
CW· DECREASE
CCW· INCREASE
+5 V OUTPUT
ADJUST (R88)
CCW - INCREASE
CW - DECREASE
I
\,
-
'1
',,'1,1,1I
\
\ ~,
" --=,:....-.------........- 6116-8
Figure 26
Locations of H780 Adjustments
417
H780
+ 12 V Adjustment - Perform the following procedure when adjusting
the + 12 Vdc output.
1. Apply power to the system and allow a 5-minute warmup period.
2. Using a DVM. measure the + 12 V output at the system backplane
terminal block (Figure 19 ).
3. Using a small screwdriver. adjust R87 (Figure 26 ) until the DVM
indicates + 12.0 V (+ 11.64 V to + 12.36 V acceptable range). Turning R87 clockwise decreases the + 12 V output. while turning
counterclockwise increases the output.
NOTE
If R87 is turned too far counterclockwise. the
+ 12 V output will crowbar and drop to approximately 0 V. This will occur between + 13.0 V
and + 16.5 V. Do not allow the supply to crowbar as this may blow the internal fuse (F1) protecting the + 12 V regulator.
4. Using an oscilloscope. measure the ripple on the + 12 V output at the
backplane terminal block. The ripple should not be greater than 350
mV peak-to-peak.
5. Using an oscilloscope. measure the amplitude and frequency of the
ripple on the + 12 V output at the backplane terminal block. The
ripple should not be greater than 350 mV peak-to-peak with a period
from 65-140 p.s. If the ripple period is not within 80-140 p.s. adjust
R37 to + 12 V.
+ 5 V Adjustment - Perform the following procedure when adjusting
the + 5 Vdc output.
1. Apply power to the system and allow a 5-minute warmup period.
2. Using a DVM. measure the + 5 V output at the system backplane
terminal block (Figure 4-50).
3. Using a small screwdriver. adjust R88 (Figure 26 ) until the DVM
indicates +5.0 V (+4.85 V to +5.15 V acceptable range). Turning
R88 clockwise decreases the + 5 V output. while turning counterclockwise increases the output.
NOTE
If R88 is turned too far counterclockwise. the
+ 5 V output will crowbar and drop to approximately 0 V. This will occur between + 5.6 V and
+6.8 V. Do not allow the supply to crowbar as
this may blow the internal fuse (F2) protecting
the + 5 V regulator.
418
H780
4. Using an oscilloscope. measure the amplitude and frequency of the
ripple on the + 5 V output at the backplane terminal block. The ripple
should not be greater than 150 mV peak-to-peak with a period from
80-140 p.s. If the ripple period is not within 80-140 p.s. adjust ·RS6
(Figure 26 ). Turning RS6 clockwise decreases the ripple period.
while turning counterclockwise increases the period. After adjusting
the ripple period. recheck the + 5 V output (steps 2 and 3).
419
H909-C
H909-C GENERAL PURPOSE LOGIC ENCLOSURE
GENERAL
The H909-C is one of the three basic enclosures available: the H909-C
enclosure, the BA 11-M expansion box and the BA 11-N mounting box.
SPECIFICATIONS
Width
Height
Depth
48.25 em (19 in.)
13.33 em (5.25 in.)
62.86 em (24.75 in.)
70.48 em (27.50 in.) including
bezel
Weight
27.21 kg (60 lb.)
Mounting Space for Power
Supplies
12.7 em X 15.8 em X.50.8 em
(5 in. X 6.25 in. X 20 in.)
Figure 1
H909-C Enclosure
420
H909-C
DESCRIPTION
The H909-C is a general purpose logic box designed to accommodate
the DDV11-B backplane or anyone of several different standard logic
subsystems (Figure 1). In addition, with the use of compatible logic
frames and connector blocks, it can house custom-configured subassemblies. The box features a distinctive front panel that can be drilled
for lights and switches as desired by the user. A fan is provided for
cooling capability and ample room is reserved for power supply installation.
CONFIGURATION
A detailed description of each, including application and configuration
information, is presented in the following table. The various options
available are listed below.
Options
Voltage
(V)
Bezel* Includes
Mounting
H909-C
No
Fan and H0341
card guide
PDP-11/03-XA 115
Yes
X=E: KD11-F
PDP-11/03-XB 230
Yes
X=K: KD11-R
PDP-11/03-LC 115
Yes
PDP-11/03-LD 230
Yes
KD11-R.and BDV11-A BA11-NC or
BA11-ND
KD11-R and BDV11-A BA11-NC or
BA11-ND
BA11-ME
BA11-MF
BA11-NE
BA11-NF
No
No
No
No
115
230
115
230
Cable to daisy chain
Power supply
* Including switches
421
BA11-MC or
BA11-MD
BA11-MC or
BA11-MD
H984
H984 SERIES CABINETS
GENERAL
H984 series is one of two types of low-profile cabinets available: the
H984 series and the H9800-A. The H984-BA (115 Vac) and the H984BS (230 Vac) are low-profile cabinets equipped with a walnut-grained,
plastic laminate top surface and four ball-type casters mounted on a
supporting frame for ease of positioning on solid or carpeted surfaces.
The cabinets are a light gray steel enclosure trimmed in flat black to
make them compatible with the decor of the modern office or laboratory.
Figure
SPECIFICATIONS
Dimensions
Width
Depth
Height
1
H984 Series Cabinet
59.7 cm (23.50 in)
71.3 cm (28.06 in)
54.6 cm (21.50 in)
Module enclosure
Standard 48.3 cm (19 in) EIA
Mounting space
Usable height
Usable depth
59.7 cm (23.50 in)
61.7 cm (24.28 in)
44.6 cm (17.56 in)
Color
Walnut-grained top surface, light gray side
panels, chrome and flat black trim
422
H984
Description
Weight
Low-Profile Cabinet (115 Vac)
Low-Profile Cabinet (230 Vac)
H984-BA
H984-BB
31.8 kg (70 Ib)
31.8 kg (70 Ib)
Optional Hardware
Blower Fan (115 Vac)
Blower Fan (230 Vac)
Blank Connector Panel (back)
Louvered Cover Panel (front)
Blank Metal Cover (front)
Connector Panel Frame (back)
Connector Panel Assembly (back)
70-12438-0
70-12438-1
74-17440
12-11474-0
H950-NC
74-16743
70-12871
3.6 kg (8Ib)
3.6 kg (8Ib)
2.3 kg (Sib)
0.45 kg (1Ib)
1.8 kg (4Ib)
Part No.
Shipping
DESCRIPTION
Each H984 provides mounting space for standard 48.3 cm (19 in.)
panels or racks at both the front and rear of the unit. Two vertical
angles at the front and rear opening of the enclosure contain predrilled holes at EIA spacing. The angles can be laterally positioned
within the cabinet to adjust for mounting units with varying depths.
Both sides of the steel enclosure contain ventilation ports to allow
COOling of the internal components.
A service leg with caster is located beneath the center of the unit and
can be easily extended and retracted. The service leg provides stability to the cabinet when slide-mounted chassis are withdrawn from the
front of the cabinet. When not in use, the leg retracts into the channel.
A 115 Vac power distribution panel is supplied with the cabinet and is
mounted at the top of the rear opening of the cabinet. The panel can
be easily repostioned to accomodate internal chassis when required.
Optional Equipment
Fan Panel Assembly - A fan panel assembly with two enclosed
rotary fans is available as an option and provides additional cooling for
the electrical components in the cabinet. The assembly is prewired
with a cord and male connector which can be inserted into one of the
outlets on the power control panel (part of the H984 cabinet). The fan
assembly is available for 115 Vac or 230 Vac. The panel is supplied
with hardware for mounting.
Black Plastic Front Cover - A flat black, plastic louvered cover panel, 4.45 cm(1.75 in) high, can be used to complete the covering at the
423
H984
front of the H984. The panel slots allow increased air flow through the
cabinet.
Blank Connector Panel - The blank connector panel is designed to
completely enclose the rear opening of the H984 when the blower fan
assembly option is included. This provides a surface for mounting
interface cable connectors or cable openings. The panel is supplied
with hardware for mounting.
Blank Metal Panel - A light gray blank metal cover panel, 8.9 cm (3.5
in) high, can be ordered to complete the covering at the front of the
cabinet. The color is the same as the PDP-11/03 front panel and H984
cabinet.
Connector Panel Assembly - A hinged connector, preformed for
mounting up to eight cable connectors, encloses the remainder of the
H984 rear opening when the fan assembly is included.
424
H9270
H9270 BACKPLANE
GENERAL
The H9270 consists of an 8-slot backplane with a card guide assembly. This backplane is designed to accept up to eight double-height
modules (including processor), four quad modules, or a combination
of quad and double-height modules. When used for bus expansion in
multiple backplane systems, the H9270 provides space for up to six
option modules, plus the required expansion cable connector module(s) and/or terminator module.
DESCRIPTION
Mounting the Backplane
Mounting dimensions and possible methods of mounting the H9270
backplane (in any of three planes) are shown in Figure 1. Option positions are shown in Figure 2. Slot numbers indicate device interrupt
and DMA priority in LSI-11 bus systems. The lowest numbered positions receive the highest priority.
DC Power Connections
Voltage and Current Requirements - A power supply for a single
H9270 backplane LSI-11 system should have the following capacity:
+5V ±5% load; 0-18 A static/dynamic
+12V ±3% load; 1-2.5 A static/dynamic
+5 ripple; less than 1% of nominal voltage
+12 ripple; less than 150 mV p-p (frequency 5 kHz)
NOTE
Regulation at the H9270 backplane must be
maintained to the specifications listed above
The H780 power supply option provides sufficient dc power and generates the required bus signals. Installation details are included in the
H780 power supply description.
425
H9270
REAR MOUNTING
10-32 THD • 1.27em (0.5In)
THREADED STUD (4 PLACES)
0.2em
(O.08ln)
~------------------~- -r~
6.7em
(2.63In)
~
0.34 em (0.IB7.nl DIA
HOLES 4 PLCS.
tt:===:::--;2;;7:-;.6i;c;mr(liOo.:aB7i71i;n)~===:.r!110.35emI0.'4In
2B.3cm (11.15 In)
-\
VIEW FROM REAR OF BACKPLANE
TOP AND BOTTOM MOUNTING
2B.3cm
111.15 In)
1
IB.5cm
(7.29In)
",.,.)
27.9cm
.
22.96cm
(9.04In)
6-32 THD HOLE
0.64em (0.25In) DEEP
""
I
1.9em
(0.74Inl
~
---------~-----------~
,
~
CONNECTOR _I ;
BLOCK~-H~
0.79 em
10.31 In)
13.34em
15.2501nl
7.5em
12.951n
I
~
I
SIDE MOUNTING
"-5302
Figure 1
Backplane Mounting
VIEW FROM MODULE SIDE OF BACKPLANE
PROCESSOR
(HIGHEST PRIORITY LOCATION)
PROCESSOR OR OPTION 1
OPTION 3
OPTION 2
OPTION 4
OPTION 6
OPTION 7
(LOWEST PRIORITY LOCATIONI
OPTION 6
.-&./;......----
PREFERRED U)CATION FOR MMV"-A CORE MEMORY
Figure 2
H9270 Option Positions
426
4
H9270
A power supply for a DDV11-8, or a multiple-backplane system using
H9270 backplanes, should have the same voltage regulation and ripple specification as listed for the slngl~ H9270 backplane. However, It
will be necessary to calculate the actual power requirements, based
on Individual power requirements for mod,ules used In the system.
Backplane Power Connections - If the H780 power supply option Is
not used, perform the following steps to connect power to the H9270
backplane (Figure 3).
1. Select wire size. (14 gauge is recommended.) Consider load current and distance between the power supply and backplane.
2. For a standard system, connect the applicable wires to the H9270
connector block per Table 1.
3.
4.
For battery backup, remove the jumper between +5V and +58
and connect the applicable w1res to the H9270 connector block.
Connect the ground terminals at the power source.
It is recommended that the backplane frame/casting be electrically connected to the system/power supply ground.
The signal connections to the H9270 backplane are shown in Figure 4.
Table 1
H9270 Backplane Standard Power Connections
H9270 Connector Block
(To)
Power Source
(From)
+12V
+5V
GND
GND
-12V
+12V
+5V
+58
GND
GND
-12V
Factory
Connected
Factory
Connected
This voltage Is not required.
The connection Is available
for custom Interfaces.
427
H9270
A
@
+12V
+5V
+5VB
GND
GND
-12V
Figure 3
SIDE 2
H9270 Backplane Terminal Block (Pin Side View Shown)
RIBBON CABLE
\
ALIGNMENT
POSITION'
~
MATING CONNECTOR DEC PART No.12-11206-02
(3M PART No.3473-31
.
0
C
B
°g~8DCOK
BEVNT
7\~"""" BHAL T
GND
BPOK
SRUN
H9270 PRINTED
CIRCUIT BOARD
SIDE 2
Figure 4
H9270 Backplane Signal Connections (Pin Side View
Shown)
428
H9270
CONFIGURATION
Backplane and Module Configuration
lSI-11 bus systems can be classified as either single-backplane or
multiple-backplane systems. The electrical characteristics of each
system are different; hence, two sets of rules have been devised and
must be observed. These rules have their basis in bus loading and
power consumption.
Single Backplane Configuration Rules
1. The lSI-11 bus can support up to 20 ac loads, if unterminated at
the end.
2. The terminated bus can support up to 35 ac loads.
3. The bus can support up to 20 dc loads.
4. The amount of current drawn from each power supply should be
70 percent or less of the maximum rated output of the supply.
Multiple Backplane Configuration Rules
1. No more than three backplanes can be connected together.
2. Each backplane can have no more than 20 ac loads.
3. The total number of dc loads cannot be more than 20.
4. Both ends of the termination line must be terminated with 120
ohms, Le., the first backplane must have an impedance of 120
ohms, and the last backplane must have a termination of 120
ohms.
5. The cable connecting the first two backplanes (Le., the main box
and expander box 1) must be at least 60.96 cm (2 ft.) long. (A
182.88 cm (6 ft.) cable is recommended for ease of installation.)
6. The cable connecting the backplane of expander box 1 to the
backplane of expander box 2 must be at least 121.92 cm (4 ft.)
longer or shorter than the cable connecting the main box and
expander box 1 (a 304.80 cm (10ft.) cable is recommended for
ease of installation).
7. The combined length of both cables in a 3-backplane system
cannot exceed 487.68 cm (16 ft.).
8. The interbackplane cables must have a characteristic impedance
of 120 ohms.
9. The amount of current drawn from each power supply should be
70 percent or less of the maximum output of the supply.
429
H9270
To configure an LSI-11 bus system, take the following steps:
1. Choose the type of memory (MOS, PROM or combination) required for the specific application.
2. Select the CPU and memory combination most suited for the application.
3. Select additional memory, interface, and- peripheral options.
4. Count the total number of module positions.
5. Count the total number of bus positions.
6. Choose a backplane configuration that satisfies both the module
position requirement, the bus position requirement, and also provides sufficient expansion space.
7. Enter the option names in the backplane positions of the selected
configuration.
430
H9273-A
H9273·A BACKPLANE
GENERAL
The H9273-A backplane logic assembly consists of a 9 x 4 backplane
(nine ro~s of four slots) and a card frame assembly.
DESCRIPTION
The H9273-A backplane logic assembly is shown in Figure 1. Power
and signals are supplied to the backplane to conncectors J7 and Ja.
These connectors are shown in Figures 1, 2· and 3. Connectors J9
(GND) and J10 (-12V) are also shown in Figure 2.
Figure 1
H9273-A Backplane Logic Assembly
J7
JS
(])1
o
2
S 3
(]) 4
GND +5VDC
+5VDC
S 6
+5VDCIB)
(]) 7
GND +5VDC
o
+5VDC
S
FIG.
4·7
+12 VDC
GND +12VDC
o
5
~
+12 VDCIS)
Figure 2
J9
GND
-12V
H9273-A Power Connections
431
H9273-A
8POK H
A8'
8R' ·B
EVENT L
,
J8
2
LTC
SRUN L
AF'
(ROW')
GNO
GNO
BA20A2
+5VOC
AP' - - - B H A L T L
BA'
Figure 3
BOCOK H
H9273-A Signal Connections
The H9273-A backplane is designed to accept both double-height and
quad-height modules with the .exception of the MMV11-A core memory module. The backplane structure is unique in that it provides two
distinct buses: the LSI-11 bus signals (slots A and B) and the CD bus
(slots C and D). The connectors that make up this backplane are
arranged in nine rows (Figure 4). Each connector has two slots, each
of which contains 36 pins, 18 on either side of the slot.
The connectors designated "Connector 1" in Figure 4 are wired according to the LSI-11 bus specifications. Slots A and B carry the LSI11 bus signals and are termed the LSI-11 bus slots. The connectors
designated "Connector 2" are wired for +5 V and ground, and have no
connections to the LSI-11 bus; instead, C- and D-slot pins on side 2 of
each row are connected to the C- and D-slot pins on side 1 in the next
lower row. Details of the CD interconnection scheme are depicted in
Figure 5.
CONFIGURATION
The H9273-A backplane logic assembly is designed to mount into a
BA 11-N mounting box or equivalent. Refer to the BA 11-N mounting
box description for more information.
NOTE
Connector block pins do not extend beyond the
H9273-A printed circuit etch card, thus eliminating
the possibility of backplane wire-wrapping.
432
H9273·A
Three jumpers (W1, W2, and W3) are shown in Figure' 4. Jumper W1
enables the line-time clock when inserted and disables it when removed.
NOTE'
Only one BA 11-N mounting box in any system may
have the line-time clock enabled.
When inserted, jumpers W2 and W3 allow the LSI-11 quad-height
CPU to run in row 1. Jumpers W2 and W3 are removed when the
backplane is used as an expansion backplane in a system.
CONNECTOR 2
CONNECTOR 1
, f
SLOTA
SLOTB
SLOTC
~
~
W1
W2
SLOT 0
~
W3
ROW 1
ROW2
ROW3
ROW4
ROW
a
Rowe
ROW 7
Rowe
ROW9
VIEW IS FROM MODULE SIDE OF CONNECTORS.
MA·0740
Figure 4
H9273-A Backplane Connectors
433
H9273·A
COl
C02
~1
+5V
Bd ~
GNO
COB
~ ~2
Bl
>--.............
[
~
W
001
02
01
02
El
0
E2
El
E2
F2
Fl
F2
HOI
H2
HI
H2
JJ,
J2
Jl
J2
Kl
r-- --0
K2
Kl
K2
L __
-'-d
L2
L1
L2
~1
M2
Ml
M2
N,,1
N2
Nl
N2
PI
0
P2
PI
P2
0
0-,51
51
.........
'.
""
L
..........
l!
I'
0
t-'-a
0
0
)1.
0
0
I
0
I)
0
0
0
Rl
0
R2
Rl
R2
S2
Sl
S2
~
Tl-
~1
U2
Ul
U2
Vd
V2
VI
V2
~
~
~ f--
AJ.., Ai
Bd
B2
81
'bl
~
~
CJ
001
02
01
02
Ed
E2
El
E2
I
\)
R
0
0
0-
I--
!l
bJL
002
AJ..,~
I
}
-
0---
82
......
'"
h
I I
0-
-
0
9
0
~
OOB
-
r--
(
..,
i
r
"-...0
51
009
51
0
I'
51
'-0
I'
0
0
0
Fd
F2
Fl
F2
HoI
H2
HI
H2
)1
JJ,
J2
Jl
J2
(
- --0Kl
K2
Kl
K2
)
-!:;1
L2
Ll
L2
Ml
0
M2
Ml
M2
N,,1
N2
Nl
N2
P~
P2
PI
P2
Rl
0
R2
Rl
R2
Sd
S2
Sl
S2
'---
!l
0
S~
W3
I
t--o
\
L
0
001
.... -
.............
W
FJ
W2
....,
B2
'b
C09
r--
~r-
'--
~2
~1
T~
~1
U2
Ul
U2
Vd
V2
VI
V2
0
0
0
0
0
I
0
0
0
)
51
p~
~L
0
I......-
10
'--
~
0
0
~
~
VIEW FROM PIN SIDE
FEATURES
• ALL PINS Al CONNECT TO PINS Cl IN
THE NEXT LOWEST SLOT.
• ALL PINS A2 CONNECT TO +5 VOL TS.
• ALL PINS T2 OF S.1-0T C ARE CON
NECTEO TO PIN T2 OF SLOT 0 IN THE
NEXT LOWER SLOT
Figure 5
• ALL PINS C2 AND PINS T1 ARE GROUND
• JUMPER W2 IS CONNECTED ACROSS
PINS Kl AND L1 IN SLOT C ONLY.
• JUMPER W3 IS CONNECTED ACROSS
PINSKI AND LlINSLOTOONLY.
C-D Bus Interconnection'Scheme
434
MR e 1'64
H9281
H9281 BACKPLANE
GENERAL
The H9281 backplane Is designed to accept double-height modules
only. Six options of the H9281 backplane .Iet the user configure compact LSI-11 bus systems that most efficiently use available system
space.
DESCRIPTION
The H9281 2-slot backplane Is available In the following six options:
Backplane
Option
Designation
H9281-AA
H9281-AB
H9281-AC
H9281-BA
H9281-BB
H9281-BC
Description
4-module backplane
8-module backplane
12-module backplane
4-module backplane and card cage assembly
8-module backplane and card cage assembly
12-module backplane and card cage assembly
The following list presents quad-height options that are too large to be
Installed In an H9281 backplane.
Backplane
Option
Module
Description
DeSignation Number
4-channeI12-blt 01 A converter
AAV11-A
A6001
16-channeI12-blt AID converter
ADV11-A
A0121
DRV11-B
M7950
DMA Interface
M7951
DUV11-A
Line Interface
Asynchronous multiplexer
DZV11-A
M7957
KWV11-A
M7952
Programmable line-time clock
MMV11-A
H223, G653 Core memory
16K MOS memory
MSV11-CD M7955-YO
RL01 controller
RLV11
M8013
M8014
BDV11
Bootstrap, terminator
M8012
CONFIGURATION
Mounting dimensions for H9281 backplanes are shown In Figures 1
and 2. The H9281 backplanes can be mounted In any plane. The
enclosure In which the backplane is mounted, available system space,
and cooling air flow will determine an acceptable backplane position
In a particular system.
435
H9281
!,~:t-f
r
0
7.82
(3.
H9281·AA
em
4.8&
11.9& Inl
1.83 em
(0.72Inl
4.&2 em
11.78 inl
l
I
I
I
I
.L~
I
Ill.
MOUNTING
r
tI
_J
HOLES (4)
0.36 em
(0.14 in I
1.27
(O.6inl
I
H9281·AB
1&.24 em
(6.0Inl
MOUNTING
14'61em~' ~~~:61
I
(&.7& inl
-r-----.----!.. , - - - - - - - - -
---..j
--,1
I~,
"F-Li.,!~-----'TT""""----~4JJ.,
.0.38 em
(0.1& inl
2.Jem
7.:» em
(2.9inl
H9281·AC
20.32 em
(8.0 inl
-r--"
7.:» em
"lrr.'
U....-----..1L.-------l,. .
~;11: 1
MOUNTING
HOLES (61
0.38 em
(0.14 in)
MR·0469
Figure 1
H9281-AA;-AB;-AC Mounting Dimensions
436
H9281
MOUNTING
DIMENSION
MODEL
".Bem
14.57 inl
A
ASSEMBLY
LENGTH
B
H9281·BA
B.BBem
12.71nl
7.62em
13.01nl
H9281·88
11.94cm
14.7 inl
1&.24cm
IB.Oinl
H9281·Be
17.02cm
16.7 inl
2O.32cm
IB.O inl
27. em
110.B inl
MOUNTING
HOLES I1BI
0.64 em
10.25 in 1
14.B1 em
1&.7& inl
MR·0460
Figure 2
H9281-BA;-BB;-BC Mounting Dimensions
437
H9281
Connecting System Power
Seven screw terminals are provided on the slot 1 end of the backplane
for power connections. Connect system power (and optional battery
backup power) as shown in Figure 3. Power wiring should be done
with a wire gauge appropriate for the total power requirements for
options installed In the backplane. The recommended wire size for
H9281-AC and -BC backplanes is 12 gauge. 14 gauge is sufficient for
the other H9281 models.
SYSTEM {+12V
POWER
+5 V
SOURCE
GND------.
-----------::+0
BATTERY {+5 V
BACKUP
POWER-i'
G N D - - - - - - -.....
SOURCE
(OPTIONAL)
+12 V
---------"-+0
+12B
MR-0461
Figure 3
H9281 Power Connections
Select a power supply that will meet LSI-11 system power specifications and supply sufficient current for the options in the system. The
H780 power supply Is recommended.
Connecting Externally Generated Bus Signals
Externally generated bus signals can be connected to the H9281 backpanel via connector J2. These signals include power sequence signals
BPOK H. BOCOK H. BHALT Land BEVNT L. In addition. the processor-generated SRUN l signal is available via J2 for driving a RUN
indicator circuit. J2 connector pins are fully compatible with the H780
model series power supply or the KPV11-A power-failliine-time clock.
Signal connector J2 pinning and signal names are identified in Figure
4.
438
H9281
BDCOK H
NOT {CS3 l
USED
----+-0'" "'o--!I---- BHAlT l
----+-O::cr-I
: : ' - - - - - ( N O T CONNECTED I
Cl3 l
~
KEY (NO P I N I - - - - - - : .
BEVNT l - - - - + - - o O
""O~-+----GND
::;
&RUN l
...,D-II----BPOK H
MA·0462
Figure 4
H9281 Signal Connections (J2)
Device Priority
All LSI-11 bus backplanes are priority structured. Daisy-chained grant
signals for DMA and interrupt requests propagate away from the
processor from the first (highest priority device) to successively lower
priority devices. Processor module locations and device (option)
priorities are shown in Figure 5.
Bus Terminations
Backplane models H9281-AB,· -BB, -AC, and -Be include 120 {} bus
termination resistors at the electrical end of the bus; therefore, it is not
necessary to install a separate 120 {} bus terminator module in these
backplanes.
439
H9281
POWER CONNECTOR
BLOCK (J1)
>
>
N
III
+
+
j
o
III
+
!
III
C
Z
Cl
>
N
~
j
j
!
0 0
0
o
I
j
III
N
+"j
0 0
SIGNAL
CONNECTOR
PINS (J21
r-
-,
-L._-'
I
H9281-AA. -BA
4-SLOT BACKPLANE
1 - PROCESSOR MODULE
2 - OPTION 1 (HIGHEST PRIORITY)
I
3-OPTION 2
I
4 - OPTION 3 (LOWEST PRIORITY)
I
~l_ _ _ _ _ _ _J LROWNUMBER
A
o
B +---SLOT LETTER
0 0 0 0 0 0
,--,
L._-'
t -_ _ _ _ _ _-+_ _ _ _ _ _-I1 - PROCESSOR MODULE
t - - - - - - - - + - - - - - - - I 2 - OPTION 1 (HIGHEST PRIORITY)
3-OPTION 2
OPTION 3
H9281-AB. -BB
&-SLOT BACKPLANE
t---------+---------l 4 _
5'- OPTION 4
r-------------r-----------~ 6-0PTION 5
t--------+-------I
7
-OPTION 6
8 - OPTION 7 (LOWEST PRIORITY)
120 OHM BUS TERMINATION RESISTORS
o 0 0 0 o 0 0
r-,
L.._-'
I
1· PROGESSOR MODULE
2 - OPTION 1 (HIGHEST PRIORITY)
I
I
3 - OPTION 2
I
4-0PTION 3
5-0PTION 4
H9281-AC. -BC
12-SLOT BACKPLANE
6-0PTION 5
I
7-0PTION 6
I
8-0PTION 7
9-0PTION 8
I
10· OPTION 9
I
11 - OPTION 10
I
12 - OPTION 11 (LOWEST PRIORITY)
I
~ ~~
"'V
120 OHM BUS TERMINATION RESISTORS
Figure 5
MR-0463
H9281 Option and Connector Locations (Module Side)
440
H9800-A
H9800-A CABINET
GENERAL
The H9800-A is a low-profile systems desk equipped with a walnutgrained plastic laminate top and color-coordinated to fit into modern
office decor. The unit is equipped with six ball casters as standard
equipment for easy positioning on carpeted surfaces. Also included is
a 115 Vac power distribution panel.
9449-2 . A01 69
Figure 1
SPECIFICATIONS
Dimensions
Width
Depth
Height
Shipping weight
Module enclosure
Mounting space
Usable height
Usable depth
(variable)
Color
H9800-A Cabinet
121.92 cm (48 in.)
81.28 cm (32 in.)
70.1 cm (27.6 In.)
45.36 kg (100 lb.)
Standard 48.3 cm (19 in.) EIA
53.3 cm (21 in.)
73.7 cm (29 in.)
Walnut-grained top surface, beige side
panels, chrome trim
DESCRIPTION
The H9800-A is constructed of quality materials including a top constructed of 24.9 kg (55 lb.) particle board with a dark-walnut plastic
laminate. The "module" itself is constructed of 11 and 18 gauge steel
with a maximum loading capacity of 181.44 kg (400 lb.).
441
H9800-A
The H9800-A consists of a left-mounted rack enclosure offering 53.3
cm (21 in.) of usable height and 73.7 cm (29 in.) of usable depth In a
standard 48.3 cm (19 in.) EIA mount format. The right side offers knee
space, a modesty panel, and a convenient work surface ideat for using
terminals or typewriters.
442
IBV11-A
IBV11-A INSTRUMENT BUS INTERFACE
GENERAL
The IBV11-A is an option that Interfaces the LSI-11 bus with the Instrument bus as described In IEEE Standard 488-1975, "Digital Interface
for Programmable Instrumentation." An IBV11-A can be Installed in
any LSI-11 system: The IBV11-A consists of an M7954 interface module and a BN11A-04 cable for connecting the first Instrument. Additional Instruments may be connected using a BN01A cable.
The IBV11-A makes an LSI-11 based programmable Instrument system possi ble.
FEATURES
• PDP-11 software-compatible
• 40-Kbyte/sec maximum transfer capability of hardware
• Board-mounted, user-configured switches allow easy device
(register address) and Interrupt vector address selection
• Software support available under FORTRAN IV
• 5-Kbyte/sec transfer rate under FORTRAN
• System hardware-compatible with the LSI-11 component system
• Instrument bus compatible with the IEEE 488-1975 standard
• The module supports cable lengths up to 20 m (65.6 ft) total
• 15 devices (maximum) can connect to the bus
SPECIFICATIONS
Identification
M7954
Size
Double
Power
+5.0 Vdc ±5% at 0.8 A
Bus Loads
AC
DC
1.8
1
The IBV11-A, when connected to the LSI-11, will meet the following
subsets of IEEE Standard 488-1975:
SH1
AH1
TS
TE5
LE3
SR1
RL1
PP2
DC1
C1
C2
C3
C4
443
IBV11-A
This module is designed to be the only controller on the IEEE bus.
Therefore, it will not respond to another controller on the bus that
issues either a parallel poll configure command or a parallel poll control signal.
DESCRIPTION
General
The functional logic blocks that make up the IBV11-A are shown in
Figure 1. LSI-11 software controls and communicates with the IBV11A via programmed I/O transfers and interrupts. Programmed I/O
transfers are made possible by assigning unique device addresses
(also called "bus addresses") to the IBS and IBD registers.
LSI-11 Bus Interface
LSI-11 bus address selection, interrupt vector address generation,
and bus data driver/receiver (transceiver) functions are provided by
transceiver integrated circuits (DC005). Each integrated circuit provides the interface for four BDAL bus lines; thus, four transceivers
comprise the 16-line BDAL (0:15) L LSI-11 bus interface.
Bit 1 of the least significant octal digit (BDAL 0) selects the IBS or IBD
register. This is a byte pOinter and It Is significant for DATOB and
DATIOB bus cycles only. Register address selection is actually performed in the LSI-11 bus protocol and register selection circuit
(DC004); the receiver integrated circuit (DC005) simply routes the received low-order three address bits [DA (2:0)] to that function.
All I/O transfers over the LSI-11 bus are done according to a strict
protocol. One bus protocol integrated circuit (DC004) performs both
this function and the register address selection previously discussed.
When an active ADDReSS MATCH signal is present and BSYNC L
signal is asserted, the bus protocol integrated circuit is enabled to
complete its register selection function. BWTBT L, BDOUT L, and
BDIN L bus Signals are decoded in the integrated circuit, as appropriate, to produce the LOAD IBS LOW BYTE, SELECT IBS, LOAD IBD
LOW BYTE, and RECEIVE internal control signals from the IBV11-A
logic functions. The integrated circuit also asserts BRPLY L as required during the I/O sequence to complete the programmed transfer.
444
DA <7:0>
~
~~~~~ ~toi~t~~
a
REGISTER
SELECTION
( DC004)
SELECT •
IBS
LOAD IBD,
LOW BYTE
INTR _
CTL
BS7 L
£
:::i
IL---J\.
~AL<15:~
LSI-II BUS
DEVICE
ADDRESS
SELECTION
INTERRUPT
VECTDR
GENERATION
DATA IIO
INTERFACE
SRQ
IBC
n
~:~ TKRIl~
ORj
DA <15:00>
~
VECTOR
CONTROL
CONTROL
a
...
z
HANDSHAKE
INTERFACE
~
~
~
J
16
REGISTER
I
MULTIPLEXER Lo-!l~6...._
-_
--'
1- .
I" NDAC L ,
-+-_----,
L
1
SELECT
IBS
15141312 II 109 B
IBD
7-6 5 4 3 2 1 0
S E~ I ~ ~ 5 II WWWWWWWW
il 2 ~ e§ 8 S §
I
16
>:
LOAD IBD
LOW BYTE
LSI-II BUS ,. INTR CTL
INTERRUPT
INTERFACE
DA <7:0>
BINIT L
BDIN L
(DC003)
~
1 RRRRRRRR
iii·
I
~
INST;~:ENT
~
~v
•
f--ill--h-.
I
~
~'"
a:~
BIAKO L
~!~
I
~
~II\
,.
11111111
INTE:RUPT
tl
BIRO
BIAKIL L
~
ENABLE
~
(DC005)
r
o
LOAD IBS
LOW BYTE
f-- INIT
Figure 1
IBV~ 1-A Functional
Block Diagram
-III
<
~
~
••
IBV11-A
Interrupts are generated by'one interrupt integrated circuit (DC003).
Four interrupt vectors can be generated by this bus interrupt interface
function. A 5-bit vector switch allows the user to select the interrupt
vector for the IBV11-A module. The IBV11-A base interrupt vector is
factory-configured for 420. The base interrupt vector can range from
300 to 760; however, the vector interrupt must not conflict with other
bus devices, or with those interrupts reserved for system vectors.
Interrupt Vector
-000420
000424
000430
000434
Interrupt Source
Error
Service request
Command and talker
Listener
These interrupt vectors allow the IBV11-A to generate interrupts that
can most efficiently be serviced by four separate service routines.
Interrupt and vector control logic on the IBV11-A module generates
the INTR CTL signals that initiate the ,interrupts. Inputs for this logic
function include the interrupt enable (IE) bit (stored in the control
buffer), command or talker (CMD or TKR) and listener (LNR) ready
flags, error (ERR) status ,from the error detection logic, and the device
service request (instrument bus control signal).
Instrument Bus Control
The control buffer is an 8-bit register that functions as the low byte of
the IBS register. Bits stored in this register control generation of interrupts, instrument bus clear, and instrument bus control and status
logic. Setting the IBC bit actually triggers a one-shot producing a 125
J.l.S pulse that clears the instrument bus. Take control sync and
handshake contro-I logic function together with instrument bus control
and handshake interface logic to communicate with instruments on
the bus according to instrument bus protocol. Output transactions
with the low byte of the IBD register result in data being stored in the 8bit command .and talker output buffer. Instrument bus line drivers gate
this byte onto the instrument bus when th,e IBV11-A Is an active talker,
or when it is an active controller.
Instrument Bus Interface
The IBV11-A interfaces with the instrument bus -via four integrated
circuits, type MC3441. These integrated circuits are bus transceivers,
each containing four bus drivers, four bus receivers, and bus terminations that comply with instrument bus specifications.
446
IBV11-A
CONFIGURATION
General
The IBV11-A option can be installed in any LSI-11 bus to interface
various instruments via an "interrupt bus." The instrument bus is defined in the IEEE Standard 488-1975, "Digital Interface for Programmable Instrumentation." Any instruments designed to interface with the
bus defined in that standard can be interfaced to the LSI-11 system via
the IBV11-A.
The following paragraphs contain only the basic information necessary for configuring device register addresses and vector interrupts,
general installation and interface to the instrument bus, and basic
programming (e.g., device register functions).
Device Address
Device address switches provide a convenient means for the user to
configure the IBV11-A's register addresses. Only switches
corresponding to BDAL lines (3:12) are provided. By PDP-11 convention, the upper 4K address space (bank 7) is normally reserved for
peripheral devices, such as the IBV11-A. The processor module asserts BBS7 L whenever a bank 7 address [BDAL (13:15) L is asserted]
is placed on the bus. Thus, BBS7 L must be asserted to enable an
"address match" output from the address selection function. Any address ranging from 16000X to 17777X can be configured that does not
conflict with other device addresses within the system; the X in the
address represents register and byte selection within the module.
Each IBV11-A module is factory-configured for a standard device register address (160150) and interrupt vector (420). Switches S 1
(interrupt vector) and S2 (device register address) configure the module.. A summary of register addressing and interrupt vectors is provided in Figures 2 and 3. Observe that the IBD register address is always
the IBS address plus 2. Similarly, only the error interrupt vector is
configured. The remaining three vectors are permanently assigned
sequential addresses in address increments of four as shown in Table
1.
447
IBV11-A
Table 1
Standard Assignments
Description
Mnemonic
Readl
Write
Registers
Control/Status
Data
IBS
IBD
A/W
A/W
Vectors
Error
Service
Command and Talker
Listener
EA2, EA1
SAQ
CMD, TKA
LNR
First
Module
Address
160150
160152
420
424
430
434
Switches 81 and 82 are located on the IBV11-A module as shown in
Figure 4. 81 and 82 are switch assemblies, each containing several
individual switches. The individual switches indicated in Figures 2 and
3 are clearly marked on the 81 and S2 assemblies. The ON and OFF
positions are also clearly marked.
Interrupt Vectors
The IBV11-A is capable of generating four separate interrupt requests;
each have separate interrupt vectors and normally would have separate service routines. Interrupts can be requested only when the IBS IE
(interrupt enable) bit is set. Interrupt requests are priority structured in
the IBV11-A. A summary of the four types is provided below.
Priority
Vector
Associated
IBSBit
Cause of Interrupt
Highest
OOOXNNOO
ER2, ER1
Error condition.
Second
highest
OOOXNN04
SRQ
A device connected to the
instrument bus is requesting service.
Third
highest
OOOXNN1G
TKR,CMD
The IBV11-A is an active
talker and is ready for the
processor to output a byte
to the low byte of the ISO
register. (The IBV11-A will
normally then transmit the
448
IBV11-A
byte over the installation
bus to the active listener(s).)
Lowest
OOOXNN14
LNR
The IBV11-A Is an active
listener and has a data
byte to be read by the
processor.
NOTES
1. X = User-configured interrupt vector octal digit.
2. N = User-configured interrupt vector binary bits.
3. Associated ISS bits shown, when set, produce interrupt requests
if the IE bit is set.
IBS REGISTER ADDRESS FORMAT
15
14
13
12
,,,~~:l':,~~ :~~o~~l,1i
52 INDIVIDUAL
SWITCH NUMBERS
I
II
10
09
08
07
06
05
04
03
02
IIIIIIIII
I
01
00
NORMALLY 0
(RESERVED FOR
FUTURE USE I
10
NOTES:
1. OFF' Logical 0; ON. Logical I
2. Only the IBS REGISTER ADDRESS I. configured via S2. The IBD REGISTER ADDRESS alway. equal. the
IBS REGISTER ADDRESS +2.
Figure 2
'S
'4
'3
,,·4 •• 7
Register Addresses
'2
I I I
I
STANDARD VECTOR ADDRESS
CONFIGURATION (000420) ON
IIII
OFF
OFF
OFF
ON
l
o
I
o
,
INTERRUPT VECTOR
- ERROR
- SERVICE REOUEST
- COMMAND AND TALKER
• LISTENER
ON -DISABLE ERR'
,....JI..---I:_...L._...L._..I....._ _ _ _--I:......., I~~~~~~PTS
SI INDIVIDUAL
SWITCH NUMBERS L -_ _ _ _ _ _ _ _ _ _ _ _ _
NOTES:
1. OFF. Loglcol 0; ON ilLogical'
2. On I, 'he VECTOR ADDRESS bit. (8:4) ar. configured via SI. Bit. 3 and 2 are 18Vtt-A
hardwore -selected 'or the functions shown
3. 51-8 OFF" IBvtt-A Is the only system controller connected to the Instrument bus.
5t-8 ON" Another system controller Is connected to the inslrument bus.
Figure 3
Interrupt Vector
449
~
OFF' NORMAL
(ENABLE)
ERR'
INTERRUPTS
IBV11·A
20- PIN
INSTRUMENT BUS
CABLE CONNECTOR
o
Figure 4
IBV11-A Module Switch Locations
450
o
IBV11·A
Interrupt
Error
Service
Command and Talker
Listener
Preferred value range for "n"
Interrupt Vector
"n" (configured vector)
n+4
n + 108
n + 148
= 300 ~ n ~ 760
Registers
The IBV11-A communicates with devices connected to the instrument
bus under the control of the program being executed. All communication between the processor and the IBV11-A Is via the instrument bus
status (IBS) and instrument bus data (IBD) registers. The programmer
must be aware of the functional significance of each bit in both registers before any programs can be written that will control specific devices on the instrumer1t bus. In addition, the programmer must establish instrument (device) addresses, and conform to the programming
rules specified for each instrument connected to the instrument bus.
See Figure 5 for a d~scription ofthe IEEE bus.
The instrument bus status (IBS) register is similar in function to other
device control/status register (eSRs). The instrument bus data (IBD)
register is a 16-bit register that contains eight read/write data bits in
the low byte and eight read-only bits in the high byte. The eight readonly bits allow the program to read the logical state of the control and
management signals of the instrument bus.
The IBS register provides the means for controlling the instrument bus
control and management signals, and IBV11-A functions relative to
the LSI-11 bus. The low byte of the IBD register, on the other hand, is
used for passing commands to devices connected to the bus, and for
transmitting and receiving data between the processor and talker and
listener devices. In addition, the high byte of the IBD register allows for
processor monitoring of all Instrument bus signal (control) lines. IBS
and IBD registers are shown in Figure 6 and described in Tables 2 and
3.
451
IBV11-A
INSTRUMENT BUS
SIGNAL LINES
.II
DEVICE A
ttttt ttt
~
~
-
.A
DEVICE B
~
-
.A
DEVICE C
~
-
.A
DEVICE 0
...
--
-
Figure 5
-
} DID <1: 8> }
~~~~
DAV
} MESSAGE
HANDSHAKING
IFC
ATN
SRC
REN
EOI
}
GENERAL
INTERFACE
MANAGEMENT
Instrument Bus Signal Lines
452
8- LINE DATA BUS
)
CONTROL
SIGNAL
LINES (8)
IBV11-A
INSTRUMENT BUS STATUS (IBS)
INSTRUMENT BUS DATA (IBD)
Figure 6
Table 2
Register Word Format
Instrument Bus Status Word Format
Bit: 15
Name: SRO
Description: (Service Request)
Monitors the state of the instrument bus service request line at all
times. Set when the IB SRO line is low. Will cause an interrupt when
both SRO and the interrupt enable bits are set. When the ER1-inhibit
switch is set, this bit will be written by any type of instruction that writes
into the 18S. Read/write.
Bit: 14
Name: ER2
Description: (Error 2)
Asserted if the IB reports that CAC is true when the IBV11-A tries to
send a data or command byte. This condition will exist when there is
no active listener or command acceptor on the lB. An ERR interrupt
occurs when both the ER2 and the interrupt· enable bits are set.
Cleared by clearing both TON the TCS. Read-only.
Bit: 13
Name: ER1
Description: (Error 1)
Unless inhibited by the ER1-inhibit switch, this bit is asserted whenever a conflict occurs between the IB ATN, IFC, or REN lines and their
IBV11-A control hardware, i.e., if one or more of these control lines is
asserted when it should not be asserted or not asserted when it should
be asserted. When asserted, the IBV11-A will not assert the ATN line
even though the TCS bit remains set. An ERR interrupt occurs when
both the ER1 and the interrupt enable bits are set. This condition can
be cleared only by clearing the cause. Read-only.
Bit: 12
Name: Not used
Description: Always read as a zero. Read-only.
Bit: 11
Name: Not used
Description: Always read as a zero. Read-only.
453
IBV11-A
Bit: 10
Name: CMD
Description: (Command Done)
Set when the IBV11-A is ready to send a command byte; set by a
successsful TCS to indicate that ATN was asserted and the first command byte may be issued. Also set by DAC when a command has
been completely accepted. A CMD/TKR interrupt occurs when both
the CMD and the interrupt enable bits are set. This bit is cleared by
INIT, received IFC, writing a command into the IBD low byte, or by
turning TCS off. Read-only.
Bit: 9
Name: . TKR
Description: (Talker Ready)
Set when the IBV11-A is ready to send a data byte; set when TON is on
while TCS is turned off, or by DAC when TON is on. A CMD/TKR
interrupt occurs when both the TKR and the interrupt enable bits are
set. Cleared by INIT, received IFC, writing a data byte into the IBD low
byte, or by turning TON off or TCS on. Read-only.
B~8
Name: LNR
Description: (Listener Ready)
Set when the IBV11-A has a data or command byte ready for reading
from the IBD low byte; set by DAV when LON is on. An LNR interrupt
occurs when both the LNR and the interrupt enable bits are set.
Cleared by reading the IBD Ibw byte if ACC is off or by clearing the IBD
low byte if ACC is on. Also cleared when LON is turned off and by INIT
or received IFC. Read-only.
Bit: 7
Name: ACC
Description: (Accept Data)
Set and cleared under program control. When clear, reading the IBD
will automatically clear the LNR and assert DAC. When set, the programmer must write 0 to the IBD low byte in order to clear the LNR bit
and assert DAC. When the TCS, LON, and TON bits are all off (clear),
setting this bit will assert NRFD. Cleared by INIT or received IFe.
Read/write.
Bit: 6
Name: IE
Description: (Interrupt Enable)
Set and cleared under program control to enable and disable all interrupts. Cleared by INIT. Read/write.
Bit: 5
Name: TON
Description: (Talker On)
Set and cleared under program control to enable and disable the
talker function. Cleared by INIT or received IFC. Read/write.
454
IBV11-A
B~4
Name: LON
Description: (Listener On)
Set and cleared under program control to enable and disable the
listener function. Cleared by INIT or received IFC. Read/write.
B~3
N.~e: IBC
Description: (Interface Bus Clear)
Set under program control to cause the IFC line to be asserted for
about 125 ~sec. TCS will automatically be asserted at the end of IBC
(out-going IFC). Cleared by INIT. Read/write.
Bit: 2
Name: REM
Description: (Remote On)
S.et and cleared under program control to assert and unassert the
REN line. Cleared by INIT or received IFC. Read/write.
Bit: 1
Name: EOP
Description: (End of Poll)
Set and cleared under program control to assert and unassert the EOl
line. Cleared by INIT or received IFC. Read/write.
Bit: 0
Name: TCS
Description: (Take Control Synchronously)
Set and cleared under program control to take control synchronously,
or to unassert ATN. Setting TCS will cause NRFD to be asserted for at
- least 500 ns before DAV is checked. ATN is then asserted when DAV is
unasserted; NRFD is unasserted and CMD is set no sooner than 500
ns after ATN is asserted. Cleared by INIT or received IFC. Read/write.
Table 3
Instrument Bus Data Word Format
Bit: 15
·Name: EOI
Function: (End or Identify)
Monitors the IB EOIline at all times. Set when the IB EOIline is low.
Read-only.
Bit: 14
Name: ATN
Function: (Attention)
Monitors the IB ATN line at all times. Set when the IB ATN line is low.
Read-only.
Bit: 13
Name: IFC
Function: (Interface Clear)
Monitors the IB IFC line at all times. Set when the IB IFC line Is low.
Read-only.
455
IBV11-A
Bit: 12
Name: REN
Function: (Remote Enable)
Monitors the IB REN line at all times. Set when the IB REN line is low.
Read-only.
Bit: 11
Name: SRQ
Function: (Service Request)
Monitors the state of the instrument bus service request line at all
times. Set when the IB SRQ line is low. Will cause an interrupt when
both SRQ and the interrupt enable bits are set. Read-only.
Name: RFO
Bit: 10
Function: (Ready for Data)
Monitors the IB NRFO line at all times. Set when the IB NRFO line is
high. Read-only.
Bit: 9
Name: OAV
Function: (Data Valid)
Monitors the IB DAV line at all times. Set when the IB OAV line is low.
Read-only.
Bit: 8
Name: OAC
Function: (Data Accepted)
Monitors the IB NOAC line at all times. Set when the IB NOAC line is
high. Read-only.
Bit: 7-0
Name: 0108-0101
Function: IB Data I/O lines
Reading the IBD low byte picks up unlatched data directly from the IB
010 lines. Data on the IB 010 lines may change if the LNR bit is not set.
Generally, the only reason to read the 010 lines when LNR is not set is
when a parallel poll response is expected. Writing data to the IB 010
lines is permitted when TON is set and OAV is clear, or when TCS and
ATN are set and OAV is clear. Otherwise, writing into the IBO low byte
will have no effect on the 010 lines but will set OAC if both ACC and
LNR are set. Read/write.
The data and command output buffer is cleared by INIT or received
IFC.
Connecting the External Equipment
Connection from the IBV11-A to the first device on the instrument bus
is via a type BN11A cable (supplied with the M7954 module), as shown
in Figure 7. One end is terminated with a 20-pin connector that mates
with the 20-pin connector on the IBV11-A module; the other end is
terminated with a 24-pin "double-ended" connector that conforms to
456
IBV11-A
the IEEE 488 1975 standard; the cable can be connected to any device
conforming to that standard. The double-ended connector contains a
male 24-pin and a female 24-pin connector in the same connector
housing. This allows for "linear" and "star" connections to instruments
connected to the instrument bus, as shown in Figure 8. One BN11A is
included in the IBV11-A option.
The linear arrangement shown in the figure includes five devices (or
instruments), A through E. There is no particular significance to the
sequence shown, or the electrical position along the instrument bus.
Unlike the LSI-11 bus, the position along the bus does not structure
device priority in the system.
The star arrangement shown in the figure allows five devices to be
connected by stacking instrument cable connectors on the BN11A's
double-ended connector. Double-ended connectors on instrument
bus cables will normally include captive locking screws on each connector assembly (two each), allowing stacked connectors to be se.
cured together in a single assembly.
/
k-/PIN X
'1,',
PI!w~'
PIN A
Figure 7
BN11A Instrument Bus Cable
457
IBV11-A
(A) LINEAR ARRANGEMENT
I
DEVICE
E
u
I
BNItA CABLE
(B) STAR ARRANGEMENT
Figure 8
Linear and Star Configurations
The BN11A cable connector pin signal assignments are listed In Table
4 for each connector. One BN11A cable Is required for each IBV11-A
module in a system.
Optional Cables
1. Connect M7954 module to first Instrument:
BN11A-02
2 m (78.7 in.)
BN11 A-04
4 m (157.5 In.)
2. Connect instrument to Instrument:
BN01 A-01
1 m (39.4 In.)
BN01 A-02
2 m (78.7 in.)
BN01A-04
4m (157.5 In.)
458
IBV11-A
Table 4
IBV11-A
Connector Pin
U
S
P
M
R
T
V
X
B
J
F
W
K
H
E
C
D
N
A
L
w
BN11 A Connector Pin Assignments
Signal
Name
0101
0102
0103
0104
EOI
OAV
NRFD
NOAC
IFC
SRO
ATN
(SHIELD)
0105
0106
0107
0108
REN
GND (OAV GNO)
GNO (NRFO GNO)
GND (NOAC GND)
GNO (IFC GNO)
GND (SRO GNO)
GNO (ATN GNO)
GND(LOGIC)
Instrument Bus
Connector Pin
1
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PROGRAMMING
Example 1-IBV11-A to Listener Device
This programming example illustrates how the IBV11-A communicates with a listener device. Standard device and vector addresses are
used, as shown in Figures 2 and 3. Once the program is started, and
after pOinters have been initialized and the IBV11-A has taken control
synchronously, it communicates with the IBV11-A via an interruptdriven service routine. No "background" program is used; the program simply waits until another interrupt occurs.
459
IBV11-A
Communication with the listener device includes the transmission of
two command bytes (read as words from a message buffer), followed
by 24 message bytes that program device functions. After all message
bytes have been transmitted, the program halts (displays HALT PC
address = 1066).
A program flowchart for this example is shown in Figure 9; a symbolic
listing is shown in Figure 10.
NO
NO
NO
11·5231
Figure 9
Communicating with a Listener Device (Program Flowchart)
460
IBV11-A
ADDRESS
C' /~. ::::::.J
OCTAL
CODE
ASSEMBLER SYNTAX
INTR RETURN ,!1D[IRESS
f'SW
(. ( .~ .:,' (! .~:::: .:~
001020
000200
001000
001002
001004
001006
001010
00.1012
001014
012706
000500
012700
002000
012737
000110
160150
START: MOV i500,R6
001016
001020
001022
001024
001026
001030
001032
001034
001036
001040
000777
020027
002004
100006
012737
000105
160150
012037
160152
000002
WAIT :
001042
001044
001046
001050
001052
001054
001056
001060
001062
001064
020027
002004
003003
012737
000144
160150
020027
002064
100364
000000
20$:
(.1', 'I
COMi"iENTS
SET UP STACK POINTER
MOV 4J:2000,RO
fW IS MSG BUFFER ADDRESS
i"'iOV :fI:l10,160150
TAI(E CONTROL
SYNCHRONOUSLY TO BECOME
CONTROLLER-IN-CHARGE
BR
CMF' RO,:fI:2004
WAIT FOR INTERRUPT
MORE COMMANDS TO BE SENT1
IF NO,GO TO 20$
IF YES,SET IE,REM,AND
rcs BITS OF [BS REG TO
; ACTIVATE CONTROLLER
r·10V (RC> >+,160152; SEND MSG TO IB
BPL. 20$
MOV :11:105,160150
SEND:
RTI
eMP
RO~:H:2004
BGT ~~O$
MOV :11=:1.44,160:1.50
30$:
CMF' RO,12064
BMI SEND
RETURN TO WAIT--FOR
MSG TO BE ACCEPTED
IS TALKER ACTIVE'!'
IF YES,GO TO 30$
OTHERWISE SET IE, TON
ANn REM BITS OF lEIS REG
TO ACTIVATE TALKER
HAD ALL MSG BEEN SENT'!'
IF NO,GO SEND I~NOTI-IER MSG
OTHERWISE STOP
HALT
11-5232
Figure 10
Communicating with a Listener Device (Program listing)
461
IBV11-A
Example 2-IBV11-A to Talker Device
This programming example illustrates how the IBV11-A
communicates with a talker device. As in example 1, this programming example assumes standard IBV11-A device and interrupt vector
addresses. Communication between the instrument and the LSI-11
system is via IBV11-A interrupt-driven service routines. No background program is used; the program simply waits until another interrupt occurs.
Communication with the instrument involves first transmitting the content of the command message buffer, in a manner similar to the
program operation described for example 1, followed by accepting
instrument output data and storing it in a received data buffer. The
content of the command message buffer typically includes first activating the device via its listener address, followed by setting up range
mode, operating parameters for the instrument, an execute command, and finally, activating the device as an active talker via its talker
address. Once the device has received the command message buffer
data, it performs the programmed measurements (or the function,
depending on the instrument) and returns data to the LSI-11 system
via the IBV11-A. Note that during this portion of program operation,
the IBV11-A functions as an active listener on the instrument bus.
Once all measurements have been stored by the program, the program halts with a displayed PC address ~ 1102.
A program flowchart for this example is shown in Figure 11 and a
symbolic program listing is shown in Figure 12.
462
IBV11-A
NO
11-5234
Figure 11
Communicating with a Talker Device (Program Flowchart)
463
IBV11·A
ASSEMBLER SYNTAX
AIIIIRESS CODE
O(:·()4:30
001024
0<)(:1 ~~,3::':'
3 ,:~,
000200
001056
000200
001000
001002
001004
001006
001010
001012
001014
001016
001020
001022
001024
001026
001030
001032
001034
001036
001040
001042
001044
01270(,
000500
012700
002000
012701
002500
012737
000110
160150
000777
012737
000105
160150
022700
002024
001404
012037
160152
000002
001046
001050
001052
001054
012737
000320
160150
000002
001056
001060
001062
001064
001066
001070
001072
001074
013721
160152
022701
002540
001403
005037
160152
000002
001076
001100
005037
000000
()U("'i3·Q
~) ~) I~:i i~
COMMENTS
COMMANII/TALKER INTR
RETURN AI'I'RESS
PSW
LISTENER RETURN AI'DRESS
PSW
START:
WAIT:
MOV t500,R6
SET UF' STACK
MOV +2000,RO
IBVl1-A MSG BUFFER
MOV +2500,R1
BUFF FOR RECEIVEI' MSG
MOV t110,160150
TAKE CONTROL SYNCHRONOUSLY
TO BECOME CONTROLLERIN-CHARGE,C-I--C
WAIT--FOR INTERRUPT
PREF'ARE TO SENII
COMMANII MESSAGES
.
BR
MOV :f:105d60150
CMF' i2024,RO
HAD ALL COMMANIIS
BEEN SENT?
; IF YES,GO TO 20$
BEQ 20$
MOV (ROH,160152; OTHERWISE SENII MSG
RTI
20$:
MOV 1320.160150
RETURN TCI WAIT--FOR
MSG TO BE ACCEF'TEII
IBVll-A SWITCHES FROM
CONTROLLER TO LISTENER
RETURN TO WAIT-; FOR I'MM MSG
MOV 160152, (R1)H SAVE THE RECEIVEI'
MSG IN R1
HAIl 20 (OCTAL) MSG
CMF' :Jl:2540,R1
BEEN ACCEF'TEII?
IF YES,GO TO 30$
BEll 30$
OTHERWISE ISSUE I1AC
CLR 160152
RTI
RTI
30$:
CLR 160152
HALT
RETURN TO WAIT--FOR
ANOTHER I'MM MSG
ISSUE [lAC TO IB
STOF',.20 MSG RECEIVEI'
11-6236
Figure 12
Communicating with a Talker Device (Program Listing)
464
KPV11-A,-B,-C
KPV11-A,-B ,-C
POWER-FAlL/LINE-TIME
CLOCK/TERMINATOR
GENERAL
The KPV11 is an LSI-11 power-fail/line-time clock (LTC) generator. Three versions of the KPV11 are available: KPV11-A.
which has only power-fail and LTC functions; KPV11-B. which
has 120 g bus terminations in addition to the power-fail and
LTC; and KPV11-C. which is similar to the KPV11-B, but has
220 g bus terminations. The KPV11 is compatible with all LSI11 component systems and LSI-11 backplane options. It is designed for installation into any LSI-11 bus-structured backplane or remote installation (not installed into a backplane) via
an optional cable which connects the KPV11 to the LSI-11
backplane. In order to use the KPV11-B or KPV11-C as bus
terminators, they must be installed in the LSI-11 backplane. An
optional console panel and bezel are available for manual control of the LTC and the display of dc power on/off status and the
processor run/halt state.
FEATURES
• Automatic generation of BPOK and BDCOK power-up/power-down
signal sequence
• Automatic program restoration and starting when used with nonvolatile memory af!d appropriate software routines
• Line-time clock time reference provided by a signal source (usersupplied) other than the power line
• KPV11-B and KPV11-C provide bus termination when plugged into
an LSI-11 backplane
• Can be installed into the LSI-11 backplane or mounted remotely. An
optional cable (DIGITAL part no. 70-12754) connects the KPV11 to
the LSI-11 backplane
• Expandable with the 54-11808 console panel option
465
KPV11-A, -8,-C
SPECIFICATIONS
Identification
M8016 (KPV11-A)
MB016-YB (KPV11-B)
MB016-YC (KPV11-C)
Size
Double
Power
+5 Vdc ±5% at 560 mA
System DC
DC Sensing
Inputs
+5 Vdc ±5% at 0.11 mA
+ 12 Vdc ±3% at 0.B2 mA
24 Vac ± 10% at 200 mA with
grounded center tap (Figure 4)
AC Line Monitor
Input
Bus Loads
AC
DC
1.6
1.0
Options
54-11808
Console Panel (PC assembly)
70- 11656
Console Bezel
70-12754
Remote Signal Cable (for remote
mounting of KPV11)
70-086120
Console Signal/Power Cable (for
connecting optional console panel to the KPV11)
DESCRIPTION
General
The KPV11-A provides two main functions-power signal sequence
circuits and programmable line-time clock circuits. The KPV11-B and
KPV11-C haVE!, in addition, bus termination circuits, 120 {} for the
KPV11-B and 220 {} for the KPV11-C. All KPV11 modules have an
interface for the optional console panel. Figure 1 illustrates the basic
KPV11 functions.
466
KPV11-A, -8, -C
liNE XFMR
(USERSUPPLIED)
AC liNE INPUT
EXTERNtci"p~I~~:~~
'"
I"-
- -
--t
c~
24vac
BOAl (O:12)l
~
PROGRAMMABLE
LTC CKTS
BBS7 L
BSYNC
BOIN l
BOOUT
BINIT
BEVNT
BRPLY
C?
~
KPVI1-C
(M8016-YC)
LSI-"
SYSTEM
COMPONENTS
(PROCESSOR,
MEMORY,
PERIPHERAL
INTERFACE
MODULES,
ETC.)
t
J
l
~
--
LINE
FREQ
l
L
L
L
POWER
SIGNAL
SEQUENCE
CKT
---- ____ ? _S~A_R~ ..3_
~~
J
(
I'
BHALT L
--
V
(LSI-l1 BUS SIGS.)
BUS
TERMINATOR
J
~V"
J2
C:I
REMOTE
REMOTE
DC ON I
SIGNAL
CONNECTOR
OFF
(OPTIONAL)
Figure 1
KPV11 Functional Block Diagram
Power Signal Sequence Circuits
The power signal sequence circuits generate the proper LSI-11 bus
power sequencing signals (BPOK Hand BOCOK H) for the processor
power-up/power-down sequence and line-time clock interrupts at the
power line frequency. Figure 2 illustrates the KPV11 power signal sequence timing.
Power signal sequence circuits are shown In Figure 12. Operating
power for these circuits is obtained from the 24 Vac, 50 Hz or 60 Hz
input at the two ac terminals and GNO. Conventional full-wave rectifiers produce +17V and -17V operating voltages for the ac line monitor
Schmitt trigger (01 and 02) and a 5V,,3-terminal regulator; the regulator +5V is distributed throughout the power signal sequence circuit for
operating power.
467
KPV11-A, -8,-C
Power-Up - During the power-up sequence, ac voltage from the
transformer secondary is applied to a Schmitt trigger circuit (Q1 and
Q2). The Schmitt trigger squares the ac sine-wave and drives level
converter Q3. Q3's output is a TTL-compatible signal. The square
wave signal is applied to two 10 ms (nominal) one-shots (and the LTC
circuits). One one-shot triggers on the positive-going transition of the
square wave signal and the other triggers on the negative-going transition. The one-shot outputs are ORed, producing a high (normal)
output at gate E6-13. Normally, one or the other one-shot will be In the
set state. If a transition of the square wave signal is not followed by a
transition of the opposite polarity within 20 ms, both one-shots will
time out and the logic Signal at E6-13 will go low; this is a power-fail
condition.
During a power-up sequence, voltage sense +5V and + 12V (remote
sense), or +5V and +12V (LSI-11 backplane voltages) inputs rise to
voltage levels that cause voltage comparators A and B to produce high
outputs. The comparator outputs are connected and applied to one
input of gate A. The remaining input of gate A is enabled by the
normally high gate E6-13 Signal, which is applied (but not delayed) via
the 3 ms delay circuit. Gate A's output goes high. This signal is then
delayed 17 ms and inverted, producing a low signal which is applied to
the non-inverting input of comparator C and gate C. Comparator C's
output goes low, turning off Q4 and producing an active BDCOK H
signal 17 ms (minimum) after ac power is applied.
"'''"'~
BPOK H
BDCOK H
~t7m.(MIN)
POWER SUPPLY _ _ _.....JVr-~------I1
DC OUTPUT
VOLTAGES
IOl's(MIN)
------.....:.....-4.
1-/
T
W
POWER-UP
SEQUENCE
POWER-DOWN
SEQUENCE
Figure 2
Power Signal Sequence Timing
468
4ms DELAY CKT
+5V~
LSI -11 BACKPLANE POWER
j
AC2. AJ1.AM1.AT1
GND
~l.BT1
~
AD2
+12VO
+12vIREMOTEI
,;-- •••• AC
~
[(;!
+5Vcc
.,.
~
~
PIO LI NE XMFR
IUSER SUPPLIED) ~-----.GND~
~
')00
'.
',------.AC~
I
~
<0
II
03
•
+J
- t7V
LTC OUT H
(LINE FREO TO LTC CKTSI
-17V
,.
..
•
m
n•
• 17V
07
-17V
DC POWER ON H 2
<
....
....•
>
J1
I
~11
~Ell)DI'-'-----
:oJ
Figure 3
Power Signal Sequence Circuits
KPV11-A, -B, -C
Gate C's output goes high, enabling gate B. The remaining gate B
input is enabled by the high gate E6-13 output signal. Gate B's high
output signal is delayed 70 ms and inverted, producing a low signal
(E10-10) which is applied to the non-inverting input of comparator D.
Comparator D's output signal goes low, turning off 05, and producing
the active BPOK H signal 70 ms after the active BDCOK H signal. With
both signals in the active (high) state, normal system operation can
proceed.
Power-Down - When an ac power failure occurs, the trigger pulses to
the one-shots cease, and both one-shots time out. Gate E6-13 goes
low, inhibiting gate B, and initiating the 3 ms delay. (E6-4 signal voltage starts to rise from the logical low state). Gate B's output goes low;
this low signal is inverted, but not delayed, by the 70 ms delay circuit,
and the resulting high signal is applied to the non-inverting input of
comparator D. Comparator D's output goes high, turning on 05, and
negating BPOK H. Meanwhile, the 3 ms delay circuit, after the 3 ms
delay, produces a low signal at E10-14. A low signal inhibits gate A,
causing its output signal to go low. The low signal is inverted (but not
delayed) by the 17 ms delay circuit, and applied to the non-inverting
input of comparator C. Comparator C's output goes high, turning on
04 and negating the BDCOK H signal 3 ms after BPOK H becomes
negated. 06 monitors the 17 ms delay circuit output and produces the
DC ON H signal for the remote console panel display. When dc voltages are normal, E10-12 goes low; 06 cuts off and DC ON H goes high.
When dc voltages are not present. E10-12 goes high; 06 turns on and
negates DC ON H.
When the remote console panel is connected to the KPV11, the DC
ON/OFF switch can simulate a power line failure and control the user's
power supply. The simulated power line failure occurs when a low DC
POWER ON H occurs (DC OFF switch position). This low signal
produces a low signal that clears both one-shots, and the simulated
power failure results.
Remote control of the user's power supply is made possible via the
REMOTE DC ON/OFF etched pad. The signal present at this pOint is
the 3 ms delay circuit signal (E10-14) inverted by 07. Thus, when
normal line voltage is sensed and the remote console panel DC
ON/OFF switch is not in the OFF position, this signal goes low, activating a control circuit in the user's power supply that turns dc voltages
on. When this signal is high-a result of power-fail or placing the
remote console panel DC ON/OFF switch in the OFF position-the
user's power supply dc output voltages should turn off.
470
..,(1)~"a
..,
EX CL
"0
LINE FREQ
FROM POWER ,
FAIL CKT
~
BINIT L B
T2
10
."
9
E3
14
CLR H
LTC ON IOFF 4)
Jl
,,~
W14
(I)
(1)
RDAL06 H
3 3
Dl II
(i)S!2:
MAN I PROG
LTC ENABLE
W13
BDAL06 L
2,(1).
o·
== r::J::J-
5 INTERRUPTI ENABLE H
(1)
;. 3·
~
BBS7 L
BDAL12 L
C)o'V,
•
CLR L
~
::J
(1)
3
(1)
0
•
~on
(1)0_
rnlr:iBB;S2;-_ _ _ _ _ _ _ _ ·1]
..0 "_ n
0
~
(1)~"
+5V
~
~
o.,!...
LTC ENB
CLR H
~
-..,
~ 3 3
~~
CONSOLE LTC
SWITCH ENABLE
°
0
DlCOCI:I
~
-DlII
(I)
Wt5
::J::J_
oor-
........
'< !:!: -t
0
°0
..,::J_
~
BDAL05 L
00
gU,
_,
(1)(I)n
x Dl -
(j)m~
.., en
C
::J~::;
e!.o·
!:!:~
3 ~.
::J
RDAL07 L
(D
BSYNC L
tT"T1
BDOUTLfiD~A=E:2-------------------LJ
BDIN L
m
_AH~2~_ _ _ _ _ _ _ __
~(Q
r::::
(D
°m
'O~
"ct.:......I
(D"
.., c-
.. - 4845
Figure 4
Programmable Line-Time Clock Circuits
ar::::
-. 3
0"0
:'.
~
"V
<
~
~
•...••
...
III
n•
KPV11-A, -B, -C
console LTC ON/OFF switch enable/disable, and manual/-programmable operation. Additional jumpers (W1-W1 0) select the device
address for the LKS register. Jumpers are factory-configured as
shown in Figure 8.
Program access to the LKS register is via the address configured by
jumpers W1-W1 O. The processor first places the KPV11 LKS register
address on BDAL (00:15) L and asserts BBS7 L. Note that BBS7 Lis
asserted only during an addressing operation when BDAL (13:15) L
are asserted; hence, the address decoders receive only BDAL (00:12)
Land BBS7 L. Device selection occurs on the leading edge of BSYNC
L. If the address input matches the jumpered address, LKS H goes
high (true), and remains true for the duration of the LSI-11 bus cycle.
Two flip-flops comprise the two significant bits of the LKS register. Bit
6 is produced by the LTC enable flip-flop. Similarly, bit 7 is produced
by the LTC monitor flip-flop.
D.uring a programmed write operation (DATO, DATOB, or the write
portion of DATIO, or DATIOB bus cycle), LKS L (LKS H inverted) and
BDOUT L are ANDed to produce an active (high) WRITE LKS H signal.
The leading edge of LKS H clocks the logical state of BDAL06 H into
the LTC ENB flip-flop, enabling or disabling LTC interrupts. The LTC
MON flip-flop, however, can be preset only during the write cycle. Note
that the LTC MON flip-flop, when preset, is read as a logical 0 via the
flip-flop's Q output; when the flip-flop is reset, it is read as a logical 1.
BDAL07 L (0 = high) is ANDed with WRITE LKS H, producing a low
signal that presets the flip-flop; MONITOR H then goes low.
Normally, the LTC ON/OFF input to E10-5 is passive (high), producing
a low at E10-6 that enables AND gate input E13-12. When interrupts
are enabled, LTC ENB (1) L enables E13-11 and E13-13 goes high.
This signal then enables one input of the BEVNT L bus driver. The
remaining bus driver input is the LTC H signal. Thus, when LTC H goes
high, BEVNT L goes low, and the LTC interrupt request is presented to
the processor.
The leading edge of LTC H also clocks the LTC MON flip-flop to the
reset state, and MONITOR H goes true (high). MONITOR H conditions
one input of the BDAL07 H bus driver. During a read cycle, DATI (or
the read portion of the DATIO cycle), LKS L, and BDIN L are gated to
produce an active (high) READ LKS H signal. READ LKS H enables
both BDAL07 Land BDAL06 L bus drivers, gating the monitor and
interrupt enable status bits onto the LSI-11 bus.
During both programmed read and write bus cycles, the KPV11 must
472
KPV11-A, -8,-C
(respond by asserting BRPL Y L. READ LKS L and WRITE LKS L are
ORed and applied to the BRPL Y L to produce the appropriate device
response according to LSI-11 bus protocol.
The optional console panel includes the LTC ON/OFF switch. When
placed in the OFF position, J1-4 is low; E10-6 goes high, inhibiting
E13-12 and LTC interrupt requests are disabled. The function can be
disabled by removing W14.
When manual-only LTC operation is desired, W13 is removed and
W12 is installed. E13-11 is continuously enabled and LTC interrupt
requests can be disabled via the console panel LTC ON/OFF switch;
W14 must be installed for this operation.
Bus Terminations
The KPV11-C provides 120 n bus termination, while the KPV11-B has
220 n bus terminations. Each bus signal line termination includes two
resistors as shown in Figure 5. Termination resistors are contained in
16-pin dual-in-line packages that are physically identical to integrated
circuit packages. Each package contains 14 terminations. Daisycha~ned grant signals are jumpered but are not terminated. BIAKI Lis
jumpered to BIAKO Land BDMGI L is jumpered to BDMGO L.
+5V
+5V
11
3300
1800
TO/FROM
SIGNAL LINE
TO/FROM
SIGNAL LINE
6800
3900
220.n.
TERMINATION
IKPVII-CI
120.n.
TERMINATION
IKPVII-81
Figure 5
KPV11-B and KPV11-C Bus Terminations
C()nsole Panel Interface
The option console panel interfaces with the system via the KPV11
module as shown in Figure 6. The DC ON indicator (01) is driven
directly by the DC ON H driver (06) in the power signal sequence
circuit.
The RUN indicator is driven by the processor-generated SRUN L signal pulse. The 200 ms one-shot receives a continuous series of trigger
pulses, when the processor is in the "run" (program execution) state,
473
KPV11-A, -8,-C
that keeps the one-shot in the retriggered state. When in this state, the
one-shot produces a high signal that turns the RUN indicator (02) via
the LED driver. When the processor is halted, the 200 ms one-shot
times out, and the RUN indicator extinguishes.
~----------------------~:
>
~
+
>
:
+
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,
~
CD
Co)
~
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...J
....
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z
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18
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...>
-~-:..:.- ~-.:.:
L _....::
!
~
+
+
--..:.: --.:.:-..:.::..: --::..-:.:-.:.:-
!
..
n+nJ'
--..:.-:.:.-- -- -- -
_
en
CD
N
In
r- r-~ ----r---r-::-~-:: --:~-::r-::-::=Pt!l
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~
CD
... ~
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g
u~
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~ ____________
_ _ _ _ _ _ _'"_
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The three console switches each include a "debounce" circuit composed of cross-coupled inverters. DC ON/OFF and LTC ON/OFF functions are used as previously described for power signal sequence and
programmable line-time clock circuits, respectively.
The ENABLE/HALT switch enables the run mode (by not asserting
BHALT L) or halts the processor; when halted, console OOT microcode operation is invoked. An R-C filter and BHALT L bus driver
circuit on the KPV11 module interface this function to the LSI-11 bus.
CONFIGURATION
General
The KPV11 can be Installed into any LSI-11 system backplane or into a
remote installation (not installed in a backplane). All KPV11 installations require a user-supplied, 24 Vac, center-tapped transformer capable of supplying at least 0.2 A. Remote KPV11 installations also
require the optional remote Signal cable (part no. 70-12754). Users
requiring manual control of the LTC and desiring the display of dc
power on/off status and processor run/halt status need the optional
console panel, console bezel, and console signal/power cable. Mounting hardware for the console panel and remote installation must be
provided by the user.
Configuring LTC Jumpers
LTC jumpers are located on the KPV11 module as shown in Figure 7
and are factory-configured for programmable operation with the LKS
(line clock status) register at address (177546) as shown In Figure 8.
Normally, it will not be necessary to reconfigure LTC jumpers; however, it is possible to alter LTC operation as listed in Table 1 and the
LKS device address as shown in Figure 8 and listed in Table 2.
475
KPV11-A, -8,-C
EX CL
REM DC
+t2V
o
Wt4
JI
+5V
R54"
GNO
W12
W15
D
R3S"
F=t:~i=:t=±=t:~O
~
W7
.W8
WII
E12
W6
W5
W4
W3
W2
WI
~-+---+--+- E3 (KPVlI-B
(KPVH-8,
KPVll-C
ONLY) { EI7
KPVlI-C
ONLY)
c:::::J
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•• MAY USE 4-40 HARDWARE
•• aRemove for 50Hz operation
Figure 7
Jumper, Connector, Resistor, and Pad Locations
476
KPV11-A, -8,-C
15
BIT
,--.--r-____r--,--,.__--r-.......-:~~_,_-,.____r_-_r_____r-_,_-,.____, PREFERRED
ADDRESS
L..----I...--'-----'"__r_....I--r-L......r---l..._,_..L.-,..___J.-....L-...--L......r~_,_....L...-,..___J.-...L--.L.----'
ADDESS JUMPER WI
W2
W3
W4
W5
W6
W7
we
W9
(177546)
Wl0
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Figure 8
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R FACTORY JUMPER CONFIGURATION
I • INSTALLED' "1"
R • REMOVED' "0·
Device Address (LKS Register) Jumpers
Table 1
LTC Jumpers
Jumper
Installed
Removed
W12
Enable manual control
or continuous LTC
interrupt request operation. Do no install
when W13 is installed.
*Disable continuous or manualoperation.
W13
*LTC interrupt requests can be enabled
and disabled by program. Do not install
when W12 is installed.
LTC interrupt requests cannot
be program controlled.
W14
*Console (optional)
LTC ON/OFF switch
enabled.
Console LTC ON/OFF switch
disabled.
W15
*LTC signal occurs at
the power line frequency.
LTC frequency is determined
by an external source via EXT
TIME REF etched pad on module.
* Factory-jumpered configuration
477
KPV11-A, -8,-C
Table 2
Standard Assignments
Description
Mnemonic
Read/
Write
First
Module
Address
Register
Line Clock Status
LKS
R/W
177546
Vector
None
Installation In the LSI-11 Backplane
The KPV11 module can. be installed in any LSI-11 backplane. The
KPV11 may be inserted into any option location when not used as a
terminator. This option does not require the use of the daisy-chained
grant signals (BIAK Land BDMG L) and is not priority dependent on
device position in the backplane.
When used as a terminator (KPV11-B and KPV11-C), the module is
inserted after the last module in the last backplane.
When the optional console panel is used with the terminator option
and the RUN indicator is desired, the following must be performed .
• Insert the KPV11 module in the last option location in the backplane
system .
• Connect a wire on the backplane from pin CH1 or AH1 on the KPV11
module to the SRUN L signal on the processor module. The wire
must not exceed the length of the LSI-11 bus. This Signal is located
on pin AH1 of the processor.
Remote Installation
The KPV11 option can be mounted in a remote location (not installed
in a backplane), as desired. Mounting holes are provided in the module for this purpose. Mounting details (mechanical) are shown in Figure9.
NOTE
Program control of the LTC function and bus
termination is not possible when remote installation
is used. Hoever, manual control of the LTC function
is available via the optional console panel.
Electrical connection between the KPV11 option and the LSI-11 bus is
made via a 10-pin connector (J1) on the KPV11 and a 10-pin connector on the backplane (H9270 or DDV11-B) in which the processor is
478
KPV11-A, -8,-C
installed. The optional signal cable (part no. 70-12754) provides the
electrical connection between the two 10-pln connectors.
The +5 Vdc and +12 Vdc voltage sense Input must be provided by the
user when the KPV11 option is not installed in an LSI-11 backplane.
Etched pads are provided on the KPV11 module for this purpose and
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KPV11-A, -8,-C
are located as shown in Figure 7. Connect the +5V, +12V and GND
pads to the respective LSI-11 backplane power terminals.
If the optional console panel is to be used and the RUN indicator
function is desired, a wire must be installed between the SRUN L pin
(pin 3) on the 10-pin connector on the backplane and the processor
module pin AH1. A wire is normally factory-installed for this purpose
on all backplanes except DDV11-B backplanes.
Power Sense Connections
Three tabs on the KPV11 are provided for connecting the option to a
24 Vac, center-tapped transformer. This 50 or 60 Hz input voltage
produces the required dc operating voltages for the option, provides
the 50 or 60 Hz reference for the LTC function, and is the power-fail
monitor signal for the power signal sequence circuit. This voltage must
be supplied by the user. A transformer can be connected as shown in
Figure 7 for this purpose. When the KPV11 is used with a 50 Hz input
voltage, resistors R35 and R54 must be removed for proper power-fail
time to compensate for the change in frequency. The location of these
resistors is shown in Figure 10.
It
~---<>'"U>----_AC
>---O~---GND
TO KPV11
24Voc INPUT
TERMINALS
'---+----<>'"U>----_ AC
GND - - - - - - - ' - . . . , . . . . . - J
CA) 115V CONNECTIONS (TYPICAL)
230Voc,50Hz
} TO SYSTEM POWER
SUPPLY AND FANS
It
~--4V-_AC
I>--,-------..... GND
TO KPV11
24Voc INPUT
TERMINALS
*
'---+---4V-_AC
GND - - - - - - - ' - . . . . - - '
CB) 230V CONNECTIONS (TYPICAL)
It 1 AMP FAST BLOW FUSES ARE RECOMMENDED
ON THE AC INPUT LINES TO PROVIDE ADEQUATE
PROTECTION TO THE KPV11,
Figure 10
H-48:59
Power Line Monitor Transformer Installation
480
KPV11-A, -8,-C
Installing Console Panel
The optional console panel can be mounted as shown in Figure 11.
Electrical connections between the KPV11 and the console panel are
made via 16-pin dual-in-line integrated circuit sockets located on each
assembly. The electrical connection between the sockets is made using a signal/power cable (part no. 70-08612-00).
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(TYPICAL!
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IDEC PIN 70-11656)
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MODULE
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Console Panel Installation
481
KPV11-A, -8,-C
In addition to the LTC ON/OFF and RUN/ENABLE switch functions,
the console panel includes a DC ON/OFF switch. This switch, when in
the OFF position, disables BDCOK Hand BPOK H signal generation. If
desired, this switch can also control the DC ON/OFF state of the user's
power supply. This function is enabled by connecting the REMOTE DC
ON/OFF and GND etched pads on the KPV11 module to an appropriate control circuit in the power supply. The signal thus produced is
TTL-compatible and is capable of sinking 16 mA signal current in its
logical low (DC ON) state. The logical high state is the DC OFF condition.
Using an External Reference
The KPV11 normally uses the 50 or 60 Hz input (via the three power
tabs on the module) for LTC signal generation. However, an external
frequency source may be used for producing LTC signals at
frequencies other than the power line frequency. An etched pad is
provided for this purpose on the KPV11 module. First, cut or remove
jumper W15; this jumper and the external clock (EX CL) pad are located as shown in Figure 7. Then, connect the external frequency source
to the EX CL and GND pads. The frequency source must be TTL logiccompatible; the KPV11 presents three TTL loads to the source.
Console Operation
The console panel option controls and indicators are shown in Figure
12 and described in Table 3.
Figure 12 Console Panel Controls and Indicators
(P/N 54-11808 and 70-11656 shown)
482
KPV11-A, -8,-C
Table 3
Console Panel Controls and Indicators
Control
Indicator
Type
Function
DCON
LED Indicator
Illuminates when the
DC ON/OFF toggle
switch is set to ON
and proper dc output
voltages are being
produced by the
user's power supply
and sensed by the
KPV11 option.
If either the +5V or
+ 12V output from the
power supply Is faulty, the DC ON indicator will not illuminate.
RUN
LED Indicator
Spare
LED Indicator
DC ON/OFF
Two-position Toggle
Switch
illuminates when the
processor Is In the
run state (see ENABLE/HALT).
When set to ON, enabies dc outputs of
the user's power supply (If connected to
this function-see instructions for Installing the console panel). The DC ON Indicator will illuminate If
the dc output
voltages are of propervalues.
When set to OFF, the
power supply dc out-
483
KPV11-A, -8, -C
Table 3
Control
Indicator
Console Panel Controls and Indicators (Cont)
Type
Function
puts are disabled and
the DC ON indicator
is extinguished.
ENABLE/HAL T
Two-position Toggle
Switch
When set to ENABLE,
the BHAL T L line to
the processor is not
asserted and the
processor is in the
run-enable mode
(RUN indicator is illuminated only when
the processor is executing a program).
When set to HALT,
the BHALT L line is
asserted. The processor halts program execution and executes
console ODT microcode. The RUN indicator is extinguished.
LTC ON/OFF
Two-position Toggle
Switch
When set to ON, enables KPV11 option
generation of LTC interrupts. When set to
OFF, disables LTC interrupts (W14 must
be installed).
PROGRAMMING
Power-down and Power-up Routines - Power-down and power-up
routine examples for systems using core memory are provided in
Figures 13 and 14. The power-down routine shown provides an orderly power-down sequence of the system and saves the contents of the
general-purpose registers along with the stack pOinter and the Processor Status Word. Other device registers which the user desires save
484
KPV11-A, -8, -C
during power-down can be included through the use of the MOV @
NAME-(SP) instruction.
The power-down routine is entered via the routine's starting address
($PWRDN) in interrupt vector location 24; location 26 should contain
200 8 to disable device interrupts during the power down sequence.
The first MOV instruction temporarily replaces the power-down vector
address with the address of a HALT instruction ($HL T). This prevents
an erroneous power-up attempt during the power-down routine execution. A sequence of MOV instructions then saves register contents
on the stack. The second from the last MOV instruction, however,
saves the SP in location $SAVR6, which is dedicated by the program
for this purpose. It is the last register saved by the routine. The starting
address ($PWRUP) for the power-up routine is then written into location 24, replacing the temporary $HL T address. Finally, the program
halts and the power-down sequence is completed.
$PWRDN:
MOV
#$HLT,@#24
MOV
MOV
MOV
MOV
MOV
MOV
MOV
RO,-(SP)
R1,-(SP)
R2,-(SP)
R3,-(SP)
R4,-(SP)
RS,-(SP)
@NAME,-(SP)
MOV
MOV
SP ,$SAVR6
#$PWRUP,@#24
$HLT:
HALT
$SAVR6:
WORDO
Figure 13
;DISABLE FALSE
;RESTART SEQUENCE
;PUSH RO ON STACK
;PUSH R1 ON STACK
;PUSH R2 ON STACK
;PUSH R3 ON STACK
;PUSH R4 ON STACK
;PUSH RS ON STACK
;SAVEANY
;NECESSARY DEVICE
;AEGISTERS
;SAVESP
;SET POWER-UP
;VECTOR
;POWER-DOWN
;SEQUENCE
;DONE, READY FOR
;POWER-UP
;SEQUENCE
;SP SAVED HERE
Power-Down Routine Programming Example
485
KPV11-A, -8,-C
$PWRUP:
$PWRMG:
$ILLUP:
$POWER:
Figure 14
MOV
MOV
MOV
#$ILLUP,@#24 ;SET FOR FAST DOWN
$SAVR6,SP
;GET SP
(SP)+,@NAME ;RESTORE ANY DEVICE
;REGISTERS SAVED
MOV
MOV
MOV
MOV
MOV
MOV
MOV
(SP)+,R5
(SP)+,R4
;POP STACK INTO R5
;POP STACK INTO R4
(SP)+,R3
;POP STACK INTO R3
(SP)+,R2
;POP STACK INTO R2
(SP)+,R1
;POP STACK INTO R1
(SP)+,RO
;POP STACK INTO RO
#$PWRDN,@#24 ;SET UP THE POWER;DOWN VECTOR
;REPORT THE POWER
TYPE
;FAILURE
;POWER FAIL MESSAGE
WORD $POWER
;POINTER
RTI
HALT
;THE POWER-UP
;SEQUENCE WAS
;STARTED
;BEFORE THE POWER.2
BR
;DOWN
;WAS COMPLETE
.ASCII <15><12>"POWER"
Power-Up Routine Programming Example
When power ·is restored, the power-up routine is entered via the routine's starting address ($PWRUP) in interrupt vector location 24. The
power-up routine shown in Figure 14 uses the $HLT and $SAVR6
locations shown in the power-down routine for disabling false powerdown sequences and restoring the stack pOinter, respectively. The
first two MOV instructions reference those locations. A sequence of
MOV instructions that follow restore device and processor registers,
respectively. The last MOV instruction writes the starting address
($PWRDN) for the power-fail routine in location 24, replacing the temporary $HL T address. Finally, the RTI instruction pops the PC and PS
of the program where the power-down sequence occurs from the
stack and normal program execution is restored.
486
KPV11-A, -8,-C
Programming the LTe - The LTC function normally divides time into
16-2/3 ms or 20 ms intervals determined by the line frequency source
(60 Hz or 50 Hz, respectively). It is possible to disable the line frequency source and use an external frequency source (user-supplied). The
program communicates with the LTC function via the LKS register
(Figure 15) contained in the KPV11 logic circuits. The LKS register's
device address is normally configured to 177546 for system software
compatibility.
LKS
(177546)
(READ/WRITE BIT!
MONITOR
SET TO "1" BY LINE FREQUENCY CLOCK
SIGNAL. CLEARED BY PROGRAM.
(READ/WRITE [CLEAR-ONLY] BIT!
Figure 15
Line-Time Clock Status Register (LKS)
LTC interrupts, when enabled (LKS bit 6 = 1), occur as an interrupt
request (bus low assertion) on the BEVNT L signal line. This causes
the processor to execute a service routine via vector address 100.
Memory location 100 must contain the PC (starting address) for the
LTC service routine; similarly, memory location 102 must contain the
PS (processor status word) for the service routine. As with all "external" interrupts, the processor will recognize the LTC interrupt request
only when current PS bit 7 is cleared. When PS bit 7 = 1, external
interrupts, including the LTC interrupt, are ignored. The LTC interrupt
has highest priority of all external interrupts and does not require a
vector address bus transfer. An interrupt request via the BEVNT L bus
signal line, as previously stated, always results in access to the service
routine via vector address 100.
The KPV11 is factory-configured for programmable operation as described above. If the user's hardware configuration also includes the
optional console panel, the operator can disable or enable the LTC
function by setting the LTC ON/OFF switch to the desired position.
When set to the OFF position, the LC switch overrides program control
and LTC operation is disabled. W14 must be installed for this function.
487
KWV11-A
KWV11-A PROGRAMMABLE REAL-TIME CLOCK
GENERAL
The KWV11-A is a programmable clock/counter that provides a variety of means for determining time intervals or counting events. It can be
used to generate interrupts to the processor at predetermined intervals, or to synchronize the processor ratios between input and output
events. It can also be used to start the ADV11-A analog-to-digital
converter either by clock counter overflow or by the firing of a Schmitt
trigger.
The clock counter has a resolution of 16 bits and can be driven from
any of five internal crystal-contrOlled frequencies (100 Hz to 1 MHz),
from a line frequency input or from a Schmitt trigger fired by an external input. The KWV11-A can be operated in any of four programmable
modes: single interval, repeated interval, external event timing, and
external event timing from zero base.
The KWV11-A includes two Schmitt triggers, each with integral slope
and level controls. The Schmitt triggers permit the user to start the
clock, initiate A/D conversions, or generate program interrupts in response to external events.
FEATURES
• Resolution of 16 bits
• Can be driven by an external input or from any of five internal
frequencies
• Four programmable modes
• Slope and reference signal level selection switches
• Can be used to start the ADV11-A analog-to-digital converter.
SPECIFICATIONS
M7952
Quad
+5 Vdc ±5% at 1.75 A
+12 Vdc ±3% at 0.01 A
Identification
Size
Power
Bus Loads
AC
DC
Operational
Clock
Accuracy
Range
3.4
1
0.01%
Base frequency (10 MHz) divided
into five selectable rates (1 MHz,
100 kHz, 10kHz, 1 kHz, 100 Hz);
line frequency; Schmitt trigger 1
input
488
KWV11-A
Input Signals
ST1 IN (Schmitt Trigger 1 Input)
Input Range
m(maximum limits)
-3Vto +30V
Assertion level
Depends upon position of slope
reference selector switch and level control; triggering range =
-12 V to +12V
Origin
User device
Response Time
Depends on input waveform and
amplitude; typically 600 ns with
TTL logic input
Hysteresis
Approximately 0.5V, positive and
negative
Characteristics
Single-ended Input; 100 KU impedance to ground
ST2 IN (Schmitt Trigger 2 Input)
Same description as ST11N
Output Signals
ClK OV (Clock Overflow)
Asserted level
low
User device or ADV11-A
Destination
Approximately 500 ns
Duration
TTL open-collector driver with
470 U pull-up to +5V
Characteristics
Maximum source current from
output through load to ground
when output Is high (;~2.4V): 5
mA
Maximum sink current from external source voltage through
load to output when output Is low
(:S0.8V): 8 mA
ST1 Out (Schmitt Trigger 1 Output)
Same description as ClK OV
ST2 Out (Schmitt Trigger 2 Output)
Same description as elK OV
489
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KWV11-A Real-Time Clock Block Diagram
.. MISCELLANEOUS
INTERNAL CONTROL
SIGNALS
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The logic associated with the bus control block maintains proper communications protocol between the processor bus and the KWV11-A.
This logic generates and monitors the bus signals involved during
interrupts and data transfers between the processor and the KWV11A. It permits the KWV11-A to recognize when it is being addressed by
the processor (address defined by the address switch pack), to prescribe the location in memory pointing to the starting addresses of
interrupt service routines (by means of the vector switch pack), to
input control data from the processor, and to output data to the processor.
Interrupts can be enabled for both counter overflow and operation of
ST2. Since each of these conditions raises a flag bit in the control/status register, and since separate interrupt vectors exist for each
condition, the conditions may be distinguished either by vectors or by
testing flag bits.
Control/Status Register
The control/status register (CSR) provides a means for the processor
to control the operating of the KWV11-A and to derive information
about its operation condition. Sits are provided for enabling
interrupts, mode selection, maintenance operations, starting the
counter, and overflow and Schmitt trigger event monitoring.
Mode Control
Logic circuitry associated with the mode control block permits
KWV11-A operation in four different modes as specified by bits 2-1 of
theCSR.
Mode 0 (Single Interval) - When the GO bit is set in this mode either
by the processor or by a Schmitt trigger 2 event, the counter is loaded
from the buffer/preset register (which has previously been loaded with
the 2's complement of the number of counts desired before overflow).
Once loaded, the counter will increment at the selected rate until it
overflows. Overflow clears the GO bit, sets the Overflow flag, and
interrupts the processor if that function has been enabled. If interrupt
has not been enabled, the KWV11-A waits for processor intervention.
Mode 1 (Repeated Interval) - When the GO bit is set in this mode,
the counter is loaded from the buffer/preset register (SPR) and is then
incremented to overflow as for mode O. In mode 1, however, overflow
does not clear the GO bit; instead, it causes the counter to be reloaded
from the SPR, raises the Overflow flag, initiates an interrupt sequence
if the CSR Interrupt on Overflow bit Is set, and causes the count to be
continued with no loss of data.
491
KWV11-A
Mode 2 (External Event Timing) - When the GO bit is set In this
mode, the counter Is set to 0 and then incremented at the selected rate
as long as the GO bit remains set. An external signal to Schmitt trigger
2 (ST2) causes the current contents of the counter to be loaded into
the SPA while the counter continues to run. At the same time, the ST2
flag is set and, if Interrupt 2 is enabled, an interrupt is generated, thus
permitting the program to read the value held in the SPA.
The counter continues to run after the ST2 event and also continues to
run after overflow. Interrupt on Overflow may be enabled to alert the
program to the overflow condition.
Mode 3 (External Event Timing from Zero Base) - Operation in
mode 3 is identical to that in mode 2 except that the counter is zeroed
each time an ST2 event loads its contents into the SPA.
Flag Overrun - In all modes, if a second overflow occurs before the
Overflow flag is reset (Le., before a prior event is serviced by the
processor), or if ST2 fires when the ST2 flag is already set, the Flag
Overrun bit is set.
Oscillator, Divider, Rate Control Chain
The circuitry associated with these blocks provides the time base that
is fed to the counter. The KWV11-A permits eight clock conditions to
be specified by bits 5-3 of the CSR: STOP, 1 MHz, 100 kHz, 10 kHz, 1
kHz, 100 Hz, an external time base applied to ST1, and line frequency
(50 or SO Hz) picked up from bus line SEVNT. External periodic or
aperiodic pulses may be applied to ST1 and counted.
Buffer/Preset and Counter Registers
The buffer/preset register is a word-oriented, 1S-bit read/write register that can be loaded either under program control or from the counter. In modes 2 and 3, the firing of ST2 causes the SPA to be loaded
with the contents of the counter. The BPR cannot be loaded by the
program in these modes as long as the GO bit is set.
The counter is a 1S-bit internal register accessible only by way of the
SPR; in modes 2 and 3 it can be read indirectly through the BPA.
Schmitt Triggers
Both Schmitt triggers are equipped with switches to permit selecti.ng
slope direction (+ or -) and threshold reference level (TTL or -12V to
+ 12V continously variable). Each Schmitt trigger is also equipped with
a screwdriver-operated potentiometer to permit setting the variable
threshold level. Switch pack and potentiometer terminals are all
492
KWV11-A
brought to multiple connector J1 to permit attachment of external
user-provided slope and level controls.
The two Schmitt triggers are used in somewhat different ways.
ST1 - Performs as an external time base input or external input for
aperiodic signals to be counted. Outputs both to ST1 Faston connector to provide external start signals to ADV11-A and, through rate
control circuitry, to permit selection as input to the counter. Maximum
frequency varies as a function of input waveform.
ST2 - When the ST2 GO Enable bit is set, firing ST2 in any mode sets
the GO bit and initiates counter action, causes the ST2 flag to be
asserted, and generates an interrupt if that function is enabled. When
the GO bit is set in modes 2 and 3, firing ST2 causes the buffer/preset
register to be loaded from the counter, the ST2 flag to be set, and an
interrupt to be generated if enabled.
CONFIGURATION
The following paragraphs describe the procedure for device and interrupt vector address selection, slope and reference level selection,
user connections, and programming. (Aefer to the ADV11-A when
using the KWV11-A with that module.)
Device Address Selection
The KWV11-A contains two device registers that can be addressed by
the processor. These registers are the control/status register (CSA)
and buffer/preset register (BPA). The BPA's address is always equal
to the CSA address plus two. Thus, only the CSA address is configured by the user, as shown in Table 1.
Table 1
Standard Assignments
Description
Mnemonic
Read/
Write
Register
Control/Status
Buffer /Preset
CSA
BPA
A/W
A/W
Interrupts
Clock Overflow
Schmitt Trigger 2
CLKOV
ST2
493
First
Module
Address
170420
170422
440
444
KWV11-A
Switch pack S1 (Figure 2) contains 10 switches; each corresponds to
an address bit as shown in Figure 3. The ON positions select a logical 1
bit address; similarly, the OFF positions select logical Os. The eSR
address can be configured for any address ranging from 17000 to
17777r, with the least significant octal digit configured for 0 or 4. The
recommended KWV11-A eSR address is 170420; S 1 is shown configured for this address in Figure 2. Note that the 8PR address, based on
the recommended CSR address, is 170422.
Interrupt Vector Selection
The KWV11-A can interrupt the processor for clock overflow and
Schmitt trigger 2 (5T2) services. Thus, two interrupt vectors are produced by the KWV11-A. Switch pack 53 (Figure 4) selects the vector
for the clock overflow interrupts; the 5T2 interrupt vector is always
equal to the clock overflow interrupt vector plus four. S3 contains
seven switches (one not used) that correspond to vector bits (03:08),
as shown in Figure 4. Configure the desired clock overflow interrupt
vector shown in the figure. The recommended address is 000440.
I'
JI
ClK
1
@R19
BI T 11
BIT 2
ADDRESS
SWI TCHES
81T 8
BIT 3
o
VECTOR
SWITCHES
Figure 2
KWV11-A Connectors, Switches, and Controls
494
sn
00
@R180S2
KWV11-A
15
14
13
12
11
10
09
08
07
06
.......
05
04
03
02
01
00
I__
1 ..&....-1
1 ~I~I
1-'--,1
0.............,1°-L......,Io~ll 1 ____
0 I ..,....,..0
1..,.......0
I ~11...,.......01.....,.....01_0_1 _ 0I ::'~I~~
I I I I I I I I I I
STANDARD ADDRESS
CONFIGURATION
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
OFF
OFF
I I I I I I I I I I
(1704201
ADDRESS
I~~--~~--~--~--~~--~--~~~I
SWITCH (SII ~_1___________________________1_0...
MR·0868
Figure 3
KWV11-A CSR Address Switches
MR·0869
Figure 4
KWV11-A Vector Address Switches
Slope and Reference Level Selection
Slope and reference level switches and controls are shown in Figures
2 and 5. Two reference modes are selectable for each Schmitt trigger-one that picks a fixed level appropriate to TTL logic, and one that
picks a variable level that permits setting the ST threshold to any point
between -12V and +12V.
OFF~ON
TTL REFERENCE
(JI-Nl
i
I
I
I
I
BOARD HANDLE
ST LEVEL 1
(Jl-L)
ST LEVEL 2
ST SLOPE 1 (Jl-TI
RIB
ST SLOPE 2 (Jl-Rl
NOT USED
S2
BOARD FINGERS
!
11-4178
Figure 5
KWV11-A Slope/Reference Level Selector Switches and
Controls
495
KWV11-A
Slope selection is accomplished by separate switches for ST1 and
ST2, respectively. When the related switch is on, the firing point effectively occurs on the positive slope of the input waveform. When the
switch is off, the firing point occurs on the negative slope. R18 or R19
is used to set the level of the reference. Typical slope selection is
shown in Figure 6.
NOTE
Users should take care that both TTL and variable
switches for either Schmitt trigger are not on simultaneously. This condition will not damage
components, but produces unpredictable reference
levels. Note also that if no signal is connected to a
Schmitt trigger input, both threshold switches for
that ST should be open for noise immunity. Alternatively, ST1 IN and ST2 IN can be grounded externally.
POSITIVE·GOING THRESHOLD
SELECTED TRIGGER - - - - -. - - - - -- - - - - - - - - - LEVEL (R180R 19) --
-
- - - - ./.I. /-HYSTERESIS
- - - , , - "'0.5 V
NEGATIVE·GOING THRESHOLD
OUTPUT
----u
U
.....J1.-500ns
NOTE:
ST IS RETRIGGERED ONLY AFTER INPUT WAVEFORM
HAS MOVED BEYOND OPPOSITE THRESHOLD AND
THEN AGAIN PASSED SELECTED THRESHOLD.
-..II.-500ns
(a) SLOPE SELECTION: SLOPE SWITCH ON (POSITIVE SLOPE)
SEE NOTE
- - - - - - - - -;.
SELECTED TRIGGER - - - - LEVELlR180R19)-------.
POSITIVE·GOING THRESHOLD
---- - - -.- -.s( ~YSTERESIS
- - -
- __ - ___ .___ , , _
!
OUTPUT
0.5 V
NEGATIVE-GOING THRESHOLD
------iUr----------iu---.....J I.- 500n5
NOTE:
ST IS RETRIGGERED ONLY AFTER INPUT WAVEFORM
HAS MOVED BEYOND OPPOSITE THRESHOLD AND
THEN AGAIN IS PASSED SELECTED THRESHOLD.
--II.- 500n5
(b) SLOPE SELECTION: SLOPE SWITCH OFF (NEGATIVE SLOPE)
Figure 6
KWV11-A Slope Selection
496
KWV11·A
Register Format
CSR Bit Assignments - CSR bit assignments are Identified in Figure
7 and defined in Table 2.
INT 2
FOR
MAINT
osc
Figure 7
Table 2
MAINT
ST1
INT OV
RATE
MODE
1
1
GO
eSR Bit Assignments
KWV11·A CSR Bit Definitions
Blt/CSR Name
Set By/Cleared By
Remarks
15/ST2 Flag
Set by the firing of
Schmitt trigger 2 or
the setting of the
MAINT ST2 bit in any
mode while the GO
bit or the ST2 Go Enable bit is set.
Cleared under program control. Also
cleared at the" 1"-going transition of the
GO bit unless the ST2
Go Enable bit has
previously been set.
Must be cleared after
servicing an ST2 interrupt to enable further interrupts. When
cleared, any pending
ST2 interrupt request
will be cancelled. If
enabled Interrupts
are requested at the
same time by bits 7
and 15, bit 7 has the
higher priority.
Set, and cleared under program control.
When set, the assertion of ST2 Flag will
cause an interrupt. If
set while ST2 Flag is
set, an interrupt Is initiated. When cleared,
any pending ST2 interrupt request will be
cancelled.
Read/write to 0
14/INT 2
(Interrupt
on ST2)
Read/write
497
KWV11-A
Table 2
KWV11-A CSR Bit Definitions (Cont)
Blt/CSR Name
Set By/Cleared By
Remarks
13/ST2 Go Enable
Set and cleared under program control.
Also cleared at the
"1 "-going transition
of the GO bit.
When set, the assertion of ST2 flag will
set the GO bit and
clear the ST2 Go Enable bit.
Set when an overflow
occurs and the Overflow flag is still set
from a previous occurrence, or when
ST2 fires and the ST2
flag is already set.
Cleared under program control and at
the "1"-going transition of the GO bit.
This bit provides the
programmer with an
Indication that the
hardware is being
asked to operate at a
speed higher than is
compatible with the
software.
Set and cleared under program control.
For maintenance purposes, this bit inhibits
the internal crystal
oscillator from incrementing the clock
counter. Used In conjunction with bit 10.
Setting this bit slmulates the firing of
Schmitt trigger 2. All
functions initiated by
ST2 can be exercised
under program control by using this bit.
Setting this bit simulates the firing of
Schmitt trigger 2. All
functions initiated by
ST2 can be exercised
under program control by using this-bit.
Read/write
12/FOR
(Flag Overrun)
Read/write
11/010
(Disable Internal
Oscillator)
Read/write
10/MAINT OSC
Write-only
9/MAINT ST2
Write-only
Set under program
control. Clearing is
not required. Always
read as a O.
Set under program
control. Clearing is
not required. Always
read as aO.
498
KWV11-A
Table 2
KWV11-A CSR Bit Definitions (Cont)
Blt/CSR Name
Set By/Cleared By
Remarks
S/MAINTST1
Set under program
control. Clearing is
not required. Always
read as aO.
Setting this bit slmulates the firing of ST1.
All functions initiated
by ST1 can be exercised under program control by using
this bit.
Set each time the
counter overflows.
Cleared under program con.trol and at
the "1"-going transition of the GO bit.
If bit 6 is set, bit 7 will
Initiate an interrupt.
Bit 7 must be cleared
after the Interrupt has
been serviced to enable further overflow
Interrupts. If cleared
while an overflow interrupt request to the
processor is pending,
the request is cancelled. If enabled interrupts are requested at the same time
by bits 7 and 15, bit 7
has the higher priority.
Set and cleared under program control.
When this bit is set,
the assertion of
OVFLO FLAG will
generate an Interrupt.
Interrupt Is also generated If bit 6 Is set
while OVFLO FLAG Is
set. If cleared while
an overflow interrupt
request to the processor Is pending, the
request is cancelled.
Write-only
7/0VFLO FLAG
Read/write to 0
6/INTOV
(Interrupt on Overflow)
Read/write
499
KWV11-A
Table 2
KWV11-A CSR Bit Definitions (Cont)
Bit/CSR Name
Set By/Cleared By
Remarks
5-3/RATE
Set and cleared under program control.
These bits select
clock counting rate or
source.
Read/write
543 Rate
000 STOP
001 1 MHz
010 100kHz
011 10kHz
1001kHz
101 100 Hz
11 0 ST1
1 1 1 Line (50/60 Hz)
2-1/MODE
Read/write
O/GO
Read/write
Set and cleared under program control.
Function 21
Mode 0: 00
Mode 1: 01
Mode 2: 10
Mode 3: 11
Set and cleared under program control.
Also cleared when
the counter overflows
in modeO.
Setting this bit initiates counter action as
determined by the
rate and mode bits. In
modes 1, 2, and 3 it
remains set until
cleared. In mode 0 it
clears itself when
counter overflow occurs. Clearing bit 0
clears and inhibits the
counter.
Buffer/Preset Register (BPR) - The SPR is a 16-bit, word-oriented,
read/write register. Any attempt to write a byte into this register will
result in a whole word being written. In modes 0 and 1, the program
may load it with the 2's complement of the number of counts desired
before overflow. In modes 2 and 3, it permits indirect reading of the
clock counter.
500
KWV11-A
Normal Control Sequences - Mode 0 (Single Interval)
Control code for operation in mode 0 must support the following sequence:
1. The control program writes the desired count (2's complement)
into the BPR.
2. The program writes the control code into the control/status register as indicated in Table 3.
3. If the GO bit is set high, KWV11-A responds by loading the 16-bit
counter from the BPR and enabling the counter; if the GO bit is set
low and the ST2 Go Enable bit is set high, KWV11-A waits for an
ST2 event, then sets the GO bit and loads and enables the counter.
4. The counter increments until overflow, then halts (GO bit is
cleared).
5. KWV11-A raises the Overflow flag and issues an interrupt if the
CSR INT OV bit is set; if the interrupt is not enabled, KWV11-A
waits for program intervention.
6. The program responds to the interrupt or intervenes in consequence of other criteria (e.g., testing the Overflow flag or the A/D
Done flag if overflow was used to start an A/D conversion). The
program reads the CSR, clears the Overflow flag, and if no counting or mode changes are required, sets the GO bit or the ST2 GO
ENABLE bit to re-enter the sequence at step 3.
Table 3
CSR Bit Settings for Mode 0, Single Interval
Bit No.
Name
Bit Condition
as Written by
Processor
15
ST2 FLG
0
Will be set to 1 on ST2
event. Cleared by leading
edge of GO bit assertion
except when ST2 GO ENA
has previously been set.
14
INT2
x
Set to 1 by program if interrupt on ST2 event is
desired.
CSR
501
Remarks
KWV11-A
Table 3
Bit No.
CSR Bit Settings for Mode 0, Single Interval (Cant)
CSR
Name
Bit Condition
as Written by
Processor
Remarks
13
ST2GO
ENA
x
Set to 1 by program if GO
is to be set by external
signal to ST2. Cleared by
leading edge of GO bit assertion.
12
11
10
FOR
010
MAINT
OSC
MAINTST2
MAINT ST1
OVFLO
FLG
(0)
0
0
Will be set to 1 by counter
overflow. Always cleared
by leading edge of GO bit
assertion.
6
INTOV
x
5
4
3
RATE 2
RATE 1
RATEO
MOOE1
MOOEO
GO
x
x
x
0
0
x
9
8
7
2
1
0
0
0
(0)
. Set to 1 by program for interrupt on counter overflow.
See Table 2.
Set by program to O.
Set by program to O.
Set by program to 1 unless ST2 GO ENA is set;
remains 1 until written to 0
by program. Cleared
when counter overflows.
x = 0 or 1, depending on user requirements.
(0) = Automatically cleared by GO bit assertion.
502
KWV11-A
Mode 1 (Repeated Interval)
Control code for operation In mode 1 must support the following sequence:
1. The control program writes the desired count (2's complement)
into the BPR.
2. The program writes the control code into the CSR as indicated In
Table 4.
3. If the GO bit Is set high, KWV11-A responds by loading the 16-bit
counter from the BPR and enabling the counter; if the GO bit Is set
low and the ST2 GO ENABLE bit is set high, KWV11-A walts for
ST2 event, then sets the GO bit and loads and enables the counter.
4. The counter increments until overflow.
5. KWV11-A reloads the counter from the BPR, re-enables the
counter, raises the Overflow flag in the CSR, and issues an Interrupt to the processor if Interrupt is enabled.
6. If a second overflow occurs before the first is serviced (i.e., If
Overflow flag is still high when next overflow occurs), the KWV11A Flag Overrun (FOR) bit in the CSR is set high to alert the program that data has been lost.
7. The program responds to the interrupt or intervenes in consequence of other criteria. The program reads the CSR, clears the
Overflow flag, and if no counting or mode changes are required,
sets the GO bit or the ST2 Go Enable bit to re-enter the sequence
at step 3.
Table 4
CSR Bit Settings for Mode 1, Repeated Interval
Bit No.
CSR
Name
Bit Condition
as Written by
Processor
15
ST2 FLG
o
Will be set to 1 on ST2
event. Cleared by leading
edge of GO -bit assertion
except when ST2 GO ENA
has previously been set.
14
INT2
x
Set to 1 by program If Interrupt on ST2 event is
desired.
503
Remarks
KWV11·A
Table 4
Bit No.
CSR Bit Settings for Mode 1, Repeated Interval (Cont)
CSR
Name
Bit Condition
as Written by
Processor
Remarks
13
ST2GO
ENA
x
Set to 1 by program if GO
is to be set by external
signal to ST2. Cleared by
leading edge of GO bit assertion.
12
11
FOR
010
MAl NT
OSC
MAINTST2
MAINT ST1
OVFLO
FLG
(0)
0
0
Will be set to 1 by counter
overflow. Always cleared
by leading edge of GO bit
assertion.
6
INTOV
x
5
RATE 2
RATE 1
RATE 0
MOOE1
MOOEO
GO
x
x
x
0
1
x
10
9
8
7
4
3
2
1
o
x=
(0)
0
0
(0)
Set to 1 by program for interrupt on counter overflow.
See Table 2.
Set by program to 1.
Same as for Mode 0, except that bit is not cleared
when counter overflows.
0 or 1, depending on user requirements.
= Automatically cleared by GO bit assertion.
Mode 2 (External Event Timing)
Control code for operation in mode 2 must support the following sequence:
1. The program writes the control code into the CSR as indicated in
TableS.
2. KWV11-A responds by incrementing the counter (cleared when
504
KWV11-A
3.
4.
5.
the GO bit was cleared) at the selected rate until the GO bit Is set
toO.
ST2 pulse loads the current counter contents into the SPR, sets
the ST2 flag, and generates an interrupt if INT 2 is enabled.
Overflow sets OVFLO FLG high and, If INT OV bit Is high,
generates an interrupt.
The counter continues to increment until the processor sets the
GO bittoO.
Normally, the program enables the INT 2 and/or INT OV bits, permitting the processor to synchronize its operations with the external ST2
events and prevent loss of data by reinitializing the process after step
4.
Table 5
Bit No.
CSR Bit Settings for Mode 2, External Event Timing
CSR
Name
Bit Condition
as Written by
Processor
Remarks
15
ST2 FLG
0
Will be set to 1 on ST2
event. Cleared by leading
edge of GO bit assertion
except when ST2 GO ENA
has previously been set.
14
INT2
x
Set to 1 by program if interrupt on ST2 event is
desired.
13
ST2GO
ENA
x
Set to 1 by program If GO
is to be set by external
signal to ST2. Cleared by
leading edge of GO bit assertion.
12
11
10
FOR
010
MAINT
OSC
MAINTST2
MAINT ST1
(0)
0
0
9
8
0
0
505
KWV11·A
Table 5
Bit No.
CSR Bit Settings for Mode 2, External Event Timing (Cont)
CSR
Name
Bit Condition
as Written by
Processor
Remarks
7
OVFLO
FLG
(0)
Will be set to 1 by counter
overflow. Always cleared
by leading edge of GO bit
assertion.
6
INTOV
x
Set to 1 by program for interrupt on counter overflow.
5
4
3
2
1
RATE 2
RATE 1
RATE 0
MODE 1
MODEO
GO
x
x
x
1
o
See Table 2.
Set by program to 2.
0
x
Set by program to 1 unless ST2 GO ENA Is set;
remains 1 until written to 0
by program. Cleared
when counter overflows.
x = 0 or 1, depending on user requirements.
(0) = Automatically cleared by GO bit assertion.
Mode 3 (External Event Timing from Zero Base)
Operation is identical to that in mode 2 except that the counter is
cleared after the ST2 pulse. The counter continues to increment until
the GO bit is set to O.
Note that the interval between two ST2 events may be measured
directly in mode 2 or 3 with processor assistance if the CSR ST2 Go
Enable and interrupt 2 bits are set before the first event and the GO bit
is left clear. Under these conditions, the first ST2 event will set the GO
bit (and thus start the counting process) and simultaneously Issue an
interrupt. If the interrupt service routine now clears the ST2 flag bit, the
next ST2 event will cause the SPR to be loaded from the counter In the
normal mode 2 fashion. The chOice of mode 2 or mode 3 for such
506
KWV11-A
measurements will depend on whether or not an on-going accumulation of time after the second event is required by the application. If
such an accumulation is necessary, mode 2 is appropriate since the
counter is not cleared after 5T2 events.
User Connections
A 40-pin type 854 connector (J1) is provided on the KWV11-A for user
connections as shown in Figure 8. This connector will mate with an
H856 connector. External user-supplied slope and level controls can
be interfaced via this c~nnector as shown in Figure 9. J1 can be connected to the optional H322 distribution panel for convenient user
access, via an optional BC08R cable.
*
ST 2 OUT L
ST 1 OUT l
A
B
e
0
E
F
H
J
K
l
M
N
P
R
S
T
U
V
+3V
-:!r
POT 2
W
x
y
Z
AA
BB
ee
DO
EE
FF
HH
JJ
KK
II
MM
NN
PP
RR
SS
TT
UU
VV
POT 1
SLOPE 2
SLOPE 1
elK OV l
-:!r
ST 2 IN
ST 1 IN
t
BOARD SIDE
Figure 8
11-4175
J 1 40-Pln Connector Pin Assignments
507
KWV11-A
J'
J
EXT STl
LEVEL POT
15 20KI
f---
EXT ST2
LEVEL POT
15 20KI
L
RIg
RIB
NN OR PP
(BOTH ARE GND.)
EXTERNAL
SLOPE I
N
SWI~H
T
S2
ON
i
Ex7ERNAL
SLOPE 2
~'T.sH
R
BOARD
HANDLE
OFF
ON
OFF
OFF
OFF
UNUSED
BOARD
FINGERS
NOTE'
For proper operation of external level controls, bath RI8 and RI9
on KWVII- A board musl be sel 10 appraaimale mid· poinl of
rOlallon, and Ihe S2 swilches muSI be sel as shawn.
Figure 9
Connecting External User-Supplied Slope and level
Controls
In addition, two tabs (ClK and ST1) are located on the module as
shown in Figure 2. These tabs are electrically connected to J1 pins RR
(ClK OV l) and UU (ST1 OUT l); the tabs may be used to connect the
KWV11-A functions to ADV11-A TAB S (external start) and TAB C
(clock overflOW), respectively, in an ADV11-A. Optional jumpers (DEC
part no. 70-10771) are available for this purpose.
508
KWV11-A
PROGRAMMING
Record the point in double-precision timeframe for each S12 event
following GO. The program makes use of a 32-bit counter, the loworder bits of which are taken directly from the KWV11-A (KWBPR) and
the high-order bits of which are taken from a software counter (HICNT)
that is incremented with each KWBPR overflow.
MTPS
,,"ov
10
MOV
';'OO,UT2PSw
'STlS~V,
'ST3VEC
,CLUII PIW
,LOAC ST3 VEcro~
,ADUia
,SET UP PS_ ro~ 113
,1NIE~~UPT
(DI1AB~E
,ALL SU8SEQUENT
, 1 N1ER~UPTl)
t-'OV
'UUi~V,
MOV
'lOO,lIOVPSW
lIUVVEC
,LOAD OV VECTOR
, ADi)!.
,SEt UP
psw
'l~IE~PUPT
OV
FO~
(DIIA8~E
,ALL SU8SEQUENT
,J.r.n,JiRUPTS)
UP
,~El
POI~TE~
,BEGI~NING
,BUHE.I<
TU
,OL~05IT lMHZ, MOUE 2,
,INt UV EM, INT SI2 EN,
,ANU GO INTO t/0123456789:;< =
>?@
ABCDEFGHIJKLMNOPQRS
TUVWXYZ[\]L
96-Character set
All of the above plus a through z:
Type
Open Gothic print
Size
Typically 0.024 cm (0.095 in.)
high; 0.065 cm (0.025 in.) wide
518
LPV11
Code Format
ASCII
Characters per line
132
Character drum speed
64-character drum: 1200 r/min
96-character drum: BOO r/min
Printer Characteristics
Format
Top-of-form control; single line
advance with automatic perforation step-over, and carriage return. Automatic vertical format
control is optional.
Paper-Feed
One pair of pin-feed tractors for
1.27 cm (% in.) hole center, edgepunched paper.
Paper Slew Speed
50.B cm (20 in.) per second
Print Area
33.53 cm (13.2 in.) wide, left justified
Character Spacing
(horizontal)
0.254 ±0.0127 cm (0.1 ±0.005
in.) between centers; maximum
possible accumulative error for
normal spacing is 0.0254 cm (0.01 in.) per BO- or 132-character
line.
Line Spacing
0.424 ±0.025 cm (0.167 ±0.01
in.) at 6 lines per inch; 0.3175 cm
(0.125 in.) at B lines per inch.
Each character within ±0.254 cm
(0.1 in.) from mean line through
character.
50 msec maximum
Line Advance Time
Variable reluctance pick-off
senses drum position.
Character
Synchronization
Physical Characteristics
Height
Width
Depth
Weight
1.14 m (45 in.)
0.B1 m (32 in.)
0.56 m (22 in.)
150 kg (330 lb.)
519
LPV11
Ribbon Characteristics
Type
Width
Length
Thickness
Paper Characteristics
Type
Inked roll
38.1 cm (15 in.)
18.288 m (20yd)
0.01 cm (0.004 in.)
Standard fanfold, edge punched,
27.94 cm (11 in.) between folds
Width
10.16 cm to 42.55 cm (4 in. to 163/4 in.)
Weight
15-lb. bond minimum (single copy) 12-lb. bond with single-sheet
carbon for up to six parts (multiple copy)
Envi ron mental
Operating Temperature
Humidity
Print Rates
LP05-VA, -VB, -VC, -VD
(64-character drum)
LP05-WA, -WB, -WC, -WD
(96-character drum)
LA 180 DECprinter
Power
Printable Characters
10° to 32° C (50° to 90° F)
30 to 90% (no condensation)
300 lines per minute
240 lines per minute
90-132 Vac or 180-264 Vac
50 or 60 Hz ± 1 Hz
400 W max (printing)
200 W max (Idle)
96 upper- and lowercase character set (7 X 7 dot matrix):
+,-.10123456789
:;<=>?@
ABCDEFGHIJK
LMNOPQRS
TUVWXYZ
[\]Labcdef
ghijklmnopqr
stuvwxyz
I~l-!"#$%&'O*
520
LPV11
Code Format
ASCII
Non-printable Characters
Six Commands: BEL, BS, LF, FF,
CR, DEL
Number of Characters per Line
132 max
Type of Character Transfer
Parallel (7 -bit plus parity)
Printer Characteristics
Print Cycle Speed
Up to 180 characters per second
Line Printing Speeds
70 lines per minute on full line
300 lines per minute on short
lines
Print Size
0.254 cm (10 characters per inch)
horizontal
0.233 cm (6 lines per inch) vertical
DESCRIPTION
General
The M8027 interface module comprises functions that control the flow
of data between the LSI-11 bus and the line printer (see Figure 1). The
interface signals are different for the LP05 and the LA 180 line printers,
but the LPV11 detects a ground in the interface cable. and automatically configures itself for the proper printer. Each function of the interface is described in the following paragraphs. The LA 180 and LP05
strobe timing diagrams are shown in Figures 2 and 3.
521
LPV11
en
t:
o
tit:
::1
u.
.2
0')
o
...J
Q)
~
Q)
.E
T""
>
a.
...J
522
LPV11
PDEMANDH
IE1&·11
DEMAND H
IE7·121
READY H
IE15-S1
----'1
------IJ
READY' ERR
DE~~~~:'
_ _ _ _ _ _ _ _~~
READY' ERR L
\E21·6)
READY FLAG H
IE23-141 _ _ _ _ _ _ _--l1-'l
ROSTA H
IE&171 _ _ _ _ _ _ _ _-'1
BIRO L
IE&81
DATA STROBE H
IE2·101
LPSTROBE L
IE16-81
MSTROBE
IE211-Bl
PSTROBE
IE211-10) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _'1
NOTES:
1. TIMING SHOWN IS TYPICAL. AND SHOWN
FOR REFERENCE PURPOSES ONLY
2. TIMING SHOWN WITH JUMPER W1 INSTALLED
3. I
I a INTEGRATED CIRCUIT PINS.
4. TIME IS DETERMINED BY LPOS PRINTER LOGIC.
11·5638
Figure 2
LP05 Internal Timing
523
LPV11
PDEMANDH
(E16-11
DEMANDH
(E7-121 _ _ _- ' I
READYH
(E16-51
_ _ _ _""""'I
READY. ERR H
DELAY CKT
(E21-51
-----r
READY 'ERR L
(E21-61
READY FLAG H
(E23-141 _ _ _ _ _ _
-+J"
RQSTA H
(E6-171
-------"'1
BIRQL
(E6-81
DATA STROBE H
(E2-101 _ _ _ _ _ _ _ _ _
~
PSTROBE
(E28-101
NOTES:
1_ JUMPER W1 INSTALLED (REQUIREDI FOR TIMING SHOWN_
2_ TIMING IS TYPICAL, AND SHOWN FOR REFERENCE PURPOSES ONL Y_
3_ (
10 INTEGRATED CIRCUIT PINS_
11-6637
Figure 3
LA 180 Internal Timing
Bus Transceivers and Drivers
Bus transceivers (DEC 8641) receive the LSI-11 bus BDAL (0:7) L
signals and distribute the bits on DAL (0:7) H lines. In addition, they
transmit LPCS bits or interrupt vector address bits during a DATI bus
cycle or interrupt sequence. Bus drivers (DEC 8881) transmit LPCS
bits 8 and 15 during a DATI bus cycle in which the LPCS is addressed.
524
LPV11
Device Address Decoding
Device -address decoding logic receives DAL (2:7) H, BDAL (S:12) L,
and BBS7 signals and compares the address to the device address
jumpers; when the LSI-11 bus address bits 2 through 15 equal the
jumper-configured address for the LPV11, ENB H goes active. Note
that address bits 13, 14 and 15 are not decoded by the LPV11; the
processor asserts BBS7 when these bits are all logical 1s, indicating
an address is present in bank 7. In addition, address bits (0:2) are
decoded for the device register (and byte) in the bus control logic. Bus
control logic programmed transfer functions are enabled by the active
ENB H signal.
Print Data Transmission
Print data is transmitted to the printer from the LSI-11 bus under
program control. The print character buffer functions as the LPDB
register. It is an S-bit register, including the optional parity/OS bit. The
bus control logic produces WRITE DB H during a DATO or DATOB bus
cycle in which the LPDB is addressed. Jumper WS can be removed to
disable program transfer of LPDB bit 7 to the printer. When WS is
removed, P DATA S is forced low; if desired, jumper P can be installed
to force P DATA-S high.
Uppercase translation logic gives the user the option to print upper/lowercase data files on an uppercase letters-only printer (LPQ5VA, VB, ve, VD). Software overhead is reduced by performing the
lowercase to uppercase translation in hardware, rather than in
software. Jumper W7 normally applies unmodified upperllowercase
ASCII characters to the print character buffer. When the lowercase to
uppercase letters translation is desired, jumper W7 is removed and
jumper T is installed. The result is that ASCII codes 140 through 177
are translated to 100 through 137 (bit 5 = 0), as shown in Table 2.
Read Data Select Logic
Read data select logic functions enable the processor to read the
LPCS register under program control or the LPV11's interrupt vector
during an interrupt transaction. Control Signals READ CS H and VECTOR H select the bits. LPCS bits are produced by various LPVo11
interface functions as shown in Figure 1.
525
LPV11
Table 2
Uppercase-Only Code Translation
ASCII Input
Code
140
141
142
143
144
145
146
147
150
151
152
153
154
155
156
157
160
161
162
163
164
165
166
167
170
171
172
173
174
175
176
177
Character
a
b
c
d
e
f
9
h
j
k
I
m
n
0
p
q
r
5
t
u
v
w
x
Y
z
I
I
I
t
DEL
ASCII Output
Code
100
101
102
103
104
105
106
107
110
111
112
113
114
115
116
117
120
121
122
123
124
125
126
127
130
131
132
133
134
135
136
137
526
Character
@
A
B
C
D
E
F
G
H
I
J
K
L
M
N
0
P
a
R
5
T
U
V
W
X
Y
Z
[
\
]
t
LPV11
Ready Flag and LP Strobe Logic
The ready flag (LPCS bit 7) and line printer (LP) strobe logic provide
the proper control signal interface to the printer. The LP strobe function is used only for LP05 printers. The LA 180 uses the DATA STROBE
H signal generated by the bus control logic. Selection of the appropriate strobe source is automatically produced by the LA/LP select logic
function. Connecting the proper interface cable for the LA180 grounds
the SELECT line, causing the LA/LP select logic to select LA180 (data
selector port B) functions. When the LP05 is used, the interface cable
does not ground the line and LP05 (data selector Port A) functions are
selected. The LA180 strobe is a negative-going pulse. The LP05 strobe
is a positive-going pulse initiated by the leading edge of P DEMAND H
and cleared by the trailing edge of P DEMAND H.
The ready flag is produced by the logiC function when the printer is
requesting a character (P DEMAND H goes active) and no error is
present. In addition to setting the LPCS ready flag, the RaST A signal
input to the interrupt logic goes active; if Interrupts are enabled (LPCS
bit 6 is set), an interrupt request Is initiated (BIRa L goes active). The
ready flag is cleared by an active DATA STROBE L signal when writing
a new character into the print character buffer.
When an error condition occurs In the printer, the printer asserts P
FAULT L. The fault is applied to the error flip-flop logic (via the M
FAULT H signal), producing an active ERROR L signal and an active
ERROR H signal (LPCS bit 15). The ready flag logic function responds
by not producing a ready flag, although P DEMAND H may be active,
and by producing an active RaST A H signal. Thus, an error condlton
will initiate an interrupt request (if LPCS bit 6 is set) and set LPCS bit
15. The error flag is cleared by the processor reading the LPCS register if the ready flag is not set, or when the LPV11 interrupt vector is
read.
Error Filter
The error filter is always used (automatically selected) with the LA 180
printer and jumper-selected for optional use with the LP05 printer.
This function is produced by a clock pulse generator/counter circuit
that requires an active P FAULT L signal for 8 ms before the M FAULT
H Signal is produced. The minimum time requirement for the fault
signal presence prevents false errors due to noise.
BRPLYDelay
Bus control logic generation of BRPLY L signals is delayed 400 ns
(approximately) by factory-installed jumper W1. W1 connects C3 to
527
LPV11
the OC004 RxCx input pin, delaying the BRPL Y L signal for proper
operation with LA 180 printers. When LP05 printers are used, the
jumper may be either left installed or removed to reduce the BRPL Y
delay, as desired.
Initialization
The processor initializes devices on the LSI-11 bus by asserting BINIT
L. BINIT L is received by the interrupt logic and distributed as the INIT
L signal. INIT L clears the print character buffer, error flip-flop logic,
and interrupt enable bit (LPCS bit 6), and sets the ready flag.
LP05 Line Printers
LP05 printers use a 132-column, 64- (lPV11-VA, -VB, -VC, -VO) or 96(LPV11-WA, -WB, -WC, -WO) character rotating drum, and solenoiddriven hammers to print characters. Characters are transmitted to the
LP05's print buffer under program control via the M8027 interface
module. The LP05 print buffer stores up to a 132-character line. Each
print cycle is initiated by a terminating character. Terminating characters include carriage return (CR), line feed (LF), and form feed (FF).
Printing requires two revolutions of the drum. Odd-numbered and
even-numbered columns are printed during alternate revolutions of
the drum. Circuits in the LP05 scan the print buffer characters stored
for a line in synchronization with the rotating drum. Each character is
printed, as appropriate, by driving the hammmer for those odd- or
even-numbered columns ·in which a particular character appears. An
inked ribbon and paper pass between the drum and the hammers,
and thus the characters are printed.
Note that LP05 printers are available with uppercase letters only (64character set) or upper- and lowercase letters (96-character set), depending on the model. All models are capable of printing numerals
and punctuation marks.
LA 180 DECprlnter
The LA 180 OECprinter included with LPV11-PA, -PB, -PC, and -PO
models is a free-standing, pedestal-type impact printer that is capable
of printing a maximum of 132 characters per line. To initiate a print
cycle, a line terminator character (IF, FF, or CA) is required. The
printer contains a 256 by 8 character buffer, which stores printable
and nonprintable characters. This buffer is loaded character-by-character via the LPV11 interface under program control. After each character is stored in the buffer, a read function is performed to determine
if the character is a line-terminator character. If it is, the characters
528
LPV11
stored in the buffer are printed; if it is not, the next characters are input
until the complete line is stored, as indicated when the line-terminator
character is received and stored.
Each character is transferred to the printer as a parallel 7 -bit ASCIIplus-optional parity code. The printer is a high-speed dot matrix
printer that prints at speeds up to 180 characters per second. It produces a hard copy original plus up to five duplicate copies on tractordriven, continuous forms, varying in width from 10.2 cm (4 in) to 37.8
cm (14-7/8 in). The average printing speeds are 70 lines per minute on
full lines. The printer responds only to codes representing the LA 180
character set and six command characters. All other codes are ignored.
CONFIGURATION
General
The M8027 interface module is shipped from the factory with jumpers
configured for standard (DIGITAL software-compatible) device and
interrupt vector assignments. It is normally not necessary for the user
to configure the address or vector jumpers, unless special device
addresses and/or interrupt vectors are desired. The factory-installed
jumpers are shown in Figure 4. These jumpers can be removed by
carefully cutting each end close to the printed circuit board. In addition
to the factory jumpers, there is an alternate set of wire-wrap pins that
allow the user to install additional or replacement jumpers by using
the designated wire-wrap pins. In Figure 4, the dots represent wirewrap pins and a line indicating a pair of pins shows the electrical
connection that must be wire-wrapped to insert that jumper. Table 3
lists the factory jumpers that can be installed and the additional jumpers installed, as well as the associated functions. The factory-set addresses are listed in Table 4.
NOTE
Jumpers F+ (factory-installed W6) and F- do not
have associated wire-wrap pins. These jumpers
must be installed by soldering and removed by cutting or unsoldering.
529
LPV11
Table 3
Jumper Designations
Jumper·
Function
Jumper·
Function
A3
A4(W2)
A5(W3)
A6
A7(W4)
A8
A9
A10
A11
A12
F(W6)
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Error Filter
P
T(W7)
V2(W9)
V3(W10)
V4(W11)
V5(W12)
V6(W13)
V7
V8(W14)
W1
Parity
Translate to Uppercase
Interrupt Vector
Interrupt Vector
Interrupt Vector
Interrupt Vector
Interrupt Vector
Interrupt Vector
Interrupt Vector
Bus Reply Timing
* Jumpers without W designation are not normally installed by factory.
530
LPV11
NOTES:
W2. W3. W4. WI. wa. WB. MD. M1.
W12. W13. W14 WIRE-WRAP JUMPERS
WOULD NORMALLY BE USED TO
REPLACE PREVIOUSLY REMOVED
FACTORY -INSTALLED 1..,...1
JUMPERS ISHOWN INSTALLEDI _
_
IRE WRAP PIN
STANOARD
CONFIGURATION IS
INDICATED BY !WI
JUMPERS_
Figure 4
LPV11 Interface Module
531
LPV11
Table 4
Standard Assignments
Description
Read!
Mnemonic Write
Registers
Control/Status
Data Buffer
LPCS
LPDB
R/W
R/W
Interrupts
Done or Error
First
Second
Module
Module
Address
Address
177514
177516
(Use floating
address space)
200
(Use floating
vector space)
Device Address
The LPV11 is factory-configured for a device control/status register
(CSR) address equal to 177514. The data buffer register (DBR) is
always the configured CSR address +2; thus, the standard DBR address is 177516. If more than one LPV11 option is installed in the
system, or if special device addresses are desired, remove and/or
install jumpers (one for each CSR address bit) as directed in Figure 5.
BITS
DEVICE ADDRESS
,.....,...-,r--....-,,-....
15
11
-,-"T"""~-~~~.,....:~-=-~=-r-~~:....
FORMAT
FACTORY
CO~~U::7~1~~
LPDB = 177516
R
~
I
I
I
..
..
~
I
..
A12
All
AID
I
AS
I
AS
A7
IW41
..
I
I· I
~
~
..
A6
AS
IW31
A4
IW21
I
..
A3
JUMPER
(FACTORY INSTALLEDI
I=INSTALLED=LOGICAL=D
R=REMOVED=LOGICAL=1
"·5523
Figure 5
LPV11 Device Address Format and Jumpers
532
LPV11
Interrupt Vector
The LPV11 is factory-configured for an interrupt vector equal to 200 8 ,
If more than one LPV11 option is installed in the system, or if a special
interrupt vector is desired, remove and/or install jumpers (one for
each vector bit) as directed in Figure 6.
BITS
VECTOR
AF~'!:~
15
14
09
08
07
06
05
04
03
02
01
00
°....a.....
0 ....1..-,1--,-I..........
1 1...,.,..--101.......-0........,..1
0 .............
1 0...........
1 ,........0
1--,,0
1----,0I
1 --'---1..--,----,--1
,-0 I-,--I
FACTORY
CONFIGURATION
° 200
lolNSTALLEOoLOGICAL 0
RoREMOVEDoLOGICAL 1
Figure 6
JUMPER
CFACTORY INSTALLED)
III 1 1 1 1
I
R
I
I
I
I
I
1 1 ttl 1 1
V9
CW14)
V7
V6
V5
V4
V3
CW13) CW12) CW111 CW10)
V2
CWB)
LPV11 Interrupt Vector Format and Jumpers
Bus Reply Timing
Jumper D (W1) is factory-installed to delay the BRPL Y L bus signal
timing for LPV11 use with LA180 printers. If desired, this jumper can
be removed for use with future printers; however, the LP05 will function if it is left installed.
Uppercase Only
Jumper W7 is factory-installed and jumper T is not installed, enabling
upper- and lowercase letters to be printed. If lowercase letters are not
desired, remove W7 and install jumper T. This will cause the LPV11
interface to translate all lowercase letters to uppercase letters before
transmission to the printer. This feature will allow printing files configured for 96-character printers on 64-character printers with minimum
software overhead.
Do not configure the module with both jumpers W7 and T installed.
533
LPV11
Parity
Jumpers WB and P select the desired parity mode. The LPV11 is
factory-configured with WB installed and jumper P not installed,
enabling parity bit 7 to be transmitted to the printer. Configure the
parity option desired as follows:
Parity Option
Jumper we
Jumper P
Normal parity bit
No parity, bit 7 low
No parity, bit 7 high
Installed
Removed
Removed
Removed
Removed
Installed
Do not configure the module wih both jumpers WB and P installed.
NOTE
If the LPV11 interface module is used with an LP05
printer equipped with the Direct Access Vertical
Form Unit (DAVFU), it is recommended that the user
remove jumper WB. The LPV11 interface module
does not support the DAVFU function.
Error Filter
The LPV11 interface module contains an error filter (time delay) circuit
that is automatically selected when the module is used with an LA 1BO
DECprinter. Jumper F+ (W6) is factory-installed, selecting the error
filter for use with LP05 printers; however, its use with LP05 is optional.
If desired, remove the error filter by removing jumper W6 and installing jumper F-. Do not configure the module with both F- and W6
installed.
LPV11 Device Registers
All programmed communication with the LPV11 option is via two device registers in the LPV11 interface module. These registers include
the line printer control and status (LPCS) and line printer data buffer
(LPDB). These registers are factory-configured with LSI-11 bus addresses 177514 and 177516, respectively, and are software-compatible with DIGITAL software. However, if additional LPV11 options are
added to the system, or if the user requires addresses other than
those factory-configured, it will be necessary to alter interface module
jumpers and provide an LPV11 program using these special device
addresses. Each register is described in Tables 5 and 6 and both are
shown in Figure 7.
534
LPV11
LPCS
ERROR
(READONLYI
DONE
(READONLYI
ON LINE
(READ-ONLYI
INTERRUPT ENABLE
(READIWRITEI
BUSY
(READ-ONLYI
(,7" ' , " ' , ' III ' 00,1
LPDBj"
' - - -- - T _ - - - J "
(NOTUSEDI
PARITY 07
OR D8
(OR PAPER
INSTRUCTION
FOR LP061
D6
D6
.
D4
03
D2
Dl
v
(READIWRITEI
Figure 7
Table 5
LPV11 Word Formats
LPCS Register Bit Functions
Bit: 15
Name: Error
Description: Asserted (1) whenever an error condition exists in the
line printer. Error conditions include:
LP05 Errors
1. Power off
2. No paper
3. Printer drum gate open
4. Over-temperature alarm
5. PRINT INHIBIT switch off
6. Print~r off-line
7. Torn paper
LA 180 Errors
1. Fault (paper fault)
2. On-line switch (in OFF position)
Reset by manual correction of error condition if LPCS bit 6 is not set. If
bit 6 is set, bit 15 is reset by manual correction of the error and: (1)
reading the interrupt vector if the interface is "ready," or (2) after
reading the LPCS if the interface is "not ready)' Read-only.
535
LPV11
Bit: 14-8
Name: Not used
Description: Read as Os.
Bit: 7
Name: Done
Description: LP05-Asserted (1) whenever printer is ready for next
character to be loaded. Indicates that previous function is either
complete or has been started and continued to a point where the
printer can accept the next command. This bit is set by the processor
asserting BINIT L; if bit 6 is also set, an interrupt sequence is initiated.
Also set by the printer. when on-line and ready to accept a character.
Cleared by loading (writing into) the LPDB register. Inhibited when bit
15 is set. Read-only.
LA 180-Asserted (1) when the printer is ready to accept another character. Done is set by the processor asserting BINIT L and is cleared by
loading (output transfer to) the LPDB register. If the Interrupt Enable
bit is set, setting Done will initiate an interrupt request.
Bit: 6
Name: Interrupt Enable
Description: Set or cleared by the program. Also cleared by the
processor asserting BINIT L. When set, an interrupt sequence is initiated if either the Error or Done bit is set.
Bit: 5-2
Name: Not used
Description: Read as Os.
Bit: 1
Name: On Line
Description: Not supported and- not required by DIGITAL software.
The following information is provided for reference only.
LA 180-Set when the LA 180 is on-line. Read-only.
LP05-Not used. Read as O.
Bit: 0
Name: Busy
Description: Not supported and not required by DIGITAL software.
Information is provided for reference only.
LA180-Set when the LA180 is printing a line or advancing paper.
LP05-Not used. Read as O.
536
LPV11
Table 6
LPDB Register Bit Functions
Bit: 15-8
Name: Not used
Description: Read as Os. Data written into these bits is lost.
Bit: 7
Name: Parity or 08
Description: Optional use. Read as O. LA 180-0ptional parity bit.
LP05-0ptional paper instruction bit. Not supported by the LPV11.
Read asO.
Bit: 6-0
Name: Data
Description: 7-bit ASCII character register. Characters are sequentially output to the printer buffer via this register. Read as Os.
Interrupts
Programs written for use with the LPV11 are generally composed of an
interrupt-driven routine. When the LPCS register Interrupt Enable bit
is set and either the Done or Error bit is set, an interrupt request is
initiated. Entry to the LPV11 service routine is normally via the factoryconfigured vector addresses 2008 (PC) and 202 8 (PS). When servicing an interrupt and a second interrupt occurs, the second (and subsequent) interrupt may not be recognized. This condition can be
avoided by checking for both interrupt conditions (Done and Error) in
the interrupt service routine.
537
REV11-A, -C
REV11·A TERMINATOR,
REV11·C DMA REFRESH, BOOTSTRAP
GENERAL
The REV11-A DMA refresh. bootstrap/terminator module consists of
DMA refresh circuits. a bootstrap ROM. and 120-ohm termination circuits. The REVll-C is similar to the REVll-A. but does not have the
120-ohm termination circuits.
FEATURES
•
Dynamic MOS memory refresh
•
ROM programs for booting paper tapes. RXV11 floppy disks. and
RKV 11 cartridge disks
•
ROM diagnostics for CPU and memory
•
120-ohm LSI-ll bus terminations (REV11-A only)
SPECIFICATIONS
Identification
M9400- VA (REV11-A)
M9400-YC (REV11-C)
Size
Double
Power
+5 V ±5% at 1.64 A (REV11-A)
+5 V ±5% at 1.0 A (REV11-C)
Bus loads
AC
DC
2.2
1
DESCRIPTION
Addressing - The module includes a 512 X 16-bit ROM array that is
addressed in two 256-word segments. These address segments are reserved for REVll options and reside in the upper 4K address bank.
normally used for peripheral device addresses. The reserved addresses
range from 165000-165776 and 173000-173776. A power-up mode.
which will cause the processor to access ROM location 173000 upon
power-up. is jumper-selectable on the processor module.
538
REV11-A, -C
Initialization - The bootstrap ROM logic is initialiled only when BOCOK
H goes fi:llse. This condition occurs during a power failure and produces
active BO INIT Hand BO INIT L signals. These signals clear the 9-bit
address latch and circuits contained in the OMA refresh logic. The option
does not respond to (he LSI-11 bus BINIT L signal.
Terminations (REV11-A Only)
Each bus signal line terminates with two resistors as shown in Figure 7.
These termination resistors are generally contained in a 16-pin. dual-inline package which is identical to an IC package. Each package contains
14 termination pairs. The values used are shown in the figure. Oaisychained grant signals are terminated and it..:mpered. BJAXI L is jumpered
(with etch) to BIAKO L. and BDMGI L is connected to BDMGO L via
factory-installed jumper W 1.
CONFIGURATION
•• 1ar:....
(IIABL(
....
··II!8::TSTRAP
"
BBBB
Figure 1
W2
W4
REV11-A, -C, Jumpers
Insert to enable DMA refresh.
Insert to enable bootstrap ROM.
539
REV11-A, -C
PROGRAMMING
Using REV11-A and REV11-C Commands
General - The REV11 hardware option contains programs stored in
read-only memory. The normal starting address for the program is
173000. When started at this location, the program executed is a nonmemory modifying processor test. If no errors are detected, the program outputs a dollar-sign ($) for display on the console device. This
character is the prompt character for the operator to enter a command.
The starting address can be entered and program operation started
either manually, using the c'onsole OOT GO command, or automatically during power-up. Automatic operation is accomplished by selecting
power-up mode 2 by appropriately configuring jumpers on the processor module. The normal power-up response for this mode results in
the console device displaying the $ prompt character instead of the @
console OOT prompt character.
Unsuccessful execution of the non-memory modifying processor test
program results in the $ prompt character not being displayed.
Instead, the program hangs (branch to self) when a sequence of instructions does not execute properly, or the processor halts due to a
double bus error. A halt normally results in the console terminal displaying the PC contents (the address of the halt +2) followed by the
console OOT prompt character.
REV11-A and REV11-C Command Set - Once the $ prompt character is displayed, the operator can enter one of the commands described in Table 1. Note that in the command examples, characters
printed by the program are shown underlined; characters not
underlined are entered by the operator. Command inputs to the program can be either be upper- or lower-case characters. If an invalid
command is entered following the $ prompt character, the program
responds by displaying ? after the invalid command and a new $
prompt character on a new line. For example, program response to
the invalid "XJ" command is shown below:
$XJ?
$
NOTE
The function in Table 1 represents the nonprintable character "carriage return," which is recognized as an execute command.
540
REV11-A, -C
Table 1
REV11 ROM Program Commands
Command: 00
Function:
OOT (Halt). This allows the operator to examine and/or
alter memory and register locations via the console device. Control
can be returned to the REV11 program by entering the OOT P
(proceed) command, if the PC has not been altered, and the console
device will display the $ prompt character. If the PC has been altered,
the operator can start program execution by entering the starting address 165006 and the G (go) command as follows:
@ 165006G
$
The processor responds by displaying the $ prompt character on a
new line and another REV11 command can be entered.
Command: XM
Function:
Memory diagnostic program. After successfully completing the diagnostic, the prompt character ($) is displayed on the console device. Errors are indicated by the following displays on the console device:
1.
~
@
2.
This is an address test error. The expected (normal) data Is in R3
and the invalid data is in the memory location pOinted to by R2. If
desired, continue diagnostic program execution· by entering the
ODT P command.
173756
~
This is a data test error. The expected (normal) data Is stored in
R3 and the invalid data is in the memory location pOinted to by R2.
If desired, continue diagnostic program execution by entering the
ODT P command.
3.
4.
.QQQQ!Q
~
A time-out trap has occurred in testing memory locations outside
the first (lowest) 4K memory.
nnnnnn
@
Alime-out trap has occurred in testing memory locations within
the first 4K memory. The nnnnnn displayed is an indeterminate
number.
541
REV11-A, -C
The actual test consists of an address test and a data test. The address
test first writes all memory locations with addresses; it then reads and
verifies the addresses. The data test consists of two parts. An "aIl1s"
word is first walked through all memory locations, which are Initially O.
The second part consists of walking an "all Os" word through all
memory locations which are all 1s.
Command: XC
Function:
Processor diagnostic program. This is a memory-modifying instruction test. Successful execution of the diagnostic program
results in the prompt character ($) being displayed on the console
device. Errors are indicated by:
1. The program halting when an Instruction sequence Is not correctly executed.
2. The program halting in the trap vector area for various traps.
Command: AL
Function: Absolute loader program, normal (absolute address)
loading operation. Entering AL specifies that a paper tape Is to
be loaded via the console device (CSA address = 177560). However,
another device can be specified by entering the appropriate CSA address. For example, to load paper tapes in absolute loader format via
a device whose CSA address Is 177550, enter the following command:
.!.AL 177550
The program responds by first executing the memory-modifying CPU
instruction test and memory test (refer to the XC and XM commands).
Successful test execution results in the execution of the absolute loader program.
A successful program load is indicated by the loaded program automatically starting execution or by the console device displaying:
165626
@
Absolute loader errors are:
• Checksum error, with the program halting and producing the display:
165534
@
542
REV11-A, -C
• Program halts in the trap vector area for traps other than a time-out
. trap
• Time-out trap occurs, causing the display of $ on a new line on the
console device
This program can be restarted without first executing the diagnostic
programs by the following:
1. Load R4 with 165414 (AL starting address).
2. Load the highest available memory address into R5. (For
example, if the system contains 4K of read/write memory, load R5
with 17776.)
3. Start the program at 165242.
Command: AR
Function:
Absolute loader program; relocated loading operation.
When this command is entered, the memory-modifying CPU instruction test and memory test are automatically executed first (refer to the
XC and XM commands), followed by the absolute loader program.
Successful execution of the tests results in the program halting with
the following console display:
165412
@
The operator must then enter the appropriate "software switch register" contents in R4. To select relocated loading, which uses an address (bias) contained in the software switch register, enter the following commands:
@ R4/xxxxxx nnnnnn
@P
The value nnnnnn is a relocation value selected by the
operator. Observe that the least significant "n" value entered must
be an odd 'Iumber. This sets the software switch register (R4) bit 0 to a
logical 1, selecting the relocated loading mode. Note that the program
being loaded must be in position-independent code (PIC) format for
relocated loading.
When large programs are contained on more than one tape, the program halts at the end of the tape. IFlstali the second tape in the reader,
and enter a "1" in R4 using the OOT command shown below. Resume
loading by entering the P command.
@ R4/xxxxxx 1
@P
543
REV11-A, -C
The six octal digits (xxxxxx) are the present contents of R4. Entering a
value of 1 selects relocated loading for the next program tape starting
at the address following the end of the previous load operation. The P
command allows the absolute loader program execution to continue
the loading process once the software switch register value has been
entered.
A successful program load is indicated by the loaded program automatically starting execution, or by the console device displaying:
165626
@
Absolute loader errors are the same as for the AL command.
This program can be restarted without first executing the diagnostic
programs by the following:
1. Load R4 with 165406 (AR starting address).
2. Load the highest available memory address in R5. (For example, if
the system contains 4K of read/write memory, load R5 with
17.776.)
3. Start the program at 165242.
Command: DX or DXn
Function:
RXV11 floppy disk system bootstrap. Entering the
DX command starts the memory-modifying CPU instruction
test and memory test execution. (See the XC and XM commands.)
Successful test execution results in the execution of the bootstrap
program for disk drive 0, the system disk. Or, specify the drive number
(n) as 0 (drive 0) or 1 (drive 1). Floppy disk bootstrap errors are:
1. The program halts and the console device displays:
165316
@
2.
indicating that the device done flag in the RXV11 interface was not
set within the required time (approximately 1.3 seconds). The
bootstrap can be restarted by entering the P command; the $ is
then displayed on the console device and the bootstrap command
can be entered.
The program halts and the console displays:
165644
@
544
REV11-A, -C
indicating that a bootstrap error occurred. The RXV11 error register contents are stored in R2. By examining the contents of R2 and
using the information in this handbook on the RXV11, the exact
nature of the error can be determined. Examine the cont~nts of R2
(nnnnnn) as follows:
@ R2/nnnnnn
@P
$
3.
After examining R2, the bootstrap can be restarted by the P command; enter the desired bootstrap command immediately after
the $ prompt character.
The program halts in the trap vector for traps; a time-out trap
returns the program to the $ prompt character. If a time-out trap
occurs first, check for proper system cable connections and device interface module installations. Then, attempt to successfully
bootstrap the system by again entering the desired command.
The bootstrap for disk drive 0 (OX) can be started without first executing the diagnostic programs by the following.
1. Load R4 with 165264 (the OX bootstrap starting address).
2. Start the program at 165242.
Command: DK or DKn
Function:
RKV11-0 disk drive system bootstrap. Entering the OK
command starts the memory-modifying CPU instruction test and
memory test execution. (See the XC and XM commands.) Successful
test execution results in execution of the bootstrap program for disk
drive 0, the sytem disk. Or, specify the drive number n as 0 (drive 0), 1
(drive 1), or 2 (drive 2).
Oisk bootstrap errors are:
1. The program halts and the console device displays:
1§.§lli.
@
indicating that the device done flag in the RKV11-0 interface was
not set within the required time (approximately 1.3 seconds). The
bootstrap can be started by entering the P command; the $ is then
displayed on the terminal and the bootstrap command can be
entered.
545
REV11-A, -C
2.
The program halts and the console displays:
165644
@
indicating that a bootstrap error occurred. The RKV11-0 error
register contents are stored in R2. By examining the contents of
R2 and using the information contained In the RKV11-0 option
description, the nature of the error can be determined. Examine
the contents of R2 (nnnnnn) as follows:
@R2/nnnn
@P
r-
--
After examining R2, the bootstrap can be restarted by the P command; enter the desired bootstrap command Immediately after
the $ prompt character.
3.
The program halts in the trap vector for traps; a time-out trap
returns the program to the $ prompt character. If a time-out trap
occurs first, check for proper system cable connections and device interface module installation. Then, attempt to successfully
bootstrap the system by again entering the desired bootstrap
command.
546
RKV11-D
RKV11-D RK05 DISK DRIVE CONTROLLER
SPECIFICATIONS
LSI-11 Bus Module
Identification
M7269
Size
Double
Power
+5 V ±5% at 1.8 A
Bus Loads
AC
DC
RKV11-D Controller
Input Voltage
RKV11-DA
RKV11-DB
100-127 Vac, 50/60 Hz ±1 Hz
200-254 Vac, 50/60 Hz ± 1 Hz
Input Power
140Wmax
Power Supply
H780
Line Protection
115 Vac
230Vac
5 A fast blow fuse
2.5 A fast blow fuse
LSI-11 bus backplane signal from
RKV11-D power supply
BPOKH (power supply AC LO)
BDCOKH (Bus DC LO)
Module Complement
M7254
M7255
M7256
M7268
M930
M7269
Controll Status
Disk Control
Data Paths
Bus Adapter
Drive Bus Terminator
Bus Control
1.9
1
Cables
Two 40-conductor flat 70-0902602 (to first RK05 drive)
Two 40-conductor flat BC05L (to
LSI-11 bus interface)
CONFIGURATION
General
The RKV11-D/RK05 disk drive system can be configured with up to
eight RK05-J disk drives daisy-chained on the drive bus (DR bus).
547
RKV11-0
Each disk drive must have an M7700 module of revision J or later. The
M7700 module has a rotary switch that defines the logical disk drive
DR bus position. The first disk drive on the DR bus is normally set to
switch position 1 on the M7700 module and is designated as disk drive
O. The second disk drive would then be designated as drive 1 (switch
position 2), and so on, up to the eighth disk drive (switch position 8).
This configuration (Figure 1) may be varied as DR bus length allows.
The maximum length of the DR bus is 15 m (50 ft). The DR bus must be
terminated with the M930 module at the last RK05 on the bus.
Module Jumpers
The M7269 module has jumpers to configure the interrupt vector and
device register addresses. The M7256, M7255 and M7254 modules
have jumpers to configure certain RK05 disk drive functions. The
jumpers on the M7269 module have been factory-configured for an
interrupt vector of 2208 and device addresses of 1774008 through
1774168 • These addresses are the normal user addresses and should
not be altered. Figure 2 shows the jumper locations for the interrupt
vector and device address jumpers on the M7269 module. The interrupt vector and device address word formats are shown in Figures 3
and 4 and described in Table 1.
Table 1
Description
Registers
Drive Status
Error
Control/Status
Word Count
Bus Address/Current
Memory Address
Disk Address
Unused
Data Buffer
Standard Assignments
Mnemonic
Readl
Write
M7269
Module
Address
RKDS
RKER
RKCS
RKWC
RKBA
R
R
R/W
R/W
R/W
177400
177402
177404
177406
177410
RKDA
R/W
RKDB
R (PIO)
177412
177414
177416
Interrupt Vector
Interrupt Vector
220
548
RKV11-D
Figure 1
RKV11-D/RK05 System Configuration
549
RKV11-0
c
c
J1
1
J2
1
INTERRUPT
VECTOR
JUMPERS
LSI·l1 BUS
ADDRESS
JUMPERS
-+----
MR·0857
Figure 2
M7269 Module Jumpers
550
RKV11-0
...0
, r
15
11
14
11
13
:
1
12
:
I
11
I
1
09
lU
:
1
:
1
I
08
06
07
1
0
:
:
o
I
05
04
03
o : o : o
I I I I I I I I I
----+
I I I I I I I I I
----+
JUMPER ON
M7269 MODULE
FACTORY·
CONFIGURED
ADDRESS (1774001
WI
W2
W3
R
R
R
W6
W7
W8
W12
W13
W14
R
R
I
I
I
I
I
00
01
02
o :
0
:
o
I
I g INSTALLED
R c REMOVED
DEVICE ADDRESS
MR·0803
Figure 3
15
14
13
12
JUMPER ON
::;::~~ULE - +
CONFIGURED
ADDRESS 12201
-----+
11
M7269 Device Address Format
10
09
----~----~\I'----~--~ ,---------~
08
07
06
05
04
03
02
I I I I I1 I I I
Ti i
I
I
I
wr Wi wr wr Wf7
I
R
I
I
01
00
I g INSTALLED
R g REMOVED
R
MR·OB04
Figure 4
M7269 Interrupt Vector Format
551
RKV11-0
Module Utilization
Of the six modules supplied with the RKV11-D, four are installed in the
RKV11-D controller backplane as shown in Figure 5. The M930 terminator module is plugged into the last RK05 disk drive on the DR bus,
and the M7269 double-height module is plugged into the LSI-11 bus.
The RKV11-D is a DMA device. Priority of DMA devices on the LSI-11
bus is determined by the devices' electrical distance from the processor. The DMA device closest to the processor has the highest DMA
priority.
M7254
STATUS
CONTROL
M7255
DISK
CONTROL
M7256
DATA
PATHS
M7268
BUS
ADAPTER
H780POWER
SUPPLY
MA 0762
Figure 5
RKV11-D Module Utilization
Cabling
The RKV11-D is supplied with two BC05L cables which connect the
M7269 LSI-11 bus control module to the M7268 bus adapter module.
The BC05L cables are connected from J 1 to J 1 and from J2 to J2 on
each module (Figures 2 and 6). Two 70-09026-02 cables are also
supplied for connecting J3 and J4 on the M7268 module (Figure 6) to
the RK05 M993-YA module.
TO M7269
(LSI·ll BUS)
TO M993·YA
(RK05)
M7268
MR-1629
Figure 6
M7268 Cable Connections
552
RKV11-D
Registers
The RKV11-D contains seven 16-bit programmable registers that provide software interface to the LSI-11 bus. These registers are
addressable from the processor and are listed in Table 2. The formats
for these registers are shown in Figures 7 through 13. Bit descriptions
are in Tables 3 through 9.
Table 2
RKV11-D Addressable Registers
Register Name
Mnemonic
Address*
RKV11-D Drive Status Register
RKV11-D Error Register
RKV11-D Control/Status Register
RKV11-D Word Count Register
RKV11-D Bus Address Register
(Current Memory Address)
RKV11-D Disk Address Register
RKV11-D Data Buffer Register
RKDS
RKER
RKCS
RKWC
RKBA
177400
177402
177404
177406
177410
RKDA
RKDB
177412
177416
* Address 177414 is unused.
CP 3137
Figure 7
Drive Status Register (RKDS) Address 177400
NOTE
This register is a read-only register, and contains the
selected drive status and current sector address.
Table 3
Drive Status Register Bit Descriptions
Bit: 0-3
Name: SC (Sector Counter)
Description: These four bits are the current sector address of the
selected drive. Sector address 0 is defined as the sector following the
sector that contains the index pulse.
553
RKV11-0
Bit: 4
Name: SC=SA (Sector Counter equals Sector Address)
Description: Indicates that the disk heads are positioned over the
disk address currently held in the sector address register.
Bit: 5
Name: WPS (Write Protect Status)
Description: Set when the selected disk is in the write-protected
mode.
Bit: 6
Name: R/W/S ROY (Read/Write/Seek Ready)
Description: Indicates that the selected drive head mechanism is not
in motion, and that the drive is ready to accept a new function.
Bit: 7
Name: DRY (Drive Ready)
Description: Indicates that the selected disk drive complies with the
following conditions:
a. The drive is properly supplied with power.
b. The drive is loaded with a disk cartridge.
c. The disk drive door is closed.
d. The LOAD/RUN switch is set to RUN.
e. The disk is rotating at proper speed.
f. The heads are properly loaded.
g. The disk is not in a DRU (bit 10 of RKDS) condition.
Name: SOK (Sector Counter OK)
Bit: 8
Description: Indicates that the sector counter operating on the selected drive is not in the process of ehanging, and is ready for examination. If this bit is not set, the sector counter is not ready for examination, and a second attempt should be made.
Bit: 9
Name: SIN (Seek Incomplete)
Description: Indicates that because of some unusual condition, the
seek function cannot be completed. Can be accompanied by RKER 15
(drive error). Cleared by a drive reset function.
Bit: 10
Name: DRU (Drive Unsafe)
Description: Indicates that an unusual condition has occurred in the
disk drive, and it is unable to properly perform any operations. Reset
by setting the RUN/LOAD switch to LOAD. If, when the switch is returned to RUN, the condition recurs, an inoperative drive can be
assumed, and corrective maintenance procedures should begin. Can
be accompanied by RKER 15 (drive error).
Bit: 11
Name: RK05 (RK05 Disk On Line)
Description: Always set to identify the selected disk drive as RK05.
554
RKV11-0
Bit: 12
Name: DPL (Drive Power Low)
Description: Sets when an attempt is made to initiate a new function,
or if a function is actively in process when the control senses a loss of
power to one of the disk drives. Can be accompanied by RKER 15
(drive error). Reset by BUS INIT or a control reset function.
Bit: 13-15
Name: 10 (Identification of Drive)
Description: If an interrupt occurs as the result of a hardware poll
operation, these bits will contain the binary representation of the logical drive number that caused the interrupt.
CP 3138
Figure 8
Error Register (RKER)-Address 177402
NOTE
This is a read-only register.
Table 4
Error Register Bit Descriptions
Name: WCE (Write Check Error)
Bit: 0
Description: Indicates that an error was encountered during a writecheck function as-a result of a faulty bit comparison between disk data
and memory data. Clears upon the initiation of a new function. This is a
soft error condition.
Bit: 1
Name: CSE (Checksum Error)
Description: Sets while performing a read function as a result of _a
faulty recalculation of the checksum. Cleared upon the initiation of any
new function. This is a soft error condition.
Bit: 2-4
Name: Unused
NOTE
The remaining bits of the RKER are all hard errors,
and are cleared only by BUS INIT or by a control
reset function.
555
RKV11-0
Bit: 5
Name: NXS (Nonexistent Sector)
Description: Indicates that an attempt was made to a sector address
greateF than 138 :
Bit: 6
Name: NXC (Nonexistent Cylinder)
Description: Indicates that an attempt was made to initiate a transfer
to a cylinder address greater than 312 8 • .
Bit: 7
Name: NXD (Nonexistent Disk)
Description: Indicates that an attempt was made to initiate a function
on a nonexistent drive.
Bit: 8
Name: TE (Timing Error)
Description: Indicates that' a loss of timing pulses for at least 5 p,s has
been detected.
Bit: 9
Name: DL T (Data Late)
Description: Sets during a write or write-check function when the
multibuffer file ·is empty and the operation is not yet complete. Sets
during a read function when the multibuffer file is filled and the operation is not yet complete.
Name: NXM (Nonexistent Memory)
Bit: 10
Description: Sets if memory does not respond with a RPL Y within 20
J.LS of the time when the RKV11-0 becomes bus master during a OMA
sequence. Because of the speed of the RK05 disk drive, it is possible
that NXM will be accompanied by RKER 9 (data late).
Bit: 11
Name: PGE (Programming Error)
Description: Indicates that the RKCS 10 (format) was set while initiating a function other than read or write.
Bit: 12
Name: SKE (Seek Error)
Description: Sets if the disk head mechanism is not properly positioned while executing a normal read, write, read-check, or writecheck function. The control checks 16 times before flagging this error.
A simple jumper change will force the control to check just once.
Bit: 13
Name: WLO (Write Lockout Violation)
.
Description: Sets if an attempt is made to write on a disk that is
currently write-protected.
Bit: 14
Name: OVR (Overrun)
Description: Indicates that, during a read, write, read-check, or
write-check function, operations on sector 138 , surface 1 of cylinder
address 312 8 ,·were finished and the RKWC has not yet overflowed.
This is essentially an attempt to overflow out of a disk drive.
556
RKV11-D
Bit: 15
Name: ORE (Drive Error)
Description: Sets if a function is either initiated or in process, and:
a. One of the drives in the system senses a loss of either ac or dc
power, or
b. The selected drive is not ready or is in some error condition.
UNUSED
Figure 9
UNUSED
Control/Status Register (RKCS)-Address 177404
Table 5
Control/Status Register Bit Descriptions
Bit: 0
Name: GO
Description: This write-only bit can be loaded by the operator and
causes the control to carry out the function contained in bits 1-3 of the
RKCS (functions). Remains set until the control actually begins to respond to GO, which may take from 1 J.Ls to 3.3 ms, depending on the
current operation of the selected disk drive (to protect the format
structure of the sector).
Bit: 1-3
Name: Function
.
Description: The function register, or function read/write bits, are
loaded with the binary representation of the function to be performed
by the control when a GO command is initiated. These bits are loaded
by the program and cleared by BUS INIT. The binary codlngs are as
follows:
3
0
0
0
0
1
1
1
1
Bit
2
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
Operation
Control reset
Write
Read
Write check
Seek
Read check
Drive reset
Write lock
557
RKV11-D
81t: 4,5
Name: Unused
NOTE
The RKV11-D uses these bits. Since the LSI-11 bus
structure has no provision for extended addressing,
no connection is made to the bus from these bits on
the RKV11-D. They will respond as two unused
read/write bits in the status register, but like the
RKV11-D, they will increment should the RKBA overflow.
81t: 6
Name: IDE (Interrupt on Done Enable)
Description: When set, this read/write bit causes the control to issue
a bus request and interrupt to vector address 2208 if:
a. A function has completed activity.
b. A hard error is encountered.
c. A soft error is encountered and bit 8 of the RKCS (SSE) is set.
d. RKCS 7 (ROY) is set and GO is not set.
81t: 7
Name: ROY (Control Ready)
Description: This read-only bit indicates that the control is ready to
perform a function. Set by INIT, a hard error condition, or by the
termination of a function. Cleared by GO being set.
81t: 8
Name: SSE (Stop on Soft Error)
Description: If a soft error is encountered when this read/write bit is
set:
a. all control action will stop at the end of the current sector if RKCS
6 (IDE) is reset, or
b. all control action will stop and a bus request will occur at the end
of the current sector if RKCS 6 (IDE) is set.
81t: 9
Name: Unused
81t: 10
Name: FMT (Format)
Description: This read/write bit is under program control, and must
be used only in conjunction with normal read and write functions.
Used to format a new disk pack or to reformat any sector erased
because of control or drive failure. Alters the normal write operation
under which the header Is rewritten each time the associated sector is
rewritten; the head position is not checked for proper positioning be-
558
RKV11-0
fore the write. Alters the normal read operation in that only one word,
the header word, is transferred to memory per sector. For example, a
3-word read function in format mode will transfer header words from
three consecutive sectors to three consecutive memory locations for
software checking.
Bit: 11
Name: IBA (Inhibit Incrementing the RKBA)
Description: This read/write bit inhibits the RKBA from incrementing
during a normal tranfer function. This allows data transfers to occur to
or from the same memory location throughout the entire transfer operation.
Bit: 12
Name: Unused
Bit: 13
Name: SCP (Search Complete)
Description: This read-only bit indicates that the previous interrupt
was the result of some previous seek or drive reset function. Cleared
at the initiation of any new function.
Bit: 14
Name: HE (Hard Error)
Description: This read-only bit sets when any of RKER 5-15 are set.
Stops all control action, and processor reaction is dictated by RKCS 6
(IDE), until cleared, along with RKER 5-15, by INIT or by a control reset
function.
<
Bit: 15
Name: ERR (Error)
Description: This read-only bit sets when any bit of the RKER sets.
Processor reaction is dictated by RDCS 6 and RKCS 8 (IDE and SSE).
Cleared if all bits in the RKER are cleared.
16
14
13
12
11
10
09
DB
07
06
05
04
03
02
01
00
:-:-:wcool
IWCI6:-': - - : - : - : - - - :-:
CP 3140
Figure 10
Word Count Register (RKWC)-Address 177406
559
RKV11-D
Table 6
Word Count Register Bit Descriptions
Bit: 0-15
Name: WCOO-WC15
Description: The bits in this register contain the 2's complement of
words to be affected or transferred by a given function. The register
increments by one after each word transfer. When the register overflows (all we bits go to zero), the transfer is complete and RKV11-D
operation is terminated at the end of the present disk sector. However,
only the number of words specified in the RKWC are transferred.
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
CP 3135
Figure 11
Bus Address Register(RKBA)-Address 177410
Table 7
Bus Address Register Bit Descriptions
Name: BAOO-BA 15
Bit: 0-15
Description: The read/write bits in this register contain the bus
address to or from which data will be transferred. The register is
incremented by two at the end of each transfer.
NOTE
This register will not respond to commands while the
controller is busy. Therefore, RKDA bits are loaded
from the bus data lines only in the control ready (bit 7
of the RKCS) state, and are cleared by BUS INIT and
control reset. The RKDA is incremented automatically at the end of each disk sector.
CP 3136
Figure 12
Disk Address Register (RKDA)-Address 177412
560
RKV11-D
Disk Ad~ress Register Bit Descriptions
Table 8
Name: SA (Sector Address)
.
Bit: 0-3
Description: Binary representation of the disk sector to be addressed for the next function. The largest valid address (or number)
for the sector address is 138 •
Bit: 4
Name: SUR (Surface)
Description: When active, enables the lower disk head so that opera- .
tion is performed on the lower surface; when inactive, enables the .
upper disk head.
Bit: 5-12
Name: CYL AD DR (Cylinder Address)
Description: Binary representation of the cylinder address currently
being selected. The largest valid address·or number for the cylinder
address is 312 8 •
Bit: 13-15
Name: DR SEL (Drive Select)
Description: Binary representation of the logical drive number currently being selected.
15
14
13
12
:
11
:
:
..
:
~:
05
"
:
.,
:
6
04
:
03
:
02
01
: :
CP 3134
Figure 13
Data Buffer Register (RKOB)-Address 177416
Table 9
Data Buffer Register Bit Descriptions
Bit: 0-15
Name: BOOO-8015
Description: The read-only bits 01 this register work as a general
data handler in that all information transferred between the control
and the disk drive must pass through this register. Loaded from the
bus only while the RKV11-D is bus master during a OMA sequence.
561
RKV11-D
PROGRAMMING
RKV11 Boot Program
The following boot program can be used to boot an AKV11/AK05
system from drive unit O.
@1000/000000
001002
000000
001004
000000
001006
000000
001010
000000
001012
000000
001014
000000
001016
000000
001020
000000
@1000G
12700
177406
12710
177400
12740
S
10S710
100376
S007
562
RLV11
RL V11 RL01 DISK DRIVE CONTROLLER
GENERAL
The RLV11 option is designed to interface RL01 disk drives with the
LSI-11 bus. The RLV11 controller can be used only In an H9273-A type
backplane (PDP-11/03L or BA11-NE), which incorporates the LSI-11
bus in slot AB and an interboard bus In slot CD. The 2-card controller
can interface up to four RL01 disk drives for a complete system. The
RL V11 option consists of two quad-size boards, an RL01 disk drive,
and all the necessary cables.
The RL01 disk drive is a random access, mass storage system that
stores data in fixed-length blocks on a preformatted disk cartridge.
Each drive can store 5.24 million bytes and a complete system can
store up to 21 million bytes. The RLV11 transfers data to and from the
LSI-11 bus using direct memory access (DMA) techniques. This allows
data transfers to occur without any processor Interruptions and at the
bus bandwidth speed.
FEATURES
• 5.24 million bytes per RL01 disk drive; 21 million bytes per system
• 10.4S million bytes per RL02 disk drive; 42 million bytes per system
• Up to four RL01 or RL02 disk drives or a combination can be used
with one RL V11 controller
• Universal power supply, 110/220 V, 50/60 Hz
• Bootstrap provided on BDV11
• Mounts in a PDP-11/03-L system, BA11-N expansion box, or
H9273-A backplane
• DMA transfers to and from the LSI-11 bus at 256K words per second
• 256 word silo buffer that eliminates late data er;ors on normal reads
and writes
SPECIFICATIONS
LSI·11 Bus Modules
Identification
Size
MS013
MS014
, Two quads
Power
+5 Vdc ::1:5% at 6.5 A
+12 Vdc ::1:3% at 1 A
Bus Loads
AC
DC
3.2
1
563
RLV11
RL01 Disk Drive
Data Organization
256 bytes per sector
40 sectors per track
256 tracks per surface
256 cylinders per cartridge
2 surfaces per cartridge
Formatted Capacity
10,240 bytes per track
20,480 bytes per cylinder
5.24M bytes per cartridge
21 M bytes per controller
Recording Density
125 tracks/in.
3725 bits/in (max.)
Recording Method
MFM
Performance
Peak Transfer Rate
3.9,."s per word
512.5K bytes per second
15 ms track-to-track
55 ms average
100 ms maximum
12.5 ms average
Head Positioning Time
Rotational Latency
Operating Environment
Tem peratu re Range
10 0 to 40 0 C (50 0 to 104 0 F)
at sea level
10 to 90%
Relative Humidity
No Condensation
Max. Wet Bulb
Altitude
28 0 C (82 0 F)
Up to 240 m (8000 ft.) at max.
temperature of 36 0 C (96 0 F)
150 W (600 Btu/hr.)
Heat Dissipation
Operation
Start Time
Stop Time
Rotational Speed
50 seconds
30 seconds
2400 rev/min.
Power
Drive
Start Current
Running Current
Single-phase
5 A/1.6 A max., 110V, 50/60 Hz
2.5 A/0.85 A max., 230V, 50/60
Hz
564
RLV11
48 cm wide X 63.4 cm deep X 27
cm high (19. in wide X 25 in. deep
X 10.5 in. high)
Mechanical Drive
Size
Weight
33.75 kg (75 lb.)
Mounting
RETMA standard 48.26 cm
(19 in.) rack-mounted on slides
(provided). Recommended maximum height from floor is 18.9 cm
(48 in.).
Stand-alone cabinets for expansion (standard option) available.
2 data surfaces
Embedded servo
Top loading
Cartridge
Cable Lengths
Standard
Power
Controller to Drive
Drive to Drive
3.05 m (10 ft.)
3.05 m (10ft.)
3.05 m (10 ft.)
Optional
Drive Cables
6.96, 12.19, 18.29, m
(20, 40, 60 ft.)
NOTE
Maximum physical length from controller to last
drive should be 30.48 m (100 ft.).
DESCRIPTION
General
The RLV11 controller was designed to interface the RL01 disk drives
to the LSI-11 bus. One RLV11 controller can support up to four RL01
disk drives. The controller consists of two quad-height modules that
plug directly into an LSI-11 backplane assembly. The backplane
should be structured as an H9273 (slots AS are LSI-11 bus and slots
CD are an interboard bus. Refer to section H9273.)
565
RLV11
The M8014 module contains all the LSI-11 bus-related circuits. Items
such as the bus control circuits, bus transceivers and decoders. programmable registers, and the FIFO circuits are located on this module.
The bus control function consists of the register protocol, interrupt
control, operation incomplete timer, direct memory access, and nonexistent memory timer. The bus transceiver circuits transmit and receive both data and address information on the bus. The programmable registers consist of the control/status register, bus address word
counter, disk address register, and the multipurpose register. The
FIFO circuits are a first-in/first-out memory that can store up to 256
16-bit data words.
The M8013 module contains all the controller timing and sequence
logic and the data formatting Circuits necessary to read and write on
the disk. The microsequencer logic decodes the function command
and proceeds to the address of the routine associated with the command. The write precompensation logic encodes the data Into modified frequency modulation and precompensates the data for peak
shifting effects. The cyclic redundancy checker is used to detect errors
and compute eRe on a write operation. The data source selector
allows the multiplexing of the data under control of the microsequencer. The header compare circuits compare the first header word received from the data separator with the serial disk address word
coming from the disk address register.
The major functional sections of the RLV11 controller are shown in
Figure 1. The processor controls the RL01 disk drives indirectly by
means of the RLV11 controller. The controller has four registers: the
bus address register (BAR), disk address register (DAR), control/status register (eSR), and a multipurpose register (MPR). Of these
four registers, the eSR is always written last because it initiates the
microsequencer operation. These registers can be addressed like any
other memory location.
566
MBOI3
FUNCTION CMOS
DATA LATE
MICRO SEQUENCER
AND
FUNCTION CONTROL
MISMATCH
r
.ja§~f
III
::>
01
m
§"'
SEND DRIVE COMMAND
-....I
~DRCMO
:a
r<
~
~
f----r--oI-{)c:WR DATA
WRT MKR
MAl NT
'--lI
FIFO
CONTROL
I
~RD DATA
L - - - - - - - - - - - - - - - - - - - - - - - - - - r lRDI
0
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
0
10 1
0
1
0
1
0
I·
0
I
0
Figure 12
1
1
0
1
0
1
0
I
0
1
1
0
0
I
0
1
MPR Three Header Words
MPR DURING READIWRITE COMMANDS FOR WORD COUNT
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
well
Figure 13
Table 8
MPR Used as Word Counter
MPR Word Counter Format
Bit: 0-12
Name: WC (12:0)
Description: (Word Count)
2's complement of total number of words to be transferred.
Bit: 13-15
Name:
Description: Must be all 1s for word count in correct range.
587
0
I
RLV11
Operator Controls and Indicators
The following switches and indicators are located on the RL01 front
bezel.
1. RUN/STOP switch with LOAD indicator light
2. UNIT SELECT switch with READY indicator light
3. FAULT indicator light
4. WRITE PROTECT switch with WRITE PROTECT indicator light
Power ON/OFF control is via a rear panel circuit breaker switch which
is normally left in the ON position. Operation of this circuit breaker
switch will not damage the drive in any way.
RUN/STOP Switch with LOAD Indicator - The RUN/STOP switch is
a push/push alternating action switch which, when depressed,
energizes the spindle motor. When released, it de-energizes the spindle motor provided the heads are not loaded and the brushes are
retracted. If the heads are loaded, it causes the heads to unload and
then de-energizes the spindle motor.
The switch contains mechanical memory. In the event of main power
disruption and subsequent restoration, the drive will cycle up if the
switch is in the depressed state.
The LOAD indicator is lit whenever the spindle is stopped, heads
home, brushes home, and the spindle motor is not energized. A cartridge can be loaded when this indicator is lit.
UNIT SELECT Switch with READY Indicator - The UNIT SELECT
switch is a cam-operated switch which is actuated by inserting a numbered cam button. The numbered cam button is such that the drive
logic will recognize the drive address code corresponding to the unit
select number on the cam button. The numbered indicator lights to
indicate the condition identified, such as heads loaded and locked on
a cylinder, or drive ready for read or write operations.
FAULT Indicator - The FAULT indicator is lit whenever a fault or
error condition occurs in the drive.
WRITE PROTECT Switch with WRITE PROTECT Indicator - The
WRITE PROTECT switch is a push/push alternating action switch.
When depressed, it sets the drive in write protect mode. If the drive is
in the process of writing at the time that the switch is depressed,
writing will continue until the write gate is negated at the next sector
pulse. The WRITE PROTECT indicator will not be illuminated until the
write protect function is enabled. Removal of write protect will occur
immediately upon the deactivati~n of the WRITE PROTECT switch.
588
RLV11
I/O Transfer Operations
There are three kinds of 1/0 transfers that are used to interface the
processor with the RLV11 controller. They are programmed 1/0 transfers, DMA transfers, or interrupt-driven transfers.
Programmed 1/0 transfers are executed by single- or double-operand
PDP-11 instructions. By including the device's address as the effective
source or destination address, the user specifies the transfer as an
input or output operation. Programmed 1/0 allows information to be
transferred between the RLV11 addressable registers and LSI-11
memory locations and processor registers. The transfer of each word
requires the execu~ion of a PDP-11 instruction.
DMA transfers, on the other hand, require only a few programmed 1/0
transfers to set control information. Then a large block of data can be
moved to or from memory without any support from the processor.
DMA transfers are the fastest method of transferring data between
memory and a device. They can occur between processor bus cycles
and do not alter processor status in any way. Blocks of data can be
moved at speeds that are not limited by processor instruction execu-·
tion via the DMA transfer mode. The read and write data in the controller FIFO is received and transmitted under DMA control.
Interrupt-driven transfers allow the processor to continue a programmed operation without waiting for the controller to become
ready. When the controller becomes ready, it interrupts the processor's background program sequence and causes execution of the
controller's service routine. After the controller's service routine has
been executed, the background program is restored and program
execution resumes at the point where it was interrupted.
Programmed I/O Transfers - Every processor instruction requires
one or more 1/0 operations. The first operation required is a data input
transfer (DATI), which fetches an instruction from memory at the location addressed by the program counter. This operation is called a
DATI bus cycle. If the controller is referenced, additional DATI, or data
output transfer (DATO) bus cycles are required.
Writing Controller Registers When writing the controller registers,
the CPU is the bus master and the controller is the slave. The initial
DATI fetch cycle is followed by a DA TO cycle.
Reading Controller Registers When reading the controller. registers,
the CPU is bus master and the controller is the slave. The processor
performs a DATI cycle to obtain the data from the RLV11 registers.
589
RLV11
The DATI cycle is a result of a processor-programmed instruction
which addresses the controller registers.
DMA 1/0 Transfers - Direct memory access (DMA) is used to transfer
data between the controller FIFO and memory without program control. The processor can service DMA requests between bus cycles.
Upon receiving BDMR requests from the bus, the processor sets up
the conditions for DMA transfer by granting bus mastership to the
BDMG priority daisy-chain. If a high-priority device Is requesting bus
mastership, it will receive it and inhibit passage of the processor's
grant, regardless of other low priority requests. If It is not requesting
bus mastership, it will pass the processor's BDMGO through other
nonrequesting "devices to the one that is requesting the mastership. In
practice, the disk controller is the highest priority device, after memory, in the system.
Once the controller is bus master and memory Is the slave, DMA
transfers can occur without processor intervention. The DMA protocol
circuit limits transfers to four words at a time to allow other devices to
be serviced and to prevent interference with the memory refresh cycle.
After a time-out of 4 ILS, if the processor is bus master, the controller
can reassert mastership and continue the transfer with another four
words.
Interrupt-Driven 1/0 Transfers - Interrupts are requests made by the
controller that cause the processor to temporarily suspend Its present
program sequence to execute the controller service routine. The
controller can interrupt the processor only when its interrupt control
circuit is enabled. This circuit is enabled by an Interrupt enable (IE) bit
in the control/status register. A program must set this bit before an
interrupt request can be issued.
An interrupt vector associated with the RVL 11 controller Is located In
the controller interface/control logic. This vector is an address pointer
that allows automatic entry into the controller service routine without
device polling. The vector is switch-selectable In the range 0-774.
The controller requests interrupt service by asserting BIRQ L. The
processor ack!,)owledges the interrupt request by asserting BDIN L
followed by BIAKO L. The first device on the bus receives this dalsychained signal at its BIAKI L input. If it Is not requesting service, it
passes the signal via Its BIAKO L output to the next device, and so on,
until the requesting device receives the signal. The requesting d"evice
responds by asserting BRPLYL and placing Its interrupt vector on the
data/address bus lines BDAL (0:15) L. Automatic entry to the service
routine is then executed by the processor.
590
RLV11
Bus Signal Timing
Diagrams illustrating the bus timing requirements between the processor and the RLV11 controller, given in general master/slave device
terms, may be found in the Microcomputer Processor Handbook published by Digital Equipment Corporation.
591
RXV11
RXV11 FLOPPY DISK OPTION
SPECIFICATIONS
Module
Identification
M7946
Size
Double
Power
+5 V ±5% at 1.5 A
Bus Loads
AC
DC
1.8
1
Drive
Id entificati on
RX01
Size
46.3 cm w X 28.7 cm h X 53.3 cm
d
(19 in w X 10.5 in h X 21 in d)
Recommmended Service Clearance (front and rear)
55 cm (22 in)
AC Power
4 A at 115 Vac; 2 A at 230 Vac
(dual drive)
Cable Included
BC05L-15 (15 ft)
Drive Performance
Capacity (8-bit bytes)
Per diskette
Per track
Per sector
256,256 bytes
3,328 bytes
128 bytes
Data Transfer Rate
Diskette to controller
buffer
4 ~sec/data bit (250K bits/sec)
Buffer to RXV11 interface
2 ~sec/bit (500K bits/sec)
RXV11 interface to LSI-11
110 bus
18 ~sec/8-bit byte ( <50K
bytes/sec)
Track-to-track move
6 msec/track maximum
Head settle time
25 msec maximum
Rotational speed
360 rpm±2.5%; 166 msec/rev
nominal
592
RXV11
Recording surfaces per disk
Tracks per disk
77 (0-76) or (0-1148)
Sectors per track
26 (1-26) or (0-328)
Sectors per disk
2002
Recording technique
Double frequency
Bit density
3200 bits/in at inner track
Track density
48 tracks/in
Average access
Seek
262 msec, computed as follows:
Settle
Rotate
Total
(77 tks/3) X 6 msec + 25 msec + (166 msec/2) = 262 msec
Environmental Characteristics
Temperature
RX01, operating
15 0 to 32 0 C (59 0 to 90 0 F) ambient; maximum temperature
gradient = -6.7 0 C/hr (20 0 F/hr)
RX01, nonoperating
-35 0 to +60 0 C (-30 0 to +140 0
F)
Media, nonoperating
-35 0 to +52 0 C (-30 0 to + 125 0
F)
NOTE
Media temperature must be within operating temperature range before use.
Relative Humidity
RX01, operating
25 0 C (77 0 F) maximum wet bulb
2 0 C (36 0 F) minimum dew point
20% to 80% relative humidity
RX01, nonoperating
5% to 98% relative humidity (no
condensation)
Media, nonoperating
10% to 80% relative humidity
Magnetic field
Media exposed to a magnetic
field strength of 50 oersteds or
greater may lose data.
593
RXV11
System Reliability
Minimum number of
revolutions/track
3 million/media (head-loaded)
Seek error rate
1 in 106 seeks
Soft read error rate
1 in 109 bits read
Hard read error rate
1 in 1012 bits read
NOTE
The above error rates apply only to medi~ that are
properly cared for. Seek error and soft read errors
are usually attributable to random effects in the
head/media interface, such as electrical nOise, dirt,
or dust. Both are called "soft" errors if the error is
recoverable in ten additional tries or less. "Hard"
errors cannot be recovered. Seek error retries
should be preceded by an initialize.
CONFIGURATION
General
The factory jumper locations on the M7946 interface module are
shown in Figure 1. Note that two styles of modules are used; one style
(etch Rev B) has machine-inserted jumpers; the other (etch Rev e) has
wire-wrap jumpers. All M7946 interface modules are configured and
shipped with preselected register addresses and vectors as shown in
Figure 2. The control/status register (RXeS) address is 177170, and
the data buffer register (RXDB) address is 177172. The interrupt vector is 2648 • As supplied, the factory-configured jumpers are fOr" the
normal addresses used with DIGITAL software. However, in applications where more than one RXV11 system is required, appropriate
register addresses and vectors may be configured by installing or
removing jumpers. A second RXV11 system would normally be assigned register addresses 177174 (RXeS) and 177176 (RXDB), with an
interrupt vector of 270 8 (Table 2).
Register Descriptions
Control/Status Register (RXCS)(177170) - The format for the RXeS
register is shown in Figure 3. Bit descriptions are presented. in Table 3.
Loading the RXeS register while the RX01 is not busy and with bit 0 =
1 will initiate a function described in Table 3.
594
o
C
o
J1
o
J
o
o
o
o
C
J1
1
o
...0-.
:II
U1
-'"
'"
co
U1
\11111 _ _ _ _ _ _ _ _ W'3
_"4
_Wli
W2 .................. YB
1"14......--. .......... WS
-""
-""
_wo
W1 ____ """"--"'3
W8~"""""W14
\lV.S ________ wg
"'0 ________ W17
tll' ________ n15
......---Wl0
.......... W',
""'-'W12
"'3 .................... "'6
W14 .......... """"-"'1
ETCfi REV B . MACHINE INSERTED JUMPERS
Figure 1
ETCH REV C . WIRE·WRAP JUMPERS
RXV11 Device Register and Interrupt Vector Jumper
Locations
><
<
""'""'""
RXV11
RXCS·177170
RXDB"77172
nA~
I I
07
BITS-.15
vECTOR
ADDRESS
a
0
:
0
: I
0
0
:
0
: I :
0
00
0
M79~~M:~;U~~
:
I I
---INS
FACTORY-CONFIGURED
VECTOR AOORESS'264 -
!
I
\\I'
I I
\\15
I
R
I I
I I
\\13
\\12
R
I
0
0
I
I
T
R
NOTE
I: Jumper Installed· LOQlcol 0
R: Jumper rtmo'ted' LOQ.cal 1
)C.
Don', co,e
Figure 2
Device Register Address and Interrupt Vector
Table 1
RXV11 Configurations
System
Disk Drive
Line Voltage*
RXV11-AA
RXV11-AC
RXV11-AD
RXV11-BA
RXV11-BC
RXV11-BD
Single drive system
Single drive system
Single drive system
Dual drive system
Dual drive system
Dual drive system
11SV/60Hz
11SV/SO Hz
230V/SO Hz
11SVi60 Hz
11SV/SO Hz
230V/SO Hz
• 50 Hz versions are available in voltages of 105, 115,220, and 240 Vac by
field-pluggable conversion.
596
RXV11
Table 2
Description
Standard Assignments
Mnemonic
Readl
Write
First
Module
Address
Second
Module
Address
RXCS
RXDB
R/W
R/W
177170
177172
177174
177176
264
270
Registers
Control/Status
Data Buffer
Interrupt
Function
Complete
15
14
Done
13
12
11
10
09
08
07
06
05
04
I I I
)R
I
INT
ENB
Figure 3
Table 3
JNE
03
02
01
00
I ~L
*
UNIT
SEL
000 FI LL BUFFER
001 EMPTY BUFFER
010 WRITE SECTOR
READ SECTOR
OIl
100 NOT USED
READ STATUS
101
110 WRITE DELETED
DATA SECTOR
READ ERROR
111
REGISTER
RXCS Format
RXCS Bit Descriptions
Bit
Description
o
Go. Initiates a command to RX01. This is a write-only
bit.
1-3
Function Select. These bits code one of the eight
possible functions described in detail in this section.
These are write-only bits.
4
Unit Select. This bit selects one of the two possible
disks for execution of a desired function. This is a
write-only bit.
597
RXV11
5
Done. This bit indicates the completion of a function.
Dohe will generate an interrupt when asserted if interrupt enable (RXeS bit 6) is set. This is a read-only
bit.
6
Interrupt Enable. This bit is set by the program to
enable an interrupt when the RX01 has completed an
operation (done). The condition of this bit is normally
determined at the time a function is initiated. This bit
is cleared by LSI-11 bus initialize (BINIT L) signal,
but it is not cleared by the RXV11 initialize bit (RXeS
bit 14). This is a read/write bit.
7
Transfer Request. This bit signifies that the RXV11
needs data or has data available. This is a read-only
bit.
8-13
Unused.
14
RXV11 Initialize. This bit is set by the program to
initialize the RXV11 without initializing all of the devices on the LSI-11 bus. This is a write-only bit.
1.
2.
Caution
Loading the lower byte of the RXeS will also
load the upper byte of the RXeS.
Setting this bit (BIS instruction) will not clear the
interrupt enable bit (RXeS bit 6).
Upon setting this bit in the RXeS, the RXV11 will
negate done and move the head position mechanism of drive 1 (if two are available) to track O. Upon
completion a successful initialize, the RX01 will
zero the error and status register, set initialize done,
and set RXES bit 7 (DRV ROY) if unit 0 is ready. It will
also read sector 1 of track 1 on drive O.
0'-
15
Error. This bit is set by the RX01 to indicate that an
error has occurred during an attempt to execute a
command. This read-only bit is cleared by the
initiation of a new command or by setting the initialize bit. When an error is detected, the RXES is auto"matically read into the RXDB.
598
RXV11
Data Buffer Register (RXOB)(177172)
This RX01 interface register serves as a general purpose data path
between the RX01 and the interface. It may represent one of five RX01
registers according to the protocol of the command function in progress. The RX01 registers include RXDB, RXT A, RXSA, RXES, and
RXER; each is described below.
This register is read/write if the RX01 is not in the process of executing
a command. That is, it may be manipulated without affecting the RX01
subsystem. If the RX01 is actively executing a command, this register
will accept data only if RXeS bit 7 (TR) is set. In addition, valid data can
be read only when TR is set.
Caution
Violation of protocol in manipulation of this register may cause permanent data loss.
RX Data Buffer (RXOB) (Figure 4) - All information transferred to
and from the floppy media passes through this register. It is addressable only under the protocol of the function in progress.
15
14
13
12
II
10
09
08
07
06
05
v
04
03
02
01
00
v
READ/WRITE DATA
NOT USED
CP-2247
Figure 4
RXDB Format
RX Track Address (RXTA) (Figure 5) - This register is loaded to
indicate on which of the 1148 tracks a given function is to operate. It
can be addressed only under the protocol of the function in progress.
Bits 8 through 15 are unused and are ignored by the control.
15
14
13
1
12
II
10
09
08
07
06
D5
04
03
02
01
00
0
-I
1
NOT USED
0- 1148
CP-l:'lO
FigureS
RXTA Format
599
RXV11
RX Sector Address (RXSA) (Figure 6) - This register is loaded to
Indicate on which of the 328 sectors a given function is to operate. It
can be addressed only under the protocol of the function in progress.
Bits 8 through 15 are unused and are ignored by the control.
15
14
13
12
11
10
09
07
08
05
06
! I I
0
0
04
02
03
01
00
0
1-32 8
NOT USED
Figure 6
RXSAFormat
RX Error and Status (RXES) (Figure 7) - This register contains the
current error and status conditions of the drive selected by bit 4 (unit
select) of the RXCS. This read-only register can be addressed only
under the protocol of the function in progress. The RXES is located in
the RXDB upon completion of a function. Table 4 lists the RXES bit
descriptions.
15
14
13
12
11
10
09
08
07
06
I~~~ I I
05
04
DO
I
NOT USED
RXES Format
600
02
0I
00
10
PAR
CRC
I I I I
'-----....-----
NOT USED
Figure 7
03
RXV11
Table 4
RXES Bit Descriptions
Bit
Description
o
CRC Error. A cyclic redundancy check error was detected as information was retrieved from a data field
of the diskette. The RXES is moved to the RXDB, and
error and done are asserted.
Parity Error. A parity error was detected on command or on address information being transferred to
the RX01 from the LSI-11 bus interface. A parity
error indication could mean that there is a problem
in the interface cable between the RX01 and the interface. Upon detection of a parity error, the current
function is terminated; the RXES is moved to the
RXDS, and error and done are asserted.
2
Initialize Done. This bit is asserted in the RXES to
indicate completion of the Initialize routine, which
can be caused by RX01 power failure, system power
failure, or programmable or LSI-11 bus Initialization.
3-5
Unused.
6
Deleted Data Detected. During data recovery, the
identification mark preceding the data field was decoded as a deleted data mark.
7
Drive Ready. This bit Is asserted if the unit currently
selected exists, is properly supplied with power, has
a diskette Installed correctly, has its door closed,
and has a diskette up to speed.
NOTE
The drive ready bit is only valid when retrieved via a
read status function or at completion of initialize
when it indicates status of drive O.
If the error bit was set in the RXCS but error bits are
not set in the RXES, then specific error conditions
contained in the RXER can be accessed from the
RXDB via a read error register function.
601
RXV11
RX Error (RXER) (Figure 8) - This register Is located in the RX01 and
contains specific RX01 error information. This Information is normally
accessed when RXCS error bit 15 Is set but AXES error bits 0 and 1 are
not set. This is a read-only register.
15
14
13
12
II
10
09
08
07
06
05
04
03
02
01
00
NOT USED
CP-2246
/
Octal Code
Error Code Meaning
010
Drive 0 failed to see" home on initialize.
020
Drive 1 failed to see home on Initialize.
030
Found home when stepping out 10 tracks for INIT.
040
Tried to access a track greater than 77.
050
Home was found before desired track was reached.
060
Self-diagnostic error.
070
Desired sector could not be found after looking at 52
headers (2 revolutions).
110
More than 40 #Lsec and no SEP clock seen.
120
A preamble could not be found.
130
Preamble found but no I/O mark found within allowable time span.
140
CRC error on what was thought to be a header.
150
The header track address of a good header does not
compare with the desired track.
160
Too many tries for an lOAM (Identifies header).
170
Data AM not found In allotted time.
200
CRC error on reading the sector from the disk. No
code appears in the ERREG.
210
All parity errors.
Figure 8
RXER Format
602
RXV11
Function Codes
Data storage and recovery on the RXV11 system is accomplished by
careful manipulation of the RXeS and RXDB registers according to the
strict protocol of individual functions. The penalty for violation of protocol can be permanent data loss. Each of the functions is encoded
and written into RXeS- bits 1-3, as shown in Figure 3. Programming
protocol for each function is described below.
Fill Buffer (000) - This function is- used to fill the RX01 buffer with 128
8-bit bytes of data from the host processor. Fill buffer is a complete
function in itself. The function ends when the buffer has been filled.
The contents of the buffer can be written onto the diskette by means of
a subsequent write sector function, or the contents can be returned to
the host processor by an empty buffer function.
RXeS bit 4 (unit select) does not affect this function, since no diskette
drive is involved. When the command has been loaded, RXeS bit 5
(done) is negated. When the TR bit is asserted, the first byte of data
may be loaded into the data buffer. The same TR cycle will occur as
each byte of data is loaded. The RX01 counts the bytes transferred. It
will not accept less than 128 bytes and will ignore those in excess. Any
read of the RXDB during the cycle of 128 transfers results in invalid
read data.
Empty Buffer (001) - This function is used to empty the internal
buffer of the 128 data bytes loaded from a previous read sector or fill
buffer command. This function will ignore RXeS bit 4 (unit select) and
negate done.
When TR sets, the program may unload the first of 128 data bytes from
the RXDB. Then the RXV11 again negates TR. When TR resets, the
second byte of data may be unloaded from the RXDB, which again
negates TR. Alternate checks on TR and data transfers from the RXDB
continue until 128 bytes of data have been moved from the RXDB.
Done sets, ending the operation and initiating an interrupt If RXeS bit
6 (interrupt enable) is set. RXES contents are moved to the RXDB
where they can be read.
NOTE
The empty buffer function does not destroy the con- tents of the sector buffer.
If the deleted data address mark was detected, the control will assert
RXES bit 6 (DO). As data enters the sector buffer, a eRe is computed,
based on the data field and eRe bytes previously recorded. A non603
RXV11
zero residue indicates that a CRC error has occurred. The control sets
AXES bit 0 (CRC error) and RXCS bit 15 (error). The RXV11 ends the
operation by moving the contents of the RXES to the RXDB, sets done,
and initiates an interrupt if RXCS bit 6 (interrupt enable) is set.
Read Status (101) - The RXV11 will negate RXeS bit 5 (done) and
begin to assemble the current contents of the RXES into the RXDB.
RXES bit 7 (drive ready) will reflect the status of the drive selected by
RXCS bit 4 (unit select) at the time the function was given. All other
RXES bits will reflect the conditions created by the last command.
RXES may be sampled when RXCS bit 5 (done) /s again asserted. An
Interrupt will occur if RXCS bit 6 (interrupt enable) Is set.
NOTE
The average time for this function is 250 ms. excessive use of this function will result in substantially
reduced throughput.
Write Sector with Deleted Data (110) - This operation is Identical to
function 010 (write sector), with the exception that a deleted data
address mark precedes the data field instead of a standard data address mark.
Read Error Register Function (111) - The read error register function can be used to retrieve explicit error information contained in the
RXER when RXeS error bit 15 is set. The function Is initiated, and bits
0-6 of the RXES are cleared. Out is asserted and done is negated. The
controller then generates the appropriate number of shift pulses to
transfer the specific error code from the RXER to the interface register
and completes the function by asserting done. The RXDB program
can then read the error code to determine the type of failure that
occurred (Figure 8).
NOTE
Care should be exercised in the use of this function
since, under certain conditions, erroneous error information may result.
Power Fall - There is no actual function code aSSOCiated with power
fail. When the RX01 senses a loss of power, It will unload the head and
abort all controller action. All status signals are Invalid while power /s
low.
604
RXV11
When the RX01 senses. the return of power, it will remove done and
begin a sequence to:
1. Move drive 0 head position mechanism to track O.
2. Clear any active error bits.
3. Read sector 1 of track 1 of drive 0 into the sector buffer.
4. Set RXES bit 2 (initialize done) after which done is again asserted.
5. Set drive ready of the RXES according to the status of drive o.
Write Sector (010) - This function Is used to locate a desired track
and sector and write the sector with the contents of the Internal sector
buffer. The initiation of this function clears bits 0, 1 and 6 of RXES
(CRC error, parity error, and deleted data detected) and negates
done.
When TR is asserted, the program must first move the desired sector
address into the RXDB, which will negate TR. When TR Is again asserted, the program must move the desired track address into the RXDB,
which will negate TA. If the desired track Is not found, the AXV11 will
abort the operation, move the contents of the RXES to the RXDB, set
RXCS bit 15 (error), assert done, and initiate an interrupt IfAXCS bit 6
(interrupt enable) is set.
TR will remain negated while the RX01 attempts to locate the desired
sector. If the RX01 is unable to locate the desired sector within two
diskette revolutions, the RXV11 will abort the operation, move the
contents of the RXES to the RXDB, set AXCS bit 15 (error), assert
done, and Initiate an interrupt If RXCS bit 6 (Interrupt enable) is set.
If the desired sector is successfully located, the RXV11 will write the
128 bytes stored in the internal buffer followed by a 16-bit CRC character that is automatically calculated by the RX01. The AXV11 ends the
operation by asserting done and initiating an Interrupt if RXCS bit 6
(interrupt enable) is set.
NOTE
The contents of the sector buffer are not valid data
after a power loss has been detected by the RX01.
The write sector function, however, will be accepted
as a valid function, and the random contents of the
buffer will be written, followed by a valid CRC.
The write sector function does not destroy the contents of the sector buffer.
605
RXV11
Read Sector (011) - This function Is used to locate a desired track
and sector and transfer the contents of the data field to the mlcroCPU
controller sector buffer. The Initiation of this function clears bits 0, 1,
and 6 of RXES (CRC error, parity error, and deleted data detected)
and negates done.
When TR is asserted, the program must first move the desired sector
address into the RXDB, which will negate TR. When TR is again asserted, the program must move the desired track address Into the RXDB,
which will negate TR.
If the desired track Is not found, the AXV11 will abort the operation,
move the contents of the RXES to the RXDB, set RXCS bit 15 (error),
assert done, and initiate an interrupt IfAXCS bit 6 (Interrupt enable) Is
set.
TR and done will remain negated while the ~01 attempts to locate the
desired track and sector. If the RX01 is unable to locate the desired
sector within two diskette revolutions after locating the presumably
correct track, the RXV11 will abort the operation, move the contents of
the AXES to the RXDB, set RXeS bit 15 (error), assert done, and
initiate an Interrupt if RXCS bit 6 (Interrupt enable) Is set.
If the desired sector is successfully located, the control will attempt to
locate a standard data address mark or a deleted data address mark.
If either mark is properly located, the control will read data from the
sector into the sector buffer.
There is no guarantee that information being written at the time of a
power failure will be retrievable. However, all other Information on the
diskette will remain unaltered.
One method of aborting a function is through the use of RXCS bit 14
(RXV11 initialize); however, this will not clear the interrupt enable bit
(RXeS bit 6). Another method is through the use of the system
initialize signal that is generated by the PDP-11 RESET instruction, the
console ODT Go command, or system power failure.
PROGRAMMING
Bootstrapping the RXV11
The RXV11 bootstrap loader program loads the system monitor from
disk into system memory. No system operation can occur until the
monitor is contained In system memory. Bootstrapping ("booting") the
system can be accomplished via a hardware-Implemented bootstrap
in the REV11-A, REV11-C, or the BDV11 option, or It can be entered
and executed via the console device.
606
RXV11
When a bootstrap option is not included in the system, the operator
must enter a bootstrap program via the console device. Place the
processor in the Halt mode and proceed as shown below;
The bootable volume must be In drive zero. All devices are at standard addresses and vectors. Enter the code starting at location 1000. Inhibit
all interrupts by entering RS/_340 . Initialize the program
counter by entering R7/_1000 . After the code has been entered, type P.
RX01
RX01
LOCATION
CODE
LOCATION
CODE
1000
12702
1040
111023
1002
100247
1042
30211
1004
12701
1044
1776
1006
177170
1046
100756
1010
130211
1050
103766
1012
1776
105711
1014
112703
1052
1054
1016
7
1056 _
5000
1020
10100
1060
22710
100771
1022·
10220
1062
240
1024
402
1064
1347
1026
12710
1066
122702
1070
247
1030
1032
6203
1072
5500
1034
103402
1074
5007
1036
·112711
607
RXV21
RXV21 FLOPPY DISK OPTION
GENERAL
The RXV21 floppy disk option is a random access mass memory device that stores data in fixed-length blocks on a preformatted, flexible
diskette. Each diskette can store and retrieve up to 512K 8-bit bytes of
data. The RXV21 system is rack-mountable and consists of an interface module, an interface cable, and either a single or dual RX02
floppy disk drive.
FEATURES
• Compact disk system
• Stores/retrieves 512K 8-bit bytes of data
•
•
•
•
Rack mountable
Available with either single or dual disk drive
Available for 115 or 230 Vac, 50 or 60 Hz
Can be converted (50 Hz version) for 105, 115, 220 or 240 Vac
operation
• Direct Memory Access data tranfer
• Industry-compatible mode under software selection
SPECIFICATIONS
Module
Identification
M8029
Size
Double
Power
+5V ±5% at 1.8A typically
Bus Loads
AC
DC
3
1
Drive
Identification
RX02
Size
46.3 cm w X 28.7 cm h X 53.3 cm
d
(19 in. w X 10.5 in. h X 21 in. d)
Recommended Service
55 em (22 in.)
Clearance (front and rear)
608
RXV21
AC Power
4A at 115 Vac; 2A at 230 Vac
(dual drive)
Cable Included
BC05L-15 (15 ft.)
Drive Performance
Capacity (8-bit bytes)
Per diskette
512,512 bytes
Per track
6,656 bytes
Per sector
256 bytes
Data Transfer Rate
Diskette to controller buffer
2 #,sec/data bit (500K bits/sec)
Buffer to RXV21 interface
1.2 #,sec/bit (500K bits/sec)
RXV21 interface to LSI-11
I/O bus
23 #,sec/16-bit word
Track-to-track move
6 msec/track maximum
Head settle time
25 msec maximum
Rotational speed
360 rpm ±2.5%; 166 111 sec/rev
nominal
Recording surfaces per disk
1
Tracks per disk
77 (0-76) or (0-1148)
Sectors per track
26 (1-26) or (0-32 8)
Sectors per disk
2002
Recording technique
Double frequency (FM) or modified (MFM)
Bit density
3200 bpi (FM); 6400 bpi (modified
MFM)
Track density
48 tracks/In.
262 msec, computed as follows:
Average access
Seek
(77 tks/3)
Rotate
Settle
Total
x 6 msec + 25 msec + (166 msec/2) = 262 msec
609
RXV21
Environmental Characteristics
Tem peratu re
RX02, operating
15 0 to 32 0 C (59 0 to 90 0 F) ambient; maximum temperature
gradient = 11 °C/hr (20°F/hr)
RX02, nonoperating
-35 0 to +60 0 C (-30 0 to +140 0
F)
-35 0 to +52 0 C (-30 0 to +125 0
Media, nonoperating
F)
NOTE
Media temperature must be within operating temperature range before use.
Relative Humidity
RX02, operating
25 0 C (77 0 F) maximum wet bulb
2 0 C (36 0 F) minimum dew point
20% to 80% relative humidity
RX02, nonoperating
5% to 98% relative humidity (no
condensation)
Media, nonoperating
10% to 80% relative humidity
Magnetic field
Media exposed to a magnetic
field strength of 50 oersteds or
greater may lose data.
System Reliability
Minimum number of revolutions/track
3 million/media (head-loaded)
Seek error rate
1 in 106 seeks
Soft read error rate
1 in 109 bits read
Hard read error rate
1 in 1012 bits read
NOTE
The above error rates apply only to DIGIT AL-approved media that is properly cared for. Seek error
and soft read errors are usually attributable to random effects in the head/media Interface. ~uch as
electrical noise, dirt, or dust. Both are called "soft"
610
RXV21
errors in that the error is recoverable in ten addItional tries or less. "Hard" errors cannot be recovered.
Seek error retries should be preceded by an
initialize.
DESCRIPTION
The interface module converts the RX02 I/O bus to the LSI-11 bus
structure. It controls the RX02 interrupts to the processor, decodes
device addresses for register selection, and handles the data interchange between the RX02 and the processor via DMA transfers.
Power for the interface module is supplied by the LSI-11 bus.
The RXV21 floppy disk system is av'ailable in the configurations described in Table 1.
Table 1
System
RXV21-AA
RXV21-AC
RXV21-AD
RXV21-BA
RXV21-BC
RXV21-BD
RXV21 Configurations
Disk Drive
Single drive system
Single drive system
Single drive system
Dual drive system
Dual drive system
Dual drive system
Line Voltage*
t1SV/60 Ht
11SV/SO Hz
230V/SO Hz
11SV/60 Hz
11SV/SO Hz
230V/SO Hz
* 50 Hz versions are available in voltages of 105, 115, 220, and 240 Vac by
field-pluggable conversion.
CONFIGURATION
General
The factory jumper locations on the M8029 Interface module are
shown in Figure 1. All M8029 interface modules are configured and
shipped with preselected register addresses and vectors as shown in
Figure 2. The control/status register (RX2CS) address is 177170, and
the data buffer register (RX2DB) address is 177172. The interrupt
vector is 264 8 • As supplied, the factory-configured jumpers are for the
normal addresses used with DIGITAL software. However, in applications where more than one RXV21 system Is required, appropriate
register addresses and vectors may be configured by installing or
removing jumpers. A second RXV21 system would normally be assigned register addresses 177200 (RX2CS) and 177202 (RX2DB), with
an Interrupt vector of 270 8 (Table 2).
611
RXV21
Register Descriptions
Control/Status Register (RXCS)(177170) - The format for the RX2CS
register is shown in Figure 3. Bit descriptions are presented in Table 3.
Loading the RX2CS register while the RX01 is not busy and with bit 0 =
1 will initiate a function described In Table 3.
vv
A
NOTES:
1. MODULE M7744 AND CABLE ASSEMBLY
BCOSL ARE SUPPLIED WITH RX02
FLOPPY DISK SUBSYSTEM ASSEMBLY
2.RED STRIPE OF BCOSL INDICATES
PIN "A" ON THE CONNECTOR
Figure 1
RXV21 Device Register and Interrupt Vector Jumper
Locations
612
RXV21
To select the standard address, the following Jumpers are Installed:
A12
A 11
A 10
A9
A8
A7
A6
A5
A4
A3
Installed
Installed
Installed
Installed
Removed
Removed
Installed
Installed
Installed
Installed
The standard Interrupt Vector Is selected by Installing the following Jumpers:
V2
V3
V4
V5
V6
V7
V8
Installed
Removed
Installed
Installed
Removed
Installed
Installed
Figure 2
Device Register Address and Interrupt Vector
Table 2
First
Module
Address
Second
Module
Address
177170
177150
RX2DB
177172
177152
Done
264
270 .
Description Mnemonic
Registers
Controll
Status
Data Buffer
Interrupt
Function
Complete
Standard Assignments
RX2CS
Read/
Write
See register
description
613
RXV21
Figure 3
RXV21 Command and Status Register (RX2CS)
Table 3
RX2CS Bit Descriptions
Name: GO
Bit: 0
Function: Initiates a command to the RX02. Write-only.
Bit: 1-3
Name: Function Select
Function: These bits code one of the eight possible functions described in the Programming Specification. Write-only.
Bit: 4
Name: Unit Select
Function: This bit selects one of the two possible disks for execution
of the desired function. This bit Is readable only when DONE is set. At
that time, it indicates the unit previously selected. At any other time it is
not valid.
Bit: 5
Name: DONE
Function: Indicates the completion of a function. DONE will generate
an interrupt upon being asserted if Interrupt Enable (RX2CS Bit 6) is
set. Read-only.
Bit: 6
Name: Interrupt Enable
Function: This bit is set by the program to enable an interrupt when
the RX02 has completed an operation (DONE). The condition of this bit
is normally determined at the time a function is initiated. Cleared by
initialize. Read/write.
Bit: 7
Name: Transfer Request
Function: This bit signifies that the RXV21 needs the next word in the
register protocol sequence (see Programming Specification). Readonly.
Bit: 8
Name: Density
Function: This bit determines the density of the function to be executed. This bit is readable only when DONE is set. At that time, it
indicates the density of the function previously executed. This bit is not
valid at any other time.
614
RXV21
Table 3
RX2CS Bit Descriptions (Conti
Bit: 9
Name: Head Select
Function: This bit selects one of two heads for double sided operation. This bit is readable only when DONE is set. At that time, it indicates the side that was previously selected. At any other time, it is not
valid.
Bit: 10
Name:
Function: Reserved
Note: Must be written O.
Bit: 11
Name: RX02
Function: This bit is set by the Interface to inform the programmer
that this is an RX02 system. Read-only._
Bit: 12-13 Name: Extended Address
Function: These bits are used to declare an extended bus address.
Write-only.
Name: RXV21 Initialize
Bit: 14
Function: This bit is set by the program to Initialize the RXV21
without Initializing all of the devices on the UNIBUS.
CAUTION: Loading the lower byte of the RX2CS will also load the
upper byte of the RX2CS. Upon setting this bit In the RX2CS, the
RXV21 will drop DONE and move the head position mechanism of
both drives (if two are available) to track zero. Upon completion of a
successful Initialize, the RX02 will zero error and status and set DONE.
It will also read sector one of track one on drive O. At termination, d.rive
o head is at track one.
Name: ERROR
Bit: 15
Function: This bit is set by the RX02 to indicate that an error has
occurred during an attempt to execute a command. Cleared by the
initiation- of a new command. Read-only.
RXV21 Data Buffer Register (RX2DB)
This register serves as a general purpose data path between the RX02
and the RXV21. It may represent one of six RX02 registers according
to the protocol In progress. (See Programming Specification.) This
register is read/write if the RX02 is not in the process of executing a
command; it may be manipulated without affecting the RX02.
Caution
Violation of protocol in manipulation of this register may
cause permanent data loss.
615
RXV21
RX2DB-RXV21 Data Buffer Register
o
15
RX2WC-RXV21 Word Count Register - For a double density sector
the maximum word count is 128'0' For a single density sector the
maximum word count is 64'0' If a word count is beyond the limit for the
density indicated, the control asserts Word Count Overflow (Bit 10 of
RX2ES). Write-only register. The actual word count and not the 2's
complement of the word count is loaded into the register.
15
7
4
6
0
I, I
0
0- 12810
.
.
RX2BA-RXV21 Bus Address Register - This register specifies the
bus address of data transferred during Fill Buffer, Empty Buffer, and
Read Definitive Error operations. Incrementation takes place after a
memory transaction has occurred. The RX2BA, therefore, is loaded
with the address of the first data word to be transferred. This is a 16-bit
write-only register (See Programming).
o
15
RX2CA-RXV21 Track Address Register - This is a write-only register which is loaded to indicate on which of the 77'0 tracks a given
function is to operate. It is addressed only under the protocol of the
function in progress.
o
15
\~--------------~~--------~
0- 114 8
RX2SA-RXV21 Sector Address Register - This is a write-only
register which is loaded to indicate on which of the 26 10 sectors a given
function is to operate. It can be addressed only under the protocol of
the function in progress.
6
15
5
0
I0 I Io I
0
,
~
1-32 8
616
RXV21
RX2ES-RXV21 Error and Status Register - The RX2ES is a readonly register available at the termination (DONE) of each function. The
Drive Ready bit is only updated during an Initialize or Read Status
function. At the termination of any other function, it reflects the drive
status of the last Read Status or Initialize command.
15
12
Bit: 0
Name: CRC Error
Function: The cyclic redundancy check at the end of the data field
has indicated an error. The data collected must be considered invalid.
It is suggested that the data transfer be re-tried up to 10 times, as most
data errors are recoverable (soft).
Bit: 1
Name: Side 1 Ready
Function: This bit, when set, Indicates that a double-sided diskette is
mounted in a double-sided drive and is ready to execute a function.
This bit is only valid at the termination of an Initialize sequence or a
Maintenance Read Status command.
Bit: 2
Name: Initialize Done
Function: Indicates completion of the initialize routine. Can be asserted due to: a) a RX02 power failure, B) system power failure, C)
programmable or bus initialize.
B":3
Name: RXACLO
Function: RX power failure. Bit Is set when the subsystem power Is
gone.
Bit: 4
Name: Density Error
Function: Indicates that the density of the function in progress does
not match the Drive DenSity. Upon detection of this error, the control
terminates the operation and asserts Error and Done.
Bit: 5
Name: Drive Density
Function: Indicates the density of the diskette mounted In the drive
Indicated by the Unit Select bit.
Bit: 6
Name: Deleted Data
Function: In the course of recovering data, the "deleted data" address mark was detected at the beglnlng of the data field. The Drv Den
blt(s) Indicate whether the mark was an address mark. The data fol-
617
RXV21
lowing the mark will be collected and transferred normally, as the
deleted data mark has no further significance other than to establish
drive density. Any alteration of files or actual deletion of data, due to
this,mark, must be accomplished by user software.
Bit: 7
Name: Drive Ready
Function: The selected drive is ready if Bit 7 = 1. All conditions for
disk operation are satisfied, such as door closed, power OK, diskette
up to speed, etc. The RX02 may be presumed to be ready to perform
any operation. This bit is only valid when retrieved with a Read Status
function or initialize.
Name: Unit Select
Bit: 8
Function: This bit indicates the drive on which the previous command was executed. This bit should agree with bit 4 of the RX2CSR for
commands which require drive operation.
Bit: 9
Name: Reserved
Function:
Bit: 10
Name: Word Count Overflow
Function: The Word Count Register resides in the control. If the
control senses that the word count is beyond sector size it will terminate the Fill or Empty Buffer operation and set Error and Done.
Bit: 11
Name: Nonexistent Memory Error
Function:' This bit is set when a DMA transfer is being performed and
the memory address specified in RX2BA is nonexistent (does not respond to MSYN within 10 J.Lsec.).
PROGRAMMING
Data storage and recovery on the RXV21 occurs with careful manipulation of the two. RXV21 registers (RX2CS, RX2DB) following the strict
protocol of the individual 'function. Data may be permanently lost If the
protocol is not followed. New functions given before the completion of
Ii previous function are ignored.
618
RXV21
Function Codes
The following is a detailed description of the programming protocol
associated with each function encoded and written Into bits 1-3 of
RX2CS if DONE Is set.
Function
000
Description
Fill Buffer
This function Is used to fill the RX02 data buffer with
the number of words of data specified by the RX2WC
register. "Fill Buffer" Is a complete function In Itself.
The function ends when RX2WC overflows and, If
necessary, the control has zero-filled the remainder
of the buffer. The contents of the buffer may be written on the disk, by means of a subsequent Write
Sector command, or returned to the host processor
by an "Empty Buffer" command. To Initiate this
function, the RX2CS Is loaded with the function. Bit 4
of the RX2CS (Unit Select) does not affect this function, since no disk operation Is Involved. Bit 8 (DensIty) must be properly selected since this determines
the Word Count limit. When the command has been
loaded, the DONE bit (RX2CS Bit 5) goes false. When
the TR bit Is asserted, the RX2WC may be loaded
into the data buffer register. When TR Is again asserted, the. RX2BA may be loaded Into the RX2DB.
The data words are transferred directly from memory and DONE goes true, ending the operation, when
RX2WC overflows and the control has zero-filled the
remainder of the sector buffer, If necessary. If bit 6
RX2CS (interrrupt Enable) Is set~ an Interrupt Is
initiated. ,Any read on the RX2DB during the data
transfer Is Ignored by the RXV21. After DONE Is true,
the RX2ES is located In the RX2DB register.
001
Empty Buffer
This function Is used to empty the contents of the
Internal buffer through the RXV21 for use by the host
processor. This data Is in the buffer as the result of a
previous "Fill Buffer" or "Read Sector" command.
The programming protocol for this function Is Identical to that for the "Fill Buffer" command. The RX2CS
. 619
RXV21
Is loaded with the command to Initiate the function.
This function will ignore bit 4 RX2CS (Unit Select).
RX2CS bit 8 (Density) must be selected to allow the
proper word count limit. When the command has
been loaded, the DONE bit (RX2CS bit 5) goes false.
When the TR bit Is asserted, the RX2WC may be
loaded into the RX2DB. When TR is again asserted,
the RX2BA may be loaded into the RX2DB. The
RXV21 assembles one word of data at a time and
transfers It directly to memory. Transfers occur until
Word Count overflow, at which time the operation Is
complete and DONE goes true. If bit 6 RX2CS (Interrupt Enable) Is set, an interrupt Is initiated. After
DONE Is true the RX2ES Is located In the data buffer
register.
010
Write Sector
This function Is used to locate a desired sector on
the diskette and fill It with the contents of the Internal
buffer. The Initiation of the function clears RX2ES,
TR, and DONE.
A.
When TR Is asserted, the program must load the
desired Sector Address Into RX2DB, which will
dropTR.
TR will remain unasserted while the RX02 attempts to locate the desired sector. The diskette
density Is determined at this time and Is com.,.
pared to the function density. If the densities do
not agree, the operation Is terminated; bit 4
RX2ES Is set, RX2ES is moved to the RX2DB,
Error (bit 15 RX2CS) is set, DONE is asserted,
and an interrupt Is Initiated If bit 6 RX2CS (Interrupt Enable) Is set.
If the densities agree but the RX02 Is unable to
locate the desired sector within two diskette revolutions, the RXV21 will abort the operation,
move the contents of RX2ES to the RX2DB, set
ERROR (bit 15 RX2CS), assert DONE, and Initiate an Interrupt If Bit 6 RX2CS (Interrupt Enable)
Is set.
620
RXV21
B.
If the desired sector has been reached and the
densities agree, the RXV21 will write the 12810 or
64 10 words stored in the internal buffer followed
by a CRC character which is automatically calculated by the RX02. The RXV21 ends the function by asserting DONE and if bit 6 RX2CS (Interrupt Enable) is set, initiating and interrupt.
CAUTION:
The contents of the sector buffer are not valid data
after a power loss has been detected by the RX02.
"Write Sector" however, will be accepted as a valid
instruction and the (random) contents of the buffer
will be written, followed by a valid CRC.
NOTE:
The contents of the sector buffer are not destroyed
during a write sector operation.
011
Read Sector
This function is used to locate the desired sector and
transfer the contents of the data field to the internal
buffer in the control. This function may also be used
to rapidly retrieve (5 ms) the current status of the
drive selected. The initiation of this function clears
RX2ES, TR, and DONE.
A. When TR is asserted, the program must load the
desired Sector Address Into the RX2DB, which
will drop TR. When TR is again asserted, the
program must load the desired Cynlinder
Address Into the RX2DB, which wUl drop TR.
B.
TR and DONE will remain unasserted while the
RX02 attempts to locate the desired sector. If the
RX02 is unable to locate the desired sector within two diskette revolutions for any reason, the
RXV21 will abort the operation, set DONE and
ERROR (Bit 15 RX2CS), move the contents of
the RX2ES to the RX2DB, and If Bit 6 RX2CS
(Interrupt Enable) is set, initiate an Interrupt.
If the desired sector Is successfully located, the
control reads the data address mark and determines the density of the diskette. If the diskette
(drive) density does not agree with the function
621
RXV21
D.
100
density, the operation Is terminated and DONE
and ERROR (bit 15 RX2CS) are asserted. Bit 4
RX2ES is set (Density Error) and the RX2ES Is
moved to the RX2DB. If Bit 6 RX2CS (Interrupt
Enable) Is set, an Interrupt Is Initiated.
If the desired sector Is successfully located, the
densities agree, and the data are transferred
with no CRC error, DONE will be set and if Bit 6
RX2CS (Interrupt Enable) Is set, the RXV21 initiates an interrupt.
Set Media Density
This f.unction causes the entire diskette to be reassigned to a new density. Bit 8 RX2CS (Density) Indicates the new density. The control reformats the
diskette by writing new data address marks (double
or single density) and zeroing out all of the data
fields on the diskette.
The function Is Initiated by loading the RX2CS with
the command. Initiation of the function clears RX2ES
and DONE. When TR Is se"t, an ASCII "I" (111) must
be loaded Into the RX2DB to complete the protocol.
This extra character is a safeguard against an error
in loading the command. When the control recognizes this character It begins executing the command.
The control starts at Sector 1, Track 0 and reads the
header Information, then starts a write operation. If
the header information is damaged, the control will
abort the operation.
If the operation is successfully completed, DONE is
set and if Bit 6 RX2CS (Interrupt Enable) is set, an
interrupt is initiated.
NOTE:
If double-sided media Is mounted In a double-sided
drive, both sides are set to the same density automatically.
622
RXV21
CAUTION:
This operation takes about 15 seconds and should
not be interrupted. If for-any reason the operation Is
Interrupted, an Illegal diskette has been generated
which may have data marks of both densities. This
diskette should again be completely reformatted.
101
Maintenance Read Status
This function Is Initiated by loading the RX2CS with
the command. DONE Is cleared. The Drive Ready bit
(Bit 7 RX2ES) Is updated by counting Index pulses In
the control. The Drive Density Is updated by loading
the head of the selected drive and reading the first
data mark. All other RX2ES bits reflect the conditions created by the last command. During this
function, In addition to status, the control performs
the wraparound mode In the device electronics. If an
error occurs while wrapping the data from the Sector
Buffer through the device electronics, the Error bit
(Bit 15 RX2CS) Is set. The RX2ES Is moved Into the
RX2DB. The RX2CS may be sampled when DONE
(Bit 5 RX2CS) Is again asserted and If Bit RX2CS
(Interrupt Enable) Is set, an Interrupt will occur. This
operation requires approximately 250 msec to complete.
NOTE:
If double-sided media Is mounted In a double-sided
drive, the Side 1 Ready bit (RX2ES bit 1) Is set.
110
Write Sector With Deleted Data
This operation is Identical to function 011 (Write Sector) with the exception that a deleted data address
mark is written preceding the data rather than the
standard data address mark. The Density bit associated with the function Indicates whether a single or
double density deleted data ac;ldress mark will be
written.
111
Read Error Code
The Read Error Code function Implies a read extended status. In addition to the specific Error code,
a dump of the control's Internal scratch pad registers
623
RXV21
also occurs. This Is the only way that the Word Count
Register can be retrieved. This function is used to
retrieve specific information as well, as drive status
information, depending on detection of the general
ERROR BIT.
The transfer of the registers Is a DMA transfer. The
function Is Initiated by loading the RX2CS with the
command. DONE goes false. When TR is true, the
RX2BA may be loaded Into the RX2DB and TR goes
false. The registers are assembled one word at a
time and transferred directly to memory.
Following Is the Register Protocol.
NOTE:
The Density bit (bit 8 RX2CS) must be loaded with
the function. If the wrong assumption was made, an
error is returned.
Following is the Register Protocol.
15
WORD 1
0
'NORD COUNT REGISTER
DIFINITIVE ERROR CODE
0
15
WORD 2
CURRENT TRACK ADDR DRV 1
CURRENT TRACK ADDR DRV 0
TARGET SECTOR
TARGET TRACK
15
WORD 3
0
15
WORD 4
Table 4
10
SOFT STATUS
BAD TRACK •
Definitive Error Codes
DRIVE 0 FAILED TO SEE HOME ON INITIALIZE
20
DRIVE 1 FAILED TO SEE HOME ON INITIALIZE
40
TRIED TO ACCESS A TRACK GREATER THAN 76
50
HOME WAS FOUND BEFORE DESIRED TRACK
WAS REACHED
624
RXV21
Table 4
Definitive Error Code. (Cont)
70
DESIRED SECTOR COULD NOT BE FOUND AFTER
52 TRIES
110
MORE THAN 40 MICROSECONDS AND NO SEP
CLOCK SEEN
120
A PREAMBLE COULD NOT BE FOUND
130
APREAMBLEFOUNDBUTNOIDMARKFOUND
WITHIN ALLOWABLE TIME
150
THE TRACK ADDRESS OF A GOOD HEADER DOES
NOT COMPARE WITH DESIRED TRACK
160
TOO MANY TRIES FOR lOAM
170
DATA ARE NOT FOUND IN ALLOTTED TIME
200
CRC ON READING THE SECTOR FROM THE DISK
220
FAILED MAINTENANCE WRAPAROUND CHECK
230
WORD COUNT OVERFLOW
240
DENSITY ERROR
250
INCORRECT KEY WORD ON SET DENSITY COMMAND
RX02 Power Fall or Initialize
When the RX02 control senses a loss of power within the RX02, it will
unload the head and abort all controller action. The RXAC L line is
asserted to indicate to the RXV21 that subsystem power is gone. The
RXV21 asserts DONE and ERROR and sets the RXAC L bit In the
RX2ES.*
When the RX02 senses the return of power, It will remove DONE and
begin a sequence to:
1. Move each drive head position mechanism to track 00
2. Clear any active error bits
3. Read sector 1 of track 1, on drive 0
4. Assert Initialize DONE In the RXES
Upon completion of the power-up sequence, DONE Is again asserted.
There is no guarantee that information being written at the time of a
power failure will be retrievable; however, all other Information on the
diskette will remain unaltered.
625
RXV21
LSI-11 Bus Power. Fall
When the BPOK H line is negated by the LSI-11, the RXV21 asserts the
Initialize line and holds it asserted. The RX02 control unloads the head
and aborts controller action as detailed above. When LSI-11 power is
restored, the above power-up sequence is started.
* This is the only valid bit in the RX2ES at this time.
Programming Examples for Typical Operation
Disk Write
A typical disk write sequence, which Is initiated by the user program,
would occur in two steps.
Fill Buffer-A command to fill the buffer is moved Into the RX2CS. The
GO bit must be set. The program tests for TR. When TR Is detected,
the program moves the desired word count into the RX2DB. TR goes
false while the word count is moved to the RX02. The program retests
TR and moves the Bus Address into the RX2DB. The device now
requests bus mastership and DMA's one data word at a time Into the
RX2DB and shifts it across the RX02 data bus bit serially one 8 bit byte
at a time into the sector buffer. When the Word Count Register overflows and, if necessary, the RX02 control zero fills the remainder of the
sector buffer, the DONE bit is set and an interrupt will occur if the
program has enabled interrupts.
Write Sector-A command to write the contents of the sector buffer
onto the disk is moved into the RX2CS. The program tests TR and
when TR is set, moves the desired sector address to the RX2DB. TR
remains false while the sector address is shifted to the RX02 control.
The control retests TR and when it is again set, moves the desired
track address register to the RX2DB. Again TR Is negated. The RX02
locates the desired track and sector and compares the diskette density against the assigned function density and writes the contents of the
sector buffer onto the disk if the densities agree. When the write operation is completed, the DONE bit is set and an interrupt will occur If the
program has enabled interrupts.
Disk Read
A typical disk read operation occurs In the reverse order. First, the
desired track and sector are located and the contents of the sector are
read into the sector buffer (Read Sector). Then, the contents of the
sector buffer are unloaded into memory (Empty Buffer). In either case,
the contents of the sector buffer are not valid If either a Power Fail or
Initialize follows a Fill Buffer or Read Sector function.
626
RXV21
BOOTSTRAPPING THE RXV21
The RXV21 bootstrap loader program loads the system monitor from
disk into system memory. No system operation can occur until the
monitor is contained in system memory. Bootstrapping ("booting") the
system can be accomplished via a hardware-implemented bootstrap
in the BDV11 optiion, the MXV11-A with MXV11-A2 boot chips, or it
can be entered and executed via the console device.
The following bootstraps are entered under microcode ODT. The bootable volume must be in drive zero. All devices are at standard addresses and vectors. Enter the code starting at location 1000. Inhibit
all interrupts by entering RS/_340 . Initialize the program
counter by entering R71_1000 . After the code has been entered, type P.
LOCATION
RX02DOUBLE
DENSITY
RX02SINGLE
DENSITY
CODE
CODE
1000
12700
12700
1002
100240
100240
1004
1006
12701
177170
12701
177170
1010
5002
5002
. 1012
12705
12705
1014
200
100
1016
1020
1022
12704
401
12703
12704
401
12703
1024
177172
177172
1026
30011
1776
30011
100437
100437
12711
12711
1030
1032
1034
1776
1036
407
7
1040
30011
1042
30011
1776
1044
100432
1046
110413
100432
110413
627
1776
RXV21
RX02DOUBLE
DENSITY
RX02SINGL!
DENSITY
LOCATION
CODE
CODE
1050
304
304
1052
30011
30011
1054
1776
1776
1056
110413
110413
1060
304
304
1062
30011
30011
1064
1776
1776
1066
100421
100421
1070
12711
12711
1072
403
3
1074
30011
30011
1076
1776
1776
1100
00414
100414
1102
10513
10513
1104
1106
30011
1776
30011
1776
100410
1110
100410
1112
1114
10213
60502
10213
60502
1116
60502
60502
1120
122424
122424
1122
120427
120427
1124
3
7
1126
1130
1132
3735
12700
0
3735
12700
0
1134
5007
5007
1136
0
0
628
TEV11
TEV11 TERMINATOR
GENERAL
The TEV11 terminator module provides 120-ohm termination circuits
as shown in Figure 1.
FEATURES
SPECIFICATIONS
Identification
M9400-YB
Size
Double
Power
+5 Vdc ± 5% at O.54A
Bus Loads
o
o
AC
DC
DESCRIPTION
General
Each bus signal line terminates with two resistors as shown in Figure 2.
These termination resistors are generally contained in a 16-pin, dualin-line package which is identical to an IC package. Each package
contains 14 termination pairs. The values used are shown in the figure.
Daisy-chained grant signals are terminated and jumpered. BIAKI L is
jumpered to BIAKO Land BDMGI L is connected to BDMGO L via
factory-installed jumper W1.
+5
180n
TO/FROM
SIGNAL
LINES
120.0. BUS
TERMINATION
-----I
390n
11-3597
Figure 1
TEV11 Functions
MR·l171
Figure 2 Typical
120-0hm Bus Termination
629
TUSS
TUSS CARTRIDGE TAPE DRIVE
GENERAL
The TU5S is a low-cost intelligent mass memory device that offers
random access to block-formatted data on pocket-size cartridge
media. It is ideal as a small computer systems device, as Inexpensive
archive mass storage, or as a software update distribution medium. A
dual drive TU5S offers 512 Kb of storage space, making it one of the
lowest cost complete mass storage subsystems available.
Figure 1
loading a Cartridge
630
TU58
FEATURES
• 512 Kb per dual drive subsystem
• RS422, RS423, and RC232-C serial line I/O
• Reliable 30 inches per second read/write tape speed combined with
60 inches per second bidirectional search speed
• Flexible baud rates from 150 to 38,400
• Complete tape subsystem on one P.C. module for compact
mounting
• Microprocessor-based subsystem with automatic soft-error reCovery via rereads.
SPECIFICATIONS
Performance
Capacity per cartridge
262,144 bytes, formatted In 512
blocks of 512 bytes each
Data reliability
Soft data error rate
1 in 107 bits read (before self-correction)
Hard error rate
1 In 109 bits read (unrecoverable
within eight automatic retries)
Hard error rate with write verify
and system correction
2 in 10" bits read/written
Error checking
Checksum with rotation
Average access time
9.3 seconds
Maximum access time
28 seconds
Read/write tape speed
76 cm/s (30 Ips)
Search tape speed
152 cm/s (60 Ips)
Bit density
315 bits/cm (800 bits/in.)
Flux reversal density
945 fr/cm (2400 frlin.)
Recording method
Ratio encoding
Medium
DECtape II cartridge with 42.7 m
(140 ft.) of 3.81 mm (0.150 In.)
tape
Size: 6.1 X 8.1 X 1.3 cm (2.4 X
3.2 X 0.5 in.)
631
TU58
Track format
Two tracks, each containing 1024
individually numbered, flrmwareInterleaved "records." Firmware
manipulates four records at each
operation to form 512-byte
blocks.
Drive
Single motor, head Integrally cast
Into molded chassis.
Drives per controller
1 or 2. Only one may operate at a
time.
Electrical
Power consumption
Module and 1 or 2 drives
11 W, typical, drive running
+5V ±5% at 0.75A, maximum
+12V + 10% -5% at 1.2A, peak
0.6A average running
0.1Aldle
Serial interface standards
I n accordance with RS422 or
RS423; compatible with RS232·C.
Mechanical
Drive
8.1 H X 8.3 D X 10.6 Wcm (3.2 X
3.3 x 4.1 In.) with 19 cm (7.5 In.)
cable 0.23 Kg (0.516Ibs.)
Board (Module)
13.2 H X 26.5 D X 3.5 W cm (5.19
X 10.44 X 1.4 In.) 0.24 Kg (0.5316
Ibs.)
Power connector to module
AMP 87159-6 with 87027-3 contacts (DEC part nos. 12-1220209, 12-12203-00)
Interface connector to module
AMP 87133-5 with 87124-1 lockIng clip contacts and 87179-1 Index pin (DEC part nos. 12-1426802, 12-14267-00, 12-15418-00)
632
TU58
Environmental
Maximum dissipation
34 Btu/hour
TU58-AB, TU58-BB
Temperature
TU5S-AB, BB operating
TU58-AS,BS nonoperating
-34°C (-30°F) to 60°C (140°F)
Medium operating
temperature
ooe (32°F) to 50 e (122°F)
0
Maximum temperature
difference between system
ambient and TU5S module
Relative Humidity, noncondenslng
TU58 operating
Maximum wet bulb
26°C (79°F)
Minimum dew point
2°C (36°F)
Relative humidity
20% to 98%
TU58 nonoperating
5% to 98%
Medium nonoperating
10% to 80%
DESCRIPTION
General
The tape cartridges are DIGITAL preformatted miniature reel-to-reel
packages containing 42.7 m (140 ft.) of 3.81 mm (0.15 In.) wide tape.
The tape Is driven by a single puck which engages a roller which
moves an elastomer drive belt In the cartridge. This belt loops around
both tape spools and provides uniform tension and spill-free winding
without mechanical linkages (Figure 1). The simple single-point drive
mechanism allows high reliability for the entire system.
The control and drive circuitry of the TU58 Is located on a single circuit
board. The motor, tape head control, driver, and switching circuits to
manage the tape drives are located on the prInted circuit board along
with the subsystem's microprocessor. Operational amplifiers, comparators, and logic circuits perform amplification, signal switching and
633
TU58
conditioning, proportional control, and logic steering functions in the
controller. The tape is protected by motor current limiting and an antirunaway timer. Although the controller supports one or two drives,
only one drive can operate at a time. Head selection and motor
selection, speed and direction changes, etc., are managed by outputs
from 1/0 ports on a peripherallC. The mechanical actions of the drives
themselves are supervised by the microprocessor to improve the system's performance.
TU58
HOST
CONT'NUE
I
DATA
PACKET
CONTINUE
DATA
PACKET
Figure 2
An Exchange in Radial Serial Protocol
Because of the microprocessor intelligence, requests from the host for
data retrieval or storage need only contain simple specifications about
the transfer. The controller positions the tape and performs the transfer without supervision from the host.
The host and controller communicate in a format called Radial Serial
Protocol (RSP). The RSP uses two kinds of byte sequences called
message packets. Both commands and data packets have protocol
information placed in specific locations in the byte sequence. This
format is easily generated by the TU58, making host-peripheral interaction possible at a high level with low cost.
Figure 2 illustrates a typical RSP exchange between a host computer
and the TU58.
634
TU58
The serial host interface operates on full-duplex, asynchronous 4-wire
lines at jumper-selectable rates from 150 to 38,400 baud. The send
and receive rates may be Independently set with jumpers to operate in
accordance with Electronic Industries Association (EIA) Standards
RS422 or RS423. When set to RS423, the TU58 Is also compatible with
devices complying with RS232-C.
Figure 3 illustrates the structure of the TU58 system. The data path is
along the top of the diagram, passing to the host through the processor at the right. The drive control is at the lower left, also closely
associated with the processor through the I/O ports. The ports, memory, and universal asynchronous receiver-transmitter (UART) are tied
to the processor by an 8-blt-wlde data/address bus.
TO HOS'
Figure 3
TU58 Block Diagram
The cartridge drive motors are powered by servo-regulated speed and
direction circuits. These are controlled by the processor, which monitors with tachometers and with signals from the tape. The heads are
selected by processor-controlled switches and either feed the automatic-gain-controlled (AGC) read amplifier and decoder circuits or
are driven by write currents encoded by the processor.
635
TU58
The processor consists of an 8085 processor supported by firmware In
a 2 Kb read-only memory (ROM) and by scratchpad and data buffer
memory in a 256-byte random access memory (RAM). The processor
communicates with the drive control circuity through a bidirectional
1/0 port. The UART exchanges data between the TU58 processor bus
and the host computer via the serial line drivers and receivers.
CONFIGURATION
The TU58 Is available in
accompanying designations:
Components
TU58-AB
TU58-88
t~e
following configurations with
Serial Interface controller module, surface
mounting, with one drive.
Serial Interface controller module, surface
mounting, with two drives.
Additional Supplies
TU58-K preformatted tape cartridges.
TUC-01 Tape Drive Cleaning KIt.
OPERATION
The TU58 may be supplied with power from a host system. It Is ready
for operation within 1 second of voltage stabilization. It does not need
to be turned off when not In use; Its idling power consumption Is less
than 5 W.
When power is applied, the TU58 Initializes Itself, performs Its Internal
diagnostic tests, and then asks the host for an acknowledgement before It settles down to wait for Instructions. Refer to the Programming
section for a description of the required exchange.
If power is removed while a tape is being written, data may be lost, but
there are no other restrictions on power removal.
636
TU58
DRIVE PUCK
MICROSWITCHES
SWINGOUT
GATE
WRITE PROJECT
TAB
TAPE
TAPE
CARTRIDGE
Figure 5
ELASTOMER
BELT
Tape Cartridge Partially Inserted Into Drive
Cartridge Loading
The TU58 drive is designed to make correct loading easy. To load the
cartridge, hold it label-up, line it up with the grooves In the chassis,
and slide It in with a firm push. Figure 1 illustrates the fit of the car~
tridge into the drive chassis grooves.
Cartridge Unloading
Unloading the cartridge Is as simple as loading. Just pull It straight out.
It is best to wait for the tape to stop, as indicated by the run light,
before removing the cartridge. The mechanism cannot be damaged
by removing the cartridge while the tape is moving, but if a write Is in
progress, data may be lost. An error message will be sent to the host if
a command is Interrupted by removal of a cartridge.
Keeping Track of Cartridges
If the TU58 is used in a non-file-structured system, the cartridge does
not have an Identifying number or label recorded on the tape. If a
cartridge is changed, the T058 will not know that a different cartridge
. was loaded; the operator must keep track of the contents of various
cartridges.
637
TU58
Write Protect Tab
Each tape cartridge has a movable tab which, when properly positioned, protects data on the tape from unintended write operations.
When this write protect tab (Figure 6) is in the inner position (toward
the drive roller), it locks out the write circuity.
When the write protect tab is in the outer position, it closes a switch in
the chassis and allows the controller to write when it is commanded to.
The operator should be sure that system or program tapes are backed
up with copies before loading them into the TU58 with their write
protect tabs set to record.
WRITE PROTECT TAB IN
PROTECT POSITION
MOVE TO LEFT TO PROTECT
"A·23&~
Figure 6
Write Protect Tab
Cartridge Storage and Care
Store cartridges in their cases, away from dust and heat or direct
sunlight. Do not touch the tape; there is no safe way to clean the tape
and permanent errors may result. Keep tools and other ferrous or
magnetic objects away. If a tape is suspected of having been exposed
to environmental extremes as listed in the specifications and if the
software operating system permits, wind it all the way through by
requesting positioning to blocks at each end of the tape before attempting to store data on the cartridge.
638
rU58
MAINTENANCE
Head and Puck Cleaning
After 100 hours of tape running time or semi-annually, clean the head
and motor puck with a long handled cotton applicator moistened with
DEC cleaning fluid (from cleaning kit TUC-01), 95 percent Isopropyl
alcohol, fluorocarbon TF, 113 or equivalent (Figure 7). Push the puck
around ~ith the applicator to clean its entire surface. Regular cleaning
minimizes tape and head wear and prevent tape damage and data
errors caused by contamination. A new drive requires head cleaning
after the first 20 hours of actual use. After this Initial cleaning, 100 hour
intervals are adequate. This is the only regular maintenance required
for the TU58.
Wrl3
I
7lV:@lI:l
DRIVE PUCK
MICROSWITCHES
Figure 7
TAP~HEAD
View Into Tape Drive Cartridge Slot
PROGRAMMING
The TU58 Is controlled by a high-level command set that relieves the
host computer of device-related operations such as tape positioning
and read retries. The TU58 firmware contains subroutines that are
activated by brief strings of command bytes. The command strings
contain the numerical code for the operation to be performed and the
location and size of data files that are to be transferred, when applicable. They also contain various housekeeping characters that are part
of the Radial Serial Protocol (RSP) under which the byte sequences
are defined. The byte sequences are called message packets and are
designed to be transmitted by asynchronous interfaces.
Block Number, Byte Count, and Drive Number
The TU58 uses the block number and byte count to write or retrieve
data. If all of the desired data Is contained within a single 512-byte
block, the byte count will be 512 or less. When the host asks for a
particular block and a 512-or-less byte count, the TU58 will position
the specified drive (unit) at that block and transfer the number of bytes
specified. If the host asks for a block and also a byte count greater
639
TUSS
than that of the 512-byte boundary, the TU58 will read as many
sequential blocks as are needed to fulfill the byte count. The same
process applies to the write function. This means that the host software or an on-tape file directory need only store the number of the first
block in a file and the file's byte count to read or write all the data
without having to know the additional block numbers.
Special Handler Functions
Some device-related functions are not dealt with directly in the RSP or
in the TU58 firmware.
A TU58 handler should check the success code (byte 3 of the RSP end
message) for the presence of soft errors. This enables action to be
taken before hard errors (permanent data losses) occur. For example,
if the number of retries on a particular cartridge reaches some value, a
message like "Tape Maintenance Required" could be presented to the
operator. This would suggest that prompt tape copying and head
cleaning is in order.
RADIAL SERIAL PROTOCOL (RSP)
Message Packets
All communication between the TU58 and the host is divided into
message packets, which are groups of bytes arranged in fixed order.
Position within the packet determines the meaning of each byte. There
are three kinds of message packets: command, data, and end messages. The end message is a special case of the command packet. In
addition, there are three single-byte protocol management messages:
INIT, Continue, and XOFF.
Each packet begins with a flag byte, which announces its contents.
The next byte in a message packet is the byte count. This is the number of message characters in the packet, excluding the flag, byte
count, and checksum. Up to 128 message bytes may be in each packet. Larger blocks of data are sent with multiple packets. The last two
byte pairs of the message packet are a 16-bit checksum. The checksum is formed by summing sucessive byte pairs taken as 16-bit words
and using an end-around carry from bit 15 to bit O. The flag and byte
count are included in the checksum.
640
TU58
Flag Byte Op Codes
Bits 7-5 of the op code are reserved.
018
028
048
108
20 8
238
00001
00010
00100
01000
10000
10011
Data
Control (command)
INIT
Bootstrap
Continue
XOFF
Data
This flag informs the receiver that data rather than
commands are arriving. The receiver loads the incoming bytes into a buffer area in memory. It does
not look for an op code to execute.
Command
The command flag informs the TU58 that a command packet follows. An instruction code will be in
this packet. The flag Is particularly Important when
the TU58 encounters an error condition. In this case,
it sends an end packet before data transfer is
complete. The host knows that the end packet has
been sent because the packet received has a command flag instead of a data flag.
INIT
This op code is sent from the host to cause the TU58
to execute its power-up sequence. The TU58 returns
Continue after completion. It is sent from the TU58 to
the host to indicate that the power-up sequence has
occurred. When the TU58 makes a protocol error or
receives an invalid command, it reinitializes and
send INIT continuously to the host. When the host
recognizes INIT, it send Break to the TU5S to restore
the protocol.
Bootstrap
A flag byte saying Bootstrap (octal 10), followed by a
byte containing a drive number, causes the TU58 to
read block 0 of the selected drive. It returns the 512
bytes without radial serial packaging. This simplifies
bootstrap operations. Bootstrap may be sent by the
host instead of a second INIT as part of the Initialization process described below.
641
TU58
Continue
After a message is sent from host to the TU58, the
host must wait until the TU58 sends Continue before
any more messages can be sent. This permits the
TU58 to control the flow of data.
XOFF
Ordinarily, the TU58 does not have to wait between
messages to the host. However, if the host is unable
to receive all of a message from the peripheral at
once, it may send XOFF. The TU58 stops transmitting immediately and waits until the host sends Continue to complete the transfer when it is ready. (Two
characters may be sent by the UART to the host after
the TUS8 receives XOFF).
Break and Initialization
Break is a unique logic entity that can be interpreted by the TUS8 and
the host regardless of the state of the protocol. Break is transmitted
when the serial line, which normally switches between two logic states
called mark and space, is kept in the "space" condition for more than
one character time. This causes the TUS8's UART to set its framing
error bit. The TUS8 will interpret the framing error as break.
Break has two applications in the TUS8: one is routinely used, and the
other is for special conditions. When the TUS8 is powered up, it performs its internal checkout and initialization and then transmits INITs
continuously to the host to inform the host that it is present. The host
acknowledges the TUS8 by sending break for a minimum of one
character time, and then sending two INITs. The TUS8 responds with
Continue and enters an idle state in which it will wait for further instructions.
If communications break down, due to any transient problem, the host
may restore order by sending break and INIT as outlined above. Whatever faulty operations were underway will be cancelled, and the TUS8
will reinitialize itself, return Continue, and wait for instructions.
With DIGITAL serial interfaces, the initialize sequence may be sent by
the following sequence of operations. Set the break in the transmit
control status register, then send two null characters. When the transmit ready flag is set again, remove the break bit. This will time Break to
be one character time long. The second character will be discarded by
the TU58 controller. Next, send two INIT characters. The first will be
discarded by the TU58. The TU58 will respond to the second INIT by
sending Continue. When Continue has been received, the initialize
sequence is complete and any command packet may follow.
642
TU58
COMMAND SET
The command set for the TUS8 provides capabilities for random access operations. To allow for future development, certain op codes in
the command set have been reserved; these commands have
unpredictable results and should not be used. Op codes not listed in
the command set are illegal and result in the return of an end packet
with the "bad op code" success code.
A data transfer operation uses three or more message packets. The
first packet is the command packet from host to the TUS8. Next, the
data is transferred in 128-byte packets in either direction (as required
by read or write). After all data is transferred, the TUS8 sends an end
packet. If the TUS8 encounters a failure before all data has been transferred, it sends the end packet as soon as the failure occurs.
Command Packets
The command packet format is shown in Table 1. Bytes 0, 1, 12, and
13 are the message delivery bytes. Their definitions are as follows.
Table 1
Byte
Command Packet Structure
1
2
3
4
S
6
7
8
9
10
11
12
13
Byte Contents
Flag = 00000010 (02 8)
Message Byte Count = 0000 1010 (128)
OpCode
Modifier
Unit Num~er
Switches
Sequence Number-Low
Sequence Number-High
Byte Count-Low
Byte Count-High
Block Number-Low
Block Number-High
Checksum-Low
Checksum-High
o
Flag
o
This byte is set to 00000010 to
indicate that the packet is a
Command packet.
643
TU58
12, 13
Message Byte Count
Number of bytes In the packet
excluding the four message
delivery bytes. This is decimal
10 for all command packets.
Checksum
The 16-bit checksum of bytes
othrough 11. The checksum Is
formed by treating each pair of
bytes as a word and summing
words with end-around carry.
The remaining bytes are defined as follows.
2
Op Code
Operation being commanded.
Refer to Table 2 for definitions.
3
Modifier
Permits variations of commands.
4
Unit Number
Selects drive 0 or 1.
5
Switches
Selects maintenance mode.
6, 7
Sequence Number
Always zero for TU58.
8,9
Byte Count
Number of bytes to be transferred by a read or write command. Ignored by other commands.
10,11
Block Number
The block number to be used
by commands requiring tape
positioning.
644
TUSS
Table 2
Instruction Set
Decimal
OpCode
Octal
OpCode
Instruction
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
10
11
12
13
NOP
INIT
Read
Write
(Reserved)
Position
(Reserved)
Diagnose
Get Status
Set Status
(Reserved)
(Reserved)
Maintenance Mode - Setting bit 4 of the switches byte (byte 5) to 1 in
a read command inhibits retries on data errors. Instead, the incorrect
data is delivered to the host followed by an end packet. The success
code in the end packet Indicates a hard data error. Since data Is
transmitted in 128-byte packets, a multiple packet read progresses
normally until a checksum mismatch occurs. Then the bad packet is
transmitted, followed by the end packet, and the operation terminates.
Special Address Mode - Setting the most significant bit of the modifier byte to 1 selects special address mode. In this mode, all tape
positioning operations are addressed by 128-byte blocks (0-2047) instead of 512-byte blocks (0-511). Zero-fill in a write operation only fills
out to a 128-byte boundary in this mode.
Data Packets
The data packet is shown in Table 3. The flag byte is set to 00000001.
The number of data bytes may be between 1 and 128 bytes. For data
transfers larger than 128 bytes, the transaction is broken up and sent
128 bytes at a time. The host is assumed to have enough buffer capacity to accept the entire transaction, whereas the TU58 only has 128
bytes of buffer space. For write commands, the host must wait
between message packets for the rU58 to send the Continue flag
(00010000) before sending the next packet. Since the host has enough
buffer space, the TU58 does not wait for a continue flag between
message packets when it sends back read data.
645
TU58
Table 3
Data Packets
1
2
3
Byte Contents
Flag = 0000 001
Byte Count = M
First Data Byte
Data
M
M+1
M+2
M+3
Data
Last Data Byte
Checksum L
Checksum H
Byte
o
End Packets
The end packet is sent to the host by the TU58 after completion or
termination of an operation or on an error. The end packet is shown in
Table 4. The definition of bytes 0, 1, 12, and 13 are the same as for the
command packet. The remaining bytes are defined as follows.
Op Code-0100 0000 for end packet
Byte 2
Byte 3
Octal
o
1
377
376
370
367
365
357
340
337
320
311
Success Code
-0 = Normal
-1 = Success but with Retries
-1 = Failed Self-Test
-2 = Partial Operation (End of Medium)
-8 = Bad Unit Number
-9 = No Cartridge
-11 = Write Protected
-17 = Data Check Error
-32 = Seek Error (Block Not Found)
-33 = Motor Stopped
-48 = Bad Op Code
-55 = Bad Block Number (i.e., > 511)
Byte 4
Unit Number 0 or 1 for Drive Number
Byte 5
Always 0
646
TU58
Bytes 6, 7
Sequence Number - always 0 as in command packet
Bytes 8,9
Actual Byte Count - number of bytes handled In transaction. In a good operation, this
will be the same as the data byte count In
the command packet.
Bytes 10,11
Summary Status
Byte 10
BitO
Byte 11
BltO
1
Reserved
2
3
4
5
6
7
Table 4
Logic Error
Motion Error
Transfer Error
Special Condition (Errors)
End Packet
Byte
Byte Contents
o
Flag = 00000010
Byte Count = 00001010
Op Code = 01"000000
Success Code
Unit
Not Used
Sequence No. L
Sequence No. H
Actual Byte Count L
Actual Byte Count H
Summary Status L
Summary Status H
Checksum L
Checksum H
1
2
3
4
5
6
7
8
9
10
11
12
13
647
TUSS
THE INSTRUCTION SET
The instructions and their op codes are shown in Table 2. The fonowing is a brief description and usage example of each.
OP CODE 0
NOP
This instruction causes the TU58 to return an end packet. There are no
modifiers to NOP. The NOP packet Is shown below.
BYTE
o
1
2
3
4
5
6
7
8
9
10
11
12
13
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0010
1010
0000
0000
ooox
0000
0000
0000
0000
0000
0000
0000
001X
1010
FLAG
MESSAGE BYTE CNT
OPCODE
MODIFIER
UNIT NUMBER (IGNORED)
SWITCHES (NOT USED)
SEQ NO.
SEQ NO. NOT USED
BYTECOUNTL
NO DATA
BYTECOUNTH
INVOLVED
BLOCK NO. L
NO TAPE
BLOCK NO. H
POSITION
CHECKSUM L
CHECKSUM H
The TU58 returns the following end packet.
o
1
2
3
4
5
6
7
8
9
10
0000
0000
0100
0000
0000
0000
0000
0000
0000
0000
0000
XXXX
0010
1010
0000
0000
OOOX
0000
0000
0000
0000
0000
0000
11
12
OOOX
XXXX
XXXX
13
XXXX
XXXX
FLAG
MESSAGE BYTE CNT
OPCODE
SUCCESS CODE
UNIT NUMBER (IGNORED)
NOT USED
SEQ.L
SEQ. H NOT USED
ACTUAL BYTE CNTL
NO DATA
ACTUALBYTECNTH INVOLVED
SUMMARY STATUS L
SUMMARY STATUS H
CHECKSUM L
CHECKSUMH
648
TUS8
OP CODE 1
INIT
This instruction causes the TU58 controller to reset itself to a ready
state. No tape positioning results from this operation. The command
packet Is the same as for NOP except for the op code and the resultant
change to the low order checksum byte. The TU58 sends the same
end packet as for NOP after relnltializing Itself. There are no modifiers
toiNIT.
OP CODE 2
Read, and Read with Increased Threshold
This instruction causes the TU58 to position the tape In the drive
selected by Unit Number to the block designated by the block number
bytes. It reads data starting at tile designated block and continues
reading until the byte count (command bytes 8 and 9) is satisfied. After
data has been sent, the TU58 sends an end packet. Byte 3 Indicates
success, success with retries, or failure of the operation. In the event of
failure, the end packet is sent all the time of failure without filling up the
data count. The end packet will be recognized by the host by the flag
byte. The host will see a command flag (00000010) instead of a data
flag (0000 0001).
There is one modifier to the read command. A modifier of 0000 0001
causes the TU58 to read the tape with an increased threshold in the
data recovery circuit. This makes the tape drop bits if any weak spots
are present. Thus, if the TU58 can read error-free in this mode, the
data is healthy. The read transaction between TU58 and host is shown
In Figure 8.
HOST
~
TU5S
_ _--,I
i-HI "~:;,, I
I
;2~:~ES
I
-H
I 12::::ES I
-H
1126
DATA
BYTES
-1 '"
Figure 8
I
Read Command Packet Exchange
649
TU58
OP CODE 3
Write, and Write and Read Verify
This op code causes the TU58 to position the tape in the selected drive
to the block specified by the number in bytes 10 and 11 of the command packet and write data from the first data packet into that block. It
writes data from subsequent data packets into one or more blocks
until the byte count called out in bytes 8 and 9 of the command packet
has been satisfied.
The controller automatically zero-fills any remaining bytes in a 512byte tape block.
There is one modifier permitted with the write command. A modifier of
000 0001 causes the TU58 to write all of the data and then back up and
read the data just written with increased threshold and test the checksum of each record. If all of the checksums are correct, the TU58
sends an end packet with the success code set to 0 (or 1 if retries were
necessary to read the data). Failure to read correct data results in a
success code of -17 (1110 1111) to indicate a hard read error.
The write operation has to cope with the fact that the TU58 only has
128 bytes of buffer space. It is necessary for the host to send a data
packet and wait for the TU58 to write it before sending the next data
packet. This is accomplished using the continued flag. The continue
flag is a single byte response of 001 0000 from TU58 to host. The write
operation is shown for both write and writelverify operations in Figure
9.
OPCODE4
(RESERVED)
POSITION
OP CODE 5
This command causes the TU58 to position tape on the selected drive
to the block deSignated by bytes 10 and 11. After reaching the selected block, it sends an end packet. No modifiers are used.
OPCODE6
(RESERVED)
DIAGNOSE
OPCODE7
This command causes the TU58 to run its internal diagnostic program
which tests the processor, ROM, and RAM. Upon completion, TU58
sends an end packet with appropriate success code (0 = Pass. -1 =
Fail).
GET STATUS
OP CODE 8
This command is treated as an NOP. The TU58 returns an end packet.
650
TU58
OPCODE9
SET STATUS
This command is treated as an NOP because TU5S status cannot be
set from the host. The TU5S returns an end packet.
OP CODE 10 (RESERVED)
OP CODE 11 (RESERVED)
TU5S
HOST
COMMAND
PACKET
WRITE
620
BYTES
CONTINUE
DATA
128 BYTES
TAPE POSITIONS
AND WRITES DATA
.
CONTINUE
DATA
128 BYTES
I
TAPE POSITIONS
AND WRITES DATA
.
CONTINUE
DATA
126 BYTES
..
--~--II
DATA
128 BYTES
---:---11
TAPE POSITIONS
AND WRITES DATA
CONTINUE
TAPE POSITIONS
AND WRITES DATA
CONTINUE
I
I
DATA
108 BYTES
TAPE POSITIONS AND WRITES
DATA. TU68 ZERO·FILLS REMAIN·
ING 404 BYTES OF BLOCK. IF WRITEI
VERIFY, TAPE REWINDS AND READS
BLOCKS JUST WRITTEN AND TESTS
CHECKSUMS.
-----II SUCCE::~AILURE I
Figure 9
IIA-2377
Write Command Packet Exchange
651
TUSS
DRIVE AND MODULE INSTALLATION
Figures 10 and 11 provide the mounting dimensions for the circuit
board (module) and drive mechanism. The drive has a 19 cm (7.5 In.)
cable which plugs into the module header with the wires coming out of
the plug toward the center of the module. The plug is keyed to ensure
proper orientation. The cartridge extends 1.60 cm (0.62 in.) from the
front of the drive. If the drive Is recessed In a panel, clearance must be
provided around the opening for fingers to grip the cartridge. Ideally,
the cartridge slot In a front panel will be somewhat larger than minimum, to allow easy insertion. The opening should be at least the
dimensions of the cartridge, 1.3 cm (0.5 In.) X 8.1 cm (3.2 In.)/Iocated
not more than 0.53 cm (0.17 In.) above the bottom mounting surface.
The module should be mounted on a flat surface with 3 mm (4-40)
hardware and 1 cm (3/8 In.) standoffs. Both the module and the drive
may be mounted at any angle. For mounting to a surface above the
drives, the 1.80 cm (0.71 In.) clearance Is required; hole spacing is
given In the outline drawings. For mounting to a surface below the
drives, an 8.18 cm (3.22 in.) X 8.89 cm (3.50 In.) chassis cutout is
required, with the same mounting hole spacing.
CAUTION
The mounting surface for the drives must be flat within
0.64 cm (0.025 In.).
INTERFACE STANDARDS SELECTION AND SETUP
The TU58 is shipped with factory-Installed Jumpers for a transmission
rate of 38.4 kilobaud and the RS-423 unbalanced line Interface (Figure
14). A variety of standards and rates may be selected by changing the
jumpers on the controller module. Table 5 provides a list of all the pins
on the board and their functions, Including the wire-wrap (WW) pins,
Interface, and power connectors.
652
TU58
10.46
1+----(4.12)-----.t
A
-r
8.266
(3.26)
1.71)
1.80
l3.60~
(1.38) CIA
8.89
(3.50)
Figure 10
MEASUREMENTS ARE IN
CENTIMETERS EXCEPT
VALUES IN PARENTHESES
ARE IN INCHES.
Drive Outline Drawings
653
TU5S
te--------- 1924.853
.785)---------..
.64
(,251
ill·
.48
191
-IT--AMP HEADER #B7633-6 AMP 1187272-8
MATE AMP #87159-6
DECPT//12·13506-04
WITH #87027 CONTACTS MATE AMP #87133-5
12.319
14.850)
~~~~:~~OVE/
I
I
x
WITH 1187124_1 CONTACTS
0.510.21 BELOW
SERIAL INTERFACE
CONNECTOij
~EA~,..,; 10+12 POWER
y - - - - .....
3
5
II
GND CONNECTOR
+5
DRIVE 0
I
I
DRIVE 1
I
..-----I~-.,~~---------..
1~1~~)
12.235
I
14.817)
~ 4.72
UJ.-':
I
I
17.734
/4-------16.9821-----.-t·
1+---------~:.SI;) -------=-::-=::-:-----ef
.48
(.191
.58
(.231
/4------------fl~.~~41-----------..
MEASUREMENTS ARE IN
CENTIMETERS EXCEPT VALUES IN
PARENTHESES ARE IN INCHES
MEASUREMENTS ARE ± .0131.0051 CENTER TO
CENTER
_·2370
Figure 11
Table 5
Module Outline Drawing
TU58 Module Connections
Wire-Wrap
Pins
WW1
WW2
WW3
WW4
WW5
WW6
WW7
WW8
WW9
WW10
WW11
WW12
WW13
150 baud
300 baud
600 baud
1200 baud
2400 baud
4800 baud
9600 baud
19,200 baud
38,400 baud
UART Receive Clock
UART Transmit Clock
Auxiliary A (to interface connector pin L)
Auxiliary 8 (to Interface connector pin A)
654
TU58
WW14
WW15
WW16
WW17
WW18
WW19
WW20
WW21
WW22
WW23
WW24
Factory Test Point
Ground
Boot Connect together for auto-boot on power-up
RS-423 Driver
RS-423 Common (Ground)
Transmit Line +
Transmit Line RS-422 Driver +
RS-422 Driver Receiver Series Resistor
(Jump for RS-422)
Serial Interface Connector
J2-10
Auxiliary B
J2-9
Ground
J2-8
Receive Line +
J2-7
Receive Line J2-6
Key (no connection)
J2-5
J2-4
J2-3
J2-2
J2-1
Ground
Transmit Line Transmit Line +
Ground
Auxiliary A
J3,4-9
J3,4-10
J3,4-11
J3,4-12
J3,4-13
J3,4-14
J3,4-15
J3,4-16
LED
Head Shield Ground
Erase Return
Erase 1
Erase 0
Head Return
Head 0
Head 1
Power Input Connector
J1-1
+12V
J1-3
Ground
+5V
J1-5
J1-6
Ground
Drive Cable
J3,4-1
CartL
J3,4-2
No Con nection
J3,4-3
Permit L
J3,4-4
Signal Ground
J3,4-5
Motor +
J3,4-6
Motor J3,4-7
+12V
J3,4-8
Tachometer
655
TU58
1200
M
4K
FT
300
M
lK
FT
150
M
500
FT
"\.~
~~~4,
'\~"0
-"'",~
~1!
~(C'()
CABLE
LENGTH
30
M
100
FT
15
M
50
FT
M
10
FT
K~~G'
~
~
300 600 1 K
2K
5K
10K 20K 40K
DATA RATE IN BAUDS
RS-423
Figure 12
_·2388
Data Rate and Cable Length for RS-423
Selecting Interface Standards
The serial interface operates on fu"-duplex, asynchronous 4-wire lines
at rates from 150 baud to 38.4 kilobaud. The transmit and receive
rates may be independently set. Each 8-bit byte is transmitted with
one start bit, one stop bit, and no parity. The line driver and receiver
may be set to operate with EIA RS-422 balanced or RS-423 unbalanced signal standards. When set to RS-423, the TU58 Is compatible
with devices complying with RS232-C.
The TU58 Is shipped prewired for operation at 38.4 kilobaud transmit
and receive on RS-423. The maximum wire length that may be used at
the data rate in an electrica"y quiet environment Is approximately 27
m (90 ft.). The wire used with any installation should be no less than 24
AWG diameter.
Longer wire runs may be made If data rates are reduced. RS-422 Is
considerably more noise-Immune than RS-423 and can be used over
at least 1200 m (4000 ft.) at any TU58 data rate. Figure 12, derived
from the EIA standards, Illustrates the variations in distance needed by
RS-423 for different data rates. For more Information, consult the
standards for RS-422 and RS-423 published by the Electronic Industries Association.
656
TU58
Connecting Standard Jumpers
The jumper pins are standard 0.635 mm (0.025 in.) wire-wrap posts
which may be connected using 30 AWG wire and a hand tool. Other
techniques that may be used include slip-on connectors such as DEC
H821 Grip Clips, 915 patchcords, 917 daisy-chain, or soldering.
The baud rates may be set independently for transmission and reception, or both can operate together. Simply connect the pin with the
desired baud value to either the XMIT or RCV pins or both. Figure 13
illustrates the pin locations, and Figure 14 shows the factory-wired
configuration.
Leo
0'" f5l t;1
bJ EJ
,~~H; [:]
160+ WW
300+ 1
w
!~Ei 8~bJ
8
9600+
19.2K+
232~117--1-9_ . . . . J
423 18-20
Figure 13
B
XMIT +CLK
AUXA+
AUX8+~
422
21-19
22-20
23-24
6 3~~~!CLK
ww
ww
24
17
++++++++
Interface Selection Jumper Pin Locations
657
TU58
38.4 kbaud Rev + TRANS RS-423
o
o
o
o
o
o
ooooOObO
mrnD
Figure 14
Factory Wiring
The interface standards may be selected by connecting sets of pins
together. The connections are listed in abbreviated form in Figure 13.
The group of pins 17 through 24 are the interface pins. The module is
shipped prewired for RS-423 with pin 17 connected to pin 19, and pin
18 connected to pin 20. No other pins in the group are connected.
For RS-422, pin 21 should be tied to pin 19, pin 22 to pin 20, and pin 23
to pin 24. No other pins in the group are connected.
BLOCK DIAGRAM
Figure 3 shows the signal and control paths between the various elements of the TUS8 and between the TUS8 and its internal microprocessor. This diagram illustrates the control the microprocessor has
over activities in the TUS8,
Data Flow, Tape to Interface
The tape track is selected by signals from the 1/0 ports. Recorded
data passes through the selection circuits to the read amplifier. There,
the signal amplitude is adjusted to a standard level by the automatic
gain control (AGe) action of the circuit. The Gain Reduce signal allows
detection of weak recordings. The slope changes of the sinusoidal
signal are sensed by the peak detector that produces a squarewave
with a duty cycle similar to that of the original encoded data. The duty
cycle is decoded to data bits by an integrater in the bit detector that
658
TU58
delivers the bits to the microprocessor serial data input (SID) with a
strobe signal from the peak detector.
The microprocessor deserializes the read data and stores it In the data
buffer area of memory. After a 128-byte record has been stored, a
checksum calculated from the read data is compared with the
checksum read from the tape. If they do not match, retries are attempted. Failure is indicated to the host in an end packet. Success
results in the transfer of the data, one byte at a time, to the interface. If
the unit has a parallel interface, the data is transferred eight bits at
time upon receipt of a strobe from the host. If the unit has a serial
interface, the data is loaded into a UART and transmitted through line
drivers with one start bit and one stop bit. A charge pump supplies
negative voltage for the bipolar EIA line drivers since the power supply
only produces positive voltages.
a
Data Flow, Interface to Tape
Data enters the interface and is latched (parallel) or deserlallzed and
stored In a register (serial). The microprocessor receives a ready signal from the interface and transfers the data to a buffer area in memory. The data then re-enters the microprocessor, is serialized, ratloencoded, and sent to the write circuit through the serial data output
(SOD). When the write circuit interlock is released by the cartrldgeactivated write permit switches on the drives, write current Is delivered
to the correct head gap by selection circuits under microprocessor
control. The erase circuit control logic is part of this control loop.
VELOCITY CONTROL
Velocity Sensing
Each motor has a LED lamp focussed on a phototransistor through a
slotted disk on the motor shaft. (Only the activated drive delivers a
tachometer signal.) This optical tachometer output is amplified and
shaped by a comparator to produce a pulse rate proportional to the
shaft speed of the motor. The buffered pulses from the optical tachometer go into an 18-bit shift register. The clock for the shift register
is selected to give a quarter-period delay to the pulses at the desired
shaft speed. The delayed and undelayed pulses are then exclusiveORed to yield a pulse width modulated representation of the actual
velocity. Modulation occurs because the shift-register delay, a fixed'
amount of time, is a different fraction of a period for different
tachometer frequencies. Therefore, the amount of overlap varies
between delayed aand undelayed waves. The overlap is extracted by
the exclUSive-OR gate, averaged to a dc level by a capacitor, and
buffered by an operati9nal amplifier (op amp).
659
TIMER OUT
TEST POINT 2
TEST POINT 1
DIAGNOSTIC LED
DRIVE
0
TEST POINT 3
B155
E3
l..O~BOOT
(7
30 IPS
ERASE ENABLE
GAIN REDUCE
...
SELECT TRACK 0
lil
WRITE ENABLE
III
II
~I
:5
DRIVE
1
a:
....
~
C
01
CD
INTERFACE
PARALLEL
INTERFACE
E 16, 17, 23, 24,
25,31, 32
BUS
Figure 15
Tape Motion Control
TU58
FOWARDI
REVERSE
GATING
,
,,
,0.2 ohm
I
I
•
TACH
SIGNAL
MA·2689
Figure 16
661
Motor Bridge
TUS8
60-+---"""""
VELOCITY
30
T_
MOTOR
CURRENT
SPEED CHANGE
VELOCITY TEST POINT
INTERVAL EXCEEDS
"p REFERENCE TIME;
POWER IS TURNED OFF.
SE
60-+-_
_ E_K....,
30
VELOCITY I - - - - - - t - - - - - - ; i - - - -
-30
-60
REVERSE
MOTOR
CURRENT
DIRECTION
AND VELOCITY CHANGES
Figure 17
STOP
Velocity Change Waveforms
662
TU58
HEAD SELECTION
The read/write heads are selected by signals from the microprocessor. The microprocessor generates a SEL DRV B signal to choose the
head. The gap for track 0 or track 1 is chosen by SEL 0 H from the
microprocessor. The selected head gap Is connected to the read and
write circuitry through a dual 4 to' 1 multiplexing analog switch IC. The
IC's dual circuits are paralleled to minimize series resistance In the low
impendance write driver circuit. The common taps of both heads are
connected together, so only one lead per gap needs to be switched.
WRITE CIRCUIT AND INTERLOCK
The write drivers are two transistors (Q2, Q3) arranged as a constant
current source and sink operating at 7.5 mAo They use tristate buffers
as data-gated switches and return paths. Writing is gate-Interloc.ked
by the mechanical interlock on the cartridge in the drive being selected. Also, the microprocessor tests the mechanical switch for the Write
Permit signal before turning on write current. Attempting to write while
the cartridge Is write-protected results in an error report to the host.
The microprocessor Write Enable signal turns the write current on and
off at the proper times. In the absence of write enabling, the tristate
outputs become open-circuited and source and sink transistors Q2
and Q3 are biased off.
ERASE CIRCUIT
Erase gaps are selected by the same pair of signals that select
read/write gaps. They are also enabled by ERASE ENA L. A 26 mA
current source supplies the erase gaps In common. Current through
the desired gap is passed to ground through a peripheral driver (high
current capacity) gate which is part of a decoder for the control signals. A diode across each erase head winding clamps the Inductive
voltage spike when the erase current is turned off.
DATA ENCODING AND DETECTION
Data is recorded on tape using the ratio encoding method. Each data
bit is given a cell with room for three flux reversals. After an initial
positive transition, only one of the remaining reversal positions Is
used. If the reversal occurs in the first available position, the bit Is a
zero. If it occurs in the second position, the bit is a one. These position
shifts correspond to duty cycles or ratios of 1/3 and 2/3 (Figure 18). To
compensate for waveform distortion in the recording process, the
actual write encoding ratio is 1A to 3/4.
663
TUS8
RECORD
HEAD
CURRENT
I
I
I
I
1
I
I
1
I
I
I
1
I
0
0
I
I
+v~1
RECOVERY
OV
~
-V
Figure 18
I/'...
'J
I
I
I
V'\. ~I
~
Data Encoding and Decoding
The beginning of a bit cell Is defined by a positive peak at the read
amplifier. The second .flux reversal is defined by the next negative
peak. The peaks are detected by a comparator.
The read amplifier output Is fed to one input of the comparator. The
same signal Is phase-shifted and fed to the other output. The output Is
high for a positive slope input and low for a negative slope input. A
small amount of hysteresis Is added to prevent oscillation at the zerosloped-point.
The output of the comparator has a duty cycle similar to that of the
original encoded signal. The data are recovered using an integrater as
shown in Figure 188. The integrater is discharged by an analog switch
on the positive edge of the data waveform. The Integrater is sampled
by a flip-flop on the next edge. If the integrater is positive at sample
time, the recorded bit was one. If the Integrater is negative at sample
time, the bit was zero.
Decoded data is delivered to the serial data input (SID) on the 8085
microprocessor, while a strobe corresponding to the moment of integrater sampling triggers an Interrupt to get the microprocessor to store
the data bit in a register.
664
TU58
MAX CURRENT=
MAX GAIN
MIN RDIDDE
IJ
GAIN REDUCE L
HEAD
@
Figure 19
:>-,--+-----'----OUT
Read Amplifier and Automatic Gain Control
READ AMPLIFIER AND AUTOMATIC GAIN CONTROL
An op amp amplifies the signals coming from the selected head. Automatic gain control (AGC) maintains a constant output to following
. stages In the presence of large variations in output from the tape
because of worn tape or recording variations (Figure 19).
CHARGE PUMP
The principle behind the operation of the charge pump is that of
charge storage in a capacitor. This Is Illustrated by the simplified example in Figure 20. Assume that a capacitor is connected between a
positive charge source, e.g., +12V and ground. Electrons will accumulate at the grounded end. If the capacitor Is disconnected from the
source and ground, It stili has 12V across It, because the electron
charge accumulated may not move. If the original positive end is connected to ground, the 12V extends Its polarity below ground beCause
now there Is an excess of electrons relative to ground. This negative
potential Is available to do work at a rate subject to the charge capacity
of the storage element (capacitor).
665
TU58
+12 VOLTS
1.}
~
12V_
.Too
.L+}
12V_
1+
~
Too
}12V
+12
+12
tTI
b,
Figure 20
Simplified Charge Pump
MARK FINDER
A specially encoded signal is recorded on the DECtape " as part of the
formatting operation. The signal is recorded at one quarter of the
normal bit density and is located at the beginning and end of the tape
(BOT and EOT) and also between each of the formatted records. The
signal is called a mark and indicates the location of the beginning of
each record header. This allows the microprocessor to count the passage of records past the head at winding speed, and alerts the
microprocessor when the tape enters the BOT or EOT regions. Header
marks and BOT-EOT marks are distinguished by different bit patterns.
BOT is all zeros, EOT is all ones, and the header mark alternates ones
and zeros. The mark is detected by a circuit that detects the lower bit
density of the mark compared with normal data. The microprocessor
sets up the timer in the 8155 to provide a clock to the mark finder. The
clock is chosen to allow the MARK H output to be set while the pulse
rate coming, in through the read strobe input is lower than that of the
timer. MARK H appears at an input port that is examined by the markdetecting routine in the microprocessor.
INTERFACES
Serial Interface
Data moves within the TU58 microprocessor on an 8-bit parallel bus.
Data is transferred between the TU58 and the host computer through
a full-duplex asynchronous serial interface that uses one signal loop
666
TU58
. (conductor pair) for each direction. The universal asynchronous receiver /transmitter (UART) performs the parallel to serial and serial to
parallel conversions that make the economy of wire possible. The
UART, a single IC, contains circuitry allowing wired programming of its
conversion format, plus microprocessor bus protocol management,
and the capability to detect conversion and timing errors.
MICROPROCESSOR AND MEMORY
All TU58 activities are supervised or directly controlled by an 8085
microprocessor. The microprocessor operates with firmware stored In
a 2K x 8 read-only memory (ROM). Scratch pad memory for the microprocessor computations, and a 128-byte buffer for data coming
from the host, are located in a 256 x 8 random access memory (RAM).
I/O Ports
The I/O ports provides most of the communication paths between the
microprocessor and the TU58 hardware. Port A provides the Inputs for
the various status signals from the mechanism, such as cartridge present and write permit. Port B delivers control signals to the system,
such as velocity and direction commands. Port C controls the self-test
indicator lamp and causes the Interface to the host to transmit Break
as a part of the boot sequence.
Port C also carries three signals useful for module testing. Test Point 1
(pin 1) pulses high when the header of a sought record is successfully
read (confirmed by the record number complement). Test Point 2 (pin
2) pulses high each time the header of any record Is unsuccessfully
read. Test Point 3 (pin 38) pulses high after a record of data is read but
fails the checksum test.
Registers and Timer
The 8155 registers control the operation of the 110 ports and timer.
The registers are addressed as I/O locations like the ports. The control/status register defines the ports as input or outputs and sets the
timer start and stop characteristics. The timer registers define the
cycle characteristics and load the value required to generate the
desired pulse interval with the system clock at the timer's clock Input.
A 14-bit counter, parallel-loaded by the registers, provides the timer
function.
FIRMWARE
The TU58 operates under control of a microprocessor whose Instructions are stored in a ROM. These instructions, called firmware, define
the functions and capabilities of the TU58 as an integral part of the
667
TU58
normal TU58 operation. No extensive coverage is attempted because
firmware problems cannot be repaired in any direct way. The self-test
checks for proper contents in the ROM and halts the processor if a
fault is detected. The self-test checks other things as well but does not
isolate the problem to a particular component. Field repair Is the replacement of the module.
HOST
TlJ58
POWER·ON RESET (OR ERROR)
INITIALIZE
~ SEND INITS CONTINUOUSLY
..---UNTIL 8REAK IS RECEIVED
RECOGNIZE INIT ~
SEND BREAK
RECEIVE,BREAK
WAIT FOR· INIT
SEND IN IT _ _ _ _ _ _ _
RECEIVE FIRST CHARACTER
AND DISCARD
-
/
RECEIVE CONTINUE
/
SEND MESSAGE PACKET - - - - - . .
FLAG BYTE
RECEIVE SECOND CHARACTER
REINITIALIZE
SEND CONTINUE AND
LOOP IN IDLE
RECEIVE FLAG BYTE
TEST FOR COMMAND OR DATA.
IF COMMAND, STORE MESSAGE
BYTES IN LABELED LOCATIONS.
IF DATA, STORE MESSAGE BYTES
IN DATA BUFFER.
l
PERFORM INSTRUCTIONS. IF
DATA IS COMING FROM HOST,
SEND CONTINUE AS REQUIRED.
MA·2673
Figure 21
Host TU58 Power-Up Interchange
668
VK170-CA
SERIAL VIDEO MODULE
GENERAL
The VK170 module forms an Integral part of a terminal. The module
accepts serial ASCII encoded data to be stored in a refresh memory to
generate a display for a video monitor. The VK170 also accepts parallel data from a keyboard (on strobe demand) to generate serial ASCII
output.
The VK170 is an extended-length, double-height, single-width board.
Mounting holes are provided for stand-off mounting via handle rivets
and two holes located near the module fingers (Figure 2).
FEATURES
• Complete video subassembly on a double-height modlile
• Displays a full 80 characters per line and 25 lines
• 7 X 7 characters displayed in 8 X 8 character cells using standard
installed character ROM
• 8 X 8 character cell allows simple graphics with customer-defined
character set
• Selectable attributes:
blink
half intensity
reverse video
characters, from customer-defined character set
• Customer may enable video attributes on a character-by-character
basis
• I.C. socket for two customer-defined character sets (2716 EPROM
or equivalent)
• Simple EIA RS-423 serial interface for direct interconnect to DLV11J or MXV11, consequently no bus loading
• Jumper-selectable baud rates: 150, 300, 600, 1200, 2400, 4800,
9600,19,200,38,400
• Smooth scroll Is used to move text up the screen to allow entry of
new data on the bottom line of the display
• Drives standard video monitors over coaxial cable per EIA RS 170,
or jumper-selectable for direct drive monitor
669
VK170-CA
• Interfaces to a standard keyboard (8-blt ASCII)
• Can be plugged into LSI-11 backplanes or mounted on stand-offs
applying power via H807 edge connector
SPECIFICATIONS
Height
13.2 cm (S.2 in.)
Length
22.3 cm (8.S in.)
Width
1.27 cm (O.S in.)
Power Requirements
+SV ±S%, 1.2A
+12V (or -1SV)
±3%, .1SA
The VK170 module operates under the following conditions:
• Environment must conform to:
Temperature SoC to 60°C
Humidity 10% to 9S% (no condensation)
• Power dissipation is based on circuit requirements of 1.8 amps
maximum. If only S Vdc is used, power dissipation does not exceed
9 watts. An additional 2 watts (nominal) is dissipated when the ± HV
(nominal 12 volts) is enabled.
DESCRIPTION
The VK170 functions as separate input and output devices. Parallel
data bits from a user-supplied keyboard are serialized and transmitted (XMIT DATA SERIAL ASCII) to a computer serial line interface
(e.g., DLV11-J).
Serial data bits received from a serial line are decoded in the internal
logic to determine whether a received character is a displayable character or a control character (e.g., CA, LF). Displayable characters are
written into an internal memory which Is continuously read to generate
the video signal used to refresh the screen of the customer-supplied
video monitor.
The communications port contains the necessary level converters to
allow the module to communicate with the serial lines in either EIA RS423 or 20mA current loop.
A master crystal clock generates the required timing for the baud
rates for the UART in the communications port and also generates the
horizontal and vertical synchronization signals for the external video
monitor.
670
VK170-CA
The internal charge pump power supply runs on either +12Vor -15V
input. Output from the power supply Is used to power the EIA RS-423
driver for the serial line as well as provide a source of -12V for the
external keyboard.
The cursor and attribute logic. provides control over the Individual
attributes as selected by the wire-wrap jumpers and the control characters as well as relocating the video cursor as required. This logic
also provides internal control over the scroll function, allowing a normal smooth scroll to be replaced by il high-speed jump scroll If the
data Input is faster than the execution time for smooth scroll.
The video Image consists of 25 lines of 80 characters each presented
in adjacent 8 x 8 dot cells (Figure 1).
Horizontal Frequency = 15.36 kHz
Vertical Frequency = 60 Hz
Horizontal scan lines per frame = 256 lines
D,
~
t
D
~~CTER
~~~RS
8 x8
(640 DOTS)
-CHARACTER
UNES, 25 TOTAL
(200 DOTS)
MK-CI678
Figure 1
Video Image
Smooth scrolling rolls a clear line Into the bottom of the Image display.
It Is used whenever an attempt Is made to move the cursor down with a
line feed (IF) or a vertical tab (VT) after the cursor has reached the
bottom line.
Direct cursor addressing Is available (VT52 compatible).
Character attributes allow selection of blink, forward and reverse
video, alternate character set, or half Intensity. The selected attribute
may be set or cleared with bit 8 of the received data or with ASCII
character SOISI (Shift OutlShlft In).
The cursor Is a flashing reversed video cell with a 500 millisecond
nominal period and a reversed duty of 60% to 80%.
671
VK170-CA
r---------------------------------------""M71:i2'
I
CLK
l
BAUD RATE SEL
I
CNTR'L
l _______ ,
I
RCV DATA
I
..;QMMUNI·
CATION
PORT
~
~
EXTERNAL
MONITOR
-HV
+HV
Figure 2
Port Interaction
.18Typ
HOLES ARE .125d
7.44 :1:.01
M7142
8.43 :!;.01
141·---5.187.......=.~-----I11
Figure 3
Mechanical Packaging
672
VK170-CA
CONFIGURATION
Interface
This section describes the sequences of signal exchanges that occur
among the VK170 and other external devices. Figure 4 shows the pin
number locations of the Interfacing connectors.
J3
+
J 1
J2
+
+
MK-0689
Figure 4
Connector Pin Number Location Diagram
KeyboardNK170 Interface
The keyboard Interfaces to the VK170 via a 20-pln connector (J2). The
DIGITAL mating connector is the H8561. Table 1 presents the connector pin numbers and associated signal names.
Table 1
PlnNo.
1
2
3
4
5
6
7
8
9
10
KeyboardNK170 Connector (J2)
Signal Name
+5 Volts
-12 Volts
GND
KB8
KB7
GND
KB6
KBSTRBH
KB5
BREAK
PlnNo.
11
12
13
14
15
16
17
18
19
20
Signal Name
KB4
Not used
KB3
BREAK (GND)
KB2
GND
KB1 (LSB)
GND
Not Used
Not Used
Edge Connector
VK170 edge connector pins and associated signals are presented In
Table 2.
673
VK170-CA
Table 2
Pin No.
AA2,BA2
AC2,AT1,BC2,BT1
AB2
AD2
Others
VK170 Edge Connector
Signal Name
+5Vdc
GND
-15 Volts
+12 Volts
Not Connected
Video Output Connector
Video output is provided as RS170 compatible and as separate TTL
output lines. A 5-pin MOLEX* connector (J1) is used with pin assignments as shown in Table 3. (Mating connector = H8562.)
Composite video output provides RS170 output generated by combining the video signal with a composite sync signal. The picture from the
balancing level to reference white across 75 ohms is 1 volt. The synchronizing levels are imposed at 40% of the signal.
* Vendor Trademark
Table 3
Pin No.
1
2
3
4
5
Video Output Connector (J1)
Signal Name
HORIZONTAL DRIVE H
VERTICAL DRIVE L
VIDEOHIZ
GND
RS170VIDEO
Tlmlng/Freq
15.36 kHz/27 p,S
60 Hz/520 p,s
o volts =
SYNC
0.4 volts = BLACK
1.4 volts = WHITE
For direct drive output, jumper W4 must be cut, providing a high
impedance source at the MOLEX* connector, pin 3. The VK170 has
been tested with the following direct drive monitors:
.ITOH
• Ball Brothers
• Elston
Communications Port Connector
The communications port Is a 10-pln connector (J3), pinned for direct
DLV11-J connection. The electrical Interface may be wired for RS-423
674
VK170-CA
or 20 mA communication (see Figure 5). The DIGITAL mating
connector is Ha560. Table 4 presents the pin assignments and associated signal names.
Figure 5
Select RS-423/20 mA Loop
• Vendor Trademark
Table 4
Communications Port Connector (J3)
Pin No.
Signal Name
1
CLOCK 110
2
GND
3
XMITDATA
4
XMITDATA-
5
GND
+
6
NOT USED/POLARIZING POINT
7
RCVDATA -
a
RCVDATA
9
GND
10
20mASOURCE
+
Installation Procedures
The following sections describe the installation of the VK170 module.
Jumper Configurations
Figure 6 illustrates the location of the various jumpers and wire wrap
posts of the VK170. Verify that the factory-Installed jumpers are configured per Table 5. Any jumper configuration changes required for
user applications should be made at this time.
675
VK170-CA
Data Rate Selection
The data rates are generated via a 13.5168 MHz crystal and selected
through a dual 4-bit decade and binary counter. The follQwlng data
rates are selectable: 150, 300, 600, 1200, 2400, 4800, 9600, 19,200,
and 38,400 bits per second.
The UART may be configured to transmit and receive at either the
same data rate or at split data rates. Data rates are configured by
connecting a jumper from the selected data rate wire-wrap pin to the
clock input pln(s) of the UART. When configuring at the same data
rate, the wire-wrap pins may be daisy-chained. Table 6 lists the data
rates and their respective pin numbers.
The UART can be configured to operate from an external clock source
via pin 1 of J3. Both UA26 and UA27 must be jumpered to the external
clock. Do not select a data rate pin when using an external clock.
RECEIVE
LEVEL
:11
REMOVE TO
REVERSE VIDEO
\
Q
COMPOSITE VIDEO
..L.
RECEIVE LEVEL
UAS-,
\
III· ~~~~,~~",,,
~::;~
)..,
~::~
d~···
UA41---1
UA42
UA43
E52 CHARACTER
SET SELECT
l
ATTRIBUTE
CON,ROL
~
.n
UAlBJm
UA40~
UAl
9
INITIALIZE FUNCTION
UAl
UA6
M7142 ETCH REV B
POWER PUMP
VOLTAGE SELECT
UAl j
uA5
UA4
Figure 6
Jumper and Wire Wrap Post Locations
676
VK170-CA
Table 5
Factory Installed Jumper Configurations
Jumper
Function Implemented
W1 (or UA 1 to UA5)
+ 12V operation
W2 (or UA4 to UA6)
W4
RS 170 operation
Form feed receive enabled for remote Initialization
W7
8-bit-no parity
UA59 to UA61 to UA62
UA18to UA20
EIA RS-423 operation
UA21 to UA23
UA34 to UA32
UA36 to UA37
E52 character set enabled
W3
SI/SO (Shift In/Shift Out) attribute control
UA39 to UA40
Forward video
W5
UA41 to UA43
Blink attribute enabled
UA26 to UA27 to UA 15
9600 data rate selected
Table 6
FROM
Transmit clock
pin UA27
and/or
Receiver clock
pin UA26
Data Rate Jumper Configurations
TO
Pin
UA9
UA10
UA11
UA12
UA13
UA14
UA15
UA16
UA17
Data Rate
150
300
600
1200
2400
4800
9600
19200
38400
Attributes and Attribute Control Selection
Several jumpers are used for attribute and attribute control selection.
Table 7 lists the various attribute and attribute control configurations.
677
VK170-CA
Communications Selection
Four jumpers are used for communications selection. Table 8 lists the
jumper configurations required for either EIA RS-423 or 20 mA current
loop communications.
Table 7
Attribute Jumper Configurations
Jumper
Characteristic
W3
Install to enable character ROM E52
Remove to enable character ROM XE53
W5
Install for forward video
Remove for reverse video
UA7 to UA8
Install to disable half intensity
UA41 to UA42
Install to select reverse attribute
UA41 to UA43
Install to select blink attribute
UA40· to UA38
Install to select character bit 8 for attribute
control
UA40· to UA39
Install to select 51/50 for attribute control
UA40 can either be jumpered to UA38 or UA39. but not both at the same
time.
Table 8
Communications Jumper Configurations
TO
FROM
UA18
UA21
UA34
UA36
RS423
UA20
UA23
UA32
UA37
20mA
UA19
UA22
UA33
UA35
Parity Selection
As many as three jumpers can be used to select ASCII serial data
format. Table 9 lists the jumper configurations required to select either
odd, even, or no parity.
Voltage Selection
As many as six jumpers (two are optional) can be used for voltage
selection. Table 10 lists the jumper configurations required for either
+12 Volt or -15 Volt operation.
678
VK170-CA
Table 9
Parity Jumper Configuration
Characteristic
Jumper
No Parity (8 data bits)
UA59 to UA61 to UA62
Odd Parity (7 data bits)
UA60 to UA61 to UA62 to UA63
Even Parity (7 data
bits)
UA60 to UA61 to UA62 and UA59 to UA60
Table 10
Voltage Jumper Configurations
Jumper
W1 (or UA 1 to UA5)
W2 (or UA4 to UA6)
UA3toUA5
UA1 to UA6
+12V
-15V
In
In
Out
Out
Out
Out
In
In
Remote Initialize Selection
As many as three jumpers are used for remote Initialize selection.
Table 11 lists the jumper configuration required for remote Initialization.
Table 11
Remote Initialize Jumper Configurations
Characteristic
Form Feed Receive
Break
None
Form Feed or Break
W6
Out
In
Out
In
W7
In
Out
Out
In
we
Out
In
In
Out
Module Mounting
The VK170 module Is mounted by one of two methods.
1. The module can be mounted In a DIGITAL computer backplane,
taking care that aU signals (e.g., grant lines) are Jumpered on the
backplane as required.
2. The module can be mounted on a panel or chassis using nylon
hardware (i.e., spacers and #2-56 screws and nuts as required),
using the mounting holes In the module.
The H807 edge connector Is available to provide p6wer connection to the VK170 when used In this mounting configuration.
679
VK170-CA
Checkout Procedures
Two checkout methods are available to the user:
1. When the VK170 Is used on a PDP-11 system, run the diagnostic
CZVTO In accordance with the Instructions distributed with the
diagnostic.
2. To check out the VK170 without a processor, local testing can be
done over the RS-423 or 20 rnA communication lines.
If the VK170 is configured for RS-423 operation, Jumper J3-3
(XMIT DATA +) to J3-8 (RCV DATA +) to provide local testing
with a user-supplied display monitor and keyboard.
If the VK170 Is configured for 20 rnA current loop (passive), local
testing Is provided by the following three Jumpers:
. J3-1 0 (+ Voltage) to J3-3 (XMIT DATA +)
J3-4 (XMIT DATA -) to J3-7 (RCV DATA +)
J3-8 (RCV DATA -) to J3-9 (GND)
Once these three jumpers are Installed, a user-supplied keyboard
and display monitor can be used to check the operation of the
module.
PROGRAMMING
Control/Function Characters
The control/function characters are Interpreted as non-graphic data.
The following actions occur at the terminal upon receipt of these characters from the communication port:
• as (backspace)-the cursor moves one position to the left, If It Is n9t
currently In It leftmost position (left margin).
• HT (horizontal tab)-the cursor moves one position to the right, If It
Is not currently In Its rightmost position (right margin).
• FF (form feed)-the module Is relnltlallzed If the remote-Initialize
form-feed jumper Is Installed (34 ms of no transmission fill-time
required).
• CR (carriage return)-the cursor moves to the left margin.
• LF (line feed)-the cursor moves down one line If not In scroll mode.
(Scroll mode Is entered when the cursor enters the bottom line,
scroll mode Is exited by an Initialize operation.) If required, a smooth
scroll occurs and a clear line Is provided. If a scroll operation occurs
at data rates above 19,200, 512 microseconds are required before
another scroll can be requested.
680
VK170-CA
• VT (vertical tab)-the cursor moves as In a line feed, except the next
line is not cleared. If a scroll operation occurs at data rates above
19,200,512 microseconds are required before another scroll can be
requested.
• BREAK (spacing condltion)-an Initialize sequence similar to
power-up initialization Is generated If remote Initialize BREAK jumpers are installed (34 ms of no transmission fill-time required).
Cursor Addressing
Direct cursor addressing allows movement to any position on the
screen by transmitting an escape sequence to the module.
The ESC character followed by the Y character sets up the logic for a
new "Cursor location: e.g.,
<.Y>
• = Defines cursor addressing function
• = one character
040 = top line (ASCII space)
041 = second line (ASCII !)
070 = bottom line (ASCII 8)
• = one character
040 = leftmost column (ASCII space)
157 = rightmost column (ASCII 0)
The cursor is moved to the specified column of the specified line. For
example, the sequence <» places the cursor on
the tenth line (because ASCII <» is 51 8 ) and in the thirty-fourth column (because ASCII is 101 8 ; and -408 for the offset results in
octal column 41). The initial sequence should be preceded by a 'form
feed (FF) to initialize the screen registers, if a scroll has been performed.
Optlonal,Character Set Selection
Selection of the optional character ROM is accomplished via the removal of jumper W3. An optional character-generator socket is provided on the VK170.
681
VK170-CA
Data Formats
The data mode for ASCII serial input is eight-level without parity. In
this case, the lower order bits represent the appropriate character with
bit 8 as the attribute select blLlf bit 8 is set, the selected attribute is
enabled for the character received.
For the 7 bits with odd or even parity mode, SI/SO can be used to
select the attribute bits. When enabled, all characters received after
SO have the attribute selected. All characters received after SI have
the attribute deselected. The implemented ASCII 7-bit character set is
shown in Figure 7.
Attributes
Selection of the various attributes is controlled by setting ASCII bit 8 to
a logical one (1) or manipulation of SI/SO and adding/deleting wirewrap jumpers on the VK170 module (see Figure 8).
This section contains a description of each attribute, Instructions for
implementation, and illustrations of each attribute as it appears on the
screen.
Reverse Video Versus Forward Video
The forward video display on the CRT consists of white characters on
a black background. To change the entire display to reverse video,
(black characters on a white background), jumper W5 must be
removed as shown in Figure 9.
Reverse Video Attribute
The reverse video attribute reverses the video on a character-by-character basis. Wire-wrap UA41 to UA42 must be installed for the reverse
video function. (Refer to Figure 9.)
~~".~
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1
1 0 0
1 o 0
1 10
1 0 1
1 1 o
1 1 0
1 1 1
1 1 1
0
1
1
0
0
1
0
1
1
1
6
7
3
4
0
@
P
1
2
A
B
Q
R
a
3
4
5
C
5
c
0
T
d
U
e
V
W
X
y
I
v
D
W
11
I
x
1
/I
S
%
5
6
Figure 7
~
as
HT
LF
VT
6
E
F
7
G
8
9
H
I
J
:
ESC
FF
+
CR
SO
51
I
5
1
1
0
!
7
1
0
1
1
1
2
10
11
12
13
14
16
16
17
1
0
1
5P
-
1
0
0
1
0
0
1
2
3
4
0
1
0
0
0
0
t,tttROwt
0
0
0
0
0
0
0
0
0
Z
K
=
L
M
?
0
N
\
~
-
ASCII Character Set
682
D
b
Q
r
s
u
y
z
k
1
I
m
n
...
0
t
VK170-CA
RBRB H~
+5V
UA3B.:.U_A4_0____ RATRIB H
so
STRB L
RRD H
a
INIT L
51 STRB L--~
MK-2386
Figure 8
Attribute Selection Flow
SHIFT LOAD} FUP.FLOP
VIDEO HOLD
+5V
+5V
JUMPER MUST BE REMOVED
FOR FULL SCREEN REVERSE
VIDEO FUNCTION
=
WW PINS UA41 TO UA42 (FOR REVERSE VIDEO)
WW = PINS UA41 TO UA43 (FOR BUNK)
MK-0694
Figure 9
Reverse Video and Blink Attributes
683
VK170-CA
Blink Attribute
A wire-wrap must be Installed as shown In Figure 9 to Implement the
blink attribute.
Half Intensity
The wire-wrap shown In Figure 10 must be removed to enable the half
Intensity attribute.
47K.I\o
-~---+5V
VIDEO DATA L
~
UA8
1
2
74LS
08
AnRIB H '--_--'
REMOVE FOR HALF
INTENSITY FUNCTION
MK.Q677
Figure 10
Half Intensity Wire-Wrap Removal
684
W9500
W9500 HIGH-DENSITY WIRE-WRAPPABLE MODULES
GENERAL
The W9500 series of high-density wire wrappable modules enable a
user to easily configure special interface logic for the LSI-11 Microcomputer systems. These modules consist of DIGITAL's standard
double and quad height sizes and are available with or without premounted Dual-In-Llne Packages (DIP) low-profile sockets.
SPECIFICATIONS
W9511 Quad-Height Without Sockets
Height
Quad, 10.5 in. (26.6cm)
Length
Extended, 8.9 In. (22.8cm)
Width
Single, 0.5 in. (1.27cm)
Vcc Pins
AA2, BA2, CA2, DA2
GND Pins
AT1, BT1, CT1, DT1, AC2, BC2,
CC2, DC2
W9512 Double-Height Without Sockets
Height
Double, 5.2 in. (13.2cm)
Length
Extended, 8.9 in. (22.8cm)
Width
Single, 0.5 in. (1.27cm)
Vcc Pins
AA2, BA2
GND Pins
AT1, BT1, AC2, BC2
685
W9500
:II
a
~
a
DDDDDD
0 0 0 0 0 r--)
~ 1-
r
DDDDD~:!I:
DO DDD
o 0 0 0 0
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CE."..
686
I
W9500
0
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0
~
0
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03 IN CENTERS
~
~
~
r---'
03 IN CENTERS
~
'-
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~
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03 IN CENTERS
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03 IN CENTERS
n
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03 IN CENTERS
~
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UJ
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2
n
03 IN CENTERS
1/1
0
0
0
0
z
1/1
~
~
~
~
'"
0
~
'3
~
:D
03 IN CENTERS
~
"C
0
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~
~
~
03 IN CENTERS
CD
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l>
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CENTERS 0
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0
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CENTERS
0.3,0.4, & 0.6 IN. CENTERS
687
CIl
~
W9500
DESC.AIPTION
The LSI-11 compatible series consists of four modules: quad-height
with and without premounted sockets and a double height with and
without premounted sockets.
a
Table 1 provides a brief summary of each type. All modules are single-width; the height of each pin Is 5/16In.
Each module without premounted sockets is configured to accept IC
packages with pin centers on 0.3 In. (7.62cm); 0.4 In. (10.16cm); and
0.6 in. (15.24cm). The IC package density for these modules Is shown
in the drawings in this data sheet. Each module can be wrapped by
standard automatic wrapping techniques as well as by hand.
Those modules with premounted sockets accept 16-pln IC's with 0.3
in. centers. Space is provided between the sockets for decoupllng
capacitors or other discrete components as required by the user. In
addition, these modules supplied with sockets also contain universal
areas that will accept IC's with pin centers of 0.3 In. (7.62cm); 0.4 In.
(10.16cm); and 0.6 in. (15.24cm). The accompanying photos and
drawings point out these universal areas and their capacities.
The printed circuit on each board connects the appropriate edge connector pins to the Vcc plane on side 2 of the board and the ground
plane (GND) on side 1 (component side). The remaining edge connector pins terminate to a double row of wire wrap pins for user designated functions. Each of the modules also Includes a 40-pln male cable
connector to allow an Interface cable to be attached to the module
logic. The pins of the cable connector are also terminated to a double
row of wire wrap pins. The quad height modules are also provided with
a space where an additional 40-pln cable connector (labeled J2) can
be inserted by the user. When a connector Is not required, additional
Ie packages with .3, .4, and .6 in. centers can be installed in the space
reserved for the connector. Each board contains Insulated standoffs to
maintain the required clearance between adjacent modules and prevent shorting of wire wrap pins. A helpful alphanumeric X-V grid
pattern is also etched onto each board to facilitate ease In wire wrap
pin location and identification.
688
W9500
Table 1
W9500 Series Modules
Module No.
Description
W9511
Quad height, extended length, single width module
with extractor handle. No DIP sockets Included. One
40-pin male cable connector premounted on board
and space for additlonal40-pin connector provided.
W9514
Same as W9511 except with 58 premounted DIP
sockets.
W9512
Dlouble height, extended length, single width module
with flip chip handle. No DIP sockets Included. One
40-pln male cable connector premounted on board.
W9515
Same as W9512 except with 25 premounted DIP
sockets.
689
APPENDIX A
ASSIGNMENT OF ADDRESSES
AND VECTORS
ADDRESS MAP
2K
WORDS
FIXED ADDRESS AREA
RESERVED FOR USE BY
DIGITAL EQUIPMENT
CORPORATION
777 777
770000
lK
WORDS
t
767777
USER ADDRESSES AREA
764000
lK
WORDS
t
763777
FLOATING ADDRESSES AREA
RESERVED FOR USE BY
DIGITAL EQUIP CORP
760010
760006
760000
757777
001000
80
VECTORS
48
VECTORS
t
000 777
FLOATING VECTOR AREA
000 300
TRAP & INTERRUPT
VECTOR AREA
000277
000000
FLOATING VECTORS
The conventions for the assignments of floating vectors for modules
on the LSI-11 bus will adhere to those established for UNIBUS devices. UNIBUS devices are used to explain the priority ranking for
floating vectors and are included in the subsequent table of trap and
interrupt vectors as a guide to the user.
The floating vector convention used for communications and for devices that interface with the PDP-11 series of products assigns vectors
sequentially starting at 300 and proceeding upward to 777. (Some LSI11 bus modules, such as the DL V11 and DRV11, have an upper vector
limit of 377). The following table shows the sequence for assigning
vectors to modules. It can be seen that the first vector address, 300, is
690
APPENDIX A
assigned to the first DL V11 in the system. If another DLV11 is used, it
would then be ass~gned vector address 310, etc. When the vector
addresses have been assigned to all the DLV11 s (up to a maximum of
32), addresses are then assigned consecutively to each unit of the next
highest ranked device (DRV11 or DLV11-E, etc.), then to the other
devices according to their rank.
Ranking for Floating Vectors
(Start at 300 and proceed upward.)
Rank
UNIBUS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DC11
KL 11, DL 11-A, -B
DP11
DM11-A
DN11
DM11-BB
DR11-A
DR11-C
PA611 Reader
PA611 Punch
DT11
DX11
Dl11-C, -D,-E
DJ11
DIH11
GT40
LPS11
DIQ11
KW11-W
DU11
LSI·11 Bus
DLVj1, -F,-J
DRV11-B
DRV11
DLV11-E
KWV11
DUV11
INTERRUPT AND TRAP VECTORS
Vector
UNIBUS
LSI·11 Bus
000
004
DEC reserved
CPU errors
DEC reserved
Bus time-out and illegal instructions (e.g., JMP RO)
(odd address and stack
overflow traps not
691
APPENDIX A
INTERRUPT AND TRAP VECTORS (Cont)
Vector
010
014
020
024
030
034
040
044
050
054
060
064
070
074
100
104
110
114
120
124
130
134
140
144
150
154
160
164
170
174
200
204
~
LSI-11 Bus
UNIBUS
implemented on LSI-11)
Illegal and reserved
Illegal and reserved
instructions
instructions
BPT, breakpoint trap
BPT Instruction and T bit
lOT, input/output trap
lOT instruction
Power-fail
Power-fail
EMT, emulator trap
EMT Instruction
TRAP instruction
TRAP instruction
System software
System software
System software
System software
Console terminal,
Console terminal, input
keyboard/reader
Console terminal,
Console terminal, output
printer /punch
PC 11, paper tape reader
PC11, paper tape punch
KW11-L, line clock
External event line interrupt
KW11-P, programmable clock
Memory system errors
XV plotter
DR11-8 DMA Interface;
(DA11-B)
AD01, A/D subsystem
AFC11, analog subsystem
AA 11, display
AA11,lightpen
RL11
DRV11-8
RLV11
User reserved
User reserved
LP11/LS 11, line printer;
LAV11, LPV11
LA180
RS04/RF11, fixed head disk
692
APPENDIX A
INTERRUPT AND TRAP VECTORS (Cont)
Vector
210
214
220
224
230
234
240
244
250
254
260
264
270
274
300
UNIBUS
LSI-11 Bus
RC11, disk
TC 11, DECtape
RKV11
RK11, disk
TU 16/TM 11 ITS03, magnetic
tape
CD11-CM11-CR11, card
reader
UDC11, digital control
subsystem
PIRQ, program interrupt
request (11/45)
Floating-point error
FIS (optional)
Memory management
RP04/RP11 disk pack
TA 11, cassette
RX11, floppy disk
RXV11. RXV21
.
User reserved
User reserved
}
User reserved
(Start of floating vectors)
,~
374
400
404
410
414
420
424
430
434
440
444
}
ADV11-A
}
IBV11-A
}
KWV11-A
}
User reserved
450
777
(End of floating vectors)
693
APPENDIX A
FLOATING ADDRESSES
The conventions for the assignment of floating addresses for modules
on the LSI-11 bus are the same as UNIBUS devices. UNIBUS devices
are used to explain the ranking sequence.
The floating address convention used for communications and for
other devices that interface with the POP-11 series of products assigns
addresses sequentially starting at 760010 (or 160010) and proceeds
upward to 763 776 (or 163776). For compatiblity with UNIBUS convention, addresses are expressed as consisting of 18 bits (7XX XXX) rather than 16 bits (1XX XXX).
Floating addresses are assigned in the following sequence:
Rank
UNIBUS
Device
1
2
3
4
5
6
7
8
OJ11
OH11
0011
OU11
OUP11
LK11A
OMC11
OZ11
9
KMC11
10
LSI·11
Device
OUV11
OZV11
RLV11 (extras)
RL 11 (extras)
DEVICE ADDRESSES
LSI-11 Bus
Address
UNIBUS
777776
777774
777772
777770
Processor status word (PS)
Stack limit
Program interrupt request (PIRO)
777720
}
DIGITAL reserved
694
APPENDIX A
DEVICE ADDRESSES (Cont.)
Address
777716
777710
777707
777706
777705
777704
777703
777702
777701
777700
777676
777600
777576
777574
777572
777570
777566
777564
777562
777560
}
CPU Registers
R7 (PC)
R6 (SP)
R5
R4
R3
R2
R1
RO
}
}
(SR2)
Memory mgt status register (SR1)
(SRO)
Console switch and display register
~~~~~~}
}
777544
}
General
Registers
Memory management
(RBUF)
(RCSR)
777556
777554
777552
777550
777546
777530
777526
LSI-11 Bus
UNIBUS
Console
Terminal
}
Console
Terminal
PC11/PR11
KW11-L, DL 11-W
XV11
Unassigned
695
(LTC) KPV11
BDV11
APPENDIX A
DEVICE ADDRESSES (Cont.)
Address
777524
777522
777520
777516
777514
777512
777510
777506
777500
777476
777460
777456
777440
777436
777434
777432
777430
777426
777424
777422
777420
777416
777400
}
}
}
}
}
UNIBUS
LSI-11 Bus
Unassigned
BDV11
LA180, LP11
LS11, LV11
}
LAVll. LPVll
}
RKV11
TA11
RF11
RC11
#8
"'III
~
DT11, bus switch
~
}
RK11
696
#7
#6
#5
#4
#3
#2
#1
· APPENDIX A
DEVICE ADDRESSES (Cont.)
Address
777376
777360
777356
777340
777336
}
}
}
777320
777316 1""-1
777314
777312
777310
~
777306
777304
777302
777300 I'"
777276
777200
777176
777174
717172
777170
777166
777164
777162
.777160
LSI-11 Bus
UNIBUS
}
DC14-D
TC11
KE11-A, EAE #2
KE11-A, EAE #1
arithmetic shift
logical shift
normalize
step count/status register
multiply
multiplier quotient
accumulator
divide
DIGITAL reserved
1- -:~~------------
}
CR11, CM11,
CD11
697
}
RXV11
RXV11,RXV21
APPENDIX A
DEVICE ADDRESSES (Cont.)
777156
777000
776776
776770
776766
776750
776746
776740
776736
776700
776676
177530
177526
177524
177522
177520
177516
177514
177512
177510
LSI-11 Bus
UNIBUS
Address
}
DIGITAL reserved
~
AD01
}
AA11#1
}
}
}}
}
Unassigned
RP11
--- - - ---1---------
I
DL 11-A,-8
#4-#16
This area
reserved for 16
serial line units
without modem
control capability
DL 11-A,-8, #3
DL 11-A,-B #2
+
698
APPENDIX A
DEVICE ADDRESSES (Cont.)
Address
177506
177504
177502
177500
776476
776400
776376
776200
776176
775660
775656
775654
775652
775650
775646
775644
775642
775640
775636
775634
775632
775630
775626
776624
775622
775620
LSI-11 Bus
UNIBUS
1
DL 11-A,-B, #1
-------
}
}
}
#5
AA11
#2
DX11
#6-#31
}
}
}
#4
}
#2
#5
DL 11-C,-D,-E
#3
699
This area
reserved for 31
serial line units
with modem
control capability
APPENDIX A
DEVICE ADDRESSES (Cont:>
775616
775614
775612
775610
775606
775604
775602
775600
776576
775400
775376
775200
775176
775000
774776
774410
774406
774404
774402
774400
774376
774000
LSI·11 Bus
UNIBUS
Address
}
#1
-- --
}
}
}
}
}
I
------- - -
I
---~
DIGITAL reserved
#4
0811
#1
#16
DN11
#1
#15
DM11
#1
#1
DP11
}
DP11
RL01
}
DC11
#32
#32
#1
700
}RLVll
APPENDIX A
DEVICE ADDRESSES (Cont.)
Address
UNIBUS
LSI·11 Bus
,
773776 }
Maintenance loader
773700
773676
M792 diode ROM
773400
773376
773300
}
}
}
BM792-VH cassette
•
~-------
773276
773200
773176
773100
r-
BM792-VCcard
I
MR11-DB
BM792-VB
dl~k/DECtape
REV11, BDV11
MRV11-AA
256-word ROM
space
-----------
-
773076
BM792-VA paper tape
773000
•
...
-
-
-
-
-
-
-
701
-
-
--I-
-
-
-
--
APPENDIX A
DEVICE ADDRESSES (Cant.)
772776
772700
772676
772600
772576
772574
772572
772570
772566
772560
772556
772550
772546
772544
772542
772540
772536
772534
772532
772530
772526
772524
772522
772520
LSI·11 Bus
UNIBUS
Address
}
}
}
PA611 typeset pu nch
PA611 typeset reader
AFC11
}
DIGITAL {eserved
}
DIGITAL reserved
}
I
KW11·P
...
~
TM11
I"';
702
APPENDIX A
DEVICE ADDRESSES (Cont.)
LSI-11 Bus
Address
UNIBUS
772516
772514
Memory mgt status register (SR3)
772500
772456
772450
772446
772440
772436
772434772432
772430
772426
772424
772.422
772420
772416
772414
772412
772410
772406
772400
772376
772200
}
}
}
}
}
}
}
}
OST
DR11-B, #3
TJU16
DR11-B, #2
DIGITAL reserved
DR11-B,-C, #1
KW11-W
Memory management
703
}
DRV11-B.#3
}
DRV11-B. #2
}
DRV11-B.#1
APPENDIX A
DEVICE ADDRESSES (Cont.)
772176
772160
772156
772140
772136
772110
772106
772102
772100
772076
772070
772066
772040
772036
772020
LSI-11 Bus
UNIBUS
Address
}
}
}
}
}
}
}
FP11
Unassigned
Memory parity
Unassigned
MS11-K, -LP, MM11-LP
RL 11
RJS04
DIGIT AL reserved
704
APPENDIX A
DEVICE ADDRESSES (Cont.)
Address
772016
772000
771776
771000
770776
770700
770676
770500
770476
770460
770456
LSI·11 Bus
UNIBUS
}
GT40, VT48
J
}
}
}
}
770450
770446
770444
770442 }
770440
770436
UDC functional 110 modules
#8
KG11
#1
#16
DM11·BB
#1
ADF11
Unassigned
}
lPSll
705
AAVll-A
APPENDIX A
DEVICE ADDRESSES (Cont.)
LSI-11 Bus
UNIBUS
Address
LPS11
770424
770422
770420
770416
}
KWVll-A
}
ADVll-A
AR11, LPS11
770404
770402
770400
770376
DIGITAL reserved
770000
767776
767774
767772
767770
767766
767764
767762
767760
- 767756
767754
767752
767750
767746
776000
}
}
}
}
DR11-C, #1
DRV11, #1
DR11-C, #2
}
DRVll.#2
DR11-C,#3
}
DRVll. #3
User
Reserved
Area
t
706
User
Reserved
Area
,
APPENDIX A
DEVICE ADDRESSES (Cont.)
765776
765000
764776
LSI-11 Bus
UNIBUS
Address
}
}
REV11 256-word
ROM space
,
764000
763776
(start here and assign upwards to 767 776)
if
--------1----(IOPff floallng addresses)
760154
760152
760150
760146
I
Floating
Addresses
760 010
·
}
IBV11-A
A:~:~:~
(start here and assign upwards 10 763776)
~
760006 }
-
- -
-
- - -
DIGITAL reserved
}
- -
-
DIGITAL
reserved
760000
707
-
I
- - -
--
APPENDIX B
LSI-11 BUS SIGNALS
MODULE CONTACT FINGER DESIGNATION
DIGITAL interface modules all use the same contact finger (pin) identification system. The LSI-11 I/O bus is based on the use of doubleheight modules. These modules plug into a 2-slot bus connector, each
containing 36 lines per slot (18 each on component and solder sides of
the circuit board). Although the LSI-11 processor module and core
memory modules are quad-height modules that plug into four connector slots, only two slots (A and 8) are used for interface purposes on
the processor module. Etched circuit jumpers on the unused portion
of the module maintain continuity of grant signals BIAKI L to BIAKO L
and BDMGI L to BDMGO L. These daisy-chained signals are described later.
Slots, shown as Row A and Row B in Figure 1, Include a numeric
identifier for the side of the module. The component side Is designated
side 111" and the solder side is designated side 112." Letters ranging
from A through V (excluding G, I, 0, Q) identify a particular pin on a
side of a slot. Hence, a typical pin is designated as:
BE2
Slot (Row)
Identifier
"SlotB"
Module-Side Identifier
IIsolder side"
Pin Identifier
IIPin E"
Note that the positioning notch between the two rows of pins mates
with a protrusion on the connector block- for correct module position-"
Ing.
Quad-height modules are similarly pin numbered. They are identified
in Figure 2.
Individual connector pins, viewed from the underside (wiring side) of a
backplane, are identified as shown in Figure 3. Only the pins for one
bus location (two slots) are shown in detail. This pattern of pins is
repeated eight times on the H9270 backplane, allowing the user to
install one LSJ-11 microcomputer module (four slots) and up to six
additional 2-slot modules.
708
APPENDIXB
ROW A
ROW B
~8V1
Figure i
(
PIN 8V2
. Dual Moduie (;ontact finger identltlcatlon
~N
AAI
ROIl A
AYI
"-.I
:"l
BAI
ROW I
~I
'I
CAl
Rowe
CYI
'-J
'I
DAI
_D
1M
Figure 2
Quad Module Contact Finger Identification
709
APPENDIXB
H9270 POWER AND
SIGNAL CONNECTIONS
ROW IDENTIFIER
TYPICAL MODULE
LOCATION
(SLOTS AI-BI I
MODULE SIDE IDENTIFIER
I • COMPONENT SIDE
2· SOLDER SIDE
WIRE-WRAP PINS
PASS THROUGH
H9270 PC BOARD
t
I
I MODULE SIDE
~~~~~-F~~~~~
Figure 3
!
LSI-11 Backplane Module Pin Identification
BUS SIGNALS
H9270 backplane pin assignments are listed and described in Table 1.
Only slots A and B are listed. However, they are identical to slots C and
o respectively. Table 2 alphanumerically lists the LSI-11 bus pin
assignments.
Table 1
Backplane Pin Assignments
Bus
Pins
Mnemonic
Description
AA1
AB1
BIR05 L
BIR06 L
I nterrupt Request
priority level 5
Interrupt Request
priority level 6
AC1
AD1
BDAL16
BDAL17
Extended address bits.
AE1
AF1
AH1
SSPARE1
SSPARE2
SSPARE3
Special Spare (not assigned,
not bused; available for user
interconnections).
AJ1
GND
Ground-system signal
ground and dc return.
AK1
AL1
MSPAREA
MSPAREA
Maintenance Spare-normally
connected together on the
backplane at each option location (not bussed connection).
710
APPENDIX B
AM1
GNO
AN1
SOMRL
AP1
SHALT L
Processor Halt-when SHALT
Lis asserted,the processor responds by halting normal program execution. External
interrupts are ignored but
memory refresh interrupts
(enabled If W4 on the processor module is removed) and
OMA request/grant sequences are enabled. When in
the halt state, the processor
executes the OOT microcode
and the console device operation is Invoked.
AR1
SREFL
Memory Refresh-asserted by
a processor microcode-generated refresh Interrupt sequence (when enabled) or by
an external device. This signal
forces all dynamic MOS memory units to be activated for
each SSYNC LIS DIN L bus
transaction.
Ground-system signal
ground and dc return.
Direct Memory Access (OMA)
Request-a device asserts this
signal to request bus mastership. The processor arbitrates
bus mastership between itself
and all OMA devices on the
bus. If the processor is not the
bus master (it has completed a
bus cycle and BSYNC L is not
being asser.~ j by the processor), it grants bus mastership
to the requesting device by asserting SOMGO L. The device
responds by negating SOMR L
and asserting BSACK L.
711
APPENDIXB
CAUTIONThe user must avoid multiple
DMA data transfers (burst or
"hog" mode) during a processor-generated refresh operation so that a com plete refresh
cycle can occur once every 16
ms.
AS1
+12B
+ 12V Battery
Power-secondary + 12V
power connection. Battery
power can be used with certan devices.
AT1
GND
Ground-system signal
ground and dc return.
AU1
PSPARE1
Spare (not assigned, customer
usage not recommended).
AV1
+5B
+5V Battery
Power-secondary +5V
power connection. Battery
power can be used with certain devices.
BA1
BDCOKH
DC Power OK-power supplygenerated signal that is asserted when there is sufficient dc
voltage available to sustain reliable system operation.
BB1
BPOKH
Power OK-asserted by the
power supply when primary
power is normal. When negated during processor operation, a power-fail trap sequence is initiated.
BC1
BD1
BE1
BF1
BH1
SSPARE4
SSPARE5
SSPARE6
SSPARE7
SSPARE8
Special Spare (not assigned,
not bused; available for user
interconnections).
712
APPENDIXB
BJ1
GND
Ground-system signal
ground and dc return.
BK1
BL1
MSPAREB
MSPAREB
Maintenance Sparenormally connected together
on the backplane at each option location (not a bused
connection).
BM1
GND
Ground-system signal
ground and dc return.
BN1
BSACKL
This signal is asserted by a
DMA device in response to the
processor's BDMGO L signal,
indicating that the DMA device
is bus master.
BP1
BIRQ7 L
Interrupt request priority
level 7
BR1
BEVNT L
BS1
PSPARE4
External Event Interrupt Request-when asserted, the
processor responds (if PS bit
7 is 0) by entering a service
routine via vector address
1008 • A typical use of this signails a line-time clock interrupt.
Spare (not assigned; customer
usage not recommended).
BT1
GND
Ground-system signal
ground and dc return.
BU1
PSPARE2
Spare (not assigned; customer
usage not recommended).
BV1
+5
+5V Power-normal +5 Vdc
system power.
AA2
+5
+5V Power-normal +5 Vdc
system power.
AB2
-12
-12V Power--12 Vdc (optional) power for devices requiring this voltage.
713
APPENDIXB
.NOTE
LSI-11 modules which require
negative voltages contain an
inverter circuit (on each module) which generates the required voltage(s); hence, -12
V power is not required with
DIGITAL-supplied options.
AC2
GND
Ground-system signal
ground and dc return.
AD2
+12
+12V Power-+12 Vdc system power.
AE2
BDOUTL
Data Output-BDOUT, when
asserted, implies that valid data is available on BDALO-15 L
and that an output transfer,
with respect to the bus master
device, is taking place.
BDOUT L is deskewed with respect to data on the bus. The
slave device responding to the
BDOUT L signal must assert
BRPLY L to complete the
transfer.
AF2
BRPLY L
Reply-BRPL Y L is asserted in
response to BDIN L or BDOUT
L and during IAK transactions.
It is generated by a slave device to indicate that it has
placed its data on the BDAL
bus or that is has accepted
output data from the bus.
AH2
BDINL
Data Input-BDIN L is used for
two types of bus operation:
1. When asserted during
BSYNC L time, BDIN L implies an input transfer with
respect to the current bus
master, and requires a re-
714
APPENDIX B
2.
sponse (BRPLY L). BDIN
L is asserted when the
master device is ready to
accept data from a slave
device.
When asserted without
BSYNC L, It Indicates that
an Interrupt operation is
occurring.
The master device must deskew input data from BRPLY
L.
AJ2
BSYNCL
Synchronize-BSYNC L is asserted by the bus master device to Indicate that it has
placed an address on BDALO17 L. The transfer is In process
until BSYNC L is negated.
AK2
BWTBTL
AL2
BIRQ4 L
Wrlte/Byte-BWTBT L is used
In two ways to control the bus
cycle:
1. It is asserted during the
leading edge of BSYNC L
to indicate that an output
sequence Is to follow (DATa or DATOB), rather
than an Input sequence.
2. It Is asserted during
BDOUT L, in a DATOB
bus cycle, for byte addressing.
Interrupt Request-A device
asserts this signal when its interrupt enable and interrupt·
request flip-flops are set. If the
processor's PS word bit 7 is 0,
the processor responds by acknowledging the request by
asserting BDIN Land BIAKO
L.
715
APPENDIX B
AM2
AN2
BIAKIL
BIAKOL
Interrupt Acknowledge Input
and Interrupt Acknowledge
Output-this is an interrupt
acknowledge signal which is
generated by the processor in
response to an interrupt request (BIRO L). The processor
asserts BIAKO L, which is
routed to the BIAKI L pin of the
first device on the bus. If it is
requesting an interrupt, it will
inhibit passing BIAKO L. If it is
not asserting BIRO L, the device will pass BIAKI L to the
next (lower priority) device via
its BIAKO L pin and the lower
priority device's BIAKI L pin.
AP2
BBS7L
Bank 7 Select-The bus master asserts BBS7 L when an
address in the upper 4K word
bank is placed on the bus.
BSYNC L is then asserted and
BBS7 L remains active for the
duration of the addressing
portion of the bus cycle.
AR2
AS2
BDMGI L
BDMGOL
DMA Grant Input and DMA
Grant Output-This is the
processor-generated daisy-chained signal which grants
bus mastership to the highest
priority DMA device along the
bus. The processor generates
BDMGO L, which Is routed to
the BDMGI L pin of the first
device on the bus. If it is requesting the bus, it will inhibit
passing BDMGO L. If it is not
requesting the bus, it will pass
the BDMGI L signal to the next
(lower priority) device via its
BDMGO L pin. The device as-
716
APPENDIX B
serting BOMR L is the device
requesting the bus, and it responds to the BOMGI L signal
by negating BOMR, asserting
BSACK L, assuming bus mastership, and executing the required bus cycle.
CAUTION
OMA device transfers must be
single transfers and must not
interfere with the memory
refresh cycle.
AT2
BINITL
Initiallze-BINIT L is asserted
by the processor to initialize or
clear all devices connected to
the 110 bus. The signal is generated in response to a powerup condition (the negated condition of BOCOK H).
AU2
AV2
BOALO L
BOAL1L
Data/Address Lines-These
two lines are part of the data/address bus over which address and data information are
communicated. Address information is first placed on the
bus by the bus master device.
The same device then either
receives input data from, or
outputs data to, the addressed
slave device or memory over
the same bus lines.
BA2
+5
+5V Power-normal +5 Vdc
system power.
BB2
-12
-12V Power--12 Vdc (optional) power for devices requiring this voltage.
BC2
GNO
Ground-system signal
ground and dc return.
717
APPENDIX B
BD2
+12
+12V Power-+12 Vdc system power.
BE2
BF2
BH2
BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2
BDAL2 L
BDAL3 L
BOAL4 L
BDAL5 L
BOAL6 L
BOAL7 L
BOALS L
BOAL9 L
BDAL 10 L
BDAL11 L
BDAL12 L
BDAL 13 L
BOAL14 L
BOAL 15 L
Data/Address Lines-These
14 lines are part of the data/address bus previously described.
718
APPENDIXC
NOMENCLATURE FOR
CIRCUIT SCHEMATICS
BASIC SIGNAL NAMES
Signal names on DIGITAL print sets are in the following form:
SOURCE (ASSERTION) SIGNAL NAME (STATE) POLARITY
SOURCE indicates the drawing number of the print from which the
signal originates. The drawing number of a print is located in the lower
right corner of the print title block (01, 02, 03, etc.).
ASSERTION is either blank or a NOT sign. A blank indicates reference
to the asserted state (the true state) of the signal; a NOT sign indicates
reference to the negated state (the false state) of the signal. Signals
originating from flip-flops do not use the NOT sign to indicate assertion; instead, they use a 1 or 0 in parentheses following the signal
name for assertion indication.
SIGNAL NAME is the proper name of the signal. The names used on
the print are also in this manual for correlation between the two.
STATE is present when the signal source is a flip-flop; it is either 0 or 1.
POLARITY is either H or L to indicate the voltage level of the signal; H
means +3V; L means ground.
For example, the signal
05TXDONEH
originates on sheet 5 of the drawings and is read "when TX DONE is
true, this signal is at +3V.
II
LSI-11 bus Signal lines carry a dual source indicator. These signal
names represent a bidirectional wire-ORed bus; as a result, multiple
sources for a particular bus signal exist.
FLIP-FLOP SIGNAL NAMES
Flip-flop signal names add an extra dimension. Although flip-flops
have only two outputs, four signal names are possible (Figure 1). The
two real outputs are RX DONE (1) H on pin 5 and RX DONE (0) H on pin
6. The two additional outputs are simply the two real outputs reidentified. RX DONE (1) L is electrically the same as RX DONE (0) Hand RX
DONE (0) L is electrically the same as RX DONE (1) H. For example,
719
APPENDIXC
the signal RX DONE (0) L is read "when the RX DONE flip-flop is clear
(holding a zero), this signal is at ground."
RX DONE 11) H
RX DONE 111 L
RX DONE (0) L
RX DONE (0) H
11-2236
Figure 1
Flip-Flop Signal Names
720
APPENDIX D
ASYNCHRONOUS SERIAL LINE UNIT
(SLU) COMPARISONS
The characteristics listed In Tables 1, 2, and 3 compare the
different members of the DLV11 (lSI-11 bus) and DL 11 (UNIBUS)
families of asynchronous serial line products. All modules of the
DLV11 series are dual-height modules. The DLV11-E, -F, and -J modules detect overrun conditions which are reported In the receiver CSR.
These modules will not generate phantom Interrupts on overrun.
DLV11-J
Each of the four serial ports on this module are separate and Independent from the others. This is not a multiplexed module. Each port has
its own CSRs, data buffers, interrupt vectors, baud rates, UARTs, etc.
The net effect of this module Is to achieve a 4:1 compression ratio over
the DL V11. The main functional difference between the ports of the
DLV11-J and the DLV11 Is that the DL V11-J provides an RS-232Ccompatible Interface (using RS-422 and RS-423) only and requires the
DLV11-KA module (one per port) to accommodate the 110 baud, 20
rnA current loop Interface.
DLV11-E
This module Is functionally equivalent to the DL 11-E except that it has
programmable baud rates. This module provides one serial port that
has full modem control.
DLV11·F
This module is functionally equivalent to the DL 11-F except that it has
programmable baud rates. This module will eventually replace the
DLV11.
DZV11·B
The DZV11-B Is a multiplexer Interface between four asynchronous.
serial data communication channels and the LSI-11 bus. The DZV11-B
provides EIA level conversion and full modem control suitable for
support of Bell series 103, 202, or equivalent modems. Program compatibility is maintained with the UNIBUS option, DZ11-A. The only
compatibility exception Is the number of serial channels supported. As
a product enhancement feature, additional modem control leads are
supported to allow half-duplex operation on swltched-network-type
lines.
MXV11·A
This multifunction module consists of two serial ports, RAM and ROM
memory, and a 60 Hz clock. The two serial ports are RS-423 (RS-232C-compatlble, data leads only) The MXV11-A has two completely separate serial ports, where each port has Its own CSRs, data buffers,
baud rate generation, etc.
721
Table 1
Comparison of Hardware Features
Unibus
. ...... . . .
c(
II»
~
.....
~
...J
Q
...J
Q
0
~
~
...J
Q
. .
W
I.L.
Q
W
.....
.....
~
~
~
~
~
~
~
...J
Q
~
...J
Q
>
...J
Q
>
...J
Q
>
...J
Q
No. of ports per module
20 rnA current loop
RCVR active or passive
XMIT active or passive
XMIT active only
X
X
X
X
X
X
X
X
X
§ The loop-back cable is required to implement this function.
110 baud only.
Q
-!=
II»
~
.....
>
N
>
><
4
2
•
>
...J
~
C
~
Q
~
~
:E
X
X
~
"C
m
Z
C
X
Optional feature.
** RS-423 only
>
...J
.
~
'tI
:j: Applies only to the port assigned to the console Device.
I
~
X
X
* The external 20 mA option (DLV11-KB) is required to implement this function.
t
~
c(
X
X
X
X
EIA RS-423, RS-422
Data leads only
'"
r
4
EIA RS-232C
Full modem control
Limited modem interface
I\J
I\J
LSI-11 bus
X
X
><
C
Unibus
LSI-11 bus
. . . . .
C
ID
U
Q
w
. .
..,
W
II.
'P"
'P"
'P"
'P"
'P"
'P"
•
'P"
'P"
>
Q
Q
Q
Q
. .
C
~
ID
'P"
'P"
'P"
'P"
... ... ... ... ... >... ...> >... ... >...
'P"
'P"
'P"
'P"
'P"
'P"
'P"
'P"
'P"
'P"
Q
Q
Q
Q
Q
X
X
CCITT
X
Halt on framing errort
.....,
I\)
Boot on framing errort
c.:I
X
Reader run control
X
Error flags
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
t
Optional feature.
Applies only to the port assigned to the console Device.
§ The loop-back cable is required to Implement this function.
I
110 baud only.
Q
+
+
'P"
'P"
:IE
~
+
+
X
X
X
X
• The external 20 mA option (DLV11-KB) Is required to'lmplement this function.
*
>
N
•
>
><
X
X
Baud rates (Table 3)
Programmable
On-board clocks for split speed
Q
c(
X
'1J
."
m
Z
C
><
C
LSI-11 bus
Unibus
-- -- - - -- - - -- - -- - c(
c(
I
~
.....,
I\)
~
IIII
~
(.)
I
~
Q
I
~
WI
WI
~
>
~
>
~
I&.I
-"I
~
I
IIII
>
~
>
~
>
~
N
Q
Q
Q
Q
Q
Q
Q
Q
Break generation bit
X
X
X
X
X
X
X
X
Receiver active bit
X
X
X
X
X
X
X
Maintenace bit
X
X
X
X
X
X
X
§
UART cleared by INIT
X
X
X
X
X
X
X
X
§
X
X
X
X
X
X
• The external 20 rnA option (OLV11-KB) is required to Implement this function.
t Optional feature.
:j: Applies only to the port assigned to the console Device.
§ The loop-back cable is required to implement this function.
I
110 baud only.
X
X
X
UART cleared by DeOK
No trap on write to input buffer
I
Q
X
Q
>
Q
X
X
c(
I
>
><
:t
X
§
~
'"U
'"U
m
z
C
><
C
LSI-11 bus
Unibus
. .
.
C
ID
U
Q
'I""
'I""
'I""
'I""
'I""
'I""
•
W
'I""
'I""
...I
'I""
'I""
..I
•
...I
Q
..J
Q
...I
Q
Q
Q
'I""
'I""
>
..I
Q
Easy configuration using wire-wrap
jumpers
.......
I\)
(J'I
. .
W
LL.
'I""
'I""
'I""
'I""
..,•
'I""
'I""
>
...I
>
..I
Q
>
..I
Q
X
X
X
Q
. . c.
C
~
ID
'I""
'I""
'I""
'I""
>
..I
Q
>
N
Q
'I""
'I""
>
><
:E
X
X
m
z
X
><
Stop bits
1
1.5
X
2
X
X
X
X
X
X
X
X
X
X
X
X
X
* The external 20 mA option (DLV11-KB) is required to Implement this function.
t
Optional feature.
:j: Applies only to the port assigned to the console Device.
§ The loop-back cable is required to implement this function.
I
110 baud only.
~
"'U
"'U
X
X
X
X
X
X
C
C
Table 2
Baud Rates
LSI-11 bus
Unibus
Baud
Rate
.....
I\)
m
50
75
110
134.5
150
200
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38,400
External
. .
C
ID
~
'P"
'P"
9
'P"
'P"
. .
Q
W
~
'P"
'P"
'P"
'P"
>
....I
....I
....
Q
....I
C
Q
Q
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Q
....
....Q
X
X
X
X
X
X
X
X
X
X
~
'P"
X
X
. .
W
LL
'P"
'P"
'P"
'P"
>
....I
Q
>
....I
Q
C
'7
'P"
'P"
>
....I
C
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
., The external 20 mA option (OLV11-KB) is required to implement this function.
~
'P"
'P"
>
....I
Q
X
.
ID
'P"
'P"
>
N
X
X
X
X
X
'P"
'P"
>
><
Q
:E
X
X
X
X
X
X
~
X
X
X
m
X
X
-><
X
X
X
X
X
X
X
X
~
"'U
"'U
Z
C
C
X
X
X
X
X
Table 3
Comparison of Software Features
I
Unibus
~
.,..
.,..
..J
C
.....
I\)
.....
Register
Bit
Name
RCSR
15
Data Set Status/
Interrupt
14
13
12
11
10
9,8,4
7
Ring
CTS
CD
Receiver Active
2d Receive
Unused
Receive Done
Receive Int Enb
Data Set Int Enb
2dXMT
RTS
PTR
Rdr Enable
6
5
3
2
1
0
.
m
.,..
.,..
...J
C
. .,...,...
c
~
.,..
.,..
.,..
.,..
C
C
..J
..J
w
..J
C
LSI-11 bus
........
>
..J
Q
. .,...,... .,...,...
w
I.L
~
~
.,..
>
..J
>
...J
>
..J
c
)(
.,..
.,..
C
C
.,..
>
:E
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
• The external 20 mA option (OLV11-KB) is required to implement this funtion.
»
'1J
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
'1J
m
Z
C
X
X
X
X
X
X
X
X
X
X
X
><
C
LSI-11 bus
Unibus
C(
I
.....
.....
..J
Register
RBUF
--oJ
I\)
00
XCSR
XBUF
Q
m
.....
.....
I
..J
Q
0I
Q
Q
..J
..J
Q
..J
Q
.....
.....
.....
.....
I
W
I
.....
.....
.....
.....
>
..J
Q
w
.....
.....
~
~
>
..J
>
..J
>
..J
I
Q
I
.....
.....
Q
I
.....
.....
C(
.....
.....
I
>
><
Q
:t
X
15
14
13
12
11-8
7-0
Error
OE
X
X
X
X
X
X
X
X
X
X
X
FE
X
X
X
X
X
X
X
PE
X
X
X
X
X
X
X
Unused
Receive Data
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
15-8
7
6
5-3,1
2
0
Unused
X
X
X
X
X
X
X
X
XMTReady
XMT Int Enb
Unused
Maintenance
XMTBreak
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
*
X
15-8
7-0
Unused
XMTBUF
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
* . The external 20 rnA option (OLV11-KB) is required to implement this funtion.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
~
."
."
m
Z
C
><
C
APPENDIX E
COMPARISON OF DATA
TRANSMISSION TECHNIQUES
Frequently, the application arises where a data transmission path has
to be established between two devices. Usually the distance between
the device is known and also the rate of data transmission. The problem is deciding which is the best communication technique to use to
interconnect the devices.
Figure 1 is a graph of data versus distance for the various standard
transmission techniques. Parallel data transmission techniques (PLUs
and DMA) give the highest data rate; however, they are good only for
relatively short distances. The serial techniques (RS-232C, RS-422
and current loops) are good for longer distances but at limited data
rates.
While analyzing Figure 1, remember that the axes are logarithmic and
that the data in words per second rather than baud rate. The limits
established for distance and data rate are a function of both the inherent limitations of the transmission technique and of the DIGITAL device used to do the interconnection. As an example, look at the 422
section of the graph. Maximum distance is 4000 feet as established by
EIA standard RS-422, but the maximum data rate of 1920 words per
second is based on the maximum baud rate of the DLV11-J which
is 38.4K baud.
Table 1 is a summary of the LSI-11 bus and UNIBUS devices which
can be used with each communication technique. Currently, there is
no UNIBUS device for EIA RS-422.
729
APPENDIXE
lOOK
10K
EIA
RS·232C
WITH
MODEM
~
~
w
~----.... 4K
1.5K
lK
u
z
~
f-
~
0
100
100
~
__________~____~~1_92_0___________--r __ 50
DMA (TRI-STATE)
i--------------+---------------r----
_ _ 15
10
ALL
DMA
(TTL)
PLU
TECHNIQUES
480
10
100
46K
10K
lK
lOOK
500K
1M
DATA RATE (WORDS/S)
MR·I455
Figure 1
Data Rate vs Distance with DIGITAL Devices
Table 1
Loop
EIA (RS-232C)
EIA with Modem
RS422, RS423
PLU
DMA
Communication Techniques
LSI-11
UNIBUS
OLV11
DLV11
DLV11-E
DLV11-J
DRV11
ORV11-B
OL 11-C
OL 11-0
OL 11-E
OR11-C
DR11-B
730
APPENDIX E
NOTES AND ASSUMPTIONS FOR FIGURE 1
1. Data Rate Definition
a. One word equals 16 bits.
b. For serial techniques, one word equals two characters formatted with one start bit, eight data bits, and one stop bit.
Asynchronous serial transmission is assumed.
2.
3.
4.
Serial Line Maximum Data Rate
a. Modems were limited to 120 words/sec (2400 baud) because
modems with higher rates cost more than LSI-11 systems
usually warrant. Higher data rate modems are generally
synchronous rather than asynchronous.
b. 480 words/sec is equal to 9600 baud, the limit of the DLV11
SLU.
c. 1920 words/sec is equal to 38.4 baud, the limit of DLV11-J
SLU.
PLU (Parallel Line Unit) Limits
a. The TTL inputs/outputs of the DRV11 limit the distance to 15
feet.
b. 46K words/sec assumes non-interrupt-driven program servicing with bit testing (TSTB, BMI, MOV and SOB). 97K
words/sec is maximum rate with program servicing without
bit testing (MOV and BR). With interrupt-driven servicing, the
maximum limit is 20K words/sec assuming 50 ILS for interrupt
latency and software servicing of interrupt.
DMA (Direct Memory Access) Limits
a. The DRV11-B can be used up to 50 feet because it has tristate drivers and receivers. The distance is limited to 15 feet
with TTL devices like the DR11-B.
b. DMA transfer with the DRV11-B and the DR11-B are limited to
500K words/sec in burst mode operation; 250K words/sec is
the limit for single-cycle mode operation with either device.
These limits are device-dependent, not LSI-11 bus-dependent. Note that burst mode can disrupt memory refreshing If
bus refreshing (DMA and microcode) is used. Self-refreshing
memories (MSV11-CD or MSV11-D) eliminate this problem.
731
APPENDIXF
INTEGRATED CIRCUITS
Bus Receivers and Bus Drivers
The equivalent circuits of LSI-11 bus-compatible drivers and receivers
are shown in Figure 1. To perform the receiver and driver functions.
Digital Equipment Corporation uses two monolithic integrated circuits
with the characteristics listed in Table 1. A typical bus driver circuit is
shown in Figure 2. Note that 8641 quad transceivers can be used.
combining LSI-11 bus receiver and driver functions in a single package.
Bus receiver (8640). bus driver (8881). and bus transceivers (8641) are
shown in Figures 3. 4. and 5. respectively.
OUT -
+34V
~
IN
Rl
~
Cl
Rl = 120K. MIN
R2; 20K.MIN
Cl = 10pF MAX
-=R2
Figure 1
Ef
TRANSMITTER OFF ILOGICAL 01
A3; 120K.MIN
C2 = 10pF.MAX
TRANSMITTER ON ILOGICAL II
R3 = I 1 OHMS. MAX
C2 ; 10 pF MAX
Bus Driver and Receiver Equivalent Circuits
+5V
TYPICAL
BUS DRIVER
11-3307
Figure 2
Typical Bus Driver Circuit
732
APPENDIXF
Vee
14
13
12
11
10
9
,
2
3
4
5
6
8
7
GND
CP-'27,
Figure 3
8640 Quad 2-lnput NOR Gates
(Bus Receiver)
Vee
14
13
12
11
10
9
8
2
3
4
5
6
7
GND
CP '272
Figure 4
8881 Quad 2-lnput NAND Gate
(Bus Driver)
16
BUS 1
15
DATA IN 1
14
DATA OUT 1
13
BUS 2
12
DATA IN 2
11
pAT A OUT 2
10
ENABLE A
Vee
BUS 4
OATA IN 4
DATA OUT 4
BUS 3
DATA IN 3
DATA OUT 3
ENABLE B
GROUND
3 DATA OUT 1
ENABLE A 7
ENABLE B 9
Figure 5
8641 Quad Unified Bus Transceiver
(Bus Receiver/Driver)
733
APPENDIXF
Table 1
Driver
(8881)
(8641)
LSI-11 Bus Driver. Receiver. Transceiver
Characteristics
Characteristic
Sym
Specifications
Input high voltage
Input low voltage
Input current at 3.8 V
I nput current at 0 V
Output high voltage
Output high current
Output low voltage
Output low current
Propagation delay to
high state
Propagation delay to
low state
Input high voltage
I nput low voltage
Input high current
Input low current
Output low voltage
70 rnA sink
Output high leakage
current at 3.5 V
Propagation delay to
low state
Propagation delay to
high state
VIH
VIL
IIH
IlL
VOH
VOH
VOL
IOL
TPDH
VIH
VIL
IIH
IlL
VOL
1.7 V min
1.3 V max
80llA max
10 IlA max
2.4 V min
(16 TIL loads)
0.4Vmax
(16 TIL loads)
10 ns min
35 ns max
10 ns min
35 ns max
2.0V min
0.8 V max
60llA max
-2.0 rnA max
0.8 V max
IOH
251lA max
1.3
TPDL
25 ns max
1.5
TPDH
35 ns max
1.5
TPDL
1.5
6
6
1
NOTES
1. This is a critical parameter for use on the 1/0 bus.
All other parameters are shown for reference only.
2. This is equivalent to being capable of driving 16
unit loads of standard 7400 series TIL integrated
circuits.
3. Current flow is defined as positive if into the terminal.
4. Conditions of load are 390 Q to +5 Vand 1.6 kQ
in parallel with 15 pF to ground for 10 ns min and
50 pF for 35 ns max.
5. Times are measured from 1.5 V level on input to
1.5 V level on output.
6. This is equivalent to 1.25 standard TIL unit loading of input.
Bus receivers and drivers should be well grounded and use Vce to
ground bypass capacitors. These gates should be located as close as
practical to the module fingers which plug into the backplane and all
etch runs to the bus should be kept as short as possible. Attention to
these cautions should yield a module design with minimum bus loading
(capacitance ).
734
APPENDIXG
CABLING SUMMARY
Preassembled cables are available in a variety of lengths and types as
listed in Table 1 The H854 and H85S connectors are shown in Figure 1.
,
H854
CONNECTOR
H856 CONNECTOR
(SHOWN WITH
CABLE INSTALLED)
Figure 1
J 1 or J2 Connector Pin Locations
735
\
APPENDIXG
Function
Seriall/O-Asynchronous
20MA
Module Type
Cable Recommendations
DLV11-F 1-Line
DLV11-J 4-Line
BCQ5M-2C
DLV11-KA (1 per line)
EIA RS-232C
Data only
(DLV11-J is also
RS4221423)
DLV11-F 1-Line
BC01V-25 (M)
DLV11-J 4-Line
MXV11-A
BC21B-Q5 (M)
or
1 per line
BC20N-Q5 (T)
EIARS-232C
with Modem Control
DLV11-E 1-Line
DZV11-B 4-Line MUX
BC01V-25 (M)
Cable included
DUV11-DA 1-Line
BC05C-25 (M)
Seriall/O-Synchronous
EIARS-232C
with Modem Control
Digital 1/0
Programmed Transfer
DRV1116 in/16 out
2ea
DMA Transfer
Analog 1/0
AID
D/A
Mass Storage
Tape Cartridge
Double Density Floppy
Diskette
Hard Disk
(H9273 Backplane Req'd)
Note: M-Connects to a Modem
U-User end unterminated
DRV11-B 16 in/16 out
BC07D-15(U)
or
BC08R-12(B)
ADV11-A 16 channel
AAV11-A 4 channel
BC07D-15(U)
BC08R-12 (B)
TU58-BB
BC20N-Q5 plus a
Serial Modem (M) cable
Includes cable
Includes cable
RXV21-BA
RLV11-AK
T-Connects to an EIA Terminal
B-User end terminated with 40 pin Berg Connector
736
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
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1981
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