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Integrated - Circuit
Applications

JERRY EIMBINDER
CONFERENCE DIRECTOR
PRINTED IN THE U. S. A.

~COPYRIGHT 1976 INTEGRATED CIRCUITS APPLICATIONS

CONFERENCE, P. O. BOX 1021, MELVILLE, N.Y.
ELECTRONIC ENGINEERING TIMES
280 COMMUNITY DRIVE
GREAT NECK, N.Y. 11021

11746

~~Icctn)nic ~~IIAiIICCriIIA

TIMF~
Microprocessor/Mel11ory
Proceedings

Integrated Circuit·
Applications
Conference

Part One

See Last Page for Table of Contents

TABLE OF CONTENTS
MICROPROCESSORS
1.
2.

3.

4.
5.
6.
7.

Introduction: Evolution of the Microprocessor
by Sam Davis, Electronic Engineering Times .••••.•.

1-4

Recent Developments in the Design and
Application of a Bipolar Control Store
Sequencer by Steve Lau, Signe,tics .••..•••.•...•..•

5-17

Single Chip Microprocessor with Minicomputer
Performance by John D. Bryant, Texas Instruments

18-35

A Microprocessor Designed with the User in
Mind by William E. Wickes, Electronic Arrays

36-54

Introducing the 32K Read Only Memory by
Michael R. McCoy, Electronic Arrays ••.••••••......

55-67

Microprocessor Software Development by
David Lindsay, Mostek Corporation .•.•••.••••..•.•.

68-78

A Practical Microprocessor Design Example
by David C. Uimari, Signetics •••..•••..••....••...

79-103

8.

The 6710 Microprogram Control Unit by
John Birkner, Monolithic Memories .........••...... 104-115

9.

Use of the Mostek F8 Microcomputer as a
Software UART by R. L. Baldridge and
D. Lindsay, Mostek Corporation ....•.......••....•. 116-152

10.

The Latest Developments in PROM and EPLA
Programming by Dick Woods, Data I/O Corp •..•.••.•. 153-168

11.

Logic State Analyzers Gain Widespread
Acceptance as Microprocessor Debugging Tool
by Bruce Farly, Hewlett Packard Co . . . • . • . . . . . . . . . . 169-170

12.

Charge-Coupled Devices by Dave House,
Jim Oliphant and Bob Papenberg, Intel

171-173

13.

A Microcomputer Designed for Control by
Michael A. Liccardo, Scientific Microsystems ...... 174-184

14.

A Microcomputer-Based CRT Terminal by
J. E. Bass, Rockwell International •.•.•.••.••••... 185-195
LINEAR/DIGITAL

1.
2.

The Monolithic Voltage Frequency Converter
by James C. Schrnoock, Raytheon •..••••••••....••.•.

1-15

DAC-08 Applications by John Schoeff & Donn
Soderquist, Precision Monolithics ••..•..••••.•••.•

16-27

--217-

3.
4.

5.

6.
7.

8.
9.
10.
11.

12.

13.
14.

15.

16.

DTL Peripheral/Power Drivers by Paul R.
Emerald, Sprague Electric .....•........••••......•

28-46

Masterslice LSI - The Cost Effective
Alternative by Dr. Charles A. Allen,
International Microcircuits . . . . . . . . . . . . . . . . . . . . . . .

47-60

Structure and Applications of Field Progranunable Logic Arrays by Napoleone Cavlan,
S ignetics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

61-82

Low Power Schottky TTL by Peter Alfke &
Charles Alford, Fairchild Semiconductor

83-92

The AD 7550 - A 13-Bit "Quad Slope" Analog
to Digital Converter by Will Ritmanich,
Analog Devices .......•.•...•......•••..••..•.....•

93-102

Custom IC Design Using I2L Technology by
Alan B. Grebene, Exar Integrated Systems

103-111

A Low Cost 4 1/2-Digit A/D Converter by
Lee Evans & Dave Fullagar, Intersil .....•.•...•...

112-137

A Logic Compatible High Current Switch
by Marvin K. Vander Kooi, Siliconix ..•..•.•......•

138-145

Evolution of the IC Op Amp by Jim Soloman,
Tom Frederiksen and Nello Sevastopoulos,
National Semiconductor .•..•...•...•...............

146-157

164 Channel Frequency Synthesizer for Citizens
Band, 82 Channel Television CATV and Marine
Radio by Andrew C. Tickle, Nitron . . . . . . . . . . . . . . . . .

158

64x4-Bit Nonvolatile Memory 4-Bit Byte Alterable by Andrew C. Tickle, Nitron ........•...•..•.•

159

Selecting, Understanding and Using the
3-Termina1 Regulators by Jim Soloman, Tom
Frederiksen, and Nello Sevastopoulos,
National Semiconductor ......•..•......••....•.••••

160-177

Recent Advances in Linear ICs by Jim Soloman,
Tom Frederiksen and Nello Sevastopoulos,
National Semiconductor ..••...•..•...•.•...........

178-187

Exploding the Address Multiplexing Myth
by Bruce Threewitt, Fairchild Semiconductor

188-196

17.

Using the 8700 Series CMOS A-to-D Converters
by Skip Osgood, Teledyne Semiconductor ............. 197-204

18.

Ana1og-to-Digital Conversion Techniques with
the M6800 Microprocessor by Don Aldridge,
Motorola Semiconductor Products Inc ..••.••.•..•.•.. 205-214

-218-

1.

INTRODUCTION:
EVOLUTION OF THE MICROPROCESSOR
SAM DAVIS
Semiconductor Editor
Electronic Engineering Times
Great Neck, NY

Comparing microprocessor history to a 24-hour clock, it
has been said that we are still in the first 30 seconds.
The clock started counting in 1969 and since then no fewer
than 20 semiconductor companies have entered the microprocessor arena. Some backed into it, some entered with a
methodical and planned approach, others have started and abandoned approaches.
liThe electronics industry will undergo a significant positive
upheaval due to the microprocessor," comments Gordon Moore,
president of Intel.
"It is yet another step in the increasing
pervasiveness of electronics. It is the most significant,
revolutionary device since the IC, and will cause a dislocation
of roles between the user and the semiconductor manufacturer.
The semiconductor supplier has now assumed the role of system
designer as he controls the architecture of the microprocessor. II
"Father of the microprocessor" is the title bestowed by Moore
on Ted Hoff, manager of applications research at Intel.
"We
were a fairly small company founded in 1968, when Busicom of
Japan contacted us in June, 1969," Hoff recalls.
"They wanted
us to design a group of custom LSI chips for a calculator that
would have required 11 36-to 40-pin packages. If we had
followed their approach, it would have taxed our design
capabilities and their economic goals would have been hard to
meet. II
Hoff had been working with a DEC-8 at that time and was
interested in its use as a scientific calculator. This led
to the idea of developing a family of general-purpose LSI
that could be programmed as a calculator, or for many other
applications. After determining this approach was feasible,
the project started in September, 1969. The result was the
first general-purpose, LSI ,parallel processor family, the
now-famous MCS-4 or 4004. The first devices of the threechipset family were delivered in April, 1971 and the first
public announcement came in November, 1971.
Heading up the design effort for Intel was Federico Faggin
(pronounced Fa-geen), now president of Zilog, Los Altos, CA.
Faggin remarked, "The technology was ready in 1970, and the
silicon-gate MOS LSI process (which he co-invented) allowed
us to get the curcuit density required for the CPU chip.
The idea had been around before, but Intel implemented the
first cost-effective, practical family of microprocessor
devices. The key was the successful marriage of technology
and function.
The 4004 had the equivalent of 2,000 transistors;
other LSI at that time had a maximum of 1,000

-1-

transisto.rs per chip.
A third member o.f Intel's team at the time was micro.pro.cesso.r
department manager Hank Smith, who. left Intel in 1974 to. beco.me
a general partner in a New Yo.rk City venture capital firm.
"It wo.uld have been great fo.r us to. say we envisio.ned success
fo.r the micro.pro.cesso.r when we started," Smith co.mmented.
"We
knew there was so.mething 'there and it was significant, but I
do.n't think any o.f us ever fo.resaw ho.w quickly it wo.uld catch
o.n and ho.w fast it wo.uld grew. Initially it was true that we
just let things happen, but after we go.t started we put to.gether quite an extensive game plan.
II

The 8008 family was next to. be develo.ped by Intel, in co.njunctio.n with the then Co.mputer Terminals Co.rp., no.w Datapo.int.
Vic Po.o.r, senio.r vice president fo.r research and develo.pment
at Datapo.int, recalls that it was abo.ut Thanksgiving, 1969
when he and a co.lleague wo.rked o.ut the architecture fo.r a
single MOS chip pro.cesso.r.
"This was to. be the heart o.f a pro.cesso.r the co.mpany was
designing fo.r what was to. beco.me the Datapo.int 2200 CRT
terminal," Po.o.r explained. "We first bro.ught o.ut the 2200
as a bipo.lar machine with the idea that we wo.uld mo.ve into.
the MOS chip when it became available. We entered into. a
co.ntract with bo.th TI and Intel late in 1970. TI was well
into. develo.pment befo.re dro.pping o.ut, while Intel was later
in develo.ping the precesso.r than we had planned. In the
meantime, TTL prices dro.pped precipito.usly and TTL speeds
were still faster than MOS LSI. We declared a truce with
Intel and said in effect, 'we really do.n't want the parts
anymo.re, why do.n't yo.u go. market it o.n yo.ur o.wn and call it
square with us. In return, we'll let yo.u have the rights to.
it.' We have stayed with bipo.lar MSI pro.cesso.rs and have no.t
used MOS LSI in two. versio.ns o.f the 2200 and the newer 5500
CRT terminals.
"Wo.rk o.n the 8008 was an o.n and o.ff pro.po.sitio.n," Federico.
Faggin remembered.
"After we started o.n it, we had to. pull
so.me peo.ple o.ff to. wo.rk o.n a pattern generato.r to. test the
4004. When the tester was finished, wo.rk o.n the 8008 started
again in April, 1971 and the first samples were available in
January, 1972."
Faggin po.inted o.ut that the 8008 chip size was abo.ut 146 x
146 mils, taking advantage of the experience gained o.n the
4004, which had a 136 x 136 mil chip size. "We were careful
not to. go. to.o. far all at o.nce, " Faggin added. "In 1971, 170
mils o.n a side was kind o.f a 'no. man's land.' To.day,o.ver
200 mils is no.t unco.nuno.n."
Faggin said he pro.po.sed the 8080 as the next generatien
micro.pro.cesso.r in the summer o.f 1972 and by No.vember had
develo.ped the specs and architecture. The 8080 was to. emplo.y
N-channel silico.n-gate MOS techno.lo.gy, whereas the 4004 and
8008 were P-channel MOS devices. First samples o.f the 8080
-2-

became available in November, 1973.
"Compared to the 8008,
the 8080 has double the instruction set and is about eight
times faster, providing almost 20 times the improvement in
throughput.
It also has a better interrupt capability,"
Faggin observed.
"After the 8080 was introduced, things really started
happening at Intel, he continued.
"From a handful of
people who worked on the 4004 and 8008, we had expanded to
about 80 people in the microprocessor department when I left
in November, 1974."
II

Next on the list for Intel was the first complete microprocessor family of bipolar devices, the 3000 series introduced in September, 1974. MMIT came out with their 5701/6701,
four-bit slice microprocessor prior to the 3000 series, but
Intel was the first with a complete family of compatible
devices for their two-bit slice, bipolar microprocessor. This
device was followed later that year with the 4040, an improved
version of the 4004.
Microcomputer marketing manager Hal Feeney describes Intel's
hardware efforts in 1975 as directed toward reducing chip
count and improving throughput of existing microprocessor
systems. New devices include a programmable interval
timer, programmable DMA controller and programmable interrupt
controller. They are also working on devices that will allow
four-bit and eight-bit systems to be interfaced for distributed
processing applications.
Reflecting on his experience, Hank Smith noted, lilt is
significant that with microprocessors you build up a group
of loyal customers. Once they use your microprocessor, they are not likely to change and use someone else's because of
their software investment. This is unlike a memory device
where once you design it, you can use anybody's. I feel
strongly that the most important thing was to get it designed
in as many places as possible. Being first with the microprocessor was much more important than with a memory device.
II

One overlooked but significant contribution by Intel is their
high-level language, PL/M, according to Smith.
lilt brings
programming to the point where anyone can learn it in a short
period. Someone who has no experience with computers can
program these systems on an increasing level starting with
the 8008, going on to the 8080 and then to the 3000 •. You
can write one program and use it on different kinds of systems
and products: you don't have to start from scratch each time,
only recompile.
II

Gordon Moore credits Smith with originating the Intellec
program development system concept that followed the use of
simulation cards for microprocessor system design.
liThe
Intellec family was developed to make it as easy as possible
to use the microprocessor family,
Smi th explained.
"We felt
it was difficult for a circuit designer to make the transition
II

-3-

to computer user, and the Intellec simplified this. It was
a new thing for a semiconductor company to produce complete
hardware systems of this kind. II
Feedback from customers told Intel that a development system
with more capability than the Intellec would be desirable.
Out of this grew the MDS, or microcomputer development system,
started in mid-1974.
liThe idea of the MDS was to extend the
development system directly into the prototype or production
system environment," according to Mike Maerz, who was involved
in the MDS design.
lilt is a single development system with
architecture flexible enough to incorporate development
capabilities in all new products. With it, we have an interface flexible enough to allow a wide variety of peripherals
to be used. For a low-cost system, a teletype could be used,
while a more sophisticated system could employ a floppy disk,
line printer or CRT terminal.
II

"The big difference between older development systems and
the MDS is that the MDS can be used without present microprocessors or future systems,
Bill Broderick, Intel's MDS
product manager pointed out.
liThe older development systems
were for a specific microprocessor. The MDS has 14 spare
card slots to accommodate future systems, and allows software
debugging through use of interactive, in-circuit emulation
(ICE) software. Also, the user has the capability to build
and modify his hardware external to the development system.
In older systems, he had to change cards within the box when
he wanted to modify his system. 1I
II

Not only did Intel pioneer the microprocessor hardware, they
also pioneered documentation support. Gordon Moore noted,
liMy view is that, in most of the aspects of the microprocessor,
being there first meant we had to do everything first. We
recognized the need for adequate documentation and have shipped
more user's manuals than we have CPU chips. No longer could
a semi manufacturer supply a two-page data sheet. With
microprocessors, lOO-page manuals are commonplace. 1I
The best analogy made by Intel president Moore for the future
of the microprocessor was a comparison with the fractional
horsepower motor. In the Industrial Revolution, the fractional
horsepower motor replaced the water wheel with ail-rt~-etts
as a source of power. Today, the average home might have 40
to 50, he said. Moore sees the home of the future as having
at least a dozen microprocessors in everything ranging from
refrigerators to stoves and electronic games.

-4-

2. RECENT DEVELOPMENTS IN THE DESIGN AND APPLICATION
OF A BIPOLAR CONTROL STORE SEQUENCER
STEVE LAU
Technical Staff Member
Signetics Corporation
Sunnyvale, California 94086
INTRODUCTION
The basic structure of a high performance Central Processing Unit (CPU) or a
"Smart" controller can be typically classified into two distinct but interactively
related functional sections. One section is generally referred to as the Processing
Section and the other the Control Section.
With the state of the art in bipolar Schottky technology, high-performance
microprocessors are designed to perform functions of the Processing Section. Due
to the limitation on pin numbers and chip size, the overall Processing Section is
partitioned into several functionally equivalent slices. In today's bipolar microprocessor market, 2-bit and 4-bit slice architecture predominates. Each architecture
type ha s its uniquenes s but, in genera l, a s lice contains a group of genera l-purpos e
registers, an accumulator, special-purpose register(s), ALU and related status flags.
All of these elements constitute the Processing Section of a CPU.
The Control Section of the CPU is more complex in design. Typically this
section includes the macro-ins truction decode logic, tes t-branch decode, microprogram sequencing logic and the control store where the microprogram resides.
Aside from the microprogram, the remaining portion of the Control Section (macro
instruction decode, test-branch decode and sequencing), does not lend itself to
efficient partitioning into vertical slices. This is due to the random nature of the
logic usually found in the Control Section. However, horizontal functional grouping
is possible. For example the macro-instruction decode and test-branch decode
logic can now be replaced by the Signetics FPLA (Field Programmable Logic Array);
the random logic traditionally needed to implement the microprogram sequencing can
now be replaced by the Signetics Control Store Sequencer; and I of course, the microprogram can be stored in a high-density PROM or ROM such as the 82S115.
I

GENERAL DESCRIPTION
The Signetics Control Store Sequencer is a low-power Schottky LSI, designed
for use in high-performance, microprogrammed systems. The basic function of this
device is to set up the microprogram address from which the microinstruction is
fetched. All microinstructions are assumed to reside in the Control Store (ROMs,
PROMs I or RAMs I in the case of Writable Control Store).
The fundamental philosophy behind the deSign of the sequencer evolved around
three points:
(1) To deSign an LSI that can handle most of the essential sequencing functions
normally required for efficient microprogramming.
(2) To design an LSI that is easy to use.
(3) To design an LSI in a 28 pin DIP and yet maintain a high addressability of
1024 words.
Additional address requirement can be easily met by providing external page

- 5 -

registers ~ which can be either entirely or partially controlled via the microprogram.
FUNCTIONAL DESCRIPTION
The Control Sequencer architecture is shown in Figure 1. The address register
is a 10-bit D-type FF which holds the current address. The register changes state
when the CLOCK is in a Low-to-High transistion (edge triggered). The address
register can be loaded with different address sources under control of the three
Address Control (AC 2 _ 0 ) lines and .one Test input line. These sources are:
All D· s for reset
Current address +1 for simple increment
Current addres s +2 for skip
10-bit branch address from outside
Stack register file output
There is a 4-level Stack Register File and a 2-bit Stack POinter, both of which
respond automatically to operations requiring a PUSH (write to Stack Register File)
or POP (read Stack Register File).
The file is organized as a 4-word-by-IO bit matrix and operates as a LIFO.
The Stack Pointer operates as an UP/down counter.
A cross section of the activities that take place within various logic elements
is shown in Figure 2. The AC2-0 and the TEST INPUT are the variables in the chart.
This chart may be used to gain a better understanding of the device so that its
capability can be fully utilized.
Following is a detailed description of all the possible functions performed by
the Control Store Sequencer. Note that the mnemonics are in parenthesis, and the
logic state is defined as TRUE = 5V and FALSE = OV:
AC2-0 = 000: TEST & SKIP (TSK)
PERFORM TEST ON "TEST INPUT": LINE
IF TEST IS
FALSE:
IF TEST IS
TRUE:

NEXT ADDR = CURRENT ADDR +1, STACK POINTER
UNCHANGED.
NEXT ADDR = CURRENT ADDR +2, i. e. SKIP NEXT
MICROINSTRUCTIONS: STACK POINTER UNCHANGED.

This function is used to facilitate transfer of control based on the result of a test
on the "Test Input" line.
AC2-0 = 001: INCREMENT (INC)
NEXT ADDR = CURRENT ADDR +1
This function is used to 'serially sequence the address register by 1. This simple
function eliminates the need for providing 10 external address lines to do a BRANCH
to next addres s •
AC2-0 = 010: BRANCH TO LOOP IF TEST CONDITION TRUE (BLT) PERFORM TEST ON
"TEST INPUT" LINE
IF TEST IS
TRUE:

NEXT ADDR

=

ADDR FROM REG FILE (POP), STACK POINTER

-6-

() ()()() () () () () () ()

AgAaA7A6AsA4A3A2A1AO

-------------,

r---EN,
()

crcr------~~

__

10

O_U_T_P_U_T~B_U_F_F_E_R__~
10

~_-~---.L.-~

( ) AC20-- DECODE
( ) AC 1
LOGIC
( ) ACO

ADDRESS REGISTER
10

()CLKo-J
VCCo-J
GNOo--J
I

+',+2 LOGIC

+2
ADDRESS MULTIPLEXER

STACK
REGISTER
FILE
2

L-oTEST
I
()

I

I

_ _ _ _ _ _ _ _ _ _ _ _ ..J

L ___ _
8g88 B7 8 6 B5 84 8 3 B 2 B 1 BO
()()()()()()()()()()

Figure 1 - Control Store Sequencer Architecture

·-7 -

FUNCTION
MNEMONIC

DESCR IPTION

AC 210

TEST

STACK

NEXT ADDRESS

STACK POINTER

TSK

TEST & SKIP

000

FALSE
TRUE

CURRENT +1
CURRENT +2

N.C.
N.C.

N.C.
N.C.

INC

INCREMENT

001

X

CURRENT +1

N.C.

N.C.

BLT

BR.A.NCH TO
LOOP IF TEST
INPUT TRUE

01 0

FALSE
TRUE

CURRENT +1
STACK REG FILE

X
POP (READ)

DECR
DECR

POP

POP STACK

011

X

STACK REG FILE

POP (READ)

DECR

8SR

BRANCH TO
SUBROUTINE
IF TEST INPUT
TRUE

100

FALSE
TRUE

N.C.
PUSH (CURR +1)

N.C.
INCR

PLP

PUSH FOR
LOOPING

10 1

X

BRT

BRANCH IF TEST
INPUT TRUE

1 10

FALSE
TRUE

RST

SET MICROPROGRAM ADDR.
OUTPUT TO ZERO

1 1 1

X

CURRENT +1
BRANCH ADDR.

I
PUSH (CURR.
ll.DDRi

INCR

CURRENT +1
BRANCH ADDR.

N.C.
N.C.

N.C.
N.C.

ALL O's

N.C.

N.C.

CURRENT +1

x = DON'T CARE
N.C. = NO CHANGE

Figure 2 - Next Address Control Function

- 8-

DECR BY 1.
IF TEST IS
FALE:

NEXT ADDR
DECR BY 1.

=

CURRENT ADDR + 1, STACK POINTER

This function is used as the la st microinstruction of a loop (assuming that the
beginning microinstruction is a PUSH FOR LOOPING AC 2 _ 0 = 101). By means of this
function, the loop is re-executed or exited depending on the result of the test on
the "TEST INPUT" line. If the test is TRUE, the loop will be re-executed by using
the address supplied by the Stack Register File. If the test is FALSE, the control
exits the loop by moving to the next address. In either case, the Stack Pointer is
kept current automatically.
AC 2 _ 0 = 011:

POP STACK (POP)

NEXT ADDR = STACK REG FILE
STACK POINTER DECREMENTED BY 1
This function is used to POP or read the Stack Register File unconditionally. It is
usually used as the last microinstruction of a subroutine where the control will be
returned to the main microprogram.
AC 2-0

= 100:

BRANCH TO SUBROUTINE IF TEST INPUT TRUE (BSR)

IF TEST IS
FALSE:
IF TEST IS
TRUE:

NEXT ADDR = CURRENT ADDR +1, NO PUSH ON STACK,
STACK POINTER UNCHANGED.
NEXT ADDRESS = BRANCH ADDRESS (B9-0), PUSH CURRENT
ADDR +1 ~ STACK REG FILE, STACK POINTER INCREMENTED
BY 1.

This function facilita tes the transfer of control based on the result of the tes t on
"TEST INPUT" line. If the test is FALSE, no branch will take place and the next
instruction will be executed; if the test is TRUE, the address register is loa ded
with the B9-0 (Branch Address) lines and, at the meantime, the (current address +1)
is written or pushed into the Stack Register File. The latter condition allows
branching to a micro-subroutine whose beginning address is supplied by B9-0 and,
t the meantime, the return address is saved in the Stack Register File.
::j

AC 2 _ 0 = 101:

PUSH FOR LOOPING (PLP)

NEXT ADDR = CURRENT ADDR +1
STACK POINTER INCR BY 1
PUSH (CURRENT ADDR)-4 STACK REG FILE
This function is generally used as the first microinstruction of a program loop. The
current address is saved in the Stack Register File.. This function works hand in
hand with the BLT function:
AC2-0 = 110: BRANCH IF TEST CONDITION TRUE (BRT)
IF TEST IS
FALSE:

NEXT ADDR

=

CURRENT ADDRESS +1.

- 9 -

IF TEST IS
TRUE:

NEXT ADDR

= 'BRANCH ADDRESS

(B g _ O).

This function is used to facilitate transfer of control based on the result of the test
on the TEST INPUT line. If the test is TRUE, the next address is supplied by the
Bg-O lines; if the test is FALSE, the control proceeds to the next address.
AC 2 _ 0

= 111:

RESET TO 0 (RST)

NEXT ADDR

= 0,

FOR RESET

This function is used to reset the address to all O·s.
ha s no bearing on the next a ddres s setup.

The state of the Bg-O lines

The following additional functions can be performed by the Sequencer, although
they are not related to the state of the AC 2 _ and TEST INPUT:
0
1. The device will power up to a known state, which is all O's. This feature
can be used to initiate the "power on reset" subroutine.
2.

When the external clock is inhibited, all internal register contents are
undisturbed. This is a means of retaining the current address (and therefore executing the current microinstructiorl) for timing delay purposes, where
the unit time is equal to the microinstruction cycle time. The clock inhibit
signal can be supplied directly by the micro-code or it could be the status
condition of certain control logic.

3.

The three state output buffers can be disabled (placed in a High-Impedance
State) when an external address source is used to access the microprogram.
This external address can be a micro-interrupt vector, which directly
accesses the starting microinstruction of the interrupt handling subroutine.
If Address 0 is to be reserved for initialization, the micro-interrupt vector
can be asserted on any address lines other than AO' such as Al A2 A3 for 8
levels of interrupts.

HOW TO DESIGN WITH THE 8X02
The 8X02 is totally compatible with all bipolar TTL logic elements. A typical
hardware setup is shown in Figure 3. This example generally represents the control
loop of a 16-bit CPU. The various major block functions shown in Figure 3 can be
described as follows:
1.

One FPLA is used to decode the macroinstruction.

2.

One FPLA is used to decode the hardware and program status condition.

3.

A multiplexer is used to channel one of eight conditions to the "Testl! input
of the 8X02. The multiplexer select control is directly supplied by the
microcode. These conditions may vary from system to system. The multiplexer approach is a simple way to accommodate the multitude of conditions
that need to be tested. Note that to force a 1 and 0 can be accomplished by
tying the inputs to 5V and OV, respectively.

4.

The 8X02 is used to sequence the microprogram.

5.

The eight 82S115 PROMS are used to implement a lK-word-by-32 bit micro-10-

-

.....

--

--

~

CE

;.\0

AS

<

OnI Ol;;

0]1 °24

81S 115

~

---.
AU
Micro Interrupt
Vector (A1 A3)-+---+-----~

...

H>

~

~

82S 115

H2S1

82S 115

~

82S115
~

°15 0 8

°23 °16

°31 °24
CE

~

~

0']

A8

82S 115

~

AO

- - . EN
CO
SEQUENCER

~

8X02

l[Sl
-..,.......,

-

AC2 " ' - - - - - -.. -CLK

_ _F.,:7.=::::::::=..,..F 0

f

th-_-----------------

....
~------74S08

F'l __--"-_ _ F 0

FPLA

FPLA
82S100

825100

t

MACROINSTRUCTION
(16-BlTl

1

15

---t..----

8 TO 1 MUX
745151
I0

HARDWARE/PROG

STATUS

~

U

o.-.J

U
(/)

>-

(/)

Figure 3 - 8X02 as Part of Control Loop Configuration
-11-

00

~

ASI
Ag

00

~

~

825 11~

°7

°B

°15

82S115

program. Additional PROMS may be added as required. The address
output signals (Ag - AO) of the 8X02 can drive up to SMA.
To control the SX02 as it is configured in Figure 3, the firmware basically has
to provide fields for:
AC2-0:

3 bits for address control

ACK INH:

1 bit for clock inhibit

S2-0:

3 bits for multiplexer select. In a simpler design, a I-bit field
connected directly to the "TEST" input pin of 8X02 may satisfy the
design requirement •.

MICROPROGRAMMING CONSIDERATIONS

t~ND

EXAMPLES

During the design phase of the firmware (or microprogram), the firmware
engineer may find it necessary to allocate certain addresses in the microprogram
to handle specific functions which are hardware dependent. For example:
(1)

One address each may be assigned as the entry point for subroutine
handling, depending on the way that the interrupt vector is connected to
the address bus (Ag-O).

(2)

Address 0 may be assigned to handle system initialization functions.

(3)

A convenient number of addresses may be allocated to take care of memory
fetch functions as well as sampling (enabling) interrupts.

-12-

Example: Test and Skip Programming Technique (Figure 4)
(1)

The TSK instruction is used to facilitate transfer of controls.

(2)

When executing the TSK ins truction, the "Test" input is check.ed and, if
the 'TEST is TRUE, skip the next instruction and go to address (X+3). If
the TEST is FALSE, go to the next address (X+2).

(3)

The RST instruction is used to bring the control to address 0 where micfointerrupts can be enabled.

NOTE: Addresses are shown in parenthesis and instructions are shown inside the
blocks.

(Xl

T
.F

(X+3)

Figure 4 - Te~t and Skip Programming Technique Exarnple
-13-

Example: Conditional Branching Technique (Figure 5)
(1)

N-WAY BRANCH within the same 1024 word page is possible.

(2) When the "Test" condition is true, the branch will be taken. The
branch address is supplied via Bg - O• In the example it is (Y).
(3)

When the "Test" condition is FALSE, the control will proceed to the
next instruction at address (X+2).

NOTE: Addresses are shown in parenthesis and instructions are shown inside
the blocks.

(X)

T
F

(X+2)

(V)

Figure 5 - Conditional Branching Technique Example

- 14-

Example: Subroutine Nesting Technique (Figure 6)
In this subroutine the beginning ad~ress (Y) must be presented to Bg_O inputs
during the BSR instruction. If the BRANCH is taken, the return address (X+2)
will be saved in the Stack Register File. When the subroutine is done, issue
a POP instruction to return the main program to address (X+2).
NOTE: Addresses are shown in parenthesis and instructions are shown inside
the blocks.

T

(X+2)

(Y)

(Y+11

(Y+T)

Figure 6 - Subroutine Nesting Technique Example

- 15-

Example: Program Looping Technique (Figure 7)
(1)

The first instruction of the LOOP must be a PLP. During the execution of a
PLP I the sequencer pushes the current address (X) into the Stack Register File.

(2)

The last instruction of the LOOP must be a BLT instruction. When the BLT is
executed I the sequencer checks the "TEST input which is normally connected
to a loop count overflow signal., If the loop counter does not overflow I the loop
will be re -executed. If the loop counter does overflow I the next instruction
will be automatically accessed and executed.
II

NOTE: Addresses are shown in parenthesis and instructions are shown inside the blocks.

(X)

(X+ 1)

(X+2)

(X+N)

(X+N+1)

Figure 7 - Program Looping Technique Example
- 16-

Example:

4-Level Subroutine Nesting Technique (Figure 8)

When applying the subroutine nesting technique, the following can be 'Used as a
guideline:
(1)

Use the BSR instructioll to branch to the subroutine if the "TEST
the sequencer if HIGH.

(2)

Use a POP instruction to return from a subroutine.

(3)

Caution must be exercised to avoid stack overflow or underflow.

(4)

A lO-Bit address (beginning address of subroutine) must be supplied to the
Bg_O during BSR instruction.

II

input of·

NOTE: Addresses are shown in parenthesis and the instructions inside blocks
of flowchart.

T

(M)

Subroutine
Level #1

INC

T

(M+2)

I

(W)

Subroutine
Level #2

INC

I

I

I
(M+X)

T

Subroutine
Level *3

(W+2)

I
I

I
(W+T)

(Y+2)

Subroutine
Level #4

I

I
I
I

(Y+K)

Figure 8 - 4-Level Subroutine Ne!ting Technique Example
- 17-

SINGLE CHIP MICROPROCESSOR
WITH MINICOMPUTER PERFORMANCE
BY: JOHN D. BRYANT
Microprocessor Systems Engineer
Texas Instruments Incorporated
Houston, Texas

3.

INTRODUCTION
As technology keeps advancing, integrated circuits with lower and
lower cost/performance ratios continue to emerge. The introduction
of the TMS 9900 microprocessor by TI maintains this trend by offering the performance of a minicomputer at the cost of a single chip.
The TMS 9900 is a full 16 bit central processor utilizing advanced
high speed N channel MOS technology, and is system engineered to provide the most cost-effective solution to a wide variety of applications.
The philosophy which led to the 9900 was to provide a complete family
of total software compatible computers. Current family members include the TMS 9900 single chip microprocessor, the 990/4 microcomputer
on a board, and the 990/10 high-performance TTL minicomputer. A program written for one family member will run without reassembly on any
other. Thus, the family can provide a single solution to a wide range
of applications and reduce significantly the expense involved with
training and maintenance. The family concept also lends itself to the
efficient design of hierarchical and distributed processing systems.
PRODUCT SIGNIFICANCE
Advanced Features
The TMS 9900 offers several advancements over previously announced
components. These include:
1)

Single Chip 16 Bit CPU
A full 16 bit architecture that incorporates the power and
efficiency of a 16 bit instruction set on a single chip.

2)

Minicomputer Instruction Set
The instruction set contains 69 basic instructions which include
some previously available only on minicomputers (for example,
multiply and divide).

3)

Memory to Memory Architecture
This advanced architecture provides 16 general purpose registers
(accumulators, index registers, etc.) while maintaining the flexibility of fast and efficient context switching.

4)

17 CPU Vectored Interrupts
The interrupt structure is designed to allow the interface of 2
special purpose interrupts (RESET and LOAD) and up to 15 user
specified interrupts with minimal external circuitry.
-18-

5)

Simplified Bus Structure
I/O data are transferred on dedicated I/O buses using standard TTL
interfaces. The memory data and address buses are separate and
need no external demu1tiplexing circuitry.

6)

Standard Peripherals
All signals (excluding clocks) are completely TTL compatible. The
architecture is configured to interface directly with standard memories and TTL.

Target Applications
The applications for which these advanced features will be significant
are:
1)

Interrupt Driven Systems
The TMS 9900 offers very fast context switching and efficient interrupt handling for the design of high performance/low overhead systems.

2)

Limited Memory Systems
The power and efficiency of the 16 bit architecture and instruction
set tend to require fewer memory bits to perform a given function.

3)

High Throughput Systems
The powerful instruction set coupled with the fast context switch
enables the processor to achieve high speed task operation with a
3 MHZ clock.

4)

Control Applications
The bit-oriented I/O system allows the implementation of versatile
control systems with minimal program and interface hardware.

5)

8 Bits or Greater Word Systems
The 16 bit architecture along with the comprehensive subset of
byte instructions insures that the 9900 will operate efficiently
in 8 - 16 bit data applications (A/D, D/A, Control, Communications).

In other words, the 9900 is designed to perform effectively in a wide
variety of applications while minimizing program and hardware overhead.
SYSTEM ARCHITECTURE
Machine Architecture
The machine architecture is shown in Figure 1 compared to a currently
popular 8 bit microprocessor (8080). The 8080 employs a conventional
stack architecture with an 8 bit parallel arithmetic unit, a status flag
register, a 16 bit program counter register (PC), a 16 bit stack pointer
-19-

9900

MACHINE ARCHITECTURE
TMS 9900

TMS 8080
CPU

CPU

MEMORY

REGISTERS

MEMORY

PC

PROGRAM
DATA

REGISTERS
PROGRAM
DATA

WP

PC
"-

I
l\.)

o
I

L

l

ALU
FLAGS

II

I,

ALU

0

,I

STATUS

"

~~-------------~PROGRAM AND DATA
REGISTERS IN CPU
PACKAGE

0
~

"

PROGRAM AND DATA
REGISTERS IN MEMORY

v

NUMBER OF WORKSPACE REGISTERS
LIMITED ONLY BY MEMORY SIZE

v PROVIDES FAST CONTEXT SWITCHING

FIGURE 1

register (SP), and a set of program data registers. The operating
program and data are stored in external memory. The TMS 9900, on the
other hand, uses an architecture commonly called memory-to-memory. In
the processor are a 16 bit arithmetic unit, a status flag register, a
PC, and a 16 bit register (WP) that defines a 16 word location in external memory called the workspace. The workspace registers are the
program data registers and are stored in the external memory along
with the operating program and data. Two advantages of this architecture are (1) the number of workspace registers is limited only by the
memory size and (2) since there are no program data registers on the
chip that have to be stored, context switch~ng is very fast.
A block diagram of the 9900 is shown in Figure 2. Interface to the
outside world consists of the 16 bit bidirectional memory data bus
(00-015), the 15 bit address bus (AO-A14), the I/O data bus (CRUOUT,
CRUIN), interrupt inputs (INTREQ, ICO-IC3), miscellaneous control
signals, and power and clocks. Internally the circuit contains the
three user accessible registers (PC, WP, and STATUS) along with six
additional housekeeping registers. The ALU is a full 16 bit parallel
arithmetic unit, and all internal buses are full 16 bit parallel buses.
The control logic consists of a microsequence ROM controller employing
8.5K bits which is not user microprogrammab1e.
Memory Organization
All memory addresses are 16 bits and specify the location of a byte of
data. The memory is organized into 16 bit words (2 bytes/word), and
thus the 16 bit address can directly specify 64K bytes or 32K words.
Since each memory access results in 2 bytes, the least significant bit
of the address is not needed outside since it merely specifies which
byte in the word is being requested. Therefore, the address bus is
only 15 bits wide. The sixteenth bit (LSB) is maintained internally
by the processor so that if a byte operation is performed, the unspecified byte will remain untouched.
The memory interface is designed to interface directly with standard
RAM's and ROM's, and the data bus is not multiplexed to simplify system design. READY/WAIT control signals are available to slow down the
processor to mate with any memory access time and allow the use of
mixed memory speeds or slow memory (at 3 MHZ the processor requires
500 ns memories for full speed operation). HOLD/HOLD ACKNOWLEDGE is
also provided to simplify the design of asynchronous DMA systems.
An example of a small memory system is shown in Figure 3. This system
uses lK words of ROM and 256 words of RAM. Note that READY is held
high since the TMS 4700 and TMS 4042 memories are fast enough to run
with the processor at full speed. All signals are of the right polarity
and magnitude to interface directly with the memory system, and even
the inverter shown on CS for the 4042 may not be required, depending on
how the memory map is defined.
Context Switching
A context switch can be defined as a change in the program environment
due to either an external (interrupt) or internal (subroutine call or
XOP sequence) stimulus. This change can be effected by storing all
-21-

9900

CPU BLOCK DIAGRAM
r
r

,

}~~

~

--.

HOLDA
WE
WAIT

~

....

DBIN
IAQ ..-

HOLD

...

LOAD

..

READY
MEMEN . . .
RESET
CRUCLK-..-

CLOCK
4

/"'0).

~~
ISTATUS REGISTERl

~I

C
0

~

-V-

L;=>~

ALU

A

0

'III::

MEMORY ADDRE~S
REGISTER

PROGRAM COUNTER
WORKSPACE POINTER

0

rCONTROL ROM

~

"'~

INTERRUPT
LOGIC

TI
T2

rINSTRUCTION REGISTERI

~

~

IC MUX I

~~

~

"
'7

I
N
N
I

ADDRESS BUS
(AO-A14)

INTREQ (ICO-IC3)
I
I I
Ir r

"'

~

B

F

l.

""'"

~7
D MUX I

CONTROL

..

I

LOGIC

ISHIFT CtuNTER\

G

,0

1

~

r

SOURCE
DATA REGISTER

rSH IFT REG ISTER I

J
~J-

~

(00-015) DATA BUS

CRUIN

FIGURE 2

CRUOUT

9900

SMALL MEMORY SYSTEM
~

./

ADDRESS BUS

AO-A14
WE
DBIN

l

)

~7

/ DBIN WE ADDR

-;

CS

I

/

I

I

/

[\J

w
I

TMS 9900
READY

CPU

,

/cs

~

~

1

I

/

~/

I

ADDR
J

TMS 4700
1KX8 ROM

DATA

TMS 4042
256X4 RAM

DATA
II

~

~

00-015
DATA BUS
1 KX16 ROM

FIGURE 3

256~16

RAM

~1I

lI

V

information contained in the processor relative to the active program before the change and replacing with any needed information for
the new active- program. The return will then take place when the
stored information is reloaded into the processor. For example, to
service an interrupt the TMS 9900 must store its 3 internal registers
(PC, WP, STATUS) and load two (PC, WP). The return is then accomplished
by reloading the three stored registers. The time required to perform this function is pure overhead and limits the interrupt service
capability of the processor. Figure 4 shows the amount of time required for interrupt overhead for four current processors, and Figure
5 illustrates the effect of the required times. The bar charts represent the number of context changes per second that would completely
saturate the processor. For example, the TMS 9900 saturates at 80K
and the 8080 at 19K. The line at 15360 is representative of an
application using the processor as a data concentrator for 16 9600
baud lines. The percentages represent the amount of processing time
used as pure overhead. As the chart illustrates, the TMS 9900 offers a
significant advantage in applications of this type.
Interrupt Structure
The TMS 9900 offers 17 prioritized interrupt levels, and the interrupt sequence includes an automatic register save and load of the PC
and WP with vectors from memory. The two highest priority interrupts
are the RESET pin and the LOAD pin, and neither are maskable. The
remaining 15 interrupts are interfaced with 5 interrupt input pins
(INTREQ, ICO-IC3) and are masked by a 4 bit code stored in the status
register. The mask is a IIfence" mask in that all interrupts above it
are allowed, and all below are not. The mask is automatically changed
whenever an interrupt is serviced such that only higher priority interrupts can be accepted. The interface is very simple (see .Figure 6),
and has been designed to require only standard TTL circuits.
I/O Interface
I/O data is transferred by the TMS 9900 serially using 3 dedicated
lines: CRUIN is a serial input line, CRUOUT is a serial output line,
and CRUCLK is an output synchronizing signal. The data is addressed
by bit using 12 bits of the address bus. The I/O instructions can
specify that any number of bits from 1 to 16 be transferred, and several data addressing modes can be used to minimize the software overhead involved. Parallel to parallel data transfers are very easily
implemented using standard TTL components as shown in Figure 7 where
an 8 bit input port and an 8 bit output port are implemented, and
addressing by bit gives an automatic interface to single or odd bit
numbers.
Instruction Set
Perhaps the most significant feature offered by the TMS 9900 is the
instruction set. The instruction set is a complete minicomputer
instruction set containing 69 16 bit instructions including multiply
and divide. The instructions can specify two separate operands, each
of which can be specified independently by several addressing modes.
The processor allows 7 different addressing modes, and sub-groups of
instructions are oriented toward words, bytes, and bits to maintain
-24-

9900

INTERRUPT OVERHEAD
TMS 9900

.12.61"5
864.6

6800
12610
~

TMS 8080
22
I
I

20

5

PACE

'/,

'/.

~

111!II!illlllllllllllllllllllllllllllllllllllllllllll ----

14

40

40

)
TIME

FIGURE 4

INTERRUPT SEQUENCE

IDIill1

SAVE REGISTERS

~

RESTORE REGISTERS

~

RETURN

6

'///////,

I\.)

V1

D,

52.5 J1.s

~

INTERRUPT SUBROUTINE

106 J1.s
~
~"''''':
12

9900

SYSTEM CAPACITY

C

TMS

°c
N H
T
E
X
T

A
N
G
E

S

FOR CONTEXT SWITCHING OVERHEAD

80K

80 -

9900
70

-

60 -

(COOlS/SEC)

50 I

45K
6800

tv
0"1

I

40 -

30

-

20 -

19%
~-

.. ~

--

34%
I--

-

-

~-

-

~-

10 -

800/0
~

-

19K
.-..

TMS

8080

FIGURE 5

170%

15360
- - - - - - --9K
PACE

9900

INTERRUPT STRUCTURE

o SEVENTEEN PRIORITIZED INTERRUPTS ARE AVAILABLE
o HIGHEST PRIORITY INTERRUPTS ARE RESET AND LOAD FOLLOWED BY
15 AVAILABLE FOR EXTERNAL USE

o EACH INTERRUPT HAS A TWO WORD VECTOR STORED IN MEMORY

o

INTERRUPT INTERFACE:

I

rv
.......J
I

1 INTERRUPT

/

/
INT~

REO.

HARD\VAHE::::;:>IN TE R R U PT
CODE

8-15 INTERRUPTS

2-8 INTERRUPTS

8

TMS

TiviS

INTE?RUPT

9900

)

""------/

9900

REOUESTS
.. ---PRIORITY
ENCODER

FIGURE 6

i5

•

..

TMS

I r--~TERRLJ PT
REOUESTS

9900
L . -_ _

PRIORITY
ENCODEH

QUAD
AND

9900

8 BIT 1/0 INTERFACE LOG'IC
MEMORY

TMS 9900
CPU

A12-A14
I
N

00
I

ABC

AO A1 A2

SN74LS251

SN74LS259

8-1 MULTIPLEXER

8-BIT ADDRESSABLE

LATCH

o
8 INPUT
LINES

8 OUTPUT
LINES

FIGURE 7

effectiveness in all applications.
A complete summary of the instructions is shown in Figure 8. The 16
instructions in the arithmetic sub-group include the instructions to
add (for example) words, bytes, or immediate data, and to increment or
decrement by 1 or 2, depending on whether one is operating on words or
on bytes. The program control (20), data control (14) and logical (6)
sub-groups are similarly comprehensive. The shifts (4) allow left and
right, arithmetic circular and logical, and can specify shifts of from
1 to 16 locations. The I/O (5) instructions are used to communicate
with the I/O interface, and the external (4) instructions do nothing
except r.ause a unique code to be output to the outside world. The
external instructions can be used to initiate external actions.
The seven addressing modes allowed by the TMS 9900 are:
1)
2)
3)
4)
5)
6)
7)

Work Space Register
Indirect
Indirect with Auto Increment
Indexed
Symbolic (Direct)
I mm e d i ate
Program Counter Relative

Application of this instruction set has been shown to result in fewer
instructions than comparable 8 bit architectures, and in fact to result
in fewer memory bits for program storage. This in turn leads to a
significant savings in design cycle cost due to:
1)
2)
3)

Less programming time
Simplified debug
Lower hardware cost (fewer bits)
COST/PERFORMANCE ANALYSIS

Benchmark Evaluation
Figure 9 shows a comparison of the TMS 9900 with the PACE system, the
8080, and the 6800 for several different programs. The programs included are:
1)

I/O Handler
The processor accepts an interrupt, inputs a character, and checks
to see if the character is an end-of-line character. If it is, the
program jumps to another routine; if not, the character is output
to a CRT for display and control is returned to the main program.

2)

Character Search
A forty character table is searched through for a specified character, and the address is returned. If the character is not found,
a zero address is returned.

3)

Computed Go To
This routine tests a control byte which has one. true bit.
-29-

The

INSTRUCTION SET SUMMARY
69 INSTRUCTIONS

9900

.ARITHMETIC (16)
ADD (W, 8, Imm)j SUB (W, B), COMPARE (W, B, Imm)j INCR (1,2), DECR (1,2),
ASS, NEG, MPY DIV
j

.PROGRAM CONTROL (20)
BRANCH (LINK, LOAD WP), JUMP JUMP CONDITIONAL (12) RETURN, IDLE,
EXECUTE, EXTENDED OPERATION
j

-DATA CONTROL (14)
f\~OVE

I
W

(W, B) LOAD (Imm5 WP, ST)! STORE (ST, WP), SWAP BYTES, CLR, SETO,
SOC (W, BL SZC (W: 8)

o
I

.LOGICAL (6)
AND I, OR

I~

INV,

cae

l

CZC, XOR

-SHIFTS (4)
SRA SRL SRC, SLA
I

~ I/O

j

(5)

LOCR, STCR,TB, SBO, SBZ

-EXTERNAL (4)
RESET, CKON,CKOFF, LREX

FIGURE 8

9900

BENCHMARK EVALUATION
PROGRAM MEMORY

ASSEMBLER STATEMENTS

REQUIREMENTS (BYTES)

I
W

9900

PACE

8080

6800

9900

\/0 HANDLER

32

44

34

23

9

CHARACTER SEARCH

22

24

19

18

COMF'UTED GO TO

12

12

17

Ar\l - BN

20

26

SHIFT RIGHT 5 BITS

10

AN - BN

EXECUTION TIME (-"SEC)

8080

6800

9900

PACE

8080

6800

18

17

10

76

150

73

54

8

10

12

8

655

1962

743

886

18

5

5

11

9

99

352

155

162

:i6

41

6

10

21

20

513

1740

1155

1920

8

22

21

3

3

15

10

22

58

167

91

20

26

30

32

6

10

15

14

513

1740

795

1380

MOVE BLOCK

14

18

16

15

4

9

9

8

7

27

19

19 .

TOTALS

130

158

174

168

41

65

100

79

6029

31G7

PACE

j-I

I

=c-

eN

= CN

(16)

(8)

FIGURE 9

1885

4512

position of the true bit determines which one of the 8 table
vectors is used for control transfer.
4)

Vector Addition
Two twenty-word vectors are added to produce a third twenty-word
vector. Both eight and sixteen bit precision routines are shown.

5)

Shift Right 5 Bits
A l6-bit word is shifted right by 5 places with zeros being
shifted in.

6)

Move Block
A block of N characters is moved to another location in memory.
Both blocks can be anywhere in memory.
The comparison includes program memory requirements (in bytes),
the number of assembler statements needed, and the execution times
required to perform the various routines. Since all of the routines
are independent, the results can be summed to give an indication of
the processors' comparitive performances. As can be seen from the
sums, the TMS 9900 offers significant advantages in all three areas.

Total System Costs
In order to analyze system costs, they have been broken down into five
areas as shown in Figure 10 and compared with a typical 8-bit system.
1)

Memory Costs
Memory costs relate directly to program memory requirements, and
the benchmark analysis has shown that a 30% savings could be realized by using the TMS 9900.

2)

Interrupt Interface
The TMS 9900 interrupt structure requires a minimal amount of standard TTL as opposed to complex or custom circuits.

3)

I/O Interface
The dedicated I/O interface used by the TMS 9900 also allows the
use of low-cost standard TTL.

4)

Program Development
Program development can be related to the number of assembler
statements required to perform the function. The benchmark analysis indicated that use of the TMS 9900 would allow significant
savings in this area.

5)

CPU and Support
The cost of the TMS 9900 chip itself will initially be more
expensive due to the relative positions on the learning curve.
-32-

9900

RELATIVE OVERALL SYSTEM COSTS
TMS 9900 AND 8-BIT MICROPROCESSORS

2.0

8-BIT

X

8-BIT

t-

en

8

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MEMORY

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RELATIVE MEMORY
SIZE

1.0

INTERRUPTS
I/O

MINIMUi'v1

2.0

6.0

8

16

MODEST

LARGE

FIGURE 11

AND SUPPORT

4.

A MICROPROCESSOR DESIGNED WITH THE USER IN MIND
WILLIAM E. WICKES
Manager, Microprocessor Developments
Electronic Arrays, Inc.
Mountain View, California

January 22, 1976

Electronic Arrays is in development with the EA9002 MPU, a high speed 8-bit
parallel microprocessor designed primarily as a utility real time controller and
data processor. It has been carefully conceived and engineered to fill a gap in the
marketplace for a stand-alone, unbundled MPU not satisfied by the current proliferation of microprocessor products. The EA 9002, as a result of full TT L
compatibility, allows the user to select memory and supporting peripheral I/O
components best suited to his individual application. Furthermore, the incorporation of a 64 byte (64 x 8) scratch pad RAM within the MPU will allow many
system applications to be in'lplemented without the need for external RAM
components.
The EA9002 represents the first of what may be considered a new breed of
speciality microprocessor products in that it is a stand-alone MPU with a clearly
defined and unambiguous instruction set. This simplified instruction set along
with an easily understood internal architecture and simplified approach to timing
will accelerate product comprehension and software development time. Many
of its outstanding features and attributes are depicted in the attached illustrations.
The MPU architecture, speed of execution and instruction set represents a subtle
compromise between MOS/LSI logic, circuit and process technology. The internal
64 byte scratch memory is independent of external memory address and thus
provides for rapid data manipulation. The eight 12-bit general purpose registers
can be readily utilized as auxiliary accumulators, data pointers or indexing
registers. They provide the capability of pointing to data anywhere within the
range of the 12 -bit address with one cycle time. The seven level 12 bit subroutine
stack simplifies program control by providing automatic storage of current
address location when servicing a subroutine. Internal flags, including an
accumulator zero flag (A), are adequate for control of various modes of operation
as well as bit testing. External control signals, including interrupt, have been
provided to achieve maximum flexibility of selection of external components with
minimum external discrete component requirements. The single phase clock
input and +5V power supply further aid in reducing overall systems cost.
The 55 basic instructions decoded by the EA 9002 MPU have been organized for
ease of understanding while providing complete control capability. In addition
to normal address and data control instructions, a hard wired packed BCD
arithmetic mode with automatic decimal correction is included. This simplifies
the implementation of decimal arithmetic algorithms often required in even the
most minimal systems.
Minimum system configurations can be as simple as one EA9002 MPU, one EA
4700 1K x 8 ROM and two MSI devices for 8 bit parallel input output ports.
Expanded versions can be readily achieved by adding more ROM, RAM and I/O
devices. A unique wait! sync input output control pin allows the user not only to
synchronize the MPU with slow peripheral devices and suspend operation, but
also provides a synchronizing pulse at the end of each instruction execution cycle.
A further example of a minimum system configuration is illustrated utilizing
Motorola's MC6820 PIA. This is by no means the limit to compatible smart
peripherals. The EA9002 easily interfaces with many devices utilizing 8 bit TT L
compatible bus structures. It is an interesting evolution in microprocessor

-36-

developments that now that the industry has achieved TT L compatibility in MaS
products the user is able to mix and match those components from individual
suppliers best suited to his need, whether it is that of a sophisticated communications interface or a simple data interface.
The instruction set utilizes all possible combinations within the 8 bit op code as
illustrated in the op code map. There are no undefined codes. There are 14 two
byte instructions where the second byte consists of either extended address
information or an 8 bit literal with the one exception being the two byte DLY
(De lay) instruction. A 11 other instructions are defined by a single byte of instruction code. A generous distribution of instructions are allocated to operations
utilizing one of the eight general purpose registers. An individual register is
designated by the lower 3 bits of the code providing command and register identification with one byte. The instruction set and definition have been chosen with
the logic engineer in mind as opposed to those systems that can only be understood
and programmed by large computer programmers.
Relating individual instruction to the internal architecture of the MPU is straightforward. Data can be input or output over the 8 bit data bus to either the
accumulator or one of the 8 general purpose registers. Arithmetic operations
(binary or BCD) can be carried out between the accumulator and a designated
general purpose register or a designated location in scratch.
Data within the accumulator can be rotated right or left, thru carry or no, for
fast manipulation or test. Automatic jump on all zero or all 1 state within a
designated general purpose register simplifies program generation and control.
Timing for each instruction execution is straightforward and consistent. Write
the code and count the MPU cycle for a program execution without confusion or
ambiguity. Every MPU cycle is the same, regardless of whether it is an internal
operation or a data transfer. All peripherals are treated as memory locations,
therefore, instructions and/or data can be obtained from any external device.
A very simple but typical programming example illustrates the advantages
inherent in the EA9002 over competitive products. Assume the need is to implement a real time controller which receives a 16 byte string (could be any length
up to 63) of data from an external source. As a simplification it is assumed the
data is available for transfer to the scratch at the rate specified by the 9002
software. If not, the WAIT input could be used for synchronization or the interrupt
could be used and this whole routine becomes part of an interrupt service routine.
However, for this example, the DOS (Data Out Strobe) is used to acknowledge
receipt of data and outputs the received data for confirmation and error checking
if desired. Thus, each time the DOS occurs, the external circuits will input a
new byte of data. This example may relate to the input of information from a
high speed A /D converter for purposes of performing a subsequent mathematical
routine on the data block. Maybe the need is to compute a standard deviation.
Maybe the data is from sensors in a machine or plant control environment where
an alarm condition or control condition is to be tested or used for subsequent
operations.
Designating address bit 11 true as the I/O address (bit 11 false is the ROM
address location) simplifies address formating, decoding and control. General
purpose register 5 is chosen to control locations within scratch memory where
the incoming data is to be stored. General purpose register 5 is also chosen
as the string length counter (in this case it is 16) as well. This allows one
register to serve two purposes. General purpose register 4 is used to store
the address of the I/O port from which data is to be received.

-37-

The sequence of instructions follows a normal pattern of events. That is, the
accumulator is loaded with the page address of the I/O (in this case it is 08 Hex)
which is then m.oved to page register 4. Next the lower 8 bits of register 4 is
. loaded with all O's since the complete I/O address is 800 Hex. Register 5 is then
loaded with the string length (10 Hex) which also serves as pointer to scratch
memory where the data is to be stored. Initilization is now complete and the
program is written to execute a loop consisting of fetching the data from I/O to
accumulator, transferring data to scratch memory, generating a DOS strobe
for acknowledgement, decrementing the string length and scratch m.emory pointer
and, finally, jumping back to fetch the next byte of data.
It can be seen that this particular routine will allow the input of a byte of data
every lOll s or a 100KHz byte transfer rate.
Com.paring an input routine such as this with an Intel 8080 or Motorola 6800
quickly illustrates the superior speed and programming power of the EA 9002.
The EA9002 is schedule for sam.pling early this year with production by midyear. The descriptive brochure is available with the Users Manual soon to
follow. EA currently has excellent ROM and RAM supporting products and a
programmable keyboard encoder circuit available. A macroassembler is on
NCSS timesharing service and applications engineering is available to support
systems designs.
A stand alone systems emulator "EASE" (Electronic Arrays Systems Emulator)
is in development to be available in the 2nd quarter. "DEVELOP YOUR
PROGRAMS WITH EASE."
It is not too early to review and consider this new microprocessor for product

development programs. Review your old products for possible cost reductions.
Review your new products for enhanced capabilities.

-38-

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A New Microprocessor - Why?
EA Feels There is a need for a stand alone controllertype product wh ich :

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•
•
•
•

Reduces systems costs
Offers unbundled MPU
Easy to understand and program
Interfaces with readily available TTL
components

Many real time controllers do not need computer
type sophistication.

FIGURE 2

How Does This New Product
Reduce Costs?
I

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1-'I

1 Chip 8-Bit Fast Parallel Processor
On-Board 64 Byte RAM
Single +5V Power Supply
28 Pin Package
User Can Select Lowest Cost ROM, RAM,
and Smart Peripherals
Minimizes Software Development Time

FIGURE 3

OK ,- What Is It?
A 1 Chip 8 Bit Parallel MPU with 64 Byte Scratch
·o:··:!::::::....:::: ..::·O::::::::·O::::::::*::;f~~:

...?::.•::.:.o;.~:::::~$::::

~:::.*:

~ff: CARRY FLAG

RESET
RES
INTERRUPT

C
D

~ER:~~~

i.

:~~ DECIMAL MODE FLAG

INT
~~: INTERRUPT FLAG

WAIT/SYNC

i$f.

WAS
DATA IN STROBE
DIS
DA T A OUT STROBE
DOS

II'

ACCUMULATOR FLAG

..-._A_-t~r:::;;:fl
;. HALF-CARRY FLAG

---H

8

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ACCUMULATOR
8 BITS

8

DO- D7
DATA INPUT/OUTPUT

AOO· All
ADDRESS OUTPUT

FAST - COMPACT - EFFICIENT
FOR REAL TIME CONTROLLER & INSTRUMENTATION APPLICATIONS

FIGURE 4

Look At These Features

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64 Byte (512 Bit) Internal RAM
8 Bit Parallel I/O Data Bus
12 Bit Parallel Address Bus
8 12-Bit General Purpose Registers
7 Level Internal Subroutine Stack
Interrupt Input
Wait Input Control
Instruction Complete Sync Output
Binary or BCD Arithmetic
2/ls Instruction Execution Time
Simple Timing Requirements

FIGURE 5

What About Instruction Power?

I

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55 Basic Instructions
Add or Subtract in Binary or Packed BCD
8 GP Registers for Operand Addressing
or Data Handling
Input/Output Directly to Accumulator
or GP Registers
Scratch Memory I ndependent of External RAM
Jump Conditionally Anywhere Within a Page
Jump Unconditionally Anywhere
Wait on Slow Devices
Walk Across Page Boundaries

FIGURE 6

Excited !!
Then Sit Under This 9002 Controller
& Get Cooled Off
DOS
SOLENOID

ROM

FF

4700
9002
I

MPU

~

U1

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INTERRUPT
1. MPU in an Idle (Loop) Mode Until Interrupted
By Sensor
2. Interrupt Routine Toggles FF which Drives
Solenoid and Dumps Ice on Excited Engineer
3. Routine Resets FF and Ice Bucket, Inhibiting
Interrupt for 1 Minute
4. If Interrupt Still Present-Dumps More Ice

FIGURE 7

A Minimum System

_••••••••-.-.---.All
ADDRESS BUS

INT +-

r-

STROBE

JIAO-A9

MPU
I

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ms~~
1K X 8

EA 9002

IN

,

(j)

I

,'"__________1.'______..-

~1f.,. 8.-"'~

DATA BUS

UTILIZING INTEL MSI TTL DEVICES

FIGURE 8

8212

J

OUT

A Minimum System

12-

ADDRESS BUS
All

AO - All

MPU
EA 9002

INT
AO - AIO

~
00- 07

~~~ ~f:I:!1.8"~PAO-PA7
~~

~~~

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6820

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DATA BUS

UTILIZING MOTOROLA'S PIA

USE WHATEVER PERIPHERAL IS MOST
COST EFFECTIVE FOR YOUR APPLICATION

FIGURE 9

8

PSO - PB7

Instruction Set
o
0

DLY*

3

5

4

6

1

2

J- -

CONDITIONAL JUMPS*

4 LSB
8

7

9

A

B

C

E

D

CSA LAI* DSI

CPA

1

JUN* -UNCONDITIONALLY

2

JSR* -TO SUBROUTINE

3

IRJ* -INCREMENT

DRJ* -DECREMENT

4

XCH -EXCHANGE

CAP -ACC TO PAGE

5

INP -INPUT

OUT -OUT

6

LRI* -LOAD IMMEDIATE

JIN -INDIRECT

:8

INR -INCREMENT

DCR -DECREMENT

ADD-ADD

SUB -SUBTRACT

~

9

AND-AND

I~R

I

A

X~R

B

CAR -ACC

C

ADS -ADD SCRATCH

SUS -SUB SCRATCH

D

RDS -READ SCRATCH

WRS-WRITE SCRATCH

E

LRN - LOAD REG.

SRN -STORE REG.

~7

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F

CLC

ENI

-INC. OR

CMP-COMPARE

-EX. OR
~

F

REG.

CRA-REG

~

ACC

SECICLBICMCIIACIDACICLAICMA RALIRARIRLCIRRC SED SEB

RET NOP

*Two Byte Instructions

EASY TO LEARN & UNDERSTAND ALL POSSIBLE CODES UTILIZED

FIGURE 10

Think Logically
Input/Output

ALU-GP Registers
SUB
ICPR
CMP
CRA
CPA

INP
OUT
LAI*

ADD
AND
XC/}R
CAR
CAP
XCH

ALU
lAC
DAC
CMA

Address Control
I

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JVN*
JSR*
JIN

J--*
RET

RAR
RRC
RAL
RLC

ALU-Scratch
ACCUMULATOR
8 BITS

GP Registers
INR
OCR

LRN
SRN
LRI*

IRJ*
DRJ*

M iscell aneous
Set & Clear Flags

Nap
DLY
00- 0 7
OATA INPUl/OUlPUl

AOO - All
ADDRESS OUTPUl

FIGURE 11

ADS
WRS

SUS
RDS

Timing
.......: . . . . . - - - - - - - 1 MPU CYCLE

---------~

M1

T1

T2

T3

T4

EXTERNAL

ClK
AO-A11

PROGRAM COUNTER

GP REGISTER

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00-07

INSTRUCTION IN

SYNC

SIMPLE - CONSISTENT
FIGURE 12

DATA OUT

T1

Program ExampleInput a 16 byte string of data
Do not use interrupt
Use DOS (Data Out Strobe) to acknowledge
receipt and storage of data

ADDRESS
BUS_. - . - - . A I I
. ._ _ _
___

STROBE

AU - Aq

INTEL
MPU

8212

EA 9002

IN

DIS
DOS

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1-1
I

. _______________. . ::~18
DATA BUS

A! I

8212

UfYs -

SEQUENCE
1. Designate I/O Address as Bit 11 True (800 Hex)
(Source of Data)
2. Designate Word String Length as 16
3. Designate Destination of Data as Scratch Memory
Locations 1 to 16
4. Use Register 4 for I/O Address Pointer
5. Use Register 5 for Destination Address in Scratch
Memory and String Length

FIGURE 13

J

OUT

Example Program Coding
OP
CODE

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00
08
4C
64
00
65
10
54
DO
5C
3D
87

INSTRUCTION
INPUT

FETCH

COMMENT

LAI

PAGE

Load I/O page address

CAP
LRI

4
4, SOURCE

Load page reg 4 with I/O address
Load reg 4 with rest of I/O address

LRI

5,DEST

INP
WRS
OUT
DRJ

4
5
4
5, FETCH

Load reg 5 with starting address in
SM (also string length)
Fetch data from I/O & place in ACC
Write data from ACC to SM
Generate DOS for acknowledgement
Decrement reg 5 (SM loaction &
string length) & fetch next byte

Fall thru on completion

LABELS
PAGE
SOURCE
DEST

EOU
EOU
EOU

08
00
10

I/O address-bit 11 true is 800 Hex
SM location & string length (10 Hex is 16 decimal)

INPUT DATA RATE = lOllS

FIGURE 14

Microprocessor Comparison- Program Loop
For Inputing a 16 Byte Data String

INTEL 8080

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MOT 6800

EA 9002

J1S

BYTES

5
3.5
2.5
2.5
5

2
1
1
1
3

18.5

8

4

3

6

4
4

2
1
2

18

8

2
2

1
1
2

4

8,,--

CODE

COMMENT

FETCH

IN
MOV
INX
OCR
JNC

SOURCE
M,A
H,L
B
FETCH

Input to ACC from I/O
Move A to memory
Memory pointer
String length
Fetch next data

FETCH

LOA
STA
OEX
BGT

A
A,X

Input to ACC from I/O
Store A to memory indexed
Pointer & string length
Fetch next data

INP
WRS
ORJ

4
4

FETCH

FETCH

5, FETCH

Input to ACC from I/O
Store in SM
String length & pointer

~
TWICE AS FAST WITH HALF THE CODE!!!

FIGURE 15

EA Support
components:

EA 9002
EA 4700
EA 4600
EA 2101
EA 2000

8 Bit Parallel
1K X 8 Static
2K X 8 Static
256 X 4 Static
99 Key Keyboard Encoder

software:

Descriptive Brochure
Users Manual
Macro Assembler for IBM 360
Macro Assembler on NCSS Timeshare

hardware:

Start-up Board
System Emulator

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I

MPU
ROM
ROM
RAM
I/O

APPLICATIONS ENGINEERING

FIGURE 16

5.

INTRODUCING THE 32K READ ONLY MEMORY
MICHAEL R. MCCOY
Manager, Memory Product Development
Electronic Arrays, Inc.
Mountain View, California
The advent of the MOS Microproces sor has been an undeniable boon for the MOS
ROM industry. Once relegated to character generators, code converters and
laboratory curiosities MOS ROMs have now found their way into hundreds and
possibly thousands of applications attached to Microprocessors. A recent
limitation to the pervasiveness of MOS ROMs has been that the performance of
state-of-the-art Microprocessors has outstripped that of available MOS ROMs
causing the user to choose a higher cost or less desirable alternative or else
slow his system down. Recognizing this situation, Electronic Arrays is developing a new family of MOS ROMs intended for compatibility with present day and
near term future microprocessors.
The EA3200 is the first in a series of compatible ROM and PROM products to be
announced by Electronic Arrays. Key functional features of the EA3200 are:
·32, 768 Bits Organized
4096 words by 8 bits
·3 Programmable Chip Selects
·High or Complemented Low-Level Chip Enable Clock

•Three-State Outputs
·Optional Output Latches
·Input Latches on Chip

•Standard Supply Voltages

+12, ± 5, GND

·Simple Timing
Performance and electrical specifications are equally attractive:
• Acce s s Time

300ns

·Cycle Time

470ns

•Input One. Leve 1
•Input Zero Level
•Output One Level
•Output Zero Level
·Power Dis sipation

2.2 volts
0.8 vo Its
2.4 volts
0.4 vo lts
480mw Active
10mw Standby

The block diagram of Figure 1 illustrates the straightforward design of the 3200.

-55-

All addresses and chip selects are latched into the circuit with the Chip Enable
signal. The addres ses are then buffered, decoded and buffered again to addres s
and read out one word of data. The data is detected by a sense amplifier triggered
by a delayed Chip Enable signal followed by three-state output buffers. Two
options are apparent from the diagram; high or low-level-inverted Chip Enable
and output latching.
The timing diagram of Figure 2 shows the simple timing relationships of the EA
3200. Address and Chip Select signals need be present only for a short duration
following application of the Chip Enable signal. Data access occurs in less than
300ns after Chip Enable reaches a valid one level provided a valid select code
exists on the Chip Se lect Inputs. The output returns to open circuit condition
less than lOOns after the Chip Enable signal returns to logic zero. Note that
each access of data requires a Chip Enable cycle because the Chip Enable signal
and its inverse are used to initiate several internal clocks.
Should the user select the latched mode of operation, data will remain on the outputs up to 2 milliseconds after Chip Enable returns to logic zero. Data may be
altered or the chip de-selected only through initiation of another Chip Enable
cycle.
Selection of the low-level Chip Enable option has a minor effect on chip timing.
Due to the delay of the buffer circuit both access and de-select time will be
increased about 50ns. Note that selection of the low-level version inverts
the logic sense of Chip Enable.
It is not by chance that signal names and timing are similar to popular 4K RAMs.
It is believed that many users are familiar-with 4K RAMs thus making application
of the 3200 easier. In addition, one will find that the 3200 and 4K RAM operation
are sufficiently similar to be able to implement RAM/ROM memory systems
usi ng common signal line s •
Keys to the EA 3200 I S Performance
In order to achieve the density and performance required by the objective specification, substantial improvements in both fabrication and circuit techniques had
to be developed. The process selected was an Advanced Metal-gate process
recently developed and exploited by Electronic Arrays in the EA4600 and EA4700
static ROM products. The process uses a masked oxidation technique to allow
closely spaced geometries with a minimum of surface irregularities thus maximizing yield. The process is pa rticularly suitable for ROMs as no yieldreducing contacts are required in the array, such contacts being essential in
silicon-gate processes.
In the circuit design of the EA3200, we borrowed heavily from circuit techniques
developed for high performance 4K RAMs. Most of the circuitry internal to the
device is dynamic ratioless. In modern circuits such as this, the rather elaborate
clocking required is made completely invisible to the user. The only penalty paid
is the 2ms requirement placed on maximum cycle time.
One of the key circuits in obtaining the 3200's fast access time is illustrated in
Figure 3. In previous designs it was common to use a simple buffer amplifier
to read out the signal level from the ROM core. In contrast, the EA3200
uses a sense-amplifier technique similar to 4K RAMs. Here, only a very small
signal is required from the mePlory core before the output can be correctly
determined.

-56-

When Should I Consider A ROM?
In most Microprocessor applications there are several alternative methods of
program storage. MOS, due to its low cost and compatibility with popular microprocessors is the technology that is almost universally used today. Even if one
restricts the field to MOS devices, there are three distinct alternatives; RAM,
ROM and EPROM (Erasable, Programmable Read Only Memory).
The chart of Figure 4 compares these three alternatives for features of interest.
MOS RAM on the surface appears to be a winner due to its many desirable
features. Closer inspection however, reveals that it falls down in three
potentially crucial areas; density, cost in large quantity and volatility. The
fact that it must be reprogrammed when powered down is probably the most
frequent reason for dropping MOSRAM as an alternative.
The MOS EPROM's one outstanding advantage when compared to RAM is nonvolatility. Once programmed it need not be reprogrammed again for years unless
one exposes the device to ultra-violet light. Its disadvantages are its relatively
slow access time and high comparative cost in anything but small quantities.
MOS ROM's such as the EA3200 share the non-volatility advantage with EPROMs
but have the added advantage of high density and very low cost in medium to large
quantities. Figure 5 illustrates the rather dramatic differences in ROM and
EPROM pricing in various quantities. Here published prices are compared for
an 8K EPROM and EA's compatible 8K ROM. Note that the cost of the ROM
gets astronomical below 25 units due to the relatively high ($1500) one-time
masking charge. Above 25 units the situation changes rapidly with the ROM
having a 4 to 1 cost advantage at 1000 units. The comparison would even
more dramatically favor the ROM if larger, more cost effective ROM's were
compared with the 8K EPROM (currently the lowest cost device of its type
available) •
Unfortunately for ROMs, unit cost is not the only criteria for device selection.
During early production, when program changes are likely, it may be intolerable
to wait 6 weeks for a program revision. In such cases a PROM is often selected
even at a substantial cost sacrifice.
Solving System Problems With The EA3200
The prime objective of the 3200 development was to realize a device that can be
used effectively in microprocessor systems. How well this goal was achieved
can be easily seen in Figures 6 and 7. Here the 3200 is shown connected in
the two most popular microprocessor systems. Note the near absence of interconnecting devices, only a single TT L inverter is needed in the 8080 system
and direct connection is used in the 6800 system. In both cases the system can
operate at maximum rate unimpeded by the ROM and program capacity can be
expanded to 16K words without any addition to supporting circuitry. The output
drive capability of the 3200 allows direct conriection to the 8080 data bus which
is not pos sible with many existing ROMs. In both systems the user will find
that selection of low level chip enable and non-latching outputs is most desirable.
Figure 8 shows the EA1600 in an EA9002 system. The 1600 is a 16K version of
the 3200 and was selected in order not to monopolize the 9002's 12 line address
bus. A min6r amount of additional circuitry can be added to the 9002 system to
implement block addressing in which case multiple 3200 devices could be
implemented in the system.

'-57-

The EA3200 is certainly not limited to microprocessor applications, its high
performance, high density and low cost make it ideally suited for many applications.
Figure 9 illustrates an increasingly popular application-application program
storage. Here the programs stored in ROM are packaged in Plug-in modules that
the user can change at will. Several recent minicomputer announcements have
featured compilers stored in ROMs resident in the system. Such applications
appear to have high utility. The customer need no longer load his program into
the device via paper tape, cassette or the like. On the supplier's end, there are
many advantages. When a customer purchases a program, he gets hardware
rather than a "soft" copy and expensively generated software would be much more
difficult to copy and use without authorization.
Other potential applications of the 3200 are numerous. Its high capacity makes
it ideal for high-resolution character generators and digital voice response
systems. Its very low power dissipation (10mw standby) is sure to make the
device a winner in applications where available power is limited. Its low cost
per bit will allow its use in such cost sensitive areas as complex electronic
games.
The 3200 is in final stages of development and will be available in the second
quarter of 1976. Start planning now to use this highly effective device in your
next system.

-58-

CSI

...

CS

CS2

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CS3

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(OPTIONAL)
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(f)

w

0:::
C
C

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....

--

:l
....I

0

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~

<'I

...

~
~

-OVDD

I
B
B

- OUTPUT
SENSE
-

...

-

-

01

AMPS

02
03

8
B

04

Os

B

8

06
07

8

Os

B

AII

FIGURE

-0 Vee

I

-

z

-OVaa

I

X

::>

en

w
c

r

.

MEMORY
MATRIX

00
0:::0

..

LATCH
(OPTiONAU,

I ~cHI" SENSE

~

O~

3:~

r

~,

(f)

~W

----

TIMING
GENERATOR

I

....I

A5

U1
\..0

• -OVss

_

Block Diagram of the EA 3200

-\~II5-TCE -

/ -.....- - - T C E

CE----'~TAHI
ADDRESS
CHIP SELECTS

X'NPUTX-~~~DO-N-'T~C-A-R-E~~~~~~X
VALID

.

~~--- TACC --~·I
DATA
OUTPUT

-1

....

OUTPUT FLOATING

PARAMETER

-<:]

SYM

....
_ __

~ Too ~
OUTPUTS STABL-;-1>--

MIN

MAX

ADDRESS HOLD T I ME

TAH

CHIP ENABLE ON TIM E

TCE

280 ns

CHIP ENABLE OFF TI ME

Tel

130 ns

OUTPUT ACCESS TIME

TACC·

300 ns

OUTPUT DISABLE TIME

Too

100 ns

FIG URE 2

90 ns

EA 3200 Tim in g

-60-

Vee
ROM OUTPUT
MUX

OUT

ROM
OUTPUT
MUX

~----o

OUT

Vss

CIRCUIT
"ZERO"

~111:::::-----~---

NODE A
(j\

J-I
I

OUTPUT

II

--~------

Vee

NODE A

-1------+----1--I

"z ERO

Vee

Vss

--Vee

=t====~L-----+--

Vss

- - r - - - - - + - - - - - - Vss
Vee
j..----

OUTPUT

---=+=:===:IL..;..---- V SS

~
EA 3200

TACC

PREVIOUS DESIGNS

FIGURE

3

Comparison of ROM Sensing Techniques

FEATURE

COST-SMALL QUANTITY

COST-LARGE

QUANTITY

PROGRAMMABILITY

REPROGRAM TIME

I

MaS

MaS

MaS

ROM

EPROM

RAM

HIGH

MEDIUM

VERY
LOW

I

FACTORY

OFF LINE

ONLY

PROGRAMMER

VOLATILITY

DENSITY

ACCESS TIME

FIGURE 4

I'

N

SYSTEMI



ADDRESS BUS
kAO-AII

J

R/W

--

-6800

1/

JI

AI5. CSI
AI4 CS2
CS3

..

-..

CE
EA-3200

J
~
DATA BUS

.--- -,
,,
,,
I

I

I

,,

I

OTHE R
SYST EM
DEVIC ES

The EA 3200 in a 6800
Microprocessor System

-65-

I

I

I
L ___ _J

~

FIGURE 7

I
I

FIGURE 8

The EA 3200 in a 9002
Microprocessor
System

-66-

_~I

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I

I I , I I ,I I I I I

I

a.:

::e
0

U

u

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ex>

I

I
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6

Transmit Data 8'

I

I

~

1

Error Ind.

I

I
I
I
I
II
II
I
I

T
R

+s

Block Diagram-C()nventional I mplementation for
The Intelligent Typewriter System (ITS)

G

The coordinating control block is another major functional block in the ITS.
performs the coordination of all the functional blocks in the system.

It

In summary, the conventionally designed ITS consists of a TTY, TR1602 serial/
parallel interface, a memory, and a large control section. The control section
must be large and complex to handle the functions of the ITS. And it must be
designed from scratch out of a large array of SSI and MSI circuits such as inverters, gates, flip-flops, multiplexors, decoders, counters, registers, etc.
75 IC pagkages are required to implement this random logic version of the ITS.
MICROPROCESSOR-BASED ITS
By designing a general purpose serial I/O interface between the Signetics 2650
microprocessor and the teletype, we can transfer the burden of designing hardware control circuitry to implementing the necessary functions as the random
logic based design, with a software program within the microprocessor.
One basic design approach is to use a UART, as in the previous design, to convert
from serial teletype I/O to the more convenient parallel I/O. Then, the parallel
input/output data bus of the microprocessor is connected to the parallel port of
the UART. The additional control circuitry required to accomplish this is presented in Figure 6. The signals lines on the left hand side of the page are the
Signetics 2650 pins. These are summarized in Figure 7 and Table II. The number
of IC packages to implement this version would be 18 and the length of the software program is less than 350 bytes.
The main ITS software program flow chart depicted in Figure 8, describes the
process of text insertion, including the main subroutines. Referring to Figure
8, we begin by utilizing the ITS in the subroutine labeled INIT; this entails
clearing the typewriter control mechanism, the keyboard buffers and the memory
in which the text is stored. Then, subroutine "IN" gets a character from the
keyboard buffer. Since the hardware interface is parallel, the 7-bit character
pattern is directly received in register RO of the 2650. The line from the
teletype input is high (+5V or a lbgical 1) when no character is being transmitted, as in Figure 4.
In this hardware configuration, the UART handles the task of determining whether
or not a character is being sent. Later, we will propose a configuration where
this function is performed by software.
The next operation in the basic ITS flow chart depicted by subroutine "CTRL" is
the determination of the type of character just received:
1.

Character for memory storage

2.

TTY control character for memory storage

3.

Control character for text control purposes

The sequence of operations that take place within the routine are further expanded in Figure 9. The character just received is compared by the 2650 against
known values of control characters. If a match is found, like the RUBOUT control
character (Figure 10), from the TTY, the control function is executed. In this
example, the RUBOUT character causes delete of the last character in memory. The
delete-character subroutine is called by an instruction to execute the delete task.
Next, the deleted character is "echoed" to the TTY so the user can verify what he
deleted.

-89-

I\D R 1-7 >-'-------7~/7-----.,

MilO
E/NE

r f~ DEV ICE AD RS . - _ - .

A B
I------IENB
A=B

I

r..

OSC
--

UART

OPAC K ~-+----\1C
READ STATUS
WRITE CMD

ADRO~--+----------~~I
R/W----+-----t-~I

COMMAND

WRP

8

I

~

0
I

8

8

DBUS~

INTREQ
INTACK
PRIORITY IN

OPREQ

Figure 6

General Purpose Serial I/O Interface

(ITS)

FLAG

SENSE

J~
II

)1
+5V

11

.,
7

•

I

15

......

ADDRESS
l8 ... DATA
. M/IO
.,.

DATA
TRANSFER

~.

I

~

GND

......

-

--

R/W
\f\JRP

-

OP REO

•

..

,.

I

~

·2650

...

OPACK
INTREQ

C(

CLOCK

~

-~

.<{

.

"'-.

RESET

<41(

,.

)III

Figure

7

}

SYNC

} INTERRUPT

INTACK
PAUSE
RUN/WAIT

DMA

ADREN
DBUSEN
~

2650 I nterface Signals

TABLE II
2650 SIGNALS PINOUT

+5V, GROUND

Power and Ground

CLOCK

Single phase, TTL level, static
operation clock input

RESET

Starts processing from a known
state (location zero)

Data Transfer Signals
ADDRESS

Addresses program and data memory
and I/O

DATA

Bi-directional data bus for program
and data memory and I/O
Specifies a memory or I/O device
operation

R/W

Specifies an input or output operation

SRP

A pulse during an output operation

FLAG

An output line located in the PSW.
Use is programmers choice

SENSE

An input line to the PSW.
programmers choice

OP REQ

Coordinates all external operations

OPACK

Response to OP REQ from external device

INTREQ

External interrupt

INTACK

Response to INTREQ from 2650

PAUSE

Request to temporarily stop operation
of the 2650

RUN/Wi:iT

Indication of the operating or temporarily
stopped state of the 2650

ADREN

Removes 2650 Address lines from the tristate bus

DBUSEN

Removes the 2650 Data lines from the tristate bus

Use is

Sync Signals

In,terrupt

DMA Signals

-92-

ASSEMBLY LANGUAGE
PROGRAM

FLOWCHART

"IN"
CHARACTER FROM
KEYBOARD BUFFER
VIA PARALLEL I/O
CHANNEL

SET CONSTANTS
PARB = 127
NULL = 0

~

LOA D CHARACTER
FROM KEYBOARD
BUFFER (KBVF) INTO A
REGISTER (EG. RlI

-

LOAD R1, KBVF

t

REMOVE MSB FROM
8 BIT CHARACTER

.-

ANDI R1, PARB

,
REPLACE CHARACTER
IN KBUF WITH
NULL CHARACTER

.-

LOAD RO, NULL
STORE RO, KBUF

,
RETURN

Figure

8

Input Character Routine Flowchart and Corresponding Assembly
Language Instructions for a Parallel I/O Channel

-93-

"CNTL"
INPUT-CHARACTERDECODE SUBROUTINE

NO
DELETE
CONTROL-CHARACTER:
RUBOUT

YES

DELETE CHARACTER
SUBROUTINE

ECHO CHARACTER
SUBROUTINE

NO
ERASE
CONTROL-CHARACTER:
CONTROL E

YES

RETURN

Figure

9

ITS Input Character Decode Machine
(CNTL) Flowchart
-94-

Proceeding to the next level of detail, let's look at what happens inside the
delete character routine, documented in Figure 10. Referring to this Figure,
we note that the main operation in this routine is the replacement of the
given character with a null character. In the 2650, a null character is represented by an eight-bit byte containing all zeros. This byte is readily generated by the logical function instruction called "EXCLUSIVE OR". All we have
to do is "EXCLUSIVE OR" the contents of RO with itself. This is accomplished'
by the instruction:
EXCLUSIVE OR, RO
Note that it is implicit in this instruction that the other register to be
EXCLUSIVE OR'ed is RO' We will consider a version of the echo character subroutine in the next section.
In the foregoing discussion, we began with the main ITS program of Figure 8.
Then, we looked at the flow chart of a specific routine "CTRL" in Figure 9.
Subsequently, we looked at a specific routine "RUBOUT" in Figure 10. Finally,
we elaborated on the way in which the 2650 generated the null character by the
EXCLUSIVE OR operation. This process of sequentially proceeding to the next
level of detail until the task to be performed can be described by the microprocessor instructions themselves is called top-down design. Starting with a
system specification, the job of the microprocessor-based system designer is
to plan the functioning of the entire system by this logical top-down programming process. Thus, the emphasis in developing a good design in a timely
manner is to design well-structured, easy to debug/modify/understand programs.
Going back to Figure 8, we see that the next task, after performing the functions in routine "CTRL" is to check the editor status. If the editor is not in
the print mode, then, it implies that we are inputting the text; consequently,
we add a character to the text buffer memory in routine "SAVE". Of course, if
the character was a control operation as described in the last paragraphs, it
is not stored in memory. But, if it is one of the following, it is stored in
memory:
1.
2.

Character for Memory Storage
TTY Control Character for Memory Storage
(like typewriter carriage, return, line feed, or advance paper and stop)

After ensuring that there was, indeed, room left to store this new character, we
sent the character back to the teletype printing mechanism (ECHO), so that the
user can verify what he typed in. This whole process is repeated in an endless
loop until an appropriate command is decoded to indicate the completion of the
text insertion task.
MICROPROCESSOR-BASED ITS USING SERIAL I/O
We noted previously that the teletype was a serial I/O device. In the previous
microprocessor-based design, a UART was used to convert the serial I/O teletype
channel to a parallel channel so that the characters could be input to the 2650
via the parallel data bus. But, for an application involving a relatively low
speed device such as a teletype, there is not real need to use the high speed
parallel data transfer paths of the 2650.
Referring to Figure 7 and Table II, note that the "sense" bit, in the l6-bit
program status word (PSW) , is located in the most significant bit location i.e.
bit 7 of the upper half of the PSW designated as PSU; and bit 6 is the flag bit
in the PSU. These bits are directly accessable on the 2650 pins. These two
pins, namely the sense and the flag pins, can be used to implement a serial I/O
channel in the following manner.

-95-

"RUBour'
DELETE CHARACTER
SUBROUTINE

YES
BUFFER
EMPTY?

SET UP ERROR
BELL REQUEST

NO

REPLACE CHARACTER
WITH NULL CHARACTER

MOVE POINTER

RETURN

Figure

10

Delete Character Subroutine Flowchart

-96-

For inputting TTL compatible serial input data, we can use the sense line. The
sense bit is normally a 1 (+5V) between data transfers. The line drops to zero
volts (0) to indicate a start bit. Then 8 bits are serially transferred. After
this, the line goes back to a 1 (+5V) for one or two stop times, depending on
the data transfer rate. This line can be sampled inside the 2650, under software control, by executing a "STORE PSU" instruction which stores the contents
of the PSU into RO and sets the condition code bit (CC) of the PSW. For outputting TTL compatible serial data, we can use the flag line. To transmit a
start bit back to the teletype, we set the flag bit of the PSU to a 0;' to transmit a stop bit, we set the flag to a 1. Moreover, to transmit data bits, the
flag bit is set the same as the corresponding data bit. This process is accomplished under software control by executing the "SET PSU" instruction.
Thus, we realize that, in the case of this dedicated microprocessor application,
namely ITS, there is really no need for the generalized serial I/O interface.
Instead, we can directly use the sense/flag pins on the 2650 for serial I/O.
The resulting hardware configuration for this dedicated ITS application is shown
in Figure 11.
Three control signals from the Signetics 2650 control the ITS memory, not including the address bus. OPREQ is a coordinating signal indicating that an
external operation is taking place. OPACK is grounded and unu~ed since the
2606 and 2608 respond in less than I ~sec to a 2650 request. R/W selects a
read or write operation of the 2606 RAM memory, and WRP provides a timing pulse
for the same. The 10th address bit, ADRlO, acts as a chip select. It places
the 2608 in address space 0 to 1023, and the 2606 in the address space 1024
to 2047.
ADRIO and ADRO-ADR9 select one location in those address spaces.
Notice that we have a total of 6 IC packages and only one +5V supply drawing
about 500 milliamps! The hardware for this system is available from Signetics
on a 2-inch by 3-inch printed circuit card!!
Now let us look at the software program. Functiona.lly, the software program
becomes more simple! We no longer have to generate the DART control signals.
The only significantly new softwa.re program is one that converts the serial
input from the sense line to parallel byte format for further processing and
the logic required to set the flag line to echo or print the proper character
on the teletype printer. We will look at this program in more detail in the
following.
Referring to Figure 11, we note that keyboard processing is done in subroutine
"IN". Let us discuss the detailed flow chart and the corresponding program for
this subroutine, using the 2650 instruction set.
The flow chart for this conversion is shown in Figure 12. The first job is
to continually sample the sense line until a start bit is detected. Then, we
introduce a delay of half the bit time to test the sense line again to ensure
that it was not a noise spike. After ensuring that it was, indeed, the start
bit, we, then, introduce a delay of one bit time to test the sense line for
the first bit of the 7 bit character. This process is repeated until all 7
bits are received and put into the proper parallel byte format.

-97-

>

~

1
SENSE

I

r-----~

I.ei'~-.... -. 1_""

1---(!I..:J----+-1UI
--\.

U

1_F LA G t---~LJ~I 10
I-

I -

I

>TTV

• 256 BYTES RAM·
o 1 K BYTES ROM
" 6 PACI(S
• +5V @ APPROX 500mA

~.:

7439 I

.) / 8

DBUS~------~----~~--------~·---~~··~

2650
I

~

R/W

00
I

WRP
OPACK
OPREQ

I

I

I

I

,--_~II.-~l,'~.;

~---4

I

~~

/

R/W

I

r1

I

I

-

I

I

2606

1---r--rl--r~)oro,_----+:oIJI!P-JI
&:;~ CE

I-

R/W

I

'---.......--.1

2606

~ I~ CE

2608
r;J..- -CS

------P---..!

A10~~~t~------~,~----~A'----~--_+~~----~;~
10 L - . - _.....J ' - - _ - + -_ __
AO-9~/~~---------------~------~~--------~

C_L_OC_K___ ~ 741231

Io....-_ _

Fig. 11:

Dedicated Serial I/O ITS

.1~
....

. -,...

_t__
<;'lottf

-'"

Ps U.

·(~C' ~.;~ ) ....

1.

.

~

'---r----

,A

-99- "'-

~o

.--.-.- (J
J-,

)_._---_
\

~

-~-"-

..... _- -

-

!

.'- -._.- •. - -.

t

~

!

_..... _.....

- .. -.. .......

....

- - - - - - . ..... .

~

-

\.

.•. [

--_.

•
;

,

#.-~

I

..

- - - .._- -

---

----".

.~

--

"-"'--

.

-~-'-'

-.. _._..•.. _---

-- -..

..

.

•. --

i

?
...

12

.-~----

...

.

_----

__i-_'__
No

\/

-100-

LOAD R1 (WITH 0)

t
STORE PSU

-----{

'STORE' PSU IN RO

f

,

AND 128

INCLUSIVE OR R1

---~-{

CONTENTS OF RO
'AND'ED WITH 128 = 27
TO GET SENSE BIT

-----{

'INCLUSIVE OR' R1 WITH RO
AND SAVE RESULT IN RO

-----{

"STORE' RO IN R1

t
STORE R1

t
ROTATE RIGHT R1

-----{

'ROTATE RIGHT' R1

t
Figure

13

Serial to Parallel Conversion Flowchart

-101-

To delay for any timed operation is a simple matter in the Signetics 2650 Microprocessor. Any register, like RO is loaded with a number. The register is decremented by one each time through a program loop (a loop is a sequence of instructions which transfers execution from finish to start and is usually executed more than once). When the register is tested (each time through the
loop) and found equal to zero, the timed delay is complete. The timing is
provided by three things:
1.

2650 input clock frequency 1 MHz in the case of the ITS.
frequency is variable up to a maximum of 1.25 MHz.

The 2650 clock

2.

Instruction execution time. The time to execute an instruction is a fixed
value which depends on the type of instruction and the clock frequency.
The total of the execution times of every instruction in the loop gives the
loop delay time.

3.

Number loaded into the register being used in the program loop. This is
the number of times the loop is executed, and, therefore, the number of
loop delay times.

Example
Clock Frequency

= 1.25 MHz

Loop contains instructions A, B, and C
Instruction execution times

A

= 4.8

jJ.sec

B

4.8 jJ.sec

C

7.2 jJ.sec

Loop execution time

16.8 jJ.s

Number of times through loop

100

Total delay time

1.680 Msec

Once a valid start bit has been detected, a delay of one bit time (~9.l msec) is
made until the middle of the first data bit. The middle of the first data bit was
reached in the following manner: the leading edge of the Start bit was detected
because the 2650 program was continuously looking for it in a tight loop; the program loop is very fast compared to the frequency of the sense signal (several microseconds compared to 9.1 milliseconds); so when the start bit was detected, it can
be assumed the leading edge was detected and not the middle; the middle of the start
bit was located due to the 1/2 bit time delay during the noise check; finally, the
middle of the first data bit was detected due to the one bit time delay from the
middle of the start bit.
The first data bit is sampled on the sense line as "1" or "0" (high or low), and
saved. When 7 bits have been received in this manner (a count is kept in R2), an
entire character has been received.
The serial to parallel conversion for each character is accomplished by transferring a data bit from the sense bit into RO with the "STORE PSU" instruction.
The data bit alone is left in RO after execution of the "AND" instruction. The
last data bit sampled is assembled together with the data bits previously received
in RO by the "INCLUSIVE OR" instruction. The "STORE" instruction puts the contents of RO into Rl. Finally, the "ROTATE RIGHT" instruction gets the contents
of Rl ready for the next bit of the character.

-102-

The correspondance between the verbal flow charts of Figure 12 and 13 and a set
of basic instructions developed has been shown.

SUMMARY
We are now in a position to discuss the main reasons why microcomputers have a
significant advantage over random logic:
1.

Reduces system complexity

2.

Ease of development

3.

Flexibility (ease of system function modification)

4.

Reliability

5.

Ease of support

6.

Lower Cost

Comparing the two implementations, we can see that the system complexity is significantly reduced. Since the hardware complexity is reduced in terms of parts
count, it is much easier to layout the printed circuit boards; cross talk, and
other interference problems are reduced; connections, cabling) cooling and packaging requirements are reduced. Most significantly, the 2650 required only one +5V
supply. Other reasons for the ease of development are that a softwa.re programs
are usually much easier to understand than an equally complex piece of hardware.
(Debugging software is much more systematic and, therefore, usually less time
consuming than hardware troubleshooting.) For example, problems such as electronic circuit malfunction, interfacing, timing pulse alignment, radio frequency
interferance are practically eliminated. Debugging the 2650 is particularly
easy because its internal circuitry is static rather than dynamic; consequently,
the clock can be stopped to look at its pins without losing data or status. The
microcomputer-based system is more flexible and easier to support because of the
fact that software can be readily modified and is readily documentable. Reliability is greatly enhanced, again due to reduced parts count.
All the above factors can finally be translated into cost savings to the manufacturer. Software development is a one-time cost that can be spread across
the production run. Field support is easier with fewer spares required in stock.
Finally, the product can be continually upgraded without altering the hardware
packaging leading to market competitiveness in terms of the introduction of newer
products.

-103-

8.

Senior Applications Engineer
honol~thic ~emories

Sunnyvale, California
5710/6710 Logic Symbols

(Fig. 1)

r1b
· S;7illl.b 0 1 S 01-.r:> -!-'
":C
•
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01
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t~ 'He T'O'"l"
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rv-L. '-'

.... -

'-

-,

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J....:

"'w.J

tlonS. Da~a slgnals on Flag lnputs, Sh1f~ ~/U Ilnes and 1D?U1J
}j'ield T:Tl-8 do not alter their function. l'he instruction fields
hOvJever, on chanGe of active state reorder the operation tables.
'Tlhe sienal CHAC, 'VJhicb. signifies a,iciress 511 or 510 in the active
High case, now signifies address 0 or address 1 in the active Low
case. The ~CU also steps through a Control Memory backwards in
the active Low logic representation. The active High representation is a little easier to understand and it is suggested that
programming take place with this in mind. If data inputs are in
the active Low logic polarity it is then a simple matter to invert
the result of the information using the 17 control for all conditional branches.
IvICD BLOCK DIAGRAfv:l

(Fig. 2)

CEAR Logic
t"ID i\
] • -!•
t 0. t wo sec,lons,
t .
. h
" S~C01?~
-L. •
IDe ~~h.1S
Sp.l...,
up 1~
an e1~~~
OlT
WDlcn
can remaln unchanged, oe 1ncremen~cd, loaded Irom a SUbrOU~lne
temporary storage register latch and loaded. from an 8 hit e::;:~terl)al
field HI-n. The one bit section is the least si~nificant bit of
the Addre~s Word and is directly driven fr08 the~out~ut of t~e
-7'
C!..!- ..!- ..
~.-.-i
ri\'ha
,.-'-"",.,-1.J-1,...
T;11'.:l~' C-'-L.a-1.-,
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Ovt-'lJ~'l.J 0_1.
1.1'--\.8
,~~ )JvCAVUS JJOt~;.J-C
VUCre.LO.L.,-"
defines whether the next address is even or odd depending upon ~be
condition of the selected flav si~nal. ~his allows two wa~ branchl
in~_,): at r-qrcY'V c 1 eC I : 1.'
neY'loe
'-'
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n~

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(....

.J. . .

I 1b.e output of the CE}\R passes through buffers to OUt:Pl}t 3,)ins.

The eight

section buffers have three state outputs so that
Ti'1"1!:lb .Le
..
(,)i'~)
-i
n·
0'1
e"".r+A-nn~"" '~
q-; r~';'i~l
c
~,a,;
,. ,H,....·'T·_
-_--'J..lCA)
1."",_/
-,-S
_, ... 1(.),:}
..:).~u.-,-.J
11T8
the Control EeDory Address lines.

T"lYl·en
~V~
,

f-he·
v_~

~it

Oll't",,-L.
\"A.
..::",.,.0

Control Counter

-,,-V'oJ.l..d,-,.l.

__ ;.

•.

,.L ....

Ilo~ic

~-

The Control Counter Logic is 5 bit s ~:!ide ~;·Jith t11e loCic ve72~.:­
similiar to the CIU\.Ir lOf.=ic. ~he loCic includes a re2:j, ster,
-104-

•

,

pass/decrement unit, temporary subroutine register and a 3-way
input multiplexer which can select information from the external
field bits Nl -5' the temporary storage register, or the pass/
decrement uni t. The counter logic is used during the tltlO conditional jump instructions. Each time t~le t1CU encounters a conditional jump instruction the control counter register is tested
for zero and decremented. If the register \vas zero then the
MCU instead of performing a Jump instruction continues on to the
next address pair. The next time the conditional jump instruction
occurs the procedure is repeated but now the value of the register
is one less. The control counter register can be loaded from the
Nl - S inputs on receipt of a Continue Load Control Counter instructl.on.
~~ag _Stc!~~s Logi~

The Flag Status Logic consists of a loadable Shift Left/Shift Right
register, an eleven way mUltiplexer, an exclusive OR gate and a
small amount of control logic. The shift register can be loaded
\vith four flags C,N,V,Z with separate loading selection for C and
the group NVZ. The register can be shifted one place Left with N
going to C,V,to N, etc., and a logic zero being pulled into z.
The C register bit is placed on the bidirectional input/output
line QO and would most likely in a system enter the least significant bit of the Q register in the 5701/6701. A Right shift
causes C to be loaded with QO this time acting as an input, and
what is in C going to ~, etc.
The eleven way multiplexer can be used via the select and control
lines 11_h to select one of the following signals: Stored C,N,
V,Z, Present C,N,V,Z, logic 0, Q , and Q. All of these signals
can be inverted by having 1 =1, 2nabling 3branching on C,N, Etc.
The output of the Flag Stat6s logic Ex Or gate is the input to the
least significant CRAR register bit. T11e Flag Status logic also
provides a signal to the pass/increment unit to indicate that a
conditional branch is present and the unit should increment.
Shif~_~on!=-rol

Logic

The Shift Control logic provides the connections for a minimum
set of useful 5701/6701 shifting options. Two control inputs
18 and 19 are used to select the desired option. 18 indicates
which bidirectional buffers are actively sending information and
19 selects various signals to apply to the shift lines of the
5701/6701. Provision is made in the shifting logic to provide
correct sign information during right arithmetic shifts by an
exclusive OR of the N and V signals.
Contr~L Logic

The Control Logic uses the instruction control inputs 1 0 - 2 , the test
zero output of the Control counter Logic, and the signal which indicates that the Control Counter temporary subroutine storage register
contains the same value as the five least significant bits of the
-105-

CRAR register. These signals are then encoded into the control
signals necessary to implement the HCU instructions.
Two flip flops are included in the control logic. The first remembers
that the MCU is in a micro subroutine and when a return is encountered
it is obeyed if the flip flop is set, and if the flip flop is clear the
return is ignored. The second flip flop indicates that a Preprogrammed
Return Subroutine is in progress called by instruction 101, and the
MCU should automatically return when equivalence of the CRAR and CC
subroutine latch is achieved. Both these flip flops are automatically cleared during power on and may be reset by under microprogram
control by loading the Control Counter with N =1.
6
Ge~aliz~c! . Control System Using 5710/6710
(Fig. 3)
The 5710/6710 MCU, although designed to work efficiently with the
5701/6701 1-iicrocontroller, is a po\verful controller in its own right.
The device could be used in any application which requires sophisticated control of a complex system. The diagram shows system inputs
entering a PLA and being translated into condition variables which
can be processed by the MCU. The MCU is driven by a program stored
in a control memory and the system outputs also derived from the
control memory.
Typical System Block Diagram

(Fig. 4)

A typical system using the MCU would require one 5710/6710 device
and a number of 5701/6701 r1icrocontrollers defined by the vlord
length of the machine. The system memory would store both instructions and data. Instructions would be loaded into an instruction
register and then the starting address of the microprogram code,
defining the operation of the instruction, would be sent to the MCU.
The MCU would then step through the microprogram under control of
the information stored in the microprogram memory and the information
coming from the Flag Status conditions of the 570l/670ls. The MCU
would also send the programmed connections for shifting operations
in the 5701/6701.
System Instruction Fields

(Fig. 5)

The 5710/6710 Meu requires up to an 18 bit microprogram word. This
field is spli t into several groups 1 0 _ t'lhich define the MCU
2
operation, 1 -7 which control the Flag status logic and choose the
branch condifion, 18-9 which control the shifting connections in a
5701/6701 based system, and an external input field Nl - 8 which
provides both the jump address and Control Counter vatlle and
Subroutine flip flop clear. This 18 bit word can be shortened, first
by addressing a smaller memory, second by not using the shifting
capability, and third by not using the full branch condition and
operation power of the HCU.
The 5701/6701 Microcontroller microprogram word is also up to 18
bits. Eight bits are required for the two port memory addresses
A and B. The instruction is split up into two fields 1 0 - 2 , used for
defining the destination of results and the shifting option, and 1
3-7
which define the operands and operation to be performed on the
-106-

data. The remaining bits are the Output Enable and Carry In to the
ari thmetic uni t.
57l0/67l0~570l/670l

Interconnections

(Fig. 6)

Interconnections between tlle t\vO Computer Logic products consist
of the Flag signals from the 5701/6701 OVR, C + 4 ' F=L and the D0 4
n
output, which are connected to the V,C,Z and N 1nputs of the
5710/6710 respectively. The other interconnections are the shift
connections with SQLO/SQRI of the 5701/6701 going to the Q3 input
of the 5710/6710 etc. The two logic circuits would generally
operate synchronously so that the clock inputs of both devices are
connected together.
MCV Control Options

(Fig. 7)

The r'-ICU has eight instructions controlled by the field 10-2. All
of these instructions act only on the eight most significant bits
of the CRAR register with the least significant bit of the register
under control of the Flag Status logic. The instructions apply to an
instruction pair.
The first operation is Continue on to the next instruction pair. If,
however, the action is an unconditional branch the next instruction
pair is only the target address if the [-'lCU is at an odd address. This
enables the t·1CV to step uncondi tionally through addresses in the
Control Memory by changing the state of 17. The second 1nstruction
is also a Continue but in parallel with the action. The Control
Counter is loaded with the value on the external inputs Nl - 5 and
. if N6=1 the two control flip flops used during subroutines are
cleared.
The next two instructions are Conditional Jumps and cause a Jump to
the ad.dress specified on the inputs N1-8 if the Control Counter is
not equal to zero. If the Control Counter is zero the Jump is ignored and the MCV Continues on to the next instruction pair. Again
the Continue action changes slightly if an unconditional branch is
specified. During these Conditional Jump instructions the Control
Counter is always decremented by one each time the instruction is
obeyed.
.
The Conditional Subroutine Jump if the Control Counter is ndt zero
decrements the counter by one and stores the result in its subroutine
storage register. In parallel with this operation the present value
of the CRAR register is incremented by one if a conditional branch
vias being performed or the r-1CV \-1as at an odd address. The Return
instruction replaces both the Control Counter and the CRAR register
so that the MCV can continue through the main program.
Instruction 101 is a special Subroutine Jump instruction 't-lhere the
return is preprogramroed into the Control counter. Prior to using
this instruction the Control Counter is loaded with a value which is
equal to the five least significant bits of the CRAR register. The
MCV on obeying this instruction stores the CRAR return address and
the Control Counter and then starts the subroutine. The MCU automatically returns when e1e CRAR reaches the value stored in the
-107-

Control Counter subroutine storage register. This instruction allows
pieces of code to be used as subroutines without writing subroutines
and facilitates the addition and debugging of programs.
The last two instructions are Unconditional Jumps with the Jump address
being provided by the field N
•
1-8
If the MCU encounters a Return instruction and is not in a subroutine
then the HCU ignores the return and continues through the program.
This feature enables traps to be placed after Return instructions so
that programs can be debugged and system errors do not necessarily
cause complete system failure.
Flag Status Logic

(Fig. 8)

The Flag Status Logic consists of an eleven way multiplexer, 4 bit
shift left/shift right register, an exclusive OR gate and some control
logic. The output of the multiplexer passes through the exclusive
OR gate under control of the 17 control input and goes directly to
the least significant bit of the CRAR register. The logic also sends
a signal to the incrementor of the CRAR to indicate that the branch
is conditional.
The register which holds Flag Status conditions can be shifted left
and right for storage of flags during interrupts.
Flag Status Control Options

(Fig. 9)

The Flag Status Control allows one of eleven choices of signal to
be used as a branch signal. These are logic 0 for unconditional
branching, QO' Q3 and both the present and previous stored value of
C,N,V and Z. Selection of the signal is made by a four bit field
13-6 and each signal can be inverted by the control signal on 17.
There are six codes which result in an unconditional branch. These
codes also cause other actions in the Flag status logic and allow
flag signals to be stored and shifted into and out of the shift
register.
Shift Operations

(Fig. 10)

The MCU provides a minimum set of shift connections to the
5701/6701. These connections provide both an arithmetic shift
left (multiply by 2) and an arithmetic shift right (multiply by ~) •
Arithmetic shift left repeats the sign bit so as to keep the correct
sign of the shifted number. The input to the most significant bit
of the 5701/6701 word is the equation N ~ V which also satifies the
situation where two numbers are added or subtracted and then shifted
right. This is required during multiplication type routines.
The remaining shift options are rotate left and rotate right with
the 5701/6701 register forming an endless loop. Rotates do not
include the Q register in the loop.
All shifts are assumed to be double and shift the Register and Q,
but the 5701/6701 has separate control over the register and Q so
that the decision of whether the shift is single or jouble length
depends on the destination code of the 5701/6701. During a single
-108-

length ari thmetic shift t!le connections resul t in the most significant
bit of Q being shifted into toe least significant bit of the register.
Q must therefore be preset to the desired value or a single length
shift left should be derived by adding the register to itself.

IS controls tne activity of the bidirectional shift connections of
tne HCU and in the majority of systems can be tied to the 10 instruction input of the 5701/6701, thereby saving a bit in the Control
Memory word. 19 defines the inputs to the multiplexer Wilich places
onto Fa and F3 the desired logic functions to realize the various
shift operations.
HCU Next Address Table

(Fig. 11)

The key to understanding the operation of the MCU and the relative
ease of microprogranuning using the device is to split the Control
Hemory into Address Pairs. Each Address Pair has an even and odd
member. The member of an Address Pair to which the HCU points is
always defined by the output of the Flag Status Logic. If the output
of the Flag Status Logic is a 1 at a certain time period then in the
next time period the HCU will address an odd member of an Address
Pair; if it was a a then an even member would be addressed in the next
clock period. This even and odd separation allows combinatorial
two way branching based upon a flag condition at every microstep
with both target addresses specified implicitly. This assists complex porgramming since tags do not have to be attached to jump
addresses as in conditional jump branching.
At each conditional branCh the HCU always has two target addresses
and during a Continue instruction these two addresses are the next
Address Pair in sequence. In order to save address space, if an
unconditional Continue is specified the MCV only moves to the next
Address Pair if the MCV is already at an odd address. This enables
a string of unconditional steps to move through consecutive Control
Memory Addresses by calling for an unconditional step and programming
17 to point to the next even or odd address as required.
During jump instructions the target address is specified exactly
by the external input field Nl-a and the value of the Flag Status
Logic output.
Return instructions are a Ii ttle more complex. ~'nlich Address Pair
is stored in the Subroutine Temporary storage register depends upon
the MCU state at the entry point of the subroutine. If the entry
was conditional or at an odd address then the address was incremented
prior to storage, and the MCU returns to the Address Pair after the
entry point. If the entry was unconditional and at an even address
the MCU returns to the same Address Pair, which called the subroutine.
These characteristics can be used to advantage to program a wide
variety of subroutine ent~y and return variations.
Operation - Add the Contents of R to the Contents of R+l if N

~ V

is True

This microprogram example shows how the ability to branch on a Flag
input, and also its inverse, allows for a very flexible system and
saves code. The exclusive OR operation takes 4 words of Control
Memory and 2 microsteps.

-109-

Operation - Add Contents of R to the Contents of R+l if,NV + VC +
NVCZ is True
(Fig •. 12 - 15)
This is an example of a 16 way branch required by examining 4 variables
using the Flag Status inputs. '1'he 16 possible condi tions are shown
in the Flow Chart. Certain branches need not go to the complete
extreme since the result is known earlier. These branches are included
in dotted lines and can be removed. The resulting Flow Chart can then
be microcoded using the Meu.
The first action is to branch dependent upon the value of N, without
specifying as yet the target addresses. Underneath this pair of
words a branch on the value of V should occur, and underneath tnat
a branch on the value of C, and then Z. Now the Flow Chart can be
followed:
if N = 0 then branch to test V.
If V:-~= 0 down this branch
then a jump is required since the equation is False. If down this
branch, however, V = 1 then a branch on C is required.
If C down
this branch is a 0 then a branch to Z is required, otherwise the
equation is True and the addition is instructed to take place.
The programr.1er thus proceeds through the chart and parallels the
chart in the code as closely as possible.
Since all target addresses
are implicit the translation from chart to code can be performed
quickly and easily.
Operation - 16 Bit 2s Complement Hultiply

(Fig. 16)

-This multiplication microprogram performs 2s complement mul tiplication of two 16 bit signed numbers held in two 5701/6701 registers.
Initially, the multiplier is in register R+l and the multiplicand
is in register R. The first action of the 6701 is to move the
multiplier into the Q register, and the MCV steps on to the next
address.
The 6701 then performs a send zero to H+l so as to clear
it ready for receipt of the partial product and shifts the register
formed with zero a Q one place to the right arithmetically. As
the register shift is set up the least significant bit of Q, the
least significant multiplier bit, is sent out on the SQRO/SQLI pin
and is available by the HCU as a conditional flag input. 'ILle I1CU
during this period loads the control counter with the value 14 and the
next address is determined by the value of QO' the multiplier bit.
In the next step, which is the multiply iteration, the 6701 either
adds the multiplicand to the partial product and shifts the result
and the Q register right one position or performs just the shift
action. The choice is determined by the value of the Q register
least significant bit, the multiplier bit under examination.
In
order to repeat the iteration 15 times the MCV performs a 4 way
conditional branch on Q and the value of the control counter. The
HCU forces the system to move between A+l,O and A+l,l each time
performing a double length shift and adding in the multiplicand to the
partial product if the previous QO was a 1, and decrementing the control
counter. After 15 iterations the control counter reaches zero and
the NCD moves the system to the next address pair where the most
significant multiplier bit action is handled.
Since in 2s complement
multiplication the most significant multiplier bit carries a
-110-

negative weight a 1 signifies a subtraction of the multiplicant is
required. The last step moves Q to R, placing the lease significant
part of the product in register R.
The microprogram uses only 7 words of control memory and takes 19
steps. Unsigned multiplication would only require 5 words of
memory since the last iteration can be combined into the 4 way branch
action.
5710/6710 LOGIC SYMBOLS

17
16
15
14
13

Na
N7
N6
N5
N4
N3
N2
N1

5710/6710
MCU

12
11
10

5710/6710
MCU

CP
CRAC

- - 0 OE
0

CRAC
CRAR
012345678

CRAR
1

2

IIIIII I

ACTIVE HIGH DATA
(POSITIVE LOGIC)

ACTIVE LOW DATA
(NEGATIVE LOGIC)

Fig. 1
MCU BLOCK DIAGRAM
GENERALIZED CONTROL SYSTEM USING 6710
c

:,

v

INPUTS

z

c:p
+

IS 0 - - ·
IgO-----~L..--_ _ _ _ J

FLAG COND
CONTROL

N/F

6710
CRAR

t

ADDRESS
10

ROM
OUT

+
CRACo---+---4~

OUTPUTS

Fig. 3
Fig. 2
-111-

TYPICAL SYSTEM BLOCK DIAGRAM

SYSTEM INSTRUCTION FIELDS
FROM CONTROL MEMORY

SYSTEM·~-----'T-------------------'l
CLOCK.
,

CONTROL
SIGNALS

,.

r---------------------18BITS----------------~----

IN

SHIFT
..---.

6710
MCU

STATUS
FLAGS

ST~7~~TIONL_____~____1_3-_7____~____~----------_+~~--~

---,/'--r--'I

'--r--"'----I
SHIFT
STATUS

6701
1\1CONT

CONTROL

INST

CONTROL

I

I

COUNTER VALUE

/ 9

I

6701
IN STRUCTION

512 WORD
PAGES

I

FROM CONTROL MEMORY
10 BITS
OE Cn

I

'--r--"

DATA
ADORES

~I

10-2

'3-7

I

INSTRUCTI'ON

MISC

SYSTEM
1\1EI\10RY

Fig. 5
Fig.

4

5710/6710 - 5701/6701 INTERCONNECTIONS

014013012011
A3
A2
A1

17
16
15
14
13

Ao
B3
B2
B1

5701/6701

So

4 BIT
CPU
SLICE

17
16
15
14
13

12
11
10
Na
N7
N6
NS
N4
N3
NZ
N1

12
11
10

SalOl
SaRI

SOROI
SOLI

SlOI
SRI

SROI
Sll

5710/6710
MCU

CP

Fig. 6

-112-

I

OPERAND
B ADDRESS

NOTE: 'S (6700) CAN BE CONNECTED
TO 10 (13701).

I~
I INSTRUCTION
REGISTER

FROM INST REG
8 BITS

ClaCK

,

AO-3

B().3

1\

/10

18 TO 1I.1EMORY
COI\;TROL ETC

SUBROU111,!E
FF
RESET

L..:.... CONTROL

OPE RAND
ADDRESSES

COf';TROL
SIGNALS

COI'JTROL
1\1EMORY

I~+I

I~I

JUMP VALUE

'

~

1\

I
OPERAND
A ADDRESS

I

I

MCU CONTROL OPTIONS
CONTROL CODE

12

11

10

0

0

0

0

FLAG STATUS LOGIC

0

'*

1 ....

0

0

o

FROM SHIFT
LOGIC

CONTINUE TO NEXT J.LINSTRUCTION
C N V Z

CONTROL COUNTER

CONTINUE TO NEXT J.LINSTRUCTION

NONE/CRAR (COND. JUMP)

JUMP TO NEXT J.LINSTRUCTION IF
CONTROL COUNTER'; 0, DECREMENT
CONTROL COUNTER

NONE/CRAR (COND. SUBR. JUMP)

SUBROUTINE JUMP TO NEXT IlINSTRUC
TION IF CONTROL COUNTER -+ 0,
DECREMENT CONTROL COUNTER

0

0

CONTROL ACTION

NONE

0

0

ADDRESS FiElD DESTINATION

~~{;~~~GIC a---.-~-----I

0003

C N V Z

4 BIT
. - - - -....1 SLiSR REG

NONE

RETURN FROM SUBROUTINE

CRAR (JUMP SUBROUTINE)

JUMP TO NEXT J.LINSTRUCTION
RETURN FROM SUBROUTINE WHEN
SUBROUTINE CONTROL COUNTER
LATCH" CRAAO-4

CRAR (JUMP)

JUMP TO NEXT J.LINSTRUCTION

CRAR (JUMP SUBROUTINE)

SUBROUTINE JUMP TO NEXT
/-lINSTRUCTION

o

11 WAY MUX

17

THE MACHINE WILL ONLY RETURN TO THE CALLING PROGRAM IF IT ENTERED A SUBROUTINE VIA
A SUBROUTINE JUMP INSTRUCTION OTHERWISE IT WilL CONTINUE TO THE NEXT J.LINSTRUCTION
IN SeQUENCE.

0------------,

'j HIS OPERATION ALLOWS Ttl:: CONlROLLER TO BRANCH TO A SECTION OF CODE, PH, FORM THE
OPERATIONS OUTLINED BY THE CODe AND RETURN AFTER A PREPROGRAMMED CROM ADDRESS
HAS BEEN REACHED OR IF A RETURN IS ENCOUNTERED.

FLAG STATUS CONDITION
TO CRARO LOGIC

Fig. 7

COND ACTION
TO INCREMENTER

Fig. 8

MCU FLAG STATUS CONTROL OPTIONS

14

17

a

a

0

a

16

a

0

,

IS

a

,

,
,

0

,

,

,

a

a

,

a

,

0

,
,
,

SHI FT OPERATIONS
SHIFT

13

'a'
a

a

a

,

,

,

'a'

'a'
STORE C

SHIFT
LEFT

'0'
SHIFT
RIGHT

SC

C

SN

N

'"
'"

STORE C

','

SHIFT
LEFT

','

SHIFT
RIGHT

SC

C

sfii

iii

~
~ 1.[

~rION

o

ARITHMETiC
LEFT

0

o ,

LOGIC END
AROloND LEFT

~ r[~3

0;., }..,......

LOGIC END
AROLIND RIGHT

'a'
a

, ,

STORE
N, V, Z

'"

03

SV

V

STORE
N, V, Z

00

SZ

Z

STORE
C, N, V, Z

03

sv

'Ii

00

S2

Z

TO FLAG
REG

CONTROL CODE

'0'
STORE
C, N, V, Z

H~C~E~LAG

'fTO FLAG LOGlct

T

.!.!i..!.[
o 0
a

~ SRO/SLI SOLO/SaRI
(F3)

(FO)

AAITH. LEFT SHIFT
ARITH. R!GHT SHIFT

NIIIV

Fa

- HIGH IMPEDANCE
SC CARRY FLIP FLOP

Fig. 9

Fig. 10

-113-

-

~O/SQLI

(00)
FLAG (SCl

ROTATE LEFT
ROTATE RIGHT
SC = STORED CARRY ETC.

-~l
FO

FLAG (SC)

ADDRESSES IN PAIRS EVEN
ODD

CROM
ADDRESS

A,O ETC
A,1 ETC

A-1,1

INCREMENT OCCURS IF PRESENT ADDRESS ODD OR CONDITION
FLAG
STATUS

INSTRUCTION
CONTINUE

I

JUMP

RETURN

x

=

NEXT
ADDRESS

PRESENT
ADDRESS

COMMENTS

II

CONDITION

N=0

A,O

MCU ACTION

6701 ACTION

CONTINUE TO A,N

FINISH PREVIOUS
OPERATION

CONTINUE TO A+1,V

LOCKED LOOP

A,1

N= 1

CONTINUE TO A+1,V

NEXT CONS ADDRESS

A+ 1,0

V=O

JUMP TO A+2,O

NEXT CONS ADDRESS

A+ 1,1

V=1

CONTINUE TO A+2,O

UNC '0'

A,O

A,O

UNC'1'

A,O

A,1

UNC '0'

A,1

A+1,O

UNC'1'

A,1

A+1,1

COND

A,O

A+1,COND

I

SKIP OVER A,1

4 WORDS OF CONTROL ROM - 2 STEPS

COND

A,1

A+1,COND

!

NEXT ADDRESS PAIR

UNC '0'

A,X

NO TE AN N VARIABLE EXCLUSIVE OR TAKES ONLY 2N WORDS OF
CO NTROL ROM AND N STEPS. EVERY 2 VARIABLE FUNCTION CAN
BE PERFORMED WITH JUST 4 WORDS AND 2 STEPS.

UNC'1'

A,X

I
I

I SKIP OVER A+1,O

J,O

JUMP TO J,O

J,1

JUMP TO J,1

COND

A,X

J,COND

JUMP TO ADDRESS PAIR

UNC '0'

A,X

R,O
R+1,O

RETURN ADDRESS DEPENDS ON STATE OF
INCR CONDITION AT SUBROUTINE ENTRY

UNC'1'

A,X

R,1
R+1,1

COND

A,X

R,COND
R+1,COND

OPERATION

..
..

ADD R TO R+1

~dd

contents of R to the contents of R+1 if N~V is true.

'0' OR '1'

Fig. 12

MCU NEXT ADDRESS TABLE

Fig. 11

OPERATION - ADD CONTENTS OF R TO THE CONTENTS OF R+1
IF NV + VC + NVC2 IS TRUE.

EXAMPLE: IF NV + VC + NVCZ IS TRUE (T) ADD C(R) TO C(R+1), IF FALSE (F) DO NOTHING.
STR';IGHTFORWARD SOLUTION
EVERY CONDITION INSIDE DOTTED
AREA CAN BE REMOVED.

CROM
ADDRESS

CONDITION

6 BLOCKS TO GIVE 12 WORDS CROM.
MAXIMUM OF 4 STEPS.

ENTER

+

MCU ACTION
CONTINUE TO A,N

A-1,1

6701 ACTION
FINISH PREVIOUS
OPERATION

A,O

N=O

CONTINUE TO A+1,V

A,1

N= 1

JUMP TO A+4,V

A+1,0

V=O

JUMP TO A+6,0

A+1,1

V = 1

CONTINUE TO A+2,C

A+2,0

C=O

CONTINUE TO A+3,2

A+2,1

C= 1

JUMP TO A+6,0

A+3,0

2=0

JUMP TO A+6,0

A+3,1

2=1

JUMP TO A+6,0

ADD R TO R+1

A+4,0

V=O

JUMP TO A+6,0

ADD R TO R+1

A+4,1

V = 1

CONTINUE TO A+5,C

A+5,0

C=O

JUMP TO A+6,0

A+5,1

C=1

CONTINUE TO A+6,0

ADD R TO R+1

ADD R TO R+1

A+6,0
12 WORDS OF CONTROL ROM - ONLY 4 STEPS MAXIMUM

Fig. 13
Fig. 14

-114-

A MINIMUM SOLUTION
[',f!i'

+

CROl\l
ADDRESS

CONDITION

A-1,1

MCU ACTION
CONTINUE TO A,V

A,O

V

A,l

V

JUMP TO A-2,C

A·l,O

N

JUMP TO A,,4,O

6701 ACTION
FINISH PREVIOUS
OPERATION

CONTINUE TO Atl,N

A'1,1

N - 1

JUMP TO A t 4,O

ADD R TO R·1

A-2,O

C - 0

A-2,1

C

1

CONTINUE TO A+3.Z
JUMP TO A t 4,O

ADD R TO R+1

A'3,O

Z

0

JUMP TO At4.0

A'3,1

Z

JUMP TO A'1,N

A·4.0
8 WORDS OF CONTROL ROM

ONLY 4 STEPS MAXIMUM

Fig. 15
OPERATION - 16 BIT 2s COMPLEMENT MULTIPLY
MULTIPLY THE CONTENTS OF R BY THE CONTENTS OF R+1 TO FORM A
DOUBLE LENGTH PRODUCT WITH THE MOST SIGNIFICANT HALF IN R+1
AND THE LEAST SIGNIFICANT IN R.
CROM
ADDRESS

MCUACTION

6701 ACTION

A-1,1

CONTINUE TO A,O

FINISH PREVIOUS
OPERATION

A,O

CONTINUE TO A,l

R+1 TO a

A,l

SET CONTR, CNTR,
TO 14 CONTINUE
TO A+l,OO

CLEAR IH1, SHIFT
ARITH RIGHT Ri-1,O

JUMP TO A+1,OO
IF CC+ 0 DECREMENT
CC.

SHIFr M;1Tl'l RIGHT

A+l,C

CONDITION

00"'0

R+1,O

A+1,1

00" 1

JUMP TO A+1,OO
IF CC+O DECREMENT
CC.

ADD R TO R+1,
SHIFT ARITH RIGHT
RESULT,O

A+2,O

00=0

JUMP TO A+3,O

SHIFT ARITH RIGHT
R+1,Q

A+2,1

00'"

JUMP TO A+3,O

SUBTRACT R FROM R+1
SHifT ARITH RIGHT
RESULT,Q

Ai3,O

CONTINUE TO
A+3,l

aTon

7 WORDS OF CONTROL ROM - 19 STEPS

UNSIGNED MULTIPL Y WOULD TAKE ONLY 5 WORDS OF CONTROL ROM
AND 19 STEPS.

Fig. 16

-115-

9. USE OF THE MOSTEK F8 MICROCOMPUTER
AS A SOFTWARE UART
R. L. BALDRIDGE AND D. LINDSAY
APPLICATIONS ENGINEERS
MOSTEK CORPORATION
CARROLLTON, TEXAS
The Mostek F8 I.C. family permits the design of a complete
microcomputer system using only two chips, the MK3850 Central
Processing unit (CPU) and the MK3851 Program Storage unit (PSU).
This paper describes an actual application of these chips in the
development of a full duplex software UART for Teletype I/O.
This software UART forms an integral part of Designer's Debugging
Tool I (DDT-I), a software package developed as a powerful design
aid for the Mostek F8 Survival Kit. A complete listing of DDT-I,
as well as a schematic of the F8 Survival Kit are given in the
Appendix.
A block diagram of the MK3850 CPU is shown in Figure 1.
outstanding features of this chip are:

The

N-channel Isoplanar MOS Technology
64 bytes of scratchpad RAM
On-chip clock and power-on-reset circuitry
TWo 8-bit bidirectional I/O ports
vectored interrupt capability
2 MHz clock rate
(2~s cycle time)
Over 70 instructions
(most 1 cycle)
Low power dissipation, less than 330 mW
Available in a low cost plastic package
A programming model for the MK3850 is shown as Fig. 2.
The MK3851 PSU is shown in Fig. 3.

Its main features are

1024 bytes of ROM
On-chip programmable timer
TWo 8-bit bidirectional I/O ports
vector interrupt address
l6-bit program counter with stack
2 JJ. s cycle time
low power dissipation, less than 275 mW
available in low cost plastic package
These two chips together therefore form a complete microcomputer with lK of memory, 32 bits of r/o, a programmable clock,
vectored interrupt capability, and 64 bytes of scratchpad memory.
The only external circuitry required to make the system work is a
2 MHz crystal, two 10pf capacitors, and a +5V, +12v power supply.

-116-

MK 3850 CENTRAL PROCESSING UNIT

INTERRUPT
CONTROL . . .-

....

BIT

RESET

POWER
ON
TEC:T

RC

XTAL

Fig. 1

WRITE

ROMC
BUS

DATA
BUS

MK3850 CPU

MEET THE F8 FAMILY
MK 3850

CPU
I SAR

I/O
I/O

I

ItJ
En"~(_'!"'l"r
¥~:J;'!"'l"iJ-rzI

"'-S-4-X-S-B-1T~o

ALU

SCRATCHPAD
MEMORY

Ace
STATUS
REGISTER

I--_~_---I

1110Izlcisi

I--~~--I

POWER
ON
RESET

RESET

CRYSTAL 1---'----.
RC
CLOCK &
EXT
TIMING
CLOCK

. . . - - - - - - - - 1 1 NTERRUPT
REQUEST
INTERRUPT

CONTROL
LOGIC

L - -_ _ _ _--1

__

.........._

~

CONTROL
BUS

Fig. 2

INTERRUPT
CONTROL
BIT

DATA
BUS

MK3850 programming Model
-117-

MK 3851

PROGRAM STORAGE UNIT

EXT INT
REQUEST

CPU
INT

Fig. 3

program storage unit (PSU)

-118-

The next section describes the use of these chips as a software UART and also presents some design considerations for general
applications.
THE SOFTWARE UART
This design example illustrates some of the outstanding features
of the Mostek Fa 2-chip microcomputer, in particular the use of the
programmable clock, the bidirectional ports, the vectored interrupt,
and the scratchpad memory.
Problem:

Design a software UART for full duplex teletype I/O.

Systems Analysis
I/O Requirements:
Data width - 1 bit in, 1 bit out
I/O rates - 110 baud in and out
Peak I/O rates - 300 baud
Timing required - send bit time, receive sample bit time
Data storage requirements:
OB
OC
IB
IC
AS

-

output buffer
Output counter
input buffer
input counter
accumulator save register
J - status save register

The data storage requirements are thus well within the 64
byte scratchpad capability.
Design
Fig. 4 shows the timing for 110 baud asynchronous ASCII with
1 start bit and 2 stop bits. The sample bit times and send bit
times are shown relative to the programmable clock which divides
each bit interval into a timing slots. When sending an ASCII
character the output counter is initialized to 157 1 (HEX) when
the start bit is sent, thereby establishing bit times every a
counts, Qr when the last 3 bits of the counter are all ones. When
the counter counts down to IFFI (HEX) the output is finished.
Similarly, on input when a start bit is detected the input counter
is set to 149" (HEX) and sample bit times also occur every a counts
of the clock.

-119-

-OlT-

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The flowcharts for accomplishing this task are shown in Fig. 5
and are keyed to the DDT-l listing in the Appendix.
SOFTWARE UART DESCRIPTION
Fig.
operation
registers
output in

5 (a) shows the power on initialization required for
of the software UART. The input count and output count
are initialized for "No input in progress", and "No
progress" respectively.

To output a character a call is made to subroutine TC shown
in Fig. 5(b). After saving the return address, a check is made to
determine whether an output is already in progress by examining
the output count register (OC) for a positive value. When any
existing output has finished the character to be sent is moved
from the appropriate scratchpad register into the output buffer
(OB). The output count is initialized to Hex 157 1 and a call
is made to the timer interrupt routine (TI) to output the start
bit, start the timer,and enable interrupts.
(Refer to the state
of the output counter on the I/O timing diagram of Fig. 4)
To
input a character a call is made to subroutine KC (Key-in a character) shown in Fig. 5 (c). This routine saves the return address
and waits for the input counter to be counted down to Hex IFFI
by timer interrupts. When the input finishes the input counter
is set to Hex IFEI - "ready for another input" and the assembled
ASCII character is moved from the input buffer (IB) to the userls
scratchpad register.
The timer and keyboard interrupts are handled by routine TI
shown in Figs. 5 (d), (e) and (f). This routine is responsible for
loading the proper count into the programmable clock, detecting the
start bit of an inpu~ and sending the start bit of an output. It
also determines the I/O bit times, or when to send the next bit on
output or sample the next bit on input. On output it shifts each
bit of the input buffer out to the TTY port at the bit times shown
on Fig. 4. On input it samples and shifts each bit into the input
buffer at the bit times also shown in Fig. 4. I/O ceases when the
appropriate counter counts (IC or OC) down to a negative value
(Hex IFF I ). In this way simultaneous input and output may take
place on two different bit positions of the same bidirectional
I/O port. The schematic for the Mostek F8 Survival Kit in the
Appendix shows Port 5 being used for this purpose.

-121-

power on reset

0000

003B

HIFEI .. IC
HIFFI + OC

set I/O counters to
no I/O in progress
type carriage return, line
feed, followed by 1 . 1

N

execute
co nun and

DDT-l conunands
B
C
D
E
L
M
P
T
H

-

Breakpoint address
Copy memory arrays
Dump memory to tape
Execute at specified address
Load memory from tape
Memory content display and modify
Display ports and modify
Type memory content array
Hexadecimal arithmetic

Fig. 5 (a) -Power on reset

-122-

035D

N

0360

(OC ~ 0)

0364

move
character
to OB

0365

disable
interrupts

0368

set output
count

0369

call

TI

035A
supply
line feed

y

0370

Fig. 5

(b)

wait for any
existing output
to finish

Type A character

-123-

H 1 571-+0C

Generate a software
interrupt to timer
interrupt handler
to output start bit,
start timer at proper
baud rate, and
enable interrupts.

03F3

KC

N

03F6

03F9

set input
ready

03FC

IB -+RS

03FD

Fig. 5 (c)

Input A Character

-124-

H'FE'

wait for input
counter to count
down to H' FF' (-1)

~

IC

put assembled
character into
caller's scratchpad
register

(

Timer or Keyboard
Interrupt handler

037E

037F

)t---------s;:..,.

TI

~----------

r-----~~----~
save

037F

Accumulator and status

A, W

0387

300 baud

0383

038B
load clock
with
69 counts

1.070 ms/interrupt

load clock
with
24 counts

IC O?
038E

03A3
save
output
bit

:>--4---1II1II

shift in
next data
bit ~ IB

03AA
set input
count

Fig. 5 (d) -

IC-l-+IC

y

disengage
reader
clutch

H1491~I

0390

N

03A7

Timer interrupt handler

-125-

.372 ms/interrupt

Decrement
Input counter

03AB

OC~O

03AD

N

Decrement
Output Counter

03AF

N

03C8
y

set OC
for 1 stop
bit

shift out
next data
bit

• O'

03Cl
03D4

set
output
b1t

03D6

Fig. 5 ee)

Timer Interrupt Handler Cant.

-126-

clear
output
bit

03D8

enable
timer

03DE
03DB

03DF

N

restore
A,

03El

03E2

Fig. 5

(f)

W

enable
CPU
interrupt

Return

Exit from interrupt handler

-127-

enable
keyboard
interru t

disable
timer
interrupt

accumulator and status

How To calculate The Clock Count
In order to obtain the proper clock constant to provide for system
timing is is necessary to take into account:
1.

Clock countdown time before interrupt.

2.

Interrupt latency time - or the time required for the CPU
to finish its current instruction before acknowledging the
interrupt.

3.

Interrupt cycle time - the time required for the CPU to
acknowledge the interrupt and transfer control to the
interrupt service routine.

4.

Program overhead - the time spent to save registers, status,

Fig. 6 depicts the timing for a single clock cycle, showing the
hardware and software times involved.
These times may be computed as follows for the Mostek F8 software UART:
Interrupt latency time
=

Time required to finish a 2 cycle instruction

=

1 instruction x 2 cycles
instruction

x 2,,{,(s
-=---cycle

Note: The interrupt latency time may vary depending on the
point at which the interrupt occurs during an instruction, how many cycles the instruction requires,
and whether the instruction is privileged (i.e. the
next instruction must be executed before acknowledging
the interrupt). For the Mostek F8 this can be a variation
of 0 to 25).-ts. However, many of the instructions are
single cycle, hence the above figure of 2 cycles is intended to be a representative average.
Interrupt Cycle Time
Upon recognizing an interrupt, the Mostek F8 goes through
a 5 cycle sequence in order to obtain the vectored interrupt address.
This gives
5 cycles x 2A s =
cycle

10l{s

-128-

Timer Interrupt
Handler
Main

Main

A

B

C

D

E

F

EVENTS
A

Program loads clock counter

B

Clock requests CPU interrupt

C

CPU acknowledges interrupt

D

Interrupt service routine begins

E

Interrupt service routine reloads clock counter to begin
next cycle

F

Clock interrupts again etc.

TIME INTERVALS (explained in text)
TAB

Clock countdown time (Hardware)

TBC

Interrupt latency time (Hardware)

TCD

Interrupt cycle time (Hardware)

TDE

Program overhead (Software)

Fig. 6

Timing for one clock cycle

-129-

Program Overhead
Referring to the DDT-l program listing in the Appendix at
location 037E(Hex) it is seen that 10 instructions are executed
before the clock counter is loaded again. The cycles required
for these instructions may be added
Cycles

Instruction

1
1
1
2.5
4
4
2.5
3.5
2.5
4

NOP
LR
LR
LI
OUTS
INS
NI
BNZ
LI
OUTS

26.0 Cycles
and the program overhead time computed as:
26 cycles x 2 )v"s
cycle

=

52 As

Hence the clock countdown time required to obtain the proper
timing for the Teletype I/O becomes:
CDT = 1 I/O BIT PERIOD
8 clock periods

-

(Interrupt Latency Time
+ interrupt cycle time
+ program overhead)

For the software UART example this gives:
Clock countdown time = 9.09ms

-(4~s

+ 104s + 52As)

8

=

1.136ms -

.066ms

=

1.070 ms

The clock countdown time is a function of the system clock on the
Mostek F8 as follows:
CDT =

(System clock period)x(clock count)x(3l)

The clock count for the example may therefore be computed as:
Clock counts = 1.070 ms
500 ms x 31

= 69

-130-

Hence to establish the proper timing a count of 69 is loaded
into the programmable clock of the PSU.
OTHER APPLICATIONS
The Mostek F8 I.C. family may be designed into a wide variety
of applications. For example, a motor controller may be implemented
with 2 chips as shown in Fig. 7. Consistent timing may be obtained
by using the on-chip programmable clock as a reference. An optical
tachometer generates a symmetrical pulse train related to motor
speed, the microcomputer computes the speed and compares it to a
desired reference, then generates an error signal to speed up or
slow down the motor as required. Another example is the cash register
system shown in Fig. 8. Here the Mostek F8 scans a keyboard, controls a printer, and also drives a display. These functions may be
multiplexed through the bidirectional I/O ports by using the programmable timers and the external interrupts provided on the PSUS.
This example also demonstrates how the basic 2-chip system may be
expanded upward in complexity as the application grows using other
I.C. chips in the Mostek F8 family. Fig. 8 shows an additional
psu added to the F8 bus to control the printer; Fig. 9 shows additional I/O ports added with the Mostek MK 3861 peripheral I/O
(PIO) chip; Fig. 10 shows how to add additional RAM memory by using
the MK 3853 Static Memory Interface (8MI); and finally, Fig. 11
shows how to add erasable programmable ROM into the F8 system.

-131-

THE MINlMUM
F8 SYSTEM
MK 3850 CPU &MK 3851 PSIJ
provide all the I/O and motor

control capabilities.

E

TELETYPE

Fig. 7 -

OPTICAL
TACHOMETER

MOTOR

Mostek F8 as a motor controller

-132-

F8 CASH REGISTER APPLICATION

PRINT

PULSES

PRINT PULSES

Fig. 8

Mostek F8 application adding additional PSUs

F8 CASH REGISTER APPLICATION
511KO

ADDITIONAL

I/O

Fig. 9 - Adding more I/O
-133-

F8 CASH REGISTER APPLICATION

CPU=-.__It\
PRINTER
COMMANDS

511KO

'-!I~~---'"

RAM

Fig. 10 - Adding more RAM

F8 CASH REGISTER APPLICATION
PRINTER

511KO

2K x 8

PROM

Fig. 11 - Adding PROM
-134-

APPENDIX

PAGE

**

ALL SUBROUTINES lJSf SCRATCHPAO REGISTERS C,O (K REGISTER) TO SAVE PCI,
PFRMITTTNG I~TERRUpT~ ~T A~Y TI~f. INTERRUPTS IJSE QEGISTERS 8.9
* (~S,J) TO SAVE ACC,W. ~NO REGISTERS 4.5.6,1 (IC.IR.OC.08) TO PF.RFORM
* FULL ~UPLEX 1/0.
XU
f:QIJ
H'"
X REG I STERS
XL
fQU
\-f'l'
YU
EOU
H'?' Y REGISTERS
YL
EaU
H'3'
INPUT COUNT REGISTER
IC
EaU
H'4'
IR
EDU
H'S' INPUT AYTE REGISTER
OIJTPUT COUNT RfGISTER
OC
EOU
H'6'
OUTPUT RYTE REGISTER
OR
EOU
H'7'
AS
EOU
H'A' Arc SAVE REGISTER (fOR INTERRUPT ONL Y! )
..J
EOU
H'9' J REr,ISTER (fOR INTERRUPT ONLY!)
HlJ
EOU
H'A' HI! Rf.GtSTER
HL
EOU
H'B' HL REGISTER
PT
EQU
H',:)' PORT FOR TELETYPE 1/0
PORT FOR INTERRUPT CONTROL
PI
EOU
H'~'
PORT FOR TI~ER COUNT
PC
EOU
H'7'
TO
EOO
H'4;;' TElETYP~ OUTPUT CODE
TR
EaU
H'20' TELETYPE READf.R CLUTCH CODE
T8
EOU
H')" TELETYPE RAUO RATE
tt-

*

* POWER ON

iooo
1000 00 3A

.

i002 16
i003 00 AD

£2

io05 ~~

BE

*

of

.*

ORG H.... OnO.

IN
RFENTRY JUMP OFF
LM
DC
H'9.AO' RRANCH TO REENTRY AT FFBI
AQEAKPOI~T

.006
it007 ?A Ft! BE
ioo~

Del

17

CiT

;OOB r)A
tOOC 17
iOOD ~O
~Ot)f I-.A
i(H}f 40

'&010

17

;'011 49

ioi2

if

i013 F9
i014 so

~ois r9

ioi6 C;9
tOl7 FO
ioia so
iOl9 4C

;'0 I A 17

LR
LR

REO

LR
ST
LTSIJ
LISL
LR
ST
LR
LR
XS
LR
XS
LR
XS
LR
LR

ENTRY
A,QL Rf.STORE Ace AFTER JMP

a,or,

H'FFRE'
STORE Ace
STORE ISAR

o
f)

A,J
J,W
J
O.A
J
J,A

STORE RO
J TN ACC
W IN J
J/W IN ACC
...J/W IN RO
J RACK IN ACC
RESTORE J

O,A
A.S

SAVE W IN RO

o

5T

-135-

F"~X

iaiR

V~l

PAGE

CA

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17

F"~

~O~7 ';1
~O28 17

~O?9 40

17

~O?R ';)14 FIi= 85

90?E 16

~O?F

RP\Jl

BE']

STI)QE QEST OF SCRATCHPAD
H'FF"8B'
K.P
.~,KU

A,KL
ST(l~E

PCI

A.O
ST()Rf: W
H'f"FR5'

L~

n6

LP
LM
LR
LIS
LR
LR
LIS
LR
LR
PI

;010 16

8011 07

0012 70
,033 c;0
~014

A. IS
H'CI'
IS,A

OCI
LR
LR
ST
LR
5T
LR
ST
DCI

SA

~O?'5 ~O

80?A

LR
AI
LR

2

C;C

"0'35 73
0036 Sl
&031 11
0038 ?A 02 CA

QU.A
aL.A

SFT Q TO OLD

ARE~KPOINT

~·O'

XU.A
S.A
H'1'
XL.A
H.DC
CHQ

SfT INCREMENT
SET COUNT
SFT H TO START OF" OLD CODE
COpy RACK INTO PROGRAM

*

INITIALIZE
TR
LI
q5
OUTS PT
';)0 F"f;:
LI
H'FF'
')4
IC.A
LR
14
OS
IC
c:;6
OC,A
LR
,..7
IN~
LISU 7
,..F
LISL 7
PI
0045 ?A OJ 50
TCI
~

()03B
!030
103£
&040
0041
~O42
0043
i044

?O ?-I

IN

**
004A

';){' 26

~04A c;C
i04B ?8 OJ 50
;04E ?A 01 F3
i051 ?~ ()J 50
0054 ,..E
e055 ';)A OJ 54

iOC:;A 70
C~C:;9 ';ft
(tOC:;A 07

~05B f'..E
~05C c;E
"05D 70
OOC;E C;A

&05F

C;R

Fe

FfTCH COMMAND
LI
C'.'
S,A
LR
PI
TC
PI
KC
PI
TC
LISL 6
PI
TC?

DISENGAGE READER CLUTCH
SfT INPUT COUNT REAOY
SFT OUTPUT COUNT COMPLETE
TYPE CARRIAGE RETURN. LINE FEED

TYPE :;,;
KEY IN CHARACTER

ECHO CHARACTER
TYPE SPACE

*
EXPRESSION
*Of. DFCOOf
LIS
'l

LR
Of7

LR
LISL
LR
LIS
LR
LR

QU.A
QL.A

Cl.F"P

Q

6

O,A

SFr SIGN ( ISAP=1D)

0

HU,A
Hl,A

CLF"AR H

-136-

F"AX V1l1
'060
,063
e066
i067
.069
i06R

PAGE

;>A OJ F3 DEll
OJ SO
4C
;>5 2i
A4 OQ
;>5 2fi:
:;>~

i060 Fl.?

(tQ

i06F ?S 39
e071 ~? 3C;
8073 ?c:; 4.
007S ~? GS
i077 :;>5 46
t079 P.2 36
DEO
0078 ~c:; 2A
e07D P4 42
007F" ;>S 52
eOAt A4 41
.083 "f.
,084 4£
tOAS ;>5 20
0087 Q4 06
80A9 ;>8 OJ 71
tORC QO 04
,ORE :;>B 8l E1 DES
iOQl 4C
OE6
"092 ;>c; OA
00Q4 P.4 46
i096 ;>5 28
i098 A4 C2
i09A :;>S 20
i09C P.4 8~
!09E :;>5 3lJ
eOAO ~4 2":
lOA? ?S Si
eOA4 .P.4 3.
IOA6 , 1
eOA7 4A
iOAR C:;?
eOA9 4A
OOAA «;3
GOAB oF"
iOAC ~o AS
DEI
iOAf. ::>4 01
Of.:?
OORO ::>4 C9
iOR2 CiC
iOR3 4A
eOR4 lS
tORS C;A
~OA6 4A
iOR7 14
ftOR8 CA
;OR9 C;A
tORA 48
OORB 15

PI
PI
lR
CI
AZ
CI
Re
CI
BC
CI
BC
Cl
BC
CT
8Z
CT
R7
LISL
LR
Cl
AN7

KC
TC
A,S
C'.'
IN.
H'2F"'
DEe
C,q,
DEI
H'40'
DEt
C'F'
(,)E2
C'*'

PI

SU

AP
PI
LR
C1
AZ
CI

DE6
AD
A.S
H'A'

A7

CI
AZ
Cl
B7
CT
HZ

LR
LR
lR
LR
LR
LR
BR
AT
AT
LR
LR
SL
LR
LR
SR
AS
LR
LR
SL

3

KEY IN CHARACTER
fr.~O

IF"

CHARACTER

., GO START NEW LINE

fF" REF ORE 0, IS ENO OF CONSTANT. GO ADD
IF" 0-9, GO CONVERT
IF" :-AT, GO AOD
IF" A-F" • GO CONVERT

DE3

IF" *. GO PUT DC INTO H

C'R'
OE4

IF" R. GO PUT FF"Ce INTO H

6

A,(')
C'-'
DES

E

C,+,
DE7
C'-'
DE7
C'='
DEB
H'SE'
DE9
H,DC
A,HtJ
YU,A
A,HL
YL,A
DC,Q

crC::;AR=3D)

-

SF:T, •••
IF"
SUR TRACT H FROM
Ann H TO

Q

Q

IF" CARRIAGE RETURN, LINE FEEO. (;() EXECUTE COMMAND
IF" +• .,.
OR

-.

(;0

START NEW H

IF" =. GO TYPE

Q

IF" CARAT, GO DECREMENT DC

TRANSF"ER DC TO Y•••
ANn t) TO DC

DE
H'17' CONVERT 0-9
H'CQ' CONVERT A-F
S,A
A,HU
4

HU.A
A,HL
4
HU
HLJ,A
A,HL
4

-137-

fA)( V~l

PAGE

io~e re

iOBD
eORE
ioeo
iOCl
tOC3

CiA

tIJC5

CiA

QO GA
il
QO ·~l
::>0 f ..

DE3
OE4

eOC6 ;:»0 ce
OOC8 C;R
~OC9

~E

iOCA
iOCB
iOCD
aOCE
0000
io03

4C

Of In

;.~ 2~

01

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QO 9t
:::>8 ttl IF' rJE~
QO 81
OOf)S ;:»A OJ 50 DEq
t008 ::>0 FE
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...

io08 f,F'

iooc

8000

ioof
iOEl
00E2
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8«)E8 c;?

80fC ift
iOED C;3
~OEE :::>A F" J3J
00F"1 ::>0 2A
iOF"J i7
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iOs:"6 43
eOF'7 17
f,OF'B 70
iOF'9 17
~OF"A 10
10F'R ~?

eoF'C 17

iio2 1(,
;'-,03 ';4
0104 1(,
~j05

oS

PI
RR
PI
LI
AOC

... EXECUTE:
lISl
lR
CI
BNI
LR
Ea
NS

RP
01
OCI

LR
lM
lR
LM
lR
OCI
LI
ST
LR
ST
LR
ST
lIS
ST
lR
LQ

S
Hl.A
DEIO
H.De
DEIG
H'FF"

SHIfT IN DIGIT
r,n SET DATA ENTEqEO
PUT OC INTO H
GO SFT DATA ENTEQEO

..,.U.A

H'CO'
Hl.A PUT F"F'CO INTO H
6

A,S
H·Zq· ANO OF' +,D,A
MAKE SIGN NONZERO (ISAR=3D)
DEll
TO
TYPE Q
DE7

TYPE CARRIAGE
TCI
H'FE'
OfrREMENT DC

~ETURN.

7

A,S
C'E'
8

A,IC
OC
EO

IF' NOT E. GO TRy B
WATT fOR 1/0 TO FINISH

H'FF'CE'
H,OC
YU,A
Yl.A ffTCH DC
H'F'F'Al'
H'2A'
QFf."ITRY:

A.YlJ

OCI •••

A.Yl
VALUE OF DC •••
H'O'

LR PO.Q

OC.H
A,QU

ST

iOFO ~~

tOF'E 17
ioF'F' ?A

LR
BP

E

4C
?S 45
Q4 4A
44
F"6
At FD
iA
?A
CE

90E6
iOE9 1 I
iOfA ift

AS
lR
BP
lR
f3R
II
lR
IT
lP
lISL
LR

4

f~

SR

lR
ST

A,QL

OCI

H'FF"R8t

PLf\CE Q F'OR RESTORING

L~-1

LR
LM
LP

KU.A
KL.,A

-138-

lINE FEED

FRX

V~1

PAGE

ii06

OQ
!l n1 ";)A ffi:

cn

OIOA flO
ilOA ~A

;ioc

iioo

1f1
C;C

E1

ijOE oA
'IOf ";)4 CI

iiit

;11 2

~8

L~

Q4 f9

f)114 ?A f': AD
iii1 16
~li8 F9
0119

nR

iiiA nA

011A fQ

iilc

LR
OCI
LISU
LISL
LM
LR
LR
AT

r::;Q

'liD

OA
tIlE f9

AN7.
DCI
L~

XS
LR
LR
XS
LR
LR
XS

ii23

.,8

i124 ?A ff: 8f

LR
LP.
LM
LM
LR
OCI

Oi27

;>9

J~P

011f Hl

ii?o
e)~t

itl?2

59
16
16

G.

O?

il2A ?5 42

ii?c Q4 21

.i2E
ii31
il32
il13
ii34
ei35
,,136
t.i37
,j38

?A Ffi: Be;

.;?
c;A
11

~3

c;B

11

oE
70

8119 C;O

ii3A r::;c

0138 73

iilC c)l
ii3D ?A G2 CA
i140 ";)0 Fe
~142 AE
0143 71
i144 11
.i45 ~o
0147 11

jj48 70

1149 11
ii4A 7S
3i48 11

2~

* BQEAKPOINT
*
R
CT
FJNZ

DCI
LR
LR
ST
LR
LR
ST
LR
LIS
LR
LR
LYS
LR
PI
LI
AOC

LIS
5T
II
ST
LIS
«;T
LIS
ST

5

P,K
RfSTORE PCI
H'FFe.'
I)

0

S,A
A,IS
H'Ct'
IS,A
RE<;TORE SCRATCHPAO
El
H'FFRO'
F'FTCH W
J/W TN ACC
J
IS"A J/W (AITS 5-0) IN ISAR
A"IS e.JI"I IN ACC
J,,"I IN ACC
J
J,IJ IN J
J,A
A,IS '.J/W IN ACC AGAIN
J
.. I IN ACC
W,J
W TN \.II (RESTORES INTERRUPT)
J.A
J TN J
IS,A RfSTORE IS.AR
H'FfAE'
GO RESTORE ACC. ANn REENTER
F:?
C'R'
C
IF" NOT 13, GO TRY
H'F'FA5'
A,QU
HU,A
A.QL
HL,A

C

TRANSfER BREAKPOINT TO H•••

AND STORE

Q"DC

SFT

Q

TO

CODE

LOCATION

H'~'

XU,A
S,A
SFT INCREMENT
H'3'
XL,A SFT COUNT
COpy OUT Of PROGRAM
CHQ
H'rc'
SET OC BACK TO TRAP
H'7'
TRAP: LR Ql.A •••
H·?9'
JMP •• t
H·t"

H'te;'

TO BE (AT OOOS)

-139 -

fAX Vnl

PAGE

ii4C 00 32

C2

** cnpy
* THIS ROUTINE
* IS MfT:
*

*
*

i14£

•
C

~5

4l
i150 Q4 31
,1:S2 42

('153 SA
Oi54 43
0155 c;R
ii56 ~?
&iS1 r;?
~1C;8 FA

iiSq

£iC
elSA ~3
iisA C;3

iir:;c

cf.

iiso ?A oJ
.160 O?
e161
0162

11

C;f)

~,

ii63 C;)
0164 42

iif,S

;'6

~j66

41
Oi61 01
,,168 ;»A OJ E3

0168 O?

ii60 Q) OQ

Ol6F

11
~i70 ?8 OJ £3

i173 ;»0 Fi
0175 ClO e5
il71 ?A f)l 7) CO
f,11A 70
CI
i'78 C;C
~i7C ~A GZ CA
;»9 •• 4A

I.

GIVES CORQECT RESULTS

W~EN

1 OF

TH~

FOLLOWING CONDITIONS

THE NFW ALOCK LOCATION DOES NOT OVERLAP THE ORIGINAL.

THE BLOCK 5TART ADDRESSES ~~TCH IN RIT is (THAT IS, ARE.ON
THE SA~E 5IOE OF THE 1F"FF/Ae"o BOIJ~DARY).
3. THE SHIFT S'-~ IS NOT IN THE RANGE -8,G~47FFF.
CI
C-CBNZ
0
IF ~OT C, GO TRY 0
LR
A,YtJ
LR
HU,A
LR
A,YL
LR
~L,A
TPANSFER 5 TO H
LQ
A,QU
LR
YU,A
XS
HU
L~
S,A
SAVE SISLR
A,QL
LR
YL.A SAVE 5- IN Y
LR
Q,OC TRANSFER f TO 0
PI
SU
COMPUTE f-S=COUNT IN Q
LR
A,QU
LR
XtJ.A
LR
A,QL
LR
Xl,A TRANSfER COUNT TO X
LR
A,YU
LR
QU.A
LR
A.YL
LR
OL.A TRANSfER S- BACK TO Q (-5 STILL IN H)
PI
AD
COMPUTE S'-S=SHIFT IN 0
?

LR

~16C F:C

ii7F

6

XS
8M
LR
PI
L!
Aq
PI

LIS
Lq
PI

'A.QIJ

5

cn

5/5'/(5'-5)

IF S'-S NEGATIVE. GO COpy FROM START
H.OC TRANSfER f TO H
AD
COMPUTf (St-S)+F=F' IN Q
H'FE' SET OECREMENT
Cl
SU
AA~K TO S IN H. S. IN Q
~-8'
SFT JNCqf.MENT
S.A
CHO

C2
J~p
FC
* THE STARRED-OUT COpy AND SIJ8TRACT RQUTIN(S RfLOW GIVE CORRECT RESULTS
.. FOR ~LL CONDITION~.
it COpy
*C
CI
C'C'
*
8~Z
0
It NOT C. GO TRY 0
*
LR
A9YU
*
lR
HU,A

..
..

*

Lq
LR
Lq

",YL
HL,A

",au

TqA~SFER

S TO H

-140-

fAX

V~l

PAGE
lR
lR
lR
LR
PI
lR
LR
LR
lR
PI
LR
LR
LR
LR
PI
QC
PI
LIS
AR
LR
PI
LI
LQ
PI

*

*
*
*
*
*
*
*
*

•
*
*
*
*

•

*
*
*
*
*CO

*

*
*CI
*
*C?
*

iiA2 ::»5
i184
iiA6 ?6
ilR8 c;1
ilR9 11
iiAA 50
.lAB 70
~j8C C:;C
tiRO ?A

44
60
12

Q4

fa

~4

il90
ij91
oi93
0195
it96

ii99

10

OJ

•

I)

50 00

?O 2A

c;C

?8 03 50 01

"'

ii9A Q4 fB
ii9C ?8 tJ 50
ii~f ?O 5l

itAl

itA2
elAS
iiA6
iiA9

OJ

50

1I

?A ~J 71

n?

~lAA c;0

elAR it3
ilAC c;}
ilAO

nE

C;AVE S· IN Y
TRANSfER f TO Q
COMPUTE f-S=COUNT IN

Q

XlJ.,~

A.Ql
XL.A
SU

TRANSfER COUNT TO X
RACK TO S IN H

~.YU
QU.~

A.Yl
aL.A
SU
CO
SU
H'~'

Cl
H.OC

TRANSfER S· BACK TO Q
COMPUTE C;'-S=SHIFT IN Q
IF' S··(ltOOft-5).GE.IOOeO. GO COpy
RACK TO 5 IN H. S' IN Q
SET INCREMENT

J~P

TRANSfER f TO H
COMPUTE (S'-S)+f=f' IN a
H'fE' ~F"T nrCRE'MENT
S.A
CHQ
fC

CI

C'O'

AN:?

M

AD

IMP
LI
LR
SL
LR
LIS
LR
PI
OS
RN?
LI
lR
PI
OS
RNZ
PI
II

c;C

?8

1)1

YU.A
A,Ql
YL,A
Q,OC
SU
A,QU

7

LR
PI
LR
PT
lR
lR
lR
lR
LR

IF' NOT 0. GO TRY M
H't?'
XL,A SFT COUNT fOR LINE Of *S
1

XU.A

~FT

COUNT fOR NULL LEADER

H''''
S.A
TC

PUNCH NULL

DO

GO REPEAT

C'··
S.A
TC
XL

PlINCH

01

GO REPEAT
PUNCH CARRIAGE RETURN. LINE fEEn

xu

TCI
C'SS.A
TC
H.OC
SU
A,aU
XU,A
A.Ql
,XL. A
Q.OC

*

PUNCH S
SUR TRACT TO fIND COUNT •••

AND TRANSfER TO X

-141-

fRO~

fINISH

FAX V~t

iiAE

~A

PAGE

el IF

ii~l ;»8 OJ 50
q 4 ;»0 58
01
OlR6 C;C

ti

iiq1

~B

ijqA 70

.OJ 50

1'188 t;~
~i8C 78

,jAO
~lBE

elRF'

iico
eJC3
iic4
iic6

1:)3

16

~7

?A
11

O?
OJ lA

c)4 fg

8NZ

4?

LR
LR
PI
PI
LR
At
LP
BC
OS

,jC1 t;C
&lC8 ;»8 OJ 40

iicA ?~
iicE 41

O:i 50

~!Cf ?4 fa
tH>l Sl

iio2

01'14

P? Et
10

91 05 P2 De;

.,101 ?O 13

0109 c:;l
iiDA 13
~in8 so
iioc ;»0
c;inE I:)C

OIDF

CIE2
!tiEJ
iiJ:5

?~

2A

oJ 5D 04

11
C)4 Fe
?B

OJ

50

iiE8 70
~lE9 '=;C
OlEA ?~ OJ 50 05
~!ED '0
e>JEE Q4 FB

iiFO

QI}

iiF2 ?5
ilF4 C)4
iiF6 18
ilF1 Sf
OlFA ?A
iiF"B .gF

,ilFC
01F"0

iiFE
elFT

06

**

40
16

M

~F
~7

?R oJ 5 /+
0;»02 ='F' nJ JR
0?0'5 ?S3 OJ 54

~" I

PUNCH X

YU.A

CLEAR CHECKSUM

H1 8'

YL,A

OL,A
TaL
YL
02
A,YU
S,A
TH
TCl
A.XL
HIFS'
XL.A
03

SET BYTE r,OUNT
PUNCH

~YTE

GO REPEAT
PUNCH CHECKSUM
PUNCH CARRIAGE RETURN. LINE fEED
DECREMENT BY 8
GO REPEAT

XU

II
LR
SL
LR
LI
LP.
PI

H'12'

Xl.A

GO qEPEAT
S'5:'T COUNT fOR LINE Of

I

*s

SET COUNT fOR NULL LEADER

~C;

XU,A
C'·,
S.A
TC
XL

ANZ

04

PI
LYC;
LR
PI

TCl
H'O'
S.A
TC
XU

GO REPEAT
PIINCH CARRIAGE RETURN. LINE fEEn

BNZ
BR
MFMORY
CI

COM
LP
PI
LR

D5

LR
LR
PI

PI
PI

PU:~CH

*

PUNCH NULL
GO REPEAT

C2
cn."
MU

IF NOT M, GO TRY MU

D.A
TO

C;~T M UPDATE
TYPE DC

MOnE

(ISAR=3E)

OC,O

LM

lA

PUNCH DC
PU~CH CARRIAGE RETURN. LINE fEEn

0

03

R"I7

IF MO

Ta
TCl
C·x.
S.A
TC

BC

O~

ag

~J

PI
PI
LI
LR
PI
LIS
LR
LIS
LP
LM
LR
PI
OS

8

OCtO
OltA
TC?
TOl

TC2

rETCH RYTE
RrC;TORE nc
C)AVf. 8YTE
TYPE SPACE
TYPE AYTE
TYPF SPACE

-142-

F'AX Vr.t
0708 ?9

,.

PAGF:
SA

i70R ?S RJ

t70D Q4
i70F' ~E

O?iO

,0

J~P

~C

9

0714 17

0715 ?O OJ

0;;17

i?ia

16

nE

MUO
MUI

6719 00 Oi
t?iB ?S 51
0210 Q4 16
i?iF" i8
e7?O C;E

*
*

P

t??l 03
i7?2
i?24
i:)?5
i;;26
t??7

G??B

O??9
i??A
i?2A
i??C
i?2F'
0232

71 00

C;C

1F
12
C:;1

rl
(1

IF'
C;l
?A OJ 40
78 02 f7
QO CB

i?J4 ?S AF
t?J6 Q4 08
i?3A ~E'
0?39

i?SI

C)4 52

**
L

C:;O

?A
4C
7S
A4
?S
A4

OJ EC L2
53
1.

58
24

IF" NOT MlJ. GO TRY P
IF" NO DATA ENTERED, GO INCREMENT DC
UPDATE
TYPE NEW LINE
IN~qEMENT OC

(;0

GO TYPE NEW LINE

C'P'
PU

IF" NOT p, GO TRY PU

D,A
A,aL

SrT P UPDATE MODE (tSAR=3E)

H'OO'
S.A

SAVE RATIONALIZED PORT NUMBER

1

XL,A
XL
XL
XL.A
TH

STORE PORT ACCESS AnDRESS IN XL
TYPE PORT NUMBER

PA

Ml

* P()RT UPDATE
*
PlJ
cr
H'AF"'

~D

?5 4(;

UPDATE
H'8?'
P
AN?
LISL 6
05
5
ANC
MUO
A.aL
LR
ST
t..1Ul
AR
LM
Q.DC
LR
AR
MO

P(')RT5
CI
RNZ
COM
LR
LR
NI
LR
INC
SR
LR
AS
AS
INC
LR
PI
PI
AR

07JA Q? 81
i73C ~l
i?3D ?A 82 F'7
PUO
i?40 00 AF
0742
i744
i?46
'747
074A
i?4B
'740
i?4F"

DE

*
*t..1U M~MORY
CT

i?il 07 05
7 j3 .1)1

9

GO TYPE' LINE

RNZ

L

IF" NOT PU, GO TRY l

LISL
OS
BNC
OS
PI
BR

6
I
06

(YC;AR=lf)
IF" NO DATA ENTERED. GO fETCH

CI
BNl
LR
PI
LR
CI

CI

C'L'
T
XU. A.
RC
A.S
C'S'
LO
CtX'

BZ

II

XL
PA
06

LOAD

87

IF" NOT L. GO TRY T
READ IN CHARACTER
IF" S, GO SET DC

IF' X. GO READ 8 BYTES

-143-

NE~'

COMMAND

FAX Vnl

0?53
,?55
,?57
0758
i?59
e?5B

i?r;E

O?5 r
(:762

;:»5

PAGE
2A

Q4 Fi
70
(';0

Q4-Ea
79 01 41 L4
tiO
It'
~B 02 DC

i?73

Ll

t?77 IjO
1278 52
8?79 78
C?7A til

t-?A3

r.3

0784
0?85

'11

Ol DC L3

077F
i?80 ?8 43 DC

i?86
i?aB
i?89

17
Q4 F4

i?'8F

E'3
~4

Bl

0?91 ~E
i?92 ?A Ol JF"
0;)95 QO 8t
0?97

&?9q

;:»5

T

Q4 A6

O?9R 11
i?9C ;:»A
i?9F ;?
O?AO so
8?Al
'f?A2 C;1

O?A3

54

.,a

•.

...

~.

AND DATA READ ••••

r;o FETCH NEWCOM,...AND

YL.A
RH
YL
QU.A
RH

4
YL •.A
RH

YL
QL,A

oc,o

RQ

L?

LIS
LR
LR
LIe;
LR
PI
SL
LP
PI
AS
ST
OS

H .~)t

SF.T

DC

XU,A

SET

YlJ,~

CLF~R

DATA READ
CHECKSUM

~'8'
Xl,~

SfT BYTE COUNT

RH

4
YL,A
RH
YL

LOAn BYTE INTO MEMORY

XL
L3
H'F'
YU
YL.A

LIS
NS
LR
PI
XS
8Z
LR
PI
RR

YL
L?
Q,DC
TQ
L?

CI

C'Tt

GO REPEAT
CLfAN UP CHECKSUM

RH

IF CHECKSUMS DIFFER, •••
TYPE QUESTIONABLE ADDRESS •••
ANI) GET RA.CK FAST TO CATCH NEXT X

TyPE
RNZ

PU~

LR

IF NOT T,. GO FETCH NEv.!

H,DC
SU

SIJRTRACT TO FINO COUNT •••

n3

PI
LR
LR
LR

LR

XU •.h
A,QL
XL,A

70

LIe;

'"i'a·

11

IJ:"

4·

LR
LR

BNZ

7F
F'2

i7AA ;3·
e?SB 7A 02 DC

O?AF.

HtfJ •
XU
L2
INf
XU, A.
RH

AS

Or

?B
15
C:;J

L~

LIS
AS
ANZ

is

Q?7B
;?7E

C'·,

ANZ

JMP
LR
PI
SL
LR
PI
AS
LR
PI
SL
LR
PI

,763 ti3
0764 ~A f)2 DC
0?67 r.3
O?68 ~6
i269 ?A 02 DC
O?6C is
il760 ti3
e?6E 78 02 DC
i771 r.3
0772 i)7
0?74 00 OJ
i?76 70

CI

1ft

A.QU

ANn TRANSFER TO X

-144-

CO~MI\ND

F~X

V;'\1

t'?A4 ~3
O?AS 00
~?A7 7F
i?aR f:"1
i7A9 q4
e?AR ?A
i?AF: ~;E
t?AF ?A
ft?R? 71
f?R3 f:"3
O?R4 04
ft?R6 ?A
i?q9 ?A
ft?RC i~
6?RD ~1
;?RE ?A
@?CI 11
~?C2 11
9?e3 Pi'

t?es

PAGF
LP
08

~R

T3

LIS
Ne;
RNl
PI
LP.

08

OJ 50
TO
oJ IF

PI

LIe;
Ne;
RN?
PI
PI
LM
LR
PI
05
OS
RC

Tl
04
ftJ

C;4

"J 54 T?

OJ lA
El

os

10

,?C6 P? EI
O?CA on 92

AC
RP

YL.A
TO
H'FYL
TI
Tel

Q.or

TQ
H'3YL
T?
Tei'
Te?

QL.A
TaL
YL
XL
T3

xu

T1
L4

11

SFT IN,)EX FOR LINE

IF t.411LTIPLE OF te ••••
TYPE CARRIAGE RETURN. LINE FEED
TYPE DC
IF MULTIPLf OF 4 ••••
TYPE fXTRA SPACE
TYPE SPACE
TYPE RYTE
r,O REPEAT
GO REPEAT

** copy FROM H TO Q
* THIS ROUTI~E COPIFS A ALOCK Of:" X+l qYTES. STARTING AT AnORESS H. INTO
* THE LOCATION STAQTTNG AT AOORFSS Q. COPYING IS PERFORMEO FORwaQO OR

(\?CA ,;_A
6?CR 10
tl?CC 1f\
C?CD 1 1
r,?CE ;F
~?CF

11

!?OO
8?nl
O?D2
i?D3
!?,)4
O?DS

4('

PE
i·E
10

QE
11
~~O6 Q? F5
~?n8 1()
~~O9 Q? F2

O?OR

nC

• RACKWARD FROM TH~C;f:" AonRE55ES.
* fNTRY: H=ALOCK START ADDRESS. Q=NEW LOCATION sTART ADDRESS. X=RLOCK
* LfNGTH-l. RS=, FOP f:"ORWARO COPYING. FE FOR AACK~ARO COPYING.
• ExIT: H=RI.OCK FINISH ADORES~. Q=aODRESS 8EYONn NEW LOCATION FINISH.
• X=FFFF. RS=UNCHANGfow nC.ACC.W USED.
CHQ
L~
K.P
LR
DC.H
CHQO LM
FETCH qYTE
H,DC
LR
OC.o
LR
ST
PLACf ~YTE
LR
AOC
IN/OECREMFNT DCLR
LR
A,OC
IM/DECRE~ENT DC
OS
XL
CHQr. Gn R~PEAT
RC
xu
OS
CHQft r,n REPEAT
RC
PK

**

q~AO

HEX CHARACTER

* THIS ROUTINE OPEqATES THE READER CLUTCH TO RFAO A HEXADECIMAL DIGIT

* C~~RACTER. CONVERTS IT TO A HALF BYTE. ADOS IT Tn THE CHECKStJ~ IN YU.
* AND RETURNS WITH IT TN ACC.
* SFf 1/0 INITIALI7ATION REQIJIRFO RY TI.
• r:'''''!TRY: YU=PRFV t OtiC; CHECKSUM.

-145-

F~X

V~l

i?nc ~A

O?f)O

P~GE

*

ExIT:

QH

AS

YU=UPD~TEf)

LP.

K.P

INS

PT
TO
PT

NT

6?Of. ?1 41
O?f-O qC;

9?E2 l~

OUTS
LR
COM

~?~3

Q4 FO

RNZ

9?F.:S

4~

lP

~?EJ 44

~?E6 ?l 7F.
O?F8 ?5 39
i?fA 07 OJ
Q?EC '>4 oj
Q~EF ?4 C9
9?FO C;C;
{)?Fl C?

RHO

NY

CI·

BNC

AI
RH)

6?F3 45

AI
lP.
AS
lP.
LR

~4

OS

~?F2

~?F"4

r:;?

Q::>F"S pC
~?F6 ?R
t}?F7
ll?F'A
i?F"9
(}?FA
97F'A
t?F"C

~A

~100

~J"R

H'3'

LP
LP

QU.A

41

LR

Ql,t\
A.Hl
PO.,Q

qo

1\4

or

LP
lR
OUTS
INS

PK
OIJTS
INS
PK
OUTS
INS
INS

~lQF
~110

0111

ne

P,Q

,,\9
~c

A.XL
SET liP PORT ACCESS ADDRESS IN

H'"'
H't'~

H')'
H')'
H'4'
;,H4'

nON'T MESS WITH TELETYPE' PORT!
H'S'

PK

OUTS
INS
PK
OUTS
INS

H'R'
H'R'

H,q,
H'9'

PK

~1j2 PC
~li3 flC

OUTS
INS

f..PC·

ftl14 ii.c

PK
OUTS

H'D'

0115 pn

SAVE BYTE IN HL

PI<

NOP

610B ;;c
ttlOC RA
0100 ~A

SF"T INPUT READY AGAIN

*
*PA PnRT lPACCESS.
K.P

t)10A "c;

61"E

IC

PI<
NOP

?R

~309

A,IR

LTC;

0101 AO
?1"2 ;'C
!103 Rl
G104 1\1
~11)5 AC
0106 Q4

Ql01

'-9 •...

73

~?FF i,o

PRF="SERVE OUTPUT 8IT
EN(;~GE REAOER CLUTCH

WAIT FOR INPUT COMPLETE
A,Iq
H'1F'
C'9'
RH)
IF"
H'97' AnI) 7
H'Cq'
IA.A
YU
YU,A Ann TO CHECKSUM

A.Ql
Hl,A

~?FD ~7
~?FE' t.R

W tJSED.

RHO

lq
LR

nA

ACC=HALF AYTE.

A.IC

r:;R

nl

CYECt(SUM.

12

H'e-

-146-

Q

[~X

0116
.,17

Vol
M)

r;c

• ,18 1A
i1i9 01
i31A Cjf.
011A ~O
t511c
0310

PAGE

Cif

00 It

•

INS
PI(

13

H'D'

• TYPE elL
• THIS ROUTINE TYPES QL IN ? HEXADECIMAL DIGIT CHAqACTERS.
• S~E 1/0 INITIALI7ATION REQUIRED qy TT.
• ENTRY: QL=RYTf. QS,R(S-I),R(S-?) USEABLE.
• ExIT: QL=UNCHAN~fn. ACC.W,RS,R(S-l),R(S-?) USFI) •
TaL
LP.
I(,P
LQ
A,KL
lR
O,A
LR
A,KU
LR
O,A
AR
TOC

•

• TYPE Q
• THIS ROUTINE TYPES Q IN 4 HEXADECIMAL DIGIT CHAQACTERS.
• SfE 1/0 INITIALI7ATION REQUIRFO BY TI.
• ENTRy: Q=? AYTES. RS.R(S-1),R(S-2) USEABLE.
• EXIT: Q=UNCHANGEn. ACC,W.RS.R(S-1).R(S-2) USEn •
TO
LR
K,P
• 11[ ~A
LP
A.KL
.170 fi}
LR
O.A
t1?1 Cir
LP
A,KU
"0
9172 CiE
LR
O.A
.323
LR
A.QU
.124 ~?
SR
4
01?5 14
.176 c;c
LR
S.A
PI
TH
0377 ;)A OJ 40
LR
A,QU
i1?A :;7
LR
S,A
n1?R c;C
PI
TH
i1?C ~R 0] 40
ft1i'>[ it,
TQ~
LR
A.aL
,,110 14
SR
4
LR
S.A
.111 sC
PI
TM
i132 ?R OJ 4~
.115 03
LR
A.aL
LR
S,A
1116 Sf.
PI
TH
0137 ;)R OJ 40
LR
A.I
i11A 41)
LR
A,I
i11A 41)
LR
'34A ';'4 ttl
i;14C ";14

014E 00

3.
nB

9155

nA
~o

TCI

2e

1)1'57 QO {\2
('~59 7A

f>l'5A c;C
&158 00 n2

i15D

~R

i,lC)E 46

n15F 18
i~3"O Q4 fQ
0162 4C
~163

TO CHECKSUM

CI

H'nQ'

BC

IF 0-9 ••••.
T.... "
H'07' AOO 1

AI
AI
AQ

70

0152 00 oJ

91C:;4

M~!)

H'F'
S

H'31}'
TC4

** TYPE OUT CHARACTER
* THIS R0UTINE TYPES A CARRIAGE RETURN. LINE
* S~E 1/0 INITIALIZATION REQUIRED RY TI.
* E~TRY: RS USEARlF.
* EXIT: RS=A. ACC.W USED.

9150 i}a
~lc;t

THO

YU
YU.A

14

18

i164 ~7
9165 1A
i166 ~o 51

K.P
H'D'

AR
TC4
GO TYPf CARRIAGE RETURN
T41S POUTINE TYPES A SPACE.
Sff I/O INITIALI7ATION REQUIRED BY TI.
tNTRY: RS USEA~LF.
txIT: RS=20. ACC.W USED.
TC2
LR
K.P
II
C"
BR
TC4
GO TYPE SPACE
Te)
LIS
H'A'
LQ
S.A
TC4
AR
TCO
* T4I5 ROUTINE TYPES THE CHARACTER (R RITS) IN RS. IF THE CHARACTER IS
* A CAQPTAGE RETU~~. IT ALSO TYPES A LINE fEED.
* SfE I/O INITIALIZATION REQUIRED RY TI.
• ~NTRY: RS=CHARACTFR.
* EXIT: R5=UNCHANGFfl (EXCEPT D TO A). ACC.W lJSEn.
TC
LR
K,P
Tcn
LP.
A.OC
COM
TC4)
R.NZ
WATT fOR OUTPUT CO~PLETE
LR
A.S
COM
LR
08.~
PLACE RYTf INVERTED

*
*
*
*

01

LI
lP

&16A r:;f,
~169 ::>R OJ 7F
t.1f,C 70

r~1"D Fe

~16E q4 EA
&170 ~c

LR
LIS-

fEED.

PI
LIS

H'S1'
OC.A SET OUTPUT COUNT
T1
CPfATE A SOFTWARE INTERRUPT TO
HtD'

A7

S
Te3

XS

.

Tr~ER

ROUTINE

IF CAPQIAGE RETURN. GO TYPE LINF fEEO

PK

* - Sf IATR ACT H fROM ()
* ENTRY: Q=5UBTRAHFNf).

H=MINUEt..JO •
.. ExIT: Q=OIFFERf~~E. H=~EGATIVE MINUEND.
* Q ANn tOCOO-H. AC~ U5fO.
51J
LR
t<.p

-148-

CARRy SET ON ADDITION OF

r~x

V;t

"117 4A
.173 1~
0174 C;A
i175 4R
~176

lA

0177 iF

i17A C;R
&119 4.A
017A 19
t17A SA
011C 00 61

PAGE

1'5

LR
A.HIJ
COM
LR
HU.A
LP
A.HL
COM
C0MPLEMENT •••
INC
LR
HL"A
LP.
A.HU
LNK
LR
HU.A ANn INCREMENT H
RQ
AfH!
• SIIRTRACT H FROM ()
• THIS ROUTINE PUTS 100n~-H IN H AND Q+(J~eOO-H) TN Q WITH CARRY SET
* ArCOPOJNGLY.
*S'J
LQ
K.P
•
LP
A.HtI
•
COM
..
LR
HU.A
*
LQ
A.HL
•
COM
r.OMPLEMENT •••
•
INC
•
LQ
HL.A
•
LQ
A.HU
•
LNK
•
LR
HU.A ANO INCREMENT H
•
RNC
AOft
IF H:O ••••
•
PI(
RETURN WITH CARRY SET

•

•
•
•
•
•
..
•
•
•
..
•
..
•
•
..
..
~11E ?R
~11F C;8
i1~O

IF

.:V~l

;:to ••

0183 R7
;3q4 AS
'"AS ~1 .t
i3A7 Q4 04

TTMER INTERRUPT
T~IS ROIJTINE PERFooMS FULL DUPLEX SERIAL-BIT 1/0 OF RYTES IA.OR.
BIT
4 OF PORT '5 SfLECT~ 11' RAUD (? STOP 8ITS) OR 3~~ RAUO (1 STOP AIT).
ROUTINE WILL RFTIJRN TO CALLING PROGRAM AS SOON AS I/O IS INITIATED.
TTMER WILL BE SET TO INTERRUPT APPROPRIATELY TO PERMIT MULTIPROCESSING
nIIRIN~ T10.
INITIALIZATION:. RFFnRE FIRST 1/0. INITIALIZE Ir:FE. OC=FF. ANn CALL
TT To SET INTERRUPTS (CAN ALSO Rf PERFORMEn RY nlJTPUTTING A
C~ARACTFR).
THEREAFTf.R:
IC NONNEGATIV~ INDICATES INPUT IN PROGRESS.
IC=FF INDTCAT~~ INPUT 8YTf ARRIVED IN IS; OFCREMENT IC WHEN
COLLECTING TO AvOrn COLLECTING TWICE.
IC=FE JNOtCAT~~ NO NEW BYTE NOR INPUT IN PROGRESS.
OC NONNEG~TIVf INOTCATES OUTPUT TN PROGRESS.
OC=FF INOICAT~~ OUTPUT OF qYTE I~ OB COMPLETED •
ENTRY: IC"OC:COU~TS FOR 1/0. IR.OR=OATA RYTES FOR I/O.
* EXIT: TC.OC=nECQFMENTEO COUNTS FOR 1/0. 18"O~=SHIFTEO DATA ByTES FOR
• 1/0.
ACC.W (WITH INTfRRUPT ~NAALEO) RfSTOREO.
NOP
TIMER INTERRUPT VECTOR
TI
LR
AS.A SAVE ACC
LR
J.W
S~VE W
LI
H'''O'
OUTS PC
S~T TIMER fOR ?4 COUNTS C= 372US + 14US SETTING
PT
DELAY)
INS
Nt
TA
RNZ
TIt
IF ItC BAtJD ••••

-149-

fAX V';l

PAGE

81A9 ?O CA
0188 R7
01QC 44
n1~O

lA

LT
TIO

OUTS

H'CA'
PC

LR

A.lr:

COM
QP
OS

TIl

~3Af ~} 1 )
,190 14
0191 ;>1 nl
&193 q4 11
;195 45

LR

0396 17
&197 c:;s

LR

0198 1\5

INS

;'399

COM

NT

BNl
SQ

'R

039A ;>} 8t

t,)C)c

NI
AS

~s

cnQD c:;s
i19E qO OC

inAO

LP
TTl

AS

09
O~A3 ;>1 4.

e3Al

~l

i1A5 ?? 2t
01A1 qs:;
03 A8 ?O 49
01AA S4
"lAB 46
01AC 18
01AO Al ?Q
~~AF
;1~O
e.1A2
i1~4

BP
INS
AP

NT
Ot
OUTS
LI
TIt?

LQ
LP.

(=

lO69.t;US

+

H'07'
IF
TI?

~OT

A• yr:~

AT 8IT TIME ••••

1

IA.A.
PT

SHTFT OVF:R HYTE

r~IVERT 'INPUT AIT
H'88' F.XTqACT

IR
IA.A
TI2
PT
TI2
TO
TR
PT
H'49'

AnD IN

JF START BIT ••••
PRF.SERVE OUTPUT RIT

OYSENl1AGE READER CLUTCH

~c .. "

SFT INPUT COUNT

IF OUTPUT IN PROGRESS ••••
nFr.Qf.MENT OUTPUT COUNT

A,Or:

OS

TI3
OC

?1 nl
q4 24

"II

H'~7'

RNZ

46

LP.

Tl3
IF ~T RIT TIMf ••••
A,OC
H'S6'
IF" START BIT TIME. GO ('HECK 8Aun RATE
T14

~p

CI
A7.
LIS

OR

LR

A,08
TIS

AN7
SP.

C:;7

LR

~lCO

A5

91 C3

INC;
NY

00 12

28

~lnl

"c:;
0102 ;>1

qp

TI4

~c;

;1C6 ?1 I I
01C8 ~4 08
~lCA ?() 4E
t1CC C:;f,
Oleo 00 OJ
iJCF 17
,100 c:.7

2.

TIC)

TI6

..

GO OUTPUT AIT

TR

PRFSERVE READER CLUTCH BIT

TTf.
PT
TA

LT

H'4Ft

LR
AR
SR

Tl1

OUTS

)

SHJFT OVER AYTE

T17

INS

I~

OR,A
PT

q7

NT
01

0104 ?? 48

~'106 115

INS

fXTQACT DATA RIT

1

NT

lP

TY7

H'nl'

NC)

~lRF

?1

66US SETTING

IF INPUT IN PROGRESS ••••
f)Fr:RFMENT INPUT COUNT

... 6

f)1qA r::'7
01RR 47
01RC Q4 12
01Rf 1?

!)~C5

TIMER FOR 69 COUNTS
OEl4Y)

COM

03R5 ;>C; S6
01R7 ~4 OQ
01P.9 7)

iJct

Ie

C:;~T

16

oc.~

IF 300 AAun, •••
Rf:"()UCE COUNT RY A TO OUTPUT ONLY 1 STOP
(j0

OUTPUT Sl.t\RT RIT

1

OR,A
PT
TR
TO
PT

SHTFT 0VER 8YTE
PRFSERVE READER CLUTCH AIT

-150-

HIT

FAX V~t
0107
.108
'109
,10A
'10B
i100
810E
,'Of
i1FO
.1f.l

PAGE

73

TI3

lIS
OUTe;
lR
NC;
RP
lIS
OUTe;
lR
lR
EI
POP

R6
44

F"6
At tJ
71
~6

io

TIA

4A

lR

'1E2 ic

•*

H'3'
PI
A,IC
OC
TI8
H' 1 '

PI

w.J

A.AS

17

E"'bRlE TIMER
IF" 80TH COUNTS NEGATIVE ••••
OY5ARlE TIMER
RESTORE W
RJ:STORE ACC

AnD H TO Q
THIS ROUTINE PUTS O+H IN Q AND SETS CARRY ACCOROINGlY.
E~TRY:
Q=AOOENO. H=AUGEND.
• EXIT: Q=SUM. H=IJNCHANGEO. CARRY SET ON ADnITION Of Q AND H.
* U<;ED.
AD
lR
K.P
ADO
lR
A,Ql
AS
Hl
lP
Ql.,A
lP
A,QU
LNI(
AS
HlJ
lR
QU,A Ano TO Q
PI(

*
*
i1E3
,3E4
.1£5
,1E6
t1E:7
.1EB
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Schematic of Mostek F8 Survival Kit

,4

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e 7

10.

THE LATEST DEVELOPMENTS
IN PROM AND FPLA PROGRAMMING
DICK WOODS
DATA I/O CORPORATION
Sunnyvale, California

PROM programming techniques have progressed rapidly during
the past year and several new

innovat~ons

have been introduced

which will surely be of great significance to PROM users.
This paper presents an overview of the latest developments.

GENERIC FAMILY PROGRAM CARDS
The "generic" card set is designed to program several
PROMs in a bipolar family for a given manufacturer.

Now,

instead of requiring a program card set for each PROM to be
programmed, it is possible to have one card set for a family
of PROMs which are designed around a common fusing specification.
This provides a considerable savings in terms of the hardware
necessary to program anyone particular manufacturer's family
of PROMs.

As an example, it is now possible to program all of

Monolithic Memories' PROMs using one card set and several socket
adapters which control the programmer's address limit and byte
size.

A PROM comparison chart is shown in Table 1, which indi-

cates the generic family of cards and the appropriate socket
adapters.

-153-

UNIVERSAL CALIBRATOR
A Universal Calibrator is now available which can be used
to quickly determine if the manufacturer's critical programming specifications are being met.

This task is accomplished

by using the Universal Calibrator and any inexpensive digital
volt meter and calibration chart.

The new Universal Calibrator

uses the PROM programmer as a source of voltage during the
calibration procedure.

Concise calibration instructions are

included with each program adapter for calibrating a particular
card set.

Typical tests and calibrations include program volt-

age and current levels, read voltage and current levels, address
line voltages, read lines, chip enable, etc.

Periodic calibra-

tion assures maximum program yield and should be performed regularly.

A single universal calibrator accepts program adapters

for most PROM types manufactured today.

ROM PATTERN TESTING
If masked ROMs are being used for production hardware, it
may be desirable to verify their operation after receiving them
from the manufacturer.

It is possible to use the PROM program-

mer as an incoming inspection device to verify the functional
operation and the pattern of the ROM.

This technique is per-

formed by plugging two standard cards into the mainframe of the
programmer.

These cards are called "read-only cards".

They

have the ability to address the ROM and read the outputs into

-154-

the programmer bus structure.

The programmer thus sequences

through the addresses comparing the data found in the master
device with the data found in the device under test.

If there

are any differences the programmer will stop, indicating the
address and showing the bit pattern of both the master and
the device under test.

ROM patterns up to 16K size (2Kx8)

can be checked using this technique.

PAPER TAPE FORMATS
All of DATA I/O PROM programmers which are equipped with
paper tape readers will accept binary or image data as a
standard format.

If the optional translator card is inserted

in the programmer, several other tape formats are then acceptable for translation.
decimal, and Octal.

These include ASCII BNPF, BHLF, HexaTwo popular forms of Hexadecimal are

acceptable, the first being DATA I/O's format, the second,
Scientific Microsystems' for use with their ROM simulator.
Figures 1, 2, 3 and 4 show examples of binary, BNPF and Hexadecimal tape, respectively.

INTERACTIVE PROGRAMMING OF MaS PROMS
Interactive program cards are now available for programming all MaS PROMs and are designed to insure a known amount
of stored charge on each floating gate.

The technique used

is to cfiarge the floating gate with pulses until threshold is

-155-

• MOST COMPACT FORMAT
• NEEDS AN IDENTIFIER FOR BEGINNING OF TAPE DATA
• A HOLE EQUALS A PROGRAMMED BIT
ALL HOLES DATA IDENTIFIER
TAPE CHANNEL 8

...

••••
••
•• •
••
•
•
•
......-.......................................
.
•
••
••
••••
•••••
•
LEADER

~.

TAPE CHANNEL 1
ADDRESS 007
ADDRESS 000

Figure 1

• BEST FOR TELEPHONE (TWX) TRANSMISSION
• LONGEST TAPE
• BPNF FORMAT IS MOST POPULAR
• TTY CAN BE USED FOR HARD COpy READOUT
ASCIIIB'
Ip'

IN'

••••••••••
••••
••
• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • ••••
• • • • • •• • • • • • • • • • • • • • • • • • • • • • •
•••••
••••••
••••••
•
•••••
•
••••••••••
•••• ••••
~

4 OR 8 IP'S OR IN's
LEADER

"---v~-""~

ADDRESS 000

~

4 OR 8 IP'S OR IN's
v

ADDRESS 001

Figure 2

LF

• MEDIUM LENGTH FORMAT
• EASY PREPARATION ON A TTY
I

• USES HEX CHARACTERS 0 THRU 9 AND A THRU F

f--J
U1

00
I

• CONTROL CHARACTERS
DATA I/O

SMS

TAPE START

SOH

DCI

EXECUTE

SPACE

APOSTROPHE

END OF TEXT

ETX

Figure 3

TAPE START

TAPE END

•
••• •••
•

•

••••••••••••••••••••••••••••••••••••••

•
••
••••

••

000 001 002
ADDRESS
LEADER

Figure 4

reached.

The number of pulses to reach threshold is then

multiplied by a constant for the particular PROM being programmed.

Pulses are then added so that the total charge is

at a known level for proper data retention.
Coupled with the new interactive programming is the ability
to easily calibrate a UV erase lamp and PROM programmer so that
PROM erasing is properly done.

This technique consists of

erasing the PROM under the UV lamp in small increments of time
and verifying the data on the PROM programmer until the data is
just at the threshold point, i.e., has just been erased.

The

total accumulated time of erasure is now multiplied by a factor
of three, which equals the minimum time under the erase lamp
for proper erasure of a PROM prior to programming using the
new interactive programming technique.

ROMULATOR™ and RAM_PAK™
During the design of any system which will contain PROMs
as a memory element, it may become necessary to change the
PROM data several times before the proper pattern is achieved.
A useful tool which can be used in this situation is a simulator
or emulator of the PROM in use.

To help the designer, the

Romulator and RAM-PAK have been developed.

The Romulator pro-

vides the data and address readout and a keyboard for data
entry.

The RAM-PAK is a plug in, high density memory cube

approximately 3x3x3 inches in dimension, which can look and

-160-

operate like any PROM, be it bipolar, AIM, MNOS, or MOS, and
has a capacity to 8K bits.

Data can be entered and verified

using the data and address display in binary, Hexadecimal or
Octal.

The RAM-PAK can also be bidirectionally interfaced

to DATA I/O PROM programmers as an input or output device.
The RAM-PAK, after being programmed by the Romulator or programmer, can be powered by its own DC

batte~y

pack to insure

data integrity during transit prior to plugging into the host
system.

The Romulator and RAM-PAK can be interfaced to a user

system, allowing a PROM program to be emulated, verified or
updated before commiting to a PROM.

The Romulator is the

ideal approach to system debugging.

MODEL VII
If you have a microprocessor based system and would like
to have a universal PROM programmer which can be controlled by
the processor, a unit (the Model VII) will be available soon
from DATA I/O.

This programmer is universal and will program

any PROM which exists on the market today.

It can be inter-

faced to your processor system via RS-232 or 8 bit parallel
interfaces.

The programmer includes 8K of RAM buffer for

storage of the data prior to programming.

Also, a display of

the sequence is included, such as, continuity tests, illegal
bit check, program, verify and pass or fail.

A switch is

vided for local or remote selection so that control can be

-161-

pro~

handled by the computer or by the operator at th€ front panel.
All previously developed program card sets for bipolar, MOS,
AIM or MNOS PROM technologies can be used within the new Model
VII.

FPLA PROGRAMMER
During 1975, two field programmable logic arrays (FPLAs)
were lntroduced by Intersil and Signetics.

These programmable

logic devices are the first of a series from several of the IC
manufacturers.

DATA I/O has produced a programmer called the

Model X, which is capable of programming the existing FPLAs
on the market today, and is capable of programming FPLAs which
are released in the future.

The Model X FPLA Programmer has

the capability of programming FPLAs from a variety of input
sources such as punched paper tape, mark sense cards or a
master FPLA in the copy mode.

Table 2 shows the FPLAs which

are now available and those which will be available in the
near future.

The Model X programmer can be used to program

the existing devices by merely replacing a program card set
within the programmer.

These card sets are approved by each

FPLA manufacturer before their release for sale.

The pro-

grammer contains a CRT which is the heart of the system and
displays to the operator all pertinent information associated
with FPLA programming.
The Model X control system features a custom CPU system
with 24K of PROM memory and a 15 word instruction stack register.

-162-

All of the 132 instructions are completely flexible, so that
as· new developments and improvements are made, units in the
field may be easily updated.

Table 3 shows an example of a

typical FPLA truth table in an ASCII format.

The input data

to the programmer is coded in ASCII to define product term
number, input term, output term and activation level.

The

input data is monitored within the Model X to insure correct
format and field length.

A listing mode is available so that

an ASCII coded paper tape may be observed on the CRT prior to
programming the FPLA.

The modes of operation of the Model X

are divided into three categories; input to RAM, RAM to FPLA,
and clear RAM.

The input to RAM mode is selected for paper

tape reader, mark sense reader or remote input.

A keyboard

is used to manually enter data to the RAM buffer which is
displayed on the CRT or to update the data if a master FPLA
has been used to load the data to the RAM buffer.

The RAM to

FPLA mode is used to program and to compare the contents of
the RAM with the FPLA.

The clear RAM mode is used to erase

the entire contents of the RAM.

During the programming cycle

the programmer automatically sequences through illegal bit
check, program, array verify and logical verify before indicating to the operator that the FPLA has been satisfactorily
programmed.
An output interface is available to connect the Model X
to an ASR-33 teletype terminal, which can be used as a hard
copy printout of the RAM contents.

-163-

Thus when the programmer

NUMBER
OF INPUTS

PRODUCT
TERMS

NUMBER
OF OUTPUTS

PACKAGE
SIZE (PINS)

AVAILABILITY

INTERSIL

14

48

8

24

NOW

SIGNETICS

16

48

8

28

NOW

AMD

16

48

8

28

EARLY 1976

MMI

14

48

8

24

1Q76

SEVERAL OTHER MANUFACTURERS ARE IN THE DESIGN PROCESS AND WILL
RELEASE THEIR PRODUCTS IN 1976

Table 2

An example of a typical FPLA Truth Table is shown below.
*A LLLLLLLL

STX
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P
*P

00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*i
*1
*1
*1
*1
*1

LL---L-------H
LLLLLH-------HLLLLH-------HHLLLH-------LHLLLH------HLHLLLH-----HLLHLLLH----HLLLHLLLH---HLLLLHLLLH--HLLLLLHLLLH-HLLLLLLHLLLHHLLLLLLLHLLLHLLLLLLLLL---L------HL
LLHLLH-------HLHLLH-------HHHLLH-------LHHLLH-----H-LHHLLH----HL-LHHLLH---HLL-LHHLLH--HLLL-LHHLLH-HLLLL-LHHLLHHLLLLL-LHHLLHLLLLLL-H
LHHLLHLLLLLL-L
LL---L-----HLL
LLLHLH-------HLLHLH-------HHLHLH-------LHLHLH----H--LHLHLH---HL--LHLHLH--HLL--LHLHLH-HLLL--LHLHLHHLLLL--LHLHLHLLLLL--H
LHLHLHLLLLL-HL
LHLHLHLLLLL-LL
LL---L----HLLL
LLHHLH-------HLHHLH-------HHHHLH-------LHHHLH---H---LHHHLH--HL---LHHHLH-HLL---LHHHLHHLLL---LHHHLHLLLL---H
LHHHLHLLLL--HL
LHHHLHLLLL--LL
LHHHLHLLLL-LLL

*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F
*F

-----AAA----AAA
AA---AA-A---A---A--AA---A-AA--AA-AA----AAA--A-AAA---AAAA--AAAAA--------

--A--AAA-A--AAA
AAA--AA-AA--A----A-AA--AA-AA----AAA--A-AAA---AAAA--AAAAA-----AA--------

---A-AAA--A-AAA
AA-A-AA-A-A-A---AA-AA----AAA--A-AAA---AAAA--AAAAA-----AA--A--AA--------

--AA-AAA-AA-AAA
AAAA-AA-AAA-A-----AAA--A-AAA---AAAA--AAAAA-----AA--A--AA---A-AA--------

ETX
ASCII INPUT DATA FORMAT
Input data is configured in ASCII coding to define Product Term
#, Input Term, Output Term and Activation Level. Checking of

input format is accomplished within the Model X to insure
correct length of fields.
-165-

TABLE 3

is used in an engineering environment, a copy of the FPLA
contents can be easily obtained for record keeping purposes.

LOOKING AHEAD
The outlook for the future in programmable devices should
see several new PROMs and FPLAs from the manufacturers.

In

PROMs, look for lKx8 and 2Kx4 devices to be released in 1976.
For FPLAs, look for at least three new devices this year.

-166-

TABLE I

'-he Proarammer People
DATA I/O
Post Office Box 308
1297 N.W. Mall
Issaquah, Washington 98027
(206) 455-3990

c

uration

COMPARISON CHART
Personality Cards & Socket Adapters
to
Manufacturers' pROMs

Manufacturers' Part No.
Bold Face = 3
e

Data lID
Program
Card Sat

Program
Socket
r

Pro·
grammed
Logic
Level

(715~XX~xxf'~>:>":;'. :

ADVANCED MICRO DEVICE
(gOg-XXX X) (715-XXXXJ
32X8 (FL)
AM27S08, AM27S09
1119-1
1034
256X4 (FL)
AM27S10, AM27S11
1176-1
1034
256X8 (MOS)
1702/AM9702
1183-1
1047
256X8 (MOS)
1702A
1183-1
1047

VOL
VOL
VOL
VOH

AMERICAN MICROSYSTEMS
512X8 (MOS)
S6834
512X8 (MOS)
S5204-B
FAIRCHILD SEMICONDUCTOR
256X4 (FL)
9341~ 93426
256X4 (FL)
93417, 93427
9343~ 93446
512X4 (FL)
512X8 (FL)
93438,93448
10416 EeL
256X4 (FL)
HARRIS SEMICONDUCTOR
32X8 (FL)
HPROM 8256
64X8 (FL)
HPROM 0512
HPROM 1024A, 1024
256X4 (FL)
32X8 (FL)
HM7602/7603
256X4 (FL)
HM7610/7611
512X4 (FL)
H M7620/7621
512X8 (FL)
HM7640/7641
1024X4 (FL)
HM7642/7643
1024X4 (FL)
HM7644
ALL (FL)
Diode Matrix
INTEL CORP.
256X4 (FL)
3601/3601-1
256X4 (FL)
3621
512X4 (FL)
3602, 3622
512X8 (FL)
3604, 3624
512X8 (FL)
3604-6
1024X4, (FL)
3605
256X8 (MOS)
1702A/4702A/8702A
512X8 (MOS)
2704/8704
1024X8 (MOS)
2708/8708
INTERSIL
32X8 (AIM)
5600, 5610
256X4 (AIM)
5603A, 5623
512X4 (AIM)
5604, 5624
512X8 (AIM)
5605, 5625

""1037,"" '
1027..*:;;'
, .1033
1033,

1230-1
1230-1

1033
1038

VOH
VOH

1055-9
1063-21063-21063-21144-3

1034
1027-1
1027-2
1033-2
1034

VOL
VOL
VOL
VOL
VOH

1051-4
1054-3
1055-3
1063-41063-41063-41063-41063-41063-41189

1034
1033
1034
1037
1027-1
1027-2
1033-2
1039
1042
1034

VOH
VOH
VOL
VOL
VOL
VOL
VOL
VOL
VOL
OPEN

1004
1170-11170-11170-11170-1·
1170-1·
1183-1
1174-1
1174-1

1034
1027-1
1027-2
1043-1
1043-2
1039
1047
1033
1033

VOH
VOL
VOL
VOL
VOL
VOL
VOH
VOL
VOL

1142
1142
1t42.
1142·
1142
1142
1187-6
1187-10
1187-10

1050-1
1050-2
1050-2
1058-1

1002
1003
1003
1033-2

VOH
VOH
VOH
VOH

1142
1142
1142
1142

-167-

. 1:142
1142
. 1142

":'fQ27~*'
t027;":*'"

1021;;;'*';

1142t03~",
1187~i3. ' ::;.>:1 Q34 ,;

1037
1027-*
1027-*
1033

Read-Only Options

Configuration

Data 1/0
Program
Card Set

Manufacturers' Part No.
Bold Face = 3 State

MONOLITHIC MEMORIES
5330/6330,
32X8 (Fl)
256X8 (Fl)
5335/6335,
256X4 (Fl)
5300/6300,
512X4 (Fl)
5305/6305,
5340/6340,
512X8 (Fl)

(909-XXXXJ
5331/6331
5336/6336
5301/6301
5306/6306
5341/6341

Program
Socket
Adapter

Program
Logic
Level

(715-XXXXJ

Read-Only
Socket
Adapter

Read-Only
Card
(701-XXXXJ

(715-XXXXJ

1226-11226-11226-11226-11226-1-

1046
1033-1
1035-1
1035-2
1033-2

VOL
VOL
VOL
VOL
VOL

1142
1142
1142
1142
1142

1046
1033
1027-*
1027-*
1033

Note: All above are new "-1" series pROMs.

1024X4 (Fl)
1024X8 (Fl)

5350/6350, 5351/6351
5380/6380, 5381/6381

1226-11226-1-

1036
1033

VOL
VOL

1142
1142

1036
1033

MOTOROLA
64X8 (Fl)
256X4 (Fl)

2-5003
10149 ECl

1054-2
1144-2

1033
1034

VOH
VOL

1018
1187-13

1033
1034

NATIONAL CASH REGISTER
256X4 (MN08)
1105
1024X4 (MN08)
2400

1053
1056

1033
1033

VOL
VOL

1142
1181

1033
1033

NATIONAL SEMICONDUCTOR
32X8 (Fl)
7577/8577, 7578/8578
256X4 (Fl)
7573/8573, 7574/8574
256X8 (M08)
4203/5203Q/5202
256X8 (M08)
1702A
512X8 (M08)
4204/5204

1051-9
1055-12
1178-1
1183-1
1177-1

1034
1034
1047
1047
1033

VOL
VOL
VOL
VOH
VOH

1142
1142
1187-8
1187-6
1187-1

1037
1027-*
1033
1033
1033

NEC
256X4 (AIM)

1058-2

1027-1

VOH

1142

1127-*

SIGNETICS CORP.
32X8 (Fl)
8223
32X8 (Fl)
10139 ECl
32X8 (Fl)
82-8-23, 82-S-123
256X4 (Fl)
82-8-126,82-S-129
256X8 (Fl)
82-S-114
512X8 (Fl)
82-S-115
256X4 (Fl)
10149 ECl
512X4 (Fl)
82-8-130, 82-S-131

1051-1
1051-2
1051-7
1055-10
1145-21145-21144-1
1055-10

1034
1034
1034
1034
1032
1033
1034
1034

VOH
VOH
VOH
VOH
VOH
VOH
VOH
VOH

1142
1142
1142
1142
1187-3
1187-3
1187-13
1142

1037
1037
1037
1027-*
1032
1033
1034
1027-*

TEXAS INSTRUMENTS
32X8 (Fl)
74188A
32X8 (Fl)
748188, 74S288
64X8 (Fl)
74186
256X4 (Fl)
748387, 74S287
256X8 (Fl)
74-8-470, 74-S-471
512X8 (Fl)
74-8-473, 74-S-472
All (Fl)
Diode Matrix

1063-31063-31054-1
1055-5
1063-31063-31189

1037
1037
1033
1034
1028-1
1028-2
1034

VOH
VOH
VOH
VOL
VOH
VOH
OPEN

1142
1142
1018
1142
1142
1142

1037
1037
1033
1027-*
1028-*
1028-*

TOSHIBA
512X4 (M08)

1185-1

1033

VOL

1187-15

1033

4030

T3181

NOTES: 1) Shielded cable, PIN 709-1012, is required for use with all socket adapters.
2) All -1 socket adapters have a 256 word limit.
3) All -2 socket adapters have a 512 word limit.
4) Use single socket receptacle PIN 715-1026, or dual socket receptacle, PIN 715-1029,
for all adapters.
5) - Generic Program Cards
6) * Dash n umber does not matter
-1681-1-76

11.

LOGIC STATE ANALYZERS GAIN \vIDESPREAD
ACCEPTAL\lCE AS HICROPROCESSOR DEBUGGING TOOL
BRUCE FARLY

Hewlett Packard Co.
Colorado Springs, Colorado
Microprocessors, for all their blessings, have added many new
complications to the development of equipment and systems.
Ability to debug microprocessor-based designs is becoming of
major importance to the design engineer. In particular, the
engineer needs to see in real time precisely what is happening
in digital systems in an easy-to-read display format. Because
they are not dedicated, are of relatively low cost, expandable
and capable of being interfaced easily to anything from a
breadboard model to a field-installed system, logic state
analyzers are finding widespread acceptance as the answer to
debugging needs.
For sophisticated applications, the real-time nature of subtle
software/hardware interactive problems dictates the need for a
measurement tool with sufficient capabilities to meet a wide
variety of needs. For example, the l600A includes a standard
16 word by 16 bit table display, a method of displaying an active
as well as a stored table for comparative troubleshooting, an
exculsive OR display where the table displays data diffe~ences
and a map display that provides an overall, macroscopic view of
machine operations.
More Than 16 Bits
However, for applications requiring more than 16 bits, two
pieces of equipment, such as the 1600A and the l607A must be combined to provide a 32-bi t-\

w

I-

>CI)

M

~

.

.

1:

r'1

"

ID

r-

"..

.A.
-yo

INTERFACE VECTOR
I/O DATA BUS

..

.....

Lt>

W

I-

>-

M

~

....

CI)

-

0

t
INSTRUCTION
ADDRESS BUS

I
I-'

PROGR~~

.....:J

• ROM OR PROM

0'\
I

• MAX STORAGE16--BIT INSTRUCTION BUS
4096 16-BIT
WORDS

INTERPRETER (CPU)

..'"
....
-

w
l-

>-

• EIGHT B-BIT REGISTERS
• WORKING STORAGE
ADDRESS REGISTER (lVR)

ID

... -

~

.A..

.A

....

...

'--

• ARITHMETIC/LOGIC UNIT
• PROGRAM COUNTER

M

CI)

~

WORKING STOflAGE
CO"'TROLflUS

0

• INTERFACE VECTOR
ADDRESS REGISTER (lVL)

1

"

I

PAGE SELECT

I

I

~QB.!S.!_~_STO~AGE

I

• 256 BYTES OF
REA~IWRITE MEMORY

PAGE 0
128 BYTES

J~--;----

USER INTERCONNECTION

TRI-STATE INPUT/OUTPUT
DATA LINES

0

INTERFACE VECTOR
CONTROL BUS

,

"I

I

I

PAGE 1
128 BYTES

I
I

Figure 1.1 MicroControlier System Diagram

} --+--...-

INPUT/OUTPUT
CONTROL LINES

er

0
~'"
(.):::1
"'eII

>c
........
(.)c

!O
erO

...

ALU RESULT SUS
GENERAL
PURPOSE
WORKING
REGISTERS

~

~

INTERFACE
VECTOR BYTE
CONTROL
...JOw

>G)

...J-

Zer

Rl

(SI

R2

fSI

>w .....

-~~

R3

fll)

R4

(81

RS

(81

R6

(81

-l:)

O:w
~o:

~

~

...
......g
...J

III

I
I--'
-....J
-....J

I

Rll

READ-ONLY
PROGRAM

(81

STORAGE
(ROM/PROMI
512 TO
4096 WORDS

INTERFACE VECTOR INPUT DATA
WORKING STORAGE DATA

256 BYTES
Of RIW MEMORY
PAGE 1
(128
BYTES)

VARIABLE FIELD ADDRESS

Figure 1.2 MicroControl1er Arc.'hitecture

only as a destination in an instruction which
directly generates an IV byte address.
Working Storage Address (IVR) - An 8-bit write-only
register used to address a Working Storage byte.
IVR is used only as a destination in an instruction
which directly generates a Working Storage byte
address.
Data Registers Include:
Working Registers (WR) - Seven 8-bit registers for
data storage.
Overflow (OVF) - A I-bit register that retains the
most significant bit position carry from ALU addition operation. Arithmetically treated as 2°.
Auxiliary (AUX) - An 8-bit register. Source of
implied operand for arithmetic and logical instructions. May be used as a working register.
A crystal external to the CPU is used to generate
the CPU system clock. The CPU executes eight instruction types.

input status lines, set or reset output control
lines, and perform high-speed input/output data
transfers. All instructions are 16 bits in length.
Each instruction is fetched, decoded and executed
completely in 300 nanoseconds.
Data is represented as an 8-bit byte; bit positions
are numbered from left to right, with the least
significant bit in position 7.

o

1 234 567

I I I I I I III
MSB

LSB

'Within the Interpreter, all operatibns are performed
on 8-bit bytes. The Interpreter performs 8-bit,
unsigned, 2's complement arithmetic.
3.1

Instruction Formats

The General MicroController instruction format is:

The l6-bit MicroController instructions are stored
512 to 8192 words of read-only Program Storage.
Program Storage can be implemented with either mask
coded ROMs (Read-Only Memory) or PROMs (programmable
Read-Only Memory).

012 3 4 5 6 7 8 9 10 11 12 13 14 15

Op
Code

I

I

Operand(s)

The input/output system, called the interface Vector, Table 3.1 contains a summary of the MicroController
serves as the data path over which information is
instruction set and description of the operand fields.
transferred i.nto and out of the MicroController.
All instructions are specified by a 3-bit Operation
The basic elements of the Interface Vector are:
(Op) Code Field. The operand may consist of the
following fields: Source (S) Field, Destination (D)
• The general ,urpose 8-bit input/out registers
Field, Rotate/L~ngth (R/L) Field, Immediate (I)
or Interface Vector (IV) Bytes, whose tri-state
Operand Field, and (Program Storage) Address (A)
data path serves as the connection points to the
Field.
user system.
e The IVL register which addresses an IV Byte.
The Instructions are divided into five format types
• Variable field selection which permits 1- to 8based on the Op Code and the form of the operand(s).
bit field access of a selected IV Byte in a single
instruction.
The Interface Vector eliminates the need for costly
interface logic and presents a simple, well-defined
interconnection point to the user system.

OPERATIONS
(Register to Register)
MOVE AND

TYPE I

ADD

Working Storage is available as an option that provides 256 bytes of read/write memory for program
data or input/output data buffering. Working
Storage consists of:

Ia

I

• 256-bit bytes of read/write memory organized as
two pages, Page 0 and Page 1, of 128 bytes each.
• The Working Storage address register, IVR, which
addresses a byte in either Page 0 or Page 1, depending on the state of the Page Select Register.
• The Page Select Register, addressed through IVR,
is an 8-bit register used to select Page 0 or Page
1 of Working Storage.
• Variable Field Select which permits 1- to 8-bit
field transfers to or from an addressed Working
Storage byte in a single instruction.
3.

XOR

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Op
Code

S

RIL

I

I

0
OPERATIONS

TYPE II

I0

I

MICROCONTROLLER INSTRUCTION SET

The MicroController has a repetoire of eight instruction classes which allows the user to test

-178-

MOVE

ADD

AND

XOR

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Op
Code

S

RIL

0

I

I

OPERATIONS

XEC

XMIT
NZT

, 0 1 2 3
,

,I

4 5 6 7 8 9 10 11 12 13 14 15

Op
Code

I

S

NZT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

I c~e

S

R/l

I

I

1

OPERATIONS

JMP

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ~

I ~e
3.2
Op

A

I

Instruction Fields
Code Field - 3-bit Field

The Op Code field is used to specify one of eight
MlcroControl1er instructions.
OPCODE
OCTAL
VALUE INSTRUCTION

0
1
2
3
4

MOVE
ADD
AND
XOR
XEC

5 NZT
6 XMIT
7 JMP

The Sand/or D fields may specify a register, or a
1- to 8-bit 1/0 field, or a 1- to 8-bit Working
Storage field. Sand D field value assignments in
octal are shown in Table 3.2.

The R/L field performs one of two functions. specifying either a field length (L) or a right rotation
(R). The function it specifies for a given instruction depends upon the contents of the Sand D fields:

XMIT

XEC

I

.0

R/L Field - 3-bit Field
OPERATIONS

I0

implie. a third operand, .ay Z, located in the
Auxiliary a_ai.ter
that the operation which
takes place is actually X + Z, with the result
stored in Y. This powerful capability means that
three operands are referenced in 300 nanoseconds.

A. When both Sand 0 specify registers, the R/L field
is used to specify a right rotation of the data
specified by the S field. (Rotation occurs on the
bus and not in the source register.) The register
source data is right rotated within one instruction
cycle time independent of the number (0 to 7) of bit
positions specified in the R/L field.
B. When either or both the S and D fields specify
an IV or Working Storage data field, the RIL field
is used to specify the length of the data field
(within the byte) accessed, as shown below:
OCTAL
VALUE

o
1
2
3
4
5
6
7

SPECIFICATION
Field length = B bits
Field length = 1 bit
Field length = 2 bits
Field length'" 3 bits
Field length = 4 bits
Field length = 6 bits
Field length =6 bits
Field length = 7 bits

o1
WS or IV
Byte

23.. 567

I \Ixlx\x\ III

-

_ _ _ _ _ _ _ _ _ _ _ _ _ -J

A

I field - SIB-bit Field
RESULT

S,R/l,D
S,R/l,D
S,R/l,D
S,R/l,D
I, R/L,S or 1,5

(S) -+ D

(5) plus (AUX) -+ 0
(5) " (AUX) -+ 0

(S) 0 (AUX) -+ 0
Execute instruction at current PC
offset by I + (5)
I,R/l,S or 1,5 Jump to current PC offset by I if (5) ; 0
I,Rll,S or 1,5 Transmit literal 1-+5
A
Jump to program location A

The 1 field ia uaed to load a literal value (a
binary value contained in the inatruction) into a
regiater, IV or Working Storage data field or to
modify the low order bits of the Program Counter.
The length of the I field is based on the S field in
XEC, NZT, and XMIT instructions:
A. When S specifies a register, the literal I is an
8-bit field (Type III format).
B. When S specifies an IV or Working Storage data
field, the literal I is 50bit field (Type IV Format).

S,D Fields - 5-bit Fields
A field - 13-bit Field
The Sand D fields specify the source and destination of data for the operation defined by the Op
Code Field. The Auxiliary Register is the implied
source for the instructions ADD, AND and XOR which
require two source fields. That is, instructions
of the form:

The A field is a 13-bit Program Storage address
field. This allows MicroController Systems to
directly address 8192 instructions, although current offerings are limited to 4096 instructions.

ADD X,Y

-179-

TABLE 3.1
MICROCONTROLLER INSTRUCTION SUMMARY

OPERATION

FORMAT

RESULT

Content of data field addressed by S, R/L
replaces data in field specified by 0, R/L.

MOVE

ADD

Type I
Type II

Sum of AUX and data specified by S, R/L
replaces data in field specified by 0, R/L.

AND

Logical AN 0 of AUX and data specified
by S, R/L replaces data in field specified
by 0, R/L.

XOR

Logical exclusive OR of AUX and data
specified by S, R/L replaces data in field
specified by 0, R/L.

XMIT

The literal value I replaces the data in the
field specified by S, R/L.

NZT

Type III
Type IV

XEC

JMP

NOTES

Type V

If Sand 0 both are register
addresses then R/L specifies
a right rotate of R/L places
applied to the register specified by S.

If S is IV or WS address then
I limited to range 00-37.
Otherwise I limited to range
000-377.

If the data !n the field specified by S,
R/L equals zero, perform the next instruction in sequence. If the data specified by
S, R/L is not equal to zero, execute the
instruction at address determined by using the literal I as an offset to the Program
Gaunter.

If S specifies an IV or WS
address then I is limited to
the range 00 - 37. I is limited
to the range 000 - 377 otherwise.

Perform the instruction at address determined by applying the sum of the literal I
and the data specified by S, R/L as an offset to the Program Counter. If that instruction does not transfer control, the
program sequence will continue from the
XEC instruction location.

The offset operation is performed by reducing the value
of PC to the nearest multiple
of 32 (if I : 00 - 37) or 256 (if I
: 000 - 377) and adding the
offset.

The literal value I (eplaces contents of the
Program Counter.

I limited to the range 00000 07n7.

-180-

TABLE 3.2
SAND 0 FIELD SPECIFICATION

Register Specification

08· 118 is used to specify one of seven working registers
OCTAL VALUE

(Rl . R6, Rll). Auxiliary Register. Overflow Register. IVl
and IVR write·only registers.

00
01

Auxiliary Register (AUX)
Rl

02
03

R2
R3
R4
R5

04

05
06
07
10
11

12
13
14
15
16
17

R6
IVL Register· IV Byte address write·only register· Specified only in S field of XMIT
instruction. or in 0 field in all other instructions.
OVF • Overflow register· Used as an S (source) field only.

Rll
Unassigned
Unassigned
Unassigned
Unassigned
Unassigned
IVR Register· Working Storage address write·only register· Specified oniy in S
field of XMIT instruction, or in 0 field in all other instructions.

I/O Field Specification
208 . 218 is used to specify the least significant bit of a variable length field within
OCTAL VALUE

20
21
22

the IV Byte previously selected by the I V L register. The length of the field is
determined by R/L.
Field within previously selected IV Byte; position of LSe

=2
=3
=4
=5
=6
~ 1

23
24
25
26

21

o1

=0
=1

IV Byte

234 567

Q:I)h1J;Q
I

I

I

I

I

I

I

~ _________~~~I~-LI~

Working Storage Field Specification

30a· 318 is used to specify the least significant bit of a variable length field within
the Working Storage Byte previously selected by the IV R Register. The length of
the field is determined by R/l.

OCTAL VALUE

30
31

Field within previously s.'ected W.S. Byte; position of lSB

32

=0
=1
=2
:0:3
=4
=5
=6

33
34
35

36
37

-1

-181-

o1

W.S. Bvte

234 567

I............
I I I IOf IIf' I+I.,.I
I

I

I

I

I t I

I

I

I

I

I

I

I

I
I

3.3

Register Operations

When a register is specified as the source, and an
IV or Working Storage field as the destination, the
least significant bits of the operations (MOVE, ADD,
AND, XOR) resllit are stored. The operation is performed on the entire 8-bit source for a MOVE, or
between the 8-bit AUX and the source register for
ADD, AND, XOR operations. The least significant
bits of the result are stored in the IV or Working
Storage data field specified by the D and R/L fields
in the instruction.
When an IV or Working Storage field of one to eight
bits is specified as the source, and a register as
the destination, the 8-bit result of the operation
(MOVE, ADD, AND, XOR) is stored in the register.
The operations ADD, AND, XOR actually use the IV
or Working Storage data field (1-8 bits) with
leading zeros to obtain 8-bit source data for use
with the 8-bit AUX data during the operation.
Because IVL and IVR are write-only pseudo registers,
they can be specified as destination fields only
(see Table 3,2). Operations involving IVL and IVR
as sources are not possible. For example, it is
not possible to increlDent IVR or IVL in a single
instruction, aild the contents of IVL or IVR cannot
be transferred to a working register~ IV Byte, or
Working Storage location.

From the user's standpoint, however, all IV Byte
outputs can be read by an external device regardless
of whether they are selected or not.
Although the address range of IVL is 0 - 3778, only
28 IV Bytes are available on current system offerings. The addressing for the 28 IV Bytes is 018
to 348'
4.2

Each IV Byte consists of 8 storage latches which
hold data transferred between the Interpreter and
the User System, 8 tri-state input/output lines
and two inputs/output control lines, called Byte
Input Control (BIC) and Byte Output Control (BOC)
(Figure 4.1). The control lines functions are
summarized in Table 4.2.

TABLE 4.1
FUNCTIONS OF THE BIC AND BOC LINES

BOC (low true)

Addressing Data on the Interface Vector

L

H

x

L

8 I/O lines in high impedance state·
disable
8 I/O lines in output mode· 8 bit
storage latch data available in the
output lines.
8 i/O lines in input mode· data can
be read by Interpreter.

BIOGRAPHY
Michael A. Liccardo is the Product Manager "for
Scientific Micro Systems. He is responsible for
product planning, application support, and market
development for microcomputer system products. He
has previous experience in minicomputer system
design, software development, and computer interface design. He received a B.S.E.E. and an M.S.E.E.
from University of California (Berkeley) and an
M.B.A. from Stanford University.

seen in Figure 1. 2, the IVL register serves
select IV Bytes. In order for an instruction
access (read or write) an IV Byte, the address
that byte must be output to the IVL register.

Thus, two instructions are required to operate on
an Interface Vector byte:
XMIT

H

Table 4.2 contains a summary of the electrical
characteristics of the IV Byte.

The Interface Vector is comprised of general purpose 8-bit I/O registers called Interface Vector
(IV) Bytes. In the present MicroController offering, the Interface Vector may consist of up to
28 Bytes.
As
to
to
of

BIC (low true)

H

INPUT/OUTPUT SYSTEM

As seen from previous sections, the Interface
Vector is the MicroContrc1ler's input/output system. It provides a simple interconnection to the
user status, control and data lines.
4.1

FUNCTION

CONTROL LINES

The OVF (Overflow) Register can only be used as a
source field; it is set or reset only by the ADD
instruction.
4.

Electrical Characteristics of the Interface
Vector

ADDRESS t IVL

MACHINE INSTRUCTION
Once the IV Byte is selected (addressed), it will
remain selected until another address is output to
IVL. Since IVL can be used only as a destination
field of ariWinstruction, any instruction sending
data to IVL can be used to select an IV Byte.

-182-

Table 4.2

IV BYTE TERMINAL ELECTRICAL CHARACTERISTICS

CHARACTERISTIC

LIMITS

SYMBOL
MIN

"1" Input Current·

I

TYP

UNITS

CONDITIONS

MAX

I'IN

100

uA

V'IN= 5.5 V

"0" Input Current·

101N

-800

uA

V 0IN = 0.50 V

"1" Input Voltage

V'IN

2

5.5

Volts

"0" Input Voltage

V 01N

-1

0.8

Volts

Input Clamp Voltage

V CIN

High Output Voltage

V'OUT

Low Output Voltage

V eoUT

Output Short Circuit Current

ISO

Data I nput Capacitance

C IN

~

(X)

W

Volts

lOIN = -Sma

Volts

I'OUT= 1ma

0.5

Volts

I(IOUT = -16ma

-200

ma

V0QUT = 0 V

12

pf

V 0IN = 0 V

-1

I

• Input current is alwcvs present regardless of the state of BIC and BOC.

2.4

-20

IV Control Bus
7~----.

6...-----·
Interface Vector
I/O Data Bus

5~----·
41+------..

Tri-state or Open Collector
Input/Output lines

3.4-----·
,....----.
2 .....- - - -..

~_ _ _ _ _ _ _ _

}

Input/Output Control Lines

FIGURE 4.1
IV BYTE PROVIDING DYNAMICALLY DEFINED DATA

FLo\~

r---'
J----...-.II
I
~----~

U~r
System

I
I
I
,

I

I
L __ J

FIGURE 4.2
IV BYTE WIRED FOR USER OUTPUT ONLY

r--l
··4-----11

1
User
System

I

I
I
L __ ..JI

FIGURE 4.3
IV BYTE WIRED FOR INPUT ONLY

-184-

A MICROCOMPUTER-BASED CRT TERMINAL
J.E. Bass
Rockwell International Corporation
Microelectronic Device Division
3310 Miraloma Avenue
Anaheim, California 92803

INTRODUCTION
The use of microcomputers as the central control function for CRT terminals offers significant product cost
reduction possibilities. While many present CRT products use microcomputers, most of these are used only in the
peripheral functions of the system. This paper describes a 1920-character intelligent CRT terminal which uses the
Rockwell PPS-8 microcomputer as the primary means of implementation. All system functions are implemented
with the PPS-8, including keyboard servicing, CRT refresh from PPS RAM memory, editing, printer interfacing, and
communications interfacing.
The paper first describes the functional characteristics of the CRT terminal. Secondly, the PPS-8 microcomputer
components are described. Finally, the implementation of the CRT terminal is described in detail.

TERMINAL FUNCTIONAL CHARACTERISTICS
The CRT terminal uses a standard CRT monitor for display. A format of 24 lines of characters with 80 characters
per line is provided. Data may be entered through the data entry type alpha-numeric keyboard; external messages
may be received through an optional 1200 BPS modem chip. High speed modems may be used in conjunction with
our USART-type chip, the Serial Data Controller.
The edit functions include character insert/delete and line insert/delete. Editing is implemented through cursor
control in conjunction with cursor control keys and associated function keys on the keyboard. Line Tab, Display
Protect, and Line Scroll functions are also provided. A mUlti-position ~ursor is provided so that an entire word or
phrase may be deleted in one operation instead of one character at a time as is normally done. The display refresh
rate is 60 cycles per second, and the monitor is operated in a non-interlaced mode.
Output functions include optional telecommunications and serial party line operations as well as printer options.
Telecommunications options provide from 1200 to 9600 BPS operation. The 1200 BPS modem is a single chip
configuration with an external analog filter. Printer options consist of 10 to 150 character-per-second alpha-numeric
speeds with MOS controllers for full printer control. Higher speed line printers may be interfaced through our PDC
I/O chip but require discrete control logic.
The intent of the paper is to illustrate the flexibility of the PPS-8 system in this type of application, and not to
describe a finished commercial product. This exercise was undertaken basically for applications know-how. All
basic software and hardware design techniques are available to our PPS customers through the Rockwell Applications
Engineering staff.

THE PPS-8 MICROCOMPUTER SYSTEM
The PPS-8 microcomputer system is an integrated set of MOS/LSI chips designed primarily for intelligent terminal
types of applications. The set is implemented in low cost P-channel technology; system speeds equivalent to, or
surpassing, N-channel microcomputers is achieved through system organization. The Rockwell system organization
employs a form of distributed processing in which all system chips contain various degrees of intelligence, depending
upon their particular function. Some perform dedicated functions, such as printer control or display control; others
are programmable through control bytes loaded by the CPU.
We ca1l this approach the Parallel Processing System (PPS). In the Parallel Processing concept, multiple tasks may be
executed concurrently in the system. Some tasks will be executed in software; some will be executed in the firmware or dedicated hardware of the intelligent I/O controllers. The CPU becomes the system executive, setting up
tasks and assigning them out to the associated controllers. After short data buffer transfers to or from the I/O

-185-

PPS-8 CRT SYSTEM

THE PPS-8 MICROCOMPUTER SYSTEM (cont.)
controllers, the CPU is free to attend to the higher level task of the executive software. Normally, detailed CPU
intervention in the routine I/O functions of keyboard servicing, display servicing, and block transfer of data into or
out of the system is not required. With this approach, system performance may be several times that of CPUoriented microcomputer alternatives.
A brief discussion of each chip used in the CRT Terminal follows. For a full description of all 110 chips available
with the PPS-8 microcomputer, please refer to our marketing literature.

CPU
The CPU provides 109 instructions and operates with a four-microsecond instruction cycle. An instruction cycle
includes both the instruction fetch and the instruction execute. Most instructions are executed in one cycle. In
addition, all Load, Store and Exchange instructions may perform multiple functions in the one cycle to significantly
increase system speed. For example, automatic RAM address pointer incrementingldecrementing, testing for loop
completion, and switching to a second RAM address pointer can all be accommodated in one basic four-microsecond
cycle. This provides for very efficient and fast processing of table-oriented data as is found in an intelligent terminal
application. Thos, data bytes may be moved from one table, or buffer, to another at a 12-microsecond/byte rate,
including all overhead addressing functions.
The CPU contains many instructions especially useful for intelligent terminal tasks. The ability to set or reset any
bit in any byte in RAM memory is provided along with associated conditional branchlskip instructions for any bit
condition in RAM memory. The CRT Terminal uses two bits of the 8-bit character code to encode cursor, tab, and
protect functions for each individual character or character positio,,!, for example. Byte comparisons between the
PPS-8 accumulator and addressed RAM locations permit rapid table searching of data with automatic branching or
skipping on comparisons or non-comparisons. CPU registers (6) may be loaded directly from ROM memory for
subroutine parameters, stored messages, header formats, or form outl ines.
The CPU also provides three levels of priority interrupt. The highest priority level is used for power fail detection.
The second highest level is useful for a real time clpck or a relative time clock. The third level of interrupt is used
as the general system interrupt and may be daisy-chained through 15 110 chips to provide a self-contained priority
interrupt structure. The entire interrupt chain may' be enabled or disabled, and individual 110 chips in the chain
may be individually armed or disarmed to provide a very flexible interrupt structure. This structure is built in the
chips, requiring only one external"OR" tie resistor on the interrupt request line. Also, the CPU provides an
instruction, Read Interrupt'Status, which immediately identifies the 110 device requesting the interrupt and the
reason for the interrupt. No software polling of 110 devices is required.

The CPU directly addresses 16K ROM and 16K RAM. An additional chip select line on all ROM's and RAM's
provides direct extension to 32K ROM and 32K RAM without any external components. fn addition, all ROM's
and RAM's directly interface to the CPU address and instructionldata bus without the need for other interface chips.
The PPS-8 bus can directly drive up to 350 pF at rated speed. This permits loading the bus with 35-40 chips before
being concerned with bus drivers. This is several times the bus driving capability of other systems.

DIRECT MEMORY ACCESS CONTROLLER (DMAC)
The DMA Controller provides eight independent channels of DMA capability. Built-in logic provides a DMA priority
structure with Channel 0 having the highest priority and Channel 7 having the lowest priority. Each DMA channel is
loaded with a starting address and a block length by the CPU. After that, tbe CPU is free to execute its main line
program as the eight individual block transfers set up in the DMAC are executed. At the end of each individual block
transfer, the DMAC notifies its appropriate 110 controller. The associated 110 controller may be programmed to
respond to the DMA End of Block condition with an interrupt to the CPU or it may be programmed to ignore the
EOB condition. On all intermediate transfers within the associated block of data, the 110 devices (independent of
the CPU) monitor their control lines and request DMA service from the DMAC when a request for data transfer is
received externally. Thus the CPU sets up the DMA channels (up to eight), goes away to work on other tasks, and is
informed by the individual 110 controllers by means of interrupts at the end of their block transfer. Data rates on

-186-

PPS-8 CRT SYSTEM

DMA transfers may vary from 250,000 bytes per second down to one byte per second or less. Again, the CPU is only
involved in setting up the initial channel addresses and block lengths and then in responding after a block of data has
been completely transferred. Status indicators in the I/O controllers flag any error condition that may have occurred
in the block transfer.
The DMA Controller has a Block Repeat function built in for these cases where a continuous repetition of a data
block may be required as in a CRT, for example. DMA Channels 0-6 have a repeat control bit which may be set by
the CPU. In this mode, the CPU sets the Repeat Bit flag in the channel to be used in the repeat mode and loads the
channel starting address and block length in the primary channel (Channel 0-6) as well as in Channel 7, the Refresh
channel. Now, when the primary channel reaches the end of the block of data (Block Length = 0) it checks its
repeat flag bit and, since it is set, the primary channel transfers the initial address pointer and initial block length
stored in Channel 7 into its registers so that it may repeat the block transfe.r again. At every End of Block condition,
the primary channel will again refresh its initial address and block length from Channel 7, thereby continually
repeating the block transfer as desired.

PARALLEL DATA CONTROLLER (POC)
The PDC is a dual 8-bit programmable I/O controller which as the ability to initiate interrupt requests or DMA
transfer requests upon the occurrence of external control line transitions. Each 8-bit port contains two programmable
control lines whose functions are programmed by the CPU by means of control bytes. In addition, the mode of each
port is programmable; i.e., input, output, or input/output. In addition, the type of data transfer is programmable;
i.e., static, clocked, or handshake transfer. The ability of the PDC to request interrupts or DMA service may be
armed or disarmed by appropriate control byte bit patterns. In addition, the PDC may be programmed to request an
interrupt on the DMAC indication of an End of Block transfer or it may be programmed to ignore the EOB condition.
Status registers detect the occurrence of any data transfer error (buffer underrun or buffer overrun) which may OCCur.

SERIAL DATA CONTROLLER (SOC)
The Serial Data Controller is a full duplex, USART chip. The function of the chip is programmable by means of a
control byte loaded by the CPU. Controllable parameters include bits per character (5, 6, 7, or 8), number of stop
bits for asynchronous operations (1.0, 1.5,2.0), and for parity insertion/checking (odd, even, none). The SOC
contains five RS-232·C interface control lines for convenience in interfacing to high speed modems. The SOC may
be used in party line operation between master and slave terminals, for example. The SOC will transmit up to
250,000 bits per second in the synchronous mode. In this mode, the null character, once loaded into the SOC, will
be automatically repeated in transmission until another valid data character is sent. Thus, the system will stay in
sync even though a transmit buffer may run empty, provided the last character in the buffer is the null character.
Double buffering of both the receive and transmit channels is provided.

The SOC also has a Receive Compare register which continuously compares a byte loaded into it by the CPU with
incoming data. Upon comparison, the SOC can be programmed to request an interrupt, thereby notifying the CPU
of a valid comparison. This function may be used to search for the terminal's address on the party line or multi-drop
communication line, for example. Or it may be used to automatically search and verify a sequence of communication
protocol control characters. Using this feature, the SOC can be set up to strip off all null (or sync) characters, identify
the terminal address, and then start interrupting the CPU, or else requesting DMA service, on each framed input character.
This is done independent of the CPU activity after the compare byte has been loaded. Multiple byte addresses or
control sequences can be handled by successive recognition and then loading of the next byte of the sequence.
Error checking for buffer overrun/framing errors, parity errors or carrier drop-outs is provided. Thus, after a block
transfer, the quality of the entire transfer may be quickly checked by the CPU through reading the SOC quality register.

-187-

PPS-8 CRT SYSTEM

FLOPPY DISC CONTROLLER (FDC)
The Floppy Disc Controller provides all data formatting required for reading or writing on floppy disc media from
byte-oriented RAM storage. Up to four floppy discs may be serviced by one FDC. For Write operations, the FOC
provides track address verification and sector address search/comparison logic, preamble and postamble generation,
write head current enabling, parallel to serial conversion, and CRC polynominal generation and detecting. For
Read operations, the FDC provides track verification and sector address search/comparison logic, CRC polynomial
generation from sensed data and comparison with the recorded CRC field, disc format verification, and serial to
parallel data conversion.
In addition, the FDC provides a Read Compare register similar to the SOC. This register permits stripping of preamble
bits, postamble bits, and address fields from the incoming data stream so that only the addressed sector data is
transferred to RAM memory. No CPU processing is required to separate the floppy disc overhead fields (preamble,
postamble, address) from the data field of interest.
To implement a full floppy disc memory system, a General Purpose Input/Output chip (GP I/O) is required for disc
selection, track position control of the read/write head, head loading/unloading, and status information. External
circuitry is needed to combine clock and data for recording and to extract the clock from this data when reading.
The format of the F DC is under software control so that user formats may be used in addition to the compatible
I BM format. Non-I BM formats permit much greater data packing density than the I BM format provides. Many
users may want to use a packed format for data storage, and then convert to IBM format for interchangeable discs.
This can be readily done with the FDC. In fact, each track within the disc may have its own format. In a four disc
system, for example, one disc may be recorded in I BM format for interchangeability, while the three other discs are
recorded in a packed format for improved data capacity. A software routine would then be used to unpack the
packed format and record the data in the less dense IBM compatible format for disc interchange compatibility.
Disc commands include Read, Write, Write Format, Read CRC Check, Read Address Field, and Read Status.

GENERAL PURPOSE INPUT/OUTPUT CONTROLLER (GP I/O)
The GP I/O is a programmable chip which provides twelve discrete input lines and twelve discrete output lines. The
input and output lines are addressed in groups of four lines each. Thus, input lines are addressed in terms of Group
A, Group B, or Group C. Similarly, the output lines are grouped in terms of Group A, Group B, or Group C. Input
lines are static; output lines are latched and maintain their levels until re-Ioaded.
The CPU addresses the GP I/O and commands it to read from individual input groups or to output to the individual
output groups. Also provisions are made to "OR" input ~roups in one instruction, or to "AND" output groups.
Thus, the "OR" condition of .all input lines, by group, may be read into the CPU in one instruction. Or, the same
bit pattern may be applied to all output groups in one instruction.

OTHER CONTRO LLERS
Other controllers consist of keyboard controllers, display controllers, and printer controllers. The keyboard
controllers provide all strobes, strobe return sensing, key debounce, key rollover, and key buffering functions. The
CPU is only required to unload the key buffer once each 50-100 milliseconds. Display controllers provide all multiplexing of digit display information as well as digit select strobes. The CPU merely transmits up to a 16-character
display buffer to the chip; the chip does the rest. A combination keyboard/display controller, the GP K/D, is
available. This chip is used with up to 64-key keyboards and Panaplex~ Burroughs' Self Scan~ or LED displays.
Several Printer Controller chips are also available. For example, a two-chip set is available for control of a 150 cps,
alpha-numeric dot matrix printer. The only discrete circuitry required are the power driver transistors. Chip outputs
drive one standard TTL load (2.6 ma). A combination Keyboard/Printer chip is also provided to control a 64-key
keyboard as well as a 22-column printer.

-188-

PPS-8 CRT SYSTEM

TELECOMMUNICATIONS DATA INTERFACE-CONTROLLER (TOI)
The TOI chip provides a full duplex programmable UART function as well as a 1200 BPS modem function. The
modem may be strapped for Bell 202 or CCITT signaling frequency compatibility. The modem design accommodates
1200 BPS transmission over a dial up, unconditioned telephone line. The UART may be programmed for bits per
character (8, 16, 64), parity (none, odd, even), and signaling frequency. The TOI has interrupt capability; up to 16
TOI chips may be incorporate'd in a single system. A serial mode which utilizes the modem function only and
disables the UART function is also provided so that the chip can be used as a stand-alone modem.
Some external circuitry is required for full modem implementation. A four pole analog filter is required on the
receiver input and a simple operational amplifier with four summing resistors is required on the transmitter output
line.

RAM'S
The PPS-8 RAM's are 256 x 8 bit RAM's with full address decoding on each chip. The RAM's are dynamic, but
appear static to the user since all refresh is done automatically without interference to the user. Standard 4K x 1
RAM's of the 16 pin configuration can be interfaced to the PPS-8 by means of our 4K Interface Controller Chip.
This chip provides all interfacing and refresh functions required for standard memory operation. Two interface
chips are required per system. These service up to a 16K x 8 RAM and present only two units of load (10pf) to
the PPS Bus. Multiple memory modules may be used. The 4K RAM Controller Chip has the ability to float its
output lines so that external control of the 4K RAM memory is possible. Thus, the 4K RAM can be loaded
externally at-the full 4K RAM speed; then the PPS-8 can operate on this data at rates up to 250,000 bytes per
second.

The PPS-8 ROM's are 2048 x 8 bits, also with full address decoding on each chip. Thus, up to 16K of ROM easily
fits on one 5% x 7-inch PC board.

THE CRT TERMINAL
A basic CRT Terminal will first be discussed. Then an expanded terminal with floppy disc memory and printer will
be described. Finally, an expansion of the terminal to graphic display functions will be briefly outlined.
The basic organization of the CRT Terminal includes PPS-8 RAM memory as the data storage media. A OMA
channel is then used to load one of two line buffers, each being 80 characters in length. As the OMA loads one line
buffer, the other line buffer is driving the CRT monitor. As one line buffer completes its line display function,
control logiq switches to the other line buffer which has been loaded through OMA. The initial line buffer is then
refilled by OMA while the second line buffer is driving the display.
The CRT basic terminal implementation with the PPS-8 is illustrated in Figure 1. The system is implemented with
a CPU, 2560 x 8 RAM Memory, 2K x 8 ROM/PROM, a OMAC, and a POCo The CPU,.POC, OMAC, and two RAM
chips (512 x 8) are contained on our PPS-8 Processor II evaluation board. The additional 2048 x 8 RAM is
contained on our RAM evaluation board. One board of TTL logic contains the double line buffers and associated
raster control, character generator and associated control logic. Our PROM evaluation board is presently used for
program storage. Eventually, this board will be replaced with one ROM chip mounted on an option board which
also contains provision for the Floppy Disc Controller, GP I/O, and SOC or TOI modem. The hardware used in the
basic CRT terminal is illustrated in Figure 10. The display control word is illustrated in Figure 2. Two basic versions
are shown. One provides upper/lower case characters plus cursor. The other provides the expanded functional
controls of Tab and Display Protect.

-189-

PPS-8 CRT SYSTEM

DISPLAY CONTROL
The display is generated from a standard TV raster as shown in Figure 3. Eleven scans comprise the formation of
one line of 'characters as illustrated. The display refreshing is accomplished as shown in Figure 4A and 4B. In
Figure 4A, Line Buffer 1 is driving the display through the character generator and shift register. It is also
recirculating on itself corresponding to the eleven scans required to generate the full line of characters. During this
time, Line Buffer 2 is being loaded via DMA through PDC 1. Timing for this operation is illustrated in Figure 5.
After completion of the present line of display, Line Buffer 2, which has just been loaded with the next line of
characters, is switched to the active display mode, and Line Buffer 1 is switched to the load mode. This is illustrated
in Figure 4B.

SYSTEM TIMING
The timing associated with system operation is shown in Figure 6a. All numbers relate to PPS-8 system time required.
Refreshing the line buffers required 320 microseconds per line time of 698.5 microseconds. Thus, 46% of system
time is required for refreshing. At 9600 BPS, the modem servicing time requires' 0.48% of system time .for data
transfer. Thi5 does not include modem control overhead. The time left for editing and system control software is
approximately 100,000 system cycle times per second, or 40% of the system time. The expanded system with
Floppy disc memory, printer, modem, and/or party line control is illustrated in Figure 7. Timing for this expanded
system is shown in Figure 6b.

GRAPHICS DISPLAY
Addition of a graphics display function is also feasible. For a 125-line by 555-grid, graphic refresh via DMA is
feasible. This mode would provide the graphic refresh plus an 800-character refresh capability. To implement the
described graphic capability would require an additional 8K of RAM Memory. In addition, a large amount of CPU
time would be required for graphic conversion. The PPS-8 implementation for this mode might be as illustrated in
Figure 8. The additional graphics memory is constructed of standard 4K x 1 RAM chips of the 16 pin configuration.
This memory module is interfaced to the PPS-8 CPU by means of a 4K RAM I nterface chip now under development.
The system in Figure 8 would be adequate if the graphic data were previously formatted for graphic display prior to
loading' into the RAM module. Both graphic and character refresh would require approximately 75% of the CPU
time. Some additional TTL logic would also be required to "OR" the graphic and character data into the video input
of the monitor. If it is desired to do the graphic formatting in the terminal system, a second PPS-8 CPU and its ROM
may be added to the system as illustrated in Figure 9. In this configuration, CPU-2 and ROM-2 are dedicated to
graphics formatting using a 4K RAM Interface chip to access the 4K RAM memory while CPU-1 is providing the
character refresh function out of its PPS RAM. When CPU-2 has formatted a graphic display, it then passes control
of the 4K RAM module to CPU-1 for display and refresh of the graphic function as well as for a reduced (800)
character display and refresh. This mode is feasible since each 4K RAM Interface chip has the ability to float its
output lines to the 4K RAM module.
Alternately, a DMAC can be added to CPU-2 so that all graphic formatting display I and refreshing is done by the
second system. This will off load System 1 so that all other intelligent terminal functions can be executed in
System 1. The addition of System 2 would also permit graphic expansion to 225 x 555 points with the addition of
another 8K of RAM memory. System 2 would consist of a single 5 x 7 in. PC board plus the additional 8K of RAM.

SUMMARY
This application illustrates the power and flexibility of the PPS-8 microcomputer system in both the single and
multiprocessor modes. The advantages of a complete set of systems-structured, intelligent controllers are
demonstrated with this applications study. Very significant product cost reductions may be achieved with this
approach, as demonstrated by the minimal amount of hardware required for this CRT application.
The hardware for the basic display terminal is illustrated in Figure 10. The addition of the floppy disc and printer
require 3 additional chips from those shown. The addition of the graphics capability requires one additional
interface chip plus the expanded 8K of RAM plus additional ROM memory for programming ... probably one of
our 2K x 8 ROM chips.

-190-

PPS-8 CRT SYSTEM

, . . - - -_ _ _ FRAME INTERRUPT
INTERRUPT ACKNOWLEDGE

RECIRCULATE

KEVBOARD
LINE INTERRUPT

----?\

I

I

.VIDEO

~../

CHANNEL
1 2 3 4

o

Figure 1.

8

6

4

3

'CC,HAR~ER CODES

-

' - - - - - - - - - - UPPER/LOWER CASE
L-_ _ _ _ _ _ _ _ _ _ _ CURSOR

(A)

8

6

BASIC CRT SYSTEM

4

I I I

I

~~ERCODES

SCAN
1
2
3

TO SCAN

-+
-+
-+
-+
-+
-+
-+
-+

4
5
6
7
8
9 --.

10 - - .
11 - - .

------------------------------+.
_3

2

••••••
•
••
••

•••

•

•

--7::02~

_______

•

-

••••• •

••

•
•• ••
•••

~::02=-~

______

+~

_"4
_
5
_6
--. 7

• •••••
--.8
--+
•• • • • • _ _
•

9
10

--.11
___________________________________--+.12

IL__________________ CONTROLCODES
00
01
10
11

+~

63.5 usee/SCAN
698.5 usee/LINE (11 SCANS)

CURSOR
TAB
PROTECT

(8)

Figure 2. DISPLAY CONTROL

Figure 3.

-191-

SCAN TIMING

PPS-8 CRT SYSTEM

j- -- -

-l--DOT

' - - - - - - - I CLOCK/RASTER J--CHARACTER

I GENERATOR

J---+.LINE·

... _---- ...
(1) LOADING LINE BUFFER 2
(2) DISPLAY FROM LINE BUFFER 1

Figure 4a.

PPS-8 CRT SYSTEM

FHAME INTERRUPT

.,...----- ...

I

i---DOT

'--_ _ _--I CLOCK/RASTER l---+CHARACTER

L~:~::. j---+

(1) LOADING LINE BUFFER 1
(2) DISPLAY FROM LINE BUFFER 2

Figure 4b.

PPS·8 CRT SYSTEM

-192-

LINE

PPS-8 CRT SYSTEM

RECIRCULATE 11 TIMES

LINE BUFFER 1
(80 CHARACTERSI

LOAD

NEW
LINE

(320_1

VIDEO

Figure 5.

EDIT/SYSTEM
SOFTWARE

BUFFER TIMING

t.·.·.·.·.·.·.· ... ·.·.·.·.·.·.·.·.·.·.·.·.·.·.:.·.... :':':':':':':':':':':':1

I
I~~~­

320 IlSEC.

REFRESH~~~~~~~~~~

I

1--------

LINE TIME (698.5IlSEC.1 - - - - -.....1

I__- - - - - - - - - - - - - - - - - - F R A M E TIME (16.66 m S E C . I - - - - - - - - - - - - - - - - - -..
-1

Figure 6a.

BASIC SYSTEM TIMING

I
I

FLOPPY
DISC

• I

II I I I J I I II J I I I I I I 1III 1I111 III II11 II1I 11111111.

(WHEN TRANSFERRING SEC TORSI

I

I

t: ..........................................................,40%

I·····:···:·:·:·:·:·:·:·:·:·:·············:··········· ................... ~

EDIT/SYSTEM
SOFTWARE

I

J.l.ll 12..%SYSTEM TIME

T

(100,000 CYCLES/SECO NDI

I
I

I
30 CHARACTERS/SECOND

PRINTER

1 CYCLE/2 FRAMES

I

I

l"t- 0.06%

d

I

9600 BPS

MODEM

(1200 CYCLES/SECONDI

I
I

n

~2

I

360#SEC.

I

REFRESH

I

-

0.48%

~~TEMTIME

n

II

-

•

LINE TIME (698.5 IlSEC.1

-I
FRAME TIME (16.66 mSEC.1

Figure 6b. EXPANDED SYSTEM TIMING

-193-

..

PPS-8 CRT SYSTEM

LINE INTERRUPT

·

cal

"""'NTE~
~.
f {. f~- .. .-: .
J:=i~'..
G f
STATUs/CONTROL

ADDRESS

1

~

Figure

7.

.DISC
TRACK
SECTOR

..

\

~~
!
FLOPPY
I· I> :

~

l'

DISC
DRIVES

/

.~

PPS-8 CRT EXPANDED SYSTEM

r - - - - - - F R A M E INTERRUPT

FLOPPY DISC/PRINTER

Figure 8.

GRAPHIC DISPLAY CONFIGURATION

-194-

PPS-8 CRT SYSTEM

r - - - - - - - F R A M E INTERRUPT

RECIRCULATE

INTERRUP~CKtI!OWLEOGE

o,

2 3 4

~KO~:.-1· ii
FLOPPY::=..J
CRT_----'
PRINTER

_-----I

FLOPPY OISCIPRINTER

~~~~~~~~~ii~A~O~O~R~E~~i"BU~s~~~~~~l

4KRAM
INTER· 1 .......- - - - - - - ' \ I
FACE

ROM

2

Figure 9. MULTI·PROCESSOR GRAPHIC DISPLAY

Figure

1a

CRT TERMINAL HARDWARE

-195-

Part Two

Electronic Engineering

TIMES
Linear/Digital
Proceedings

Integrated Circuit
Applications
Conference

See Last Page for Table of Contents

1.

THE MONOLITHIC VOLTAGE FREQUENCY CONVERTER
JAMES C. SCHMOOCK
Design Engineer
Raytheon Company
Semiconductor Division
350 Ellis Street
Mountain View, California 94042
415 968-9211

The development of the monolithic I.C. Voltage-to-Frequenc1
Converter offers design engineers a practical low-cost alternate to modular units costing much more.
Voltage-to-frequency converters (VFC) are used for analog-todigital conversion, modulation, data transmission, and system
isolation. The sister device, the frequency-to-voltage converter (FVC) , is used for tachometry, frequency translation,
and servo control. New uses for these versatile products are
being discovered daily.
The RM/RC 4151 monolithic converter can be used in a number of
VFC and FVC connections to fill almost all needs, from low cost
single supply circuits to precision configurations which preserve transfer function linearity over five decades.
VFC PRINCIPLES
Most VFC's have an output which is a series of pulses. These
pulses have a fixed period, and can be either positive or negative. The VFC changes the duty cycle of the output pulse train
in response to the input voltage.
The block diagram for the simplest type of VFC which can be
constructed using the RM/RC 4151 is shown in Figure 1. The 4151
contains an input voltage comparator, a one-shot, a switched
current source, and an open-collector NPN logic output transistor. For this simple VFC configuration the current source
output is integrated in the passive network RB - CB. One input
of the comparator, pin 6, senses the resulting voltage. The
input voltage to the VFC, VI, is applied at the other comparator
input, pin 7.
If the input voltage is greater, the comparator
fires the one-shot. The one-shot output drives the logic output
low and also switches on the current source. During the time
period, T, when the one-shot is on, the current source will inject a lump of charge Q = lOT into the RB - CB integration network.
This increases the voltage VB by a few millivolts.
If VB
has not increased to a voltage greater than VI, the comparator
again fires the one-shot and the'current source injects another
lump of charge into the integration network. As soon as the voltage VB is greater than VI' the voltage comparator keeps the oneshot off and VB

-1-

The Monolithic Voltage Frequency Converter
James C. Schmoock

is left to decay through RB. During this resting period, the
logic output remains high. As soon as VB decays to the point
where VB = VI, the voltage comparator triggers the one shot
and the cycle repeats, giving the AC component of VB its characteristic sawtooth waveform.
In steady state operation the
one shot fires just often enough to keep VB > VI. Since the
capacitor CB discharges at a rate proportional to VB/RB' the
system operates at a frequency proportional to the input voltage. Although this simple VFC configuration is quite useful
in many of low-cost applications, it suffers from inaccuracy
due to a number of sources. Linearity errors arise primarily
from the current source output conductance and variations of
the sawtooth voltage VB. This sawtooth voltage also creates
a frequency offset as well as does the input offset voltage
of the comparator. Fortunately, all of these inaccuracies are
overcome by the precision mode VFC configuration which uses an
op-amp integrator to replace the network RB - CB.
Figure 2 shows the block diagram for the precision VFC. This
circuit actually functions as a current-to-frequency converter,
with the input current II being drawn from the summing node of
the op amp integrator.
In steady state operation the lumps
of charge coming from the 4151 current source output exactly
balance the input current.
Since the op amp inverting input is held at zero volts, this
circuit is easily transformed into a voltage-to-frequency converter by the input resistor RB. The input voltage must be
negative, because the resetting current 10 is positive. A negative input voltage VI causes the integrator output to ramp
upwards at a rate of VI/RBCI volts per second. As soon as the
integrator output reaches the voltage V, the 4151 input voltage comparator fires the one shot, which turns on the current
source. The current source injects a lump of charge Q = lOT
into the integrator summing node. During this time period, T,
the output of the integrator will ramp downward at the rate of
(VI/RB - IO)CI 1 volts per second. Any nonlinearity due to the
4151 current Source output conductance is eliminated in this
circuit because the integrator holds the current source output at zero volts. The only offset present in the voltage-tofrequency transfer function is du~ to the op amp input offsets.
If an op amp with offset trim provision is used, this circuit
will remain linear for inputs all the way down to zero.
RM/RC 4151 CIRCUIT DESCRIPTION
The 4151 VFC is easy to use and apply if you understand the operation of it through the block diagram, Figure 1. Many users,

-2-

The Monolithic Voltage Frequency Converter
James C. Schmoock

~hough, have expressed
the desire to understand the workings
of the internal circuitry. Figure 3 shows the schematic of
the 4151. The circuit can be divided into five sections: the
internal biasing network, input comparator, one shot, voltage
reference, and the output current source.

The internal biasing network is composed of Q39 - Q43. The N
channel FET Q43 supplies the initial current for zener diode
Q39. The NPN transistor Q38 senses the zener voltage to derive the current reference for the multiple collector current
source Q41. This special PNP transistor provides active pullup for all of the other sections of the 4151.
The input comparator section is composed of Ql - Q7. Lateral
PNP transistors Ql - Q4 form the special ground-sensing input
which is necessary for VFC operation at low input voltages.
NPN transistors Q5 and Q6 convert the differential signal to
drive the second gain stage Q7.
If the voltage on input pin
7 is less than that on threshold pin 6, the comparator will be
off and the collector of Q7 will be in the high state. As
soon as the voltage on pin 7 exceeds the voltage on pin 6, the
collector of Q7 will go low and trigger the one shot.
The one-shot is made from a voltage comparator and an R - S
latch. Transistors Q12 - Q15 and Q18 - Q20 form the comparator,
while Q8 - Qll and Q16 - Q17 make up the R - S latch. One latch
output, open-collector reset transistor Q16, is connected to a
comparator input and to RO terminal pin 5. Timing resistor RO
is tied externally from pin 5 to +VCC and timing capacitor Co
is tied from pin 5 to ground. The other comparator input is
tied to a voltage divider R3 -. RS which sets the comparator
threshold voltage at 0.667 VCC. One-shot operation is initiated
when the collector of Q7 goes low and sets the latch. This
causes Q16 to turn off, releasing the voltage at pin 5 to
charge exponentially towards +VCC through RO. As soon as this
voltage reaches 0.667 VCC' comparator output Q20 will go high
causing QIO to reset the latch. When the latch is reset, Q16
will discharge Co to ground. The one shot has now completed
its function of creating a pulse of period T = 1.1 ROCO at the
latch output, Q21. This pulse is buffered through Q23 to drive
the open-collector logic output transistor Q32. During the oneshot period the logic output will be in the low state. The oneshot output is also used to switch the reference voltage by Q22
and Q24.
The low T.C. reference voltage is derived from the combination
of a 5.5V zener diode with resistor and diode level shift networks.

-3-

The Monolithic Voltage Frequency Converter
James C. Schmoock

A stable 1.89 volts is developed at pin 2, the emitter of Q33.
Connecting the external current-setting resistor RS = 14.0kn
from pin 2 to ground gives 135~A from the collectors of Q33
and Q34. This current is reflected in the precision cu~rent
mirror Q35 - Q37 and produces the output current IO at pin 1.
When the R - S latch is reset, Q22 and Q24 will hold the reference voltage off, pin 2 will be at 0 volts, and the output current will be off. During the one-shot period T, the
latch will be set, the voltage at pin 2 will go to 1.89 volts,
and the output current will be switched on.
USING THE RM/RC 4151 VOLTAGE-TO-FREQUENCY CONVERTER
One of the advantages to using the RM/RC 4151 is its extreme
flexibility.
It operates on a single supply from 8.0 to 22
volts, the open-collector output is compatible with all popular logic types, and nearly every aspect of its performance
can be altered by appropriate choice of component values.
Full scale output frequency can be programmed from 1.OHz to
100kHz.
Figure 4 shows the complete applications circuit corresponding
to the block diagram of Figure 1. The resistor Rs tied from
pin 2 to ground sets the output current from pin 1. With the
nominal values of RS = 14.0kQ, the output current IO will be
about 135~A.
If it is necessary to trim scale factor, use the
resistor-pot combination as shown. The load resistor RL tied
to pin 3 should be connected to the appropriate pull-up voltage for the logic type used, up to +22 volts. The timing
network, ROCO, is connected to pin 5. Keep RO and Co within
the ranges 6.8kn < RO < 680kn and .001~f < Co < 1.0~f. Calculate the one-shot period using the formula T-= 1.1 ROCO.
Using the design equations given in Figure 4, it can be determined that the full scale frequency output is 10kHz for
the maximum input voltage of +10 volts. Although this circuit
configuration is the least accurate of all the ones presented
here, it is quite useful because of its low cost, and because
it operates from a single positive supply. It accepts positive
input voltage from 0 to +10.
Figure 5 shows another single-supply configuration which uses
the RC3403A ground sensing op amp to provide increased accuracy. Input voltage range for this circuit is 0 to +10 volts.
The pair of lkn resistors attenuate the input voltage by a
factor of two. In addition, the nominal value of RS has been
increased to 28kn, so that the voltage at 4151 pin 1, the current source output, varies only over the range 0 to +5 volts.
This is one reason for the increased linearity of this circuit.

-4-

The Monolithic Voltage Frequency Converter
James C. Schmoock

The circuit features a unique offset trim adjustment which
uses the RC3403A bias current to develop a voltage across RS
which cancels the offset voltage. To use this technique it
is necessary to have an op amp with stable input bias current
such as the RC3403A.
For maximum accuracy, use the circuit of Figure 6, the precision mode VFC connection. This is the complete applications
circuit corresponding to the block diagram of Figure 2.
Input
voltage range is from Q to -10 volts and full scale frequency
is 10kHz. The RC 4131 op amp specified has an offset trim adjustment, so with the offset nulled this circuit retains linearity all the way down to OHz. The 4151 operates from only
the positive supply, but the op amp specified requires the
positive and negative supply. A ground sensing op amp may be
used instead, in which case the negative supply can be eliminated, although input voltage range is still negative. Also, no
ground sensing op amp to date has built-in offset trim. The
diode connected across the op amp stops a potential latch-up
condition by preventing the voltage at 4151 pin 7 from going
more than 300mV below ground. This circuit as shown achieves
typical linearity error of only 0.02 percent. Refer to Table 1
for a performance comparison of the different VFC configurations.
COMPARISON OF VFC APPLICATIONS CIRCUITS
Table 1 compares the VFC applications circuits for typical
linearity, frequency offset, response time constant for a
step input from 0 to 10 volts, sign of input voltage, and whether the circuit will operate from a single positive supply or
split supplies.

Linearity
Frequency Offset
Response Time Constant
Input Voltage
Single Supply
Split Supply

FIGURE 4

FIGURE 5

FIGURE 6

1%
+lOHz
l35mS
+
yes

0.2%
0

0.02%
0

10~S

10~S

TABLE 1

-5-

+
yes

yes
yes

The Monolithic Voltage Frequency Converter
James C. Schmoock

FREQUENCY-TO-VOLTAGE CONVERSION
Making an FVC with the RM/RC4151 is just as easy as making a
VFC. All of the same equations for scale factor, period, and
voltage range still apply. See Figure 7 for the simple single
supply FVC circuit. The incoming frequency signal triggers the
4151 input voltage comparator which fires the one shot. The
one shot switches on the current source for a period of time
T = 1.1 ROCO. The current pulses or lumps of charge come out
of pin 1 and are integrated in the RB - CB network to produce
the output voltage.
In order to correctly trigger the one shot, the 4151 input voltage comparator must be turned on for a time period which is
less than the period of the one shot, T. The comparator is
considered to be on when the voltage on 4151 pin 7 is greater
than the voltage on pin 6.
Figure 7 also shows how to trigger the 4151 input with a square
wave. With no signal present, resistive voltage dividers tied
to 4151 pins 6 and 7 keep the input comparator in the off state.
An incoming 5 volt p-p square wave is differentiated by the
.022~f capacitor and the resistive voltage divider.
This produces a pulse at pin 6 which turns on the comparator for a time
less than the one-shot period of 75~S.
Another scheme for input signal conditioning is shown in Figure 8. Here, a O-type flip-flop acts as a differentiator. As
soon as the input signal turns on the 4151, the pulse output
from pin 3 resets the flip-flop, making a very short pulse.
For any of the FVC configurations, an external voltage comparator can be used to square-up small sinusoidal waveforms.
The precision FVC circuit of Figure 9 gives the best accuracy
and linearity. As with all 4151 applications, scale factor can
be programmed by choice of component values. The op amp integrator improves the linearity of this circuit because it keeps
4151 pin 1 at zero volts. This prevents any change of IO due
to output conductance of the 4151 switched current source. Like
all frequency-to-voltage converters, there is a tradeoff between
response time and output ripple.
If Cr = O.l~f, the ripple will
be lOOmV. The response time constant is TR = RBCI = lOmS.
PROGRAMMING THE 4151
The 4151 can be programmed to operate with a full scale frequency anywhere from 1.OHz to 100kHz. In the case of the VFC
configuration, nearly any full scale input voltage from 1.OV

-6-

The Monolithic Voltage Frequency Converter
James C. Schmoock

and up can be tolerated if proper scaling is employed. Here
is how to determine component values for any desired full scale
frequency.
1.

Set R~ = l~kn or use a 12k resistor and 5k pot as shown in
the f1gures.
(The only exception to this is Figure 5.)

2.

Set T = ROCO = 0.75 (~)where fo is the desired full scale
frequency. For optimu~ performance make 6.8kn ~ RO ~ 680kn,
and .001~f ~ Co ~ 1.0~f.

3.

a)

For the circuit of Figure 4 make CB = 10- 2 (~) Farads.
Smaller values of CB will give faster responsg time, but
will also increase frequency offset and nonlinearity.

b)

For the active integrator circuits make CI = 5 X 10- 5
(f~) Farads. The op-amp integrator must have a slew
rate of at least 135 X 10-6(c~) where the value of CI
is again given in Farads, and the op-amp slew rate is
in volts per second.

4.

a)

For the circuits of Figures 4 and 5 keep the values of
RB and RB as shown and use an input attenuator to give
the desired full scale input voltage.

b)

For the precision mode circuit of Figure 6, set RB =
V

10~~A where VIa is the full scale input voltage. Alternately the op amp inverting input (summing node) can
be used as a current input with full scale input current
110 = 100~A.
For frequencies over 10kHz, bypass pin 6
to ground with .Ol~f.
5.

For the F-V converters, pick the value of CB or CI to give
the optimum tradeoff between response time and output ripple for the particular application.

DESIGN EXAMPLES
I

Problems
Design a prec1s10n VFC with fo = 100kHz and VIa
Use the applications circuit of Figure 6.
1.

Set RS

2.

T

=

=

= -10

volts.

l4.0kn.
1

0.75 (10 5 ) =

7.5~S.

Let RO

-7-

=

6.8kn and Co

=

O.OOl~f.

The Monolithic Voltage Frequency Converter
James C. Schmoock

II

3.

1
CI = 5 X 10- 5 (10 5 ) = 500pf. Op amp slew rate must be
1
at least SR = 135 X 10- 6 (500pf)
= 0.27 V/llS.

4.

RB

5.

Bypass 4151 pin 6 to ground with O.Olllf.

=

10V
lOOllA

=

lOOkn.

Problem
Design a very low cost average temperature indicator with
digital readout. See Figure 10 for the block diagram of
the solution. Use the RM/RC 4151 precision VFC configuration of Figure 6 to convert the output voltage of a temperature transducer to a low frequency which can be counted
by a calculator chip. One of the new solid state temperature transducers or a more conventional diode op amp circuit
can be used to sense temperature. An absolute value circuit
can be used ahead of the VFC for transducers which have outputs that swing positive and negative for temperatures above and below zero. The sign bit from the absolute-value
circuit triggers the calculator chip to count up or down.
Refer to the literature for more detailed instructions on
how to use low cost calculator chips as event counters.
Since calculator chips can only count very low frequencies,
let's program the 4151 for a full scale frequency of 1.OHz,
using the circuit of Figure 6.

1.

Set RS = l4.0kn.

2.

T = 0.75 (1)
1.Ollf.

1

3.
4.
III

=

0.75 seconds.

Let RO

=

680kn and Co

=

50llf.
RB = lOOkn.

Problem
Design a tachometer with bar-graph LED readout. Maximum
rate is 5000 RPM and supply voltage is 12.0 volts. Accuracy requirement is ±5 percent, and output response time
constant should be less than lOOmS.
Figure 11 shows the solution to this one.
The single-supply FVC circuit of Figure 7 is used here to convert the
pulse train into a voltage proportional to the frequency.

-8-

The Monolithic Voltage Frequency Converter
James C. Schmoock

It is assumed that the input signal has already been conditioned using one of the techniques mentioned earlier. As
the 4151 output voltage increases with increasing RPM, low
cost quad voltage comparators light up green, yellow, and
red LED's which make up the bar graph. The bar graph can
be made as large as desired by using more comparators and
LED's. The 4151 is to be programmed for a full scale frequency of 5000 RPM (83.3Hz).

=

1.

Set RS

2.

T

3.

Full scale output voltage is 10.0 volts.
100krl.

4•

Output response time constant T R < lOOmS. Therefore
TR
CB < or CB < 211f. Worst case ripple voltage VR =
- RB
-

=

14.0krl.
1

0.75 (83.3)

9mSX13511A
2.011f

=

=

9mS.

608 mV.

Let RO

=

82krl and Co
RB

=

O.lllf.

=

10V
1001lA

A ripple of 608 mV out of 10 volts

would cause some blurring of the display between adjacent LED's, but it would still be possible to achieve
5 percent accuracy with a display of 20 LED's.

-9-

+Vcc

FREQUENCY
OUTPUT

~

+I

~T

VI
INPUT
VOLTAGE

FIGURE 1 - RM 4151 VFC BLOCK DIAGRAM

tV cc

r---------l

I
~

______

~

I
I
I
I

10!

______________________

~

I

I

vo-.:....I_~
OP-AMP
INTEGRATOR

I
I

I
I

SWITCHED
CURRENT
SOURCE

FREQUENCY
OUTPUT

I

ONE-SHOT

I
I

INPUT
VOLTAGE
COMPARATOR

_

I

L ________ -..-J
RC4151

FIGURE 2 - RM 4151 PRECISION VFC BLOCK DIAGRAM

-10-

+Vcc

®

FIGURE 3 - RM 4151 SCHEMATIC DIAGRAM

+ Vcc

~_ _----;~

TO PIN 6

R,S

2 ( 12 kl!

FREQUENCY
OUTPUT

1fir

T~ ~
TO +VCC
DESIGN EQUATIONS

RS

fO : KV I Where K ; 0.486 RBROC
O

FIGURE 4

kHz

V

SINGLE SUPPLY VFC
-11-

CI
,-------l

.0021-'1

OFFSET ADJUST
R'B

1.0':n
1.0kll

+ '/CC
RS - FULL "'CALE TRIM

+ 15

,.----A..-----.,

~

+15

'v

2

10 0 - - - . - - - - - 1

I

RM4151
VFC
5.1

l-:------J

k~~

01,;1

6.8 k~'

OUT?i.J-:- FREQ'JENCY

+ VCC

0", '.:. ::: 10 k Hz

FIGURE 5 - PRECISION SINGLE SUPPLY VFC

CI .005 pi
lN914

RB 100 k~!

FULL SCALE TRIM

5

k~!

12

k~!

+VCC

10

k~!

OUTPUT
FREQUENCY

o

'0'

10kHz

-=-

FIGURE 6

Co

RO

.011-'1

6.8 kll

PRECISION VFC

-12-

VOLTAGE
OUTPUT
o to +10V

+15V

Vo

II
FREQUENCY .022 ;,1
INPUT
o--1l----~

4151
FVC

....--.

PULSE
" ' - - - - . . J OUTPUT

(optional)

lSlJ
5V p-p
SOt'ARE
WAVE

RO
6.8

k~:

'15V
DESIGN EQUATIONS:

FIGURE 7

RO

SINGLE SUPPLY FVC

6.8k~1

to +15V

10

k~!

r
.022 pI

0----1

II
FREQUENCY
INPUT
10 kHz
0 II
5V p-p
SQUARE
WAVE

2

12k" ] RS

+15V

5 kU
FULL
SCALE
TRIM

10 k~l

-=

CI
RB100k~!

-=
R'B
100k~!

-=

FIGURE 8

T'

10 ku
OFFSE
TRIM _

VOLTAGE
OUTPUT
-10V' VO' 0

l

PRECISION FVC

-13-

+5V

+5V

5.1k!!

INPUT FREQUENCY

-......rv

C

7474
D-FLOP

Q

-U-

Q

JL

6

RC4151
FVC

VOLTAGE
COMPARATOR

INPUT SIGNAL CONDITIONING FOR FVC

FIGURE 9 - FVC INPUT CONDITIONING

TEMPERATURE
TRANSDUCER

CALCULATOR
CHIP AND
DISPLAY

RC4151
PRECISION
VFC

SCALE FACTOR

1 HzIV

LO;\H; TERI" AVERAGE THIPERATURE WITH DIG!TAL READOUT

FIGURE 10 - LOW COST AVERAGE TEMPERATURE INDICATOR
-14-

+10V ~---<.--t

+Vcc

RC4151
FREOUENCY
TO
VOLTAGE
PULSE INPUT

TACHOMETER WITH LED DISPLAY

FIGURE 11 - TACHOMETER WITH LED DISPLAY

-15-

2.

DAC-08 APPLICATIONS COLLECTION
JOHN SCHOEFF & DONN SODERQUIST
Precision Monolithics
Santa Clara, CA

There has been a trend in recent years toward providing totally
dedicated Digital-to-Analog Converters with limited applications versatility. This application note describes a new type of
monolithic DAC designed for an extremely broad range of
applications, the Precision Monolithics DAC-08.
Several unique design features of this low cost DAC combine

to provide total applications flexibility. Principal among them
are: dual complementary, true current outputs; universal logic
inputs capable of interfacing with any logic family; 85 nsec
settling time; high speed mUltiplying capability; and finally,
the abil ity to use any standard system power supply voltages.
A description of these features is given followed by specific
applications using each feature.

• CMOS, TTL, DTL, HTL, ECL, PMOS
COMPATIBLE 2p.A LOGIC INPUTS

• 85 NSEC SETTLING
TIME TO ± 1/2 LSB

• DUAL COMPLEMENTARY
OUTPUTS WITH
-10V TO+18V
VOLTAGE
COMPLIANCE

• HIGH SPEED
MULTIPLYING
REFERENCE
INPUT

• ±4.5V TO ±18V
33mW AT ±5V

• EXTERNAL
COMPENSATION
FOR MAXIMUM
BANDWIDTH

• ADJUSTABLE LOGIC
INPUT THRESHOLD
VTH=VLC+l.4V

THE FLEXIBLE D/A CONVERTER

-16-

OUTPUT
All bits ON

HIGH VOLTAGE COMPLIANCE CURRENT OUTPUTS

TA= T min 10 T max

Many older current-output DAC's actually have resistive out-

2.S

puts which must be terminated in a virtual ground. The DAC-

08, however, is a true digitally-controlled current source with

2.4

:;x
.5

an output impedance typically exceeding 20 megohms.
Its outputs can swing between -10V and +18V with little or

~

13

no effect on full sca,le current or linearity. Some of the appli-

1

r

1.6

IREF=2mA

V-= -5V.

V-=-15V.

~ 2.0

I

~

cations that require high output voltage compliance include:

!;

o

1.2

IREF=lmA -

r

1) Precise current transmission over long distances.
O.S

I

2) Programmable current sources.

I

0.4

3) Analog meter movement driving.

IREF= 0.2mA -

r

4) Resistive termination for a voltage output without an op
amp.

I

0_ 14 -12 -10

5) Capacitive termination for digitally-controlled integrators.

-S

-6

-4

-2
0
2
4
6
S
OUTPUT VOLTAGE (volts)

10

12

14

16

OUTPUT CURRENT VS. OUTPUT VOLTAGE
(OUTPUT VOLTAGE COMPLIANCE)

6) Inductive termination with balanced transformers, transducers and headsets.

+10.000 V

MSB
LSB
Bl B2 B3 B4 B5 B6 B7 BS

~

10.000Ks)

IREF
=2.000mA

FULL SCALE
FULL SCALE-LSB

=2'~14

Bl B2 B3 B4 B5 B6 B7 BS
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0

HALF SCALE+LSB 1 0
1 0
HALF SCALE
HALF SCALE -LSB 0 1
ZERO SCALE +LSB
ZERO SCALE

o
o

0
0

o

10 mA 10mA
EO
1.992 .000 -9.960
1.9S4 .OOS -9.920

EO
.000
-.040

0
0 0

0
0

0 0
0 0

1
0

1

1

1

1

1

1

.9S4 -5.040 -4.920
.992 -5.000 -4.960
.992 1.000 -4.960 -5.000

0
0 0

0
0

0
0

0
0

1
0

.OOS 1.9S4
.000 1.992

0

TO)

DAC-08

POS FULL SCALE
POS FULL SCALE-LSB

1.0 OS
1.000

EO

10 }.

JREF

ZERO SCALE+LSB
ZERO SCALE

NEG FULL SCALE+LSB
NEG FULL SCALE

-

EO

Bl B2 B3 B4 B5 B6 B7 BS
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0

EO
EO
-9.920 +10.000
-9.S40 + 9.920

1 0 0 o 0 0
1 0 0 0 o 0
1 1 1 1 I

1
0
1

-O.OSO + 0.160
0.000 + O.OSO
0.000
+O.OSO

0 0 1
000

+9.920 - 9.S40
+ 10.000 - 9.920

0
0
1

ZERO SCALE- LSB 0

-.040 -9.920
.000 -9.960

pO.OOOKS)

o
o

o

0
0

o

0

0
0

0

BASIC BIPOLAR OUTPUT OPERATION

BASIC UNIPOLAR NEGATIVE OPERATION

+20~--~---r--~----~--~---T----~--~---r---'

+16

+12
o

~ +S.O
L.LJ

<.!>

~

<3

+4.0

>

POS FULL SCALE
POS FULL SCAL E - LS8

o

(+) ZERO SCALE

H ZERO SCALE

-4.0 t---+--..,.

8182 8384B5 86 8788
1 1 1 1 1 1 1 1
1 1 I 1 1 1 1 0

1 0
1

• 0

NEG FULL SCALE+Lse\ 0 0
0
NEG FULL SCALE

i°

-S.O
•
•
•
•
•

-12----~--~--~----~--~--~----~--~--~----

+50
TEMPERATURE (OC)

+100

+150

o

EO
+9.920
+9.840

0
1

0
1

0
1

0
1

°

+0.040

1

1

-0.040

0

0

0

0

0

o

0

0

0

0

1
0

-9.840
-9.920

PROVIDES ISOLATION FROM GROUND LOOPS
SYMMETRICAL ttOv OUTPUT
USEFUL WITHIN SYSTEMS BETWEEN BOARDS
TRUE COMPLEMENTARY / DIFFERENTIAL CURRENT TRANSMISSION
HIGH SPEED ANALOG SIGNAL TRANSMISSION

HIGH NOISE IMMUNITY CURRENT
TO VOLTAGE CONVERSION

OUTPUT VOLTAGE COMPLIANCE VS. TEMPERATURE

-17-

IS

DUAL COMPLEMENTARY OUTPUTS

Conventional DAC's have a single output, so they cannot drive
balanced loads and are limited to a single input code polarity.
The DAC-08 was designed to overcome~hese limitations

o mA-

Input coding of positive binary or complementary binary is
obtained by a choice of outputs, 10 for positive-true or 10 for
negative-true. In many applications both are used either
independently or in combination. Dual complementary outputs
allow some very unusual and useful DAC applications:

1.0 mA-

2.0 rnA-

1) CRT display driving without transformers.

lOUT

(t I 1 1'1111)

(0000'0000)

2) Differential transducer control systems.
3) Differential line driving.
4) High speed waveform generation.

TRUE AND COMPLEMENTARY OUTPUT OPERATION

5) Digitally controlled offset nulling of op amps.

+f20VDC

60V COMMON
MODE LEVEL

• FULL DIFFERENTIAL DRIVE LOWERS POWER SUPPLY VOLTAGE
• ELIMINATES INVERTING AMPLIFIERS AND TRANSFORMERS
• INDEPENDENT BEAM CENTERING CONTROLS

CRT DISPLAY DRIVER

v+

•
•
•
•
•

TRANSDUCER:
STRAIN
PRESSURE
TEMPERATURE

FULLY DIFFERENTIAL INPUT
ELIMINATES INSTRUMENTATION AMPLIFIER -LOW COST
DIGITALLY CONTROLLED SYSTEM ZEROING
HIGH CONVERSION SPEED
EXCELLENT COMMON MODE REJECTION

SUCCESSIVE
APPROXIMATION
REGISTER

BRIDGE TRANSDUCER CONTROL SYSTEM WITH
FULL DIFFERENTIAL INPUT

-18-

PARALLEL OUTPUT

SERIAL
OUTPUT

OUTPUT
DUAL COMPLEMENTARY OUTPUTS

VREF

DIGITAL INPUT

DIGITAL INPUTS

256nA
V REF D--JVVIr--(:>-I

•
•
•
•
•

-15V
•
•
•
•

DAC OUTPUT IS 1nA PER STEP
REPLACES NULLING POTENTIOMETER
WORKS WITH OP- 07, OP-05, SSS725
VOS NULLED BELOW NOISE LEVEL

BIPOLAR OUTPUT WITH OFFSET BINARY CODING
PROVIDES DC ISOLATION BETWEEN SOURCE AND LOAD
HIGH VOLTAGE OUTPUT CAPABILITY
USEFUL WITH PULSE OR SINE WAVE REFERENCE INPUT
USEFUL WITH PULSE OR SINE FUNCTION DIGITAL INPUT

BALANCED TRANSFORMER DRIVE

DIGITALLY CONTROLLED
OFFSET NULLING

HIGH SPEED

1) 1 J.1.sec, 2J.1.sec and 4J.1.sec A/D's. (These are completely
described in AN-16, available upon request)

SUb-microsecond settling times are common in current-output
DAC's. Many DAC's settle in 500 nsec; 300 nsec is not
unusual. But 85 nsec settling time for a low cost DAC is
exceptional, and this characteristic allows use of the DAC-08
in formerly difficult and expensive-to-build applications:

2) 15 MHz Tracking A/D's.
3) ECl compatible applications.
4) Video displays requiring a low-glitch DAC.
5) Radar pulse height analysis sytems.

all bits switched ON
FOR TURN-ON, VL' 2.7 V
FOR TURN· OFF, VL .0.7 V

VL

+5 V

2.4 vLOGIC
INPUT

0.4 VOUTPUT -112 LSB SETTLING
0+ 112 LSB-

15Kll

-15V
TO O.U. T.

50 nsec/division

I FS = 2mA RL =1K n
tl2 LSB

= 41'A

FULL SCALE SETTLING TIME

SETTLING TIME MEASUREMENT CIRCUIT

-19-

HIGH SPEED
CLOCK INPUT

OUTPUT
TYPE

SWITCH CONDITIONS

(EO)

S(+)

UNIPOLAR POSITIVE
UNIPOLAR NEGATIVE
BIPOLAR 110 V F S

S H
GND

GND

5KU

,--..J\I\Ar----115

13

81
B2

R2
5KU

83
84

0----11-++-+

850-----+-+-++-+

B6 0----1-+-+-+~
87 0----1'-+-+-+_+_+-'
B8 0----1'-+-+-+-+-+-+....

SERIAL
OUTPUT
START

14 13 12 11 6 5 4 3
1

AM2502

2. FOR TRIANGLE WAVE, COUNT UP TO FULL, REVERSE AND COUNT DOWN.

CONVERSION
COMPLETE
TTL CLOCK INPUT
2.25 MHZ

NOTES: 1. BIPOLAR OU1 PUT IS SYMMETRICAL AROUND ZERO, ADJUSTABLE PEAK TO PEAK
AMPLITUDE.

SUCCESSIVE APPROXIMATION
REGISTER

0--------'

3. FOR POSITIVE-GOING SAWTOOTH, COUNT UP TO FULL, CLEAR, REPEAT.

NOTE 1. CONNECT "START" TO "CONVERSION
COMPLETE" FOR CONTINUOUS CONVERSIONS.

4. FOR NEGATIVE·GOING SAWTOOTH, COUNT DOWN, CLEAR, REPEAT.

NOTE 2. FOR DETAILED LOW-COST DESIGNS
REQUEST AN' 11 AN 0 AN-6.

5. FOR OTHER WAVEFORMS, USE A ROM PROGRAMMED WITH THE DESIRED FUNCTION.
6.85 nsec SETTLING TIME PERMITS WAVEFORM PERIOD OF 25.6 "sec, OR 39 KHz
REPETITION RATE

3 IC LOW COST AID CONVERTER

HIGH SPEED WAVEFORM GENERATOR

+5V

ANALOG 0 TO + 10 VOLTS
INPUT

+ 15V

=
MS8o---~-------------~

L S 8 o - - - - + - - - - - - 4 - - - - - - - + - - - - - - + - - - - - -__-------~------~------·~------~

I

CLEAR AND
RESET
(STROBE)

IL

________________________________ J
GATED
6.5MHz
CLOCK
CP2

SIMPLIFIED SCHEMATIC 1J.1sec AID

- 20-

LOGIC INPUTS
ADJUSTABLE INPUT lOGIC THRESHOLD
1) ECl applications without level translators.

Most DAC's have TTL or CMOS compatible inputs which
require complicated interfaces for use with ECL, PMOS,
NMOS or HTL logic. By contrast, the DAC-08, with typical
logic input current of 2J1A and an adjustable input logic
threshold, interfaces easily with any logic family in use today.
The logic input threshold is 1.4V positive with respect to
pin 1; for TTL pin 1 is therefore grounded; for other families
pin 1 is connected as shown in the interfacing figure.
An adjustable threshold and a -10V to +18V input range
greatly simplify system design especially with other-thanTTL logic:

2) Direct interfaces with Hi-Z RAM outputs.
3) CMOS applications without static discharge considerations.
4) HTL or HNI L applications without level translators.

5) System size, weight, and cost reductions.

VTH = VLC +1.4 V
TTL,DTL
VTH s +1.4V

+15V CMOS, HTL, HNIL
VTH = +7.6 V

+12 V TO +15 V

6.2 V
ZENER
-5V TO -10V
NOTE: DO NOT EXCE ED NEGATIVe
LOGIC INPUT RANGE OF DAC

-----------------------T--~-----------I
+5V CMOS

+10V CMOS

I

I
I
I
VLC
IN4148

10K ECL

I

VTH=-1.29V

1.3K.n

I
I
I
I
I

3.9 K.n

I
I
I
I
I

INTERFACING WITH VARIOUS LOGIC FAMILIES

-5.2V

2.0
1.8

v-

V+

...

1.6

~

...........

1.4

............

.........

1.2

]

~ ......

u

>...J 1.0

"'~ ~

"'

':r:
;t'0.8
0.6

..n...r1CMOS DATA INPUT

0.4
0.2
0

o

-50

+50
TEMPERATURE, 'C

+100

+150

V TH - V LC VS. TEMPERATURE

CMOS DIFFERENTIAL LINE DRIVER/RECEIVER

500

400

2.4 yBIT 8
LOGIC INPUT

300

0.4YOY200

8~A-

lOUT

~

0-

100

,

1LSB' 61 nA

~

II
.05

-

1LS\ = 7.B,.A

I

.01 .02
.05 0.1
0.2
0.5
1.0 2.0
[FS, OUTPUT FULL SCALE CURRENT (mAl

II
5.0

10

14

16

50 nsec/division

LSB SWITCHING

IREF=2.0mA

:i

LSB PROPAGATION DELAY VS.I FS

BI

1.0

:i

oS

i::i

f-

i::i

6.0

~

f-

g:
3

0.8

Cl::
Cl::

~

3

4.0

~ 0.6
B2

CL
f::J

o

0.4
2.0

l

B3
0.2

_~=-15V

o

-12 -10

B4
(ft5V

B5
-8.0 -6.0 -4.0 -2.0 0
2.0 4.0 6.0 8.0 10
LOGIC INPUT VOLTAGE (valls)

12

14

16

18

o

-12 -10 -8.0 -6.0 -4.0 -2.0 0
2.0 4.0 6.0 8.0 10
LOGIC INPUT VOLTAGE (valls)

12

NOTE: Bl THROUGH B8 HAVE IDENTICAL TRANSFER CHARACTERISTICS.
BITS ARE FULLY SWITCHED, WITH LESS THAN 1/2 LSB ERROR, AT
LESS THAN ± 100mV FROM ACTUAL THRESHOLD. THESE SWITCHING POINTS ARE GUARANTEED TO liE BETWEEN 0.8 AND 2.0
VOLTS OVER THE OPERATING TEMPERATURE RANGE (VlC =O.OV).

BIT TRANSFER CHARACTERISTICS

LOGIC INPUT CURRENT VS. INPUT VOLTAGE

18

REFERENCE INPUTS

MULTIPLYING CAPABILITY
Fixed internal references are included in many DAC's, but
they limit the user to non-multiplying, single polarity reference

1) Digitally controlled full scale calibration.

applications and do not allow a single system reference. To
achieve the design goals of low cost and total applications
flexibility, the DAC-08 uses an external reference. Positive or
negative references may be applied over a wide common mode

2) 8 x 8 multiplication of 2 digital words.

voltage range. In addition, the full scale current is matched to
the reference current eliminating calibration in most applications.

MSE

I~

+ VREF

:'

3) Digital Attenuators/Programmable gain amplifiers.
4) Modem transmitters to 1 MHz.
5) Remote shutdown and party line DAC applications.

LSB

VREF (+)
4

14

RREF
(RI4)

~

R15

-VREF

-10

RREF

DAC-08

R15'

15

2

-10

- VREF
255
I FS '" RREF x 256
.II'F

.II'F*_

I_

V-

v+

NOTE 1. RREF SETS IFS; R15 IS FOR
BIAS CURRENT CANCELLATION.

FOR FIXED REFERENCE, TTL
OPERATION, TYPICAL VALUES
ARE:
VREF = +10.000V

10 + fO = IFS FOR ALL
LOGIC STATES

RREF = 5.000K
R'5 '" RREF
Cc =0.01I'F
VLC =0 V (GROUND)

BASIC NEGATIVE REFERENCE OPERATION

BASIC POSITIVE REFERENCE OPERATION

All bits ON

5.0

I

TA = T min 10 T max

r---- :-- ALL

BITS "HIGH"

~

~
I-

~ 3.0

a::
a::

:;)

u

I-

ir

~ 2.0

o

~
1.0

V

V

/

/

2.8

LIMIT FOR
........... V-=-15V

TA=Tmin 1o Tmox
4.0

/

/

/

1/

2.4
V-= -15V

V-=-5 V

'-~I_M=I~~SR

J

r

1.6

r

0.8

IREF=lmA

I

I

IRE[=0.2mA I

I
3.0
2.0
IREF, REFERENCE CURRENT (mA)

IREF=2mA

1.2

0.4

1.0

V+=+15V

2.0

4.0

0_ 14 -12 -to

5.0

I
-8 -6 -4 -2
0
2
4
6
8
10 12
V'5, REFERENCE COMMON MODE VOLTAGE (volts)

14

NOTE: POSITIVE COMMON MODE RANGE IS ALWAYS (V+)-1.5 V

REFERENCE AMP COMMON MODE RANGE

FULL SCALE CURRENT VS. REFERENCE CURRENT

- 23-

16

18

DIGITAL
CONTROL

• IREF ~ PEAK NEGATIVE SWING OF liN

•
•
•
•

o-.JVV\r---i 14

DAC-08

AC VOLTAGE TO DIFFERENTIAL CURRENT CONVERSION
DC TO tMHz INPUT RANGE
OUTPUT DRIVES TWISTED PAIR DIRECTLY
CMOS COMPATIBLE

VIN~

15
HIGH iNPuT R15 (OPTIONAL)I.-_ _ _ _ _J
IMPEDANCE
• +VREF MUST BE ABOVE PEAK POSITIVE SWING OF VIN

ACCOMODATING BIPOLAR REFERENCES

MODEM TRANSMITTER

WORD" A" INPUT

-15 V

+15V

±5%

INPUT
R2
10Kn
+15 V

EO

B7 o--t-H-t-H....
LSB B8 o-+-I-+-H-+~

-15V

5 6 7 8 9 1011 12
R5
...-----"Nv---114
14Kn

DAC-08

R6

•
•
•
•

FAST -85 NSEC PLUS OP AMP SETTLING TIME
ANY LOGIC FAMILY FOR WORD "A" OR "B"
BIPOLAR OUTPUT
ELIMINATES SEVERAL LOGIC PACKAGES

BIPOLAR INPUT} PERFORMS 2 QUADRANT
OFFSET BINARY
MULTIPLICATION-AC INPUT
OUTPUT
CONTROLS OUTPUT
POLARITY.

DIGITAL ADDITION OR SUBTRACTION
WITH ANALOG OUTPUT

+ 15 V

NOTES: 1. Rl=R2=R3
2. R4=R5
3. EO DC TO 20 KHZ", ±5 V
4.EO DCTO 10 KHZ"±10V

DC-COUPLED DIGITAL ATTENUATOR/
PROGRAMMABLE GAIN AMPLIFIER

WORD "B"
DIGITAL INPUTS

RI

•
•
•
•
•

-t5V

R3
10Kn

IFS IS THE PRODUCT OF 2 DIGITAL INPUT WORDS
MAY BE USED AS A 8x8 DIGITAL MULTIPLIER WITH ANALOG OUTPUT
ELIMINATES DAC AFTER DIGITAL MULTIPLICATION
FUNCTIONS WITH ANY LOGIC FAMILY
NOTE: LIMIT WORD "B" INPUT RISE AND FALL T.IMES TO 200NSEC MINIMUM

DIGITALLY CONTROLLED FULL SCALE CALIBRATION (MULTIPLIER)

POWER SUPPLIES

POWER SUPPLY REQUiREMENTS
The DAC-08 works with ±4.5V to ±18V supplies allowing
use with all standard digital and analog system supply voltages

8.0

plus most battery voltages. With only 33mW of power dissipation at ±5V and 85nsec settling time, it has a lower speed
power product than CMOS DAC's. Power dissipation is almost
constant over temperature, and bypassing is accomplished
with 0.01 J.l.F capacitors-no large electrolytics are required.
These power supply requirements allow:

I

I

I

ALL BITS "HIGH" OR "LOW"
I

7.0

V- =-15V

1-

6.0
[REF

=2.0mA

5.0

4.0

1) Battery operation.

3.0
V+ = +15 V

1+

2.0

2) Use of unregulated or poorly regulated power supplie~.

1.0

3) Use in space-limited areas due to small bypass capacitors.

0

o

-50

+50
TEMPERATURE (DC)

+100

+150

4) Use in constant power dissipation applications.
5) Common digital and analog power supplies.

POWER SUPPLY CURRENT VS. TEMPERATURE

8.0

8.0

I

I

ALL BITS "HIGH" OR "LOW"

BITS MAY BE "HIGH" OR "LOW"
7.0

7.0

1- WITH [REF=2mA

16.0

6.0

5.0

5.0

4.0

4.0

3.0

3.0

[-WITH lREF~'mA

I

I

[-WITH [REF =0.2mA

1+
2.0

2.0

1.0

1.0

2.0

4.0

6.0
8.0
h
V+. POSITIVE POWL

'2
14
J"PPLY (Vdc)

16

18

20

'\.. -1+

-2.0

-4.0

-6.0
-8.0
-10
-12
-14
V-, NEGATIVE POWER SUPPLY (Vdc)

-16

POWER SUPPLY CURRENT VS. V-

POWER SUPPLY CURRENT VS. V+

-25-

-18

-20

OTHER APPLICATIONS
"1" = COUNT UP, "0" =COUNT DOWN

DATA
BUS

MICROPROCESSOR APPLICATIONS
The ability to use' J1P power supply voltages and the ability
to interface with any logic family make the DAC-08 especially
useful in J1P applications:

OTO-10V
ANALOG
INPUT
+5.000V
2.5KD.

1) Tracking AID converters.
2) Successive approximation AID converters.

2.5KD.

3) Direct drive from Hi-Z MOS RAM outputs.
5KD.

+5V

By programming the ROM's with the successive approximation or the tracking AID algorithm, all of the logic for AID
conversion is contained in the J1P. This is a very inexpensive
approach, since there is no need for the usual AID conversion
logic packages.

•
•
•
•
•
•

-15V

-15V

USEFUL FOR ENCODING DC INPUTS
ELIMINATES UP/DOWN COUNTERS
ANSWER CONTINUOUSLY AVAILABLE
LOW POWER CONSUMPTION
HI-Z INPUT
RAM OUTPUTS MAY BE USED IN PLACE OF TTL I/O

MICROPROCESSOR CONTROLLED
TRACKING AID CONVERTER

OTHER APPLICATIONS:

The following list summarizes
just a few of the many applications for this flexible DAC.
Consult the factory for further information.

GRAPHICS AND DISPLAYS

AID CONVERTERS

DATA TRANSMISSION

Polar to Rectangular Conversion
CRT Character Generation
Chart Recorder Driver
CRT Display Driver

Modem Transmitter
Differential Line Driver
Party Line Multiplexing of Analog Signals
Multi-level 2-Wire Data Transmission
Secure Communications (Constant Power Dissipation)

Tracking (Servo)
Successive Approximation
Ramp (Staircase)
Microprocessor Controlled
Ratiometric (Bridge Balancing)

CONTROL SYSTEMS
TEST SYSTEMS
Transistor Tester (Force IB and Ie)
Resistor Matching (Use both outputs)
Programmable Power Supplies
Programmable Pulse Generators
Programmable Current Source
Function Generators (ROM Drive)

Reference Level Generator for Setpoint Controllers
Positive Peak Detector
Negative Peak Detector
Disc Drive Head Positioner
Microfilm Head Positioner

AUDIO SYSTEMS
Digital AVC and Reverberation
Music Distribution
Organ Tone Generator
Audio Tracking AID

ARITHMETIC OPERATIONS
Analog Division by a Digital Word
Analog Quotient of Two Digital Words
Analog Product of Two Digital Words-Squaring
Addition and Subtraction with Analog Output
Magnitude Comparison of Two Digital Words
Digital Quotient of Two Analog Variables
Arithmetic Operations with Words from Different
Logic Families

CONCLUSION
High voltage compliance complementary current outputs,
universal logic inputs and multiplying capability make the
Precision Monolithics DAC-08 the most versatile monolithic
high speed DAC available today.

-26-

APPLICATION NOTES AVAILABLE UPON REQUEST
AN-12

"Temperature Measurement Method Based On
Matched Transistor Pair Requires No Reference"

AN-13

"The OP-07 Ultra-Low Offset Voltage Op AmpA Bipolar Op Amp That Challenges Choppers,
Eliminates Nulling"

"Instrumentation Operational Amplifier with Low
Noise, Drift, Bias Current"

AN-14

"Interfacing Precision Monolithics Digital-ToAnalog Converters With CMOS Logic"

AN-l0

"Simple Precision Millivolt Reference Uses No
Zeners"

AN-15

"Minimization of Noise in Operational Amplifier
Applications"

AN-ll

"A Low Cost, Easy-To-Build Successive Approximation Analog-To-Digital Converter"

AN-16

"High Speed
DAC-08"

AN-2

"Monolithic

Chip

Assembly

Information"

AN-5

"Applying a Monolithic 10-Bit 01 A Converter"

AN-6

"A Low Cost, High-Performance Tracking AID
Converter"

AN-9

-27-

AID

Conversion

Using

The

3. DTL Peripheral/Power Drivers - "A Giant Step Backward"

Reverting to DTL Adds New Dimensions To
Sprague Peripheral/Power Drivers
Paul R. Emerald
Manager, Applications Engineering
Digital Products
Sprague Electric Company
Worcester, Masso
Introduction
Although not widely known in the industry, Sprague Electric
was one of the pioneers with Peripheral/Power Driver ICs; the
Sprag~e UHP 400{500 series quad drivers being introduced in 1970.
Concurrently Texas Instruments was bringing out its 75450 series;
and, although the circuit types are quite similar, each is
targeted at somewhat different markets. The TI dual drivers are
high speed, lower output breakdown devices chiefly sold in 8
lead mini DIPs; while the Sprague power drivers were introduced
as quad, high voltage, moderate speed devices supplied in a 14
lead DIPo
The design and manufacturing of a quad driver meant rather dramatic
deviations from any standard bipolar processing/packaging/circuit
design techniques in use at the timeo To allow the use of four
high current outputs in the same DIP necessitated developing high
beta, high current, high voltage output NPNs; chiefly done to
minimize package power dissipation when confronted with a quad 14
LDIP rather than an 8 lead dual mini DIP driver o Reducing the
ICC drive power for the output transistor via improvements in high
current beta significantly affected the overall package powero
Further it was necessary to utilize a copper alloy lead frame for
the DIP; another requirement if the units were to be used in
systems requiring the four outputs to be energized continuously
and simultaneously. The standard Kovar (iron alloy) in use
definitely would not allow this, but the change to a copper alloy
package frame reduced the DIP 0ja (junction to ambient rise) from
+125 0 C/W (Kovar) to a figure of +60 o C/W (copper). The
combination of the high beta process and dramatic improvement in
package technology allowed the Sprague quad power drivers to
simultaneously and continuously switch 250mA in all four outputs,
in a +70 o C ambient without exceeding a junction temperature of
+150 o Co

-28-

The Sprague Electric UHP 400/500 series quad drivers have been
an industry standard for the past few years. Schematically the
UHP 407/507 is shown in Figure 1; these ICs are available with
NAND, NOR, AND, and OR logic gates and with three output breakdown minimums, the 400 series at 40 volts, 400-1 series at 70
volts, and 500 series with 100 volt output breakdown. Additionally
there are four basic relay driver types which incorporate
internal transient suppression diodes for use with inductive loads.
All types are guaranteed to sink a minimum of 250mA with a VCE(sat)
of less than 0.7 volts, and all are compatible with TTL and DTL
logic families.
VCC

CATHODE
COMMON

FIGURE I

40V507 SCHEMATIC

Electromechanical Loads
Primarily the Sprague high current/high voltage drivers have been
designed for use with electro-mechanical loads. No attempt has
been made to produce a high speed device; moderate switching
speeds result in less noise generation during output transitions o
Virtually all peripheral loads are much slower than any
semiconductor switching device, and it is neither necessary nor
desirable to utilize high speed switching for interface to
electromechanical loads. Needs for decoupling and/or critical
PC board layout are diminished with slower switching devices
coupled with the serious attempts to minimize logic circuit power
(ICC 0).
High Voltage/High Current ICs
Many design and process changes were imposed to create the Sprague
drivers; to obtain the high voltage output NPNs it was necessary
to modify the N doped epitaxial layer. The epi layer has been
increased in both thickness and in resistivity to provide higher
output breakdown. These changes meant that these ICs more
resembled linear circuit processing than TTL digital process
techniques.
-29-

Transistor design tolerances were quite dramatically changed to
sustain the much higher "OFF" voltages required of these circuit
applications. Much deeper junctions with greater curvature
and rounded transistor diffusions (another element of the
curvature) were part of the design modifications for improving
breakdown voltages. Through use of these techniques it became
possible to achieve breakdowns of 100 volts very repeatably.
A combination design/process addition was also instituted to
minimize the output NPN saturation voltage. The use of higher
resistivity epitaxial layers would have adversely affected the
collector/emitter VCE(sat) were it not for the use of a highly
doped, low resistiv~ty collector diffusion. Necessary was the
addition of a low resistivity N+ collector plug which is driven
sufficiently to contact the N+ buried (floating) collector
diffusion beneath the NPN base.

FIGURE 2

CROSS SECTION MONOLITHIC POWER NPN

The cross sectional view of Figure 2 indicates the series collector
resistance associated with the buried N+ collector plug. Without
the low resistance collector diffusion the series resistance
between the buried N+ collector and the metalization on the chip
surface would be much higher. Through use of the N+ collector
diffusion, which also serves as an N+ surface guard ring to prevent
unwanted inversion of the epi, it is possible to achieve an Rsat
of less than 1 ohm (very large, high current circuits) to a more
standard 2 to 3 ohms collector resistance.
Package Availability
The original quad power drivers (400/500 series) have been supplied
to commercial/industrial users in the previously mentioned plastic
DIP using a copper lead frame, thus allowing use of all four
outputs simultaneously and continuously'at 250mA each. Also
supplied, primarily for military systems, have been two types of
fully hermetic packages; a 14 lead ceramic DIP, and a 14 lead flatpack - both manufactured to meet the requirements of MIL STD 883.

-30-

The newer additions to this product family, the DTL VDN 3600M
and 5700M dual drivers, have added a new package type. The
series of dual devices is supplied in a copper frame 8 lead
mini DIP, and the 3600 series units are pin for pin with the
National LM 3611 etc., as well as the higher speed TI types
(75451 etc.).
The new DTL quads (VDN 5700A series) also have added a new
package - the 16 lead copper frame DIP. Use of the 16 LDIP was
largely predicated upon the desire for all gates to have
separate inputs, rather than a pair connected (strobed) together,
thus somewhat improving the versatility of the quads. All the
newer plastic power drivers benefit greatly from the improved
0ja of the copper frame packageo
The new DTL types with their improved electrical parameters will
also be supplied in fully hermetic packages to MIL 883 for use
in adverse environments or military systems requiring a full
temperature range unit and/or hermeticity. Some reduction in
package dissipation potential results, but the ease of interface
to logic families such as CMOS with the newer DTL circuits will
benefit those unable to obtain standard TTL or CMOS logic with
either sufficient output current and/or the high breakdown
capability (80 volts) of these ICs.
Standard package power curves are shown in Figures 3A (plasti'c)
and 3B (hermetic). The curves of Figure 3A compare the two
copper lead frame DIPs with the capability of the Kovar frame
packages used for standard lower power circuits. Any area
beneath the appropriate package curve represents allowable
average power and is plotted against ambient temperature to a
+85 0 C limit. It is quite apparent that both the mini DIP at
+80 o C/W and the 14 or 16 lead quads at 60 oC/W with copper
frames are much superior to the Kovar DIP with a rating of
+125 0 C/W.
FIGURE 3A

25W

ZOW

1.5W

- - I'\..

I"-

DEVICE LIMIT

'"

-

~

,
"

"

'" ,,,
' ~-

~

,,
, , ,,

'
" ".......' \,.
... ......

... ... ~,
...

....
-25

50

85

AMBIENT TEMPERATURE (oCI

100

I

-

25

--.t-

""c~-*--------1

I.

IJ
-31-

--- .- --

I

________________

I

150

-ll

"o·'4~1··~

"'"

05W

"

----Il

1

-~

C/W

;'~

\

"
~

I

~

~-j>

C:0,0

~25·C/W

'4<\>

0_5W

I

i15wlt"-,,,.I "-.. 100-;--

80·C/W\

~

UHC/UHD 400/500 SERIES

"·i1-T-·~

5700A SERIES

''(c/W

--

I.OW

!-- r-------FIGURE 38

UH'iUDN PLASTIC PACKAGES

-

I

- - - - - - - - - - - ; - - - -------------

5C--

AMBIE~T TEMPERATURE 1·(1

::'..' ,

------ -~
CO

IZ5

5C

The curves of Figure 3B apply to the hermetic packages used with
the series 400/500 quads. This shows that the differential in
the materials used and the size of the package have a considerable
bearing on the package dissipation limits. The flatpack is the
poorest of all, and should not be used unless there is
insufficient space (chiefly height) for the hermetic DIP. With
either type the average power is reduced, particularly if the
ambient temperature is to reach +125 0 C.
These 0ja rating curves show the maximum junction temperature rise
with a unit of power applied" the plastic types are generally
restricted to uses below +85 0C, while the hermetic units may be
used up to +125 0 C. In either case the upper junction limit will
not exceed a +150 0 C level, and is shown by the dashed lines
extending to zero (O)power at +150 0 C. Operating within these
ambient temperature/average power limits will insure that the
junction temperature does not exceed +150 0 C, since variations in
manufacturing and electrical parameters are guardbandedo
DTL Logic - "A Giant Step Backward"
Through ongoing evolutionary improvements the power drivers have
seen a series of improvements; the most notable being a conversion
to a DTL logic gate in the UDN 3600 and 5700 series. Others have
been made affecting the high current output NPN and a small
reduction in the typical ICC 0 powero
Converting the logic gate (Figure 4 - schematic 5707/5712) to
a diode input (DTL) has brought new potential applications into
the picture, particularly the use with CMOS and PMOS circuitry.
Prime advantages are associated with the much higher input
voltages allowed (up to 30V), and the extremely low logic "0"
input current (lOO~A maximum vs 1.6mA for a standard TTL). This
comparison is between the new, improved Sprague DTL types and
the TI 75451 types and the LM 3611 series by National. The
earlier Sprague UHP 400 family had an industry low of 800~A
(1/2 TTL load), and that has subsequently been reduced further to
a 100~A maximum (200~A on strobe inputs) thus allowing use with
CMOS and PMOS logic; while the TI and National TTL types have
the standard lo6mA TTL maximum.
Vee

FIGURE 4

570V5712 SCHEMATIC

-32-

Lamp Interface - Inrush Current
One type of application these IC drivers are well suited to is
the switching of incandescent lamps. Of great concern to those
using semiconductor devices for switching lamp filaments
is the high inrush (surge) current associated with cold lamp
filaments. When switched with either mechanical or electromechanical switches this inrush current may reach a value that
is 1000% to 1200% of the nominal steady state current. This
lO-12X the nominal can be disastrous to lower current Ies since
they are unable to sustain the instantaneous currents of a
cold filament and are prone to destruction; usually resulting
from secondary breakdown during turn on of the output.
A technique frequently employed to obviate this ty,pe of failure
with lower current devices is the use of "warming r resistors
across the switching output. Maintaining the filament partially
warmed reduces the inrush (surge) current in the transistor, but
it complicates designs considerably when a large number of lamps
are used. The high current peripheral/power drivers are able to
sustain these momentary inrush currents; and, hence, it is not
necessary to add one "warming" resistor for each lamp.
The Sprague power drivers have been widely used since 1970 in
systems employing them as lamp drivers, and the most typical
is a parallel pair of 28 volt, 40rnA lamps (#327 or #387) switched
by each NPN output. Even though none of the standard IC
peripheral/power drivers available will be in saturation under
conditions of lamp inrush, they have been designed to sink
currents of 300rnA (well saturated) and are able to sustain the
momentary high powero The transistor design and process chosen
precludes these drivers from failure due to secondary breakdown
when used in a conventional mannero
The current at which the output comes out of saturation is
related to the transistor design (chiefly emitter periphery) and
process related variables: beta of output NPN, diffused resistor
tolerances (determine base current of output), etce As the
graph of inrush current shown in Figure 5 indicates, the time
necessary to reach a current level within the device saturation
level is less than 5 millisecondso Even assuming the use of two
(2) lamps in parallel, which is the typical case (current value
is thus skewed by a factor of two), the outputs of these power
drivers will need only sustain an inrush period of approximately
2 to 3 milliseconds (intersection at e12A). The newer DTL
units with a guaranteed output saturation voltage at 300mA are
somewhat better than the earlier UHP 400/500 series, although
neither has given trouble with inrush currents when used with
#327 or #387 lampso

-33-

TYPICAL

INRUSH CURRENT

vs
TIME WITH DESIGN VOLTS APPLIED
LAMP NO. 327
0.40
0.36
0.32
0.28

I
0.24
Ul

W

0.20

a::
w

a.

0.16



~

........

"""'-,
....

....

,

......

"',
""

-2~

50

70

811

100

""

"
150

AMBIENT TEMPERATURE (oC)

FIGURE 20

SPRAGUE .. NATIONAL

The Sprague UDN 3611 or 5711 will have a worst case power (same
conditions of Vee and Ie) of only 677mW, and is also manufactured
in a DIP package capable of sustaining 1.OW rather than the

-44-

727mW limit. A clear advantage for lower junction temperatures,
less heat, and/or greater output capability in a systemo Maximum
junction temperatures obtained would be: LM 3611 with 782mW
~ l56°C; 75451 with 76lmW ~1530C; and the Sprague UDN 3611/5711
with 677mW ~ l24oC.
Stepping Motor Applications
Combining the use of a peripheral/power driver and a dual
Darlington switch (type ULN 2061) provides a capability of
driving a 4-phase bifilar stepping motor. Motors designed to
operate with voltages and currents compatible with these ICs
may be driven with a minimum of components. In Figure 21 the
signals from appropriate logic/sequencing circuitry operate a
Sprague UHP 407 or UDN 5707 (may also be done with two UDN
57l2s) for 'switching the motor coils selected. The transient
suppression diodes are utilized here as per solenoid/relay
applications, although here they are connected through a zener
diode to the supply voltage. The zener will improve the speed
of the switching, but should be chosen such that the maximum
voltage across the output (+V added to VZ) is below the device
breakdown. Permitting voltage excursions of this sort produces
improved high speed motor operation, but must be clamped to a
safe valueo
STEPPING MOTOR DRIVE
FIGURE 21
UON-5707

Applications requ~r~ng a holding or detent current may employ
a dual Darlington (ULN 2061) ,as shown. One Darlington switch
is used for the RUN mode, while the second (lower) half of the
2061 is used to provide a lower, holding current to maintain
the position of the motor. Use of two supplies is shown, and
diode Dl decouples the power supplies and prevents unwanted
reverse bias from reaching the STANDBY Darlington. Similar
schemes may be employed to obtain bipolar drive schemes for

-45-

high speed stepping motor applications. Current is spurced
from the positive supply (a PNP switched by a gate capable of
sustaining the supply voltage is one example), while an
appropriate peripheral/power driver is used to sink coil
current per Figure 21.
Control 100 Watts With an IC
The quad peripheral power drivers are capable of controlling
(switching) loads that total 100 watts per package (50 watts
for duals). Load currents beyond the standard 250mA level
(UHP 500s) or 300mA (UDN 5700A quads) would result in the
capability of switching loads in excess of the 100 watt
capability with standard specifications.
The UHP 500 series has a 100 volt/250mA capability for each of
four outputs: 100V X .25A X 4 outputs = 100 watts of controlo
The 'UDN quads offer an 80 volt/300mA comb.ination for each of
four outputs: 80 volts X .3A X 4 outputs = 96 wattso
All of these high current/high voltage peripheral/power drivers
offer simple, inexpensive interface solutions to some tough
load requirements. Those applications beyond the output voltage
and/or current handling limits of lower current, TTL type
devices are quite easily handled with these units. Additionally,
the newer DTL types provide solutions to interface problems
associated with PMOS or CMOS that are quite often impossible
with TTL type unitso The "giant step, backward" actually
results in a product "stride forward' with the newer DTL
peripheral/power drivers.

-46-

4.

I.

MASTERSLICE LSI -- THE COST EFFECTIVE ALTERNATIVE
DR. CHARLES A. ALLEN
Vice President of Engineering
International Microcircuits, Inc.
Santa Clara, CA 95051
What is Masterslice LSI?

Masterslice LSI is a cost-effective approach to the design and manufacture of custom integrated circuits. A Masterslice circuit is a
predesigned and preprocessed array of logic elements, ready to be
customized for each special requirement. Each Masterslice circuit
also contains bonding pads, input and output buffering circuits, and
cross-over elements that may be interconnected in a vast variety of
patterns to form any sort of complex or specialized logic function.
The physical arrangement of these elements is the same for each application. Only the interconnect wiring pattern is unique for each new
design.
The use of Masterslice LSI is straight-forward.
Even with many of the
design trade-offs left in the hands of the system designer, the procedure is not complex and can usually be learned in a few days by an
experienced circuit or logic designer.
The basic steps are these:
1.

After the system is specified, it is partitioned appropriately and the desired circuit function is defined.

2.

The detailed logic design required to implement the function is fully designed.
Breadboarding is often valuable
at this point as a functional check.

3.

The detailed logic design is converted to a complete circuit design showing every transistor and every electrical
connection required. A count of Input/Output lines and
logic elements will indicate which of the available Masterslice circuits can accommodate the required function.

4.

Since the elements on the Masterslice circuit are already
physically placed, the remaining design effort required
is the physical placement of all the interconnect wiring.
This is done by sketching the desired wires on a large
drawing of the Masterslice chip. This process is similar
to the layout of a complex printed-circuit board involving
an element of trial-and-error and requiring both some
intuitive feel for the grouping of the various parts of the
circuit and a careful attention to detail to assure that
every wire is correctly shown.

5.

This interconnect sketch is used to produce precision artwork which will determine where the aluminum interconnect
wiring on the Masterslice wafer is to be located.
This
artwork is also used to check against the logic design performed in Step 2, and the detailed circuit design performed
in Step 3 to assure that no errors have been introduced in
the process of translating the logic design into chip artwork.
-47-

6.

A photomask produced from this artwork is used to perform
the aluminum etching step on a preprocessed Masterslice
wafer.

7.

The resulting chips are inspected, diced, packaged, tested,
and shipped to the customer.

The Masterslice approach to custom LSI has several obvious advantages
over the conventional custom-design process.
1.

The chip design cycle is very short since most of the engineering has been done before the custom design starts.
Only one of the six or seven photomasks must be customized
for each new custom circuit, and even that mask has over
80% of the geometries already specified. Only the noncritical geometries of the interconnect wiring need to be
added to complete the chip design. Typical design cycle
from logic drawing to finished artwork is three-to-four
weeks rather than three-to-four months as in a conventional
design.

2.

The engineering costs associated with chip layout are correspondingly reduced since these costs are almost entirely
manpower and overhead.
Typical layout and artwork charges
for a Masterslice chip are $500 to $2,000 rather than the
$3,000 to $15,000 required for a conventional design.

3.

Tooling costs are very low in the Masterslice approach
since only one new mask needs to be manufactured for each
new custom circuit in place of the usual six or seven masks.
The rest of the tooling is common across a large number of
Masterslice users, so that the costs can be amortized widely.

4.

Prototype manufacturing schedules are very short since 80%
of wafer processing has already been accomplished.
Only
the metal interconnect etching remains to be done. Prototype schedules of two-to-four weeks are easily attainable
in place of two-to-three months with conventional custom
designs.

5.

Because the tooling costs are low and the turnaround time
is short, it is viable to institute changes and updates to
the circuit as market conditions change.

6.

Production prices after the prototype stage are very low
for low or moderate volumes since much of the processing
can take advantage of the large volume associated with all
the custom parts being produced on a given Masterslice
rather than the very small volumes associated with a
single custom circuit. A typical wafer lot will yield
10,000 to 40,000 finished circuits, which is frequently
more than the total annual production of a single custom
circuit. With a conventional approach, all the wafers in
a lot must be personalized for a single-part type, and thus
the manufacturer is faced with either feast or famine,
depending on final test yield.
The Masterslice approach
allows the wafer lot to be split at the metal etch step
-48-

into sublots as small as one wafer, and thus production
runs as small as 100 pieces are feasible.
7.

Rapid changes in production volume can easily be accommodated using the Masterslice approach. With a total production cycle of four-to-eight weeks including overseas
assembly and final testing, the production schedule can be
increased or decreased on a monthly basis with little risk
to either the supplier or the customer.
Even if changing
market conditions require that the program be canceled
altogether, the pipeline is so short that usually only a
one-month notice is required.
The uncommitted wafers can
readily be diverted to other custom circuits at almost no
penalty.
In a usual custom design, with a production pipeline of four-to-five months, the impact of changes in
either demand or yield are much more severe and the cost
associated with cancellation can be very substantial.

The advantages of Masterslice LSI over standard SSI and MSI design are
many and well known:
1.

Size.
By reducing five-to-forty packages to a single package, the overall system can usually be made much smaller
and lighter, often opening up entirely new markets.

2.

Reliability.
Integrated circuit reliability is usually
related to the number of connections to the outside world
rather than to the number of switching elements. Equally
important, with a single package it is frequently attractive to spend a few more pennies per package for greater
integrity or for active burn-in to further improve
reliability.

3.

Market Monopoly. A custom circuit which is available to
you but not to your competition allows you to sell your
creativity at a substantial profit. A design using standard parts, on the other hand, is an o'pen invi tation to any
and all competitors to capitalize on your creatlvity.

4.

Dependable Parts Supply. Standard parts appear and are
discontinued or "unavailable" for reasons over which a
single customer has no control or foreknowledge.
With a
custom part, however, production and delivery schedules can
be directly monitored and controlled, and thus there are
fewer surprises in your production schedule.

5.

Cost.
The major advantage of LSI is in reducing total
system cost by reducing dramatically the cost of assembly,
test, rework, printed-circuit boards, system-interconnect
sockets and cables, power supplies, cooling elements,
frames and covers, and all the miscellaneous costs of supporting the numerous circuit packages in a standard SSI-MSI
design.
Since these support costs increase year by year as
labor and material costs increase while LSI costs per circuit
function decrease with improvements in processing yield, the
cost advantage of LSI has become more pronounced each year
and this trend can be expected to continue for many years to
come.
-49-

The advantages of Masterslice LSI over conventional custom designs are
less well known:
1.

Schedules. A Masterslice design cycle from conception to
volume production is typically three-to-four months rather
than 12-to-18 months with a fully custom design.

2.

Engineering Costs. The nonrecurring costs associated with
a Masterslice design typically amount to $4,000 to $6,000
rather than $50,000 to $100,000 for a fully custom design.

3.

Availability. It is feasible to develop a Masterslice chip
for production runs as low as 100 parts, while it is rarely
possible to find a fully custom vendor willing to tie-up
scarce engineering talent without guarantees of over 100,000
parts per year.

4.

Ease of Change. Since the tooling investment
process are so low with a Masterslice design,
to modify either the design or the production
match a changing market. Contracts for fully
on the other hand, must be much more rigid to
supplier from enormous scrap charges.

5.

Continuity of Supply. All Masterslices being presently
offered are designed around standard wafer and assembly
technology, with the expectation that a single design can
be fabricated at anyone of a number of semiconductor or
packaging facilities.
Thus, the risk of "losing the recipe"
is minimized.
In addition, since preprocessed wafers are
stockpiled ready for personalization, short-term fluctuations
in either demand or yield can be quickly compensated for
with almost no impact to the customer.

6.

Ease of Communications. The system designer's role in a
Masterslice design is very similar to his accustomed role
in designing and testing printed-circuit boards and subassemblies, so that there are very few new skills to learn
and no mysteries that must be accepted on faith. With the
design kits and manuals provided, an experienced designer
can become conversant with the Masterslice details in a few
days. And he can use his unique perspective on the market
and system environment to optimize the LSI circuit function.
With a fully custom design, the costs are so large, the
schedules so long, and the risks so great that they normally
involve numerous layers of purchasing, marketing, legal,
production, quality, and shipping departments until the
system designer is hopelessly lost in a maze of bureaucracy.

7.

Cost. All costs in LSI production are strongly dependent
on production volume. The Masterslice approach allows all
customers to benefit from their combined production volume,
whereas many of the costs of a fully custom design must be
amortized over that single customer's production. Thus,
the real costs of production are lower for Masterslice
designs at any production volume with this difference being
most pronounced for low-volume customers.
-50-

and work-init is possible
schedule to
custom parts,
protect the

A comparison of nonrecurring engineering costs for a typical subsystem
is shown in Fig. 1. For both the standard SSI/MSI design and the Masterslice design, the dominant costs are the in-house labor and overhead
for design, drafting, printed-circuit layout and prototypes, test fixtures, and documentation.
In addition, the Masterslice approach requires
the expenditure of approximately $5,000 for chip layout and prototypes.
For the full custom circuit, however, a huge additional expenditure of
$50,000 is required for chip development plus some additional costs associated with the longer development cycle and the greater difficulty in
monitoring vendor progress.
A comparison of manufacturing costs for these same three systems is
shown in Fig. 2, with the nonrecurring costs amortized over a production
volume of 10,000 units. Note that the fully custom and the Masterslice
design are nearly equal in reproduction costs, but the very large development charge of the fully custom chip is an overwhelming disadvantage.
The SSI/MSI design yields the lowest parts costs, but the assembly, test
and rework, and system-support hardware result in an unattractive total
cost. As labor costs escalate and as environmental constraints on
printed circuits and plastics manufacturers become more severe, we can
expect this system overhead to continue to grow, while yield improvements will allow even more circuitry to be compressed into a single LSI
chip, with even lower costs per gate.
II.

The MasterMOS-M chip

A scale drawing of one of three CMOS Masterslice circuits developed by
International Microcircuits, Inc., called the MasterMOS-M chip, is
shown in Fig. 3. The entire central region of the chip consists of
254 P-channel and 254 N-channel MOS transistors and 322 interconnection
underpasses arranged in a regular array of unit cells.
An enlarged drawing of one of the cells is shown in Fig. 4. The rectangles identified by a diagonal slask mark are contact openings through
the protective silicon oxide to the bare silicon below. All circuit
connections to source, drain, Vdd, Vss, or to underpasses are made by
running a metal line to or across the appropriate contact opening.
The dashed lines on the drawing indicate thin-oxide regions. Note that
all contact openings are enclosed by a thin-oxide region.
This improves
contact hole uniformity and alignment tolerance and reduces unwanted
pinhole contacts, and thus improves circuit yield. Note also several
large areas of thin oxide within the cell. These areas will form the
gate regions for all the N-type and P-type transistors. The P side can
be identified by the narrower channel stop diffusion which is the same
width as the contact hole. The N side has a channel stop diffusion
which is 50% wider than the contact hole. All P-channel transistors are
located on the P side, while all N-channel transistors are located on
the N side. Note that alternate rows of cells are mirror-imaged and
thus the relative location of P side and N side varies from row to row.
Each cell contains two groups of complementary transistors. The first
group contains two N-channel devices and two P-channel devices, while
the second group contains three transistors of each type. Actual

-51-

transistor action takes place in the thin-oxide regions (dashed lines)
of the cell. The source and drain-diffusion areas are the small
irregularly-shaped areas each containing a single contact hole. This
contact opening is used to perform the desired circuit interconnection.
There are fourteen separate source/drain areas in each cell; seven on
the P side and seven on the N side. Note that six of the fourteen
source/drain areas are common to two transistors within the cell. This
greatly simplifies the wiring in performing combinational logic.
The N+ bed surrounding the P-channel devices forms a channel stop for
those devices, while the P+ bed surrounding the N-channel devices forms
a channel stop for those devices.
The region between the N-type and P-type transistors contain eight contact openings to permit circuit connection to Vdd and Vss.
The four
contacts in the N-side channel stop are Vss contacts, and the four
contacts in the P-side channel stop are Vdd contacts.
Because of the
very low quiescent current in CMOS logic, no other wiring is necessary
for Vdd and Vss in the cell area.
The narrow horizontal region between the N+ and the P+ channel stops
is the N- substrate. This region serves to raise the breakdown voltage between the N+ and P+ regions to permit circuit operation with a
higher supply voltage.
The long vertical bars of N+ and P+ serve as underpasses or circuit
cross-overs for signal interconnect wiring.
Contacts are provided at
both ends on all underpasses and at an intermediate point on four of
the seven underpasses.
Up to seven horizontal metal lines can be run
between the end contacts. See the following section for details on
allowable interconnect patterns.
The periphery of the chip contains:
(a)

20 medium-power buffers;

(b)

4 high-current N-channel transistors;

(c)

2 high-current P-channel transistors;

(d)

I

high-impedance N-channel transistor;

(e)

I

high-impedance P-channel transistor;

(f)

28 bonding pads.

The medium-power buffers are suitable for driving low-power TTL or
standard CMOS circuitry. The high-current N-channel devices have adequate drive capability for one standard TTL load.
The high-current
P-channel devices are useful for active pull-up on low-impedance loads.
The high-impedance devices are useful for special applications where
either the input or output current must be very low, but not zero,
during a standby condition, e.g., low-power pUll-up.
The 28 bonding
pads may be assigned arbitrarily by the system designer as Input, Output, Voltage, Intermediate Test Points, or left blank.
Input protection is provided by the underpasses available near each pad.

-52-

Fig. 5 shows two efficient realizations of a simple inverter circuit.
Note that Vss is connected to the source of the N-channel device
through the channel-stop contact and that Vdd is similarly connected.
A simple two-input NOR is illustrated, showing two N-channel devices
in parallel and two P-channel devices in series. A two-input NAND
circuit would be formed by wiring the N-channel devices in series and
the P-channel devices in parallel.
Fig. 6 shows a D-type Master-Slave flip-flop without Set or Reset.
The dashed line shows the interconnect necessary for binary operation.
An important feature of this circuit is the large amount of interconnect area needed when transmission gates and feedback are used in a
cell.
III.

MasterMOS Applications.

Fig. 7 shows a simple consumer product implemented on the small MasterMOS-S chip.
This circuit displaces five packages of standard CMOS plus
twelve discrete components for a size reduction of eight-to-one.
Fig. 8 shows a multiplex circuit implemented on the medium-sized
MasterMOS-M chip which displaces ten standard CMOS chips in a hybrid
application. Wire bonds and package real estate are both reduced by
a factor of ten-to-one.
Fig. 9 shows a communication circuit implemented on the large-sized
MasterMOS-L chip which displaces an entire board containing 32 packages
of standard CMOS logic plus 18 discrete components.
These three typical applications illustrate the broad flexibility of
the Masterslice approach to custom LSI.

-53-

I

I INTERNAL

. . VENDOR

SSI - MSI SYSTEM

MASTERSLICE SYSTEM

FULL
CUSTOM
SYSTEM
DEVELOPMENT COSTS

o

25K

q
50K
DOLLARS IN THOUSANDS

Figure 1. TYPICAL ENGINEERING COSTS

75K

100K

SSI- MSI
SYSTEM

MASTERSLICE
SYSTEM

FULL
CUSTOM
SYSTEM
PRODUCTION COSTS

2

4

q
6

8

10

12

18

16

14

20

DOLLARS

______I COMPONENTS
_ _ _ PCB

.

~~~~I ASM & TEST
~ HARDWARE

Figure 2. TYPICAL PRODUCTION COSTS

-55-

---

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DEVELOPMENT

Figure 3. MASTERMOS CHIP - 60 times actual size

-56-

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-57-

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