EFM32JG1 Reference Manual
EFM32JG1-ReferenceManual
User Manual:
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Page Count: 953 [warning: Documents this large are best viewed by clicking the View PDF Link!]
- 1. About This Document
- 2. System Overview
- 3. System Processor
- 4. Memory and Bus System
- 4.1 Introduction
- 4.2 Functional Description
- 4.3 Access to Low Energy Peripherals (Asynchronous Registers)
- 4.4 Flash
- 4.5 SRAM
- 4.6 DI Page Entry Map
- 4.7 DI Page Entry Description
- 4.7.1 CAL - CRC of DI-page and calibration temperature
- 4.7.2 EUI48L - EUI48 OUI and Unique identifier
- 4.7.3 EUI48H - OUI
- 4.7.4 CUSTOMINFO - Custom information
- 4.7.5 MEMINFO - Flash page size and misc. chip information
- 4.7.6 UNIQUEL - Low 32 bits of device unique number
- 4.7.7 UNIQUEH - High 32 bits of device unique number
- 4.7.8 MSIZE - Flash and SRAM Memory size in kB
- 4.7.9 PART - Part description
- 4.7.10 DEVINFOREV - Device information page revision
- 4.7.11 EMUTEMP - EMU Temperature Calibration Information
- 4.7.12 ADC0CAL0 - ADC0 calibration register 0
- 4.7.13 ADC0CAL1 - ADC0 calibration register 1
- 4.7.14 ADC0CAL2 - ADC0 calibration register 2
- 4.7.15 ADC0CAL3 - ADC0 calibration register 3
- 4.7.16 HFRCOCAL0 - HFRCO Calibration Register (4 MHz)
- 4.7.17 HFRCOCAL3 - HFRCO Calibration Register (7 MHz)
- 4.7.18 HFRCOCAL6 - HFRCO Calibration Register (13 MHz)
- 4.7.19 HFRCOCAL7 - HFRCO Calibration Register (16 MHz)
- 4.7.20 HFRCOCAL8 - HFRCO Calibration Register (19 MHz)
- 4.7.21 HFRCOCAL10 - HFRCO Calibration Register (26 MHz)
- 4.7.22 HFRCOCAL11 - HFRCO Calibration Register (32 MHz)
- 4.7.23 HFRCOCAL12 - HFRCO Calibration Register (38 MHz)
- 4.7.24 AUXHFRCOCAL0 - AUXHFRCO Calibration Register (4 MHz)
- 4.7.25 AUXHFRCOCAL3 - AUXHFRCO Calibration Register (7 MHz)
- 4.7.26 AUXHFRCOCAL6 - AUXHFRCO Calibration Register (13 MHz)
- 4.7.27 AUXHFRCOCAL7 - AUXHFRCO Calibration Register (16 MHz)
- 4.7.28 AUXHFRCOCAL8 - AUXHFRCO Calibration Register (19 MHz)
- 4.7.29 AUXHFRCOCAL10 - AUXHFRCO Calibration Register (26 MHz)
- 4.7.30 AUXHFRCOCAL11 - AUXHFRCO Calibration Register (32 MHz)
- 4.7.31 AUXHFRCOCAL12 - AUXHFRCO Calibration Register (38 MHz)
- 4.7.32 VMONCAL0 - VMON Calibration Register 0
- 4.7.33 VMONCAL1 - VMON Calibration Register 1
- 4.7.34 VMONCAL2 - VMON Calibration Register 2
- 4.7.35 IDAC0CAL0 - IDAC0 Calibration Register 0
- 4.7.36 IDAC0CAL1 - IDAC0 Calibration Register 1
- 4.7.37 DCDCLNVCTRL0 - DCDC Low-noise VREF Trim Register 0
- 4.7.38 DCDCLPVCTRL0 - DCDC Low-power VREF Trim Register 0
- 4.7.39 DCDCLPVCTRL1 - DCDC Low-power VREF Trim Register 1
- 4.7.40 DCDCLPVCTRL2 - DCDC Low-power VREF Trim Register 2
- 4.7.41 DCDCLPVCTRL3 - DCDC Low-power VREF Trim Register 3
- 4.7.42 DCDCLPCMPHYSSEL0 - DCDC LPCMPHYSSEL Trim Register 0
- 4.7.43 DCDCLPCMPHYSSEL1 - DCDC LPCMPHYSSEL Trim Register 1
- 5. DBG - Debug Interface
- 5.1 Introduction
- 5.2 Features
- 5.3 Functional Description
- 5.4 Register Map
- 5.5 Register Description
- 5.5.1 AAP_CMD - Command Register
- 5.5.2 AAP_CMDKEY - Command Key Register
- 5.5.3 AAP_STATUS - Status Register
- 5.5.4 AAP_CTRL - Control Register
- 5.5.5 AAP_CRCCMD - CRC Command Register
- 5.5.6 AAP_CRCSTATUS - CRC Status Register
- 5.5.7 AAP_CRCADDR - CRC Address Register
- 5.5.8 AAP_CRCRESULT - CRC Result Register
- 5.5.9 AAP_IDR - AAP Identification Register
- 6. MSC - Memory System Controller
- 6.1 Introduction
- 6.2 Features
- 6.3 Functional Description
- 6.3.1 User Data (UD) Page Description
- 6.3.2 Lock Bits (LB) Page Description
- 6.3.3 Device Information (DI) Page
- 6.3.4 Bootloader
- 6.3.5 Device Revision
- 6.3.6 Post-reset Behavior
- 6.3.7 Flash Startup
- 6.3.8 Wait-states
- 6.3.9 Suppressed Conditional Branch Target Prefetch (SCBTP)
- 6.3.10 Cortex-M3 If-Then Block Folding
- 6.3.11 Instruction Cache
- 6.3.12 Erase and Write Operations
- 6.4 Register Map
- 6.5 Register Description
- 6.5.1 MSC_CTRL - Memory System Control Register
- 6.5.2 MSC_READCTRL - Read Control Register
- 6.5.3 MSC_WRITECTRL - Write Control Register
- 6.5.4 MSC_WRITECMD - Write Command Register
- 6.5.5 MSC_ADDRB - Page Erase/Write Address Buffer
- 6.5.6 MSC_WDATA - Write Data Register
- 6.5.7 MSC_STATUS - Status Register
- 6.5.8 MSC_IF - Interrupt Flag Register
- 6.5.9 MSC_IFS - Interrupt Flag Set Register
- 6.5.10 MSC_IFC - Interrupt Flag Clear Register
- 6.5.11 MSC_IEN - Interrupt Enable Register
- 6.5.12 MSC_LOCK - Configuration Lock Register
- 6.5.13 MSC_CACHECMD - Flash Cache Command Register
- 6.5.14 MSC_CACHEHITS - Cache Hits Performance Counter
- 6.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter
- 6.5.16 MSC_MASSLOCK - Mass Erase Lock Register
- 6.5.17 MSC_STARTUP - Startup Control
- 6.5.18 MSC_CMD - Command Register
- 7. LDMA - Linked DMA Controller
- 7.1 Introduction
- 7.2 Block Diagram
- 7.3 Functional Description
- 7.4 Examples
- 7.5 Register Map
- 7.6 Register Description
- 7.6.1 LDMA_CTRL - DMA Control Register
- 7.6.2 LDMA_STATUS - DMA Status Register
- 7.6.3 LDMA_SYNC - DMA Synchronization Trigger Register (Single-Cycle RMW)
- 7.6.4 LDMA_CHEN - DMA Channel Enable Register (Single-Cycle RMW)
- 7.6.5 LDMA_CHBUSY - DMA Channel Busy Register
- 7.6.6 LDMA_CHDONE - DMA Channel Linking Done Register (Single-Cycle RMW)
- 7.6.7 LDMA_DBGHALT - DMA Channel Debug Halt Register
- 7.6.8 LDMA_SWREQ - DMA Channel Software Transfer Request Register
- 7.6.9 LDMA_REQDIS - DMA Channel Request Disable Register
- 7.6.10 LDMA_REQPEND - DMA Channel Requests Pending Register
- 7.6.11 LDMA_LINKLOAD - DMA Channel Link Load Register
- 7.6.12 LDMA_REQCLEAR - DMA Channel Request Clear Register
- 7.6.13 LDMA_IF - Interrupt Flag Register
- 7.6.14 LDMA_IFS - Interrupt Flag Set Register
- 7.6.15 LDMA_IFC - Interrupt Flag Clear Register
- 7.6.16 LDMA_IEN - Interrupt Enable register
- 7.6.17 LDMA_CHx_REQSEL - Channel Peripheral Request Select Register
- 7.6.18 LDMA_CHx_CFG - Channel Configuration Register
- 7.6.19 LDMA_CHx_LOOP - Channel Loop Counter Register
- 7.6.20 LDMA_CHx_CTRL - Channel Descriptor Control Word Register
- 7.6.21 LDMA_CHx_SRC - Channel Descriptor Source Data Address Register
- 7.6.22 LDMA_CHx_DST - Channel Descriptor Destination Data Address Register
- 7.6.23 LDMA_CHx_LINK - Channel Descriptor Link Structure Address Register
- 8. RMU - Reset Management Unit
- 9. EMU - Energy Management Unit
- 9.1 Introduction
- 9.2 Features
- 9.3 Functional Description
- 9.3.1 Energy Modes
- 9.3.2 Entering Low Energy Modes
- 9.3.3 Exiting a Low Energy Mode
- 9.3.4 Power Configurations
- 9.3.5 DC-to-DC Interface
- 9.3.6 Brown Out Detector (BOD)
- 9.3.7 Voltage Monitor (VMON)
- 9.3.8 Powering off SRAM blocks
- 9.3.9 Temperature Sensor Status
- 9.3.10 Registers latched in EM4
- 9.3.11 Register Resets
- 9.4 Register Map
- 9.5 Register Description
- 9.5.1 EMU_CTRL - Control Register
- 9.5.2 EMU_STATUS - Status Register
- 9.5.3 EMU_LOCK - Configuration Lock Register
- 9.5.4 EMU_RAM0CTRL - Memory Control Register
- 9.5.5 EMU_CMD - Command Register
- 9.5.6 EMU_EM4CTRL - EM4 Control Register
- 9.5.7 EMU_TEMPLIMITS - Temperature limits for interrupt generation
- 9.5.8 EMU_TEMP - Value of last temperature measurement
- 9.5.9 EMU_IF - Interrupt Flag Register
- 9.5.10 EMU_IFS - Interrupt Flag Set Register
- 9.5.11 EMU_IFC - Interrupt Flag Clear Register
- 9.5.12 EMU_IEN - Interrupt Enable Register
- 9.5.13 EMU_PWRLOCK - Regulator and Supply Lock Register
- 9.5.14 EMU_PWRCFG - Power Configuration Register. This is no longer used
- 9.5.15 EMU_PWRCTRL - Power Control Register.
- 9.5.16 EMU_DCDCCTRL - DCDC Control
- 9.5.17 EMU_DCDCMISCCTRL - DCDC Miscellaneous Control Register
- 9.5.18 EMU_DCDCZDETCTRL - DCDC Power Train NFET Zero Current Detector Control Register
- 9.5.19 EMU_DCDCCLIMCTRL - DCDC Power Train PFET Current Limiter Control Register
- 9.5.20 EMU_DCDCLNVCTRL - DCDC Low Noise Voltage Register
- 9.5.21 EMU_DCDCTIMING - DCDC Controller Timing Value Register
- 9.5.22 EMU_DCDCLPVCTRL - DCDC Low Power Voltage Register
- 9.5.23 EMU_DCDCLPCTRL - DCDC Low Power Control Register
- 9.5.24 EMU_DCDCLNFREQCTRL - DCDC Low Noise Controller Frequency Control
- 9.5.25 EMU_DCDCSYNC - DCDC Read Status Register
- 9.5.26 EMU_VMONAVDDCTRL - VMON AVDD Channel Control
- 9.5.27 EMU_VMONALTAVDDCTRL - Alternate VMON AVDD Channel Control
- 9.5.28 EMU_VMONDVDDCTRL - VMON DVDD Channel Control
- 9.5.29 EMU_VMONIO0CTRL - VMON IOVDD0 Channel Control
- 10. CMU - Clock Management Unit
- 10.1 Introduction
- 10.2 Features
- 10.3 Functional Description
- 10.3.1 System Clocks
- 10.3.1.1 HFCLK - High Frequency Clock
- 10.3.1.2 HFCORECLK - High Frequency Core Clock
- 10.3.1.3 HFBUSCLK - High Frequency Bus Clock
- 10.3.1.4 HFPERCLK - High Frequency Peripheral Clock
- 10.3.1.5 LFACLK - Low Frequency A Clock
- 10.3.1.6 LFBCLK - Low Frequency B Clock
- 10.3.1.7 LFECLK - Low Frequency E Clock
- 10.3.1.8 PCNTnCLK - Pulse Counter n Clock
- 10.3.1.9 WDOGCLK - Watchdog Timer Clock
- 10.3.1.10 CRYOCLK - Cryotimer Clock
- 10.3.1.11 AUXCLK - Auxiliary Clock
- 10.3.1.12 Debug Trace Clock
- 10.3.2 Oscillators
- 10.3.3 Configuration For Operating Frequencies
- 10.3.4 Energy Modes
- 10.3.5 Clock Output on a Pin
- 10.3.6 Clock Input from a Pin
- 10.3.7 Clock Output on PRS
- 10.3.8 Error Handling
- 10.3.9 Interrupts
- 10.3.10 Wake-up
- 10.3.11 Protection
- 10.3.1 System Clocks
- 10.4 Register Map
- 10.5 Register Description
- 10.5.1 CMU_CTRL - CMU Control Register
- 10.5.2 CMU_HFRCOCTRL - HFRCO Control Register
- 10.5.3 CMU_AUXHFRCOCTRL - AUXHFRCO Control Register
- 10.5.4 CMU_LFRCOCTRL - LFRCO Control Register
- 10.5.5 CMU_HFXOCTRL - HFXO Control Register
- 10.5.6 CMU_HFXOCTRL1 - HFXO Control 1
- 10.5.7 CMU_HFXOSTARTUPCTRL - HFXO Startup Control
- 10.5.8 CMU_HFXOSTEADYSTATECTRL - HFXO Steady State control
- 10.5.9 CMU_HFXOTIMEOUTCTRL - HFXO Timeout Control
- 10.5.10 CMU_LFXOCTRL - LFXO Control Register
- 10.5.11 CMU_CALCTRL - Calibration Control Register
- 10.5.12 CMU_CALCNT - Calibration Counter Register
- 10.5.13 CMU_OSCENCMD - Oscillator Enable/Disable Command Register
- 10.5.14 CMU_CMD - Command Register
- 10.5.15 CMU_DBGCLKSEL - Debug Trace Clock Select
- 10.5.16 CMU_HFCLKSEL - High Frequency Clock Select Command Register
- 10.5.17 CMU_LFACLKSEL - Low Frequency A Clock Select Register
- 10.5.18 CMU_LFBCLKSEL - Low Frequency B Clock Select Register
- 10.5.19 CMU_LFECLKSEL - Low Frequency E Clock Select Register
- 10.5.20 CMU_STATUS - Status Register
- 10.5.21 CMU_HFCLKSTATUS - HFCLK Status Register
- 10.5.22 CMU_HFXOTRIMSTATUS - HFXO Trim Status
- 10.5.23 CMU_IF - Interrupt Flag Register
- 10.5.24 CMU_IFS - Interrupt Flag Set Register
- 10.5.25 CMU_IFC - Interrupt Flag Clear Register
- 10.5.26 CMU_IEN - Interrupt Enable Register
- 10.5.27 CMU_HFBUSCLKEN0 - High Frequency Bus Clock Enable Register 0
- 10.5.28 CMU_HFPERCLKEN0 - High Frequency Peripheral Clock Enable Register 0
- 10.5.29 CMU_LFACLKEN0 - Low Frequency A Clock Enable Register 0 (Async Reg)
- 10.5.30 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0 (Async Reg)
- 10.5.31 CMU_LFECLKEN0 - Low Frequency E Clock Enable Register 0 (Async Reg)
- 10.5.32 CMU_HFPRESC - High Frequency Clock Prescaler Register
- 10.5.33 CMU_HFCOREPRESC - High Frequency Core Clock Prescaler Register
- 10.5.34 CMU_HFPERPRESC - High Frequency Peripheral Clock Prescaler Register
- 10.5.35 CMU_HFEXPPRESC - High Frequency Export Clock Prescaler Register
- 10.5.36 CMU_LFAPRESC0 - Low Frequency A Prescaler Register 0 (Async Reg)
- 10.5.37 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg)
- 10.5.38 CMU_LFEPRESC0 - Low Frequency E Prescaler Register 0 (Async Reg). When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect
- 10.5.39 CMU_SYNCBUSY - Synchronization Busy Register
- 10.5.40 CMU_FREEZE - Freeze Register
- 10.5.41 CMU_PCNTCTRL - PCNT Control Register
- 10.5.42 CMU_ADCCTRL - ADC Control Register
- 10.5.43 CMU_ROUTEPEN - I/O Routing Pin Enable Register
- 10.5.44 CMU_ROUTELOC0 - I/O Routing Location Register
- 10.5.45 CMU_LOCK - Configuration Lock Register
- 11. RTCC - Real Time Counter and Calendar
- 11.1 Introduction
- 11.2 Features
- 11.3 Functional Description
- 11.4 Register Map
- 11.5 Register Description
- 11.5.1 RTCC_CTRL - Control Register (Async Reg)
- 11.5.2 RTCC_PRECNT - Pre-Counter Value Register (Async Reg)
- 11.5.3 RTCC_CNT - Counter Value Register (Async Reg)
- 11.5.4 RTCC_COMBCNT - Combined Pre-Counter and Counter Value Register
- 11.5.5 RTCC_TIME - Time of day register (Async Reg)
- 11.5.6 RTCC_DATE - Date register (Async Reg)
- 11.5.7 RTCC_IF - RTCC Interrupt Flags
- 11.5.8 RTCC_IFS - Interrupt Flag Set Register
- 11.5.9 RTCC_IFC - Interrupt Flag Clear Register
- 11.5.10 RTCC_IEN - Interrupt Enable Register
- 11.5.11 RTCC_STATUS - Status register
- 11.5.12 RTCC_CMD - Command Register
- 11.5.13 RTCC_SYNCBUSY - Synchronization Busy Register
- 11.5.14 RTCC_POWERDOWN - Retention RAM power-down register (Async Reg)
- 11.5.15 RTCC_LOCK - Configuration Lock Register (Async Reg)
- 11.5.16 RTCC_EM4WUEN - Wake Up Enable
- 11.5.17 RTCC_CCx_CTRL - CC Channel Control Register (Async Reg)
- 11.5.18 RTCC_CCx_CCV - Capture/Compare Value Register (Async Reg)
- 11.5.19 RTCC_CCx_TIME - Capture/Compare Time Register (Async Reg)
- 11.5.20 RTCC_CCx_DATE - Capture/Compare Date Register (Async Reg)
- 11.5.21 RTCC_RETx_REG - Retention register
- 12. WDOG - Watchdog Timer
- 12.1 Introduction
- 12.2 Features
- 12.3 Functional Description
- 12.4 Register Map
- 12.5 Register Description
- 12.5.1 WDOG_CTRL - Control Register (Async Reg)
- 12.5.2 WDOG_CMD - Command Register (Async Reg)
- 12.5.3 WDOG_SYNCBUSY - Synchronization Busy Register
- 12.5.4 WDOGn_PCHx_PRSCTRL - PRS Control Register (Async Reg)
- 12.5.5 WDOG_IF - Watchdog Interrupt Flags
- 12.5.6 WDOG_IFS - Interrupt Flag Set Register
- 12.5.7 WDOG_IFC - Interrupt Flag Clear Register
- 12.5.8 WDOG_IEN - Interrupt Enable Register
- 13. PRS - Peripheral Reflex System
- 13.1 Introduction
- 13.2 Features
- 13.3 Functional Description
- 13.4 Register Map
- 13.5 Register Description
- 13.5.1 PRS_SWPULSE - Software Pulse Register
- 13.5.2 PRS_SWLEVEL - Software Level Register
- 13.5.3 PRS_ROUTEPEN - I/O Routing Pin Enable Register
- 13.5.4 PRS_ROUTELOC0 - I/O Routing Location Register
- 13.5.5 PRS_ROUTELOC1 - I/O Routing Location Register
- 13.5.6 PRS_ROUTELOC2 - I/O Routing Location Register
- 13.5.7 PRS_CTRL - Control Register
- 13.5.8 PRS_DMAREQ0 - DMA Request 0 Register
- 13.5.9 PRS_DMAREQ1 - DMA Request 1 Register
- 13.5.10 PRS_PEEK - PRS Channel Values
- 13.5.11 PRS_CHx_CTRL - Channel Control Register
- 14. PCNT - Pulse Counter
- 14.1 Introduction
- 14.2 Features
- 14.3 Functional Description
- 14.4 Register Map
- 14.5 Register Description
- 14.5.1 PCNTn_CTRL - Control Register (Async Reg)
- 14.5.2 PCNTn_CMD - Command Register (Async Reg)
- 14.5.3 PCNTn_STATUS - Status Register
- 14.5.4 PCNTn_CNT - Counter Value Register
- 14.5.5 PCNTn_TOP - Top Value Register
- 14.5.6 PCNTn_TOPB - Top Value Buffer Register (Async Reg)
- 14.5.7 PCNTn_IF - Interrupt Flag Register
- 14.5.8 PCNTn_IFS - Interrupt Flag Set Register
- 14.5.9 PCNTn_IFC - Interrupt Flag Clear Register
- 14.5.10 PCNTn_IEN - Interrupt Enable Register
- 14.5.11 PCNTn_ROUTELOC0 - I/O Routing Location Register
- 14.5.12 PCNTn_FREEZE - Freeze Register
- 14.5.13 PCNTn_SYNCBUSY - Synchronization Busy Register
- 14.5.14 PCNTn_AUXCNT - Auxiliary Counter Value Register
- 14.5.15 PCNTn_INPUT - PCNT Input Register
- 14.5.16 PCNTn_OVSCFG - Oversampling Config Register (Async Reg)
- 15. I2C - Inter-Integrated Circuit Interface
- 15.1 Introduction
- 15.2 Features
- 15.3 Functional Description
- 15.3.1 I2C-Bus Overview
- 15.3.2 Enable and Reset
- 15.3.3 Safely Disabling and Changing Slave Configuration
- 15.3.4 Clock Generation
- 15.3.5 Arbitration
- 15.3.6 Buffers
- 15.3.7 Master Operation
- 15.3.8 Bus States
- 15.3.9 Slave Operation
- 15.3.10 Transfer Automation
- 15.3.11 Using 10-bit Addresses
- 15.3.12 Error Handling
- 15.3.13 DMA Support
- 15.3.14 Interrupts
- 15.3.15 Wake-up
- 15.4 Register Map
- 15.5 Register Description
- 15.5.1 I2Cn_CTRL - Control Register
- 15.5.2 I2Cn_CMD - Command Register
- 15.5.3 I2Cn_STATE - State Register
- 15.5.4 I2Cn_STATUS - Status Register
- 15.5.5 I2Cn_CLKDIV - Clock Division Register
- 15.5.6 I2Cn_SADDR - Slave Address Register
- 15.5.7 I2Cn_SADDRMASK - Slave Address Mask Register
- 15.5.8 I2Cn_RXDATA - Receive Buffer Data Register (Actionable Reads)
- 15.5.9 I2Cn_RXDOUBLE - Receive Buffer Double Data Register (Actionable Reads)
- 15.5.10 I2Cn_RXDATAP - Receive Buffer Data Peek Register
- 15.5.11 I2Cn_RXDOUBLEP - Receive Buffer Double Data Peek Register
- 15.5.12 I2Cn_TXDATA - Transmit Buffer Data Register
- 15.5.13 I2Cn_TXDOUBLE - Transmit Buffer Double Data Register
- 15.5.14 I2Cn_IF - Interrupt Flag Register
- 15.5.15 I2Cn_IFS - Interrupt Flag Set Register
- 15.5.16 I2Cn_IFC - Interrupt Flag Clear Register
- 15.5.17 I2Cn_IEN - Interrupt Enable Register
- 15.5.18 I2Cn_ROUTEPEN - I/O Routing Pin Enable Register
- 15.5.19 I2Cn_ROUTELOC0 - I/O Routing Location Register
- 16. USART - Universal Synchronous Asynchronous Receiver/Transmitter
- 16.1 Introduction
- 16.2 Features
- 16.3 Functional Description
- 16.3.1 Modes of Operation
- 16.3.2 Asynchronous Operation
- 16.3.2.1 Frame Format
- 16.3.2.2 Parity bit Calculation and Handling
- 16.3.2.3 Clock Generation
- 16.3.2.4 Auto Baud Detection
- 16.3.2.5 Data Transmission
- 16.3.2.6 Transmit Buffer Operation
- 16.3.2.7 Frame Transmission Control
- 16.3.2.8 Data Reception
- 16.3.2.9 Receive Buffer Operation
- 16.3.2.10 Blocking Incoming Data
- 16.3.2.11 Clock Recovery and Filtering
- 16.3.2.12 Parity Error
- 16.3.2.13 Framing Error and Break Detection
- 16.3.2.14 Local Loopback
- 16.3.2.15 Asynchronous Half Duplex Communication
- 16.3.2.16 Single Data-link
- 16.3.2.17 Single Data-link with External Driver
- 16.3.2.18 Two Data-links
- 16.3.2.19 Large Frames
- 16.3.2.20 Multi-Processor Mode
- 16.3.2.21 Collision Detection
- 16.3.2.22 SmartCard Mode
- 16.3.3 Synchronous Operation
- 16.3.4 Hardware Flow Control
- 16.3.5 Debug Halt
- 16.3.6 PRS-triggered Transmissions
- 16.3.7 PRS RX Input
- 16.3.8 PRS CLK Input
- 16.3.9 DMA Support
- 16.3.10 Timer
- 16.3.11 Interrupts
- 16.3.12 IrDA Modulator/ Demodulator
- 16.4 Register Map
- 16.5 Register Description
- 16.5.1 USARTn_CTRL - Control Register
- 16.5.2 USARTn_FRAME - USART Frame Format Register
- 16.5.3 USARTn_TRIGCTRL - USART Trigger Control register
- 16.5.4 USARTn_CMD - Command Register
- 16.5.5 USARTn_STATUS - USART Status Register
- 16.5.6 USARTn_CLKDIV - Clock Control Register
- 16.5.7 USARTn_RXDATAX - RX Buffer Data Extended Register (Actionable Reads)
- 16.5.8 USARTn_RXDATA - RX Buffer Data Register (Actionable Reads)
- 16.5.9 USARTn_RXDOUBLEX - RX Buffer Double Data Extended Register (Actionable Reads)
- 16.5.10 USARTn_RXDOUBLE - RX FIFO Double Data Register (Actionable Reads)
- 16.5.11 USARTn_RXDATAXP - RX Buffer Data Extended Peek Register
- 16.5.12 USARTn_RXDOUBLEXP - RX Buffer Double Data Extended Peek Register
- 16.5.13 USARTn_TXDATAX - TX Buffer Data Extended Register
- 16.5.14 USARTn_TXDATA - TX Buffer Data Register
- 16.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register
- 16.5.16 USARTn_TXDOUBLE - TX Buffer Double Data Register
- 16.5.17 USARTn_IF - Interrupt Flag Register
- 16.5.18 USARTn_IFS - Interrupt Flag Set Register
- 16.5.19 USARTn_IFC - Interrupt Flag Clear Register
- 16.5.20 USARTn_IEN - Interrupt Enable Register
- 16.5.21 USARTn_IRCTRL - IrDA Control Register
- 16.5.22 USARTn_INPUT - USART Input Register
- 16.5.23 USARTn_I2SCTRL - I2S Control Register
- 16.5.24 USARTn_TIMING - Timing Register
- 16.5.25 USARTn_CTRLX - Control Register Extended
- 16.5.26 USARTn_TIMECMP0 - Used to generate interrupts and various delays
- 16.5.27 USARTn_TIMECMP1 - Used to generate interrupts and various delays
- 16.5.28 USARTn_TIMECMP2 - Used to generate interrupts and various delays
- 16.5.29 USARTn_ROUTEPEN - I/O Routing Pin Enable Register
- 16.5.30 USARTn_ROUTELOC0 - I/O Routing Location Register
- 16.5.31 USARTn_ROUTELOC1 - I/O Routing Location Register
- 17. LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
- 17.1 Introduction
- 17.2 Features
- 17.3 Functional Description
- 17.4 Register Map
- 17.5 Register Description
- 17.5.1 LEUARTn_CTRL - Control Register (Async Reg)
- 17.5.2 LEUARTn_CMD - Command Register (Async Reg)
- 17.5.3 LEUARTn_STATUS - Status Register
- 17.5.4 LEUARTn_CLKDIV - Clock Control Register (Async Reg)
- 17.5.5 LEUARTn_STARTFRAME - Start Frame Register (Async Reg)
- 17.5.6 LEUARTn_SIGFRAME - Signal Frame Register (Async Reg)
- 17.5.7 LEUARTn_RXDATAX - Receive Buffer Data Extended Register (Actionable Reads)
- 17.5.8 LEUARTn_RXDATA - Receive Buffer Data Register (Actionable Reads)
- 17.5.9 LEUARTn_RXDATAXP - Receive Buffer Data Extended Peek Register
- 17.5.10 LEUARTn_TXDATAX - Transmit Buffer Data Extended Register (Async Reg)
- 17.5.11 LEUARTn_TXDATA - Transmit Buffer Data Register (Async Reg)
- 17.5.12 LEUARTn_IF - Interrupt Flag Register
- 17.5.13 LEUARTn_IFS - Interrupt Flag Set Register
- 17.5.14 LEUARTn_IFC - Interrupt Flag Clear Register
- 17.5.15 LEUARTn_IEN - Interrupt Enable Register
- 17.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg)
- 17.5.17 LEUARTn_FREEZE - Freeze Register
- 17.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register
- 17.5.19 LEUARTn_ROUTEPEN - I/O Routing Pin Enable Register
- 17.5.20 LEUARTn_ROUTELOC0 - I/O Routing Location Register
- 17.5.21 LEUARTn_INPUT - LEUART Input Register
- 18. TIMER - Timer/Counter
- 18.1 Introduction
- 18.2 Features
- 18.3 Functional Description
- 18.3.1 Counter Modes
- 18.3.1.1 Events
- 18.3.1.2 Operation
- 18.3.1.3 Clock Source
- 18.3.1.4 Peripheral Clock (HFPERCLK)
- 18.3.1.5 Compare/ Capture Channel 1 Input
- 18.3.1.6 Underflow/Overflow from Neighboring Timer
- 18.3.1.7 One-Shot Mode
- 18.3.1.8 Top Value Buffer
- 18.3.1.9 Quadrature Decoder
- 18.3.1.10 X2 Decoding Mode
- 18.3.1.11 X4 Decoding Mode
- 18.3.1.12 TIMER Rotational Position
- 18.3.2 Compare/Capture Channels
- 18.3.2.1 Input Pin Logic
- 18.3.2.2 Compare/Capture Registers
- 18.3.2.3 Input Capture
- 18.3.2.4 Period/Pulse-Width Capture
- 18.3.2.5 Compare
- 18.3.2.6 Compare Mode Registers
- 18.3.2.7 Frequency Generation (FRG)
- 18.3.2.8 Pulse-Width Modulation (PWM)
- 18.3.2.9 Up-count (Single-slope) PWM
- 18.3.2.10 2x Count Mode
- 18.3.2.11 Up/Down-count (Dual-slope) PWM
- 18.3.2.12 2x Count Mode
- 18.3.2.13 Timer Configuration Lock
- 18.3.3 Dead-Time Insertion Unit (TIMER0 only)
- 18.3.4 Debug Mode
- 18.3.5 Interrupts, DMA and PRS Output
- 18.3.6 GPIO Input/Output
- 18.3.1 Counter Modes
- 18.4 Register Map
- 18.5 Register Description
- 18.5.1 TIMERn_CTRL - Control Register
- 18.5.2 TIMERn_CMD - Command Register
- 18.5.3 TIMERn_STATUS - Status Register
- 18.5.4 TIMERn_IF - Interrupt Flag Register
- 18.5.5 TIMERn_IFS - Interrupt Flag Set Register
- 18.5.6 TIMERn_IFC - Interrupt Flag Clear Register
- 18.5.7 TIMERn_IEN - Interrupt Enable Register
- 18.5.8 TIMERn_TOP - Counter Top Value Register
- 18.5.9 TIMERn_TOPB - Counter Top Value Buffer Register
- 18.5.10 TIMERn_CNT - Counter Value Register
- 18.5.11 TIMERn_LOCK - TIMER Configuration Lock Register
- 18.5.12 TIMERn_ROUTEPEN - I/O Routing Pin Enable Register
- 18.5.13 TIMERn_ROUTELOC0 - I/O Routing Location Register
- 18.5.14 TIMERn_ROUTELOC2 - I/O Routing Location Register
- 18.5.15 TIMERn_CCx_CTRL - CC Channel Control Register
- 18.5.16 TIMERn_CCx_CCV - CC Channel Value Register (Actionable Reads)
- 18.5.17 TIMERn_CCx_CCVP - CC Channel Value Peek Register
- 18.5.18 TIMERn_CCx_CCVB - CC Channel Buffer Register
- 18.5.19 TIMERn_DTCTRL - DTI Control Register
- 18.5.20 TIMERn_DTTIME - DTI Time Control Register
- 18.5.21 TIMERn_DTFC - DTI Fault Configuration Register
- 18.5.22 TIMERn_DTOGEN - DTI Output Generation Enable Register
- 18.5.23 TIMERn_DTFAULT - DTI Fault Register
- 18.5.24 TIMERn_DTFAULTC - DTI Fault Clear Register
- 18.5.25 TIMERn_DTLOCK - DTI Configuration Lock Register
- 19. LETIMER - Low Energy Timer
- 19.1 Introduction
- 19.2 Features
- 19.3 Functional Description
- 19.4 Register Map
- 19.5 Register Description
- 19.5.1 LETIMERn_CTRL - Control Register (Async Reg)
- 19.5.2 LETIMERn_CMD - Command Register
- 19.5.3 LETIMERn_STATUS - Status Register
- 19.5.4 LETIMERn_CNT - Counter Value Register
- 19.5.5 LETIMERn_COMP0 - Compare Value Register 0 (Async Reg)
- 19.5.6 LETIMERn_COMP1 - Compare Value Register 1 (Async Reg)
- 19.5.7 LETIMERn_REP0 - Repeat Counter Register 0 (Async Reg)
- 19.5.8 LETIMERn_REP1 - Repeat Counter Register 1 (Async Reg)
- 19.5.9 LETIMERn_IF - Interrupt Flag Register
- 19.5.10 LETIMERn_IFS - Interrupt Flag Set Register
- 19.5.11 LETIMERn_IFC - Interrupt Flag Clear Register
- 19.5.12 LETIMERn_IEN - Interrupt Enable Register
- 19.5.13 LETIMERn_SYNCBUSY - Synchronization Busy Register
- 19.5.14 LETIMERn_ROUTEPEN - I/O Routing Pin Enable Register
- 19.5.15 LETIMERn_ROUTELOC0 - I/O Routing Location Register
- 19.5.16 LETIMERn_PRSSEL - PRS Input Select Register
- 20. CRYOTIMER - Ultra Low Energy Timer/Counter
- 20.1 Introduction
- 20.2 Features
- 20.3 Functional Description
- 20.4 Register Map
- 20.5 Register Description
- 20.5.1 CRYOTIMER_CTRL - Control Register
- 20.5.2 CRYOTIMER_PERIODSEL - Interrupt Duration
- 20.5.3 CRYOTIMER_CNT - Counter Value
- 20.5.4 CRYOTIMER_EM4WUEN - Wake Up Enable
- 20.5.5 CRYOTIMER_IF - Interrupt Flag Register
- 20.5.6 CRYOTIMER_IFS - Interrupt Flag Set Register
- 20.5.7 CRYOTIMER_IFC - Interrupt Flag Clear Register
- 20.5.8 CRYOTIMER_IEN - Interrupt Enable Register
- 21. ACMP - Analog Comparator
- 21.1 Introduction
- 21.2 Features
- 21.3 Functional Description
- 21.4 Register Map
- 21.5 Register Description
- 21.5.1 ACMPn_CTRL - Control Register
- 21.5.2 ACMPn_INPUTSEL - Input Selection Register
- 21.5.3 ACMPn_STATUS - Status Register
- 21.5.4 ACMPn_IF - Interrupt Flag Register
- 21.5.5 ACMPn_IFS - Interrupt Flag Set Register
- 21.5.6 ACMPn_IFC - Interrupt Flag Clear Register
- 21.5.7 ACMPn_IEN - Interrupt Enable Register
- 21.5.8 ACMPn_APORTREQ - APORT Request Status Register
- 21.5.9 ACMPn_APORTCONFLICT - APORT Conflict Status Register
- 21.5.10 ACMPn_HYSTERESIS0 - Hysteresis 0 Register
- 21.5.11 ACMPn_HYSTERESIS1 - Hysteresis 1 Register
- 21.5.12 ACMPn_ROUTEPEN - I/O Routing Pine Enable Register
- 21.5.13 ACMPn_ROUTELOC0 - I/O Routing Location Register
- 22. ADC - Analog to Digital Converter
- 22.1 Introduction
- 22.2 Features
- 22.3 Functional Description
- 22.3.1 Clock Selection
- 22.3.2 Conversions
- 22.3.3 ADC Modes
- 22.3.4 Warm-up Time
- 22.3.5 Input Selection
- 22.3.6 Reference Selection and Input Range Definition
- 22.3.7 Programming of Bias Current
- 22.3.8 Feature Set
- 22.3.9 Interrupts, PRS Output
- 22.3.10 DMA Request
- 22.3.11 Calibration
- 22.3.12 EM2 or EM3 Operation
- 22.3.13 ASYNC ADC_CLK Usage Restrictions and Benefits
- 22.3.14 Window Compare Function
- 22.3.15 ADC Programming Model
- 22.4 Register Map
- 22.5 Register Description
- 22.5.1 ADCn_CTRL - Control Register
- 22.5.2 ADCn_CMD - Command Register
- 22.5.3 ADCn_STATUS - Status Register
- 22.5.4 ADCn_SINGLECTRL - Single Channel Control Register
- 22.5.5 ADCn_SINGLECTRLX - Single Channel Control Register continued
- 22.5.6 ADCn_SCANCTRL - Scan Control Register
- 22.5.7 ADCn_SCANCTRLX - Scan Control Register continued
- 22.5.8 ADCn_SCANMASK - Scan Sequence Input Mask Register
- 22.5.9 ADCn_SCANINPUTSEL - Input Selection register for Scan mode
- 22.5.10 ADCn_SCANNEGSEL - Negative Input select register for Scan
- 22.5.11 ADCn_CMPTHR - Compare Threshold Register
- 22.5.12 ADCn_BIASPROG - Bias Programming Register for various analog blocks used in ADC operation.
- 22.5.13 ADCn_CAL - Calibration Register
- 22.5.14 ADCn_IF - Interrupt Flag Register
- 22.5.15 ADCn_IFS - Interrupt Flag Set Register
- 22.5.16 ADCn_IFC - Interrupt Flag Clear Register
- 22.5.17 ADCn_IEN - Interrupt Enable Register
- 22.5.18 ADCn_SINGLEDATA - Single Conversion Result Data (Actionable Reads)
- 22.5.19 ADCn_SCANDATA - Scan Conversion Result Data (Actionable Reads)
- 22.5.20 ADCn_SINGLEDATAP - Single Conversion Result Data Peek Register
- 22.5.21 ADCn_SCANDATAP - Scan Sequence Result Data Peek Register
- 22.5.22 ADCn_SCANDATAX - Scan Sequence Result Data + Data Source Register (Actionable Reads)
- 22.5.23 ADCn_SCANDATAXP - Scan Sequence Result Data + Data Source Peek Register
- 22.5.24 ADCn_APORTREQ - APORT Request Status Register
- 22.5.25 ADCn_APORTCONFLICT - APORT Conflict Status Register
- 22.5.26 ADCn_SINGLEFIFOCOUNT - Single FIFO Count Register
- 22.5.27 ADCn_SCANFIFOCOUNT - Scan FIFO Count Register
- 22.5.28 ADCn_SINGLEFIFOCLEAR - Single FIFO Clear Register
- 22.5.29 ADCn_SCANFIFOCLEAR - Scan FIFO Clear Register
- 22.5.30 ADCn_APORTMASTERDIS - APORT Bus Master Disable Register
- 23. IDAC - Current Digital to Analog Converter
- 23.1 Introduction
- 23.2 Features
- 23.3 Functional Description
- 23.4 Register Map
- 23.5 Register Description
- 23.5.1 IDAC_CTRL - Control Register
- 23.5.2 IDAC_CURPROG - Current Programming Register
- 23.5.3 IDAC_DUTYCONFIG - Duty Cycle Configauration Register
- 23.5.4 IDAC_STATUS - Status Register
- 23.5.5 IDAC_IF - Interrupt Flag Register
- 23.5.6 IDAC_IFS - Interrupt Flag Set Register
- 23.5.7 IDAC_IFC - Interrupt Flag Clear Register
- 23.5.8 IDAC_IEN - Interrupt Enable Register
- 23.5.9 IDAC_APORTREQ - APORT Request Status Register
- 23.5.10 IDAC_APORTCONFLICT - APORT Request Status Register
- 24. GPCRC - General Purpose Cyclic Redundancy Check
- 24.1 Introduction
- 24.2 Features
- 24.3 Functional Description
- 24.4 Register Map
- 24.5 Register Description
- 24.5.1 GPCRC_CTRL - Control Register
- 24.5.2 GPCRC_CMD - Command Register
- 24.5.3 GPCRC_INIT - CRC Init Value
- 24.5.4 GPCRC_POLY - CRC Polynomial Value
- 24.5.5 GPCRC_INPUTDATA - Input 32-bit Data Register
- 24.5.6 GPCRC_INPUTDATAHWORD - Input 16-bit Data Register
- 24.5.7 GPCRC_INPUTDATABYTE - Input 8-bit Data Register
- 24.5.8 GPCRC_DATA - CRC Data Register
- 24.5.9 GPCRC_DATAREV - CRC Data Reverse Register
- 24.5.10 GPCRC_DATABYTEREV - CRC Data Byte Reverse Register
- 25. CRYPTO - Crypto Accelerator
- 25.1 Introduction
- 25.2 Features
- 25.3 Usage and Programming Interface
- 25.4 Functional Description
- 25.5 Register Map
- 25.6 Register Description
- 25.6.1 CRYPTO_CTRL - Control Register
- 25.6.2 CRYPTO_WAC - Wide Arithmetic Configuration
- 25.6.3 CRYPTO_CMD - Command Register
- 25.6.4 CRYPTO_STATUS - Status Register
- 25.6.5 CRYPTO_DSTATUS - Data Status Register
- 25.6.6 CRYPTO_CSTATUS - Control Status Register
- 25.6.7 CRYPTO_KEY - KEY Register Access (No Bit Access) (Actionable Reads)
- 25.6.8 CRYPTO_KEYBUF - KEY Buffer Register Access (No Bit Access) (Actionable Reads)
- 25.6.9 CRYPTO_SEQCTRL - Sequence Control
- 25.6.10 CRYPTO_SEQCTRLB - Sequence Control B
- 25.6.11 CRYPTO_IF - AES Interrupt Flags
- 25.6.12 CRYPTO_IFS - Interrupt Flag Set Register
- 25.6.13 CRYPTO_IFC - Interrupt Flag Clear Register
- 25.6.14 CRYPTO_IEN - Interrupt Enable Register
- 25.6.15 CRYPTO_SEQ0 - Sequence register 0
- 25.6.16 CRYPTO_SEQ1 - Sequence Register 1
- 25.6.17 CRYPTO_SEQ2 - Sequence Register 2
- 25.6.18 CRYPTO_SEQ3 - Sequence Register 3
- 25.6.19 CRYPTO_SEQ4 - Sequence Register 4
- 25.6.20 CRYPTO_DATA0 - DATA0 Register Access (No Bit Access) (Actionable Reads)
- 25.6.21 CRYPTO_DATA1 - DATA1 Register Access (No Bit Access) (Actionable Reads)
- 25.6.22 CRYPTO_DATA2 - DATA2 Register Access (No Bit Access) (Actionable Reads)
- 25.6.23 CRYPTO_DATA3 - DATA3 Register Access (No Bit Access) (Actionable Reads)
- 25.6.24 CRYPTO_DATA0XOR - DATA0XOR Register Access (No Bit Access) (Actionable Reads)
- 25.6.25 CRYPTO_DATA0BYTE - DATA0 Register Byte Access (No Bit Access) (Actionable Reads)
- 25.6.26 CRYPTO_DATA1BYTE - DATA1 Register Byte Access (No Bit Access) (Actionable Reads)
- 25.6.27 CRYPTO_DATA0XORBYTE - DATA0 Register Byte XOR Access (No Bit Access) (Actionable Reads)
- 25.6.28 CRYPTO_DATA0BYTE12 - DATA0 Register Byte 12 Access (No Bit Access)
- 25.6.29 CRYPTO_DATA0BYTE13 - DATA0 Register Byte 13 Access (No Bit Access)
- 25.6.30 CRYPTO_DATA0BYTE14 - DATA0 Register Byte 14 Access (No Bit Access)
- 25.6.31 CRYPTO_DATA0BYTE15 - DATA0 Register Byte 15 Access (No Bit Access)
- 25.6.32 CRYPTO_DDATA0 - DDATA0 Register Access (No Bit Access) (Actionable Reads)
- 25.6.33 CRYPTO_DDATA1 - DDATA1 Register Access (No Bit Access) (Actionable Reads)
- 25.6.34 CRYPTO_DDATA2 - DDATA2 Register Access (No Bit Access) (Actionable Reads)
- 25.6.35 CRYPTO_DDATA3 - DDATA3 Register Access (No Bit Access) (Actionable Reads)
- 25.6.36 CRYPTO_DDATA4 - DDATA4 Register Access (No Bit Access) (Actionable Reads)
- 25.6.37 CRYPTO_DDATA0BIG - DDATA0 Register Big Endian Access (No Bit Access) (Actionable Reads)
- 25.6.38 CRYPTO_DDATA0BYTE - DDATA0 Register Byte Access (No Bit Access) (Actionable Reads)
- 25.6.39 CRYPTO_DDATA1BYTE - DDATA1 Register Byte Access (No Bit Access) (Actionable Reads)
- 25.6.40 CRYPTO_DDATA0BYTE32 - DDATA0 Register Byte 32 access. (No Bit Access)
- 25.6.41 CRYPTO_QDATA0 - QDATA0 Register Access (No Bit Access) (Actionable Reads)
- 25.6.42 CRYPTO_QDATA1 - QDATA1 Register Access (No Bit Access) (Actionable Reads)
- 25.6.43 CRYPTO_QDATA1BIG - QDATA1 Register Big Endian Access (No Bit Access) (Actionable Reads)
- 25.6.44 CRYPTO_QDATA0BYTE - QDATA0 Register Byte Access (No Bit Access) (Actionable Reads)
- 25.6.45 CRYPTO_QDATA1BYTE - QDATA1 Register Byte Access (No Bit Access) (Actionable Reads)
- 26. GPIO - General Purpose Input/Output
- 26.1 Introduction
- 26.2 Features
- 26.3 Functional Description
- 26.4 Register Map
- 26.5 Register Description
- 26.5.1 GPIO_Px_CTRL - Port Control Register
- 26.5.2 GPIO_Px_MODEL - Port Pin Mode Low Register
- 26.5.3 GPIO_Px_MODEH - Port Pin Mode High Register
- 26.5.4 GPIO_Px_DOUT - Port Data Out Register
- 26.5.5 GPIO_Px_DOUTTGL - Port Data Out Toggle Register
- 26.5.6 GPIO_Px_DIN - Port Data In Register
- 26.5.7 GPIO_Px_PINLOCKN - Port Unlocked Pins Register
- 26.5.8 GPIO_Px_OVTDIS - Over Voltage Disable for all modes
- 26.5.9 GPIO_EXTIPSELL - External Interrupt Port Select Low Register
- 26.5.10 GPIO_EXTIPSELH - External Interrupt Port Select High Register
- 26.5.11 GPIO_EXTIPINSELL - External Interrupt Pin Select Low Register
- 26.5.12 GPIO_EXTIPINSELH - External Interrupt Pin Select High Register
- 26.5.13 GPIO_EXTIRISE - External Interrupt Rising Edge Trigger Register
- 26.5.14 GPIO_EXTIFALL - External Interrupt Falling Edge Trigger Register
- 26.5.15 GPIO_EXTILEVEL - External Interrupt Level Register
- 26.5.16 GPIO_IF - Interrupt Flag Register
- 26.5.17 GPIO_IFS - Interrupt Flag Set Register
- 26.5.18 GPIO_IFC - Interrupt Flag Clear Register
- 26.5.19 GPIO_IEN - Interrupt Enable Register
- 26.5.20 GPIO_EM4WUEN - EM4 wake up Enable Register
- 26.5.21 GPIO_ROUTEPEN - I/O Routing Pin Enable Register
- 26.5.22 GPIO_ROUTELOC0 - I/O Routing Location Register
- 26.5.23 GPIO_INSENSE - Input Sense Register
- 26.5.24 GPIO_LOCK - Configuration Lock Register
- 27. APORT - Analog Port
- Appendix 1. Abbreviations
- Table of Contents