EFM8LB1 Reference Manual
User Manual:
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- Table of Contents
- 1. System Overview
- 2. Memory Organization
- 3. Special Function Registers
- 4. Flash Memory
- 5. Device Identification
- 6. Interrupts
- 6.1 Introduction
- 6.2 Interrupt Sources and Vectors
- 6.3 Interrupt Control Registers
- 6.3.1 IE: Interrupt Enable
- 6.3.2 IP: Interrupt Priority
- 6.3.3 IPH: Interrupt Priority High
- 6.3.4 EIE1: Extended Interrupt Enable 1
- 6.3.5 EIP1: Extended Interrupt Priority 1 Low
- 6.3.6 EIP1H: Extended Interrupt Priority 1 High
- 6.3.7 EIE2: Extended Interrupt Enable 2
- 6.3.8 EIP2: Extended Interrupt Priority 2
- 6.3.9 EIP2H: Extended Interrupt Priority 2 High
- 7. Power Management and Internal Regulator
- 8. Clocking and Oscillators
- 9. Reset Sources and Power Supply Monitor
- 10. CIP-51 Microcontroller Core
- 11. Port I/O, Crossbar, External Interrupts, and Port Match
- 11.1 Introduction
- 11.2 Features
- 11.3 Functional Description
- 11.4 Port I/O Control Registers
- 11.4.1 XBR0: Port I/O Crossbar 0
- 11.4.2 XBR1: Port I/O Crossbar 1
- 11.4.3 XBR2: Port I/O Crossbar 2
- 11.4.4 PRTDRV: Port Drive Strength
- 11.4.5 P0MASK: Port 0 Mask
- 11.4.6 P0MAT: Port 0 Match
- 11.4.7 P0: Port 0 Pin Latch
- 11.4.8 P0MDIN: Port 0 Input Mode
- 11.4.9 P0MDOUT: Port 0 Output Mode
- 11.4.10 P0SKIP: Port 0 Skip
- 11.4.11 P1MASK: Port 1 Mask
- 11.4.12 P1MAT: Port 1 Match
- 11.4.13 P1: Port 1 Pin Latch
- 11.4.14 P1MDIN: Port 1 Input Mode
- 11.4.15 P1MDOUT: Port 1 Output Mode
- 11.4.16 P1SKIP: Port 1 Skip
- 11.4.17 P2MASK: Port 2 Mask
- 11.4.18 P2MAT: Port 2 Match
- 11.4.19 P2: Port 2 Pin Latch
- 11.4.20 P2MDIN: Port 2 Input Mode
- 11.4.21 P2MDOUT: Port 2 Output Mode
- 11.4.22 P2SKIP: Port 2 Skip
- 11.4.23 P3: Port 3 Pin Latch
- 11.4.24 P3MDIN: Port 3 Input Mode
- 11.4.25 P3MDOUT: Port 3 Output Mode
- 11.5 INT0 and INT1 Control Registers
- 12. Analog to Digital Converter (ADC0)
- 12.1 Introduction
- 12.2 Features
- 12.3 Functional Description
- 12.4 ADC Control Registers
- 12.4.1 ADC0CN0: ADC0 Control 0
- 12.4.2 ADC0CN1: ADC0 Control 1
- 12.4.3 ADC0CN2: ADC0 Control 2
- 12.4.4 ADC0CF0: ADC0 Configuration
- 12.4.5 ADC0CF1: ADC0 Configuration
- 12.4.6 ADC0CF2: ADC0 Power Control
- 12.4.7 ADC0L: ADC0 Data Word Low Byte
- 12.4.8 ADC0H: ADC0 Data Word High Byte
- 12.4.9 ADC0GTH: ADC0 Greater-Than High Byte
- 12.4.10 ADC0GTL: ADC0 Greater-Than Low Byte
- 12.4.11 ADC0LTH: ADC0 Less-Than High Byte
- 12.4.12 ADC0LTL: ADC0 Less-Than Low Byte
- 12.4.13 ADC0MX: ADC0 Multiplexer Selection
- 12.4.14 ADC0ASCF: ADC0 Autoscan Configuration
- 12.4.15 ADC0ASAH: ADC0 Autoscan Start Address High Byte
- 12.4.16 ADC0ASAL: ADC0 Autoscan Start Address Low Byte
- 12.4.17 ADC0ASCT: ADC0 Autoscan Output Count
- 13. Comparators (CMP0 and CMP1)
- 14. Configurable Logic Units (CLU0, CLU1, CLU2, CLU3)
- 14.1 Introduction
- 14.2 Features
- 14.3 Functional Description
- 14.4 Configurable Logic Control Registers
- 14.4.1 CLEN0: Configurable Logic Enable 0
- 14.4.2 CLIE0: Configurable Logic Interrupt Enable 0
- 14.4.3 CLIF0: Configurable Logic Interrupt Flag 0
- 14.4.4 CLOUT0: Configurable Logic Output 0
- 14.4.5 CLU0MX: Configurable Logic Unit 0 Multiplexer
- 14.4.6 CLU0FN: Configurable Logic Unit 0 Function Select
- 14.4.7 CLU0CF: Configurable Logic Unit 0 Configuration
- 14.4.8 CLU1MX: Configurable Logic Unit 1 Multiplexer
- 14.4.9 CLU1FN: Configurable Logic Unit 1 Function Select
- 14.4.10 CLU1CF: Configurable Logic Unit 1 Configuration
- 14.4.11 CLU2MX: Configurable Logic Unit 2 Multiplexer
- 14.4.12 CLU2FN: Configurable Logic Unit 2 Function Select
- 14.4.13 CLU2CF: Configurable Logic Unit 2 Configuration
- 14.4.14 CLU3MX: Configurable Logic Unit 3 Multiplexer
- 14.4.15 CLU3FN: Configurable Logic Unit 3 Function Select
- 14.4.16 CLU3CF: Configurable Logic Unit 3 Configuration
- 15. Cyclic Redundancy Check (CRC0)
- 16. Digital to Analog Converters (DAC0, DAC1, DAC2, DAC3)
- 16.1 Introduction
- 16.2 Features
- 16.3 Functional Description
- 16.4 DAC Control Registers
- 16.4.1 DACGCF0: DAC Global Configuration 0
- 16.4.2 DACGCF1: DAC Global Configuration 1
- 16.4.3 DACGCF2: DAC Global Configuration 2
- 16.4.4 DAC0CF0: DAC0 Configuration 0
- 16.4.5 DAC0CF1: DAC0 Configuration 1
- 16.4.6 DAC0L: DAC0 Data Word Low Byte
- 16.4.7 DAC0H: DAC0 Data Word High Byte
- 16.4.8 DAC1CF0: DAC1 Configuration 0
- 16.4.9 DAC1CF1: DAC1 Configuration 1
- 16.4.10 DAC1L: DAC1 Data Word Low Byte
- 16.4.11 DAC1H: DAC1 Data Word High Byte
- 16.4.12 DAC2CF0: DAC2 Configuration 0
- 16.4.13 DAC2CF1: DAC2 Configuration 1
- 16.4.14 DAC2L: DAC2 Data Word Low Byte
- 16.4.15 DAC2H: DAC2 Data Word High Byte
- 16.4.16 DAC3CF0: DAC3 Configuration 0
- 16.4.17 DAC3CF1: DAC3 Configuration 1
- 16.4.18 DAC3L: DAC3 Data Word Low Byte
- 16.4.19 DAC3H: DAC3 Data Word High Byte
- 17. I2C Slave (I2CSLAVE0)
- 17.1 Introduction
- 17.2 Features
- 17.3 Functional Description
- 17.4 I2C0 Slave Control Registers
- 17.4.1 I2C0DIN: I2C0 Received Data
- 17.4.2 I2C0DOUT: I2C0 Transmit Data
- 17.4.3 I2C0SLAD: I2C0 Slave Address
- 17.4.4 I2C0STAT: I2C0 Status
- 17.4.5 I2C0CN0: I2C0 Control
- 17.4.6 I2C0FCN0: I2C0 FIFO Control 0
- 17.4.7 I2C0FCN1: I2C0 FIFO Control 1
- 17.4.8 I2C0FCT: I2C0 FIFO Count
- 17.4.9 I2C0ADM: I2C0 Slave Address Mask
- 18. Programmable Counter Array (PCA0)
- 18.1 Introduction
- 18.2 Features
- 18.3 Functional Description
- 18.4 PCA0 Control Registers
- 18.4.1 PCA0CN0: PCA Control
- 18.4.2 PCA0MD: PCA Mode
- 18.4.3 PCA0PWM: PCA PWM Configuration
- 18.4.4 PCA0CLR: PCA Comparator Clear Control
- 18.4.5 PCA0L: PCA Counter/Timer Low Byte
- 18.4.6 PCA0H: PCA Counter/Timer High Byte
- 18.4.7 PCA0POL: PCA Output Polarity
- 18.4.8 PCA0CENT: PCA Center Alignment Enable
- 18.4.9 PCA0CPM0: PCA Channel 0 Capture/Compare Mode
- 18.4.10 PCA0CPL0: PCA Channel 0 Capture Module Low Byte
- 18.4.11 PCA0CPH0: PCA Channel 0 Capture Module High Byte
- 18.4.12 PCA0CPM1: PCA Channel 1 Capture/Compare Mode
- 18.4.13 PCA0CPL1: PCA Channel 1 Capture Module Low Byte
- 18.4.14 PCA0CPH1: PCA Channel 1 Capture Module High Byte
- 18.4.15 PCA0CPM2: PCA Channel 2 Capture/Compare Mode
- 18.4.16 PCA0CPL2: PCA Channel 2 Capture Module Low Byte
- 18.4.17 PCA0CPH2: PCA Channel 2 Capture Module High Byte
- 18.4.18 PCA0CPM3: PCA Channel 3 Capture/Compare Mode
- 18.4.19 PCA0CPL3: PCA Channel 3 Capture Module Low Byte
- 18.4.20 PCA0CPH3: PCA Channel 3 Capture Module High Byte
- 18.4.21 PCA0CPM4: PCA Channel 4 Capture/Compare Mode
- 18.4.22 PCA0CPL4: PCA Channel 4 Capture Module Low Byte
- 18.4.23 PCA0CPH4: PCA Channel 4 Capture Module High Byte
- 18.4.24 PCA0CPM5: PCA Channel 5 Capture/Compare Mode
- 18.4.25 PCA0CPL5: PCA Channel 5 Capture Module Low Byte
- 18.4.26 PCA0CPH5: PCA Channel 5 Capture Module High Byte
- 19. Serial Peripheral Interface (SPI0)
- 20. System Management Bus / I2C (SMB0)
- 20.1 Introduction
- 20.2 Features
- 20.3 Functional Description
- 20.4 SMB0 Control Registers
- 20.4.1 SMB0CF: SMBus 0 Configuration
- 20.4.2 SMB0TC: SMBus 0 Timing and Pin Control
- 20.4.3 SMB0CN0: SMBus 0 Control
- 20.4.4 SMB0ADR: SMBus 0 Slave Address
- 20.4.5 SMB0ADM: SMBus 0 Slave Address Mask
- 20.4.6 SMB0DAT: SMBus 0 Data
- 20.4.7 SMB0FCN0: SMBus 0 FIFO Control 0
- 20.4.8 SMB0FCN1: SMBus 0 FIFO Control 1
- 20.4.9 SMB0RXLN: SMBus 0 Receive Length Counter
- 20.4.10 SMB0FCT: SMBus 0 FIFO Count
- 21. Timers (Timer0, Timer1, Timer2, Timer3, Timer4 and Timer5)
- 21.1 Introduction
- 21.2 Features
- 21.3 Functional Description
- 21.4 Timer 0, 1, 2, 3, 4, and 5 Control Registers
- 21.4.1 CKCON0: Clock Control 0
- 21.4.2 CKCON1: Clock Control 1
- 21.4.3 TCON: Timer 0/1 Control
- 21.4.4 TMOD: Timer 0/1 Mode
- 21.4.5 TL0: Timer 0 Low Byte
- 21.4.6 TL1: Timer 1 Low Byte
- 21.4.7 TH0: Timer 0 High Byte
- 21.4.8 TH1: Timer 1 High Byte
- 21.4.9 TMR2RLL: Timer 2 Reload Low Byte
- 21.4.10 TMR2RLH: Timer 2 Reload High Byte
- 21.4.11 TMR2L: Timer 2 Low Byte
- 21.4.12 TMR2H: Timer 2 High Byte
- 21.4.13 TMR2CN0: Timer 2 Control 0
- 21.4.14 TMR2CN1: Timer 2 Control 1
- 21.4.15 TMR3RLL: Timer 3 Reload Low Byte
- 21.4.16 TMR3RLH: Timer 3 Reload High Byte
- 21.4.17 TMR3L: Timer 3 Low Byte
- 21.4.18 TMR3H: Timer 3 High Byte
- 21.4.19 TMR3CN0: Timer 3 Control 0
- 21.4.20 TMR3CN1: Timer 3 Control 1
- 21.4.21 TMR4RLL: Timer 4 Reload Low Byte
- 21.4.22 TMR4RLH: Timer 4 Reload High Byte
- 21.4.23 TMR4L: Timer 4 Low Byte
- 21.4.24 TMR4H: Timer 4 High Byte
- 21.4.25 TMR4CN0: Timer 4 Control 0
- 21.4.26 TMR4CN1: Timer 4 Control 1
- 21.4.27 TMR5RLL: Timer 5 Reload Low Byte
- 21.4.28 TMR5RLH: Timer 5 Reload High Byte
- 21.4.29 TMR5L: Timer 5 Low Byte
- 21.4.30 TMR5H: Timer 5 High Byte
- 21.4.31 TMR5CN0: Timer 5 Control 0
- 21.4.32 TMR5CN1: Timer 5 Control 1
- 22. Universal Asynchronous Receiver/Transmitter 0 (UART0)
- 23. Universal Asynchronous Receiver/Transmitter 1 (UART1)
- 23.1 Introduction
- 23.2 Features
- 23.3 Functional Description
- 23.4 UART1 Control Registers
- 23.4.1 SCON1: UART1 Serial Port Control
- 23.4.2 SMOD1: UART1 Mode
- 23.4.3 SBUF1: UART1 Serial Port Data Buffer
- 23.4.4 SBCON1: UART1 Baud Rate Generator Control
- 23.4.5 SBRLH1: UART1 Baud Rate Generator High Byte
- 23.4.6 SBRLL1: UART1 Baud Rate Generator Low Byte
- 23.4.7 UART1FCN0: UART1 FIFO Control 0
- 23.4.8 UART1FCN1: UART1 FIFO Control 1
- 23.4.9 UART1FCT: UART1 FIFO Count
- 23.4.10 UART1LIN: UART1 LIN Configuration
- 23.4.11 UART1PCF: UART1 Pin Configuration
- 24. Precision Reference (VREF0)
- 25. Watchdog Timer (WDT0)
- 26. C2 Debug and Programming Interface
- 27. Revision History