EK 11040 TM 002 PDP 11 40, 35 (21 Inch Chassis) System Manual

EK-11040-TM-002 PDP-11-40,-11-35 (21 inch Chassis) System Manual EK-11040-TM-002 PDP-11-40,-11-35 (21 inch Chassis) System Manual

User Manual: EK-11040-TM-002 PDP-11-40,-11-35 (21 inch Chassis) System Manual

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PDP-11 /40,-11/35
(21 inch chassis)
system manual

EK-II040-TM-002

)

fillhor PDP~11/40,-11135

LPA~~2t j.~Cfh cb,~s$is)
'sysle'l1l manual-

)

(

)
digital equipment corporatio~ • maynard. massachusetts

First Edition, June 1973
2nd Printing (Rev), February 1974
3rd Printing, July 1974
4th Printing, January 1975

.~.)
..

The material in this manual is for informational
purposes and· is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.

Printed in U.S.A.

)

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIPCIDP
DIGITAL

UNIBUS

PDP
FOCAL
COMPUTER LAB

)

CONTENTS

Page

)

CHAPTER 1

INTRODUCTION

1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.5.1
1.3.5.2
1.3.5.3
1.3.6
1.3.7
1.3.8
1.4
1.5

SCOPE . . . . . . . . . . . . .
SYSTEM COMPONENTS
FUNCTIONAL DESCRIPTION
Unibus . . . . . . . . . .
KDll-AProcessor . . . .
KY11-D Programmer's Console
MF11-L Core Memory ..
Optional Memory Systems
PDP-11 /40 Memories
PDP-11/20 Memories
MFll-U/UP Core Memory
LA30 DECwriter . . . . . . . .
DL11 Asynchronous Line Interface
Power System . . . . . . . . . . . .
APPLICABLE DOCUMENTATION
ENGINEERING DRAWINGS . . . . . . .

CHAPTER 2

INSTALLATION

2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.3.1
2.2.3.2
2.2.3.3
2.2.3.4
2.2.3.5
2.2.3.6
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.5.1
2.3.5.2
2.3.5.3
2.3.6
2.3.7
2.3.8
2.4
2.5

SCOPE . . . . . . . . . .
SITE PREPARATION ..
Physical Dimensions
Fire and Safety Precautions
Environmental Requirements
Humidity and Temperature
Air Conditioning .,
Acoustical Damping
Lighting . . . . . .
Special Mounting Conditions
Static Electricity . , .
Electrical Requirements
INSTALLATION PROCEDURES
Unpacking . . . .
Inspection . . . . . .
Cabinet Installation
AC Power Connections
Intercabinet Connections
Unibus Connections
Remote Power Connections
Ground Strapping . . . . .
Remote Peripheral Interconnection
Installation Verification . . . . . .
...... .
Initial Power Turn-on
INITIAL OPERATION AND PROGRAMMING
CUSTOMER ACCEPTANCE . . . . . . . . . .

)
iii

1-1
1-1
1-1

1-4
1-5
1-6
1-6
1-7
1-7
1-8
1-9
1-9
1-10
1-10

1-11
1-13

2-1
2-1
2-2

2-2
2-3
2-3
2-3
2-3
2-3
2-3
2~3

2-3
2-4
2-4
2-5
2-5
2-6
2-6
2-6
2-6
2-6
2-7
2-7

. 2-12
2-13

. 2-13

)

CONTENTS (Cont)
Page
CHAPTER 3

SYSTEM OPERATION

3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.2.1
3.5.2.2
3.5.3
3.5.4
3.5.4.1
3.5.4.2
3.5.5
3.6

SCOPE . . . . . . . .
KYII-D PROGRAMMER'S CONSOLE
DECwriter . . . . .
TELETYPE
.... .
BASIC OPERATION
Power On
Basic Console Control
ENABLE/HALT Switch
Loading Data Manually
Manual Program Loading (Bootstrap Loader)
Automatic Program Loading . . .
Loading Absolute Loader
Loading Maintenance Loader
Running Programs
BASIC PROGRAMMING . . . . . . .

CHAPTER 4

PROCESSOR INSTRUCTIONS· AND OPTIONS

4.1
4.2
4.2.1
4.2.2
4.2.3
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7

SCOPE . . . . . . .
INSTRUCTION SET . . . .
Address Modes . . . .
Basic InstruCtion Set
Extended Instruction Set
PROCESSOR OPTIONS . . .
KEI1-E Extended Instruction Set (EIS) Option
KEI1-F Floating Instruction Set (FIS) Option
KJll-A Stack Limit Register Option ..... .
KT11-D Memory Management Option
KWII-L Line Time Clock Option
KMI1-A Maintenance Console Option
Small Peripheral Controller

CHAPTERS

SYSTEM PERIPHERALS AND OPTIONS

5.1
5.2

SCOPE . . . . . . . . . . . . .
PERIPHERALS AND OPTIONS . . . . .

CHAPTER 6

EQUIPMENT MOUNTING AND POWER

6.1
6.2
6.2.1
6.2.2
6.2.3
6.3
6.3.1
6.3.2

SCOPE . . . . . . . . . . . . . . .
SYSTEM MOUNTING BOX . . . .
Processor Module Allocations
Memory Module Allocations .
Programmer's Console Mounting
CABINET AND SYSTEM MOUNTING
System Cabinet
. •
System Configuration . • . . . .

·
·
·
·

·
·
·
·
·
.
.
.
.
·
·
·
·

3-1
3-1
3-15
3-15
3-19
3-20
3-20
3-20
3-20
3-21
3-25
3·26
3-28
3-29
3-29

·
·
·
·
·
·
·
·
·

4-1
4-1
4-3
4-5
4·17
4-22
4-23
4-24
4-25
4-26
4-27
4-29
4-29

)

5-1
5-1

6-1
6-1
6-3
6-3
6-3
6-3
6-5
6-5

)
iv

.. , CONTENTS'(Cont)

Page

)

6.4
6.4.1
6.4.2
6.4.2.1
6.4.2.2
6.4.2.3
6.4.3
6.4.3.1
6.4.3.2
6.4.3.3
6.4.4
6.4.4.1
6.4.4.2
6.4.4.3
6.4.4a
6.4.5
6.4.6
6.4.7
6.4.7.1
6.4.7.2

POWER SYSTEM
861 Power Controller
H742 Power Supply
H742 +15V Output
H742 Clock Output
AC LO and DC LO Circuits
H744 +5V Regulator ......
H744 Regulator Circuit
H744 Overcurrent Sensing Circuit
H744 Overvoltage Crowbar Circuit
H745 -15V Regulator
H745 Regulator Circuit .....
H745 Overcurrent Sensing Circuit
H745 Overvoltage Crowbar Circuit
H754 +20, -5V Regulator
861 Power Controller Interconnection
Power System Cable Harnesses ....
DC Power Distribution · .......
Early Power Distribution Systems
Newer Power Distribution Systems

CHAPTER 7

GENERAL MAINTENANCE

7.1
7.2
72.1
7.2.2
7.2.3
7.2.4
7.3
7.4
7.4.1
7.4.2
7.4.2.1
7.4.2.2
7.4.2.3
7.4.2.4
7.4.3
7.4.3.1
7.4.3.2
7.4.4
7.4.5
7.4.5.1
7.4.5.2

SCOPE . . . . . . . . . . . · .........
OVERALL MAINTENANCE TECHNIQUES
Knowledge of Proper Hardw~re Operation
Detection and isolation of Error Conditions
Means of R.epairing Error Conditions
.
Digital Field Service .........
MAINTENANCE EQUIPMENT REQUIRED
PREVENTIVE MAINTENANCE· ...
Physical Checks ...........
Electrical C;hecks aqd Adjustments . .
Processor Clock Adjustment Check
Voltage Regulator Checks
861 Power Controller ......
AC Po~er Connector Receptacles
ASR 33 Teletype' . . . . . '., . . .
Preventive Maintenance Checks
Lubrication
.........
LA30 DECwriter Preventive Maintenance
PC05 High-Speed Paper-Tape Read/punch Option
Mechanical Checks
Electrical Checks · .............

;."

• •'

•

)
v

•••

6-7
6-9
6-9
6-10
6-10
6-10
6-10
6-11
6~12

6-12
6-12
6-12
6-12
6-13
6-13
6-13
6-15
6-15
6-16
6-18

7-1
7-1
7-1
7-2
7-2
7-2
7-3
7-3
7-3
7-3
7-5
7-5
7-5
7-5
7-5
.7-5
7-6
7-6
7-6
7-6
7-7

'.. -

CONTENTS (Cont)

)
Page

7.5
7.5.1
7.5.2
7.6
7.7
7.7.1
7.7.2

DIAGNOSTIC PROGRAMS . . . .
General Description . . . . .
Diagnostic Program Utilization
USE OF MODULE EXTENDERS
PDP-l1/40 POWER SYSTEM MAINTENANCE
Visual Inspection . .
Power System Checks

APPENDIX A

SUMMARY OF EQUIPMENT SPECIFICA nONS

7·7
7-7
7-9
7-12
7-12
7-12
7-12

ILLUSTRAnONS
Figure No.
1-1
3-1a
3-1b
3-2
3-3
3-4
3-5
4-1
4-2
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14

Title
PDP-l 1/40 Basic System Block Diagram
PDP-l1/40 Programmer's Console
PDP-l 1/35 Programmer's Console
LA30-S Keyboard
LA30 Power Controls . . . . . .
Teletype Controls
. . . . . .
Flowchart of Procedure for Loading and Running Programs
Double and Single Operand Addressing
Instruction Formats . . . . . . . . .
PDP-l 1/40 System Cabinet
.... .
PDP-ll/40 Mounting Box (BAll-FC)
Module Allocation - KDl1-A Processor, Basic and Options
Module Allocation - MF l1-L Memory, Basic and Optional MM ll-Ls
Typical Multiple Cabinet System Configuration
PDP-l 1/40 Power, System Block Diagram . . . . .
Precision Voltage Regulator El, Simplified Diagram
Power Control Interconnection
......... .
Regulated DC Power Distribution . . . . . . . . .
Power Distribution - Early Units with System Serial No. 5999 and Lower
Power Distribution Schematic - Early Systems
(System Serial No. 5999 and lower) . . . . . . . . . . . . . . . . . . . .
MF 11-U /UP Installation - Early Systems . . . . . . . . . . . . . . . . .
Power Distribution - Newer Unit with System Serial No. 6000 and Higher
Power Distribution Schematic - Newer SYstems
(System Serial No. 6000 and Higher)
.................. .

Page

·
·
·
·

1-4
3-2
3-2
3-16
3-16
3-17
3-23
4-4
4-4
6-2
6-3
6-4
6-4
6-6
6-8
6-11
6-14
6-16
6-17
6-19
6-20
6-21
6-22

TABLES·
Table No.
1-1
1-2
1-3

Title
Possible PDP-l 1/40 Variations .
Applicable Documents . . . . .
Drawing Set/Sheet Code Prefixes

1-2
1-11

1-14

Page

)

TABLES (Cont)
Table No.
2-1
2-2
3-1
3-2

3-3
3-4
3-5
3-6

3-7

3-8
3-9

)

4-1
4-2
4-3
4-4

4-5
4-6
4-7
4-8
4-9

)

4-10
4-11
4-12
4-13
4-14
4-15
4-16

4-17
5-1
6-1
6-2

)

7-1
7-2

7-3
7-4
7-5

Title
Option Installation Verification
Memory Verification or Installation
PDP-11/40 Console Indicators
PDP-I 1/40 Console Controls
LA30 Controls and Indicators
Teletype Controls . . . . . .
Program Identification Codes

Page

2-8
2-10

3-3
3-7
3"15

3-17
· 3-22

Bootstrap Loader (DEC-ll-LIPA-LA)
Binary Tape Load Selection (using Absolute Loader)
Relocation of Memory Contents
PDP-II Programming Comparison
ISP Symbology . . . . . . .
Address Modes . . . . . . .
Double Operand Instructions
Single Operand Instructions
Register Source or Destination Instruction
Branch Instruction . . . .
Miscellaneous Instructions ..
Condition Code Operators ..
Extended Instruction Set (EIS)
Floating Instruction Set (FIS)
Memory Management Instruction Set
Location of Processor Options
KE11-E (EIS) SpeCifications
KE11-F (FIS) Specifications
KJ11-A SpeCifications
KTll-D SpeCifications .. .
KW11-LSpecifications .. .
PDP-ll/40 Peripherals and Options
Timing Characteristics of PDP-II NPR Devices
Priority of Devices Affected by BR Latency
Maintenance Equipment Required
DC Output Voltages . . . . . . . . . . . .
PDP-ll/40 Diagnostic Programs . . . . . .
PDP-11/40 Processor Preliminary Diagnostic Program Error Analysis
Power System Troubleshooting Guide . . . . . . . . . . . . . . . .

)
vii

· 3-24

· 3-27
· 3-28
· 3-30
4-2
4-3
4-6
4-8
· 4-12
· 4-13
· 4-15
· 4-16
· 4-18
· 4-20
· 4-22
· 4-23
.. 4-24
· 4-26
· 4-27

· 4-28
· 4-28
5-1
6-5

6-7

7-4
7-5

7-8
7-10
7-13

FOREWORD

)

This Manual describes all PDP-ll/40s and those PDP-ll/35s that are
mounted in a 21-inch, (as opposed to a 10-1/2 inch) box.
Text references that specify "PDP-l 1/40" also apply to the PDP-l 1/35.

)

)
ix

)

CHAPTER 1
INTRODUCTION
1.1 SCOPE
This manual provides a general introduction to the PDP-ll/40 System and includes sections on installation,
operation, the instruction set, options, peripherals-, equipment mounting, power, and maintenance. This overview is
supplemented with references to other manuals in the PDP-l 1/40 series for detailed explanations.

)

The PDP-ll/40 series manuals provide the user with the theory of operation necessary to understand, operate, and
maintain the PDP-II /40 System. These man~als and the associated engineering drawings are discussed in Paragraph
1.4. Please note that the associated drawings' are separate volumes documented by their Drawing Directory number.
The manuals and drawings combine to form a complete documentation package.
The level of discussion in each manual assumes that the reader is familiar with basic digital computer theory. The
maintenance philosophy presents information about normal system operation and enables the user to recognize
trouble symptoms and take necessary corrective action. Each individual manual contains theory of operation,
diagrams, and maintenance techniques. Logic drawings for the specific components covered are contained in separate
volumes.
This chapter describes the basic system components (paragraph 1.2) and provides a functional description of the
overall PDP-ll/40 System and each of its major components (paragraph 1.3). The remainder of the chapter covers
applicable documents and engineering drawings (paragraphs 1.4 and 1.5).
1.2 SYSTEM COMPONENTS

)

The PDP-II/40 System consists of six basic components: processor, programmer's console, core memory,
DECwriter with associated control, power system, and mounting box. Possible variations to this basic system are
listed in Table 1-1.
I

Options and peripherals added to the basic PDP-ll/40 System are covered in separate manuals delivered with the
system. Manuals are included only for those options specifically ordered with an individual system.
1.3 FUNCTIONAL DESCRIPTION
The PDP-ll/40 is a 16-bit, general purpose, parallel logic, microprogrammed computer using single and double
operand instructions and 2's complement arithmetic. The system contains a multiple word instruction processor,
which directly addresses up to 28K words of core memory. All communication among system components
(including processor, core memory, and peripherals) is performed on a single high-speed bus, the Unibus. Because of
the bus concept, all peripherals are compatible, and device-to-device transfers can be accomplished at the rate of 2.5
million words per second. All system components and peripherals are linked by the Unibus and power connectors,
and all peripherals are in the basic system address space. Therefore, all instructions applied to data in memory can
also be applied to data in peripheral device registers, enabling peripheral device registers to be manipulated by the
processor as flexibly as memory.

)

Subsequent paragraphs present a brief functional description of basic PDP-II /40 System components (Figure 1-1). A
functional description of all processor options is presented in Chapter 4.
Revision 1
January 1974
1-1

Table 1.1
Possible PDP-I 1/40 Variations
Possible Variations

Major Component
*KO 11-A Processor

No variations in basic processor. However, any of the following internal
processor options can be included:
KE11·E Extended Instruction Set (EIS)
KEll·F Floating Instruction Set (FIS)
KJll·A Stack Limit Register
KM11·A Maintenance Console
KTll·D Memory Management
KWll·L line Time Clock

*KY1I-D Programmer's Console

None

Core Memory

MMll-L - 8K word core memory, 900 ns cycle time, 350 ns internal
access time
*MFll·L - MMll·L memory plus double system unit backplane,
(space exists for two additional MMll·Ls)
MFll·LP - Same as MFll·L with the addition of two parity bits
making it an 18·bit word memory
MEll·L - MMll·L memory plus backplane, mounting box, and power
supply (complete memory system)

MM II·S - MM 11-L memory, plus backplane (may be used for
expansion of memory above 24K)
NOTE
Memory systems compatible with the PDP·ll/20 may also
be used in the PDP·ll/40. However, these memories must
be housed in their own mounting boxes and powered by
their own power supplies. The memories are:
MMll·E
MMll·F
MMll·FP
MMll·H
MM11·J

4K by
4K by
4K by
lK by
2K by

)

16 bit
16 bit
18 bit, with parity
16 bit
16 bit

MMll·U - 16K word core memory
MFll·U - MMll-U plus double backplane (can accept one additional
MMll-U)
DECwriter
MMll-UP, MFll-UP - Same as MMll-U and MFll-U but with
addition of parity.
DECwriter

Revision 1
January 1974

* *LA30 - Standard 97·character keyboard. Optional 128-character
keyboard available. (LA30.S is a serial DECwriter and is controlled by a
DL11 control; LA30·P is a parallel DECwriter and is controlled by an
LCll control.)
.

1-2

)

Table 1-1 (Cont)
Possible PDP-l1/40 Variations

)
Major Component
Teletype Unit

Input Terminal Control

Possible Variations
**33 ASR
33 KSR
35 ASR
35KSR

Each unit is available in 120V or 240V models.

DLl1-A - Teletype, display, or LA30-S control.
DLl1-B - EIA terminal control.
DLl1-C - Teletype, display or LA30-S control. The DLl1-C is simply a
more flexible version of the DLlI-A. The DLlI-C features a variable
character code plus crystal and switch selectable baud rates.

)

DLlI-D - EIA terminal control. The DLlI-D is simply a more flexible
version of the DLl1-B. The DLlI-D features a variable character code
plus crystal and switch selectable baud rates.
DLl1-E - Dataset control.
KLli-A
KLll-B
KLlI-C
KLlI-E
KLlI-F

)

ASR or KSR Teletype control. Units differ primarily
in baud rates as described in KL11 manual.

LCl1 - LA30-P DECwriter control.
Power System

*H742 Power Supply (may be jumpered for either 120V or
50/60 Hz).

nov,

*H744 +5V regulator, 25A (three supplied with basic system)

)

*H745 -15V regulator, lOA (one or two)
H754 +20, -5V regulator, used with MFI1-UjUP
*861 Power Controller - mounted in bottom rear of cabinet. Two
versions available:
861B - requires 240 Vac input
861C - requires 120 Vac input
Mounting Box

*BAII-FC Mounting Box

*An asterisk indicates that this is the normal configuration shipped with the basic machine, unless otherwise specified by the
customer.
**Either the LA30 DECwriter or the Teletype unit may be used as the basic PDP-ll/40 System input/output device.

1-3

Revision 1
January 1974

UN I SUS

DLll
ASYNCHRONOUS
LINE INTERFACE

KDll-A
CENTRAL
PROCESSOR

MFlI-L
CORE
MEMORY
. (8K)

DECWriter
OR
TELETYPE

KDlI-D
PROGRAMMER'S
CONSOLE

)
POWER SYSTEM
861 POWER CONTROLLER

PR~~~~~>--

r------------------------________ ~..r~2_"~~~ :'U~~ _________ _
H744 REGULATOR (2)

I- - - - - - - - - H745-REGULATOR i2)~ -

- - - - -11-1719

Figure 1-1 PDP-I 1/40 Basic System Block Diagram

1.3.1 Unibus
The Unibus provides high-speed communication between system components. With bidirectional data, address, and
control lines, the Unibus allows data transfers to occur between all units on the bus, with control of the bus an
important factor in these transfers. The fIxed repertoire of bus operations is flexible enough for speed and design
economy, yet provides a fIxed specifIcation for interfaces. The asynchronous nature of these operations also eases
design and operation. The repertoire of bus operations is:

)

DATI, DATIP, DATO, DATOB - data operations
INTR, BR, NPR - control operations
Full I6-bit words or 8-bit bytes of information can be transferred on the bus between the master and slave. The
DATI, DATIP operations transfer data into the master; DATO, DATOB operations transfer data out of the master.
When a device is capable of becoming bus master and requests use of the bus, it is for one of two purposes: to make
a Direct Memory Access (DMA) transfer of data directly to or from another device or memory without processor
intervention, or to INTeRrupt (INTR) program execution and force the processor to branch to a specifIc address
where an interrupt service routine is located.
Bus control is obtained under a Non-Processor Request (NPR) for the DMA or under a Bus Request (BR) for an
INTR. A device can perform a DMA after acquiring bus control via a BR.
Requests for the bus can be made at any time on the BR and NPR lines. Transfer of bus control from one device to
another is made by the processor priority arbitration logic which grants control of the bus to the device having the
highest priority. NPRs are accorded higher priority than BRs. The NPRs are serviced befor~ and immediately after
Unibus data cycles, in addition to specifIc times during WAIT or TRAP sequences. The BRs are serviced upon
completion of the current instruction if the requesting priority exceeds that of the processor.
Revision 1
January 1974

)

The PDP·11/40 processor has a special role in bus control operations as it performs the priority arbitration to select
the next bus master. The processor assumes bus control when no other device has control.

l
/

The Unibus originates in the processor with the Internal Unibus and Terminator module (M981), which carries the
Unibus from the processor to the next system unit. All 56 Unibus signals and 17 grounds are carried in this one
module. In addition, a 120-conductor Mylar cable may be used to connect system units in different mounting boxes
or to connect a peripheral device removed from the mounting box.
A complete description of the Unibus, including specifications, is presented in the PDP-II Peripherals Handbook.

1.3.2 KDI1-A Processor

)

The KDll-A Processor decodes instructions; accepts, modifies, and outputs data; performs arithmetic operations;
and controls allocation of the Unibus among external devices. The processor contains sixteen hardware registers,
eight of which are programmable. Two of the eight programmable registers are specifically used for processor
operation: a program counter (PC) and a stack pointer (SP); the remaining six serve as arithmetic accumulators,
index register, and autoincrement and autodecrement registers.
The eight non-programmable registers are used for storage of a variety of functions including: intermediate address,
source and destination data, a copy of the instruction register, the last interrupt vector address, console operation
data and stack pointer for the KT11-D Memory Management Option.
Because of the flexibility of hardware registers, address modes, instruction set, and DMA, PDP-ll/40 programs are
written in directly relocatable codes. The processor also includes a full complement of instructions that manipulate
byte operands and provisions for byte swapping. Either words or bytes may be displayed on the programmer's
console.

)

Any of the eight programmable internal registers can be used to build last-in, first-out stacks. One register serves as a
processor (or system) stack pointer for automatic stacking. This stack-handling capability permits save and restore of
the program cou;nter and status word in conjunction with subroutine calls and interrupts. This feature allows true
reentrant codes and automatic nesting of subroutines.
The Unibus serves the processor and all peripheral devices; therefore, there must be a priority structure to determine
which device becomes bus master. Generally, a device requests use of the bus for one of two reasons: to make a
non-processor transfer of data directly to or from memory, or to interrupt program execution and force the
processor to br~nch to an interrupt service routine. An NPR is granted by the processor at the end of bus cycles and
allows device-to-device data transfers without processor intervention. A BR is granted by the processor at the end of
an instruction and allows the device to interrupt the current processor task.
The processor recognizes four levels of hardware BRs, with each major level containing sublevels. Many devices can
be attached on each major level, with the device that is electrically closest to the processor given priority over other
devices on the same priority level. The priority level of the processor itself is programmable within the hardware
levels; therefore, a running program can select the priority level of permissible interrupts.
Additional speed and power are added to the interrupt structure through the use of the PDP-ll/40 fully vectored
interrupt scheme. With vectored interrupts, the device identifies itself, and a unique interrupt service routine is
automatically selected by the processor. This eliminates device polling and permits nesting of device service routines.
The device interrupt priority and service routine priority are independent to allow dynamic adjustment of system
behavior in response to real-time conditions.

)

The Unibus addresses generated by the KDll-A Processor are 18-bit direct byte addresses, even though the
PDP-l1/40 word length and operational logic is all 16-bit word length. Thus, while the PDP-ll/40 word can only
contain address references up to 32K words (64K bytes), the KDII-A Processor can reference addresses up to 128K
words (256K bytes).
1-5

In addition to the word length constraint on basic addressing space, the uppemiost 4K words of address space are
reserved for peripheral control, status, and data registers. In the basic PDP-ll/40 confj.guratibn (without memory
management), all address references to the uppermost 4K words of 16-bit address space (160000-177777) are
converted to full 18-bit references with bits 16 and 17 always set to 1. Thus, a 16-bit reference to address 1732248
is automatically converted toa full I8-bit I/O device register address of 7732248 . Consequently, the basic
PDP-ll/40 configuration can address up to 28K words of core memory and 4K words of I/O device registers. If core
memory is increased beyond 28K words, the KT11-D Memory Management Option must be installed. A brief
description of the KT11-D Memory Management Option is provided in Chapter 4.

)

A detailed description of the KDll-A Processor is contained in the KDll-A Processor Maintenance Manual,
EK-KD11A-MM-00l.
1.3.3 KYI1-D Programmer's Console
The KYII-D Programmer's Console provides the programmer with a direct system interface. The console allows the
user to start, stop, load, modify, examine, step, or continue a program. Console displays indicate processor operation
and the contents of the address and data registers. The console is mounted as the front panel of the BAll-FC
Mounting Box and is connected to the processor by two cables.

)

The programmer's console interacts with the processor through a microprogram control located in the processor.
The console contains only indicators (light emitting diodes), switches, and the contact bounce ftltering circuits for
the control switches. Console operation does require certain Unibus operations through the processor: DATO for
DEP and DATI for EXAM. For single-step operation, the processor responds to a Console Bus Request (CBR) whose
priority supersedes all other BR priorities. Note that use of the KMll Maintenance Console option provides a
further display of machine states, and allows single microword stepping.
Console operation, including descriptions of all controls and indicators, is presented in Chapter 3. Detailed descriptions of console logic circuits are contained in the KDll-A Processor Maintenance Manual, EK-KD11A-MM-001.

)

1.3.4 MFll-L Core Memory

The PDP-ll/40 contains an MFll-L Core Memory. The MF11-L consists of a three-module, 8K, 16-bit word,
MMI1-L memory mounted on a double system unit backplane. The backplane has nine slots of mounting space,
hence two additional MMII-L memories may be mounted on the backplane as options. With two additional MMll-L
memoi."ies installed, the memory size is increased to a total of 24K. A detailed description of the memory is
contained in the MMll-S, MFll-L, and MFll-LP Core Memory System, EK-MMI1S-TM-003.
NOTE
PDP-ll/40 memory is powered for non-interleaved and
non-overlapped situations. Successive and continuous
operations to alternate 8K memory segments is considered a
prohibited overlapped situation. Intedeaving is not allowed
within the MFlt-L or MMll-S powered by the basic box.

)

The core memory uses the Unibus for data transfers to and from the processor and other devices. The core memory,
however, is never bus master; therefore, DATO or DATOB indicates information transferred out of the master into
the memory. Because of the Unibus structure, the memory can be directly addressed by the processor or any other
master device. Because of double operand instructions, every location in core can function as a true arithmetic
accumulator.
The memory does not enter the priority structure because it is always a slave device. The master device, however;
can request use of the Unibus and thus the memory through either a BRor a NPR. Because the memory is
completely independent of the processor, any master device can perform direct data transfers with memory without
processor intervention.
1-6

)

NOTE
The instruction timing specified for the PDP-ll/40 applies
only for the memories mounted within the computer
mounting box_ These memories employ a special MSYN A
signal between the processor and the memory.
1.3.5 Optional Memory Systems
Memories with different ranges of speeds and various physical and electrical characteristics can be freely mixed and
interchanged in a single PDP-ll!40 System. The basic system mounting box can house up to 80K of memory in
addition to the processor and processor options. Additional memory units may be added by using separate mounting
boxes and power supplies up to a total of 124K. Note that the KT11-D Memory Management Option is required if
core memory is increased beyond 28K.

)

Generally, memory systems compatible with the PDP-l1/40 fall into two categories: memories designed for use
with the PDP-ll/40 and memories designed for use with the PDP-ll/20. The PDP-ll/40 memories are: MMII-L,
MFII-L, MFI1-LP, MEII-L, and MMll-S. The PDP-ll/20 memories are: MMII-E, MMII-F, MMII-FP, MMl1-H,
and MMII-J.
1.3.5.1 PDP-ll/40 Memories - The following paragraphs provide brief descnptions of the MMll-L, MFll-LP,
MEll-L, and MMll-S memories (the MFll-L memory was described in Paragraph 1.3.4). For detailed descriptions
of the MMll-L, MFll-LP, and MMll-S memories, refer to the MMll-S, MFll-L, and MFll-LP Core Memory
System, EK-MM lIS-TM-003. For a detailed description of theME 11-L memory, refer to the MEll-L Core Memory
System Manual, DEC-I1-HMELA-B-D.

1.3.5.1.1 MMll-L Core Memory - The MMll-L Core Memory is a read/write, random access, coincident current,
magnetic core type. memory with a cycle time of 900 ns and Unibus access time of 400 ns. The memory is organized
in a 3D, 3-wire planar configuration. It provides 8192 (8K) 16-bit words that are both word and byte addressable.

)

The memory is organized into 16-bit words, each word containing two 8-bit bytes. The bytes are identified as the
low-order byte (bits 07-00) and the high-order byte (bits 15-08). Each byte is addressable and has its own address
location. Low bytes are always even numbered and high bytes are odd numbered. Full words are addressed .at
even-numbered locations only. When a full word is addressed, the high byte is automatically included. For example,
the 8K memory has 8,192 words or 16,384 bytes; therefore, 16,384 locations are assigned. Address 000000 is the
first low byte, address 000001 is the first high byte, 000002 is the second low byte, 000003 is the second high byte,
etc.
The MMll-L consists of three modules: ~G1l0 Hex module containing the memory control logic and data
channels; a G231 Hex module containing the memory driver logic; and an H214 Quad module containing the
memoryco~
The memory control logic acknowledges the request of the master device, determines which of the four basic
operationS (DATI, DATIP, DATa, or DATOB) is to be performed, and sets up appropriate timing and control
circuits to perform the desired read or write operation. It also contains the inhibit drivers and sense amplifiers as well
as device selector logic to determine if the memory bank has been addressed from the Unibus. The control logic
includes a 16-bit flip-flop storage register. During DATI operations, this register stores the contents of the memory
location being read (destructive read) so that the data can be written back into memory (restoted). The register is
also used during DATa and DATOB cycles to store incoming data from the Unibus lines so that it can be written
into core memory.

)

The memory driver logic includes: address selection logic th~t decodes the incoming address to determine the core
specifically addressed; the switches and drivers that direct current flow through the magnetic cores to ensure the
proper polarity for the desired function; and the X and Y current generators that provide the necessary current to
change the state of the magnetic cores.
1-7

The ferrite core memory stack consists of 16 memory mats arranged in a planar configuration. Each mat contains
8192 ferrite cores arranged in a 128 X 64 matrix. Each mat represents a single bit position of a word. Each ferrite
core can assume a stable magnetic state corresponding to either a binary 1 or binary O. Even if power is removed
from the core, the core retains its state until changed by appropriate control signals.

1.3 5.1.2 MFll·LP Core Memory - The MFl1·LP is an 8K, 18·bit word memory consisting of four modules
mounted on a double system unit backplane. Three modules perform identical functions as those in the MMll·L
memory while the fourth module contains parity control circuitry. The two additional bits (bits 16 and 17) provide
parity bits for the low and high bytes of the data word respectively. The MFll·LP may be expanded to 24K
capacity by installing two additional 8K segments (three modules each) on the double system unit backplane.
Note that while the 8K MFll·LP memory contains four modules, the 24K unit only requires 9 module slots (one
double system unit). This is possible because only one parity controller module is needed for 24K. The parity
controller module is a dual·height module and is installed in the two normally vacant slot/sections next to the
memory stack module.

1.3.5.1.3 MEll·L Core Memory - The MEll·L is a complete memory system consisting of an MMll·L Core
Memory and associated backplane housed in its own mounting box which contains an integral power supply. This
power supply and mounting box can accommodate up to three MMl1·L Core Memories. In effect, the MEll·L can
be expanded up to 24K in 8K increments. These memories should not be interleaved due to power supply
limitations.

)

The system mounting box is 5·1/4 in. high, 19 in. wide, and 20 in. deep and is d~signed for mounting in a standard
19·in. cabinet. Rack·mountable slides are included but the box can be used as a stand·alone unit, if desired. In
addition to holding the core memory, backplane, and power supply, the box contains all cables necessary for
providing power and for interfacing the units of the MEl1·L. It also provides for connection to the Unibus. The rear
of the box contains cable clamps, a line cord for input power, a cooling fan for the memory modules and power
supply, and a power control circuit breaker.
The memory system power supply converts single·phase 115 or 230 Vac line voltage to the two regulated dc voltages
required by the memory system: +5V for the logic and -15V for the core memory. Both outputs are overvoltage
and overcurrent protected. The power supply also provides line power to the mounting box cooling fan and the BUS
AC LO and BUS DC LO signals which are sent to the Unibus in the event of a power failure.
The power supply consists of a power control, a power chassis assembly, and a dc regulator along with associated ac
and dc cables. The power control contains a thermal circuit breaker which protects against input and overload and is
reset by depressing a button on the rear of the mounting box. A thermostat in the regulator opens one side of the
primary circuit and deenergizes the power supply if the temperature rises above 100° C. It is automatically reset
when the temperature reaches 63° C.

)

1.3.5.1.4 MMll·S Core Memory - The MMll·S Core Memory is an MMll·L memory on a single system unit
backplane. The prime physical difference between the MMll·S and the MFll·L is that the MMll·S is an 8K single
system unit while the MFll·L is a 24K capacity double system unit.. The MMll·S should not be interleaved in the
PDP·ll/40.
1.3.5.2 PDP·11/20 Memories - Brief descriptions of the PDP· 11 /20 memories are proVided belQw. These memories
may be used with the PDP· 11 /40 System prOVided they are powered by H720 Power Supplies and are mounted in a
BAll·ES Mounting Box. The MMll·E and MMll·F memories are expandable to 28K with interleaving of 4K
segments permitted.
MMll·E - 4K by 16 bit, 1.2 J.1.s access time
MM11·F - 4K by 16 bit, 950 ns access time
MMll·FP - an MMll·F with parity option included
MMll·H - 1K by 16 bit, 950 ns access time
MMl1·J - 2K by 16 bit, 950 ns access time
1·8

)

1.3.5.3 MFII-U/UP Core Memory - The MFII-U/UP Memory is a read/write, random access coincident current~
magnetic core type with a maximum cycle time of 980 ns and a maximum access time of 425 ns. It is organized in a
3D, 3-wire planar configuration. Word length is 16 bits and the memory consists of 16,384 (16K) words.
The MFII-U provides 16,384 (16K)
parity.

16~bitwords;

the MFI1-UP provides the same number of words but includes

The memory can be interleaved innK increments for faster operation. Interleaving causes consecutive bus addresses
to be located within alternate 16K memory blocks.
.
..
The chart below shows the various option descriptions associated with the 16K memory.
MFII-U

M8293 16K Unibus Timing Module

.G 114 Sense Inhibit Module
G235 X-Y Driver
H217D Stack Module ( 16 bits)
7009295 Backplane Assembly

)
MMI1-U Module Set

Includes all modules listed in MFll-U but does not include backplane
assembly

MFll-UP

M8293 16K Unibus Timing Module
G 114 Sense Inhibit Module
G235 X-Y Driver Module
H217C Staok Module (18 bits induding parity)
7009295 Backplane Assembly
M7259 Parity Control Module

MMll,UP Module Set

Includes all modules listed in MFl1~UP except M7259 Parity Control
Module and does not include backplane assembly

)

If a user has a 16K memory system and wishes to add another 16K, he merely specifies the appropriate module set
since the existing backplane assembly can hold 32K of memory.

)

The MFI1-U/UP Core Memory is explained in detail in theMF11-U!UPCore Memory System Maintenance Manual,
DEC-ll-HMFMA-C-D.
.
1.3_6 LA30 DECwriter
The LA30 DECwriter is a dot. matrix impact· printer and keyboard for use as a hard copy 1/0 terminal. It i~Cilpabh~
of printing a set of 64 ASCII characters at speeds up to 30 chftracters per Seconc;t C;>n asprocket.fel,l 9~ 718 in.
continuous form. Data entry is from a keyboard capable of generating either 97 or 128 characters.
The LA30 is available in two versions: parallel (LA3O-P) and seriaJ. (LA30·S), The serial version is nonpaHy used
with the PDP-1l/40 System in that it is interfaced to the Unibus via the DLll Asynchronous Une lnterface. The
.
.
DL11 is basic to the PDP.l1/40 System.
The LA30 DECwriter is covered in Chapter 3 and a detailed description is contained in the LA30 DECwriter

Maintenance Manual, DEC-00-LA30-DD.

)
1-9

1.3.7 DLll Asynchronous 'Line Interface
The DL1l Asynchronous Litle Interface provides an interface between a communications device, such as a serial
LA30 DECwriter or Teletype, and the PDP·ll/40 Unibus. Serial information read or written by the device is
assembled or disassembled by the control for parallel transfer to or from the Unibus. The control also formats the
data from the,Unibus so that it is in the format required by the device. The interface provides the flags that initiate
these data transfers and cause a priority interrupt to indicate the availability of the device.
The DL1l transfers data via processor DATI and DATOB bus cycles. Although a DATO can be used, normal
operation consists of a DATOB transfer because the device and the interface handle byte rather than word data. The
interface can acquire bus control through a BR and is normally set at the BR4 priority level. Because the DL1l
'
interface operates through an interrupt, no NPR hardware exists.
Five available DL1l interface options (DLll-A through DLll"E) pr9vide the flexibility needed to handle a variety
of terminals. For example, the user can select an option for interfacing a Teletype or display keyboard, for handling
EIA data, or for handling dataset devices. In addition, depending on the option used, the user has a choice of line
speeds, character size, stop-code length, and panty ..

)

The DL1l consists of a single quad module, which is, normally installed in the processor Small Peripheral Controller
(SPC) slot. This module contains address selection logic for decoding the incoming bus address, an interrupt control
for generating the interrupt, and receiver/transmitter logic that perform~ the'conversion and formatting functions.
A detailed description of the DL11 interface is presented in the DLll Asynchronous Line Interface Manual,
EK-DL11-TM-002.
1.3.8 Power System
NOTE
Two different power distribution systems are used in' the
PDP-l1/40; both are described in detail in Chapter 6. This
manual refers to these systems as early or older and recent or
newer models. This note applies to both CPU and expansion
'
boxes and cabinets.

)

The new power distribution ,is incorporated in PDP.ll/40 "
systems with serial number 6000 and greater.

)
The PDP-l1/40 power system consists of an 861 Power Controller, an H742 Power Supply, three H744 +5V
Regulators, two H745 - i 5V Regulators, and interconnection arid power distribution cabling. One H754 +20, - 5 Vdc
regulator may replace an H745 if the MF ll-U/UP Memory is installed.
The 861 Power Controller controls all ac power input to the system cabinet. The controller is equipped with a
circuit breaker for overload protection and a thermostat for excessive heat protection. The power controller provides
switched ac outputs (controlled) and unswitched ac OlJtputs (uncontrolled) which provide power for the entire
system cabinet and related peripherals.
The H742 Power Supply takesac input power from the 861 Power Controller, generates and distributes dc power
and control signals to the system, and provides ac power to the logic cooling fan and H744 and H745 regulators.
There are three control signals generated: a clock signal, a DC LO logic signal, and an AC LO logic signal. The clock
signal drives the processor real-time clock option (KWll-L or KWH-P) ifit is installed. The AC LO and DC LO
signals warn the processor of imminent power failure, allowing the processor time to perform a power-fail sequence.

1-10

)

The H744 and H745 regulators generate +5V and -15V outputs, respectively, which are distributed to the KDII-A
Processor and MF 11-L Memory backplanes and the KY Il-D console.
Expansion cabinets are similar to the PDP-l 1/40 cabinet, but can accept two H754 +20, - 5V regulators in place of
the two H745 -15V regulators, if required by the MFII-U complement.

1.4 APPLICABLE DOCUMENTATION
PDP-II documents related to the PDP-I 1/40 System are listed in Table 1-2 in two main categories: general
handbooks and PDP-ll/40 hardware manuals. Hardware manuals cover equipment specifically related to the
PDP-I 1/40 and have associated engineering drawings. General handbooks cover overall PDP-II system descriptions,
instruction set, addressing modes, basic logic modules, Unibus deSCription, and interfacing information. Also covered
is general software documentation for basic programs necessary to develop, load, and run programs. Both the
PDP-ll/40 hardware manuals and the general PDP-II handbooks must be used together for a complete
understanding of PDP-I 1/40 Systems.
,

)
Table 1-2
Applicable Documents
Title

)

Description

Associated
Drawing Set

PDP-I 1/40 Processor
Handbook DEC, 1972

N/A

A general PDP-ll/40 System handbook covering
system architecture, addressing modes, the instruction set, programming techniques, memory management, internal processor options, console operation, and system specifications.

PDP-II Peripherals
Handbook

N/A

A general peripheral interface handbook. The first
part is devoted to a discussion of the various
peripherals used with PDP-II Systems. The second
part provides detailed theory, flow, and logic
descriptions of the Unibus and external device
logic; methods of interface construction; and
examples of typical interfaces.

Logic Handbook
DEC, 1972

N/A

Presents functions and speCifications of the MSeries logic modules and accessories used in
PDP-Ii interfacing (includes other types of logic
produced by DEC but not used with the PDP-II).

PDP-II Paper-Tape
Software Programming
Handbook,
XPTSA-A-D

N/A

Detailed discussion of the PDP-II software system
used to load, dump, edit, assemble, and debug
PDP-II programs; input/output programming; and
the floating point and math package.

)

)
/

1-11

Table 1-2 (Cont)
Applicable Documents
Title

Associated
Drawing Set

Description

PDP-11/40, -11/35
(21 inch Chassis)
System Manual
EK-ll 040-TM-002

PDP-11/40 System

A general introduction to the basic PDP-ll/40
System including sections on installation, operation, and the instruction set. Also provides
detailed information, including maintenance, of
the system power supply.

KD 11-A Processor
Maintenance Manual,
EK-KD11A-MM-00l

PDP-11/40 System

Block diagram discussion, flow diagram discussion,
theory of operation, and maintenance for the
KD II-A Processor, KYll-D Programmer's
Console, KJII Stack Limit Register Option,
KWII-L Line Frequency Clock Option, and KMII
Maintenance Module Option.

MM11-S, MF11-L, MFI1-LP
Core Memory System,
EK-MM11S-TM-003

PDP-I 1/40 System

General description, detailed description, and
maintenance of the MFII-L, MF11-LP, and
MM11-S memories. (Note that MF11-L is the
memory system; MMll-L the basic core memory.)
The MF11-L consists of a MM11-L Core Memory
on a double system unit backplane.

MFII-U/UP Core Memory
System Maintenance Manual, DEC-11-HMFMA-C-D

MF11-U/UP

Contains a detailed description and maintenance
information for the MFll-U and -UP Memory
Systems. MF11-UP is a parity memory.

KE11-E and KE11-F Instruction Set Option Manual,
EK-KE11E:'TM-002

KEll-E Extended
Instruction Set
(EIS) Option and
KEll-F Floating
Instruction Set
(FIS) Option

Algorithms, data programming, theory of
operation, and maintenance for the KEII-E Extended Instruction Set (EIS) Option and the
KEI1-F Floating Instruction Set (FIS) Option.

KT11-D Memory Management Option Manual,
EK-KT1ID-TM-002

KT11·D Memory
Management

Operation, programming, and detailed theory of
operation for the KTll-D Memory Management
Option.

DLll Asynchronous Line
Interface Manual,
EK·DLl1-TM-002

PDP-11/40 System

IilStallation configuration, programming, and
theory of operation of the DLlI interface. Covers
DLlI-A through DLl1-E. The DLl1-A or C is
normally used as a control for the Teletype or the
LA30-S DECwriter but the DLlI can be used for a
variety of communications devices. The DLl1-C is
simply a more flexible version of the DLll-A in
that the DLlI-C features a variable character code
plus crystal and switch selectable baud rates.

861-A, B, C Power Controller Maintenance Manual,
DEC-00-H861A-A-D

N/A

Installation, theory of operation, and maintenance
of the 861-A, Band C Power Controllers.

1-12

)

Table 1-2 (Cont)
Applicable Documents
Associated
Drawing Set

Description

LA30 DECwriter Manual,
DEC-OO-LA30-DD

DEC-OO-LA30-DA

Presents a detailed discussion of the DECwriter
including installation, operation, principles of
operation, maintenance, troubleshooting, and engineering drawings.

LCll DECwriter System
Manual, DEC-II-HLCB-D

DEC-ll-HLCB-D

Provides general and detailed descriptions, programming, and operation for the LC11 DECwriter
interface. The LCl1 is used when an LA30-P
(parallel) DEC writer is used as a system input/
output device.

KLll Teletype Control
Manual, DEC-11-HR4C-D

DEC-I1-HR4C-D

Provides general and detailed descriptions, programming, adjustments, and maintenance for the
KLll Teletype Control that may be used instead
of the DLll control.

Automatic Send-Receive
Sets, Manual

Bulletin 273B,
two volumes,
Teletype Corp.

Describes operation and maintenance of the Model
33 ASR Teletype unit that can be used as an
input/output device with the PDP-ll/40 System.
Comparable manuals available for other Teletype
models.

Model 33 Page
Printer Set, Parts

Bulletin 1184B,
Teletype Corp.

Contains an illustrated parts breakdown to serve as
a guide for disassembly, reassembly, and parts
ordering for the Model 33 ASR Teletype unit.
Comparable manuals available for other Teletype
models.

Title

)

1.5 ENGINEERING DRAWINGS
A complete set of engineering drawings and module circuit schematics is provided with each PDP-ll/40 System.
These print sets are listed in Table 1-2 either under a Drawing Directory reference or as a second volume to the
maintenance manual. The engineering drawings support manual discussions and are often directly described therein.
The Drawing Director Index (DDI) provides a list of prints included in the set and includes drawing number, title,
and revision. An X in the column labeled CUSTOMER PRINT SET indicates each drawing that is prOVided for the
customer. The 1972 DEC Logic Handbook contains general logic symbols used on DEC drawings. A more detailed
discussion of drawing set conventions is contained in the KDll-A Processor Maintenance Manual,
EK-KD11A-MM-001 with this convention directly applicable to the PDP-ll/40 processor and processor options.
All DEC drawings are identified with a drawing identification code shown below:
D-CS-M7233-0-1

~~~!::

t--lt

s_iz_e_ _ _ _ _ _ _ _ _

t tt

:~~f.ct",ing

v",.tion

Module type, equipment type, or a
7-digit DEC part number.

1-13

Drawing Type Designations
CS:
BS:
BD:
FD:
DD:
MU:

AD:

Circuit schematic
mock schematic
Block diagram
Flow diagram
Drawing directory
Module utilization

UA:

WL:
PL:
AL:

Assembly drawing
Unit assembly
Wire list
Parts list
Accessory list

In addition to the basic drawing identification code, a drawing set/sheet code is also used to identify logic drawings.
This code is written in the title block and consists of three characters: two letters identify the equipment drawing
set; and a number identifies the sheet in that drawing set. For example, KT-3 indicates sheet 3 of the KTll-D
Memory Management Option drawing set.
Because of its multiple module configuration, the processor drawing set/sheet code is a little different. Only one
letter, the letter K, is used in the processor code along with two numbers. The first number indicates the module,
and the second number indicates the sheet. For example, K2-4 indicates sheet 4 of the processor U WORD Module
Drawing set. See Table 1-3 for a complete listing of drawing set/sheet code preflXes.

Table 1-3
Drawing Set/Sheet Code PrefIXes
Drawing Set

Module Number

Code Prefixes

KDll-A Processor Modules:
DATA PATHS
UWORD
IRDECODE
TIMING
STATUS

M7231
M7232
M7233
M7234
M7235

Kl
K2
K3
K4
K5

ltJII-A Stack Umit Register

M7237

KMII-A Maintenance Board

W130, W131

KYI1-D Console

)

KYD

DL11 Asynchronous Une Interface

M7800

KT11-D Memory Management

M7236

KEll-E Expanded Instruction Set

M7238

KEll-F Floating Instruction Set

M7239

)
1-14

CHAPTER 2
INSTALLATION

2.1 SCOPE

)

This chapter provides infonnation on PDP-ll/40 System site preparation, equipment installation, operation and
programming, and customer acceptance. Only installation of the basic PDP-ll/40 System and processor options is
included in this chapter. A section on installation of peripherals is not provided because of the modular and Unibus
concepts of the system. To install a peripheral, for example, it is usually only necessary to insert the interface
module(s) into the basic system mounting box and connect appropriate cabling between the interface and the
peripheral. Installation and maintenance of the peripheral itself is covered in associated manuals.

2.2 SITE PREPARATION
It is recommended that sufficient time be given to site planning and preparation with particular attention given to

the user's specific system configuration especially if a large number of peripherals are part of the system.

)

Two DEC documents will aid in proper site planning: the PDP-ll/lO, 40 Configuration Worksheet and the PDP-ll
Site Pre~aration Worksheet.
The Configuration Worksheet permits the user to layout the system prior to ordering so that he is aware of drawer
layout, cabinet layout, and Unibus interconnection. This ensures that the proper number of drawers and cabinets are
used and that Unibus length and loading is proper for the system.

)

The Site Preparation Worksheet permits the user to detennine the power requirements, environmental preparations,
and physical arrangement of his system. The worksheet provides data on operating environment, power
requirements, service and access requirements, and physical speCifications for the basic system and available
peripherals.
A final layout plan should be approved jointly by the user and DEC prior to delivery of equipment. It is
recommended that any modifications to the installation site be effected prior to shipment and installation of the
system.
DEC Sales Engineers and Field Service Engineers are available for consultation and planning regarding objectives,
course of action, and progress of the installation. It is recoinmended that a qualified DEC representative either install
the system, or at least be present during installation.
Adequate site planning and preparation can greatly simplify the installation process, resulting in a more efficient and
reliable installation. Infonnation in the follOWing paragraphs is provided primarily to pennit review of the site
planning.

)
2-1

2.2.1 Physical Dimensions
TIle overall dimensions and total weight of the particular PDP-I 1/40 as well as dimensions, weights, and cable
lengths of any optional cabinets and free-standing peripherals should be known prior to shipment of the equipment.

)

TIle route the equipment is to travel from the customer receiving area to the installation site should be studied.
Measurements of doors, passageways, etc., should be taken and submitted along with floor plans to the DEC Sales
Engineers and Field Service to ensure that the equipment is packed to suit the installation site facilities. Any
restrictions (such as bends or obstructions in hallways, etc.) should be reported to DEC.
Secondly, elevator limitations should be determined. If an elevator is to be used for transferring the PDP-l 1/40 and
its related equipment to the installation site, DEC should be notified of the size and gross weight limitations so that
the equipment can be packed accordingly.
TIlirdly, systeni operational requirements should be considered. Operational requirements determine the specific
location of the various options and free-standing peripherals of the system. Dimensions, weights, and cable lensths of
free-standing peripheral equipment must be determined prior to installation, preferably during site preparatjon and
planning. Note that peripheral cables must not exceed maximum specified lengths. Operational requirements that
should be considered are listed below:
a.

Ease of observation of input/output devices by operating personnel.

Adequate work area for installing tapes, access to console, etc.

Space availability for contemplated future expansion.

Proximity of the cabinets to peripherals.

Proximity of cabinets and peripherals to any humidity controlling or air conditioning equipment.

Finally, site space requirements should be determined by the specific system configuration to be installed and, when
applicable, provision for future expansion. To determine the exact area required for a specific configuration, a
machine-room flOOI plan layout can be helpful. When applicable, space should be provided in the machine room for
storage of tape reels, printer forms, card flies, etc. The integration of the work area with storage area can be
considered in relation to the work flow requirements between areas. In large installations where test equipment is
maintained, DEC recommends that the test equipment storage area be within or adjacent to the machine room.
2.2.2 Fire and Safety Precautions

)

The following fire and safety precautions are presented as an aid to providing an installation that affords adequate
operational safeguards for personnel and system components.
a.

If an overhead sprinkler system is used, a "dry pipe" system is recommended. This type of system, upon
detection of a fire, removes source power to the room and then opens a master valve to flil the room's
overhead sprinklers.

If the fire detection system is the type that shuts off the power to the installation, a battery-operated
emergency light source should be provided.

If an automatic carbon dioxide fire protection system is used, an alarm should sound prior to release of
the CO 2 to warn personnel within the installation.
.

If power connections are made beneath the floor of a raised-floor installation, waterproof electrical
receptacles and connections should be used.

An adequate earth ground connection should be prOvided for the protection of operating personnel.
2-2

)

2.2.3 Environmental Requirements
An ideal computer room environment has an air distribution system that provides cool, well-flitered, humidified air.
The room air pressure should be kept higher than that of adjacent areas to prevent dust inflitration.
2.2.3.1 Humidity and Temperature - The PDP-II /40 electronics are designed to operate in a temperature range of
from 500 p (l0°C) to I22°p (50°C) at a relative humidity of 20 to 95 percent without condensation. However,
typical system configurations that use I/O devices such as magnetic tape units, card readers, etc., require an
operational temperature range of from 60 0 p (l5°C) to 80 0 p (27°C) with 40 to 60 percent relative humidity.
Nominal operating conditions for a typical system configuration are a temperature of 700 p (20°C) and a relative
humidity of 45 percent.
2.2.3.2 Air Conditioning - When used, computer room air-conditioning equipment should conform to the
requirements of the "Standard for the Installation of Air Conditioning and Ventilating Systems (non-residential)",
N.P.P.A Number 90A; as well as the requirements of the "Standard for Electronic Computer Systems", N.P.P.A.
Number 75.

)

2.2.3.3 Acoustical Damping - Some peripheral devices (such as line printers and magnetic tape transports) are
quite noisy. In installations that use a group of high noise level devices, an acoustically damped ceiling reduces the
noise. Operator comfort and effiCiency is a major concern here.
2.2.3.4 Lighting - If cathode·ray tube (CRT) peripheral devices are part of the system, the illumination
surrounding these peripherals should be reduced to increase the visibility of the display.
2.2.3.5 Special Mounting Conditions --' If the PDP-l 1/40 is to be subjected to rolling, pitching, or vibration of the
mounting surface (e.g., aboard a ship), the cabinets should be securely anchored to the installation floor by
mounting bolts. Since such installations require modifications to the system cabinets, DEC must be notified upon
placement of the order so that necessary modifications can be made.
2.2.3.6 Static Electricity - Static electricity can be an annoyance to personnel and can, in extreme cases, affect the
operational characteristics of the PDP-ll /40 System and related peripherals. If carpeting is installed on the
installation room floor, it Should be of a type designed to minimize static electricity. Plooring consisting of metal
panels, or flooring with metal edges, should be adequately grounded.
2.2.4 Electrical Requirements

)

The PDP-II /40 can be operated from a nominal 11 5 or 230 Vac, 50/60 Hz power source. Line voltage should be
maintained within 10 percent of the nominal value and the 50/60 Hz line frequency should not vary more than 3
Hz. A PDP-ll/40 System with 16K of memory and standard peripherals requires approximately 690W of input
.
power (6A@ 115 Vac, 3A@ 230 Vac).
Primary power to the system should be provided on a line separate from lighting, air-conditioning, etc., so that
computer operation is not affected by voltage surges or fluctuations.
The PDP-ll /40 cabinet grounding point should be connected to the building power transformer ground or to the
building ground point. Any questions regarding power requirements and installation wiring should be directed to the
DEC Sales Engineer or Pield Service Engineer.
Primary power outlets at the installation site must be compatible with the PDP-ll/40 primary input connectors. The
input connectors provide power directly to the cabinet-mounted 861 Power Controller (one per cabinet) and each
model of the power controller uses a specific type of connector. Power controller models 86l-B and 86l-C are used
in the PDP-ll/40 System cabinets. Refer to Pigure 2-1 in the 86J-A, B, C Power Controller Maintenance Manual,
DEC-00-H861-A-A-D for complete connector information.

)
2-3

2.3 INSTALLATION PROCEDURES
The procedures presented in the following paragraphs are provided to assist in unpacking, inspecting and installing
the PDP-II /40 System and associated processor options.

CAUTION
Do not attempt to install the system until DEC has been
notified and a DEC Field Service Representative is present.

2.3.1 Unpacking
Before unpacking the equipment, check the shipment against the packing list. Ensure that the correct number of
packages. has been delivered and that each package contains all the items listed on the accompanying packing slip.
Also, make certain that all items on the accessories list in the Customer Acceptance Procedures have been included
in the shipment. Unpack the cabinets as described in the following procedure.

)
1.

Remove outer shipping container.

NOTE
The container may be either heavy corrugated cardboard or
plywood. In either case, remove all metal straps first, then
remove any fasteners and cleats securing the container to the
skid. If applicable, remove wood framing and supports from
around the cabinet perimeter.

Remove the polyethylene cover froin the cabinets.

Remove the tape or plastic shipping pins, as applicable, from the cabinet(s) rear access door(s).

Unbolt cabinet(s) from the shipping skid. The bolts are located on the lower supporting siderails, and are
exposed by opening the access door(s). Remove the bolts.

Raise the leveling feet above the level ofthe roll-around casters.

Use wood blocks and planks to form a ramp from the skid to the floor and carefully roll the cabinet
onto the floor.

Roll the system to the proper location for installation.

If applicable, repeat steps 1. through 7. for the expansion cabinets.

When the cabinets are oriented properly, follow the procedures in Paragraphs 2.3.2 and 2.3.3 to install
the cabinet(s).

)

)
24

2.3.2 Inspection
Mter. removing the equipment packing material, inspect the equipment, and report any damage to the local DEC
sales office. Inspect as follows:

)

Inspect external surfaces of the cabinets and related equipments for surface, bezel, 'switch, and light
damage, etc.

Remove the shipping bolts from the rear door, then open the rear door of the cabinet. Internally inspect
the cabinet for console, processor, and interconnecting cable damage; also inspect for loose mounting
rails, loose or broken modules, blower or fan damage, any loose nuts, bolts, screws, etc.

Inspect the wiring side of the logic panels for bent pins, broken wires, loose external components, and
. foreign material.
. '

Inspect the power supply for proper seating of fuses and power connections.

Inspect all peripheral equipment for internal and external damage. This includes inspection of magnetic
tape and DECtape transport heads, motors, paper-tape sprockets, etc.
CAUTION
Do not operate any peripheral device which employs motors,
tape heads, sprockets, etc., if they appear to have been
damaged in shipment.

2.3.3 Cabinet Installation
The PDP-ll/40 cabinets are provided with roll-around casters and adjustable leveling feet. It is not necessary to bolt
the cabinet to the mounting floor unless conditions indicate otherwise (e.g., shipboard installation). Cabinet
installation procedures follow.

)

NOTE
In multiple cabinet installation, receiving restrictions may
necessitate shipping cabinets individually or in pairs. In such
cases, the cabinets are connected at the installation site.

)

With the cabinets positioned in the room, install H952-GA Filler Strips between cabinet groups (filler
strips are shipped attached to the end of a cabinet group). Remove 4 bolts each from the front and rear
fIller strips. Butt the cabinet groups together while holding the filler strips inplace and rebolt through
both cabinets and the fIller strips. Do not tighten the bolts securely at this time.

Lower the leveling feet so that the caoinet(s) are not resting on the roll-around casters but are supported
on the leveling feet.

Use a spirit level to level all cabinets and ensure that all leveling feet are firm against the floor.

Tighten the bolts that secure the cabinet groups together and then recheck the cabinet leveling. Again
ensure that all leveling feet are planted firmly on the floor.

Remove the shipping bracket that secures the extendable BAll-FC Mounting Box in the cabinet.

)
2-5

2.3.4 AC Power Connections
A 3-wire cable is used to connect the site source power to the power controller in the H960-C cabinet. The cable is
connected at the factory for either 230V, 50 Hz or 115V, 60 Hz operation. All cabinets in a PDP-II /40 System
include a power controller and a single ac power cable; power is distributed within the cabinet from the power
con troller.

)

Proper connection of power is basic to system operation and personnel safety. Power cables must be connected to a
site power system that proVides ac power plus ground. The cabinets should be grounded to an earth ground, with
ground straps connecting all the cabinets to each other. In addition, the frame ground wire in each power cable
connects the cabinet ground system to the site power system ground.
Before connecting any power cables to the site source power, check all site wiring. Ensure that power receptacles of
the appropriate types have been provided for each cabinet, and that the receptacles are positioned close enough to
the cabinet positions to allow connecting the cables without stretching or crossing the cables. In particular, check
that the proper voltage levels are present and that the phase wires have been connected to the same pins in each
receptacle so that all cabinet power controllers receive the same voltage phase.

)

2.3.5 Intercabinet Connections
When a multi-cabinet system is assembled, three types of electrical connections must be made between cabinets (see
Paragraph 2.3.3 for mechanical connections). These connections are:
a.

Unibus connections - a BCII-A cable must connect the last system unit in a cabinet to the first system
unit in the next cabinet. The shortest possible length should be used to reduce loading.

Remote power connections - all cabinet power controllers are interconnected by a 3-wire control bus
that proVides for system turn-on and turn-off and emergency shut-off.

Ground strapping - the frame ground of the system is distributed through the cabinets by direct
electrical connections between the cabinet frames.

2.3.5.1 Unibus Connections - To connect the Unibus between the H960-C Cabinet and an H960-D Expansion
Cabinet, insert the BC 11-A cable in the rear system unit slot of the BA 11-FC Mounting Box of the H960-C Cabinet.
The cable then runs through a cable clamp in the upper left corner at the rear of the BAII-FC Mounting Box and is
passed under the power supply mounting rails into the next cabinet. In the H960-D Cabinet, the cable passes
through a similar cable clamp and is inserted in the appropriate slot of the first system unit of the mounting box.
The BAIl·FC is noted above as an example, other mounting boxes might be the last box.

)

2.3.5.2 Remote Power Connections - Each cabinet in the system has one 861 Power Controller. All controllers are
connected by a 3-wire bus that enables a remote turn-on and turn-off, and an emergency shut-off. There are three
Mate-N-Lok connectors on each power controller for the 3-wire bus. A cable is supplied with each cabinet to
connect the power control of that cabinet to the next cabinet. Because each 861 Power Controller must be capable
ofconnecting to the 861 Power Controllers in the preceding and following cabinets, two Mate-N-Lok connectors are
reserved for the intercabinet cables. The third connector is provided for connection to a remote on/off switch and a
thermal switch, or other emergency shut-off devices within the cabinet.
2.3.5.3 Ground Strapping - Electrical safety is provided by connecting all the cabinet frames to the ground level of
the site power system .. This is done by connecting a wire in each power cable between the frame and the power
system ground; this is not a load carrying wire, and is intended only as an emergency ground path. The green wire in
each power cable is the frame ground, while the white wire is the neutral, or return wire, that carries the load
current.

)
2-6

)

To improve the level of safety provided by the frame ground connections, all cabinet frames are connected by
braided copper straps of 4 AWG solid wire with crimp-on lugs, which are fastened to copper studs that are welded to
the frames (this also prevents the generation of ground loops between cabinets that are connected by signal-carrying
cables). The studs are welded to the bottom side rails of the cabinet frame, facing inward; the stud on the left side of
the cabinet is slightly forward of center while the stud on the right side is slightly to the rear.
The ground strap supplied with each cabinet is fastened to one stud, passed over the side rail of that cabinet and the
side rail of the adjacent cabinet, and fastened to the stud in that cabinet. The c-opper studs are threaded, and nuts are
supplied on the studs.
2.3.6 Remote Peripheral Interconnection
Installation instructions for remote peripherals, such as line printers, card readers, and magnetic tape units, are
covered in the appropriate peripheral maintenance manual. Normally, the peripheral itself is·a free-standing unit and
the peripheral controller is mounted in one of the system drawers. The controller and peripheral must be
interconnected, and the peripheral must also be connected to an ac power source.
In a basic PDP-II /40 System, there is a small peripheral controller mounting slot that houses the controller for the
system input/output device (LA30 DECwriter or Teletype unit). This device is characteristic of remote peripherals
installation.
When installing the system, it is necessary to interconnect the system and the input/output device (DECwriter or
Teletype) as described in the following steps:
1.

Place the free-standing LA30 DECwriter or Teletype in the desired position next to the system cabinet.

Run the control cable from the DECwriter or Teletype unit through the back of the system cabinet and
through the cable clamp at the rear of the mounting box. Note that because of the size of the control
cable connector one side of the cable clamp must first be loosened and moved aside before the
connector can be brought into the box.

Bring the cable connector into the mounting box and connect it to the receptacle on the input terminal
control (DLll, KLlI ,or LCU) mounted in the small peripheral controller slot of the processor.

Place the cable clamp moved in step 2. above over the cable and tighten.

Verify that the input terminal control module is pluggedsecurelyinto the small peripheral controller
slot.

Connect the power cable from the DECwriter or Teletype unit into one of the 861 Power Controller
power receptacles.

)

2.3.7 Installation Verification
Prior to turning power on, proper installation of all processor internal options and memory should be verified.
Although memory and processor options are installed in the system at the factory, installation should be verified at
the site.
Installation verification procedures for the available processor options are given in Table 2-1. Verification procedures
for core memory, as well as procedures for installing additional memory, are given in Table 2-2. A diagram of the
memory system unit is shown in Chapter 6 (Figure 6-4).

2-7

Table 2-1

Option Installation Verification
Option

K.E ll-E ExtendedlnstructiOri
Set (EIS) Option

Procedure
L Verify that KEl1·E moduleM7238 is installed in slot 02
(sections A-F) of processor backplane.

2. Ensure that jumper WI on print K3·8 of KDl1·A processpr
module M7233 (located in slot OS, sections A-F) has beim
removed.
"
'
,,
'
3. Ensure that the three over-the·backcables have been
connected to the 40"pin Berg connectors on the M7238
KEll-E module and the M7232 processor moduie (slot 03,
section A~D); These cables provide a required logic interco~nectonbetweeri the processor and the KE 11-E option.
KEll-F Floating Instruction
Set (PIS) Option ,

)

1. Verify that the KE 11·E' option has been installed. The KE 11-E
is a prerequisite for the KE 11· F.
2. Verify that KEll·F module M7239 is installed in slot 01
(secti9ns A-D) of processor backplane.
3. Ensure that the three jumpers on the KEI1-E M7238 module
have' been removed. These jumpers must be removed to allow
theKEI1-F option to execute floating-point instructions. The
jumpers are as follows:
Jumper
WI
W2
W3

Print
KE-2
KE-5
KE:9

)

Module
M7238
M7238
M7238

KTll-D Memory Management "
Option (requires theKJl1~A
installa tion procedure also)

1. Verify that KTlI-Drrio(lule M7236 is installed in slot 08
(sections A-F) ofprocessor backplane.

)

2;Verify that processor jumper changes have been ,made as
indicated below (these changes are detailed in the installation
seciionof the KT11 ,D option manual):
Verify that the following jumpers have been removed:
Jumper,
W9
W6
WS
WI
W2
W3
W4
W7
W8
2·8

Print
Kl~8

KI-8
Kl·S
KI-7
Kl·7
Kl·7
Kl·7
Kl·9
Kl~9

Module
M7231
M7231
M7231
M7231
M7231
M7231
M7231'
M7231
M7231

)

Table 2·1 (Cont)
Option Installation Verification·
Procedure

Option

Verify that the following jumpers have been· mo~ed in
accordance with notes on prints:
WI0
W2

KI·6
K4·4

M7231
M7234

Verify that the following components have been added:
C1l3
CIl4
KJll·A Stack Limit Register

)

K4-4
K4·4

M7234
M7234

1. Verify that KJIl·A module M7237 is installed in slot E03 of
the processor backplane.
2. Verify that the following processor jumpers have been moved
in accordance with notes on prints:
Jumper
W2*
WI
WI

)

Print
KI·7
K4-4
K5-4

Module
M7231
M7234
M7235

*Note that if the KT1I·D option is
present, jumper W2 of M7231 is
removed completely.
KWll·L Line Time Clock

Verify that KWll·L module M787 is installed in slot F03 of the
processor backplane. Verify that the backpanel wire between pin
F03R2 and F03V2 for BG6 H has been removed.

KMll·A Maintenance Console

This option consists of a double·length module (W130/W131)
that is plugged into slot FOI when used to monitorKDll·A
operation, alld slot EOI when used to monitor KT1I·D, KEll·E,
or KEII·F operation.
Note that this option is not installed in the system during normal
use.

)
2·9

Revision 1
lanuary1974

Table 2-2
Memory Verification or Installation
Procedure

Memory
MFII-L Core Memory
(basic to PDP-ll/40)

Verify proper address selection on jumpers on GllO Control &
Data Loops module.

Verify that modules are installed for basic 8K memory as follows:
Module
H214 Memory Stack
G231 Memory Drivers
G 110 Control & Data Loops

4a.

Slot/Sections
01/C-F
02/A-F
03/A-F

Verify Unibus interconnection to the KD11-A processor (M981)
and interconnection or termination to rest of system (M920 or
M930).

)

If older type system:
Verify that system unit power cable (D-IA-7009103-0-0) is
connected from the system unit to Mate-N-Lok receptacles of the
power distribution panel located on the BAI1-FC Mounting Box
(see Figure 6-10). Connector P I goes to 3; connector P2 goes to
4.

4b.

Ifnewer type system:
Verify that system unit power cable (D-IA-7009565) is connected
from the system unit to the power distributors: the - 15V
connector (I5 pin, 2 wire: blue and black) and the 6 pin signal
connector, to the first power distributor; the +5V connector (I5
pin) to the second power distributor.

MM II. L Core Memories
(additional memories
added toMFU-L
memories) .

Select proper address selection on jumpers on GIl 0 Control &
Data 'Loops module.

For 16K memory, insert modules as follows' in addition to the 8K
configuration described above:
Module
G231 Memory Drivers
G 110 Control & Data Loops
H214 Memory Stack

)

Slot/Sections
04/A-F
05/A-F
06/C-F

For 24K memory, insert modules as follows in addition to the
16K configuration described above:
Module
G231 Memory Drivers
GII0 Control & Data Loops
H214 Memory Stack

Slot/Sections
07/A-F
08/A-F
09/C-F

)
Revision 1
January 1974

2-10

Table 2-2 (Cont)
Memory Verification or Installation

)

Procedure

Memory
MFII-LCore Memory
(expansion units added
to basic PDP-I 1/40)

)

Insert the MFII-L system unit into the BAII-FC Mounting Box
using thumb screws provided.

Rearrange Unibus connections and termination using the M920
and M930, respectively. If memory is last unit in the mounting
box, use BC1I-A cable for interconnection to a next box,

Verify proper address selections on jumpers on G 110 Control &
Data Loops modules.

Insert modules according to locations noted. for MF Il-L Core
Memory (basic) and MMII-L Core Memories (additional).

Sa.

If older type unit:
A system unit power cable (D-IA-7009174-0-0) is used to connect
the backpanel of the additional MFII-L to the power distributor
panel's Mate-N-Lok receptacles. See Paragraph 6.4.7 for power
loading restrictions.

5b.

Same as Sa, except that the power cable is D-IA-7009560.

)

NOTE
If PDP-ll/20 Memory Systems are installed, they must
be housed in their own mounting boxes and powered by
their own power supplies.

MFII-U/UP

)

If newer type unit:

Install the MFII-U/UP backplane into the mounting box, using
the screws proVided.

Rearrange or install Unibus connections, as required.

Verify that address and interleaving jumpers are correct. Refer to
Chapter 2 of the MFII-U/UP Core Memory SystemMaintenance
Manual, DEC-1I-HMFMA-C-D, for details.

Insert modules as shown in Chapter 1 of the MFIl-U/UP Core
Memory System Maintenance Manual.

Sa.

If early type unit:
Install as explained in Paragraph 6.4.7 of this manual.

5b.

If later type unit:
Install power harness 7009535 between the MFII-U/UP and the
Power Distribution Panel. If. this memory is next to the
PDP-l 1/40 CPU, the harness should be plugged into the second
power distributor (not the same one as the CPU).
2-11

Memory

Table 2-2 (Cont)
or Installation

V~rification

Memory

Procedure

MFll-U/UP
(Cont)

Make sure that an H754 +20, - 5V regulator is installed in the
H742 Power Supply.

A complete checkout procedure is included in the MFll-UjUP
Core Memory System Maintenance Manual, Chapter 5.

2.3.8 Initial Power Turn-on
NOTE
Power distribution system differences are described in Chapter
6~ Refer to Figures 6-10 and 6-13 for plug locations.

)
Before turning power on, check the PDP-ll/40 System as described in the following steps:
1.

Ensure that all installation verification procedures (Paragraph 2.3.7) have been performed.

Before plugging in the system ac power cord, disconnect the following Mate-N-Lok connectors in the
basic H742 Power Supply wiring harness: PI through P7 (and P18 if a newer system). Note that
connectors P8 through PIS remain connected.

Turn off the circuit breaker on the 861 Power Controller. (If more than one cabinet exists, turn off all
861 Power Controllers.) Check all cable connections for proper seating.
CAUTION
Before connecting the 861 Power Controller to local power, be
certain that line frequency and voltage are compatible with
power controller requirements. Line frequency should be
50-60 Hz (±3) and line voltage should be 180-270V for the
861-BPower Controller and 90:"'135Vfor the 861-C Power
Controller.

Plug in the acpower cord, turn on the circuit breaker and check the dc voltages generated by the
regulators. These voltages can be checked at pins of connectors PI through f6 (and P18 if a newer
system). See Figures 6-11 and 6-14 for specific pin numbers. Check fan ac power on connector P7. If
any voltages are found to be incorrect, refer to power system maintenance in Chapter 7 and take
corrective action before continuing to the next step of this procedure.

Turn off the circuit breaker and reconnect all connectors.

Turn on circuit breaker and perform voltage regulator checks in accordance with Paragraph 7A.2.2.

Verify correct operation of the 861 Power Controller's REMOTE/OFF/LOCAL switch in accordance
with Paragraph 7A.2.3.

)

)
Revision 1
January 1974

2-12

2.4 INITIAL OPERATION AND PROGRAMMING
Once the system has been installed and power applied, preliminary operating and programming procedures should be
followed prior to using the system. Console operation, as well as the basic operating procedures noted in Chapter 3,
should be performed first. If the user is already familiar with console operation, then the basic operating procedures
given in Paragraph 3.6 may be performed immediately. These procedures are necessary to, but independent from,
the customer acceptance procedure noted in Paragraph 2.5.
Mter initial operation, the above procedures use a common set of system, peripheral, and individual instruction
diagnostics. These programs, listed in Table 7-3, define initial acceptance and operation. They also provide for a
continuing check on proper operation and permit analysis of system failures.
2.5 CUSTOMER ACCEPTANCE
Verify corfect system operation by performing the Customer Acceptance Procedures. The Customer Acceptance
Procedures document is shipped with the PDP-ll/40 System and lists all the tools, programs, and tests required to
certify system operation.

)

)
2-13

CHAPTER 3
SYSTEM OPERATION

3.1 SCOPE

)

This chapter provides the information necessary to operate and program the PDP-ll/40 System and associated
input/output terminal, (LA30 DECwriter or ASR 33 Teletype). The description is divided into five major
parts: programmer's console, DECwriter, Teletype, basic system operation, and basic system programming.
The description of controls and indicators for the consoles is in tabular form and provides the user with the type and
function of each operating switch and indicator. Operating controls for peripheral devices that are not part of the
basic machine are contained in the appropriate peripheral manual. Operation of the programmer's console, LA30
DECwriter, and ASR 33 Teletype is covered in Paragraphs 3.2, 3.3, and 3.4, respectively.

)

Basic step-by-step procedures for both manual and program operation are given in Paragraph 3.5. More specifically,
procedures for loading the bootstrap loader, absolute loader, and the maintenance loader are proVided in Paragraphs
3.5.3,3.5.4.1, and 3.5.4.2, respectively. Basic system programming is covered in Paragraph 3.6.

3.2 KYll-D PROGRAMMER'S CONSOLE
The KYll-D Programmer's Console (Figure 3-1) provides the PDP-ll/40 System with a necessary and useful
programmer's interface. Manual operation of the system is controlled by switches mounted on this console which is
the front panel of the basic mounting box. Visual displays indicate processor operation and the contents of the
address and data registers.

)

All register displays and switches, whether marked on the console panel or not, are numbered from right to left. The
numbers correspond to the power of two: 215 ••.••••••• 22 , 2 1 , 2°. Therefore, the most significant bit (MSB) is
at the left of each specific register or display, the least significant bit (LSB) is at the right. Whenever an indicator is
on, it denotes the presence of a binary 1 in the particular bit position. The alternate color coding on the console
identifies the different functions or segments of the binary word in octal format.

In addition to the alternate segment color coding, the DATA register contains an index mark that divides the
low-order byte (bits 7-0) from the high-order byte (bits 15-8). The high-order byte is divided into octal format by
two more index marks. No marks are required for the low-order byte because octal coding for this byte is identical
to the alternate segment color coding.
Figure 3-1 shows the location of all PDP-ll/40 console controls and indicators. Each indicator and associated
function is listed in Table 3-1. Each control and related function is listed in Table 3-2.

)
3-1

)
Figure 3-1a PDP-ll/40 Programmer's Console

)

Figure 3-1h PDP-ll/35 Programmer's Console

)
3-2

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ..------ --

"~,,

"--~.'

Table 3-1
PDP-ll/40 Console Indicators
Indicator
DATA

Type
16-bit display
MSB at left
Color-coded in 3-bit segments
for octal format
Byte division noted with additional indeXing for octal format
in upper byte

w
W

Function

Remarks

Displays the output of a processor data
multiplexer which gates informatiQn from a
variety of sources within the, processor.
Normal programming use results In the
following displays:

When console switches are used, information
shown on the DATA display is as follows:

HALT instruction has R(OO)
RESET instruction has R(OO)
WAIT instruction has R(IR)
SINGLE STEP and HALT switch has
Processor Status·(pS)
The display of the data multiplexer is
especially important when used in the single
clock mode. During this mode, the KMll
Maintenance Console is used to step through
a program a single microword at a time. In
this instance,the information in the DATA
display is the result of a single microword
and shown on the processor flow diagrams
(refer to KD JJ-A Processor Manual).

LOAD ADRS - the transferred Switch register address.
DEP - the Switch register data just deposited. Note that data and address are
correlated. The address is where this data
was stored;
EXAM - the information from the address
examined. Note address and data cor-relate.
HALT - displays
Status (PS) word.

the

current:!'Processor

When a programmed HALT instruction is
issued, bus control is transferred to the
console and processor register RO is displayed on the DATA display. This allows
program identification of halts.
During DMA operations, the processor is not
involved in· data transfer functions. Therefore, the data displayed in the DATA display
is not that of the last bus operation.

-----·--~l

Table 3-1 (Cont)
PDP-ll/40 Console Indicators
Indicator
ADDRESS

Type
18-bit display
MSB at left
Color-coded in 3-bit segments
for octal format

Function

Remarks

Displays the address in the Bus Address
register (BAR) of the processor. This varies
with an instruction execution but for a
HALT, WAIT, or single step operation, the
program counter is displayed between operations. The updated (or incremented) value
of the program counter is always displayed.

When console switches are used, information
shown on the ADDRESS display is as
follows:
LOAD ADRS - the transferred Switch register address.
DEP or EXAM - indicates the bus address
just deposited into or examined.

If the KT11-D Memory Management Option
is not included in: the system, the two most
significant bits (AI7, A16) are ordered
according to the lower 16 bits; they are set
only when bits A1S, A14, and A13 are all
set. Addresses between 160000 and 177777,
therefore, are translated to addresses between 760000 and 777777, respectively.

.(:...

During a programmed HALT or WAIT instruction, the ADDRESS displays the incremented address of the instruction. The BAR
is the instructibn location plus 2.
In single instruction mode, the next PC is
placed into the BAR and displayed in
ADDRESS between instructions.

If the KT11-D option is installed, the ADDRESS display usually displays a virtual
address with the KT11-D providing an offset
physical bus address (not displayed). During
console operations, however, the console
provides and displays a full· 18-bit physical
address.

During DMA operations, the processor is not
involved in the data transfer functions, and
the address displayed in the ADDRESS
display is not that of the last bus operation.
Within instructions, the display indicates
various processor bus addresses. These values
are apparent only in a maintenance mode,
using the KM II and single clocking.

'--.-/

.'-..--~

-----~----

.,-~'

',--,-

-------

'--'

Table 3-1 (Cont)
PDP-ll/40 Console Indicators
Indicator
RUN

Type
Single light

Function

Remarks

When the RUN indicator is on, the processor
clock is running and is operating on an
instruction or looping in console operation.

During normal machine operation, the RUN
light flickers on and off (indicated by a faint
glow).

When the RUN indicator is off, the microprogramming is not processing an instruction. The processor may be in control of the
bus and awaiting a response for a data
transfer; or the processor may have relinquished bus control for an NPR or BR
request.

A programmed RESET command turns off
the RUN light. This also occurs between
single clocks when the KMII Maintenance
Console is used.
For programmed HALT and WAIT instructions, the clock continues to run with the
processor looping in the microprogram. This
is also true for console operation from the
HALT switch.

PROC

Single light

When on, indicates that the processor is
controlling the Unibus as the master device.

When the PROC light is on and the RUN
light is off, the processor is waiting for data
from the bus.

BUS

Single light

When on, indicates that some device has
control of the Unibus. If the PROC indicator
is lighted, that device is the processor.

This display is useful for determining where
bus control is and that it is present.

CONSOLE

Single light

When on, indicates that the processor is in
the console mode (manual operation). Control switch activation is sensed and acted
upon.

NPRs and BRs are not serviced in the
console mode. Bus errors are also serviced
differently (see Table 3-2 for details).

USER

Single light

When on, indicates that the processor is in
the user mode and certain KTll-D restrictions on instruction operation and processor
status (PS) word loading exist. Refer to the
KT11-D option discussion in Chapter 4 of
this manual and the KT11~D manual.

Does not function unless the KT1I-D Memory Management Option has been installed
in the system.

Table 3-1 (Cont)
PDP-l1/40 Console Indicators
Indicator
VIRTUAL

Type
Single light

Function

Remarks

When on, indicates that a virtual address is
displayed in the ADDRESS display. This
virtual address is usually modified by the
KTll-D option to provide a different physical address for the Unibus. If the KTIl-D
option is installed, this display is usually
active during program operation. During
console operation, the console ADDRESS
display and Switch register both provide a
full 18-bit physical address. The VIRTUAL
light is off in this instance.

Does not function unless the KTlI-D Me1l).ory Management Option has been installed in
the system.

When VIRTUAL lightis off, it indicates that
the bus address indicated by the ADDRESS
display is the physical address.

"-../

"---'

'-...-/

,--,/

'~~

Table 3-2
PDP-11/40 Console Controls
Switch
OFF /POWER/LOCK

Type
3-position,
switch

key

Function
operated

Remarks

Provides system power control and lockout of console controls as follows:
OFF position - removes all power from
the system.

System not being used.

POWER position - applies primary
power to the system. All console controls
are fully operational when switch is in
this position.

Normal operation.

LOCK position - disables all console
(panel) controls except the Switch register key switches. This prevents inadvertent control switch operation from disturbing a running program.

System operating; console control disabled.

The data entered in the Switch register is
still available to the processor whenever
the program explicitly addresses the
Switch register (address 777570).

-------------------------------------------------------------~--

Table 3-2 (Cont)
PDP-ll/40 Console Controls
Switch
Switch register

Type

Function

18 key-type switches
Bit position of each switch is
labeled; MSB is at left.

Remarks

Provides a means of loading an address or
data word into the processor.

Color-coded in 3-bit segments
for octal format.

If the word in the Switch register represents an address, it can be loaded into the
ADDRESS register by depressing the
LOAD ADRS key.

Up position -logical one (or
on). Down position -logical
zero (or off).

If the word contains data, it is loaded
into the address specified by the ADDRESS register by lifting the DEP key.
If the KT11-D Memory Management Option is used, bits 17 and 16 are directly
used as the physical bus address during
console operation.

If the KT11-D option is not installed, the
processor bus address bits 17 and 16 are
set if Switch register bits 15, 14, and 13
are all set. Bits 17 and 16 of the Switch
register have no effect.
The contents of the Switch register may
be used by the processor any time the
program explicitly addresses the register
at address 777570. This address can only
be used by the processor.

,-----,'

'--.-"

''-..-/

Table 3-2 (Cont)
PDP-ll/40 Console Controls
Switch
LOADADRS

Type
Momentary key-type switch
Depress to activate

Function
The LOAD ADRS switch transfers the
contents of the Switch register to the Bus
Address register (BAR) through a temporary location R(ADRSC) within the processor. This bus address, displayed in
ADDRESS, provides an address for the
console functions of EXAM, DEP, and
START.

Remarks
The address is loaded into a temporary
location which is not modified during
program execution. To restart a program
at a previously speCified address, it is only
necessary to depress the START switch.
NOTE
Consecutive examine or deposit
functions increment the value of
the loaded address both in the BAR
and in R(ADRSC).

Console operations are word-ordered
operations. If an odd bus address (bit 00
enabled) is used, the odd address is stored
in the Bus Address register and the
temporary location. Examine or deposit
operations on this address will be treated
as word operations (bit 00 is ignored).

Table 3-2 (Cont)
PDr-11/40 Console Controls
Switch
EXAM

Type
Momentary key-type switch
Depress to activate

Function

Remarks

The EXAM switch uses the contents of
R(ADRSC) as a bus address; the contents
of this bus address is displayed in DATA,
the bus address is displayed in ADDRESS.

If an odd address is examined, bit 00 is
ignored. Fot example, if address 1001 is
examined, the address 1000 is displayed
in ADDRESS. Byte data for location
1001 is located in DATA (bits 15-08).

A LOAD ADRS operation usually preestablishes the initial R(ADRSC) address;
sequential examines automatically update
R(ADRSC).

An EXAM operation that references a
non-existent address causes a time out (with
no TRAP) and the Switch register address
(777570) is displayed in DATA.

If the EXAM switch is depressed twice in
succession, the contents of R(ADRSC) is
word incremented and the next sequential bus address is examined. This action
is repeated each time EXAM is depressed
proVided no other switch is used between
these steps. When the LOAD ADRS or
DEP switch is depressed, it destroys the
incrementing sequence. The next time
EXAM is used, it displays the current
address rather than the next sequential
address.

'-f
......
o

'-....../

'---./

-----./

.....--'

'------'

''-"

Table 3-2 (Cont)
PDP-ll/40 Console Controls
Switch
CONT

Type
Momentary key-type switch
Depress to activate

Function

Remarks

Causes the processor to continue operation from the point at which it had
stopped.

If program stops, depressing CONT provides a restart without power clear.
Because the restart occurs through the
service portion of machine operation, any
outstanding BRs may be serviced before
program operation.

If the EN,AaLE/HALT switch is in the
ENABLE mode, CONT returns bus control from the console to the processor
and continues program operation.

'-f
.....

If the ENABLE/HALT switch is set to
HALT, depressing the CONT key causes
the processor to perform a single instruction. Control is returned to the console
after each instruction, permitting a program to be stepped through one instruction at a time. ~Rs and interrupts are
serviced in this mode of operation.

__ ______ - ___1

Table 3-2 (Cont)
PDP-ll/40 Console Controls
Switch
ENABLE/HALT

Remarks

Type

Function

2-position, key-type switch

Allows either the program or the console
to control processor operation.
ENABLE position - permits the system
to run in a normal manner. No console
control requests are made.

Continuous program control requires the
ENABLE mode.

HALT position - halts the processor
after the next instruction or outstanding
TRAP sequences, and before Unibus Bus
Requests service, and passes control to
the console.

The HALT mode is used to interrupt
program control, perform single instruction operation, or clear the system.

The HALT mode is used with the CONT
switch to step the machine through programs one instruction at a time.

w
......

When the START switch is activated in
the HALT mode, a system clear is effected without program start. This mode
of operation is useful for clearing conditions in the system that might prevent
proper operation. When the START
switch is activated in the ENABLE mode,
it provides a system clear with a program
start.

~--

''----'-

'-...-./

----../

Table 3-2 (Cont)
PDP-) 1/40 Console Controls
Switch
START

Type
Momentary key-type switch
Depress to activate initialize,
release to have START function occur.

Function
Depressing the START switch provides a
sy stem clear (initialize). When the
ENABLE/HALT switch is set to HALT,
the processor does not start.
When ENABLE/HALT is set to ENABLE,
releasing START begins processor operation. The starting address is that of the
last console operation determined by
R(ADRSC). Usually, this temporary location is loaded from the Switch register by
a LOAD ADRS operation.

.....
w

If the program stops at any time, it can
be restarted at its original location by the
START switch; the value of R(ADRSC)
remains unchanged.
Use of the START switch in the HALT
mode provides for a system clear. This
mode of operation is useful for clearing
conditions that might prevent proper
operation.

Remarks

Table 3-2 (Cont)
PDP-l1/40 Console Controls
Switch
DEP

Type
Momentary key-type switch
Uft to activate

Function

Remarks

The DEP switch uses the contents of
R(ADRSC) as a bus address. The contents
of the Switch register are transferred to
this location. After use, the data appears
on the DATA display and the address is
on the ADDRESS display.

If an attempt is made to deposit an odd
address, bit 00 is ignored and a word
deposit occurs.

A LOAD ADRS operation usually preestablishes the initial address; sequential
DEP operations automatically update
R(ADRSC).
If the DEPswitch is raised twice in
succession, the contents of the Switch
register is deposited in the next sequential
bus address location. This action is repeated each time DEP is raised provided
no other switch is used between these
steps. Whenever the LOAD ADRS or
EXAM switch is depressed, it destroys the
incrementing process. The next time DEP
is used, it deposits the current address
rather than the next sequential address.

......
.j::.

',-_./

'~'

'--/

'---../

A deposit operation that references a
non-existent address causes a time out
(with no TRAP). No error message is
visible from the console for a deposit to a
non-existent address. An immediate verification by an examine operation, however, would result in the display of the
Switch register address in the DATA
display.

,-J

)

3.3 DECwriter
The LA30 DECwriter is an input/output device that can be used with the PDP-ll/40 System. Data can be entered
into the processor via the keyboard or data from the processor can be printed out by the DECwriter under program
control. Controls and indicators for the serial version LA30 DECwriter are shown in Figures 3-2 and 3-3 and listed in
Table 3-3. The serial version of theLA30, the LA30-S, would normally be used with the PDP-ll/40 in that it is
compatible with the DL11 input terminal control and the DL11 is part of the PDP-ll /40 basic configuration. The
LCll is compatible with .the parallel version of the LA30, the LA30-P. Further detailed operating information is
contained in the LA30 DECwriter Manual (DEC-00-LA30-DD) and in the Len DECwriter System Manual
(DEC-II-HLCB-D).

Table 3~3
LA30 Controls and Indicators
Index

)

. Function

Con trol/Indicator

READY

Lamp - Indicates power up on printer electronics
and that the DECwriter is READY for use.
Indicates an interrupt is enabled by keyboard
electronics, if INT bit is set by software.

LOCAL LINE FEED

Switch - When depressed, causes a local line feed
to be applied to the printer without a code being
sent out to the computer. This control will also
disrupt printing, but no characters will be lost.

MODE LOCAL LINE

2-Position Switch - Selects either local or on-line
operation.

BAUD RATE, 110, 150,300

3-Position Switch - Selects the baud rate clock
frequencies for 110, 150, and 300 baud.

MOTOR POWER

Breaker (CB2) - Applies power to printer stepping
motor electronics.

ACJ,>OWER

Breaker (CB1) - Applies ac power to the unit
power supply.

3.4 TELETYPE
The ASR 33 Telety~e unit is an input/output device that can be usedwith the PDP-ll/40 System. Data can be
entered into the processor via the keyboard or through a paper-tape reader. The Teletype can also be operated
off-line to punch paper tapes. Controls for the ASR 33 Teletype are shown in Figure 3-4 and listed in Table 3-4.
Further detailed operating information is contained in the Teletype Corporation manuals listed in Table 1-20fthis
manual.

)
3-15

)
Figure 3-2 LA30-S Keyboard

)

Figure 3-3 LA30 Power Controls

3-16

)

Figure 3-4 Teletype Controls

)

Table 3-4
Teletype Controls
Control

Type

Function

Punch:
REL. pushbutton

Momentary switch,
depress to activate

Disengages the paper tape from the
punch to allow loading or removal of
tape.

B. SP. pushbutton

Momentary switch, depress to activate

Backspaces the paper tape by one
space each time the pushbutton is
depressed to allow manual correction
or rubout of character just punched.

ON pushbutton

2-position switch, connected to OFF pushbutton

When depressed, turns on the papertape punch and releases OFF switch.

OFF pushbutton

2-position switch, connected to ON pushbutton

When depressed, turns off the papertape punch and releases ON switch.

)

)
3-17

Remarks

Table 3-4 (Cont)
Teletype Controls
Control

Function

Remarks

Controls operation of the tape reader.

Used on-line

Type

Reader:
START/STOP/
FREE switch

3-position switch

START position - engages tape reader
which begins operation under program
control.
STOP position - engages reader mechanism but does not energize it. In
effect, tape is locked in the reader but
reading operation does not begin until
the switch is moved to START.
FREE position - disengages reader to
permit loading and urJoading of tape.
LINE/OFF/
LOCAL switch

3-position
rotary switch

Serves two functions: applies primary
power to Teletype and connects computer to Teletype.
LINE position - energizes Teletype
and connects it to the computer as an
input/output device. Signals from
either the Teletype reader or keyboard
can be used as an input while the
computer output can be used to control the keyboard or punch.
OFF position - deenergizes the Teletype by removing primary power.

)

LOCAL position - disconnects the
Teletype from the computer. The
Teletype can be used for punching or
reading tapes but all control is localized at the keyboard.
Keyboard

45 printing
characters
6 non-printing
characters
Typewriter-like
layout

Uses a typewriter-like keyboard to
print characters on paper, punch tape,
or input information into the computer.
Off-Line Operation (LOCAL) - When
tape reader and punch are off, prints
characters on paper.

)
3-18

Table 3-4 (Cont)
Teletype Controls
Control

Type

Keyboard (cont)

Function

Remarks

When punch is on, simultaneously
prints characters on paper and punches
. equivalent code into paper tape.
When reader is on, reads code from
punched paper tape and prints equivalent characters on paper.
On-Line Operation (LINE) - When
tape reader and punch are off, prints
characters on paper and sends equivalent signals to the computer.

)

When tape reader is on, reads code
from punched paper tape and sends
equivalent signals to computer. No
characters are printed.
When receiving signals from computer,
prints equivalent characters on paper
and punches tape if punch is on.

)

Cover Guard

Latch, push to
release

Used to hold paper tape in position
when using tape reader.

3.5 BASIC OPERATION

)

Many methods exist for storing, modifying, and retrieving information from the PDP-I 1/40 System. These methods
depend on the fonn of the information, time limitations, and the peripheral equipment connected to the processor.
The following procedures are basic to the use of the PDP-l1 /40 System. Although they may be used less frequently
as the programming and use of the system become more sophisticated, they are valuable in preparing the initial
programs and in learning the function of system input and output transfers. For an understanding of the various
operational controls and indicators, refer to Paragraphs 3.2 through 3.4. Basic programming techniques are given in
Paragraph 3.6.
Operating procedures are separated into the following categories:

)

Power on - Paragraph 3.5.1

Basic console control- Paragraph 3.5.2

Manual program loading.-r Paragraph 3.5.3

Autolllatic program loading - Paragraph 3.5.4

Running programs -'- Paragraph 3.5.5

3-19

3.5.1 Power On
When the programmer's console OFF/POWER/LOCK switch is turned from OFF to POWER, the system is
initialized (zeroed). A time delay allows sufficient time for voltages to logic units (especially memory elements) to
stabilize.
The power-up initialization logic directly sets the microprogram control to a sequence of controlled events
determined by the setting of the ENABLE/HALT switch. If the console ENABLE/HALT switch is set to ENABLE
when power is turned on, the processor executes a power-up microprogram sequence with the power-up vector
address determined by jumpers on the Status module (M7235) of the KDll-A Processor. A new Processor Status
(PS) word and Program Counter (PC) are unstacked from the vector address, and vector address plus two,
respectively.
Program operation begins with an entrance to the FETCH portion of the microflow with the new PC used to obtain
the first instruction. Note that the processor status module jumpers are initially set at octal location 24. This
location can be changed to accommodate system requirements.
If the console ENABLE/HALT switch is set to HALT when power is turned on, the processor microflow is directly
set to the console microloop. The machine awaits the activation of a console control switch.

)

The LOCK position of the programmer's console OFF/POWER/LOCK switch provides for program operation with
the console control switches disabled. However, the console Switch register may still be accessed.
3.5.2 Basic Console Control
Two major areas of control exist: control influenced by the ENABLE/HALT switch, which selects either program
or console control; and control by the switches and sequences used for loading data manually into the processor.

)

3.5.2.1 ENABLE/HALT Switch - When the processor has control (ENABLE/HALT in ENABLE), either the
START or CaNT switch causes the program to run. The START switch initializes the system with a clear signal and
begins operation at a specific address determined by the last console operation (usually LOAD ADRS). The CaNT
switch merely releases console control, and the program continues at the existing Program Counter (PC).
When the ENABLE/HALT switch is set to HALT, the console obtains control. The LOAD ADRS, EXAM, and DEP
switches can be used. The CaNT switch can now cause the processor to step through the program a single
instruction at a time.
3.5.2.2 Loading Data Manually - Whenever data is manually loaded into a computer, it is desirable to have the
address increment automatically upon each deposit. Thus, the user can set a starting address and continue to store
data in sequential memory locations providing only new data for each location. The programmer's cohsolelogic also
permits the user to immediately examine the data just deposited without re-addressing, to re-deposit if necessary,
and to continue with automatic incrementation. These sequences are associated with the functioning of the DEP and
EXAM switches.

)

The address in the ADDRESS register, and R(ADRSC), does not increment the first time EXAM or DEP is used after
a HALT or LOAD ADRS. It does not increment if DEP is used immediately after EXAM or if EXAM is used
immediately after DEP. It does increment if a DEP is used immediately after a DEP, Or if an EXAM is used
immediately after an EXAM. This increment is a word increment as the console is word oriented. Thus, the user can
look at a location, change it, deposit the changed data, and then reexamine it without having to load an address each
time.
Incrementation is on even boundaries for all addresses except the addresses specifically designated for the processor
internal registers, which are incremented by 1.

3-20

)

For example, to alter several successive locations, the following steps are performed:

)

LOAD ADRS (starting location)

EXAM (no increment -looks at starting location)

DEP (no increment -loads starting location)

EXAM (no increment - checks previous deposit)

EXAM (increment -looks at next location)

DEP (no increment -loads second location)

EXAM (no increment - checks previous deposit)

EXAM (increment -looks at third location)

If the user desires to take advantage of automatic address incrementation for examining or loading data, the
following steps can be used to load data into sequential locations:
1.

LOAD ADRS (starting location)

DEP (no increment -loads starting location)

DEP (increment -loads second location)

DEP (increment -loads third location

DEP (increment -loads fourth location)
etc.

The same procedure can be used for examining data in sequential memory locations.
3.5.3 Manual Program Loading (Bootstrap Loader)
A primary manual use of the programmer's console is to store the bootstrap loader in the core memory. (Programs
and data can be stored or modified by manual use of the programmer's console.) The bootstrap loader
(DEC-II-LlPA-LA) is a minimal instruction program that can automatically load programs into core memory from a
paper tape punched in a special bootstrap format. One of these programs, after being stored, can in turn load any
binary format tape into the computer. (An explanation of the number designations used for DEC programs is given
in Table 3-5.)
The sequence for loading the computer is shown in Figure 3-5, with programs noted as follows:
a.

Bootstrap loader (DEC-II-LlPA-LA) - manually loaded by console switches; provides for automatic
loading of programs punched in a special format.

Absolute loader - punched in special format; loaded by bootstrap loader; provides for automatic loading
of programs punched in binary format.

Selected program - punched in binary format; loaded automatically by absolute loader.

3-21

Revision 1
January 1974

Table 3·5
Program Identification Codes

COMPUTER
PRODUCT
\

IDENTIFICATION
~ ;DISTRIBUTION

" DEC·l1·L1PA·LA
t--'--. .-"-.

Format:

• • HH H

Notes:

Product Code

2 3456 78
MAINDEC
DEC

maintenance library products
programming library products

Computer Series

PDP·1i Computer Systems

Major Category

Loader

Minor Category
(sequential numbers)

1
2

Option Category
(hardware required
to use software)

P
H

K
M

= first in a series of programs
second in series, etc.

paper tape system
high·speed reader and/or punch
Teletype keyboard only
magtape

Revision Category
(sequential letters)

A
B
C

= basic program
first revision
second revision, etc.

Distribution Method

L
P

listing
= paper tape

Distribution Mode

A
B

a
Example:

DEC·ll·L2PB·PO

)

ASCII
binary (absolute)
other (bootstrap binary)

Indicates a PDP-II programming library product,
second in a series of loaders, requiring a paper tape
system to use, the first revision to the program, sup·
plied as a paper tape in bootstrap binary format.

)

)
3·22

USE ABSOLUTE
LOADER TO
LOAD PROGRAM

)
USE
MAINTENANCE
LOADER TO
LOAD PROGRAM

USE BOOTSTRAP
TO LOAD
ABSOLUTE OR
MAINTENANCE

~---~

LOAD BOOT
LOADER
PROGRAM
11-1023

Figure 3-5 Flowchart of Procedure for Loading and Running Programs

)
To eliminate the necessity of more than one bootstrap loader, the bootstrap loader instructions contain two
variables (x and y) to provide compatibility with various memory configurations and reading devices. These variables
are listed in Table 3-6. A complete explanation of the bootstrap loader program is given in Chapter 5 of the PDP-}}
Paper Tape Software Programming Handbook (DEC-ll-XPTSA-A-D); further information may be found in the
program listing, DEC-ll-LlPA-LA.

)
3-23

Table 3-6
Bootstrap Loader
(DEC-ll-LlPA-LA)

Bootstrap loader should be toggled into highest core memory bank.
Address

Instruction

xx7744

016701

xx7746

000026

xx7750

012702

xx7752

000352

xx7754

005211

xx7756

105711

xx7760

100376

xx7762

116162

xx7764

000002

xx7766

xx7400

xx7770

005267

xx7772

177756

xx7774

000765

xx7776

yyyyyy

)

xx represents highest available memory bank. First location of the loader is one of the following, depending
on memory size; xx in all subsequent locations is the same as the first.
Address

Memory Bank

Memory Size
8K

037744
077744

16K

137744

24K

157744

28K

)

Contents of address xx7776 (yyyyyy) should contain device status register address of paper-tape reader to be
used when loading the bootstrap formatted tape. Addresses are:
Teletype Paper-Tape Reader

177560

High-Speed Paper-Tape Reader

177550

)
3-24

)

TIle following procedure is used to manually load the BOOT bootstrap loader program (DEC-ll-LlPA-LA):
1.

Set ENABLE/HALT switch to HALT to give bus control to the console when powering up.

Turn OFF/POWER/LOCK switch to POWER position. This energizes the programmer's console.

Enter starting address of bootstrap loader (Table 3-6) into Switch register. Make certain that the correct
xx value is used (037744 for SK memory, 077744 for 16K memory, 137744 for 24K memory, etc.).

Depress LOAD ADRS switch. The address set in the Switch register is shown on the ADDRESS display,

Enter starting address contents (016701) into Switch register.

Lift DEP switch. The contents just entered in the Switch register is displayed in the DATA display.

Enter contents of next address into Switch register.

)

It is not necessary to load addresses after the starting address
has been loaded because the address is automatically
incremented by two each time DEP is used consecutively.

Lift DEP switch.

Repeat steps 7 and S above for each location of the bootstrap loader. When loading the contents of
address xx7766, make certain that the correct x value is used. When loading the contents of the last
address, make certain that the correct y value is used.

10.

The bootstrap loader program is now loaded in memory locations xx7744 through xx7776 and can be
used to automatically load other programs into memory.

11.

Correct program entry can be verified by examining the addresses between xx7744 and xx7776. This is
accomplished by setting the starting address into the Switch register, depressing the LOAD ADRS switch
and depressing the EXAM switch. The contents of the starting address are shown in the DATA display.
Each time the EXAM is again depressed, the address is automatically incremented by two and the
corresponding contents displayed.

12.

Step 11 alone (verification) may be sufficient if the bootstrap loader program has already been loaded
into the system. The program is stored in the last portion of available memory so that it tends to survive
program operation and is available for reloading programs. If the program is not in tact, load according
to the above procedure, beginning with step 1.

)

3.5.4 Automatic Program Loading
Information can be stored or modified in the computer automatically only if a program capable of performing these
functions has previously been stored in the core memory. For example, haVing the bootstrap loader stored in the
computer enables the user to operate any program that has been punched in the special tape format required by the
bootstrap loader. Typical programs of this type include the absolute loader, the absolute dump, and the teleprinter
dump.

3-25

The bootstrap loader is limited because of the special tape format; anotherloader is used to load any binary format
tape into the computer. This is the absolute loader (DEC~l1-LlPC-PO), which is loaded into the computer by the
bootstrap loader. Once the absolute loader is in memory, any binary tape program (such as PAL III assembler,
symbolic editor, input/output service routines, diagnostics, mathematical routines, etc.) may be automatically
loaded.
The following paragraphs give procedures for loading the absolute loader, and for using the absolute loader to store
other programs. A complete description of the absolute loader program is given in Chapter 5 of the PDP-ll Paper
Tape Software Programming Handbook, DEC-ll-XPTSA-A-D; refer also to the program listing, DEC-II-L2PC-LA.
3.5.4.1 Loading Absolute Loader - The following procedure is used for automatically loading the absolute loader
program (DEC-II-LlPC-PO):
1.

Set ENABLE/HALT switch to HALT.

Make certain that the bootstrap loader has been stored in core memory (paragraph 3.5.3, step 11).

Enter starting address of bootstrap loader into Switch register. The starting address is xx7744 (037744
for 8K memory, 077744 for 16K memory, 137744 for 24Kmemory, etc.).

Depress LOAD ADRS switch. The address set in the Switch register is displayed in ADDRESS register
indicators.

Place the input/output device (LA30 DECwriter or Teletype unit) on-line (connected to the computer).
NOTE
If some other reading device (such as the high-speed paper-tape
reader) is used, ensure that the y value in bootstrap loader
address xx7776 corresponds to the device as described in
Table 3-6.

Place the absolute loader tape in the reader. Make certain that the special leader (a sequence of 351
punches) is under the reader station. Blank leader does not work.

Set ENABLE/HALT to ENABLE.

Depress START switch. The tape is now read into the computer which halts when the entire program is
loaded.

When the tape is completely loaded, the DATA display lights may be in any configuration. The main
reason for this is that no checksum capability exists in the bootstrap loader.

)

Any PDP-ll program punched in binary format may be loaded automatically by using the absolute loader. The
absolute loader can be set up to select either an absolute or relocatable code. If a relocatable code is selected, the
user may specify that the relocatable· code start at a specific address or that the code start loading at the point the
previous load stopped. The absolute loader also provides a checksum test to ensure accurate loading. Although the
computer normally stops when the binary tape is loaded, instructions on the tape itself may cause the computer to
begin execution of the program immediately after loading is finished .. This action is beyond the control of the user
because it is a part of the program on certain binary tapes.

)
3-26

The following procedure is used for automatic loading of binary tapes into the computer using the absolute loader:
1.

Make certain thatthe absolute loader program is stored in core memory (paragraph 3.5.4.1).

Set ENABLE/HALT switch to HALT.

Enter starting address of absolute loader into Switch register. The starting address is xx7500 (037500 for
8K memory, On500 for 16K memory, 137500 for 24K memory, etc.).

Depress LOAD ADRS switch. The starting address of the absolute loader is now displayed in ADDRESS
register indicators.

Select the type of load desired by setting the Switch register as speCified in Table 3-7.

Make certain that input/output device (Teletype unit or LA30 DECwriter) is on-line.
NOTE
The reading device may be changed at any time by the user
without reloading the absolute loader. If a reader is to be
changed, simply replace the contents of address xx7776 with
the appropriate device status address (y value in Table 3-6).

)

Load desired binary tape into reader by placing leader under the reader station.

Set ENABLE/HALT switch to ENABLE.

Depress START switch. This begins the binary tape load.

10.

If the binary tape contains a transfer address instruction, the computer begins execution of the program
as soon as loading is complete.

11.

The computer stops when either loading is complete or there is a checksum error.
a.

Loading complete - the low-order (right-hand) byte displayed in the DATA indicators is zero.
Additional binary tapes may be loaded by repeating steps 5 through 7 above and depressing the
CONT switch.

Checksum error - the low-order byte displayed in the DATA indicators is not zero, thereby
indicating a checksum error has occurred in the previous block of data. In this case, reposition the
tape in front of the error-producing block and depress the CONT switch.

)

Table 3-7
Binary Tape Load Selection
(using Absolute Loader)
Type of Load

)

Switch Register Settings
Bits 15-01
Bit 00
Not applicable

Normal (absolute)
Relocatable (continue where left off)
Relocatable (load at specified address)

o
Offset from tape origin

3-27

o
1
1

3.5.4.2 Loading Maintenance Loader - The maintenance loader program, MAINDEC-ll-D9EA, provides an
alternate method of loading diagnostic programs that can be used if the absolute loader fails to function because of a
hardware failure. This loader should only be used to load diagnostic programs if the absolute loader malfunctions.
Use the following procedure to automatically load the maintenance loader:
1.

Set ENABLE/HALT switch to HALT and depress START to clear the system.

Make certain that the bootstrap loader has been stored in memory, starting at address 037744.
NOTE
The maintenance loader operates in the lowest 8K of memory.
If some other memory area must be used, several program
locations must be changed as listed in Table 3-8 after the
maintenance program is loaded.

)

Set Switch register to 037744 and depress LOAD ADRS.

Place the input/output (LA30 DECwriter or Teletype unit) on-line.

Place the maintenance loader tape in paper-tape reader.

Set ENABLE/HALT switch to ENABLE and depress START. The tape is read into memory and the
processor halts when the entire program has been loaded.
NOTE
If the maintenance loader was not loaded into the lowest 8K
of memory, make location changes at this time (Table 3-8).

)

Table 3-8
Relocation of Memory Contents
Move Contents of

xx7502
xx7510
xx7542
xx7566
xx7624
xx7674
Where xx equals:

)

xx7470
xx7474
xx7475
xx7475
xx7776
xx7474
03 for 8K memory
07 for 16K memory
13 for 24K memory

)
3-28

3.5.5 Running Programs
When running any program, the program must first be loaded into the core memory either manually or via the
automatic loading programs (bootstrap loader or absolute loader). Once the program is in storage, it can be run at
any time by loading the starting address of the program (refer to appropriate program documentation) into the
Switch register, depressing the LOAD ADRS switch, and then depressing the START switch. The user also must
make certain that the ENABLE/HALT switch is in ENABLE and that the appropriate external devices are on-line
(connected to the computer).
The program can be manually stopped at any time by setting the ENABLE/HALT switch to HALT. It can be
restarted from that point by returning the ENABLE/HALT switch to ENABLE and depressing the CONTswitch. It
can be started anew by reloading the starting address and depressing the START switch.
A program can be altered during operation, or new data introduced, through the Switch register. This console
register has a bus address that the processor can reference in its instruction sequence. The information transferred
may be treated as data or used to alter program flow.

)

Because of the speed of the computer, console indicators are of limited value while the computer is running. Console
indicators are used primarily during manual operation, single instruction operation, or during the maintenance mode.
During manual operation, the console indicators reflect the console operations of LOAD ADRS, EXAM, and DEP.
During maintenance operations, the console indicators display various data functions of the processor as the
maintenance module is used to step through the program a microword at a time. Use of the maintenance module is
described in the KDII-A Processor Maintenance Manual, EK-KDIIA-MM-OOI.

3.6 BASIC PROGRAMMING

)

To produce programs that fully utilize the power and flexibility of the PDP·1I/40, it is necessary for the user to first
become familiar with various programming techniques that are part of the basic design philosophy of the PDP-l 1/40
System. These techniques (such as use of stacks, subroutine linkage, interrupt nesting, reentrant and recursive
programming, etc.) are covered in the PDP-ll/40 Processor Handbook, which also provides a detailed discussion of
the instruction set.
In addition to the general programming information given in the PDP-ll/40 Processor Handbook, the user should be
familiar with console operation (paragraph 3.2) and with the basic and extended PDP·1I/40 instruction sets
described in Chapter 4.

)

For those users already familiar with PDP-1I/20 system programming, the primary programming differences
between the PDP-ll/20 and PDP-1l/40 Systems are listed in Table 3-9. With this table, the experienced user can
immediately begin to program the PDP-l 1/40 System.
Basically, the PDP-ll/40 offers increased flexibility and speed. The basic system (without options) has five more
programming instructions than the PDP·11/20. These instructions are: eXclusive OR (XOR), Subtract One and
Branch (SOB), ReTurn from inTerrupt (RTT), Sign eXTend (SXT), and MARK (MARK). System flexibility is
increased even more if the KT11·D Memory Management Option and the KEll Extended Instruction Set (EIS) and
Floating Instruction Set (FIS) Options are installed.

)
3-29

Table 3-9
PDP-l1 Programming Comparison
PDP-ll/40

PDP-l1/20
JMP/JSR (R)+ uses (REG)+2 as address

JMP/JSR (R)+ uses (REG) before autoincrement as address. All autoincrements are now
post autoincrements.

All REG 6 (SP) autodecrement references can
cause overflow. Address modes 4 and 5, JSR
and traps are tested.

Address modes 1, 2,4, and 6, JSR and traps are
tested except that nonaltering (DATIs) references to stack data are always allowed.

No red zone on stack overflow.

Red zone trap occurs if stack is 16 words below
boundary. This trap saves PC+2 and PS on new
stack at locations 2 and O.

SWAB instruction does not affect V.

SWAB instruction clears V.

Program HALT displays PC of HALT instruction in ADDRESS display.

Program HALT displays PC+2 of HALT instruction in ADDRESS display.

Byte operations to the odd byte of the PS cause
odd address traps.

Byte operations to the odd byte of the PS do
not trap. Not all bits may exist.

No R TT instruction.

If RTT sets the T bit, the T bit trap occurs after
the instruction following RTT.

If RTI sets T bit, T bit trap acknowledged after
instruction following RTI.

If RTI sets T bit, T bit trap acknowledged
immediately following RTI.

Explicit reference to PS can load T bit. Console
Can load T bit, initialize can clear it.

Only implicit references (RTI, RTT, traps, and
interrupts)can load T bit. Console cannot load
T bit but initialize can clear it.

The BUS INIT of the RESET instruction occurs
when the processor has control of the bus. No
bus cycles are interrupted.

The BUS INIT of the RESET instruction occurs
asynchronously with other Unibus operations.

)

CAUTION
BecausePDP-l1/20 and PDP-l1/40 RESET instruction timing
precludes the POWER FAIL routine, use of the RESET
instruction should besevereIy limited.

Odd address or nonexistent references using the
SP cause a fatal trap. On bus error in trap
service, a new stack is created at locations 0 and

Odd address or nonexistent references using the
SP cause a HALT. This is a case of double bus
error with a second error occurring in the trap
service of the first error.

)
3-30

Table 3-9 (Cont)
PDP-II Programming Comparison

)

PDP-l1/20

PDP-11/40

Stack limit boundary fixed at octal 400 with
violations serviced by an OVFL trap.

Optional variable stack limit boundary (KJ 11-A
option). Use of red and yellow zones on either
basic (octal 400) or optionally variable boundary.

First instruction in an interrupt service routine
is guaranteed to be executed.

The first instruction in an interrupt routine is
not executed if another interrupt occurs at a
higher priority level than was assumed by the
first interrupt.

Power up vector at 24 when power returns.

Power up vector is initially at 24; can alter
jumpers to other addresses.

A trap instruction to vector location 14 exists
for the IR code 3. No name is given this
instruction.

The formerly unnamed instruction for IR code
3 is now called BPT.

Condition codes for a MOV instruction are not
altered for present data if a bus error occurs on
the last destination address. The error trap
occurs on the DATIP of the DATIP, DATa
sequence of that address.

Condition codes for a MOV instruction are
altered for present data if a bus error occurs on
the last destination address. The error trap
occurs on the singular DATa sequence to that
address.

NOTE
The following is the priority sequence of service for internal
processor traps, external interrupts, and HALT and WAIT.

BUS ERROR TRAP - odd address, data time
out.

BUS ERROR TRAP - odd address, fatal stack
overflow (red); if KT11-D option is used,
memory management violations; parity error
trap response.

HALT instruction for console operation.

Same. (Refer to KT11-D, if installed, for other
changes.)

TRAP instructions - illegal or reserved instructions, TRT, lOT, EMT, TRAP.

TRAP instructions - illegal or reserved instructions, BPT, lOT, EMT, TRAP.

TRACE TRAP - T bit of processor status.

Same

OVFL trap - stack overflow.

OVFL - warning (yellow) stack overflow.

PWR FAIL trap - power down.

Same

)
/

)
3-31

Table 3-9 (Cont)
PDP-I 1 Programming Comparison
PDP-ll/40

PDP-ll/20
CONSOLE BUS REQUEST - console operation after HALT switch.

Same

UNIBUS BUS REQUEST - peripheral request,
compared with processor priority, usually an
interrupt occurs.

Same

WAIT LOOP -loop on a WAIT instruction in
the IR until an interrupt allows exit. A CONSOLE BUS REQUEST returns to this loop after
being honored.

Same

)

)
3-32

CHAPTER 4
PROCESSOR INSTRUCTIONS AND OPTIONS

4.1 SCOPE
This chapter presents a brief introduction of the PDP-II instruction set and the processor options available for the
PDP-1 1/40 System.

)

Paragraph 4.2 discusses the basic PDP-II instruction set and also covers the additional instructions that are available
if certain processor options (KEII-E, KE II-F, and KT1I-D) are installed in the basic system.
Paragraph 4.3 describes each of the options that can be mounted in the basic KDII-A Processor and references
appropriate documents containing detailed information on the specific option. These options are: KE II-E, KE II-F,
K1II-A, KT1I-D, KWII-L, KMII-A, and a Small Peripheral Controller. Specifications are contained in Tables 4-12
through 4-16.

)

4.2 INSTRUCTION SET
This section summarizes the PDP-I 1/40 address modes and instruction set. Its purpose is to define the operation of
the KDll-A Processor and provide quick-reference tabular information. A complet-e description of PDP-I 1/40
address modes and instructioris, with additional details and examples, is provided in the PDP-ll/40 Processor
Handbook.

)

The Instruction Set Processor (ISP) notation is used to define the processor operations for each address mode and
instruction. Table 4·1 defines the modified ISP symbology used in this chapter. A more detailed description of ISP
notation is provided in Appendix A of the PDP-ll/40 Processor Handbook. Modified ISP notation is used in the
KDll·A Processor Manual in the block diagram and flow diagram description of instruction implementation. The
modifications are as follows:

()

•+

plus
minus

is used for ( ) or [ ]
or ( ) around an expression indicates logical AND
indicates logical OR
indicates logical negation
indicates addition
indicates subtraction

The following paragraphs cover address modes (paragraph 4.2.1), the basic instruction set (paragraph 4.2.2), and the
extended instruction set (paragraph 4.2.3).

)
4-1

Table 4-1
ISP Symbology
Symbol

Definition

(

Defines the limits of an expression, such as word length (15 :0).

[ 1

Defines the limits of a memory declaration; Mw [SPl specifies the address of the
stack pointer in memory.
The expression to the left of this symbol is replaced by the expression to the right
of this symbol, .
Z ..... I indicates the Z bit is set,
PC ..... PC + 2 indicates the program counter register (PC) is incremented by 2.

cat
equiv
&
OR

Indicates concatenation; registers to the left and right of this expression are considered to be one register.
Designates that expressions to the left and right are equivalent.
Logical AND
Logical inclusive-OR

)

Negate
XOR

Logical exclusive-OR
Indicates that a reference to the expression with which this symbol is used may
cause side effects, e.g., registers may be changed as a result of the operation.
Used as a delimiter

;next

A sequential delimiter, the operation to the left.must occur before the operation to
the right.

Designates an address mode; address mode 1 is indicated by m = 1.

General register 7 (program counter)

Auto-incrt1ment; by 2 for word instructions, and by 1 for byte instructions.

Indicates a result; used many times with limit symbols as an intermediate register
(r 05:0»).

Addition; expression to the left is added to expression to the right.
Subtraction; expression to the right is subtracted from expression to the left.

Multiply; expression to the left is multiplied by expression to the right.

Divide; expression to the left is divided by the expression to the right.

sign-extend

)

The sign bit of a byte, bit 7, is extended through bits 8 to 15.

Memory word declaration; the address in brackets points to the memory location.

nw'

Indicates next word, as pointed to by the PC with side effects ('). The word is at
the next sequential PC address, or the word pointed to by the next word (deferred
addressing).

R [drl

)

Indicates that a register (R) address as a memory declaration is that of a device
register.

Destination

Byte destination

Source

Byte source

)
4-2

4.2.1 Address Modes
The instruction set of the PDP-I 1/40 System flexibly interacts with the general-purpose registers through the address
modes. Table 4-2 lists all of the address modes, including the Program Counter (PC) register address modes. These
address modes, along with the general-purpose register designation, determine the instructions' operands (source
and/or destination) and form part of the 16-bit instruction format (Figure 4-1).
Table 4-2
Address Modes
Mode

Designation

ISP

Description

General Purpose Register Addressing
0

if (m=O) then Rr (w I: 0);

The register (R, Rr) is the operand.

@Ror(R)

if (m=l) then M[Rr 1;

Defer to operand through register
(R, Rr) as address.

auto-increment

(R)+

if (m=2) and (rgf7) then
(M [Rr 1; next
Rr ~ Rr + ai);

Defer to operand through register
(R, Rr) as address, then increment.

auto-increment
deferred

@(R)+

if (m=3) and (r'617) then
(M [Mw [Rrll; next
Rr~Rr+ 2;

Defer to operand through (R), Mw
[Rr 1 as address, then increment
register (R, Rr).

auto-decrement -(R)

auto-decrement
deferred

@-(R)

if (m=5) then (Rr ~ Rr - ai;
next M[Mw[Rrll);

Defer to operand through (R), Mw
Rr after decrement of register (R, Rr).

indexed

±X(R)

if (m=6) and (rgf7) then
M[nw' + Rrl;

Index via register = (R, Rr) by the
amount specified in next PC word (X).

indexed
deferred

@±X(R)or
@(R)

if (m=7) and (rgf7) then
M [Mw[nw' + Rrll;

Defer to operand through index of
register (R, Rr) specified in next PC
word (X) as address.

)

if (m=4) then (Rr ~ Rr - ai); Decrement register (R, Rr), then defer
next M [Rrl;
to operand through register (R, Rr) as
address.

PC Register Addressing

)

immediate

if (m=2) and (rg=7) then
nw' (wl:O)

Defer to operand through PC value
(next word); next word is immediate
operand.

absolute

@#A

if (m=3) and (rg=7) then
M[nw'l

Defer via next word (PC address) as
address to operand; absolute addressing.

relative

if (m=6) and (rg=7) then
M[nw' +PCl;

Relative to PC; uses next word as deferred address of operand.

relative
deferred

if (m=7) and (rg=7) then
M[Mw[nw' +PCll;

Defer relative to PC; uses next word as
address of deferred address of the operand.

NOTE: The following symbols are used in this table:

)

R
= Register
X, n, A = next program counter (PC) word (constant)

4-3

SINGLE OPERAND

MODE

!@ I

OP CODE

""*
Rn
I

DESTINATION
ADDRESS FIELD

*= SPECIFIES DIRECT OR INDIRECT ADDRESS.
**= SPECIFIES HOW REGISTER WILL BE USED.
***=SPECIFIES ONE OF EIGHT GENERAL PURPOSE REGISTERS.

-- j@1
-

DOUBLE OPERAND

I MOIDE

OP CODE

-**

MODE
I
5
4

SOURCE
ADDRESS FIELD

***

i @I

DESTINATION
ADDRESS FIELD

.=DIRECT/DEFERRED BIT FOR SOURCE AND DESTINATION ADDRESS.
.... =SPECIFIES HOW SELECTED REGISTERS ARE TO BE USED.

)

,,**=SPECIFIES A GENERAL REGISTER.
11-1068

Figure 4-1 Double and Single Operand Addressing

)

DOUBLE OPERAND
OP CODE

Src

dst

Src/dst

REG

I
SINGLE OPERAND
OP CODE

dst

)

M ISCELLAN EOUS

REG

BRANCH (PROGRAM CONTROL)
OP CODE

OFFSET

CONDITION CODE OPERATORS

I
11-1069

Figure 4-2 Instruction Formats

)
4-4

4.2.2 Basic Instruction Set
The KDII·A basic instruction set is divided into six groups of instructions. The format of each group is shown in
Figure 4·2. The six groups of instructions are:
a.

Double Operand - Operations which imply two operands (such as ADD, SUBtract, MOVe, and
CoMPare) are handled by instructions that specify two addresses. The first operand is called the source
operand; the second is called the destination operand. Bit assignments in the sOurce and destination
address fields may specify different address modes and different registers.
Double·operand instructions are listed in Table 4·3.

Single Operand - Operatiolls which require only one operand (such as CLeaR, INCrement, TeST) are
handled by instructions that specify only a destination address (operand). The operation code, address
mode, and destination address are specified by the instruction.
Single·operand instructions are listed in Table 4·4.

)

Register Source or Destination - Instructions in this group make use of the general processor registers as
simple accumulators and the resultant is stored in the selected register. Information can be used as either
a source or destination operand. For example, the eXclusive OR of the selected register and the
destination operand can be stored in the destination address.
Register source or destination instructions are listed in Table 4·5.

)

Branch (Program Control) - These instructions permit control of the program by branching to new
locations in the program dependent on conditions tested by the program. The instructions cause the
program to branch to a location specified by the sum of an offset value (multiplied by 2) and the current
contents of the Program Counter (PC), provided the branch is either unconditional oris conditional and
the conditions are met after testing the Processor Status (PS) word.
Branch instructions are listed in Table 4·6.

Miscellaneous - These instructions include HALT, WAIT, and RESET as well as interrupt and trap
handling instructions such as RTI, RTT, EMT, and TRAP.
Miscellaneous instructions are listed in Table 4·7.

)
f.

Condition Code Operators - These instructions are used to set or clear individual condition codes in the
Processor Status (PS) word. Selected combinations of these bits may be set or cleared together.
Condition code operators are listed in Table 4·8.

)
4·5

Table 4-3
Double Operand Instructions
Mnemonic
Instruction
andOp Code
MOV
Move

r <- S'; next
N <- r (15)

(Src to Dst)
01SSDD

if (r (15:0> =0) then (Z<- 1 else Z <- 0),
V <- 0;
D' <- r

MOVB
Move Byte
(Src to Dst)
llSSDD

r <- Sb'; next
N <- r (7);

CMP
Compare
(Src to Dst)
02SSDD

CMPB
Compare Byte
12SSDD

BIT
Bit Test
03SSDD

BITB
Bit Test,
Byte
13SSDD
BIC
Bit Clear
04SSDD

BICB
Bit Gear,
Byte
14SSDD

.. Description

ISP Notation

if (r (7:0> =0) then (Z <-1 else Z +- 0);
V<-O;
Db' <-r
r (16:0) <- S; - D';next

Move source to intermediate register, r.
Set N if negative.
Set Z ifO.
Clear V.
Transmit result to destination.
Move source to intermediate register, r.
Set N if negative.
SetZ ifO.
Clear V.
Transmit result to destination.

(V <- 1 else V+- 0);
C<-r(6)

Source and destination operands are compared, but unaffected.
Only condition codes are affected, as follows:
Set N if r is negative.
Set Z if r is O.
Set V if operands have opposite signs and the sign of the source
is the same as the result, r.
Clear C if 17th bit is carry.

r (8:0> <- Sb' - Db'; next

Same as CMP, except operands are bytes.

N <- r(15);
if (r (15:0> =0) then (?: <- 1 else Z <-0);
if (S OS) =~D (15») & (S (15) XOR r (15») then

N<- r(7);
. . :.:
if (r (7:0) = 0) then (Z <- 1 eise Z <-0);
if(Sb <7> = ~ Db <7> & (Sb <7> XOR r (7)) then
(V <- 1 else V <- 0);
C <- r(8)
r <- D' & S'; next

N <- r OS);

if (r (15:0>
V<-O

=0) then (Z <-l.else Z <- 0);

r <- Db' & Sh'; next

)

)
Logical AND of source and destination operands.
Set N if negative.
Set Z ifO.
No overflow.
Same as BIT, except byte

N <- r <7>;

)

if (r (7:0> =0) then (Z <-1 else Z ~O);
V<-O
r <- D' & ~ S'; next
N <- r (15);
if (r OS :0) =0) then (Z +- 1 else Z <- 0);
V<-O;
D <- r
r <- Db' & ~ Sb'; next
N <- r <7>;
if {r (7:0> =0) then (Z +- 1 else Z <- 0);
V +-0;
Db<-r

AND destination operand with complemented source operand.
Set N if negative.
Set Z ifO.
Clear V and put result in
destination address.

Same. as BIC, except byte..

)
4-6

Table 4-3.(Cont)
Double Operand Instructions
Mnemonic
Instruction
and Op Code

BIS

r +- D' OR S'; next
N +- r (1S);

OSSSDD

if (r (1S:0) =0) then (Z +- 1 else Z +- 0);

Set Z ifO.

V+-O;

Clear V.

D +- r

Put result in destination.

r +- Db' OR Sb'; next
N +- r <7>;
if (r (7:0) =0) then (Z +- 1 else Z +- 0);
V+-O;
Db +-r

Same as BIS, except byte.

Bit Set, Byte
lSSSDD

)

Description

Bit Set

BISB

)

ISP Notation

Inclusive OR of source operand and destination. operand.
Set N if negative.

ADD

r 06:0> +- S'+ D'; next

Add source and destination to provide 17-bit sum.

Add

N +- [(IS);

Set N if negative result.

06SSDD

if (r OS :O)

=0) then (Z +- 1 else Z +- 0);

Set Z ifO.

if (S OS) equiv D (1S}) & (S OS) XOR r (IS})
then (V +- 1 else V+- 0);
C+-r(16};

opposite sign.
Set C if carry.

D +- r 05:0>

Put result in destination.

SUB

r 06:0} +- D' - S'; next

Subtract source operand from destination operand.

Subtract

N+-rOS};

Set N if negative results.

16SSDD

if (r (1S:0)

=0) then (Z +- 1 else Z +- 0);

Set V if both operands were same sign and the result is of

Set Z ifO.

if (D (15) XOR S (1S)) & (D (15) XOR r

Put result in destination.

sign from destination.

)

)
4-7

Table 4-4
Single Operand Instructions
Mnemonic
Instruction
andOp Code

ISP Notation

CLR

D' ..... O;

Clear dst

N ..... O;

OOSODD

Description

Clear destination, N, Y, and C; set Z.

Z ..... 1;

Y ..... O;
C ..... O
CLRB

Db' ..... O;

Clear Byte dst

N ..... O;

1OS0DD

Z ..... I;

Clear destination byte.

Y ..... O;
C ..... O
COM

r ..... ~ D'; next

Complement destination.

Complement

N ..... r OS};
if (r ;
if (r (7:0) = 0) then (Z ..... 1 else Z ..... 0);
Y ..... O;
C ..... 1;
Db ..... r

Same as COM, except byte.

INC

r ..... D' + 1; next

Result is sum of D plus 1.

Increment dst

N ..... r OS};

Set N if negative.

00S2DD

if(r 05:0} = 0) then (Z ..... 1 else Z ..... 0);

Set Z ifO.

if(r OS:O}= 100000S) then (Y ..... l else Y ..... O);
D ..... r

Put result in destination.

Set Y if result equals 1000008 (dst was 077777 8 ).

Increment

r ..... Db' + 1; next
N ..... r <7>;

Byte dst

if (r (7:0) = 0) then (Z ..... 1 else Z ..... 0);

1OS2DD

if (r<7:0)= 200 8 ) then (V ..... 1 else Y ..... 0);
Db ..... r

DEC

r ..... D' - 1 ; next
N ..... rOS};

Set N if negative.

if (r OS :O) = 0) then (Z ..... 1 else Z ..... 0);

Set Z ifO.

if (r (IS:o) = 77777 8 ) then (Y ..... 1 else Y ..... 0);
D ..... r

Put result in destination.

INCB

Decrement
dst
00S3DD

DECB
Decrement
Byte dst
1OS3DD

)

Same as INC, except byte.

)

Set Y if result equals 200 s (dst byte was 177 S).

Result is destination operand minus 1.

r ..... Db' -1 ; next
N ..... r <7>;

Set Y if result equals 777778 (dst was 100000 s).

Same as DEC, except byte.

if (r (7:0) = 0) then (Z ..... 1 else Z ..... 0);
if (d7:0) = 1778 ) then (Y ..... 1 else Y ..... 0);
Db ..... r

Set Y if result is 1778 (dst byte was 000 8).

)
4-8

Table 4-4 (Cont)
Single Operand Instructions
Mnemonic
Instruction
and Op Code
NEG
Negate dst
OOS4DD

ISP Notation

Description

r .... -D'; next

N .... r (IS);
if (r OS :0) = 0) then(Z .... I else Z .... 0);
if(r OS:O) = 100(008 ) then (V .... 1 else V .... 0);
if (r 0 S :0) = 0) then (C .... 0 else C .... 1);
D ..... r

Negate D by 2's complement.
Set N if negative result.
Set Z ifO.
Set V if result is 100000 8 .
Clear C if result is 0, otherwise set C.
Put result in destination.

NEGB
Negate Byte
IOS4DD

r .... - Db'; next
N .... r (7);
if (r (7:0) = 0) then (Z .... 1 else Z .... 0);
if (r (7:0) '= 200 8 ) then (V .... I else V .... 0);
if (r (7:0)= 0) then (C .... 0 else C .... I);
Db .... r

Same as NEG, except byte.

ADC
Add Carry
OOSSDD

r .... D' + C; next
N .... r OS);

Add the C bit to the destination.
Set N if negative.
Set Z ifO.
Set V if destination was 0777778 and C was 1.

)

if (r 05:0) = 0) then (Z .... 1 else Z .... 0);
if (r (15:0) = 1000008) & (C '" 1) then (V .... I
else V .... 0); next
if (r OS:o) = 0) & (C = 1) then (C .... 1 else
C .... O);

Set C if destination was 177777 8 and C was 1.

D .... r
ADCB
Add Carry
Byte
IOSSDD

r .... Db' + C; next
N .... r <7>;
if (r (7:0) = 0) then (Z .... 1 else Z .... 0);
if (r (7:0) = 200 8 ) & (C = 1) then (V .... 1 else
V .... 0); next
if (r (7:0) = 0) & (C = 1) then (C .... l else C .... O);
Db .... r

Same as ADC, except byte.

SBC
Subtract
Carry
OOS6DD

r .... D'-C; next
N .... rOS);
if (r 0 S:O) =0) then (Z .... 1 else Z .... 0);
if (rOS:o) = 100(008) then (V .... 1 elSe V .... 0);

Subtract C bit from contents of destination.
Set N if negative.
Set Z ifO.
Set V if result is 1000008 .
Clear C if result is 0 and C = i.

if(r ;
if (r (7:0) =0) then (Z +- 1 else Z +- 0);
V+-O;
C+-O

)

r <16:0) +- D' (0) cat C cat D' (15: 1); next

17-bit intermediate result is C and contents of destination
rotated right one place.
Set N if high order bit is set.
Set Z if result is O.
Put 17-bit result into C bit and destination.
Load V with exclusive-OR of Nand C (after. rotation is
complete).

N +- r (15);
if (r (15:0) =0) then (Z +- 1 else Z+- 0);
C cat D 05:0) +- r (16:0); next
if (N XOR C) then (V +- 1 else V+- 0),

RORB
Rotate Right
Byte
1060DD

r (8:0) +- Db' (0) cat C cat Db' (7: 1>; next
N +- r <7>;
if (r (7:0) =0) then (Z +- 1 else Z +- 0);
C cat Db +- r (8:0); next
if (N XOR C) then (V +- 1 else V+- 0)

Same as ROR, except byte,

ROL
Rotate Left
00610D

r <16:0) +- D' <15:0) cat C; next

17-bit result is C and contents of destination rotated left one
bit.
Set N if resul t is negative,
Set Z if result is 0,

N +- r (15);
if (r (15:0) = 0) then (Z +- 1 else Z +- 0);

Put result into C and D. Bit 15 into C bit and previo~s C bit
into bit O.
Load V with exclusive-OR of Nand C after rotation is
complete.

C cat D +- r <16:0); next
if (N XOR C) then (V +- 1 else V,+- 0)

ROLB
Rotate Left
Byte
10610D

ASR
Arithmetic
Shift Right
0062DD

r (8:0) +- Db' (7:0) cat C; next
N +- r <7>;
if (r (7:0) =0) then (Z +- 1 else Z +- 0);
C cat Db +- r (8:0); next
if (N XOR C) then (V +- 1 else V+- 0)

Same as ROL, except byte.

r +- D'/2; next

Contents of destination shifted right one place (7 2).
Least-significant bit loaded into C,
Set N if result negative,
Set Z if result 0,
Load V with exclusive-OR of Nand C after shift is complete,
Put result into destination,

C +- D (0);
N +- r (15);
if (r <15:0) =0 then (Z +- 1 else Z +- 0); next
if (N XOR C) then (V +- 1 else V+- 0);
D+- r

)

)
4-10

Table 4-4 (Cont)
Single Operand Instructions

~)
Mnemonic
Instruction
and Op Code

)

Description

ASRB
Arithmetic
Shift Right
Byte
1062DD

r +- Db'/2; next
C +- Db (0);
N +- r (7);
if (r (7:0) = 0) then (Z +- 1 else Z +- 0); next
if (N XOR C) then (V +- I else V+- 0);
Db +- r

Same as ASR except byte.

ASL
Arithmetic
Shift Left
0063DD

r +- D' (15) cat D' (13:0) cat 0; next

Shifts contents of destination left one place, but sign bit
remains in most signifkant place.
Bit 14 loaded into C.
Set N if result negative.
Set Z if result O.
Load. V with exclusive-OR of Nand C after shift completed.
Put result in destination.

)

ISP Notation

C +- D (14); next
N +- r (15);
if (r (15 :0) =0) then (Z +- 1 else Z +- 0); next
if (N XOR C) then (V +- I else V+- 0);
D +-r

ASLB
Arithmetic
Shift Left
Byte
1063DD

r +- Db' (7) cat Db' (5:0) cat 0; next
C +- Db (6); next
N +- r (7);
if (r (7:0) = 0) then (Z +- I else Z +- 0); next
if (N XOR C) then (V +- I else V+- 0);
Db +- r

Same as ASL, except byte.

MARK
Mark
0064nn

SP +- SP + (2 X df (5:0); next

Adjusts stack pointer by the number of words indicated in the
low 6 bits of the instruction (2 X nn locations).
Puts old PC (R5) into PC.
Contents of old R5 popped into R5.

PC +- R[5] ; next
R[5] +- Mw [SP] ;
SP +- SP + 2

SXT
Sign Extend
destination
0067DD

if (N = I) then (r (15:0) +- -I else r (15:0) +- 0);
next
if (r (15:0) = 0) ,then (Z +- I-else Z +- 0);
D' +- r

If the N bit is set, then - I is placed in the destination operand.
Otherwise, 0 is placed in the destination operand.
Set Z if result is O.

JMP
Jump
OOOIDD

PC +- D address

D address is computed in a fashion similar to D.

SWAB
Swab Bytes
Destination
0003DD

r +- D' (7:0) 0 D' (j 5 :8); next
N +- r (7);
(r (7:0) = 0) --> (Z +- 1 else Z = 0);
V+-O;
C +- 0;
D <- r

Result is byte swapped of D negative?
Zero?
Clear V, C
Transmit result to D.

)
4-11

Table 4-5
Register Source or Destination Instructions
Mnemonic
Instruction
and Op Code

ISP Notation

XOR
Exclusive-OR

r +- R[sr] XOR D'; next

074RDD

if (r =0) then (Z +- 1 else Z +- 0);
N +- r OS);
V+-O;
R[sr]+-r

SOB
Subtract
One and
Branch
077R offset

r +- R[sr] -1; next
R[sr] +- r;
if (r =1= 0) then (PC +- PC - 2 X df (5 :0»)

Description

The exclusive-OR of the register and the destination operand
is stored in t,,;
if (D (5) = 0) & (D (5:0> 1 0) then
C +- £(64);

Contents of R, and R ORed with I, form a 32-bit word (R =
31 :16, ROR 1 = 15:0) that is shifted right or left NN places,
specified by six low-order bits of destination operand, DD.
Store results in Rand R OR I.
Set Z if result is O.
Set N if result is negative.
Set V if sign bit changes during the shift.

Load C with high order if left shift.
Load C with low order if right shift.

if (D (5:0) = 0) then C+-O

Otherwise, clear C.

XOR
Exclusive-OR

r +- R[sr] XOR D'; next

074RDD

if (r = 0) then (Z +- I else Z +- 0);
N +- r OS);
V+-O;
R[sr] +- r

The exclusive-OR of the register and the destination operand
is stored in the destination address.
Set Z if result is O.
Set N if result is negative.
Clear V; no overflow possible.

SOB
Subtract
One and
Branch
077R offset

r+-R[sr] -1;next
R[sr] +- r;
if (r f 0) then (PC ..... PC -2 X df(5:0»)

)

Decrement register by I. If result is not equal to 0, branch.
Subtract 2 X 6-bit offset from PC to get new PC.

)

)
4-19

Table 4-10
Floating Instruction Set (FIS)
The following abbreviations are used in this table:
FSP =Floating Stack Pointer
FAC =(31:00) =FSP + 4 05:00) D FSP + 6 (l5:00)
FAS' (31 :OO) = FSP (I 5:00) D FSP + 2 (15:00)
Mnemonic
Instruction
and Op Code
FADD
Floating ADD
07500R

ISP Notation

Description

FR+-FAC + FPS';next

Move sum of accumulator and source to temporary register.

«FR < XUL) V (FR > XLL»-+
(F AC +- FR else NO OP); next

Store result if no underflow or overflow, NO OP otherwise.

«FAC < 0) V (FAC < XLL»-+
(N +- 1 else N +- 0);

Negative?, underflow?

(FAC = 0) = > (Z +-1 else Z +- 0);

Zero?

«FAC> XUL) V (FAC > XLL»-+

Overflow?, underflow?

)

(V +- 1 else V+- 0);

FSUB
Floating
Subtract
07501R

C+-O

Clear Carry

FR +- F AC - FPS'; next

Move difference of accumulator and source to temporary
register.

«FR < XUL)V (FR > XLL» -+
(FAC +- FR else NO OP); next

Store result if no underflow or overflow, NO OP otherwise.

(FAC < 0) V (FAC < XLL»-+
(N +- 1 else N +- 0);

Negative?, underflow?

(FAC

=0) -+ (Z +- 1 else Z +- 0);

Zero?

(FAC > XUL) V (FAC > XLL»-+
(V +- 1 else V+- 0);

Overflow?, underflow?

C+-O

Clear Carry

)

)
4-20

Table 4-10 (Cont)
Floating Instruction Set (FIS)
Mnemonic
Instruction
and Op Code
FMUL

ISP Notation

FR ...... FAC

Description

* FPS'; next

Move product of accumulator and source to temporary
register.

Floating
Multiply
0750~R

l(FR < XUL) V (FR > XLL»-+
lFAC +- FR else NO OP); next

Store result if NO overflow or underflow, NO OP otherwise.

«FAC < OV (F AC < XLL».-+
(N +- I else N +- 0);

Negative?, underflow?

=0) -+ (Z +-

(FAC

)

FDIV
Floating
Divide
07503R

)
/

I else Z +- 0);

Zero?

«F AC > XUL) V (F AC > XLL» -+
(V +- I else V+- 0);

Overflow?, underflow?

C+-O

Clear Carry

(FPS

=0) =C +- I

(FPS ~ 0) -+ FR +- FAC / FPS'; next

Move result of division to temporary register.

«FR < XUL) V (FR > XLL»-+
(FAC +- FR else NO OP);

Store result if NO overflow or underflow, NO OP otherwise,

«F AC < 0) V (FAC > XLL» -+
(N +- I else N +- 0);

Negative?, underflow?

(FAC

=0) -+ (Z +- I else Z +- 0);

Zero?

«FAC> XUL) V (FAC > XLL»-+
(V +- I else V+- 0);

)
(FP.S

Overflow? , underflow?

=0) -+ (C +- I else C +- 0)

Divide by Zero?

)
4-21

Table 4-11
Memory Management Instruction Set
Mnemonic
Instruction
and Op Code
MFPI/D
Move From

Description

ISP Notation

r +- D'; next
SP +- SP-2;
N +- r (15);

Get destination operand from previous I space.

Previous
Instruction
Space
006SDD

if(r (15:0) =' 0) then (Z +- I else Z +- 0);
V+-O;
Mw [SP] +- r

Push stack.
Set N if negative.
Set Z ifO.
Clear V.
Put operand into current address space.

MTPI/D
Move To
Previous
Instruction
Space
0066DD

r+-Mw [SP];
SP +- SP + 2; next
N +- r (15);
if (r (15:0) =0) then (Z +- I else Z +- 0);
V+-O;
D' +-r

Get data from current stack.
Pop stack.
Set N if negative.
Set Z ifO.
Clear V.
Move to previous I space destination.

)

4.3 PROCESSOR OPTIONS
The basic KDII-A Processor contains space for installing six processor options. In addition, there is a Small
Peripheral Controller (SPC) slot that is usually used for an input terminal control (such as the DECwriter or Teletype
interface) but that also can be used for a variety of options dependent on the user's individual requirements. The
specific slot, or slots, allocated for each option is listed in Table 4-12 and shown in Figure 6-3.

)

The available processor options are:
a.

KE ll-E Extended Instruction Set EElS)

KEII-F Floating Instruction Set (FIS)

K1ll-A Stack Limit Register

KT11-D Memory Management

KWII-L Line Time Clock

KMl1-A Maintenance Console

Small Peripheral Controller (variable option)

)

The above options can be used in any combination as they function independently with two exceptions. The
KE II-F (FIS) option physically requires the KE l1-E (ElS) option, and software for the KT11-D option requires the
K111-A option. Each option is discussed separately in subsequent paragraphs which include a general description,
specifications, and a reference to more detailed documents.

)
4-22

Table 4·12
Location of Processor Options

)

Option

Section(s)

Slot

KEII-E Extended Instruction Set (EIS)

A-F

KE II-F Floating Instruction Set (FIS)

A-D

K111-A Stack Limit Register

KT11-D Memory Management

A-F

KWll-L Line Time Clock

KMI1-A Maintenance Console
For maintenance of the basic
processor

C-F

For maintenance of the KT11-D
and/or EIS and FIS options
Small Peripheral Controller

4.3.1 KEll-E Extended Instruction Set (EIS) Option

)

The KEII-E Extended Instruction Set Option is a processor option that expands the basic PDP-ll/40 instruction set
to include: MULtiply (MUL), DIVide (DIV), Arithmetic SHift (ASH), and Arithmetic SHift Combined (ASHC).
The option permits multiplication and division of signed 16-bit numbers and arithmetic shifting of signed 16-bit or
32-bit numbers. Condition codes are set on the result of each instruction.
The KEII-E (EIS) option is a single hex (six section) module (M7238) that plugs directly into slot A02-F02 of the
processor backplane. The option functions as an extension of the basic KDII-A data paths, microbranch control,
and control ROM. The basic processor timing is not degraded when this option is used. The NPR latency is not
affected when the instructions are being executed. Interrupts are serviced at the end of each instruction in the
standard manner.
There are no addressable registers in the KEII-E option. All operands are fetched from either core memory or from
the general processor registers and the result of each operation is stored in the general registers.
The MUL instruction uses the contents of the effective addresses specified by the destination register and the source
register as 2's complement integers which are multiplied. The result is stored in the source register and, if even, the
low-order result in the succeeding register. If the source register address is odd, only the low-order product is stored.
The MUL instruction multiplies full 16-bit numbers for a 32-bit product.

)

The DIV instruction permits a 32-bit 2's complement dividend in the destination registers (R and R+1) to be divided
by a 16-bit divisor in the source register. A 16-bit quotient is left in R and the 16-bit remainder is left in R+l. The
sign of the remainder is always the same as the sign of the dividend unless the remainder is zero. Overflow is
indicated if more than 16 bits are required to express the quotient. In this case, the instruction is aborted, the
overflow condition code is set, the expansion processor status (EPS) word is loaded into the processor PS register,
and the program branches to a service routine. If the source register is zero, indicating divide by 0, an overflow is
indicated.

4-23

When the ASH instruction is used, the contents of the selected register is shifted right or left the number of places
specified by a count. this shift count is a 6-bit, 2's complement number which is the least significant 6 bits of the
destination operand. If the count is positive, the number is shifted left; if it is negative, the number is shifted right.
This allows for shifts from 31 positions left to 32 positions right (+31 to - 32). A count of zero causes no change in
the number.

\
)

When the ASHC instruction is used, the contents of a register (R) and the contents of another register (R+1) are
treated as a single 32-bit word. Register R+ 1 represents bits 0-15, register R represents bits 16-31. This 32-bit word
is shifted right or left the number of places specified by a count. This shift count is the same as that described for
the ASH instruction and permits shifts from +31 to -32. If the selected register (R) is an odd number, then Rand
R+1 are the same. In this case, a shift becomes a rotate and the 16-bit word is rotated the number of counts
specified by the shift count (up to 16 shifts).
Specifications for the KE11-E option are listed in Table 4-13. A detailed description of this option is given in the
KEll-E and KEll-F Instruction Set Option Manual, EK-KE11E-TM-002.

Table 4-13
KEI1-E (EIS) Specifications
Function

)

Description

Instructions

MULtiply (MUL)
DNide (DIV)
Arithmetic SHift (ASH)
Arithmetic SHift Combined (ASHC)

Operations

Multiplication and division of signed 16-bit numbers.

)

Arithmetic shifting of signed 16-bit or 32-bit numbers.
Registers

None in option. Operands fetched from core or general
processor registers.

Timing (approximate)

MUL= 9.5 J.ls
DIV = 10.5 J.ls

)

ASH = 3.4 J.ls plus address calculation time plus 300 ns
times absolute value of shift count.
ASHC = 3.8 J.ls plus address calculation time plus 300 ns
times absolute value of shift count.
Size

Single hex module (M7238)

4.3.2 KEll-F Floating Instruction Set (FIS) Option
The KE11-F Floating Instruction Set Option enables the KDI1-A Processor to perform arithmetic operations using
floating point arithmetic. The prime advantage of this option is increased speed without the necessity of writing
complex floating point software routines. The KE11-F performs single-precision operations. The KE11-F option
cannot be used unless the KEll-E (EIS) option has been installed in the system.

4-24

)

The KE11-F (FIS) option is a single quad module (M7239) that plugs directly into slot AOI-D01 of the processor
backplane. If a BR is issued before the instruction is within approximately 8 f.l.S of completion, the floating point
instruction is aborted. In this event, the Program Counter (PC) points to the aborted floating point instruction,
making the instruction the next instruction to be performed by the program. The NPR latency is not affected when
floating point instructions are being executed. Interrupts are serviced at the end of each instruction in the standard
manner.
The FIS option provides four special instructions: Floating point ADDition (FADD), Floating point SUBtraction
(FSUB), Floating point MULtiplication (FMUL), and Floating point DIVision (FDIV).
Floating point representation of a binary number consists of three parts: an exponent, a mantissa, and the sign of
the mantissa. The mantissa is a fraction in magnitude format with the binary point positioned between the sign bit
and the most Significant bit. If the mantissa is normalized, all leading Os are eliminated from the binary
representation; the most significant bit is thus a 1. Leading Os are removed by shifting the mantissa left; however,
each left shift to the mantissa must be followed by a decrement of the exponent value to maintain the true value of
the number. The exponent value represents the power of 2 by which the mantissa is multiplied to obtain the value to
be used.

)

For FADD or FSUB operations, the exponents must be aligned (or equal). If they are not, the mantissa with the
smaller exponent is shifted right until they are. Each right shift is accompanied by incrementation of the exponent
value. Once the exponents are aligned (equal), the mantissa is added or subtracted. The exponent value indicates the
number of places the binary point is to be moved in order to obtain the actual representation of the number.
For FMUL instructions, the mantissas are multiplied and the exponents are added. For FDIV instructions, the
mantissas are divided and the exponents are subtracted.

)

The KE11-F option stores the exponent in excess 2008 notation. Therefore, values from -128 to +127 are
represented by the binary equivalent of 0 to 255 (octal 0-377). Mantissas are represented in sign magnitude form.
The binary radix point is to the left. The result of the floating-point operations is always rounded away from zero,
increasing the absolute value of the number.
If the exponent is equal to 0, the number is assumed to be 0 regardless of the sign bit or fraction value. The
hardware generates a clean 0 (32-bit word all zeros) in this instance.

)

Specifications for the KE11-F option are listed in Table 4-14. A detailed description of this option is given in the
KEll-E and KEll-F Instruction Set Option Manual, EK-KE11E-TM-002.
4.3.3 KJII-A Stack Limit Register Option
The KJ11-A option enables variation of the limits of the stack area. In the basic PDP-11/40 System, the first 4008
memory locations (0 through 377 8 ) are reserved for storage of trap and interrupt vectors. This area of memory
should be accessed only when an interrupt subroutine is to be executed or a trap error occurs such as a power
failure. Normally, memory is arranged such that the system stack area is above this vector area. However, to prevent
inadvertent entrance of the stack into the vector area, protection is provided. In the basic KD11-A Processor, this
protection is provided by a fixed boundary (400 8 ), detection circuit. The KJl1-A Stack Limit Register Option
provides a programmable boundary detection circuit. Note that the processor response for a yellow or red zone
boundary violation is unchanged; only the location of the boundary is variable.
SpeCifications for the KJ 11-A option are listed in Table 4-15. A detailed description of this option is presented in
the KDll-A Processor Maintenance Manual, EK-KDI1A-MM-00I.

)
4-25

Table 4-14
KEI1-F (FIS) Specifications
Function

Description

Prerequisite

KE 11-E Extended Instruction Set Option

Instructions

Floating point ADDition (FADD)
Floating point SUBtraction (FSUB)
Floating point MULtiply (FMUL)
Floating point DIVide (FDIV)

Operations

Single precision, floating point addition, subtraction, multiplication, and
division of 24-bit numbers.

Registers

None in option. Operands fetched from core.

Timing

Time = Basic Time Plus Binary Point Alignment Time Plus Normalization
Time

INSTR

FADD
FSUB
FMUL
FDIV
Size

Basic Time*
(J1s)
18.78
19.08
29.00
46.27

Binary Point
Alignment Time
(J1s)
0.30
0.30

Normalization Time
Per Shift
(J1s)
0.34
0.34
0.34
0.34

)

Single quad module (M7239)

*Basic instruction times for FADD and FSUB assume exponents are equal or differ by one.

4.3.4 KTll-D Memory Management Option
The KTll-D Memory Management Option provides the capability to expand the 32K word addressing of the
KDII-A Processor to I28K words and to enhance the use of multi-user, multi-program sY9-tems. A timesharing
environment is created by providing two operating modes: kernel and user. These modes can operate with or
without relocation and protection. Mode selection is made by using an expanded KDII-A processor status word.

)

The KTII-D option basically performs four functions:
a.

Expands the basic 32K word address capability to I28K words.

Provides address space with memory relocation and protection for multi-user timesharing systems.

Implements the separate address spaces for the kernel and user modes of operation.

Provides memory management information for use of memory in multi-user, multi-program systems.

Specifications for the KTlI-D Memory Management Option are listed in Table 4-16. A detailed description of this
option is given in the KTll-DMemory Management Option Manual, DEC-Il-HKTDA-B-D.

4-26

)

Table 4-15
K111-A Specifications
Function

Description

8-bit stack limit register (bits 15-08) addressable by console or
processor, but not by any bus device.

777774 (word addressing)
777775 (byte addressing)

Stack Umit

Programmable; if register is all Os, then:
000-337 = red zone
340...:...377 = yellow zone

)

Yellow Zone Violation

Occurs if the stack operation's address is equal to or less than the stack
limit address by 16 words or less. The operation is completed and then
a TRAP is executed.

Red Zone Violation

Occurs if the stack operation's address is less than the stack limit
address by more than 16 words. The operation is aborted (fatal stack
error), a stack vector exists at address 4, and a bus error TRAP occurs.
The old PS and PC are pushed into locations 2 and 0; the new PC and
PS are taken from locations 4 and 6.

Initialized Stack Umit

The initialized state of the KJII-A option is 377; this is equivalent to
the fixed stack limit of a PDP-ll/40 System without the KJlI-A
option.

Size

One single-height module.

4.3.5 KWI1-L Line Time Clock Option

)

The KWll-L Line Time Clock option provides a method of referencing real intervals. This option generates a
repetitive interrupt request to the processor. The rate of interrupt is derived from the ac line frequency, either 50 Hz
or 60 Hz. The accuracy of the clock period, therefore, is dependent on the accuracy of this frequency source.
The KWll-L option can be operated in either an interrupt or noninterrupt mode. When in the interrupt mode, the
clock option interrupts the processor each time it receives a pulse from the line frequency source. In the
noninterrupt mode, the clock option functions as a program switch that the processor can examine or ignore. Mode
selection is made by the program.
Specifications for the KWI1-L Line Time Clock Option are listed in Table 4-17. A detailed description of this option
is given in the KW JJ-L Line Time Clock Manual, EK-KWI1L-TM-002.

)
4-27

Table 4-16
KT11-D Specifications
Description

Function
Memory Expansion

Expands PDP-11/40 memory address capability up to 124K words.

Interface

Address line outputs compatible with PDP·11 Unibus.

Timing

Timing derived from KD11-A Processor ..

Delay

Adds 150 ns to every memory reference when installed.

Operating Modes

Kernel and user.

Available Pages

Provides eight 4K word pages for each mode.

Page Length

A page can vary in length from one 32-word block up to 128 32-word
blocks. Maximum page length is 4096 words.

Program Capacity

Eight 4096-word pages accommodate.32K word programs.

Size

Single hex module (M7236).

Table 4-17
KWII-L Specifications
Function

)

Description

2-bit status register
bit 06 - interrupt enable
bit 07 - interrupt monitor

777546

Vector Address

100

Mode Control

bit 06 set - interrupt mode
bit 06 clear - non-interrupt mode

Monitor Function

Bit 07 can be used to serve as a partial check on the origin of the interrupt
vector.

Interrupt

Same as line frequency; 50 or 60 Hz.

Priority Level

BR6

Size

Single-height module (M787) that mounts in KDI1-A Processor slot F03.

)

)
4-28

4.3.6 KMll-A Maintenance Console Option
The KMll-A Maintenance Console (also referred to as the maintenance module) is a 2-module set containing 28
indicator lights and 4 switches used to monitor and control functions during maintenance tests.
The functions monitored by the option depend on which processor slot the module is installed in. Different overlays
are provided to indicate the function being tested. The module is installed in processor backplane slot FOI when
testing the KDIl-A Processor and is installed in slot EOI when testing the KT1l-D or KEll-E, F options.
A detailed description of the maintenance console is provided in the KDlJ-A Processor Maintenance Manual,
EK-KDllA-MM-001.
4.3.7 Small Peripheral Controller
Processor backplane slot 09, sections C-F, permit installation of any Small Peripheral Controller option. This slot is
normally used to install the controller for the PDP-l 1/40 System input/output device, but may be used for any
Small Peripheral Controller, if desired.
)

)

The standard controllers for system I/O devices are:
a.

DL1l Asynchronous Line Interface - the standard PDP-ll/40 controller used for either the LA30-S
DEC writer or for the ASR 33 Teletype unit.

LC11 DECwriter Control- a controller used when the LA30-P DECwriteris used as the system I/O
device.

KL11 Teletype Control - an earlier version of the Teletype control which is used only with the ASR 33
Teletype unit.

A brief description of the DL1l is given in Paragraph 1.3.7. Detailed descriptions of all three controllers are included
in related maintenance manuals listed in Table 1-2.

)

4-29

)

CHAPTER 5
SYSTEM PERIPHERALS AND OPTIONS

5.1 SCOPE
This chapter lists the peripherals and options that may be used with the PDP-1l/40. Functional and detailed
descriptions of these units are contained in other documents, listed in Paragraph 5.2.

)
5.2 PERIPHERALS AND OPTIONS
Table 5-1 lists the PDP-11/40 peripherals and options. The PDP-ll Pen'pherals Handbook contains functional
descriptions of these units. Detailed descriptions are provided in associated equipment maintenance manuals. The
handbook is provided with each system and each peripheral and option delivered is accompanied by its own
maintenance manual.

Table 5-1
PDP-ll/40 Peripherals and Options

)
Function

Equipment

Input/Output

Teletype
PC11 High-Speed Reader/Punch
LP11 High-Speed Line Printer
CMl1/CRll Card Reader
LA30 DECwriter

Magnetic Tape Storage

TC11/TU56 DECtape
TMll/TUlO Magtape

Display

VTOIA Storage Display
VR01A Oscilloscope
VR14 Point Plot Display
VT05 Alphanumeric Terminal
RT01 DEClink Terminal

Disk Storage

RC11/RS64 DEC disk Memory
RF 11 /RS 11 Disk and Control
RKll-C/RK02, RK03, RK05 DEC Pack
Disk Cartridge System

)
5-1

Table 5-1 (Cont)
PDP-l 1/40 Peripherals and Options
Function

)

Equipment

Bus Extension

DBII Bus Repeater
DTlI-A, DTlI-B Bus Switches

Communications

DCII Asynchronous Line Interface
DNII Automatic Calling Unit Interface
DPli Synchronous Interface
DMII Asynchronous 16-Line Single Speed Multiplexer
DLll Full Duplex 8-bit Asynchronous Line Interface

DATA Acquisition and Control

AFC 11 Low Level Analog Input Subsystem
ADOID Analog to Digital Conversion Subsystem
AAIID Digital to Analog Conversion Subsystem

)

5-2

CHAPTER 6
EQUIPMENT MOUNTING AND POWER

6.1 SCOPE
This chapter provides detailed information on the PDP-II /40 equipment mounting and power system.

)

The BAII-FC Mounting Box is basic to PDP-l 1/40 equipment mounting and is discussed in Paragraph 6.2. System
unit allocations as well as processor and basic memory slot allocations are noted for the basic box. This information
covers mounting space within the basic system cabinet and in adjacent cabinets (paragraph 6.3).
The power system is duscussed in Paragraph 6.4 and consists of the 861 Power Controller (paragraph 6.4.1), the
H742 Power Supply (paragraph 6.4.2), two H744 +5V Regulators (paragraph 6.4.3), two H745 -15V Regulators
(paragraph 6.4.4), a power distribution panel, and interconnection and distribution cabling. Power controller
interconnection, power system cable harnesses, and dc power distribution are discussed in Paragraphs 6.4.5, 6.4.6,
and 6.4.7, respectively.

)

6.2 SYSTEM MOUNTING BOX
The major components of the PDP-l 1/40 System, with the exception of the power system and console I/O device,
are mounted in a single BAll-FC Mounting Box. Space for additional memory and/or peripheral interfaces is also
provided within this mounting box.

)

TheBAll-FC Mounting Box is mounted in a standard DEC H960-C Cabinet, shown in Figure 6-l. The box is
mounted on chassis slides that enable it to be pulled out for maintenance and/or installation oflogic modules; the
power supply, however, remains within the cabinet. Cooling fans are mounted on top of the box to -provide proper
cooling of the logic elements within the box. The KYII-D Programmer's Console is located on the front of this box.
The mounting box is capable of holding nine system units or eqUivalents. Each system unit casting contains four
slots for mounting logic modules. An alternate double system unit contains nine slots because it has no center
casting. This double system unit is used for the KDII-A Processor and MFII-L Memory.
Allocation of logic within the box is shown in Figure 6-2. A double system unit (with nine slots) is used for the
processor and processor options. Another double system unit is used for the MFII-L Core Memory, which includes
three modules to provide a basic 8K memory. This leaves space for five additional system units (or equivalents) for
additional memory and/or peripheral interfaces. Note that core memory should always be placed as close to the
processor as possible. The basic mounting box provides mounting space and cooling for these additional (expansion)
units. Module allocations for the processor, and memory, are covered in Paragraphs 6.2.1 and 6.2.2, respectively.
Programmer's console mounting is covered in Paragraph 6.2.3.

)
6-1

Revision 1
January 1974

NEW POWER
OISTRI BUTION
PANEL

)
BAII-FC MOUNTING
BOX-NEW STYLE

H960-C CABINET
CA: 115Vae
CB : 230 Vae

)
CABLE SUPPORT STRAP
AND CABLE HARNESS
H742
POWER SUPPLY
WITH REGULAFJRS --+H-+iHl--~-.:--~~""'l!'I
BOX

;,..,.--;=-,"""'=o;r-UPPER LOGIC FANS
KYII-D CONSOLE

)

FAN POWER
DISTRIBUTION
BOARD (OLDER

MOOE~L
ONLY).
861 POWER
CONTROLLER
861-C:115VAC
861-B:230VAC

MOUNTING SPACE
FOR ADDITIONAL----"
SYSTEM UN ITS

11-2308

Figure 6-1 PDP-ll/40 System Cabinet
Revision 1
January 1974

6-2

)

MFll-L BK
CORE MEMORY
DOUBLE SYSTEM
UNIT, 9 SLOTS

KY11-D

~ PROGRAMMER's

A
B

CONSOLE

SECTIONS
D

I
SPACE FOR
ADDITIONAL MEMORY
OR PERIPHERAL
INTERFACES
5 SINGLE SYSTEM
UNITS OR EQUIVALENT

)

KD11-A PROCESSOR
DOUBLE SYSTEM
UNITS, 9 SLOTS

LEFT SIDE VIEW
(MODULE VIEW)
"-1570

Figure 6-2 PDP-I 1/40 Mounting Box (BAII-FC)

6.2.1 Processor Module Allocations

Figure 6-3 shows the module allocation for the basic KDII-A Processor and processor options. The modules noted
with an asterisk are the standard basic modules and must always be present. Other modules are optional with the
specific option designation noted on the figure. The KT1I-D Memory Management Option requires the Klll-A
M7237 module in addition to the M7236 module. The KMII-A Maintenance Console Option may be plugged into
either slot FOI or EOI, depending on whether the user is monitoring the basic KDII-A Processor or one of three
processor options (KT1l-D Memory Management, KEll-E Extended Instruction Set, or KEll-F Floating
Instruction Set). Note that the maintenance console option is not installed during normal system operation.
6.2.2 Memory Module Allocations

)

Figure 6-4 shows the module allocation for the MFll-L Memory system. The basic MFll-L Memory consists of a
single MMll-L 8K memory segment mounted on a double system unit backplane. The modules comprising the basic
MFll-L Memory are indicated by an asterisk. If two additional MMll-L 8K segments are installed in slots four
through nine as shown, the memory is expanded to 24K.
6.2.3 Programmer's Console Mounting
The KYll-D Programmer's Console is mounted on the front of the BAll-FC Mounting Box, shown in Figure 6-1.
Mounting is integral with the bezel and panel mounting. The console interfaces directly with the processor. It
provides control signals and Switch register information to the processor and receivers status and data information
and operating power from the processor.
6.3 CABINET AND SYSTEM MOUNTING

)

Because of the modularity of the PDp· 1 1/40 System, a variety of peripherals may be added to the basic system.
Depending on the type and number of peripherals selected, the unused space in the basic system cabinet may be
sufficient. If necessary, additional cabinets may be added to the system. The basic system cabinet is discussed in
Paragraph 6.3.1; multiple-cabinet systems are discussed in Paragraph 6.3.2

6-3

::0

::IE

I
I

"'T1

I
I

I
I
I
I

fT1

SMALL PERIPHERAL CONTROLLER
(USUALLY DL11)

(XI

I
I

0
--I

UNIBUS(M981)

*
STATUS M7235
*
IR DECODE M7233 *
DATA PATH M7231 *
U WORD M7232

REAR

TOP-

)

KE11-F FIS OPTION M7239

LEFT SIDE VIEW

* BASIC SYSTEM COMPONENTS
11-1381

Figure 6-3 Module Allocation - KDll-A Processor, Basic and Options

)

SECTION
F

,
I
H214 MEMORY STACK

UNIBUS

GI10 CONTROL AND DATA LOOPS

08
07

G231 MEMORY DRIVER
H214 MEMORY STACK

SLOT
09

GI10 CONTROL AND DATA LOOPS

G231 MEMORY DRIVER

*GllO CONTROL AND DATA LOOPS

*G231 MEMORY DRIVER

*H214 MEMORY STACK
UNIBUS
REAR
TOP.... BASIC MF11-L MEMORY SYSTEM MODULES

)

NOTE:
Memory in PDP-11/40 System is powered for non-interleaved and non-overlapped
situations. Successive and continuous operations to alternate 8K memary segments
is considered a prohibited overlapped situation. Interleaving is not allowed
wIthin the MF11-L or MMll-S powered by the basic box.

Figure 6-4 Module Allocation - MFll-L Memory, Basic and Optional MMll-Ls

)
6-4

6.3.1 System Cabinet
The cabinet housing the basic PDP-l 1/40 is divided into six levels (Figure 6-5). The bottom level (level six) is
reserved for cable entry, however, power supplies and the ADOl-D option may be installed there. Levels four and
five contain the BAll-FC Mounting Box which houses the basic system. Levels one through three provide space for
mounting up to three peripherals, each having a front panel height of 10-1/2 inches. If a high-speed paper-tape
reader is added to the basic system, it is always installed directly above the BAll-FC Mounting Box. There are
certain restrictions to mounting peripherals in cabinets (paragraph 6.3.2). With the basic system cabinet, any
free-standing peripheral (system I/O device, card reader, etc.) can be no further from the cabinet than the maximum
length of the interconnecting cable between the interface in the cabinet and the device itself.
6.3.2 System Configuration

)

In many cases, the number and types of peripherals added to a basic system necessitate additional mounting
cabinets. The standard cabinet layout for PDP-II systems starts at the right and evolves to the left. Another standard
practice is to define the equipment in the processor cabinet first, then move to the next cabinet not defined for a
specific device. It is always necessary to keep in mind the overall Unibus chain to keep Unibus length to a minimum.
Cooling, cabling, and logic interaction are all system considerations that must be accommodated.
Generally, configuring multiple cabinet systems requires that no full-depth device or combination of devices should
be placed at the top position (level one) or bottom position (level six) of a cabinet. This restriction is necessary to
ensure unrestricted cable entry at the bottom and proper air flow at the top. Devices can be placed in the unused
cabinet space of another device prOVided the installation does not interfere with the operation of that device. Disk
cabinets are normally used only for mounting a specific disk system and its options.

In any cabinet, the top position (level one) should be used only for rigidly fixed equipment. Levels two through five
may be used for either rigidly fixed equipment or slide-mounted equipment. In any cabinet, levels two through five
may be used for a peripheral device or for mounting an extension mounting box which is then used to house various
device interfaces at the discretion of the user. Figure 6-5 illustrates typical'mounting information for a multiple
cabinet system.

)

A major logic interaction consideration in multiple cabinet systems is latency. Latency is defined as the longest time
a device can be left unserviced before data is lost. Latency is usually a problem only in extremely large systems but
should be considered for optimum system performance. A recommended priority scheme has been established to
determine which peripherals should be mounted electrically closer to the processor to compensate for timing
characteristics of theNPR devices and latency requirements for BR devices. These priorities are listed in Tables 6-1
and 6-2, respectively. The typical mounting information of Figure 6-5 accommodates these priorities. Additional
information on system configuration is contained in PDP-ll Configuration Worksheet and the PDP-11/lO,40 Site
Preparation Worksheet.
Table 6-1
Timing Characteristics of PDP-ll NPR Devices

NPR Priority

)

1
2
3
4
5
6
7
8
9
10

Device
RKlljRK03
RP11
RC11
RF11
RKll/RK02
TMll
TCll
DM11
CD 11
DR11-B

Worst Case Latency (JIs)
8.5
11

12
13
19
29
67
100
800
Dependent on customer use

*The RP11 transfers two words each 14.8 microseconds.

6-5

Time Between Data Available (JIs)
11.1
14.8*
16
16
22.2
32 (at 800 bpi)
200
119 (at 1200 baud)

MAGNETIC TAPE DRIVES
(INDUSTRY COMPATI BlE)

DECTAPE
DRIVES
~

EXTENSION
MOUNTI NG BOXES

FIXED HEAD
DISKS

DM11-AA
TCll
CONTROL

TUlO

TU10

TUlO

TU10

TUlO

TU10

TUlO

7 OR 9

TRACK

TU56
TU56
TU56
TU56

H961

H960-E

RS64 OR
DM11-AA

RSll

RSII

RF11
CONTROL

RSII

RS11

RSll

RK05

RS1!

RSII

RSll

RK05

RC111RS64
OR
VR14

H961

CARTRIDGE
DISKS

H960-D
TMII
CONTROL TU56-H

PROCESSOR
CABINET

RKll
CONTROL VT01-A OR
VR01-A OR
BA11-ES
BAn OR
PC11

PDP- 11140
BAI1-FC

j
AD01-D

-r

CABINET
lEVELS

FREE-STANDING
lIO UNITS
CRll OR
COli
CARD
READER

2
3
4

lPll
LINE
PRINTER

94 OR 96
CHAR

~-~~-

lA30
DECWRITER

11-1572

Figure 6-5 Typical Multiple Cabinet System Configuration

'--'-/

,----,/

Table 6-2
Priority of Devices Affected by BR Latency
BR Level Priority

)

1
2
3
4
5
6
7
8
9
10
11

BR Levels
BR7

BR6

BR5

BR4

ADOI*
DTII-B

KWII·L
TCII
CRII
CMII
KWII-P
UDCllt

DPII @ 9600 baud or higher
DCII @ 1800 baud
DPII @ 4800 baud
DCII @ 1200 baud
DPII @ 2400 baud
DCII @ 600 baud
DC 11 @ 2000 baud
DCII @ 300 baud
DMll
DRII-A**
DRll-B

KLlI
UDCllt
AFCll**

*For ADO! sampling at high rates. Can be assigned to a lower level for slow input applications.
**Priority positions depend on customer application.
tUDC immediate = BR6; UOC deferred =BR4.

6.4 POWER SYSTEM

)

The PDP· 1 1/40 power system converts a single phase, 115 or 230V, 47-63 Hz line voltage to dc voltages required
by the system. In addition, the power system distributes ac power to drive cooling fans and generates power fail
early warning signals and a clock signal.
The basic power system (Figure 6·6) consists of an 861 Power Controller, an H742 Power Supply, three H744 +5V
Regulators, two H745 -15V Regulators, cooling fans, a power distribution panel, and interconnection and power
distribution cabling. One H754 +20, - 5V regulator may be substituted for an H745 if the MFII-U/UP is installed in
an 11/40 mounting box. Two H754s may replace two H745s in an expansion box. One H754 can power two
MFII-U/UP backplanes (up to 64K).

)

The power system block diagram (Figure 6·6) illustrates component interconnection and power and signal
distribution within the power system.
All power system input power flows through the 861 Power Controller. The power controller output is switched on
and off by the programmer's console OFF/POWER/LOCK switch. The H742 Power Supply and the cabinet fan
obtain 115 or 230 Vac power from the power controller output connectors. Jumper wires are used to adapt the
H742 to 115 or 230V input power. TheH742 distributes 115 Vac to the logic fans, power supply fan and regulator
fans, and 20-30 Vac to each of the regulators. The H742 also generates a +15V output, power fail early warning
signals, and clock control signals which are distributed along with the regulator dc outputs to the power distribution
panel. The power distribution panel provides a central distribution point for all dc voltages and control signals. Three
power distribution expander boxes, mounted on the panel, provide input and output connectors that route power to
the processor and memory power distribution harnesses.
The following paragraphs are detailed descriptions of power system components as well as dc power distribution.
Prints referenced in the following discussions are contained in the PDP-ll/40 System Engineering Drawings.

)
6·7

Revision 1
January 1974

.....

::l

<1>

c. 00'
po

TO
LOGIC
FANS

"' ::l
C
'<
\0
--J
~

PART OF
PROGRAMMER'S
CONSOLE
OFF/POWER/LoCK
SWITCH

SEE
NOTE 1

AC
INPUT
115V/230V

•

B61
POWER
CONTROLLER

H744
+5V
REGULATOR
(SLOT A)

H744
+5V
REGULATOR
(SLOT B)

SEE
NOTE 2~

POWER
DISTRIBUTION
PANEL

115V
115/230V

H742
POWER
SUPPLY

20-30VAC
~

H744 +5V
REGULATOR ~
(SLOT C)

.-- ....

1115vAC

POWER SUPPLY
AND
REGULATOR
FANS

----

H745
-15V
REGULATOR
(SLOT D)

H745 -15V
REGULATOR
OR H754
+20, -5V
REGULATOR
( SLOTE)

TO KD11-A
PROCESSOR

,....

TO MFl1-L
MEMORY
BACKPLANE

POWER
DISTRIBUTION
EXPANOER
BOXES
(3)

+15V, CONTKOL SIGNALS
TO
CABINET
FAN

NOTES'
1. Model 861- B used for 230V operalion
and 861-C used for 115V operation.
2. Jumpers used to adapt H742 to 115 V or
230V operation. For jumper information, see
engineering drawing D-CS-H742-0-1.

'1-1381

Figure 6-6 PDP-ll/40 Power, System Block Diagram

',,--/

''---.J

6.4.1 861 Power Controller
The 861 Power Controller centralizes control of all system power. All power for one or several equipment cabinets is
controlled by a single master switch. The ac input power cord (one per cabinet) is connected to the 861 Power
Controller; the controller also provides two sets of ac power output connectors. One set of connectors can be
switched on and off locally (via the power controller LOCAL/OFF/REMOTE switch) or remotely (via the
programmer's console OFF/pOWER LOCK switch) and is referred to as the switched ac output. The other set of
connectors provides a continuous (uncontrolled) ac output power and is referred to as the unswitched ac output. All
system units and peripherals are normally connected to the switched ac output. The unswitched ac output is
provided for peripherals that require continuous power.
The power controller also provides protection against circuit overloading and excessive heat or fire in the equipment
cabinet. If excessive current is drawn (30A @ 115V, 20A @ 230V), the input circuit breaker trips and all input
power is removed. If there is excessive heat in the cabinet (I60°F), the therml;ll switch closes and removes power
from the power controller switched ac output.

)

For a complete description of the 861 Power Controller, refer to the 861-A, B, C Power Controller Maintenance
Manual, DEC-00-H861A-A-D. Note that the PDP-ll/40 uses model 861-BJor 230V operation and model 861-C for
115V operation.
For information on interconnecting 861 power controllers installed in separate equipment cabinets plus information
on connecting the H720 Power Supply to 861 Power Controller, refer to Paragraph 6.4.5.

6.4.2 H742 Power Supply
.The H742 Power Supply is functionally divided into two major parts:

)

Power Supply (drawing D-CS-H742-0-l) - used to provide the various ac input voltages required by tp,
fans, regulators, and power control board.

Power Control Board (drawing C-CD-5409730-0-l) - used to provide +15V, line clock, and AC LO apr
DC LO signals for system use.

The PDP-11/40 power system operates with 115 or 230 Vac primary power inputs. Although different models of the
861 Power Controller are used, only one power supply (H742)is necessary. Jumpers are used onthe H742 terminal
strip (TB 1) to adapt it to a 115 or 230 Vac primary power. If 115 Vac primary power is used, jumpers are placed
between pins 1 and 2, and between pins 3 and 4 of TBI. If 230 Vac primary power is used, a jumper is connected
between pins 2 and 3.
Line power is applied through TBI to the primary of transformer Tl. The transformer secondaries provide 20-30
Vac and 15-24 Vac input power for the power control board and 20-30 Vac for the regulators. Power to cooling.
fans is taken from transformer primary. 115 Vac is provided for fan operatiop with either 115 or 230 Vac prime
power input.
The power control board portion of the power supply (drawing C-CS-5409730-0-1) provides a +15V output to
power the Small Peripheral Controller, a clock output used to drive the KW11-L or KW11-P clock option, and the
AC LO and DC LO control signals used to warn the processor of imminent power failure. The power control board
circuits, which generate these outputs, are discussed in Paragraphs 6.4.2.1 through 6.4.2.3.

)
6-9

6.4.2.1 H742 +lSV Output - The power control board of the H742 Power Supply contains a +15V!+8V dc supply
and is shown on print C-CS-5409730-0-1. This dc supply receives 15-24 Vac from the secondary of transformer TI.
This ac input is full-wave rectified by qiode bridge D 1. The resultant dc is applied to Darlington power amplifier Q 1,
through fuse FI. The bias on Ql is controlled to provide +15 Vdc at output pins 2 and 3 with respect to output pins
4, 5, and 6 (ground). If the Ql collector voltage starts to increase, the bias at the base of Q2 increases, and Q2
conducts slightly more current to maintain a constant output voltage. Zener diode D7 provides approximately +8
Vdc at output pin 1. The +8V output is not used in the PDP-ll!40 System. When DC LO is grounded at output pin
9, Q2 conducts hard to cut off Ql completely, thus removing the +l5V output.

-\
)

6.4.2.2 H742 Oock Output - The CLOCK output is derived off one leg of full-wave rectifier bridge Dl by voltage
divider RIO and Rll, and Zener diode D2. The CLOCK output is.a 0 to 5V square wave at the line frequency of the
input power source (47 to 63 Hz). The CLOCK output is used to drive the KWlI-L Line Time Clock Option, which
mounts in slot F03 of the processor backplane or the KWII-P option, which can be mounted in the Small Peripheral
Controller slot. Operation of the KWll-L option is described in the KWll-L Line Time Clock Manual,
EK-KWllL-TM-002; operation of the KWII-P option is described in the KWII-P Programmable Real-Time Clock
Manual, EK-KWIIP-MM-002.
6.4.2.3 AC LO and DC LO Circuits - The AC LO and DC LO control signals are used to warn the processor that a
power failure is imminent, allowing the processor time to perform a power-fail sequence. If there is an ac power
failure (line power or pOWer supply failure), AC LO is asserted on the bus followed by DC LO. Sufficient time exists
between these signals to allow storage of volatile data and the conditioning of peripherals. Note that the DC LO
control signal is also used by the MFII-L Memory to inhibit memory operation.

)

The 20-30 Vac input from the secondary of transformer T1 is applied to the AC LO and DC LO sensing circuits on
the power control board. The ac input is rectified and filtered by diodes D8 through Dl1 and capacitor C3. A
common reference voltage is derived by resistor R18 and Zener diode D12. Both sensing circuits operate in a similar
manner, and each contains a differential amplifier, a transistor switch, and associated circuits. The major difference)
is that the base of Q6 in the AC LO circuit differential amplifier is at a slightly lower value than that of Q9 in the DC
/
LO differential amplifier. The operation of both sensing circuits depends upon the voltage across capacitor C3.
When AC LO is being sensed, the 20:...30 Vac input is rectified and stored in capacitor C3 which charges and
discharges at a known rate whenever the ac power is switched on or off. Thus, the voltage that is applied to the
emitters of differential amplifier Q6/Q7 through R17 is a rising or falling waveform of known value. For example,
when power fails or is shut down, the dc voltage decays at a known rate as determined by the RC time constant. If
the voltage decreases to apptoximately 20V, the base of Q6 becomes negative with respect to the base of Q7. The
increased forward bias on Q6 causes it to conduct more and the resultant decrease in Q7 causes it to cut off. This
removal of voltage across R16 causes Q5 and Q4 to conduct, grounding the AC LO line at pin 8. The AC LO signal is
applied through the cable harness and processor backplane to the processor power-fail initialize logic so that the
power-fail sequence can be started.

The DC LO sensing circuit operates in a similar manner to the ACLO sensing circuit. The prime difference being the
voltage level at which they "trip." For example, if the ac input starts to decrease, as a result of a power failure or
shutdown, the AC LO lines are grounded before the DC LO lines. As power is restored, the ground is removed from
the DC LO lines before it is removed from the AC LO lines. The DC LO signal is also applied to the power-fail
initialize logic.
A description of how the AC LO and DC LO control signals are used in the KDl1-A Processor is provided in the
KDII-A Processor Maintenance Manual. For a description of how the DC LO control signal is used by the MFII-L
Memory, refer to theMMll-S,MFll-F, andMFII-LPCoreMemory System Manual.
6.4.3 H744 +SV Regulator
Two H744 +5V Regulators are used in the basic PDP-ll/40 power system. The H744 circuit schematic is shown in
drawing D-CS-H744-0-1. The following paragraphs describe the regulator circuit, overcurrent sensing circuit, and
overvoltage crowbar circuit.
6-10

)
..

)

6.4.3.1 H744 Regulator Circuit - The 20-30 Vac input is a full wave which is rectified by bridge Dl to provide a
dc voltage (24 to 40V, depending on line voltage) across filter capacitor C 1 and bleeder resistor RIo Operation
centers on precision voltage regulator El which is configured as a positive switching regulator. A simplified
schematic of El is shown in Figure 6-7. Regulator El is a monolithic integrated circuit that is used as a precision
voltage regulator. It consists of a temperature-compensated reference amplifier, error amplifier, series-pass power
transistor, and the output circuit required to drive the external transistors. In addition to El, the regulator circuit
includes pass transistor 02, pre-drivers 03 and 04, and level shifter 05. Zener diode D2 is used with 05 and R2 to
provide + 15V for E 1. 05 is used as a level shifter; most of the input voltage is absorbed across the collector-emitter
of 05. This is necessary since the raw input voltage is well above that required for El operation. This +15V input is
supplied while still retaining the ability to switch pass transistor 02 on or off by drawing current down through the
emitter of 05.

V+

)

INVERTING
INPUT
V REF

FREQUENCY
COMPENSATION

0----------+--.,
0---..--------,

, - - - - - - - - 0 Vc

SERIES PASS
TRANSISTOR

....._-----0 V OUT
'------ovz

)

NON INVERTING o------+~-------'
INPUT

V-

CURRENT CURRENT
LIMIT
SENSE
11-0965

)

Figure 6·7 Precision Voltage Regulator El, Simplified Diagram

The output circuit is standard for most switching regulators and consists of "free-wheeling" diode D5, choke coil Ll,
and output capacitors C8 and C9. These components make up the regulator output filter. Free-wheeling diode D5 is
used to clamp the emitter of 02 to ground when 02 shuts off, thus providing a discharge path for Ll.
In operation, 02 is turned on and off generating a square wave of voltage which is applied across D5 at the input of
the LC filter (Ll, C8 and C9). This type circuit is basically only an averaging device, and the square wave of voltage
appears as an average voltage at the output terminal. By varying the period of conduction of 02, the output
(average) voltage may be varied or cOhtrolled, thus supplying regulation. The output voltage is sensed and fed back
to El where it is compared with a fixed reference voltage. El turns pass transistor 02 on and off according to
whether the output voltage level decreases or increases. Defined upper and lower limits for the output are
approximately +5.05V and +4.95V.

)
/

During one full cycle of operation the regulator operates as follows: 02 is turned on and a high voltage
(approximately +30V) is applied across Ll. If the output is already at a +5V level, then a constant +25V would be
present across Ll. This constant dc voltage causes a linear ramp of current to build up through Ll. At the same time,

6-11

output capacitors C8 and C9 absorb this changing current and voltage, causing the output level (+5V at this point) t o )
increase. When the output which is monitored by EI reaches approximately +5.05V, EI shuts off turning Q2 off,
and the emitter of Q2 is clamped to ground. L1 discharges into capacitors C8, C9, and the load. Pre-drivers Q3 and
Q4 are used to increase the effective gain of Q2 to ensure that Q2 can be turned on and off in a relatively short
period of time.
Conversely, once Q2 is turned off and the output voltage begins to decrease, a predetermined value of approximately
+4.95V will be reached causing El to tum on which in turn causes Q2 to conduct, beginning another cycle of
operation. Thus, a ripple voltage is superimposed on the output and is detected as predetermined maximum
(+5.05V) and minimum (+4.95V) values by El. When +5.05V is reached, EI tl,lms Q2 off and when +4.95V is
reached, El turns Q2 on. This type of circuit action is also referred to as a "ripple regulator;"
6.4.3.2 H744 Overcurreut Sensing Circuit - The overcurrent sensing circuit consists of: QI, R3 through R6, R25,
R26, Q7, and C4. Transistor Ql is normally not conducting; however, if the output exceeds 30A, the forward
voltage across R4 is sufficient to turn Ql on, causing C4 to begin charging; When C4 reaches a value equal to the
voltage on the anode gate of Q7, Q7 turns on and El is biased off, turning the pass transistor off. Thus, the output
voltage is decreased as required to ensure that the output current is maintained below 35A (approximately) and the
regulator is "short-circuit" protected. The regulator continues to oscillate in this new mode until the overload
condition is removed.

)

6.4.3.3 H744 Overvoltage Crowbar Circuit - The overvoltage crowbal," circuit consists of the following
components: Zenerdiode D3, silicon-controlled rectifier (SCR) D7, D8, R22, R23, C7, and Q6.
Under normal conditions, the trigger input to the SCR (D7) is at ground because the voltage across Zener diode D3
is too small to cause it to conduct. As the +5V line approaches 6V, Zener diode D3 conducts and the voltage drop
across resistor R23, draws gate current, and triggers the SCR. The SCR shorts the +5V line to ground through
resistor R21, which is a current-limiting resistor. The SCR remains on until the capacitors discharge.

)

6.4.4 H745 -15V Regulator
Two H745 -15V Regulators are included in the PDP-ll /40 power system. Operation of the H745 is basically the
same as that of the +5V regulator. TheH745 schematic is shownin drawing C-CS-H74S-0-1. Input power (20 to 30
Vac) is taken from the secondary of transformer T1 and applied to the full·wave bridge rectifier (dl). The output of
Dl is a variable 24 to 40 Vdc and is applied across capacitor Cl and resistor Rl. The following paragraphs discuss
the regulator circuit, overcurrent sensing circuit, and the overvoltage crowbar circuit.
6.4.4.1 H745 Regulator Circuit - Regulator operation is almost identical to that of the +5V regulator; however,
the +15V input that is required for operation of El is derived exter\1ally and is applied across capacitor C2 to El and
the inverting and noninverting inputs to El are reversed. In addition, the polarities of the various components are
reversed. For example, Q5, which is used as a level shifter, is an NPN transistor on the +5V regulator but a PNP is
required on the -15V regulator to allow the regulator to operate below ground (at -lSV).

)

Under normal operating conditions, regulator operation centers around linear regulator El and pass transistor Q2,
which is controlled by El. Predetermined output voltage limlts are -14.85V (minimum) an.d -15.15V (maximum).
When the output reaches -15.15V, El shuts off, turning Q2 off, and L1 discharges into C8 and C9. When the output
reaches -14.85V, El conducts, causing Q2 to turn on, increasing the output voltage.
6.4.4.2 H745 Overcurrent Sensing Circuit - The -15V regulator overcurrerit sensing circuit is basically made up of
the same components as the +5V regulator except Ql is an NPN transistor in the -15V regulator. Transistor Ql is
normally not conducting; however, once the output exceeds 15A,Ql turns on and C3 charges. When C3 reaches the
same value as the anode gate of Q7, Elis biased off, which turns Q2 off, thereby stopping current flow and turning
the -15V regulator off. Thus, the regulator is short-circuit protected.

)
6-12

6.4.4.3 H745 OvervoItage Crowbar Circuit - When SCR D5 is fired, the -15Y output is pulled up to ground and
latched at ground until input power, or the +15Y input is removed. A negative slope on the +15Y line can be used to
trip the crowbar for power-down sequencing, if desired.
6.4.4a H754 +20, - 5Y Regulator
If the system contains an option requiring +20 and - 5Y, such as the MFll-U/UP, H754 regulator(s) must be added.
They are mounted into slot Eof the PDP-l 1/40 cabinet or into slots D and/or E of an expander cabinet. Note that
the installation of an H754 reduces the amount of available -15Y power, because an H745 must be removed.
a.

The output of the basic regulator is 25Y (-5 to +20Y). The shunt regulators are connected across this
output, with a tap to ground between pass transistors Q9 and QIO. The voltage at the bases of Q6 and
Q4 will vary with respect to ground, depending on the relative amount of current drawn from the +20Y
and - 5Y outputs of the regulator. If the +20Y current increases, while the - 5Y current remains
constant, the output voltage at the +20Y output will tend to go more negative with respect to ground;
this will cause the - 5Y output to go more negative also, since the output of the basic regulator lS a fixed
25Y. This change is sensed at the bases of Q6 and Q4; Q6 will conduct, causing Q9 to conduct also, thus
increasing the current between - 5Y and ground until the balance between the +20Y and the - 5Y is
restored. At this time, neither Q6 nor Q4 will be conducting. If the -5Y current increases, Q4 and Q10
will conduct to balance the outputs.

)

Regulator Circuit - The circuit (refer to schematic D-CS-H754-0-l) is very similar to that of the other
regulators: like the H746, it has a voltage doubler input, but the output consists of two shunt regulator
circuits, one for the +20Y, the other for the - 5Y. The +20Y shunt regulator consists of transistors Q4,
QIO and Ql1; the -5Y shunt regulator, ofQ6 and Q9. Q10 and Q9 are the pass transistors.

Overvoltage Crowbar Circuits - There are two crowbar circuits in the H754: Q7 and its associated
circuitry for the +20Y, and Q12 and its circuitry for the -5Y. Either one will trigger SCRD9.

Overcurrent Sensing Circuit - The overcurrent circuit is comprised of Ql, Q8, Q13, Q14, and associated
circuitry. The total peak current is sampled through R4. When the peak current reaches approximately
l4A, Ql turns on sufficiently to establish a voltage across R7 and R38, thus firing Q8. This pulls the
voltage on pin 4 of the 723 up above the reference voltage on pin 5, thereby shutting off Q2. D6 now
conducts, and the current through R37 turns on Q14, which turns on Q13. This keeps Q8 on for a time
which is determined by the output voltage and Lt. This action, in turn, allows the off-time of Q2 to be
greater than the on-time; the off-time increases as the overload current increases, thereby changing the
duty cycle in proportion to the load. The output current is thus limited to apprOXimately IOA.

Voltage Adjustment- The +20Y adjustment is located on the side of the H754; and the -5Y
potentiometer is on the top, next to the connector. To set the output voltages: power down, disconnect
the load, power up, adjust for a 25Y reading between the +20 and -5Y outputs with the 20Y
potentiometer, then set the -5Y between its output and ground. Power down, reconnect the load, power
up, and then check and adjust the outputs again. This procedure is necessary because the +20Y
potentiometer (R17) actually sets the overall output of the regulator (25Y from +20 to - 5Y), while the
-5Y adjustment (R2l) controls the -5Y to ground output. Refer to schematic drawing D-CS-H754-0-1.

,.)

6.4.5 861 Power Controller Interconnection
The 3-pin Mate-N-Lok connectors on the 861 Power Controller serve a multiple purpose. They are used along with
the power controller bus cabling to (Figure 6-8):
a.

)

connect the programmer's console OFF !POWER/LOCK switch to the 861 Power Controller, thus
enabling remote control.

6-13

Revision 1
January 1974

interconnect 861 Power Controllers in adjacent equipment cabinets when more than one cabinet is used
in a system, thus enabling all power controllers to be controlled by the programmer's console switch.

connect Hno Power Supplies to the 861 Power Controller (Hno Power Supplies must be used
whenever PDP·ll/20 memories are used in the PDP-II /40 System).

connect optional cabinet-mounted thermal switches (cabinet-mounted thermal switches must be
connected to pin 2 of any available connector, normally the same connector used for the programmer's
console switch).
JUMPER PLUGS

7007 006-2-[l
1

2 3)

1 2

70070061

J2
LOCAL
H720E/F
(OPTIONAL)

)
AC PRIMARY
POWER"

i'l-SWITCHED AC
OUTPUT
CONNECTOR
861
POWER C.oNTROLLER
(APDITIONAL CABINET)

861
POWER CONTROLLER
(PROCESSOR CABINET)
1 2

3) (1

I
70090
5~.........
CAB LE

PDP-11/40
CONSOLE
(KYII-D)

1 2

:J
2

3) ( 1

I I
.'

861
POWER CONTROLLER
(ADDITIONAL CABINET)

II
I

)

7008964_
CABLE
7008288
CABLE
1 f-----<

CABINET MOUNTED
THERMAL SWITCH
(OPTIONAL)

2
H720
ElF
REMOTE
(OPTIONAL)

NOTES:
1. The optional H720 ElF power
supply may be connected
in either of the two
configurations shown.
2. No terminators are needed
on the unused pins of the
MATE-N-LOK connectors

r--

I'-'
Ir-

1 r---2 r--

)

3f-

1
2
AC PRIMARY"
POWER

H720
ElF
REMOTE
(OPTIONAL)

I'-'
h
1
2

3
7007006-1
L ASTH720 IN LINE
MUST BE JUMPER EO

Figure 6-8 Power Control Interconnection
Revision 1
January 1974

6-14

11 1118

)

6.4.6 Power System Cable Harnesses
TIle overall layout of the PDP-l 1/40 power system is shown in Figures 6-10 for the early systems, and 6-13 for the
newer ones. Four cable harnesses are shown on these drawings, which interconnect all power system units and
provide power to the logic fans and the KDII-A Processor and MFIl-L Memory backplanes. These harnesses and
their functions are listed below:
a.

H742 to 11/40 Power Harness - interconnects the H742 Power Supply, the H744 and H745 regulators,
the logic fans and the power distribution panel (refer to Figures 6-11 and 6-14 for detailed wiring
information on these harnesses).
Harness Numbers:

Console to Power Controller Harness - connects programmer's console OFF/POWER/LOCK switch to a
3-pin Mate-N-Lok connector on the 861 Power Controller (enables system power to be turned on and
off by the programmer's console switch).
Harness Numbers:

)
c.

)
i

OLD: 7009053; NEW: 7009053

PDP-l 1/40 Processor Power Harness - routes dc power and control signals from the power distribution
panel to the KD Il-A Processor backplane.
Harness Numbers:

OLD: 7008754; NEW: 7009566

OLD: 7009046;NEW: 7009564

First Memory (11/40) Power Harness - routes dc power and control signals from the power distribution
panel to the basic MFll-L Memory backplane.
Harness Numbers:

OLD: 7009103; NEW: 7009565

A fifth cable harness, not shown on Figures 6-10 and 6-13, is used to connect any additional MFll-L Memories that
may be installed in the basic BAll-FC Mounting Box to the power distribution panel. This harness is referred to as
the MFll-L Power Harness (BAll-FC) and its cable number is 7009174 (OLD) or 7009560 (NEW).
If any DDII type system units requiring the G772 module are installed in the basic BAll-Fe Mounting Box, they
are connected to the power distribution panel by cable harness 7009177 (OLD) or 7009562 (NEW).
\

For additional information on the DDII system unit and its installation, refer to Chapter 2 of the PDP-II
Peripherals Handbook.
Appendix A lists all system unit power harnesses.
6.4.7 DC Power Distribution
Two different power distribution systems may be found in the PDP-l 1/40 and H960-D, -E Expansion Cabinets. The
newer systems (serial number 6000 and higher) are easily distinguished from the older ones by observing the
BAll-FC Mounting Box (see Figure 6-1): the newer machines have a horizontal power distribution panel, while the
early ones have a vertical one. Harness numbers for the various system unit options are given in Appendix A.
The early systems are explained in Paragraph 6.4.7.1; the newer ones in Paragraph 6.4.7.2.

6-15

6.4.7.1 Early Power Distribution Systems (Refer to Figures 6-9 and 6-10) - DC power and control signals
generated by the H742 Power Supply and the H744 and H745 regulators are distributed to three power distribution
expander boxes that are mounted on the power distribution panel (Figure 6-9). Each expander box contains two
input connectors and three output connectors. The three output connectors are wired in parallel, and all signals
applied to the input connectors are applied to each of the output connectors.
Expander boxes.. El and E2 distribute power to the KDl1-A Processor and the MFll-L Memory backplanes.
Connector n receives dc power from the +5V regulator in slot A and the -15V regulator in slot E. This power is
distributed through output connectors 1 and 3 and is totally committed to the KD 11-A Processor and MF 11-L
Memory. Connector 13 receives dc power from the +5V regulator in slot B and the -15V regulator in slot D. Output
connector 4 distributes +5V to the MFII-L Memory. Note that a 24K MF ll-L Memory only requires 6.4A of +5V
. power, leaving 13.6A for distribution to expansion units.
Expander box E3 distributes power for expansion units. Connector J5 receives power from the +5V regulator in slot
C and the -15V regulator in slot D. Care must be taken when connecting expansion units to avoid overloading the
-15V regulator which is also connected to J3 on expander box E2.
Note that the H742 +15V and control signal outputs are not shown on Figure 6-9. The +15V output is applied to
input connectors n, J3, and J5. The control signal outputs are applied to input connectors J2, J4, and J6. Refer to
Figure 6-11 for detailed information on the power distribution (harness 7008754).

)

In the case of an 11/40 CPU cabinet only (not in an H960-D or -E expansion cabinet), the Console to Power Control
harness 7009053 is tied in with the main power harness. .

-15V,10A
REGULATOR
SLOT E

+5V,20A
REGULATOR
SLOT A

POWER DISTRIBUTION
PANEL

+5V,20A
REGULATOR
SLOT B

1-5V,20A
REGULATOR
SLOT c
(OPTIONAL)

-15V,10A
REGULATOR
SLOT 0

)

- - - - - ---.., r-------------, r - - - - - - - - ---...,

I
I
L

E1
2

II
II
II

_ _ _ _ _ _ -' L..

-15V*
KDll-A
+5V",20A
-15V,,, lA

BI I
E3
I
J4 110
J5J6 I
_ _ _ _ _ _ _ _ _ _ _ ._.JI I
L... _ _ _ _ _ _ _ _ _ _ _ _ .JI

0E2

)

+5V

MFll-L
(SEE BELOW)

MF11-L POWER REQUIREMENTS (NON - INTERLEAVED)
There are only two wires
on this cable one blQck,
one blue.

BASIC MEMORY

OPTIONAL MEMORY

16K

24K

+5V,,, 3.4A

+5V'" 4.9A
-15V,,, 6.5A

-15V,,, 7.0A

-15V,,, 6.0A

+5V," 6.4A

11-1717

Figure 6-9 Regulated DC Power Distribution

)
Revision 1
January 1974

6-16

-.,,---/

,-,'

,----../

CONSOLE TO 861 POWER CONTROL
HARNESS # 7009053

CONSOLE TO 861 POWER CONTROL
HARNESS. 7009053

rt'
,...
-..,J

Two!Jf ires on IV

on t~jl coble,

-blue -and blaek

TO. SWITCfiED
OUTLET
POWER CONTROL

11-2::f09

Figure 6-10 Power Distribution - Early Units
with System Serial No. 5999 and Lower

Installation of MFI1-U/UP in Early Units (See Figure 6-12) - A 7009569 conversion harness must be used between
the H754 +20, - 5 V dc regulator and the backplane, in addition to a 7009568 harness between the backplane and the
~ower Distribution panel. One 7009569 can power two MFl1-U/UP backplanes. If only one backplane is used, the
Jumpers to the second backplane should be cut. One 7009568 harness is required per backplane.

)

The H754 Regulator should be installed in slot E; the blue -15V wire between Pl-l and P 15-1 should be removed' a
jumper wire should be installed between Pl-l and P3-2. This will allow the H745 in slot D to supply -15 Vdc to the
entire box.
The FMI1-U field modification kit permits installation of up to two MFII-U/UP backplanes of 16K memory.
Refer to the field modification kit print set for installation procedures (DD-FMII-U).
6.4.7.2 Newer Power Distribution Systems (Refer to Figure 6-13) - Three 5410590 Power Distributors transmit
the power generated by the H742 and its voltage regulators to the system units. Each distributor has five IS-pin
power and five 6-pin signal connectors. Two of the power connectors on each distributor are used by the harness
plugs, thus leaving three for connection to system units. The 6-pin signal connector is used only on the 5410590
Power Distributor closest to the CPU. A jumper harness connects the 6-pin plugs on the other distributors to this
one (harness number 7009573).
The two power distributors closest to the front of the mounting box handle power for the KDII-A Processor and to
the first MFII-L Memory. The CPU gets its +5 Vdc from the H744 in slot A and its -15 Vdc from the H745 in slot
E. The MFII-L, as in the early power distribution system, gets its +5 Vdc from the H744 in slot B and its -15 Vdc
from the H745 in slot E. The KDl1-A uses harness number 7009564, and the first MFI1-L number 7009565, to
connect to the power distribution panel. The first MF l1-L is connected as follows: the -15V connector (15 pin, 2
wire: blue and black) and the 6 pin signal connector plug into the first power distributor (the same one as the
KDII-A); the +5V connector (the other 15 pin) plugs into the second power distributor. Any additional MF ll-Ls
require harness 7009560 and obtain power from a single power distribution connector, as would any other system
units in the mounting box.

)

Figure 6-14 shows details of the new power distribution system (harness 7009566). Note that in the case of an
11/40 CPU cabinet only (not in an H960-D or -E expansion cabinet) there is a Console to Power Control harness
7009053 which is tied in with the main power harness.

)

)
6-18

PII

Pll
PB-I
PB-2

'6
7

loy

~
H744
+5V REGULATOR

2
3
;

.
PI-7
Pl-B

Pl-~

Pl-l0

-......

Itt
SLOT A
PB

~
H742
BULK SUPPLY

2
7
B

PII-6
P11-7
P14-6
PI4-B

"
-......
-......

Pl0-1P~
PIO-2

)

P5-11
P14-5
P14-2
P15-3

PIO
f'-' P12-6
1
PI2-7
2
5
6

PI2
~ P3-7
3 P3-B
H744
+5V REGULATOR

P3-~

P3-10

~
SLOT B

P5-6
6
P6-6
7
P6-12
B
P6-7
12
P6-2

)

~9
2
3
4
5

P7-1
P7-2

P13-6
B
P15-6
9 P13 -7
10
PI5-B
12

-.....,
"

......
......

-......

-.....,

VPI3
Pl0-B --;
PIO-l0
7

......
......
......

PI3

fH744
+5V REGULATOR

2
3
4
5

P5-7
P5-B
P5-9
P5-10

"
"
V- P4-2
V-

......

PB-7P~

"
-......
"............

PB-B

f'-'

P4-6

P14

H745
-15V REGULATOR

I
2

~
5

P5-1
P9-4
P5-3
P15 -14
P9-3

V-

-......

""
"

)

P4 -7
P4-12

V-

P9-7
P9-12

P9-B

H745
-I5V REGULATOR

I
2

PI-I
PI-3
P9-5
P14-4

P12-2

+5V C REG

P12-3

GND
GND
I
+5V C REG i
I
I

P12-4
P12-5

VV- P5-12
V- PI -11

I
I

LCLK

P6-3

V-

P2-2

4
5

GNO

OCLO

B
9
10

OCLO

ACLO

P2-6
I

GNO

5
6

GNO
GNO

+5V B REG

GNO

P15-2

---------------

9
10

GNO
+5V B REG

II
12

+15V
+15V

P3-5
Pl1-2
P1t-3
PI'-4
P11-5
P3-12

V- P6-5
V- P6-1O
V-

P2-12

V
,

P6-11

3
4
5
6
7

GNO

GNO
+5V A REG

GNO

+5V A REG

11
12

+15V

~
1
2

1
2

LCLK

GNO

OCLO

P4-3

LCLK

4
P4-5
P4-10

B
P2-7

-I5V E REG

'---

I
2

2
3
4

PI5-1~

P15

PI-6
P5-5

GNO
GNO

+15V
+I5V

P3
P5-2 ,...;-15V DREG
I
P5-4

GNO

L...--

P15
Pl0-9 ,.....
6
Pl0-12
B

,,-

GNO

~
P9-11

-......
......

-15V 0 REG'
-15V 0 REG:

'---

SLOT C

SLOT 0

P5
PI4-1""':"':'"
1
P3-1
2
P14-3
3
P3-3
4
P3-6
5
P9-6
6
P13-2
7
P13-3
B
P13-4
9
P13-5
10
P9- 2
II
P3-1t
12

-......

GNO

OCLO

9
10

OCLO

ACLO

9
10
P4- 11

'---

11
12

ACLO

L.--

./
./

SLOT E

,..fL
Pl0-5
Pl0-6

1
2

} 115V AC TO
LOGIC FANS

I
'---

./
11-2305

Figure 6-11 Power Distribution Schematic - Early Systems'
(Sy'stem Serial No. 5999 and lower)

)
6-19
Revision 1
January 1974

I
I

I
,\

9 PIN
,
CONVERSION HARNESS
7009568 (I PER MFII-U/UP
BACKPLANE)

NOTE 1

IN EXPANDER BOX,
PLUG MF11·U/UPsIN
SLOTS:
SU2&5V3,or
SU5&SU6,or
SU8&SU9
IN t"40CPU BOX,
PLUG MF n.U!UPJ IN
SLOTS:
SUS& SU6,or

SU8&SU9
NOTE 2; a. WHEN REMOVING
SLOT E H745 TO
INSTALL H754 AND
CONVERSION HARNESS,
THE BLUE 15 V WIRE
IFROM P15) MUST BE
REMOVED FROM Pt·'
AND A JUMPER WIRE
ADDED FROM Pl·' TO
P3·2, TO PERMIT THE
SLOT 0 H745 TO PROVIDE
15 V TO THE ENTIRE

)

BOX.
h. THE REO AND WHITE
AC WIRES MUST BE
REMOVED FROM P15
PINS 6 AND 8 AND
PLUGGED INTO PINS 7
AND 8 Of REGULATOR
HARNESS 7oo95.s9.

NOTE 3;

Figure 6-12 MFII-U/UP Installation - Early Systems

Revision 1
January 1974

6-20

)

IF ONLY ONE MF11-U/UP
IS USED, CUT THE UNUSED
JUMPER WIRES AT THE
CONNECTOR TO PREVENT
POSSIBLE SHORT CIRCUITS.

)

CONSOLE TO 861 POWER CONTROL
HARNESS'" 7009053

RED
BlK

POWER DI5TR I BUTION
PANEL

)
SU

~P1B

KDl1-A HARNESS
7009564
pLUG INTO 1ST
POWER
DISTRIBUTOR

)

• If the first memory is an MF11 L/LP, the --15 V plUII
(blue and black wires only) goes to the SU-3 socket;
the other lS-pin plug connects to SU-4 jack. _. If the
first memory is an MF11·U/UP. the 15-pin plug
connects to SU·4 jack.

POWER
HARNESS
7009566

WIRING 51 DE

@
006
00

OPTION POWER CONNECTO.R5
PIN ASSIGN MENTS
1. GND
-BlK
2. LINE ClOCK-BRN
3. DC lO
-VIO
4. AC lO
-VEL

5.
6.

)

1.+5V-RED
2.+15V-GRY
3.+20V-ORN
4.+5V -RED
5. GND - BlK

6.
7. GND-BlK
8.GND -BlK

9.GND-BlK
10.
11.GND -BlK
12.
13.-15V -BlU
14.-5V -BRN
15.

TO SWITCHED
OUTLET
POWER CONTROL

11-2310

)

Figure 6-13 Power Distribution - Newer Unit
with System Serial No. 6000 and Higher

6·21

Revision 1
January 1974

- -H74z--1
,E!!,......-----H--7--4-4-----.!,E..~1I

BULK SUPPLY I
REF ONLY 1

=RED PIO-I

XWHT P10-2

SECO NOARY -H 742

5409730
JI
POWER. rI-i~
CONTROL tBV
I
BOARD tl5VI
2 P5-2 GRY
3 P14- 5 GRY
.15V2
4 P14-2 BlK
GNDI
2
5 P15-3 BlK
GND2
6 P5-5 BlK
GND3
7 PIB-I SHlD
lOGND

C
l5

7 AC6
8

DC l02

H-744
'5V

6
7
9

RED
GRY

PI-7 8lK
P2-7 BlK
P2-1 RED

P,.@

AC2 P12-7
WHT·
'-'

nRED PIO-S

H-744
t5V

6 AC7

XWHT PIO-IO

7 AC8

'-'

2
3
4
5

P3-1
P3-7
P4-7
P4-1

PI3
+5V CI 2 P5-1 RED
GND CI 3 P5-7 BlK
GND C2 4 P6-7 BlK

~12

8 AC7 P13-6
RED

20-30
VAC

S AC3

XWHT ps-s
. '--'BLK P9'4
GRY P15-4
GRY P9- 3

AC4
2 GND I
4 +15V 3
5 +15V2

SPARE 2
GND 01

SPARE"'3

BlU

P14-1

BRN

P2-14

13 -15V 01
14 -5VJ3

-5VI

P6-1 RED

H-745
-15V

AC 10
GND2

GRY P14-4

+15V 3

P13-5

GRY
ORN

P4-2
P4-3

AC7

BlK

P13-4

AC8

BlK

P2-

BLK

P2-9

BlK

P4-11

BlU

P4-13

PI?
-15VDI I
GNDDI 3

P5-13 BlU
P5-IIBLK

QBLK PI-II

QORN PI-3
SLOT 0

I
2
3

)

rlA'P

J-~N

+20V2

GND 4
SPARE"!
GND C2

GND 5

9
10

GND 6
SPARE"2

P4- ~~ 14 - 5V3
15

1L9.:L---

AC9

,,-------

ACIO

GNO

P12-3
PI- B

BlK

PI- 9

10 SPARE~
II GNO 10

lr~~LJ.-!:.I::!~

12 SPARE"'3
13 -15VJ1

BRN

P16- 3

TWP

GND 9

BlK Pl6-2

14 5VI
15 SPARE#3

RED

P12-5

PI .5V B2

GRY
ORN

P6-2
P6 -3

2 tl5V 5
3 +20V3

SPARE#3

BlK
BLK

P6-5
P12-4

5
6
7

GND 4 Ii'
SPARE I
GND B2

BLK

5 GND

BlK

PII-3

6 SPARE"!
7 GND AI

BlK
BlK

P3-B
P3- 9

B GND 8
9 GND 9

~~_~~-L3
BRN

12 SPARE"3
13 -15VJ 1

P17-3

14 -5V2
15 SPARE""3
'-

RED

PII-5

~~I~

CABLE

I,J

DEC 91077~1

5VA2

.2~N.. _P":;=.3_

20VJ2

5 GND
6 SPARE'*i
Ir=Bc::l:..:K_..:.P..:.1:...1-_4"--1 7 GND A2
v=:B"'lK"----'-PS"-.-",S-1 S GND 5
B:::.
l :..:.
K _-,-P..::6_-..:9--j 9 GND 6
Ir:

10 SPARE#2
II GND 7

IrB:=L",K_-,-P.:c15=---,Z'--l11

PS-II

BLU

P6-13

13 -15V2

BRN

P6-14

14 -5V 3
15 SPARE*'3

10 SPARE"'2
GN D EI

12 SPARE"'3
,,=B:=l=U_-,-P.;.c15=--...c1'--j12 SPARE#3
13 -15V EI
"
~~N_ .!.:?-..!.~ 14 -5VJ3

LI NE ClO C K

LlNEZ TO FANS

DC lO I
AC LO I

3
4

1r--+--+-::Pc:9c:-:=,S-I4
RED
P..:,9--7'::--l I
1r--"""'-'::c
SHlD

r-r--.

CABLE
{
DEC 9107574

lO GND

SLOT E

)

RED

*EHl- --\

115 VAC
-

5
6
4

- - - -

I---

II
1-'--'-c:"-1f-I--'
~I~:l
WHT

------'

Figure 6-14 Power Distribution Schematic - Newer Systems
(System Serial No_ 6000 and Higher)

115 VAC TO H742 FANS

.i.

~TI ~}

II
13
14
15
L-

o P22

-1'

115 VAC

ACIOW~~-8 ~

)

15 SPARE#3
'--

1r--+--+-;~:7~'-,~C'12=--j

)

4 .5V

P9- II
1r--+--+"'B"'l-;:K;-,-,2

~:~~SISG~

2 +15V

(FEMALE)
HOUSING
LINE I (115 VAC )

1A--lI-i;R;i'E;';D~R"E"D',71 I

PIS a PI7
SEE NOTES"ZB 3

8 GND
9 GND
BlK

TWP

10 SPARE"'2
II GND II

BlK P17-2

';:;
"PI0-5

20V2

4 '5V

BlK

I .5V AI
2 15V4

4 +5V

II
GND 7
12 SPARE"'3
13 -15V2

GNDII
-5V2

+5V C2

5
6
7

BlK

SPARE"3

2 tl5V5
3 .20V3

P4-5

o~19

SPARE I
7 GNO BI
B GNDB

4 +5V
BLK

20VI

P I 5 r - - - - - - - - - - - , t E lPI5
i
Fs
H-745
-15VEIt"J P2-13 BlU
AC9
-15V
P2-11 BLK
GND EI Z r.:::..c~=,::--..

RED P10-12
'-'BLK P9- 5

T~P

RED

8
12

6-22

"WHTPI0-9

9 AC9 PI5-S "
RED

20-30
VAC

Revision 1
January 1974

GND

P14-3

9
10
II

,J:L
RED
PII-2
GRY
P3-2
. OORN P17-5

I t5V BI
2 .15V4

;:"'6

GNDIO

P10-12

P21 BlK

V-------

'DBRN PI-14

GN 0 3

SPARE"!
GND CI
GND

P
4 '5V

:"20 BlK

6
7
B

P13-3

BLK

RED
BlK
BlK
RED

.r.RED P8-7

+5V C2 5

SLOT C

AC-4
S Pl4-B(PI7-S)
._+-' WHT
'-"
,£'PIO
I AC5 PII-6
RED

3 +20VJ2

4 +5V
BLK

+5VBI
GND BI
GNO B2
t5VB2

RED
P12-2
GRY
PI- 2
. OORN P16-5

I t5V CI
2 tl5VI

v9~'--~~~-

.20VI
AC-3
P14-6
(PI7-7)
RED

P13- 2
P9- 2

SLOT B

4
5

20-30
VAC

RED

J31PB
t - - + - - t - - - - - - o r - - , = t ' j ' ACI P12-6 r.
20-30
RED
VAC
2
3

PI-I

9 X W H T PB-2
'-'
AC l02
10
10 t - - + - - t - - - I 4
LINE ClOC K
I I PIB-2 BLK
DC lO I
12J-P
:-;I",,8-::-3:'--+-+-.... 1
L-_ _ _ _ _
'--~=
ClR

20-30
VAC

AC lOI

2
3
4
5

1r:B:::.l:.;.K---,-P..:9..:.--=6'---l 5

6 AC 5

1--+----1--1 3

+5VAI
GND AI
GND A2
+5VA2

SLOT A

BI-'PI=B--'4"'R"'E"'Df--+-.... 1 r.RED P8 - I

+5V

7 AC2
B

rt
20-30
VAC

6 AC I

NOTES:

1.
2.

CABLE
. DEC "'91077SI
3.

All wIres are 14 AWG unless otherwise SPllGlfle1
If options requiring +20 V and -5 V are instaile,d
in box replace H745 and P15 in slot E with H7!)4
and P17, transfer AC wires from P15 pin 6 & afto
P17 pins 7 & 8. If additional +20, -5 is require~,
replace H745 and P14 in slot D with H754 and I
P16, transfer AC wires as above.
'
WARNING - To prevent damage to regulators I
remove/add jumpers according to table:
I

REGULATORS

slot D, slot E
H745
1--1745
H754

H745
H754
H754

JUMPERS

-15VJl

+20VJ2 -5VJ3
in

11-2307

)

CHAPTER 7
GENERAL MAINTENANCE

7.1 SCOPE
This chapter provides general maintenance information for the PDP-ll/40 System and includes: preventive
maintenance of mechanical assemblies, diagnostic programs, system power checks, and power supply maintenance.

)

Maintenance information related to the processor and memory components of the basic PDP-ll/40 System is
presented in the associated maintenance manuals. Maintenance of Unibus peripherals requires not only the
associated maintenance manual, but also an understanding of Unibus operation.
In addition to the maintenance information contained in the proces~or, memory, and peripherals manuals of the
PDP-ll/40, significant maintenance information is available in the diagnostic programs documentation. The
diagnostic programs are a major tool for detecting and isolating machine faults, and preventive maintenance should
include their regular use. Diagnostic programs are discussed in Paragraph 7.5.

)

7.2 OVERALL MAINTENANCE TECHNIQUES
Maintenance of the PDP-l1/40 System requires:
•
•
..

knowledge of proper hardware operation,
ability to detect and isolate an error condition, and
means to repair the error condition.

The above conditions are true for all but the preventive maintenance procedures for mechanical assemblies and for
the relatively simple power check-out procedures. This section outlines techniques for performing maintenance on
the PDP-ll/40. Note, however, that the essential starting point is to have knowledgeable and capable service
personnel.
7.2.1 Knowledge of Proper Hardware Operation
Training courses and machine documentation provide information on hardware operation and are available at the
programming, systems, and individual device levels.
The training courses available for the PDP-II /40 System include:
PDP-ll/40 Hardware Familiarization (10 days)
KDII-AMaintenance (3 days)
PDP-ll/40 Options Maintenance (5 days)
Interfacing the PDP-II (5 days)

)

Other courses are available on Paper Tape Software, Disk Operating System Software, and Resource Timesharing
System Software. Information on these and other PDP-II courses is available from either the Digital Account
Representative or from the Digital Education Centers.

7-1

Documentation pertinent to the PDP-II/40 System includes documents produced specifically for the PDP-1I/40,),
and common PDP-II documents on programming and Unibus interfacing. All of the relevant documents are listed in
Table 1-2.
A special effort has been expanded in production of documents relating to the PDP-ll/40 processor (KDll-A) and
processor options (KEll-E, KEll-F, KJll-A, KWll-L, KMll-A, and KT11-D). Innovations include: print set
formats, tables and notes on the prints, and wire list print notations. These are provided to facilitate initial learning
but, more importantly, to provide instant reminders of specific details during maintenance. Information describing
the print sets appears in the processor and options maintenance manuals.
7.2.2 Detection and Isolation of Error Conditions
Malfunctioning hardware is normally indicated by either software failure or peripheral malfunctions. Failures can
occur with customer's system software or during the periodic operation of various MAINDEC diagnostic programs.
If the failure occurs with system software, verification by MAINDEC diagnostic programs is suggested.
The PDP-ll/40 maintenance philosophy requires that service personnel be well trained on the PDP-ll/40 System
and experienced in computer maintenance. While MAINDEC diagnostic programs are provided to isolate faults to a
specific program operation or device, service personnel must fully understand hardware and software operation and
system documentation to use the diagnostics effectively. This understanding can only come through training and
experience.
Once the fault has been isolated to a device, the level of repair determines the difficulty and/or expense involved in
making the repair. In the power system for example, regulator units such as the H744 or H745 are replaced if their
output voltages are in error; the circuit board of the H742 unit is replaced if the AC LO or DC LO control signals are
in error. Replacement ofKDII-A Processor modules is suggested for situations requiring minimum downtime. While
module replacement is usually the most expeditious method of repair, experienced service personnel may find
integrated circuit (IC) replacement a practical alternative to the cost or transportation of modules.

)

7.2.3 Means of Repairing Error Conditions
The method of repairing an error condition is directly related to the levels of fault isolation mentioned in the
previous paragraph. If, for example, fault isolation and repair is to be at the IC level, then the parts identified in the
machine documentation must be available and suitable repair and rework techniques must be followed to avoid
equipment damage. If module or subassembly level of fault isolation and repair is to be used, these modules and
subassemblies must be available. Spare part kits are available for the PDP-ll/40 (SPll-KF for processor and
SPll-PD for the power supply) and the various Unibus devices. Repair is normally at the module or subassembly
level when downtime is critical or when a large number of machines are involved.

)

NOTE
Memory module replacement may require readjustment of the
strobe delay. Refer to MMll-S, MFll-L, and MFll-LP Core
Memory System, EK-MMllS-TM-003 for adjustment procedure.

Verification of repair at any level is made by running the appropriate MAINDEC diagnostic programs.
7.2.4 Digital Field Service
The present state-of-the-art in complex computer systems requires qualified service personnel. Installation and 90-day
warranty. service are provided by such personnel from Digital Field Service. These people are trained both in basic
PDP-11/40 components (processor, console, and memory) and in peripherals that may be placed on the Unibus.
Material support exists both at the IC level (directly equivalent parts) and at the module and subassembly level.

7-2

)

Digital Field Service support may be continued beyond the warranty period with a Digital Service Agreement. Total
equipment maintenance programs are available. Details of this service may be obtained from the Digital Account
Representative at the local Field Service Office.
7.3 MAINTENANCE EQUIPMENT REQUIRED
Maintenance procedures for the PDP-ll!40 require the standard equipment (or equivalent) listed in Table 7-1.
Especially important in analyzing operation of the processor, or processor options, is the KMII option consisting of
the W131 Module and the W130 or W133 module and associated overlays. Use of the KMll maintenance displays
and switches is covered in the processor and processor options maintenance manuals. The module extender board
(W900) is also an important diagnostic tool and is discussed in Paragraph 7.6.
7.4 PREVENTIVE MAINTENANCE

)

Preventive maintenance consists of specific tasks performed periodically; its major purpose is to prevent future
failures caused by minor damage or progressive deterioration due to aging. Any equipment defects or deterioration
detected during preventive maintenance checks should be documented in a maintenance log book. This maintenance
log, compiled over an extended period of time, can be very useful in anticipating possible component failures,
resulting in module replacement on a projected module or component reliability basis.
Preventive maintenance tasks consist of mechanical and electrical checks. All maintenance schedules should be
established according to conditions at the particular installation site such as environmental conditions, usage, etc.
Mechanical checks should be performed as often as required to allow the fans and air filters to function efficiently.
All other preventive maintenance tasks should be performed on a regular schedule determined by reliability
requirements. A recommended schedule is every 1000 operation hours or every three months, whichever occurs first.
7.4.1 Physical Checks
The following procedure contains the necessary steps required for mechanical checks and physical care of the
PDP-ll/40:

)

Clean the exterior and interior of the cabinet with a vacuum cleaner or a clean cloth moistened with
nonflammable, noncorrosive solvent.

Ensure that the fans are not obstructed in any way. Vacuum clean the air vents of the upper and lower
logic fan housings, and upper and lower regulator fan housings. Remove and wash the filters in the
cabinet fan, located in the top of the cabinet.

Inspect all wiring and cables for cuts, breaks, fraying, deterioration, kinks, strain, and mechanical
security. Repair or replace any defective wiring or cable covering.

Inspect the following for mechanical security: LED or lamp assemblies, jacks, connectors, switches,
power supply regulators, fans, capacitors, etc. Tighten or replace as required.

Inspect all module mounting panels; ensure that each module is securely seated in its connector and the
locking-releasing mechanism is functioning properly.

Inspect power supply capacitors for leaks, bulges, or discoloration and replace as reqUired.

Inspect module guides for wear, damage, and secure fastening.

7.4.2 Electrical Checks and Adjustments
Make the following checks when the system is first installed and whenever a new component is installed in the
system (such as an additional regulator, processor option module, interface module, etc.).

7-3

Table 7-1
Maintenance Equipment Required
Equipment or Tool

Manufacturer

Model, Type,
or Part No.

DEC Part No ..

453*

Oscilloscope

Tektronix

Volt/Ohmmeter (VOM)

Triplett

Unwrapping Tool

Gardner-Denver
(Cat. H812A)

505244-475

29-18387

Hand Wrap Tool

Gardner-Denver
(Cat. H811A)

A-20557-29

29-18301

Diagonal Cutters

Utica

47-4

29-13460

Diagonal Cutters

Utica

466-4 (modified)

29-19551

Miniature Needle Nose Pliers

Utica

23-4-1/2

29-13462

Wire Strippers

Millers

lOIS

29-13467

Solder Extractor

Solder Pullit

Standard

29-13467

Soldering Iron
(30 watts)

Paragon

615

29-13452
(IC type head)

Soldering Iron Tip

Paragon

605

29-19333

16-pin IC Clip

AP Inc.

AP923700

29-10246

24-pin IC Clip

AP Inc.

AP923714

29-19556

KMll Option Maintenance Console Modules

DEC

KMll-A

W131 and W130 orW133**

Maintenance Card
Overlay (KDll-A)

DEC

559081-0-12

Maintenance Card Overlay (KEII-E, F, KT11-D)

DEC

5509081-0-13

Module Extender Board

DEC

W900

Regulator Extender Cable

DEC

70-08850-0-1

29-13510

)

*Tektronix Type 453 Oscilloscope is adequate for most test procedures;Type 454 (or equivalent) may be required for some
measurements.
**W133 is a dual version of W130. It provides the drivers for two W131 maintenance cards. The W130 may still be used, but
two units would be required for simultaneous monitoring of the basic processor and options. Two W131s are required ·for
simultaneous monitoring in any case.

7-4

)

7.4.2.1 Processor Clock Adjustment Check - Perform the processor clock adjustment according to the clock
adjustment procedure on the KDII-A timing module (M7234) print K4-?
7.4.2.2 Voltage Regulator Checks - Perform the power system checks listed in Table 7-2. Use a YOM to check the
output voltages under normal load conditions at logic backplanes. Use an oscilloscope to measure the peak-to-peak
ripple content of all dc outputs. Each voltage regulator has an adjustment potentiometer located just below the
output indicator lamp. If the regulator output is not within the specified tolerance, adjust as required to obtain an
acceptable output (use a nonconducting adjustment tool). If a voltage regulator cannot be adjusted to meet
specifications, remove and replace the regulator.
Table 7-2
DC Output Voltages
Regulator

Slots

Voltage and Tolerance

Output Current (max)

Ripple

H744

A,B,C

+5 Vdc ± 5%

25A

200mV

H745

D,E

·-15 Vdc ± 5%

lOA

450mV

H754

D,E

+20Vdc ± 5%
-5 Vdc ± 5%

8A
lA

------

+15 Vdc ± 10%
+8 Vdc ± 15%
20-30 Vac (5 outputs)

3A) (I)
lA
300W ea output, 1 kW
max. total output

H742

---

------

Note 1: Total not to exceed 3A continuously.
7.4.2.3 861 Power Controller - Operate the REMOTE/OFF/LOCAL switch on the 861 Power Controller to verify
that power is turned on in the LOCAL position and disconnected in the OFF position. Return the switch to the
REMOTE position after performing this test. Paragraph 6.4 references a detailed description of the 861 Power
Controller.
J

7.4.2.4 AC Power Connector Receptacles - Test the output voltage at each plug and ensure that 115 or 230 Vac
power is available.
7.4.3 ASR 33 Teletype
7.4.3.1 Preventive Maintenance Checks - Check the following ASR 33 items dliring system preventive
maintenance:

)

Check distributor plates for deposits.

Check platen and typewheel for deposits.

Check wires around distributor area for secure mechanical and electrical connections.

Check the print hammer and replace if worn.

Rotate the mainshift manually and check that movement is free. If movement is restricted, check clutch
assemblies.

Check typewheel pinion racks, and gears for dirt.
7-5

Revision 1
January 1974

7.4.3.2 Lubrication - Use a 50-50 mixture of 20 weight, non-detergent oil and STP oil additive for viscosity
improvement to perfonn the follOwing lubrication, except where otherwise noted:
a.

Oil all clutch assemblies.

Oil all felts until saturated.

lightly oil all pivot points.

Oil drive motor at both lubrication points provided.

Oil print carriage bearings.

Oil main shaft bearings.

Oil bearing on function shaft.

Oil the eye ends of all springs.

Oil the typewheel pinion and gear.

Oil repeat mechanism in keyboard assembly.

Clean the dashpot assembly and lubricate it with graphite dust.

)

NOTE
Do not put oil in the dashpot.

)

Grease the teeth on spacing ratchet.

7.4.4 LA30 DECwriter Preventive Maintenance
A maintenance manual is provided with the LA30 DECwriter. Refer to Chapter 5 of that manual for detailed
preventive maintenance procedures.
7.4.S PCOS High-Speed Paper-Tape Reader/Punch Option

)

The PCOs High-Speed Paper-Tape Reader/Punch includes a Roytron 500 Series Reader/Punch mechanism. Complete
lubrication and preventive maintenance instructions for this mechanism are contained in the Preventive Maintenance
Section of the Roytron Maintenance Manual, which is supplied with the PCOS. In addition to the preventive
maintenance procedures listed in that manual, perfonn the following mechanical and electrical checks as part of the
system preventive maintenance procedure.
7.4.S.1 Mechanical Checks - Inspect the PCOs as follows:
1.

Visually inspect the general condition of the tape reader.

Clean the PCOs, inside and out, using a vacuum cleaner or a clean cloth moistened with a nonflammable
solvent.
.

Lubricate the chassis slide mechanism with a light machine oil. Wipe off excess oil.

)
Revision 1
January 1974

7·6

Inspect all wiring and replace any defective wiring or defective cables.

Check that the READER FEED switch, READER ON/OFF LINE switch light condenser,
photo transistor assembly, depressor arm, hold· down bracket, all connectors and circuit modules, tape
feed motor, front cover, and resistor assembly are mechanically secure.

7.4.5.2 Electrical Checks - Perform power supply output tests listed in the following chart:

Output

Pin Number

+5V
-15V
-18V
-36V

)

AIA2
AIB2
B8V2
A8V2

Tolerance
±0.25V
±1.0V
±2.0V
+4.0V

Ripple (peak·to·peak V)
O.IV
O.IV
1.0V
1.0V

Use a YOM to measure output voltage and an oscilloscope to check ripple voltage. The +5 and -15V outputs are
adjustable; the -18 and - 36V outputs are not adjustable.

7.5 DIAGNOSTIC PROGRAMS
7.S.1 General Description
The following groups of diagnostic programs are applicable to the basic PDP·ll/40 System and options:

)

PDP· 11/40 System Diagnostics

KDII-A Processor Diagnostics

Core Memory Diagnostics

KEII-E Extended Instruction Set Diagnostics

KE 11-F Floating Instruction Set Diagnostics

KT11·D Memory Management Diagnostics

KJ 11· A Stack Limit Register Diagnostic

KWll·L Line Frequency Clock Diagnostics

Diagnostic programs for peripherals and I/O devices in the system are listed and described in their associated
maintenance manuals. Detailed descriptions and specific operating procedures for each diagnostic program are
provided in related diagnostic program description (MAINDEC) documentation.
Generally, all diagnostic programs are loaded into the lowest 4K words of physical memory. All diagnostic programs
start at address 200 8 and run in kernel mode.

7-7

Revision 1
January 1974

Any trap or interrupt vectors not used by the testinprogres~ are set up as "trap catchers"; the new Program Counter
(PC), stored in the first word of the vector, points to the second word of the vector, which contains a O. When the 0
is fetched as an instruction, the processor interprets it as a HALT instruction. The instruction being executed when
the 1rap occurred can be identified as follows:
I.

Examine R6 (777706).

Set the number found in R6 in the Switch register and do a LOAD ADRS operation.

Do an EXAM operation to determine the contents of the top word in the stack. This is the PC at the
time the false trap/interrupt occurred.

Generally, the ·PC is pointing at the instruction following the instruction that caused the trap or
interrupt. Use this value and the program listing to determine the instruction being executed when the
trap or interrupt occurred.

-\
)

The available diagnostic programs are listed in Table 7-3.

Table 7-3
PDP-I 1/40 Diagnostic Programs
Title

Code

System Exercisers
Communications Test Program (CTP)
General Test Program (GTP)
System Sizer
ProcessofTest ·17 System Exerciser

MAINDEC-II;DZQCAMAINDEC-II-DZQGA:
MAINDEC-II-DZSSAMAINDEC-II-DZQKB-

Processor Tests
Processor Test 14 Traps
- PDP-11 /40,11/45 Instruction Exerciser
Processor Power Fail Test
PDP-I 1/40 Basic CP Test SXT
PDP-II /40 Basic CP Test SOB
PDP~II/40 BasicCP Test XOR
PDP-I 1/40 Basic CP Test MARK
PDP-I 1/40 Basic CPTest RTT

MAINDEC-II-DBKDMMAlNDEC-U-DCQKCMAINDEC-II-DZKAQ-AMAINDEC-II-DCKBAMAINDEC-II-DCKBBMAINDEC-II-DCKBCMAINDEC-II-DCKBDMAINDEC-II-DCKBE-

Memory Tests
- 0-124 Memory Exerciser
CPU Parity Test'"

MAINDEC-II-DZQMBMAINDEC-II-DBKBR-

KEII-E(EIS) Option Tests
PDP-II!40 Basic CP Test ASH
PDP-I 1/40 Basic CP Test ASHC
PDP-I 1/40 Basic CP TestMUL
PDP~ 11/40 Basic CP Test DIV
MUL,DIV Random Exerciser

MAINDEC-II-DCKBIMAINDEC-II-DCKBJMAINDEC-II-DCKBKMAINDEC-II-DCKBLMAINDEC-II-DCQKA-

*U.se.only with parity memory systems.
Revision J
January 1974

7-8

)

Table 7-3 (Cont)
PDP-l1/40Diagnostic Programs
Code

Title

)

KEI1-F (FIS) Option Tests
KEIIF Instruction Tests
KE 11 F Exerciser
KEIIF Systems Exerciser (GTP) Overlay

MAINDEC-II-DBKEAMAINDEC-II-DBKEBMAINDEC-II-DBKEO-

KTlI-D Memory Management Option Tests
KTllD Basic Logic Test
KTll D Access Keys Test
MTPI/MFPI with Memory Management Test
KTlID Processor States Test
Memory Management Abort Tests
KTll D Exerciser

MAINDEC-II-DBKTAMAINDEC-II-DBKTBMAINDEC-II-DBKTCMAINDEC-II-DBKTDMAINDEC-II-DBKTFMAINDEC-II-DBKTG-

UII-A Stack Limit Register Option Test
PDP-l 1/40 Basic CP Test Stack Limit
KWII-L Line Frequency Clock Test

MAINDEC-II-DCKBFMAINDEC-II-DZKWA-

LA30 Serial - 300 baud

MAINDEC-II-DZLAB-

KLll/DLllA Teletype Tests
Is and Os Test Tape
Special Binary Count Pattern Tape
Maintenance Loader

MAINDEC-II-DZKLAMAINDEC-00-D2G2-PT
MAINDEC-OO-D2G4-PT
MAINDEC-II-D9EA-

7.5.2 Diagnostic Program Utilization
Diagnostic programs are designed to facilitate maintenance of the PDP-II /40 System and its options. Their specific
purpose is to aid in the defmition and isolation of error conditions; this is accomplished in greater detail than is
possible with system operational software.

)

There is a definite order in which diagnostics should be run. When problems occur or are suspected, a system type
exerciser (GTP or CTP) should be run to isolate the failure to a specific Unibus device. Once the fault is isolated to a
specific Unibus device, the programs designed to checkout that device should be run. This naturally assumes that
programs can be loaded and run.
Relative to the PDP-l1!40 processor, an effort has been made to correlate a specific diagnostic program error with a
particular module failure. Table 7-4 correlates the processor and processor option diagnostic programs to the
modules most likely to be at fault in the event an error is detected. The diagnostics are listed in the order they
should be run (top to bottom), and the modules are listed in the order of failure probability (left to right). The
percentage of failure probability is also noted. Be advised that Table 7-4 presents the initial effort to correlate
diagnostic programs to specific module failures and should not be considered an absolute error indicator.

7-9

Revision 1
January 1974

§~

Table 7-4
PDP-ll/40 Processor Preliminary
Diagnostic Program Error Analysis

o·

...... ::1
\0
-.J

.j:>.

Diagnostics*

-;-J

......

Module Replacement
3rd
Prob. (%)

lst

Prob. (%)

2nd

Prob. (%)

Test 1 Branch

M7232

M7233

M7231

Test 2 Con Branch

M7235

M7233

M7231

test 3 Unary

M7233

M7235

Test 4 Unary & Binary

M7.233

M7232

Test 5 Rotate/Shift

M7232

M7233

Test 6 Compare

M7232

M7233

Test 7 Compare NOT

M7232

M7233

Test 8 Move

M7232

M7233

Test 9 BIS, BIC, and BIT

M7232

M7233

Test 10 ADD

M7232

M7233

Test 11 Subtract

M7232

M7233

Test 12 JMP

M7232

M7233

Test 13 JSR, RTS, RTI

M7232

M7235

M7233

SXT Instruction

M7232

M7233

SOB Instruction

M7232

M7233

XOR Instruction

M7232

M7233

8
----

"--"

"'-/

4th

Prob. (%)

5th

Prob. (%)

M7235

M7234

10 .'

'-/'

L _ _ __

'-"

'~---'

'--"

Table 7-4 (Cont)
PDP-l1/40 Processor Preliminary
Diagnostic Program Error Analysis

Diagnostics*

-;-J

1st

Prob. (%)

2nd

Prob. (%)

MARK Instruction

M7232

M7233

RTT Instruction

M7232

M7233

Test 14 Traps Test

M7232

M7234

K111-A Stack Limit
Option Test

M7237

M7231

KEIIE Option Tests**

M7238

M7232

KEllF Option Tests**

M7238

Test 18 Power Fail

M7235

Test 15 11 Family
Instruction Test

M7232

Module Renlacement
Prob. (%)
3rd

M7233

M7239

M7231

M7234

M7233

4th

Prob. (%)

M7233

5th

*See Table 7-3 for diagnostic program complete title and code. Tests 1-13 are listed primarily for reference purposes. These diagnostics are not part of the standard set
(LIBKIT-ll/40-BASE-A-K, August 22, 1973), but may be purchased on special order.
**This test consists of several separate diagnostics. See Table 7-3 for complete listing.

;;';-:;:tl

::l

.... -.
-:§
t:

1.0
-....J
~

<
tn"

Prob. (%)

)

7.6 USE OF MODULE EXTENDERS
The W900 Module Extender is a double-height, multi-layer etch board that provides one-to-one connections between
module connectors and corresponding processor backplane connector slots. Thus, three W900 Module Extenders can
be used to extend a PDP-l1/40 hex~size module from the processor backplane to provide access to ICs and discrete
components for test purposes underactive operating conditions.
CAUTION
Do not attempt to extend more than one module at a time
while performing tests. Note that the processor clock may
have to be adjusted to allow operation with the modules
extended. See processor timing module (M7234) print K4-2
for clock adjustment procedure.

7.7 PDP-l 1/40 POWER SYSTEM MAINTENANCE
WARNING
Dangerous voltages (115/230 Vac) are present in the power
system. AU electrical safety precautions must be observed.

)

For, the most part, maintenance of the power system in the field consists of replacing defective modules, such as
voltage regulators. Paragraph 6,4 provides the theory operation of the power system. When a failure occurs, the
recommended troubleshootillga.pproach is to visually inspect the power system and then, if necessary, check
voltages at specific points in the power system to isolate the fault to a particular module.
7.7.1 Visuallnspection
If a power system fault is suspected, visually inspect the system components for obvious fault indications. For
example, each of the voltage regulator modules is provided with an output indicator lamp that is on when the output
voltage is within range. Ifa single indicator lamp within the group is off, the fault is probably within that voltage
regulator module. In the case of the H744 +5V Regulator, this can be verified by swapping H744 regulators.
CAUTION
Because there are two +5V and two -15V regulators in the
PDP-ll/40 System, a common troubleshooting technique
would be to swap an operating regulator with a faulty
regulator.If this is done, first check regulator input voltages to
prevent damage to the second regulator in the event the fault
lies in ,the H742 Power Supply.

)

If none of the voltage regulator output indicator lamps in the group are on, the fault is probably in the associated
H742 Power Supply or 861 Power Controller. Visually inspect the power indicator lamps and circuit breakers
provided with these components to determine whether the fault can be isolated to either the H742 or the 861.
7.7.2 Power System Checks
Table 7-5 provides a procedure that can be used as a guide to locating defective modules.

)
/

Revision 1
January 1974

7·12

..~/'

\--.-J

'---.-/

,---",'

Table 7-5
Power System Troubleshooting Guide
Step

Test
Verify that proper ac voltage input
to H742 Power Supply is present.

Procedure
l15V system - measure between
pin I, or 2 and pin 3 or 4 of TBI on
H742 Power Supply,
230V System - measure between
pin 1 and 4 of TB1.

Verify that H742 Power Supply is
providing the proper ac outputs.

20-30 Vac should be present on
the following pins:
II - pins 1,2
12 - pins 1,2
12 . .:. . pins 8, 10
12"':' pins 9, 12
J3 - pins 1,2
J3 - pins 3, 4
J3 - pins 5,6
J3 - pins 7,8

-;-l
......
w

Results
Correct - proceed to'step 2,
Incorrect - indicates failure may be
in 861 Power Controller or input
line. Refer to Chapter 5 of the
861-A, B, C Power Controller Manual and troubleshoot the 861 Power
Controller.
Correct - proceed to step 3.
Incorrect - indicate failure of
H742 transformer. If all voltages
are correct except one, problem
could be either transformer secondary or a wiring malfunction.

15-24 Vacshould be present between pins 3 and 4 of J 1.
3

i;;':;tI

::l

+5V Regulator - check for 20-30
Vac at pins 6 and 7 of J1.
-15V Regulator - check for 20-30
Vac at pins 6 and 8 of J 1. Check
for +15V at pins 4,5 of J1.

s· ~.
-< o·
..... ::l
\0

Verify that the proper input voltage
is present at the regulator.

+20, - 5V Regulator ~ check for
20-30 Vac at pins 7 and 8 of J1.

Correct - proceed to step 4.
Incorrect - indicates failure is
probably in the wiring between the
H742 and the regulator. If the
+15V for the -15V regulator is not
present, the trouble may be in the
H742 Power Control Board .

..... :;:0

Table 7-5 (Cont)
Power System Troubleshooting Guide

2 ~.
'"-< g
'"

('I)

(O~
-..]

Step

Test

Verify that proper output voltage is
being produced by the regulator.

Procedure

Results

+5V Regulator - measure between
pins 2, 5 (+5) and 3, 4 (GND) of
J1. Output must be between +5.05
and +4.95V.
-15V Regulator - measure between pin I (-15V) and pins 2, 3
(GND) of J1. Output must be
between -15.15 and -14.85V.
Backplane voltage measurement
with proper voltmeter is occasionally necessary.

Correct - check remammg regulators. If all regulators are within
tolerance, the power system is not
malfunctioning and the problem
exists elsewhere.
Incorrect - If the +5V regulator is
not functioning, check fuse P I in
the regulator. If the -15V regulator
is not functioning, check fuse PI in
the regulator. If this does not correct the problem, replace the respective regulator.

+20, - 5V Regulator a. Measure between pins 5 (+20V)
and 2 (GND). Output must be
between + 19 and +21 V.

-;.J

b. Measure between pins 3 (-5V)
and 2 (GND). Output must be
between -4.75 and -5.25V.

'-./

APPENDIX A
SUMMARY OF EQUIPMENT SPECIFICATIONS
This table gives mechanical, environmental, and programming information for PDP-II optional equipment. The
equipment is arranged in alphanumeric order by Model Number.
NOTES

)

Mounting Codes
CAB = Cabinet mounted. If a cabinet is included with the option, it is indicated by an X in the "Cab
Incl" column.
FS

= Free standing unit. Height X Width X Depth dimensions are shown in inches.

TT = Table top unit.
PAN = Panel mounted. Front panel height is shown in inches. An included cabinet is indicated when
applicable.

)

SU = System Unit. SU mounting assembly is included with the option.
SPC

= Small Peripheral Controller. Option is a module that mounts in a quad moduJe, SPC slot.

MOD = Module. Height is single, double, or quad.
( ) = Option mounts in the same space as the equipment shown within the parentheses.

)

Some options include 2 separate physical parts and are indicated by use of a plus (+) sign.

Cabinet and peripheral equipment (such as magnetic tape) are included in the specifications.

Relative humidity specifications mean without condensation.

EqUipment that Can supply current is indicated by parentheses ( ) around the number of amps in the
POWER section. MEMORY POWER: MFll- and MMll- require the same amount of power. In this
table, MFll- power figures show the power required when the memory is active, while MMll- figures
reflect that required by an inactive unit.

Non-Processor Request devices are indicated by an X in the "NPR" column.

7008855 in 11/45-11/50 CPU; 7008909 in H960-D and 11/40.

7009174. If first MFll-L in 11/40, use 7009103.

A-I

Revision 1
January 1974

7009560. If first MFll-L in 11/40, use 7009565.

H960-C, D only (not CPU Cabinet): one 7009568 per backplane (9 pin conversion) and one 7009569
for two backplanes (regulator harness).

CONVERSION FACTORS

(inches)
(lbs)
(Watts)
[CC) x.2.] + 32
5

X 2.54
X 0.454
X 3.41

:::
:;
;:;::
=

(cm)
(kg)
(Btu/hr)
CF)

)

)
Revision I
January 1974

A-2

Model'
Number

AAII-D
ADOI-D
AFCII
BAII·ES
BA614
BBII
BBII-A

)

BCllA
. BM792-Y
CBll
CDII-A
CDII-E
CMII-F
CRU
DAII-B
DAII-F
D811
DCII-A
DDII
DECkit OI:A

')
DECkit II-F

DECkit ll-H

DECkit II-K
DECkit II-M

DFOI-A
DFII
DHII
Dl1 I
DLlI-A
DLlI(others)
DMII-BB
DNII
DPII
DQII
DRII-B
DRII-C
DT03-F
.OX I I
GT40

Description

D/ A Subsystem
A/D Subsystem
AID Subsystem
Mounting Box
D/ A Converter
Blank Mntg Panel
Blank Mounting
Pariel (non-slotted
blocks)
UNIBUS Cable
Bootstrap Loader
Telephone Switching
Interface
Card Reader
Card Reader
Card Reader
Card Reader
UNIBUS Link
UNIBUS Window
Bus Repeater
Asynch Line Inter
Periph Mntg Panel
Remote Analog Data
Concentrator: 8
Channels,. Serial
I/O Interface: 3
Words In/4 Words
Out
I/O Interface: 4
Words In/4 Words
Out
I/O Interface:
8 Words In
I/O Interface:
Instrumentation
Interface
Acoustic Coupler
Line Sig Cond
Asynch Line MX
Asynch Line MX
Terminal Control
Asynch Line Inter
Modem Ctr. MUX
Auto Calling Unit
Synch Line Inter
DMA'Sync Line
Interface
DMA Interface
General Interface
UNIBUS Switch
IBM Chan. Interface
Graphics Terminal

Mounting
Code

SU
PAN
CAB
PAN
(AAII-D)
SU
SU

Size
HXWXD
(inches)

MECHANICAL
Weight
Cab
(Ibs)
Incl

Power Harness
Early
New

Note 6

7009562

514
10l-2

ENVIRONMENTAL Oper
Rei
Temp
Humid
(0C)
(%)

POWER
Cur needed/(supplied)
+5 V
115 Vac / Other
(amps)

10-50
0-55
10-55

20-95
10-95
10-95

0.5
0.5
IS

Power
Dis
(W)
60
60
1700

100

"PROGRAMMING
Int
htReg
Vector
Address

776756
776770
772 570

140,144
130
134

UNIBUS
NPR

Bus
Loads

Model
Number

4,5
4-7
4

I
I
I

AAll-D
ADOI-D
AFCII
BAII-ES
BA614
BBII
BBII-A

I
1,2

BR
Level

p.3

SPC
Cab
SU+TT
SU+TT
SPC + TT
SPC + TT
SU
SU
SU
SU
SU
PAN

X
14 X 24X 18
38 X 24 X 38
IIX 19 X 14
II X 19 X 14

300
85
200
60
60

5l4X19X13

Note 6
Note 6

7{)09562
7009562

Note 6
7009099
Note 6
Note 6
7009099

7009562
7009563
7009562
7009562
7009563

10-50

10-90

10-50
10-50
10-50
10-50

10-90
10-90
10-90
10-90

5.6

650

764 000

float

4-7

4
6
4
4

450
700
400
400

772 460
772 460
777
160
,
777160
772410

230
230
230
230
124
float

4
4
6
6
5
7

774000

float

1O~95

5-50
10-50

20-90

0-50

10-95

2.5
2.5
1.5
1.5
4
5
3.2

see Product Bull.
1.5 (al 115 Vac
0.75 (al 230 Vac

175

BCIIA
BM792-Y
CBII

I
I
I
I
I
I
I+I
I

CDII-A
CDII-E
CMII-F
CRll
DAII-B
DAII-F
DBII
DCII-A
DDII-A
DECkit Ol-A

X
X

i
1

Note 6

0-70

10-95

1.84

User

DECkit II-F

Note 6

0-70

10-95

3.91

User

5-6

DECkit II-H

DECkit I1-K

DECkit II-M

,
I

Note 6

0-70

10-95

1.97

U~er

Note 6

0-70

10-95

1.75

User

TT
DF slot
2SU
SU
SPC
SPC
(DHlI)
SU
SU
SU
SU
SPC
PAN
CAB
TT

6X7X.12

0-60
7009466
7009099

7009561
7009563

5-45

10-95

Note 6
Note 6
7009099

7009562
7009562
7009563

0-40
0-40
10-50

20-90
20-90
10-90

8.4
5
1.8
1.8
2.8
1.4
2.5
5.7

Note 6

7009562

10-50
10-50

20-90
20-90

3.3
1.5

514
X
18X20X24

180
150

10-55
15-35

10-90
20-80

0.3
see Product Bull.
0.24 A (01 -15 V
see Product Bull.
0.15 A@-15V
0_15 A@-15V

I
I

float
float
7''/7 560
776500
775000
775200

O.lOA@±15V
O.lOA@±15V
0.04 A (a}+15 V
0.07 A@-15V

2
2.5
15

User

4OO
7V
fl at
!
772410
767770
!

300
1500

776200
flt at

float
float
060,064
float
float
float
float
float

5
5
4
4

124
float
user
float
float

5
5
7
4-7

4
5
5

2
I
I
I
I
I
1

DFOI-A
DFII
DHII

DIll

DLII-A
DLII (others)
DMII-BB
DNl1
DPII
DQII

I
1
I+I
I
I

DRll-B
DRII-C
DT03-F
DXII-B
GT40

)
A-3

Model
Number

)

Description

··Mounting
Code

H312·A
H720·E
H722
H742
H744
H745
H746

Null Modem
Power Supply
Transformer
Power Supply
+5 V Regulator
-IS V Regulator
MOS Regulator

(BAll)
(pCll·A)
(H960·D)
(H742)
(H742)
(H742)

H754

+20, -5 V Regulator

(H742)

H933·C

Mounting Panel
(H803 blocks)
Mounting Panel
(H808 blocks)
Cabinet
Cab (I drawer)
Cab (2 drawers)
Cab wlo side pan
Ext. Arith. Elem.
Comm Arith Unit
Line Clock
Programmable Clock
DECwriter
LA30 Control
Printer (80 col)
Printer (132 col)
Ptr (heavy duty)
Lab Periph System
Line Printer
Teletype
Electrostatic Ptr
Adrs Select Module
Bus Transmitter
Bus Receiver
Bus Transceiver
Diode ROM
Word Count
Bus Control
Bus Jumper
Bus Terminator
Bus ,Input Interface
Bus Output Interface
DVM Data Input
Interface
Instrument Remote
Control Interface
Unibus Interface
Foundation
16·Bit Relay Output
Interface

H933·D
H960·C
H960·D
H960·E
H961·A
KEll·A
KGII·A
KWll·L
KWII·P
LA30
LCll·A
LPII·F
LPll·J
LPII·R
LPSll
LSll
LT33
LVII
MI05
M783
M784
M785
M794
M795
M796
M920
M930
MI501
MI502
MI621
MI623
M1710
MI801

Size
(HX W X D)
(inches)

MECHANICAL
Weight
Cab
(Ibs)
Incl

Power Harness
Early
New

ENVIRONMENTAL
ReI
Oper
Humid
Temp
(0C)
(%)

0-50

20-95

POWER
cur, needed/(supplied)
+5 V
115 Vac I Other
(amps)

(22)

6
8

Power
Dis
(W)

(lOA) @-15 V
1.5 A @ 230 Vac
(1 A)@+15 V

PROGRAMMING
Int
lst~eg
Vector
Address

BR
Level

UNIBUS
NPR

Bus
Loads

H312·A
H720
H722
H742
H744
H745
H746

700
I
i

(25)

Model
Number

(10A)@-15V
(1.6 A)@ 23.2 V
(3.3 A)@ 19.7 V
(1.6A)@-5V
(8 A)@+20V
(I A)@-5 V

H754
H933'(

H933·D

FS
FS
FS
FS
SU
SPC
MOD
SPC
FS
SPC
SPC + FS
SPC + FS
SPC + FS

PAN

72 X 21
72 X 21
72 X 21
72 X 21

X 30
X 30
X 30
X 30

X
X
X
X

120
300
470
120

7008754
7008754

7009566
7009566

(75)
8
(150) 16

Note 6

7009562

4
1.5
0.8
I

single ht
31 X 21 X 24

110

15-35

20-80

46 X 24 X 22
46 X 48 X 25
48 X 49 X 36
5¥1
12 X 28 X 20
34 X 22 X 19
38 X 19 X 18
single ht
single ht
single ht
single ht

200
575
800
80
ISS
60
160

10-43
10-43
10-43
5-43
5-38
15-35
10-43

15-80
15-80
15-80
20-80
5-90
20-80
20-80

1.5
1.5
1.5
1.5

SPC + TT
FS
SPC + FS
MOD
MOD
MOD
MOD
SPC
MOD
MOD
MOD
MOD
MOD
MOD
MOD

double ht
single ht
double ht
quad ht

0-70
0-70
0-70

10-95
10-95
10-95

1.25
0.3
0.75
0.78

MOD

quad ht

0-70

10-95

1.6

MOD &
SPC
MOD

quad ht

0-70

10-95.

0.79

0-70

10-95

1.46

quad ht

1.5
1.5
0.34
0.2
0.2
0.3.
0.23

(20 A)@-15 V
(40A)@-15V

900
1800

I
I

777~00
100
104

6
6

I
I
I
I

14
777r
777514
777 1514
floatI
777 1514

060,064
200
200
200
float
200

4
4
4
4
4-6
4

I
I
I
I
2
I

777 pl4

200

770;700
777546
3

300

2
4
17
3
3
2
5

250
500
2000
300
300
200
600

772

777 60

opt

I,
I

;

773:000

i
.,.

MI623

H960'(
H960·D
H960·E
H961·A
KEIl·A
KGll·A
KWII·L
KWII·P
LA30
LCII·A
LPII·F
LPll·J
LPII·R
LPSII·S
LSll
LT33
LVll
M105
.M783
M784
M785
M792
M795
M796
M920
M930
MI501
MI502
MI621

M1710

opt

MJ801

)
A·5

(
Model
Number

(

Mounting
Code

M7820
M7821
MEll·L
M.Fll·L
MFll·LP
MFll·U

Interrupt Control
Interrupt Control
Core Memory (8K)
Core Memory (8K)
Parity Memory (8K)
Core Memory (16K)

MOD
MOD
PAN
2SU
2SU
2SU

MFll·UP

Parity Memory (16K)

2SU

MMll·L
MMll·LP
MMll·U

Core Memory (8K)
Par·ity Memory (8K)

MMll·UP
MRl1·DB
MSll
PCII
PDM70
PRII
RCll·A
RFII·A
RK05
RKII·D
RP03
RPII·C
RSII
RS64
RTOI
RT02

(

Description

TAll
TCll·G
TMII
TUlO
TU56
UDCll
VROI
VRI4
VTOI
VT05

Size
(H X W X D)
(inches)

MECHANICAL
Weight
Cab
(Ibs)
Incl

Power Harness
Early
New

single ht
single ht
5\4

ENVIRONMENTAL
ReI
Oper
Humid
Temp
(0C)
(%)

POWER
Cur needed/(supplied)
+5 V
115 Vac / Other
(amps)

Note 7
Note 7
Note 9

Note 8
Note 8
7009535

0-50
0-50
0-50
0-50

10-90
10-90
10-90
0-90

Note 9

7009535

0-50

0-90

(MFll·L)
(MFll·LP)

0-50
0-50

10-90
10-90

1.7
1.7
4.5

Parity MemQry (16K)

(MFll·UP)

0-50

0-90

4.5

Bootstrap
Semiconductor Mem
Paper Tape
Programmable Data
Mover
Paper Tape (rdr)
Disk & Control
Disk & Control
Disk Drive
Disk & Control
Disk Drive
Disk & Control
Disk Drive
Disk
Numeric Data Entry
Terminal
Alphanumeric Data
Entry Terminal
Cassette
DECtape & Control
Magtape & Control
Magtape Transport
DEC tape Transport
I/O Subsystem
Display
Display
Display
Alphanum Terminal

2SPC
(11/45)
SPC + PAN
IT

50
55

0-50
13-38
0-40

10-80
20-95
10...,95

13-38
17-50
17-33
15-43
15-43
15-33
15-33
17-33
17-50
0-40

20-95
20-80
20-55
20-80
20-80
10-80
10-80
20-55
20-80
10-90

0-40

10-90

1Ol?
5\4 X 19 X 23

10l?
1Ol?
16+ 16
1Ol?
1Ol?
40X30X24
16
1Ol?
6.5 X 12.5 X 15

50
115
500
110
250
415
740
100
65
12

6.3 X 14.4 X 16

X
X
X

5\4
1Ol? + 1Ol?
26 + 10l?
26
1Ol?
1Ol?
1Ol?
12X12X23
12 X 19 X 30

X
X
X

250
500
450
80
30
75
50
55

7008992

7009562

10-40
15-27
15-27
15-27
15-27
5-50
10-50
10-50
0-50
10-43

20-80
40-60
40-60
40-60
40-60
10-90
10-90
10-90
10-80
8-90

1.5

125
125
125
120

1
1
2
1

M7820
M7821
MEll·L
MFll·L
MFll·LP
MFll·U

120

MFll.UP

125
125

1
1

MMll·L
MMll·LP
MMll·U

7.5

3
2.2
6.5
2
2
7
2
2.2

6 A@230Vac
6 A@230Vac

0.25 @ 115 Vac
0.12,@ 220 Vac
110 Vac
220 Vac
1.5

BR
Level

I
I

MMll·UP
I

115 Vac
230 Vac
1.5

UNIBUS
NPR

MOC1el
Number

0.6

SPC + PAN
PAN
PAN + PAN
PAN
SU+PAN
FS
CAB + FS
PAN
PAN
TT

SPC + PAN
PAN + PAN
PAN + PAN
PAN
PAN
CAB
PAN
PAN
TT
TT

6A@-15V
6A@-15V
3.5 A@20V
0.5A@-5V
3.4 A@20V
0.5 A@-5V
0.5 A@-15V
0.5 A@-15V
0.5 A@20V
0.5A@-5V
0.5 A@20V
0.5 A@-5V

3.4
4.9
4.5

PROGRAMMING
Int
1st Reg
Vector
Addryss

Bus
Loads

Power
Dis
(W)

1
9
9
9
3
15
I
4
2.2
2

350
250
250
350
250
750
160
200
1300
2100
200
250
30
50
50
120
870
1000
1000
350
1700
120
400
250
130

772 100
777 5:50

2
1
1

MRll·DB
MSII
PCII
PDM70

1
1

PRl1
RCII·A
RF11·A
RK05
RKlI·D
RP03
RPII-C
RSl1
RS64
RTOI

114
070,074

070
210
204

4
5
5

X
X

7774PO

220

7767110
!

254

777 5~0
777 4~0
777460

I
i
I

RT02

777 5~0
77730
772 520
I

260
214
224

6
6
5

234

4,6

I
I
I

X
X

i
I

771

7~4

A·7

TAlI
TCll·G
TMll
TUIO
TU56
UDCll
VROI
VRI4
VTOI
VT05

PDP-ll/40, -11/35 SYSTEM MANUAL
EK-ll040-TM-002

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FIRST CLASS
PERMIT NO. 33
MAYNARD, MASS.
BUSINESS REPLY MAIL
NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES
Postage will be paid by:

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Modify Date                     : 2017:08:04 18:01:25-07:00
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EK 11040 TM 002 PDP 11 40, 35 (21 Inch Chassis) System Manual

EK-11040-TM-002 PDP-11-40,-11-35 (21 inch Chassis) System Manual EK-11040-TM-002 PDP-11-40,-11-35 (21 inch Chassis) System Manual

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