EK EBOX UD 003_EBOX_Instruction_Execution_Unit_Unit_Description_Dec76 003 Instruction Execution Unit Description Dec76

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. EK-EBOX-UD-003

EBOX
INSTRUCTION EXECUTION UNIT
UNIT DESCRIPTION

•

digital equipment corporation • marlborough, massachusetts

1st Edition, May 1976
2nd Edition, January 1976
3rd Edition (Rev), December 1976

The drawings and specifications herein are the property of Digital Equipment
Corporation and shall not be reproduced or copied or used in whole or in part
as the basis for the manufacture or sale of equipment described herein without
written permission.

The material in this manual is for informational
purposes and is subject to change without notice .
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this

manual.
Printed in U.S.A.

This document was set on DIGITAL's DECset-8000
computerized typesetting system_

•
The following are trademarks of Digital Equipment
Corporation, Maynard , Massachusetts:
DEC
DECtape
PDP
DECCOMM
DEC US
RSTS
DECsystem-1O
DIGITAL
TYPESET-8
DECSYSTEM-20
MASSBUS
TYPESET-II
UNIBUS

\
\

CONTENTS
Page
SECTION 1
1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.4.1
1.2.4.2
1.2.4.3
1.2.4.4
1.2.5
1.2.6
1.2.6.1
1.2.6.2

(

2.3 .B

:t 0

INTRODUCTION . . . . . . . . . . . . . . . . . . .
BASIC FUNCTIONAL BLOCKS . . . . . . . . . . .
Instruction Register-Dispatch-Main Control Store
Fast Memory . . . . . . .
Address Path . . . . .. .
Request and MBox Control
KI Style Paging .. .
KL Paging . . . . . .
MBox Error Conditions
--VMA Control . . . . .
_ _ _ _ EBus Control and PI Control
........ .
Data Path
Information Flow To and From Memory
Information Flow I!O and Priority Interrupt

SECTION 2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2 .7
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7

)

2'.4
2.4.1
2.4.2
2.5
2.5.1
2.5 .2
2.5.3
2.6
2.6.1

OVERVIEW

FUNCTIONAL DESCRIPTION
INTRODUCTION . . . . . . . . . . . . . . . . . . . . .
MICROPROGRAM STATES AND PROCESSOR CYCLES
EBox Reset
Microprogram Halt Loop
Microprogram Running
Microprogram Wait State
Microprogram and EBox Frozen
Microprogram Deferred
Microprogram Organization
ASIC MACHINE CYCLE
Instruction Cycle - NICOND Dispatch to XCTGO
Indirect Word Request . . . . . . . . . .
MBox Response to Indirect Word Request . . . .
Address Calculation Continues . . . . . . . . . .
'-.... A READ Dispatch - Set Up Data Fetch and Prefetch
MBox Response to Data Read - Prefetch Begins . .
Executor - Set Up for Store Cycle
..... .
Finish Store Cycle - Perform NICOND Dispatch
PAGE FAIL CYCLE INFORMATION
Page Fail Handling - Functional Flow
Process Table References . . .
TRAP CYCLE - INTRODUCTION
Trap Handling .. . . . . . .
Address Generation . . . . .
PT Reference for Trap Instruction
INTERRUPT CYCLE - INTRODUCTION
~ Duration of Uninterruptable Intervals

iii

EBOX/I-I
EBOX/I-5
EBOX!I-B

EBOX/I- II
EBOX/I -15
EBOX/I-18
EBOX/I- 19
EBOX/I-22
EBOX/I-37
EBOX! I-37
EBOX/I-39
EBOX/I-42
EBOX! I-42
EBOX/I -46

EBOX!2-1
EBOX!2-1
EBOX!2-1
EBOX!2-4
EBOX!2-7
EBOX!2-8
EBOX ! 2-B

EBOX!2-12
EBOX!2-14
EBOX!2-20
EBOX!2-24
EBOX!2-26
EBOX!2-29
EBOX!2-29
EBOX!2-29
EBOX!2-33
EBOX!2-33
EBOX!2-35
EBOX!2-35
EBOX!2-38
EBOX!2-42
EBOX!2-42
EBOX!2-42
EBOX!2-44
EBOX!2-44
EBOX!2-44
EBOX!2-47

CONTENTS (Cont)
Page
2.6.2
2.6.3
2.604
2.7
2.7.1
2.7.2
2.7.3
2.7.3.1
2.7.3.2
2.704
2.704.1
2.704.2
2.704.3
2.70404
2.704.5
2.8
2.9
2.9.1
2.9.2
2.9.3
2.904
2.9.5
2.9.5.1
2.9.5.2
2.9.5.3
2.9.504
2.9.5.5
2.9.5.6
2.9.5.7
2.9.5.8
2.9.5.9
2.9.5.10
2.9.5.11
2.9.5.12
2.9.5.13
2.9.5.14
2.9.5.15

)

Interruptable Instructions
General Interrupt Sequencing
Interrupt Dialogue . . . . . .
BASIC MACHINE MODES INTRODUCTION
Mode Initialization - Private Instruction
Loading Flags and Changing Mode . . .
.. . . . . . . . . .
User Public Mode
Entry from User Public Mode to User Concealed
Concealed Violation Data Reference
Restoration of Programs by the Supervisor
Restoring a Concealed Program
Restoring a Kernel Program . . .
Restoring a User Public Program
Saving Flags and Leaving User
User Concealed
ADDRESS PATHS . . . . . . . . . .
DATA PATHS . . . . . . . . . . . . .
Virtual Memory Address Register
Program Counting . . . . . . .
Loading PC . . . . . . . . . . . .
General Data Path Organization
General Data Path Mixer Selection
AD Field
ADA Field
ADB Field
AR Field
ARX Field
BR Field
BRX Field
FMADR Field
SCAD Field
SCADA Field
SCADB Field
SC Field
SHFieid
The AR Mixer Mixer (ARMM)
VMAField . . . . . . . . . . . . . .. .. .

;:i~·l ~BOX INS~~0~~~ON SET·FUNCTIONAL OVERviEw·
2.10.1
2.10.1.1
2.10.1.2
2.10.1.3
2.10.2
2.10.2.1
2.10.2.2

Effective Address Calculation
Indexing . . . . . . .
Indirection . . . . ..
No Indirection or Indexing
Fetch Cycle . . . . . . . . . .
Instructions That Do Not Require (E)
Instructions That Require (E)
iv

EBOX/2-47
EBOX/2-47
EBOX/2-48
EBOX/2-5l
EBOX/2-56
EBOX/2-58
EBOX/2-59
EBOX/2-62
EBOX/2-62
EBOX/2-62
EBOX/2-62
EBOX/2-64
EBOX/2-64
EBOX/2-65
EBOX/2-65
EBOX/2-67
EBOX/2-70
EBOX/2-70
EBOX/2-72
EBOX/2-72
EBOX/2-74
EBOX/2-74
EBOX/2-74
EBOX/2-82
EBOX/2-82
EBOX/2-83
EBOX/2-85
EBOX/2-86
EBOX/2-86
EBOX/2-86
EBOX/2-86
EBOX/2-87
EBOX/2-87
EBOX/2-87
EBOX/2-88
EBOX/2-88
EBOX/2-88
EBOX/2-88
EBOX/2-88
EBOX/2-9l
EBOX/2-92
EBOX/2-92
EBOX/2-96
EBOX/2-96
EBOX/2-96
EBOX/2-99

(

CONTENTS (Cont)
Page

2.11.2.3
2.11.2.4
2.11.2.5
2.12
2.12.1
2.12.2
2.12.3
2.12.3.1
2.12.3.2
2.12.3.3
2.12.3.4
2.12.4
2.12.4.1
2.12.4.2
2.12.4.3
2.12.5
2.12.5.1
2.12.5.2
2.12.5.3
2.12.5.4
2.12.5.5

Execution Cycle . . . . . . . . . . . .
EBox Data Store Cycle . . . . . . . . .
Basic Four Mode Type Instructions
SKIP, JUMP Compare Instructions
Store Cycle for Other Instructions
INTERF ACE CONTROL
Introduction . . . . . . . . . . . . . .
MBox Control . . . . . . . . . . . . .
DATA FETCH REQUEST EN - Begin EBox Cycle
Begin MBox Cycle - End Current EBox Cycle
and Start Next . . . . . . . . . . . . . . . . .
SETUP PREFETCH - Wait for MBox Response
MBOX RESPONSE RECEIVED
General Memory Cycle Control
EBUS INTERFACE CONTROL .
EBus Signal Lines . . . . . . . . .
EBus Interface Organization . . . .
Interrupt Handling - Loading the Request
Testing the Request ..
Requesting the EBus . . . . . . . .
Beginning the Dialogue . . . . . . .
Interlocks and Dialogue Completion
Basic Input Output Control
Requesting the EBus
Dialogue Overview
Functional Breakdown
PI and EBus to Microcode Interface --:-: .
Sensing the Interrupt .
Requesting the EBus
Beginning the Dialogue .
Terminating the Dialogue
Entry to the PI Handler

SECTION 3

LOGIC DESCRIPTIONS

3.1
3.1.1
3.1.2
3.1.3
3.1.3.1
3.1.3.2
3.2
3.2.1
3.2.2
3.2.3
3.2.3.1

INSTRUCTION REGISTER LOADING AND CONTROL
DRAM and IRAC Control
DRAM Addressing and Selection
IR TEST SATISFIED
Introduction
Implementation
PROCESSOR TIMING
Clock Overview
Crobar and Clock Initialization
EBus Reset . . . . . . ; . . .
Initialization Clock Pulse Generation

2.10.3
2.10.4
2.10.4.1
2.10.4.2
2.10.4.3
2.11
2.11.1
2.11.2
2.11.2.1
2.11.2.2

(

EBOX/2~101

EBOX/2-103
EBOX/2-103
EBOX/2-107
EBOX/2-108
EBOX/2-108
EBOX/2-108
EBOX/2-110
EBOX/2-112
EBOX/2-112
EBOX/2-116
EBOX/2-116
EBOX/2-116
EBOX/2-116
EBOX/2-120
EBOX/2-123
EBOX/2-123
EBOX/2-123
EBOX/2-123
EBOX/2-124
EBOX/2-124
EBOX/2-124
EBOX/2-124
EBOX/2-124
EBOX/2-126
EBOX/2-127
EBOX/2-127
EBOX/2-131
EBOX/2-131
EBOX/2-133
EBOX/2-133

EBOX/3-3
EBOX/3-7
EBOX/3-8
EBOX/3-10
EBOX/3-10
EBOX/3-10
EBOX/3-15
EBOX/3-15
EBOX/3-17
EBOX/3-19
EBOX/3-19

CONTENTS (Cont)
Page
3.2.4
3.2.5
3.2.6
3.3
3.3.1
3.3.2
3.3.2.1
3.3.2.2
3.3.3
3.3.3.1
3.3.3.2
3.3.3.3
3.3.3.4
3.3.3.5
3.3.3.6
3.3.4
3.3.5
3.3.6
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.5.1
3.4.5.2
3.4.5.3
3.4.6
3.4.7

EBox Clock Control
Error Detection
. . . . . . . . . .
Clock Control Logical and Skew Delays
ARITHMETIC PROCESSOR FACILITY
Introduction . . . . . . . . . . . . . .
Address Break . . . . . . . . . . . . .
Address Break INH and Saving Flags
Address Break INH and Loading Flags
Arithmetic Processor Status Register
SBus Errors . . . . .
Nonexistent Memory . . . . .
Other External Errors . . . . .
Input/Output Page Failure Error
Power Fail
....... .
SWEEP and SWEEP DONE
Processor Identification
Cache Refill RAM Facility .
MBox Error Address Register
CONTROL RAM ADDRESSING
Pushdown Stack . . . . . .
Current Location Register (CRA LOC)
Control RAM Dispatch Field . . . . .
Miscellaneous CR Address Gates . . .
Special CR Address Modification Considerations
CLK FORCE 1777 .
CON COND ADR 10
MULDONE
AREAD Logic
CRA Dispatch Parity

APPENDIX A

UNDERSTANDING THE MICROCODE

APPENDIX B

EBOX/3-19
EBOX/3-22
EBOX/3-25
EBOX/3-27
EBOX/3-27
EBOX/3-27
EBOX/3-3l
EBOX/3-31
EBOX/3-31
EBOX/3-33
EBOX/3-34
EBOX/3-34
EBOX/3-34
EBOX/3-34
EBOX/3-38
EBOX/3-40
EBOX/3-41
EBOX/3-43
EBOX/3-44
EBOX/3-44
EBOX/3-47
EBOX/3-47
EBOX/3-47
EBOX/3-50
EBOX/3-50
EBOX/3-50
EBOX/3-50
EBOX/3-50
EBOX/3-52

(

. ABBREVIATIONS AND MNEMONICS

ILLUSTRATIONS
Figure No.
1-1
1-2
1-3
1-4
1-5
1-6

Title
EBox Simplified Block Diagram
Control Pyramid . .
DRAM I/O, JRST . . . . . . .
DRAM Organization . . . . . .
EBox RAM Structures, Interfaces, and Controls Block Diagram
EBox Overall Block Diagram . . . . . . . . . . . . . . . . .

Page
EBOX/l-2
EBOX/1-3
EBOX/l-4
EBOX/1-4
EBOX/1-6
EBOX/1-7

[

ILLUSTRATIONS (Cont)
Figure No.

(

1-7
1-8
1-9
1-10
1-11
1-12
1-13
1-14
1-15
1-16
1-17
1-18
1-19
1-20
1-21
1-22
1-23
1-24
1-25
1-26
1-27
1-28
1-29
1-30
1-31
1-32
1-33
1-34
1-35
1-36
1-37
1-38
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13

Title
Instruction, Dispatch, and Control Formats
Microprogram Main Loop ..
Basic Fast Memory Structure
VMA Structure Simplified . .
PC + 1 Function . . . . . . .
MBox-VMA-EBUS Control Simplified
Page Table Access . . . . . . . .
KI Style Paging . . . . . . . . .
Physical Memory Address Format
Page Fault Overview . . . . . . .
KL Paging Layout . . . . . . . .
Page Mapping (Virtual to Physical)
Typical Paging Path
Immediate Section Pointer
Shared Section Pointer
Indirect Section Pointer .
Pointer Interpretation (Normal Section Pointer; Shared)
Pointer Interpretation (Indirect Section Pointer)
Pointer Interpretation (Indirect Page Pointer) .
Pointer Interpretation Flow Diagram . . . . .
KL Core Status Tables Updating Flow Diagram
Basic Address Translation . . . . . . . . . .
Virtual Address Mapping, KIl 0 Paging Mode
Simultaneous Interrupts
PI Dialogue Overview . . . . . .
API Word Format . . . . . . . .
1/0 Instruction Dialogue Overview
KL 10 Register Interconnection Diagram
Core and Fast Memory Information Flow
Loading ARX . . . . . . . . . . . . . .
EBox Data Paths Simplified Paths Diagram
Input/Output Priority Interrupt Information Flow
EBox Functional Block Diagram
Primary Hardware Cycles
Microprogram Static States
Microprogram Halt Loop
Run-Halt-tontinue Logic
Dispatch Path State Diagram
Basic Microprogram Address Control
CRAM Address Inputs Simplified
Wait State . . . . . . . . . . . . . .
MBox Wait and EBox Clock . . . . .
MBox Wait on Prefetch from Fast Memory
PI 40 + 2n Skip
M Program Modules . . . . . . . . . . . .

vii

Page
EBOX/1-9
EBOX/l-10
EBOX/l-12
EBOX/l-16
EBOX/1-17
EBOX/l-18
EBOX/l-19
EBOX/1-20
EBOX/l-21
EBOX/1-21
EBOX/l-22
EBOX/l-23
EB0X/I-24
EBOX/l-25
EBOX/l-25
EBOX/l-26
EBOX/l-27
EBOX/l-28
EBOX/l-29
EBOX/I-30
EBOX/l-35
EBOX/l-37
EBOX/l-38
EBOX/1-39
EBOX/1-40
EBOX/l-41
EBOX/l-41
EBOX/1-43
EBOX/I-44
EBOX/l-47
EBOX/1-48
EBOX/I-49
EBOX/2-2
EBOX/2-3
EBOX/2-4
EBOX/2-5
EBOX/2-6
EBOX/2-7
EBOX/2-9
EBOX/2-10
EBOX/2-10
EBOX/2-11
EBOX/2-11
EBOX/2-13
EBOX/2-15

liLLUSTRATJONS

2-14

2-1
2 ·17
2-J 8
e

2-19
2-20
2-21

2-25

Fault Handler
Input/Clul:put Handler
I~asic IV[acrdrle ~=ycle ()vervievJ
KL 10 JPn)cessor
Openrtiol1
Instruction
Set
and, Make Indirect
rvTBox

2-27

2-30
2-31

E-'B· nv/) __ ",n
,

~,j'~

-~,

EBOXi2-30

Iltmox
I~Iardvifare

Selection

Executor Setup for Store Cycle
Ferf()rl11.
Page Fan
EBox Priorities
Process Table PF Location
Trap Cycle , , , . . , . .
Central-Server Niodel (Round Robin
J

2-37

EBOX/2-43

2AO

Dialogue Overview
IVl:ode Structure and Hierarchy
Mode Transfer

2-47
2-48

Virtual Address
I

!INDEX

FAST MEMORY

8 BLOCKS
APR
DP

CONTROL
NO TE:
CACHE clearer device CCA
is in the MBOX
'0-1537

Figure 1-1

EBox Simplified Block Diagram

EBOXjl-2

The control portion of the EBox comprises two Random Access Memories (RAMs). The first is called
the Dispatch RAM (DRAM); it consists of.~torage for 512 decimal words, one word for each KLIO
instruction. During instruction execution, the content of the DRAM word provides information about
'-' the type of memory references required by the executing instruction. It also provides an index into the
main control programs contained in a second control memory called the Control RAM (CRAM). The
CRAM consists of storage for 1280 microinstruction words that are structured into a sophisticated
control program. The main progr:aIilconsists of a main loop and a number of subroutines or handlers.
The structure provides for the implementation of a wide variety of internal register transfers, arithmetic and logical control, memory interface, and EBus control functions. The control program is generally
referred to as the "microcode." Associated with the microcode and CRAM is a hardware pushdown
stack, which enables the control program to make subroutine calls up to four levels deep, while performing various KLI0 instructions. The basic machine control flow may be viewed as a pyramid, as
shown in Figure 1-2. The instruction initially enters the IR consisting of two sections. One section, bits
0-8, holds the op code of the instruction, and the other, bits 9-12, holds the Accumulator (AC)
address. During the instruction fetch cycle, the IR is unlatched via Load IR. During this time, it sets up
with the op code. When the fetch cycle terminates, Load IR is removed and the IR latches.

(1
"INSTRUCT I O N " - - - - . x o

CRAM
CRAM REGISTER

10'1~63

Figure 1-2 Control Pyramid

(

Because of the provision for prefetching, instructions may enter IR during the execution of the current
instruction. This implies that, for these cases, the information provided by IR for the currently executing instruction must be somehow saved, while allowing IR to set up with the op code of the next
instruction. This is accomplished by selecting an appropriate word from the DRAM.
The op code contained in the IR is used to address a corresponding DRAM word, and a Next Instruction Condition (NICOND) unlatches the DRAM register during this time. Encoded in the DRAM
register fields (A, B~ is all information necessary for operand fetching, storing, and the microprogram executor jump address. Therefore, those instructions that prefetch an instruction do not
require the IR to be reliable beyond the point of loading the DRAM register.
"

Input/output (I/O) instructions never prefetch. The device select code and operation for these instructions are specified directly in the IR. This must be made available to the microcode I/O handler during
the instruction's execution cycle.
A special case in DRAM addressing is concerned with the JRST instruction. Because the JRST
instruction encodes its JRST type in IR 9-12, these bits can be used directly as part of the DRAM
word for this instruction. Normally, the DRAM address is as shown in Figure 1-3.

EBOX/I-3

777~~~~~~~~~

770~~~~~~~~~

767

700~~~~~~~~~

256
254

f-L.LL.LL.LL.L.L.L.L.L.L.L.L...<.... ..........

--.

lO-BIT SHIFT COUNTER
ADDER AND INPUT
MIXER CONTROL

\
\V

36- BIT SHIFTER
AND AR MIXER
- MIXER CONTROL

/
\

CLOCK
CONTROL

SKIP/COND

!
./

"- '-./ ./

A
R

I DISP/SPEC

MBOX
INTERFACE
CONTROL

~ --l

--.

././

I:~~::CRO

PROVIDE
FUNCTION1 AND MAJOR
BRANCHING WITHIN THE
MICRO PR@GRAM

CODE

-....-....

-- -----------

...-...-"'-

USED I N CONJUNCTION
WITH THE SPECIAL
FUNCTIONS OF THE
DISPATCH FIELD
10- 2088

)

Figure 1-7 Instruction, Dispatch,
and Control Formats
EBOX/1-9

LOAD INSTRUCTION WORD

R,J

•

ARITHMETIC REGISTER
EXTENSION CONTAINED
IN DATA PATH

c8bE

I AC I I I

-1

' - - INSTRUCTION
REGISTER

\ /

I
~

PROCESS
TRAP

PROCESS
INTERRUPT

"Load word select,~d into

DRAM Register

MICRO
PROGRAM

I - DRAMA IBI

r ---------.-

OP-CODE

---l
-I

~-------""\
TRAP REQUEST

•

, JI
,

I DRAM
REGISTER
BEGIN
EXECUTION

....

(

1')

c:-

PROCESS
INSTRUCTION

,-: -

JU-

-,>--§~~O..p-,
/

1
1

I
I

-,/

CALCULATE
EFFECTIVE
ADDRESS

INTERRUPT REQUEST

CRAM-

-' -

EAMOD:
I

A READ

r-------i
1"
PRE- FETCH

-- -"

A READ --r----'-(

FETCH
REQUIRED
OPERANDS

""\,.

FETCH
NICOND

r------...,

J.
1\

{

--,
__ J

~llB';"M..L

___

-- --'I""

'"Me" """,0'
./

r-M.I~Q... __

-<- --)

FETCH NEXT INSTR

PERFORM
EXECUT ION

(

I
I
I

INTERRUPT REQUEST

I
I
STORE
FETCH NEXT INSTRUCTION
RESULTS
____________ v I ___________
JI ':- -'r---,
I

[ -~~l~Nf!D--1
,

__J
--

r -B - WRITE
- - ___ f .....
I

L.
CONTROL
REGISTER

1JUMP'I

1
1
1
1

DISPATCH

I OTHER
10- 2180

Figure 1-8

Microprogram Main Loop

EBOXj1-1O

Table 1-1
DRAMA 3-Dit Code

0
1

2
3
4
5
6
7

AREAD

MEM/AREAD
Immediate class instruction; pre fetch disabled.
Immediate class instruction; prefetch enabled.
Not used
Write-check the paging; prefetch disabled.
Data read required; prefetch disabled. '"
Data read required; pre fetch enabled.'"
Data read required as separate cycle; also write-check the
paging; prefetch disabled.
Data read modify write required; prefetch disabled.

DISP/AREAD
DRAMJDISP
DRAMJ DISP

42
43
44

45
46
47

*These two cases are distinguished only by dispatching to different microcode locations. The microcode entered at location
45 prefetches, that at 44 does not.

(
The next block is entered to perform the specific execution function or functions for the particular
instruction by the microprogram giving a DRAM J dispatch. Remember that each instruction has its
own DRAM word with a unique Jump field specifying where to go for that instruction's execution.
The execution is very complex and is described in detail elsewhere in this manual. Basically, it performs
all required arithmetic, logical, or other types of functions required, and may also, in some cases, fetcD
additional operands as required.l Upon completion of this portion of the microprogram, the next
instruction may be started, provided that no data storage is required. If storage is required, two basic
cases must be considered. Those instructions that do not know where to store their data utilize the B
field of the DRAM as an index into the final block to store results. After storing results, the next
instruction is fetched and a NICOND dispatch is issued. Instructions that know where to go specifically in order to store their data do so by jumping to a specific location in the microprogram, but may use
the B field of the DRAM to decode additional types of memory requests as required. This completes
the basic loop.

1.2.2 Fast Memory
--An instruction word has only one 18-bit address field for addressing any location throughout all of
memory. Most instructions, however.nave two 4i bjt fi~ for addressing the first 16 locations of
memory. These 16 locations consist of a set of 16 general-purpose, high-speed integrated circuit registers grouped locally into eight physical blocks .. ,.which are software-assignable by block. Non-I/O
instructions have an accumulator address field that ca'n address one of these 16 locations as an accumulator. Every. instruction has a 4-bit Index register address field that can add~ss 15 of these locations
for use as Index registers in modifying the 18-bit memory address. (A zero mdex register address
specifies no indexing.) The factor that determines whether one of the first 1610catio~s in memory is an
accumulator or an Index register is not the information it contains, nor how its contents are used, but
rather how the location is addressed. The eight blocks of fast memory are contained physically on the
data path board within the~ This allows much quicker access to these locations whether they are
addressed as accumulators:lmieX'registers, or ordinary memory locations. They can even be addressed
from the program counter, gaining faster execution for a short but often repeated subroutine. Of the
~
eight blocks contained within the EBox, bl~s permanently assigned to the microcode. Referring
~ to Figure 1-9, the monitor uses an assigne~ock in the same way that a user program described in
the following paragraphs would. The microcode uses the assigned AC block when executing complex
instruction algorithms. From the remaining blocks (0-6), two can be assigned under program control
lDA TAO PAGj as the current and previous context AC blocks. The current context AC block is used
by the user program for' exin in effective address calc
.on and for general storage as specified by
the A C field of the instruction and/or by tee ectlve virtual address (location 0-17).
EBOXjl-11

7-(ASSIGNED TO MICRO CODE)

SOURCE
OF ADR's
(4 LINES)

FM BLOCK 4,2,1

FAST MEMORY
} BLOCK SELECT

FM ADR 10,4,2,1
FM BLOCK
SOURCES

(_':r:t"

,F_M_______________

(
CONTROL
RAM

CONTROL
REG

CURRENT

I ' L - - - ~~: ~~OMONITOR

"--___B_L_K_R_EG____-'---___B_L_K_R_EG
__- - - ' ,.--_ _ _ IN STR U CTl 0 N
10-2181

Figure 1-9

Basic Fast Memory Structure

The previous context AC block is used by the monitor to allow the monitor to reference the previous
user's address space to pass arguments, data, or status information between the user program and the
monitor. This is normally done when the user program executes a monitor call for some type of
service.

~ The microprogram running within the CRAM may select eight possible sources to be the word address

?f\.

for fast memory; these sources are indicated on the figure as follows:
AC dJ
AC+l
AC+2
AC+3
AC+4
ARX 14 - 17 (¥I'J.. ) tf3''j<.
VMA32-35
~~
CRAM 05 - 08 ~~

""'- -

...

The selection of the appropriate source is a function of the 3-bit microinstruction
DR FIELD.
s
The block to be used is selected by the same FM ADR FIELD and corresponds to three bloc
as indicated in Table 1-2.

EBOX/l-12

(

Table 1-2 FM Selection
FM ADRField
0
2
3
4
5

6
7

FM ADR 10, 4, 2,1 Source
AC
AC+1
ARX 14-17
VMA 32-35
AC+2
AC+3
AC+4
CRAM #05-08

FM ADR BLK 4, 2, 1 Source
Current Block
Current Block
XR Block*
VMA Block*
Current Block
Current Block
Current Block
CRAM #02-04

*These may select either the current or previous AC block address.

(

The selection of AC, AC+l, AC+2, and AC+3 is a function of the class ofKLlO instruction being
performed. All non I/O instructions specify an accumulator address in the instruction word, bits 9-12.
The logical instructions - Logical Shift Combined (LSHC) and Rotate Combined (ROTC) - specify
the use of both AC and AC+ 1. Similarly, the fixed-point arithmetic instructions Multiply (MUL),
Divide (DIV), and Arithmetic Shift Combined (ASHC) specify use of AC and AC+ 1. The double
integer arithmetic instructions Double Add (DADO), Double Subtract (DSUB), Double MUltiply
(DMUL), and Double Divide (DDIV) specify use of AC, AC+l, AC+2, and AC+3. As pointed out
previously, the microprogram is permanently assigned AC block 7 for its own use. During extended
instruction processing, the microprogram addresses words in AC block 7 by using magic number field
bits 05-08, while selecting AC block 7 with magic number field bits 02-04. These ACs provide temporary working storage for the microprogram. Similarly, the microprogram addresses AC+4 by combining the AC address taken from IR AC9-2 with bits of the magic number field in an adder network
to produce AC+4

(

For selection of AC, AC+ 1, AC+2, AC+3, or AC+4, the current block is always used. Whenever a
main memory reference is made, the microcode references the fast memory location given by YMA
32-35, enabling the hardware to switch the reference to fast memory, if necessary. When the instruction's effective address is calculated, the microprogram allows the specified Index register to be
addressed in fast memory by enabling ARX.-L4-17 to address the word. For both cases, Le., VMA
32-35 or ARX 14-17 addressing fast memory, the AC block may be either the current block or the
previous block, but is a function of the context of the instruction.

-----

If an executive XCT is performed in response to a user's call (MUUO), then the previous physical
block and current physical block will be made to be different unless the operating system saves the
user's current AC block and then wishes to use the same block once again, which is unlikely. As an
example, assume the user is assigned AC block 1; his previous AC block would initially be 1 also. If the
user then performs an MUUO, the executive subroutine entered may safely load the current AC block
with some other block number and the previous user block will remain unchanged. The operating
system may perform an executive XCT utilizing the user's previous block and an AC within that block.
The hardware enables the selection at the time of the previous block for indexing. In addition, the
operating system may also reference the user's AC block (previous context block 1 in the example)
from the VMA. In this case (referring to Figure 1-9), mixer selection 3 is enabled and the micro word
FM ADR field specifies VMA.

During normal instruction processing, if VMA bits 13-31 are equal to 0, the address in bits 32-35 is an
FM address.
EBOX/I-13

f
.>

Some examples using the current AC block in various selections are given below. Assume the following
is performed by the operating system:
EXAC = 1
HRLEI EXAC , 102200

;This will default to Exec block
;#0, AC#1
;Load bit, current Blk#2
;Previous Blk#2.

DATAO PAG, EXAC

;Load the current Blk# = 2, and the
;Previous Blk# = 2.

JRST 2, @ USRPCWD

;Pick up user mode , flags , and
;turn on user.

(
The following codes are for the user:
AC1 =1
AC2=2
MOVEI AC1, 777777
HRLEM AC 1, AC2
SETCMM,AC1
PUSH AC1, 3(AC2)

;This will be in Blk#2
;This will be in Blk#2
;The word 0,777777 to ACl
;The word 777777 ,777777 to AC2
;The one's comp of the word in ACl to AC2
;Which is equal to 777777 ,0
;This instruction attempts to
;push the contents of AC2 into
Jocation ACl.lt will cause PDOVL
;and this generates TRAP#2.

In the example, the symbol EXAC is defined as the number 1. Assume, for this example, that EXAC is
referenced as an AC accumulator in executive block O. The first use of EXAC is in the instruction
HRLEI EXAC, 102200. This instruction takes the number in the Y field of the instruction, which, in
this example, is the effective address, and places it in the left half of EXAC (which is executive AC1),
with the sign of the right half of the word 0,102200 extended in the right half of EXAC. In this
instruction, the current AC is referenced in bits 9-12 of the instruction, and the mixer selection is O. To
load the user AC blocks, both current and previous, it is necessary now for the executive to perform
the indicated DATAO PAG instruction.
The left half-word in EXAC contains the necessary bits to enable the loading of the current and
previous blocks (EBus bits 6,,7, and 8 for the current block and bits 9, 10, and 11 for the previous
block). Next, we assume location USRPCWD contains the appropriate bit configuration to start the
user for whom we loaded the AC block numbers. The instruction JRST 2, @ USRPCWD makes an
indirect reference to location USRPCWD. The resulting word will then contain the user mode bit (bit
5), possibly the public mode bit (bit 7), any other relevant flags in the remaining left half-word, and the
user virtual address in the right half-word. The user has defined the symbols ACI and AC2 as having
the values 1 and 2, respectively. As indicated in this example, these correspond to ACI and AC2 in
block number 2. The first instruction performed by the user is MOVEI AC1, 777777, which places the
number 0,777777 in accumulator 1. On the next instruction, the word in ACI as addressed by instruction field bits 9-12 is read out. Remember that during the effective address calculation, the AC number
is loaded from ARX 9-12 into register AC in the EBox.
EBOX/I-14

(

The FM ADR field of the microword that is performing the fast memory reference will specify a field
function of 0, which will select the current }'lock as well as register AC which, as pointed out, contains
the value of AC 1 (1). The operation, specified by the instruction, is to take the right half of ACI and
store it into the left half of AC2 with its sign extended into the other half-word. Because the sign of the
right half-word in ACI is negative, the result is the word 777777,777777. Notice that we must now
reference AC block 2, location 2, by using VMA bits 32-35. This operation is specified with a different
microcontrol word and at a different time than the fetch of the word from ACl. Actually, the content
of ACt is obtained by performing a READ; the word 777777,777777 is stored into AC2 on B WRITE.
The next instruction, SETCMM, reads the word from AC t as addressed by VMA, takes the 1's complement of it, and stores the result (777777,0) back into ACt again as addressed using VMA. Thus, the
same address is used for read as well as write. Finally, the PUSH instruction performs an indexing
function using the current AC block. The number 3, which is the Y field in the instruction, is added to
the number contained in AC2, as addressed in the example, using the mixer selection of 2 (XR).

Thus, the address is taken from ARX 14-17 during the effective address calculation. The number 3 is
added to the number 777777,777777 and the right half of the result (2) is used as the effective address.
Then the instruction attempts to push the number 777777,777777 onto the stack as addressed by the
updated right half of the word in ACl. The updating takes place first. The word is fetched from AC1
using the current block and the address in the EBox register AC. Then, this word has + 1 added to both
halves and, if the left word is such that the addition causes a carry from bit 0, a pushdown list overflow
trap occurs.

1.2.3 Address Path
The EBox performs a program by executing instructions retrieved from locations addressed by the PC,
a 23-bit register contained in the EBox data path. At the beginning of each instruction, PC is
incremented by one so that it normally contains an address one greater than the current instruction.
Sequential program flow is altered by changing the contents of PC, either by incrementing it an extra
time as in a Skip instruction, or by replacing its contents with the value specified by a Jump instruction. Instructions may be fetched either from core memory, which is external to the EBox, or from fast
memory, which is internal to the EBox.

(

Generally, instructions provide at least two operand addresses to the EBox. One address is that of an
internal accumulator, and is addressed by bits 9-12 of the instruction. The other address, also supplied
" - by the instruction, may be used to address eith~re or fast memory and is contained in bits 185 of
the instruction word. This is a composite address, such that bit 13 specifies the type of addressing, i.e.,
direct or indiiect; bits 14-17 specify an index register for Use in address modification; and bits 18-35
address a virtual memory location.
~~

Because the PC is used to keep track of where in the program the EBox is executing instructions, an
additional register is provided to handle addresses that can be generated during effective address
calculations, durin&. oj?eran.d reads and/or writes, and at other times. This 23-bit register, also contained in the EBox data path, is called the VMA register.
Figure 1-10 illustrates the oasic path connections from the-PC and AD. A control field consisting of
two bits in the microinstruction is provided to select the source of1nput to VMA. This field is called
the "VMA field." In addition, two other fields are used to provide alternate iilpUt to the VMA as well
as provide the ability to increment or decrement the VMA directly. These fields, also a part of the
number field."
microinstruction word, are called the "condition field" and "magic
,
Referring to Figure 1-10, to load the VMA from AD, the micrOinstruction VMA field is coded symbolically as "VMA/ AD." The field format is indicated at the lower right of the figure. The AD is
enabled into the input of the VMA register by the function VMA +- AD, and the input to VMA is
enabled for any of the following functions: VMA +- PC, VMA +- PC+ 1, or VMA +- AD.

EBOX/1-15

VMA 13-35
71+---------,
M

I
N
VMA 27-33
T I+---'-"'c...:...::c.:.....;=-=--{

R
F
A

MBOX GATE 27-35

~ ~---------~
COND/VMA DECREMENT
COND/VMA INCREMENT

(
VMA-PC
VMA-PC+1
VMA--,m(ANY OF THESE
LOAD VMA)

LOAD

VMA- AD
VMA-#:THIS
ENABLE GIVES PC+1
OR A COMBINATION OF
# AND MISCELLANEOUS
SPECIAL CONDITIONS

(
CRAM
VMA
FIELD
i4------MICRO INSTRUCTION-----.t

FUNCTION

VMA/VMA

1
0

VMA/PC+1

VMA/PC

VMA/AD

Figure 1-10

VMA Structure Simplified

EBOX/1-16

10-1556

is cod.ed to sp<;clty
to VlvfA +- V1VIA .AD all

ADto
1!l forced to

regi3t{;';r
and A..DJl3':P
is i10t used; H"H'"'"r.·".~.

j·JOTE :
PC+1

I~,JH

is normcd!y false e:':.c.ept

1~or

Hue

fol~owint]

L NICOND d!5palch

iO--155?

The special number, magic number, and miscellaneous conditions shown on VMA AD in Figure 1-10
are used during LUUO, MUUO, aru1...f!.handliftg to generate a range of special addresses to reference
the user or executive process tables in memory. During these types of functions, the VMA AD is
controlled by VMA #, which enables the Boolean function "B." MVA AD B input bits 27-35 are
manipulated, while bits 18-26 are cleared; this allows for the generation of process table word aadresses in the range of 000-777. Note, however, that addresses in the range of 40-510 only are currently
generated by hardware.

1.2.4 Request and MBox Control
In general, most of the EBox memory request type operations are controlled by the 4-bit MEM field in
the microinstruction (Figure 1-12). This may be used alone or with the DRAM A or B field values for
most reads and writes. In addition, the 5-bit special microinstruction field (SPEC) can specify a function SP MEM CYCLE, which is sometimes used with the magic number field (a 9-bit microinstruction
field) to modify MBox read and write operations, e.g., for MUUO or LUUO. Note that the basic
MBox activity involves a request, a virtual address, and MBox qualifiers consisting of a multitude of
control signals that qualify the type of request being made. This is followed by:
1.
2.
3.

A response from the MBox with the data when the request is successful,
PF HOLD followed by MBox response IN and no data on a page fault, or
MBox response IN with data followed by MB PAR ERR, for an MB parity error condition.

Additional conditions are covered elsewhere in this manual.

_ VIRTUAL ADDRESS

(

NORMALLY FROM
AD OR PC

VMA
CONTROL
VMA/VMA
PC
PC+I
AD

E BOX REQ

DEMAND

MBOX RESP IN
TRANSFER
MBOX QUALIFIERS

EBUS
CONTROL

MBOX
CONTROL

MB PAR ERR

I---

PF HOLD

r-J
JI
A

DISPATCH
RAM

MEMI
A READ
B WRITE
FETCH
REG FUNC
A IND
BYTE IND
LOAD ARX
WRITE
RPW

52 53

EBUS PAR BIT

EBUS
CTL

~I.----- MICRO
Figure 1-12

(

SPEC I
SPEC
MEM CYC
#OO-OB

5960 65

~ VM~~MEM COND~SPEC ~

EBUS QUALIFIERS

CONDI

76
#

INSTRUCTION - - - - - - - - - + 1
..

MBox-VMA-EBUS Control Simplified

CJ
EBOXjl-18

tIle IviBox
a

are lmplemlell'!:,:!d;
the se:fxmd

KIlO

regi3ter§ ar©
is I10rmaHy
a normal
th!e

U8r:~~ l.JSER B!~SE
ESR - E)(EC B!\SE

Figure

is obtained am!
half-word entries

1~1

""C"d.""''''"'

the
at a

The five bits A, P, W, S, C (generally called use bits or page descriptor bits) are tested against the
qualifiers sent by the EBox during the ref~rence. Then the MBox, using the physical address, looks in
the cache for the word requested. If it does not find the word, it concatenates the physical page address
(Figure 1-14) with the virtual word address provided in VMA bits 27-35 and makes a second physical
memory reference. This address is indicated in Figure 1-15.

(13 BITS)
18

USER PROCESS
TABLE

•
•

USER PAGES
0-777

2627

(13 BITS)

•
PAGE776

PAGE777

377
?

PAGEO

600

(13 BITS)

•

EXEC PAGES
0- 337

757

HALF WORD

I I I Isic I PH::~~AL I
A

\-.

A CAN CAUSE
{
PAGE FAULTS P W-

18 BITS

ACCESSABLE IN CORE

~UBLIC

PAGE
WRITEABLE

S -

FOR SOFTWARE USE

C -

USE THE CACHE

PHYSICAL
PAGE:512 1O
WORDS

(

l/.

.. \

1
USE BITS

10-1551

Figure 1-14

KI Style Paging

EBOXjl-20

SUPPLI ED BY
VMA 27-35

SUPPLI ED BY
PAGE TABLE
(

35
QUAD WORD

PHYSICAL PAGE

1 + 1 - - - - - - - - 22 B I T S - - - - - - - - - - + l _ 1
10 -1552

Figure 1-15

Physical Memory Address Format

NOTE
A quadword is a block of four contiguous words
whose address differs only in the two least significant
bits.

In practice, address bits 14-33 specify a 4-word block called a quadword; bits 34 and 35 specify which
word within that quadword is required by the EBox, or is being written by the EBox. Once the address
translation process has been successfully completed for a virtual page, subsequent references to that
same page cause the MBox to fill in She corresponding words in the cache within the MBox. Each time
a reference finds a valid word in the cache during a read, it is placed on the EBox cache data lines and
MBox response is issued. Page faults occur as follows: For the initial reference, the MBox looks in the
hardware page table in the MBox, does not find the physical page address, and performs the subsequent process table reference (refill cycle) for the half-word containing the use bits and physical page
address. Then, upon receiving the eight half-word entries from core meriiOrY:""the MBox finds the
access bit turned off, i.e., 0; then a page fault is generated. The eight half-words are always written in
the MBox hardware page table (directory) whether or not the access bit in the associated word is on.
However, when the access bit for the associated word is off, the MBox asserts PAGE FAIL HOLD.
The MBox loads an internal register (EBus register) with a pase fail status..word that describes the type
of fault and also contains information about the user's virtual address. Referring to Figure 1-16, the
EBox detects the PAGE FAIL HOLD level from the MBox, and forces the CRAM address logic to
CRAM location 1777. Here the page fault handler is entered. It performs the indicated functions
(Figure 1-16), ana enters an Executive routine to handle the fault.

• CLEAN UP
CURRENT
INSTRUCTION

("
\

READ MBO X, PF WORD
E !--"'=c.::-"-.;:...::...c.:.....:....:.--"-=_ _--...._
~~W~R~ITE~UP~T~L~0~C~5~00~.~50~1--~

I
N
T
E
R
F

C
E

• READ PF
CONDS FROM
MBOX

READ NEW PC WORD LOC 502

• WRITE COMPOSITE
PF WORD IN UPT
LOCATION 500

PF HOLD

• WRITE OLD PC
WORD IN UPT
LOCATION 501 '

MBOX
RESPONSE
IN '

CLOCK
CONTROL

• READ NEW PC WORD
FROM UPT
LOCATION 502

r-------+t

* If

BITS 5 and 7 of
PC WORD are 0

10 -1553

(
Figure 1-16

Page Fault Overview

EBOX / I-21

In addition, the MBox asserts MB PARITY ERR five MBox ticks after issuing MBOX RESPONSE
IN. This sets APR MB PAR ERR, which causes an interrupt. The remaining errors set appropriate
APR error flags and likewise cause interrupts 6n the assigned APR interrupt channel.
1.2.4.2 KL Paging - The KL paging facilities support sophisticated operating system features such as
efficient program working set management and demand paging, and extensive sharing of data and
programs on a page-by-page basis. Much of the paging mechanism is implemented by the KL microcode, rather than just specific hardware. This combination of microcode and hardware is referred to as
the KLIO pager of TOPS-20 paging.

Refer to Figure 1-17. Each user's virtual address space comprises 32 equal sections of 256K words per
section (512 pages of 512 words per page). A section is represented by one of 32 sectionpointers
located in the User Process Table (UPT). For EXEC sections, the 32 section pointers are in the EXEC
Process Table (EPT). The monitor can divide the EXEC address space into "per-process" and "perjob" areas through the use of indirect pointers; no such division is built into the Pager.

USER BASE REGISTER

...

PAGE TABLE

L : E R PROCESS TABLE

PRIVATE PAGE

PRIVATE
USECT

SHARED

SECTION~

SPT BASE REGISTER

SPT
l.::ARED PAGE

{flB0
TABL

PAGE TABLE

~~
~
~
~

\
"

"
INDIRECT

~
"

,",

•

~~
SHARED PAGE

,,,-"-\.'-: ,\.\.\.\.\.\.\.\.\.'-: ,\.~

r-'
PRIVATE PAGE
(+ INDIRECT I

PAGE TABLE

UPT

l
10-2610

Figure 1-17

KL Paging Layout
EBOXjl-22

(

A section pointer eventually addresses a page table that represents all pages in a 256K virtual address
space. The section pointer may be Immediat~, Shared, or Indirect, but must yield a physical address of
a page table that represents all pages of the section.
The page pointer is divided into three sections: Type Code, Access Bits, and Storage. Figure 1-18
illustrates the basic page pointer format and Figure 1-19 shows the sequence of steps in its
interpretation:
1.

A virtual memory reference addresses a section pointer in the UPT or EPT for EXEC
operation.

The section pointer is used to fetch an entry from the SPT (this is a pointer to a page table).

The SPT entry points to a location within a page table representing 512 pages by one page
pointer for each page.

The page table holds the physical page number required to complete the virtual to physical
address mapping.

STORAGE ADDRESS·

rr--------------------~A~--------------------_,

(IMMEDIATE POINTER ONLY)

CODE

12-17=0

:PAGE IN MEMORY

CODE:

;23-35 < PHYSICAL PAGE NO _>

0- NO ACCESS

{

;18-22

1 - IMMEDIATE
12-1U'0

j.:~~~

4-7 - RESERVED (NOT USED)

:PAGE NOT IN CORE
;< BITS 13-35 MAY BE USED TO
HOLD DISK OR OTHER BACKUP
STORAGE ADDRESS>

BITS: (defined with.
logic 0 in the bit position).
P =

PUBLIC
Reference only from the

(

concealed or kernel mode.

W =

·STORAGE ADDRESS

WRITE

This example shows an

Write r..sferences not allowed.

elementary type of page
C =

CACHE

mapping : the Section Pointer

Data fro m page may be
placed in the cache_
B6
1; CACHE
B6 = 0; NO CACHE

points through the SPT to a
Page Table_
(TOPS-20

USIS

shared or

indirect section pointers).
10-2611

Figure 1-18

Page Mapping (Virtual to Physical)

EBOXjl-23

UPT
(USER PROCESS TABLE)

SPT
ENTRY

SECTION
POINTER

PAGE TABLE
(512 WORDS)

SPT
(SPECIAL/SHARED
PAGES TABLE)

PAGE
POINTER

DATA PAGE
(512 WORDS)

USECT

f---/

.... '-'

PHYSICAL
ADDRESS
REQUESTED

,..L"

10·261 2

Figure 1-19

Typical Paging Path

(
These steps describe the most elementary and immediate reference type. The complexity of other
reference types requires a discussion of pointer types.
Page Pointers - The pointer type is encoded in bits 0-2 of the page pointer word (Figure 1-18). Again
the pointer types are:
Code

Function

No Access
Immediate or Private
Shared
Indirect
Not Used (reserved)

1
2
3

4-7

(

The Immediate Pointer (Figure 1-20) holds a storage address in bits 12-35. The pointer is called a
private pointer because it is "private" to the particular page table containing the pointer. This should
not be confused with the Public bit, which describes the type of access allowed.
The Shared Pointer (Figure 1-21) contains an index that addresses into the Special/Shared Pages Table
(SPT). The SPT Base Register (SBR; reserysd AC block) points to the beginning of the SPT. The sum
of the SPT index and the SBR points to a word containing the storage address of the desired page. The
word number from the virtual address is used to complete the reference. Regardless of the number of
page tables holding a particular shared pointer, the physical address is recorded only once in the SPT.
Therefore, the monitor can move the page with only one address to update.

(

The Indirect Pointer (Figure 1-~2) identifies both another page.table and a new pointer within the page
table. This allows one page to be exactly equivalent to another page in a separate address space. The
object page is located by using the SPT index.
Like a Shared Pointer, the SPT index in the Indirect Pointer allows the physical address of the page
table to be stored in just one place. If the associated page is in memory, the page number field of the
Indirect Pointer is used to select a new pointer word from the page table. This pointer can be anyone
of three types previously described, or no access and the access bits are ANDed with the access bits of
the Indirect Pointer.

EBOX/ 1-24

( J

IMMEDIATE SECTION POINTER (1,)

PAGE TABLE ADDRESS

BIT

DEFINITION

00-02

Pointer Type

Public Bit

DESCRIPTION
A 1, in this field defines the Immediate
Section Pointer.
If this bit is off (0), the page may only be
referenced by programs running in Concealed

or Kernel Mode_
04

Write Bit

Not Used

Cache Bit

When set, allows write references to be
executed to the page.

When set, allows page data to be entered
into the Cache.

07·22

Not Usee!

23-35

Address Bits

Defines the Page Table Address,

NOTE: BITS 12-35 CONTAIN A "STORAGE ADDRESS"_ IF 12-27 .. 0, A TRAP IS CAUSED.

1 (}-2613

Figure 1-20 Immediate Section Pointer

SHARED SECTION POINTER (2.)

•

W~C~

35
SPT INDEX (SPTX)

BIT

DEFINITION

DESCRIPTION

00-02

Pointer Type

A 2, in this field defines the Shared
Section Pointer_

Public Bit

If this bit is off (0), the page may only be
referenced by programs running in Concealed
or Kernel Mode_

Write Bit

When set, allows write references to be
executed to the page_

Not Used

Cache Bit

07-17

Nbt Used

18-35

SPT Index

When set, allows page data to be entered
into the Cache_

The SPT entry is found at the physical core
address given by the sum of the SPT base
register and the SPT I ndex_
10-2614

Figure 1-21

Shared Section Pointer

EBOXjl-25

~r~Cilp,ECT

SECTmN POiNTER !3 D )
;;:

:::

113

'""""""I~~I~~~~?:a'~-'""~"~~~-~-~~'---~"-~~-'-'--;I
i)

I __LI ____
", I
I ~~
~

L~L

'iN

I"J:',GE l\I:iJil,1l8EPi

PP,GE TABLE IOEN1r!Fi1:[I

is?TXl

, ~~L~~~~~,._"~__!,",_~,_"",_._._~_"~_~~".._ _~~_,_ _ oj

oo-o:!

/5;;. 313 in thiz
Sf.H.~'-~iofl

ne~d

dedimt5 the

~ndi[r9Cl

f\:;JinitG!' .

U th-is b1i!: ~s (':':rf {fJL tha

[p'ilg!:)

rrDaJY if}n~v Ihe

~·etenHlItoo;l

flJiV prOflnHlI1l:B u"lHIllnirng in C01"l],':ooied
U[f K5fnci ModfJ.

Bit

'iJ\lhelil Sli.l'~~ a!k:inlJ5 ':uil'ite ~'il]~:erc!l1lc~~ tli.ll be

f"ncGcfJt('5d to

1rVhen

Cr.whe Bit

££',f d ;?Jlk'\-~.Ja p~!lj!8

ill'lito, the

Sel~iol1!

Ta[oira

~nde;.(

~Pa9!H! NumbF.H"~

18-35

~-ch!E! ;J'-il{!J'3'.

nm:rh:~;i.t't0S; t]le iq,:H~]il:io;r~

o·~ t!1E"

Th~

dfrta t(l',

~]le :a~ll'~.gU'ed

C;;.eh~.

new

wi1tullun the P21g$

r-Q~nte'; H~l!direct

7Elb~G

}"ahwen!J;;0L

gPT ent!t)f is; ·~(wnd at·i;h13 iJhysi~1 ,~oU"£,
ghn9:ril bV thi21 :sum of the S~)T ba:se

~;j(::kllij'~
ire{~ifrt®r

and the SPT

[nrlI3;~.

10-2615

Figure]

The Indirect
after

vUtUU.''"6

Indirect

Pointer

arbitrary in depth, but the PI
interrupt in the C!l§©
lon.g

nrUt,liT,IV

SpecE:a§/SRuU'ecl! P~ge§ TafulRe
Speciai/Shared
Table
addresses of
that are shared
page tables, or of pag'es
modification to
pages by 't"H(!Wl!,:,>H,,§
They are stored in OJ1'e COmJ.1lOn location to
Index is added to
SIP base
to
B\ physical address
entry.

management requires
the Con;; 318.tu8 Table (CST)
permits the nWflitor to

placing a 1 in that bit
a H:fe;rence is
in the page:r
CST
in the
position assigned to the pfOGeSS making
bit (35) is set if
p0\ge is nlOd£~
fied,
tlu;, monitor to
swapping out pages to which
refennJ.ces are

EBOX/1-26

(
UBR
PAGE
TABLE

UPT
SBR

~t=======r-__~r-_P_AG_E

SPT
USECT+
SECTION NO.

__,

WORD
NO .

SPTX

.-l~--t

PAGE NO.

WORD NO.

500

VMA

• 323
26 27

SECTION NO.
PAGE NO.
WORONO.

00
500
= ;1;23

SECTION NO.

- PAGE NO.
... WORD NO.

00
367
323

010
0

HARDWARE PAGE TABLE
500=367

}

USECT

PHYSICAL

VIRTUAL

SPT INDEX (SPTXI

220
23

35
SPTX =220

ENTRY
~

SBR

SPTX

~0------------------------~12--------------------------------------------35~

SPT

PHYSICAL ADDRESS OF PAGE TABLE
100

C(SBR + SPTXI

N = 100

PAGE TABLE
100
500

STORAGE ADDRESS OF PAGE
367

~
~
12
2
35
N
® ~~~----------------~----------------------~------------~
0

C (UBR' USECT + SECTION NO.1 CONTAINS SPTX
C (SBR + SPTXI CONTAIJ,lS PAGE TABLE PAGE NO. N
C (N'MI CONTAINS STORAGE ADDRESS OF DESIRED PAGE

NOTES: A'B:: = A CONCATENATED WITH B
Assume page is in core.
1 ()'2616

Figure 1-23 Pointer Interpretation (Normal Section Pointer; Shared)

EBOXjl-27

PAGE
TABLE
UBR
SECTION
TABLE, !

UPT
SBR

SPT

USECT+
SECTION NO.

PHYSICAL
TABLE

11-----1

(N)

LINE
NO.

1....----1

SECTION
VMA

011

I
0

17 18

SECTION TABLE
INDEX

USECT+
SECTION NO.

I®

PAGE NO.

LINE NO.

356

562
26

SECTION TABLE IDENTIFIER (SPTX)

172

102
17 18

SECTION TABLE
ADDRESS
SPT
035

ENTRY
172

'-...IJ

'-V

SBR

SPTX

---.J1 C(SBR + SPTX)

'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.J...._®_P_ _ _ _ _ _ _2_2_7

(

PHYSICAL ADDRESS OF NEW PAGE TABLE
SECTION

227
\-.,..-I

T~E~I_0_0_l_.~I_________~__QY____________________12_7_~ C(P'N)

PAGE

STORAGE ADDRESS OF PAGE

127

TABLE
356

\-.,..-I

001
0

345

12
VMA

C(A'M)

PMA

00 356 562 = 00 345 562
NOTE: Assume page is in core.
10-2617

Figure 1-24 Pointer Interpretation (Indirect Section Pointer)
EBOXjl-28

PAGE TABLE 1"

PAGI NO.

-.l
3

I I®I

SPTX'

I---

SPTX'

PAGE
LILE
NO.

-*-PAGE TABLE 2

f
PAGE TABLE 1

PAGE NO.

100

500

PRIVATE

PAGE TABLE IDENTIFIER (SPTX')
127

210
17 18

NEW PAGE TABLE PAGE NUMBER
SPT

ENTRY

035
1...,/
SBR

127
1...,/
SPTX'

®
o

277
35

<;:IMMEDIATE>
PAGE TABLE 2

•

,;2.. 27
1...,/

210
1...,/

11
2

107
12

*Page table pOinter now Indirect instead

VMA
00 500 323

of Immediate. From Figure 1-23, the UPT
addressed Page Table 1. Now, because
page table pointer is Indirect, go back
through SPT again. This results in a
new Page Table (2).

PMA
00 107 323

which is now equivalent
to a VMAof:
00 210 323
'--./

NOTE: Assume page table is in core.

with SPTX' = 127
10-2618

Figure 1-25 Pointer Interpretation (Indirect Page Pointer)
EBOX/1-29

Goa~

l
i"

~ T~"'e HR can:ai,lis
, a Sf.!ction

Poh~lJ.elJ.

10-2619/\

Figure 1

Poi.nt~r

In.terpretation Flow Diagram (Sheet I

EBOXjl-30

(IMMEDIATE)

r Bits 23-36 contain
----l
L the Page Table address.

C(SBR +
AR <18-35>
... AR

r SPT Base Register (SBR) and
- - - -I SPT Index (SPTX) point to Page

L Table Physical Memory Address (PMA).

___ ..rL

Same as shared, except
new section pointer.

AR <9-17>-+
SECTION NO.
C(SBR +
AR <18-36»
-+ AR
N

CST UPDATE
TRAP
TYPE 4-7
(UNDEFINED)

C(AR<23-35>'
SECTION NO.
-+AR

10-26198

Figure 1-26 Pointer Interpretation Flow Diagram (Sheet 2 of 5)

EBOXjl-31

TRAP
(NOT IN CORE}

AR <23-35>
.... PTPAGE
C(CBR + PT PAGE}
.... AR

r Page Table in core use

- - - -I

Fetch Page Pointer from:
PT PAGE <14-26> and Current
Virtual Page came from either;
1} VMA <18-26>, or
2} AR <9-17> of last Indirect Point

PT PAGE to update

L CST information .

(
TRAP

(AR'CSTMSK}
V

CSTDATA ....AR
STORE; C (PT PAGE'
PAGE NO.} .... AR

r Modify CST Entry for this

I
I

I physical Page Table.

>- - - - -I

Bit 35 (modified bit} is not
set because Page is not
L being changed.

I
P'AR <3> .... P
W'AR <4> ....W
C'AR <6> ....C
AR (O-2} .... TYPE
TEST TYPE

I
I

r Now check page pointer found

/';'

by section pointer evaluation.

TRAP
(NO ACCESS}

10-2619C

Figure 1-26 Pointer Interpretation Flow Diagram (Sheet 3 of 5)

EBOXjl-32

C(SBR +
AR<18-35»
--+AR
(SHARED)

r Get SPT Entry from SPT Base

- --I Register (SBR) and bits 18-35
L of the Share Pointer_

AR<9-17>
--+PAGE NO_

I Bits 9-17 become new Page Number
_ -1 and bits 18-35 are used as the
I SPI Index (SPTX) to identify a
L new page table_

•

AR <23-35>
-+PAGE NO_
C(CBR + PAGE NO.)
--+AR

10-2619D

Figure 1-26 Pointer Interpretation Flow Diagram (Sheet 4 of 5)

EBOXj1-33

r
~I

1O·2EV19E

1-26 P""';nter
. VI

Flow

(Sheet 5 of 5)

Core Status Tables
• (Each addressed by page number)
~T2

CST 1

CST 0

-+__

PAGE~~______~~__~~______

CST4

CST 3

________+-____+-______-+____ ________;-__
~

CST 5

______-;

NO.

MICRO.cODE
STATUS

SHARED =
SPTX

STORAGE
ADDRESS

PHYSIO

FORK
OWNERSHIP

NOTE:
CST 1 THROUGH CST 5
ONLY RELEVANT TO
MONITOR SOFTWARE

FETCH
CST
ENTRY

TRAP

AC BLOCK 6
Word 0

TEMPORARY
STATUS

Page is inaccessible.

CST ENTRY
II
CSTMSK

I
I

>___ -lr Set and merge information
I

Lfields about current reference.

AC BLOCK 6
Word 1

R
V
CSTDATA

RV BIT 35

Set modified bit.

STORE
CST
ENTRY

10·2620

Figure 1-27 KL Core Status Tables Updating Flow Diagram

EBOXjl-35

Paging Hardware Support - The paging hardware is transparent to the user. All memory, both virtual
and physical in user and monitor space, is divided into pages.
The virtual address comprises 23 bits, five (5) bits for section numbers, nine (9) bits for virtual page
numbers, and nine (9) low-order bits (line number), which address the location within the page. The
virtual page number is first used as an index into a hardware page table that contains up to 512 direct
virtual-to-physical address translations. If the 13-bit physical address is found in the hardware page
table, a 22-bit physical address is formed by concatenating the 13-bit physical address with the 9-bit
line number. If the entry does not exist in the hardware page taole, a sequence of translations is
initiated to locate a page table in memory that contains a physical address (if one exists) for the virtual
page.
Cached Paging Data - The hardware page table referred to at the beginning of this section is effectively
a cache of paging data (not to be confused with the memory data cache) that has been accumulated by
previously fetching the data from memory, or by previous pointer interpretation. A virtual address is
first checked against the current contents of this hardware pager and, if found, immediately returns a
physical address. If the physical address is not found, the pointer interpretation (Figure 1-26) fetches
information from memory to resolve the virtual address. Upon completion, this translation may be
placed in the hardware page table forming the cache of recently used page addresses.
The hardware page table is loaded b~ the micro~ode. The paging cache is implemented as 512 entries,
one for each page of a user's virtual address space. The EXEC and USER are offset from each other,
but they share the same 512 entries. Therefore, at any given time, the paging cache holds,translation
information about most of the active pages. A guarantee that the 512 most recently used pages will be
addressed by the paging cache cannot be made. However, the last page used will always be in the
paging cache.
When the monitor takes any action that would invalidate information about existing virtual-to-physical address translation, the paging cache must be either partially or completely cleared. Examples of
such instances are:

Change of user process - clear entire paging memory (entire user address space has
changed).

One page removed from core - clear the entire paging memory (several Shared and Indirect
Pointers may have used the page).

Pointer is removed from UPT - clear the entire paging memory (association for many pages
through UPT is changed).
.

Monitor mapped page to EXEC space for local use - only one entry cleared (When page is
unmapped, only that one pointer must be cleared. Because this facility is provided by the
pager, it may be used to reduce reload overhead.)

If the paging data is not found, the flow in Figure 1-26 is followed. A special trap is initiated and the
microcode saves vulnerable EBox data before starting on the pointer tracing algorithm. If the
algorithm is successful, the resolved pointer and associated information are loaded into the paging
memory, the EBox registers are restored, and the memory request is again issued.

The microcode must also handle the first Write Request trap, inhibiting the write until the modified bit
can be set. The pager maintains this modified bit. The microcode implements this as follows.

EBOXjl-36

(--

p&ging !nernory r~~load~

]'iI/KBox

Enlr)Jl!

a write is legal ~Oi"

rrefe.ren(ce is

'l~rroi'S can

aC ceS8 bit

l§ set in. d'H;; pagmg l1?;femory only if the current
Thus, if the first refen;:!1ce: to a page is a
entry sets to O. A. subsequent
reference
the pointer interpretation is repeated! and

<~
to
pag(;!
by the MBm itO the EBox:

ComllWol]s

following five

Parity

2,
4l ,

Parity
l\JOl1.,exxstent
rvlB Parity

~\/iemorJ

upon detecting a

faunt hamHer to

or an

I.l,A.4VIViA CmlltrOJ - Two

styh,,:

addre§~u!s can
KJ~style paging;

pa§,~ed

the VfvIA lines actually

style paging, bits 1
unused and forced to O. In the logi(;al sense,
vie'lved for Kl-styk paging as
of li 8 bits of addressing
medla:ljgl1l. is indkatled
Figl..Ire 1~21t

2 PMi\ IS THE PHYSICAL MEMORY
ADDRESS f1EGISTEfl Ii'J THE MDOX

U" IJSE BITS

(JUAD WORD
(FOUfl 36 BIT WORDS)

Translatwn

Figun: 1-28
EBOXjl-37

to the M:Hm[ for ,.~ore

i'H:Jcoi1d 15

Actually, the virtual address in KIlO paging mode is derived from the instruction Y field, which may
be modified during the effective address calculation. This consists of 18 bits. The additional five bits
(VMA 13-17) are present to facilitate KL paging mode, which can generate a 23-bit virtual address.
However, the MBox does utilize the high-order part of the VMA as indicated in Figure 1-29 to generate a Hashed Page Table address for internal use. The hashing technique is basically an associative
process, but precludes the necessity for hardware associative memory.
PHYSICAL ADDRESS

I
PHYSICAL
ADDRESS
SPACE
IDEALIZED
4096K

256K

I..EVEN..j.. ODD
PAGE
PAGE

.J
I

CORE
PAGE
TABLE
256
WORDS

r
I
~~D~:l~
FUNCTION

rUSER

I.-

EXEC.,

0001077200/277
10011.77300/377
200/2770001077
300/377 100/177
400/477 600/677
500/577 7001777
600/677 400 /477
700/777 500/577
HASH TABLE

PHYSPAG£PHYSPAG

PAGE 777

-J

HARDWARE
PAGE
TABLE
512 WORDS

~4--_---J

27-33

27-

27-35*

27-33

27- 35

"MATCH"

128
DIR 0

r
I ~Kk~CT
18
PHYSICAL
PAGE

VIRTUAL ADDRESS
VIRTUAL

2627

~~LREDCT

Ia
35

WORD WITHIN
PHYSICAL PAGE

*PHYSICALLY. BITS 27-34 SELECT ONE OF FOUR 256 x 2
SELECTS A SINGLE WORD FROM THIS ·LOCATION PAIR.

CACHES.

BIT 35

10-1 !S!S5

Figure 1-29

Virtual Address Mapping, KIlO Paging Mode
EBOX/I-38

The VMA can be loaded from the ADDER or VMA ADDER. Generally, during calculations for the
effective address, it is loaded with the contents of ARX via the ADDER. At this time, ARX contains
an intermediate address [Y + C(XR)].or E:1.2.5 EBus Control and PI Control
The EBus control consists primarily of two major sections. One section is used exclusively for priority
interrupt handling (PI CONTROL) and the second is used for I/O instruction handling ~BUS CQ,NTROL). Each IQJQ.controller (except the DIA20 I/O Bus Adapter) is assigned a devIce code. This
code is seven bits wide (ll\..l;;2.). In addition, each device controller is wired to contain a physical
device number that relates to a preassigned scheme, and is slot dependent. Thus, Massbus controllers
hold physical numbers in the range of 0-7; DTE20 numbers 10-13 8 and D~O number 17 8 • This
provides a physical priority scheme that supplements the programmable priority interrupt system.
In the situation illustrated in Figure 1-30, both DSKs are assigned to the same PI level (levelS). This is
accomplished by the operating system with a CONO PI to the PI system enabling the processor to
accept interrupts on level SC)ln addition, the operating system performs a CONO DSK, assigning the
DSK to levelS. For the situation where both DSKs interrupt simultaneously, the EBox arbitrates the
priority interrupt levels and then physical device numbers are requested from both DSKs. These are
arbitrated according to the fixed scheme discussed previously. The DSK with physical No. 0 has
highest priority in this situation.

MASSBUS
DEVICE :DS K

PI5

f-EBOX

E
B
U
S

PHYS#O

MASS BUS
DEVICE=DS K

PI5
PHYS#1

.......
Figure 1-30 Simultaneous Interrupts
The basic dialogue is shown in Figure 1-31. Once the priority interrupt system has been turned on and
set up by the operating system to handle interrupts, the EBox control automatically carries out all
dialogues necessary to obtain the API function wor.5!... When the API function is on the EBus and
transfer is received from the device, the EHUS control asserts PI READY, signaling the microprocessor
to take over. The microprocessor looks at this line, however, only at specific times during normal
instructions. One such instance is at NICOND Dispatch, which always occurs at the beginning of each
instruction. If at NICOND'time, the PI ROY condition is true (INT REQUEST sets), the PI HANDLER is called. To prevent further interruptions until the function can begin, the microprocessor sets
the PI CYCLE flag. This causes the EBus Control to defer any further PI READYs. The PI HANDLER evaluates the API function word (Figure 1-32) and performs the indicated service. As long as PI
CYCLE is on, other interrupts are not honored by the micro~ssor. The time that PI CYCLE is
cleared is dependent upon the service performed. If the interrupt IS a standard interrupt to 40 + 2n, the
instruction in 40 + 2n should save the hardware state of the EBox, Le., the flags, PC word. Appropriate instructions are JSR and MUUO. Bad choices are JSP and PUSHJ, which use ACs. The choice is
particularly bad because at the time of the interrupt nothing is krlown about their contents.

EBOX/I-39

INCOMING PI REO'S

•
•
•
INCOMING PI REO'S
"SELECT HIGHEST PRIORITY LEVEL"
FUNCT PI SERVED
MAIN
MICRO
PROGRAMS

CONTROLLER SELECT
4-6 =PI REOUEST TO BE HONORED

MICRO PROGRAM
LOOKS

DLY
L-______________~D~E~M~A~N~D~__________~~

,-________________________-;U
RECEIVE PHYS #
PI ROY' INT REO

•
•
•
PI ADR IN
CONTROLLER SELECT
0-3 = PHY PHYS # SEL
4-6 =PI CH TO BE HONORED

DLY
DEMAND
EBUS TRANSFER
API FUNCTION WORD IS NOW
ON EBUS SEE FIGURE 1-25

•

Figure 1-31

10-1567

PI Dialogue Overview

1\
/

(

EBOXjl-40

05 06 07

0203

ADDRESS
SPACE

I FUNCTION~.I I
0

10 II

PHYSICAL
CONTROLLER

12 13

VI RTUAL ADDRESS

ASSJRTED
BY PI SYSTEM

FUNCTION
(AS SPECIFIED BELOW)

ADDRESS SPACE
(AS SPECIFIED BELOW)
ADR. CODE
CODE

0
I

2.3.5-7

FUNCTION
COOE

DEFINITION
EPT
EXEC VIRTUAL
PHYSICAL
UNDEFINED

a
I

2
3
4

5
6
7

QUALIFIER
(AS SPECIFIED BELOW)
OBIT
INTERPRETATION

FUNCTION
CODE

OEFINITION
STANDARD INTERRUPT
STANDARD INTERRUPT
VECTOR INTERRUPT
INCREMENT
DATAO IEXAMINE)
DATAl IDEPOSITI
BYTE TRANSFER
RESERVED FOR DEC

0,1,2,7

IGNORED

O=AOD+ 1

I = SUBTRACT + ,
4,5

(

, = APPL Y PROTECTION

AND RELOCATION
6

, = TO'O BYTE TRANSFER

a = TO"

BYTE .TRANSFER

* THESE

BITS ARE MICRO CODE-DEPENDENT. CHECK THE
LATEST MICRO CODE LISTING FOR POSSIBLE CHANGES.

Figure 1-32 API Word Format
Generally, a JSR instruction is placed in 40 + 2n for calls to the operating system PI HANDLER. This
instruction causes PI CYCLE to clear. At this time, a pending interrupt may request microprocessor
attention and can raise PI READY. In general, for the other cases, the equivalent of one instruction is
provided before PI CYCLE is cleared.

(

I/O Instruction Dialogue Overview - For I/O instruction transfers, the basic concept is illustrated in
Figure 1-33. The EBus Driver is called from the I/O HANDLER to generate the appropriate EBus
dialogue. First, the EBus is requested. This is necessary because the EBus is also used by the PI system.
If the EBus is free, the EBus driver sets a CP GRANT flag to hold control of the EBus; if the EBus is in
use, the EBox waits.
GEN DIALOGUE

GET EBUS

(

FUNCTION DATAO.
DATAl CONO. CONI
BLKO. BLKI

CSOO-OG. FCN 0-

SERIES OF
MICRO
INSTRS
PREFORMED
TO CARR'!'
OUT
DIALOGUE

WAIT

HOLD

ASSERT DEMAND

EBUS
CONTROL

CONTROLLER
SELECT=
IR 03-09

WAIT AN 0 HOLD
RELEASE EBUS

DEMAND

",TRANSFER

DATA/STATUS OR CONTROL
TO/FROM DEVICE EBOX
NOTE:
The XLATOR provides level shifting
between the ECL side of EBUS and the TTL side.

"MICRO ROUTINES"
10 - 1569

Figure 1-33

I/O Instruction Dialogue Overview
EBOX/I-41

SasicRHy, a
hElving the
C01'.TD JEHUS
and the appropri.ate
number
field} Specific; ;~""H"'rl,
the number fidd 'with EBUS C1'1, true I,~au§e
diaLJ,gue. ER
3··9 are
fUl1ction to be
the

Datu JP'ath
Ref1erring to
R~e,gist.ef

M\JltipHer
Fast l\1:emory
Adder
A.dicier
included is fast

ARX,or
.,,,A;t,U,\J.'!',!}'Ib:tI!,,,,,,,.,"!;M~~~!;;, in the

that can imlpl<&::ment

and a 36-blt shift

:Gombined AR and ,,~JitX. The
is used to handle

hand.ling

tionsG
Double-precision floating-point and
and
where ADX is a 36-bit extension

pn,:dsion integer operations requine use of
the main AD and ARX is a 36-bit

AR,
BRX, together with
and
with IViQ, a lOS-bit path where
In addition, A,RX is
memory. The main
lo;t~'d

buffer,

words coming

ill1lformllltiol11! F~mli Til]; alI1lti! }i'mID

as a buffer
or going to eon:; or fast

Referring to Figure
informatiol1 into
via the MBox. Because of the structtJre
uU" •
v'Im
a

those paths that are used in
.,J'",

EBOXjl-42

HH,'Aucn

FORCE 1777
DRAM J (II)

STACK
4 x 11

1 + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ' - - - - - - - - - - - - - - - - - - - - , (11)

CONTROL
RAM
1280 x 75

(11)

DIAGNOSTIC REGISTER
EBUS (11)

~--------------------------~----_..-... TO REGISTER SELECTS (EDP, VMA,SCD,CRM,IR,CRA,CTL)

TO FAST MEMORY SELECTS (APR)

TO CONTROL LOGIC (CON,CTL,MCL,CLK)

SCAD

AD
(36

DRAM A
DRAM B
DRAM J

(3)
(3)
(11)

AR EXP

SH
~--~-r--~

3-AR

AR POS

*
AR
SIZE

O-SHIFT AR, ARX
{ 1-AR X
2-AR SWAP
DISPATCH
RAM
512 x 18
(LOGICAL
STRUCTURE)

AR" ARO-8

CONTROL RAM FCN

FM BLOCK 4,2,1

FM ADR 10,4,2,1

IR AC
9-12

FAST MEMORY ADDRESS
(3)

EBUS (6)
(DIAGNOSTIC
FUNCTION)

AC+ 1
AC+ 2

VMA 32-35

ADDER

AC+3
CURRENT
BLK

PREV
BLK

AC+#

AD
(13)
SH

ADX

CACHE DATA (36)
BR
NOTE:

This symbol means
Level Mixer.

2}mmu,,,
INPUTS

SCAD TO
P FIELD

SCAD
TO
EXP

EBUS
ARX
BRX
(DIAGNOSTIC MIXER)
10-2182

/
Figure 1-34 KLlO Register
Interconnection Diagram

EBOXjl-43

LEGE~JD

-t;r·9:;:i--1>-'I>-/.";;r.-'';·'--.E>-f.>

I\'OTES:
Ili'ISTR 'FROM

-~-'~-['P>-{/[tto-~-"~~-~'""t~ INSTR FRC>ivl FM ~~
---!>~l>--l>-i>

¢.:...

(INDEX REGISTER

--l>---l>---i>---I>

INDEXED .IIDDflESS

-"-['-'-li>- -\l>- -UJ>

Y FiELD OF CURRE!H

~-··-t,.__

Parity logic is not

indi~ded

on this drawing.

WORD FROM FM

INSTRlJCTIO~J

10-2'1133

Figure

Core

Fast

~~1\~mory

EBOX/l~44

Information Flow

Table 1-3 Memory Information Flow

Source

Destination

Comments

Type of
Request

Type of
Information

Read

Instruction

Core Memory
or
Fast Memory

ARX

Loaded via cache data lines if from core memory or via the AD if from fast m~ry .

Read

Data

Core Memory
or
Fast Memory

AR,ARX,
or both

Loaded via cache data lines if from core memory or via AD if from fast memory.

Write

Data

Core Memory
or
Fast Memory

Read

Indirect
Word

Core Memory
or
Fast Memory

ARX

Loaded via cache data lines if from core memory or via AD if from fast memory.

Read

Index
Register

Fast Memory

AR, VMA

The contents of the addressed Index register is
read into the ADDER "B" input where it is
added to the current value of Y. The sum is
loaded into both AR and VMA under microcode control.

AR goes to the FM and to the cache,
regardless of which reads it.

The microinstruction contains a number of separate fields for register selection including a 3-bit AR
field and a 3-bit ARX field. In addition, three fields are provided for controlling the adder; two of
these, the ADA (3-bit field) and ADB (2-bit field), select various inputs to the adder. The third field,
AD (a 6-bit field), controls the adder directly. The actual selection of the source or destination registers
depends on the following:
1.
2.

•

The ,microinstruction register select field function
The source or destination memory (e.g., fast memory or core memory) .

As an example, consider an instruction fetch (not a prefetch) from fast memory. Refer to Figure 1-36.
The MEM field function of the microinstruction desiring the word is coded as FETCH. From this, the
term MCL LOAD ARX is-produced and routed to EBox Control No.1, where it partially enables the
ARX SELect 1 and ARX SELect 2 Mixer Selection logic. The final selection is a function of the
address contained in VMA. If this address is a fast memory address (e.g., VMA 13-31 = 0), then the
ARX SELect 2 line is fully enabled and the ARX SELect 1 line is inhibited by VMA AC REF.
Similarly, if the address in VMA is a core memory address, VMA AC REF will be false, inhibiting the
ARX SELect 2 line and enabling the ARX SELect 1 line.

EBOXjl-45

indicatt:d in
these eight inputs,

atied 01!X!elf are very i'ii.milar to
memory, tlH~ MEIVI field fmlc/don, LOA,D
,;:ontrol,
!enabling the
(lfthe
Zif,ro,
a(kJer is
into th~ ,AR nmnber 2 Input,
nonZ!;;fO, the cach\;;: data Hm:s an~ ,enabled into tltH~ AJ:l number :2 input. As with }l\"RX,
instJi'w;:;tion
any of th;e dght hlPUtS em thle AR mixer! if required.
version
loath::;. The basic
COflJ1iecitnons and the direction
tranflf\~rs an~
I~Jong the
the::'
is
portion
word format
data path. The
not
~/o !'lm~l!

lPrllof1ty ll.nternllpt

Figure

"u,"''''',''' ",,',1' operatiomL The major path is

de'llic,t';s, and
and control
pathsi?mOlregisters. EU'\~

inttrnal EeL

EBU1L

but
interrupt
has

u[!H::d

lis a simplified path diagram

area, including the

i::; cross-hatched
the SH, SC, SCAD) F1R, and
ae working
usage dep{;;nds

CHi,

information
data) is not translated, but
Externall device information,
entering or k:aving the
TTL to
or EeL hli TTL. If
operation being p:erfornH~d is a CONI ()f
the
is C01\TO or DATAO, the
thf: /~j,Pli
word
may involve an instruction
;a
The Inicmprogram begins to process the
transmitted! from device and the EEus

r use later and performs a SHIFT
i
microprogram" To
output bits (SH OO~03) 2lre
another type M",'~"""'H r.~an performed; this is

The microprogram places a copy of this
on
A.PI function code to the appropriate
the i'dl.', Is .
the
matrix; Hu:n

Address

a standard int©rmpt (API FeN 0 or l)an instruction is ""I,.'""UV'.'
where n is
to du~ intlerruJPtillg"chlumd 1"",7,
locations generaHy
a
that must be performed! in order to
and PC of
intecffupted
In addition, the current ACs fiiu§t not be
must be entered
(40 +
to

FETCH.

qualifier, lEBox EFT,

1~46

"--'

""'\

)
•t

REQUEST QUALIFIERS

__
MC.!:J
~ CRAM ARX SEL4

MCL
LOAD
ARX

fDATA~----

w
u

CACHE DATA

IEsOx--'

I
I
I
I
I

L _ __ ~Or:!.J
~----~--+14.

tT1

::;;

t::J:j

--><

rcLOci(-'

ARX SEll

I-

CRAM ARXM SEL 1

_________

-,
I

I ~E~S~ I

~.J

Z
H

ICONTROL

1#2

CRAM ARXM SEL2
ARX SEL2

MBOX RESP

/------0_-11

- - -

I
I
I
I

-..J

~----.JI
L __

EBOX REQUEST

~K..I

FM
DATA

r---,
VIRTUAL ADDRESS

r - [ =r

j-ARiTHMETiCl

PROCESSOR I
I
STATUS
I
IL _______
i= =i' A~I

VMA AC REF

I 13!~r=v~
IVIRTUAL
MEMORY
IADDRESS

L... _ _ _ VM.!J

)
Figure 1-36 Loading ARX

I
I
I
II
10- 2184

PROC SERIAL '"

10 BIT LOGIC

~ MAIN DATA TRANSFER REGISTER
PATHS SHOWN IN FIG 1-4

BIT
LOGIC

"'-

/
/

\
\
"I.

1---

- - - - - - - - - - - - - - - MICRO INSTRUCT ION DATA PATH C O N T R O L - - - - - - -- -- - - -_ _
10-1548

Figure 1-37

EBox Data Paths Simplified

P~ths

Diagram

::::3- When

the API function specifies a dispatch (API FCN 2), the virtual address of an interrupt instruction (JSR) is provided by the device. In this situation, the request does not assert the qualifier EBox
EPT because the address is not an EPT address, but rather somewhere in the virtual address space. For
the situations described up to this time, the instruction will enter ARX. Control is passed to the main
microcode loop for processing. The API function (PI increment or PI decrement) is slightly different,
in that a word must be fetched from the virtual address provided by the device. This word is then
incremented or decremented as specified in the API word and the result is written back into memory.
Here the AR is used both for the
, read and write operations.

; 'PiPI functionsiandj require a DATAO and a DATAl, respectively, to be performed to the device.
Prior to performing the specified DATAO, a word is fetched from the virtual address provided in the
API word and this word is loaded into AR. The path is now from AR to AD and then to the EBus,
which is controlled for the DATAO by the microcode. For the specified DATAl, the operation is the
reverse. The required word is obtained from the device via the EBus under microcode control (EBus
dialogue) and the word is loaded into AR. Next, the contents of AR must be written into the virtual
address supplied by the API word. Of the remaining functions, only API FCN6 is used and this is
reserved for the DTE20 (10-11 Interface). Examines and deposits, as well as byte transfers, may be
requested by the DTE. This subject is covered in Section 2.
EBOXjl-48

r - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - l ··
INSPECTION AND CONTROL
.
I

•

CONTROL RAM
ADDRESS
CONTROL

FROM {
CONTROL
REGISTER

I
I
#
I
r-----------J

AR 0-3 DISP

SH DISP

' - ---i> - ---i>- ---i>- ---i>-- --i> - - --i>-- --i> ----i>

'I'
I
I

L ______ _

'I'

--i> - - --i> - - --i> - ....

.... --

.... -- .... -- .... -- ....

.... -- .... -- ....

-- .... --

- -.... -- .... --+<

••1111111--4---4--4----+---+---+INTERNAL
DEVICES

CACHE DATA

LEGEND:

III

MAJOR PATH

INSPECTION AND CONTROL PATH

----i>

INCOMING DATA FLOW

---+

OUTGOING DATA FLOW
10-2185

Figure 1-38

Input/Output Priority

Interrupt Information Flow.

EBOX/I-49

SECTION 2
FUNCTIONAL DESCRIPTION

2.1 INTRODUCTION
Figure 2-1 illustrates the major functional elements of the EBox. The purpose of this drawing is to
support the functional descriptions contained in this section. The major data and address paths and
the individual controls introduced in the previous section are shown on this diagram with some additional detail. Major interfaces are also shown in some detail.
The interface between the EBox and the MBox is not a bus, but is functionally shown and described as
if it were, because its operation is similar to that of a bus.

As described in Section 1, the EBox serves as the Instruction Execution Unit for the KLlO system.
Access to main memory is logically controlled by the MBox; therefore, as the EBox requires memory
operands or instructions, it performs MBox cycles to obtain these words. These cycles take place over
the E/M interface. In a similar fashion, access to I/O devices is via the EBus. Devices may communicate with the EBox over the EBus by utilizing the priority interrupt system. In addition, as the EBox
requires status or data from devices connected to the EBus or wishes to transmit data or control
information to devices on the EBus, it does so by performing EBus cycles. These cycles take place over
the EBus. Figure 2-2 illustrates these primary hardware cycles. The implementation of MBox or EBus
cycles is via the microprograms stored in the CRAM.

)

2.2 MICROPROGRAM STATES AND PROCESSOR CYCLES
Referring to Figure 2-3, the EBox microprogram can be in one of the following states at any time:
Microprogram Running
Microprogram Wait State
Microprogram Halt Loop

(

Microprogram and EBox Frozen
Microprogram Deferred
EBox Reset (Power Up Sequence)

A discussion describing how to read and understand the microcode is provided in Appendix A.
2.2.1 EBox Reset
During the power up sequence, the EBox, MBox, and all controllers are reset to known states. The
EBox, MBox, EBus, and SBus clocks are initialized and the CRAM register is cleared. This clearing
action places the EBox in the diagnostic state, because the dispatch field is equal to zero
(DISP/DIAG). A program running in PDP-II memory then initializes the EBox, loads the Dispatch
RAM andVer'iries it, loads the CRAM and verifies it, and starts the microBrogram into the Halt loop.
In general, at this time, the system must be bootstrapped; to accomplish this, a number of diagnostic
functions are necessary. This is discussed in Section 3 and in the system and interface descriptions.

EBOX/2-1

ONE EBOX CYCLE
FOR EACH MICRO INSTR.

c
CONSISTS OF (USUALLY)
TWO EBOX CYCLES.
THE FIRST IS FOR ISSUING
THE REQUEST AND THE
SECOND IS USED TO LOAD
THE VMA. IN PRACTICE
THERE ARE FAST AND
SLOW MBOX CYCLES.

CONSISTS OF A NUMBER
OF EBOX CYCLES USED
TO CONDUCT THE E BUS
DIALOGUE FOR: PI
HANDLING OR 1/0
INSTRUCTION EXECUTION

10-1580

Figure 2-2

Primary Hardware Cycles

EBOXj2-3

REQS

DEVICE ACTION
[ EXTERNAL OR
INTERNAL ACTION

EXTERNAL ACTIONJ
REQUIRED VIA
10-11 INTERFACE

I
I

(

DIAG START
OF MICRO PROG

*MAY
__

{

EXTERNAL
]
ACTION REQUIRED
VIA 10-11
INTERFACE (DTE)

BE SAME STATE

WAIT STATE - MBOX WAIT
MBOX WAIT - MEM 02 (1)
AND MEM CYC (1)

"POWER UP"
[CRO BAR]

(

NOTE:
The notation used here is similar to that used
with "PITRI NETWORKS:'The meaning of the
notation, "SJGNAL/n~is as follows. The mnemonic
to the left of the/is a condition which must be in the
state indicated to the right of thel, E.G. 1 or a in order
to pass from one bubble to another.
10-158 I

Figure 2-3

Microprogram Static States

2.2.2 Microprogram Halt Loop
The Halt loop is entered following a NICOND Dispatch, when RUN and PI CYCLE are found clear.
Figure 2-4 is the flow diagram. Referring to Figure 2-5, the EBox contains a synchronizer (CON
ST AR T), which is set for three clock periods when CONTINUE is pressed. In addition, it also contains a flag (CON INSTR GO), which is set by CONTINUE and remains set until a HALT instruction
is performed. The RUN flag in the EBox consists of a RUN source enabled by DIAG SET RUN and
CON INSTR GO true. Referring to Figure 2-4, assuming a HALT instruction has just been performed
(JRST 4) and the RUN flag has been found clear at NICOND Dispatch time, the Halt loop is entered.
The following occur immediately:
The
The
The
The

AR is cleared.
HALT flag is set.
current value of PC is loaded into VMA.
current value of VMA is placed in PC.

EBOXj2-4

HALT
LOOP

CLEARAR
SET HALT FLAG
FOR PDP·" TO
SEE. VMA<-PC.
PC <- PREVIOUS
VMA

YES
NO
"XCT
INSTR"

ENABLE START
FLAG, VMA<-PC
SPEC INSTR/CONT

EXECUTE
CONTENTS
OFAR
"PC IS NOT
UPDATED"

MAKE MBOX
CYCLE TO
FErCHINSTR

THE ONLY PI
FUNCTIONS
ALLOWED
HERE ARE
FUNC 3,4
OR 5.
THIS IS A
HARDWARE
RESTRICTION

AR <-INST
, -_ _......_ _ _.... ARX <- AR
"PERFORM
THE INSTR"

CLEAR STATE
REGISTER AND
DO NICOND

RELEASE
EEBUS

NO
"SINGLE
I NSTR
MODE"

•

ENTRY VIA:
JRST 4,
2. NICOND WITH RUN(O)

I ,.

'CON INT REQ
IS INHIBITED
FOR INSTRUCTION

PROCEED
FROM
NICOND
DISPATCH

"THE AR MAY ALSO BE
LOADED WITH THE
DIAGNOSTIC FUNCTION.
10·1582

Figure 2-4

Microprogram Halt Loop

EBOXj2-5

Thus, if the HALT instruction was fetched from location 600, and the effective address supplied in the
HALT instruction was 100, PC would become 100 and VMA would become 601 (the updated PC
value). The START flag is tested to determirre if CONTINUE was pressed. In this case, START will
be clear. If an interrupt is pending, the 'PI Handler is entered to service this interrupt.
When this is done the next instruction is requested. This is followed by a NOOP microinstruction.
Finally, the State register (a hardware register in the EBox) is initialized clear. Then NICOND Dispatch is issued and the Halt loop is entered again.
If no interrupts are pending, the "Tight loop" is entered, continually checking the START flag and

interrupt requests. Note that HALT INSTR does not clear the RUN source, but merely clears INSTR
GO, which removes the CON RUN signal (Figure 2-5).

LEGAL TO HALT

CON INSTR GO
CON RUN

DIAG CONTINUE
CON CLK

DIAG RUN SET
DIAG RUN CLR

SET
RUN
SOURCE
CLR

CON CLK

"CONSISTS OF A :3
TICK SYNCHRONIZER"

NOTE:
LEGAL TO HALT is 0. generic term o.nd o.lso 0. simplifico.tlOn
of the o.ctuo.l 10giC,[(KERNAL MODE V USER IOT)I\(JRST 4,)J

Figure 2-5

10-1583

Run-Halt-Continue Logic

The HALT instruction is a "privileged instruction"; therefore, the EBox must be in either diagnostic,
USER lOT, or KERNEL mode to clear CON INSTR GO. The PDP-II may clear the RUN source at
any time by issuing (via the 10-11 Interface) DIAG RUN CLR. This causes the Tight loop to be
entered at the next NICOND Dispatch (assuming no interrupts are pending).
If it is desired to execute a single instruction, the AR may be loaded with the desired instruction by use

•

of the prescribed'DIAG function, issued via the 10-11 Interface. After the AR has been loaded, the
STAR T flag is enabled by issuing DIAG CONTINUE. The AR is tested for a nonzero value. If it is
nonzero, the contents of AR are executed; upon its completion, the Halt loop is once again entered.

---

It should be noted that PC+J INHIBIT is true during the Execute function, to prevent the PC from

being updated. Similarly, by clearing AR and pressing CONTINUE while CON RUN is disabled, one
instruction may be fetched at a time and executed, or the program may be resumed if CON RUN is
true after performing the instruction in AR. For this function, the microcode, at XCTW, is used to
fetch the instruction and wait for it. This instruction is performed, and the PC is allowed to be updated
by + 1. At the end of the instruction, NICOND Dispatch is issued and the state of CON RUN is tested
together with other hardware conditions, to determine what to do next.

EBOXj2-6

2.2.3 Microprogram Running
Once the microprogram is running, it may enter any of the other states (Subsection 2.2). Normally, the
microprogram passes through a regularly~tlefined sequence consisting of at least the five main dispatches (Main loop) shown in Figure 2-6. Between each dispatch, some number of microinstructions is
performed. A rough equivalence exists between the traditional computer machine cycles and those of
the EBox. In general, the relationship is as shown in Table 2-1.

Table 2-1

EBox Main Loop/Traditional Machine Cycle Comparison

EBox Dispatch Main Loop

Traditional Machine Cycles

NICOND Dispatch
' - EAMOD Dispatch
::::---. A READ Dispatch
~ DRAM J (See Note)
B WRITE Dispatch

Instruction
Address
Fetch
Execute
Store

NOTE
This dispatch is referred to in the Microcode as IR Dispatch.

10-1584

Figure 2-6

Dispatch Path State Diagram

EBOX/2-7

Altogether, there are 16 dispatches. The five basic dispatches constitute the main loop; an additional
eleven are, in general, instruction dependent and usually, if issued, follow an IR Dispatch (DRAM J
DISP). Each time an EBox clock tick OCl;urs, 'he CRAM register is loaded with a microinstruction.
This microinstruction then contoIs formation of the next microinstruction address. This is accomplished by the particular coding of the appropriate microinstruction fields. In general, there are four
types of CRAM address modifications (Figure 2-7):
Branch On Condition
Branch On Condition With Skip
Skip
Jump
The CRAM address logic samples conditions (Figure 2-8) supplied by various portions of EBox logic,
together with the current microinstruction J, COND, and Dispatch fields, and then generates the next
CRAM address (CR ADR 00-10).
2.2.4 Microprogram Wait State
As indicated in Figure 2-3, the Wait state (MBOX WAIT) occurs during memory requests involving
the M Box. In general (Figure 2-9), three main uses of the Wait state exist. The first is to assure that the
microprogram waits for an MBox response after having started an MBox cycle. The second use is to
hold off a second MBox cycle when the MBox has not yet responded to the first MBox cycle.
As shown in Figure 2-10, the EBox clock control samples the following signals:
MBOX WAIT
VMA AC REF
RESP MBOX
If an MBox cycle is started, MEM CYCLE sets, as enabled by the request. It remains set until XFER is
generated. When the request is to the MBox, and VMA 13-33 is nonzero, the XFER is generated as a
direct result of MBOX RESPONSE IN. If, however, VMA 13-33 is zero, VMA 32-35 is a fast memory
address and the EBox aborts the cycle. The XFER is a result of FM XFER, a signal generated from
within the EBox itself. If VMA AC REF is true, the EBox clock ignores MBOX WAIT. However,
when VMA AC REF is false and MBOX WAIT is true, the EBox clock may be inhibited.

The third case involves instruction prefetches from fast memory (Figure 2-11). For this situation, the
microinstruction generating NICOND Dispatch also asserts MB WAIT. This is necessary because the
EBox hardware requested the next instruction from the MBox rather than from fast memory. The
MBox detects that the VMA address contained a fast memory address and aborts the cycle. The EBox
hardware switches- the ARX input to the AD output, thus reading from fast memory.
NOTE

XFER

= MB XFER V FM XFER

2.2.5 Microprogram and EBox Frozen
The microprogram and EBox frozen state occur in practice when any of the following events occur:
1.

D RAM Parity Error while the EBox clock is running.

CRAM Parity Error while the EBox clock is running.

Fast Memory Parity Error while the EBox clock is running.

EBOXj2-8

('
"

/
i
!

LSB IS

":>eJN T F: 0 Lt. E IJ
BV THE S~UP

i D-15S5

36 BIT
DATA
PATH

IRAC

BIT
LOGIC
SCD

SH
DP

CLK
FORCE 1777

CONTROL
CLKI-----i
CTL
CON

CR ADR 00-10

CONTROL RAM
ADDRESS

MEM
CTL
MCL

71
DISP

CRAM
REG
10-1586

Figure 2-8

CRAM Address Inputs Simplified

DRAM A=4-7; SOME
FORMAT READ DATA
E.G. READ, READ PRE
FETCH, READ PSE
WRITE, READ-WRITE
DRAM A= 3; WRITE
PAGE CHK

THIS MICRO INSTRUCTION HAS MEM=MB
WAIT

EBOX CLOCK IS
INHIBITED UNTIL
RESPONSE IS
RECEIVED FROM
THE BOX

•

NOTE:
MEM=MB WAIT implies that the micro
instruction mem field contains a code of

,
10-1587

Figure 2-9

Wait State

EBOXj2-1O

r---,
I

'" - - -

I MBOX CONTRO Lr-_ _ _

.,'

_~_

I-t--.:C:.:l::.:Kc..;C::;.R::.:M'-+_!'_-_-_-_-_-_M_I_C_RO_IN_S_T_R_U_C_T_IO_N.:-_-_-_-_-

I
I

I
IL _______ ...JI

ClK CRM

MBOX
WAIT

E
/
M

RESP MBOX

VMA AC REF

•
•
•

EBOX
CLOCK
CONTROL

T
E

ClKS TO OTHER
EBOX BOARDS

EBOX ClK

R
F
A
C

E
ENABLED BY CYCLE REQ
DISABLED BY XFER

MBOX RESP IN

XFER=FM XFER OR
MB XFER

VMA

10-1588

Figure 2-10

MBox Wait and EBox Clock

DRAM A=5
READ PRE FETCH
ASSUME PRE FETCH
IS FROM FAST
MEMORY

•
NOTE:
REQ/1 implies that the request sets up but
VMA remains latched from the previous REQ
until MBOX response, At th~t time RESP/lATCH
REQ implies that the VMA can lATCH for
the 2nd REQ,

Same EBOX CLOCK
**MICROprogram must reinitiate the FETCH later (NICOND)
10-1589

Figure 2-11. MBox Wait on Prefetch from Fast Memory
EBOXj2-11

prior to

Associated
each
rence
the error to

OC(;Uf-

Function

Enable

eLK iFM f' AR CI-:1ECK

eLK CRAM PAR GIECK
eLK DRA,Jv1 PAR CHECK

mAG FUl'IC 046
mAG FlJNC 046
DIAG FIJNC 046

each il1StnH~tilm,
or dropped an eVI;';fl.
changed the
up to the point. vl"here it U""I"'------..- .

-~->-.--~--.

---,-,--~.-

Conditi.oHG ~:() Consider
Vlhe~'~

Why

hi, Go

Second pzrt
PICydtf':

BASI-':ADR

Halt Instnlc-ijon or

JJ.t\.SE ADP:-l-:2

1; c2used

MTRINT

BASE

ADR+":~

Request
PI Request bu t
not J.,-ITR

Instru.::t1on

BASEADR+6

RUN

MTR

INT

INT
REQ

REQ

REF

Low-C)~oder

TRAP

ra,,}

ANY

i/}< . '.· ·

',-I

eRA,pil /\.DR

NlCOND
fJ7

:~:nts

INlCOND
ng

as FoHo'ps
NICOND
(;9

NICOND

liD

r?;};i~~ »(' 1./ !,,~~Ir/L/':;"<"" />;/'.
;~~;i~ l/~>~/ l~~/( l}l;//~/;/ ,>(/
r~;:;0:~1/<'/I./~'/;/ /.,:'/( /~,/(/
[~~~}:; l~/( /~/r/' ..,~/(/'"
IJ

NlCOND
TRill?

ADR+J.2

BAS:S A.DR+13

(}

>--.~.-~

{]

from menvxy
tr<:lPS p~nding

Instrucrion
from memory :JSJ.d

a trap is pending

Instruction
b., fetched

PM and
pending
Instm_ction must
be fetched from
FM and a trap

BASE i\DP.+ 17

~~~1;~~;
~;;;,'~:

~ji:'~

?~f~i
:~~~~ ~
1

is pending
Overriding condition

10-1590

Figure

EBOX/2~13

~~
~!~
?~?i ~~

in LI·D

+ 2n is performed

DO"NE
[BUEll

Dismiss

such

nature

interrupt
instruction :should be

at l'.JICOl'U)

Dispatch
di§patch is
the appropriate 41

Th,~ PI HarH:H,er generat,~§
instruction
be perfornv:xl, one\,:: again omitting a NICOND Disp,Bilch,
hr.; one
the foHcnving:

address and caUSCll/

111lsltruction fetched mu§(

use

cause PI CYCLE to
2,2.7

rt;Ikropmgnulll Org!;Umiz3.dolTl!
basic control program modules are illustrated
illustrated
2-13 j"'·,·",,·p·opn
'u',",,,,,,,',,,, indud,e

V'b,"""""',",,,,,

1'<"'1,",,"'1'"0,''·1"'''''

functional areas
the lIIicrocode.
bnmching to e8.ch
handiers

intefface (Figure 2~
. Th,;: nature; the

evaluates initial
could be a pending priority
aU
must pass through
process. The nmem.onic for
process is DISP /NIOOND (Next
Condition).

Manager (Figure 2,,15)

indin;:ct ad.dress flag
13, index field
and
hardware conditioD.§ such as
aURA"""'" or calculat,es the

contains the cunreui

cyclt;s.

DATA
STORAGE
MANAGER

EBUS
DRIVER

FINPU~

\. OUTPUT

~________~)~~j~ct.~#MiliWilij~f______-+~__-.________{r:~~~:t:;,"

L{:

\HANDLER

HALT

EXECUTOR

HAN~~)--------;~

J--l--r---l--/'P;'A~G;;;E~F;A~U:;:LT;:\
I

"NICOND" DISP
DATA
FETCH
MANAGER

HANDLER

A,B

rn~777
700

._677
DISPATCH-TABLE===

--(~

000
,-,

IR INSTRUCTION
REGISTER

CBEG IN)

",6 "

EAMOD
DISP

89
OP

EFFECTIVE
ADDRESS
MANAGER

ARXI

TRAP
HANDLER

"CONDS"

'(~I~~~~"
START UP
AN D STOP
INTERFACE

4---

"CONDS"

"Ill, ARX
LOADING"

(NT¢gNJt

VARIOUS
HARDWARE
CONDI TIONS

'Pl$F>'}}}}

Major dispatches -see figure 2-6

Figure 2-13

LL...__---...--__...J.J

M Program Modules

(

EBOXj2-15

10-1538

CONTROL
RAM

1
2
3

PRI
ENCODER 4
5
6
7

PI CYCLE
-RUN
MTR INT REO
INT REO
AC REF
PI CYCLE

Figure 2-14 Startup and Stop Interface

CONTROL
RAM

•

iO-1540

Figure 2-15

Effective Address Manager

The Data Fetch Manager (Figure 2-16) evaluates the 3-bit A (FETCH) field (for the current instruction), which is in the Dispatch Table. The code in the 3-bit field defines the type of data fetch or write
or combination operation (if any) required. The Data Fetch Manager takes the proper action, i.e.,
enabling the EBox clock to stop as appropriate, dispatching directly to the executor, or initiating an
instruction prefetch. Note the Instruction register is used to address the proper location in the Dispatch Table (DRAM) based upon the op code for the instruction.
EBOXj2-16

CONTROL
RAM

DISPATCH RAM
10-1541

Figure 2-16 Data Fetch Manager

The Dispatch Table (Figure 2-17) consists of four fields:

•

DRAM A - Bits 0-2; defines the type of operand fetch cycle.

DRAM B - Bits 3-5; defines Jump, Skip, and Compare conditions for certain instructions,
or result store mode, etc.

DRAM P - Bit 11; parity bit (parity is normally odd).

DRAM J - Bits 14-13; jump address. This is the entry address of the executor routine. The
mnemonic for the dispatch to the executor is IR DISP (DRAM J) (Instruction Register
Dispatch).

r
bi-

012.345
777 A A A B B B

~~14
2.3
~

•
•
•

000

Figure 2-17

Dispatch Table Fields

EBOXj2-17

The
rOl.ltln.e (Figure
is
autonomom:, routines used to execute the
(me
to
or pl1§h a
onto

mic;wprogram.. It contains a tmrnber
3,pe;cific functions, e,g., 1110'111;; a halJ-vv'ord frOll.l
§ubroutim;

'""'""F,."~'&H.",

on the DR,AJ1/K B
additiol1,when
from
it
the appropriate MBox ccmtwl sig··
'"',lUI''',"'''' the
operation. When the Dam
l'vlanager is entered in the
controTI generally paSI'M;:S to
Execut:Of. Finany" a
aDd 'b::ontrol passes to the Startup
tei or from
while

ctiscn:~te

the

is pass1ed to
Fault
(Figure 2~20) routine from the Effective
Ivianager
or Dam Store IVlanager
the l'lflBIJX a;!;sert§
HOLD prior to an rV!Box response
The implication is that a
address violaHon
violation, or shnHar
In addition,
EBOX HA11'IDLE may be assertt~d to the EBox
that the paging
translation shouid be
via mkroprogrum
The Page
is
usred for
,error conditions"

CONTROL
R,\M

DETECT
8iTS

14-23

IF: lOt,

r-.--",,~ ,JR'ST lOR

N(}RMAL '

D~Sp/.rrCH

Rl}.M

IROO.'i2i
W-1543

ExecutDr

CONTROL
RAM

10-1544

Figure 2-19

Data Store Manager

CONTROL
RAM

LOCATION 1777

FORCE ADR
TO 1777

MICRO INSTR FORCED
BY HARDWARE

•

MBOX
CONTROL
10-1545

Figure 2-20

Page Fault Handler

EBOX/2-19

The Halt Handler routine is entered from the Startup and Stop Interface when the RUN flip-flop is
clear at NICOND Dispatch time. The RUN -{lip-flop can be cleared by various mechanisms. For
example, when a HALT instruction is executed, RUN is disabled. On power up, RUN must be set by a
diagnostic function initiated from the DTE20.
The I/O Handler (Figure 2-21) is dispatched via IR Dispatch from the Dispatch Table on DATAO,
CONO after the data or status has already been fetched, or directly on DATAl, CONI, CONSO, or
CONSZ. The handler calls the EBus driver, which generates the necessary EBus dialogue with the
device. On BLKI or BLKO, the pointer has been fetched but must be updated, stored back at E, and
the first word fetched. This is performed in the I/O Handler first. When the data has been fetched, the
EBus driver is called. On DATAl or CONI. the EBus driver is called to negotiate the transfer from the
selected device over the EBus to the EBox. The I/O Handler then passes control to the Data Store
Manager where the data is stored.
2.3 BASIC MACHINE CYCLE
The basic machine cycle for a typical instruction is illustrated in Figures 2-22 and 2-23. The cycle
begins at the EBox clock following NI COND Dispatch and terminates at the trailing edge of the next.
NICOND Di~atch. In this example, assume that the instruction MOVE 3 @ 200 (1) has been fetched
from core memory symbolic location Pc. The following information relates to the example:

PC/
PC+l/
300/
100/

MOVE 3 @ 200 (1)
NEXT INSTR UCTION
000000, 000 100
171717,111111
000000,000100

(-_

Current Instruction
Indirect Address = 300
Effective Address = 100
Index Register = 1

CONTROL

RAM

(
1-------'------'-----1 777

DISPATCH

RAM
10-1546

Figure 2-21

Input/Output Handler

EBOX/2-20

LOC/\TION IN-STRUCTION

MOVE 2; \tt'~ 200 il)

300:.000000,OOOEiO

'IOO~rl17nj1l11'H

1 ,;DOOOQO,OO'O~OO

;r------

~ARo
000000,
000100
,

INDIREC1' WORD
IN AR)("

AR"171717,::]11111

-----------

:c.._.....l2!'OOC:0 ,OOOI00J

NOTES:
.)1,

During 1;J.80X wail's EBQ)(

SY~.,jC

remains

true unHI MSQ)( reel'.

eHe funclion·al operations
which are !)sed 1'0 dosG!'ibe ffi'5!mory rmql!8S'rS
Cit H18 E/f..1 lNTERF.ti.CE.

3. MBOX cycles

lndG}<;ing is p2dormed eVffl thou?,:') ill ¥his exomp!e

ARX 14-17

dispu1ch \o1]ill

uno will not D8 used.

(;OUS·<,l

Th~

EAfv10D

i--- E<)O)(

the ne&r:T MICRO instruction ~o

do ih& correct step e.g.

P,D; E

5. P,R<:I- 000200+000'100'" 000300
This is the IND!RECT WORD ,o.DORESS

CYCLE

, X - - - - - ·...I

TIME Bft.SE FOR-l,
EBOX CYCLES

10- 1591

Figure

IVlachine

EBOXj2-21

Ov!erview (Sheet 1

EACH SECTION IS A
MINOR MACHINE CYCLE

ENTRY POINT
PRIORITY

10-1592

Figure 2-22

Basic Machine Cycle Overview (Sheet 2 of 2)

EBOXj2-22

c:;0
I

MTR REO
FOR PI

NleONO DISPA TCI-II'VAS ISSUED AND
UNLESS AN INSTRUCTION PRE FETCH

IF INTERRUPTOA TRAP
IS PENDING DIVERT FROM
HERE PERFORMING FIAST

WAS ATTEMPTED fROM FAST MEMORY,

f--------

=,_~

! rJ

hE
tll
W

IFA

N
LA'>

(""
'-'

>:~

~-........

~,jl

I
AR

r~":EMo:lI
,

CYCLE
CONTROL

XCTGO

l~-.-J

1111 i1
NOTE:
Thi's clj)et"(Jiioi'i fGfiect11

th~

rrnitl'O cocl~ ve!"~ion 0200

000000,G0010(}

VMA I~D

II
I

r~'.~.~J~.~.."

r-~--\

VCMI ADB \

{~~~.---..::.

,C.

VMA ADA

!~--L.......~_\

_BR)(~ \
..-.-~~-.~-~

-----.-~--~--.-------

d
RI

tTl
~

~'~I

~--~-~
FM

•

1/,

--l

7/'ib

7'777777

..~L~~~
/ / 1 / / , / ' 1/1

Ie.)

--f I
I

~~. "~'.f2_1

r~-~~~~~

---_.

0 - - - '

~_J

ARM

~ ___-=p,DA

[

n
AC'

17 1

MEMORY
CYCLE.
CONTROL

x
A+r:,
-~)'; I
~ L~
_
_
_
_
I
~L _ _._________
_

~-~--!

____

'DB
~-::_'~",--.,,_

SC:TUP FM

c:.l}!:~TROL

F. DR'\
~!"'l:1.

~AR ~

"
/
~-~~-r-'I~~---'-~~-~
-1

10 LOOI< AT

I~RX

14-'7

I,
1

GRAM

I"':{h.:~;,; Li"""'1
[
],I
MEM

1-----, -:-;-:

DISF'
== ---"T""":~

ME"
-j~'

--T~~'

-L~~_~_~

~-'-..L""_::,-=_~J~'---'-- -.~~
I

___---l.____
I

_ _ _ _ _ _. _ _ _ _ _

1 , - - _~~,

I;
i

EBOX
CLOCr:
CONTROL

Ir-

I
I

CON1R0l Rt\~;.!1
RFGI"TER

1}:-_r I

//a" 1[10 11

1/// /

DISPATCH
RAM REGISTER

L-~
Il.RXM

'Mnv. E

~L~,..J

r-----.---.~
"\ _____. ._____111~__; . .
,I

~-,
~---A-'
.~~."
'-\

'---r-~ /77/

----

I--~~'-~'-l
,
FM
I

REQ

r~l~ -~--T~~--~

(" K "RrM

ARX1

r:: f
/

~~,~g-:;"'-1ir ~_-==-'--- (
J-I
II L'"~:'''
.
~ BOX ~
I
COM~EA ~NDRCT I I ,,:I
j
I
i
__
000000.000100 ,1'---

'-"J'
-

l
____..i'
1

f·--..J.~··-~,\

~-.. - - -....~.

DRAM

l__!~.J

I NI

r~---L._--._-~."

CLOCK CRM
----.-.-----

,____________ ----1

~
-

CLOCK DP

~-~-<,~-~~-==<..~~

10 -159~~

Figure 2-25

Up and Make

Work

Table 2-5 MBox Cycle Requests
MEM02

MEM Field

MEMOO

Causes

Function

MBox Wait

A READ

Fetch Cycle

BWRITE

Store Cycle

FETCH

Instruction Fetch

Yes

REGFUNC

MBox register reference

Yes

AIND

Indirect reference during
effective address calculation

BYTEIND

Indirect reference for byte
instruction special

LOADAR

Data read during
execution, loads into AR

Yes

LOADARX

Data read during execution,
loads into ARX

Yes

ADFUNC

Not used

BYTERD

Data read during byte
execution loads into AR
andARX

WRITE

Store data during execution,
writes from AR

Yes

RPW

Initiates a read PSE write
cycle, data loads into AR

Yes

The time field for the microinstruction at location COMPEA+3 specifies a period between the EBox
clock that loaded the microin~truction from COMPEA + 3 and the next EBox clock. It allows sufficient
time for the access of fast memory to be completed. Note that EBox request and EBox sync are
concurrent (Figure 2-26). The earliest time that the MBox can clear the request is on the MBox clock
following EBox sync. In Figure 2-26, EBox sync occurs one MBox clock prior to where the time field
indicates EBox clock can occur, but because MBox wait is true and the MBox has not yet responded,
the EBox clock is postponed as indicated.

EBOXj2-28

Mt,MORY CYCLE

~~@:-;:o~~j~~~- ~~'=~~J
E!~,;=tllEST

T!ME i'A80>: Cf,N

CLEA,R EG,C)( REQ

CSH EBOX TO

to-1596

'Wm'o

R.'~'lJlne§t

fc:tched frOhn symbolk: LV'~;'H.<

ADB

IR~ i~

6 ~

r:::T":'"l

ADA

1
DRAM

,
5

MOVE

'--_,,_ _ _ _ _ _...1

LATCHED"
•
FM

~AR

---

ADR=O

V//lmili////;:

Vol

000000,000100
GARBAGE

1
ARM

ARXM

~~gx

.......".,.-,..-_....1

__ ~

FM WRITE
SETUP FM
CONTROL
CONTROL TO LOOK
AT VMA 32 - 3 5 '
J
AD
ADA
ADB
FM ADR

f~SEBOX J :gE~1~rL

MBOX
RESP
IN

INDRCT:IIND1LP

ARX

VMA

~
CRAM

000000,000100

L CONTROL

[IARX

I-------t------------+---------------.Tf
I

IS FROM FM

BR~

/ '"' "'\ / ,.,1", \

tTl

lVMA

000300

ED~~~DI

INPUT 1
SELECTED
BY MB XFER

COMPEA

:INDLP

I
MEM

IA~~; I

•

DISP

1~~~;rsR,.~LRRAM

'------------------~I--+-----------------------~-----------I

EBOX
CLOCK
'--_________________________________________~[iN~H~C~L~O~C~K]~ CONTROL
[RESTART
CLOCK]
MBOX WAIT

CLOCK CRM
I

NOT YET GENERATED
BUT AB~UT TO BE.
I - CLOCK DP
10-1596

Figure 2-27

MBox Response to Indirect Request

•
1

/
/

E
I
M

tI1

c:I

o
><

---....
I

VMA ADA \

CO::ROL

DRAM

ARX 4-17=0

1MEMORY
CYCLE
CONTROL

FM WRITE
CONTROL

MOVE

1 !

IIARX13=0

ARM

ARXM

-t

CRAM

~ .. i OOOOOOiooo,ooi

3
2

CRAM ADR
09-10=0

-V////////// / //

000000,000100

CRAM
ADR
CONTROL

·'3

F
M

ADA

(ACO)

VMA ADB \

I I 1~1

000000,000100

\=/

ADB

1<::

"LATCHED"

,.r

VMA AD

ADR=O ~

1<::

1:1 '"

IR 1200

AD
+B
(ACO)

I
N
T
E
R
F
A
C
E

Wfi1

IVMA

lOOO100

AREADl

COMPEA

I
AD

INDLP: COMPEA

A+B

ADA
I

ARX

ADB

FM ADR

XR
I

DISP

I CONTROL
RAM
REGISTER
I

EA MODI
DISP

I
EBOX
CLOCK
CONTROL

CLOCK CRM
f-- CLOCK DP
10-1597

Figure 2-28

Address Calculation Continues

•
o

E
/
M

tTl

tJ::J

...... ........
~

........

.--.

lR \200

VMA

... .--.

I ~ i~\
3

DRAM

I
N
T
E
R
F
A
C
E

,---J

----

IjJf///ug,~

tv
I

CRAM ADR 08-10,05-1

tAR

I
ARXM

:45

000000,000100

EBOX REQ

EBOX READ

r-~---.--~~-r~~~'-~~--r------'-------r~~~-r~~-L~-------------'i

MEMORY
CYCLE
CONTROL

CONTROL RAM
REGISTER
~

DRAM A=5

EBOX
CLOCK
CONTROL

CLOCK CRM
CLOCK DP
10-1598

Figure 2-29

AREAD Dispatch Setup Data Fetch

/-\

2.3.6 MBox Response to Data Read - Prefetch Begins
Figure 2-30 illustrates the CRAM register cop.taining the microinstruction from location 45. Thejump
address once again is zero, because the 'actual jump address is provided by the DRAM register jump
field. In the case of MOVE, the symbolic address is "MOVE." This location contains the first microinstruction in the executor for the MOVE instruction. Only one microinstruction is required for the
execution of the basic MOVE. This dispatch field contains DRAM J, enabling the CRAM address
control to utilize the jump address in the dispatch register. Thus, for the basic MOVE, symbolic
location "MOVE" contains the desired microinstruction. The MEM field is coded as fetch to enable
the memory cycle control to begin the prefetch by asserting EBox request with EBOX READ.
Until the MBox response to the data read is received, the VMA is latched and only the VMA input
contains the updated PC value. When the MBox response is received, the VMA is loaded with the
updated PC value (PC+ 1). At the same EBox clock, the data on the cache data lines is clocked into AR
(000100). Referring to Figures 2-30 and 2-31, the FMADR field enables FM to be addressed via VMA
32-35, even though in this example VMA address 000100 is not an FM address. FM location 0 is
actually accessed and enabled via ADDER B into the AR mixer.
The Memory Cycle Control asserts LOAD AR. The address in VMA is checked in the VMA Control
and, because it is not a fast memory address, - VMA AC REF is asserted. This is passed to EBox
Control No.1 logic and inhibits the generation of FM XFER.

MBox RESPONSE IN is passed to the EBox clock control where it becomes (on the next MBox clock)
RESPONSE MBox. This, with LOAD AR, enables the selection of ARM SEL 1, which enables the
cache data into AR. The EBox clock then strobes the AR register. This clock also clocks the next
microinstruction from symbolic location MOVE into the CRAM register.

~./-:::)2.3.7

Executor - Set Up for Store Cycle
'\.) . For the basic MOVE instruction, the data word in AR must be stored in the FM location specified in
the AC field of the currently executing instruction. The microinstruction J field contains the base
address for the data storage microprogram. This is symbolic location STO. The Dispatch field is coded
as DISP B, which enables the B field of the DRAM register to modify the low-order three CRAM
address bits (CRAM 08-10). The B field is 5 for MOVE and this yields symbolic location STAC.If, for
example, STO was physically 60, the resulting address would be generated by logically ORing 60 with 5
for a result of 65.. symbolically STAC.

•

Referring to Figure 2-32, IRAC contains AC address 3, and is enabled to address FM because the
microinstruction FM ADR field is coded as ACO. This is the AC specified by AC 09-12. The MEM
field specifies B WRITE, but no request is issued. This is because the memory cycle control samples the
DRAM B field and inhibits an EBox request when DRAM BOI is a zero.

EBOXj2-33

•
VMA WILL BE LOADED WITH
PC + I ON THE NEXT EBOX CLOCK

000100

000100
)

IVMA

I:l 9

h~1

ADB

ADA

E
/
M

tTl
t:Ij

IV
I

!..hI

+1'

VMA ADB \
+1

ADR~

A
D
R

EBOX REO

...J

\
I

•

i MEMORY

CYCLE
CONTROL
--,

1000000,000100

-I

45:

GARBAGE

i 171717,111111

ARM

f f

I MOVE

I
CRAM ADR
00 10

ARXM

•

)11,WRITE
B :IDRAMI
B

STO

MOVE

FM WRITE
CONTROL

CSH EBOX
TO

..... 'i'////////////

FM
CONTROL

~~--

DRAM

.('"

CACHE DATA
00-35

CRAM
ADR
CONTROL

~
F
M

000000,000100

VMA ADA

--.1

IN CASE REF
IS TO FM

""'"

I
N
T
E
R
F
A
C
E

----

VMA AD

PC+I

PC+l

':I

IRE[]

ADA

ADB

MEM

FETCH

MBOX WAIT
UN CLOCK]

DISP

DRAM J

J
FM ADR
VMA

EBOX
CLOCK
CONTROL
[CLOCK
RESTARTSJ

CLOCK CRM

Figure 2-30 MBox Response with Data Word Requested

LCONTROL
RAM
REGISTER

10-1599

AR SEL 2

*AR

r-----.,

SEL 1

EBOX
CONTROL
#1

1--'-"'--'-"-==---1

1
1 - 1- - - - - ,

--~

MBOX CACHE DATA LINES

r----l
LOAD AR

I
I

I
L-

r-----.,
I

MBOX RESP IN
...;.:;,::c,;:.,;.;....:.:.::.::.:.-...:'-'--_ _ _ _--.j.

EBOX CLOCK
CONTROL

I RESPONSE

r,----;,
MBOX

_-..J

L-"""""'"

* Somewhat

VMA=OOOI00

VMA

L_-

II
-VMA AC REF

1------'

CON:O:-_J

idealized.

Figure 2-31

(

MEMORY
CYCLE
CONTROL
.............. - - - J

Hardware Selection of ARM Data

2.3.8 Finish Store Cycle - Perform NICOND Dispatch
The CRAM register now contains the microinstruction from symbolic location STACK (Figure 2-33).
The J field specifies the base address NEXT and the Dispatch field contains NICOND Dispatch. This
completes the basic machine cycle by reentering the instruction cycle once again.
The FM ADR field maintains the FM address via IRAC and the COND field is coded as FM WRITE
to write the contents of AR into FM location 3. The MEM field is coded as MB WAIT for the cases
where the next instruction has been prefetched from memory. This forces the EBox to wait until the
instruction enters the ARXM and MBOX RESPONSE is received. If the instruction is being fetched
from fast memory, MB WAIT has no effect and the microprogram selects the appropriate microinstruction to load ARX from fast memory as addressed by VMA 32-35.

_ - - - 2.4 PAGE FAIL CYCLE INTRODUCTION
____ Normally, primary memory is the MBox cache memory, secondary memory is core memory, and the
auxiliary memory is a disk or drum. Information is moved into the core only on demand (Demand
..
Paging), i.e., no attempt is made to move a page into core memory, and consequently words into the
cache, until some program references it. Information is returned to core memory in accordance with a
hardware algorithm in theMBox hardware. Information is returned from core memory to auxiliary
storage at the discretion of the operating system:a,pagi0ia,algorithm. Information movement across the
gap bridging the level between auxiliary storage and core memory-cache memory is called page traffic.
The MBox, in a sense, is an interface between the EBox (processor) and the SBus. It provides individual mapping (relocation) of each page (512 words) of both user and monitor address spaces, using
separate maps for each. The MBox uses hardware storage to access and load the mapping information.

EBOX/2-35

•
u

PC +1

IVMA

L
/
/

E
/
M

tI1
tl:i

~
tv
I

---

I
VMA

I
/

ADB\

ADA

IRED

IR~1
AC

VMA ADA \

ADR: 3

F
M

31/////////;7;/// 3

2
1

FM WRITE
CONTROL

FM
CONTROL

"NO REQ
IS
ISSUED"
FOR FM
DATA WR

CRAM
ADR
CONTROL

MEMORY
CYCLE
CONTROL

MOVE:

171717,111111

ARM

171717,111111l

A
D
R

0'\

DRAM

•

I
N
T
E
R
F
A
C
E

1,./

ADB

VMA AD

lAR

CRAM ADR
OB-l0

ARXM

"LAT CHED"

1 1
1

MEM DISP
1MB_I NI
WAIT COND

:STAC

STO

ADA

A +XCRyl

ADB

BR* 2

MEM

FM ADR

ACO

B WRITE

DISP

DRAM B

I REGISTER
CONTROL RAM
I

I
LDRAM 8=5

EBOX
CLOCK
CONTROL

CLOCK CRM

10-1601

Figure 2-32

Executor Setup for Store Cycle

•
--NEXT INSTR COMMING IN

PC+l
I

/
J..--

t'I1

IJ:j

-........

VMA ADS \

ADS

I
ADA

t±J

i~1

1
DRAM

VMA ADA \

CRAM ADR
07-10
"CONDITlONS"-

~
F
M

ADR= 3

171717,111111

MEMORY
CYCLE
CONTROL

ARM

ARXM

FM WRITE
CONTROL

STAC:

f"NEXTINSTR"

I CO~TMROL

~ARI

3
2

CRAM
ADR
CONTROL

A
D
R

,.r

BR3

/ VMA AD

I
N
T
E
R
F
A
C
E

VJ
-...l

VMA=
AC REF

/
E
/
M

IVMA

FM
WRITE

ADA

ADS

NEXT IA + XCR1

I
I

MEM CONDI
MS
WAIT

FM ADR DISP

FM I
WRITE

ACO

I CONTROL
RAM
REGISTER

NICOND

I
I

.ESOX
CLOCK
CONTROL

CLOCK CRM

10-1602

Figure 2-33

Finish Store Cycle, perform! NICOND Dispatch

It also contains a 2048 word cache for holding the data for the mapped references. On each memory
request from the EBox, the nine high-order bits of the virtual address and the type of request (read,
write) are compared with the contents of the' hardware tables in the MBox. If a match is found, the
location containing the match also contains 13 high-order address bits to reference the physical page in
the cache. If no match is found, a 512-word "Page Table" in physical core memory is referenced. The
word selected in this page table is determined by a dispatch bas d on the original nine high-order
address bits. The 13 high-order address bits and use bits found in tn word are written into the MBox
hardware table; the use bits are checked against the type of EBox re rence. Four possible cases exist
concerning the disposition of the use bits:

1..........The
2. The
3. The
4. The

page
page
page
page

is
is
is
is

not in core.
8~
protected from the type of request.
(... ~
nonexistent.
'\
in core and is compatible with the type of request.

£?

For the first three cases, a page fault (trap) occurs; for the fourth case, the requested word is fetched
from core memory (actually words are fetched four at a time, differing only in the two least significant
address bits) and written into the cache. Concern here is with the page fault situations. The MBox
constructs a page fault 'Ulrd in one of its internal hardware registers, the EBus register. The word
contains information relating to the type of fault that occurred. The EBox is waiting for an MBox
response to its request; the MBox, therefore, asserts PF HOLD, and some time later asserts MBOX
RESPONSE IN. When the EBox recognizes the PF HOLD signal, it forces the CRAM address to
1777. This is the first microinstruction in the micropage fault handler. The EBox does not issue an
EBox clock until the CRAM address has had time to set up. Once the address is stable, a single EBox
clock is issued to the CRAM board to access the microinstruction.
2.4.1 Page Fail Handling - Functional Flow
Figure 2-34 is a functional flow of the microprogram page fault handler. The EBox contains a 4-bit
state register. This register, during certain instructions, holds a number that may be used to modify the
state of the CRAM address. For instructions that do not use the State register, it contains zero.
Generally, the STRING, EDIT, and BLT instructions require cleanup following a page fault so that
they may be properly terminated. For these cases, the State register contains a value in the range of
1-7. The more general case is discussed here; this is where the State register contains zero. For both
cases, INSTR ABORT (coded in the condition field of the microinstruction fetched from CRAM
address 1777) performs the following functions:

(

(
I

TRAP REQ 1 +- TRAP CYCLE 1
TRAPREQ2 2 TRAPCYCLE2
ADR BRK INH +- ADR BRK CYCLE
These actions are necessary to assure that the PC flags reflect the state of the EBox when a page fault
occurs during the fetch of the trap instruction, during its execution, or during an address break page
fault. A State register dispatch is given, but because the State register is clear, the base address is used
to obtain the next microinstr1!ction. A priority interrupt has a higher priority than a page fault (Figure
2-35); therefore, a pending interrupt is checked for first. If INT REQUEST is true, the PI Handler is
entered to service the interrupt. If no interrupts are pending, the page fault is handled. The third level
of priority is given to traps and finally to all other events being processed by the microprogram.
A page fault occuring in response to an API interrupt function is a fatal error. Thus, when the page
fault handler finds PI CYCLE set, it sets the I/O Page Failure flag, dismisses the failing interrupt, and
then, if possible, restores the EBox to the state it was in prior to the interrupt. The setting of IOPF
eventually causes an interrupt on the APPR error channel. The PF Handler now attempts an instruction
fetch.

EBOX/2-38

"ANY PAGE
FAUL T ENTRY"

PERFORM STATE REGISTER
DISPATCH. (STATE REGISTER
RANGE 0 .; SR .; 17)
INSTR ABORT: COPY STATES
OF ACTIVE TRAPS (TRAP
CYCLE 1.2) INTO
CORRESPONDING TRAP REO
FLAGS THEN CLEAR TRAP
CYCLE 1 AND 2.
INH ADR BREAKS

"NON PAGE
FAILURE ENTRY"

SR=O

CLEANUP
EXTENDED

IOPF-l
"FATAL ERROR"
DISMISS THE
INTERRUPT AND
TRY AN INSTR
FETCH. WHILE
WAITING FOR
THE APR INT.

YES

WAIT FOR BUS

READ EBUS REG
ARX-PC;
CURRENT PC
PC-VMA;
FAILING
VIRTUALADR

10·1603

Figure 2-34 Page Fail Handling (Sheet 1 of 2)

EBOXj2-39

PHYS~C!';;'L

A.DDRE!]S

N01"E

[Ins

~BOX

REPU·\CES

'1;2,-2G

't1~ lH '1!'L,~.~, 'j

mTS

14-~G GO~~TA~,r'J

3-:26

THE V1B"rU.I.4.L PAGE:;¢
iHE F,~.ULTH\jG

,')r

PAGE,

:
pr-

HOLD 01
~}S~R

____==-u,-.-",-=-_ _

PC WORD
f-H(JM rnOCESS

TP,m.. E lOCAT:1.:)r\l
UBR+5!D2

EBOX R:=OUEST

ESOX REQUEST

1'1180)( REsr

INPUT fROM 501

;iJlOBX RES?

Ji--~I

~II

UPT REF, STORE
OLD PC WORD

Ir~

!I:

PROCESS TABLE

ullOC,'lTION

-, "r

UUBR+,;;5,;;,O~1~_~_

MBOJ(WAIT~O

I~~-J

" lViBOX WAIT'~l

ENI\BlE V M A '
, H>JPUT FROM 5[12

f'~

EBOX REQUEST

i\!ISOX FlESP

"~"""~O J

N07E 2:

\,~X'f

FO~NT

THE
THE

(

T:-~= HjrTii~L Ef'JTR':r'

START

"',-"I

Handling

FOR THE fv'H;C:RG Pt:10GiR,j.,\M

,t:\;~

= FLAGS, FC

vr\"1;\~-/.\j:~

(

ENTRY)

YES

"I/O PAGE FAULr '
PI HANDLER

"TRAP INSTR PAGE FAULTS"

YES

PF HANDLER

YES

NO
TRAP HANDLER

OTHER ACTIVITY

10-1605

Figure 2-35

EBox Priorities

Obtaining and Adjusting the PF Word - Assuming PI CYCLE is clear, the AR is cleared and the ECL
EBus is requested. This is to transfer the PF word from the MBox EBus register to the AR register in
the EBox via the EBus. Because the PI system and external or internal devices can also use the EBus,
the microprogram must force its release. When the ECL side is .obtained, the EBox reads the PF word
into AR. The PF word, as it is constructed by the MBox, contains the physical page number in bits
14-26. The EBox must replace this with the virtual address and also clear bit 13. The current virtual PC
is temporarily placed into ARX; the failing VMA is placed into AR while the old PC is saved in BRX.
The ECL EBus is then released. The ARX and AR are shifted to adjust bits 13-26 to be the VMA
13-26.
Figure 2-36 shows the three locations in the user process table dedicated to page fault handling.

EBOXj2-41

~
UBR

II
_

...!BOX

;..J

500

STORE PF WORD HERE

501

STORE OLD PC WORD
HERE

502

NEW PC WORD

SECTION OF
USER PROCESS
TABLE

!
i,..10-1606

Figure 2-36

Process Table PF Location

2.4.2 Process Table References
The VMA is loaded with low-order process table location 500 and an EBox request is issued to write
the PF word (concurrently in AR) into process table location UBR+500. The next microinstruction is
loaded and EBox clock sets MEM CYCLE, causing MBOX WAIT. The AR is enabled from the old
PC word; the input to VMA is now 501. As soon as the MBox responds, MBOX WAIT is removed
and the cycle is repeated. This time the EBox request is to write the old PC word (now in AR) into
process table location UBR + 501. Once again, the next microinstruction is loaded and EBox clock sets
MEM CYCLE, causing MBOX WAIT. The VMA input is now 502. As soon as the MBox responds,
MBOX WAIT is removed and the cycle repeats, in this instance for reading a new PC word from
process table location UBR + 502. The new PC word places the EBox in a specified mode and the first
instruction is fetched from the appropriate handler. This completes the page fault cycle.
2.5 TRAP CYCLE - INTRODUCTION
A Trap is produced by setting either of two trap request flags in the EBox (TRAP REQ1 or TRAP
REQ2). The programmer knows these flags as TRAP2 and TRAPI. The conditions that set TRAP
REQ1 are equivalent to the arithmetic overflow conditions that set SCD OV. TRAP REQ2 is set by
the various pushdown overflow conditions: the left half of the pointer is counted down to -1 (no carry
out of bit 0) in a POPX, or is counted up to zero in a PUSHX. (The condition for this is the presence of
a carry out of bit 0, but the condition is detected by the microprogram and the trap request flag is set.)
2.5.1 Trap Handling
The Trap Handler (Figure 2-37) is entered at NICOND Dispatch time providing its priority is highest
of the major priority events. The microprocessor NICOND Dispatch, together with four queues
arranged in a round robin priority structure, is shown in Figure 2-38. The TRAP request is served only
when QO priority interrupt requests are pending and no page fault is pending. It does, however, preempt the normal instruction cycle. Both the user and exec process tables contain dedicated locations
for processing traps. These locations are XXX 421 for arithmetic overflow (TRAP1), xxx 422 for
pushdown overflow (TRAP2), and XXX 423 for the programmed trap (TRAP3). XXX is replaced by
the appropriate base registel' (UBR or EBR), which resides in the MBox. The base register used by the
MBox is determined by the state of the qualifiers sent during the EBox request. The MBox fetches the
appropriate trap instruction and places it on the cache data lines while issuing MBOX RESPONSE
IN. The EBox then executes the trap instruction. It is possible for the EBox request for the trap
instruction to cause a page fault. If this occurs, the page fault handler is entered at CRAM address
1777 and the trap cycle flags are pushed into the trap request flags so that the trap flags may be saved;
the trap cycle properly reenters at a later time.

EBOXj2-42

•
,...

CYCLE Z
CYCLE 1
"
~\
'l"BIT 34" lBIT 35"
()O
#=420
COND=VMA-#
VMA
"SEL VMA AD"
CONTROL
EBOX CLOCK

/1-

421-AROV
VMA= 422- PDOVL
423-PROGRAMMED TRAP

EBOX REQUEST

LOAD ARX
EBOX
REQUEST
CONTROL

CSH EBOX Till

MCl MBOX
CY C REQ

f
MBOX CLOCK

,
MCl VMA UPT

PAGE TABLE
REFERENCE
CONTROL

MCl VMA EPT
MCl PAGE UEBR REF

t:Ij

--tv
I

"'"

~VMA~CONDl

~MEM~SPECT

~
"ADA"
MEM02=1

MODE
CONTROL

EBOX ClK

USER

MEMORY
CYCLE
CONTROL

T
T

I.U

ClK
RESP
MBOX
MBOX RESPONSE IN

INSTR

--------

MBOX WAIT
ClK RESP MBOX

MICRO
INSTR

-------

]

T
lOAD IR
T

L--f

MCl
lOAD
ARX
EBOX ClK

-------

TADATMEMICOND~

"ARX"

EBOX
CLOCK
CONTROL

-- --'
---MICRO

PT REF,READ
TRAP INSTR.
FROM USER OR
EXEC PROCESS
TABLE INTO ARX

#04,05

ARX-MEM

I
N
T
E
R
F
A
C
E

MICRO
INSTR

--------

-------#"

SP MEM CYCLE

E
/
M

tI1

ADA

-t:

SEl2
-'''SELECT SEll
'----' CACHE DATA"

CACHE DATA LINES (TRAP INSTRJ-

ARXM

HANDLER

"EBOX C

\
:/

NOTE l'
VMA
27-33

VMA
34

420 8

I LTRAP

ARX

WAIT FOR MBOX
RESP ENABLE
ARX INTO AD
ENABLE AD
INTO IR

420 8

VMA
35

I TYPE

OF TRAP

AROU

PDOVl
PROGRAMMED
TRAP
10-1607

Figure 2-37

Trap Cycle

...

~
MICRO
INSTR

MICRO
INSTR

NICOND
DISP

[H IGHEST]
01
DEV
1

PI
REO

f--

FAULT

PAGE
FAULT
REO

r--

TRAP
FLAGS

TRAP
REO

EVENT
0

INSTR
CYCLE

DEV
N

DEV
2

MICRO PROCESSOR
WITH EMPHASIS ON
NICOND

NOTE:
Event 0 would be for example the
INSTRUCTION CYCLE

[LOWEST]
10-1608

Figure 2-38

Central-Server Model (Round Robin Priorities)

2.5.2 Address Generation
Referring to Figure 2-37, the VMA is enabled to be input from the VMA ADDER. The condition field
of the current microinstruction enables the number field to generate the process table low-order
address 420; the low-order two bits of VMA AD 34 and 35 assume the state of the trap flags.
2.5.3 PT Reference for Trap Instruction
The next microinstruction must generate the EBox request and enable the appropriate qualifiers to
appear on the EjM Interface lines. The page table reference control samples the state of the USER,
together with the special function and number bits and then asserts either MCL VMA UPT and MCL
PAGE UEBR REF for a USER trap situation or asserts MCL EPT and MCL PAGE UEBR REF for
an EXEC trap situation. The MEM field is coded to load ARX and enable the EBox request.
Assuming no page fault occurs, the MBox fetches the instruction, places it on the cache data lines, and
asserts MBOX RESPONSE IN. The MEM cycle control samples the MEM field function LOAD
ARX to enable one leg of the ARXM and CLK RESP MBOX enables the other leg. Thus, the instruction enters ARX on the next EBox clock. Next, op code and AC field of the instruction in ARX must
be enabled into the ADDER and then latched into IR. The condition field of the current microinstruction CONDjLOAD IR unlatches the IR for one EBox cycle, allowing the AD to load into IR.
On the next EBox clock, it latches again. The final step is to perform the trap instruction. This completes the trap cycle.
2.6 INTERRUPT CYCLE - INTRODUCTION
The system must possess a true priority interrupt system that is flexibly structured and controlled. Its
operation in establishing priorities and recording and sequencing interrupt requests is essentially
instantaneous and independent of EBox action. Interrupts of high priority must be permitted to interrupt partially completed responses to those of lower priority. To maintain fast response, interrupt
requests should require no decoding action on the part of the EBox to determine their source or
nature. Capability for dynamically varying the priority structure to meet the demands of a changing
environment must be available. In addition, no other system element may be designed such that its
proper operation requires inhibition of the priority interrupt system for any period of time.

EBOX/2-44

~ The basic priority interrupt level has four mutually exclusive states that can be described as Disarmed
(-PION), Armed (PION), Waiting (PI REQ), and Active (PI HOLD). Figure 2-39 shows the basic
concept of the interrupt system for two channels. It is arranged in four groups, the interrupt state, the
FF configuration for two of the seven possible channels, the level enable, and the source of change
signal. In the Disarmed state, the interrupt level rejects all incoming interrupt trigger signals. By
performing a CONO PI and specifying the appropriate bits, the priority interrupt system can be armed
or disarmed for any or all channels.
>-In Figure 2-39, the processor (CPU) performs a tONO PI and arms both channels. In the armed state,
the interrupt level accepts a trigger signal from an outside source or from an internal source, e.g., the
APR, and moves to the waiting state (REQU..,gST STATE), where it remains until it is acknowledged
by the EBox: All waiting and enabled requests are input to a priority network where they are compared
with the current state of the priority interrupt system. In this example, both channell and channel 2
are requesting service, and both channels have previously been armed by a CONO PI instruction. In
addition, an interrupt is shown holding on channel 2. Thus, until it is dismissed by the processor, the
channel 2 request pending is held in abeyance. Furthermore, the channel 1 request causes the device
subroutine for channel 2 to be interrupted, diverting the processor to the device subroutine for channel
1. The first instruction that will be executed as a result of an interrupt (subroutine type service) is a JSR
instruction. This instruction saves the processor flags, program counter value, and also holds the
interrupt.
FF CONFIGURATION

INTERRUPT
STATE

CH # 2

DISARMED
(- PION)

(

CH # I

[EJ
I

LEJ

SOURCE OF
CHANGE SIGNAL

"CONO PI"

~I.----------TI---------CPU

cd]' dJ'

ARMED
(PION)

'..

I
DEV A} INTERNAL OR
14:.- --------DEV B EXTERNAL SIGNAL

I
I

WAITING
(PI REO)

LEVEL
ENABLE

I-__~_ TO MICRO CODE
PI NET
~ PI HAN DLER
~~---CH-#--l----~I~

ARBITRATION

REO
I
HIGHEST:
ENABLED

ACTIVE
(PI HOLD)

! K t SPI
E
HOLD
T

:~:~N:0+2N
NO HIGHER PRIORITY
LEVEL ACTIVE

DEVICE SUBROUTINE
IN PROGRESS IS
[ DEFERRED
FOR
HIGHER PRIORITY
ON CHANNEL # 1

E BOX FETCHES
JSR INSTR

WAITING, AND ENABLED

CHANNEL #2
IS HOLDING NOW

THIS WILL SET HOLDING THE
INTERRUPT ON CHANNEL #1
TO DISMISS THE INTERRUPT A JEN
INSTRUCTION IS EXECUTED IN THE
CORE MEMORY INTERRUPT HANDLER
10 - 1609

(

Figure 2-39

Interrupt Level Operations
EBOXj2-45

When service has been completed, the service routine dismisses the interrupt, restores the flags and
program counter, and the channel 2 subroutin~ continues. Interrupt channels are organized into seven
basic levels, which are software assignable (armed): the lowest number has the highest priority within
the numbered sequence (Figure 2-40). Each channel is subdivided into finer levels or priority by hardwired physical device numbers. As indicated, the first eight physical numbers (0-7) are assigned to 1-8
Massbus controllers in the system. The next four physical numbers (8-11) are assigned to 1-4 DTE20s
(10/11 Interfaces); and numbers 12-14 are reserved for expansion. Finally, physical number 15 10 is
assigned to the I/O bus adapter (one exists per system, if needed).
Each interrupt channel has a dedicated pair of unique locations within the EPT. These locations may
be indicated as 40 + 2n, and 41 + 2n; where n represents the channel number. When a device initiates
an interrupt in the KL10 system and is selected for service, the device places onto the EBus a special
function word hereafter labeled API function. This function contains information that specifies the
type of service regui~d. Figure 1-32 indicates the format of this word. Note that the format varies
from device to device, but the functions that can be specified in bits 3-5 are common to all system
devices. Function codes of 0, 1, and 7 cause instruction fetches from 40 + 2n initially and, depending
upon the type of instruction in 40 + 2n, may at some point perform an instruction fetch from 41 + 2n.
--.
In general, 40 + 2n contains one of the following types of instructions:
~JSR

,.--. JSP* .---- PUSHJ*
, ___ MUUO

151 PRIORITY
HIGHEST
INTERNAL TO PROCESSOR
2nd PRIOR ITY

3rd PRIORITY

41h PRIORITY

•

M M M
B B B
C C C

6th PRIORITY·

------

'" - -7th PRIORITY - - ....
LOWEST

PHYSCAL # WIRED
PRIORITIES

HIGHEST

5th PRIORITY

M M
B B
C C

M
B
C

LOWEST

7' 8

9 10 11

12 13 14 15

M
B
C

U
B
C

I
B
C

U
B
C

~
LEGEND
M BCU BCIBCAPR MTR -

--------

MASS BUS CONTROLLER -RH-20
UNIBUS CONTROLLER DTE-20
I/O BUS CONTROLLER DIA-20
ARITHMETIC PROCESSOR STATUS REG
DEY ICE OK -20
10-1610

Figure 2-40 Typical Interrupt Priority Chain
*These instructions should not be used because nothing is known about the ACs when the interrupt occurs. JSR
or MUUO are better choices.

EBOX/2-46

C. .

All of these instructions save the flags and PC, a requirement when entering the device service routine.
If the instruction at 40 + 2n is a BLIQ(~ction, a specified number of transfers are performed, one
transfer at a time, each time returning to the interrupted program or to a higher level subroutine. On
the last transfer, the return to the interrupted program is "NOT SKIPPED" and an instruction is
fetched from 41 + 2n. In a similar fashion, if 40 + 2n contains a SKIP class instruction; when'the skip
condition is satisfied, a return to the interrupted program takes place. If the skip is not satisfied, the
instruction in 41 + 2n is executed instead of the return. The API function generated by the Massbus
controller is always a function code of 2 in bits 3-5; this implies a dispatch to the physical address
\ provided in the API function word. The dispatch is into the device handler for the Massbus devices.
The type of API function requested varies with the device or controller responding.
It is possible for the processor to generate a program request for an interrupt on any of the seven
channels. This permits the processor to carry out the highly time-sensitive portion of the interrupt
""" ~esponse, and to then create for itself a low priority interrupt to call for the deferred servicing of the
~ss time-sensitive portion at a less pressing time.

(

2.6.1 Duration of Uninterruptable Intervals
Such an interrupt system is of little value if the CPU can remain in an uninterruptable state for any
significant period of time. Under normal operating conditions, the longest uninterruptable interval
must be kept short. In addition, no malfunctioning peripheral hardware or software can be allowed to
"hang up" the CPU in a noninterruptable state.
2.6.2 Interruptable Instructions
To ensure that the longest uninterruptable interval that the EBox may experience in normal operation
is short, some long instructions have been designed so that they may be interrupted during execution.
First, all instructions are interruptable at indirect references during the effective address calculation.
Second, instructions that consist of two parts may be interrupted between the two parts, a PC flag
being set to record this for later, when only the second part will be done. Third, iterative instructions,
such as BLT, may be interrupted at any point, as an AC pointer defining work still to be done is beng
updated continually.

-92.6.3
/
\.

General Interrupt Sequencing
The mechanism for handling the various levels of interrupt priority in the hardware, and the relation
between this mechanism and the device subroutine call and return sequence as it might occur in practice are shown in Figure 2-41. Three channels are armed by setting their PIOtJ" flags. Channel 2 has
highest priority, followed by channel 3, and finally by channel 4. Note that the e~cution of a CONO
PI instruction caused the PION flags to set. Three separate interrupts occur simultaneously on channels 2, 3, and 4. The priority network is shown arbitrating the three priorities. The lowest channel
(highest priority) is serviced, provided it is of higher priority than the current level.

In this example, all three channels are requesting and no channels are currently holding interrupts;
thus, the channel with the lowest number is selected. As a result of the arbitration, the selected channel
number is combined with the appropriate constant to form the address 44[40+2X (2)]. In Figure 2-41,
the device subroutine is entered by fetching and executing the instruction in EPT location 44, which in
this instance is a JSR. The request is not cleared until the program issues CONO, DEV. Notice during
the entire service routine (in this example), the requests on channels 3 and 4 are waiting for the processor. The last instruction to be executed in the device subroutine is a JEN (JRST 12); this restores the
flags saved by the JSR instruction executed in 40 + 2n and dismisses the interrupt on channel 2, which
is holding off channels 3 and 4.

{
EBOX/2-47

CONO PI

PION 2 (ARMED)

PION 3 (ARMED)

~ON 4 (ARMED)

PIREQ 2 (WAITING)

•

~ IREO 4 (WAITING)

PI HOLD 2 (ACTIVE)

PI HOLD

PIREO 3 (WAITING)

(

DE V REO'S
2,3,4

3 (ACTIVE)

DISMISS
CONO

~ HOLD 4 (ACTIVE)

"'HO LD
THU S
DISM ISS

CONO
DISMISS

PRI NET (ARBITRATION)

iCH 2,3,4

CH 3,4

Ji R

JR~TF

BL KO
DISMIS SES

(

40+2NIIIDEV
SERV ROUTINE

DEV SUBR CH 2

MUUO

JRSTF

DEV SUBR CH 3

DEV SUBR CH 4

(

j- SINGLE
INSTR
MAIN PROGRAM

I\------..J
NOTE:
ASSUME 40+2N, 41+2N TYPE INTERRUPTS.
CH#2 -44,45
CH#3-46,47
CH#4 -50, 51
10-1611

Figure 2-41

Basic Interrupt Sequencing

2.6.4 Interrupt Dialogue
The handling of the EBus dialogue and processor bus requests during I/O instruction execution and
priority interrupts is provided by the Priority Interrupt Board, which comprises the necessary inter-~acing logic, control logic, and registers. Initially (Figure 2-42), assume that the appropriate PION
flags have been set on the PI Board and it is now capable of accepting interrupts. For this example, the
DTE20 will generate an mterrupt fOJ a byte 0Ldata. The drawing is divided into three sections: EBox,
control activity., and DTE20. The control activIty consists of control action taken by either the EBox
or the DTE20, as appropriate.
EBOX/2-48

CO:\~it:'lOl

E 8UX

,l\C'ff';ltrl"

DYE 20

//?'"'------I ~\rf E F; r~Al ~"'~--."" .."\

\, r:
,f

' '-.-Ji
II

I)TE 20

!NT~rqNp.t

PROe

kc·_ _ _

.~!

f"~

)
/

~_~-=

10-1'51:?

Dialogue

The DTE20 asserts one of its interrupt lines P\.,l-7; this level enters the PI Board where, as indicated, it
is arbitrated with any other incoming requests and any holding interrupts. The PI Board now commences a dialogue between all candidates on the selected interrupt channel. The selected channel
_ number is encoded in controller select (CS) lines 04-06. The function "PI SERVED" is encoded in
function (F) lines 00-02. These signals are placed on the EBus and 200 ns later the PI Board asserts the
signal DEMAND. This signal instructs the device (DTE20) to place its physical controller number on
a prespecified bit position of the EBus (bit positions 8-11). Each controller, therefore (including the
I/O bus adapter, bit position 15, disks or drums, bit positions 0-7), on the selected channel does the
same. Approximately 400 ns "later, the EBox drops DEMAND; nowever, the controller select and
function lines do not change for an additional 150 ns after DEMAND is removed. The physical
controller numbers received by the EBox over th.e EBus are arbitrated in much the same way as the
channel priorities. An exception is the ARP, which is an internal KLlO device, and does not fall into
~ quite the same type of scheme, i.e., it does not place a physical number on the EBus; obviously this is
"not necessary because it is already within the EBox. Rather, it provides a physical number directory on
the board. This device vies with the device that is selected on the basis of physical number highest
priority (Figure 2-40). Basically, the lower the numeric value of the EBus bit position onto which the
device is hardwired to place its physical number, the higher the priority of that bit. The highest physical number priority, therefore, is given to bit position 0, and the next to bit 1, and so on. The highest
priority physical number (in this example only) is assumed to be that of the DTE20 (one of four such
possible Unibus controllers on the EBus).
The PI Board now asserts the enco,~d phY§~1 number of the selected controller (DTE20) in controller select (CS) lines 00-03,., the interrupting channel number encoded in CS lines 04-06, and the
function "PI ADDRESS IN" is encoded in function lines (F) 00-02. Again, the EBox waits a period of
200 ns and then asserts DEMAND. At this point only, one controller has been selected; it compares its
physical number (hardwired on its backplane) to the number received on EBus bits 00-03. Upon
determining that it is the selected controller, the DTE20 places the required API interrupt function
onto the EBus data lines and asserts ACKNOWLEDGE and TRANSFER to the EBox. The
ACKN.0trL!DGE signal causes the I/O bus adapter to ignore the function code "PI ADDRESS
IN.'' In tea sence of ACKNOWLEDGE, PI ADDRESS IN would enable the I/O bus adapter to
send its API function to the EBox, because no decoding and comparison logic exists in the adapter.
This logic does exist in the DTE20 and other devices. The TRANSFER signal specifies to the EBox
that the appropriate device has responded, and alerts the EBox that an interrupt is set up and pending.
If the API function is sent during _!! DTE20 to lO byte transfer, this could specify that the EBox
perform aDA T AI function to the DTE20; in this way, a byte of data is picked up as indicated in
Figure 2-40.

~he case of DTE20 byte transfer is somewhat unique in that the DTE20 holds onto the EBus until the
EBox transmits the appropriate function, in this case DATAl encoded in function select lines 00-02 (at
this time CSOO-06 = 0). The byte is picked up by the EBox, and the DTE20 generates ACKNOWLEDGE and TRANSFER once again. This completes the operatiora Note that ACKNOWLEDGE
informs the I/O bus adapter not to respond to the functions being carried out(Because the requests on
channels 3 and 4 have been pendihg during the service routine, when the interrupt that has been
holding on channel 2 is dismissed, the priority net arbitrates between channels 3 and 4 and selects 3 for
service. This generates the address 46 (40 + 2n), and this time the instruction is an MUUO. As with the
lSR during the execution of the MUUO, the request is transferred to the channel 3 hold flag. Note that
in the example, the request on channel 4 is still waiting for service. Finally, the lEN instruction at the
end of the channel 3 service routine restores the flags and priority interrupt system, dismissing the
interrupt on channel 3. In the same fashion as with the other interrupts, the priority net generates the

EBOX/2-50

(

address 50 (40 + 2n). In this case, however, location 50 contains a BLKO instruction, which cannot
save the flags or PC of the interrupted proc.ess. This type of instruction behaves in a special manner
when used in an interrupt location; the BLKO instruction performs a series of transfers to a specific
device; however, after each transfer, return is passed to the current PC value, whatever it is. This
continues until the last transfer is completed, when the instruction in EPT location 51 (41 + 2n) is
executed. This instruction should be of the type that saves the flags and PC, and will generally enter a
subroutine probably to set up a new block pointer, because the currenf one has been expended. Note
that in the beginning some main program, perhaps the monitor, was interrupted, and now control is
passed back to it.

2.7 BASIC MACHINE MODES INTRODUCTION
In general, the KLl 0 permits the operation of a number of different programs, all resident in the
machine simultaneously, without interference or undesired interaction among them whether due to an
inadvertent program bug or maliciousness. The operation of the machine is divided into two modes,
User mode and Exec mode, each with two submodes. User mode consists of Public mode and Concealed mode. Exec mode consists of Supervisor mode and Kernel mode. The machine mode structure
and hierarchy are illustrated in Figure 2-43.
I"

r - I
I
I
I

PUBlIC------*foo~----

-::L~U:;-

EXEC

~~=~xxxxXlI
LEG.END
K
S
C
-C

KERNEL
SUPERVISOR
CONCEALED
NON CONCEALED
10-1613

Figure 2-43

Mode Structure and Hierarchy

EBOXj2-51

Basically, the programs of individual users operate in Public User mode, where the program can have
access to one of two possible virtual address spaces. If KL 10 paging is in effect, the user has access to a
virtual address space of 256K words via an 18-bit virtual address, which may not be referred to by any
other user (without the cooperation of the monitor). If KIlO paging is turned on, the program has
access to a virtual address space of 256K addressed via a 18-bit virtual address, which as previously
pointed out cannot be referenced by any other user without the monitor's cooperation. All instructions
that do not compromise the integrity of the system are legal; this includes the following:
1.
2.
3.
4.
5.

The halt instruction (JRST 4)
Any instruction attempting to affect the PI system (JEN)
Any I/O instruction directed at devices with device select codes below 740
Any reference to the concealed address space except for fetching of a portal instruction
All illegal instructions or op codes.

The user's address space (when KLlO paging is in effect) is divided into 32 (decimal) sections; each
section contains 512 (decimal) pages and each page consists of 512 (decimal) words. The existence of
these pages is nominally invisible to the user program. However, the amount of physical address space
available is actually a number of these pages (at least one page), none of which need be contiguous
either in physical core or in the user's virtual address space, although it is desirable from a machine
standpoint to do so. Each of these pages can be designated public or writable by a 1 in bit 1 or 2,
respectively, in the page table word for the page. Pages that are not designated writable cause an
instruction, which attempts to write them, to trap to the monitor as a write protection violation page
failure. A program running in pages designated public is in Public mode. A program running in pages
not designated public is running in Concealed mode. Whether an instruction is performed from Public
or Concealed mode is determined by the Last Instruction Public bit of the PC word (bit 7). The Last
Instruction Public biUs copied from the Public bit of the page map word for the page from which the
instruction was fetched. An instruction in Public mode (that is, one performed with the Last Instruction Public bit a 1 in the PC word), which attempts to transfer to a location in a non public area not
containing any Portal instruction, or an instruction in Public mode which attempts to read, write, or
execute a location in a nonpublic area, traps to the monitor as a concealed violation page failure. A
Public mode program can only transfer to a Concealed mode program by transferring to locations that
contain Portal instructions. A Concealed mode program can read, write (if writing is allowed), execute,
or transfer to any user location designated pUblic. Concealed mode is provided to allow the loading of
a proprietary software package together with a user's program and data while preventing the user's
program from copying information discerning the structure of the proprietary software. This provides
protection of proprietary software without complicated protective overlay or transfer schemes
involving the monitor and allows direct interaction between user and software package with virtually
no overhead.

•

The monitor operates in Exec mode. It is responsible for scheduling users, allocating memory and
other facilities, servicing interrupts, and performing actual I/O. At any instant, the monitor has access
to an effective address space of up to 8192K (for KLlO paging mode) or 256K (for KIlO paging mode)
words and by overt action may address any portion of physical memory. The monitor can be divided
into two parts: a normally small part, which operates in Kernel mode and is resident, and a larger part,
which operates in User or Supervisor mode and may be swapped as necessary.

EBOX/2-52

(~'

The Kernel mode part of the monitor handles the PI system, performs the direct I/O for the system,
performs page management, and perfor~ all other functions that affect all users of the system. The
Supervisor mode part of the monitor performs the general management of the system (such as MUUO
handling and dispatch) functions which affect only one user at a time. The Supervisor mode and
Kernel mode of the monitor are analogous to the Public mode and Concealed mode of the user's
programs in that the Supervisor runs in that part of the Exec address space designated public and the
Kernel runs in that part of the Exec address space which is designated nonpublic; this simplifies illegal
reference detection logic. Each address from 20 through 337,777 is broken up into pages, but these
addresses can be made to refer to the same addresses in the physical memory space by making the
virtual page address equal to the physical address portion in the corresponding page table entry. The
entire Exec address space is broken into pages of 512 words which may be designated either accessable
or not access able, public or nonpublic, and writable or nonwritable and can be swapped out. An
instruction in Supervisor mode that attempts to write into a page which is not writable will trap as a
page failure. An instruction in Kernel mode may write into any location whether or not it is designated
public. An instruction in Supervisor mode (that is, one performed with the Last Instruction Public bit
a 1 in the PC word) that attempts to transfer to a location in an Exec nonpublic area not containing a
Portal instruction traps to the monitor as a page failure. An instruction in Supervisor mode that
attempts to read, write, or execute a location in an Exec nonpublic area traps to the monitor. In each
instance, the trap is a Kernel violation page failure. A Supervisor mode program can only transfer, i.e.,
jump to a Kernel mode program, by transferring to locations that contain Portal instructions (JRST
1).

A Supervisor mode program can also reach Kernel mode (or any other mode) by performing an
MUUO or other instruction that causes a trap, if the appropriate trap new PC word indicates that the
next instruction is in Kernel mode. A Kernel mode program can read, write, execute, or transfer to any
location designated public, i.e., in Supervisor mode; all instructions illegal in User mode are also illegal
in Supervisor mode.
The mode control logic consists of the following:
User Mode
Public Mode
User lOT
Private INSTR
Miscellaneous Combinational Logic
The mode control exerts a powerful influence over the disposition of the processor. It monitors
instruction fetches from Public mode to prevent illegal entry to either Concealed mode from User
Public mode OJ Kernel mode from Supervisor. In addition, it detects the fetch of a Portal instruction
and adjusts the state of the mode logic accordingly. The relationships between the various modes and
their transfer instructions are shown in Figure 2-44. In general, two instructions allow flags that affect
processor modes to be manipulated. These instructions are:
MUUO
JRST 2
Of the two, only the MUUO can cause transfers to any mode from any other mode. The JRST 1
(Portal 1) simply allows entry to a Private mode from a Public mode. Each time an instruction fetch is
specified and the reference is to a nonpublic page, a test for illegal entry must take place to maintain
integrity in the system.

EBOX/2-53

PUBLlC-O
PRIVATE INSTR-1
MUUO OR
JRST 1 (PORTAL)
PUBLlC-1
PRIVATE INSTR-0

JRST 2

PUBLIC (1)
USER-I
USER-1
PUBLIC (1)
PRIVATE INSTR-1

USER CAN CLEAR BY
JRST 2 BIT 6 (0), BUT
CAN NOT SET IT BY
PLACING BIT 6 (0) AND
ISSUING A JRST 2

USER (1)
PUBLlC-1
PRIVATE INSTR-0

(

BIT ASSIGNMENTS
CONTROL OF
USER MODE
USER lOT
PUBLIC MODE
PREVIOUS CONTEXT
10-1614

Figure 2-44

•

Mode Transfer

Referring to Figure 2-44, assume a User Public program has been started by a monitor routine that
performed a JRST 2 (ajump and restore flags). To place the processor in User Public mode, bits 7 and
5 of the flag's PC word must be set; this results in the setting of Public mode and user mode, respectively. The processor is now in User Public mode. Assume that the User executes some miscellaneous
instructions and then performs an instruction fetch from a nonpublic area. The following test takes
place: instruction fetch is decoded from the microinstruction MEM field or specified as a prefetch in
the DRAM A field. The ElM Interface asserts EBOX READ and loads the address into VMA. Note
that if a reference to a private address for a read or write of data is attempted, it page fails on the
attempted reference because PA.GE TEST PRIVATE is asserted. However, in this case, the fetch must
be allowed from the private address space. Its identity is checked in the EBox and, if it is not aJRST 1
(portal), a page failure occurs on the very next memory reference. This is implemented by delaying
generation of the signal that would cause a page failure to be generated by the MBox (P AG E ILLEGAL ENTRY), until the instruction fetch is completed. When the MBox responds with the level PAGE TABLE PUBLIC (PT PUBLIC), this signal with the MB response sets PRIVATE INSTRUCTION. This causes the generation of PAGE ILLEGAL ENTRY. If the instruction which is decoded
by the hardware is not a Portal, Public mode remains set maintaining PAGE ILLEGAL ENTRY,
which enables a page fault on the next MBox reference for whatever reason. If the instruction fetched
is a portal (JRST 1), then Public is cleared and the processor enters Concealed mode.

EBOX/2-54

(

All user references and concealed references are paged. The difference between the types of paged
references is that user paged references ar.e public while concealed references are nonpublic when
referencing the concealed address space and may be public when referencing the users address space.
Executive references are paged, this includes both Kernel and Supervisor references. Supervisor mode
programs must be capable of reading both User Public and User Concealed address spaces. To bypass
the portal mechanism normally necessary for any public program to reference a nonpublic program
area, a bypass exists, which is under control of the Kernel; when operational, the Supervisor is allowed
to read and possibly write the concealed area as necessary, remembering, of course, that the supervisor
is part of the operating system and it is performing job-related tasks within that context.
Normally a public program is only allowed to fetch an instruction from a non public area and this
instruction must be a portal (JRST 1) instruction; however, this is necessary for the supervisor to
perform its system tasks. Basically, the process for checking a User Public program's reference to a
concealed address is as follows. The mode is User Public and an instruction fetch begins. EBOX
REQUEST is issued to the MBox, together with the appropriate paging qualifiers and any other
appropriate signals. The MBox performs the necessary check of the page descriptor bits; then the state
of the Public bit in the page table is asserted over the EjM Interface where, together with signal MB
XFER and a signal indicating an instruction fetch is being performed, it is used to enable the setting of
Private instruction. If the Page Table Public bit is off, Private instruction is set on the clock occurring
concurrently with MBox response. PAGE ILLEGAL ENTRY is not asserted. The response given by
the MBox was given at the same time it placed the desired instruction onto the cache data lines; this
instruction is now in ARX. If the instruction is indeed a portal instruction (JRST 1), the Public mode
will be cleared. removing the PAGE ILLEGAL ENTRY signal. This procedure then has effected the
proper entry to Concealed mode. If the instruction was not a Portal, then the PAGE ILLEGAL
ENTRY signal will not be removed nor will Public be cleared, which constitutes an illegal state in the
EBox. On the very next MBox request by the EBox (providing VMA AC REF is false), a page fault
occurs and an appropriate code is placed in the EBus register in the MBox identifying the disposition
of this fault. This will shortly be followed by a trap to the operating system as a concealed violation
page failure. This same procedure is applied to a Supervisor reference to the Kernel address space, and
in this way the integrity of the system is protected from any unwarranted references. Figure 2-45 shows
a typical layout of the virtual address space for the various modes. The space shown is for KilO paging
mode (256K, made up of 512 pages numbered 0-777 octal). Any program can address locations 0-17
as these are in a fast memory block and are completely unrestricted (although the same addresses may
be in different blocks for different programs). The Public mode user program operates in the public
area, part of which may be write protected. The Public program cannot access any locations in the
concealed area, except to fetch instructions from prescribed entry points. The Concealed mode user
program has access to both the public and concealed areas, but it cannot alter any write protected
location whether public or concealed; fetching an instruction from the public area automatically
returns the processor to Public mode. The Supervisor mode program is confined within the paged area
of the address space. Part of the public area in this space may be write protected, but the program can
read information in the concealed area. It cannot, however, alter any location in a concealed area,
whether that area is write protected or not. Pages 340-377 constitute the per process area, which
contains information specific to individual users and whose mapping accompanies the user page map.
In other words, the physical memory corresponding to these virtual pages can be changed simply by
switching from one user to another, rather than the operating system changing its own page map. The
Kernel mode program can access all of the unpaged area without restriction and can reference all of
the accessible paged area both public and concealed, with the usual restriction that it cannot alter a
write protected area. As in the case of Concealed mode, fetching an instruction from a public area
•
returns control to Supervisor mode.

EBOXj2-55

EXECUTIVE MODE

USER MODE
CONCEALED

PUBLI C

0..--------.
FAST

MEMORY

SUPERVISOR

FAST MEMORY

PUBLIC
WRITEABLE

KERNEL

FAST MEMORY

PUBLIC
WRITEABLE

PAGED AND
AVAILABLE TO
THE RESIDENT
MONITOR

PUBLIC

PUB LIC

------

-------

CONCEALED

4001---------1

400

PUBLIC
WRITE
PROTECTED

CONCEALED
ENTRY POINTS

(

340

CONCEALED

400

PUBLIC
WRITE
PROTECTED

PUBLIC
WRITEABLE

CONCEALED
WRITE
PROTECTED

PUBLIC
WRITE
PROTECTED

CONCEALED
WRITEABLE

CONCEALED

CONCEALED
WRITE
PROTECTED

777 I..-_ _ _ _----J

777

777
10-1615

Figure 2:45 Typical Virtual Address Space Configuration
2.7.1 Mode Initialization - Private Instruction
When the KLlO system is powered up, the power control issues the signal CROBAR for approximately 5 seconds. This results in the generation of RESET, which causes LEAVE USER to be
asserted. LEAVE USER enables the clearing of USER, USER lOT, and PUBLIC and sets PRIVATE
INSTRUCTION. This action places the KLlO in Kernel mode. Referring to Figure 2-46, each time an
instruction is fetched from either Fast Memory or Core Memory (via MBox), the private instruction
recirculation path is broken (Figure 2-47).
EBOXj2-56

CROWBAR
GENERATE
LEAVE USER.
CLEAR: USER,
USER lOT AND
PUBLIC

"DATA FETCH
OR STORE"

YES

USER lOT· 1
KERNEL MODE
PREV CONTEXT
OPERATIONS MAY
BE PERFORMED

YES

•

YES

USER MODE PUBLIC

USER lOT MODE

101616

Figure 2-46

Mode Initialization

EBOXj2-57

10-1617

SiInplified

is fetcIH',:d

the

fWIn

:~p8ce (~.PUBUC

or th!\'; fnodf.!of the:
(FIguTe 2~

private in5tructkm is enabled to

machine is not

r~~'1

! INSTRUCTION
~~~

INST!~ FETCH~

~:FER ~;r--':h

--PUBLIC~~~,
,IJ

MB XFER

-.:::.r~

_ _ _ __

,,'/Ifj--

PAGE-.-~-·

- PUBLiC

JO - 1618

Figun:: 2·43

or written, the
is used with

Setting Private

redrculatil)rl leg
(with

previous ';;;OJ1text

to Public
together, these
access amy part the address space
mode, iHega! entry
1,(Jll;uUlrng Hags

C~umgnng

can change the

to a privileged

Because the

no significance,

rV!odiIC

of the machine. Thf;':se instructions

aH~

and

JRSTF.
As
submo;,:lces"

bits

and

various

to 'enter appropriate

Table 2-6 Flags Effecting Mode
Major Mode

Instruction being perfonned is MUUO,JRSTF (See Note)
Enable
PREVCONTXT

User lOT

Flag Bits
AR06

0
1

0
0

0
0
0
0

0
1
0
1

0
1
N/A
0
1
0
1

Effecting Modes
AR05
AR07

0
0
0
1
1
1
1

0
0
1
1
1
0
0

Exec Submodes
Super
Kernel
1
1
0
0
0
0
0

0
0
1
0
0
0
0

User Submodes
Concealed
Public

0
0
0
0
0
1
1

0
0
0
1
1
0
0

NOTE
A JRSTF may not clear user by placing bit 05 (0) but an MUUO may.

In addition, for Direct User I/O, bit 06 (USER lOT) is available to allow the running of privileged
user programs with paging in effect. This mode provides some protection against partially debugged
monitor routines, and permits running infrequently used device service routines as a user job. Direct
control by the user program of special devices is particularly important in real-time applications. A
special MUUO is available to enter USER lOT mode, but it is privileged because time-sharing is
effectively stopped while in this mode.
2.7.3 User Public Mode
Once the processor is in User Public Mode (Figure 2-49), the user program can freely read and write
data in the user public address space with the cooperation of the system. When demand paging is in
effect, each reference to a previously unreferenced page causes an access page fault. The operating
system page manager must assess the fault, obtain the page from mass storage, and build an entry in
the user's process table.

•

Assuming that the current user's process table (PAGE TABLE PART) is initially clear, the first reference causes a NOT IN CORE page fault (Figure 2-50). The EBox, upon detecting the PAGE FAIL
HOLD signal from the MBox, enters a microcode page fault handling routine that communicates the
failure to the operating system. Next, the page manager or a related routine requests the page from
mass storage. When the page is in core, the appropriate process table is constructed and the reference
by the user program may be tried once again (Figure 2-51) .
The MBox performs the reference to the process table; the use bits now reflect the following:
PAGE
PAGE
PAGE
PAGE

IS IN CORE A = 1
IS WRITABLE W = 1
IS PUBLIC P = 1
SHOULD BE CACHED C

EBOX/2-59

PUBliC

USER MODE
COf'JCEALED

10-151 S

Figure

PAGE
UBR

i1l

PROCESS TABLE BEFORE
USER REFERENCE

PAGE f1)

~
(/j

000

®
READ
ENTRY

•

EBOX REO' PAGE 1

CD
(/j

(/)

377
400

PAGE FAIL HOLD

ACCESS BIT'(/) PAGE NOT IN CORE
10-1620

Figure 2-50

User Mode Public Initial Reference

PAGE 1

,------- A P W S C

UBR

•

PROCESS TABLE AFTER
/ENTRY IS WRITTEN

"'---0--""T"'""-r-r-;--r:~"'~';"~.".r;~ 000
•
•

•

MBOX READS
OR WRITES
DATA AS
APPROPRIATE
EBOX REO' PAGE 1

®
RESPONSE
ACCESS BIT'1
}
WRITEABLE BIT' 1 NO PAGE FAI LURE
PUBLIC BIT "1
CACHE BIT' 1
10-1621

Figure
2-51
,

User Mode Public Second Reference

EBOX/2-61

The entry (one of eight half-word entries fetched) is written into the page table in the MBox, the MBox
then performs the data reference part of the request. This can involve reading or writing and depends
upon the type of EBox request. During the reference, PAGE ILLEGAL ENTRY was not asserted
because the reference made by the user p'rogram was to a public page and it was for an instruction.
2.7.3.1 Entry from User Public Mode to User Concealed - To correctly enter User Concealed mode,
the User Public program must execute a Portal instruction (Figure 2-49) from the concealed address
space. The EBox generates the EBox request and provides the MBox via VMA with the concealed
address. The MBox either finds the page entry and use bits in the MBox Page Table (hardware) or
performs a refill cycle to obtain it from core memory. Figure 2-52 shows the typical Concealed Page
Table format. Presumably, the entry is nonpublic and write protected, and mayor may not be cached.

111010~
l-

13 BITS
PHYSICAL PAGE
IB BITS

-I

10·1622

Figure 2-52 Typical Concealed Page Table Format (Half Table Entry)

The MBox asserts PT PUBLIC (0) and MBOX RESPONSE IN to the EBox. Referring to Figure 2-48,
MB XFER resulting from MBox response and -PUBLIC PAGE resulting from PT PUBLIC (0)
enables the setting of Private instruction. The instruction fetched by the MBox is in ARX at this time.
If it is a JRST 1 (Portal), its execution clears Public and the processor enters User Concealed mode. If
the instruction is anything else, Public remains set and the next MBox reference occurs with PAGE
ILLEG AL ENTRY true, PUBLIC PRIVATE INSTR (1); this causes a page failure.
2.7.3.2 Concealed Violation Data Reference - If a User Public program references the concealed
address space for read or write, PAGE TEST PRIVATE is asserted during the EBox request and
results in an immediate page fault. Page Test Private is a signal composing Public and -INSTR
FETCH.
2.7.4 Restoration of Programs by the Supervisor
The Supervisor portion of the operating system deals with those tasks which affect one job at a time. It
must, therefore, have the ability to restore various programs to an operational status, e.g., by executing
a JRST 2 instruction that picks up a PC word consisting of the appropriate flags in the left half and a
virtual PC in the tight half of the word.
2.7.4.1 Restoring a Concealed Program - The Supervisor may restore a concealed program providing
it also sets User. Referring to Figure 2-53, while executing a JRST 2 instruction, LOAD FLAGS is
derived from the presence in the magic number field of bit 04, and this together with -User (User is off
in Supervisor mode), and AD bit 05 (which will set User) generated CLR PUBLIC. Thus, on the next
clock pulse, Public clears and User sets, restoring Concealed mode. Figure 2-54 shows the necessary
conditions. Note that performing a JRST 2 cannot generate Leave User, unless the processor is in
Kernel mode.

EBOX/2-62

(

•
SUPERVISOR
MODE

YES

SEE NOTE 1

NO
PRIVATE
INSTR-1
ILL ENTRY-l

YES

t'I1

"JRSTF"

AR05(1)

~
I
0'\

IoU

~UPERVISOJ

NEXT MBOX REF
WILL PAGE FAIL
WILL OCCUR ON
THIS REF.

RESTORES
USER MODE

CLEAR PUBLIC
ILL ENTRY-O
PRIVATE
INSTR-l

KERNEL MODE

AR07(1)

AR07(1) & AR06(1)

l
NOTE 1:
IF THE SUPERVISOR FETCHES
AN MUUO. MODE CHANGES
ACCORDING TO FLAGS.

USER MODE
PUBLIC

1
USER MODE
CONCEALED

USER MODE
PUBLIC (lOT)

AR06(1)

1
USER MODE
CONCEALED (lOT)

10-1623

Figure 2-53

Supervisor Mode Functional Flow

SPEC FUiG

en.

ST,~RT

OR MUUO

,JSR

JRST 2 FROM
~(ERNEL 11i10DE:
10-162<.1

User

1,7A.2
a KelrrieH Program .- The
is somewhat different in
Public.

Th~

must
JRST

1:.1

entry
"while not setting
it is given in KJ::rnei

SUPEFiVI50R
,~DD RE 5S
SP,i\CE

JRST 2,@8

'-8

FLAGS, C

10 -1625

Figure

2~55

Restoring KernEl.!

2,7 Ai.3 Restoring a
Public PmgnuI! JRST 2,
sets User. This is
Public set. The

SPEC/

EBOX/2-64

2.7.4.4 Saving Flags and Leaving User - It is not generally known at just what moment an interrupt
will occur with respect to execution of a given instruction. The microprogram governs the handling of
interrupts by looking for interrupts only~at certain times. In general, an interrupt is sampled for
between each instruction and during certain classes of instructions. The following classes of instructions can be interrupted:
Byte Instructions
Block Transfer Instruction
I nput/Output Instructions
In addition, for any instruction, an interrupt is sampled during the portion of the microprogram that
performs indirect addressing (INDRCT). An interrupt has higher priority than a Page Fault and thus,
upon entry to the Page Failure microroutine, an interrupt condition is tested for; if found, a dispatch
to the micro routine for interrupt handling is given.
When an interrupt occurs and the PI logic has completed the handshake, it informs the EBox by
asserting a signal PI READY. This results in the microprogram generating a skip to a microinstruction
that asserts SPEC/SET PI CYCLE. As a result, Kernel cycle (normally false as long as PI CYCLE is
clear) sets, and MCL VMA PUBLIC is disabled. This is necessary to disable the MCL PAGE ILLEGAL ENTRY signal when PI CYCLE sets because the interrupt instruction, which will be fetched
from a Kernel address, must not generate a page fault.
When the interrupt instruction is being fetched, User and Public may be set, or Public alone may be
set. In the last instance, a page fault would result if some action were not taken to prevent it. This is
why MCL PAG E ILLEGAL ENTRY is disabled (by setting PI CYCLE). At the time of the interrupt,
the state of the current user ACs is unknown. The instruction in 40 + 2n, therefore, must not disturb
the ACs in any way while transferring the flags and PC to the Kernel mode subroutine. Therefore, JSR
is a likely instruction for use in 40 + 2n. The JSR instruction causes the flags and current PC to be
stored in the effective address of the JSR instruction and then enters the subroutine by performing an
instruction fetch from E + 1. After calculating the effective address for the JSR instruction, the microprogram performs a write test which, if successful, is followed by a branch via the DRAM J field to the
executor. Now the flags and PC are loaded to be copied into the AR for storage and are then disabled.
The microinstruction asserts SPEC FLAG CTL; this with PI CYCLE generates LEAVE USER, which
detaches the feedback path for User, User lOT, and Public. In addition, if User were set, User lOT
would be set at this time and represent "Previous Context User." This is an indicator to the hardware
that previous context references must be in User mode. In any event, the processor enters Kernel mode
and begins to handle the interrupt.
2.7.4.5 User Concealed - This mode is useful for running certain proprietary programs in User mode
without allowing the user to discern the composition of the concealed program. For example, assume a
user has developed a program that performs circuit analysis. The user is a time-sharing house and
desires that this program be available to users for execution only, that is, the user must not be able to
read or write into this program.
I n some computer systems~ complex overlays in core memory are necessary to assure concealment of
the program from its users. In the KLlO, this program has been solved by creating two submodes from
User mode, each with separate powers and each separate from the other. Both modes, however, run
with User on. Figure 2-56 indicates the hierarchial structure present in the KLlO processor. The User
Public program can only transfer to a concealed program at a selected entry called a Portal. The
instruction fetched must be a Portal instruction (JRST 1). The concealed program can read or write
data to the Public area. Figure 2-57 is the Concealed mode functional flow diagram.

EBOX/2-65

I
~

WECT~-i-,--~-

l_,
__ J. _ ._,_, __ .~i
I

j nJ3TRu~T'':'.Nll_

MCIUC

PUE,LIC AI',JD USER
CLEI',," ,PRIVATE

hEfiNEL.

I-

1rl
rJ)

lIJ

rJ)

>
lIJ
a:

lIJ

TRANSFER TO
EXEC MODE

MUUO, E
OLD PC WORD
PROCESSOR ENTERS ~--------l
NEW PC WORD

•

READS THIS

CWSX+VMA
PREY SECT

ARMM 13-\7 IS NORMALLY=PCI3-17 BUT
FOR PXCT OR EXEC PREY CONTEXT OPS
ARMM= VMA PREY SEC 13-17 AND
ARMM 12 = CWSX
10-1629

Figure 2-59

Typical VMA 13-17 Manipulations

EBOXj2-69

For these process table references the EBox supplies valid addressing information only on VMA bits
27-35. The MBox replaces VMA 13-26 with the PMA mixer 14-26 to generate a proper physical
~,
address.

2.9 DATA PATHS
The specific address and data paths in the EBox are illustrated in Figure 2-60.
The functional elements in the address path between the VMA at the MBoxjEBox Interface and the
primitive address source involved in forming the virtual addresses are:
Virtual Memory Address Register (VMA)
VMA Held or PC Mixer
VMA Held Register
VMA Previous Section
VMA Mixer'
VMA Adder (VMA AD)
SCD TRAP Mixer
ADDER (AD)
Arithmetic Register Exten~lion (ARXML)
Arithmetic Register (AR)
Program Counter (PC)
Microinstruction Number Field
Other Miscellaneous EBox Registers
The appropriate virtual address is formed by the VMA under explicit control of the VMA control and
the microprogram.

2.9.1 Virtual Memory Address Register
The VMA is loaded during an EBox request and remains latched until the MBox responds (Figure 261). The VMA is a 23-bit register that accepts input from a double mixer arrangement. Thus, the
incrementing or decrementing is performed in the register itself. When both VMA SEL 2 and 1 are
clear, the lower mixer is enabled into VMA. The level VMA ~ AD selects AD as input. The default is
VMA AD as input.

~In general,

•

the VMA AD contains one of the following:

PC (18-35)
PC+ 1 (18-35) + (1)
PC+2 (18-35) + (2)
Process Table' Address (27-35)
Fast Memory Address (32-35)
The AD contains one of the following:
Effective Address
Word Address
Some Special Address

@
,

The VMA Held register is loaded during each MBox memory request [MEM 02 (1)]. The left-most 12
bits of VMA Held are loaded with the request qualifiers, type of paging, context of the reference, and
various other signals asserted during the request. The right-most 23 bits of VMA are preserved in
VMA Held right. The contents of VMA Held are used during KL Paging mode to buffer the request
state while the page fault handler sets up an MBox Page Refill cycle. This operation is generally
described in Subsection 1.2.4.2, KL Style Paging and is described later in greater detail.
EBOXj2-70

CRAM
SH-ARMM

SIGNALS

SHIFT

AR<

SHIFT INH
000 PARITY

ARSWAP

r-------------------,
CURRENT BLOCK

r-------------------~

-,.--------.-10

•

1
1

1
1
1
1

CRAMSCAOZ
SCAD 51

:
I

SH-ARMM

1
I ________________
AO
L

I
I

CRAM
SH-ARMM SEU

1L ______ _

1
I
1
I
I
I
I

1
I
1

CRAM

~~U

~~~ ~~:~

SCAD

r----------------~
I

1
1
1

- CLK HMO~7~:

r-------------------------------------l
1

1
1
1

_~~I2..J

---------, :
I

II~__~~~L_~========~~~~

I
L L------------------------------~~~J

------------------------,

I
N
T

R
F

1
1

MOSEL 2

A
C

r-------- -- - - - - ---;M::E:;;o7p";" I
I
1

I
1
1

WROTE

- - - - - =F':;M~E¥o-iPc=-ll'

I
I

1001211

IIV... "."

1L. _______
M8530 I
:.l1
,OAO

SCD flAGS VMA flAGS

mv CONTEXT

-F

I
I VMA 17-26

r----------.J

I
:

MO FUNCTION
HOLD

PR;V

SEd

-CRAMADADIS-<¥--~::_--',_--+_----_l_-£2~~!L,;r-__:=:_-"\

SHifT LEFT

S'
AO

CR"IroIADASEL2

•

CRAM ADA SEL I

-'~I-~I--jl---ir-~

SHIFT RIGHT *2
OIV ISH LEfTl
MUL(SHRT*ZI
RESET (II

VMA SEL 2 _ l ' - - - - . . L - - . = A A
VMA S[L I

- L_ _ _-y-_-l.:.!!2!.21

VMASEL2 VMASELI

1
1

LM~5::_____ _ _ _ _ _ _ _ _ _ _

MOS£L I

CRAM CONO

MO." MO.

° .,°,
, .,
,, Nt
0

-0

.. '"..

MO
SEC
00

° 00 "
°,, 00 '000
,, 00"" 00
" 00
°,, 00 00"
0

° 00"

00
00

NOTE:
ARSHIFT (fill lin I.n with ARIII

fUNC
ViolA _VMA
VMA _ VMA+I
VMA _VMA-I
VMA LOAD

--------------------------------------------------~~~~
r----------------------------------,
I
"
--------------~~~

I
I
I
I

CRAM SH-ARMMSEL 2

ARMM

CRAMSH-ARMMSELI,,'
PC
ARSIGN
SMEAR

13~17

t :s'------

VMA PftEV
13-17

1
I
I
I
I

L __ ~---------------------------~~~~

Figure 2-60 EBox Data and Address Paths
EBOXj2-71

17
VMA

O-LOAD
I-INC
2- DEC
3-HOLD

SPECIAL
CONTROL
SEE FIG.

2-49

VMA AD

AD
10-1630

Figure 2-61

VMA Inputs

The first three selections (Subsection 3.2.1) enable the output of VMA into the VMA register for any
of the following select codes:
VMA S EL 2 (0) and VMA S EL 1 (1) - Increment
VMA S EL 2 (1) and VMA S EL 1 (0) - Decrement
VMA SEL 2 (1) and VMA SEL 1 (1) - Hold
2.9.2 Program Counting
The PC is normally loaded from VMA at NICOND Dispatch, except when PI Cycle is true; this
prevents alteration of PC during priority interrupt handling. When the processor is ready to fetch an
instruction in sequence, the incremented PC address is supplied to VMA via the VMA AD. The VMA
then supplies the address to PC. Thus, program counting is effected by the loop of PC, VMA AD,
VMA, and back to the PC (Figure 2-62).
Wihen a skip condition is satisfied, this loop is used to advance the PC during the instruction execution
cycle. The PC, therefore, is automatically updated at NICOND time and if the skip is satisfied, it is
updated a second time, pointing PC to the location two beyond the current location.
The PC output is available to the AD for saving a return address in a subroutine call JRST, MUUO,
or similar instruction. Generally, the address saved should be for a return to the next instruction, i.e.,
the instruction that would have been performed had the call or jump not occurred. However, if an
instruction is terminated because of a page fault or interrupt, the current address must be saved for a
later return to the beginning of the interrupted instruction.
2.9.3 Loading PC
New addresses are always supplied to PC via the VMA regardless of the point of origin. The update of
the PC or its inhibition is controlled by the microprogram. The following conditions cause PC+ 1 INH
to set, inhibiting the update of PC via VMA AD:
Priority Interrupts - Setting PI Cycle
Console Instruction Execution
Halting the Processor - Halted
Performing the Trap instruction in process table location 421, 422, 423

EBOXj2-72

(

CRAM
AD FUNC

A+B

-PC+ 1 INH
CRAM VMA=PC

+1
10-1631

Figure 2-62

Program Count Loop

The PC is loaded at NICOND Dispatch time (Figure 2-63), providing PI CYCLE is clear. In addition,
the special field function LOAD PC may also be used to load PC from VMA. During page fault
handling, the SPEC/LOAD PC function is used to save the failing virtual address (VMA) in PC while
saving the current PC value in ARX. Basically, the MBox builds a page fault status word in its EBus
register. The physical page number is stored in bits 14-26 of this word. The EBox page fault handler
must replace this address with the virtual page number in VMA 14-26 and then store the updated page
fault word in user process table location 500. The operation is as follows:

Simplified Microprogram Steps Ref PF Handler
1.

ARX +-- old PC, PC +-- failing VMA
AR +--EBus Register; PF word

BRX+--ARX; old PC+-- ARX AR; PF WORD
AR+-- PC; failing VMA

At this .time, the AR and ARX are Ref PF Handler shifted in such a way as to discard the
physical page number and align the proper virtual page number in AR 14-26.

A second case is where SPEC/LOAD PC is used while halting the EBox. In this case, either a Console
Halt was issued via the 10-11 interface, or a Halt instruction was performed in either user lOT mode or
Kernel mode. The VMA is loaded with the current PC and the PC is loaded with the effective address
currently held in VMA. At the time of the halt, the PC value in VMA points to an address one greater
than the location containing the Halt and the PC contains E. PC+ 1 INHIBIT is set to prevent premature incrementation of the jump address now in PC.

EBOXj2-73

DISP/NICOND

SPEC/LOAD PC

VMA

PI
CYCLE

CON PC+lINH
PC+1
INH
CON CLOCK

(Il

VMA SEL2'PC+1

SCDTRAP MIX35
"TO VMA AD B INPUT"

#02{11

COND/SPEC INSTR

141-------- MICRO

INSTRUCTION

---------t
..1
10-1632

Figure 2-63

PC Loading or Inhibit

2.9.4 General Data Path Organization
The data path (Figure 2-60) is divided into four major areas, as listed in Table 2-8.
1.

2.
3.
4.

Fast Memory and Fast Memory Address Logic
Virtual Memory Address, Program Counter and related logic; 23- and 18-bit logic
Arithmetic logic - 36-bit logic
Instruction register - 12-bit logic

All of these areas derive control functions from specific fields in the microinstruction .

•

2.9.5 General Data Path Mixer Selection
The microinstruction or microword consists of 75 bits including parity. It is organized into variable
length fields that are used to control the data path and control sections of the EBox. In the following
pages each field is described functionally in terms of the particular logic with which it is associated.
2.9.5.1 AD Field - This field consists of six bits and is used to control the main adder (AD and
ADX), that is constructed of type 10181 Arithmetic Logic Units. Table 2-9 lists the ALU functions.
The low-order four bits specify one of 16 10 functions. These functions are Boolean or Arithmetic as a
function of bit 1 (the mode bit). If bit 1 is a one, the functions are Boolean; if zero, the functions are
Arithmetic. Bit 0 is the carry in, when true it adds + 1 to any Arithmetic function.

EBOX/2-74

Table 2-8

Data and Address Path Breakdown
Micro field

Major Area
Fast Memory

FMADR Field
COND/FM Write

Virtual Memory Addressing

VMA Field
COND/VMA +- #
+ X (see Note)
COND/VMA DEC
COND/VMA INC

VMAHELD

COND/LDVMA HELD

PC FLAGS (PC LEFT)

COND/AD Flags
COND/PCF +- #
SPEC/LOAD PC
DISP/NICOND with PI Cycle (0)

PC (RIGHT)

COND/LOAD IR

Shift Count and Auxiliary Arithmetic 10-Bit Logic

SCAD Field
SCADA Field
SCADB Field
SC Field
FE Field

Arithmetic 36-Bit Logic and 72-Bit Logic

AD Field
ADA Field
ADB Field
AR Field
ARX Field
BR Field
BRX Field
MQ Field
SH Field
ARMM Field

72-Bit Operations Require SPEC/AD Long

NOTE
X is a constant selected by the low-order three bits of the

COND, code.

EBOX/2-75

Table 2-9

ALU Functions

BOOLEAN·
CIN

a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a

BOOLEAN

FUNCTION

CARRIES

a
a
a
a
a
a
a
a

a
a
a
a

a
a

A
AYB
AYB

A
A+(A8)
A+(AB)
2*A
AYB
(AB)+(AYB)
A+B
A+(AVB)
AVB
A-B-l
(AYS) + (A B)
A + (AYB)

a
1

a
a

a
a
a
a
1

AS
I3"

EQY
AYB
AB
XOR
B
AYB

a
1

a
a

-1

A-S

AB
A

A13-l
AB-l
A-I

ARITHMETIC
CIN

a
a
a
a
a
a
a
a
a
a
a'
a
a
a
a
a

a
a
a
a
a
a
a
a

a
a
a
a
a
a
a
a
a
a
a
a
a
a
a

ARITHMETIC
S2

FUNCTION

CARRIES

a
a
a

A
A + (AB)
A + (AB)

A
A + (A"if)
A + (AB)

2*A
AYB
(AB) + (AYB)
A+B
A + (AYB)
AYB
A-B-l
(AYE) + (AB)
A + (AYB)
-1
AB -1
AB -1
A-I

2*A
AYB
(AB) + (AYB)
A+B
A + (AYB)
AYB
A-B-1
(AY-if) + (AB)
A + (AYB)

a
1

a
a
1

a
a
a
a

a
a

a
1

a
a

a
1

-I

AB -1
AB-1
A-I

._--------------

NOTE: If CIN is true, add +1 to the given arithmetic function. Carry out is true if the adder.
extended left, would need carry in to generate the correct function.
Carry Out is not affected by the mode (i.e., BOOLEAN FlINCfIONS give the same
carry as the ARITHMETIC FlINCfIONS).

EBOXj2-76

F or Boolean functions, the carry in can cause a carry out if the corresponding Arithmetic function for
the same S-bits would have produced a carry given the appropriate inputs. For example, assume the
A D function to be performed is A and the ~ input equals 777777,777777. The Boolean function A
performs the I s complement of the A input, which yields a result of 000000,000000. The corresponding
Arithmetic function is A and thus, if carry is true, this yields A + 1. Using the existing A input
777777,777777 + 1 gives a sum of 000000,000000 and a carry. If the Boolean function A is given and
carry in is true, assuming the same A input as above, the function out is 000000,000000 and a carry is
generated.
The 10181 may be thought of as concurrently performing the Arithmetic operation specified and the
Boolean operation specified; the sum, however, is not affected when the Boolean functions are implemented, yet the state of Carry Generate and Carry Propagate will reflect the Arithmetic result that
would have formed the sum.
MCI0181 Arithmetic Logic Unit Description
Figure 2-64 is an overview diagram of the ALU logic. Table 2-10 lists the ALU functions, with carry.
GEN ";A'{S4 B + SsB)
PROP

=A+

SIB

S2B

Signals GEN and PROP are used in each digit to generate the output signal Fn. In the logic mode,
carries are inhibited on the output stage, and the logic function F is given by
F GEN V PROP (XOR)
(The output function is the Exclusive-Or of the two internal signals GEN and PROP).
When adding two n umbers, in the absence of a CARRY IN, the Exclusive-Or function is the function
required. A CARRY IN signal always complements this in this circuitry by controlling the final Exclusive-Or on the output stage.

ARITH MODE L

LOGIC LOW
CARRY HIGH

-----~:f--_......,

CARRY IN L - - - - - - - Q

~-------------~

B---.------.(J

----+---.(J

ALL SIGNALS LOW = TRUE
GEN=A(S4 B + S s B1
PROP=A+S18+S2B
10-1633

Figure 2-64

AL U Overview

EBOXj2-77

Table 2-10

ALU Functions With Carry
~

Cooe
S,

0
0
0
0
0
0
0
0
I

0
0
0
0

0
0
I
I
0
0

0
I
0
I
0

I
i

1
I
I
I
0

1
1
0

0
I

1
1

0
0
O~
I
1
1

]

I
I
I

1
0
I

0
1
0
1
0

0
0
1

GEN'

PROP

Logic Fn

Arithmetic
CARRY LOW
CARRY HIGH

A
A
A
A
AVB
AVB
AVB
AVB
AV'S
AVS
AVB
AV-S
1
1

A
Av's

A
A+AB
A+AB
2*A
AVB
AB+(AVB)
A+B
A+(AVB)
AVB
A B I
AB+(AVB)
A+(AV"t3)
I

AS
AB
A
0
AB
AB
A
0
AS
AB
A
0
AS
AB
A

1
1

0
1

AVB
1
--

AB
B
EQV
AVB
AB
AVB
B
AVB
0
AS
All
A

All I
Al

AB
A

All

A+ ]
A+AB+]
A+AB+]
2*A+!
AVB+J
Ai3+( AVB)+ I
A+B+I
A+(AVB)+ I
AV-S+l
A B
AB+(AVB)+l
A+(AV-B)+l
0

NOTE
All signals high true except GEN and PROP,

The MClO181 carries out an addition by converting the two numbers at A and B to two alternative
signals GEN and PROP, given by
GEN
PROP

=
=

AB
A+B

(Ss = 1, S4 = 0)
(SI = 1, S2 = 0)

For example:

then

•

A
B
AB
A+B
SUM

=
=
=
=
=

0011
0101
0001
0111
1000

T
7

(GEN)'
(PROP)

Adding any two numbers A and B is equivalent to adding the two functions AB and A + B. However,
the advantages of the second part are that one (AB) shows when carries should be generated, while the
other (A + B) shows when carries should be propagated. The final sum is the XOR of the two numbers
(AB and A + B), complemented by the CARRY IN signal.
GEN
PROP

= A(SsB + S4B)

+ S, +S2B

These two equations show that PROP is generated whenever A is true, which is a requirement for
GEN to be true, i.e., GEN implies PROP, and thus whenever GEN is a one, PROP is also a one, and
thus G EN plus PROP must generate a carry.

EBOX/2-78

(

G EN is sufficient indication of carry generation. Similarly, PROP is sufficient indication of carry
propagate.

High Logic
Actually, the circuit was designed to promote understanding for low logic, and the descriptions and
tables given in the literature are far clearer for this case.
Although the circuit does give the correct answers for high logic, the circuit does operate on the low
signals. Th us, an addition can be considered as an addition of the zeros, with carry generated from the
addition of two zeros, and propagated, as before, by the XOR of the two numbers.

001 1 0

01010

1001 I

XOR

I 000 1

GEN

I 1 10 1

PROP

COUT +-

10000

Cin (low)

COUT +-

1 0001

Carry (high)

The correct answer, therefore, occurs when Cin is asserted to the least significant bit. This can be
viewed in two ways:
I.

Carry is asserted high. In this case, the function considered above is Fn = A plus B and carry
input adds a one. This is simple, but GEN and PROP meanings become obscure (especially
when passed through the LOOK-AHEAD CARRY block).
Generate = > (G = High and P
Propagate = > (G = High)

2.
/

•

= High)

Carry is asserted low. In this case, the above function is Fn - A plus B plus 1, and the carry
input subtracts a one, but hardware is simple to foliow:
Generate = > (G = Low)
Propagate = > (P = Low)

To functionally de~cribe the use of the various Boolean and Arithmetic functions, it is first necessary to
define two other microinstruction fields which are used to enable various data to the AD A and B
inputs. The first field is ADA, a 3-bit field. ADA can select the inputs shown in Figure 2-65 .

FIELb CODES

INPUT
AR*4
ARX

VMA OR PC
AR*4 ARX MO VMA
OR PC
10-1635

Figure 2-65

ADA Example

EBOXj2-79

is i\DB, a

2~bit

FIELD CODEs

can
nWUT

BR
2

:2
8R

JJlI'!\OR a~so :::0!"\trol~, ADXB,
£,e l; ,2\08 Fif.!1j;:J,

various operatiom;
guarai!1itei~

might be performed. u:!iln.g
and
is made that the operatio:rJ§ Hh~stl'ated are used in

"'" OHHOl, 10
=0
The
A
13 corrupllement of the
is 767676,676767.
at
tirne the
In is
corresponding carries function i§ A

()utpl1li
~!{amplie

~ Function 24
I nidal
ARX """ 777777,
PM = 777777,777776
ADA Field::: 2
.AJJB
"'" 0

50-1536

ADA, Fidd C
id~,"DjB

.Field 2

Figure 2-68

Functinn

AIf

logical AND
is
out1Jiut is 000000,

the vahu~ in BR
Referring to Table 2-9, the;

and,
the existing
it can be demonstrated lJ.1!it a
any two values H')3UItS a nonzero sum, Tfule
if the A.I'-JD

/\ 000765,100070

000000100000
-:~

777777

00000 077777

Function 37
ARX ""

'V'vV"JV"""",vv

EBOXj2-81

is
GENEnt'!TED

FUl.1Gtl0l1

2-70).
is .A ""' 1.

10-1639

2-70

maill1
Referring to
and 'VIvlA, HELD or PC(3). The
high-order bit of the

in a similar fashion to that
the
i~ as

i1.Dii

FIV1(O),

Table 2-11 ,.ADA, ADXA Selection
CRAM

ADA Source

AR
ARX

1
2

MQ
PC
Os

3
4-7

ADXASource
ARX
ARX
ARX
ARX
Os

..~

Table 2-12

ADD, ADXD Selection

CRAMADB

ADB Source

ADXB Source

FM
BR*2
BR
ARX*4

(unused)

BRX*2
BRXj2
ARX*4

In addition, ADB directly controls ADXB utilizing the same 2-bit field. Here the selection is unused
(0), BRX*2(1), BRXj2(2) and ARX*4(3). Although AD and ADX together with ADA, ADXA, ADB,
and ADXB normally function concurrently, information in ADX does not affect AD unless so specified. Carries from ADX must be specifically enabled to AD in order to affect its sum.
2.9.5.4 AR Field - This field consists of three bits. Figure 2-71 details the breakdown of various
combinations of CRAM AR Selection and hardware controlled selection. Generally, the CRAM AR
field specifies selection as follows: ARMM(O), CAClfE(l), AD(2), EBUS(3), SH(4), ADX*2(5),
ADX(6) and ADXj4(7).
AR register loading is controlled by either the hardware or microcode. Normally, the AR register
recirculates its contents. Selecting any of the AR select lines CRAM ARM SEL 4, 2, or 1 enables
loading AR. The selection of none of the CRAM ARM SEL lines enables the AR mixer to select
ARMM. The loading of AR)s then a microcode function.
During reads from core, the signal CLK RESPONSE MBOX, selects ARM SEL 1 to enable the cache
data lines into AR. Similarly, on reads from fast memory via AD, FM XFER selects ARM SEL 2 to
enable the AD into AR. Various combinations of clearing of AR are possible depending on the conditions. This information is given in table form on Figure 2-71.

EBOXj2-83

--I

(
SIGNAL

SIGNAL

FUNCTION

CTl AR 00-11 ClR

ENABLES lOADING O'S INTO
AR OO-DB

CTl REG#OO

ENABLES MICRO CODE LOAD
ARMM INTOAR [COND/REG
CTl]

CTl ARR ClR

ENABLES lOADING O'S INTO
AR 18-35

CTl COND/ARll
lOAD

ENABLES MICRO CODE TO
lOAD ARMM INTO AR

CTl REG#02

CTl ARl SEL 4,2,1

TO ENABLE lOADING AR
00-08 WHEN ANY ARl
SEl1,2,4

CURRENTLY USED TO ENABLE
SER # TO BE lOADED INTO
AR 18-35

eTl COND/ARR lOAD

CURRENTLY USED TO
ENABLE SER # INTO ARR

CTl ARl IND fI
CRAM#OI

TO ENABLE AR 00-08 TO
BE lOADED VIA ARRM
INDEPENDENT OF AR 09-35

CTl ARM SEl 4,2,1

ENABLE lOADING AR 18-35
ON ANY ARM SEl 4,2,1

FUNCTION
ENABLES lOADING O'S INTO
AR 09-17

CTl AR 00-11 ClR

CTl REG#01

ENABLES MICRO CODE TO
lOAD PC/SECT 13-17 INTO
AR [COND/REG CTl]

CTl COND/ARlR
lOAD

ENABLES MICRO CODE TO
lOAD PC/SECT INTO AR

CTl ARl SEl 4,2,1

TO ENABLE lOADING
AR 09-17 WHEN ANY
SEL 1,2.4

r-- CTl AR 09-17 lOAD

CTl AR OO-DB lOAD

SIGNAL

FUNCTION

CTL ARR lOAD
18

(

ARlL
ClK

CTl AR 00-11 ClR
SIGNAL

FUNCTION

CTl AR 12-17 ClR

EN
CRAM AR~-i4
SEL 4
2

.--/1 0
MCl23 BIT EA

EXTENDED EA CALCULATIONS

r--

ARM

l'!o

ARIMM
CACHE

SEE TABLE AR 12-17 ClR

ARlR

ARR

OP-

J J J
SIH

EBUS

EN
4
2

ARM

r '

A6x
AO*Z
AOX14

EN
4
2

r--r-- I

1AO~'4

ARM

SE~ #

CAJHEI EBlusl A0 *2
AD
SH
AOX

PCI

I do

CACHE

J J
SIH

EBUS

Abx
AO*2
AOX14

SECTION

CTl ARl SEll
SIGNAL

' - - - CTl ARR SEl'2

I
I

SIGNAL

DIAL lOADAR
I

.
CTl ARl SEl 2

1FUNCTION

SIGNAL

CTl ARR SEll
AR 12-17 ClR
SIGNAL

SIGNAL
DIAG lOADAR

MICRO CODE MUST CONTROL
SELECTING ONE OF THESE
AD, E BUS, ADX, AD/4

CRAM ARM SEll

CON FM XFER fI
MCl lOADAR

READ INSTR ON OCCASION
OR DATA VIA FAST MEMORY

MCl lOADARfI
ClK RESP MBOX

READ INSTR ON OCCASION
ORDATAVIAMBOX

CTL 36 BIT EA

DURING A READ WITH CTl
AR 00-11 CLEAR FALSE

MCl lOAD AR fI
ClK RESPSIM

DIAGNOSTIC FUNC

VARIOUS USES FOR EXAMPLE
lOADING AN INSTR INTO AR
VIA DTE·20 FOR EXECUTION

FUNCTION

MCl 18 BIT EA

NON EXTENDED EA CAlCUlATION

CTl RESET

POWER CLEAR DIAGNOSTIC
FUNC

'--

CTl ARLIND SEl 2

VARIOUS USES FOR EXAMPLE
lOADING INSTR INTO AR VIA
DTE·20 FOR EXECUTION OR
BOOTSTRAP SEa

CRAM ARM SEl 2

SELECTING ONE OF THESE
AD, E BUS, ADX, AD/4

CON FM XFERfI
MCl lOADAR

READ INSTR ON OCCASION
OR DATA VIA FAST MEMORY

CTL DISP/A READ

ENABLE E VIA AD INTO ARR

VARIOUS USES FOR EXAMPLE
lOADING AN !NSTR INTO AR
VIA DTE·20 FOR EXECUTION

CTl ARl INO SEll

MICRO CODE MUST CONTROL
SELECTS ONE OF THESE
CACHE, E BUS, AD*2, AD/4

MCl lOADAR fI
ClK RESP MBOX

READ INSTRPN OCCASION
OR DATA VIA MBOX

MCl lOADAR
ClK RESPSIM

DIAGNOSTIC FUNC

FUNCTION

VARIOUS USES FOR EXAMPLE
lOADING AN INSTR INTO AR
VIA DTE·20 FOR EXECUTION

DIAGAR lOAD

FUNCTION

OIAG lOADAR

SELECTING ONE OF THE
FOllOWING CACHE, E BUS,
AD*2,AD/4

COND/AR ClR

AllOWS MICRO CODE TO
CLEAR AR 00-17

ARl IND fI
CRAM#04

AllOWS MICRO CODE TO
CLEAR AR 00-17INDEPENDENTLY

•
v

(

eTl ARR ClR
SIGNAL

FUNCTION

eTl RESET

POWER CLEAR OR DIAGNOSTIC
FUNC

eTl ARl IND fI
CRAM #05

AllOWS MICRO CODE TO
CLEAR AR 18-35INDEPENDENTLY

,
10· '640

Figure 2-71

AR Selection

EBOXj2-84

2.9.5.5 ARX Field - This field consists of three bits. Figure 2-72 details the breakdown of various
combinations of CRAM ARX selection and hardware controlled selection. Generally, the CRAM
ARX field specifies selection as follows:, UNUSED(O), CACHE(l), AD(2), MQ(3), SH(4), AD*2(5),
ADX(6), and ADX/4(7). ARX register loading is controlled by either the hardware or microcode.
Normally, the ARX register recirculates its contents. Selecting any of the ARX select lines CRAM
ARXM SEL 4, 2, or 1 enables loading ARX. The selection of none of these lines currently defaults to
an unused input (0). As with AR, during reads from core, CLK RESPONSE MBOX, selects ARXM
SEL 1, to enable the cache data lines into ARX. Similarly, on reads from fast memory via AD, FM
XFERselects ARXM SEL 2 to enable the AD into ARX. Generally, the ARX is cleared via ARL
IND and number 03. The various combinations are shown on Figure 2-72 in table form.

FUNCTION

SIGNAL

\
.--

CTlARXClR

CRAM ARXM SEl 4

SELECTING ONE OF THESE,
SH, AD*2, ADX, AD/4

SIGNAL

CTl ARX SEl2

SEE TABLE BELOW CTl ARXR
SEl2

CTlARXSEll

SEE TABLE BELOW CTl ARXR
SEll

CTl RESET

POWER CLEAR OR DIAG FUNC

CTl ARXClR

SEE TABLE CTl ARX ClR

CTl ARl IND
CRAM#03

FUNCTION
TO CLEAR ARX WHilE OPERATING ON AR

CTlARX lOAD

ARX
CLiC D P -

I
EN

CRAM ARX
M SEl 4

4
ARXM
2

.-/1

}

CACHE

"--

ADX

ADX*2

ADX/4

CTl ARXSEl 2

CTl ARXSEl 1
FUNCTION

SIGNAL
SIGNAL

FUNCTION

CRAM ARX M SEl 2

SELECTING ONE OF THESE
AD, MO, ADX, ADX/4

CONFM XFER A
MCl lOADARX

READ OF INSTR, INDIRECT
WORD OR DATA VIA FAST
MEMORY

MCl lOAD ARX A
ClK RESP MBOX

READ OF INSTR, INDIRECT
WORD OR DATA VIA MBOX

MCl lOAD ARX

DIAGNOSTIC FUNC

CRAM ARXM SEll

SELECTING ONE OF THESE,
CACHE, MO, ADX*2, ADX/4

10-1641

Figure 2-72 ARX Selection
EBOX/2-85

to the

18
to
§ources [nay be

:lFh;'M - The UR
Regl§tel· (BR), Tl"H::

one
§ourcI;;s may

BRXt1.ekl

BRX fiif:id. to

Ol'H':;
tw~)
seleGt~d: BR(O),

po§§ibRe SOUK'{;eg
selected:

t'Il\fO

three bits :and is 'Us,;:;;d in the
§·eliection is

fatl[

::iB

foHo1:1\,l!l:

'V.MA 32--35,

~~"

AC2(4), {IRA.C

9~·12)+2

(IRAC 9+2)+3

ModlJJk~

it is,

SCAD If:i'nleld ~.
SCAD field
three bits and is uSI;d to control the
Counter
(SC.,,'IlD) during various microinstrw;:tiol1 operations. It i5 wired to implement eight functions as
TabXe 2-L1 The
§~nlctme is similar to that
the AD Of ADX
there
are two input
labeled
SCADB. These
are selected
two control RAM
labeled

and SCADS.

2.9.5.10 SCADA Field - The SCADA field consists of three bits and is used to select various sources
as input to the SCADA Input. The following sources may be selected: FE(O), AR POS(I), AR EXP(2),
#(3). SCADA selections of 4-7 disable SCAD A producing zeros as output.
The floating-point exponent register (FE) is a lO-bit register. The AR position field is used in byte
instructions and consists of AR 00-05. The AR exponent field consists of AR bits 00-08 and the magic
number field is a 9-bit control RAM field used to implement various operations. The SCADA mixer
selection is shown in Table 2-14.

Table 2-14 SCADA Mixer Selection
CRAMSCADA

Source

0
1
2
3

FE
ARO-5
AREXP

4-7

2.9.5.11 SCADB Field - The SCADB field is a 2-bit field used to select various sources as input to the
SCAD ±B input. The following sources may be selected in the SCADB mixer: SC(O), AR SIZE(I),
AROO-08(2), and #(3). Selection of 4-7 disables SCADB, producing zeros as output. The SCADB
mixer selection is shown in Table 2-15.

Table 2-15

SCADB Mixer Selection

CRAM SCADB

Source

1
2
3

AR6-11
AROO-08

4-7

•
The shift counter (SC) is a general-purpose lO-bit register used in shift counting operations such as
performed in floating-point instruction and shift instruction execution. It also controls the shifter
when the SH-ARMM field is zero (SH AR and ARX). The AR SIZE field is used in byte instructions
and consists of AR bits 06-11. The AROO-08 is used in string and edit functions. The magic number
field is a 9-bit general-purpose CRAM field used for various functions.
2.9.5.12 SC Field - The SC field consists of one bit and is used with the special field function SCM
alternate. With SC and SCM alternate, four possible sources may be selected as follows:

EBOX/2-87

With the special field function SCM ALT and SC field equal to zero, FE is selected. Similarly, with
SCM ALT and SC field equal to one, AR SHIFT is selected. AR SHIFT consists of bits 18 and 28-35
of AR, which are derived from the effective..address for shift instructions. If bit 18 is set, the shift
specified is a right shift; otherwise, it is a left shift.
2.9.$.13 SH Field - The SHIFTER field consists of two bits and is used to select four possible inputs
to the shifter. The selection is as follows: the combined AR, ARX(O), AR(l), ARX(2), and AR
SWAPPED(3). When shifting AR, ARX left (which is the only way SH shifts physically), SC can
specify up to 3510 shifts. Any number less than 0 or greater than 3510 selects ARX as output.
2.9.5.14 The AR MixerMixer (ARMM) - The AR Mixer Mixer (ARMM) field consists of two bits
and is used with other control signals and the absence of ARM SEL 4, 2, and 1 to select various
sources as input to AR mixer.
The ARMM comprises three parts: bits 00-08, bit 12, and bits 13-17. The same field that controls SH
controls ARMMOO-08. The following may be selected as input to ARMMOO-08: #(0), AR SIGN
SMEAR(I), SCAD EXP(2), and SCAD POS(3). AR SIGN SMEAR is ARO-8 from ARO. SCAD
EXP is ARO-8 via SCAD, and SCAD POS is ARO-5 via SCAD.
ARMM bit 12 is controlled by CRAM SH-ARMM SEL 1 when transferring the previous section to
AR for certain operations. ARMM bits 13-17 are also under control of CRAM SH-ARMM SEL 1
but the signal is actually MCL PREY SECT to ARMM. The default value for ARMM 13-17 is PC
13-17 and the selected value is VMA previous section 13-17.
2.9.5.15 . VMA Field - The VMA field consists of two bits and is used to select various sources as
input to VMA. The following are specified by the CRAM field VMA(O), PC(l), PC+ 1(2), and AD(3).
. Address control is presented in Subsection 2.4 and a path diagram is provided to show various combinations in Figure 2-58.
2.9.5.16

MQ Field - The MQ field consists of one bit and is used in combination with the following:

DISP/MUL
DISP/DIV
SPEC/MQ SHIFT
SPEC/REG CONTROL
MAGIC NUMBER FIELD
Refer to Figure 2-73 for various combinations.
2.10 EBOX INSTRUCfION SET FUNCTIONAL OV,ERVIEW
Figure 2-74 breaks down the KLtO instruction set into several functional areas. These areas are related
to the minor machine cycles and to the microcode dispatch RAM decoding. The figure shows seven
basic areas as follows:
1.

Group

Class of instruction

Address Calculation

xr, @, B, Y

Data Fetch

IMM, Read, Read-Write, Write, Read, Pse Write

Execution

36-Bit Data Path (DP), 18-Bit Address Path
(AP), 23-Bit AP, to-Bit AP

Special Conditions

Can cause PI, Trap

Store Data

Write

Interruptable
EBOX/2-88

( ..~

0= LOAD
1 =SHRT
2 =SHLT
3= HOLD

MQ SEL 2

MQ SEL 1

MOM Out

MOM EN

MO/4
SH
AD
1',

,
1

MO Sel2

MOSel 1

0
0
1
1

0
1
0
1

MOM
MOM/2
MOM*2
Hold

0
1
0
1

0
0
1
1

1
1

MO~

MOM Sell

MOM Sel2

COND/REG
CTL
CONTROLLING FIELDS

CRAM
MO Field

SELECTED CONTROL SIGNALS

CRAM
MO

MOM EN

MOMSel2

MOM Sell

MO Sel2

MOSel 1

0
0
0
1
1
1
0
1
1
Reset

0
0
0
1
1
1
0
1
1
1

0
0
0
l'
0*
0
0
l'
O·
0

0
0
0
0'
l'
0'
0
1*
0
0

1*
1*
l'
0
0
0
1
0
0
0

'*
0*
O·
0
0
-0
0
0
0
0

SPEC/MO
SHFT

DISP/
DIV

DISP/
MUL

#07-08

0
0
l'

0
l'
0

0
0
0

00*
OX*
OX'

O·
0
0
0
0
0

0'
1"
0
0
0
0

00'
00
01
10*
11*
0

10-1642

Figure 2-73

MQ Selection

EBOX/2-89

1 INTERRUPTABLE

·SPECIAL ADDRESS MANIPULATIONS

GROUP
OPCODES

CLASS

READ

IMM

200-217

MOVE GROUP

YES

IMM

BASIC

500-577

HALF WORD
GROUP

YES

IMM

BASIC

YES

120-125

400-477

260-263

104-105

DOUBLE WORD
FULL WORD
GROUP
BOOLEAN
GROUP
STACK GROUP
JSYSAND
ADJSP

YES

IMM

YES

IMM

600-677

TEST GROUP

YES

330-337
350-357
370-377

ARITHMETIC
SKIPS

YES

300-317

COMPARES

YES

CAIXX

320-367
252-253

CONDITIONAL
JUMPS

YES

IMM

252-253

ARITHMETIC
TESTING

YES

264-267

SUBROUTINE
CALL

YES

254-255

AC DECODED
JUMPS

YES

XCP

YES

257

MAP

YES

270-277

FIXED POINT
ARITH

256

220-227
230-237

114-111

140-147
150-157
160-167
170 177
130-132
122
126-127
000-103

FIXED POINT
ARITH

DOUBLE
INTEGER
SINGLE PREC
FLOATING
POINT
UFA, DFN, FSC
FIX, FIXR
FLTR
UUO'S

YES

134-137

BYTE GROUp·

YES

240-247
{NOT 2431

SHIFTS AND
ROTATES

YES

251

SLT"

700-777

INPUT
OUTPUT

YES

EXCH

YES

250

110-113

DOUBLEPREC
FLOATING
POINT

Figure 2-74 Instruction Set Divisions

EBOXj2-90

BASIC

IMM

YES

READ

•
-

~
SETMB

WRITE

READ PSE WRITE

BASIC

SKIPXX

CAMXX

IMM

ADDI
SUBI

SELF

ALL

MEM

g
BOTH

~~~

SOSXX
AOSXX

~~~

~ ~~~

~ ~~ ~
V////~ V/////,/ V/////i; V/////i;
ADDM
SUBM

ADDB
SUSB

XMULM, }(MULB
XDlVM, XDIVB

BASIC

IMM

FSC

BASIC

UFA, FIX
FIXR
FLT, FLTR

MEM
BOTH

w:w w:w

•••••
AC*O
ADJBP
AC=O
IBP

ILDB
IDPB
[FPDI

IMM

~~~~
~
BASIC

BLKX

MEM

. ~~~~

ALL

EXCH

~~~

INTERRUPTABLE

WRITE
IMMTO FM
BASIC TO FM
MEMTO E
SELF TO E AND FM
SAME AS FULL WORD GROUP

BASIC TO FM, FM+1
MEMTO E, E+1

SAME AS FULL WORD GROUP
IMM TO FM ALSO CAUSES A FETCH
FROM FM

ALL

~7P~VL0

ALL

JSYS

YES

IMM TO FM
IMMTO FM
BASIC TO FM

ALL

SKIPXX, IFA * STORE {EI; INAC
CAIXX STORES NOTHING
CAMXX STORES NOTHING

ALL

CONDITIONAL
ALL

ALL

CONDITIONAL
ALL

~AOJX [AROVI'~

JUMPX STORES NOTHING
AOJXTO FM
SOJXTO FM

ALL

CONDITIONAL
ALL

ALL TO FM

ALL

UNCONDITIONAL
ALL

ALL

JRSTSARE
UNCONDITIONAL

ALL

UNCONDITIONAL

FETCH
IN KERNAL MODE PXCT

ALL

UNCONDITIONAL

PAGING INFO TO FM

ALL

YES

ALL

V}~)////

'0'/'/////

)'//~~oj0

WI
~

~("~
~/////0

(

STORE DATA

ALL

JSRTOE
}
JSP TO FM
JSA TO E AND FM
JRATO AC

(

ALL CAUSE
FETCH

HIGHER LEVEL FUNCTIONS
PERFORMED

SAME AS FULL WORD
IMULI.IDIVI TO FM
IMUL, IDIV TO FM
IMULM, IDIVM TO MEM
IMULB, IDIVB TO FM, MEM
MUll, DIVM TO FM, FM+1
MUL, DIV TO FM, FM+1
MULM, DIVM TO E, FM+1
MULB, DIVB TO E, FM+1
D ADD TO FM, FM+1
o SUB TO FM, FM+1
o MUL TO AC, AC+1, +2, +3
o DlV TO E, E+1

~ft.{~6~
/};///,'/

(

~{~{~t~
//"/'}7/ '/

DFN

~ ~~

IMM

TRAP

MEM

~~~~

IMUL
IDIV

CAN CAUSE
PI

~~~

10BIT
DP

~~~~

ADD
SUB

23 BIT
AP

ALL

••••
•
•
•
• •••
IMM

18 BIT
AP

SELF

IMM

36 BIT
DP

MEM

~~ ~ ~

IMM

BASIC

READ-WRITE

SPECIAL CONDS

EXECUTION

DATA FETCH

ADDRESS CALCULATION

ALL

HIGHER LEVEL FUNCTIONS
IBP, UPDATE POINTER {El
ILDB, UPDATE POINTER {EI
BYTE- FM
IDPB, UPDATE POINTER {EI BYTE - AC

ALL

YES

ALL

YES
[CONOPI]

EIE INTERFACE OPERATIONS

ALL

E:FM

ALL

~{(tfo(~

ALL

YES

///////;

YES
IN@
LOOP

LSH, ASH: AC -10 FM
LSHC, ASHC: AC+1 -10 FM+1
ROT: AC-IoFM
ROTC: AC+1 -10 FM+1
MULTIPLE WORDS MOVED SOURCE+N
TO DEST+N

DFAD,DFSS: RESULT TO AC, AC+1
DFMP.DFDV: RESULT TO AC, AC+1

YES

. Once the instruction has been loaded into IR and ARX, the major machine cycle begins; this is shown
in Figure 2-75.·
Three functional flows and two tables are included to supplement the functional descriptions of the
address, fetch, and store cycles that follow.

INDEXING
.,__--( INDIRECTION
INTERUPT

10-1644

Figure 2-75

Major Machine Cycle

2.10.1 Effective Address Calculation
Figures 2-76 and 2-77 illustrate the instruction word formats. Bits 13-35 have the same format in every
instruction whether the instruction addresses a memory location Qr not. Bit 13 is the indirect bit, bits
14-17 are the Index register address and, if the instruction must reference memory, bits 18-35 are the
memory address Y. The effective address E of the instruction depends of the values of I, X, and Y.

08 09

'.'T"C:'•• C.DE AC'.'CAT.' .... E"

INDEX REGISTER
ADDRESS (X)

VIRTUAL MEMORY ADDRESS

(Y)

INDIRECTION

Figure 2-76

•

Basic Instruction Format

INDEX REGISTER ADDRESS

35
VIRTUAL MEMORY ADDREsS

INDIRECTION
10 -1646

Figure 2-77

In-Out Instruction Format

EBOX/2-91

2.10.1.1 Indexing -If the Index register address is nonzero, the contents of the specified Index register are added to the Y address to produce a.modified virtual address.

(

Referring to Figure 2-78, the EBox tests ARX 14-17; if it is nonzero, the contents of the specified
Index register are added to ARX 00-35. The result in AD 18- 35 is loaded into AR 18-35 with AR
00-17 cleared, and also loaded into VMA 18-35 while VMA 13-17 is recirculated.
2.10.1.2 Indirection ~hether indexing is performed or not, if ARX 13 is equal to 1, indirection will
be performed. Two cases are to be considered. The first is where no indexing was performed. Here
(indicated on Figure 2-78 as (;\) ) VMA 18-35 is loaded via AD with ARX 18-35. In the second
case, indexing is performed and tile VMA is loaded via AD with AR. Here AR holds the sum of ARX
18-35 and FM 18-35 effectively, with AD bits 00-17 clear.
In either case, VMA 13-17 is recirculated while VMA 18-35 will be loaded via AD. The microinstruction MEM field function for the indirect request is MEMj AIND. This function has MEM 02 =
0, so MBOX WAIT is conditionally a function of the next microinstruction.
Testing for Interrupts
The microinstruction causing the EBox request also tests for a pending priority interrupt. If an interrupt is pending, the CRAM address is modified to allow entry to the PI Handler (Figure 2-79).
The request, which is made both to fast memory and core memory via the MBox, is ignored as long as
it does not page fault. MBOX WAIT is false, so the EBox clock does not stop at this time. The EBox
ignores an indirect reference when an interrupt is pending, but the EBox hardware remembers a page
fault (if one occurs) until the page fault handler has been called. After the PF Handler is called, Force
1777 will be cleared.
Referring to Figure 2-80, assume the indirect request has been started. Because the indirect reference is
always a "READ," the only types of page faults that can occur in KI paging mode are no access (page
not in core) or proprietary violation.
The requesting microinstruction detects the interrupt and the microprogram branches (via CRAM
Address) to the PI Handler.
If the page fault occurs (for example) because of no access, the MBox must first read from the in core
process table to obtain the paging information (use bits A, P, W, S, C and physical page). Reading this
can take between 600 and 1000 ns. During this period, the PI Handler is setting up the requested PI
service.

Eventually, a read, write or instruction fetch occurs, caused by the handler. When MBOX WAIT
becomes true, the clock board (which remembered the Page Fail Hold level) forces the microprogram
to the page fault handler.
Now the page fault handler detects the pending interrupt and the microprogram branches back to the
PI Handler or to the instruction cycle. Thus, the entry to the page fault handler satisfied the clock
board "page fail hold condition" and this condition now clears. Should the EBox make a second
MBox reference before the page fault occurs, the EBox waits.

EBOXj2:.92

(

ADD THE CONTENTS
OF THE SPECIFIED
INDEX REGISTER
TOARX IN AD

AR - 00-17 - 0
AR18 -35' AD~8·35
VMA 13·17 ··-VMA 13·17
VMA18·35- · AD18·35

NOTE 1:
IF NO INDEXING
WAS PERFORMED
AD=(ARXI ELSE
THE (ARI

NUMBER OF EBOX CYC J ES REQUIRED

REF CAN
PAGE FAIL?

FMADR32-35 VMA32·35.
"ACCESS FAST
MEMORY"

VMA13·17 ·-VMA 13·17
VMA 18·35 --AD18·35
"BEGIN EBOX REO"

EBOX OOES NOT
USE THE FAST
MEMORY WORD

VMAAC
REF?

MBOX CYCLE

I
FASTMEM CYCLE

INDIRECT
REF?

NO MBOX
TERMINATES

YES

BEGIN CYCLE,
BUT EBOX IGNORES

BEGIN CYCLE, @
WORD TO ARX

YES

NOMBOX
TERMINATES

YES

BEGIN CYCLE,
BUT EBOX IGNORES

BEGIN CYCLE
BUT EBOX IGNORES

YES

BEGIN CYCLE, @
WORD TO ARX

BEGIN CYCLE,
BUT EBOX IGNORES

YES

BEGIN CYCLE ,
BUT EBOX IGNORES

BEGIN CYCLE,
BUT ~BOX IGNORES

YES

YES, I F SO EBOX
DIVERTS TO PF
HANDLER
NO

MBOX COMPLETE
CYCLE?

YES,BUT NOT
ACTED UPON
UNTIL THE NEXT
MBOX WAIT'

'ONCE IN THE PAGE FAULT HANDLER
THE INTERRUPT PENDING WILL
CAUSE A RETURN TO THE PI HANDLER
AND THE PF HOLD EN LEVEL WILL BE
CLEARED, REMOVING TEMPORARILY
ALL TRACES OF THE FAULT.

SEE NOTE 2
INTERRUPT
?
NO
YES -DIVERT
TO PI
HANDLER
NO

YES-DIVERT
TOPI
HANDLER

REQUESTING
MICRO INSTR

NEXT MICRO
INSTR

MEM/AIND

MEM02=1
MBOX WAIT

MEM/AIND

MEM02=0

MEM/AIND

M EM02=1
MBOXWAIT

MEM/AIND

MEM02=0

NOTE 2:
MEM CYCLE 1\ MEM 02( 11 = MBOX WAIT
MBOX RESP OR FM RESP CAUSES MEM CYCLE TO CLEAR
MBOX WAIT I\-VMA AC REF:. EBOX CLOCK STOPS IF:
•. MBOX IS SERVICING THE EBOX REO
b. WORD IS IN THE CACHE AND
TIME FIELD IS < 3 OR ...
MBOX IS SERVICING THE EBOX REO
b. WORD IS NOT IN THE CACHE OR . .•.
• . MBOX IS SERVICING THE EBOX REO
b. A PAGE FAULT OCCURS OR .. . .
• . A CONTROL RAM PARITY ERROR IS
DETECTED OR .. ..

10-1647

Figure 2-78

Effective Address Calculation
EBOX/2-93

Figure

Du.ring Div!ef!:ed

NOl!'lIT!ud Case - Nt} I~ternupt§~ IV.lLBm. Re{ll!lu')§t

When the ERox
is made specificaHy
fonowing
which made the
MEl".!!, This function, together with IV!:EM

are pending, the
field coded as

micrct~
i-

'VAIT,

fault
not occur, the word
once again.

the

No Interrupt§!, FlBl§t Memoli:! ReqMte§t
determines
the
contains
is used to
the
EBox
fast memory
control uses VMA
may
a care memory address;. The

The

mernory address, it asserts
is not to
by
to 8!1,;::cess

dirc'cts the

address manager (Figure 2m 1

it s81111pies this
."HaL'''.-''' the correct registers to be loaded; it may,
the: next
performs

13 ami 14-17. In addition,
assu.me a

a rnkWl11strw:::tion

information
information provided
it
to a

is to always perform
indexing
AD,
information only if ARX
7 ~ O. This approach

to
the

of the logic.
The
at the
of Figme
Ihrw the four possiMe
ences to either MBox or
IT}.emory.

resu1ting

indirect refer-

ENTER WITH AR=E
"DRAM A=4, 5, 6~9R 7"

YES

YES
"DRAMA=4"

YES

PERFORM REAO &
PAGE TEST OF
EFFECTIVE
ADDRESS.

"DRAM A=O"

NO DATA
FETCHED. AR=E

NO DATA
FETCHED. AR=E
NO

PAGE FAULT
HANDLER

WRITE IN E

"READ-WRITE"
PERFORM READ
AND WRITE PAGE
TEST OF
EFFECTIVE
ADDRESS

YES
"READ PSE
WRITE"

PERFORM READ
AND WRITE PAGE
TEST OF
EFFECTIVE
ADDRESS
IDOING READ
PSE WRITE)

AR- DATA

PAGE FAULT
HANDLER

FETCH lAC). FAST
MEMORY
ADDRESSED VIA
IRAC 09·12
AR-"AC

AR-·DATAWORD

PAGE FAULT
HANDLER

10-1649

Figure 2-80 EBox Data Fetch
EBOXj2-95

2.10.1.3 No Indirection or Indexing - For this case, ARX 18-35 contains the effective address. Here, it
remains only to load AR 18-35 via AD with E and ((lear AR 00-17. The Fetch cycle is now entered.
2.10.2 Fetch Cycle
Once the effective address has been calculated, the second minor machine cycle is entered. This is the
Fetch cycle and is illustrated in Figure 2-81.

IMM
IMM-PF
READ
READ-PF
WRITE TST
READ-WRITE
READ PSE WRITE

10-1650

Figure 2-81

Fetch Minor Cycle

After the effective address has been calculated, the microprogram effective address manager gives "A
READ DISPATCH" and control is passed to the Data Fetch Manager.
In general, two major classes of instructions exist in terms of the Data Fetch cycle. These two classes
are those instructions that require the contents of the effective address and those that do not. Within
each of these two categories are a n umber of divisions. The flow of the Fetch cycle is illustrated in
Figure 2-80.
2.10.2.1
1.
2.
3.

•

Instructions That Do Not Require (E) - Three general groups form this category.
Complex or PC change instructions
Immediate non-PC change instructions
Instructions that write in E

For these three g'roups, the DRAM A field is coded 0, 1, and 3, respectively. The AREAD Dispatch
functions are listed in Table 2-16 .
Complex or PC Change Instructions
The DRAM A field is coded as 0, and no data is requested. In addition, the next instruction is not
prefetched. The AREAD /Dispatch dispatches directly to the execute code. This consists of a table
lookup, where one discrete entry exists for each instruction. Thus, for example, the move instruction
indexes into location "200" in the DRAM. The organization of the DRAM is illustrated in Figure 1-4.
Immediate and Non-PC Change Instructions
The DRAM A field is coded as 1, and no data is requested. The next instruction is prefetched and
loads into ARX when the instruction becomes available. The AREAD /Dispatch dispatches directly to
the execute code.

EBOX/2-96

Table 2-16 AREAD Dispatch
DRAMA

DISP/AREAD

MEM/AREAD

Require (E)

Executor

NoPrefetch

Executor

Start Prefetch

Not used

Symbolic Address 43 *

Perform write test.

Symbolic Address 44*

"LOAD AR."

Yes

Symbolic Address 45*

A read operation is in progress:
"LOAD AR, PREFETCH."

Yes

Symbolic Address 46*

LOAD AR. READ-PAUSE-WRITE

Yes

Symbolic Address 47*

LOAD AR, WRITE TEST

Yes

N/A

*The Data Fetch manager is a combination of hardware mostly on MeL and the microprogram consisting of 43-47.

Instructions That Write in E
The DRAM A field is coded as 3 and a write page test is initiated. If the address is not writable, a page
failure occurs. This action causes a transfer to the page fault handler as indicated in Figure 2-80.
The appropriate Fetch EBox Qualifiers may be determined by referring to Figure 2-82. For DRAMA
= 3 the following qualifiers are specifically asserted:
EBOX REQUEST
EBOX PSE
EBOX WRITE
In addition, the state of the qualifiers is more complex and may depend on the previous history of the
EBox. The state is indicated by an asterisk (*). Once again referring to Figure 2-80, if the write page
test is successful, the EBox fetches the contents of the addressed fast memory location (via IRAe
09-12) and then dispatches via the DRAM J field to the executor.

EBOX/2-97

EBOX REQUEST QUALIFIERS

c:
t2

ta: .,w
;: :J

X
0

ffi

MEM
FUNC

CYCLE

ADDRESS

DRAM
A

S :'i"c:
DRAM

X
0

ffi ffi ffi ffi

":E

'a"

...,"'"
>

t:;

~
>

:::!

~ u~

£" t;;
-' W
t-

""w

""-'w w"
0

0
0

;;

"> ."'" ~'" '~"

INDIRECT WORD READ, MAY BE TO MBOX OR

A IND FOLLOWED
BY LOAD AAX

X X

* *

FETCH

10R5

X X

* * *

•

* * *

FETCH

AREAO

X X

* * * *

•

* * *
* * *

EXECUTE
STORE

FETCH

A READ

FETCH

X X

4-5

X X

A READ

AREAD

* * * *

X X X X

A READ

* * * *

* * *

* * * *

X X * *

* *

•

eD* * *

BWRITf

2-3

EXECUTE

BYTE IND

X X

EXECUTE

BYTE RD

X X

EXECUTE
STORE
MISC

WRITE

EXECUTE

LOADAR

* * * *

* * * *
* *

X X

* * * * *

* *

TO FAST MEMORY, VMA AC REF INDICATES
WHICH VMA HOLDS ADR.
INSTR FETCH. MAY OCCUR FOLLOWING A
READ WITH DRAM A=1 OR 5 TOGETHER WITH
MEMiFETCH.
INSTR FETCH FOR JRST 0 OR=JRSTO)
PI CYCLE IS CLEAR. USED WHERE NO PRE FETCH
WAS ISSUED TO CAUSE AN INSTR FETCH.
DATA READ ISSUED BY INSTRUCTIONS REQUIRING
THE fE) AS FOLLOWS: COMPLEX OR PC CHANGE
INSTRUCTIONS OR SIMPLE NON PC CHANGE INSTRUC·
TIONS.

CYCLE

COND
FUNe

EXECUTE
MUUO
PART 1,2.
METER
REQUEST,
PAGE FAIL
PART 1,2.

SPEC
FUNe

MEM
FUNC

SP MEM
CYCLE

WRITE
SEE FIG

-= FIELD

SPMEM
CYCLE

LOAD AR
FOLLOWED
8YMB
WAIT
SEE FIG

<.:>

WRITE INTO USER PROCESS TABLE. MBOX
USES VMA 27-35 ONLY. MBOX APPENDS
UBR 14-26 TO FOAM PHYSICAL REFER·
ENCE UNPAGED. CANNOT PAGE FAIL.

=220

=110

X X

FOA DEPOSIT WRITE ACCORDING TO
RELOCATED VIRTUAL ADDRESS. THERE
WAS NO PROTECTION VIOLATION.

=110

FOR DEPOSIT OR EXAMINE, READ PROTEC·
TlON AND RELOCATION INFORMATION
FROM EXEC PROCESS TABLE . FOR MTR
REQUEST READ DOUBLE PRl:.CISION WORD
AS APPROPRIATE .

INSTR FETCH FROM EPT FOR STD INTER·
RUPT OR 2ND PART OF STD INTERRUPT.
MBOX USES VMA 27-35 ONLY. MBOX
APPENDS EBR 14-26 TO FORM PHYSICAL
REFERENCE UNPAGED. CANNOT PAGE
FAIL.

2·54

EXECUTE
MUUO
PART 3,
PAGE FAIL
PART3

READ NEW PC WORD FROM USER PROCESS
TABLE . MBOX USES VMA 27-35 ONLY. MBOX
APPENDS UBR 14-26 TO FORM PHYSICAL
REFERENCE UNPAGED. CANNOT PAGE FAIL.

2·54

EXECUTE
DEPOSIT

SPMEM
CYCLE
:t08(1):.
PHYS REF

EXECUTE
EXAMINE,
DEPOSIT,
METER REQ

SPMEM
CYCLE
#08( 11:.
PHYS REF

EXECUTE
STD
4Ot2N INT
2ND PART
STD INT

SPMEM
CYCLE
#00( 1):

EXECUTE
NICOND
PI VECT,
EXAMINE
SEE FIG
1·25

SPMEM
CYCLE
.N08(1):.
PHYS REF

NICOND
TRAP
FETCH

SPMEM
CYCLE

WRITE
SEE FIG

2·54
LOAD AR
FOLLOWED
BYMB
WAIT
SEE FIG

2·54

EXECUTE
BLKO PI

EXECUTE
DATAl

LOAD ARX

=510

FETCH
EN IN

I/O
LEGAL

LOAD AR
FOLLOWED
BY MB
WAIT SEE
FIG 2·54

LOAD ARX
FOLLOWED
BY LOAD
ARX

X X

.::1 10
IF EPT
SPECIFIED
SEE FIG
'·25

.::30

SPEC
EXEC
KILLS
USER
EN

FETCH WORD FROM ADDRESS SPACE
SPECIFIED VIA API WORD BITS 0-2MAY
BE: EPT, EXEC VIRTUAL, UPT, USER
VIRTUAL, PHYSICAL. THE STATE OF
VMA EPT, VMA UPT, MAY BE PAGED
CONTROLS CONTEXT OF REFERENCE.

FETCH INSTA FROM USER PROCESS
TABLE If TAAP OCCURRED IN USER
MODE AND EXEC PROCESS TABLE IF
TRAP OCCURRED IN EXEC MODE.
THE STATE OF VMA UPT AND VMA
EPT IS A FUNCTION OF MCL USER EN .

* * *

I/O
LEGAL

AEG FUNC

.::142

I/O
LEGAL

REG F!JNC

:::'" 143

EXECUTE
BLKI PI

I/O
LEGAL

REG FUNC

EXECUTE
BLKO PAG

CTl

EXECUTE
DATAO

I/O
LEGAL

REG FUNC

=242

I/O
LEGAL

REG FUNC

=243

PAG

EXECUTE
CON I

PAG

READS INFORMATION FROM EBOX AND
MBOX. FIRST READS LOOK, LOAD, SEC
TRAPEN, THEN REQUESTS MBOX TO PUT
EBR INTO EBUS REG. EBOX THEN READS
EBUS REG AND STORES RESULT IN E.

READS THE MBOX ERROR ADDRESS
REGISTER. THE WORD IS STORED IN
THE SPECif i ED AC .

x
x

PAG

EXECUTE
CONO

READS INFORMAT ION FROM EBOXAND
MBOX . FIRST READS AC BLOCKS, CWSX
AND VMA PREV SECT THEN REOUESTS
MBOX TO PUT UBR INTO EaUS REG.
EBOX THEN READS EBUS REG.

STEP 1=!:"1
STEP 2==21
STEP 3=0

MBOX

TRANSMITS 36 BITS OF CONTRO L INFOR·
MAT ION FETCHED FROM E TO THE
INTERNAL OR EXTERNAL MEMORIES.
THIS IS PERfORMED VIA THE MBOX.
THE MEMORY CONTRO LLER SELECTED
RETURNS A WORD WHICH IS STORED
IN E+1 .

REG FUNC

INVALIDATE ENTRIES IN THE PAGE TABLE
WITHIN THE MBOX . EBOX USER REFLECTS
USER MODE, AND THE PAGE TO INVALIDATE
IS IN VMA.
LOADS CONDITION ALL Y AC BLKS, PREY
CONTEXT, AND UBR (IN MBOX) AND
CLEARS THE PAGE TABLE IN THE MBOX .

~~:D2E5~~~~~~~:~N THE Dp

PAG

EXECUTE
MAP

I/O
LEGAL

REG FUNC

=540

EXECUTE
BLKO
APR

I/O
LEGAL

REG FUNC

=145

Figure 2-83 Execute-Register-MBox
Control and Miscellaneous General
Memory References
EBOX/2-100

(

READS PAGE FAILWORD FROM MBOX
EBUS REGISTER. THE WORD IS STORED
IN THE SPEC[FIED AC .

A TO BE

LOADS THE CACHE STRATEGY BITS
(LOOK, LOAD) SECTION AND TRAP EN
FLAGS IN THE EBOX . THE EaR (lNTHE
MBOX) IS LOADED VIA VMA 24-35.

WRITE THE CACHE REFILL ALGORITHM.
VMA 18-20 CONTAINS THE ALGORITHM
B[TS AND VMA27-33 CONTAIN THE REFILL
ALGORITHM ADDRESS.

(

The DRAM A field is coded as 6, causing a dispatch to location 46; the MBox performs both a read
and write page test. The address must be b<¥:h accessible and writable, even though this portion of the
operation only reads a word. If a page failure occurs, the EBox transfers control to the page fault
handler. Otherwise, the word enters AR and then a DRAM J dispatch is issued.

Read PSE Write Type Instruction
The DRAM A field is coded as 7 causing a dispatch to location 47; the request qualifiers are shown on
Figure 2-82. The MBox performs both a read and write test, and if no page fault occurs, reads a word
from the specified (Xlated) address.
If the cache is disabled for the reference and the word requested was not in the cache (a Refill cycle was
necessary first), then the MBox is held waiting until the EBox issues the write portion of the cycle. The
word requested loads into AR and a DRAM J dispatch is issued to enter the Executor.

2.10.3 Execution Cycle
The Executor is entered from the Fetch cycle. While in the Fetch cycle, the (E) or (AC) is fetched in
accordance with the DRAM A field. In addition, read and/or write page testing is performed while in
the Fetch cycle. The EBox Execution cycle overview is in Figure 2-84.
Early in the Instruction cycle, the DRAM is accessed using one of three basic types of addresses.
Referring to Figure 2-84, if the instruction is JRST 0-17, then the IR address is used to address the
DRAM initially as indicated. Thus, the JRSTs handler is entered at location 254 for JRST and 255 for
JFCL.
From the initial dispatch into the handler, the IRAC is used to redispatch within the handler for the
proper type of JRST. For JFCL, a JUMP is made to a separate handler from the initial dispatch
If the instruction is an I/O type, then the DRAM address is formed by the hardware such that the
dispatch is in the range of 700-777. Once the I/O handler has been entered, a determination must be
made as to whether the instruction is legal in the current processor mode. If it is determined that the
instruction is not legal, the MUUO executor is used to store the illegal instruction and PC word in the
user process table. Following this, a new PC word is fetched. This new PC word causes the processor to
enter an executive routine in core memory. If the I/O instruction is legal, use of the EBus is obtained
and the appropriate EBus dialogue is carried out. The specific actions evoked depend upon the device
and the type of I/O instruction being performed.

The remaining instructions index into the DRAM utilizing the op code in IR bits 00-08. Two general
categories exist ,as follows:
1.

Simple Type - stores in AC, E, or both

Complex Type - may store in AC, AC+ 1, E via normal store cycle or else store via a special
handler, or may do some of each

The complex instructions may nest microcode subroutines up to four levels deep.
Referring to Figure 2-85, the mechanism consists of CRA LOC, a register that is loaded with the
"current microinstruction address." This register is loaded at the same time that the CRAM register is
loaded with a new microinstruction. In addition, a 4-word stack is provided. The contents of CRA
LOC are pushed onto the top of the stack when the call has been asserted by the microinstruction. To
return from a subroutine, the returning microinstruction asserts DISP /Return. This pops the top entry
off of the stack and onto the CRAM address mixer lines, where it is logically ORed with the J field of
the microinstruction, asserting DISP /Return.
EBOX/2-101

MIXTURE OF COMPLEX
AND SIMPLE

(

~ORAM-----1
DISPATCH TABLE

DRAM
REGISTER

"MICRO PROGRAM SUBROUTINE
CALLS MAY BE NESTED TO
FOUR LEVELS"
INSTRUCTIONS
WHICH MAY

OPERANDS

STORE IN AC,AC+1, E

STORE IN E

·1'0 LEGAL DETECTS
ILLEGAL INPUT
OUTPUT INSTRUCTIONS
IF INPUT OUTPUT IS
ILLEGAL AN MUUO 18
PERFORMED AND THE
INSTRUCTION IS STORED
AS IF IT WAS AN MUUO.

Figure 2-84

EBox Execution Cycle Overview

EBOXj2-102

CLK CRAM

"NEXT

ADDRESS"

CRAM
REGISTER

"CRAM
ADDRESS
MIXER"

CLK CRA
PUSH
POP

2
3
4

"ALWAYS POP OFF THE LAST PUSHED ON"

10-1654

Figure 2-85

Microstack Operation

Some of the complex instructions, such as DMUL, which stores in AC, AC+ 1, AC+2, and AC+3, use
a separate handler for storing multiple operands. This type of instruction does not pass through the
normal store cycle. Other complex instructions, such as MULB, which stores in AC, AC+ 1 and E,
store multiple operands via the normal store cycle.
2.10.4 EBox Data Store Cycle
The flow for the EBox Store cycle, illustrated in Figure 2-86, is used by most of the instructions
executed by the microprogram Executor. Exceptions to this are certain instructions such as D MUL,
which stores more than two ACs. For these instructions, a special handler exists that is entered from
the executor. This handler stores all the operands and then issues an instruction fetch followed by a
NICOND Dispatch. In this text, the more general categories (which do use the normal store cycle) are
covered.
2.10.4.1 Basic Four Mode Type Instructions - This type of instruction may have one of four basic
modes as follows:

•

Immediate or Basic - store in AC only

Memory - store in E

Both - store both in AC and E

SELF - store in Eand conditionally store in AC. Note that if writing back in E is redundant,
the write cycle is ~kipped.

Writing for these four mode instructions is controlled by MEMjDRAM B and the DRAM B field
code. The store cycle is dispatched with DISP jDRAM B. Thus, the dispatch RAM B field (three bits)
is used to form the low-order three bits of the Store cycle address.

(

Immediate or Basic Mode
Referring to Figure 2-87, the DRAM B field is coded as 5. The contents of AR are written into fast
memory, which is addressed via IRAC 09-12. Because a large number of these instructions prefetch
the next instruction, it is necessary to assert MB WAIT in the event MEM cycle is set waiting for a
response from the MBox. This has no affect if MEM cycle is clear. NICOND Dispatch enables entry
to the instruction cycle if no priority interrupts, page faults, or traps are pending.
EBOXj2-103

STORE AR IN E
MBOX OR FM VMA
AC REf TELLS
WHICH TYPE

IN AC AND AC+1

"SC=3S" ....-ST-O-R""'E'"A"R--IN""A'"C,..-'"
AS ADDRESSED
VIA IRAC09·12
PUT$IGN Of
RESULT INAR

00-35

•

NOTE 1:
CERTAIN COMPLEX INSTRUCTIONS.
SUCH AS DOUBLE MUL.DOUBLE D!V.
ETC. STORE ALL, OR A PORTION OF
THEIR RESULTS VIA THEIR OWN
SPECIAL MICRO ROUTINES .
NOTE 1:
DISP/DRAM B ENABLES THE B fiELD
Of THE DISPATCH RAM WORD FOR THE
CURRENT INSTRUCTION TO MODIfY
THE CRAM BASE ADDRESS INTO THE
STORE CYCLE fOR H MODE TYPE
INSTRUCTIONS
MEM/DRAM 8 WRITE ENABLES THE
MEMORY CONTROL HARDWARE TO
PERFORM A WRITE TO MEMORY IF
DRAM 8=3, 6, 7

F--

SIGN

--::3

LOW ORDER WORD

Is I

MARX

LOW ORDER WORD

"STORE LOW ORDER
WORD IN AC+'"
...._ _ _1-_ _.....

10-1655

Figure 2-86 EBox Data Store

EBOX/2-104

,-LlO::O.. OlfBlISCTL
~

APIIEBvSI!£TURN

I--

~I--I~~~~--"~

~
~

I-L..!!!

1#05

,.... 1

CONTROL

USER EN

PAGE"E~"8l~ ~"'02.04-05
CONTIIOI.

~ ...J

. t-SPEC/SPMEMCYC

MCLLOAOVMJlCONTEXT

~~~~~::;,J::;:
~''''''''

1--,,<-0,

I- ." ""

eo. ••

,~~: ;ii):

APIISET
lOP. EIUI

MBOlCTL
FUNCTIONS

PT'loUBL'C

•
I

10-1752A

Figure 2-87

MBox-EBox-EBus Control (Sheet 1 of 2)

EBOXj2-105

•
10- 17528

Figure 2-87

MBox-EBox-EBus Control (Sheet 2 of 2)

EBOXj2-106

Mer{~1liry Or."

The

Both
B field is coded as 6

memiory mode iE1§tructloI1i§. If VMA
liS ,:::ie:ar, lItoring is to
is fnadle to ston;; AR in catche U"'~!LA"'-'" VM:AAC REF
men1ory. An l.mcondiHonaJ "''''''''''''''''''' fetch 13
AD
1)
as soon a§ IvIBox

DliV\1\,~

enabled at
n~cdved,

"ell"-'RAJ'''''''

in case the

irH~truction

is being fetched

This is
by M13
tlnaHy I"HCOl"'ID Disp"atch is

:state n"''''''''''iF'''"

me;l:110ry, a
I:!~lgf, tt.Ht;

(in

For Both r·.,1oc!e, DRl-\Jl! B is coded as 7, Hen~, th,e departure is
is
stor,ed in
by IRiLC
dearing
state
Dispatch is h;sued.
SELF Mml!u:

to Figure 2-87, the DRAM B

iih.is means

i.s coded as; 3, SELF
HSHlllCI:H)H§ are
address 'wa§ read and
page tested during the

being nonzero.l~R is stored in the
is tC'lsted (in IRJ!!:~qo [RAe i§ nonzero,
location (ml addre!lsed via IRAC), If HV\C is zero, no
iill performed. In
'6~a8;e, a microinstru;ction NOlP' Is
This guarbetween
instruction
and
NICOND

antelElf; one
adequate setup time for the
those cases where the

logic to detect a
feV;h is to fa§t memory.

2,i0.4,,2 SlK}[P~ JUrVIP Olllmpare b.l§tn,!(:tiOlrmcategory.

fonowing lIlstrUi::t1ons listed

Conditional Jumps

Pliithmetic

AOJ3JP
AOEJI\[
CAIXX

~~~.~.~~.

I Cl\JvIXX .•
__-1______L __ _
I·

memory

Yes
Yes
No
No

EBOX/2-H)7

fan into

No Results Stored - CAIXX, JUMXX
Referring to Figure 2-87, because CAIXX arrd JUMPXX store no results, preparations are made for
entry to the instruction cycle. The state'register is cleared, MB WAIT is asserted, and a NICOND
Dispatch is issued. Depending upon the outcome of Test Satisfied, the next instructionfetch is from
PC+l, PC+2, or E.
Conditional Storage in AC - SKIPXX AOSXX, SOSXX
IRAC is sampled and if nonzero, AR is stored in fast memory as addressed via IRAC 09-12. Depending upon the outcome at Test Satisfied, the next instruction fetch is from PC+ 1 or PC+2 and this is in
progress. The state register is cleared, MB WAIT is asserted, and a NICOND Dispatch is issued.
Unconditional Storage - SOJXX, AOJXX, AOBJX
These instructions all store unconditionally, in fast memory from AR, as addressed via IRAC, then
prepare to enter the Instruction cycle. The state register is cleared, MB WAIT is asserted, and
NICOND Dispatch is issued. Both SOSXX and AOSXXunconditionally store in E and conditionally
store in AC.
2.10.4.3 Store Cycle for Other Instructions - Generally, the remaining instructions that use the Store
cycle fall into two groups. These are instructions that store results in AC, AC+ 1 and E, and those
, instructions that store results in AC and AC+ 1 only. All these are complex instructions.
Complex and Store Both
For these instructions, the store flow is entered with a write request already in progress to store the
high-order result of some operation and MB WAIT is asserted (MEM/MBWAIT). Also, the shift
counter (SC) contains 35, enabling alignment of the low-order word with the sign of the high-order
word later in this flow. The AR is now stored in fast memory as addressed via IRAC and the sign is
smeared in AR 00-35. At this time, AR contains all sign bits and ARX contains the low-order word
left-justified. The instruction fetch begins. The AR and ARX are shifted left 35 places and the result
(correctly signed) is loaded into AR via SH. Now the state register is cleared and the low-order word
(in AR) is stored in IRAC + 1. The EBox hardware facilitates the incrementation of IRAC by + 1.
Finally, the appropriate entry to the instruction cycle is made.
Complex and Store in AC, AC+ 1
The basic difference here is that these instr1,!ctions bypass the storage into E. Otherwise, the operation
is identical to that for Complex and Store Both.
2.11

•

INTERFACE CONTROL

2.11.1 Introduction
Figure 2-88 illustrates the major functional control elements of the EBox. The purpose of this drawing
is to support the functional descriptions contained in this section. In addition, it is provided to support
the ElM interface control and E/E interface control functional descriptions to follow.
The EBox is associated with two interfaces, the EBox/MBox Interface and the EBox/EBus Interface.
The ElM interface is treated as a pseudo-bus because in many ways it behaves as a bus. In the first
portion of the functional description, the basic organization and function of the firmware microprogram was described. In addition, the major machine cycle was defined and described in terms of its
functional elements.
Thus, the individual microprogram modules (Figure 2-13), taken collectively, comprise the main
microprogram. The blending of this program with certain pieces of EBox hardware constitutes the
basic machine cycle (Figure 2-88).

EBOX/2-108

.-------------~HOW

MICRO
PROGRAM
LL-.,,~~~:::±:t--

STARTUP
AND
STOP
INTERFACE

___ AUX I lLiARY

,
/YylEZ
DISPATCH
PI
PF TRAP
Til BlE ::---.:..::

/
N A T A STORAGE
DATA FETCH
MANAGER
MANAGER
EXECUTOR
EFFECTIVE
ADDRESS
MANAGER
10-1656

Figure 2-88

Basic Machine Cycle Summary

Figure 2-89 is the subcycle summary and Figure 2-90 is the hardware cycle summary.

BREAKDOWN,

•
10'1657

Figure 2-89

Subcycle Summary

EBOXj2-109

CONTROLLED
BY MICRO
INSTR

Figure 2-90

Hardware Cycle Summary

Next, the basic sub cycle was presented in terms of a functional flow with additional graphics to support the description; in the interface section, the relationship of the hardware to the internal EBox
cycles was described. These basic cycles were introduced in Subsection 2.1 as EBox, MBox, and EBus
cycles. For example, the fetch cycle can be viewed as composed of a number of EBox and MBox cycles.
2.11.2 MBox Control
Referring to Figure 2-91, a number of functional elements work together to implement the basic MBox
cycle. The grouping of the interface signals shown is as listed in Table 2-18.

To exercise the functional areas illustrated on Figure 2-91, a basic data fetch is covered in four steps.
These steps are related to EBox timing in terms of occurrence.
Table 2-18

•

Request Summary

Grouping

Signals

Basic EBox Request Handshake

EBOX REQUEST
CSHEBOXTO
CSH EBOX RETRY REQ
PFHOLD
MBOX RESPONSE IN

Address and Address Control

VMA 13-35
VMAACREF

Timing

EBOXSYNC
MBOXCLOCK

Type Request

EBOXUSER
EBOXREAD
EBOXPSE
EBOXWRITE

Address Violation Logic

PAGE TEST PRIVATE
PTPUBLIC
PAGE ILLEGAL ENTRY
PAGE ADDRESS COND

EBOXj2-11O

(

AS3ur"lE MOVE

If~STR

10-J65':1

ngUl'!ie

2-9
Control

,","l,Uj.!'!,"""'''"

EBOX/2-111

2.11.2.1\ DATA FETCH REQUEST EN - B~in EBox Cycle (Figure 2-92) - The fl'Ow is entered at an
EB'Ox cl'Ock and the CRAM register l'Oads. The micr'Oinstructi'On begins t'O be dec'Oded. N'Ote that the
MEM field is the maj'Or input t'O the MB'Ox c'Ontr'OII'Ogic. Assume that the effective address has been
calculated, the MEM field is c'Oded as AREAD, and the dispatch RAM A field is 5. In Figure 2-91 at
,the MEM field functi'On AREAD is a c'Ode 'Of 4. This enables MBOX CYCLE REQ. In additi'On, if MEM 01 = 1, then REQ EN is asserted t'O enable the request qualifiers t'O be latched 'On the
next EB'Ox cl'Ock. MBOX CYCLE REQ enables the EB'Ox request t'O be asserted 'On the next MB'Ox
cl'Ock. As indicated 'On the fl'Ow, this is a fast cycle. Tw'O basic classes exist: fast and sl'Ow. The timing is
illustrated in Figure 2-93.

Signal CLK SYNC EN must wait t'O 'Occur, S'O that (f'Or a fast cycle) EBOX SYNC sets at the same time
as EB'Ox request.
Referring t'O Figure 2-91, the VMA field, with 'Other signals, enables LOAD VMA. In additi'On, the
effective address must be input t'O VMA via AD S'O the VMA c'Ode (3) generates VMA +-AD.
The basic peri'Od between the leading edge 'Of 'One EB'Ox cl'Ock and the leading edge 'Of the next is
c'Ontrolled by the T field 'Of each micr'Oinstructi'On, al'Ong with certain 'Other hardware signals. The basic
pulse width 'Of the p'Ositive EB'Ox cl'Ock is fixed at 32 ns but the time between cl'Ocks is variable. EBOX
SYNC 'Occurs 'One MB'Ox cl'Ock pri'Or t'O the MB'Ox cl'Ock that causes EB'Ox cl'Ock t'O 'Occur. The basic
relati'Onships are indicated in Figure 2-94.
2.11.2.2 Begin MBox Cycle - End Current EBox Cycle and Start Next (Figure 2-95) - As s'O'On as
SYNC EN is true, EBOX SYNC sets and MBOX CYCLE REQ (FAST CYCLE) enables EB'Ox
request t'O set (refer t'O Q) 'On Figure 2-91). At this p'Oint, MBOX WAIT is tested and f'Ound clear.
(This functi'On is described in basic terms is Subsecti'On 2.2.4.)
T'O summarize, the EB'Ox request is then issued, and the VMA input mixer is set up and enabled t'O l'Oad
with E via AD. The request type l'Ogic is enabled t'O assert the appr'Opriate c'Ombinati'On 'Of EB'Ox Read,
PSE, and/'Or Write (which 'Occur 'On the EB'Ox cl'Ock t'O c'Ome at Q) ). In additi'On, the Address
C'Ontext C'Ontr'Ol is enabling the pr'Oper c'Ombinati'On 'Of its qualifiers als'O t'O be asserted at

N'Ow an'Other MB'Ox cl'Ock 'Occurs Q) ; simultane'Ously, an EB'Ox cl'Ock 'Occurs. The f'Oll'Owing acti'Ons
result:

EBOX CLOCK +- 1
EBOX REQ +- 1 (REDUNDANT)
MEM CYCLE +- 1; MBOX WAIT +- 1
VMA LOADS AND LATCHES
CRAM +- NEXT MICRO INSTR
EBOX QUALIFIERS LATCHED
Thus, we have passed thr'Ough 'One EB'Ox cycle and n'Ow reenter the fl'Ow t'O begin a sec'Ond EB'Ox cycle.

EBOX/2-112

(

10·1660

Figure

2~92

Begin EBo]l;

Data Fetch Request

IClK

EBOX ClK

ClK

SYNC

EBOX CYCLE

-I

EBOX CYCLE

MBOX CYCLE REQ

ClK EBOX SYNC

- ---

(

EBOX REQ (FAST)

MBOX CYCLE REQ

EBOX REQ (SLOW)
10-1664

Figure 2-93

EBox Request Fast or Slow

TIME FROM lEADING
EDGE TO lEADING EDGE
(APPROX I MATE)
rEBOX CYClE-j
T=OO

--.J

80ns

i E B O X CYClE--,
T- 01.
TIME
FIELD
VAlUES 2

IT= 10

-I

EBOX CYCLE

I-

T= 11

120ns

EBOX CYCLE

160ns

-I

200ns

10-1665

Figure 2-94 Basic EBox Clock Period

EBOX/2-114

lOAD CRAM
REGISTER BEGIN

MCl REO EN,
ENABLE. REO
OUALIFIERS

WAIT SPECIFIED
BVCRAMT

. . ~~~~~~:~~~i?

1;;~~~I~~····~~~~~~Z~:;
~

\VMA lOADS'"
.
"'CRAM REG lOADS',
:: WITH NEXT:.
,', MICRO INSTR.'i}"
:" MCl REO EN, ,i)i\,
':: lATCH MEMDRV:

...~~~~~~.~~; •••.•.•..'....••.•••.

10-1661

Figure 2-95

Begin MBox Cycle, End Current EBox Cycle, Begin Next EBox Cycle

EBOX/2-115

2.11.2.3 SETUP PREFETCH - Wait for MBox Response - Referring to Figure 2-96, the flow is
reentered at G) where the EBox clock generated loads the second microinstruction (Figure 2-91
G) ). Now the MEM field function is FETCH and MEM 02 = 1. If the MBox has not responded
with the word requested (E), MEM cycle is still set. The combination of MEM 02 (1) and MEM Cycle
(I) generates MBOX WAIT. Providing that the request is not to fast memory, the EBox stops until the
MBox response occurs.
This is true whether a page fault occurs or not, although PF hold is asserted 5 MBox clocks before
MBOX RESPONSE is asserted when a page fault has occurred. In this example, assume that the
MBox is working on the request, but has not yet responded.
Referring to the flow (Figure 2-96), the current microinstruction MEM field function fetch is a code of
6. Note, however, that because a priority interrupt takes precedence over any other activity, PI
CYCLE is checked before enabling the MCL MBOX CYCLE REQ. Here PI CYCLE is clear, so
Q) points to a "Fast Request." Again, a wait for SYNC EN, as defined by the T field, takes place.
The state of the SYNC EN during MBOX WAIT is always true; this keeps EBOX SYNC true until the
response is received.

("
,

The MBox continues to run during the waiting period. Thus, MBOX CLOCK sets EBOX REQUEST
even though the VMA is still latched up with E. During the waiting period, the VMA input receives
PC+ 1 via VMA AD.
The EBox now loops, waiting for MBOX RESPONSE to restart the EBox clock.
2.11.2.4 MBOX RESPONSE RECEIVED - Referring to Figure 2-97, MBOX RESPONSE enables
the EBox clock. Thus, EBOX CLOCK becomes true and, simultaneously, EBOX SYNC becomes
false. The third microinstruction is now loaded into the CRAM register (Figure 2-91 G)) and is
decoded. In addition, the VMA is loaded and latched with PC+ 1, the request qualifiers are latched
and now, with the requested data word in AR, a DRAM J dispatch is issued.

2.11.2.5 General Memory Cycle Control - Figure 2-98 contains all combinations of the MEM field
that can generate MCL MBOX CYCLE, and hence EBOX REQ. In general, the following functions
are of the "Slow Cycle" type:
B WRITE
PI FETCHES
SKIP SATISFIED FETCHES
REG FUNCTIONS
SP MEM CYCLES

•

A Slow cycle is required during MEM/REG FUNC because the MBox requires additional time to
decode the type of request. In all the "slow" cycle types, the EBOX does not necessarily have time to
determine whether to make the request (or not) before EBOX SYNC. Thus, the decision, and therefore
the request, is delayed purely for hardware timing reasons.
2.12 EBUS INTERFACE CONTROL
The I/O system for the KLlO processor includes the EBus, the peripheral equipment with its interfaces
to the EBus, and various control logic. The EBus interface may be controlled either by the EBox
during input or output instruction execution, or by the PI system during priority interrupt handling.
Subsection 2.8.1 gives a basic summary of the EBus signals. This is followed by a functional description of the interface, which is covered at two levels. The first level describes the basic functional
organization and operation of the PI board and other related logic. The second description deals with
the microprogram to PI board interfacing. This description attempts to give insight into the manner in
which the hardware and the microprogram interact to carry out various interface related functions.
EBOX/2-116

C/,.

lOAD CRAM
REGISTER BEGIN
,....---, DECODING

YES

MCl REQEN:
ENABLE REQ
QUALIFIERS

Maox WAIT

WAIT SPECIFIED
BY CRAM T

•
FAST OR SLOW
CYC:
EBOX REQ- 1
MEMCYClE-l
VMA lOADS
CRAM REG lOADS
WITH NEXT
MICRO INSTR.
MCl REQEN:
lATCH MEMORY
CONTROL
QUALIFIERS
10-1662

Figure 2-96

Setup Prefetch Waiting for MBox Response
EBOXj2-1l7

YES

~JlCl t~IEGB'!.:
~f\M·.13lE t~EQ

QUt\.Ur-IEr-~S

YES

WA,IT S(P\EClf~ED
BY Ct:;AM T
F~EU)

10·1663

Figure

~Imox

Respomle, End
Next EBox Cycie,

Current

SLOW C'::'CU:.:

FOR TH\:3

:,"'VPE OF CYCU£, [\1130),;
CYGL~ REG IS "'lOT
ASSEC'!TED lJNTIL [:130;<

WAIT SPECIf-itD

r'-~'"""!

mm(SY"C

~"~"~_~~

t~"

I~-""'""'l\

MBOX

eye

HEQ

-~"~"~"~~"

SLOW

\_~~."-

10-165G

Figure 2-98

2.12. . EBus Signal Line
0 signals. All devices~ including the KLlO, are connected to these lines in
The E
parallel. The bidirectional nature of 36 of the signals permits some information to flow in both directions. These lines are the data lines. The remaining 24 signals are used for control functions. Table 2-19
lists the data transfer signals.

Table 2-19

Data Transfer Signals

Name

Mnemonic

Data
Controller Select
Function
Demand
Acknowledge
Transfer

D(OO:35)
CS(OO:06)
F(OO:02)
DEM
ACK
XFER

Number of Lines
36
7
3
1
1

DA TA LINES D(00:35) - The 36-data lines transfer information between the EBox and its devices.
The most significant bit is bit 00; the least significant bit is bit 35.
CONTROLLER SELECT LINES CS(00:06) - These seven lines select the desired controller for a data
transfer. Each controller has a unique select code hardwired on the backplane of the device.
FUNCTION LINES F(00:02) - The function lines specify the type of data transfer (or non data
transfer) to take place. Table 2-20 lists the functions implemented.
Table 2-20 Table Data Transfer Commands

•

FOO

FOI

F02

Operation

0
0
0
0

0
0
1
1

0
1
0
1

CONO
CONI
DATAO
DATAl

DEMAND (DEM) - This line causes the addressed controller to inspect the CS and F lines and decode
their meaning. Upon implementing the specified function, Transfer and Acknowledge are asserted in
response and data is placed onto or taken from the EBus as specified by the decoded function.
ACKNOWLEDGE (ACK) - This signal line notifies the I/O bus adapter not to respond to the current
operation. If it does not detect ACKNOWLEDGE within some period following assertion of
DEMAND, it attempts to perform the transfer. It does not decode the CS lines as the standard KLlO
devices do.
TRANSFER - This line is asserted by the selected controller when it is ready to execute the specified
function as decoded in F(OO:02).

EBOX/2-120

(

PRIORITY TRANSFER LINES - To perform priority interrupts between the KLlO and its devices,
the same basic set of signals is used in a slightly -modified form. Table 2-21 lists the necessary signals as
they are used.

Table 2-21

Priority Transfer Signals

Name

Mnemonic

Controller Select
Controller Select
Function
Demand
Acknowledge
Transfer

CS(04:06)
CS(OO:03)
F(OO:02)
DEM
ACK
XFER

Number of Lines
3
4
3

CONTROLLER SEL CS (04:06) - During interrupt arbitration, these three lines represent the octal
encode of the interrupting channel.
CONTROLLER SEL CS(00:03) - These four lines specify the controller or device that the EBox is to
honor during this interrupt sequence. This is, of course, only a single device or controller, even though
several may be interrupting on the same channel. This code also corresponds to the hardwired physical
device number of the appropriate controller or device. In CONTROLLER SEL CS(OO:03), the range is
o through 17.
FUNCTION F(00:02) - Two functions are generated during the interrupt dialogue. The first is a code
of 4 in F(OO:02) and specifies to the interrupting controllers that those controllers being addressed by
Channel number in CS(04:06) should send their Physical Controller number by placing them onto the
EBus upon sensng DEMAND. The second function is a code of 5 in F(OO:02) and specifies to the
interrupting controllers or devices that one has been selected. The selected controller will see CS(OO:03)
as the same number as its physical controller number.

ACKNOWLEDGE (ACK) - Same as for data transfers.
TRANSFER (XFER) - In the case of interrupts, the device selected for service by the EBox places a
special function on the EBus data lines D(OO:35). Figure 2-99 is the EBus interface functional block
diagram. Table' 2-22 lists the priority transfer commands.

Table 2-22

Priority Transfer Commands

FOO

FOI

F02

Operation

I
1

0
0

PI SERVED
PI ADDRESS IN

EBOX/2-121

(
CON EBUS REl

•

APR EBUS REQ

EBOX

PI REQ 1-7
PI REQUEST
DECODING AND
CONTROL

SET PI HOle
r--

WAiT2

PI COMP

EBUS RETURN

EBUS
REOUEST
CONTROL

APR

r--

MTR PHYS NO.

APR DISABLE CSCOMP
TIME 7

I-

TIME 6

EBUS 000-015

IR03-09-

I
I

INT
REO

S~~~ ~g~-

,"'" Q'"
PI CYC

TIME 1
TIME STATE
GENERATOR

I
I

~
HOLD

-PI CYCLE
Clf<. PI (35MHz)

I
I

APR EBUS FOI

CTl T TO E EN

APR EBUS RETURN

I
I

PI TIMER
AND
TIME STATE
CONTROL

TIMER
DONE

.
I

PI 0

DEv,
DTE 20

(

r-r-'--

EBUS 000-35

NOTE:
ProvidinQ CON PI CYCLE is clear, PI
REO tOQether with TEST will cause the
RING COUNTER to hold in the TEST
STATE until EBUS PI GRANT sets. Once
GRANT SETS TEST is removed and the
counter (all staQes) ,produces 0's until
a). The hand shake completes and both
EBUS PI GRANT clears and PI CYCLE
sets and clears.
10-1~67

Figure 2-99 EBus Interface Functional
Block Diagram
EBOX/2-122

(

I-

EBUS 007 - 010

DISABfE
COUN
-PI CYC STA.RT
-TIMER DONE

r--

EBUS TRANSFER

-T~

I
I
1 I
I

PI 1-7

DEMAND

TIME 2

I
PI
CYCLE

FOO

~Al!~~A2!I~B~J

r-r-r--

CS04 -06

F02

TIME 3

E
B
U
S

Il-

CSOO-03
EBUS
DIALOGUE
CONTROL

TIME 4

INTERLOCK

X
l
A
T
0
R

APR EBU~_
DEMAND

TIME 5

MICRO
PROGRAM
lOOKS

II EBUS
I
000 -35
i
I
I API WORD FOR
I
INTERRUPTS STATUS
I INFO FOR CONI, CONso,1

MTR

APR
PHYS
NO.

PI EBUS
PIGRANT

I ClK DP---1 r
I /
ARM

PI GATE TTL TO ECl

TEST

~
T

I I

I <. TEST

PI READY

EBUS MIX

I /

(lOAD
RING COUNTER
WAin
<'WAIT2
HOLD CONTROL

PI REQ

lOAD
WAiTI

PI REQ 0 [DTE-20]

"lOAD THE REQUEST"
AND ARBITRATE IT

,,--

DOO-3~

r---1---,

EBUS CP GRANT
PI DISMISS

PI REO

DATA FOR DATAO
Co NTR 0 l INFO FOR
CONO

/'.

(

2.12.2 EBus Interface Organization
Referring to Figure 2-99, the interface consists basically of six functional elements. These elements are
as follows:
1.
2.
3.
4.
5.
6.

PI Request Decoding and Control
PI Request Counter and Control
EBus Request and Control
EBus Dialogue Control
PI Timer and Time State Control
Time State Generator

The EBus request control and EBus dialogue control are used both by the EBox to carry out I/O
transfers and by the PI system in response to an interrupt. During priority interrupt handling, the
EBus dialogue is carried out in asynchronous fashion. This operation is controlled by the PI timer and
time state control, together with the time state generator.

To obtain the use of the EBus dialogue control, the PI request decoding and control logic must compete with the EBox. No priority exists, and control is obtained on a first-come, first-served basis. Once
the EBus has been granted to the EBox, the priority interrupt must wait until the EBox releases the
bus.
If the PI system obtains the EBus, the EBox may "demand" the EBus if a page fault occurs (EBus
Return).

(

2.12.3 Interrupt Handling - Loading the Request
Referring to Figure 2-99, there are two cases. The first is an interrupt request from some device on PI
1-7. This may be from any KLlO device, including the APR. The second case is an interrupt from the
DTE20 on channel O. Only the DTE20 may generate channel 0 interrupt requests.
In either case, the PI request enters the PI request decoding and control logic. Here there is a variation
in priority. The PI system must be turned on in order for a request on channel 1-7 to be inspected,
while interrupts on channel 0 will always be inspected whether the PI system is on or off. The ring
counter controls the sampling of PI requests and also determines when a particular request (the highest) is ready to be serviced. In general, "PI LOAD" enables all active requests 0-7 into a request
register, providing corresponding PION enables are on for channels 1-7.
A programmer may disable interrupts on selected channels by clearing PION for each channel he
desires to inhibit (note PIONO is in the DTE20). This is done by performing a CONO PI instruction.
While the ring counter advances through "WAIT I" and "WAIT 2," the priority network arbitrates
all incoming priority interrupt levels and selects the one with the highest priority (numerically lowest
number).
2.12.3.1 Testing the Request - Next, PI TEST is asserted with PI REQ to request the EBus. PI TEST
remains true until EBUS PI GRANT sets, giving the EBus to the PI system. Once PI GRANT sets, the
PI TEST condition is cleared and the ring counter is disabled until the entire EBus dialogue is carried
out and PI CYCLE is "set and
cleared" by the microprogram.
,
2.12.3.2 Requesting the EBus - Setting EBUS PI GRANT begins the EBus dialogue by enabling the
assertion of CS 04-06 as the selected channel and FOO(4) as function PI SERVED, and also causes the
PI timer to begin its sequence by setting PI CYC START.

(

In general, all external devices that connect to the EBus are presumed to be composed of TTL logic.
The PI and EBox logic consist of ECL logic. To temporarily connect these two different types of logic
requires use of a logic level shifter. This device is called a translator. The translator must be notified of
the conversion direction, TTL to ECL or ECL to TTL. Actually, only the data portion of the EBus is
switched from one level to the other. The control signals are connected to fixed level shifting logic. For
example, EBUS DEMAND is a unidirectional signal and it is connected to a noncontrollable level
shifting gate on the translator module (ECL to TTL).
EBOX/2-123

2.12.3.3 Beginning the Dialogue - The setting of PI EBUS PI GRANT asserts the level PI G ATE
TTL TO ECL, which causes translation of incoming data from TTL logic levels to ECL logic levels.
The PI timer and time state control manipulates the time state generator such that each time state is
held for the appropriate length of time. The following relationships exist between the dialogue signals
and the time state logic:
CSH 04-06: EBUS PI GRANT
FOO: EBUS PI GRANT
DEMAND: sent at T2, T5, and T6
LA TCH INCOMING PHYS numbers: T3
CSOO-03: T3
F02: T4
EBUS TRANSFER: WAIT AT T5 FOR TRANSFER
PI CYCLE: WAIT AT T6 FOR PI CYCLE TO SET
2.12.3.4 Interlocks and Dialogue Completion - Upon entering T5, the timer is inhibited from
incrementing the count until EBUS TRANSFER is received or forced. While waiting, the timer holds
the loaded count. As soon as TRANSFER is received and recognized by the PI logic, the timer is once
again allowed to count down T5 .
" Thus, while T5 is counted down, the API word is stabilizing on the input to AR. Next, T6 is entered
and here the absence of PI cycle causes STATE HOLD to be asserted. This time the timer may count
down and even generate TIMER DONE. If this point is reached and PI CYCLE is still false, the timer
loads the count specified by T6 and continues to count while waiting for PI CYCLE to set. The PI
board must not begin to service a second interrupt before the microprogram has a chance to look at
the first one. Hence, the timer is prevented from entering T7 COMP, until the microprogram has set PI
CYCLE. This also enables the ring counter to perform load.

(

Assuming PI CYCLE sets, the time state generator proceeds through T7 and into complete (COMP).
Note that the EBus dialogue control removes DEMAND some time before removing the CS and F
lines. This avoids the possibility of misselection of a device. The generation of COMP enables PI
EBUS PI GRANT to clear, removing FOO and CS04-06.
2.12.4 Basic Input Output Control
Referring to Figure 2-99, the implementation of I/O operations is similar to interrupt processing, if
taken at the point where the EBus is requested. The difference is that instead of a hardware arbitration
. process taking place, followed by a single request subsequently asking for the EBus, the microprogram
I/O handler (part of the executor) requests the EBus. This is accomplished utilizing the condition field
function COND /EBUS CTL, together with a particular pattern in the magic number field all in the
same microinstruction. Only the resulting signal is indicated on the figure (APR EBUS REQ) but the
various other signals are simply formed by combinations of COND/EBUS CTL and an appropriate
magic number.
2.12.4.1 Requesting the EBus - The EBus request control treats both an EBox-EBus request (APR
EBUS REQ) and a PI EBus request equally. Whichever request is seen by the EBus request control
first receives the EBus.
The microprogram is waiting for an indication that it has been granted the EBus. The indication of this
condition is EBUS CP GRANT. The microprogram loops, waiting for this signal to become true.
Once this occurs, the next step in the operation may be performed.
2.12.4.2 Dialogue Overview - Basically, the EBox decodes bits 10-12 of the instruction to determine
which type of I/ O operation is to be performed. Eight possible combinations exist; these are indicated
in Figure 2-100 at the bottom left. The logical mapping of I/O op code into appropriate DRAM
addresses is also illustrated in Figure 2-100.
EBOX/ 2-124

(

# 5101
#,
# 1
#3
# 511 1
#2
# 0
SELECTION
APR EBUS APR EBUS CON EBUS APR EBUS HOLD
REL
DEMAND STATE CONTROL
RETURN
REO

MAGIC # FIELD
OPERATION
BASIC EBUS
OPERATION
USED BY ALL
I/ O INSTR

MTR INT,
INTERNAL
DEVICE
CONTROL,
PAGE FAIL
HANDLER,
READ EBUS
REG

USED TO
OBTAIN ONLY
THE ECL SIDE
OF EBUS. THEN
GIVE BACK
lATER

DEPOSIT, BY TE
XFER OR PI
DATAO, FOL·
LOWED BY
BASIC EBUS
OPERATION
EXAMINE, BYTE
X FER OR PI
DATAl , FOL
LOWED BY
BASIC EBUS
OPERATION

cuND
EBUS CTL

012345678

YES

010000000

YES

000011000

YES

000110000

YES

000010000

YES

001000000

YES

100000000

YES

000000000

FUNCTION

- APR
AC10111
#7
APR EBUS
F01

# 6
# 6
APR EBOX
DISABLE CS

APR F02
EN 111
#8
APR EBOX
SEND F02

CS 00-06

REQUEST
Eeus
I/ O INIT

IR 03-09

Holding

SET EBUS
DEMAND
CLEAR EBUS
DEMAND
RELEASE
EBUS
GRAB ECl
EBUS
RELEASE
ECl EBUS

INPUT OUTPUT
INSTR ENTER
HERE

APR EBUS REO

YES

000010110

SET DATAO

I
YES

000010100

SET DATAl

PI BOARD WAITS
AT T6 UNTIL PI
HANDLER TAKES
DATA AND SETS
PI CYCLE

eBUS CP GRANT

O'S

I
I
I
I

O'S

--------,I
I

I
I
I
I

EBOX CLK

"FOR ALL I/O
INSTRS
I ROO-02_7"

COMP
T7
T6
T5
T4
T3
T2

SET PI CYL

_CO':.!

r-0-2

IR
().2=7

IR
03·06
'0

r--DRAM FOR 1/ 0 INSTRS--1
777 "7 OR 0"

03-05

IR
07·09

I
I
I
I

06·08

CONSO APR
CONSZ APR
CONI APR
CONO APR
DATAO APR
BLKO APR
DATAl APR
BLKI APR

,I
I

-bt)03.

MAP INTO
770·777
770
767 :=::_~-710 - --,

rIR
10-12

LOCAL
DEVICES

,--

r--

EXTERNAL
DEVICES

DRAM
ADR
FOR
liD

'--

EXTERNAL DEVS

L _ _

774

LOCAL
707 - l I MAP INTO APR
PI
I 1710.767
PAG
, I
CCA
TIM
, I
I~ ~= =- __ .-: MTR
SPARES
MAP INTO ... _
700·707
'
700 - - - - - ~

Devs
000
004
010
01.
020
02.
030

"EOR PI
HANDLING MAY
ENTER HERE
WITH FCN AND
CS ALREADY"
SET UP
PI BOARD IS
WAITING IN TG
FOR PI CYCLE
TO SET

----------1
HIF OUTPUT PUT
WAIT

~ AR ONTO EBUS

===:;;;;;:===

VIA AD"

HOLD
CS, F
NO

APR EBUS DEMAND

4NOTE: fOR EXTERNAL DEVICES
IR 03-06*0 SO MAKE
DRAM ADR 03 05 = 7

---'
WAIT

MAP INTO
XXO-XX7

EXT
TRANS
REC

AR~EBUS; IF
INPUT OPERATION
DROP DEMANO

WAIT THEN DROP
F, CS LINES
RElEASEEWS

1----'

t_______CO_N_E~BU~S~R~E~L~

_ _ _ _ _ _~ _ _ _ _ _ _~

~----~

10-1668

Figure 2-100

EBus Control Functions
EBOXj2-125

The dispatch to the proper operation is obtained by mapping bits 10-12 into DRAM ADR 06-08,
while the device address 3-6 is mapped into DRAM ADR bits 03-05. Thus, for example, a DATAl
APR with op code 701 is mapped into DRAM address 701. Similarly, BLKO PAG, with op code 722
is mapped into DRAM address 722. This is device 010 8 ; therefore, the type of operation performed is
determined in advance and the DRAM jump address is coded to cause a jump to the appropriate
group of microinstructions. The device select code is in bits 3-9 of IR and must be used to address the
device. This addressing is accomplished by converting 3-9 to CSOO-06 in the proper form. The function is controlled by the combination of two EBox control signals, APR EBOX SEND F02 and APR
EBUS FOI. With these two signals, all combinations of input and output operations may be performed
as indicated on Figure 2-100. Notice that EBus FOO is not used for any of the operations. This signal is
generated during priority interrupt dialogue for the function PI SERVED (Function 4) and for PI
ADDRESS IN (Function 5).

2.12.4.3 Functional Breakdown - Figure 2-100 is essentially composed of three sections. The first is a
breakdown of the EBus microcode operations into four basic suboperations as follows:
I.
2.
3.
4.

Basic EBus operation as used by all I/O instructions.
ECL EBus acquisition and subsequent release
Generation of the DA TAO function followed by the basic EBUS operation
Generation of the DATAl function followed by the basic EBus operation

The second section illustrates how the operation specified in IR 10-12 and a portion of the device
select code IR 03-05 are mapped into the DRAM words that pertain to I/O operations.
Finally, the third section consists of a simplified flow of the basic EBus operation, including the
handshake between the microprogram EBus driver and the PI Board.
Basic EBus Operation
This is illustrated in the flow on the bottom right of Figure 2-100. Five basic COND/EBUS CTL
functions are generated from particular magic number bits. The first is to request the EBus from the PI
Board. This consists of asserting APR EBUS REQ.
The microprogram now loops, waiting for an indication that it has obtained the EBus. The indication
consists of receiving EBUS CP (Central Processor) GRANT from the PI Board. This moves the microprogram to the next logical step which is 10 INIT. Here magic number 5 enables the function lines FOI
and F02 to be driven from -APR AClO and APR F02 EN, respectively. The table of I/O operations
given at the bottom left on Figure 2-100 shows that FO 1 is true whenever AC 10 is false. This is true for
DATAO, DATAl, BLKO, and BLKI. Conversely, F02 is true whenever AClO is true, or both AClO
and ACII are false.
Magic number 4 is used to latch the particular function (HOLD IT). Note that during the 10 INIT
period, IR 03-09 is passed to the PI Board to become CSOO-06. A fixed delay is generated by the
microcode at this time to allo~ the controller select lines to set up at the device.
Next, SET EBUS DEMAND is issued, while holding the previous function lines FOI and F02 as
previously set up. Once again, the microprogram waits a predetermined period. The waiting is controlled by the time field and the number of successive microinstructions issued. Thus, two successive
microinstructions with T = 5 is approximately 300 ns.
N ow the microprogram loops, waiting for TRANSFER from the device. This signal indicates that the
device has completed the specified transaction and has either taken or transmitted status, data, or
control over the EBus. At this time, if the operation was CONSO, CONSZ, CONI, BLKI or DATAl,
the EBus is loaded into AR. If the operation was CONO, BLKO or DATAO, during 10 INIT the AD
is enabled to the EBus. The AD contains the contents of AR.
EBOX/2-126

(

function

that i.s now 011

I02 generaHy
operation:;L Figure

Flirth";T,

DSKA on
range of
Rand that J)SKB

that DSKAc is
that DSKA is

aSSlJ))TIe

P]
PI
011 5 through 1 ('0 is DTE20
a3.sj~rtirtg REQ:o obtain use
the
and is

check those cha:meIs holding
never holds),
5 1:3 seh~I~'ted. The nf.",t pha5e
iE,Bus.

E.J3()J(/2~ 127

l ~.

1,4'1
F' "1l'l're 2-.HJ
lie '

..
,pil'
EBOJL.,

. ...
1,kicrOicod~
If.l.

Board

~ terfae.:;
JlllL
.

"2,..1 PORTION OF 5TO

IERRUPT-

CONO/SET "lCVC

FUNCTION IS IN
SHOI-O!

10-1751A

Figure 2-102 EBus Control Hybrid Flow (Sheet 1 of 2)

EBOX/2-129

1--------------------

PI AND EBUS CONTROL LOGIC

1
01;

CONSOLE
CONTROL

-osoo

·I~

CONI OR
OArAI

-CONSOLE
CONTRO\.

1
1

EBuSXfER

I
1

I
I
I
I

•

I
I
I
I
1

I
1

I
I
I
I

C500-03

P>1VSII'OO-15

PI SERVED (~COl 4)
PI AORIN{FCN 5)
BYTETRAN$ (FeN 6)
UNUSED (FCN7)

CO"'l!FCN!)
DATAl (FCfII3)

PI ADR IN(FCN5)

NEW
TIMER
GEfS2

LOAD
TIMER

OLD
TIMER
STATt

"lEW
TIMER
STATE

C!'-tNT

CYCLE

READY

W.6IT,,, T~
FORTRIINS

.l,SSERT
PIR[ADY
[BOX WILL

WAITt'" T6

SET tNT REO

FOR PI CYCLE

COMP
ADDRESS Ao..::L'ROING

TO BITS OC·-,2

IGNORED

I-[X[CVIRTUAL
4-PHYSICAL

2-3-RESERVEO

0'.0.00.'
,-SU8+1
'-APPLY PROTECTION
ANORElOCATION
'.TQ10BYT[ltfEI'I

D-TOII BYTE X'ER

10-17516

Figure 2-102

EBus Control Hybrid Flow (Sheet 2 of 2)
EBOXj2-130

EBUS
PI GRANT

PI ClK

CYC
START

ClRt

SETf

SHIFT REG
10141

-+ SHIFT 0 IN

"R!O"

T1
T2

TIMEG
-PI CYCLE
- PI CYC
START

......-

.-----..

SHIFT REG
10141
SHIFT 0 IN
T5
T6

COMP

I--

STATE HOLD
2 0'lOAD
-RESET- 1 1·SH0IN
PI ClK- ClK

20'lOAD
I I =sH0IN
PI
CLI(- ClK

PI
TIMER

-TIMER DONE

(See lable
on figure 2-94)
10-1670

Figure 2-103

Time State Generator Control

2.12.5.2 Requesting the EBus - To obtain use of the EBus, the PI logic must set EBUS PI GRANT.
This is illustrated on Figure 2-102. Note that the following requirements must be fulfilled to set EBUS
PI GRANT:
1.
2.
3.
4.
5.

PI test must come up.
REQ must be true (PI 4, 2, 1 = some selection).
The Ebox may not be halted or there are no interrupts selected on 1-7.
EBUS PI GRANT is currently clear.
The PI Board is not trying to set CP Grant.
~

If all five conditions are satisfied, EBUS PI GRANT sets. If the conditions are not currently satisfied,

the interrupt waits.
2.12.5.3 Beginning the Dialogue - At this time, several events take place. The setting of EBUS PI
G RANT enables setting of cycle state, which begins the dialogue. In addition, the PI Timer (see the
·......."..table on Figure 2-104) is loaded with 25 8, which defines the duration of the time state entered, in this
~ase time 1. The'time states are used to direct the EBus dialogue from beginning to completion. EBUS
PI GRANT forces FOO to a 1. This function (4) is PI served and is issued together with CS 04-06,
which are encoded to be the selected channel (5). The interrupting devices (in this example two DSKs)
decode the function lines (,00-02, together with the controller select lines CS 04-06. The PI timer
counts from 25 8 to 378 then, generates TIMER DONE. The devices have now had sufficient time to
decode the CS and F lines so the next phase of the dialogue begins. The timer is now loaded with lis,
Time T1 is removed and T2 is entered.

EBOXj2-131

1111111111111111111111111111111111111111111111111111111IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIrfI~

PI2CLK
PI5 CYC STRT
PI2 TIM I

PI BOARD RUNS AT
MBOX CLOCK RATE

rL
j

L
L
....Jr--l
I
L-

PI2 TIM 2 _ _ _ _ _...J

WAIT IN T5

PI2TIM 3 _ _ _ _ _ _ _ _ _ _ _ _ _ _

vWAITINT5FOR
EBUS XFER

PI BOARD SUPPLIES PHYS CONT TO EBUS FOR API WORD

EBUS
007-010
---lr---1L-

PI2 TIM 4 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1. - - - - - - .

PI2 TIM 5 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--::--......

P~TIM6 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~_~i~j'--------_~

PI2TIM 7 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-,'/-_ _ _ _ _ _ _ _ _ _- '

PI2 COMP _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-,'/-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - '
PI2 STATE
HOLD
PI2 TIMER 16

U
j

U
I

Lr'

LIl..I

I
W'

l.JiiLJ1

UI
I0

LfIJ
L.fi'LJ1

I~l

(

PI2 TIMER4
PI2 TIMER 2
PI2 TIMER I

PI2 TIMER
8,4,2,1 CRY IN

PI2
TIMER
16 CRY
IN _ _ _....J
PI2 TIMER
8,4,2,1 CRY OUT

LOAD

PIR T~~~ ;y'TlMER

~PG~~~~

"--Ir----'

rL..II_
rL..II

'-_____

LOAD
TIMER

LOAD

ILJI
ILJI
'L......,!,I-'L":'"OA:":D------:--:-:-:::-'
LOAD

_ _....JI~,I-'_ _ _ _ _ _- - "

LOAD

TlMER"fL...Jt: TIMER

Ft:;"TlMER

TIMER'):]

LOAD
I'("TIMER

n
n

Il
Il

LOAD
A:::::T I MER

LOAD
R:TIMER

,,,'

T I MER GETS

00-03 _ _ _ _ _ _ _ _ _ _ _ _ _- - 'r------~,jl-'--------------------~L -_ __
EBUSCS

CURRENT STATE

NEW STATE

25 8

PI CYC START

E~~~g~

118

EBUb~

,.,'

34 8

EBUb~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ ___'

25 8

T4
T5

EBUS OEM

LMCH PHYS#',
EBUS XFER
PI TRANS REC

-'r'

'--_ _ _ _ _

===========================:x~-------------------------------------------------I/,;-J
-------------------.:----I';----J

PI2READY _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-.:-_ _ _ _ _ _ _ _ _ _ _-'r---1~

CONPICYCLE _ _ _ _ _ _ _ _ _ _ _

WA~~
FOR
EBU XFER

LWAITFOR PI
CYCLE TO SET

21 8

20 8

35 8

20 8

20 e

COMP

________

~-~
--------~"(----------~I
SET BY MICRD/
PROGRAM

NOTE:
IF PI CYCLE DOES NOT SET BY THE COMPLETION
OF THE TIMER COUNTOOWN DURING T6 THE
PI BOARD HOLDS AT T6 UNTIL PI CYCLE SETS
10-1754

Figure 2-104 PI Timing

EBOXj2-132

(

•J

Time 2 enables EBUS DEMAND. Note that the function PI served and controller select lines are
maintained. The DSKs are commanded to place their "hardwired" physical numbers onto the EBus,
bit 1 for physical number 1 and bit 7 for number 7. Referring to Figure 2-103, DEMAND is held up
through Time 2 and then removed while the F and CS lines are maintained. It is good procedure to
remove the DEMAND signal before attemping to change the function lines; this avoids any spurious
misselection. The timer is next loaded with 25 8 and T3 (a brief time state) is entered. Here, two functions are performed:
1.

The physical numbers, by now on the inputs to a register on the PI Board, are clocked into
that register for arbitration.

The PI Board is timing out a period of time until it is safe to change the function lines.

The next part of the dialogue is begun when Time 4 is entered.
Here, FOO and F02(5) are asserted; CSOO-03 reflect the encoded physical number that has highest
priority (#01) and CS04-06 still reflect the PI channel being served. When Time 4 is removed and T5
sets, DEMAND is asserted once again. This time DSKA is selected as the DSK to be serviced.
DEMAND commands DSKA to place its API word on the EBus and to assert EBUS TRANSFER to
the EBox. The PI Board waits in Time 5 until TRANSFER is received, or forced. If, for example, the
interrupting device (DSKA) can respond to most of the dialogue but cannot send EBUS TRANSFER,
,,\ the PI Board waits. If TRAl'fSFER is not forthcoming, TRANSFER is forced and the EBus (which
\Jcontains zeros) is treated as an API function of O. This ultimately causes a 40 + 2n interrupt on the
interrupting channel. The DSKs service routine must then decide what went wrong. Assume that the
DSKs succeed in placing the appropriate API function word on the EBus and generate TRANSFER.
The timer is loaded with 35 8 and Time 6 is entered where PI READY is asserted. At this point, the PI
Board is notifying the EBox microprogram that the API word is currently on the AR mixer inputs.
2.12.5.4 Terminating the Dialogue - With the assertion of PI READY, the PI Board waits in Time 6
until the PI Handler (microcode handler) looks at the interrupt. PI READY enables INT REQ to set
in the EBox and when the PI Handler detects this, it sets PI CYCLE. Now the timer continues by
entering Time 7, drops DEMAND and finally enters COMP, where the CS and FUNC lines, together
with EBUS PI GRANT, are removed. This completes the PI Boards dialogue.
2.12.5.5 Entry to the PI Handler - Referring to Figure 2-102, the handler is entered at symbolic
location fNTRPT, with the API word loading into AR, and PI CYCLE not yet set. Thus, the PI Board
is at this time in Time 6, waiting for PI CYCLE to be set. The shift counter is loaded with 2, in order to
enable the API word in AR to be shifted left two positions, bringing the function code in bits 03-05
into bits 01-03. PI CYCLE is set and then a shift dispatch is given; depending upon the function 0-7,
the dispatch is to one of eight routines within the main handler.
Function 00 - STD INTERRUPT NO TRANSFER
.
The word is buffered in MQ. The VMA is loaded with the appropriate 40 + 2n address. This address is
- , implemented via the SCD TRAP mixer (refer to Figure 2-60) and derived from number with PI 4, 2, 1.
. PI 4, 2, 1 is simply the octal' equivalent of the channel on which the interrupt was taken. Thus, the
instruction is fetched from 40 + (2 X 5) in the example cited in Subsection 2.8.5.3. This yields an
address in VMA of 0000050.
The program branches to Execute Wait (XCTW) where the microprogram waits for the instruction
fetched to load into AR. This instruction should be a "JSR," which saves the flags and PC and then
enters a subroutine in main memory to deal with the situation. The performing of a JSR causes
SPEC/SA VE flags, which clear PI cycle and set PI HOLD, to hold the interrupt.

EBOX/2-133

F~mcdol1i

02 - 'VECTOR. H'''ITER.RUPT
PtP'I

and an addness space

'VI'V1A.
ote, that

a dispatch is given on ARGO-03 TI:H;; ,6\,1"1
thre:e address
currently tl\;;

o - EXEC

TABLE (EPT)
1 - EXEC VIRTUAL l!lLDDRESS SPA.CE
4 ~ PHYSICAL ADDRESS

PH,]) (iHustrated

is caHed for the
the
bits 27~35
the qualifiers asserted to the

FIgure

1(2).

A,D. T!H: EBox l1:1ake§ an EPT
are as fol1o\A/s:

EBOX REQUEST

VMA
P/-\(] E

:REF

SPEC/SF MEM cycle
number and u.ser
looks at a
either VIvIA
or U PT, depending on
state of user. In this case,
a direct referen(x~ to EP'T. The AR RS loaded
the
is either the first
a
in a service
or an
instruction directing entry to a service
As
40 + 2n interrupt
the instruction
be a
to save the flags and PC. By performing a
PICYCLE
set PI HOLD 011
PI Board. This holds the interrupt.
Vi1ituud Address
the IVI Q.
this case,
from EPT, only
of the addre§s
address
a base address (EBR) to this
address. Here thtneques1t
qualifiers are as foHovvs:
EBOX REQUEST
EBOX READ

MBox
instruction actualliy
EPT reference.

instruction
AR. Then

lFet.d'ming fmm Phy§nc:d Memi()lry
Here,
address contained

to occur,

physical

magic number

vvith

cyde, inhibits th;:; qualifier MAY BE PAGED.

du.ring

MBox

not page the address.

perfonns, One.:;: again, SPEC/SAVE flags

EBOX/2-1

instruction
sets

Function 03 - PI INCREMENT
This function causes a word in the specified address (API word bits 13-35) to be incremented or
decremented as a function of the Q BIT in the API word. If Q = 1, the function is decremented;
otherwise, it specifies increment. Referring to Figure 2-102, the API word is buffered in MQ and Q is
tested. If Q = 0, the contents of the address specified in the API word 13-35 are fetched and
incremented. The incremented word is then stored back in the same address and an instruction fetch is
performed from Pc. This contains the interrupted program. Note that the microcode must set PI
HOLD in order to hold an interrupt on the PI Board. This is done when the 40 + 2n or vector function
fetches and performs a JSR or similar instruction. Here, after completion of the storage operation, the
interrupt is dismissed and PI CYCLE is cleared. PI CYCLE is cleared with SPEC/FLO CTL and
number 02.
Function 04 - PI DA TAO or EXAMINE
he \ 0-\\ interface may perform an Examine function to either core memory or fast memory. In
addition, the address supplied in the API word may be a relocated address or not depending on the Q
IT in the A PI word. Associated with the Examine operation are two words of information for each
\ 0-\\ interface in the system. These word pairs are in predefined areas in the EPT. One word of the
pair is a protection constant, which limits the address of the virtual address sent in the API word. The
number of pages specified in bits 13-26 may be less than or equal to the value of the protection
constant, but not greater than that value. The microprogram utilizes the low-order 2 bits of the physical number supplied to the API word (bits 7-10) and forms an address 140 + 8n, where n is the loworder 2 bits of the physical number for the interrupting 10-11 interface. The physical numbers are
hardwired as 108-13 8 • This gives low-order 0,1,2, or 3. The FPT location thus obtained is accessed for
the protection constant and the comparison is made. If a violation occurs (protection violation), a
word of zeros is transmitted tn the 10-11 interface via the EBllS. If no violation occurs, the relocation
word is fetched from EPT and added to the address supplied in 13-26 of the API word. This address is
now treated as a physical reference and it is not paged. The word is obtained and transmitted via
DATAO function to the 10-11 interface. Upon completion of the EBus dialogue, the PI CYCLE is
cleared. Note that for the 10-11 interface Examine function, the interrupt occurs on channel O.

(

This channel is implemented solely to enable the 10-11 interface to utilize the PI facility at any time,
} whether it is on or off for DMA type transfers. No HOLD flip-flop exists for PIO, so clearing PI
CYC LE effectively releases the PIO interrupt. Devices other than the 10-11 interface may utilize this
operation under the classification PI DA TAO. Two differences in its implementation from that of
Examine exist. First, no protection or relocation is applied and hence no violation can occur. A page
fault, however, can occur. If this occurs, the PF Handler sets IOPF and transfers control to the operating system. The second difference is that other devices interrupt on channels in the range of 1-7.
Once again, holding the interrupt for this one time transfer is unnecessary and only clearing PI
CYCLE is necessary to release the PI Board. Other than these differences, the operation is identical to
Examine.
Function 05 - PI DATAO or DEPOSIT
I n terms of the 10-11 interface, this operation is the reverse of Examine, except that after the 10-11
interface sends the API function (which contains the address), the EBox must perform a DATAl
function to obtain the 36-bit word to deposit in the specified address. A second difference is that if a
violation occurs, after performing the protection check a violation occurs, no word is stored in the
specified address. With these exceptions, the operation is basically the same from the point where the
36-bit word is obtained from the 10-11 interface to the completion of the operation.

EBOX/2-135

Function 06 - PI BYTE TRANSFER
This function can only be carried out betweerr'a 10-11 interface and the EBox. This function is initiatecj
on PI channel 0 as are Examine and Deposit. The transfer is part of either a TO 11 or TO 10 byte transfer
occurring in the 10-11 interface. The information being transferred is either a byte right-justified in
EBus bits 28-35, or a word right-justified in EBus bits 20-35. The API word specifies whether the
transfer is TO 10 or TO 11 by the state of the Q BIT. If Q = 1, the transfer is TO 10; otherwise, it is a TO 11
transfer. In addition, the PI Board is supplying the physical number in bits 07-10 of the EBus while the
API word is present. The other portions of the word 0-2, 11-35 are ignored.
TOtO Byte Pointer Fetch, Byte Read, and XFER
The low-order two bits of the physical controller number 0, 1, 2, or 3 are obtained and combined with
EPT base location 14X to form the EPT location of the TOll byte pointer. Next, the byte pointer is
obtained from the EPT and updated. The pointer is a standard KLIO byte pointer. The microcode for
load byte instructions is used for the pointer update. Note that the byte pointer may specify indirection
and/or indexing. Once the effective address has been calculated, the updated byte pointer is stored
back in its slot in EPT and the byte is obtained by performing an EBox request. Finally, the byte now
in AR is transferred via the EBus (DATAO) to the 10-11 interface and PI CYCLE is cleared.
TOtO Byte Pointer Fetch, Byte Transfer and Storage
The byte is initially requested by issuing a DATAl to the 10-11 interface. The byte is then picked up via
EBus 28-35 and loaded into ARX and into BRX. Next, the low-order two bits of the physical controller number 0, 1, 2, or 3 are obtained and combined with EPT base location 14X to form the EPT
location of the TO 10 byte pointer. The byte pointer is obtained from the EPT and updated. The pointer
is a'standard KLIO byte pointer. For the TOll XFER, the microcode for deposit byte is used for the
pointer update and, as with the byte pointer for TOll XFER, may specify indirection and/or indexing.
Once the effective address has been calculated, the updated byte pointer is stored back in its slot in the
EPT and the byte is stored in the pointer's effective address. Finally, PI CYCLE is cleared and this
terminates the operation.
Function 07 - UNASSIGNED
This function is unassigned and currently behaves the same as function 00 .

•

EBOX/2-136

SECTION 3
LOGIC DESCRIPTIONS

In this section, a selection of the twelve board types comprising the EBox are described in detail.
Wherever possible, a functional perspective is given to highlight the particular functions a board or
portion of a board implements, and multiple boards are shown interconnected to aid in tracing various
control signals from one functional area to another.
PHYSICAL CONFIGURATION
The EBox consists of a total of 23 modules, configured as indicated in Figure 3-1. A brief description
of each module is contained in the following paragraphs.

Module M8532, Priority Interrupt Control (PIC) - One board, illustrated on customer prints PIC
1-6, contains PION register 1-7, PI GEN register 1-7, PI REQUEST Register 0-7, PI HOLD
register 1-7, and the PI ACTIVE flip-flop. In addition, it contains the priority interrupt networks
for arbitration of priority interrupt requests, EBus dialogue logic, control and internal timing,
and the assignment registers for the ABR: PIA APR 1,2,4 and Meter PIA 1,2,4.
Module 8526, Clock (CLK) - One board, illustrated on customer prints CLK 1-6, contains the
crystal-controlled master clock oscillator and crystal-controlled margin clock oscillator, as well as
Source and Rate Selection registers and their associated logic. It contains logic and counters to
produce the EBus clock, SBus clock, MBox clocks, and EBox clocks; In addition, it contains
single step, burst, normal, and diagnostic mode logic and registers. It also contains MR reset,
EBus reset,crobar logic, error detection logic, page fail, and MBox request logic.
Module 8539, Arithmetic Processor Status (APR) - One board, illustrated on customer prints
APR-7, contains an 8-bit APR Status register, 8-bit Interrupt Enable register, and associated
interrupt request detection logic. It contains the EBus dialogue control logic used while performing I/O instructions. In addition, it contains'the address break compare enable bits, fetch
comp, readcomp, write comp, and user compo It contains a 5-bit section register, fast memory bit
36, RAM storage, and parity network. It also contains the fast memory block and word addressing logic, mixers, adder network and current, previous XR, and VMA Block Selection registers. It
also contains MBox control and MBox register function decoding logic.
Module 8525, EBox Control No.2 (CON) - One board, illustrated on customer prints CON 1-6,
contains CRAM condition field decoding; COND and SKIP enables; and VMA select lines CON
VMA SEL 1 and 2. It contains meter, interrupt request and interrupt request detection logic, run
and continue logic, IR strobe, DRAM strobe, start logic, various flip-flops, and associated sychronizer logic. It also contains the NICOND decoding and COND ADR bit 10 logic. It contains a
4-bit State register, diagnostic function decoding logic, Parity Enable register, Cache Strategy
register, paging enable, trap-enable bits, and I/O control signals for CONO APR, CONO PI,
CONO PAG, and DATAO APR. It contains the Load AC blocks and Load Previous Context
signals, 4-bit Microcode State register, AR and ARX bit 36 with associated logic, fast memory,
write logic, various PI control signals, and associated logic.
EBOX/3-1

Z-£/XOH3

XCD

orn~~x

M8532
PI CONTROL

M8526
CLOCK

VI
VI

M8538
METERS

M8539
APR

M8525
EBOX CONTROL # 2

-I>

()I

M8527
EBOX CONTROL # 1

-.j

BACK PLAIN JOINING

VI
CD

MB528
VMA

M8512
DATA PATH BITS 30-35

-I>
0

M8528
CRAM BITS

:!!

M8512
DATA PATH BITS 24-29

-I>

M8528
CRAM BITS

-)
-.
"Tj

0tI
~
'"1
(\)

Yo.)

•

..tI1

Ij;j
0

><
~

0
0..

S
(\)

N·

-I>

-I>
-I>

{8-11
M8528
28 -31
48-51
CRAM BITS
68,70

-I>

M8511
CRAM ADDRESS

IlJ
.......

o·
::s

{12-15
32-35
52-55
72,74

M8512
DATA PATH BITS 18-23

{16-19
36·39
56-59
76,78

()I

-I>

M8510
SHIFT MATRIX

-I>

M8530
MEMORY CONTROL

-I>

M8522
IR, DRAM ,CARRY

-.j

-I>
,tD

()I

-I>

M8512
DATA PATH BITS 12-17
{ 424-27
-7
M8528
CRAM BITS
44-47
64,66
M8512
DATA PATH BITS 06-11
{ 0 20-23
-3
M8528
CRAM BITS
40-43
6062
M8512
DATA PATH BITS 00-05
M8524
SCAD

Module 8527, EBox Control No.1 (CTL) - One board, illustrated on customer prints CTl 1-4,
contains CRAM dispatch, field decoding, some adder carry control logic, and register mixer
selection control logic for AR, ARX, MQ, and PC. It also contains the majority of the diagnostic
decoding logic and the translator enables T to E enable and E to Tenable.
Module 8523, Virtual Memory Address (VMA) - One board, illustrated on customer prints VMA
1-6, contains an 18-bit VMA adder, VMA AC reference detection logic, a 23-bit VMA register,
and associated input mixing logic. It also contains a 23-bit Address Break register, associated
match logic, 23-bit Program Counter register, 23-bit VMA Held register, and AR Mixer Mixer
(ARMM) logic bits 13-17.

Module 8528, Data Path (DP) - Six boards, illustrated on customer prints DP 1-5, each contain
six bits of a full 36-bit data path. Each board contains the following mixers: AR ryfixer (ARM),
ARX Mixer (ARXM), MQ Mixer (MQM), ADA Input Mixer, ADB Input Mixer, ADXA Input
Mixer, and ADXB Input Mixer. In addition, each board contains the following registers: Arithmetic Register (AR), Arithmetic Register extension (ARX), Buffer Register (BR), Buffer Register
extension (BRX), and Multiplier Quotient register (MQ). It also contans fast memory, the adder
(AD), and adder extension (ADX). In addition, it contains the fast memory, write pulse generation logic, and fast memory, write pulse generation logic, and fast memory parity network.
Module 8512, Control RAM (CR) - Five boards, illustrated on customer prints CR 1-7, each
contain 14 bits of the control word (microinstruction) stored in RAMs containing 1280 words. In
addition, each board contains CRAM address gating and 14 bits of the CRAM output register
(CRAM register).

(

Module 8511, Control Ram Address (CRA) - One board, which is illustrated on customer prints
CRA 1-6. This board contains the circuitry to generate the address of the next CRAM word. This
includes the microcode push-down stack, plus the Dispatch and Skip logic.
Module 8510, Shift Matrix (SH) - One board, illustrated on customer prints SHM 1-5, contains
shift counter decoding logic, shift matrix, and AR and ARX parity networks.
Module 8530, Memory Control (MCL) - One board, illustrated on customer prints MCl 1-7,
contains CRAM MEM field decoding; memory request enable logic; request type decoding, e.g.,
MCl VMA Read, MCl VMA Pause, MCl VMA Write. It also contains User and Public
Enable logic, as well as all the request-type qualifiers. It contains bits 1-12 of the VMA Held or
PC Mixers, together with various VMA Control and Selection logic.

(

Module 8522, lR, DRAM, and Carry (IRD) - One board, illustrated on customer prints IRD 1-5,
contains the 13-bit Instruction register (IR), 4-bit IRAC register, DRAM address mixers,
DRAM, and IS-bit DRAM Output register. In addition, it contains the IR Test Satisfied logic
and normalization CRAM address bits (IR NORM 08-10). It also contains the AD and ADX
carry anticipation networks (CARRY SKIPPER).
Module 8524, Shift Counter Adder (SCA D) - One board, illustrated on customer prints SCD 1-6,
contains the 10-bit Shift Counter register and associated input mixer, 10-bit Floating Exponent
register, and associated input mixer, AR Mixer Mixer (ARMM) bits 0-8, and SCD TRAP Mixer
(32-35). It also contains the lO-bit Shift Counter Adder (SCAD) as well as the Program Counter
Flags register and mode control logic.

(

3.1 INSTRUCTION REGISTER LOADING AND CONTROL
Refer to Figures 3-2 and 3-3. The IR is composed of 13 mixer latches as illustrated. The default
selection is AD selected by -ClK MB XFER. The alternate selection is the cache data lines selected by
ClK MB XFER. Because the IR consists of latches (DC devices), the clock is used indirectly to
synchronize unlatching and latching of IR. This is done by ORing the EBox clock with the control
signal on the IR Board. Unlatching the IR may be accomplished in one of three ways.
EBOXj3-3

-:f

I VMA BOARD

I
VMA 13-35

rZo"N;;- - - - - - - - - - - - - -

I
I

,13_ _ _ _---:-:-.;..,35

VMA 1

-:;

AC
REF

L
I

VMA AC REF

~-CL-

-- -

-I

OUALIFIERS TO MBOX

t.lCL

LOGIC

~ W~f?-

.----.....FM

~~~

:::(

I-I-__

WRITE

REO EN-

PAUSE f--

READ

I
I

DIAG DRAM STROBE-t------I
CON LOAD DRAM
CON
j-F_ET_C_H_-,-CY--,C...::;L",E

-tll-~E_\_LC_:_M_A_'I ~I1-----4------,
II

LOAD

L_MC~L=~L~_.J

CON CLK- _

l _ _ _ r-- _ _

COND/IR LOAD

~---:OD~~--

ONIIO
LEGAL

~ ~

C:L.>-

I IR I/O LEGAL

CON
2 0
DIAG IR 3 0
STROBE 4 E
R
_

FQ II

R~N

D_COND/LOAD
IR

==1

11--<

C-CON CLK

II-I-+-,--"--'---+-t-I, +-----+------'

L ;:

CO~¥~OL

C-CON CLK

~
~~
MBOX·
r-l----/

CYC REO

OTHER
~ OUALIFIERS
-FROM OTHER
BOARDS

~-NICOND

L ______ U

- ----1

I- DIAG

CONTROL
FUN C 01 X

E
B
U

EBUS 004-06

I
I

(

--------J

__ - _ _

~~;;R;---i

MBOX

&...

M EM

COND

I II

~C~

1/1

:::.---=-=-. J
(

I
I
I

MBOX RESP IN

EBOX REO
CLK EBOX
MBOX

I
MBOX SYNC

CHS EBOX
RETRY REO

EBOX SYN CEN

CSH EBOX T0

·1

CLK MBOX CYC DISABLE
RESET
CLK PAGE FAIL EN

Figure 3-2

CON
MBOX WAIT

(

-VMA AC REF-

I
I
I
I

::!:

10-1671

IR DRAM Control (Part 1)

EBOXj3-4

DRAM ADR 00-02

I---3

EVEN HALF
256X3

EVEN HAL1'
256XI

EV,N HALF
56X3

i
I

COMMON
256X3

COMMON

··
·

COMMON
256XI

256Xl

])-1
SEL

2377
I 720

I NACCESS IBLE
1717
1700

I
DRAM ADR 03 -05

EVEN HALF
256X3

FOR NON 1 0 - - 1
INSTRS
56
8 9
12

INACCESSIBLE

I 277
I 220

INACCESSIBLE

I 177
1120

INACCESSIBLE

I 077
I 020

1217
1200

DRAM ADR 06 -07

FOR
ALL
INSTRS

'''7
1100

IF IR
3-6'0
LOCAL

r-:

Il~6~~
7-9'

LOCAL
DEV

ODD HALF

/'S'EL
12

IAIIl-2X

opi
CODE
DRAM ADR OIL\

I--- FOR 10 INSTRS---j
IR011l-02'7~

0
HOLD

INSTR
7XX

r--0
I-- DIAG 04-06
r - - SET
~I
~
I
2
IR EN
3
IO
4
JRST
CLR
5
,-- 6
t - I-- 7
I--DIAG LOAD FUNC 06X
'--~

-r;--F
IR EN
AC
0

ODD HALF
256X3

256X3

CLR

'---

~EL

'L
1

~~EL

CLK IR

HOLD DRAM

IPARX

1J01-03

IPARY

\~EL

ODD HALF
a56X3

1
\~EL

I
2

HOLD

P
HOLD

I
HOLD

1
I

-IR

I
J

fill

IJ0

JRST~~EL

I
3
HOLD

770
767
760
757
750
747
740
737
730
727
720
717
710
707
700
667

0
SEL

4
J

HOLD

034-774

RESERVED

030

MTR

024
020

CCA

014

~ ~HO~D

010

/.1

004

;:::/,~
~/

255

JFCL

254

JRST

I1ARITY
I J

\~J

07
J

I I

IJ
I

OY
J08 1
-

IRIO-I 2

000

ALL OTHER INSTRS

JRST, JFCL
'/ / / / / / / / / / / / // / / / /

~~~MCL~~~ ~~~~6~-

ODD

§--DRAM JOI-04

5
PARITY
NET

~ ~ORAM
10

12
13
14
15

J07-10

4m
3

577
520

INACCESSIBLE

477
420

40 0
377

INACCESSIBLE

320

30 0
277

INACCESSIBLE

220

21 7
20 0

~ErDRAM

INACCESSIBLE
51 7
50 0

THE AREAS MARKED
INACCESSIBLE ARE
NOT ADDRESSABLE
VIA THE
DRAM J FIELD,

3\ 7

677
620

6\ 7
60 0

I
0

720

41 7

ODD

777

I NACCESS IBLE

IOJ

1017
100 0

71 7
70 0

PAG

~:%~

IR09

DEV SEL

APR

\0 !
SEW

7
PARITY J

JRST~~EL

'HOLD
TIM

t:r

ALL OTHER DEVS

IJ07

777

256
-CON LOAD DRAM

B0-2Y

IB0-2X

AIil 2Y
-

ODD HALF
256Xl

AOO-02

BOO-02
DRAM
5
'
6
PARITY 7
NET
8
9
10
" ----;DRAM PARITY
12
13
14
15

177

INACCESSIBLE

120

11 7
100

I NACCESS IBLE

7
0

------.J

~ CRAM ADDRESSES
r---INACCESSIBLE TO DRICM---'l
"HARDWARE ADDRESSING MISSING"

L __ DRAM

STORAGE~
ALLOCATION ~

Figure 3-3

IR DRAM Control (Part 2)
EBOXj3-5

During an instruction
qualifiers

together
EBox React
the ERax
They are
reason, MEIvl

setso It
one of t'l~;VO events oc~;;urEL
cycle, or
XFER oC:CUl'S response to an internal
feedback path
MEIVI CYCLE mp~nop,
FETCH are
is
because ~COl"'J LOAD

COND

The operation
unlatching ami loading in. this lTumner
one
Note
eLK 1R i:~; RogicaHy ORed
,·COl'"T LOAD
Figun;:

CR.~,1\l REG

EBOX CLOGlI

E'Se})!.:

SV!~C

-=''\,.

f'rrED~--~~-~~'--~~----'=,

'~__

MICRO
IHSTl'~UCTIOi\l
_
_
_

l~._~~

_ _ _ _~.- - - . I

,,<

:,"

,,~'-~~=~--=-

MICRO_
li·1STRUCTION
>.:.
_ ._~_ _ ~~/ -,

~~,,~~~._

_ _ _JI~_,_ _~~~~.~I
i

~--~~--,

L - _ .~.~._.~._I

COND/LO,O;O 1R

ADIA

ADA/A,R

_/~

10-1673

cwU''''''Hl,;e;

Via AR (COND fLOAD

tRy
or
IS

AD, it is sometimes necessary to UBI;: the COND f!R
to Figures 3-2
bits 32~·35
fast
ADRfield.
. The

L
memory as
selects AD
COT'Il"D field is
()nce

note

and

H{ is in step

EBox dock (eLK IR) .

CRAM REG

EBOX CLOCK

==><
~

X
L

COND/LOAD IR

AD/B~
ADB/FM

~
UNLATCHES

ILATCHES

IR MIXER IN _ _ _ _ _ _ _ _----'XFM DATA

X,-__

EBOX SY NC

FM ADR

/
-----'

FM DATA

_ _ _ _ _ _- - - - J

Figure 3-5

Loading IR Via FM (COND jLOAD IR)

3.1.1 DRAM and IRAC Control
The DRAM register is controlled in a manner similar to that oflR. The DRAM register consists of19
mixer latches. Refer to Figure 3-3; unlatching the DRAM register may be accomplished in one of three
ways. As with IR, note unlatching and latching of the DRAM register is synchronized by ORing the
EBox clock with the control signal on the IR Board.
"Each time that the COND jLOAD IR function is Ilsed to unlatch the IR, it also enables the generation
orCON LOAD DRAM on the next EBox clockLThus, the IR unlatches beginning with the trailing
edge of one EBox clock and latches on the leading edge of the next. Similarly, the DRAM register
unlatches beginning with the trailing edge of the EBox clock that latched IR, and latches once again on
the leading edge of the following EBox clock. The timing is illustrated in Figure 3-6.

•

A similar operation takes place following NICOND Dispatch. Referring to Figures 3-2 and 3-7,
NICOND is latched into a flip-flop on the control board at the same time that the microinstruction
selected by the NICOND Dispatch loads into the CRAM register.

Here we assume the case where some instruction has completed its store cycle. An earlier microinstruction generated MEMjFETCH which started the EBox Request.

EBOXj3-7

CRMf. REG

COND/LOi\D IR

If1rtill:~(ER

:IIIPUTS

"'=-""""r."

~"'\,~,,~'~~-~--'-'--'--~'~~'--~-',,~.~-~-,-~'=~":'''''''''''''''''''''-

,'-

_~"_,>\,~""~ __,__~~",~~__" ,.~._."_~~_~_~~_. __ ~_"~.~__'""_.~.~._~~.~._.~~~
Jt=--~-~·-··U_'-~~-~~~--~~,

CON

/
-----..-.~'"
LA7CHED

IRAC

(IRAC 09-12.,,- IR 09-12)

!i.

UH L ATCHED

\_----~~-~--~~

I~--~-'~---'~' ~~.~

LATCHED
10-1675

Figure 3-6

DRAM

Following

DR.AM Addre§sirng ~md '-''''.,'''',... '"'''
DR EN 10, JRST,
into the DRAM

DRAM
,ilkS

indicated on the figure,
device is
to

zero~

APR:DEV
PI: DEV

. DEV 1010
OCA: DEV 014

c.~-

CRAM REG

SEE NOTE 1

><=
I

EBOX CLOCK

EBOX SYNC

NICOND DISP

LATCH ON
CON BOARD
CON
LOAD DRAM

UNLATCHED
LATCHED

DRAM REGISTER

LATCHED

MEM CYCLE

MCL VMA
FETCH

UNLATCHED

IR
INSTR
ARX

(

LATCHED

LOADS~

CLK
RESPONSE MBOX
MBOX DATA

NOTES:
1. Micro Instr Asserting NICOND
Disp and Woiting for Instr.
2. Micro Instr Selected According
to N ICOND Disp .

to- 1676

Figure 3-7

NICOND Dispatch and Waiting

If IF. bits 3-6 are nonzero, the device is external to the processor. This includes device select codes 034
to 774.
All other op codes in the range of 000-677 address locations in the DRAM that correspond to locations 000-677. This is illustrated in Figm:e 3-2. DRAM address 00-02 is formed from IR 00-02, while
DRAM address 03-08 is formed from IR 03-08.
AC decoded jumps JRST and JFCL reference locations in the DRAM that correspond to their numerical op codes (254 and 255, respectively). The DRAM register is loaded specially for JRST. Note that
IR JRST (Figure 3-3) forces DRAM register J4 to zero while enabling DRAM J07-1O to be input from
IR 09-12. This enables the microcode for JRST to be entered at the appropriate location relative to the
type of code in IR 09-12.

(

DRAM register bits 00, 05, and 06 are missing in the hardware (Figure 3-3). This prevents DRAM J
Dispatch from accessing certain CRAM locations.
EBOXj3-9

,3,:£.3

SATiSFIED
It is

with

CA1VKXX
CAl.IXX

JUlv1PXX

sosxx
SOJXX
AOIJJX
instructi.ons test S(HlH')
or conditions,
dept'!ll1ding UpOl.l
result
The fetch can be from tl~C+ 1 or PC+2, (in the case of CiUXX, CAMXX,
TXXXX, and BLKX), Olr from E
PC+- 1 (ill the CBlse of
AOJXX,
1ll1!ll,X;~~~'H;!Jmtathm ~ To suppleru le nt this section, five tables tH'le prf;sent\~d (Tab1es 3 1 throll.gh 3~
which aid in understanding the taMe
Figure 3-8. Tablie 1 is Skip,
Compa.re
controls.
is divided
areas, Eight Skip, Jump,
are indicated,
These are microcode
indicated coding of
DRAM field and imply the type
Jump, or Compare condition being tested,
example, the nrlStructiol1 CAIE compares the
address with the contents of AC
next instruction in the program sequence if
condition is satisfied. The DRAM B field mnemonic is "SJCE," which is at value of 1 in DRAM B. The
coding of DRAM SO controls the sense the
Thus, referring to Figures 3~9 and 3~1O, IR
SATISIFIED is the
of DRAM BO
the §ignaJ indicated on the figure as "resultanL"
Kn
current
to zero, the IF. TEST SA,TISFIED signal is tn.l l<::
onliy if the "resultant"
is true,
3,L:~,2

As inoj(';ated
Figure
of
:= 0
DRAM 13 OR (0)
CRAJ~.1 #070)
enables "resultant" to be true, This yields
TEST SATISFIED. Referring to Figur~ 3-8, the VIVIA
which it received at AREAD
The
field
is PC+ 1 [CRftLlIcII V1VIA SEL 1
(O) /'.CRAM
SEL 2 0)], Because
1 INHIBIT is false at this time, the ":8" input to VMA
AD i§ equivalent to + 1, while
VIvlA ilicD function is "A + R'"
field function is
"FETCH," and the lnagnc
field function is "corv[p FETCH,"
is coded as i¥20L Thus,
0) with "FETCH" and IR TEST SA,
MeL SKJf11 g,ATISFIED, Providing PI
is clear,
INC incn::r,nents
is now PC+ 1, to a
of

bit of the CRAM
load gate
that IR
TEST SATISFIED or roMEMjCOl'·lD
is nece§§ary to anow
SATISFIED to
loading the
during Jump-type
VMA, contained the
add.ress prior to
that the
number field function and ME:M
instructions is different than
COfnpares. It lis necessary to prevent PC+2
occurring
by blocking the term !ltfCL SKIP SATISFIED. Because the
nuraber field ftH1ctloJr1l for jumps, 'which is "'JUMP FETCH,." has #01 (0), the gate is inhibited, If
test is fwt satisfied,
with PC+ 1 and
operation continul'::§.
EBOXj3

•

(

r.-----------,

~~o~----l

rco~,,:;~o;;D-1

I
I
I

I
I.

I
I
I

VMA BOARD

I
r

VMA CONTAINS
IE INITIAllY
SEl2
SEll

I
KI

I
I
I
I
I _ _ _ _ JI

MCl VMA INC

PI
CYCLE

I
I
_____ J

CON
ClK

I
I
IL _ _ _ _ _ _ _ _ _ I
-PC+I
INH
CRAM SEl2

--.J

#01 (1\ See Table
-MEM/COND JUMP. MEM/COND JUMP. MEM/FETCH
"!

CRAM VMA SEl2. CRAM VMA SEll. VMA/PC+1

tI1

=
~
-

..........
W
I

------~ I BOARD

-----------, r

- - DRAM REG-----l

IR TEST SATISFIED

"CONTROLS SENSE

I
I
I
I
I

I
I

I
I I
I I

I
I

I I

CRAM
#01

CRAM
#02

0
0
SKIP=I
JUMP=O

IL
I

SELECTION
INSTR
USED FOR
FOR

CRAM CRAM
#07
#08
0

UNUSED

SKIP=O

JUMP=I

G or E

SKIPX
JUMPX

NOTES

NOT USED CURRENTLY

CAMX
CAlX

THIS SIGNAL
IS EQUAL TO

OR BOTH

G=(AD00 ¥ ADCRY-02) 1\-#06 IF AD!Il!ll ¥ ADCRY-02
E=(AD=OO)I\-#Ol
IS TRUE ADA> ADB

l or G
OR BOTH

l= AD00 1\ - #07
G= (AD=OO) 1\ -#01

IF AD!Il0 = I THE AD
IS NEG

I I
I I

I I

CL""

I .

I
9' I
9'

CRAM
ClK

I I

ADCRY-02
X
AD CRY!Il
I
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 'J
TXXX

---,

I ,,"''''IVI

I
I

J
'-------I

ov""nu

,0-,677

Figure 3-8 IR Test Satisfied

IR TEST SATISFIED
DRAM.,08
DRAM#07
10-1678

Figure 3-9 IR Test Equal

-DRAM B02

-DRAM B01

CRAM#07

CRAM#08~___~~==~t---~A~D~=~0~~jl-J
ADOO

A>B

-CRAM#07
IR TEST
SATISFIED

ADCRY-02
AD/XOR
CARRIES
A-B-1

-CRAM#08-_-,

(

- ADCRY-02--",,--.J '-..
TEST
}()---"
' " CO N S 0
CONSZ

ADOO

BlK I
BlKO
NOTE'
Comp
Skip
Test
Jump

fetch' 201
fetch' 202
fetch' 203
fetch' 102
10-1679

Figure 3-10 IR Test Satisfied Logic

Table 3-1 Skip, Jump, Compare Controls
DRAM B Field

Skip, Jump, Compare Controls

Controls Sense of Skips, Jumps, and Compares

DRAM BOO
3
2
1

•

7
6
5
4

o
o
o
o

SJCSJCL
SJCE
SJCLE
SJCA
SJCGE
SJCN
SJCG

NOTE
See Table 3-4; uses Skip or Jump fetch with various AD
functions.

EBOXj3-12

(

Table 3-2 Test Controls
DRAM B Field

Tist Controls

Contro18 Sense of Test
DRAM BOO

TNTNE
TNA

o
o

TNN

4
5

1
1

TZTZE
TZA
TZN
TCTCE
TCA
TCN
TOTOE
TOA
TON

5
6
2
2
6
7
3
3
7

o
o
1
1

o
1

NOTE
See Table 3·4; uses TEST fetch with various AD functions.

Table 3-3 CONSX and BLKX Controls

•

DRAM BField

CONSX, BLKX Controls

BLKI

TEST FETCH
TESTBRL

BLKO

TEST FETCH
TESTBRL

CONSO

TEST FETCH
TEST ARBR

CONSZ

TEST FETCH
TEST ARBR

Contro18 Sense of
CONSX, BLKX, Skip
DRAM BOO

COND Causing Skip

,
1

EBOXj3-13

Table 3-4 Fetch Control Modifiers

Magic No. Field

FETCH

201

SKIP FETCH

FETCH

202

BLKO, BUG,
CONSO, CONSZ,
TXXXX

TEST FETCH

FETCH

203

JUMPXX

JUMP FETCH

FETCH

102

Actual Instruction
Using

Microinstruction Function

CAMXX, CAIXX

COMPFETCH

SKIPXX

MEM Field

Table 3-5 CRYO Generation (MACRO)
Instruction That Uses
BLKI,BLKO
CONSO, CONSZ
TEST
TEST

CRYO Generators Used

AD Field Function

TESTBRL
TEST AR-BR
TEST AR-ACO
NO CRY

Additional Signal

ORCB+l
CRY A-B#O
CRY A-B#O
SETCA

GENCRY 18

Figure 3-10 illustrates the actual logic that develops IR TEST SATISFIED. The use ofthe E, G, Land
X portions is indicated. The result of the test in the AD determines one of the conditions on each gate.
For Equal (E), the term is straightforward AD = O. In the case of Greater (G), the Exclusive OR of the
sign of AD (ADOO) with a carry out of the AD sign (AD CRY -02) produces the A >B output when
AD is performing the Exclusive OR function. For example, assume CAIG AC, 010101.
AR
AC

= 000000, 010101

= 000000,007777

;O,E
;(AC)

The function performed in AD is:
ADB+-FM; (AC)
ADA+-AR; 0, E
AD = XOR
Note that while the AD performs the logical function XOR, the carry function is A-B-l (Table 2-8,
ALU Functions). Therefore, the ADB input is 000000,007777 and the ADA input is 000000,010101.
The operation is as follows:
Is complement of ADB input____ 000000,010101 ...
777777 770000
ADCRY-02

ADA Input

000000000101 - - - - - Adding the Is complement
of B to A = A- B-1

EBOXj3-14

Note that the following relation is true:
-B

= H±1

-B-1 = B+l -I
-B-1 = H, which is the Is complement of B.
XORingAD CRY -02 with ADOO, which is 0, should indicate A

>B.

For less than (L), the term is ADOO, and this indicates the AD result as a negative value. Skips utilize
the Boolean AD function A. Here, the carries function is really A -I. Thus, if the instruction is SKIP L
0, E, the contents of E are compared with zero and a SKIP occurs if (E) is any negative value. The
implementation follows:
X: SKIPL 0, E
(E) == 777777, 777774 ; -4
AR = (E)
The function performed in AD is ADA .-AR, AD = A and effectively the (AR) is compared to zero
because any negative value in AR satisfies the SKIP until a value of zero is placed in AR. This turns off
ADOO.
The remaining term (X) is used during TEST, BLKI, BLKO, CONSO, and CONSZ instructions. The
AD carries function is AB-1. For example, assume the instruction is CONSO DEV, 1. At the time of
the test, BR contains 000000,000001, the effective address, and AR contains the bits (if any) from the
device. The implementation follows:
BR
AR

= 000000,000001
= 000000,000001

;O,E
;assume the bit was set in the device

"AND"

000000,000001
000000 00000 1

For the carries function add - 1

000000,000001
777777,777777

AD CRY -02

•

000000,000000

Here ADCRY -02 inhibits the (X) function but DRAM BO is coded to enable the IR TEST SA TISFlED condition: The PC is updated by +2 and loaded into VMA (Figure 3-9). If the instruction were
CONSZ DEV, 1 and the device flag was not set, the AD function [000000,000000-1] yields -I and -AD
CRY-02. This satisfies the (X) function and DRAM BO is clear. Once again, the IR TEST SATISFIED condition is satisfied and the SKIP occurs.
3.2 PROCESSOR TIMING
The KL 10 is a synchronous machine. Figure 3-10 illustrates the basic clock layout and distribution.
3.2.1 Clock Overview
The clock resides in the EBox and contains a selectable source (Figure 3-12). This source can be a
crystal controlled 50 MHz oscillator, for normal processor operations, but may be an external source
for special applications or a 56 MHz crystal-controlled oscillator for speed margining.

Basically, the clock consists of three other rather distinct sections: the clock control, the EBox clock
control, and the clock diagnostic control labeled CD , ~ , (J) ,respectively, in Figure 3-13.
EBOX/3-15

~,~

DMA-20

~
ClK SBUS'I ClK

MEMORY

sLt :)

SHIFT
MATRIX
BOARD

CRAM ADR
BOARD
CRA

PI BOARD
PI

r----- ------,
I
I~
I
I
I
EXT

CLOCK
SOURCE
ClK CONTROL

ClK PI
ClK SELECT

ClK MB 00

•

ClK FUNCTIONS

ClK MB 06

-+_--;

I
I

I -\

C=.;lKc....:.:;Mc;:cB....:Ic=2_ _t w..::c

,...
I
....
Cl;:;.;K,,;....:..CH'-'--_ _f--I---l
ClK CHS
CLOCK
I
!+"C..::l'-'.K-'C:..;,H'-X'--_-+_--ICONTROl
ClK MBC

ClK CRA
Cl K CRM

ClK ODD

14-"'=-.;='------II~---l
MBOX

~~..::~.:.::....::.:::::..::=------=--I---l
~C..::;l.:.:K-C:..:C:.:W'----t_I---l

ClK MBOX 13
ClK MBOX 14
C
B
U

ClK MBX
ClK PMA

CLOCK
DIAGNOSTIC
CONTROL

50MH{ FREE

t--=C..::;l:,.:.K....:C:.;..R:;:C_ _

CRAM
BOARD

~~: :B:~X SOURCE

VMA
BOARD
VMA

,--.

EBOX
CLOCK ClK VMA
CONTROlr:::..:....-='-'-I----'
ClK EDP I
ClK CON I

I
ClK ClK APR
CONTROL ClK IR

ClK SCD

PAGE FAil HOLD!

L - t - - - - - - I - - - - ....

ClK EBOX S Y N C . 1

EBOX
CONTROl#2
BOARD
CON

EBOX
CONTROL #1
BOARD
CTl

I
I

ClK DK20

DATA PATH
BOARD
EDP

ClK MCl J
CLOCK ClK ClK
CONTROL

C--

MEMORY
CONTROL
BOARD
MCl

L.....:to

APR
DIAGNOSTIC
BOARD
APR

ClK EarS ClK
A

IR AND
DRAM BOARD
lR

E BUS

•

11 v

DTE-20

RH-20

•

DIA-20

SCAD. PC •.
FLAGS BOARD
SCD

DK20
10-1680

Figure 3-11

Clock Basic Block Diagram

l
EBOX/3-16

50 MHz ~ - - - ---,0-----------

EXT
SOURCE

64 MHz FREE
EXT

EJ----

66 MHz FREE
10-1681

Figure 3-12 Clock Source Simplified

CLOCK
SOURCE

50MHz

•

ClK PI

SBUS CLOCK
CLOCK
CONTROL

EBOX
CLOCK
CONTROL

S
B
MBOX-QU CLOCKS
S

j CLOCK
EBUS
CLOCK

CLOCK
FUNC
GATE

CROWBAR

ClK
SEl
SOURCE SEl

RATE SEl
ClK GO

- D - E BOX
Cl OCKS

CLOCK
DIAGNOSTIC
CONTROL

...
EBUS

"
PO WER
CON TROl

lOAD

DS04-06

CONTROL
CROWBAR

EBOX
CONTROL
#1

STROBE
DSOO-07

~
10-1682

Ficure 3-13

•

Basic Clock Block Diagram

3.2.2 Crobar and Clock Initialization
When the KL10 system is powered up, the EBox clock board must be initialized to a known state. In
addition, the device controllers on the EBus must be initialized and a series of MBox, EBox, SBus, and
EBus clocks must be generated for various initializtion purposes. First. the power controller asserts
CROBAR for approximately 5 seconds. This signal is passed to the clock diagnostic control logic,
where it enables the initialization process. The clock diagnostic logic contains a 2-bit source selection
register, a 2-bit rate selection register, and various other registers and logic. During power up, the state
of these registers is undefined. To avoid an improper source selection, the clock CROBAR signal is
used directly to select the 50-MHz oscillator as the clock source to be used during the power up
initialization phase (Figure 3-14).
The selected 50-MHz source is now divided down as indicated in Figure 3-15 to provide 25-MHz, 12.5MHz, and 6.25-MHz free-running clocks.

(
EBOX/3-17

50 MHz
XTA l
CONTROllED

"normal"

\-----_._---1

EXT CLOCK

ClK 50 MHz FREE

"FOR
, - - - - - - , SPEED
56 MHz
MARGINS"
XTAl
CONTROllED

SEll
SOURCE}
SELECTION
REGISTER
SEl2

I NITIAl STATE
UNDEFINED

10 ... 1683

Figure 3-14

Basic Source Selection

ClK 50 MHz FREE

---I
1 i-I---,

1---40n5

ClK 25MHz FREE

1..- - - - 80n5 _ _ _ _+l
..
14

-----I

ClK 12.5 MHz FREE

14
.1
.-

160n5 - - - - - -....

ClK 6.25 MHz FREE

10-1684

Figure 3-15

Free-Running Clocks

The 50·MHz FREE clock source is next passed to a rate-selectable mixer. However, because the Rate
register may initially be in an undefined state, the selected rate is apt not to be the 50 MHz source. This
presents no problem because the inputs to the mixer (50 MHz FREE, 25 MHz FREE, 12.5 MHz
FREE, or 6.25 MHz FREE) are all even multiples; the rate is not critical during the power up phase of
operation. The mixer is shown in Figure 3-16. Its output is labeled 2*Rate Selected, and this output is
twice the clock selected frequency.

50
25
12.5
6.25

MHz
MHz
MHz
MHz

FREE 0
FREE
FREE
FREE

ClK 2* RATE SELECTED

ClK
SELECTED

+2
'------JC

SELECT
RATE}
REGISTER
INITIAL
STATE
UNDEFINED

SEll
SEl2

REG SEl2

REG SEll

RATE SELECTED
50 MHz
25M Hz
12.5MHz
6.25MHz

FREE
FREE
FREE
FREE
10-1685

Figure 3-16

Basic Rate Selection

EBOXj3-18

(

3.2.3 EBus Reset
Referring to Figure 3-18, the CLK CROBAR signal enables the counter to subtract one on each 12.5
MHz clock pulse. Once again, the initial ttate of the counter is undefined. During the crobar period
(approximately 5 seconds), the counter is decremented toward zero. When zero is reached, a carry is
generated and if CROBAR is false at this time, the -1 function is disabled and the counter is loaded
with zeros. This removes~. In practice, the counter passes through zero many times until
finally CROBAR is removed by the Power Controller logic. Signal EBUS RESET is a 1280 ns square
wave.
3.2.3.1 Initialization Clock Pulse Generation - As shown in Figure 3-18, CROBAR is shifted four
places into the shift register, activating the CLK SS stage. This, with the Clock Selected flip-flop,
enables the gated clock. It is this signal (GATED CLK) that becomes the source of the clocks generated via the clock control and EBox Clock Control. When CROBAR is removed, 4 CLK selected
pulses later, CLK SS is also removed. The approximate sequence is indicated in Figure 3-17. Figure 319 shows the power up timing. Note that this shift register also serves to synchronize CROBAR.
3.2.4 EBox Clock Control
The EBox Clock' Control provides a source of clocks for the EBox boards together with an MBOX
Sync Point (EBOX SYNC), which is always asserted one MBOX Clock prior to the generation of the
EBox clock (Figure 3-20).
Depending upon the nature of the EBox cycle (a period extending from the rising edge of one EBox
clock to the rising edge of the next), the period between EBOX CLOCK pulses may be extended by
some multiple of 40 ns, i.e., 80, 120, 160, 200, etc.
Refer to Figure 3-22; this drawing illustrates the functional structure of the EBOX CLOCK Control. It
consists of an MBOX CLOCK counter/marker generator, a clock phase sync detector, an EBox sync
source, and an EBox clock source. The CRAM time field (TOO, TO 1) specifies the duration of the EBox
cycle (Figure 3-21).
The marker generator consists of a shift register that may be loaded with zeros when EBOX CLK EN
is true or have ones shifted in (beginning with the 40-ns stage) for each MBOX CLK generated, as long
as EBOX CLK is false. Table 3-6 describes the marker generator.

® 12.5MHz
®
,...-_---,CDCROWBAR
[ .. 5 SECONDS]

ClK SELECTED

.---"--......... @

CLOCK
CONTROL

MBOX
CLOCKS

ClK CROWBAR

CLOCK

i-=-----=-----.j D IAGNOSTI C
CONTROL

FREE

@MRRESET
ClK
ClK

ClKODD

ClK

Q A EBUS
'eY RESET

EBOX
CLOCKS

EBUS
10-1686

Figure 3-17 Clock Initialization

(

EBOX/3-19

COUNTER INPUTS
ARE ALWAYS

~
r-------------+_~--~--+__.CARRY

OUT
CLK
CROBAR

1=-1
0= LOAD
4 - BIT COUNTER

---'L-~

12.5 MHz FREE

CLK EBUS RESET

Qal-----------------------------------t

CLK

640ns

E
B
U
S

CLK
CROBAR
CLK
SELECTED

CLK GATED

EBUS CLK

C
CLK SELECTED
NOTE
If CROBAR is false
a CARRY OUT disables
the -1 functions and
loads O's into the counter.

CLK
CLK

CLK
ODD

'------------+----lD
EBOX
CLOCK
CONTROL

SBUS CLK

S
B
CLOCK
DIAGNOSTIC
CONTROL

RESET

10-1-11'87

Figure 3-18

EBus Reset and Clock Initialization

•

EBOXj3-20

CROWBAR /

CLK CROWBAR /

50 MHz FREE

25 M Hz FREE

12.5 MHz FREE

CLK EBUS RESET

"'mm"~
CLK SS

CLK RESET

MR RESET

~------------------------------------------R

~~----------------------------------------~n
10-1688

Figure 3-19

Power Up Timing

CLK MBOX CLK
NOTE
Actually. EBOX CLOCK is
clocked via CLK ODD which
occurs ",6 ns earl ier than
MBOX CLK

CLK EBOX SYNC

CLK EBOX CLK _ _ _ _ _ _-I
10-1690

Figure 3-20 Simplified Diagram, MBox Clock, Sync, EBox Clock

•

-1 40 I-

EBOX CLOCK

~:ABLE

-LFI~
10-1689

Figure 3-21

EBox Cycle

EBOXj3-21

Table 3-6 Marker Generator Function
TOO

TOt

Duration

MBOX

CLK

Marker Generator
40ns
l20ns
80ns

EBOX

CLK

SYNC

0
0
0
0
0
1
1
1
1
1
1
1
1
1

0
0
1
1
1
0
0
0
0
1
1
1
1
1

120

160

200

1
2
1
2
3
1
2
3
4
1
2
3
4
5
1

0
1
0
1
1
0
1
1
1
0
1
1
1
1
0

0
0
0
0
1
0
0
1
1
0
0
1
1
1
0

0
0
0
0
0
0
0
0
1
0
0
0
1
1
0

0
1
0
0
1
0
0
0
1
0
0
0
0
1
0

1
0
1
0
0
1
0
0
0
1
0
0
0
0
1

0
1
0
0
1
0
0
0
1
0
0
0
0
1
0

The clock phase sync detector compares the marker generator content with the CRAM time field
(loaded at EBOX CLOCK TIME) whenever EBOX CLOCK EN is false. If the marker count compares with the bit combination in the time field, SYNC EN is asserted and the next MBox clock sets
EBOX SYNC. EBOX SYNC then enables EBOX CLOCK EN and similarly disables the detector.
This completes 'One cycle.
Note that with MBOX WAIT true, -EBOX CLK EN is also true and EBOX CLK EN is false (Figure
3-22). This enables the MBox clock counter/marker generator to keep shifting 1s from the 40"ns stage
toward the 120-ns stage. Similarly, the detector is enabled and when the marker compares with the bit
combination in the time field of the CRAM word, SYNC EN will be asserted and remain so until the
MBox responds or aborts the cycle. Thus, one MBOX CLK after SYNC EN is asserted, EBOX SYNC
will set. In other words, EBOX SYNC is asserted one MBOX CLOCK prior to where EBOX CLOCK
would have been asserted.
•

With SYNC EN true when MBox response is received (Figure 3-22) EBOX CLOCK EN becomes true
allowing the marker to reset to 000, and SYNC EN is removed allowing EBOX SYNC to clear on the
next MBOX CLOCK. At the same time, EBOX CLK EN becomes true and EBOX SOURCE EN is
also true; thus, when EBOX SYNC is cleared, EBOX CLOCK sets (Figure 3-23).

3.2.5 Error Detection
Figure 3-24 illustrates the logic that stops all clocks in the event of any of the following:
1.
2.
3.

A DRAM parity error occurs.
A CRAM parity error occurs.
A fast memory parity error occurs.

EBOX/3-22

(
'

~- -

ClK CRM

+--r--i-

2 BIT TIME FIELD
I N CONTROL RAM
REGISTER

.l-.,.......L-.,......J.. _ ....

SYNC EN

~~2~
CLOCK
PHASE
SYNC
DETECTOR

40 ns

ClK MBOX
ClK

MBOX
CLOCK
COUNTER/
MARKER
GENERATOR

80ns
120ns

ClK
MBOX ClK

ClK EBOX SYNC

GENERATOR

-EBOX ClK EN

EBOX ClK EN

-MBOX WAIT
___---'~--- C l K RES P M BOX

ClK EBOX
SOURCE EN
NOTE

ClK ODD

EBOX ClK EN
IMPLIES SYNC EN-O

EBOX
CLOCK
GENERATOR

ClK EBOX
CLOCK

10-1691

Figure 3-22

EBox Clock Control Block Diagram

ot·----

EBOX ..
Ir-CYCLE

EBOX CYC lE

----1°1

MBOX ClK

r-1
r -Lr___
- - ~N!D
POST
L..J
_____

EBOX ClK..J

EBOX SYNC

MBOX
RESPONSE

•

MBOX WAIT

10-1692

Figure 3-23

Basic MBox Cycle Timing

EBOX/3-23

ClK ERR STOP EN

ClK ERROR

CLOCK
DIAG
CONTROL

ClK ODD
CLOCK
CONTROL

lOGIC
MBOX CLOCKS
ClK EBOX
SOURCE EN

ClK
ERROR HOLD

EBOX
CLOCK 14------1
CONTROL

DRAM PARITY ERROR

CRAM PARITY ERROR

FM PARITY ERROR

ClK ODD

EBOX ClK

ClK CRM

C l K ERROR HOLD

ClK ERROR
ClK ERROR STOP EN

#///

CRAM PAR 16

_ _ _ _ _...J

_____

-'~ITS

All CLOCKS"

--iI-I------~I\
10-1693

Figure 3-24 Clock Error Stop

•

The timing shown is for a CRAM parity error. The CRAM register is clocked by CLK CRM; sometime later, the parity network settles and asserts -CRAM PAR 16. This indicates thatthe CRAM word
has dropped or picked up bits and is not correct. The signal-CRAM PAR 16, together with an enable
previously set by a diagnostic cycle (CLK CRAM PAR CHECK), enables the generation of CLK
ERROR HOLD.
'
If it is desired to stop on parity errors, CLK ERROR STOP EN must have been set by the console. In

this case, on the next occurrence of CLK EBOX SOURCE EN, the CLK ODD gate will be latched
false, inhibiting all clocks and freezing the system.

EBOX/3-24

lA}~k!!i all'~d

the

MBOX CLOCKS,

IleCeli',sary ~o ammre that the pWpt~r timing rdaticJI1§hip exists
CLOCKS,
of thY.': CRAM time fiel(t

ns consists of
to dock a HH41 Shift

delays, gate and
\vhkh has a propagation

~'",.'·h,.''''''~''''
hun~

Th,e CH.ltput is CLOCK. ODD
of

~!2,65 ilii!L

NOTE
t'U'2!

dRlrlt~§ O~l~Y.

i!!!p[l!n:rxhllll!!lte

cu:.

,. ,

rr'""~·~.~~"-i

otJlJ,.~

~<
...........
wI

tv
'-0

E
I

-:?
MCl ClK

CON DATAO APR

USER
COMP

SCD ADR BREAK PREVENT
SCAD ClK

APR ClK

.-----L._...,
EBOX
MEMORY
CYCLE
CONTROL
lOGIC

NOTES:
I. Output compares if either of
the following is true:
(a) MCl USER II USER
COMP
(b) -MCl USER II -USER
COMP
.
Thus (a) can be used in U1ler
public or concealed mode and
(b) can be used in supervisor
or KERNEL MODE
2, A public program has fetched
an instruction from a non
public oddress

SCD
ADR
BRK
CYC~

E
R
F
A

C
E

MBOX

CONTROL

MCl ClK

MCl ___ .

MCl
REQ
EN

BOARD
CTl

-:?

CON COND INSTR ABORT
SCD PI a SAVE FLAGS
CTl DISP/MCOND

SCD lOAD F::::

I I

CON IRSTR ABORT - - - - - ' - - - - - j - - - [

SCD
ADR
BRK
INH
1

"VARIOUS REQUEST QUALIFIERS" INCLUDING EBOX REQUEST

MCl

-:?

10-1721

Figure 3-29

Address Break Facility

In addition, the reference may be further qualified to a user or executive reference. The address break
conditions are loaded into the EBox hardware by performing a DATAO APR instruction. The left half
of (E) specifies the following:
Bit
Bit
Bit
Bit

09:
10:
11:
12:

Address
Address
Address
Address

Break
Break
Break
Break

on
on
on
on

FETCH
DATA READ
DATA WRITE
USER REF

The right half of (E) specifies the break address in bits 13-35, where 13-17 represents the virtual
section number and 18-35 the virtual page number, line number.
The Address Break Inhibit logic, illustrated in Figure 3-29, may be set up to inhibit an address break
by performing any of the following instructions:
JRSTF - JRST2
JEN - JRST 12
JRST 10
MUUO

(

The PC word provided by these instructions must have bit 8 = 1 to set SCD ADR BRK INH. If a
JRSTF is given setting SCD ADR BRK INH, the NICOND Dispatch occurring during the JRSTF
transfers the set state of SCD ADR BRK INH into SCD ADR BRK CYC, while clearing ACD ADR
BRK INH. Therefore, for the duration of the next instruction, address breaks cannot occur. This is
useful, for example, when continuing from an address which subsequently caused an address break.
Consider the following example:

677/
700/
701/
702/
703/
704/

SET03,
ADDM3,3oo
AOS700
HRRZ4,7oo
CAIE4,lOoo
JRST700

;PUT -1 IN AC3
;ADD TO TABLE
;ADD 1 TO TABLE ADR
;PUT CURRENT TABLE
;ADRIN AC4
;WHEN IT IS 1000 ALL DONE

NOTE
This sample program illustrates the use of ADR
BRK INH and is not meant to be a well-structured
program.
The sample program adds -1 to a table beginning at location 3008 and ending at location 1000s. A bug
exists, however, in this program. Note that the AOS instruction in location 701 is incrementing the
table address in the right half of location 700. The problem occurs when the right half of the instruction in 700 becomes 700. At'this time, the instruction becomes ADDM 3,700 and this wipes out the
instruction in location 700. Several references to location 700 are in the program. First the monitor is
requested from a terminal to set ADR break on data write for address 700 to assure that the AOS
instruction is working correctly, i.e., attempting a write into 700. The monitor performs a DATAO
APR, which sets USER COMP, WRITE COMP, and loads the address break register with 700. At this
time, ADR BRK INH is clear and when the EBox performs the write request, the comparator will
satisfy the OR gate labeled CD because the following conditions are true:
1.

2.
3.

VMA 13-35 = ADR BRK register 13-35
MCL VMA WRITE = WRITE COMP
MCL VMA USER = USER COMP
EBOX/3-30

(

At this time, both SCD ADR BRK INH and SCD ADR BRK CYC are clear; therefore, the signals
MCL PAGE ADR COND and MCL PAGE ILL ENTRY are asserted together with all other necessary request qualifiers. The MBox detects this condition and places a page fail word in its EBus register
(indicating an address break page failure) and asserts PF HOLD to the EBox. The EBox senses this,
and enters the microcode page fault handler. Now the EBox flags must be gathered for storage in user
process table location 501. Because SCD ADR BRK INH is one of the processor flags, it must be
made available; however, at this time it is clear. Regardless of this, the process of obtaining this flag
will be discussed. Upon entry to the microcode, CON INSTR ABORT is generated to cause proper
termination of the faulting instruction. Referring to Figure 3-29, CON INSTR ABORT enables SCD
TRAP CIR, which breaks the recirculation paths for both SCD ADR BRK INH and SCD ADR BRK
CYCLE; it also transfers the state of SCD ADR BRK CYC into SCD ADR BRK INH. This makes
the flag available for storage in 501. The page fault handler reads the MBox EBus register and stores a
page fail word in user process table location 500, stores the flags PC word (PC is now 701) in 501 and
then fetches a new PC word from user process table location 502. The processor now enters Execute
mode and handles the page failure appropriately.
Eventually, after evaluating the page fault word in 500 and other data, the monitor informs the user at
his terminal that a write was attempted to location 700. If after giving the problem some thought, the
user requests a break on the same address for write but now suspects that somehow the instruction in
700 is being overwritten by itself, the break can be inhibited. Now the monitor wishes to continue the
program by performing the entire AOS instruction to ascertain that it works but also must avoid
thewrite page fault associated with this instruction.
The monitor can perform a JRSTF instruction that sets ADR BRK INH and restores the old PC of
701 for the AOS instruction via user process table location 501. Referring to Figure 3-29, during the
execution portion of JRSTF, SCD LOAD flag sets SCD ADR BRK INH. During the JRSTF instruction NICOND Dispatch occurs and transfers the set state of SCD ADR BRK INH into the BRK
CYCLE flip-flop while clearing SCD ADR BRK INH. The AOS instruction is successfully fetched
from 701 and the "AOS write reference" to 700 is prevented from causing MCL PAGE ADR COND
because this is blocked by SCD ADR BREAK COND (L). The next NICOND Dispatch clears SCD
ADR BRK CYCLE, enabling the ADR BREAK to occur if a write is performed to 700. Eventually,
through many tries, the overwrite of the instruction in 700 will be detected by this method. Note this is
only a simple example and is not necessarily a practical one.
3.3.2.1 Address Break INH and Saving Flags - The signal CON COND INSTR ABORT is generated
by the microcode whenever external conditions require the microcode to abort a partially completed
instruction. If this occurs during an address break cycle, this signal copies the state of SCD ADR BRK
CYC back into SCD ADR BRK INH, thus making it available to save as a bit in the flag's PC word.

•

3.3.2.2 Address Break INH and Loading Flags - SCD LOAD FLAGS can be generated in a number
of ways: JRSTF, JRSTIO, JEN, JRST, and MUUO can set SCD ADR BRK INH. The 10-11 interface
can place the flags PC word in AR and perform a console start. This causes the microcode to generate
SCD LOAD FLAGS. During a JFCL instruction, the flags are read and the specified flags cleared.
Then the microcode reloads'the flags using the signal SCD LOAD FLAGS.
3.3.3 Arithmetic Processor Status Register
This facility enables special internal conditions to signal the monitor on a priority interrupt channel
assigned to the processor. Condition I/O instructions are used to control the appropriate flags and to
inspect the conditions of interest.
The arithmetic processor status register consists of two 8-bit registers and associated control logic. One
register receives the error or status signals and the other register enables or inhibits the generation of
an interrupt when one or more of these error or status flags sets.

EBOX/3-31

Figure 3-30 provides the basic format for the CONO APR word, the basic organization of the error or
status flag and the interrupt enable or inhibit for the two registers. In addition, the bit assignments are
provided in two tables, as well as the source of the error or status signals available to set the appropriate flags in the APR register.

APR APR INT
-APR RESET------,
CON SEL DIS

APR CLK

APR EBUS WW
BASIC CONFIGURATION
8 FLIP FLOPS.
FOR LOADING INFORMATION
SEE TABLE A

CON SEL EN _ _ _ _---I
XX-----~

APR EBUS

-CON SEL SET------,
APR E BUS YY --~--,
-CON SGL CLR
-APR RESET

---'===j::;;::gE:!9'i

-APR E BUS ZZ - - - - - - - r l C ' : : J
ERROR SIGNAL ------~

BASIC CONFIGURATION
"--- 8 FLI P FLOPS.
FOR LOADING INFORMATION
SEE TABLE B

APR CLK

FOR SPECIFIC SIGNALS
SEE TABLE C

TABLE A

TABLE B

E BUS
CON E BUS INTERRUPT INTERRUPT
CON
BIT WW SEL Di'S SEL EN BIT XX EN SETS
EN SETS
YES
02
06 S BUS ERR
S BUS ERR
03
0..YES
""""" L""-.."-.." 06
02
YES
07 NXM ERR
YES
07
NXM ERR
03
02
YES
08 I/O PF ERR
YES
08
I/O PF ERR
03
02 "",- t'-.."'''''''
YES
09 MB PAR ERR
03
YES
09
MB PAR ERR
02
YES
10 C DIR P ERR
10
C DIR P ERR
03 t'-..""
YES
""
' " ~"'''..:.
02 l"-.."-.."-.." YES
11
S ADR P ERR
t'-.."''''''''''''''''
YES
11
03
S ADR P ERR
0..""'"
12 PWR FAIL
02
YES
0..
""
""
""
""
'"
12
PWR FAIL '03
YES
02
YES
13 t'-.."''''''''''''''''
SWEEP DONE
YES "-..
03
13
SWEEP DONE

CON E BUS
E BUS
CON
ERROR
ERROR
BIT YY SEL SET SEL CLR BIT ZZ FLAG CLRS FLAG SETS
04
YES
06 S BUS ERR
05
YES
06
S BUS ERR
NXM ERR
04
0..YES
""""'" 07 t'-..
""
""
""
""
""
"
07
05
YES
NXM ERR
04
YES '- 08 I/O PF ERR
YES
08
I/O PF ERR
05
09 t'-.."'''''''''''''''
YES
MB PAR ERR
04
1:'-...""",,
09
YES
MB PAR ERR
05
~"'''''<
04
YES
10 C DIR P ERR
YES
10
05 0..""
C ""
DIR
P""
ERR
""'"
0..
""""
'""
04
YES
11 S ADR P ERR 1'-.."-.."-.."-.."-.."-.."-..
,"-.."-.."-.."
S ADR P ERR
05
YES
11
YES
12 PWR FAIL
04 ~,,"
t'-..
, , 'FAIL
"""""
"-..
Oe,
YES
PWR
."-.."-.."-.." 12 ,"-.."-.."-..
YES
04
13 SWEEP DONE
13
SWEEP DONE
05
YES
t'-.."''''''
1:'-..."''''''''''''''''

['\,"'-"'-"'-"
,,,,-"'-"
['\,"'-"'-"

~"'"

'"'" ~""""
~"'"

'"'"'" ~'"'"
~"''''"
~"''''"
~'""''

l"'-"'-"'-"'-'""'-" ~"''''''''''"

,'"'"'"'"'""

~"'''''''''''''
~"''''''''''''''' ~

""""""""""'"
~'"'"'"'"'"

~"''''''''''''''''

~"''''''''''''
~"''''''''''"

,,,,-"'-"'-"'-"'-"'-'< ~"''''''''''''''''

~"''''"
~

~""""'"

,"'-"'-"'-"'-"'-'<" 10..""""""""""""

~'"'"'"'"'"" ~'"'"'"'""'-"
,,,,-,,,-,,,,,,-,,,-,,

~'"'"'"'""

~"'''''''

0-.,,'-

~"''''''''''''..:.

""""'"

~'"'"""""""'"

"'' ' '

~"''''''''''"

TABLE C
ERROR FLAG
S BUS ERR
NXM ERR
I/O PF ERR
MB PAR ERR
C DIR P ERR
$> BUS ADR P ERR
PWR FAIL
SWEEP DONE

•

ERROR SIGNAL
MBOX S BUS ERR
MBOX NXM ERR
APR SET I/O PF ERR
MBOX MB PAR ERR
CSH ADR PAR ERR
MBOX ADR PAR ERR
PWR WARN
APR SWEEP BUSY II -APR SWEEP BUSY EN

~I.-----------------CONO APR WORD FORMAT---------------~.I
10-1722

Figure 3-30 APR Register and Interrupt Enables
EBOXj3-32

(

The basic organization of the APR is illustrated in Figure 3-31. The register is broken down into four
sections based on the origin of the error. Jhe first five flags set as a result of an error condition
involving some memory activity. Three·oftlie flags: [SBus Error, Nonexistent Memory (NXM) Error,
and S ADR Parity Error] originate in the memory adapter (DMA). The remaining two originate in the
MBox. The flag IN-OUT PAGE FAIL (lOPF) sets because of an external stimulus, but the actual
setting takes place by the microprogram, in response to a page failure that occurred during a priority
interrupt. The power failure flag sets when the power controller detects a low voltage condition. The
sweep done flag signals the completion of a cache sweep operation. This operation is the result of
performing a sweep instruction.

* S BUS *
ERROR

NXM
ERROR

MB
PAR
ERROR

C DIR
PARITY
ERROR

* S ADR
PARITY
ERROR

EXTERNAL TO EBOX
ERROR CONDITIONS

SET INTERNALLY
BUT DUE TO AN
EXTERNAL
CONDITION

These errors originate
inthe DMAand are
passed to the M BO X
which then passes
them to the EBOX.

POWER
FAIL

SWEEP
DONE

FROM
POWER
CONTROLLER'

EXTERNAL
CONDITION
NON ERROR

--....

10-17?3

Figure 3-31

APR Register Breakdown

Once again referring to Figure 3-30, to enable interrupts for any or all of the eight conditions, a CONO
APR is performed with bit 20 equal to 1 and ones in bits 24 through 31 for the desired flags. Similarly,
to disable interrupts for any of the eight flags, which have previously been enabled, place bit 21 equal
to 1 and ones in bits 24 through 31 for the flags to be disabled. This means that once the processor has
been powered up, and providing a power failure condition has not occurred, that once an interrupt
enable has been set, it must be specifically cleared as indicated above.
Any of the eight flags can be selectively set or cleared by placing bit 23 or 22 on, respectively, together
with those bits in 24-31 to be changed.

•

3.3.3.1 SBus Errors - Two error lines are available frpm the DMA to the MBox. These are SBUS
AD R PAR ERR and SBUS ERR. If the DMA starts a memory cycle and also detects bad address
parity, it sends SBus Acknowledge (SBUS ACKN) to the MBox, acknowledging receipt of the address
and within 125 ns transmits SBUS ADDRESS PAR ERR. The MBox now latches the error address
register (ERA), which contains the address in question and additional bits which specify information
associated with "data parity error conditions." These two bits specify which of the four memory
buffers (MBs) the parity errQr is associated with. The address used to address memory specifies which
word is to be transmitted (for a write) or received (for a read) first. This information is contained in
bits 34 and 35 of the address. If, for example, the address in the ERA is 101 [bit 34(0) and bit 35(1)] and
the address in the PMA used to address memory is 100, the indication is that the word requested by the
EBox, for example, was not the word actually causing the data parity error. Thus, in this example, the
EBox requested the contents oflocation 100, received it, and how, while fetching a word from 101 (of a
quad word group), an error occurred associated with that word.

EBOXj3-33

In addition, a 3-bit code identifies the origin ofthe data in the memory buffer register and indicates the
type of reference, i.e., read, write, etc. As the MBox latches the ERA, it transmits MBOX RESPONSE
IN and MBOX S ADR PARITY ERROR to the EBox. MBOX S ADR PARITY ERROR occurs
concurrently, with an MBox clock and, therefore, on the next MBox clock (that will be also an EBox
clock) APR S ADR PARITY ERROR sets. Providing the SBUS ADR PARITY ERROR INTERRUPT enable is set, an interrupt will be requested on the APR channel. In addition, to prevent the
MBox error condition from being changed, the APR error flag which sets is sent over the E/M interface to recirculate the MBOX SBUS ADR PARITY ERR COND; also, APR ANY EBOXERR sets
and is passed to the MBox to hold the ERA. As a result of the interrupt, the monitor determines that
the APR was the source of the interrupt via a condition I/O instruction (CONSO, CONSZ, CONI,
APR), make a determination, and finally clear the error flag, releasing the MBox ERA and associated
error logic.
3.3.3.2 Nonexistent Memory - Each time the EBox makes a memory reference, the MBox interprets
the request qualifiers and performs all the steps necessary to satisfy the request. A core memory
reference must be issued by the MBox in order for NXM to occur. When the MBox issues a memory
request to read or write a word to core memory via the memory adapter (DMA), it starts a timeout (32
Jls) and waits for SBUS ACKN from the DMA indicating acceptance of the request and address. If 32
JlS elapse and SBUS ACKN is not forthcoming, the MBox sets MEM ERR (Figure 3-32) .. An additional 32 JlS elapses and if SBUS ACKN has not been received by the MBox, MBox NXM error is asserted
~tOgether with MBOX RESP IN.

(

Referring to Figure 3-33, MBOX NXM ERROR is loaded into the APR register with APR CLK. If
the NXM ERR interrupt enable is set, APR INTERRUPT is asserted to the PI Board. To preserve the
ERA and NXM ERROR in the MBox, the APR NXM flag is recirculated back to the MBox. In
addition, PAR ANY EBOX ERR sets, holding the ERA information in the ERA register.
3.3.3.3 Other External Errors - Referring to Figure 3-34, all five external error conditions set the
appropriate APR ERROR flag and request interrupts (if enabled) on the error channel assigned. Also,
all the indicated error flags recirculate to the MBox and all cause APR ANY EBOX ERROR to set,
preserving the contents of ERA. Of the five errors, one, MB PAR ERROR, is handled as if it were a
page fault. That is, it causes control to be passed to the microcode page fault handler, where it is
evaluated. The status word is obtained from the ERA in the MBox. The format for this word is
initially as indicated in Figure 3-35.
The page fault microcode places a code in bits 0-5 of 268 and places the virtual address for the reference in bits 13-35 where bits 13-17 are 0 for KI paging mode; this word is stored in user process table
location 500. The remainder of the operation is identical with that for a page failure and is covered in
Section 2.

•

3.3.3.4 Input/Output Page Failure Error - During a priority interrupt [PI CYCLE (1)], page failures
are not expected to occur for interrupt instruction fetches or PI dispatches. This is regarded as a fatal
error, and it causes an interrupt on the assigned APR error channel. The page fault handler sets 10PF
in the APR register and then dismisses the interrupt. The PC is placed in VMA and an instruction fetch
begins while waiting for the PI system to honor the interrupt for the APR.
3.3.3.5 Power Fail - The power controller asserts the signal POWER WARN whenever the power
supplies reach a marginal value. This results in the setting of the APR POWER FAIL flag and requests
an interrupt on the APR error channel.

EBOX/3-34

(

MBOX CLK

EBOX SYNC

EBOX CLK

------'

EBOX REQ _ _ _ _---1

~L-----------nll--------------MBOX GENERATES

CSHEBOXTO _ _ _ _ _ _ _----1

' - - - - ITS OWN DATA VAll 0
SEQ CLEARING 0 UT
MBOX REQ LOGIC

T:...:1~1T.:,:2::...1..I.:...T3:....1..1T.:...4-l.1_...:E:.....:..CO.:..R...:E:.....:..R..::..Dl~:: __R Q - = - - - - - - - - ' ! -

MBOX TI ME _ _ _ _ _ _ _ _ _ _LI
STATES

MEMSTART _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

NXMTIMEOUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-L_ _ _ _ _ _

t:~:-6-4~~-S-----~

MEMERR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~!~

TIMEOUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~_32~~_S_ _~:~
INDMA
.~

EBOX DETECTS AND
SETS APR NXM ERR
REQUESTING AN
INTERRUPT

MBOX NXMERR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _II~I---~---__

MBOX RESPIN _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _II~I--__- - -__- - - '

CLKRESPMBOX _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

APR NXM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

lll~--------------'r----

-_-I!I~----------~r---10-1724

•

Figure 3-32

NXM Timing Overview

EBOXj3-35

10-\713

Error

'-1
1

"TO MBOX'

MBOX S BUS
MBOX NXM
MBOX M B PAR
"FROM
MBOX"
CSH ADR PAR
MBOX ADR PAR

ERR
ERR
ERR
ERR
ERR

I
APR CLK

"TO MBOX"

--.J

~r-<

APR ANY EBOX ERR

THESE FLAGS CAN BE
SET OR CLEARED
BY CONO APR
AND READ BY
CONI APR

r- APR

I I

BUS' NXM'
ERR
ERR

MB ,CDIR, SADR ,

~~~

f~~

~~~

If_ENABLE SET= E BUS 04
- E BUS BITS 06,07, 09,10, 11
If-ENABLE CLR= E BUS 05
/,

I I

CLK

'---

S BUS ERR
ERR INT EN
NXM ERR
NXM ERR INT EN
APR APR INTERRUPT
MB PAR ERR
MB PAR ERR INT EN
S ADR PAR ERR
S ADR PAR ERR INT EN
10-1714

Figure 3-34 External Error Conditions (MBox, SBus)

DATA SOURCE CODE

WRITE REF

DATA SOURCE

EBOX VIRTUAL ADDRESS
WILL REPLACE THIS

MEMORY (READ, RPW )
CHANNEL STORE STATUS (WRITE)
CHANNEL DATA (WRITE)
AR (EBOX WRITE)
CACHE (PAGE REFILL, CHANNEL READ)
CACHE WRITE

EBOX RELATED EVENT
10-1715

Figure 3-35 ERA Word

EBOXj3-37

3.3.3.6 SWEEP and SWEEP DONE - The MBox contains a section oflogic called the Cache Clearer
(CCA). This is addressed as if it were a device (014), using I/O instructions. Six operations may be
initiated. These are listed in Table 3.7. .
Table 3-7 CCA Summary
New Mnemonic

SWPIA
SWPVA
SWPUA
SWPIO
SWPVO
SWPUO

Old Mnemonic

DATAICCA
BLKOCCA
DATAOCCA
CONICCA
CONSZCCA
CONSOCCA

Function
Invalidate all cache data; do not update core.
Sweep cache, validate core, leave cache valid.
Unload all pages updating core; validate the cache.
Invalidate one page of the cache; do not validate core.
Sweep cache, validate one page of core, leave cache valid.
Unload one page, update core, invalidate the cache.

To request CCA cycles from the MBox as a function of one of the six instructions in Table 3·7, the
EBox places the virtual page number into VMA 27-35, verifies that the performance of the Sweep
instruction (which is privileged) is legal in the current mode of the processor and then either begins the
operation or, if illegal, performs an MUUO.
Figure 3·36 illustrates the various logic associated with the sweep operation. Three basic operations
can be specified in various combinations by the six types of Sweep instructions. These are illustrated in
Figure 3-36 in the table at the upper left.
In the cache, associated with each word of a four word block (quadword), are two bits labeled valid
and written. If the valid bit is off for any of the four words, these words are considered to contain
incorrect data and, if referenced (for example by the EBox), the words must be fetched from main
memory. Similarly, if the written bit is on for any of the valid words, these words contain different data
than the copy in main memory and the cache copy is correct. At some point, the written words must be
flushed from the cache into core memory. On power up, the cache must be invalidated, clearing all the
entries. For this case, the DATAl instruction is performed to device CCA. Because AC bit 10 is 0, the
MBox, upon receiving the EBox request and appropriate qualifiers (APR EBOX CCA and APR
EBOX LOAD register), will invalidate the entire cache. Similarly, because AC bit 11 is 0, the MBox
disregards the written words and no writebacks are performed to core memory. Finally, AC bit 12 is 1,
which specifies invalidation.

•

Referring to Figure 3-36, IRAC contains the AC field 9-12 of the instruction. The microcode executor
sets up the request utilizing the MEM field function MEM/REG FUNC together with the magic
number field coded as LOAD CCA (60ls). To follow the memory request, it is best to refer to Figure 298 which can be found in Subsection 2.7.2.5. Note that on Figure 3-36 MEM/REG FUNC (07) has bit
01 equal to 1 and this generates MCL REQ EN. This signal is used to enable the various registers
involved in the EBox request tQ load with the appropriate information prior to latching the VMA. The
following conditions set up for the CCA request.
Controlling Signal(s)

Signal Generated

MEM/REG FUNC
MCL REQ EN/\ MEM/REG FUNC /\ CRAM#OO
MCL REQ EN/\ MCL REG FUNC /\CRAM#<)I

MCLREQEN
MCLREGFUNC
APR EBOX LOAD
REG
APREBOXCCA
MCL MBOX CYCLE
REQ

APR REG FUNC EN /\ CRAM#<)6-08 = 1
MCL REG FUNC/\CLK EBOX SYNC

EBOX/3-38

(~.

(

c
.,..---EBOX OR CHANNEL
CAN STEAL A
IDLE
CACHE CYCLE HERE

CLK MBOX CLK

MEM REG FUNC

--.l

MCL REO EN

ClK EBOX REO
VMA

MBOX

BOARD

i~'-----

APR EBOX LOAD REG

CLK EBOX REO

:\\'--___
APR SWEEP BUSY

MCL MEM CYCLE

MBOX CCA

MCL MBOX WAIT

REO

MBOX ClK

-.J

II--"---,

! •

MBOX CCA REO

MBOX RESP IN

CLK RESP MBOX

APR SWEEP BUSY

NOTE:
MAGIC'" for LOAD CCA· 601.

I
I

___________~r-l~-----

APR EBOX CCA
APR EBOX lOAD REG
MBOX CCA REO

______________~r_l~_____

APR SWEEP BUSY

~:~~O~~~H~p~~~F~~~R
OPERATIONS
TERMINATES
CCA
OPERATIONS

JUI.,~

APR SWEEP DONE

APR APR TNT

ClOCKi
CONTROL

ClK MCl
ClK PI

I II I I

PAGE #<

ClK EBOX
REO

ClK RESP
EBOX

I
I
I

AC \I

AC 12

ONE
PAGE

WRITE
BACK

INVALIDATE

YES

OATA I

BlK 0

Y ES

DAtA 0

YES

CON I

YES

CONS Z

YES

Y ES

CONS 0

YES

Y ES

YES

, I

MBOX ClK

J L ________

I
I
I

AC 10

--.-.-

~~~D-------------,

I'"

I
I

~'--r-

_ _ _ _ _ _ _ _ _ _ _--11-

----------~~

"APR INTERRUPT
ENABLE REGISTER"

L-"_A_P_R_R_E_G_IS_T_E_R_"_-,-I_~_~,...~_~P~

:ECODER

I
I

---

4I ':
I
I

I SWEEP
I PNOTNE~

APR CLK-

I
I -

APRClKLF~

________~r_l~_______

ClK APR

::J

ClK IR

I NSTR

CSH EBOX TO

---.Jr--il
_____

ClK VMA

MBOX RESP IN

SWEEP TERMINATION

----~~~I~I---

L ___________

_____-JI!:

~LK

UMA

-----

MCL REG FUNC

APR EBOX CeA

VMA

_______--JI!

IRAC

1":":'-----------1
I
26 27
I
I
I I
I I
27- 35 I

----00

APR REG FUNC EN

I
I
I

I
I

MCL MBOX CYCLE REO

BASIC
CCA
REOUEST
TIMING

I
I
I

FUN CTION

SELECTION

CLOCK BOARD

BOARD

'-------_..1

CLK EBOX CLK

_ _ EBOX MAY EXECUTE
MBOX READS AND
WRITES WHILE THE
CACHE CLEARER IS
WORKING ON THE
CURRENT CACHE
SWEEP

,
1"'----------:-'""1
I
i I

CLK EBOX SYNC

CRAM REGISTER _ _--J

.... -------,I
I

-+~
-L-

REG

---

_~RAM#
06-08

I
I
I

!Pi BOARD -

)-..,------+-+-----+--1'I

BOARD

MCl REG FUNC

I:Iii I: I

----CRAM #0'

INTERUPT

~~O~6~~DTO

II
J

r- r-. - - - - - - - - - - - - - -,

~M~l~B~:O

Ii j

~~~

r--

'-----+-------l

REG
EN

MCl REO EN

L ___ _

I rMC'L I I
I I

-APR ClK

1
- - - '

REG

SWEEP
BUSY

APR ClK--.J

L _________ ~ ______

CRAM #00
MEM/REG FUNC

~~lK

ENt---

I\!EM 00

-APR ClK

Ii I

MEM 01

I' II
,

I, I

..JlI:

Figure 3-36 Sweep Logic
EBOXj3-39

The basic timing for the CCA request as well as CCA termination is illustrated in Figure 3-36. The
VMA must contain the virtual page number in VMA 27-35 for CONI, CONSZ, or CaNSO CCA
operations. In the current example (DATAl CCA), the MBox cache clearer does not use this information because the entire cache is to be invalidated. However, the cache clearer has an associated register
that is loaded by the MBox with VMA 27-35. IRAC bits 10-12 are similarly loaded into the MBox
control logic that directs the type of operation carried out. Each time a CCA cycle is completed in the
MBox, an idle period occurs where the channels or EBox can obtain an MBox cycle. The EBox can
continue to execute instructions but must guard against defeating the purpose of the Sweep operation,
i.e., write new data into already swept words in the cache. Summarizing, three of the six instructions
operate on one page of the cache (512 words). For these three instructions a different set of sweep
functions is available; these are: invalidate, writeback all written words in the specified page, or perform both. Similarly, three instructions operate on the entire cache (2048 10 words) but the operations
are the same as with the other three. In all cases, the EBox performs an EBox Request providing the
appropriate qualifiers and the VMA contains (in bits 27-35) the page number. The MBox loads its
CCA register and then asserts MBox CCA Request together with MBOX RESPONSE IN. Now the
EBox is free to perform operations while waiting for SWEEP DONE to generate an APR interrupt. If
a second sweep instruction is started by the EBox before the first is completed, the MBox begins the
second sweep just as it would another instruction; however, it reloads the CCA register with the new
information supplied by the second sweep instruction and does not complete the first.

(
.

3.3.4 Processor Identification
The processor identification consists of four parts:
Microcode options
Microcode version number
Hardware options
Processor serial number
This information is obtained by performing what was traditionally a BLKI APR, now called APRID.
The format is illustrated in Figure 3-37.
o
LEFT
HALF

8 9

MICRO CODE OPTIONS

MICRO CODE VERSION NUMBER

23 24

HARDWARE OPTIONS

PROCESSOR

SER~L

NUMBER

10-1717

Figure 3-37

APRID Format

This is not strictly a visible hardware function, but rather a combination of microcode and hardware.
The microcode for a given version is coded in such a fashion that the version number is obtained
utilizing the magic number field and the function AROO-O&'- number. The microcode obtains the
processor serial number that is hardwired to the 0 input of the ADXB mixer and places it in AR. Next,
the microcode version number is obtained and adjusted as follows. The serial number in AR is copied
to BR and the version number is loaded into AROO-08; next, the ARX. At this time the BR, AR, and
ARX are as indicated in Figure 3-38.

EBOXj3-40

(

8 9

r~~~~'~-~~-"'---~-'~-~'~~'-'~'~I'~'~'--~-~~r---

SERf~~L +~(.

.i'ie

~'---i
J

.~I~

~--..~.~~-~~.~.-..- ...~-~~~.~-.~"'~~~~'--'~~-~1l--"'-----""~""~~~

()

8 9
35
I'-'-~'-~--""'~'''''-~~'- ~--~--"'~""~-'--"~-~'--~"'~--l f-"--"~~~-~~I

L~ __~~_._._..~~.

. ~. _~. ~.=:'~~. ._~,,_. _.~~!Iil,R:'
!O-H18

AHgnrriJ:mt Step 1

are
IlUruber hi pkal:>led
stored in location

17, the

and

27 28

resulting

i;"7""~~'·~"?7""'-'~r'"'7"""""~.,-:Fr7-rr.",..r···~··-·~~n!iir-"·-·~-"·i--~~~·'~~~'~-'-~-'--~~~--'i

· ...
Cj',
, I'
H L
S

~.,.,,:;
u.

VER
¥:. \ ""
,;

!:..::..~~,-,,-t-{..~.~L""~~~-';''";,,(--'''''' _ _~.~~!~~_~

_ _.~_~_~._~~_~~~.. (LOADED
SH

Figure 3·39

C~dlle

P.tefm

The cache ren11 RAlvll in
This RAM is:
for :new ones.
aJgorithm was
into
cache.
the form.at

AHgnment

0r-____________~
M130X
14--------1 ADDRESS

I + - - - - - - - - V M A 27-33

LOGIC

127 t======~==~~r-----~W~R~IT~E------1

o
OR D E R

-----!--L-_---JI'----'-__---!
\--LRU--l

VMA 18-20
REFILL RAM
WRITE

IREFI~L
18

RAM: DATA

33 34 35
ADDRESS

~I.--------------------- BLKO

APR WORD FORMAT

----------------------1-1

Figure 3-40 Refill RAM Overview

When the instruction. is legal, the microcode performs a MEMjREG FUNC with the magic number
field coded as WR REFILL RAM. The APR logic decodes the REG FUN during the EBox Request:
APR EBOX READ REG
APR EN REFILL RAM WR
The MBox writes the three high-order bits (18-20 of VMA) into the refill RAM at the location
addressed by bits 27-33 of VMA. Writing the entire algorithm requires a loop using the basic instruction BLKO APR as a focal point. The following is an example:
SETZBZ,AC

;CLEAR REGISTERS

MOYE AC,TABLE(Z)
BLKO APR,O(AC)
CAIN Z,127
JSRDONE
AOSZ
JRSTRAMI
THE TABLE

;PICK UP A WORD
;WRITE THE FILL RAM
;DONE ALL 12810 WORDS?
;YES'
;NO, UPDATEZFORNEXT
;PICK UP NEXT WORD FROM

RAMI:

In the sample program, table through table+ 127 contain the appropriate entries to be written into the
MBox Refill RAM. These words are in the format indicated on Figure 3-40. The refill algorithm may
be adjusted by changing the sequence of the bit patterns. By doing this, portions of the cache may be
bypassed as appropriate. Normally, all four cache quarters would be used equally. Table 3-8 is reproduced as extracted from the MBox theory section simply as an example.

EBOXj3-42

Table 3-8 Sample Algorithm
'!'

Refill RAM Contents

Refill RAM Locations

0-7
8-15
16-23
24-31
32-39
40-47
48-55
56-63
64-71
72-79
80-87
88-95
96-103
104-111
112-119
120-127

0
3
7
6
0
0
0
4
3
0
0
4
0
0
4
0

1
1
1
5
3
1

7
6
7
1
5
1
5
5

2
2
2
6
2
2
7
6
3
7
2
5
2
6
6
2

3
3
7
7
3
3
7
6
3
7
3
7
2
6
5
3

4
2
1
5
0
4
0
4
1
0
4
4
0
0
4
4

5
1
1
5
2
5
0
4
1

0
5
5
5
5
5

6
2
2
6
2
6
0
6
1
0
6
4
2
6
6
6

7
3
7
7
3
7
7
4
3
7
7
7
1
0
4
7

3.3.6 MBox Error Address Register
The MBox contains a number of registers that can be loaded and read by the EBox. These.registers are
address registers for storing the address in the event of an error and for modifying the physical memory
address in response to certain request qualifiers. The registers are:
a.
b.
c.
d.

User Base Register - UBR
Executive Base Register - EBR
Cache Clearer Address - CCA
Error Address - ERA

The ERA register can only be read by the EBox. In addition, the EBox can also read the contents of
the page table to transform (map) the virtual address to the physical address and load the cache refill
RAM with the cache refill algorithm.

•

A status word i~ formed and stored by the MBox in the event that an error is discovered. The error
address is basically a status word that is formed and stored by the MBox when an error is sensed. In
the case of a parity, time-out, or an NXM error, the corresponding error flags are set and the error
address and associated status bits are loaded into the ERA register. The format of this word was
shown in Figure 3-35. This register is read by the EBox when an RDERA (BLKI, PI) instruction is
executed.

EBOXj3-43

Cond

fIelds

microinstruction

Mixers

Forcing a special CR address

fault

output gates.

is
on the
logic is described

3.41.1
The

Stadt
stacie, consists
eleven docked shift registers
SPEC/CALL
CTL DISP /RET,
a secp.H:;I}Ce
two subroutine cans followed
two sUbroutine return,§',
on
fIgure is not a practical
of
and retiIrn:7"tmt an
stack behaves in respons i:;: to the
and return controR
In practice,
microinstructions. For conveni,ence, these additional instructions
the first
asserts the
is the address
the CR address is "A",
significant events occur.

P!lli§MO'WIl

The CR
2,

docked in.to

current address

The second
this micwinstnlctioDl begins and,
LOC on the next
CLOCK.

(eRe
the CRAM
stack to push

SBRET 0-10
.--.L.-----..L...,
OUT
IN

•

PUSHDOWN
STACK 4 X II BITS

CRADR 8-10
MI XER f - - - - - - - ,

MIXER

0-10

DISP 30-378

CRA ClK

eLK

CRA lOC

SKIP 40-47

CRADR 10

CON COND ADR 10 7 ) - - - - - - - l

CRADR 0-10
~-----~3

~----~2

MIXER

CRADR
7-10
CRADR 0-6

r------,
: DRAM A 00-02

-7:

I
I

I
I
I
I

I
I
-71

DRAM J 00 - 10

SKIP
50-57

l ______

A READ
lOGIC
JI-4,J7-1O

A READ 1-4,7-10

1--~--+--+---t2

I - - - - - -......---.l 0
04

MIXER

I-

NOTE:
CRADR 0-10 is the logical "OR" of
JUMP 0-10 wilh all the indicated
signals _

CRM DIA
FUNC 051

PORTION OF CRAM_I
REGISTER ON CRM~

TO CONTROL RAM AND TO
- _ .£9NTROl RAM ADDRESS RAM

---

CRA ClK
CONTROL
RAM
DISPATCH
RAM

_ __ ~ MR RESET CLEARS
CRM ClK

USED DURING MULTIPLY INSTR
MAY BE MODIFIED

DISPENO-3
DISP EN 0-7

'------:..:...:....-....,1

MUl DONE
CRA D R 0 - 6

EBUS

__ _

FORCE 1777

CRADR 10

J 1- 4,7- 10

8-IO,FORCE 1777
SKIP 40-47,SKIP 50-57,
CON COND ADR 10
ASSERTED BY ClK BOARD
DURING PAGE FAilURE

CRM DIA
FUNC 052

0-7 , FORCE 1777

CRADR 8-10

I
I R

CRADR 7-10

DISP 0-78

CRA ClK

MR RESET C EARS

Ot-05

E
B
U

___- - - . . I . . -_ _ _.,_~MR RESET CLEARS

JUMP
(11)

CRM ClK

I...-PORTION OF CRAM---1
1- REGISTER ON CRM
-I

CRM DIA FUNC 054
10-1961

Figure 3-41

CR Addressing Overview
EBOXj3-45

CRI\ LOC

r--~-;~~-I-~~';;-~-~~~~-~'-I~-~8+1

1--~

L__~.~_._._. . ~.~~_~I_._.~.,_~..___._~l_,,_~._!

SBRET(QO)

_ _ _ ~, _ _ _ _ _ _

r-~

_ _ _.~~~--.c_'~'_~ "___ _ _ _ _ _ _ _ _ _

10-1957

Figur.e

Example

r~.lOT:£

.e)\Uillmlin,2;~

A $md Ei an:

IlB§tml 1r:!:i ~fIi

i'!VI,m

nmlf~bef:~,
,'L"..I"l".'ltj'YI!ll

R{~g:i§te:r (CRP!
1it ,docked. D-typl;;:

tVi/O

provide; the cwrrent addrei:l's
2.

the current

for diagnostic

The
the
patch
of 5 bits, is contained on.
board is used to address

duringJY1.!LRESJ;I,
the D.!agnostic: register
for loading or reading.
3.4.4 l\1Ustl:eHalrlIB,rms CR
Refer to
3-43.

there are four sections

eft
CR

eft Address

This grouping correspDnds to the '.vay

The

of course,) i'3'ees only an address

:rnay
o~

EBOXj3- 4 7

C~'}

•.
ClK FORCE 1777

CRAM JOO
CRADR

CRAM J01
CRADR 01

CRAM J02
CRADR 02

CRAM

CRADR 03
I

CRAM ~04

I
CRA1

CRADR 04

(

CRAM J05
CRADR 05

TO CRAM
INPUTS

CRAM J06
CRADR 06

CRA2

CRAM J07
CRADR 07

CRAM J08
CRADR 08

CRAM J09
CRADR 09
CRA2

CRA MUl DONE

CRAM JlO

CRADR 10

CON COND ADR 10

CRA2

CRA2
10-1958

Figure 3-43

CRADR Gates

EBOXj3-48

The fact that the CR address gates are OR gates should be kept in mind when trying to determine an
CR output address from a particular input condition or set of conditions. To enable a particular CR
address line only requires one of its input lines to be true. For example, consider the example presented
in Figure 3-44, which shows the mixers' that are used to select conditions to modify CR address bits
08-10. In the example, the dispatch function is effective address modification (EA MOD), which is
encoded in the dispatch field as 368 • Note that in the example the J field (CRAM J 08-10) is 4 in bits
08-10. The four possible combinations of ARX 13 and SH indexed allow any of the following:
1.
2.
3.
4.

No modification to CR ADR 09 and 10
Modification to only CRADR 10
Modification to only CRADR 09
Modification to both CRADR 09 and 10.

Because CRAM J 08 is a 1, the respective output gate, CRADR 08, will be a 1 even though the open
pin on that mixer (input 6) is effectively a O.

CRAM J08
CRADR 08

ARX 13

CRAM J09
CRADR 09

CRAM J10

SH INDEXED

DISP 02-04

~
V-

-------~----~----~

CRADR 10

DISPATCH FUNCTION
IS EA MOD ( 36 8)

01 SP EN 30-31 - - - - - ' - - - - - ' - - - - - '

CONTROL

•

D~SPEN

DISP

30-31

02-04

YES

INPUTS

CRADR

08-10
4

SH INDEXED

YES

OUTPUT
CRAM J

ARX 13

10-1959

Figure 3-44

Example CRADR 08-10

EBOX/3-49

3.4.5 Special CR Address Modification Considerations
Three special CR address modification comiderations are:
1.
2.
3.

CLK FORCE 1777
CRA MUL DONE
CON COND ADR 10.

3.4.5.1 CLK FORCE 1777 - This signal originates on the clock board and is used to force the output
gates CR address 01-10 to the address 17778 • This event occurs during a page fault. The page failure
microcode handler begins at CRAM location 1777. Thus, the EBox, as controlled by the clock, enters
a prearranged page fail sequence. Loading the first microinstruction from the page fault handler, CLK
FORCE 1777 forces the CRAM address lines, as indicated, and then issues a single CRM CLK, which
loads the microinstruction into the CRAM register. At this point, EBox's normal operation continues.
Note that CLK FORCE 1777 does not affect CR ADR 00, and thus may force the microcode to either
1777 or 3777. The first step of the page fault handler is duplicated in these two locations.
Note, also, that at the same time as the CLK board is forcing CLK FORCE 1777, the CTL board is
forcing CTL SPEC CALL in order to place the return ~ddress on the pushdown stack.
3.4.5.2 CON COND ADR 10 - This external signal is formed on the CON board and routed to CRA
2 as CON COND ADR 10. Refer to Figure 3-45, which shows the boards involved in decoding the
Cond and Dispatch fields. Note that each board contains tables indicating those functions that are
decoded on that board. The signal CON COND ADR 10 is formed when Skip 60-67 or Skip 70-77 are
decoded. The various hardware conditions involved are indicated on the tables.
3.4.5.3 MUL DONE - During the Dispatch function, MUL, the state of the sign of FE, as well as
MQ34 and MQ35, are used to modify the CRAM address in the multiply loop. When the sign of FE
becomes false an exit is made from the multiply loop. This is done via CR ADR 08. Simultaneously,
MUL DONE (Figure 3-46) is generated to force address bits 09 and 10. This is done merely to save
microcode words. Without this logic, MUL DISP would be an 8-way branch; with this logic, it is a 5way branch.
3.4.6 AREAD Logic
Refer to Figure 3-47. The AREAD logic is shown on the lower right-hand side. It consists of a mixer
and various gating elements. Basically, this logic is controlled by bits of the DRAM A field. Specifically, when the DRAM A field bits 00 and 01 are Os; then the AREAD logic AREAD 01-04 and AREAD
~7-110 bhecomAeReEquAivDaloenl t o(4b it fOdrob7it)10to DRAM 4JoOI-04Aandi? DRA
J07- 1O· ~he4n2DhRAMhA4070.or 0h 1
IS a ,t en
- an
- generate 8 + ~ spatch mg to 1ocatIon
t roug
mt e
microcode.

!'1

•

The outputs of the AREAD logic (to be able to modify the CR address lines) must be selected in the
appropriate mixers. Once again referring to Figure 3-47, the mixers involved are those controlling
CRADR bits 00-06 and 07-10. These mixers will select the AREAD function when the dispatch field
is coded as "2."
,

EBOX/3-50

c-_

("
,

COND

NON SKIP SPECIAL FUNCTIONS
LABEL

TO OTHER
BOARDS

OCTAL

DECODED

NOP

LD AR

DISPATCHES

LD AR

•

CTL2

'8-35

SKIP (CON COND ADR 10)
MICRO PROGRAM SKIPS
LABEL

OCTAL

DECODED

FETCH

KERNEL

USER

PUB LI C

D1SP (CRA 7-10)

OCTAL

LABEL

DECODED

9-17

0-8
LDAR

APW

DRAMJ

DRAM

DECODED

CRAl

A AD

ARX CLR

RETURN

SI(IP (CON COND ADR 10)

ARL IND

PG FAIL

M ICRO PROGRAM SKIPS

REG CTL

NICOND

SH 0-3

OCTA L

DECODED

AR CLR

LABEL

DECODED

DIAG

CRADR 7-10

71
DECODED

CON2

DECOD ED

CON2

AEF

TO OTHER
BOARDS

PI CYCLE

- EBUS

r--

GRANT

"'I

- EBUS

DISP (CRA 8-JO)

XFER
DISPATCHE S

LABEL

CTL 2

COND

NON SK IP SPEC IAL FUNCTIONS

NON SKIP SPECIAL FUNCTIONS

CRA 1

/
OCTAL

LABEL

DECODED

LABEL

OCTAL

OECODED

/
FM

DIAG

WRITE

FUNC

PCF - =:

EBOX

STATE
FE SHRT

DECODED
ON

AD FLAGS

LOAD

EBUS

CONl

eTL

DECODED ON

CON'

MBOX

(
'-

eT l
SPARE

IA
SPARE

SPEC

,,
,

CONDS FROM
OTHER BOARDS

CRA 2

COND 0 - 7

,,
,
,,
,,
CON 2
'-

DISP 0-7

CON COND

-V

INSTR

TO OTHER
BOARDS

SEL VMA

SPARE

DECODED

SPARE

EVEN

BAO

DECODED

ARXO

44
45

AC.:; 0
seo

VMA
VMA-

=
=•

SKI P
60 -67

SKI P
70-77

TRAP
VMA-

MODE

DECODED
ON

VMA- '" +
AR 32-35

VMA-

:::+

CON'

f--I

PI·2
VMA DEC

VMA INC

LDVMA

CON 1
COND
20-27

NORM

EAMOD

EATYPE

ON
CRA2

CRADR 0-6

LABEL

OCTAL

DECODED

SC-LT -36

SCADO

SCAD = 0

ADXO

CRA2

AD CRY 0

ADO

AD::: 0

SPARE

DISP
30-37

SKIP
40-47

SKIP
50-57

DE~O:ED _
CRA2

CONDS FROM
OTHER BOARDS

I
I

__ J\

COND
10-17

BYTE

--,

JUMP

'--

HELD

DRAM B

t
DECODED

PrAR

AAO

DECODED

MICRO PROGRAM SKIPS

OCTAL

AR18

OCTAL

SKIP (CRA '0)

LABE L

NON SK IP SPECIAL FUNCTIONS

DIV
SIGNS

SK IP (CRA 10)

COND

LABEL

MICRO PROGRAM SKIPS

ADR 10

DECODED

OCTAL

MU l

COND
30-37

,--------I

...... OTHER FI ELDS
I
L _________

~14o-------------

1
COND

65 66 67

I1
U

DISP

CONTROL RAM REG I STE R

-----------,
OTHER FIELDS-':
_ _______ ___ J\

------------.!-I
10 - 1963

Figure 3-45

COND and Dispatch

Layout and Control

EBOX/3 -51

FE WENT TO Of- FE S I G N p -CRA DISP 02
1\
MUL DONE
-CRA DISP 03
DISP FUNC 30=MUL( -CRA DISP 04
DISP EN 30-37

10-1960

Figure 3-46

MOL Done

3.4.7 eRA Dispatch Parity
Control RAM dispatch parity is computed using a 10160 parity circuit. This circuit (except during
periods when MR RESET is true) samples CRA DISP bits 00-04 and computes CRA DISP parity.
Normally the combined CRAM parity is odd, when correct. The clock board monitors the state of
CRAM parity, which includes the parity for the dispatch field. If the CLK CRAM PARITY CHECK
flag is set on the clock board (via diagnostic function 044), then any CRAM parity error stops all
clocks. This will occur on the EBox clock following the CRAM parity error.
During the power up sequence MR RESET sets and remains set. This generates the signal DISP
RESET PARITY, which forces the state of the dispatch parity network to indicate odd parity,
although the parity of the dispatch field (which now contains all zeros) is even. This, together with the
remainder of the control RAM register which is clear, yields odd parity. The effect is to make the
parity of the CRAM register appear to be odd following MR RESET. This logic assures that the
clocks have no chance of stopping in the event that CLK CRAM PAR check is true when a CONO
instruction is issued after the EBox has been powered up and this instruction causes MR RESET or
similarly if a diagnostic MR RESET is issued.

(

c
(

EBOXj3-52

SPARE-~
41

- SH AR PAR ODD

BROO

ARXOO

EDP

ARI8
AROO

ADCRY-02 -

ADOO -

"32

DRAM BOI- 33

BRI2- 34

IR NORM 0 9 - 35

~CON

47
'i'24

FE S I G N t

SKIP
EN 40-47

IR NORM OS-10

BIT 09

DRAM B02 -

SCAD SIGN -

SH INDEXED -

MCL EA TYPE 0 9 - - V

......

SC·GE·36

0 - - 37

ADXOO

AD CRY- 02

ADO O

0 - 36

- SCAD'O

&EATYPE10

AD'O

..r:

BIT 10
CRA2

DRAM

,...-~ CON SKIP

57
,...I 2 4

DIAG ADR 07-10

SPARE-

10
3

2
CRA4

BIT OS

CRA2

",,1

CRA LOC
CRA3

'--

CLK FORCE 1777

BIT 10

......

"CO,"

NEXT
ADDRESS"

~>-

MUL DONE
---j

DRAM J07 -

SH 00-03

BITS 07-10

DRAM J08 _

DRAM AOO -

DIAG ADR 0-6

____ J

DIAGNOSTI C
ADDRESS
CRA3

DRAM J09 _

DRAM AOI -

DRAM JIO _

DRAM AO~

1"'--,

EBUS
01-05

PUSH

POP

HOLD

3
AREAD 07

ARE AD 10

DRAM AOI

V-

AREAD 01
ARE AD 05

AREAD 02
(SEE TABLE BELOW)

DIAGNOSTIC 1
ADDRESS 3
CRA3

JO~,g4~~,~

-- 1

CRM DIA
FUNC
051

EBUS
00-05

O'tl~g5~g

DRAM J02

BITS 00-06

AREAD 03

CRAI
CRM DIA
FUNC
051

DRAMA02_~
SEL

0
5

NOT
USED

FUNC

AREAD 09

~UM; -

'- ____

AREAD 08

\-r - -r"!

"'~EN

07-10

CTL
o ISP
RET

CR ADR 00-10

CRAI
CRA2

0_1
07-10 - - 2
07-10
3
CRA2
CLK PF DISP 07 -10
4
CON SR 00- 03
5
CON NICOND 07-09,
6
SCD N ICOND 10

CTL
SPEC
CALL

CTL

'---J

J07-10 _ _ I

A READ
SBRET

EN 50-57

CLK

'tj

CTL SPEC CAL L

CRA1CLK

CON~~/

CON
ADR 10

iJ."STACK"

IR NORM O S - 35

50......

SCAD SIGN

BIT 10

r----

MCL EA TYPE 10 -

AROO- 32
DRAM BOO- 33
SCD FPD- 34

"CURRENT
LOCATION"

IR NORM 1 0 - 35

ARX 1 3 - 36

M035-~

SC SIGN

Q
CON

CRA2

BR00-r 31
BIT 10

IR AC'O

M034 -

-- 2

DRAM J03

AREAD 04
DRAM J04

SBRET 00- 06
3/

l(
COND

~--

oo-~~~

OTHER
FIELDS

---'

COND

I --- --J~I~;I~~s;I~ls;I~ls; 1~ls;I--J I
00

------------ ---------

DISP EN
00-03

-OU
- 01
-02

(J)

'--

TABLE A
DRAMA
AREAD
00 01 01 02 03 04 05 06
0
0 JOI J02 J03 J04 0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0

::;)

1 1
DISP EN
00-07

DISP EN
30 -37

-00
- 01

00
01

DECODE
DISP 00 - 02

CRA CLK

CRA3

-......

CRA5

)

CONTROL
RAM
) DISPATCH
RAM
)
ON CRA
BOARDI280X5

(

(
J

DRAM AS

FUNCTION

0
1
2
3
4
5
6
7

IMM
IMM-PF
UNUSED
WR TST
READ
READ-PF
RD-WR
READ PSG WRITE

07 08 09 10
J07 JOB J09 JIO
o
0
1 A02
o
0 A02
o
A02

CONTROL RAM 1280 WORDS BY 75 BITS

}
I

CRM

)

10-1962

Figure 3-47

Control RAM Addressing
EBOXj3-53

APPENDIX A
UNDERSTANDING THE MICROCODE

The control portion of the EBox comprises the DRAM and the CRAM. The DRAM has storage for
512 decimal words, one for each KL instruction. During instruction execution, the DRAM word
provides information about the type of memory references by the executing instruction. It also provides an index into the main control programs contained in the CRAM.
-

The CRAM provides storage for 1280 microinstruction words that are structured into a complicated
control program called the "microcode." This section defines and explains the microcode. Although
many figures of sample listings from the microcode listing are used throughout the discussion, an
assumption is made that the reader has an up-to-date copy of the microcode listing (either hard copy
or microfiche). The examples shown here refer to specific sections of the listing; the reader may wish to
follow the examples through the actual listing while reading this section.
The discussion begins by introducing the microcode and describing field, value, label, and microinstruction definitions. This leads into defining macros, pseduo-operators, and location control. Then,
two instructions (MOVE and ADD) are illustrated, leading the reader through the microcode listing.
Figures A-17 through A-23 (located at the end of this appendix) complement the discussion and define
all the CRAM and DRAM fields. Refer to these figures whenever necessary.
The microcode is presented in groups, with each group (designated a through g) representing four octal
digits as they appear in the listing. Each group represents one or more fields. For example, the listing
for microcode address 0724 is shown in Figure A-l.

(
U0724

0004,

3242,

ADI~I~

4600,

0000,

0206,

1010,

0400

AR-FM

10-BIT
LOGIC

SH-MEM

CaNOl
SPEC

+- GROUP

+- FIELD

CRAM location into which this word is loaded
10-2621

Figure A-I

Sample Microcode Listing

EBOXjA-I

Each of the group's coding is defined in the respective figures listed below:
Group

Figure

a
b
c
d
e
f
g

A-I7
A-18
A-19
A-20
A-21
A-22
A-23-25

The DRAM contains storage for each instruction. During instruction execution, the DRAM word
(Figure A-4) provides information about the type of memory references required by the executing
instruction and also provides an index into the main control program located in the CRAM.
Conditional Assembly Variable Definitions
The Conditional Assembly variables observed in the microcode listing are listed and defined below.
(The definitions are presented for the variable set to 1. The values shown are the normal settings.)
Variable

Definition

TRACKS

OP.CNT

Enables code to build a histogram in core to count the usage of
each op code in both USER and EXEC mode. *

OP.TIME

Enables code to accumulate time spent by each op code. *

FPLONG

Enables KA style double precision floating-point instructions
(e.g., F ADL, FSBL). This feature is not supported in systems
running the TOPS-20 monitor.

MULTI

If operating a multiprocessor system, this suppresses cache on
unpaged references; paged references are left up to EXEC. *

MODEL.B
XADDR

KLPAGE

•

Enables storing the PC after every instruction and creates
DATAI/O PI, to read/setup the PC Buffer address.*

IMULI.OPT

Enables the KL-Paging mode, for systems running the TOPS-20
monitor.
Indicates extended addressing hardware, primarily a 2K
CRAM, rather than a 1280 word CRAM.*
Enables extended addressing microcode. (Cannot do extended
addressing without Model B; Cannot have extended addressing
without KL page).*

Enables optimization of IMULI to take only nine multiply
steps.

*This feature is not supported.

EBOX/A-2

(

Variable
SXCT

Definition

Enable&' special XCT instruction, which allows diagnostics to
generate large addresses. (Do not need SXCT with extended
addressing. Cannot do it in Model B hardware.)

EXTEND

Enables the extended instruction set.

DBL.lNT

Enables double integer instructions.

ADJBP
RPW

WRTST

Enables adjust byte pointer.

Enables Read-Pause-Write cycles for non-cached references by
some instructions.

Enables Write-Test cycles at AREAD time for instructions such
as MOVEM and SETZM.*

BACK.BLT

.SET jINSTR .ST A T

Enables BLT to decrement addresses on each step if E
(AC); breaks many programs. *

Enable instruction statistics code. *

Field Definitions
The actual (physical) CRAM bits are derived from the CRAM Board logic. However, no logical
relationship exists between the physical bits and the respective microword bit names. Figures A-2 and
A-3 are located at the end of the introductory discussion, just before the two examples. Figure A-2
shows how the physical CRAM bits are derived. Figure A-3 shows the physical bits and the corresponding microword bit position (and name). The microcode listing is ordered with respect to the
microword bit positions, not the actual CRAM order.

Microcode field definitions have the form SYMBOLj = J, K, L, MI The J parameter is only meaningful when "D" is specified as the default mechanism. The K parameter defines the field size in the
number of bits (in decimal). The L parameter defines the field position (in decimal) as the bit number
of the right-most bit of the field; bits are numbered from 0 on the left. Note that the position of bits in
the microcode word (Figure A-3) bears no relation to the ordering of bits in the hardware microword,
where fields are often broken up and scattered. The M parameter is optional; it selects a default
mechanism for the field. The legal values of this parameter are the characters D, T, P, or +, where:
D

Indicates that J is the default value of the field if no explicit value is specified.

Is used on the time field to specify that the value of the field depends on the time
parameters selected for other fields. Within the microcode, Tl parameters are used to
specify functions that depend on the adder setup time; T2 parameters are used for
functions that require additional time for correct selection of the next microinstruction
address.

Is used on the parity field to specify that the value of the field should default, such that
parity of the entire word is odd. If this option is selected on a field where the size (K) is
zero, the microassembler attempts to find a bit somewhere in the word for which no
value is either specified or defaulted.

*This feature is not supported.

EBOXjA-3

ROIA!

5
20=ADSEL W}
24 = l~D BODLE
28:=:: !-.. 08 ;:;i::::L. {21
32 Ave SEt
36 = l\R:~r-.l1 SEL

1 -, [}::;. SCA!);."!. :'J[S

.:/.:::-: FE tOi;,,!)
:3 --48 == JfJEUJ (,3)
12 = JPlr:LD

-" 16 = "VIQ SEL

S}~~f"T

'''' SCAD ~o.ll

21 =;1,D ScL (in

,',.IFI ELD Wi

2.5 = tl,Ot" filS

.j~H::l.D

{41

13 = .lfu ELD

131

1~' = r.~!(iPjGOND

.2::.:;
=--

S(~!\U

t?)

JFiElD

\~n

'~B

2f) "" CRAM #(0)

H~""JrlELD (5}

:j,u-;;; GRf;f,fl

:~7

18"" SKtPlCOI'JD (1)

34 = C fLt.J,,1
3:3 = e~ip-Jv"i

JF1~LD

~ 2C/~.tU (1,
f' = Jr-;;:;::~_J) ,;21
n ,- JrriClD {C;

33"" GR.'1.M t-;:-(3)
= CR,&,M -tt{G)

";;:i

1t~

:2:rn

"-'

,_in~u}<

~~GP/CO~~:D

.~\D ~jt::L

.= r4.D,L\ SF:. L

{'if);

:J;~~ =

c:;:;t~r;i~

;::('2i

CfL':.M -# iSl

12i

REG

'~'LH41

CRfv'j OUT H\l+OOIH

CR;\Jj (HJT (N+2G1H

(N+OO}H
CRM OUT (r-~+(r!/H

(r~+i}1IH

(N-:-21J}H

(N+21IH

GR!Vl OUT \f'J+J+t:,1IH
CRM OUT (i'.H52)H

O\!+60!H
(;R~V~

iN·;·03IH

CRM OUT !N+22iH

{i\1+4,OlH
CF;M OUT (r,~+40)H

!llh021H

CAM oU'r (N+O~·dH

OUT {H\i'H}OH--;

;:::HM OU"(
{r"':'';'4:~,:!~~

(f-,J+6ZiH

CRIVI SEL 2 H
CRM S~L 1 H

CR_M

cu~

CPer-../~

eLK E: H

cnfv~

r:u<

RO!iJ\1

'11

" -~ 40 SC/1.0A Sf:: l (;j
:2 -,
"" Vni}1A SEL
3 ----;.~.g
4 -,. 5L
5

j\'l~M

LOt,i)
56 = ftif\ /\,DR \cfi
~-= 8f~

60"" SC.:1,DB SEL

t:!'l

64 = _B..RM SEL {2}

45 = ARbl!" SEL {4l
49 MEfJ~ {1)
'58 "'" SKW!COh~D ::3)
57 FIV: .6.DR. {21

63 ,t\nxr",] SEL (Z)
72:::-: VivlA SEl {'I ~

1'6 = TOO

SGADA SEt (1)

42::-: SCI-\DE', :;EL (~l
--~5 = SH/f-~,RM~\·'l (2)50 = MElV~' i2i
540 Dr-"\X to,:'"D
58- fr\l; ,Lo,DR !:1)

!j.:J = rll'l{ooRK

,.-i2 = SCi\:1
\A5 Ai-W",! S0L ~"li
70;'" £~R: 0

Microcode Address 160, 161

D 0270,5500,0504

;4091 270: R-PF, AC,

Figure A-13

J/ADD

DRAM Word 270

;2711 BR/AR, FIN XFER, I FETCH ;GET OPERAND, PREFETCH,
;& START EXECUTE
U0045 ,0000,3240,0043,0000,0226,0001 ,0400 ;2712 TIME 3T, I/R DISP, J/O

Figure A-14

Microcode Address 45

U0504,0170,0600,2000,0000,002S,1333,0000 ;4098 ADD: AR AR*ACO, AD/A+B, AD FLAGS, EXIT

Figure A-15

Microcode Address 504

UOI75,0I40,4001,0000,0403,0002,1006,0000 ;2749 STAC: ACO_AR,NXT INSTR ;NORMAL AND IMMEDIATE MODES

Figure A-16

Microcode Address 175

UaU

·1

J FIELD
MICRO CODE BASE ADDRESS
MICRO WORD
POSITION

NOTES:

(

'-.

1. The J FI ELD defines the base address
to which this microinstruction jumps.
10-2637

Figure A-17

Microword "a" Field

EBOXjA-14

I" _ _ _

"b" _ _
1

AD
CONTROLS ALU FUNCTIONS

MICRO WORD
POSITION

ADA/ADXA
SELECTS AD "A"

00
03
06
11
17
40
43

A +XCRY
A * 2
A+B
A-B-l
A-l
A +1
A * 2+1

46
50
51
54
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37

A +B+1
ORCB + 1
A-B
XCRY-l
SETCA
ORC
ORCA
l's
ANDC
SETCB
EOV
ORCB
ANDCA
XOR

01
02
44

A +ANDCB
A +AND
OR + 1

Bit 18:
0 EN
1 O's

1
2

3
05
07
52
53

OR + ANDCB
A + OR
AND + ORCB
A + ORCB

15
16
17

ANDCB-l
AND-1
A-l

ADB/ADXB
SELECTS AD "B"

"I" 1~

I " I " 1" 1" I' " I"

---+t~

~"1 1
n

AR
ARX
MO
PC

2
3

FM •.1 (See Note)
BR"2
BR
AR-'4

NOTE:
Must have time
for parity check

B
OR
O's
ANDCB
AND
A
10-2638

Figure A-I8

IMICRO WORD
POSITION

~#cn

0 AR
0' AR if SPEC 22
1
2

•

Mieroword "b" Field

CACHE
AD
3 E-BUS
4 SH
5 AD*2
6 ADX
7 AD*.25

ARX

I
0
2
3
4
5
6
7

ARX
CACHE
AD
MO
SH
ADX*2
ADX
ADX*.25

BRX

FMADR

1
0
BR

0
BRX

0
MO

ARX

o
1
2
3
4
5

ACO (lR 9·12)
AC1 (ACO + 1)
XR (ARX 14-17)
,VMA (32·35)
AC2 (ACO + 2)
AC3 (ACO + 3)
CB
#B

If SPEC/MO
SHIFT:
0

MO*2
MO*.25

If COND/REG
CTL:
0

MOSEL
MOMSEL

10·2639

Figure A-I9

Mieroword "e" Field
EBOX/A-15

I + - - - - - - - - - - - - - - - ..d .. ----,------------~

SCAD

SCADB

SCADA

N.U.

1
o
1
2
3
4
5
6
7

A
A-B-1
A+B
A-1
A +1
A-B
OR
AND

1
2
3

FE
AR 0-5 (NOTE 1)
AREXP (NOTE 2)
# (NOTE 3)

1
2
3

SC
AR6-11
AR 0-8
#(no
sign extend)

1
0
SC

0
FE

SCAD

Bit 39

0'5
If
SPEC'13
0
FE
1
AR
SHIFT

NOTES;
1. Byte Pointer Position Field
2_ IAR (01-08)j XOR IAROOI
3_ Sign e>ctended with #00
10-2640

Figure A-20

I...· - - . - - - S H - ' - A - R M - M - - - - - - - - - -

MICRO WORD
POSITION

T' --T-IM-E--I----------·~I

o
1
2

SHIFT AR ARX
1 AR
2 ARX
3 AR SWAP

•

Microword "d" Field

2T
3T
4T
5T
5

6
ARMM

o
1
2

#0-8
EXP <-SIGN
SCAD EXP

SCAD POS

7
10
11
12
13
14
15
16
17

B WRITE

FETcH
'REG FUNC
AIND
BYTEIND
LOAD AR
LOADARX
AD FUNC
BYTE READ
WRITE
RPW

10-2641

Figure A-21

Microword "e" Field

EBOX/A-16

!<'---------..~.--.---~.- "'~"","---.--

II
CO!~D

SPEC

[,/HeRO WORD

POSlTlON

NON-SKIP IFUNCTHJNS

I\lOI'
LiD ,lU::;:

SKiP

SPARE
EVEi\~ Pr:\,P,

o-e

tD Ae! !J-'1i7

43
Ml), eLR

Ai'lL 11\10

REG CTL

DRAMJ

,t~2

""!'leu!
5

DiSP/:; TCHES

FU~.CTiONS

RETURN

il.RXO
lUllS
AJ'tIl
AC #0

fiG FAil

SR
7
30
31

SC I)

SC.t\D 0

lOP'~[) ~R

15
16

20
21
22

SPEC ~!,JST
SR -t- #
SEt VMA

E130XSTATE

EBIJS CTl
MBOXGTl

62
63
6465

SPARE

25
26

SP,l\RE

21
30
31

32
33
34
35
36.
37

53
54
55
56
57
60

SPARE
SPARE

VMA~#

10
71

VMA'~ # +TRAP
VMA ~ #+ MODE
VM.l\,- # +AR 32·35
VMA ~ #+1'1'2
VMA DEC
VMA If,le
LD VMA HELD

73
74
75
76
77

MUL
DiV
S~Gr',]s

SCAilD 7:: 0

,I\D FL4GS

SH 0-3

ADX III
AD CRY 0

AD *0

36
31

DR.4.M B
BYTE
r~ORM

lEA MODiE

USER
?U8LIC

RPW REF
PI

eye

EBUSGRAiIlT
EBUS TRANS
IN,RI'T

·START
RUN
10 lEGAL

iEI30XI'F
AC REF
~;V!ll'!l

REG

NOP

10
1'1
12
13
14
15
16
17
20
2'1
22
23
24
25
26

SP rtliEr..1 CYCLE

Dispatch
A READ 2-29,2-96,2-97
CRA Parity 3-52
DRAM J 1-11
IR 1-8
NICOND 1-3, 1-8, 1-11, 2-4, 3-9
State Diagram 2-7
Table 2-17
DRAM 1-3, 1-8,2-12, 2-101, 3-7, A-I
Addressing and Selection 3-8
Organization 1-4
Parity Error 2-8
Register Fields 1-3
Word Format A-21
DTE20 2-48, 2-50
E

•

EA Calculation A-9
EA MOD 1-8,2-14
EBox 1-2
Clock 2-11, 3-6, 3-19
Data Fetch 2-95
Data Paths 1-48
Data Store Cycle 2-103
Execution Cycle Overview 2-102
Frozen 2-8
Instruction Set 2-88
Main Loop 2-7
Module Utilization 3-2
Priorities 2-41
REQUEST IN 2-26
Reset 2-1
EBR 1-19, 2-67
EBus
Basic Operation 2-126
Control 1-39
ECL Acquisition 2-127
Interface Control 2-116
Interface Organization 2-123
. Requesting 2~ 124, 2-131
Reset 3-19
Signal Lines 2-120
Effective Address
Calculation 2-91, 2-93
Manager 2-14
EPT 1-22
ERA Word 3-37, 3-43
Error
CRAM Parity 2-8
Detection 3-22
DRAM Parity 2-8
External 3-34

I/O Page Fail 3-34
MBox 1-37
MBox Address Register
NXM Overview 3-36
SBus 3-33
Stop Enables 2-12
EXEC Virtual 2-134
Execution Cycle 2-101
Executor 2-18, 2-33

3-43

Fast Memory 1-11, 1-42
Address Field 1-13
Addressed by VMA 2-67
ADR Field 2-86
Information Flow 1-44
Parity Error 2-8
Request 2-94
Fetch Cycle 2-96
Field 1-8
ARMM 2-88
Microword A-14
MQ 2-88
SC 2-87
SCAD 2-86
SCADA 2-87
SCADB 2-87
SH 2-88
SPEC A-9
VMA 2-88
Flags 2-58, 2-65
Function
00 2-133
01 2-134
02 2-134
03 2-135
04 2-135
05 2-135
06 2-136
07 2-136
Functional Blocks 1-5
G

General Interrupt Sequencing 2-47

H
Halt
Handler 1-8, 2-20
Loop 2-4
Hardware
Cycle Summary 2-110
Page Table 1-36

EBox/INDEX-2

I, J, K
Indexing 2-92
Indirect Word Request 2-26
Indirection 2-92
Instruction Cycle 2-24
Instructions 1-5
Basic Four Mode Type 2-103
Complex 2-96
Immediate 2-96, 2-103
N on-PC Change 2-96
Non-Read PSE 2-99
Not Requiring (E) 2-96
PC Change 2-96
Read-PSE-Write 2-101
Requiring (E) 2-99
Instruction Set
Divisions 2-90
Overview 2-88
Interface Control 2-108, 2-116
Interlocks 2-124
Interrupts 1-5, 1-39, 2-44
Dialogue 2-48
General Sequencing 2-47
Handling 2-123
Instructions 2-47
Priority Chain 2-46
Sensing 2-127
Simultaneous 1-39
Testing For 2-92
Introduction 1-1
I/O
Basic Control 2-124
Handler 2-20
IR 1-8
AC Control 3-7
DRAM Control 3-4
Loading and Control 3-3, 3-6
Test Satisfied 3-10
L
Lines
CS 1-1, 2-120
DATA 2-120
EBus Signal 2-120
FUNCTION 2-120 '
PRIORITY TRANSFER 2-121
Loading Flags 2-58
Logic Descriptions 3-1

M
Mapping
Virtual Address 1-38
MBox 1-1
Clock 2-28
Control 1-18, 2-110
Cycle 2-8
Error Conditions 1-37
Request Cycle 1-42, 2-28, 2-70, 2-94
Response 2-29, 2-33, 2-42, 2-117
Response Received 2-116
Wait 2-11
Memory Cycle Control 2-116
Memory References 2-98, 2-100
Memory Request 1-18
MBox 2-70
Microcode 1-36, 2-14, A-I
Example A-9, A-12
Field Definitions A-2
PI and EBus Interface 2-127
PI Board Interface 2-128
Sample Listing A-I
Variable Definitions A-2
Microinstruction 1-45
Microprogram 1-10,2-7, A-I
Address Control 2-9
Deferred 2-12
Frozen 2-8
Halt Loop 2-4
Organization 2-14
States 2-1, 2-4
Wait 2-8
Microstack Operation 2-103
Mnemonics B-1
Mode
Control Logic 2-53
Initialization 2-56
Memory 2-107
SELF 2-107
Structure 2-51
Transfer 2-54
User Concealed 2-65
User Public 2-59, 2-60
MOVE Instruction Example A-9

Field 2-88
Selection 2-89
MUUO 2-50, 2-53, 3-41

EBox/INDEX-3

NICOND 1-3, 1-8, 1-11, 2-4, 2-12,
2-13, 3-9, A-9
Nonexistent Memory 3-34, 3-35

o
Overview
Basic Machine Cycle 2-21
Clock 3-15
Execution Cycle 2-lO2
I/O Instruction 1-41
Instruction Set 2-88
Interrupt Dialogue 2-49
Page Fault 1-21
PI Dialogue 1-40
p

Page Fail
Cycle 2-35
Handling 2-38
Word Adjusting 2-41
PAGE FAIL HOLD 1-21,2-59
Page Fault 2-38
Handler 2-18
Overview 1-21
Page Mapping 1-23
Page Pointers 1-23, 1-24
Immediate 1-24, 1-25
Indirect 1-24, 1-26
Shared 1-24, 1-25
Page Table 1-19, 1-23, 2-44
Paging
Hardware Support 1-36
KI 1-19, 1-20, 1-37
KL 1-22, 1-37
Path 1-24
PC
Loading 2-72
Loading or Inhibit 2-74
Loop 2-73
Physical Memory Address Format 1-21
Physical Page Address 1-20
PI 1-46
Control 1-39
Handler 2-14, 2-18, 2-92, 2-127
Timing 2-132
Pointer Interpretation 1-28
Power Fail 3-34
Power Up Timing 3-21
Priority Transfer Lines 2-121
Process Table References 2-42

Processor
Cycles 2-1
Identification 3-40
Timing 3-15
Program Counting 2-72
Pushdown Stack 3-44
Q
Quadword

1-21
R

Restoring
Concealed Program 2-62
Kernel Program 2-64
Programs by Supervisor 2-62
User Public Program 2-64

s
Saving Flags 2-65
SBus Error 3-33
SC Field 2-87
SCAD Field 2-86
SCADA Field 2-87
SCADB Field 2-87
Section Pointer 1-23
Setup PREFETCH 2-116
SH Field 2-88
Skew Delays 3-25
SPEC Field A-9
SPT Index 1-24, 1-26
Startup /Stop Interface 2-14
SWEEP 3-38
SWEEP DONE 3-38
T
Timing
Clock Control 3-28
Power Up 3-21
TOlO Byte Pointer Fetch 2-136
TRANSFER 2-50,2-120
Translator 1-5
Trap
Cycle 2-42
Handling 2-42

UBR 1-19, 2-67
UPT 1-22

EBox/INDEX-4

v
Violation 2-62
Virtual Address 1-19
Adder 2-67
Classification 2-67
Effective 1-11
Space Configuration 2-56
VMA 1-15, 1-20,2-70
Control 1-37
Field 2-88
Register 2-70

Wait 2-10
MBox 2-11
Word Request 2-26

X,Y,Z
XCTGO 2-24, 2-26
XCTW 2-133
XFER 2-8, 2-55, 2-121

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EBoxjINDEX-5

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EK-EBOX-UD-003

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