ELTEC_PIG1_68K_May86 ELTEC PIG1 68K May86
ELTEC_PIG1_68K_May86 ELTEC_PIG1_68K_May86
User Manual: ELTEC_PIG1_68K_May86
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Documentation
PIG1/68K
Revision A
dated 5/86
DO .6801749
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Page -2-
(C) 1986 ELTEC Elektronik GmbH, Mainz
This document contains copyrighted information. All rights
including those of translation, reprint, broadcasting,
photomechanical or similar reproduction and storage or
processing in computer systems, in whole or in part, are
reserved. If single copies are made for professional
purposes with written approval of ELTEC, an allowance will
have to be paid in accordance with para. 54.2 of Urh.G.
For details please contact ELTEC.
ELTEC reserves the right
product described herein
technology at any time.
reviewed carefully ELTEC
misprints and detriments
to modify without notice the
in keeping with state-of-the-art
Although this document has been
refuses any liability due to
caused thereby.
This document is edited and printed by:
ELTEC Elektronik GmbH, 0-6500 Mainz
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Page -3-
CONTENTS
Contents
How to use this manual?
Part A Specificat ions
Scope of delivery
1
1.1
Hardware
1.2
Software support
2
Technical features
3
VME Eurocard Specification
4
Nomenclature used in this manual
Part B
1
2
3
3.1
3.2
3.3
3.4
4
4.1
4.2
4.2.1
4.2.2
4.3
5
6
7
Adaption to your system
Introduction
Default setting as board is shipped
VMEbus-Interface
Base address
Address modifier
Device addresses
Interrupter
Adaption to your monitor
Monitor synchronisation
Video signals
Separate lines
Composite video signal
Blinking
Numbers of bitplanes
Master/slave operation
External access to 1 oca 1 bus
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Page -4-
Part C Programmer's information
Registers of the ACRTC
1
1•1
Hardware accessible registers
1.2
Directly accessible registers
1.3
FIFO accessible registers
2
Frame-buffer interface of the ACRTC
2.1
Introduction
2.2
Colors and bitplanes
3
Examples to set up the ACRTC
4
The horizontal display width
Crawl
5
Zoom
6
Blinking
7
Hardware status register
8
ELTEC Elektronik GmbH Main
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Page -5-
Part D Hardware
1
VMEbus lnterface
2
Control logic for VMEbus and local Bus
3
Local hardware status-register
4
Advanced cathode ray tube controller
5
Frame-buffer interface
6
Central timing logic
7
Two-port-RAM timing generator
8
Video shift-register
9
Frame-buffer
10
Monitor interface
Appendix
Addressmodifier VMEbus
A
B
Jumpers. switches
C
Connectors
D
Sample program
E
Layout diagram
F
Parts list
G
Circuit diagrams
H
Data sheet HD63484
ELTEC E1ektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Page -6-
How to use this documentation?
-----------------------------This documentation is divided into four parts to give only
as much information as needed for a certain purpose.
Part A contains all general specifications of the
product and its documentation like scope of delivery
and technical specs and the general nomenclature used
in this manual.
Part B decribes the procedure you should follow to
adapt the product to your specific system and
peripherals.
Part C gives detailed information to the user who wants
to program the board himself.
Part D gives detailed information about the
hardware-aspects of the board for service etc.
If you only use the board with a software package, that
means as a user, not as a programmer, you should find
complete information while reading only part B.
ELTEC Elektronik GmbH
E L T E C
6 8 K -
DOCUMENTATION
PIG1/68k
PART A
00.68 01749
S Y S T
E M
ELTEC Elektronik GmbH
Main~
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part A
Page -2-
1 Scope of delivery
-----------------
1.1 Hardware
PIG1/68k •••••••••••••••••••••••••• Order No
Consisting of
PIG1/68k with 1MByte frame buffer
Dot clock generator of 55MHz
Factory configured as described
in part B, chapter 2
Documentation PIG1/68k
5 cables FE KAB 1888
FE .68 01748
PIG2/68k •••••••••••••••••••••••••• Order No
Board set consisting of
PIG1/68k with 1MByte frame buffer
and local extension of another
1MByte frame buffer
Dot clock generator of 55MHz
Factory configured as documented
Documentation-package
,
consisting of documentations
PIG1/68k and PIG2/68k
2 cables FE KAB 1888
8 cables (4 sets) FE KAB 1726
FE .68 01750
Cable (SMB-Coax to BNC, 3 mtr) •••• Order No
FE KAB 01888
Cable-set (2
*
5MB-Coax 20 cm) •••• Order No
FE KAB 01726
Documentation PIG1/68k •••••••••••• Order No
DO .68 01749
Documentation PIG2/68k •••••••••••• Order No
DO .68 01751
ELTEC Elektronik GmbH Mainz
ELTEC-68K-5Y5TEM
Documentation
PIG1/68k
Revision A 5/86
Part A
Page -3-
1.2 Software support
PIGpac for 05-9/68000
8"/77T •••• Order No
AS 059 01753
PIGpac for OS-9/68000
5"/40T •••• Order No
AS OS9 01762
PIGpac for 05-9/68000
5"/80T •••• Order No
A5 059 01763
PIGpac is a complete, modern gr ifics package,
which is completely window-orie Ited.
It consists of an OS-9/68000 de lice driver
with a terminal emulation and a 1 interface
to assembl~r and C language. Slme samples
and several monitor tables are included.
GKS-0A for OS-9/68000
8"/77T •••.• Order No
AS OS9 01770
GKS-0A for OS-9/68000
5"/40T ••••• Order No
AS OS9 01773
GKS-0A for OS-9/68000
5"/80T •••.• Order No
AS OS9 01771
GKS-0A is an implementation of the Grafical
Kernel System in accordance to 150 7942
and DIN-Standard. A C-binding is provided.
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part A
Page -4-
Dia A.2.1: B~ock diagram PIG1/68k
I' 5HIF~T-
,0
FRAME BUFFER
1M BYTE
LOCA L MEMORY
EXTENSION
,0 8 BITPLANES
MONITOR INTERFACE
Ei
X5
- --"-'o--'t;
X6
GREEN
LOG~
_
VIDEO BUFFER
o INJ Dour
BLINK CONTROL
~~-E X7
Ei
..l.
X 11
SCRATCH
X8
DOTCLOCK
VIDEO CONTROLLOCIC
MONITOR·
CONTROL'SYNC
BUFFER 1-1---==---11-0
MAD0,.19
eLK
ACRT C
HD 63 ~81.
. - - - - 1 INTERRUPT
LOGIC
' - - - - - - - - - - - - - i INT. - ID
V
t·j
.,.------1 VME bus
'-----"
CONTROL
LOGIC
E
b
'----Y
BASE ADDR.
~
----L---»-~
----- - - - - - - - - - - - - - - - - - - - - - - - - _ . /
I-LEVEL
X~
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part A
Page -5-
2 Technical specifications
-----------------------------------------------VMEbus interface in accordance to reV1Slon C
with interrupter option on all levels
-Grafics controller ACRTC HD63484
-Black and white, greyscale and color operation
-Maximum dotclock 64MHz in a l l
bitplane
configurations
-Programmable sync format and flexible
hardware interface to control nearly every
raster scan monitor on the market
-Modern dual-port video RAM architecture to
provide highest drawing speed; useful
especially with the ACRTC's powerful
bit-block operations
-Three bitplane configurations:
One bitplane with 8 MegaPixel capacity
Two bitplanes, each with 4 MegaPixel capacity
Four bitplanes, each with 2 MegaPixel capacity
-Option PIG2/68k to get 8 bitplanes with
no restriction in dotclock
-Video-Zooming with factors of 1, 2 or 4 for
both directions; separate vertical zooming
with factors of 1 to 16
-Pixel-by-pixel panning facility in both directions
-Exact pixel-based blinking attribute
-Access of local CPU-module prepared
-Software support PIGpac
-Software support GKS
ELTEC-68K-SYSTEM
ELTEC Elektronik GmbH Mainz
Documentation
PIG1/68k
Revision A 5/86
Part A
Page -6-
3 VME Eurocard Specification PIG1/68k
-----------------------------------
Slave Data Transfer Options
A16 : 016
Interrupter Options
Anyone of
1(1),1(2),1(3),1(4),1(5),1(6) or 1(7)
(STAT)
Environmental Options
Storage temperature: -55 ••• +85 degree Celsius
Operating temperature: 0 ••• +70 degree Celsius
Maximum operating humidity: 85 Percent relative
Power options
max 4.2 A (3.8 A typ)
Physical configuration options
NEXP
at +5 Volt
ELTEC
Elekt~onik
GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Pa~t A
Page -7-
4
Nomenclatu~e
of this manual
---------------------------
A hexadecimal notation is identified by a leading
sign ("$").
A bina~y notation is identified by a leading "8".
dolla~
A logic low (high) level is identified by "L" ("H") o~ "0"
("1") independent of the asse~tion-type of the signal.
Names of level-cont~olled signals p~eceded by a slash ("/")
indicate that this signal is active low.
Names of edge-cont~olled signals p~eceded by a slash ("/")
indicate that this signal becomes active with the t~ailing
edge.
Positions of jumpe~s ~efe~ to those shown in diag~am dia
8.1.1_ which are identical to pin numbe~s. If not mentioned
othe~wise, "J401:1-2" fo~ instance means, that jumpe~ J401
must be set to connect pins 1 and 2.
ELTECElektronik GmbH
E L T E C
6 8 K- S YS T E M
DOCUMENTATION
PIG1/68k
PART B
00.68 01749
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part B
Page -2-
1 Introduction
----------------------This part of the manual gives you all information necessary
to adapt the board to your system, ie to your
VMEbus-computer and monitor. If you use ELTEC's PIGpac
there should be no need to read other parts of this manual
to get started.
Please follow this procedure for adaption:
Adaption of the base address refer to chapter 3
Adaption of the address modifiers refer to chapter 3
Adaption of desired interrupt level - refer to chapter 3
Adaption to your monitor refer to chapter 4
Blinking refer to chapter 4
Adaption of numbers of bitplanes refer to chapter 5
Master/slave operation refer to chapter 6
External access to 1 oca 1 bus refer to chapter 7
Block diagram Dia A.2.1 gives an overview over the whole
board.
Diagram Dia B.l.l shows the position of all jumpers,
connectors and switches.
In appendix B you will find a complete list of all jumpers
and switches.
In appendix C you will find a complete list of all
connectors.
In chapter B.2 you find the default setting as board is
shipped.
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part B
Page -3-
Dia B.l.l: Switches, jumpers, connectors PIG1/68k
(1 i
Xl
,.---
511111
32
tliiJ
reo
o.
J1Ql
..
f
51 III 2
0
o.
>---
00
511113
~
X12
~~
1\ ~J202
J2~3
: : J80,.
~~JB01
00
:~Je02
00
00
00
00
J8Q3
00
o 0 J1~02
00
~ ~ Jl001
: : J b02
00
00
00
00
J401
~J604
HQl
@
(1
~
X l'
32
UOilJ
J
J2D1 o.
~
150
1
J603
501
1
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIGl/68k
Revision A 5/86
Part B
Page -4-
2 Default setting as board is shipped
----------------------------------$FF8D00
Base address
S101:8
S102:D
S103:0 (Non-privileged; i.e.
- Refer to chapter 3.1!
Address modifier
User-Mode 110)
short supervisory 110
SlB3:0
J101:1-2 (AM2 decoded>
- Refer to chapter 3.2!
Interrupter
J201: 1-2
- Refer to chapter 3.4!
1(7)
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part B
Page -5-
Monitor interface
- Sync signals
J1001:3-4
J1002:5-6
- Video outputs
R1001 -- 0 Ohm
R1002 -- 0 Ohm
R1003 -- 0 Ohm
R1004 -- 0 Ohm
R1005 -- no resistor
R1006 -- no resistor
R1007 -- no resistor
R1008 -- no resistor
R1009 -- no resistor
- Dot clock
- Refer to chapter 4!
Blinking
J 1003: 1-2
- refer to chapter 4!
separate syncs
positive polarity
TTL-level
TTL-l evel
U601
==
55 MHz
disabled
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part 8
Page -6-
Number of bitplanes
4 bitplanes
J6eJ2:1-2
J6eJ3: 1-2
J8eJ1: 1-2
J8eJ2:1-2
J8eJ3: 1-2
J8eJ4: 1-2
J8eJ4:3-4
J5eJ1:1-2
- refer to chapter 5!
Master/slave-mode
stand-alone
J4eJ1:1-2
J601:1-2
J604: 1-2
- refer to chapter 6!
External access to local bus
J2eJ2:1-2
J2eJ3:1-2
- refer to chapter 7!
disabled
ELTEC E1ektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part B
Page -7-
3 VMEbus-Interface
----------------
The slave PIG1/68k occupies 64 Byte in short I/O addressing
range.
All on-board devices are byte- or word-oriented. While
trying to access the board with 10ngword bus transfer cycle
or with single-byte transfer on even addresses, a bus-error
is generated.
The interrupter module can generate interrupts on all VMEbus
interrupt levels, selectable by a Jumper. Several interrupt
sources can be chosen by software.
The complete VMEbus interface logic is realized
So it is possible to make changes in addressing
devices, decoding of address modifiers etc very
ELTEC's firmware, however, expects the features
herein.
via PAL's.
the on-board
easy.
documented
The bus grant daisy chain is closed in the ·printed circuit,
so there is no need for modifications on the backplane.
You always have to remove the Jumper for the corresponding
interrupt acknowledge daisy chain on the backplane.
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part B
Page -8-
3.1 Base address
The base address can be switched via hex-switches S101, S102
and S103 in steps of 64 Bytes (address-lines A15 thru A06 short I/O).
For adaption to the desired base address its highest nibble
must be switched with S101. S102 is for the next nibble
(All thru A08). S103 determines with its lower bits A07 and
A06 of the base address. The upper bits of S103 are used to
decode adressmodifier AM2 and AMi. Please refer to chapter
B.3.2!
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part B
Page -9-
3.2 Address modifier
The address modifiers AM2 and AMl can be switched via
hex-switch S103. Please refer to table Tab B.3.1!
AM0 is decoded in a PAL to assert only with AM0=H.
AM5 and AM3 are wired to H, AM4 is wired to L (16-Bit
addressing).
With jumper J101 set to position 2-3 it is possible to
decode Adressmodifier AM2 as "don't care" to decode the
board in the non-proivileged and in the supervisory
addressing range.
Please refer to appendix A (Address modifier in the
VMEbus-specification) for further details.
Tab B.3.1: Switching the desired address modifier
AM-Code
Hex
29
2B
20
2F
AM5 AM4 AM3 AM2 AMl AM0
1
1
1
1
o
o
o
o
1
1
1
1
o
o
1
1
o
1
1
1
1
1
o
1
S103
Note
0-3
4-7
8-B
C-F
non-privileged
·reserved
supervisUry
reserved
Note:
-The lower two bits of S103 define
Address lines A07 and A06 of base address.
-Decoding of AM2 is only done if jumper
J101 is in position 1-2
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part B
Page -10-
3.3 Device addresses
Table Tab B.3.2 shows the relative addresses of allan-board
devices.
Tab 8.3.2: Relative addresses of all devices
rel addr
hex
Device
Transfer-type
R/W
Length
o
Read
Write
Both
Both
12}
2
5
HD63484 status reg
HD63484 address reg
HD63484 control regs
Hardware status reg
Word
Word
Word
Byte
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part 8
Page -11-
3.4 Interrupter
The interrupter module on PIG1/68k is able to generate
interrupts on one of any VMEbus interrupt-level. The
selection is done by jumper J201. For details please refer
to table Tab 8.3.3! Please be sure to set the levels of
request and acknowledge identically.
If you use the on-board interrupter, you must remove the
jumper for the interrupt acknowledge daisy chain on the
backplane.
For programming the internal interrupt sources and the
interrupt-1D-8yte (vector) please refer to part C!
Tab 8.3.3: Selecting the interrupt level
Desired
interrupt 1 eve 1
Jumpering J201
VMEbus
Interrupt-acknowledge
IRQ-Level
level decoding
----------_._-----------------------------------------1(7)
1(6)
1(5)
1(4)
1(3)
1(2)
1(1)
= IIRQ7
= IIRQ6
= IIRQ5
= IIRQ4
= IIRQ3
= IIRQ2
= IIRQ1
J201: 1-2
J201 :3-4
J201:5-6
J201:7-8
Level
Level
Level
Level
J201 :9-10
J201:11-12
Level 3
Level 2
J201:13-14
Level 1
7
6
5
4
= not set
= J201:19-20
= J201:17-18
= J201 17-18
J201 19-20
J201
15-16
=
J201
15-16
=
J201 19-20
= J201 15-16
J201 17-18
J201 19-20
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part 8
Page -12-
4 Adaption to your monitor
------------------------
4.1 Monitor synchronisation
PIG1/68k is able to drive monitors with different
logic-levels on the sync line(s). The voltage level is
always TTL-level.
Refer to table 8.4.1 to see what to do to adapt PIG1/68k to
the sync line(s) of your monitor. Please be sure to program
the grafic display controller with a suitable parameter set.
You have to use the corresponding dotclock generator U601,
too.
Refer to Part C for further information about parameter sets
for synchronisation and dotclock.
Refer to documentation of PIGpac to choose the correct
parameter set for your monitor under control of this
package.
To connect your monitor to PIG1/68k you should use the added
coaxial cables.
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SVSTEM
Documentation
PIG1/68k
Revision A 5/86
Part 8
Page -13-
Tab 8.4.1: Monitor syncnronisation PIG1/68k
HSV
VSV
P
P
P
N
N
P
N
N
CSV
N
Jumper
Connection
J1002:5-6
J1001:3-4
J1002:5-6
J1001:1-2
J1002:3-4
J1001:3-4
J1002:3-4
J1001:1-2
J1002:1-2
HSV'
VSV
HSV
VSV
HSV
VSV
HSV
VSV
CSV:
X3
X4
X3
X4
X3
X4
X3
X4
X3
Notes:
HSV •••••• Horizontal synchronisation
VSV •••••• Ve r t i ca 1 synchronisation
CSV •••••• Composite synchronisation
P •••••••• Positive logic-level (active hign)
N•••••••• Negat i ve logic-level (active low)
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part 8
Page -14-
4.2 Video signals
4.2.1 Separate lines
PIG1/68k is able to generate up to four bitplanes per pixel.
Normally the voltage-level is TTL. Please notice, that it
is possible to adapt the hardware to reduce the number of
planes in order to get higher pixel capacity per plan~.
Please refer to chapter 8.5!
There is a possibility to reduce the output voltage by
changing resistors R1001 to R1004. In combination with the
input-impedance (mostly 750hm) of the monitor the result is
an "analogue" signal. A good approach for 750hm-input and
1Vpp is to use 1000hm resistors instead of 00hm.
Table 8.4.2 show~ you the connectors for the bitplanes. In
case of using a standard RG8-color monitor, one bitplane is
not u~ed. If you want to apply a color monitor with a
separate white- or intensity-input you can drive it by this
scratch-plane. In other cases you can use the plane to
contrql the generate shapes to control the blink attribute
(see chapter 4.3!).
ELTEC-68K-SYSTEM
ELTEC Elektronik GmbH Mainz
Documentation
PIG1/68k
Revision A 5/86
Part B
Page -15-
Tab B.4.2: Bit planes and connectors
Monitor
B/W
B/W
B/W
Color
Color
Color
No of planes
4
2
1
4
2
1
X5
X6
X7
X8
P3
P3
P3
P2
P1
P2
P0/S
G
R
B
S
G
RIS
G
Notes:
P3-P0 ••• Weight of greyscale modulation
to be connected to a monitor
with integrated D/A-Conversion
R••••••• Red-channel
G••••••• Green-channel
B••••••• 81 ue-channel
S ••••••• Scratch-plane
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIGl/68k
Revision A 5/86
Part 8
Page -16-
4.2.2 Composite signal
Via resistors R1001 to R1008 it can be build a simple
d/a-converter (R-2*R-ladder-network) generating an analogue
signal at connector X5. Please notice, that this conversion
is not always free of glitches. Respectively with dotclocks
of more than 40MHz you should use this simple converter only
as a first approach.
To get a 1Vp-p video-signal (at 750hm video input) with 16
greyscales R1001 to R1005 must be 1000hm and R1006 to R1008
must be 500hm. If you want to generate a composite video
signal, you have to add the composite synchronsignal via
R1009 (=ca 150 Ohm). Please refer to chapter 8.4.1, too!
Tab 8.4.3: Components of video mixer
Plane
Resistor
Serial Parallel
P3
R1001
P2
R1002
R1006
P1
R1003
R1007
P0
R1004
R1008
Terminator
R1005
Note:
- PC) denotes significance of bitplane
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part B
Page -17-
4.3 Blinking
The blinking attribute can be statically enabled with jumper
J1003 set in position 2-3. If blinking is enabled, all
shapes generated in the scratch plane blink against
background (video-"black"). The blinking rate can be
programmed in the ACRTC. Please refer to part C of this
manual or to manual of PIGpac.
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part B
Page -18-
5 Number of bitplanes
-------------------------------------
In most cases PIG1/68k is used in the four bitplane mode,
where you get four planes with a capacity of 2Mega-pixels
each. Some hardware modifications can be done to define the
attributes controlled by the several planes. Please refer
to chapter 4!
In some cases it can be necessary to have a higher bitplane
capacity. As documented in table Tab B.5.1 you have to make
some adaptionso
The X-V memory configuration depends on programming the
ACRTC. Please refer to part C of this manual.
Jumper J501 is reserved for special purposes in combination
with the display memory upgrade. It should be set to
position 1-2 or left open.
Tab B.5.1: Adapting the bitplane number
Capacity per
plane (pixel)
J602
Set jumpers
J603 J801 J802
2Mega/4 planes
1-2
1-2
1-2
4Mega/2 planes
3-4
3-4
8Mega/1 plane
5-6
5-6
J803
J804
1-2
1-2
3-4
3-4
3-4
5-6
5-6
5-6
1-2
3-4
1-3
2-4
1-2
3-4
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part B
Page -19-
6 Master/slave operation
----------------------
If you want to use several PIG1/68k in parallel to work on
the same monitor, you must define one board as master, the
other(s) as slave(s).
Please be sure to make the following adaptions:
Master
- Set jumper J601:1-2 and J601:3-4
- Set jumpers J401 and J604 (default)
Slave
- Set jumper J601:1-3
- Remove jum~ers J401 and J604
- Remove U601
Connect master and slave via X9, X13, X14
(use cable-set FE KAB 1726!)
The stand-alone mode is nearly the same as the master mode
with no connection to other PIG1/68k's and with jumper
J601:1-2 only.
Of course it is possible to have several PIG1/68k in
stand-alene-mode in one system, having each of them work to
a separate monitor.
Please refer to PIGpac manual for software support!
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part B
Page -20-
7 External access to local bus
---------------------------The complete local address- and databus and most of the
lines of local controlbus are wired to connector X12. So it
is possible to access to all local devices of PIG1/68k by a
separate CPU and/or a DMA-controller, situated on a
piggy-back-board, having full advantage of a separate bus.
In low-cost applications a local CPU-module can access
without the need of a separate VMEbus-backplane.
To make external access possible it is necessary to disable
the VMEbus-buffers and -latches. Jumpers J202 and J203 are
intended for this purpose.
Because all lines on X12 are decoupled VMEbu~-lines, the
buslogic and timing on the local bus is the same as on the
VMEbus.
To enable the external access, please do the following
modifications:
- Set J202:2-3, instead of J202:1-2
- Set J203:2-3, instead of J202:1-2
ELTEC Elektronik GmbH
EL T E C
6 8 K- S v S T E M
DOCUMENTATION
PIG1/68k
PART C
00.68 01749
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part C
Page -2-
1 Registers of the ACRTC
---------------------The ACRTC occupies two wordwide VMEbus address locations,
which are documented in chapter 8.3.3 of this manual. The
ACRTC must be accessed as a wordwide device. In some cases
only the lowest 8 bits are siginificant, however.
In this chapter a short introduction is given to the ACRTC's
programming model. For more details you should read the
data sheet of the controller and other literature, which is
published by Hitachi Ltd.
The ACRTC has over two hundred bytes of accessible
registers. These are organized as Hardware, Directly and
FIFO accessible.
.
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part C
Page -3-
1.1 Hardware accessible registers
The lower address location of the ACRTC provides the status
register, when a read-cycle is performed. The status
register summarizes the ACRTC state and is used by the CPU
to monitor the overall operation of the ACRTC. When a
write-cycle is performed to the lower address-location, the
address register is activated, in order to program the ACRTC
with the address of the desired directly accessible internal
register.
Only the lower 8 bits of both registers are significant.
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part C
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1.2 Directly accessible registers
These registers are accessed by prior loading of the address
register with the chosen register address. When the CPU
accesses the higher VMEbus-address location, the chosen
register is activated.
The FIFO entry enables access to FIFO accessible registers
using the ACRTC's read and write FIFO's.
The Command Control Register CCR is used to control overall
ACRTC operation such as aborting or pausing commands,
defining DMA protocols, enabling/disabling interrupt sources
etc.
The Operation Mode Register OMR defines basic parameters of
ACRTC operation such as frame buffer access mode, display or
drawing priority, cursor and display timing skew factors,
raster scan mode etc.
The Display Control Register OCR allows the independent
enabling and diabling of each of the four ACRTC logical
display screens (Base, Upper, Lower and Window). Also this
register contains 8 bits of user defineab1e video
attributes, the Attribute Register ATR.
The Timing Control RAM TCR contains registers which define
ACRTC video timing. This includes timing specification
registers for CRT control signals, logical display screen
size and display period, blink timing and so on. The names
of some important registers are:
-
Horizontal Sync Register HSR
Horizontal Display Register HDR
Vertical Sync Register VSR
Vertical Display Register VDR
Split Screen Width Register SSW
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SVSTEM
Documentat i'on
PIG1/68k
Revision A 5/86
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The Display Control RAM OCR contains registers which define
logical screen display parameters such as start addresses,
raster addresses and memory width. Also included are the
cursor(s) definition, zoom factor and light pen registers.
The names of some important registers are:
- Memory Width Registers MWR0 .•• MWR3
- Start AddressRegisters SAR0 ••• SAR3
- Zoom Factor Register ZFR
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part C
Page -6-
1.3 FIFO accessible registers
For high performance drawing, key drawing processor
registers are coupled to the CPU via the ACRTC's separate
16-byte read and write FIFO's.
ACRTC commands are sent from the CPU via the write-FIFO to
the command register. As the ACRTC completes command
execution, the next command is automatically fetched from
the FIFO into the command register.
The pattern RAM is used to define drawing and painting
patterns. The pattern RAM is accessed using the ACRTC's
Read Pattern RAM (RPTN) and Write Pattern RAM (WPTN)
register access commands.
The Drawing Parameter Registers DPR define detailed
parameters of the drawing process, such as color control,
area control and pattern RAM pointers. The DPR's are
acess~d using the ACRTC's Read Parameter Register (RPR) and
Write Parameter Register (WPR) register access commands.
ELTEC E1ektronik GmbH Mainz
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Documentation
PIG1/68k
Revision A 5/86
Part C
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2 Frame-buffer interface of the ACRTC
-----------------------------------
2.1 Introduction
The ACRTC has a 16-bit wide data interface to the frame
buffer lines (MAD0~ •• MAD15). These 16 bits can be defined
to be from 16 pixel in one plane to 16 planes of one pixel.
On PIG1/68k all even MAO-lines are connected to the
data-port of the frame buffer. All odd lines are used for
the frame-buffer extension in the PIG2/68k-upgrade.
On PIG1/68k the frame buffer size is one MegaByte, which can
be configured as one bitp1ane with eight MegaPixe1, as two
planes with four MegaPixe1s each or as four planes with two
MegaPixe1s each. Please refer to part B of this manual for
correct adaption, concerning the hardware-videa-port.
According to the video-read-out configuration the ACRTC must
be programmed with the correct Graphic Bit Mode GBM. It is
important to have in mind, that the complete hardware is
designed for generating 8 bitp1anes with one ACRTC. If you
use PIG1/68k alone, the effective GBM must be twice the
desired number of bitp1anes.
One of the design goals of PIG1/68k was to support the high
drawing speed of the ACRTC by a suitable frame buffer
architecture. Modern video RAM-chips have been used to
reduce the need of time for display refresh to an absolute
minimum: Only one cycle per raster scan line is necessary
for that task. It is sufficient to program the ACRTC with a
horizontal display width of one, to load 4096 bits (physical
pixels) in the RAM's on-chip shift registers. In the
four-bitplane-mode 1024 logical pixels are provided for one
raster scan line, which is the maximum in that mode. In the
two-bitp1ane-mode 2048 logical pixels are provided and in
the one-bitp1ane~mode 4096 pixels per raster scan line are
possible.
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part C
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The dual-port-RAM architecture brings a very high throughput
(factor 4 to 6 in comparison to conventional
frame-buffer-concepts), but there are some restrictions,
which should be mentioned here:
- The window (fourth screen) has always
the same width as the other screens
- The horizontal pan feature (crawl) works
always within one module of logical pixels
- The horizontal memory width must always
be defined modulo the number of logical pixels
- The horizontal memory width has to be a power
of two (512, 1024, 2048 •• )
Some of these restrictions can be compensated by using the
powerful instruction set of the ACRTC efficiently. The
bit-block-operations should be mentioned in this context.
Because of the modern frame-buffer architecture they are
working and thus can be used extensively without additional
host-interaction.
ELTEC E1ektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part C
Page -9-
2.2 Colors and Bitp1anes
Controlling of the color mode is done with the Drawing
Parameter Registers and wit~in that set especially with the
color registers COL0 and CaLl. Please notice, that always
all bits must be set according to the desired color. Please
refer to table C.2.1 for details!
Tab C.2.1: Color control for PIG1/68k
Color
BLACK
GREEN
RED
BLUE
SCRATCH
YELLOW
CYAN
MAGENTA
WHITE
Control
Byte
$001
$01
$04$lel
$4el
$0:1
$11
$14$1:1
Note:
Color •••••
Register-value
GBM=3
GBM=2
GBM=l
$0000
$0101
$0404
$1010
$4040
$0505
$1111
$1414
$1515
$0000
$1111
$4444
$0000
$5555
$5555
means the effect on the monitor when
connected as described in chapter B!
Register-va1ue ••• means the effective value to be
written into the appropriate registers
with different Grafic Bit Modes GBM
--- •••••••• denotes impossible configurations
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SVSTEM
Documentation
PIG1/68k
Revision A 5/86
Part C
Page -10-
3 Examples to set up the ACRTC
----------------------------
In table C.3.1 you will find some set-up's for different
monitors. It is important to have in mind, that the
horizontal CRT sync timing is given in units of memory
cycles. The length of one cycle is the dotrate, divided by
32. The length of the vertical parameters are given in
units of raster scan lines. Please notice, like mentioned
in the ACRTC data sheet, that some of the parameters must be
subtracted by one before written into the ACRTC' registers.
Table C.3.1 shows adjusted parameters.
Please note some general hints:
- The Grafic Address Increment parameter GAl
should always be set to 2.
- The board should always be initialized as slave,
even in standalone mode.
- The grafic bit mode GBM must always be twice
the effective number of bitplanes,
if no frame-buffer extension is used.
- The display start addresses must be adjusted
by several so-called kluge-factors, which
must be subtracted from the desired display
start addresses. These factors depend on the
ACRTC's mask-version and therefore can change.
The given examples are evaluated with as-mask.
- The horizontal display width HOW should
always be set to one. The lrue parameter
must be set in the ATR (Attribute Control) register.
ELTEC Elektronik GmbH Mainz
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Documentat i'on
PIG1/68k
Revision A 5/86
Part C
Page -11-
Tab C.3.1: Set-up-examples for PIG1/68k (4 bitplane-mode)
Parameter
Notes in ()
Monitor-Type
012
Name
2
2
3
HSW
Hor Sync Width ( 1 ; 2)
45
41
Hal" Cycle (1 ;2)
HC
27
1
Hor Disp Width (1 ;2;4)
1
1
HOW
Eff Hor DislP Width (1 ;5) 19
31
31
2
6
3
HDS
Hal" Disp St.art ( 1 ; 2)
3
3
113
Ver Sync Width (1; 2)
VSW
625
625
8513
VC
Ver Cycle (1 ;2)
Ver Disp Width (1; 2)
512
512
785
SPx
67
40
Vel" Disp Start (1; 2)
VDS
67
Hor Plane Width ( 1 ; 2)
4096
1024
11324
MW
3
Graphic Bit Mode (1; 2)
3
3
GBM
2
2
2
GAl Mode ( 1 ; 2)
GAl
Operation Mode (1 ; 3)
41eB
41138
41138
Kluge Factor: (2;6)
Screen 13 (Upper)
4
4
4
4
Screen 1 (l8ase)
13
4
Screen 2 (Lower)
4
4
4
Screen 3 (Window)
13
13
13
Dotclock (7)
14
48
55
Horiz. frequency in kHz
15.6
32.13
42.13
Field frequency (8)
50
513
513
ACRTC
Reg
HSR
HSR
HDR
ATR
HDR
VDR
VSR
SSW
VDR
MWR
CCR
OMR
OMR
SARe
SAR1
SAR2
SAR3
Notes:
1 ••• Parameter given not ~egister-value
2 ••• Decimal notation
3 ••• Hexadecimal notat ion
4 ••• 0nly one cycle because of Dual-part-RAM
5 ••• Please refer to chapter C.4
6 ••• To be subtracted from desired display start address
7 ••• The dotclock is given in MHz with U6el
8 ••• ln Hz; monitor-type 13 with interlaced fields
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part C
Page -12-
4 The Horizontal Display Width
----------------------------
As mentioned earlier. the effective horizontal display width
(HOW) is programmed with register ATR. To be compatible
with the ACRTC's normal nomenclature. it is recommended to
calculate this parameter like to be written into register
HDR.
Example:
If you want to have a horizontal
display width of 1024 pixels on the screen
with the four-bitplane-mode (GBM=3)
the equivalent parameter HOW is 31 (32 minus 1).
The lower byte of register HDR should be set to one and the
effective horizontal display width must be transformed in
the following way:
First step: Complement HOW
Second step: Apply AND-mask of hex 3E
Third step: Write this value into register ATR
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part C
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5 Crawl
---------
Crawling is defined as repositioning the screen on the
display memory in horizontal direction. In general always
ACRTC·s registers SARx are used for panning. If you want to
use the horizontal pixel-by-pixel pan-feature the parameter
Start Dot Address SDA within the SAR-registers are used.
Those four bits define the offset of the screen position
within that module which can be reached with the used grafic
bit mode G8M. Please refer to table C.5.1!
Tab C.5.1: Significance of SAR-bits
G8M
011
3
2
1
x
x
x
SAR-bits
010 009
x
x
4
x
2
2
008
1
1
1
Note:
G8M ••••• means grafic bit mode, which corresponds to
the hardware-adapted number of bitplanes
x ••••••• not used - should be set to zero
1.2.4 ••• binary significance of Start Dot Address
ELTEC Elektronik GmbH Mainl
ELTEC-68K-SYSTEM
Documentation
PIG1/68k
Revision A 5/86
Part C
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6 Zoom
Programming the zoom-factor is very easy. The ACRTC has a
special Zoom Factor Register ZFR. Four bits are used for
the horizontal and another four bits are used for the
vertical zoom factor VZF. The vertical zoom factor is used
only within the ACRTC to modify vertical display refresh
addressing. All 16 factors can be used. The horizontal
zoom factor HZF is used by the ACRTC and external hardware,
which supports only factors of 1,2 and 4. That is why only
these factors should be used for horizontal zooming. Please
refer to table C.6.1!
Tab C.6.1: Allowed horizontal zoom factors
Zoom
factor
1
2
4
ZFR-Bits for HZF
015 014 013 012
o
o
o
o
o
o
o
o
1
o
1
1
Note:
ZFR •••• means Zoom Factor Register
HZF •••• means Horizontal Zoom Factor
Zoom-factor 1 stands for unzoomed display
ELTEC Elektronik GmbH Mainz
ELTEC-68K-SYSTEM
Documentation
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Revision A 5/86
Part C
Page -15-
7 Blinking
---------------
Blinking is controlled via shapes generated in the scratch
bitplane. Blinking must be hardware-enabled with Jumper
J1003 as described in part B of this manual. With ACRTC's
register BCR
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