F 57_pdp5maint_Oct64 57 Pdp5maint Oct64
F-57_pdp5maint_Oct64 F-57_pdp5maint_Oct64
User Manual: F-57_pdp5maint_Oct64
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F-57 PROGRAMMED DATA PROCESSOR-5 MAINTENANCE MANUAL DIGITAL EQUIPMENT CORPORATION • MAYNARD, MASSACHUSETTS COpy NO. Thismanualcontainsproprietary information. It is provided to the customers of Digital Equipment Corporation to help them properly use and maintain DEC equipment. Revealing the contents to any person or organization for any other purpose is prohibited. Copyright 1964 by Digital Equipment Corporation 75047 PRINTED IN " U.S.A. 10-10/64 PREFACE This manual contains information for the planning and execution of all tasks involved in the installation, operation, and maintenance of the Programmed Data Processor-5, a core memory, stored program, parallel, digital computer designed and manufactured by the Digital Equipment Corporation. Information in this manual is prepared for engineers and technicians familiar with digital logic: techniques and digital computer principles, and is not intended to teach basic theory. The manual does attempt to describe and explain the operation of the PDP-5 computer in detail. Every attempt has been made to organize this manual to allow rapid access of information required for a specific task. In an attempt to emphasize the importance of study and planning before the actual performance of a physical task, the first portion of this manual contains exposaory information, and the last portion contains task-oriented information and detailed procedures. This manual is organized into the following sections: Section 1, Introduction and Description - Information of a general nature which is applicable to the entire PDP-5 system is contained in this chapter. The chapter contains a detailed summary which describes the system as consisting of a processor, core memory, and input/output facilities. An understanding of this information is a prerequisite for reading the chapters containing detailed theory. Section 2, Processor; Section 3, Core Memory; and Section 4, Input/Output - These chapters contain detailed theory of operation for the three major logic elements which constitute the PDP-5. The function of each circuit is explained and the generation of all control signals is described in detail with the aid of references to the block schematic engineering drawings. Section 5, Logic Function - All operations involved in the performance of computing functions are described in detail in this chapter with, the aid of the engineering flow diagram. Opera- tions are described in detai I with regard to accompl ish ing a spec ific task and are not encumbered by explanations of circuit operations as described in the previous chapters. Th is chapter tends to integrate the reader's understanding of the functions performed by the processor, core memory, and input/output logic el ements. iii Section 6, Interface - The technical characteristics of the interface circuits of the PDP-5 are defined and described in detai I in th is chapter to a II ow adequate design and installation planning of special peripheral equipment. Section 7, Installation - Information is contained in this chapter to allow personnel to plan and implement the installation of a PDP-5 system. Section 8, Operation - The function of controls and indicators of the computer and the standard Teletype unit are listed, and procedures are given to allow operation of this system. These procedures are written to allow interpretation and expansion required for the performance of spec ific tasks. Section 9, Maintenance - Planning information and specific detailed procedures are contained in this chapter to allow personnel to perform thorough preventive maintenance and rapid logical corrective maintenance of the standard PDP-5. Section 10, Pertinent Documents - Reference material in the form of a I ist of publ ications and copies of the engineering drawings are reproduced in this chapter as an aid to understanding the information contained in the manual. iv CONTENTS Section 2 Page INTRODUCTION AND DESCRIPTION ......................... . 1-1 Computer Organization ................................... 1-1 Proc essor ........................................... 1- 1 Core Memory .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -4 Input/Output .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -5 Functional Description.................................... 1-6 Instructions ......................................... 1-6 Major States ........................................ 1-9 Time States ......................................... 1-10 Physical Description...................................... 1-11 Specifications ........................................... 1-12 Physical ............................................ 1-12 Electrical ........................................... 1-13 Ambient Conditions .................................. 1-13 Fun c t i 0 na I .......................................... 1 - 13 Symbols and Term inology ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 PROCESSOR ............................................... . 2-1 Power C Iear Generator (5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Special Pulse Generator (5) ............................... 2-2 Timing Signal Generator (17) .............................. 2-3 Operator Console (WD-D-5-0-10) ... . . . . . . . . . . . . . . . . . . . . . . . 2-6 Interlock and POWER Switches. . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Key Circuits ..........................•............. 2-7 Indicator Circuits .................................... 2-7 SWITCH REGISTER Toggle Switch Circuits... . .. ......... 2-7 Run and 10 Halt Control (5) ............................... 2-8 Program Counter ......................................... 2-9 Instruction Register (6) ................ . . . . . . . . . . . . . . . . . . . . 2-9 Major State Generator (6) ................................. 2-11 v CONTENTS (continued) Page Section 3 4 Memory Address Register Control (7) ....................... . 2-14 Memory Buffer Register Control (7) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Accumulator Control (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Memory Address Register (9) ..........•.....•...••......... 2-23 Memory Buffer Register (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 Accumu lator (9) . . . . . . . . • . • • . . . • . . . . . . . . . • . . • • • • . . . . . . • • . • 2-25 Link (9) . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . • . • • . • . . . . . . . . . . . • 2-27 Output Bus Dr ivers (31) ................................... 2-27 Input Mixer (14) ......................................... 2-28 Skip Control (8).......................................... 2-28 lOP Pulse Generator (6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 Program Interrupt Synchron ization (8) ....................... 2-32 Type 153 Automatic Multiply and Divide Option.............. 2-33 CORE MEMORY ............................................ . 3-1 Memory Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Current Source.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Memory Drivers (17) ...................................... 3-7 Address Selection (16) .................................... 3-9 Memory Diode Units and Core Array (11, 12)................. 3-10 Inhibit Selections (17) .................................... 3-11 Sense Amplifiers (17) ..................................... 3-12 Type 154 Memory Extension Control Option...... . . . . . . . . . . . . 3-13 Type 155 Memory Module Option. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 INPUT/OUTPUT ............................................ . 4-1 Teletype Model 33 Automatic Send Receive Set .............. . 4-2 Te letype Control (18) .................................... . 4-3 Type 137 Ana log-to- Di gita I Converter (137-2-1) ............. 4-6 vi CONTENTS (continued) Page Section 5 6 LOGIC FUNCTION ........ , ................................ . 5-1 Manual Operation.. . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 LOAD ADDRESS Key ............................. 5-2 DEPOS IT Key. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 EXAMINE Key... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 START Key .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 CONTINUE Key.. ... . .. .. . . . . .. .. . ..... ... .. ... . 5-4 STOP Key ...................................... 5-4 SINGLE STEP and SINGLE INST. Keys.............. 5-5 Automatic Operation ..................•.................. 5-5 Instructions ......................................... 5-5 Logical AN D (AN D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Twos Complement Add (TAD) . . . . . . . . . . . . . . . . . . . . . . . 5-7 Index and Skip if Zero (ISZ) ... . . . . . . . . . . . . . . . • . . . . 5-8 Deposit and Clear Accumulator (DCA) ... . .... . .. . .. . 5-8 Jump to Subroutine (JMS) ......................... 5-9 Jump (JMP) ..................................... 5-10 Input/Output Transfer (lOT) ....................... 5-11 Operate (OPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Program Interrupt.......... . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Data Break .......................................... 5- 15 INTERFACE ....................•..•...................•..... 6-1 Loading and Driving Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Base Load ........................................... 6-8 Pu Ise Load .................•........................ 6-8 Pu Ised Em i tter Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 DC Em itter Load ..................................... 6-9 Power C I ear Generator (5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • 6-10 Special Pulse Generator (5) and Timing Signal Generator (17) . . • 6-10 vii CONTENTS (continued) Page Section Run and I/O Halt Control (5) .............................. . 6-10 Run ................................................ . 6-10 1/ 0 Ha It and Restart .................•................ 6-11 Major State Generator (6) ................................ . 6-12 Break Request ....................................... . 6-12 Break ...........................•................... 6-12 Memory Address Register Control (7) ...•..................... 6-12 Address Accepted ................•.................... 6-12 Increment Request ............................. 6-13 Memory Buffer Register Control (7) . Transfer Direction . 0 0 • 0 • 0 0 0 0 0 000 0 • 0 • 0 0 0 0 0 0 000 0 0 ••• 0 0 0 ••••• 0 • 0 0 0 0 0 0 0 0 • 0 0 0 0 0 000 • 00 0 •• 0 0 0 Accumu lator Contro I (8) 0 0 ••••• Addre~ss Accept~ed ... 0 ••• 0 0 •••• 0 0 0 0 0 • 0 •• • ..... •• 0 0 0 0 • 0 0 ••••• ••••••• 0 •• •••••• 0 •• 0 ••• Memory Address Reg ister (9) ............... Memory Buffer Register (9) .... MB Outputs ........... 0 Increment MB ........ 0 0 •••• 0 ••••• ••• 0 •••• 0 ••••• 0 ••••••••••• • 0 0 •••••• 0 0 ••••••••••••••••• 0 •••••• 0 ••• •••••••••••••••••• 0 0 0 ••• 0 0 0 0 0 ••••• Data Bit Inputs .................. AC Outputs ... o...... AC Inputs .......... 0 0 •• 0 ••••• •••••• Skip Control (8) ................ lOP Pulse Generator (6) ...... 0 0 ••• INSTALLATION.o.o. o. 0., 0 Site Preparation ....... 0" 0 0 o... . ••• 0 ••••• •• 0 •• 0 0 •••••• 0 •••••• 0 0 •• • •••••••••••••• 0 '.' 0 •• 0 ••• 0 •••• 0 0 ••• 0 • 0 ••• 0 0 0 0 '0 0 • 0 • 0 ••••• 0 • 0 ••••••• 0 •• 0 ••••••••••••••••• ••••••••••••• 0 •• 0 0 0 • •••••••• 0 •••• • 0 0 •• 0 0 •• •• •••••• ••••••••••••• •••••••••••••••••••••••••• vii i •••••••• •• • 0 Program Interrupt Synchron i zat ion (6) .. Device Selector (RS-4605) . •• ••••••••••••••••••••••••••• •••• 0 0 ••••••••••••••• Accumu lator (9) and Input Mixer (14) ............ 7 6-13 6-14 Data - - . . MB Clear AC .... 6-13 0 ••••••• 6-14 6-14 6-14 6-15 6-15 6-15 6-16 6-16 6-17 6-17 6-17 6-18 6-18 6-19 6-19 7-1 7-1 CON TEN TS (c 0 n tin u e d ) Page Section 8 9 Preparat ion for Sh ipment .................................. . 7-3 Installation Procedure ....................•................ 7-5 OPERATION ................................................ . 8-1 Controls and Indicators .................................... 8-1 Operating Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . 8-8 Manua I Data Storage and Modi fication . . . . . . . . . . . . . . . . . . . 8-8 Loading Data Under Program Control. . . . . . . . . . . . . . . . . . . . . 8-10 Off-L i ne Tel etype Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 Assembling Programs with PAL .................•........ 8-13 Tel etype Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . • . . 8-14 Programming .....•...............•....................... 8-19 MA INTENANCE ..................................•........... 9-1 Preventive Maintenance 9-4 Mechanical Checks 9-4 Power Supply Checks . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . • . . 9-5 Marginal Checks. . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 Memory Current Check ................................ 9-11 Sense Amplifier Check. . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . 9-12 Type 137 Analog-to-Digital Converter Maintenance ....... 9-12 Converter Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 Integrating Single Shot Check and Adjustment. . . . . . . . . 9-16 Prec ision Power Supply Check and Adjustment. . . . . . . . . 9-16 Di gital-to-Ana log Converter Check and Adjustment. . . . 9-17 The Difference Ampl ifier Check and Adjustment. . . . . . . 9-22 Corrective Maintenance ................................... 9-23 Preliminary Investigation..... . ..... ... .... . ....... . .... 9-24 System Troubleshooting.... .. ........................ .. 9-25 Memory Troubleshooting ........................... 9-25 Logic Troubleshooting 9-27 ix CONTENTS (continued) Section Page Signal Tracing... .. ..... ................... .. ..... 9-28 0... 9-28 Aggravation Tests •••.......................... Circuit Troubleshooting ............ o. Module Circuits .......... In-Line Dynamic Tests ..... 0 •••••••• 0 •• 0 •• •••• 0 •••••••• 0 ••••• 0 ••• 0 0 0 •••••• 0 0 o. ••• ••• 0 • 0 •••• o. 000 o •••••• •• 0 0 • 0.0.00 In-Line Marginal Checks ...•..•.............. Static Bench Tests ... 0 • • 0 • 0 0 0 • • • • • • • Dynamic Bench Tests............ ................ .. Repa ir •..•......... Spare Parts .. 0 ••• 0 0 •••••••••• ••••••• 0 •• 0 0 •••• 0 ••••••••••• ••••••• 0 •• 0 0 • • • • • ••••••••• 0 0 • • • Standard PDP-5 Spare Module List ......... 0 0 •••• 0... 9-29 9·-29 9-30 9-31 9-32 9-34 9-34 9-35 9-37 Type 34B Osc illoscope Display Spare Module List. . . . . . 9-38 Type 50 Magnetic Tape Transport Spare Module List ...... 9-38 0 • 0 • 0 ••••••••••••••• 0 •• 0 0 •••• Type 57A Automatic Tape Control with Type 157 Interfac e Spare Modu Ie List ........... Type 75A High Speed Perforated Tape Punch and Control Spare Module List ..... 0 •• Type 137 Analog-to-Digital Converter Spare Modu Ie Li st ........... 0 •••••• Type 139 General Purpose Multiplexer and Control Spare Module List. 0 ••• 0 0 0 •• •••• 0 •••• 00 •••• ••••• •••• Type 153 Automatic Multiply and Divide Spare Module List ... o 0 ••••• 0 • 0 0.0. 0 •••••••••• 0 •• 0 •••• 0 • 0 0 • • 0 • • • • • 0 ••• 0 • • • 0 • • 0 •••• 0... ••••••••• • 0 0 Type 154 Memory Extension Control Spare Module List ... 0 0 ••• •• 0..... 9-38 9-38 9-38 9-38 9-38 9-38 Type 155 Memory Module Spare Module List.......... 9-38 Type 350 Incremental Plotter and Control Spare Modu Ie Li st .... 9-39 0 •• 0 ••••••• 0 • 0 •• 0 • • • Type 552 DECtape (formerly called Microtape) Contro I Spare Modu IeLi st ...... 0 • • • • Type 750 High Speed Tape Reader and Control Spare Modu Ie List ........... Val idation Test ...... 0 x 0 •••• 0 • • • • • • • • • • • • • • • • • • • • • • • • 0 • • • • • • • • • • • • • • 0 • • • • • • • • • •••••••••••••••• 9-39 9-39 9-39 CONTENTS (continued) Section Page Log Entry ......................................•..... 10 9-40 PERTINENT DOCUMENTS .................................... . 10-1 Publications ..................•.......•......... .;. ....... 10-1 Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . • 10-2 Power Supply and Control. . . . . . . . . . . . • . . . • . . . . . . . . . . . . . 10-2 System Modu Ies .....................•........•.•..... 10-2 Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . 10-4 Module Location and Wiring .....................•..... 10-5 TABLES Table 3-1 Read-Write Switch Gating .................•...........•....... 3-10 4-1 Tel etype Control Interface with Processor ..................•..... 4-3 4-2 Analog-to-Digital Converter Interface with Processor ........•..... 4-8 4-3 Characteristics of the 137 ..................................... . 4-9 6-1 Input Signals ...................................•............. 6-2 6-2 Output Signals .........................................•..... 6-5 8-1 Operator Console Controls and Indicators ................•....... 8-2 8-2 Teletype Controls and Indicators ...............................• 8-6 8-3 Readin Mode Loader Program ...........•....................... 8-9 8-4 Tel etype Code ...................•............................ 8-15 9-1 Maintenance Equipment ....•.................................. 9-1 9-2 Maintenance Controls and Indicators ........................... . 9-3 9-3 Type 779 Power Supply Outputs ................................• 9-6 9-4 Maindec Programs Used in Marginal Checking ................... . 9-10 9-5 Analog-Digital Number Conversion ............................ . 9-15 9-6 Digital-to-Analog Converter Adjustment Program ................ . 9-19 9-7 Suggested Spare Semiconductors ............................... . 9-35 xi TABLES (continued) Page Table 9-8 Suggested Miscellaneous Spare Parts ............................ . 9-36 9-9 Suggested Spare Parts for Type 50 Magnet ic Tape Transports ........ . 9-37 ILLUSTRATIONS Figure 1-1 A Standard PDP-5 System xvi 1-2 Simpl ified Block Diagram 1-2 1-3 Instruction Formats .............•......•....•...•....•........• 1-7 1-4 Component Locations ......................................... . 1-12 1-5 Logic Symbols ............................................... . 1-15 2-1 Timing Diagram ................................•............. 2-4 3-1 Core Memory Block Diagram (During Writing) .................... . 3-3 3-2 Core Memory Drive System Equivalent Circuit. ................... . 3-4 5-1 Data Break Timing ........................................... . 5-16 7-1 Installation Outl ine Drawing .................................. . 7-2 7-2 Installation Connections ...................................... . 7-6 8-1 Sta ndard Operator Conso Ie ................................... . 8-1 8-2 Operator Console with Type 153 Automatic Multiply and Divide and Type 154 Memory Extension Control ........................ . 8-2 Teletype Console ...................•.....•................... 8-6 8-3 DRAWINGS Drawing RS-735 Power Supply ..................................•............. 10-7 RS-1701 Power Supply Control .................•....................... 10-7 RS-737 Power Supply ............................................... . 10-9 RS-779 Power Supply 10-9 RS-832 Two Step Power Contro I ...................................... . 10-11 xii DRAWINGS (continued) Drawing Page RS-1000 Clamped Load Resistors •••.....•.•.•.••••.......•.••..••••.••. 10-11 RS-1011 Diode ..................................................... . 10-13 RS-1020 Memory Diode Unit •.•.............•..•....••............••.• 10-13 RS-1151 Bi nary-to- Octa I Decod~r ..•.........••. > ••••••••••••••••••••• 10-15 RS-1310 Delay Line •.••..•....••...•...••.•.••••.•..•..•••..•.•.•.•.. 10-15 RS-1311 De lay Line .•..••....•.•..•.•.•.••••...•.••.•..•.••..•..•.... 10-17 RS-1406 Crystal Clock •..•.....•...••.•....••..••..•.•..••......•••.. 10-17 RS-1571 Dual Sense Amplifier .•..•.••...•.•.•.•.••...••...•......•.••• 10-19 RS-1572 Difference Ampl ifier ......••.•••.......••.••..••..•.•..•..•.. 10-21 RS-1574 12-Bit Digital-to-Analog Converter .•...••....••...•...••.•..•• 10-21 RS-1607 Pu I se Amp Ii fi er ............•..........•.••..•..•...•....•..•. 10-23 RS-1684 Bus Driver 10-23 RS-1685 Bus Driver 10-25 RS-1704 -10V Prec is ion Power Supply .••••......•...•...............•.•. 10-25 RS-1976 Res i stor Board 10-27 RS-1978 Resistor Board 10-27 RS-1982 Inhibit Driver 10-29 RS-1987 Read-Write Switch .••....................•.......•........•.• 10-29 RS-1989 Memory Driver ...........•......•.....................•...•. 10-31 RS-4102 Inverter 10-31 RS-4106 Inverter 10-33 RS-4111 Diode ...............••..•••.•.....•.........••.••........•. 10-33 RS-4112 Negative Diode NOR ......•.......•...•.......•............. 10-35 RS-4113 Diode ..................................•.•..............••. 10-35 RS-4114 Negative Diode NOR •......•.•.........•..••••...•......•... 10-37 RS-4115 Positive Diode NOR ....•....•••...•......•.•................. 10-37 RS-4116 Diode ..•..........•......•.......•.••.•••.................. 10-39 RS-4117 Positive Diode NOR ...........•........•....•.•........•..... 10-39 RS-4123 Negative Capac itor Diode Gate ....•....••...................• 10-41 RS-4127 Pulse Inverter 10-41 xiii DRAWINGS (continued) Drawing Page RS-4129 Pulse Inverter ••••.•••.•••••••••.•.•.•.•.••.•••..••.•.••••••.. 10-43 RS-4130 Pos itive Capac i.tor- Diode Gate •••.•..••.•.•••••....•.•••.•....• 10-43 RS-4151 Binary-to-Octa I Decoder ••.•...•....•••..••.•••.••••..•....•.• 10-45 RS-4205 Dual Flip-Flop ••...•••.•••..•.••.••.•..•.•..•.•.•..•.•..•••.• 10-45 RS-4206 Triple Flip-Flop ••...•••.•.•....•.••.••....•••.••.•••.•••••.•• 10-47 RS-4215 4-B it Counter ..••.••..• ,•.•.•.•••.••..•••••.••.•.••••.••••.••• 10-49 RS-4217 4-8 it Counter ............................................... . 10-49 RS-4218 Quadruple FI ip-Flop ••.•.•••••.•••••••••.•••••••••.••.•••••... 10-51 RS-4220 a-Bit Buffer Register ..................•......................• 10~51 RS-4225 8-Bit BCD or Binary Counter .•.••••.•.•••.•.••••.••..•.•.•.••.• 10-53 RS-4231 Quadruple Flip-Flop ••...•....•....•..••..•..••.•.•.•.••....•. 10-55 RS-4301 Delay (One Shot) ••..........•..••.••.•...••...•.•••••••.••.• 10-57 RS-4303 Integrating Single Shot ••••....•.••••••••.••.•.••.•.•.•.••••••• 10-57 RS-4401 Variable Clock ..•..•..•.•.••.•.••••....•••...•.••••.•••..••.• 10-59 RS-4407 Crystal Clock •.•.•...•...••..•••.••••••••••••.•••••••••••••• 10-59 RS-4410 Pu Ise Generator ............................................. . 10-61 RS-4554 Dual Sense Amplifier •••••••..••••••.....••..••.•••..•••••••••. 10-63 RS-4603 Pu I se Amp Ii fi er ..•.•..•••.•••.•..•.•••••.••.••••..•••••••••.•• 10-65 RS-4604 Pulse Amplifier ...••, .••••• ,•.••.••••••..•.•.•.•••.••....•••.••• 10-65 RS-4605 Pulse Amplifier .•.••••••.•••••..•.•...••.••••• ',' ••••.••••••••• 10-67 RS-4606 Pulse Amplifier .......•.•.••..•.••••.••..•.••.••..•••••••.••.• 10-67 RS-4678 Level Amplifier .•...•.. 10-69 RS-4706 Teletype Incoming Line Unit ••.•.......•.....•••••.••.•••.••.•• 10-71 RS-4707 Teletype Transmitter .....••.•••••.....•.....••••••...•••...••• 10-73 RS-4801 22-Pin Plug Adapter with Bus Driver •••••••.••.•..••••.•.. ' .••.••• 10-75 RS-4802 22-Pin Plug Adapter with Bus Driver ••...•..••••.• 10-75 RS-4903 18-Lamp Bracket •••.......•....•••.•••.••...••••.••.•••••.••• 10-77 RS-4904 9-Lamp Bracket ••.•..•••....•••.••..•.•••.•••••••...•.•••..•• 10-77 RS-6102 Inverter .................................................... . 10-79 0 ••••••••••••••••••••••••••••••••••••••• xiv 0 •••••••••••••• DRAWINGS (continued) Drawing Page FO-0-5-0--2 Flow Diagram .••...................................... 10-81 BS-0-5-0-5 Keys, Switches, Run, I/O Halt, SP's, Power Clear ....... ~. 10-83 BS-0-5-0-6 Major States, Instruction Register, 10p·s ................. . 10-85 BS-0-5-0-7 MA and MB Contro I •................................... 10-87 BS-E-5-0-8 AC Control, Skip, and Interrupt Sync .••................• 10-89 BS-E-5-0-9 Link, AC, MB, MA (Sheet 1 of 2) •............•.•......• 10-91 BS-E-5-0-9 Link, AC, MB, MA (Sheet 2 of 2) 10-93 BS-E-5-0- '11 Memory Stack Diagram 4K •.•........................... 10-95 BS-E-5-0- '12 Memory Stack Diagram 1 K ..•.•..•.....•...•..•......... 10-97 BS-0-5-0-14 Input Mixer ........... ................................ . 10-99 BS-0-5-0-16 Memory II X" and Se lection ........•..............•.. 10-101 BS-0-5-0-17 Memory System Timing, Inhibit, Sense Amplifier Output .•.. 10-103 BS-0-5-0-18 Keyboard/Pr inter Contro I •.•..•.....................•..• 10-105 BS-0-5-0-31 Output Bus Dr ivers ••..•...•....••....•......•.......•.. 10-107 BS-0-137-0-1 Analog-to-Oigital Converter •........................... 10-109 BS-0-153-0-5 AR Control, lOT Gen., Step Counter, Time Gen ..•....... 10-111 BS-0-153-0-6 MQ Register ........•.........................•....... 10-113 BS-0-153-0-7 AR Register •..........•...................•.•.•...•... 10-115 FO-0-153-0-11 Flow Diagram, Automatic Multiply and •............ 10-117 BS-0-154-0-4 Memory Extension Logic ...•........•.........•.•....... 10-119 ML-0-5-0··15 System Module Location •...............•...........•... 10-121 WO-E-5-0··3 Wiring Diagram lA, lB, lC •.•.......................... 10-123 WO-E-5-0··4 Wiring Diagram 10, 1E, 1 F .•........................... 10-125 WO-0-5-0,-10 Operator Control Keys and Switc hes ....................•. 10-127 UML - 0- 15:3-0-3 Ut iii zat ion Modu Ie List for Type 153 ...............•..... 10-129 WO-0-153·-0-4 Wiri ng Diagram 1 K and 1L (Sheet 1 of 2) ................. . 10-131 WO-0-153·-0-4 Wiring Diagram 1 K and 1L (Sheet 2 of 2) ................. . 10-133 UML - 0-154-0-6 Utilization Module List for Type 154 .................•... 10-135 WO- 0-1 54·-0-5 Wiring Diagram for Type 154 ............•............... 10-137 lIyll xv ~ivide Figure 1-1 A Standard PDP-5 System xvi SECTION 1 INTRODUCTION AND DESCRIPTION The Digital Equipment Corporation (DEC) Programmed Data Processor-5 (PDP-5) is a small, general-purpose, stored-program, d!gital computer that performs 2 1 s complement binary arithmetic. The PDP-5 is a l-address, 12-bit, parallel machine with a 6-microsecond cycle time. A standard PDP-5 contains a 1024- or 4096-word ferrite-core memory, which can be expanded in fields of 4096 words to a 32, 768-word maximum by the addition of memory options. Highcapacity, flexible, input/output circuits of the computer allow it to operate all types of modern peripheral data processing equipment and many types of process control instruments. Standard equipment for the PDP-5 includes a Teletype unit that provides an input to the computer from a keyboard or perforated tape and provides a page printer or perforated-tape output. COMPUTER ORGANIZATION The PDP-5 Is a completely integrated system constructed of standard DEC system modules using transistor-diode switching circuits and self-contained solid-state power supplies. The computer operat~s on static dc levels, or the shift of them, and is organized into a data processor, a core memory, and facilities for input/output devices. The major functional elements of the PDP-5 and their sinnal interrelationship are shown in Figure 1-2. Processor All arithmetic, logic, and system control operations of the standard PDP-5 are performed by the processor. The major circuit elements which perform these functions are as follows: Accumulator (AC) - The AC is the primary arithmetic register of the PDP-5. It also serves as an input/output register for programmed information transfers between core memory and peripheral equipment. Link (L) - This 1-bit register serves as an extension of the AC and is used as a carry or overflow register for arithmetic operations. 1-1 ADDRESS DATA MA CONTROL AC CONTROL INPUT MIXER A C C DATA U M U 12 MB CONTROL L A T DATA MEMORY ADDRESS REGISTER o R OPTIONAL PERIPHERAL EQUIPMENT USING PROGRAMMED DATA TRANSFERS DATA { OUTPUT BUS DRIVERS DATA 12 12 LINK SELECT CODE MEMORY BUFFER REGISTER 12 I t-.:.) ~ OPTIONAL PERIPHERAL EQUIPMENT USING THE DATA BREAK FACILITIES DATA BREAK REQUEST ADDRESS IOP PULSES IOP PULSE GENERATOR IO HALT RESTART ALL OPTIONAL PERIPHERAL EQUIPMENT ~ SKIP PROGRAM INTERRUPT ... RUN AND IO HALT CONTROL - SKIP CONTROL - PROGRAM INTERRUPT SYNCHRONIZATION -'" TIMING SIGNAL GENERATOR SPECIAL PULSE GENERATOR POWER CLEAR PULSE GENERATOR ~~~-----INPUT/OUTPUT ------~~~4~------------------------------------PROCESSOR-----------------------------------------1~~~~------CORE MEMORY----------~~~ Figure 1-2 Simp\ ifi ed Block Diagram Memory Buffer Register (MB) - The MB serves as a buffer register for all information passing between the processor and the core memory. The MB also serves as a buffer directl y between core memory and peripheral equipment during data break information transfers and is used as a digital sh ift register for the Type 137 Analog-To·-Digital Converter option. Memory Address Register (MA) - The location in core memory which is selected for data storage or retrieval is determined by the MA. This 12-bit register can directly address all 4096 words of thc~ standard core memory. Instruction Register (lR) - This 4-bit register is loaded from the four most significant bits of the MB during () fetch cycle and so contains the four most significant bits of the instruction to be performed. The contents of the three most significant bits of the IR are decoded to produce the eight instruction performed by the computer. The least significant bit of the IR serves as a control bIt to specify direct or indirect addressing of core memory to locate the operand during memory reference instructions, and is used to di fferentiate between the two groups of operate instructions. Major State Generator - Two or more major control states are entered to determine and execute an ins1-ruction. The major state generator produces the signals wh ich determine the machine state during each computer cycle. Each state is produced as a function of the current instruction, the current state, and the condition of the Break Request signal suppl ied to an input bus by peripheral equipment. Program Counter (PC) - The address in core memory from which the next instruction will be drawn is controlled by the PC. The PC is located in address 0000 of core memory. Input Mixer (1M) - The 1M extends the input gating capabil ity of the accumulator to allow it to handle information received from the switch register, the Teletype unit, and from peripheral equipment. Switch Register (SR) - Twelve toggle switches on the operator console allow manual selection of addresses to be set into the MA and data to be written in core memory by passing through the 1M, AC, and MB. Output Bus Drivers - When necessary, output signals from the computer can be power ampl ified by removal of dummy plugs and insertion of output bus driver modules. 1-3 Basic Timing Generators - Timing pulses used to determine the 6-microsecond computer cycle time and produce time-synchronized gating operations are produced by the timing signal generator. Timing pulses used during operations resulting from use of the keys and switches on the operator console are produced by the special pulse generator. Pulses that reset registers and control circuits during power turn on and turn off operations are produced by the power c Iear pu Ise generator. Control Elements - Circuits are also included in the PDP-5 that produce the lOP pulses that initiate operations involved in input/output transfers, determine the advance of the computer program under normal and I/O halt/restart conditions, allow instructions to be skipped as a function of the status of registers and control circuits within the computer or in peripheral equipment, and allow peripheral equipment to cause an interruption of the main computer program to transfer program control to a subroutine which performs some service for the I/O device. Other control elements generate the signals that control and activate the AC, MB, and MA. Core Memory Permanent (longer than one instruction time) local information storage and retrieval operations are performed by the core memory. The memory is continuously cycling, automatically performing a read and write operation during each computer cycle. Input and output address and data buffering for the core memory is performed by the MA and MB of the processor, and operation of the memory is under control of signals produced by the timing signal generator of the processor. The major functional elements of the core memory are as follows: Memory Drivers - The direction of read-write drive current passing through the address drive Iines of the core memory is determined by the memory drivers. Address Selection - Addresses contained in the MAare decoded to enable passage of readwrite current through an X and a Y drive I ine of the core memory. Inhibit Selection - Data to be written in core memory is contained in the MB. Since the read-write current passing through the address selection Iines produce binary ones in each bit of the addressed memory register, the inhibit selection circuits inhibit setting of cores in planes corresponding to bits of the MB containing zeros. 1-4 Memory Diode Units and Core Array - The ferrite core array consists of 12 planes that are 64 cores wide by 64 cores deep for a 4096-word memory. Memory diode unit modules connected directl y to the array prevent read-write current from passing through unsel ected drive lines. Sense Ampl ifiers - Signals induced on the sense windings of the core array during reading are detected by the sense ampl ifiers and converted ,to pulses that set corresponding bits of the MB to transfer information from a specific address in core memory to the MB. Input/Output Interface circuits for the processor allow bussed connections to a variety of peripheral equipment. Each input/output device is responsible for detecting its own select code and for providing any necessary input or output gating. Ind ividually programmed data transfers between the processor and peripheral equipment take place through the accumulator. Single or multipi e data trclnsfers can be in itiated by peripheral equipment, rather than by the program, by means of the data break faci! ities. Standard features of the PDP-5 also allow peripheral equipment to perform certain control functions such as program stop and start by means of the I/O hal t and restart fac iI i ties, instruction sk i pping, and program contro I transfers in itiated by a program interrupt. Standard peripheral equipment provided with each PDP-5 system consists of a Teletype Model 33 Automaf'ic Send Receive set and a Teletype control. The Teletype unit is a standard mach ine operclting from serial 11-un it-code characters at a rate of ten characters per second. The Teletype provides a means of supplying data to the computer from perforated tape or by means, of a keyboard, and suppl ies data as an output from the computer in the form of perforated tape or typed copy. The Teletype control serves as a serial-to-parallel converter for Teletype inputs to the computer and serves as a parallel-to-serial converter for computer output signals to the Teletype unit. Faci! ities for the Type 137 Analog- To-Digital Converter are wired into each PDP-5. The converter operates by the successive approximation process, using the computer memory buffer register as a distributor shift register and using the accumulator as a digital buffer register. Conversion time for this option is a function of the predetermined accuracy, which varies 1-5 from 24.5 microseconds for 6-bi t accuracy to 132 mi croseconds for 11-bit accuracy. The converter is able to use the registers of the computer because it stops the computer program by means of the I/O hal t faci I ity during its operation. Space and wiring within the processor are provided so that activation of this option requires I ittle more than insertion of eight modules in a mounting panel. Standard equipment, which can be obtained as peripheral equipment for the PDP-5 at the customer's option, includes high-speed perforated-tape readers and punches, card readers and punches, line printers and digital plotters, a variety of cathode-ray tube display equipment, a choice of magnetic tape equipment, Teletype data communication equipment, and multiplexer equipment which allows up to four I/O devices to use the computer data break facilities. FUNCTIONAL DESCRIPTION Operation of the computer is accompl ished on a Iimited scale by keys on the operator console. Operation in this manner is I imited to address and data storage by means of the switch register, core memory data examination, the norma I start/stop/continue control, and the single step or single instruction operation that allows a program to be monitored visually as a maintenance operation. Most of these manually initiated operations are performed by executing an instruction in the same manner as by automatic programming, except that the gating is performed by special pulses rather than by the normal c lock pulses. In automatic operation, instructions stored in core memory are loaded into the MB and executed during two or more computer cycles. Each instruction determines the major control states that must be entered for its execution. Each control state lasts for one 6-microsecond computer cycle and is divided into six 1-microsecond time states which can be used to perform logical operations. Performance of any function of the computer is controlled by gating of a specific instruction during a specific major control state and a specific time state. Instructions Th.e three most significant bits of words brought from core memory which are to be used as instructions are loaded into the IR. The IR decodes the first three bits as the operation code to generate the eight instruction signals. Instructions that store or retrieve data from core mem- ory are called memory reference instructions and are designated by operation codes 0 through 1-6 5. Instructions that do not reference core memory can be microprogrammed to cause a variety of operations to be performed as a function of binary ones in the remaining nine bits of the instruction. In a sense, these instructions use bits 3 through 11 to augment (or as an extension of) the operation code. Augmented instructions with an operation code of 6 perform input/output transfer (lOT) operations, and instructions with an operation code of 7 perform local data handl ing and control operations (aPR). Microprogramming of the lOT instruction allows combining of several bits to perform multiple operations within the limit of the capabilities of the peripheral equipment selected. ' Microprogramm ing of the operate instruction allows bit combinations and multifunction operations to be performed in two groups, as determined by the contents of bit 3 of the instruction. The format of all instruction classes is indicated in Figure 1-3. , I 0 I OPERATION CODE 6 MEMORY PAGE ,...--A--, OPERATION CODES 0-5 , I I I I I I I I 2 5 4 3 GENERATES AN IOP4 PULSE AT T6 TIME IF A 4 6 7 8 10 9 GENERATES AN 10PI PULSE AT T4 TIME IF A I ~ .-A-, III '--y---' ADDRESS INDIRECT ADDRESSING DEVICE SELECTION (A) MEMORY REFERENCE INSTRUCTION FORMAT OPERATION CODE 7 0 CLA CMA ~ III I I I 2 3 L--y----I CONTAINS JI 0 TO SPECIFY GflOUP I 4 5 ~' CLL 6 (B) lOT INSTRUCTION FORMAT ROTATE I ROTATE POSITION IF AO, AC AND L 2 POSITIONS IF A 4 RIGHT ~ ~ I I I 7 8 10 1 L-..,--J ~ CML ROTATE AC AND L LEFT . II I 0 CLA ,...--A--, III I I I 3 2 ~ '---y--I lAC CONTAI NS AI TO SPECIFY GROUP 2 (C) OPERATE t MICROINSTRUCTION FORMAT Figure 1-3 REVERSE SKIP SENSING OF BITS OPERATION CODE 7 ~ 9 GENERATES AN IOP2 PULSE AT T5 TIME IF AI 4 SZA 5,6,7 HIT ~ r-"---. r-"---. 5 '--y---J SMA 6 I I 7 ~ SNL 8 9 1 10 III L-..,--J L-y-J OSR NOT USED (D) OPERATE 2 MICROINSTRUCTION FORMAT Instruction Formats A memory reference instruction specifies a 12-bit core memory address for the operand in one of the following four ways: a. When bits 3 and 4 of the instruction contain zeros, bits 0 through 4 of the address are zeros and bits 5 through 11 of the address are taken from the corresponding bits of the instruction. 1-7 b. When bit 3 contains a 0 and bit 4 contains a 1, bits 0 through 4 of the address are the same as the address of the current instruction and bits 5 through 11 are taken from correspond ing bits of the i nstruc tion. c. When bit 3 contains a 1 and bit 4 contains a 0, the address of the operand is taken from the content of the core memory register whose address contains zeros in bits 0 through 4 and corresponds to the content of the instruction for bi ts 5 through 11 . d. When both bits 3 and 4 contain ones, the address of the operand is taken from the content of the core memory register at an address corresponding to the address of the current instruction for bits 0 through 4 and corresponding to the content of the current instruction for bits 5 through 11 . The memory reference instructions are as follows: AN D (operation code 0) - The logica I AN D. Th is operation is performed between the content of the specified core memory register and the content of the accumulator. The result of this combination is left in the accumulator; the original content of the accumulator is lost, and the content of the addressed core memory register is restored. TAD (operation code 1) - Twos complement add. The content of the spec ified core memory address is added to the content of the accumulator in 2 1 s complement arithmetic. The result is left in the accumulator, the original content of the accumulator is lost, and the content of the addressed core memory register is restored. If there is a carry from AC O during this opera- tion, the Iink is complemented. ISZ (operation code 2) - Index and skip if zero. The content of the spec ified core memory 1 register is incremented by one in 2 s complement arithmetic and then restored. If the result of this incrementing is zero, the program counter is incremented an additional time so that the succeeding instruction is skipped. DCA (operation code 3) - Deposit and clear accumulator. The content of the AC is deposited in the core memory location spec ified, and the content of the accumu lator is cleared. The previous content of the spec ified core memory register is lost. 1-8 JMS (operation code 4) - Jump to subroutine. The content of the program counter is incremented by one and depositied at the specified core memory location. The next instruction is taken from tlhe content of the spec ified core memory address +1 . JMP (operation code 5) - Jump. The core memory address spec ified in the instruction is set in- to the progrclm counter so that the next instruction is taken from th is spec ified core memory address. The ori gina I content of the program counter is lost. An augmentE~d instruction having an operation code of 6 is designated an input/output transfer (lOT) instruc:tion and uses bits 3 through 8 to signify a select code for a spec ific I/O device or register, enclbling it to produce lOT pulses during computer time states T4, T5, and T6 as a result of binc:lry ones in bits 11, 10, and 9 respectively of the instruction. These lOT pulses initiate operation of logic elements within the peripheral equipment and/or execute data transfers to or from the processor. Augmented instructions having an operation code of 7 spec ify the operate (OPR) instruction. When bit 3 of an OPR instruction contains a 0, a group 1 (OPR1) microinstruction is indicated; and when bilt 3 contains a 1, a group 2 (OPR2) microinstruction is indicated. Group 1 micro- instructions (:Ire used primari Iy for clearing, complementing, rotating, a nd incrementing operations, and l~roup 2 microinstructions are used principally in test and skip operations. Any log- ical combincltion of bits within one group can be combined into one microinstruction. Naturally, bits which cc]use diverse functions cannot be programmed simultaneously. Major States Two or more states are entered during each instruction. Assuming that the core memory address of the next instruction to be performed is conta ined in the MA, each instruction can be considered as beginning in the fetch state. The fetch state draws an instruction from core memory and begins executing it. At the conclusion of a fetch state other states are entered as a function of the current instruction. If no other states need be entered, the program count state is entered to load the content of the program counter into the MB, to modify the program count suitably, then to load the program count into the MA and the PC. At the conclusion of a program count state the fetch state is a Iways entered. The operations performed in each of the major states lore as follows: 1-9 Fetch (F) - During this state, instructions are brought from core memory and their operation code is transferred into the IR. The JMP, lOT, and aPR instructions are completely executed during the F state. Execute 1 (E1) - The content of a core memory address spec ified by a memory reference instruction is loaded into the MB, and the instruction is executed during this state. Execute 2 (E2) - This state is_ entered during a JMS instruction to write the progrom count into the core memory address specified by the instruction. Defer (D) - The effective address of an indirectly addressed instruction is brought from core memory into the MB during this state. Break (B) - This state is entered in response to a break request signal received from peripheral equipment and is used to execute data transfers directly between the MB and the device. Successive break cycles can be entered for multiple-word transfers. When the transfer has been completed, the norma I program sequence is resumed. Program Count (P) - This state is responsible for retrieving the program count from the PC at core memory address 0000 and modifying it according to the current instruction. Modification of the program count involves incrementing by one for non-branching instructions, incrementing by two for satisfied skip instructions, and changing the address for JMP or JMS instructions. Time States Six 1-microsecond time states designated T1 through T6 occur during each computer cycle (or major state). Major states are changed at the beginning of time state T6 of each cycle so that logical operations in the new major state can commence with time pulses produced during time state T1. Time pu Ises, designated TP, occur at the start of each time state except T2. These time pulses initiate gating circuits to perform sequential or synchronized logical operations. Core memory is automatica lIy cyc led during each computer cyc Ie so that reading occurs during time states T2 and T3, and writing occurs during time states T5 and T6. 1-10 PHYS ICAl DESCRIPTION The standard PDP-5 is contained in a single DEC computer cabinet 60-1/8 inches high, 47 inches wide', and 27-1/16 inches deep. A table 30 inches wide and 18 inches deep is attached to the front of the cabinet, just below the operator console. The operator console contains all keys, switches, and indicators used in normal operation of the computer. When sufficient optional equipment is used with the standard PDP-5, additional cabinets are bolted to the main cabinet. In such cases, the table extends the width of two or more cabinets. A cabinet is constructed of a welded steel frame covered with sheet steel. Double rear doors are held cl()sed by magnetic latches. A full-width plenum door provides mounting for the power control and power suppl ies inside the double doors. Controls and indicators used in maintenance activities are located on components mounted on the plenum door. The plenum door is latched by a spring·-Ioaded pin at the top. Double doors at the front of the cabinet conceal module mounting pClnels above and below the operator console. These mounting panels are positioned with in the cabinets so that the connector block wiring is accessibl e by open ing the front doors, and the modules are accessible from the back of the equipment. A fan mounted in the bottom of each cabinet draws cooling air through a dust filter, passes it over the electronic components, and exhausf"s it through louvered panels and other openings in the cabinet. Four casters allow mobil ity of each cabinet. A coordinc:ite system is used to locate cabinets, module mounting panels, modules and signal cable connectors and terminals within a PDP-5 system. The cabinet containing the operator console is odways designated cabinet 1 , and additional cabinets may be numbered from left to ri ght or right to Ieft, depending upon the configuration. Each 5-1/4 inch posi tion on the front of a cabinet is assigned a capital letter, beginning with A at the top. Figure 1-4 indicates the location of components within the standard PDP-5. Modules are numbered from 1 through 25 from left to right in a mounting panel, as viewed from the wiring side. Connectors on the connector paned (1 J) are numbered from 1 through 6, from right to left as viewed from the back of the machine. Blank module and connector locations are numbered. Terminals on a module con- nector are designated by capital Ietters from top to bottom. The letters G, I, 0, and Q are omitted from module and terminal designations. Therefore, 1C06J is in cabinet 1 (1), the third component location from the top (C), the sixth module from the left (06), and the ninth terminal from the top of the modul e (J). Components mounted on the pi enum door are not identi fi ed by location. 1-11 LOGIC lA TWO STEP POWER CONTROL TYPE 832 LO'GIC 1B POWER SUPPLY TYPE 731 LOGIC 1C LOGIC 10 POWER SUPPLY TYPE 135 LOGIC IE LOGIC IF POWER SUPPLY TYPE 119 OPERATOR CONSOLE I BLANK CONNECTOR PANEL 1J BLANK BLANK FRONT VIEW REAR VIEW Figure 1-4 Component Locations The Teletype unit which is standard equipment with the PDP-5 can be used on either side of cabinet 1. This unit is approximately 33 inches high, 22-1/4 inches wide, and 18-1/2 inches deep and is described in detail in the Teletype technical manual. SPEC IF ICATION S Physical Cabinet Height: 69-1/8 inches Cabinet Width: 22-1/4 inches for a single-cabinet PDP-5 (30-inch table) 42 inches for a dual-cabinet PDP-5 Cabinet Depth: 45-1/16 inches 1-12 Cabinet Door Clearance: 14-7/8 inches at back Teltype Height: 33 inches to top of console 44-1/4 inches to top of copyholder Teletype Width: 22 - 1/4 inc h es Teletype Depth: 18-1/2 inches C(Jbinet Weight: 540 pounds for a standard PDP-5 890 pounds (average) for a dual-cabinet PDP-5 Teletype Weight: 40 pounds Electrical Power Requirements: 115 volts, 60 cycles, 1 phase, 7.5 amperes for standard PDP-5 (can be constructed for 220 vol ts or 50 cyc Ies upon spec ia I request) Power Dissipation: 780 watts Diigital Signal Levels: ground and - 3 vol ts Ambient Conditions Operating Temperature: 50 to 104°F (10 to 40°C) Operating Hum idity: o to 90% Storage Temperature: 32 to 104°F (O to 40°C) Storage Humidity: less than 90% HE~at 2370 BTU/hour Dissipation: relative humidity Functional ~sec Cycle Time: 6 Word Length: 12 bits C()re Memory Size: 1024 or 4096 words, expandable to 32,768 in fields of 4096 words. 1-13 Instruc tions: 8 basic instructions, 6 memory reference and 2 augmented. The augmented instructions are microprogrammed to produce more than 100 commands. Input/Ouput Capabi I ity: 64 different devices can be individually selected and addressed by 3 command pulses. SYMBOLS AND TERMINOLOGY Engineering drawing numbers for this equipment contain five pieces of information, separated by hyphens. Read from left to right these bits of information are a lettered code specifying the type of drawing, a lettered code specifying the size of the drawing, the type number of the equipment, the manufacturing series of the equipment, and the number of a drawing within a particular series. The drawing type codes are: a. BS, block schematic or logic diagram b. Cl, cable list c. FD, flow diagram d. Ml, module location diagram e. RS, replacement schematic f. UMl, utilization module list g. WD, wiring diagram In the succeeding sections of this manual, block schematic engineering drawings are specified only by the drawing number. A reference to engineering drawing 9 is interpreted as a reference to BS-E-5-0-9. Block schematic drawings for optional equ ipment and for all other type drawings are referenced by the complete identification number. Symbols used on engineering drawings to represent basic logic circuits are defined in Figure 1-5. 1-14 SYMBOL DEFINITION STANDARD DEC POSITIVE PULSE OR POSITIVE - GOING TRANSITION STANDARD DEC NEGATIVE PULSE OR NEGATIVE-GOING TRANSITION STANDARD DEC GROUND LEVEL SIGNAL STANDARD DEC NEGATIVE LEVEL SIGNAL (- 3 VOLTS) NON-DIGITAL SIGNAL LOAD RESISTER CLAMPED AT -3 VOLTS COLLECTOR BASE -9 OR [2Q PNP TRANSISTOR INVERTER EMITTER I3Zl NPN TRANSISTOR INVERTER ZERO ONE oumr:TU OUTPUT T SET-TOONE INPUT -= -= -= -= BISTABLE MULTIVIBRATOR CONSTRUCTED OF TWO CROSS-COUPLED INVERTERS CLEAR-TOZERO INPUT GATED SETTO-ONE --+_---. LOUTPUTS J ZERO ONE GATED CLEAR TO-ZERO INPUTS FLlP- FLOP CONSTRUCTED OF FIXED COMPONENTS WITHIN A SYSTEMS MODULE DIRECT CLEAR_--r;,a....,.--~...,...... TO-ZERO GATED CLEARTO-ZERO COMPLEMENT----' GATED SETTO-ONE ---------' DIODE GATE. GROUND - LEVEL NAND OR NEGATIVE - LEVEL NOR DIODE GATE. NEGATIVE - LEVEL NAND OR GROUND-LEVEL NOR DIODE ~ CAPACITOR PULSE INPUT PULSE OUTPUT CAPACITOR- DIODE GATE (POSITIVE OR NEGATIVE AS INDICATED BY INPUT SIGNALS) RESISTOR LEVEL INPUT CAPACITOR-DIODE GATE (NEGATIVE)WITH OUTPUT PULSE INVERTER Figure 1-5 Logic Symbols 1-15 Conventions and notation on engineering drawings and in text describing the PDP-5 are used as follows: v Programming notation for the inclusive OR function. Programming notation for the exclusive OR function. /\ Programming notation for the AND function. -, -/ Programming notation for an information transfer. + Design notation for the inclusive OR function and program notation for addition. Design notation for the AND function. Design notation for an information transfer accompl ished by a single signal (used wi thout parentheses). Design notation for a jam transfer of information accompl ished by gating both the 1 and 0 inputs of a storage device. () The content of a storage device. C(A) V C(B) =>(A) The content of register B is OR combined with the content of register A wi th the resul t stored in register A. 1-16 The contents of bits 0 through 5 of register A are jam transferred into the contents of bi ts 6 through 11 of reg ister B. Bit 2 of register A is in the state correspond ing to a binary 1, or contains a 1. A2( 1) Same as above. +1 ----. A The content of A is incremented by 1 . O---..A Register A is cleared or set to contain all zeros. Other terms used in this manual are defined as follows: se't - means to set a storage device to the state correspond ing to a binary 1 . clear - means to establish the state corresponding to a binary O. flelg - a flip-flop or signal that is sensed by the program to indicate a specific equipment condition or status. instruction - a computer word which causes a specific machine function and wh ich is identified by a distinct operation code. microinstruction - an instruction in which numerous different machine functiems can be programmed by the placement of ones and zeros in bits other thc)n in the operation code. Effectivel y the entire word is used as an operation code wh ich is decoded, not onl y by the instruction register, but by gating circuits within the machine. command - a signal that causes a specific operation to occur as the whole or partial execution of an instruction or microinstruction. 1-17 subroutine - a routine that can be called upon from any core memory address of the main program to provide a service to the main program or peripheral equipment, usually to perform operations that are repeated many times, and thus to simpl ify the main program. program interrupt - an interruption in the main program caused by transfer of program control to a subroutine, after storing the current program count. The interruption is initiated by peripheral equipment to cause a subroutine to be executed. Usually the subroutine is used to locate the equipment that caused the interrupt and to transfer information with it, or service it in some way. data break - a temporary halt or break in the main program used to transfer data with peripheral equipment under control of the peripheral equipment (not under direct computer program control). operand - a stored number to be mathematica Ily operated upon. address of the operand - the location of a core memory register currently conta ining the operand. absolute address - a 12-bit number used directly to specify any address in core memory. effective address - the address of the operand as spec ified in an instruction or by an absolute address. 1-18 SECTION 2 PROCESSOR The major arithmetic, logic, and control functions performed by the PDP-5 are accompl ished by logic circ:uit elements of the processor. All operations of the PDP-5 are performed by the processor except those directly concerning data storage and retrieval in core memory, and information transfers to or from peripheral equipment. In performing these operations the pro- cessor draws instructions from core memory and executes them by sequentially entering one of six major control states. Each control state lasts for the duration of one computer cycle in which there are six time states, each of which produces various logical operations depending upon the ma jor control state. Functional operation of the processor can be compared to a three dimensiona I matrix. As in the matrix an X, Y, and Z coordinate must be spec ified to locate a given point, so within the processor an instruction, major state, and timing pulse determine the specific logic function performed. A change in any of these three items changes the resultant logical operation. Therefore, assuming one instruction and one state, as many different operations may be executed as there are timing pulses employed. In general, states are entered as a function of the current instruction, except that the break state is initiated by a break request originating in peripheral equipment, ,and the program count state is entered to locate the next instruction when no other state need be entered. Execution of each of the eight instructions requires two or more states to be entered. Each state lasts for 6 microseconds and so has five timing pulses available for initiating sequential logical operations. POWER CLEAR GENERATOR (5) During the power turn on sequence, the power c lear generator produces repeated Power Clear pulses at a 500 kc rate. These pulses clear the run and I/O-hit flip-flops to assure that transients within the machine do not start computer operation. These pulses are also supplied to terminals 1JOl-49 and 1J03-47 of the interface connectors and to the line unit out (LUO) buffer of the Teletype control to assure that registers of I/O devices are cleared or are in some preset state prior to programmed operation. The logic circuits for this functional element are shown on the upper left side of engineering drawing 5. 2-1 In the power turn on sequence, the 735 Power Supply, which produces the memory currents, is energized through the delayed closure/fast release contact K2 of the 832 Power Control. The time delay of K2 is between 3 and 5 seconds, so for this period of the turn on sequence the - 35 volt output of the 735 supply is essentially at ground potential. The ground potential is supplied through the centertap of the power transformer and diode D4 of the rectifier in the 735 Power Supply. This potential from terminal E of the 735 Power Supply is isolated by two series-connected inverters of the 4102 module at location 1E04 and is used to enable or disable the 4401 Clock module at location lE05. The initial ground potential is isolated from the clock module by an external diode connected to terminal V, so the clock is uninhibited and generates the standard DEC negative pulses designated the Power Clear pulses. After the initial delay the - 35 volt power supply output causes a - 3 volt level to be suppl ied to terminal V of the clock from the clamped load resistor of the last inverter. This level inhibits operation of the clock and prevents generation of Power Clear pulses during full computer excitation. SPECIAL PULSE GENERATOR (5) Operation of the keys and switches causes the computer to perform functions similar to those performed automatically during execution of instructions. These operations require sequenced timing pulses which are provided by the special pulse generator. The special pulse generator is shown on the upper left portion of engineering drawing 5. Initiation of the special pulse generator occurs at the positive-going leading edge of the Key Manual signal. This signal is produced when any of the manual keys, except the STOP key, are operated. The Key Manual signal is inverted to produce the negative shift required to initiate operation of the 4410 Pulse Generator module at location 1E06. The output of this pulse generator is a l-microsecond negative pulse, designated the SPO pulse, which is distributed to the run control element to clear the run fl ip-flop, to terminal 46 of interface connector 1 J03, and to the pulse input of the 4301 Delay module at location 1E07. The delay module produces a 10-microsecond delay between generation of the SPO pulse, which is generally used to clear registers and control devices in peripheral equipment using the data break facility, and generation of the SPl through SP3 pulses, which strobe registers or transfer information. The standard DEC negative pulse output of the delay module initiates operation of the first pulse amplifier circuit on the 4604 module at location lE08. Each of the three pulse amplifier circuits on this 2-2 module produces a 1-microsecond negative pulse which is designated by an appropriate SP number. The series connection of these pu Ise ampl ifiers causes turn off of SP1 to in itiate generation of SP2, and the turn off of SP2 to initiate generation of SP3. When SP3 expires, the special pulse generator has completed its operation and awaits another Key Manual signal, since this circuit is not regenerative. TIMING SIGNAL GENERATOR (17) The basic timing cycle of the PDP-5 is determined by the 1406 Crystal Clock module at location 1C25. The standard DEC 70-nanosecond negative pulse output of this 1-megacycle crystal c lock is converted to 400-nanosecond DEC standard negative pulses, required to operate the 4000 series system modules of the computer, by the 4604 Pulse Amplifier module at location 1C24. The negative pulse output from this pulse amplifier is supplied to terminal 45 of interface connector 1J01 and provides the trigger pulse input to the 4127 Pulse Inverter module at location 1C:21 which drives the 4215 Four-Bit Counter module at location 1C22. All timing pu Ises used in automatic operation of the computer are derived from the state of these fl ipflops and are shown in the timing diagram of Figure 2-1. The pulse inverter circuit which drives the least significant bit (TG ) of the counter is controlled by the 4115 Positive Diode 3 NOR module at location 1 D1 0 which functions as a ground-level NOR to enable the pulse inverter, and serves as a negative NAND gate to inhibit operation of the counter. Therefore, if any of the fl ip-flops in this 4-bit ring counter are in the 1 state except TG3, or if the run fl ip-flop is in the 1 status, a ground potential is appl ied to one of the signal inputs to this gate, and the counter is enabled and allowed to advance upon receipt of each output pulse of the crystal clock. Conversely, the counter will run until all inputs to this gate are negative; this occurs in time state T 1 when the run fl ip-flop is in the 0 state. The state and/or transition of the 4-bit counter initiates operation of the 4604 and 4606 Pulse Amplifier modules at locations 1C24 and 1C23 to produce the TP pulses used throughout the logic circuits to initiate clockbased sequence operations. When the computer is energized initially, the counter commences in time state T1, and so no TP1 pulse is generated as a function of the counter. A TP1 pulse is generated under either of the following conditions: 2-3 T1 T2 T3 T4, T5 T6 Tl T3 T4 T5 T6 T1 I I MEMORY WHITE (ICI9R) I MEMORY INHIBIT (ICI9T) T2 I I -JI1 ..- 200nsec MEMORY STROBE (IA01J) I --...a I MEMORY READ (1CI9V) I I ...--600nsec I I TP 6 (1C 23P) TP5 (1C24J) TP4 (1C24S) TP 3 (1C23H) TP1 (IC23W) TGb (IC 22 Z) L TG~(1C22U) TG~(IC22P) TG~ (1C22J) ~UN' (1D01T) 1 MC CLOCK (1 C 24V) Figure 2-1 Timing Diagram 2-4 a. During SPlafter operation of the CONTINUE key. b. When TG 1 changes from the 1 to the 0 state and either the EXAMINE or DEPOSIT key is operated, or the run fl ip-flop is in the 1 state, or the I/O-hit flip-flop is in the 1 state. This gating is effected by the negative NAND circuit of the 4113 module at location lCll and the ground-level NOR gate of the 4115 module at location 1 Dl0 which provide enabling levels to the pulse amplifier circuit producing the TPl pulse. Therefore, the TPl pulse is produced for each machine cycle except the first cycle of operation initiated by the START key, and during time state Tl immediately following receipt of an I/O Halt signal. Timing pulses TP4 and TP5 are suppl ied to terminals 39 and 40 of the data break interface connector 1J03 for use in input-output equipment as well as for use in the processor. The timing pulses which control cyc Iic memory functions are generated by transistor gating circuits which combine the conditions of various flip-flops in the 4-bit counter directly and through delay lines. Since the TP pulses which produce operations in the processor and the memory coni-rol signals are derived from the same tim ing source (the l-megacyc Ie crystal clock), the processor and the core memory are synchronized. During each computer cycle, core memory is in the read status during time states T2 and T3 due to the presence of the Memory Read signal derived from the binary 1 state of flip-flop TG and is in the write state during time 2 states T5 and T6 due to generation of the Memory Write signal derived from the binary 1 status of flip-flop TG • The Memory Strobe pulse, which allows the sense amplifiers to sample inforO mation induced on the sense windings during the read operation, is a DEC standard negative pulse produced by a circuit of the 1607 Pulse Ampl ifier module of 1A01. Operation of this pulse amplifier is initiated 600 nanoseconds after the start of the Memory Read signal, except under the co,nditions specified by the signal supplied to the 4-input negative NOR diode gate of the 4115 module at location lC18. This gate inhibits generation of the Memory Strobe pulse during the program count state of a JMP or JMS instruction, during the execute 1 state of a DCA instrucHon, during the execute 2 state of a JMS instruction, or during a data break in which the direction of data transfer is into the PDP-5. To assure that data bits containing zeros are inhibited during writing, the Memory Inhibit signal is generated beginning 200 nanoseconds after the end of the Memory Read signal and ending with expiration of the Memory Write signal. The Memory Inhibit signal is generated as a function of the binary 1 state of flip-flop TG by 1 2-5 the 2-transistor NOR circuit composed of inverter ST of the module at location 1C19 and inverter UVW of the module at location 1A01. The 1311 Delay Line module at location 1C20, whose output line is normally held at -3 volts by clamped load resistor F of the module at 1 D07, and the inverter ST inhibit generation of the Memory Inhibit signal during the first 200 nanoseconds of the 1 state of TG . The inverter UWI assures turn off of the Memory 1 Inhibit signal as soon as TG reverts to the state. 1 ° OPERATOR CONSOLE (WD-D-5-0-10) The operator console provides a means of manually controlling the operation of the computer, manually inserting data into fl ip-flop and core memory registers, and provides visual indication of the contents of the most important registers and control fl ip-flops. Wiring connections to the keys and switches on the operator console are shown on en9ineering drawing WD-D-5-0-1 0, and the logic signal level gating of the signals produced by the keys and switches is indicated on engineering drawing BS-D-5-0-5. Indicator lamps and drivers are shown on the appropriate replacement schematic drawings; connections to these drivers are indicated on cable lists CL-A-5-0-20 and 21, and the isolating resistors and connections between fl ip-flops or registers and the input to the indicator drivers are shown on the appropriate block schematic engineering drawings for the registers or control fl ip-flops. Interlock and POWER Switches One deck of the interlock switch is connected in parallel with the POWER switch so that if either of these switc hes is closed, a short c ircu it is provided between term ina Is 2 and 4 of the 832 Power Control. This short circuit supplies primary power to the coils of the time-delay relays which control the application of primary power to the power supplies. The POWER indicator is connected directly between ground and the -15 volt output of one of the power suppl ies and therefore Iights to indicate the presence of secondary power. A second deck of the interlock switch supplies either ground or -15 volts to the circuits of the keys and switches on the operator console. When this switch is in the locked position, ground potential is suppl ied to these circuits to disable them. When the switch is unlocked, -15 volts 2-6 enables the switch circuits. Therefore, in the locked position the interlock switch prevents power turn off by means of the POWER switch and disables all of the keys and switches on the operator console except the SWITCH REGISTER toggle switches. Key Circuit~ When the computer is energized and the interlock switch is in the unlocked position, operating any of the keys or setting either the SINGLE STEP or SINGLE INST switch to the right position supplies -15 volts to an appropriate terminal of connector 1H04. Negative 15-volt signals supplied to this connector are combined in transistor and diode gating circuits shown in the lower left portion of engineering drawing 5. These diode-transistor gating circuits produce the Key Manual signal (which initiates operation of the special pulse generator) and produce other conditionin~~ signal levels (which enable appropriate gates which are triggered by SP pulses during manual operations). Indicator Clircuits Indicators on the operator console are 28-volt incandescent lamps driven by 4903 Light Bracket Assemblies or 4904 Short Light Bracket Assemblies. These assemblies contain a number of series circuits consisting of a transistor switch connected between an indicator and ground potential. One side of each of the indicators is connected in common to -15 vdc. Ground potential is connected in common to the emitter of each transistor switch through parallel-connected diodes which provide the appropriate emitter-base junction bias. Each transistor switch is turned on by a negative signal level applied to the base through a 3000-ohm resistor connected to the output of a fl ip-flop. When the output of a fl ip-flop is at ground potential, the transistor switch is cut off, and the circuit to the indicator lamp is incomplete. When the output of the flip-flop is at -3 volts, the transistor switch is closed to energize the indicator with approximately 14 volts. SWITCH REGISTER Toggle Switch Circuits The 12 toggle switches wh ich comprise the switch register (SR) supply enabl ing or disabl ing signal levels to the level input of positive capacitor-diode gates of the input mixer to allow the condition of the switches to be sensed automatically by the OSR instruction. A switch set 2-7 to the up position corresponds to a binary 1, and supplies a ground-potential enabling signal level to a capacitor-diode gate of the appropriate bit of the input mixer through a 1k resistor and a terminal of connector 1H04. A switch in the down position corresponds to a binary 0, and supplies a -15 volt signal to disable an input mixer capacitor-diode gate through the same path. Connections to the input mixer from the SR are indicated on engineering drawing 14. RUN ANn I/O HALT CONTROL (5) Contro'l of the circuits which produce the timing signals of the PDP-5, and hence which control automatic operation of the computer, is exercised by the run and I/O-hit flip-flops. These flip-flops and their associated input gating circuits are shown on the right side of engineering drawing 5. The run flip-flop enables the timing circuits to generate timing signals when in the 1 state. The 1 output from th is fl ip-flop is a Iso suppl ied to term ina I 42 of the data break interface connector 1 J03 (via a bus driver circuit shown on engineering drawing 31). The I/O-hit flip-flop provides a means of setting and clearing the run flip-flop by means of signals suppl ied by an I/O device. The run flip-flop is cleared by a positive pulse that grounds terminal U of the 4215 module at location 1001 under one of the following conditions: a. During the power turn off and turn on sequence by the Power Clear pulses. b. By an SPO pulse following operation of either the START, LOAD ADDRESS, EXAMINE, DEPOSIT, or CONTINUE key. c. By a TP6 pulse to cone lude operations when the STOP key is pressed or to conclude an operation when the SINGLE STEP or SINGLE INST switches are in the on (right) position. d. By a TP5 pulse during an operate 2 instruction in which bit lOis a 1 to prov i de a programmed ha It. e. By the positive transistion of the signal at terminal 1001 N when the I/O-hit flip-flop changes from the 0 to the 1 state. 2-8 The run flip-flop is set by a positive pulse that grounds terminal T under one of the following conditions: a" By an SP3 pulse after operation of either the CONTINUE, START, EXAMI NE, or DEPOSIT key. b" Upon receipt of a Restart pulse from an I/O device when the I/O-hit flip-flop is in the 1 state. The I/O-hit flip-flop is cleared by a positive pulse that grounds terminal P by Power Clear pulses, by an SPO pulse, or by a Restart signal in the same manner as these pulses clear the run flip-flop. The I/O-hit flip-flop is set by a positive pulse that grounds terminal N when a standard DEC negative pulse is suppl ied to terminal 1 S12U during T6 of an ADC miscroinstruction for the Type 37 Analog-to-Digital Converter, or by receipt of a similar negative 1/0Halt signal received at terminal 46 of interface connector 1J01 . PROGRAM COUNTER Address 0000 in core memory is used as the program counter (PC) and contains the core memory address from which the last instruction was taken. During a program count (P) state, the con- tents of the PC is read into the memory buffer register, is incremented, and is written back into the PC. The contents of the memory buffer register is then transferred into the memory address register as i-he address of the current instruction. Use of a core memory register for the PC a IIows the program sequence to be man ipu lated by the program in the same manner as the contents of any core memory location. INSTRUCTION REGISTER (6) The instruct'ion register (lR) consists of a 4-bit fl ip-flop register that determines the instruction currently being performed, based on the 3-bit operation code, and controls entry into the defer state during memory reference instructions. This register consists of a 4215 4-B it Counter module at locat'ion 1 D22 with the associated input gating circuits and output decoding circuits indicated on the right side of engineering drawing 6. 2-9 The IR is cleared by the positive pulse output at terminal lC01X of a gated pulse amplifier on a Type 4606 module. The IR is cleared by one of the following: a. During manual operation by the SPl pulse following operation of either the START, EXAMINE, or DEPOSIT key. Clearing by the SPl pulse allows the register to be set by the SP2 pulse to a specific operation code appropriate to the key which is operated. The gate pulse that initiates clearing the IR under these conditions is routed to the program interrupt synchronization logic as the 0 ---..... Int Ack signal. b. By a TP5 pulse in either the program count or break state. During the program count state, the IR is cleared in preparation for receiving the new operation code during time state T3 of the following fetch state. During the break state, the IR is cleared to dispose of the instruction preceding the break in case the break lasts for longer than one cycle. If the instruction in progress at the time of the break request is a rotate or increment accumulator microinstruction, these operations are completed during Tl of the break cycle. Therefore, the IR is cleared at T5 of the first break cycle so that these operations are not repeated in successive break cyc les. The IR is set by supplying a standard DEC positive pulse to ground the flip-flop output terminal which is normally at ground level when the flip-flop is in the 1 state. During manual operation, bits 0 through 3 of the IR are set by an SP2 pulse to force an instruction determined by the key which is operated. (START sets bits 0 and 2 to force a JMPi DEPOSIT sets bits 1 and 2 to force a DCA instruction, or EXECUTE sets bit 2 to force a TAD instruction.) Thjs gating is produced in the 4127 Pulse Inverter module at location 1 D23. During a program interrupt, when the Interrupt Acknowledge signal level is present, bit 0 of the IR is set during T3 of the fetch state to force a JMS instruction. Fore ing the JMS instruction causes the fetch state to be followed by the execute 1 state, the execute 2 state, and the program count state. These states are entered to store the contents of the program counter in core memory location 0001 and to transfer program control to address 0002. In normal opera- tion, when no interrupt request is present, all four bits of the IR are set to correspond with the contents of memory buffer register bits 0 through 3 during time state T3 of the fetch cycle. 2-10 Th is operatiion corresponds to sensing the operation code and indirect address bit, and instigates execution of a new instruction. The gating which performs setting of the IR in this manner consists of t"he 4127 Pulse Inverter module at location 1 D24 and the 4112 Negative Diode NOR module at location 1 D16. In this application the 4112 module circuits function as ground-level NAND gates. The outputs from bits 0 through 2 of the IR are supplied to indicators on the operator console and to a 1151 Binary-to-Octal Decoder module at location 1 D21. Decoding of the content of the IR produces the eight instruction control signals used in the PDP-5. MAJOR STATE GENERATOR (6) The six complementary pairs of control signals which indicate the state, or mode, in which the computer is operating are produced by the logic element shown on the left side of engineering drawing 6. These signals, combined with the instruction in progress and timing pulses, perform most of the gating which performs the logical operations of the computer. The operations performed by the computer in each state are described in detail in Section 5 of this manual. The major state generator consists of a 6-state device composed of six 5-input ground-level NOR gates composed of the 4117 modules at locations 1 D18 and 1 D19. The output from each of these gat"es is the normal state signal which is at ground potential during the indicated state; program count (P), fetch (F), execute 1 (E1), execute 2 (E2), defer (D), and break (B). Each of these signals is inverted by a circuit of the 4102 module at location 1D20 to provide a complementary signal for each of the control states. The inverted state signals are distributed with the normal state signals throughout the processor and are suppl ied to circuits which drive the indicators on the operator console. The inverted break signal is also supplied to terminal 41 of the data break interface connector 1 J03 via the output bus drivers shown on engineering drawing 31" The output of each NOR gate is also supplied to one input of each of the other NOR gates" This arrangement prevents any state signal from being generated during any of the other states. A state is set by grounding the output terminal of the N OR gate with a positive pulse from a 4127 Pulse Inverter module at location 1 D17 or 1 D23. Forcing the output of a NOR gate to ground potential by the positive output of a pulse inverter disables all other state NOR circuits and so enables the input to the gate whose output is pulsed. 2-11 The pulse inverters which set the states are enabled by diode gating circuits as a function of the current state, the current instruction, the content of bit 3 of the instruction, and/or the condition of the Break Request signal supplied externally and are a" initiated by the TP6 pulse. Pulse ampl ifiers of the module at location 1 D23 set the P state during SP2 when the START key is operated or set the E1 state during SP2 when either the EXAMI NE or DEPOSIT key is pressed. Setting of a state is normally triggered by a TP6 pulse so that operations within that state can commence, or be initiated, by a TP1 pulse. The gating c ircits which enable entry into each state respond to the following conditions: a. The program count state can be entered from any other state and is normally entered when the conditions present do not allow entry into any other state. Entry into the P state is enabled by the 4116 module at location 1 D12 which functions as a negative NOR circuit to inhibit setting P if any other state can be entered. When cond itions are not present to set the execute state, defer state, or break state, and the current state is not the P state, all of the inputs to this NOR gate are at ground potential. Therefore, entry into the P state is not inhibited, so the negative P Set signal level is produced to enable the pulse inverter. b. The fetch state is entered following each P state and can not be entered from any other state. Therefore, the inverted P signal alone supplies the direct enable signal to the pulse amplifier to set the F state. c. The defer state is entered only at the conclusion of the fetch state when bit 3 of the instruction is a 1 (indicating indirect addressing or deferring) and the current instruction is a memory reference instruction (which is not an lOT or an operate instruction). d. The execute 1 state is entered from either the fetch or defer states for all instructions requiring more than two cycles. These instructions are JMS and the instructions having an operation code of less than four (AND, TAD, ISZ, and DCA). Therefore, the E1 state is entered from the defer state for 2-12 instructions requiring more than two cycles and is entered from the fetch state for instructions requiring more than two cycles which do not employ indirect addressing (bit 3 of the instruction is a 0). e. The execute 2 state is entered on Iy from the execute 1 state duri ng a JN~S key. instruction or following operation of either the EXAMINE or DEPOSIT Note that execution of a JMS instruction or pressing of either the EXAMINE or DEPOSIT key causes entry into the E1 state and thus enables entry into the E2 state for the following computer cycle. f. The break state is entered only from the fetch state at the conclusion of 2-cycle instructions or from the execute 1 state at the conclusion of instructions requiring more than two cycles. When a Break Request signal is present at terminal 43 of interface connector 1.103 at T4 time, this condition is stored in a flip-flop composed of inverter LK of the 4102 module at location 1D06 and negative NOR SRT of the 4112 module at location 1E03. This flip-flop is cleared by the TP3 pulse to synchronize operations of the computer with peripheral equipment during a data break by assuring that break requests made after T4 time are not honored unti I the next cyc Ie. The 1 status of this flip-flop, in which terminal 1 D06L is at ground potential, provides one of ,the conditioning signal inputs to the ground-level 2-input diode NAND gate which produces the B Set signal. The second input to the NAND gate which produces the B Set signal is present if the computer is currently in the break state (to allow multiple-cycle data break operation), or if the computer is in the execute 1 state but not performing a JMS instruction (indicating that the last cycle of instructions requiring more than two cycles is taking place), or if the computer is currently in i~he fetch state and is executing either an lOT or OPR instruction (indicating that the last cycle of a 2-cycle instruction is being executed). 2-13 MEMORY ADDRESS REGISTER CONTROL (7) All of the signa Is used to control the operation of the memory address register (MA) are produced by the control logic circuit shown on the left side of engineering drawing 7. This logic element consists of six pulse amplifiers which produce the standard DEC positive pulses that cause the clearing, shifting, and transfers of information within the MA and also consists of the diode gating circuits which control the initiation of these pulse amplifiers. Diode gating circuits and a flip-flop composed of two cross-coupled inverters are also contained in this logic element and produce the Disable MA signal, which forces the output terminals of the MA to simulate address 0000. Pulse ampl ifier circuits FJH KL and NRST of the 4606 module at location 1C15 produce pulses which clear the least significant seven bits of the memory address register and the five most significant bits of the memory address register respectively. Both pulse amplifiers are initiated simultaneously and thus clear the entire MA under either of the following conditions: a .. At SP1 time following operation of the LOAD ADDRESS key, thereby clearing the MA to a II ow a new address to be set into it from the switch register. b. By the TP1 pulse durlng the execute 1 state of program interrupt operations, so that the program count can be read and subsequently stored in address 0001 . The Clear MAO_4 pulse is also produced under eit~er of the following conditions: a. By the PT1 pulse during the execute 1 state of a memory reference instruction in which both the indirect bit and the memory page bit contain a 0, indicating that the effective address is to be taken from page 0 of core memory at the address specified by bits 5 through 11 of the instruction. b. By the TP1 pulse during the defer state for an instruction in which the memory page bit is a 0 (MB~), indicating that the effective address is to be taken from memory page 0 at the address current Iy spec i fi ed by bits 5 through 11 of the MA. 2-14 The MA Carry Enable signal is a DEC standard ground level that enables the capacitor-diode gate at the complement input of each flip-flop of the MA, thus allowing the MA to function as a binary counter. This signal is produced at terminal 1C11 H of the 4113 Diode module under any of the f()llowing conditions: a. When either the EXAMINE or DEPOSIT key is pressed, allowing the MA to be incremented and facilitating examination or depositing of information in core memory at sequential addresses without specifying each address. b. During the execute 2 state of a program interrupt operation to allow in- crementing of the MA to address 0001 for storing the program count. c. During the break state when the Increment Request signal is received at terminal 45 of interface connector 1 J03 to allow data break transfers to occur at sequential core memory addresses without spec ifying each address. The MA Carry Enable signal also is gated by the TP1 pulse to produce the Count MA signal at terminal 1C11 P. This positive pulse is supplied to the pulse input of the capacitor-diode gate at the complement input of fl ip-flop MAll' thus incrementing the content of the MA at T 1 time under any of the conditions specified for generation of the MA Carry Enable signal. The Data Address ~ MA signal is a standard DEC positive pulse produced at terminal lC16F of the 4102 Pulse Amplifier module. This pulse initiates operation of the capacitordiode gates at the input of the MA to provide a jam transfer (a transfer of both ones and zeros) into the MA of the address suppl ied to terminals 26 through 37 of interface connector 1J03 from an external device. This signal is also supplied to terminal 49 of interface connector 1J03 as the Address Accepted pulse. The signal is produced by a TPl pulse during the break state when j~he Increment Request signal is not present at terminal 1J03-45. The SR ---.... MA signal is produced at terminal lC16K. This standard DEC positive pulse is applied to a capacitor-diode gate at the 1 input of each MA flip-flop to provide a ones transfer from the content s of the switch register into the MA. Th is pulse is produced during SP2 following operation of the LOAD ADDRESS key (the MA having been cleared during SP1). 2-15 The MB ...:J--III... MA _ pulse is a standard DEC positive pulse produced at terminal 1C16N. 5 11 This pulse strobes the positive capac itor-diode gates at the input of each MA fl ip~flop to provide a jam transfer between the 7-bit address of an instruction into the MA. This pulse is produced by a TP1 pulse during the fetch state, or during the defer state, or during an execute 1 state wh ich is not caused by a program interrupt. The MB...:J--III... MAO_4 signal is a standard DEC positive pulse produced at terminal1C12F of a 4603 Pulse Amplifier module. This signal triggers the capacitor-diode gates at the input of MA fl ip-flops 0 through 4 to provide a jam transfer between the contents of corresponding bits of the memory buffer register and the memory address register. Th is signal is produced under either of the following conditions: a. By the TP1 pulse at the beginning of a fetch state to correspond with generation of the MB ...:J--III... MA _ pulse to transfer the entire word con5 11 tained in the MB into the MA. b. By a TP1 pulse at the beginning of an execute 1 state of an instruction in which the indirect address bit is a 1 (lR~). The Disable MA signal is a standard DEC positive signal level which forces the output terminals of the MA to simu late address 0000 without disturbing the contents of the register. Therefore this signal allows information to be read or written in the program counter. The signal is produced at terminal 1 D09Z, which is the buffered 1 output of the flip-flop composed of crossedcoupled inverters WX and YZ of the 4102 module at location 1 D06. This fl ip-flop is in the binary 1 state when terminal 1 D06X is at - 3 volts, thus producing a ground-potential Disable MA signal. The flip-flop is set by a positive pulse that grounds terminal 1 D06D under one of the following conditions: a. During 5P3 following operation of the 5T ART key. b. By a TPl pulse occurring at the start of a program count state. c. By a TPl pulse at the start of an execute 1 state for a JM5 instruction. 2-16 The fl ip-flop is cleared by a positive pulse that grounds terminal 1 D06X under either of the following conditions: a. During SP1 time following operation of the LOAD ADDRESS, EXAMINE, or DEPOSIT key. b. By a TP1 pulse at the start of all states that are not the program count state or which are not the execute 1 state of a JMS instruction. MEMORY BUFFER REGISTER CONTROL (7) The logic ciircuits which produce the signals that control the operation of the memory buffer register (MB) are shown on the right side of engineering drawing 7. This logic consists of transistor and diode gating circuits and six pulse ampl ifiers. The Clear MB signals for bits 5 through 11 and 0 through 4 are produced at terminals 1C15X and 1C14X, respectively. These standard DEC positive pulses are applied to the direct clear input terminals of the respective MB fl ip-flops. Since generation of the Clear MB _ pulse 5 11 initiates operation of the pulse amplifier to produce the Clear MBO_4 pulse, the entire MB is cleared under one of the following conditions: o. Upon receipt of a Restart 1 pulse from the Type 137 Analog-to-Digital Converter signifying that the program can continue. The converter leaves unwanted information in the MB during its programmed I/O halt operation, and so the MB is cleared before resumption of the main computer program. b. During SP1 following operation of either the START, EXAMINE, or DEPOSIT key to remove any extraneous number from the content of the MB at the start of a program or when a word is to be read from or written into core memory by means of the keys. c. By means of a TP1 pulse during the fetch, defer, execute 1, or break state of any instruction or during the program count state of either a JMP or JMS instruct ion. 2-17 The Clear MBO_4 signal is also produced by the TPl pulse at the beginning of a program count state of a JMP instruction directly to an address on memory page O. The AC -::J-~ MB signal is a DEC standard positive pulse produced at terminal lC12K during T3 of an execute 1 state of a DCA instruction. This pulse triggers capacitor-diode gates at the input of each MB flip-flop to transfer the content of the AC into the MB so that the word contained in the accumulator can be written in core memory. The Count MB signal is a standard DEC negative pulse produced at terminal 1 D09Z and supplied to a 2-input negative NAND gate which provides the pulse input to the capacitor-diode gate at the complement input of the MBll and MB fl ip-flops. The content of the MB is incre10 mented by one or by two to advance the program count as a function of the condition of the skip flip-flop. The Count MB signal triggers diode gate EFH of the 4113 module at location 1 D02 to complement MB11 and increment the content of the MB by one if the skip fl ip-flop contains a o. The Count MB signal triggers diode gate EFH of the 4113modu Ie at location 1013 to cQmplement MB and increment the content of the MB by two if the skip fl ip-flop 10 contains a 1. The Count MB signal pulse occurs 2 microseconds after the MB Carry Enable signal is produced so that the carry pulses produced by incrementing the MB can be propogated through the register. The content of the MB can also be incremented by o~e upon receipt of a positive pulse received from an external device at terminal 38 of data break interface connector 1 J03. The Count MB pulse is produced by a TP4 pulse under one of the following conditions: a. During the defer state when the address of the operand is between 0010 and 0017 {indicating an instruction using the auto-indexing core memory registers} . b. During tbe program count state of a II instructions except the JMP. The MB is not incremented during a JMP instruction because program control is transferred to an address specified in the instruction so that the sequential instruction:address sequence is broken. c. During the execute 1 state of an ISZ instruction to provide the incre- menting prior to sensing by the skip control element. 2-18 d. During the execute 2 state of a JMS instruction (not during a program interrupt) . The MB Carry Enable signal is produced at terminal 1C18Z of the 4115 Positive Diode NOR module. This DEC standard positive level signal enables the capacitor-diode gates at the complement input of each MB flip-flop to allow operation of the MB as a binary counter. This signal is produced from the start of time state T2 until the end of time state T4 during a" major states utilizing a memory strobe, in other words in a" states except execute 1 of a DCA instruction. The MA -:J--.III... MB signals are produced at terminals 1C14J and 1C14R for bits 0 through 4 and bits 5 thr()ugh 11 of the MB, respectively. These DEC positive pulses initiate operation of the positive capac itor-diode gates at both the 1 and 0 inputs of each MB fl ip-flop to effect a jam transfer from the memory address register into the memory buffer register. Both pulse amplifiers are initia'~ed to provide a 12-bit transfer between the MA and MB under the following conditions: CJ. During SP3 following operation of the START key, thereby setting an effective program starting address into the MB. b. By a TP1 time pulse during the program count state of a JMS instruction, clilowing the effective address to be set into the MB from the instruction address rather than from core memory. The MA -~ MBO_4 pulse is also produced by a TP1 pulse during the program count state of a JMP instruction in which bit 3 is a 0 and bit 4 is a 1. This transfer allows the five most significant bits of the instruction address to be saved during jump instructions within the current memory page. The Data --..... MB signal is a DEC standard positive pulse produced at terminal 1C12N. This pulse triggers the capacitor-diode gates at the 1 input of each MB flip-flop to transfer information into the MB from an external device supplying signals to terminals 13 through 24 of the data break interface connector 1J03. This pulse is also returned to terminal 48 of connector 1 J03 to indicate to the external device that data suppl ied to the computer has been received. 2-19 This pulse is produced by a TP3 pulse during the break state i.n which the direction of transfer is into the PDP-5 (core memory write request). The direction of this transfer is indicated by a - 3 volt signal suppl ied by the external device to terminal 43 of connector 1 J03 which is connected to terminal 1C17S of a 2-input negative NAND gate on the 4113 Diode module. ACCUMULATOR CONTROL (8) The logic circuits that produce the six positive and two negative DEC standard pulses which control the operation of the accumu lator (AC) are shown in the top left portion of engineering drawing 8. The circuits consist of 4606 Pulse Amplifier modules with appropriate diode and pulse inverter gating. The Clear AC signal is produced at 1C01 J under any of the following conditions: a. During SP2 following operation of either the DEPOSIT, EXAMINE, or START key. b. By the TP6 pulse during the fetch state of lOT microinstruction KCC (command 6032, clear AC and keyboard flag). c. Upon receipt of a standard DEC positive pulse at terminal 47 of inter- face connector 1J01 from an I/O device. d. By a TP6 pulse in the fetch state, of lOT microinstruction ADC (command 6004, convert analog signal to digital value on the Type 137 Analog-toDigital Converter). e. By a TP4 pulse during the fetch state of an operate 1 or operate 2 instruction in which bit 4 is a 1. These conditions designate a CLA microinstruction. f .By a TP3 pulse during the execute 1 state of a DCA microinstruction. The positive SR ---... AC signa'i initiates operation of the capac itor-diode gates in the input mixer to transfer the word contained in the switch register into the accumulator. Connection of this signal to the input mixer is shown on engineering drawing 14. This signal is produced 2-20 at SP3 time following operation of the DEPOSIT key or by a TP5 pulse during the fetch state of an OSR microinstruction (these conditions being determined by the presence of an operate 2 instruction having a binary 1 in bit 9). The Half Add signal is a positive pulse produced at lC02J. This pulse initiates operation of the capacitor-diode gate at the complement input of each AC flip-flop to perform an exclusive OR operation between the content of the memory buffer register and the content of the accumulator. This pulse is produced by a TP4 pulse during the execute 1 state of a TAD instruction. The second Ihalf of the TAD instruction takes place during time state T6 by means of the Carry Initiate pulse. The Carry Initiate signal is a negative pulse produced at terminal lC02W. This pulse is supplied to the pulse input of a negative capacitor-diode gate whose input is enabled when a memory buffer bit holds a binary 1 and the corresponding bit of the accumulator holds a o. The output of this capacitor-diode gate is inverted by a pulse inverter to provide a direct input to the next most si!~nificant bit of the accumulator (or link). The Carry Initiate pulse is produced by a TP6 pu Ise during the execute 1 state of the TAD instruction. The MBO - . AC signal is a positive pulse produced at 1C02R. This pulse triggers operation of a positive capacitor-diode gate at the clear input of each AC flip-flop. The capacitordiode gates are enabled when the corresponding bit of the MB contains a binary o. The MBO ~ AC signal is produced by a TP4 pulse during the execute 1 state of the AN D instruction. The Complement AC signal is a standard negative pulse produced at terminql lC03H. This pulse initiates operation of the pulse inverter that provides the direct complement input to each AC flip-flop. This signal is produced by a TP5 pulse during the fetch state of a CMA instruc- tion as designated by an operate 1 instruction signal and bit 6 of the instruction being a 1 • The Right Rotate and Left Rotate signals are produced at terminals R and X of the 4606 module at location 1C03. These signals provide the initiating pulse for capacitor-diode gates at both the 1 and 0 inputs of each AC fl ip-flop to provide a jam transfer of information into the AC from either the next most significant or next least significant bit of the accumulator (or link). The Right Rotate signal is produced under either of the following conditions: 2-21 a. By a TP5 pulse during the fetch state of the RAR microinstruction, as designated by an operate 1 instruction signal and a binary 1 in bit 8. b. Bya TPl pulse during Tl time of the cycle following the fetch state of the RTR microinstruction. These conditions provide the additional rotate command during a rotate two microinstruction and are designated by binary ones in bits 8 and 10 of an operate instruction designated as group 1 by the presence of a 0 in bit 3 of the IR. The Left Rotate signal is produced under conditions similar to those described for the Right Rotate signal except that bit 8 is replaced by bit 9. The Index AC signal is a positive pulse produced at terminal lC05L of a 4127 Pulse Inverter module. This signal provides a direct pulse input to the complement terminal of the AC 11 flip-flop. This signal is produced by a TP1 pulse during the cycle following the fetch state of an lAC microinstruction as determined by the presence of the operate instruction signal, the presence of a 0 in IR3 to designate operate group 1, and the presence of a binary 1 in bit 11 of the instruction to signify the lAC microinstruction. The AC Carry Enable signal is a complementary level produced by diode gating circuits. The primary purpose of this signal is to enable the capacitor-diode gate whose pulse inverted output complements each bit of the accumulator. This signal is produced under any of the following conditions: a. From time state T4 to time state T2 during the execute 1 state of a TAD instruction. This gating assures that the capacitor-diode gates are enabled for at least 1 microsecond prior to being strobed by the TP6 pulse. b. During time states T5 and T6 of the fetch state during execution of the lAC microinstruction. This gating assures that the capacitor-diode gates are enabled for at least 1 microsecond prior to being strobed by the TP1 pulse. c. During the program count or break state of a TAD instruction, and not during a rotate or lOT instruction, and not following the operation of either the EXAMINE or DEPOSIT key. This gating assures that the AC Carry Enable 2-22 signal is present during the cycle following execution of the TAD instruction (program count or break follow the execute 1) to allow the AC Carry pulse to ripple through the accumulator. This gating also inhibits generation of the AC Carry Enable signal during any rotate microinstruction (as determined by bit 10 of the instruction being a 0) to assure that carry pulses are not introduced into the accumulator during the second rotation, during any IC)T pulse to prevent any interference with the accumulator during the ADC microinstruction, and during manual operations involving the EXAMINE or DEPOSIT keys which must clear the accumulator. MEMORY ADDRESS REGISTER (9) The memory address register (MA) determines the core memory address currently selected for reading or writing. The register is shown at the top of both sheets of engineering drawing 9 to consist of 1 flip-flop and associated gating from each of the 12 4206 Triple Flip-Flop modules at locations 1B02 through 1 B13. Since the register contains 12 bits, it can directly address 4096 words of core memory. The register can be set or cleared by gated signals, can be complemented by gated signals, can be cleared directly, can be disabled, and the status of each flip-flop in the register is visually denoted by an indicator on the operator console. All gating inputs are accomplished through positive capacitor-diode gates which require 1-microsecond setup time. The gating circuits allow the MA flip-flops tobe set to correspond with binary ones inthe switch register whe!n the SR ~ MA signal is produced, allow the content of corresponding bits of the memory buffer register to be jam transferred into the MA by means of an MB ~ MA signal, and allow signals supplied to terminals 26 through 37 of interface connector 1J03 to be jam transferred into the MA by a Data Address ~ MA signal. The MA can operate as a binary counter when the MA Carry Enable signal is present at the capac itor-diode gate connected to the complement input of each flip-flop, thus allowing each flip-flop to be complemented on the positive shift produced as the next least significant flip-flop changes from the 1 to the 0 state. The input to the complement capacitor-diode gate of the least significant bit is provided by the Count MA signal. The Clear MA signal is supplied in parallel to the direct clear input of each flip-flop bit. The MA can be disabled (forced to indicate that all 2-23 fl ip-flops are in the 0 status without affecting the contents of the register) by the standard DEC ground-level Disable MA signal. The MA is disabled to select address 0000 when reading or writing the program count. MEMORY BUFFER REGISTER (9) The memory buffer register (MB) serves as a data buffer between the fl ip-flop logic of the processor and core memory. The MB consists of 1 flip-flop and associated gating from each of the 12 4206 Triple FI ip-Flop modules at locations 1B02 through 1 B13, and is shown in the center of both sheets of engineering drawing 9. Circuit operation of the MB is identical to that of the MA except that the MB cannot be disabled, is provided with an additional set of capac itor-diode gates for jam transfer inputs, and is provided with a direct set-to-l input from the sense amplifiers. Each flip-flop of the MB is cleared by the Clear MB signal supplied to the direct input and is set by a positive pulse supplied to the gated set-to-l input from the corresponding bit of the sense ampl ifier when data is being read from core memory. The gating circuits allow the MB fl ip-flops to be set to correspond with binary 1 signals suppl ied to terminals 13 through 24 of data break interface connector 1 J03, the transfer being initiated by the presence of the Data ---.. MB signal. Jam transfers into MB flip-flops are accomplished by capacitor-diode gates enabled from corresponding bits of the accumulator and initiated by the AC -:J--.III... MB signal or enabled from corresponding bits of the memory address register and initiated by the MA ~ MB signal. Another pair of positive capacitor-diode gates is provided for jam transfers into each flip-flop of the MB and is used with the Type 137 Analog-to-Digital Converter. These gates allow a binary 1 to be set into MBO during the start of a conversion and permit this 1 to be shifted to the right through the MB until the conversion has been made to the desired accuracy. During the first approximation, the A-D Start signal from the converter is supplied to enable the level input of these capacitor-diode gates of flip-flop MB ' and the O enab I ing input to the capac itor-diode gates of successive MB fl ip-flops is provided by the 1 output of the next most significant fl ip-flop of the MB. These gates are initiated to perform the jam transfer by the MB Shift pulse which is also supplied from the Type 137 converter. The complement capacitor-diode gate functions in the same manner as the corresponding circuit of the MA to allow the MB to be used as a binary counter when the MB Carry Enable 2-24 signal is provided. These capacitor-diode gates for flip-flops MB _ are initiated directly O9 when the next least significant fl ip-flop changes from the 1 to the 0 state. Complementing of the two least significant bits of the MB is controlled by gating circuits shown at the right of sheet 2 of engineering drawing 9. This gating initiates the complement capacitor-diode gate of MB11 when the skip fl ip-flop is in the 0 state or when a positive pulse is suppl ied to 1J03-38 from an external device, thus incrementing the content of the MB by one. If MBll changes from the 1 to the 0 state when complemented, this change initiates pulse inverter XYZ of the module at location 1C05 to propagate the carry pulse that complements fl ip-flop MBl O· The c,omplement capacitor-diode gate of MBl 0 is also triggered by a count MB pulse when the skip flip-flop is in the 1 state, thus incrementing the content of the MB by two. Terminal K of each MB flip-flop is supplied to terminals 1 through 12 of the data break interface connector 1J03 through the output bus drivers (shown on engineering drawing 31) for use by peripheral equipment. Terminal L of each MB flip-flop is routed to an indicator driver on the operator console. The L terminals of MB bits 3 through 8 are also supplied to terminals 27 through 38 of interface connectors 1 J01 and 1J02 via the output bus drivers. These signals allow complementary outputs of MB _ to be used by device selectors in all peripheral equipment. 3 8 ACCUMULATOR (9) The accumu lator (AC) is the major arithmetic register and input-output register of the PDP-5. The AC is shown on the bottom portion of both sheets of engineering drawing 9 to consist of one flip-flop cJnd associated gating from each of the 12 4206 Triple Flip-Flop modules at locations lB02 through 1B13. The accumulator can be cleared directly, complemented through a variety of gating, and cleared and set through jam-transfer gating circuits under the control of signals genc~rated by the accumulator control element. The accumulator can also be cleared and set by mec:ms of gating circuits which provide a jam transfer under the control of signals received from the Type 137 Analog-to-Digital Converter, and can be set directly by pulses received from the input mixer as a result of data supplied by peripheral equipment. Complementation of a flip-flop occurs when a positive pulse is applied to the direct-complement terminal from either the complement capacitor-diode gate or from the pulse inverter shown above the indicator connector for the accumulator on engineering drawing 9. 2-25 During T5 of the CMA microinstruction, the Complement Accumulator signal is produced as a negative pulse which is applied to this pulse inverter, causing complementation of the associated AC flip-flop. During the TAD instruction, the AC fl ip-flop can be complemented in each of the following three sta ges: a. If the corresponding bit of the MB is a 1, the complement capacitor-diode gate is enabled during T4 and is triggered by the Half Add signa I. b. If an AC bit contains a a and an MB bit contains a 1 following the half add operation, carry pulses for the half add are produced by one of the negative capac itor-diode gate that precede the pulse inverter. Th is gate is triggered during T6 by the Carry Initiate pulse, and the pulse inverter is initiated to produce the AC Carry pulse suppl ied to the complement input of the next most significant AC flip-flop. c. The second negative capac itor-diode gate preceding the pulse inverter is enabled between time states T4 and T1 and is initiated when any AC bit changes from the 1 to the a state, thus initiating operation of the pulse inverter to complement the next most significant AC flip-flop. The set and clear operations of each AC flip-flop are performed very simply. A flip-flop is cleared when the positive Clear AC signal is supplied to its direct-clear input, this signal being produced by the accumulator control element as a function of the CLA instruction, pulses suppl ied by peripheral equipment, or by various control states within the computer. Positive pulses supplied to the gated set input of each flip-flop from the input mixer effectively transfer information into the accumulator from signals suppl ied by peripheral equipment to terminals 17 through 24 of interface connector 1 Jal. During an AND instruction, the MBa ~ AC signal is produced to initiate operation of the positive capacitor-diode gate enabled by the a status of the corresponding MB flip-flop, thus transferring zeros into the AC fl ip-flop if the corresponding bit of the core memory word held in the MB is a binary o. Other gates to the input of the AC fl ip-flops provide a jam transfer of information from the next higher significant AC fl ip-flop bit during rotate right commands and from the next lower significant AC flip-flop bit during rotate left commands. Still other gates to the input of the AC fl ip-flops allow an AC flip-flop to be cleared when the next higher significant MB flip-flop 2-26 bit contains a 1 or allow it to be cleared when the corresponding MB flip-flop contains a 1 when the Comparator signal is present. The Comparator signal and the A-D convert signal that effect this gating are produced by the Type 137 converter. Output signals from terminal F of each accumulator flip-flop are supplied to indicator drivers on the open::ltor console and to the ladder network of the Type 137 converter. Outputs from terminal E of each flip-flop are supplied to the output bus drivers for application to terminals 1 through 12 of interface connectors 1JOl and 1 J02 for transfers to peripheral equipment. liNK (9) The link (l) is a l-bit register used to extend the arithmetic capabilities of the accumulator by serving as a carry or overflow register. The Iink is shown at the lower left corner of sheet 1 of engineeri'ng drawing 9 to be one flip-flop of the 4215 4-Bit Flip-Flop at location 1 DOl and associaf'ed gating circuits. The link is cleared by a standard DEC positive pulse applied to the direct input from terminal 1 D24Z. A pulse occurs at this terminal during SP3 of an operation initiated by pressing the START key or during T4 of the fetch state of the Cll microinstruction (as indicated by the negative Nd-'HC +-+'>--f->r-I'-'r-f-'rtC -<>---< o I T~ READ-WRITE SWITCH 0_ TYPE 1987 READ-WRITE SW~H ~ 50n ~ ~TYPE 1976 R~g~~gR t+'<+~'d"~:=l=l=j:::j:::ttU~:::U TYPE 1987 READ-WRITE SWITCH TYPE 1987 READ-WRITE SW~:H 50n o ~TYPE 1976 R~g~~gR t+VVV\-L:=t:ttttt:tt=l=1=U -13V -0-- ~ TYPE 1987 READ-WRITE SWITCH ~ -13 J -3V TYPE 1989 MEMORY DRIVER X TYPE 1989 MEMORY DRIVER TYPE 1987 READ-WRITE SWITCH 50n ~.~~~~~~~:=.========~ R~g~~~ ~.I\C:------1 ~~======~~o~_ ____________ >-----<> -A-AI'I'T~ I TYPE 1987 READ-WRITE SWITCH Figure 3-2 Core Memory Drive System Equivalent Circuit 3-4 control two unidirectional current switches. On the read side of the core array, these switches are connected in parallel to allow passage of either read or write current and so are indicated by a single switch on the diagram. The current switches of the read-write switch modules on the write side of the core array are not connected in parallel since the direction of current flow through these switches is controlled by the memory diode units. The read-write switches at the top of Figure 3-2 are shown in the selected condition, whileall other read-write switches are shown in the disabled condition. During the read cycle, pulses induced on the se~se windings of each of the 12 planes are sampled by the sense ampl ifiers and compared with a preset sl ice level during receipt of the Memory Strobe pulse. If the vol tage induced on the sense winding is of greater ampl itude than the differential sl ice level vol tage, a DEC standard positive pulse is produced by the sense ampl Hier to set a corresponding bit of the memory buffer register to the binary 1 state. The Memory Strobe signal is timed to produce the most reliable transfer of information from the core array into the memory buffer register, with the best signal-to-noise ratio. During the write cycle, the Memory Inhibit signal enables operation of the inhibit selection element to produce hal f-select bucking currents in planes corresponding to bits containing zeros in the word being written into memory. Inhibit current flows through each core in the selected plane in a direction which cancels the effect of either the X or the Yaddress drive line, thereby preventing full selection and writing of ones. The planes receiving inhibit current are selected as a function of bits of the memory buffer register containing zeros. The timing of the Memory Inhibit signal causes the inhibit currents to be generated for a period which begins before and lasts until the address currents are no longer generated, thereby providing absolute surety that cores in inhibited planes cannot be set to 1 . CURRENT SOURCE The 735 Power Suppl y I shown in the lower left corner of engineering drawing 7, provides the current which is switched by the address and inhibit circuits and drives the core array. Core array drive currents are produced by this supply as the -13 volt R/W and -3 volt common line suppl ied to both the read and write memory drivers, and the -13 volt inhibit and -3 volt common line supplied to the inhibit drivers and inhibit resistor boards. 3-5 These voltages are regulated and temperature compensated by thermistors mounted in a dummy plane between bits 5 and 6 of the array. This supply also produces the -35 volt potential which is required by all of the decoding circuits and produces a +10 volt level which is used in the internal shunt-regulator and power supply control circuits. This supply consists of a dual power supply, as shown on engineering schematic RS-735, and a 1701 Power Supply Control module, as shown on engineering schematic RS-1701. The supply outputsat terminals Band C provide the compensated currents required by the inhibit circuits, and the outputs at terminals Band D provide the compensated current required by the read-write circuits. Since the read-write and inhibit vol tages must be well regulated, compound-connection shuntregulator circuits are used across these outputs. The bases of shunt-regulator transistors Q1 and Q3 are brought to terminals F and N (for connection to power control 1701) rather than to their respective output voltage points. The inhibit and read-write supplies are similar except that the output current adjustment range of the read-write supply is from 0.0 to 0.4 amperes, andthe output of the inhibit supply can be varied from 0.0 to 1.0 amperes. Consequently, both the inhibit supply series dropping resistance (R1-R2) and the emitter resistor (R4) of the principal shunting transistor Q4 are smaller than the corresponding resistors in the read-write supply. Besides regulating the output vol tages, the 1701 control compensates the output vol tages according to the ambient temperature at the core array and permits output voltage adjustments to meet individual requirements of a specific core array. The 1701 control module contains two identical circuits, the one shown in the lower half of schematic diagram RS-1701 controls the -13 vol t RjW supply, and the one shown at the top of the schematic controls the -13 volt inhibit supply of the 735. Operation of the control is implicit with the terminal connections as follows: a. Terminals E and M are connected to the -3 volt common. b. Terminals Hand P are connected to the -13 volt R/W and -13 volt inhibit line, respectively. c. Terminals F and N are the control outputs for the read-write and inhibit suppl ies, respectively. d. Terminal A receives + 1O-vol t operating potential from the 735 suppl y. 3-6 As an adjunct to the 735 supply, the control circuits perform the following functions: a. The outputs at terminals F and N bias the base of the shunt-regulator transistors Q1 and Q3 in the 735. This bias determines the read-write and inhibit output voltage. The bias and the resulting output voltage can be adjusted by turning rheostats R13 and R3. b. The thermistors in the dummy plane makes the bias temperaturedependent. Because the thermal coefficient of this thermistor is negative (- 4.4% per degree centigrade), the supply output voltage is a negative function of temperature (- 0.50/0 per degree centigrade). As the temperature of the core array increases, the read-write and inhibit voltages and currents decrease. This compensation adjuststhe output voltages in inverse proportion to the ambient temperature at the core array, since the core winding current required to switch a memory core is inversely proportional to the core temperature. c. The third function of the control circuit is to compensate for changes in the supply output voltages which are caused by variations in the load and in the primary input voltage. Currently DEC purchases memories which have two different core sizes and so have different current-correct ion coeffic i ents. Tota I read-write current and inh ib it current is compensated I - 0.7% per degree centigrade in a Ferroxcubearray and is compensated - 0.4% per degree centigrade in Electronic Memories Incorporated core arrays. MEMORY DR IVERS (17) The read and write memory drivers are shown in the lower left portion of engineering drawing 17 to consist of the 1989 modules at locations 1A03 and 1A04. The X and Y address drive currents at the outputs of these drivers are identical in magnitude but of opposite polarity, the polarity being establ ished by the connection of the driver in the memory system. Each memory driver functions as a programmable switch, the output terminal being switched to the - 3 volt common when the input signal is at ground potential, or the output being switched to the -13 volt read-write potential when the input is a standard DEC negative level. 3-7 The exact value of the X and Y half-select current passed by the output terminal of a memory driver is determined by the temperature-compensated -13 volt R/W output of the 735 Power Supply and by the impedance of the resistor boards and other circuit resistance between the output terminals of the read and write memory drivers. Both the X and the Y half-select cur- rents are nominally 210 milliamperes; however optimum current settings are determined at the factory and are designated on a label attached to the core array. These values are determined empirically for each memory system to assure maximum rei iabil ity and to assure peak performance of the address, inhibit, and sense circuits. A memory driver, shown on schematic diagram RS-1989, consists of an output I ine which is connected to the -13 volt read/write output of the 735 Power Supply through parallelconnected transistor current switches containing Q5, Q7, Q9, and Q11. The output terminal is also connected to the - 3 volt common output of the 735 supply through parallel-connected transistor current switches containing Q6, Q8, Q10, and Q12. The output circuit containing Q5 through Q11 serves as a current switch controlled by the emitter output from the circuit containing Q3. The output circuit containing transistors Q6 through Q12 functions as a current switch controlled by the circuit containing Q1. These two output circuits are identical and operate in complementary fashion, due to insertion of the inverter containing Q4 which precedes the input to the control circuit containing Q3. When the input to terminal J of this module is negative, transistor Q2 of the input stage becomes saturated, so that its collector output assures cutoff of transistors Q4, Q1, Q6, Q8, Q10, and Q12. The negative collector potential from cutoff transistor Q4 enables control transistor Q3 to conduct and thus turn on the odd-numbered output transistors to essentially connect the -13 volt potential at terminal X to the output terminal V. Conversely, when the input is at ground potential, Q2 is cut off causing conduction of Q4 and cut off of the output circuit containing odd numbered transistors. Under these conditions Q1 conducts to turn on the transistors in the output circuit containing even numbered transistorsto effectively connect the -3 volt common at terminal R to output terminal V. Current equalization through the output stages is accomplished by resistor networks in the emitter circuit of each output transistor. Output-circuit overshoot protection is provided by diode D6, which parallels the emitter-base junction of Q3, and by diode D4, which parallels the emitter-base junction of Q1 . 3-8 ADDRESS SELECTION (16) The clddress se lection circuits spec ify one of 64 X address I ines and one of 64 Y address lines which will be conditioned to pass read or write current through the core array. Address selec- tion is performed by the eight 1987 Read-Write Switch modules connected to the output of the memory drivers. Each module contains diode gating circuits that control four high-current read--write switch circuits. Half of the address selection is performed before the half after the current passes through the core array. Address switching performed at the output of the write memory driver is shown on the right side of engineering drawing 16, and switching performed at the output of the read memory driver is shown at the left side of this drawing. All address selection is performed as a function of the address contained in the memory address regis1-er. Complementary output signals from the 12 bits of the MA are decoded by four groups of two read-write switches as follows: a. MA , MA , and MA5 are decoded by modules at locations 1A05 and 4 2 1A06 to select the X address on the read side of the array. b. MA , MA , and MA9 are decoded by modules at locations 1A07 and 3 8 1 AD8 to select the Y address on the read side of the array. c. MAO' MA , and MA7 are decoded by modules at locations 1A09 and 6 1A 1D to select the X address on the write side of the core array. d. MAl' MAlO' and MAll are decoded by modules at locations 1All and 1A 12 to select the Y address on the write side of the core array. Half-select current drives 64 cores selected by the X address switching in each plane and 64 cores selected by the Y switching in each plane. Coincidence of X and Y write current in each plane provides the flux necessary to drive a core to the binary 1 state, if it is not inhibited by current from the inhibit selection circuits. Coincidence of X and Y read current in each plane completely switches a core to the binary 0 state. nate of each of the 12 planes are connected in series. Drive lines for each coordi- Half-select current for the X coordi- nate passes through one drive I ine for each of the 12 planes, each drive Iine of each plane 6 containing 2 or 64 cores. Half-select current for the Y coordinate also passes through one drive line of each of the 12 planes and drives 64 cores in each plane. 3-9 A 1987 Read-Write Switch module contains four similar circuits, each circuit consisting of a 4-input ground-potential NAND gate which enables or disables transistor switching circuits to allow passage of read or write current. Two unipolarity switching circuits which pass cur- rent in opposi te directions are control Ied by each NAN D gate. A common bus provides readwrite current from terminal S to one side of each of the eight switches within a module 0 On the read side of the core array the output terminals for each pair of switches in a 1987 module are connected in parallel, and the outputs of each pair of switches on the write side of the core array are connected in parallel after passing through the memory diode unitso The output switches enabled by each combination of input signals are indicated in Table 3-1 . TABLE 3-1 Grounded Input Terminals READ-WRITE SWITCH GATING Sel ected Pos i tive* Current Switch Transistor Output Terminal I Selected Negative* Current Switch Transistor Output Terminal 1 E oF . M 0 N Q4 Y Q3 z H . J . M 0 N Q12 W Qll X EoK o M 0 N Q8 U Q7 V Q16 P Q15 R J o L °M-N *Polarities are specified with respect to terminal S MEMORY DIODE UNITS AND CORE ARRAY (11, 12) The core array is composed of 12 core planes, each containing 4096 ferrite memory cores. Each plane is 64 cores wide by 64 cores deep, corresponding to the 64X and 64Y drive lines. Every core is threaded by four windings: X and Y address windings; an inhibit winding or digit line; and a sense winding. Each X or Yaddress line is threaded through a row of 64 cores in each plane; jumper connections between the planes connect corresponding rows of each plane in series 0 A single X winding and a single Y winding intersect at only one core location or address in each plane; correspond ing cores in each plane constitute a 12-bit memory address or memory register. Each plane contains an inh ibit winding wh ich passes through each core in the plane. One end of each of these windings is connected to the inhibit selection circuits, and the other end is connected in common for all 12 planes and is connected to the - 3 volt common 3-10 output of the 735 Power Supply. Sense windings are also wired on a per-plane basis. A sense winding passes through each core in a single plane, and both ends of the winding are connected to separate input terminals of a sense ampl ifier. Connectors on the core array allow plug-in mounting of the 1020 Memory Diode Unit modules directly on the array. These diodes prevent read-write current from passing through unsel ected address drive lines. Coordinate X and Y address drive I ines are shown on engineering drawings 11 and 12 with the ir connection to the memory diode units and the connectors which mate with the address selection circuits. INHIBIT SELECTIONS (17) During write operations, the inhibitselection circuits supply half-select current in the read polarity to all cores corresponding to bits in which zeros are to be written. This half-select current cancels the effect of one of the hal f-sel ect write currents suppl ied by the X and Y drive lines, so that a core is prevented from being set to the binary 1 status. Inhibit selection is different from address selection in that up to 12 planes, or 0 planes can be selected simultaneously as determined by the contents of corresponding bits of the memory buffer register. The inhibit selection element is shown in the upper right portion of engineering drawing 17 to consist of 1982 Inhibit Drive modules at locations 1 B21 through 1 B23 and 50-ohm 1978 Resistor Board modules at locations 1B24 and 1B25. Each 1982 Inhibit Driver module consists of four identical circuits, each circuit consisting of a 2-input ground-level NAND gate which controls the operation of a current switch transistor. One input to each NAND gate is provided by the inverted Memory Inhibit signal produced by the timing signal generator of the processor, thus enabling the inhibit selection circuits during time states T4, T5, and T6 of each memory cycle. The second input to each NAND gate is provi'ded by the output of the associated memory buffer register fl ip-flop which is in the ground condition during the binary 0 state. When enabled, the current switch operated by each NAND gate allows current to flow from the -3 volt common through the core array, through the resistor boards, and through the switch to the -13 volt inhibit output of the 735 Power Supply. The inhibit current ampl itude is determined by the potential difference between the temperaturecompensated -13 volt inhibit output and the -3 volt common output of the 735 Power Supply and by the resistance in the circuit which is mainly determined by the 50-ohm resistors in the 3-11 resistor board modules. Like the address drive current, exact inhibit current is specified by a label attached to the memory to specify optimum values for each particular memory system. Inhibit current is nominally 180 milliamperes. SENSE AMPLIFIERS (17) Sense system connections are made on a per-plane basis; each sense winding passes through each core in a particular plane, and both ends of the winding are connected directly to the input terminals of a sense amplifier circuit. The geometry of the winding and of the plane form a 2 by 2 checkerboard pattern of positive and negative polarity pulses induced on the sense winding as a function of the core addressing. Fu" or partial magnetic flux changes of all cores in a plane induce a voltage on the sense winding. During the 70-nanosecond duration of the Memory Strobe signal produced during read operations, the rectifying sense amplifiers compare the amplitude of the voltage induced on the sense winding with a preset slice level. If the amplitude of the induced voltage is greater than the amplitude of the slice level, the circuit produces a DEC standard positive pulse at the output terminal. The output pulse from each sense amplifier is applied to the direct-set input of the corresponding bit flip-flop of the memory buffer register. The sense ampl ifiers are shown in the lower right portion of engineering drawing 17 to consist of either 1571 or 4554 Dual Sense Amplifier modules at locations lB15 through 1 B20. When a core is switched from a binary 1 to the binary 0 state by a full-read current, a signal of approximately 60 millivolts is induced on the sense winding in that core plane. This 60millivolt signal is sensed by one of the two sense amplifiers on a 1571 or 4554 module and compared with an internally-generated slice level. These modules are similar except that the slice level is adjustable in the 1571 modules and is not adjustable in the 4554 modules. Sense winding attenuation is provided by a balanced input circuit of the differential preampl ifier. This preamplifier has a difference gain of approximately 20 and a common-mode gain of 0.5. The output of this preamplifier is ac coupled to a rectifying slicer with a variable slicing voltage. The output of this slicer is amplified and used as the enabling level for a pulse amplifier which functions as the final stage of the module. 3-12 TYPE 154 MEMORY EXTENSION CONTROL OPTION Field select control and address extension control for Type 155 Memory Modules are provided by the Type 154 Memory Extension Control. Extension of the storage capac ity of the PDP-5 beyond the capac ity of the standard 4096-word core memory is accompl ished by adding fields of 4096-word core memories, each field being a Type 155 Memory Module. Up to seven fields can be added to the standard 4096-word memory, providing a maximum storage of 32,768 words. 15 Direct addressing of 32,768 words requires 15 binary bits (2 = 32,768) . However, since programs and data need not be directly addressed for execution of each instruction, a field can be program-selected, and all 12-bit addresses are then assumed to be within the current memory field. The memory extension control consists of several 3-bit fl ip-flop registers that extend addresses to 15 bits to establish or select a field. The Type 154 Memory Extension Control consists of one mounting panel of modules which can be added to a cabinet containing the added Type 155 Memory Modules. The logic circuits of the memory extension control are shown on engineering drawing BS-D-154-0-4. The wiring of the module mounting panel and the type and location of modules within this panel are shown on engineering drawings WD-D-154-0-5 and UML-D-154-0-6, respectively. Addition of a memory extension control to a standard PDP-5 requires a modification of the operator console to add indicators and switches associated with the instruction field register and the data field register of the control. These indicators are similar to all other indicators on the operator console, and the switches function in the same manner as the switch register to load information into the fl ip-flop registers when the LOAD ADDRESS key is lifted. The nine functional circuit elements which comprise the memory extension control perform as follows: Inst. Field Register - The instruction field register is a 3-bit flip-flop register which determines the memory field from which instructions are to be taken from memory. This register consists of three fl ip-flops of a 4218 Quadrupl e FI ip-Flop modu Ie at location 2A 13 wh ic h can be se"t by the 4127 Pulse Inverter module at location 2A16, and whose outputs are decoded by the 4151 Binary-to-Octal Decoder module at location 2A04. The register is cleared directly during SP1 and is set by a ones transfer of information contained in the INSTRUCTION FIELD switch register during SP2 following operation of the LOAD ADDRESS key. 3-13 The register is also set by a jam transfer of information contained in the instruction buffer register by a TP5 pulse during the program count state of a JMP or JMS instruction. This latter transfer is performed to establish the instruction field when changed under program control or to re-establish the field as an exit from a program interrupt subroutine. The octal numbered output signals from the decoder are routed to input points of the enable field signal generator of the corresponding numbered field memory module. Data Field Register - This 3-bit fl ip-flop register determines the memory field used for programmed data storage and retrieval. The register consists of three flip-flops of the 4218 Quadruple FI ip-Flop at location 2A 14 and pulse inverters of the 4127 modules at locations 2A 15 and 2A 16. The register is direct Iy cleared during SP1 and set by a ones transfer of information contained in the DATA FIELD switch register during SP2 following operation of the LOAD ADDRESS key. The register is set by a jam transfer of information from bits 6 through 8 of the MB during a CDF microinstruction to establ ish a microprogrammed field. This transfer is initiated by an lOT 62X1 pulse which loads the data field register from MB _ during a change data field 6 8 microinstruction. The register is also set by a jam transfer of information from bits 3 through 5 of the save field register. This transfer is enacted by execution of the RMF (restore memory field) lOT microinstruction to restore program control at the conclusion of the program interrupt subroutine. The output of this register is decoded by the 4151 Binary-to-Octal Decoder at location 2A03 and supplied to enable field signal generator circuits of the corresponding field memory modu Ies. Break Field Register - This 3-bit flip-flop register provides a means of enabling a memory module field during data break transfers. In addition to specifying an initial address and a break request, a peripheral device can specify a memory field by supplying three address lines to the input terminals of this register. The register consists of the 4218 Quadruple Flip-Flop at location 2A19, three circuits of the 4102 Inverter module at location 2A18, and the 4151 module at location 2A05 which decodes the flip-flop output signals. Addresses supplied by an external device must be at ground potential to signify a binary 1. These signals and their complement enable the set and clear positive capacitor-diode gates at the input of each break field fl ip-flop. These gates are triggered to produce a jam transfer of information from the external device into the register by the Data Address ~ MA signal produced by the MA control element. Therefore, the transfer occurs during T1 of the break state in which there is no address Increment Request signal. 3-14 Inst. Buff Register - The instruction buffer register serves as a 3-bit flip-flop input buffer for the instruction field register. All field number transfers into the instruction field register are made through the instruction buffer, except transfers from the operator console switches. The instruction buffer consists of the 4218 module at location 2A10 and the 4127 modules at locations 2A11 and 2A12. The buffer is cleared and set by operation of the LOAD ADDRESS key in the same manner as the instruction field register. Jam transfer of information into the instruction buffer is accompl ished by the positive capac itor-diode gates at the input or by supplying positive pulses to ground the output terminals from the pulse inverters. During a CIF microinstruction (change instruction field), the lOT 62X2 pulse triggers the capacitor-diode gates to load the buffer with the programmed field number contained in MB6-8. During an RMF microinstruction, the pulse inverters at location 2A 12 are triggered to transfer the contents of bits 0 through 2 of the save field register into the instruction buffer to restore the instruction field to the conditions that existed prior to a program interrupt. Save Field Register - When a program interrupt occurs, this 6-bit register is cleared, then loaded from the instruction field and data field registers. The RMF microinstruction can be given immediately prior to the exit from the program interrupt subroutine to restore the instruction field and data field by transferring the contents of the save field (SF) register into the instruction buffer and the data field register. The SF consists of the 4220 8-Bit Buffer Register module at location 2A17 and the 4102 Inverter module at location 2A18 which serves as an output buffer amplifier for the register. The register is directly cleared during T1 of the execute 1 state of the operations which transfer program control for a program interrupt (in other words during the cycle in which the program count is stored at address 0001 of the JMS instruction forced by a program interrupt request). Then the instruction field and data field are strobed into the SF by a ones transfer by the capacitor-diode gates at the gated 1 input of each flip-flop. These capacitor-diode gates are triggered by the output of pulse amplifier NPRST at location 2A08, which in turn is triggered by a TP3 pulse during the El state following the program interrupt request. State Register - The three states or conditions for generating the Enable Field signals are produced by a 3-state circuit. This circuit is designed exactly Iike the major states generator of the processor, and is constructed of the 4113 Diode modules at locations 2A24 and 2A25. Circuits EFH, JKL, and MNP of the module at 2A24 serve as 2-input negative NAND gates to maintain a condition set by the corresponding circuits of the module at 2A25. The El output 3-15 signal enables generation of the Enable Field signal as a function of the data field and is produced by a TP1 pulse during every execute 1 major state. The F V E2 output signal enables generation of the Enable Field signal as a function of the instruction field and is produced by a TP1 pulse during both fetch and execute 2 major states. The B output signal enables generation of the Enable Field signal as a function of the break field and is produced by a TP1 pulse during every break major state. Entry into anyone state disables the other two states by inhibiting the inputs to the NAND gates that maintain them. Enable Field Signal Generator - When the PDP-5 core memory capacity is extended, the standard memory is designated as field O. This designation is effected by connecting terminal N of all 1987 Read-Write Switch modules to the Enable Field 0 signal produced by the memory extension control. This signal is generated by diode gating circuits of the 4114 module at location 2A06 and circuit RST of the 4113 module at location 2A25. The configuration of these circuits produces the ground-level Enable Field 0 signal as a function of any of the following conditions: a. When the Disable MA signal produced by the MA control element is at ground potential, which is indicated by the MAD signal being at -3 volts. b. When the MAD signal is at ground potential during the execute 1 state when the appropriate data field (0) is selected. c. When the MAD signal is at ground potential during either the execute 1 or fetch state when the appropriate instruction field (0) is selected. d. When the MAD signal is at ground potential during the break state when the appropriate break field (0) is selected. NOTE: The MAD signal is the unbuffered output from terminal 1 D09Y of the disable MA flip-flop of the MA control element. Therefore, this signal provides ground-level enabling of circuits in the memory extension control when the computer MA is not disabled. - 3-16 A circuit similar to this one is provided in each Type 155 Memory Module to control the address selection circuits. In a memory module the circuit differs only in that the output line from the decoders that corresponds to the field number is used as the input to each of the three ground-level NAND gates, and the condition when the MAD signal is at -3 volts (entry a of the prev ious list) is not used. Accumulator Transfer Gating - Diode gating circuits allow the contents of the SF, instruction field register, or the data field register to be strobed into the accumulator. Transfer of information in this manner is accomplished by circuits of 4113 Diode modules which sample the contents of registers and supply positive pulses to the input mixer upon receipt of lOT command pu Ises. During an RI B microinstruction, bits 6 through 11 of the AC are set by the content of the SF by 2-input negative NAND gates of the 4113 module at location 2A20. During an RIF microinstruction, bits 6 through 8 of the AC are set by the content of the instruction field regis1"er through gates EFH, JKL, and MNP of the module at 2A21. During an RDF microinstruc- t ion, bits 6 through 8 of the AC are set by the content of the data fie Id register through gates RST, UVW, and XYZ of the module at 2A21. Initiation of the 4113 modules to produce the pulses applied to the input mixer is caused by pulse amplifier circuits of the 4606 module at location 2A22. These pulse amplifiers are gated by the lOT 62X4 pulse and the contents of the memory buffer register bits that spec ify the appropriate lOT microinstruction. Device Selector - Bits 3 through 5 of the lOT instruction are decoded by the 4605 Pulse Amplifier module at location 2A07 to produce the lOT command pulses for the memory extension control. Bits 6 through 8 of the instruction are not used for device selection since they spec ify a field number in some commands. Therefore, the select code for this device selector is desi gnated as 2X. Note that the PC is always contained in address 0000 of field O. Programming considerations for the Type 154 Memory Extension Control are discussed in computer option bulletin F-53(154). TYPE 155 MEMORY MODULE OPTION Extension of the PDP-5 core memory beyond the standard 4096-word capac ity is accompl ished by addition of Type 155 Memory Modules to the system. Each 155 module extends memory by 4096 12-bit words. Up to seven memory modules can be added to a standard PDP-5 containing 3-17 4096 words, increasing the capacity of the system to 32,768 words. Addition of from one to seven memory modules requiresthataType 154 Memory Extension Control be added to the system. A 155 module consists of a core array, address selection circuits, inhibit selection circuits, sense ampl ifiers, memory drivers, and a 735 Power Supply wh ich are identical with these described previously in this section for the standard PDP-5. The minor differences between the standard core memory and a 155 module are as follows: a. A Field Enable signal generator is added which is identical with that described previously in this section of the manual under Type 154 Memory Extension Control Option. Th is generator in each module is operated from different octal field select code output signals of the data field, instruction fi e Id, and break fie Id register decoders of the extension control. When the assigned code is present in any of these register, the generator produces a Field Enable signal during appropriate major states. This signal is connected to input terminal N of all 1987 Read-Write Switch modules in the 155 module to enable address selection. In the standard PDP-5 with no memory extension, no connection is made to terminal N of all of the 1987 modules. With the addition of memory extension these terminals of the standard machine are connected to the Enable Field 0 signal produced by the Type 154 Memory Extension Control. b. The Memory Strobe signal produced by the timing signal generator of the processor is reshaped by a 1607 Pulse Amplifier module in the memory module before it is supplied to the sense amplifiers. Each 155 memory module added to the PDP-5 system requires two mounting panels of system modules. Engineering drawings for the memory module are designated by the type number and are not included in this manual because of their similarity with engineering drawings 16 and 17, and BS-D-154-0-4. 3-18 intricately involved in the operations of the PDP-5. The Type 153 Automatic Multiply and Divide option described in Section 2 of this manual, the Type 154 Memory Extension Control, and the Type 155 Memory Module options described in Section 3 of this manual are not peripheral equipment options. TELETYPE MODEL 33 AUTOMATIC SEND RECEIVE SET The Teletype unit suppl ied as standard equipment with a PDP-5 serves as a keyboard input and page printer output and as a perforated-tape reader input and a tape-punch output device. This unit is a standard Model 33 Automatic Send and Receive set (ASR) as described in the bulletins 273B and 1184B produced by the Teletype Corporation. For operation with the PDP-5, this unit has been modified as follows: a. The WRU (who are you) pawl is removed. This pawl is used only when several Teletypes are connected in a communication system so that a unit receiving a message sends a IIwho are you II message to the transmitting unit. The transmitting unit automatically produces the "here is ll identification code and suppl ies it to the receiving station. In the computer system this pawl is removed to prevent insertion of the IIhere is II code into data suppl ied to the computer from the Teletype unit. b. In early units containing a dial call control unit the OUT OF SERVICE lamp is drawn down into the console (not disconnected) and the ON L1NE/ LOCAL toggle switch is put in its place. c. Cable connections are made between the Teletype unit and the control as shown on engineering drawing 18. On units containing a dial call control a signal cable is permanently connected to one of the two cables within the unit which are terminated in 50-pin connectors. In Teletype units Wi!hr.:' out the dial call control, these connections are made to a terminal blo.c k within the stand. In both cases a relay is added and connections ore made to the tape reader advance magnet that enable tape motion while a character is being assembled in the control and disable the magn~.t when the keyboard flag is a 1, indicating that the character has be.en assembled and is ready for transfer to the computer. 4-2 SECTION 4 INPUT/OUTPUT Signals which pass between peripheral equipment and the PDP-5 are normally in the form of pulses supplied to a processor input bus or static levels as processor output signals which may be sampled or strobed by a selected I/O device. The exceptions to this rule are the address and data signals supplied to the processor during data break operations as static levels and the Address Accepted and lOP pulses, which are pulse outputs of the processor. The bussed nature of input/output signals of the processor requires that the peripheral equipment contain gating circuits to control the appl ication of input pulses to the processor and timing control circuits to strobe processor output Iines to. transfer information into external devi ce buffers. The design of circuits in input/output equipment that performs these operations depends upon the characteristics of the processor interface circuits as described in Section 6, the functional operation of the processor interface logic elements as explained in Section 2, and by the nature of the circuits in the peripheral equipment wh ich receives or transmi ts signals. Gating circuits in peripheral equipment that supplies input pulses to the processor can be similar to those shown on the processor drawings for standard input/output devices. Programmed information transfers (including initial izing of equipment using the data break facility) between the processor and all other devices require that each circuit (or group of circuits) transmitting or receiving information be enabled by a pre-establ ished select code contained in bits 3 through 8 of an lOT. instrucstruction, and require that transfers are accompl ished in synchronism with the ti ming of the '. processor. These operations are accomplished by a 4605 Pulse Ampl ifier module that serves as a d~vice selector. Typical device selectors are shown on engineering drawing 8 for both the progra:n interrupt synchron ization element and the Type 137 Analog-To-D igital Converter, and "- on engineering drawing 18 for the Teletype control. The schematic circuit for a device selector is shown on drawing RS-4605. The standard peripheral equipment suppl ied with a PDP-5 consists of a Teletype Model 33 Automatic Send Receive~'~ and a Teletype Control which are described in this section of the manual. Optional peripheral\.equipment is described in separate documents, except for the Type 137 Analog- To-Digital Converter which is described in this section because it is 4-1 This modification takes only a few minutes and does not permanently limit any normal use which can be made of the 33 ASR. TELETYPE CONTROL (18) Serial information read or written by the Teletype unit is assembled or disassembled by the control for parallel transfer to the input mixer or from the accumulator of the processor. The control a Iso provides the program flags wh ich cause a program interrupt or an instruction skip based upon the availability of the Teletype unit and thus controls the rate of information transfer flow between the Teletype and the processor as a function of the program. The control is shown on engineering drawing 18 to consist of the eight system modules at locations 1 F18 through 1 F25. This drawing also shows the interface connections between the control and the Teletype unit. Interface connec tions between the control and the processor are i nd ica ted on Tabl e 4-1, except for the standard inputs to the device selectors from the lOP generator and the memory buffer register, which are described in detail in Section 6 of this manual. TABLE 4-1 TELETYPE CONTROL INTERFACE WITH PROCESSOR Processor Signal Power Clear Logic Element Power Clear Gen Engineering Drawing Terminal Symbol and Direction Teletype Control Terminal 5 1 E05E .... lF25M 1 AC 4 AC 9 1 B06F --<> 1F25X AC 1 5 AC 9 1 B07F --<> 1 F25Y AC 1 6 AC 9 1 B08F ----<> 1F25Z AC 1 7 AC 9 1 B09F --<> 1 F25L AC 1 8 AC 9 1 B1 OF --<> 1 F25K AC 1 9 AC 9 1 B11 F --<> 1 F25.J 4-3 TABLE 4-1 TELETYPE CONTROL I NTERFACE WITH PROCESSOR (continued) Processor Signal Symbol and Direction Teletype Control Terminal Logic Element Engineering Drawing Terminal AC 9 1B12F --<> 1F25H AC 9 1 B13F --<> lF25F Teleprinter Flag Skip Control S lC04X Teleprinter Flag Interrupt Sync S 1D04F Keyboard Flag Skip Control S 1E09Y Keyboard Flag Interrupt Sync S lD04H lOT 6031 Skip Control S lOT 6032 AC Control lOT 6034 1M AC AC 1 10 1 ll lOT 6041 Skip Control lF24V 1E09X • • • •... S 1COl E 04 lF19H 14 1E12K - lF24J 1M 14 1E14X <>- 1F24K 1M 14 1E14L <>- 1F24L 1M 14 1E13X 0--- 1F24N 1M 14 1E13L <>- lF24F LUI? 1M 14 1E12X 1F24H LUiS 1M 14 1E12L <><>- LUI LUI LUI LUI 2 3 4 5 6 lF24V In all programmed operation, the Teletype unit is considered as two separate devices. It is considered a line unit in (LUI) as a source of input intelligence from the keyboard or the perforated-tape reader and is considered a line unit out (LUO) for computer output information to be printed and/or punched on tape. Therefore, two device selectors are used; the 4605 Pulse Ampl ifier at location 1F19 is assigned the select code of 03 to initiate operations associated 4-4 with the keyboard/reader, and the device selector at 1 F20 is assigned the select code of 04 to perform operations associated with the teleprinter/punch. Parallel input and output functions are performed by corresponding lOT pulses produced by the two device selectors. Pulses pro- - duced by IOP1 pulse trigger skip gates in the skip control element; pulses produced by the IOP2 pulse clear the control flags and/or the accumulator; and pulses produced by the IOP4 pu Ise in itiate data transfers to or from the contro I. Signals used by the Teletype unit are standard 11-unit-code serial current pulses consisting of marks (bias current) and spaces (no current). Each 11-unit Teletype character consists of a l-unitstart space, eight 1-unit character bauds, -and a 2-unit stop mark. Teletype characters from the keyboard/reader are received by the 4706 Teletype Incoming Line Unit module at location 1 F24 containing the 8-bit fl ip-flop shift register LUI. The character code of a Teletype character is loaded into the LUI so that spaces correspond with binary zeros and marks correspond to binary ones. Upon program command thecontentof the LUI istransferred in parallel to the accumulator, via the input mixer. Eight-b it computer characters from the accumulator are loaded in parallel into the 8-bit flip-flop shift register LUO of the 4707 Teletype Transmitter module at location 1 F25 for transmission to the Teletype unit. This module generates the start space, then shifts the eight character bits into a flip-flop which controlsthe printer selector magnets of the Tel etype un it, and then produces the stop mark. Th is transfer of informat ion from the LUO into the Teletype unit is accomplished in a serial manner at the normal Teletype rate. A negative Active signal is produced by the control circuit of the Teletype incoming line unit module when a Teletype character starts to enter the LUI. This signal clears control flip-flop FF , which in turn de-energizes a relay in the Teletype unit to release the tape feed latch. 1 When released, the latch mechanism stops tape motion only when a complete character has been sensed and before sensing of the next charac1"er is started. A keyboard flag on the 4706 module is set and causes a program interrupt when an 8-bit computer character has been assembled in the LUI from a Teletype character. The program senses the condition of this flag with a KSF microinstruction (skip if keyboard flag is a 1, lOT 6031) and issues a KRB microinstruction (lOT 6036) which clears the AC, clears the keyboard flag, transfers the content of the LUI into the AC, andsets FF1 to enable advance of the tape feed mechanism. A teleprinter flag in the Teletype transmitter module is set when the last bit of the Teletype code has been sent to the teleprinter/punch, indicating that the LUO is ready to receive a new character from the AC. This flag is connected to both the program interrupt synchronization element and the skip control element. Upon detecting the set condition of the flag by 4-5 means of the TSF microinstruction (skip if teleprinter flag is a 1, lOT 6041) the program issues a TLS microinstruction (lOT 6046) which clears the flag and loads a new computer character into the LUO. Operation of the Teletype incoming line unit module requires an input clock signal which is eight times the baud frequency of the Teletype unit. This signal is used to control the strobing of Teletype information into the LUI during the center of each baud (which is the most reliable time for sensing) and to control the shifting of information through the fl ip-flops of the LUI. The Teletype transmitter module requires an input clock frequency which is twice the baud frequency of the Teletype unit. This signal is used to control the shifting of the LUO and thus determines the timing of the 11-unit-code Teletype character it generates. The LUI Clock and LUO Clock signals are produced by the 4225 8-Bit BCD or Binary Counter module at location 1F23. Six flip-flops of this module are connected asabinary counter which provides frequency division of the output from the 4407 Crystal Clock module at location 1 F22. This frequency division method is used since electronic clocks are not reliable at the low frequency required for Teletype operation. The 14.08-kc frequency of the clock is 128 times the baud frequency of the Teletype unit. Division of the clock frequency by 16 (4 binary flip-flops) yields the LUI Clock signal, which is 8 times the baud frequency, and division by 64 (6 binary flip-flops) yields the LUO Clock signal, which is twice the baud frequency. TYPE 137 ANALOG-TO-DIGITAL CONVERTER (137-2-1) This converter operates in the conventional successive approximation manner, using the memory buffer register as a distributor shift register and using the accumulator as the digital buffer register. This process starts by assuming that the value of the analog input signal is at mid scale by setting a binary 1 into the most significant bit of the accumulator and producing a voltage equal to the center of the range of the converter (ground to -10 volts). This voltage is produced by a digital-to-analog converter which operates as a function of a number contained in the accumulator. This voltage is then compared with the analog input signal and the results of the comparison are used to clear the least significant bit of the accumulator if the approximated voltage generated is of greater ampl itude than the analog input signal. This process is then repeated by setting the next least significant bit of the accumulator to the 1 state, generating the analog signal according to the contents of the accumulator, and comparing 4-6 this signal with the analog input signal to clear the bit of the AC which was just set previously if the generated signal is greater than the input signal being measured. This process is repeated a number of times depending upon the preset accuracy of the conversion. Each approximation reduces the error of the resul tant binary number in the AC by approximately one half. The bit of the accumulator which is first set then evaluated is controlled by the memory buffer register. During the first approximation, a binary 1 is set into most significant bit of the MB and irs shifted right one place at the conclusion of each approximation. The bit of the accumulator which is processed is controlled by the location of this binary 1 in the MB. The location of this binary 1 in the MB is also used to control the number of approximations performed, and hence determines the accuracy of the conversion. Since the conversion is started at the time the binary 1 is shifted in the MB, one conversion takes place after the sensing of the 1 in the MB which discontinues the conversion process. At the concl usion of the conversion, the unsigned binary number contained in the accumulator is accurate to ± one half of the digital value of the least significant bit converted. At the conclusion of the conversion a Restart 1 pulse is produced by the converter wh i ch cl ears the MB and continues the normal computer program. The Type 137 Analog-To-Digital Converter consists of the eight system modules in locations 1E17 through 1E24 and a fl ip-flop and three inverters in module mounting panel 1D which are unused in the operation of the processor. Complete module mounting panel wiring for i'he converter is provided in the standard PD P-5, so that addi tion of the 137 option requires onl y addition of the modul es and wiring connections that determine the accuracy of the conversion and connection of the analog input signal to be measured. The block schematic for the logic cir- cuits of the converter is shown on engineering drawing BS-D-137- 0-1 , and the interface connections between the converter and the PDP-5 processor are indicated in Table 4- 2, except for the inputs to the device selector. Note that the input connection to converter terminal 1E17L is one of six possible connections to the MB and determines the accuracy of the conversion. The origin of this signal in the MB is indicated in Table 4- 3 with other characteristics of the converter affected by the accuracy connection. To save program running time, the converter should be connected to provide onl y the accuracy required by the program appl ication. Maximum error of the converter is equal to the switching point error plus the quantization error. Maximum quantization error is equal to ± one half of the digital value of the least significant bit. Switching point error, total conversion time, and execution time of the lOT microinstruction which initiates operation of the converter are indicated in Table 4-3. 4-7 TABLE 4-2 ANALOG- TO-DIGITAL CONVERTER INTERFACE WITH PROCESSOR Processor Signal Symbol and Direction Logic Element Engineering Drawing Terminal lOT 6004 I/O Halt 5 1D12U ~ 1F18K lOT 6004 AC Control 8 lC04K .... 1F18K Restart 1 Restart 5 1E02W ..... 1E17H Restart 1 MB Control 7 1C15U .... lE17H Converter Terminal A-D Start MB 9 1B02M • 1DOl J Shift MB MB 9 1B02B -- lD20Z 1 MB _ 5 10 MB 9 lB07-11L AC 1 0 AC 9 1B02F AC 1 1 AC 9 1B03F AC 1 2 AC 9 1B04F AC 1 3 AC 9 1B05F AC 1 4 AC 9 1B06F AC 9 1B07F AC 1 5 AC 1 6 AC 9 1B08F AC 1 7 AC 9 1B09F AC 1 8 AC 9 1Bl OF AC 1 9 AC 9 1Bll F 4-8 • • • • • • • • • • • lE17L lE21F lE21H lE21J lE21K lE21F lE20F lE20H lE20J lE20K lE20L TABLE 4-2 ANAlOG-TO-DIGITAl CONVERTER INTERFACE WITH PROCESSOR (continued) Processor Signal logic Element Eng ineer ing Drawing Terminal AC 9 1 B12F AC 9 1 B13F TABLE 4-3 Symbol and Direction Converter Terminal • • lE19F lE19H CHARACTERISTICS OF THE 137 Origin of MB Signal to lElBT Switching Point Error 6 1 B07l ±1.6% 3.5 24.5 36.5 7 1 BOBl ±O.B% 4.0 32.0 44.0 B 1 B09l ± 0 .4% 4.5 40.5 52.0 9 1 Bl Ol ± 0.20/0 5.0 50.0 62.0 10 1 Bl1l ±0.1 % 6.0 66.0 78.0 11 1 B12l ±0.05% 11 .0 132.0 144.0 Adjusted Bit Accuracy Conversion Time per Bit (in IJsec) Total Conversion Time (in IJsec) Instruc tion Execution Time (in ~sec) Operation of this converter is initiated by execution of an ADC microinstruction which causes generation of an lOT 6004 pulse. This pulse is produced by the device selector at location t.FIB which has the assigned select code of 00. This device selector also serves the program interrupt synchronization element and is shown on engineering drawing B. This pulse performs the follc.wing operations: a. ':~ts the I/O- hit fl ip-flop which in turn clears the run fl ip-ftop, as shown O'=', engineering drawing 5, to temporarily halt the computer program after issu ing the TPI pu Ise. The TPI pu Ise in itiates generation of signa Is which clear the MB. 4-9 b. Initiates operation of the pulse amplifier in the AC control element, shown on engineering drawing 8, that produces the Clear AC signal. c. Sets the A-D starf fl ip-flop to the 1 status by suppl ying a positive grounding pulse to the 1 outpu.t terminal. d. Initiates operation of the 4303 Integrating Single Shot at location 1E18. The binary 1 output of the A-D start flip-flop enables a capacitor-diode gate at the set-to-l input of the most significant bit of the MB and the AC. These capacitor-diode gates are triggered by the Shift MB and A-D Convert signals produced by pulse amplifiers UWX and MPR of the 4606 module at location lE17 of the converter. These pulse amplifiers are initiated by the negative shift of the 0 output level of the integrating single shot when the time delay has expired. The integrating single shot is a monostable multivibrator whose 0 output (at terminal U) is at ground potential during the delay period and whose 1 output (at terminal W) is at -3 volts during the delay period. This circuit is self-regenerative through a positive capacitor-diode gate which is enabled by a binary 1 output from a selected flip-flop of the MB. The output from th is fl ip-flop of the MB is in the ground condi tion unti I a spec ified number of approx imations have taken place, at which time this MB flip-flop is set to 1 and the signal changes to -3 volts, disabling the capacitor-diode gate. This gate is initiated by the positive transition of the 1 output of the mul tivibrator at the conclusion of each delay period as long as the MB accuracy control flip-flop remains in the 0 state. The timing of the single shot delay period is adjusted by an internal potentiometer to correspond with the conversion time per bit as specified in Table 4-3. When the MB accuracy control bit becomes a binary 1, it enables the capac itor-diode gate at the input to pulse amplifier JH of the module at location lE17. This pulse amplifier is initiated by the negative shift of the 0 output from the integrating single shot at the expiration of the final delay period, and thus produces the Restart 1 pulse. The Restart 1 pulse setsJ:·h"e run flip-flop to allow the computer program to advance, clears the I/O-hit flip-fIO{J, and causes generation of the pulses which cle~r the MB .. The A-D Convert signal is suppl ied to the direct-clear input of the A-"D start fl ip-flop so that a single 1 is set into the MB. This flip-flop is also cleared during the power turn on and turn off sequence by the Power Clear pu Ises. 4-10 Having been cleared by the lOT 6004 pulse, then having a binary 1 set into the most significant bit flip-flop, the accumulator contains a binary number which corresponds to one half of its possible maximum value during the first approximation. The state of each bit of the accumulator controls a level ampl ifier of the modules at locations 1E19 through 1 E21. The level amplifiersalso receive a -10 volt potential from the output of the 1704 -10 Volt Precision Power Supply module at location 1E23. Each level amplifier circuit provides an output ground potential when the input signal is at ground level, and produces a -10 volt output signal when the input is at -3 volts. The output from each level amplifier is combined in a 1574 12-·Bit Digital-To-Analog Converter module at location 1E22 that produces the analog voltage to represent the binary number contained in the accumulator. The output of this converter is compared with the analog input signal to be measured by a 1572 Difference Amplifier module at location 1E24. The output (at terminal F) of this difference amplifier is -3 volts if the input from the converter (at terminal P) is more negative than the analog input signal (at terminal N) being measured. The output of this ampl ifier is at ground potential if the input from the converter is more positive than the analog input signal. This output is inverted and suppl ied to the accumulator as the Cdmparator signal. The Comparator signal is supplied to one input of a 2-input ground-level AND gate at the input of each fI ip-flop of the accumulator. The second input to each AND gate is enabled by the corresponding bit of the memory buffer register being in the 1 state. When the AND gate is enabled by both conditions, it supplies the enabling level to a positive capacitor-diode gate at the clear input of the accumulator flip-flop. A corresponding positive-capacitor diode gate at the set-to-1 input of each AC fl ip-flop is enabled by the binary 1 state of the next most significant bit of the memory buffer register. of AC O This input to the set-to-1 capacitor-diode gate is cond itioned by the binary 1 state of the A-D start fl ip-flop of the converter. These cOj:'Ocitor-diode gates are triggered at the conclusion of each delay period of the integrating single Sll"'~' At this time also, the Shift MB signal is produced to shift the contents of the memory buffer reg:ster one position to the right. Th is sh ifting is accompl ished by a jam transfer of information from ,he next most significant bit of the MB (and from the A-D start fl ip-flop for MB ). This operatio:1 transfers a binary 1 into MBO during the first conversion and shifts it to O the right for each succes:ive conversion, The MB bit contain ing a 1 enabl es the next Ieast significant bit of the accumulator to be set to 1 for the next approximation. 4-11 In summary, the lOT 6004 pul se clears the MB and AC, in itiates an I/O hal t, starts operation of an integrating single shot whose period is determined by the time required to generate and compare an analog signal with the signal to be measured, and sets the A-D start fl ip-flop wh ich serves as an extension for the memory buffer register. When the single shot period elapses for the first time, the content of the memory buffer register is shifted to the right so that all bits contain zeros except the most significant bit which contains a 1. At this time also, themost significant bit of the accumulator is set to ,. The content of the accumulator is then used to produce an analog signal which is compared with the signal to be measured. If the generated analog signal is more negative (greater ampl itude) than the signal being measured, the Comparator signal is at ground level, enabl ing the capacitor-diode gate at the clear input of AC • When the time period of the integrating single shot elapses again, AC O O is cleared if the Comparator signal is at ground potential and AC, is set to , from the content of MBO. This operation of setting a , into the next least significant AC fl ip-flop, producing a comparator signal to clear the AC bit based on the comparison with the signal being measured, and advance of a binary' through the MB continues until the integrating single shot is no longer regenerative. Regenerative operation of the single shot is inhibited when the binary , shifted through the MB reaches a preselected bit. At this time the MB bit output enables a pulse ampl ifier to produce the Restart' signal when the last time period of the single shot expires. The restart pulse restores the processor timing signal generator to allow the program to continue and clears the MB. At this ti me the AC holds an unsigned binary number that corresponds with the value of the analog input signal. This number can be processed under program control. 4-12 SECTION 5 LOGIC FUNCTION Manual and automatic operation of the PDP-5 is required in the performance of any complete task. Manual operation is normally limited to storing a readin mode loader program, modifying data or addresses in an existing stored program, or establishing the starting conditions for a program to be run automatica Ily. Automatic operation is used in the performance of a II programs except in maintaining the equipment or troubleshooting a nev-; program. The functions performed during each time state of each major state for both manua I and automatic operation are shown on engineering drawing FD-D-5-0-2. Manual operation and manual timing are indicated on the right side of this drawing, and automatic operation is indicated on the remaining portion of the drawing. All manual operations are performed in one cycle of the special pulse generator, and automatic operation cycles through major states, determined mainly by i'he instruction currently in progress. Automatic operation is in itiated by a manua I operation and, since there is no instruct! on in progress when operations are started, automatic operation always begins in the program count state to locate the first instruction to be executed. MANUAL OPERATION Keys and switches on the operator console allow information to be stored in core memory, allow the contents of a specified core memory register to be displayed for visual examination, and allow execution of a program automatically or semi-automatically. Operation of either the LOAD ADDRESS, DEPOSIT, EXAMINE, START, or CONTINUE key initiates operation of the special pulse generator to produce the four SP time states. These time states enable sequential actions to occur, beginning during time state SPO by clearing the run fl ip-flop. Operation of either the DEPOSIT, EXAMINE, STOP, key or setting of either the SINGLE STEP or SINGLE INST switch to the right position causes operations to stop by clearing the run fl ip-flop during T6 of any time cycle or the final time cycle of the current instruction. 5-1 LOAD ADDRE SS Key This key is Iif ted to load a number, manua Ily set into the SR, into the MA to specify an address for succeeding manua I or automatic operations. Operation of the key clears the run fl ip-flop during sPa, clears and enables the MA during SP1, and transfers the content of the SR into the MA during SP2. DEPOSIT Key This key provides a means of storing a number, manually set into the SR, into the core memory register currently specified by the MA. When this key is lifted, immediately the MA Carry Enable signal level is produced, and the following actions take place during the cycle of the spec ia I pu Ise genera tor: a. During spa the run fl ip-flop is cleared. b. During SP1 the MA is enabled, the IR is cleared, the int ack (interrupt acknowledge) fl ip-flop is cleared, and the MB is cleared. c. During SP2 fl ip-flop IR1 and IR2 are set to designate the DCA instruction, the AC is cleared, and the major state generator is set to the execute 1 state. d. During SP3 the int (interrupt) delay fl ip-flop is cleared, the content of the SR is transferred into the AC, and the run fl ip-flop is set. Setting the run flip-flop enables operation of the timing signal generator, and the computer commences normal operation beginning with time state T2 during major state E1 of a DCA instruction. During time state T3, the content of the AC is transferred into the MB and the ac- cumulator is cleared. The content of the MB is then written into core memory during T5 and T6, and the E1 major state expires at the beginning of T6 when a new state is entered. In automatic operation the E1 state of the DCA instruction is normally followed by a P state, however during the P state the MA is disabled, and so the E2 state is forced at T6 of this manual operation. During T6 the run flip-flop is cleared, disabling the time pulse generator at the end of the T1 state. During T1 of the E2 major state the content of the MA is incremented by one to allow successive operations of the DEPOSIT key to store information at successive core memory addresses without the necessity of loading each address into the MA by means of LOAD ADDRESS key. Since the time pulse generator is disabled and stops at the end of T1, the operations per- formed by the DEPOSIT key are then concluded. 5-2 This key provides a means of reading the information contained in a specified core memory address so that its content can be examined as displayed by the indicators of the MB. Immediately upon pressing this key, the MA is enabled and the following operations occur during the cycle of the special pulse generator: a. During SPO the run fl ip~flop is cleared. b. During SP1 the MA is enabled, the IR is cleared, the int ack flip-flop is cleared, and the MB is cleared. c. During SP2 the AC is cleared, the major state generator is set to the execute 1 state, and the IR2 flip-flop is set to establish the TAD instruction. d. During SP3 the int delay flip-flop is cleared and the run flip-flop is set. When the run flip-flop is set, the timing signal generator is enabled and operation continues in the E1 state of the TAD instruction. During T2 and T3, the content of the core memory register currently selected by the MA is read and transferred into the MB. During T4 of a TAD instruction, the content of the MB is combined with the content of the AC in a half add operation. Since the accumu lator was cleared during SP2, this operation serves as a direct transfer between the MA and the AC. During T5, the content of the MB is rewritten into core memory. During T6, the major state generator is forced to the E2 state and the run fl ip-flop is cleared. During T1 of the E2 state the content of the MA is incremented and the cycle stops to complete the operations performed by the EXAMINE key. The incrementing of the MA during major state E2 allows repeated operation of the EXAMINE key to display the contents of successive core memory registers without specifying each address. Operation of th is key initiates automatic operation of the PDP-5, commenc ing at the program count currently contained in the MA. When this key is pressed, the timing signal generator is initiated and the following operations take place: a. During SPO the run fl ip-flop is cleared. b. During SPl the int ack fl ip-flop is cleared, the IR is cleared, and the MB is cleared. 5-3 c. During SP2 the AC is cleared, the major state generator is set in the P state, and fl ip-flops IRO and IR2 are set to establ ish the JMP instruction. d. During SP3 the int delay and int enable flip-flops are cleared, the content of the MA is transferred into the MB, the I ink is cleared, the MA is disabled, and the run fl ip-flop is set. When the run fl ip-flop is set, the tim ing signa I generator is enabled and automatic operations commence at time state T2 in the program count state of a JMP instruction. Since the MB already contains the address of the first instruction to be performed, no Memory Strobe signal is produced and automatic operation continues as normal. During time state T5 the IR is cleared, and during T6 the fetch state is entered to bring the specified instruction from core memory and to commence executing it. CONTINUE Key Th is key provides a means of restarting a program at the beginning of any cyc Ie under the conditions which currently exist in the program counter and major state generator. When the CONTINUE key is pressed, the special pulse generator is initiated to perform the following operations: a. During SPO the run flip-flop is cleared. b. During SPl a TPl pulse is produced to allow clearing of registers and other functions performed during time state T1 of a normal cycle. c. Duri ng SP3 the run fl ip-flop is set. When the run flip-flop is set, the program continues in the normal automatic mode of operation beginning in time state T2. STOP Key lifting of the STOP key provides a means of halting the program. Operation of this key causes the run flip-flop to be cleared at T6 so that the timing signal generator is inhibited and stops at the conclusion of the T1 state. 5-4 SINGLE STEP and SINGLE INST Switches These two switches provide a means of advancing through a program semi-automatically, either one cycle at a time or one instruction at a time. In normal automatic operation both of these switches are set to the left position so that they perform no function. When the SINGLE STEP switch is in the right position, the run flip-flop is cleared during T6 of any cycle so that operations stop during T1 time. When the SINGLE INST switch is set to the right position, the run fl ip-flop is cleared during T6 of the major state that normally precedes the program count state, therefore halting operation at the conclusion of the execution of any instruction before another instruction is read from core memory. When either of these switches is set in the right position, a program can be advanced by means of the CONTINUE key. Both of these modes of semi- automatic operation are useful in monitoring the operation of a program as a means of checking a new program or in maintaining the PDP-5. AUTOMATIC OPERATION The normal mode of PDP-5 operation is automatic execution of programmed instructions. Automatic programmed operation can be modified by a program interrupt {produced by peripheral equipment to transfer program control to a subroutine} and can be temporarily disrupted by a data break {initiated by a peripheral device for a transfer of information between that device and core memory}. Features of automatic programmed instruction execution such as I/O skip, and I/O halt and restart are standard means which can be utilized during a program and so are not program modes in themselves and are not discussed in this chapter. These features are discussed in detail in Section 2 and in Section 4. Instructions The following explanations of the functions performed during the execution of each instruction assume that the PDP-5 is energized and operating normally and that the address of the next instruction is located in the MB. Therefore, each instruction explanation begins at the start of the fetch state. Logical AND {AND} The AND function is performed between the content of a specified core memory register and the content of the accumulator in three cycles; fetch, execute 1, and program count. As in 5-5 a II instructions, the fetch state is entered with the program count stored in the MB. During Tl of the F state the content of the MB is transferred into the MA, the MB is cleared in preparation for receiving the current instruction, and the skip flip-flop is cleared. At the start of T2, reading of the new instruction begins and strobing of the instruction into the MB occurs during T3. Also during T3 the four most significant bits of a new instruction word are transferred into the IR from the MB. As in all instructions, the instruction word is restored in the original core memory address during T5 and T6 of the fetch state. Since the AND instruction is a memory reference instruction (not an lOT and not an OPR), nothing further is accompl ished during the fetch state. During T6 of the fetch state, the major state generator is set to the El state since the instruction is not a JMP and contains a 0 in bit 3, assuming direct addressing. If the instruction does contain a 1 in bit 3, the defer state is entered from the fetch state, and then the execute 1 state is entered from the defer state. If the AND instruction contains a 1 in bit 3, the defer state is entered to load the MB with the 12-bit effective address of the operand from the core memory address specified in the instruction. During time state Tl the core memory address containing the effective address is loaded into the MA by transferring the content of bits 5 through 11 of the MB into corresponding bits of the MA, and by maintaining the current content of bits 0 through 4 of the MA (containing the PC) if bit 4 of the instruction is a 1, or clearing bits 0 through 4 of the MA if bit 4 of the instruction conta ins a o. After this transfer the MB is cleared during Tl and the content of the core mem- ory register at the modified address is read into the MB as the effec tive address. If th is effec- tive address is one of the eight auto-index registers (address 0010 through 0017) the content of the MB is incremented by one during T4. The content of the MB is restored in memory during T5 and T6. During T6 of the defer state, the major state generator is 'set to the El status since the current instruction is not a JMP. The El state of the AND instruction is entered to locate the operand and perform the logical AND operation (in other words to execute the instruction). The effective address of the operand is loaded into the MA as a function of the content of bits 3 and 4 of the current instruction. If bit 3 of the instruction contains a 1, the 12-bit effective address of the operand is loaded into the MB during the defer state, so the content of the MB is transferred into the MA. If the instruction contains a 0 in bit 3, the address portion of the instruction (bits 5 through 11) is transferred into the MA (which currently contains the program count) from the MB and bits 0 5-6 through 4 of the effective address are established in the MA as a function of the content of bit 4 of the instruction. If the instruction contains a 1 in bit 4, bits 0 through 4 of the MA are cleared (to specify memory page 0); if the instruction contains a 0 in bit 4, bits 0 through 4 of the MA are undisturbed (to spec ify the current memory page conta ins the operand). After this transfer the MB is cleared and the operand is read from core memory into the MB during T2 and T3. The logical AND operation is then transacted be1ween the content of the MB and the content of the AC by a transfer of zeros. In other words, if an MB bit conta ins a 0, the corresponding bit of the AC is set to O. Therefore, at the end of this operation all bits of the AC are cleared except bits which contained a 1 in both the accumulator and in the operand prior to the operation. During T6 the El state is concluded by setting the P state into the major state generator. Th is operation takes place because the instruction is not a JMS and since a break request is not present. If a break request is present, the break state is entered rather than the program count state. The P state is used to load the address of the next instruction into the MB from the program counter. During the entire P state, the MA is disabled so that the program counter is addressed. Since the AN D instruction is not a JMP instruction and is not a JMS instruction, the MB is cleared during Tl. During T2 and T3 the address of the next instruction is read from core memory at address 0000 and strobed into the MB. Since the skip flip-flop is in the 0 state (it was clear during T1 of the fetch state), the content of the MB is incremented by one to advance the program count to the address of the instruction to be performed next. During T5 and T6 this address is restored into the program counter at address 0000 of core memory, and the instruction register is cleared. During T6 the major state generator is set to the fetch state so that the new instruction is drawn from core memory during the following cycle at the address currently contained in the MB. Twos Complement Add (TAD) The TAD instruction is performed by a fetch, execute 1, and program count cycle normally, but can have a defer cycle interposed be1ween the fetch and execute 1 states to locate an indirectly addressed address of the operand. The fetch, defer, and program count cycles of this instruction perform operations identica I to those described previously for the AN D instruction. The operations performed during time states Tl, T2 ,and T3 of the El state are identical to the operations performed under the corresponding conditions of the AND instruction. 5-7 During the T4 state of the El cycle of the TAD instruction, the 2 1s complement add operation is performed by executing a half add beiween the content of the MB and the content of the AC. During T5 the AC carry chain is enabled, and the carry pulses are propagated during T6. The operand is restored in core memory during T5 and T6, and a new state is set into the major state generator at T6 time. This new state is the program count state unless a break request has been made, in which case the break state is entered following expiration of the El state. Index and Skip If Zero (lSZ) The ISZ instruction is performed in three cycles consisting of a fetch, execute 1, and program count. If the address of the operand must be determ ined indirectly, a defer state is executed beiween the fetch and the execute 1 state. The ISZ instruction is performed exactly as specified for the AND instruction during the fetch, defer, and program count states and during time states Tl, T2, and T3 of the execute 1 state. During time state T4 of the E1 cycle, the content of the MB is incremented by one and the MB carry is enabled. If the most significant bit of the MB changes from the 1 to the 0 state as a resu It of the carry be ing propaga ted through the register, the skip flip-flop is complemented (to set it since it was cleared during T1 of the fetch cyc Ie). The skip fl ip-flop is complemented only when the MB carry signa I ripples through the entire register to change the contents of the register from -1 to O. During T5 and T6 the operand is restored in core memory, and during T6 the El state expires and is replaced by the P state. The program count" state of the ISZ instruction performs functions identical to those described for the P cycle during execution of the AND instruction except that the sensing of the skip fl ip-flop increments the content of the MB by iwo if the skip coniditions are satisfied (the content of the MB changed from 7777 to 0000 when incremented by one) so that the program count is incremented to skip one instruction. Deposit and Clear Accumulator (DCA) Information contained in the AC is deposited in a core memory register specified in a DCA instruction by performance of a fetch, execute I, program count cycle, and possibly by a defer cycle beiween the fetch and execute 1 if the instruction designates indirect addressing. The functions performed by the fetch, defer, program count states, and during time state T1 of the El state are identica I to the functions performed during correspondi ng cyc les and times of the AN D instruction. 5-8 During T3 of the E1 state the Memory Strobe signal is inhibited so that the MB is settled to receive the new information, the content of the AC is jam transferred into the MB, and the AC is cleared. The MB carry path is disabled from T2 to T5 times to prevent carry pulses from setting adjacent flip-flops if a flip-flop containing a 1 is cleared by the transfer of AC information into the MB. During T5 and T6 the information in the MB is written in the specified core memory register to complete execution of the deposit and clear accumulator operation. During T6 the execute 1 state expires and the program count state is entered to locate the address of the next instruction to be performed. Jump to Subroutine (JMS) The JMS is the most compl icated instruction performed by the PDP-5. Th is instruction is performed to store the current program count in a spec ified address and to transfer program control t() the first instruction of a subroutine as contained in the specified address +1. Exit from this subroutine is normally executed by a jump to the specified address which is performed as the fina I instruction of the subroutine. Th is JMP instruction transfers program control to the instruction contained in the specified address of the JMS instruction and thus continues the main program with the instruction following the JMS. The JMS is performed by a fetch cycle in wh ich the instruction is brought from memory and placed in the MB and the IR, a defer cycle to locate the effective address if indirect addressing is specified, an execute 1 cycle performed to load the effective address into the MA and to load the MB with the program count, an execute 2 state to increment the program count contained in the MB and to store this incremented PC in the designated core memory address, and a program count state in which the specified core memory address is transferred into the MB to be used as the starting program count for the subroutine. The functions performed during the fetch and defer states of the JMS instruction are identical to those performed during the AND instruction. During the execute 1 state of the JMS instruction, the address of the operand is set into the MA as a function of the conditions of bits 3 and 4 of the IR in the same manner that these operations occur during the AN D instruction. Also during this time state, the MB is cleared and the MA is disabled in preparation for reading the program count from core memory during time states T2 and T3. After the program count is read into the MB it is restored in core memory and the rna ior state is transferred to E2 dur ing T6. 5-9 Assuming there is no program interrupt, the E2 state is used to increment the program count stored in the MS and to store this incremented program count in the core memory address spec ified in the instruction. This is accomplished by inhibiting generation of the Memory Strobe signal so that the program count in the MS (obta ined during the El state) is not disturbed. Then the content of the MS is incremented by one during T4 and written into core memory during I T5 and T6. Also during T6 the E2 state expires and the program count state is set. The P state is entered with the specified address in the MA and with the incremented program count in the MS. During T1 the 12-bit absolute address containing the program count is jam transferred into the MS. The Memory Strobe signal is inhibited during T3 so that the program count in ,the MS is not disturbed. During T4 the program count is incremented by one so that the MB now contains the starting address of the subroutine to be retrieved from core memory during the following fetch state. In preparation for the fetch state the IR is cleared during T5 and the fetch state is set during T6. Jump (JMP) The JMP instruction is used _to transfer program control to an address spec ified in the instruction. This operation is performed by a fetch cycle. If indirect addressing is indicated, a defer cycle is employed, and the instruction is completed by a program count cycle. The fetch and defer cycles perform functions identical to those performed during execution of the AND instruction. The fetch state is used to load the MS with the instruction spec ified by the program count and the defer state is used to locate the effective address. The program count state is entered from the defer statewitha 12-bitabsolute effective address contained in the MS. Since this address is to be taken as the program count for the succeeding instruction, no operations occur during the P state until T4. The programcountstateis entered from the fetch state with the instruction in the MB and with the current program count in the MA. The content of the MA is modified to form the new program count dur ing T1. Th is address mod ifica tion is effec ted as a func tion of the content of bit 4 of the instruction. If bit 4containsa 0, bitsO through 4 of the MB are cleared. Ifbit 4 contains a 1, bits 0 through 40f the MB are jam-set to correspond with bits 0 through 40f the MS. In any eventat the end of Tl the new program count is contained in the MB. Therefore, no program count need be drawn from core memory, so generation of the Memory Strobe pulse is inhibited. No incrementing is performed as a func tion of the skip fl ip-flop. As in program count cyc les the program count contained in the MB is written i'nto core memory address 0000 during 5-10 time states T5 and T6, the IR is cleared during T5, and the fetch state is set during T6. This operation is terminated with the new program count contained in the MB and in the PC. ~ut/Output Transfer (lOT) The lOT instruction is an augmented instruction which can be microprogrammed to address one of 64 devices and supply from one to three time pulses to initiate I/O device operations. During this instruction the processor generates lOP pu Ises during time states T4, T5, and T6 and supplies them to the device selectors of each peripheral device. The content of bits 3 through 8 of the instruction is used as a device select code that is made directly available to the device selector of all peripheral equipment. When a device selector is enabled by its specific select code, lOP pulses gate generation of correspondingly numbered lOT pulses as a function of binary ones in bits 11, 10, and 9 of the instruction. The lOT pulses, in turn, initiate appropriate operations. The lOT instruction is performed by a fetch cyc Ie followed by a program count cycle. The fetch state of the lOT instruction is entered with the program count contained in the MB. During time state T1 the program count is transferred from the content of the MB into the MA, the MB is cleared, and the skip flip-flop is cleared. During T2 and T3 the content of the core memory register spec ified by the program count is read into the MB so that the MB now conta ins the lOT instruction to be executed. Assum ing that no program interrupt occurs, bits 0 through 4 of the MB are transferred into the IR and the instruction is executed during T4, T5, and T6 of the current cycle by generating lOP 1, lOP 2, and lOP 4 pulses respectively. During T5 and T6 the instruction is restored in memory for future use. During T6 the fetch state is concluded by setting the major state generator to the program count state. The functions performed during the program count state of an lOT instruction are identcial to the functions performed during the corresponding state of the AND instruction. As described previously, the program count state disables the MA, clears the MB, and reads the address of the forthcoming instruction from the program counter at locations 0000 into the MB. The P state is concluded by clearing the IR in preparation for receiving the new instruction and setting the fetch state. 5-11 Operate (OPR) The OPR augmented instruction decodes the content of bits 4 through 11 of the instruction in two ways, determined by the content of bit 3. If bit 3 contains a 0, bits 4 through 11 are de- coded as an operate group 1 microinstruction; and if bit 3 conta ins a 1, bits 4 through 11 are decoded as a group 2 operate microinstruction. The decoding of these bits in both operate groups is clearly indicated in Figure 1-3. The instruction is executed during a fetch and a program count state. The fetch state is used to load the instruction into the MB from core memory and to perform the operations specified by bits 4 through 11. The program count state is used to locate the address of the next instruction to be performed in the manner described for the AND instruction. The functions performed during time states T1, T2, and T3 of the fetch state of the OPR instruction are exactly the same as those performed during any of the instructions described previously. The functions performed during time states T4 and T5 are different from other instructions and can be separated into the two classes as a function of the content of bit 3 of the i.nstruction. If bit 3 contains a 0, an OPR 1 microinstruction is indicated, and bits 4 through 11 are decoded as follows: a. If bit 4 is a 1, the AC is cleared during T4 (CLA). b. If bit 5 contains a 1, the Iink is cleared during T4 (C LL). c. If bit 6 contains a 1, the content of each bit of the AC is complemented during T5 (CMA). d. If bit 7 conta ins a 1, the Iink fl ip-flop is complemented during T5 (CML). e. If bit 8 contains a 1, the content of the AC and the L is rotated one posi- tion to the right during T5 (RAR). f. If bit 9 contains a 1, the content of the AC and the L is rotated to the left one position during T5 (RAL). g. If bits 8 and 10 both contain ones, the content of the AC and L is rotated one addHional place to the right during time state T1 of the following cycle (RTR) . h. If bits 9 and 10 both conta in ones, the content of the AC and L is rotate an additional position to the left during time state T1 of the following cycle (RTL) . 5-12 I. If bit 11 contains a I, the content of the AC is incremented by one during time state Tl of the ensuing cyc Ie (lAC). If the instruction contains a 1 in bit 3, an OPR 2 microinstruction is indicated, and bits 4 through 9 are decoded as follows: a. If bit 4 contains a I, the content of the AC is cleared during T4 (CLA). b. If bit 5 contains a I, the skip fl ip-flop is complemented (set since the flip-flop is cleared during Tl of the fetch state) during T4 if AC contains O a I, indicating that the accumulator contains a 2 1s complement negative number (SMA). c. If bit 6 contains a I, the skip fl ip-flop is complemented during T4 if each bit of the AC contains a d. a (SZA). If bit 7 contains a I, the skip fl ip-flop is complemented during T4 if the link contains a 1 (SNL). e. If bit 8 conta ins a 1, the skip fl ip-flop is complemented during T5 to reverse the sense of skipping for microinstructions containing ones in bits 5 through 7. f. If bit 9 contains a 1, the content of the switch register is transferred into the accumulator during T5 (OSR). g. If bit 10 contains a 1, the run flip-flop is cleared during T5 (HLT). During time state T6 the fetch state expires and the major state generator is set to the P state. However, ifa Break Request signal is present, the fetch state is followed by a break state. Therefore, the operations performed by the OPR 1 microinstructions having binary ones in bits 8 through 11 are normally performed during the P state but might also be performed during a break sta te . Program Interrupt Peripheral equipment connected to the program interrupt bus can cause an unscheduled JMS instruction to be executed during the running of the main program. Program interrupts initiated by grounding of the program interrupt bus allow the instruction in process at the time to be completely executed; then a JMS to address 0001 instruction is forced so that the current program count is stored at location 0001 and program control is transferred to 0002. 5-13 The instruction stored in core memory address 0002 is executed next as the first instruction of a program interrupt subroutine. The program interrupt subroutine is responsible for finding the peripheral equipment causing the interrupt, performing any necessary service to the I/O device, enabling the program interrupt synchronization element for another program interrupt, and returning to the original program. Enabling of the program interrupt synchronization element is accomplished by an ION microinstruction (lOT 6001), and exit from the subroutine back to the original program can be accomplished by a JMP I 1 instruction. This mode of operation is used to expedite the transfer of information to I/O devices by allowing alarm conditions to be checked by a subroutine initiated by them rather than by a program which checks them periodically. If the program interrupt synchronization element is enabled by prior performance of the ION microinstruction (lOT 6001) and a peripheral device supplies a program interrupt request, the program interrupt synchronization element generates the Interrupt Acknowledge signal. Generation of the ~nterrupt Acknowledge signal immediately clears the interrupt synchronization element by automatically performing the operations accomplished by the 10F microinstruction (lOT 6002) so that no additional interrupt requests are honored during the interrupt subroutine (unti I an ION microinstruction is performed). Generation of the Interrupt Acknowledge signal is delayed so that the interrupt does not occur until T5 of the next P state of the program in progress at the time the request is received. Therefore, the program count is the only factor that must be saved to reinstitute the main program following completion of the program interrupt subroutine. All operations performed during the P state prior to the interrupt are normal for the execution of instructions. During T1 of the following fetch state, the program count is transferred from the MB into the MA, and the MB and skip fl ip-flop are cleared. The norma I instruction is drawn from core memory and stored in the MB during T2 and T3; however, transfer of this instruction into the IR is inh ibited, and IRa is set to force a JMS instruction. The instruction drawn from memory during T2 and T3 is rewritten during T5 and T6, and the major state generator is set to the execute 1 state during T6 (since 1R3 contains a a as a result of clearing during T5 of the previous P state). During the El state the MA and MB are cleared, and the MA is disabled during Tl. During T2 and T3 the program count is read from core memory into the MB and is rewritten during T5 and T6. During T6 the major state generator is set to the execute 2 state. 5-14 During Tl of the E2 state the MA is incremented by one to establ ish address 0001. The Memory Strobe pulse is inhibited during the core memory read cycle, and the program count contained in the MB is written into address 0001 during T5 and T6. During T6 the int ack flip-flop of the program interrupt synchronization element is cleared and the major state generator is set to the P state. During the program count state address 0001 is transferred from the MA into the MB during Tl . Memory Strobe pulse generation is inhibited during T3 so that no core memory reading operation takes place. During T4 the content of the MB is incremented by one {since the skip fl ipflop has remained cleared since Tl of the previous fetch state} so that it now contains address 0002 which serves as the program count for the succeeding fetch state. The IR is cleared at T5 and the major state generator is set to the fetch state during T6 to complete the operations of the program count cycle and the program interrupt mode. Exit from this mode leaves a program count of 0002 in the MB for transferring to the MA during Tl of the succeeding fetch cycle to transfer program control to that address, and the current program count is stored in core memory register 0001 to provide a return to the original program at the conclusion of the subroutine. Data Break One external device can be connected directly to the data break facility or up to four devices can be connected to it through the Type 129 Data Channel Multiplexer. Peripheral equipment connected to the data break facility can cause a pause in the program in progress to transfer information between the device and core memory, via the MB. Th is mode of operation provides a high speed transfer of blocks of information at sequential core memory addresses or at addresses individually specified by the device. Since program execution is not involved in these transfers, the program counter is not disturbed or involved in these transfers. The program is merely suspended at the conclusion of an instruction execution, and the break state is entered to perform the transfer; then the program count state is entered to continue the main program. The timing of signals involved in a data break is indicated in Figure 5-1 . To initiate a data break, an I/O device must supply three signals simultaneously to the data break facility. These signals are the Break Request, which sets a flip-flop in the major state generator to control entry into the break state; a Transfer Direction signal, suppl ied to the MB 5-15 T4 BREAK REQUEST T!I T6 REQ REQ OUT TRANSFER DIRECTION IN T2 T!I T6 T2 T 1 T3 T4 T5 T6 ~------------------------------------------------------_ - - - - , . . . - - - - M U S T BE SET BEFORE T2 Yf- I o o BREAK STATE o CHANGE ADDRESS I .......-- MUST BE AVAILABLE AT LEAST lJ.nec BEfORE T 1 I B SET OCCURS AT THE DATA ADDRESS ~MA AND ADDRESS = iNCREMENT REQ 1\ B STATE 1\ I Lr:.. I o------~I -3 DATA- MB o FIRST T6 FOLLOWING BREAK REQUEST _______rl-: ~~~EPTED -3 DATA TO MB T4 T3 _J -.... ADDRESS TO MA Tl I COMPUTER TIME 1.-1 rr;+ • 1 - MA = INCREMENT "EQ 1\ TP 1 _ MUST BE AVAILABLE AT LEAST 1.ulec BEFORE T3 ~I__________________~ - - - f G - - -nl.J- MUST BE AVAILABLE AT I LEAST 1 sec BEFORE T1 TO INCREMEN ______________________ _ ~=-A INCREMENT REQUEST REQ MUST NOT OCCUR UNTIL WELL AFTER Tl PULSE HAS SETTLED IN CYCLE WHICH SPECIFIES ADDRESS --~L-________..J Figure 5-1 Data Break Tim ing control element to allow generation of the Data-.MB signal which strobes data into the MB from the peripheral equipment and inhibits generation of the Memory Strobe pulse; and an address of the transfer which is supplied to the gating circuits at the input of the MA. When the break request is made, the break state is set into the major state generator prior to entry into the program count state of an instruction. Therefore, the break state is entered at the conclusion of the execute 1 state of all memory reference instructions and at the conclusion of a fetch state for augmented instructions. Having establ ished the break state, each mach ine cycle is a break cycle until all data transfers have taken place, as indicated by removal of the Break Request signal by the peripheral equipment. Each computer cycle can be used to transfer a data word at addresses specified to the input gating circuits of the MA by the peripheral equipment or can be specified initially by the peripheral equipment and then occur at sequential addresses by application of an Increment Request signal to the MA control element. This signal allows generation of the Count MA signal to increment the content of the MA during T1 of each break cycle. Entry into the break cycle is indicated to the peripheral equipment by means of an Address Accepted pulse so that the device can initiate internal operations involved in the 5-16 transfer and supply data to the input gating circuits of the MB. The Address Accepted pulse supplied to the external device is designated the Data Address ~MA pulse within the PDP-5. Data is strobed into the MB by a Data - - . MB signa I produced during time state T3. The operations performed during each computer cycle in the break state are shown on the engineering flow diagram. During Tl the data supplied to the gating circuits at the input of the MA is strobed into the MA if the Increment Request signal is not present, or the content of the MA is incremented by one if the Increment Request signal is supplied by the external device. Also during T1 the MB is cleared in preparation for receipt of data from either the core memory or the external device. If the Transfer Direction signal establishes the transfer direction as out of the computer, the content of the core memory register at the address spec ified during T1 is transferred into the MB during time states T2 and T3 and is immediately available for strobing by the peripheral equipment. If the Transfer Direction signal specifies a data direction into the PDP-5, generation of the Memory Strobe signal is inhibited and the Data ---.....MB signal is generated to transfer information into the MB from signals supplied by the peripheral equipment. Data read from core memory during T2 and T3 is restored in core memory or the data set inf'o the MB during T3 is stored in core memory during T5 and T6. The Break Request signal is sampled again at T6 to determine if additional break cycles are needed. If the Break Request signal is still present, the BSet signal is produced to maintain the break state of the major state generator. If the Break Request signal is not present at this time, the program count state is set into the major state generator to complete the data break operation. 5-17 SECTION 6 INTERFACE All logic signals which pass between the PDP-5 computer and the input/output equipment are standard DEC levels or standard DEC pulses. A standard DEC level is either ground potential (0.0 "to - 0.3 volts) or - 3 volts (- 3.0 to - 4.0 volts). Standard DEC pulses are 2.5 volts in amplitude (2.3 to 3.0 volts) and are referenced to ground potential. The standard pulse duration is 70 nanoseconds for pulses originating in Series 1000 modules and 400 nanoseconds for Series 4000 modules. Three 50-terminal Amphenol 115-1145 cable connectors are available on the connector panel (1 J01-1 J03) for connection to I/O devices. Interface connections to 1J01 and 1J02 are used in normal programmed information transfers between the PDP-5 and peripheral equipment. Connections to 1 J03 are used for data and control signals transferred in the data break mode. Corresponding terminals of 1J01 and 1J02 are connected together and routed to signal origins or destinations in the machine logic. Additional connector locations (1 J04-1 J06) are available for installation of connectors, as needed. Wiring to a new signal connector can be planned for bus connection to either 1J02 or 1J03, so direct connection to the logic is not necessary. It is suggested that bus connections be made from all terminals of existing connectors to all terminals (used and unused in the device being added) of new connectors. In this manner the bus connections can be maintained for all future expansions of the system. Connections to the interface connectors are summarized in Table 6-1 for input signals and in Table 6-2 for output signals. 6-1 TABLE 6-1 Signal 1 0 1 AC 1 1 AC 2 1 AC 3 1 AC 4 1 AC 5 1 AC 6 1 AC 7 1 AC 8 1 AC 9 1 AC 10 1 AC 11 AC 0I I'\) Symbol INPUT SIGNALS Connector Terminals Programmed Data Break 1 Dest i nat ion Logic BS Drawing ---;> 1J01-13 1E16E 1M 14 --t> 1J01-14 1E16F 1M 14 --t> 1J01-15 1E16H 1M 14 ---t> 1J01-16 1E16J 1M 14 --t> 1J01-17 1E16K 1M 14 ---t> 1J01-18 1E16L 1M 14 --t> 1J01-19 1E16M 1M 14 --t> 1J01-20 1E16N 1M 14 ---t> 1J01-21 1E16P 1M 14 ---t> 1J01-22 1E16R 1M 14 --t> 1J01-23 1E16S 1M 14 --t> 1JOl-24 1E16T 1M 14 Skip --t> 1J01-25 1D03E Sk i p Contro I 8 Prog. Interrupt --<> 1J01-26 1E04Y Prog. Inti pt Sync. 8 MB1 0 --<> IJ03-13 1B02V MB 9 TABLE 6-1 INPUT SIGNALS (continued) Connector Terminais Programmed Data Break I Destination Logic BS Drawing 1J03-14 1B03V MB 9 --<> 1J03-15 1B04V MB 9 MB1 3 --<> 1J03-16 1B05V MB 9 MB1 4 --<> 1J03-17 1B06V MB 9 MB1 5 --<> 1J03-1B 1B07V MB 9 MB1 6 ---<> lJ03-l9 1BOBV MB 9 MBl 7 --<> --<> --<> --<> --<> --<> ---<> --<> --<> --<> 1J03-20 1B09V MB 9 1J03-2l 1B10V MB 9 1J03-22 1B11 V MB 9 1J03-23 1B12V MB 9 1J03-24 1B13V MB 9 1J03-26 1B02R MA 9 1J03-27 1B03R MA 9 1J03-2B 1B04R MA 9 1J03-29 1B05R MA 9 1J03-30 1B06R MA 9 Signal Symbol MB1 1 ---<> MB1 2 I 0I w MBl B MBl 9 1 MB 10 1 MBll Data Addr. 0 Data Addr. 1 Data Addr. 2 Data Addr. 3 Data Addr. 4 TABLE 6-1 Signal 0I Connector Terminals Programmed Data Break I Destination Logic BS Drawing Data Addr. 5 -<> 1J03-31 1B07R MA 9 Data Addr. 6 -<> 1J03-32 1B08R MA 9 Data Addr. 7 -<> -<> 1J03-33 1B09R MA 9 1J03-34 1B1 OR MA 9 Data Addr. 8 ~ Symbol INPUT SIGNALS (continued) Data Addr. 9 -<> 1J03-35 1B11 R MA 9 Data Addr. 10 -<> -<> 1J03-36 1B12R MA 9 1J03-37 1B13R MA 9 MB 9 (sheet 2) Data Addr. 11 Increment MB ----i> 1J03-38 1B13X Break Request -<> 1J03-43 1D16X Major State Gen. 6 1J03-44 1C17S MB Control 7 1J03-45 2C11 F MA Control 7 Transfer Direction Increment Request .*• I/O Halt ---. 1JOl-46 1D12Y I/O Halt Control 5 Clear AC ----i> 1JOl-47 lC01 F AC Control . 8 Restart ----+ 1JOl-48 1E02W Run Control 5 ...L Ground 1JOl-50 1J03-50 * Into PDP-5 when - 3 volts, out of PDP-5 when ground. TABLE 6-2 Signal Symbol 1 0 1 AC 1 1 AC 2 1 AC 3 1 AC ---<> ---<> ---<> AC ~ 1 5 1 AC 6 1 AC 7 1 AC 8 1 AC 9 1 AC 10 1 AC ll AC 0-. I tTl MB1 0 MB1 1 MB1 2 ---<> ---<> ---<> ---<> ---<> --<> ---<> ---<> ---<> ---<> ---<> ---<> Connector Termina!s Programmed Data Break OUTPUT SIGNALS Bus Driver Output Origin logic BS Drawing lJ01-l 1F06l 1B02E AC 9 lJOl-2 1F06N lB03E AC 9 lJOl-3 1F06T 1B04E AC 9 lJOl-4 1F06R lB05E AC 9 lJOl-5 1F07l 1B06E AC 9 lJOl-6 1F07N 1B07E AC 9 lJOl-7 1F07T 1B08E AC 9 1JOl-8 1F07R 1B09E AC 9 1JOl-9 1F08l 1B1 OE AC 9 1J01-10 1F08N 1B11 E AC 9 1J01-11 1F08T 1B12E AC 9 lJOl-12 1F08R 1B13E AC 9 1J03-1 1F12l 1B02K MB 9 1J03-2 1F12N 1B03K MB 9 1J03-3 1F12T 1B04K MB 9 TABLE 6-2 0I 0- Connector Term i na Is Programmed Data Break Bus Driver Output Origin Logic 1F09L 1B05L MB 9 1F09N 1B05K MB 9 1F09T 1B06L MB 9 1F09R 1B06K MB 9 1Fl OL 1B07L MB 9 1F10N 1B07K MB 9 1F1 OT 1B08L MB 9 1Fl OR lB08K MB 9 1F11 L 1B09L MB 9 1F11 N 1B09K MB 9 1F11 T 1B1OL MB 9 1J08-9 1Fll R 1B1 OK MB 9 ---<> 1J03-1 0 1F13L 1B11 K MB 9 ---<> 1J03-11 1F13N 1B12K MB 9 ---<> lJ03-12 lF13T 1B13K MB 9 Signal Symbol O 3 ---<> lJOl-28 MBl 3 O MB 4 ---<> lJOl-27 ---<> lJOl-30 MBl 4 O MB 5 ---<> lJOl-29 ---<> lJOl-32 MBl 5 O MB 6 ---<> ---<> lJOl-31 1JOl-34 MBl 6 O MB 7 ---<> 1JOl-33 1JOl-36 MB1 7 O MB 8 ---<> ---<> ---<> lJOl-35 MB1 8 ---<> lJOl-37 MB1 9 1 MB 10 1 MB11 MB OUTPUT SIGNALS (continued) 1J03-4 1J03-5 1J03-6 1J03-7 1J03-8 1JOl-38 BS Drawing TABLE 6-2 Signal lOP 1** lOP 1 Symbol ---. lOP 2** lOP 2 ---. lOP 4** 1 Bus Driver Output Origin Logic BS Drawing 1JOl-39 1D25J lOP Pulse Gen. 6 1JOl-40 1D25H lOP Pulse Gen. 6 1JOl-41 1D25R lOP Pulse Gen. 6 1JOl-42 1D25P lOP Pulse Gen. 6 1JOl-43 1D25X lOP Pulse Gen. 6 6 lJOl-44 1D25W lOP Pulse Gen. 1MC Clock 1JOl-45 1C24V Timing Signal Gen. Power Clear --+ 1JOl-49 1J03-47 1E05E Power Clear Gen. 1J03-39 1C24S Timing Signal Gen. 17 1J03-40 1C24J Timing Signal Gen. 17 ().. '" Connector Terminals Data Break Programmed ---. ----. lOP 4 I OUTPUT SIGNALS {continued} TP 4 TP 5 Break Run SP 0 ---. ---. • • 17 5 1J03-41 1F12R 1D20T Major State Gen. 6 1J03-42 1F13R 1DOl U Run Control 5 ~ 1J03-46 1E06E SP Gen. 5 Data - - . MB ---t> 1J03-48 1C12N MB Control 7 Address Accepted ---t> 1J03-49 1C13F MA Control 7 Ground ...L 1JOl-50 1J03-50 **Ground side of pulse transformer secondary winding LOADING AND DRIVING DEFINITIONS The following definitions and rules serve as a useful guide in determining the driving capability of output signals and the load presented to input signals by the PDP-5. Base Load Base load is the current which mu~t be drawn from the base of a dc inverter to keep it saturated. In this condition the inverter circuit input terminal is at -3 volts, the emitter is at ground, and a nominal 1 milliampere of current flows through the 3000-ohm base resistor from ground. A 1500-ohm load resistor clamped at -3 volts can nominally accept 8 milliamperes, but tolerance considerations limit this number to 7 milliamperes. Thus, an inverter collector with a 1500-ohm clamped load can drive a maximum of 7 base loads. Pulse Load Pulse load is the load presented to the output of a pulse source by an inverter base in the same speed series, or by the direct set or clear input ofa flip-flop. Pulse amplifiers are usually limited to driving 16 pulse loads. This number should be decreased if the bases are widely separated physically, and can be increased to 18 if the bases are all physically close together. The series inductance and shunt capacity of connecting wires can make pulses at the end of a series of bases either large or small. Consequently, when driving nearly the maximum number of bases, the pulse amplitude should be carefully checked after installation. A terminating resistor in the 100-to-300 ohm range is desirable to reduce ringing on a heavily loaded pulse line. The loading on a pulse source is approximately the same when driving a base as a direct input to a flip-flop. One pulse source, of course, cannot drive both direct inputs of flip-flops and inverter bases because the direct inputs require DEC standard positive pulses and base inputs require DEC standard negative pulses. A pulse load is largely determined by the value of the speed-up capclc itor connected in parallel with the 3000-ohm base resistor. In the 4000 Series 500kc modules this capacitor is 680 pf; in 1000 Series 5mc modules it is 82 pf; and in 6000 Series 10 kc modu les it is 56 pf. 6-8 Pulsed Emitter Load Pulsed emitter load is the load applied to the collector of an inverter which drives the pulse input to a flip-flop, pulse amplifier, or delay. The pulse current passes through all of the inverters in series with the pulse input, and it should be assumed to be the load on each of the ser ies inverters. DC Emitter Load -------The load applied to the collector of an inverter driving a clamped load resistor is the dc emitter load. This load is also presented by the collector of an inverter which drives an emitter in an inverter network terminated by a clamped load resistor. Under these conditions, the collector of an inverter driving an emitter in a transistor gating network must also supply the base current leaving the succeeding inverters which are saturated. This current is small, but in complex networks it must be considered. An inverter in the DEC 1000 or 6000 Series modules can supply 15 milliamperes, and in the 4000 Series modules can supply 20 milliamperes. An inverter network can always be analyzed by assuming: a. that a short circuit exists between the emitter and collector when - 3 volts is appl ied to the base. b. that 1 milliampere of base current will flow if either the collector or emitter is held at ground potential. c. that the maximum dc collector current through an inverter is 20 milliamperes for4000Series 500-kc modules and is 15 milliamperes· for all other DEC series modules. A capac itor-diode gate level input does not present any dc load. A transient load occurs when the input level changes. Note thatall capacitor-diode gates in the standard PDP-5 require that the level input precede the initiating pulse input by at least 1 microsecond. 6-9 POWER CLEAR GENERATOR (5) The Power Clear pulses generated and used within the PDP-5 are made available to both the programmed and data break interface connections. External equipment can make use of these pulses to clear registers and control logic during the power turn on period. Use of the Power Clear pulses in this manner is valid only when the logic circuits cleared by them are energized under the control of, or in synchronism with, the 832 Power Control in the PDP-5. The Power Clear pulses are DEC standard negative 0.4 microsecond pulses produced during the the first 5 to 10 seconds after the POWER switch is turned on. These pulses are generated at approximately a 500-kc rate by the 4401 Variable Clock module at location 1E05. Interface cable connections to the Power Clear pulses can drive 15 pulse loads. When an I/O device is mounted within the main PDP-5 cabinet or in cabinets bolted to it, the normal wiring practice is to use a single source of primary power and a single power control. When the I/O device is external to the PDP-5 and util izes a separate source of primary power, a separate cable can be used to connect the power controls of the PDP-5 and the device. This connection can be made to allow contact operations in the computer power control to cause similar operations in the I/O device power control. Under these conditions an I/O device can make effective use of the Power Clear pulses. SPECIAL PULSE GENERATOR (5) AND TIMING SIGNAL GENERATOR (17) Four timing pulses used in the PDP-5 are supplied to I/O devices using the data break facility. These signals can be used to synchronize operations in external equipment with the computer. The l-mc clock, TP4, and TP5 pulses are produced by 4604 Pulse Amplifier modules, and the SPO pulse is produced by the 4410 Pulse Generator module at location 1E06. All of these signals are standard DEC negative 0.4-microsecond pulses. The 1-mc clock pulse output can drive 15 pulse loads; and the TP4, TP5, and SPO pulse outputs can each drive 5 pulse loads. RUN AND I/O HAL T CONTROL (5) Run The 1 output of the run flip-flop is supplied to external equipment using the data break. This signal is at - 3 volts when the computer is performing instructions, and is at grou nd potential 6-10 when the program is halted. Magnetic tape and DECtape equipment make use of this signal to stop transport motion when the PDP-5 halts, and thus prevent the tape from running off the end of a reel. The signal is routed to the interface connector via contacts of the dummy plug at location 1F13. With the dummy plug in the circuit, this signal can drive 1 base load. With the dummy plug replaced by a 1684 Bus Driver module this signal is capable of driving 15 5-mc base loads at 500 kc or 8 500-kc base loads at 500 kc or 15 500-kc base loads at lower frequenc ies. It can supply a maximum current of ± 15 mi" iamperes. I/O Halt and Restart The I/O halt fac iI ity provides a means of halting the advance of the program for an undetermined length of time while an I/O device executes a programmed operation. A specific lOT instruction is decoded in the device selector of an I/O equipment to produce lOT pulses which initiate device operation and return to the PDP-5 as an I/O Halt pulse. The I/O Halt pulse sets the I/O-hit flip-flop, which in turn clears the run flip-flop, so that the program stops. When the I/O device completes the operation specified by the lOT instruction, it supplies a Restart pulse to the PDP-5 which returns the run flip-flop to the 1 state to continue the program and clears the I/O-hit flip-flop. I/O Halt pulses are received by a 4116 Diode module at location 1 D12 which functions as a negative NOR gate. When it is at ground potential, the inverted output of this gate sets the I/O-hit flip-flop. This flip-flop is contained in the 4215 module at location 1 DOl. When the I/O-hit flip-flop is set, the positive transition of the 1 output clears the run flip-flop. The run flip-flop is also contained in the module at location 1 DOl. I/O Halt pulses must be standard DEC negative pulses {0.4 microseconds} or equivalent. The dc load presented to the signal by the input is 1/8 dc emitter load. This load is shared by those inputs which are at ground. The transient load presented to a pulse input is 1 pulse load. Restart pulses are received at the pulse input ofa 4129 {negative} Capacitor-Diode Gate at location 1E02 and at the 4116 Diode module at location 1D12. The conditioning level input to this capacitor-diode gate is provided by the 1 status of the I/O-hit flip-flop. The Restart pulse may be driven from a standard DEC 0.4 microsecond negative pulse, or equivalent 6-11 source having a negative-going level change from 2.5 to 3.3 volts, with a maximum fall time of 0.4 microseconds. This input represents 3 pulse loads and 1/8 dc emitter load. MAJOR STATE GENERATOR (6) Break Request The break state is entered to transfer information between a peripheral device and the core memory via the memory buffer register. This state is entered only after a ground-level Break Request signal is supplied to the computer by the external device. The signal is buffer inverted and supplied to one input of a 2-input negative NAND diode gate in the 4113 module at location 1 D15. The second input to this gate is the TP4 pulse that strobes the Break Request signal into a synchronizing flip-flop. This flip-flop is cleared during T3 of each cycle so the Break Request signal must be present during T4 of the cyc Ie in which the break state is entered. Entry into the break state occurs during T6 of the cycle preceding the program count cyc Ie of the instruction in progress when the Break Request signal is present. The major state generator presents one base load to the Break Request signal source. Break When the compu'ter is in the break state, a negative signal level is supplied to external devices. This signal is at -3 volts when the computer is in the break state and is often logically combined with a timing pulse to initiate operations in an I/O device. Generated in diode gate circuits, this signal is suppl ied to the interface connector through the dummy plug at location 1F12. With the dummy plug in the circuit this signal can drive 1 base load. With the dummy plug replaced bya 1684 Bus Driver module, thesignal can supply ±15 milliamperes and can drive a load as described for the Run signal. MEMORY ADDRESS REG ISTER CONTROL (7) Address Accepted During T1 of each cycle during the break state, the PDP-5 produces a standard DEC positive pulse when the externally supplied address is strobed into the MA. The Address Accepted 6-12 pulse is produced by the same pulse amplifier circuit on the 4603 module at location 1C13 which triggers the input capacitor-diode gC?tes of the MA. This signal output can drive four pulse loads. Increment Request An Increment Request signal is use~ to determine the signa Is produced by the memory address register control element during each break cycle. Data Address If this signal is at ground potential, the J .... MA pulse is produced during T1 of the break state to strobe an address into the MA from signals supplied to it externally. If this signal is at - 3 volts, indicating a request to increment the transfer address by one, the MA Carry Enable signal is generated during the entire break cycle, and the Count MA pulse is produced during T1 to increment the content of the MA. If the address is to be suppl ied to the MA by an I/O device, the Increment Request signal should be at ground potential during computer time state Tl. If the address is to be incremented by one, the Increment Request signal must be at - 3 volts during and for appro)cimately 1 microsecond prior to T1. The signal is received as one input to a 2-input negative NAN D diode gate on the 4113 module at location 1Cll and by an inverter on the 4102 module at location lC16. The gate is conditioned by the Break signal to enable generation of the MA Carry Enable signal and the Count MA pulse. The inverter output is also suppi ied "to a 2-input negative NAN D diode gate conditioned by the Break signal. The output of this latter gate enables generation of the Data Address J .. MA pulse. The PDP-5 presents one base load to the Increment Request signal. MEMORY BUFFER REGISTER CONTROL (7) Transfer Direction A Transfer Direction signal must be supplied to the computer before and during computer time states T2 and T3 of a break state to determine the read or write status of the memory. At ground potential this signal designates transfer from the core memory to the I/O device, and at - 3 volts the signal spec ifies transfer into core memory from an external device. This signal must be at ground potential before T2 or no Memory Strobe pulse is produced and data cannot be transferred out of core memory. If the signal is at - 3 volts, the Data 6-13 .... MB pulse is produced during T3 and the data supplied to the MB inputs is strobed into the MB flip-flops. This Transfer Direction signal is received by one input of a 2-input negative NAND diode gate in the 4113 module at location 1C17. The second input to the gate is provided by the Break signal so that the direction signa I has effect only when the computer is in the Break state. Th is input presents 1/8 emitter load upon the Transfer Direction signal source. Data -----III-- M B During a data break in which the direction of transfer is into core memory, this pulse signal can be used as an indication that the data has been strobed into the MB, and the device register supplying the data can be changed. This signal is a standard DEC positive pulse of 0.4-microsecond duration, produced during computer time state T3 by the 4603 Pulse Amplifier module at location 1C12. Four pulse loads can be driven by this signal. ACCUMULATOR CONTROL (8) Clear AC Input connection to the PDP-5 is provided to allow a programmed I/O device to clear the accumu lator. An external device supplying information to the computer input mixer can assure that the word being read into the AC is not transferred in over an existing word by clearing the AC prior to strobing the 1M. Transferring a word into the AC from the 1M without clearing the AC first, results in the inc lusive OR of the new word with the previous word being held in the accumulator after the transfer. The Clear AC signal initiates operation of the 4606 Pulse Ampl ifier module at location 1COl by driving the input terminal to ground. A standard DEC positive pu Ise or a positive-going transition of from 2.5 to 4.0 volts, with a rise time less than . 0.4 microsecond and a duration greater than 70 nanoseconds, supplied to this input triggers the pulse amplifier. This connection presents one pulse load to the pulse source. Address Accepted During time state T1 of each break state cycle, the PDP-5 produces a standard DEC positive pulse when the address upplied externally is strobed into the MA. This Address Accepted pulse 6-14 is produced by the same pulse amplifier circuit on the 4603 Pulse Amplifier module at location 1C'I3 which triggers the input capacitor-diode gates of the MA. This signal output can drive four pulse loads. MEMORY ADDRESS REGISTER (9) Data Address signals suppl ied to the PDP-5 during data break operations to designate a transfer address condition a pair at ground-potential capacitor-diode gates at the input of each MA flip-flop. A Data Address signal is applied directly to the gate at the 1 input and is applied to the gate at the 0 input through an inverter, therefore providing a jam transfer. These gates require a 1 microsecond set up time and are triggered during computer tim~ state T1. Therefore, the Data Address signals must be supplied during T6 of the cycle preceding the break state. To assure this timing, these signals should be presented concurrent with the Break Request signal. Each Data Address connection presents one base load to the signal source in the I/O device. MEMORY BUFFER REGISTER (9) MB Outputs Bits 3 through 8 of an lOT instruction held in the MB are used to select the I/O device addressed by the instruction. Complementary output signals from fl ip-flops MB _ supply the 3 8 input to each device selector module. When the device selector is located within the I/O device, these MB Iines must be connected through an interface connector. During the data break, 12-bit words are transferred between core memory and an I/O device, via the MB. The binary 1 output of each MB flip-flop is available at the data break interface connector for these transfers. Memory buffer register outputs are wired from their point of origin in a 4206 Triple Flip-Flop module at locations 1 B02 through 1 B13 to module connectors at 1 F09 through 1 F13. Normally, locations 1 F09 through 1 F13 contain dummy plugs with jumpers between terminals corresponding to the inputs and outputs of a 1684 Bus Driver module. Therefore, when sufficient device selectors are added to the system or when a device which utilizes the data break draws sufficient current to overload the normal driving capabilities of the 4206 modules, these dummy plugs can be replaced by 1684 Bus Driver modules. Each 4206 output can drive four 4605 Pulse Amplifier 6-15 modules in device selectors. When the bus drivers are inserted in the system, each MB signal can drive at least 12 device selector modules, since a 1684 module can supply ±15 milliamperes, and each device selector module requires 1 .25 milliamperes shared among the grounded inputs. Under most circumstances, a single 1684 module output can drive more than 12 device selector modules because the load presented by a 4605 module is shared by all of the 1684 modules that drive it. The maximum number of 4605 modules which can be driven by 1684 modules is determined by the condition where the minimum number of driver circuits hold the maximum number of outputs at ground level. Under this condition, the current delivered by each driver circuit in a 1684 module is equal to 1.25 milliamperes multiplied by the number of loads, divided by the number of driver circuits. This current must not exceed 15 milliamperes per driver circuit. Data Bit Inputs Input connections to the MB are a Iso made at the data break interface connector. These connections are made to the Data Bit Ievel input of the ground-potential capac itor-diode gate in each 4206 module. Therefore, these inputs present no dc load. These gates require a 1-microsecond set-up time and are strobed during computer time state T3. Data Bit signals must, therefore, be present during T2 and T3. Increment MB A signal input connection is provided to allow an external device using the data break facility to increment the content of the MB. This connection is used in pulse-height analysis and time-of-flight applications. This signal triggers the ground-level capacitor-diode gate at the complement input to flip-flop MB11 if the gate has been conditioned for at least 1 microsecond by the MB Carry Enable signal level. Therefore, this gate is enabled during T2, T3, and T4 of each computer cyc Ie except the execute 1 state of the DCA instruction. The Increment MB signal input connection represents one emitter load. 6-16 ACCUMULATOR (9) AND INPUT MIXER (14) AC Outputs Datet contained in the AC is available as static levels to supply information to I/O devices. These static levels can be strobed into an I/O device register by lOT pulses from the associated device selector. The static output signal level of each AC fl ip-flop is at - 3 volts when the bit contains a binary 0 and ground potential when that bit contains a binary 1 • Accumulator outputs are wired from their point of origin in a 4206 Triple Flip-Flop module to c()nnectors at locations 1 F06, 07, and 08. Normally these locations contain dummy plugs which jumper terminals corresponding to the inputs and outputs of a 1685 Bus Driver module. When sufficient I/O devices are connected to the AC output to overload the 4206 modules, these dummy plugs can be removed and replaced by 1685 Bus Driver modules. With the dummy plugs in the system, each AC output signal is capable of driving six 1500-ohm capacitor-diode gate level inputs, or ten 5-mc base loads, or six 500-kc base loads, or two dc emitter loads. With the dummy plugs replaced by bus drivers, each AC output signal is capable of driving 100 1500-ohm capacitor-diode gate level inputs, or 15 base loads, or 12 negative NOR diode gates. Each driver circuit of a 1685 module can supply ±15 milliamperes. The rise and fall times of the output signals are approximately 1 microsecond. For more than a 5000-picofarad output 10adjT the maximum rise of fall time, in microseconds, is equal to the capacitance in picofarads divided by 5000. Maximum rise or fall time of a bus driver output should be limited to 10 microseconds. AC Inputs Data transferred from an I/O device to the PDP-5 is received at the input mixer and transferred to the accumulator input. The AC input is accessible to I/O devices only through a pulse input to the 4130 Capac itor-Diode Gate modules at locations 1E1 0 through 1E15 which comprise the 1M. The level input to these gates is permanently connected to system ground, and the pulse input is clamped at -3volts by the 1000 Clamped Load Resistor module at location 1E16. Therefore, gated register outputs from many I/O devices can be connected to the pulse inputs of the 1M, so that programmed lOT pulses set the information into the AC of the PDP-5. 6-17 Driving an 1M input connection point to ground potential sets a 1 into the corresponding AC flip-flop. The input signal change should be a maximum of 0.5 volts to avoid setting a flipflop to a 1, and must be at least 2 volts with a rise time of less than 0.3 microseconds to rei iably set a 1 into the AC. Each input presents a load of one standard clamped load resistor in parallel with 330 picofarads to ground. SKIP CONTROL (8) A skip bus is available for input connections to the PDP-5 from gated Skip pulses generated in I/O equipment. Input Skip pulses are usually produced by a flag or device status level which is strobed or sampled by an lOT pulse. The lOT pulse from the device selector strobes the flag; and if it is in the preselected binary condition, the instruction following the lOT is skipped. These input pulses provide the complement input to the skip flip-flop, which is one of the four circuits on the 4215 4-Bit Counter module at location 1D03. Within the computer, this point is clamped at -3 volts by the collector load resistor of a 4129 Negative Capacitor-Diode Gate at location 1C04. To cause an instruction to be skipped, the skip bus must be driven to ground potential for 0.4 microsecond by a pulse with a rise time of less than 0.2 microsecond. This pulse must originate in a high-impedance source, such as a transistor in a standard DEC inverter, diode gate, or capac itor-diode gate. The source of the Skip pulse cannot exhibit more than 1000 picofarads for the driving transistor. lOP PULSE GENERATOR (6) The lOP 1, 2, and 4 pulses trigger pulse ampl ifiers in the selected device selector located in peripheral equipment. These pulses are produced in a 4606 Pulse Amplifier module in location 1 D25 and are routed by twisted-wire pairs to the appropriate input terminals of all 4605 Pulse Amplifier modules in the PDP-5 system. Each lOP pulse can drive 16 pulse amplifiers in 4605 modu Ies • 6-18 PROGRAM INTERRUPT SYNCHRONIZATION (6) Signals from I/O devices which interrupt the program in progress are connected to a bus on the PDP-5. Connections to this bus must be in the form of static levels: ground potential to interrupt, .- 3 volts for no effect. The Program Interrupt signal is clamped at - 3 volts by the collector load of the 4114 Diode NOR module at location 1004, is inverted and isolated by the 4102 module at location 1 E04, and is supplied to one input of the 4115 Diode NAND module at location 1005 as the primary condition for initiating the internal interrupt gate. Connection to the program interrupt bus represents 1 dc emitter load. The maximum total leakage current from all sources connected to the bus must not exceed 6 milliamperes DEVICE SELECTOR (RS-4605) The device selector function is performed by a 4605 Pulse Amplifier module for each I/O device or external register which is individually selected. Each I/O device added to the system must contain a 4605 module which has been prepared to select the device for a given combination of bits 3 through 8 of an lOT microinstruction. When selected in this manner, a 4605 module produces lOT pulses (related to the lOP pulses) in accordance with the presence of binary ones in bits 9, 10, and 11 of the lOT microinstruction. These lOT pulses, in turn, must be wired to initiate operations in the I/O device or can be returned to the computer as I/O Skip, ~/O Halt, Restart, etc. signals. Cable connections must supply inputs to each 4605 module from both the 1 and 0 outputs of memory buffer register bits 3 through 8 (12 lines in 6 twisted pairs) and from the three lOP pulse generator outputs (6 lines in 3 twisted pairs). Connections are then made from the three output terminals of a 4605 module directly to the logic circuits of the I/O device or to the interface connector for return to the computer. The 4605 Pu Ise Ampl ifier modules are del ivered with jumper wires connecting each input of the 6-input negative NAND diode gate to both the 1 and 0 input terminals for the appropriate MB input signal. The user must remove one jumper from each of the six NAND gate inputs to establ ish the appropriate select code. (Both jumpers may be removed if the select code requires it, such as in the Type 154 Memory Extension Control option.) This system allows select codes to be changed in the module and not in cable connections. As delivered, these modules are 6-19 also wired to produce negative lOT pulses. Positive lOT pulses can be obtained by reversing both jumper wire connections of a pulse transformer secondary winding on a module printedwiring board. Note that the MB and lOP connections to the 4605 modules are fixed and cannot be modified to operate more than one pulse ampl ifier (per module) at the same time. Should an I/O device require coincident positive and negative lOT pulses, two separate 4605 modules must be used or an lOT pulse can be used to trigger external positive and negative pulse amplifiers. Note also that positive lOT pulses cannot be inverted to produce negative lOT pulses but can be used to trigger a negative pulse amplifier. Output pulses from a 4605 Pulse Amplifier are standard for the DEC 4000 Series systems modules (0.4 microsecond). Each output is capable of driving 16 pulse loads. 6-20 SECTION 7 INSTALLATION SITE PREPARATION Space must be provided at the installation site to accommodate the PDP-5 and all peripheral equipment and to allow freedom of access to all doors and panels for maintenance. In larger systems, consideration should be given to human engineering factors which minimize the effort required by an operator seated at the operator console to obtain visual or physical access to all controls, indicators, input bins, and output hoppers of all equipment in the system. A singl e-cabinet PDP-5 requires a floor space 30 inches wide and 45-1/16 inches deep with a minimum service clearance of 14-7/8 inches at the back. A dual cabinet PDP-5 requires a space 42 inches wide wi th the same depth and servi ce clearance, since the tabl e on a dualcabinet system does not extend beyond the end panels. Additional width of 19-3/4 inches is required for each additional computer cabinet which is bolted to the main frame or console cabinet. Figure 7-1 indicates the space requirements, cable access, and floor loading for a single-cabinet PDP-5. This diagram can also be used in planning the installation of all I/O equipment housed in standard DEC computer cabinets, real izing that other cabinets do not have the table at the front of the operator console and that 1-1/4 inch end panels are added to the side of each multiple-cabinet configuration constructed of 19-3/4 inch cabinets bolted together. The standard Teletype Automatic Send Receive set requires a floor space approximately 22-1/4 inches wide by 18-1/2 inches deep. Signal cable length restricts the location of the Teletype to within 18 inches of the side of the computer. No special environmental condition need be met for proper operation of the PDP-5. Ambient temperature at the installation site can vary between 50 and 104 degrees Fahrenheit (between 10 and 40 degrees centigrade) where the relative humidity varies between 0 and 90 percent with no adverse effect on computer operation. To extend the Iife expectancy of the system, it is recommended that the ambient temperature at the installation site be maintained between 68 and 86 degrees Fahrenheit (between 20 and 30 degrees centigrade) and that the relative humidity be held below 70 percent. During shipping or storing of the system, the ambient 7-1 temperature may vary between 32 and 104 degrees Fahrenheit (between 0 and 40 degrees centigrade) and the relative humidity should not be allowed to rise above 90 percent. Although all exposed surfaces of all DEC cabinets and hardware are treated to prevent corrosion, exposure of systems to cl imates where the relative humidity rises above 90 percent for long periods of time should be avoided to prevent rusting. FLOOR PLAN TOP VIEW CABLE ACCESS IL------..::~__ ...JI \ I II" ~----------T---50~ I 1 I I I I I REMOVABLE END PANEL I B~O~ 4~O ~171o~ II I I I I I I I I I I 4 I 32 I \ -I 4 I / I I I _________ l.. I I-L rLC I. 1\ J 1\ SWINGING PLENUM DOOR :=J 14--1~-30,,~~1 FRONT VIEW (DOORS REMOVED) I.-I SIDE VIEW I" IOo~ 114..- - - - - - 2 7 1 6 I 224" - -----1·-.11 LOGIC IA LOGIC IB LOGIC IC LOGIC 10 LOGIC IE I" LOGIC IF 6 9B OPERATOR CONSOLE I CONNECTOR PANEL I J 1" , [J4J 26, C:5l Ue:!I ~ 1- 16 Figure 7-1 Installation Outl ine Drawing 7-2 A source of l1S-volt (± 17 volts), 60-cycle (±O.S cycle), single-phase power capable of supplying at least 7.S amperes must be provided to operate a standard PDP-So To allow connection ,to the power cable of the computer, this source should be provided with a Hubbel 7310,B, or equivalent twist-lock flush receptacle rated at 20 amperes at 2S0 volts. Power dissipation of a standard PDP-S is approximately 780 watts, and the heat dissipation is approximately 2370 BTU/hour. Upon special request a PDP-S can be constructed to operate from a 220-volt (±33 volts), 60-cycle (±O.S cycle), single-phase power source or from a laO-volt (± lS volts), SO-cycl.e (±O.S cycle), single-phase power source. PREPARATION FOR SHIPMENT The following shipping practices are followed by the factory in preparing a system for del ivery to a customer and should be adhered to by the customer in any future shipment or relocation. Usually a shipment consists of at least three parcels containing the computer main frame, the Teletype, and a carton containing related documentation, cables, and other miscellaneous material. Shipping weightof a standard single-cabinet main frame is approximately 600 pounds, and is approximately 9S0 pounds for a dual-cabinet equipment. Shipping weight of the Teletype equipment is approximately 60 pounds, and the miscellaneous equipment carton weighs up to 100 pounds. The cabinet of a PDP-S system is prepared for shipment as follows: a. The cabinet is placed upon a sturdy wooden pallet and held in place by passing a machine screw through the center of the tubular frame on each side of the bottom of the cabinet and turning this screw securely to the pallet. b. The tabl e is removed from the cabinet by removing the two mounting screws which attach the table extension arms to the side of the cabinet at the back; then the screws are returned to their position in the cabinet. c. Modules are taped within the mounting panels and the power cables are coiled and taped to the floor of the cabinet. The plenum door is then bolted shut. 7-3 d. The table is cushioned by packing material and attached to the outside of the cabinet by metal straps. A wooden protector plate, wrapped in packing material, is strapped to the front of the cabinet to cover the operator console. e. A full-height plastic bag is placed over the entire cabinet. f. A wooden cover plate with appropriate packing material is placed on top of the cabinet and metal shipping straps are run vertically around the cabinet, over the cover plate, and under the pallet. When preparing the cabinet for overseas shipment, boards are nail ed between the cover plate and the pallet to form a shipping crate which totally encloses the cabinet. The Teletype is pClckaged in the original manufacturer's shipping carton and is prepared for shipment to the customer as follows: a. Having disconnected the Teletype from the computer cabinet, the copy- holder and chad box are removed. b. The back panel of the stand is removed, all cables are disconnected, and the power pack is removed. c. The Teletype console is removed from the stand and attached to a wooden pallet by four shipping screws. The pallet is then placed in the shipping carton and corrugated packing material is placed on all sides of the console. d. The stand is placed in the shipping carton above the Teletype console. The copyholder, chad box, and power pack are individually wrapped in shipping material and packed within the stand; then the back of the stand is attached by means of the two normal mounting screws. e. Additional packing material is added and the carton is sealed. 7-4 INSTALLATION PROCEDURE No special tools or equipment are required for installation of a PDP-5 system. A fork-lift truck or other pallet-handling equipment and normal hand tools, including shears to cut the shipping straps, should be available for receiving and installing the equipment. ,To install the computer: 1. Place the computer cabinet package within the installation site near the final location. Cut the shipping straps and remove all packing material. Remove the table from the side of the cabinet and remove the protector plate from the front of the cabinet. Open the rear doors, remove the shipping bolts which hold the plenum door closed, and open the plenum door. Remove the machine screw which holds each side of the cabinet to the pallet. Slide the cabinet off of the pallet, using a ramp (approximately 4-3/4 inches high) from the floor to the top of the pallet. Move the cabinet to its final location with in the installation site (this location must be within 18 feet of the pri mary power connector wi th in the si te) . 2. Remove the tape which holds the modules in place within the mounting panels and the tape which holds the power cables to the floor of the cabinet. Assure that all modules are securely mounted in their connectors. 3. Remove the machine screw from the table mounting guide at each side of the back of the cabinet; install the table by passing the extension arms through the openings in the front of the cabinet and into the guides at the back of the cabinet; then replace the machine screws by passing them through the extension arms and turning them into the captive nut in each guide. The table extension arms are shown installed in the guides in Figure 7-2. 7-5 Figure 7-2 Installation Connections 7-6 4. Open the Teletype carton and remove the packing material. Remove the back cover from the stand and remove and unwrap the copyho Ider, chad box, and power pack. Remove the stand from the shipping carton. Remove the Teletype console from the carton, holding it by means of the wooden pallet attached to the bottom. Remov.e the Teletype console from the pallet and mount it on the stand. Snap the power pack in place within the top front of the stand, and connect the Teletype console to the power pack (a 6-lead cable attached at the console is connected to the power pack by means of a white plastic Molex 1375 female connector which mates with a mal e output pi ug on the power pack). Pass the 3-wire power cable and the 7-conductor signal cable (which is terminated in a female Amphenol 143- 022- 04 connector) through the opening at the lower left hand corner of the Teletype stand; then replace the back cover of the stand by means of the two mounting screws. 5. Ad just the stabil iz ing feet on the four corners of the computer cabinet and on any I/O equipment. Adjust the level ing devices on the feet of the Teletype stand. 6. Remove the fan and fil ter assembl y from the bottom of the computer cabinet by disconnecting the captive screw at each side of the filter housing. SI ide the rear portion of the cable port towards the rear door. Pass the larger diameter computer power cable out through the cable port, pass the Teletype signal and power cables into the cabinet through the cable port, and pass any other I/O equipment signal cables through the cable port; then replace the back half of the cable port and the fan and filter assembly. The computer power cable, the Teletype power cable, and the Teletype signal cable are shown passing through the cable port in Figure 7-2. 7. Connect the 3-prong male connector of the Teletype power cable to the female connector at the end of the smaller diameter power cable within the computer cabinet. Connect the Amphenol 22-pin female connector of the 7-7 Teletype signal cable to the mating connector to the right of module mounting panel 1 F (as viewed from the inside of the cabinet). Connect all I/O device 50-pin cable connectors to the female interface connectors on connector panel 1 J, remembering that connectors 1JOl and 1J02 are used for normal programmed connections, and connector 1 J03 is used for data break signal connections. Assure that the lock switch is turned fully clockwise and tha't the POWER switch is set to the left position, then connect the computer power cable to the primary power source. 8. Turn the lock switch counterclockwise, set the POWER switch to the right position, and observe that the ad jacent i nd icator lights. 9. Install the printer paper in the Teletype printer/keyboard, and install a tape in the punch as described in the Teletype Technical Manual or as described in Section 8 of this manual. 10. Se"t the LINE/OFF/LOCAL switch on the front of the Teletype unit to either side position (for early Teletype units press the LCL pushbuttonindicator, and observe that the indicator lights). Press the punch ON push- button. Strike several keys and observe that the printer and punch operate. Set the LINE/OFF/LOCAL switch to the OFF position (or on early models press any of the pushbuttons adjacent to the LCL pushbutton-indicator, and observe that this latter indicator becomes extinguished). 11. Set the POWER switch to the left position, and observe that the ad jacent indicator becomes extinguished. This completes the installation of a standard PDP-5 system. Before commencing normal use, verify the operating capabi Iity of the system by performing the Power Supply Checks and perform the Marginal Checks while running all of the diagnostic (Maindec) programs as described under Preventive Maintenance in Section 9 of this manual. Be sure to enter the margins ob- tained during each of these programs in the maintenance log, since these levels are essential to determining rate of change in future preventive maintenance. 7-8 SECTION 8 OPERATION CONTROLS AND INDICATORS Manual control of the PDP-5 is exercised by means of keys and switches on the operator console. Visual indication of the machine status and the content of major registers and control flip-flops is also given on this console. Indicator lamps light to denote the presence of a binary 1 in specific register bits and in control flip-flops. The"function of these controls and indicators is listed in Table 8-1, and their location is shown in Figures 8-1 and 8-2. The function of all controls and indicators of the Model 33 ASR Teletype are described in Table 8-2, as they apply to operation of the computer. The Teletype console is shown in Figure 8-3. SINGl£ lNST pow£Jt Fi gure 8- 1 Standard Operator Conso Ie 8-1 MEMORY ADDRESS INSTRUCTION ./ ) / ~ } Figure 8-2 Operator Console with Type 153 Automatic Multiply and Divide, and Type 154 Memory Extension Control TABLE 8-1 OPERATOR CONSOLE CONTROLS AND INDICATORS Control or Ind icator Function MEMORY ADDRESS indicators Indi cate the C (MA). Usua Ily the C (MA) denotes the core memory address of the word currently or previ0usy read or written. After operation of either the DEPOSIT or EXAMINE key, the C(MA) indicates the core memory address to be selected for the next memory cycle. MEMORY BUFFER indicators Indicate the C(MB). Usually the C(MB) designates the word just read or written at the core memory address held in the MA. ACCUMULATOR indicators Indicate the C(AC). ARITHMETIC REGISTER indicators* Indicate the C(AR). The arithmetic register (AR) holds the most significant half of the product at the conclusion of multiplication, holds the most significant half of the dividend at the beginning of division, and holds the remainder at the conclusion of a divide operation. *Provided only on systems containing the Type 153 Automatic Multiply and Divide option. 8-2 TABLE 8-1 OPERATOR CONSOLE CONTROLS AND INDICATORS (continued) Control or Indicator Function MULTIPLIER QUOTIENT indicators* Indicate the C(MQ). The multiplier quotient (MQ) holds the mu Itipl ier at the beginn ing of a m!J Itipl ication operation and the least significant half of the product at the conclusion. It holds the least significant half of the divident at the start of a divide operation and at the end holds the quotient. AR LIN K indicator* Indicates the C (ARL). The arithmetic register I ink (ARL) is used as an extension of the AR and to indicate overflow to the control logic. SWITCH REGISTER switches Provide a means of manually setting a 12-bit word into the mach ine. Switches in the up position correspond to binary ones, down to zeros. The content of this register is loaded into the MA by the LOAD ADDRESS key, or into the MB and core memory by the DEPOSIT key. The C (SR) can be set into the AC under program control by means of the OSR instruction. INSTRUCTION indicators Indicate the C(lR), and so denote the operation code of the instruction currently being performed. RUN indicator Indicates the 1 status of the run fl ip-flop. When lit, the internal timing circuits are enabled and the machine performs instructions. IN-OUT HALT indicator Indicates the 1 status of the I/O-hit fl ip-flop when lit. An 1/ 0 dev ice programmed to use the I/O Ha It feature of the PDP-5 produces an I/O Halt pulse which sets the I/O-hit fl ip-flop when the device is initiated, and produces a Restart pulse which clears both the I/O-hit and run fl ip-flops when it has completed the programmed operation. When the I/O-hit fl ip-flop is set, it c Iears the run fl ip-flop to prevent program advance. LINK or AC LINK indicator Indicates the C(L). PROGRAM COUNTER, FETCH, EXECUTE, DEFER, BREAK indicators Indicate the primary control state of the machine and that the next memory cyc Ie wi II be a program count, fetch, execute 1 or 2, defer, or break cycle, respectively. *Provided only on systems containing the Type 153 Automatic Multiply and Divide option. 8-3 TABLE 8-1 OPERATOR CONSOLE CONTROLS AND INDICATORS (continued) Control or Indicator Function SINGLE STEP switch and indicator The switch is off in the left position. In the right position the switch causes the run fl ip-flop to be cleared during T6 to disable the timing circuits at the end of one cycle of operation. Thereafter, repeated operation of the CONTINUE key steps the program one cyc Ie at a time so that the content of registers can be observed in each state. The indicator lights to denote the single-step mode of operation. SINGLE INST switch and indica'tor The switch is off in the left position. In the right position the switch causes the run fl ip-flop to be cleared at the end of the next instruction execution. When the computer is started by means of the START or CONTINUE key, this switch causes the run flipflop to be cleared at the end of the last cycle of the current instruction (during T6 of the program count state). Therefore repeated operation of the CONTINUE key steps the program one instruction at a time. The indicator lights to denote the singleinstruction mode of operation. POWER switch and indicator In the left position this switch removes primary power from the computer, and in the right position it appl ies power. The indicator Iights to denote the energized condition. I NSTRUCT ION FIELD indicators and switches** The indicators denote the C(lF}, and the switches serve as an extension of the SR to load the IF by means of the LOAD ADDRESS key. The i.nstruction field register (IF) determines the core memory field from whic h instructions are to be taken. DAT A FIELD indicators and switches** The indicators denote the C(DF} and the switches serve as an extension of the SR to load the DF by means of the LOAD ADDRESS key. The data field register (DF) determines the core memory field of data storage and retrieval. LOAD ADDRESS key Lifting this key sets the C(SR} into the MA, sets the C(lNSTRUCTION FIELD switches} into the IF, and sets the C(DATA FIELD switches} into the DF. **Provided only on systems containing the Type 154 Memory Extension Control option. 8-4 TABLE 8-1 OPERATOR CONSOLE CONTROLS AND INDICATORS (continued) Control or Indicator Function START key Starts the computer program by turning off the program interrupt circuits, clearing the AC and L, setting the program count state, and forcing the instruction JMP to the address currently held by the MA. Therefore, the word stored at the address held by the MA is taken as the first instruction. DEPOSIT key Lifting this key sets the C(SR) into the MB and core memory at the a'ddress specified by the current C(MA). This operation is performed by setting the execute 2 state and forcing a DCA instruction. The C(MA) is then incremented by one, to allow storing of information in sequential memory addresses by repeated operation of the DEPOSIT key. EXAMINE key Pressing this key sets the content of core memory at the address specified by the C(MA) into the MB and AC. This operation is performed by clearing the AC, setting the execute 1 state, and forcing a TAD instruction. The C(MA) is then incremented by one to allo'w examination of the contents of sequential core memory addresses by repeated operation of the EXAMI NE key. STOP key Causes the run fl ip-flop to be cleared at the end (T6) of the cycle in progress at the time the key is lifted. CONTINUE key Pressing this key sets the run fl ip-flop to continue the program in the state designated by the I ighted console indicator at the instruction currently held in the PC. Lock switch With this switch turned clockwise, all keys and switches except the SWITCH REGISTER switches on the operator console are disabled. In this condition the power can not be turned off by the POWER switch, and the program can not be disturbed by inadvertent key operation. The program can, however, monitor the C(SR) by execution of the OSR instruction and can be modified accordingly by skip instructions. 8-5 Figure 8-3 TABLE 8-2 Teletype Console TELETYPE CONTROLS AND INDICATORS Control or Indicator Function REL. pushbutton Disengages the tape in the punch to allow tape removal or tape loading. B. SP. pushbutton Backspaces the tape in the punch by one space, allowing manual correction or rub out of the character just punched. OFF and ON pushbuttons Control use of the tape punch with operation of the Tel etype keyboard/ pr inter. 8-6 TABLE 8~2 TELETYPE CONTROLS AND INDICATORS {continued} Control or Indicator Function START/STOP/FREE switch Controls use of the tape reader with operation of the Teletype. In the lower FREE position the reader is disengaged and can be loaded or unloaded. In the center STOP position the reader mechanism is engaged but de-energized. In the upper START position the reader is engaged and operated under program control. Keyboard Provides a means of printing on paper in use as a typewriter and punching tape when the punch ON pushbutton is pressed, and provides a means of supplying input data to the computer when the LINE/OFF/LOCAL switch is in the LINE position {or in early machines when the ON LINE/LOCAL switch is in the ON LINE position} . LINE/OFF/LOCAL switch Controls appl ication of primary power in the Teletype and controls data connection to the processor. In the LINE position the Teletype is energized and connected as an I/O device of the co~puter. In the OFF position the Teletype is de-energized. In the LOCAL position the Teletype is energized for off-line operation, and signal connection to the processor is broken. Both line and local use of the Teletype require that the computer be energized through the POWER switch. ON LINE/LOCAL switch* Allows use of the Teletype as an input/output device of the computer in the ON LINE position or separate, off I ine use in the LOCAL position. Both on Iine and loca I use of the Tel etype requ ire that the computer POWER switch be in the on position. REST indicator* Not used. NORMAL RESTORE switch* Not used. Dial* Not used. LCL pushbutton-indicator* Power control wh ich energizes the Teletype with primary power from the computer when pressed. The indicator lights to signify the energized status of the Teletype. *These devices are provided on early PDP-5 systems due to unavailability of more appropriate Teletype equipment. In later systems these devices are replaced by a LINE/OFF/LOCAL switch. 8-7 TABLE 8-2 TELETYPE CONTROLS AND INDICATORS (continued) Contro I or Ind icator Function OR IG, C LR, AN S, TST, and BUZ-RLS pushbutton-indicators. Not used electrically but pressed to mechanically reset the LCL pushbutton indicator to de-energize the Teletype. VOL control* Not used. *These devices are provided on early PDP-5 systems due to unavai labil ity of more appropriate Teletype equipment. In later systems these devices are replaced by a LINE/OFF/LOCAL switch. OPERATING PROCEDURES Many means are available for loading and unloading PDP-5 information. The means used are, of course, dependent upon the form of the information, time Iimitations, and the peripheral equipment connected to the computer. The following procedures are basic to any use of the PDP-5, and although they may be used infrequently as the programming and use of the computer become more sophisticated, they are valuable in preparing the initial programs and learning the function of machine input and output transfers. Manual Data Storage and Modification Programs and data can be stored or modified manually by means of the fac iI ities on the operator console. Chief use of manual data storage is made to load the readin mode loader program into the computer core memory. The readin mode (RIM) loader is a program used to automatically load programs into PDP-5 from perforated tape in RIM format. This program and the RIM tape format are described in the PDP-5 handbook and in Digital Program Library descriptions. The RIM program is listed in Table 8-3 for rapid reference and can be used as an exercise in manual data storage. To store data manually in the PDP-5 core memory: 1. Turn the lock switch counterclockwise and set the POWER switch to the right. 8-8 2. Set the bit switches of the SWITCH REGISTER (SR) to correspond with the address bits of the first word to be stored. Lift the LOAD ADDRESS key and observe that the address set by the SR is held in the MA, as designated by lighted MEMORY ADDRESS indicators corresponding to switches in the 1 (up) position and unlighted indicators corresponding to switches in the 0 (down) position. 3. Set the SR to correspond with the data or instruction word to be stored at the address just set into the MA. Lift the DEPOSIT key and observe that the MB, and hence the core memory, hold the word set by the SR. Also, observe that the MA has been incremented by one so that additional data can be stored at sequential addresses by repeated SR setting and DEPOSIT key operation. TABLE 8-3 Address Content 700 701 702 703 704 705 706 707 710 711 712 713 714 715 716 717 720 6032 6031 5301 6036 7106 7006 7510 5301 7006 6031 5311 6034 7420 3720 3320 5300 READIN MODE LOADER PROGRAM Mnemonic BEG, KCC KSF JMP .-1 KRB eLL RTL RTL SPA JMP BEG +1 RTL KSF JMP .-1 KRS SNL DCA I TEMP DCA TEMP JMP BEG TEMP, 8-9 Comments CLEAR AC AND FLAG SKIP IF FLAG = 1 LOOKING FOR CHAR READ BUFFER CH 8 IN ACO CHECKING FOR LEADER FOUND LEADER OK, CH 7 IN LINK READ, DO NOT CLEAR CHECKING FOR ADDRESS STORE CONTENTS STORE ADDRESS NEXT WORD TEMP STORAGE To check the content of an address in core memory, set the address into the MA as in step 2, then press the EXAMINE key. The content of the address is then designated by the MEMORY BUFFER indicators. The content of the MA is incremented by one with operation of the EXAMINE key, so the content of sequential addresses can be examined by repeated operation of the key after the original {or starting} address is loaded. The content of any address can be modified by repeating both steps 2 and 3. Loading Data Under Program Control Information can be stored or modified in the computer automatically on Iy by enacting programs previously stored in core memory. For example, having the RIM loader stored in core memory allows RIM format tapes to be loaded as follows: 1. Turn the lock switch counterc lockwise and set the POWER switch to the right. 2. Set the Teletype LINE/OFF/LOCAL switch to the LINE position. 3. Load the tape in the Teletype reader by setting the START/STOP/FREE switch to the FREE position, releasing the cover guard by means of the latch at the right, loading the tape so that the sprocket wheel teeth engage the feed holes in the tape, c losing the cover guard, and setting the switch to the STOP position. Tape is loaded in the back of the reader so that it moves toward the front as it is read. Proper positioning of the tape in the reader finds three bit positions being sensed to the left of the sprocket wheel and five bit positions being sensed to the right of the sprocket wheel. 4. Load the starting address of the R1M loader program {not the address of the program to be loaded} into the MA by means of the SR and the LOAD ADDRESS key. 5. Press the computer START key and set the 3-position Teletype reader switch to the START position. The tape will be read automatically. The program contained on the tape mightbe initializedand started automatically 8-10 because some tapes in RIM format are concluded with address 0000 and a data word equal to one less than the starting address of the program just read. Therefore, after the last tape character is read, the program starting address is taken by the program counter as the address of the next instruction to be executed. Automatic storing of the binary loader (BIN) program is performed by means of the RIM loader program as previously described. With the BIN loader stored in core memory, program tapes in the program assembly language (PAL) binary format can be stored as described in the previous procedure except that the starting address of the BIN loader (1777 or 7777 depending on the size of core memory) is used in step 4. When storing a program in th is manner, the computer stops and the AC should contain all zeros if the program is stored properly. If the computer stops with a number other than zero in the AC, a checksum error has been detected; so the program has been stored incorrectly, and the storage procedure should be repeated. When the program has been stored correct Iy, it can be in itiated by loading the program starting address (usually designated on the leader of the tape) into the MA by means of the SR and LOAD ADDRESS key, then pressing the START key. Off-Line Teletype Operation The Teletype can be used separately from the PDP-5 for typing, punching tape, or duplicating tapes. To use the Teletype in this manner: 1. Assure that the computer lock switch is turned counterclockwise and set the POWER switch to the right. 2. Set the Teletype LINE/OFF/LOCAL switch to the LOCAL position. 3. If the punch is to be used, load it by raising the cover, manually feeding the tape from the top of the roll into the guide at the back of the punch, advancing the tape through the punch by manua lIy turn ing the friction wheel, and then c losing the cover. Energize the punch by pressing the ON pushbutton, and produce about two feet of leader. The leader-trailer can be code 200 or 377. To produce the code 200 leader, simultaneously press 8-11 and hold the CTRL and SH 1FT keys with the left hand; press and hold the REPT key; press and release the @ key; when the required amount of leader has been punched release all keys. To produce the 377 code, simultaneously press and hold both the REPT and RUB OUT keys until a suffic ient amount of Ieader has been punc hed • I.f an incorrect key is struck wh i1e punching a tape, the tape can be corrected as follows: If the error is noticed after typing and punching N characters, press the punch B. SP. (backspace) pushbutton N + 1 times and strike the keyboard RUB OUT key N + 1 times. Then continue typing and punching with the character which was in error. To dupl icate an existing tape: perform steps 1 and 2 of the procedure under the current heading and repeat step 2 of the procedure outl ined under Loading Data Under Program Control to energize the equ ipment and load the tape to be dupl icated into the reader. Then perform step 3 of the procedure under the current heading. Initiate tape dupl ication by setting the reader START/STOP/FREE switch in the START position. Corrections to insert or delete information on a perforated tape can be made by duplicating the correct portion of the tape, and manually punching additional information or inhibiting punching of information to be deleted. This is accomplished by duplicating the tape and carefully observing the information being typed as the tape is read. In this manner the reader START/STOP/FREE switch can be set to the STOP position just before the point of the correction is typed. Information to be inserted can then be punched manua IIy by means of the keyboard. Information can be deleted by pressing the punch OFF pushbutton and operating the reader unti I the portion of the tape to be deleted has been typed. It'may be necessary to backspace and rub out one or two characters on the new tape if the reader is not stopped prec isely on time. The number of characters to be rubbed out can be determined exactly by the typed copy. Be sure to count spaces when counting typed characters. Continue dupl icating the tape in the normal manner after making the corrections. New, dupl icated, or corrected perforated tapes shou Id be verified by reading them off line and carefully proofreading the typed copy. 8-12 Assembl ing Programs With PAL Programs prepared in binary format and written in PAL symbol ic language can be assembled into binary, machine-language program tapes by PAL as described in appropriate Digital Program Library documents. Basically, this operation is accompl ished as follows: 1. Energize the computer by assuring that the lock switch is turned counterclockwise and by setting the POWER switch to the right. 2. Energize the Teletype by setting the LINE/OFF/LOCAL switch to the LINE position. Check the paper supply in the printer and punch and replenish as necessary. 3. Store the RIM loader program as described under Manual Data Storage and Modification. 4. Store the BIN loader program as described under Loading Data Under Program Contro I • 5. Load the PAL program tape in the Teletype reader and set the ST ART/ STOP/FREE switch to the STOP position. . 6. Load the starting address of the BIN loader program (1777 or 7777) into the MA by means of the SR and the LOAD ADDRESS key. 7. Press the START key, set the Teletype reader switch to the START position, and wait until the tape has been completely read. When the tape stops, the AC should contain all zeros. If any ACCUMULATOR indi- cator is lit, a checksum error has been encountered and th is procedure should be repeated from step 5. Repeated errors indicate defects in the tape being read or in the operation of the PDP-5 system. 8 . Load the binary tape in symbo Ii c Ia nguage into t he reader a nd set the START/STOP/FREE switch to the STOP position. 8-13 9. Load the starting address of the assembler (200) into the MA by means of the SR and the LOAD ADDRESS key. 10. Set bit 0 of the SR to the 0 position, and set bit 1 to the 1 position. These switch settings indicate to the program that the first pass of this' 2-pass assembler is to be performed. If a starting address other than 200 is to be generated for the program being assembled, set this address into bits 7 through 11 of the SR. 11. Assure that the Tel etype punch is turned off by press ing the OFF pushbutton. 12. Press the computer START key, start the tape reader by setting the 3-position switch to the START position, and wait for the tape to be completely read and a symbol table to be typed. If an error printout is obtained at th is time, the symbol ic tape must be corrected and this procedure is repeated from step 8. If no error printout is obtained, proceed to step 13. 13. Remove and reload the tape in the reader. 14. Repeat step 9, then set SR bit 0 to 1 and bit 1 to 0 to indicate that the second pass is to be performed. 15. Press the Tel etype punch ON pushbutton, press the START key, and wait until a leader is automatically punched. When leader punching stops, start the tape reader, and wait unti I the program stops. The perforated tape obtained in the second pass (reading) of the symbol ic tape is an assembled binary tape which can be stored by means of the BIN loader and can be run as described under Loading Data Under Program Control. Teletype Code The 8-bit code used by the Model 33 ASR Teletype unit is the American Standard Code for Information Interchange (ASCII) modified. To convert the ASCII code to Teletype code add 8-14 200 octal (ASCII + 200 = Teletype). This code is read in the reverse of the normal octal 8 form used in the PDP-5 since bits are numbered from right to left, from 1 through 8, with bit 1 having the most significance. Therefore perforated tape is read: 7~S~ 8 Most Significant Octal Bit 2 Tape is loaded into the reader: 3 S • 4 Least Significant Octal Bit 5 6 7 8 The Model 33 ASR set can generate all assigned codes except 340 through 374 and 376. Generally codes 207, 212, 215, 240 through 337, and 377 are sufficient for Teletype operation. The Model 33 ASR set can detect all characters, but does not interpret all of the codes that it can generate as commands. The standard number of characters printed per Iine is 72. The sequence for proceeding to the next Iine is a carriage return followed by a Iine feed (as opposed to a I ine feed followed by a carriage return). Key or key combinations required to produce octal codes from 200 through 337, 375, and 377 are indicated in Table 8-4 with the associated ASCII character. TABLE 8-4 Octal Code Character Name TELETYPE CODE ASCII Character Teletype Character Key or Key Combinations 220 Null/Idle NULL CTRL @ 201 Start of Message SaM CTRL A 202 End of Address EOA CTRL B 203 End of Message EOM CTRL C 204 End of Transm ission EaT CTRL D 205 Who Are You WRU CTRL E 206 Are You RU CTRL F 207 Audible Signal BELL CTRL G 8-15 TABLE 8-4 Octal Code TELETYPE CODE (continued) Character Name ASCII Character Teletype Character Key or Key Combinations 210 Format Effector FE CTRL H 211 Horizontal Tabulation H TAB CTRL I 212 Line Feed LF CTRL J 213 Vertical Tabulation V TAB CTRL K 214 Form Feed FF CTRL L 215 Carriage Return CR CTRL M 216 Shift Out SO CTRL N 217 Sh ift In SI CTRL a 220 Device Control Reversed for Data Line Escape DCa CTRL P 221 Device Control On DCl CTRL Q 222 Device Control (TAPE) DC2 CTRL R 223 Device Control Off DC3 CTRL S 224 Device Control (+APe) DC4 CTRL T 225 Error ERR CTRL U 226 Synchronous Idle SYNC CTRL V 227 Logical End of Media LEM CTRL W 230 Separator I Information SO CTRL X 231 Separator I Data Del imiters Sl CTRL Y 232 Separator I Words S2 CTRL Z 233 Separator I Groups S3 SHIFT CTRL 234 Separator I Records S4 SHIFT CTRL , L 235 Separator I Fi I es S5 SHIFT CTRL M 236 Separator I Misc. S6 SHIFT CTRL N 237 Separator I Misc. S7 SHIFT CTRL a 240 Space SP Space Bar 241 Exclamation Point 242 Quotat ion Marks Space SHIFT II 8-16 II SHIFT II K TABLE 8-4 Octal Code Character Name TELETYPE CODE (continued) ASCII Character Teletype Character Key or Key Combinations 243 Number Sign # # SHIFT # 244 Dollar Sign $ $ SHIFT $ 245 Percent Sign 0/0 ok SHIFT 0/0 246 Ampersand & & SHIFT & 247 Apostrophe SHIFT I 250 Parenthesis, Beginning ( ( SHIFT ( 251 Parenthesis, Ending ) ) SHIFT 252 Asterisk * * SHIFT * 253 Plus Sign + + SHIFT + 254 Comma 255 Hyphen 256 Period 257 Virgule / / / 260 Numeral 0 0 0 0 261 Numeral 1 1 1 262 Numeral 2 2 2 2 263 Numeral 3 3 3 3 264 Numeral 4 4 4 4 265 Numeral 5 5 5 5 266 Numeral 6 6 6 6 267 Numeral 7 7 7 7 270 Numeral 8 8 8 8 271 Numeral 9 9 9 9 272 Colon 273 Semicolon 274 Less Than Equals 276 Greater Than < = > SHIFT 275 < = > 8-17 SHIFT SHIFT < = > TABLE 8-4 TELETYPE CODE (continued) ASCII Character Octal Code Character Name 277 Interrogation Point ? ? SHIFT ? 300 At @ @ SHIFT @ 301 Letter A A A A 302 Letter B B B B 303 Letter C C C C 304 Letter D D D D 305 Letter E E E E 306 Letter F F F F 307 Letter G G G G 310 Letter H H H H 311 Le'tter I 312 Le"tter J J J J 313 Le'tter K K K K 314 Le'tter L L L L 315 Le'tter M M M M 316 Letter N N N N 317 Letter 0 0 0 0 320 Letter P P P P 321 Letter Q Q Q Q 322 Letter R R R R 323 Letter S S S S 324 Letter T T T T 325 Letter U U U U 326 Letter V V V V 327 Letter W W W W 330 Letter X X X X 331 Letter Y Y Y Y 332 Letter Z Z Z Z 8-18 Teletype Character Key or Key Combinations TABLE 8-3 Character Name Oc1'al Code TELETYPE CODE (continued) ASCII Character Teletype Character Key or Key Comb i nat ions 33~3 Bracket, Left [ [ SHIFT K 334 Reverse Virgule "- "- SHIFT L 335 Bracket, Right ] ] SHIFT M 336 Up Arrow (exponentation) t t SHIFT t 337 Left Arrow +- +- SHIFT .- 340 through 374 are not avai lable 375 Unassigned Control 376 Not Available 377 Delete/Idle/Rub Out G) DEL ALT MODE RUB OUT PROGRAMMING Refer to the PDP-5 Programming Handbook F-55 for information on basic programming of the system. Refer to individual Digital Program Library documents for specific information on the format, specifications, and procedure for using a particular program language, such as PAL or FORTRAN. 8-19 SECTION 9 MAINTENANCE Maintenance of the PDP-5 consists of procedures repeated periodically as preventive maintenance and tasks performed as corrective maintenance in the event of equipment malfunction. Maintenance activities require use of the equipment I isted in Table 9-1, or equ iva lent, as well as the use of standard hand tools, cleansers, and test cables and probes. TABLE 9-1 MAINTENANCE EQUIPMENT Equipment Manufacturer Designation Multimeter Triplett or Simpson Model 630- NA or 260 Potentiometric Vol tmeter** John Fluke Model801H Audio Oscillator** Hewlett Packard Model200CD Oscil loscope Tektronix Type 540 Series CI ip-on Current Probe Tektronix Type P6016 Current Probe Ampl ifier Tektronix Type 131 PI ug-In Uni t** Tektronix Type L System Module Extender* DEC Type 1954 System Module Puller* DEC Type 1960 Maindec 501, Instruction Test* DEC DEC- 5-12-M Maindec 502, Memory Checkerboard Test* DEC DEC- 5-15-M Maindec 503, Add ress Test* DEC DEC- 5-16-M Maindec 510, Read Paper Tape Test* DEC DEC-5-13-M Maindec 512, Punch Tape Test* DEC DEC- 5-14-M Maindec 514, Teleprinter Test* DEC DEC- 5-19-M *One is suppl ied with the equipment **Required only for the Type 137 Analog-to-Digital Converter 9-1 TABLE 9-1 MAINTENANCE EQUIPMENT (continued) Equipment Manufacturer Designation Paint Spray Can* DEC DEC Blue 5150-865 Paint Spray Can* DEC DEC Gray 3277-1R55 Air Fi Iter* Researc h Products Corp. E Z Kleen 2-inch Type MV Fi Iter- Kote* Researc h Products Corp. By Name *One is suppl ied with the equipment The Maindec routines are diagnostic programs designed to exercise or test specific functions within the computer system. Maindec routines are prepared as a perforated-paper program tape in readin mode format and are accompanied by a detailed description of the program contained onthe tape, procedures for usingthe program, and information on analyzing the program resultsto locate spec ific circuit fai lures. Use of these routines is indicated at the appropriate poi nts in th is manual as they apply to preventive or corrective maintenance of the standard PDP-5 system. If is is necessary to remove a module during either preventive or corrective maintenance, the Type 1960 System Module Puller should be used. Turn off all power before extracting or inserting modules. Carefully hook the small flange of the module puller over the center of the module rim, and gentl y pull the module from the rack. Use a straight even pull to avoid damage to plug connections or twisting of the printed-wiring board. Since the puller does not fasten to the module, grasp the rim of the module to prevent it from falling. Access to controls on the module for use in adjustment, or access to points used in signal tracing can be gained by removing the module, connecting a Type 1954 System Module Extender into the vacated module connector in the mounting panel, and then inserting the module into the extender. The procedures presented here assume that the reader understands the function of the keys, switches, and indicators on the operator console and is familiar with machine programming as described in the PDP-5 Programming Handbook, F55. In addition to the controls and indicators on the operator console and on the Teletype unit (described in Table 8-1 and Table 8-2), maintenance operations use controls and indicators 9-2 on component assembl ies mounted on the pi enum door of the computer. The function of these controls and indicators is described in Table 9-2. TABLE 9-2 MAINTENANCE CONTROLS AND INDICATORS Control or Indicator Function 832 Power Contro I Circuit breaker Protects the computer power source from overload due to failure of the computer power circuits. REMOTE/OFF/LOCAL switch Allows control of the computer primary power from the back of the machine during maintenance. In the REMOTE position, appl ication and removal of computer power is controlled by the lock and POWER switches on the operator console. In the OFF position the computer is de-energized, regardless of the position of switches on the operator console. In the LOCAL position the computer is energized regardless of the position of operator console switches or door interlocks. Elapsed ti me meter Ind i cates the total number of hours the computer has been energized and so provides a unit of measure that is more appropriate than calendar time for determining preventive maintenance schedules. MEM. POWER switch Controls the appl ication and removal of operating voltages for the memory circuits. 737 (Marginal-Check) Power Supply -15/off/+ 10 switch Controls the output of the marginal-check power supply. In the -15 position the output is negative and is connected to the bl ue connector on each module mounting panel. In the off (center) position the suppl y is de-energized and the output is disconnected. In the +10 position the output is positive and is connected to the green connector on each module mounting panel. 9-3 TABLE 9-·2 MAINTENANCE CONTROLS AND INDICATORS (continued) Function Control or Indicator MARGINAL CHECK voltmeter Indicates the output voltages of the marginalcheck power suppl y. Contro I knob Controls the amplitude of the marginal-check vol tage between 0 and 20 v. PREVENTIVE MAINTENANCE Preventive maintenance consists of tasks performed prior to the initial operation of the equipment and periodically during its operating life to ensure that it is in satisfactory operating condi tion . Fa ithful performance of these tasks will foresta II poss ibl e future fail ure by d iscovering progressive deterioration and correcting minor damage at an early stage. Data ob- tained during the performance of each preventive maintenance task should be recorded in a log book. Analysis of this data will indicate the rate of circuit operation deterioration and provide information to determine when components should be replaced to prevent failure of the equipment. These tasks consist of mechanical checks, which include cleaning and visual inspections; marginal checks, which aggravate border I ine circuit conditions or intermittent failures so that they can be detected and corrected; and checks of specific circuit elements such as the power suppl ies, sense ampl ifiers, and memory currents. All preventive maintenance tasks should be performed as a function of conditions at the installation site. Perform the mechan ical checks at least once each month or as often as required to allow efficient functioning of the air filter. All other tasks should be performed on a regular schedule, at an interval determined by the rei iabil ity requirements of the system. For a typical appl i cation, a schedule of every 600 equipment operating hours or every four months, whichever occur first, is suggested. The most important schedule to maintain is that of the simplest procedure, --the Mechanical Checks. Many hours of computer down time can be avoided by rigid adherence to a schedule based upon the cond ition of the air fil ter. Mach ine fai lures can occur due to overheating caused by an air filter becoming so dirty that no cooling air can be drawn into the cabinet by the fan. 9-4 Mechanical Checks Assure good mechanical operation of the equipment by performing the following steps and the indic(lted corrective action for any substandard conditions found: 1. Clean the exterior and the interior of the equipment cabinet using a vacuum cleaner or clean cloths moistened in nonflammable solvent. 2. Clean the air filter at the bottom of the cabinet. Remove the filter by removing the fan and housing, which are held in place by two knurled and slotted captive screws. Wash the filter in soapy water and dry it in an oven or by spraying with compressed gas. Spray the fi Iter with Fi Iter- Kote (Research Products Corporation, Madison, Wisconsin). 3. Lubricate door hinges and casters with a light machine oil. Wipe off excess oil. 4. Visuall y inspect the equ ipment for completeness and general condition. Repaint any scratched or corroded areas with DEC blue tweed paint number 5150- 865 or DEC gray enamel number 3277-1 R55. 5. Inspect all wiring and cables for cuts, breaks, fraying, wear, deterioration, kinks, strain, and mechanical security. Tape, solder, or replace any defective wiring or cabl e covering. 6. Inspect the following for mechanical security: keys, switches, control knobs, lamp assemblies, jacks, connectors, transformers, fan, capacitors, elapsed time meter, etc. Tighten or replace as required. 7. Inspect all module mounting panels to assure that each module is securely seated in its connector. 8. Inspect power supply capacitors for leaks, bulges, or discoloration. Re- place any capacitors giving these signs of mal function. 9-5 Power Suppl y Checks Check the output voltage and ripple content of the 779 Power Supply (not the 735), and assure that they are within the tolerance specified in Table 9-3. Use a multimeter to make the output vol tage measurements without disconnecting the load. Use the oscilloscope to measure the peak-to-peak ripple content on dc outputs of the supply. This supply is not adjustable, so if the output voltage or ripple content is not within the tolerance specified, the supply is considered defective and troubleshooting procedures should be undertaken. TABLE 9-3 Measurement Terminals at Power Supply Output TYPE 779 POWER SUPPLY OUTPUTS Output Voltage Range Nominal Output Voltage Maximum Peak-to-Peak Output Ripple Orange {+} to Yellow (-) +10 9.0 to 11 .0 1 .0 vol t Yellow (-) to Blue (-) -15 14.0 to 16.0 0.5 volt Red (+) to Yellow (-) +15 14.0 to 16.0 1 .25 volt Yellow (+) to Green (-) -15 14.0 to 16.0 1 .25 volt Check the operation of the varible-output 737 Power Supply which produces the marginal-check voltages. With all of the normal/marginal switches in the normal (down) position, make the following measurements at the color-coded connector at the right side of any convenient module mounting panel: 1. Connect a multimeter between the yellow (-) and black (+) terminals; set the -.15/off/+ 10 switch to the -15 position, and turn the control knob clockwise to assure that at least -20 volts can be produced by the supply (as ind icated on the mul timeter). Record the ind ication given on the MARGI NAL CHECK voltmeter and on the multimeter. These indications should be I equal ±] volt. Connect the oscilloscope to the yellow terminal, and measure the peak-to-peak ripple content to assure that it is no more than 1.0 volt. Turn the control knob fully counterclockwise; set the -15/off/+1 0 switch to the off position, and disconnect the multimeter and oscilloscope. 9-6 2. Connect the multimeter between the green (+) and black (-) terminals; set the -15/off/+10 switch to the +10 position, and turn the control knob clockwise to assure that at Ieast +20 vol ts can be produced by the suppl y. Turn the control knob fully counterclockwise, set the -15/off/+1 0 switch to the off posi tion, and disconnect the mul ti meter. Marginal Checks Margina I checking uti! izes the Maindec diagnostic programs to test the functional capabil ities of the computer with the module operating voltages biased above and below the nominal levels within a specified margin. Biasing the operating voltages aggravates borderline circuit condi- tions within the modules to produce failures which are detected by the program. When the program detects an error, itusually provides a printout or visual indication which is helpful in locating the source of the fault and then halts. Therefore, marginal components can be replaced during scheduled preventive maintenance to forestall possible future equipment failure. If no marginal components exist, the operating vol tages are biased beyond the spec ified margins, and the operating voltages at which circuits fail are recorded in the maintenance log. By plotting the bias voltages obtained during each scheduled preventive maintenance, progressive deterioration can be observed and expected failure dates can be predicted. In this manner these checks provide a means of planned replacement. These checks can also be used as~a troubleshooting aid to locate marginal or intermittent components, such as deteriorating trans istors . Raising the operating voltage above +10 volts increases the transistor cut-off bias that must be overcome by the previous driving transistor. Therefore low-gain transistors fai I. Lowering the bias vol tage below + 10 vol ts reduces transistor base bias and noise rejection and thus provides a test to detect high-leakage transistors and simulates high temperature conditions (to check for thermal run away). Raising and lowering the -15 vol t suppl y increases and decreases the output pulse ampl itude of pulse ampl ifier modules. Since the -1 S vol t suppl y is the collector load voltage (which is clamped at -3 volts in most modules), raising and lowering this source would have little effect upon the logic circuits. Therefore, wiring in the PDP-5 allows marginal check ing of the -15 vol t suppl y connected to pulse ampl ifier modul es onl y. 9-7 The +10 volt margin should be about ±5 volts, and the -15 volt margin should be about +3 (-18 v) and - 8 (- 7 v) volts. It is important that the -15 volt margin not be increased above 18 volts or damage can result within the logic. The 779 Power Supply produces the normal module operating voltages of +10 vdc and -15 vdc. The 737 Power Supply produces an adjustable voltage which is used to check for marginal circuit operations under biased conditions. The output of this supply can be selected to be positive, disconnected, or negative by means of a -15/off/+ 10 switch; is adjusted by means of the large knob on the supply; and is indicated on a MARGINAL CHECK voltmeter on the supply. Outputs from both of these supplies are connected to each module mounting panel through a color-coded connector at the right side of each panel, as seen from the module side. The color coding of these connectors is as follows, from top to bottom: a. Green, +10 vdc marginal-check supply b. Red, normal +10 vdc supply c. Bl ack, ground d. Blue, normal-15vdcsupply e. Yellow, -15 vdc marginal-check supply Three single-pole double-throw, normal/marginal switches at the end of each module mounting panel allow selection of either the normal power source or the marginal-check power supply output for distribution to the modules. The top switch selects the +10 volt supply routed to terminal A of all modules in the panel. In the down position the normal fixed +10 vol t sup- ply connected to the red terminal is supplied to the modules, and in the up position the marginal-check voltage supplied to the green terminal is supplied to terminal A of the modules. The center switch performs the same selection as the top switch for connection of a nominal +10 volt level to terminal B of all modules in the panel. The bottom switch selects the -15 volt supply to be routed to terminal C of all pulse ampl ifier modules in the panel. In the down position the normal 15-volt output of the fixed power supply, received at the blue terminal, is supplied to pulse amplifier modules. In the up position the marginal-check voltage, con- nected to the yellow terminal, is suppl ied to terminal C of all pulse ampl ifier modules. 9-8 The normal/marginal switches at the end of panel 18 are wired slightly differently so that the top switch selects the +10A supply for all modules in the panel except the sense amplifiers at locations 1815 through 1 820; the center switch functions as normal; and the bottom switch selects the +10A supply for the sense amplifiers. This connection allows separate checking of the sense ampl ifjers, since no pulse amplifier modules are contained in the panel. To perform the checks: 1. Assure that all three normal/marginal-check switches on each module mounting panel are in the down position. 2. Set the -15/off/+ 10 switch on the marginal-check power supply to the +10 position. 3. Ad just the output of the margina I-check power suppl y so that the MARGI NAL CHECK voltmeter indicates 10 vol ts. 4. Set the top normal/marginal switch to the up position on the panel to be checked. 5. Start computer operation in a diagnostic program or routine which full y uti I izes the circui ts in the panel to be tested. If no program is suggested by the normal system application, select an appropriate Maindec program from Table 9-4. To completely test the PDP-5, all Maindec programs listed in Table 9-4 should be performed at elevated and reduced voltages for each terminal (+lOA, +108, and -15C) and for each module mounting panel indicated in the table. 9-9 TABLE 9-4 Module Panel MAINDEC PROGRAMS USED IN MARGINAL CHECKING 501 1 A 1 B Maindec Program 510 503 502 A, B, C A, B, C 512 514 A, B, C A, B A* S A 1 C A, B, C 1 D A, B, C 1 E A, B, C 1 F A, B, C A, B, C A, B, C *Bottom normal/marginal switch on module mounting panel lB. 6. Decrease the margina I-check power suppl y output unti I normal system operation is interrupted. Record the marginal-check voltage. At this point marginal transistors can be located and replaced, if desired. Readjust the marginal-check power suppl y output to the nominal +10 vo It Ieve I. 7. Restart' computer operation. Increase the marginal-check suppl y output until normal computer operation is interrupted, at which point record the marginal-check voltage. Transistors can again be located and replaced. Readjust the marginal-check power supply to the nominal +10 volt level. 8. Return the top normal/marginal switch to the down position. 9. Repeal steps 4 through 8 for the center normal/marginal switch on the mounting panel being checked. 10. Set the -15/off/+ 10 switch on the marginal-check power suppl y to the -15 position and adjust the output until the MARGI NAL C HECK vol tmeter indicates 15 volts. 11. Set the bottom normal/marginal switch to the up position for the panel to be checked, then repeat step 5. 9-10 12. Repeat steps 6 and 7, readjusting the marginal-check power supply to the nominal -15 volt level at the end of each step. Return the bottom normal/marginal switch to the down position. 13. Repeat steps 2 through 12 for each module mounting panel to be tested. 14. Turn the marginal-check power supply control knob fully counterclockwise, and set the -15/off/+10 switch to the off position. Memory Current Check Measure and compare the memory currents with the values listed on the memory array label. This label indicates the optimum memory settings determined at the factory. Allow the equipment to warm up for approximately one hour before making measurements. Whenever possible this check should be performed at an ambient temperature of 25 degrees centigrade. Compensate measured read-write and inhibit currents by subtracting 1 milliampere for every degree of ambient temperature above 25°C. (Add 1 milliampere for each degree below 25°C. The Memory Curr.ent Check and Sense Ampl ifier Check procedures must not be performed when the equipment temperature is below 20°C. Measure the read-write current using the osc illoscope and c lip-on current probe at the read side of a fully selected drive line. Synchronize the oscilloscope with the negative-shift of the Memory Read signal at 1C19V. Adjust the read-write current to the value specified on the label of the core memory array label. Clockwise rotation of the lower potentiometer (R13) on the 1701 Power Supply Control module in the 735 Power Supply increases the read-write current. In Iike manner, measure the inhibit current by connecting the clip-on current probe at a selected output Iine of the 1978 Resistor Board at either location 1 B24 or 1 B25. Synchronize the oscilloscope on the negative shift of the Memory Read signal at 1C19V. Adjust the memory inhibit current to the value indicated on the memory array label. Clockwise rotation of the upper potentiometer (R3) on the 1701 module increases the memory inhibit current. 9-11 To obtain consistent measurements, the current probe should be positioned to indicate read current as a negative pulse, and write and inhibit currents as positive pulses as displayed on the osci Iloscope. All current ampl itude measurements should be made just before the knee in the curve at the trai I ing edge of a pulse. Note that read and write currents are measured from base line to peak amplitude, not from peak to peak. Sense Amplifier Check The 1571 Dual Sense Ampl ifiers are adjusted for optimum efficiency through marginal checking techniques. This check is not performed on systems containing 4554 Dual Sense Ampl ifiers, since these modules have a fixed sl ice level. Perform the Marginal Checks procedure using the Memory Checkerboard Program (Maindec 502) and the bottom switch (+1 OA) on module mounting panel 1 B. Check and, if necessary, adjust each sense amplifier circuit so that approximately equal positive and negative margins can be obtained for the +1 OA supply. The sense ampl ifiers are located at 1 B15 through 1 B20, 1 B15 containing SAO and SAl' and 1 B20 containing SA and SA 10 . The sense ampl ifier for the more significant bit in a module is adjusted by the up- ll per potentiometer (R26), and the less significant bit is adjusted by means of the lower potentiometer (R28). Clockwise rotation of a potentiometer decreases the clipping level of the sense ampl ifier. Type 137 Analog-To-Digital Converter Maintenance The checks and adjustments presented in this portion of the manual apply only to PDP-5 systems containing the Type 137 option. Maintenance of the Type 137 involves program-repeated operation of the converter performed during each scheduled preventive maintenance to check the general accuracy and function of the option, and adjustment checks and procedures used to verify and/or adjust the operation of specific functional components. The functions which are checked by module are the timing of the 4303 Integrating Single Shot, the -10 vol t output of the 1704 Precision Power Supply, the adjustment of the ladder network in the 1574 12Bit Digital- To-Analog Converter, and the common balance and zero set of the 1572 Difference Ampl ifier. The timing checks and ladder network adjustments should be performed only when the need to do so is ind icated by the converter check or by normal troubl eshooting procedures. The -10 volt reference supply and the difference amplifier should be checked approximately 9-12 every three weeks or every 100 equipment operating hours, whichever occurs first. Maintenance of the Type 137 option requires use of the following equipment: a. A potentiometric voltmeter which has infinite input resistance at null and wh ic h has an accuracy of ± O. 025°k. b. A single-frequency sine wave source, between 30 and 1000 cps. The output should be floating and the amplitude should be variable from 2 to 20 millivolts. A 115-volt 60-cycle power source may be used as this source if it is suitably stepped down in ampl itude. c. A dc source of 5 ± 0.5 volts for biasing the output of the sine wave source. A voltage divider connected across output terminals 1E23D (ground) and 1E23E (-10 volts) can be used as this source. d. A dual-tracer osc illoscope having a vertical-deflection sensitivity of 5 mill ivolts per centimeter. There are many ways to check and adjust the components of an analog-to-digital converter. The information and procedures presented here can be varied greatly as a function of the test equipment available and the object of the test or adjustment. Additional background information and procedures for testing and adjusting converters is found in the Analog-Digital Conversion handbook, form E-5100, publ ished by DEC. Converter Check This test repeatedly operates the converter by means of a 2-step program. With a known analog input, the conversion result displayed in the accumulator is then verified by the operator. To perform the check: 1. Physically disconnect the normal analog input from the input to the Type 137. This connection usually is made by means of a connector on panel 1 J that can be disconnected. If the connection is made directly to the module connector, it must be broken at term ina I 1 E24N . 9-13 2. Supply a known constant dc voltage to the input connector or to terminal 1E24N. This potential can be obtained by connecting a voltage divider across output terminals D (ground) and E (-10 volts) of the 1704 Precision Power Supply at location 1 E23. 3. Store the following 2-instruction sequence into the computer core memory by means of the switch register, LOAD ADDRESS key, and DEPOS IT key on the operator console. Address BEG, 6000 6001 Instruction Mnemonic 6004 5200 ADC JMP BEG 4. Start the program by loading the initial address into the MA by means of the switch register and LOAD ADDRESS key; then press the START key. 5. Record and compare the binary number in the accumulator with the value of the voltage connected in step 2. The answer in the accumulator is in 2 s 1 complement unsigned representation and can be converted to a decimal voltage value by using Table 9-5. 6. Repeat steps 2, 4, and 5 for several values of input voltage between 0.0 and -10 volts. Record the analog input signal and the binary answer obtained in each measurement. From these results determine if the answers obtained are within the limits specified by the accuracy connection of the converter or if the converter requires adjustment. If no adjustment is necessary, halt the program by I ifting the STOP key; then remove the test connections made to the analog input, and restore the normal connection from the signal measured during programmed operation of this system. 9-14 TABLE 9-5 ANALOG-DIGITAL NUMBER CONVERSION Analog Voltage Twos Compl ement Octal Number Signed Unsigned {Negative} 4000 0000 o. 4001 0001 0.00244140625 4002 0002 0.0048828125 4004 0004 0.009765625 4010 0010 0.01953125 4020 0020 0.0390625 4040 0040 0.078125 4100 0100 0.15625 4200 0200 0.3125 4400 0400 0.625 5000 1000 1 .25 6000 2000 2.5 0000 4000 5. 2000 6000 7.5 3000 7000 8.75 3400 7400 9.375 3600 7600 9.6875 3700 7700 9.84375 3740 7740 9.921875 3760 7760 9.9609375 3770 7770 9.98046875 3774 7774 9.990234375 3776 7776 9.9951171875 3777 7777 9.99755859375 10000 10. 9-15 Integrating Single Shot Check and Adjustment Check the timing of the 4303 module at location lE18 to assure that sufficient time is allowed for the conversion of each bit. To perform the check: 1. Connect the oscilloscope signal inout to termina I 1E l8W; connect the trigger input to 1E18K, and adjust for synchronizing on an external negative pulse. 2. Perform steps 3 and 4 of the previous procedure. 3. Observe that the pulse displayed on the oscilloscope is negative for the duration I isted under "Conversion Ti me per Bit" and occurs every 12 microseconds plus the duration I isted under the col umn "Instruction Execution Time" in Table 4-3 for the adjusted bit accuracy of the converter. Make any necessary adjustment in the conversion time by turning the potentiometer in the 4303 module (accessible through a hole in the handle of module 1E18) . Precision Power Supply Check and Adjustment The -10 volt output of the 1704 Precision Power Supply module at location 1E23 supplies the reference vol tage used by the level ampl ifiers and determines the accuracy of the analog vol tage generated by the converter ladder network. A rough check of this ad justment can be made using the oscilloscope. However, an accurate check or adjustment MUST be made with a high impedance instrument which is accurate to within at least 0.1%, such as the John Fluke potentiometric voltmeter. Adjustment of the supply must be performed within 1 minute due to drifting of the vol tmeter. To ad just the suppl y: 1. Calibrate the potentiometric voltmeter. 2. Connect the potentiometric voltmeter between terminals 1E23D (ground) and 1E23E (-10 volts). 3. Turn "the screw-driver ad justment, accessible through the hole in the 9-16 handle of the module, until the voltmeter indicates -10 vdc ±0.1 mv. (This adjustment controls the setting of the fine control potentiometer R7 shown on schematic diagram RS-1704. The coarse control potentiometer R9 and the current control potentiometer R2 are preset at the factory and must not be adjusted in the field.) If the output of the supply is 0.0 volts check the external circuit for short circuits to ground. If the output can not be adjusted within the tolerance specified in this procedure, return the module to the factory for calibration. Digital-To-Analog Converter Check and Adjustment This procedure is performed to check and adjust the ladder network of the 1574 12-Bit DigitalTo-Analog Converter module at location 1 E22. This procedure should be used if the module has been subjected to a drastic change in temperature, a mechanical shock sufficient to change the setting of the potentiometers, or following repair or replacement of the level amplifiers on the 4678 modules associated with bits 0 through 7. This test checks and aligns the ladder to compensate for variations in resistors of the divider network and for variations in the output impedance of the level amplifiers. The ladder output voltage obtained only from the bit to be tested is compared with the output voltage resulting from all of the bits of lesser significance. The difference is trimmed so that it is equal to one least significant bit. This is accomplished by a test configuration which monitors the output of the module or terminal 1E22E on a high-gain ac-coupled osc i IIoscope as the content of the bit being adjusted and the complementary content of all of the lesser significant bits are program alternated. All bits of greater significance are disabled by permanent test connections to stimulate zeros, and the test is performed from the least significant to the most significant adjustable bits (from bit 7 to bit 0). The ladder network is shown on engineering schematic RS-1574. This module contains a biasing leg consisting of potentiometer R1 and resistor R10, adjustable-resistance legs containing potentiometers R2 through R9 for bits 0 through 7, non-adjustable legs for bits 8 through 11 containing odd-numbered resistors R28 through R33, and the terminating resistor R34. The module is physically arranged in three horizontal groups of circuits. The group of circuits at 9-17 the top of the module contains potentiometer R5 for bit 3, R4 for bit 2, R3 for bit 1, and R2 for bit 0 progressing from the handle end to the connector end of the module. The center group of circuits contains potentiometer R9 for bit 7, R8 for bit 6, R7 for bit 5, and R6 for bit 4 progressing from the handle towards the connector end of the module. The bottom group of circuits contains fixed resistors R27 for bit 8, R29 for bit 9, R31 for bit 10, R33 for bit 11, and R34, the terminating resistor progressing from the handle towards the connector. The biasing resistor R1 is a Iso located on the bottom group of c ircu its near the connector end. Perform the test as follows: 1. Connect the osci lIoscope input to terminal 1 E22E and adjust it for negative internal sweep triggering. Be sure the oscilloscope is solidly connected to the analog ground at terminal lE23D. The oscilloscope vertical preamplifier should be set to a sensitivity of approximately 5 millivolts per centimeter and cal ibrated with an external reference so that the least significant bit value of 2.4 millivolts can be readily observed. 2. Turn off all power in the PDP-5; remove the ladder module at location 1 E22 by means of a 1960 System Modu Ie Pu II er; connect a 154 System Module Extender into the module connector at location 1 E22; insert the ladder module to the extender, and then restore PDP-5 power. 3. Connect the analog ground at terminal 1E24D to the level amplifier input terminals corresponding to bits 0 through 6 at terminals 1E21 F, lE21H, 'IE21J, lE21 K, lE21L, lE20F, and lE20H. 4. StorE~ the program listed in Table 9-6 in the PDP-5 core memory by means of the switch register, LOAD ADDRESS key, and DEPOSIT key. If this test is to be repeated periodically, the program can be punched on tape and stored by means of the Readin Mode Loader as described in Section 8 of th is manua I. 9-18 TABLE 9-6 Address PAD DIGITAL-TO-ANALOG CONVERTER ADJUSTMENT PROGRAM Content Mnemonic Comments 6000 7200 CLA INITIALIZE 6001 1107 TAD PAD FETCH PATTERN ADDRESS-l 6002 7001 lAC CORRECT PATTERN ADDRESS 6003 3007 DCA STORE CORRECTED PATTERN ADDRESS 6004 1607 TAD I PAD LOAD APPROPRIATE PATTERN 6005 7040 CMA COMPLEMENT PATTERN 6006 5005 JMP .-1 ALTERNATE PATTERN CONTINUOUSLY 6007 6007 PATTERN ADDRESS (PAD) 6010 0020 PATTERN BIT 7 6011 0040 PATTERN BIT 6 6012 0100 PATTERN BIT 5 6013 0200 PATTERN BIT 4 6014 0400 PATTERN BIT 3 6015 1000 PATTERN BIT 2 6016 2000 PATTERN BIT 1 6017 4000 PATTERN BIT 0 5. Start the program by loading the initial address into the MA by means of the switch register and the LOAD ADDRESS key. 6. Read and record the value of the two levels of the square wave displayed on the osc i lIoscope. The higher ampl itude value corresponds to the condition when the bit being checked (bit 7) is a binary 1 and all less significant bits are zeros. The lower amplitude value corresponds to the condition when the bit being checked is a binary 0 and all less significant bits are ones. 'Compare these two values, and adjust the potentiometer (R9 for bit 7) until the higher amplitude is 2.4 millivolts greater than the smaller amplitude, or until the higher amplitude is equal to the value listed in 9-19 Table 9-5. During this adjustment it is possible to invert the relative values of the two signal amplitudes; so care should be taken to prevent adjustment so that the bit being checked is of lower value than the value of the less significant bits. Since the ladder potentiometers are wire wound, it is necessary to assure that they are adjusted to a stable position in which the sl iding arm is resting in a position that cannot be moved in either direction by vibration or shock. Therefore, after adjusting the potentiometer, tap the module once or twice, and note any change in the output voltage displayed on the osc illoscope. If a change is observed, readjust the potentiometer to a more stable position closer to the ideal value. 7. Stop the program by lifting the STOP key on the operator console. 8. Disconnect the ground connection from terminal 1 E20H made during step 3. 9. Check bit 6 by repeating steps 5 through 7 and adjusting potentiometer R8. Then disconnect the ground connection made to term inal 1 E20F made duri ng step 3. 10. Check bit 5 by repeating steps 5 through 7 and adjusting potentiometer R7. Then disconnect the ground connection made to terminal 1 E21 L during step 3. 11. Check bit 4 by repeating steps 5 through 7 and adjusting potentiometer R6. Then disconnect the ground connection made to terminal 1 E21 K during step 3. 12. Check bit 3 by repeating steps 5 through 7 and adjusting potentiometer R5. Then disconnect the ground connection made to terminal 1 E21 J during step 3. 9-20 13. Check bit 2 by repeating steps 5 through 7 and adjusting potentiometer R4. Then disconnect the ground connection made to terminal 1 E21 H during step 3. 14. Check bit 1 by repeating steps 5 through 7 and adjusting potentiometer R3. Then disconnect the ground connection made to terminals 1E21 F and 1 E23D during step 3. 15. Check bit 0 by repeating steps 5 through 7 and adjusting potentiometer R2. The zero end point of the ladder network can be checked and adjusted as follows: 1. Load a word containing all zeros into any convenient core memory address by means of the switch register, LOAD ADDRESS key, and the DEPOSIT key. Then clear the accumulator by setting this word into the AC by means of the switch register, LOAD ADDRESS key, and the EXAMI NE key. 2. Calibrate the oscilloscope so that analog ground can be determined by a fixed position on the graticule. 3. Connect the osc i lIoscope to the ladder output at terminal 1E22E, and measure any voltage differential between the analog ground and the ladder output. Adjust the biased terminal potentiometer R1 until no difference can be measured between the output voltage and analog ground. 4. Disconnect the ladder inputs from analog ground. The full scale end point of the ladder network can be checked and adjusted as follows: 1. Load a word containing all binary ones into the AC by using the keys and switches on the operator console as in step 1 of the previous procedure. 9-21 2. Connect the oscilloscope input to terminal 1E23E, and adjust the position to some fixed measuring point on the graticulei then disconnect the oscilloscope from this point. 3. Connect the oscilloscope input to terminal1E22E and measure the output voltage of the ladder network. Ad just the output of the 1704 Prec is ion Power Supply module at location 1E23 until the voltage obtained on the osc i Iloscope is exactly -10 volts. 4. Remove all test connections. Since the two end point adjustments interact, it is difficult to align them both perfectly while maintaining linearity. A somewhat more convenient method is to adjust the zero and half-full scale points for optimum fit, which permits closer control over the lower-weighted {and therefore more error sensitive} bits. The two end points can be checked and adjusted more accurately if the potentiometric voltmeter is subst ituted for the osc i Iloscope in the two precedi ng procedures. The Difference Ampl ifier Check and Adjustment The 1572 Difference Ampl ifier module at location 1 E24 should be tested periodically and at any time when it has undergone severe temperature change or mechanical shock. The need for readjustment depends upon the accuracy required and upon the environment. Adjustment of the common balance is made by turning potentiometer Rl {accessible through the lower hole in the module handle}, and zero set is adjusted by means of potentiometer R4 {accessible through the upper hole in the module handle}. To perform the checks: 1. De-energize the PDP-5i remove the modu Ie from location 1 E22i then energize the PDP-5. 2. Connect the two inputs of a dual-trace oscilloscope to the two output terminals 1 E24F and 1E24W of the difference amplifier. Connect the oscilloscope ground to the module ground at terminal 1E24D. 9-22 3. Connect the difference ampl ifier input terminals 1E24N and 1E24P to an ungrounded si ne wave source of approx imately 10m ill ivo Its ampl itude, 30 to 1000 cps, and biased at - 5 volts. 4. Connect the osc i "oscope trigger input to one of the difference ampl ifier input terminals to synchronize the trace. 5. Observe that the two difference ampl ifier output signa Is displayed on the osc i IIoscope appear as two compl ementary square waves. Adjust the lower module potentiometer so that the output signal at terminal 1 E24 W is symmetrical, and then adjust the upper module potentiometer until the output signal at terminal 1E24F is symmetrical (these adjustments must be performed in the sequence given). To improve the resol ution of these adjustments, repeat the procedure with the sine wave input reduced to 5 mill ivo Its. It may be necessary to repeat the ad justment sequence severa I times since there is interaction between the two potentiometers. This concludes the maintenance of the Type 137 Analog-To-Digital Converter. De-energize the PDP-5, test connections, and restore the original connections and condition of the converter. CORRECTIVE MAINTENANCE The PDP-5 is constructed of highly reliable transistorized modules. Use of these circuits and faithful performance of the preventive maintenance tasks ensure relatively Iittle equipment down time due to failure. Should a malfunction occur, the condition should be analyzed and corrected as indicated in the following procedures. No special tools or test equipment are required for corrective maintenance other than a broad bandwidth oscilloscope and a standard multimeter. However, a clip-on current probe such as the Tektronix Type P6016 with a Type 131 Current Probe Amplifier is very helpful in monitoring memory currents. The best corrective maintenance tool is a thorough understanding of the physical and electrical 9-23 characteristics of the equipment. Persons responsible for maintenance should become thoroughly fa mil iar with the system concept, the logic drawings, the operation of specific module circuits, and the location of mechan ical and electrical components. It is virtually impossible to outline any specific procedures for locating faults within complex digital systems such as the PDP-5. However, diagnosis and remedial action for a fault condition can be undertaken logically qnd systematically in the following phases: a. Prel iminary investigation to gather all information and to determine the physical and electrical security of the computer. b. System troubleshooting to locate the fault to within a module through the use of control panel troubleshooting, signal tracing, or aggravation techniques. c. Circuit troubleshooting to locate defective parts within a module. d. Repairs to replace or correct the cause of the malfunction. e. Validation tests to assure that the fault has been corrected. f. Log entry to record pertinent data. Prel iminary Investigation Before commencing troubleshooting procedures, explore every possible source of information. Ascertain all possible information concerning any unusual function of the machine prior to the fault and all possible data about the symptoms given when the fault occurred, such as the program in progress, condition of operator console indicators, etc. Search the maintenance log to determine if this type of fault has occurred before or if there is any cyclic history of this kind of fault, and determine how this condition was previously corrected. When the entire machine fails, perform a visual inspection to determine the physical and electrical security of all power sources, cables, connectors, etc. Assure that the power supplies are working properlyand that there are no power short circuits by performing the Power Supply Checks as 9-24 described under Preventive Maintenance. Check the cond ition of the air fi Iter in the bottom of the cabinet. If this filter becomes clogged, the temperature within the cabinet might rise suffic ientl y to cause marginal semiconductors to become defective. System Troubleshooting Do not attempt to troubleshoot the system without first gathering all information possible concerning the fault, as outl ined in the Prel iminary Investigation. Commence troubleshooting by performing that operation in which the malfunction was initially observed, using the same program. Thoroughly check the program for proper control settings. Careful checks should be made to assure that the PDP-5, and not the peripheral equipment, is actually at fault before continuing with corrective maintenance procedures. Faults in equipment which transmits or receives information or improper connection of the system frequently give indications very similar to those caused by computer malfunction. Faulty ground connections between peripheral equipment and the computer are a common source of trouble. From that portion of the program being performed and the general condition of the indicators, the logical section of the machine at fault can usually be determined. If the fault has been determined to be within the computer but cannot be immediately localized to a specific logic function, it can usually be determined to be within either the core memory or the processor logic circuits. Proceed to the Memory Troubleshooting or Logic Troubleshooting procedures. When the location of a fault has been narrowed to a logic element, continue troubleshooting to locate the defective module or component by means of signal tracing. If the foul t is intermittent, a form of aggravation test should be employed to locate the source of the fClul t . Memory Troubleshooting If the entire memory system fails, use the multimeter to check the outputs of the 735 Power Supply. Measure the voltages at the terminal strip as indicated on engineering drawing BS-D-5-0-17. Do not attempt to adjust this supply. If the supply is defective, troubleshoot it and correct the cause of the trouble; then adjust the output voltage by performing the Memory Current Check. If the power supply is functioning properly, proceed as follows: 9-25 1. De-energize the computer. 2. Connect a jumper from chassis ground to the fol lowing module terminals: 1C 19Z, 1C09Y, 1C 11 J, and 1DO 1T . 3. Remove the modules at locations 1COl through 1C03 and 1C12 through 1C14. 4. Restore computer power and press the 5TART key. This procedure causes the memory address register to advance in a normal binary counting sequence and causes the memory to cycle continuously. With the memory cycling continuously (from the preceding procedure or by a simple program loop) continue troubleshooting by using the osci lIoscope and current probe to measure fu II read and wri te currents at the output of the 1989 Memory Driver modules. Measure read current at 1A04V and write current at 1A03V. If these currents are far in excess of the value specified on the memory, multiple address selection is indicated. If the base I ine of the oscilloscope trace is present during the read or write current pulse, an address is not being selected. Check the 1987 Read-Write 5witches for short circuits or for a permanently closed switch when multiple address selection is indicated. When nonselection is indicated, check the 1987 modules for an open or disabled switch. Also check the 1976 Resistor Board modules for an open circuit and check the 2010 Memory Diode Un it modules for an open diode if nonselection occurs. If the read and write currents are acceptable at the output of the memory drivers, use the oscilloscope and current probe to trace them to the core array. Trace read current from 1A04V through the wiring to terminal 5 of each of the read-write switches at locations lA08 through 1A05. Trace write current from A 103V through the wiring to terminal 5 of each of the readwrite swi tches at locations 1A 12 through 1A09. When read-wri te curren't is not observabl e at terminal S of a read-write switch, continue tracing the current from the output of the previous read-write switch to one of the memory plug connectors at locations lA13 through lA21. Refer to engineering drawing B5-D-5-0-16 when tracing read-write current in this manner. Perform the Memory Address Test program (Maindec 503) to locate defective core memory addresses. Complete the entire program and record all addresses which fai I. Inspect the record of failure addresses for common bits. Refer to engineering drawing B5-D-5-0-16 and Table 3-1, and check the read-write switches that decode common bits of the fail ing addresses. If 9-26 this read-write switch is on the read side of the array, also check the associated resistor board; if it is on the write side of the array, also check the associated memory diode units. Substituting a known good memory diode unit at successive locations for each pass of the memory Address Test program is an effective troubleshooting technique. If an address is dropping bits, use the operator console to deposit all binary ones in that address. Then examine the address todetermine whith bit position is not being set (contains a 0). Check the sense ampl ifier, inh ibit driver, and resistor board for the assoc iated bit. If bits are drop- ping out, check the memory inhibit current as described in the Memory Current Check. If an address is picking up bits, use the operator console to deposit all binary zeros in that address, and proceed as described in the previous paragraph. To locate the cause of a specific address failure, use the oscilloscope and current probe to trace read and write current while performing a repetitive program such as the memory Address Test program or the Memory Checkerboard Test program. Trace read current from lA04V through the wiring to terminal S of each of the read-write switches at locations lAOS through lAOS. Trace write current from 1A03V through the wiring to terminal S of each of the read-write switches at locations 1A 12 through 1A09. When read-write current is not observable at terminal S of a read-write switch, continue tracing the current from the output of the previous read-write switch to one of the memory pi ug connectors at location 1A 13 through 1A21. Refer to engineering drawing D-5-0-16 when tracing read-write current in th is manner. Perform the Memory Checkerboard Test program (Maindec 502) to troubleshoot all other memory conditions. Logic: Troubleshooting If the instructions do not seem to be functioning properly, perform the 1nstruction Test program (Maindec 501). This test halts to indicate instructions that fail. When an instruction fails, as indicated by the operator console indicators when the program stops, manually load a short program loop which exercises that instruction. For example, if the rotate right instruction fails, load the program: 9-27 ClA Cll TAD (4000) A, RAR JMPA With the SIN GlE STEP switch on (set to the right) this program can be executed by repeated operation of the C()NTINUE key, and the advance of a single 1 through the accumulator and I ink can be observed. Fai Iure of a routine of th is nature shou Id suggest spec ific areas of logic circuits to be checked by signal tracing. If the computer interrupt system or the Teletype teleprinter do not seem to be functioning properly, perform the Teleprinter Test program (Maindec 514). If the Teletype tape reader or punch operation is questionable, perform the Read Paper Tape Test (Maindec 510) or the Punch Tape Test (Maindec 512). Refer to the Teletype documents for detailed maintenance information on the Model 33 ASR set. Signa I Trac i ng If the fault has been located within a functional logic element, program the computer to repeat some operation in which all functions of that element are utilized. Use the oscilloscope to trace signal flow through the suspected logic element. Oscilloscope sweep can be synchronized by control signals orclock pulses, which are available on individual module terminals at the wiring side (front) of the equipment. Circuits transferring signals with external equipment are most likely to encounter difficulty. Trace output signals from the interface connector back to the origin, and trace input signals from the connector to the final destination. The signal tracing method can be used to certify signal qualities such as pulse amplitude, Quration, rise time, and the correct timing sequence. If an intermittent malfunction occurs, signal tracing must be combined with an appropriate form of aggravation test. Aggravation Tests Intermi ttent faul ts shoul d be traced through aggravation techn iques. Intermi ttent logic mal- functions are located by the performance of marginal-check procedures as described under Preventive Maintenance. 9-28 Intermittent failures caused by poor wiring connections can often be revealed by vibrating modules while running a repetitive test program. Often, wiping the handle of a screw driver across the back ofa suspect panel of modules is a useful technique. By repeatedly starting the test program and vibrating fewer and fewer modules, the malfunction can be localized to within one or two modul es. After isolating the mal function in th is manner, check the seating of the modules in the connector; check the module connector for wear or misal ignment, and check the module wiring for cold solder joints or wiring kinks. Circuit Troubleshooting The procedure followed for troubleshooting and correcting the cause of faults within specific circuIts depends upon the down time limitations of equipment use. Where down time must be kept at a minimum, it is suggested that a provisioning parts program be adopted to maintain one spare module, power suppl y, or standard component which can be inserted into the cabinet when system troubleshooting procedures have traced the faul t to a particular c0'1!ponent. Static and dynamic bench tests can then be performed without interfering with system operation. Where down time is not critical, the spare parts I ist can be reduced and module troubleshooting procedures can be performed with the modules in-I ine (within the system). Although in-I ine module troubleshooting extends the down time of the system, it is economical of personnel time because the module can be program exercised to locate the cause of the fault more rapidly. Module Circuits Circuit schematics of each module are supplied in Section 10 of this manual and should be referred to for detailed circuit information. The basic function and specifications for standard systems modules are presented in the System Modules Catalog, C-l00. The following design considerations may also be helpful in troubleshooting such standard modules: a. Forward-biased silicon diodes are used in the same manner as Zener diodes, usually to provide a voltage differential of 0.75 volts. For instance a series string of four diodes is used to produce the -3 vdc clamp vol tage used in most modules. b. The state of DEC flip-flops is changed by an incoming pulse which turns 9-29 off the conducting transistor amplifier. Since these flip-flops use PNP transistors, the input pu Ise must be posi tive and must be coupl ed to the base of the transistor. FI ip-flop modules that accept negative pulses to change the state invert this pulse by means of a normal transistor inverter circuit. c. Fixed-length delay lines such as the 1310 and 1311 are extremely reliabl e and very seldom mol function • However, if a mal function should occur, these delay I ines should not be replaced on the printed-wiring board. In such cases the entire module should be returned to DEC for repair. d. Each 4301 Delay module consists of an input buffer amplifier which is transformer-coupled to a monostable multivibrator. The multivibrator output is directl}< coupled to a level ampl ifier and transformer coupled to an output pulse amp Iifier. e. ihe 1607 and 4603 modules both contain three independent pulse amplifiers, each with its own input inverter. Output pulse duration is determined by the time required to saturate the interstate coupl ing transformer. No multivibrators or other RC timing circuits are used in the pulse amplifiers. f. The 4604 and 4606 Pulse Ampl ifier modules both contain three independent circuits, each containing a monostable multivibrator and an output pulse ampl ifier. The period of the multivibrator is establ ished by an RC time constant which is determined by external connections to the module. The output from the pulse amplifier is determined by the period of the monostable multivibrator and so ranges between 0.4 and 1 microsecond. In-Line Dynamic Tests To troubleshoot a module while maintaining its connection within the system: 1. De-energize the computer. 2. Remove the suspect module from the mounting panel by meanS of a 1960 System Module Puller. 9-30 3. Insert a 1954 System Modu Ie Extender into the mounting panel connector which normally holds the suspect module. 4. Insert the suspect module into the module extender. All components and wiring points of the module are now accessible. 5. Energize the computer and establ ish the program conditions desired for troubleshooting the module. Trace voltages or signals through the module, using a dc vol tmeter or an osci Iloscope, until the source of the faul t is located. In-Line Marginal Checks Marginal checks of individual modules can be performed within the computer to test specific modules of questionable reliability, or to further localize the cause of an intermittent failure which has been local ized to within one module mounting panel by the normal marginal checking method. These checks are performed with the aid of a modified 1954 System Module Extender. To modify an extender for these checks, disconnect the small wire leads from terminals A, B, and C of the connector block, and solder a 3-foot test lead to each of the three wires. Attach a spade Iug, such as an AMP 42025-1 Power Connector, to the end of each test lead, and label each lead to correspond to the A, B, or C terminal from which the wire was disconnected. To marginal check a module within the computer: 1. De-energize the computer. 2. Remove the module to be checked from the module mounting panel; replace it with the modified extender, and insert the module in the extender., 3. Connect test leads A, B, and C to the appropriate terminals of the colorcoded connector at the end of the moun'ting panel. The module being checked can draw the power from the marginal-check power supply via the green (+10 vdc) or yellow (-15 vdc) terminals, or from the normal power supply via the red (+10 vdc) or blue (-15 vdc) terminals. Note that the marginal check switches at the end of the rack should remain in the down position during the entire procedure. 9-31 4. Restore computer power, adjust the marginal-check power supply to provide the nominal vol tage output, and start operation of a routine which fully uti Iizes the modul e being checked. The procedures and routines suggested in Preventive Maintenance for use in marginal checking the computer can be used as a guide to marginal checking modules. 5. Increase or decrease the output of the marginal-check power supply until the routine stops, indicating module failure. Record each bias voltage at which the module fails. Also record the condition of all operator console controls and indicators when a failure occurs. This information indicates the module input conditions at the time of the failure and is often helpful in tracing the cause of a fault to a particular component part. 6. Repeat steps 4 and 5 for each of the three bias voltages. If margins of ± 5 volts on the ± 10 vdc suppl ies can be obtained, and the -15 vdc supply can be adjusted between -7 volts and -18 volts without module failure, a module can be assumed to be operating satisfactorily. If the module fails before these margins are obtnined, use normal signal tracing techniques within the module to locate the source of the fault. If an external dual-voltage variable power supply is available, such as a DEC 730, perform steps 1 and 2; connect test leads A, B, and C to either the normal machine power supplies at the red (+10 vdc) and blue (-15 vdc) terminals at the end of the module panel or directly to output at this supply i then continue the procedure from step 4. When using this connector, the ground connections of the dual-voltage supply must be connected to computer signal ground. This connection can be made to the black connector at the end of any module mounting panel. Static Bench Tests Visually inspect the module on both the component side and the printed-wiring side to check for short circuits in the etched wiring and for damaged components. If this inspection fails to reveal the cause of trouble or to confirm a fault condition observed, use the multimeter to measure resistances. 9-32 CAUTION Do not use the lowest or highest resistance ranges of the mul timeter when checking semiconductor devices. The X10 range is suggested. Failure to heed this warning may result in damage to components. Measure the forward and reverse resistances of diodes. Diodes should measure approximatel y 20 ohms forward and more than 1000 ohms reverse. If readings in each direction are the same, and no para II el paths exist, repl ace the diodes. Measure the emitter-collector, collector-base, and emitter-base resistances of transistors in both directions. Most catastrophic failures are dueto short circuits between the collector andthe em itter or are due to an open circuit in the base-emitter path. A good transistor indicates an open circuit in both directions between collector and emitter. Normally 50 to 1OOohms exist between the emitter and the base or between the collector and the base in the forward direction, and opencircuit conditions exist inthe reverse direction. To determine forward and reverse directions, a transistor can be considered as two diodes connected back-to-back. In this analogy PNP transistors are considered to have both cathodes connected together to form "the base, and both the emitter and collector assume the function of an anode. In NPN transistors the base is assumed to be a common-anode connection, and both the em itter and coil ector are assumed to be the cathode. Multimeter polarity must be checked before measuring resistances, since many meters (including the Triplett 630) apply a positive voltage to the common lead when in the resistance mode. Note 1hat although incorrect resistance readings are a sure indication that a transistor is defective, correct readings give no guarantee that the transistor is functioning properly. A more rei iable indication of diode or transistor mal function is obtained by using one of the many inexpensive in-circuit testers commercially available. Damaged or cold-solder connections can also be located using the mul timeter. Set the mul timeter to the lowest resistance range and connect it across the suspected connection. Poke at the wires or components around the connection, or alternately rap the module lightly on a wooden surface, and observe the mu Iti meter for open-c ircui t ind ications • 9-33 Often the response time of the multi meter is too slow to detect the rapid transients produced by intermittent connections. Current interruptions of very short durations, caused by an intermittent connection, can be detected by connecting a 1 .5-volt flashlight battery in series with a 1500-ohm resistor across the suspected connection. Observe the vol tage across the 1500-ohm resistor with an oscilloscope while probing the connection. Dynamic Bench Tests Dynamic bench testing of modules can be performed through the use of special equipment. A 922 Test Power Cable and either a 730 or 765 Power Supply can be used to energize a system module. These supplies provide both the +10 vdc and -15 vdc operating supply for the module as well as ground and -3 volt sources which may be used as signal inputs. The signal inputs can be connected to any terminal normally supplied by a logic level bymeansof eyelets provided on the power cable. Type 911 Patch Cords may be used to make these connections between eyelets on the pi ug. In th is manner logic operations and vol tage measurements can be made. When using the 765 Bench Power Supply, marginal checks of an individual module can also be obtained. Repair In all soldering and unsoldering operations in the repair and replacement of parts, avoid placing excessive solder or flux on adjacent parts or service lines. When soldering semiconductor devices (transistors, crystal diodes, and metallic rectifiers) which may be damaged by heat, the following special precautions should be taken: a. Use a heat sink, such as a pair of pi iers, to grip the lead between the device and the joint being soldered. b. Use a 6-volt soldering iron with an isolation transformer. Use the smal- lest soldering iron adequate for the work. c. Perform the soldering operation in the shortest possible time, to prevent damage to the component and delamination of the module etched wiring. 9-34 When any part of the equipment is removed for repair and replacement, make sure that all leads or wires which are unsoldered, or otherwise disconnected, are legibly tagged or marked for identification with their respective terminals. Replace defective components only with parts of equal or greater qual ity and equal or narrower tolerance. Spare Parts For rapid maintenance and minimum system down time it is suggested that the following spare parts be stocked at or near each installation: 1. A complete Model 33 Automatic Send Receive set by Teletype Corporation. 2. The quantity of transistors and diodes listed in Table 9-7. 3. The quantity of miscellaneous spare parts Iisted in Table 9-8. 4. The quantity of Potter Instrument Company spare parts listed in Table 9-9 for systems containing Type 50 Magnetic Tape Transports containing the Potter Instrument Model 90611-2 mechanism. 5. ~5W 01 BRN IN'::09 TI ~ lTV 5% 50W 7511 2W ~'lTf: 10% Fl2 ~,;5W ~3A 55W ylL v GRYI ORN 7 r N BlK 5,6 - ..SOV Fo 4 04 " E 3SO J 01 ,,~ ~ C6 950 _;::; MFD 75V + Q2 2N456A ~A~W vv UNLESS OTH ERWISE INDICATED: RES ISTORS ARE 5· % CAPACITORS ARE M MFO : 1 AMPHENa.. } BLK BRN GRY/WHT o } 1~~18 E , TO THERMI5TERS FENWAL TYPE JA41JI OR E:QU!V. OH GRY/GRN Fl9 VEL TEMPERATURE COEFFICIENT: I -0.5 % PER DEGREE C WHEN PINS V,W AND Y, Z ARE SHORTED 2 -0.8 % PER DEGRE E C WHEN ABOVE PINS ARE lEFT OPEN. WHT 9 ~ 99 25W 3 FI S R6 10 2SW RS BlU M CONTROL OJ GRN r-K F GRY IYEl 0--- P 1701 POWER SUPPLY PLUG -IN UNIT ......_A +."-,;3 03 )BRN IN!208 PLUG 126- 198 >2ZO Fli :> BRNI~~209 ..:r:g 04 AMPHENOL ~ ~!Ng3~BB C7 R8 02 IN3208 BR FlN ... I5 + ,C$"-' ......, BLU 8 1 ~ FlED tfj GRY/BlK B -311 bT.J. J $R4 950 MFD GND 220 2W 10% :~I~~16a 1711 ,% 50W GRY/vra..ET f~~J· -....0 -13 FlW}AMPHENOL E - 35V PLUG 126-198 Bl.U Power Supply RS-735 A+IOV(AI r-------~--------------~r_--------------------~--------._--------_+------~~-----_oM .REO DOT 01 IN429 FlJ 2.000 R22 .;-t--+--"""H 10,000 WW .-------~-r------~N 02 0-662 r-------~------------~------------------~----~~------------~_+----__oE • RED DOT R21 03 IN429 10,000 RI3 2,000 :>O-~---- --- " DI , . O. D3 D2 ~ ~ I-- " D'9 D·662 C2 .01 r·OI ! " ,-0 ;> 010 0·662 D5 I I , D6" ~ " >--- DII ~ t Dl~ DI3 ,,014 I ~ ~ >--- R9 RIO 1,500 5% RII >',500 5% 016 DI5 ~ '-- R7 { RI 1,500 5% ;. R2 I,SOO R3 1,.500 5% ( 5% ( R4 ',500 5% S 05 S·,5 OC 5% ~ ~ eo';;: 1,500 5% 1 I AS 1,500 5°/.. 1,500 5% 1 UNLESS OTHEWISE INDICATED: RESISTORS ARE 114"; 10% CAPACITORS ARE MFr oIOO£S ARE D-664 Clamped Load Resistors RS -1000 RI~ RI2 1,500 ~ 5% i,.500 ~ 5% ( ( RI. 560 112W J'o Diode RS-10ll Memory Diode Unit RS-l020 10-13 ., ., ., ., ., ., >--...r----6 C -1511 CS .001 MFO _If 012 E 0 F 0 H 0 ---....---'C{ .r.. ~ n __ I 0 ..--..1...--9_--0 I 1 A I 016 ~662 i i 05 R4 _A ., ., r 04 R3 I 5600 I 0 R9 68,000 vV' ,... I 014 ~-662 0 >--I~-6 I 02 CI .001 ...... 1 I 013 I f----.t-~6 RS R2 5600 68,000 MFO ~9-n 01 UNLESS OTHERWISE INDICATED RESISTORS ARE 1/4 W, 10%. DIODES ARE 0-001 .... 1 I I 03 TO 68,000 5600 YV- C2.001 MFO P 0 >--I~-9_--- ., ., W RIO 1 1015 !-662 >--~-6 ~ 0_ V- 1 --.r---o---~( ~ S RII yv 68,000 R5 5600 MO R R 12 68,000 5600 C3 .001 MFO 06 NO + 101liAI C4 .001 MFO De L ~662 I 0 ----.r-----O 07 RS C5 .001 MFO I' 1017 I K .... I 010 09 I 1018 02S62 011 J A A 1- 662 1 R7 R I 5600 68,000 Di od e RS - 10 1 1 D-g~7 n D-O~~ ~~ , ---4 ------1 i -- I I • DI D-007 i • ~~00~7 -- ~ I I I D8 0-007 D_~067·· .03 . [)-007 • D5 0·007 A DIO A~ 0-007 D7 0-007 I ·~~'~07 A~~'~7 1 I 1 ~ ~ II D_~~;n DI4~~ 0-007 I j. g~g07 0-007 I I I ) ( 6 ( NOTE REFER TO MAO-B-1020 FOR MEeHAN ICAl ASSEMBLY AND DETAilS Memory Diode Unit RS -1020 ( J ( 1 Binary-to-Octa I Decoder RS-1151 Delay Line RS-1310 10-15 ~-----..,...~-Q-,----f"-------~------f"------"1----::.-::.-::.-::.-::.-::.-::.-::.-::.-=--::.-::.~-::.-::.-=--=--=O~OAptlOlrlA! ">~.------_t-----_f" RI '~> R2 R3 ,,~ <;. R5 ).~ R6 '~> R7 68,000~ RS < , ~ 9 68,000 66,000 <> ~ <> 68,000 68,000 68,000 68,000 > < 68,000 <:> < :r1 ,fJo r1 ,f;, I,J .~;, ,J .:;, ,J ,:;, ,J .::' I,J .g., ~~ ~~ ~~ ~~ ~~ ~~ ~~ i-F-~ ~ ~ f-- ~ <> > . - - - -.....--1p-Q0 ~ .g:, '~o:;, +~) ~ ,,~028 ..027 D-662 .01' "~032 RIS_> -" -' ~, O:~ r.FO ~,. D44 D-002 < 5% ~'D421 C2 >-0; ~ GNO ';> ~, 049 045 0-662 ~r ~ OS, -"050 -' 0-66< D-66< ~r ~ 052~1' II 0-662 ? 0-662 .----r--~~~_i-~~_t-_+--1-4r--;_--~-..,...-+_-+-_t-_+---4-~-~-~~~_i--4----~----~~_C-15v R9.> -" 2.000~> .. ~ DI RIO.~ ~, RII"> ~_~D3512,000< RI2 ,:? ~, D3612,o00~ RI3 ~ " RI4"~ . , RIS ~>~.~D39'2,o00<, RIG.> " 033 12,000< D-662 ;> f-D34I 2,OOO?> D-662 0-662 D-662 > 038 12,00°< D-662;> 037 ' 2,00°<' D-662 ~~02 .. ~_03 ~~04 ~~05 ..i~06 ~~.07 ~~OS .. ~D9 ~~DlO .. ~011 ..i~012 ~~013 .. ~014 .... DIS A~016 .... DI7 ;> 0-662 ~ ..i~020 .. . . . . 018 Dl9 .... 021 r040 0-662 ..~022 .. ~023 .. ~C24 a L~IOC~==t===t==j~===t==~:===:==~===~===t==~~==~~==::===~==~===1==~~==~===~==~===~==~+--~~~~ ~ J~lo--~-~---~~---~-~----~-~---~-~--~r-~---~-+----t-~ H oo--+--~---~~~--~-------r------r-~--~r--J UNLESS SE INOICATEO: RESI STORSOTHERWI DIODES AREARE V4 'II, 0-001 FFF'o--r-------r-----_i-----;_-----~----~------A-----~ E Oo--~-----~----~------~ 10% Binary-to-Octal Decoder RS -1151 ~------------_+---~~-----4r----_t----4r----~------4r--~----------------------~D~ RI R3 330 10,000 R4 68 J K L 68 w M UNLESS OTHERWISE INDICATED: RESISTORS ARE 1/2W; 10% DE I = TECH N I TROL 0.2 ~ sec DELAY LINE 330 OHMS TAPPED AT 0.051' sec. INTERVAL DE2= TECHNTROL 0.2 I' DELAY LINE DE5 01 0-003 Rli sec. Delay Line RS-1310 Delay Line RS-1311 Crystal Clock RS-1406 10-17 r-----------------------~------~--------------------------~----------------------_t------_1r_---------------------------rODGND R5 330 1'12 330 n 1 n Fli 1!1 illl J K 1'14 180 L M 1 ill 111 U 1/ W T UNLESS OTHERWISE INDICATED: RESISTORS ARE 114W;· 10% DE I !:I DE2 ARE TECHN ITROL DELAY LINE 0.2 ~ sec 330 OHMS TAPPED AT 0.05 ~ sec Delay Line RS -1311 A+IOV(A) +rOVIS) C4 .01 MFD C7 .01 MFD D GND 06 D-662 1'12 270 FlI9 220 5% 02 IN14B 3,911 l/ZW 06 ofC2894-3 RIO iOOO 5% MFD C2 220 . 2 D3 01 IN748 1'17 390 3.91/ UNLESS OTHERWISE INDICATED: RESISTORS ARE 114W; 10% CAPACITORS ARE MMFD DIODES ARE 0 ·664 FOR VALUES LI, CI,CR-I SEE DRAWING A-00511 L r 03 2N3009 TI T2008 I fill 82 1'114 470 5% 1'15 470 l/ZW I/2.W Crystal Clock RS - 1406 J .01 MFO C-1511 Duo I Sense Ampl ifier RS-1571 10-19 ~~-TRS 4,700 R25 1,500 5% 1% CI 39 MFO R9 220 C3 39 MFO .( RIS --II---=~f--c <;56.000 til 1 + IOV- '1% !' ~ • Q3 MD« INPUT ED-l- - ~~~__ S270 1 ·\'~D --1t- R6 4,700 RI7 1% 2,200 4,700 R7 1% I > RI3 ;>' 4,700 II ~9 MF~ +!ovi--'\,~ C2 I Q2 YO-- --- {:co. -- ,~: C5 39 MFO c-tv+ f' r o , _ ---Of R Ie 5% -,56,000 ---- ,,~'''~ RESISTORs~RWISEINOICATEO'~ R24 RI9 J I I ,02 066 C8 ~WfNE~SAT~~~Ai~~::~o 4~78001 1~--- '''''''M':' ".w, 00. 1% ,;g A8 112W ~ .00" ,I , RI4 R31 4,700 :2,200 • ; __ 016 ~ R47 :i~ 13 "lTf2!02~ ~SEI I 5% ~*- I!ZW I ~T + M - P 1m .01 MFO CI3 01 MFO R~" 220 5% 2 200 112W C-15V 6L --. OUT PULSE IN R43 68,000 - 1_- " ~- , r 500 1, Q --I t ---~------T----- ~~'4 I 10 I i T '" • --.. ".::y~ _~J : . ) e~o t~\ I R46 270 J: I L , : Lfv E L 00 T Dual Sense Amplifier RS-1571 ,1'[I'I;'.,i [J t"" I - t 3,000 T 5% i PULSE IN ~- , ~-lc'2 82 6- J ~ ! , 016 2NI309 I:~" ""o;;·,l';II~:E ~--:~ .l.CIO OOO «~,\ fl:::~6~06~_ _ _-. - iG I 6R OUTPUT RS3 ~'----.l' R40~ - 1 b ; . i!et PRE-At.1P ~ CI I R42 3,000 ~ 82 1 220 5% - ,--- OK L! t- --- - -1--~ I : I 270 t LEVEL +- ~- 06 t--------.J I I I ' ~R4S ~~ "'1 R34 6,BOO Gl6 ~I - f ~H'· .,,1 __ : tu~ 1'000: • _- ' R--------- 250 i 1 __ ~ 0-662 R28 I t- ,600 I t'S,OOO ~ ~~26~FD 4;0~0 ' '~[j ---I r-- _( _ I_ t4;_~~_O _-i------t--I o GNe 08 I , -----t--- ~if\ _____ YDS +IDVIB) I R27 1,500 _I R37 --,- - OUTPUT _ f R35 • PRE-AMP ) t-------t _, i MO~~ MOJl4 s,,:p;----tr-\ RIO uo ! l 390 12w J-t r---..J , j R31 I 1 I' R39 • ~_ j, I : t-- -\hj : j t--- 1' - I I 1- ~-, --- ----=~I[--', . - "~ ,~" :'f ", fel --I % -11 t 002C27~FO i -~B R41 --r- -f- 01 0-G62 --~ - - - - - - - ' 0 A +IOV(A) , 68,000 f ! RIG 4,700 C4 0022 R3 R33 6,800 -IOV+ MDI14 RI t RII 4,700 1% -! R48 2,200 R5~ 220 5% 1/2W R 50 I 2;~_ , - ---- CI4 ,01 MFO ~ R56 220 I!2W 5% Difference Ampl ifier RS-1572 12-Bit Digital-to-Analog Converter RS-1574 10-21 B+IOY (81 R~3 681 C2 .01 I~ MFO D GNO 02 tEC2B94-3 05 018 07 DEC 2894-3 DZ 0-664 lei 014 0-664 017 r MFO ~Z894-2 W 016 DIS I 01 0-864 03 UNLESS OTHERWISE INDICATED: RESISTORS ARE 114W; 10%. R3, R5, R6,R7 AND RI3 ARE LOW- .01 MFD ~~:~ ~OI~/~TALLIC FILM DIODES ARE 0-6e2. R4 IS A CHICAGO TELEPHONE SUPPLY co. METAL FILM POT. ~:O RIO All ,800 R9 750 5% 112W 6,800 012 5% 112W 011 RIZ 560 1/2W 010 L-------~----------------~~~~~--------------4_----~------------~--------------~~_4--_oC Difference Ampl ifier RS -1572 RI2 1000 .::!:O2% RIO 9945 !O2% RII 1965 :to 20;., RI4 1000 R 13 965 RI6 1000 R 15 1%5 RI8 1000 R 17 1965 R20 1000 R22 1000 R24 1000 R 26 1000 RI9 1965 R21 1965 R23 1%5 R25 1965 R6 60 R7 60 RS 60 R9 60 R 28 1000 R27 1998 IW M R:50 I R2 60 R3 60 R4 60 R5 60 J w UN_ESS OTHERWISE INDICATED RESISTORS ARE AC! ME~AL FILM 05%, 1/2W RIO· R 8 ! 10 ppm ("c Rig- R22 :!: 50ppm/oc R23- R34 ! l50ppm/oc POTENTIOMETERS; c.AYSTROM TYP~ 510, ± 5 %, :!:50 ppml'!RI: RESOLUTION OF .55%, MAX. END RESISTANCE OF 211. R2- R9; RESOLUTION OF.6 %. MAX. END RESISTANCE OF 0.511.. 12-Bit Digital-to-Analog Converter RS-1574 R30 1000 R29 1998 R 32 1000 R31 1998 R 33 1998 R 34 1998 -'!IV Pu Ise Ampl ifier RS-1607 Bus Driver RS-1684 10-23 .-----------------------------------------------------~--------------------------------------______OA+~(A) .---------------------------------+------------------------------------------~B HOI/(8) ~--~t---~------t=============+=+=~==~====~====~============~~~~==t===:;=====+=============+~======~==~==~:8~~~ DI6 R28 10 ~1 MFO 019 D·662 lCIl .01 MFO R30 01 150 -5'lro II2W UNLESS OTHERWISE INDICATED: RESISTORS ARE 1/4 W: 10 "t. CAPACITORS ARE MMFD DIODES ARE D-664 Pulse Ampl ifier RS - 1607 r-------------------------------------~~~----~--------~~----------------------------------~------~-------------OAtlOV~1 .-------~----------~--------r_------t_----------~------~------~----------~------_t------~--------_____OBtlOVel it 150 1 L-----_4--_4--------~--~==~------~--~--------~--±_--~----~--~--------~_4----+_~~--~E-3V L-______~~__+-~ ________ INPU T I OUTPUT I UNLESS OTHERWISE INDICATED: RESISTORS ARE 1/4 W; 10% CAPACITORS ARE MMFD +_--~-------4--~--~------_+--~--------~--~~~----~--~--------~--+_--~------~QC-15V M INPUT 2 U INPUT 3 Bus Driver RS -1684 INPUT4 Bus Driver RS-1685 -lOY Precision Power Supply RS-1704 10-25 r--~------------~r---------------------~--------~--------------~--------------------------~---oA~10V(AI ,--------,-----------+----------t---------------+-----"""?'""---~---------_+.__{)B+ IOV(8 I r---~r---~---~-_+---_+---+_-_.----4~·~r_-~r_-~---~--_+---_+----+_-_?-~-~--_t~--oo GNO 011 0-003 1>31 560 1/2 W ~~~~~JL-----~==========j:==============:t:::::::::jt::::::::::::::::::::i====::~L--1--------~c-I~V UNLESS OTHERWI SE INDICATED: RESISTORS ARE 114 1M; 10"4 CAPAC I TORS ARE MM FD Bus Driver RS -1685 r-~------------------~_.---------------_.-------------~------~~----~--_.------t_OO R3 27,000 I%,WW +SENSE RII 1,000 R4 .27,000 5'l1. 1%,- RI4 150 RI3 1,000 5'l1. RIB 56 3W 0--.....-----;-+---.....----, T 03 2NI309 01 IN3496 GND RZZ I RI9 56 31'1 CI . IMFO B.2V is'll. 100 II2W + 06 05 2N2218 Fl23 2N2Z18 C3 47MFD 20V ~--+-+--+--+~ M TP RI5 470 RI6 + 10,000 100 WW CW TP R6 425 I%,WW Y cz 47 liFO ZOV R2 02 0-662 ~-------+_----------~------------4---------~------~----._--------------~~----+_OE· RI ·450 0.1% WW - SENSE Z R21 40 !5'11. 0----------------------------.. . UNLESS OTHERWISE INDICATED: RESISTORS ARE 1/4 ... 10% RIO, R6 AND RI ARE DAVEN 3 PPM TYPE 1195 R3,R4,R5 AND RB ARE DAVEN 20 PPM TYPE 1283 R2,R9, ARE 50 PPM D.U'STRUII TRANSITRIM -10V Precision Power Supply RS -1704 lOW L---------------------......-oC -1!lV Resistor Board RS-1976 Res istor Board RS- 1978 10-27 R3 50 J C2 112~ 3W R5 JC3 50 1/2"" rr 1 R4 I '... X R6 w UNLESS OTHERWISE INDICATED" RESISTORS ARE 47 OHMS I·k CAPAC I TORS ARE 4700 MMFD 1% Resistor Board RS -1976 M CI 4700 1% C2 4700 I'll. 112 47 1% R3 220 R6 220 C3 4700 I'll. C4 4700 1% I". RI147 1% 'II C5 4700 I'll. FlI2 220 C6 ~!! 4700 I'll. 4700 I'll. 1% RI8 22.0 1% T R21 220 R24 220 ~----------~--------~~---------+----------~----------~--------~----------~---oP-3V ~ +~FD 10V D GND UNLESS OTHERWISE INDICATED: RESISTORS ARE II2W; 10% CAPACITORS ARE MMFD Resistor Board RS -1978 Inhibit Driver RS-1982 Read-Write Switch RS-1987 10-29 -+----~----------------<_----------f_---_oA + 10VIAI ul4 0-001 M:j' IN 131 R8 1,200 N~ L~_+--~--+--l 013 D-OOI DI7 D-003 L--_+..-I--__________ --- - RI4 820 --+-------II----+--~--O -:9 IW GNO 1 - -9 22,O 0~4 ... GI ~ >.:'-70 ~ ~ RI 1,200 ~~3 '"'" Q4 GA212 >R3 IZPOO RS 820 1111 ,~4 023 ~4 < '~. Q3 1/2W ... R20Q 470 QI2 GA212 1/2111 \.S,) Z Q ... QIO 112) ~ GA21~ ~31 RI!! 1,200 ~9 20 1111 , ~'O , ,~'2 ~" 11100 T(Z) D~2 (zz.oooi Q9 027 D-007 ~ ,~2 OZB D-~007 Q2 0-O'~7 ,~' R6~ >i,~~ 019 Y OUT (I) RI7 IZPOO RI9 820 .J...W ... QII ~i7'Q X < RIB 820 1111 v T- 35" r- g!g~ R9 ZZjX)O O~Z ... 1i5 RI3 470 IJZW ~ ~ \h 017 0-007 I ,~5 ,r ~~8 «2- D26 0-~7 ..... Q8 GAZI2 >,RI4 470 1/2111 £21 >~,~O ~ RI2 820 IW >r" 820 IW ~" . 07 GA212 - Q < R22 1,200 ,~'3 {4 1.,~'5,~6 >i/~~ GAZI2 ~Rf~ QI5 GA21Z IlIo4 ~ V GNO >R27-Q O.~T \S, .... o POUT (41 ~O 025 Q6 RS 1,200 ,~6 U 0U1t3 ~ R24 < 12.000 RZ6 820 fW ~ ~9 ... R25 8Z0 IW I/2W Q R v o 6 ( H b ( L M Read-Write Switch RS-1987 S BUS UNLESS OTHERWISE IN DleATED RESISTORS ARE 114 W,IO% DIODES ARE 0-003 TRANSISTOR ARE M M999 Memory Driver RS-1989 Inverter RS-4102 10-31 r-----------------~-----------------------------------------------------------------------------oD GNO r-----~--------~------_+-----------------------------------------------------------------------------oA+10V(A) r-------------------------------------------------------------------~~--OZ GNO + - R4 68,000 R2 39,000 ~~~----~------~----_1~--~._----_1------._----._----~--~----._--+_--~R-3V ISOMFO 6V C4 RIO 47 Ri 31)00 5% RI8 10 R20 10 C6 50MFO - C3 1'270 CI 56 ..1 SOV R6 ~ C7 .01 MFO 5,600 04 0-003 ~----~------+_----~----~~----~----~----~~~r_--_r--_r---oV OUT RI9 10 R21 R23 10 10 R25 10 R27 10 C9 .22MFD 01 I(EXT. C5 .22MfD 1 I ~M:NER I NECESSARY) I ~----------~~----------~~----------~--+_~~~~--_r--_r--_oM d~~o R7 R3 2,200 150 IW 5% UNLESS OTHERWISE INDICATED; RESISTORS ARE 114W; 10% CAPACITORS ARE MMFO TRANSISTORS ARE 2N2904 Rg 2200 IW RII 470 2W L-----------------------------~----------_r--1_--_oX -13V VARIABLE L-__~----------------------------------------------------------------~--+_--~T-35V C -15V Memory Driver RS - 1989 r---------~---------1~--------._--------_.----------._--------~--------~~--------~--------------------_oA~I~~) r----4r---~----1_---1----_+----._----+_--~----_+----r_----+_--~----_r--~~--~----~----~--~--_.--~0 GNO 012 0-662 CIO . ----~OT 02 R O>-----t~I+-~ IN S 0 - - -.....01--4-, 01 UNLESS OTHERWISE INDICATED RESISTORS ARE 114W,10% CAPACITORS ARE M MFo DIODES ARE 0-003 OUT DI2 W OUT D22 Z OUT x U Q-----1~-... IN IN yO-09 01' 019 021 029 C -15\1 Diode RS-4113 Negative Diode NOR RS-4114 Positive Diode NOR RS-4115 10-37 ~----------------------~r-----------------------~~----------------------~~--------------------------------~A+IOV(A) ~----------------~~--~~------------------r-----~------------------r-----~--------------------------~B+IOV(BI RI R3 120,000 I20,o0o RI3 R15 120,000 I20,o0o r-----------;-----_r------~----------_r----_r------~----------_r----_r------~------~r_--~--~_{)O C04 120 R6 2,200 5% r 04 E~ ':ij I I 09 I 01 ":ij ':±j 06 C6 OI T·MFO I :~ 011 015 U 010 019 0-662 I 017 I S N 05 t UI3 07 D2 H 14 2,200 5% I I L0---!4-----1 GNO Y 014 018 P J R4 1,500 R8 1,500 5% 5% RI2 1,500 5% RI6 RI7 560 V2W 1,500 5% L-------------------------~------------------------+_------------------------+_------_4------~~_oC-15V UNLESS OTHERWISE INDICATED: RESISTORS ARE 1/4W; 10% CAPACITORS ARE !.!MFO DIODES ARE D-6M Negative Diode NOR RS -4114 r---------------------------------------------------~----------------------------------------------------~A+~V~ ~------------------------~----------------------~r_--------------------------~B +IOV(~ R2 R5 68,000 68,000 R8 68,000 r-----------------4-------._----------------~------~----------------4_------~------~----._~~_U0 017 [III 04 010 D3 H DI R3 1,500 5% 07 022 016 D21 .,~ u DI4 08 P r W DI!! 'jj C6 02~ ':E T M D2 I 020 I I I I I RI 12,000 UNLESS OTHERWISE INDICATED: RESISTORS ARE 114W. 10%. CAPACITORS ARE MMFO. DIODES ARE 0-664 TRANSISTORS ARE OEC289 - R4 I2POO R6 I,!!OO 5% R7 12,000 R9 I,!!DO 5% GND RIO 12,000 ~ 5% 13 so 1/2W C-1511 Positive Diode NOR RS -4115 Diode RS-4116 Positive Diode NOR RS-4117 10-39 ~------------------------------~--------------------------------_T---------------------------------oA+1OVIAI r-------------------------~----~r_------------------------_r----_T--------------------------~B.IO~~ RI 12OPOO 117 R9 120POD 120,000 ~------------------~----_r----~--------------------~----~----~----~------~r_--~OO L T- Re R2 2200 2200 I 07 01 OI 013 I -:E uo--4~--+-----~ 08 02 H~:tJ03 ~ J 016 X 017 Oil 05 K y S os I 0iS : : ± J 0j 04 I'" 014 09 RIO 1500 Ril 1500 5"" 5"4 ole RI2 1500 5% RI3 ~60 112W ~------------------------------~--------------------------------~----~--------------~C-15V UNLESS OTHERWISE INDICATED: RESISTORS ARE 1/4Wj 10% CAPACITORS. ARE MIIFO DIODES ARE 0-664 TRANSISTORS ARE 2894-4 Diode RS -4116 r---------------------------------------------------------------~------------------------------~A+~~) ..-------------------------------+------------------------------~B+ R2 IOV(B) lie RS 68,000 Ei8P00 68,000 r-------------------~----------~------------------_+----------~--------._--_.----~~O GNO Z T 05 II 04 012 03 011 020 019 W 02 DID 018 R 01 OS RI IZPOO GNO 09 Dl6 R3 R4 1,500 12,000 5% 017 024 R6 R7 R9 1,500 12POO 1,500 5 .. 5% L-______~~--------------__~--------~----------------~--------~------~--------~C-~ UNLESS 01l£RWISE INDICATEDRESISTORS ARE 114W; 10.. DIODES ARE 0-664 Positive Diode NOR RS -4117 Negative Capacitor Diode Gate RS-4123 Pu Ise Inverter RS-4127 10-41 A +IOV (AI RI 68,000 J">. D! R3 1,500 5% I;~O I,~~ , '02 T ).. .. 1 C2 330 " 1 .. DI3 p C>----< 016 ... T RI9 p 6~0~0 « R20 100 5% RII 330, ~~OO I J.- 0159' K OJ 9 RIS 10,000 ,.. '2"8 C7 330 330 .... I W HO P ~iOO ;io* I ~ R22 ~ • D22 1,500 1500 5% ~ R23 ~ .. D24 5% U 0~~~2 " ~ ,,031 D-662 z CI3 " 030 0-662 "01 MFDf I A~ 028 I I ~ 021 ti "5% R29 560 1/2 W R25 -'l.R].4 I~~Y D GND D33 0-662 D;: ;~~ , 020 .. ~ D23 I >:00 ~~~'''' 11 ~ i A 90<18 R8 1,500 R 28 1,500 5% .JyYV OF N X90<,7 ( R27 33,000 --QE Q2 MDI14 y ( RI6 iOO '" 1 >~14 RI3 018 ~1 0";"2 ,r::, t <'' 9 '00'9 I ~ ~ QI MDI14 ~ ~tl ~ ~, U9 017 v~ I ,; ~'- R2 3,000 ~ vv J 01 MFO 05 " 5% AA.A RI2 100 R , '04 1,500 5% or v- I,~~ , '03 5% 5% '" RIO 100 R9 I .JI V''' B +IOV (61 .. ~025 ~5~OY !;% ~ ~026 R26 3,000 5% 1'\ C -15V C 12 01 MFD )1 5% UNLESS OTHERWISE INDICATED RESISTORS ARE 1/4 W, 10% CAPAC I TORS AR E MM FD DIODES ARE 0-001 Negative Capacitor Diode Gate RS -4123 r-----------------------------~~----------------------------_.--------------------------------------_oA+~V(AI r-------------~~------------~~------------_;--------------_.----------------------_o8+~V(81 .-------+-------.-------+-----~~------~----~~----~~----_1~----_;------_1--------1_--_.~DGHD + CI3 - IOV 3.9 lIFO 112W ~----~~----~~----~------~~----_;------~------_+-------*-----~~----~~~~--~----~~c-~v M UNLESS OTHERWISE INDICATED" RESISTORS ARE 1/4W, 10% ARE MMFO CAPACITORS Pulse Inverter RS -4127 Pulse Inverter RS-4129 Positive Capacitor-Diode Gate RS-4130 10-43 ~------------------------------------------------------------------------~~--------------------~JA+OVIA) r---------~~------------------------~r_--------------------~B+I~m) R3 33,000 RI~ 33,000 03 09 t------------------r----------4---------------~----------;_--~----~------------<>0 GNO RZI 560 V2W ~----------------~----------1---------_r-----+----------+_--------~----------+_OC-I~V 01 R1 ~500 t E UNLESS OTHERWISE INDICATED: RESISTORS ARE 1J4W; 10% CAPACITORS ARE MMFD DIODES ARE 0-001 Pulse Inverter RS -4129 CB 330 Eo---j R9 F",,500 5% R8 66,000.J RT J Ay 68,000 L -" f r -! R II 1,500 5% ~, g~662 .. 016 A~ 10V(Al ~ o GNO R24 10,000 4~ C5 330 ~ 02 oEC2894-4 03 DEC 2894-4 C9 1,000 ~ ~, g~~6Z 06 J .... Oil P "" e>---1 M ~ 07 C6 330 KQR6 R20 ~ 68,000 . RIO J ,..,:,500 5% J 68,000 ..A ;;0 J o---j H ..... DB .. < RI9 < 12,000 D5 RIZ R5 .,500 5%J 68,000N? v ..- < R21 017 >~~O R25 750 5% II2W 4. -3V 020 A. YV- C4 330 S<>--! RI3 1.500 5°"'1 RoO 68,000 T f' .AA R3 RI4 . 1""1..1,500 5%J V C2 J 330 wc---j , UNLESS OHiERWISE INDICATED RESISTORS ARE 1(4W; [0% CAPAC ITORS ARE MM"D DIODES ARE 0-664 J 3% J YO---1 R 16 I ..... 4~ "g:~62 I ~'~~62 "g:~62 R23 10,000 -:k'?15 ff 01 OEC2894-4 cra \b "g~~62 Q4 OEC2894-4 CII ;; .... 1000 .,,013 D-662 ..J ... ....014 .. Oi r.. , ,500 5%J RI 68,000 Z ........D3 02 R 15 6BR~00 x",,500 5% < RIS >68,000 C3 330 uo--! 68,0~0 D4 ... ~ < RIT < 12,000 < R R22 I,~~O 018 .~ ( R26 ( ~iO ~ ~ ( 112W l~ 019 I J RZ7 >560 < 112W ~ I Positive Capacitor -Diode Gate RS -4130 C-15V Bi nary-to-Octa I Decoder RS-4151 Dual Flip-Flop RS-4205 10-45 r-.~-a-ooo--------~~----------~~----------~-----------'----------~~----------«~----------~<;--------------------~~A+IOV(Al ~>"'" 68,000 6epOO 68,000 > .hJ~\ 01'11305 ~"~2NI305 I!..V...J!. I, , 01 ~~NI!o!> ~~r... I -< .4 .. "00 ~ ,,00, ~~IN6451 < ~[. 2 '1'11305 II j I • >--~ ,,< I I I ~~1~451 ~~N64' ,r ~ 2NIJ05 ' i 2 '1'11305 I i" '''0 11'00 ~'1N645 ~~1 ." D.P GND I 1H645 i 1..01 , '~... ,1 4 ~', T,MFD -,-.01 MFD I 1N6-45 '~"'" I > I I ! ... I 08 r~.. .4~. . .. _ 01 I , ,r~ ,0, '"0'( ~~IN6~ -4). L-€ 0 1 ~tS2M305 ,.,~, I :> 68,000 '> 68,000 S Q6 '2NI305 -----: K0 03 +--'--4 If .~ 02 2 68,000 I I ~~;2~ .---~--+---~--+_--~--~--~--~--~--~--~--~--_+--~--~--_r--~--~--~--~--~--~--~------~~------~C-15V 2,ooo~<» ." 12,000<>" > L I tcFFO J tl FF I 0 ~, 12,OOO,i <> 12.000> 12,000~<> ~, 12.000~<> ." > <> ." !2,O00{ 12'000~~, -" <> > f- ..., . . .~ .~ .~ . .~ .~ . .~ t . .~ .~ .~.. . . . .~ . . .~ .~ . ,." IN64!! > IN645 1N645 ;> 11'1645 IN645 IN645 > IN6.. 5 IN645 I '" 1 ,." ,., FFFI E 0 r. UNLESS OTtlERWISE INDICATED: RESISTORS ARE 114 W, IO'!I. 0100£5 ARE 11'1276 Binary-to-Octal Decoder RS-4151 r----------------------------.-----------------------------_----------------------------~------_{)A + 10VIAI r---+-----------_---------------+-------------------1~----------__+------------__._--------------+_-----_o~IB +IOVIBl .------', < RII 68.000 R7 < 22,000 < c> ( < RI4 68,000 M~O~!4 Mg~14 ~ 1 +07 ~1 06 I,;~~ i ~ONO 2~i~o~ r-' .,.08 R9 1,500 ~~0'664 CI3 R 13 ::CIOtl 3,000 1'50T 5% ....._ ....._-+--:~,O,__14H r : >R5 I < 750 R 18 1 RIO 3,000 5% r~U~~~ 1 R30 68.000 RZ6 22,000 R40 22.000 R33 68,000 < ,~~N~;09(~N~~9 !'-l-'---;~H -.IT''OOOC3 1c1<";,T ::.v " < D GNO Q9 N~~09 ~ 1'~5R~06i40.~; RI9 22,000 OC I~F-' 0013 .I ... ~ 0·664 U l' RI2 1,500 CARRY OUTPUT FFB 1 M~QrI4 lMg~'4 R~ ~ I r--.-T--<~H 0 OUTPUT 1,500::: C IS-.l , r . . . . . . . . , . , lOaAT' FFA~ '~I- 5 0/,(, YI ~:FB i A~ D20'---~-+---------· I OUTPUT +015 RI7 1,0(0 022* > R21 > 750 I R24 750 021 <'128 1,501) ~II>0-664 c~T R32 3,000 5% > t[l~o2°[ ,,~,g~~,- :. 1 < 3,000 R·29 « 5% C19-1150lT ~~0~i6~ " 0~~i2 '----<[ffNI. R39 150 rr--' ,,---I------~Qt::IO+-f UL II ... 03 ~rO-6~2 I " C27 1~03()0IMFD r .023 ~~0~~~2 Y CARRY OUT· UT FFA I D29 2NI309 C25' I RA2 0·28 '~(R38" D'664 •••;OFI0 1 <1,000 755~ I~~OW I ~_2W __._-+_______5_'I._~_1--5-%------_+_--_1--'--;_-j,----;<__5-%-.-2W--t-I-<~t_5-%-.-I-/2-W--__I-------5-.,,___--<_5-%____-I_~__-oi:...._-+'1~/2=-~!!.W......_ _+4{)~,..,-15V R4 1,500 I, I R3 \~O ~HIF{U:S~~2 B-A : ! H CLEAR f 025 D24 D?6 D27 .. All> ~~D4 I 3C3~ ~ t----<.---1 Cb P 37 1,500 II 5% _'-7 *;~6 Z ' J'l I OUTPUT! I! FFA ~H.~-33-0+-j3-0+--1-T~--------+-------~--+-~~~-+~I-----~} 5% I OIN(}J'A 1,5~ 5% ' IIN'f I 033 D2~ All> ~___ C5 .001 MFD j~Off-J1 0 L COMP FFB ;io* L..... r1 R22 1,500< 5% RS 3000 5% ~ ~ R 27 3~~ n}~5Iyb, :'v~",6r+ r.. C24 ~-----+----t,-' -I_P\J-o:S: l'_r:_O_M_/_r:_F_A-++---v' __+--"-:"-__ CI8330 ,---R41 i (;14 330 R34 3,000 330 1.5<:,0}",," I I ~HIFTII 0 IN A B 'I IN .("lu I Ii I( RI5 I, 1 ----J Lf-,50~3~% I FFB~r------*pV~.---_f3~OOO~5~%~------------------------------~--~__+--------~~5~%~_+----I'__+\--------------------~. UNLESS OTHERWISE INDICATED RESISTORS ARE 1/4W, 10""" CAPACITORS ARE MMFO DIODES ARE 0·001 C8 ,..'6.00' MFD FFB SET _. CI7 .,]".001 MFD 1 C 22 ..,....001 MFO ~x '16 FFA CLEAR Dua I FI ip - Flop RS -4205 FFA SET- Trip Ie FI ip- Flop RS-4206 10-47 C27 ~~ r;1MQ T DB _. - I' I 1 , .. R60 1,600 5"10 o ROC MA (MAil -lMAQl 1.500 RI 5"10 U. R42 3.~~0 010 011 ~7 RA CARRY ENABLE RK 100 R6 6,800 !.D4 MB"::MA RRC--MA-MB CIS 1.000 S~~~· R24 ~ ~ R~~~~ 1.500 5"10 COMPLEMENT R32, 3.~~q LEFT ~~_"*-___ ROTATELEVEL C1irtR 11.000 K OR '" EXAMPLE F-I50 r - - ..... - - - - , r - - - - - - -1 II Jisoo I 1 I I 330 : II '5% 4 I ~31 1,1100 1 330 5% ~ L ______ 1 I I 1 4 150 1 1 3.~~0 I I 1 1,500 I 5% 1 I 2 1,500 029 1 (R19 S3.~0 5% 330 SW-MA ~LEVEL 1.500 5"10 Fm R OLEVEL D!,I ... RPo- ~~8 Dj,71~fJ.~6 ,.... R54 • --(ITII-'- IDO,oo~ MB SHIFT 068 X o---+-~1=i!~If1tJl-l COMP MB 074 T o ~J !l,600 t MA COMP rc21 'i9O -083 RF M8O---·----.-----~ COMP ENABLE R40 >3.000 > 15"10 DATA ADDRESS MA 064 R23 1 1 'I .J L _______ J I _ ..r- C~ PULSE} 1 0 _664 I 1 l~oo -.- R39~tJ°·i~ 1.5005"10 081 ",PULSE} EI6 CR-330 .LCIB p. ... ~rrr' RLQ SHIFT LEVEL R22 1 3 ~'\- 1.48 1 1 OO ..........,,68..r·v '-0_ _ I :JM CLEAR MA EI7 D70>CR-330 CD76 ......... ? I / _ IfL .. EID CI3 RM R;! EXAMPLE CR-330 3.0005% RNoPULSE D:~A ~V Ell CR-330 W --..052 L CI6 0117 EVEL LEFT RY ROTATE 0--++1-+-----' PULSE J -0A+IOVIAI -QB+lc1'i(13 -oC-15V o GND RH o MA COMP ENABLE UNLESS OTHERWISE INDICATED. ~~~~~W~~ SA~~EI/M\WFb 10 % DIOOE$ ARE 0-003 TRANSISTORS ARE 2NI754 NOTE' REAR PLUG IS FEMALE Triple FI ip - Flop RS -4206 R47 3,000 5% 3,~~0 QIB+-- I BUFFER 4-Bit Counter RS-4215 4-Bit Counter RS-4217 10-49 ~;> RI I;> R4 6!¥)OO< > < 5 1 R2 ,3,000 ..- 5% R5 150 S% I I 012 j ? ' r CII..1. 150 150 < RI6 > 3POO 06 cg.L 150 R25 > 68,000> R22 68,000 ;> ;> I ~~~~ f, "< 150 I > RIB 68,000 ;> ~.' ~" -!- C5 :> RI!S 68,000~ Rig I :> RI7 <:> I~~ R37 1500 R35 )~~ ~ ~L- v 6w,y ____________ ?~rk~(T UNLESS OTHERWISE INDICATED: FFA ~~~S N~'iDR ~~~~~E~~: ~ ~l~.c= 5% 6K , """ "S% C21 330 Wo T 025 P ONE OUT M ON AOO ZERO FFC OUT FFC ~500 I~ ~T:--'~ 026 R34 I,!SOO __ I U ONE OUT 'l,.ATHIS ~ IS NOT INSTALLED DURING MFG. IT IS USEDWHEN INHIBIT FEATURE IS NOT NEEDED AN) I,SOO *S%** 330 ONE SET AOO ZERO OUT ZERO FFB OUT ~It~ ARE 114W; 10% CAPACITORS ARE MMFO DIOOES ARE 0-664 ''''t 5% 3~l:~lL~~__+-__v_~_% 5% SET ZE'RO ONE OUT ~ A~{v R36 INHIBIT FFC H OE ADD ZERO FFO OUT FFD "Fe MFG fl~fs1~D~0A0ING OF FFC IS DESIRED. TRANSISTORS ARE DEC 2894-4 J ONE OUT FFD 4-Bit Counter RS -4215 A r-~-----------------;----.--------------------;----.--------------------t----~--------------~--~+IO~) ~t---...... LEAR C'23 2200 01 ~------~--4-------------.-------~--4-------------,-----~~--+-------------~-r--__o+IO(Bl > ;> R2 ~ P R I > ~68000 > R3 68,000 R4 68,000 02~r c RS • 68,000 R6 68,000 B > > R8 )68,000 R7 68,000 R9 C 68,000 RI9 3pOO 5% 68000 I ~~ 330 r--+--~rr----~----~--;-------+----+--~r---'---~------+---~--~~--'---~------+---~---1__--~--;--;~__~--oD G~ ~ 02 01 03 04 05 08 07 Q6 09 t--......HH ~ 3000 5% D~. ~CI- ~ RI4 3,000 5% RII 3,000 5% 150" j • 1' C4 150 j ~ ~ 5% I~' ~ j~014 ~ 017 j~ .~21 >R23 >I~ .1500 ~ 5% RIS 3,000 5% RI5 3poQ ~ I ~~018 012 ~ ~ I' ISO 019j~ ~ .>t:;, > ~ 5% R41 >I~ ~ ~w K L...----+-i-t+_R-2-9...........- -.....----+-i-+~--t--R-3-1...- -......t.;5::.;%=--ir-+t-1r-~-.R.-3_3--...---+..;:5:'::%:'-;-~I-+;---I-----t----+-.ii!:lI.--;--;-++"--1"o0c -I,5V FDA~------+--+-r~~~~,-----~~-t~ I OUTPUT 1500 5~ ~ ..A!~ o-22.j~ -'.!: 1"'669 CIO ~ C!~:!: 1500 3~ 33~. 5% UNLESS OTHERWISE INDICATED RESISTORS ARE 1/4 W,IO% CAPAC;TORS ARE MMFO OIOOES ARE 0-664 TRANSISTORS ARE DEC 2894-4 .A~ 500 5-41 . I 3C3120'..L- R32 I T COMPLEMENT o )H 0 OUT FFO :'.V'r-''''''' i~~ 155~ -! CIS• 330 :' """' 1500 5", IL C20 ~ U lOUT FFB 5% .!. 1" I" 1500 CL I IN FFD CI4 330 .. R37 • D!~'r ...__+-lsOO ___5_%1t-__~JVR,,34""'tD-0!''!..,~ ..--+-___t_--''''''JVV\t1 COMP~:IotENT B C21 3~ • : 0 ruT FFB N I OUT FFC COMPLEMEN.,. C 0 OUT I IN FFC FFC 4-Bit Counter RS -4217 COMPLEMENT A I~~ O~~ I ~~ FFA FFA 5% Quadruple FI ip-Flop RS-4218 8-Bit Buffer Register RS-4220 10-51 C3 2,200 I' CLEAR 0 ~ '022 ~r02" ~, 02~ 025 " A+IOV(Aj ? R4 68,000 > RI 100,000 R7 68,000 > > < CI 330 k6 1- :¢ 1!l0 R2 < 3,000 ,..........< r- ~ I R3 1,500 5% > I .~ . R8 3~ r~ D2 > RI6 68POO > S RI9 68,000 S> I~ ~ ~ 150 3,~~ .DI > RI~ 68,000 >::19 A~ f3~i~ I,~~O >~~ "----+-. 150 >,~ooo RII > 5% ..... '""ii71 ~~oe I .~ R6 n~ ~ ~ ~ 150 .l.C4 > H5 5% RIO 68,000 > > ·RI2_~ • iJ6 I,~~O~ .~ 150 . >, RI7 RI~o< 3,00 5% roe < 3,000 ~ ...... 09 RIS· < I,~ IfsJ 010 5% ~ A~ RI8 ~ 1,!500> 5% .~~ '"8+1OV!B) .." R22 ? 68,000 > ..lce 150 >I,~ r~7 ~ 'Di2 ...... 013 6~i ~ 5% 014 ~ ~ ~R24 I,~ ~~68 ii~r-M01FD 1!50 R~ C19 '018 ~IO .3,~ ~ 019 0-662 R26 3,000< r-~ 5% ~~ ~ R27~~ 021 n£S ~~ 020 0-662 >------< >R2 ?56 ~ clI)l' 330 P READ IN R29 I,~~ ' ~ > ONE o 0 330 CI1' OF 9.~ OL ZERO OUT ?R30 < 1,500 ~ 5% o > 1,500' 5%. ~ ~H ONE OUT N ZERO OUT ONE IN 0 C C J ZERO IN IN R~2 R31 ~500 c!i 330 5% ( K ZERO IN C ~!5 ~30 ( M ONE OUT C R3'I~ I,~ ( W ZERO OUT' B 6s ONE IN 8 >,R33 >~ 6u ZERO IN B ciy ~ 330 CZ ZERO OUT A T ONE OUT B R36 < 11~~ Cv ONE IN A ., ~,R35 ~~ OX ZERO IN A CIS 330 c>y ONE OUT A UNLESS OTHERWISE INDICATED: RESISTORS ARE 1/2W; 10% CAPACITORS ARE MMFD . TRANSISTORS ARE DEC 2894-4 OIOOES ARE 0-664 Quadruple Flip-Flop RS-4218 EXAMPLE CR-330 EXAMPLE F-150 r-------i ,--------, II £ 330 500 5 I 3000 I I I 5% II 5% ~ I I I 4 3 330 I I I I I I Z ('}-_-'V'V\.._-i CLEAR 1500 5% I I: 1500 5% 2 II I I L.. - I ~ - - - - - - I UNLESS OTHERWISE INDICATE .J ~~28'ci~sA~~~/~:f:tO% Rz I~O ~':---------4~--~....I ALL TRANSISTORS ARE DEC 2894-4 AU DIODE5 A~t;: 0-664 8-Bit Buffer Register RS -4220 D Gi'/D ~ Dl7 ' - 0-662 Q9 150 5% 1,!500 R37 ~ '"" 08 RlO 3,000 > R21 R2S 68,000 ' - - - - - - - - - - - - - - -....- - - ' C-15V 8- Bit BCD or Binary Counter RS-4225 10-53 ~ ys - i'c ''''D8 : c_ -- r---t---t----.-,-- r EI I i ~ ~>: ~ E2 )F-150 F-150 DI 4f--< ~,~, DSD7 I E3 F- ~~5~ -~ - ,c_ ~- ~~'U E4 ) F-150 D D E5 F- 0 ~-H-~~~ 12 ~+/H >I TI I ,~,~, E6 F-150 c D D-O JL 16 17 _ < E7 E8 <- F-150 ~5~ ~'1'" DOD EIO F-150 E9 F- ~-H-t-~ 22~~5~ > ,~~", 0 • D [l ~12 Ell F- S27~5~ F-15O > ~,,~, TI I EI3 EI4 F-I50 • D D D~' t-H_...... ~~2~~H > TI I I I °° "" C ~IOV(AJ -15 V I D GND '_H_'~H37 ) o.-:0~~f)~ ~>---~(f)~ ~>---~~~ '~>----1:~'- ._~~ ~>---~~~ ~.~ ~ I-!,jt'r: t II EI5 02 " D.;.6G6 ~ 1 , ......, 10 ~ '" "". ,. 0 ~ ~ ~ D4 < < 0-:: D!Ge :: :: " .E 17f'-.~, >668 I ;rF%F? ~I ~j'0~~~8 :i-~:668 HI1-1f--)~~ CR-330 > > - E 18 < 668 CR-330< 0J~ o~~ ,,'iii: '" 0>' IH>68 : ~'11IH~ E 19 >668 '" '" O~ .---:-=;0' 6681 ~ ~, '" ~ ~H€4 S Ji- E20 CR-33O:? CR-3~0 ~I~ 6S8 ~1~ :: S ? 11III "'" ... JI E21 l ~: ~S6B CR-330 ) HI1r-l~·r; E2~~~~ ~ >--- • _ _ • • • CR-330 ~ T U 11111, LO~~-- EX~MPLE C R - 33 0 I I -"~ ,.-- - & ~ _~ ___ 5 1500 I ~" " 3T30I;~2 1 I L , 3 If--=- :l_!5% 1 1500 1 5% I I L 3 68 ,g9;.O 1 EXAMPLE - ~9 150 ~ H-< E23 F'150 1 t-t-' ~ H~·031l ~f=F- T I ~I +059 =1- lI:J~-4if}~rlJ I I I 2 ____ I~ l~~'\ I ! I 3000 J I • I --I 1 I - -4 *150 I I I I I I 2 1-- I 1 I I I I OTHERWISE I ~DICATEO DEC 2894-4 DIODES ARE ::>-664 CAPACITORS ARE MMFD UNLESS TRAN~ISTORS ARE RESISTORS ARE 1/4W; 10 % ~ w I F~O- - J 8 - Bit BCD or Binary Counter RS -4225 Quadruple FI ip-Flop RS-4231 10-55 za-- CLEAR 8+IOVIB) I .JI _____ : £:6: EXAMPLE CR-330 r----------, I,;~O I I UNLESS OTHERWISE INDICATED ~~!I~~I~~R~R~R~4~~I!'~·~ : 330 : I ~--3 DIODES ARE D-664 I CERA CIRCUITS ARE CR-330 : I I I 330 1,500 5% I I ·~_1, ;!; ... ~ § I- 0 '0 ..J ~ w IW Vl ~ ~ § § '0 I- :::J 0 :0 Quadruple Flip-Flop RS-4231 GJ ~ I- ~ ..J W ~ ~ l- :::> 0 "- ~O :::J 0 W ..J W > W ..J I- "- iii Delay (One Shot) RS-4301 Integrating Single Shot RS-4303 10-57 vo------------i------~----------~----------------~------r_------------+_--~--~--~~--~~----~~_p--o zo-------------~_, x0-----------------+ C3 220 R3 D2 1,500 RII 3,900 ~ UNLESS OTHERWISE INOICATED RESISlORS ARE 112W; 10% CAMCITORS ARE MMFO DIOOiS ARE 0-664 5% L---------------~------------------------~------~----------4---------------~--~~~----_cc __ v Delay (One Shot) RS -4301 "A+IO\ICAl > R6 >68,000 >.'lh> > Ri • 68,000 ~ .(> > RI7 ~K>~<~K>,ooo <':l5o :33- < ~ R24 680 R21 < 680 < 01 ~~rl DEC 2894-1 C2 330 K ~lAA 'R2 , ~ ~ 3,000 11% D2 ,,.. O~ D~ 0-664 .. w~~ I T - ;----' ,~ > <~~ ,019 02 03 DEC 2894-1 D!S , 0-664 ~' ~ ~G >,. ~ _T'&, ~ < 1M • 82 >Rli >'000 '~ ~'8 ,,~ ~:lJ 0-.2<'3 .... C7 220 010 ~~: 5% Al3 09 08 '" "'.-, ~. ~ 680 ~ QII ~ >R2!) ~.CII-G 5% 3 3 0 T j l,poe 07 ·~0~OO3 4~ ~& .. ~OGN) OS DEC 5% _B+IO\IUI) 002 ~r-68 _ CI3 ~ < 5% ::~CI4 3.9 ., [)I3 ~ 012 ., 011 lED fiTOl ·~3 >Rl9 RIIS ~ rIM '~~D ~?ck ~ooo Dill ",010 ,,09 RIO J.O,o~O ~~ Mo UNLESS OTHERWISE INDICATED : RESISTORS ARE 1/4 W; 10 % CAPACITORS ARE MIlFO DIODES ARE 0-662 CW~ > ~ 5% C6. BOURNS C T~33 c) z ) b t!3 ~F "'-:~~9 + IFO () H ~ =t~ + 6 R22 - .>'r.:' >~ IFO ) II Integrating Single Shot RS -4303 ( W ONE OUT ..-->~ c U ZERO OUT c R28 390 1/2W _C-I5V Variable Clock RS-4401 Crystal Clock RS-4407 10-59 r-'--'-------------;:;;-,---,-----,-------r---,.---------------.. . . -o I R4 2QOOO "%~O ~' r C9 " R7 22 R9 10 r.L~ ~M RI 470 D.l,Z GNO • C4 ( - 3.9MFD C8 0 R MFO C5 t----+--I ~ p (6 ~N C7 ( .0027MFO 0 U Q2 12J T2 R3 820 T2021 T2021 T2019 R8 220 R6 R() 100 150 5'lb 5°", U~ESS O:TH:E:RW:,:~~,:N:O,:CA~T:E:O---~------------!-----;~~~--~L-----------_J~_ __v\lV'--J~_oC-15V RESISTORS CAPACI TORS ARE 1/2 W; ARE MMFD 10% Variable Clock RS -4401 ,----~--------------p----------{)A+IOVIA) '--t---T----------+--------o__c;BtIOVIBJ RC 2.200 ce .01 MFO 5% .01 MFO 1 T ! r-------~---~~----~-~r_----~------_-~---~~-._---.......~~......._oOGND RI 4,700 R23 220 5% 06 RI3 1,000 C4 220 RII 390 06 o-OCI D-OOI RI5 560 FOR SEE R20 220 '," 'IIC: R22 220 UNLESS OTHERWISE INDICATED' ~~~T~;~s A~EE "~:F60'" T2 04 5~ + C9 .L .01 MFO ~ I L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~-----~------~~C_15V VALUES lI, C I, C2 AND CR. I, DRAWING CHART A-00517- 2 Crystal Clock RS -4407 Pu Ise Generator RS-4410 10-61 - --------1~---------------~---------~=====: ---L-----,----------------------------- A +IOY(AJ vB +IOY(8J Mf'\..------.---r--~~~-=--f==~---- 3,0'00 ~ J.:: ~ R50 220 5% II2W II Mf ..... IIIFD -3 4 l'Cf5 .01 CI3 r ·01 ~_2018 ~C12 <,R32 (,5,600 06 0-003 0-003 05 0-003 ... f"'II )R42 82 ') 2,200 R49 220 !I'll. II2W C-l5V OL LEVEL OUT PULSE IN RI2 $~6~F R9 221 1% MF RI6 39,200 C4 39 MFD 0II =lH- 1% R27 6,600 R37 68,000 MF R20 1,200 1% MF 03 RI5 4,640 1% MF C3 0022 J 1% hEr) <,R33 1,500 MF 05 MFO 5% 09 ~ .0022 ,dJ ~)" MFD .JL 1\ D4 D7 0-0030-003 -C9 'Tj',ooc t-----{CQII TRANSISTORS ARE DEC2894-~ 4,640 I'l1o MF L--, RII 4,640 R25 390 112W I'll. MF Ow PRE-AMP <~;'~OO R31 15,600 R49 220 5% II2 W 220 15% I-'2W Ou LEVEL OUT Duo I Sense Ampl ifier RS -4554 ~: J R47 • Oz OUTPUT ~ MFO UNLESS OTHERWISE INDICATE!) )Re Q15 DEC2994-3 DEC2894-3 If 1\ J DI [1-682 R23 180 RI9 4,640 C7 ~~~~~W6WSA:~l~~~g% 2 R39 OH (01 ~~~O TD2 .0-003 112W ~~O 016 DEC2894-3 OEC2894-3 PRE-AMP OUTPUT rR6 4,640 5% 010 .JL R4 270 .012 +0-662 ~ R24 ·VVV FlI7 o GN J MFO 5R2 ~270 R40 68,000 I'll. MF 02 SIGNAL INPUT ---QB+IOV(BI I'll.. MF 10~~WL C5 .0022 • R14 PU~~E IN Pu Ise Ampl ifier RS-4603 Pu Ise Ampl ifier RS-4604 10-65 A+IO'VIAl S+ICMBJ RI3 RI '8~0 ?3lf OO o GND Cl3 ~ ~~~ rn~~ iio X R2 3,000 iao J~1 R U R26 RIC I .01 R~ RII H 000 ,000 f l~o .001 111'0 V Y I 1 C4 .01 liFO S liFO I cal .01 MFD RIB R6 120 120 01 UN..ESS OTHERWISE INDICATED; RESISTORS ARE IICWi CAPACllORS ARE MMFD ,% ~............~....................................- - - -....................~............~................................................- -........~............~....................~~c-IBY Pulse Amplifier RS -4603 : 'lJ" ~ "~'130rlr+~ ~~OI2,4700 RI9 06 CIO 330 47oo ~33O +t9-1.({iH.'2N2714 . ...- - - - -.... ' t9~~14 +IN RI6 1,500 ~~< .. t92~1:714 -IN CI5 330 R 33 ~ 4700 Yo-J r-..--t-----+--+t +IN c> R30 1,500 5"10 5% 5%'< ~ l ' OIB 014 CIG 330 z04r-~------~~ _~ f--.------il~ .. ~--~""""""""""-------+-+-----------+----~~--------------~~r-----------~----~-----------+----~OA+CW~J ~--------------t-t-----------~----~~---------------r-r-----------+t----+-'----------+----O~,B+OV~ >.~ ~'%oo~ > 1,500 "'3 RI7 >68,000 >~ _ 05 ~"oo' >/27 66,000 6~3&o< >,R31 >'~O r-- 08 ' < R41 ~ 68,000 '''r( ~ ~'--5%""-28-:~,;;.;;;.C~--t+>~-n"R-;&O--+-+()--""'2-~-'k--""'--+-~-:E~--~-"""-2-e"'::O~"'C~--~ 11,000 CB 150 TI ~7 ~_ PO t-< ~ill~ ~"'~ '.>~ ~ RI2 470 ~ 04A~ RI >000 i~ 5% .'r'" RI5 RI4 > ~ 112 w~ 1 < 3~ u() 2894 ,..... ru R21 n< R22, ~ ,01 3,000,> 1,500; MFD 5'l1. 5'l1. ' ipOO T2 DEC WO YCIl A~09 r:nr' R2~'>'i i6r 470< 010 ~ _ ' ~~ 112W CI4 150 ~,t-~.... R3~ 3,000 5'l1. 013~. 3000 ~ &NO ..... R36, ~ hllCI7 ~'lI. 1',000 I,~~ <' '022 0-662 ~ .01 MFD CI9 • 021 M~O 0-662 Uc r::r:lr &ox ill R29 R28 ' .015 'ozo 0-662 R40< ,; 470 > 016 R42 120 > IIi!'> R4 RG RII RI8 R20 R25 R32 < R34 < R39 1,500 ~I,~OO 180 ,,1,500 ,,1,500 160 1,500 < 1,500 < 180 ~~5~%~~'~5"10~~__~~__~~V~2~W~,5~~~.__________~/~5% __-+'_5_% ______-+_____~~I~f2~W~,~5~~.__________~~~%~--+~5~"Io~____~_____~~1/_2_W~,_5% ____--OC-.5V UNLESS OTHERWISE IN ICATED RESISTORS ARE 1/4W, 10% CAPACITORS ARE MMFD DIODES ARE 0- 664 Pulse Amplifier RS -4604 Pulse Amplifier RS-4605 Pu Ise Ampl ifier RS-4606 10-67 r-~------------------------------~--------------------------~~--------------------OA~~W o .-----?_~----_T------~------t_------~------?_----~~--_t------~~----~------_tU~D III 0----0 - - 0 -_ _----iI---+ No---0 - -D--II*---; T 0--0' R28 10 '" UO--O - vo--<::f'" w 0----0- - -0--"--+ x 0-<1 / -{)---+ 0----0 - y zo- RI 1500 5% 5% R3 ~ 'k(5""~~'~ ....... > 5% IPC~O / R? 155~> 471 R9 1500 5% 2NI309 >3~OO ;[ aDZ > > ,,·lll(: ~~i)3 , ~ LEVEL ,'.,.N RI4 100 ~ ! < I '~I ~ 1 Ko-jJ-. C5 330 ~ J ~~6 DIM 06 RI3 1500 5% ~ RIS 1500 5% ~B"!' -" 150 ~ ~I~ ---.W .. "- ~ R22 68,000 Rli 58,000 > RI? ~. DII 1205~2W~ ,I CIO '~!;' J 155~ .ti~DI4 JI 1.111 3 +R 470 ~ > R29 1205,~2W~ R2B 180 1/2 W 5°;' :'! CI2 330 R32 100 01 MFD ~ H 1500 5% C13! I50C 5% ~ ~C14 "'DI7 I or LEVEL IN ...- + I ~,j ~ 024 R35 4700 :'! '{ o-jt-' RSO 100 Z~ LEVEL IN DIR '---'~ Pu Ise Ampl ifier RS -4606 v R~I 01 !IIFD 1500 5°.. > k6~" TIOOO J "~D21 > R49 1500 5% ~ D~ ..... 026 .01 MFD ~ ,0·662 C22 .01 MFD ,,!~g~ R43 1500 5"(. GNO D28 ~ CIB CI7 T3 T2024 ~D23 I, jll[~ R!54 470 "!~g~ I.. ~ R 47 I - - - 120 112W 5% R46 IBO Inw 5% R52 1,'iOO 5% ~:o CI9 330 07 2N2714 R42 >3000 5% R44 1500 5% > R4S 3000 5% ~ +IOII(AI 1011(8) ~ 2NI309 r---z R4!5 1500 5% ,j~D20 .JL Ct3 T "': R36 R34 1,500 5% JI5 ,f 30?0. T2 ....... C2: r-r;ll(' I'", I "~DI2 R27 1500 5'1', R41 R3S 68,DOC (l10 r;; C II a R40 68,000 j6a.ooo ~ 1'000", .m~ R25 R39 5"1. 09 ~ >,R24 CZ6 R30 3COD 5% so-jt-' ~ D9 ....... 2NI309 R26 1500 5% >4700 03 2N2714 'M~" 58,000 0& ~ 5';' RII RIO IBO II2W 5% 1500 47-1 RIS 470 >1500 5% > C6 (l5 R2~ TI T2024 > RB RI2 3,000 5% n ~ R4 68,000 ~s8:OOC ~ 0-;; I 68POO: C25 ~ 1 15DO 5% C2 150 ~ -IN > ~ ,... CI5 330 uo--j D~ C24 .01 MFD 01 MFD "C ~ ~ W .l. "Te23 ' -1!5V R53 4700 2N2714 TI~ ,.~ 027 UNLESS OTHERWISE INDICATED: RESISTORS ARE 1/4 W; 10 % ,CAPACITORS ARE M MFD TRA"ISISToRS ARE DEC 2894-4 DIODES ARE D-664 Leve I Ampl ifier RS-4678 10-69 r----------------------.----------------------~----------------------._----------------------._-------------------QA+IOV(A) r-------------~~-----.--------------_+------~--------------~------~--------------4_------o_----------_oB+IOVIBJ 1'<20 r--+--~----------_t---.--+_--_t----------1_--~--r_--+_----------+_--.__1----+_----------~--o__+--~~--~~K)D GND R4 4700 ~-------+4_------~ R3 3,000 5% __~--------4_+_------+_--~--------+_r_----~~--~--------~~----~~~~~~~~E-lOY RI7 R5 221 I"" MF 221 1% MF UNLESS OT:iERWISE INDICATED; RESISTORS ARE 1/4 W: 10% TRANSISTORS MARKED WITH IRD) ARE SPECIALLY TESTED CAPACITORS ARE r.lMFD Level Amplifier RS -4678 R23 221 1% MF R29 221 1% MF Teletype Incoming Line Unit RS-4706 10-71 I I -b-- BITI R43 ~oo 10_~ _____ BIT I _ BIT2 RGD ~ BIT 2 r BIT3 R71 q.t ___ ____ : _~~~_____~ I~",,- ____%> _ • 011 :> R44 ~ R40 +1014 01\ TJ I R61 1 021 R56 r--< *. . 022 R57 017 " " 019 ~Ill ~. '68R8B 000 115% 010 I !9~t.u_j ~92< 68,OOOC 09 II] +;----- t------ 0 BIT5 RID7 100 0 LO_"k ___ ~ IV BIT5 RI06 BIT6 RI24 100 I 1;----- RIIO 0 BIT7 RI42 100 I lS>Jb ___ ~ 0 I.Q~---~ IV BIT6 RI23 ~~0'06 Q7;6Ef'~f 10%( BIT7 +;----I ~'5' RI27 ~8~0'Q6 05161j'~ ~ BIT8 RI52 100 $ >R105 D34 R9o ___ RI04 ~035 1T11 0291AIli RB6 02B* ... 030 RB4 R109> i~RI0804°1'11 *1+ 039 RIZ2 RI26 RI21 RI25 , I 1~~~~5( ;I1+ 48 A RI2?" 'V 013 RI46 C'R64 DB t 07 C6 2200 II .. ~ II , I ~ '-~nn I " II ~12 b W O!LEAR 3 ,~II~R5 ~q 10,000 MFO, 00 I L..-.J\N''' ~% FLA~ --------+-------- I" IN LAST UNII I -. INC DATA INV, RIOI< 1809.$ R51 R2 1,500 RI5 3,000 RIB FLAG RII6 R53 > CI9 2.206 .010 jL UNLESS OTHERWISE INDICATED: RESISTORS ARE 3,000 OHMS RESISTORS ARE 1/4 W RESISTORS ARE 5% CAPACITORS ARE MMFD DIODES ARE 0-664 S CLOCK D GND -15V RI37 R21 0" 0 0571 A R143> 056 I~B8 I1 I A+IOV(A) o fVV R29 • 18f 02 QI.c:18~ 047 043 RI03 R67 R39 ~ ttl 0 IQ~_n+ 81TS • R91 RB7 R73 ~R72 R6B 023 BIT4 RB9 100 81T4 I R74 68POO 10% ,/ II I II -<>M 1,= iN'SN~~~~~~~L:N-R~~:E~~ORP "*1762 REF 85-4706 Teletype Incoming Line Unit RS -4706 ,~ D53 Teletype Transmitter RS-4707 10-73 R34 68,000 01 3,000 ~-+~~~-~~-~~~~~~~-r~~=~·i-t~~~ij~~~~Ii~~~;ttt~~~t-~~~;t~~~~Ir~~~~jt~Jt~~~~~~ti~~~~=t~~~~ttr-t-~C-15V D .. R30 D-668 '-~r1~----~~~~~~~~--~~~-----r++------~~-----++1------~~----~~+-----~~L-----+++------4~~----~~------~~----~r+----~ 043 R98 E~ ENABLE C32 330 l ' R28 R22 68,000 68,000 RIB 68,000 RI3 2 C2 68,000 26BO ~ R6 6B,000 2R9 M POWER 26B,000 CLEAR R4 .3. 00 READ I N PULSE INVERTER READ IN 04 D48 0-662 RI59 68,000 ~II 3,000 D6B P SI ~~ >RI57 1,500 R8 750 1/2 ill SOLENOID DRIVER I I BUFFER .,,_. 11<12" 3"000 >VI:' • DI ~\:P~~ INVt~TER OUT SI FLAG RI48 68,000 RI53 68,000 <. RI54 68,000 .051' t: R106~ 1,500 < (R102 D50 ?lo,OOO < - 4 -~- .... 051 ~ V OUTPUT o W OUTPUT 1_~~7 RIIQ, ·0'668 L..I....'>.80 "!'R'J...°A. H3~ "056 RII1 1,500 1.0·· UNLESS OTHERWISE INOICATEO~ 1,000 1,500 a 3,000 OHM RESISTORS ARE 1/4W; 5% ALL OTHER RESISTORS ARE 1/4 W; 10% DIODES ARE 0-664 TRANSISTORS ARE DEC 2~4- 4 CAPACITORS ARE MMF,D II-IS TRANS-ELECTRON ICS CflRp#1762 REF 85 4707 D54 062'" RI21 :..T. +-I-C38 Rloe 3,000 0-668 ~:J& ~OO v3,OOO C40 2,200 i L fl~'\...H C42 3.000i:!::uoo C41 R13~ 3,000 CLOCK "g~i62 2fOO ( U ACTIVE R WAIT 1 T CLOC~ D73 D-003 ( S CLEAR FLAG Teletype Transmitter RS -4707 22-Pin Plug Adapter with Bus Driver RS-4801 22- Pin Plug Adapter with Bus Driver RS-4802 10-75 +IOVIA)A -15V C R2 68,oeO R3 1,500 R4 22,000 Fl6 68,000 6NO R8 22,000 >~:oe RIO 68,000 5~ 5~ l: to" O~t tO~ ~,)1 (E) "-~ .O!~F ~ CI TI50 RI (3,000 5% L-- 2NI754 2NI3 C2 .01 MFD~, A~DI 2NI309 54 C3 AS 3,000 5% 02' ~ '--=------ FlI2 22,000 05 2NI754 C6 2NI309 5~ 0 2NI754 RII 1,500 ~~D3 . C5 TI50 04 ~ L R9 3,000 5% ~~;Ol MFD, «) \b < AI5 RI3 47 < RI7 47 ( RI9 47 47 R21 47 _ ~D6 RI4 47 RI6 47 Rle 47 ~70 EO-- . < R22 47 A* F'"' H J'"' -- K L'"' M N - B* C* E* H* J* K* L* M* N" H I ! j H~ vo~-------------------------------------------------------------------------------------------------------oV* oW'> wb x0 0 x* 0 Y* 0 i! 0 y OlIO UNLESS OTHERWISE INDICATED: RESISTORS ARE 114 W; 10% CAPACITORS ARE MMFD DIODES ARE 0-662 *'NDICATES BACK PANEL PLUG 22 PIN AMPHENOL #143-022-04 22 - Pin Plug Adapter with Bus Driver RS -4801 + 10v1A) Ar\. -ISV C - < R2 68,000 IGNol 0 lCI L «l RI 3,000 5% R3 I,SOO So", 01 2N 1754 ~~ .01 MFD ~ C R5 R4 22,000 330 2W R6 330 2W 2R «l~~ \~ ~k 02 ~) >RB )1,500 > 5% R9 22,000 2NI7S4 fS3 0 ~ >R7 3,000 5% ~~ 01 02 IiIFD~' ~ 2NI30 03 RIO 47 RI4 47 ( RI2 47 < Flil 47 RI3 ( 47 RIG 47 RIS ( 47 >RIB 47 RI7 47 R20 47 RI9 47 >Fl22 47 R21 47 r.. B* ~ C" Fe-- -:- J'"' K ,;:; L* 0 iii ..... M* N N* pr> R S -'"' P* 1""0 Fl* ,.., U 1\ v J"\ W ;J* - E* FlO J* - K* H ..... s" u* v* ...r. W* .r. x )(* y* .r-. i!* y'"' '" UNLESS OTHERWISE INDICATED: RESISTORS ARE 1/4 WI 10'1'. CAPACITORS ARE MMFO DIODES ARE 0-662 *INDICATES BACK PANEL PLUG 22 PIN AMPHENOL-143-022-04 22 - Pin PI ug Adapter with Bus Driver RS -4802 18- Lamp Bracket RS-4903 9-Lamp Bracket RS-4904 10-77 A M ~----------+-----------~----------~----------~----------~~----------~----------+-----------+-----~---O-I~V UNLESS OTHERW";E INDICATED: TRANSISTORS ARE 4JXIC741 DIODES ARE 0-662 INDICATOR LIGHTS ARE DRAKE"I'II-504, DIALCO .#39-28-375 ELDEMA CF ZWT-1762 la-Lamp Bracket RS-4903 GNDNo----1r-----------~ -15V Mo---~------------'_----------~----------~~----------~----------~-----------4~----------~----------~ UNLESS OTHERWISE INDICATED- TRANSISTORS ARE 4JXIC741 INDICATOR LIGHTS AR£ ONE OF THE FOLLOWING; DRAKE NO. 11-504 DlALCO NO. U-28-375 ELOEIIA NO. CF2-WT-1782 9 - Lamp Bracket RS -4904 Inverter RS-6102 10-79 r-------~~-------4~~--~~+-.-----~~-.----~R~3~5+-.-----~~~----~~~~----~~.----------.------~~_oA +IOV ~J RI51OO,OOO R6tOO!1Xf 68,000 R27 68,000 68,000 Cl3 CI4 .01 .01 MFD MFD D r---t-r---~--~;---~~-i-i----~--~t----.---i-+--~~~r-r---~--~~--~~-4-+----._----.---._--~--~~eoGND CI2 01 MFD CI DID DI7 D-662 D-662 CII .01 MFD RI R4 1,500 1,500 5% 5% R7 1,500 5. RI3 1,500 5% L -________~--------~~--------~--------~~--------*_--------~---- R22 R2~ 1,500 1,500 5% 5% R2B R29 560 V2W 560 112W ____~~--------~--------~~--____~--~~--~--Q-15V C UNLESS OTHERWISE INDiCATED RESISTORS ARE 1/4 W, 10% CAPACITORS ARE MMFD TRAHSISTORS ARE DEC 2894-1 DIODES ARE 0-664 Inverter RS -6102 p o F I I c-r 8' :>0-'11 l I B _ I_ I I I i I -t1~ I I I i I I I I I I I I I t- I I I ~I CONTIN"~ UI:. I l I I I I l i +---I I -L I I I I I I j I I I --f-- + I I ~ I~ -1---';;-'-e 1,0 b BeK "Q~,T_r L2jP j ~~§J JrY.P 1 ~ 1- _ ~~r ------1 - JMP -1-- I I ~J_ + JMS J; R I _ RQST -r-B I 1 I 1 I rr;::--~ L9--=----~QS C':~Pl BRK I I Flow DOlagram FD - D-5-0-2 10-81 START DEPOSIT EXAMINE INDICATO IH02 IC97 r T W ") R 5 I S,p. 3.3K SP3 SPO I 4410 ,'E06 'OK T : KEY _'::"S-OC::l MAN 14712 Z I I C~_J i 5..L II 0- L. -=-l 1 : 4129 'I L_----L-----L-----------~-----------------~ ! -: -L--J 1 -: I 1 4604 I (08 .~ PWR, CLR. 1--:------- -, - 35V EXT 33K 1 ,IE05 I I I 1 KEY LOA D ADORE SS 1 I 1- I sw. SINGLE STEP Y I ~ I X I y R 4~ CaNT 1./1 " I I L > ~ - - - I I - - -l -- - _ _ _ _ _ _ _ ---1 - - - - - - - - I I I I KEY EX+DP I I ...-----'........... RUN STOP R I_ _ _ _ _ _ _ _-+-_ _ _OCJ .--_~ - - - - -..... KEy STOP ~--------------~~~~ C ~-...-.SW. SINGLE STEP I K KEY EX+DP I :P SET 1 _____ J p M 1 I t ~ SW. SINGLE -+-______-.sw Keys, Switches, Run, I/O Halt, Sp·s, Power Clear BS-D-5-0-5 SINGLE INSTRUCTION INS TRUCTION I L IH06 _...1 'J 1 KEY ST+EX+OP - - - - - _ _ _ _ _ -1 14114-R ~ 1 F E 1 IO-HLT' ~----~~----~~--~~OKEYST+EX+DP -I - 5~ I ---< KEY -I~II I CO 7 3 I -t - W/1 PiC}- I I IE04 IE03 .-- 2~ EXAMINE I 1004 KEY STOP X- V ,~, 004 7::- ISP-C~ Z -15V RUN STOP W IOT---l- "P'L.. r-J /0 N 10K 1 - IO-HLT I PWR iv1 I (LR ---;:: r I ~ T I ! 4102-R 14112-R J W .-+------.............. KEY DEPOSIT ~ RESTART 2 ' 1012 L _______ ~ -,-- - K;::Y MAN I V~_ _ _ _""'KEY START KEY DEPOSIT -1 MB1'o---L...:..:M"---Dl--I I ,-- KEY EXAMINE ..r-h ~-- sw's ' CONTINUE x.-+-----_..... KEy M I i------, IU KEY KEY ST+EX+-OP --l -..I----.~~_L_O_A_O_A_D_D_R_E_S_S_ _ _ _ _-+-....:....tc;)-' KEY START L --- - :"l I I I t RESTART 1 t-' I Z 1 I J K PwR I ,4114 R 1004 I 3 T 1 4116 ~ CLR I L ______ J KEY CONTINUE SP- I I z~-----~KEY IE I 1 IH04 ~R IO-HLT I --,~......o:~ sp-o ~~-.P""R CLR KEYS/ ----1----- ----T-----~ p 1 ------ NI p ~ ~M. °lO-HLT ! '! RUN s - ip N TP- 5 I XI w TP6 14401 o ....--.-6- 1 ------ Tt_·~~ IIEO~ I - -- - - - 14215 1 EXT I 3.3K S R r-- - ------, ,- - - - -:"5v- ,- - - - 14 '02-R IE04 1077 10-83 INDICATOR lHOl 1C'37 L u v w M N p M N p ALL RESISTORS ARE 3.3K 1D77 1151 R!~--O AND (0) 1021 5 "--_-0 TAD (I) r---~----------+---------~--------~~--~E ~--------~---------4----------+-----~F r---~----------4---------_+----~H ~--------~--------~----~J TI-l- - 0 15Z (2) UI-I---~O DCA \.3) ,- - ----.JMS v ~JMS (4) W~--OJMP (5) r----4----------+-----~K ~--------+------L Z <>CPR (7) 'N14i27 - - -- 11024 I i I TP3 J _L _ _ _ P --:rr - 4127 11023 I z T I I SP2~R~~____U~~______~X~E I ", 1 s v , KEY KEY - ~! - - - Q£>- Y I KEY I S2+EX+DPI I I 4102-R 1 L ____ ~I~ ~ - ------I Instruction Register, IOPls BS-D-5-0-6 10-85 Ir- I I --- -r- -- 4115R 1010 I II IF TPI_S~~~.~r-,------~~------ ~ I I NT ACK T ~ - - -- - - ICII C~~y R ~._ 4113 ICIO ICI9 __ L w -IU~- - r--I I I 4 II COUNT MA I 1 ,- _ _ 14113 - - - _______ - ~IIJ:IEj::0199 __ _.. - - . I _ 411~ j W - Ie!? : : I _____ f I ~D~ Et'DCA ~ IDII I I MB ~lPA3~M F 14127k .IC05 R I J"'IP~: 1009 ICIO : 4606 -I ICl4 I I E.J..-l , II 4~ I1 I ___ ;- _J-w LK 4115R 1014 I TP-I I JMS I F --=E.j('h...-r.J..., I D p 1 i . ~ f-- ~-r--.-- I H' ..J i i jMAg 1M 1 -- I 1 I~---R---'r~ I =-410i _. II = t:}--'--'S T Pl 'T_~..--!.~5 I _ .l r: ~~.~ I 41)GR I -.L =- Wl 10,9; I L L~CE r:>P3 I1 ...L F KEY ST l T T 6: -;--{)I--_-<"'I...l!; 0 I 0 I .,. 6~ IMA~ I~Ag IMA~ I~·t. ~ -I -L A2 IMA 3 -,-- ___ I I IMA? 4113R 4113 . D02 IIE09 j_ I 1 MB I L _I 7 I __ .J -.l. v 1 I I -1 'WJ9 R wiI I 4114R 1011 I J - I -:;:- IR~~l I 1_ _ _ _ _ I P~: ' I r---I 4106~ --L. rlNtAC~ "I - Ir~'-I---'-- r ~'< 1 I r--- - 4113 I II ITPIUr'1 J.:AS~I: -= I _..:..._:"-L I I I - -II rI 4 4-; - - - I - --l ~MA LOADK ADDRESS :. rr:DcA I MA~M8~ I I I KE Y : -<>Ei.·DCA I I ---:..L---- : I S __u_..-r-'-, _--,-Y", L I pJ-=L I ~~ I I -41:~ ":'. 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DATA I I U 108 cc~v~.:;. !-..C CARRY INITIATE- ACCAkRY~S MB6~ I E AC CARRY ENABLE - A I 1001 I - HALF ADD --- ~IGHTRO~TE--- RIGHT ROTATE ACL~ACRRY CLEAR AC IA LEFT 1" ACg I : MB:~ AC~ I T : L ~ W : SA3 I I DATA ACCARRY~SS BIT3 ~ BIT~ W : SA41 I 'r MBk~ AC~ MB~~ I : 1" ACg MB~~ I I 1" ACg I I, IB9P E F I H I K ~ ARE3f·3~K=====q=========='==============~========~'==============~========='==============~~========'==============Et==~ L E~F V Iv Z Z I ~Io ACO' : Z ~F, E8F I 0 ~LA~~~~ I AC,,~ Iu AE;2' : E~F , JO AC3'~ I ED.F : 0 AC.' ~LA~T~~~t~R~Y~I----~~~~~~2~~~B719tn~~R~Y~I-----~~~~~~~Z~A~~~f~f~~~~~I'--------~~~~p~ZAnirl~~nR~R~Y~Q~R~ ~~~--~~--------_+>$_+--~~--_+_----------~$r+_~~L---~--------~~~--~~~_T----------_+~_+--~~--~----------~~·+_~~~~pHALFADD I I M!' Y I M!: Y I M!' Y I M!' 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F_+-.:: 3.3K U IB98 BIT~ : I I MB~£:. OPI H A-D CONV KI o TiT COMPARATOR --- ~ I MBg : MB9 II MB',~ ~ : IT I ,~ ~ . MBO A-DST.4kT I MB,!, KEY 5T MB : MB2 MB: I: MB3'~ ~- MB1 I: MB4'--"""-----~ I I ~ NOTE: ALL PACKAGES A-RE 42010 UNLESS OTHEPWISE INDICATED. Link, AC, MS, MA (Sheet 1) SS-E-5-0-9 10-91 MB~ rr__________ 1'---_______ IM_C-:I'---~[*-----------I-M-l+--_ _~~---_ _ _ _ _IM_2___,_1_ _ _ _rr---:L-_ _~_ _ _ _ IM_3+'-----+--- 1 _ _ _ _ _ _ _ _ _. _ _ i _ _ _ _ _ _ _ _ _ _ _ _1- ___ I ~t_~~~IW~--------~~----~~~_r----------~~----~~~+I----------~~----~~~~I----------~3~----~>$-T,-----------~~----~~~~A-DCONV I I I. X I SPI W O 1 ___________ 1 _____________~ _________ _ II I_M..,41¢ COMPARATOR IND THlS P!-UG IS LOCATED ON THE REAR - ; \ OF THE MODULE 1959 IBI4 ~ r- __ ~B~'~~~_~L~~~~~I~~~~~~~~M~=-~~~T~~-~~~=-=~~N~-~~~~~~~~~~_=~~p~~_=_=~I~~~~-=~~~~R~=-~=-~I~-=~-=~~~~S~~~~~~~~~~~~=T~--J- l .~p I .~p I ~P I .~p I If-~P I· .~p I ~P i I r l_ _ _ _ _ _ _ _ I - I MB~ MB~ IJ SR-MA L I ~K-+~K~~~IK~------~,--~~~~~~~_+----~I--------+,--~~~~~~r-~~--~'--------+----o~~$~~r---r---~I--------_tr--~~~~---t~_+----41r-------ir--~~-Q~~ri~--t_--~------~~---~~~~~+r--+____ r " M IC61 <: L ALL qESISTORS ARE3.3K,~__-,+_------__--------------~--------__-------------,~--__ -------------------'rl------------------------ni-----------------------cr--- F D jD I I I I I ...L-+....,.L+--LCL~-------<>f10)'MAs"II'I---------+---+-------<~oMA6'1,"r-------'Ic----+------<>r.o'l"MA7'1'''r--------'------II------~oM'A8<-:",.....-------t---+-------<~oMA9"""r--------+----+-----<,r,O'l'MA,o~I'I---------,-----+-----<~>f10)"M~A"I I 1 TI I 1 TI I 1 TI I 1 T: 1 TI I 1 T I H IH Y I f I f I f I f I f ! r.lCOUNT MA DISA BLE MA CLEAR MA S- IICARRY ENABLE MA MB-d-- 5 IHOI<~---rF~--------------·--------~H~-----------------------J~-----------------------cKr------------------------'M~----------------------·--rrN~----------------------~P--~ I I I MB~ MB~ : MB9 MB~ I I I MB~ MB~ MB~ MB~ f ' : MB~MB,~ ~ ~r--~~~--r- - IE DATA ADDRESS rMA I U U I U I I U IBI2 IBI3 I I I I I AC-rMB M M R R 1M - - COMPo AC CARRY INITIATE I I CARRY ENABLE I A I I I I E~-s:",F IV x I Ix MB~~ AC~ 1 AC~ EF E F I I I ~F I EF E I FIE F E I FIE F E : I F EF E F r MY~ y .I : I -h"r-" MB6 I, I Y : -h" ~ MB7 +-~---r"'Y:" I I : I r I MB~ I I, I .Y, r ..... MB,o : r"- 1, y~ I I IU I AC~ _H_+-+--_1-~ -* : : I chr-" MB9 r-......,.......,r=,Y I I I I I I I I I AC~ _H_+-+--_«$1 : '*: I MB~ W I :T I I MB~ -KiT MB~: IMSI II _____________ I L I I MBb: lM 6J I AC~ _H_+-+--_«$1 : .* MB~--Kl---~ AC~ _H_+-+--_«$1 :, AC,'O _H_+-+____ ~ :, 1** I MB~ MB~I : I lM7' I MB~ : I I MBs-l::l--~ , MB~: IME _ ...l _ _ _ _ _ _ _ _. _____ ,_______________ NOTE' ALL PACKAGES ARE 4206 UNLESS OTHERWISE INDICATED. Link, AC, MS, MA (Sheet 2) BS-E-5-0-9 10-93 ' M COWl'. I Y, Y I MB" -4---!~---A-C-~~~J~-+~-~-+~~-~~~.-~+--r-r~j----A-C-~~~J::::::::~~~~.-r-t-t~!----A-C-~~J:~:~~~~~~~K.-~-~--i--r-~:~---A-C~--~J::::::::~:_~:.--r-t-t~:----A-C-~~Jr~~r+~~~r-~.-t-i-i-i:----A-C-k~~J~~::::::~:~~_~--+-~:-----A-C-io~J:~::::~~~.r~~. I COMPARATOR AC~ ~AC51 : ~ I JOAG71 ~ I ~ I~' ~~ ~I02--l: ~Z+--~IZ~------~~~~~T-"~,A7~7f~fT~~RIRmY~----------~~l:~~~AU~~I~~T~~GR,~R~Y~,--------~~~1:~T~~Z'A~~~lt~A~f~RNY-~I--------~~l:~~~,AVC~Bf~t~~~RNY~Ir-------~~~~~~~7TAr~7~.. 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I RIGHT ROTATE I INC IH03L-__~F~--------,--------------~HT-----------------------~Jt-------~,--------------~KT---------"------------~M9r--------,'--------------~NT--------,,---------------Lpr---J N P R S T M IC7R L ALL RESISTORS I I I I I I I CLEAFi AC HALF ADD I I AC~ I MB~ : MB~--Kl---- MB~: I.r-I AC,', _H_+-+--_«tl : 1* 1_ _ _ _ _ _ _ _ _ _ . -IM.,I I LI H I MB~O I [*- MBk: IM,c,1 : ____________ I MB,',-Ki- MB,'O: 1M" I L ________. ______ ~ AC I i----l I MB~ I MB'O-Ki- I I: 1* I _ _ _.1.. y ..JI MP3 r • 5 - 3 - 13 - 2 3- 3 3 - 4 3 - 5 :3 - E 3- 7 3 I 1-11-21-31-41-51-61-71 i +1 J3 I y- REAl) SlOE ~ Sf' ;;S ~5 4 2 0 0) 2,4,6 i I§' I I '..0 r-I w X x S S T T IN MP3 I X- REAu Silk CI 2 , 4 , 6 ----~ MP4 Memory Stack Diagram 4K BS-E-5-0-11 10-95 Z ~ U 0 II IA21 y Z X WRITE SIDE I 2 i ~I 8 t-++- f-<' 1 ~ :~::~.: r-:. IJ") I- I 9 J, I J i 1 1 1'-' I tt ~, 1 ~- T+ 0 1,3,5,7 ---~------ /--------- I I 15 I D' 70-77~ I 5 I I i I-U- 6 t-- ~ I I J"+ 7, ~ r :r~MP4 SIDE ") 1421 \\X ll 10-97 i-IIN l X-WRITE SIDE J 1 A i ! I I I "A E r<) ! ---ft--P-! ------u----eJ E r<) I I I F 20-23 .., tl"I N N r ..- 1 X - READ r<) I 1 MP3 ~ I E F 0 34:'37 tl"I - E 0 ,.... \( 3 ~r; I pl l r- 0 14 -17 30-33 SIDE 34,36 35,37 C\; D B 24-27 ID C C Y-READ SIDE , II I -: ..... .., C I B 10 -13 35 35 I B C 4-7 +~ ~ 0-3 36 36 ~ r:1 B ,......, 36 3 4 ,36 IA20 (I F F H H J , J '---' MP 4 IA21 CJ 1M; r ... E s R-AC I U I iE I I T W I I M I L y ..r- "I _N I ~,.., I I f-l -- -= E I MEM'~.~ L'--r1N/ REAC - IT - 1 L I I . / N I B· KJ. 45'4 1617 1815 ---r- 4554 1618 I / ~ _ _ _ _ ~----------.J T 45<; '\ IMP SA R x Y _ J.._ +-.-I-------+.A g -~- _-1 .- -1------1---.+---. C x Y J Y _1... 0 E F H J K 0 [ F '1: J K L M N-.,) '\ -'--" '- _--''- ,--,_-_13 V R/VI MPI- ---.-------- - .35 v -13V INHIBIT GNC -35V 7 PIN AMPH X ~ oeD..~lM IAI9 - - IT ME:. MORY RtAD DR~R"AD 1929 IA04 Z ~1--+--+-~-+~ MP2 - c -+ 0 0 IAIS /Y1PI R/W REC {WHT TWP M E ~- Memory System Timing, Inhibit, Sense Ampl ifier Output BS-D-5-0-17 THERMISTOR INHIBIT REDfWHT TwF THE:PI\AISTOR IAI9 MP2 N -t------+-----+-----+--'- .../ ~ TA C K so C ~ U IB28 5 PIN AMPH ~ SENSE WIN DINGM----·---N~/ MEM~RY L_+::===M=t::"== 10-103 N I -f~~~ I ICI8 I I ." : I IAGI E 1607 -= F 'c'Q',1P+JMS}:: ,-------, FI :5C'7 EI'CC" ~ I d~ 113--1-_ 1310 -= I r - ~ 1_ - ~ I '-----< 1.. 01 ~~~~ __L 1 _ELA~ ." C2Il I WOs~?2ft "i-~s-~ ~.J 1. x - I I .-----,E MB~ MBy 0 r-- - : 4127- R i IC 21 1,406- -- - 14 GO 4- ( N I- <" I 4115 R ) .J R rS ,IA155 Z w E ~ -'~'--, I rl 1 1 - - - ----' .:.LL DIODES 1-ISvICCN'IFCTEO T0 ~ 3K 1 19 ::-2 ARE D-C 03 1;21~ IOHLTl1y I N 6f MFO W y ;t. 1982 I; 21 F J K M l.M i i 1~11.:i: TG3 L 1 II~III TGZ0~ K I J ± b =r ----'---- J _ I--+--- E I I I CONTINUE ~ TGOO~II I . I I t I I I, 0 . I I Soo.ET I TE I ME\10RY STAC K 5P-I~ T2 A INHI[?IT WIND ING- I TI ~--~-- ( LUG --r--T--?---- LUI ----~ L 4407 H IF 22 i I I I I I I ~L--,I t I I I CONTROL :.;r--r~_~ L 4706 - - - -- - - 51 ~~ __ ! F2~ _ _ _ I- L----------- LUI.! ------------ _.J;Lqs:~ r- .. --.------ IFI25 , f-::L r-I ~ ~ W POWER. C LEAR -P-= M J'I ~ ____ ,_ _ _ _ - - - - - - - - - - - - - - - - - c;>- --+ - DO " II -,-J-L---.J>..L---,J-.L.---,-J--------r---T~ ~c:..7 r • 0 I lOT -t-..:-_~ L AC~ AC~ ~t A c~ ~c T x AC~ rhc- IF'24 47J7 LUO CLoeK 5 03t' r: T- [j T A -tIC -15 V A C C V \ .- 680 N1 6 ~- .n. NC - \ KS 1689L3 _ F ;:::IN h YIP PI~J ~E :,1t-LE --i~Cl\NO'5 to L _ -:-2t T TE~YPE' ~_tl~ 1 ~ PRINTER SELECTOR MAGNETS KEYBOARD GENERATOR f-IN AMP ~..:?INTE.R L IC2b3i.) '2~ I 220JL iW ~ 1°,003 ~~~;k.f-Cx~ I 1 I ASR 33 TE LEPPINTER WITH 01 AL CAL l CON T R OL UN IT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----" \ \ ~- ( TERM RC' ARr IF29 T 0 V ,F I A T 4 :; 0 V .iF C 22 PI N MALE AMP 0 22 PI AMP FEMAL r L/_: TELETYPE KE Y BOARD GENERATOR 71 6 I LtCQ':.1.L I I PRINTER SELECTOR MAGNETS REMCVE WIRE F~orJ PIN II OF. PLUG4 AND CONNEC T TO THIS POINT ASR 33 MODEL TC WITHOUT DIAL CALL CCNTROL UNIT 1-/.] POW sw WHEELOCK 2C2-2L5XI DTP PIN L2 POW sw PtN LI I Keyboard/Printer Control B5-D-5-0-18 10-105 ~ I M I I "~ ':JEMBL Y I -=- - 1 - - _.-1.. rOT 032 Tl- "1-4 ;~l_~22tT24J ) I T43 I H -- I E FE_.£: I' 225' 4 IF 2 3 IIIz~~~~ t..MP \1A;E. .. ORr -j -- - - I I I ..J . ___ 4 F) I T7 5C PIN AMP (T4 IN PRINTER I I ! c - NO rG ~,--- , 4102 106 1--- - \ $-- 1 I I I IF 29 CLEF -: SIDE) N~ I I ror's -:f'D I - L L-:J.... ION liNt:: : C'FF LI r,;c SWITCH ':f I ~/-t '~ LUOi;- 0-'44 I-= ~50fl V,...._ _-,-, .-_ _-, ~:...I.i-l___ ~,v ~P: I 101 -I N -=- - 41021, 1006 I I _ _ .J Output Bus Drivers BS-D- 5- 0-31 10-107 ,-----, , 1685 ' I i IJOI+IJ02 I 1684 ;:=12 IF06 Acl~4BDl--~-----~l o I ~D MB I _-.:....:.1K=--c I o 1, r iJ03 I BD J---.'=-L-'..-'--+--41 I MB~ I AC: 2 1M I I 3 I f;C 2 I I RI I I L ____ .J r I IF07 LI AC~ , I I 3 T B~ ----'-:....:1u~ BDJ........:...-'..-'_---1-..... B ___ : S--eI MB~ !J03 ~L~I_ _ _-+~27~_ _ _~4 I I i---!---+----+-29 41 BDf---'-R-,-:_---+--41 --+ I ~~I______H28 I , L ____ s MB~ - _ - II<--<;:l 80 6 MB 30 I I ~ I AC6~ T I 7 L I 10 31 I I 1M, N I II 32 ---'---Co! 80 I----_+_. I 11.8:,-__Iu=-96D~T_I_---+-- SCD -12 I I I S -=- -'REG. - -'- - IllS 14127 IL25 I - - CLEAR-r 6'-C>CLEAR PA 2 '{,. AR 10K I iW -- U --::-;-5~ l Z -=- . F' --lH- I PA 1 AR !-,'>RLOETAFTTE ~~ 1 ~ I 1 _ I L23 ..Y1. 1 .. - - --' : 1- - - -·-'-----1 - -- -; ~ 1--- - - - T - - - - l 1 14606 IL20 I I I ~--\1F' TGF~ ~W TGp LAw; PA x 0 TGO 2 1 4· 5 - u ~ ~ 22S1. -= - T~' 0 - .T 22.n Y ::- "0 ,z __ R ~ MUL , ~ L - - __________ .J I I I 14606 -- :,IV _- - - " __ ..1 NOTE AR Control, lOT Gen., Step Counter, Time Gen BS-D-153-0-5 10-111 ," -,- - L~~~-~---·-: I ~~~-12~- - ' r-I--~I -: - - - -, -- - I EXT Tb) TGP O 0 47~ ~ - - -, - - - , - - - - , ' L :- - PI - 1 o ILl6 1::- 1.. -_-_-_- 1-' - TG 2 1 -_~,TGP2L N I K ' , ISC'J'O--)t-, '_ I I M -.<~ -=-....L -'- 14113 I IL2 3 __ 7 TC'o: TC0 , I - - -- I I ~ ~I 'L 1: tU<~ Jc,lftH co~t:'R - "V DIV-Df l , I MlIl TIPLY L._ I PLUGSILOI ..-IL02 ARE BUSSED TOGETHER I - ' , I' 1 IZ TG 0 '.Lz ~: ~ -. f'lliL- •~i--0~' y - ,Y I MD : - I 1_ 1 --,-- -----~ ' ; : '--_----'I R ENABLEI - I:-,- - - - - - - - - . : . 1 ~' X - -= (L16 s ~ ~:1 I ~ -=- I STEP 4GC1') TGIII~X i x I'Ll8 I II' 1 '( MOoll--Ci...J L ,..: M N I I'L23 OIV -- __ iI 41=,05 ~I-'ILld - F: I : ~ IIK20 r--~ J L I .I~.~'+.L 41"2-R Z14113- Mo.->AC MULoGof.szo 1E1H J tl ,SC[;-o41t/';_ AR ~ i A~Ic~b~·------h8~ _~~.:__ =_C.< .~ IL 011-(/""-+) - - - ~. - - - !.~ --p l 31'---------tI-:--=-C::L~-----~--_+j-:-c..J..-----------II-~-c-'=~~---------+l:....A8.::.-c.L~-----------_+A-9 -------------l:....~O...:C291------------1~1~- =IC. !.IO~I c--", __________]t-:....:c. l - "il C.: ._8><..1 ----- IL02 I -~ - NOTE I. PLUGS ILOI tlL02 ARE BUSSED TOGETItER. MQ Register BS-D-153-0-6 10-113 LI NK0 IL02~,----------------------------------------- :LOI LINKIND~~R __________------~----------~------------------------------------------_________________________________~ ~1_3_____________'__14_____________1~rl-5----------_r1-6-----------.-17----______-T_i8__________~!1_9___________Ti2-0------------~T-2-1----------+-22___________~+_2-3--------2~4_v.~ ARIN~~O~:~~~-A~~~~~-----------------B--~~--~i,==-r-C~~~==:-_--_---r-D-~-__-_-_-_~-_-_-~-_--~--_--_-_-+-----------F---~___~-H----~!----~~-----~~--~I---~----~r-N----~!I'---',PP) ---------------------------~----~----~----~----__r------~--_L__---~------~----~----~----~------t-----~----~'----~I------r_----_r----_r------r_----r-----~----~_4--_. ,,7 x! w Iv u ~ I I F I J (T 1L70 Y ALL R'SISTORS 3.3< I I, T f L I K ' IJ 'f _ I , Z \ L ¢ AR COMP (T4)(T~ IL02 ILOI ~IL02 tE I E AR~AC----------------~-------------- NOTE I PLUGS H ARE BUSSED TOGETHER. AR Register BS-D-153-0-7 10-115 J ---------------. - -T------------·- MULTIPL Y DIVIDE. TIM£. .PULSE:. DIV _ 8 DIV _ 11 -~---------~L~---~l~-- -------------------------- --l SE.T UP CONDITIONS MJL FIRST DIV. FIRST SC=O T (iiR + AC) T ~ i.e) (AR J I X-QR j ' I AR = DIVIDEND 0-11 I ~ T2 I I CARRY INITIATE ~-1~.0~-~2~.0~-+----~-----~----~--~-----------~-----~CARRY 5[=13 O-RUN STOP I I I I ! I -------- I ~_ _~-1- JLJrlK=l L-J-------~ :(=0 AR I --T-------+------ - - ------------ - --------------l I T4 . S/OP 'JIV O.F. I .---~~---. I~;: EHIFTRIGHT > I +l-SC ,--~--' (AR + AC) (AR - AC) = r-lJLTIPLIER ~~ o --+ RIJ. ~TOP 3.0 - 4.0 ~ ROT AtE LEFT AR LINK =0 T5 1-~ r-D-I;:;_-lAsT +1 1M ~ --+ SC L1t,K =1 _O-MO ~;;~JL1l9~BQLLEFL ~UL_ Si:n & ReTATl CD~JNECTIONS ROTUE LEFT -- ____ _ ~ SC c 12 All LINK=O O_RUN, STOP 4.0 ~ 5.0 qOTATE LEFT DI\,IDE LAST TG C(J!1P. DIV. 6 AR RIGHT St'IFT ~~_Jf-------.J~L- __ AR _ _- " LSI:! rUTIPLIER OUT o IN 5.0 - b.O DIV.A 0-11 AC = MJLTIPLICAN 0-11 I I C(J!1P =0 ~------~---~------j I I 20 - 3.0 AR ~ PROP~GATE I T3 = Dl'lISOR 0-11 CARRY I I I I PROPAGATE _______________________ = DI~'IDEND 12-23 AC L~ 1 ~~~.o~~-~~~-~~i-~-~----~~~~'--~·~~-·~----~I-------~~ ~ ~ Flow Diagram, Automatic Multiply and Divide FD-D-153-0-11 10-117 A C-8(1) SF-')(C) SF-ICO) S F-2(O) SF-3D) SF-4(') AC-9(f) AC-IO(l) AC-II (I) 5 F-5 (0) INT. ACK. I 50 PIN CANNON F l..- .~\ 4127 1 I 2AI6 S.R. ~ FIELD E .. -'V\~>------, DIMPX~'K '\..-1\1 2-31 14 F .4114 fl, 2A6 . SEL3 01 ADD EX DIMPX SEL 2 J I H I I ~--t-_ _----;_H~~ II 50 PIN CANNON I KEY LOAD ADDRESS IOT~--~~ I 2X4 2A28 SAVE jtl FIELD I SO PIN CANNON 2A28 J!tP JMS rop I ~'+--t:::f--t-~ lOP 2 --Hl4--I--+-}--=-tI I 0 P4 -t-4*"I:-f-+-~ 21 TOT 2X2 50 PljI( C;" ''IN'JN 2A28 <;:CK c. •• ' 40 ~r---r----'----'I------'I----~ M8 6 (0) MB 5(1) MtO 7 (0) ME' 7 (I) r,16 I-: (0) Mf:' ,,(I) "I -15V Memory Extension Logic 10-119 BS-D- 154-0-4 o o rn » OJ L o z o-I ,;t -------- r r---,---------~ ttl '" 'i ~ o z POS. CAP. 0 I ODE ~'~ ~J30R ~l' -±-B I T CQUIHEB.___g~ .-r PULSE INVERTER 41 29 N pas. DIODE o NEG, 0 lODE NOR 4112R 01 4-8 I T COUNTER 4215 ~ INVERTER 4102R 4>0 NEG.DIODE NOR 4114R z ~ ~ + l' o ~ ~LOC~ __ 4401 ~ PULSE GENERATOR 4410 CJ) DELM (ONE SHOT) 4301 o PULSE AMPL I F I ER ( --- .... iiI DIODE iil -I DIODF m iii DIODE I NVERTEK NEG, DI ODE j N '"1:: ~HJDL (;j r------ f/I POS._~AP,DIODE GATE 4130R LOAD RES 1ST ORS PULSE Ar~PL 1009 LEVEL Ilr~PL It 1t:R ,4678 12-3 I T DnC m m CJ) .... .... .... (I) (I) (I) ~DIODE_NOR 4112R .CD (5 4114R POS, DIODE NOR gjJ} 1(5 ___411L N (;j I'i9_R____ 4L1,L PULSUl!.'1f'UF IER PULSE (jj A~1PL I FI ER ~L~-~ I~ Ui Ul Oi fJEb. 0 lODE NOR 4112R Oi ~~~~==~~Oi ~Jl:II,1:RI~ r-------- -- DlODE NOR iii 4117R --- INVERTER N o 4102R ~ BI NARY TO-, OCT - DEC. 1151 4B I T COUNTER 1-------~SE IIM_RTER N sup, ~~O f 1 4215 -~ /11n. PULSE I iWERTER F' 4127 ~r'~PL 46Gb PULSE I F I ER ''iV" 41 lIn N ~ DU.AL IDELAYLli~E PULSE I NVEflTER ill R - ------- ----- --_. - --- . --- -- - ~ - iii N o ~ ~ 411 I T COUI'JTER 4215 ~ 1 PULSE IlMPL I F I ER 46Gb Il>I N ~ PUI SE l\~lPL.1 F I ER 4604 I~ 140b IN I CRYS1AL CLQCK (JJ _____ 19.8.2.. ~:AR~~'~~~F~ : ! E-- ! -.j T-I(I) N "" N RES I SIQR....!illA~Q ___ 1978 til t---~- I t------------I 'l>I I t----'-- l>I "" (JJ t~1 -.j ~=- ---=-= -===--====, t;;: 4>0 r=--===== Ul I----~----- l>I I (I) CD CD (5 o ~----------------~I(5 = t--- (I) o· ::J N I f--------~- -----l 1-------------11 N (;j til ~ c.;, I u. __ 0 _ _ • • _ _ _ _ _ . . . . _ _ I -0; c.;, Oi --,-.j -~--- ------t-- ~ ~~~ E~: 1= IN ~~-----_____llll t==-==-=--===I ~ ~ _ r-~--- =---=t== RFAD--j£ I IF Sid I ICH 1982 I N ~TQR BO_~Rl:L __ j'iZIL I (jj .n:& I~ BOARD t===t=-=-:.~--=---- 1=-:- I ::;j -t------------i iii r-- I- t iD t--~-_r_----------- ~=t=~= I~ I\l [-----+---- - ~ I~ -l ... .~ ~ s"c~;~_=1: ~ IN i::j .~ ~-~= lUi 1--- ---- (I) ~---~--d~ ~---~=--- ==- - - -----d: I: 01 I----~~___rll ~ I---------il ~ [-- c;; I iii ~; t===~ I~ ~-----fl; ---------- r-' Ul DR I VER -HUS --- 1685 BUS DR I VER 1685 BUS DR I VER 1684 BUS DR I VER 1684 - -~- lD ~: E--~--J~ L= I~ r------------fl ~ \----- -.j (I) CD o f-- BUS DR I VER 1684 f---- --- ----r------------BUS DR I VER 1684 1684 ------- Q -_."-----" "" l1I -- ------~-- -- ------ I~ 460~ PUL SE AMP 460') 1l~~P 4605 REU1Y 1807 -- -"-~------- CRYSH\L CLOCK -~ P~ 4225 ,1:-~:~'''l-U'II~lJ II:.LLTYPI:. TRAI~SMI 4706 HER 470i '\ fT1 :u fT1 CJ ~ .... § (I) iD I\) f------.---- co c ., --.--, Cj r------~--- f-- f------ L: Oi ---~- r-E~JLSE Ar~P PULSE ~ ~ r: N 01 t--'-~------------ ---- i<5 M --i I BUS DR I VER r-r-r---------- -- - - - - - - -- --- - ~-- F= m 1685 ----- r---------------CJ) ~------- VI "" t------ --------~ l::;j '::;j ____ I\l I [JUS DR I VER CD ~-- I ----,-----~---- m ----- ------ --- r----------------1 r---------- - - ----.j Oi ~ "" ~--- 1------ iD t= r; ~. I CD --- ::;j iii _ _ -------------lCD f----~--=====l ~ ~ r--- _m f---- 01 -~-:--=~==--=~-~~ _._-" o ~ f-------------, -~----~~-- m (I) I - - ---- - N Ul .... -.j r- oI 1\ m ~ o ------~--"~ ~ o () c .... I -I' _-W o r=:--~----- IN t---~-- (JI CJ) CD ~ r- ~ i r----- ---- \---- ~-------------f ===J ~ c '" I\l 4>0 3 oI ----- I Vl ~ c.. r. ~ , N ....CD J> F 0 1989 I l>I Oi N N N r~E~'ORY DR I VER ~ I I~ 1311 I~ ·_Jiii ---.J-L~-----4~ iii _ £.ttlIQ -_S-E_INS~A~~P '__ ~45~il -- (I) I NVERLE[L~ ____ rLlr-rLur ~"~-" l::::i iii -- POS ~ 46Gb ____J]lfl.1 N 1--- ----~ ~_ 0 1 OQU'JOfL_~4 LllB_ NO ~ ~ ___ lliL (5 IN 4603 DE:LAY LINE II) = POS, 121 ODE._NOR ___!lJJJ_R_ ' 4113R 1E~~~~:e~u:u:R15721 ~ 0 01 "" POS. DlODE NOR D IN UI 411!B.. ~ ~o 157LI 10V PREC.PllR V0t, (JJ POS. 0 lODE tJOR c I ~? LEVEL AlruFJ~lL_'%ZfL TR I PLE~--+LOP ~ ~ ;00 4678 l>I Ui 1~;rEbRATING j!'JQ'=-:~lIOT4303 I iii 0 IHEL iirWL I F I ER 01 CD 4115R r~OR _ ~LODs :;:jo iJ.b I F I ER -----~ -- 41C6Jl.. POS. DlODE NOR o 1 N -~---- (5 POS , Cgp '_ QlQDE GAlE 4130R -- ----- ..lbOL ,- () N "" --------- 4111 r---- - CD 4113 - r---------- (I) 4604 --- ----- -- -~.-.- 4113R POS I TI VE DlODE NOR 'ILl L f-------INVERTER 4102 () 1: NOR PULSE..1\~~UElER 22 PI N PLUG ADAPTER o I\l N I\) ~ N "" N l1I ~ TO -1'5 v MARGINAL CHE K SW SEE NOTE"4 18 Ej r- I I I~vl 102C 1001F 1)13 '107K 1.21" 1001 ,!,';;',46 I I ~DOEL IDa, 21J 18 17 3 a 14 PLUG BUSS BAR MEMORY PANEL SEE DWG: MA-E ar;- ~ ~ ;= :- I~ I~ c - 5-0-27 III IB - - ( - - ir . . . . . SEE .. NOTE 6 I. ;. , - I' - +K IL 10 USE 1935,OM PANELS TO ~I 5V 9 10- EfJ r= ~ I )05u 1121U II 12 'E9'1i IXJ5~ 11 ~ = ---' 'P21V 19 BEl Aii5 ~ .~ A : A : 18 I ~"5r = - 'M IN If' r-f¥- I IR I )21W 15 'i6OO"D' ~ 4i"i3 T+'~ MARGINAL CHECK 5'1i .. .~ IEo95 r= 20 §] r= - +- 10 j - Ie ~ '-----:'I f - - ,- I 1120T IF 19H 1'003E IFI2' IEOII IEOII I 1'020F IFII5 101 r.- I 'ID09~ IC~:) Oil II l_ '023Y I D07F I,OBJ 024J bl7E IDZSS I IIR NellES; IF 1K ME~ORY IS USED, REMOVE ~t,CKi\GES 19<'7 IAIO AN~ 1937 1~12. ,. ALL RESISTORS LOCATED ON STANDOFFBOARDS ARE 3.3K. 3. UNLESS OTHERWISE INDICATED ALL DIODE5 ARE 0-003. " IAI8A-N AND IAI9-N ARt: YEL!SLK TW. PRo 'SEE DRAWING B-5-0-30 FOR SPECIAL Mt.RGINAL CHECKING PANEL FOR lB. :6 DO NOT RUN ANY WIRES ACROSS IBI5 THRU IB25 UNLESS iT'S GOING TO A PIN LO:ATlc'N ('N ONE OF THOSE PLUGS Wiring Diagram lA, 1B, 1C WD-E-5-0-3 10-123 '[)()9K I" IC215 (--8 ICI6 Y .......-"'J --- ------------- 0.003 I" +~ 20 21 ~IDOIU ~ ~ I' I" to 11 UI II I" lu 1 .~ IT r . IOOIP~ I' 22 ~ 23 = :: ~ -+~ - := ::: i~ ~r - 25 g ··-- ·c - o - , ,J -,- IE ", - ··--,," v - ,w-z- '-- IF NOTES: I. USE 19,5FOM I~GUNTING PANELS_ 2. UNLESS OTHERWISE INOICATED ALL CAPACITORS LOCATED ON 5TAtWl1FF· BOARD ARE 6.8MFQ 35V. 3. ALL RESISTORS LOCATED ON STANDOftBOARD ARE 3.3~ Wiring Diagram 1D, 1 E, 1 F WD-E-5-0-4 10-125 I 10001'1 § I r-- I I ~ I i ( I I I I , n: ~~,_-, ! ~ I ?: ~~ I I Ll r--i ~EAR VIEW NC NC r------6~----------------------~~6 ~ ~-- ~ I (: ~.; ,0gs g i~ o ~ ~: -l- I" START L~ ____ EXAM c--- _ _ _ - CON r-- - .-+-4r--~N~O~--------------------+-~NO IHOS IH06 IHOI n I I INSTRUCTION I 1-0 HLT i I --' MA 'IH02 RUN Me I .j :::> ~(--------------~> ~ ~O~~J_ '0 oK oL_oMo_N oP oR oS ~):: ':T____ u__l_v___._1w___J_x___l_v__!_Z_) ._I IH03 L AC 1"---1 STOP D 0 CONTINUE DEPOSIT 0 EXAMINE LOAD ADDRESS 0 B -15 ~------------~ IH04 SW REG ] -------- --~-- I NC +----0 I A GND ~.~~---------~---------~~~----~~~ C START E 4.7K SINGLE STEP 4.7K LOCK SW K SINGLE INSTRUCTlQN C NC NO I C I L-() NCNO POWER NO H Operator Control Keys and Switches WD-D-5-0-10 10-127 I I ~~------------ J 3 2 I ~?:. , 4 5 4!1' 4?7 - - - - - - - MQ - - 0-,3 -- , C) -- 5 4-7 - - - - -- - 6 -- - - - - - - - - .. ! l ". - -- - - - - - b 3 10-11 COMP AR g ,COMP AR" 13 4. !J"' -Af. ~/ -: AC 6r -AC7 1- -AC S'-'AC: '9 r - J\ t-:r, AR -1------ 12 ·1:0? ;, AC 3 1 16 15 14 ., ·-:1,· ~ 18 17 .:;, (-"oJ {"', ' ;:..() r (~ ~, ,:: :~ -11 ? 19 ~1. ~:> -+-,. 20 -',I' f'l -l, - - - AR6 - -- AR - - - - - - - - - - - - -- 6-7 S-i! -- COMP AR2 CaMP A R4 COr..1P A.R-~AC --ACIO r AR 4 -5 - ------ - - I I I I I I 1 I 1 IL caMP COfo.1P CaMP AR7 ARS AR3 - 4604 4102 I-':UNrROL I 4606 L 1"" AR. CaMP AR tp?~~R~cui ROTATE I (T4 -T6) 1 LEFT f-- - A'R SHIFT L+ MO 2 -3 Li606 4113R x FLAG (T _ \ I OR -co"fp- II II I I I I I I I I ARO AR~AC -a -5 DiV QIV - - 1I1UL - - - AR SHIFT - - - - - - 4218 I TG" C. -- - - - 0 1 TGP i - TGP -' - - 0-1 - - -- - LINK RUN - ARI - - 2 0 - I I f I i I ! ! I 4115R SC SCD-O o - - 4113 4114R - - -- DIV - - - - SCl)-12 - -, FLAG L I-- - - - - TGo - -- - - TG O - I ! I I I ; I I I I I I I - AR OVERFLO I , i I I I I Utilization Module List for Type 153 UML-D-153-0-3 10-129 - - -- - - - - - - OIV DIV' PYEBEL9~ I I I , FLAGO I I - -- 1--- - - ! I - -- RUN O RUN - - - - , --.--scc -12 ,::,CO-12. FF - - SC 2 4127 -SKIP - - FLAG I SC 3 I -- - LINK 4215 - -- -- . CLR a A'R I I CONTROL AR - COMP SC I 0 TGP 0 FLAG - - - - - - - ,- (T- I·) POWER - - - AR - - - - ENE 4606 - - OVERFLO 1----- i I I COMP - I I I DIV I I I I PULSE TGO-2 RIGHT (T - 4) A.R X OR I 25 421'::: - 1-- , ~W_E~CL8 I 24 "if' ~p =A=(2~ ~ - - - - .------ - ".- - - (T:t =-l6.t TG CARRY ~~~q2 ~~c CONTROL ROTAn: TG 1 a - - - -LEFT INITA.TE CLEAR CA-RR'Y CLEAR - ,/\,( I-(T..:.:-';i)_ (T- 2) ENABLE TG - -- -- -. - - - - L-+MO REA-O- - - -- X-'O-R- - - - -OX OR ~HIFT CLEAR DIV MR-+AC SAF ,- ! 23 42 () ') - "'~U L - -- REG ClR M~L GO MC~AQ AR-7AC AC~AR szo 22 4;; ?,p - CAR~'( 4605 4605 : -A"(l r AR AC 11 14605 2I d.! " AC 0 1 -- AC ~I- ARe MO - ~ COMP 8-- !i II I1 '.., - ".- : i.: -:', 1--\ :- ARI0 - - MQ-AC MQ MOi AC <'f:_~ COMP - - 10 9 L; (~ :: ' - - - - fK 4," - - 8 7 6 ,~ ROT m ._ c_ o- ma_ co- f- f_ f f_ _ .- m rrL . - H~ :~ f----J , lru': x_ y- z_ lru':I x_ y- z_ N_ ;~ ni . . "l 1935 FOM:: D. :~ N_ MTGA PANEL:: c_ ..-.., - [tn ~ ,~B , u_ w- '] ,. I- c_ o. c_ U M_ - r - I*-t. , M· 8 - J J! I::::::::'. 1 ' u_ g[t .. '---- - Bv .-.- --'- .-,- o. c_ 0_ 0_ .-- , ' H_ H- .., ,- ...c· , M_ M. .. .- J ....,-= JI ::e h , I-- .. u_ B I H_ ' 'u_ - v_ .. :~ ..,,. ,- '-- '---- '---- w- U ,. .-.-,..-- r-- A- BN- ,. '--- .- ,- M. u_ B r-- M_ ,- r-n I- r-- .-.- .- o. , IK ~ ,----:. w_ ,. r-- I 4 5 6 7 8 ..-H_ ,- , ,- - u_ u_ v. v_ ,~ l=:::::::' '''i . ,- ' ,- W· ,- :t w_ , ,. == '-- l I 10 r-- . ~ ~H MI ~ -E eF IH 11 I- ,,. I I , ' - II .- l ,~ tJ 'K'L .IV: 12 ~J ~ P I RI . S . u_ ! I----W p~ ,- .c_ .- a_ a- , . M_ - , N_ .-.,,- v. uv_ Iv. w_ w_ W· w_ .. I- e_ e_ ,. ~ '-- tT eU eV eW.X eY ~i '---- ;~ r--f-'-- i w· ,. ,. ,- '-- '== ,- .z J ,- ,. .'1.1 /K99 4 ..: ~ 14 15 .z I 16 /,17'1 17 18 - .-'8 Ii P I I ~K I ..' M_ N_ ,. '---- '---- 'll ~L eM eN"P eRes --T I· ,. U p ,- '-- ~ ~V . aw ~~X > : . Z Y '> ~ > c ~ iK IL eM .N eP eReS tT tu av tw ex .y -J 21 20 22 23 24 • E eF _H 19 w· w~ .U . I ~: I v- W. ,,,",,- H_ , r. u_ Ii CI '-- M_ I:: ,- :~ ,. , M_ ~~ ,. .-.,,c • N_ .- W. N_ , M_ I~: I ,. M_ , ' II c. .., - .. ,- ... ,- ,. ,. ""8 mm ., -- I .- c_ a. D_ H. ,- .. .- A- c_ - 25 ",/;;1/5" .- I. ,- '-- E • F ,H 4 J :~ , l I ' N_ r-~ N_ :~ t-- t-- w- '---- M_ r~ ,. J .-, . .-..1'I :: I m .. :1< ,. K_ I· ,- D_ N- ,- c· I. D- c. .- I--r- t - M_ 24 r-- .- A- ,- ' II!'"B ,- .- I- , I c. m - m m .H_ 22 ;--- c. W· _N e~ eR itS .T .U eV eWeX eV 13 . ...- , 21 q'//"3 E - , ,. M. , r--- t - - E. ,. H_ ,- c_ a. c. M. M- N'8' .- I- v. ,- ,- ,. 20 19 "1;)17;5 ..........- v_ v. :fl N_ M ,,. u_ ~ E _ I 4 J • K4 L . ·. ~ -- 4E • F N_ w- ' .. M_ I:-t ,. - 'I ,c-==: :s: ,- - .- L w_ , , , ME! - , . w_ x- , H_ H~ ,. v_ 9 M_ N_ N_ , :~ f - ~- ~.: ,- , M. M_ M_ - .-, - - ' ··-- ~'S I- o. 0_ ..,~l-- r--- ...-, - I .- I- o. .-, .., --- ' M_ IL7& 3 I- c- 0_ 1t:l{o 2 I- c_ I ..- n 18 m m ~ m .. m m .. .- AI- i""- 16 14 12 10 2 ~ .z I 25 IL 1935 FOM MTG PANEL-t 1939 B .. ' 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 .-. NOTE: ALL RESISTORS AHE 3.3K Wiring Diagram 1K and 1L (Sheet 1) WD-D-153-0-4 10-131 23 24 J 25 2 /1( /'13~ rt?/Yl /17 Tv /'fi/'/E£.. I: I Iw':1 I _ ~ _ 1_ 1_ u_ u_ 11- v_ w_ w_ W _ ~ .1_ X_ .l_ 2 IL 1935 Fom />fT,,~, 'ph/VE';:" ~ /7398 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 f:l I:~.- I:~ I ru :: ~ u_ • _ I - I,' Wi;;I u_ v_ w_ ... - X_ le_ ,- ,- 1_ z_ I~: I [j Wiring Diagram 1K and 1L (Sheet 2) WD-D-153-0-4 10-133 24 25 4151 4 43 ' 41 G2 I NT. 3 .2 I 4 5 1.\15', 4151 DE:CJtR DECODER IF 8e 10 7 8 9 4605 QbJb 46Gb 4218 o-SAVE SR-.++ BUFFO (1) OF ADD Flc-LD D. F. J F 1tLD - -' t- - t- - t- - 1 ADD 1 4127 13 i, 127 - - 4218 - t- I 14 15 16 17 18 4218 4217 4217 4220 4102R ItJST DATA F IELDO FI ELDO ff¥r - -- 19 4218 INST iF 0 BUFF ~ , 1 lOT 2X , FI ELD 16-+-1 e IF_SF 1 1 1 ENABLE INST F: ElO 0 BUFF 2 - -tI ~~ST :....DAD IIIST DATA FIELD, cIEL0 1 7* 1'"-5F F,E.LD - 1 1:'15T G;.Ji~ F IEL02 FIELD2 DATu r- J 5F-2 (Q) 3 SF-3 (0) ~ -1- FI ELC SAVe: -I FIELD -I- 4 1 51'-4 (0) FIELD SELECT .r- I~A F' ELJ , 5 $0-5 (0) - r- -t- IF~C7(;) MlD EX 2 - P J UMP IF~C8(1) , SF r--AC 9( i ) , Sflr+ACW(1 ) DF~Cl0(1) SF~Cl1~1) DFrAC11 (: ) I 2X4 I I I I I i I I IF _ eJABLE OF EIJA3LE OF ENABLE 3F EIJABLE BF ENABLE 1 OF ENABLE ~1,J~th6 lOT 224 CLEAR IF CLEAR ENABLE FlELD lOT 214 E1 lOT 234 " I IF ADD EX 3 I I I E~IABLE SET BF: I I J~15 1 DF~C9(1) I I ACK f-- 'OT SET BF 2 I 4113 ~'r-AC7(1) I I NH I BIT I 4113R I~IT. SF~C8(1) SET 8F O INT. 4112R IF~C6(11 F I ELD2 t-- DATA ADD B. F _ 0 25 - BREAK EX 3 S~VO~ 24 Se~Cc:1) BREAK SI~·:I;'E - 46Gb 23 SF-! (0) F I ELDI SR -j--* , 1 IN::T - - - - - 1-- -SAVE I SAVE 1 - 22 F I ELDa 1 SELECT 21 4113 BREAK 5f"-0 (01 n ~ - 20 SR~ EX 2 '- 12 II INST SELECT DECOCER ENAf3LC f- 4' 14R I tirll BIT (0) INT . 1Nf'l BIT 2A 6 I I I I I I I I I t I I I I I I I Uti I ization Modu Ie List for Type 154 UML-D-154-0-6 10-135 1 4102 Cl I:: 1 2A I OF 2 25 1- H_ ,--I ~ ,_ I ,-I- ~ ~ ,- , , - :: 1 , - , ,- ,- W W W I- 3 4 5 um 6 7 - ,.-I- - c_ 8 9 10 11 r my ;:,,,, --~ 21- _"'/: ~ ---~ T -t~-}K~f~L;~;-;N-~P TH "\t 4-13---- K':. fK I --------_ ;'{,' ,c,r; oN oe ru oR-oS ;T oU oV 0'; ;X oy 02 fJ 14 c_ w I_ , _ 2873 2 , c_ I w_ ,- , ~ ~ fr}" - :: 1 :: 1 0,' oS or oU oV o. oX oy 02 ~,)/-'-tT 15 ·*?Ai 15 17 18 19 20 21 22 .- .,-- I I ,--I .' -- I ,-I , c_ l~: I 8 I'·--s _ , 8 1== 1 w- W 1'- Wiring Diagram for Type 154 WD-D-154-0-5 10-137 24 25 ,,- m : : 23
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