Force_SPARC_CPU 5V_Technical_Reference_Manual Force SPARC CPU 5V Technical Reference Manual

Force_SPARC_CPU-5V_Technical_Reference_Manual manual pdf -FilePursuit

Force_SPARC_CPU-5V_Technical_Reference_Manual Force_SPARC_CPU-5V_Technical_Reference_Manual

User Manual: Force_SPARC_CPU-5V_Technical_Reference_Manual

Open the PDF directly: View PDF PDF.
Page Count: 464

DownloadForce_SPARC_CPU-5V_Technical_Reference_Manual Force SPARC CPU-5V Technical Reference Manual
Open PDF In BrowserView PDF
SPARC CPU-5V
Technical Reference Manual
Material Number: 203651
FORCE COMPUTERS IncJGmhH
All Rights Reserved
This document shall not be duplicated, nor its contents used for
any purpose, unless written permission has been granted.

Copyright by FORCE COMPUTERS®
Part Number 14028101 420000 AA

NOTICE

The information in this document has been carefully checked and is believed to be
entirely reliable. FORCE COMPUTERS makes no warranty of any kind with regard
to the material in this document, and assumes no responsibility for any errors that
may appear in this document. FORCE COMPUTERS reserves the right to make
changes without notice to this, or any of its products, to improve reiiabiiity, performance or design.
FORCE COMPUTERS assumes no responsibility for the use of any circuitry other
than circuitry which is part of a product of FORCE COMPUTERS GmbH/Inc.
FORCE COMPUTERS does not convey to the purchaser of the product described
herein any license under the patent rights of FORCE COMPUTERS GmbH/Inc. nor
the rights of others.

FORCE COMPUTERS Inc.

FORCE COMPUTERS GmbH

2001 Logic Drive

Prof.-Messerschmitt-Str.1

San Jose, CA 95124·3468

0-85579 NeubiberglMunich

U.S.A.

Germany

Tel.:

(408) 369-6000

Tel.:

(089) 608 14-0

FAX:

(408) 371-3382

FAX:

(089) 609 77 93

FORCE COMPUTERS France S.A.R.L.

FORCE COMPUTERS U.K. Ltd.

Le Volta

Alton House Office Park

17 -19 rue Jeanne Braconnier

Gatehouse Way

F-92366 Meudon La Foret Cede>:

Aylesbury, Bucks. HP19 3XU

France

United Kingdom

Tel.:

(1141 0795 15

FAX:

(1)

45 37 06 19

Tel.:

(01296) 310400

FAX:

(01296) 310420

FORCE COMPUTERS strives to contribute to the safety and preservation of the
environment with the same care it applies to the performance and quaiity of its
products.
To support this effort, this Product Manual has been printed on paper that is completely chlorine free and conservation friendly.

cpu-sv Technical Reference Manual

Table of Contents

List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table II.

Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.

Specifications of the SPARC CPU-SV .............................................................................. 4
Ordering Information ......................................................................................................... 6
History of Manual.. .... .... ......... ....... .... ...................... ................ ............ ........ ..... ....... ...... .... 8
Default Switch Settings .................................................................................................... 12
Device Alias Definitions ............................................ ...................................................... 22
Setting Configuration Parameters .................................................................................... 23
Diagnostic Routines ......................................................................................................... 25
Commands to Display System Inform.ation ..................................................................... 29
Front Panel Layout........................................................................................................... 33
SPARC CPU-SV Connectors ........................................................................................... 34
Ethernet Connector Pinout ............................................................................................... 35
Serial Port A and B Connector Pinout ............................................................................. 36
SCSI 50-Pin Connector .................................................................................................... 38
KeyboardIMouse Connector Pinout................................................................................. 40
VME P2 Connector Pinout .. _.................................................................................. ........ 41
IOBP-I0 PI Pinout........................................................................................................... 43
IOBP-10 P2 Pinout (SCSI) .............................................................................................. 45
IOBP-I0 P3 Pinout (Floppy)............................................................................................ 46
IOBP-I0 P4 Pinout (Centronics) ...................................................................................... 47
IOBP-I0 P5 Pinout (Serial).............................................................................................. 48
IOBP-IO P6 Pinout (Ethernet) .~ ....................................................................................... 48
Physical Memory Map of microSPARC-II...................................................................... 54
Bank Selection ................................................................................................................. 55
CPU-SV Memory Banks .................................................................................................. 56
MEM-5 Memory Banks ................................................................................................... 56
Physical Memory Map of SBus on SPARC CPu-SV...................................................... 57
NCR89CI05 Chip Address Map ...................................................................................... 63
RS-232, RS-422 or RS-485 Configuration ...................................................................... 64
Serial Ports A and B Pinout List (RS-232) ...................................................................... 65
Switch Settings for Ports A and B (RS-232}.................................................................... 65
Serial Ports A and B Pinout List (RS-422) ................................................................ ...... 66
Switch Settings for Ports A and B (RS-422}.................................................................... 67
Serial Ports A and B Pinout List (RS-485) ...................................................................... 68
Switch Settings for Ports A and B (RS-485).................................................................... 68
8-Bit Local YO Devices ................................................................................................... 70
Boot Flash Memory Capacity ..............................•...................................... ..... ................ 71
User Flash Memory Capacity ............................................•............................................. 72
Physical Memory Map of VMEbus Interface on SPARC cpu-sv ................................ 79
Front Panel Layout....................................... ... ............ ........ .... ................. .............. .... ...... 83
Interrupt Mapping. ............................................ ........................ .... ........ .... ....... ...... .... .... 109
V}dEbus Transaction TImer Timeout Values ................................................................ 153
Watchdog Timer TImeout Values .................................................................................. 156

FORCE COMPUTERS

Page vii

This page intentionally left blank

Cpu-sv Technical Reference Manual

Table of Contents

SECTIONl INTR.ODUCTION .................................................................................... 1
1.
1.1.
1.2.

1.3.
1.3.1.
1.4.

Getting Startec:l ........................._............. .............•...... •.•• .................................... ..... 1
The SPARe CPU-SV Technical Reference Manual Set .................................................... 1
Summary of the SPARC CPU-SV ...................................................................................... 2
Specifications ...................................................................................................................... 4
Ordering InfoIDlation ................................................................................................. 6
History of the Manual ......................................................................................................... 8

SECTION 2 INSTALLATION ...................................................................................... 9
2.
2.1.
2.2.

2.3.
2.3.I.
2.4.
2.4.1.
2.4.2.
2.4.2.1.
2.4.2.2.
2.4.3.
2.4.4.
2.4.5.
2.4.5.1.
2.4.5.2.
2.4.6.
2.4.7.
2.4.8.
2.4.9.
2.4.10.
2.5.
2.5.I.
2.5.2.
2.5.3.
2.5.4.
2.5.5.
2.5.6.
2.6.
2.6.1.
2.7.
2.7.I.
2.72.
2.7.3.

In'trod.uction............................................................................
89
Caution ................................................................................................................................ 9
Location Diagram of the SPARC CPU-SV Board .............................................................. 9
Before Powering Up .......................................................................................................... 12
Default Switch Settings............................................................................................ 12
Powering Up .............................. ..... ......... ................ ............................................. ...... ...... 14
VME Slot-1 Device.................................................................................................. 14
VMEbus SYSRESEr EnablelDisable ..................................................................... 15
SYSRESEr Input ........... ............. .............................................................. ...... 15
SYSRESET Output ......................................................................................... 15
Serial Ports ............................................................................................................ '" 15
RESET and ABORT Key Enable ............................................................................ 16
SCSI Termination ............•....................................................................................... 16
SCSI Termination at the Front Panel............................................................... 16
SCSI Termination at P2 ................................................................................... 16
Boot Flash Memory Write Protection...................................................................... 17
User Flash Memory Write Protection ...................................................................... 17
Reserved Switches .......... ......•............................. ..................................................... 17
Parallel Port or Floppy Interface via VME P2 Connector ....................................... 18
Ethernet via Front Panel or VME P2 Connector .................................................... 19
OpenBoot Fimlware...........................•.............................................................................. 20
Boot the System ..........................................................................•............................ 20
NVRAM Boot Parameters ....................................................................................... 23
Diagnostics ............................ ... ...... ................................................................. ......... 24
Display System Information ..................•................................................................. 28
Reset the System .............................................. .............................. ......... ... ..... ......... 30
OpenBoot Help .. ...................................................................... ....................... ......... 30
Front Panel ...•..........•......................................................................................................... 32
Features of the Front Panel ...................................................................................... 33
SPARC CPU-SV Connectors ............................................................................................ 34
Ethernet Connector Pinout ....................................................................................... 35
Serial Port A and B Connector Pinout ..................................................................... 36
SCSI Connector Pinout ............................................................................................ 38

FORCE COl\fPUTERS

I .....................................

Pagei

Table of Contents
2.7.4.
2.7.5.
2.7.6.
2.8.

CPU-SV Technical Reference Manual

KeyboardlMouse Connector Pinout......................................................................... 40
P2 Connector Pinout ...................................................................................... 41
The IOBP-I0 Connectors ......................................................................................... 42
How to Determine the Ethernet Address and Host ID ...................................................... 49
~

SECTION 3 HA.RDWARE. DESCRIPTION ...................._ ...................................... 51
3.

Overview ________•_ _._................_ _ _ _ _ _ _ _ _ _ 51

3.l.
3.2.
3.2.l.
3.2.2.
3.3.

Block Diagram .................................................................................................................. 51
The microSPARC-n Processor ......................................................................................... 53
Features of me microSPARC-II Processor .............................................................. 53
Address Mapping formicroSPARC-n .................................................................... 54
The Shared Memory .......................................................................................................... 55
Memory Module ~-5 .................................................................................................. 56
SBus Participants ......................•....................................................................................... 57
Address Mapping for SBus Slots on the SPARC CPU-SV ..................................... 57
NCR89Cl00 (MACIO) ..................................................................................................... 58
Features of the NCR89Cl00 on the SPARC CPU-SV ............................................ 59
SCSI ......................................................................................................................... 60
SCSI Termination .................................................................................................... 60
Ethernet ......... ...... ... .............. ...... ...... ...... .... ..... ....... ... ... ......... .............. ............. ... ..... 61
Parallel Port .............................................................................................................. 61
NCR89CI05 (SlAVIO) ................................................................................................... 62
Features of the NCR89CI05 on the SPARC CPU-SV ............................................ 62
Address Map of Local I/O Devices on SPARC CPU-SV ........................................ 63
Serial I/O Ports......................................................................................................... 64
RS-232, RS-422 or RS-485 Configuration .............................................................. 64
RS-232 Hardware Configuration ............................................................................. 65
RS-422 Hardware Configuration ............................................................................. 66
RS-485 Hardware Configuration ............................................................................. 68
Keyboard and Mouse Port ....................................................................................... 69
Floppy Disk Interface ..................................................................................... ......... 69
8-Bit Local I/O Devices ........................................................................................... 70
Boot Flash Memory ................................................................................................. 71
User Flash Memory ...................................................................................•.............. 72
Programming the On-board Flash Memories .......................................................... 73
Flash Memory Programming Voltage Control Register ................................. 74
Flash Memory Programming Control Register 1 ............................................ 75
Flash Memory Programming Control Register 2............................................ 76

3.4.

3.5.
3.5.l.
3.6.
3.6.1.
3.6.2.
3.6.3.
3.6.4.
3.65.

3.7.
3.7.1.
3.7.2.
3.7.3.
3.7.4.

3.7.5.
3.7.6.
3.7.7.
3.7.8.
3.7.9.
3.7.10.
3.7.11.
3.7.12.
3.7.13.
3.7.13.1.
3.7.13.2.
3.7.13.3.
3.7.14.

3.8.
3.8.1.
3.8.2.
3.8.3.

Pageii

RTCIN'VRAM ..................................•..............................................•........................ 77

VMEbus Interface ............................................................................................................. 78
Address Mapping for the VMEbus Interface FGA-5000 ........................................ 79
Adaptation of the FGA-5()()() ................................................................................... 80
VMEbus SYSRESEr EnablelDisable ..................................................................... 81
FORCE COMPUTERS

cpu-sv Technical Reference Manual
3.8.3.1.
3.8.3.2.
3.9.
3.10.
3.10.1.
3.10.1.1.
3.10.1.2.
3.10.2.
3.10.2.1.
3.10.2.2.
3.10.3.
3.10.3.1.
3.10.4.
3.10.4.1.
3.11.
3.11.1.
3.11.2.

Table of Contents

SYSRESET Input ............................................................................................ 81
SYSRESET Output ......................................... ................................................ 81
On-board Control Registers (System Configuration) ....................................................... 82
Front Panel ..........................•............................................................................................. 83
RESET and ABORT Keys ....................................................................................... 84
The RESET Key .............................................................................................. 84
The ABORT Key ............................................................................................. 84
Front Panel Status LEDs .......................................................................................... 85
USER LED 1 Control Register........................................................................ 86
USER LED 2 Control Register........................................................................ 87
Diagnostic LED (Hex Display) ................................................................................ 88
Seven Segment LED Display Control Register............................................... 88
Rotary Switch........................................................................................................... 89
Rotary Switch Status Register ......................................................................... 89
Additional Registers .......................................................................................................... 90
FMB Channel 0 Data Discard Status Register ......................................................... 90
FMB Channell Data Discard Status Register ......................................................... 90

SECTION 4 OpenBoot ................................................................................................. 91
4.
4.1.
4.2.
4.2.1.
4.2.2.
4.2.3.
4.2.4.
4.2.5.
4.2.6.
4.2.7.
4.2.8.
4.2.9.
4.2.10.
4.2.11.
4.2.12.
4.2.13.
4.2.14.
4.2.15.
4.2.16.
4.3.
4.3.1.
4.3.2.
4.3.3.
4.3.4.

Sof'tw'are •••••••••
'1'
91
OpenB oot ........•......•.............•......................................•................•.................................... 91
I'

•

I

. . . . . . . . . . . . . . . . . . . . . . . ., . .

"

•• 1

......

•

•••••••••••••••••••••

I

..................

VMEbus Interface ............................................................................................................. 92
Generic Information ......................................... .............................................. ...... .... 92
Register Addresses .............................. .......... ... ... ............. ................................. ....... 93
Register Accesses ..................................................................................................... 98
VMEbus Interrupt Handler ......•............... .............................................................. 108
VMEbus Arbiter..................................................................................................... 112
VMEbus Requester ........................................................... ... .......... ...... ......... ......... 113
VMEbus Status Signals.......................................................................................... 115
V1\1Ebus Master Interface ...................................................................................... 117
V?ffibus Slave Interface ........................................................................................ 127
VMEbus Device Node ........................................................................................... 131
VMEbus NVRAM Configuration Parameters ....................................................... 133
DMA Controller Support ....................................................................................... 142
Mailboxes and Semaphores ................................................................................... 146
FORCE Message Broadcast................................................................................... 148
Diagnostic .............................................................................................................. 151
Miscellanea ............................................................................................................ 152
Standard Initialization of the VMEbus Interface ............................................................ 154
SPARC FGA-5000 Registers................................................................................. 154
VMEbus Transaction Timer .................................................................................. 154
SBus Rerun Limit .................................................................................................. 154
Interrupts ................................................................................................................ 154

FORCE COMPUTERS

Page iii

Table of Contents
4.3.5.
4.4.
4.4.1.
4.4.2.
4.4.3.
4.4.4.
4.4.5.
4.4.6.
4.5.
4.5.1.
4.5.2.
4.5.3.
4.5.4.
4.6.
4.6.1.
4.6.2.
4.6.3.
4.6.4.

4.65.

CPU-sv Technical Reference Manual

SBus Slot 5 Address Map ...................................................................................... 155
System Configuration ..................................................................................................... 156
Watchdog Timer .................................................................................................... 156
Watchdog Timer NVRAM Configuration Parameters .......................................... 158
Abort Switch .......................................................................................................... 158
Abort Switch NVRAM Configuration Parameter.................................................. 159
LEDs, Seven-Segment Display and Rotary Switch ............................................... 159
Reset ................................................•...................................................................... 160
Flash Memory Support.................................................................................................... 162
Flash Memory Programming ................................................................................. 162
Flash Memory Device ............................................................................................ 164
Loading and Executing Programs from USER Flash Memory ............................. 166
Controlling the Flash Memory Interface................................................................ 167
Onboard Interrupts ............................................. _................ ..... ...... ... ............. ............ .... 169
~us Interrupts................................................................................................. 169
SYSFAII.. Interrupt ... ...... ................. ..................... ......... ... ...... ............. ...... .... .... .... 170
ACFAII.. Interrupt ... .......... ...................................................................... ......... ...... 171
ABORT Interrupt ................................................................................................... 172
Watchdog Timer Interrupt ..................................................................................... 172

SECTIONS CIRC'UIT SCHE.MA.TICS ....._ ........................................................... 175
.

..... _ _ _ ....

......_._.175

5.

CPU-SV Schematics ....................... .

5.1.

MEM-5 Schematics......................................................................................................... 176

SECTION 6 SUN OPEN BOOT DOCUMENTATION ____••___............ _.177
6.

Insert your OPEN BOOT 2.0 PROM MANUAL SET here. .....

..

............._177

SECTION 7 APPENDIX. ............................................................................................ 179
7.

.. .............. 179

Product Error Report ......

SECTION 8 USER'S NOTES .................................................................................... 181
8.

_11_.__..._..._...___.................... 181

User's Notes_
..._..._.IT_Jl._._ _ _ _._
..._..._..._..._..._.. _
... _...

SECTION 9 O'PTIONS .............................................................................................. 183
9.

Pageiv

Additional Options_
•••_.. _._ _ _._
..._.. _..._._
..._•••_ _ .............. _ . _ . _ . _ .__•• 183

FORCE COMPUTERS

,r--' .

Cpu-sv Technical Reference Manual

Table of Contents

SECTION 10 MODWICATIONS ............................................................................... 185
10.

Additional ModificatioDS_....... ..... ___•____•_____•__•______._. 185

SECTION 11 APPLICATIONS .................................................................................. 187
11.

Additional ApplicatioDS_,_ _ _ _ _ _ _._
••• _ _ _..,_______.187

FORCE COMPUTERS

Page v

cpu-sv Technical Reference Manual

Table of Contents

List of Figures
Figure 1.

Figure 2.
Figure 3.
Figure 4.
Figure 5.

Figure 6.
Figure 7.

Figure 8.
Figure 9.

Figure 10.
Figure 11.
Figure 12.

Figure 13.

Page vi

Block Diagram of the SPARC CPU-SV ............................................................................ 3
Diagram of the CPU-SV (Top View) ............................................................................... 10
Diagram of the CPU-SV (Bottom View) ......................................................................... 11
Floppy Interface Via VME P2 Connector ........................................................................ 18
Ethernet Interface via Front Panel ................................................................................... 19
Diagram of the Front Panel .............................................................................................. 32
Pinout of the Ethernet Cable Connector .......................................................................... 35
Serial Ports A and B Connector Pinout ............................................................................ 37
Pinout of SCSI Connector ................................................................................................ 39
KeyboardIMouse Connector ___ ,_' ___ .................................................................................. 40
The IOBP-l 0 .................................................................................................................... 42
Block Diagram of the SPARC CPU-SV .......................................................................... 52
SegIIlents of the Hex Display ........................................................................................... 88

FORCE CO:MPUTERS

SPARC CPU-SV Technical Reference Manual

Introduction

SECTIONl

INTRODUCTION

Getting Started

1.

This SPARe CPU-5V Technical Reference Manual provides a comprehensive guide to the
SPARe CPU-5V board you purchased from FORCE COMPUTERS. In addition, each board
delivered by FORCE includes an Installation Guide.
Please take a moment to examine the Table of Contents of the SPARC CPU-5V Technical
Reference Manual to see how this documentation is structured. This will be of value to you
when looking for infonnation in the future.

1.1

The SPARe CPU-SV Technical Reference Manual Set

When purchased from FORCE, this set includes the SPARC CPU-5V Technical Reference
Manual as well as two additional books. These two books are listed here:
Set of Data Sheets for the SPARC CPU-SV
OPEN BOOT PROM 2.0 MANUAL SET

The Set of Data Sheets for the SPARC CPU-5V contains the following data sheets.
NCR SBus YO Chipset Data Manual

AMD Flash EPROM (AM2SF020)

microSPARC-ll User's Manual (STPI012POA)

Intel Flash Memory (28FOOSSA-L)

SOS-THOMSON MK48T08(B)-10/12115/20

The OPEN BOOT PROM 2.0 MANUAL SET contains the following three sections.
Open Boot 2.0 Quick Reference

FCODE Programs

Open Boot 2.0 Command Reference,

FORCE COMPUTERS

Pagel

Introduction

1.2

SPARC CPU-SV Technical Reference Manual

Summary of the SPARe cpu-sv

The SPARC CPU-5V addresses embedded applications where processing performance is as
important as VMEbus throughput. Based on FORCE COMPUTERS FGA-5000 VMEbus to
SBus interface gate array, the SPARC CPU-5V provides high speed VMEbus transfer
capabilities for standard transfers and extended 64-bit :MBLT transfers. In addition, the SPARC
CPU-5V implements the capabilities of Sun Microsystems' SPARCstation 5 workstation on a
single-slot VMEbus board.
The SPARC CPU-5V is powerd by the microSPARC-II processor, which delivers a sustained
processing performance of 76 SPECint92 and 65 SPECfp92. The complete suite of I/O
functions includes fast SCSI-2, Ethernet, floppy disk, serial 110, Centronics parallel ItO and
keyboard/mouse ports making the SPARC CPU-5V the ideal solution for computing and VME
transfer intensive embedded applications.
A complete 64-bit VMEbus interface and two standard SBus slots enable the expansion of 110
memory and processing performance with a broad range of off-the-shelf solutions. The
software support for the SPARC CPU-SV ranges from Solaris, the most popular
implementation of the UNIX operating system on a RISC architecture, to sophisticated realtime operating systems such as VxWorks.
The SPARC CPU-5V is a single board computer combining workstation performance and
functionality with the ruggedness and expandability of an industry-standard single-slot
6U VMEbus board.

Page 2

FORCE COMPUTERS

Introduction

SPARC CPU-SV Technical Reference Manual

Block Diagram of the SPARe cpu-sv

FIGUREl.

f7

RotaIy

S1aIus

Mouse

Swkh

Display

r-!

r-I

Keyboard!

SCSJ.2

BhemeI

Serial 110
t

I

Reset

Abort

\

\

~

t?

J

l)
16- Of'Sf..Wbyre

~

IMtrtcty &p.nsicn

1~\7I~ \ll

an.m.tSlA

16-0f'~

rl
H
Y
I

NCR89Cf05

NCR89C100.

StllialVO.

at.met SCSI.

~

FIapf:1y.te.y-

c.no-c:s

I~
H~ I
MalrixJ

Boot

Flash IUtnoty

I

SSusSlot

RTCINVFIAN

I

I
I

CJD.boatrI DRAM

I

mit:toSPARC-I1

IUIFPUIIIMUI

Floppy

I

I

16-«~

zMBU-

II
L

seus

I

IJ«nOI'y &p.nsian

I

RahIMmtNy

~

i--

~

I

l

SBusSSot

C«dIe

FGA-SOOO
ditct
S8uH>VAIBU

J

~

I

I

"W

VllEbu:rP2

FORCE COMPUTERS

VlleusP1

Page 3

Introduction

1.3

SPARC CPU-SV Technical Reference Manual

Specifications

Below is a table outlining the specifications of the SPARC CPU-5V board.

Table 1: Specifications of the SPARe cpu-sv
Processor

85 or 110 MHz microSPARc-n
64.0/76 SPECint92
54.6/65 SPECfp92

Page 4

Memory Management Unit

SPARC Reference MMU

Data/lnstruction Cache

8 Kbytel16 Kbyte

Main Memory

16-0r 64-Mbyte base board DRAM,
expandable to 192 MB with mezzanine
modules

SBus Slots

2

SCSI-2 with DMA to SBus

10 Mbyteslsec fast SCSI-2
110 on front panel and P2

Ethernet with DMA to SBus

10 Mbitslsec, AM7990 compatible
AU! port on front panel or P2

Parallel Port with DMA to SBus

3,4 Mbytes/sec
110 on P2 via switch matrix

Floppy Disk Interface

250, 300, 500 Kbyteslsec and 1 Mbytelsec
110 on P2 via switch matrix

Serial 110

2 RS-232 ports, RS-4221485 option via
hybrid modules,
110 on front panel and P2

KeyboardIMouse Port

Sun compatible, on front panel and P2

CountersITtmers

Two 22-bit, SOO ns resolution

Boot Flash Memory

512 Kbyte, on-board programmable
Hardware write protection

User Flash Memory

2 Mbytes, on-board programmable
Hardware write protection

RTCJNVRAM/Battery

M48T08

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

Introduction

Table 1: Specifications of the SPARC CPU-SV (Continued)
VMEbus Interface

64-bit master/slave

Master

A32, A24, A16
064, D32, D16, D8
MBLT,BLT

Slave

A32, A24, A16
D64, D32, D16, D8
MBLT, BLT, UAT

Additional Features

Reset and Abort switches
Status LEDs, HEX display, Rotary switch,
Power-on reset circuitry, Voltage sensor

Firmware

OpenBoot with diagnostics

Power Consumption
(no SBus Modules installed)

+5V
+12V /-12V

Environmental Conditions
Temperature (Operating)
Temperature (Storage)
Humidity

Board Size

FORCE COMPUTERS

5.0 A
0.7/0.2A

Ooc to +550 C
-400 C to +85 0 C
0% to 95% noncondensing

Single-Slot 6U form factor
160.00 x 233.35 nun
6.29 x 9.18 inches

PageS

Introduction

SPARC CPU-5V Technic31 Reference Manual

1.3.1

Ordering Information

This next page contains a list of the product names and their descriptions.

Table 2: Ordering Information
Catalog Name

Product Description

CPU-SV/16-110-2

110 MHz microSPARc-n CPU board with 16-Mbyte base
board DRAM, 2-Mbyte User Flash Memory, SCSI, Ethernet,
floppy disk, parallel and 2 serial I/O ports, 64-bit VMEbus
interface, 2 SBus slots, OpenBoot firmware. Installation guide
included.

CPU-SVI16-85-2

as above, except 85 MHz microSPARC-n.

CPU-SV164-110-2

as above, except 110 MHz microSPARC-ll and 64-Mbyte base I
board DRAM.

CPU-SV/64-85-2

as above, except 85 MHz microSPARC-n.

:MEM-5/16

16-Mbyte mezzanine memory module for use on the SPARC
CPU-sv. Up to two memory modules can be used.

MEM-5/64

64-Mbyte mezzanine memory module for use on the SPARC
CPU-SV. Up to two memory modules can be used.

SBus Modules

SBuslGX

Color 2-D and 3-D wireframe accelerator 1152x900, 8 bits per
pixel, single SBus slot.

SBustrGX

Color 2-D and 3-D wireframe high performance graphics accelerator up to 1152x900, I-Mbyte VRAM, 8 bits per pixel, single
SBus slot.

SBustrGX+

Color 2-D and 3-D wireframe high performance graphics accelerator up to 16OOx1280, 4-Mbyte VRAM, 8 bits per pixel, double buffering, single SB us slot.

SBusIFP

6U front panel for up to 2 SBus cards.

Accessories

Page 6

CPU-SVIfM

Technical Reference Manual Set for CPU-SV including OpenBoot User's Manual and a detailed hardware description.

IOBP-IO

I/O backpanel on VMEbus P2 with flat cable connectors for
Ethernet, SCSL serial I/O and parallel/floppy disk interface for
use with the CPU-SV.

Serial-2CE

Serial adapter cable 26-pin micro D-Sub to 25-pin D-Sub for
use with the cpU-SV.

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

Introduction

Table 2: Ordering Information (Continued)
Catalog Name

Product Description

FHOO3/SET

Hybrid modules for RS-422 serial I/O configuration.

FHOO51SET

Hybrid modules for RS-485 serial I/O configuration.

Software
Solaris 2.xlCPU-5V

Solaris 2.x package with Desktop Right-To-Use license, VMEbus driver on tape. Please contact your local sales representative for current version information.

Solaris 2.xlClient-RTU

Solaris 2.x Desktop Right-To-Use license. Without media
Please contact your local sales representative for current version information.

Solaris 2.xlServer-RTU-up

Solaris 2.x Desktop to Workgroup Server Right-To-Use
upgrade license. Without media Please contact your local sales
representative for current version information.

Solaris 2.xIUM

Solaris 2.x operating system user manual. Please contact your
local sales representative for current version information.

Solaris l.xlCPU-5V

Solaris l.x package with Right-To-Use license, VMEbus driver
on tape. Please contact your local sales representative for current version information.

Solaris I.xlCPU-5V!RTU

Solaris l.x Right-To-Use license. Without media Please contact your local sales representative for current version information.

Solaris l.xlCPU-5VIUU-

Solaris l.x multiuser Right-To-Use license. Without media
Please contact your local sales representative for current version information.

RTU

Solaris I.xIUM

Solaris 1.1 operating system user manual. Please contact your
local sales representative for current version information.

VxWorksIDEV SPARC products

VxWorks development package for SPARC host and target.
Please contact your local sales representative for current version information.

VxWorksIBSP CPU-5V

VxWorks board support package for CPU-5V. Please contact
your local sales representative for current version information.

FORCE COMPUTERS

Page 7

Introduction

1.4

SPARC CPU-SV Technical Reference Manual

ffistory of the Manual

Below is a description of the publication history of this SPARC CPU-5V Technical Reference

Manual.

Table 3: History of Manual

Page 8

Revision No.

Description

Date

1

First Print

April 1995

FORCE COMPUTERS

SPARC CPU-SV

Installation

SECTION 2

INSTALLATION

2.

Introduction

This Installation Section provides guidelines for powering up the SPARC CPU-5V board. The
Installation Section, which you have in your hand now, appears both as Section 2 of the SPARC
CPU-5V Technical Reference Manual and as a stand-alone Installation Guide. This standalone Installation Guide is delivered by FORCE COMPUTERS with every board. The SPARC
CPU-5V Technical Reference Manual provides a comprehensive hardware and software guide
to your board and is intended for those persons who require complete information.

2.1

Caution

Please read this Installation Section before installing the board. Take a moment to examine the
Table of Contents to see how this documentation is structured. This will be of value to you
when looking for specific information in the future.

2.2

Location Diagram of the SPARe CPU-SV Board

A location diagram showing the important components on the top side of the CPU-5V appears
on the next page. On the page next to it, there is a location diagram showing the bottom side of
the CPU-5V. Both of these diagrams show only the components on the board which are of
interest to the user.

FORCE COMPUTERS

Page 9

SPARC CPU-SV

IDstalIation

Diagram of the CPU-SV (Top View)

FIGURE 2.

..:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:
•••••••••••••••••••••••••••••••••
............
-:.:.:
:.:.:.
:.:.:.
.:.:.:
~.~

••••••

~,.

• ••

•:.:.:MicroSPARC.fi ::::::

:.:.:.
••••••

•!.!..

.

.:.:.:
••••••
•........

••••••
••••••
•••••••••••••••••••••••••••••••••
:.:•••••••••••••••••••••••••••••
.••..•••.•.••••.•...•••...•..

••••••
•••
•••

• •••
.......
••••
••••

••••
..--- ••••

_.Y:!:~.. r-~JS9 (Hybrid for Serial Port)

•••••
••••
••••
••••
••••
••••

FGA-5000
FORCE Cdte Arnt!. 5800

••••
••••
••••
••••
••••
••••

Serial Port
AandB

B3t B2, and Bl
are the sockets for
Floppy I Parallel
Switch Matrix

I

SCSI

NCR89CIOS
"SLAVlO"

. ' Ethernet

:.I·

:

••
••
•••

e
"-~~::;;..I

Page 10

••

B11, B12, and B13

-4-.-

I"
BUBllB13

••••
••••
••••

••••
••••
••••
••••
••••
••••
••••
••••

••••
••••
••••

are the sockets for
Ethernet Switch
Matrix

NCR89C100

''MAClO''

•=~

-liiiiiiiiiiiiiiiiiiiiiii'"

••••
••••
••••
••••
••••
••••
••••
••••
••••

••••

y..--.;;;..-.te • • • • •

FORCE COMPUTERS

SPARC CPU-SV

IDstaIlation

FIGURE 3.

Diagram of the CPU-SV (Bottom View)

Switch 8
LCA CoIIfig.
Rc:scnaI
Slot IFIICt.

WriII:User

~

CII3b1cd
PoM:rSeasc
4.514.7SV
RranI:d

00000

ooooe
ooooe

••
SW6

SW8

00000
00000

ooooe

00000
00000

ooooe
ooooe

00000
00000

ooooe
ooooe

00000
00000

Switch 5

0
0
~o~

°coo
00°0
°coo
°coo
°000

0000

••
SWS

SW4

•

SW7

Switch 7
RESETSW
eDabIcd

Switch 4

ABORI'SW
eDabIcd
SYSltESET
1Naab1cd
SYSRESET
our eab1ed

00000

ooooe
ooooe
ooooe

00000

00000
00000

ooooe
ooooe

00000-;

ooooe
ooooe

00000

ooooe
ooooe
00000
ooooe
ooooe
ooooe
00000
ooooe

00000
00000
00000

ooooe
00000
ooooe
ooooe
ooooe
00000
ooooe
ooooe
ooooe
Oooooe
Oooooe

000000
000000

Oooooe
Oooooe
Oooooe
Oooooe

000000
000000
000000
00:1000

FORCE COMPUTERS

Page 11

SPARC CPU-SV

Installation

Before Powering Up

2.3

Before powering up, please make sure that the default switch settings are all set according to
the table below. Check these switch settings before powering up the SPARe CPU-5V because
the board is configured for power up according to these default settings. For the position of the
switches on the board, please see "Diagram of the CPU-5V (Top View)" on page 10.

2.3.1

Default Switch Settings
Table 4: Default Switch Settings

Diagram of Switch
with Default Setting

Switches

Default
Setting

Function

SWITCH 4 (Serial A Configuration)

SWITCH SWS (Controls Serial Channel B)
SWS

SWS-1

ON

SWS-2

OFF

On

=
=
On =crS_B_CONN (Pin 13) to SER_RIXCB and
Pullup to SER_CI'SB
Off =RTXC-.B_CONN (Pin 22) to SER_RTXCB and

SER..TRXCB to TXC_B_CONN (Pin 25)
Off SER_RrS_B to TXC_B_CONN (Pin 25)

On

crs_B_CONN (Pin 13) to ~crsB

Page 12

=
=

SWS-3

OFF

On SER_TRXCB to RTS_B_CONN (Pin 19)
Off SER_RrS_B to RrS_B_CONN (Pin 19)

SW5-4

OFF

RESERVED

FORCE COMPUTERS

SPARe cpu-sv

Installation

Table 4: Default Switch Settings (Continued)
Diagram of Switch
with Default Setting

Switches

Default
Setting

Function

SWITCH 6
SW6
Off 1
Off 2
Off 3

Off 4

SW6-1

OFF

SW6-2

OFF

SW6-3

OFF

SW6-4

OFF

=
=
On =SCSI-Tenn VME P2 disabled
Off =SCSI-Tenn VME P2 enabled
On =Write Boot Flash enabled
Off =Write Boot Flash disabled
On =Write User Flash enabled
Off =Write User Flash disabled

On SCSI-Tenn Front Panel disabled
Off SCSI-Tenn Front Panel automatic

SWITCH 7
SW7-1

ON

On = RESET Switch enabled

=

Off RESET Switch disabled

SW7
l-......IfI!~

2
3

4

SW7-2

On
On
On
On

ON

On = ABORT Switch enabled

Off = ABORI' Switch disabled

=
=

SW7-3

ON

On

SW7-4

ON

On = VME_SYSRESET output enabled (See "VMEbus
SYSRESET &ableJDisable" on page 15)
Off = VME_SYSRESET output disabled

VME_SYSRESET input enabled
Off VME_SYSRESET input disabled

SWITCH 8
SW8-1

OFF

On = LCA Configuration Mode Download

Off = LCA Configuration Mode Serial PROM

SW8
1
2
003

SWS-2

ON

Off = VME Slot 1 Function disabled (See "VMEbus
SYSRESET EnableJDisable" on page 15)

Off

Off

On

SW8-3

OFF

On

=Power Sense 4.SV

Off = Power Sense 4.7SV

4
SWS-4

FORCE CO:MPUTERS

On = VME Slot 1 Function enabled

OFF

Reserved

Page 13

Installation

2.4

SPARC CPU-SV

Powering Up

The initial power up can easily be done by connecting a teoninal to ttya (serial port A). The
advantage of using a teoninal is that no frame buffer, monitor, or keyboard is used for initial
power up, which facilitates a simple start up.
Please see the chapter "OpenBoot Firmware" on page 20 for more detailed information on
booting the system.

2.4.1

Vl.\IJE Slot-l JJevice

The SPARC CPU-5V can be plugged into any VMEbus slot; however, the default
configuration sets the board as a VME slot-l device, which functions as VME system
controller. To configure your CPU-5V in order that it is not a VME slot-1 device, the default
configuration must be changed so that SW8-2 is OFF. In that case, it would also be necessary
to change the SW7-4 to OFF, so that the VME_SYSRESET output is disabled.

CAUTION
Before installing the SPARe CPU-5V in a miniforce chassis, please first disable the VMEbus
System Controller function by setting switch SW8-2 to OFF and also setting SW7-4 to OFF.

Page 14

FORCE COMPUTERS

Installation

SPARC CPU-SV

2.4.2

VMEbus SYSRESET EnableIDisable

2.4.2.1

SYSRESET Input

An external SYSRESET generates an on-board RESET in the default switch setting, i.e., SW73 is ON. When SW7-3 is OFF, the external SYSRESET does not generate an on-board RESET.

2.4.2.2

SYSRESET Output

An on-board RESET drives the SYSRESET signal to the VMEbus to low in the default switch
setting, i.e., SW7-4 is ON. When SW7-4 is OFF, an on-board RESET doesn't drive the
SYSRESET signal to the VMEbus to low.

CAUTION
Do not switch SW7-4 (SYSRESET output) to ON and SW8-2 (VMEbus Slot-1 device) to OFF
at the same time.
The VMEbus Specification requires that if SYSRESET is driven, the SYSRESET signal shall
be driven low for at least 200 IDS. However, when the CPU-5V is not a VMEbus slot-1 device
and the SYSRESET output signal is enabled, then the CPU-5V no longer conforms with this
rule.
By default, the SYSRESET output is enabled. In this case it generates the SYSRESET signal
to the VMEbus.

2.4.3

Serial Ports

By default, both serial ports are configured as RS-232 interfaces. It is also possible to
configure both ports as RS-422 or RS-485 interfaces. This optional configuration is achieved
with the special FORCE Hybrids FH-003 and FH-005.
The chapter ''Default Switch Settings" on page 12 shows the necessary switch settings for
RS-232 operation, where SW4 controls serial port A and SW5 controls serial port B. Please
check that the switches are set accordingly.

FORCE CO:MPUTERS

PagelS

IDstaDation

2.4.4

SPARC CPU-SV

RESET and ABORT Key Enable

To enable the RESET and the ABORT functions on the front panel, set switches SW7-1
(RESET) and SW7-2 (ABORT) to ON.

2.4.5

SCSI Termination

2.4.5.1

SCSI Termination at the Front Panel

Tennination at the front panel for the SCSI interface is automatic when SW6-1 is OFF. This is
the default setting. Automatic means that when a SCSI cable is plugged into the front panel
connector, the tennination is automatically disabled. When there is no SCSI cable plugged into
the front panel, then the tennination is automatically enabled.

2.4.5.2

SCSI TennUmtion atP2

Tennination at the V1v.IEbus P2 for the SCSI interface is enabled when SW6-2 is OFF. This is
the default setting.

CAUTION
When installing the SPARC CPU-5V in a :MICROFORCE chassis, please first disable the
SCSI tennination by switching SW6-1 and SW6-2 to ON.

Page 16

FORCE COMPUTERS

SPARe CPU-SV

2.4.6

Installation

Boot Flash Memory Write Protection

Both of the Boot Flash Memory devices are write protectable via the switch SW6-3. When
SW6-3 is OFF, the devices are write protected.

2.4.7

User Flash Memory Write Protection

The User Flash Memory devices are write protectable via SW6-4. When SW6-4 is OFF, the
User Flash Memory devices are write protected.

2.4.8

Reserved Switches

SW4-4, SW5-4, and SW8-4 are reserved for test purposes.

FORCE COMPUTERS

Page 17

Installation

2.4.9

SPARC CPU-SV

Parallel Port or Floppy Interface via VME P2 Connector

Via a 16-pin configuration switch matrix, it is possible for either the parallel port interface or
the floppy interface to be available on the VME P2 connector.
The default setting enables the floppy interface via the VME P2 connector, with the
configuration switch matrix plugged into Bland B2. This means, of course, that by default the
parallel port interface is not available via the VMEbus P2 connector.
To enable the parallel port interface via the VME P2 connector, plug the configuration switch
_ _ ...! __ ! _ _ _ _ 1._",_

lll(1U.lA. III

'0'" __ .l '0'-'
C11.lU DJ.

~u\';l\.~~ D~

FIGURE 4.

Floppy Interface Via VME P2 Connector

cpu-sv Board

PagelS

FORCE COMPUTERS

Installation

SPARC CPU-SV

2.4.10

Ethernet via Front Panel or VME P2 Connector

Via an 8-pin configuration switch matrix, it is either possible for the Ethernet interface to be
available via the front panel or the VME P2 connector. The default configuration provides the
Ethernet through the front panel connector.
In order to have the Ethernet interface accessible via the VME P2 connector, the default
configuration must be changed.

By default, the Ethernet interface is available through the front panel with the configuration
switch matrix plugged into connectors B12 and B13.
To configure the Ethernet interface to be accessible from the VMEbus P2 connector, the
configuration switch matrix must be plugged into connectors B 11 and B 12.

FIGURES.

Ethernet Interface via Front Panel

BIIB12BI3

Cpu-sv Board

I
WARNING: When the Ethernet interface is configured via VMEbus P2, do not connect
the Ethernet at the front paneL
FORCE COMPUTERS

Page 19

Installation

2.5

SPARe cpu-sv

OpeuBoot Firmware

This chapter describes the use of OpenBoot fIrmware. Specifically, you will read how to
perform the following tasks.
•
•
•

Boot the System
Run Diagnostics
Display System Information

•

Reset the System

•

OpenBoot Help

For detailed information concerning OpenBoot, please see the OPEN BOOT PROM 2.0
MANUAL SET. This manual is included in the SPARC CPU-5V Technical Reference Manual
Set.

2.5.1

Boot the System

The most important function of OpenBoot ftmlware is booting the system. Booting is the
process of loading and executing a stand-alone program such as the operating system. After it
is powered on, the system usually boots automatically after it has passed the Power On Selffest
(POST). This occurs without user intervention.

If necessary, you can explicitly initiate the boot process from the OpenBoot command
interpreter. Automatic booting uses the default boot device specified in non-volatile RAM
(NVRAM); user initiated booting uses either the default boot device or one specified by the
user.
To boot the system from the default boot device, type the following command at the Forth
Monitor prompt.

Iok

boot

or, if you are at the Restricted Monitor Prompt, you have to type the following:

Page 20

FORCE COMPUTERS

SPARe cpu-sv

InstaI1ation

The boot command has the following format:
boot [device-specifier] [ftlename] [-ah]

The optional parameters are described as follows.
[device-specifier]

The name (full path or alias) of the boot device. Typical values
are cdrom, disk, floppy, net or tape.

[filename]

The name of the program to be booted filename is relative to the
root of the selected device. If no filename is specified, the boot
command uses the value of boot-file NVRAM parameter. The
NVRAM parameters used for booting are described in the
following chapter.

[-a]

-a prompt interactively for the device and name of the boot file.

[-h]

-h halt after loading the program.

NOTE: These options

are specific to the operating system and may differ from system to system.

To explicitly boot from the internal disk, type:

Iok

boot disk

or at the Restricted Monitor prompt:

I

>bdisk

FORCE COMPUTERS

Page 21

SPARC CPU-SV

Installation

To retrieve a list of all device alias definitions, type devalias at the Forth Monitor command
prompt. The following table lists some typical device aliases:

Table 5: Device Alias Definitions
AIias

Boot Path

Description

disk

liommu/sbuslespdmalesp/sd@3,0

Default disk (1st internal) SCSI-ID 3

disk3

lionunuisbuslespdmalesp/sd@3,0

First internal disk SCSI-ID 3

disk2

liommuisbuslespdmalespJsd@~O

Additional internal disk SCSI-ID 2

disk 1

liommulsbuslespdmalesp/sd@ 1,0

External disk SCSI-ID 1

diskO

liommuisbuslespdmalesplsd@O,O

External disk SCSI-ID

tape

liommuisbuslespdmalesp/st@4,0

First tape drive SCSI-ID 4

tapeO

liommuisbuslespdmalesp/st@4,0

First tape drive SCSI-ID 4

tape 1

liommuisbuslespdmalesp/st@5,0

Second tape drive SCSI-ID 5

cdrom

liommuisbuslespdma/esplsd@6,O:d

CD-ROM partition d, SCSI-ID 6

net

liommulsbuslledmalle

Ethernet

floppy

lobiolSUNW,fdtwo

Floppy drive

Page 22

°

FORCE COMPUTERS

Installation

SPARC CPU-SV

NVRAM Boot Parameters

2.5.2

The OpenBoot fmnware holds configuration parameters in NVRAM. At the Forth Monitor
prompt, type printenv to see a list of all available configuration parameters. The OpenBoot
command setenv may be used to set these parameters.

setenv [configuration parameter] [value]
This information refers only to those configuration parameters which are involved in the boot
process. The following table lists these parameters.

Table 6: Setting Configuration Parameters
Description

Default Value

Parameter
auto-boot?

true

If true, boot automatically after power on or reset

boot-device

disk

Device from which to boot

boot-file

empty sning

FIle to boot

diag-switch?

false

If true, nm in diagnostic mode

diag-device

net

Device from which to boot in diagnostic mode

diag-file

empty sning

File to boot in diagnostic mode

When booting an operating system or another stand-alone program, and neither a boot device
nor a fllename is supplied, the boot command of the Forth Monitor takes the omitted values
from the NVRAM configuration parameters. If the parameter diag-switch? is false, boot-device
and boot-file are used. Otherwise, the OpenBoot fmnware uses diag-device and diag-flle for
booting.
For a detailed description of all NVRAM configuration parameters, please refer to the OPEN
BOOT PROM 2.0 MANUAL SET.

FORCE COMPUTERS

Page 23

Installation

2.5.3

SPARC CPU-SV

Diagnostics

At power on or after reset, the OpenBoot firmware executes POST. If the NVRAM
configuration parameter diag-switch? is true for each test, a message is displayed on a tenninal
connected to the first serial port. In case the system is not working correctly, error messages
indicating the problem are displayed. After POST, the OpenBoot firmware boots an operating
system or enters the Forth Monitor if the NVRAM configuration parameter auto-boot? is false.
The Forth Monitor includes several diagnostic routines. These on-board tests let you check
devices such as network controller, SCSI devices, floppy disk system, memory, clock and
installed SBus cards. User installed devices can be tested if their ftrmware includes a seiftest
routine.
The table below lists several diagnostic routines.

Page 24

FORCE COMPUTERS

Installation

SPARC CPU-SV

Table 7: Diagnostic Routines
Description

Command

probe-scsi

Identify devices connected to the on-board SCSI bus

probe-scsi-all [device-path]

Perform probe-scsi on all SCSI buses installed in the
system below the specified device tree node. (If
device-path is omitted, the root node is used.)

test device-specifier

Execute the specified device's selftest method. devicespecifier may be a device path name or a device alias.
For example:
test net - test network connection
test Imemory - test number of megabytes specified in
the selftest-#megs NVRAM parameter or test all of
memory if diag-switch? is true

test-all [device-specifier]

Test all devices (that have a built-in selftest method)
below the specified device tree node. (If device-path
is omitted, the root node is used.)

watch-clock

Monitor the clock function

watch-net

Monitor network connection

To check the on-board SCSI bus for connected devices, type:
ok probe-sc:si
Target 3
Unit 0 Disk MICROP 1684-07MB l036511ASOC1684
ok

To test all the SCSI buses installed in the system, type:
ok probe-scsi-all
liommu@O,lOOOOOOO/sbus@O,lOOOl000/esp@2,lOOOOO
Target 6
Unit 0 Disk Removable Read Only Device SONY CD-ROM CDU-8012 3.1a

liommu@O, 1OOOOOOO/sbus@O, 10001 OOO/espdma@4,8400000/esp@4,8800000
Target 3
Unit 0 Disk MICROP 1684-07MB 1036511ASOC1684
ok

The actual response depends on the devices on the SCSI buses.

FORCE COMPUTERS

PagelS

IDstaJlation

SPARC CPU-SV

To test a single installed device, type:

I ok

test device-specifier

This executes the device method name selftest of the specified device node.
device-specifier may be a device path name or a device alias as described in Table 5, ''Device
Alias Defmitions," on page 22.The response depends on the selftest of the device node.

To test a group of installed devices, type:

Iok

test-aD

All devices below the root node of the device tree are tested. The response depends on the
devices that have a selftest routine. If a device specifier option is supplied at the command line,
all devices below the specified device tree node are tested.
When you use the memory testing routine, the system tests the number of megabytes of
memory specified in the NVRAM configuration parameter selfiest-#megs. If the NVRAM
configuration parameter diag-switch? is true, all memory is tested.

:ling

I ok_imemOIy

32 megs of memory at addr 0 TI

The command test-memory is equivalent to testlmemory. In the example above, the frrst number (0)
is the base address of the memory bank to be tested, the second number (27) is the number of
megabytes remaining. If the CPU board is working correctly, the memory is erased and tested
and you will receive the ok prompt. If the PROM or the on-board memory is not working, you
receive one of a number of possible error messages indicating the problem.

To test the clock function, type:
ok watcb-dock
Watching the 'seconds' register of the real time clock chip.
It should be 'ticking' once a second.
Type any key to stop.

22
ok

The system responds by incrementing a number once a second. Press any key to stop the test.

Page 26

FORCE COMPUTERS

SPARC CPU-SV

Installation

To monitor the network connection, type:
ok watch-net
Using AUI Ethernet Interface
Lance register test - succeeded.
lnternalloopback test -- succeeded.
Externalloopback test -- succeeded.
Looking for Ethernet packets.
, .' is a good packet. 'X' is a bad packet.
Type any key to stop.

...........x...........................x..............

ok

The system monitors the network traffic, displaying"." each time it receives a valid packet and
displaying "X" each time it receives a packet with an error that can be detected by the network
hardware interface.

FORCE COMPUTERS

Page 27

Installation

2.5.4

SPARC CPU-SV

Display System Information

The Forth Monitor provides several commands to display system information. These
commands let you display the system banner, the Ethernet address for the Ethernet controller,
the contents of the ID PROM, and the version number of the OpenBoot fIrmware.
The ID PROM contains information specifIc to each individual machine, including the serial
number, date of manufacture, and assigned Ethernet address.
The following table lists these commands.

PagelS

FORCE COMPUTERS

Installation

SPARC CPU-SV

Table 8: Commands to Display System Information
Command

Description

banner

Display system banner.

show-sbus

Display list of installed and probed SBus
devices .

.enet-addr

Display current Ethernet address .

.idprom

Display ID PROM contents, formatted.

.traps

Display a list of SPARC trap types .

.version

Display version and date of the Boot PROM.

show-devs

Display a list of all device tree nodes.

devalias

Display a list of all device aliases.

FORCE COMPUTERS

Page 29

Installation

2.5.5

SPARe cpu-sv

Reset the System

If your system needs to be reset, you either press the reset button on the front panel or, if you
are in the Forth Monitor, type reset on the command line.

I

ok reset

The system immediately begins executing the Power On Selffest (pOST) and initialization
procedures. Once the POST finishes, the system either boots automatically or enters the Forth
IvIonitor, just as it would have done after a power-on cycle.

2.5.6

OpenBoot Help

The Forth Monitor contains an on-line help. To get this, type:
ok help
Enter 'help command-name' or 'help category-name' for more help
(Use ONLY the first word of a category description)
Examples: help select -or- help line
Main categories are:
File download and boot
Resume execution
Diag (diagnostic routines)
Power on reset
>-prompt
Floppy eject
Select YO devices
Ethernet
System and boot configuration parameters
Line editor
Tools (memory~numbers,new commands,loops)
Assembly debugging (breakpoints,registers,disassembly,symbolic)
Sync (synchronize disk data)
Nvramrc (making new commands permanent)

ok

A list of all available help categories is displayed. These categories may also contain
subcategories. To get help for special forth words or subcategories just type help [name]. An
example is shown on the next page.

Page 30

FORCE COMPUTERS

SPARe cpu-sv

Installation

An example of how to get help for special forth words or subcategories:
ok help tools
Category: Tools (memory,numbers,new commands,loops)
Sub-categories are:
Memory access
Arithmetic
Radix (number base conversions)
Numeric output
Defining new commands
Repeated loops
ok
ok help memory
Category: Memory access
dump ( addr length - ) display memory at addr for length bytes
fill ( addr length byte - ) fill memory starting at addr with byte
move ( src dest length - ) copy length bytes from src to dest address
map? ( vaddr -- ) show memory map information for the virtual address
I? ( addr - ) display the 32-bit number from location addr
w? ( addr - ) display the 16-bit number from location addr
c? ( addr - ) display the 8-bit number from location addr
l@ (add! - n ) place on the stack the 32-bit data at location addr
w@ ( addr - n ) place on the stack the 16-bit data at location addr
c@ (addr - n ) place on the stack the 8-bit data at location addr
l! ( n addr -- ) store the 32-bit value n at location addr
w! ( n addr - ) store the 16-bit value n at location addr
c! (n addr - ) store the 8-bit value n at location addr
ok

The on-line help shows you the forth word, the parameter stack before and after execution of
the forth word (before - after), and a short description.
The on-line help of the Forth Monitor is located in the boot PROM, so there is not an online
help for all forth words.

FORCE COMPUTERS

Page 31

IDstaIIation

2.6
FIGURE 6.

SPARe cpu-sv

Front Panel
Diagram of the Front Panel

r=1
t...=:J
@RESET
",." ABORT

[8]!
[@]g
E

mRUNBM

[]Ol

~K

~g
S

E
R

I

A
L
A

+

B

s
c
S
I

E

T
H
E
R
N

E
T

Page 32

FORCE COMPUTERS

Installation

SPARC CPU-SV

2.6.1

Features of the Front Panel

The features listed below are described in detail in Section 3 of the SPARC CPU-5V Technical

Reference Manual.

Table 9: Front Panel Layout
Device

Function

Name

Switch

Reset

RESET

Switch

Abort

ABORT

HEX. Display

Diagnostic

DIAG

Rotary Switch

User defined

MODE

LEDlLED

RUNIHALT
VME BusmasterlSYSFAlL

RUN
BM

LEDILED

Software prognmunable

01

Mini DIN Connector

KeyboardIMouse

KBD

Serial Connector

Serial Interfaces

SERIALA+B

SCSI Connector

SCSI Interface

SCSI

D-Sub Connector

Ethemet

ETHERNET

FORCE COMPUTERS

Page 33

Installation

2.7

SPARC CPU·SV

SPARC CPU-5V Connectors

The connectors on the SPARC CPU-5V are listed in the following table.

Table 10: SPARe CPU-SV Connectors

I
r--- -

~--.----

Serial Pon A + B

---

Manufacturer Part
Number

-AMP
- -- 747&45-4
- - - -- -

'Front Panel

26-pin Fine Pitch

AMP 749831-2

SCSI

Front Panel

5O-pin Fme Pitch

AMP 749831-5

KeyboardIMouse

FrontPaDeI

8-pin MiDi DIN

AMP 749232-1

SBus SI0t2
(SBus Slave Select 1)

P3

96-pinSMD

FUJITSU FCN-234J096-GN

SBusSI0t3
(SBus Slave Select 2)

P4

96-pinSMD

FUJITSU FCN-234J096-GN

VMEbusPl

PI

96-pinVGA

Various

VMEbusP2

P2

96-pinVGA

Various

The following pages show the pinouts of the connectors.

Page 34

FORCE COMPUTERS

SPARe cpu-sv

2.7.1

InstaUation

Ethernet Connector Pinout

The following table is a pinout of the Ethernet connector. The figure below shows the Ethernet
connector and pin numbers.

Table 11: Ethernet Connector Pinout
Pin

FIGURE'.

Function

1

AnalogGND

2

Collision+

3

Transmit Data+

4

AnalogGND

5

Receive Data+

6

AnalogGND

7

N.C.

8

AnalogGND

9

Conision-

10

Transmit Data-

11

AnalogGND

12

Receive Data-

13

+12VDC

14

AnalogGND

15

N.C.

Pinout of the Ethernet Cable Connector

• •••••••

15 • • • • • • • 9

FORCE COMPUTERS

Page 35

SPARe cpu-sv

Installation

2.7.2

Serial Port A and B Connector Pinout

The following table is a pinout of the serial port connector. The figure on the next page shows
the serial port connector and location of the pin numbers.

Table 12: Serial Port A and B Connector Pinout

t

Port
1

none

none

A
- --

Description

Not connected
--

---

2

TD

output

A

Transmit Data

3

RD

input

A

Receive Data

4

RTS

output

A

Request To Send

5

crs

input

A

Clear To Send

6

DSR

input

A

Data Set Ready

7

SG

none

A

Signal Ground

8

DCD

input

A

Data Carrier Detect

9

none

none

Not connected

10

none

none

Not connected

11

SDTR

output

B

Secondary Data Terminal Ready

12

SDCD

input

B

Secondary Data Camer Detect

13

scrs

input

B

Secondary Clear To Send

14

STD

output

B

Secondary Tnmsmit Data

15

TC

input

A

Transmit Clock: DCE source

16

SRD

input

B

Secondary Receive Data

17

RC

input

A

Receive Clock

18

STC

input

B

Secondary Transmit Clock

19

SRTS

output

B

Secondary Request To Send

20

DTR

output

A

Data Terminal Ready

21

SDSR

input

B

Secondary Data Terminal Ready*

22

SRC

input

B

Secondary Receive Clock*

23

SSG

none

B

Secondary Signal Ground

24

TC

output

A

Transmit Clock: DIE source

25

STC

output

B

Transmit Clock: DIE source

Page 36

FORCE COMPUTERS

Installation

SPARC CPU-SV

FIGURES.

Serial Ports A and B Connector Pinout

•••••••••••••

1

26············· 14

FORCE COMPUTERS

Page 37

Installation

2.7.3

SPARC CPU-SV

SCSI Connector Pinout

The following table is a pinout of the SCSI connector. The figure on the next page shows the
SCSI connector and location of the pin numbers.

Table 13: SCSI SO-Pin Connector
Pin No.

Signal

Pin No.

-

_....-

-'"

~~.l~ClLGV

2

GND

27

SCSI Data 1

3

GND

28

SCSI Data 2

4

GND

29

SCSI Data 3

5

GND

30

SCSI Data 4

6

GND

31

SCSI Data 5

7

GND

32

SCSI Data 6

8

GND

33

SCSI Data 7

9

GND

34

SCSIDP

10

GND

35

GND

11

GND

36

DISABLE
TERM

Page 38

12

N.C.

37

N.C.

13

N.C.

38

TERMPWR

14

N.C.

39

N.C.

15

GND

40

GND

16

GND

41

SCSIATN

17

GND

42

GND

18

GND

43

SCSIBSY

19

GND

44

SCSIACK

20

GND

45

SCSIRST

21

GND

46

SCSIMSG

22

GND

47

SCSISEL

23

GND

48

SCSI CD

24

GND

49

SCSlREQ

25

GND

SO

SCSI 10

FORCE COMPUTERS

Installation

SPARC CPU-SV

Pinout of SCSI Connector

FIGURE 9.

••••••••••••••••••••••••• 1

·························26

FORCE COMPUTERS

Page 39

Installation

2.7.4

SPARC CPU-SV

KeyboardIMouse Connector Pinout

The following table is a pinout of the keyboard/mouse connector. The keyboard and mouse
port is available on the front panel via a Mini DIN connector.

Table 14: KeyboardIMouse Connector Pinout

---,,-..

Pin

l?nn.-tinn
....

... A&&

FIGURE 10.

Page 40

1

GND

2

GND

3

+SVDC

4

Mouse In

5

Keyboard Out

6

Keyboard In

7

Mouse Out

8

+SVDC

KeyboardIMouse Connector

FORCE COMPUTERS

Installation

SPARC CPU-SV

2.7.5

VME P2 Connector Pinout

The following table is a pinout of the V1v.IE P2 connector.

Table 15: VME P2 Connector Pinout

PIN

Row A

RowC

RowC

(Floppy drive available via
switch matrix connected
to sockets Bl & B2)

(parallel Port available via
switch matrix connected to
sockets B2 & B3)

1

SCSI Data 0

FLPYDENSEL

CENTRDS

2

SCSI Data 1

FLPY DENSENSE

CENTRDO

3

SCSI Data 2

CENTRDI

CENTRDI

4

SCSI Data 3

FLPYINDEX

CENTRD2

5

SCSI Data 4

FLPYDRVSEL

CENTRD3

6

SCSI Data 5

CENTRD4

CENTRD4

7

SCSI Data 6

CENTRD5

CENTRD5

8

SCSI Dati 7

FLPYMOTEN

CENTRD6

9

SCSIDP

FLPYDIR

CENTRD7

10

GND

FLPYSTEP

CENTRACK

11

GND

FLPYWRDATA

CENTRBSY

12

GND

FLPYWRGATE

CENTRPE

13

TERMPWR

FLPYTRACKO

CENTR~

14

GND

FLPYWRPROT

CENTRINIT

15

GND

FLPYRDDATA

CENTRERR

16

SCSIA1N

FLPY HEADSEL

CENTSLCTIN

17

GND

FLPY DISKCHG

CENTRSLCI'

18

SCSIBSY

FLPYEJECT

N.C.

19

SCSIACK

ETH+12V

ETH+12V

20

SCSIRST

GND

GND

21

SCSIMSG

GND

GND

22

SCSISEL

ETHREC+"')

ETH REC+:l)

23

SCSI CD

ETHREC.:l)

ETH REC·:l) .

24

SCSlREQ

ETHTRA+:lJ

ETHTRA+"'J

25

SCSI 10

ETHTRA.:l)

ETHTRA.:l)

26

Mouse IN

ETHCOL+:l)

ETHCOL+:l)

27

Keyboard OUT

ETHCOL-:l)

ETHCOL-"')

28

Keyboard IN

GND

GND

29

TXDPortA

TXDPortB

TXDPOItB

30

RXDPortA

RXDPortB

RXDPoItB

31

RTSPOItA

RTS PortB

RTS PortB

32

CTSPortA

ers PortB

ers PortB

FORCE COMPUTERS

Page 41

SPARe cpu-sv

Installation

2.7.6

The IOBP-IO Connectors

The 10BP-I 0 is an 110 back panel on VMEbus P2 with flat cable connectors for SCSI, serial
110, Centronics/floppy interface, and a micro D-Sub connector for an Ethernet interface. This
back panel can be plugged into the VMEbus P2 connector. The diagram below shows all the
connectors. This 10BP-IO back panel is especially designed for the SPARC CPU-5V. Do not
use any other 110 back panels on the SPARC CPU-5V, for example, the IOBP-l.

FIGURE 11.

The IOBP·I0

P5

.!!S

P4

P3
1

1

1

1

>

1 ~

11

1

P2
1

1

f49

so

>
)

13

14

AlllID/SERIAL

i§=3
P6

~IO~

33

34

FL£FPY

39

40

CENTRlMCS

SCSI

The pinouts of the connectors (P I) ... (P6) are shown in the following tables.

CAUTION
This 10BP-lO back panel IS especially designed for the SPARC CPU-5V. Do not use any other
110 back panels on the SPARC CPU-5V, for example, the IOBP-I.

Page 42

FORCE COMPUTERS

SPARe cpu·sv

Installation

Table 16: IOBP-I0 PI Pinout
ROW
A

Signal

ROW

B

Signal

ROW
C

Signal for
Floppy
Interface 1

Signal for
Parallel Port
Interface 1

1

SCSI Data 0

1

N.C.

1

FPYDENSEL

CENTRDS

2

SCSI Data 1

2

GND

2

FPYDENSENS

CENTR Data 0

3

SCSI Data 2

3

N.C..

3

N.C.

CENTRData1

4

SCSI Data 3

4

N.C.

4

FPYINDEX

CENTR Data 2

5

SCSI Data 4

5

N.C.

5

FPYDRVSEL

CENTRData3

6

SCSI Data 5

6

N.C.

6

N.C.

CENTRData4

7

SCSI Data 6

7

N.C.

7

N.C.

CENTRData5

8

SCSI Data 7

8

N.C.

8

FPYMOTEN

CENTRData6

9

SCSIDP

9

N.C.

9

FPYDm

CENTRData7

10

GND

10

N.C.

10

FPYSTEP

CENTRACK

11

GND

11

N.C.

11

FPYWRDATA

CENTRBSY

12

GND

12

GND

12

FPYWRGATE

CENTRPE

13

TERMPWR

13

N.C.

13

FPYTRACKO

CENTRAF

14

GND

14

N.C.

14

FPYWRPROT

CENTRINIT

15

GND

15

N.C.

15

FPYRDDATA

CENTRERR

16

SCSIATN

16

N.C.

16

FPYHEADSEL

CENTR SLCf IN

17

GND

17

N.C.

17

FPYDISKCHG

CENTRSLCf

18

SCSIBSY

18

N.C.

18

FPYEJECT

RESERVED

19

SCSIACK

19

N.C.

19

+12VOC 2

+12VDC 2

20

SCSIRST

20

N.C.

20

GND

GND

21

SCSIMSG

21

N.C.

21

GND

GND

22

SCSISEL

22

GND

22

ETHREC+ 2

EfHREC+ 2

23

SCSI CD

23

N.C.

23

ETHREC- 2

EfHREC- 2

24

SCSlREQ

24

N.C.

24

ETHTRA+2

EfHTRA+2

25

SCSI 10

25

N.C.

25

ETHTRA_2

ETHTRA_2

26

Mouse IN

26

N.C.

26

ETHCOL+ 2

ETHCOL+ 2

FORCE CO:MPUTERS

Page 43

Installation

SPARC CPU-SV

Table 16: IOBP-IO PI Pinout (Continued)

I

ROW
A

I

Signal

ROW
B

Signal

ROW
C

Signal for
Floppy
Interface 1

Signal for
Parallel Port
Interface 1

27

Keyboard
Out

27

N.C.

27

EffiCOL-2

ETIICOL_2

28

Keyboard In

28

N.C.

28

GND

GND

29

TxDPortA

29

N.C.

29

TxDPortB

TxDPortB

30

RxDPortA

30

N.C.

30

RxDPortB

RxDPortB

31

RTS PortA

31

GND

31

RTS PortB

RrS PortB

32

CTSPortA

32

N.C.

32

crsPortB

CTSPortB

1) For further information, see ''Floppy Interface Via VME P2 Connector"
2) For further information, please see "Ethernet Interface via Front Pane!"

Page 44

on page 18
on page 19

FORCE COMPUTERS

Installation

SPARCCPU-SV

Table 17: IOBP-IO P2 Pinout (SCSI)
Pin

No.

FORCE COMPUTERS

Signal

Pin

No.

Signal

1

GND

2

SCSI Data 0

3

GND

4

SCSI Data 1

5

GND

6

SCSI Data 2

7

GND

8

SCSI Data 3

9

GND

10

SCSI Data 4

11

GND

12

SCSI Data 5

13

GND

14

SCSI Data 6

15

GND

16

SCSI Data 7

17

GND

18

SCSIDP

19

GND

20

GND

21

GND

22

GND

23

GND

24

GND

25

GND

26

TERMPWR

27

N.C.

28

GND

29

GND

30

GND

31

GND

32

SCSIA1N

33

GND

34

GND

35

GND

36

SCSIBSY

37

GND

38

SCSIACK

39

GND

40

SCSIRST

41

GND

42

SCSIMSG

43

GND

44

SCSISEL

45

GND

46

SCSI CD

47

GND

48

SCSIREQ

49

GND

50

SCSI 10

Page 45

SPARC CPU-SV

Installation

Table 18: IOBP-IO P3 Pinout (Floppy)
Pin

No.

Page 46

Signal

Signal

No.

1

FPYEJECT

2

FPYDENSEL

3

GND

4

FPYDENSENS

5

GND

6

N.C.

7

GND

8

FPYINDEX

9

GND

10

FPYDRVSEL

11

GND

12

N.C.

13

GND

14

N.C.

15

GND

16

FPYMOTEN

17

GND

18

FPYDIR

19

GND

20

FPYSTEP

21

GND

22

FPYWRDATA

23

GND

24

FPYWRGATE

25

GND

26

FPYTRACKO

27

N.C.

28

FPYWRPROT

29

GND

30

FPYRDDATA

31

GND

32

FPYHEADSEL

33

GND

34

FPYDISKCHG

FORCE COMPUTERS

SPARe cpu-sv

Installation

Table 19: IOBP-IO P4 Pinout (Centronics)
Pin
No.

FORCE COMPUTERS

Signal

Pin
No.

Signal

1

CENTRDS

2

GND

3

CENTRDataO

4

GND

5

CENTRDatal

6

GND

7

CENTRData2

8

GND

9

CENTR Data 3

10

GND

11

CENTRData4

12

GND

13

CENTRData5

14

GND

15

CENTRData6

16

GND

17

CENTR Data 7

18

GND

19

CENTRACK

20

GND

21

CENTRBSY

22

GND

23

CENTRPE

24

GND

25

CENTRSLCT

26

CENTRINIT

27

CENTRAF

28

CENTRERR

29

N.C.

30

GND

31

GND

32

N.C.

33

N.C.

34

N.C.

35

N.C.

36

CENTR SLCT IN

37

N.C.

38

N.C.

39

N.C.

40

N.C.

Page 47

SPARe cpu-sv

Installation

Table 20: IOBP-IO P5 Pinout (Serial)
Pin

Pin

Signal

No.

Signal

No.

1

GND

2

Keyboard In

3

Mouse In

4

Keyboard Out

5

TxDPortB

6

TxDPortA

7

RxDPortB

8

RxDPortA

9

RTS PortB

10

RI'S PortA

11

crs PortB

12

crsPortA

13

GND

14

GND

Table 21: IOBP-IO P6 Pinout (Ethernet)
Pin

Page 48

Function

1

GND

2

Collision+

3

Transmit Data+

4

GND

5

Receive Data+

6

GND

7

N.C.

8

N.C.

9

Collision-

10

Transmit Data-

11

GND

12

Receive Data-

13

+ 12VDC

14

GND

15

N.C.
FORCE COMPUTERS

SPARC CPU-SV

2.8

Installation

How to Determine the Ethernet Address and Host ID

This information explains how an Ethernet number and a host ID number are determined on a
CPU-5V board.

The 48-Bit (Six Byte) Ethernet Address
5

Bytes

4

3

2

Iy
47

40

~

39

32

31

24

______+-______~

23f21

o

1

S16

y

15

I
8

7

o

____~--~

Mm~r

FORCE Inc. = 01
FORCE GmbH = 00
The value of these three bytes always

Specific Machine
(HEX)

These two bytes contain the

rightmost four digits of the

remains 008042 (HEX)

board's serial number in its
hexadecimal representation

The Ethernet Address
The Ethernet Address consists of a 48-bit (6-byte) number. The value of the most significant
24 bits is always 008042 (HEX). The value of the least significant 24 bits is calculated as
follows.
The bits 23 and 22 identify whether the product is designed by FORCE COMPUTERS GmbH
or by FORCE COMPUTERS Inc. The value is 00 for GmbH products and the value is 01 for
Inc. products.
The bits 21 through 16 (least significant six bits of the third byte) identify a specific machine.
The value of a CPU-5V board is 11 (decimal). Thus, the value of the most significant 32 bits
(most significant four bytes) of a CPU-5V board from GmbH is 0080420B.
The least significant 16 bits (least significant two bytes) contain the rightmost four digits of
the board's serial number in its hexadecimal representation.
Sample Serial HUmber :

2910 (decimal)

=>

OBSE (hexadectmal)

Sample Ethernet Address: 00 80 42 OS OS SE (hexadecimal)

FORCE COMPUTERS

Page 49

Installation

SPARC CPU-SV

The Host ID Number
The host ID is a 32-bit (4-byte) number and the eight most significant bits identify the
architecture of the machine. The value representing the architecture of CPU-5V is 80 (HEX).
The least significant 24 bits (least significant three bytes) contain the rightmost four digits of
the board's serial number in its hexadecimal representation and the value 8B7000 (HEX) must
be added to the converted serial number.

The Host ID Number

o

2

3

Bytes

~ ~
I
32 •

25

24

~
I

16

7

0

These 8 bits identify architectme type
The least significant 24 bits contain the rightmost
four digits of the board's serial number in its
hexadecimal representation and the value 8B7000

most be added to the converted number.

Sample Serial Bamber: 2910 (decimal)

=->

OBSE (hexadecimal)

80 8B 7000
OBSE

+

Sample Bost :ID:

Page 50

80 8B 7BSE (hexadecimal)

FORCE COMPUTERS

/"

SPARe CPU-SV Technical Reference Manual

SECTION 3

3.

Hardware Description

HARDWARE DESCRIPTION

Overview

Based on FORCE COMPUTERS FGA-5000 VMEbus to SBus interface gate array, the SPARC
CPU-5V provides high speed VMEbus transfer capabilities for standard transfers and extended
64-bit MBLT transfers. In addition, the SPARC CPU-5V implements the capabilities of Sun
Microsystems' SPARCstation 5 workstation on a single-slot VMEbus board.
The SPARC CPU-5V is powered by the microSPARC-II processor, which delivers a sustained
processing performance of 76 SPECint92 and 65 SPECfp92. The complete suite of JJO
functions includes fast SCSI-2, Ethernet, floppy disk, serial I/O, Centronics parallel IlO and
keyboard/mouse ports making the SPARe CPU-5V the ideal solution for computing and VME
transfer intensive embedded applications.
A complete 64-bit VMEbus interface and two standard SBus slots enable the expansion of I/O
memory and processing performance with a broad range of off-the-shelf solutions. The
software support for the SPARC CPU-5V ranges from Solaris, the most popular
implementation of the UNIX operating system on a RISC architecture, to sophisticated realtime operating systems such as VxWorks.
The SPARC CPU-5V is a single board computer combining workstation performance and
functionality with the ruggedness and expandability of an industry-standard single-slot
6U VMEbus board.

3.1

Block Diagram

A block diagram showing a functional overview of the CPU-5V is shown on the next page.

FORCE COMPUTERS

Page 51

SPARC cpu-sv Technical Reference Manual

Hardware Description

Block Diagram of the SPARe cpu-sv

FIGURE 12.

)J

SCSI-2

Ethernet

SeIIaIIfO

..---,

~

RoIary

SIaIus

Mouse

Swtch

Display

.r---1

r-.

I

I

~

\

\

t?

1601'tullbya
"-"Y~

IaVI1 VI

Ett..tSlA

I

I

1601'tullbya

r-1I

NCR I1!JC105

NCRI9C1OD.

s.;.J1iO.

~~

~

I~
~

H=

I

I

I

Fi.ASH ii&iOiff

RASH M9«)RY

y

~

Boot

H211B1br

Floppy. K#y-

c.nInnics
~

RTCINIIRAM

II

SSusSlat

"-"Y~

1601'tu _ _

I
I

0rt«Iard DRAM

mictoSPARC-II

RYFPUIIIMUI

Floppy

I
L

Cat:M

I

SSus

I

Page 52

R-.et

~

-

"U

AboIt

I

SSusSlDt

~

ahd

.....

.5'BuN>o*E64

I

I
~P2

VleusPf

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

3.2

Hardware Description

The microSPARC-TI Processor

The microSPARC-ll CPU chip is at the core of the SPARC CPU-5V. This chip is realized in a
321-pin CPGA package. A Floating Point Unit, an Integer Unit, an MMU, an Instruction
Cache, and a Data Cache are integrated in the microSPARC-ll processor. Please see the
microSPARC-ll User's Manual (STPI012PGA) for further information.

3.2.1

Features of the microSPARC-TI Processor

• microSPARC-ll chip running at 85 MHz and 110 MHz
• Integer Unit with 5-stage pipeline
• Floating Point Unit
• SPARC Reference Memory Management Unit
• A 16 Kbyte instruction cache and an 8 Kbyte data cache, directly mapped
• Memory interface which supports up to 256 Mbyte DRAM
• SBus controller supports up to five SBus slots plus one "master-only" slot

FORCE COl\.fPUTERS

Page 53

Hardware Description

SPARe CPU-SV Technical Reference Manual

Address Mapping for microSPARC·n

3.2.2

The table below lists the physical addresses of the microSPARC-II processor.

Table 22: Physical Memory Map of microSPARC·n
Address

Function

00000000->
OFFFFFFF

User Memory

10000000->
1FfFFFFF

Control Space

20000000->
2FFFFFFF

AFX Frame buffer

SBusSlot#

Select #

SBus Slot 0

30000000->
3FFFFFFF

SBus Slot 1

SBus Slave Select 0

40000000->
4FFFFFFF

SBus Slot 2

SBus Slave Select 1

50000000->
SFFFFFFF

SBus Slot 3

SBus Slave Select 2

60000000->
6FFFFFFF

SBusSlot4

SBus Slave Select 3

70000000->
7FFFFFFF

SBus SlotS

SBus Slave Select 4

Page 54

FORCE COMPUTERS

SPARC CPU-SV Teclmical Reference Manual

3.3

Hardware Description

The Shared Memory

The microSPARC-ll chip interfaces directly to a 64-bit wide DRAM on one side and to the
SBus on the other side. The shared DRAM is 64-bit wide with one parity bit for 32-bit data.
The SPARC CPU-5V provides 16- or 64-Mbyte DRAM which is assembled on the board itself.
There are 4-Mbit devices used to realize 16 Mbytes and there are 16-Mbit devices to realize 64
Mbytes.
The microSPARC-n chip supports up to eight memory banks (bank 0 to bank 7). Two of the
eight memory banks are used on the SPARC CPU-5V base board (bank 0 and bank 1). The
signals for the remaining memory banks are routed to the memory module connectors for
module #1 and module #2.
Memory connector for memory module #1 supports banks 2,3,4 and 5. Memory connector for
memory module #2 supports banks 4, 5, 6 and 7. Memory modules with up to 4 memory banks
can be used. As shown in the table below, the memory bank structure is organized so that
memory modules with a bank count from 1 to 4 (if available) can be used in any combination.
Each module has up to 4 banks, only up to 8 banks in total are allowed. A memory module can
contain bank A, or banks A and B, or banks A, B and C, or bank A, B, C and D.
Table 23: Bank Selection
Base-boani

Bank

Module on Connector #2

Module on Connector #1

Select

from
Processor

Bank A

o

x

BankB

Bank D

Bank A

Bank B

Bank C

Bank D

x

5

x

x

6
7

x

x

The shaded area above shows an example of how the banks are selected by the processor. In
other words, the processor can select Bank B of the module on connector #1 by its own bank
select 3. CAUTION: Do not connect more than one physical memory bank to one bank select
from the processor. In other words, you can connect either bank C of the module on connector
# 1, or bank D of module on connector # 2 to bank select 4, or you can connect either bank D
of the module on connector # 1, or bank C of the module on connector # 2 to bank select 5.

FORCE COMPUTERS

Page 55

Hardware Description

SPARC CPU-SV Technical Reference Manual

The table below shows the base board memory capacity and the memory banks used by the
microSPARC-ll.

Table 24: CPU-SV Memory Banks
CPU-SV
Memory
Capacity

3.4

Memory Banks
oand 1 are Used.

16
- - Mhvte..~
_._-J ---

x

64 Mbytes

x

Memory Module MEM-5

It is possible to upgrade your CPU-5V board with one or two memory modules (the remaining
banks 2 to 7). The memory modules are available in different variants.
The MEM-5 provides 16- or 64-Mbyte DRAM. There are 4-Mbit devices used to realize 16
Mbytes and there are 16-Mbit devices to realize 64 Mbytes.
The table below shows the board memory capacity and the memory banks used on the
microSPARC-ll.
To understand the structure of the memory make sure you read ''The Shared Memory" on
page 55.

Table 25: :MEM-5 Memory Banks
MEM-S
Memory
Capacity

Memory Banks
A and B are Used

16Mbytes

X

64 Mbytes

X

Installing the memory modules is described in the document "How to Install MEM-5."

Page 56

FORCE COMPUTERS

SPARe cpu-sv Teclmica1 Reference Manual

3.5

Hardware Description

SBus Participants

There are two SBus slots located on the component side of the board. SBus Slot # 2 is located
at connector P3 and SBus Slot # 3 is located at connector P4. A diagram of the board is located
in the figure "Diagram of the CPU-5V (Top View)" on page 10.
The microSPARC-ll chip supports up to 5 SBus slots plus an additional "master-only" slot. The
SBus controller is inside the microSPARC-II chip.
The following table shows the microSPARC-II physical address map including all of its SBus
slots and their functions on the SPARC CPU-5V.

3.5.1

Address Mapping for SBus Slots on the SPARC CPU-SV
Table 26: Physical Memory Map of SBns on SPARC CPU-SV
Address

Function

SBusSlot#

Select #

20000000->
2FFFFFFF

AFX Frame buffer

SBusSlotO

30000000->
3FFFFFFF

VMEbus Interface

SBos Slot 1

SBus Slave Select 0

40000000->
4FFFFFFF

SBus Module P3
VMEbus Interface

SBos Slot 2

SBus Slave Select 1

50000000->
SFFFFFFF

SBus Module P4
VMEbus Interface

SBus Slot 3

SBus Slave Select 2

60000000->
6FFFFFFF

VMEbus Interface

SBusSlot4

SBus Slave Select 3

70000000->
77FFFFFF

NCR89CI05 (SLAVIO)
chip

SBusSlot5

SBus Slave Select 4

78000000->
7DFFFFFF

NCR89ClOO (MACIO)
chip

SBos SlotS

SBus Slave Select 4

7EOOOOOO->
7FFFFFFF

VMEbus Interface

SBus Slot 5

SBus Slave Select 4

IT there are no SBus modules installed, SBus Slot 1, 2, 3 and 4, together with SBus Slot 5
address range: 7Eoo 0000-7FFF FFFF, are available for the VMEbus Interface.

FORCE COMPUTERS

PageS'

SPARC CPU-SV Technical Reference Manual

Hardware Description

3.6

NCR89CIOO (MACIO)

The NCR89Cloo is located on SBus Slave Select 4 at physical address $7800 0000. This chip
drives the SCSI, Ethernet and Centronics parallel port.
The NCR89Cl 00 SBus master integrates high performance I/O macrocells and logic including
an Ethernet controller core, a fast 53C9X SCSI core, a high-speed parallel port, a DMA2
controller and an SBus interface.
The Ethernet core is compatible with the industry standard 7990 Ethernet controller. The SCSI
- - - - ! _________ 6 _& 6L_ ':_...1 •• ~.
~urc 1:S C1. :supta~ct. UI
IUU~U'y

we

_.__ ...1 __...1 'lllrr.TI""DCO""nn A •••1...: .....1.. 1.. ....... 1..."' ......... _ ..... A.:~.-A +,.. ..........................
;)U1lIU41.U J.',",,"'-'J,",,7V~ Wl11\...1l 11(0) ~~11 1l1VU111~ I.V ""'ppvn

fast SCSI. The unilbi-directional parallel port is Centronics compliant and can operate in either
programmed I/O or DMA mode.
The DMA2 block comprises the logic used to interface each of these functions to the SBus. It
provides buffering for each of the functions. Buffering takes the form of a 64-byte data cache
and 16-bit wide buffer for the Ethernet channel, and a 64-byte FIFO for both the SCSI channel
and the parallel port. The DMA2 incorporates as improved cache and FIFO draining algorithm
which allows better SBus utilization than previous DMA implementations.

PageS8

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

3.6.1

Hardware Description

Features of the NCR89CI00 on the SPARC CPU-SV

• Fast 8-bit SCSI
• Supports fast SCSI mode
• Backward compatible to 53C90A
• 799O-compatible Ethernet
• Parallel Port
• I/O or DMA programmable modes
• Centrollics compatibility
• LS64854-compatible DMA2 Controller
• Glueless SBus Interface clocked with 21.25 MHz @ 85 MHz processor frequency
• Glueless SBus Interface clocked with 22.00 MHz @ 110 MHz processor frequency
• Concurrently supports:
• 10MB/sec SCSI transfers
• 3.4 :ME/sec Parallel port transfers
• 1.25 :MB/sec Ethernet transfers
• 64-byte FIFO for SCSI and Parallel Port data
• Supports SBus burst modes
• 4-word, 8-word and "nolburst"
• Packaged in 160-pin PQFP
For further information about the NCR891 00, please see NCR SBus YO Chipset Data Manual.

FORCE COMPUTERS

PageS9

Hardware Description

3.6.2

SPARC CPU-SV Technical Reference Manual

SCSI

The SCSI interface provides a standard interface to a wide variety of mass storage devices, such
as hard disks, tapes and CD-ROMs. The SCSI transfers up to 10 Mbytes per second.
The SPARC CPU-5V board's SCSI is realized via the NCR89Cl00. The NCR89ClOO has onchip 48 rnA drivers and therefore provides direct drive of single-ended SCSI bus. The SCSI
core is a superset of the industry standard NCR53C90A which has been modified to support
fast SCSI.
The SCSI interface is single ended and supports "TEID,,1P\VR". The l"~CR89Cl 00 D~. 1A2
.
core
is able to transfer the data to and from the shared main memory.
All signals of the SCSI interface are routed to a standard connector on the front panel and to
the VME P2 connector. This 2nd connection is compatible to the CPU-2CE, CPU-3CE and the
CPU-5CE. Please see the ''VME P2 Connector Pinout" on page 41 where the SCSI signals on
the VME P2 connector are shown.

3.6.3

SCSI Termination

When only one of the SCSI connectors is used, the other one is an end point. In that case, the
SCSI bus must be terminated near the unused connector. This is supported on the CPU-5V
board through one termination at the front panel and one termination at VME P2.
The front panel termination of the SCSI can be configured via the on-board switch SW6-1. If
SW6-1 is ON, the front panel termination is disabled. If SW6-1 is OFF, the termination is
automatic. Automatic means that when a SCSI cable is plugged into the front panel connector,
the termination is automatically disabled. When there is no SCSI cable plugged into the front
panel, the termination is automatically enabled.
The VME P2 termination of the SCSI interface can be enabled or disabled via the switch
SW6-2. If SW6-2 is OFF, the termination is enabled. If SW6-2 is ON, the termination is
disabled.
Please see ''Diagram of the CPU-5V (Top View)" on page 10 for the location of the switches
on the board.

CAUTION
When installing the SPARC CPU-5V in a MICROFORCE chassis, please first disable the SCSI
termination by switching SW6-1 and SW6-2 to ON.
Page 60

FORCE COMPUTERS

r"'"

SPARC CPU-SV Technical Reference Manual

3.6.4

Hardware Description

~theI1let

The NCR89Cl00 DMA controller enables the Ethernet interface to transfer data to and from
the shared main memory. The Ethernet core is register level compatible with the AMD
Am7990, Revision F, standard Ethernet controller, which is capable of transferring Ethernet
data up to 10 Mbitlsec.
An 8-pin configuration switch matrix selects whether the Ethernet interface is available via the
front panel or the VME P2 connector. By default, the Ethernet Interface is available through
the front panel connector with the I/O bridge plugged into connectors B12 and B13.
It is possible to have the Ethernet interface accessible on the VME P2 connector by changing
the default configuration. In order that the Ethernet interface is accessible from the VMEbus
P2 connector, the I/O bridge array must be plugged into connectors B 11 and B 12.
Please see the figure ''Ethernet Interface via Front Panel" on page 19 for information about
changing the Ethernet configuration.

CAUTION
When the Ethernet is configured via P2, do not connect the Ethernet at the front panel.

3.6.5

Parallel Port

The parallel port is centronics compliant and provides unilbi-directional communication. It
operates in either programmed I/O or DMA mode.
The default configuration enables the floppy interface via the VME P2 connector, with the
configuration switch matrix plugged into Bland B2. This means, of course, that by default the
parallel port interface is not available via the VMEbus P2 connector. It is the floppy disk
interface which is available on the VMEbus P2 connector by default.
In order to configure the parallel port to be accessible from the VMEbus P2 connector, the
switch matrix must be plugged into connectors B2 and B3. Please see the figure ''Floppy
Interface Via VME P2 Connector" on page 18 for information about changing the
configuration.

FORCE COrvlPUTERS

Page 61

Hardware Description

3.7

SPARC CPU..SV Technical Reference Manual

NCR89CI05 (SLAVIO)

The NCR89CI05 SBus slave integrates most of the 8-bit system lIO functions including two
dual channel 853O-compatible serial controllers, a high speed 8277AA-l-compatible floppy
disk controller, counter/timers, interrupt controllers, and system reset logic. It also provides an
SBus interface for several other byte-wide peripherals through an external expansion bus.
The primary serial controller is 853O-compatible and can be used as two general purpose serial
ports.
T'ne second serial controller is subset of the 8530 standard and is dedicated for the keyboardi
mouse connection.
The 8277AA-l-compatible floppy disk controller supports up to 1 Mbitlsec data transfer rate.
To reduce part count and system cost, a glueless interface to the SBus is provided. The slave
I/O also includes an 8-bit expansion bus with control to support RTCINVRAM, EPROM and
generic 8-bit devices externally.

3.7.1

Features of the NCR89CI05 on the SPARC CPU-SV

• Dual-channel serial ports (8530-compatible)
• Keyboard! mouse port
• 82077AA-l floppy disk controller
• 8-bit expansion bus for Flash MemoryfI'ODINVRAM
• Glueless SBus interface clocked with 21.25 MHz @ 85 MHz and 22.0 MHz
processor frequency

@

110 MHz

• Interrupt controller
• System reset control
• Programmable 22-bit counters & timers

• Auxiliary I/O registers
• Packaged in 160-pin PQFP
For further information about the NCR891 00, please refer to the NCR SBus I/O Chipset Data
Manual.

Page 62

FORCE COMPUTERS

SPARC CPU-SV Teclmical Reference Manual

3.7.2

Hardware Description

Address Map of Local 110 Devices on SPARe cpu-sv

The following table lists the physical addresses for all local I/O devices and the accesses
permitted «(B)yte, (H)alfWord and (W)ord).

Table 27: NCR89CI05 Chip Address Map
Physical
Address

Device

Access

70000000->
70FFFFFF

Boot Flash Memory and User Flash Memory

B,H,W

71000000->
711FFFFF

Keyboard. Moose, and Serial Ports

B

71000000
71000002
71000004
71000006
71100000
71100002
71100004
71100006

Mouse Control Port
Mouse Data Port
Keyboard Control Port
Keyboard Data Port
1TYB Control Port
1TYB Data Port
TIYA Control Port
TIYA DATA Port

71200000->
712FFFFF

RTCINVRAM

B,H,W

71300000 ->
7137FFFF

Boot Flash Memory and User Flash Memory Programming

B

71380000->
713FFFFF

Additional Registers

B

71400000->
714FFFFF

Floppy Controller

B

71400002
71400004
71400004
71400005
71400006
71400007
71400007

Digital Output Register (DOR)
Main Status Register (MSR, Read Only)
Datarate Select Register (DSR, Write Only)
FIFO

Reserved (Test mode select)
Digital Input Register (DIR, Read Only)
Configuration Control Register (CCR, Write Only)

71500000->
71700000

Reserved

71800000

89CI05 Configuration Register

B

71900000->
719FFFFF

Auxiliary 110 Registers

B

71900000

Aux 1 Register (Miscellaneous System Functions)

71910000

Aux 2 Register (Software Powerdown Control)

FORCE COMPUTERS

I
Page 63

SPARC CPU-SV Technical Reference Manual

Hardware Description

Serial VO Ports

3.7.3

The two serial I/O ports are available on the front panel via one 26-pin shielded connector.
Both of the two ports are available via the VMEbus P2 connector, each with four signals (RXD,
TXD, RTS, CTS). Each of the two serial 110 ports are independent full-duplex ports.
The 8530 sec block is functionally compatible with the standard NMOS 8530 and therefore
provides two fully independent full-duplex ports.
~-

-

-y----. - - ,

- --1--1 _ _ _ _ _ _ _ .1: __ ...L

Ine pnYSlca1 auurcss map

lUI

___ --=_1 __ ~_ ! _ _ L _ _ _ !_ """-TI""InOn",1I\C r"L.':_ A .J.J_ ................. _"
PUIl~ I~ ~llUWll III
l""\"'''''O:7"\'''~V.J "\"'lllp rl.UUl~~i) J.uap

we

scum

on page 63.

3.7.4

RS-232, RS-422 or RS-485 Configuration

Both serial ports can be configured as RS-232, RS-422 or RS-485. By default, the FH-002
hybrid module is installed for RS-232 operation.
In order to simplify changing the serial interfaces, FORCE COMPUTERS has developed
RS-232, RS-422 and RS-485 hybrid modules: the FH-002, FH-003 and FH-005. These 21-pin
sa modules are installed in sockets so that they may be easily changed to meet specific
application needs.
To change the configuration of serial port A, insert the respective hybrid in socket J59. To
change the configuration of serial port B, insert the respective hybrid in socket J60. For the
position of the sockets on the board, please see "Diagram. of the CPU-5V (Top View)" on
.
page 10.

Table 28: RS-232, RS-422 or RS-485 Configuration
Hybrid

Configuration

Socket for
Serial Port A

Socket for
Serial Port B

Default

FH-002

RS-232

J59

J60

*

FH-003

RS-422

J59

J60

FH-005

RS-485

J59

J60

Page 64

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

3.7.5

Hardware Description

RS-232 Hardware Configuration

The serial ports A and B are configured by default for RS-232 operation. The following
individual I/O signals are available for serial ports A and B on the front panel connector.

Table 29: Serial Ports A and B Pinout List (RS-232)
Transmitted Signals

Received Signals

TXD-Transmit Data

3

RXD-Receive Data

RTS-Request to Send

5

crS-Clear to Send

Ground

6

SYNC

DTR-Data Terminal Ready

8

DCD-Data Carrier Detect

TRXC-D1E Transmit Clock

15

TRXD-DCE Transmit Clock

17

RTXC-DCE Receive Clock

The pinout for serial port A is shown in the white area and the pinout for serial port B is shown
in the grey area.
The table below shows the switch settings for each port.

Table 30: Switch Settings for Ports A and B (RS-232)
PortA

PortB

Default

SW4-1

SW5-1

ON

TRXC is available on front panel connectors, pin 24

SW4-3

SW5-3

OFF

RTS is available on front panel connectors, pin 4

SW4-2

SW5-2

OFF

CTS is available on front panel connectors, pin 5

Function for RS-232

Please see the "Diagram of the CPU-5V (Bottom View)" on page 11 for the location of the
switches on the board.

FORCE COMPUTERS

Page 65

Hardware Description

3.7.6

SPARe CPU-SV Technical Reference Manual

RS·422 Hardware Configuration

It is possible to reconfigure serial ports A and B for RS-422 operation. In order to configure the
serial ports to RS-422, the hybrid module FH-003 must be used. Termination resistors can be

installed to adapt various cable lengths and reduce reflections.

Table 31: Serial Ports A and B Pinout List (RS-422)
Transmitted Signals

Pin

Received Signals

TXD+ Transmit Data

20

RXD+ Receive Data

TXD- Transmit Data

7

RXD- Receive Data

RTS+ Request to Send

2*

CTS+ Clear to Send

RTS- Request to Send

5*

crs- Clear to Send

1RXC+ Transmit Clock

2*

RTXC+ Receive Clock

1RXC- Transmit Clock

5*

RTXC- Receive Clock

The pinout for serial port A is shown in the white area and the pinout for serial port B is shown
in the grey area.

* Signals RTS and TRXC can be switched so that they are available on connector pins 3 and 4

(16, 19). Signals ers and RTXC can also be switched so that they are available on connector
pins 2 and 5 (14,93). This is done by switch SW4 for port A and by switch SW5 for port B.
The table on the next page shows the corresponding switch settings.

Page 66

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

Hardware Description

Table 32: Switch Settings for Ports A and B (RS-422)
PortA

PortB

Configuration

SW4-1

SW5-1

ON

ON for RS-422

SW4-3

SW5-3

ON

TRXC +/- on front panel connectors, pins 3/16
and 4119 available

SW4-3

SW5-3

OFF

RTS +/- on front panel connectors, pins 3/16 and
4119 available

SW4-2

SW5-2

OFF

crs +/-

Function for RS-422

on front panel connectors, pins 2114 and

5113 available
SW4-2

SW5-2

ON

RTXC +/- on front panel connectors, pins 2114
and 5/13 available

Please see the ''Diagram of the CPU-5V (Bottom View)" on page 11 for the location of the
switches on the board.

FORCE COMPUTERS

Page 67

Hardware Description

3.7.7

SPARC CPU-SV Technical Reference Manual

RS-4S5 Hardware Configuration

It is possible to reconfigure serial ports A and B to be RS-48S compatible by using the hybrid
module FH-OOS.
The following I/O signals are available on the front panel connectors of both serial ports.

Table 33: Serial Ports A and B Pinout List (RS-4S5)
Signais
7

20

RXTX+ Receivelfransmit Data
RXTX- Receivelfransmit Data

The pinout for serial port A is shown in the white area and the pinout for serial port B is shown
in the grey area.
The Receive-Enable (REN) and Transmit-Enable (TEN) of the hybrid module PH-OOS are
controlled via the NCR89CI0S serial I/O signals DTR (REN) and RTS(TEN).
The following table shows the corresponding switch settings

Table 34: Switch Settings for Ports A and B (RS-485)
PortA

PortB

Configuration

Function for RS-485

SW4-1

SW5-1

OFF

RTS functions as TEN

SW4-3

SWS-3

OFF

No function for RS-485

SW4-2

SW5-2

OFF

No function for RS-485

Please see the "Diagram of the CPU-SV (Bottom View)" on page 11 for the location of the
switches on the board.

Page 68

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

3.7.8

Hardware Description

Keyboard and Mouse Port

The keyboard and mouse port is available on the front panel via an 8-pin mini DIN connector
and on VME P2.
The serial port controller used for the keyboard and mouse port is compatible with the NMOS
8530 controller.
The pinout of the keyboard and mouse port is described in Section 2, Installation.
The physical address for the keyboard and mouse port is shown in ''NCR89C 105 Chip Address
Map" on page 63.

3.7.9

Floppy Disk Interface

The floppy disk interface is available on the P2 connector by default, with the configuration
switch matrix plugged into Bland B2. The floppy disk configuration is described in the
chapter ''Parallel Port or Floppy Interface via VME P2 Connector" on page 18.
The floppy disk interface is 82077AA-l compatible. It is able to transfer data rates of 250, 300,
500 Kbytes/sec, and 1 Mbyte/sec.
The floppy disk controller block is functionally compatible with the Intel 82077AA-1. It
integrates drivers, receivers, data separator, and a 16-byte bidirectional FIFO. The floppy disk
controller supports all standard disk formats (typically 720 K and 1.44 M floppies). It is also
compatible with the 2.88 MB floppy format

FORCE COMPUTERS

Page 69

Hardware Description

3.7.10

SPARe CPU-SV Technical Reference Manual

8·Bit Local 110 Devices

The following local I/O devices are interfaced via the NCR89C 105

Table 35: 8·Bit Local 110 Devices
Function
u"""~ R

$7003FFFF

Boot Flash Memory
Device#2
256 Kbyte (default)

No

$7004 0000 ->
$7007FFFF

User Flash Memory
1 Mbyte Device # 1

No

$7010 0000 ->
S701FFFFF

User Flash Memory
1 Mbyte Device # 2

No

$70200000->
$702FFFFF

RTCJNVRAM

No

$7120 0000 ->
$712FFFFF

F1asb Memory Programming Area

No

$71300000->
$7137FFFF

Additional Registers

No

$7138 0000 ->
$713FFFFF

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

3.7.11

Hardware Description

Boot Flash Memory

The boot flash memory consists of two 2-Mbit or 4-Mbit flash memory devices. In the default
configuration, there are two 2-Mbit devices installed. The 4-Mbit devices are an additional
assembly option.
The boot flash memory devices can be reprogrammed on-board and can also be write protected
via hardware switch SW6-3.
When SW6-3 is ON, write accesses are possible. The devices are write protected when SW6-3
is OFF.
The boot flash memory devices are installed in sockets at location J26 (device #1) and J22
(device #2). This pennits programming them in a standard programmer. This may be necessary
if the power fails during reprogramming. In this case, the contents of the Boot Flash Memory
would be lost and the board would not be able to boot.

Table 36: Boot Flash Memory Capacity
Devices

Count

Capacity

Default

256 K * 8

2

512 Kbyte

X

512 K* 8

2

1 Mbyte

The on-board programming of the boot flash memory devices requires setting some bits in the
Flash Memory Programming Voltage Control Register and Flash Memory Programming
Control Register 1 and 2. These registers are shown on the following pages.

FORCE COMPUTERS

Page 71

SPARe CPU-SV Technical Reference Manual

Hardware Description

3.7.12

User Flash Memory

The user flash memory area consists of a maximum of two 8-Mbit flash memory devices,
providing a capacity of 2 Mbytes. The capacity of user flash memory is outlined in the product
nomenclature, which can be seen in the table "Ordering Infonnation" on page 6.
This area can be used to store ROMabie operating systems as well as application specific code.

Table 37: User Flash Memory Capacity
Devices

Count

Capacity

IM*8

2

2Mbyte

The user flash memory devices can be reprogrammed on-board and can also be write protected
via hardware switch SW6-4. When SW6-4 is ON, write accesses are possible. When SW6-4 is
OFF, the devices are write protected.
The on-board programming of the user flash memory devices requires setting some bits in the
Flash Memory Programming Voltage Control Register and Flash Memory Programming
Control Register 1 and 2. These registers are shown on the following pages.

Page 72

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

3.7.13

Hardware Description

Programming the On-board Flash Memories

Both areas of flash memories, the Boot area and the User area, can be reprogrammed on-board.
Please see "Flash Memory Support" on page 162 for details about programming the on-board
memories.
The address range in which the flash memory devices can be programmed is located in a 512
Kbyte page (programming window) of the Generic Port area of the NCR89CI05 (SLAVIO).
The physical address range is $71300000 .. $7137 FFFF.
Please note the following steps for programming the on-board flash memory devices.
• Disable hardware write protection in order to program the flash memory devices. The
switch SW6-3 must be ON in order to program the boot flash memory and the switch SW64 must be ON in order to program the user flash memory. For the location of the switches
on the board please see ''Diagram of the CPU-5V (Bottom View)" on page 11.
• Switch the programming voltage ON by setting the appropriate bit
• Set address lines A[21: 19] to the requested address range. Set the device number of the
device to be selected.
• Select either the user flash memory or the boot flash memory for programming.
• After the flash memory devices have been programmed, we recommend that you return to
the default settings of SW6-3 and SW6-4. This protects the flash memory devices from
being programmed by accident

In order to enable programming and to decide which area is to be mapped to the programming
window, the following six bits VPP_ON, A[21:19], SEL_ROM and SEL_BOOT are used to
control this.

FORCE CO:MPUTERS

Page 73

Hardware Description

3.7.13.1

SPARC CPU-SV Technical Reference Manual

Flash Memory Programming Voltage Control Register

To enable the programming of the flash memory devices, the + 12V programming voltage must
be switched ON. This is done by setting bit VPP ON in the Flash Memory Programming
Voltage Control Register.

InitiaUzation: VPP ON is cleared on reset. This inhibits the programming of the flash memory
devices.

Physical Address: 7138 OOOA16
7

6

5

4

3

2

i

1

1

1

1

1

1

1

o
vpp
ON

VPP_ON (RW) This bit is used to turn the +12V programming voltage for all flash memories
on or off. When the bit is set (1) then the programming voltage is turned on; and the
programming voltage is turned off by clearing (0) this bit.

Page 74

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

3.7.13.2

Hardware Description

Flash Memory Programming Control Register 1
Physical Address: 7138 000216
7

6

5

4

321

o

1

1

1

1

A[21:19]

SEL
ROM

A[21 : 19] (RW) The outputs of these three register bits are directly connected with the address
pins A21, A20, and A19 of both USER flash memories which allows to address flash
memories with up to 4 Mbyte size.
Because the flash memories are accessible only in the physical range 7130.0000 16 to
7137.FFFF I6, software has to modify these bits to make a specific 512 Kbyte page
available in this address range.

A[21:19]

Page

0002

0

00.000016 •.. 07.FFFF16

001 2

1

0102

2

08.000016 ... 0F.FFFF16
10.000016 .•. 17.FFFF16

011 2

3

18.000016 ... 1F.FFFF16

1002
101 2

4

20.000016 ... 27.FFFF16
28.000016 •.. 2F.FFFF16

1102
1112

5
6
7

Accessible Area of Flash Memory (offset)

30.000016 ···37.FFFF16
38.000016 ... 3F.FFFF16

SEL_ROM (RW) This bit and the SEL_BOOT bit in the Flash Memory Programming Control Register 2 are used to select one of four flash memory devices to be accessible in
the physical address range 7130.000016 to 7137.FFFFI6 .

FORCE COMPUTERS

Page7S

Hardware Description

3.7.13.3

SPARe CPU-SV Technical Reference Manual

Flash Memory Programming Control Register 2
Physical Address: 7138 000916
7

6

5

4

3

2

1

1

1

1

1

1

1

0

SEL_BOOT (RW) This bit and the SEL_ROM bit in the Flash Memory Programming Control Register 1 are used to select one of four :flash memories to be accessible in the
physical address range 7130.0000 16 to 7137.FFFF I6 . The following table shows all
possible configurations:

SEL_BOOT

0

1

0

first USER flash memory
device accessible

first BOOT flash memory
device accessible

1

second USER flash mem- second BOOT flash memory device accessible
ory device accessible

SEL_ROM

Page 76

FORCE COMPUTERS

SPARe CPU-SV Technical Reference Manual

3.7.14

Hardware Description

RTCINVRAM

The MK48T08 combines an 8 K x 8 full CMOS SRAM, a bytewide accessible Real Time
Clock, a crystal, and a long-life lithium carbon monofluoride battery, all in a single plastic DIP
package. The MK48T08 is a nonvolatile pin and functionally equivalent to any Jedec standard
8Kx8SRAM
For a detailed description of the RTCINVRAM, please see the respective Data Sheet.

FORCE COMPUTERS

Page 77

Hardware Description

3.8

SPARe CPU-SV Technical Reference Manual

VMEbus Interface

The CPU-5V utilizes the FGA-5000 chip to provide fully SBus and VMEbus compliant
interfaces. Supported functions include master and slave data transfer capabilities, VMEbus
interrupt handling and arbitration functions. Additional VMEbus utility functions and a special
loop-back cycle for stand-alone testing of the interface are provided.

Features of the FGA-5000
• VMEbus Master Interface
• VMEbus Slave Interface
• DMA Controller
• Interrupts
• VMEbus Arbiter
• FORCE Message Broadcast
• Mailboxes and Semaphores
• Reset Functions
• System Controller Functions
• Timers
A complete description of the FGA-5000 chip is found in the FGA-5000 Technical Reference
Manual, available from FORCE COMPUTERS.

Page7S

FORCE COMPUTERS

Hardware Description

SPARC CPU-SV Technical Reference Manual

3.8.1

Address Mapping for the VMEbus Interface FGA-5000

The table below lists the physical addresses of the VMEbus interface FGA-5000.

Table 38: Physical Memory Map of VMEbus Interface on SPARe cpu-sv
Address

Function

SBusSlot#

Select #

30000000->
3FFFFFFF

VMEbus Interface

SBusSlot 1

SBus Slave Select 0

40000000->
4FFFFFFF

VMEbus Interface
(SBos Module)

SBusSlot2

SBus Slave Select 1

50000000->
SFFFFFFF

VMEbus Interface
(SBus Module)

SBusSlot3

SBus Slave Select 2

60000000->
6FFFFFFF

VMEbus Interface

SBus Slot 4

SBus Slave Select 3

7EOOOOOO->
7FFFFFFF

VMEbus Interface

SBusSlot5

SBus Slave Select 4
(SB_SEL<5>)

The FGA-5000 can be selected with up to six SBus select input signals SSEL<5_.O>. The
microSPARC-ll CPU chip supports only 5 select signals SLVSEL<4..0>. The remaining select
signal of the FGA-5000 can be used to expand the VMEbus address area.
The I/O chips NCR89ClOO (MACIO) and NCR89CI05 (SLAVIO) are selected in SBus Slot 5
by SBus Slave Select 4. The upper part in this range is not used by these chips. So we decided
to split the SBus Slave Select 4 into two signals: SB_SEL<4> and SB_SEL<5>. Now the I/O
chips are selected by SB_SEL<4> and the VMEbus interface FGA-5000 is selected by
SB_SEL<5>. With this expansion, the VMEbus interface FGA-5000 shares SBus Slot 5 with
the I/O chips and can use an additional address range of up to 32 Mbyte in this SBus Slot.
On the base board, SBus Slot 2 (SBus Slave Select 1) and SBus Slot 3 (SBus Slave Select 2)
are provided for SBus modules. When no SBus modules are installed, you can use these SBus
slots to expand the VMEbus address range again. In this case, you gain 256 Mbyte with every
additional SBus Slot.
When using all address range resources for the VMEbus interface the microSPARC-ll CPU can
access the VMEbus interface FGA-5000, internal registers and VMEbus slaves, in an address
area of 1056 Mbyte (1 GByte + 32 Mbyte).

FORCE COMPUTERS

Page 79

SPARe CPU-SV Technical Reference Manual

Hardware Description

3.8.2

Adaptation of the FGA-SOOO

Some aspects of the VMEbus interface chip FGA-5000 require a small amount of glue logic be
built around this chip in order to use the chip on this base board.
In the case where the FGA-5000 is not VMEbus master, the VMEbus input signal BERR has
not been directly routed to the FGA-5000. This masking is required for nonnal VMEbus
transfers. However, during Fl\m transfers the VMEbus slave should see the input signal
BERR.
~TL

__ ...L _

~,....

A

~1'\nF\

VV Den we ru.ft.-JUVV

~

_____

~

_______ 1 __ 1 __ ... _.-1 _1 _____ .-1 __ --! _ _ _ _ T:"II. """""

____ 1 _ _ _ .-1 _ _ _ _ _ _ _ _ _

1:S um:: VI :sevenu :seu:;\,;u:;u :Slave:s uWlug all rlVlD \,;Y\,;le,

i1UU

vue VI wVle

of the other slaves acknowledges the transfer with Bus Error, then the FGA-5000 doesn't
recognize that the message is invalid. In order to enable the software to discard this invalid
message, additional registers have been implemented in a separate programmable device on the
base board.
How to access and interpret the contents of the added registers can be found in the chapter
"Additional Registers" on page 90.
For information about the Fl\m implementation in the FGA-5000 chip, please refer to the
FGA-5000 Technical Reference Manual.

Page 80

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

3.8.3

VMEbus SYSRESET EnableIDisable

3.8.3.1

SYSRESET Input

Hardware Description

An external SYSRESET generates an on-board RESET in the default switch setting, i.e.,
SW7-3 is ON. When SW7-3 is OFF, the external SYSRESET does not generate an on-board
RESET.

3.8.3.2

SYSRESET Output

An on-board RESET drives the SYSRESET signal to the VMEbus to low in the default
switch setting, i.e., SW7-4 is ON. When SW7-4 is OFF, an on-board RESET doesn't drive the
SYSRESET signal to the V1\1Ebus to low.

CAUTION
Do not switch SW7-4 (SYSRESET output) to ON and SW8-2 (VMEbus Slot-1 device) to
OFF at the same time.
The VMEbus Specification requires that if SYSRESET is driven, the SYSRESET signal shall
be driven low for at least 200 IDS. However, when the CPU-5V is not a VMEbus Slot-1 device
and the SYSRESET output signal is enabled, then the CPU-5V no longer conforms with this
rule.

By default, the SYSRESET output is enabled. In this case it generates the SYSRESET signal
to the VMEbus.

FORCE COMPUTERS

PageS!

Hardware Description

3.9

SPARC CPU-SV Technical Reference Manual

On-board Control Registers (System Configuration)

The following table shows the physical address of the registers used for system configuration.
The registers are described in their respective functional chapters, for example, the USER
LEDs are described in the chapter "Front Panel Status LEDs" on page 85.

Address

I

Reset

I Size IDeSCription

nnnn
• •"''''·''''''''''''16

~~ue
• "'i6

7138.0001 16

F016

8 bit USER LED 2 Control Register

7138.0002 16

F016

8 bit Flash Memory Programming Control Register 1

7138.000316

8 bit Rotary Switch Status Register

7138.000716

FX16
XX16
XX16
XX16
XX16

7138.000816

FE16

8 bit Boot ROM Size Control Register

7138.0009 16

FE 16

8 bit Flash Memory Programming Control Register 2

7138.000A16

FE 16

8 bit Flash Memory Programming Voltage Control
Register

7138.000B16

XX16

8 bit Seven- Segment LED Display Control Register

7138.000C 16

FE 16

8 bit FMB Channel 0 Data Discard Status Register

7138.000016

FE 16

8 bit FMB Channel 1 Data Discard Status Register

7138.000E16

XX16

8 bit reserved

7138.000F16

FX16

8 bit LCA Identification Register

71~Q

7138.000416
7138.000516
7138.000616

Page 82

......

A ha

'"

I~-=:D

1_ _ _ I

1 -=:n 1• ('
.............
'"'VI
111.1 ",.1 D",,,;"',,,r
I

I ___

'v~I~"vl

8 bit Reserved
8 bit Reserved
8 bit Reserved
8 bit Reserved

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

3.10

Hardware Description

Front Panel

The Reset and Abort functions, the Hex display, the Rotary switch, and the LEDs are described
on the following pages. The pinouts for the connectors shown in grey below are described in
Section 2, Installation.

Table 39: Front Panel Layout
Device

Function

Name

Switch

Reset

RESET

Switch

Abort

ABORT

HEX. Display

Diagnostic

DIAG

Rotary Switch

User defined

MODE

LEDILED

RUNIHALT

VME BusmasterJSYSFAIL

RUN
BM

Software programmable

01

LEDILED

FORCE COMPUTERS

Page 83

Hardware Description

3.10.1

SPARC CPU-SV Technical Reference Manual

RESET and ABORT Keys

The front panel on the SPARC CPU-5V has two mechanical switches which directly influence
the system..

3.10.1.1

The RESET Key

The RESET key enables the user to reset the whole board. If the board is VMEbus system
controller (Slot-l device), the SYSRESET signal of the VMEbus also becomes active with the
RESET key. This resets the complete VMEbus system. The switch SW7-4 can be used to
disable driving the vlvlEbus SYSRESET signal (see ~~v"MEbus SYSRESET Enable/Disable"
on page 81). With on-board switch SW7-1, it is possible to deactivate the RESET key. When
SW7-1 is ON, the RESET key works and when SW7-1 is OFF, toggling the RESET key has no
effect.
Please see also "VMEbus SYSRESET EnablelDisable" on page 81.

3.10.1.2

The ABORT Key

The ABORT key on the front panel can be used to generate a nonmaskab1e interrupt (level 15).
The ABORT key function is controlled by switch SW7-2. When SW7-2 is ON, the key works
and when SW7-2 is OFF, toggling the ABORT key has no effect. If the ABORT key produces
a nonmaskable interrupt, the pending signal can be read in the Miscellaneous Control and
Status Register 0 (MCSRO register). The ABORT Interrupt Request Mapping Register
(ABORT_IR is inactive for more than
0,5s in order to signal a hang up. In all other cases, this LED is green.
The BM LED reflects all VMEbus master activities on the CPU-5V. When the board accesses
the VMEbus, the BM LED lights up green. The BM LED turns red when the CPU-5V is
asserting SYSFAll... to the V1vffibus.
There are 2 additional STATUS LEDs, which are freely programmable LEDs controlled by
accessing registers in the LCA.

FORCE COMPUTERS

Page 85

SPARC CPU-SV Technical Reference Manual

Hardware Description

3.10.2.1

USER LED 1 Control Register
Physical Address 7138 000016
7

6

5

4

1

1

1

1

3

2

o

1

COLOUR

COLOUR (RW) These two bits are used to tum the first USER LED on or off, and to control

the colour of the LED. The table below lists all possible values:
COLOUR

Colour of the first USER LED (LED #0)

002

USER LED is tumed off

01 2
102
112

USER LED is tumed on and shines green
USER LED is tumed on and shines red
USER LED is tumed on and shines yellow

BLINK_FREQ (RW) These two bits control the frequency at which the first USER LED is
blinking. The table below lists all possible values and the corresponding blink fre-

quency:
BLINK_FREQ

PageS6

fblink of the first USER LED (LED #0)

002
01 2

USER LED is not blinking

1°2
112

USER LED is blinking at 1 Hz

USER LED is blinking at 1/2 Hz
USER LED is blinking at 2 Hz

FORCE COMPUTERS

SPARC CPU-SV Teclmical Reference Manual

3.10.2.2

Hardware Description

USER LED 2 Control Register
Physical Address 7138 0001 16
7

6

5

4

1

1

1

1

3

2

1

o

COLOUR

COLOUR (RW) These two bits are used to turn the second USER LED on or off, and to control the colour of the LED. The table below lists all possible values:

COLOUR

Colour of the second USER LED (LED #1)

002
01 2

USER LED is turned off

102
112

USER LED is turned on and shines red

USER LED is turned on and shines green
USER LED is turned on and shines yellow

BLINK_FREQ (RW) These two bits control the frequency at which the second USER LED is
blinking. The table below lists all possible values and the corresponding blink frequency:

BLINK_FREQ

f blink of the second USER LED (LED #1)

002
01 2

USER LED is not blinking

102
112

USER LED is blinking at 1 Hz

FORCE COMPUTERS

USER LED is blinking at 1/2 Hz
USER LED is blinking at 2 Hz

Page 87

Hardware Description

3.10.3

SPARC CPU-SV Technical Reference Manual

Diagnostic LED (Hex Display)

A freely programmable LED display on the front panel provides diagnostic features. It can be
accessed via the Seven Segment LED Display Control Register.

3.10.3.1

Seven Segment LED Display Control Register
Physical Address 7138 OOOB16
765

432

;

0

The following figure shows the hex display with the segments named in accordance to their bits
in the Seven Segment LED Display Control Register. To switch a specific segment on, the
corresponding bit must be set to one.

FIGURE 13.

Segments of the Hex Display

SEG.fi

>

o

DP

Page 88

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

3.10.4

Hardware Description

Rotary Switch

The CPU-5V provides an additional rotary switch for user selectable settings. See the
''Diagram of the CPU-5V (Top View)" on page 10 for the position of the rotary switch on the
board. It is a hexadecimal rotary switch, decoded with 4 bits. The status of the rotary switch
can be read in the Rotary Switch Status Register.
The table below shows the rotary switch settings and the corresponding values of the bits
ROT[3 ..0], which you can read from the Rotary Switch Status Register.

3.10.4.1

Rotary Switch Status Register
Physical Address 7138 000316
7

6

5

4

1

1

1

1

2

3

o

1

ROTARY_SWITCH[3:0]

ROTARY_SWITCH[3:0] (R) These bits reflect the current state of the rotary switch. On the
SPARe CPU-5V the rotary switch is connected in such a way to the LCA that the signals ROTARY_SWITCH[3:0] are inverted!

ROTARY
ROTARY
Rotary Switch SWITCH [3:0] Rotary Switch SWITCH [3:0]

016

816

0111 2

916
A16

01102

116

11112
11102

216

1101 2

316

4 16

11002
1011 2

5 16
6 16

10102
1001 2

0 16

E16

00102
0001 2

7 16

10002

F16

00002

FORCE COMPUTERS

8 16
C16

0101 2
01002
0011 2

Page 89

Hardware Description

3.11

SPARC CPU-SV Technic:al Reference Manual

Additional Registers

The following additional registers are provided on the CPU-5V to increase functionality.

3.11.1

FMB Channel 0 Data Discard Status Register

FMB channel 0 consists of an 8-stage FIFO and so does the FMB Channel 0 Data Discard Status Register. Read accesses to this register switch the internal read pointer one step ahead in
the FIFO. Whenever your software needs to perform elementary functions as such, we recommend coordinating accesses to this register and the related FGA-5000 registers so that synchronisation of both f41f4"Os be not broken.

Physical Address 7138 OOOC16
7

6

5

4

3

2

1

1

1

1

1

1

1

0

MSG_VALID (R) The state of this bit indicates whether to discard the data in the FMB channel 0 of the SPARe FGA-5000. When the bit is cleared (0) then the data in the FMB
channel must be discarded. In the case that this bit is set (1) the data in the FMB channel is valid.

3.11.2

FMB Channell Data Discard Status Register
Physical Address 7138 OOOD16
7

6

5

4

1

1

1

1

3

2

1

0

MSG_VALID (R) The state of this bit indicates whether to discard the data in the FMB channel 1 of the SPARC FGA-5000. When the bit is cleared (0) then the data in the FMB
channel must be discarded. In the case where this bit is set (1) the data in the FMB
channel is valid.

A complete description of the FGA-5000 chip is found in the FGA-5000 Technical Reference
Manual, available from FORCE COMPUTERS.

Page 90

FORCE COMPUTERS

SPARC CPU-SV TeclmicaI Reference Manual

SECTION 4
4.

Software

4.1

OpenBoot

OpenBoot

OpenBoot

This section describes the enhancements to the standard OpenBoot firmware that have been
done for the SPARC CPU-5V. For a description of standard OpenBoot firmware features,
please see the OPEN BOOT PROM 2.0 MANUAL SET.
Besides the commands already provided by the standard OpenBoot firmware, the OpenBoot
firmware available on the SPARe CPU-5V includes further words for the following:
• accessing and controlling the VMEbus Interface,
• accessing and programming available flash memories,
• controlling the operating mode of the Watchdog Timer, and
• making use of the Diagnostics.

The following subsections describe these words in detail, and examples are given when it
seems necessary to convey the usage of a particular or a group of words. In general, each word
is described using the notation stated below:

name (stack-comment) description
The name field identifies the name of the word being described.
The stack parameters passed to and returned from a word are described by the stackcomment notation - enclosed in parentheses - , and show the effect of the word on
the evaluation stack. The notation used is:

parameters before execution - parameters after execution
The parameters passed and returned to the word are separated by the "-".
The description body describes the semantics of the word and conveys the purpose and
effect of the particular word.
The OpenBoot ported to the SPARC CPU-5V is based upon the OpenBoot 2.15 obtained from
Sun Microsystems.

FORCE COMPUTERS

Page 91

SPARC CPU-SV Technical Reference Manual

OpenBoot

4.2

VMEbus Interface

The VMEbus Interface on the SPARC CPU-5V consists of FORCE COMPUTERS' SPARe
FGA-SOOO (Vsn chip. The FORCE Gate Array-5000 is a VMEbus to SBus interface chip.

4.2.1

Generic Information

The variables - which are declared as value - described below are used to retrieve generic
information about the VMEbus interface:

vsi-va ( - vaddr) returns the virtual base address vaddr of the registers included in the
SPARe FGA-5000.
vs i -pa ( - paddr ) returns the physical base address paddr of the registers included in the
SPARe FGA-5000.
vsi-sbus-slot# ( - sbus-slot#) returns the number of the SBus slot sbus-slot# where
the registers of the SPARC FGA-5000 are accessible.
vsi-offset (-offset) returns the offset within the particularSBus slot at which the registers, included in the SPARC FGA-5000, are accessible.
The base address of the SPARC FGA-5000, which is specified by the values vsi-sbusslot# and vsi-offset, may be modified by the command described below:

vsi-base-addr! (offset sbus-slot# - ) sets the base address of the SPARC FGA-5000
according to the given SBus slot number sbus-slot# and the offset offset within the
specified SBus slot. The values sbus-slot# and offset are stored in the appropriate variables vsi-sbus-slot# and vsi-offset.
Furthermore, the command sets the variables vsi-pa and vsi-va according to the
given parameters.
On the SPARe CPU-5V the SBus slots are utilized as stated in the table below.
sbus-slot#

SSEL

Address Range

Description

0

-

2000.000016···2FFF.FFFF16

SBus Slot #0 (AFX)

:1

'Q

., 3()()()~o09016·~.3FFEFfFFI6

·····SBusSlotifl(reservedforVMEbus
accessesthroUgh·the,SPARCFGA~5000)
..

<.

..

SBus Slot #2 (Sbus Card 1)

2

4OOO.000016···4FFF.FFFF16
5000.000016···5FFF.FFFF16

4

3

6OOOJX)OO16··· 6FFF.FFFF16

SBus Slot #4 (Sbus Card 3)

5

4

7000.0000 16•••7FFF.FFFF16

SBus Slot #5 (MACIO,SLAVIO,
SPARe FGA-5000 Registers)

2

1

3

Page 92

SBus Slot #3 (Sbus Card 2)

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

vs i - base-addr@ ( - offset sbus-slot#) returns the base address of the SPARC FGA-5000
represented by the SBus slot number sbus-slot# and the offset offset within the specific
SBus slot.

4.2.2

Register Addresses

The commands described below are used to obtain the virtual addresses of specific registers in
the SPARC FGA-5000:

vsi-sbus-base ( - vaddr) returns the virtual address vaddrofthe SPARC FGA-5000's
SBus Base Address Register.
vs i - id ( - vaddr ) returns the virtual address vaddr of the SPARC FGA-5000's Identification Register.
vs i -vme-range ( range# - vaddr) returns the virtual address vaddr of the SPARC FGA5000' s SBus Address Decoding And Translation Register identified by its register
number range#. The value of range# may be one of the values in the range zero
through 15. Each value specifies one of the 16 SBus Address Decoding and Translation Registers.
vsi-vme-master-cap ( range# - vaddr ) returns the virtual address vaddr of the
SPARC FGA-5000's VMEbus Master Capability Register identified by its register
number range#. The value of range# may be one of the values in the range zero
through 15. Each value specifies one of the 16 VMEbus Master Capability Registers.
vsi-vme-cap ( - vaddr) returns the virtual address vaddr of the SPARC FGA-SOOO's
VMEbus Capability Register.
.
vs i - sbus - ssel ( range# - vaddr) returns the virtual address vaddr of the SPARC FGA5000' s SBus Slave Slot Select Register identified by its register number range#. The
value of range# may be one of the values in the range zero through 15. Each value
specifies one of the 16 SBus Slave Slot Select Registers.
vsi-sbus-master-cap ( - vaddr ) returns the virtual address vaddr of the SPARC
FGA-SOOO's SBus Master Capability Register.
vsi-sbus-retry-time-ctrl ( - vaddr ) returns the virtual address vaddr of the
SPARC FGA-SOOO's SBus Retry Time Control Register.
vsi-sbus-rerun-limit-ctrl ( - vaddr) returns the virtual address vaddr of the
SPARC FGA-SOOO's SBns Rerun Limit Control Register.

FORCE COMPUTERS

Page 93

OpenBoot

SPARC CPU-SV Technical Reference Manual

vs i - swpar ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's SBus
Write Posting Error Address Register.
vsi-vwpar ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5OOO's
VMEbus Write Posting Error Address Register.
vs i - s lerr ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's SBus
Late Error Address Register.
vsi-slerr-irq-map ( - vaddr) returns the virtual address vaddr of the SPARe FGA5000' s SBus Late Error Interrupt Level Select and Enable Register.
vsi-iack-emu (level- vaddr) returns the virtual address vaddr of the SPARe FGA5000' s lACK Cycle Emulation Register associated with the given level. The value of
level may be one of the values in the range one through seven. Each value specifies
one of the seven VMEbus interrupt request levels.
Only the least significant three bits of level are considered and when level is zero then
the command treats it as if the value "one" has been passed to the command.
vsi-vme-base ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's
VMEbus Base Address Register.
vs i - sbus -range ( range# - vaddr ) returns the virtual address vaddr of the SPARe
FGA-5000's VMEbus Address Decoding and Translation Register identified by its
range number range#. The value of range# may be one of the values in the range zero
through two. Each value specifies one of the three VMEbus Address Decoding and
Translation Registers.
vsi-vme-ext ( range# - vaddr) returns the virtual address vaddr of the SPARe FGA5000' s VMEbus Address Extension Register identified by its range number range#.
The value of range# may be one of the values in the range zero through two. Each
value specifies one of the three VMEbus Address Extension Registers.
vsi-reset-stat ( - vaddr) returns the virtual address vaddr of the SPARe FGA5000' s Reset Source Register.
vsi-intr-stat ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's
Interrupt Status Register.
vsi-irq-map ( level- vaddr) returns the virtual address vaddr of the SPARe FGA5OOO's VMEbus Interrupt Level Select and Enable Register associated with the
given level. The value of level may be one of the values in the range one through
seven. Each value specifies one of the seven VMEbus interrupt request levels.
Only the least significant three bits of level are considered and when level is zero then
the command treats it as if the value "one" has been passed to the command.
Page 94

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

vsi-mbox-irq-map ( mailboX# - vaddr) returns the virtual address vaddr of the
SPARC FGA-5000's Mailbox Interrupt Level Select and Enable Register identified by its mailbox number mailboX#. The value of mailboX# may be one of the values
in the range zero through 15. Each value specifies one of the 16 Mailbox Interrupt
Level Select and Enable Registers.
vsi-dma-irq-map ( - vaddr) returns the virtual address vaddr of the SPARe FGA5000' s DMA Interrupt Level Select and Enable Register.
vsi-wpe-irq-map ( - vaddr) returns the virtual address vaddr of the SPARe FGA5000' s Write Posting Error Interrupt Level Select and Enable Register.
vsi-arb-irq-map ( - vaddr) returns the virtual address vaddr of the SPARe FGA5000' s Arbiter TlDleout Interrupt Level Select and Enable Register.
vsi-wdt-irq-map ( - vaddr) returns the virtual address vaddr of the SPARe FGA5000' s Watchdog IlDler Interrupt Level Select and Enable Register.
vsi -acfail- irq-map ( - vaddr) returns the virtual address vaddr of the SPARe FGA5000' s ACFAIL Interrupt Level Select and Enable Register.
vsi-sysfail-irq-mapO ( - vaddr) returns the virtual address vaddr of the SPARe
FGA-5000's SYSFAIL Assert Interrupt Level Select and Enable Register.
vsi-sysfail-irq-mapl ( - vaddr) returns the virtual address vaddr of the SPARe
FGA-5000's SYSFAIL Negate Interrupt Level Select and Enable Register.
vsi-abort-irq-map ( - vaddr) returns the virtual address vaddr of the SPARe FGA5000' s Abort Interrupt Level Select and Enable Register.
vsi-arb-ctrl ( - vaddr) returns the virtual address vaddr of the SPARC FGA-5000's
Arbiter Control Register.
vsi-req-ctrl ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's
Requester Control Register.
vsi-bus-ctrl ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's
Bus Capture Control Register.
vsi-mbox ( mailbox# - vaddr) returns the virtual address vaddr of the SPARe FGA5OOO's Mailbox Register identified by its mailbox number mailbox#. The value of
mailbox# may be one of the values in the range zero through 15. Each value specifies
one of the 16 Mailbox Registers.
vsi-mbox-stat ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's
FORCE COMPUTERS

Page 95

OpeuBoot

SPARC CPU-SV Technical Reference Manual

Mailbox Status Register.
vs i - sem ( semaphore# - vaddr) returns the virtual address vaddr of the SPARC FGA5000's Semaphore Register identified by its semaphore number semaphore#. The
value of semaphore# may be one of the values in the range zero through 47. Each
value specifies one of the 48 Semaphore Registers.
vsi-fmb-ctrl ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's
Message Broadcast Control Register.
vs i - fmb- irq-map ( channell - vaddr ) returns the virtual address vaddr of the SPARC
FGA-5000's Message Broadcast Interrupt Level Select and Enable Register identified by its channel number channell. The value of channell may be one of the values
in the range zero to one. Each value specifies one of the two Message Broadcast Interrupt Level Select and Enable Registers.
vsi-fmb-addr ( - vaddr) returns the virtual address vaddr of the SPARC FGA-5000's
Message Broadcast Address Register.
vsi-fmb-stat ( channell - vaddr) returns the virtual address validr of the SPARe
FGA-5000's Message Broadcast Status Register identified by its channel number
channell. The value of channell may be one of the values in the range zero to one.
Each value specifies one of the two Message Broadcast Status Registers.
vsi-fmb-msg (channel#- vaddr) returns the virtual address vaddr of the SPARe FGA5000' s Message Broadcast Register identified by its channel number channell. The
value of channell may be one of the values in the range zero to one. Each value specifies one of the two Message Broadcast Registers.
vsi-gcsr ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's Global
Control and Status Register.
vsi-wdt-ctrl ( - vaddr) returns the virtual address vaddr of the SPARC FGA-5000's
Watchdog Tuner Control Register.
.vsi-wdt-restart ( - vaddr ) returns the virtual address vaddr of the SPARe FGA5000' s Watchdog Restart Register.
vsi-mcsrO ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's Miscellaneous Control and Status Register O.
vsi -mcsrl ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's Mis..
cellaneous Control and Status Register 1.

Page 96

FORCE COl\1PUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

vsi-dma-ctrl ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's
DMA Control Register.
vsi-dma-mode ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's
DMA Mode Register.
vsi-dma-stat ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's
DMA Status Register.
vsi-dma-src ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's
DMA Source Address Register.
vsi-dma-dest ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's
DMA Destination Address Register.
vsi-dma-cap ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's
DMA Capability and Transfer Count Register.
vsi-ibox-irq-map ( - vaddr) returns the virtual address vaddr of the SPARC FGA5000' s Interrupt Box Interrupt Level Select and Enable Register.
vsi-ibox-ctrl ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's
Interrupt Box Control Register.
vs i - ibox-addr ( - vaddr) returns the virtual address vaddr of the SPARe FGA-5000's
Interrupt Box Address Register.

The following commands are available to get the virtual addresses of the System Configuration
Registers.

sysconfig-va ( - vaddr) returns the virtual base address vaddr of the System Configuration Registers.
ledl-ctrl ( - vaddr) returns the virtual address vaddr of the First User LED Control
Register.
led2 -ctr 1 ( - vaddr) returns the virtual address vaddr of the Second User LED Control
Register.
flash-ctrll ( - vaddr) returns the virtual address vaddr of the Flash Memory Control
Register 1.
rotary-switch-stat ( - vaddr) returns the virtual address vaddr of the Rotary
Switch Status Register.
FORCE COMPUTERS

PagefJ7

SPARC CPU-SV Technical Reference Manual

OpenBoot

boot-rom-size-ctrl ( - vaddr) returns the virtual address vaddr of the Boot ROM
Size Control Register.
flash-ctr12 ( - vaddr) returns the virtual address vaddr of the Flash Memory Control
Register 2.
flash-vpp-ctrl ( - vaddr) returns the virtual address vaddr of the Flash Memory Pro-gramming Voltage Control Register.
led-display-ctrl ( - vaddr) returns the virtual address vaddr of the LED Display
Control Register.
fmb-O-data-discard ( - vaddr) returns the virtual address vaddr of the FMB Channel 0 Data Discard Status Register.
fmb-l-da ta -discard ( - vaddr ) returns the virtual address vaddr of the FMB Channell Data Discard Status Register.
lca - id ( -

vaddr) returns the virtual address vaddr of the LCA ID Register.

4.2.3 Register Accesses
The commands described below are used to read data from and to store data in specific registers
of the SPARe FGA-5000:
vsi-sbus-base@ ( - long) returns the contents Address Register.

a 32-bit data - of the SBus Base

vsi-sbus-base! (long - ) stores the 32-bit data long in the SBus Base Address Register.
vs i - id@ ( - id-code ) returns the contents - the 32-bit data id-code - of the Identification
Register.
vsi-vme-range@ (range#-long) returns the contents - a 32-bit data- of the SBus
Address Decoding And Translation Register identified by its register number range#.
The value of range# may be one of the values in the range zero through 15. Each value
specifies one of the 16 SBus Address Decoding and Translation Registers.
vsi-vme-range! ( long range# - ) stores the 32-bit value long in the SBus Address
Decoding And Translation Register identified by its register number range#. The
value of range# may be one of the values in the range zero through 15. Each value
specifies one of the 16 SBus Address Decoding and Translation Registers.

Page 98

FORCE COMPUTERS

OpenBoot

SPARC CPU-SV Technical Reference Manual

vsi-vme-roaster-cap@ (range#- byte) returns the contents - an 8-bit data- of the
VMEbus Master Capability Register identified by its register number range#. The
value of range# may be one of the values in the range zero through 15. Each value
specifies one of the 16 VMEbus Master Capability Registers.
vsi -vme-roaster-cap! (byte range#-) stores the 8-bit data byte in the VMEbus Master Capability Register identified by its register number range#. The value of range#
may be one of the values in the range zero through 15. Each value specifies one of the
16 VMEbus Master Capability Registers.
vsi -vme-cap@ ( - byte) returns the contents - an 8-bit data - of the VMEbus Capability Register.
vsi -vme-cap! (byte - ) stores the 8-bit data byte in the VMEbus Master Capability Register.
vsi-sbus-ssel@. ( range# - byte) returns the contents - an 8-bit data - of the SBus
Slave Slot Select Register identified by its register number range#. The value of
range# may be one of the values in the range zero through 15. Each value specifies
one of the 16 SBus Slave Slot Select Registers.
vsi-sbus-ssel! (byte range#-) stores the 8-bit data byte in the SBus Slave Slot Select
Register identified by its register number range#. The value of range# may be one of
the values in the range zero through 15. Each value specifies one of the 16 SBus Slave
Slot Select Registers.
vs i - sbus - cap@ ( - byte) returns the contents 5OOO's SBus Capability Register.

an 8-bit data -

of the SPARC FGA-

vsi-sbus-cap! (byte - ) stores the 8-bit data byte in the SPARC FGA-5000's SBus
Capability Register.
vsi-sbus-retry-time-ctrl@ (-byte) returns the contents-an 8-bit data-of the
SPARC FGA-5000's SBus Retry Time Control Register.
vsi-sbus-retry-time-ctrl! (byte - ) stores the 8-bit data byte in the SPARC
FGA-5000's SBus Retry Time Control Register.
vs i - sbus -rerun-limi t -ctr l@ ( - word) returns the contents the SPARC FGA-5000's SBus Rerun Limit Control Register.

a 16-bit data - of

vsi-sbus-rerun-limit-ctrl! (word - ) store the 16-bit data word in the SPARC
FGA-5000's SBus Rerun Limit Control Register.

FORCE COMPUTERS

Page 99

OpenBoot

SPARC CPU-SV Technical Reference Manual

vs i - swpar@ ( -long) returns the contents - a 32-bit data Error Address Register.

of the SBus Write Posting

vs i -vwpar@ ( -long) returns the contents - a 32-bit data - of the VMEbus Write Posting Error Address Register.
vsi-slerr@ (-long) returns the contents Address Register.

a 32-bit data -

vsi-slerr-irq-map@ ( - byte) returns the contents Error Interrupt Level Select and Enable Register.

of the SBus Late Error

an 8-bit data -

of the Late

vsi-slerr-irq-map! (byte - ) stores the 8-bit data byte in the Late Error Interrupt
Level Select and Enable Register.
vsi-iack-emu@ (level- byte) returns the contents - an 8-bit data - of the lACK
Cycle Emulation Register associated with the given level. The value of level may be
one of the values in the range one through seven. Each value specifies one of the seven
VMEbus interrupt request levels.
Only the least significant three bits of level are considered and when level is zero then
the command treats it as if the value "one" has been passed to the command.
vsi-vme-base@ ( - byte) returns the contents Address Register.

an 8-bit data - of the VMEbus Base

vsi-vme-base! (byte - ) stores the 8-bit data byte in the VMEbus Base Address Register.
vs i - sbus -range@ ( range# -long) returns the contents - a 32-bit data - of the VMEbus Address Decoding and Translation Register identified by its range number range#.
The value of range# may be one of the values in the range zero through two. Each
value specifies one of the three VMEbus Address Decoding and Translation Registers.
vs i - sbus- range! (long range# - ) stores the 32-bit data long in the VMEbus Address
Decoding and Translation Register identified by its range number range#. The value
of range# may be one of the values in the range zero through two. Each value specifies
one of the three VMEbus Address Decoding and Translation Registers.
vsi-vme-ext@ ( range# - byte) returns the contents - an 8-bit data - of the VMEbus
Address Extension Register identified by its range number range#. The value of
range# may be one of the values in the range zero through two. Each value specifies
one of the three VMEbus Address Extension Registers.

Page 100

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

vsi-vme-ext! (byte range#-) stores the 8-bit data byte in the VMEbus Address Extension Register identified by its range number range#. The value of range# may be one
of the values in the range zero through two. Each value specifies one of the three
VMEbus Address Extension Registers.
vsi-reset-stat@ ( - byte) returns the contents Register.
vs i-in tr- s ta t@ ( -long) returns the contents Register.

an 8-bit data -

a 32-bit data -

of the Reset Source

of the Interrupt Status

vs i-intr- s ta t! (long - ) stores the 32-bit data long in the Interrupt Status Register.
. vsi-intr-stat ( - ) displays the actual contents of the Interrupt Status Register. The
contents of the register is displayed as shown below:
ok .vsi-intr-stat
VME-IRQ1: 0 VME-IRQ2:
VME-IRQ6: 0 VME-IRQ7:
IBOX
:
0 LERR
MAILBOX
:
SWPERR
0
SYSFAIL- : 0 ACFAIL :

0
0
0
0

VME-IRQ3: 0
VME-IACK: 0

VME-IRQ4: 0

0
ARBTOUT : 0

DMATERM
ABORT

WDOG

FMBl

0
0
0

VME-IRQ5: 0
FMBO
VWPERR

: 0

0

SYSFAIL+: 0

0

ok

When an interrupt is pending the command displays the one (1); otherwise it displays
the zero (0) to indicate that the interrupt is not pending.

Note! The state of the entry SYSFAIL- reports the occurrence of a negative edge of
the VMEbus SYSFAIL* signal which indicates that the SYSFAIL* signal has been
asserted. The state of the entry SYSFAIL+ reports the occurrence of a positive edge
of the VMEbus SYSFAIT...* signal which indicates that the SYSFAIL* signal has been

negated.
vs i - irq-map@(level-byte)returnsthecontents-an8-bitdata-oftheVMEbus
Interrupt Level Select and Enable Register associated with the given level. The value
of level may be one of the values in the range one through seven. Each value specifies
one of the seven VMEbus interrupt request levels.
Only the least significant three bits of level are considered and when level is zero then
the command treats it as if the value "one" has been passed to the command.
vsi-irq-map! (byte level-) stores the 8-bit data byte in the VMEbus Interrupt Level
Select and Enable Register associated with the given level. The value of level may be
one of the values in the range one through seven. Each value specifies one of the seven
VMEbus interrupt request levels.
Only the least significant three bits of level are considered and when level is zero then
the command treats it as if the value "one" has been passed to the command.
FORCE CO:MPUTERS

Page 101

OpenBoot

SPARe CPU-SV Technical Reference Manual

vs i -mbox- irq-map@ ( mailboX# - byte) returns the contents - an 8-bit data - of the
Mailbox Interrupt Level Select and Enable Register identified by its mailbox number
mailbox#. The value of mailbox# may be one of the values in the range zero through
15. Each value specifies one of the 16 Mailbox Interrupt Level Select and Enable Registers.
vs i -mbox- irq-map! (byte mailboX# - ) stores the 8-bit data byte in the Mailbox Interrupt Level Select and Enable Register identified by its mailbox number mailbox#. The
value of mailboX# may be one of the values in the range zero through 15. Each value
specifies one of the 16 Mailbox Interrupt Level Select and Enable Registers.
vsi-dma-irq-map@ ( - byte) returns the contents rupt Level Select and Enable Register.

an 8-bit data- of the DMA Inter-

vs i-dIna - irq-map! (byte - ) stores the 8-bit data in the DMA Interrupt Level Select and
Enable Register.
vsi-Vt7pe-irq:-map@ ( - byte) returns the contents - an 8-bit data - of the Write Posting Error Interrupt Level Select and Enable Register.
vs i -Vt7pe- irq-map! (byte - ) stores the 8-bit data byte in the Write Posting Error Interrupt Level Select and Enable Register.
vsi-arb-irq-map@ ( - byte) returns the contents - an 8-bit data Timeout Interrupt Level Select and Enable Register.

of the Arbiter

vsi-arb-irq-map! (byte - ) stores the 8-bit data byte in the Arbiter Timeout Interrupt
Level Select and Enable Register.
vs i -wdt - irq-map@ ( - byte) returns the contents Timer Interrupt Level Select and Enable Register.

an 8-bit data -

of the Watchdog

vsi-wdt-irq-map! (byte - ) stores the 8-bit data byte in the Watchdog Timer Interrupt
Level Select and Enable Register.
vsi-acfail-irq-map@ ( - byte) returns the contents ACFAIL Interrupt Level Select and Enable Register.

an 8-bit data -

of the

vsi-acfail-irq-map! (byte - ) stores the 8-bit data byte in the ACFAIL Interrupt
Level Select and Enable Register.
vsi -sysfail-irq-mapO@ ( - byte) returns the contents - an 8-bit data - of the SYSFAIL Assert Interrupt Level Select and Enable Register.

Page 102

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

vsi-sysfail-irq-mapO! (byte - ) stores the 8-bit data byte in the SYSFAIL Assert
Interrupt Level Select and Enable Register.
vs i - sys fail- irq-mapl@ ( - byte) returns the contents - an 8-bit data - of the SYSFAIL Negate Interrupt Level Select and Enable Register.
vsi-sysfail-irq-mapl! (byte - ) stores the 8-bit data byte in the SYSFAlL Negate
Interrupt Level Select and Enable Register.
vsi-arb-ctrl@ ( - byte) returns the contents - an 8-bit data Register.

of the Arbiter Control

vsi-arb-ctrl! (byte - ) stores the 8-bit data long in the Arbiter Control Register.
vsi-req-ctrl@ ( - byte) returns the contents - an 8-bit data- of the Requester Control Register.
vsi-req-ctrl! (byte -) stores the 8-bit data byte in the Requester Control Register.
vsi-bus-ctrl@ ( - byte ) returns the contents Control Register.

an 8-bit data -

of the Bus Capture

vsi-bus-ctrl! (byte - ) stores the 8-bit data byte in the Bus Capture Control Register.
vs i -mbox@ ( mailbox#- byte) returns the contents - an 8-bit data - of the Mailbox Register identified by its mailbox number mailbox#. The value of mailbox# may be one of
the values in the range zero through 15. Each value specifies one of the 16 Mailbox
Registers.
vs i -mbox! (byte mailbox# - ) stores the 8-bit data byte in the Mailbox Register identified
by its mailbox number mailbox#. The value of mailbox# may be one of the values in
the range zero through 15. Each value specifies one of the 16 Mailbox Registers.
vs i -mbox- s ta t@ ( - word) returns the contents - a 16-bit data - of the Mailbox Status
Register.
vsi-mbox-stat! (word-) stores the 16-bit data long in the Mailbox Status Register.
vs i - sem@ ( semaphore# - byte) returns the contents - an 8-bit data - of the Semaphore
Register identified by its semaphore number semaphore#. The value of semaphore#
may be one of the values in the range zero through 47. Each value specifies one of the
48 Semaphore Registers.

FORCE COMPUTERS

Page 103

OpenBoot

SPARC CPU-SV Technical Reference Manual

vs i - sem! (byte semaphore# - ) stores the 8-bit data byte in the Semaphore Register identified by its semaphore number semaphore#. The value of semaphore# may be one of
the values in the range zero through 47. Each value specifies one of the 48 Semaphore
Registers.
vsi-fmb-ctrl@ ( - byte) returns the contents - an 8-bit data- of the Message Broadcast Control Register.
vsi-fmb-ctrl! (byte Register.

) stores the 8-bit data byte in the Message Broadcast Control

vs i - fmb- irq-map@ ( channell - byte ) returns the contents - an 8-bit data - of the
Message Broadcast lnterrupt Level Select and Enable Register identified by its channel number channel#. The value of channell may be one of the values in the range
zero to one. Each value specifies one of the two Message Broadcast Interrupt Level
Select and Enable Registers.
vs i - fmb- irq-map! (byte channell - ) stores the 8-bit data byte in the Message Broadcast Interrupt Level Select and Enable Register identified by its channel number channel#. The value of channel# may be one of the values in the range zero to one. Each
value specifies one of the two Message Broadcast Interrupt Level Select and Enable
Registers.
vs i - fmb-addr@ ( - byte) returns the contents - an 8-bit data - of the Message Broadcast Address Register.
vs i - fmb- addr! (byte Register.

) stores the 8-bit data byte in the Message Broadcast Address

vs i - fmb- stat@ ( channell - byte) returns the contents - an 8-bit data - of the Message Broadcast Status Register identified by its channel number channell. The value
of channell may be one of the values in the range zero to one. Each value specifies
one of the two Message Broadcast Status Registers.
vs i - fmb- s ta t! (byte channell - ) stores the 8-bit data byte in the Message Broadcast
Status Register identified by its channel number channell. The value of channell may
be one of the values in the range zero to one. Each value specifies one of the two Message Broadcast Status Registers.
vs i - fmb-msg@ ( channell - long true Ifalse) returns the contents - a 32-bit data - of
the Message Broadcast Register identified by its channel number channel#. The value
of channell may be one of the values in the range zero to one. Each value specifies
one of the two Message Broadcast Registers.

Page 104

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

vsi-gcsr@ ( - byte) returns the contents -

OpenBoot

an 8-bit data -

of the Global Control and

Status Register.

vsi-gcsr! (byte - ) stores the 8-bit data byte in the Global Control and Status Register.
vs i -mcsrO@ ( - byte) returns the contents -

an 8-bit data - of the Miscellaneous Con-

trol and Status Register O.

vsi-mcsrO! (byte - ) stores the 8-bit data byte in the Miscellaneous Control and Status
Register O.

vsi-mcsrl@ ( - byte) returns the contents -

an 8-bit data -

of the Miscellaneous Con-

trol and Status Register 1.

vsi-mcsrl! (byte - ) stores the 8-bit data byte in the Miscellaneous Control and Status
Register 1.

vsi -wdt-ctr l@ ( - byte) returns the contents - an 8-bit data - of the Watchdog Timer
Control Register.

vsi-wdt-ctrl! (byte - ) stores the 8-bit data byte in the Watchdog Timer Control Register.

vsi-wdt-restart@ ( - byte) returns the contents -

an 8-bit data -

of the Watchdog

Restart Register.

vsi-wdt-restart! (byte - ) stores the 8-bit data byte in the Watchdog Restart Register.
vsi-dIna-ctrl@ ( - word) returns the contents -

a 16-bit data -

of the DMA Control

Register.

vsi-dIna-ctrl! (word-) stores the 16-bit data word in the DMA Control Register.
vs i-dIna -mode@ ( - byte) returns the contents - an 8-bit data - of the DMA Mode Register.

vsi-dma-mode! (byte - ) stores the 8-bit data byte in the DMA Mode Register.
vsi-dma-stat@ ( - byte) returns the contents -

an 8-bit data -

of the DMA Status

Register.

vsi-dma-stat! (byte - ) stores the 8-bit data byte in the DMA Status Register.
vsi-dma-src@ ( -

long) returns the contents Address Register.

FORCE COMPUTERS

a 32-bit data -

of the DMA Source

Page 105

SPARC CPU-SV Technical Reference Manual

OpenBoot

vsi-dma-src! (long - ) stores the 32-bit data long in the DMA Source Address Register.
vsi-dma-dest@ (-long) returns the contents tion Address Register.
vsi-dma-dest! (long Register.

a 32-bit data -

of the DMA Destina-

) stores the 32-bit data long in the DMA Destination Address

vs i -dma -cap@ ( - long) returns the contents and Transfer Count Register.

a 32-bit data -

of the DMA Capability

vsi-dma-cap! (long - ) stores the 32-bit data long in the DMA Capability and Transfer
Count Register.
vsi-ibox-irq-map@ ( - byte) returns the contents Box Interrupt Level Select and Enable Register.

an 8-bit data -

of the Interrupt

vsi-ibox-irq-map! (byte - ) stores the 32-bit data long in the Interrupt Box Interrupt
Level Select and Enable Register.
vsi - ibox-ctr l@ ( - word) returns the contents Control Register.
vs i - ibox- c tr I! (word ister.

) stores the 16-bit data word in the Interrupt Box Control Reg-

vsi - ibox-addr@ ( - word) returns the contents Address Register.
vsi-ibox-addr! (word Register.

a 16-bit data - of the Interrupt Box

a 16-bit data -

of the Interrupt Box

) stores the 16-bit data word in the Interrupt Box Address

The following commands are available to read data from and store data in the System
Configuration Registers .

. ledl- ctrl@ ( - byte) returns the contents - an 8-bit data - of the First User LED Control Register.
ledl- ctr I! (byte -

) stores the 8-bit data byte in the First User LED Control Register.

led2 - ctr l@ ( - byte) returns the contents Control Register.

an 8-bit data -

of the Second User LED

led2-ctrl! (byte - ) stores the 8-bit data byte in the Second User LED Control Register.

Page 106

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

flash-ctrll@ ( - byte) returns the contents Control Register 1.

OpenBoot

an 8-bit data -

of the Flash Memory

flash-etrll! (byte - ) stores the 8-bit data byte in the Flash Memory Control Register
1.

rotary-swi teh-stat@ ( - byte) returns the contents - an 8-bit data - of the Rotary
Switch Status Register.
boot-rom-size-etrl@(-byte)returnsthecontents-,an8-bitdata-of the Boot
ROM Size Control Register.
boot-rom-size-etrl! (byte - ) stores the 8-bit data byte in the Boot ROM Size Control Register.
flash-etr12@ ( - byte) returns the contents Control Register 2.

an 8-bit data -

of the Flash Memory

flash-etr12! (byte - ) stores the 8-bit data byte in the Flash Memory Control Register
2.
flash -vpp-e tr l@ ( - byte) returns the contents - an 8-bit data - of the Flash Memory
Programming Voltage Control Register.
flash-vpp-etrl! (byte - ) stores the 8-bit data byte in the Flash Memory Programming
Voltage Control Register.
led-display-etrl@ (byte - ) returns the contents - an 8-bit data- of the LED Display Control/Status Register. Because the LED Display Control Register is only writable, the command returns the contents of the LED Display Control Shadow Register.
led-display-ctrl! ( - byte) stores the 8-bit data byte in the LED Display Controll
Status Register. Because the LED Display Control Register is only writable, the command stores the given data in the LED Display Control Shadow Register, too.
fmb-O-data-diseard@ ( - byte) returns the contents - an 8-bit data Channel 0 Data Discard Status Register.

of the FMB

fmb-l-data-diseard@ ( - byte) returns the contents - an 8-bit data Channel 1 Data Discard Status Register.

of the FMB

lea - id@ ( - byte) returns the contents - an 8-bit data - of the LCA ID Register.

FORCE COMPUTERS

Page 107

SPARC CPU-SV Technical Reference Manual

OpeoBoot

4.2.4

VMEbus Interrupt Handler

vrne-intr-pending? ( level- true Ifalse ) checks whether an interrupt is pending on a
given interrupt request level and returns aflag. When an interrupt is pending theflag is
true; otherwise it isfalse. The value of level may be one of the values in the range one
through seven. Each value specifies one of the seven ~bus interrupt request levels.
Only the least significant three bits of level are considered and when level is zero then
the command treats it as if the value "one" has been passed to the command.
The command verifies the state of the interrupt pending bit in the Interrupt Status register associated with the given level. When the corresponding status bit is set then no
V~'hllC ;nt~rrllnt ;c ~nrf;n(f ~nrl th~ I"nTT1TT1~nrf r~tllrnc
.. .L .. .4AJ..., ..... ~ .& ...... "''-'&..& ""'"I"'" .&.u .t'...,... .1.~~ .. b
...... & ...... tooiil ... " ....,V'&.&.u.....&....... .&~ .. ...,.-...&..I. ... u

£,,1"0 {)th~rur;c~
_
J"'''''''''''''.
""" ..........,... "..,. . .
~

th~ Ct~tllC

-..&..,a"" u ...... ""w.t.:I

bit is cleared - the value true is returned.

vme- iack@ ( level- vector) initiates an interrupt acknowledge cycle at the given ~bus
interrupt request level and returns the obtained 8-bit vector. The value of level may be
one of the values in the range one through seven. Each value specifies one of the seven
VMEbus interrupt request levels.
Typically, the vector returned is within the range 0 through 255, but when no interrupt
is pending, and therefore no interrupt has to be acknowledged, the value -1 is returned.
Only the least significant three bits of level are considered and when level is zero then
the command treats it as if the value "one" has been passed to the command.

Page 108

FORCE COMPUTERS

SPARe CPU-SV Technical Reference Manual

OpenBoot

vme- intr-ena ( mapping level- ) enables the interrupt to be generated upon the receipt
of a VMEbus interrupt at level. The parameter mapping defines the interrupt asserted
by the SPARe FGA-5000 when the certain VMEbus interrupt request level is asserted.
The value of mapping may be one of the values in the range one through seven. Each
value specifies one of the eight SPARC FGA-5000 interrupt request lines. The table
below lists all allowed mappings.
The value of level may be one of the values in the range one through seven. Each value
specifies one of the seven VMEbus interrupt request levels.
Only the least significant three bits of mapping and level are considered. When level is
zero then the command treats it as if the value "one" has been passed to the command.

mapping Constant

Interrupt generated by SPARe FGA-5000

0

vsi-nmi

!NT (connected with nonmaskable interrupt)

1

vsi-sbus-irq-l
vsi-sbus-irq-2
vsi-sbus-irq-3

S!NTI (connected with SBus IRQ1)

S!NT4 (connected with SBus IRQ4)

5

vsi-sbus-irq-4
vsi-sbus-irq-5

6

vsi-sbus-irq-6

SINT6 (connected with SBus IRQ6)

7

vsi-sbus-irq-7

SINT7 (connected with SBus IRQ7)

2

3
4

SINT2 (connected with SBus IRQ2)
SINT3 (connected with SBus IRQ3)
SINT5 (connected with SBus IRQ5)

The words listed in the second column of the table may be used to specify a valid interrupt mapping.

Table 40: Interrupt Mapping.
vme-intr-dis (level-) disables the interrupt to be generated when the specified VMEbus interrupt request at level is asserted. The value of level may be one of the values in
the range one through seven. Each value specifies one of the seven VMEbus interrupt
request levels.
Only the least significant three bits of level are considered and when level is zero then
the command treats it as if the value "one" has been passed to the command.

vme- irq-ena ( level-) enables the interrupt to be generated upon the receipt of a VMEbus interrupt at level. The value of level may be one of the values in the range one
through seven. Each value specifies one of the seven VMEbus interrupt request levels.
Only the least significant three bits of level are considered and when level is zero then
the command treats it as if lQe value "one" has been passed to the command.

FORCE COMPUTERS

Page 109

OpenBoot

SPARC CPU-SV Technical Reference Manual

vme- irq-dis ( level-) disables the interrupt to be generated upon the receipt of a VN.IEbus interrupt at level. The value of level may be one of the values in the range one
through seven. Each value specifies one of the seven VlvIEbus interrupt request levels.
Only the least significant three bits of level are considered and when level is zero then
the command treats it as if the value "one" has been passed to the command.

vme-irq-map@ ( level- mapping) returns the interrupt asserted by the SPARC FGA5000 when the VN.IEbus interrupt request level is asserted. The value of level may be
one of the values in the range one through seven. Each value specifies one of the seven
VN.IEbus interrupt request levels.
Only the least significant three bits of level are considered and when level is zero then
the command treats it as if the value "one" has been passed to the command.

vme- irq-map! (mapping level -

) defines the interrupt asserted by the SPARC FGA5000 when the certain VN.IEbus interrupt request level is asserted. The value of mapping may be one of the values in the range one through seven. Each value specifies
one of the eight SPARC FGA-5000 interrupt request lines. The table ''Interrupt Mapping." on page 109 lists all allowed mappings.
The value of level may be one of the values in the range one through seven. Each value
specifies one of the seven VN.IEbus interrupt request levels.
Only the least significant three bits of mapping and level are considered. When level is
zero then the command treats it as if the value "one" has been passed to the command.

ins tall-vme- in tr- handler ( mapping level- ) installs the interrupt service routine
dealing with the given VN.IEbus interrupt level. The parameter mapping defines the
interrupt asserted by the SPARC FGA-5000 when the certain VMEbus interrupt
request level is asserted. The value of mapping may be one of the values in the range
zero through seven. Each value specifies one of the eight SPARC FGA-5000 interrupt
request lines. The table "Interrupt Mapping." on page 109 lists all allowed mappings.
The value of level may be one of the values in the range one through seven. Each value
specifies one of the seven VN.IEbus interrupt request levels. The address of the interrupt service routine currently in effect is preserved.
Only the least significant three bits of mapping and level are considered. When level is
zero then the command treats it as if the value "one" has been passed to the command.

uninstall-vme-intr-handler (level-) removes the interrupt service routine dealing with the given VMEbus interrupt level and installs the old interrupt service routine. The value of level may be one of the values in the range one through seven. Each
value specifies one of the seven VMEbus interrupt request levels.
Only the least significant three bits of level are considered and when level is zero then
the command treats it as if the value "one" has been passed to the command.

. VIne-vectors (-) displays the VMEbus interrupt vectors received during the last interrupt acknowledge cycle.
OpenBoot maintains seven variables called vme- in tr {112
Page 110

13 14 15 I 6 17 } -veeFORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

tor which are modified by the VMEbus interrupt handlers. In general, the interrupt
handlers store the vector obtained during an interrupt acknowledge cycle in the appropriate variable.

FORCE COMPUTERS

Page 111

OpenBoot

4.2.5

SPARC CPU-SV Technical Reference Manual

VMEbus Arbiter

The commands listed below are available to control the arbiter:

vme-slotl-ena ( - ) enables the board to act as the system controller. In particular the
command calls VIne-slotl! - passing the value true to it - to enable the system
controller function.
vme-slotl-dis ( - ) disables the board to act as the system controller. In particular the
command calls VIne - s lotl! - passing the value false to it - to disable the system

controller function.
vme-slotl! (true Ifalse - ) enables or disables the board's function to operate as the system controller. When the value true is passed to the command the board acts as the
system controller. Otherwise - the value false is passed to the command - the system controller function is disabled.
vme-arb-mode@ ( - mode) returns the mode the arbiter is currently operating in. The
value of mode may range from zero to three. Each value specifies a particular mode:
the values zero and three indicate that the arbiter is operating in the priority.mode; the
value one specifies the round-robin mode; and the value two specifies the prioritizedround-robin mode.
Three constants are available to specify one of the three bus arbitration modes: pri prioritized - (3 10), rrs - round robin select- (110), prr - prioritized round
robin - (6 10).
vme-arb-mode! (mode - ) selects the arbiter mode specified by mode. The value of mode
may range from zero to three. Each value specifies a particular mode: the values zero
and three indicate that the arbiter operates in the priority mode; the value one specifies
the round-robin mode; and the value two specifies the prioritized-round-robin mode.
vme-arb-irq-map! (mapping - ) selects the interrupt to be geneI\'lted by the arbiter
when the arbitration timeout expired, The parameter mapping defines the interrupt
asserted by the SPARe FGA-5000 when the certain VNlEbus interrupt request level is
asserted. The value of mapping may be one of the values in the range zero through
seven. Each value specifies one of the eight SPARC FGA-5000 interrupt request lines.
The table "Interrupt Mapping." on page 109 lists all allowed mappings.
vme-arb- irq-ena ( - ) enables the interrupt to be generated by the arbiter when the arbitration timeout expired. In particular the command calls vme-arb-irq! - passing
the value true to it - to enable the interrupt.
vme-arb-irq-dis ( - ) disables the interrupt to be generated by the arbiter when the
arbitration timeout expired. In particular the command calls vme-arb- irq!
passing the value false to it - to disable the interrupt.
Page 112

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

vme-arb- irq! (true I false - ) enables or disables the interrupt to be generated by the
arbiter when the arbitration timeout expired. When the value true is passed to the command the interrupt is enabled. Otherwise - the value false is passed to the command
- the interrupt is disabled.
. vsi-arb-ctrl (-) displays the current contents of the V:MEbus Arbiter Control Register.

4.2.6

VMEbus Requester

The commands listed below are available to control the requester and to obtain some
infonnation about the requesters's operational state:

vme-bus-request-level@ (-level) returns the VMEbus request level in use when
the VMEbus interface tries to gain the ownership of the VMEbus. The value of level
may be one of the values in the range one through three. Each value specifies one of
the four VMEbus request levels.
vme-bus-request-level! (level-) selects the bus-request level to be used when the
VMEbus is being accessed. The value of level may be one of the values in the range
one through three. Each value specifies one of the four VMEbus request levels
vme-bus-request-mode@ ( - mode) returns the VMEbus request mode in use when
the VMEbus interface tries to gain the ownership of the VMEbus.
vme-bus-request-mode! (mode - ) selects the bus-request mode to be used when the
VMEbus is being accessed.
Two constants are available to specify one of the two request modes: fair (010) and
unfair (1 10).
vme-bus-release-mode@ ( - mode) returns the VMEbus release mode in use when the
VMEbus interface has gained the ownership of the VMEbus.
vme-bus-release-mode! (mode - ) selects the release mode to be used when the
VMEbus interface has gained the ownership of the VMEbus
Four constants are available to specify one of the four release modes: ror - release
on request - (3 10), roc - release on bus clear - (5 10), rat - release after timeout
- (6 10), and rwd - release when done - (7 10).
Because the SPARe FGA-5000 allows to consider more than one bus release mode
simultaneously - however, the combination of the release modes should be reasonable - the following two examples show how to use the available constants and command to specify the release mode:

FORCE COMPUTERS

Pagell3

SPARe CPU-SV Technical Reference Manual

OpenBoot

ok ror rat and v.me-bus-release-mode!
ok
In this example the VMEbus will be released either when another master requests the
VMEbus, or after a fixed timeout expired. In the example below the VMEbus is
released either when the BBSY* signal is negated, or after a fixed timeout expired.

ok roc rat and v.me-bus-release-mode!
ok

) ~11ows or prevents the requester from releasing
the VMEbus early. When the value true is passed to the command the requester
releases the VMEbus before the cycle has been terminated completely. Otherwise the value false is passed to the command - the requester releases the VMEbus only
when the cycle has been terminated completely.

'vme-early-release! (trJ.J£! false -

vme-bbsy-filter! (true I false - ) enables or disables the BBSY* glitch filter. When
the value true is passed to the command the BBSY* glitch filter is enabled. Otherwise
- the value false is passed to the command - the BBSY* glitch ftIter is disabled.
. vsi-req-ctrl ( -

) displays the current contents of the VMEbus Requester Control

Register.

vme-bus-capture! (true Ifalse - ) enables or disables the bus-capture-and-hold capability of the SPARC FGA-5000. If the value true is passed to the command the VMEbus Interface starts to capture the bus and when it gains the ownership of the bus it
holds the as long as the bus is released. The bus is released when the command is
called and the value false is passed to it.

vme-bus-captured? ( - true Ifalse ) determines whether the VMEbus interface gains
the ownership of the bus. The value true is returned when the VMEbus interface gains
the ownership of the VMEbus. Otherwise the value false is returned to indicated that
the VMEbus interface has not gained the ownership of the bus.
In general this command is called immediately after a capture-and-hold cycle has
been initiated as shown in the example below:

ok true vme-bus-capture!
ok begin vme-bus-captured? until
ok
ok fa1se vme-bus-capture!
ok

Page 114

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

4.2.7

OpenBoot

VMEbus Status Signals

The commands listed below are available to access and control the VMEbus status signals.

vme-sysfail-set (-) asserts (sets) the VMEbus SYSFAIL* signal.
vme-sysfail-clear (-) negates (clears) the VMEbus SYSFAIL* signal.
"vme- sys fail? ( - true Ifalse) determines the state of the VMEbus SYSFAIL* signal and
returns ajlag set according to the signal's state. When the SYSFAIL* signal is asserted
theflag returned is true; otherwise its value isfalse.
vme-sysfail-assert-irq-map! (mapping - ) selects the interrupt to be generated
when the VMEbus SYSFAIL* signal is asserted. The parameter mapping defines the
interrupt asserted by the SPARe FGA-5000 when the SYSFAIL* signal is asserted.
The value of mapping may be one of the values in the range zero through seven. Each
value specifies one of the eight SPARe FGA-5000 interrupt request lines. The table
"Interrupt Mapping." on page 109 lists all allowed mappings.
vme-sysfail-assert-irq-ena ( - ) allows the VMEbus interface to generate an
interrupt upon the assertion of the VMEbus SYSFAIL* signal.
vme-sysfail-assert-irq-dis ( - ) disables the interrupt to be generated upon the
assertion of the VMEbus SYSFAIL* signal.
vme-sysfail-assert-ip? ( - true Ifalse) checks whether an interrupt is pending due
to the assertion of the VMEbus SYSFAIL* signal and returns a flag set according to
the appropriate interrupt pending flag. The flag is true when the interrupt is pending;
otherwise its value is false."
vme-sysfail-assert-ip-clear ( - ) clears a pending interrupt generated by the
assertion of the VMEbus SYSFAIL* signal. This command clears on the corresponding interrupt pending bit in the Interrupt Status Register of the SPARe FGA-5000.
vme-sysfail-negate-irq-map! (mapping - ) selects the interrupt to be generated
when the VMEbus SYSFAIL* signal is negated. The parameter mapping defines the
interrupt asserted by the SPARe FGA-5000 when the SYSFAIL* signal is negated.
The value of mapping may be one of the values in the range zero through seven. Each
value specifies one of the eight SPARe FGA-5000 interrupt request lines. The table
"Interrupt Mapping." on page 109 lists all allowed mappings.
vme-sysfail-negate-irq-ena ( - ) allows the VMEbus interface to generate an
interrupt upon the negation of the VMEbus SYSFAIL* signal.

FORCE COMPUTERS

Page 115

OpenBoot

SPARC CPU-SV Technical Reference Manual

vme-sysfail-negate-irq-dis ( - ) disables the interrupt to be generated upon the
negation of the VIvlEbus SYSFAIL* signal.
vme-sysfail-negate-ip? ( - true Ifalse) checks whether an interrupt is pending due
to the negation of the VIvlEbus SYSFAIL* signal and returns a flag set according to
the appropriate interrupt pending flag. The flag is true when the interrupt is pending;
otherwise its value is false.
vme-sysfail-negate-ip-clear ( - ) clears a pending interrupt generated by the
negation of the VIvlEbus SYSFAIL* signal. This command clears on the correspondin~ --------rlnt~Tnlnt r-------Q
TlP.nciin~ hit
in th~
Tnterrunt ----Stanl~ ---Q----Re~~t~T nfth~
---Q
-------- -------r-- --- ~PARr
------ -Fl1A-,\OOO
--- ----.

vme-acfail? ( - true Ifalse) determines the state of the VMEbus ACFAIL* signal and
returns aflag set according to the signal's state. When the ACFAIL* signal is asserted
the flag returned is true; otherwise it is false.
vme-acfail-assert-irq-map! (mapping - ) selects the interrupt to be generated
when the VMEbus ACFAIL* signal is asserted. The parameter mapping defines the
interrupt asserted by the SPARC FGA-5000 when the ACFAIL* signal is asserted.
The value of mapping may be one of the values in the range zero through seven. Each
value specifies one of the eight SPARC FGA-5000 interrupt request lines. The table
"Interrupt Mapping." on page 109 lists all allowed mappings
vme-acfail-assert-irq-ena (-) allows the VIvlEbus interface to generate an interrupt upon the assertion of the VIvlEbus ACFAIL* signal.
vme-acfail-assert-irq-dis ( - ) disables the interrupt to be generated upon the
assertion of the VIvlEbus ACFAIL* signal.
vme-acfail-assert-ip? ( - true Ifalse ) checks whether an interrupt is pending due
to the assertion of the VIvlEbus ACFAIL* signal and returns ajlag set according to the
appropriate interrupt pending flag. The flag is true when the interrupt is pending; otherwise its value is false.
vme-acfail-assert- ip-clear ( - ) clears a pending interrupt generated by the
assertion of the VIvlEbus ACFAIL* signal. This command clears on the corresponding
interrupt pending bit in the Interrupt Status Register of the SPARe FGA-5000.

Page 116

FORCE COMPUTERS

SPARe CPU-SV Technical Reference Manual

4.2.8

OpenBoot

VMEbus Master Interface

The SPARe FGA-5000 provides 16 sets of registers to control any VMEbus master operation.
Each set may be used to address a certain address range within the VMEbus' address space. A
register set is identified by an unique number, the range number (range#), in the range zero
through 15.
When the VMEbus is being accessed the part of the SPARC FGA-5000 connected with the
SBus is considered as the SBus slave device, whereas the part of the SPARC FGA-5000 that
is connected with the VMEbus is operating as VMEbus master. This fact is reflected in the
names of the commands available to control the VMEbus master interface.
The commands listed and described in the following are available to initialize and control the
VMEbus master interface:

#vme- ranges ( - #vme-ranges ) returns the number #vme-ranges of available register sets
which are used to control accesses to the VMEbus.
vme-master-ena ( range# - ) enables the address decoding associated with the range
number range# to access the VMEbus. The value of range# may be one of the values
in the range zero through 15. Each value specifies one of the 16 register sets controlling any VMEbus master operation.
vme-master-dis ( range# - ) enables the address decoding associated with the range
number range# to access the VMEbus. The value of range# may be one of the values
in the range zero through 15. Each value specifies one of the 16 register sets controlling any VMEbus master operation.
vme-master-wp-ena ( range# - ) enables write posting within the VMEbus address
range associated with the range number range#. The value of range# may be one of
the values in the range zero through 15. Each value specifies one of the 16 register sets
controlling any VMEbus master operation.
vme-slave-wp-dis ( range# - ) disables write posting within the VMEbus address
range associated with the range number range#. The value of range# may be one of
the values in the range zero through 15. Each value specifies one of the 16 register sets
controlling any VMEbus master operation.
VIne-supervisor! (true I false - ) selects the mode in which the VMEbus is being
accessed. When the value true is passed to the command, the VMEbus is accessed in
the previleged mode. Otherwise - the value false is passed to the command - the
VMEbus is accessed in the non-previleged mode.
The mode selected with this command applies to all ranges used to access the VMEbus.
vme-master-cap@ ( range# - data-capability address-capability) returns the addressand data capabilities associated with the range number range# which are used when
FORCE COMPUTERS

Page 117

OpenBoot

SPARC CPU-SV Technical Reference Manual

the VMEbus is accessed. The value of range# may be one of the values in the range
zero through 15. Each value specifies one of the 16 register sets controlling any VMEbus master operation.
The value of data-capability and address-capability may be one of the values listed in
the table below.

vme-master-cap! (data-capability address-capability range#-) defines the addressand data capabilities associated with the range number range# which are used when
the VMEbus is accessed. The value of range# may be one of the values in the range
zero through 15. Each value specifi~s one of the 16 register sets controlling any VMEhn~
--- ma~ter
-------

nnerntinn_
-r--------

The value of data-capability and address-capability may be one of the values listed in
the table below:
value

data-capability address-capability

0002
001 2

cap-d8

cap-a16

cap-d16

cap-a24

0102
011 2

cap-d32

cap-a32

cap-bIt

reserved

1002

cap-mblt

cap-a64

101 2

reserved

reserved

1102

reserved

reserved

1112

reserved

reserved

sbus-slot-sel@ (range#- sbus-slot#) returns the number of the SBus slot sbus-slot#
that is associated with the range identified by range#. The value of range# may be one
of the values in the range zero through 15. Each value specifies one of the 16 register
sets controlling any VMEbus master operation.

sbus-slot-sel! (sbus-slot# range#-) sets the number of the SBus slot sbus-slot#that
is associated with the range identified by range#. The value of range# may be one of
the values in the range zero through 15. Each value specifies one of the 16 register sets
controlling any VMEbus master operation.

sbus-slot#>ssel# ( sbus-slot# - ssel#) converts the logical SBus slot number sbusslotH to the corresponding SBus slave select number ssel#.
s sel #> sbus - s lot# (ssel# - sbus-slot#) converts the SBus slave select number ssel# to
the corresponding logical SBus slot number sbus-slot#.

Page 118

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

/ sbus-range ( range# - size) returns the size of the range associated with the range
number range#. The value of range# may be one of the values in the range zero
through 15. Each value specifies one of the 16 register sets controlling any VMEbus
master operation.

sbus-slave-range@ (range#- offset sbus-slot# size) returns the SBus slave parameters associated with the range identified by range#. The value of range# may be one of
the values in the range zero through 15. Each value specifies one of the 16 register sets
controlling any VMEbus master operation.
The parameters returned by the command specify the SBus address range to be
accessed to reach the VMEbus. The address range is represented by the triple offset,
sbus-slot#, and size.

sbus-slave-range! (offset sbus-slot# size range# - ) sets the SBus slave parameters
associated with the range identified by range#. The value of range# may be one of the
values in the range zero through 15. Each value specifies one of the 16 register sets
controlling any VMEbus master operation.
The parameters passed to the command specify the SBus address range to be accessed
to reach the VMEbus. The address range is represented by the triple offset, sbus-slot#,
and size.

vme-master-range@ ( range# -

addr data-capability address-capability size) returns
the VMEbus master capabilities associated with the range number identified by
range#. The value of range# may be one of the values in the range zero through 15.
Each value specifies one of the 16 register sets controlling any VMEbus master operation.
The VMEbus address range being accessed is represented by the addr-size pair, where
addr specifies the physical VMEbus address and size identifies the address range covered. The value of data-capability and address-capability may be one of the values
listed in the table below.

VIne-master-range! (addr data-capability address-capability size range# -

) sets the
VMEbus master capabilities associated with the range number identified by range#.
The value of range#may be one of the values in the range zero through 15. Each value
specifies one of the 16 register sets controlling any VMEbus master operation.
The VMEbus address range being accessed is represented by the addr-size pair, where
addr specifies the physical VMEbus address and size identifies the address range covered. The value of data-capability and address-capability may be one of the values
listed in the table below.

FORCE COMPUTERS

value

data-capability address-capability

0002

cap-d8

cap-al6

001 2

cap-dl6

cap-a24
Page 119

SPARe CPU-SV Technical Reference Manual

OpenBoot

value

data-capability address-capability

0102
011 2
1002
101 2
1102

cap-d32

cap-a32

cap-bIt

reserved

cap-mblt

cap-a64

reserved

reserved

reserved

reserved

reserved

reserved

1112

· vrne-master-range ( range# - ) displays the current settings of the VMEbus master
interface asociated with the range number range#. The value of range# may be one of
the values in the range zero through 15. Each value specifies one of the 16 register sets
controlling any VMEbus master operation.

· vme-master-ranges ( - ) displays the current settings of all register sets of the VMEbus master interface.

· vrne-cap (-) displays the contents of the VMEbus Capability register.
vme-roaster-map ( range# - vaddr ) makes the physical address range, as defined by the
contents of the range register set specified by the range number rangel, available to
the processor's virtual address space and returns the virtual address vaddr.
Because the command obtains all information from the specific range register set, the
particular range register must be initialized before.

vme-mas ter-unmap ( vaddr range# -

) removes the physical address range, as defined
by the contents of the range register set specified by the range number rangel, from

the processor's virtual address space.

addr, size>sbus-compare-code ( address size - compare-code) returns the SBus
compare-code which corresponds with the given address and size pair.
sbus-compare-code>addr, size (compare-code - address size) converts the SBus
compare-code to the corresponding address and size pair.
The examples on the following pages describe how to initialize the VMEbus interface for
subsequent VMEbus master accesses.
The example below shows how to access a 1 :MByte area within the extended address space
(A32) of the VMEbus beginnig at address 4080.000016 . The register set associated with the
range number zero (range# is 0) is used to access the VMEbus area mentioned above.
The first commands initializes the VMEbus master interface. It sets the data- and address
Page 120

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

capabilities, as well as the VMEbus address and the size of the area being accessed. The data
capability is defined using the predefined constant cap-d3 2 which enables the VMEbus
master interface to access bytes (8bit data), half-words (16bit data), and words (32-bit data)
within the VMEbus area The address capability is defined using the predefined constant capa32 that enables the VMEbus interface to access the extended address space (A32) of the
VMEbus.
The SBus slave interface is initialized by the second command which specifies that the
VNlEbus is accessed when the SBus slot one (1) is being accessed at offsets AO.0000 16 to
BF.FFFF16 which corresponds to the VMEbus addresses in the range 4080.0000 16 to
409F.FFFF16 of the extended address space (A32).
ok hi 4080.0000 cap-d32 cap-a32 1Meg 2 * 0 vms-master-rangel
ok 1Heg dt 10 * 1 1Meg 2 * 0 sbus-slave-rangel
ok 0 v.me-master-eDa
ok 0 vme-master-map value v.mebus

ok

Finally, the third command enables any access to the VMEbus. The fourth command maps the
physical address area to be accessed in order to address the VNlEbus to the virtual address
space of the processor and stores the virtual address in the variable vmebus. This variable may
be used to access the VNlEbus area using the commands to read and write data provided by
OpenBoot.
ok vmebus 0 vme-master-umDap
ok

When the translation (SBus to VMEbus) defined by the contents of the register set associated
with the range number zero is no longer used, then the memory mapped to the processor's
virtual address space to access the VMEbus must be released before the contents of this
register set are modified. This has to be done with the command vme-master-unmap as
stated above.
.

In the next example the VMEbus interface is initialized to allow accesses to the standard
address space (A24) of the VMEbus beginnig at address 98.000016 • The size of this area is
512KByte and the register set associated with the range number one (range# is 1) is used to
access this VMEbus area.
The first commands initializes the VMEbus master interface. It sets the data- and address
capabilities, as well as the VMEbus address and the size of the area being accessed. The data
capability is defined using the predefined constant cap-d16 which enables the VMEbus
master interface to access bytes (8bit data), and half-words (16bit data) within the VMEbus
area The address capability is defined using the predefined constant cap-a24 that enables
the VMEbus interface to access the standard address space (A24) of the VNlEbus.
The SBus slave interface is initialized by the second command which specifies that the
VMEbus is accessed when the SBus slot one (1) is being accessed at offsets 120.000016 to
127.FFFF16 which corresponds to the VMEbus addresses in the range 98.000016 to 9F.FFFF16
of the standard address space (A24).

FORCE COMPUTERS

Page 121

OpenBoot

ok
ok
ok
ok
ok

SPARe CPU-SV Technical Reference Manual

hi 98.0000 cap-d16 cap-a24 !Meg 2 I 1 v.me-master-range!
1Meg dl 18 * 2 1Heg 2 I 1 sbus-slave-rangel
1 vme-master-ena
1 vme-master-map value vmebas

Finally, the third command enables any access to the VMEbus. The fourth command maps the
physical address area to be accessed in order to address the VMEbus to the virtual address
space of the processor and stores the virtual address in the variable vmebus. This variable may
be used to access the VMEbus area using the commands to read and write data provided by
OpenBoot
ok 1 vme-master-map value vmebus
ok

When the translation (SBus to VMEbus) defined by the contents of the register set associated
with the range number zero is no longer used, then the memory mapped to the processor's
virtual address space to access the VMEbus must be released before the contents of this
register set are modified. This has to be done with the command vme-master-unmap as
stated above.
The last example describes how to initialized the VMEbus interface to allow accesses to the
short address space (A16) of the VMEbus beginnig at address 000016 . The size of this area is
64KByte and therefore covers the entired short address space. The register set associated with
the range number two (range# is 2) is used to access this VMEbus area
Again, the first commands initializes the VMEbus master interface. It sets the data- and address
capabilities, as well as the VMEbus address and the size of the area being accessed. The data
capability is defined using the predefined constant cap-dB which limits the VMEbus master
interface to access only bytes (8bit data) within the VMEbus area. The address capability is
defined using the predefined constant cap-a16 that enables the VMEbus interface to access
the standard address space (A16) of the VMEbus.
The SBus slave interface is initialized by the second command which specifies that the
VMEbus is accessed when the SBus slot one (1) is being accessed at offsets 400.0000 16 to
4OO.FFFF16 which corresponds to the VMEbus addresses in the range 0000 16 to FFFF16 of the
short address space (A16).
'
ok
ok
ok
ok
ok

hi 0000 cap-d8 cap-a16 hi 1.0000 2 v.me-master-rangel
1Heg dl 64 * 3 hi 1.0000 2 sbus-slave-rangel
2 v.me-master-8D&
2 v.me-master-map value vmebas

Finally, the third command enables any access to the VMEbus. The fourth command maps the
physical address area to be accessed in order to address the VMEbus to the virtual address
space of the processor and stores the virtual address in the variable vmebus. This variable may
be used to access the VMEbus area using the commands to read and write data provided by
OpenBoot.
Page 122

FORCE COMPUTERS

SPARC CPU-5V Technical Reference Manual

OpenBoot

ok 2 v.me-master-map value v.mebus
ok

When the translation (SBus to VMEbus) defined by the contents of the register set associated
with the range number zero is no longer used, then the memory mapped to the processor's
virtual address space to access the VMEbus must be released before the contents of this
register set are modified. This has to be done with the command vme-master-unmap as
stated above.
Assumed the first three register sets have been used to access the VMEbus address spaces as
described in the examples above, then the following command may be used to display the
settings of the registers sets:
ok .v.me-master-ranges

FORCE COMPUTERS

Page 123

SPARC CPU-5V Technical Reference Manual

OpenBoot

The following commands are available to control the various operating modes of the SPARC
FGA-5000 SBus interface.

sbus - burs t -length@ ( - #burst-lenght ) returns the maximum length of an SBus burst
that is generated by the SPARC FGA-5000. The value of#burst-Iength is in the range
zero through three. Each value specifies one of four possible burst lengths as stated in
the table below.
sbus - burs t -length! (#burst-Ienght - ) sets the maximum length of an SBus burst that
is generated by the SPARC FGA-5000. The value of #burst-Iength may be in the range
zero through three. Each value specifies one of four possible burst lengths as stated in
the table below. The command considers only the least significant two bits of the value
#burst-Iength.
#burst-length

Burst Length

0

8-byte burst

1

16-byte burst

2

32-byte burst

3

64-byte burst

sbus-master-read-stop-point@ ( - #read-stop-point ) returns the SBus master
read stop point currently in effect. The value of #read-stop-point is in the range zero
through three. Each value specifies one of four possible read stop points as stated in
the table below.
sbus-master-read-stop-point! (#read-stop-point - ) sets the SBus master read
stop point used by the SPARC FGA-5000. The value of #read-stop-point may be in the
range zero through three. Each value specifies one of four possible read stop points as
stated in the table below. The command considers only the least significant two bits of
the value #read-stop-point.
#read-stop-point

Page 124

Read Stop Point

0

Stop at 8-byte boundary

1

Stop at 16-byte boundary

2

Stop at 32-byte boundary

3

Stop at 64-byte boundary

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

sbus-retry-time@ ( - #retry-time) returns the number of SBus clocks before an SBus
cycle is terminated with a retry by the SPARe FGA-5000. The value of #retry-time is
in the range zero through 255 and specifies the number of SBus clocks.
sbus-retry-time! (#retry-time - ) sets the number of SBus clocks before an SBus
cycle is terminated with a retry by the SPARe FGA-5000. The value of #retry-time
may be in the range zero through 255 and specifies the number of SBus clocks. The
command treats the value of #retry-time as a modulo 256 number.
When the command is called it verifies whether the given number of SBus clocks falls
below the limit specified by min-retry-time. If this value falls below the given
limit, then the commands uses the value of min-retry-time instead. This ensures
L~at the SBus interface is operating properly_
sbus-rerun! (true IfaIse ) enables or disables the SPARe FGA-5000's capability to generate reruns on the SBus. When the value true is passed to the command the SPARe
FGA-5000 will initiate SBus rerun if necessary. Otherwise - the value false is passed
to the command - the SPARe FGA-5000's capability to initiate SBus reruns is disabled.
sbus-rerun-ena ( - ) enables the SPARe FGA-5000's capability to generate reruns on
the SBus.
sbus-rerun-dis (-) disables the SPARe FGA-5000's capability to generate reruns on
the SBus.
sbus-rerun -1 imi t@ ( - #rerun-limit ) returns the number of reruns before the SPARe
FGA-5000 terminates an SBus cycle with an error. The value of #rerun-limit is in the
range zero through 255 and specifies the number of reruns.
sbus-rerun-1imit! (#rerun-limit - ) sets the number of reruns before the SPARe
FGA-5000 terminates an SBus cycle with an error. The value of #rerun-limit may be
in the range zero through 255 and specifies the number of reruns. The command treats
the value of #rerun-limit as a modulo 256 number.
When the command is called it verifies whether the given number of reruns falls below
the limit specified by min-rerun-limit. If this value falls below the given limit,
then the commands use the value of min -rerun-limi t instead. This ensures that
the SBus interface is operating properly.
sbus-burst-ena ( - ) enables the SPARe FGA-5000's capability to transfer data using
SBus burst transfers.
sbus-burst-dis (-) disables the SPARe FGA-5000's capability to transfer data using
SBus burst transfers.

FORCE COMPUTERS

Page 125

OpenBoot

SPARC CPU-SV Technical Reference Manual

sbus-hidden-arb-ena (-) enables the SPARe FGA-5000's capability to perfonn hidden arbitration.
sbus-hidden-arb-dis ( - ) disables the SPARe FGA-5000's capability to perform
hidden arbitration.
sbus-spli t-flow-ena (-) enables split fIowthrough.
sbus-split-flow-dis (-) disables split fIowthrough.
sbus-spli t-ena (-) enables the SPARe FGA-5000's capability to split SBus cycles.
sbus-spli t-dis (-) disables the SPARe FGA-5000's capability to split SBus cycles.
· sbus - cap ( - ) displays the current contents of the SBus Master Capability Register as
shown below:
ok .sbus-cap
Split: 1
Split Flow: 1
Arbiter: 1
Burst: 1
Master Read Stop Point: 32 bytes Max. Burst Length: 32 bytes

ok

· sbus-retry-time-ctrl ( - ) displays the current contents of the SPARe FGA5000' s SBus Retry Time Control Register as stated below:

ok

.sbus-ret~-time-ctrl

Retry time: 10

ok
· sbus-rerun-limit-ctrl ( - ) displays the current contents of the SBus Rerun Limit
Control Register as depicted below:

ok

~sbus-rerun-limit-ctrl

Enable Reruns: 0

Rerun limit: 255

ok

Page 126

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

4.2.9

OpenBoot

VMEbus Slave Interface

The SPARC FGA-5000 provides three sets of registers to control any VMEbus slave access.
Each set may be used to make a certain slave address range - standard- (A24) or extended
(A32) slave address range - available to the VMEbus' address space. A register set is
identified by a unique number, the range number (range#), in the range zero through two.
Only the A24 and A32 slave mode allows a VMEbus master to access the memory of the
SPARe CPU-5V. In the A16 slave mode all VMEbus master accesses are limited to the
registers of the SPARe FGA-5000 which are accessible from the VMEbus.
When the ~bus interface is being accessed from the ~bus, then the part of the SPARC
FGA-5000 connected with the VMEbus is considered as VMEbus slave device. Whereas the
part of the SPARC FGA-5000 that is connected with the SBus is operating as the SBus master.
This fact is reflected in the names of the commands available to control the VMEbus master
interface.
The commandS listed and described in the following are available to initialize and control the
A16 ~bus slave interface:

vme-a16-s1ave-ena (-) enables the capability to access the SPARe FGA-5000 registers from the VMEbus in the short address space (A 16).
vme-a16-s1ave-dis (-) disables the capability to access the SPARe FGA-5000 registers from the ~bus in the short address space (A16).
vme-a16-s1ave-addr@ ( - addr) returns the 16-bit address addr at which the registers
of the SPARC FGA-5000 are accessible within the short address space (A16).
vme-a16-s1ave-addr! (addr-) defines the 16-bit address addr at which the registers
of the SPARe FGA-5000 are accessible within the short address space (A16).
The least significant nine bits of the address addr are ignored by the command - the
command treats them as if they are cleared - , because the SPARe FGA-5000 is only
accessible from the ~bus beginning at 512 Byte boundaries.
The commands listed and described in the following are available to initialize and control the
A24 and A32 ~bus slave interface:

vme-slave-ena ( range# - ) enables the address decoding associated with the range
number range# to allow accesses from the ~bus. The value of range# may be one
of the values in the range zero through two. Each value specifies one of the three register sets controlling any VMEbus slave access.
vme-slave-dis ( range# - ) disables the address decoding associated with the range
number range# to allow accesses from the ~bus. The value of range# may be one
of the values in the range zero through two. Each value specifies one of the three register sets controlling any ~bus slave access.
FORCE COMPUTERS

Page 127

OpenBoot

SPARC CPU-SV Technical Reference Manual

vrne-slave-wp-ena (range#-) enables write posting within the VMEbus slave address
range associated with the range number range#. The value of range# may be one of
the values in the range zero through two. Each value specifies one of the three register
sets controlling any VMEbus slave access.
vme-slave-wp-dis ( range#-) disables write posting within the VMEbus slave address
range associated with the range number range#. The value of range# may be one of
the values in the range zero through two. Each value specifies one of the three register
sets controlling any VMEbus slave access.
/,\7!ne-a24-r~1'lge

( Tange#- size) returns the size of the standard (A24) slave interface
associated with the range number range#. The value of range# may be one of the val-

ues in the range zero through two. Each value specifies one of the three register sets
controlling any VMEbus slave access.

sbus-a24-master-range@ (range#- vaddr size) returns the SBus master parameters
associated with the A24 slave interface identified by range#. The value of range# may
be one of the values in the range zero through two. Each value specifies one of the
three register sets controlling any VMEbus slave access.
The parameters vaddr and size identify the virtual address range within the SBus, into
which all A24 slave accesses are translated.
sbus-a24-master-range! (vaddr size range#-) defmes the SBus master parameters
associated with the A24 slave interface identified by range#. The value of range# may
be one of the values in the range zero through two. Each value specifies one of the
three register sets controlling any VMEbus slave access.
The parameters vaddr and size identify the virtual address range within the SBus, into
which all A24 slave accesses are translated.
vme-a24-s1ave-range@ ( range# - paddr size) returns the VMEbus base address
paddr and the size size of the A24 slave window associated with the range identified
by range#. The value of range# may be one of the values in the range zero through
two. Each value specifies one of the three register sets controlling any VMEbus slave
access.
vme-a24-s1ave-range! (paddr size range#-) sets the VMEbus base address paddr
and the size size of the A24 slave window associated with the range identified by
range#. The value of range# may be one of the values in the range zero through two.
Each value specifies one of the three register sets controlling any VMEbus slave
access.

Page 128

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

/vme-a32-range ( range#- size) returns the size of the extended (A32) slave interface
associated with the range number range#. The value of range# may be one of the values in the range zero through two. Each value specifies one of the three register sets
controlling any VMEbus slave access.
sbus-a32-master-range@ (range#- vaddr size) returns the SBus master parameters
associated with the A32 slave interface identified by range#. The value of range# may
be one of the values in the range zero through two. Each value specifies one of the
three register sets controlling any VMEbus slave access.
The parameters vaddr and size identify the virtual address range within the SBus, into
which all A32 slave accesses are translated.
sbus-a32-master-range! (vaddrsize range#-) defines the SBus master parameters
associated with the A32 slave interface identified by range#. The value of range# may
be one of the values in the range zero through two. Each value specifies one of the
three register sets controlling any VMEbus slave access.
The parameters vaddr and size identify the virtual address range within the SBus, into
which all A32 slave accesses are translated.
vme-a32-s1ave-range@ ( range# - paddr size) returns the VMEbus base address
paddr and the size size of the A32 slave window associated with the range identified
by range#. The value of range# may be one of the values in the range zero through
two. Each value specifies one of the three register sets controlling any VMEbus slave
access.
vme-a32-s1ave-range! (paddrsize range#-) sets the VMEbus base addresspaddr
and the size size of the A32 slave window associated with the range identified by
range#. The value of range# may be one of the values in the range zero through two.
Each value specifies one of the three register sets controlling any VMEbus slave
access .
. vme-slave-range (range#-) displays the current settings of the VMEbus slave interface associated with the range number range#. The value of range# may be one of the
values in the range zero through two. Each value specifies one of the three register sets
controlling any VMEbus slave access .
. vme-slave-ranges (-) displays the current settings of all register sets controlling any
VMEbus slave access.
addr size>vme-compare-code (address size - compare-code) returns the VMEbus
compare-code which corresponds with the given address and size pair.
I

vme-compare-code>addr size ( compare-code - address size) converts the VMEbus compare-code to the corresponding address and size pair.
I

FORCE COMPUTERS

Page 129

OpenBoot

SPARC CPU-SV Teclmica1 Reference Manual

The following example lists all steps to be taken, to initialize the V1v.IEbus interface for A32
accesses from the V1v.IEbus beginning at address 2340.0000 16 and ranging to 235F.FFFF16 .
The register set associated with the range number zero (0) is used to control this particular
VMEbus slave interface.

ok hi 2340.0000 ~eg 2 * 0 vae-a32-s1ave-range!
ok hi ££eO.OOOO ~eg 2 * 0 sbus-a32-master-range!
ok hi 10.0000 obmem hi f£eO.OOOO ~eg 2 * iamap-pages
ok a v.me-slave-ena
ok
As shown above the first command defines the V1v.IEbus slave interface's base address and size
of the slave window. The second command defines that any A32 access is translated to an
access of the SBus beginning at SBus address FFEO.000016 . And the third command creates
all necessary entries within'the IOMMU to translate the SBus access to an access of the
on-board memory beginning at physical address 10.000016 .
Finally, the VMEbus slave interface is enabled using the fourth command.
The next example lists all steps to be taken, to initialize the VMEbus interface for A24 accesses
from the VMEbus beginning at address CO.OOOO I6 and ranging to CF.FFFF I6 . The register set
associated with the range number one (1) is used to control this particular V1v.IEbus slave
interface.

ok
ok
ok
ok
ok

hi cO.OOOO 1Heg 1 v.me-a24-s1ave-range!
hi fffO.OOOO ~eg 1 sbus-a24-master-range!
hi 20.0000 obmem hi f£fO.OOOO ~eg iamap-pages
1 vme-slave-ena

As shown above the first command defines the V1v.IEbus slave interface's base address and size
of the slave window. The second command defines that any A24 access is translated to an
access of the SBus beginning at SBus address FFFO.OOOO16 . And the third command creates
all necessary entries within the IOMMU to translate the SBus access to an access of the
on-board memory beginning at physical address 20.000016 .
Finally, the V1v.IEbus slave interface is enabled using the fourth command.

Page 130

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

4.2.10

OpenBoot

VMEbus Device Node

The OpenBoot device tree contains the device node for the VMEbus interface and is called
''V!m''. It is a child device of the device node" I iommu" (The full patbname of the VMEbus
interface device node is displayed by the command show-devs). The device alias vme is
available as a shorthand representation of the VMEbus interface device-path.
The vocabulary of the VMEbus device includes the standard commands recommended for a
hierarchical device. The words of this vocabulary are only available when the VMEbus device
has been selected as shown below:

ok cd vme
ok words
self test

reset

close

open ...

... list offurther methods of the device node

ok self test •

o

ok device-end
ok
The example listed above, selects the VMEbus device and makes it the current node. The word

words displays the names of the methods of the VMEbus device. And the third command calls
the method self test and the value returned by this method is displayed. The last command
unselects the current device node, leaving no node selected.
The following methods are defined in the vocabulary of the VMEbus device:

open ( - true ) prepares the package for subsequent use. The value true is always returned.
c lose ( - ) frees all resources allocated by open.
reset (-) puts the VMEbus Interface into quiet state.
sel f tes t ( -

error-number ) performs a test of the VMEbus interface, and returns an
error-number to report the course of the tes~. In the case that the device has been tested
successfully the value zero is returned; otherwise it returns a specific error number to
indicate a certain fail state.

decode-uni t (addr len - low high) converts the addr and len, a text string representation, to low and high which is a numerical representation of a physical address within
the address space defined by the package.
map- in (low high size - vaddr ) creates a mapping associating the range of physical
address beginning at low, extending for size bytes, within the package's physical
address space, with a processor virtual address vaddr.

FORCE COMPUTERS

Page 131

OpenBoot

SPARe CPU-SV Technical Reference Manual

map-out ( vaddr size - ) destroys the mapping set by map-in at the given virtual address
vaddr of length size.
dma-alloc (size - vaddr) allocates a virtual address range of length size bytes that is suitable for direct memory access by a bus master device. The memory is allocated
according to the most stringent alignment requirements for the bus. The address of the
acquired virtual memory vaddr is returned via the stack.
dma-free ( vaddr size - ) releases a given virtual memory, identified by its address vaddr
and size, previously acquired by dma-alloc.
dma -map- in ( vaddr size cachable? - devaddr ) converts a given virtual address range,
specified by vaddr and size, into an address devaddr suitable for direct memory access
on the bus. The virtual memory must be allocated already by dma-alloc. The
SPARe CPU-SV does not support caching. Thus the cachable? flag is ignored.
dma-map-out (vaddr devaddr size - ) removes the direct memory access mapping previously created by dma -map- in.
dma - sync (vaddr devaddr size - ) synchronizes memory caches associated with a given
direct memory access mapping, specified by its virtual address vaddr, the devaddr and
its size that has been established by dma-map-in.

Page 132

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

4.2.11

OpenBoot

VMEbus NVRAM Configuration Parameters

The NVRAM configuration parameters listed below are available to control the initialisation
and operation of the VMEbus Interlace. The current state of these configuration parameters are
displayed using the printenv command, and are modified using either the setenv, or the
set -defaul t command provided by OpenBoot.

vme-sysfail-clear? when the value of the configuration parameter is true the SYSFAIL* signal will be cleared by OpenBoot. In the case that the configuration parameter is false OpenBoot will not clear the SYSFAIL* signal, but the operating system
which is loaded has to clear it. (default: true)
The state of this NVRAM configuration parameter is considered independent of the
state of the vme- ini t? configuration parameter.
vme-bus-timer? controls whether the VMEbus transaction timer in the SPARC FGA5000 is used to watch each VMEbus access. When the flag is true the transaction
timer is enabled. If the flag is false the transaction timer is disabled. (default: true)
The state of this NVRAM configuration parameter is considered independent of the
state of the vrne- ini t? configuration parameter.
vme-bus - timeou t contains the timeout value of the SPARC FGA-5000 VMEbus transaction timer and is a value in the range one to three. Each 'value selects a particular timeout period. Independent of the state of the configuration parameter vme-bustimer? the timeout value is stored in the appropriate register. When the value of this
configuration parameter is not in the range one through three, then the value three is
used instead. (default: 3 10)
The state of this NVRAM configuration parameter is considered independent of the
state of the vme- ini t? configuration parameter.
vme-slot# specifies the logical VMEbus slot number assigned to the SPARC CPU-5V
board. The value may be in the range one through 255, but preferably should be set in
such a way that it corresponds with the number of an available VMEbus slot.
The state of this configuration parameter does not control whether the VMEbus interface is operating as system controller when the configuration parameter's value is one.
(default: 1} 0)
vme- fair- req? specifies whether the VMEbus requester operates in the fair mode when
requesting the VMEbus. When the value of the configuration parameter is true, the
VMEbus requester operates in the fair mode. Otherwise - the value of the configuration parameter is false - the requester does not operate not in the fair mode.
(default: true)

FORCE COMPUTERS

Page 133

OpenBoot

SPARC CPU-SV Technical Reference Manual

vrne- ini t? controls whether the VMEbus interface is initialized by OpenBoot. When this
flag is true the VMEbus interface is initialized according to the state of the NVRAM
parameter listed below. In the case that the flag is false the VMEbus interface is not
initialized. The VMEbus interrace is initialized after OpenBoot set up the main memory. (default: true)
The state of the NVRAM configuration parameters listed in the following are only considered
by OpenBoot when the configuration parameter vme- ini t? is true!
vme - in tr 1 controls whether the VMEbus interrupt request level 1 has to be enabled. When
the value is 255 then the VMEbus interrupt request level 1 is not enabled. In the case
that the value is within the range one to seven, the corresponding interrupt handler is
activated and the VMEbus interrupt request level 1 is enabled. The values one to seven
specify the SPARC FGA-5000 interrupt request line to be asserted when a VMEbus
interrupt request level 1 occurs. (default: 255 10 )
vme- in tr2 controls whether the VMEbus interrupt request level 2 has to be enabled. When

the value is 255 then the VMEbus interrupt request level 2 is not enabled. In the case
that the value is within the range one to seven, the corresponding interrupt handler is
activated and the VMEbus interrupt request level 2 is enabled. The values one to seven
specify the SPARe FGA-5000 interrupt request line to be asserted when a VMEbus
interrupt request level 2 occurs. (default: 255 10 )
vme-intr3 controls whether the VMEbus interrupt request level 3 has to be enabled. When
the value is 255 then the VMEbus interrupt request level 3 is not enabled. In the case
that the value is within the range one to seven, the corresponding interrupt handler is
activated and the VMEbus interrupt request level 3 is enabled. The values one to seven
specify the SPARe FGA-5000 interrupt request line to be asserted when a VMEbus
interrupt request level 3 occurs. (default: 255}0)
vme- in tr4 controls whether the VMEbus interrupt request level 4 has to be enabled. When

the value is 255 then the VMEbus interrupt request level 4 is not enabled. In the case
that the value is within the range one to seven, the corresponding interrupt handler is
activated and the VMEbus interrupt request level 4 is enabled. The values one to seven
specify the SPARC FGA-5000 interrupt request line to be asserted when a VMEbus
interrupt request level 4 occurs. (default: 255 10 )
vme- intr5 controls whether the VMEbus interrupt request level 5 has to be enabled. When
the value is 255 then the VMEbus interrupt request level 5 is not enabled. In the case
that the value is within the range one to seven, the corresponding interrupt handler is
activated and the VMEbus interrupt request level 5 is enabled. The values one to seven
specify the SPARe FGA-5000 interrupt request line to be asserted when a VMEbus
interrupt request level 5 occurs. (default: 25 5 10 )

Page 134

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

vme- in tr6 controls whether the VMEbus interrupt request level 6 has to be enabled. When
the value is 255 then the VMEbus interrupt request level 6 is not enabled. In the case
that the value is within the range one to seven, the corresponding interrupt handler is
activated and the VMEbus interrupt request level 6 is enabled. The values one to seven
specify the SPARC FGA-5000 interrupt request line to be asserted when a VMEbus
interrupt request level 6 occurs. (default: 255 10 )
vme- in tr7 controls whether the VMEbus interrupt request level 7 has to be enabled. When
the value is 255 then the VMEbus interrupt request level 7 is not enabled. In the case
that the value is within the range one to seven, the corresponding interrupt handler is
activated and the VMEbus interrupt request level 7 is enabled. The values one to seven
specify the SPARe FGA-5000 interrupt request line to be asserted when a VMEbus
interrupt request level 7 occurs. (default: 255 10 )
vme-sysfail-assert? controls whether a nonmaskable interrupt is generated upon the
assertion of the VMEbus signal SYSFAIL*. When the flag is true an interrupt handler, dealing with this interrupt, is installed and the ability to generate a nonmaskable
·interrupt upon the assertion of the SYSFAll.,* signal is enabled. In the case that the
flag is false the ability to generate a nonmaskable interrupt upon the assertion of the
SYSFAll....* signal is enabled. (default: false)
vme-sysfail-negate? controls whether a nonmaskable interrupt is generated upon the
negation of the VMEbus signal SYSFAIL*. When the flag is true an interrupt handler, dealing with this interrupt, is installed and the ability to generate a nonmaskable
interrupt upon the negation of the SYSFAIL* signal is enabled. In the case that the flag
is false the ability to generate a nonmaskable interrupt upon the negation of the
SYSFAll....* signal is enabled. (default: false)
vme-acfail-assert? controls whether a nonmaskable interrupt is generated upon the
assertion of the VMEbus signal ACFAIL*. When the flag is true an interrupt handler, dealing with this interrupt, is installed and the ability to generate a nonmaskable
interrupt upon the assertion of the ACFAIL* signal is enabled. In the case that the flag
is false the ability to generate a nonmaskable interrupt upon the assertion of the
ACFAll....* signal is enabled. (default: false)
vme-ibox-addr the least significant 16 bits of this 32-bit configuration parameter define
the address at which the interrupt box (!BOX) of the SPARC FGA-5000 is accessible
within the short address space (AI6). Only the least significant 16 bits of this configuration parameter are considered, and the state of the remaining bits is ignored. Independent of the configuration parameter vme- ibox-ena? OpenBoot will set the
address of the mox. (default: 016)
vme- ibox-ena? indicates whether the interrupt box (mOX), accessible in the short (AI6)
address range of the VMEbus, should be enabled. When this NVRAM configuration
parameter is true then the mox is enabled. In the case that the NVRAM configuraFORCE COl\'lPUTERS

Page 135

OpeuBoot

SPARe CPU-SV Technical Reference Manual

tion parameter is false the mox is not enabled.
The default value of this NVRAM configuration parameter is false.

fmb- ini t? controls whether the FMB system is initialized by OpenBoot When this flag is
true the FMB system is initialized according to the state of the NVRAM parameter
listed below. In the case that the flag is false the FMB system is not initialized. The
FMB system is initialized only during the initialization of the VMEbus interface,
which means that the vme- ini t? configuration parameter must be true, in order to
set up the FMB system. (default: true)
;=mh-~l nt-:i ~.r.ifie~ the Inuirnl ~lot nnmheT ::I~~icmeii to the FMR ~h~n~l~ nf thp. .c;:PARr
------ - .. -r------- --- --0---- ---- --------- ---0---- -- --- -_ . - ----..--- _. . _. - .............. ,"'"'"

CPU-5V board. The value may be in the range one through 21, and preferably should
be set in such a way that it corresponds with the number of an available VMEbus slot.
(default: 1 10)

fmb-addr specifies the address - the most significant eight bits of a 32-bit address where the FMB system resides in the extended address space (A32) of the VMEbus.
(default: fa 16)

The NVRAM configuration parameters listed below are associated with the slave interface
accessible in the short (AI6) address range.

vme-a16-slave-addr specifies the base address of the slave interrace accessible in the
short (AI6) address range of the VMEbus.
The default value of this 32-bit NVRAM configuration parameter is zero (0).
vme-a16-s1ave-size specifies the size of the memory which is made available to the
short (AI6) address range of the VMEbus. When the value of this configuration
parameter is zero OpenBoot will not initialize the slave interrace, even if the vmea16 - s lave-ena ? configuration parameter is true!
The default value of this 32-bit NVRAM configuration parameter is zero (0).
vme-a16-s1ave-ena? indicates whether the slave interface, accessible in the short (A16)
address range of the VMEbus, should be enabled. When this NVRAM configuration
parameter is true then the VMEbus slave interface is enabled. In the case that the
NVRAM configuration parameter is false the VMEbus slave interrace is not enabled, and any attempt to access the VMEbus slave interface from the VMEbus will
lead to an error termination on the VMEbus.
The default value of this NVRAM configuration parameter is false.

In the case that the NVRAM configuration parameter vme- ini t? is true and the OpenBoot
will initialize the slave interface according to the configuration parameters described above.
When the vme-a16-s1ave-ena? configuration parameter is true, then OpenBoot will
Page 136

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

initialize the VMEbus slave interface according to the NVRAM configuration parameters
vme-a16-slave-addr and vme-a16-slave-size. It will provide the required
amount of physical on-board memory and builds up the necessary MMU and IOMMU settings
to make the memory available to the VMEbus. The virtual base address of the physical
on-board memory provided for VMEbus slave accesses is stored in the variable vme-a16slave-mem.
Thus, applications executed within the OpenBoot environment may benefit from this
mechanism, because OpenBoot will initialize the slave interface completely according to the
NVRAM configuration parameters associated with the slave interface.
In addition, this mechanism allows to report the parameters of the slave interface to an
operating system loaded, which in turn provides its own memory and the corresponding MMU
and IOMMU settings. In this case the VMEbus device driver is responsible for the access to
the slave interface from the VMEbus. In general, the configuration parameter vme-a16slave-ena? must be set to false to prevent OpenBoot from initialising and enabling the
slave interface when an operating system will be loaded. Supposed that the slave interface is
initialized and enabled by OpenBoot prior to loading the operating system, any access from the
VMEbus to the slave interface while loading the operating system may alter memory and cause
severe damage.

Note! The SPARC CPU-5V does not provide the ability to access its on-board memory from
the VMEbus within the short (A16) address range. Therefore, the NVRAM configuration
parameters associated with the A 16 slave interface, control the access to the registers of the
SPARC FGA-5000, which are accessible within the short address range. The configuration
parameter vme-a16-slave-size is not of any importance and will be ignored.
The NVRAM configuration parameters listed below are associated with the slave interface
accessible in the standard (A24) address range.
vme-a24-slave-addr specifies the base address of the slave interface accessible in the
standard (A24) address range of the VMEbus.
The default value of this 32-bit NVRAM configuration parameter is zero (0).
vme-a24-s1ave-size specifies the size of the memory which is made available to the
standard (A24) address range of the VMEbus. When the value of this configuration
parameter is zero OpenBoot will not initialize the slave interface, even if the vmea24-s1ave-ena? configuration parameter is true!
The default value of this 32-bit NVRAM configuration parameter is zero (0).
vme-a24-s1ave-ena? indicates whether the slave interface, accessible in the standard
(A24) address range of the VMEbus, should be enabled. When this NVRAM configuration parameter is true then the VMEbus slave interface is enabled. In the case that
the NVRAM configuration parameter is false the VMEbus slave interface is not
enabled, and any attempt to access the VMEbus slave interface from the VMEbus will
lead to an error termination on the VMEbus.
The default value of this NVRAM configuration parameter is false.
FORCE COMPUTERS

Page 137

OpenBoot

SPARC CPU-SV Technical Reference Manual

In the case that the NVRAM configuration parameter vme- ini t ? is true and the OpenBoot
will initialize the slave interface according to the configuration parameters described above.
When the vme-a24-slave-ena? configuration parameter is true, then OpenBoot will
initialize the VMEbus slave interface according to the NVRAM configuration parameters
vme-a24-slave-addr and vme-a24-slave-size. It will provide the required
amount of physical on-board memory and builds up the necessary MMU and IOMMU settings
to make the memory available to the VMEbus. The virtual base address of the physical
on-board memory provided for VMEbus slave accesses is stored in the variable vme-a24slave-mem.
Thus, applications executed within the OpenBoot environment may benefit from this
mechanism, because OpenBoot will initialize the slave interface completely according to the
N-VRAM configuration parameters associated with the siave interface.

In addition, this mechanism allows to report the parameters of the slave interface to an
operating system loaded, which in turn provides its own memory and the corresponding
IOMMU settings. In this case the VMEbus device driver is responsible for the access to the
slave interface from the VMEbus. In general, the configuration parameter vme-a2 4 - s l~ve­
ena? must be set to false to prevent OpenBoot from initialising and enabling the slave
interface when an operating system will be loaded. Supposed that the slave interface is
initialized and enabled by OpenBoot prior to loading the operating system, any access from the
VMEbus to the slave interface while loading the operating system may alter memory and cause
severe damage.
The NVRAM configuration parameters listed below are associated with the slave interface
accessible in the extended (A32) address range.

vme-a32-slave-addr specifies the base address of the slave interface accessible in the
extended (A32 address range of the VMEbus.
The default value of this 32-bit NVRAM configuration parameter is zero (0).
vme-a32-slave-size specifies the size of the memory which is made available to the
extended (A32) address range of the VMEbus. When the value of this configuration
parameter is zero OpenBoot will not initialize the slave interface, even if the vmea24-slave-ena? configuration parameter is true!
The default value of this 32-bit NVRAM configuration parameter is zero (0).
vme-a3 2 -slave-ena? indicates whether the slave interface, accessible in the extended
(A32) address range of the VMEbus, should be enabled. When this NVRAM configuration parameter is true then the VMEbus slave interface is enabled. In the case that
the NVRAM configuration parameter is false the VMEbus slave interface is not
enabled, and any attempt to access the VMEbus slave interface from the VMEbus will
lead to an error termination on the VMEbus.
The default value of this NVRAM configuration parameter is false.

In the case that the NVRAM configuration parameter vme- ini t ? is true and the OpenBoot
Page 138

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

will initialize the slave interface according to the configuration parameters described above.
When the vme-a32-slave-ena? configuration parameter is true, then OpenBoot will
initialize the V1v1Ebus slave interface according to the NVRAM configuration parameters
vme-a16-slave-addr and vme-a32-slave-size. It will provide the required
amount of physical on-board memory and builds up the necessary MMU and IOMMU settings
to make the memory available to the V1v1Ebus. The virtual base address of the physical onboard
memory provided for VMEbus slave accesses is stored in the variable vrne-a32-slavemem.

Thus, applications executed within the OpenBoot environment may benefit from this
mechanism, because OpenBoot will initialize the slave interface completely according to the
NVRAM configuration parameters associated with the slave interface.

In addition, this mechanism allows to report the parameters of the slave interface to an
operating system loaded, which in tum provides its own memory and the corresponding
IOMMU settings. In this case the VMEbus device driver is responsible for the access to the
slave interface from the V1v1Ebus. In general, the configuration parametervrne-a3 2 -slaveena? must be set to false to prevent OpenBoot from initialising and enabling the slave
interface when an operating system will be loaded. Supposed that the slave interface is
initialized and enabled by OpenBoot prior to loading the operating system, any access from the
VMEbus to the slave interface while loading the operating system may alter memory and cause
severe damage.
The NVRAM configuration parameters listed below are associated with the master interface to
access the short (AI6) address range.
vme-a16 -mas ter-addr specifies the base address of the short (A16) address range to be
accessed on the VMEbus.
The default value of this 32-bit NVRAM configuration parameter is zero (0).
vme-a16-master-size specifies the size of the area in the short (A16) address range of
the V1v1Ebus which will be accessed. When the value of this configuration parameter
is zero OpenBoot will not initialize the master interface, even if the vrne-a16-master-ena? configuration parameter is true! If the specified size exceeds the size of
the short (A16) address range, then it limits the specified size to 64 Kbyte. Due to the
capabilities of the SPARe FGA-5000 OpenBoot will always adjust the specified size
to 64 Kbyte.
The default value of this 32-bit NVRAM coufiguration parameter is zero (0).
vme-a16-master-ena? indicates whether the master interface, to access the short (A16)
address range of the VMEbus, should be enabled. When this NVRAM configuration
parameter is true then the VMEbus master interface is enabled. In the case that the
NVRAM configuration parameter is false the VMEbus master interface is not enabled.
The default value of this NVRAM configuration parameter is false.

FORCE COMPUTERS

Page 139

OpenBoot

SPARC CPU-SV Technical Reference Manual

In the case that the NVRAM configuration parameter vme- ini t? is true OpenBoot will
initialize the master interface according to the configuration parameters described above. When
the vme-a16-master-ena? configuration parameter is true, then OpenBoot will
initialize the necessary registers in the master interface and provides the virtual memory to
access the VMEbus. The virtual base address necessary to access the VMEbus is stored in the
variable vme-a16-master-mem.
Thus, applications executed within the OpenBoot environment may benefit from this
mechanism, because OpenBoot will initialize the master interface completely according to the
NVRAM configuration parameters associated with the master interface.

In
addition, this mechanism allows to report the parameters of the master interface to an
.... _ .... _ • .: ____ ._ ..... _ 1 .... _..3 .... ..3 •••1...: ....1..:_ ... ___ ......:..3 .... _ :._ .... _ _ ••:_._1 _ _ _ _ _ •• _______ .1.._ ,TIl. .f"r.L __ _
V~.uLUlle ;)J;)L.t;l11lU4U~,

WU.I\;U 111 LUlll

PIUVIU~;).I1..;)

UWl1 VllLUCU

Ul~l11UlJ

LV

~\.N;);) W~

y .ly.u::.uu~.

In this case the VMEbus device driver is responsible for providing the necessary virtual address
range to access the VMEbus. In general, the configuration parameter vme-a16-masterena? must be set to false to prevent OpenBoot from initialising and enabling the master
interface when an operating system will be loaded.
The NVRAM configuration parameters listed below are associated with the master interface to
access the standard (A24) address range.

vme-a24 -mas ter-addr specifies the base address of the standard (A24) address range to
be accessed on the VMEbus.
The default value of this 32-bit NVRAM configuration parameter is zero (0).

vme-a24-master-size specifies the size of the area in the standard (A24) address range
of the VMEbus which will be accessed. When the value of this configuration parameter is zero OpenBoot will not initialize the master interface, even if the vme-a24master-ena? configuration parameter is true! If the specified size exceeds the
size of the standard (A24) address range, then it limits the specified size to 16 Mbyte.
The default value of this 32-bit NVRAM configuration parameter is zero (0).

vme-a24-master-ena? indicates whether the master interface, to access the standard
(A24) address range of the VMEbus, should be enabled. When this NVRAM configuration parameter is true then the VMEbus master interface is enabled. In the case
that the NVRAM configuration parameter is false the VMEbus master interface is
not enabled.
The default value of this NVRAM configuration parameter is false.

In the case that the NVRAM configuration parameter vme- ini t? is true OpenBoot will
initialize the master interface according to the configuration parameters described above. When
the vme-a24-master-ena? configuration parameter is true, then OpenBoot will
initialize the necessary registers in the master interface and provides the virtual memory to
access the VMEbus. The virtual base address necessary to access the VMEbus is stored in the
variable vme-a2 4-roas ter-mem.
Thus, applications executed within the OpenBoot environment may benefit from this
mechanism, because OpenBoot will initialize the master interface completely according to the
Page 140

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

NVRAM configuration parameters associated with the master interface.
In addition, this mechanism allows to report the parameters of the master interface to an
operating system loaded, which in tum provides its own virtual memory to access the VMEbus.
In this case the VMEbus device driver is responsible for providing the necessary virtual address
range to access the VMEbus. In general, the configuration parameter vme-a24-masterena? must be set to false to prevent OpenBoot from initializing and enabling the master

interface when an operating system will be loaded.
The NVRAM configuration parameters listed below are associated with the master interface to
access the extended (A32) address range.
vme-a32-master-addr specifies the base address of the extended (A32) address range to
be accessed on the VMEbus.
The default value of this 32-bit NVRAM configuration parameter is zero (0).
vme-a32-master-size specifies the size of the area in the standard (A24) address range
of the VMEbus which will be accessed. When the value of this configuration parameter is zero OpenBoot will not initialize the master interface, even if the vrne-a32master-ena? configuration parameter is true!
The default value of this 32-bit NVRAM configuration parameter is zero (0).
vme-a32 -mas ter- ena? indicates whether the master interface, to access the extended
(A32) address range of the VMEbus, should be enabled. When this NVRAM configuration parameter is true then the VMEbus master interface is enabled. In the case
that the NVRAM configuration parameter is false the VMEbus master interface is
not enabled.
The default value of this NVRAM configuration parameter is false.
In the case that the NVRAM configuration parameter vme- ini t? is true OpenBoot will

initialize the master interface according to the configuration parameters described above. When
the vme-a24-master-ena? configuration parameter is true, then OpenBoot will
initialize the necessary registers in the master interface and provides the virtual memory to
access the VMEbus. The virtual base address necessary to access the VMEbus is stored in the
variable vrne-a2 4 -mas ter-mem.
Thus, applications executed within the OpenBoot environment may benefit from this
mechanism, because OpenBoot will initialize the master interface completely according to the
NVRAM configuration parameters associated with the master interface.
In addition, this mechanism allows to report the parameters of the master interface to an
operating system loaded, which in tum provides its own virtual memory to access the VMEbus.
In this case the VMEbus device driver is responsible for providing the necessary virtual address
range to access the VMEbus. In general, the configuration parameter vme-a32-masterena? must be set to false to prevent OpenBoot from initializing and enabling the master

interface when an operating system will be loaded.
FORCE COMPUTERS

Page 141

OpenBoot

4.2.12

SPARC CPU-SV Technical Reference Manual

DMA Controller Support

The commands listed below are available to control the DMA controller of the SPARC FGA5000, as well as to get information about the actual state of the DMA controller.

dIna - irq-map! (mapping - ) selects the interrupt to be generated by the DMA controller
when the DMA process terminated successfully or due to an error. The parameter
mapping defines the interrupt asserted by the SPARC FGA-5000 when the certain
VMEbus interrupt request level is asserted. The value of mapping may be one of the
values in the range zero through seven. Each value specifies one of the eight SPARC
FGA-5000 interrupt request lines. The table "Interrupt Mapping;" on page 109 lists all
allowed mappings.
dIna - irq! (true Ifalse) enables or disables the interrupt to be generated by the DMA controller when the DMA process tenninated successfully or due to an error. When the
value true is passed to the command the interrupt is enabled. Otherwise - the value
false is passed to the command - the interrupt is disabled.
dIna - ip? ( - true I false) checks whether an interrupt is pending because a DMA process
has been tenninated. The value true is returned when an interrupt is pending due to the
tennination of a DMA process. Otherwise the value false is returned to indicate that no
interrupt is pending.

dIna - ena ( -

) enables the DMA controller and starts a DMA process.

dIna -dis ( -

) disables the DMA controller and stops the DMA process currently running.

dIna - hal t ( -

) halts the DMA process currently running.

dIna - resume ( -

) resumes the DMA process that has been halted before.

dIna-src-cap@ ( - data-capability address-capability) returns the data-capability and
address-capability currently defined for the source of the DMA process.
dma-src-cap! ( data-capability address-capability - ) sets the data-capability and
address-capability for the source of the DMA process.
The constants listed below are available to specify the data-capability and the
address-capability:

Page 142

value

data-capability address-capability

0002

cap-d8

cap-a16

001 2

cap-d16

cap-a24

01°2

cap-d32

cap-a32

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

value

data-capability address-capability

011 2
1002
101 2
1102

cap-bIt

reserved

cap-roblt

reserved

reserved

reserved

reserved

reserved

reserved

reserved

1112

dma-dest-cap@ ( - data-capability address-capability) returns the data-capability and
address-capability currently defmed for the destination of the DMA process.
dma-dest-cap! ( data-capability address-capability - ) sets the data-capability and
address-capability for the destination of the DMA process.
The constants listed below are available to specify the data-capability and the
address-capability:
value

data-capability address-capability

~

cap-d8

cap-al6

001 2
0102
011 2
1002
101 2

cap-dl6

cap-a24

cap-d32

cap-a32

cap-bit

reserved

cap-roblt

reserved

reserved

reserved

11°2
1112

reserved

reserved

reserved

reserved

dma-count@ ( - transfer-count) returns the current state of the transfer count. The value
transfer-count indicates the number of bytes to be transfer by the DMA controller.
Because the DMA controller only transfers a multiple of 32-bit data (longword, which
is a word in the SPARC terminology), the command returns the appropriate number of
words to be transferred.
dma -count! (transfer-count - ) sets the number of bytes - transfer-count - to be transferred by the DMA controller.
Because the DMA controller only transfers a multiple of 32-bit data (longword, which
is a word in the SPARC terminology), the command calculates the appropriate number
of words to be transferred. The transfer-count is considered to be a modulo 4 Mbyte
less four bytes number.
FORCE COMPUTERS

Page 143

SPARC CPU-SV Technical Reference Manual

OpenBoot

dma -running? ( - true Ifalse ) checks whether the DMA controller is in the nmning state.
The value true is returned when the DMA controller is currently running. Otherwise
the value false is returned to indicate that the DMA controller is disabled.
dma -wai ting? ( - true Ifalse ) checks whether the DMA controller is in the waiting state.
The value true is returned when the DMA controller is currently waiting, which means
that it has been halted. Otherwise the value false is returned to indicate that the DMA
controller is not waiting.

dma-normal-terminated? ( - true Ifalse) checks whether the DMA process has been
terminated successfully. It returns the value true when the DMA process has been terminated successfully. Otherwise the value false is returned to indicate that the DMA
process has been terminated due to a fail state, or because the DMA process is still in
progress.

dma-error-terminated? ( - true I false) checks whether the DMA process has been
terminated unsuccessfully. It returns the value true when the DMA process has been
terminated due to a fail state. Otherwise the value false is returned to indicate that the
DMA process has been terminated due to nonnal tennination, or because the DMA
process is still in progress .

. dma - s ta t ( - ) displays the current state of the DMA Status Register.

ok .dma-stat
ERR: 3 NT: 0 HALT: 0 RUN: 0

ok
The fields tll', HALT, and ROR reflect the current state of the DMA controller. When
the NT field is set to one (1), then the DMA controller terminated successfully (normal
termination). In the case that the HALT field is set to one (1), then the DMA controller
is halted - in general, this field is set along with the RUN field. The DMA controller is
running when the RUN field is set to one (1). When one of the fields described previously is cleared (0), the DMA controller is not in the particular state.
Typically, the ERR. field indicates the course of the DMA controller operation and may
indicate the fail states listed in the table below:

Error Code

Page 144

Description

0

Error occurred on source bus

1

Error occurred on destination bus

2

No error tennination

FORCE CO:MPUTERS

SPARC CPU-SV Technical Reference Manual

Error Code

3

OpenBoot

Description
No error termination

The following two commands used to initiate a DMA transfer do not set the data- and address
capabilities of the source area and destination area The capabilities must be appropriately set
with the dma-src-cap! and dIna-dest-cap! commands before the DMA transfer is
started.
dIna -mem>vme ( src-addr dest-addr count -

true IfaIse ) initiates a DMA transfer from the
SBus to the VMEbus and awaits the termination of the DMA process.
The amount of bytes given by count is transferred from src-addr - an address area on
the SBus (virtual address) - to dest-addr - an address area on the VMEbus (physical address). The command returns the value true when all data have been transferred
successfully. Otherwise the value false is returned to indicate that an error occurred
during the DMA process.
Because the DMA controller only transfers a multiple of 32-bit data (longword, which
is a word in SPARC tenninology), the command calculates the appropriate number of
words to be transferred. Furthermore, the count is considered to be a modulo 4 Mbyte
less four bytes number.

dIna -vme>mem ( src-addr dest-addr count -

true Ifalse) initiates a DMA transfer from the
V1\.ffibus to the SBus and awaits the termination of the DMA process.
The amount of bytes given by count is transferred from src-addr - an address area on
the VMEbus (physical address) - to dest-addr - an address area on the SBus (virtual address). The command returns the value true when all data have been transferred
successfully. Otherwise the value false is returned to indicate that an error occurred
during the DMA process.
Because the DMA controller only transfers a multiple of 32-bit data (longword, which
is a word in the SPARC terminology), the command calculates the appropriate number
of words to be transferred. Furthermore, the count is considered to be a modulo 4
Mbyte less four bytes number.

FORCE COMPUTERS

Page 145

SPARe CPU-SV TeclmicaI Reference Manual

OpenBoot

4.2.13

Mailboxes and Semaphores

The commands described in this section control the mailboxes, the semaphores, and the
interrupt box (IBOX).

vme-mbox- take ( mailbox# - true I false ) takes the mailbox semaphore specified by
mailbox# and returns the value true when the mailbox semaphore has been taken successfully. The value false is returned when the mailbox semaphore has been taken
already.
The value of mailbox# may be one of the values in the range zero through 15. Each
v~ lue specifie~s one of the 16 M~i1box Registers

vme-mbox-gi ve ( mailboX# - ) gives - releases - the mailbox semaphore specified by
mailbox#.
The value of mailbox# may be one of the values in the range zero through 15. Each
value specifies one of the 16 Mailbox Registers.

vme-mbox- irq-map! (mapping mailbox# - ) selects the interrupt to be generated when
the mailbox semaphore specified by mailbox# is taken. The value of mailbox# may be
one of the values in the range zero through 15. Each value specifies one of the 16
Mailbox Registers.
The parameter mapping defines the interrupt asserted by the SPARe FGA-5000 when
the mailbox semaphore is taken. The value of mapping may be one of the values in the
range zero through seven. Each value specifies one of the eight SPARe FGA-5000
interrupt request lines. The table "Interrupt Mapping." on page 109 lists all allowed
mappings.

vme-mbox- irq-ena ( mailboX# - ) allows the VMEbus interface to generate an interrupt
when the mailbox specified by mailbox# is taken. The value of mailbox# may be one
of the values in the range zero through 15. Each value specifies one of the 16 Mailbox
Registers.

vme-mbox- irq-dis ( mailbo:x# -. ) disables the interrupt to be generated when the mailbox specified by mailbox# is taken. The value of mailbox# may be one of the values in
the range zero through 15. Each value specifies one of the 16 Mailbox Registers.

vme-mbox-ip? (mailbox -

true I false

) checks whether an interrupt is pending because
the mailbox semaphores specified by mailbox# have been taken. The value true is
returned when an interrupt is pending because the mailbox semaphore has been taken.
Otherwise the value false is returned to indicate that no interrupt is pending.
The value of mailboX# may be one of the values in the range zero through 15. Each
value specifies one of the 16 Mailbox Registers.

vme-sem-take (semaphore#- true Ifalse) takes a semaphore specified by mailbox# and
returns the value true when the semaphore has been taken successfully. The value
Page 146

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

false is returned when the semaphore has been taken already.
The value of semaphore#may be one of the values in the range zero through 47. Each
value specifies one of the 48 Semaphore Registers.

vme- sem-give ( semaphore# - ) gives - releases - the semaphore specified by semaphore#.
The value of semaphore# may be one of the values in the range zero through 47. Each
value specifies one of the 48 Semaphore Registers.
The Interrupt Box is only accessible from the VMEbus within the short address space (A16).
Any byte access - reading or writing - may lead the SPARe FGA-5000 to generate an
interrupt. The address of the interrupt box within the short address space may be any byte
location in the range 000016 through FFFF16.
The commands listed below are available to control and initialize the Interrupt Box.

vme- ibox- irq-map! (mapping -

) selects the interrupt to be generated when the interrupt box is being accessed.
The parameter mapping defines the interrupt asserted by the SPARe FGA-5000 when
the interrupt box is accessed. The value of mapping may be one of the values in the
range zero through seven. Each value specifies one of the eight SPARe FGA-5000
interrupt request lines. The table "Interrupt Mapping." on page 109 lists all allowed
mappings.

vme- ibox- irq-ena ( -

) allows the VMEbus interface to generate an interrupt when the
interrupt box is accessed.

vme-ibox-irq-dis ( - ) disables the interrupt to be generated when the interrupt box is
accessed.

vme-ibox-ip? ( - true I false ) checks whether an interrupt is pending because the interrupt box has been accessed. The value true is returned when an interrupt is pending
because the interrupt box has been accessed. Otherwise the value false is returned to
indicate that no interrupt is pending.

vme- ibox-ena ( - ) enables the interrupt box.
vme- ibox-dis ( - ) disables the interrupt box.
vme- ibox-addr@ ( - addr ) returns the physical address addr of the interrupt box.
vme- ibox-addr! (addr - ) sets the physical address addr of the interrupt box.
As shown in the example below the first command sets the address of the interrupt box. The
interrupt box is accessible at the address 4002 16 within the V1vlEbus short address space. An
SBus IRQ 5 is generated by the SPARe FGA-5000 whenever the interrupt box is accessed
from the V1vffibus. The fourth command enables the interrupt box.
FORCE CO:MPUTERS

Page 147

OpenBoot

ok
ok
ok
ok
ok

4.2.14
Thp
_

..... -

SPARC CPU-SV Technical Reference Manual

hi 4002 v.me-ibox-addr!
5 v,me-ihox-irq-mapl
vme-ibox-irq-ena
vme-ibox-ena

FORCE Message Broadcast

rnTnTn~nr1C!

l1dpn hPloUl

~rp ~v~11~hlp

- " ' ...........................................,. ............................ " " . . . . . . . 'W'

to l"ontrnl thp
l=4()1)~ M~C!C!~O'~ 'R.T'n~r1,..~"t... ,.&.
tmJf'R\
.a.., ... ............ ,.....,1a.I ........""uu""'O'" .A.I.&."w.......

. . . . . . . . . . . . . . . . . , . . . . . . . . . .' "

_ " ....... "

...,~

......

"'Y~J

system and to obtain status infonnation about the state of the FM:B system.
fmb-super-only ( true I false - ) allows or prevents the FM:B message registers from
being accessed in the non-privileged mode. When the value true is passed to the command the FM:B message register is accessible in the privileged mode, as well as in the
non-privileged mode. Otherwise - the value false is passed to the command - the
FMB message registers are accessible in the privileged mode only.
fmb- ena ( channell - ) enables the FM:B channel specified by channel#. The value of
channel# may be one of the values in the range zero to one. Each value specifies one
of the two FM:B channels.
fmb- di s ( channell - ) disables the FM:B channel specified by channel#. The value of
channell may be one of the values in the range zero to one. Each value specifies one
of the two FM:B channels.
frob! ([ true Ifalse] channell - ) enables or disables the FM:B channel specified by channel#. When the value true is passed to the command the FM:B channel is enabled. Otherwise - the value false is passed to the command - the FM:B channel is disabled.
fmb-slot@ ( - slot#) returns the slot number slot# assigned to the FM:B channels.
frob-slot! (slot# - ) assigns the slot number slot# to the FM:B channels. The value of
slotH may be one of the values in the range zero to 21. Each value specifies a specific
slot.
fmb- addr@ ( - fmb-space ) returns the most significant eight bits - the fmb-space - of
the 32-bit VMEbus address the FM:B will respond to when an FM:B transaction on the
VMEbus is detected.
fmb-addr! (fmb-space - ) sets the most significant eight bits - the jmb-space - of the
32-bit VMEbus address the FM:B will respond to when an FM:B transaction on the
VMEbus is detected.

Page 148

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

fmb- irq-map! ( mapping channell - ) selects the interrupt to be generated when the
FMB message has been accepted, or rejected by the channel specified by channel'.
The value of channell may be one of the values in the range zero through one. Each
value specifies one of the two FMB channels.
The parameter mapping defines the interrupt asserted by the SPARe FGA-5000 when
the FMB message is accepted or rejected. The value of mapping may be one of the
values in the range zero through seven. Each value specifies one of the eight SPARe
FGA-5000 interrupt request lines. The table "Interrupt Mapping." on page l091ists all
allowed mappings
fmb- irq! ([ true I false ] channell - ) enables or disables the interrupt to be generated
when either an FMB message has been accepted or rejected by the channel specified
by channell. The value of channell may be one of the values in the range zero
through one. Each value specifies one of the two FMB channels.
When the value true is passed to the command the interrupt is enabled. Otherwise the value false is passed to the command - the interrupt is disabled.
fmb- ip? ( channel#- true Ifalse ) checks whether an interrupt is pending because an FMB
message has been accepted or rejected by the channel specified by channell. The
value of channell may be one of the values in the range zero through one. Each value
specifies one of the two FMB channels.
The value true is returned when an interrupt is pending. Otherwise the value false is
returned to indicate that no interrupt is pending.
fmb-accepted- ip? ( channel# - true I false ) checks whether an interrupt is pending
because an FMB message has been accepted by the channel specified by channell.
The value of channel# may be one of the values in the range zero through one. Each
value specifies one of the two FMB channels.
The value true is returned when an interrupt is pending because a message has been
accepted. Otherwise the value false is returned to indicate that no interrupt is pending.
fmb-rejected-ip? (channel#- true I false ) checks whether an interrupt is pending
because an FMB message has been accepted by the channel specified by channel#.
The value of channell may be one of the values in the range zero through one. Each
value specifies one of the two FMB channels.
The value true is returned when an interrupt is pending because an message has been
rejected. Otherwise the value false is returned to indicate that no interrupt is pending.
fmb-rej ected- ip-clear ( channell - ) clears a pending message rejected interrupt
generated by the channel specified by channell.
fmb-msg@ ( channell - message true Ifalse) fetches a message - a 32-bit data - from
the FMB channel specified by channell. The message and the value true are returned
when an FMB is available. Otherwise the value false is returned to indicated that no
FMB message is available.
FORCE COMPUTERS

Page 149

SPARe CPU-SV Technical Reference Manual

OpenBoot

fmb-msg! (message slot-list chan:nel#- true Ifalse ) sends the message - a 32-bit datato all FMB channels identified by the slot-list and chan:nel#. The value true is returned
when the message has been sent out successfully. Otherwise the value false is returned
to indicate that one or more FMB channels have rejected the message.
The value of channel# may be one of the values in the range zero through one. Each
value specifies one of the two FMB channels.
The value of slot-list identifies the hosts participating in the FMB transaction. Each bit
of the slot list is associated with a host identified by a unique FMB slot number. The
first bit - bit 0 - relates to the host with the FMB slot number one (1); the second bit
- bit 1 - relates to the host with the FMB slot number two (2); and so forth.
Rpl'~nC!P
mAR.
C!'UC!tPTn
~l1nU1C!
"1.........
hnC!tc!
..... u,..,. thp
...A....,..A.
......
t.J'J"'
• ...,.&.&& .........
,,""yW' nnl'U
""4&AJ nn
.....1:" tn
. " ..."..,..w,
~~

~

thp
I'nTnTn~nrl
I'nnc!1np~
nnl'U thp
.......""" .....,."
...................
U'A .......,... ..,. 'fItJ.&..&.Aj
...........,
-...&........ ....,"' ......

least significant bits of the parameter slot-list (bit 0 through 20).

fmb- ini t ( slot# jmb-space - ) performs all rudimentary steps to initialize the SPARe
FGA-5000 in such a way that the subsequent FMB cycles are carried out using the
fmb-msg! command.
The slot number slot# specifies the slot number the FMB channels are associated with.
The value of slot#may be one of the values in the range zero to 21. Each value specifies a specific slot.
The last available register set in the SPARe FGA-5000 is initialized to carry out an
FMB cycle on the VMEbus within the appropriate VMEbus address area that has been
specified by jmb-space. The parameter jmb-space defines the most significant eight
bits (one of 256 16-Mbyte pages) of the VMEbus address where the FMB area is
located. The capabilities of this VMEbus master range are A321D32 and write posting
is disabled. The variable fmb-va contains the virtual address to be accessed to execute an FMB cycle on the VMEbus.

The example below assigns the slot number 15 10 to the FMB channels available (all other hosts
must have a different FMB slot number). The FMB address space is set to FA16 which means
that the FMB system is accessed when the address FAXX.XXXX16 appears on the VMEbus
address lines (the least significant 24 bits are used to select a specific FMB channel and specific
hosts). And the second command enables the second FMB channel.

ok dl lS hi fa £mb-init
ok true 1 £mb!
ok hi 1234AASS hi 0010.800£ 1 £mb-msg!
ok 1 fmb-msg@.
ok .s 2drop
1234AA55 ffffffff
ok 1 fmb-msg@
ok .s drop

o
ok

Page 150

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

Finally the message 1234.AA55 16 is sent to the second FMB channel available on the hosts
with the FMB slot number one, two, three, four, 15, and 20. Because the message is sent to the
host with the FMB slot number 15 - the host that sent the message - , the message is read
from the second FMB channel on the host, as shown by the fourth command. "When the FMB
channel is read again, and supposed the host did not receive another FMB message, the
command fmb-msg@ will return the value false to indicate that no more messages are
available.

4.2.15

Diagnostic

The commands listed and described in this section are used to obtain various error status
infonnation from the SPARe FGA-5000 in the case of write posting errors and SBus errors.

wperr- irq-map! (mapping - ) selects the interrupt to be generated when a write posting
error occurs on the SBus or VMEbus. The parameter mapping defines the interrupt
asserted by the SPARC FGA-5000 when the write post error occures. The value of
mapping may be one of the values in the range zero through seven. Each value specifies one of the eight SPARC FGA-5000 interrupt request lines. The table "Interrupt
Mapping." on page 109 lists all allowed mappings.
wperr- irq! (true Ifalse - ) enables or disables the interrupt to be generated when a write
posting error occurs on the SBus or VMEbus. When the value true is passed to the
command the interrupt is enabled. Otherwise - the value false is passed to the command - the interrupt is disabled.
vme-wperr-ip? ( - true Ifalse ) checks whether an interrupt is pending because a write
posting error occurred on the VMEbus. The value true is returned when an interrupt is
pending due to a write posting error. Otherwise the value false is returned to indicate
that no interrupt is pending.
sbus-wperr-ip? ( - true Ifalse) checks whether an interrupt is pending because a write
posting error occurred on the SBus. The value true is returned when an interrupt is
pending due to a write posting error. Otherwise the value false is returned to indicate
that no interrupt is pending.
sbus-wperr-clear ( - error-adtir ) reads the SBus Write Posting Error Address Register and returns the address error-adtir.
vme-wperr-clear ( - error-adtir ) reads the VMEbus Write Posting Error Address Register and returns the address error-addr.
slerr-irq-map! (mapping - ) selects the interrupt to be generated when a late error
occurs on the SBus. The parameter mapping defines the interrupt asserted by the
SPARe FGA-5000 when the late error occurs. The value of mapping may be one of
FORCE COMPUTERS

Page 151

OpenBoot

SPARe CPU-SV Technical Reference Manual

the values in the range zero through seven. Each value specifies one of the eight
SPARC FGA-5000 interrupt request lines. The table "Interrupt Mapping." on
page 109 lists all allowed mappings.

s 1 err- irq! (true Ifalse -

) enables or disables the interrupt to be generated when a late
error occurs on the SBus.When the value true is passed to the command the interrupt
is enabled. Otherwise - the value false is passed to the command - the interrupt is
disabled.

slerr-ip? ( - true I false ) checks whether an interrupt is pending because a late error
occurred on the SBus. The value true is returned when an interrupt is penrling due to a
late error. Otherwise the value false is returned to indicate that no interrupt is pending.

slerr-clear ( - error-addr) reads the SBus Late Error Address Register and returns the
address error-addr.

4.2.16

Miscellanea

The commands listed in this section are used to control miscellaneous functions in the SPARe
FGA-5000.

freeze-intr-mapping (-) prevents the SYSFAIL*, ACFAIL* and ABORT Interrupt
Select and Enable Registers from being modified by setting the freeze bit in the Miscellaneous Control and Status Register. This mechanism is intended to prevent the
appropriate Interrupt Control and Status Register from being modified after it has been
initialized once.

dtb-dri ver-ena ( - ) enables all VMEbus DTB drivers.
dtb-driver-dis (-) disables all V1vIEbus DTB drivers.
vme-timer-ena (-) enables the V1vIEbus transaction timer.
vme- timer-dis ( - ) disables the V1vIEbus transaction timer.
vme-timeout@ ( - timeout) returns the V1vIEbus transaction timer timeout value in use.
The value of timeout may be one of the values in the range one through three. Each
value identifies a particular timeout period as shown in the table below.
vme- timeou t! (timeout - ) sets the VMEbus transaction timer timeout according to the
given timeout. The value of timeout may be one of the values in the range one. through
three. When the value being specified is not in the range one through three, then the
command selects the longest timeout period automatically.
The values select a particular timeout period. The table below lists all possible values:
Page 152

FORCE COMPUTERS

SPARe CPU-SV Technical Reference Manual

OpenBoot

timeout

immsactiontimeout

1

32 us

2

128 us

3

512 us

Table 41: VMEbus Transaction Timer Timeout Values

FORCE COMPUTERS

Page 153

SPARe CPU-SV Technical Reference Manual

OpenBoot

4.3

Standard InitiaIization of the VMEbus Interface

Besides the initialization performed according to the state of the NVRAM configuration
parameters, the V?v.IEbus interface - mainly the SPARC FGA-5000 - is initialized as
described in the subsections below.

4.3.1

SPARe FGA-5000 Registers

The registers of the SPARC FGA-5000 are accessible beginning at offset OFFF.FEOO 16 within
the SBus slot 5 and occupy the last 512 bytes in this slot (OFFF.FEOO 16 ... OFFF.FFFF16). This
-corresponds with the physical address range 7FFF.FEOO 16 through 7FFF.FFFF16.
The area in the range OFEO.OOOO 16 through OFFF.FDFF 16 is available for any application.
Preferably, this area may be used to access the standard (A24, max 16 MB) and short (AI6,
max 64 KB) address space of the V?v.IEbus.

4.3.2

VMEbus Transaction Timer

The SPARC FGA-5000 contains a VMEbus transaction timer which is disabled after a RESET.
This timer is enabled during the initialisation phase of OpenBoot and the transaction timeout
period is set to the longest possible value (512 us).

4.3.3

SBus Rerun Limit

The SBus Rerun Limit counter, within the SPARe FGA-5000, is disabled to avoid any
unproper behaviour of the system.
.

4.3.4

Interrupts

The SPARC FGA-5000 is initialized in such a way that in the case of the occurrence of one of
the events listed below, a nonmaskable interrupt Oevel 15 interrupt) is generated:
1.) Pressing the ABORT switch

PagelS4

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

4.3.5

OpenBoot

SBus Slot 5 Address Map
S"Bus Slot 5
Offset
OFFF.FE00

16

~..-........;~..........~~~~~SPARC FGA-5000 Registers
This area may be used to access
the entire standard (A24) and
Available for
short (A16) address space of the
VMEbus
VMEbus.
Accesses

OFEO.000016

0000.000016

FORCE COMPUTERS

L-.-......;...-..;.._..-..;..--:._ _.....

Page 155

OpenBoot

SPARC CPU-SV Technical Reference Manual

4.4

System Configuration

4.4.1

Watchdog Timer

wd - ena ( - ) enables and starts the watchdog timer.
wd-dis (-) stops and disables the watchdog timer.
wd-timeout@ ( - timeout) returns the watchdog timer's reference value in use. The value
of timeout may be one of the values in the range zero through seven. Each value ident;np~ ~ n~ri;t'111~1" t;Tn~nllt ~"n.rI ~C'

.............., - 1'-... ......... _ ... -..

104...

.u.'''''''_..

C'hnu"" ;'"
+ho +.,,1-..1.... 1-..01 ........ ,
~ll loLl'" 1oQAJ.l'" ~.lVVY.

,t''''.L'&v,,",",", o;lIJ,J,vnJ.J.

wd-timeout! (timeout - ) sets the watchdog timer's reference value for timeout according to the given timeout. The value of timeout may be one of the values in the range
zero through seven. Only the least significant three bits of the value timeout are considered. The values select a particular timeout period. The table below lists all possible
values:

timeout

lwd-timeoutmin

0

408ms

1

1.68 s

2

6.7 s

3

26.8 s

4

1 min 48 s

5

7 min 9 s

6

28 min 38 s

7

1 h 54 min

Table 42: Watchdog Timer Timeout Values
wd-nmi-ena ( expired.

) allows an interrupt to generate when half of the watchdog time has

wd-nmi-dis ( - ) disables the interrupt's ability to generate when half of the watchdog
time has expired.
wd-irq-map! (mapping - ) selects the interrupt to be generated when half of the watchPage 156

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

dog time has expired.
The parameter mapping defines the interrupt asserted by the SPARe FGA-5000 when
half of the watchdog time has expired. The value of mapping may be one of the values
in the range of zero through seven. Each value specifies one of the eight SPARe FGA5000 interrupt request lines. The table "Interrupt Mapping." on page 109 lists all
allowed mappings.

wd-nmi -clear ( - ) clears a pending interrupt caused by the watchdog timer when half of
the watchdog time has expired.
wd-ip? ( - true lfalse) checks whether an interrupt is pending due to an interrupt generated by ~lte watchdog timer when half of the watchdog time has expired. The value
true is returned when the interrupt is pending; otherwise the value false is returned.
wd - res tart ( - ) resets the watchdog timer and starts a new time count In particular the
command invokes one of the commands vsi-wdt-restart@ or vsi-wdtrestart! to restart the watchdog timer.
The watchdog timer is started by the commands listed below:

ok
ok
ok
ok
ok

3 wd-timeout!
vsi-nmi wd-irq-map!
wd-mu.i.-ena
wei-ana

In this example the watchdog timer timeout is set to 26.8 seconds, and a nonmaskable interrupt
is generated whenever half of the watchdog time has expired. The OpenBoot already contains
an interrupt handler dealing with the interrupt generated by the watchdog timer, and this
interrupt handler increments an internal variable by one, whenever the watchdog timer emits
an interrupt. The state of this variable is detennined by:

ok wdDmi-occurred? ?
6

ok
.' This variable is cleared -

set to zero - by

ok wdDmi-occurred? off
ok
wd- reset? ( - true I false ) detennines whether a reset has been generated because the
watchdog timer has expired. If a reset has been generated because the watchdog timer
reached the timeout value, then the value true is returned; otherwise the value false is
returned
FORCE COMPUTERS

Page 157

OpenBoot

4.4.2

SPARC CPU-SV Technical Reference Manual

Watchdog Timer NVRAM Configuration Parameters

The NVRAM configuration parameters listed below are available to control the initialisation
and operation of the watchdog timer. The current state of these configuration parameters are
displayed using the printenv command, and are modified using either the setenv, or the
set-defaul t command provided by OpenBoot.

wd-ena? controls whether the watchdog timer has to be started. When the flag is true, then
the watchdog timer is started after it has been initialized according to the configuration
parameter wd-timeout. If the flag is false the watchdog timer is not started, but
the watchdog timer registers are initialized according to the configuration parameter
wd-timeout. (default: false)
wd - timeou t contains the timeout value of the watchdog timer and is a value in the range 0
to 7. Each value selects a particular timeout period. Independent of the state of the
configuration parameter wd-ena? the timeout value is stored in the appropriate
watchdog timer register. (default: 7 10)

4.4.3

Abort Switch

abort - swi tch? ( - true I false ) determines the current state of the abort switch. The
value true is returned when the abort switch is pressed. And the value false is returned
when the abort switch is released.
abort-irq-map! ( mapping - ) selects the interrupt to be generated when the abort
switch is pressed.
The parameter mapping defines the interrupt asserted by the SPARC FGA-5000 when
the abort switch is presssed. The value of mapping may be one of the values in the
range zero through seven. Each value specifies one of the eight SPARC FGA-5000
interrupt request lines. The table "Interrupt Mapping." on page 109 lists all allowed
mappings.
abort-nmi-ena (-) allows an interrupt to generate when the abort switch is pressed.
abort-nmi-dis ( - ) disables the interrupt's ability to generate when the abort switch is
being pressed.
abort-ip? ( - true I false) checks whether an interrupt is pending because the abort
switch has been pressed. The value true is returned when the interrupt is pending; otherwise the vallue false is returned.
abort-nmi-clear (-) clears a pending interrupt caused by the abort switch.

Page 158

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

4.4.4

OpenBoot

Abort Switch NVRAM Configuration Parameter

The NVRAM configuration parameter listed below is available to control the initialisation and
operation of the abort switch. The current state of these configuration parameters are displayed
using the printenv command, and are modified using either the setenv, or the setdefaul t command provided by OpenBoot.

abort-ena? controls whether the abort switch has to be enabled. When this flag is true
the abort switch is enabled and has the same effect as pressing the STOP-A key on an
available keyboard. If the flag is false then the abort switch is disabled. (default:
false)

4.4.5

LEDs, Seven-Segment Display and Rotary Switch

The commands described below are available to control the seven-segment LED display, the
user LEDs, and are used to retrieve information about the state of the rotary switch.

diag -1 ed! (byte - ) stores the data byte passed to the command in the register used to
control the seven-segment display.
>7 -seg-code (u - 7-seg-code) converts the value u to its corresponding seven-segment
code 7-seg-code. Only the least significant four bits of the value u are considered.

) controls the user LED identified by led#. The value of led# may
be either zero or one. The value zero specifies the first user LED, and the value one
specifies the second user LED. The command only considers the state of the bit 0 of
the value led#.
The parameters colour and freq define the colour of the LED and the frequency at
which the LED is blinking. The following constants are defined to specify the colour:
black, green, red, and yellow. When the colour black is specified the LED is
turned off.
The constants no-blinking, slow, moderate, and fast are available to specify
a frequency. The constant no-blinking causes the LED to be turned on pennanently.

1 ed ! (colour freq led# -

The following example shows how to let the second user LED blink at about 2 Hz
(moderate) in red

ok red moderate 1 led!
ok
1 ed- on (led# - ) turns the user LED identified by led# on. The value of led# may be either
zero or one. The value zero specifies the first user LED, and the value one specifies
the second user LED. The command only considers the state of the bit 0 of the value
FORCE COMPUTERS

Page 159

SPARC CPU-SV Technical Reference Manual

OpenBoot

led#.

led-o f f ( led# - ) turns the user LED identified by led# off. The value of led# may be
either zero or one. The value zero specifies the fIrSt user LED, and the value one specifies the second user LED. The command only considers the state of the bit 0 of the
value led#.

1 ed? ( led# - true I false ) determines the state of the LED identified by led#, and returns
either true or false to indicate if the LED is turned on or off. The value of led# may be
either zero or one. The value zero specifies the fIrSt user LED, and the value one specifies the second user LED. The command only considers the state of the bit 0 of the
value led#.
When the LED is turned on, then the value true is returned; otherwise the value false is
returned.
toggle-led (led# - ) determines the state of the user LED identified by led#, and turns
the LED on or off. The LED is turned on when it was turned off before, and vice versa
The value of led# may be either zero or one. The value zero specifies the :first user
LED, and the value one specifies the second user LED. The command only considers
the state of the bit 0 of the value led#.
rotary-swi tch@ ( - byte) returns the current state of the rotary switch. The value of
byte may be one of the values in the range zero through 15. The value zero corresponds to the position 0 of the rotary switch, the value one corresponds to position 1,
and so forth.

4.4.6

Reset

The command listed below are available to initiate various RESETs, and to obtain infonnation
about a previous RESET.
vme- sysreset ( reset.

) asserts the VMEbus SYSRESET* signal and thus causes a system

reset-call ( - ) forces a local reset. This command provides the same function as the
OpenBoot command reset.
vme-sysreset-in! (true I false ) allows or prevents the board from being reset by the
assertion of the VMEbus SYSRESET* signal. When the value true is passed to the
command the board will be reset whenever the VMEbus SYSRESET* signal is
asserted. Otherwise - the value false is passed to the command - the board will not
be reset by the assertion of the SYSRESET* signal.

Page 160

FORCE COl\.fPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

sbus - reset? ( -

true I false ) determines whether the last reset occurred was due to an
SBus reset. The value true is returned when the last reset was because of an SBus
reset. Otherwise it returns the value false to indicate that the last reset was not because
of an SBus reset.

wdt-reset? ( - true I false ) detennines whether a reset has been generated because the
watchdog timer has expired. If a reset has been generated because the watchdog timer
reached the timeout value, then the value true is returned; otherwise the value false is
returned.

vme-sysreset? ( - true Ifalse ) determines whether the last reset occurred was due to the
assertion of the VMEbus SYSRESET* signal. The value true is returned when the last
reset was a VMEbus SYSRESET* reset. Otherwise it returns the value false to indicate that the last reset was not a VMEbus SYSRESET* reset

vme-sysreset-call? ( - true I false) determines whether the last reset occurred was
due to a VMEbus SYSRESET* call. The value true is returned when the last reset was
because of a VMEbus SYSRESET* call. Otherwise it returns the value false to indicate that the last reset was not a VMEbus SYSRESET* call.
A VMEbus SYSRESET* call is done by clearing the SYSRESET bit in the SPARC
FGA-5000's Miscellaneous Control and Status Register.

reset-call? ( -

true I false) determines whether the last reset occurred was due to a
local reset call. The value true is returned when the last reset was because of a local
reset call. Otherwise it returns the value false to indicate that the last reset was not a
local reset call.
A local reset call is done by clearing the RESET bit in the SPARC FGA-5000's Miscellaneous Control and Status Register.

vme-reset-call? ( - true Ifalse) determines whether the last reset occurred was due to
a reset call initiated by an access via the VMEbus. The value true is returned when the
last reset was because of a reset call. Otherwise it returns the value false to indicate
that the last reset was not because of a reset call initiated by an access via the VMEbus.
A reset call is done by clearing the LOCRESET bit in the SPARC FGA-5000's GLobal Control and Status Register.

FORCE COMPUTERS

Page 161

SPARC CPU-SV Technical Reference Manual

OpenBoot

4.5

Flash Memory Support

4.5.1

Flash Memory Programming

The commands listed below are available to access and program the flash memories available
on the SPARC CPU-5V.

flash-messages ( - vaddr ) returns the virtual address of the variable flashmessages. The state of this variable controls whether the words to erase and program
the flash memories will display messages while erasing or programming the flash
memories. Messages will not be displayed after turning off this variable by flashmessages off, and are displayed after turning on this variable by flashmessages on.
flash-va ( - vaddr ) returns the virtual base address vaddr of the flash memory
programming window. The virtual address returned is only valid when the flash memories
have been previously prepared for accessing using the select-flash word.
boot-flash-va ( memory.

vaddr) returns the virtual base address vaddr of the BOOT flash

user-flash-va ( - vaddr ) returns the virtual base address vaddr of the USER flash
memory. When the USER flash memory is not accessible directly, but only through the
flash memory programming window, then the address returned is zero. On the SPARC
CPU-5V the USER flash memory is accessible only through the flash memory
programming window. Thus, the commands described above have to be used to access the
USER flash memory.
select-flash ( ''USER'' I ''BOOT'' - ) prepares either the BOOT flash
memories, or the USER flash memories for programming. In detail, the number and size
of the available flash memories are detennined, as well as the size of the flash memory
programming window. The flash memory programming window is mapped and the
virtual base address of the window is stored internally, and may be obtained by using the
word flash-va.
user- flash? ( - true Ifalse ) checks whether the BOOT flash memory or the USER flash
memory is accessible through the flash memory programming window. It returns true in
the case that the USER flash memory is accessible through the programming window;
otherwise it returns false.
move> flash ( source-addr dest-addr count - ) programs the selected flash memory
beginning at dest-addr with a number of bytes, specified by count, stored at source-addr.
flash>move ( source-addr dest-addr count - ) copies a number of bytes, specified by
count, from the selected flash memory beginning at source-addr to dest-addr. The flash
memory is accessed through the flash memory programming window for reading data
from the memory. Thus, the flash memory has to be prepared for accessing using the
Page 162

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

command select-flash.

fill-flash (dest-addr count pattern - ) fills the selected flash memory beginning at destaddr with a particular pattern. The number of bytes to be programmed in the flash
memory is given by cozmt.

erase- flash ( device-number - ) erases a flash memory device identified by its devicenumber. The devices are numbered beginning from zero (0).

c! -flash (byte addr-) stores the byte at the location within the selected flash memory
identified by addr.

w! -flash (half-word addr - ) stores the half-word (16 bits) at the location within the
selected flash memory identified by addr.

1 ! - flash (word addr - ) stores the word (32 bits) at the location within the selected flash
memory identified by addr.
The USER flash memory is prepared for programming by:

ok se1ect-f1ash USER
USER flash memory is selected for programming
Flash memory programming window at $ffe98000 size 512 Kbyte
512 Kbyte BOOT flash memory is available at $ffe58000.
2048 Kbyte USER flash memory is available.
ok
As shown above, the word select - flash informs the user that the USER flash memory has
been made accessible through the flash memory programming window. It displays the base
address (virtual address) of the window and its size.
The total amount of the available BOOT flash memory and USER flash memory is displayed,
too. After the USER flash memory has been prepared for programming, all commands
described above operate on the USER flash memory. And the BOOT flash memory is only read
and programmed by these commands when the BOOT flash memory has been prepared for
these operations by:

ok select-tlash BOOT

BOOT flash memory is selected for programming
Flash memory programming window at $ffe98000 size 512 Kbyte
512 Kbyte BOOT flash memory is available at $ffe58000.
2048 Kbyte USER flash memory is available.
ok
To read data from the selected flash memory - in the current context from the USER flash
memory - the command f lash>move is used as follows:

ok flash-va hi 10.0000 hi 20.0000 ftash>move
ok
FORCE COMPUTERS

Page 163

OpenBoot

SPARC CPU-SV Technical Reference Manoal

The contents of the entire USER flash memory is copied to main memory beginning at address
10.000016 . A specific area within the selected flash memory is read by:

ok f1ash-va hi 6.8000 + hi 10.0000 hi S.8cOO f1ash>move
ok
and copies 363520 bytes beginning from address flash-va + 6.800016 to main memory
beginning at address 10.000016 .

4.5.2

Flash Memory Device

The device tree of OpenBoot for the SPARe CPU-5V contains a device node associated with
the USER flash memories. Thus, it is possible to load an executable image stored in the
available USER flash into memory and start such an executable.
The device is called "flash-memory£lO, 71300000" and is attached to the device node" /
ohio". The device alias f1ash is available as an abbreviated representation of the flash
memory device pa.$.
The vocabulary of the flash memory device includes the standard commands recommended for
a byte device. The words of this vocabulary are only available when the :flash memory device
has been selected as shown below:

ok cd f1ash
ok words
close
open
write-blocks read-blocks
max-transfer block-size
ok self test •

self test
seek

reset
write

load
read

o
ok device-end
ok
The example listed above, selects the :flash memory device and makes it the current node. The
word words displays the names of the methods of the VMEbus device. And the third
command calls the method self test and the value returned by this method is displayed. The
last command zmselects the current device node, leaving no node selected.
When the command se1ect-dev is used to select the :flash memory device, the NVRAM
configuration parameters hootf1ash-imegs and hootflash-Idevices have to be set
properly, before the device can be selected.
The NVRAM configuration parameters listed below are available to control the loading of an
image from the USER :flash memory. The current state of these configuration parameters is
displayed using the printenv command, and is modified using either the setenv, or the
set-defaul t command provided by OpenBoot.

bootflash-#megs specifies the amount of available USER flash memory in megabyte.
Page 164

FORCE CO:MPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

(default: 0 Megabyte)

bootflash-#devices specifies the number of available USER flash memory devices.
(default: no devices)
bootflash-load-base specifies the address where the data loaded from the available
flash memory are stored when the load or boot command, provided by OpenBoot,
is used to load an image from the flash memory.
When this parameter is set to -1 - which is the parameter's default value - then the
image loaded from the flash memory is stored beginning at the address addr. But when
the value of the configuration parameter differs from -1, then the image loaded from
the flash memory is stored beginning at the address specified by the configuration
parameter bootflash-load-base. And the same address is stored in the variable
load-base maintained by OpenBoot.

The methods listed below are available in the vocabulary of the flash memory device:

open ( - true ) prepares the package for subsequent use. The value true is returned when
the device has been opened successfully; otherwise the value false is returned. Usually, the fail state is indicated when the NVRAM configuration parameters bootflash-#megs and bootflash-#devices are not consistent.
close (-) frees all resources allocated by open.
reset (-) puts the flash memory device into quiet state.
. sel f tes t ( - error-number) always returns the value zero.
read ( addr lenth - actual) reads at most length bytes from the flash memory device into
memory beginning at address addr. If actual is zero or negative, the read failed. The
value of length may not always be a multiple of the device's normal block size.
wr i te ( addr length -

actual) discards the information passed to the command and always
returns zero to indicate that the device does not support this function.

seek ( offset file# - error? ) seek to byte offset within the file identified by file#. The flash
memory device package maintains an internal position counter that is updated whenever a method to read data from or to store data in the flash memories is called. If offset and file# are both zero, then the internal position counter is reset to offset zero,
otherwise the value of offset is assigned to the internal position counter, and a subsequent access to the :flash memories starts at the offset selected.
Because the flash memory device does not support any file system, the parameter file#
is ignored, except in the case mentioned above.
When the seek succeeded the value of error? is zero, otherwise the value -1 is retunFORCE COMPUTERS

Page 165

OpenBoot

SPARC CPU-SV Technical Reference Manual

rned to indicate the fail state.
read-blocks ( addr block# #blocks - #read) reads the number of blocks identified by
#blocks of length block-size bytes, each from the device beginning at the device
bvlock block#, into memory at address addr. It returns the number of blocks actually
read (#read).
write-blocks (addr block##blocks-#Written) discards the information passed to the
command and always returns zero to indicate that the device does not support this
function.
block- size ( - bytes) returns the size in bytes bytes of a block which is always the size of
the flash memory programming window.
max-transfer ( - bytes) returns the size in bytes bytes of the largest single transfer the
device can perform. The command returns a multiple of block-size.
load (addr-Iength) reads a stand-alone program from the flash memory beginning at offset 016 and stores it beginning at address addr. It returns the number of bytes length
read from the flash memory.
This method considers the state of the NVRAM configuration parameter bootflash-load-base: when this parameter is set to -1 - which is the parameter's
default value - then the image loaded from the flash memory is stored beginning at
the address addr. But when the value of the configuration parameter differs from -1,
then the image loaded from the flash memory is stored beginning at the address specified by the configuration parameter bootflash-load-base. And the same
address is stored in the variable load-base maintained by OpenBoot.

Loading and Executing Programs from USER Flash Memory

4.5.3

Besides the ability to load and execute an executable image from disk, or via a network, or
other components, the OpenBoot for the SPARe CPU-5V provides a convenient way to load
and execute an executable image from the available USER flash memory. The executable
image to be loaded has to be either a binary image (a.out format), a FORTH program, or a
FCode program.
As mentioned at the beginning of this section the device alias flash is available as an
abbreviated representation of the flash memory device. The command listed below is used to
explicitly load and execute an image from the flash memory:
ok boot flash
The following NVRAM configuration parameters can be modified to determine whether or not
the system will load an executable image automatically after a power-up cycle or system reset:

Page 166

FORCE CO?dPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

auto-boot?
boot-device

Assuming, that the SPARe CPU-5V is equipped with one USER flash memory device which
size is 1Mbyte, then commands listed in the following have to be used to load and execute an
image from the flash memory automatically after a power-up cycle or system reset:

ok setenv bootflash-Idevices 1
bootflash-#devices

=

1

ok setenv bootflash-#.megs 1
bootflash-#megs =

1

ok setenv boot-device flash
boot-device =

flash

ok setenv auto-boot? true
auto-boot? =

true

ok reset

4.5.4

Controlling the Flash Memory Interface

The commands listed below are available to control the flash memory interface. These
commands are used to make a specific flash memory device available in the flash memory
programming window, and to control the flash memory programming voltage.

flash -vpp-on ( -

) turns the programming voltage on.

flash-vpp-off (-) turns the programming voltage off.
userprom-select-page (page - ) makes a page (one of a eight possible 512 KB pages)
of a USER flash memory available in the flash memory programming window.
bootprom-select-page (page - ) makes apage (one of a eight possible 512 KB pages)
of a BOOT flash memory available in the flash memory programming window.
select-bootprom-l ( - ) makes the first BOOT flash memory device available in the
flash memory programming window.
select-bootprom-2 (-) makes the second BOOT flash memory device available in the
flash memory programming window.
select - bootprom ( device-number - ) makes a BOOT flash memory device, identified
by its device-number, available in the flash memory programming window. The devices
are numbered beginning from zero (0).
select-userprom-l ( - ) makes the first USER flash memory device available in the
FORCE COMPUTERS

Page 167

OpenBoot

SPARe CPU-SV Technical Reference Manual

flash memory programming window.

select-userprom-2 (-) makes the second USER flash memory device available in the
flash memory programming window.
select-userprom ( device - ) makes a USER flash memory device, identified by its
device-number, available in the flash memory programming window. The devices are
numbered beginning from zero (0).

Page 168

FORCE COMPUTERS

SPARC CPU-SV Teclmical Reference Manual

4.6

OpenBoot

Onboard Interrupts

Besides the interrupt handlers already available in the standard OpenBoot, the OpenBoot of the
SPARC CPU-5V provides further handlers that deal with the interrupts generated by following:
• one of the VMEbus interrupt levels one to seven;
• the assertion and negation of the SYSFAIL* signal;
• the assertion of the ACFAll..* signal;
• pressing the ABORT switch;
~

4.6.1

the Watchdog Timer, when half the time has expired.

Vl\mbus Interrupts

The interrupt handlers for any VMEbus interrupt are not installed automatically by OpenBoot;
however, appropriate words are available to activate and deactivate an interrupt handler
serving a specific VMEbus interrupt. Such an interrupt handler is activated by:
ok 0 pill
ok 3 5 install-VDle-intr-handler
ok

The pil! command decreases the processor interrupt level to allow the processor to respond
to all interrupts. By default, OpenBoot sets the mask to 13 and allows the processor to respond
to interrupts above interrupt level 13. The second command installs the interrupt handler that
deals with the VMEbus interrupt level 5. Furthermore, this command specifies that an SBus
interrupt level 3 will be generated upon the occurrence of a VMEbus interrupt 5. Any of the
seven SBus interrupt levels may be specified to be generated upon a VMEbus interrupt.
OpenBoot maintains seven variables called vme-intr{112\3\4IS\6\7}-vector
which are modified by the VMEbus interrupt handlers. In general, the interrupt handlers store
the vector obtained during an interrupt acknowledge cycle in the appropriate variable. The state
of these variables is displayed by
ok .vme-vectors
1:
2: -3:-ok

4: --

5: 33

6: --

7: --

By default, the value -1 ( true ) is assigned to these variables to indicate that no VMEbus
interrupt occurred. So, the word . vme-vectors, as shown above, will display "--"
indicating that no interrupt occurred; otherwise it shows the vector obtained (a value in the
range 0 to FF16).
Another way to display the state of a variable used to store the interrupt vector is
ok vme-intrS-vector ?
FORCE COMPUTERS

Page 169

OpenBoot

SPARe CPU-SV Technical Reference Manual

33

ok
and the variable is set to -1 (true) by

ok vme-intrS-vector on
ok
An interrupt handler is removed and the corresponding interrupt is disabled by

ok 5 uninstall-vme-intr-handler
ok
All interrupt handlers serving all VMEbus interrupts are installed by

ok 0 pill
ok 8 1 do i i install-v.me-intr-bandler loop
ok
In this case, all interrupt handlers are installed and the VMEbus interrupt to SBus interrupt
mapping is as follows: SBus interrupt level 1 is generated upon the occurrence of a VMEbus
interrupt 1; SBus interrupt level 2 is generated upon the occurrence of a VMEbus interrupt 2;
and so forth.

4.6.2

SYSFAIL Interrupt

OpenBoot for the SPARe CPU-5V already includes an interrupt handler to serve the nonmaskable interrupt generated upon the assertion and negation of the SYSFAIL* signal. This
handler need not to be installed because it is already installed by OpenBoot.
By default, the interrupts that will be emitted by a status change of the SYSFAIL* signal are
disabled and have to be enabled by

ok vme-sysfail-assert-Dmiena
ok v.me-sysfail-negate-umiena
ok
which enable the generation of a nonmaskable interrupt whenever the SYSFAIL* signal is
asserted and negated.
When an nonmaskable interrupt occurred due to the assertion of the SYSFAIL * signal, then the
appropriate interrupt handler increments the variable sysfail-asserted? by one to
report the occurrence of such an interrupt. The variable sys f ai I-nega ted? is incremented
by the interrupt handler when the SYSFAll...* signal has been negated and caused a nonmaskable interrupt. The state of both variables are obtained by

ok sysfail-asserted? ?
Page 170

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

o
ok
and

ok sysfail-negated? ?
1

ok
And these variables are cleared - set to zero - by

ok sysfail-asserted? off
ok sysfail-negated? off
ok

4.6.3

ACFAIL Interrupt

OpenBoot for the SPARe CPU-5V already includes an interrupt handler to serve the nonmaskable interrupt generated upon the assertion of the ACF.Aa* signal. This handler need not
to be installed because it is already installed by OpenBoot.
By default, the interrupt that will be emitted by asserting the ACFAIL* signal is disabled and
has to be enabled by

ok vme-acfail-assert-irq-ena
ok
which enables the generation of a nonmaskable interrupt whenever the ACFAll.,* signal is
asserted.
When a nonmaskable interrupt occurred due to the assertion of the ACF.Aa* signal, then the
appropriate interrupt handler increments the variable acfail-asserted? by one to report
the occurrence of such an interrupt. The state of this variable is obtained by

ok acfail-asserted? ?
2

ok
And the variable is cleared -

set to zero - by

ok acfail-asserted? off
ok

FORCE COMPUTERS

Page 171

OpenBoot

SPARC CPU-5V Technical Reference Manual

ABORT Interrupt

4.6.4

OpenBoot for the SPARC CPU-5V already includes an interrupt handler to serve the nonmaskable interrupt generated by pressing the front panel abort switch. This handler need not be
installed because it is already installed by OpenBoot.
By default, the interrupt that will be emitted when the abort switch has been pressed is disabled
and has to be enabled by

ok abort-mni-ena
ok
which enabies the generation of a nonmaskable interrupt whenever the abort switch is pressed.
When a nonmaskable interrupt occurred due to pressing the abort switch, then the appropriate
interrupt handler increments the variable abort-occurred? by one to report the
occurrence of such an interrupt. The state of both variables are obtained by

ok abort-occurred? ?
7
ok
And these variables are cleared -

set to zero - by

ok abort-occurred? off
ok
Besides the effects described above, the pressing of the abort switch has the same effect as
giving the Stop-A keyboard command. The program currently running is aborted and the
FORTH interpreter appears immediately.

Watchdog Timer Interrupt

4.6.5

OpenBoot for the SPARC CPU-5V already includes an interrupt handler to serve t.l}e nonmaskable interrupt generated by the watchdog timer when half of the time has expired. This
handler need not to be installed because it is already installed by OpenBoot.
By default, the interrupt that will be emitted by the watchdog timer is disabled - the watchdog
timer is disabled - and has to be enabled by

ok wd-mni-ena
ok wd-ana
ok

In this example a nonmaskable interrupt is generated whenever half of the watchdog time has
expired. The interrupt handler included in OpenBoot restarts the watchdog timer to ensure that
the watchdog time will not expire and cause a reset. Additionally, the interrupt handler
Page 172

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

OpenBoot

increments the variable wdnmi -occurred? by one whenever the watchdog timer emits an
interrupt The state of this variable is detennined by

ok wdDmi-occurred? ?
6
ok
This variable is cleared -

set to zero -

by

ok wdDmi-occurred? off
ok

FORCE COMPUTERS

Page 173

OpenBoot

Page 174

SPARC CPU-SV Technical Reference Manual

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

SECTIONS

S.

Circuit Schematics

CIRCUIT SCHEMATICS

CPU-5V Schematics

Copies of the CPU-SV schematics are found on the next page. The schematics contain the
signal and unit cross references as well as the history of the schematics.

FORCE COMPUTERS

Page 175

....----___ "____ _

A

B

D -_.

C

_ _ _ _ _ "_ _ _ _ _ _ _ _.1- _ _ _ _ _ _ _ _ _ _ _ _ _ "_ _ _ _ _ _ "_" _ _ " _ _ _ "__ "_ _ _ _ _

---~.---

ROOM'VIIE_8ur _WIT

ETH_CONN_BUS

-------

_BCSI_BUS


1

~OOH.SBOS

SH 8

_Cllmx:~~::~::=~~~
---1"--1---+.'
+t--+'
__
_'l.()ppv...u••• ,I.()"
_KlD-"SI_COHII_IU'cOII)C

I

_.!ltA..COOII_.U .... pc ....
_.!IUI_cH 39

_T~~~

ROOM.VIII..COInl

i~~1
VPP - UNIT ---

_LOC_BUS- ~

neFt

Dye'AMH~

epD 0

RY9,o9Poq,.-,

r.

L--..f-~.

3

r§

R

,?ye~AeQni2"

SH 6

I:C:::R:;BUS

-~~~~

SBUS_SELECT=3
CLK....NR= 0

ilVYf.

SIP



SH

LOC BUS

SH

;L

~~... IIUS<~~~m!_~_~

_SBUS


IRL

I

211
SYSEPROM UNIT ~
LOC_BU8

N"IRAlrbNIT ~

;

Fe:;;;.:
v

<

r'U""W~

... ~

c: c,_•••.., .. o;~-·· _DRAM_CODB_BUS
IRL
dCODI.
_HEH_ARRAY_BUS

>

0>

[~f~;~~c~~~I_~C~K~?U_-_- I.~~:~~~~~~

~~---

- AMIA.) ,
MAU

'of~

~"ii"'-~_UBUF

MEMoHAAY

3

-i

OM

E-- DRM "-1
~OOM'DPAII

SH 45-80

lS
DM

-.~~~~~...

_HHI

_HEM lOP _HPI_l

_MR

_HPI_Q
_OM

_CONN
oCYMDICC)o

4

JWI

5

~~'D~_ _ Y~·>~-·

:HEH' 1It'" _HEH

_MR

___

"-·--·---···----·--·---B-··---·-- "------ .-..

AOORESS_BUS=O
HAX_ROW=O
HIII_ROW-O
WO_PBR_ROWa2
ROW_MAX_WO.l
ROW_HIN_WO.O
BIT_PER_WO.J6
WD_MAX_DIT"lS
WO_HII'-BIT-O

BIT_PER_CHIP-.
BIT_PER_CHIP_.
CIIIP_TYPE-DRAM4H4R4 CHIP SYPE-DRJlH4H4R4
SPBEO=70IlS
SPEEO.70tIS

LOCATION=Jl
.:I_TAG_INDEX-1

ROOM.sau.

[WDEC'~~LiW?)

ADDRESS_BUS.O
HAlCROW.O
HIN_ROW.O
HO_PER-ROW.2
ROW_MAX_WOol
ROW_HIN_WOBO
IIIT_PER_WO·J6
WO_MAX_DIToJ5
WO_HIII_BIT·O

V~~_::_THRW

BOb'1' UNIT . 4IP . I

I

J.1P

SH 43

LOCIIIDEX.200----t:OCINDEX;;s:00

E2g~n8lJ2:~

~f~:;~~&ECT=4

I <~::OJ:~;BU9

DRM CONN

, _DRAH_COOE_BUS

MAC'XMEMCC>l_HEH ~t~y~~S

JTAG INDEX .. 3
r!.Jurr& PY2~OFUV£R'

19

SBUS-:SPC--t!im

SLAVE_UNIT
5'gn

SH



Y'YY"I 'tYKe RV2"'°'tVI.J'9....

I

I <:::n~BUS

POWERI

~

.. 5
LOC;......sUPP---..;--

S¥~~~NgEX

I I

SBUS
:LOC_BUS


"

2

LOCATION-J6

I

-CL~i~tft3

Ic::g6:: B_ BUS

J

20

LOC BUS SJI_~_

......

DOH

SJP

·~-;;--1

DIAG_UNIT

LOCAL
CLOCK""
~.~ J~sR83?1

I1

~~~~~~~-

VME~.~t~FACE

i ~§

_CBNTRlCBUS


~OOM.VIII_COIIH

LOCATION=J5
JTAG INDEX .. 4

SBUS_S~kECT=Q

;

'" =i1&JJ IIIii'II 1."~B~g;~~;;Z~,
IT

y~~~-

"

IP

2

SBUS_SUPP

I <:~~:~~_BUS
MASTER_UNIT

COMPUTERS

_.QR!\.J'illiG_

SHEET

ABBREV=CPU5V
APR/25/95 Manual

CPU5V

1

OF
94

REV.
0.2

c
--------------------------------

B
SB_D<31. .0>

SBUS SELECT=O
CLK::..NR=O

,I

SB~D<31~.O;~

.

SB_PA<27 •• 0>

,-1I1I..)'A<27 •• 3~

r<~~

11J CPU

58 PAen

00-1
070112
01., .. 0
02l.2U
01"121

I'A<37 .. 24~

S8"S1Z<2. • • >'' , _ " "m
" .

__ ___ ~__

58 LERR

_

_

Ohn
010.'
DI1.U
02 ..1"
011.119

M.UI 1110161 AI.1I1 Ahl..
Ahn
Ah2U Ah211 AIO.IU
AI .. an AlhUO Alh2n "lh2U
AI~::~~¥Z~~ ~~(f~4 AH.n

~

~1f~D
SB AS Io----==---._~

010121
0'"211
OlhU.
021.221
010-11t

OhU. os.,
OhU'
oll.n DU.IU 0110111
OU-IU Dlhn, DaO.UI
025.11& 0260120 DnolO

SB_PA<27 •• 0>

:~)-

Q>

Ol-IU
01...
01S.2U
DU.229
ou_nl

AI.2"
1111.10'
""0215
A2S.Ul

As.no
MI...
,..,.JO,
A2hm

Ah .. O
MhU2
AlO.IU
AI1o"

SilO-ill 11I1-n '"1-211

SBj.CK<2 •• 0>

ACKO-UJ '-C1U-I"

MOOdS' IIDl0ao, 1ID2d.
IIDI." iio,.u, IIDs.ao.
Mot.n. IIDh,.
IIDhn
l'/I)9oa07 1ID10olU lIDu.n
ND12.,O, IIDIIoU MOUoas1 IIDIS.UI 1ID1"153 1ID17'"
NIII"20t IIDlto" IIDIOdSS IIDU.,OI IIDlhU' 1ID2I.'O
MDUoUI IIDU.251 IIDU.IOI IIDlhU' lIDa .. u IIDU."
MDIO.211 IIDU.201 IIDlhlU IIDlhlU MOU.IO "DlS'"
MDJ,"I" IIDlh2U IIDI"'" IIDltolU _o.UO "041.2 ..
H04I'IU _hll' _ •• 210 IIOn.lI. IID'''U lID",,,
"04"111 _toU IIDso.a16 IIO"-IU IIDShlU IIDShU
"OU-1I1 IIDss.n IIDShUI IIDShlH IIDSh" IIDS90I11

l

>t
tJj ~O
q i!§i

M060.1I

ME~p!!!~~ !;";1~~'

Ul !i!

____

1

IIDn~~tf'X~l\ ~D~IO~S
llAo.n IlAI-US IIAJ-U IlAhU, IIA.-ii IlAS_U, IlAhtS
MAhlts IIA'."I IIAt.U IlAl0_IU 1lA1I-U.

Ul

ACk2.1U

SB_LERR

IOOOII'CPU

MEM D<63 •• 0>

UP

~G:M

__

D

RAS<7 •• 0>

J l

1tA10 .. 1

______

1tA9I0I .. nU-IU 'AShH ItAU.US

nss.uo C"~~~'J .~"3;!1

-

t A S O ' 2 nCAS1.1I CA82021 CASI.l"

RESET

ROOM=CPU

MWE

SB_CLK<2 •• 0>
CL1I.0_1I. ClJ(hlU cW.I2I

STANDBY

~g:&tti~

i

~g:&tt~~

r . A··. D···A···· P·····T····
1_

JTAG

!-

EJ--_~t1";""

NA
33R
IOOOII.cPU

ruo ct'
JTM_TDI
ruo TOI TllCkb
,JTAO_Too ~AO TOr TllCkb
~~~O~RS'l' 0
.rr.'- u_

3~~8:~D~ ~

JTAG_RST ,

.......

AVA

3 3 ORft~-· 111 I'LL BYI'

02 (

213

fMft2"5'7,-llIP-JV CNTL.g>

1t--l!nJi------'.:l·IOOOII'CPU ..... m
n ...i!1!l.!'LCNTL .~ ')
IOOOII.CPU

IOOOII.CPU

PA~27

<=ff

~~PU PA _ _ _

U!!~
hll!
VSE

iIL.B!i1'_________ - - - - - - - - .

11
18

n!.~t>-_--mI-'

PLC

CP3 ')--..

-~"~~=.:"~ - - 'O'''"_'"!O''''''

I

-

VALUE-1BH7

PI

f'l
M

&l ~

... ...,
M

PA<27

1>

OIWLCOC!-'cO~

i..

24>

___ . R D N~ii..» ____ 2.'!'
m.._Ul~J,.Yl~~_k
JlI§"YS'~~j)_'
___ R!1v NA~UMa'" _____ .
IHCPU.-!'! _ ... _ _ fi17~ NA .!!...fAc26>
...
s

... _
, •.

UI~fu_fM.u~_
._ . .Hi'},
...;'---'-s. D'
~"~_
... _. _______.~,
IUS;\:.U.-fM1L-___
'f~.N"S8PA<2t>
..~.
>

, ..•• '''_UJl;pU_Pt-~.) ---

'.OO)tIC",

IRL<3 •• 0>
c,_nATO_IIo c._nATa-IO)

fSB~CR

,235

t:J S¥S~!

~ 68
-'l05
-156

RESERVED

210

AL __ .TS~

3

··--SONOElCn=NK-

; _AD~~;;;-.~~~;;~RR!
_HEM_ARMV_BUS;
..:"t •. 0. r

L

...; HIIBUSADDR_l

i-

DIWI_CODI..,\cl. :....
DIWI_COOI..,\cO. ,_
DIWI_COOI_\AlCcl. I-

..........

~.'1't14_D<61

:gg~::~~~::~t

..

3K3
~ th--.ll}~!IT-~'L---illJ~.'

CP_STAT

«c.y

HC • U

•• 32>.MEH P,M D

R
llltli~f-!l-

SB pA<27

- . '-' -

at>

,

FLAT_DRAWINO. CPU_UNIT_l. LOOJC.l.1
JNSTANTJATIotll ICI'U5V CI'U_UNJTI6PI

---~·--"·'·"-'-~---·-A--'--~_ --=--'~[-"'--·'·---·-B·------'--·----

)F?:>
RJ
Hon Apr

c

: ~~:~::~~

~ MABUS_OR
I HABUS_WR

1M!

ABBREV=CPU_UNIT

1·[-:·-:1

ll~-:~

. . _. r'
~
...

. HII8USADDR_0

ARMtIJ~Q.

3 00:55,06 1995

/

::j ~~:~:~gg::~

9>

MABUS-,DATA

SK

DESIGNER:

9B SRL<§, 3>

HfiH A<11

88: HMB~J:: K>

8P:-~ILc.0. J-----!il'Jj:~------

'iii',

SPEED StlS
!1ISLVSEL

ulI-n Ul"" ABU_II

DIWI-CO:::~:~: ~~~_._

--'ll!loill"~iL~n ._!!...m.;t;.-.--1=-IllJU'''''''''~'''''''i!'~f.twU:t.J~.-_:.=_:~,

_6.V8

;XCODS; DwLCOIIl..lcl.

i

,

ROOH-SLAVB_SBL
ROOH=9LAVB_SEL
ROOH.SLAVE_SEL

ROOH-SLAVE_SEL

J4

GAL

r

ROOH .. SLAVB_SBL
ROOM-SLAVE_SEL
ROOH-SLAVB_SEL

FJ-=11-n...
F7 .....!.LJ1~

.IlcjillJn1:E~t__]J

2

._"ULY1-..

! j\OAPT~DiWt~coi>E I
i DRM-'C~D~"'B;m
I

n

:.r

I000H'CPU

146

IALC." "",.,,, 11IIl-ld'O IkLhU

SON'OER':':'A=NO

24>

14

1 C~1I0
Oillt
§UL ___________ - - ....t.=

@_c.1~~ ___ sW4"-------r.::::.= - - ] 5

PA<27

200

¥~~:~~~

CPUMB86904

pRAM GO 8 QU§\1

<~~----------- -- n

< > _.

J

:=:~~ rt:~~
~M I:L&l 1~1rt:~
l~~I~M

250

P REPLY

l

VIS_co",.n •• 212. 211. IU. Ut, 100.101.10'.11).'"
VOD_SlV.·a.I.I ......... n.10.1I.5I.II.II
62.1).101.101.101.121.122.111
vlS_Ievs-IU.12S.UI.lst.aU.ln.IU.170,112
In. In. i1l.I1'.111.11I.210.2U
VOO_OIWI.IO. ll. IS, U. n.lI. 20. U. n. 21. 10,
U. n. n.
7I .... n.n.lu.no
VI8_DIWI.15. n. 1I0.IU.ln.ln. 1I'.lta.IU.I., ...,
IU.ISS. ItO.IU, Ita. 10). lot, 105.112, 151

SPEED=85M
SB

~

r::t: ._UPLYO.",

".fl.

o

DIV_CNTL<1 •• 0>

'W!...2&'!1h---"'~a.
,- -U~l!
_ __ 6

24>

PLL_BYP
REF_CLK
OIVO • . , DIVIoIO)

It N'f~---------33R

F0921
IlICPU

I

r> EXT_CLK2

G~~:

S_REPLY

VDD_SBUS=VP5
VDD_DRAM=VP5
POWER
VOO_CO"'-210, 215.2".291.211.102.101. III. 115. no

JTAG TMS I
JTAG:ChK ~

JTAO_CL~

EXT_CLKl

CJ,J<~
HJN_LJNE_WIDTH-I0

3

JT.\O_THS"!

CPGA

td

JTAO_JNDEX-JTAO_INDEX

4

o

II " " I l l

100-"" 1Il1_1)) 1Il1t" tal-II' .1C.U tIlhlU

I

··-----r
:x:

J25

SB_BR<5 •• 0>

...S~:BG',g.:.:'b;:hlU ....

t«)'f_"'I-'L\'MI.tn

___ ~~E __ .

.,_"nO_l0 GP_IILl_'
------~---

SLVSEL<4 •• 0>

IILO.St .U.h'Ullt..).". ilL-hUt lIu_ne

2

·l.I!~

SP_SEL
?

APR/25/95 Manual

___ :1

COMPUTERS

CPU_UNIT

4
SHEET
2
OF
94

REV,
0.2

.------_____~_

13 .__ ==________. ______

..-1__

u ' .•

J. ' _____ ._._. ___ ~. ________ .~. __ ._. _. . _. _._.___ ._._..... o

1

1

[Q~~r~f:~'____
o~mtJ 1--l8ll1ijft:
tHe=--=
1
II.OOH'CI'U_CLOCK

..

i-

-

~

SPEED=42M5

Q2

VALUE-NA
SPEED .. NA

2

IU)O.hC",_CLOCIC

II.OOM.CI'USLOCK

j

II.OOII.CPII_CLOCII

._l2.~~JUl.UOM
HIN_LINB_WIM'HalO

__..{~~~

2

--

J12 .,

I.~~-

.!2ICLKHALF
HIN_LINB_WIIYI'HalO

l~~.r- _ .

._________CLKQJl!L

.---

HIN_LINE_WIM'Ha9

1l0000aCl'U_CLOCII

..1u).OO'

,.~LJ

T!IUI

1I.0000aCPII_CLOCl(

06

~

p:

'~4~"~~ J.~
1

3

3

35

.

NA

II.OOM'T!M_CI'U_CLOCIt

011

1I.0000.TEIII'-CPI.u:LOCIt

4

4
DESIGNER:
Hon Apr

~r[I~I~
~ \~J/r~·~.~ ~

FLIIT_DRAW 1110 , CPUSLOCK_2. LOOlC. 1 • 1
INSTANTIATIOtl.

L_______

CCPUSV CPU_CLOCK69PI

A

.J!J3.MttN.<;t

SK

3 08 t 54 t 45 1995

-,

B-'

-------·----·--··,-------c--I

tC::J

COMPUTERS

ABBREV=CPU_CLOCK

APR/25/95 Manual

CPU_CLOCK

SHEET
3

OF
94

REV.
0.2

a

A

________.___,_________

_ __C~_ _ __

D

1

1
P3
VALUE=\VALUE

SONOER_A~~~~O-OFF

r--

FSB

10
aND
G- __3 ___ ~~~<1>
0-- 2-___~ ___ SB 0<0>
G-- _1-____ SB O
G- .!3_____ ~
G--

2

u_---IDLD~lli
27

SB SIZ<2>

G-- 29
SB PA
0-- n ______Sp PA<4>
)0--- _~3 ____ ~~
G-- .1.~ SB PA<10>
G _~~j.J.~
G-- ----.!L

SB PA<16>

tl-_.~~JA<1~
SB PA<22>
()__ L...!J

1 G---

3

SB IN'J.'<1>
_-"--_ _---=S~ 0<2>
'!'.___ -.SIL.:tNT< 2 >

__SL_____@--M

~o (J- _ _iQ. _ _~S_'L~G< l~

o

G---I-J!L----~Q< 1 >
G-

_~~ _ _~SB

0<5>

1 G- .-l!L __ J B 0<7>

00-

(jj_4_L_~A<24.~
7 f)-- _3.L _____ ~B OP

~_4_ _ _ _ ~lLO<3>

o

.SV

o
18

0--

h4

II 0--- --'~JI_~Z

G-...ll-....-.BB INT<7>

a

~2 0-

a
G

o

_9L __ ~~
42_____ ~1~20>

I --

G._- __~L.... __lUJ._ACK<2>
G _.. 46

____SB

_~~

0<15>

SB PA<23>
SB PA<2S>

SB PA<26>

SB_RST

-12V

~OG-

o

Ul

ffl!

==8

il=D~l~--------~ ~t8t-B~

SIZ<1>

'!'..------~ ~B:n~T

_1UAili

~B CLK

S8 INT<7

82_ _ ~JL~~~~

t:>.
2

I

r::...

~
~

,Q
fi ~

~SLOT CLK
-{>SB_CtK<7. ,0>

b

d

SB_INT<7 .. 1>

§'.~B:Ba~~ : :o~

SB_SEL<7 • 60>

OND
..J!L_J..D~

_SBUS

.SV

90

I

dSB_ACK<2. ,0>

iB~~"--:-~~--- ----b. S8_AS
i~~===---~~~o¥Dsa
~---'----SB_LERR

+SV

.I

SB PA<21>

OND
94

~60

, SB_PA<27 •• 0>
! SB_SIZ<2 •• 0>

.

.SV

OND
18

,S8_0<31,.0>

SB SIZ<2" 0>
SB ACK<2, 0>

1!!_~S8~

SP

0>
0>

SB PA<27

.5V

74

0-

32

o-1.l-.-_-l:!.P ACK
G-- - 38
S8 PA<14~
(}.

0
0

SB PA<2>

SB LERR
40- __
14_ _ ..SJ3 PA<8>

20-

aND

o I aND

G.- 22
S~
G--- __
2_4_ - _S1LlNT<6>

G

S80<31

60_+_ll___ SB 0<20>

SB 0<21>

_2_0_ _ 1I.D~

0--

SBUS-SELECtL~~M~=~Ek~~~

8 0 - _~_8___ ~_~~

G-

o

aND

G-

o

S~<.lli

0- _..19_
SB Q~h
G- __ LL ___S.a 0<25>
__1.L_
SB 0<29>
G---

_L-~BR<1>

~.--~~ 0<1.§2

70- - 17

5 G-

_49_ _~lU~~K

3

SBUS\I

SB PA<27>

+12V

4

4
OESIGNER:
Hon Apr

FLAT_DRIIWItlO. SBUB_COllle4. LOGIC .1.1
INBTMITIATIOIl. (CPUSV SBUS_COI/N6PI

-----------.-----p;--- -------.-

----r-

.. -_.....!-

-----s-----

-c--

SK

J 09: 54.31 1995

hOt~r[[e
COMPUTERS

_.QlY\llJ.t:lJt

SHEET

A88REV=SBUS_CONN
APR/25/95

Manual

SBUS_CONN

4
OF
94

REV.
0.2

r

A

,-----

.__ .___. _L ___ ._.. ___.__ -='·C-~~=-~~~~

B

___. . .

~L._

._____ _

-

D

.---.~.--.----

........

1

1
P4
VALUEc%VALUE

SONDER_~.~AND_OFF

rv.-

----

FSBt
10

E=ND

G. -

3

G-' S
G I 7
9

G-

~!L$~J..~~~

70- .

o

11

SJLI!.9..2l:

._!L--....S.tL1>~

G--- u ----.-sP D<25>
G ---1L
SD I!<29.:!
50-

0.

0-G
30--

25

~.-P~~

u __ SlLm<2>

SB

'M.!i~

0-- .11......-.....::mJl\~_~
G-- !t.__ 'sD PA<16>

3

~0G-

~_1__ .S~ PA
() ___..L_.__ S~_rA<2~
1 G-- . _li _ _ _ SD D~

SB INT<2>

sa D<8>

10

G-

j~B INT<3>

0.--

M _ _....s~ D

G
G-

sa INT<4>

16

.. ___S~D

_20

~9~~4,!_ _ _S!l..£.r,..t«0>
0--. __
51_ _ _ ~!LM

SB INT

§--~ D<2>

80-- __ u

D<2~

SB INT<5>

G- _.JL~_ 'sa~7>
G-- lL __ JULINT<6>
~6G-- ...1_6_ _ SIL~

G-- ... ~!L _ _ SII PA<2>
0-sa LERR
~4

G
0G.
G-

J.! ___ SD PA<8>

36

SB ACK<~

38

sa PA<

>

..!g_ _ JnJ ACK<1>

~2G-- _4l_ _.J1!LPA<20>

0 .. _....!c~_.2JJ~~~~~
G-- 46
SB PA<26>

~80

~OC+-

o

_.21_ _ _ lHl_D<1 >

o-+~

SD

~ 7 o----l--n

S~

59

0- .61

G--

(I

sn

D<17>

__ S.ILI!<18>

65

~ __ ~D D<22>

SD RD

SB D<31

o

GilD

G-

1!~_ _ .JUL~lli

o

tSV

o
n

o

.SV

1E[~SD~
G- -~~>
~

PA<13>

87

S»

PA< 17>

89

SB PA<19>

91

SD PA<23>

93

SD PA<.25>
SD RST

~2

r
o

'SB_PA<27 •• 0>

SB SIZ<2 .0>

iSB_SIZ<2 •• 0>

0>

CiSB_ACK<2 •. 0>

SD INT<7

f5V
'1._ _ ~A<.22

d

1>

I~

~ ~,

I

I;

SD_INT<7 •• 1>

PAd5>

_SBUS

I·

GND
94

2

I'

SD_SEL<7. 60>
'SB BR<7 •• >
SB:DG<7 •• 0>

GilD

~j'"

~i

til!

§'.

0 0- .~ PA<21>

o

00·

~~I<~·Q.~-----::i;~k~~r;~~~ .. 0>

s.uMh

8~

60

-12V

SIZ<1>

GilD

G-~-'-

'SB_D<31 .• 0>

SUS----.---------r.; SB_AS
~ - EL<2;;-·-·--·-·"-::: SDO~s'L
S
EIUt------ ----=R ~k L'eRR
~R~~~;-~~:~--~~SL~-"R
lBj~~ - ____~___;~K~n~¥G

GilD

~4;_ ....1~»

0>

SD PA<27. 0>
SD ACK<2

.1..~ __ ~_Q.<~6>

SD D<28>
D<30>

SBUS_SELEC~L~~M~~~Ek:~A

__ j_8_ _ _ ._.S_B.-P~

~6 8-- ._~L ___SJLD<20>

!--''-L..-_-"S,-",D D<2 4 >
\~,-~_____S~

~~2>

tSV

8 0-.

SD D<13>

63
5 G-

D
33

_._2~ ___S_~J!R<2~

G- __8___

29

0--- _H _ _ SJLl'M1~

113-

0 ..

SD D<4>

J~_ _ _ SB_P..51i~

G-

0--' ._.L._

~~~

G---~..l..-----.S~
0-.....1.L _ _ .mL~
0 .. - __ .1~ _ _ Jm~~

2

2

r--

3

SBUS\1

SD PI\<27>

.12V

4

I)

---.l
DESIGNER:
Non Apr

~fl)rJ
~ ~\~_

FWlT_DRIIWINGI SBUS_cotn,-J. LOGIC. 1. 1
I1ISTIINTIATIO'It CCPU5V SBUS_CONNSPI
--~--------------I'

'

B

.... _-------

. J~IV\W!N
(1_
9

7_______1m D<4~

0
..? ___._.~.~Jt<6>
G- 11 _~_p~.l~

o

SB D<12>

13

G_··1L _ _ .sJLP~~

70---

-1L_._._:ULD~l~

O--U_--~ D<212:

G-

2

_.!L..

SB D<2~

10-- ~_3_~!!?!

2

8-+..L-- _~lm~~~

5 G+2-~--. SB C~.K.<..Q..~

....!... ___ )HL~<2>
0-- __ ~_ .. _ _SB INT<~
o G- _.!!........ __IDLP<8>
G-- u
SB_INT<3>
G- ...!! ____...SJLD_-tl...~~
f)--

0-' _.ll._-.S1LINT<4>
80 _l.!I_ _ J~k

G.-

G
• 0--

______SJLM

6 C-"- ....1_6___ .sJLB~l~~

-.lL_~_P5~

(.:.- -.tl_--···--GiiW
0- .H) __ ~_Q~?

0-_I~_7

L __mLIN'!'5:~

1

G*c

S~J)_ili

ll_ _
ll .. __ ..-----l!!LP5:1?

G--- _35_ _ _ SB D<1l?
0-. _~1 _ _~~~_~J3>
0--.

19_ _ JlJLPg.1~

SB 0<18>

41.

.l.!L------..SJLmT..<.~
~SB

D<27>

~-~

_..2L._.SILI~

SBUS_SELECtL~~H~~8Ek~~i

(\- ...lL-----tGi'W
48- .1.L-_ _ ~D<9:>:
'3-- 3_L_ _ _ ~

'-::-1G-

SB D<31 •• 0>

3B _ _ _ ~JU~g~~

··4L--·_--MmiJ

, SB_PA<27 .• 0>

SB SIZ<2. 0>

: SB_SIZ<2 •• 0>

SB ACK<2

..3'--.-.l1ILP~ 2 0>

0--1..3 4 -·----tEJ
o--l-..4L....--·--SJLP.<26>

SB_D<31 .. 0>

SB PA<27 •• 0>
0>

(\ SB_ACK<2 .. 0>

I~.I
~ .
Cli

SB-B~3~-_-'--8"
SLOT_BR
ILlJ l?~_._.~. ___ <.) SLOT
SB
...,G
S
---------0 SB_R~

~~ ~.

<3>,,---,,"-::1 SB...RD ~l..
~.. ~ "
- - - ' - - - , 0 SLvT... Sr;
... - - - _ _ _ .~ \ SB_Lc.RR
T.

::l___ '_ _ ~ ___ -j SB_DP

rr

~t.UE=TH~BHFD2
FNP

1 (}---

_L _ _ IDL~lli

G

_3_ _SJLS.lZ.<2>

I}-

5

_~PA<9~

G-- _7_ _ _SILPA<4.~
9 G- __
9 ______IDLPA<6>
() .. _1_1_ _ JtB~<10>

3

(}-__

13 ._.........Jm_~~!=12>

8-- - _!i. ___ ~~~<16>
1 1) ••. _.!J_____ .l?P..-f!\~.tQ?
() __ !J _ _ SJLfA<22>

.) ____2.1____ .~HLI'A...~h
) I"}.- _.1~ .____ ... ____SJLP~

'0
GG

S8 INT<7

S!~~

SB PA<~~
~J..j:.RR

B

_~_S~<8>

G _!n.!!.._~~'~..ACK< 1>
8 j - 4 - ....!! _ _
SB PA<20>

_~!l.

2

.

2

,

I'

__ @

d

1>

SB_INT<7 •• 1>

d
S8 SEL<7 •• 0>
S8:BR<7 •• 8>
a(j SB_BG<7
•• >

SB
_mLUIT<7>

G.- ...J_t __SB..ACK
__ !L..-__~Ul\.5:.H~

,; ..

~

SJLCJ'-~----~::B:~k~~~~~~ .. 0>

G- ._6____
00--

~:
Ul'

SUhi·----·-··-ri SB_AS

s

--4.!1----.-Nm§J

Ul'

~~
lL_~JL~
}~. ___
S~A<1)~

lL __

~B

PA<.13>

~UA<17>

__:;B

ACK<2~

PA

_36_ _ _ _
38

_SBUS
S8US\I

mm

3

se PA<15>

~--Mm2J'
42
SB PA<21>

0-_[.--u----Wiii2J

0-~~---. SB PA<2~

G- ..J.!.. _ _~IL.~A<~.'l~

40-- ...14-----H2BmJ

8 G--. _4-B_ _ _ H2lIEl

4

4
DESIGNER:
Hon Apr

FLAT_OMWINO, SBUS_spc_comcs. LOOIC.I.1
1"81»ITIA110". ICPU5V SBUS_SPC_COI1N58PI

------·-··---··--··-A--

-'-- ----.,...---_.__ .-

-····B-

--------c-

_Jl~w.mG.

SK

3 08,54.26 1995

~~~i[l[
\\:::J.~ .~ U__

U

SHEET

ABBREV~SBUS_SPC_CONN

:J

COMPUTERS

.• ::J

APR/25/95

Manual

SBUS_SPC_CONN

6
OF
94

REV.
0.2

B

A

_ _ _ _ _ . ___ .____________ _____

D

__ _ _ _ _ _ _ .1 __ ._. __ .. ____ ._. ___ . _____ .

SBUS SELECT"O
CLK_NR=O
SB_D<31 •• 0;!~--------------------------------__----------__------------------------------------__________,
SB_PA<27 •• 0>
....., SB_SIZ<2 •• 0> I
(::Q
I
rn SB_ACK<2 •• 0> 0

1

I
r:....tl
P-t
.....
Nf

~I r:

,

iii

I

"l!!...!UCIC
II! AS

B
§..

IRLJ.' 18

D,

L::

§

.~

---

SB_AS o-----~---- --.D SB RDl:-________________ ---ll.JY! _____ ----- --"t
SLOTrSEL
12
SB_LlERR
_ _ _ _ _ _ _ _ _ _ _ -SI! LUll
.SLOT BR
SLOT-BG .
SB ltST
------sa lIST
a~r~1
K
Sn_DP ~.
SI!
1 K

SLOT_CLIt(L
SB CLK<7 •• O><}SO INT<7 •• 1>

2

NA
K
'K
, OK
I OK
I OK
I
OK
~ 110K
-m 110K
-R~ II NA
f
,.. 10K

_-!u!I~
_______ ~r- R9R"S
€!M!Iili________
,.!!.!!~------- R§~2>
--- _----1 -- N§ L( .. SI! AC!!."
.--~- iW-

I VA'
! (;"1

I'

ij-- 1I.!i1 18

~

til
h

SO-SEL<7 •• 8> I
s9 BR<7 •• >
SB:BG<7 •• 0> •
SBUS
1

Ddl>
I .... <30>r---M!~~--

'·'H'''''_'''_'.'

.i ~

.""' ....,,_ ..._,.,
.".....".-"'-,..

•

.«M ...·"_ ... ",

.""'·.IUS_"'..

,

·s

8~
OK
8~

::~

."........ _.u

I'"

:::::~::::

I

·"_.u

i

''''''''''U_'U

•

~

I'Xft"t'JI.tU .. ''''

1I-:C.SI!
nn-<2~J!~. _____ ------,.....!l..P<~ ___________

J~>-~l-o>------~-----l nr-

• .,..........,._.',
• "H...

:

------~-j

<13».-S8 o.lb

-

'~:tt·"'·JfI .. tt.I.ln
1I·... :te·U\J ... MI.III.

''X'tt'1'I''J,.,u.,4'I'

OK

<16>!-!~!!-----------W- Nf<15>r-!!.A!l_5>_______ ~_ - - - - - ;
nlJ<14)1_.l!!.R;!lR- _ _ _ _ _ • ____ ----*l_·--

" .... H.U·U, tv. I'}'
It'XtI· .•• ')s .• u U',

.~,;;H.~.'JI.t\I.IOr.

O~

g:m----------·-r n§"

1

IIXtl·',,'J,.",_I<',

18~
8

--------5"-- H9

III,

f!I'):M'U'JI.,.J.l0,

K

<11>L.~~~ ____ • ---------10---

'_'S"".'.

n:: :::~:

0K
OK

I <19>'-~!'-·-----------_r flr!M <18>;-::
ng::-_

."",•..,•. tv.'"

":'-·_oH.~"}J_ru.

1

<22>\-_
----------1-- N§
<21>_"1! 0.21> -----.~ ----1- Hf---

-~ <20LSI! 0.20.

C
_

J

".r<27>~ --------. ----. _._a __ "r<26)L_!~lli_. ___ .. ___ .____ .__ . __ 1_. iU---

<23)1-~~~~*----------t- ~IJ~

.

''''''.SIV'.•U
:::::::::~

." •• BII<5>
• BII< >
II!
< >
S!I BIId>

-·-1-

<29>\-.D~U~~____ .. - - . - --!.- ..

<24>r.!1! 0.2 •• - - - - - - - - - - . - . - -

'''''''''U'_'''

>

-.-

-·---···-----·t- II
<2!1>'_~M2~. ___ ----------- ----.---- lur.
<25>'.--~.1~------------------.-__=l- iU'- If)"

.

;
,
,

c>

.n II! IIIT<

J

'
I 0 : <31~f!.8

'·.

3

ADAPT

_SBUS_200

------------al'
1
.ru.E, Kj

ABORT ~MI'
KEY t ___
HQl\!_,
------1!l!L
~ f
RES P P
_~.L.
R78,'
i PLUlflIlIO SB RsT
§.=_JlI! lIST R'IL...-_________
i SBUS
1)'SI "t:L!S<}-i  VSYSCL~_
;.
.

JrnO

0K
K
K

09

~OlO
l
"~lL ~\ '"
r
~08

3

TOAA

-J------- -------

1ICY.ft.U'JJa IOI)
'O(tcIJt'JI~IO"

III OCfl I saU' a 100
IIOCtl_5I<.IS.JOt

.,S47

1

IIXtc·S.')J.I'.'"

'.:'H·U~'_'U"

£
rl

4

4
DESIGNER:
Hon IIpr

IV

3 011154,33 1995

f(~[lE

FIJlT_DRAWINO, SBUS_SUPP_6. LOGIC .1.1

INSTANTIATION, (CPUSV SBUS_SUPP52PI
----------B----------~·----

c

COMPUTERS

_J!.IYWflNQ_
ABOREV=SBUS_SUPP
APR/25/95

Manual

SBUS_SUPP

SHEET
7

OF
94

REV.
0.2

1

~

____
.
_________

~

_ . _ . __ • _ _ _ _ _ _

~

_ _ _ _ _ _ . • _ _ • _ _ _ _ L.

.

B

A
----------------------------------

______

1

SB D<31:0>

>

DO~108
oh119
016-153
024 .. 4

D1-109
09-120
011-154
025-5

D2 .. 110
010 .. 121
018-155
02h6

03-111
011"122
019-157
02"'8

04-113
012-123
020-159
028-9

05'115
013-125
021-160
029-10

~B:~~
SB PA<5:0>
19:Tu ll:U9 l~:IU
fPz~~1~~<:I~~?139
SD ACK<2:0>

01=118
015-128
023-2
011al2

EN~~ ~X

EN T RX

ENET_CtSN

Bg:U B~:H Bi:U 8J:n
SCSIs8s1:g~

SB_AS

~g~I:~~~

~R:~L

~gn:~~R

PQFP

~B:RgT

~

ENET-ERCL~

SIZ2-138

SB_LERR
SD DR

ADAPT

ETHERNET

ENET£TCLK

AC.rn-137 AcKl .. 1l0 ACK2-129

2

06-116
014-126
022,,1
030-11

E~~¥TT~Hl

~~=~RvCS

(:>

~

S§~~tM~g

I

SCSI;IO
SCSI ,..TN
SCSCRST
P_D<~:g~

p_DsY

~IR~
_SBUS
SQu8 \I

PpA~~

J2

PpS~~

p_s[c~~I~
p DS~D~K
~:Rg~:gIft

.5V.
VoO-'.17. 24.21.33.51.97.
98.105.114.124.141.156

d

OND.

VSS-l. 13.15. 20.30. 36. 41. 55.
69.70.15.81.86.92.93.94.102.
103.101.112.111.121.143.158

3

~~~~;·N';';~':JTAO_J~D~l!. •
JTAG TMS
___
61._
..
T JTAO THS '-~A
----.
~
..-JTAG
ADAP JTAO:CLK-'t-___
r:TDO---=~
11=1
JTAO_TDI.
rur:::T1Jr='1'DO<~
i.

JTAO_TOO
JTAO.,RST

-----'""J'l'~S~

O-~-

--~-- --

_______ :19.

P-~D~~»

SCC XTIN
SCC,..XTOUT
FPY ~\..~tC~~

FPYF~~~4t~~I
Ft~YxU~2nIN

~~~g-~~~
g~~g:~g6

g
_

I,..

~_
____ ---{

SCSI_REO
SCSLACK
~" SCSLHSO
~, SCSI_CO
_ . SCSI 10
--SCSI:ATN
-~------(J SCSLRST
_~ TERHPWR
_ _• •

SBM89C100

i:m

.

J

~_g;7 •. 0>
P:BSY
P_ACK
P_PE
P_SLCT
P_ERR

ADAPT!
SCSI

-

,

_SCSI_BUS


I

2

SCSI BUS \ I

I

ADAPT ;

CENTRONICS

~ ~:~~tIN

_ _ _I P_AF
1 P_OS_DIR
P_BSY_DIR
_ _ - ' P_ACJ{_OIR
-----i P_O_OIR
.lD_CS

1--__;

.._

-

-

-=-0

·
iii

FPY_CtK~~  \ I

hti:t= fttH:ar::::< ,SCSLD<7 •• 0>
-_
.-==9.
:g:~:~:L
_ _ ~ SCSI_BSY

00-35 01-H 02-32 01-31
D4-29 05-28 06-2601-25

PIRR

',.,

_ETHERNET_BUS '
<)(ETHS> :

"u., ..

S8_CLK

. . . .. I

D

._.L

ft"'"

----0,

u_

_C!Im\X_BUS

!

cJl:cnrrs)o I

CEtlTBX BUS\I

3
I · · · ......,,"---.

s~~l~x~~3~

'--------

4

4
DESIGNER:
Hon Apr

W-(Qr.-1) [[ [E

FLAT_DRAWING. HASTER_U}IIT_'. LOGIC _1.1
IIISTANTIATION. (cpu5V HASTER_U}IlT8PI
"--~A--------'-----I---'

SK

1 00,55.ll 1995

-- -- -------8·----:--------

·-----·"r--· -----c ---

COMPUTERS

.. ~MWlNQ._
ABBREV=MASTER_UNIT
APR/25/95 Manual

MASTER_UNIT

SHEET
8

OF
94

REV.
0.2

r-----

A

B
.- ------------------------

J_._------

________L _______________ ._.P. ___ .. __._. ______ --.-- __

c

.--_..

1

1

---~

.,
..J
S

SCSI_D<7 .• 0>
SCSI_UP
. SCSI-SEL
SCSI-BSY
SCSI-REO
. SCSI_liCK
SCSLHSO ,SCSLCD
-

8

2

~

LL~__lIIIT~US. ~21 I>I-'n~-HIN_LINE_WIm'Ha35
RooK-SCSI_POWER

t

o ~g:~:~~
H

SCSI_RST
-; TERHPWR

!

1

2

ADAPrr:1
SCSI
I

SCSI BUS 1
-  !

SCSI BtJS\I

!

HIN LINE WIDrH-25
-

ROOK-SCSI_POWER

cl

--

+ CE16

lOOK-20T_120.~U-C-l.V-T•

•""".,,,,___

,

'OOH.'"'--'''''''

3

3

.

-.

4

L}

DESIGNER:
Kon IIpr

f=t]~)[r~~
.~./ ,"[.::::1

FLAT.DRI\WINO. SCSLl'WR.B. LOGIC .1.1
INSTMITllITIOlh (CPU5V SCSI_PWR24PI

--- --- ..

~-------

A

·-I-__.-~

B

._--------

SK

1 08:55.14 1995

I

c

COMPUTERS

_PRAWlJI.G

ABBREV=SCSI_PWR

SHEET
9
OF

APR/25/95 Manual

SCSI PWR

94

REV.
0.2

.----------_ _ _ _

~o

______

A

__H

B

••• _ . _ _ _ _ • __

__ L_o ___ '__ 0__ 0__ 0 _

~_

-C _________o_L_~ _____ o_. __ 00 __ 0_0000 ___ 0_ .

D

1

1

14Wp----12.)~ATERM BACK
ROOH·SCSCVHB_P2

T3

____
.,_ __

~------

~:

--~~*_K7~->===~~-

;::~

T7

rt=-=-=-1t~t~~~====:-~=l
!! PWg20
--_0
< >

2

J

u.

----

_

~CSI

0<7 •• 0>

-SCSI_DP
SCSI
SBL'
SCSI:BSY

I.

----i~

o_~

l-A DAPT SCSI_REO.
:g:~-~~~ ~
0--_-- -

I

SCSI BUS\I

l-SCSI
I
I <:~g~j:~9
!

SCSLCD
SCSI_IO

:g:~~:.:

TERHPWR I

----- ---

-------l

1118

T PWR2
TPWRl

T9

~~
T6
T5
-

~~

PW020

T2
Tl

<)

Etl

ao
--r
•
0_~lL9-+__
o

-

TI

L

SW6

r:---- _}

-----7--l~!' C3LDorr~----

TLUII-3n

SCSI

TERMTI

VALUE=lBH7
OFF -> TERMINATION ENABLE
ON -> TERMINATION DISABLE

~~PWR

3

2

SCSI

TERMTI

- ___-_-_ -

+

ROOHoSCSI_VHB_P2

T4

-

_

~

BII

~L22I!~2IS

Tl
T2
ft

< >

I=b

11

3

100N_20T_1206

-1~29

I""'"' ' .VH'-'

rom

4

4
DESIGNER:
Hon Apr

FLAT _DAAWINO I BCBI_TERH_9. Lomc. 1 • 1
INSTANTIATION,
L............-~_.

(CPU5V SCSLTBRH61PI

-0--.-0-----0- - ---o-----------------r-ooo-- ------.0------0.-.--- ____ .____ ----,-_____ 0-0-----.-_
A
B
I
C

SK

.0.P.RA~lNQ.

3 00,55:52 1995

f(lf)[[lE
~::-_/

.,

__ :I

COMPUTERS

ABBREV=SCSI_TERM

APR/25/95 Manual

0

SCSI_TERM

SHEET

10
OF
94

REV.
0.2

___
A_

B

_~ ______ ._. ___

J_: ____ .

l_._. ____ .__ ~_._.

C

D--.-. ____ --0.0--------_··

... S. CLASS=IO

... .sm:t:t,.D

"-"'--~!'F~~~-~:h~r,
P8

1

:fSCSI

. __ P.Ql.Q.~s..L~p_O~O:> __ . _._~6. J_'_n
___ llQJS.C;;S.I_fLP~t~ __ . . p ... .J_!._n
._ .. U.9J_$~S.LFP_Q<2.>... ___ .__2!1 .. J.'_. [)

21

HIN_LINB_WID'l'H-e
HIN_LINB_WID'l'Hae
HIN_LINB_WID'l'Hae
HIN_LINE_WID'l'H_'
HIN_LINB_WID'l'Ha8
MIN_LINB_WID'l'H-'
HIN_LINB_WID'l'H-'
MIN_LINB_WID'l'HaB
HIN_LINE_WID'l'H.e

ROOH"SCSl_HACIO
ROOH-SCSI_HACIO
ROOHaSCSl_HACIO
ROOHcSCSI_HACIO
ROOHsSCSI_HACIO
ROOH-SCSI_HACIO
ROOH-SCSI_HACIO
ROOH-SCSLKACIO
ROOH.SCSI_HJlCIO

HIN_LINB_WID'l'Hae
HIN_LINB_WID'l'H-'
MIN_LINB_WID'l'H-'
HIN_LINB_WID'l'H-'
MIN_LINE_WID'l'HsS
HIN_LINB_WID'l'H-'
HIN_LINB_HID'l'Ha'
MltCLINB_HID'l'Ha'
MIN_LINE_WID'l'Ha'

ROOH-SCSCHACIO
ROOMaSCSCHJlCIO
ROOH"8CSI_KACIO
ROOH-SCSCKACIO
ROOH-SCSI_KACIO
ROOH-SCSLHACIO
ROOH-SCSLHACIO
ROOH-SCSLHACIO
ROOHaSCSI_KACIO
ROOHaSCSl_POWBR

C
on

f----.
-(
'r---In

D<7>
>

< :~
< >

< :~
< >
p

lfHl
C-I<-

8ft

n
8ft
OR

II

__ .L1..QJ.s:_l?L~P_Q~~~. ___ ._~_
___ HQ) ~tG~1;_f.~P~~~._ .. ...J-L
__ .-J.tQl..~~_~J_r~Q~ __lL
._U9.lJ!~J!I.-f.~1;l~§~ ____ ....;Jl_
_._ltQ l~CJtLf~~l~ ... _!L

HIN_LINE_WID'l'Haa
HIN_LINE_WID'l'H.e
HltCLINB_WID'l'H.8
MIN_LINB_WID'l'H.e
HIN_LINB_wunH"a
HIN_LINB.WID'l'HaB
HIN_LINB_WID'l'lIaa
HIN_LINB_HID'l'II.a
HIN_LtNB_WID'l'H.e

HIN_LINB_WID'l'H D 8
HIN_LINE.WID'l'HD8
HIN_LINE_wIInll.a
HIN_LINB_WID'l'Ha9
HllI_t.tNB_WID'l'H-'
HIII_LINE_WUnH-'
HIN_LlNE_WID'l'Ha'
MIN_LINB_WID'l'H-a
HIN_LINE_WID'l'II.a
HlN_LINE_HID'l'H-20

pi

.0 SCSI F
~.

)<7>

< >

I.wp--l-..

ROOH·SCSI_FRPL

ROOH~~F
3
S

11

Til
Te
T7

~o

"' TPWR2
TPWR1

-----d] T;-..- H
< > ~_~ ;~ PW020 EN
! §
.
" :-: m!.~ t-T4
I)
~
. :g, S :::~l
< >-=::...
~~
TLm,·m

"j. !

.U~.

~ ~

18

S

_1=1
9

!

lL..}---

YI

~

[J

_

S

P

SCSI

T1

Tl

: ADAPT

~SCSI

3

.

SCSI BUS\I

ruit-=~!jU:igm~f::imfr==-=-:='Jttj ~~
fl

: _SCSI_BUS

;~

,  AUTOMATIC TERMINATION
----------.--J ON -> TERMINATION DISABLE

'01100

4

I}
DESIGNER:
Hon Apr

FLAT_DRAWIIIO. SCSI_COtR'-10. LOOIC .1.1
INSTANTIATION.

ICPUSV SCSI_cotmtlP)

L- ____ ._ _ _ _ _ _ _ _

~-

--

~----

____ _

- - - -..- .~-·-.-~~--·-·~._-~·--·----~·-c--I

3

_J;!~N:mG.

SK

oe, SS, 32

1995

r~~[[E
COMPUTERS

SHEET
ABBREV=SCSI_CONN

APR/25/95 Manual

SCSI_CONN

11
OF

94

REV.
0.2

B

A
-_._------------._------

_ _ _ _ _ . __ -1._._ .• ______ • ___ ......•. _ •. _•.

_ .. _ _ •.• ____ ---1. _ _ _ ._____. _ _ _ _ _ _

_P..... _ ... "._._._._. __ ... __ ..

1

1

~.;, :".R)~__ ~_

ITERM~~~~~_ ~ J~5
~(330R)~

Nl

I~~

~

- f - - -e

~

'l'
I-~-:l
3

~

lnA

G

~; ~~

(220R)

I TERM)

(330R)

_ADAPT_
ETH_CONN

21

J15

"

ADAPT

I

iETHERNET

I

0

I

_ETHERNET _BU8

I 

BNB'l'J,UI
ENET_TENA

B==

COL- . COL+ETH
COL- ETH elL-I~H:E8t-P-'I!Il!.M!!~~!.L-'-i
COL_M
COL+
_.J.!i..•. _ .... _. _.. __ ..• __ !!l!!-~!JI~'tIWl!.~!4!. .... ~. COL_P

TENA
t- Ji
LK

EN:~E;:~~ 
-l COL_M
COL_P

ETH CONN BUS\I

-i

2

2

-l TRA_M
TRA_P
-l

T..

,-""~,~.,,

.~
.
'iA'F- "'-"",-",~."

I .>ND., 1

1

.B.'PT

OHDG

""U-,,~,,~,"

+ CE19

c

100N_20T_120

Ej'H rOWER

IU_D_25V_TA
0

I

:; ft~8:~
: ETH_POWER
.., .TILGND

OND
MIII_LIHI_Nllmton

.

01100

3

3

4

4
DESIGNER:
"on Apr

PLAT_DRAWING, P.THEIUIET_POWER_l2. LOGIC.l.l
ttlSTIINTIATION,

(CPU5V ETHEIUIET_POWER20PI

-.------------

A

----_·---·1--_·_--·-·--B-------

,---

SK

1 09,54,40 1995

ft]~Y~): I[ lE
c

COMPUTERS

_D.1~~WJ1fG._

ABBREV=ETHERNET_POWER

APR/25/95 Manual

ETHERNET_POWER

SHEET
13
OF
94

REV.
0.2

L

A

B

.. ______.____ . __ .1 _____ ._._______

c

~

___ J

~-

..

-~-.--

...

D---- ..----

1

1

P7
.....m:J].F;k!L _____ ~_I--

, .J.nAPT_

!<~k"'l'R~~NN_BUS,1
'

2

W
-----r.. _ _ _ _ .___

8E.~~ §IB!Fl_
"1 _
FETH
_~

..

_~___
_ ______
-.0)2
U
--~-----'-._---- ----.. --.-~
88t:~ ~-.. Irn-c -=------------- - - r--~ ___ . _____._ e'3 1011 c.-- __

ETH_CONN ,

ETH cOHN PUS\J

.

'

__ .!. __

.

THc£8f::

TRA_Mr---1BliIlHf-

RBC_~ t----:llIl:l!oo-\I
r

TRA_P:

REC_

ETH_POWER,I

£ON_GND t

ETH POWER

.---.-------------- -..

--·------~1+___

.__ .__ . _ _ _

2_.

r.'.

()-

3

'_' _. . _

-- 4.. -'04

___ .__

• __ ... _ _

------

2

J..L ___ . __

___ ll. ________ _

'.0 5 120_ 13
130
-_-_-_L--06
Ne 1.. _ 1 14 (>__ _-''----- __ _
.__
-0
15 N
De 150CON
J __

~SUB15../

GND

------

....
VALUE=THRW
SONDER_A=VERRIE
SONDER_B=NA

3

3

4

II
DESIGNER:
Hon Apr

ffJf? II' [~~~L

F LAT_DRAW 1110 I ETH_COtm_STO_ll. LOGIC.l.l

IIISTAtITIATIONI

(CPU5V ETH_COIIN_ST019P)

.--.1\----------------,

·-----·-····B-------..

------r---· . ---

.PMw.nm_

SK

l 08: 55,18 1995

":::':::.'

c

;.

__ •. _J

COMPUTERS

ABBREV=ETH_CONN_STD
APR/25/95 Manual

SHEET
14
OF
94

ETH_CONN_STDI ~~~.

._____ ~._- __________-' ___._________~___

iii' , .. -"
________
~rL ___
---t-

~
-~... _ ---~--~
_
___
_ ._

.~ > - 4 - A6
A7

87 -86
85 _
----~--~~.
M
84 J~.J!5.f~--r- Al ,) OJ
~___

D~?.--g-

-___________
-----"P<>
2"
,!!...
---'-.<"-___
__

1

- - --LD_DJR

?{------------~JL

.J14

~!;;MTR

A2 " "02
"
_

EN" _----------?-.~~l-n!
~_./
..'

e

>

0D>R

-

If-~:J

_ ___

.-.l;mL.R..!!::.2..-____ ..

. -

~IU:iIB

I'~ ____[

0>

U<1

.~,

~.

.. - _

_ •

-

>
-=~J>

A8 -

~


X< >
D

AJ
- - A2
A1

(1

lK3

7

.--- - ·lllru~ ... -}~,

J 13

P_QILt>1.R _ _ .... -- ---.LI~~C~iiJ <.4_

!'I !'I

-

s·

---~-. ~T125

~OOH'CDm_I'II_IKI

R:ml;--=

C

'JI0



--12-C~b<6>

A7

V

J7

-

I
---~
__ < >

ROOM.CENTRONICS

"....

Q
QQ
M
MM

P~>

J13

L~~,~._o..llF_D~.NY _~ r~~;~2S ,_. _6_ 0, _... - - _[0' _______ ....CJ;;M'rR_DS

CEN~ - - - - - - - - - - -

ROOM-CENTRONICS

_w_~_

-

_

RooK-CENTROIIICS

~~>
--~-_
_!:fIrnLD
-H~~~+
--- --- - --.0
----

.'-

___

D

C
3J<3

ENTRONICS

"-J;"T'Hll~-------~~!I~------CENT
< >
_______
_ _ _~.
_

AS

___________

_-=___ J. _____ .___.__._

J13

ROOH-CENTRONICS

~Tiyo.1.:tJ.1.U~C!UNV.2.~~~_.! __ ._. __
lv
~~~J7

1

0_ • •

___

. _ ; . [• • _

•• _ _

C~~j'IL~CJ<

.

P_D<7 •• 0>

------<) "_DS

----,

~
M

ROOH=CEtITRONICS

ri

P_8SY

~ LC'f'===-":w!
~:::~~K
.._. __ ... =-: P _SLCT
____
-'
- n~
~~ ___ .NO __ .___;
J

I

_.-l'-:-tJS~II<_ .. _
._

q~

~JL __ ,

c _. . -----;::
___ ... -'in
_________
_ .1.,

'

ADAPT;

---.-----------.---.-- A

;;~t

3

ItOOH.C°mL",_'Kl

--

39

100P\=
__

RooM·CENTRONICS
ROOH=CEtITRONICS

. _____ .

IOOR~}

8

ADAPT

-CENTR
- _CONN

C:SLCT

C_I!RR

g:::~r:T-1tI :~~.~~v~~:

I4

CEHTRX COHN BUS \I

P_ERR
P _IIIlT

P_SLCT_IN
P 8SV DIR
P:::ACK:DIR
P_D_DIR
ID_CS

DESIGNER:
Hon Apr
_cvtt1lX_aUl

---

SI(

l 08. S5 .42 1995

1

1 R::P:[lE

.rxcbrrs.1

CENTRX BUS \I
'---'-'-~-B-----'--'-

,;,!ii.Y--...JP'

5
----

C_ltIIT

.

PloAT DRAWING. CElITRONICS 14. LOGIC .1.1
(CPUSV CENTRONICS26P)

g-~~y
g::~~K

CENTRONIC""
i:l:

~:p··rnnm{:'--== ~=~tDIR
_~

JNSTAtITIATIOlh

............

_.. _L 1,~3., ""

ROOM-CENTRONICS

C_DX<1 •• 0>
C_DX_ENA
C_D<7 .• 0>

AND THE PARALLEL PORT MODE IS SELECTED.

II

RooH-CElITRONICS

_

J14

~MEI8~~koao~ ~8~~gTl8 ~~~~EFgnI~CIO TJ~T

.----_RJ.11:

6

-~----- .-(}:{A~~.l~

-----U-~F~~~7._-

ROOH-CENTRONICS

ROOM-CENTRONICS

:.-..

j141C ACKINV

ROOHcCENTRONICS

SL T
9 ~O~~8
P SLCT
C.e.N'l'IL -S;-~--J'----- PACT~I------.~---- """-J16
lK3 In ---}.....l9
ltooHoclim_M:l1tps'lB

:::

12

ROOM-CENTRONICS

ROOM-CENTRONICS

J-.-.-L~~~-

J1.-/"~

II

_......1jjl.cmtTfL~~~1I

CENTILPE

-'f-

J13

c

COMPUTERS

.PMWJt.{G.

ABBREV=CENTRONICS
APR/25/95 Manual

CENTRONICS

SHEET
15

OF
94

REV.
0.2

B

A

n_I~k~~l

s~ ~'31 .. 0>

L:;~!:

- -- --

________ . ' - - ____ . _ _

01043
09.52
011.63
025-n

00.42
08,,51
016a6
024-1

02e44
010·54
018-64
026-73

Ole45
011-55
019=65
027-14

L: 0>

SB D<

'~OT

SS_AS
SB_RD
SB_SE

b

SB_INT<7 •• 1>

SB INT<-"

SBftSBL<7 •• ~>
S" BR<7 •• >
SB:BO<7 •• >_

2

01

1.>

........1. ........ .

§I

XFLOP~>

SER DTRA

.--------, Ir~i

SB_IN ~7 U~.lS6 IRQS.155

SER:RTXC
SER_SYNCA

SER_RT
-. ----...-----.---.- .. ; SER_~9~

~~~:¥fil

i4 IRQ3-153 IRQZ-152

_SBUS_200

>

c~Dn8~I:~D8~

~ILRST R",..

'§:

<

'§__

VPP:~~I~~~t_

.

-

JLV

POWER I"AIL

0),1

f·. .·
In

()

1LL

.

Ri, 0>

~~-ft8

_KBD ~~~nEg~

EB::wR ~s
NVRAM. CS

LINK TEST EN
. ENET_IR~
SCSI_IR

~&nO~

VDD PAD=VP5

GEN-RI)"'i

JK
TIir'
-

RES PWUP P~•. " .• " ....,,,.....
RES",PWtJP h
·
RES PWU... REO n
RUN_HALTrtED ;:.

--.--.---VOO.:.CORE=vPS----1

-

,

·'. BM SYSFAIL_LED<
SuV SYf LED___
8> ': USER_L~R< -:.
SEG~

Fi

4

, ADAPT
!,_DIAG

===-o!T~!J:.::
OO

.-'l'Uo'i

J:t'A(f

QJTQ9~~'
--- .-'l
Ml_!!!1

_oITf\O

< >

rlft

VOO_COR£,,22.l2.10l.1l2

JTAG
JTAG-''
JTAG: ~~~

[

.

CP41 CP'
ItISTANTI AT 1011 , (CPUSV SLAVB_UlIIT9PI

KBD MSE BUS\I/3

.-.', CP38

~--'-1-"finJll
IR
- -mJ., I
< >~IL ______ ~¥.!I I

11I
I

....: scc XTIN
_.J SCC-XTOUT -

ADAPT,
CLOCK!
:J.'-n~:~~2a-6ITT

r---.. :,SCC-CL~
04

-- --iifjCI'1} '1" _____ 1

r--t

,_. _ _ _ _ _ _ ..__

--;

LR22---·----·--f">FPY-CLJ21"
-.-l--~-l
FPY_XT 2_IN
'-:, FPY_XT 2 OUT
__TllUkl~____ . __ .. ~==-==-~::H~-8t~3:l...y."

----.-

='i~:~t"l~bU+

OND,

~:::~~~~!~O~~1~~1~~j~~o~13·141

_CLOCK_BUS 

CLOCK BUS\I

I)

ABORTP t..
·
ABORTN ,_
i_LOC_BUS
'

FLAT_DRAWING I SLAVB_UNIT_1S. LOGIC. 1.1

SCCrC~K

FPY_CuK 4
FPY_CLK 2

LINILTEST EN

---<->---

VOD_PAO.19.53.68.95.140

RD_ItOTARY ()

~~~~~~["

-

IRLO .. 117 IRL1-UO
IRL2a129

.SV,

JT G TMS

--zI.A0 THO

sm

MO¥~1~n~

_LOC_BUS·

----'

,p5

llL___

ItlSiRi~

-

o

SYS_L

SER B BUS\I

KDD DIN
117
__
'KDD DIN ADAPT
KBD nOUT
9
- - - - l KBD-DOU r
_KBD
MsE DIN
___
' MSE-DIl'l
M S E l ( U O U T y - - - - - - - - . - J MSE-DOU ~F _MSE
POWE _OFF
- - ' POWER_O

06-139 05=138 04-137
02-13S 01-134 00-132

EB_D<

SY~Q

~~~:~§. C
R BUS:
-~l SERS>!

.~] POWER P_IN

>

GEN ltDY o----T~----Tlt;t"'CLK
..,..,'t--------~~---.--CTRL
vrPINV'
-._

12

SER_CT

07-1

'---,..31 i _ A DAP£TB-~Dru>
EB:WR
~_
LaC N=_CS I ---~PROM::Cg---,EP~~tr:8~ --~~~_
i

SER A BUS\I

SER:TR C

N~ _ _ U..111d

, CS SYSEPR< •• >
- ED A19 ORaG ~
EB;A<21.. > IED D<7 •• >.

BUS;

'-f:IiAA--ff-·-------~ ~~~-8l;j

RES PWUP
I nlllfllllO SB RsT R. ~t5
1 _SBUS
~~~'S]t
I 
."

I

C

c

R

SER_TX:

1

<

IAL'

_R

3

J

ABORT_~~¥ L

!

MIIU.IIILMllmhlO

APT:

_B~I 'APT'
IALi

_ADAPT
_SBUS
I
:

FLOPPY BUS\I

!

IROl-151

_SBUS

i

SER DTI

s~~RTRi8A

<>

IRQ1
IRQ4

EL
'
-~==.-----.--------.-l FPY_~~ PPY
BUSi

lUll

11

t:!t'
~'
I

______ ~ __ .__ ...J FP'C~ ,TA
.TE

lH:t==='~:::-~='~Hi:DR~ ~L
r;--------.--: FPY_MOT

~

FPY MOTEN
FPY_15ENSEL

TYP

SD_C

-~~===__====:_:~ Hy:gn

~~

n~-tm~~i~

P QF P

SB_RS
._ _ _ _ _ _ _-'uuA'-[>

=-==.:--==-==--=-~ H~:ffiE

~~yS6¥~

1\0-24
SB_S! :2:0>
SIZ2- ~ S!Zl a 81 SnOe8l
SBJ\C '~C~:'85 ACKO.86
ACK2 ..

49r
Sa-:sEI;
S~i:fg

SB_AS
SB..AS
SB RD ~SB KD
SEL Q-_
SB_tERR P

.. _ _ _ _ _ _ 1 - - - _____________ . _ _ _

Y._ _ . _ _ _ _ _ _ _'

F~~Y~n~i~

~~:~~ •

>

_

FPYyDENSENSE
FP DISKCHG
FPY_WRPROT
FPY_TRACKO

_CS

SB-PA'

1

c

04.41 '-05';-48 -06;49" 01.50
012-56 013-51 014-58 015=59
020=66 021=61 022-69 023=10
020.76 029=71 030.78 0l1=19

_.1 4 t t -1 MMCRE

l

~E~~X

l.lI!,· MON M
-

I·_PM~J~Q._
Mon Apr

JTAO_1I10£XcJTAO_INO£X

ADAPT "Mi_,"' _____. __ ..........3.'
~~~~:~~~~-=-==~:=. ~~~ ~~LTOO<2>

CP42 CP43 , -JTAG
. . .

SBS 8 9 C1 0 5

• ;()'f~ "'".'I.'.'H1'1I)1

i-

__

JTAO_TOO '. ______ .__ .• __ •..,IT~9.-'!'.!!I_TOO
JTAG_RST i~I_. ______ -!1.T _G_Rl.iT

-------'---8---

-·-------c---

1 08,56,09 1995

C-T]1F '-])~ 1[1~.-) l[IF~
[r,_~J
COMPUTERS

ABBREV=SLAVE_UNIT

APR/25/95

Manual

SLAVE_UNIT

SHEET
16
OF
94

REV.
0.2

B

- - - A- - - - -

---------------

--- ----.

__~_ _ L

C

-~-

_______________ ~ ____.____ _

--~-

1l00H.QUAAZ_SCC

---~E~tJ.r-------~~

I ADAPT SCCXXTIN '.------- HI1LLI1/P.JIlMIIal°
:-CLOC SC~C TgU~~::::::::t:::!~-

1

:
r
-

:
I

.
I

I

I).py XT~t ~N

------

-

_1I1lLL'1/P.JIIDI1IaUl_
JU1I.J.llIUtJ.DDWQ
--

"""_""'rL""'U!PY Cr;K3~9--TIM CLti'''f=--

MU' !III.

_CLOCK_BUl{~LisfJ(}T r-- -~=~
!

r.r 1
1

___

"'''DIaL.__

IIlJ1.).111P.,J11IL-

-

SCSI XTIN

---SCS

-xTWr:h
OOK.QUAAZ_ICSI

OOK'QUAAZ_SCSl

_.j~3i..

r=;E~!'32M
..

I~~D=40M

~~I~

---fIDThN~4
lOR
ROOK'QUAAZ_SC&I

~

·_·_u'"' -.....~.. -

.,

~()()'hQUAAz_scn

n==.=J 09

-an_ NA -- ~OOK,~1~g
C231\
0
~-lIioN :';',y, ~ ~:.

CI,QCK BUS\I

~OOlhQUAA1_rPYn

~OO'hQUAA'-SCsrC1~11

J

----------------~~~~~f~~~'L--l
- -- - -1"
ADAPT

_SBUS_200
'ABORT_KEY
jNMI

'--1......,1"--L->'' ' O_Q><.!P'-' 3'---_ _ _

h RES PWU~EO

(j SJlJSJCJ<

-·=~::.-=-=--:B:VSygCLK

PLUnnlO,

SBUS !
.  r

4

r-D-E-S-I-G-N-~-:-S-K-----~Ir~-p---~-~-ij-G------------~-S-H-E-ELT~
Hon Apr

3 08,56,18 1995

F(}:":[[

FLJIIT_DPJlWmG, LOCAL_CLOCK_16. LOGIC .1.1

Jtl5TI\1IT111110tl.

SBUS\I

0

SO

1

3

ICPU5V LOCIIL_CLOCK65PI

---·-----B-------------·----l--·---------c--

COMPUTERS

ABBREV=LOCAL_CLOCK
APR/25/95 Manual

LOCAL_CLOCK

17
OF
94

REV.
0.2

A

r--

;L~ ---~

---. -- - B~_~_~~_~_____-~~_~_______~_L ______________________
C _____________ J_

- .. "--.- -D- -------------- ----- -"-- -

II

CP29 CP2B
ROOIIaLOC

J6B

-lHI....!'Mn? _ _ _ _ _ _
. ___

~~~: ::~n;_

___

.---------- cH4k-

1

_.

---------.I!u~~n:--:-=-=-----·---~~\

---ll..f~!.I_
••_ _

H81t.=':~=__==~~.~~~ ---------,
=»-l-JLMl~-- .. ---.. --. ----/

--=:

__

SB_D<31..0>r
SB_PA<27 •• 0>

U)

fij

81
I

~

~

• SOP

Tll.J

2:0 U<27- .0>
,.I

llOO11aLOC

/~

SIlPAdIO.

-~

/ It

\~

I-i

J67

.j 20
10

II

_

._.!!..~_"H.?
__
- -. __
-.. -----)
.. _!I!..~_U~
___
•. _~'_'

L.._

"',

..ItA =m~t~~:~:~=~I'

L

P

'501'

Ee

A<23

Q>

i

~ Ii

2

~o¥~s~Q
SB_uERR(1

SB_ASO
'OOIIaLOC

1-

SLOT_BRp'

s~gT1'tB~t:

,II

SD_DP >SLOT_CL~_

SB_INT<7 •• 1>
SB SEL<7 •• ~>
sD BR<7 •• >
SB:BG<7 •• >
SBUS
.- .

MONaLOC

b

'§

J66

=tt::!.: ==~~=-~-==-~~\
1t1
JfJlitf~~!~~0---------.J

"'18

____ SJLBM.____ _

SB_CLK<7 •• 0><)-

-

c

e

SB_SIZ<2 •• 0> ;-

U) SB_ACK<2 •• 0>

2

=tlt~th~m ~ _=--=-~~_=~:.:_~.::,;

~

L

J

1

_'

1~~t~_-_-._--~=::~~___ ._1~8_

~E:&«~&ECT.O

.IU~_~~._._._. _____;\

li7AmJftr&C-~UF-"'-F--_ _---.-t-<

R17~

33JUt

lSOP

B.TJ.ll

,

I~B~9~Y~BUS> \I

3

3

v.-o'l~''ftl·'LUH'lltJ

RD DRAM CODE ~

CS~~yJ~~~~I:
:8~ 8
EB_AU ORIO
'
EB A<2J' •• 8> :

K
... ': ~': ~_
--~
_~J~===. -_Rl }', 18OKK
DeS.

EDt!lD<7.. >
_,II D,LOC BUS\I

I

4
DESIGNER:
Hon Apr

- --. -- .. ----

I'LAT•. ORJ\WII/O, LOC_BUFI'_17. Loare.l.l
JlISTIINTIATlON,
L.. ______ -

------ -- -.

W407~:[le

--

(CPU5V LOC".BUI'1'41PI

____-------,

--------A_~~

-------'--8--------·--·------r-·--

SK

c

__Q.~~;I_~q.
ABBREV=LOC_BUFF

J 08: 55: 44 1995

COMPUTERS

SHEET
18
OF

APR/2S/9S

Manual

LOC_BUFF

94

REV
0.2

a

~~U:NR~~~R~NA

1

JT~O ...JNDBX.~J'I'A?":"IH.D~X·I

~

~

A

I

!SB_ACK<2 •• 0> P

SB_SIZ<2 .• 0>

I

.

JTM_RST I)

_TRA_VME


_: VDDIR
....J VD<31 •• 0>

SONDER......I\=SOCKET

1

SB_AS
SB
RD p'

SB_tERR (_I

~~gf-B~ ()

I

,iii

SB RST
SICDP

~~-AS,!,
t-

VA~I~. ____ ~VADIR
.. 1>
'VA<31 .• 1>
CjVLWORD

~A<31

J6

SBg SEL<7 •• R>

~B:K~~~ : :~~

§

SB SEL<4>
'VSCON
IJ.

,.ClJK

:<:j~m:!

_SBUS

._ .... :1 :.~~~S

VD::J

~2:O;

: >

:J>
VD::J.

_SBUS

_ADAPT
I
_8BU8_200 :
ABORT~~lL-=~~
PLUIIB
.. 1110 SBRl~TPW~P
_!rue

SBUS
VSl l::L
 VSYSCL
.. .

0

=m11>
Ll>
_ <

§--

. ' . . . - ...

.>
>

U

io

11
I'i
S!OOOO
-.
..
HHHHf'l • •2f'l00

@U U
~8cK/IO ~ :1

HH

.~r"tr~~.H.\'~~I.~

I

I

DEBUG 1 PULLUP 100R MSI!HBLI!D

~~~~: :~~~ g~F

[IJ

i21

~

~

H

til

DI!FAULT. SWITCH ON. PULLUP NOT ASSEHBLED

TPENCLIWY J- .. GElOll!Y':'-=:=
CTRL VPPINV
VPP_SW1TCH L
SB_RSTa
.,..LOC_B~S;

t.:>

I

<

- - - "

p;

~~

~

,
stv SYj_LED 1 _ _
iBM_SYSFAIL LED< •• 0>
,
USER:LED< •• 0>
,
R 7SEGM 0--'

~

~

- - - .

_.

-

~

UJ

DONE - S

R

<)

VBERRI
VBERRO
VRETRYI
. VRETRYO

a

VIRQO<7 •• 1>

t.:
o
M

~

dVIACKIN
i'j VIACKOUT

~!

I

2\

("j VBRI<3 •• 0>

'" ~ _

" VBRO<) •• 0>
() VBGIN<3 ~ .0>
VBGOUT
VBBSYI
VBBSYO _. VBBSYO

VALUE .. IBH7
SW8

1f·~GH I

3

LCA;~~;E~~O_] ~~~~~SRESETO

I lor~_4~ _ _ ' ___

VSISYSRESETI

VSISYSRESETI

~~bttT~T=~--~ gl~~I~lt!

VALUE=lBH7

~

2

VIRQ1<7 •• 1>

VACFAILI
VACFAILO

~3Ht.l!~~§ ~~~~~~I~6

VSCQ=
.. ______________~

.... 1 ...... .

_TRA_VME

u -, "
.

~~

./



"

Rtg~n~~~~ ._......::...rr=::--===-.===

S_W~

10K

.J VSYSCLK

~p!. . ~O~__ ~g~~4 .. 0>

1.{~full--H1

IHNTh---G.u CC[Jorrr-----· _. __ .. ----·----d VSCON

_ADAPT
_TRA_X

i

33R

--VALUE .. 1BH7

TRA VME

1

,

-

BODY...TYPE·PLIIHBIlIO

VBERRIVS1
VBERROVSI
VDTACKDIS
_ TIULVME

:~~!~~S \ I

.-----

SK

---~-C·--~-'

.J~MWl@_

ABBREV=LOC_SUPP

3 08,55,02 1995

fOF)r[[~
\\J ~ -~-~

FLAT_DRAWIlIO, LOC_SUPP_18. LOGIC .1.1

....-

VME BUS SLOT 1 FUNCTION
ON .. ENABLE

I

4

:<_:::YP'l'._~R.Ql _



TRb VME\I

INSTANTIATION,

,J

!f-11t~orr~ o~}_5

~~

:::;S

_,

)

I---lllUtcX'MODE
I
RESERVED SWITCHE~
FOR TEST PURPOSE
SW

:::>tibibUJ

'VMADIR
VDS<1 •• 0>
VWRITE
Q VIACK
uVAM<5 •• 0>

~o

CP68

~..

PROGRAM

I"1l
~

8

~ VDTACKDIR
_O~.-=_..rl VDTACKROE
__.. VDTACK

-

Iol

~~

llI----

RES
PWUP.
... (}--_
RES
PnuP

'RUN_HA~¥St~~i:-~~~o--·-

• -

- 1'\
H

CTRL_~Pl~r

'_ADAPT

IIIIHHH22~

10

_6

t!

3 I ,_ADAPT U--llll~=-H-­
: _LOC ~~~:gl' ,~,~m~~SCS

:I "'("_"fl.",,"IIII'

000

2
-.. .
1\

18
POCKfig =if

0>

'lASD..11L....! VASDIR
Yl'!-S-_d VAS

"6

M

C~Dgg~I??I~_-< OOH>
•• 0>

!
! CS_SVSEPR< •• >
!
EB_A1hoR G~_
;
E~DAD.

PQ100

10

~~>

11

LCA4003A

10
10
10

:1>

\I

_ADAPT
_TRA

SGCK/IO 76
DIN/IO '-'5
10
10
10
10

PGCK/IO
10
10/TDI
IO/TCK
IO/TMS
10



.-]TAG TJ!I_TDO<5>

C6e~

SB_INT<7 •• 1> 0

4

. . . 1 ....
1

~~~~:~g~~~

SLOT_CL~_SB CLK

1

---=,"6 )

EPROM1765

SB_CLK<7 •• 0><:....

I

CE"""0CEO

~

PH

-.

~LOT BEL O--~~<4>

~ ~

2

1,14
[-r-I
gt~A ~2i.'PP ~-'-MimJ
~~~~ I I ~

JTAG TMS

··ADAPT ~~~~:~::~.=.tI:~-:-TDO<4>
JTAG JTM_TDI
JTM_Too r--::t+RG:+tit:TDO<5>
__

I.

D

---~---.-----~~-~-----------~.--

11-

SB_PA<27 •• 0> ;..

C-t'
n.

c

IOOr'Jfa·n.VHlltJJ

SB_D<31 •• 0> ;...

til
~
til

L __.

._ _-----''---_ _ _ _ _ _
B___

A

COMPUTERS

APR/25/95 Manual

LOC_SUPP

SHEET
19
OF
94

REV.
0.2

r---~------------

A

B

I
-L_~
_ _ _ _ _ _ _ _ _ _ _ _ .__ ._. __ ... ____ ._ ..

1._--

-.L- - - -.. -.---.. -------- D--_."

C

-------

--~---.~.-.-- ~ ... --.. -.- .. ~.

ONLY ONE OF THESE BLOCKS CAN BE ASSEMBLED

M

o

1

~

r---------------------------------------------,,
,0
,

1~

i

ROOH,,,,_HAX

CE2

-

,

33U_D_l6V_T~

,

~

.J27

1

ROOMoVPP_MAXD23

~!'

2

2

J69

ROOM~VPP_MAX

.tt-L]--r--~ ----.------

:

PRLL5917

C2

:

-Jiil""'OVPPJtAX

,
,

2

2

I
I

L _____________________________ .

r-------------------~r--------·

I

,

I

,
tcOy_",,-rt.W1ltJJ

;

...

1

CDDB8~{?8~ R

I
I

3

l2!!!3--_._-L

,
,

1

_L

,

tffiW

L g g J2
t6:=g0 ('> 0g_ L-M2BlEJ
Mmm

,
'

1--·
.1._ 0
0
:12iii!§I
,
1
1
, _____________________________________________ J ,

cs_slg~Kr9 6RI~~
EB~<2'1 •• 0>

ROOM.VPP _SOCKET

I-

:. -LOC
AD;P~~iG~~~r:

mm -...

EB_WR

~:g~
G~tt5~

1i

~

C~D~~hn~

,
SB_RSTO
. _LOC_BUS I

3

--.--------------'

~:~_L~~E_WIDTH~:~ ___________ ._ _ ------L:VP!'-l!~J'!~.1:I _______ _
M

o

I

LOC BUS\I

eEl

rl

~

c;.-;~U

l~

D l6V TA

I -""':_T
ROOM-VPP

ROO,-"'_""'''
4

o

DESIGNER:
Man Apr

.IlMW.lNQ_

SK

1 09: 55: 50 1995

f1'I~lrle~
,~))

FLIIT_ORIIWINO. VPP_UNIT_19. LOOIC .1.1

'0• • _J

IIISTIINTIATION. (CPU5V VPP_UNIT5JPI

A

4

[

B

--------I·--

C

COMPUTERS

__ J

ABBREV"VPP_UNIT

l\PR/25/95 Manual

VPP_UNIT

SHEET
20

OF
94

REV.
0.2

r-----

A

h

__

, - - -

-==~--

B

~ ___ --=---~==l

_________ ____
-=~~=

C ______________

l ___________________ _

D

J22

1

r-_ _ _ _ _ _ _ _ _ _,_ _..£j:IiiL.~<:..oIo.Ju....U!.:>:,..._~

FLASH EPROM WRITE PROTECTION:

8~F~I~E~~¥~CTION

J63

r--------. - - -. ---- ------~--~-~~Tlr 6

'20'BOOTEPR
-----~-

mt--r1iT'J1I~OR

~

~

SW6

18

L

VALUE .. 1BH7

~

ROOM-BOOTPROM

1!!I~d'>

lSI

~ ROOH-BOOTPROH

~

••

M

1

m:,J: :::;
At·,
AISoJ

. ! - . - - - - - - - - - - - C S BOO1'51.,"
__ -~4~'- CE vcc.\2
Il
B,rrmnr.mITE?-4 OR CIID.16 Alh
.-----------1..-- u__ !Yv.,u.. ", __ U/:' WE
M:a~
AiloiO AI-n
J201'VPP AD1pr
---1---1------1---- - __ u ___

------------¥2OUV

A7.'

D7.21

:~:to

DI-,'
gl:.l

AlaU

Dl.,1

g::f~

-----J----LS~~:D~~5~~~7~SJ~ER:i:sOCKET
:~=

ROOH.BOOTPROH

ROOH=BOOTPROH

rn:rn, NA

CBL132
o

~

ROOH-BOOTPROH

II

t

~

12M

2

---------J

ROOH·BOOTPROH

1

-------- --FEPROMaXK2mr--A <11 •. 0.
PLCC
0<7 .. 0 '10'1_ _ __

~I

~

2

i
J26
1-__+

___+-+_+___

.-2--

(,W,..'O;:<:.&Jt..a..;....v..>::;....._~

--.--13-----~,
~QT
-U
---

-ate eE vee-I

~.l.T&J!4"..

--- - - --

-

_1(_

______ J ~.QJ.vpP A~.Pf_-l
~

:-~

FEPROM8XK 256PLCC
D<7 .. 011-_ _ _..

A <17 .. 0.

AIS.'

OE 0110.11

~1'1:n

m:u
A a-I

AhS

~t:,

AI..

~:tlo
~~~~o ~::u~~

WE

Dlon

a
gt:
:
DI- l ,
gJ:U

g&_:~~

SPEED=150NS SONDER_A=SOCKET
ROOH·BOOTPROH

ROOH.BOOTPROH

CBL131

3

______________

L - . _______ ~LWR

~_

F.BA<23 •• 0>

3

NC
--4, .....

• UI

' -

RD DRAM CODE
BOOT
csCSS'lSEPR<
•. 0>

8

t~c==:::±::!---------------------------------------------------t----t-------------------------I
________________~

EB-A<2l' • 8>
- EB
A19 ADDRL
ORI L
EDER<

!

ADAPT -~g-~ ~---­

-LOC
-

NVRAM:CS

EPH~n-8~ ~
TP~NdWY!~

CTRL_VPPI~H

ROOHQBOOTPROH

'-!L.!!!I..Mtt>

"P~~'f.Cl! ___________ . __ -------------Rl.~_nw-----vn

VPP SWITC ;--'------------ ___ --'!L
-SB_RSTO
LOC BUS ,

4

LOC BUS;;

I

-----tUThNA:--------

4

ROOH-BOOTPROH

DESIGNER:
Hon Apr

u ,~Uo

A

r-----

------.-----13·· . -- ---- 0-0. -- ---.. --.-]----.0--- -. ------C----

o. __
J

SHEET

ABBREV=BOOT _UNIT

li=n1' 1[' n~:=:

FLAT_DRAWING: BOOT_UIlIT_20. LOOIC _1.1
INSTANTIATION. (CPUSV BOOT_UNIT49PI

__DJVWU:t:I~_

SK

l 08,56:26 1995

Ll

COMPUTERS

APR/25/95

Manual

BOOT_UNIT

21
OF
94

REV.
0.2

I

A

.....J.

B

.l. ___ "" __'._...

C

••

D

_______ • __ 4

_ _ _ _ _ 0 __

ROOHcSYSEPROH

J57
>
1

1

·.m.m.lle --FEPROMBXMlTSOP
0-'
.. 0 .JUl..J2S1.
AU.'
Al_11
OJ.'I
CB
IIf... Dl:P
Pt·,.
:A2&·t o Alt'f
AI:' 111:1&
OB ~f':I' M.f, ~hn
g"11

0>

1\ -n .. 0.

C~PR

9 - - --_ ... - ---·n'w
r--"---====JSEPn-mr-'--"'-'---'n'w
--~
WER~ImWN---··-··n··----'n·--~-""'- ... ---.--- ".
.-.---~

r-_~~!·n.T.~.tL. ---·------r--

1L

~~ AI...

MO'"

m:l

~::u

AI.U
~&:n

PhU

CA:n

1

~~... CIID~~~~;~i'~~~~~_~~~' .H_

"'1

--'.- CBL129

'.

-cilm

CP2

ROOHaSYSBPROH

ROOH=SYSBPROH

J58
<

'A21.II;o;h;;·--FEPROMBXM1·) EB D<7
-21 .. 0.
TSOP
0.7. .0>J.'\-'_IIIIJ_IoI....j_"'--_
.....

>

1\

FttE-'--JlCW;;O>------__

_.
(2l)SYSEPR ~--'-I--"I------+--

r

2

-.

m:!

--~-==.-=--=~:.. ~:o 1116.4 ~um
11.. 16

___ ~S.wJ.T.C1L. _______ [ ___.1.L

mn glm

1.0.24

yPP ~~~~OE~;f;~~~1

:'Ji CBL130
FLASH EPROM WRITE PROTECTION:
ON=WRITE ENABLE
OFF-WRITE PROTECTION

~~I!~)~L_'_I

2

CPl' .

I

--..J

ROOH-SYSBPROH

SW6

l

PO."

ROOH·SYSBPROH

3K3 ,.~ _ _U!.l POW.e:JLMmLl_·_· __ 1

-ED:<>::J -oiiJ-~~"'-LU1SYS
VALUE=lBH7

•

3

'~7('

CB 'AlO."
'1\21.40
>u.(' OE

0>

IIU'l 1I1·U Ph'l
~1J:' 114'30
~,:U Ct:l,
1112.'
Dhn

~ ,00'.''''''011

~ ROO••"'''OO.

Q
M

Q
M

~NC
....../'u.
"~

.. _._. ___ IDJ_WR
_ _ _.. _________ _

I
EB_RDF-

c»DD8~I~?D8~

~

•• > ..::.
, CS_S'll'SEPR<
EB_Al hORIG

;
i

3

E~DAD<7::8~~·::::::=+::::::::::::::::::::::~

EB_ADDRL

ADAPT

. -LOC ~-~ - - - -

;-

~
________________~~
____~__________.______________________________________~~

----.-----------

EPROH:CS

G~~NRfi~'

!

TIILCLl<_<"'-.
CTRL_VPPINV·'_.

vPP-~~:ft~~ ~.---.-------- .. - - - - - - - - . - - . - ..--....

4

--.' _... __ ..... _______ 1

4

_LOC_BUS ..
LOC BUS\I

I

DESIGNER:
Hon Apr

flJlT_DRAWIIIO. SYSEPROH_UlIIT_21. LOGIC .1.1
INSTIINTl1\TIOlh

(CPU5V SYSEPROH_UNIT51PI

1\

I---··---·---S-.. -·.-~-------r-----·c-1

SK

3 09.55.34 1995

f{tJF?:[IE
COMPUTERS

.P.MW.HtG.

ABBREV=SYSEPROM_UNIT

APR/25/95 Manual

SYSEPROM UNIT

SHEET
22
OF
94

REV.
0.2

I

A

r-

B

.1~

C

____.... __.__...

D

• . _ _ _ _ .0 _ _ _ _ -

____

~_._

ROOH·SYSEPROH

J57
'A'I.A'O,IIC
cu .. 0.

>

CU;PR
9 - CB
~-----'--------"E
- . - - - - --- ---Jr8
r---"--'~-~1
SEPD-:wJ{'-----"'-'---'Jfj'0
-----:-:-=1
WERL'UOWN--··-·----12'· WE

I

1

- - .~- ..... - ••. - - - - -

,.--.---.

r---""_..¥!>L.~J.'r.c.tL __ - ' -

-

1\

-

., - PHD

'FEPROM8XJnTSOP
0.1 .. 0 ~
AlhS

:A21.!0

AhU

0>

PhIS

Ap:l Al:l& "1:P
AI'"

Aloll

",.,.

m:I' :d.f)
:hU
g).,1
,.,.,.
1>1.17
m:l ,.'0.14
~::u ~&:u
CA:n

"1'"

1

--l--·lL ~~. ~'m~~i~~~i~~~~~-~~~· ,n_ '-1
-- .. - CBL129

'.

-~-

CP2

RooH~SYSEPROH

ROOH·SYSEPROH

--

J5B
<

l=n~iIIEfO>

.

..

(21) SYSEPR_WR_ _ _._. ____.I.~_ _.-+--

2

·--.____ .....ir
7 ('

C8 ,,,1 .. 60

..

---...YIJLSl-IJ.T.C1L.-------.e-J.L.

PWO All.)
AI'"

vpp

0.1 .. 0

Ah\5

AIo"

~J:n

Cl:U

AI.U

Dl."
1>0.)5

1.0.,.

0>

<

OIlD~~~;~~;1 ~~~~)~L_'_I

CBL130

2

,.

mm

ROOH.SYSyg~

EB D 7

AU'I "1"1 ChI:
~1):1 ~t:l, ,,1:1)
A •• '
A"10
Dton

m:, m:u

08 'A20."
8( WE

~:T-

FLASH EPROM WRITE PROTECTION:
ON=WRITE ENABLE
OFF-WRITE PROTECTION

TSOP

1\ cU .. O.

WR _______
-~-.--.
--_Ii

-

'--FEPROM8XM1'~

·".I.Al0,11C

>

CPl

ROOHsSYSBPROH

3K31.~-----.t1!}.Rm'lf!..B....I2.Qmll-·--·-I----t-----1
ROOH-SYSBPROH

SW6

I--

. . . LUJ..syS

c8TI.GB----5~

l

VALUE=lBH7
\D

1'1. ROOH.SYSBPROH

ROOH-SYSBPROH

G

~

3

_.. _____ ruLWR
__.

~NC

&!

M

,Itt

~ .. ~

M

._____

c»DD8~I<:?8~

r=
g

3

- - - - - - -.- - -

CS- SYSEPR<
• 00>
~
EB_A19 0RIG'::'
EB A<2
~----+-----------

~

...
EDED>.r------t----------------------------------------1-----~---------------------------------------______~__~

_

ADAPT-~~rus
EB_WR

_ LOC

~_g~

_ __

G~~NRB~'

cTJ.:~llf~~:

vPP-~~:ft~~ ~.---.----------------------.- ..--.....

4

-- ....... ___ .... _ .. _ _ _ _ 1

4

_LOC_BUS ..
LOC BUS\I

I

DESIGNER:
Hon Apr

FLI\T_DRAWltIOI IlYSBPROH_UmT_21. LOGIC .1.1
lNSTIINTIATIOIII

(CPU5V SYSEPROH_UNIT51PI

.... --·-··--------A----·-..----·r---·-·----·----B . -·-----------r-------·-c

SK

3 08:55134 1995

f~)~[rE
COMPUTERS

_PMWJ.M.G.

ABBREV=SYSEPROM UNIT

APR/25/95 Manual

SYSEPROM UNIT

SHEET
22
OF
94

REV.
0.2

1-

A

--

--_._----------

RS232

---

--.----CONNECTOR

SCC

SCC

PIN It

11

¥~~A

RTXCA
DSRA

TXD
RXD
RTS
CTS
DTR

TXDA
RTSA,
TRXC
CTSA,
RTXC
RXDA

2J

¥~g/RXC
RTXC
DSR

.. -

CONNECTOR

-------~-.

-------~--.

TXDA
RXDA
RTSA
CTSA
DTRA

RS422
-------~--

6

---------

~~------

PIN

It

----~---

TXDt
TXDRTS+/TRXC+
RTS-/TRXCCTS+/RTXC+
CTS-/RTXCRXDt
RXD-

24

S

i

.___ ~ .. _ .. ,J ________ ~ _____.___._.

B

PORT A:

.

~- ~-- CONNECTOR
~~4 B5~r~--SCC
PIN It

---

TXDA/
RXDA
REN=DTRA
TEN.,RTSA

D

PORT B:

-~ --~-----

--

SCC

---

RXTXt
RXTX-

RS422

RS232

7
20

CONNECTOR

TXDB
RXDB
RTSB
CTSB
DTRB
DCDB
TRXCB
RTXCB
DSRB

20
7

TXD
RXD
RTS
CTS
DTR
DCD
TXC/RXC
RTXC
DSR

--_.
PIN "

--- ------- - .

--.-,~~--

SCC

CONNECTOR

TXDB
RTSB,
TRXC
CTSB,
RTXC
RXDB

TXDt
TXDRTS+/TRXC+
RTS-/TRXCCTS+/RTXC+
CTS-/RTXCRXD+
RXD-

PIN It

- ' - ------

2J
2~

H

11

h

sec

CONNECTOR
..RXTX+
RXTX-

.---------.- -..

TXDB/
RXDB
REN=DTRB
TEN=RTSB

RS485
~--------

_--_

...

It
__PIN
.. - ....

H
11

23

27K

mIml4 -. -. -(i~I.4Jr--

ADAPT
!:SERIAL
SER TXD

ADAPT
"SERIAL

!

i

r-

SER-RXD .. -

~~~:~~~ ~==

2

S. E. R:DTR
SER
DCD f_ - ·
SER
TRXC L
r--·-·
SER-RTKC
-.
SElt DSR f
_SER BUSI
, .

- _CONN
t- X r ... - - -.. _. ___________~ __._.. _ _ _ _ _ _ _ _ _ ... __ .. ___ ._ _ .__.lL.
tI-' - - - - - - - - - - .

TXD IN
RXD-OU'r

t-

;
OUT
.•.
lL.·---DCD_OUT '.. TXD
CTS",IN
. -3--'
-•. S
A
~
DSR_OUT
·-J S ·---·-~e
-l
IN
J59. DTR_vUT
OUT
:-c
.
_
.
GND_OUT
.----~.-S
.-c.J
--.-...
C
i

'

I-' ...... -

-~--.--.--.-----

A
A
-A.

I

_.-

.• -

-.~~

-I

.-------.

,--f

TRXc.JL~_-'-~.~

SEa

-

J63

.,

Y. IT~

SW4

DCD IN •
DSR-IN

~U:6UT
DTR:IN

R~~~03¥j-------sle~§I.
-·1
-12---

-- FliP 0 ~.-.

I r-- - ---. i SERC~CCONN'

SONDER_A=SOCKET

I

SER
~J~5t

..,

~~CT1WO
..................

10K I

.~-----

VALUE=lBH7

BUS\I

I

J63

-

..-.---.:.-~ J64
__
11
J65
•.

10K 14CJrn--- :1---.-

SW

~ -~)

U-~~!l-'( ).ll..-~~~~_
_ '.

.

1

3

2

~

i~~-·-·ER R~ !.Li~~
-

3-Erl

CONN

_BUS

~~j.L __

2

TBZ~'l:0

SR4

--.. .

SERC:TXD
SERC_CTS
SERC
DTR
SERC-TXC
SERC:GND
SERC_RTXC

__ S k
.. -~--

SmU~T..X..c-.~_ 8

. _- --. ---

d21.
s

CTS A __ 8

__

3

8TU5

.

J65

~

. J64

'1R~~-.

8 1~ -_.

_

0

~~CT1::'~
~J63
~~-rrIT""JOH}2=ts
~..T)(.L1L.JL~25
__ _
.~K I.~-J?~

_ _ _ ... _ .• __8.

ii~ _to
J 61

./

. ----<6189

'~Hlli-c.~_J

-.1

--

9

I

------

VALUE .. 1BH7

_______._

~l!:B-'rRKC-A-------{]ffir

J61

/~. ..1....____ _
-:"'-<'1.~189.

m-

1

, ' .. s

r"

/) cJUJllClL--<:I

4

DESIGNER:
Hon Apr

f~Jf~[[E

PLIIT_ORIIWINO. SBRIAL_21. LOGIC .1.1
IIISTANTIATION.

(CPU5V SERIAL4SPJ

---......-.. --------x-----..------.-.-.-r----.._-- -.--.-8·--·-·---------

SK

3 08:55:23 1995

--···--·-·l-·--·------·-C~-

COMPUTERS

4
.

PMW:UH~.

ABBREV=SERIAL

APR/25/95 Manual

SERIAL

SHEET

23
OF
94

REV.
0.2

__L

A

--._.==-__=_==-._I.. __-_. __.__

B

RS232
-----

------

----- --- ---------_.

11

--

TXOA
RXOA
RTSA
CTSA
DTRA
DCDA
TRXCA
RTXCA
DSRA

!

I:SERIAL

2

SER ~D
~~~:RT~
SEJCCTS
I
SER_DTR
.
SER DCD
I
SER TRXC
I
SER-RTXC
SEIt-DSR
SER BUg-·

~XSERS>

f::_
!

TKOA

TKO
RXO
RTS
CTS
DTR
DCD
TXC/RXC
RTXC
DSR

ADAPT

SCC

PIN It

CONNECTOR

SCC

L__.___.__ . . __ . . _._._ ..... _._.Q. ......____ ..______ ..

c

-

PORT B:

PORT A:

RTSA,
TRXC
CTSA
RTXCA
RXDA

wit

6

'I

RS422
----- ...
.----------------._.

__

RS485

0---_·--

~-

CONNECTOR

PIN It

.

TKO+
TXDRTS+/TRXC+
RTS-/TRXCCTS+/RTXC+
CTS-/RTXCRXD+
RXD-

'0·

SCC

--_.-

24

S

~

___ . _ . _ _ • _ _ _ _

CONNECTOR
___

TKOA/
RXDA
REN=DTRA
TEN=RTSA

._~.

-

.0- _____ .

._---

_ _-

SCC
.--.. TXOB
RXOB
RTSB
CTSB
DTRB
De DB
TRXCB
RTXCB
DSRB

PIN It

_ _ 0'0

..

RXTX+
RXTX-

7

20

20
7

RS232
-...

RS422

~-

CONNECTOR

-----TKO
RXD
RTS
CTS
DTR
DeD
TXC/RXC
RTXC
DSR

-~--

PIN It

SCC

--_ ..

.. ---- .---

TKOB
RTSB/
TRXCB
CTSBI
RTXCB
RXDB

JI

.. - ....... ----CONNECTOR

21

,._.

.-~-

TXO+
TXDRTS+/TRXC+
RTS-/TRXCCTS+/RTXC+
CTS-/RTXCRXD+
RXD-

0·0',,_,_,-,

see

PIN II

RS485
.---- .. ---._.-

TXOB/
RXDB
REN=DTRB
TEN=RTSB

H

II

"'--'.'-

RXTX+
RXTX-

H
11

23

27K

ADAPT'

!

I

~~=-.

PIN It

CONNECTOR

- _._---------

x

r--

B

-- -----------.

._~

f ~
c-.

-I
I

BUS\1

.-

I

t

------~-- -- . - - - - - - - - -

<

~.LtW'=~I;L-L·-=t-.

'-

~

~.~

sws

10K '4Ciilll
VALUE-1BH7

"'ER

2

DTS
>i!_n-L'

S __ .

~

~-1o"rnLJ~I-~--_•... -------t _ _ !OK

L-\ _____ \ __ 10K

'4 CJiijJ---LJ

'4t=il11

FACTi

13

SW5

•• 0 _ _ _ _

~___ 10K '4

0

. '-_ E"-- -.
_ ____
-H.-=~~=s

0

.J SERC_CTS
SERC_DTR
.: SERC
TXC
-~

~ ~~~g:R~~c

..

,---- -.-

---i

,

1
I

SERCS'B~cCONN:
BOS<,"Eac>

2

SEa CONN - BUS \'

--

.

.,

J62

TRXC B _--..-L I~T12. _3_ _ _ _

~6

2.

__ ._

PACT1~8_ _ _-~

~

~~:2

S _ CTS B_-l!~"~r-II

-

...Lfr'OTI:J.(~l-·U'-1- ;c;,...... -.
(\

_

___

._ _

'

.

~
.-.-.---~.

-S~~5~:

'--'l'-.'
ml"~~ SERC_RXD
~~Rg:~R
~~~g:~I~

'~t==:

SONDER A=SOCKET
-

]

_________.__r!l J52
~~TILQ _ _ I~T12 ~
~
io
J27
10...-(')
9

1

BTH

-L

6__

I.

~.

< L.

FHO 02

__

J52

DCD_IN
R~~-IU
RTS_UUT
TXO OUT
CTS7t IN
DTR-uUT
OUT
GNO_OUT

"1f'0 (\

B

J27

10

--s---

62
J

TXD_1U
R~g:¥NT
CTS_OUT
DTR_IN
OCD_OUT /.
DSILOUT '
IN
J60

B__~J~~_~

__ _ _S_EILTIU\I

BUI
~

81"

--=-___- ' ____ . _______.____ ._ . _ . ___.P__ .. _.__.____ ._.

1

.$.tl.I_ELP __

P9

FSER'

S~~~~R~g

'_SER_CONn
I..,..llu13

.__

-!-r.j> G_~ .....H .. _________ .. __ ._$f:.B_~lHUL~9~ ______ ....... -. ----.-. '-'-'"
G-.!!. 15 1I\II-l.ltI!·:~~ _ _ ... _.~~y._~.C"JL~'Otm_ ..

NC ___L
!

......sf:.R..-T1H>

A CO~_ _ _ _ _ _2_ ~

_ . .9~R Rx~_lfl~~WllmhIO

l..-lfSEB

RT'

~

1

A"l:I1!!k......:~-' ... ' [)

~ CTs_~~~l1lfu~'_10_ _ _ 5
.......smLDJ!.lLlf ' Cb'1fuH' 1>111'10
6

SEILGL~lMh'O
SER nPD '" CONN

7

'-- ~~"'L"_.'~~ ~

2

.

0- 11

...!..tJ

G.-!..!

7

18 HItI-I.III!~~~ ___ .. ......s~.ILI:!XC_!LC.O.NR_ ....__...

~~\II!·"~ _____~ErLB1,!L!LGQmL •..... __ .. _.~ .• ____ .....
ll~~~~ _____...Sl!;JLQT.IL~LCQ.tm. ...... _. __ "_'
U . " HItI_l.ltIE~IIII>11I'IO
SER DSD B CONN

G-~

•

.~ ~-:: -:: ::~~::;;~;;:: __.:-:~~~~~~Otm

~. '=IIF~=".

2

G....!· ..1.L__________S.~IL1_KCJLCQJm._ _ _ _ _
~ n~~~____S~_RJK..C-.JLC=O~NN,,-,--_ _

~Jn'.R_Jt£mm

r-+-_=S=E~~~~

SER..CTS B'I 'Clmk"11>111. 10
II I".I.INI.III 1>111. 10

G'..'! Jl.~""L'~._... _ _ $.J,':.R_~1~C_A_<;:~NN __ . -. -

EI

5

L - - ...

... __~ER_B~D-!LC;:.Otm

G.....!! _16 1I1II.I.III!.IIII>11I'IO

13

U

Gu~ ....1..LH1 r.rt!"I.WII>11I.IO

HALFP26
.,£9~;t

VALUE=THRW

SONDER-A=2UNC56X3Z16
SONDER_B=2UNC56X3Z16

-r------.--.- ...--.----..
----···-1+------·--·------

L........-.....--t-.--I.-----.-.-.

3

"---'-- -------..--.---.--.-..-.----.. --------------.----.---.-.-..-....

------.---------.--.... ---..... - .. -- .. --"---'-

3

AbApT

=~~MAL
SERC

B§D

~.

__

~

__. ____

-----1

J~~=- =~~- . ::~ =-.---.-----~--~~:~~~
SERe RXC

SER B CONN BUS \ I

i

!

_SER_coNN

_BUS

~-

.• - - -

j
!

4

4
DESIGNER:
Non Apr

1[' If~
.~. _=:1

~t]-tjf:C;;'

FLIIT_DRAWIIIOI SERIIIL_2_coml_24. LOGIC .1.1
INSTANTIATION 1 !CPU5V SERIAL_2_cotmUPI

··--··A ·-----·--····-·r

. .P..MWJPG.

SK

:) 09:5412. 1995

B

l--· . . ·--·------c-·I

II '.~':::._._. ~'

ABBREV~SERIAL_2_CONN

APR/25/95 Manual

_.::J

COMPUTERS

SERIAL_2_CONN

SHEET
25

OF
94

REV.
0.2

I _

A

_______ J__________

B

- -- c

___ ==-=-==-~[

______________________

._P___________________ _

RooH=KBDHSE

RBD MSE BUS\I

J65

__ ..Ktl'p..Jl.J_tLJ(~c:;aJ L...l~ftQ.!N ----&~r---J.~---

·<;1

1

RooM-KBOMSE

I _KBD
I

MSE

'----ll

K~~,£Dg¥~ 1----MSE DOUT

J65

I



---

-

-

_

I

33R

T~'--'

-1C

,.".

I

1411>ll

~

1

~

_____!!!!!.!1!!!-J!IW.!!L ________ KBD_DIN

ADAPT

~~DOt1'!'~tW____ - - - - - =!------~l:r~l~~~-------- ---.-. ~~~-8~Hr
~__

______

lOOP

KBD MSE CONN BUS\

~l'iJ.~ ~::~ :gg~:~:g~~~

ROOM=KBOMSE

KBD.-POUT_}~~~L-~l.KB.Jl...Q~IDr___~

i - RBD
__ MSE_BUS
_P_ OWElt_OFF It-

~

---------___ .-KllP'.IlU...QNN

lOOP
..£. ---

RooM·KBOMSE

! _ADAPT KBD DIN L. __________ 1

I

RooM=KBOMse

r-----r==------===_-=:=iijij~I!,.E~~~!ii::_:::::_~_=.._.::-:

RooM-KBDMSB

----- ~ MSE:DOUT

_______"J!!-.~!!I.E~!!>nI.!1L -----------

_KBD
CM~ :

KBDK~ftRMSE
-

gONN L-....
_BUS!

~

RooM-KBDMSE
RooH-KBDMSE

2

LHsLDJ1LJ.

J65
~I_lMS~_~
125)
33R
ACT14
_ _ _ _ _ -.l1~ltLc..O.1m.........

=r

"

2

lOOP

C

RooM.KBDMSE

J27

.1ffi.E..J!9Jtr..Ll~

RooM-KBOHSE

RooM-KBOMSE

~

!--.illJMru!~_ _
~~Q.tITS_Qmt

-r

lOOP

C

RooM.KBOMSE

~

3

L

3

NN

PG

__

RooM-KBOMSE

_

----' W ,

m'-'

_ ___________

r-:.l±'CElS
-nt,
lOON_20T_1206 _[_ _ _
J --- -T-

RBJL~__

_ ___ _

A 16V_TA

RooM=KROHSE

•

RooM:KBDMSB

4

4
DESIGNER:
Hon Apr

r~i~'l[rE

FUoT_OAAWIIlG, KBO_HSE_25. LOGIC .1.1
ItISTIltITIATIOIl:

ICPUSV KBD_HSE31PI

-~---:-A

SK

1 08: 54: 21 1995

------·-,--·------B----·

-- --- ---·------l-------

'-=---

c

COMPUTERS

_PMWING_
ABBREV=KBD_MSE

SHEET
26
OF

APR/25/95 Manual

KBD_MSE

94

REV.
0.2

B

A

___ . _________

~.

___ ._ _ _ _ _ _ _ ~_ _ ~-::.. _ _ _ _ _ _ _ _ _ _ _ _ _ _ . ____ L _ _ _ . ___ • ____ . __ . _

D _._. _______ .______ _

1

1

PiO
_____ .JU1V.1lIUlJ1l'TU .....:.o.._ _ _ _ .

2

KBD HSE CONN BUS\I

I~...

.

.-

-

...

-_. __ ._._.

-----.
.
.
1
--SH:rnYL---.-.l.-~;;~:~,~~. .
!,t-;-},~.~ .-.
--.-.-.--

J

....S

P!. .

9

.....
.-.-..

-

I ADAPT KBD DIN L _
I =KBD K=B!Dg¥~
I_MSE HSE_DOUT L
I _CONN KBD PWR I
KBD. nn "'~tn..
"I
1-~8~<~~~n8~NN I

t--

-----_._. __

-----

---

____5_

'1- ----

L~
I~'
\ ;! .

__

0 ±

0-J.1

I
rc~~~~~~

--

\

...

,.,

2

___
1

J

- - - -.._----_ ... _-------

___._ _ _ _ _ JIlJ.IJ.IU.P...1M'HalCL.

3

3
. - - - - - . - - - - _ ---.... - ______ . ________ . __ . ___ I

_ _ _ _ _ _ _ _ _...JIUl,.Llm...IIlIXIHolO

4

4
DESIGNER:
Hon Apr

.P_~WJNG_

SK

ABBREV=KBD_MSE_CONN

1 09:56:29 1995

n~r]~T~~) ,T-· I~::"~
l

FI.AT_DRAWJNO: KBD.HSE_COml_26. LOGIC .1. 1

I NSTAtITIATION,

U

ICPUSV KBD_HSE_COIm41PI

--·---· ..-··---·---13··--···----··---------·---··-1---··-·--·--·---c----·I

,..~... .

.._

.:.~::,

COMPUTERS

t. :)

APR/25/95 Manual

KBD_MSE_CONN

SHEET
27
OF
94

REV.
0.2

___~_____ A_________
r-

___L

.= r - B - - - - -

c

__________ . ______D~ ____________ _

1

1
J51

'.H-~~--------~-2~
~1~

:N~l!: - - - - - - - - - - 2 r

f- ::

~~t;_--=----====---=--_----2
-----J
J.i_JH$----·-------=___
,~A<1>

_
II Ad.___
'-'f---.. !!h!~'
'-..!l ___ .~_

.... A

••••

__

or----;

III Ad-

I

..

a,.}.~._ _ _ _ _._.=l.

EB RD

--1-·
t~I 0 D::
BI :: -if-"-::
~~ .~--~=~==::---= .-~. r
-n:____. !BD<2>-====~:::===_~l:
AD..
_.1...
A-l2--D'f~; ~l----.!~~1?-------. ------.

D6 .. -I7--~H~~---·---·--·-·~---5···

A 1

A
A

~
A

AO
G

....!!IOt
I. CS - SYSEPR<
•• > '-EB A19 ORIO

:i
I

E~D~D~~::8~~
r.B_ADDRL

:

,

L..

_

.--------.----

~_g~

3

GEN-CS'
Y

rret.'W

!

i!

e~~?:Oe>

_ADAPT ~G:lm~~--

'. _LOC

3

II

CTRL 'IlPPINt1.=
VPP:SWITCH L

~

SB_RSTO
_LOC_BUS !

LOC BUS ,'1··

..

--'CBIDroR-

U'-- CI-->l;r

I . ..

D3 NA

~N:LINE_WIDTH=25
E STIm.'l__

2

(){

D4

NA

~BL 33

-----~~~·TOETR·-ENFOTRION
3K3

DATA R

~

4

4
DESIGNER:
Hon Apr

ftl~):[[E

FLJ\T_DAAWltIO. tMWUIlIIT_21. LOGIC .1.1
INSTANTIATION,

(CPUSV NVRMCUNITSOPI

A

SI(

3 08:55.20 1995

-----S·--

'--'-I---"---'--~-c----'

COMPUTERS

_PMWJN~..

ABBREV=NVRAM_UNIT

APR/25/95 Manual

NVRAM UNIT

SHEET
28
OF
94

REV.
0.2

A
------------------

__ ~ _ _ _ _ _

_.1

~._ _ _ __

. _ . ___ ._ _

~_

•.••• __

~

_ _ .•

. _ - - -_ _ . _ _ .1

2 RESERVED READABLE BITS:
(·.J:2.4'1

l~KM'~~~

1

- - - - ----_._- --.. _-_.---D.. --- -------------_.- .----

J55

__________ ~___ .______._. . ______J1Q.lAL_ll...~~t>__1__---.--~JLlt<.7.:>-. _____ ..

1

1~6

l~KA~tle--.---. . -------.---

~

J55

2 DRAM SPEED SELECT BITS FOR LOCAL DRAM CHIPS:
1 OK',4·CBIDr---t

NJ\X-~-------'

J55

13~tEIffi=l-------------------------- DRML.C;;Q!)!Lt&~.?'_ _ _
2 1~!.L---.-~·P-Q-..,.4.~-.- ---.------- . 10K '4Cirn

DRAM...-CQl21LP.~t>

1

2

2
10K

. . . . . --=~-,-,,=,

.~_5

C_Q.P..f!.J._~>._·-~--~50'~
~

10K '.0illl~6---=..."...."-"=

~u
~.,.,_--ul:ltIl

:_LA<" .~--1lGlI 88Crnr=,~:::
CgMP,~_".'_'O"'.
:::::~:!: t ---DllmFgmHU!!h,-----

_ _ ___ _ _ __ _

DRAM CODE BUS \ 1

•...,
......
•••
Ii__DRAM_CODE_BUS
tooy.'UII
....\tt.Uu
_AoAPT_DRAM_COOE'

l_•... 0

I

L_
<-

I

3

, ....

"RAIl

10K

14CJill'

DRAM

rl

.-

__

CODE 8<1>

EB D

..-

'
4 ABT
J55 __.- __ ...IDLQ5Q?:.
4 >-J!..........
rl

_OC---

=~l

~~-ll ~II----------:::::::----D~
.------L-:-::-':---

---=-----------:::::-:
~~~-:-.-:
~~~.:..=--~.---~...
-----,

-

3

..

t~v_t'itl·'t.\'H.W1

I.

RD DRAM CODE
CS BOOT
CS_SYSEPR< .. 0>

I§ RD DRAM CODE

~G-~~h~~~~ ::

EBEg~loDRt:L~E~B~D~<7~~Q">~------------------------------------------------________J

B

ADAPT EB_RD
-L
~_WRI
- OC EPROM-g~ H

8
c~~~=~rf~L
SB_RST (',
GENiES
Tr:NCLKY~

4

4

_LOC_BUS LOC Bus\I"

I

DESIGNER:
Hon Apr

9~~::'
II
. ~ij/J ., [C
___ If~

FLAT_DRAWINO: DRAM_CODE_UNIT_28. LOGIC .1.1
INSTANTIATION.

I

(CPU5V DRAH_CODE_UNIT73PI

A

.J}M,W1NG_

SK

1 08 I 54 I 11 1995

- - . - - - - -·---B----·-·-------·--

-------··--c- 1

COMPUTERS

ABBREV=DRAM_CODE_UNIT

APR/25/95 Manual

_-:-1

DRAM_CODE_UNIT

SHEET
29
OF
94

REV.
0.2

A:______________~

00------

CI

_____2_

12.2.1l!7SEGJ1~--rnlnr470---------- __ .L

_lA2lJ,.7SI;:~1'I~~1"_____ (~,~--------4---, ,.70R

11

G

~

A

c:::::::;)

C

h m~ f1\J
P

E

1

j~lL1S]:9M~J.~----{]:g!J470R ---- - - - - - -~-

D

~

-lO----------m1'1'4'rO---..l29lylS~Gtt"5~

-,-----------

C

~~

RooH=DJAO_PWSBNSB

RE~-ID',:~ ~emt---j-----{]ll_'r---J........J29IPW sgNSE
RooH.DIAO_PWSBNSE

l

,OR

RooHaDIAO 7SEO

7 _SEG_LED

J31

&!

RooH.DIAO::7SEO t.:

:gg~:g~!~3~~~

RooH-DIAO

M

~

U!LQXSF.Al.I.Wi.F;pgL

I~J

RooH-OIAO_PWSBNSF.

RESET IN
SENSEI'.
CAP_DEL-'

-;l:)5

RESET
RESET:P
VREF

&!

RooM-OUO

11

1- .. - ._B.ILSYSJ:AJ.L_LED
__ ..1~9).1tJ-t~~P_R

.Kl. ...

\.~l''''''''_''''

RUN / HALT_LED

USER_LED<3>
USER LED
---~~-

CJ

___

RooH.DIAO

USER_LED-u~1")'

.--{!~8rR---_..._.1_L
.1;;>.~:~:-;~~:
~~-t~~~:~j:2. -----~:~~-~!~:~:-.-m.________ .- ·C+· . _L ._____

. -..

~B_ ... -.---- _____ --.

(.B.illI------

RooH-OUO

YOON_20T

1100N_20T

RooH,OUO_PWSBNSE

&!

RooH-OIAO

D1

RES PWUP-'

RooH.OIAO

RooH-OJAO_PWSBNSB

&!

1,
.L~9 )J~J-tl!ED_ij_< >_. __ .M. ~ii~

~.!t~~
__ ~P

c_~

RooH-OIAO_PWSElISE

BM LED

I",gl

L\

SVSTL7705A

Ii

SW8
VALUE=1BH7

~w~~::~:;;j~ - ~I~- - -- ------ - ~
j 1 1"1" 1
l~l~J~.--1;uu.(3!:J..=;YSF'hJ-~ B~ ·-·l\~-f I~~I·I!~

_ _ _ _ _ _ _ _ _ __

(29)CAP DEL 3

LF;;~~~I

L~_' ..

GHOO

HIII_LlIII_NIDt1hl

680R

-rnIiiIlJ470-l~~J 41SJ';G~~_>

-Jt

~

RooH-DJAG_'SEO

_____________ I~llLJ!~kT_~ED~O~ __

§ _ _ _ _ _ _ _ _ _ _ _ _ _ _ rli;;.~-(~1S.E.9M~7>

D

J9 DIS7SEG
SONDER_A=SOCKET

RooH-DIM_7SBO

:gg~:g:~g:~:~g

_________ J ____.. _ _ _ ._ _ _ _._. ___._-=-.. __________ .____.

C

;---,~ ;-; -~. _L---------------------{ID_!r47~: (~jJ...1~~GHc:J2

Roo~.~JAO-7SI!1

illll-!?A.I;:m1_9~ ---m!~-)rft~--

_._ __________

B

33 OR

'__-w'LI-;11.'I ... tm.":tI

----------------------------~R-oo--H--O-I-A~O_PWSMSE

USER_LED_B

RooM.DJAO

v.-o'l_t"i'U·H.IJH.IUn

r
Ot

2

ROOM. DI AO

t

RooH-DIAO
RooM-DIAO

ROTARY_SWITCH

CS_SYSEPR1)

-_H~~~::E~O:EYSW7BNA8L'~j 11l1IBt: 18~
_____ 1. ErnLJ 0+
RELI(&'i

~G-~~h~~3~
Elt D<7 •• 0> ~
; _ _ _ _ _......,
...

i

E

ADAPT-ti~ru>
(;,
0
EB_WR( I

RooH-OIAO

8

VALUE=lBH7

_1.2~u\!llI~ELOJlI.0

~---

i

_ __

1_

!_L C ~-g~o

- __ .F.1!~JITH.

-- -

SW3

RooH-DIAG
RooH·OIAO
RooH'OIf,O
ROOH·OIAO

RooHcDIAO

[Olma

S.l:I.I]:.-HP_

2

c~Dlt8M~h-:~D8~ ;::

1

rll __ML RESET KEY
~f2-1rr <; II SWITCH -

BEL

GEN-CS ,~'

,

GEN RD'i:~

,

CTJ.I~~~=

VPP-SWITCH '--SB_RSTr"}LOC BUS,LOC 8US ABORT KEV ENAnLE
.
I
K

t~r:;.~tJ__=~:B~
SW7
----.

ROOM.OIAO_7SEO

RooM-DIAO

JO

RooH-OIAO

f

_2

_l1UMIQB1]Y_ORI~

41

. . ___ =
1-

-·--··---~t._

SHIELD

BEP2_
..

r~

AB RTP

_ADAPT

ABORT KEY
SWITell

-

f I

--1'"

:-~ED
_w- ----=--=
RUN_HAL~r;~E~~~l:-~~~
USER...L~R<
sJ~:.,---IUmJ
Bgd'm!~~~~
Jllll!l:m~::l:
-~
~ .------~-::-=_J~SOPgl :.._=AI'tl§~91H2>
:::1;:0.-;--"-

.,

.

.-'-

','-

;; Ql

~~~n

"r

9

." ..,,,;

h?l._!!gq!l<&>

- ---

A8BREV=DIAG_UNIT
APR/2S/95 Manual

DIAG_UNIT

1L.7!l..f.GM_\I

I

.. 1. .

_TRA_VME


SD<31.
800-274
804-269
808 .. 264
8012 .. 259
S016-253
8020=248
S024-241
8028-235

_ADAPT
_TRA_X
&ODY_TVPE.PLUHBlua

1

R-:---..Jrn~SI-­

VBERRIVSI

~M~~gU X---~-.--~-L

_TRA_VME"


,.

8B_D<31. .0>:
SB_PA<27 •• 0> I

i

P

SB- SIZ<2 •. 0>

I

8

~
i

2

811

1

I

Ii
B

SLOT DR

m·

-----

ShgT;~~ ~---:-------- -!l!';r;:;
ow.

Sle~I~~l: :8~ ~

SD_'NT<7 •• 1> 0

,-

SBUS

T
l~

5JHL.J!.lML-----....
re:ilB O
:______ .__ .. __________ --.----....-.;-1
-----.. -------.- ....

Sll-£l.~

u

SCLK

(,

I~ ~III
6

:; :~'"

~ .~.l.'f!:~l.· ;f,i;,.", ".".",

8;;~~:~.

:: : : : : ;

:~~;:~~~

::5-223
8SELO.U S8EL1an SSEL2-39
8SBL3-38 8SBU-35 S8BLS.J4

. .I. ~B~S\I

VDTACKDIR
08 V "CIUlIR __ . ______ ._
VDTACKDIR
VDTACKROE ')
_.'lIm!;!.~.IL. ________ .. _..... __ .____________ .. __________ ( j VDTACKROE
VDTACK W-...Y.rn''J~ElUtIVSI·- ---'- ---.-- . -.-... -_.- -.. ----.. - - --- ----- (~l VDTACK
n'

m--

~H~1m5

VRETRYI

~

'''oi.tr,toni,IH"f,h

ADAPT .JTI\O_THS-------,-JTAG
~~~~:~~~:===--===-=-=JTAG_TOO '_.______ ._ _+-___

...u._".. !~i=t- >THS
TCK
~~

.-

TDI
TOO

JTAO_RST i)

~~:n1IlJc::~-I--==·t--==---niiI'{AE~1L1~J
---u-Al
N U. :m.1Lr=- '1"1-- _. ___l1lilvSI TES_TIl.~_2r

1

33d'-rnR=U
N -RU-33 . 'R2S -- -- -

TEST

_ _ _ _ • _ _ _ .... _ _ _ u

~l ~H~1m5

VIROle'

It

~::~~:~g9 VIRt6vl~og~R1~:y> ~

yJRoo.?

I>

0

VIACKIN
VIACKOUT

.-------.

.-----------------8" VIACKIN
- - - - . ____ ._ VIACKOUT
j

---- - - -

---H ~~~~~SRESETO

3

J------- --------- -tl;-1 6~~S~Ws~Tr

VSISYSRESETI

.

VSYSRESETI

-------~-lVS~I~~I~r~

VCC-40,65,82,100,IU,179,nS,219,Z34,246,258,266
SVCC.9,21,13,49,61,7J,95,91,109,12S,ll1,149,
161.t173,185,201,213,225,237.249,261,277,289,301
GNu:

~~~:l:9~;O:?2~~:n2?h:~2~~~2~~~2~~~2~~~2~;l,

SGNO.3,15,27,43,55,67,79,91,101,119,130,143,
155,161,201,231,243,255,211,283,295
.-.----------

70

V8ISYSIUlSBTI___ _ _ _ _

~:~URlr::=.~==-~_--=_:_=_==-_-----:--=--::.-=..-~--~--- ----~ ~:l ~1~~~¥f¥TO

_1t6
VSYSFAILI
6~YSl l i l VSYSFAILo:>il
_"'"

VSCON

68

VSYS'''ILO

--- -------_.-------

-------- ---------- ----

.BI_._________
---- ---

-~

- --

._-------

<) VVASCyFSAFAIL10LI
---- i)
. - - - ' I VSYSFAILO
-

- ---

--

:: ~~X~a~~o>
--,

VGAP

------- ---- ---. -- - - - - ,-, VSCON

_TRA_VME

IRA

-------.~-

-

j-- ----- - ---

VSCON

y-----------.

~~~:t:~~mc _______V
__

----.-----.-.-~~-------.-~----~--.-.

~G~5~1· :8~
~Gg5HT~j :~~>

-=~~===-=~==~::~~==__=__:- <. ~GG~M
--.---------- -

VCC-VP5
-

VIROI<7 •• 1>

J VIROO<7 •• 1>

VIROZ-160 VIROl-tn VIR04 .. 163
VIROS.16S VIR06.166 VIROh168

-

2

_ •.. --.:

(1 VRETRYO

~~:g::~ VIRll~~ro~~14;1: ~

VBCLR

+Sv:

___ •

v~J!:IDJQY13r_:_~~=__=

~BG~~~

ABORT KEY L_____ .._ . ___ ._ __
__.. "BORTP __
ABKEY
-NHI 0--------__!!!!L_I
INT
PL"
RES PWUP O----------------------~~-n'7
PWRRES
lIHII 10 SB RsT REOb----------.. ----.--------.---.~~51(
LOCRES
SBUS
'VSI ~LIVr--------.
VBI eLK
• - >VCLK
-  VSYSCLK{ _ _ _'{SY~~ __ _

_____ n

!.L......Y.l!Ir.BYL ----.---.------.-.-------------. -- ------d VRETRYI

~:=~g:~~ ~:=M:~~ ~=M:~~ ~:M:~: ~n5~1: :8~
v~mg:~~~ v~~~~~:g~ v~~g~~~:ln ~~g~~~:g~ vX~g3~~~:: 8~

_ADAPT
_SBUS_200

JTAO_INDI!X~JTAO_INDI!X

4

PQFP
$LOCATION=J5

SBR
SBG
SRST

_SBUS

3

_TRA

SB_DP f-

SLOT CLJX·L--SB_CLK<7-:-.0><>-

~::.

L

..

Y

I

P>

s::<::::>
sa AC;';;>

. I:Q SB.-ACK<2 .• 0> ~
I t I l ; -

1
~~ l

PAd?

Y

803=270
807=265
8011 .. 260
8015-254
8019-249
8023=242
8021-236
S0l1=230

ADIR IJil·!LWHlL-------. - - :::.::J~~~n 1>
VA<3 •• 1>
YAdl 1>
___ .__________ . _____ .,) VLWORD
VA1=131 VA2"U2 Vv~~~rR .:}§l _Y1!iQ.IID______ ._
8PA2-14
SPA].l3
SPAG-10
8PA7.8
VU-1l4 VAS-US VU-136
8PA10 .. 5
8PAll-4
VA1·U8 VA8-139 VA9.UO
_ADAPT
8PA14 .. l04 8PA15 .. 303
VAI0 .. 1U VAU-142 VA12-U4
SPA18 .. 299 SPAU-298
VAll-US VAH-U6 VA1S-1n
VAI6-149 VAll-150 VA18 .. l51
I :&~~~:~:~ :&~n:~:~ :~~n:~:~ :~~~t~::
VAl9-U2 VA20=U3 VAU-154
8ODY_TYPE-PLtlMltlflO
VA22.156 VA230151 VA24,,78 VA25-80
VA26-81 VA21-81 VA29-Q4
SSIZ<2
••
0>
VA29a86 VA30=81 VA31=88 VMADIRI~lL.YI:!~!lli! ____ . _____ . ___ ._. _____ . ___ .. _
. . VMADIR
snO-Z80 8IZl-219 S1Z2-278
1) SACK<2 •• 0>
VOSO=l94 V08bl96 VDS~Ri~~
~IfE' 0>
ACKO.286 ACKl-285 ACU-284
VAHO-U8 VAH1.181 VAM2·U6
VIACK
---""--("1 VIACK
SAS
VAH3.U4 VAH4-183 VAHS=U2 VAM<5 •• 0> It,
YNf·S o.
,- VAM<5 •• 0>
SRD
.•.~ VASDIR
SLERR
__ '.)VAS

811 Ddl..O.
911

802-272
806_267
8010 .. 262
8014 .. 256
8018-250
8022=244
8026-238
8010,,212

SPA<27 •• 0>
SPAO-11
8PII1Ql6
SPU-12
SPAS~l1
SPI\8-1
SPM.6
SPAI2.2
SPAll-I
SPA16.l02 8PAl7-JOO

SBUS SELECT=SBUS SELECT
CLK_NR=CLK_NR
-

til

.0>
SOl .. 273
805-268
809-263
8013-251
8011-251
8021"245
S02S .. 239
8029=233

...

_TRA_VME

. ___ . ____ .__ .. _ VDDIR
i VD<31 .• 0>

___ .______________________
DDIRl-206.-llWHL----.. - - - - - - - - . VD<3 •• 0>
Well 0>
VOO=90
V01=!/2
V02-91
V03-94
V05 .. 96
V06agQ
V07-n
V04c95
V08 .. 101 V09 .. 102 V010-104 VOU-I0S
V0l2-106 VOll-107 VOU-I08 vou-uo
VOU-1ll V011=ll2 V018-113 von-llS
V020=116 V021-U7 V022-U8 V023=120
V024-12l V025.122 V026 .. 123 V021 .. 124
V028.126 V029=127 V010.128 V0l1 .. 129

WE\I

--_

g&n

::::::::~~~_

DESIGNER:
Hon Apr

SK

09.54.19 1995

fU~'[[E

FUT_DRAWING. VHE_IIITI!RFACE-51. LOGIC .1.1
JIISTANTIATION. !CPUSV VHI!_INTERFACE28PI

-----------.------1\.---------

3

---------J3--------------,-------c-'1

COMPUTERS

_QMW. .U'.r~_

SHEET

ABBREV=VME_INTERFACE
APR/25/95

Manual

VME_INTERFACE

31
OF
94

REV.
0.2

....... 1. ._

_TRA.-VME


,

VD<3Y~~~~ C:

.
'~~~~~'~'::'::'l
__ll.Ul!!l..1!'$.~~r.!!~$~_8PSJ_<..!l?___ ~~__ '<~~ II
--~!.!I~-·- ~R!!!J...~!-----l:J!illJ-lOK 4IJllH-------1
(J ~1
lOOP
lSOR
J r.::r.--,;=,,---;-\
'
6
.J 31) RESI_I!!'I_______ • ______ .. _~
-~r.::--J OIlT- - - - - - . - -

J; ~~~·~-lB-H7

1

~p~
rl

N

YADIR~

VHADIR
VDS
VWRITE

r:-~

vAM<~~~5~i

2

_1I.1~_Pt(UJ'...L

V9YSRBI!.IIT
.. 0

--

.

~v

.....

~ J

_-J
I - T5

...

lK

BC

"

CI/ .') T7

VDTACKDIR~
VDTACKROE~
VDTACK

VIRQI<7 •. 1>

0

I'K
--.J

t::JIDJ- J

~.~
N

ACFAIL

_~_.

_'0KI4~-~·

___ •__ "

\l3Y~'AILI

-.-~L

lOOP

__

~G~6~~ : :8~ ~
8>

VBGIN< •• >'
VBGOUT< ••
I
VBBSYI
VBBSYO
VBCLR'

_

_.

BCB47B

RES PWUP P i--------------------~.,
VSYSRESETI 0---..- ----VSYSRESETO u~--------·----·

g------------------

VSYSFAILI.-C _ _ _ _ . _ _ _ _ _ _ _ _ _
VSYSFAILO 1 . : 5 - - - - - - - - - - - - - - -

VGX~l~:&~~

fl

VGAP - - - - - - - - - - - - --VSCON n-- --- - - - - - - - - - - - - - - .
VME
-

,

TRA YME\I

.

_ _ _ _ _ _ VSYqMLO
____ ._

!

.

(--I ) T8

VIIE_D.el •• 0.
'~i VltI_MIIITI

,-I

U)

~

o

O:J

=rIII ______. J!.V! ! OA~<2~'_ _
~

MMMMM

__

~

-.~

J29

v~~ _______ -----·U<~~CT
',.'! -J29

_____

___

.'''L._ ..... _.._.. '" ;

'~~~.Jl.

::§::

.

.J vlIt_nll
--'. VIt!_TCk
_ VIt!_TOI
..: VItI_TOO
('I VltI_'I1IST

J

_ "'.

.,

DESIGNER:

3 3R!f-LRffi-.....Jl!,U\~ ..dIiIT_"
FLAT_DRAWJtIG. VHIClNIT_IINIT_S2. LOGIC

.1.1

ItISTANTJIITIOII. ICPUSV VHE_IIIIT_UNIT66PI

-------------A--------------

-.-----~.---------

--.-.-----..-1'---- -------- c

l

09.55.10

I~~']J~")'
1[' [~~
'~.::' .~ U..

U

_I

COMPUTERS

;

(l

VIII_IOOI1f

VIII GAd.

l'=-~_----V.9~-.-----. --·--,--rn~ ~

jij

VIt!j.1

q

:I
",':-In
r ~ ~I
_~

- , VltI..AJ)DP

VOA<1!._ - - - -

_ _ _ _ . ___ .. __ .. ______

~~~~~

00000

(!
-i

.""'x

~,
H

VIII_lACk
.;;;. VIIIjJ«S •. 0.

e8418

S'iSFAX.L

,--

I

~

(~; VItI_11M

>ll-1~~BT12
6
'J39

.~~..!4> ____. ____

~

'IKE_IUD"'"

'-I

_1 YHI.,AItCP

__ -

.. ; VIII_SUl'LK
__4

,~l

SYSFA.Ii-::'-~ --I~~~~_~~---J--------YHJ

.~--·L-- .~

~~~~~~~~~~t~ ~j-------------------

I

-

lOOP

cn

ie

VII!_LWO'!)

..,

--Y.~&~~t!-!..------.---.. ---L---------~-dn._m 3_~_"''''''''

~II·

VIACKINIS
VIACKOUTI

_T~..

---.

-----"1-------------- -----------

I
VIRQO<7. ,1> ()

~~g~~lt6

t

T6
VALUE=lBH7
BCB47B

"-.'

~~~;:l

____ - , - - - - - •

~B~fm6'

4

. .I

VASDIR :::
VAS 0

VRETRYI
VRETRYO'

3

=.tr

J49

1

~ VltI_A'
_~.I~...L__ -0478j'" ~ (.1~12\
.. )
I hv(')'
,/".

_TRA

_~~~~I
~

~ ~f&!

P:I:
g:;!

_______ ----'£A_S.J~~!1.0_ _ _ _

I

VIII SYSRB.!!! _ _ _ _ _ _ _ _ _ _ , _____ . ______ ~ _____ ._. ____ .. ___ .

M

N

_ADAPT

__

:>

-~\~

VA<3 •• > 0VLWORDO

_ _ _ _ _ _ _ _ ---'. _ _ .. _. _ _ _ _ _ _ •• _ _ _ • _ _ _ _ _ _ _ _ _ . _ _ _ _ _

~

_ _ ..l_ _ _ .••• _ _ .• _ _ _ _ _ •

.

.

~

___

.

B

A

" ..." ...,_••

VME_INIT_UNIT

APR/2S/95 Manual

__ J

VME_INIT_UNIT

4

:>

SHEET
32
OF
94

REV.
0.2

A

_ _ _----'-I.

_______ .___ .. ___ ~=J

B

_

c

il~i1~-~-;;;J
I" --..... -- -2'1~T~ --

/ ........- - - - - - -... - - -.... --- .. -. - . .'''h.L._. - ..- - - ... -

-\------1.
:.:--==ll
1

, __

M

.YBR'
.mO. _ _ _ _

.~.-.--------=~~

BR

.... 1 ...

_y::~,~~s

_TRA_VME
 VDDIR ~
VD<31 •• 0> L...

~

:

I
I
yADIRr-

VA<3LW6~6
I

_ADAPT :
_ TRA

1

VM£_D------.----

I

2

1

YJl'!!.W~_.

-:-i

V8RO_cl_>_ _

-f=-----

V8Rlili
YI1E~!!.!.O~

-

IODY_TlPI·tLUIIIIIOO

VMADIRI

_ _ _ _ ~l\O

€ _

VDS<1. .0> ~
VWRIT~

VAM<~~~ij>

.n

.J1IC:!!!lc3>

yllOlH
___
V,-IIO=IN~<=O,,->_
Vile""

VASDIR~

...._-.--_ .. ,

_J

YMI_SUCLK

~

H

I

I~I YME_DS •••• 0.
(i YME_1IIt1T1

-..----

ti

(J)

--=~~~

,~

~

'-=1

YMI.....

d

YMI_I11'ACI(

~.

VAS 0

VDTACKDIR

1

10KI.~l!'.~L

VDTACKROE~
VDTACK

-..---·~.I 10K

C;

VBERRI

vX~¥~i

YMI_8U11

~)

(J

VIII_MImIY

~:

q'.

YMI_"O,' .. I>

VIRQO<7 .. 1>

3

0

YSYSCLII

6

SYSCLK

,') YMI_tACKIII
'-:.. VH!_IACICCM1I'

VIACKINh
VIACKOUTij
!

III

\~~OUT'~~
~

YHE~~

__

. =:~.~:~: :::::::

____

--''--_......J.!VH_~_IlQ.Q.1lr!~

6~~S&W&T~ '8'-

_____ .. _

'~I YMI_SVS .. ISET

IJ YIII ....C'AIL

~~gf~ItI I.)

4

VGX~X~?~~ ;:-.-

VGAP
VSCON
_TRA_VME

I

!

llllI. _J.__150R
rlf2§9,.----1~21!!!!$.I.IDJ!.2.illC!my.~0.~_ -1-__

01100

~j~ .ll-----rYJ!~.J}~~L- .. -.. --- . _ - - ' - - ... __
'0,;4 m~23
_ - ..d--~ . I~:Tl~--

.

11 ...
J23

lOOP

.•.- ... - ... ----.- .- -- ----.-.-- -



_ .... _
___ ._.Y.!I.B.fiCL_ - - - - - - - - -

.. - - .. -_ ..

--.-~

ARB

TRA yME\I

DESIGNER:

f=t]R: [[ [:

~~H~o~n~A~pr~~3~O~91~5~5~'2~1~1~9~95~

... __tm.NL. _____._

r:l
.1

~Q.

VII!_SY8PAlL

l._ ... - ... - .. _.....! YMI.. IYSCLIt

-~~~~
I

ABBREV=VME_ARB_UNIT

____~____________________________~
APR/25/95

Manual

fLAT_DRAWING, VHE_ARB_UNIT_53. LOGIC. 1.1
INSTANTIATION.

3

-j YMB_8I
~·,YIIUIG()II1'
> Ii
VBGIN< .. >
VBOOUT< •• >
V BSYI
VBBSYO r~---LCASYSR~~~~~ l -.-.-~-----.
VSISYSRESETIJ

.

~.

VRETRYO'

VIRQI<7 •• 1>

'

, I YMI_tACK
.::. VMt_AJhS •• 0 ..

-.---==-~\.

YP(!lH~l!

_

VIII ..... ]!.
VIII_LWOI\JI

., W'-"_'!

_ _ .. _, ___ .. _

BGIN BCLR

J24

I

.Iii

, '1

ICPU'jV VHE_ARB_UNIT40PI

c

COMPUTERS

VME_ARB_UNIT

REV.

4

A

c

B

C4911 lOOP f-.-.--

o

--....-{l!!~!>J---

yME BUS\I
TRA yME\I

I

-:-':::r.~~s

1

- _.. _.1 ..

"""'!

_TRA_VME

~-''!II,-00P
___
c5°11
- - -"-~~----~-----··-~-l.\.,!u;·J42

i



VD<3Y~~A~ C

.

,

150R

J

;.l so

2 . ___

'5>r--_~_---!V-,-"III!I9..fl!...___

1

2~
~j
J42BT12

b

b--- --------.

::

___~'h

~G~A~I ~~ 8
Ii
l8-

vVG~t:R~~w,

LCASYSRESETO,
VSISYSRESETI \:.::

L....----

v~~s~rs~r L-

VSYSRESETO

8

VSYSFAILI
VSYSFAILO

h
0

~~8~~ItA ~

4

VGX~I~:&~=
VGAP_

VHB IROd>

I>

_

~==-=~l r~'b

~=:~~~~t~~ ::~§-

~

J4

d.

~I

C!

VIRIIO...ili _ _ _ _ _ ._._ ..

VIACKIN
VIACKOUT Q __ _
!
VBGIN< •• >
VBGOUT< •• >
VBBSYI

ya. 1K9Cl
J

DI

YHE_8lM

(l VME_",,",Y

~~
_ __

VIRgo,?

I

(} YHUI

dw._~~. ~

~~~_6____ ~~ _____ ___
_ _ _ __

2
Ul!

d>

V!!~.~>

H

...., VHE.J\IIeS •. 0.

VIROOcS>

VRETRX¥
VRETRXOVIRQI <7 •• 1> 0,......;&V.&IIRlII.9~1:C""I~I>;...-_ _ __
I
VIRQO<7 •• 1> ()

~

__'llIIIIROd>

VDTACKROE~
VDTACK
~BIImI

I

VMI_"~CLK

cl :::::!E

VDS~

~,

VHI_IIIOc6>
VI

_J
-'l

...

YHE..LWOP-O

VIm IR~

J

VMADIRI

lACK
VAM< •• 0>

w~ ,.1

...

__

_ADAPT
_TRA

q

__

Jff

!

3

VH._I!"!!Q~_~_.

12::

VA<3Y~~I~
!:
VLWORDb

2

~~

~1I,ooP
mI-~---------~~:
:30 _._~~t>_111 L~=:: =~~\
C"I,oop -lllttr~.------- ~ :12~
Ll'=~-:;~=:~_==::;;:,i

---- lOoP

BOOY_T1PI' PLUJdIJlIO

. __

1

VME_Ocn •• 0>

,

~:

f)

I!

VMI_IROe1 .. "

.•. ___ {--, VHE_IACKIII
____ ( , VHE_IACKOOI'

,-j

I
!

VHE_8~eS_ .0>
VMI_lIOlIIel •• 0>

B

I,
ti

3

,_\ VHLL8GO(1fof) •. 0,.

:~l :::~~:

_ _ _ _ _ _ _ ._u!J

oj VHE_SYSUSl'1'

ct VHE-"C'AlL

.. I VMI_8Y8'AlL
I

____ •_ _

----.ll~J-!!.------~~~;a-hr--

- - - - - - - - -.... - - - - - - ------ _ _

'l!~mlrr____________ .~

.::JJ

VHB IACKIN

_______________

--Jilt ~~~l~-U~-'flgl-'~C;~----- I~, -(

_- VHI....YSCLK

!

-- -

-~~~~

----- - - ---_______________ ---'

I

4

I

VSCONh
_TRA_VME
'

------- .---.~



DESIGNER:

I

Hon Apr

. -,. -:-,

~-]

PLAT_DRAWIHO, VHE_IRILUNIT_54 - LOOIC _1_1

Rf
'. ~-=- . .

~_ r_.~~2-' IC--

3 3Rit --omlr---- .i!WBIl-L

1I1STANTIATlotl: (CPU5V VH£_IRO_UNIT74PI
-A~.- - - - - - - - - -

-------a--------.-----

c

':'D~~ftG.:

J 08: 56. Jl 1995
'-:-:::1

[":'::1

'" _

COMPUTERS

L

VME_IRQ_UNIT

SHEET
34
OF

APR/25/95 Manual

94

::::1

VME_IRQ_UNIT

REV.
0.2

A

r-----~RA

~-~T------

VME\I

~ti~'!"·


TRA...VMVDDIR [I

_

VD<31. .0>....

LE

!!

h~

B

________._____L____._

-

..

!

.

".

V
I

_.' I

V~BI~rRYOII
...

VIROO<7 .• 1> ()

-

!
VRETRYO,
VIACKIN'S'
IROI<7
•• 1> ()
VIACKOUT'
I

-

DRAM

D

-

_~~'/~?S
~

3'

I

1

~VII!-".n.JI

I.Cj j~

~~--~
:~: : - :~-

--""""-

L~crnL
!lL~-.~_

!!:::n· -10K. -'!AL.
10K
VMACII

TL.m!::J •• 10K

CODE BUS\1

-1.L1W

M~'

- -=-~ : :~': '

iH"."'---Cf.R3.----t1lL

--

--

_

4

'-J.'

~I w~ "
,I

8.

--

0WL~"

q
w.__ ,, __ •
n W, ....

r>o

'-'~(J

~

••

__ ". ;

3

' ) VIIE_SVO'U'"

VSYSRESETO
VACFAILI
VACFAILO
VSYSFAILI'
VSYSFAILO I

"~j VM!_~CrAIL

VS1SCLKL
VGA< VGR~=
VSCONb
_TRA_VME
i

L __ _ _ _ _ _ _ _ _
~

,

SONDER_1
SPEED
~

---~.~

J~2.
I -~--- L<.~,r--~-­
__ V~L_ -------t
_X'. ~
,_.~~_8!~!L _ _

I



~_ -------~--·-t=rn.ml.' lK--·--------·-~ln:_l~-·-·----t-~- C<~t---~'L----- ~----- ------~-.I
~

33F1tOiU·!r-~.lJ~;NIL~r~..._-

ICPU5V VHICCTRL_UNIT67PI

A

--'------'-- T----T-B --------=-~~-_=_1---

DESIGNER:
Hon Apr 3 08.55,16 1995

ffOR[[[E

FLAT_DRAWJlIO, VHILCTRL_UNIT_SS. LOGIC .1.1

--.-.-.---------

I

c

COMPUTERS

VII!_SYSF~IL

_....;

VM!_.'fSCt.~

cyV)tOCJO

Jl0

__ .__ • _ _ _ _ _ _ _ _

'j

_VHI_BU'

J47

VB!AAO

1 ____- - -

L._~

JlISTANTIAT10N.

H

V'IE_BBSY

VBRO<
>
VBRl
VBGOUT< •• >
VBBSYI !
VBBSYO
VBCLR

4

i ,_
n!

'VII,,-IACI

i

------.-.---------

(1 VII!_L"'I\D

R

RRI'

-

n"_~_

"---

.....

---,

VDTACDTKlgn~_._~
~
V

----

!

!

i

------_._--_ ... ----

.150
.150

I

TRA_VME

I

..

J50
J50

ADI~C'ADAPT
VA<~LW6RD
0
-n.MT n.

21

~.-

~QIR
--- ----;J!Hr---·-·

vB~Im~~~I
R VgrACKDIS
~~ACKDIS 1)-._

!
I
!

C==-=-,

ADAPT
TRA_X

IIODr:.TYPhPLUllllIlIO

1

Y

______

-DRAWING-. -

VH~ BUS\,I

ABBREV=VME_CTRL_UNIT

- - .. -

APR/25/95 Manual

VME_CTRL_UNIT

REV.
0.2

A

c

B

___1.. _______________ - ____

~- ________ • _ _ _ _ _ _ _

TRA VME\I

TRA1VME

-!

 VDDIR

~

VD<31 .• 0> L-

1

J
_

VME ... BUS \ I

_,,"p...IU.

~~ d'>._~

r.r~

VADI R 1
,.------------ .
VA<31 .• >
yAd&. 11:
VLWORD 0
_____'U'~~ __________VL'
I

~

1'"
I

•

ADAPT

;

VIACK
VAM

VASDIR I
VAS

6
VDTACKDIR
~I
VDTACKROE
VDTACK
VBERRIVBERRO
VRETRYI
VRETRYO

0

6

I

VIACKIN'8
VIACKOUT

,

VBRI<~.

VBRO< •.·S>
>
VBGIN< •• >'
VBOOUT< •• 0>

3

31>......-_ _ _ _ _ _12 _ _ _
v ... dO.
________

'<28,;

<25>f----

VAcas>

<24>L

v...ca..

N

I CJ

<18>1

VA,..

V...el6>

<15>i

VAelb

I

<14,.1

V"'cl"

I
I
I
I
I

<13>1

-

~-.4 ~ ENA ~,

VII.!I~_'<27>,

VlldO.

<9~

v .... , .

r-

<8>1

I

<7>

,

8

l!!

B

12

llO,~'B

L2

I'AI

110'

IRNa.

-- ,_ .... ~IA..

~ ~~

n

fNA

r-lfNA

ABT245

,

Vl~c!~-"'-:<20>

VIIII~<\!.

v ...c6.
VAc$>

ABT245 I~:,DIL~~

ABT245i~t-rr-

-.

Ci:

!_~

BNA ft'
it·
.. ABT245"~I-~'~:pU'B
lei

------.i' IRNA

'~Iii.·

ft.

h,..
ABT245"~

1

<4>

_.

v......

mil ...ell

.1>

. VIIEj.

J
J38

VIllI Aell>

I
"

(', VIlE_OS." -O.

~I ::=~:!I

N,

B

~ VlCt..,AKcS •• OJ>

M

m!

~

OVII£-"S

d

f:]

C,i

a

!d3>
!

q

2

~:

VIIp"'DTACt(

I.

VIII.I!IUI
VIII.uray

!

.'l!m.Ml~12>

J38

VIII_tWO'D

..J
VIIE.IUctlC
_~ VIII.SU\DAT

19

_.,.<16>

I

i
m-

'HLYM1!.kWQ..I\l>_______ --(j

~_-----....YH!!..A

VIII.Uo<' ....

~

I

,

J~

..YH!! Aelb
ViIII..Ado.

><11>

o

I

VIIE.'ACICIII
() VIII_'AtICOIII'

dO>

I

~9>

VIII_I~<) •• 0.
.:, WI_It'llIl« S.. 0 ..

rj

ViIII,.A"'.J.:9>

J35

I

J3b

I

..--~~~~_"';<1>

lI

(~,

WE_Bl"..ouTcl .. 0"

a/.1

VIII_8In
VIII_IICLII

0.,
_~ ...~_·---"

I)

VIIE.syoua"

V!I!!--"~~ ___ j.:2>

('l

VIIIj.CPAIL

~~.. 6>

.3

r"Ti::

'

ViIII ...

f-l
k: iRK ABT245
ft'
1 ,AI DI~I--h--' J43
_• . - A
.10. -81__ fL-VIIIIj..,.
_1 (' ~--'-~!-fT-' Jlr----

---Ai<: fNA ABT245 l~:, 8
ENA ft.
I, .... DI"~ ' - ~ A ABT245 no,"jj ,5
I
v...c J>
~c ENA w,
~~'-T<3)or-------------f----ti-::"
ABT245 ISO' 81__ ~
. .4~C ENA ft.
l'AlDI~!-'r-<2>1
V.A~t-~"
ABT245 1101' 8 .;C ..
I
~
EN" ft'
hAl Dl~1- 'T"1>'
VAel.
---"
ABT245 lao, 8~- ~
<0;
VLIfORD
lNA ABT245 Il~l<5,1

,

:

I'
-- - - - f ' > M
ViIII....Ml~~l9> CJ
\III!--"..!.l_7._ _~17> IX:

J35
J35
J35
J35
JJ8

V"'cl>
__ 1--..... ~"
ABT245 110,--8 ~eo _
.~ fl- BtlA ft.
1' .... nl~l--hr---'-~--I---r;":: A
ABT24!i~
11.

<6>r-------

VSYSFAILI
VSYSFAILO

JJ5

~--rt ~tr::~BT245 lIOP--Br-~-----;'

I

dO>'

_

ABT2451~:p

,'- A

~~.
1r"ABT245
t---rp::
~f{
~'l,AI

~!tr~-~I-!'-v"'~-~t----T ~" ABT245 '~:pu'B !Ii 1----" I('~-~-,--;"'~t-rr--

dl,J

I

I,,.. DI~t-h--

ABT245 '10. -8 ~!i
~ f<- ENA ABT245 1 'AI DI!I-~
_J
"ft'
I~:P B
Oft/A ABT245 110' B 17
L.... "

VAcl»~'

I
<12>1--

' u
'

<,

I

I

'

,-

J33'
J y----IJ!I!I~~~------1<29.
',
r3
Vl4B.....~ _ _ .j<28>,
J33
"

FABT245-~I--[s

__

1

:

I~I:NA ABT2451~::m::=fI= J33
VIIu~~~!..._ _ ~"26>
~Tf(-~---r~~I__h.-- 'J33
_;i~ A ABT245 ;::-'8 L~
y--__Vl4~~}~ ______ 25>

1M <20>_ _ _ _ _.YMll·
I
I 19 I
VAcU.
I Ii1 < >j

~~g~~I~a'

I

Y!e~ ___ -,j.':''' ~~T245_~~;pU'B Leo
f---'lS: ~NA ABT2451~:~r--rr,-

J3
WII--MU~ ____i.c24>
<23>1_ _ _ _ _ _ ~ _ _ ~~ 9C fNA ABT2451~:pDI&I-rr- J35 ~._ _ !<2l>
I'
~I
ENA ft'
hAl
JJ8
:
<2~"lVAcUo
"
ABT245 '101' B
....--_VlI~.2..._____ ;<22>
I
~!t ENA ft'
I'AI DI~ _~~ J .. 3
'
I
<21~
v...cU·
I
3~"
ABT245 lSOP 8 ~, .
VIIIIA~~~ _ _'<21>

~BB~~~



~C~--~~-lr
'< >:;:
A
ABT245 ISOP B - -J , - - -Vl411"'e30.
- - - - , 30 v

VAea&>

v ...<2b

~ fl~
;

'- iT-- -In-----!LM!------J3 3
WI! e31>
8:-fL31 > •

~k EN" ~.
I'AI DI~r--r..<21,J_ _ _ _ _ _~~~ __ I-Tt-::: A ABT245 110,"8 L3

VBCLRLCASYSRESETO
VSISYSRESETI
RES PWUP P t-:VSYSRESETI
VSYSRESETO ~

VSYSCLKL
VGA<4 •• 0> rVGAP _
VSCONb
_TRA_VME
!

1~ EiiA-;;;----'-~I__r_.__
DI~

w
,
--.lJC 'ENA-ABT245
IIAI
---'r~"
810P

-

.. 26~r

VMADIRI
VDS ~
VWRITE'

VIRQO<7 •• 1>

V... el >

<29>1_:_ _ _ _ _

:

-

VIRQI<7 •• 1>

"

I

I

IODY.Tl'!·PLUK8111O

2

<'

::;:!

I

- TRA

~ VIIE_;':7:'~·:0.

VADIF

J39

VillI .... 5>

J43

.VlIB .... t>

J43

uuw

J .. "

k5>

,

'.. 4>

I

J43
I
"'J4Y--VIllI ... 

(j VIII.SY8PA't

Yl!J..!.!!Q~_.~\l
Yoiii- ""0;-----------._--.-------------.--.--.- ----.---.. ----- -- - ___~!>mB... _ _ ._ _ _ _

I

'J...

~
'~--.

•

.i~'h ~~T~Il:> _.~p ~1

_ _ _ _ _ _ ~~8.?__. __

__

j"

VD<2.~!.

<26>;
<25><~.

VMADIRI
VDS<1. .0> ~
VWRpE

,WL~" ..,.

,

~
V

Jj"'1""-----"lI.!!..~~!-.__;<29>
.Ti'1
-- ___
__ .f'2B>

~~T;'!Il:J _'~P__ ~t-r---t-:r1'1

YKZ 1><21>

.\,;21>

VII.£ 1><26>

.'---:<16.

_ _ _ _ _ _ _ VD<25>__

._

VIII_BUCLI!

~

.

VME_S!JU)AT

~

<24>'-. _ _ _ __

y!.O:",,~

<23>;

VAM<~~ .ij~

VKR_DSC 1 •• 0)

H

IjVIII_IIIlIU

VASDIR'5
VAS
VDTACKDIR'
VDTACKROE c:~

(i

N:

VIII_lACK
...... VMItJJtcS. ,0)

.

f"'l'

~Biru\~

<19""~

\'
M

~,

<17.'I

~;

<16 •.,....._ _ _ _ _....n~
<15~

I

.1-1

\11)<15 7

I

~I

Ci VII!.J!T\ty

@

I

d VIIt."OC'· .1'

<12>ir--------'==-<11,1
<10,,1

!

VBRO< .,
>
VBRI<~
..
VBGIN<
.. ~>>
VBGOUT< .. >VBBSYI
VBBSYO
VBCLR
LCASYSRESETO
VSISYSRESETI

_

~

_

VD

~10>
__

<9>j

~
___

YIfB 1><11>

~32
_ax

-AN ABT24:>
~Dttu~~.~~,~~·

YIfB 1><10>

I

YIfB_l> . ,~p.. _!H·

VD

<5~~

<4>1

VACFAILO
VSYSFAILI
VSYSFAILO 0

'.-l

VIII.IBSY
VIIE_BCLR

"

VIII.IYSRUET

,.'j

VIII_AcrML

VD



'~i VII!_~ACK

t?,

______ ~ ..

til

'-I VII!_AS

VIRQO<7 .. 1> 0

i

~

:

(-~

<22>,)-;_ _ _ _ _- - ' =

VBERRO
VRETRYI
VRETRYO·
VIRQI<7 .. 1> 0

31

1

~ VIII-"cn •. I!
q VIIt_LWOW ~

VJ!II~~

<27>'_________ ~lli_

8ODY_TYPI-'LVKBIIIO

0»

~ ___ ..Yl!!!~AQ? _ _~lO> ~

<29>~ _ _ _ _ _ ._yt>__

_ADAPT
_TRA

2

-J37._-- ~.'P.!B_~l!...._i<31>

_ _ _ _ ~Q,

ADIRI
VA<3Y .. l>e
VLWORDt>

I

JJ7

~

-~::~;~~.
yttI P({I)
P2C4. 3
CENT1\"D~2~
'----- @
MI.,!;III\,'' .....
@

'.:v

'c'
--- ~

~~C10

;WWt\~-;- @
HIYLlIltAA•·•
@
FP T~KO

P2Cll

FPI; ""PROT

P2C14

8

5

P2C9

{;;\

FP:}L'~4A

B3

~

ii~2'

.

8

11

5

HI"R:~WJ01'h'

- - .'",!;'"'~.,.....

~

cENT1Lti'SY"

@
@
G:\

CENT

8

'--'

.I·R"A'I.....
F

·,·B....·!!!'!!'··
CENT_INIT

10

@
G:\

NI{rt.1If1 WI011I"

- - -- - . - -

~~1L.@
P
Ek.J1. {;;\

11

"1/1

Rli}-=--=tNA

NA

~OON.UDH.I

-

_CONN

I

:BUS~X_KI3nc::>

I-SERIAL

~OOII'VIII_U

I\OOII.VIII-PI

~~H~~--

I
I

FLOPPY

~OOII."y

.FPY DENSENSE'

~

I

-

~rt.t

~Q
r:(
I

I,

---

r':I~KI
K
~, I K

FLOPPY

DEtUL_______

>B

BUS!
COL_M !_ _ _~~TlLQQJ.Jt 1
COL_P r----~I:L.CQL P
TRA M ,
___ L
TRA:P r

~00H.'''_'''_11t1

-= CENTRONICS~
-

ETH_P~WER~.I
ETH_GND f-

1m

r--

-~®

.'''''''10

- - . 1 - -.. V ET

___E'I'H---R.~GJ_L I-®
ETH PQHEILL @

B12
o

~___

..L@

VHB_P2C<31>

---J VHB_P2e<30>

- - ~::::;~g:~::

-j VHB_P2C<27>

I'lnw

-

-~~-

-=!

~_!!!!'.l_.!!!!.'!!!"..!:!:L ___..1 VHB P2C
VHB-P2C

..J

P2C 9_ _ _~ ..l!J.!!.!.J!!!.!!LO!!!!.L_ - - i
2C ---.-'!!!!"!'!!'!.!!!!!!'!!!-_
-

P

1

M___ _

-

B

3

VHB-P2C<10>
VHB-P2C<9>

__ ..l!tt!.H!!!-'!!.I!!!!!L... ___ ..J VHB-P2Ce8>

.,"'".. -

H~:S.i~·-"J~"·
VHB::P:W<7>
___<.2_ ;:;;~~:::::--~ =:J ~=:-;~g:~:

~Q~~;:';:~!;;--=

-oj

~::;~g:~=

-------!!I!!.~~-- ____ ] VHB-P2C<2>
_1 VHB::P2C<1>

---.J

@J.--!-.HC

~

VHB_P2D

...J

VHB_P2Z

c)3 •• I)o

i cll .. 113"

~OON.m'-rI\PL

.-----------c-

i.

-----_--1!!!'.l.!I~..!'_'.P!!'.!.!...__

6.....YJ~

~OOII.mt_'~PL

DESIGNER:

-------- .-.---

,

VHB_P2C<20>
_-1 VHB P2C<19>

GI'Da

(CPUSV VHICIO_AC29PI

t-1!

----< VHB:P2C<24>

--..! VHB_P2C<23>

~~g "1""---=-.-=:""'_ ::: ~::!_~~ __ ~ -------j ~=:::;~g~n: B

I)

FLAT_DRAWING, VHI!_IO_AC_S9. LOOIC, 1 .1

Q

...,____-_-~---'H"'~,"",~~~-;.~- _ _----, ~~:=;~g~g: ~

-

kOON.mC'IlI'L

,

~

----i VHB_P2C<22>
__
VHB~P2C<:n>

ETU

-u--

-.---l

______ -- ~:-;~g:~~:
.

Pac
Pac

@-L..L.Y-~!L~OL

@-

--

----

P2C

B13

@ ..LETH POW

2

rn

----,VHB_P211<1>

--

------

--~--Jj§

(c))..J-'L-..l!..-!'LJU!-'REC

r

....J ~::::;~~~~: S
~
eI ,
I VHB_P2C

"H L!!!!.I!!.I!IlI!L_
"'tl_~
!I

r~

Hon Apr

INSTANTIATION,

R

ETlLTIl.
TRA.

ETlt.-B~CJLL

ti

Nt---mw'
HIL-- n,--,f I S : HI. LI"t VIPlM.!O
.IN LI" VIPlN.\O

{Q)

----1 VHB_P2A<5>

I

1

VHB_P2A<2>

->---

L~~.J.L~

'---1 11__

REC_M I
REC_P

B11

__________ -1 VHB_P2A<6>

~--.-

C

;. ·.JJ)APT_ ····1
1 ETH_CONN I

VHB:P2A<13>

--------1 VHB_P2A<8>
______ ., VHB_P2A<1>

<~----

~00N.8111IAL

~::

..

J VHB-P2A

II\,;
'" ~----

:::::::::~

1!!.!o!H1
::: :'::::0
m
nI

_

-=,

=~ ~~:=:~~:t~:
~s;;~~~------ ---j ~=:=~~~:~~>

_ _ IN

SERe GND L
SERC RTXC l-SERC-RXC :_SER_CONN
I
I _BUS

:g:~:~g
S~=~~: !~~._-:-=
----.----

SCSI_ATN

~Ing:~~~

SERC_CTS

- - 1 VHB_P2A<19>
VHB_P2A<18>
VHB_P2A<17>

- - -~--------- '::-~:J ~::-~~:~t~:

--~----------------·s

L-__

'.

1\00II""_"'_11tI

SCSI

I
SERC_DCD~
I~r--

SERC_DSR
SERC_RXD

I

K

FPyF~R~~C=-FDiI= -lUi. :I ~K
FPY- GATE ~-- - "
FPYVrm~Ul1 C
W HOroo=-- =in: I K

,
F~~ D~SEL r---=--:..L
~ <~~£g~l>nus
I

I

~

rp'l STEP ~-~-~

'

1

:I~

FP'l:mCKO l - - _.

:8@)
F!J~-~~~it==.ItliH FP'l
HEADSEL r.:=n...
3

1

1\00II.,"_

::::::~ ~OOII.",

f

, >t FnyDH~iMG r-- ::
I

11

---,

- ---- -.----- -- ---SCSI ATN
----I

~OOH·SlllIAL

~WI

VHB_P2A<22>

SCsr.:ttST-:~~-=~ -=-'-=1 ~::;~~:~~:

OR

I-CONN!

'---

VHI!_P2A<2S>

-of

==~::-_-_ -~- __ i ~:::~~:~~:

'U:J!MPW_R______

!ADApT' '·-·1 SERIAL B

m;.._H_ @

Q _____._____

~8~I-ii~---'----1

KBD_MSE

FPiLlEJECT

~_ _
~

VHB_P2A<:l8>
VHB_P2A<21>

SCS:t:CD

8RR

KBD PWR 1
KBD MSE colm
I

____

D

_.!!!l!..Y!!L!!1!!1!!!!. .. __

OR

l ADAPT KBD DIN L~KBB6MTcgNN
===tIlDI-KBD RBD DOUT~-~EIN-CO~ .B1 - - - MSl:: DIN
R2 ~--~ _MSE MSE_DOUT L
I

~. ___ ---1 ~::~~~~~~:

_!!I!I.-!-I.!!!.'lllml'.!.._

::::::::::

~

~_....J VHB_P2A<32>
--------1 VHB_P2A<31>

_

__

~J~

t

LI~~

pm-1ill!.~1ID!!!__

[f}t.:Bf~HJl_.U ~

2

4

I \I

~i¥l\'''r-----;--;

~

- _ _ _ _ . J VHB_poe

I :BUS

~)
tOI

~~T~ "CK

' -15 •• O.

~ ~:'~:.OA

1t00ll'8UIAL

~~~g-a~fi

SERC RTXC
SERt! RXC

'c'

~ VHIULUIO~:~~~,

1100II' 11II1 AL

~~Rg:,~g

':::.J
~

CENTv<7>

t(j\

~AC1L-..lL

H'rIL'r.~I.....

~~TR.D

'c'

~

rnzHEC>U--__._-T----

D

----VIWBUS

:::::::::::

SERC CTS
SERC:DTR

Q..~~__ ~L ~
NIl' LI~ID1'jI"
t~}

~_~_ t:::\
~

t:::\
~J

_ _ _ _ _ _ _ L - __ ~_ _ _ .

~~~g-~R

B2

0

C

SERIAL A

sERc-rum

I

v,.....

@)

I

;=CONN

~OOII·"Y

rl'l~,~_D..wsiL ___ L

[

. ___.

=-. ____

B
-=-~~~- - - - - - - . 'ADAPT

~OOII'''V

f!lLHI1K

.. P-MWlNQ._

SK

3 08,55:36 19!}5

~~~j[--"r~
'~_
~
lL
_'I

COMPUTERS

ABBREV=VME_IO_AC

APR/25/95 Manual

VME_IO_AC

..W9f.l:'!.US

I"

.

4

SHEET
38
OF

94

REV.
0.2

B

A
1\OOII."Y

---t!m:=1R

. - - - - - -·-iOOH."Y

~~:;,()L---{!2-~.kNA--1

10

1\OOII."Y

/') I

@

d'L_~~___ L

11).f~'lf'DENSktQtN-. ~

1

"IAL1H! ,nOT."1

_____ FPY

B1

"I

'.'
--1-1@

P2CL~.

SERC_DCD

B2

~NTR"'Q'S'··' ___ .
CE.NTRD~O~

--

.:.1

B3

SERC:RTS

FPY D.LR

HI.'l.LIMlII:'OTM"

F~EP

~~~g-d~5

@

-FPY
"'Jl.L'l'.~~··A
¥'flU/AT

@

P_~Q!J

8

-" Hii'III"U01'H.'

F~'~L'~~~:
FP

@

kOO'hVMI..'2

3

r:

I

I

:

FPY STEPI--- ___ 1'
y
FPyF~R~~ C---y
FPX:WRGATE I- -__
FPXyDRVSEL C
F~~ Dml~~~ f--- Fpf

I

r :I

lU'
_

G
-my HOrm

<~~£g~~>~US
'.. .
.. .

FLOPPY BUS \ I

SCSI

-m:

LADAPT
L-SCSI

4

:g:l::"~
:g:~:::~

SCSI_Hsa
SCSCCD

s~~~~~

SCSI_RST
TI!IUIPWR

_~

K

~

K
K

~

~OOM."'t_PU_J'U

'-00II.", tv_IU
1I0000."':tII_IRI
1\OOII'PPY_tII_I1\1

1I0000."Y_tII_IU
1I00'h"'_tII_IJ<'

~OO.h'PY_tu_JlU

-. _.-= :=-:= ~::::~~:l:

I

i
2

VHB_P2A<5>

~----

VHI!:P2A<2>

--

VHI!_P2A<1>

.. ____-___. _____.._~
_
----.J
~---

M

eI

s.
1

--' VHI!_P2C
I
----l
VHB_P2C ~
---j VHB_P2C<30>

~:::~~g:~::

IIIE

L'.L.''''....

..

.

_-1 VHI!:P2C<19:>

I ETH_CONN I

B11

I_ETI;!....CONN_BUS!
i 
!
COL_M I
ETH CO~.JL.l.-1@
COL_P r-----~GQtd? L
TRA_M
~
TRA_P - - - L-ETH T~__~
r
REC_M I~
ETtL'l'M_~@
REC_P!( l _ _I::j'jLBJtGJLL-@
1 - 1-

B12

_ _

1

I

I

ETH_P~WER :.~--,
ETH_GND f-!

tLC__ L@
>

1

-j

@ j

'--,
~:::~~g:g:
---1

--.::]
~::-:~g:n: ~I
-~
VHI!:P2C<1l>

or==-_-=__ ::: ~*i~ .. :.-=::J ~::-~~g:u:

VHI!-P2C<10>

______
I~i}_-~~~~::::_=

~=::~~g:l:

!lli!.H!!L!!!l!!'!_·'_
_-1!!!lJ,W!.!!JI!!!!,L__

==:J VHI!:P2C<5>

--_-.!!!!'~!I!J..!!.I!'!~.!L_.

--1 VKI!:P2C<1>

_~

<.l~_l!l!!.!:.!'"
·'OIH" __ - ___
~.I!!..~'M' .,OI.,!!... ... ___ ]
-

3R3

VHI! P2C<4=>
VHB-P2C
VHB-P2C<2>

i

~ ~~~:-~2D

-.!-~

@I 8 NC

~ ~~:-rl~!
(;lIDO

ROOM'!'I1L'IIPL

~OOH.m'-'II'L

3

B

-=~~~~:~;;;-- -=J ~:::~~g=::

_7 -.--t=ffiJ}1

@

~

VHE_P2C<16>

P2C 9____ .,. LIII • .!!W..!!!!_
2C
--._-_-:

@t-·4

@

L ___ETH

R&'C-L_L@
ETHJQm!JL.L@

:_-_-

:::_~:;;t;:::::-~_
F=--!!!!!.!:.!~!-.!!W~

B13
'>

@f~!
®-I-'
_:J

'OOM.rt1!_'ItPL

.~rf.US

I" . 4

:-::

____

_ __

DESIGNER:

FLAT_DRIIWINOI VHI!_IO_IIC_S9. LOOIC .1.1
INSTANTIATION I

I

~ ~------ -;~:=-~~:=~: fg

c

kOOll'BUI'AL

co

Hon Apr

ICPUSV VHI!_IO_AC29PI
'Hn"y' MY"" H¥W-"'O>tH"'"C

l.

~ ~.

< ~ ___ --I

;. JJ)APT_

-

__

<7>------ -~-I ~=::::~~:~~e>
0>----- ----1 VHE_P2A<8>

.

-= CENTRONICS~

\-____ .

!~

K

IKKI
K

1I0000'rPY_tv_m

l--=-l - -'
=1

I

~

kOOll.rPY_tv_JU

SCSCDP
_ . _" .
SCSI_D<7
•• 0
I

I

:
IUfo I

-- =!lli

~--:~-=-

I

__. VHB:P2A<12>

~OOII'B!Jl'AL

i"
rrnm
nI

VHI!_P2A<16>

..-1 VHI!_P2A<11>

r=
mlNt--_1H:f-~
t------------I~
Ir~
~ rlr.-=T-!!l!U!$.I!!Jm!!L
T
_--~ .N
,,-1!.11I-~WR'~~vIfl

L-..

-'--1

'-~.-j ~=:-~~~:u:

alU1I'wJ.t______ -=--=, VHB-P2A<1l>

:::::::::::

K'.

FPYyRDDATA L-__

I

I

~H

..

_----.-------1
\2-----_of
SCSt:CD ==~:'-'::'-:'''''':- ..i ~=:~~~=~~:

1

SERC_CTS
LIIIIVIIm!"O
_."
C~_
VHE_P2C<21>
SERC_DTR
KI. L,
.. ",OIH.,O
__ ..
_ _ _ -~ VHI!
P2C<26> Q
~
SERC_TXC LIlli .'OIH"O
- - - _..- - - .
VHI!-P2C<25>
I
SERC GND L
HI.
----< VHE-P2C<24>
SERC RTXC !K'MN L,"
·'bI"·'O
- - -...!
VHI!-P2C<2l>
SERe RXC :...ri
L,.!
VI!"'C.!1!...-----l VHE-P2C<22>
_SER_Cotm 1
_
......... VHI!-P:ZC<2l>
! _BUS
_-.! VHI!~P2C<20"

11K

q ~~Y:i~~~ f----FPY H&:.HUSEL
- ...

I..:x:

I

SERC_DCD
SERC_DSR
SERC_RXD

VHI!_P2A<22>

It~

ICc

~~~g:~I~ ~

~ FP1CTrJ~UO ~:::

Q

I

1I

~g~I~fifj----"----'1

~

_-. -~ .- .. ----.-_

OR

!ADAPT.... "1 SERIAL B
I-SERIAL
I

:r---------

VHE_PZA<28>
VHI!_PZA<21>
VHE_P2A<26>
VHE_P2A<2S>

~~§~--'-'-"--1 VHI!_P2A<19>

KBD_MSE

FLOPPY

'~rt.t

r

2-----------1

- .. -.--.-.....----... -- - - - - VHI!_P2A<18>
SCSI ATN
----·1 VHI!_P2A<11>

8R

. . ..... ....

I-CONN

iJI.. __ .---1 ~:::~~=~g;

SCst::ttST-:_:'::'-=':-:'=--~=i ~=:~~~:~~~

==til

KOD HSE com

••.,2>
-----1 ,,"U
VHI!_P2A

_

'-OOM.ItIDNIl

1:BUS

F

I 

.

P2C14

~ F~JyDMKCHGr--_-

..J ~~B~~OC

_I!I!I...!-l!!Uillm!.·,!,__

f-~C13

kOO'hVMI_P2

~

-

NA_j..l!!l!-Y!!L!!!I1ItI.! .. _OR
fn'-L'.m..'!.!.IlI!I~'-OR

I KBD
,-

NC.-.H_I@

'8
Cl!1-1

~J

~:...-=r-

i_ADAPT KOD DIN L .• "B~MTcgtillN
RBD !lOUT 1-- MSEIN-COmr-- .B1~
MSE DIN
R2ti's---! _MSE
MSE_DOUT L
! _CONN KOD PWR I
R

__ _

[Pi"BiS'KCHG l i
d'f'E3EcT 15

,

lIT

__

:::::::::::

rl1jEA'DSf;lL.l.L 1@

FPY DENSENSE'

~~

SER A cONN BUS\I

FP\'~mpR(h
FP~LIRJ)1r~lL @

2

sElt:D'

--.J NIH LillI

NA

~C12

_T_~K

i=!

SERC RTXC fSERe RXC :...SER coNN
I,
1:BUS

F.~C10

-r---J

' <15 .. 0.
... VHI!_POA

11

u

~__

HIN LII11l'01H'1

1100II' S!Jl1 AL
ROOM'BUlIAL

I

I-

.1..

~ VHIU1_UIO~:~~~!

t

I

@
@
6 __ . @
@

D

-vmr-BUS

.!;.3---.1tUV11~J!U~<1>

.:;._ ... JU__ ... (;ull~!1!_P_O_Q

,.?_

0)- _.~.4_.11!Il!nlJ'!J.l!-.C",,4>

._Q~__ U.!lI.VJ1~J!l_1;l<4>

?>-_ .. J;~ __ Hl!lYlI!!JQ~5>
0- __<;LJHl.Y!'I'!U·.9_G.~6>

5 ,~.. _ _ ..!1L.J.)!lI'mEJO_I;l<5>

.. _ .. ..2.6 ___ (UI.V1!.~_1'9_Q<6>

(~

P~7"

.~_

.. _~1._1 ~!I.YH~_~~7>

(~ ..... .QL . .J)QI.~J'_O_Q~1>

.M.......DJ!lvtlE PO 1.<8>

'':'_..

..!;!l_I1!!I.YIffiJ.9_~~8>

1)__ !l'-_._(:J.!!.l\f}l..E_1'9_Q~9>

(-1. __<;2 __ lUl\ffl!LI'j)_<;~9>

!l.~ . ...J J~ I VI1~-l'.9_D~9>

...Ml!......ll~ol~10>
J..!LJ.l.8l..'ll!B~11"

G--

_.MLJl!!.lYl1UU~12"

G-

MLilll'lH!L!.'Q....A~1 l>

A

0-- --'?L . .J.!!lI~~_!,Q_P<1>

_£!_I,:!.U."!1'-E_~Q~2"

5 •.

_M_t!l!l.'nI~6>

G-

G~

BU8< 1 >
BU8<
>

VMI_'nII__

III

alUllivtl!

10(j-- _.n2....ll!!.lYll.!Ll'.9~10>

'3>-

...£1L..U'@lY~!.!Lr.9~ 11>

100.

PO..A~14>

B

·1_·n!LJ.:!!!.I.Yl!.~_P'Q
.. _o. 
_.ru.L.JJJ!J.YHE.J.!!_Q~ t 1"

(:)-_ -S.l.L1UlYlIB PO C
.....£!.l__ illLIIHB_rQ~ 11>
.S.H__..1~JI.'D4..JJJL<;~l4 >

0- _..QU....n!!IYlIJU'!U?~l1>
0-- -"JL1;u1.1Yl1.I,t_P'Q_D~14>

c

D

(."4--.

(~. ._P.!LJ}I!J~!!_P.O_D~ 12>

Lt-

3

. I . . ......""'.

11':i~'

12

G-

VMI.'nIU VM~.TOOJ LVM ....TItITJ 0

o

t

REX ~
II--_llHUl!L............::

:::~!! r

I

lOG

VHPoIV

b-

:~::: p

()_

G1-M_...Jl!!lY!i!t.n.A~9>

VH! MCP
VH! MoP .-.-.

Y1tUDD'

."}- .

B2

C+-tA2_.t~!!.lyKE PO A<5>

I-

YHLAHC' I

til

PO A<2>

D

0-. . _«L....P~lYH!!_!'.9_~<1>

,,_4_11!!.JJl!.4J!-l'.9_~4>

Z<4>
Z<5>

G--~.~~!U.~~1>

~L.Jl!!.l.'O:If!.J'U3l>

_WUUI :

-f\'Ml':",

Y1t~_III\C ••• 0.

3

G_I~L-Ll~I.YHE

Z

Z

G-~~POZ<2>

G-- ...lL....illlYllE PO
G--. .~J\ PO
'G-' ...!L.JllIYl4Jl! PO

PO

VALUE=THRW

!

>I,

'_VHErPUS

i

coo'

, 0

j:Q1

I

~I

I
o

iI

,~I:.

4

VMI_Pl_UIO

mJIIHB

c

·vHt~~!~;~:-i~;-~
VMI.,2Cc U •• 17' ~

VM~.PJCcU .• t. i -

I. VMI.'2D

-:;."-

A

0,-

i

!

1

G-VIII",C Il .. l>

VIII_LIIOI\D

ftfM_0_k5
p __VME
~11

11

L----.'a'!~BUS<3>

i--~
_V"_ ILIm8<1>

G--

:~

II

~_~.B osd • • 0>
~.:.~

VIII;~~~~~'

Ul
1

~

I

VIIl..IlM p-~_~_'mE

It

VIII_..... '

180<7

b

Ul

t:>

iJ--Vlm
1

I

I
U

§1

VH~~=;:: ::: ,I~bU
VIIl..IAcl .. O.

_VMl....tw. !

VII~OA.... 0. :

VIII_IACKIN ~~~
VIII_IACKOIJI'
IACKOUT

H

Q_ VMS_8PM
VIIIJlCL~ ~..r---vHiLiiCLli:

VIII_IBIY

:::
I
VIII..AJI(:P
YNUODP
VIII,",,"

3
VIII_.YI~1I1T

I

0 __ VMS_lITltRBSBT

VII~OPY

VIIlJ,crML

O~~CPA.!~

fJ---~~YSP_AIL

VIII_IVSCLII ;____ -.Yf:.IS

c~~s

_VHE BUS
cYVKlc.

~

~11i

'~

I

_~~~?S

(~_

,02

I+-_

D)

J..L_.'m~-.Qp__ _

o

~L

....b!~, VMS S'(Il.~

)

CUD

VME

B..@~r,g?.

__

810

V!f~9IN___ _

811

VME-llJ~OUT<)_~ __ _

,J.!LYH1U1~_

A13 VMB os

91 PAd
PAP

0>

!I;"'

~
A

r:t:

I

WI_LII

I
I

g~

':>-, __G.6_._.YI:IE_~<.UL ___ _

,?--

__06

(,:> __ , ,__~J_.Y.!lJ;:_P<}4~ _ _ ..
C'-- __ C_8___ Ytl~_0__ _

<;_~Q._VME

() __

~_014
_)H~ ___ ~VH~_Ql\_

1\(:1-

~r'

L~8US<:U0>

0--

BUS<2IT>

:::~! ;--VRft:I&~n-R

10

020

021

0-- - .s1.LY!1!U\~~

021

022

024

o
o

.

z

",-,d.

-~Y~~~,>---,A30 VME

2

G- 018
G- _019

A_ _

A

G--

~.!I_Y:M.Jt~

~~'

012

,:-...:.--

_ __

VII~TDOL

.•

,Qu .. _______Vlfl!_~~_ _

20G--

I

_~~

lOI . . . ~· •

,~ _____~J.L_VI1~_~_~~J.~ __

()_

')

.08

(" ___ 016

o

f0-

05

_

(:' ___ j:.H_,Y1!f:_A, ____ _
(I

1.l2v

()

I.~v

-1-

I--I---j-- 029

lb~-~

3

--:::

HIII_LII1I_Wllrl1hZS

I.sv

':';1 __ 1 _0l2

c

B

D

~

~:~~i:~~~t:;;_;

_ ;::;~;:.:~:;;.C

Ul

;

Zll

~II VII~LIOCt-

I

VII._lYsrML

I~" __ ~2_.YI1_'L!2~~ ____ _

G-- ~)""""y~~_Q~Q>_ _ _ ,
C~

GilD

0 ___ 1, __ 01

__

VIII_DA"_~

I

41;

IO'~

_!=J._V_~!LQ~9.>____ __

(-t.

8~ ___ .

~~_L

GilD

41"'1Kt(a

I
I

VMS

150~Ctlb
0-" ....All....YH!W1l'~
o

_,,1..,.

b VMS

_~J. __ .Y.!:Iug?_~

8

14 VMS_WRITB

:

In.1_''OC1 .. h

G-

o

BBM

VIII_UTltYO

~

0--- J)

Z12

~~

VIIIJlTACII

G

()

0-- _~J/lIJtl\l!

VIII""

E-tI
~

II

Z9

'

~

2

G-

VMB Xli~!IAij~

-

J.~

0- __~~M~<~_

__ _

10G-LHO. ----

1

VIIIJllcl .. O.
VIII_Nun

Z7

G-L~9

__ lrn~~>_ __

D

C
Jll~..Jll3~Y_~ __

8- ,M__ Ylf,LD<5> - - - G- _AL __"'~.!L°<6_>- - -

!--

0.-

B

o

____._

_.AL..'lt!E_P~2? _ __

s 'r-

!

VIII_IMeLII
YHI_IMDAT

__

_~J_V.m:_o~>:

G--

(~

Zl

I

I

!

.. ~----

D

Pi

VALUE=THRW

!J_Z1

G-

c

_ _ _ _ _ _ _ _ _ _ _ _ _ _ • __________ _

0fI1 BHI:tU: :UIi

r:

YMI_'2Ac12 •. 2b "-

V::i::~~!!,: ~!:

._. 'y"~~J~c.!..I~1VHI_'2CcJJ .. Jb _
VHI_P2Cc2t •. t1~ LVIII.Plccll,
VKt_.JCcl •• 1> ~
- VIIE_PiD"J. :-JS .....
YHI_PJDcU .. Il> ~
VNI_PZOcU .... ~
VM!_P2~' •. 1> ~

4

.t. ;....

DESIGNER:
Hon Apr

r-

VHt_piicll: ,""12; ....
YHI_,21cILI.2>

FIJ\T_DAAwlIio.

rs-n~~51 l-[~~l I~~
U_. \~~~~)} :~: '",', _-~I

ABBREV=VME_Pl_CONN

APR/2S/9S Manual

Ll:

vME_Pl_COIm_60. LOOIC. L 1

INSTANTIATION: tCPU5V VME_PCCOlml4PI
----~-~----------

,::Q~~tIJ:ID"::

) 08,55: 27 1995

c

COMPUTERS

VME_Pi_CONN

SHEET
40
OF
94

REV.
0.2

B

A- - - - -

-.. :--] ..

MVME2

-~~~~~.
\IlIB Pdt

VlCB_D

z ._~J__ ~J!.!L~·!/1U~_O.m1
0--'
0---

!

!

o
\IlI E A

L
t:

I

OO

2

I

VIII.DTACK
VlCI.81M

~

VIIB.",,"",Y

~

,
:

l....1_IRO<1. .1.

o

GIll>

Zl1 SRR D!.B.A.£OIm

0

0.1l>

G-

....Al1...JLBR OSR 8..£OIm

0

OND

.b.~_!!.~I_P~~.>_

G- _M......§.£.1!.W!~1~_
G-- _~£lIl.Jl_p_.__
lOG-

A!~D_~ __

YHE RETA.1

o

G __ ~!!L..RXC

" COIm

b

zll....J!~..£.otm

G.-

o

I

G.-

i

za9 S!ULDS~_£.OIm

VH!!~.

100-- ..-£J..L!,!CJIL - - -

811

VHE ,,<31>

G._- __~J_L_!'.~ __
0-- _C..!Ln~a~ ___ _

1)--

_PJ~

'3-...£!L.p.a~1-~l_._

(:'

_t!l.L~~ttT.B-~ __ _

c----

-PH ..t;f.!.I'ffi_Q!!L __

lOG

0

0110

0
G

.sv
814

O_Lm-.!!1!!LOCD A COIm

b

P

I

VHl_IYSCLK

c~~1

!_

GilD

.

. I.

:_~,J~9
'00

CTS OCD_A

UG(;\-_

..lU.L..._...Y.!!lL~

1:_

Cl

_.I'~!;H

___ .

(~

1__ _

~.1_J'.~c;. •.

G--

_.U9_ _ _V_I!~~n?:

20G--'mL-~_~.u?:

20':)- ..J;~_Q._Qtm. __ .____ ...

825

829

o
"~r"
o

0--.

G-__ I_._~TH

P1.Q._G..m'l'B_QM;.'L._.

l2lL9!I.9. _ _ _ _

G--

~u....J1_~:r1U!t:.~.J!.

VME D<~~

JnL_~IW!Y!i.~ll>._.

(~ ..J1ll_VH.JJ!.t!l!

G-·

.P.ll.._YH!U:ly'.~,L4J>..,­

VMB 0<29>

,~

.!>21~V}4U.l!S...:!'_H~~_

_. .!;.t!I._QlIJL _ _

VMB 0<29>

VMB

D<10~

G ·.. ·I~E!LTXD

VMB_D

1

0.1l>

o

.IV

0-

B

ClO

2

_JHJL£.m!1'!L~!.lR... .• __ _

t:;t- __ !;>U_C.£JrrB_!!t.!:;T_J.t! ..
2 0 0--

._C;_~_.Y_I?TII..B!'&J.

YHLQ~~~
VHE 0<25>

._p.J.~ .. c;p.p1'Il._!'~ - - .. _
___IHLGEtIT!LI\..f__ .. _ ..

~~l .. 9I.lP_ _ _ _

8-

G.1l>

.. t;WT.Il._I!.<.l>__ _

(;._. _Q.IJ •.!;.mJ'U!t!1' ... __

G ... _._C19_.r.~~.1.I! .. __ ._
0-- SU _.I;:T.Il_1'9!,!__ .

G

-. __

,:;>- __ .I>!LJ:~!~"p...:!'!:,___ _

u0'.-

_..l!.1~_HE D<2Q?

VH!LQ..ill?:

_~~ __~!ll!~!:t_D.~~

10':' .... 1>!«1-.-£~1.:Il."~.~~__ ._ ....

___ _

C1Lr.~.l;a~

1

I';' ... _.1?9 __ 3E~TIl._()~~.>___ .
I.:' ...

G _s.lLn

0<19>

G- ...J!1.!l-..

1ITl!-!lrn_"~

__

o

A Cptm

10 0

VIC~'YlUnTO

£!.....!'.~~L_.

J!! L __ ,_----'ll!.!LQ<17>

G- ._827
_~~?...!I!R..TXD

_ l>.l! _. J~~T!L[):< ~,. .
(._. _.I)] ....Cj:.NTltJ~~~>...

VHB_~~

2S(

OHD

c~JTJ:LO~">.

_SL_~tw:r_R.-QlC_

59

G
!l23
0-- _Q1_4.

o
0-- 10110
-ID.J.!!.lUlI'B...A...£OIm

8

...

1?5 __ . ~ENTR.-O._._ .. _

VHB..A~n~

o

'§

f

S ';'._ ..

87

821

YMI.IIIl< ••• O.
V1U ...BOIHcl . . 0» .
VME_'IGOUTC t .. 0:.

1,)~ ___WEJI\!S.gp~ -.
..~_ ._!>l __ .S:!lliT~L __ .. __ .

J~ ___Ym:~~.4~

(::' . -1 _~L

_01 ___VME_\l_U!!.~.H_6.~ ..

1_.:\

c1.._t;~.T!I_Qlt..~l~.

0- _.!!!. _ _ _VJf..u.~~~

0-

0
0

S'!!Jt.C1HP~OIm

VIC!...AC'A1L

._~J_ _ ~RY

G-

0--

0-. -Ml OND . _ _~
G _AU_...!!.!!P_ _ _

i

'.:"_j .

o--t- C~__ r~~L. ____ .

Itsv

--p-- ---.. -.-

I D

8-1- ...tl. __nCl.. ---.-

0-. _.!ll. _ _ _YHE

VII!_IAC""'8
VlCB.IACKOUT ,_

VH!_svsrAIL

C I

§
0-

___________L_________

C

s 0- ..M_ _ _V.tl~~<25>

I

VlCE_BBIY
VIC I_BeLlI

31

'3- _A1_ .. ~cs~_Qi~~__

b

:

II

(}

....E..-_~.B-g!lQ_~_~olm

GIll>

0

_M .. _!!~ll.LP_
.. _ _ _ Al-.-J!CSI
.--.~-- ..--..

IJ fllO

11

--P2

_______ ._~ ___ . _
VALU~_1.'HRW

f~..

_!!~!I. __\1!'IJLQl!s~.HJ."__

8.£.OIm

..P.~..2...~~!U!!!!l.< 14~~_

SBB-RXD 8 COIm

10G-~1-g!L-VME..!!!!S.~.H~>-

Cll RTS OO'R 8

(":\

QL~TS OC~_

3

_.!>.1..1~VM~-!!US<146>

t~.-. __ I>.~L_YH~_IW...s...:!'H1~_

C

D

:Ili i
4

~I'II
~I

4

, -~-J~s

DESIGNER:
Hon Apr

~C~lt~II·C
~.- tE

FLJ\T_DRAWIIIO: VHE_P2_COlm_61, LOGIC .1.1

,.<~::::.:.... J".

INSTI\IITIATION: ICPU5V VME_P2_COllNllPI
-------··---J\---·----··--·----·l~---·-------B·--·-·

3 09155,10 1995

c

COMPUTERS

·.PMWJmt:

ABBREV=VME_P2_CONN

APR/25/95 Manual

VME_P2_CONN

SHEET
41

OF
94

REV.
0.2

r

A
FROM CPU

!

ARB

______________

L. ______. __
c _ _ ._________ _

(41,un;p,;p;t fJQtsljQ9.1.{orpl~.I.o,; flt\L~J;Z;Z.t,l,q7;y MP<"~;L MPJ.fii;,yTdWi!'*~mbr8Mp~'~;y I\1

MP<4'>jY

KI\:S<,'i

!

I

-A?!~~;;-,~:'~;;-ARR i

;_ADA~:;;-,~.~~;;~R:

I _HBH_ARMY-BUS

! <4t' . . 0»

MABUSADDR_l

-4 HABUSADDR_]

ARB

CON<499

0>\1

I

1

HABUSADDR_O

MABUS_RIIS
HABUS_CAS
MABUS_DB _
MABUS_WR .
.IABUS.,.D~'I'A

.0.

j ~~:~:~gg:t~

HABUSADDlLO

I.

c""

TO CONNECTOR
AND ONBOARD RAM
MEM

_HEH_l\RAAY_BUS
I

I-

::~:~gg::~ C

1

i

$177P$Y<16> :_MAU<355 .• 348> :U_RAS<7 •• 0>

HABUS_RIIS
HABUS_CAS
....; HABUS_OE
. HABUS_WR
....--! HABUS_DATA
I

M

l---1

isR!
18KKI

1

RK I

~~ 1

8~

OK

2

~I

2

II

-;L

-PiA

8~
8~

~

II
OK
OK

~~
sR
OK

3

>

8~
8~

,

10K 14CID11 1

\\

HI!K"Pd>

10K 14c:::!!!:!J 15

\

H!II Pd>

10K '40ml-..!.L..-\-------·-~-----.
<0>·

01<
01<

3

.~~~-------------------

>

8~

j~

101<
101<

isR

1 ~~
8~

4

-

4

18K

t

o~
OK

DESIGNER:

OK

Hon Apr

FLAT_DRAWIIIO. HEH.-ARAAY_COlm_JO. LOOre. t.1

IIISTIINTIATION:

-------..

~-

(CPUSV HEH_AARIIY_CONN71PI

A

------~---.,jr-------.

----13-

-----·-·--·-c -1

SK

3 OB. 54 .49 1995

fO~[IE
COMPUTERS

._~Mw.nt(,1_

ABBREV=MEM-ARRAY_CONN
APR/25/95 Manual

SHEET
42
OF

94

MEM_ARRAY_CONN REV.
0.2

A

I. __ ._..___.__.____._.~R ......_____._..__ ._.. __ .,

c

B

CPl7

l
:l~:nl~·: :;~=~::iui;:~:~
.._1'_M.~~a~

1

,"-...
;. ..~.o_w
tl-·-:·

-I·I-1-··
-+.... t!- .... ...~

'U ···f··-· c.

... !"--_ _ ..
~~k

--

~

~
r~t!
~rn'-'
AU

0-'
JO 0

'X20

,_
_

2

If

... §i
-m-

'Ff -0<5">

!

~_

JO

CON

:ll~ ~

.A

)0

~.

A

M
MD<

A:

M D<

"

I~

>
>
>

j ~.~
.Al

.

•

Pl03

VALUE=SMDIOBH

1lB1iR
H.D<15>

nw

uti

.-

<
<

IH€~

.... 1.1_=-___ ~<7>

~

?=~i-=Hr-=-·H-----··~RH3~

I+--!U-+-~

L4.~

J!t:;~.Jl3n~ ~.~~?

·-·-T·AI1--~t·----- ~Jj~

"t1jll-It=:=Jl=!un
~-::~=~it-.-=~-.---H-R~~

~
~~

I~--t "~,,-I'+----

-'..

CP~p

10

N_B~~~

M

I----·JI::M~*

.~
J.l.f

4:
5>

~

::1\<1>

)RM

f-~~.~t4tr-----·~j~

20

441:1>

~

o--t--7~t-~

M_D<51:ii

I'I_U<:> 1:1 >
",":"D<59 >
20

tLD
C'LU

-0
.~

r--:-I=-'~
.-..
-.-~--< ">

! . 'ADAPT oiWi cODE'!.

-

PRAM COPE BUS \ I
.

4

I

'.

I

.HEHJJU\1IY _BUS

I

n'

I -

100,... ;;,.",.. ,;;'

i

.1U?~t1}:>

;~=;c~~::O~~_lIcI' L -

_~

~=lit:::=:
~
_~-I.--O

··REmF=>:

MEM P<4>

.~

)

< >

0-

0-

lO~·I-'-·-""-··

10

8<1>

HEM _1'<5>
HEM P<6>
.!m!'UL~??

CON

DIWI CODI...•• O. l - - - _
DIWI:CODUcl' r-----~
DIWI.COD!JocO. !
_.-------.S~
DIWI_COO!.LOCcl> I-

IMOD~_~.~

OM.M_COOI_LOCcO»o ~_

HABUSADDR..l ~

=:~~~g:=f i:::
HABUSADDR_O.
~~:~:_~:

HC'U HEM A

r,;; NC

MEM P<7
\~~ MEM P<3

./..

4> 'M 0<63
O>jM 0<31

DESIGNER:

32>
0>

Hon Apr

SI<

1 09:56.21 1995

FO?[[~r~
'~>~---J tC:

(CPU5V DRH_cotm22PI

A

4

6$RAS< 6 > : U_RAS< 5 > : P_RAS<4 > : U_RAS< 3> : P_RAS< 2 > : U_RAS< 1> : P_RAS< 0>

FLAT_DRAWING, OIlM_COIIN_l1. LOOIC .1.1
INSTANTIATION,

milu-~¥-:>~E ~Y--·""--~·O-h )
--e
)
____
--

3

M D<60>

·C
.~

, . " .. 0.

-ll-*;];~

>
>

M.D
D«20>
>
'M:'1r<21>
H..D<22>
H"::'U<2:J>

3

~

1

2

C:J

VALUE=SMDIOBH

0-··

o

N°i,~~O~~~: Rv~E~~IrfN~~TH

P102

MODA60
o

OR
2 2...
V'

M D< >

•.:t

~

-

'M"ll <4">

11:1:

o

~

lFBi~:>

- f l L M -n

~._.

N. _... ___ ...__ ..J1::jfmt-A<~>

(\----f--

P-4

'Ff 0<1'>

_

10.:r-• .

)

....~ _ _ • _ _ _ _ J.-.+.,.~=t~~10

--.---.---8:8AS:'!O~

---If'-'-

--·-------~c--··

COMPUTERS

_PMW..J.N9.._
ABBREV=PRM_CONN
APR/25/95 Manual

DRM_CONN

SHEET
43

OF
94

REV.
0.2

,..---_._----------------------_._--

B

'

D

.. -----.--.~~-.---.--

;~ADAPTjIEM~ArtR:

FROM CPU

I_H;;~::::~

MEM ARB CONN<499. 0>\1

~_ADAPT_MEM_ARR:
_KIlH_IIRMY_BUS:

! -c4", ,OJ>

:~~~~gg:-~

c

HABUSAOOR::O :

:~:~~:~: :
~:~::::

r-

NC ; U MEM A< 11 . 0>

15>

2

.... KABUSADDR_1
.., HARUSIIOOR_2
..J HABUSAOOR_l
! HABUSAOOR_O

:~~i~i:~S

NC ; B MEM A< 11. 0>

ME iHOOB~ ~ : :8~

DC'

NC ; U WE

HIIBUS-:-DATA ,!

RooM·ORIIH
RooMcORIIH
RooK-ORIIH
RooK-ORIIH
RooH-ORIIH
RooK·ORIIH
RooK-ORIIH
RooK-ORIIH
RooK·ORIIH
RooK-ORIIH
ROOK·DRIIH

MEM 0 DBM<499. 0>\1

-c4", .0,.

HIIBUSIIOOR_1 ....

1

TO DRAM

.... " .. ~H".Pl\'H.lln:

,

,

(Sf!;i.I:;~:

r'

;_ADAPT_MEM_ARR,
.

OOOH._

II If!K Acll?_

NC 'B

11 >

NC'

MEM

A< 11 •• 0>

~

~:<~>
M

(8+\6'I:;

12> IN"," r:sJ

IU'UIISlLADAPT_H!H....AM$lIOP$HABUSc2 ... '_HACc

__ ~--"...!lli

.~t'\

.UU-'l.':HfllU)

_HEM_ARRAY_BUS
ct" .. 011>
.... MABUSADDR_l
....; MABUSAODR_2

-1<11>

9t IN 'Hll

0>

..J

MEM 1 DBM<499

0>\1

=~:~~~gg:=~

2

i :~i~i:~S

MABUS_RAS
HABUS_DATA

10>
<15
9>

8>

\0

fill

<7

IIJmL"~kk7>

fill

6>

~

&1

~

3

\0

M

M

<6

5>

<5

RooM.ORIIH

CP45

"~!~,a>

mu:tm~::Ulgf":1

4>

w-m-----.--

~---

4

3

B RAS<1>

-------B·J:Al1;q;-:2>

~4

MIN

MIN_

!T10R
LIUE_WI8f"~§

-tF====-=ilJTh:TI!iL--------------···
.__ ... -- -..-U-------~tR~lOR-=:-.-·:~=--.=-· ..
__ 18

---

__

-·nr . i

.__. ____ . ___ .___ lOR ___ .___ .____ .~=~~

~----

MIN LINE WIDTH=8
MIN:LINE:WIDTH=8
MIN_LINE_WIDTH=B

MIN LINE WIDTH=B
MIN:LINE:WIDTlI=8
MIN_LINE_WIDTH=8

~

_

-.

RRAS

···-"n- CJi

Pi
V

.~·~=--------==---U.i.!!
...~' -=-~t8L
-=-.-=
~:::::..--::r.' "IN-LLm~-~I8t"~H
.

11]

mU:~IN~:~IDTH=8

.

111

r
____

CPU

J72

J44

2>

1>

RooH.ORIIH

10K'4~:L _I:]~l

3>

~

ROOK-DRAM
RooH·ORIIH
RooH-ORIIH

~

t1

---r:JNC;B MEM A<11 .0>

DESIGNER:
Hon Apr

33 Rlf· [fiffi--- UJ }Jt""LMJ;;I'1-»lJf_. -.--. .
ROOK-DRAM
PLAT_DRAWII/G, MEM_AARAY_ORN'-12. LOGIC .1.1
INSTIINTIATION,

-

(CPU5V MIlH_ARRAY _DRAM10PI

--.~--.-----~---------

... -

..

_--_ ..

__ --·---·----B-· --- .------...
.

_PM}'tlN~t

SK

1 08154123 1995

~~'F~"J
f
' ~·:::-ll! Ir~ lE
·-----'-C-'>.

-

..::=-J

COMPUTERS

ABBREV=MEM_ARRAY_DRAM

APR/25/95 Manual

MEM_ARRAY_DRAM

SHEET
44
OF
94

REV,
0.2

A

B-

- -~===---===-J

_ _ .__.

c

1

1

JI00

18() I/O
H8
I/O

2

i

TSOP

~6
-

.

2

I~g:t~ A:UJ=-----·~~-~Y'

!!n ~~l~M

DRAMSPEZ
SPEED=%SPEED
3

3

EXPR~(CHIP_TYPE~DRAM4M4R4)

4

4
DESIGNER:
Hon Apr

PLAT_DRAWING 1 DIW-I_CHIP_61. LOGIC _8.1
INSTANTIATION:

(CPUSV DRH7SP DlWCCHIP]PI

------·--·------A------··~-

);:lRAWJ.t-JG..

IV

3 08156132 1995

[~~I I[~~
I~~R'
~-:
~
f
---------------a----------------T--- -----C--

ABBREV=DRAM_CHIP

APR/25/95 Manual

_:J ___"I

COMPUTERS

SHEET
45

OF
94

REV.

DRAM_CHIP

0.2

---_. A

_ _ _ _ .... _.

_ _ _ _ _ _ _ _ _ _~.~ _ _ _ _ _ _ _ _ _ _ _ _

. __ . . _._L .. ______ •. _ _ _ _ _ _ _ _ _ _ _ _ _ _ . _ _ . ___________ L

--_ ..--.--.- ...

_._-_ .....D-._---------------- ----_._-_.

1

1

Jl01

1B

2

<)

H8

~

I/O i
I/O 0

2

TSOP

~_

a.J(1

:m~,aM

DRAMSPEZ
SPEED .. fisPEED
3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:
Hon Apr

ffi~~[lE

FI....T_ORAWINO, 0IW4_CHIP_69. LOGIC. 9.1
INSTAtITIATION.

ICPU5V DRH75PIl DIW4_CHIP1PI

-----..---- ··-----A---------r-- .. _ . . ---'--8----·----·--·_-

IV

3 08.56,04 1995

c

COMPUTERS

__QMWU1~L

ABBREV=DRAM_CHIP

APR/25/95 Manual

SHEET
46

OF
94

REV.

DRAM_CHIP

0.2

A

B

_____________________

~

__

~

_ _ .l_ _ _ _ _ _ _ _ _ ..

________

L_~

___ . _ _ _ _ _ _

o

1

1

Jl02

18

2

t')

I/O
I/O
I/O
I/O

i
2

TSOP

G ~g-v'

~1(] ~~tAM

DRAMSPEZ
S~~u"J;'IJ=!D

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

tl
DESIGNER:
Mon Apr

FLAT_DRAWING. DRAM_CHIP _11. LOGIC. 8.1
ltISTIINTIATION. ICPU5V DRH15PI2 DRMCCHIPlp)

----------~-F~-.---

------·. --·B-----------------·----~I--- . ---·-C---I

IV

.PIV\WXNG..

1 08. S6. OS 1995

[~(JVR:[[:
COMPUTERS

ABBREV=DRAM_CHIP

SHEET
47

OF
APR/25/95 Manual

I

DRAM CHIP

94

REV.
0.2

A

_ _ _ _ _ _ _ _ _-1

_ _ _ _ _ _ _ __

D

1

1
Jl03

18

2

.')

I

I/O
I/O
I/O
I/O 0

2

TSOP

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:
Hon "pr

ICPU5V ORM15PIJ DlWCCHIPlPI

A

_PJ!AW]:.N~

ABBREV=DRAM_CHIP

f(Jz'j[[E

PLAT_ORAWItIG. OIWCCHIP _78. LOGIC. 8.1
lNSTANTI"TION.

IV

3 08,56.10 1995

'.'

-~B--·--·----·--·--

------c---

._J

COMPUTERS

II.PR/25/95 Manual

[

DRAM_CHIP

SHEET
48

OF
94

REV.
0.2

____________~A___________

B

1

1
JI04

18

o

2

H8

1/0

I

110

2

'i-----L----''-'-'''--'=-'=

TSOP

R OOi''Y'"

UC1 t.mSt~M

DRAMsPEZ
SPEED .. 9iSPEED

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Hon Apr

f;(flVfo~1 I[

F ......T_DMWINO, ORAH_CHIP_19 ,LOGIc, 8.1
INSTANTIATION.

-~._.

(CPUSV DRH7SP14 DMH_CHIP3PI

--··--------~--·--·-·A--·---·--

.. --· .--

J)R}\}'r!J~tG ..

IV

3 09,56.11 1995

B

~.~--~.-.-----------

...

----.----------~-.

C

_,

__ .. :.1

r

COMPUTERS

ABBREV",DRAM_Cln p
APR125/95 Manual

_~

DRAM_CHIP

SHEET

49
OF
94

REV.
0.2

A

B

---------- -- .. -..

~-.---

..

_--------- ----

c

______ ~. __ .__ ~ __ ..__ .

D

--.-- .. -

-~-~-

------

~.--

... _._---

1

1

Ji0S

18

<>

2

I/O ~

.~

I/O 0

_

H8

t •:

-~~=1t~
~

2

TSOP

~~t~M

DRAMSPEZ
SPEED,,\SJ?Ef;D
3

3

EXPR={CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:
Hon Apr

fl
-

FI.1\T_ORAWINO, ORAH_CIIlP _80. LOGIC. 8.1
INSTANTIATION, ICPUSV ORM15PIS ORAH_CHIP1PI

- ···-----------r---------

B

-·--~-c

IV

_PMW.l..NG..

1 08.56,12 1995

-f1~~..'.-=>') [-['::-::1 fEJ
[-~
'~~

J\BBREV=DRAM_CHIP

J\PR/25/95 Manual

SHEET
50

OF
94

",

.':.~

-=-_-:1..=.-:1

COMPUTERS

DRAM_CHIP

REV.
0.2

______A

_ _ _---:-L-.-_ _ _ _ _~B=_____

__._._._. __ _

C

1

1

Jl06

18

o

RAS

2

CAS

~
~

R M§
•

•

8

8f
R

A-M
~-IU

~:

I/O

I

I/O 0

2

TSOP

~~

~ >~

I/O
I/O

I

U

RAS 4M

WR_1M

DRAMSPEZ
S\rE,5?uE'"sltfID

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Hon Apr

ABBREV=DRAM_CHIP

APR/25/95 Manual

:J

ICPU5V DRM15PU DRAH_CIIIP3PI

A

..Q.IY\Wl.NY.

f~~"I[I[~
r \\~r . _.. _L

PLAT_DRAWING' DRAtCCIIIP_81. LOOIC. 8.1
INSTANTIATION,

IV

3 08,56.13 1995

'--Y--"" - - - -

---

-----= .-

1-

~---------c--

COMPUTERS

DRAM_CHIP

SHEET
51

OF
94

REV.
0.2

A

B

._. _______ ..1. __ •___ .____

D

__ _ .• _.1 ___ ._. __ ...

1

1

Jl07

I:RU~
<0>
.

2

18

$:] ~ftS

--

()

RAS

I/O
I/O
I/O
I/O

3
2
1
0

2

TSOP

OE

!

... "'-==it ~:Inn
tim
8811 ~:
A

M

:.m~l'aM

DRAM
3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
"on Apr

fLIIT_DRI\WUIOI DRAH_CllIP _82. LOOIC. 8.1
JIISTAtITJI'ITJONI

~.[~r··, ".,
~lf~r[E

ABBREV=DRAH_CHIP
APR/25/95 Manual

--=

\CPUSV DRM15PI1 DIWCCHIPJPI

------1\------

__QRf.\W.UIG. .

IV

J 09:56: 14 1995

--·--·--·-----------B--·~-----·

--

·------c--

COMPUTERS

SHEET
52

OF
94

REV.

DRAM_CHIP

0.2

._ _ _ _ A

....___ .__ L_____.______ ~

B

_I

1

1
Jl08

1B

<>

2

I/O
H8

~ •

I/O

If: --:
•

__

2

TSOP

a IXU~"Y""

!!trt

Ms,AM

DRAMsPEZ
s~mr:..sIJfD

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:
Hon Apr

(CPU5V DRH75P19 DRAM_CHIPlPI

A

.-.P-MWIm;..

f(-rJrF' [' [[:~

I't.AT_DRAWltlO, DRAM_CHIP_e). LOGIC. 8.1
INSTANTIATION,

IV

1 09,56,19 1995

,_~...,

·--l--~.-

B·

----····-·---1--

c

__1

COMPUTERS

ABBREV=DRAM_CHIP

APR/25/95 Manual

._J

DRAM CHIP

SHEET
53

OF
94

IREV.
0.2

D

C

1

1
JI09

18
t.)

2

I/O
I/O
I/O

~

.
·1=.A~·-·--·--nm<
~~.
.
_1__
2
• --1-_._____
< L

2

TSOP

p

om".

------!Un :.m:t~M

DRAMSPEZ
s\rE!'t..~..sI..f!D

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Hon Apr

~J~~~~I
[[ [r~
IJ \~'~k
~ -.-~ =

FLAT_DRAWI/la. DRAM_CHIP_e4. LOGIC. 0.1
JIISTAIITIATION, !CPUSV DRH7SP19 DRAM_CHIP1PI

A

-----------

IV

3 08. S6: 2S 1995

B

--'--

COMPUTERS

_QMW.lNQ_

ABBREV=DRAM_CHIP

APR/2S/95 Manual

SHEET

S4
OF
94

REV.

DRAM_CHIP

0.2

_____ A

1

1
JUO

18

I

21

M§~~~

,.;d ~~
WR
OE

<>

I/O ~
1/0
I/O
I/O 0

TSOP

-1

--~

12

--------

tn
~n
t: n
RAS 4M

WlLtM

DRAMSPEZ
3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:
Hon Apr

fLAT_DAAWINO. DRAH_cHIP_69 _LOOIC _8_1

INSTANTIATION,

IcPUSV DRM75PI10 DRAH_CIIIP1PI

--A----------------l-------------B-------------r---------C--

IV

_JJMWJ~q_

ABBREV=DRAM_CHIP

3 08.54.41 1995

f~TJ~~)rr
.... ,:-:::-.:_ •

~.

__ .:1

COMPUTERS

APR/25/95 Manual

.:==:J

DRAM_CHIP

SHEET
55
OF
94

REV.
0.2

-----

A

___________

B

1 _________ _

________1___________________ =__________________ _

C

1

1

Jill

>
~~

--~~

18

2

o

"JO ~~

13K

~...

I~g

i
.i---L-----!~=

I /0

2

TSOP

WR

"0 os

p

I/O

~:In
~~
A

~~U=J ~:a ~
g OOg~v'"

R

:!O lm~laM

DRAMSPEZ

S\f~uEt,.sIJ!D-

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

11

DESIGNER:
Hon Apr

IV

_PMWIN~lo

J 09154,43 1')95

ff~)'rlE
u ,~':..-j~r ~ ~o

FLAT_DMWlNO, DIWCCHIP_10 _LOGIC.8_1
INSTANTIATION 1 !CPUSV DRK1SPI11 D1WCCHtP)PI

ABBREV=DRJ\M_CHIP

APR/25/95 Manual

- -

--C_

O

COMPUTERS

56
OF
94

REV.

_

------B------------

O

SHEET

DRAM_CHIP

0.2

B

A

_ _. _ _ _ _ _ _ _ _ _ _ ..• _ ... _ •. _..•. _. ______ . _ _ _ ..

__ .•_ _ _ _ ._.--..1

-------.----.-~-

-- -._- ..D
--"---_._--_._.. -. --------_.-.-

1

J112

lB

I/O 3
I/O 2

(;. H8 A
TSOP

2

p

&'In!:.

B~

2

RAS 4M

WR_l"M

DRAMSPEZ
D
SPtffl'uE',!llrff

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Hon Apr

rs-~]=r--:

FLAT_DAAWIIIO, DIWCCHIP_71.LOGIC. 9.1
1I1STIINTIIITIOll, CCPU5V DRM1SPI12 ORAH ..CIIIPJPI
.-.--~--.-

.. -.~~-.---.--.-

-"·-·--B ··---····---····..··-·-·..

-···r .. ---- ·_"C-·-"-

.QMW.1~~..

IV

3 08.54.46 1995

~~:)

~:)

(t~,.lF. L, u:::
r::;-l

COMPUTERS

ABBREV=DRAM_CHIP

APR/25/95 Manual

DRAM_CHIP

SHEET
57
OF
94

REV.
0.2

.-______ .________ ._ A ___ . _ _ _ _~

_______ .__ ~ ________ _

B

C

---------_. -

-

------- ..

~-

.. --- .... -----.- ..

~--.--------.-

1

1

J113

18

HXB

21

dQ ~~
WR
OE

<>

I/O ~
I/O
I/O
I/O ~

'i_2_ _ ..J'J~~

12

TSOP

~JHHI
A_

fY'~tAH

DRAMSPEZ
3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

I}

DESIGNER:
Hon Apr

FLAT._ORAWltIO, ORAH_CIIIP_12. LOGIC. 9.1

JIlSTI\IITIATIOIII

ICPU5V DRK15PIU DRAH_CHIPlPI

-.----.---. -··-------·--A--~------·T-------·----·---B------·--·-------l-----·---C-

IV

3 0111:54:54 1995

IF{]ff~;~: I[ ~::
COMPUTERS

QM~INg ..

ABBREV=DRl\M_CIIIP

APR/25/95 Manual

SHEET
58

OF
94

REV.

DRAM_CHIP

0.2

A

----'------- --~---------~---===-=-].---------------

D

C

1

1

J114

18
<)

2

I

I/O
I/O
I/O
I/O 0

2

TSOP

~...

!'td OOS,~M

DRAMsPEZ
S\f~u"J!ltf!D

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Hon Apr

.PM\i:Ut_G_

IV

r

l 09,54,54 1995

IF(Jll~~~'1
ff
'-:-::-:._ . _. U_ = l'=::l

fLAT_DAAWUlO: DRAM_CHIP_n. LOGIC. 9_1

ltISTMlTIATION, ICPUSV DRM7SPIl4 DIWCCHIPJPI

--------------·_---i3--------------------r----------c---

COMPUTERS

ABBREV=DRAM_CHIP

APR/2S/95 Manual

SHEET
59

OF
94

REV.

DRAM_CHIP

0.2

A

--"~-"---"----.-------~-

B

"---'------~---------~-------

.. __ "_L_. __ ._______________
C _ . __________ "____ '-- _. ___________ .__ ... ___ . _." _"

_~ _____ ._____ . ____ _

1

1

JUS

GJmL-~~a~-I

18

HM~~¥~

21

2td ~~

(>

H8 I
1'0
10 0

+_i!_----.rLJL~!1~_

12

TSOP

WR
OE

--------

I

t:lH
~: n

~t~M

DRAMSPEZ

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Non o\p~

IE

1~~~V~~il,,_~
[- , __ _

FUT_ORAWINO. OJWCCHIP_74. LOOIC.8.1

U \\~U

JNsTIltITIo\TIOIIs (CPU5V ORH75PI15 DMH_CHIP1PI

-.. - - - - - - - - A

_.PMW.:UiQ_

IV

1 08,54,55 1995

-

-·-~---------·-B--------~--r--·-----·---·--C--

COMPUTERS

ABBREV-DRAM_CHIP

APR/25/95 Manual

SHEET
60
OF
94

REV.

DRAM_CHIP

0.2

B

D

C

1

1
J116

1B

<)

2

I/O 3
I/O 2
I/O 1
I/O 0

2

TSOP

OO~taM

DRAMSPEZ
SPEED .. \SPEED
3

3

EXPR={CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Hon Apr

f(f11p
[
.~~~/ ~

FLAT_DRAWJlIO. DRAM_CHIP_1S. LOOIC. 8.1
INSTAIITIATION.

U \

(CPU5V DRM75PIl6 DRAM_CHIP)P'

------·---~-A--

B

---------

C-~

..

_.PJv~.w;um

IV

3 08: 54 I 56 1995

If::~

COMPUTERS

ABBREV=DRAM_CHIP

APR/25/95 Manual

_::::1

DRAM_CHIP

SHEET
61

OF
94

REV.
0.2

c

B

A

.L_~_ _ _ _ _

___

~ __ .~_ _ _ .~_ _• __ • _ _ _ _ _

1

1

J1l7

18

o

2

I/O
I/O
I/O
I/O

3
2
1
0

2

TSOP

~ OOM~Y'

un If'~l~M

DRAMSPEZ
StEr5?u=E'..SlrffD
3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Hon IIpr

PMW~N{t_

[[

RJw:~~ lL:

PLAT_ORAWINQ. OIVJLCHIP_16. LOGIC. 8.1
INSTANTIATION. (CPUSV DRH1SPI11 D1WLCHIP)PI
--.-------~-------.~-T-~-----~-----

IV

3 08.55.00 1995

c

COMPUTERS

ABBREV=DRAM_CHIP

APR/25/95 Manual

DRAM_CHIP

SHEET
62
OF
94

REV.
0.2

- - - -A

B

________ 6

_ _ _ _ _ _ _ _ _ _ _ _- _ _ _ _

C

-----------.- ------------

__OC ____

--

--- ------- ---

_I

'-.

1

1

J200

18

o

2

B8
I/O

J/O

i
2

TSOP

~~t~H

DRAMSPEZ
S\F~u"E'!IJfD

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Hon Apr

R:]~R}:[[E

PLI\T _DRAWING I DRAH_CtU P_31 _LOGIC _8 • 1
INSTAtITIATION, CCPUSV DRM21P DRAICCHIP1PI

----1;:-------------- --

IV

1 08: 56: 24 1995

B

----------- C - -

COMPUTERS

_QMW1RQ_

ABBREV=DRAM_CIH P

APR/25/95 Manual

DRAM_CHIP

SHEET
63

OF
94

REV.
0.2

B

1

1
J201

1B

o

2

I/O
I/O ~
I/O
I/O 0

2

TSOP

RAS 4H

WR_1"H

DRAMSPEZ
SPEED .. \SPEED ---

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:
Mon Apr

~9r:]I~:i' [[ If:

FLAT_ORAWIIIO. DlWCCHIP_34 . LOGIC. 8.1
INSTANTIATION: (CPU5V DRH21PIl DIWCCHIP1PI

------------·----13----------------

IV

3 09.55.53 1995

c

COMPUTERS

PMwum

ABBREV=DRMCCUIP

APR/25/95 Manual

DRAM_CH-IP

SHEET
64

OF
94

REV.
0.2

A

B
-----_._---_.

_. ________ . _ _ 1 _ _ _ _ _ _ _ _ _ _ _~ ______-_ _ _ _ _ _ _ _ _ _ _ _ _ _ • _ _ 1. _ _ _ . ____ .. _______ .___

I? ________________ ..

1

1

J202

18

~R~~~

21

2~Q §~

,)

I

I/O
I/O
I/O
I/O 0

'i-L-_M~-

/2

TSOP

OE

--------

I

l-J=
~: n

A: M 0

UA~t~M

DRAMSPEZ
3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Hon Apr

FLAT_DRAwn/o, DRAH_CIIIP_41. LOGIC. 8.1
ItlSTl\NTIATIOtl.

ICPUSV DRH21PU DRAH_CHIP1PI

-----.~---.-

B

--c-

IV

l 08,55.54 1995

~~~)[I~
~ \\:_-ij~ ~ lC
,---

COMPUTERS

_J!MWI_~~

ABBREV.,DRAM_CHIP

APR/25/95 Manual

DRAM_CHIP

SHEET
65

OF
94

REV.
0.2

__________ L____________________

B

- - -A

L _

_ _ _ _ _ _ _ _ . __ . _ _ _

D ____________ .

1

1
J203

18

2

m~r~~

~ y~

.~,,~
~' ... "':

RAS

;i§ ~~S
OE

o

H§l

I/O 0

2

TSOP

-~ ~III
!10 la~tAM

DRAMSPEZ
SPEEO .. tiSPEEO
3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Hon Apr

FLAT_DRlIWltIO. DAAH_CIIlP_44. LOGIC. 8.1
INSTANTIATION. (CPU5V DRH21PIl DAAH_CHIPlPI

A

--·-------------13--------- ·-----T-·----C-

IV

J>MWltt..9.

r Ir~lb

3 08.55.55 1995

I~Tf~'"
I ~~111

-~ u. =

COMPUTERS

ABBREV=DRAM_CHIP

APR/25/95 Manual

DRAM_CHIP

SHEET
66

OF
94

REV.
0.2

A

________________ L_. _______ ._______ C

B

1

1

J204

1B

I.)

2

I/O
I/O
I/O
I/O

i.

.

•
___
< >
·8~--=lt=HU~
• L~6?"

2

TSOP

~~l~M

DRAMSPEZ
s\F~u·J..sll!D

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Mon Apr

rOR~'r~
'==_ /
~ IL::J ~-~

FLAT_DRAWnIG. DRAM_CHIP _45. LOOIC. 8.1
JtISTAtITIATIOII. ICPUSV DRM21PU DRAM_CHIPlPI

A

IV

3 08:55:56 1995

B

---~----

-

C

COMPUTERS

_.~MWJ.NCJ._

ABBREV==ORAM_CHIP

APR/25/95 Manual

SHEET
67

OF
94

REV.

DRAM~CHIP

0.2

B

D
------------------

C

1

1
.1205

I/O
18

o

2

-

U8

I/O

i .:HL.-----mm=
.p=-.:.:.-- --

<

>

2

TSOP

R GQg'~'

~ ~tAM

DRAMSPEZ
Sl~J}5'Ou..:!It_flD

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Hon Apr

~1S\--

W=-tJ~C;'?) [[

FLAT_DRAWING. DRAICCHIP_46. LOGIC _8.1
INSTANT I ATlOII,

ICPUSV Drut21PI5 DRAH_CHIP3PI

A

_PJ~h,WIN9_

IV

1 011,55,57 1995

-'---13------------------'----

C

--I

t

1":':'-'

COMPUTERS

J\BBREV=DRAM_CHIP

J\PR/25/95 Manual

DRAM_CHIP

SHEET
68
OF
94

REV.
0.2

, - - -_ _ _ _ _ _ ~_ _ ~_-~_____ ~ _______--------.l _ _ _ _ _ _ _ _ _ _ _ _ _~_ _ _ _

------- - _- ~~.f.. ____ ~ _____________

.I

1

1
J206

18

o

2

I/O
I/O
I/O
I/O

3 .J_~'
1'1 _u-'''' "
2
' ~-~---~~

1
0

2

TSOP

lm~~~M

DRAMSPEZ
SPf;ED .. lsPEf;D
3

3

EXPR={CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:
Mon Apr

IV

3 00156:01 1995

[~~~[[E

FLAT_DRAWING. DRlIH_CHIP_47. LOGIC. 8.1

INSTTillTIr.TION, (CPUSV DRM21PI6 DIW'-CHIP1P)

------- ------13----------

C

COMPUTERS

_QM.W1N.G_

ABBREV=DRAM_CHIP
APR/25/95 Manual

DRAM_CHIP

SHEET
69
OF

94

REV.
0.2

A

1________<::- -

B_

.l ________ . _. ___~ ____ ..______ _

11

1

J207

_II

I

,

WI!
~

MEM A

R~R t~aW=~

lB

RAS

21

CAS

WR
OE

I)

TSOP

--------

~IU

~ :~ -~ I~n~

fl8
I/O.
I/O 0 .

2

< ~
<_>_

12

-------1/0_2=
1/0_

~.1
•

S2

81

H_D

~:tAM

DRAMSPEZ]

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Non Apr

FLAT_DAAWIIIO' DRIIH_CIIIP_48. LOGIC. 0.1
IIISTAtITJATION,

ICPU5V DRH21PI7 DAAICCHIPlP)

'---·--------A-----~-l-----·--·----B------·-------T-·-·----·C-

IV

3 08,56,01 1995

~~Jp:~i: I[ Ie-:
COMPUTERS

J;mp.~m~Q_

ABBREV=DRAM_CltIP
APR/25/95 Manual

SHEET
70

OF
94

REV.

DRAM CHIP

0.2

B

A
-----------------------

D ------ ..

C

-------------------.------~--

---.-.~

..

-

1

1

J20B

18

R-Hru~

21

21Q M~
WR

<>

I/O
I/O
I/O

i

.t-l _ _MEM

1'<0>_

12

TSOP

OE
--------

A-naa
~:
~:

lm~t~M

DRAMSPEZ

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Mon Apr

f(f:[[[E

FLAT_DRJ\WItIO. DRJ\JCCHIP_49. LOGIC. 8.1
JlISTANTIATION. ICPU5V DRH21P18 DIWLCHJPJPI

A

-------

IV

J 08: 56. 02 1995

B

-------~-----.------

c

COMPUTERS

__ P.MW.lNQ _
ABBREV=DRAM_CHIP
APR/25/95 Manual

SHEET
71

OF
94

REV.

DRAM_CHIP

0.2

A

.1

l__________ ._____Q. __________ _

c

B

1

1

J209

lB

<>

2

i .+_-_

I/O
I/O
'l±=----~"~"
1/0
.
< >I/O.
< >-

2

TSOP

A_jM

t

!!!.!F!~~!
DRAMSPEZ
S~J!Du:;;lrfjD

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4

DESIGNER: IV
Hon Apr

__ ILRAWltiG_

3 08,56,0) 1995

r-(tJr t J::
~I'-<-'

2

FLAT_DRAWltIO, D1WCCIIlP_50. LOGIC. 8.1
JNSTANTII\TJOII:

Ir-.:.
.!

APR/25/95 Manual

!

CCPU5V DIU421PIO IJRAH_CIIJP1PI

-~-----p:------------

.-~:::J

ABBREV=DRAH_CHIP

~---

B

C

COMPUTERS

DRAM_CHIP

SHEET
72

OF
94

REV.
0.2

B

A._----

--

c

---.--~-------

------

1

1

J210

>

0:>---9

I/O

18
(>

2

~

H8
t
I/O 0

2

TSOP

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:
Hon Apr

ABBREV=DRAM_CHIP

t'-~T~=--:-)) ~-=:-J [[-::::1___

f -,~~.::::::[
_::1

FLAT_DRAWING, OIWCCHIP_15. LOGIC. 8.1
INSTANTIATION. (CPU5V DRM21PIl0 DRAH_CHIP3PI

A

__DMt'l.:t.N_G_

IV

1 08154127 1995

B

---------------,.-----

C

j~_
I

-"

--:.

::-~:1

COMPUTERS

APR/25/95 Manual

SHEET
73

OF
94

I

[

REV.

DRAM_CHIP

0.2

B

A=-_ _ _ _ _ __

D

1

1

J21l

lB

~>
< >

21

21Q ~~
~~

(;>

I

I/O
I/O
I/O
I/O 0

+ L _____ tJ.Jl<4U>_.

12

TSOP

--------

~- ~
~n
~: u

4M
lHtR_sI M

DRAMSPEZ
3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Mon Apr

.P.~WIN<;t

IV

1 08,54,30 1995

I~l~' [[~I I~[[~~~

fLAT_DRAwn/o, DRAH_CIUP_J6. LOOIC. 8.1

U \~JJ~

INSTANTIATIONI (CPU5V DRK21Plll DIWCCHIP3PI

·--.-·----B---·----··--·--·-r------·----c-·

~
lL
COMPUTERS

ABBREV=DRAM_CItIP

APR/25/95 Manual

_:::1

DRAM_CHIP

SHEET

14
OF
94

REV.
0.2

A; _ _ _ _ _ _

B

C

1

1

J212

I/O

18

2

I)

I~g
/0

i .:tr==~U~
l~---=~-

------

2

TSOP

A_jH j

ti![J[j i~IH ~
~:"{AH

DRAMSPEZ
S~J5?u:..slJfD

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4

DESIGNER: IV
Hon Apr

lLRAW.nm._

3 09,54.35 199!i

I~fi;:?)
lic ~~
~ \;~J-}) ~ ~-.- 11_1
ee

APR/25/95 Manual

SHEET
75
OF
94

•

FLAT_DRAWIt/G. DRAICCIIIP_37 _LOGIC. 8.1

INSTANTIATION. (CPU5V DRK21PIl2 DRIIH_CHIPlPI
-----~---·---A~------'

ABBREV=DRAM_CHIP

B-

COMPUTERS

REV.

DRAM_CHIP

0.2

r-------

1___

A

B

._. __ .____ ._ ..

J_ . ___ .

.:.~l

-C

___ ._. _____ ._____ _____ p___________ .__ ._____..__ .....

1

1

J213

BI ~EH
A<11>
M~n I~ 11>
r

Po

0:-

~
18

N-f.wg.~----dn ~~

2

()

.....

___

~~ i:t~ t
< >

RAS
R._EWE

...l__ _-------"LP< 4 11_>

2

TSOP

If--J:ma-----..-l
.l----sI----lr1J«B~

1/0 4H 1.t....n._
I/0:4H 0

RAS 4M
WR_~M

DRAMSPEZl
S~r5?U:..s!J!fD

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Hon Apr

~r-f~ ~~?) [-::1 I[~
IJ \\·,~~::-u·~r~ "~ .___ __

FLAT_DRAWINO. DRAM_CIIIP_18. LOGIC. 9,1

INSTANtII'\TION: (CPU5V DRH21PI13 DRAMSHIP]PI

A

--··----------------1-----·--·--

IV

3 09,54.36 1995

B

-----~-I--·~---c-

COMPUTERS

j}M..w.:!:tt~.

ABBREV=DRAH_CHIP

APR/25/95 Manual

DRAM CHIP

SHEET
76

OF
94

REV.
0.2

A

__________ L_. __________ ._. ________ ~ ______ . _______ _

_____

1

1

J214

18

(.>

2

I/O

I~g

i

I/O

2

TSOP

tm~T~M

DRAMSPEZ
SPEED=lsPEED

--

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Hon Apr

ff'~:'
[[ [[::~
~Jl ~=[

PLIIT_DRAWINO. DRIIJoCCHIP_39. LOGIC. 8.1
INSTIIJoITIATION. ICPU5V DRH21PIU DIWCCHIPJPI

--------------

----A---~---

-.--,-- --B ---

------.-

IV

3 08.54.36 1995

c

COMPUTERS

_PM~_nlc:;t

ABBREV=DRAM_CIIIP
APR/25/95 Manual

SHEET
77

OF
94

REV.

DRAM_CHIP

0.2

A

B

C

--.--- ---------

o

1

1
J215

fl,

18

2

o

RAS

CAS

i

I/O

2

TSOP

~~

~Xf

B8

I/O

t-~n

XU II~IH

i
!

W'~iJAM

DRAMSPEZ
S~.att=J..sl~!D

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:
Hon Apr

FLAT_DRAWING: DIWCCHIP_40.LOGIC.8.1
INSTANTIATION. ICPUSV OllH21PIl5 DIWCCIIlP3P,

--------A--·

----------B---------------T-------C----

IV

J 09.54.31 1995

IFO~[lE
COMPUTERS

..J>.E)\JlIN~_

ABBREV=DRAM_CHIP
APR/25/95 Manual

DRAM_CHIP

SHEET
78

OF
94

REV.
0.2

B

A

_ _ _ _ _ _ _ _ _ _ _ L. _____________________________

. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . __ l __ .___

-=- ______ ._____ .___________ _

1

1

J216

:>

20

RAS

2

CAS

WR

OE

n~

fln~

,

,

...

~.L...

18
<)

I/O

I~g

~

2

I/O

TSOP

~-l~ i

11H~:
~i
A: M 0
Aft

HgJ~ ~ ''\-¥.----- ~Itt--

Ud~:t~M

DRAMSPEZ
SPEED"%SPEED
3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Hon Apr

ABBREV=DRAM_CHIP

---------B----------~---

c

COMPUTERS

SHEE1'
79

OF
APR/25/95 Manual

.,

(CPU5V DRM21PI16 DRAH_CHIP1PI

---------A=----- ---------

.J~MWl.NJt

ftJr~:;J
f[= [:,~.::...-I/I

FLAT_DRAWING. DRI'JCCIIIP_41 _,,oole. 9.1

INSTANTIATION.

IV

1 09: 54.19 1995

DRAM_CHIP

94

REV.
0.2

D

A

1

1

J217

I/O ~

18

()

2

H8
t
I/O 0

2

TSOP

~p

!!ICJ W'~,AM

DRAMSPEZ
S~~uJ..slr.ffD

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:
Hon Apr

FLAT_DRAWINO, DRAH_CIUP_42 • LOGIC • 8.1
I1ISTAtITIATION,

ICPU5V DRH21PIl7 DRAH_CIIIPlPI

---------A-----------

-------13------------

------~~

_·c---

_R.MW.lJlG__

IV

l 09,54, J9 1995

\\J~ ~ l!_ _ l[
fI~w;~)r~

ABBREV=DRA~'-CHIP

APR/25/95 Manual

80

OF
94

REV.

:J

COMPUTERS

SHEET

DRAM_CHIP

0.2

Y.lJ?.J~CO.mL_~_.~_
HIN_LINR_WIIyrH.25

-·-:-------I~~Rlll
~~
-. -n~f,=
NA
_
{2'NA

33U
CE10D 16V TA

:h

.--~---.

T

oT"

1
CHANGE FILE PSTXNET.DAT:

NET_PHYSICAL_T~b

J20

_1_ 1100.

NA_RM2T
( 1 OU,:2
..:'~SV:ALU)

NA

ALTERNATE ASSEMBLY

'XX(lOUT

+

t

-- -JiTh--

T-l-fiN'-

1

CEl

c

B

A

[

•

ellAnu~-'

NET_PHYSICAL_TYPE

OR
OR
OR

2

n

POWLVR

VALUBDI.T1085,...JJ>J
SONOBILA-HEATSINK

~
L
±
~
±
;,m *
_

lS4R_1T_120LW4
(NA)

VALUES IN PARANTHESES
ARE VALID FOR LT10BS_3V3

CE9

I CEB

I

c2.L

-rnU_D_16V_TA -rr3U_D_16V_TA

--l~

2 BOR_1T_1206_W4
(OR)

-CRlbn;"_R_ _l !l2UILV3P3IN
-

1:.1:.

HIN_LINB_WIDTH-25

--riOON_20T

12
..rrn~;r-.lItQ.H'.U"'Yf.llfLf-l
-1M
CE
HIN_LIIIB_WIDTH-25

1

Sil·
s
~ _______. __ . T'~------ J------

ASSEMBLY FOR S.lV: N
RJ22R): REMOVE

~lU~I; l7g~lV
=> I (R) .. 15MA

~

+

C

OU_C_16V_TA

C5

100N_20T

.

-li'OON_20T

-I6BOP ··J"6-BOP

ci._

c

]'-OO"::2_0~

__] ••O.

3

HIII_LIIIB_WIIYrH.8

.

-["6'BOP

SK

J 08:55:48 1995

f(J)~:[E
B

1:----

-- .----.. - .... --.. __ .. _______ f.IJNP~

Hon Apr

IIlSTIINTIIITION. (CPU5V POWBR_UNIT62PI

c5

11105

DESIGNER:

PLIIT_ORIIWmG. POWBR_UNIT_62. LOGIC. 1 . 1

2
c2!L

:r-"'--

'1

BLH·411101PT

.=r

IIET_PHYSICIIL_TYP·POWER
HIII_LINB_WIIYrH-25

~GE:-;~'Wffi-:--r--- ~I-------·-- -HiN~Li.ii~Wi~~~P.3

IOU_06V_TA

lW2M --- .. ~ 22R
l2imM-fBIDJro;:- rl

~

cMl_

~.::----

t

3

~

~

CBLl BCBLl 6CB 122 CBL~23~B l~ CBLl SCB l~ ~B 127

~

:!J

,± l
~ l

COMPUTERS

._PMwm9 ..
ABBREV=POWER_UNIT
APR/25/95

Manual

POWER_UNIT

REV.

A

13

1_

__ .__________ '- ______. ._

_c_ _ _ __

••• A _

______

~

__ • _ _ _ _ _

D

_ . _ • • • • • _ _ •• _ _ _ _ • _ _ _ _ _ _ _ • _ _ _ _ _ _ _

1

1

~~~~ .a:
~~~~ ~

(10K)

B4

SAP=NOT_AS

- -· -[r

2

___

G

toOY_U"·f"I.QfIINl

JTAO_INDEX-t

;. ADAPT

" .. _. _ _ _ _ _'ttMl...!Ks"--_ _ __

--('1]

•• _ _ _ _ _ _.JTAO£L_It_ _ _ _ _ _L.IA;·

J-----------

.~!M!_TP.!..'m9~9.~ __ }

..

iii)

__ ,_________....u~_TPLT.!>O~L _ _LLU),

I~

____________________J!!!P_ _ _ _ _ ---~--1.4i.

L_..

_ _ _ _ _ _ _ _ _JTAO I\ST_ _ _ _ _ _ _

-4-_1.

~

TMS
eLK
TDI
TDO

2

~ GOO

;f~\

RST

~

g
....

,:JTAG

I.

lCoy .. fYn· ...\lHl.OO

JTAO_INDEX-JTAO_INDEX

!ADAPT

1-JTAG
1-

3

JTAO_TKS L
JTAO_CLIt-J-

~~:g:~~c__ .__
JTAO~RST.

3

J

0----------.--

4

4
DESIGNER: GP/IV
Hon Apr

INSTANTIATION.

f

--I [-:-':J [[~
_~'
_ _ _/
[,,1

FLAT_DRAWINO. JTAo_tnIlT_61. LOOIC .1.1
ICPUSV JTAO_UNIT51P)

-------------A-----

1 09.55.46 1995

T---·----·---------B

·--------c---

~w.nro=

g~~g:mH~

APR125/95 Manual

SHEET
82
OF
94

.~

,..~.,'

-:-"':.

':::J_::=1

COMPUTERS

JTAG_UNIT

REV.
0.2

c

B

A, - - - - ,

er "j~"T"'-"t'~"l~''T''t''''i ~"j~''j~''.'j''''~1'~i'l,,''~t'''~i~''T'i~t'Li_~t''.:.r.iL~L
'=cJm

1

..~-

-~- -~' -~ ~ ~ ~. ~

~

-=JD-

'~

. . . . ;tm

-~..

lM_1206_W4 lM_1206_W4
_....SlJl1';J,.Jl·-·om!r-· 1.82) .$Hi!R~!~rl

lJm .- ""J;

~

'~~8LTBL~tBL~B~BL1:BL~rB~~BLr~BL~tBL~rLi.TLi~t~Ll~i~~~.l~BLTLi~'~Li.j~Llj_
-~ -~ ~ ~

.' -. '* -. lilm -. -• .
~

~- ~- .~' -~- ~. ~ .~

1

.'.

BL~l~BL~t~B~BT~B~~BLTBTBLTBL:1:BLTBL~BLTLi:1~~B~~B~j~~B~~tL~B~l

lM_1206_W4

~~~~~~~~~~~~~~~~~~~~

lM_1206_W4

( • 21 E~Q_ll'r~! p._ --- I"'l~- -1'2 LEl!OOJ)rl

8L~BLr~BLT8L~~8LT8LTB~CBT8~Ll~BL~B~~Ll~BLTLlTB~I~BL:rLl~B~

~~~~~~~~~~~~~~~~~~~~
8L~CBTBLT8LTBLTBLTB~BL~c~cBTBLTB~BLj2BLT8L~L~L1TB~L~

~~~~~~~~~~~~~~~~~~.~
2

VME_STDBY SEE VME_Pl_CONN
V3P3_VMECONN SEE POWER_UNIT
FILVP5 SEE POWER_UNIT
FILV3P3 SEE POWER_UNIT

C~j~CB~BLTB~B~BLOTBL~C~CTBL~BL~B~BL~BL~B~BTBL~B~B~

~~~~~~~~~~~~~~~~~~~~

~T

PAGE
PAGE
PAGE
PAGE

2

o

CE7
33U_D_16V_TA

NET_PHYSICAL~TYP=POWER

33U D lQV_TA
- - ~__
CE6
+

T

+

MIN_LINE_WIDTH=2

-I.

~

lOU_C_16V_TA

CE[
__
33U D 16V TA
NET_PHYSICAL:TVP=POWE

3

.

I

CE4

L_.

3

J;-"

01

lOU_C_16V_TA

V3P3

sI
t
~

CE3

MIN_LINE_WIDTH=2~

V3P3

NET_PHYSICAL_TYP=POWE~._.J
4

4
DESIGNER:
Hon Apr

f('~~:[[IE

PLAT _DRAWIIIO. DECOUPLINO_64. LOGIC .1.1
INSTANTIATlot.. ICPU5V OECOUPLIN055PI
--'·------1\~-----------l---'·'---·----B----'---

SK

1 00,54.59 1995

. '------. "'-r---------C·--

COMPUTERS

.QMWJNg_

ABBREV=DECOUPLING
APR/2S/95 Manual

DECOUPLING

SHEET
83

OF
94

REV.
0.2

A

.-

___ J ____.

B

_I___~=_=__._.. _==_~J? .___.__________ .

c

J27

10KI~~~-1

i~'"

CP62 <~-. _ _ _ l ~~CTo/-.:>~-------.-..
'!.---/

CP70

1

"

<'-1~.

10KI~m.~
CP31
CP16 ~~!--L~~r_22~'3 _______ --<:,
10K14-Offi"h
I.'~ ,
CP1S

10KI4~
CP61

10K '4CiilJ---ll--~~~··
10K 14c::m-.i·CPR~,

2

10K I~OIDJ
10K ,4UiIlJ 6

.. ~

SO

FACT:~8

10KI~

-TI
::l

10K I 4-c::nrn-,9

31<3 1~c:irn-1L--·~)
3K3 14c:::Ji§) 10
Cp1 O~>

CP14

D12

NA

1

J.;

:<':

/'

NA

CP63

~

_,,\

D11

2

~

.,

~-.L.-I

31<3 141_"~1-.!--------<;)

_'

1\

'-;f~. ~_~I~L J

0

10KI4

CP72

CPI09

D

~J

E': 1,
3

~~1 ~.'

CP.88

A CP60

J.LjfL~,):;

CPS7 <)

~.

12

~129

~

~

<+---1----4-----

10KI~
CP66 0---CP87

~

.~"_' __ '.T-_1_.
---I

CP89

Jl
~

_2_

D

0

SO
FACT74
h 6
ON,.)

LX'

3

3

4

4
DESIGNER:
Hon Apr

IFF~~rIF=:
II\\~/I'·::·;~!. U= t[

FLAT_ORAWINO, VARIOUS_UNIT_6S. LOOIC .1.1
INSTANTIATION.

(CPU5V VARIOUS_utIIT56PI

A

SK

3 08,55,59 1995

~

B

I

C

COMPUTERS

.. PMW.1.N!L
ABBREV=VARIOUS_UNIT
APR/25/95 Manual

VARIOUS UNIT

SHEET
84

OF
94

REV.
0.2

A

B

_ _ _ _ _ _ _ _ _--1---

HOUIrrlllO

~ MH9

1B(~_1

MH44®_lNC
MH43@) __ lNC

"OUIrrlllO

MH7
1B«))__ 1
HOLE

'-:::;/

VALUE=P5MCJM2D
MH15
lB(0)----i:

MH41@ __ lNC

VALUEaP5HCJH2D
HOUHI'JOO
HOLI

MH13

HOUIrrll1O

lB~l

HOLZ
MH5
1B~__ 1

VALUE-P5MCJH2D
MHl1
(Q)-_1
HOL.

1B

__

~~~E§U~
BY SCREW

NO

']
zp;C~J'
[

1B~1

HOLI!

[_~_o~_;_-~1iL~~E__-I_F_~_-~
VALUE=FORCE

MH16

VALUE=FORCE

MHe

lB~ MI\6

VALUEaP5MC3M2D

VALUE=P5MC3M2D

HOUHI'IIIO

HOIIIrrJOO

HOLI

MH14
10(0)_1
HOL!

HOLI

VALUE=P5MC3M2D
HOIIIrrll1O

VALUEaP5MC3M2D

VALUE=CPU5V

VALUE=FORCE

ZF03

3

MH2

HOIIIrrJNO

MH12
1B ~ __ 1

ZF01

1B~_1

VALUE=P5MC3M2D
HOLII

ZF02

[-C~O~D~.I~~~~~~~-_I-F_--~~

MANUAL

1B~11

2

[~;D;;i~~~EIFENJ

ZFOB

lB~"__ 1

3

1

l"OR SWITCH MATRIX:

VALUE-PJM8C3MD

HOUIrrJIIO

r~

..

.~

1B~1

VALUE .. P5MCJM2D

..

M
M

DOPPEL
EURO
,_
.0-c===
VALUE=CPU5VROO

NC...

HOUHI'JOO

N

. T100N_20T_1206

MH3
1B(0)_1

VALUE-P5HC3H2D

"0IIItI'1I1O

M

cl __

HOLI

MHl0

"OUHI'JIIO

.~~:=~J~;-=~-=-~

IE

M

l_·-·---·-I"/US.TIfl; --.-._--

VALUE-P3MBCJMD

HOUHI'JOO

HOLI

•

tI

N

HOUHI'JOO

VALUE .. P5MCJM2D
HOL'

--·-------JI
[E~~f~~-~
_.:_----~=~_ _~
_____

~·~V~·;~~~~
rE

E~-

VALUE=PJM8C3MD

HOUHI'IJIO

2

t!?)P~T]

r_~D~~!J

VALUE=FORCE
VALUE=CPU5V
ZF05 FRONTPANEL ... NC

STI2
SONDER C.. LRRS2M5X5
SONDER:B=SRRS2M5X5
SONDER A=LRRS2M5X5
[--.-----.------/

STIl
SONDER-C=LRRS2M5X3
SONDER-BaNA
SONDER A=~S2M5X3

VALUE=rU5VROO

"OUIrrlllO
HOLI

...

. _ _. _

MH42 (ftr- 1NC

.• _ _ _ _ _ .. .1-_ _ _ _ _ _ _ ._. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .___ ._ ... ,

N~F07

NC.L!F06

VALUE=P5MCJM2D

1

___ L._. _ _ _ _ ._

Hon
MH4
1B ~) __ l

VALUE=P5HCJM2D

4

t1
DESIGNER:
Hon Apr

rr~it"]~fjf~~2)

FLAT_DRAwn/G. HECHIINIC.66. LOGIC .1.1

.~!I

JNSTANTIATIOI" (CPU5V HECHIINIC54PI

A

.. P.MWlt.lG_

SK

3 09.56.07 1995

--------B---·-----·-

----~c·-·-·l

~

I[ IF
_J

COMPUTERS

_-=::1

ABBREV=HECHANIC

APR/2S/95 Manual

MECHANIC

SHEET
85
OF
94

REV.
0.2

.~

A
••• 81gnlll CroslI-Refeunce ...
--- for the entlre deslgn --

1

2

3

4

.. ---.. -. --------_._-"- -

---~- _. __

123111CA
H.3C
I 23 I IIC8
23.4C
U51KBDIN
26.18
C25IK8DOUT
26.1B
1251HSEIN
26.38
U51HSEOUT
26.38
1211CE2
28. 2c
1281116
29.1C
1281A7
29.1C
129IA80RT_KEY_ORIG 30.4A
12910H_SYSFAIL_R d .• 1> 30.1C
I 29IC/lp_OEL
30.28
1291L7SEGH <1 .. 0> 30.1/1 30.1C 30.40
1291 PH_SEIISE
30.110
I2I1IRES_KEY_ORIG 10.lJl.
IUIRHLEO_R <1 .. 0> 30.1C 30.10
1291ROT <3 .. 0> 30.3C
C29IUSER_R <3 .. 1> 30.20
12111VREF
10.28
130IVSI_TEST
31.48
ClOIVSCTESTASYHC 31.48
C30IVSI_TESTSCAII 31.48
UlIEII"-..IH1T_L 32.48
1l1lRESI_SW
32.18
C3l1UN$l$JI.8T12S$88P$Y <0 .. 0> 32.18
Cl21Et1A..I\R8
n. 48
1121 PUAl
n.2c
1l21PU81
33.28
Cl2IUN$1$Jl.8T125$10"$Y <0 •. 0> 33.48
13lIJRo..L
H.4O
1l4lDT/lCK_IHEtIA 35.38
DTACIC_OUTDIA 35.38
1341ENA_CTRL
3S.n
(341Gr2
15.38
(341010
15.38
(34)019
)5.38
1341 PULLJl....CTRL 15 .18 35.20
I341PULLB_CTRL 35.10 )5.2C
U41 RETRY_INEtIA 35.38
U51£NA...A8UF
n.n
1361 ENA_OBur
37 • 40
131IFPY_ODlSDlIIlV 38.110
I3IIVHE_PO-"  39. 2C 39. 3C
138JVHE_PO_8 <14 •• 1> 39.2c 311.20 311.30
C381VHE_PO_C <14 •• 1> 39.20 39.30
C381VHE_PO_O <14 •• 1> 39.2039.30
131IVHE_PO_Z <14 •• 1> 39.2839.38
1411TPIN
U.1C
IUITPOUT
H.2C
14lIUN$1S9 HERGE$117P$Y <16 .. 16> 42.18
14lIUNS1$9 HERGE$l1IPSY  n.1C
IUIRESERVEO d •• O> 43.2A 43.2C
1421V3P3STB
n.1A
InIENA_HEH_BUF ".4J1.
141IUN$1$_Jl.DJl.PTJ4EH_ARR$110PSHAOUS <288 •• 288> 44. 2C

III CPU_CLK <2 .• 0> 2.28
ClICPU_Pl\ <21 •• 24> 2.182.4/1 2.40
C110IV_CtlTL <1 •• 0> 2.]/1
111 EXT_CLK2
2.38
111 EXT_EV
2.]0
1111'LL_8VP
2.38
I1IP_REPLY <1..0> 2.20
I1ISLVSEL <4 .. 1> 2.28 2.4/1 2.48
CliSTAND8Y
2.28
121 CLKHALF
3.28
I2lcLICCPU_QUOH ].28
121 LOOP
3.38
18ITERHFU8£
9.2/1
19IEN/ITERH_8J1.CK 10.2C
1101 ENJl.TERH_FROtIT 11.2C
110lRTERHI'WR
11.2C 11.1C
UOISC91_FPJ.CI( 11.2c 11.38
110ISCSJ_FPJ.TN 11.2C 11. 38
C10ISCSI_FP_8SY 1l.2C 11.38
C10ISCSLFP_CO 11.381l.1C
UOISCSJ_FP_O <1 •• 0> 1l.1C 11.28 11.2C 11.38
1I0ISC9LFP_OP 11.2C 11.38
UOISCSI_FP_IO 11.38 11.3C
UOISCSJ_FP_HSQ 11.38 11.3C
110ISCSLFP_REQ 11.38 11.3c
110ISCSLFP_RST 11.38 11.3C
110ISCSLFP_S!L 11.38 11.3C
111IENET_CH
12.28
I 11 I ENET_CP
12.28
I 11 I EtlET_1IH
12.28
1111 EHET_RP
12.28
111IEHET_TH
12.28
1111 EIIET_TP
12.28
UlIETHPF
12.38
Ull ETlIRF
12.38
IlllETHlIl
12.38
I111ETHlI2
12.38
1111GND_ETH
12.1C 12.3J1. 12.3C 12.4JI.
IlllTSEL
12.38
I11IVPS_ETH
12.3J1. 12.38 12.4/1
U4ICEtlTR_EIlA.-R lS.3J1.
114lc-"CItlIlV
15.30
U41C_89YJIlV
15.20
U4)C_OSIIlV
15.10
1141P_/lCItIIlV
lS.3C
114IP_8SYJIlV
15.2c
1141P_D911lV
lS.lC
C15ILIHK_TEST_EH 16.3C
115IHSLJRO_PU 16.3C
11 61 CLK_8UF_32 11.3C
1l61LOOP3
n.4C
1111 EHJI._LOC_8UrF 18.38
I 18II.CJI._HODE
n.3C
1l81I.CJI._HODE_R 19.38
UBI RESERVEO_SW8_H 19. 2C
1201 BOOTEPR_WR 21. lB
t20IBOOTWRITE
H.lc 21. lC
1201000T_E/I/I
21.2/1
C20IVPP_AOOR
n.lc 21.3C
121IPOWER_1JOWN az.lc 22.20 22.2c
121ISYSEPR_WR
22.IC 22.20 H.2C
C2118YS_E/I/I
22.3A
U2IHCJI.
24.3C
IHIIICD
24. 4c

,---~~-~--------.-------

B

13"

180IFILV1P31N
180IFJLVP51N
caOIVlPLOEN
182IESOR
1821 ESO_STRJ I'
1121SHJ
1841STIFF
/lBORTH
AOORTP

81.3C
81.41<
11.18
83.10
Bl.1C
n.l0
'5.10
19.3C 19.40 30.4A 30.4C
7.3/1 19.2/1 19.3C 19.48 ]0.4A 30.4C
11.30

L_. _ . _

I.________.__._~._. __ ._

C

D

BH_SYSFAlL_LED <1. .0> 19.18 19.48 30.1C 30.10 30.4C

CEtlTR_pE

15.4A 15.fC 18.28 38.4841.20 41.4c

8_CAS <3 •. 0>

CElrrR_SLCT

15. 4J1. 15. fC 3e. 28 38.48 41. 20 41. 4C

CElrrR_SLCT_11I

15.38 lS.4C 38.28 38.f8 41.20 U.4C

".lC ".2C ".10 "'.40 45.28 46.28
41.2848.2849.2850.28 51.28 52.28
53.28 H.28 55.28 56.28 57.28 51.28
59.28 60.2B 61.2B 62.28 63.28 64.28
65.2866.2861.28 68.28 69.28 10.28
71.2872.2811.2814.2875.2816.28
11.2818.2819.2880.28
8_HEH-" <11. .0> ".lC
".2C 44.38 ".48 4!1.18
45.2846.1846.2847.1841.28 ".18
48.2849.1849.2850.1850.28 51.18
51.2852.1852.2853.1853.285 •. 18
54.2855.18 S5.28 56.18 56.28 51.18
51.2858.1858.2859.18 59.28 60.18
60.2861.1861.2862.1862.2863.18
n.aa 64.18 64.28 65.18 n.28 66.18
66.2861.1861.2868.18 68.28 69.18
69.2870.1810.2811.1871.2872.18
12.2813.1873.2814.1874.2875.18
15.2816.1816.2877.1817.287Ilo18
11.2879.1879.2880.1810.28
8J1HE
".lC ".2C 44.40 45.28 45.30 46.28
46.38 41.2B 41.38 48.28 ".38 49.20
49.38 50.28 50.3D 51.2D 51.3D Sa.2D
52.38 53.28 51.18 54.28 54.38 55.28
55.38 56.28 56. 3D 51.28 51.l0 58.28
51.3859.28 59.38 60.28 60.38 61.28
61.18 62.28 62.38 61.28 n.38 U. 20
U.1B 65.28 65.38 66.28 66.38 61.28
61.]868.2868.1869.2869.3870.28
70.3871.1811.3812.1871.1813.28
13.3814.2874.1875.2815.3816.28
16.1811.2817.3878.2018.38 79.28
19.3080.28 80.38
B_OE
... lc ".2C 45.2846.28 47.28 n.28
49.2850.2051.2852.2851.2854.28
55.2856.28 51.28 58.28 59.28 60.28
61.2862.2861.2864.2865.2866.28
61.28 68.28 69.28 70.2D 11.28 '72.28
73.28 14.ZB 15.28 76.28 11.28 78.28
19.28 80.28
8_RAS .1 .. 0>
".lc ".2C ".30 4S.28 46.28 41.28
48.28 49.28 50.28 51. 28 52.28 53.28
54.2855.2856.2057.2858.2859.28
60.2861.2862.2861.28 64.28 65.28
66.2867.2868.28 69.2810.2871.28
12.2813.28 '74.28 75.28 76.28 '17.28
78.28 79.20 80.28
CIIS < 1 .. 1>
2.10
CEtlTR-ACK
15.30 15.4c 38.18 38.48 41.20 41.4C

".n

CDlTR..,AF

15.18 lS.4C 38.28 38.4D 41.20 41.4C

CEtlTR_8SY

15.20 15.fC 38.28 18.48 41.20 41.4c

CEtlTR_O .7 .. 0>

15.18 lS.lc 15.28 n.4C 38.18 38.48
41.10 41.20 U.4c
15.10 lS.4C 38.18 18.48 41.10 41.4C

CEtlTR_OS

CEHTR_OX . ' .. 0> lS.2D
41.10
CEHTR_EHII
1S.U.
CENTR_ERR
lS.4J1.
CEHTR_IIIIT

lS.2C 15.4C 38.3038.48 18.40
41.4C
lS.2A lS.4C 18.28 38.48
15.fc 38.28 11.48 41.20 41.4C

15.38 15.4C 31.28 38.4D 41.20 41.fC

CLKCPU
1. 48 2. 3A 1.20
CP_STAT .1. .0> 1.48 2.]0 16.30
CS_BOOT <1 .• 0> 19.20 19.]A 21.1C 21.2C
CS_SVSEPR <1 .. 0> 19.20 19.3A 22.1C 22.2C
CTRL_VPPIIlV
\8.48 19.3A 19.38
CTS_DCO_A
38.10 41.]C 41. fC
CTS_DCO_8
]8.20 U. 3D 41.4C
OIW',-COOE_1I <1 .. 0> 29.2829.3835.18 B.1C 41.]C
43.fC
0IWCCOOE_8 <1 .. 0> 29.2829.3835.38 41.1A 43.]A
43.4C
ORJ\H_CODE_LOC <1 .. 0> 29.1C 29.2C 29.38 35.38
E8_A <23. .0>
lB.1C 11.2C 18.20 19.1C 19.28 19.20
19.3A 21. lc 21. 28 21. 2C 21.38 21. 48
22.1C 22.'C 28.1828.2828.38
E8_/119_0RIG
19.1C 19.3/1
E8_/IOORL
16.3/1 18.38
E8_0 <7 •• 0>
16.3/1 lB.3C 18.fC 19.28 19.3A 22.10
22.20 2B.1C 28.2c 28.38 29.1029.20
29.30 29.4C lO.3c 30.40
E8_RO
16.3A 19.20 19.3/1 21.1C 21.1C '2.1C
22.2c l8.2C
E8_WR
16.3/1 19.20 19.3A 21.3A 22.3J1. 28.2C
EIRO
EIIA_HEH_OE
EIIET_IIUI
EHET_CLSH
EIIET_RCLK
EIIET_REIIA
EHET_RX
EHET_TCLK
ENET_TEHA
ENET_TX
EPROHSS

ETICCOL_H
ETN_COkP
ET,,-pOW
ETI'-POHER
ETH_REC_H
ETH_REC_P
ETH_TRA_H
ETN_TRI\..P
FILVlP3
FlLVP5
FPLCLK24
FPY_CLK32
FPY_OEIISEL
FPY_OENSEHSE
FPY_OIR
FPY_OISKCHG
FPV_ORVSEL
FPY_EJECT
FPY_HEAOSEL
FPY_IOOEX
FPYJ40TEH
FPY_ROOAT/I
FPY_STEp
FpY_TRACKO
FPY_WRO/IT/l
FPY_WRGIITE

1

2

1.28 8.2A 16.3C
".lC ".2C
'.lC 12.2A
'.2C 12.2/1
8.1C 12.2A
'.lC 12. 2J1.
8.2C 12.2A
•. 1C 12.2J1.
8.1C 12.2A
a.1C 12. 2J1.
16.3J1. 19.20 19.3A
12.2c 14.28 38. 3C
12.2c 14.28 3B.1C
38.30 3B. fC 41. 2D 41. 4C
11.28 14.28 le.4C
12.2C 14.28 18.4C
12.2C 14.20 38. 4C
12.2c 14.28 18. lC
12.2c 14.28 lB.4C
2.28 81.30
2.28 II. 40
8.1C 16. 4C 17.28
8. 3c 16. fC 11.] 8
16.1c 38.IA 38.3A
lS.1c 38.10 38.3A
n.1C 38.1A 38.1A
16 .1C 38. 2A 38. lA
16 .1C 38.1A 38. 3A
U.1c 38.2/1 38.]/1
16.1C 38.2J1. 31.1/1
16.1C 18.1A 38.1A
16.1C ]B.1J1. ]8.3A
16.1c 38.2A 31.311
16.1C 3e.1A 38.3A
16 .1C 18.2/1 38.1/1
16.1C 38.2A 18.1A
16 .1C 38.2/1 lB. 1/1

3

4

.- .. - - .. ---- .

-'-'----

DESIGNER:

SHEET
86

--.-·----0 ..·-

A

--C------B--------

·---------c--

ft)~[E
COMPUTERS

APR125/95 Manual

CROSS REFERENCE

OF
94

REV.
0.2

B

A
----,-.~-----------------

1

FP'CWRPROT
FPCXT24_JII
FPY_XTH_OUT
FPLXT12_I11
FPCXT3LoUT
GEICCS
GEN_ROY
10_CS
IIlL d. _0>
KOD1NU
KODIN_colm
KOOOUTp2
KOOOUT_colm
KOO_OIII
KOD_OOUT
KOO_I'WR~CONII

LCI\SYSRESETO
HEH_P <7 .. 7>

HSEIHP2
HSEIII_CONII
HSEOUT_CONII
HSE_OIII
HSE_OOUT
H_O <63 •• 0'

2

3

4

NC81
HHI
tlVRIIH_C9
P2Cl
P2C2
P2C4
P2CS
p2Ca
P2C9
PZC10
P2Cll
P2c12
P2CU
p2CU
nCIS
nc16
P2C11
P2cU
POWER_OFF
P_IICK
P_",CK_OIR
P_I\F
p_OSY
P_8SY_OIR
P_O .1_ .0>
P_OS
P_DS_DIR
P_O_OIR
P_ERR
"_IIIIT
P_PE

H.IC 18.21\ lS.31\
8.3C 17.10
8.3C 17.18
8.3C 17.10
9.3C 17.10
16.31. 19.20 19.31\
16.31. 19.20 19.31.
8.1C 1~.40
1.482.)016.30
38.10 41.3C n.4C
2S.lc 27.2D n.lc
38.10 U.3C n.4c
26.1C 27.20 38 _2C
16.3C 26.11\
16.3C 26.11\
26.,e 2'.28 41.18
19.30 19.30 n.11\
2.10 2.'C 42.11\ 42.lD n.3A 42.39
U.3c 43.31\ 41.30 43.1C 43.10 41.40
".lC S3.2C n.2C 71.2C aO.2C
38.10 41.1C n.'c
26.2C 27.20 18.2c
26.30 21.2D 41. 20
16 .1C 26.21\
16.3c 36.",
2.10 2.4c 42.11\ 42.21\ 42.28 42.311
42.10 U.3C 42.'1\ n . u 41.18 n.1C
41.1041.21\ 41.20 n.2C 41.20 41.11.
43.-30 n.3C n.10 43.'0 ... ac 45.2C
U.2C n.2C ".2C U.2C 50.2C Sl.2C
S2.2C S'.2C 5S.2C 56.2c ".2C 5S.2C
59.2C GO.2C 61.2c 63.2C 54.2C 55.2C
st.2C 51 _2C 68.2c 69.2C 70.2C 72. 2C
H.2C 7'.2C 'S.2C H.2C 77.2c 7a.2C
79.2c
15.10 15.20 18.IC
7.31. 16.3'" 19.2'" 19.2B 11.38
16.1'" 18.48 28.2C
18.11. 38.40 41.10 41.4C
38.111 38.4D 41.10 U.4C
38.11\ 38.1041.10 41.4C
38.11\ 31.3041.10 U.4C
38.1'" 38.10 41.10 U.4C
38.11\ 3'.3041.10 U.4C
38.11. 38.3041.10 41.4C
18.21. 38.30 41. 20 n. 4C
31.21\ 18. 3D 41.20 U. 4C
18.2'" 38.10 41.20 U.4C
38.21\ 18.30 41.20 n.4C
18.21\ 38.30 41.20 U.4C
38.2'" 18 .30 41.20 U .4C
18.2'" 31.3041.20 41.4C
38.21\ 3a.30 41.20 41.4C
16.1C
a • 2C 15. lC 15. 48
'.lC lS.3C 15.48
a.3C 15.31\ 15.48
'.2c 15.2C 15.48
'.3C 15.2e 15.48
8.2C 15.111 15.21\ 15.48
e.2c lS.1c 15.48
B.3C 15.1C 15.48
a.3C 15.1'" 15.21\ 15.'0
'.3C 15.48
8.1c 15.31\ 15.40
a.2c 15.40

-------- - .. -

-,---------~---~--

..

~----.-

... -

-P_IUIS <6 .• 0>

------_. -- ..

..I
-~-.--

n.lc 42.2C 41.11\ n.lc 43.10 43.4c

8.2c 1~_40
8.3C 15.31\ 15.48
19.2019.)1\ 29.3C
19.20 19_ 40 30.4C
30.21\ )0.4c
19.3C 19.48 30.211 10.4C
7.31\ 19.211 19.20 19.40 30.IC 30.4c
n.30
RES_I'WUP_p
19.3019.40 10.IC 30.4C 32.21\
IIES_I'WUP_IIEQ
19.3C 19.4D 30.11\ )0.4C
IITS_OOII_A
3a.l0 41.3C 4L4C
RTS_OOR_O
3a.20 41 .30 41. 4C
RUII_HAI.T_LED <1..0> 19.3D 19.4D 30.1C 30.10 30.4C
SO_ACK <2 •• 0>
2.11. 4.2C 4.38 S.2C S.3D 6.20 6.30
'.188.21\ 16.11. 31.20
S9_119
2.1'" 2.41\ 4.19 '.2C 5.19 S.2C 6.19
6.207.18 B.211 16.1A 31.2D
SO_DO <5 •• 0>
2.21\ 2.20 4.1c 4. 2C 5.1c 5. 2C 6. lC
6.20 a.2'" 31.28
SO_OR .5 •• 0>
2.28 4.18 '.2c 5.19 S.2C 6.IB 6.20
7.2B 8.21\ 31.20
SO_CLI( <0 •• O'
2.21\ 2.41\ 4.18 4.3C 5.18 S.3C 6.10
6.20 7.3C e.2'" 16.21\ 19.11\ 19.1C
31.29
SO_O <31 .• 0>
2.111 4.21. 4.28 4.2C 5.21\ 5.28 S.2C
6.11. 6.18 6.1C 6.21. 6.20 6.2C 6.20
6.3'" 6.18 '.IC 1.2C 8.1'" 16.1'" n.1B

P_SLCT
P_sLCT_III
1I0_0RIIH_CODE
IID_ROTI\RY
IIESETII
liES_KEY
IIES_I'WUP

S8_0P
SO_ltlT 01 •• 1>

• _2C •• III 5. 2C S .3A 6.20 S .3", 7.1B
'.10 '.20 '.3C S.lD 5.20 S.3C G.l0
6.206.20 6.3D 1.28 a.2'" 16.2'" 31.28

SO_I.ERR

2. III •• 2C •• 30 5. 2C 5.3B 6.20 6.30
7.18 '.21\ 11.28
2.11. 2.48 2.4c '.211 '.28 4.2C '.3A
4.10 t.lc 5.21\ 5.20 5.2C 5.'''' 5.38
S.lC &.20 6.1A 6.30 S.IC '.lA 16.11\
18.1C 18.2'" 18.20 18.2C 31.2D
2.1'" 4.20 '.2C 5.2D s.2C 6.20 6.38
7.108.21\ 16.11\ 31.20
2.21\ a.41\ 4.ac 4.38 5.2C 5.30 6.20
6.301.188.21. 16.2'" 18.211 18.4D
19.11\ 19.10 10.40 31.20
7.11. 16.311 19.211 19_1C 31.38
2.21\ 2.48 2.4C 4.1'" 4.2C 5.111 S.2C
6.1'" 6.20 a.21\ 16.11\ 19.1A 19.21\
11.21\
2.1A '.21. 4.28 '.2e S.2A 5.28 S.2C
6.20 6.3A 6.30 6.3C 7.18 8.21\ 16.11\
11.28
8.3C 16. 4C 17. ac
a.3C 11.10
a.1C 17.18
8.2C 10.1D 11.30 38.1039.4'" U.2C
n.'c
a.2C 10.1D 11.30 3a.20 38.41\ U.2C
n •• c
a.2c 10.2D 11.38 3S.2D 3a.411 41.2C
n.tc
a.2c 10.30 11.30 38.10 18.4'" 41.1C
n.4c
a.2C 10.20 11.20 11.38 38.20 38.4A
n.le 41.4C
l.lC 10.20 11.3038.20 la.4'" 41.1C
n.4C

SO_P'" e21 •• 0>

SD_II0
S8_RST

S8_RST_REO
SO_SEL <7 •• 0>

SO_SIZ .2 .• 0>

SCC_CLK
SCC_XTIII
scc_xroUT
SCS,-",CK
SCSI.J\TH
SCSI_OSY
SCSI_CD
SCSCD ., •. 0>
SCSI_OP

'---------------- ------- ------------

J______________ ~ _.__________________

C

.--.- ...

---

,.-----~-

SCSI_IO

-~------------.--

U_IUIS <7 •. 0>

8.2C 10.38 11.38 18.1038.41\ U.3C
41.4c
SCSJ_HSO
8.2C 10.30 11.30 38.10 39.41\ H.2C
41.4C
SCSI_REQ
8.2C 10.28 11.30 38.10 38.4'" U. 3C
41.4C
SCSI_liST
e.2C 10.3811.3838.10 3e.4'" ".2e
41.4e
SCSI_SEI.
8.2C 10.2D 11.30 18.10 38.411 U.2C
n.4C
SCSI_XTIN
8.3C 17.10
SCSI_XTOUT
a.3C 17.10
SER_CTS_I\
16.2C 24.21\ 24.30
SER_CTS_I\_cotm 24.20 25.2D 3S.1C
SER_CTs_8
16.2C 23.21\ H.)O
SER_CTS_D_CONII 23.202S.203a.2c
SER_OCO_A
16.2C 24.2/>,
SER_OCO_A....CONII 24.2025.20 la.lc 41.30
SER_OCO_O
16.2C 2).2'"
SER_OCO_B_CONII 21.20 25.lo 18.2C 41.20
SEII_OSII_'"
16.2C 24.2'"
SER_DSR...A_COIRI at.20 25. 2D 41.3B
SER_OSR_B
H.3C 23.211
SER_OSR_O_COtm 23.2025.2041.28
SER_OOII_'"
16. ac 24.21.
SER_OOR_A....CONll 24.2025.20 3B.IC 41.30
SER_OOR_B
16.2C 21.2'"
SER_OOR_D_CONII a).20 25.2B 3B.2C 41.20
SER_OHD_"'_CONII 24.20 2S.28 41.30
SER_ONO_B_CONII 21.20 2S.20 41.18
SER_IITS_A
16.2C 24.21\ 24.20 24.30
SER_RTS_I\_CONII 2'.20 25.20 18_1C
SER_RTS_O
16.2C 23.2'" 21.20 23.30
SER_IITS_8_CONII 23.20 25.20 3a.2c
SEII_IITXC_I\
16.2C 24.2'" 24.30 24.40
SER_RTXC..I\...CONII 24.20 25.20 U. 20
SER_RTXC_D
16.3C 23.2'" 21.1023.40
SER_RTXC_O_CONII 21.20 25.20 41.IB
SER_IIXC_II_CONII 24.2025.1041.20
SER_RXC_8_CONII 23.2025.2041.10
SER_RXO_I\
16.2C 24.2'"
SER_RXO...A_CONII 24.2025.28 38.10 41.3C U.4C
SER_RXO_O
16.aC 23.21.
SER_RIID_8_CONII 21.20 25.20 38.20 U. 10 U. 4C
SER_TRXC_II
16.2C 24.2'" 24.28 24.30 24.4B
SER_TIIXC_B
16.2C 23.21\ 23.28 n.1B 23.40
SER_TXC_I\_CONII 24.20 25.20 41.1D
SER_1'XC_B_CONll 23.2025.2041.10
SER_TXO_A
16.2C 24.2'"
SER_TXD_A_CONII 24.2025.18 38.10 41.3C 41.4C
SER_TXD_B
U.2C 21.2'"
SEII_TIID_D_CONII 23.2025.1018.2041.30 41.4C
SHIELD
11.10 14. ac 2S.1c 21.2C 30.11\ 30.4'"
83.1C
SIRO
1.20 a.2'" l6.1C
S!.V_SVS_LEO
16.11\ 19.1c 19.40
Sp_SEL <1. .0>
2.202.4015.383S.3C
TERHPWR
9.20 10.1C 11.'C 38.20 38.4A H.2C
41.4C
TIH_C[.I(
16.31. 16.4c 17.3D
USER_I.EO <3 •• 0> 19 .IC 19.48 10. 2C 10.20 10. 4C
U_CAS "3 .. 0>
2.4042.1841.111 n.1D H.1C 41.10
43.41\ ".IC U.1B 44.40
U_MDt_1\ <11..0> 2.102.40 n.18 n.ll\ 41.18 n.1C
41.10 n.4C H.IC 44.21\ 44.3A 44.41.
U_HWE
2.202.4042.1041.11\ n.1C 41.41\
H.lc ".48

V3P3_YMEcotm
VI\ <11 .. 1>
V",CFIIILI
VIIDJR
VAH <5 .. 0>
VI\S
VASDJR
VOBSYJ
VBBSYO
VOCLR
VOERRI
VOERRIVSI
VOERRO
V8ERROVSI
VOGIN <3 •. 0>
VOGOUT <3 .. 0>
VORl <1 .• 0>
VORO <1 .. 0.
VO 
VODJR
Vos <1 •• 0.
VDTIICK
VOO",CKOIR
VOOI\CKOIS
VDTI\CKROE
va", .4 .. 0.
VOIIP
VIACK
VIIICKIH
VII\CKOUT
VIRQI <7 .. 1>
VIRQO .1 •. 1'
VLWORO
VMlIOIR
YME_I\ ell .• 1>
YME_"'CFIIJ[.
YME_1I00P
VME_AH <~ .• 0.

..------.-----

2.102.4042.18 n.lc 42.2C 43.11\
43.18 43.1C 4l.4C U.IC 44.30
81.1",
19.1019.30 3L1C 36.11\ 36.18 36.20
16.)0 )6.40
3Llc 12.20
19 .10 19.38 31.1C 36.10
3L2C 35.18 3~.2D U.2C n.4C
19.20 U.1C 31.2C 35.20
19.20 19_1C 31.2C 3S.2C
31.1C
19.)C 19.)0 31.)C 33_4B
31.3C H.20
19.1C 19.20 35.40
19.1C 19.4C 31.1A H.2D
19.ID 19.20 35.40
19.18 19.4C 31.11\ 31.2D
31.3C 1l.20
31. JC 33.30 33.49
31.3C 33.10 13.20
31.3C )).IB 31.20
31.1C 11.11\ 17.\0 37.20 31.30 31.40

1

31.1C 37 .IC
19.211 \9.20 H.2C 35.18
19.20 31.2C 35.30
\9.203l.2C
19.3C 19.4C )~.10 35.)C
19.201l.2C
19.1019.4012.1032.40
19.10 19.40 H.40
)1.2C 35.10 n.20 42.4c
31.1C 34 .40
31.3C 34.48
31.2C 34.3'"
31.2C 34.20 14_111 34.30
31.1C 36.1'" 16.48
11.2C 35.10 42.2B n.4c
36.1C 36.10 36.2C 36.3c 36.4C 40.11\
40.20 40.3C 40.3041.1'" 41.1C U.2C
12.2C 40.1C 40.31\
39.2'"
35.1035.2040.21\ 40.2C 40.20 40.3C

2

YME_AHCP
39.211
YME_I\PV
39.21\
YME_I\S
35.2040.211 40.2C
YME_OOSV
3l.4C 40.1c 40.31\
VHE_8CI.R
3l.2C 40.1C 40.)"
YME_OERR
35.4C 40.21\ 40.20
YME_DOJH <3 •. 0> ll.2C 40.1c 40.311
YME_BGOUT .3 .. 0> 33.1C 33.4C 40.1c 40.2C 40.3"
YME_OR 03 •• 0>
H.1C 33.2C 40.2c 40.1A
YME_O 
n.IC 31.10 31_2C 17.3C 11.4C 40.1"
40.1C 40_10 41.1A U.2c 41.1C
YME_OATP
39.211
YME_OPV
19.2'"
VME_DS <1. .0>
15.10 40.2'" 40. ac
YME_OOI\CK
3S.3C 40.21\ 40.2C
VHE_GI\ <4 .. 0>
12.3C n.4C '0.1040.2040.20
VHE_O",p
32_4C 40.10 40.2B
YME_I"'CK
35.10 40.21\ 40.2C
YME_lI\CKIN
14 . 4c 40.2'" 40. ac
YME_II\CKOUT
14 .4C 40.2C 40.311
YME_IRQ <7 •• 1> H.1C H.2C H.3C H.30 40.2'" '0.3C
YME_I.H

--- --------------- --- - - - - - - - - - - - ----- ------

-----_

DESIGNER:

3,

39.21\
...

__

.... _.

--._-------------

41

--~.-

------.~-

SHEET
87

fl~])K;) [
'<::::_

-------------1\---

----·-----T----------B---------------------I--'-~------c---

~

~

lE

COMPUTERS

__ :::l

APR/25/95 Manual

CROSS REFERENCE

OF
94

REV.
0.2

A
-------------------------------------- -----------

1

2

3

4

VME_LI0
VME_LWOllO
VME_P2Z <1..1'
VHE_Rt'fRY
VME_SB,.
VME_SBB
VME_STDBY
VME_SYSCLK
VHE_SYSFAlL
VME_SVSRESE1'
VMF._VPC
VME_WRITE
VPSIIVAAM
VPP_SHITCH
VRETRYJ
VSCON
VSJSYSRESETJ
VSJ_CLK
VSVSCLK
VSYSFAlLI
VSYSFAlLO
VSYSRESETI
VSYSRESETO
VWRJTE
V_ETlf_COLJt
V_ETlf_COL_'
V_ETH_REC_H
V_t'fH_REC_'
v _ETlf_TAA_H
V_ETlf_TAA.,P
HR_1SEGH
_""I,. d •• 0>

39.3"
36.10 36.4C 40.1" 40.20
n.4c
35_4c n.lC 41.211
39.2"
39.211
28.40 40.3C 43.3" 43. 3C
40.1C 40.3"
H.3C 40.1040.3"
H.IC 40.20 40.311
19.3"
35.1040.2" 40.2C
a8.2c
20.3021.40 22.1C 22.2C
31.2C 3!L40
19.20 19.4C 31.4C H.2C H.3C
19.30 19.30 11.3C
11.4831.38
n.3C 31.3,. n.30
19.3C 19.3D 31. 3C 12 .30
19.2D 19.40 31.3C 32.3B
19.38 19.1032.1"
n.3c U.2,.
11.2C 35.18
U.3C 38.3D 41.1D 41.4c
38.3C 38.30 U. lD U. 4e
18.30 38.4C 41.30 U.4e
38.30 3I.4e 41.2D 41.4e
38.3C la.3D 41.30 41.4C
)8.30 n.4C 41.30 41.4c
19.3B 19.48 30.40
l.IC 1.4C 35.1" 15.2c 42.2c U.48
U.4C
_CEIITRX_OUS <1 .. 1> 1.1,. 8.30 15.40
_CEIITRX_COIIN_BUS <1 •. 1> 1.2B 15.40 38.48
_CLOCK_BUS <1 .. 1. 1.208.3016.40 17.2"
_DIWLCODE_BUS <1 .. 1> 1. 3D 2. n 29.1" 15.30 41.4B
_t'fIlERNET_BUS <1 .. 1' 8.1D 12.lA
_t'fIl_BUS <1 .. 1. 1-1A
_t'fH_CONN_BUS <1 •• 1> 1.1,. 12.1D 11.20 14.'" 38.18
_FLOPPY_BUS <1 .. 1> 1.3" 16.10 lB.l"
_JT"O_CLK
2.188.1" 16.4" 16.4c 19.18 19.28
11.10 sa.2C
_JT,.O_RST
2.38 •. 1" 1&.4" ".4C n.2C
_JT"O_TDI_TOO <'.1 .. 0. 2.388.3" 1I.4A 16.4C 19.18
19.1019.2831.48 82.2C
_JT"O_'I11S
2.208.311 1&.4" 16.4C 19.18 19.28
31.38 82.2e
_KBD_HSE_OUS <1 .. 1> 1. 3" 16 .1D 26.1"
_KBD...HSE_CONN_BUS <1 .. 1> 1.1" 26.10 21.2" 38. 2C
_LOC_OUS <1 .. 1> 1.3C 16.4A 18.4B 19.4A 20.3A 21.4"
22.4" 2B.l" 39.48 10.3C 30.40
_IUIC <1 .. 1'
1.3D 42.1C ".2C
_IUID <1 .. 1>
1.40
1 .• 0
_lUI! <1 .. 1'
_lUlU <1 .. 1>
1.4c .:i.18
_HEH_O_DRH <499 •• 0> ".10
_HEH_I_DRH <499 .. 0. 44. ~o
_HEH_"RAAY_BUS <499 .. 0. 2.4D 43 .• "
_HEH_"RR_CON <499 .. 0) 41.10
_HEH_ARR_CONN <499 .. 0> H. 111
_HEH_"RR_UBUF' <499 .. 0> 42 .1"
_SBUS <1 .. 1>
1.1C 2.~" 4.3D 5.10 6.30 1.2" '.111
16.3" 11.ID 18.3" 19.2A 31.1"
_SCSLBUS <1 .. 1> 1.1" 8.209.2010.3" 1l.3A 38.411
_SER_"_BUS <1 •• 1> 1. 3" 16.2D
_SER_"_CONN_OUS <1 •. 1> 1. 3" 25.1" 3a.lC

________

- ________

~

_ _ • _ _ _ _ _ • _ _ w~·

_ _ _ _ "_ _ _ ~.

B

------~-----.-

--.... -------_._--

.. -

,---------------_._---_. ----- -----

C --------

l __ ~ ___.__________ ~ _____________________________

_SER_BUS <1 •• 1~ 23.2" 24.211
_SER_B_BUS <1 •• l' 1.311 16.3D
_SER_B_COIllCBUS <1 •• 1> 1. 3,. 25.411 38. 3C
_SER_COIIN_BUS < 1'•• 1> 21.2D H. 2D
_TAA_VME <1 .. 1~ 1.1C 19.4B 19.4D 31.111 31.4D 32.411
33.4" 34.111 35.1" 36.111 37.111
_VME_OUS <1 .. 1> 1.2c 32.4D 13.1D 14.1D 35.4D 36.1D
31 .1D 38. ID 19 .3,. 39. 3C 39. 4C 40. III
40.2C 40.3B 40.411 40.4B 41.10 41.20
41.3D 41.411 41.tC
_VME_BUS_X <199 •• O~ 32.4D

l'
!

-------

2

3

_ •• _ _ _ _ _ _

4
DESIGNER:

--'.-_._ .. -.-

SHEET
88

-----

-r;---- -------- I

If~~[[(~
~ ---)-[
B

I

c

COMPUTERS

APR/25/95 Manual

CROSS REFERENCE

OF
94

REV.
0.2

,--______

A

B
r'--

... Unit Cron-Raference •••
--. for the enthe design --

1

C58
CSt
c60
cn

Bl
B2
Bl
B4
Bll
B12
Bll
Cl
C2
Cl
C4
cS
c6
c7
c8
C9
Cl0
Cll
Cll
Cll
cU
ciS
c16

COil SOC 1111 6 1&.110
COlIsOCIX16 18.1B
COlIsOC1X16 l8. IB
COIISOCIX6 82. IC
COlIsOCIX8 1& .1C
COIISOCIX8 18.1C
CONSOCIX& 18.1C
CAPC
81. 4B
CAPC
81. ]0
CIIPC
11.]B
CIIPC
t? 3D
CIIPC
26.1B
CAPC
26.4B
CIIPC
26. lB
CIIPC
26.2B
CIIPC
26. 2S
CllfC
12 .1B
CIIPC
IS .10
CIIPC
9.]B
CIIPC
12.]B
CIIPC
12 .• 10
Clift
12.]8
CIIPC
12.311
CIIPC
12. 2C
C18
CAPC
12 .1A
Cit . CAPC
12. 3A
c20
CAft
12. 2C
CIIPC
12.410
cn
Clift
84.20
C21
CAPC
17. 2B
cat
CAPC
17.2C
C2'
CAPC
20. 2C
c26
CIIPC
20. 2C
cn
CAft
20.20
C28
CIIPC
11.4C
C29
CAft
10.3C
C]O
CAft
".10
Cll
CIIPC
13 .1B
cn
CAPC
17.1C
cll
Cllpe
31.4B
C14
CIIPC
]0.2B
c15
CAPC
1.lC
C]6
CAPC
30.2B
c17
CAPC
15.10
cn
CIIPC
15.20
C]9
CAPC
15.10
C40
Clift
11.1C
Ctl
CIIPC
17.IC
cn
CIIPC
11.10
cn
CApe
H. 110
c44
CAPC
14.110
C45
CAPC
H. 110
CIIPC
14 .110
cn
CAPC
7.]0
cta CIIPC
14.210
c49
Clift
34 .111
C50
CIIPC
34 .110
c5t
CllfC
81.20
C52
CApe
81.2D
C51
CAPC
81. 2C
C5t
CIIPC
11.10
cS5
CAPC
81.4B
C56
CllfC
11.1D
CS1
CAPC
17 .10

cn
cn
C64
C6S
c66
c61
C68
c69
C10
Cll
C8LI
CBL2
COLl
CDL4
CDL!!
COL'
CBL?
CSL8
CBL9
CBL10
CBLtl
COL12
COL13
CSLU
COLlS
CBL16
CBLt?
CBL18
COLl9
CBL20
CBLU
COL22
COL23
CBLU
CBL2S
COL2S
CDL27
CBL2.
COL29
COL10
CBLll
CBL32
CBLll
CBLH
CDL]S
CDLlS
CBL1?
CDLlI
CDL]t
CBL40
CBLU
CDLU
CDL.,
COL. .
C8Lts
CBLU
CDL41
COL"
CDLU
CDLSO
COLSl
CBLS2
CBLS]

cn

2

cn

3

cn

4

t

_______
--~---------

CIIPC
CAPC
CIIPC
CAPC
CAPC
CIIPC
CIIPC
CApe
CAPC
CAPC
CAPC
CIIPC
CAPC
CAPC
CIIPOLOCK
CAPBLOCK
CIIPOLOCK
CA'DLOCK
CIIPBLOCK
CIIPOLOCK
CAPBLOCK
CAPSLOCk
CIIP8LOCK
CAPOLOCK
CAPBLOCK
CAPOLOCK
CAPBLOCk
CIIPOLOCk
CAPBLOCK
CAPBLOCK
CAPBLOCK
CIIPOLOCK
CAPBLOCK
CAPBLOCK
CAPOLOCK
CIIPBLOCK
CAPBLOCK
CAPOLOCK
CIIPOLOCK
CAPBLOCK
CAPBLOCK
CIIPBLOCK
CAPBLOCK
CAPBLOCK
CIIPOLOCK
CIIPOLOCK
CAPBLOCK
CAP BLOCK
CIIPDLOCK
CAPDLOCIt
CAPOLOCK
CliP BLOCK
CIIPDLOCK
CIIPBLOCK
CAPDLOCK
CAPDLOCK
CIIPDLOCK
CIIPDLOCK
CIIP8LOCK
CA'BLOCK
CAPBLOCK
CAPBLOCK
CIIPBLOCK
CIIPDLOCK
CllpOLOCK
CIIPBLOCK
CIIPDLOCK

81.20
81.30
17 .1C
11.]B
17.2B
17.20
17 • 410
12.1B
210
]2.310
12.110
U. 2C
17. 2B
17.10
8]. 2B
81.210
83.2B
81.2B
U. 210
83.210
83.2S
&1.2S
.3.210
83 .210
81.210

n.

n. 2B
83 .1B

n

.'10
'3.210
83.210
83.110
U. 10
n .111
13.210
83.210
81.210
83.110
U .110
83.10
U. 210
83.210
83.210
'A
81. 'A
81.110
83.210
83.210
83.210
13. lA
n.1A
83.110
n . 20

n.

n.211
83.210

81.11'.
n.1A
13 .110
n .2D
n . 210
83.111
81. III
83. 1A
83. 2D
81.110
81.110
83.110
83_ 'D

____ l

C

__._______ . ___.

o

•
COL54 CIIPOLOCK
COLSS CIIPOLOCK
CBL56 CAPOLOCK
CBL!)l CAPBLOCK
CBLS8 CAPO LOCK
CDLS9 CAPOLOCK
COL60 CIIPDLOCK
COL61 CAPOLOCK
CDL62 CAPDLOCK
COL&) CAPBLOCK
CDLU CAPOLOCK
CDL6S CAPBLOCK
CBL66 CIIPBLOCK
CBL61 CAPDLOCK
CBL68 CAPBLOCK
CBL69 CIIPBLOCK
COL10 CIIPOLOCK
CBLH CAPBLOCK
CBL12 CIIPBLOCK
CBL13 clIPOLOCK
CBL14 CAPDLOCK
CBL1S CAPDLOCK
COL16 CIIPDLOCK
CBL" CAPOLOCK
CBL18 CIIPOLOCK
CBL19 CAPDLOCK
COL80 CAPBLOCK
COL81 CIIPDLOCK
CDLU CAPDLOCK
COL83 CAP8LOCK
CDL84 CAPBLOCK
CDL8S CIIPDLOCK
CBL" CAPBLOCK
CBL87 CAPBLOCK
CDL88 CII'BLOCK
CDLa9 CAP8LOCK
COL90 CAPBLOCK
CBL91 CII'DLOCK
CDL92 CAPDLOCK
CDL93 CAPBLOCK
COLU CAPDLOCK
CBL95 CA'BLOCII
CDL96 CAPDLOCK
COL97 CAPDLOCK
COL98 CIIPDLOCK
COL'9 CAPOLOCK
CBL100 CIIPOLOCK
COL101 CAPOLOCK
CDL102 CAr8LOCK
C8L10l CAPBLOCK
CBL104 C"PBLOCK
COLI OS CAPBLOCK
CBL106.CAPBLOCK
CBL10l CIIPDLOCK
COL108 CIIPDLOCK
CDL109 CIIPBLOCK
COLllO CAP BLOCK
CBLlll CUBLOCK
CDLI
CIIPBLOCK
COL1l3 CAPOLOCK
CDL1l4 CIIPBLOCK
CDLUS CAPOLOCK
CBLll6 CAPOLOCK
COL1l1 CAPBLOCK
CDLU8 CIIPBLOCK
CBLU9 CIIPBLOCK
CDL120 CIIP8LOCK

n

--~~

8] .110
83.1A
8] .1B
8] .1A
83 .1B
83.10
8] .1D
83.10
8]. 2B
81.2D
83. 2B
81.2B
83 .1D
n.1B
83.1D
n. 2B
Bl _2B
Bl.2C
83. 2c
Bl.2c
81.2B
Bl. 2B
n.2B
83 .lc
n.1C
Bl .1B
83. 2B
n.2B
83.2C
83. 2C
n.l0
83 .10
81.1C
81.2D
81.2B
81.2C
81. ac
81.1B
83.1B
lC
n.2B
8] .1D
81_ 2C
81. IC
U.IB
83. lC
83.28
83. 2B
83.28
83. ac
83 .1B
83 .1B
n.1D
ac
83. ac
83.1B
83 .1C
83.2D
ac
83. ID
83.1C
n.1C
81.10
83 .1C
83.1D
81. 20
n .1C

COL121 CIIPOLOCK
CBLl22 CII1'8LOCK
COLl23 CIIPDLOCK
C8L1H CIIPBLOCK
COL12'.i CIIPOLOCK
CDL126 CAPBLOCK
CBL121 CIIPDLOCK
CBLl28 CIIPBLOCK
COL12t CIIPBLOCK
COLI30 CIIPBLOCK
CBL1]1 CIIPOLOCK
CBL1]2 CIIPBLOCK
CDL1)] CIIPOLOCK
CDLll4 CIIPBLOCK
CDL1]S CIIPBLOCK
CBLU6 CIIPDLOCK
CBL11l CIIPBLOCK
CDLll8 CIIPBLOCK
CBLI39 CAPBLOCK
CBLl40 CIIPDLOCK
CBLI4l CIIPBLOCK
CDLl42 CIIPBLOCK
CBLIU CIIPBLOCK
CDLI . . CAPDLOCK
COL14S CAPBLOCK
CDLl46 CIIPDLOCK
COLIn CIIPDLOCK
COLU8 CIIPBLOCK
COLU9 CAPOLOCK
CDLI SO CIIP81,ocK
CDL151 CIIPBLOCK
CEI
CIIPELKO
CIIPELKO
CEl
CIIPELKO
CE4
CAPELKO
CES
CIIPELKO
CE6
CIIPELKO
CEl
CIlPELKO
CEe
CAPELKO
CEt
CIIPELKO
CEIO CIIPELKO
CEll CAPELKO
cEta CIIPELKO
CEll CAPELKO
CE14 CIIPELKO
CE1S CIIPELKO
CEU CIIPELKO
CEn CArELKO
CEte CIIPELKO
CEl9 CIIPELKO
CPl
cr
CP2
CP
CPl
CP
CP4
CP
CPS
CP
CP1
CP
CP9
CP
cPlO CP
CPU CP
cPU CP
cpn CP
CPU CP
Cpt S CP
CPU CP
CP17 CP
CPU CP
CPU CP

cn

n.

n.

n.

..---

L--. . _ . __ ...

_~

Bl.1C
81. 2C
81. ac
81.20
8t. 20
81. ac
81.20
8t. ac
22.10
22.20
21_10
21.20
28 _4c
81.211
81. 2B
83.2B
83.211
83. aB
83.211
81.211
81.211
81.211
81.211
8).28
83.2D
81.2B
83.2D
81.20
8)'2D
8l.2C
8].2C
20.10
20.1C
81. ]0
n.]O
81.1C
83.1C
81.10
8l.2c
8l.ac
81.110

1

2

8t. ]C
81. 411
81.110
81. 2B
26.4C
9.3B
12.48
12.4B
1), 2B
22.20
22.10
2.411
42.2C
84.210
42.20
42.2D
3S.1C
42.2B
lS.1D
]S.1D
84. ]0
84 .1B
84.1B
41_10
41.211
12.2D

_ _ . _____ ._. _____

3

.~_.

II

___ .

DESIGNER:

SHEET
89

W~(fWf:il

[[ [~

,~U,
~
COMPUTERS
_.J

A

I

---·--9--·--·---·-··-----1-·---·

c

::J

APR/25/95 Manual

CROSS REFERENCE

OF
94

REV.
0.2

A
,.-.

1

2

-~--

~--.'

-

..

.....

CP20 CP
n.2"
H.2C
CUI CP
n.2C
CP22 CP
n.4e
CP23 CP
H.le
cPU CP
24 .4C
cP25 ep
H.1C
CP21 CP
18.10
CP28 Cp
18.10
CPU CP
2.21\
cno CP
cp31 CP
at.1C
16.10
CP18 CP
cp.O CP
16.4B
16.411
CPU CP
Cp42 CP
16.48
cpn Cp
16.48
Cp
CPU
".lC
CP45 CP
".3C
29.IB
cpn CP
29.18
CPSO CP
CPS7 CP
84 .28
CpGO CP
84 .2c
cPU CP
".28
CP52 CP
".18
cpn CP
84 .ac
84.28
CU6 CP
19.20
CPU CP
14.1c
CP70 CP
14.2B
CP12 CP
CP74 CP
31.4"
Cp75 CP
31.4"
CP76 CP
84.211
cPU CP
cpas CP
".2"
Cp81 CP
14.2"
84.20
CPU CP
CPU CP
".10
CP10S Cp
84.3"
CP108 CP
".31\
CP109 CP
".211
LEDDSIIORT 30.10
01
LEDOSKOIIT 30.20
02
28.3C
010D8
01
28.4C
OIOOE
04
OlOOETEIIH 17.30
05
OIOOETEIIH 1.3C
D6
OIOOETEIIH 12 .IB
01
OJOOETEIIH 1.30
08
OloOETERH 1.30
09
010
OIOOETEIIH '.10
OIOOE1'EIIH U. 20
Oil
DIODETEIIH 84.10
012
OIODETEIIH 17. 3C
013
DJODEZXXX 81..,.
014
OIOOETERH 11.20
DIS
016
OIOOETEIIH 12. I"
011
DlOOETEIIH 11.3"
DIOOE1'EIIH 11.38
018
OIODETEIIH 11.10
019
OIOOE1'EIIH 11. 2c
D20
9.28
OIOOE
021
20.IC
OIOOE
023
OIOOEZXXX 32.IC
02.
26.38
FUSEPTe
FUl
rUSEPTC
13.2"
'Ul
FUSEPTC
FUl
9.1"
11.18
11101 IND

H.'"

3

4

--------_.- ..• _--_ ..-----

-

..

_______ L____._____.___C_~ _ _ _ _L
__. ___ . _
____._____._.._0__.____
____ ·..__ _. .. _______
. __1.=>._________
__________. ...____
.

~--.-------

----~

...

IIID

12.3c
12.3C
20.2c
1110
81.3e
1110
81. 411
1110
11.20
IIID
17.2C
"8T125
1.3C 15.2c 15.)" 15.1C 84.18
SBH89CI00 1. 18 8.28
S8S89CIOS 1. lB 16. 2B
GIIL16V8
2.4B
VSI
I.IC 11. 2c
LCMOXX_P0100 L,C 19.18
118TI25
lS.1C 15.1" 15.1D
A8T213
30.30
OISlSEG
10.1"
ABTUS
15.1D 15.2D 1'.1C 35.4c
ABT245
15.18
3.2884.211
f"CT14
FIICT14
IS.1C 15.10 1S.2C 15.20 IS.3C 15.30

0114

FIICTI4

0115
.116
0117
0119
0120
J2l
.122
Jal
.124
0125
0126
0121
012.
0129
0130
0131
JU
JU
0134
0115
0136
Jl1
0138
0139
0140
JU
JU
.ttl
.1U
.14S
.146

LAH1IH79928 12.28
a.4C 15.311 IS.4"
F"CT14
LAHPTRAIIS 12. 2C
11.3C 84.38
fACTH
POWLVII
81.1"
I!PIIOHl165 19.10
fBPIIOM811J( 21.10
32.2C 33.4C
ABTUS
H.2C
"8T2n
CPUKB86904 2. 2C
Fl!PROHeXK 21. 20
20.20 n.2B 23.38
'IICTU
ll.lc
"8T125
n.3C 32.3C 32.3C
fllCT14
H.1C H.1C
1\81'125
SVSTL710S" 30.18
37.3C 31.4C
ABT245
36.1C H.2C
ABTUS
ABTUS
37. ac 31.3c
36.2C H.3C
ABT245
37 .2C
ABTU5
I\BTlt5
31 .1C 31.2C
H.2C 36.2C U.3C
ABT245
U.3C H.2C
MT125
H.IC 3S.2c
ABTZtS
H.Ic H.2C 14.4C
"BT125
118T125
14. Ie H. 2C H. 3C
118T245
16.2C 36.3C H.3C
ABT244
".2,. 44.3" ".3C
".2,. 44.3" 44 • .,.
MT2"
ABT125
H.le H.2C
H.lC 33.4C 35.4C
ABT125
H.1C 35.3C
ABTUS
ABTUS
32.1C 32.28 33. 3C
35.IC 35.2C
ABT245
RTCHI!UT08 28.1C
ABTUS
23.2C 2l.3C
42.2C
G"L16V8
A8TH5
35.2C
29.IC H.1C 19.3C
ABT2U
35.38
G"L16V8
F£PROH8XH 22.10
FEPROHBXH 22. 2D
24.2C
FH002

In

.. -.- ..... .... -

B

IND2
11103
IIID4
11105
IIID6
IND1
tNDB
011
J2
013
014
015
016
011
018
019
0110
0111
0112
.113

.148
0149
0150
0151
.152
0153
.154
0155
0156
0151
0158
0159

---.--.-.-~----.-

-

--~~---~--

INO

JU
0164
J6S
0166
0161
0168
0169
0111
0112
J11
Jl00
01101
01102
01103
01104
oliOS
01106
01101
0I10B
01109
01110
01111
01112
01113
01114
01115
JU6
J117
01200
01201
01202
01201
01204
01205
01206
01201
J20a
01209
01210
J211
01212
01213
J2U
J2l5
01216
01211
HlI1
HlI2
HHl
HH4
HlI5
H116
HIll
HlI8
""9
HlIIO
HIll 1
HH12
HHIl
HlI14
HHI5
HlI16
HH41
Hllfl

15.1" 15.10 15.20 15.30 15 •• " 38.1"

.-------- .. ---------- ..

26.30 84.10
12.4C n.4c

36.3C 36.3c

36.4C

35. 3C

--.------.-~.

-

..

-.-.~-

--

~.-.----

J60
0161
J62

1110

.. -.------

.. -.--..

_~._.

FH002
H.2C
15189"
23.3021.4024.3024.40
23.2C H.3c 24.3C
"8T125
III1TUS
31.111 H.2C H.3C
1\8T125
22.20 24.2c U.3c H.3C
FIICTl4
24.2824.3826.111 2S.28
18.2C
"8T371
1\8T313
18.IC
1\8T313
18.1C
20.2C
HAX1J4
118T245
15.1B
10.lc U.lC
"BT2U
COHSOCOJL14 20. ac
ORAHSPEZI 45. IB
ORAHSP£ZI 46.18
DRAHSpEZI 41.18
DRAHSPEZI 48.IB
DRAHSpEZl 49 .IB
ORAHSpEZI 50.18
ORAHSPEZ1 51.1B
OIlAHSpEZl 52.18
ORAHSPEZI 51.IB
ORAHSPEZI 54. lB
DIlAHSPEZl 55.18
DRAHSPEZl 56.18
DRAHSPEZl 51.18
OIlAHSPEZl 58.10
DIlAHSPEZI 59.IB
ORAHSPEZI 60.IB
ORAKSpEzt 61.1B
ORAHSPEZl 62 .18
OIlAHSpEZl n .18
ORAHSPEZI 54 .18
DIlAHSPEZl 0.18
ORAKSpEZl 66 .1B
ORAKSPEZl n .IB
ORAHSPEZl 68 .1B
ORAHSpUl 69.18
ORAHSP8Z1 10.18
DRAHSpEZI 11.IB
ORAHSPEZ1 12.18
OIlAHSpEZI 13.18
ORAHSPEZI 14 .IB
DIU\HSpEZI 15.IB
DIU\HSpEU 16.18
DRAHSPEZl 17.18
ORAKSpEZI 18 .18
DRAHSPEZI 19.18
DIU\HSPEZl 80.18
HOLE
85.3"
HOLE
85.3"
HOLE
85.28
HOLE
85.4"
HOLE
85.28
HOLE
1S.3"
HOLE
85.111
HOLE
85.1"
KOLE
B5.1"
HOLE
85.2"
HOLE
1S.2"
HOLE
85.4"
HOLE
85.2"
HOLE
85.1"
1l0LE
85.1"
HOLE
as.18
HII4
85.18
HlI4
85.18

-~--'-

-- ----------------.-.--- ..

Hlln
HIIH
111
112
III
114
115

H6
III
HB
H9
1110
1111
1112
Hil
PO
Pl
P2
Pl
1'4
1'5
1'6
Pl
1'8
1'9
1'10
I'll

PIOO
1'101
1'102
1'103
01
Q2
01
04
OS
06
01
08
09
111
112
113
R4
R5
R6
R7
118
119
1110
Rll
1112
Rll
Rl4
R15
1116
1117
1118
1119
~.-

..

..

~-

...

DESIGNER:

-_._-_._-.--.
--------r----·--·----------------r-. . __ A
_
_
B.

C

COMPUTERS
-

-.--

--

1

IIESIIV16S0 IS.IB 15.10 15.20 15.20 15.30 15.4"
19.3C 84.111
IIESIIV16S0 42.211 U. 111 42 .• "
IIESIIV16S0 42.1" 42.2" 42.2" 42.3" 42.'"
RESIIV16S0 1.18 1.107.20 18.4C 23.18 24.38
29.3B
RESIIV16S0 42.2" 42.2" 42.3" 42.4"
IIESIN16S0 1.10 1.20 19.40 23.20 23.38 39.10
29.2835.10 lS.48 42.28
RESIN16S0 1.20 18.3C 18.4C 23.40 35.18 35.10
35.20 3S.20 35.10 42.28 84.)8
IIt:SIN16S0 1.IB 7.ID 7.20 19.10 10.111 42.38
84.211
COIIVGZ"8CO_HIIPRO 39. IC
COIIVGZI\BCO_HlIPlll 40. IC
COIIVGZII8CO_HVME2 U .IC
cOIISBUS_FSOU 1. 2C 5. I"
COIISOUS_FSOU 1. 2C 4. III
COIIPCS4B_FIIPR 6. I"
COHPCS48-,lIpll S. 211
CONDSUBlS_fETH 1.111 14 .10
COllllALFpSO 1. III I t. 10
COmtALFP26_fSEIl t. 3" 25.1C
COIIHDIHB 1.1" 27.IC
COIISPROHlo04000 19. lC
COIIHODMO 43. 2C
COIIHODMO n.2c
COIIHOOMO U. 2B
COIIHOOMO 41.20
OUMZ506 12.30
QUOIfI'TLII 3.2"
QUMZS06 l'.IC
OU"RZS06 17.10
OUMZS06 11.10
OUOH'M'LII 11.411
OUOHCHOSPL 3. I"
OUOHCHOSPL 11.1"
QUMIZ506 17 .10
RESEO
15.411
IIESEV
30.10
RESEV
3.38
RESEV
28.20
RESEV
1.211
IIESEV
30.1C
IIESEV
3.3C
IIESEG
18.2"
IIESEG
lS.IC
IIESto
lS.1C
IIESEV
38.3"
RESEV
18.111
IIESEV
18.3"
RESEV
lB.3B
IIESEV
18.18
IIESEV
3B.3"
RESEV
18.1B
IIESEV
38.3"
IIESEV
18.30

-- .

.

'-'--------, . .-- ._.-_. -•.. - , .. ,.

~--.

- '---

---. ---_ ..

~[[E
_.-

85.10
85.18
IIESllVlfiSO 18.3C 24.28 24.38 2'.48 30.2" )0.2C
30.31\ 84.21\
IIESIIV16S0 42.2" 42.3" 42.41\
IIESIIV16S0 7.10 7.10 1.20
IIESIIV16So 1.1829.2010.2" 30.31\ 35.28 35.30
42.2" 42.31\ 41.30
IIESIN16S0 15.18 15.21\ 15.20 IS.2C 15.41\ 84.11\
10lt
IOU

.l\PR125/95 Manual

CROSS REFERENCE

---

.-

..

2

3

41

""

SHEET
90
OF
94

REV.
0.2

A
'--.

..-

..1

B

___.__ . . ___ L_~ ___ .

-.------~------

C

-

c------.--.--~--.

.-

.I . ____._________ .~. __. _. _____.___. . __ . '"

I

r--- -_ .. ---...- - - -....- . - - - - - . - - - - - - - . - -

1
I

1

f---

2

--

3

R20
1131
1122
lin
R24
1125
R26
R21
R28
1129
1130
Rll
RU
Rll
Rlt
R15
R36
R31

Al8
RU
1140
RU
R42
Rn
RU
At5
R46
R41
R48
1149
1150
1151
RS2
R53
R51
ASS
1156
R51
Rsa
R59
1160
R61
R62
lIS 3
IIU
1165
R66
R61
R68
1169
Rl0
R71
R72
R11
R14
R1S
R15
1117
R18
1179
1180
R81
R82
RU
II at
R85
1186

RESEY
RESEY
IIESEY
IIESEV
RESEY
RESEY
RESEV
RESEV
RESE
IIESEY
RESE
RESE
RESE
RESE
IIESE
RESE
RESE
RES!
RESEO
RESE
IIESE
R!SEO
RESE
RESE
RES!
RISEO
IIESE
REBE
RESEV
RESto
RESEY
RESEY
IIESEO
RESEY
RESEY
RESEY
RESEY
RESEY
R!SEO
RESEY
IIESEY
RES EO
IIESEY
RESEY
RESEY
R!SEY
IIESEY
RESEY
IIESEY
RESEY
RESEY
RESEY
RESEV
RESEO
IIESEY
RES EO
RESEY
RBSEY
RESEY
RESEY
RESEY
RBSEY
IIESEO
RESEO
RESro
RESEO
RESEO

4 --_._---_.-

R81
1188
1189
1190
R91
RU
R93
R94
1195
R96
1197
1198
1199
R100
11101
R102
Rl0]
R104
Rl05
Rl06
Rl07
11108
R109
Rll0
Rll1
R112
1111]
1111.
RllS
R116
Rll1
11118
Al19
R120
R121
11122
IIU)
R121
R125
R126
R121
11128
R129
IIUO
IIlll
Rln
Rll)
Rlli
R135
Rll6
R131
1113'
11139
R140
R141
R1U
II1n
R1U
R14S
R1U
11141
11148
R1U
R150
11151
11152
R1S3

38.1"
38.38
38.38
]8.40
38.28
38.38
38.38
38.]D
81.18
11.3C
81.3C
81.28
81.1D
2.2"
81.18
38.2D
81.4A
81.28
l'.3D
81.1D
2.2A
7.1D
81.18
2.2"
81.1D
1.3D
8LSD
n.1D
11.]0
14.20
7.18
1.2D
1.18
1.3D
1.28
1.28
1.28
1.28
".10
1.2D
1.2B
12.18
1.28
7.28
12.18
1.2D
1.18
84 .20
7.28
16.1D
84.1D
16.3D
1.2D
11.3C
16.3D
11. )C
7.3D
1.1D
1.38
1.18
1.38
1.2B
11.20
l1'lC
11.3D
11.2D
12.1"

..

----~-.--

..•

----' .. _..

_

........ _.. - . . . . -

...

RESEO
IIESEY
IIESEY
IIESEY
RESEY
RESEY
RBSEY
RESEV
IIESEO
RESE
IIESE
RESEO
RESEY
RESEY
RESEY
liES EO
IIESE
RESE
IIESE
RESEO
RESEY
RESEY
RESEV
RESEO
REBEY
RESEY
RESEY
IIESEV
IIESEV
RESEY
RESEY
RESEY
REsEY
RISEY
liES!
RESEY
RESEY
R!SEV
IIESEY
RESI
RESE
liES!
RESEO
IIESEO
AESEY
RBSEY
RESEY
IIESEV
RESEY
RESEO
RESEO
II!SEO
RESEO
RES!
RESE
IIESE
IIESE
IIESE
RESE
RESE
IlESE
RESE

lIEU
RESE
RESE
RESE
RESE

11.4"
12.18
11.20
11.38
11.4"
l'.]C
11.28
11.3"
81.28
81.28
H.2c
19.1C
31.4A
11.4"
11.41\
n.48
".10
... ]D
".4D
37.4D
84.2D
84.18
".lC
20.2D
12.4D
84.28
u.]C
U.1C
12.3C
32.]C
".18
84.28
".28
32.3C
35.3C
32.38
U.2D
n.28
22.28
U.3D
44.4D
U.4D
14.48
32.4D
18.4C
22.3D
32.18
n.2D
32.18
44.4"
35.48
36.4D
19.3C
2l.4C
24.4C
31.10
24.1D
26.1C
a6.1C
26.18
26.3D
26.28
26.18
3.28
12.2C
12.2C
12.2c

--~~--.----------

..

--.-.-----.--------~.-

R154
R155
R156
11157
R1S8
R159
R160
R161
Rl62
11163
R164
RUS
R166
R161
R168
R169
R110
R111
R112
Rl13
R114
R11S
R116
11111
II11B
11119
R180
11181
Alsa
R183
Al84
R185
R186
Rl81
R1U
R189
U90
R191
Rna
R1n
11194
11195
R196
11191
Al98
R199
R200
11201
R202
11203
11201
R20S
R206
R201
11208
R209
R210
R211
11212
R213
R214
R215
R216
11217
11218
R219
R220

.

--_.. ---

--

RESE
RESE
RES!
IIESE
RESE
RESE
RESE
RESE
RESEG
IIESE
RESE
RESE
RESE
RESE
RESE
RESE
RESE
RESEO
RESE
RESE
RESE
liES!
RESE
IIESE
IIESE
RESE
RESE
RESE
RES!
IIESE
IIESE
IIESE
RESE
IIESE
RESE
R!SE
RESE
RESE
RESE
RESE
RESB
RESE
IIESE
RESE
RESE
RESB
RES!
RESE
RESE
RESE
RESE
RESE
IIl1SE
RESEO
RESEO
RESEY
RESE
IIESEO
RESE
RESEY
RESEY
IIESEV
RESEY
RESE
RES EO
RESEV
IIESE

12.]A
12.18
12.2C
12.3C
12.3C
12.3C
12.3C
41.1"
'5.10
3.18
42.2C
20.]C
20.4D
21.4C
21.4C
21.28
21.18
18.3D
2.48
2.4D
2.48
2.48
2.48
30.S8
30.1D
2.4D
2.48
10.lA
2.4D
30.S"
30.1"
30.18
30.S"
lB.1C
30.18
H.2D
11.]8
11.28
11.3D
11.38
11.3D
11.]8
11.38
11.3D
38.20
11.38
11.28
11. )8
11.2D
11.18
11.28
11.3D
11.3D
2.2D
a.2D
".18
81.28
2.28
17.1D
2. I"
2.aD
2.30
2.20
11.28
29.1D
2.28
).2C

R221
R222
11223
11224
R225
R226
R221
11228
R229
IIHO
R211
R212
R233
R214
R235
11236
112)7
RH8
IIU9
R240
11241
R242
IIH3
R2U
R245
R246
112.,
R248
RH9
R250
R251
R252
R253
R254
R2SS
11256
R2S1
11258
R259
R260
11261
II2U
U6'
11264
R26S
R266
11261
11268
11269
R210
11211
R212
11213

11214
11275
R216
R211
R218
R219
R280
R281
R282
R283
R281
R285
R286
R281

-~-.-.-

'-----

DESIGNER:

RESE
RESE
IIESEY
IIESE
RESE
RESE
RESEY
RESE
RESE
RESE
RESE
RESE
RESEY
RESE
RESE
IIESE
RESE
RESEY
IIESE
RESE
RESEG
RESE
IIESE
RESE
RESEO
RESto
RE9EO
RESE
RESEO
RESE
RESEO
RESEO
RESE
RESE
RESEY
IIESEO
RESEY
RESEO
RESEY
RESE
IIESEY
RESEY
RESEY
RESE
IIESE
RESE
RESEY
RESE
RESE
RESE
RESE
RESE
IIESE
REBEY
RESEY
RISEO
RESEO
RESEY
IIEBEV
RES EO
RESE
IIESE
RESE
RESE
RISEO
RESEG
RESro

11.28
30.10
18.4C
30.10
30.1"
30.10
11.2C
1.2c
10.2C
10. ac
30.1C
10.lD
20.18
18.20
18.1C
38.1C
11.2D
l'.3C
]8.1"
2.38
11.4"
38.1C
]8.11\
11.28
2.'"
31.4"
S9. )8
38.2C
U.1C
lB.2C
2.3"
2.4"
38.1C
38.2D
2.1A
11. 4A
a.3"
lS.3D
2.3D
n.1C
19.28
lL2C
22.3"
83.10
28.3D
83.10
10.2C
15. )0
20.1C
15.20
15.10
83.10
83.1D
21.211
21.28
3.1C
29.28
29.18
29.28
19.4C
81.4"
12.1D
12.28
12.1C
12.2D
32.2D
12.2c

I

1

I

21
I

I

I

3

4

-._.-.-_._--- ._------_._--_.-. ---'-"'._- .
~-.-------

SHEET
91

-.----... - ------·-·----·-·-A·-·--·

··-----·----r---- -'-·-'---'8-- -._._--._- -'---r-' -·-----C---

f~f~"'I[ [f~
'':::=::--/

~

____ 1

COMPUTERS

..:.::=.l

APR/25/95 Manual

CROSS REFERENCE

OF
94

REV.
0.2

A
---------

1

--

2

I

B

___________ .L________

c

_____ .J ______ .____._______._P__________________.. __

Rna
R289
R290
R291
R292
R29l
R294
R295

RE9£0
29.1B
RESEO
29.1B
RESE
19.1c
RESE
n.IC
RESEO
82.2C
RESEO
82.2C
RESEO
82.2C
RESE
33.40
R296 RE9£
n.2C
Rl97 RESEO
n.2c
Rl98 R£BEV
n.1C
R299 RESEV
42.4~
R300 RESE
34.1B
34.18
AlOl RESE
R302 RESE
14.10
R30] RESE
34.1B
R304 RESE
34.28
R105 RESE
34.1B
R106 RESE
H.1B
R107 RESE
32.2B
R108 RESE
12.1B
R109 REBE
12.1B
Rll0 RESEV
n.1C
Rlll RESEV
n.lc
Al12 RI!SEV
az.IC
RJll RESEV
n.1C
Rllt RESEV
n.1C
R1l5 RESEV
1!1.4B
RlU RESEV
35.4B
U17 RESE
U.2C
Rl18 RESE
n.1C
RUg RESE
RUO RESE
42.2C
n.IC
R121 RESE
17 .2C
R122 IIESE
STU STIF137F3 n.IC
liT 12 STU21HAl 85 .11>
]O.JA
SHJ_Tf'l'
SHI
]0.4A
SH2
SHLTFT
SWl
SWIROTDILS 30.2B
Slit
SWSHD12R04 1. 3~ 2. 4~ 24. 2B 24. 3B
SH5
SHSHD12R04 1. l~ 19.1C 2J. 2B 2J .1B
SHSHDUR04 10. 3C 11. 3D 21. 2A 22. 2A
8H'
S\f1
SHSHDUR04 10.2A 10.lA n .1B 32 .lc
SH8
SHSHD12R04 19. lD 19.1C 19.4C 10.2A
SCSITERHTI U. 3C
Tl
T2
SCSITERHTI 1l.2C
SC91TERHTI 10.2C
T3
T4
SCBITERHTI 10. 2C
TRAtISINPH 32. lD
TS
T6
TRAtISIHPH n. ac
T7
TRAtISIHPH U.2C
T8
TRl\NSIHPH U. 2C
nOl CODIERUD '5. 3D
ZFo2 CODIER"D 85.20
no) CODIERl60 85.10
ZF05 FROlnPMlEL IS .1B
zrOG IDEln
85.1B
nOl IDENT
85.IC
no8 HANIIAL
as.2C
UCDI PCBDOPEURO 85.10

1

2

u.ac

--

3

. --

- - -..

~-----

3

--------------

4

4
DESIGNER:

L...-. _ _ _ _ _ _ _ _ _ _

A··-·------ ·--------r-~-----______a---·----------I----·-

C

-

ffi?r:/[fe
COMPUTERS

_ _ OM

••••

_ _ ••••

APR/25/95 Manual

CROSS REFERENCE

SHEET

92
OF
94

REV.
0.2

r-------~-~-

A

~_._.-_-_~

_ _ _ _----,---L--_ _

B~=__=__

__ ~___________ J~. __ .____ .___

C

._ _ _ _ _

L. _____________ .__.___ Q. ___ ._______ ~ __ ..._____.___ _

HISTORY FOR SOURCE SCHEMATIC CHANGES
Chonges from CPU-5V Revision 0.0 to Revision 0.1:
(File: .. I .. /doc/changes/history_0_1)

1

--~

Standard serial PROM connection implemented:
-> serial PROM cyyntef reset
Ch8~~::to~e*H8~ij J~~b e

~gg~~~~n~~ ~Ao§~.cS installed.

Signals EB_A<21~.20> driven by LCA for Flash PROMs.
Changes on SH , J68. SH 18 J6.
CAS<2> and CAS<3> swapped and CAS and CAS swapped.
Changes on SH 1 J2s.

MIN_LINE_WIDTHcO addet to VHEbus signals.
Changes on SH 31.

~~~~~~sa~g ~n<~6J2~wapped for HACIO.

~R!~;e:n~~r~a ~~~o schematics.

S~_PA<}5>hSBSPA<20>

Replace LTI085 3V3 with LTI085 ADJ.
Changes on SH gO J20, R96, R21U.

~g~g~:~ g~ S~ iOJ~~7S~n ~B ~5g, ~~oYi Jg~, 8ftti~ gSap{:~~ons.
Boot Size Switch CQnnected with correct LCA pin:
Changes on SH 18 J6.
PI00 and P10l exchonged with P182 and PI03 (height).
Changes on SH 42 P10 , P10l, P 2. Pl03.
position of LEOS Ll and L2 exchanged.
Changes on SH 29 D .

~~:~ge~eg~a§Rd8~i~n r~;sSH 25.

3

Signals EB_D<3 O> connected with LCA instead of EB 0<7 .. 4>.
Changes on SH 1Au J6.
DRAM Data Bus Dulled.
Changes on SH ~2.
SYSRESETin through LCA to FGA-SOOO.
Changes on SH 18 J6, SH 30 JS.
SYSRESETout from LCA in oddition.
Changes on SH 18 J6, SH 31 T1.
8Y8RESETout driven by 3 transistors
Changes on 8H 18 J6, SH 29 J31, SH jo J5. SH 31 J49.
~sg~g!: ~~IS~E~~'J~~I_TESTASYNC and VSI_TESTSCAN pulled up and down.
Signals ACFAIL SYSFAIL, SYSRESET, BBSY, IRQ<1 .. 0> glitch filtered.
Changes on 8H A~l, 8H 32, SH 33.
~h~g~e~~~u~Hc~~ector PO pins disconnected.

--

~h~g~e~~~u~Hc~~~ector Pl: Z only GND, D disconnected.
~h~~~e~~~u~Hc~~ector P2. Centronics: Dl .. D19 shifted to D3 .. D21.

address lines connected with CPs.
Changes on SH 31.
GNO for serial interface connected with hybride GND.
Changes on 8H 24.
Additional SMD footprint for Q6, V8I_CLK: QUOM Q8.
Changes on SH 16.
G~ographical

4

1

gg!~~e~eg~t~HnlB~ ~~b~~.signal BERR· when not being VHEbus master.

Signrlh-iTCG_R§T, liTaGaTMS. iT~G~JLK, ~TAG~TDI_TDO<4> pulled
gga~g~s og Sftn01 P".e
own w t
R (3 R N .

SB_PA<26> connected with the correct
~h~9~S ~neSHB~sJ~?~RC~o~~: SH 5 P6.
SP SEL<~ •. O> generated in PAL.
Nore: Tie tignals namea ~P_S~L in the !chewrtic ravT been renamed

2

Disable VBERRI-Qnd VRETRYI when not being VHEbus master.
Changes on SH 18, 30, 34.

~R!~~g: g~v~RiBs.resistors for 3.5V changed from 0805 to 1206.

~~~ge~'~n6~Ha2~~rtion delayed.

~~1~~:sr~~0~Rdi9 J10, D22, R164.
Quom 80 MHz is used only for FGA-5000, J18 (FACT14) removed.
Changes on 8H 16.
Clock siinal for SCSI generated with new quartz Q9 instead
gha~~~~10n SH 16.
Signal ENET TCLK used for SLAVIO signal TIM_CLK (10 MHz).
Changes on SH 7, 83.
MIN_LINE_WIDTH Qf quartz signals changed from 8 mil to 10 mil.
Changes on SH 16.
Signals ENETnTCLK ~nd ENET_RCLK terminated on the destination end.
Changes on S 11. 16, 03.

2

Chonges from CPU-5V Revision 0.1 to Revision 0.2:
(File: .. I .. /doc/changes/history_0_2)

3

~~:ng~I~~3SHoI.added.
~S:~g~.~~e~~ y~mber updated.
~~~Ag!sP~gM8~cl~3~2I~placed with XC1165.

~fi~~~~~oo~0RneI~eg6~ith LCA.

~~~~ge:dg~dshn1~r~~ ~,s~~o~~, t~~~~.overtone crystals.
DRAM_CODE_A connected.
Changes on 8H 29 _ADAPT_DRAM_CODE.
AM3VSI controlled by AH3VHE, VIACK and VHADIR.
Changes on SH 35 _ADAPT_AHIA, SH 42 J53.
History updated
Changes on SH 9 j .
DESIGNER:

SK

r

Thu Mar 23 00,09.42 1995

ff'J-2
I \\~~ .~ _~ ll~~
[
1

L-..~. _ _ _ . ---·-·-------A - . - - - - -·---r·---·----'--B-~----~-r---------C--

COMPUTERS

4
_.D.I~lWU.N~_

ABBREV=HISTORY

APR/25/95 Manual

HISTORY

SHEET

93
OF
94

REV.
0.2

r------------.

A

B,

---~=_.=I__________

._____~ __I__________ ~ ___________ _

C

HISTORY FOR SOURCE SCHEMATIC CHANGES
Ch~oges

from CPU-SV Revision 0.1 to Revision 0.2:
(File: .. I .. /doc/changes/history_O_2J

1

Bus AMIA<3 .. 0> added.
Changes on SH 1.
History sheet number updated.
Changes on Sit 1.
Serial PROM XCi736 replaced with XC1765.
Changes on Sit 9 J21.

1

~~~KS!~Oo~0~eI~e36~ith LCA.
PC rts added Anl~rd~r t~ ~uPR~~~ th~id oV~jtone ~rystals.
83~nR~~1?nR~22, C~~: ¥N6§:
' R 7, C , IND ,

g~g~gD~~sft>2~o~gK~¥~DRAM_CODE.
AM3vSI controlled by AM3VME, VIACK and VMADIR.
Changes on SH 35 _ADAPT_AMIA, Sit 42 J53.
SYSRESET ip prohib~ted with an additional transistor and
rpsistor when the oard is not a slot 1 dev ceo
Changes on Sit 32 T , R97.

2

~C~~g:~do~ngHm~»sR2tieR~g8"R~~~~ with VMEbus P2 by default.

2

Resistors fQr JTAG chanaed.
Changes on Sit 82 R313 R296.
JTAO daisy chain closed.
Changes on SH 1.

~g:~g~~ro~a~He4~hft~~3~ for RAS timing.

gCC~g~~0~nr~woxtdCE13.
~g;~g~sfg~ »~C2fihSg~~d.
Sockets for OALs added.
Changes on SH 2 J4, SH 35 J56.
PCB changed to Rev. 0.2.
Changes on SH 85 ZF04.

3

~~!~~:~e~nb~~Y8§h~¥¥t~·

3

pcrameter name chang~d: SB~SELECt Inst2ad of SBSSLgT.
~Ha¥g~ssHnlB~ ~fi f~, ~ItSYl.' SH , SH . SH 7. H •
Switch SW 4-4 is connected with Select GAL.
Changes on Sit 2 J4, R252, R213.
Switch SW 5-4 iv connected with LCA.
Changes on SH 19 J6, R98, N6.
History updated!
cfianges on SH 9Q.

4

4
DESIGNER:
Hon Apr

L...---------·-----

x-,

J

. P.MWING_

~rFQFj)
[C IE~
~_.. ~

u
---·--B-------··--·----r--··---c--

SK

1 08:12:55 1995

_.,1

COMPUTERS

ABBREV=ItISTOR'l

APR/25/95 Manual

__ ;:I

HISTORY

SHEET

94
OF
94

REV.
0.2

Circuit Schematics

S.1

Page 176

cpu-sv Technical Reference Manual

MEM-S Schematics

FORCE COl\1PUTERS

A

_~ ______ L

B

c

- - - - -___1 ____________ ~_..P ________________ .

1

1

2

._-

r ....;;:;....y...1
......

lr

LOCINDBX.I00
AODRBSS_BUS.O

HAlLROW.O
HIN_ROW.O

H,.'LROW·O
HIN_ROWcO

WD_PBR_ROWaa
ROW_MAX_WOal
ROW_HIN_WO a 0

WO_PER_ROW=2
ROW_MAX WO a l
ROW_HW:WOoO

8IT_PBR..WO.l6
WD_MAX_8ITal5
WD_HIN_BITsO

~~T_PER..WD.l6

MAC

1IRR
-""
-CONN

;YM~ •

2

WD~N~~I;!~

BIT_PER_CHIPa4
CHIP_TYPEaORAH4H4R4
SPBEOa10NS

CHIP TYBITp.loER_CHIpa4
1U\H4H4R4

_

_zMI¥'Y

OHM CONN

3

LOCINDEXa200
ADDRESS_BUSaO

<0.

I ';;~
r·
-"lMlIJ'M

MAD

_"ULI

_"rJI_3

cYMEIRII'
_OM

3

60 NS DRAMS EINTRAGEN!! I

4

:t~2CBLJ~~l"~C:tCj~~-"~L"~r"j~6CBLXCBL~
":LCYTrB:rj~
-.lIlm
..
-:Jm
liIm
-~- ~ -~ 1rtm~- ~

-~.

;J;

~ -~-

-~

__

~ ~- ~

C'8CBLI6CBLIACBL,2CBLlacBlIByCBLrTBrBrr"j~r':B~r~Rrsr~~

:~:~::r.:~-::.
A

-* ~. -~ lilm ~ ~ Tilm ~ .- -. -~ ~ ~ -. ~
B

-----,

c

4

DESIGNER:

SK

Thu Aug 18 13,29,38 1994

~[[E
COMPUTERS

.J>J!AWIN!.1_
ABBREV=MEM5V2B
MAR/21/95 Manual

MEM5V2B

SHEET
1

OF
39

REV.
0.0

A

B

.___ ._ _ -'

___ L. _______.__ .___.____ ._D _ _

C

MIM3

J:

(w.~

__ l_.

Mlt44

t 11

(~.. L ..

1

MH4i
(~.J... _.

MH42

CP3

l~-·J..-··

s
o

2
Pi

2

)0

CON

VALUE=SMD

!iQPA60=

---

3

3

:_AoAPT_MEM_ARlt i
I
~'_'''I.tt.l~'IU1
I
I

r--'1 ;!!~~:f.'AAY_8U8
I

i
4

!
I
I
I

HABUSI\.DDR-l
HA8USAODR_3

I

to-

r
::~:~g:t~;-

NCjA<11

::~:-~ r

NC; WE

HABUS_DATA

I.

,Q>

4

NC' RAS<'7 8~
Rc!CAS

HABUS RAS:
HABUS:CAS

.
MEM ARRAY BUS<499" 0>\1

F NC
-I-__
D:.,.;<...7..1...,....,....3...6..:;>;"",._ _ _ _ _ _ _ _ _ __

DESIGNER:

\~ ...
D:.;:<:.oi3~5r""...,.,J,Q">:..-_ _ _ _ _ _ _ _ _ _ __

~[E

PIJ\T_ORAWINO. ORH_COmC2, LOOIC, 1. 1
INSTANTIATION. IHEHSV2B ORH_COmI22PI

A

-------

13----

------1

SK

....D.BJWUtID_

Thu Aug 18 13.30.10 1994

C

COMPUTERS

MAR/21/95

ABBREV=DRM_CONN

Manual

DRM_CONN

SHEET
2

OF
39

REV.
Q,O

-----

A

B

FROM CONNECTOR
ARB

MEM

CQNN<499 .. 0>\1

-~__

L___ ._~ __.____ _.12 _______ _________ .

C

(_ADAPTjiEl'U\M:

!_ADAPT_MEMJ\RR'

I _HeH...AARJ\Y_BUS

i
I

I

I(O'~ ,,,t.Il\.'MI ..n

I •• " .. 0.

~

HABUSADDR_l ~

"ABUSADDR_O

_HeH_ARMY_BUS
.Ut .. 0. ,

TO DRAM
MEM

2

DBM<499. O>\I

-I HABUSADDR_l

NC; A< 11

0>

~8! ~~<~ ~ B~

H~:~~i~~: _;<
~
NC ' WE

HABUS RAS:

.~D'_l ... U.Jt.\JM.ltn

f

I

::~:~g::~ C
I

1

-~~---

:

"ABUS_WR !

H1I~US~DA~A I

=

Ne! B HEH A< 12. 0>

@. MA

:J ~~:~=~gg::~

. MABUSADDR_O

ee(S+; :s i

HABUS RAS

M

,.

1

l~~:~~:g~s

~! ;:<~>

, "ABUS_WR

HABUS_OATA

33R!t--~~1I1L11IDLQ_EPSG

.

'.

,_ADAPT_MEM_ARR:
_HeM_ARMY_BUS'

J~

2

B III!K Aell>

l-E'a Nl-,'-""0<'"
-

1\

DR

12>

~ '; ~:

11>

:

@'@A

... HABUSAOOR_3
~ HABUSADDR_2

c." ..01> :

HEM 3 DBM<499

0>\1

~ ::~:~gg~~

".

2

~ :!~i~~S

!

HABUS RAS

HA~US_DATA

<15 •• 0>

9>

lL.____~_
__

\0

fill

3

ell -;r-J~r-~r--;r-;;l~J cll clJ cl cJ~
T20T
10l6frbJlkJOT-L~~~J';
l=~JoNIlOTttl
iJON.JW
ruON 20T
ruON__ 20T
20T
ON OT

\0

rl

M
.-~~-.

~

~~.

.~~~-,,_

k1>

rill

[:: ~

ruON_20T

__ -_t=.~l>

etB3f'-......
- 0>::----

2>

J1.. ___ .....L~~~d.

-1<1>

~

ea3~L::

WE

ON_20T CpfOON_20T

J1

~~

Al -

()

,

~--,l;c-----(>

~~ -t=---==

Yl

~4 •• Y4
'~P

-l-=fi.·H

B RAS 3

R-

---~----....--r--=--':_-·_---_-_---S..2.:cp..:.:.o:l.g<::..31LJ-'I,.I··1~2.:::.~

----- -.::::.l.hrlolt-----------··w.'>--·

UIN-~I~I~IBi":§
MIU:LINE:WIDTIt=B

3

MIN LINE WIDTfl=8
HIN:LINE:WIDTH=8

§f:--F~ll1L-- ----------------.. ---·If-cRJIBP!~J.~ij~
.-~----- ~l8IC--=~=-==.::~][>-j -----__
L

b

lJI--r~ o~

~uON

roON_20T

MIN:LINE:WIDTH=B

11'1

0>

4

'"J

[-'NC'B MEM A<12

0>

4
DESIGNER:

33M

0iTh_UEN1U1~.tLt)l!f-! ___ _

--~_-J

--~-.---~-----------

ftlR[E

FLAT_DRAWING. MeM...AARJ\Y_2B1C_l. LOGIC .1.1
INSTANTIATION.

(HI!H5V2D HI!H_ARRAY_2D70PI

A

B

-----

SK

Thu Aug 18 13.29.50 1994

c

COMPUTERS

.J2IY\WIN~

ABBREV=MEM_ARRAY_2B

MAR/21/95 Manual

MEM_ARRAY_2B3C

SHEET
3

OF
39

REV.
0.0

_L

__ !!_____

-----

B

_______-=-=-==~~

____.l_____.____

~__

~_.

______ .___________ .__!J_____________ ._____._____.

1

1

$LOCATION=J4

I

UEH
A:>
EM A<
_:MEH:"A< >
~HEM

. ----.---------.--.. . -----

_ _ _ _ _ _ _-..,.;.-1

il~9

A<8>

AH8

IU!.EIL~________
B
..A<6>

AS6

HEM~
-~---.ILMt:..!i..A.'S.f>
It-HEM

A<~>

I~8

A6

~~5
~i4

T SOP

F

P_t1'~JoLA.

s

: 1S-----------p..'SQ.
D

lOS , S
10. -

"

IOS3 •
IO~ •
•

lOS

~~6

ILMEM A

la(,,~"'

~~4

___

IU1E1LA~

__ .____

•
,
,
•

RASS.

C~~:

~8°

D_l1ID'LA

lOS
10
lOS
100

TSOP

~~2
~~l

ILM~M_t.~l~_

1'

10

ASS
AS

ILl-.lEM A<4>
JLtmM...A~~

~~8

A8
AS?
A7

IUWL~~---D MEM A<6>

2

Ap
A 0
AS~9
AS

CAS.
WRS.
WR.
OES.
OE.

XAlg

~R~

----~~~
____
D<~

____Jl~~
D<4>

B

RA~3>

B

CAS~A~

2

B MWfi
ENlLM.gjLm:

DRAMSPEZ2

B MEM A<3>

s~E~uE..slJfD

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

11
DESIGNER:

IV

Thu Aug 18 13,:19,39 1994

f{]R[[E

PLAT_ORAWINO, OAAH_CHIP_S _LOGIC. 9.1
INSTANTIATION.

(HIlH5V2B DRM21pll DIVJCCHIPJPI

A

B

----------c----

COMPUTERS

DR1\~lNG

ABBREV=DRAICCI1IP

HAR/21/95 Manual

SHEET
S
OF
39

REV.

DRAM_CHIP

0.0

..---- -.. -----

A

I

----~

B

C

J___.___ .___.__ .__ ---.P_. ___._____ .___ ...... _

1

1

$LOCATION=J7
-.-

.

1:i1IU=lU~~'~.~.< >

.

ILMIDL~<8>
1Lm;~

A<7>

D HEH

~~

B HEH A<2>

li:

1! i=~ ~17

Iqg~ : :1l~1

ILMJ1;W A

ILmttL~>

_._-"

-

~
10 <.
los8

10 <
__

cl!=r

t= r-t!fi=

>-

____ ._

IU1mLb~~

._-

_~2 t=

A
A 6
A!
AS5
A5
8
A~4
LlL A

B HEM ~<...4>

DJ1E.!L~~l~

A10

s

ILMf:1l....A~~

2

t-''Ail--------

.. -,rf-

l~~r-- ASS9

llll'~'

"

_~
~2
TSOP
L
~yl
~~: -rt=b:=

------?id=-

AgO
A

CASS

B RM~.32:
B

< ~ij;;=!

~~~: ~~
WR. \~~
O~~: }.~.LJ

CAS<~>-

.

JLX'DRAMSPEZ2
~~t~

2

ILM~j;

~H.ILI1~~

SPEED,:,"J"S,ftEjD
VALUE= H

3

3

--

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:

IV

Thu Aug 18 13.29.41 1994

PLAT_DRAWING, DRAM_CHIP_6. wole. 9.1
INSTAtITIATION.

IHBH5V2B DRH21P12 DRAM_CHIP3PI

----~------A~-------l----------B--·-·

-I

.------- c -

~ OR.[[E
COMPUTERS

.J!AAJll.~.G_

ABBREV=DRJ\M_CHIP
HAR/21/95 Hanual

DRAM_CHIP

SHEET
6
OF
39

REV.
0.0

A

B

r-------... ------~------

.------~--.-----.

L

- - - . - _... -

I

C

.---~-.----

- - - - - - - .----.------.------- ..

D

1

1

$LOCATION=J8

WW=·· . -.--==~---.----

~~~9

~<8>

~IB

D-MEM A<7>

~~7

""-'-"~"__.

_______~______

ILt.,~~_>______
ILMEIL~.5.>__

2

____________________

P.5JJi~

T SOP

MSS.
RAS. ~Ii2B4;
CASS •
CAS.
.

AS'
Al
ASO
AO

" MEM A
J\~

18(\".

~~2

ILMElLJ\~t.L..._
__

~~5

~~4

ILHElL1t<2L-. __ ._

.
_______
I¥8i : Jfj-----------f!~.L42!
I¥81 : -1-2 :1---__ ._.P~U~
I~g8 : -~L1---....P~la.~

I¥g~

~H6

_ __ .___

!U1~M A<4~

~~H

U~

XA10

~~~3

2

B RJ\.S~.~
~~

B

~e!: h2.=-------~N-;. MEM~
OE. J~

DRAMSPEZ2

,,~~3>

S~.aoUJi:!.rfD

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:

IV

Thu Aug 18 13.29.43 1994

~[lE

FLAT_DRAWINO. DRAH_CltIP_7. LOOIC. 9.1
INSTMITI~TIONI

(KEK,)V28 DRI121Pll DlWCCHIPlP)

.A

l-~-~-.

-·---B-·------r---····

C

COMPUTERS

~I!A.WING

ABBREV=DRAM_CHIP
MAR/21/95 Manual

SHEET
7

OF
39

REV.

DRAM CHIP

0.0

_ _ _ _ _--=-A=--------__

___~_==C

B

C - ] _________________ ~ ____________ .

1

1

$LOCATIONo:J9

I

Ail
Alo

MEM A
~ C
2>

aR~M ~~~>_____

!1~9

!LM!'-~..A'.• '

B MEM A<1>

D....HID-L~<6>
ILH~>

21

B HEM A<4>

D HEM A<2>

P-"l!L.ll6l>...~

B_HEM_A

1Lt1~~1~

IL.M_EJi...M;l~_____

-----

~H·

M76

lOS

t2

A~5

I~3

10

li

4

t~2
Rfl

A80
A
XA10
XAS3
XA3

I~31

'80n •

I~88

TSOP

'I::
I
s

•
:

"AH :

CASS •

~~~:
WR.

-

OES •
OE.

D<",

~18>

~

1~

D<

I2

>

B RAS

B....QAS~~

B

~

ENA...MruLQE

DRAMSPEZ2
S~~uJ';;IJfD--

3

13

t----

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:

IV

Thu Aug 18 13129.44 1994

PLJ\T_DRAWItIO. DRMCCHIP_8. LOGIC. 9.1
JtISTIINTIATIOH,

IHEH5V28 DRK21Pi4 ORAtCCHIP1PI

-----,;:---------r-.-.-·-------s-----------,---------C--

f{)C~[[E
COMPUTERS

..PMWJ.t'lQ_

ABBREV=DRJ\~'-CH I P

HAR/21/95 Hanual

DRAM CHIP

SHEET
8

OF
39

REV.
0.0

B

A- - - - - - - - -

--------.- .-

C

-~.-----------

_._---_ ...

-----~--

D
.. -----.------.---... -----------.- ..

1.

1

$LOCATION=Jl0

-r-------

__----

frilff:i~"~-

Uo
AS~9
AS

B MEM

A:~_~

_____

~~---~--------JLMEM A<6>
B HEM A<5>
P_MEH A~~ ______

2

ILMEH A<2>
DJ1IDlA.< 1> _ _

__

105
10
lOS
10
10Sl
101
lOS8
10

~i6
ASS
AS

la<;!"

~~4

______

,
•
•
•
,
•
,

0<22>

_ _ _~U~
D<4tQl:

TSOP

RASS.
RAS,
CASS.
CAS.

B RA..J35.J~

OES,
OE.

ENlLMgtLQ~

XA1~

~~~

DjiJ1;..!LA..

1'

~~7

R~2
~il
R~O

IUIEJLl\~Q>

tlJ1IDiA<10>

liS

2

B CAS<_?2:
B

WRS.
WR.

2

m1f:

DRAMSPEZ2
S\f~u1..s1JfD

I

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:

_ DRA\fLti

81
Ai 8
W~ A

""

IUiEM A<7>

-.!f t

ILMrut..A~_>_ _ _ "

~r:;;
.

r
811

~.M..A<1>

l.su-

-q}-

________~_.

~.!LM.9~

19l' =h=!
11-1

10
• ~H=J
10 •
lOS.
10.

ff--

-e::::

P MEM A<.2_>_ _ _ _ _..___

'8

t~4

(:"

ILMEM-.A<10>

--

P.Jf..,gILA.< 3 >

2'

.----------.l2~ __ ~
D 24

<_""_~

TSOP

A~2

~rl

RASS. 114
RAS. ~
CASS. S
CAS • ~
WRS. ~

A

A~O

T=xL A

_.-

D<~.§~

iP

L;;-. AS

B MEM A<4>

D

2

rnr---------

oBi:

m~

XA3

2

JLMS<3>
B CA~~~
B mJE
.__

b'::!---- __ ." ___~t:lAJ.mM..QJ;;

DRAMSPEZ2
S(~,t}5?u"J=sIJfD

3

3

--

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:

IV

J>MIDJill_
ABBREV=DRAM_CHIP

Thu Aug 18 1],29:47 1994

fOJt:~[IE

PLJ\T_DAAWU\Q. DlWCCHlP _10. LOOIC. 9.1
ltISTlIlffJATJON. 'HI!H5V2B OIlM21PI6 DrWCCHJP1PI
L _ _ _ _ _ _ _ _ ._._. _ _ _

A

---r--

B

I

c

COMPUTERS

MAR/21/9S Manual

DRAM_CHIP
-

SHEET
10
OF
39

REV.
0.0

L________

A

_____.1 _ _ .___ .

B

C

__ . _____. _____ .I. ____._________ ._R_. ___.___ . _.........

_.

1

1

$LOCATION=J12
B HEM A < P > " A f !

~9~!E---.--=~-----.~~-

A
R~B9
A9

-

1LMf:~.-.-- _ _ - _ _

2

~i8

D HEH A<7>

~~7

PJ:truLA~_>--- .. ----~

Ri

ILt-tJULa<5>

R~5

ILMEM....A~.-

Ri4

B~....

B MEM A<1~._ .... ___

~.~~~~'

R~l

s

F9

P_t1f.;,MJt___

A

ILMg~La~.10>_ _._.

L

10 ,
10SI'
I~g : --2

-..

-.P..sJ.1>

825

6

I~g

:

I~8o'
181)"'

TSOP

RASS.
RAS,
CASS.
CAS.
WRS.
WR.

RHO
~m

°8~

D

-'---

B CAS<2>

S4

fF=
: ~!Ct-s
8

~J

2

-

B MWE

~~1LMruLM

XA3

P_t1gM_l\~.____D~~!t~-~ Z 2
VALUE- M

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:

IV

Thu Aug 18 13 ,29, S2 1994

f(JR[[E

PLAT_OllAWINO, ORAlCCIIIP_ll. WOIC. 9.1

INSTMlTIATIOlh IM2M5V1B DRM21P17 D1WCClfIP1PI
1 . - . . - - - -... - - - - - - - -

--"A'-

-"'---"-~'r---'

B

T-----------c-

COMPUTERS

-.l>BA.mHIJ..

ABBREV=DRAM_CHIP

MAR/21/95 Manual

SHEET
11

OF
39

REV.

DRAM CHIP

0.0

,--__

A

-- ---

-- - - - 13--

~

___

._=______._L

J___________ ._._~ _______ .____ .. __ .

C

1

1

$LOCATION=J13

___

. --.

+

I:HI~;l>~--l~ __. _ . _ _ _ _ . _
-85"
~=--.--'--·--'----'---·'----r/

IU~_~~~Q.>

-Il

P. MEM A<7>

I~S3 :flf=i~
10S~. s

~~6

~

~--.

~jfEM A

A6

102 .
10s1 •

U4

I¥S8

10

~g5

MEM A<5>
B MEM A<4~_______

Il..MID1 A<2>

~~~9

Uo
AS7

B ~ A<6>
--

2

A 1
A
0

11(>",

D<35_~

D<34>

D<33>
.-

:-g

D<3~~

2

l~2

U1

--.. ~-.---

~80

ILtt-EJ'LM.Q;>
1U1El'f..-A~Q~--------·--------------..rlrl

ILMruLA~

_ __

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:

IV

) [-

_PMWINCt

Thu Aug 18 1l.29.54 1994

i

FIJlT.DRAWltlO. ORJUCCHIP_12. LOGIC. 9.1

IlISTANTIATJOtl. IHI!H5V28 ORH211'19 D1WCCHIPll'l

----------

..

~-.~~--=-r

B

.----r----

_._- ~:J- >~-"

W
c

~

[

~f::--:-J
[~

__1

COMPUTERS

ABBREV=DRAH_CHIP

MAR/21/95

Manual

SHEET
12

OF
39

REV.

--=:1

DRAM CHIP

0.0

A

B

-~=-=-

______

~_J_______

_______ " ______

_=~_===r

C

.Q ________________ ""

1

1

$LOCATION=J14
1-----

I~~_--_--=----"~==---------------

'12L

eP HEH
HEH A
A<7>

IOSI
10 ,
I~8
s
lOS '~-r

2

e HEM

JIg

A

B HEM A<4>

~~2

e_MEH Ag~

~~1
AgO

..D<;_3JJ~

sr::::-:~-----

-D~U2

~";!~

2

2

T SOP

RlU :~_____ L~S<3~
3
_~"S5~
~ft~ :
_____B_l1!'lli

CASS,

A

10
ILHIDL~_"_>~_

:

~o8.

l\,}"

lLJiIULM.a~_____
"-HEH A

.Qg2.~

:

ILMl!!M A<6>

~~~~

WR •
O~~:

A HEu
E
2 -- _ _ _ _ _ _ _ _EIN.__
"'-'!.-JL

XA3
um~LM_3~_____

DRAMSPEZ2
"--SP".&>uJ~!J"~

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:

IV

Thu Aug 18 1],29,56 1994

PLAT_DRAWING, DIWCCIIIP_13. LOGIC. 9.1
INSTANTIATION. (HI!H5V28 VRH21PU VRAH_CIIlPlPI

A B C

~[[E
COMPUTERS

_rmAWIN _~ ____ ~_

~n-~~~9

ILMEJL~~>

A9
~H8

B MEM A<1>
B MEM A<6>
D~JtM A<5>
B MEM A<4>

~~1

DJS~~L-___________

~~2

I~g3

~~6

~~5
~i4

lB"J'

M

P__MEM

~~1

A
B MEM A

s

--1t~

__________

D5.4..3.~

D<4~~

---~~

..9~

TSOP

~80

~-'lJ!!LI\<1·>

:

: :..ib
I~gl : ~
I~gg :
I~g~

RAd~ : ~

CASS

<

~~~:

_

3

--'LBA.J?~h
B CAS<3>
B MWE

_

WR.

KAi.
XAS3
XA3

2

_ _~NA MEM OE

08. •
OE •

DRAMSPEZ2
S\FJ5?u~IJ!-

B MEM A<3>

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:

IV

....P.BAWIN~_

Thu Aug 18 13.29.16 1994

f;{]l~R) 11[=;1 rf~~

FU.T_DRAWJlIO, DRAM_CHIP_14. LOGIC. 9_ 1

INSTANTIATION: IHEH5V2B ORH21PIlO OIWCCHIPJPI

A

B

---.-___

--.--=-r------.-

~~4

c

U___

ABBREV=DRAM_CHIP

MAR/21/95 Manual

L~

COMPUTERS

SHEET
14

OF
39

REV.

DRAM CHIP

0.0

.--_ _ _ _ _ _
A_ _ _ _ _ _ _

I

J_____

B

.L.__________ Q _______.________ ....

C

1

1

.-.

Ula
.-

$LOCATION=J25

~~11>

l2>

6

<: ~ -.-..

t=:
L,; r-

DJSEH. A<8>

3,

1LMt:...tLb~ _ _ .. ~--'

L~.H .A<6>
B MEM A<5>

2

p MEM A<4>

l-

J

~

An

.-

AIO

~1~9

~S8

IOS3. 825
I~g~ : ~r
IO~ .~.
I~Si
~~ _J
10SO
100 • - 2 -

A8

~~7

s r- A~6
r- ~S5

__

La

s ,--

I

__ ...

: ...

Ai
A 4

LL A

1LM~~~~1L _ _ _.__

e fl=:

PJtEM A<.Q>

L

B MEM A<2)'

ll -.

U2

-

~80

s

'l=I=1-sr-.

18(\n.

.___JL~..5~
D<44>

2

v

TSOP

A~l

RASS.

,84

C~~: ~hr~

~a!: ~tl='t-

LAlL A
B MEM A < l o ? : - - · · - - - - - - - - - - - r - = . r - 1 XA1~
s
~~~

OES.
OE.

:.=

--

D<.47>
D<46>

J}5.
.~

B RAS-Q.?

-..ILC~;t~
B MWE
ENA MEtLQE

DRAMSPEZ2

P~~~>

s~~uE'..sIJ,pD

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4
DESIGNER:

_PMW!.t::!Q..

IV

If:=J
t
:
,
.
[E
~
-----c...J

FLAT DRAWING: DRAH CHIP IS.LOGIC.9.l

ItIS1'~t"TtON. IH\!~SV2B-ORM21P'l1
A

ORMCCHIP1PI

,

I

B

I

[

COMPUTERS

SHEET
ABBREV=DRAM_CIIIP

Thu Aug 18 1).29.18 1994

4
15

OF
MAR/21/95 Manual

39

REV.

.

DRAM CHIP

0.0

r-------

J

A

~I_____

B

L____________________:Q _________________ _

C

1

1

$LOCATION=J26

B HEH A

6
~<12~----------------------1I-D-:MEf.rX<~~-------------_~=
9>_____
________ y __

___ ---------

A 8
ILMruu_~
B HE~__

_

IU!f:M A<6>_
ILMEM~S>___

2

B HEM A<4>

________

-...-1--------A~
AlO
~~~9

A9
~fi8
AS7
A7
~i6

10SI'
I=112
I~8 :::!blOS
IO

ASS
AS
~~4

t ,}"

1S

I~S3

,
•

S2

: =f=J

D~-~O~

D<51>

D<49>
--D<48>

___

2

T SOP

!L.t1EM A<2>_____ ~_

~~2

lLMf:lLMh_______

~f1

~~:

~-.Mf:!L~~~___

ASO
AO

IUtEIL~<;.l~_ --------~-

I~~~

CAASSS,
C
,
W~R:

O~~:

~:1-----------B RAS~l~
saL:!
B CM~

r- Jf=J

------

B MWE

ENA MI:;H...Qk!

XA3

DRAMSPEZ2

PJiEl!iA~~

S~fr?UE..s!J!~-

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

I)
DESIGNER:

IV

Thu Aug 18 1].29.19 1994

f@~[l(:

PIJ\T_DRAWltla, DRAM_CHIP_16. LOGIC. 9.1

ltISTANTIATION, (HEHSV2B DRH21PIl2 ORM,-CHIP)PI

----- ------ -----X----------

,--

----;---B-------------l------C~-

COMPUTERS

..DMW_ni~L

ABBREV=DRAM_CHIP
MAR/2l/95 Manual

SHEET

16
OF
39

REV.

DRAM CHIP

0.0

A

__ ~ ________,

B

~

C

___ ,_________ ~_______________ ,_,_

1

1

$LOCATION .. J27

Hmt:~~U~--

Ai
A

(CMEtCA:<9>
~ _ _~~____

AS~9

ILMt!Lh,~~
__~,_
ILMIDJ

~18;
55
~~7
1~8~ : --#i-r-_~- __ ---------P~~

A<7>

IOS~ • _sir:
102 • __IL!

A7
I!....MEM A<_6>_ _ ,_______________~f_l AS6

t~5

D MEM A<5>
MEM

2

4

1L __ ....A·~_2:,______

lLMt:..M h,<2> - - - ILMg!LM.l~ __ - - - DJrntLA _~-_
B

MEM.-Ml~_

IL.~.L

______ ~__

1~5~:

AS

18

~~4

(j"

1 --

lOS.

10.

D<54>

p.s3

_52

___ D<52~

2

T SOP

t~2
~i1

RAJ~ : ~)fJ------t-------J3_~s.g~

ASO

CASS •

1!5

oUD :

3li5

~~~:

AO

XAlg
~~~

B.-CA.s~h

B MWE

'S3

ENA

OE. J-

ME~--';

DRAMSPEZ2
-S~~uE%,.sltf--

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:

IV

Thu Aug 18 13,29.20 1994

Ir=-O~ I'{---:---:I l[~

u,

FLAT_ORAWING. ORAJCCHIP_17, LOGIC, 9 ,1
tNSTAHTJI'ITION.

IHEH5V28 ORH21PI11 OIlAH.CIIlP1P)

-----.---

A

-------r=-

---B-------'---~------C--

....P-MNUiG.

ABBREV=DRAM_CHIP

MAR/21/95 Manual

~ = =

COMPUTERS

DRAM CHIP

SHEET

17
OF
39

REV.
0.0

~_ _ A-

___
-~. ~ ______ .--l

._J_.____

B

C

___

._L __ .___

-_._.

D

-----~--

---------- --

1

1

$LOCATlON=J28
~U~

--

-

---------

G~W-----~----- -~-----

~~~--

JLMF;H-A____. __ .
ILMEM A<1~ IL1fEM A

~~4

B MEM A<2>.____

~~2
~rl
~80

JLMgM A
B MEM A<10>

IUiEJ1 A<3~

~___

I~g~

I~g~

~~6

p...J1f;M A<5L..

P....MEtoi ~<1>

____
.+
___
I~gI :-B~t-·----

~~8

~r

J!l

XAl~

~~~

11<1'

: --w..,
:

I¥gg : :fj

TSOP

:~

~~
C~~~ :

WRS.
WR.
OES •
OE.

1

~1
S)

J>~9~

~!t~

___ . I2SS.1.?.~~~?:

2

~:-!~
ENA

B MWE
MK,tL
B HE A
'
tr:MEH'""X<:9>-------

Al-~------

A

l\S~9

:::::~~~IL1.ooL~_~6~

R~6

~I:

~~~-A<5>

~~5

~~M

~i4

_ _ . ---.. -------~-

2

A<4>

1LMIDLA..c:;!?' _____ ~_

~~2

~lLA~t>

~il

ILMEM A

D<~~

_ -_

D<60>

~__

B RA~~h
B Cl\S _

D_t1l!:lLM.~_____
ILM~:<~~__________

2

li6
~~4

lLMEMJ.~~__

~~2

ILH.f:JLA~Q.>_

ASO

ILMruLA~!~______

~rl
AO

lL.Ml';M.Ag.Q~ __ ._____

IU1.E.M..M.J~ _____ ._

I~82

~~5

It...MJULl~~_~_~_

XA10
XAS3
XA3

: -it2-------.----»~(i7.>
___ -'!.<66~
I~81 . -P--,
--P~H~
I~~8 : ---:c:..
Jl!~J~4~
I~8~

AS7

_

111(';.

;16 .J

T SOP

~~:

~-r-'---

CASS .....~

~ft~ : :>~l_
WR.
OES.
OE.

s

2

B RAS.~~
BSM~3>

_ __-1Lmm
_EN1LMEM__OE

4

DRAMSPEZ2
Sv:m,=l..SIJ!D

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:

IV

Thu Aug 18 13.29.24 1994

PlJ'.T... DRAWItlO I D1WCCHIP... 20. LOGIC. 9.1
INSTIINTIATIOlh IHEH5V2B DRM21PI16 DIWCCHtP3PI
L-. _ _ _ _~~ ____

---1\

- - - - r - · - - - - - - · · - B---.-----~-.----- C

~-O)(:[[[E
COMPUTERS

_.IDU.\JiING

ABBREV=DRAM_CHIP

MAR/21/95 Manual

SHEET
20

OF
39

REV.

DRAM CHIP

0.0

I

A

.__ .. ___ L.___

B

- __..-.l _____.__.__ ._ .. _... __ .Q .... __.._._. __ .. _____ ....

C

1

$LOCATION=J31
6
B
MEM A11
~I2~----------.-.-.--.-~
..- _ r

All°

IU1.E.:t-f~L.--------·----···----___________elF RHO
P~:c1>_.. __... _______ ._..... -_..__. - - - _.._ - B I_ AS7
A7
D..J1gM...A.:~._.~_________

l!

P_I1~1ol..M5~__

2

D..lI~lC~<~_~

AS6
A6
~~4

R~2

_______ .__

R¥'

R8 0
!Ui~ A___

-------.--=*---1 XA1~

F' - ~R~

._ _ _ _-------'1

~11>

1'

lOS
10
lOS
10
lOS

R~5

IU1~!'I A<4>

'I

.• - - - -

B""J.tER"J\<95----------·· ----.------------ss--. A
-·~·~~----------·-·-·----·--eiE ~1~9

l~g8

"\)"'

D<70>

,...
•
,

. _ _ _ _ __
D 69
<--.-.2

: .-f!-t-

10.

__D<60>

B

=r:::!-

2

T SOP
~~ :J-------.lL...RAS<3~

C~f~:

WRS •
WR,
OES.
OE,

I
,

j--

B CAB~~-E>
____ In'l_.

r-

E;mUi~lLQ-'!;

-

D~ij/~Z4

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:

IV

Thu Aug 18 13,29,26 1994

r~J [-r---::1 I[['~

PLAT_DRAWIIlO, DRMCCHIP.21. LOGIC. 9.1

INSTANTIATION. IHBH5V2B DRH21PI17 DRAM.CHIP)P)

A

--T------·-····---s-·--.---·----···-1---

c

~ \W1,·~~~:, - ' j . =
COMPUTERS

._~.I!b\'JI~_

ABBREV=DRAM_CHIP

MAR/21/95 Manual

SHEET
21
OF
39

REV.

DRAM CHIP

0.0

__1?_______________ J__________~ _____

A
---_._-----

.----- ...

--~----.-

D -- ._------_ .... - ... -----

--'.'--"

.

1

1

$LOCATION=J5

1iIt!-j~1~-----------

<9~=--===-----

1LM~lLA.<7>

~~~9
D<3>

~~7

D MEM .A<6>
1l..,.Mf;.tLA~~--

____

"....HEM A~42._
~<2>

111
A9
AS8
A8

ILMEM A<8>

2

6

D<1>

__

A4~ _ _ _

D_MEM

A<~

_____

____

TSOP

~~2
~~1
~~O
XA1~

~~

P.

MEM A<;.;'>

---.lL

AS6
A6
ASS

2

BM~~

RASS.
RAS.
CASS.
CAS.
WRS.
WR.
OES.
08.

B

CAS<~

B MWE
tlliA MEM OE

DRAMSPEZ2
SPEED"%SPEjD-VALUE=4M

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

L]
DESIGNER:

IV

Thu Aug 18 13,29,15 1994

~r[E
.~ '~= L._

PLAT_DRAWING, DRAICCIIJP_22 _LOGIC. 9.1
INSTAIITIATION, CHBH5V2B DRH15P DRAM_CHIPlPI

A

--------13-------------

-_._------

C

COMPUTERS

....ImbIDN..Q..

ABBREV=DRAM_CHIP

MAR/21/95 Manual

SHEET
22
OF
39

REV.

DRAM_CHIP

0.0

A

_______ ~

B

_______!?____________ ..

___-_--_.-~_.

C

1

$LOCATION=J15
I-----

I

~Ut ~:=----.
~_~~9_~ _____

-!l~.

P-MEM
IUiE.M
... A<7>
A_<-.
ILMEtf~

B_MEMJ\

====--.-----

6

S;"

-

_ -----

_____

-----------------

_

_

It...MEtf.....A<4~

2

B MEM...A<2>

S

~

S

~l
_ _ _ _ .._ _ _ _ _ _ _ _

All

A10

MS9

~~9

Asa
Aa

~-_-----.--....J!.c;.h

AS?
A7
AS6
A6

R~5
R~4

P~§,>­
D<;.~
la(~n.

2

~~2

ILMIDL1>6n____

AS1
Al
ILtmM...A

D<~

~~~

RASS
RAS •• ~~i5

B RAS,~

C~~~:. _.
WRS.
WR.

OES.
OE.

B CAS
B

S

!

mm

ENA-MElLQE

2

DRAMSPEZ2
S\'~=J!IJED--

ILH~MJ~~._

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:

IV

-_ JlliAm.N.Q.

Thu Aug 19 13,29,57 1994

~.)~-[= lE-::1
•

PLAT_DAAWJ NO , DIIAM_CHIP_21. LOGIC. 9.1

. .--

A

MAR/21/95 Manual

SHEET
23

OF
39

__ =.1

~,

INSTANTIATION. (HEMSV28 DRM15PI1 DIIAM_CHJP]PI
L..

-./

ABBREV=DRAM_CHIP

. -_____. - . _

I

.

B

-----,-

.,'.:~

C

-

COMPUTERS

REV.

DRAM CHIP

0.0

->J____

._ _ _ _ A

B

______ ~ ___

J ____________~

_....-1. __ ._ ._. __ ._ .. ___ ._._. ____ .R._. _______ .__ .

1

1

$LOCATION=J16

nA

--'

P'.J1f:1LIL<;jl~
7

B

AS~9

... __._._

ME.M~ ___.. _______ ~_

B MEM A<6>
P...-MEM

2

A<~~. _____ .______~______

B MEM A<4~

l~8
A8

~~6

l~~~

A6

ASS
AS
AS4

A4

ILMEM_~_~_~__

~~2

PJI>;H A

'L_ ._________

<;._~

2

1

D 8

r

--_____

<.~

2

TSOP

RASS'I

RAS ,
C~KB:
WRS.
WR.

O~~:

.P-Bl\l!,<2>
B

CAS

DRAMSPEZ2
S~.&'u"~..sIJ!- ---

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

1\
DESIGNER:

IV

_P~..wING_

ABBREV=DRAM_CHIP

Thu Aug 18 13,29,59 1994

~[[-)IC

FI..AT_DRAWINO, DRAH_CHIP_24. WOIC. 9.1
INSTl\NTIATION, (HEH5V2B DRM75P12 DRAH_CIIIP)PI

L

---"1\--'-

---~-I---·--···---·----B-----------T--~---

c

I

u --O~~~

_ r::

COMPUTERS

MAR/21/9S

I

Manual

DRAM CHIP

SHEET
24

OF
39

REV.
0.0

J

A

~______

B

_____.1_____________ J2. _________________ _

C

1

1.

$LOCATION=J17

UIH~H~
9>

~~~

-------.--

-----

J;U1ElU~-_

2

6

s

AIl

Alo
U~9

tH9

10SI'I
1£8 .
__
10

t~7

D-MEH A<7>
lLM~.M A<6>

/

- - - . - - - - --~---~-

.~--

U6

JLMEM.-M..S~ ______.____

t~5

P....MIDLA:<4>__

ti4

A<~_.__ ~ ______.
ILHEMJ~l>______

t~2
A~l

lLHEH

p HEM A

lOS
10

I£~g

lB/!'.

TSOP

RASS

tso

IL11~JLMJ-Q:> _-__

HEM

M~

·.-i

~

______

'r:•

J

: _f=!

C~~: s 1..
~ft~ :8
WR,
O~~: lLJ

AO

II

•

--

D<15>
~.i~

D<13>
----

D

B CAS

B MJif;
ENA HEH_QE

__ _

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:

IV

Thu IIug 18 13.30,00 1994

FLAT_DRAWING, DRJUCCHIP_25. LOOIC. 9.1
IIISTANTIIITION.
L-_.

IHBHSV2B DRH7SPil DRIIICCIUPJP)

A

-----B-------=::----.

_r-----------C---~

f(J~[lE
COMPU'rERS

_Q.IYWlJ.NQ_

ABBREV=DRAH_CHIP

HAR/21/95

Manual

SHEET
25
OF
39

REV.

DRAM __CHIP

0.0

_l ____ ._._____~ ____ .=_~~~ __ ._. ______ .. L _____.__.__

___________ ._.__ A

__.____.____._.__._ ._. __ .__ . 0

___ -~_~~=_=r

C

1

1

$LOCATION=J18

Umt:~H~--~_@M A<~

..

B MEM

A<8~ __._______

I) MEM

A<7>

2

ILt1ruL.A<4>

."

s

~

----e

_

2

IIr----·----ASS9
AS9
A9
UB

------.----e _
-----------t

I~~I:

~~7

ILM~L _ _ .. _
ILM_EllA~~_

'--~--~---:=-~~-----i=

.

--~------~---_ _ _ ~__

s
___
~_

sN-

I~~

AS6
A6

I~8

AS5
114

111

0

I~88

",

T SOP

______D<19.2

~p

: =h-~------_-----D-~l~~

: ~:=t------_-_-J1~n~
; --f-r-------- ____.-lL<.1.~

I:}.-m:-".-A~~?'. ____ ._______

~~2

1)_t1~!I..A~ ______ ..

R~l

~I

:

lJ_BM_oe;2?'.

ILMgtL.A~~

ASO

CASS •

B CAS<.2?.

B MEM A _______._

~~~ ---'--JLHEM

__

A.<~8~>

IU'mIL~~~--_-------lLl1EM

J) MEM

Iag2:
lag!:

__ .. __

IU1~tL~~.

2

IOS~.

-_

A<6>

-:I

A<4>

JLH..~"'~~_____

:-=-~:~:
.'-

----

" MEM A<10>:

lLtSEM A<3>

11(1'"

S_

I~go : - --

~~'

RASS.
RAS.
CASS •
CAS.

~

W~R:
o~~ :

F1iD·~2K£!Z2
s

5

~~tg

0<23>

O<~~

0-;21>

O<;Q-;

TSOP

~
I~~
Ll
AO

--.-----.----~--

p===--=-

~

2

B RAS<2>

~---_-----.lLCA.~~~

~fiG

~--

~

_____

~B_MWE

ENA MEM OE

_ _ _ _ _ _ _---'

VALUE=4M4

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:

IV

Thu Aug 18 13130.04 1994

[~[[[E

FLAT_DRAWING. DRAICCHIP_21.I.00IC. 9_1
IIISTIINTIATION. (HI!HSV2B DRH15PIS DAAlCCHIPJPI

---------------A

J

.

B

-----------.-.--.~-J---

c

COMPUTERS

_1!.I!AW1N..Q._

ABBREV=DRAM_CHIP

MAR/21/95 Manual

SHEET
27

OF
39

REV.

DRAM CHIP

0.0

,__________

-r=

A-~-

=_L . ____. ___~=~-

B

______

C - - - . - - - -_ _._J __ ._____________ .______ ._ . ___ ~I;?___________ .____.______ .. _._.

1

1

$LOCATION=J20

e-u~~M
~~~B~-------~>--

"'-"=-<-=..::..!

.----

All

U-HEM-~8>

~H8

It-HIm A<7> ____________________

2

~~6

B M~~5>

~~5

~~ A<4>

~~4

A<;;!~_____

~~2

ILMI!;M A-;1.>
ILM~H A<~ __ ~
.

ILM~M
B

I~~I

~~7

~MEH A<6>

B MEM

----

AO

R~~9

----

A<10> __~_

lOS
10
1~8
111(;.

I~88

TSOP

:
•
..

:
:

____________

D

--tP-r

ENA M..ruLQf;

HLt

____1

3

3

EXPR={CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:

IV

Thu Aug 19 13.30.05 1994

~[E

FLAT_ORAWltlo. ORNCCHIP_29 .LOOIC.9.1
INSTANTIATION. (HEH5V28 DRH15P'6 DRAH_CHIP3PI
--------~.

--1---

B

----------,

C

COMPUTERS

__tm.AmN!L

ABBREV=DRAM_CHIP
MAR/21/95

Manual

DRAM CHIP

SHEET
28
OF
39

REV.
0.0

L

____ A

___ .__ ._.. _L ___________~ ____._.____ .J _____ .. __ ..... __ ..!:?___ .__.____ ._. __ ..

B

1

$LOCATION=J21

.... .-.. ---.. ----1--- --.--.-.-.---.--.
..

B:fJlltj~l~~---~-

B

~>----.

-~-

~gM-A

PJ1ID-LA:c.S;..
JU02f;HJ\oc;.4~.

Asa
R~7

B

ILM~M-A

P,..J1.f;.H.,...A,. <
....

R~2
. ... - .... -...- ..-...... ---..

--~

t~'
ASO

1.

<)ft'

I~8~ :~J)~:U>
I¥82
:
___ ~O~
I~8 :
j__
....J2<2~
=t':=1
D

~R~

:Ir

. ___QJ1J'1B.

U

J.MP< MEM QE

c

:
WR.

~ftl

S

OSS c
OE.

8n'-:

/.

B RAS<2>
JL~.M...

DRAMSPEZ2
-

P_t1~~J? __. ____ .

"-S~J5?u=l..sIJfD

3

]

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

t]

DESIGNER:

_pN'M.um..

IV

T".
f
------==r----C-

Thu Aug 18 1l.JO.07 1994

FLAT_ORAWINO, DRAH_CIIIP_29. LQOIC. 9.1
INSTANTIATION. (MEH5V2B ORH75P17 ORAH_CHIP1PI

-------

A

t·

~

...>~

[.:1 [E'c-·:::!

ABBREV=DRAM_CHIP

MAR/21/9S Manual

J

REV.

'-~

B - - ....

COMPUTERS

SHEET
29
OF
39

DRAM CHIP

0.0

_~

L

A

___ ._. __ ._____ . . _J ___

C

.-.--.---.-.~-.--.

-- ..

D

--~----.--------.-.--

...

1

1

$LOCATION=J22

tIEI~l~----<9>
__~_.-:-

Ap
A 0

. ~_

AS~9

~i

ILH.EMA~.

~~8

ILHJi:M A<7J>
B HEH

A~

D~5.L

2

u

_________

IUft:~QL

lLHEM A<10?

_ _ ._ _ _

D-=~U~
D<3~

tl!ll'~"'

~~4

1:lJ!EMJ.~2>

ILMEM A..___

D<34>

A 5
~r
A

____ .__

1LlmM-A~-

IL.H~ILI\.~J_>

D<3.~2.

AS7
A7

TSOP

~~2
~~1
ASO
AO
XA1~

~~~

RASS.
RAS.
CASS.
CAS.
WRS.
WR.
OES.
OE.

14 ,

2

. _ _ _ILBAS~22

f1

B

C~O>

_.----...P...Jftl.E

-L

DRAMSPEZ2
sP,f~uE..sl:!D

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:

IV

DRAWING
ABBREVaDRAM_CHIP

Thu Aug 18 13,30112 1994

FLAT_DRAWING. DMM_CHIP_10. LOGIC. 9.1

U

I NSTAlrrJ1ITJONI IHI!K5V28 DRK15P18 DMM_CHJP1PI
~~---------

A

---·--13------

c

O~[[E
COMPUTERS

MAR/21/95 Hanual

SHEET
30
OF
39

REV.

DRAM_CHIP

._-

0.0

,---_________

A

B

______ ._._. __

L___ . _______.__C _____________ ~~I=~_=_. ______ .___·-· Q____________ _

1

1

$LOCATION=J23

IJUjntt_______~----------- .~=---~-==-p.~~_________

B HEM A<7>

ILM~

6

-pIE

-----.-~--------

81

~ir---------------

ll~9
~B8

~~6

ILM.f;M A<4>

~~54

H HEM

U

A<2>

ILM~M A
ILMEMJ.S..Q~_._
ILM.t;t-L~~J_Q:._

ILti~" A<3>

--------------~~~
P_<)J12:

~~7

ILti~t.L~~~_

2

-

_______
lBO"'

TSOP

~~2
~~1

RASS •

F1
s

,-----~--'

XA10
XAS3
XA3

~81

2

B RAS<2>

C~~:

~3°

D~312:

D<36>

A

:

g~

eJ1Ng

El-l~_~fLQE

OES.
OE.

DRAMSPEZ2
SI!f;.~DU;''' - ---

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:

IV

..l>J!}\J'/1m}_
ABBREV=DRAM_CHIP

Thu Aug 18 13:30.15 1994

r~fi-Jr!-:::J

f \l:IW'''. [

Pt.AT_OI\AWINO, ORMI..CtlIP_ll. LOOIC. 9.1
INSTANTU\TION. (HI!H5V38 ORM15P19 ORAN_CHJPJPI
L -. . . ______________ .

A

--·---·-··----·-~-'-----B------·--··----r

c

lC

COMPUTERS

MAR/21/95 Manual

DRAM CHIP

SHEET
31

OF
39

REV.
0.0

I

A

B

-- ..

---~----.'---------

C

------.------.. -.---.- ._-Q_... _-----_._---_ ...

--------

11

1

$LOCATION=J32
B MEM

A

tr:MEICA
BJOOCA<9>

II!
ASS9

-~-.---

9
RB
8
RR

D MEM A<8>
B MEM A<7>

R~7
AS6
A6
R~5
R~4

~~
ILMIDLA~.~

2

B

______~_.__.__
____

MEM..A~

lU1~M..A<2>

R~2
R~l

IU1f;M A<~ ___ . __
B MEM..A .__________
1LMIDLA.<,1,~_>

t8°

_

XA1~
XA~

XA

2

ll(~,

TSOP

RASS.
RAS.
CASS.
CAS •
WRS.
WR.
OES.
OE.

__.1LM.S_"!.i!2
J;L{;AS~12

B WE
E AJ1f!JLQg

-------

DRAMSPEZ2

ILMEM A<3>_

~~u=E..slJ!D

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:

IV

Thu Aug 18 13.29.27 1994

FLAT_DIlAWINO. DIW1_CHIP_32. LOGIC. 9.1
INSTANTIATION. IHEHSV2D DRH7SPtlO DIW1_CHIP1PI

-

...

~.----

---

----

--~-

A

---B----

- ..- - - - - - C - -

rFtJR[[E
COMPUTERS

_PMWIN9_

ABBREV=DRAM_CHIP

MAR/21/95 Manual

DRAM_CHIP

SHEET

32
OF
39

REV.
0.0

_. __ ._J ___.

B

A

C

______ ]_ . ___ .___ ._._._____ .P.__

------.- ...

1

1

$LOCATION=J33
B MEM A

~~~>-.

----.. -----.--

A
AiO
ASS9

-~

~~9
~H8

_____.
A<7>
Ad>
A_________
A<4> _ _

ILH~M.._A~J!>_.

2

B MEM
B MEM
IU1EM
ILHK.M

.___
1' =Ih=!
fLt--------

108
10

AS7
A7

~~6

ASS
AS
4

111<)".

U

B HEH A<2>
UEM A~l>

[LtfIDLM1Jl>

.....Jtoe;~5.~

•
,

_ _

0<44>

o~»

XA1~
XA~

:

OE.

2

<2>
B
B CAS

RASS.
RAS.
CASS.
CAS •
WRS.

XA
.L.MEM

:XRI:
lOS .
10
10

JL~h

----p~~~

TSOP

~~2
~~1
tHO

ILlI~~

,

mm
s

ENA HEM

~

DRAMSPEZ2
SPEED"'S!t'~

A<~_

VALUE= M

3

]

EXPR={CHIP_TYPE=DRAM4M4R4)
4

4'
DESIGNER:

IV

Thu Aug 18 13.29,28 1994

f~~[[E

FLAT_DRAWING. DRAM_CHIP_33. LOGIC. 9.1
INSTMITIATION. IHIlKSV2B DRH15PIU DRAM_CHIPlPI

-A---

---~

B

.

~--

c

COMPUTERS

.J2M~JJlG_

ABBREV~DRAM_CHIP

MAR/21/95 Manual

SHEET
33

OF
39

REV.

DRAM_CHIP

0.0

L

A

...1._. ____ ._____

B

.___~..

c

_=r= __ .___ ._ . __. . . _Q .. ___.._..._.________.__ ...

1

1

$LOCATION=JJ4

I:MtSn~~

~ 6--·-~

..

~ ~.

tl~9

~M A

D.lmtLlI<"
Lti8M~>
It-HEM A~

2

ASO

--~----"'-"#-4 AS6

1LM~.lLM~_._.

~F;JoLM2.L _ _~___

ILH.!i:M....A~_____
ILm:~ __._..
ILtmM A

A6

ASS
AS
----.~t+_l ~i4

~~2

tiFr

1
IY8
IOS~ .

~ iR,
A7

ll(~.

102
10Sl
101
IOSO
100

•
•
•
•
•

.. _ _ _ _ _

1"--tJ

'-sr_~

D<40>

__

2

T SOP

if'"H~
:I~'
I
CASS. l! 3 _

ABo
A

~ft~

XA1~

OES •

~~~

D<.b
D<50>

4ft
___D~.2~

D RAS<2,

.13 CAS

: _

WR.

B M.WE

.>!t:.t

ENA MEM...QE

OE. J

.DRAMSPEZ2
SP"~uE~IJlj)---

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

4
DESIGNER:

IV

Thu Aug 18 13.29.30 1994

~[[E

PLAT_DRAWING. DRIJCCHIP_34. LOOIC. 9.1
INSTMlTIATlOlh (HEH5V28 DRH15PI12 DlWCCHIPJPI
1-.

A

--·~B-·----=r--

C

COMPUTERS

.J2M.W.l..tiCL

ABBREV=DRAM_CHIP

MAR/21/95 Manual

DRAM CHIP

SHEET
34

OF
39

REV.
0.0

------

B

A

~-----~.--

----._----------

C

-~------.-

_.

__"

D

_ _ _ .. _ _ _ _ _ _ _ . _ _ _ _ _ 0-

_ _ • __• ______

1

1

$LOCATION=J35

G =~= ~~i!}---~--··--

JU1r;~~_-----=--_

B MEM A<8>
B MEM A<7>
B MEM A<6>
JLMIDLA<5> _ _ _ _ _

_F' _ _ ~ _ _

2

B MEM A<4>
A<2>
IL.tiruI A
ILMm'J A

-n~

ASS9

~~9

8
U
AS?

A7

~~6
~~5

Q5~3>

TSOP

~~~

__

I

JLMS<;22.
_ B CAS

~~:

XAlg

21

----p~~?

18(:,.

~8°

!LMIDLI\:

A<3~_~

1-

~~4
AS2
A2
~~1

D MEM

B MEM

6

CASS.
CAS.
WRS c
WR.
OKS.
OK.

s

_--'Ll1W~

ENA

2

MEIL~

DRAMSPEZ2
s~~u"E ..slME1D

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:

IV

Thu Aug 18 11: 29.ll 1994

PLAT_DRAWING. DRAICCIIIP_35. LOGIC. 9.1
INSTANTIATION. IHEH5V28 DRH75PIll DlWLCHlP3P)

--------------,;:-------- -----------8---------

----------

c

fffi[f
".~
~
COMPUTERS

Jm.MUlliL

ABBREV=DRAM_CHIP

MAR/21/95 Manual

DRAM_CHIP

SHEET

35
OF
39

REV.
0.0

r------------

I

A

B

]~

----~---------------- _____ 1>___________________

C

1

1.

$LOCATION .. J36
._-

Bn~~~t~~---__ ?___

f>

II

~.3

s~

e~
3,-

A9
t~ f- ~~8
Sr- AS7
A7
f-

JLH~JLM8>

JLm:M A<7>

B HEM

Li1

A<~

-~r-

ILJmM...Aill ____

2

ILMJ):M A<4>

d~

-

DJ1ID!.A<2> __ .. _____ ~__ . __

~

ASO
AO

r

B MEM A

P HEM A

P.J1gl1~

~~2
~rl

~

9

____

:a=rl
TSOP
10SJ •

D<59>

825

Ibg
10 • ~---------~~~

~~6
~~5
~~4

.5t
st--f--

DJiE;M....A

-

-~n
~~~9

lOS
10
lOS
10

111(;1"

•
•
•
•

I=J

~~:b

CASS.
CAS.

It=!

WR.

~

WRS.

~tt~

.P~~

D
B

CAS<~

B HWIl;

og~: !L1---

XA

______

~~M_.Qi

DRAMSPEZ2
s\'~uE'..sIJfD

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)

4

L]
DESIGNER:

IV

Thu Aug 18 13.29.32 1994

frn[[E

I'LAT_DAAWlIIO. DIUIM_CHIP_36. LOGIC. 9. t
INSTANTIATION. (HIlH!iV28 DRH75PI14 DRAM_CHIPlPI
L.. ____________________

A

I

------

B

I

c

COMPUTERS

-PMWlN----Imt~

1"-

.

US

D MEM
D MEM

A
A<7>
It.lm.M Ad>
D MEM A<5>

2

1LM-~~<4_>~

AS7
A7

~i6

AS5
AS

____

ILMEM...A~---

~~4

.--

~~2
~~1
~~o

____
<0>

~

2

11(';.

TSOP

RAS~

B IY\~~

CASS

B

RA •<
<
CAS.
WRS <
WR.
OES.
OE <

CAS ._

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

4
DESIGNER:

IV

'l'hu Aug 18 UI29134 1994

~ ~[[E

PLAT_DRAWING, DRAICCHIP_31. LOGIC. 9.1
INSTAN'l'IA'l'lON, IH£H5V2B DIUI751'115 DRAM_CHIP)P)

----

A

B

c

COMPUTERS

~.lliL

ABBREV-DRAM_CHIP

MAR/21/95 Manual

DRAM_CHIP

SHEET

37
OF
39

REV.
0.0

,.------

__ .L___

A l B

..._~._______ ._____ .... y

C

__ . ____.____.__.___ _

1

1

$LOCATION=J38

.

L

~lA

'-.lifr's r-

AS8

~

~9 6

~u91lL=----.
B~M~

.,

B MEM A<8>

D MEM

. 8:>

_

A<7~

~

IU1f:M A<6>
P---Hf:M

A<~_

~87

~ &- ~S4
L._AL M

I~SI

I~~

:!=!p.
,~
:

-_ _ _ _ .D~&J2

_n:1
.t-¥-f-

_-»<6~

sr-:
I~~O : ~--:::r----

lOS
10
IB/'J"

•

.~-'')~
_.JKt$Jl~

2

tl81_ ~~2 TSOP

1LH~<2>

t
t

ILt-OOI-A.<..l_>____

JUOOCA~.Q>

-

~~

L,;8 ~~
Ai
6
A~5

D MEM A<5>

2

j-

r-

~-

AS~9

8 MEM~O>.

RASS • - ~-_--_-_-!LIv.\-S<2-:>:

Afl

8

CMI:

RS O
.9

WRS.
WR.

OES •
OE.

XA10

IJ~ ~~~3

D....J1.gtLb~__._ _ _ _ _ _ _---'

!f.1----.---- _.____JLQMtg~

~

8 MWE;

_mJ~~ILQ(!;

V.

i~L.J

D~=..~EE~Z2
VALUE .. 4M4

3

3

1-

EXPR=(CHIP_TYPE=DRAM4M4R4)

4
DESIGNER:
IV
Thu Aug 18 13.29.35 1994

~ 2F-~)
'.

FLAT_DRAWING, DRAH_CHIP_1B.LOOJC.9.1
JlISTMITIATION, (HI!.H5V2B DRH75PI16 DRAH_CHJP1PI

~-

1\

-----,

B

I

~

c

FO

.. :~~

[I [E

J>...MW1.N.Q.

SHEET
ABBREV=DRAM_CHIP

38

OF
MAR/21/95 Manual

39

REV.

~

COMPUTERS

4

DRAM CHIP

0.0

------

B

A

________1_________

C

D ___ •_ _ _

_ _ _ _ _ _ _ _ _ _ _ _ ._A _______ . ___ .__ •__

~

~_~

_____ ..

1

1

$LOCATION=J39

H~=
EM ~~B~

A
A 0
ASi9

1\<-g~---

I)

~~

MEM A<8>
A<7>

B MEM

D<71>

U6

-~~

~q7

~A<6>

B MEM A<5>

2

~i8

~r

ILM&M--A~~ _ _

A 4
A

____
P...J1IDLA.
B MEM A

1

UO

M

MEM A_

XAlg

~~

2

18(f'

TSOP

RASS.
RAS.
CASS.
CAS.
WRS.
WR •
OES.
OE.

MSS_2~

B CASsn
B _..E
EMA MEM og

s

DRAMSPEZ2

ILM.EM A<3> ____

s~~uE..slrfPD

3

3

EXPR=(CHIP_TYPE=DRAM4M4R4)
4

t1
DESIGNER:

IV

Thu Aug 18 13.29,36 1994

~[[E

FIJ\T_DRAWIIIOI DRAILcHIP_19.LOOIC.9 .1
INSTANTIATION 1 CHI'.M5V2B DRH1SPI11 DRMCCHIPlPI

.----------

A

-----

-------

B

C

COMPUTERS

_P_RAHlllit

ABBREV=DRAM_CHIP

MAR/21/95 Manual

SHEET
39
OF
39

REV.

DRAM_CHIP

0.0

SPARC CPU-SV Technical Reference Manual

SECTION 6
6.

SUN OPEN BOOT DOCUMENTATION

SUN OPEN BOOT DOCUl\1ENTATION

Insert your OPEN BOOT 2.0 PROM MANUAL SET here.

•

FORCE COMPUTERS

Page 177

SUN OPEN BOOT DOCUMENTATION

cpu-sv Technical Reference Manual

'-,

Page 178

FORCE COMPUTERS

SPARC CPU-SV Technical Reference Manual

SECTION 7

7.

Appendix

APPENDIX

Product Error Report

Dear Customer,
Although FORCE COMPUTERS has achieved a very high standard of quality in products and
documentation, suggestions for improvements are always welcome.
Customer feedback is always appreciated.
Please use the "Product Error Report" fonD. on the next page for your comments and return it
to one of our listed offices.
Sincerely,
FORCE COMPUTERS GmbHlInc.

FORCE COMPUTERS

Page 179

This page intentionally left blank

HARDW AREISOFIW ARE/SYSTEMS
PRODUCf:

SERIAL NO.:

DATE OF PURCHASE:

ORIGINATOR:

COMPANY:

POINT OF CONTACT:

ADDRESS:

TELEPHONE:
EXT:

PRESENT DATE:
THIS AREA TO BE COMPLETED BY FORCE COMPUTERS:

DATE:
PR#:
RESPONSIBLE DEPT.:

-

-

ENGINEERING
MARKETING
PRODUCTION

AFFECTED PRODUCT:

-

HARDWARE
SOFTWARE
SYSTEM

AFFECTED DOCUMENTATION:

-

HARDWARE
SOFTWARE
SYSTE~1

ERROR DESCRIPTION:

_0

Please send this product error rcport to one of our neareSl FORCE COMPUTERS offices:

FORCE COMPUTERS Inc.

FORCE COMPUTERS GmbH

2001 Logic Dri\'e

Prof.-Messerschmitt-Str.l
D-85579 Neubiberg/Munich
Genllany

San Jose~ CA 95124-3468
U.S.A.

FORCE COl\1PlJTERS Fnlnce S.A.R.L.
Le Volta
17-19 rue Jeanne Braconnicr
F-923()() Mcudon La Fora Ccdex

FORCE COMPUTERS U.K. Ltd.
Alton House Office Park
Gatehollsc \Vay
Aylesbury. Bucks. HP I') 3XU
United Kingdom
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.6
Linearized                      : No
Create Date                     : 2015:10:12 11:31:13-08:00
Modify Date                     : 2015:10:12 11:13:59-07:00
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Metadata Date                   : 2015:10:12 11:13:59-07:00
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:b76bc683-a703-e84f-b53e-ecdd6f3a9135
Instance ID                     : uuid:96e37651-aad6-ef43-a860-40ade967cde8
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 464
EXIF Metadata provided by EXIF.tools

Navigation menu