Force_SYS68K_CPU 40_41_Users_Manual_Feb92 Force SYS68K CPU 40 41 Users Manual Feb92

Force_SYS68K_CPU-40_41_Users_Manual_Feb92 manual pdf -FilePursuit

Force_SYS68K_CPU-40_41_Users_Manual_Feb92 Force_SYS68K_CPU-40_41_Users_Manual_Feb92

User Manual: Force_SYS68K_CPU-40_41_Users_Manual_Feb92

Open the PDF directly: View PDF PDF.
Page Count: 756

DownloadForce_SYS68K_CPU-40_41_Users_Manual_Feb92 Force SYS68K CPU-40 41 Users Manual Feb92
Open PDF In BrowserView PDF
Index

1 Introduction

2 Installation

3 Hardware User's Manual
4 Appendices to the
Hardware User's Manual
,

5 Copies of Data Sheets

6 Eagle Module
7 Introduction to VMEPROM

8 Appendices to the
VMEPROM Introduction

9 Bios Source Code Listing

10 User Notes
11 Options/Applications/
Modifications

SYS68K/CPU-40/41
USER'S MANUAL
Revision No.2
February 1992

FORCE COMPUTERS Inc./GmbH
All Rights Reserved

This document shall not be duplicated, nor its contents used
for anv purpose, unless express permission has been granted.

Copyright by FORCE COMPUTERS®

INTRODUCTION

This page intentionally left blank

NOTE

The information in this document has been carefully checked and is believed to be
entirely reliable. FORCE COMPUTERS makes no warranty of any kind with regard to
the material in this document, and assumes no responsibility for any errors that may
appear in this document. FORCE COMPUTERS reserves the right to make changes
without notice to this, or any of its products, to improve reliability, performance or
design.
FORCE COMPUTERS assumes no responsibility for the use of any circuitry other than
circuitry which is part of a product of FORCE COMPUTERS GmbH/Inc.
FORCE COMPUTERS does not convey to the purchaser of the product described
herein any license under the patent rights of FORCE COMPUTERS GmbH/Inc. nor the
rights of others.

FORCE COMPUTERS Inc.
3165 Winchester Blvd.
Campbell, CA 95008-6557
U.S.A.

FORCE COMPUTERS GmbH
Prof.-Messerschmitt-Str. 1
0-8014 Neubiberg/Munich
West Germany

Phone: (408) 370-6300
FAX: (408) 374-1146

Phone: (089) 608 14-0
Telex: 524190 forc-d
FAX: (089) 609 77 93

FORCE COMPUTERS FRANCE Sari
11, rue Casteja
92100 Boulogne
France

FORCE Computers UK Ltd.
No. 1 Holly Court
3 Tring Road
Wendover
Buckinghamshire HP
England

Phone: (1) 4620 37 37
Telex : 206 304 forc-f
FAX: (1) 4621 35 19

Phone: (0296) 625456
Telex: 838033
FAX: (0296) 624027

This page was intentionally left blank

TABLE OF CONTENTS
1.

GENERAL INFORMATION

................................... .

1-1

1. 1

Features of the CPU Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-4

2.

THE PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . .

2-1

2.1

The CPU 68040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1

2.2
2.2.1
2.2.2
2.2.3
2.2.4

The
The
The
The
The

.
.
.
.
.

2-3
2-3
2-4
2-5
2-6

2.3

The System EPROM

....................................... .

2-7

2.4

The Local SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-7

2.5

The Local FLASH EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-7

2.6

The Boot EPROM

......................................... .

2-7

2.7

The FGA-002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-8

2.8
2.8.1
2.8.2

The PI/T 68230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The I/O Configuration of PI/T 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The I/O Configuration of PIIT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-9
2-10
2-10

2.9

The Real Time Clock 72423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-11

2.10
2.10.1

The DUSCC 68562 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The I/O Configuration of DUSCC 1 and DUSCC2 . . . . . . . . . . . . . . . . . . . .

2-12
2-13

2.11

The EAGLE Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-15

2.12

The VMEbus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-15

2.13

The Monitor of the CPU board

2-17

2.14

Default Jumper Settings on the CPU Board

3.

SPECIFICATIONS OF THE CPU BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

4.

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1

5.

HISTORY OF MANUAL REVISIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-1

Shared RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRM-O 1/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRM-O 1/1 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRM-01/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRM-01/8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

............................... .
...................... .

2-18

LIST OF FIGURES
Figure
Figure
Figure
Figure

1-1:
1-2:
2-1:
2-2:

Photo of the CPU Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2
1-3
Block Diagram of the CPU Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Location Diagram for All Jumperfields . . . . . . . . . . . . . . . . . . . . . . . . . .
2-20
The Front Panel of the CPU Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-21

LIST OF TABLES
Table 1-1:
Table 1-2:

The Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
The Base Addresses of the Local liD Devices . . . . . . . . . . . . . . . . . . . . . ..

ii

1-6
1-7

INTRODUCTION

SECTION 1

1. GENERAL INFORMATION
This CPU board is a high performance single board computer based on the 68040 microprocessor
and the VMEbus. The board incorporates a modular I/O subsystem which provides a high degree
of flexibility for a wide variety of applications. The CPU board can be used with or without an I/O
subsystem, called an "EAGLE" module.
The board is able to hold a RAM Module which can be DRAM (CPU-40) or SRAM (CPU-41) based.
The CPU-40/41 family design utilizes all of the features of the powerful FORCE Gate Array
(FGA-002). Among its features is a 32-bit DMA controller which supports local (shared) memory,
VMEbus and I/O data transfers for maximum performance, parallel real time operation and
responsiveness.
The EAGLE modules are installed on the CPU board via the FLXi (FORCE Local eXpansion interface).
This provides a full 32-bit interface between the base board and the EAGLE module I/O subsystem,
providing a range of I/O options.
Four multi protocol serial I/O channels, a parallel I/O channel and a Real Time Clock with on-board
battery backup are installed on the base board which, in combination with EAGLE modules, make
the CPU board a true single board computer system.
A broad range of operating systems and kernels is available for the CPU board. However, as with
all FORCE COMPUTERS' CPU cards, VMEPROM firmware is provided with the board at no extra
cost. VMEPROM is a Real Time Kernel and is installed on the CPU board in the two 16-bit wide
EPROM sockets, which results in a 32-bit wide System EPROM area. This ensures that the board
is supplied ready to use.

1-1

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

Figure 1 -1: Photo of the CPU Board

o

s

;-2

INTRODUCTION

SECTION 1

Figure 1-2: Block Diagram of the CPU Board

1-3

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

1 . 1 Features of the CPU Board

•
•

68040 microprocessor:

25.0 MHz on CPU-40B/41 B/x

68040 microprocessor:

33.0 MHz on CPU-40D/41 D/x

•

Shared DRAM Module:

4 Mbyte DRAM with Burst Read/Write and Parity Generation and
Checking (DRM-O 1/4)
16 Mbyte DRAM with Burst Read/Write and Parity Generation and
Checking (DRivi-O iii 6j

•

Shared SRAM Module:

4 Mbyte SRAM with Burst Read/Write (SRM-01 /4)
8 Mbyte SRAM with Burst Read/Write (SRM-01 /8)

•

32-bit high speed DMA controller for data transfers to/from the shared RAM, VMEbus
memory and EAGLE modules; DMA controller is installed in the FGA-002.

•

Two system EPROM devices supporting 40-pin devices. Access from the 68040 using a 32bit data path

•

One boot EPROM for local booting, initialization of the I/O chips and configuration of the
FGA-002

•

1 28 Kbyte SRAM with on-board battery backup

•

1 28 Kbyte FLASH EPROM

•

FLXi interface for installation of one EAGLE module

•

Four Serial I/O interfaces, configurable as RS232/RS422/RS485, available on the front panel

•

8-bit parallel interface with 4-bit handshake

•

Two 24-bit timers with 5-bit prescaler

•

One 8-bit timer

•

Real Time Clock with calendar and on-board battery backup

•

Full 32-bit VMEbus master/slave interface, supporting the following data transfer types:
•
•
•

A32, A24, A 16 : 08, 016, D32 - Master
A32, A24: 08,016,032 - Slave
UAT. RMW, ADO

1
I

I!

"'T

INTRODUCTION

SECTION 1

Features of the CPU Board (cont'd)
•

Four-level VMEbus arbiter

•

SYSCLK driver

•

VMEbus interrupter OR 1-7)

•

VMEbus interrupt handler (lH 1-7)

•

Support for ACFAIL * and SYSFAIL

•

Bus timeout counters for local and VMEbus access (1 5 psec)

•

VMEPROM, Real Time Multitasking Kernel with monitor, file manager and debugger

1-5

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

The following table summarizes the memory map of the CPU board.

Table 1-1 : The Memory Map

I

I

II

Start
Address

End
Address

00000000
00000000
00000000

003FFFFF
007FFFFF
OOFFFFFF

Shared Memory (4 Mbyte)
Shared Memory (8 Mbyte) or
Shared Memory (1 6 Mbyte)

I

00400000

F9FFFFFF

VMEbus Addresses (4 Mbyte Shared Memory)

I

Type

A~~.

Mv~.

n~~

Uv~,

~~A

~~~

U~~,UIO,

~n

uo

00800000

F9FFFFFF

VMEbus Addresses (8 Mbyte Shared Memory)
A32: 032, 024, 016, 08

II

01000000

F9FFFFFF

VMEbus Addresses (16 Mbyte Shared Memory)
A32: 032, 024, 016, 08

I

FAOOOOOO

FAFFFFFF

Message Broadcast Area

FBOOOOOO

FBFEFFFF

VMEbus
A24: 032,024,016,08

FBFFOOOO

FBFFFFFF

VMEbus
A16: 032, 024,016, 08

FCFEFFFF

VMEbus
A24: 016, 08

FCFFOOOO

FCFFFFFF

VMEbus
A16: 016,08

FOOOOOOO

FEFFFFFF

Reserved

FFOOOOOO

FF7FFFFF

SYSTEM EPROM

FF800000

FFBFFFFF

Local I/O

FFCOOOOO

FFC7FFFF

LOCAL SRAM

FFC80000

FFCFFFFF

Local FLASH EPROM

FFOOOOOO

FFOFFFFF

Registers of FGA-002

FFEOOOOO

FFEFFFFF

BOOT EPROM

FF803EOO

FF803FFF

VMEbus Arbiter

FFFOOOOO

FFFFFFFF

Reserved

FCOOOOOO

I

1-6

I

SECTION 1

INTRODUCTION

This table gives a brief overview of the local I/O devices and the equivalent base address.

Table 1-2: The Base Addresses of the Local 110 Devices

BASE ADDRESS

$FF803000
$FF802000
$FF802200
$FF800COO
$FF800EOO

DEVICE

RTC
DUSCC1
DUSCC2
PIIT1
PIIT2

1-7

72423
68562
68562
68230
68230

This page was intentionally left blank

INTRODUCTION

SECTION 1

2. THE PROCESSOR
2.1 The CPU 68040
The 68040 is a third generation full 32 bit enhanced microprocessor. The 68040 is upward object
code compatible with the 68030, 68020, 68010 and 68000 line of microprocessors.
The 68040 combines a central processing unit core, an instruction cache, a data cache, a memory
management unit, and an enhanced bus controller.
This virtual memory processor utilizes multiple, concurrent execution units and a highly integrated
architecture providing a high level of performance.
The 68040 processor combines a 68030 compatible integer unit, a 68881/68882 compatible
floating point unit (FPU), memory management units (MMUs), and a 4 Kbyte instruction and data
cache. Cache functionality is strengthened by the built-in on-chip bus snooping logic which instantly
supports cache logic during multimaster applications.
Instruction administration is routed through both the integer unit and FPU, which link to the fully
independent data and instruction memory units. Each memory unit consists of an MMU an address
translation cache (ATC)' a main cache, and a snoop controller.
I

The internal blocks are designed to operate in parallel, allowing instruction execution to be
overlapped. In addition, the internal caches, the on-chip memory management unit, and the
enhanced bus controller operate parallel to one another.
The 68040 contains an enhanced bus controller that supports both synchronous/ asynchronous bus
cycles and burst data transfers. It contains a nonmultiplexed address bus and data bus and supports
32 bits of address and data.

2-1

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

Features of the 68040

•

Nonmultiplexed 32 bit address and data buses

•

1 6 general purpose address and data registers (32 bit wide)

•

8 floating point data registers (80 bit wide)

•

Two supervisor stack pointers (32 bit wide)

•

19 special purpose control registers

•

4 Kbyte instruction and 4 Kbyte data cache

•

On-chip paged memory management unit

•

Pipelined architecture with parallelism allowing accesses to internal caches, bus transfers, and
instruction execution in parallel

•

Synchronous bus cycles and burst read and write data transfers

•

Complete floating point support given to the 68882 FPCP subset and software emulation

•

68030 compatible

•

Low latency bus accesses to reduce cache miss penalty

•

Maximized throughput from the integer unit, FPU, MMU and bus controller

•

4 Gbyte direct addressing range

INTRODUCTION

SECTION 1

2.2 The Shared RAM
On this CPU board the shared RAM is placed on a module to allow the adaption of DRAM or SRAM
to the base board.
All signals which are needed to control the shared RAM are available on the RAM module connector.
Therefore RAM devices with different access times can also be used on this CPU board to take
advantage of the 68040 with higher frequency if it becomes available.

2.2.1 The DRM-01/4
The DRM-O 1/4 is a 4 Mbyte RAM module which is used on the CPU-40B/4.

Features of the DRM-O 1/4
•

4 Mbyte DRAM

•

Burst READ and Burst WRITE capability

•

Parity Generation and Checking

•

Asynchronous refresh is provided every 14J.ls

•

Accessible via VMEbus

The access address for the 68040 is $00000000 to $003FFFFF.
The access address for the VMEbus is programmable in 4 Kbyte steps through the FGA-002. The
defined memory range can be write protected in coordination with the address modifier codes. For
example, in supervisor mode the memory can be read and written, in user mode memory can only
be read.
The DRAM module includes byte parity check for local and VMEbus accesses. If a parity error is
detected on a VMEbus cycle, a BERR is forced to the VMEbus informing the requestor that a parity
error has occurred. On local accesses, a Transfer Error Acknowledge (TEA) is forced to the
processor if a parity error was detected.
The following chart lists the required CPU clock cycles and wait states for accessing the shared
RAM.
Board
Type

68040 Clock
Frequency

No. of CPU Clock
Cycles Counted
From TS to TA
for Normal Cycles

No. of CPU Clock
Cycles for
Burst Cycles

No. of Wait
States for
Normal Cycles

No. of Wait
States for
Burst Cycles

CPU-40/8

25 MHz

4

1

3

0

2-3

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

2.2.2 The DRM-01/16
The DRM-01/16 is a 16 Mbyte RAM module which is used on the CPU-40B/16.

Features of the DRM-O 1/16
•

1 6 Mbyte DRAM

•

Burst READ and Burst WRITE capability

•

Parity Generation and Checking

•

Asynchronous refresh is provided every 14ps

•

Accessible via VMEbus

The access address for the 68040 is $00000000 to $OOFFFFFF.
The access address for the VMEbus is programmable in 4 Kbyte steps through the FGA-002. The
defined memory range can be write protected in coordination with the address modifier codes. For
example, in supervisor mode the memory can be read and written, in user mode memory can only
be read.
The DRAM module includes byte parity check for local and VMEbus accesses. If a parity error is
detected on a VMEbus cycle, a BERR is forced to the VMEbus informing the requestor that a parity
error has occurred. On local accesses, a Transfer Error Acknowledge (TEA) is forced to the
processor if a parity error was detected.
The following chart lists the required CPU clock cycles and wait states for accessing the shared
RAM.
Board
Type

68040-B Clock
Frequency

No. of CPU Clock
Cycles Counted
From TS to TA
for Normal Cycles

No. of CPU Clock
Cycles for
Burst Cycles

No. of Wait
States for
Normal Cycles

No. of Wait
States for
Burst Cycles

CPU-40/B

25 MHz

4

1

3

0

2-4

INTRODUCTION

SECTION 1

2.2.3 The SRM-01/4
The SRM-O 1/4 is a 4 Mbyte RAM module which is used on the CPU-41 B/4.

Features of the SRM-O 1/4
•

4 Mbyte SRAM

•

Burst READ and Burst WRITE capability

•

Battery Backup via VMEbus

•

Accessible via VMEbus

The access address for the 68040 is $00000000 to $003FFFFF.
The access address for the VMEbus is programmable in 4 Kbyte steps through the FGA-002. The
defined memory range can be write protected in coordination with the address modifier codes. For
example, in supervisor mode the memory can be read and written, in user mode memory can only
be read.
Parity check is not necessary for SRAM devices, because these components are protected against
soft errors owing alpha emission. The following chart lists the required CPU clock cycles and wait
states for accessing the shared RAM.
Board
Type

68040 Clock
Frequency

No. of CPU Clock
Cycles Counted
From TS to TA
for Normal Cycles

No. of CPU Clock
Cycles for
Burst Cycles

No. of Wait
States for
Normal Cycles

No. of Wait
States for
Burst Cycles

CPU-41!S

25 MHz

3

1

2

0

2-5

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

2.2.4 The SRM-01/8
The SRM-01 /8 is an 8 Mbyte RAM module which is used on the CPU-41 B/8.

Features of the SRM-01 /8
•

8 Mbyte SRAM

•

Burst READ and Burst WRITE capability

•

Battery Backup via VMEbus

•

Accessible via VMEbus

The access address for the 68040 is $00000000 to $007FFFFF.
The access address for the VMEbus is programmable in 4 Kbyte steps through the FGA-002. The
defined memory range can be write protected in coordination with the address modifier codes.
For example, in supervisor mode the memory can be read and written, in user mode memory can
only be read.
Parity check is not necessary for SRAM devices, because these components are protected against
soft errors owing alpha emission. The following chart lists the required CPU clock cycles and wait
states for accessing the shared RAM.
Board
Type

68040 Clock
Frequency

No. of CPU Clock
Cycles Counted
From TS to TA
for Normal Cycles

No. of CPU Clock
Cycles for
Burst Cycles

No. of Wait
States for
Normal Cycles

No. of Wait
States for
Burst Cycles

CPU-41/B

25 MHz

3

1

2

0

2-6

INTRODUCTION

SECTION 1

2.3 The System EPROM
The CPU board offers two 40-pin EPROM sockets for the installation of two 16-bit wide EPROM
devices. The EPROMs present a full 32-bit data path to the processor enabling maximum
performance. The following devices are supported in the system EPROM area:

Supported Device Types in the System EPROM Area:
Total Memory Capacity

Organization

256 Kbytes
512 Kbytes
1 Mbyte
2 Mbytes

64K x 16
128Kx16
256K x 16
512K x 16

2.4 The Local SRAM
The CPU board contains a 1 28K * 8 bit SRAM. Battery backup is provided via the on-board battery
or the VMEbus + 5VSTDBY line.

2.5 The Local FLASH EPROM
A 128 Kbyte FLASH EPROM is included on the base board of the CPU-40 which can be used as
additional data backup under conditions of power down for long periods. FLASH EPROM is ideal to
hold details of the board status, such as software revision or user data which is to be kept
permanently.

2.6 The Boot EPROM
The CPU board contains, in addition to the two system EPROMs, a single boot EPROM to boot the
local microprocessor, initialize all I/O devices and program the board-dependent functions of the
FGA-002. All basic initialization of the I/O devices and the FGA-002 are made through the boot
EPROM.
In addition, the boot EPROM contains user utility routines, which may be called out of the user's
application program. These routines provide easy software access to the functionality of the
FGA-002 (DMA controller, FORCE Message Broadcast, Interrupt Management, etc.).

2-7

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

2.7 The FGA-002
One of the main features on this CPU board is the FGA-002 Gate Array with 24,000 gates and 281
pins. The FGA-002 controls the local bus and builds the VMEbus interface. It also ipcludes a DMA
controller, a complete interrupt handler, message broadcast interface (FMB), timer functions, mailbox
locations, and a VMEbus interrupter. This gate array monitors the local bus, which in turn signifies
that if any local I/O device is to be accessed, the gate array overrules all control signals, used
address signals, and data signals.
The FGA-002 serves as a VMEbus manager. All VMEbus address and data lines are connected to
the gate array through the buffers. Additional functions such as the VMEbus interrupt handler are
also installed on the FGA-002. The on-chip Drv1A controiler can access the iocai memory, VMEbus
memory, and on-board devices which are able to function in a DMA mode. The start address of the
FGA-002 registers is $FFDOOOOO. All registers of the gate array and associated functions are
described in detail in the FGA-002 Users Manual. On the following page you will find a list of
features for the FGA-002.

Features of the FGA-002
•

32 bit DMA Controller

•

2 Message Broadcast Channels (FMB)

•

8 Mailbox Interrupt Channels

•

One 8 bit timer

•

Complete Interrupt Management for VMEbus interrupts, ACFAIL, SYSFAIL, Onboard
Interrupts and FGA-002 internal interrupts

•

VMEbus interface including a single level arbiter

•

Decoding logic for accesses to the Shared Memory of the CPU board

A complete functional description of the FGA-002 may be found in the FGA-002 Users Manual.

2-8

INTRODUCTION

SECTION 1

2.8 The PIIT 68230
The MC68230 ParallellnterfacetTimer (PItT) provides versatile double buffered parallel interfaces and
an operating system oriented timer for MC68000 systems. The parallel interfaces operate in
unidirectional or bidirectional modes, 8 or 16 bits wide. The PItT timer contains a 24 bit wide
counter and a 5 bit prescaler.

Features of the PIIT
•

MC68000 Bus Compatible

•

Port Modes Include:

•

Selectable Handshaking Options

•

24 bit Programmable Timer

•

Software Programmable Timer Modes

•

Contains Interrupt Vector Generation Logic

•

Separate Port and Timer Interrupt Service Requests

•

Registers are ReadIWrite and Directly Addressable

Bit I/O
Unidirectional 8 bit and 1 6 bit
Bidirectional 8 bit and 16 bit

2-9

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

2.8.1 The 1/0 Configuration of PltT1
Port A is connected to the two 4 bit HEX rotary switches provided on the front panel for application
dependent settings.
Port B is used for programming the local base address for A24 accesses from the VMEbus.
Port C is used for port and timer interrupts and to control the RMC behavior of the board.

2.8.2 The 1/0' Configuration of PltT2
Port A and the handshake lines are routed to a 24-pin header which allows the connection of a flat
cable. 8 bits are connected to port A of the PI/T and can be used as inputs or outputs, with the
remaining 4 bits being connected to the handshake pins of the PI/T. This port can be used to
establish a "Centronics type" interface.
Port B allows the memory capacity of the Shared RAM to be read. Each CPU board of this type
contains three readable status bits describing the memory capacity. In addition, the CPU board type
can be read through the remaining 5 bits.
Port C grants the RAM type (DRAM/SRAM) burst and parity capability of the Shared RAM to be
read.
A "Powerup Reset" can be initiated by software.

2-10

INTRODUCTION

SECTION 1

2.9 The Real Time Clock 72423
There is a Real Time Clock (RTC) 72423 installed on the CPU board. The CPU board contains a self
supportive battery to sustain the RTC during power down.

Features of the RTC
•

Built-in quartz oscillator makes regulation unnecessary and allows easy design

•

Direct bus compatibility (120 ns access time)

•

Incorporated built-in time (hour, minute, second), and date (year, month, week, day) counters

•

12 hour and 24 hour clock switchover functions and automatic leap year setting

•

Interrupt masking

•

An error adjustment time function of 30 seconds

•

READ, WRITE, HOLD, STOP, RESET, and CHIP SELECT inputs

•

The C-MOS IC boasts low current consumption and features a backup function

•

A 24-pin so package

2-11

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

2.10 The DUSCC 68562
The Dual Universal Serial Communications Controller (DUSCC) 68562 is installed to communicate
with terminals, computers, or other equipment.
The DUSCC is a single chip MOS-LSI communications device providing two independent,
multi protocol, full duplex receiver/transmitter channels in a single package. Each channel consists
of a receiver, transmitter, 16-bit multifunction counter/timer, digital phaselocked loop (DPLL)'
parity/CRC generator and checker, and associated control circuits.

Features of the DUSCC
•

Dual full duplex synchronous/asynchronous receiver and transmitter

•

Multiprotocol operation consisting of:
BOP:
COP:
ASYNC:

HDLC/ADCCP, SDLC, SDLC Loop, X.25 or X.75 link level
BISYNC, DDCMP, X.21
5-8 bit plus optional parity

•

Programmable data encoding formats: NRZ, NRZI, FMO, FM1, Manchester

•

4 character receiver and transmitter FIFOs

•

Individual programmable baud rate for each receiver and transmitter

•

Digital phase locked loop

•

User programmable counter/timer

•

Programmable channel modes full/half duplex, auto echo, local loopback

•

Modem control signals for each channel: RTS, CTS, DCD

•

CTS and DCD programmable autoenables for Receiver (RX) and Transmitter (TX)

•

Programmable interrupt on change of CTS or DCD

2-i 2

INTRODUCTION

SECTION 1

2.10.1 The I/O Configuration of DUSCC1 and DUSCC2
The four channels may be configured to function as a RS232 or RS422/RS485 compatible interface.
Termination resistors can be installed to adapt various cable lengths and reduce reflections upon the
selection of the RS422/RS485 compatible interface. The DUSCC can interrupt the local CPU at a
specified programmable IRQ level.

I/O Signals for DUSCC1:
The I/O signal assignment of channel 1 to 2 is listed as follows:

Signal

Input

DCD
RXD
TXD
DTR
GND
DSR
RTS
CTS
GND

X
X

Output

X
X
X
X

X
X

9 Pin Micro
D-Sub Connector
1
2
3
4
5

6
7
8

9

2-13

Description

Data Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
Signal GND
Data Set Ready
Request to Send
Clear to Send
Signal GND

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

The I/O signals of channel 1 can be connected to the VME connector P2 in parallel to the 9-pin Micro
D-Sub connector as follows:

Signal

Input

Output

VME Connector

Description

P2

X

c29
c30
c31

v

vv4-

LJO lO

a29
a30
a31
a32

Data Set Ready
Request to Send
Clear to Send
Signal GND

X
X

DCD
RXD
TXD
f""I,O
LJ I 11

"

X

DSR
RTS
CTS
GND

X
X

X

,.,,')')

Data Carrier Detect
Receive Data
Transmit Data
F""'\",+", T""'r'Y"'!I.:~",1 0"",,..1 ...
I

vi 11111 101 I lC;OU

Y

NOTE
This is only possible if these VMEbus P2 lines are not used by an EAGLE module.

1/0 Signals for DUSCC2:

The I/O signal assignment of channels 3 and 4 is listed as follows:
Signal

Input

DCD
RXD
TXD
DTR
GND
DSR
RTS
CTS
GND

X
X

X
X

Output

9 Pin Micro
D-Sub Connector

1

2
X
X

3
4
5

X
X

6
7
8
9

2-'14

Description

Data Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
Signal GND
Data Set Ready
Request to Send
Clear to Send
Signal GND

INTRODUCTION

SECTION 1

2.11 The EAGLE Modules
EAGLE modules are 1/0 subsystems designed not only to increase the functionality of the board but
to add the exact 1/0 features to fit the application requirement. EAGLE modules connect directly
onto the FLXi of the base board. FLXi and EAGLE modules will be a feature on future FORCE board
generations to ensure continued flexibility.
If your CPU board is assembled with an EAGLE module please refer to the "EAGLE Module" manual
which is shipped with this board and should be placed in Section 6 of this manual.

2.12 The VMEbus Interface
The CPU board has a full 32-bit VMEbus interface. The address modifier codes for A 16, A24 and
A32 addressing are fully supported in master mode. In slave mode, the address modifiers for A32
and A24 are fully supported.
Read-Modify-Write cycles are fully supported to allow multiple CPU boards to be synchronized via
the shared RAM. The FGA-002 determines whether or not an access to the shared RAM is allowed
and, if allowed, controls the access cycle.
The CPU board provides an interrupt handler capability (I H 1-7) which can be enabled/disabled by
programming the FGA-002. The CPU board also provides an interrupter function which enables the
VMEbus on seven programmable levels with a softwareboard to send interrupts to the
programmable vector.
The following bus release modes are supported:
RWD
ROR
RBCLR
RAT
REC
ROACF

=
=
=
=
=
=

Release
Release
Release
Release
Release
Release

When Done
On Request
On Bus Clear
After Timeout
Every Cycle
On ACFAIL *

2-15

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

Each of the listed modes is software programmable inside the gate array. The bus request level of
the CPU board is jumper or software selectable (BRO-3).
The DMA controller installed in the FGA-002 on the CPU board is able to access the VMEbus
interface independently from the microprocessor, enabling VMEbus communication to take place
without impacting the processing capabilities of the rest of the board for number crunching or
servicing on-board I/O.
A four level arbiter with round robin and prioritized round robin arbitration modes, a power monitor,
a SYSRESET* generator, IACK* daisy chain driver and support for ACFAIL *, SYSFAIL * and SYSCLK
complete the VMEbus interface.

"

. ,..

'£-10

INTRODUCTION

SECTION 1

2.13 The Monitor of the CPU board
Every CPU board contains VMEPROM, a real time multitasking monitor debugger. It consists of a
powerful real time kernel, file manager and monitor/debugger with 68040 line
assembler/disassembler.
The monitor/debugger includes all functions to control the real time kernel and file manager as well
as all tools required for program debugging such as breakpoints, tracing, memory display, memory
modify and host communication.
VMEPROM supports several memory and I/O boards on the VMEbus to take full advantage of the
file manager and kernel functions.
A built-in selftest checks all on-board devices and memory. This allows detection of any failures on
the board.
Memory initialization and test commands offer easy installation of global memory in the environment
on the local RAM and/or the VMEbus.
The one line assembler/disassembler is 68040 compatible and supports all 68040 commands in the
original mnemonic described in the MC 68040 User's Manual.

2-17

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

2.14 Default Jumper Settings on the CPU Board
The following are the default jumper settings and a location diagram displaying all jumpers.
Default Jumper Settings for the CPU
Jumperfield

B2

B20

B1

Default
Connection

Schematics

Reset Voltage Sensor

---

SH4
B4

Backup Supply for Local SRAM and
RTC via + 5 VSTDBY

---

SH4

Backup Supply for Local SRAM and
RTC via Bat 1

1-2

Description

B2
SH4
B2

Default Jumper Settings for System EPROMs and SRAM/EEPROM
Jumperfield

Description

Default
Connection

Schematics

B11

System EPROM device select

1-6

SH5
A4

B16

FLASH EPROM write dis-tenable

1-2

SH4
C2

Default Jumper Settings for Serial 1/0 (RS232)
Jumperfield

Description

Default
Connection

Schematics

B3

Connector 1, PD 1
(DUSCC 1 Port # 1)

2-15
8-9

SH6
B2

B4

Connector 2, PD2
(DUSCC1 Port #2)

2-15
8-9

SH6
B3

B5

Connector 1, PD 1
(DUSCC1 Port #1)

---

SH6
C2

B6

Connector 2, PD2
(DUSCC Port #2)

---

SH6
C3

B7

Connector 3, PD3
(DUSCC2 Port #3)

2-15
8-9

SH7
B2

B8

Connector 4, PD4
(DUSCC2 Port #4)

2-15
8-9

SH7
B3

B9

Connector 3, PD3
(DUSCC2 Port #3), PD3

---

SH7
C2

Connector 4, PD4
(DUSCC Port #4), PD4

---

SH7
C3

B10

2-18

SECTION 1

INTRODUCTION

Default Jumper Settings for VMEbus
Description

Jumperfield

Default
Connection

Schematics

819

Four level Arbiter Request Level

1-6
2-5
3-4

SH9
84

813

SYSCLK
SYSFAIL
Receive VMEbus RESET
Drive VMEbus RESET

1-8
2-7
3-6
4-5

SH10
C2

Default
Connection

Schematics

1-2

SH16
A1

Default
Connection

Schematics

---

SH8
D1

Default Jumper Settings for Test
Jumperfield

817

Description

Clock Signal to CPU

Headers for 12 Bit 1/0 and 8 Bit 1/0
Jumperfield

812

Description

User I/O

2-19

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

Figure 2-1 : Location Diagram for All Jumperfields

o

D

D

D

J::fi

D
D~
JI9

o ~D

D~
2-20

D~

INTRODUCTION

SECTION 1

Figure 2-2: The Front Panel of the ·CPU Board

~1

,

!RESET
e

ABORT
RUN

G8M

@4
o

@3
o

@2
o
3

@1

4

5

6

EJ
EJ

1

7
8

o ___

o

F

9

E

A

DeB

3

4

5

1

o ___
F

A

DeB

MODULE

DEPENDENT

FORCE

o
2-21

7

8

9

E

EAGLE

6

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

This page intentionally left blank

2-22

INTRODUCTION

SECTION 1

3. SPECIFICATIONS OF THE CPU BOARD
68040

CPU Type
CPU Clock Frequency

CPU-40B/x
CPU-400/x

25.0 MHz
33.0 MHz

Shared DRAM Capacity with Parity

CPU-40X/4
CPU-40X/16

4 Mbytes
16 Mbytes

Shared SRAM Capacity

CPU-41 X/4
CPU-41 X/8

4 Mbytes
8 Mbytes

SRAM Capacity with On-board Battery Backup
FLASH EPROM

128 Kbytes
128 Kbytes

Number of System EPROM Sockets
Data Path

2
32-Bits

Serial I/O Interfaces (68562)
RS232/RS422/RS485 Compatible

4
4 of 4

24-bit Timer with 5-bit Prescaler
8-bit Timer

2
1

Parallel I/O Interface (68230)

12 Lines

Real Time Clock with On-board Battery Backup

72423

VMEbus Interface

A32, A24, A 16:08, 016, 032, UAT, RMW
A32, A24:08, 016, 032, RMW

Four Level Arbiter
SYSCLK Driver
Mailbox Interrupts

Master
Slave
Yes
Yes
8

FMB FIFO 0
FMB FIFO 1

FORCE Message Broadcast

8 Bytes
1 Byte

VMEbus InterrupterNMEbus and Local Interrupt Handler
All Sources can be Routed to a Software Programmable IRQ Level

1 to 7
Yes

RESET/ABORT Switch

Yes

VMEPROM Firmware Installed on All Board Versions

256 Kbytes

Power Requirements

+5V minImax

+ 12V minimax
-12V min/max

5.2A/6.0A
0.1A/0.3A
0.1A/0.3A
0 to + 50°C
-40 to + 85°C
0 to 95%
234x160mm/9.2x6.3in
1

Operating Temperature with Forced Air Cooling
Storage Temperature
Relative Humidity (noncondensing)
Board Dimensions
No. of Slots Used

3-1

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

This page intentionally left blank

3-2

INTRODUCTION

SECTION 1

4. ORDERING INFORMATION
SYS6SK/CPU-40B/4-00

25.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared DRAM, 4 serial
1/0 channels, FLXi, VMEPROM. Documentation included.

SYS6SK/CPU-40B/4-0 1

25.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared DRAM, 4 serial
1/0 channels, EAGLE-01 C (SCSI, floppy disk and Ethernet Interface),
VMEPROM. Documentation included.

SYS6SK/CPU-40B/1 6-00

25.0 MHz 68040 based CPU board with DMA, 16 Mbyte shared DRAM, 4 serial
110 channels, FLXi, VMEPROM. Documentation included.

SYS6SK/CPU-40B/16-01

25.0 MHz 68040 based CPU board with DMA, 16 Mbyte shared DRAM, 4 serial
110 channels, EAGLE-01 C (SCSI, floppy disk and Ethernet Interface),
VMEPROM. Documentation included.

SYS6SK/CPU-400/4-00

33.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared DRAM, 4 serial
110 channels, FLXi, VMEPROM. Documentation included.

SYS6SK/CPU-400/4-0 1

33.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared DRAM, 4 serial
110 channels, EAGLE-O 1C (SCSI, floppy disk and Ethernet Interface),
VMEPROM. Documentation included.

SYS6SK/CPU-400/16-00

33.0 MHz 68040 based CPU board with DMA, 16 Mbyte shared DRAM, 4 serial
liD channels, FLXi, VMEPROM. Documentation included.

SYS6SK/CPU-400/16-01

33.0 MHz 68040 based CPU board with DMA, 16 Mbyte shared DRAM, 4 serial
liD channels, EAGLE-01 C (SCSI, floppy disk and Ethernet Interface),
VMEPROM. Documentation included.

SYS6SK/CPU-41 B/4-00

25.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared SRAM, 4 serial
liD channels, FLXi, VMEPROM. Documentation included.

SYS6SK/CPU-418/4-01

25.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared SRAM, 4 serial
liD channels, EAGLE-01 C (SCSI, floppy disk and Ethernet Interface),
VMEPROM. Documentation included.

SYS6SK/CPU-41 B/S-OO

25.0 MHz 68040 based CPU board with DMA, 8 Mbyte shared SRAM, 4 serial
I/O channels, FLXi, VMEPROM. Documentation included.

SYS6SK/CPU-41 B/S-01

25.0 MHz 68040 based CPU board with DMA, 8 Mbyte shared SRAM, 4 serial
110 channels, EAGLE-01 C (SCSI, floppy disk and Ethernet Interface),
VMEPROM. Documentation included.

SYS6SK/CPU-41 0/4-00

33.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared SRAM, 4 serial
I/O channels, FLXi, VMEPROM. Documentation included.

SYS6SK/CPU-41 0/4-01

33.0 MHz 68040 based CPU board with DMA, 4 Mbyte shared SRAM, 4 serial
liD channels, EAGLE-O 1C (SCSI, floppy disk and Ethernet Interface),
VMEPROM. Documentation included.

SYS6SK/CPU-410/S-00

33.0 MHz 68040 based CPU board with DMA, 8 Mbyte shared SRAM, 4 serial
I/O channels, FLXi, VMEPROM. Documentation included.

4-1

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

SYS6SK/CPU-410/S-01

33.0 MHz 68040 based CPU board with DMA, 8 Mbyte shared SRAM, 4 serial
I/O channels, EAGLE-01 C (SCSI, floppy disk and Ethernet Interface),
VMEPROM. Documentation included.

SYS6SKIIOBP-1

Backpanel for single board computers providing SCSI and floppy disk drive
connectors.

SYS6SK/CABLE MICRO-9 SET 1

Set of three adapter cables 9-pin micro D-Sub male connector to 9-pin O-Sub
female connector, length 2 m.

SYS6SK/CABLE MICRO-9 SET 2

Set of four adapter cables 9-pin micro O-Sub male connector to 25-pin O-Sub
female connector, length 2 m.

SYS68KNMEPROM/40/U P

VMEPROM update service for the SYS68K/CPU-40 series.

SYS6SKNMEPROM/UM

VMEPROM User's Manual excluding the SYS68K/CPU-40 description.

SYS6SK/CPU-40/UM

User's Manual for the SYS68K/CPU-40 product, including VMEPROM User's
Manual and EAGLE-01 C User's Manual
(separately available as
EAGLE-01 C/UM).

SYS6SK/FGA-002/UM

User's Manual for the FGA-002 Gate Array.

4-2

HARDWARE USER'S MANUAL

SECTION 3

6.8 RESET Generation
There is an IEEE 1014 compatible SYSRESET* driver installed on the epu board. The RESET
generator circuitry is operable if the power supply vee is at least 3 volts. The RESET signal can be
asserted (low) on anyone of the following conditions:
•

Front Panel RESET switch toggled

•

Voltage Sensor detects

•

Execution of the RESET instruction by the microprocessor on the board

vee

below limit (4.8V)

The asserted RESET signal will be held low for at least 200 milliseconds after removing all the above
conditions.
When the Reset Switch is toggled twice a Powerup equivalent Reset can be generated. The time
lapse immediately after the Reset Switch is released must be 0,2 seconds or less.

6.8.1 The Front Panel RESET Switch
The upper switch on the front panel of the epu board is the RESET switch. Toggling it provides a
reset of all on-board devices, independent from the jumper options. With the jumper 813 3-6
connection inserted, the SYSRESET* signal of the VMEbus backplane will be asserted. When the
RUN LED is red, the processor is in the HALT state. For example, this state will be entered if a
double bus fault occurs. A reset of the board must be performed by toggling the RESET switch or
by asserting the SYSRESET* backplane signal. The light of the RUN LED is also red while the RESET
generator drives the reset. After reset, the red light must change to green.

6.8.2 The Voltage Sensor Module FH001
The voltage sensor module FHOO 1 is included with the RESET generator. Power up reset is provided
by this sensor, as soon as the supply voltage vee has reached 3 volts. RESET will be asserted if
vee is less than 4.8 volts on the board, once the jumper 82 pin 1-2 is removed (8). This jumper
is removed upon delivery. When the jumper at 82 1-2 is inserted (A), RESET will be asserted if vee
is less than 4.6 volts. RESET will stay asserted at least 200 milliseconds after the supply voltage
has passed the threshold. Jumperfield 82 pin 1-2 must be removed for normal operation, and may
be inserted for test purposes.

Figure 6-7: Jumper Settings for Jumperfield B2
A)

B2

4.6V

1

p:

0

2

B)

o

B2

4.8V
(default)

6-27

2

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

Figure 6-8: Location Diagram of Jumperfield 82

, "0

Ea~TI
~

0
o 10

AMPM5

I-

~

[JD~

~

II!

~

L..

l:I...DLJ

~
'---

~o~

HARDWARE USER'S MANUAL

SECTION 3

6.8.3 VMEbus RESET Conditions
6.8.3.1 Receive RESET from VMEbus
In order to receive a RESET from the VMEbus on the CPU board, jumper 813, 4-5 must be inserted.
If removed, the SYSRESET signal from the VMEbus is not monitored on the CPU board.

813
8

7

6

5

0

0

0

[:0

.:.:.:

0

0

0

1

2

3

4

I
I

[

6.8.3.2 Drive RESET to VMEbus
To drive the RESET signal on the VMEbus, jumper 813, 3-6 must be inserted on the CPU board.
When inserted, the RESET from the front panel switch and voltage monitor are driven to the
VMEbus. If not inserted, SYSRESET is not VMEbus driven.

813
8

7

6

5

0

0

0

I
I

[:

0

0

0

1

2

3

4

.:.~.:

[

6.8.3.3 Default Configuration of Jumperfield B13
By default, SYSCLK and SYSRESET are driven to the VMEbus; SYSRESET and SYSFAIL are
monitored by the CPU board.

813
8

7

6

5

0

0

0

0

I
6.:.:.:

I

I
I

I
I

0

0

0

1

2

3

4

6-29

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

Figure 6-9: Location Diagram of Jumperfield B 13

o

jr'-/"

0GI() ~-----.

~

D
[J
D

n

,Q0 11 D~
/
f'"

0
o

~D
.....

Pte

[JD~
6-30

..'~-

II

~

'-

~

~
'----

"-D~

HARDWARE USER'S MANUAL

SECTION 3

6.8.4 The RESET Instruction
The RESET instruction of the microprocessor is designed to reset peripherals under program control,
without resetting the processor itself. This instruction is fully supported by the CPU board. The
RESET instruction triggers the RESET generator and resets all peripherals on the board driving RESET
to low. At this point the processor on the CPU itself will not be reset. Therefore, program execution
will go on with the next operation code. If another board asserts SYSRESET* before this instruction
triggered reset is ended, then the processor will still not be reset because of a lockout logic.

6-31

This page was intentionally left blank

APPENDIX TO THE
HARDWARE USER'S MANUAL

This page was intentionally left blank

LIST OF APPENDICES
A.

SPECIFICATION OF THE CPU BOARD

B.

MEMORY MAP OF THE CPU BOARD

C.

ADDRESS ASSIGNMENT AND REGISTER LAYOUT OF THE 110 DEVICES

D.

PIN ASSIGNMENTS OF THE EPROM SOCKETS
D.1
Pin Assignment for EPROM Area

E.

CIRCUIT SCHEMATICS OF CPU BOARD
E.1
Circuit Schematics of DRM-01
E.2
Circuit Schematics of SRM-01

F.

DEFAULT JUMPER SETTINGS ON THE CPU BOARD

G.

CONNECTOR PIN ASSIGNMENT
G.1
J1/P1 Pin Assignments
G.2
J2/P2 Pin Assignments

H.

COMPONENT PART LIST

I.

GLOSSARY OF VME/1 014 TERMS

J.

LITERATURE REFERENCE

K.

PRODUCT ERROR REPORT

This page is intentionally left blank.

APPENDIX TO THE HARDWARE USER'S MANUAL

SECTION 4

APPENDIX A
SPECIFICATIONS OF THE CPU BOARD
68040

CPU Type
CPU Clock Frequency

CPU-40B/x
CPU-40D/x

25.0 MHz
33.0 MHz

Shared DRAM Capacity with Parity

CPU-40X/4
CPU-40X/16

4 Mbytes
16 Mbytes

CPU Clock Frequency

CPU-41 Blx
CPU-41D/x

25.0 Mhz
33.0 MHZ

Shared SRAM Capacity

CPU-41 X/4
CPU-41 X/8

4 Mbytes
8 Mbytes

SRAM capacity with On-board Battery Backup
FLASH EPROM

128 Kbytes
128 Kbytes

Number of System EPROM Sockets
Data Path

2
32-bits

Serial 1/0 Interfaces (68562)
RS232/RS422/RS485 Compatible

4
4 of 4

24-bit Timer with 5-bit Prescaler
8-bit Timer

2
1

Parallel I/O Interface (68230)

12 lines

Real Time Clock with On-board Battery Backup

72423

VMEbus Interface

A32, A24, A 16:08, 016, 032, UAT, RMW
A32, A24:D8, 016, 032, RMW

Master
Slave
Yes
Yes
8

Four Level Arbiter
SYSCLK Driver
Mailbox Interrupts
FMB FIFO 0
FMB FIFO 1

FORCE Message Broadcast

8 bytes
1 byte

VMEbus InterrupterNMEbus and Local Interrupt Handler
All Sources can be Routed to a Software Programmable IRQ Level

1 to 7
Yes

RESET/ABORT Switch

Yes

VMEPROM Firmware Installed on All Board Versions

256 Kbytes

TO BE CONTINUED

A-1

SYS68K/CPU-40/41

FORCE COMPUTERS

SPECIFICATIONS OF THE CPU BOARD CONTINUED

Power Requirements

+5V min/min
+ 12V min/max
-12V min/max

5.2A/6.0A
0.1 A/0.3A
1.0A/0.3A

o to

+50 o C
-40 to +85C
o to 95%
234x160mm/9.2x6.3in
1

Operating Temperature with Forced Air Cooling
Storage Temperature
Relative Humidity (noncondensing)
Board Dimensions
No. of Slots Used
I

-- -

A-2

II

INTRODUCTION

SECTION 1

5. HISTORY OF MANUAL REVISIONS

Description

Revision No.

Date of Last Change

0

First Print.

FEB/05/1991

1

The following sections/pages have been changed:

APR/16/1991

Section 1:
Page 2-16 (EPROM Description)
Section 3:
Pages 3-11,3-12,3-14,3-15 (EPROM Description)
Section 4:
Page F-1 (EPROM Description)
Sections 7, 8, and 9:
These have been changed to adapt to
VMEPROM Version 2.74
Section 1:

AUG/23/1991

Chapter 3: Power Requirements for
from 0.1 A/0.5A to 0.1 A/0.3A

+

12V changed

Section 3:
Chapter 3.9.4 has been eliminated.
Chapter 3.9.12: New Board Identification.
Chapter 3.9.16: 1 and 0 were switched.

2

Rework for PCB Revision 2

FEB/03/1992

5-1

This page was intentionally left blank

INSTALLATION

This page was intentionally left blank

WARNING

TO AVOID MALFUNCTIONS AND COMPONENT DAMAGES, PLEASE
READ THE COMPLETE INSTALLATION PROCEDURE BEFORE THE
BOARD IS INSTALLED IN A VMEBUS ENVIRONMENT.

This page was intentionally left blank

TABLE OF CONTENTS

1.

GENERAL OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

1-1

1. 1

The Rotary Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

1-1

1.2

The Function Switch Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "

1-1

1 .3

Connection of the Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-3

1.4

The Default Hardware Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-4

2.

INSTALLATION IN THE RACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1

2.1

Power ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1

2.2

Correct Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

2-2

3.

ENVIRONMENTAL REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

LIST OF FIGURES
Figure 1-1:
Figure 1-2:

Front Panel of CPU Board and the Rotary Switch Positions .............
Pinout of the Micro D-Sub and D-Sub Connector for RS232 . . . . . . . . . . . ..

1-2
1-4

This page was intentionally left blank

ii

INSTALLATION

SECTION 2

1. GENERAL OVERVIEW
Easy installation of the CPU board is provided since the memory map, the I/O devices, and the
interfaces are configured to communicate with a standard terminal containing RS232 interface.
The monitor (VMEPROM) boots up automatically with the setup of the rotary switches on the front
panel.

1 . 1 The Rotary Switches
Two rotary switches are installed on the CPU board to configure the startup of the VMEPROM or
a user program.
The following lists the default configuration for bootup.

II

Switch

Hex Code

2
1

$F
$F

II

The different functions of the rotary switches are described in detail in the Introduction to
VMEPROM as well as in the Hardware User's Manual of this particular CPU board.

1.2 The Function Switch Positions
The CPU board contains two function switches. These two switches are defined as RESET and
ABORT. The RESET switch is located in the first and upper position, and the ABORT switch is
located directly underneath in the second and lower position.
The two moveable positions of these switches are defined as "Up" and "Down".
ll

All function switches must be set to the position "Down upon performing initial installation.
Please toggle each of the switches before installing the board in the rack in order to detect
mechanical damages to the switches during transport.

1-1

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

Figure 1 -1: Front Panel of CPU Board and the Rotary Switch Positions

0
~1

,•
t

•

RESET
ABORT

RUN
8M

4

3

2

@1

8
8

1

7
8

o ___

0

F

E

9

'A

DeB

1

7
8

o ___

Q9

F

E

EAGLE

DeB

MODULE

DEPENDENT

x
FORCE

o
1-2

9

'A

INSTALLATION

SECTION 2

1.3 Connection of the Terminal
The terminal must be connected to the 9-pin Micro D-Sub connector 1 on the CPU board.
The board is delivered with a 9-pin Micro D-Sub to 9-pin D-Sub adapter cable.
The following communication setup is used for interfacing the terminal.
terminal to this setup.

Please configure the

No Parity
8 Bits per character
1 Stop Bit
9600 Baud
Asynchronous Protocol
The hardware interface is RS232 compatible. The following signals are supported on the 9-pin Micro
D-sub connector on the front panel:
Signal

Input

DCD
RXD
TXD
DTR
GND
DSR
RTS
CTS
GND

X
X

Output

X

9 Pin Micro
D-Sub Connector

X
X

2
3
4
5
6
7
8
9

X
X

X
X
X

Description

Data Carrier Detect
Receive Data
Transmit Data
Data Terminal R~ady
Signal GND
Data Set Ready
Request to Send
Clear to Send
Signal GND

1

X
X
X

Required

9 Pin D-Sub of the
Adapter Cable

1
2
3
4

5
6
7
8
9

CAUTION
1)

The terminal used must not drive a signal line which is marked to be an output of
CPU board.

2)

All signals marked as "Required" must be supported from the terminal to enable
the transmission.

3)

If the terminal is configured to the listed setup, please connect the 9-pin Micro DSub connector to the terminal with a cable which supports all of the required
signals.

1-3

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

Figure 1-2: Pinout of the Micro D-Sub and D-Sub Connector for RS232
A) Micro DSUB Male Connector Soldered
on the CPU Board

OSR
RTS

RS232

RS232

Pa

Pa

~
60

.
02

DCD
GND
CTS

90

RTS
OTR

04

OTR

03

TXD

02

RXD

80

TXD

80
04

~GND

RXD

70
03

CTS

B) Micro DSUB and DSUB Female Connectors
on the Adapter/Terminal Cable

70

DSR

GNO

DCD

GND

1-4

INSTALLATION

SECTION 2

1.4 The Default Hardware Setup
The VMEbus interface is configured to be used immediately, without any changes.
This results in a default hardware setup which may conflict with other boards installed in the rack.
The following signals are driven/received from the CPU board:

Signal

SYSCLK
BR3*
BR[3 .. 0] *
BG[3 .. O]OUT *
ACFAIL*
SYSFAIL *
SYSRESET*

Driven

Received

X
X
X
X
X
X
X

X

From

FGA-002 Gate Array
FGA-002 Gate Array
4 Level Arbiter
4 Level Arbiter
FGA-002 Gate Array
FGA-002 Gate Array
FGA-002 Gate Array

CAUTION
1)

The on-board four level arbiter is enabled and reacts on every Bus Request * .

2)

The CPU board is configured as a slot 1 controller.

1-5

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

This page intentionally left blank

1-6

INSTALLATION

SECTION 2

2. INSTALLATION IN THE RACK
The CPU board can immediately be mounted into a VME rack at slot 1.

CAUTION
1)

Switch off power before installing the board to avoid electrical damage to the
components.

2)

The CPU board contains a special ejector (the handles).
The board must be plugged in, and the screws on the front panel tightened up to
guarantee proper installation.

3)

Unplug every other VMEbus board to avoid conflicts.

2.1 Power ON
Power to the VMEbus rack may be switched on when the board is correctly installed, the switches
are in the correct positions, and the terminal is correctly configured and under power.
Initially, the green RUN LED will light up, and after one to three seconds the message "Wait until
hard disk is up to speed" will be displayed. A few seconds later the VMEPROM banner should
appear.
The terminal is now at the user's discretion. At this point, it is advised to make a few carriage
returns, to obtain the question mark (? J prompt.

2-1

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

2.2 Correct Operation
To test the correct operation of the CPU board, the following command must be typed in:

? SELFTEST < cr >
It is a matter of a few seconds until all tests are completed. Once all tests are completed, the
following messages will appear on the screen:

VMEPROM Hardware Selftest

1/0 test ...... passed
Memory test ..... passed
Clock test ...... passed

Any errors will be reported as they occur.

If an error message is displayed, please refer to Section 7, "Introduction to VMEPROM" containing
the command description" SELFTEST" .

2-2

INSTALLATION

SECTION 2

3. ENVIRONMENTAL REQUIREMENTS
This board was specified and tested for reliable operation under certain environmental conditions.
Based on our performance tests, this board is capable of operating with.in the temperature range of
O°C to 50°C when used inside of a FORCE TARGET-32 chassis. The following chart details the
calculated rate of forced air cooling.

Rate of Forced Air Cooling
Total Air Cooling - Target-32

Air Cooling per Board

131 CFM = 0.062 cubic meter/sec
= 0.0026 cubic meter/sec
275 LFM = 1.4 meter/sec
275 LFM* * = 1.4 meter/sec
* CFM = Cubic Feet per Minute ** LFM = Linear Feet per Minute
5.5 CFM*

The TARGET-32 chassis performs forced air cooling using four axial fans. The amount of airflow
needed for cooling and normal operation is reflected by certain factors such as ambient temperature,
number and location of boards in the system, and outside heat sources. Sufficient air cooling is
normally obtained when 5.5 CFM and 275 LFM is circulating around each board at an ambient
temperature between O°C and 50°C. Allowable storage temperatures may range between -40°C and
85°C. The rate of relative humidity (non-condensing) should not be less than 50/0, and should not
exceed 950/0. The following illustration is a pictorial view of the fan placement in the chassis.

TARGET-32
20 SLOTS AVAILABLE FOR 20 BOARDS

3-1

This page was intentionally left blank

HARDWARE USER'S MANUAL

This page was intentionally left blank

TABLE OF CONTENTS
1.

GENERAL INFORMATION

........•..•....••..•........••••••..

1-1

2.

THE PROCESSOR . . . . . . . . . . . . . . . . . • • . . . . . . . . . . . . . . . . . . . . • • .

2-1

2.1
2.1.1
2.1.1.1

The CPU 68040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Interface of the 68040 ................ ".............. .
General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1
2-1
2-1

2.2

The Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1

2.3

Vector Table of the 68040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-2

3.

THE LOCAL BUS

.......................••...............•.

3-1

3.1

The FGA-002 Gate Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
3.2.10
3.2.11
3.2.12
3.2.13
3.2.14

The Shared RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2
General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2
3-2
Shared RAM Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4
The DRM-01/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAM Type Information for the DRM-O 1/4 . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Summary of the DRM-O 1/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5
The DRM-O 1/16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6
RAM Type Information for the DRM-O 1/16 . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3-7
Summary of the DRM-O 1/1 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The SRM-01 /4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-8
RAM Type Information for the SRM-O 1/4 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Summary of the SRM-O 1/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-9
3-10
The SRM-01 /8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-11
RAM Type Information for the SRM-01 /8 . . . . . . . . . . . . . . . . . . . . . . . . .
3-11
Summary of the SRM-O 1/8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5

The System EPROM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Organization of the System EPROM Area . . . . . . . . . . . . . . . . . .
Usable Device Types for the EPROM Area . . . . . . . . . . . . . . . . . . . . . . . .
Access Time Selection of the System EPROM Area . . . . . . . . . . . . . . . . . .
Address Map of the System EPROM Area . . . . . . . . . . . . . . . . . . . . . . . .
Summary of the EPROM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-12
3-12
3-15
3-18
3-18
3-18

3.4
3.4.1

The FLXibus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction to the FLXibus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-19
3-19

3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6

The Local FLASH EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Organization of the FLASH EPROM . . . . . . . . . . . . . . . . . . . . . . .
Programming the FLASH EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Map of the FLASH EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of the Local FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . .
Jumper Settings for B 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Location Diagram of Jumperfield B 16 . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-20
3-20
3-21
3-21
3-21
3-21
3-22

3.6
3.6.1
3.6.2
3.6.3

The Loc.al SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ .
Memory Organization of the User SRAM . . . . . . . . . . . . . . . . . . . . . . . . .
The Address Map of the SRAM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of the SRAM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-23
3-23
3-26
3-26

3.7
3.7.1

The Boot EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of the Boot EPROM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-27
3-27

3.8
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5

3-29
3-30
3-32
3-38
3-38
3-45

3.8.7
3.8.8
3.8.9
3.8.10
3.8.11
3.8.12

The DUSCC 68562 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Map of the DUSCC 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
RS232 Hardware Configuration of Port #1 and #2 . . . . . . . . . . . . . . . . . .
Cable for the Micro D-Sub Connector . . . . . . . . . . . . . . . . . . . . . . . . . . .
RS422/RS485 Hardware Configuration of Ports #1 and #2 ........... .
RS232 and RS422/RS485 Driver Modules FH002 and FH003 ......... .
Summary of DUSCC 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Map of the DUSCC2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
RS232 Hardware Configuration of Ports #3 and #4 ................ .
Cable for the Micro D-Sub Connector . . . . . . . . . . . . . . . . . . . . . . . . . . .
RS422/RS485 Hardware Configuration of Port #3 and #4 ............ .
RS232 and RS422/RS485 Driver Modules FH002 and FH003 ......... .
Summary of DUSCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
3.9.6
3.9.7
3.9.8
3.9.9
3.9.10
3.9.11
3.9.12
3.9.13
3.9.14
3.9.15
3.9.16
3.9.17
3.9.18
3.9.19
3.9.20
3.9.21

The PI/T 68230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Map of the PI/T 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Configuration of PI/T1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rotary Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lock Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A24 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of PI/T1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Map of the PI/T2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110 Configuration of PI/T2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Size Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Board Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Request Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 Bit I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAM Module Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer IRQ/Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable A24 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of PI/T2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-59
3-60
3-61
3-62
3-64
3-65
3-65
3-65
3-66
3-67
3-68
3-69
3-69
3-69
3-70
3-72
3-72
3-73
3-73
3-73
3-74
3-74

3.10
3.10.1
3.10.2
3.10.3

The Real Time Clock (RTC) 72423 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Map of the RTC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-75
3-75
3-75
3-79

3.8.6

ii

.
.
.
.

3-45
3-46
3-48
3-52
3-52
3-58
3-58

4.

FUNCTION SWITCHES AND INDICATION LEOs ••.•..............•..

4-1

4.1

RESET Function Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1

4.2

ABORT Function Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1

4.3

IIRUN II LED

............................................. .

4-2

4.4

IIBM" LED

.............................................. .

4-2

4.5

Rotary Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-2

5.

THE CPU BOARD INTERRUPT STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . .

5-1

6.

VMEBUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-1

6.1
6.1.1
6.1.2

VMEbus Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transfer Size of the VMEbus Interface . . . . . . . . . . . . . . . . . . . . . . . .
Address Modifier Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-1
6-1
6-4

6.2
6.2.1
6.2.2
6.2.3

VMEbus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Access Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transfer Size of the Shared RAM . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Modifier Decoding and A24 Slave Mode . . . . . . . . . . . . . . . . . . . .

6-8
6-8
6-8
6-8

6.3

The VMEbus Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-11

6.4
6.4.1
6.4.2
6.4.3
6.4.3.1
6.4.3.2
6.4.3.3
6.4.3.4
6.4.3.5
6.4.3.6
6.4.3.7

VMEbus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Four Available VMEbus Arbiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The On-Board Four Level Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The VMEbus Release Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Release Every Cycle (REC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Release on Request (ROR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Release After Timeout (RAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Release on Bus Clear (RBCLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Release When Done (RWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Release Voluntary (RV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Release on ACFAIL (ACFAIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

.
.
.
.
.
.
.
.
.
.
.

6-12
6-12
6-12
6-18
6-18
6-18
6-18
6-19
6-19
6-19
6-19

6.5
6.5.1
6.5.2

The VMEbus Interrupter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Interrupt Generation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-21
6-21
6-22

6.6

The SYSCLK Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '...... .

6-23

6.7

Exception Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-25

6.8
6.8.1
6.8.2
6.8.3
6.8.3.1

RESET Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Front Panel RESET Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Voltage Sensor Module FHOO 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VMEbus RESET Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive RESET from VMEbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-27
6-27
6-27
6-29
6-29

iii

.
.
.
.
.

6.8.3.2
6.8.3.3
6.8.4

Drive RESET to VMEbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Configuration of Jumperfield 813 . . . . . . . . . . . . . . . . . . . . . . . .
The RESET Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

6-29
6-29
6-31

LIST OF FIGURES
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure

2-1 :
2-2:
3-1:
3-2:
3-3:
3-4:
3-5:
3-6:
3-7:
3-8:
3-9:
3-10:
3-11 :
3-12:
3-13:
3-14:
3-15:

Figure 3-16:
Figure
Figure
Figure
Figure
Figure

3-17:
3-18:
3-19:
3-20:
3-21 :

Figure 3-22:
Figure 3-23:
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure

3-24:
3-25:
3-26:
3-27:
4-1:
6-1:
6-2:
6-3:
6-4:
6-5:
6-6:
6-7:
6-8:
6-9:

Jumper Setting for B 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Location Diagram of Jumperfields B 17 . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Organization of the System EPROM Area . . . . . . . . . . . . . . . . . .
Location Diagram of the System EPROM Area . . . . . . . . . . . . . . . . . . . . .
Configuration Jumper Settings of System EPROM Area Jumperfield 811 .. .
Location Diagram of Jumperfield B11 Configuration of .the System EPROM
Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Location Diagram of the Backup Supply Jumperfield 81 and B20 ....... .
Location Diagram of the Boot EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . .
Location Diagram of the on Resistors R563 to R569 . . . . . . . . . . . . . . . .
RS232 Connection Between DUSCC1 and VMEbus Connector P2 ...... .
RS232 Connection Between DUSCC 1 and Micro D-Sub Connector ...... .
Pinout of the Micro D-Sub and D-Sub Connector for RS232 ........... .
Location Diagram of RS232 Configuration Jumperfields B3, B4, B5, and B6
Location Diagram of the on Resistors R563 to R569 . . . . . . . . . . . . . . . .
RS422/RS485 Connection between DUSCC1 and VMEbus Connector P2 ..
RS422/RS485 Pinout of the Micro D-Sub and D-Sub Connectors ....... .
Location Diagram of RS422/RS485 Configuration Jumperfields B3, 84, 85, and
86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Location Diagram of RS232/RS422/RS485 Driver/Receivers J20 and J21 plus
Resistor Arrays J22 and J23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connection Between DUSCC2 and D-Sub Connector for RS232 ........ .
Location Diagram of RS232 Configuration Jumperfields 87 through B 10 .. .
RS232 Pinout of the Micro D-Sub and D-Sub Connectors ............ .
Connection between DUSCC2 and Micro D-Sub Connector for RS422/RS485
Location Diagram of RS422/RS485 Configuration Jumperfields 87 through
B10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RS422/RS485 Pinout of the Micro D-Sub and D-Sub Connectors ....... .
Location Diagram of RS232/RS422/RS485 Driver/Receiver J25/J26 and
Resistor Arrays J27/J28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Board Front Panel and Rotary Switch Positions . . . . . . . . . . . . . . . . .
Location Diagram of Header B 1 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Location Diagram of the Backup Supply Jumperfield B1 and B20 ....... .
Front Panel of the CPU Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Requester/Arbiter Jumperfield B 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Location Diagram of Jumperfield 819 . . . . . . . . . . . . . . . . . . . . . . . . . . .
Usage of Jumperfield B13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Location Diagram of B 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Usage of Jumperfield 813 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Location Diagram of Jumperfield B 13 . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jumper Settings for Jumperfield B2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Location Diagram of Jumperfield B2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Location Diagram of Jumperfield 813 . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

2-3
2-4
3-12
3-13
3-16
3-17
3-25
3-28
3-34
3-35
3-35
3-35
3-37
3-40
3-41
3-42
3-43
3-44
3-49
3-50
3-51
3-53
3-54
3-55
3-57
3-63
3-71
3-76
3-78
4-3
6-16
6-17
6-23
6-24
6-25
6-26
6-27
6-28
6-30

LIST OF TABLES
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Tabie
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table

Exception Vector Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Map of the EPROM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial I/O Port # 1 (DUSCC 1) Register Address Map . . . . . . . . . . . . . . . . . .
Serial I/O Port #2 (DUSCC 1) Register Address Map ... ~ ............. .
Ports #1 and #2 (DUSCC1) Common Register Address Map .......... .
Default Setting of RS232 Configuration Jumperfields ............... .
RS422/RS485 Configuration Jumperfield Settings . . . . . . . . . . . . . . . . . .
PCB Locations for the RS232/RS422/RS485 Configuration ........... .
Serial I/O Port #3 (DUSCC2) Register Address Map . . . . . . . . . . . . . . . . . .
Serial I/O Port #4 (DUSCC2) Register Address Map . . . . . . . . . . . . . . . . . .
Ports #3 and #4 (DUSCC2) Common Registers Address Map .......... .
Default Setting of the RS232 Configuration Jumperfields ............ .
3-i 2: RS422iRS485 Configuration jumperfieid Setting . . . . . . . . . . . . . . . . . . .
3-13: PCB Locations for RS232/RS422/RS485 Configuration .............. .
3-14: PltT1 Register Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-15: PltT1 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-16: PltT2 Register Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-18: PltT2 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-17: RTC Register Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1:
Data Bus Size of the VMEbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Defined VMEbus Transfer Cycles (032 Mode) . . . . . . . . . . . . . . . . . . . . . .
6-2:
Defined VMEbus Transfer Cycles (016 Mode) . . . . . . . . . . . . . . . . . . . . . .
6-3:
6-4:
Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Modifier Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-5:
6-6:
Address Modifier Codes Used on the CPU Board . . . . . . . . . . . . . . . . . . . . .
6-7:
VMEbus Slave AM Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-8:
VMEbus Arbiter IRequester Register Layout . . . . . . . . . . . . . . . . . . . . . . .
6-9:
Description of Arbiter/Requester Register Bits . . . . . . . . . . . . . . . . . . . . .
6-10: Bit Settings for VMEbus Request Level . . . . . . . . . . . . . . . . . . . . . . . . . .
6-11 : Bit Settings for VMEbus Arbiter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-12: Bus Release Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-13: VMEbus Interrupter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-14: Description of the IRQ Generation Register . . . . . . . . . . . . . . . . . . . . . . .

2-1:
3-1:
3-2:
3-3:
3-4:
3-5:
3-6:
3-7:
3-8:
3-9:
3-10:
3-11:

Vi

2-2
3-18
3-30
3-31
3-31
3-38
3-41
3-42
3-46
3-47
3-48
3-51
3-55
3-56
3-60
3-61
3-67
3-68
3-75
6-2
6-3
6-3
6-4
6-5
6-7
6-10
6-13
6-13
6-14
6-15
6-20
6-21
6-22

HARDWARE USER'S MANUAL

SECTION 3

1. GENERAL INFORMATION
This CPU board is a high performance single board computer based on the 68040 microprocessor
and the VMEbus. The board incorporates a modular I/O subsystem which provides a high degree
of flexibility for a wide variety of applications. The CPU board can be used with or without an I/O
subsystem, called an "EAGLE" module.
The board is able to hold a RAM Module which can be DRAM (CPU-40) or SRAM (CPU-41) based.
The CPU-40/41 family design utilizes all of the features of the powerful FORCE Gate Array
(FGA-002). Among its features is a 32-bit DMA controller which supports local (shared) memory,
VMEbus and 110 data transfers for maximum performance, parallel real time operation and
responsiveness.
The EAGLE modules are installed on the CPU board via the FLXi (FORCE Local eXpansion interface).
This provides a full 32-bit interface between the base board and the EAGLE module I/O subsystem,
providing a range of I/O options.
Four multi protocol serial I/O channels, a parallel 110 channel and a Real Time Clock with on-board
battery backup are installed on the base board which, in combination with EAGLE modules, make
the CPU board a true single board computer system.
A broad range of operating systems and kernels is available for the CPU board. However, as with
all FORCE COMPUTERS' CPU cards, VMEPROM firmware is provided with the board at no extra
cost. VMEPROM is a Real Time Kernel and is installed on the CPU board in the 16-bit wide EPROM
sockets, which results in a 32-bit wide System EPROM area. This ensures that the board is supplied
ready to use.

1-1

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

This page intentionally left blank

...

"')

1-'

HARDWARE USER'S MANUAL

SECTION 3

2. THE PROCESSOR
2.1 The CPU 68040
2.1 . 1 Hardware Interface of the 68040
The 68040 uses a nonmultiplexed 32-bit address and 32-bit data bus. The 68040 does not support
the dynamic bus sizing like the 68020 or 68030. On this CPU board the dynamic bus sizing is built
in external hardware (two programmable gate arrays). This means if the 68040 does a long word
read from a byte device, the external hardware will fetch 4 bytes from this byte wide device, from
a long word and acknowledge the access cycle to the 68040. Therefore all device drives within the
68020 or 68030 can be used on this CPU board. Please note that the 68040 has a 4 Kbyte
instruction and a 4 Kbyte data cache which may cause problems.

2. 1 . 1 . 1 General Operation
The CPU drives the address lines (AO-A31 ), the size lines (SIZO, SIZ 1 ) the transfer type (TTO-TT 1)
on every cycle, and modifier (TMO-2) signals independent of a cache hit or miss. These signals are
used to decode the memory map of the CPU board.
The transfer start (TS) signals the hardware on the CPU board that the current cycle is not a cache
cycle, and that the decoding outputs are valid.
The 32 data lines (00-031) are also driven from the processor on write cycles and sensed on read
cycles.
The size of the data transfer is defined by the SIZE output signals (always driven from the CPU when
master). The transfer acknowledge or the transfer error acknowledge signal (TA, TEA) or both
terminate the transfer cycle. CPU 68040 cycles only allow a port width of 32 bits.
If an access error occurs (TEA sensed from the CPU)' exception handling starts because the current
cycle has been aborted (illegal transfer or wrong data).
During local bus operation, an access error will be generated if a device does not respond correctly.
VMEbus transfers may also be aborted via a TEA (VMEbus : BERR *).
The TA and TEA signal asserted simultaneously initiate a retry cycle.

2.2 The Instruction Set
For the 68040 instruction set and further information relative to programming, please refer to the
68040 User's Manual.

2-1

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

2.3 Vector Table of the 68040
The following table lists all vectors defined and used by the 68040 CPU.

Table 2-1: Exception Vector Assignments
Assignment

Vector

Vector Offset

Number(s)

(Hex)

0
1
2
3

000
004
008
OOC

Reset Initial Interrupt Stack Pointer
Reset Initial Program Counter
Access Fault (Bus Error)
Address Error

4
5
6
7

010
014
018
01C

Illegal Instruction
Integer Divide by Zero
CHK, CHK2 Instruction
FTRAPcc, TRAPcc, TRAPV Instructions

8
9
10
11

020
024
028
02C

Privilege Violation
Trace
Line 1010 Emulator (Unimplemented A-Line Opcode)
Line 1111 Emulator (Unimplemented F-Line Opcode)

12
13
14
15

030
034
038
03C

(Unassigned, Reserved)
Defined for MC68020/MC68030, not for MC68040
Format Error
Uninitialized Interrupt

16-23

040-05C

24
25
26
27

060
064
068
06C

Spurious Interrupt
Level 1 Interrupt Autovector
Level 2 Interrupt Autovector
Level 3 Interrupt Autovector

28
29
30
31

070
074
078
07C

Level
Level
Level
Level

32-47

OaO-OBC

48
49
50
51

OCO
OC4
OC8
OCC

FP
FP
FP
FP

Branch or Set on Unordered Condition
Inexact Result
Divide by Zero
Underflow

52
53
54
55

000
004
008
ODC

FP
FP
FP
FP

Operand Error
Overflow
Signaling NAN
Unimplemented Data Type

56
57
58

OEO
OE4
OE8

Defined for MC68030 and MC68851, not for MC68040
Defined for MC68851, not for MC68040
Defined for MC68851, not for MC68040

59-63

OEC-OFC

(Unassigned, Reserved)

64-255

100-3FC

User Defined Vectors (192)

(Unassigned, Reserved)

4
5
6
7

Interrupt
Interrupt
Interrupt
Interrupt

Autovector
Autovector
Autovector
Autovector

TRAP #0-15 Instruction Vectors

HARDWARE USER'S MANUAL

SECTION 3

For test purposes the clock signal for the microprocessor is connected via jumper 817 to the
devices. When using the CPU board, this jumper must be inserted according to the following figure.

CAUTION
If jumper 817 is removed, damage may be caused to the devices on the CPU board.

Figure 2-1: Jumper Setting for B 17

B17
2

1

2-3

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

Figure 2-2: Location Diagram of Jumperfields 817

o ir'V 0Gt() r - - - - - - - ,

[) ~
[)
n

~
~

KF

2-4

HARDWARE USER'S MANUAL

SECTION 3

3. THE LOCAL BUS
3.1 The FGA-002 Gate Array
The FGA-002 Gate Array featured on this CPU board has 24,000 gates and 281 pins.
The FGA-002 Gate Array controls the local bus and builds the interface to the VMEbus. It also
includes a DMA contro"er, complete interrupt management, a message broadcast interface (FMB),
timer functions, and mailbox locations.
This gate array monitors the local bus. This in turn signifies that if any local device is to be
accessed, the gate array takes charge of a" control signals in addition to used address and data
signals.
The FGA-002 Gate Array serves as a manager for the VMEbus. A" VMEbus address and data lines
are connected to the gate array through the buffers. Additional functions such as the VMEbus
interrupt handler are also installed on the FGA-002 Gate Array. The SGL VMEbus arbiter in the
FGA/002 must remain disabled because the 4 level VME arbiter of the CPU board is designed in a
separate device and connected with the VME bus (please refer to chapter 6.4 VMEbus Arbitration
in this section).
The start address of the FGA-002 Gate Array registers is $FFDOOOOO. A" registers of the gate array
and associated functions are described in detail in the FGA-002 Gate Array Users Manual.

3-1

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

3.2 The Shared RAM
On this CPU board the shared RAM is placed on a module to allow the adaption of DRAM or SRAM
to the base board.
All signals which are needed to control the shared RAM are available on the RAM module connector.
Therefore RAM devices with different access times can also be used on this CPU board to take
advantage of the 68040 with higher frequency if it becomes available.

3.2.1 General Operation
The Shared RAM is accessible from the 68040 and from the VMEbus. The access address for the
68040 starts at $00000000. The access address for the VMEbus is software programmable in
4 Kbyte steps. The defined memory range can be write protected in coordination with the address
modifier codes. For example, in supervisor mode the memory can be read and written, in user mode
memory can only be read.
If an access from the VMEbus takes place the onboard logic requests the local bus mastership from
the local arbiter via the FGA-002 Gate Array. After the arbiter has granted local bus mastership to
the FGA-002 Gate Array, the access cycle is executed. A read cycle is terminated by latching all
data from the memory; a write cycle is ended by storing the data in the memory cells. Both read
and write cycles are terminated on the local bus side and the FGA-002 Gate Array immediately
releases bus mastership to the CPU while completing the fully asynchnronous VMEbus access cycle.

3.2.2 Shared RAM Information
The RAM module connector holds several signals which are software readable and inform the user
concerning RAM type and functionality.
These pins are readable via the PlfT2 device which is installed on the CPU board. For base address
and register address information please refer to the chapter "Address Map of the PI/T2 Registers".

3-2

HARDWARE USER'S MANUAL

SECTION 3

The following table shows the information which can be read and the corresponding PlfT bit. The
RAM modules which are accessible are described in the following chapters which also contain the
"RAM Type Information" description.

RAM Type Information on PI/T2
PI/T Bit

Name

Value

Description

PBO
PB1
PB2

MCDO
MCD1
MCD2

*
*
*

Describes the memory size of the module.
Please refer to the following chapters.

PC2

RAMTYP

0

SRAM
DRAM

1
PC4

BURST

0

Not available
Available

1
PCG

PARITY

0

Not available
Available

1

3-3

SVS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

3.2.3 The DRM-01/4
The following CPU boards are assembled with the DRM-01/4.
CPU Board

RAM Module

CPU-40B/4/xx

DRM-01/4

"xx" contains the EAGLE module number and is independent for the RAM module.

The DRM-01/4 is a 4 Mbyte RAM module using Dynamic Random Access Memory devices. The
RAM module has the following features.

Features of the DRM-01/4
•

4 Mbyte DRAM

•

Burst READ and Burst WRITE capability

•

Parity Generation and Checking

•

Asynchronous refresh is provided every 14Jls

•

Accessible via VMEbus

The access address for the 68040 is $00000000 to $003FFFFF.
The access address for the VMEbus is programmable in 4 Kbyte steps through the FGA-002. The
defined memory range can be write protected in coordination with the address modifier codes. For
example, in supervisor mode the memory can be read and written, in user mode memory can only
be read.
The DRAM module includes byte parity check for local and VMEbus accesses. If a parity error is
detected on a VMEbus cycle, a BERR is forced to the VMEbus informing the requestor that a parity
error has occurred. On local accesses, a Transfer Error Acknowledge (TEA) is forced to the
processor if a parity error was detected. The following chart lists the required CPU clock cycles and
wait states for accessing the shared RAM.
Board
Type

68040 Clock
Frequency

No. of CPU Clock
Cycles Counted
From TS to TA
for Normal Cycles

No. of CPU Clock
Cycles for
Burst Cycles

No. of Wait
States for
Normal Cycles

No. of Wait
States for
Burst Cycles

CPU-40/B

25 MHz

4

1

3

0

SECTION 3

HARDWARE USER'S MANUAL

3.2.4 RAM Type Information for the DRM-01/4
The following information can be read from the PIJT2.
RAM Type Information
PI/T Bit

Name

Value

PBO
PB1
PB2

MCD4
MCD1
MCD2

1
1

0

PC2

RAMTYP

1

PC4

BURST

1

PC6

PARITY

1

3.2.5 Summary of the DRM-01/4
Capacity

4 Mbytes

Address Range

$00000000 to $003FFFFF

Port Data Width

32 bits

Local Data Width

32 bits

Burst Mode

Supported

Parity Mode

Supported

Device

1 M x 1 Nibble Mode

Supported Transfers

Byte, Word, Long word, Cache Line (16 bytes)

3-5

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

3.2.6 The DRM-01/16
The following CPU boards are assembled with the DRM-O 1/16.
CPU Board

RAM Module

CPU-40B/16/xx

DRM-01/16

"xx" contains the EAGLE module number and is independent for the RAM module.
The DRM-01 /16 is a 16 Mbyte RAM module which is used on the CPU-40B/16.

Features of the DRM-O 1/16
•

16 Mbyte DRAM

•

Burst READ and Burst WRITE capability

•

Parity Generation and Checking

•

Asynchronous refresh is provided every 14ps

•

Accessible via VMEbus

The access address for the 68040 is $00000000 to $OOFFFFFF.
The access address for the VMEbus is programmable in 4 Kbyte steps through the FGA-002. The
defined memory range can be write protected in coordination with the address modifier codes.
For example, in supervisor mode the memory can be read and written, in user mode memory can
only be read.
The DRAM module includes byte parity check for local and VMEbus accesses. If a parity error is
detected on a VMEbus cycle, a BERR is forced to the VMEbus informing the requestor that a parity
error has occurred. On local accesses, a Transfer Error Acknowledge (TEA) is forced to the
processor if a parity error was detected. The following chart lists the required CPU clock cycles and
wait states for accessing the shared RAM.
Board
Type

68040 Clock
Frequency

No. of CPU Clock
Cycles Counted
From TS to TA
for Normal Cycles

No. of CPU Clock
Cycles for
Burst Cycles

No. of Wait
States for
Normal Cycles

No. of Wait
States for
Burst Cycles

CPU-40/8

25 MHz

4

1

3

0

3-6

HARDWARE USER'S MANUAL

SECTION 3

3.2.7 RAM Type Information for the DRM-01/16
The following information can be read from the PIIT2.
RAM Type Information
PIIT Bit

Name

Value

PBO
PB1
PB2

MCD4
MCD1
MCD2

0
0

PC2

RAMTYP

1

PC4

BURST

1

PC6

PARITY

1

3.2.8 Summary of the DRM-01/16
Capacity

16 Mbytes

Address Range

$00000000 to $OOFFFFFF

Port Data Width

32 bits

Local Data Width

32 bits

Burst Mode

Supported

Parity Mode

Supported

Device

4M x 1 Nibble Mode

Supported Transfers

Byte, Word, Long word, Cache Line (16 bytes)

3-7

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

3.2.9 The SRM-01/4
The following CPU boards are assembled with the SRM-01 /4.
CPU Board

RAM Module

CPU-41 B/4/xx

SRM-01/4

"xx" contains the EAGLE module number and is independent for the RAM module.
II

I'

The SRM-O 1/4 is a 4 Mbyte RAM module using Static Memory devices. The RAM module has the
following features.

Features of the SRM-01/4
•

4 Mbyte SRAM

•

Burst READ and Burst WRITE capability

•

Battery Backup via VMEbus

•

Accessible via VMEbus

The access address for the 68040 is $00000000 to $003FFFFF.
The access address for the VMEbus is programmable in 4 Kbyte steps through the FGA-002. The
defined memory range can be write protected in coordination with the address modifier codes. For
example, in supervisor mode the memory can be read and written, in user mode memory can only
be read.
Parity check is not necessary for SRAM devices, because these components are protected against
soft errors owing alpha emission. The following chart lists the required CPU clock cycles and wait
states for accessing the shared RAM.
Board
Type

68040 Clock
Frequency

No. of CPU Clock
Cycles Counted
From TS to TA
for Normal Cycles

No. of CPU Clock
Cycles for
Burst Cycles

No. of Wait
States for
Normal Cycles

No. of Wait
States for
Burst Cycles

CPU-41!B

25 MHz

3

1

2

0

3-8

HARDWARE USER'S MANUAL

SECTION 3

3.2.10 RAM Type Information for the SRM-01/4
The following information can be read from the Plrr2.
RAM Type Information
PI/T Bit

Name

Value

PBO
PB1
PB2

MCD4
MCD1
MCD2

1
1
0

PC2

RAMTYP

0

PC4

BURST

1

PC6

PARITY

0

3.2.11 Summary of the SRM-01/4
Capacity

4 Mbytes

Address Range

$00000000 to $003FFFFF

Port Data Width

32 bits

Local Data Width

128 bits

Burst Mode

Supported

Parity Mode

Not necessary

Device

128K x 8 Static RAM

Supported Transfers

Byte, Word, Long word, Cache Line (1 6 bytes)

3-9

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

3.2.12 The SRM-01/8
The following CPU boards are assembled with the SRM-01 /8.
CPU Board

RAM Module

CPU-41 B/8/xx

SRM-01/8

"xx" contains the EAGLE module number and is independent for the RAM module.
The SRM-O 1/8 is an 8 Mbyte RAM module which is used on the CPU-41 B/8.

Features of the SRM-O 1/8
•

8 Mbyte SRAM

•

Burst READ and Burst WRITE capability

•

Battery Backup via VMEbus

•

Accessible via VMEbus

The access address for the 68040 is $00000000 to $007FFFFF.
The access address for the VMEbus is programmable in 4 Kbyte steps through the FGA-002. The
defined memory range can be write protected in coordination with the address modifier codes.
For example, in supervisor mode the memory can be read and written, in user mode memory can
only be read.
Parity check is not necessary for SRAM devices, because these components are protected against
soft errors owing alpha emission. The following chart lists the required CPU clock cycles and wait
states for accessing the shared RAM.
Board
Type

68040 Clock
Frequency

No. of CPU Clock
Cycles Counted
From TS to TA
for Normal Cycles

No. of CPU Clock
Cycles for
Burst Cycles

No. of Wait
States for
Normal Cycles

No. of Wait
States for
Burst Cycles

CPU-41/B

25 MHz

3

1

2

0

3-iO

HARDWARE USER'S MANUAL

SECTION 3

3.2.13 RAM Type Information for the SRM-O 1/8
The following information can be read from the PI/T2.
RAM Type Information
PI/T Bit

Name

Value

PBO
PB1
PB2

MCD4
MCD1
MCD2

0
1
0

PC2

RAMTYP

0

PC4

BURST

1

PC6

PARITY

0

3.2.14 Summary of the SRM-01/8
Capacity

8 Mbytes

Address Range

$00000000 to $007FFFFF

Port Data Width

32 bits

Local Data Width

128 bits

Burst Mode

Supported

Parity Mode

Not necessary

Device

128K x 8 Static RAM

Supported Transfers

Byte, Word, Long word, Cache Line (16 bytes)

3-11

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

3.3 The System EPROM Area
The first two read cycles after RESET of the microprocessor are fetches of the Initial Interrupt Stack
Pointer and the Initial Program Counter. These cycles are executed under addresses $0 and $4
respectively. A special control logic maps the System EPROM Area down to this address to start
the CPU from the installed EPROMs. As a result of this downmapping, the first two long words in
the EPROM must contain the following data:
$0 in EPROM Initial Interrupt Stack Pointer
$4 in EPROM Initial Program Counter
The data path of the System EPROivi Area is 32 bits wide. The system EPROM consists of two i 6
bit wide EPROM devices.

3.3.1 Memory Organization of the System EPROM Area
The memory organization of the System EPROM and the location number of the sockets are outHned
in the following figure. The one after that shows the location diagram of the sockets.

Figure 3-1: Memory Organization of the System EPROM Area
Long Word Address 031

08 07
1

0241023

DO

Byte 0

Byte 1

Byte 2

Byte 3

$FFOO 0000

$FFOO 0001

$FFOO 0002

$FFOO 0003

Byte 4

Byte 5

Byte 6

Byte 7

$FFOO 0004

$FFOO 0005

$FFOO 0006

$FFOO 0007

UU
J30

UM
J30

LM
J29

LL
J29

$FFOO 0000

$FFOO 0004

UU = Upper Upper Byte in J30 ')
UM = Upper Middle Byte in J30~
LM = Lower Middle Byte in J2~;
LL = Lower Lower Byte in J29,;

-~='~-'.' . .~~--------~~-----------------------

3-12

SECTION 3

HARDWARE USER'S MANUAL

Figure 3-2: Location Diagram of the System EPROM Area

3-13

FORCE COMPUTERS

SVS68K/CPU-40/41 USER'S MANUAL

The following read only cycles can be forced to the System EPROM Area:
Byte: 8 Bits

I

Word: 16 Bits

I

Long Word: 32 Bits

The processor supports long word read instructions odd addresses, resulting in byte and word
accesses which meet the 68040 boundary requirements. If a user program must be burned into
EPROMs for CPU board usage, the data bytes must be burned into the different chips as shown
below.

II -.-- ..... -----_.. _......

.. ..

__ .

..;

II

.........

UU, UM:
J30 (UPPER)

XXXO
XXX4
XXX8
XXXC

XXX1
XXX5
XXX9
XXXD

LM, LL:
J29 (LOWER)

XXX2
XXX6
XXXA
XXXE

XXX3
XXX7
XXXB
XXXF

CAUTION
1)

The bus size of the System EPROM Area cannot be changed.
always be used for proper operation.

2)

Microprocessor interactive fetches can only be on addresses ($0,2,4,6, 8 .. ). An
Address Trap Error occurs if a program is started/executed on odd addresses
($1,3,5,7 ... ).

3)

Data can be read from any address; odd, even or unaligned in byte, word, or long word
format.

4)

Write cycles to the EPROM Area are forbidden.

5)

All chips must be the same device type and access time for usage in System EPROM
Area.

3-14

Two EPROMs must

HARDWARE USER'S MANUAL

SECTION 3

Example for Data Transfers:
The following instruction is fully supported from the System EPROM Area:
MOVE.X ($FFOO OOOY), DO
X =
X =
X =

B = Byte
W = Word
L = Long Word

Y
Y
Y
Y

0

=
=
=
=

1 Byte
2 Bytes
4 Bytes

1
2

3

All combinations of the listed instructions are allowed and possible.

3.3.2 Usable Device Types for the EPROM Area
The following device types or equivalent are supported by the System EPROM Area:

Device
27210
272048
UNDEFINED
UNDEFINED

Device Capacity
64K x
128K x
256K x
512K x

16
16
16
16

Total Capacity
256 Kbytes
512 Kbytes
1 Mbyte
2 Mbytes

Default Configuration
X

The default configuration, using 27210 devices, is provided for the installation of VMEPROM. The
following figure outlines the different jumper settings for the listed device types and the one to
follow shows the location diagram of Jumperfield B11 for device dependent configuration. The
Appendix of this Hardware User's Manual lists a table of the usable pinouts for the System EPROM
Area if other devices than those listed must be used.

3-15

SVS68K/CPU-40/41 USER'S MANUAL

Figure 3-3:

FORCE COMPUTERS

Configuration Jumper
Jumperfield B11
Jumpersetting:

Settings

of

System

Device:

Organization:

27C210

64K x 16

811

1rl
I

o.:.:.:.

0

o

0

0

0

I

811

go
0
0

1mtt?j~

0

27C2048

128Kx 16
(DEFAUL.:T)

0

B11
1

9-0
0-0
0

UNDEFINED

256K x 16

UNDEFINED

512K x 16

0

811
1

a-o
.:.:.:.

0-0
0-0

3-16

EPROM

Area

SECTION 3

HARDWARE USER'S MANUAL

Location Diagram of Jumperfield B 11 Configuration of the System
EPROM Area

Figure 3-4:

Gt()
o jrv 0
r-------,

[)

~

D

D

1

3-17

FORCE COMPUTERS

SVS68K/CPU-40/41 USER'S MANUAL

3.3.3 Access Time Selection of the System EPROM Area
The access time of the System EPROM Area is software programmable in the FGA-002 Gate Array.
It can be adapted to various access speeds of the EPROM devices. A complete description of the
FGA-002 Gate Array can be found in the related manual.

3.3.4 Address Map of the System EPROM Area
The start address of the System EPROM Area is mapped via the FGA-002 Gate Array and cannot
be changed. The size of this memory area depends on the memory capacity of the used devices.
The following table lists the address map of the EPROM area.

Table 3-1: Address Map of the EPROM Area
Start Address
FFOO
FFOO
FFOO
FFOO

End Address

0000
0000
0000
0000

FF03
FF07
FFOF
FF1 F

FFFF
FFFF
FFFF
FFFF

Used Device

Total Capacity

27210
272048
UNDEFINED
UNDEFINED

256 KBYTES
512 KBYTES
1 MBYTE
2 MBYTES

3.3.5 Summary of the EPROM Area
Not Allowed Access with Function Code

111

Usable Data Bits

DOO - D31

Supported Port Size

Long Word

No. of Devices to be Installed

2

Upper Upper Byte
Upper Middle Byte
Lower Middle Byte
Lower Lower Byte

J30
J30
J29
J29

Maximum Capacity

2 Mbytes

Default Configuration for

128K * 16 Devices

Default Access Time

200ns

Access Address Range

$FFOO 0000 START
$FF03 FFFF END

3-18

Default
Configuration
X

HARDWARE USER'S MANUAL

SECTION 3

3.4 The FLXibus
The CPU board can be used with or without an I/O subsystem, called an "EAGLE" Module.
The EAGLE module increases the functionality of the board and adds extra I/O features to fit the
application requirement. EAGLE modules connect directly to the FLXi (FORCE Local eXpansion
interface) of the base board.
If your CPU board is assembled with an EAGLE module please refer to the "EAGLE Module" manual
which is shipped with this board and should be placed in Section 6 of this manual.

3.4.1 Introduction to the FLXibus
The FLXi (FORCE Local eXpansion interface) is a 32 bit interface with non-multiplexed data and
address lines.
An EAGLE module holds a FLXibus interface and an I/O interface (64 pins), which is directly
connected to row a and row c of the VMEbus P2 connector.
The aim of the
the complete
implemented.
for the design

EAGLE module concept is to be more flexible in the liD part of the board. This avoids
redesign of a board if new I/O devices or customer specific solutions must be
When having several modules available we can take advantage of a basis contingent
of new boards.

The EAGLE module has the ability to become master of the FLXi and therefore the devices on the
EAGLE module are able to transfer data to the "main memory" on the base board if they have DMA
capability.

Features of the FLXibus
•

One or more identical or different EAGLE modules can be used on abase board. This CPU
board is capable of holding one EAGLE module.

•

The EAGLE modules contain all necessary software which is stored in the on-board EPROMs.

•

The EAGLE module can become bus master (e.g. for DMA transfers) on the base board.

•

Interrupts to the base boards are supported.

•

FLXibus definition is based on the 68020 asynchronous interface and supports frequencies
up to 50 MHz.

3-19

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

3.5 The Local FLASH EPROM
The CPU board holds a 1 28K x 8 FLASH EPROM which allows data storage without the need of a
battery or supply via the + 5VSTDBY VMEbus line.

3.5.1 Memory Organization of the FLASH EPROM
The FLASH EPROM is connected with the data lines D24 to D31. This device features a byte port.
The cycle control.chip (CCC) between the 68040 processor and the FGA-002 simulates the dynamic
bus sizing, so that succeeding bytes seen by the microprocessor are handled in the same manner
as succeeding bytes for the FLASH EPROM. Byte, word, and long word accesses are managed by
the dynamic bus sizing of the microprocessor. For further details, please refer to the CCC
description.
Data can be read from any address; odd, even or unaligned in byte, word, or long word format, and
written to any address in byte format.
Example for Data Transfers:
The following instruction is fully supported from the FLASH EPROM Area:

MOVE. X

($FFC8 OOOY), DO

Byte
= WB = Word
= =
= L = Long
Y =0
Y =1
Y =2
Y =3

X
X
X

1 Byte
2 Bytes

Word

4

Bytes

HARDWARE USER'S MANUAL

SECTION 3

3.5.2 Programming the FLASH EPROM
The software and hardware to erase and program the FLASH EPROM is installed on the CPU board.
For detailed information on how to program the FLASH EPROM, please refer to the CPU-40
VMEPROM description which is located in Section 7 and Section 8 of this manual.
Before programming the FLASH EPROM the write protection jumper on jumperfield B16 must be set
from 1-2 to 2-3. The following page shows the location of jumperfield B 1 6.

3.5.3 Address Map of the FLASH EPROM
The address range of the FLASH EPROM Area is mapped via the FGA-002 and a PAL and is
uncha ngea ble.

3.5.4 Summary of the Local FLASH Memory
Not Allowed Access with Function Code

1 1 1

Supported Port Size

Byte

Capacity

128 Kbytes

Chip Organization

128K x 8

Access Time

200ns

Access Address

$ FFC80000 to FFC9 FFFF

3.5.5 Jumper Settings for 816

=

write disabled
write Protection
(Default)

1

write enabled

1

o

I

o

o

3-21

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

3.5.6 Location Diagram of Jumperfield B 16

II

3-22

~

HARDWARE USER'S MANUAL

SECTION 3

3.6 The Local SRAM
The SRAM allows the user to retain data even when the power supply is switched off. A battery
provides the voltage for the SRAM standby mode. With Jumper B20, it is possible to select either
the on board battery or the + 5VSTDBY of the VMEbus for backup supply.

3.6.1 Memory Organization of the User SRAM
This device features a byte port. External hardware simulates the dynamic bus sizing, so that
succeeding bytes seen by the microprocessor are handled in the same manner as succeeding bytes
for the Local SRAM. Byte, word, and long word accesses are managed by the dynamic bus sizing
of the external hardware.
Data can be read from and written to any address; odd, even or unaligned in byte, word, or long
word format.
Example for Data Transfers:
The following instruction is fully supported from the SRAM Area:

MOVE. X

($FFCO OOOY), DO

X
X
X

= B = Byte
= W = Word
= L = Long Word

Y
Y
Y
Y

=
=
=
=

1
2
4

Byte
Bytes
Bytes

0
1
2
3

3-23

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

All combinations of the listed instructions are allowed and possible.
This SRAM can be used to save special settings of the FGA-002 as described in Section 7,
"Introduction to VMEPROM" of this manual.
The following figure shows the location diagram of Jumperfield 820 for the backup supply. The
default configuration uses the on board battery.
Please note that the Real Time Clock on the CPU board is supplied via the same jumperfield.

~

Bl
1

rn
rn
:\:::
I
0

Battery is connected to
Backup Supply Line
(default)

1

:y::
I
0

~
:;::::::

Battery is cut from
Backup Supply Line

0

B20

B20

1

.

ElI..L

+5VSTDBY is connected to
Backup Supply L'ine

1

~
9

o·

+5VSTDBY is cut from
Backup Supply Line
(default)

NOTE
The battery is not installed on the CPU board to avoid damage during shipment.

CAUTION
If the special settings for the FGA-002 which are stored in the SRAM are used, these settings
will be erased when
a)

removing the jumper on jumperfield 81 or disassembling the battery

b)

removing the jumper on jumperfield 820 or removing the board from the
VMEbus.

and

SECTION 3

HARDWARE USER'S MANUAL

Figure 3-5: Location Diagram of the Backup Supply Jumperfield B 1 and B20

, 0
[JD~

~
~rJOOil
,r

./

0
o ~D

~

~P9C

3-25

II

=tzJ

~

l'!...DL.I

!1L--r

__ D~

'---

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

3.6.2 The Address Map of the SRAM Area
The address range of the SRAM Area is mapped via the FGA-002 and a PAL and is unchangeable.
The SRAM is used by the boot software and therefore not fully available to the user. Please refer
to the FGA-002 User's Manual, Section 10, Boot Software.

3.6.3 Summary of the SRAM Area
Not Allowed Access with Function Code

111

Supported Port Size

Byte

Capacity

128 Kbytes

Chip Organization

128 K * 8 Devices

Access Time

100ns

Access Address

$FFCO 0000 - $FFC 1 FFFF

3-26

HARDWARE USER'S MANUAL

SECTION 3

3.7 The Boot EPROM
The CPU board contains one 28-pin EPROM which is used to boot up the processor and run a
program to initialize register contents of the FGA-002 Gate Array. This program finishes in such a
manner that the System EPROM appears to have booted the CPU Board. The device type of the
Boot EPROM is 27512 with the total memory capacity of 64 Kbytes. The location is J15.
For more detailed information over the Boot EPROM, please refer to Section 10, "Boot Software
Description" of the FGA-002 Users Manual.
The figure on the page to follow displays the location of the Boot EPROM on the CPU board.

3.7.1 Summary of the Boot EPROM Area
Access Not Allowed with Function Code

111

Supported Port Size

Byte

No. of Devices to be installed

1

Maximum Capacity

64 Kbytes

Default Access Time

200ns

Access Address

$FFEO 0000 - $FFEO FFFF

3-27

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

Figure 3-6: Location Diagram of the Boot EPROM

uo

o

D

D

D

u

--==

"----~~ 0 [j ----.. .~

OUt]

",----J42

m

-

J4J

3-28

,-

HARDWARE USER'S MANUAL

SECTION 3

3.8 The DUSCC 68562
The Dual Universal Serial Communications Controller 68562 (DUSCC) is a single-chip MaS-LSI
communications device that provides two independent, multiprotocol, full duplex receiver!
transmitter channels in a single package. Each channel consists of a receiver, a transmitter, a 1 6
bit multifunction counter/timer, a digital phaselocked loop (DPLL), a parity/CRe generator and
checker, and associated control circuits.

Features of the DUSCC
•

Dual full-duplex synchronous/asynchronous receiver and transmitter

•

Multiprotocol operation consisting of:
BOP:
COP:
ASYNC:

HDLC/ADCCP, SDLC, SDLC Loop, X.25 or X.75 link level
BISYNC, DDCMP, X.21
5-8 bit plus optional parity

•

Programmable data encoding formats: NRZ, NRZI, FMO, FM1, Manchester

•

4 character receiver and transmitter FIFOs

•

Individual programmable baud rate for each receiver and transmitter

•

Digital phase locked loop

•

User programmable counter!timer

•

Programmable channel modes full/half duplex, auto echo, local loopback

•

Modem control signals for each channel: RTS, CTS, DCD

•

CTS and DCD programmable auto enables for Receiver (RX) and Transmitter (TX)

•

Programmable interrupt on change of CTS or DCD

3-29

SVS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

3.8.1 Address Map of the DUsCC1 Registers
The following tables contain the complete register map of the DUSCC 1 .

Table 3-2: Serial 1/0 Port #1 (DUsCC1) Register Address Map

Port Base Address: $FF802000
Address
HEX

Offset
HEX

Reset
Value

$FF802000
$FF802001
$FF802002
$FF802003
$FF802004
$FF802005
$FF802006
$FF802007
$FF802008
$FF802009
$FF80200A
$FF80200B
$FF80200C
$FF80200D
$FF80200E
$FF80200F
$FF802010
$FF802011
$FF802012
$FF802013
$FF802014
$FF802015
$FF802016
$FF802017
$FF802018
$FF802019
$FF80201A
$FF80201 C

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1C

00
00

Mode

Label

--

RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
R
R
RIW
RIW

DUSCMR1
DUSCMR2
DUSSS1R
DUSS2R
DUSTPR
DUSTTR
DUSRPR
DUSRTR
DUSCTPRH
DUSCTPRL
DUSCTCR
DUSOMR
DUSCTH
DUSCTL
DUSPCR
DUSCCR

Channel Mode Reg 1
Channel Mode Reg 2
SYN 1/Secondary Adr Reg 1
SYN2/Secondary Adr Reg 2
Transmitter Parameter Reg
Transmitter Timing Reg
Receiver Parameter Reg
Receiver Timing Reg
Counter/Timer Preset Reg H
Counter/Timer Preset Reg L
Counter/Timer Control Reg
Output and Miscellaneous Reg
Counter/Timer High
Counter/Timer Low
Pin Configuration Reg
Channel Command Reg

--

W

DUSTFIFO

Transmitter FIFO

--

R

DUSRFIFO

Receiver FIFO

00
00

RIW
RIW
RIW
RIW

DUSRSR
DUSTRSR
DUSICTSR
DUSIER

Receiver Status Reg
Transmitter/Receiver Stat Reg
Input + Counter/Timer Stat Reg
Interrupt Enable Reg

--00

--

00

----00

--00

-00

Description

3-30

HARDWARE USER'S MANUAL

SECTION 3

Table 3-3: Serial 1/0 Port #2 (DUSCC1) Register Address Map

Port Base Address: $FF802000
Address

Offset

HEX

HEX

$FF802020
$FF802021
$FF802022
$FF802023
$FF802024
$FF802025
$FF802026
$FF802027
$FF802028
$FF802029
$FF80202A
$FF80202B
$FF80202C
$FF80202D
$FF80202E
$FF80202F
$FF802030
$FF802031
$FF802032
$FF802033
$FF802034
$FF802035
$FF802036
$FF802037
$FF802038
$FF802039
$FF80203A
$FF80203C

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10,
11 I
12 I
13-1
14,
15 I
16 I
17-1
18
19
1A
1C

Reset
Value

Description

Mode

Label

--

RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
R
R
RIW
RIW

DUSCMR1
DUSCMR2
DUSSS1R
DUSS2R
DUSTPR
DUSTTR
DUSRPR
DUSRTR
DUSCTPRH
DUSCTPRL
DUSCTCR
DUSOMR
DUSCTH
DUSCTL
DUSPCR
DUSCCR

--

W

DUSTFIFO

Transmitter FIFO

--

R

DUSRFIFO

Receiver FIFO

00
00

RIW
RIW
RIW
RIW

DUSRSR
DUSTRSR
DUSICTSR
DUSIER

Receiver Status Reg
Transmitter/Receiver Stat Reg
Input + Counter/Timer Stat Reg
Interrupt Enable Reg

00
00

--00

-00

----00

--

-00

-00

Channel Mode Reg 1
Channel Mode Reg 2
SYN 1/Secondary Adr Reg 1
SYN2/Secondary Adr Reg 2
Transmitter Parameter Reg
Transmitter Timing Reg
Receiver Parameter Reg
Receiver Timing Reg
Counter/Timer Preset Reg H
Counter/Timer Preset Reg L
Counter/Timer Control Reg
Output and Miscellaneous Reg
Counter/Timer High
Counter/Timer Low
Pin Configuration Reg
Channel Command Reg

Table 3-4: Ports #1 and #2 (DUSCC1) Common Register Address Map

Port Base Address: $ FF802000
Address

Offset

HEX

HEX

Reset
Value

Mode

Label

$FF80201B
$FF80201E
$FF80201 F
$FF80203E

1B
1E
1F
3E

00
OF
00
OF

RIW
RIW
RIW
R

DUSGSR
DUSIVR
DUSICR
DUSIVRM

Description

3-31

General Status Register
Interrupt Vec Reg Unmodified
Interrupt Control Register
Interrupt Vec Reg Modified

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

3.8.2 RS232 Hardware Configuration of Port #1 and #2
Ports #1 and #2 are built around the DUSCC (J19). The DUSCC is connected to the local 8 bit data
bus.
The RS232 interfaces of port #1 and #2 are identical except that port #1 is additionally wired to a
resistor field which allows connection to the VMEbus P2 connector. The
resistors are not
installed in the default configuration because it may conflict with the EAGLE module. All RS232
driver and receivers are installed in the default configuration. The I/O signals of port # 1 are
connected to the VME connector P2 as follows:

on

on

-

Signal

Input

DCD
RXD
TXD
DTR
DSR
RTS
CTS
GND

X
X

X

. . _-

--

...

----_ ..

Output

VME Connector P2

X
X
X
X

c29
c30
c31
c32
a29
a30
a31
a32

X

Description
Data Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
Data Set Ready
Request to Send
Clear to Send
Signal GND

The individual lID signal assignment of ports #1 and #2 are listed as follows:

Signal

Input

DCD
RXD
TXD
DTR
GND
DSR
RTS
CTS
GND

X
X

Output

X
X
X
X

X
X

9 Pin D-Sub Connector

Description

1
2
3

Data Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
Signal GND
Data Set Ready
Request to Send
Clear to Send
Signal GND

4
5
6

7
8
9

3-32

HARDWARE USER'S MANUAL

SECTION 3

The following figure shows the location diagram of the on resistor fields R563 to R569 and the
figure afterwards displays the connection between the DUSCC and the VMEbus Connector P2, and
the Micro D-Sub connector.

CAUTION
Before installing the on resistors to generate the port #1 availability on the VMEbus P2
Connector, please make sure that the EAGLE module which is being used does not occupy the
VMEbus P2 signals c29 to c32 and a29 to a32. Otherwise the board will be damaged.

3-33

SYS68K/CPU-40/41 USER'S MANUAL

Figure 3-7: Location Diagram of the

FORCE COMPUTERS

on Resistors R563 to R569

O ... D~
o

3-34

HARDWARE USER'S MANUAL

SECTION 3

Figure 3-8: RS232 Connection Between DUSCC1 and VMEbus Connector P2

DUSCC
68562

FH002
VME P2

CHANNEL
12

B

A

Ba

Pin No. Pin No.

36

13

~TX_D______________~_1~9 ~---+-.
W6

41

08

I-so_u-+-+-

33

16

I-0U_2-+-+-

34

15

I-0U_1-+-+-

39

10

I-RT_C-+-+-

40

09

f-TR_C-*+--I-

W3

wa

'1(1

'1(2

'1(5

32

17

f-CT_S- . f -

44

05

f-IN_1_ _ _ _ _ _ _ _ _ _~

38

11 ~DC-D------------~

37

12

Figure 3-9:

~~-D--------------~-0-7~

r ___
051-_ _ _ _ _ _ _'I(_4_ _ _ _ _ _ _ _ _ _~

RS232 Connection Between DUSCC1 and Micro D-Sub Connector

DUSCC

FH002

68562

6

D~

7

Rrs

CHANNEL

A

B

Pin No.

Pin No.

36

13

41

08

TXD

~-

~

19

~CTS

'10'6

18

16

f\
9'-"'GNO

SOU

2

15

02

01

'10'3

3

14

14

13

'liB

33

16

OU2

1S

OU1

4

13

34

16

15

39

10

RTC

5

12

06

04

40

09

TRC

6

~

17

09

10

10

DB

1

RXD

2

TXO

3

'10'7

12

Ba

ceo

0-

orR

4

GNO~

1QBb
'10'1

32

17

CTS

44

05

I N1

38

11

DCD

37

12

RXD

-B
a

!

20

30

'1(2

'10'5

I

9

07

05

"'-f

I
I

3-35

'10'4

I

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

The devices are labeled as shown in the following chart.

Port#

Channel

Ba

Bb

Pa

Connector

1
2

a
b

83
84

85
86

P01
P02

1NME P2
2

The next figure shows the pinout of the Micro O-Sub connector for RS232. The figure on the next
page displays the location of the RS232 configuration jumperfields. The default setting of the
RS232 configuration jumperfield is shown in the next table,

Figure 3-10: Pinout of the Micro O-Sub and O-Sub Connector for RS232
A) Micro DSUB Male Connector Soldered

B) Micro DSUB and DSUB Female Connectors
on the Adapter/Terminal Cable

on the CPU Board

RS232

RS232

Pa

Pa
GND

DeD
GNO

DSR

02
RTS

70
03

eTS

RXO

80

RTS

70

TXD

80

04

eTS

04

OTR

03

TXO

02 RXO

DTR
OSR

GNO

DeD

GNO

3-36

SECTION 3

HARDWARE USER'S MANUAL

Figure 3-11 :

Location Diagram of RS232 Configuration Jumperfields B3, B4,
B5, and B6

LJom

o

~ UD--.o-----'OD~~

L

~

D

C)

mU

JJ5

°D

DO
0
D
Q

D~
0
o ~D

jig

D~
3-37

Di

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

Table 3-5: Default Setting of RS232 Configuration Jumperfields
B5, B6

B3, B4
1

:;

2

16

1

S

0-0

15

2

0

3

0

0

14

3

0

4

0

0

13

5

0

0

12

6

0

0

11

7

0

0

10

8

0-0

9

0

3.8.3 Cable for the Micro D-Sub Connector
The CPU board is delivered with one 9-pin Micro O-Sub to 9-pin O-Sub Adapter Cable. Additional
cables or a 9-pin Micro O-Sub to 25-pin O-Sub Adapter Cable are available from FORCE
COMPUTERS.

3.8.4 RS422/RS485 Hardware Configuration of Ports #1 and #2
The CPU board is delivered with RS232 compatible interface buffers installed on all serial I/O ports.
It is possible to reconfigure I/O ports #1 and #2 to be RS422/RS485 compatible. Termination
resistors can be installed to adapt various cable lengths and reduce reflections. The resistor value
The
is user application dependent. A recommended value for all resistors is 1 KOHM.
RS422/RS485 interfaces of ports #1 and #2 are identical except that port #1 is additionally wired
to a on resistor field which allows connection to the VMEbus P2 connector.

3-38

HARDWARE USER'S MANUAL

SECTION 3

The on resistors are not installed in the default configuration because it may conflict with the EAGLE
module.
Signal

Input

TXDRTSCTS+
RXD+
TXD+
RTS+
CTSRXD-

Output

VME Connector P2

X
X

c29
c30
c31
c32
a29
a30
a31
a32

X
X
X
X
X
X

Description
Transmit Data
Request to Send
Clear to Send
Receive Data
Transmit Data
Request to Send
Clear to Send
Receive Data

The next figure shows the location diagram of the on resistors R563 to R569 and the figure
afterwards displays the connection between the DUSCC 1 and the VMEbus connector.

CAUTION
8efore installing the on resistors to generate the port #1 availability on the VMEbus P2
Connector, please make sure that the EAGLE module which is being used does not occupy the
VMEbus P2 signals c29 to c32 and a29 to a32. Otherwise the board will be damaged.

The devices are labeled according to the following chart.

Port#

Channel

Ba

Bb

Pa

Connector

Resistor Array

1
2

a

83
84

85
86

PD1
PD2

1NMEbus P2
2

J22
J23

b

3-39

SYS68K/CPU-40/41 USER'S MANUAL

Figure 3-12: Location Diagram of the

FORCE COMPUTERS

on Resistors R563 to R569

3-40

SECTION 3

HARDWARE USER'S MANUAL

Figure 3-13:

RS422/RS485 Connection between DUSCC1
Connector P2
+5V

DUSCC

and

~1
2

FH003

68562
VMEbus P2

CHANNEL
19

B

A

Pin No. Pin No.

36

13

41

08

f-so_u-+--+-

33

16

l---oo_-t-+-

34

15

1---00_1-t--t-

39

10

5
C
I---I'IT_---t

~[J

.os

DO
DO 0
D

0

D~
0
o

iD

Jig

D~
3-43

SYS68K/CPU-40/41 USER'S MANUAL

Figure 3-16:

FORCE COMPUTERS

Location Diagram of RS232/RS422/RS485 Driver/Receivers J20
and J21 plus Resistor Arrays J22 and J23

[jom

o
J4.4

~ '---~

,---.JQ

~

L
A

n n----...J'
'---:Ii'r'

D

<::)

~LJ
0

.!lS

Do
0
D
D

D~
0
o

iD

Jig

L...---.....I

D~
3-44

IL.....-,--..II

SECTION 3

HARDWARE USER'S MANUAL

WARNING
1)
2}

Please make sure that the jumper setting is adapted to the user driver module.
Any mistakes could ruin the inserted component upon board powerup.

3.8.5 RS232 and RS422/RS485 Driver Modules FH002 and FH003
To save space and to be able to vary the interface, FORCE COMPUTERS has developed the RS232
and RS422/RS485 modules with the FH002 and FH003. These 21-pin SIL modules are installed
with sockets so that they may be easily changed. The default jumper setting on the CPU board for
the RS232 module is as shown below:

B3 , B4
.:.:.:.:

B5 , B6

1

g

0

16

1

i!iI!e!iiI:

2

0-0

15

2

0

3

0

0

14

3

0

4

0

0

13

5

0

0

12

6

0

0

11

7

0

0

10

8

0-0

9

3.8.6 Summary of DUSCC1
Device

68562 DUSCC

Access Address

$FF802000

Port Width

Byte

Interrupt Request Level

Software programmable

FGA-002 Interrupt Level

Local IRQ #4

3-45

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

3.8.7 Address Map of the DUSCC2 Registers
The following tables contain the complete register map of DUSCC2.

Table 3-8: Serial 110 Port #3 (DUSCC2) Register Address Map

Port Base Address: $FF802200
Address

Offset

HEX

• ''''-1
nt:A

$FF802200
$FF802201
$FF802202
$FF802203
$FF802204
$FF802205
$FF802206
$FF802207
$FF802208
$FF802209
$FF80220A
$FF80220B
$FF80220C
$FF80220D
$FF80220E
$FF80220F
$FF802210
$FF802211
$FF802212
$FF802213
$FF802214
$FF802215
$FF802216
$FF802217
$FF802218
$FF802219
$FF80221A
$FF80221 C

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10-,
11 I
12 I
13-'
14-,
15 I
16 I
17-'
18
19
1A
1C

Description

,Reset
._L __
Value

Mode

Label

00
00

--

R/W
R/W
R/W
R/w
R/w
R/W
R/W
R/w
R/W
R/W
R/W
R/W
R
R
R/W
R/W

DUSCMR1
DUSCMR2
DUSSS1R
DUSS2R
DUSTPR
DUSTTR
DUSRPR
DUSRTR
DUSCTPRH
DUSCTPRL
DUSCTCR
DUSOMR
DUSCTH
DUSCTL
DUSPCR
DUSCCR

Channel Mode Reg 1
Channel Mode Reg 2
SYN 1ISecondary Adr Reg 1
SYN2/Secondary Adr Reg 2
Transmitter Parameter Reg
Transmitter Timing Reg
Receiver Parameter Reg
Receiver Timing Reg
Counter /Timer Preset Reg H
Counter /Timer Preset Reg L
Counter/Timer Control Reg
Output and Miscellaneous Reg
Counter/Timer High
Counter/Timer Low
Pin Configuration Reg
Channel Command Reg

--

W

DUSTFIFO

Transmitter FI FO

--

R
R/W
R/W
R/w
R/w

DUSRFIFO
DUSRSR
DUSTRSR
DUSICTSR
DUSIER

Receiver FI FO
Receiver Status Reg
Transmitter IReceiver Stat Reg
Input + Counter/Timer Stat Reg
Interrupt Enable Reg

--00

-00
--

---00
---

00

00
00

-00

3-46

SECTION 3

HARDWARE USER'S MANUAL

Table 3-9: Serial 1/0 Port #4 (DUSCC2) Register Address Map
Port Base Address: $FF802220
Address
HEX
$FF802220
$FF802221
$FF802222
$FF802223
$FF802224
$FF802225
$FF802226
$FF802227
$FF802228
$FF802229
$FF80222A
$FF80222B
$FF80222C
$FF80222D
$FF80222E
$FF80222F
$FF802230
$FF802231
$FF802232
$FF802233
$FF802234
$FF802235
$FF802236
$FF802237
$FF802238
$FF802239
$FF80223A
$FF80223C

Offset Reset Mode
HEX Value
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10-,
11 I
12 I
13.J
14-,
15 I
16 I
17.J
18
19
1A
1C

00
00

--

R/w
R/w
R/W
R/W
R/w
R/w
R/w
R/w
R/W
R/W
R/w
R/w
R
R
R/w
R/w

--

W

--

R
R/W
R/W
R/W
R/w

--

--

00

-00

----

-00

--

-00

00
00

-00

Label

Description

DUSCMR1
DUSCMR2
DUSSS1R
DUSS2R
DUSTPR
DUSTTR
DUSRPR
DUSRTR
DUSCTPRH
DUSCTPRL
DUSCTCR
DUSOMR
DUSCTH
DUSCTL
DUSPCR
DUSCCR

Channel Mode Reg 1
Channel Mode Reg 2
SYN 1ISecondary Adr Reg 1
SYN 2/Secondary Adr Reg 2
Irransmitter Parameter Reg
Irransmitter Timing Reg
Receiver Parameter Reg
Receiver Timing Reg
Counter /Timer Preset Reg H
Counter/Timer Preset Reg L
Counter/Timer Control Reg
Output and Miscellaneous Reg
Counter/Timer High
Counter /Timer Low
Pin Configuration Reg
Channel Command Reg

DUSTFIFO ITransmitter FI FO

DUSRFIFO
DUSRSR
DUSTRSR
DUSICTSR
DUSIER

Receiver FI FO
Receiver Status Reg
Irransmitter/Receiver Stat Reg
Input + Counter/Timer Stat Reg
Interrupt Enable Reg

3-47

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

Table 3-10: Ports #3 and #4 (DUSCC2) Common Registers Address Map

Port Base Address: $FF802200

$FF80221B
$FF80221E
$FF80221F
II $FF80223E II

Description

Label

Offset Reset Mode
HEX Value

Address
HEX

00
RIW DUSCMR1 Channel Mode Reg 1
OF
RIW DUSCMR2 Channel Mode Reg 2
00
RIW DUSSS1R SYN 1/Secondary Adr Reg 1
II OF II R II DUSS2R IISYN2/Secondary Adr Reg 2

1B
1E
1F
3E

1\

3.8.8 RS232 Hardware Configuration of Ports #3 and #4
Ports #3 and #4 are built around the DUSCC (J24). DUSCC2 is connected to the local 8 bit data
bus and is accessible in the byte mode. The RS232 interfaces of port #3 and #4 which are wired
to the two 9-pin Micro D-Sub connectors (named "3" and "4") on the front panel are identical. All
RS232 driver and receivers are installed in the default configuration. The individual I/O signal
assignment of the two channels is listed as follows:

Signal
DCD
RXD
TXD
DTR
GND
DSR
RTS
CTS
GND

Input Output 9 Pin D-Sub Connector
X
X
X
X

1
2
3
4

5
X
X

X
X

6

7
8
9

Description
Data Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
Signal GND
Data Set Ready
Request to Send
Clear to Send
Signal GND

The following figure displays the connection between DUSCC2 and the D-Sub connectors.

3-48

HARDWARE USER'S MANUAL

SECTION 3

Figure 3-17: Connection Between OUSCC2 and O-Sub Connector for RS232

OUSCC

FH002

68562

6

DSR

7

RTS

CHANNEL

B

Pin No.

Pin No.

36

13

TXD

41

08

SOU

33

16

OU2

34

15

OU1

39

10

RTC

40

09

-L

.-B

-PeTS

-=- -

8a

'11'6

18

19
16

2

15

3

14

4

13

1

RXO

2

TXO

3

'11'7

12

A

oco

(\

02

01

'11'3

14

13

'11'8

16

15

0-

OT"

~cw 6~
GNO

TRC

12

6

~

~
32

17

CTS

44

05

I N1

38

11

DCD

37

12

RXD

10

5

1GJBb

I

'11'1

2

5

4

06

04

17

09

'11'2

10

08

'11'5

05

'11'4

3(!)

9

8

07

I

""'J

The devices are labeled as shown in the following chart.

Port #

Channel

Sa

Sb

Pa

Connector

3

a
b

87
88

89
810

PD3
PD4

4

4

3

"Location Diagram of the RS232 Configuration Jumperfields" is found in the figure on the next page.
The default setting of the RS232 configuration jumperfield is shown in the next table.

3-49

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

Location Diagram of RS232 Configuration Jumperfields 87
through 810

Figure 3-18:

o

j""'V

oo

~

[)

D

D

r-

Is
'-

rW1Lr

I~

[J'
~

""
~

'\..

~

I[

Ql

JI J

~

II

~

I-

~

./

~

o

'---

,-D~

3-50

HARDWARE USER'S MANUAL

SECTION 3

The following is the displayed pinout of the D-Sub connector for RS232 Configuration.

Figure 3-19: RS232 Pinout of the Micro D-Sub and D-Sub Connectors
B) Micro DSUB and DSUB Female Connectors
on the Adapter/Terminal Cable

A) Micro DSUB Male Connector Soldered
on the CPU Board

RS232

RS232

Pa

Pa
GND

DCD
GND

DSR

02
RTS

CTS

70
03

CTS

RXD

RTS

04

DTR

DTR

03

TXo

02

RXD

80

TXD

80

04

70

DSR

GND

OCO

GNo

Table 3-11: Default Setting of the RS232 Configuration Jumperfields
B9, B10

B7, B8
::=:::::

1

::::::::

o

16

1

B

2

0-0

15

2

0

3

0

0

14

3

0

4

0

0

13

5

0

0

12

6

0

0

11

7

0

0

10

8

0-0

9

P-

3-51

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

3.8.9 Cable for the Micro O-Sub Connector
The CPU board is delivered with one 9-pin Micro D-Sub to 9-pin D-Sub Adapter Cable. Additional
cables or a 9-pin Micro D-Sub to 25-pin D-Sub Adapter Cable are available by order from FORCE
COMPUTERS.

3.8.10 RS422/RS485 Hardware Configuration of Port #3 and #4
The CPU board is delivered with RS232 compatible interface buffers installed on all serial I/O ports.
It is possible to reconfigure I/O ports #3 and #4 so that they are RS422/RS485 compatible.
Termination resistors can be installed to adapt various cable lengths and reduce reflections. The
resistor value is user application dependent. A recommended value for all resistors is 1 KOHM. The
I/O signal assignment of each of the channels is listed as follows:

Signal
TXDRTSCTS+
RXD+
RXDTXD+
RTS+
CTSRXD-

Input

Output

9 Pin D-Sub Connector

X
X

1

2
3
4
5
6

X
X
X
X
X

7

X
X

8
9

Description
Transmit Data
Request to Send
Clear to Send
Receive Data
Receive Data
Transmit Data
Request to Send
Clear to Send
Receive Data

The next figure displays the connection between DUSCC2 and D-Sub connectors.

3-52

HARDWARE USER'S MANUAL

SECTION 3

Connection between DUSCC2 and Micro D-Sub Connector for
RS422/RS485

Figure 3-20:

_Q6

lXII.

7

flt1.

Je.
+5V

OUSCC

15

CHANNEL

A

B

Pin No.

Pin No.

36

13

~8a
-B

::oJ

41

08 -

33

16 -

34

OU1
15 -

39

10

40

0U2

09

-

ATC

TRC

---I

15

44

05

IN1

38

11

OCO

37

12

RXO

09

W2

01

W3

--B
-B

14

r--..

!J=
'"

I

r.::-.,4

6

....0;
~

--q

~.....

5

5
6

~

",,7
\.J

02tf
05

,.--...8

W4

V
",9

13

\.J

",10

~
~r-

~
~

10

'-.../

11

4----E)
10 / '

"r

18

W6

08

W5

l

"V

~

17

8b

1~;- 30

16

~

~

32

"~

W1

~!f

~

~

FH003

68562

2

RTS-

9

f

13

'-.../

~415
07

.-1

"I

13

we

12

W7

\.J

16

The devices are labeled according to the following chart.

Port #

Channel

8a

8b

Pa

Connector

3
4

a
b

87
88

89
810

PD3
PD4

3
4

3-53

SYS68K/CPU-40/41 USER'S MANUAL

Figure 3-21 :

FORCE COMPUTERS

Location Diagram of RS422/RS485 Configuration Jumperfields 87
through 810

[jO~

o

[)
[)
D

u

6dD'---JJ~~OM~~

3-54

HARDWARE USER'S MANUAL

SECTION 3

Figure 3-22: RS422/RS485 Pinout of the Micro O-Sub and O-Sub Connectors
B) Micro OSUB and OSUB Female Connectors

A) Micro OSUB Male Connector

on the Adapter/Terminal Cable

Soldered on the CPU Board

RS4221 RS485

RS4221 RS485

Pa

Pa

RXO-

TXORXO-

TXO+

02
RTS+

70

CTS-

03
CTS-

RTS-

RTS+

04

TXO+

05

RXO-

03

CTS+

02

RTS-

01

TXO-

70

RXO+

RXO-

RXO+

80

CTS+

80

04

60

Table 3-12: RS422/RS485 Configuration Jumperfield Setting
B7, B8

1

g

2

3

B9, B10

16

1

~I~~~~I~~:

0-0

15

2

0

0

0

14

3

0

4

0

0

13

5

0

0

12

6

0

0

11

7

0

0

10

8

0-0

9

0

I

3-55

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

The following table shows the PCB locations and devices that have to be inserted according to the
RS232/RS422/RS485 configuration.

Table 3-13: PCB Locations for RS232/RS422/RS485 Configuration

RS232 Devices

RS422/RS485 Devices

Port #

\1

Driver and Receiver FHOO2

Driver and Receiver FHOO3

Resistor Array Ja

~

J25

J25

oJ"-'

4

J26

J26

J28

I') "7

II

The RS422/RS485 compatible interface supports TXD, RXD, RTS, CTS with differential outputs and
inputs. Each port occupies the same nine pins of the D-Sub connector as in the RS232 compatible
configuration, but with a different signal association. The following figure displays the location
diagram for the RS232 RS422/RS485 driver/receiver J25/J26 and resistor arrays J27/J28.

WARNING
1)
2)

Please make sure that the jumper settings are adapted to the user driver module.
Any mistakes could ruin the inserted component upon board powerup.

3-56

HARDWARE USER'S MANUAL

SECTION 3

Figure 3-23:

Location Diagram of RS232/RS422/RS485
J25/J26 and Resistor Arrays J27/J28

o .

...6J

DO
0
D
Q

D~
D
o iD

JI9

D~
3-57

D~

Driver/Receiver

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

3.8.11 RS232 and RS422/RS485 Driver Modules FH002 and FH003
To save space and to be able to vary the interface, FORCE COMPUTERS has developed the RS232
and RS422/RS485 modules with the FH002 and FH003. These 21-pin SIL modules are installed
with sockets so that they may be easily changed. The default jumper setting on the CPU board for
the RS232 module is as shown below:

B7, B8

B9, B10

1

§

0

16

1

j~j:~:j~9:~:~:~::

2

0-0

15

2

0

3

0

0

14

3

0

4

0

0

13

5

0

0

12

6

0

0

11

7

0

0

10

8

0-0

9

3.8.12 Summary of DUSCC2
Device

68562 DUSCC

Access Address

$FF802200

Port Width

Byte

Interrupt Request Level

Software programmable

FGA-002 Interrupt Channel

Local IRQ #5

3-5a

HARDWARE USER'S MANUAL

SECTION 3

3.9 The PItT 68230
The MC68230 Parallel Interface/Timer provides versatile double buffered parallel interfaces and an
operating system oriented timer. The parallel interfaces operate in unidirectional or bidirectional
modes, either 8 or 16 bits wide. The PI/T contains a 24 bit wide counter and a 5 bit prescaler.

Features of the PItT
•

MC68000 Bus Compatible

•

Port Modes Include:

•

Selectable Handshaking Options

•

24 bit Programmable Timer

•

Software Programmable Timer Modes

•

Contains Interrupt Vector Generation Logic

•

Separate Port and Timer Interrupt Service Requests

•

Registers are ReadIWrite and Directly Addressable

Bit liD
Unidirectional 8 bit and 16 bit
8 bit and 1 6 bit

3-59

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

3.9.1 Address Map of the PIIT1 Registers
PI/T1 is accessible via the 8 bit local I/O bus (byte mode). The following table shows the register
layout of the PI/T1 .

Table 3-14: PIIT1 Register Layout

II

Default 1/0 Base Address: $FFBO 0000
Default Offset: . $0000 OCOO
Default Name: PI T1
Address
HEX

Offset
HEX

Reset
Value

FF800COO
FF800C01
FF800C02
FF800C03
FF800C04
FF800C05
FF800C06
FF800C07
FF800C08
FF800C09
FF800COA
FF800COB
FF800COC
FF800COD
FF800C10
FF800C11
FF800C12
FF800C13
FF800C14
FF800C15
FF800C16
FF800C17
FF800C18
FF800C19
FF800C1A

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
aD
10
11
12
13
14
15
16
17
18
19
1A

00
00
00
00
00
00
00
00

----

---00
OF

-------

II

Label

Description

PIT1 PGCR
PIT1 PSRR
PIT1 PADDR
PIT1 PBDDR
PIT1 PCDDR
PIT1 PIVR
PIT1 PACR
PIT1 PBCR
PIT1 PADR
PIT1 PBDR
PIT1 PAAR
PIT1 PBAR
PIT1 PCDR
PIT1 PSR
PIT1 TCR
PIT1 TIVR
PIT1 CPR

"
"

"

"
PIT1 CNTR

"
Count Register

"

--

"
"
"

00

PIT1 TSR

--

Port General Control Register
Port Service Request Register
Port A Data Direction Register
Port B Data Direction Register
Port C Data Direction Register
Port Interrupt Vector Register
Port A Control Register
Port B Control Register
Port A Data Register
Port B Data Register
Port A Alternate Register
Port B Alternate Register
Port C Data Register
Port Status Register
Timer Control Register
Timer Interrupt Vector Register
Counter Preload Register
"

3-60

"
"
Timer Status Register

HARDWARE USER'S MANUAL

SECTION 3

3.9.2 1/0 Configuration of PltT1
The following table lists all I/O signals connected to PIIT 1. The functions of these signals are
described in the corresponding chapter. Additional information is provided in the PI/T data sheet,
included in Section No.5, "COPIES OF DATA SHEETS".

Table 3-15: PltT1 Interface Signals

PI/T 1 I/O Pin

PI/T Signal Name

Connected Signal

Input/Output

4
5
6
7
9
10
11
12

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

Rotary Switch 1

I
I
I
I
I
I
I
I

14
15
16
17

H1
H2
H3
H4

Reserved
Reserved
Reserved
Reserved

18
19
22
23
24
25
26
27

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

34
35
36
37
38
39
40
41

PCO
PC1
PC2
PC3
PC4
PC5
PC6
PC7

..

.
..
Rotary Switch 2
..
..
..

A31 .. A24
Control
for
Accesses in
Slave Mode
Reserved
Reserved
Reserved
Timer IRQ
Lock Cycles
Reserved
Reserved
Reserved

3-61

-

0
0
0
0
0
0
0
0

-

0
0
-

FORCE COMPUTERS

SVS68K/CPU-40/41 USER'S MANUAL

3.9.3 Rotary Switches
There are two rotary switches installed on the front panel of the CPU board. The position of each
switch can be read in via port A of the PIIT1. The next figure outlines the front panel and the
position of the rotary switches. Each rotary switch covers four bits. Therefore, each switch holds
16 positions and the code shown on the switch (i.e., 0-9 and A-F) can be read from the line PAOPA3 (SW1) and PA4-PA7 (SW2) of PIIT1. The following lists the input signals of PIIT1 in relation
to the rotary switch signals.

Rotary Switch Signals Assignment

PltT1 Signal

Rotary Switch

Bit

Data Bit of PI/T Port A

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

SW1/1
SW1/2
SW1/3
SW1/4
SW2/1
SW2/2
SW2/3
SW2/4

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

For application programs, the rotary switches can be used as a general purpose input channel for
diagnostics, configuration selection, or automatic system boot with different configurations.
VMEPROM uses the rotary switches for automatic configuration.

NOTE:

The rotary switches serve a special function in conjunction with the RESET
and ABORT switches. This functionality is built into the BOOT EPROM and
is described in detail in the BOOT Software description of the FGA-002
User's Manual.

3-62

HARDWARE USER'S MANUAL

SECTION 3

Figure 3-24: CPU Board Front Panel and Rotary Switch Positions

!RESET
! ABORT
e

RUN

•

8M

@4
o

@3
o

@2
o
3

@1

4

8
8

5

6

1

7
8

o ___

o

F

9

E

'A

DeB

3

4

5

7

F

9

o ___
E

EAGLE

DeB

MODULE

DEPENDENT

FORCE

o
3-63

6

1

8

A

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

3.9.4 Lock Cycles
On the initial cycle of a line access, a retry causes the MC68040 processor to retry the bus cycle.
A retry signaled during the second, third, or fourth cycle of a line transfer is recognized by the
processor as a bus error, and causes the processor to abort the line transfer and start an access fault
exception subroutine.
When the local MC68040 wants to access a slave on the VMEbus and has already been granted the
local bus, and a master on the VMEbus wants to access the MC68040's Shared Memory and has
already been granted the VMEbus, a bus collision occurs. In this case the FGA-003 signals a retry
to the MC68040 to resolve the collision on hardware level. It is not necessary that software
observes this eve"nt.
When a bus collision occurs during the second, third, or fourth cycle of a line transfer, where the
processor is not able to retry the cycle, the MC68040 initiates a bus error. So the collision appears
on the software level and can be resolved there with considerable time expense.
To prevent the software from being concerned, the following feature is implemented on the CPU40/41 Rev. 2 and succeeding revisions.
The signal ENARMC 16 can be activated by software via PI/T1 Pin PC4. With this signal driven low
a line transfer from the MC68040 is defined as a locked RMC transfer. So the FGA-002, when
being granted the VMEbus, doesn't release the VMEbus until all four long cycles of the line tranfer
are successfully completed or an actual bus error occurred.
When using this feature the FGA-002 must be programmed to drive ASVME high between the locked
RMC similar cycles and not to support real VMEbus compatible Read Modify Cycles. Actual RMC
transfers from the MC68040 are treated the same way. As a result, on a slave board which is
accessible from the VME bus as well as from the VSB, this kind of arbitration locked read modify
cycle can be broken.

PC4:

To enable the feature that line transfers are defined as locked cycles, this bit must be programmed
to low. Be sure to program the FGA-002 so that ASVME is driven high between RMC transfers.
To disable this feature, this bit must be programmed to high. VMEPROM programs this bit to low
by default.

3-64

HARDWARE USER'S MANUAL

SECTION 3

3.9.5 Interrupt Request Signal
TOUT:
The PI/T1 pin 37 is used as an interrupt request line. The 24 bit timer can generate interrupt
requests at a software programmable level. This interrupt request line is connected to the IRQ #2
of the FGA-G02.
PIRQ:

The PI/T pin 33 is used to generate an interrupt depending on the handshake lines of the PI/T. The
PIRQ is connected to the TOUT pin but is not able to generate an interrupt because the handshake
lines are not used and are reserved.

3.9.6 A24 Slave Mode
In order to allow an A24 slave mode as described in the chapter "Address Modifier Decoding and
A24 Slave Mode" , the A31 to A24 address lines are programmable for this mode as described in the
following table displaying the PI/T bit and the coordinating address line.

PI/T Port B Bit

Address Line

0
1
2
3
4
5
6

A24
A25
A26
A27
A28
A29
A30
A31

7

3.9.7 Reserved Lines
Ht, H2, H3, H4, PCO, PCt, PC2, PC5, PC6, PC7:
These lines are not used. In order to retain compatibility to following versions, these lines should
not be used in any applications.

3-65

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

3.9.8 Summary of PIIT1
Device

68230 PI{f

Access Address

$FF800COO

Port Width

Byte

Interrupt Request Level

Software programmable

FGA-002 Interrupt Channel (Timer IRQ)

Local IRQ #2

3-66

HARDWARE USER'S MANUAL

SECTION 3

3.9.9 Address Map of the PIIT2 Registers
The PI/T2 is accessible via the 8 bit local liD bus (byte mode). The following table shows the
register layout of PI/T2.

Table 3-16: PIIT2 Register Layout

Default 1/0 Base Address: $FF80 0000
Default Offset: $0000 OEOO
Default Name: PI T2
Address
HEX

Offset
HEX

Reset
Value

FF800EOO
FF800E01
FF800E02
FF800E03
FF800E04
FF800E05
FF800E06
FF800E07
FF800E08
FF800E09
FF800EOA
FF800EOB
FF800EOC
FF800EOD
FF800E10
FF800E11
FF800E12
FF800E13
FF800E14
FF800E15
FF800E16
FF800E17
FF800E18
FF800E19
FF800E1A

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
10
11
12
13
14
15
16
17
18
19
1A

00
00
00
00
00
00
00
00

----

--

--

--

00
OF

-----

---

Description

Label
PIT2 PGCR
PIT2 PSRR
PIT2 PADDR
PIT2 PBDDR
PIT2 PCDDR
PIT2 PIVR
PIT2 PACR
PIT2 PBCR
PIT2 PADR
PIT2 PBDR
PIT2 PAAR
PIT2 PBAR
PIT2 PCDR
PIT2 PSR
PIT2 TCR
PIT2 TIVR
PIT2 CPR

Port General Control Register
Port Service Request Register
Port A Data Direction Register
Port B Data Direction Register
Port C Data Direction Register
Port Interrupt Vector Register
Port A Control Register
Port B Control Register
Port A Data Register
Port B Data Register
Port A Alternate Register
Port B Alternate Register
Port C Data Register
Port Status Register
Timer Control Register
Timer Interrupt Vector Register
Counter Preload Register

..
..
..

II
II
II

PIT2 CNTR
II

--

II

--

II

00

PIT2 TSR

Count Register

.
..
..

3-67

Timer Status Register

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

3.9.10 1/0 Configuration of PIIT2
The following table lists all I/O signals connected to PIIT2. The functions of these signals are
described in the corresponding chapter. Additional information is provided in the PIIT data sheet,
included in Section No.5, "COPIES OF DATA SHEETS".

Table 3-18: PIIT2 Interface Signals

II

PI/T I/O Pin

PI/T Signal Name

Connected Signal

Input/Output

4
5
6
7
9
10
11
12
14
15
16
17

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
H1
H2
H3
H4

I/O Port via
B12

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I
I/O

18
19
22
23
24
25
26
27

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

Memory Size
"
"
Board 10
"
"
"
"

I
I
I
I
I
I
I
I

34
35
36
37
38
39
40
41

PCO
PC1
PC2
PC3
PC4
PC5
PC6
PC7

MOOLOW
Reserved
RAMTYP
Timer IRQ/Reset
BURST
PORT IRQ
PARITY
ENA24

3-68

I

I

0
I

0
I

0

II

HARDWARE USER'S MANUAL

SECTION 3

3.9.11 Memory Size Recognition
PBO-PB2:

From these lines, the on-board memory capacity can be read in by software. Please refer to the
chapter The Shared RAMII for detailed information.
II

3.9.12 Board Identification
PB3-PB7:

From these lines, the CPU board identification number can be read in by software. Every CPU board
has its own number. Different versions of one CPU board (i.e. different speeds, capacity of memory,
or modules) contain the same identification number. In the case of the CPU-40/41 , the number is
ten (11$20 11 ).

3.9.13 Interrupt Request Signal
TOUT:

PI/T2 pin 37 is used as an interrupt request line. The 24 bit timer can generate interrupt requests
on a software programmable level. Together with the Port Interrupt Request line, the timer interrupt
request line is connected to the 10cailRO #3 of the FGA-002. Therefore the software has to check
whether the interrupt request was generated by the timer or by the port handshake lines.
PIRQ:

PI/T2 pin 39 is used as an interrupt request line. The port handshake lines can generate interrupts
on a software programmable level. Together with the Timer Interrupt Request line, the port interrupt
request line is connected to the 10cailRO #3 of the FGA-002. Therefore the software has to check
whether the interrupt request was generated by the timer or by the port handshake lines.

3-69

FORCE COMPUTERS

SVS68K/CPU-40/41 USER'S MANUAL

3.9.14 12 Bit 1/0 Port
PAO-PA7, H1-H4:
This 12 bit 1/0 port is routed to a 24-pin header B 12 allowing flat cable connection. Eight bits are
connected to PIIT2 port A and are used as inputs or outputs; the remaining four bits are connected
to the PIIT2 handshake pins. This port can be used to build a Centronics type interface.

II

PI/T

Header B 12

,

Signal

Pin

Pin

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
H1
H2
H3
H4

4
5
6
7

1
2
3
4
5
6
7
8

9
10
11
12
14
15
16
17

II

9
10
11
12

The figure on the next page shows the location diagram of Jumperfield B 1 2.

3-70

SECTION 3

HARDWARE USER'S MANUAL

Figure 3-25: Location Diagram of Header B12

[jom

o

D

o
D

6

~ o[j~~

Uo'----.o

3-71

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

3.9.15 MODLOW
PCO

This line is driven low by an Eagle Module if there is one inserted. Be sure to leave this pin undriven
by the PI/T. If no Eagle Module is inserted and this signal is driven low the local lACK daisy chain
is not closed!

3.9.16 RAM Module Configuration Signals
PC2, PC4, PC6:

From PC2, RAMTYP of the RAM module can be read as shown in the following chart.

PC2

RAM Type

1

DRAM
SRAM

0

For more information please refer to the chapter" The Shared RAM".
From PC4, BURST capability of the RAM module can be read as shown in the following chart.

II

PC4

Burst Mode

1

Yes

o

No

II

From PCB, PARITY capability of the RAM module can be read as shown in the following chart.

II

peG

Parity

1

Yes

o

No

For more information please refer to the chapter" The Shared RAM" .

3-72

II

SECTION 3

HARDWARE USER'S MANUAL

3.9.17 Timer IRO/Reset
PC3:
This line can be connected to FGA-002 L1RQ 3 or to the RESET operation via jumperfield 818. An
interrupt can be requested by the PI/T timer or directly by programming this line to low, when the
jumper is inserted in 2-3. With a jumper inserted in 1-2, this bit can generate a RESET which is
equivalent to a Powerup RESET so that the contents of a RAM disk in DRAM area can be destroyed.

3.9.18 PIRO
PC5:
Interrupts from the PI/Ts handshake lines are routed to this FGA-002 LlRQ3 line.

3.9.19 Enable A24 Slave Mode
PC 7:
The A24 slave mode can be enabled via the PC7 bit as described in the chapter "Address Modifier
Decoding and A24 Slave Mode".

PC7

Enabled VMEbus Slave Mode

1
0

A32
A32/A24

3-73

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

3.9.20 Reserved Line
PCt:

This line is not used. In order to retain compatibility to following versions, this line should not be
used in any applications.

3.9.21 Summary of PI1T2
Device

68230 PI/T

Access Address

$FF800EOO

Port Width

Byte

Interrupt Request Level

Software programmable

FGA-002 Interrupt Channel
Timer IRQ:

Local IRQ #3

3-74

HARDWARE USER'S MANUAL

SECTION 3

3.10 The Real Time Clock (RTC) 72423
There is an RTC 72423 installed on the CPU board, containing its own battery to maintain the RTC
function during power down.

3.10.1 Address Map of the RTC Registers
The RTC 72423 is a four bit device. It must be accessed in byte mode and the upper four bits are
"don't care" during read and write accesses. The base address of the RTC is $FF803000. The
following table shows the register layout of the RTC 72423.

Table 3-17: RTC Register Layout

Default 1/0 Base Address: $ FF80 0000
Default Offset: $0000 3000
Default Name: RTC
Address HEX

Offset

Label

FF803000
FF803001
FF803002
FF803003
FF803004
FF803005
FF803006
FF803007
FF803008
FF803009
FF80300A
FF803008
FF80300C
FF80300D
FF80300E
FF80300F

00
01
02
03
04
05
06
07
08
09
OA
08
OC
OD
OE
OF

RTC1SEC
RTC10SEC
RTC1 MIN
RTC10MIN
RTC1HR
RTC10HR
RTC1DAY
RTC10DAY
RTC1MON
RTC10MON
RTC1YR
RTC10YR
RTCWEEK
RTCCOND
RTCCONE
RTCCONF

Description
1 Second Digit Register
10 Second Digit Register
1 Minute Digit Register
10 Minute Digit Register
1 Hour Digit Register
PM/AM and 10 Hour Digit Register
1 Day Digit Register
10 Day Digit Register
1 Month Digit Register
10 Month Digit Register
1 Year Digit Register
10 Year Digit Register
Week Register
Control Register D
Control Register E
Control Register F

3.10.2 RTC Programming
The following programming example shows how to read from or write to the RTC. Please note that
the RTC must be stopped prior to reading the date and time registers. For further details, please
refer to the RTC 72423 Data Sheet in Section 5, "COPIES OF DATA SHEETS" in this manual.

3-75

8VS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

Figure 3-26: RTC Programming Example
/*****************************************
** read RTC 72421 and load to RAM
**
**
30-0ct-87 M.S.
**
*****************************************/
setclock(sy)
register struct SYRAM *sy;
{

register struct rtc7242 *rtc = RTC2;
register long count=100000l;
rtc->dcontrol = 1;
/* hold clock */
while(count--)
if(rtc->dcontrol&Ox02)
break;
if(!count)
{ printf(lI\nCannot read Realtime Clockll);
rtc->dcontrol = 0;
return; }
sy->_ssec[O]
(unsigned char)«rtc->sec10reg&Ox07)*10 + (rtc->sec1reg&OxOf»
sy-> smin
(unsigned char)«rtc->min10reg&Ox07)*10 + (rtc->min1reg&OxOf»
sy->-shrs
(unsigned char)«rtc->hou10reg&Ox03)*10 + (rtc->hou1reg&OxOf»
(unsigned char)«rtc->yr10reg&OxOf)*10 + (rtc->yr1reg&OxOf»;
sy->-syrs[O]
sy->-sday
(unsigned char)«rtc->day10reg&Ox03)*10 + (rtc->day1reg&OxOf»;
sy->-smon
(unsigned char)«rtc->mon10reg&Ox01)*10 + (rtc->mon1reg&OxOf»;
rtc->dcontrol = 0;
/* start clock */
)

/*****************************************
**
write RTC 72421 from RAM
**
**
30-0ct-87 M.S.
**
*****************************************/
wri teclock(sy)
register struct SYRAM *sy;
{

register struct rtc7242 *rtc RTC2;
register long count=100000l;
rtc->dcontrol = 1;
/* hold clock */
while(count--)
if(rtc->dcontrol&Ox02)
break;
if(!count)
{ printf(lI\nCannot read Realtime Clockll);
rtc->dcontrol = 0;
return; }
rtc->fcontrol
5·,
rtc->fcontrol
4·
/* 24-hour clock */
rtc->sec10reg sy-> ssec[O]/10;
sy->-ssec[O]%10;
rtc->sec1reg
(char)(sy->_smin/10)
rtc->min10reg
(char)(sy-> smin%10)
rtc->min1reg
(char)(sy->-shrs/10)
rtc->hou10reg
(char)(sy->-shrs%10)
rtc->hou1reg
rtc->yr10reg
sy-> syrs[O]/10;
sy->-syrs[O]%10;
rtc->yr1reg
rtc->day10reg = sy->-sday/10;
sy->-sday%10;
rtc->day1reg
sy->-smon/10;
rtc->mon10reg
sy->-smon%10;
rtc->mon1reg
O·, rtc->dcontrol
/* start clock */
}

3-76

HARDWARE USER'S MANUAL

SECTION 3

The following figure shows the location diagram of jumperfield B20 for backup supply. The default
configuration uses the onboard battery. Please note that the SRAM on this CPU board is also
supplied via this jumperfield.

Bl

Bl

p

1

"'r
rn:
I

o

1~

Battery is connected to
Backup Supply Line
(default)

Battery is cut from
Backup Supply Line

B20

B20

+5VSTDBY is connected to
Backup Supply Line

1~

+5VSTDBY is cut from
Backup Supply Line
(default)

NOTE

The battery is not installed on the CPU board to avoid damage during shipment.

CAUTION
Before altering jumperfield B 1 or disassembling the battery, please consult Chapter 3.6, "The
Local SRAM".

3-77

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

Figure 3-27: Location Diagram of the Backup Supply Jumperfield B 1 and B20

o

jrv'""

D

0Gf() r - - - - - - - ,

~

[)
D

I)

,oodo D~
/
/

0
o ~D
AWAj5

DD~
3-78

I!

N-r

~

~

nL.r
'---

L-D~

HARDWARE USER'S MANUAL

SECTION 3

3.10.3 Summary of the RTC
Device

72423 RTC

Access Address

$FF80 3000

Access Mode

Byte only

Supported Transfers

Byte only, the upper 4 bits are to be ignored for read and
write accesses

Battery Type

Varta CR 1/3 or equivalent

Interrupt Request Level

Software programmable

FGA-002 Interrupt Request Channel

Local IRQ #0

3-79

This page was intentionally left blank

HARDWARE USER'S MANUAL

SECTION 3

4. FUNCTION SWITCHES AND INDICATION LEOs
The following paragraphs describe all switches and indicator LEOs. Figure 4-1 shows the front panel
of the CPU board.

4.1 RESET Function Switch
A reset of all on-board I/O devices and the CPU is performed if the RESET switch is pushed to the
"UP" position. RESET is held active until the switch is in "DOWN" position. In addition, a local
timer guarantees a minimum reset time of two to three seconds. Power fail and power up also force
a RESET (2-3 seconds), to start the board if the supply voltage is out of range (below 4.8 Volts).

Normal switch position: "DOWN"
If enabled, the reset is also driven to the VMEbus. For more information, please refer to the chapter
"VMEbus RESET Conditions".
In combination with the ABORT switch, the RESET switch has a special function which is described
in the BOOT Software description of the FGA-002 User's Manual.
When the Reset Switch is toggled twice a Powerup equivalent Reset can be generated. The time
lapse immediately after the Reset Switch is released must be 0,2 seconds or less.

4.2 ABORT Function Switch
An interrupt on a software programmable level is provided on the board to allow an abort of the
current program, to trigger a self-test or to start a maintenance program. ABORT is activated in
"UP" position and deactivated in "DOWN" position.

Normal switch position: "DOWN"
In combination with the RESET switch, the ABORT switch has a special function which is described
in the BOOT Software description of the FGA-002 User's Manual.

4-1

FORCE COMPUTERS

SVS68K/CPU-40/41 USER'S MANUAL

4.3 "RUN" LED
The first LED below the RESET and ABORT switch is the RUN LED. This bicolor LED is green if the
processor is not in HALT state. It is red during the RESET phase, and when the processor is in HALT
state.

4.4 "8M" LED
If the CPU board is the current bus master, the BM LED is lit. Optical control is provided through
this LED whether or not the board is working on VME.

4.5 Rotary Switches
There are two rotary switches (SW 1 and SW2) which are four bit, hexadecimal encoded. These
switches are completely under software control. The default setting is $FF. For a detailed
description of the use of these switches under VMEPROM, please refer to the Section No.7,
"Introduction to VMEPROM".
In combination with the RESET and ABORT switches, the rotary switches have a special function
which is described in the BOOT Software description of the FGA-002 User's Manual.

4-2

HARDWARE USER'S MANUAL

SECTION 3

Figure 4-1: Front Panel of the CPU Board

,
!

RESET

ABORT

•

RUN

•

BM

3

4

8
8

5

6

1

7

o ____

8

F

9

E

2

A

DeB

1

3

4

5

6

1

7
8

o ____
F
E

EAGLE

DeB

MODULE

DEPENDENT

FORCE

o
4-3

9

A

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

This page was intentionally left blank

4-4

SECTION 3

HARDWARE USER'S MANUAL

5. THE CPU BOARD INTERRUPT STRUCTURE
All interrupts on the CPU board are handled via the FGA-002 or the hardware which is controlling
the FLXibus.
The interrupts of the FLXibus and the interrupts handled by the FGA-002 are daisy chained. If an
interrupt occurs on the FLXibus with the same priority as an interrupt occurring through the FGA002, the priority is as follows:

Priority of the Onboard Interrupts
Highest Priority
FLXibus
FGA-002

Lowest Priority
The interrupts which are caused by the EAGLE module are described in the Section 6, "EAGLE
Module". Interrupts handled by the FGA-002 are described in the following paragraphs.
The Gate Array installed on the CPU board handles all local and VMEbus interrupts. Each interrupt
request from the local bus through the two DUSCCs, RTC, the two timers, as well as the Gate Array
specific interrupt requests, are combined with seven VMEbus interrupt requests.
Each IRQ source including VMEbus IRQs can be programmed to interrupt the CPU on an individual
programmable level (1 to 7).
The Gate Array supports the vector, or initiates an interrupt vector fetch from the .1/0 device or from
the VMEbus.
In addition to local interrupts, the ACFAIL and SYSFAIL signals can be used to interrupt the CPU on
a software programmable level.
Gate Array supplied interrupt vectors have basic vector and fixed increments for each source. The
basic vector is software programmable.
For a complete description of interrupt handling, please refer to the FGA-002 Users Manual.

5-1

FORCE COMPUTERS

SVS68K/CPU-40/41 USER'S MANUAL

The chart below shows the connection between local devices and the local interrupt request of the
FGA-002.
Base Address

Function

Local Interrupt
Request Number

FGA-002 Pin
Number

RTC

$FF803000

*

0

C07

PI/T1

$FF800COO

Timer IRQ

2

E07

PI/T2

$FF800EOO

*

3

A06

DUSCC1

$FF802000

*

4

B06

DUSCC2

$FF802200

*

5

B05

Device

*

More than one function is available. Please refer to the data sheet of the
coinciding device in Section No.5, "COPIES OF.DATA SHEETS", for a
complete description.

5-2

HARDWARE USER'S MANUAL

SECTION 3

6. VMEBUS INTERFACE
The CPU board contains a VMEbus interface which is compatible with the following standards:
IEEE 1014
The VMEbus interface supports 8, 16,32 bit, and unaligned data transfers. The extended, standard,
and short I/O address modifier codes are implemented to interface to all existing VMEbus products.
Read-Modify-Write cycles on the VMEbus are handled as described in the VMEbus Standard (see
above). The address strobe signal is held low during this cycle while the data strobe signals are
driven low twice, once for the read cycle and once for the write cycle, and high between the both
of them.
All seven interrupt request signals are connected to the FGA-002 which can optionally map every
level and then interrupt the local CPU. A four level bus arbiter together with several release
functions are implemented with all slot 1 functions such as SYSRESET driver and receiver and
SYSCLOCK driver.
The following chapters describe the functions of the interface parts in detail.

6.1 VMEbus Master Interface
6.1.1 Data Transfer Size of the VMEbus Interface
The VMEbus interface contains memory areas where the transfer size is software programmable to
be 16 or 32 bits wide.
The memory areas which contain the software programmable data bus size are fixed mapped and
can't be modified.
The hardware on the CPU board adjusts the transfer size of the data bus automatically, so that no
additional overhead in the programs is necessary.
The table on the next page lists the VMEbus memory areas and their data bus sizes in detail.

6-1

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

Table 6-1: Data Bus Size of the VMEbus

Start Address

End Address

Type

Transfer Size

XXXX XXXX*

F9FF FFFF

VME:A32

PROGRAMMABLE

FBOO 0000

FBFE FFFF

VME:A24

FBFF 0000

FBFF FFFF

VME:A16

FCFE FFFF

\/I\J11I"".A,,\A

IVI~~I-\.L""

FiXED i 6 BiT

FCFF FFFF

VME:A16

FIXED, 16 BIT

PROGRAMMABLE

FCFF 0000

* XXX X XXX X
* XXXX XXXX

V

I

= 0040 0000 for CPU-40x/4 or 0100 0000 for CPU-40x/16

= 0040 0000 for CPU-41 x/4

or 0080 0000 for CPU-41 x/8

NOTE
1)

The data bus transfer size of the areas marked "FIXED" cannot be modified.

2)

The data bus transfer size of the areas marked as "PROGRAMMABLE" can be set
to 1 6 or 32 bits. The default setup after RESET through the hardware is 32 bits.

VMEPROM contains a command (MEM) to set up the data bus transfer size of the software
programmable areas.
MEM
MEM 16
MEM 32

displays the current data bus transfer size
sets the size to 16 data bus transfer bits only
sets the size to 32 data bus transfer bits
(8 and 16 bit transfers are also allowed)

In addition, VMEPROM uses one bit of the rotary switches available on the front panel to select the
data bus size of the VMEbus after RESET or power up.
This default configuration is useful if a user program or an operating system is started, and additional
memory boards with known data sizes are installed.
For details on the usage of the rotary switches, please refer to Section 7, "Introduction to
VMEPROM".

6-2

HARDWARE USER'S MANUAL

SECTION 3

Table 6-2: Defined VMEbus Transfer Cycles (032 Mode)

Transfer Type

031-024

023-016

014-08

07-00

Supported

x

y
y

Byte
Byte

x

Word

x

x

y

x

x

x

y

x
x

x
x

x

y
y

x

x

x

x
x
x

Long Word
Unaligned Word
Unaligned
Long Word A
Unaligned
Long Word B
RMW
RMW
RMW
RMW

Byte
Byte
Word
Long Word

x

x

y
x

x

RMW

x
x

y
y
y

Y

= Read Modify Write

Table 6-3: Defined VMEbus Transfer Cycles (016 Mode)

Transfer Type

031-024

023-016

014-08

Byte
Byte

x

Word

x

RMW Byte
RMW Byte

x

RMW Word

x

RMW

= Read Modify Write

6-3

07-00

Supported

x

y
y

x

y

x

y
y

x

y

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

6.1.2 Address Modifier Implementation
The VMEbus defines three different Address Modifier Ranges as shown in the following table:

Table 6-4: Address Ranges

Mode
Extended Addressing
Standard Addressing
Short I/O

Used Address Lines

Short Form

A 1-A31

A32

1\.1_1\.,)11

T'"\ I-T'"\'""T

I\. ')11
I"'\L""T

A 1-A 15

A16

All allowed and defined Address Modifier (AM) Codes are listed in the next table. The supported AM
codes are marked with an asterisk (*).
The address range of the microprocessor (4 Gigabyte) is split into several areas to support all of the
listed AM codes. The table to follow lists the address ranges and the supported AM codes for this
range.
All I/O and Memory Boards on the VMEbus which will be addressed in the listed address ranges must
use one or a combination of the AM codes to guarantee proper operation.

6-4

HARDWARE USER'S MANUAL

SECTION 3

Table 6-5: Address Modifier Codes

Address Modifier
HEX
Code

5

4

3

2

1

0

3F
*3E
*30
3C
3B
3A
39
38

H
H
H
H
H
H
H
H

H
H
H

H

H
H

H

L
L

H

H

H
H
H
H

H

H

H
H
H
H

H
H
H
H

L
L
L
L

H
H

H

L
L

H

37
36
35
34
33
32
31
30

H
H
H
H
H
H

H
H
H
H
H
H
H
H

L
L
L
L

H
H
H

H
H

H

L
L

H

H
H

H

H

H

L
L
L
L
L
L
L
L

H
H
H
H
H
H
H
H

L
L
L
L
L
L
L
L

L
L
L
L
L
L
L
L

2F
2E
*20
2C
2B
2A
*29
28
27
26
25
24
23
22
21
20

H

H
H
H
H
H
H
H
H

H

L
L
L
L

H
H
H
H

H
H
H

L

=

H
L
L
L
L
H
H
H

H
L
L
L
L

H

H
H

H
L
L
L
L

L
L

H
H
L
L
H

L
L
L
L
L
L
L
H
L

H
L
H
L

H

H

L

L
L

H

H
H

H

L
L
H

H

H
L
L

L
L
L
H
L

H
L

low signal level

Function
Standard
Standard
Standard
Reserved
Standard
Standard
Standard
Reserved

Supervisory Block Transfer
Supervisory Program Access
Supervisory Data Access
Privileged Block Transfer
Previleged Program Access
Previleged Data Access

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Short Supervisory Access
Reserved
Reserved
Reserved
Short Previleged Access
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

H

=

6-5

high signal level

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

The Address Modifier Codes (cont'd)

Address Modifier
HEX
Code

5

4

3

2

1

0

1F
1E
10
1C
1B
1A
19
18

L
L
L
.L
L
L
L
L

H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H

H
H
H
H
L
L
L
L

H
H
L
L
H
H
L
L

H
L
H
L
H
L
H
L

Standard
Standard
Standard
Reserved
Standard
Standard
Standard
Reserved

17
16
15
14
13
12
11
10

L
L
L
L
L
L
L
L

H
H
H
H
H
H
H
H

L
L
L
L
L
L
L
L

H
H
H
H
L
L
L
L

H
H
L
L
H
H
L
L

H
L
H
L
H
L
H
L

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

OF
*OE
*00
OC
08
*OA
*09
08

L
L
L
L
L
L
L
L

L
L
L
L
L
L
L
L

H

H

H

H
H

H

H
H
H

H

H

L
L

H

L
L
L
L

H
L
L

L
H
L
H
L
H
L

Reserved
Reserved
Short Supervisory Access
Reserved
Reserved
Reserved
Short Previleged Access
Reserved

07
06
05
04
03
02
01
00

L
L
L
L
L
L
L
L

L
L
L
L
L
L
L
L

H
H
L
L
H
H
L
L

H
L
H
L
H
L
H
L

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

H
H
H
L
L
L
L
L
L
L
L

H
H
H

H
L
L
L
L

H

L = low signal level

Function
Supervisory Block Transfer
Supervisory Program Access
Supervisory Data Access
Previleged Block Transfer
Previleged Program Access
Previleged Data Access

H = high signal level

6-6

HARDWARE USER'S MANUAL

SECTION 3

Table 6-6: Address Modifier Codes Used on the CPU Board

Address

Range

Address Modifier Code

VMEbus (Extended Access)
A32:032,024,016,08

001110
001101
001010
001001

SPA
SOA
NPA
NOA

VMEbus (Standard Access)
A24 : 032, 024, 016, 08

111110
111101
111010
111001

SPA
SOA
NPA
NOA

VMEbus (Short I/O Access)
A16: 032,024,016,08

101101 SOA
101001 NOA

VMEbus (Standard Access)
A24: 016,08

111110
111101
111010
111001

VMEbus (Short I/O Access)
A 16 : 016, 08

101101 SOA
101001 NOA

XXX X 1XXX*
I~CO:

600

F9FF FFFF
F~OOOO

00 .

FBFE FFFF
FBFF 0000

FBFF FFFF
FCOO 0000

FCFE FFFF

SPA
SOA
NPA
NOA

FCFF 0000

FCFF FFFF
SPA
SOA
NPA
NOA

=
=
=
=

Supervisor Program Access
Supervisor Data Access
Nonpreviliged Program Access
Nonpreviliged Data Access

* XXX X XXXX = 0040 0000 for CPU-40x/4 or 0100 0000 for CPU-40x/1 6
* XXXX XXXX = 0040 0000 for CPU-41 x/4 or 0080 0000 for CPU-41 x/s

6-7

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

6.2 VMEbus Slave Interface
6.2.1 The Access Address
The onboard shared RAM of the CPU board is also accessible from the VMEbus side. Both the begin
and end address are programmable in 4 Kbyte increments inside the FGA-002. The complete
address decoding for the shared RAM logic is performed inside the FGA-002 Gate Array. For details
on the programming of the access address, please refer to the BOOT Software description in the
FGA-002 User's Manual.

6.2.2 Data Transfer Size of the Shared RAM
The VMEbus interface of the shared RAM is 32 bits wide. It supports 32 bit, 1 6 bit, and 8 bit as
well as unaligned (UAT) and read-modify-write (RMW) transfers.

6.2.3 Address Modifier Decoding and A24 Slave Mode
For access to the shared RAM from the VMEbus side, extended (A32) and standard (A24) accesses
are allowed.
The FGA-002 only recognizes A32 accesses.
programmed as described above.

The access address for an A32 access can be

If an A24 access takes place additional onboard hardware translates this A24 access to an A32
access to the FGA-002. This means that the standard address modifier code from the VMEbus is
modified to extended address modifier to the FGA-002. In A24 mode the address lines A31 to A24
of the VMEbus must not be used for address decoding. Therefore these address lines are driven to
the FGA-002 via an additional driver. The value of these address bits are programmable via the
PI/T 1 Port B. For detailed information about the address map and register layout of the PI/T 1 please
refer to the chapter "Address Map of the PliTt Registers".

5-8

HARDWARE USER'S MANUAL

SECTION 3

The following table shows which PI/T bit belongs to which address line.

A31 to A24 for FGA-002 in A24 Slave Mode
PI/T1 Port B Bit

Address Line

0
1
2
3
4
5
6
7

A24
A25
A26
A27
A28
A29
A30
A31

The value of these bits must be programmed according to the access address inside the FGA-002.
For example if the shared RAM access address for VMEbus is programmed to:
Start Address $10000000
End Address $10400000
the PI/T bits must be programmed to:
PI/T1 Port B Bit 7 6 5
000

4

3

1

0

2 1 o
o o o

to allow A24 accesses.
If an A24 master now accesses the address $005000, it reaches the same address as an A32
master accessing the address $10005000.
A32 mode is always enabled and A24 mode can be enabled in addition via the PI/T2 Port C Bit 7.
For detailed information about the address map and register layout of the PI/T2, please refer to the
chapter "Address Map of the PI/T2 Registers".

6-9

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

The following table shows the function of the PI/T2 Port C bit 7.

PI/T2 Port C Bit 7

Enable VMEbus Slave Accesses

1
0

A32
A32/A24

The following table shows the allowed AM Codes for VMEbus accesses to the Shared RAM.

Table 6-7: VMEbus Slave AM Codes

Address Modifier
HEX
Code

5

4

3

2

1

0

3E
3D
3A
39

H
H
H
H

H
H
H
H

H
H
H
H

H
H
L
L

H
L
H
L

L
H
L
H

Standard
Standard
Standard
Standard

Supervisory Program Access
Supervisory Data Access
Previleged Program Access
Previleged Data Access

OE
00
OA
09

L
L
L
L

L
L
L

H
H
H
H

H
H
L
L

H
L
H
L

L
H
L
H

Extended
Extended
Extended
Extended

Supervisory Program Access
Supervisory Data Access
Previleged Program Access
Previleged Data Access

L

L = low signal level

Function

H = high signal level

6-10

HARDWARE USER'S MANUAL

SECTION 3

6.3 The VMEbus Interrupt Handler
All seven VMEbus interrupt request (IRQ) signals are connected to the interrupt handling logic on the
FGA-002 Gate Array. Each of theVMEbus IRQ signals can be separately enabled or disabled. The
FGA-002 Gate Array allows high end multiprocessor environment board usage with distributed
interrupt handling.
The FGA-002 Gate Array uses the interrupt as a D08{O} interrupt handler in accordance with the
VMEbus Standard.
In addition every VMEbus interrupt level can be mapped to cause an interrupt on a different level to
the processor. So for example a VMEbus interrupt request on level 2 can be mapped to cause an
interrupt request on level 5 to the processor.

CAUTION
The CPU board only supports the byte interrupt vectoring.
The byte interrupt vector is implemented on most of the existing boards because the VMEbus
Specification Rev. A and 8 do not include a word or long word interrupt vector. Therefore,
older VMEbus boards can be used together with this CPU board if they are compatible to the
current timing specification.

The complete VMEbus interrupt handling is done inside the FGA-002. Therefore please refer to the
FGA-002 User's Manual for a detailed description of the programming of the interrupt management
functions.

6-11

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

6.4 VMEbus Arbitration
Each transfer to/from an area marked in Table 6-6 causes a VMEbus access cycle. The VMEbus
defines an arbitration scheme to arbitrate the bus mastership. Four request levels are defined as 0,
',2, and 3.

6.4.1 Four Available VMEbus Arbiters
A VMEbus Arbiter may operate in one of the following modes:
a)
b)
c)
d)

Single Level Arbiter
Prioritized 4-Level Arbiter
Round Robin 4-Level Arbiter
Prioritized Round Robin 4-Level Arbiter

The arbiter modes a, b, and c above are defined in the VMEbus standard and mode d has been
developed by FORCE COMPUTERS and implemented on the CPU board. The arbiter mode used is
application dependent.

6.4.2 The On-Board Four Level Arbiter
The CPU board contains a four level arbiter which can be enabled/disabled through hardware. The
four level arbiter together with the VMEbus request level control and the VMEbus interrupter is built
in an LCA which is a programmable gate array.

CAUTION
1)

If the four level arbiter is enabled, the board must be plugged into slot 1 of the VMEbus
rack, as defined in the VMEbus standard.

2)

All other boards must force bus requests at level 0 ... 3 if the on-board arbiter is
enabled.

3)

No other arbiter can be used if the on-board arbiter is enabled.

4)

If an external arbiter is used, the on-board arbiter must be disabled.

5)

By default, the four level arbiter is enabled.

6)

The SGL VMEbus arbiter in the FGA-002 must remain disabled in all cases.

The arbiter can work in the Prioritized 4-level, Round Robin 4-level or Prioritized Round Robin 4-level
mode.

6-12

HARDWARE USER'S MANUAL

SECTION 3

The VMEbus Arbiter/Requester/Interrupter LCA has three internal registers which are one byte wide.
One of the registers is used to control the VMEbus Requester and the VMEbus Arbiter. It can be
accessed on address $FF803E02.

Table 6-8: VMEbus Arbiter/Requester Register Layout
Default I/O Base Address: $FF800000
$OOO03E02
Default Offset:
Address
HEX

Offset
HEX

FF803EO
2

00

Mode Default
Value
RIW

73

Label

Description

ARBRE
G

Arbiter /Requester Register

Table 6-9: Description of Arbiter/Requester Register Bits

Description

Bit

Value

Mode

0

1*

RIW

Request level: low bit

1

1*

RIW

Request level: high bit

2

2*

RIW

Arbiter mode: low bit

3

2*

RIW

Arbiter mode: high bit

4

--

R

No function

5

--

R

No function

R

Setting of arbiter jumperfield:
Arbiter enabled (Jumper inserted)
Arbiter disabled (Jumper not inserted)

6
1
0
7

RIW
1
0

1*
2*

Control of request level:
Done by software
Done by hardware

See the description IIRequest Level
See the description "Arbiter Mode"

ll

6-13

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

Request Level
The control of the request level on VMEbus can be done either by software (bit 7 is set to one) or
by hardware (bit 7 is set to zero).
If the control of the request level is done by hardware the request level is selected via jumperfield
819. The jumpersettings for the VMEbus request levels 0 to 3 are shown in figure 6-1:
Requester/Arbiter Jumperfield 819.
If the control of the request level is done by software the request level is selected via bit 0 and bit
1 of the register. The bit settings for the VMEbus request levels 0 to 3 are shovvn in the next table.

Table 6-10: Bit Settings for VMEbus Request Level
Bit 1

Bit 0

VMEbus Request Level

0
0

0

0

1

1
1

0

1
2

1

3

Default

*

NOTE

If the user wants to select the request level by software (bit 7 set to one) the two jumpers
in jumperfield 819 for the request level (see Figure 6-1: Requester/Arbiter Jumperfield 819)
must be removed before. Otherwise bit 7 can't be set to one.

6-14

SECTION 3

HARDWARE USER'S MANUAL

Arbiter Enable/Disable
The onboard VMEbus arbiter can enabled or disabled via the third jumper of jumperfield B 19 (see
Figure 6-1: Requester/Arbiter Jumperfield B19). The setting of the jumper can be read by software
via bit 6 of the requester/arbiter register (see Table 6-9: Description of Requester/Arbiter Register
Bits).

Arbiter Mode
The arbiter mode of the onboard VMEbus arbiter can be selected by software via bit 2 and bit 3 of
the requester/arbiter register. The bit settings for the three arbiter modes are shown in Table 6-11:
Bit Settings for VMEbus Arbiter Mode.

Table 6-11: Bit Settings for VMEbus Arbiter Mode
Bit 3

Bit 2

Default

0

0

*

0

1

1
1

0

Arbiter Mode

prioritized mode
round robin mode
prioritized round robin mode
prioritized round robin mode

1

6-15

FORCE COMPUTERS

SVS68K/CPU-40/41 USER'S MANUAL

Figure 6-1: Requester/Arbiter Jumperfield 819
Arbiter Disabled

Arbiter Enabled

II

B19 (default)

Bus Request Level 3

B19

.:.:.:.:

1

0.---0
::::::::

6

1

0
-0
:.:.:.;.

6

2

0-0

5

2

0-0

5

4

oJ

':l
...,

I

0-0

I

B19

Bus Request Level 2

0

0

I

.,.A

1

0.---0
::::::::

6

1

.9-0

6

2

0

5

2

0

0

5

3

0-0

4

3

0

0

4

.:.:.:.:

0

819

1

0::::::::

0

6

1

·R

0

6

2

0-0

5

2

0-0

5

3

0-0

4

3

0

0

4

B19

Bus Request Level 0

I

B19

B19

Bus Request Level 1

~

B19

1

§

0

6

1

0.
::::::::

0

6

2

0

0

5

2

0

0

5

3

0-0

4

3

0

0

4

6-16

HARDWARE USER'S MANUAL

SECTION 3

Figure 6-2: Location Diagram of Jumperfield 819

o

D

D

D

6-17

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

6.4.3 The VMEbus Release Function
The CPU board contains several different software selectable bus release functions to relinquish
VMEbus mastership. The Bus Release Operation is independent of whether or not the on-board
arbiter is enabled and independent of the Bus Request level. Easy handling and usage of the bus
release functions is provided through the FGA-002 Gate Array. RMW Cycles are always completed
before the bus is released. VMEPROM allows the user to change the release function through the
ARB command. Please refer to the Introduction to VMEPROM for details. The modes are defined
in the following chapters.

6.4.3. 1 Release Every Cycle (REC)
The REC mode causes a release of VMEbus mastership after the initiated transfer cycle has been
completed. A normal read or write cycle is terminated after the address and data strobes are driven
high (inactive state). A Read Modify Write cycle (RMW) is terminated after the write cycle is
completed by the CPU, through deactivation of the address and data strobes. If the REC mode is
enabled, all other bus release functions have no impact ("don't care"). The REC mode is only for
CPU cycles to the VMEbus, and not for DMA cycles. The programming of the REC mode is
described in the FGA-002 Gate Array User's Manual.

6.4.3.2 Release on Request (ROR)
The ROR Mode is defined as a release of bus mastership if another bus requester has requested bus
mastership and the CPU board is the current bus master. The Gate Array contained DMA controller
can also be the requestor causing such a bus release. The ROR mode is only for CPU cycles to the
VMEbus, and not for DMA cycles. The ROR mode cannot be disabled, it is programmable how long
the CPU stays VMEbus master despite of a Bus Request pending. The programming of the ROR
mode is described in the FGA-002 Gate Array Manual.

6.4.3.3 Release After Timeout (RAT)
A timer with a fixed clock rate is installed in the FGA-002 providing a bus mastership release after
100 microseconds of no CPU cycles to the VMEbus. This release function is active only after the
ROR mode timeout. This function cannot be disabled. The RAT Mode is only for CPU cycles to the
VMEbus and not for DMA cycles. The programming of the RAT mode is described in the FGA-002
Gate Array Manual.

6-18

SECTION 3

HARDWARE USER'S MANUAL

6.4.3.4 Release on Bus Clear (RBClR)
The RBCLR function allows the bus mastership release if an external arbiter asserts the BCLR * signal
of the VMEbus. This function then overrides the ROR function timing limitations. The RBCLR Mode
is only for CPU cycles to the VMEbus and not for DMA cycles. The programming of the RBCLR
mode is described in the FGA-002 Gate Array User's Manual.

6.4.3.5 Release When Done (RWD)
The DMA Controller installed in the FGA-002 Gate Array can also be VMEbus master. It always
operates in transfer rounds (maximum 32 transfers). The bus is always released after completion
of such a transfer round. The other Bus Release Functions are for CPU mastership to the VMEbus.
The VMEbus board mastership is always a CPU or DMA Controller mastership. Gaining mastership
is always a VMEbus arbitration sequence.

6.4.3.6 Release Voluntary (RV)
If the local processor is VMEbus bus master, the release on request counter inhibits the gate array
from releasing the bus for the specified time (See ROR function). After this time elapses, the gate
array may release the bus voluntary if the local CPU does not perform accesses to the VMEbus
within a 100 microsecond time period. After each new access to VME, this 100 us time period
must pass until the bus is released voluntary.

6.4.3.7 Release on ACFAll (ACFAll)
If the board is programmed by the Gate Array to be the ACFAILHANDLER in the VMEbus Rack, and

if the ACFAIL * signal of the VMEbus is asserted, the CPU will not release the VMEbus if it is the bus
master. That is, REC, ROR, RAT, and RBCLR do not operate in this case. If the board is not
ACFAILHANDLER and the ACFAIL * signal is asserted, the board will release the VMEbus
immediately.

6-19

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

Table 6-12: Bus Release Functions

Enabled

Release

REC
ROR
RAT
RBCLR

Yes
V
V
X

Every Cycle

REC
ROR
RAT
RBCLR

NO
V
V
NO

BR(O,1,2} = 0
or
Timeout

REC
ROR
RAT
RBCLR

NO
Y
V
YES

BR(O,1,2) = 0 or
Timeout or BCLR = 0

Function

X

= don't care

Y

=

cannot be disabled

6-20

HARDWARE USER'S MANUAL

SECTION 3

6.5 The VMEbus Interrupter
The VMEbus Interrupter on the CPU board can generate interrupts on the VMEbus interrupt levels
IRQ1 to IRQ7. The interrupts can be generated by software. The interrupter can generate a byte
wide interrupt vector which is software programmable.
The VMEbus Interrupter on the CPU board together with the VMEbus Arbiter/Requester is built in
an LCA which is a programmable gate array. This LCA has three internal registers which are byte
wide. Two of these registers are used to control the VMEbus Interrupter. They are accessed on
addresses $FF803EOO and $FF803E01.

Table 6-13: VMEbus Interrupter Registers
$FF800000
$00003EOO

Default I/O Base Address:
Default Offset:
Address
HEX

Offset
HEX

Mode

Default
Value

FF803EOO
FF803E01

00
01

R/W
R/w

01
00

Label
IRQREG
VECTRE
G

Description
Interrupt generation register
Interrupt vector register

6.5.1 The Interrupt Generation Register
The VMEbus Interrupts on levels IRQ1 to IRQ7 can be generated by software via bit 1 to bit 7 of the
IRQ generation register. Bit 0 of the register has no function (see Table 6-14: Description of the IRQ
Generation Register). An interrupt is generated by setting the corresponding register bit to one.
When the interrupt is acknowledged by the VMEbus Interrupt Handler the bit is automatically set to
zero again.

6-21

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

Table 6-14: Description of the IRQ Generation Register
Bit

Value

Mode

0

--

--

1

VMEbus interrupt IRQ1
Active
Inactive (automatically set to zero again)

R/w

VMEbus interrupt IRQ2
Active
Inactive (automatically set to zero again)

R/w

VMEbus interrupt IRQ3
Active
Inactive (automatically set to zero again)

R/W

VMEbus interrupt IRQ4
Active
Inactive (automatically set to zero again)

R/W

VMEbus interrupt IRQ5
Active
Inactive (automatically set to zero again)

R/w

VMEbus interrupt IRQ6
Active
Inactive (automatically set to zero again)

R/W

VMEbus interrupt IRQ7
Active
Inactive (automatically set to zero again)

0
·1

0
3
1

0
4
1

0
5
1

0
6
1

0
7
1

0

No function

R/W
1

2

Description

6.5.2 The Interrupt Vector Register
The interrupt vector register holds the byte wide interrupt vector for the VMEbus interrupts. It can
be read and written and must be set to the right value before an interrupt is activated. It must not
be changed as long as a VMEbus Interrupt from the board is pending.

,..

......

o-~~

HARDWARE USER'S MANUAL

SECTION 3

6.6 The SYSCLK Driver
The CPU board contains all circuities to support the SYSCLK signal. The output signal is a stable
16 MHz signal with a 50/50 high/low cycle.
The driver circuitry for the SYSCLK signal has a current driver capacity of 64mA.

The SYSCLK signal can be enabled and disabled via a jumper setting at 813.

SYSCLK driven (default)
SYSCLK not driven

Jumper 1-8 inserted
Jumper 1-8 removed

The usage of jumperfield 813 is shown in Figure 6-3 and the location diagram of the SYSCLK
jumperfield is outlined in Figure 6-4.

CAUTION
Only one board (located in slot 1) in the VMEbus environment must drive the SYSCLK signal.

Figure 6-3: Usage of Jumperfield 813
"SYSCLK driven if jumper 1-8 is inserted"

813

8

I~
1

7

6

5

0

0

0

0

0

0

2

3

4

I

6-23

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

Figure 6-4: Location Diagram of B13

o

Gf()

0

i~

IJ

r-------,

~

[)
D
--'1

Ii
!

I\.

I

'------.uc-----'

J42

~........ J3

DOD
J71

170

,.....

0 [j ~ ~
.!!

~~

II

~-

5-24

~

HARDWARE USER'S MANUAL

SECTION 3

6.7 Exception Signals
The VMEbus defines the signals ACFAIL, SYSFAIL, and RESET for signaling exceptions or status.
The ACFAIL and the SYSFAIL signals of the VMEbus are connected to the FGA-002 Gate Array.
The FGA-002 may be programmed to generate interrupts on SYSFAIL and ACFAIL. For detailed
information please refer to the FGA-002 User's Manual.
VMEPROM monitors the SYSFAIL line during the initialization of external intelligent I/O boards. The
ACFAIL line is ignored by VMEPROM.
The FGA-002 drives the SYSFAIL line after Reset until initialization of the board is completed.
To remain compatible to older boards this signal can be enabled and disabled via a jumper setting
at 813.
Jumper 2-7 inserted
Jumper 2-7 removed

SYSFAIL driven (default)
SYSFAIL not driven

The usage of jumperfield 813 is shown in the following figure, and the location diagram of the
SYSFAIL jumperfield is outlined in the figure on the next page.

Figure 6-5: Usage of Jumperfield B 13
"SYSFAIL driven if jumper 2-7 is inserted"

813

8

I:

7

6

5

0

0

0

I
I

......

0

0

0

1

2

3

4

1

6-25

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

Figure 6-6: Location Diagram of Jumperfield B 13

Gf()

o i:V- 0 ,..-------.

~

D
D

D
r-li

LJ'"

,·0
[JD~

,aDO]]
"

./

0

o iD

~f"e

!l

6-26

I'

~

c.rL..
~

~
'-

,-D~

APPENDIX TO THE HARDWARE USER'S MANUAL

SECTION 4

APPENDIX B
MEMORY MAP OF THE CPU BOARD

Start
Address

End
Address

00000000
00000000
00000000

003FFFFF
007FFFFF
OOFFFFFF

Shared Memory (4 Mbyte)
Shared Memory (8 Mbyte) or
Shared Memory (16 Mbyte)

004~,000

F9FFFFFF

VMEbus Addresses (4 Mbyte Shared Memory)
A32: 032, 024, 016, 08

008~000

F9FFFFFF

VMEbus Addresses (8 Mbyte Shared Memory)
A32: 032, 024, 016,08

01000000

F9FFFFFF

VMEbus Addresses (16 Mbyte Shared Memory)
A32:032,024, 016, 08

FAOOOOOO

FAFFFFFF

Message Broadcast Area

FBOOOOOO

FBFEFFFF

VMEbus
A24: 032, 024, 016, 08

FBFFOOOO

FBFFFFFF

VMEbus
A16: 032, 024, 016, 08

FCOOOOOO

FCFEFFFF

VMEbus
A24:016,08

FCFFOOOO

FCFFFFFF

VMEbus
A16: 016,08

FOOOOOOO

FEFFFFFF

Reserved

FFOOOOOO

FF7FFFFF

SYSTEM EPROM

FF800000

FFBFFFFF

Local I/O

FFCOOOOO

FFC7FFFF

LOCAL SRAM

FFC80000

FFCFFFFF

Local FLASH EPROM

FFOOOOOO

FFOFFFFF

Registers of FGA-002

FFEOOOOO

FFEFFFFF

BOOT EPROM

FF803EOO

FF803FFF

VMEbus Arbiter

FFFOOOOO

FFFFFFFF

Reserved

+- ~o 1(0

fLt'

~ 0C c- cl

Type

B-1

SYS68K/CPU-40/41

FORCE COMPUTERS

This page was intentionally left blank

B-2

APPENDIX TO THE HARDWARE USER'S MANUAL

SECTION 4

APPENDIX C
ADDRESS ASSIGNMENT AND REGISTER LAYOUT OF THE 1/0 DEVICES
Serial 110 Port #1 (DUSCC1) Register Layout

Port Base Address: $ FF802000

/

Address
HEX

Offset
HEX

Reset
Value

$FF802000
$FF802001
$FF802002
$FF802003
$FF802004
$FF802005
$FF802006
$FF802007
$FF802008
$FF802009
$FF80200A
$FF80200B
$FF80200C
$FF80200D
$FF80200E
$FF80200F
$FF802010
$FF802011
$FF802012
$FF802013
$FF802014
$FF802015
$FF802016
$FF802017
$FF802018
$FF802019
$FF80201A
$FF80201C

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1C

00
00

Mode

Label

--

RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
R
R
RIW
RIW

DUSCMR1
DUSCMR2
DUSSS1R
DUSS2R
DUSTPR
DUSTTR
DUSRPR
DUSRTR
DUSCTPRH
DUSCTPRL
DUSCTCR
DUSOMR
DUSCTH
DUSCTL
DUSPCR
DUSCCR

Channel Mode Reg 1
Channel Mode Reg 2
SYN 1 /Secondary Adr Reg 1
SYN2/Secondary Adr Reg 2
Transmitter Parameter Reg
Transmitter Timing Reg
Receiver Parameter Reg
Receiver Timing Reg
Counter/Timer Preset Reg H
Counter/Timer Preset Reg L
Counter/Timer Control Reg
Output and Miscellaneous Reg
Counter/Timer High
Counter/Timer Low
Pin Configuration Reg
Channel Command Reg

--

W

DUSTFIFO

Transmitter FIFO

--

R

DUSRFIFO

Receiver FIFO

00
00

RIW
RIW
RIW
RIW

DUSRSR
DUSTRSR
DUSICTSR
DUSIER

Receiver Status Reg
Transmitter/Receiver Stat Reg
Input + Counter/Timer Stat Reg
Interrupt Enable Reg

--00

-00

----00

--00

-00

Description

C-1

SYS68K/CPU-40/41

FORCE COMPUTERS

Serial 1/0 Port #2 (DUSCC1) Register Layout
Port Base Address: $FF802000
Address
HEX

Offset
HEX

Reset
Value

$FF802020
$FF802021
$FF802022
$FF802023
$FF802024
$FF802025
$FF802026
$FF802027
$FF802028
$FF802029
$FF80202A
$FF802028
$FF80202C
$FF80202D
$FF80202E
$FF80202F
$FF802030
$FF802031
$FF802032
$FF802033
$FF802034
$FF802035
$FF802036
$FF802037
$FF802038
$FF802039
$FF80203A
$FF80203C

00
01
02
03
04
05
06
07
08
09
OA
08
OC
OD
OE
OF
10...,
11 I
12 I
13...J
14...,
15 I
16 I
17...J
18
19
1A
1C

00
00

Description

Mode

Label

--

R/W
R/W
R/w
R/W
R/w
R/w
R/W
R/w
R/w
R/W
R/w
R/W
R
R
R/w
R/w

DUSCMR1
DUSCMR2
DUSSS1R
DUSS2R
DUSTPR
DUSTTR
DUSRPR
DUSRTR
DUSCTPRH
DUSCTPRL
DUSCTCR
DUSOMR
DUSCTH
DUSCTL
DUSPCR
DUSCCR

--

W

DUSTFIFO

Transmitter FIFO

--

R

DUSRFIFO

Receiver FIFO

00
00

R/w
R/W
R/w
R/W

DUSRSR
DUSTRSR
DUSICTSR
DUSIER

Receiver Status Reg
Transmitter/Receiver Stat Reg
Input + Counter/Timer Stat Reg
Interrupt Enable Reg

--

-00

-00
---

--00

--00

--

00

Channel Mode Reg 1
Channel Mode Reg 2
SYN 1/Secondary Adr Reg 1
SYN2/Secondary Adr Reg 2
Transmitter Parameter Reg
Transmitter Timing Reg
Receiver Parameter Reg
Receiver Timing Reg
Counter/Timer Preset Reg H
Counter/Timer Preset Reg L
Counter/Timer Control Reg
Output and Miscellaneous Reg
Counter/Timer High
Counter/Timer Low
Pin Configuration Reg
Channel Command Reg

Ports #1 and #2 (DUSCC1) Common Register Address Map

Port Base Address: $FF802000
Address
HEX

Offset
HEX

Reset
Value

Mode

Label

$FF802018
$FF80201E
$FF80201 F
$FF80203E

18
1E
1F
3E

00
OF
00
OF

R/W
R/w
R/W
R

DUSGSR
DUSIVR
DUSICR
DUSIVRM

Description

C-2

General Status Register
Interrupt Vec Reg Unmodified
Interrupt Control Register
Interrupt Vec Reg Modified

SECTION 4

APPENDIX TO THE HARDWARE USER'S MANUAL

Serial I/O Port #3 (DUSCC2) Register Address Map

Port Base Address: $FF802200
Address
HEX

Offset
HEX

$FF802200
$FF802201
$FF802202
$FF802203
$FF802204
$FF802205
$FF802206
$FF802207
$FF802208
$FF802209
$FF80220A
$FF802208
$FF80220C
$FF80220D
$FF80220E
$FF80220F
$FF802210
$FF802211
$FF802212
$FF802213
$FF802214
$FF802215
$FF802216
$FF802217
$FF802218
$FF802219
$FF80221A
$FF80221 C

00
01
02
03
04
05
06
07
08
09
OA
08
OC
OD
OE
OF
10-,
11 I
12 I
13...1
14-,
15 I
16 I
17...1
18
19
1A
1C

Reset Mode
Value

Label

Description

--

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W

--

W

DUSTFIFO

Transmitter FI FO

--

R
R/W
R/W
R/W
R/W

DUSRFIFO
DUSRSR
DUSTRSR
DUSICTSR
DUSIER

Receiver FI FO
Receiver Status Reg
Transmitter/Receiver Stat Reg
Input + Counter/Timer Stat Reg
Interrupt Enable Reg

00
00

--

-00

-00

--

---00

--00

00
00

-00

DUSCMR1
Channel Mode Reg 1
DUSCMR2 Channel Mode Reg 2
DUSSS1R
SYN 1/Secondary Adr Reg 1
DUSS2R
SYN2/Secondary Adr Reg 2
DUSTPR
Transmitter Parameter Reg
DUSTTR
Transmitter Timing Reg
DUSRPR
Receiver Parameter Reg
DUSRTR
Receiver Timing Reg
DUSCTPRH Counter/Timer Preset Reg H
DUSCTPRL Counter/Timer Preset Reg L
DUSCTCR
Counter/Timer Control Reg
DUSOMR
Output and Miscellaneous Reg
DUSCTH
Counter/Timer High
DUSCTL
Counter/Timer Low
DUSPCR
Pin Configuration Reg
DUSCCR
Channel Command Reg

C-3

SYS68K/CPU-40/41

FORCE COMPUTERS

Serial I/O Port #4 (DUSCC2) Register Address Map

Port Base Address: $FF802220
Address

HEX
$FF802220
$FF802221
$FF802222
$FF802223
$FF802224
$FF802225
$FF802226
$FF802227
$FF802228
$FF802229
$FF80222A
$FF802228
$FF80222C
$FF80222D
$FF80222E
$FF80222F
$FF802230
$FF802231
$FF802232
$FF802233
$FF802234
$FF802235
$FF802236
$FF802237
$FF802238
$FF802239
$FF80223A
$FF80223C

Offset Reset Mode
HEX Value
00
01
02
03
04
05

00
00

06

00

07
08
09
OA
08
OC
OD
OE
OF
10-,
11 I
12 I
13-1
14-,
15 I
16 I
17-1
18
19
1A
1C

Label

Description

RIW
RIW
RIW
RIW
RIW
RIW

DUSCMR1
DUSCMR2
DUSSS1R
DUSS2R
DUSTPR
DUSTTR

RIW

DUSRPR

--

RIW
RIW
RIW
RIW
RIW
R
R
RIW
RIW

DUSRTR
DUSCTPRH
DUSCTPRL
DUSCTCR
DUSOMR
DUSCTH
DUSCTL
DUSPCR
DUSCCR

--

W

--

R
RIW
RIW
RIW
RIW

--00

-----

-00

--

-00

00
00

-00

Channel Mode Reg 1
Channel Mode Reg 2
SYN1/Secondary Adr Reg 1
SYN2/Secondary Adr Reg 2
iTransmitter Parameter Reg
iTransmitter Timing Reg
RAt'Ai\lAr
P~r~rY\o+or Ron
....... ""' .......... ...., . . . . . . . . . . . . . . . . ....,.,,""".
IIV~

Receiver Timing Reg
Counter/Timer Preset Reg H
Counter /Timer Preset Reg L
Counter/Timer Control Reg
Output and Miscellaneous Reg
Counter/Timer High
Counter/Timer Low
Pin Configuration Reg
Channel Command Reg

DUSTFIFO Transmitter FIFO

DUSRFIFO
DUSRSR
DUSTRSR
DUSICTSR
DUSIER

Receiver FIFO
Receiver Status Reg
ITransmitter/Receiver Stat Reg
Input + Counter/Timer Stat Reg
Interrupt Enable Reg

Ports #3 and #4 (DUSCC2) Common Registers Address Map

Port Base Address: $FF802200
Address

HEX
$FF802218
$FF80221E
.$FF80221 F
$FF80223E

Offset Reset Mode
HEX Value
18
1E
1F
3E

00
OF
00
OF

RIW
RIW
RIW
R

Label

Description

DUSCMR1
DUSCMR2
DUSSS1R
DUSS2R

Channel Mode Reg 1
Channel Mode Reg 2
SYN 1/Secondary Adr Reg 1
SYN2/Secondary Adr Reg 2

C-4

APPENDIX TO THE HARDWARE USER'S MANUAL

SECTION 4

PltT1 Register Layout

Default I/O Base Address: $FF80 0000
Default Offset: $0000 OCOO
Default Name: PI T1
Address
HEX

Offset
HEX

Reset
Value

FF800COO
FF800C01
FF800C02
FF800C03
FF800C04
FF800C05
FF800C06
FF800C07
FF800C08
FF800C09
FF800COA
FF800COB
FF800COC
FF800COD
FF800C10
FF800C11
FF800C12
FF800C13
FF800C14
FF800C15
FF800C16
FF800C17
FF800C18
FF800C19
FF800C1A

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
10
11
12
13
14
15
16
17
18
19
1A

00
00
00
00
00
00
00
00

--

--

----00
OF

----

--

---

--00

Description

Label
PIT1 PGCR
PIT1 PSRR
PIT1 PADDR
PIT1 PBDDR
PIT1 PCDDR
PIT1 PIVR
PIT1 PACR
PIT1 PBCR
PIT1 PADR
PIT1 PBDR
PIT1 PAAR
PIT1 PBAR
PIT1 PCDR
PIT1 PSR
PIT1 TCR
PIT1 TIVR
PIT1 CPR
"

"
"
PIT1 CNTR
"
"
"
PIT1 TSR

C-5

Port General Control Register
Port Service Request Register
Port A Data Direction Register
Port B Data Direction Register
Port C Data Direction Register
Port Interrupt Vector Register
Port A Control Register
Port B Control Register
Port A Data Register
Port B Data Register
Port A Alternate Register
Port B Alternate Register
Port C Data Register
Port Status Register
Timer Control Register
Timer Interrupt Vector Register
Counter Preload Register
"
"
"
Count Register
"
"

"
Timer Status Register

SYS68K/CPU-40/41

FORCE COMPUTERS

PI/T2 Register Layout

Default I/O Base Address: $FF80 0000
Default Offset: $0000 OEOO
Default Name: PI T2
Address

Offset

HEX

HEX

Reset
Value

Label

FF800EOO
FF800E01
FF800E02

00
01
02

00
00
00

PIT2 PGCR
PIT2 PSRR
PIT2 PADDR

~~Q()()~()'2
I \Jv""" .... V'tr.tI

f"\'J

rll

FF800E04
FF800E05
FF800E06
FF800E07
FF800E08
FF800E09
FF800EOA
FF800E08
FF800EOC
FF800EOD
FF800E10
FF800E11
FF800E12
FF800E13
FF800E14
FF800E15
FF800E16
FF800E17
FF800E18
FF800E19
FF800E1 A

04
05
06
07
08
09
OA
08
OC
OD
10
11
12
13
14
15
16
17
18
19
1A

vv
""

I

V-..I

00
00
00
00

------00
OF

---

-----

OIT')
L

Description

nOl""\l""\n

rouun

PIT2 PCDDR
PIT2 PIVR
PIT2 PACR
PIT2 P8CR
PIT2 PADR
PIT2 P8DR
PIT2 PAAR
PIT2 P8AR
PIT2 PCDR
PIT2 PSR
PIT2 TCR
PIT2 TIVR
PIT2 CPR
"
"
"
PIT2 CNTR

"
"
Count Register

"

--

"
"
"

00

PIT2 TSR

--

Port General Control Register
Port Service Request Register
Port A Data Direction Register
Port 8 Data Direction Register
Port C Data Direction Register
Port Interrupt Vector Register
Port A Control Register
Port 8 Control Register
Port A Data Register
Port 8 Data Register
Port A Alternate Register
Port 8 Alternate Register
Port C Data Register
Port Status Register
Timer Control Register
Timer Interrupt Vector Register
Counter Preload Register
"

C-6

"
"
Timer Status Register

APPENDIX TO THE HARDWARE USER'S MANUAL

SECTION 4

RTC Register Layout

Default 1/0 Base Address: $ FF80 0000
Default Offset: $0000 3000
Default Name: RTC
Address HEX

Offset

Label

FF803000
FF803001
FF803002
FF803003
FF803004
FF803005
FF803006
FF803007
FF803008
FF803009
FF80300A
FF80300B
FF80300C
FF80300D
FF80300E
FF80300F

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF

RTC1SEC
RTC10SEC
RTC1 MIN
RTC10MIN
RTC1HR
RTC10HR
RTC1DAY
RTC10DAY
RTC1MON
RTC10MON
RTC1YR
RTC10YR
RTCWEEK
RTCCOND
RTCCONE
RTCCONF

Description
1 Second Digit Register
10 Second Digit Register
1 Minute Digit Register
10 Minute Digit Register
1 Hour Digit Register
PM/AM and 10 Hour Digit Register
1 Day Digit Register
10 Day Digit Register
1 Month Digit Register
10 Month Digit Register
1 Year Digit Register
10 Year Digit Register
Week Register
Control Register D
Control Register E
Control Register F

C-7

FORCE COMPUTERS

SYS68K/CPU-40/41

This page was intentionally left blank

C-8

APPENDIX TO THE HARDWARE USER'S MANUAL

SECTION 4

APPENDIX D
PIN ASSIGNMENTS OF THE EPROM SOCKETS
Pin Assignment for EPROM Area

2

2

7

7

2

2

1

o

0

vpp

VCC

CE

2

39

015

3

38

NC

014

4

37

A15

013

5

36

A14

012

6

35

A13

011

7

34

A12

010

8

33

A11

09

9

32

A10

08

10

31

A9

GNO

11

30

GNO

07

12

29

A8

06

13

28

A7

05

14

27

A6

04

15

26

AS

03

16

25

A4

02

17

24

A3

01

18

23

A2

00

19

OE

20

1

~
~

0-1

A1
AO

SYS68K/CPU-40/41

FORCE COMPUTERS

This page was intentionally left blank

0-2

APPENDIX TO THE HARDWARE USER'S MANUAL

SECTION 4

APPENDIX E
CIRCUIT SCHEMATICS OF CPU BOARD

E-1

FORCE COMPUTERS

SYS68K/CPU-40/41

This page was intentionally left blank

E-2

~=~~=--f-===-=-_~
'i. . .

r--

........... ,....,

....

.... 1"lt")1"l

"I "
o

",.

:::>
...

:::>
Do

~

9TI

RU£JIiQ'____ - -:~.-

II
II

B-

--

............

D

~~

_+--I;;

g

- ---~-=t=t--~------.------~

~

,,~

----H--l~=-===t+ ~ ~+H+++ I I I I II I II I I I I I
J 42

_ ACPU! 0: l.!!

~

J40
58040

ItfSETCPI

.n_

=
•
IIESETCPO

13

ft • •

L'" ""

11115

.J'iI.C!'lIJ_ TIl

-J'SICl'J.I~psi2

l'ntfJU ~..lli PS'
JSTCPUO. T15- -_.

......
•

fIlS

4

TDI
TOO
TIIS

5'_

.

+5V

OCPUO

1.0
v

=~~~:~~
tlV

2

__

.Je

h~i:·13.

~

----~--__r--.-

r--~r--

~"~ ~~~~~~~~~.=SS~~~~~S~~""

N_

~

D--

~r--~

......... ......

Q

c

T

8

....

II

Cl

:~ I~f'
u.. :~~~~

AJ

--»

>Aft . . .

A4

1.1100

IIII~:
- :::

1.13

012
DI3

-

AI4
AI5
AU
AI7
Alii

DI4
DI5
DII
D17

--_..

AU

A20
UI
U2

...

1.23

:::Itl! 1-I
1.2.

U7

U.

A30

110

:-1/0

-cJ

>-3
... 4

L.JIAU{"--::t,
ASIIDD

A8
AID
All
AI2

All .AL.......ACPUll __

vee
QMO

-t

A5
AI
1.7

A28

JiII1JIII'

mrr

0

:::0

-

~

•

DCPU;

..

,.~

L------Ps~___t

fLNI
fLNO
UPAI
UPAO

UIO'---·

R/W

m't:;;~'

CfJl

SIZO

II

~5Y-

-~

~
L+-Ittlt±±t:±t=±-++-+±iWH=-+++-++----++:t-H+Httf-tt-ttt C.:----- _____--.-S

-----------

1/0... 5

:~g::o

:~g::~

rll

~A
'"

~::

~g:: ~

:1/0-:11
~g:;:

:~g::~

I/O-iUClN
1/0-"

:

1/0>-15
1/0-11

:~g:~:

~

:~g:::

g

:4~ ~ 7

2.14.17
2.11
2.17

I/t~~:

ft" U U , " A f t

r""'''Y~U!!::.I!---

r

TACPU
.ACPJI.J.

..ACfIll
ACPUlO: 311

I/o-t 1 t-!!,=-:M~
I/O-'O~""""'"h':~

~--

ACPU2

IPEIIDlnl
~YY
AYE e ------ll!1.!!L

1/0-7
I/H

l

I/00l. f-'l'l'--...!Ilo:kaL

.AE&At_
'FGiO-- _ _ _ ~_.......Jt~:~g:~;

ft

§"i.e: •.

++-+-+-

4.8

Il.14
.3
2

I/O~OUT ~~
I{O

n2~

~

21
I

2.10
2.17
14.17
14
II

.-+++-1-1+++-1-1-+++-----+------

SCt~~~~

TA

Jill

2. Il. I 7
13.17
Il. I 7
13
2

:AII
I/O-TClKIN :~g:~~
------¥--!'~;--~ 1/0-22
1/0-"
W.~~~'-11/0-2l
1/0-50
~~~~:-i1/0-24
1/0-41 ,...,..o-----=-~=_~~~~;_f[/O-U
1/0-48 ~!---'-'","",:..M--,
~~~---!1'-1 F/G-2I
1/0-47 ...,'-'::J
~~~~'--ll 10-27
1/0-41 I-!-lf-.~~!¥"
~-* 1/0-28
1/0-45
.FCOF;A
.2;) ~,,~!~
:~g:U
- AFGAJ
1/0-42 f-g-~~

SCO ....LL-'--~~
TS
TIP

-'

_~~~E_D-'!--1:~g:g

~-. - - - - -

~
-~

LOCK
LOCKE

ClOUT
III

L

r.~"'"

IIODLOW

1/0>-70

:I/o-t.
~g::;
I/o-tt

i ~o::

:8. ,

17

3

A
: 4~i?'

__ ____

B .---.-~---- - ___ =r==.~ '===-~~

=r.

~: 14. 17 DrQA! 0: III

DrQAeo: 31l

C
_ _ _._____~=.=~T---'~'

0

DFQAU):~

DTRAe 0: 311 11. 11
ATRAe 1: 311

ACPU! 0: 311

:73.1'.~
RESKEYl

lJ

13. 14

I • I 4. I 7

1.17
1.17
I. I 4. I 7

If£SrTCOr Ull.
.rSKEYI
Ei

-

LlcKDEl

-. ------t---r-- .--....-- ---'-

...._-

--

_JlAl.JIIiA_

,"-

"-_ ..

~ 1-.

=II

-----~

I-~.

.-~.~~--

-.-------~-~------

_l.illQA

..RUi........

H?rCA

DIll

...

~B

-t-=-mrlli--

r

QN0F-i~
34

I"""
ClACK

,~r--- ----~
- - - - - ---- - t=~

GNO

_---..S1ZOf-'~

,'--

m:~

_._ SI7[O

"--'--'

...BW£.QA

DCPUll

JI,l.JIl'"--~-11/0-1

fJlIo~'&-;;-;;:-1;I: ~t~
1-.J-I1Iof.!~~~: ~g::

I:jt~~~~~:~~
1/0-\2
1/0-\3
~--~~~~~4-.

++t~""--I----t·~~~~~l..~"'--~--:'ll1: :~g::;
"'

:) -r

I

,
I 13 17
•

•

1/0-TeLICI.

Al :1.0

1/0-22
1/0-23

ni
ni

All

~n

In
ni orCA .I ,

DI

nt/ual

nr.':!u~i.':f

1/0-47

:~g:~~

:~t~~
:~g:~~

-

72

~
'2

114

I •

1-"~~lIirJlU.2,. .I

~LL~

Ull

..Dill

m

gE~.U

:~m:1E

DCPU27
DCPUZI

=ll

YIIQ3
YIRQ2

m.....=.JillL

~~-~H':'--'"
~!-!---M-li~--'I
~~-~:=~
r:;~-~~-

....

...

IA~Y~u---------~~~

r:;~----------fiI!H.!Al: ~g:::

ACPUU
ACPUI7
ACPUI I
ACPUI.
ACPU20
ACPU21
ACPU22
ACPU23

•t

.~~.
'1»1-'--+
.IRXOUL CJ •

!~I
:r,:::
_._ . ~-

..Dl'ASll

1--~~;A-r.-1: ~t:

3

I;;;;; ~;; I:::

--- H~U--·]Frcf

120

I. 4. Dllill1P!!1
•• 13.14. "
J c::r--'llJtfJlt

_

--LL

I~."'-:::::

CI f
U
.______ Gfj;A._. ll.( IIGCPU
_IGACI._ .. - IIGACI(

;~!:~:Q

on...
on
S31

IRr'A

~'~'

DCPUI 0: 311

2

..tW.GAIl-11
..-kI..UL--ill-jCKT III

-'---~-~-

RrSElLDC AI f
JlAL.I["---ll.~H~

§-DW~
Ii-

iliff
.
RCt lIN "

~!.-!!+-1AVllEI

AVIlE 2

ill

BltlllL!!C.

1.1 '.17
1.14.17
1.1 '.17

t

~GA002

GNO SWI

§D-'z.~_IiAA t

• II

t."II

I .:.

I'

--~---"..,.

:Bfl~ll~f

'.1 l.14
I

~~5¥

'.11.
11

DLlO'L~L....._~~..........

~~ii.~~ji=~iir=~~~~~~~~[~
gt:~

,--..;;.;;.;. . .- ....
OLOCI 0: 71

L

lL4-4............~.........,.

liND

SYS68K/CPU-40

+5Y

~

--.---=~_~ L_-_--=-~=--_-~==-~=C__ ~~-=--=---· -------I. . . ~_~_~_~_R_s.-'--I__
F
_C_OU_

4.'. "
17 14.

I4

REV. 2

_1:::.:: J

l_C_A_r_G_A-_O_O_2

r-----------c--- -

_J

o
AlOC! 0: 231

J67
PAL22Vl O-Pl CC

.0

WCK :~g':

IZO:B~

III i ~ii1i

r

Ii I!ri

t. 1 7

I ''

ICSIRTC

------...L--ll: m:i
.3

4:

i

,--------

i~~"

,ill

-I;';r-I~

J3
74F244

~~

0[8~1C>

~YO

n.vv..
.. hr. 1

f'

iii\;:~'

.J

2

AO~~V.V.-

In -

I/oe

----

a

-----~-------------,--- ---~-------------

CJ

:z

J71
PA116LB-PLCC
1/07
1/06
1/05
1/04
1/03
1/02
1/01

RESETCPO

I tP~I"7

-=--=--=--=--=--=--=--=--=--=--=-ijlP"tTTltlotCPiC
-------

:: : ~

I

~

I

I l. 17
13.11
13.17
14.17
14.17
14.17
1. I. 14. I a

4
D

Jl.EStlCP 1--

I~~

_ _ _ ._~ ___._ _ _ _ _ _. _ ._____ ----'

SYS68K/CPU-40

===--A---------------r_-L-____

8

C

FORCE
COMPUTERS

CPU ADDRESS BUFFER

REV.

2

SHEET l
FROM 18
SHEETS

B

____________ A

----_~______
--~-- -~-----

2,6,7,8,

DLOCI 0: 71

C

o
2,18

----------~--~----

OLOCI 0: 71

8,14,17

ALOCI 0: 2J1

3,5,1,7,

ALOCIO: 2J1

ALOCI 0: 2J1

J 16

8, t, 17

RTC72423

,----

J

e>-_C.sRIC.__ _

2,14,18~--

~

+5V

_ _ ---J
2

-;r

I

81

BAT!

l--L--L~ ~~I
GND

12: 15, I 8
3
3,13
2,14,18

0

SYSTDBY

-

.;r.t.

820
0

1

c
.

II

~2~.~~

121

t

r#-------

03_

I

B~a:i't

JI~-

~~

CESRAU

J~--GND

~

3

3
1,2, t, I J,
14,16

10

I J, 14

j

I~I

~

1,8

~-~ ~/;~~;8

-.-

QND

c::::>--1'GlII!.ll----

4
J

0

CSBOOT

SYS68K/CPU-40
A

_-~_==r:

_____

--4----

B

________ C

j~OMPUTERSI RTC SRAt.l BOOT-PROM

C

8

DFIOAI 0: 311

Of CAl 0: 311

11

2,3,14, I 7

3,4,6,7,

Al DC! 0: 231

AlOCI 0: 231

ft, t, 17

~-----

~

2,14,18

C)- CSEPR

1,2,17

D>--"A..
SfLlG",A~_.~~______________

1---------

-h
J33
74F244

JJI
74F244

J29

CSEPR

EPROM64K16
Aloe
At
~
AL
Al

g

21

DO Ii
18
01 11
02 1&
03 15
04
05
06
2
07
08 r ~o

AO
AI
A2
AJ

A5
AL
A6
Al e
A7
~ fo
AS
AL II
A9
~~.-~ AIO
All
AI2
AI3
ALOCI
AI4
~lL A15

Ot
010

DII

~-t
r-

012
013
014
015

ASF~er
2~lj[

O£A

IQ

0£8

OF

DE
nr

AD
AI
A2

OF

!~

DE

A5
AS
A7

~

~~
-ill!

Y2
-{>-

~~

g~

12

L--_--.J

nrPR'5

I

011-1
g: ~ '7

I

0121F
013'4

l.

[PRnlll

~L.El'RDJI.l8.

nt
II

g~g~ r+_

Y7

g:; ~

~AO

_ D PR16
-,

g~ :-.

V5
VI

~- mg~~·~
J

DEPR16

DO I

6

ypp 'I

40

~OEii

EPROM64K16

m~~l
N. C.

~

JJO

VO~
VI

n~

Jt---

At

I

~

i1:~
~:~
~::

--

19

DEPR2i _

- .~. -

-

~~

~~

Y2
-{>-

A7

w.:~--'lIrilUf9

~:
Y7

2
-~--

..

~hHilll=l

ASfCAilier
20 lj[

N. C.

..

30

GND

-

~'"

GNO

+SY

+5V

J32
74F244

GND

JJ4
741-"244

i

~-i

3

vo

...il.

YI

16

.-tl
.Ii

~
5

J

1~

Fe

~iiEii

I

DEGA8
9

R
·DEPR24

rc f!
G 14
'G 15

DEPR! 0: 311

j
I

"

4

____ _

r~.-jll-··· - - .-.---.-.---. -- . _.- --_._--._.- 1
~~~I~-t~ ~~~-+---------------. -----------.. .-.----.------.-----

-~-- . - -

AD

26

12

YO

If--.

Df!;AH

~~~t6

AI
VI
A2
Y2
A3 -{>- V3
At
Y4
AS
V5

31

'CA

~f8'

I

'Q

rCA
GA 10

!~~;

rcA 1
I

+SV

II
~Lt

LrmD'i
1

ALOC20

J-f]

4

1

d..rPJlOJIL ______ . ___

_ ________ ._

I I1

___ ____________________ .. _ _ _ ~
12 ......-"
I

14

Bl1

I
r-lfAfC

I

NAME

f:_~~J....91·fK~
I

FORCE
COMPUTERS
----~_~=.==_-=:.._._A _=--===_~.~==r==~_==__==_==e=_==--~===_~-.==~-=_===.-===~===_..c--==--======._

SYS68K/CPU-4Q
~--------.-

-

.

REV.

2

-.-_._----- j - - . _ - -

SYSTEM (PROMs

SHEE T 5
fROIl 18
SHEETS

J
I

J

'I

-

-r ___

~-A----_=~~=-=-

r--

"---8- - - '-----L---------~=~·-C~~,_~--=__===--

D
+5Y

1I

G-'----

3, t, S, 7,
I, ',17

a"a"-

U:l~,14

TXO
_ _ _ ---.1... sou

--B"

+

F'·----"""-""oo

"

§JiHr~

-e'

- "---"""--

--- _85,

[!]

POI

, , ,--"
" """'M 'HI

'

0"

I

;

L _______ ,_

I

RXO

... : :"

-ltv

I

I

I

I21

[7L0

'_

14,15,18

~=~
..,

_ _1

I....00

B-tIf","- "
3

M"
WIn

::=~~ ~1~E; ~T~~~:IL----~-:~~jr~-= " "~- - - 1O'-",---LIIIlN2C;CIHHll~-l !~
--t---,~Jj-~;: +12Y--------~~~~~---r
:::~::::-t-,~, ~---~ I ::: :;~;:'. .

2, t, 7,1,
_,14, I 7

3
7, I",,,

J20

ell~
"''-1~-

",,,,,71

2

r~~_~_

.1

____

AlOCI 0: 231

""

I

12,15
t 2,15
12,15
12,15

12,IS
12,15
12,1,5

12,15

I

I

H
I

1

II
I I
I '

C

2, I 8
2,111

3

1

X~ l ·.~
DCDIII

_
4

II
i

,......'--"""'.'n.

1·
... '"
--'--IOP--

H

• '"

1

I

IIL~_

-- ______

I

~

UoIIJL-....... .....l.-

I

L--

I

-rj

14

'Ill!

SYS6BK /CPU-40

A

---- 1--0.------8 --------

,
_
-~ FORCE
I
__________
~___-------,---------- COMPUTERS

DUSCC-t

I REV.

I ~::T~' J
SIIEET'

8

A

C

0_______ _
.5Y

3,4,5, "
I, ',17

J24
68562PlCC

AlOCI 0: 211

J25
FH002

~

':ITXD

14

I

I i

-1

L

I

I
GIIO

.SY

1

~'

I

.

I

n

GNO

FH002
PD.
Dsua'-1iI1 CRD

I

II

S2

J26

1

121

GIlD

+5Y
112

II
131

II

~::~~8
+5V ••
GilD

5V

't

~
GND

GilD
CliO

+~y

GIlD

+Sy

I I LI _________

m~~

--

47

Q2

HAL

II

~D

12C!"
"CH'

I

=1-:10•

~
J4

~---·------------::iE--B8-J::
t----e"",
~

L_._.

I

.

I

5

&'!CHf

, Cll

4

1_-r5

.-

eND

GND

SYS68K/CPU-40

_______.====_

_________

~-~==__~===~·_~~~=.I~

REV.

--

FORCE
'-Fl--====--=--===r---~=-==-=-=-_~~-C-::~-=~~~=_=~~=~_--'-l COYPUT ERS

I

DUSCC-2
I

SHEET 7
FROII 18
-"-ETS

~II&

'J

---A---~---=r--------------~-------B--- ~-----_u---r---------C------~-_-J-L---

_ __

o

/

I

AP IT( 24: 311
2,4,6,7,9,
14,17

3,4,5,6,7,

DlOC! 0: 71

OlOC! 0: 71

Al DC! 0: 23J

AtQC!Q:.~!

II

9,17

6,7,9, 1

~l

1,2,8,7,8,
I l, 1 4
18

§ilW

BI2

---_.-+

SW4

,--

~

~'-

~-~

J35

J36
41
41

.J.

51

..AUlC.l

~

..ll I~~'
---Jl-iRSS

CSPITI

r--

U~CS

pu~~Mi~{!CK
R~SETlOC

eLK8

4;,RESET

4

CLK

t'----

it-~11m

J.-

1L-

3

RWL DC

RESETlOC
t-+l~rtJlll'ERI)

elK8

Oll!~~~~m ~[1iilliCTifl
PIRQ/PCS
PI ACK/PC6
T I ACK/PC7

4601oTACK
4J

H-Jc~~ET

-.L

Fit~~:Y=;+fe:B=

ll\,
fHN.C.

j

-----<

GND

12

+sv

GND

+5V
__

~_

~

I

~

So

20

H~AD6

6

HEAD7

70

18

.J!J~'4l

17

18

0

18

110

HEADI~

IS

"!!B!1J_I_ _
I '--£l

14

_ HEAD1~2_~1~2-£l

13

I
I

..

~:~

I

pao
pal
PB2

CHD~

I

----------'
nlH-1+ 1 - - - -

~~IlI&lU'-_ __

PB3t-""'~-~

!!CllI

~
.

121
13
13
13

I I

~

PB4 ~'----.
PBS

HI
H2
Hl
H4

~~

t-'-C!----l:u;..(lJIlJL.~

-4lliJ.L--

Pco~~~~L-------~--.

II
I !i

PCI ~H~=-TI N/PC2 ~~~LlL_
TOUT/PCl Kc~~~-----,
OIlAREO/PC4 ~'--'IIlJiOll.PIRO/PCS f--'<-!~~~
PIACK/PC6 ~'--!~~
T I ACK/PC7

13
I I

GND

I

42

I

GND

I

!

II

___ -----l

II

~

'6

EDCERR
~~"DrT
>--Ll!.!l.LL!-_ _ _ _ _

--

""""-'----------- ----

-----

---

----~- --------

-- - - -

-----

----

1",

-~?
~~

1

1_1

1

2
13" S § !
R~"·u~
13

1J

21

HEADS

~

3
3
2,18

I, J, I 4, 18

40

PH7

45

.-!LJ::~.

PUllDTA

2~

~J

.ou

41

22

HEAD4

pa6,......,~----'"

CSPIT2

T IN/PC2

ibN. C.

~J

PA2
PAl

PA7
AlQCJL ___ ------ll.

~~

PCO
PCI

'!;-~o~

PAl HE __
PAOm:---'lJ
"~~_J
P~

~~~?~~~=~~-~~~

J2

AlDeo
DC2
AlDCl

5-

I.~

lOCS

2

1,4

2l

"!!UJtL_l.tJ

H~AD9

68'2}OPLCC

682JOPLCC

I
10
13

24

20

H~A02

B1fW:Q!;--

'."." I

'0

HEADI

I--

tn-JUC-

41

WOOL OW

~-------L_-+- SYS6BK/CPU-40
A

--==r--------

._JL___________~

c

FORCE
COMPUTE RS

PiTs

REv.,1

;~~r,:1J
SHEETS

_ _~

A

B

D

----.C.

VIRQ":7J

r

--dAiOOt§ ~~

J65

HBCT244

;... :y,..

YO.

OEBur~

I RaVIIEII: 7]

'.12

~ii'

~

R

Y!

ICLRVIIE

I ,....IL

-{>-

TP

V.

~JJ
_..
112-1/0

iii

L--

Y7

•

L-___

_

2

.0

.=~+t
____++ ____________. __
'r

10

.0
2,10, II
2.10, II
2.10.11

.'--'''--1+

~

11

I

1___

VIii

21

1/0-41
1/0 .... 5

I/O_II
I/O-II
1/0-20

It-_---'!~~~~I/O-Zl

153

rsr---~
IIC!

~.ln

-=--=---'i=l~~~~.:..!----1f-_+}.__I"L--~~~~: ~g:~~

-++++--IlL.jI/o-U

~

§

10
12
t

..

!i~ifr~~-=~----~t-------·---

~

au

1.2.

I

'. ll. I 4. II
I

2
12
12

12
12

R=:Im&
DJ.Iftl.UI..--

L
L
L

L
L

,:1

...D.tACIU'lIt....CJ 10.12

1'O~
c. g I-HI-~~~'"

~..M.u:A.L_

t
T

'"0
LJ

'.12

1'1

Q,

~"""-I-H:-1A4 -l>1---.-----!!LLoL-+-H-........Jf!.--I: ~g:~;

ICLIV.IIE

r=
L.....

LL..

lL.

1'7

BRTOVI 0: J1

1/0-45
1/0-44

1/0-21

4

A7

DDTn....

f-M--lil
l~~: ~

1/0-28

..IB.E.Y.l..

~:

::

-

IR TD~t.

51
50
U

... . . --.. . --...,H",...------------i---------j~----~1':-'{f(-;~~~j~:~g:~; :~g::~

I

A3 -{>- Y3
A4
1'.

11.12

IloVDl
IRoVO~
!loy05

C---.

I/O-50

t==~~~~.==l~=1:~g:~:

..BIlfu.

YO

:~ ~~

.Jillj;J

IRQW1_
lRoVo2

I/o_U

I/O-XTll
: }g:~;
.-----.l~kiJ!~-~I/O-TCLKIII I/O_52
_ _ --'~!!&_-_!+_l1/0-22
I/O_51

.~

AD

.

1/0.... 2
1/0.... 1
I/O.....
I/O-51

0'111£10: Jll

LL....
LL....

:~g::; I/O~'~~!: lL...::g~~

.....IlIJlU

OlOCI 0: 7]

..l'----

1.::1:::::

ggfTO

:~g:::!

-----!~1/0-13

_ DLDC7--

2.4. t. 7.
I.H.17

1/0-7
I/O-I

------'1'-/1/0-14
1/0-15

-~ __-~

AlIAII: J. 1

I

..YE.Ct£Jl

OVECT! 0: 71

:}g~:,..-----

t-~wtt::::;::====:jtjI/O-1I
1/0-12

...

VECTEM

:~::~

l~::~°

I r;:--

-+-_ _--...JI

J75

HBCT2H

m:: :~g:::;~~~~~~~~jll~~

'J r-----____ -DI Del

2.11.11

vcc~;

~0fh:l
La.:
1/0_1: }g:m J-.lL
1/0-2

co

~~

YlI

10

IIPn'T

I ' . . ~ -'~ I~~'
-~-

1'2

"'f!¥~---!-HA4

2.11

RESElCOf

C

2.13. I'

,.
~

ANYBR

3

CJ

1

+~v

lmd'

! I

III

~H
II

J66

PALl6LB-f'LCC

~~~~E~II'I
~
~----------~--~------~---~~~.~f_---~--~-=--:---~---.--_.=.-===-_-~_.=_=~~-_-_-_~_-_~_=_~-~-~--~----~----------·----=--~---~-----------~~-~i~ 1~~.2
~---~

D-~----------

~__ . ____ =_

------ ._-\-++._-----------_._._-------_.. _--

I II

___._ ___

818

A-.

_. ____

_

._-----'

~riInft~

c;;,J:t---ill'l.
'

~ c#--.....1ill
~~--ARlI.Elt
B

T---------·--·-··
____

SYS68K/CPU-40

REV.

2

1

___--- L__

C ________

1

FORCE
COMPUTERS

ARB I TER I NTERRUPTER

:~c!Tl:
SHUTS

-\-------------------A----------=r~

__--=-===--=-]~==~=__=~=~____=~__C ---==~=-__==_~-_~~=~_

B

J37

74nH
<>

O£A
OEB

•
2."
2.11

AO

z

u

I!

!m~.._

2.11

•

--i--·--lAK.D.IIl.B..Lc ·

2.11
12

._=~~..

c:::>..kl.KiIIP.--

.

2

___ _

[l

_____ _
_

___

._

c:::>JillIViJ

I

I I1
3

I

=

~
!:.L:illlll: -.-..

~:~

~--

I

" , '

_ _ __ _

m

...

I

__'if

'''-

0

_._lIfliI

-'."

-,---.-.-

.

_

----

1_._ ._..

"''''

-_

....

_--

---,

---, i

U

----.------

C>wu

-~

I

I
I

4

-~>

I

I

I

!

I

iI ,:

I!

§
M~II~_

ASVIIE
--- S

-:--~ -

..

i

12
12
12

!

3
1

I '
! I
. I

>-

~

III

I

iI

I

I

I
II

~

l1E'llILcJ.

-_.-.

_ _ _ ~------1_

2.11
2.11
2.18
2.11

i
I

CJ •

lEO.

1 ;'..

-

---0

-

I

121
I i

12

_____ ._

I

!

- _-.:iiuf.L: :::.J~&_.-'
DTRAI 0: 311

.---

..

I

DTRAI 0: 31)

DTRAI 0: 31)

2,1 B

I

31

J7

J9

74F245

~

14fH5

~

lit• •l!

M
M

M
M

AI

A2

U

A4
AS

AI

A7

~

A4
A5

AI

A7

1

~.--~

in!! gili ·

_..D.VME.2L-1..L 12

u 3g1
115
II
B7 .11

DYII£2l

1111111::
F

IJ

84

~~
g~~Ji

il1:;85

AI

A7

-----

I
I
I

,

DVIIEI 0: 31)

!

3

I

AI
At
A
O.
AJ
A4
A5

I

4

I
I

21

DVllEl 0: 31 )

~12

i

!

I

II

~

I

41
i

Ie-

, __., ___ •

A

-=--~-----.=I-_==~,'~~=~_=_~:='-IL_=----·' -'''-''-~---·-L~-=====--=~-C-'-----'--·--- CO~~mRS ~:SA~:RK~~~U_~~: ;,:~ ~ ~
_.~ ... ____. _ _ _

II'

SHEET':'--l

--'--A

-----~----T·-------·

e.15

'.15

---=r=.

C

-~

0

YDP2e[ I: 321
DVYE[ 0: 311

DVIIE[ 0: 311

DYIIE[ 0: 311

1.11
II

---·-------8-·----- ---.-----=J=---===~

I

"YIlEt 1: 311

I

"VlIEt I: 311

"YIlEt I: 311

IIDP2At I: 321
BAYllEt 0: 31

I

•
•
•
I
I

I
I

10
I

10

-==--==---~l

)~~~ ~~,~-c~:~!'-I"
---1
., " Ll~v l
fh------------

II

lA~B2

AJ

.

2

i:~~::~ ~I

10
10

L:)--DlACKYJIE.
'.10

10

10
10

0"

.. ,,'

G-'ll-

810 I N3_

JI

IAJ(O

AIIYIlEO_ _ _ _ _ __

oMy~

[3-B17

"IIYIlE1

10

C)--AIM'EL-----£I A2l

Dell
c¥1 2

oM-------MD,_P~2A~7__

oJ!

o£.L--lIllfl~

"VilE 25,

sM. __ AVIIEZ6
_.

r#--~

olI ______"-VIlE27

oM-

UDPUR

~.::::::

"VllElS

1

121

UDPZCI!

\1

=r== I
RESETV~-=--l-, I

~

olli-~

BERRYIIE

oJ!L--1~
olli-...... ~

'

114

oJ!!-

+

~lil

oill-----

Al'

~

I

I

I

II
AI_~

t

o-A1L_

~ ___.__ -J]tqY.!!ll...J
IH(
oliL---

-- 91!IILj

o-llL'-'l

!~

~
+SV

I RQYIIEI I : 71

JI.lj]

I

I
oill---~
(#_2_ _ ._._~

W.1.L~_Illi!!£.L

uny:JD

3\

0 821
0. 22

[3ll.L----~1I ,

~L...__

oll--..JIIlfliL-.-~

!3J4_..~i
o-!~-

l

---

slli--i~

A25

~_

+

OCI

o-ill--~-

::-=: l=lJI

<5

~~

4

..III

etM--JmUAL

t

Ja

,3

0" 5

__ .-----£)"21
OA22

~UT

-

;u-.:-:~:::

oll----

~

Oil

C14

0.1.

10

UftD

...

O~!.L...i.YSFL Y!!L_

III

o-J-AKYliL~tL-1 ~
r::=rJAKlll-- -----£J 410
r-"..

WPU2

('::cAl

011

r#-1~

I

~--1~

--£) Ale

oA2

~----'l'lIIil.L

~
~"-"".
"'''~-----'''''''---

<5

- .----£l AI&

C)-AllIIL- __

oR---oll---. JIJlllE1n._

#--VI_ . . ~
#_ ..___ .D'lIIEli

11'1

_-----£I AI 4

10

oM--..---1ID1'W

oM·--..JID.P2.A.L,

0"--'' ' :: ~ II

o-lli--1 ~
-------fl'"
o-JI.llYIIE-.-----------£) AI 2
ooJI'lI<"'''' ----£J'"

WJ- ... ----.DYIIEL-

1I11

a"---j;;

omD<--

I--

P2

I

----.oJ

!#-J(;JJlL:=J
~~

10

3j

YIIEZ

1

I '

~

I:
AI . . . "

o-ill--o-ill--

r¥"-------~""_'"__I

&ill----.~~-

[3-ill-- ____ A

~l;

II

II
1111

I II

oAl6

MOP'AU

oA27

MOP

oM!-

Uppa2!!

o-!lL--"1lf.illL __

I
sID---~1

oID--o.JJ~!
Din

DVIILlI

.. >~

14
I
SYS68K/CPU-40

REV.

2

.;

-

.... .

.

- - - - -------~--------

---"--_.

___--~---_--a=-=-'---··----·~::--·-~I:::::=~=-~--=--_-_------t··-----------~-,·-j CO~~~~~RS I

VUE CONNECTORs

~ili:~!~J

__

_~ ~=--==~

l, 4

___

A___~_ _ _ _

=r

c

B

-

JI£&A

:?;:::::;::. . . --~::- -----------,---'·i::: ,:-==::--~--=-::-:-'::-:=--~~=:--,~-------,-----:
--__ '''''-~-''----''----~---

1,17

:::~

1,2,17

~=--=-~~:---=-'-'-----

..:;~
I:;

r:::::>~~--£lAI

aURSI

OAt

etL--1CtllL..-

c::J-~----ElA4

014

DCPU2

c::r-JICllIU---£J U

DIS

~

I

sRi

I

II
I

i

~Il
31

II

C~Ul..DJL-~-£l Aft

.
..

o-~
~ __ --£]AIO

II

t

s-ill

I

aM
~~--ElAI4

0-'1--0..1.'-

oJJ,

DCPU6
DCPU7

-t

£1110

oJ1L

Dcpue

slli---~

1

OilS

ill!!!

Ollt

DCPUll

I

16

o-lli-~

o.J.lL--~

~--

::::'

,-,121

ACPU4

I

UV4---{!IU"'J---£l A21

~

ACPU8

c:r-CUHll.O......,--O~2l
AU

11

I

11
II
41

Q---CI..KHllL...--o m

s!h-q

16

C",>,..kl.lIIJlL.----f) A27
~8

o 128

18

C~--oA21

0128

~i
GND

1,2, l, 14, 17

1,',7,8, I, 14
1,2
1,17
1,17
1,17

0-&-~A2

I

oR

~

1

t

ACPU20 .

DCPU2S

o-ll-L

DCPU28

I

OCI'

DCPU2t

1

0 tl7

DCPUJI!.

I

~!.L_

DCPUll

~CII

'
l

;.

. "I"" O..

o-ID--..m.1l1L

C20

ACPU.}

!:¥ll---~
o~u-~-­

s-ill--

ACPU!I

o-Q.i._--~
OC2S

ACPUI J

sill--~O-'IL,- ACPUU,
o-ill-,_-~PUlj-­
~_~21

--fJ ClO

ACPUt 0: Jl)

ALry"

----£l14

GAl

SIZ,CPU

ACPUO

--£l IS
---'--£l"

ACPU)

--£l87

I

---..AClJUi----£l 18

I

U

jill

1

OI!lJ

I

I

o-A1Li

I

TEACPiJ

OA2J

I

'III~A I
I
II I! III-~~ eYli
~-+

I

PU

1

---

.

,A25

ol-lL...,

~

--.l.&B.Q.L---£J A27

~A2t

II I II
III I

C2

C5

C.

on

sll-

I

14

GkL

121

I

II

I II I
I II

~

0..1.

oJ1L
Till CPU
r:tID-.-l!llifU

~III

0120

I

SCCPU;-

I

G I21

SCCP~

0122

TTOCPU

0123

TCICPU

4,12,14,
15,11

[#.1

Ii

!

I

I

3i

I
-.-l

--'

I

~~V

~-----ffillJ""""
fRilll~5Y

I

'NO

ACPUI 0: 31 :

~-=-=~===--=====:~==~~;:~-=:-;. -~._ . . =-==~·:~i~jJ

1,17

3, I 4, I 7

'---~'----'-'-'-'---B--"------'---"-----.-------'-'---'----~--",--.
---1.-__

, -_ _ _ . _ _ _ _ " _ _

~ _ _ _.J___________ J:;____ ,__,

! I
I '

14
I !

r-"-S-Y-S_6-_8'=K=/=C_-P_U=_~.4-0.-~--_RE~V'~2l.
I, COMPUTERS
FORCE I
;~~\~l
_
, SH~
' - "7.O
... -;o.=
..

A

1

I
I

~5V

TOO

~

II

CII

#L-

G-~~' __..--J

01Z8

I

l,I7

1

r:tlli

~- ~~ . - ...~'" I

~

'I I

II

I
I

~----£J112
~~--D.ll

DAti

:,17

(#

>JUL--f]111

olli---,-llilllL

i

,~CPUI,

o til

Uil7

+5Y

t---£J

.-..AC.fIIa---£J II 0
DCPU24

0

Oil

I'U27

CID

,
I
I
I!

.--.-ACfl/l.1

r

DCPU2J..,

o-Cll

U:17

rei

[

AC.PUl.L.._, -----£]

'~i~---~~:~

GNP

ACPUt 0: Jl J

~::==.::--=::I
1

810
GND

on-J
.2

PIUO

A
P.oL.a '

DCPU5

1:::

ri

+5Y

oJ!-----.J!~

I

c::>---'I..l.lDL--El All

r~ . . . ]1

4,14
1,17

rr--

~-£J'"

elli---~

~-----£JAI2

1&

II

I,

I

sillII

D,'" I

~'--f)Al

~---£lAl

~I
===;llil

------~l

DCPUt 0::

o

.

'---D-CP-U-(0-:3-I-J

Pllt

I

III ~

r:::::>-D'llLL-~-- ~-,----,-,---

1, 2, 3,

12

__.It, _~, __ , ____.____ '_._~_(

RAM CONNECTORs

J

_

-=--=--==~=~ =-A-=-=-===--=~~-:r=-------B------··-·--··~~:=r-==
_

~~:;

..;~

. I"l,.,,...

..,.

. . . ._

I""l

.....

N

..

CIa
......
_Cft
_

......m

N

___

C'oIN_1""l

N.o

................
N

mlil~

....

1"'11")"'"

..

._

.. .. ..,.

NN

..

.:J

eo

_

..

....

•

..........

........

U")

_eClC"4_

N N

oC

~:;

..:

::

~~~

..;

'"'
..:

Nr--";

.-

iUUI~
CI

~,,;

-

"'..;
,.:

~~

..... ,..,..

.........

...

....

~

....

c
..;~

~

,,}r-r--.

N.o

....;

,...)NNNNNN

....

_

.............N

......

.. ......

--,-,---rrTl I

;;;

I

NNNNN

Iii

-<

u

CI

0

'"

r-

~

I

I

III

[#-!l!I-!!Q..

~U-ffi!.D-l-.

[ ;L_:=_
III
JI
86 I

-.J

R597

2

G-~ .. llE.SllC..oL

~

s!!Q._..~GAO

B10
G
GIll

c¥J.L_~GA2

Ci

AFGAI

sill:

AfGAl

Cll

o-!U-____A_C~
WlL---...!C.I'.U.z..

Ml'lLL

~.L.~

-~

I

..

Of GAl

OfGA6

Clf

OfGA8

s-ill+

Of GAIl I
Of GAl l

C17

3

.... v. u • •

~

I

GA21

~ __ -..ACfll

Gill.

IPIOIIOO

.1I00l0W

~~V
~5"}-I>UV
0 Ali
oAlO

4

~~.~----A----'--.

Wll-

"'W t
slli--.---.ACf
slli-----..ACI'..IJ.JL..

0'"

I
IU==::::

~

r:l.lle
_ .. = L ~.
L;T~5V
829

IPUIIDO

BlO RIICIIOO

!I

r~JI

Of GAl

AI

GNO

B:~

#L.J2f.ill......A11

......!!.FGA21

r¥llC24

DfGAn

~

OFGA26
OFGA28

C26

C27

a
cn

=F

5V

___

#~

OfGH

FC2fGA
012 SI OFGA

G913

I

A14

orGA9

14

A15

Of GAl 0

I'

AI6

orCAl

G

..

ASIIOO

III
I

I

~

Of GAl.
OFGA15

A19

OfGA17

s!ll-

A20

OrGA19

~5V

A21

OfGA20

A1

OfGA22

slll--HAl HGA

A2l

OfGAH

~5V

OFGA25_

021

WL-ltr-·;.,~

III'I I
I

o Cl 0

G v' ~

".

G v' •

"I

BERilFGA

~5V

G vn

~5V

sill-

~fGA29

~5V

G~DfG"lO

s-I-~n

J __

I

0"'-

GND

ACKOUTII

,,·c·
OFGAlI

-£l A29

I ,

II
31

oB2t

on'-~"

4,13

:!:12_V~ 4,6,7,12,15,18

~5V
I ACKSI!

I

L'' '-l

___c

I

,i

GNO
CIHHIIOD

141

CJ

SYS6BK /CPU-40.

._-=---=r

II
I !

rl

5Y

IllS

-_._____--'l ___

I

! I
I I

rffi1};>o-sv

+12VR

~GA27

A28

I

5VSTOOY --c::J 4,12,1 J, 15,18

OSAI FGA

I

I

~

II

el2

w1J

G-

~

II

6,7,12,15,18

fiiill}--i>+SY

Cl1

'I

I

121

SIZIFGA.

A18

G

#-SV

I
I

I

.... ,

.. r¥L--

! II

s-ill-G

II

C21

I

oA6

-fJA1
-fJ A8

OfGA7

I
II

Of GAlS
!!fGAI8

I

1111

GAil

II

ACPU22

~~.tI'.IJ.

I

G C18
ClI
C20

::~~-=-~

'

LOC6

At

~~Qg.-

~~A5

Cll

~

; ~-II

Al ClOC5

G

[#1.

C15

[#9-

l·

r#--: £.8s.EILnC..._

o-!L~Q!.

BGACk

s-ill- .-.

~~ A2 OlOC.

_

I

11111

AI

l#---

L~-i>+5V

--fJ "7
GNO
----oA9

,..,61

~on
i Wi

/

L

2

15

I

~

!I

+5V
PII4
--4] AI

~

...... 1""")10_

.

.......

.:;

.:;

__

---- . . . -"""''''''f''-.
-.... _.........
------ --1-'.- _-

r- _ _ _ _ "'"" .-_t-.r'l • __ ..
_""'NN""'_N_ ~NNNN

fORCE
COMPUTERS

EAGL E CONNE CTORs
-

~~---

-

,j

REV. :

r

SHEET I
FRDII 18
SHEETS

- - - - -- ---

--

J

.A

T

---,B~______-..L

IIDPZCII: :SZl

UOl'2Cll: 321

I•

1I0PlAll: JZ1

o

~---

C

IIDP2AII: 321

1I0P2Cll: 321
IIDPUII: 321

_______--=-:L.A,JZV...IIE",-CJ

',12
',1 Z

" 7, 12, 14, 111

.-----.~nnL.cJ .,12,13,1.,18

~
~"

i

t1

%VII:

CJ •. "

7. 12, 14, 111

'"

8"

C~

21

2

II

[3H_MO.UCJ

3

3

I

~

II

WDP2CJI

,

I14

GNO

--..-·---------A---- ·---··-----·-l

s

---r -

1

41

C

FORCE
COMPUTERS

SYS68K/CPU-40

REV.

2

EAGLE P2 CONNECTOR

SHEET

I~

fROII "
SH£[TS

IH,'d;'~~~~ -rf~~-.~~i~~~;;:~~--= .--r_----:::;;1 ~~~L' IIIP
----= ._.-. . =:~

A

1
1.2

0

M

1.2.4.

~--55

9.1 l. 1 4

~UO."ECl
",'
~e~K1..i.O-EJ

+5V~IIJ

_

••••_ _ .

+5V
+5V
.5Y
.5V
+5V

J58
HF244

_ _ : _ •• _

RaJ

0

, ,,,.,,

"p

Q4-F /4

J
1J

1

1J
1J
1J
1J

'

2

21
~~o~~:

+5V

GND
5V

r J CLkLDROU

13
1J
13
1J

13
1J

R5J.

I------*,-=---~41

0

5V

H
GND

r J HALTLED

J!OO.ll.__

3

~

--~

----

JSJ
DO"'
" "

- := ·11

-

3

J499

1.2
2
6: 9
2••
9

a

1.2.l.~

GND

;~

1 D. 1 J. 1 4, 1 7

4

74FH

A __

~=--====T

-=====~~~8

===_:==-~-:=:I------

rrrrr

I

~--------~

.5V~-

I

___
C__________
-------------

I

I

FORCE
1COMPUTERS

SYS6BK/CPU-40

141
REV.'
SHEET 16

CLOCK GENERATION

I ~:~T~8

J
j

i

I

I 'r I 'r 'z 'I

[ It :0 lOd:lY

t

( I r :0 lOd:lO

\: I 'Z 'I

I
!

i

I

!

I

lui

1

i
!

Ii .
I

!

I

H
i

I

[11::Ol:101Y

5 'i 'l 'g', 't
t 1 '5

[ II: :0 1'f9JO

tI

'r

I

!
!

's 'l ','t 'z

'~ 'r 'z

I

I, !I

ieol
i

i

! I

! I
! I

i
i

I
I

! I

H
I
1

I

I

I I

i !

i

Ii

i

i I

I I

1<1
I
I

I

i
i

II
---':!-..:_-..:_-

o
N

! I
I
I

\J

_~_~

_________________

=-T-==_~_-_==~_~_=_=~B-------==:==-=r

tSV

~ _______________ J)_____________________ __(

+SY

tSV
~AlRA.L _ _ _ _
___ _AIRAJ.. _____ _

t5V

t5V

t5V

2.2,2.111100
2.10
2.2.1100
2.10
2.10
2.10

2.9.10

___

2.10

.AI.B.AL~

_____

: I

--=-=-~
___
________ ...1iB
__ ATRA1.L____ _

2.10

2.
I~
2.11
2.11
2.11

•

tSY

+SY

+sv

+5V

+5V

+5V

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

t5V

tSV

tSV

tSV

+5V

t5V

t5V

+5V

+sv

t5Y

t5V

+5V

+sv

+sv

+sv

t5V

1111111111111111
GND

GND

GND

GND

t5V

tSV

tSV

+5V

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

t5V

tSV

tSV

t5V

tSV

t5V

+SY

tSV

+sv

+5V

+5V

I

;-sv

----~--

_____JHlI.ll_
DTRA6

_____JURAL_

_=:JillL____--»IBAl.L
--==illft.t-

----

Mii-------

==uR

_.nJWQDTRA31

:5
:6

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

t5V

+5V

+sv

+sv

t5V

tSV

tSV

tSV

tSV

+sv

+sv

+sv

+5V

+5V

j•

H

I1II~IIIIIIIIIII
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

+SY

+sv

tSY

+5V

t5Y

t5V

tSV

tSV

tSV

t5V

tSV

+sv

+sv

+sv

+sv

+sv

GND

GND

~V

~Y

GND

~Y

GND

~V

GND

~Y

GND

GND

~V

GND

~v

GND

!

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

:9

r-

....
<:>

C:ND

-c

::
N

'"
'"

GND

1,

1 Cl

' '" ,

-;j_

---1---1-

_

U'

1
I

GND

II

GND

-

-

---

7.12.1'.IS

CJ·6
6,7,12,1',\5
~

SVSTPBY

r---o

•

•

II4

CJ '. n ....... "

---

c

~

co

SYS68K/CPU-40
------------

___.__Ji_

1

+

N

}.------~=-==~~_==C---=__==-

3

+5V

1111111
,----",1--------,r--l---------------------"" ~4.
~_~.~~ ___ ------- _-- __ +12VI
- 12VIIE
1115
~
----=-~=-~~-=--=----~ L
-;r
, ""
_. -ClIS

4

------ -----

GND

tSV

-------

G---

: 10

GND

tSV

11101111111211,31,1.1,251126

--EJ

:7

GND

179180 181 182183 18.185186187 1aa1u "Cl 0511 0611 07110811 09
IIIIIIIIII~IIIII

GND
: 4

2

L3L.L5L6L7L8L91D1112131.15161718

DTRA3

------

..kSl.lJl_____ -

l:~: ~~14

-~-------

------

2'14.~
~: ~
illJ__===---

2.2.53..1144

tSV

1111111111111111

~-~--­
____ AlRAJ.Q_ _ _

2.2.44..144
---2.7
2.2.88 14 ~.~~: :_::===jB.L
2.4

2.1'

tSV

L5L6L9101112131.1516171a19101,L2

10.

2.10

2. B.

t5V

GND

~IltA2.L....

2.6

tSV

L7L819101112131.1s16171819LoL3L.

_--A1RAL6... __

_~ ________

2.10

2.14
2.14

t5V

1111111111111111

2.9.10

I

t5Y

L10111.1s16171a19LoL1L2L3L.LsL6

2.10
2.10
2.10
2.9.10

3

C

VIRQI I: 7J

2.9

2

_ _ -:----

FORCE
COMPUTERS

PULL UPs 2

REV.

2

-------

FROII

SHEET 18
18
SHEETS

APPENDIX TO THE HARDWARE USER'S MANUAL

SECTION 4

E.1 Circuit Schematics of DRM-O 1

E-3

SYS68K/CPU-40/41

FORCE COMPUTERS

This page was intentionally left blank

E-4

" A

B C D
8ClO! 0: 71
PClO! 0: 31
DCP! 00: 31 J

DCP! DO: 311

w

3

0

i ACP! 00: 31 J

I

PARIT

+SV

Pili

S1
S2

PUll

OAi

04

BURSJ

0

.--El
..... 12

DCPOO

,.,C2

DCPt.

2

03

RAMI,

OAl

..... 13

DCPOI

C3

DCPt 7

..... 84

nCP02

,.,C4

nCPtll

U

MCOOZ

OU

2

MCDOI

0 A5

3(

04

Mcnpn

0

r---£lCI

1111111111,
-=81

~ ...

~A3

~

~

+5V
r-£lCI

•

ACP"
ACP7~

........

~

ACP24

~

.15

nCPOl

..., ..

...... C5

DCP! I

~

..... 15

ACP2S

..... ce

~A5

~CPJJ~

DCP70

...,AI

IL

..... 11.

UPOO

..... A7

..... 17

DCPOS

C7

ncp"

OA7

IIEFPl

17

ACPO!

~

..... 11

DCPOI

nCI

DCP22

OAII

REscr

...,81

ACP21

at

nCP07

..... c.

£¥L--.

DCP21

~At

..... 11

ACPZ7

~C'

..... 810

ACP?8

~CIO

2

~IIO

B811

DCPOI

CIO
t----Br:1CII

812

nCPol

S-C12

,..,81l

DCPIO

Cil

ncP?"

~AIl

BI14

DCPtl

r:1C14

DCP27

r--:A14

DCP! Z

..... C15

DCPZR

AI5

B 81 • _JlCPt J

"CI.

nCP?g

CI7

DCP30

L-oAI7

...,CII

OCP31

815

..... 817

DCPI4

..... 811

DCPtS

~B1I

OAiD
DCP24

~AII

DCPZS

r:::1.-"12

t--;:

A16

OCI.

81

OCI.

ACPOS

0-1 22

lCPOI

.-.C22

ACP07

~A22

na2l

~

..... C23

ACPOI

r:::l.A21

...,824

ACPIO

ACPI!

~A24

..... 825

lCP!7

r:1C25

ACP13

..... 1.25

..... C2I

ACP!5

ACPIII

..... 121

lCP20

~830

",cn

ACPI 9

..... C2'

ACP2!

t---£lClO

I

~UI

tJ

..... 122

OPIUII

TEARII

..... 823

OP Ilil

0124

OPlll

TARAII

~125

IA80T

A21

0.\2.

III CPU

ClIO

DPOUU

)127

DPOUII

OUI

DPOllI

sID--llill

---L.

GND

DIU

t-----e

~AlO

llO

S

C2!

3

cn

~

~
~C2'

sill---<
sill-t-----aC21

t-----rJ ClO
-L-

GNO

GND

2

C20

DPIUU

ue

OA27

'
-120

~821

RAIiSl

2.3
2.3

OCI5

RESlO

A20

3
2

~C14

CA2RII

C21

ro828

~

OBI5

r:::l.AI,

ACP04

ACPt 7

C8REQ

..... AII

...,121

ACP!I

ACP.ll

...,814

OCI •

OUI

ACl'H_

..... 813
SICPO

OCI7

ACP02

B828

~

ACP30

0 817
OBII

...,120

B 827

ACPU

..... 812

081S

DUO

3

.,111
TSCPU

0

2.3.4
2
2
2

~CI

S I CPI

~CI'
..... C20

ACPO~

T811111

II

3

~C2

.....82
..,83

AI

GND

ClIO

PII2

~AI ~

'

cf
IT

I

II

ACP! 00: 31 J 2. 3. 4

,ACP! 00: 311

ClIO
2
3.5

J,5
3, •

3; •

4

4

3, S
3.5

3 ••
3.6

SYS68K/DRM-01

N"""'NN

A

B

C

FORCE
COMPUTERS

CONNECTOR

REV.

2

SHUT I
FROM •
SHUTS

A

c

B

I Ar.TA

n:I:UIII
•
:c :c :c :c :c

1i

~

WI ..

1.CL..II.IL

21iJ

r§

1I:J.Jl.l.-4J

T4

1:111:1
PI:LDI

PClD! 0: 31

~~h

i
I

~~+-I'--l!-:!~~-l13
~~~~~~~~14
-k~~~~~~~15

01
07
011

~-"--~II

~~!,---Il.IL.jI7

I----!'.......""-~III
~.......-!!Jo!...1!"-"""'"~I.

r---I--I-~~-+i--lll 0
I-"-"'--~III

I

~~

:2

i

nm

U
e~ f!~n

I.

I

....lJ.B.AS.

J8A

JIIB

74F112

74F112

74F112

74F112

L---

I I l- 'l.\d. 1L1l-~;-'---11 ::

~i

f4

III

[I . """

I---

R--ftIIi¥---

"

"

+SV
HRUY

[llf[V'

::

J98

J9A

+-

I'r ~~:.:.:-=::::::=-~

i~i~ I:IIIIIL·JI LTJII
74F112

Ll-+--I-I~~~"iI:;

::

1

' 1I

74F112
FIICAS

74F112

74F112

.YCI

SFDAI

'1B

c>

o

REFPl

1BEfEll

r

RHPI

..

S

o

_

J68

~

R

S

0

Q

'floUr

I
• III/CK
I/O I
12
13
14
15

II

R

17

la

Q

""'iTl"

:l~

~La

~
__

S

0

R
Q

II

~LI

PAl22Vl0

_

r.IIIRP

~~

,TAERY

J5

-_._-----

~J,4

REser

+SY

J
~

3

.ICI

SHOO

t--

aD

~

'1 I

REser

---.

4

'--'

~ lOB

~

55
~02

~

~ 1 01.

'---PA-l-16-l-=-e-

J6A

2

J2

c::::>--Billf---- ------

!

J..~!l!1 ,.,

I I I I

- - - - - - - 1 - - - - -1 - 1

I---.

.~

III'

~----~-~---

+5V

•

;r.:;

ElaUU

IIIKICAS"1
:stell

c:::r-J..W.L.--

J7B

--'lAiISD

ENCAS I

I

~

J7A

SEllAS

J4

,::I~ §3Ib=~~:=--=--======-=-~======~~~f~=~~~~~~il
,3

KARlY

R[SCY

PO.U

.

RlRUIl

PAl20l8

BClD! 0: 71

~

RARUU

~~~H.--lI12
-IlI........L-.Jk.!.....j 11 3
L.-_ _--'

-t ~ ~ ~ ~-Bru.Q.

I

Rfk!

~~t-I1--~~H--l12

~iii~

i
!

___~~H-lIO

~~-!rl'--l!-:!~H-l11

53

~

j

J3

01
02
03
04
05

a

~
llllU

+SV

~

i

D

1/0-2
1]0:)
I/O 4
1/0:5

nAI FN

nAIFN

IIill!

~
II CA2RII

a

::tiib:g
....lAIWI..

I/O I

..l.AB.I!L-c:J

1/0-7

I/o-a

1/0-'
1/010

TAtRIl

~

I

.

14

112

II.H.l.!-

~~~Tf 90fE:

~

SYS68K/DRM-Ol

REV.

2

1,3,4

/

B

c

FORCE
COMPUTERS

DRAM lOGIC

SHUT 2
rROY •
SHEETS

~

r

~

2
2
2,4

!~m

lfft:
lDLAl

!~;

I

'ini
1\

Ig
-543

,

!~~ I[ j

t: iii

.. ~ ..w'

III

L-.-

c

B

A

"'-''-

I
~

~

rI

)!

~
I

PH
~

I

DRill 00: 311

DRill 00: 311

--1101

10

~17---P.'-i: ~
!+-----'~

...

[VEil

13

!-1--Jl.I'-Gll

:~

106

_

-

AO
AI

2

A2
A3
At
AS

m
m
m

AI
A7

,

II I

~

'0--

t
I'

I

II
12

S7

I

14

[V£ll~

II

1

-£]'

d

DPIlI!

CJ

1,6

13
15

ODD~

74F2BO

m

I
I

.
I

,

-543

1,6

J17

~;

HABg
HABib
HABS:

CJ

74F2BO

16
17
18

~

~

DPILl

'--------'

~;

I[ j

L:=
~

02

ODD~

:~

DPOL

..1'

!k~b

S6
,1

~-~~14

L.. _.-.,

!k~\ zi~l

S.6

J16

1--.

10

J 13

o

m
m
m
m
m
m
m

2

J18

~--~-i:~

I

~--~-j12

S8
[V[II~

-Ell [32

DP I UI!

CJ

9
S,I 02

DP I uu

n "5

I, 5

~--~-i13

~---!-+-j14
~--~-iIS
~---!;--i

ODD~

16

~----+-j17
-----~-iIB

.....------,

II! I !krli

'iUI
AO

AI
A2
A3
A4
A5

3

AI
A7

~;

i~i I[ j

'--------'

74F2BO

J19

~

L_ i_ _

_

-:--

us

lin

tJ.

+sw

....v

iI

DRY2:

DRII'I
DRII'·
-_ .. -

I.
I

~:::

L--

:r-

~;

....:Ml.

10
II
12

13
14
IS
It
17
IB

[VEN~

ODD~

3

74F280

LACTA

[I

I

Ikrli

'i~ !~i
AO

AI

A2

4

A3
At
A5

',:.

A.
A7

DCP( 00: 31 )

-=llJ..

L--

L-~

L--

L--~

'0--

II

1111

1_'
ill~
: ilb ~

IIII

'"

/

',2

•

'1
INO:'~TJ~ 90 I ~A~~
r

ACP[ 00: 31 )

A

I..

1,2
1
1
1
1

S10

4

GIlD

I, •
1,5
1,5

1,2,4

..IAE.I.Il

B

c

FORCE
COMPUTERS

SYS6BK/DRM-01
DATA TRANSC, PARITY

REV,

2

SH£ET J

nOlle

SIt[ETS

r-

_.B__

A

c

D

IUiUU
J21
74F241
AD~

r-________________________________________________

t---l-Q0£2

~
'------,

AO

+5Y

GND

74F241

~

ID

2

5,'

AI
At
Al
A4
AS
AI
A7

J22

Uft.~

~A~R~M(~O~O~:1~2~1

AO
AI
At
Al
A4
AS
AI
A7

llll!
'r7

3

Iii
ARCIB

~

•
II nn
I

II

2

.20 10

+5V

eND

"

ARMOB

3

I, 2, 3

3

ACP( DO: JI 1

~
~OE2
I
__..JIDUIJjAO

U

J24

f--

2,3

~------~

---- - -

ADDSL

- --

---

,.
+

:~

AI

113

A4
AS
AI
A7

YO
YI
Y2
Yl
Y4
YS

.Jl.D.RIIU
RORI

H:mB±

M
~_

::ImCg

Y'~---~~--~W
Y7~----~~----L~

4

4
+5V

GND

SYS68K jDRM-01
~

A

r=----------B--

C

FORCE
COMPUTERS

ADDRESS UUX

REV. 2

c

B
DRill 00: 31)

J, I

DRill 00: JI)

J2&

J25

AD
AI
A2
AJ
A4

DRill 00: 31)

OO~
Ol~

IlASE

R
CAS A
4 SE

CAS 24

,--0;;;;;-:0-----:;",1. 0
I'-'~~--"+-IA II
II:
t---'IlI1IILL-.L1AI2
L..-_ _--'

1.10
All

II:

2

AI2

DRAII411XI

DRill 00: 311

J27

DO~~
DI~

DRAII411XI

BfHHt

I

J21

DO~
DII-LJ

01

US
I.I

AI
AID
All
1.12

R
CAS A
4 sE
II:

II:

01

I

01

A4
1.5

CAS

IDSUU

CAS

CAS

II:

IE

II:

<=1 , ,3
<=I 1,3

US J

C: 24

2

~~--,AI2

DRAII411XI

DRAII411XI

USUU_JJ3
1.0
AI
A2
AJ
A4
1.5
AI
A7

AI
AI

3

RDSUU

I

~---

DRAII411XI

D

DO~

DI

AI
1.7
AI
AI
AID
All

lAS

4

2

AD
AI
1.2
AJ

DRII25

"~

CAS

HI

JJ2

lAS J

2

IIn!:1I1I

II:

JJI

01

D

r--;=;-:-----:;",AI 0
~~~~-IAII

"""'-"""'----"'-1 AU

OO~

AD
AI

011-LJ

AJ
A4
A5
AI
A7
AI
At
AID
All
1.12

1.0

00 25

AI
A2
AJ
A4
AS

DRII21

A2

IlAS~

CAS~

CAS

II:~

II:

L..-_ _--'

DIAII411XI

JJ8

JJ5

Llb-=~=== DRAII~IIXI

01

AI
A7
AI
AI

lIAS
CAS

AID
All
AU

IDSUU

II:

A2

AJ
A4
1.5

AI
A7

AI

"~

01

I

lIAS

J

AD
AI
A2
AJ
A4
AS

AI
A7
AI

CAS

• At

AI

,1.10
I
2

II:

Z

~00:121

1.1111 00: 12)

II:

4

2

RnSUU

3

_J42_

,,~'
01

DRAII411XI

OO~

I

01

US

I

B

-C]I,J

CAS
2

IDSUU

AID
.--=:-:~-~AII

t---IlI1IILL-.L1AI2

II:

'-----'
DRAII411XI

4

11.1.. 00: 121

SYS68K/DRU-Ol

A

-C]I,J

lAS

CAS

AID
II:
I
2
'--DUII411XI

RDSUU

L-

DRAII411XI

RAS

CAS

HO

J31
AD
AI

I

0lAII411XI

DRAII411XI

J38

"~
01

c

FORCE
COMPUTERS

UU UM BYTE

REV.

2

SHUT .5
'1011 •
SHEETS

c

8
3.5

DIIIIlOO: 311

0111/[00: 31 I

I'-I'--

~

I'--

'--

I'-

'--

t--

I'-I'-I'-I'--

t--

B

:-~

'--

c---

J43

J ..

~

AD
AI
U

'--

AJ

DO 25

I'-

'--

:--

,

t--

c---

I'--

lIAS 3

AI
A7
AI
At
AID
All
AU

:--

.0111/15

01W

CAS 124

t--

I'--

CASLI/

I'-

c--:--

t--

~

c---

I'--

•

IZ

~

I'-

RDSLL

ORAI/41/Xl
IASLII

:ASLI/

------

-

t--

I'-I'--

t--

I'--

2

!----'

........
'--'

t--

!----'

r--

----

~Al

~

:-;--

~

~

00 25
01

.DR1/14

-L.J

c---

~

L...-

~

US J
CAS

Z4

IASLI/
CASll/

c---

~

~

:--

~

'--

:--

~

l=i

~

•

Z

IDSLL

~

'--

'-'

AI
A3
A4
1.5
AI
A7
1.8
At
AID
All
1.12

i

.DRI/ll
I'--

DI..L-l

~

t--

~

c---

I'--

US

CAS

J

24

L...-

I'-

IASLIl
CASIII

c--

I'-I'--

:--

I'-

!--

c--

t--

r--

RDSII
•

DO 25

.DR1/13

t--

~

I'--

;--

t--

Dl..L-l

AI

lAS J

RASLI/

I'--

A7
A8
At
AID
All
AU

CAS Z4

CASLI/

I'--

~

l--

t--

.--

I'-

l--

~

IDSLL

•

2

ORAI/41/Xl

DO 25

.DR1/12

DIU
US l

RASLI/

CAS Z4

CASlI/

.~

IInSI

ORAI/41/Xl

l=i

I'-

2

I'--

AD
AI
AI
1.3
A4
AS
AI
1.7
AS
AI
AID
All
AU

DO 25

. DRill 0

-

'-'
'-'

:--

;--

'---'

DI..L-l
lAS J
CAS

24

~

'---'

HASLII
CASIII

!--

~

~

'-'

l--

I'-

!--

'-'

':::::::J:

JlDSll
•

2

AI
At

1.10
All
AU

DRAI/41/Xl

•

J50

HI
AD
AI
U
1.3
A4
1.5
AI
A7

DO U

.ORI/OI

DIU
lAS

J

CAS 24

RASHI
CASLI/

~

!--

~

;--

~

>----'

~

'-'

!--

RDSLL

•

2

AD
AI
AZ
AJ
A4
1.5

DO 125
01

DRII08

k-J

AI

US 3

RASll/

CAS 2f

CASlIL

.2

.....
.....

!-!--

'-'

~

'-'
'--'

RnSI

t--

r--

DO 25

DPOtI/

DI

1

DPILII

lAS

J

IASIIi

At

.....

~

1.7
AI
A,
AID
All
AU

J51
AD
AI

Al
A4
1.5
AI
1.7

~

;--

CAS 24

AI
At
AID
All
AU

!--

~

"--

•

2

CJ 1. J
CJ 1. J

CASlI'

2

RDSll

DRAII411Xl

ORAI/41/Xl

ORAI/41/Xl

DiD.sL1.

AD
AI
AZ
A3
A4
1.5
AI
1.7
AI
At
AID
All
AU

~----

HI
DO 25

AD
AI
1.2
1.3
A4
1.5

- ... ._----_.

----"--

'---'

'--- ~AO

:--

:--

J48

H5

DRAI/41/Xl
--~

J47
I'-I'--

A4
A5
AI
A7
AI
At
AID
All
AU

L...-

HASt 1/

0111/[ 00: 311

0111/[ 00: 31 I

AD
AI
A2
A3
A4
A5

D

ORAI/41/Xl
--_ ..

..

-

-----------

J54
J51

t--

r-r-I'-r-I'-I'--

r--

t

3

'---

:--

AD
Al

~

At

;-~

;--

ii;fJ ,
ARII12

1.3
A4
AS
AI
A7
AI
AI

AID
All
1.12

J52
DO 25
01

ARIIDD
ARIlDl

.DR1/07

k-J

liAS

3

RASLL

CAS

24

CASll

I

RDSLL

•

ORAI/4I/XI

8 mtL

- - -------- - - - - - --- -"--

--

-

1.3
A4
1.5

r-r--

'---

:--

~

'--

~

'-'--

~
~

~
~

~

~

c---

AD
AI
AZ
A3
A4

AI

A7

c--

AI
AI

'---

AID
All
AU

AI

AI
AI

4.5

ARII[ 00: 121

ARII[ 00: 121

DIU

AID
All
AU

DO 25

lAS
CAS

J
24

RASlL
CASLL
ROSLL

•

L...-

I'I'--

3

RASll

CAS

24

CASLL

r--

'-'-;--

~-

:--

I'--

:--

I'-

r--

'--

RDSll
•

2

AD
AI
AZ
1.3
A4
1.5
AI
A7
AI
AI

AID
All
AI Z

00 25
01

.L.-l

J
US
CAS

.DR1/05

24

• . 2.

RASLL
CASll
RDSLL

r-I'-r-r-I'-r--

' - - - ~AO

-

: - - ~Al

.-f-f--

~

I'-

~

1.2
1.3
A4
1.5
AI

AI
AID
All
AU

.L.-l

US 3

1.7
AI

ORI/04

DO 25
DI

CAS
•

HASll

24

CASll

2

RDSLL

3

ORAI/41/Xl

-------"----.~

DRI/03

Ol~

~

ORAI/41/Xl

~

'--

'-'
'-'

'-'--

'-'
'-'

:-:--

'--'

~

'--'

:--

'-'

~

2

ORAI/41/Xl

4

r--

ORAI/41/Xl

..

~--

J56

AS

:--

.DR1/06

RAS

A7

J55

I'-

00 ZS

At

ARII12

2

AD
AI

J53

AD
AI
AZ
A3
A4
1.5
AI
1.7
AI
AI

AID
All
1.12

DRI/02

DO 25
OIU

•
ARI/OO

~

~

'-'

!--

AD
AI
AZ
1.3
1.4
1.5
AI
1.7

~

AI
AI

ARII05

US

CAS
IE

J

RASLL

24

CASLL

2

RDSLL

J57

'-'
'-'
'-'

~

b

ORAI/41/Xl

AID
All
1.12

ORI/Ol

DO 25

US

CAS

3

RASll

24

CASLL
ROSLL

•

2

ARIlll1

ARIID2

OIU

I

ARlll
AIIIII?

ARII[ 00: 121

AD
AI
1.2
A3
A4
AS
AI
A7
AI
AI

AID
All
1.12
ORAI/41/Xl

ORAI/41/Xl

ARII[ 00: 121

J60

J58
ARI/OO

'--'

DRI/OO

00 25

'-'
........
'-'

DIU
US 3
24
CAS
•

2

r--

~

.IASll

"-'

CASLL-

I'I'--

RDSll

r--

~ ~AO

..--

~Al

At

~

!--

~
~

;-~

.1

1.3
A4
1.5

DO 25

OPOLL

1.3

01

1

OPILL

CJ I. J

3

RASLL

US

AI

1.7
1.8
AI
AID
All
1.12

CAS
•

i

24

CASII

2

RDSll

DRAI/411Xl

SYS68K/DRM-01
A

8

4

ARII[ 00: 121

C

FORCE
COMPUTERS

REV. 2

SHEET •

LM LL BYTE

~::T:

-~-

.. ---

-

--_.

1

A

c

I

B

D

/

BCLD[ 0: 71

T

CLKCY

A

DP I UU

B

RAMTP

C

PCLD[ 0: JJ

T

CLKRP

A

OPIUM

B

BURST

C

RASUU

T

CYC[ 00: 05]

A

OP I LM

B

PAR I T

C

RASUM

T

TSCPU

A

OPILL

B

I.ICOOO

C

RASLI.I

T

TARAI.I

A

DPOUU

B

I.ICDOI

C

RASLL

T

TEARI.I

A

OPOUM

B

I.IC002

C

ARI.I[ 00: I 2]

T

RARUU

A

OPOLI.I

B

POWRU

C

ROSUU

T

RARUM

A

OPOLL

B

TBI RI.I

C

ROSLL

T

RARLM

A

ACP[ 00: JI]

B

TAECP

C

CASUU

T

RARLL

A

DCP[ 00: JI]

B

REfPL

C

CASUM

T

AOOSL

A

SI CPO

B

WUUCL

C

CASLM

T

KI RAS

A

SI CPI

B

WUMCL

C

CASLL

T

SERAS

A

RDINV

B

WLMCL

C

KI CAS

A

RDBur

B

WLLCL

C

ENCAS

A

1.11 CPU

B

ELWUL

C

SECAS

A

I ABOT

B

KIREf

C

ARC02

A

RESCY

B

REf EN

C

ARCOS

A

RAI.ISL

B

ELRUU

C

2

3

4

ARC07

A

REfSL

B

ELRUM

C

ARC09

A

RAI.ISO

B

ELRLM

C

ARC11

A

RErSD

B

ELRLL

C

ARCI J

A

CBREN

B

BEREN

C

ARCIS

A

SEDAL

B

REser

C

ARCI7

A

TAREN

B

RESLO

C

ARC19

A

SHOO

B

GA2RM

C

ARC21

A

REfRQ

B

ARC2J

A

RHH

B

ARC2S

A

DALEN

B

ARROJ

A

ORM[ 00: Jl J

B

ARR04

A

OPGUU

B

ARR06

A

OPGUY

B

ARR08

A

OPGLI.I

B

ARR10

A

OPGLL

B

ARR12

A

RDLAT

B

ARR14

A

ARRI6

A

ARR18

A

ARR20

A

ARR22

A

ARR24

A

RDRUU

A

RDRLL

A

RDPUU

A

ROPLL

A

ARXNN

A

1

f--

2

f--

3

I--

4
I

ARX09

A

ARX10

A

LACTA

A

1

I

DATE
I NAME
INOV.I J. 90 I S. K.

J

A

8

SYS68K/DRU-Ol

REV.

2

I

I

C

FORCE
COMPUTERS

lAYOUT lEVEl

SHUT 7

FROII I

SHUTS

J

"

I

A

8

l e o

/

1

1
~

+~

~

co

-T

~

~

CI

T

~

~

~

C2

T

~

~

~

Cl

T

~

-.L

~

C4

T

~

-.L

~

C5

T

~

~

~

~

CI

T

~

~

C7

T

~

-.L

~

CII

T

~

~

~

C.

T

~

-.L

~

CID

T

~

-.L

~

CII

T

~

-.L

~

cn

T

~

-.L

~

CIJ

T

~

~

~

CI4

T

~

-.L

~

CIS

T

~

~

-.L

CII

T

~

~

~

CI7

T

~

-.L

~

CIII

T

~

-.L

~

Cit

T

~

-.L

C20

T

~

~

I

i--

r~

-.L

~

C21

T

T
~

~

T
~

~

C2l

~

T
~

~

C24

-.L

~

C25

T
~

-.L

T
~

~

~

m

~

T

T

~

~

~

m

~

T
~

~

C2t

~

T
~

~

ClO

-.L

T

~

+5V

cn

-.L

T

~

+5V

C47

-.L

T

~

+5V

~

C45

~

T

~

+5V

C45

~

C27

T

~

+5V
C44

~

T

~

+5V
e43

-.L

T

~

+5V

cn

-.L

T

~

+5V

C41

-.L

T

~

+5V

~

~

C22

T

~

2

~

~

~

Cll

-.L

T
~

~

Cl2

-.L

T
~

~

cn

-.L

T
~

~

Cl4

-.L

T
~

~

Cl5

-.L

~

Cli

T

~

-.L

cn

T

~

~

-.L

T
~

~

CllI

-.L

T
~

~

ell

-.L

e40

T
~

2

+5V
C4I

-.L

C50

T
~

-

-

3

3

-

-

4

4
DATE

I NAME

INOY.IJ. 90: S. K.

SYS68K/DRM-Ol

REY.

2

I

V

~.

~------------.~.....

A

1 ____

8

I

C

FORCE
COMPUTERS

POWER

SHEET I
FROII I
SHEETS

SECTION 4

APPENDIX TO THE HARDWARE USER'S MANUAL

E.2 Circuit Schematics of SRM-01

E-5

FORCE COMPUTERS

SYS68K/CPU-40/41

This page was intentionally left blank

E-G

I

A

I"-

1.41 A
PARI TY
BURST

.5V---------El A.

l

IICOOI

I,.

t#1-----tg

_

RAIITYP

OCI

COA TI 00: 311

Ii

._ _
COATU - - - £ l C2

1--__ COATI ~---fJ Cl
COUI8

---£J C4

COUll

---£]C5

_ _COH Ol-------f) 85

C:J------_£) AS

7
U1C

~

COU20 ---£J CI
l

COH04

IICOOO C::>------£J AI

e~L---1E

-

---£lB6
. ___ ~~!..~C7

_ _ CDAI05 _ _ .-£) 87

BClOO C:=J

f--~DAT06___ -£J 88

DAB

COAT2l
OAt
5

BClOl

COU07

Ii

5

0

810

sill- ------15

Ii

_ _ ~~2.~ _ _ --£]Cll

~-CDATO~Bll

1---_~_.__£JBll

elli--. -----11

5

BClDlCJ

__

e-ill---Ie

~~_---B8IS

BCL06 (J-------£J A16

>-.

B-&L-----ie
5

e!!..L---Ie

~

1,2, l, 5

CAORI 00: 31 J

OA20

-£)B16

COAT14

817

0

f--

f--.~T~---£JCI7

>--___ ~_T.i~ ------£l Cl 8

-

G-~--i!

oM1----ie

1,2, l, 5

CADRI 00: 31 )

.____ ~_O.~~ _____ _f) C20

1------ CADR~2. ___-£1 820

<=r--------D A2l

~~~E~----fJ C2l
_--~~___f)C2l

i--_~DR08 ------£JBll

CADRII
_

B-A.~L------l~
f--

J

PCLOI

CAOR!...O_' _ _ -El 824

CADRIS
OA26
J

__ ~Ai)RI~816

Ie

CADRI8

~M------l~

~

J

0

CADR20

PCLDl (::=J---------£) AU

---:~~~---£l m

828

_ . __ CAOR2_~ ____'£J C211

[3qo

G-UO---l!

a

DATE
f NAME
09, 90 f H R
01 91 I H. R.
I

18.

A

I

8

~

OBU

e:!~L--ie

V

f--

--£lca

--.....:~.~~------£J C27

_____~~ __£) 827

PCLD2 eJ.-------B A27

---£lCH

~_:AORll ____ -£lC25

1---. CADR~B25

<=J----------EJ AU

3

~~"E..R_OS_ _ ---£) C21

___ ._~~R06 ___ -£]B22

eAli-----le
PCLOO

CllUIl

L----. CADRO~821

OA21

J

_ _ ~_'?.A~_---£lCI5

>-. __ E.O~~i______-o Cl S

____ CDATl5_ _ ---£J 818

BCL07 c:J-------o 1018

-£) CI3

I------- COAT~ ___ --£J Cl 4

CDAT1~BI4

OA14

2

-~~------D C12

__ -.-fJl~!.Q~_-£] 812

BClD2 C:=3---- --£] AI 2

COAT26

5

---oct

-£lBP

CJ------___£] AI 0

elli----U!

2

-

-

CDAT22 .----£J C8
5

I

C

FORCE
COMPUTERS

SYS68K/ SRM-Ol
CONNECTOR

1

Ii
REV. 1
SHEET I
FROII 15
SHEETS

-_-==-______

_____________A
_ _ _ _ _---=r=---------B-_

c

1

M2A
I, 3, 5

_~~ ____

OA2

~"'-----EJ C3

RDBur G - - £ l A4

t:.AOR2~----f] 84

~"' ___ --£lC4

OA5

CADR25 ----f] 85

RESPDWeJ-----£J AS

~~O!O_~ -----£] 86

REscor

OA7

CADROI

--£]B7

c.=:>------£J A8

CADR26

oBB

CADR27

,., Bg

£JA8
OAIO

~_-£]BIO

i<4----£J AII

CADR29--£lBII

lSCPuc:J-----£lAI2

~~--ElBI2

lBIRII!)

i"----£J AI3
3,5

CAOR31

SIIOCPU<=}---------£lAI4

i...
3,5

3,5

SI II CPU C J - - - - E l AI6

3,5

J79-67

Cl----

~Q------lli

OB20

0 A21

OB21

sML---l1i

Oil22

I

~-----11i

I
II

i.--_-EJ

CII

I
II
I i
I
I

OB23

Hi

i--£l:::

0

824

15

SVSlDBYCJ--

f

I

i.----£J C24
r¥~i

'!l ...

OC27

OB2B

;41

OC2S

HI

~---li

oBn

r¥ll---li

830

sill---l!i
r-onE
I NAWE
24 09. 90 I H, R,
(,COl 91 I H_ R.
I

-----------_·-----A----·---------r=----------S---==~=_=-_=~=r::=---

1

OC2l

OB27

0

3 \

Iii

r#L---l!i

i.

OA27

15

II

~--l!i

OC21

OB26

oAn

~

CIS

CII

J3:-ill----15
Iii

I

-oCI7

OB25

oAJO

fl

~.-----£l CI 2

OA25

om

--

15

oCg

-£] BI6
OBI7

lECPU D--------£I A23

III CPU c:J

OCB

#L--lli

OBI8

IABOTc-J

$41

r#-L--l!i

OBI9

TACPU[)

Iii

BUREQ < = } - - - - - - - -----f] BI 4

GA2RIICJ----£lAI9

~24

OCS
;._---£lC7

oBI3

oAIB

RAIiSEt (""""")

c¥L----U:

J79-65 C } -_ _ _ _ --£jBI5

OAI5

i..-----fJ AI 7

3,5

G~ii

c¥L---lii

_~AOR23____ --£] BJ

;41

'2

OBI

-£lB2

i<4----El AJ

i..

J,5

M2C

CAOR( 00: 311

~. ____ --£I AI

J,5

~-------~-~------

M2B

FORCE

C-------------....., COMPUTERS

SYS68K/ SR~-01

CONNECTOR 2

~

REV.

1

SHEET 2
rRDII 15
SHEETS

--

B

A
PCLDO
PCLDI

C

~

mm--......---fiiw~::
I
I
5

1.5
2. ~

2.5
1.5
2
2.5
2.3
2
2
5
1
1.2.5

m~

PCLDl
GRAYRES
SIZOCPU
SIZICPU
BUREQ

:~~~~

rECPU
RESCor
IABOT
RAIISn
ADRCLK

CADR::~~:11

20

~

l

rlf

SJ

IF

pm

~

GJ

0

_______
______________.______

------

IY

r=--

'1=

01
02H:-l~------<
03 ~"-------

!5·r---------::;
===-1 r==n---

-~A:~ _-.- - - - - - - - - -

______

t~..

1l!lliIJ::t~lO,,~=-

,,,an

:~

:~g::

14
IS
16
17
III
19
liD

1/0_7
110 6
1/0:5
1/0_4
1/0_3
1/0_2 t-+'~I-"-"~'---....J
I/O_'

g~

18

----

06
07
011

It
110
III
112

:Is~

~m

CYCO

lr-,......

::::::

A!

II

L...

,

:I
2.5

J8J
~~

IYO~

·0

IYI
I Y2
IYl

ZYO
ZYI
2Y2
2Y3

CEI
CEl
CEl
CE4

6.7
8••
10.11
12.13

LADR! 04: 221

6: 14

r

~

VBll

---- .--!

'''''~-T'

-'tJ

:~:::CJ---.-- ~. -- -- .--------

2. J

CYC4
CYC3

~GA2RII

112

2

titj8rutu;Q

L.._ _ . _

II/CK 1/010

111

II
12
Il
I.
15

~
---:::-_1
====..JI"r=
-.--l 1---

. _ _ _ _ _ _ _ _ _ . ____ . _
_ _ _ _ _ _ _ _. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ --=-.J 1___________
==-.J
_ .. _ .. ____________
--____
--.

C:U'f-COUHTEIl

RE~~~~U.D-----I---I

~

'

I

J68
OEA
OE8

E

I

I

YOI r=

---Cm!lrS

YI 1.L_

~--T-IAI

._ CADHD'
_ CADHlo

II i
I
II
~I

Y2

-{>- Yl
Y4

:,

Y5

lL_

E

L-

Y6fj--

I

Y7

L_

I

j

..1l!4_

.:1 :1 '- 2

~
I

I

J69

O[A

~

DEB

--CAl) I

A2

I

A

I

g

AJ-{>-Y4
A4
Y5
AS
Y6

:;

_
Y7..t.-

L

H

I
I

illH1L:

.11.!LJ
J70
DPLcAD-----

:=L_
--L_.
____

___

----A-·-----==--=:~_=-----I_.====_=:~_S

~

--C::>SEREPRCE

n-ATTilli

f-.Utlf4r SYS68K/
____=_===

=_---------T-----_--~=-C==-

I

-

SRU-01

REV. 1

I FORCE
]COMPUTERS
T I UER '" DECODER ~:~~T,~
_~_ _ _---"':""L-_ _ _ _ _ _ _l_ SHEETS
II

'.--------

-~=~~~-==)- -~-

7,1,11,13,14

DUU[

7, I, II, 13, I •

DUIII

I

., 8, 10, 12, 14

DlIl!

I

S, B, 10, 12, 14

---------- [

________lL_________________ ~=_-T---

-==~==--

____=__=__=r=--_==_==--0

c

_:==~==_

~~-====

I

Dll!

I

COAT

II

J71

rnt~

~W

COEll

~-~ I
:DATOO

:DAr04
nuos
'DArDIi
DATDl
COAToa
COUOI
'DA 10
COUll

42
40

U

-~nH---¥SCDA

3

a IS

JJ

II
l

lAS

IAI

..L

1A7
ZAO
lAl
U2

llO
1I

m-~
20\5
20\6
U7

1

1----- --------

§:~--=-

--

COlT
CDA I~

...CDllLJ..

I

--

-

--

OlUOft
2BO 42
4
nt 11M
2Bl
2B2
-gt~l
2B3
01111 ,
2B4
l
285 _346 DlUI
DlUI4
286
287 I-JL.JlJ.JILL

J 72

~OO

!=t II
~

COAl
CU'
:OA'
:OA-

eDA:

1

CDA'

1

CDAT24

15

1 AO
tAl
lA2
lA3
1A4
1 AS
1A6
tA7

20\0
20\1
r-gemi----lt21.2
:OA'
lA3
21.4
HHffit---1fCDA'30
23 2AS
(I

1.4

20\6
lA7

- -

iw
180
181
182
1B3
184
185
181
187

~OHi+-

2BO
281
2B2
2B3
2B4
2B5
2B6
287

Dll24

-~

18
lll.!-

tHF'
L12.
_2,

l
II
l

l

--

--._-_.

--~------

COAToa

IS
16

CDAIJI.i.

gg:

f-

.

----~----

-----.--~--------

-----

I
I

-1+

10

1 AD
I AI
lA2
lA3
lA4
lAS
lAS
lA7

180
181
182
183
184
I B5
IB6
IB7

21.0
21.1
21.2
lA3

280
281
282
2Bl
2B4
295
286
287

.ll 2At
I

..cDAJU
COl.

-:illHt----#-

2AS
21.6
21.7

COEUU

--~~ I

I
r

it-

~ ~

I"-

!!---- ~

I-

I--

l-

~

COAToa
COATOt
COA 10
COATI I
CDAT12
COATI
~!.....kDAIl.S
__

:'~

i~~

180
181
182
183
184
185
18S
187

lAO
lAI
10\2
11.3
lA4
11.5
lAS
lA7

2BO
281
282
283
284
285
2BI
287

21.0
2AI
20\2
21.3

tAt

2AS
UI
2A7

_DllllDlL

•

~ ~

/0

!4

IS

-:-.lll!J_

-1654 '

I

- t----

..

---

-~--

I
(--J l_

- f----------------

----------- ----~---

r--t-

,--- r- -- _

c__

---------------

-~-----~---

'00

H

llit ~ lRlll

""~!I I~
I BO
181
182
183
I B4
I BS
186
187

lAO
IAI
11.2
1A3
1A4
lAS
lAS
I A7

280
281
2B2
283
284
2BS
286
207

21.0
Ul
21.2
21.3
21.4
U5
21.1
20\7

----------------- t----

~--~--------------

--------~-

--

J74
CDELIIJ1i:

I

--- ~

"-

--------

-~

- --

J76
CDEUU
lEUIl

~~ rnt~TIlilll

~I

I

0
2
4

-:1.6..ti..l

J78

~2L

180
181
182
183
IB4
185
I B6
187
280
281
2B2
283
284
28S
20e
2B7

I~
lAO

IAI
1A2
11.3
11.4
I AS
10\6
1 A7
2AO
21.1
21.2
2A3

COEUU

_~ 00:

lEUU~
~

r-

I

----------

lAO

~
'----

I BO
181
182
lal
184
185

tAl
1A7

IB'

f0-

r-

f-

.-

20\0
20\1
20\2
2Al
20\4
U5
2AS
20\7

280
281
282
2BJ
284
285
2al
287

-

;-

~

~

-

r-

tAt

'-

2AS
2A6
21.7

;-

~

I

:'-

.-

lAS

~
~

r-

f-

L--

'-

~

_--=l~

'--

----_---------

3

:-

;~

:~

;-

187

-t6543

....

, . , ..,

,

,

SYS68K! SRM-01
_------s-----------------=r-----------------'---- C-

II

;;r

1 Al
tA2
1A3
1A4

~

c

~=-=~_~~~===- A-==~-==-=~=-I

'2

12

d= t±-

---

---"-------- --------------- ------- ----

--

-------------- -------

CDA'JI

1 BO
181
182
10l
I B4
1 BS
186
lB7 -

-u

-~~ II I ;"~

~ mI

I

-.-~-~--~

---

:D,

r-

-

I

- - - - - - - - - 1--I
--------- r--- j----------------- -

~--

COAT

21.2
21.3
21.4
US
21.6
21.7

2l

'-----=l~

-------------------------- - ----" ----- -- . "--- - ----1--- r---

com

~

19
ZII
..li

I-~

LI

_":"_LlliL_

I AD
lAl
11.2
11.3
IAt
lAS
11.6
11.7

IIlf

J77

~ mt mI

corull

--

---- -

§.:-:-=--'-

§==--

--~--

..1:lllI1..O..

I
1
1I
4

2

rggm:--#- 21.0
2AI

OllOe

I

~-

8==

~~I

DllOO
1
l
l

lAO
lAl
lA2
IAl
IAt

280
2BI
2B2
2B3
284
285
286
2B7
L-

I--

LU.<

lBO
181
182
103
184
IB5
lB6
187

Sn&1:--:DU03

.

TRll

II~ ~

J75

ill---conu ~ 00
illt~ TRLU

CO~~~~~RS

DE -

1

REV. 1

Y:UTCTNI-PL EXE R . ~:~::~~J

A

T

c

I

B

JL ___

---=-__ -----

DATA TRANSCE I VER CONTROLLER

J81
1.5
1.5
1.5
1.5
2.3.5

2.3.5

"'''(
8ClDI

!~~g~

-----

------------

~----

-----

REscor C>--------

-.

-.!.-~f\~~lilli~-=~-;21\I!l

--- -------, ------ ---- -- ,------

18

~~nl'

I I Ir I

Dl

:~O

_

L~

RIIUOO: 15]

6: I J

•
I
"'---------------

~I

i

II

I
I I I-c)RRDO

RESPDWD---

"'_"[~__

+5vDPlCA

H
I

I

1.5
1.5

4

I

1.5
1.5

~ _- =- =~ . --'A-:~

I

_
___________ _____ _ _______ ____ __
______________
=r= ________B

____

___(_~_=~==~:===_n---jCOMPuTERS I SRAM-CONTROL~;~~T~5

_____~~-=_~===_==

,____ ~_

'

_:~_~ 6B~s~u-Ol __ J_~~~~~

FORCE

SHEET 5

j

~

--------

.. -

__

_.. ___ L __

--

~_~~_
_=~_
_=_=l_______ .~____6__.===·====I===~~=-===__=_ .c.__=__=~~~---=r=_.

____ ._~~ ___ D=__===_=~ .~--~

4.8. 10.12. I 4 OLL! 00: 31 1

J. 7: 14

l ADR[ 04: 221 _

nI

J1

J2
00
01
02

I

03~:---~~04~;--~~
OS H-.\;--~~

06

::

"o
000

'2
l.7

-.------~------.

5.8. 10.12
5.7: Il
4.8. I O. 12. 14

RROOC>---

04
05
06
07

t-

~

!5

<>-

'"

:;;

t-~~---~~.

~

r

II

r
I
II I:

...J...a........"----,N. C.

,!,1

i

!4

li~~----

J
I

RIR[ 00: lSI

giiiUt1f
IA6
---.llitii~-.-J. l~~
-

~-

-. LADR08

g

AJ
A4
AS

LAORIO

3

--!!tl-=tJ

J6

I

I

I

i

; I
~

L.

06

'

07

.

AI3
...

.,v0

0-

ao I

~

04
OS
06
07

I

" ' : e_
i~
""~ I
nR04 ~Bt
::
l-

5~

:s
'"- II

'"
a:

..,

'

1

!

I

1

II

~

"

,

I

!

I

I

GO

:

,.,.

1..U.IJU.L

I

fl

no

Olll[ 00: 311

J5

I

I

Jllr
... . . . - .

1..L......

I

!5

Vl

:;;

J.~ ,;:

-<

i

!-

1

~

N

:iii

1

Lllll...............

~-

g~~

2LllJJ.ll._

~~

AI2
AI3
AI4
--:-~~------'..-:.-i'" 5
..........""".........------''-''---lAI6

nor •• 1

DO
01

03lLDLU1.. -

~~~------:--!;---1AII0

'"
""ao

J4

r eve'.1

U
g: fUll: Ii
g~

"-~~!--+!--jAJ

~=~~~;;=::::~~~~

07

J3

nor.a I

Ao---O ..2.L..1l1J..ll
.~~~'~t-::....~~.::j~~
g~ 1.t1[l·u~

I

!

i I
I !

H

"

I

I

II

!A--..Jft

I

I

Ii

5,8. 10,12

RHOI L:)------.--.--~.

~---.-------- .. -------.-~-.-.------- .. - - - - .

• I

. . ,. . ,

.- . . - - - - - -

SYS68K / SRM-Ol

--A-~---------- ----.-- ----...---.----- ..---.----r ORCE
-S-R-A--::-R--O' --. "- -/-_________.___________ ~__ ___._ _ _ _ _ _ •. _
8 ___
.--------:=c~.--------.--.-(
..--- .. -------- COMPUTERS
M
Wl LL LM
_ _ _ _ . _ _ _ _ _ _ _ _ _ _ _ _ _ ~_____

1~1

MY. 1

siIn-;-;-

FROU U

'I

SHEETS.

----A--

.-._.-----"-"-

4,

t, 11,1 l, 14

l,', 8: 14

8

OUU! 00: 31 I

LAOR! 04: 221

I

J9

~~
-_J.AIlRDl

A4
A5

A6
A7
A8
A9
AID

J10 r eVlr'e
-------

1

10r ••

DO
DI
D2
D3
04
05

I

~m~i

I

~mH

AD
AI
A2
Al

I

07

AI2
AI3
A14
A15

AI6

A5

AI

A7
AS

CEID-

S, I, II, 1 J

RRD2D-

5, i, 8: 1 J

Rlllt 00: lSI
OUU! 00: 31 I

4.

I. 11. 13,14

IIII

~

.i

as

'-

....cEL.-JO

LADR21

__lAllltll----1-

GNO

14

I-

CL

07

• ""ft.

11:

AID

""

oo
N

~

5i

~

~F
GND

GND

24

II

24

'NI

'NO

GIlD

--~---

r
IOf ••

J1 ..

1

gi

D7

DI
02
03
04
D5
06_
07

l L _J)1J!1.QL
-

D-

~

""

00

'NO

RROJ C)----------

07

~

~I

J

D-

i

~i

~12

~i

1

eND

'11..~8

I

t--- - - - - - - -- ------- ---------4t-I----

r

a

IXI
Ul

I--uIllU-L-~N. C'

____GND

GND

1NO24

14
GND

'NO

- ------.---~

---"-

4

SYS68K/ SRU-Ol

________~_ _=-A=~~__=~=~--_=~ _

_.l__-___=______=__= 8== __~=

I

I

~m-

24

DOE

01
02
03
04
05
06
D7-

lLJI.lU!2.l__ ""-

D6

t=

r--

N

GND

14

01
OOIUl
02

o
en
co

~

J16

I

04
05 .l.L.~

D-

5i

~<}-_J8

10f.O

OJ

•

'-

~N.C.

J 15
1JJlLL_

DO

04

l

g: Ini~=U

AS

o
en

""

GNO

Ol

tCD

N

".

DO
01
02

D-

0
V>
t-

oo
oo

m-

A4

r '.Ir I,

At

t ......--

W

I"-

A5
'--- f-AI
~ f- A7

-

~

AI2
AI3
AI4
AI5
A18

..R1II09
12
~

01
--OO_11-_-JlllUllll
02
Ol 2S DUU03 .

S, 9. 11. I J

~g

--

AD
'--- f- AI
~ !-- A2
Al

~

All
D-

~

J 13

14

DO
01
D2
D3
04
D5
06
07

AID

N. C.

..J ,

J12

nor •• 1

~
H;

At

5i

ADR22

J 11
15

DO
DI
D2
Dl
D4
D5
D6
D7

A4

os

All

3,6

___ -.Ll____ __ - - - - - - - - -

C

_ ~~___==-==_=r= __=-==~_-=__=_~~~~=_=__----

----------j

CO~~~~~RS ISR AM

I REV.
SHEET 7

ROWl UM/UU

FROU 15
SHEETS

J'

=_==e_=_ _~=--=_=--====r
4, 6, 10, 1 2, 1 4

J,6,7,g:14

------~-

__ _ _ _ _ _ _
~

~=_~___L_~==~=_~-

_______

IL ___________________---{

DLL I 00: J 1 1

LADRI04:22J_

J 17

nor

_Q

J19

I

J 20

ncr.a I

rev.r ..

"'"
D-

;1

o

V1
I00

""

00
N

~

~

J, II

RROOL>- -

5,6,7, II: 1 J
4,6,10,12,14

00: 1 5]
DLII[OO:JIl

R~I

~-.-~-----~--~

--.---.- ---

~-

o

00

""

CD
N

""

N

a

a

--.... _-

GO

-

- --

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ • ____ h

I ===I ; ,
J 21

II

1.2
1.3
1lOL
!.AIlR.O.L
1.4
lAIlB10......ll 1.5

02
Ol
04

- lAIIl!U -

J 22

I

-=:1\;

--

_

...

II

-----------.

- - - -..

-~

.... ~~
J23

r ••• r ..

~~---->---.-

I i
• II II
Il
I

I
J 24

nor.,1

l-'

r ... r ..

---~.
00
01

J.A.IlBJl.L.

•

-:

nor.a I

A0
AI

J.AIlR.Qj

b

U1
I-

~I

mDJ

5,6,10,12

D-

V1
IeD

o

::i

I

D-

-Y--i ~~

~!~

-ll&tl
[Hill:
~Al0

26

DlII04

O~ 28
g7

DL 1106

I

Ii
i

r2.L..--JlLItQL

P

-lAllJU.5._=;E--'-- All

W~~

l

~2

~-~~~
1.15
1.16

~

err

ADR21, ~
~ji2
' r r --....
-9

I

eE2

ltMiO.! -

I

J

0

D-

~
~

GO

~ I
~ ii

5
e; ,

~,

I
I

,.

:x;
~
~

I

~~ I

RROID ..

~j

I
----+J

I

H

II
I

1
_ ._ __

I

I

I

kl

1--

~~'---i SYS68~/

A

!

I

<>::

'~z~~:--:(~__jl--~ 'l______

5,',10,12

I

!

---r= --

-~~
----------8----~~------'-

----------- .. --~-----------

SRU-01

l

REV.

: __

----------.----- ---- ---------------- -- -----

I

ji

-

FORCE
SHEET 8 I
COMPUTERS SRAU ROW2 L L /L M ~:~T~5_J

~
'.7.11.1 J. 1 •

l. 6. 7. I. 10: 1 J

DUII[ 0

LADR[ 0

III

J26

'IVer..

AD
Al
A2

DO
01
02

~~~~!'--H~::

gg07

J=~#~;;t=-~1~~~

'1

DUIIDD

I'--~~~~--l::

r---

m
AI 5
A16

en
:;;

...J.ADlli ~

err
~2

:i

!

.RR.D.2..

;:'--1
Bt

12.

I """,.J
>
eE2

5.7.11.1 J

RRD2

RIRC
DUU[

~

)-----

>----------

17

~

.~:

~~:
L-.....

~DR

~

::1.7

g:07

:~

.ADR~:

en
:;;

1.13
1.14
.ADRI.I
_I 1.15
......lAll.B.2lL-J..Jl 1.16

.AD~~f-·~~ err
~2

:i

1

m

:i

I -

un"

• u

~

g;

~

li-An~~' 3~

I
~

RWRI 0

----

,~, ,

---.--.-.----.--------.-

5

RRD2

I

d

:: ~

err
liP
~

"'1!ll....J! •. c

1 ___.,__ .___ J'_ .... I

--- - - - - . - - - - - - - .

DO
Dl
02

J28
AnRO'

AD
Al
A2

~-

g~

~:~

r---::

--

-

1.7

~

..

~::

-=UDJIl

en
:;;

~

.ADi~2 J~

:i

URI 1

~

'~I

c· ,

,. .:.

•• , •• 1
DO 21 DUII31
01 ~~ ~~~~~
02 •

g~

1f

ggD71-"-"--"-'''-'''':<----1

P;.-

AID
lADRI f----r~ :: ~
.ADRI
AI J
IDRI
AI,
.ADRI.\1 S
.AD121
I
All

I
g;

fIT

5

RRD2

12

~"',

'

~

:i

~~~.

,:,

Bt

II

g;

en
:;;

"-2

· ·

~

I
I

~.

, I

r---.----.---.-.-- -.--------------- - - - - -

-' - . - - . - - - - - - - -

r

III

J29 .... rae
DO
01
02
D3
04

1--~~~~--lAl

_~~

A2
_LADIlll._...J..6_ A3
....L..!DR.D.9......l.!i A4

__ LAnBl_L..1..! :~
-lAllB.l.L~--4-iA7

-illlli~

13

_ADRI
.ADRI S

I

_AOR·

~ 1
t--.lAJlR.2D.
----

iI

-::It<-

AD
AI
!~:~'
! 1.2
.ADRCB
16 Al
___ LAJlR.O.i~ A,

~-H---R1l-11M-

L1L.Jl.UllJU___

!.2§__lllIlJ.D.L":'t lL._JHW.D..L_

!

I

Al0
All
A12
A13
A14
A15
A16

_BHDJ~~.

LADRO'
.ADR05

g;
V1

:;;

I

I

~i

..

~

I·

20
19

"[Aiim 1. :~

07 ~...D..U.lLO]__

~~tr-t ID"

If'

J30
~~L...JlUl!DIL_

~~ L2!LDUJ!o.L___

-+ !~

...ADlU..L

>_

20

r---~.

I~
t~----rt AD

5,7.11.13

LADRD7

rovera.

AD
Al
A2

1.13
A14
1.15
1.16

~

I __.BltD.L~ ~

1 __ :~~ _~.

20

-Hg:g~--ft-

f---"

f--

g~

ADRO'

--HRfH-.J!- AI D

RWR09

~

f--

AID

llDR
.ADR
.ADR
.ADR
.ADR

g;

ID

:i

g:07

A7
. ::

---'..ADR

-1
_1..ADJUl._-.L 1.13
mill II' 1.14

RMlO!

~::

..

~~~~-"-!-~AI 0
.AnRU
.AD.R.2.0..

DO
01
02

~:~

t-

J27

no, •• 1

AD
AI
A2

~L....llIlItQL~

g~

~~~~~~A7

5: 8.1 0: 13
'.7.11.13.14

I

!21_

J25

3.8

o

c_

B _. __________--'-_ ~___.

A

."DR.

--

:IAili!it -~

g~ .~

07[ ti...D.UJJ.D.8.......-_

1.10
All
1.12
All
1.14
AI 5
AI6

I
g; I
~

:.,

Bt

§I
~I

1- jW1L~~~

I r r --=_~-BBD3~

J31

DO ~
LADRH.2o.
Dl
_AOR05
I9
112 .n. JlJlU12
~-WnIM-----H
03
6 D U U I 1 ! D R . O . . L _ 16
04 lLDU'11 n
~~

1.7

~_!:
ADR·. 5
.ADR· 6
1
~
1
I AOR20
10

.0, •• 1

j ,~'Mm~~~_=I=_~_~J.I;"'~.~~~.

J32

DO _21 DUU16
01 !2 DUUI
D2fj
03i6'DiiTI20 -04 ~2LD..U.lIlL_

_..L.ADRl1........l~_ A7

07 ~_2LIl.IJ.I1ll..._

r--~l.Ail..Rl..Q..JL ~~

~

, •• .,..

AD
Al
A2
A3
A4

~::lliifLJ: !~

AD
AI
_~:g6
A2
...l..!DltD..8.........J.i.. 1.3
'::J.AJlBJlL_..ll 1.4

8Htll :--

I

~i [l~::'-=

~
~
~

~DRI6

r

r

k::~l: 'lID'
m

Bt

!i1.7
::AID

~

f----.L....J.

~AAo ~~

All
1.12
1.13
AI 4
A15
AIS

RRILL

Bt

~

--lliIt- ~ . . .

g;
V1

, .lnp1 I

:;;

~I
~

-#
"I

IDRI 5

.ADRI7
.ADRI!

20
19

~L.AIl1I1.o._.J.J

...

"TIDiiI4 ...JL Al 0

All
1.12
4 A13
., A14
~HnAI 5
~~"- AI6

ADRO(
mR05

I

~C'j: 'l~

I

1

aor •• 1
DO 21 DUUJI 01 . 22 OUU30
D2 -~--D3 1LUJ.llllL __ .~
04 2LJl.JH1.2L__

g~ _.~Lil1Jill __ _
07

2Lll.U.U2.i.__ ,

I

r .::'Ilifl1'~ID'
___
a~ I

c-

I

I

I

II
l I

i

g; ,
en
:;;

~

I

!

Ii

I

~~

~j ,~""~~:. -J..

II

RRDl

r
SYS68K/ SRM-01

~~~-~~~-~--~ A~_~

____

_____

~~ _______-==-~-=~~J3~__-_=~_~_==---==__~~__ I---~=_~~-=--·---·----C------·-_----m-]CO~~~~~RS ISRAM
_____. _ _ _ _ _ _ .

_

ROW2 UM/UU

REV. I

I ~:~~\~_JI
SHEETS

· - - - - - - - - - - - . - - - ' - - ' - - - - - - - - - - - . - - - - - - . __.L _ _

4,6,8,12,14

~.

_________

==_-=.ft-==~=~:_=.=-___

OLUDD:JI)

'"

-

L=---====~==-=~c==--==~_

-----L---~

,........,.-""-""'-----_....-

-_-_--~=-=-D~----~--·-·------·------

......

l, 6: a,l1: 14 LAOR( 04: 221 _

J33

J 34

J35 .. v ....

nor IIG I

g~~=

J 36

01

o2 H-1r--'.?'~:-­

02
OJ
04
05
06
07

OJt~~~~---t

04
05

~.---e-~
06H1~~!'-~--1I
07t-"-'~"""'''''''''--1I

0-

~

01
02
OJ
04
05

'-

0-

a.
U1
I-

o

5:

a, 11: I J

4, S, 8, 12,14

CEl

c : : : : : : r - - - -----.- ---

RROOD--

~

CD

'"

I

L ADR22

~

W-1N. C.

I

~I

GNO

II

~--.J8

24
GIlD

---------.___.__________.___ _

- .-------------

II

________ _

R.[OO:(5):::~:::::::::::::::::::::::::::::::;~~::~::::::::::::::::::::::::::::~~;:::~:::::::::::::::::::::::::::::;~:;~_IBM..........................~

Olill 00: JI )

J37

r 'VI'.I

J 38

J 39

ftoraa I

~~'22D11111_

00Y!=t1l00
01
IlO1.._

gllt:-~gt:g~

Ol
04
05

04

05
OLII05
06 .a._..Jllll.Oi.07129
DLII07
""'-

6

06

'""

~I

~I

. -

I

RROID---

~8

~~

,

1.2

1.5
1.6

-L1U=j::t
~

-.J..AORllj

DO.
Dl

01
02

D2
!lJ
D4
D5
06
07

DJ
D4
05
D6
07

~..

1I..LM2.L....

r-- t--.---'E.L

IIIP~

0-

0-

I-

U1
I-

~

~

I

o

~

!

I
I

..,

CD

~l=-~=~f

ffi"

-------t~~ ~~-~~~' __J

I

N, C.

a

~

aJ·
fOlNO

I
I
I
I

II
I

ClIO

I

. . . .I~-.

rl

124. 09 .9.0 I H. R.
18 01 91 I H. R.
J

-r- ---====ffa~=-~_- ----·---·~=::r===-=-~====·-C-··__=~_=__

I

!

H

---14

.r-Lj

!DAfE-- 1 NAME

...L.____ _

I

I

pi

~g
1.14
1.15
1.16

l~

0°11 II

ftor.a I

1.8
1.9
1.10

11
L

14

GIlD

i.AW.L

J40

r 'Vt, Ie

All

I

-ltt.---.------.-----.--..
.-.-.---- .--- ---'-- --- ---.--- . . .-----1.1--------

ili
1

AD
AI

.-1.ADi1

:I
c:o
I

.

.l.LJll.WL
•• 1\1
.................IroB.--

07

3

5,6,8,12

"'"

,----

'"

;4~:----!'
5,6,8,12

-

.1LlU.lli.

ea

""

....J.All.Rl2.._

il.......OlJ.J.
.2LJU.J..2i.

I--

Ul
I110

110

Ul

l,l1

g;

o

~

ftor.a (

DO.L.QlUL.

...l~~~

DO

--

__

FORCE
COMPUTERS

SYS68K/

- ..----------

SRM-Ol~:' V.

-------_.-._.

-.-"~

SRAU ROW3 LL/LM

1

---

SH ~-~O'

FA 011 15
SH EElS

I

----~--A--

4,1,9,1l,14

OUIII 00: 31 I

3,6:10,12:14

LAORI04:221_

c

B

J 41

J42

ftOr •• I

r ,w,r

I'

J 43

Ao~--gllJHm
~~
02
~
Dl
~.
u

D4

05

0
1
2
J

•

5
1.18

~~

.~.

"""

+f"
8

'-

tialH

f

1&.,,1:1141"1

i~• I:~
1.8

1.9
1.10
All
1.12
1.13
AI •

CL

~

a

'~'"err

V)

I-

ao
ao

'"

..All

a

9

J, 10

~

12

--

--

---

- ------

J 45

~~

- -- -

niiiiD'
"Anft~

-~-

- -- -

J46

.or •• I

, I

'Ie, SI

t-

~~~if
9

o~

N. C.

.::u.J~: ~

~

'"

~
'NO

RRDJ L>-- --4.- ----~-

L-

L-

All

~

~

. .••••L - - •

C£l.

..lit

~

lC'PT'

6,::~:

iEl'

RRll.2.

~

CL

IbJ::

ADRZI
RlIlII

:iii

AI!

!---l

lADR22

a

..L1N. C.

14

~~u

1·

i

GlO

5
6

J47

'
!!

i-- ~~err
R~ilr--=~12

J.AM2L_~N. C.

~--lH~:

~~

CL

a

V)

I00

""

ao
N

~

-1.All.IUJL

~~

_____

D2
D3

O'
D5
06
07

II

~
L

err

'"
N

t

l_~

~

LL~
L~

'-

02
DJ
O'
OS
06
07

LLL-

-

cn

LAM2l

.JtIR1.5..
RRI

~!!~~t

C
L

t=

I

'-L-

'-L-

L~

II

II

CL

a

1.15

'"
00

I-

All

>C

30

"'"
6':::

IX)

N

~.nli:t.

:i

~

IB-

""

~N.C.

aI~2
Bt
I

If

,_LA::

~

g~

02
OJ
iH
05
06
07

LADRO'
.AOROS
AORO

,_

L.

_GND

I...

J 56

~

it·:r

n' ,,,.
~
02 ~
, ','

I B A2
,::g:~~ 16 A3
UIROI
15 A4
• AS
..J.AIllU..L._ ~ A6

a

I
:x;
~ I

'~ ___. ~ I
~ I

a::

mR*!at-~ i-2
''''UI-.J.~ Bt
CE4
,AOR7'

N

--

II

JO6

GND J

I,

'.AOR22

9 M. C.

,_

~~.

~

I

""'" I

I

'

I
:x;
N

D<.
til

GNO

___

l'

j

I

~I

I
~

I I
: !
I I

til

V1

~~
~

i

: I

D- I

I

:x;
~

I
I

I I
i I

N

::ii

~

~

I; .I

I

I

!I
i

!I

~

I

u_~=~=~~-.- · A- ·- - - -=.=~ ___ ~==:_=Ji.=~~:===~_=_n-.----·---.C------------·
J ______

I

I
i

I

0

AID

Ul

I

0

m

~

~

oor.o I

.n r-------,.. n, ''',

0

A7

AI3
At4
.lIS
AI6

I . I. • , ..",ft,

o. ,

,,!:

...

AID

-.£ A13

r---

N

I
D-

±!&l&l--j!--

J 55

re'e"e

1_~_~~!~===JI __ ~=~=:l~:~=_~_ ~.J.
I

RROI

A2
,~
L A3
.
A4
AS
···~..J..T-!- A6
.~ A7

D7L.l1QL-

m

.~:

•

_~JtD6.:.=Ir

l1.L

04

.J~A1O

L_, UIR

_J..Alllru~-' ~~

OJ

A7

l-tm
.ADK

~-

05
06

---- r '

J54
~~

D2~'

A2
Al
A4
A5
A6

,

tl Ii m

.or •• , _

g~

1U::

a, 1 0

N

::ii,

I

J.AD,

5,5,

""

co

~

a, 1 0

4,', a,l 0,14

Ul

eo

N. C.

~

l-~

r

.- .LADRll

3,13

5: II, 1 J

a

;I

~}4
5,6,

~

~

t-

GND.1

I
I '

~I

i

~
I I

I

~

i

-

i

SYS68K / SRM-01
fORCE
COMPUTERS SRAM ROW4

LL/LM

REV. 1
SHEET 12
FROII 15
SHEETS

__________~____.__.__ ._ L=---=______]L __
" 7, I, II , I.

J,6:12,14

-=-=___

LAORI04:121

_

J 58

J59

nor.o I

'-~

~~m!

BH~21

02
03
04 '}.7 . DUII05

t

05

g;

'-

o
en
oo
co

t-

""

CE4

---I

14

GND

D--+--I--+·---------- .-.. -.----.

RR02

5:12
4,7,1,11,14

Rill I 00: 151
DUUIOO:311

~

:e:

H
I
13

~l ·~._1!~o

!

n.[il~1
r~--.

I

! I

H

- J.AlllU.L~A 1J
Al4
---.UJlR1.J...
1.15

.i 1'"

0t-

oo

.--CE.1.-~EIT
L_..JjEi-2

~~~Bt

_.. -llDli2....

~-Lkc.

,

!

D7

A16

30

..-.r.-

t!l

0-

o
cn
too
:w:
oo

CE4

'"
:;

-RiIIII

a

RRD2

IAIlR22

AIO

All
AI2
AI3

A14

AI S

All

,W

5-J»-'
ff'jA-

-.LjH. C.

0-

~=-

a

1-

GND

-T

14

;ND

UII

I

=

I

J63

nor.a I

t t=
il~

. II II

:~ I
J64

.or.o I

l=tIHHH

IWllt1

05

g;

'--L

All
A14

!1~
~~~ti~
'

""

oc

3~ ~

1tIIU.l.~_

:

8803

I- J..AllR1L_L~".

c.

1

07 ..'Z.L.D.lllJ1..

~
.

CE4

.lOR?

Rill I 4

RIIO,

LADR22

I.....

AIO

All

AI3
A14
AI5
A16

JD_
6i~~~
5_1~'

--:J:CJ~

~N,C.
1.L~v

~~'1>at.a Hold
'?OATA Set up Time

S2

SI

S20

S'O

0-5

IO-second digit register

2 0 0 I 0 Mil

mie

mi.

I mi:i

mil

0-9

3 0 0 I

,...,

I-minute digit register

mi.o

milO

milO

0-5

IO-minute digit register

-

h.

hz

hi

0-9

I-hour digit register

PM/AM

h20

hiD

7 0 I I I 010

,...,

,...,

8 I 0 0 0 MOl

mOa

mo.

I MilO

I 0 01

Sa

he

de

d.

d2

dl

0-9

I-day digit register

d lo

0-3

I D-day digit register

,...,

A I 0 I 0 VI

Ye

- Y.

B I 0 I

yeo

Y.o

I 10 I 0 W

,...,

W.

mOl

0-9

I-month digit register

mOlD

0-1

I D-month digit register

Y2

YI

0-9

I -year digit register

Y20

y,o

0-9

I O-year digit register

WI

m02

0-6

Week register

HOLD

-

Control Register 0

ITlPf/STNO MASK

-

Control Register E

--

Control Register F

I

W2

0 I I 0 I !legO 3OsecAOJ IRQFUG BUSV
E I

I

I

o !legE

F I

I

I

I !legf TEST

t.

to

D-ZorO-1 PtA/1M, 1O-hcu digit register

d 20

9 I 0 0 I MO lo
I VlO

I-second digit register

24/12

STOP

REST

*0 = "L" revel. 1= "H" revel. REST = RESET ITRPT/STND= INTERRUPT I
STANDARD
11l3it - does not exist
;"i) Test must be set O.
:!ll'lease mask PM 'AM bit with
I:! hours mode.
31 Hus}, is read only.
~I.IRQ must be setl.
.Set IRQ to 0 after interruption.

• WRITE mode (wi th ALE)

! nsec

: 120'

tW(W)
tpzvCR-Q,

Remarks

o

tSU(W-ALE)

Jm 1Q Date

i

Value

0'

, .ALE, After WRITE
WRITE Pulse Width

!

---l

Do

:

G,I

Standard pulse = 64Hz out

sec

T.=2S"C Voo=4.5V

!soc

Do - 0 3• STO.P

10

Voo=ZV

Voo =2-5.5V

\I

_.

01

i

6 0 I

Inputs except Do - 0 3

i

s.

SlO

4 0 I 0 0 H,

STO.P

O2

S.O

oI I

5 0 I 0 I H,o

pF

20

03

s,

I Count

Data

03

-

I 0 0

0 0 -0]

V

10

00 -

...

-0;;

i

0-9

0 0 0 01 0

0 0 -0]

10 JJA

Voo=SV

CS, =OV

1002

Inputs except

JJA
V

2.4

~

All inputs
except CS,

V

0.8

~ A3 A2Al~

Remarks

CL = 120pF

i ..

i 120

i

o . --I

tPVZ(R-Q)
tsut-

- ~~~~----...

\'~.,

~~~.--

i~

~---UNOER I S'v'OD---~!

~" :'V~I~G

THIS riME CSO ='H

JG 'Nl-.!tBIT WR

--

ALE

RD------------~--~I

AFIER THIS THE INTERFACE
WITH RTC IS AVAILABLE

" 'HIS '5 THE SAME OPERATION AS A STATIC RAM

D.' 0, --------------------~f~<'R~

DMAR>~ Floppy Disk Controller
The CPU can read from or write to the Floppy Disk Controller via the LCA
(non-DMA mode).

2.

CPU < == > Buffer Memory
The CPU can read from or write to the 16 Kbyte Buffer Memory via the LCA
(non-DMA mode).

3.

Floppy Disk Controller < = = > Buffer Memory
The Floppy Disk Controller can read from or write to the 16 Kbyte Buffer Memory
via the DMA controller which is inside the LCA.

Page 14

SYS68K1EAGLE-OIC USER'S MANUAL

2.2.2.1 LeA Data Transfers
The CPU accesses the Floppy Disk Controller via the FGA-002 for initializing, for writing
the floppy commands and for reading the status information of the Floppy Disk Controller.
When the Floppy Disk Controller is initialized and it has received a floppy command (e.g.
read/write a sector/track command), the Floppy Disk Controller starts transferring the
floppy data bytes. The Floppy Disk Controller can be initialized in DMA mode and in
non-DMA mode.
The data transfer of floppy data is described as follows:
Non-DMA Mode

In non-DMA mode floppy data is transferred by the CPU. The Floppy Disk Controller
generates an interrupt to the CPU when it has received a data byte from the floppy drive
or when it wants to send a data byte to the floppy drive. The CPU must then transfer the
data byte to or from the Floppy Disk Controller within a certain amount of time so that
no data will be lost. For each byte which has to be transferred the Floppy Disk Controller
will generate an interrupt.
DMA mode

In DMA mode floppy data is transferred with the help of the DMA controller inside the
LCA. The Floppy Disk Controller generates a DMA request to the LCA when it has
received a data byte from the floppy drive (DMA READ) or when it wants to send a data
byte to the floppy drive (DMA WRITE). After each DMA request the LCA generates a
DMA acknowledge to the Floppy Disk Controller. The LCA contains a DMA Control
Register. One bit holds the information for the LCA about the direction of the DMA
transfer (DMA READ or DMA WRITE). It has to be set to the right value before a DMA
transfer is started (See Chapter 2.2.2.3 LCA DMA Control Register).
In a DMA READ operation the LCA transfers byte for byte of the floppy data (e.g. a
sector or a track) from the Floppy Disk Controller into the Buffer Memory. When the
transfer is complete the Floppy Disk Controller generates an interrupt to the CPU to
indicate that the buffer memory is filled with the floppy data and that the Buffer Memory
can be read by the CPU.
Before a DMA WRITE operation is started the CPU has to fill the Buffer Memory with
the floppy data (e.g. a sector or a track). Then the LCA transfers byte for byte of the
floppy data from the Buffer Memory to the Floppy Disk Controller. When the transfer is
complete the Floppy Disk Controller generates an interrupt to the CPU to indicate that
the memory buffer has been read by the Floppy Disk Controller and the floppy data has
been transferred.

Page 15

FORCE COMPUTERS

2.2.2.2 LCA DMA Control Lines·
The LCA automatically generates the DMA control lines for the Floppy Disk Controller.
A DMA control line called TC (Terminal Count) exists on the Floppy Disk Controller.
TC is used to stop a data transfer between the Floppy Disk Controller and the Floppy
Drive. This is done by accessing a dedicated address (read or write access). This address
is shown in the table below. TC will become active during the access and inactive after
the access. For detailed information please refer to the FDC Data Sheet in Chapter 5,
~COPiES OF DATA SHEETS".

Table 2-3: Address Map for Generating TC
$FF800000
$00003800

Default I/O Base Address:
Default Offset:
Address

Offset

Mode

Label

Description

FF803805

05

RIW

TC

Terminal Count

HEX

Page 16

HEX

SYS68K1EAGLE-OIC USER'S MANUAL

2.2.2.3 LCA DMA Control Register
The LCA contains a register which controls the DMA transfer between Floppy Controller
and the Buffer Memory. Register bit 0 controls the direction of the DMA transfer and
must be set to the right value before a DMA transfer is started. The register bit 0 can be
read back. Register bit 1 indicates whether a DMA transfer is in progress or not. It can
only be read and will not be affected by a write access.

Table 2-4: LCA DMA Control Register Layout
Default I/O Base Address:
Default Offset:

$FF800000
$00003804

Address

Offset

Mode

Reset
Value

Label

Description

FF803804

04

RIW

FC

LCAREG

DMA Control Register

HEX

HEX

Table 2-5: Description of LCA DMA Control Register Bits
Bit

Value

Mode

0

1
0

RIW

1

1
0

R

Description
Buffer Memory to Floppy Disk Controller (DMA WRITE)
Floppy Disk Controller to Buffer Memory (DMA READ)
D MA transfer in progress
DMA transfer ready

2.2.3 Floppy Buffer Memory
The Floppy Interface of the EAGLE-OIC holds a 16 Kbyte Buffer Memory. The Buffer
Memory can be accessed by the CPU and by the Floppy Disk Controller via the LCA (See
Chapter 2.2.2.1 LCA Data Transfers). The Floppy Buffer Memory is accessed by the CPU
via the 8 bit Local I/O Interface of the FGA-002 in the address range $FF880000 to
$FF883FFF. \Vhen the Floppy Buffer Memory is accessed by the Floppy Disk Controller,
the LeA generates the address for the Buffer Memory. The address is set to zero at the
beginning ofa DMA transfer and is counted upwards by the LCA during the DMA transfer.

Page 17

FORCE COMPUTERS

2.2.3.1 Summary of the Floppy ButTer Memory

* 8 SRAM

Device

32K

Addressable Space

16 Kbytes

Access Address

$FF880000 to $FF883FFF

Port Width

Byte

2.2.4 The Floppy Disk Bus
The floppy disk bus is an SA450 type drive interface. The floppy drive signals are provided
directly from the Floppy Disk Controller with no additional buffers. Some of the floppy
drive signals can be changed via switch 1 to switch 8 of the dip switch array SWI. The
switches must be changed for the different types of floppy drives which are used. Switch
9 is used for the LCA configuration mode and must not be changed by the user. Switch
lOis used for the write protection of the FLASH EPROMs and is described in Chapter
2.5 The EAGLE FLASH EPROM. The default setting of the dip switch array SWI is
shown in Figure 2-2. The location of the dip switch array is shown in Figure 2-1.
The following floppy disk signals can be changed via the dip switch array SWl:
M012IHEADLOAD
The motor on signals M01/DS3 and M02/DS4 of the Floppy Disk Controller are open
collector lines. They are tied together and have the signal name M012. Via switch 1 and
switch 2 either MO 12 or HEADLOAD can be connected to the MOTOR ON signal of
the floppy drive. So both signals can be used to start the motor of the floppy drive.

CAUTION: The switches must not be both opened or both closed at the same time.
Table 2-6: Dip Switch Setting for M012lHEADLOAD
Active signal

Switch 1

Switch 2

Default Setting

MOl2

off

on

*

HEAD LOAD

on

off

PagelS

SYS68K1EAGLE-01C USER'S MANUAL

HEADLOAD/EJECT
There are special 3 1/2" drives which need an eject pulse to eject the floppy out of the
drive. The eject signal must be connected to the pin which normally holds the HEADLOAD
signal. Via switch 3 and switch 4 either HEADLOAD or EJECT can be connected to the
floppy drive.
The FJECT signal can be generated by accessing (read or write) a dedicated address.
FlECT is active during the read or write cycle to this address and automatically becomes
inactive after two microseconds.

Table 2-7: Address Map for Generating EJECT
Default 1/0 Base Address:
Default Offset:

$FF800000
$00003806

Address
HEX

Offset

Mode

Label

Description

FF803806

06

RIW

EJECf

Ejection of Floppy Disk

CAUfION:

HEX

The switches must not be both opened or both closed at the same time.

Table 2-8: Dip Switch Setting for HEADLOADIEJECT
Active signal

Switch 3

Switch 4

Default Setting

HEADLOAD

off

on

*

EJECf

on

off

Page 19

FORCE COMPUTERS

DRIVE TYPE
The DRIVE TYPE (DRV) signal is used to indicate to the Floppy Disk Controller whether
a floppy drive with a two spindle motor or a one spindle motor is used.

CAUTION:

The switches must be both opened or both closed at the same time.

Table 2-9: Dip Switch Setting for DRIVE TYPE
Drive Type

Switch S

Switch 6

One Spindle Motor

off

off

Two Spindle Motor

on

on

Default Setting
III

PRECOMPENSATION VALUE
The PRECOMPENSATION VALUE (pCV AL) signal is used to select the write
precompensation time of the Floppy Disk Controller. The time is selected via switch 7.

Table 2-10: Dip Switch Setting for PRECOMPENSATION VALUE
Precompensation Time

Switch 7

125 ns

off

187 ns

on

Default Setting
III

DISK CHANGEENABLE
The DISK CHANGE ENABLE (DCHGEN) signal is used to enable the DCHG input
status at pin 40 of the Floppy Disk Controller. DCHG is the door lock signal of the floppy
drive and indicates whether the door of the floppy drive is open or not.

Table 2-11: Dip Switch Setting for DISK CHANGE ENABLE
DCHG Signal

Switch 8

Default Setting

Enabled

on

III

Disabled

off

Page 20

SYS68K1EAGLE-OIC USER'S MANUAL

Figure 2-1: Location of Dip Switch Array SWI

a«

/

d i l ll:I
&

§ I~

[[]]

J13

.. 0

Q

a:

Jl2

J17

J2

Pagell

FORCE COMPUTERS

Figure 2-2: Default Setting of Dip Switch Array SWI

ON

OFF

~u~uuu~~~~
l
01

02

OJ

04

05

06

07

08

09

10

2.2.4.1 The Floppy Drive Signals on VMEbus P2 Connector
The floppy drive signals are available on the EAGLE 110 Connector which is connected
to row C of the VMEbus P2 Connector. The pin assignment for the floppy disk signals is
shown in Table 2-12. The floppy drives can be connected to the VMEbus P2 Connector
via the backpanel SYS68/IOBP-l (See Chapter 2.6 The SYS68KI/OBP-l).

Table 2-12: Pin Assignment for Floppy Drive Signals on VMEbus P2 Connector
Pin Nwnber
Cl
C2
C3
C4
CS
C6
C7
C8
C9
CIO
CII
Cl2
Cl3
Cl4
CIS
C16
C17

Page 22

Signal Mnemonic
RWC/RPM
HEADLOAD/EJECT
DRIVE SELECT 2
INDEX
DRIVE SELECT 1
DRIVE SELECT 2
DRIVE SELECT 1
MOTOR ON/HEADLOAD
DIRECTION IN
STEP
WRITE DATA
WRITE GATE
TRACK 000
WRITE PROTECT
READ DATA
HEAD SELECT
DISK CHANGE

SYS68K1EAGLE-GIC USER'S MANUAL

2.3 SCSI Interface
The SCSI Interface on the EAGLE-OIC is built with the SCSI Controller MB87031. The
SCSI Interface is installed for direct interface to SCSI Winchester Disks, optical drives,
tape streamers and other SCSI compatible devices with a data transfer rate of up to 4
Mbyte/s. The 1/0 signals of the SCSI interface are provided on the VMEbus P2 Connector
of the base board via the EAGLE 1/0 Connector. The SCSI devices can be connected to
the VMEbus P2 Connector via the backpanel SYS68/10BP-l (See Chapter 2.6 The
SYS68KI/OBP-l) .

2.3.1 SCSI Controller MB87031
The SCSI Controller MB87031 is a CMOS LSI chip designed to control an SCSI Interface.
The MB87031 can serve as either an INITIATOR or TARGET for the SCSIbus. The
Controller contains an 8 byte FIFO data buffer register and a 24 bit transfer byte counter.
The Controller has two independent 8 bit buses for the DMA transfer and non-DMA
transfer.

Features of the MB87031 SCSI Controller
Full support for SCSI control
Serves as either initiator or target device
Eight byte data buffer register incorporated
Transfer byte counter (24 bit)
Independent control and data transfer bus
Asynchronous data transfer speed of 2 Mbytesl sec
Synchronous data transfer speed of up to 4 Mbytesl sec

PageD

FORCE COMPUTERS

2.3.1.1 Address Map of the MB87031 Registers
The registers of the MB87031 are accessible via the 8 bit Local Interface of the FGA-002.
The following table shows the register layout of the MB87031. Additional information is
provided in the MB87031 data sheets (See Chapter 5, COPIES OF DATA SHEETS).

Table 2-13: l\ffiSi031 Register Layout

I

Default I/O Base Addre
&oJ
a::

I

I
I
0 1

II
I£X)

I

I

I

:

H
j
1

I

i

I

iI

I

I

i

I

I

!

i

i : iii
I

~

!
i

!) ~:

00

sl

i

ul:

~~i~ 0

!

HUH

I

j- ::
., ""
"
I"Benu
II

"I

..
II

n

_.1
.....
_.1--.,

I

&I

ltHll

IeNII
am1l
amll
ICH12

1I/C1
II'

...
..

il4
I'

...--,.

IJ

Doli••

,-

...
-----n

"I

1/1111
1/1.,
1/1.,
1/1_'
1/1_'
I/I.J
1/1_4

I/lJ
I/lJ

C8,....
PI_

,i•

-

U ..
iKsl

...- 5.'
E~·,
II

"UII
II

~

iiiI
CSIO

.

_I
...-1
>-- 7
_I

-

£ ......

1/1-1

Itt

111

3

.-

ICHII:JII

--

3
05.•.•.•. 10

-

-

~ll

en

4

4

NoN

I NAU[
DAn
I 7i1nl ,--,,_

~rp_

T

SYS68K/EAGLE-01C

REV. 1

I

/--

A

I

B

I

C

'--.~-

FORCE
COMPUTERS

IOC/DECODING

SH[[T 3
FROM "

SHEETS

,..,.,

.. -

"

w
cor:

..:

-'"
=!=
..... '"
r.~

-

u
0

I

&.oJ
~

c.,:)

<
&.oJ
.........

~

(.)

0
..J
(.)

::.::::

(I)

CD
V)

>-

V)

en
~

LIJ LIJ

c.u-

~~

OD.

L..:::'
0
U

;
I

lu
I

;

;

I
. I

Ii
II

H
I

.

I

I

I '

IlenI
I

;
,-----+-I------4_-----+-~~ ~II
•

l.---l

~II

Ii
I

!j

I
I
1

v~·---------------=-----------~---------------~---------------~----------~~----------~---------------------------~l

A

l,',7,'
2,10

___~

8

~c~

_____~

o

_11:111
I[PlOIII': 11

Imll:!11

J10
11["
III
At

cur.OIII 2
••ur

J 11
r
--------

4------

I[ra_
o[raOlll _~

AI
A2 -}

"PlOII2

:! •
::

~

A7

I

_ma_
I
HASH-UEUORY
- K,iOiii - - - - -14 DOt
128. 8
~_ _.MIIltL----tI
- "iiiQi1 ----- - - - - , DOl

-==-~ ~--ftt~~-- --

:~

::;

-'1 :::
D[PlOII!~-b-;iioij7~:

--=w.3I":::: ~~!m~-=-:-~-

DOl
D01

CUPlOIII

••ufln
__'_~_I!!!L

Ic[

• /Ill

JI

,.
--MI£Ll.~

AilVI"

~

VI"

2

2

~- .. I--------

- - - -- ---- --- --- - - --- ---- - -

1.2

S41

C)--ill-YL~I

2

IlUf'II

II~-~-H-~

J12

3

3

__ 1!!'_~__ _

__ It'll!!!1 ____ _

.

:l!~_~~~=

-

~"
~~~•• ~~~-~~- ~=~-~=~~~~

c~_

- -----• •Uf In
_1~!!IJ!!l

'----

----

2
• /ct
/Ill
JI,..

__AI-,~r ---LjVl"

.5'

4

4

pr,r

/

A

_____I-=~___~~===B

____ ________
~

_____ _
C- -

_____

II

lIUI";)

fORCE
COMPUTERS

ISYS68K/EAGlE-01CI

REV. I

EPROMs

SHUT 5
FROM II
SHUTS

___=-=-==-------C_-=~====~=-_-_-~~~_~~(~=__==_~~~=-==~:~_==L

8

_________

o

InCII:71

oIV

II.ICII:71

i, 7,'
3, 5, 7, 1

...,,,: UI

.

IFDtllO: 71

J15

WOJ 7C65-Pl CC

--11:--------

.. on
__ AjlHC_

1·_---------

[e ~,1J

_1_

~ w':;2-100

~"'-- 11 1 1---' -lCAIIOI[
....t~t"
HaIPn

__

Me

- -1----

~~m;!:"
IIf
m
m

vecs·
lL_j

:-=--:-~:--

5110

11\

111-1/0

If,.
~----

....

1/0-'

IILKL

1/11-'
1/11'"

.,KIt
..u.

~
._.

2

1/11-1
:~:!

1/11-7

nIH

1/11'"
1/11'"
1/0-11

--------~HI/II-II

_I

--_

ICl2

U!lf2
rm1
AWl
.---.
F.
'.....

~

--

1/11-1'
I/II-Il
1/11-14
1/0-11

--

1/11-11
I/II-If
1/11-11
1/11-11
1/11-"

Iff
II'

mr

uv

,/o-lIDe

,/o-ar

II

-

U[Cf

.(Sneor -- -j

-~:t::--I--~

:~~~tu1t===~~~ll~~~.-..Ill
_--I-----'
:::~:LU~-~~'~~ue.-_·_-~

'/11 ... 1
1/11... 2
'/0""
'/0-10

:~:::

1/0"'1.1"

'/0-51

---= _

---.-I[AW.

-

--

---;-1---·~-XTAl

-

1

Il~!!_
__J"- _ _

~=~g_

-

j_----"

--'f:KL

IIW~'
.~
27
____
rnmr 7 M-

,---------

-1-1

Iftn

~

.'IIL-_
nr~.
'm
lAC!'
II I

DrDCIl

::::1:
I/O....

=~

CS::m_~~_==~1

,--------.-~-~==-J::l~J.

--I---.

i

----~E

---~ll'

I

_-----<

CI

C7

-----.l!lli!!LCJ

2

SWl

__

1::~t J8Pf

-1-------------'

_

•

Cl4'F

-=::J

-=:::J
-=:J
-=::J
-=:J

J16

t--_-.- ---r=~--~-

t!:;------,-

5RAUJ2K8

___
I
_.-10.

-=:::::J

IDI;

-==:J
-==:l

5Wl TCH1 0

I'
I'
IJ
U

-»JCI.t.__ _
~­

~

15
II

J[JIW, _ _~-;

3

-=::J
-=:J

3

11

'-"""----t--=-"I~
L ._____ .

If'

.a,
14

21
tlv

.,IC.. I:UI

-~*- T- -=~--=:=~~--~:~==~==-=~===~=~----

4

;1
...

A

B

------i

--~---~~'==8

a

14

~

~ ~

9SYS68K IE AGlt -01 C I

I~----------C--------------- CO~~n¥~RS I

FLOPPY CONTROL

I

REV. I
SHEET.
FROM II
SHEETS

_~_A

-- ---"-1'--'

__ _

,_~

____. ___.a __

__.____ L_

-=-~_._=~~

71

0

7••

..

'

3. 5.,. I
2.1 ••

J22

D

74f642

..!{m1.!l~lft.__ _

_. ______ .~[S[IlOCln

UKIt: 121

I

J 501010:11

.SV

.. DIDII.
_SUOi
DIQ2

IlOCIG: 71

-

_Dial
.lJIlIDI __
kiWI

-~:~
_1. [VEl

rJ ..JLOCPn

2

t

__L 000

~ 4F 2_8~

c:::>-..ILacru£1

SOIlO
R41
5DIlI
5D.U
SDIU ......' - - - ' 11.'SDIU
SO.U,.......-..-lD . .
SOil.
501£7 LLIl_·- n ..........

J.L - - -

:~ JJ~---==ili=l==!m--=ftj
:: _lL

:~

II

__

50.0

i-= ...:-_---=-=- ~~~_.
j

~l

12
15

AS

1 1 I' 1 1 I 1
I I I I I~ I I

...
•••
!!!

I I I I I I I..

'"

I I 1,

I.

p11

D

o

§
c:
,

c(,
-

II

JmOO
-

t" -=-

II~~501110: 71

•

t--

SlllJR_
-.- WU

~-.- VI
YI

.----

.IRI12...
--lRIJL - - . - - lIIlli ________.__

2

YJ
YJ
Y4

85t_~ ~~ ~~-:-=:-..i ~~

__

1---- --_.---

SDIOI' .lL--____ ~
~

:!

J23
74F240

::::~ 7L--_~:~~

c..:>-..JIIJIL.

.

AI
At
U
AI

--~--' :~

•

..mn-

.--

-

JI))J)J)J

.0

AO

20

SD.OO
50.00
50.0, l l -_ _ _ ~J.!!!01
50101
50'01
SD.Ol
50.04
SO.04 --50.05
SDIOS

---ti.lD--

- -=.. -

.sv

'-~~-

J18

~

--.-~

D8Q.1 __

.DIDt

J21
11887031

0[

.----illjJ-~DI.

_ _ _ _ _ _..ill!L_.

~--------~~---

_nual

:':;L::w

.-"Desl
11

14

~~

_ _ _ _~~I~---

JI9

SDIIP

~

7••

J24
74FHO

~~-----~~
50117

It-rr-r"rrrTj-r"LITO]

IllllU

·1

.--~----

3

3

'I

illUJJJ

-~-----

++-H--,

5111

J25

.."

74F642

TAIII

.1L
..1L

.1!..

•

~.uurIIU _____

2••• I

4

4..

.IUf.IJ.K

. - . - - - - -_ _ _ _ _ _ _
- -.-. ------

'---.-----~~-~

..!!--

..
.--J

IO~
:~

~ •. c.

IAnlt: 71

L -_________~__~~--~

..n..

L -_ _ _ _ _ _ _ _ _ _ _... _ .

lli..

---------"--

y

u

If.
"12
AU

:~

~
-.-. . . -.. -----.A
_____

B

__

4

~~I~~~~
_ ___________

•
I

IT

DATE

J NAME

SYS68K/EAGlE-01 C

C _.___

I

I

REV. I

SHEET 7
rORCE
FllOIIll
SCSI CONTROL
._.....L..C---.:.O_t.tP_U_T_ER---.:.S....J.._ _ _ _ _-L-~_
SHEETS

A

8

.~~ 1_~·==~_~=~_-~·=

____

0

j;__...

14
2,',7

.lOCl.: 71

_--.e'

(

T'.5

J 27
74F 38

J26
PAl22VIO

" .. L.·~Il ___ .

_._r··

4,7
7
7

n

3
3,5,', ',10

---~ ·--t-.---+l-+~+I-tl-------,

n 1--'

2, •

3,5
3,5

--. -. - - - -

~!~~~~~

'!~:::!!

CJ ,

n _ CJ

1[1".

2

0' ......

II.

a

I

ACI

C1

I

2

C£SUP.OII,

.! I
!! I
'41-LL

7

7

'~-I
uv

---.~-

--.------

3

3

2
6

2,7, •

-~.-

.. -

.-~-.-.

_ _-----"--------..

7

4 - - - - - - - - - - _...-

------------

7
""!:'::~

-----

o-'lIf'1.

-+-i

+-_._------- -_._.'---, ,..-

IIV

',7
5

.Sf . .

41

14

liI<.r

)

A

=__._ _ _

___L ____

_ _ I =___·--

~-fI======~

c

If

!lUI

n.>

fORCE
COMPUTERS

ISYS68K/EAGlE-01CI
SCSI CONTROL

REV, 1
SHUT'
nOlI II

SHUTS

)

A_________________

L -_ _ _ _ _ _ _ _ _ __

_ L=::==--.-.

B====~~-

3.5.'.1

JJ2
AIH992B

J31

AlUIIII,,,,

10

0

---C--

A1I7990-PlCC

_~I"'l!
ADlA.•~ __ ..
AOli.i

"AOlIU_

. J OALI
~. OAU

ClU

OAlt
DAll

IUA

. ...ll

-Aii.".L........J.L
-li" ..... --..::11

~

II

DAL4
AI.lill
..•.. ---- __ .
.. OAlS
AjiLUI __. _..........-J.L OALI
_~j,MlL_ .._._ .... _.J] DAll
A.Ql A.~ _ .__

..

ICLII-B---

I."

"

JJJ
UT12102

I

I£IA
II

DAU

ICll

-::H:~i=_~_
.-_~:--=R. OAlII
::~:I
lOl AlII
__ .____
~~Hm··_ - _._~ ::~:!

1lli:lt~:~_~~ ::~~.
'SY<4~

~II

..JIIIfJ..

~L~----=~;~~_ ~~_

.~31

'»
«

r'-T

tav

2
2

I.C.

t1F
5'
iD

l1'IO~

It

JJO
PAl22Vl0

18

1_~

-~---11---

1\

2

ct

CI

Cit

..17

c::>-JIIl!l

2.7._ ~lK.

CI5

--------1

51

---tr---- - -----~~----.-.- __
.SV

;:: ~.t+lR-.
=-=
rtt --- ---..
l

.av

»57

Wet

::

o-.JR"

1/111

ell

tn

.

L-----!:~:=-~,,,

..--~5~_7.:_i"

..--'~~.........,~
~~~~It

1""''"'''''''--~111

III
III

3

3
CI7

J1.t

PAl22Vl0

II

l..__

-- --..
---

---- - -

---- -

1fi4-~-·-;·~=~=-===-~-=~=--=--

~.~ =~-

~~

----===:-- --

--- . -

~

~

__

Il:i!
.0

---.---

41

4

IIWI

l1~~_~A

-t---iSYS68K/EAGLE-01 C I

B

---=-~=-r

___________
____ ~__

fORCE
COMPUTERS

LAN CONTROL

REV. 1

:::'.:
SHEETS

-'"
I:::
.Z
......
0-

<..J

..:
!

C

•

I
LAJ
-L
(.!)

cC

I
c

LAJ
........
~

- -.:I~

CO
cD
C/')

>

~C/'):;";"""+-_-l

1.;;:::1;

I-Y I'

u

"' 0

J

Iii i

.
......
..,

.
Ip-ill

Ip-ill

N

::II

...
c
.., Q:

1;1~5~15151~~~:~~~: 1:1
1

Sill! i n!i~

...,'"

I

I

Iii

I I i iii
;I;;;I;;;I~;;I;;I;I~;I;
J
!

IUiiili ~
1.:::::1=
--------

liiiiii ~Ar.

-IftIlQ

..

I

....

......

R:"",~ '£

~--------".-

A

I

1

~

C

0

/

I

...

~l..

1-1

.--

I---

-::-

t'+'~+H f" f" +j~+H f" f" II.. #" II" f" 111111T
.. 1-.1.. 1.. ru~C

2

2

--1---

I--

I---

I

\3

3

II
f--

t--

4

4

e

DATE

p

v:---'-

A

_______L

B

-r----------.L.
_____ .__

C

17

INAME

gOI

A S

fORCE
COMPUTERS

ISYS68K/E AGL E-01 CI REV.
BLOCK-Cs

1

I

SHEET II
nOlI II
SHUTS --1

SYS68K1EAGLE-OIC USER'S MANUAL

4. COMPONENT PART LISTS

FOR INTERNAL USE ONLY

Page 55

FORCE COMPUTERS

This page is intentionally left blank.

Page 56

SYS68K1EAGLE-OIC USER'S MANUAL

5. COPIES OF DATA SHEETS

PageS'

FORCE COMPUTERS

This page intentionally left blank

Page 58

SYS68KIEAGLE-OIC USER'S MANUAL

COPIES OF DATA SHEETS
Floppy Disk Controller WD37C65
SCSI Controller MB87031
LAN Controller AM7990
Serial Interface Adapter AM7992B
FLASH EPROM 28FOI0

Page 59

FORCE COMPUTERS

This page is intentionally left blank.

Page 60

FDC37C65C

STANDARD MICROSYSTEMS
CORPORATlON~

;liiiii'
,jCOMPONENT
i
..
35 M¥CUS Blvd
15161 273·3100

~.
F~J

NY 11788
15161 23HOOC

PRELIMINARY INFORMATION

PRODUCTS OIVrSJON

Floppy Disk Subsystem Controller
PIN CONFIGURATION

FEATURES

o

o
o
o
o
o

o
o
o
o
o
o
o
o
o
o

o
o

Supports 1 Mbitlsec Data Rate
Integrates Formatter/Controller, Data Separation.
Write Precompensation, Data Rate Selection. Clock
Generation, and Drive Interface Drivers and Receivers into one Chip
IBM PC/AT Compatible Format (Single and Double
Density)
Provides Required Signal Qualification to DMA
Channel (in PC/AT Mode)
BIOS Compatible; Dual Speed Spindle Drive Support
Enhanced Host Interface:
- Supports 12 MHz. 286 JlP With 0 Wait States
- Capable of Driving 20 lS TTL loads
- Schmitt Trigger Inputs (Except Data Bus and
XTAl)
Compatible With PD8080/85. PD8086, and PD780
(Z-80®) Microprocessors
Internal Address Mark Detection Circuitry
Internal Power Up Reset Circuitry
Provides Direct Interface to Floppy Disk Drives
Provides the Disk Change and Disk Change Enable
Inputs. Allowing Direct Connection of DCHG to the
FDC37C65C
48 mA Sink Drivers and Schmitt Trigger Line Receivers
125. 250. 300. 500. & 1 Mbitlsec Data Rates
Multisector and Multitrack Transfer Capability
User Programmable Track Stepping Rate and Head
Load/Unload Time
Controls up to Four Floppy or Micro-Floppy Drives
Data Transfer in DMA or Non-DMA Mode
Parallel Seek Operations on up to Four Drives

~:"5 ~;
.

"" - '

"0 q 4
;5;(i!h
A;C/~

TC ... 6

I'Q.

ii)2/0$.

:lO
01

.c5iiOSl

02

0S2

OJ

GHO

C)4

lEi

os

12

0&

')

ffiP

0iAc

wr

J!:: ~.35 : -<~

)4: ~~!~

7

~3 ~

8

320

9
'0

)" J

,,

0....
'CIO

.. :oc .

Pac"'a~s;

0r-~r,

'"'9

44-Pin
1 nt'or"..,t

>'Lee or
.on

25:;

"'&

o
o
o
o

o
o
o

:aM)

25::

W!

.:s

24:' =-:--""
23C:~IC~

20

n:

::1\<

2' :

=_cZ

40-P.n :J;P

I=OC37C65C .. ",:J for
FDC]7C6SC

o

m

JO;: :5-

lV
~ "19
'8
:lST
~

.z.. ~J.

29:;~
2e;:~
2~ ~ ;0

0'

iD

;~§ ~~
~~ § ~:a

l

~

PLCC

'or DIP

Integrates Improved Standard Microsystems
FDC92C39 Digital Data Separator Algorithm
Automatic Write Precompensation, Selectable Between 125 or 187 nsec, with disable option
Power-Down Mode For Reduced Power Consumptt:on
On-Chip Clock Generation
Pin-to-Pin Compatible with Industry Standard
WD37C65C
Available in Either 40-Pin DIP or 44-Pin PlCC
XTAl Oscillator Circuits (PlCC)ITTl Clock Inputs
(DIP) Allow for Use Of Non-Standard As Well As
Standard Data Rates
low Power CMOS, +5 V Supply

GENERAL DESCRIPTION
The FDC37C65C is a CMOS device which interfaces a
host microprocessor to the floppy disk drive. It integrates the functions of the Formatter/Controller, Data
Separator, Write Precompensation, Data Rate Selection,
Clock Generation. High Current Drivers, and TTL
compatible Schmitt Trigger Receivers. The FDC37C65C
consists of a microprocessor interface. a microsequencer, and a disk drive interface.
The microprocessor interface of the FDC37C65C
supports a 12 MHz, 286 microprocessor bus without the
use of wait states. For PC and PCI/AT applications. the
device provides qualification of interrupt and DMA
requests.
The disk drive interface of the FDC37C65C directly·
connects to up to four drives. All drive-related outputs
can sink 48 rnA; all host related outputs can sink 12 mAo

All host and drive related inputs except for the data bus
and crystal have internal Schmitt triggers.
The FDC37C65C uses two clock inputs which proYlde the
necessary signals for internal timing. A 16 MHz oscdlator
handles the data rates of 500. 250, and 125 Kblts/sec. a
9.6 MHz oscillator handles the 300 Kbits/sec data rate
used in PC/AT designs. A 32 MHz oscillator is used for
the 1 Mbitlsec data rate. Internal crystal oscillator CirCUits
may be used with the 44-pin PlCC package. The 40-pm
DIP requires TTL clock inputs.
The FDC37C65C may be used in applications uSing two
speed disk drives, such as AT compatible systems
• IBM and PC/AT are registered Irademarks of Internaliona' 8us.".u
Machines Corporation.
Z-80 is a regil'ered Irademar" or :.toq
Incorporaled,

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN CONFIGURATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

1

GENERAL DESCRIPTION

. . . . . . . . . . .' . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . ,.....

1

DESCRIPTION OF PIN FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3

SYSTEM DESCRIPTION

8

...................................................•..
.........................................

8

DRIVE INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,

8

FUNCTIONAL DESCRiPTiON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .- . . . . . . . . . . ..

8

HOST INTERFACE LOGIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

8

JNTERNAL REGISTERS

................................................

9

Data Rate Selection Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

9

MICROPROCESSOR INTERFACE

Main Status Register

............................................

10

Status Registers 0-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11

Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14

Digital Output Register . . . . . . . ..

. .............................. .

14

MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14

Base Mode

.................................................. .

PC/AT/EISA Mode

............................................. .

SpeCIal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14

14

15

................................................. .

1.5

RESET LOGiC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16

CLOCK GENERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

17

COMMAND SEQUENCE

...............................................

17

INSTRUCTION SET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

20

FUNCTIONAL DESCRIPTION OF COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29

POLLING ROUTINE

OPERATIONAL DESCRIPTION . . . . . . . . . . . .

~

...... : . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

36

MAXIMUM GUARANTEED RATINGS .. ',' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

36

DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

36

TIMING DIAGRAMS

37

..................................................

2

DESCRIPTION OF PIN FUNCTIONS
PLCC
PIN NO.

DIP PIN
NO.

7-14

7-14

1

NAME

SYMBOL

Data 0-7

00-07

I n put/Output.
The data bus connection used by the host
microprocessor to transmit data to and from the FDC37C65C.
These pins are in a high-impedance state when not in use.

1

Read

~.

Input. This active low signal is issued by the host microprocessor to indicate a read operation. A low pulse on this input
when the FDC37C65C is selected enables data from the Buffer
or Status Register onto the data bus for reading by the host.

2

2

Write

~

Input. This active low signal is issued by the host microprocessor to indicate a write operation. A low pulse on this input
when the FDC37C65C is selected enables data from the data
bus to be written into the FDC37C65C.

3

3

Chip
Select

CS

Input. This active low signal issued by the host microprocessor
allows data transfers to occur.

4

4

Address 0

AO

Input. This host processor signal determines whether data or
status information will appear on the Data Bus.

Direct
Memory
Access
Request

DMA

Output . This active high signal is a DMA request for byte
transfers of data. This signal is cleared when the host responds with the L5ACK signal going low. This signal is normaUy
driven in the Base Mode. When the FOC37C65C is in the
Special or PC/AT mode, this pin is three-stated and is enabled
by the DMAEN signal from the Digital Output Register.

DESCRIPTION

HOST PROCESSOR INTERFACE

. 15

15

5

5

L5MA Acknowledge

L5ACK

Input. A low level on this pin indicates a response by the host
to a DMA request. It is used by the DMA controller to transfer
data to or from the FDC37C65C. Logical equivalent to CS and
AO = logic "1". In Special or PC/AT mode, this signal is qualtfied by DMAEN from the Digital Output Register.

6

6

Terminal
Count

TC

Input. This active high signal indicates to the FDC37C65C that
data transfer is complete. In Base Mode. TC will be qualified
by 'C5ACK only in DMA operations. In non-DMA (Programmed
I/O) operations. ~ and the R1J and W1{ signals are used as a
gating function. In Special or PC/AT mode, TC will always be
qualified by ~ (whether in OMA or non-DMA operations}.
but will only be qualified by L5ACK if DMAEN from the Digital
Output Register is a logic "1".
In PC/AT mode. non-DMA
operations will occur successfully but will cause an abnormal
termination error at the completion of a command.

16

16

Interrupt

IRQ

Output. This interrupt indicates the completion of command
execution or data transfer requests (in non-DMA operations).
This signal is normally driven in the Base mode. When the
FDC37C65C is in the Special or PC/AT mode, this pin is threestated and Is enabled by the oMAEN signal from the Digital
Output Register.

18

17

[oad r5igital (5utput
RegIster

~

Input. Active low Digital Output Register load enable. When
~ and W1{ are low, the Data Bus is latched into the oigitar
Output Register.

19

18

Loaa L5ata
Rate Selectlon
Register

~

Input. This active low signal allows access to the Data Rate
Selection Register. When ~ and wR are low. the two
LSB's of the Data Bus are latched into this register. Wtlen
~. Jrn'. and DCHGEN are low, the ~ input status is
carried on bit 07 of the Data Bus. while bits 00-06 remain in
the high impedance state.

3

DESCRiPTION OF PIN FUNCTIONS

PlCC
PIN NO.

DIP PIN
NO.

NAME

SYMBOL

20

19

Reset

RST

DESCRIPTION
Input. This active high signal resets the FDC37C65C. When
RST occurs, the FDC37C65C defaults to Base Mode and the
data rate is defaulted to 250K MFM (or 125K FM, code depen.
dent). When RST is active, the high current driver outputs to
the disk drive are disabled.
DRIVE INTERFACE

21

20

Read Disk
Data

29

26

Write

mm
~

Output. This active low high current driver allows current to
flow through the write head. It becomes active just prior to
writing to the diskette.

fwD:

f Ot!tput. !hi: aetivG lo," high Ci.ffrent drtv6r provides the encoded data to the di$k drive. Each falling edge causes a flux
transition on the media.

AS

Output. This high current output selects the floppy disk side for
reading or writing. A logic "1" on this pin means side 0 will be
accessed, while a logic "0" means side 1 will be accessed.

Enable

t

30

J

27

I Wrat&
-Data

I

Input. Raw serial bit stream from the disk drive. Each falling
edge represents a flux transition of the encoded data.

28

25

Head
Select

31

28

Oirection
Control

32

29

Step Pulse

~

Output. This active low high current driver issues a low pulse
for each track-to-track movement of the head.

40

N/A

Disk
Change

L>CHG

Input. This active low input senses from the disk drive that the
drive door is open or that the diskette has possibly been
changed since the last drive selection.

';7

Nii-.

I
r

lil~K

C~ang.e

nmc

IOC~GEN

~nab'e

Output. This high current output determines the direction of the
head movement. A logic "1" on this pin means outward motion,
while a logic "0" means inward motion.

f Jnput·n7f~'.~ .:~Ive ",10'11

input e~ab':S the L5CRG. input s~atu5
• on~o _., ...... r. .. ~ 3 ,~d of ~he Dab Rate Selection Register.
f This signat ;$ conn~cted to an internal puU-up resistor.

33

30

Drive
Select 1

r5S1

Output. This is an active low output. When the FDC37C65C is
in the PC/AT/EISA Mode. a logic "0· on DSEl and a logic "1"
on MOEN 1 from the Digital Output Register will cause O'ST to
enable the Drive 1 interface. When the FDC37C65C is in the
Base Mode or the Special Mode. C5'S'T is number 1 of the four
decoded Unit Selects. as specified in the device command. and
the Digital Output Register has no effect.

35

32

Drive
Select

~

Output. This is an active low output. When the FDC37C65C is
in the PC/AT Mode. a logic ·0" on DSEl and a logic ·1" on
MOEN2 from the Digital Output Register will cause D'S} to
enable the Drive 2 interface. When the FDC37C65C is in the
Base Mode or the Special Mode. this output is number 2 of the
!~!,!!' de~e~ !J~~t So~:t:). =~ ;pec~f~d in the device command,
ana the Digital Output register ha3 no effect.

M01JOS3

Output. This is an active tow output. When the FDC37C65C is
in the PCiAT MOde, a logiC '"1" on MOEN1 from the Digital
Output Register will cause this output to go low. thereby acting
as the Motor-On Enable for Drive 1. When the FDC37C65C is
in the Base Mode or the Special Mode. this output is number 3
of the four decoded Unit Selects, as specified in the device
command. thereby acting as drive select 3, and the Digital
Output Register has no effect.

36

33

2

. Motor

0rl17
Drive
Select

3

4

DESCRIPTION OF PIN FUNCTIONS
PLCC
PIN NO.

DIP PIN
NO.

37

34

NAME

SYMBOL

DESCRIPTION

Motor

M02/DS4

Output. This is an active low output. When the FDC37C65C is
in the PC/AT Mode, a logic "1" on MOEN2 from the Digital
Output Register will cause this output to go low. thereby acting
as the Motor-On Enable for Drive 2. When the FDC37C65C is
in the Base Mode or the Special Mode, this output IS number 4
of the four decoded Unit Selects, as specified in the device
command. thereby acting as drive select 4, and the Digital
Output Register has no effect.

0"n2i
Drive
Select 4

38

35

Head
Loaded

HOl

Output. This active low high current driving signal causes the
head to be loaded against the media in the selected drive.

39

36

Reduced
Write
Current!
Revolutions Per
Minute

RWC/RPM

Output. This active low signal occurs when tracks greater than
28 are being accessed. and the inner track location has caused
increased bit density. This signal, valid in the Base Mode and
the Special Mode. indicates that write precompensation is
necessary. In the PC/AT mode. this signal may be used to
select a 300 RPM spindle rate on two speed drives' when 250
Kbps MFM is selected.

41

37

Write
Protected

42

38

Track

43

39

Index

27

24

Precompensation
Value

24

22

Drive
Type

N/A

23

CLOCK 1

CLK1

16 or 32 MHz TTL level clock input for all standard data rates.
The frequency should be accurate to within 0.1% and may have
a 40% or 60% duty cycle.

N/A

21

CLOCK 2

ClK2

TTL level clock input for non-standard data rates. The frequency Is selected from the Data Rate Selection Register in
Table 1.

25.26

N/A

Crystal 1.
Crystal 1

XTArf.
XTAL1

An external 16 MHz or 32 MHz series resonant crystal should
be connected to these pins for all standard data rates. If an .
external 16 MHz or 32 MHz TTL clock is used instead. it should'
be connected to XTAL 1 and XTA[1 should be left floating.

Crystal 2.
Crystal 2

~.
XTAL2

An external series resonant crystal should be connected to
these pins for all non-standard data rates. If an external TTL
clock is used instead. it should be connected to XTAL2 and
~ should be left floating.

00

wrs
moo
mx
PCVAl

- DRV

Input. This active low Schmitt Trigger input senses from the
disk drive that a disk is write protected.
Input. This active low Schmitt Trigger input senses from the
disk drive that the head is positioned over the outermost track.
Input. This active low Schmitt Trigger input senses from the
disk drive that the head is positioned over the beginning of a
track, as marked by an index hole.
Input. The level on this pin determines the amount of write
precompensation to be used on the inner tracks of the diskette. :
logic "1" programs the value of 125 ns; Logic "0" programs
187 ns. When precompensation is disabled. this pin has no
effect. This input has an internal pull up resistor.
Input. This input is used to indicate the drive type being used.
A logic "0" on this input indicates a two speed spindle motor, in
which case the second clock input should be grounded. This
signal is connected to an internal pull-up resistor.
MISCELLANEOUS

22.23

N/A

44

40

Power

Vee

+ 5 Volt supply pin.

34

31

Ground

GND

Ground pin.

5

Vee

•

FOC37C65C

I

(/)

I

:::>

i
i

0

.

1-..
i

!

0::

I

w

t

0

..
..

0::

I

Q..

o.

Ct:

OSl
-

DS2
DS3/MO 1
-DS4/M02
HDL
RWC/RPM

14

U
~

14I------:~! ~:~
I

t(/)

0

~

i

I

~

WE
WD
HS
DIRC
STEP'

RD
!
WR
I
AD
Il-4----------i1
..
DMA
I
,. DACK

U

!

I

'.j

!

(/)
(/)

I

Vee

!/

CD

!

I

,.

I

.-.

-

\

I

I

0:::

w O

>t_U

.

o:::W

OZ
Z

I

Vee

I

wO
Q..u

>-

t-w

oU
I.()«

I

ADDRESS
DECODING
CIRCUITRY

r--------...~II
~I

CS

I

LDOR

! 150
• DCHG

, Vee

•

WP

• Vee

TROD

16 MHz

••

9.6 MHz
15 pF

!

T

Vee

150

DRV

lOX

XTAL2·

• DCHGEN

XTAL2·

GND

T. T T

47 pF

~

68 pF
56 pF

• These s;gnals exist only for PLCC package .

•• 32 MHz for 1 Mbif.

FIGURE 1 - TYPICAL SYSTEM BLOCK DIAGRAM

6

(/)~
:

i

150

PCVAL

«0:::

Z

150

Vee

~u...

Vee

-i

07

07 <

DO

,1
'J

:-::====-~=-=-=-=-=-=-=-=-=-~=-=-=-=-=-=-=-=-=-=-=-~=-=-=-=-=-=-=-=-=-~~I"4~----·-"
~;
!!
!
i
~ ,L
il
r.
~

v~

I DATA

i

U

I
I

!

I

R

I
.

REGISTER

-{ ~

}
I
I

I
I

DIGITAL
OUTPUT
REGISTER

••

I

,

I

tI

!

j
I

I

~

II I

I

II

I

I

I

I

II

DCHGEN
REGISTER

i

I

j

!
i

;r

'7

:!

.....

DRV ------------------~-~

L - -_ _ _ _~• •

t..---t=:__________

I--------------~~~

SCLK

L---

a

CRYSTAL

ClK1· (XTAL 1··)

-------I-~

OSCILLATOR

CLK2· (XTAL2··)

-------I-~

X2

(XTAL2··)

-

PCVAL

......

-11-----------

-

WO

...---~--

DIGITAL
DATA
~ SEPARATOR ....

(XTAL1··)

WE

• Th.se signols .:wlst only In DIP packag•
•• ihese slgnols .:wlst only in PlCC packoge

FIGURE 2 - INTERNAl BLOCK DIAGRAM

7

ROD

SYSTEM DESCRIPTION
The system block diagram in Figure 1 illustrates a
complete implementation of the FOC37C6SC used in a
floppy disk drive system. The FOC37C65C provides
simple interfacing to both the microprocessor and the
drive.

sor. The Data Register fS used in data transfers with the
drive during Read and Write operations, and holds the
command blocks issued by the microprocessor and the
results after the command is executed. The Digital
Output Register provides the Motor On and Drive Select
signals and the DMA Enable qualifier for the DMA and
IRQ outputs.

MJCROPROCESSORJNTERFACE
The left half of Figure 1 illustrates a typical FDC37C65C
interface to the microprocessor. It consists of an 8-bit
data bus and a control bus: All signals are directly
connected to the host, eliminating the need for external
circuitry. All inputs to the FDC37C65C (except for the
data bus) are Schmitt triggers and the outputs to the
host are able to sink 12 mA, ThR F=DC37C65G ~o!'!tai~~
the fotlowing intema[ registers for tnte=rlaci.ng to the host
microprocessor: Data Rate Selection Register, Main
Status Reglster. Data Register. and Digital Output
Register. The Data Rate Selection Register selects the
data rate for internal clock generation and synchronization of disk data transfers. The Main Status Register
contains information related to the status of the drives
and provides handshaking functions for the microproces-

DRIVE INTERFACE
The right half of Figure
illustrates a typical
FOC37C65C interface to up to four drives. All signals
are directly connected to the drives, eliminating the
need for external circuitry. All inputs to the FDC37C65C
~r~ Schm!tt tr:;;~:'z and ~h~ output:; sra open-drain, 48
mA drivers. The FDC37C65C contains the Standard
MicrosY3tems FDC92C39 afgorithm. which provkies Data
Se!Jaration as well as Aytomatic Write Precompensation.
The FDC37C65C also provides the DCRG and DCHGEN
signals, which provide the option of conne:.: ·:ng the
(jCRG signal directly to the FDC37C65C so that the
~ status may be supplied to the host microprocessor via 07 of the data bus.

FUNCTIONAL DESCRIPTION
Refer to Figure 2 for Internal Block Diagram of the
FOC37C65C.

as the interrupt signal. If a Write command is in process,
then the Write signal performs the reset to the interrupt.
The timing parameters mentioned above will double for
mini floppy data rates.
After an interrupt in the
f1on-OMA Mode, the Main Status Register must be
axamined to d,~term-in'9- !he C3U3'B-, since it could be a
data tntemJp~ or a cQmmand termination interrupt. either
normal or abnormaL In the DMA Mode. no interrupt
signals occur during the Execution Phase. Instead. a
DMA Request is generated and the DMA controller
responds with a DMA Acknowledge and either a Read or
a Write, which clears the DMA Request. After the
completion of the Execution Phase or the EOT sector
has been read or written. an interrupt will occur,
signifying the beginning of the Result Phase. The
reading of the first byte of data from the Data Register
clears the interrupt.

HOST INTERFACE LOGIC
The internaf registers are used chiefly in writing command3 to, and:resdmg $tatu~ from, the. FOC37C65C. in
th:e ~nterlacing of the internal regi:.sters ~o ttls host, the
user must keep in mind a few considerations. During
the Command Phase of a command, the Main Status
Register must be read before each byte of the command
word is written into the data register to ensure that bits
06 and 07 are logic "0" and "1 ", respectively. During
the Result Phase of a command, the Main Status
Register must be read before each result byte from the
data register is read to ensure that bits 06 and 07 are
both logic "1 to. The user should ensure that 12 ,",s
elapses before each access of the Main Status Register "'
by the CPU. To avoid waiting 12 ,",s before each access
to the Main Status Register in a Command Phase, the
user may save time by polling 06 and 07 of the Main
.5iaiua Register lor tne appropt'tate tHt settings. When
the correct bit settings appear. the FOC37C65C is ready
for commands. No access of the Main Status Register
;s iiac6~~ary in ihe execution phase of a command.
During the execution phase, each receipt of a data byte
from the drive is indicated by an interrupt signal on the
IRQ pin when the FDC37C65C is in the non-DMA mode.
The generation of a Read or Write signal clears the
interrupt and outputs the data onto the data bus. If the
processor cannot respond to the interrupts quickly
enough (every 13 ,",S for MFM and 27 ,",S for FM), then
it may poll the Main Status Register and bit D7 functions

In PC/AT use, since non-OMA host transfers are not
normally used, the FOC37C65C will successfully completf!! c;:omm~!"Ids blJt wH! always give abnormal termination error statu.s. since tne TC signal is qualified by the
DACK signal.
The ltrJ or ViR signalS should be asserted while DACK
is true and the ~ signal is gated with RlJ and ~
during programmed I/O operations. ~ has no effect
during DMA operations. If the non-OMA Mode is being
used, the tJACK signal should be pulled up to VCC.
During the Result Phase of a command, all bytes from
the Data Register must be read in order to successfully
complete the command, and the FDC37C65C will not
accept a new command until all bytes have been read
8

The bytes in the Command Phase and the Result Phase
must be written and read in the exact order as seen in
the Commands section of this document. No shortening
of the phases is allowed. The last byte sent to the
FDC37C6SC in a Command Phase causes the Execution
Phase to automatically begin and when the last data
byte is read out in the Result Phase, the command is
automatically ended, making the FDC37C6SC ready for
a new command.

INTERNAL REGISTERS
The FDC37C6SC contains eight internal registers which
facilitate the interfacing between the host microprocessor and the disk drive. The eight registers consist of the
. Data Rate Selection Register, the Main Status Register,
Status Registers 0-3, the Data Register, and the Digital
Output Register. Table 1 shows the bit combinations
required to access the registers. Combinations other
than the ones shown below are illegal.

Table 1 - Register Accesses
DCHGEN

CS

AO

LDCR

LDOR

RD

WR

X

1

X

1

0

1

X

0

0

1

1

X

0

1

1

X

0

1

0

1

X

FUNCTION

ADDR

0

Write Digital Output Register

3F2H

0

1

Read Main Status Register

3F4H

1

0

1

Read Data Register

3FSH

1

1

1

0

Write Data Register

3FSH

X

0

1

0

1

Read

1

X

0

1

1

0

Write Data Rate Selection Register

X

0

0

1

1

1

0

Illegal-

X

X

X

X

X

0

0

Illegal

OCHG Register

3F7H
3F7H

Status Registers 0-3 are available only in the result phase of a command and may be read only after the
completion of the command.

· cs =~ = 0 is allowed when AO = 0, the

RST pin is inactive, and bit 2 of the Digital Output Register
(Software Reset disabled). This places the FDC37C6SC into the Power Down Mode.

=1

the Data Rate Selection Register is not being used, the
data rate is determined by the supplied clock or crystal.
The frequency must be 64 times the desired MFM data
rate, up to a maximum frequency of 32 MHz. Therefore,
the maximum data rate that can be used without the use
of the Data Rate Selection Register is 250 kbits/sec or
SOOk for 32 MHz. Refer to Table 2 for manipulation of
the Data Rate Selection Register.

Data Rate Selection Register
The Data Rate Selection Register provides support logic
that latches the two LS8's of the data bus upon
receiving ~ and WR. These bits are used to select
the desired data rate which. in turn. controls the internal
clock generation. When the data rate Is switched. the
clock is de-glitched to allow for continuous operation. If

9

Table 2A - Data Rate Selection Register - 16 MHz
DB1

DBO

DRV

I

Encoding Scheme

Data Rate
(kbits/s)

RPM
(in PCIATI
EISA Mode)

I
0

0

X

MFM

500

1

0

0

X

FM

250

1

0

1

0

MFM

250

0

0

1

1

MFM

300

0

1

0

X

MFM. RST Default

250

1

1

0

X

FM. RST Default

125

1

x

FM

125

o

1

Table 28 - Data Rate Selection Register - 32 MHz
DB1

080

DRV

Encoding Scheme

Data Rate
(bits/s)

RPM
(in PC/AT!
EISA Mode)

0

0

X

MFM

1M

1

0

0

X

FM

SOOk

1

0

1

0

MFM

500k

0

0

1

1

MFM (9.6 MHz XTAL)

300k

0

-1

~

SCCt

"1

t .

,

{)

1

I

L
i

t

X

,

X

I
i

X

~

MFM.

R~T D~fcu.jlt

;

FrAt RST· Default

t

250k
1"

~M

I

2S0k

j

0

The FOe supports 150 kbps FM data transfer as shown in table 2C. This data rate is selected by driving CLK1 or
XTAL1 with 9.6 MHz.
Table 2C - Data Rate Selection Register - 1501300 kbps Option
081

080

ORV

Encoding Scheme

Data Rate
(kbits/s)

RPM
(in PC/ATI
EISA Mode)

0

0

X

MFM

300

1

0

0

X

FM

150

1

The Write Precompensation may be disabled in the
PC/AT/EISA mode by writing a logic high to bit 2 of the
Control Register. Please note that a hardware reset

wiH reset bit 2 to a logic low. re-enabling Write Precompensation.

Main Status Register

data between the microprocessor and the FDC37C65C.
That is, Status Registers 0-3 may be read only after the
completion of a command and provide no assistance in
the transfer of data between the microprocessor and the
FDC37C65C. Each time the Main Status Register is
accessed, the microprocessor should wait 12 ~s if 500

The Main Status Register is an 8-bit register that
contains the status information of the FDC37C65C, and
may be accessed at any time. Only the Main Status
Register may be accessed to facilitate the transfer of

10

kbits/sec MFM is selected as the data rate. 6 ~s if 1
Mbitlsec is selected. and 24 ~s if 250 kbits/sec MFM is

selected. Refer to Table 3 for the contents of the MGltlm
Status Register.

Table 3 - Main Status Register
BIT NO.

BIT NAME

SYMBOL

DESCRIPTION
:

A high

0

FDD 0 Busy

DOB

level on this bit indicates that drive 0 is in the Seek Mode and :
that the FDC37C65C will not accept READ or WRITE commands. •
!

1

FDD 1 Busy

D1B

A high level on this bit indicates that drive 1 is in the Seek Mode and:
that the FDC37C65C will not accept READ or WRITE commands.

2

FDD 2 Busy

D2B

A high level on this bit indicates that drive 2 is in the Seek Mode and:
that the FDC37C65C will not accept READ or WRITE commands.

3

FDD 3 Busy

D3B

A high level on this bit indicates that drive 3 is in the Seek Mode and ~
~
that the FDC37C65C will not accept READ or WRITE commands.

4

FDC Busy

CB

A high level on this bit indicates that a READ or WRITE command is PIm ,

1

i

progress and that the FDC37C65C will not accept any other commana.

1
\

5

Execution
Mode

EXM

A high level on this bit indicates that the FDC37C65C is in the ExecutKlm
Phase in Non-DMA Mode. When this bit goes low. the Execution Phase
has ended and the Results Phase has begun. This bit operates only I'm
the Non-DMA Mode.

I
;

;

6

Data

010

A high level on this bit indicates that the direction of data transfer IS
from the Data Register to the microprocessor. A low level on th is ~t
indicates that the direction of data transfer is from the microprocessor. t!:l
the Data Register.

•

7

Request

ROM

A high level on this bit indicates that the Data Register is ready to sen-an
or receive data to or from the microprocessor. Both the 010 and th'e
ROM bits should be used to perform the "ready" and "direction" handshaking functions to the host.

.

.'

• Note: A write to the Main Status Register (CS = WR = 0) when bit DBO = 1. bit DB2 of the Digital Output
Register = 1 and AO RST O. will place the FDC37C65 in the Power Down Mode.

=

=

Status Registers 0-3
completing a command. The command that has treen.
executed determines which of the Status Registers • •
be read. Refer to Tables 4-7 for the contents of Stalbit;s
Registers 0-3.

Status Registers 0-3 are each 8 bit registers that contain
status information on the FDC37C65C and are available
only in the Result Phase and may be read only after

11

T abre .. - Status Regrater 0
BIT NAME

BIT NO.

r

SYMBOL

DESCRIPTION

0

Unit Select 0

USO

Thi! flag i! used to indicate a Drive Unit Number at interrupt.

1

Unit Select 1

US1

This flag is used to indicate a Drive Unit Number at interrupt.

2

Head Select

HS

This flag is used to indicate the state of the head at interrupt.

3

Not Ready

NR

This bit will always be a logic "0", since Drive Ready is always presumed
to be true.

4

Equipment
Check

EC

A high level on this bit indicates that the Track 0 signal has failed to
occur after 77 step pulses (Recalibra~e Command).

5

Seek End

SE

A high level on this bit indicates that the FDC37C65C has completed the
seek command.

6,7

r-~_

f ~w~

I

IC

Interrupt
f

I

The four combinations of these bits indicate four different situations:

, 7

~

I~

I

1 0
1 1

Normal. Termination of command wa~ completed and property
executed.
Abnorm~~ T.NJl-L30 COOES
PHASE

RIW
07

Command

W

Result

R

REMARKS

DATA BUS

I OS I 05 I D4 I 03 I 02 1 01 1 DO
Invalid Command Codes
(NoOp • FDC goes into Standby State)

Invalid Codes

STO

5TO

= 80H

SOFTWARE RESET
PHASE

RIW

OATABUS

07 J OS
COMMAND

W

0

0

REMARKS

J 05 1 D4 J 03 I 02 I 01 I DO
1

1

0

1

1

0

Command Codes
Same as hardware reset

Execution

28

FUNCTIONAL DESCRIPTION OF COMMANDS
Read Data

the data from the next sector is read and output on the
data bus. This continuous read function is called a
"Multi-Sector Read Operation-. The Read Data Command may be terminated by the receipt of a Terminal
count signal. TC should be issued at the same time that
the I5ACK for the last byte of data is sent. Upon receipt
of this signal. the FOC37C65C stops outputting data to
the processor, but will continue to read data from the
current sector, check CRC (Cyclic Redundancy Count)
bytes, and then, at the end of the sector, terminate the
Read Data Command.

A set of nine (9) byte words are required to place the
FDC37C65C into the Read Data Mode. After the Read
Data command has been issued, the FDC37C65C loads
the head (if it is in the unloaded state)" waits the
specified head settling time (defined in the Specify
Command). and begins reading 10 Address Marks and
10 fields. When the current sector number (MRM) stored
in the 10 Register (lOR) compares with the sector
number read off the diskette. then the FDC37C65C
outputs data (from the data field) byte-to-byte to the
main system via the data bus.

The amount of data which can be handled with a singfe
command to the FDC37C65C depends upon MT (MultiTrack), MF (MFM/FM), and N (Number of Bytes/Sector).
Table 13 shows the Transfer Capacity.

After completion of the read operation from the current
sector, the Sector Number is incremented by one, and

TABLE 13 - TRANSFER CAPACITY
Multi-Track
MT

MFM/FM
MF

Bytes/Sector
N

0
0

0
1

00
01

1
1

0
1

00
01

0
0

0

01
02

1

0

1

1

0
0

0

02

1

03

1
1

0
1

02
03

1

Maximum Tranafer Capacity
(Bytes/Sector) X (Number of
Sectors)

01
02

= 3,328
= 6,656
(128) x (52) = 6,656
(256) x (52) = 13.312
(256) x (15) = 3,840
(512) x (15) = 7,680
(256) x (30) = 7,680
(512) x (30) =15,360
(512) x (8) = 4,096
(1024) x (8) = 8.192
(512) x (16) = 8,192
(1024) x (16) =16.384
(128) x (26)
(256) x (26)

The -multl-trackM function (MT) allows the FOC37C65C
to read data from both sides of the diskette. For a
particular cylinder. data will be transferred starting at
Sector L, Side 0 and completing at Sector l, Side 1
(Sector L Is the last sector on the side). Please note
that this function pertains to only one cylinder (the same
track) on each side· of the diskette.

Final Sector Read
from Diskette
26 at Side 0
or 26 at Side 1
26 at Side 1
15 at Side 0
or 15 at Side 1
15 at Side 1
8 at Side 0
or 8 at Side 1
8 at Side 1

At the completion of the Read Data command. the head
is not unloaded until after the Head Unload Time Interval
(specified in the Specify Command) has elapsed. If the
processor issues another command before the head
unloads, then the head settling time may be saved
between subsequent reads. This time out is particulariy
valuable when a diskette is copied from one drive to
another.

=

When N O. the OTl defines the data length which the
FDC37C65C must treat as a sector. If OTL is smaller
than the actual data length In a Sector, the data beyond
OTl in the Sector is not sent to the Data Bus. The
FDC37C65C reads (internally) the complete Sector
performing the CRC check, and depending upon the
manner of command termination, may perform a
Multi-Sector Read Operation. When N is non-zero. then
DTL has no meaning and should be set to FF Hexadecimal.
.

If the FOC37C65C detects the Index Hole twice without
finding the right sector. (indicated in -RIO). then the
FDC37C65C sets the NO (No Data) flag in Status
Register 1 to a 1 (high). and terminates the Read Data
Command. Status Register 0 also has bits 7 and 6 set
to 0 and 1 respectively.
After reading the 10 and Data Fields in each sector, the
FDC37C65C checks the CRC bytes. If a read error is

29

detected (incorrect GRG in fD field). the FDC37C65C
sets the DC (Data Error) flag in Status Register 1 to a 1
(high). and if a CRG error occurs in the Data Field the
FOC37C65C also sets the 00 (Data Error in Data field)
flag in Status Register 2 to a 1 (high), and terminates
the Read Data Command. Status Register 0 also has
bits 7 and 6 set to 0 and 1 respectively.

During disk data transfers between the FDC37C65C and
the processor. via the data bus. the FDC37C65C must
be serviced by the processor every 27 ,",S in the FM
Mode. and every 13 ~s in the MFM Mode. or the
FDC37C65C sets the OR (Over Run) flag in Status
Register 1 to a 1 (high). and terminates the Read Data
Command.

If the FDC37C65C reads a De1eted Data Addres; Mark
from the diskette. and the SK 'bit (bit 05 in the first
Command Word is not set (SK = 0) then the
FDC37C65C sets the CM (Control Mark) flag in Status
Register 2 to a 1 (high). and terminates the Read Data
Command~ after reading all the data in the Sector. If SK
1. the FDC37C65C skips the sector with the Deleted
Data Address MarK and reads- ihe next sector. Tne eRC
bits in the defeted data fleld are not checked when SK
= 1.

If the processor terminates a read (or write) operation in
the FoC, then the 10 Information in the Result Phase is
dependent upon the state of the MT bit and EOT byte.
Table 14 shows the value for C. H. R. and N. when the
processor terminates the Command.

=

Table 14 - 10 Information in Processor - Terminated Command
MT

HO

0
f

I'

•
1

Notes:

C

H

R

N

{)

less than EOT

NC

NC

R + 1

NC

0

Equal to EOT

C+1

NC

R = 01

NC

1

less than EOT

NC

NC

R + 1

NC

,

cqu~~ iu ~C7

- ..
",-,Vi

NC

i

R:.: 01

NC

0,

Less than EOT

NC

NC

,t

R+l

NC
.-NC

~

I

10 I nformation at Result Phase

Final Sector Transferred to
Processor

,..

i
I

0

Equal to EOT

NC

lSB

R = 01

1

less than EOT

NC

NC

R+1

NC

1

Equal to EOT

C+1

lSB

R = 01

NC

1. NC (No Change): The same value as the one at the beginning of command execution.
2. lSB (least Significant Bit): The least significant bit of H is complemented.

this "Multi-Sector Write Operation" until the issuance of
a Terminal Count signal. If a Terminal Count signal is
sent to the FDC37C65C. it continues writing into the
current aector to complete the data field. If the Terminal
Count signal, is recaived while a data field is being
written. then the remainder of the data field is filled with
00 (zeros).

Write Data
A set of nine (9) bytes are required to set the
FDC37C65C into the Write Data mode. After the Write
Data command has been issued. the FOC37C65C loads
the head Of it is in the unloaded 3tate). waits tha
specified Head Settling Time (defined in the specify
command). and begins reading 10 Fields. When all four
bytes loaded during the Command (C. H. R. N) match
the four bytes of the 10 field from the diskette. the
FDC37C65C takes data from the processor byte-by-byte
via the data bus. and outputs it to the drive.

The FDC37C65C reads the 10 field of each sector and
checks the CRC bytes. If the FDC37C65C detects a
read error (incorrect CRC) in one of the 10 Fields. it sets
the DE (Data Error) flag of Status Register 1 to a 1
(high), and terminates the Write Data Command. Status
Register 0 ,also has bits 7 and 6 set to 0 and 1 respectively.
'

After writing data into the current sector, the Sector
Number stored in lOR- Is incremented by one, and the
next data field is written. The FoC37C65C continues
')1'\
0.1\1

The Write Command operates in much the same manner
as the Read Command. The following items are the
same, and one should refer to the Read Data Command
for details:

(high), and terminates the command. Status Register 0
has bits 7 and 6 set to Oand 1 respectively. ,

Transfer Capacity
EN (End of Cylinder) Flag
NO (No Data) Flag
Head Unload Time Interval
10 Information when the processor terminates command (see Table 2)
Definition of DTl when N 0 and when N .. 0

The READ 10 Command is used to give the present
position of the recording head. The FDC37C65C stores
the values from the first 10 field it is able to read. If no
proper 10 Address Mark is found on the diskette before
the INDEX HOLE is encountered for the second time.
the MA (Missing Address Mark) flag in Status Register
1 is set to a "1" (high), and if no data is found then the
NO (No Data) flag is also set in Status Register 1 to a
"1· (high). The command is then terminated with Bits 7
and 6 in Status Register 0 set to "0· and "1"
respectively. During this command there is no data
transfer between FDC37C65C and the CPU except
during the result phase,

Read 10

=

In the Write Data mode, data transfers between the
processor and FDC, via the Data Bus, must occur every
27 JlS in the FM mode, and every 13 JlS in the MFM
mode. If the time interval between data transfers is
longer than this, the FDC37C65C sets the OR (Over
Run) flag in Status Register 1 to a 1 (high), and terminates the Write Data Command. Status register 0 also
has bit 7 and 6 set to 0 and 1 respectively.

Format a Track
The Format Command allows an entire track to be
formatted. After the INDEX HOLE is detected. Data is
written on the Diskette. Gaps, Address Marks, 10 Fields
and Data Fields, all per the IBM System 34 (Doubie
Density) or System 3740 (Single Density) Format are
recorded. The particular format which will be written is
controlled by the values programmed into N (number of
bytes/sector). SC (sectors/ cylinder), GPL (Gap Length).
and 0 (Data Pattern) which are supplied by the processor during the Command Phase. The Data Field is filled
with the Byte of data stored in 0, The 10 Field for each
sector is supplied by the processor; four data requests
per sector are made by the FOC37C65C for C (Cylinder
Number), H (Head Number), R (Sector Number) and N
(Number of Bytes/Sector). This allows the diskette to be
formatted with nonsequential sector numbers, if desired.

Write Deleted Data
This command is the same as the Write Data Command
except a Deleted Data Address Mark is written at the
beginning of the Data Field instead of the normal Data
Address Mark.
Read Deleted Data
This command is the same as the Read Data Command
except that when the FDC37C65C detects a Data
Address Mark at the beginning of a Data Field and SK
0 (low), it will read all the data in the sector and set
the CM flag in Status Register 2 to a 1 (high), and then
terminate the command. If SK
1, the FDC37C65C
skips the sector with the Data Address Mark and reads
the next sector.

=

=

The processor must send new values for C, H, R, and N
to the FOC37C65C for each sector on the track, If the
FDC37C65C is set for DMA mode, it will issue 4 OMA
requests per sector. If it is set for interrupt mode, it WIll
issue four interrupts per sector and the processor must
supply C, H, Rand N load for each sector. The contents of the R register are incremented by one after
each sector is formatted. The R register therefore
contains a value of R when it is read during the Result
Phase. This Incrementing and formatting continues for
the whole track until the FDC37C65C encounters the
INDEX HOLE for the second time, whereupon It
terminates the command.

Read a Track
This command is similar to the READ DATA Command
except that this is a continuous READ operation where
the entire data field from each of the sectors are read.
Immediately after encountering the INDEX HOLE, the
FDC37C65C starts reading all data fields on the track,
as continuous blocks of data. If the FDC37C65C finds
an error in the 10 or DATA CRC check bytes, it continues to read data from the track. The FDC37C65C
compares the 10 information read from each sector with
the value stored in the lOR, and sets the NO flag of
Status Register 1 to a 1 (high) if there is no comparison.
Multi-track or skip operations are not allowed with this
command.

If a FAULT signal is received from the drive at the end
of a write operation, then'the FDC37C65C sets the EC
flag of Status Register 0 to a 1 (high), and terminates
the command after setting bits 7 and 6 of Status RegISter 0 to 0 and 1 respectively. Also, the loss of a READY
signal at the beginning of a command execution phase
causes bits 7 and 6 of Status Register 0 to be set to 0
and 1 respectively.

This command terminates when the number of sectors
read is equal to EOT. If the FDC37C65C does not find
an 10 Address Mark on the diskette after it encounters
the INDEX HOLE for the second time, it sets the MA
(missing address mark) flag in Status register 1 to a 1
31

Table 15 shows the relationship between N, SC, GPL for various sector sizes. (See Table 16 for recommended IBM
PC and PC/AT compatible programming parameters.)

Table 15
Format

N
Sector Size
SC
8" .Standard Floppy
128 Bytes/Sector
00
1A
01
OF
256

FM Mode

!

MFM Mod" '"

MFM Mode

(4)

02
03

08
04

04
05

02
01

C8
C8

8A
FF
.FF

256

01
02

'1A

OE.

. 36

OF

1B

54

VO
04
02
01

35
99
C8
C8

14

512
1~~""
v, ..

......

V~

04
05
06
5'1." Minifloppy

12

07

128
256
512
1024

00
01
02

10
08
04

10
18
46

03

02

C8

09
19
30
87
FF

2048
256

04
01

01

C8

FF

OA

OC

256
51'2

Ot

12"
1.0

.·20-

·32

_1)'2

1')0

~A

.50

03
04

04

80
C8
C8

FO
FF

07
OE
1B

1B
2A
3A

OE

36

128 Bytes/Sector
256
'.
512
256

(2)
(3)
(4)

FF
FF
FF

00

02

01
05
3~ Sony Micro Floppydisk-

Notes: (1)

3A

128 Bytes/Sector

4096

MFM Mode

1B
2A

512
1024
2048
4096

1024
2048

FM Mode

GPL(2)(J)

07
OE
1B
47

2048
4096
8192

FM Mode

GPL(1)

...

0
1

OF
09

2
1

05
OF

FF

54
09
18
2
74
3
05
35
S~g;3-stad vaJue:- ~f GPt. :n R:;;d cr \"!.;te commands to avoid splice point between data field and
10 field of contiguous sections.
Suggested values of GPL in format command.
All values except sector size and hexadecimal.
In MFM mode FDC37C65C cannot perform a
ReadlWrite/Format operation with 128 bytes/sector.
(N = 00)
512
1024

from the diskette to be compared against data which is
being supplied from the main system. The FDC37C65C
compares the data on a byte-by-byte basis, and looks

Scan Commands
The SCAN Commands allow data which is being read
32

for a sector of data which meets the conditions of:
D'DD

=

D,ROCEssoR. D'DD

£)'DD

~

~

D"ROCESSOR.

If the conditions for scan are met, then the FDC37C65C
sets the SH (Scan Hit) flag of Status Register 2 to a "1'"
(high), and terminates the Scan Command. "the
conditions for scan are not met between the starting
sector (as specified by R) and the last sector pn the:
cylinder (EOT), then the FOC37C65C sets the SN (Scan
Not Satisfied) flag of Status Register 2 to a 1 (high). and
terminates the Scan Command.
The receipt of a
TERMINAL COUNT signal from the Processor or DMA
Controller during the scan operation will cause the
FOC37C65C to complete the comparison of the particular byte which is in process, and then to terminate th.e
command. Table 16 shows the status of bits SH and SN
under various conditions of SCAN.

or

£)PROCESSOR

The hexadecimal byte of FF either from memory or from
the drive can be used as a mask byte becau,se it always
meets the condition of the compare. Ones complement
arithmetic is used for comparison (FF largest number,
00 smallest number). After a whole sector of data is
compared, if the conditions are not met, the sector
number is incremental (R + STP - R), and the scan
operation is continued. The scan operation continues
until one of the following conditions occur:

=

=

1. The conditions for scan are met (equal, low, or
high), or,
2. The last sector on the track is reached (EOT), or
3. The terminal count signal is received.
Table 16
STATUS REGISTER 2

COMMAND

Scan Equal

Scan Low or Equal

Scan High or Equal

BIT 2 (SN)

BIT 3 (SH)

0

1

0"00

1

0

0'00 .. O"ROCt$$OR

0

1

0'00

0

0

0'00 < O"ROCES$OR

1

0

D,,~o > D"RQt~OR

0

1

0"00

0

0

0'00 > D"AocnsoR

1

0

0'00 < O"AOCESSOR

If the FOC37C65C encounters a Deleted Data Address
Mark on one of the sectors (and SK = 0), then it regards
the sector as the last sector on the cylinder, sets the
CM (Control Mark) flag of Status Register 2 to. 1 (high)
and terminates the command.
If SK
1, the
FDC37C65C skips the sector with the Deleted Address
Mark, and reads the_next sector. In the second case (SK
1), the FDC37C65C sets the CM (Control Mark) flag of
Status Register 2 to a 1 (high) in order to show that a
Deleted Sector had been encountered.

= O"ROC!$SOR
= O"ROCUSOR

= D"ROCEssoR

23 and 25 will be read, then the next sector (26) wilt be
skipped, and the Index Hole will be encountered before
the EOT value of 26 can be read. This will result in an
abnormal termination of the command. If the EOT has
been set at 25 or the scanning started at sector 20. then
the Scan ~ommand would be completed In a normal
manner.

=

=

During the Scan Command, data is supplied by either
the processor or DMA Controller for comparison agains-t
the data read from the diskette. In order to avoid having
the OR (Over Run) flag set In Status Register 1. it is·
necessary to have the data available in lesa than 27 ps
(FM Mode) or 13 pS (MFM Mode). If an Overrun occurs
the FDC37C65C ends the command with bits 7 and 6 of
Status Register set to 0 and 1, respectively.

When either the STP (contiguous sectors = 01, or
alternate sectors = 02) sectors are read, or the MT
(Multi-Track) is programmed, it Is necessary to remember that the last sector on the track must be read. For
example, if STP 02, MT 0, the sectors are numbered
sequentially 1 through 26, and we start the Scan Command at sector 21, the following will happen: Sectors.21,

=

COMMENTS

=

a

33

Seek
The read/write head within the drive is moved from
cylinder to cylinder under control of the Seek Command.
FDC37C65C has four independent Present Cylinder
Registers for each drive. They are clear only after the
Recalibrate command. The FDC37C65C compares the
PCN (Present Cylinder Number), which is the ct,lrrent
head position, with the NCN (New Cylinder Number).
and if there is a difference performs the following
operation:
PCN < NCN:

Direction signal to drive set to
a 1 (high),and Step Pulses are
issued (Step In) .
. Direction ~ignai to drive set to
a 0 (low), and Step Pulses are
issued (Step Out).

The rate at which Step Pulses are issued is controlled
by the SRT (Stepping Rate Time) in the SPECIFY
Command. After each Step Pulse is issued. NCN is
compared against peN; when NCN = PCN, the SE
(Seek End) flag in Status Register 0 is set to a 1 (high),
and the command is terminated. At this point the
FDC37C65C interrupt goes high. Bits DBO - DB3 in the
Main Status Register are set during the seek operation
and are cleared by the Sense Interrupt Status Command.
During the Command Phase of the Seek operation, the
I=QC37C65C i~ in thflt ~r)r;37CS5C RUSY d;at-., ~qt
during the Execution Phase ~t is in the NON-BUSY state.
While the FDC37C65C is in the NON BUSY ;state,

another 3eek Command may be issued. and in this
manner parallel Seek Operations may be performed on
up to 4 Drives at once. No other command can be
issued for as long as the FDC37C65C is in process of
sending Step Pulses to any drive.
If a drive is in a NOT READY state at the beginning of
the command execution phase or during the seek
operation, then the NR (NOT READY) flag is set in
Status Register 0 to a 1 (high), and the command is
terminated after bits 7 and 6 of Status Register 0 are set
to 0 and 1 respectively.

If the time to write 3 bytes of seek command exceeds
150 JlS, the timing between the first two Step Pulses
may be shorter than set in the Specify command by as
much as 1 ms.
Recallbrate
The function of this command is to retract the read/write
head within the drive to the Track 0 position. The
FOC37C6SC clears the contents of the PCN counter,
and checks the status of the Track 0 signal from th6
drive. As long as the Track 0 signal is low. the Direction
signal remains 0 (low) and Step Pulses are issued.
When the TraCK 0 signai goes high. the SE (SEEK END)

flag in Status Register 0 is set to a 1 (high) and the
command is terminated. If the Track 0 signal is sttJIlow
after 77 Step Pulses have been issued, the FDC37C65C
sets the SE (SEEK END) and EC (EQUIPMENT CHECK)
flags of Status Register 0 to both 1's (highs), and
terminates the command after bits 7 and 6 of Status
Register 0 are set to 0 and 1 respectively.
For IBM compatibility. two RECALIBRATE Commands
must be issued for disks with more than 77 tracks.
The ability to overlap RECAll BRATE Commands to
multiple drives and the loss of the READY signal, as
described in the Seek Command, also applies to the
RECALIBRA TE Command.
Sense Interrupt Status
An ~nterrupt s~gnal wm o-e geni;fated by thC! FDC37C65C
for one of the following reasons:

1. Upon entering the Result Phase of:
a. Read Data Command
b. Read a Track Command
c. Read 10 Command
d. Read Deleted Data Command
e. Write Data Command
f. Format a Cylinder Command
g. Write Deleted Data Command
h. Scan Commands
2. Ready Line of drive changes state
'3. ~~d -;,f S~~~ ~~ ?~c~m:!,3b Gommar.d
4. During Execution Pnase in the NON-OMA Mode
;nte~ry~~~ c;:alJ!!i~J"f b~ "'",.asol"l$1 and 4 above occur
during normal command operatio~d are easily
discernible by the processor. During an execution phase
in the NON-oMA Mode, DBS in the Main Status Register
is high. Upon entering the Result Phase this bit is
cleared. Reasons 1 and 4 do not require a Sense
Interrupt Status command. The interrupt is cleared by
reading or writing data to the FoC. Interrupts caused by
reasons 2 and 3 above may be uniquely identifie~ with
the aid of the Sense Interrupt status Command. This
command when issued resets the interrupt signal and
via bits 5. 6, and 7 of Status Register, 0 identifies the
cause of the interrupt. See Table 17.

Neither the Seek or Recalibrate Command have a Result
Phase. Therefore. it is mandatory to use the Sense
Jnterrupt Status Command after these commands to
effectively terminate them and to provide verification of
the head position (PCN).
Issuing the Sense Interrupt Status Command without an
interrupt pending is treated as an invalid command.
Specify
The Specify Command sets the initial values for each of
the three internal timers. The HUT (Head Unload Time)

Sense Drive Status
Table 17
INTERRUPT
CODE

This command may be used by the processor whenever
it wishes to obtain the status of the drives. Status
Register 3 contains the Drive Status information stored
internally in the FDC37C65C registers.

CAUSE

SEEK
END
BIT 5

BIT 6

BIT 7

0

1

1

Ready Line changed state.
either polarity

1

0

0

Normal Tennination of Seek
or Recalibrate Command

1

1

0

Abnormal Tennination of
Seek or RecaJibrate C0mmand

Invalid
If an invalid command is sent to the FoC37C65C (a
command not defined above). then the FOC37C65C wilt
terminate the command after bits 7 and 6 of Status
Register 0 are set to 1 and 0 respectively. No interrUpt
is generated by the FDC37C65C during this condition.
Bit 6 and bit 7 (010 and RaM) in the Main Status
Register are both high ("1") indicating to the processor
that the FDC37C65C is in the Result Phase and the
contents of Status Register 0 (STO) must be read. When
the processor reads Status Register O. it will find an SO
hex indicating an invalid command was received.

defines the time from the end of the Execution Phase of
one of the ReadlWrite Commands to the head unload
state. This timer is programmable from 16 to 240 ms in
increments of 16 ms (01 = 16 ms. 02 = 32 ms. '" OF =
240 ms). The SRT (Step Rate Time) defines the time
interval between adjacent step pulses. This timer is
programmable from 1 to 16 ms in increments of 1 ms (F
= 1 ms. E 2 ms. 0 3 ms. etc.). The HLT (Head Load
Time) defines the time between the Head Load signal
going high and the ReadlWrite operation starting. This
timer is programmable from 2 to 254 ms in increments
of 2 ms (01 = 2 ms. 02
4 ms. 03 6 ms, ... 7F 254
ms).

=

A Sense IntemJpt Status Command must be sent after
a Seek or Recalibrate Interrupt. otherwise the
FDC37C65C will consider the next command to be an
Invalid Command.
In some applications the user may wish to use this command as a No-Op command. to place the FoC37CS5C
in a standby or no operation state.

=

=

=

=

Table 18

COMPARISON: FDC37C65B & FDC37C65C

The time intervals mentioned above are a direct function
of the clock (CLK1 or XTAL 1). Times indicated above
are for a 16 MHz clock; if the clock is reduced to 8 MHz
then the time intervals are increased by a factor of two.
If the clock is increased to 32 MHz then all time
intervals are decreased by a factor of two.

FDC37C65B

FDC37C65C

Max Data Rate: 1 Mbps

Max Data Rate: 1 Mbps

Max Clock: 32 MHz

Max Clock: 32 MHz

No Power Down Mode

Power Down Mode

No Write
Feature

The choice of oMA or non-OMA operation is made by
the NO (NON-DMA) bit. When this bit is high (NO = 1).
the non-DMA mode is selected. and when NO O. the
DMA mode is selected.

=

P~p

Disable

Pull up resistor on DMA
pin

Write Precomp Disable
Feature

No Pull-up resistor on
DMA pin

SYSTEM 34 (DOUBLE DENSITY) FORMAT
GAP 4. SYNC lAM GAP1 SYNC lOAM C H S N C GAP2 SYNC DATA AM DATA
SOx
Y 0 E 0 R 22x
12x
SOx
12x
12x
3x ,"FB
3x lFE L
3x IFC 4E
4E
00
00
C
C
00
00
A1
A1
F8
C2
GAP4a SYNC
40x
6x
FF
00

lAM
FC

C GAP3 GAP
4b
R
C

SYSTEM 3740 (SlNGlE DENSITY) FORMAT
GAP1 SYNC lOAM C H S N C GAP2 SYNC DATA AM DATA C GAP3 GAP
Y D E 0 R 11x
6x
6x
R
4b
26x
FE
FB or F8
C
FF
00
L
C
FF
00
C

35

OPERATIONAL DESCRlPTION
MAXIMUM GUARANTEED RATINGS·
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ooe to + 70·e
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _55° to +150 0 e
Lead Temperature Range (soldering. 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +325°e
Positive Voltage on any pin, with respect to Ground .. . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .. V,,+0.3V
Negative Voltage on any pin, with respect to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V
M.aximum V" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
• Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and
functional operation of the d'evice at any other condition above those indicated in the' operation sections of this
specification is not implied.
Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum
na\iiig~ iiVl u~ oA,;~o.jad v~ da.~;ca failure ~an resi.M~t Some power 5uppJies exhibit voltage spikes o.n their outputs
when the AC power is $witenea on Of off. in addition, voltage transients on the AC power line may appear on the De
output. If this possibifity exists. it is suggested that a clamp circuit be used_
DC ELECTRICAL CHARACTERISTICS (TA = O·C - 70·e, Vee = +5.0 V :t 10%)
PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

COMMENTS

0.8

V

TTL Levels

Low Input Voltage 1
{00-07. XTAL 1, XTAL2
High Input Voltage 1
(00-07. XTAL 1. XTAL2)

V'Lt
V'M'

2.0

V

Low Input Voltage 2
(Low to High Threshold)
(All inputs except 00-07.
XTAL 1. XTAL2)
High Input Voltage 2
f (Hfgnto LOW {nnssnofdl

V ,U

0.8

V

Schmitt Trigger

V

Schmitt Trigger

r

V ,MZ

2.0

i

I

{oAtH in-pub e-xcapt 00--01,

Schmitt Trigger Hysteresis

VMYS

Low Output Voltage 1
(00-07, IRa, OMA)
High Output Voltage 1
(00-07, IRa, OMA)

VOLt

J

I'

VO"t

0.45

V
0.4

2.8

Low Output Voltage 2 (All outputs You
except 00-07. IRQ. OMA)
Latch Up Current

IlU

Input Leakage Current 1 (All inputs except PCVAL and DRV)
Low Input Pull-Up Current

'Lt

i?CVAi. ana uRVi
High Input leakage Current 2

I

~

XTAll, XTAl2).

0.4

V

10L

V

10 "

= 24.0 mA
= -5.0 mA

V

10L

= 48 mA

mA

:t200
:t10.0

JlA

= OV
= 5V

I"u

10.0

60

JlA

V IN

11.%

0.0

-10.0

~

V,N

100~A Source Loads
5 mA Source Loads
V ,N
GND or Vee; 10 :. 0

(PCVAL and DRV)

V~e Supply Current 1
Vee Supply Current 2
Power Down Mode Vee Supply
Current

Icc,
leez
'ec"D

45
95
100

mA
rnA

Power Dissipation 1
Power Dissipation 2

P0 1
P0 2

425
575

mW

Power Qualified Reset Threshold

VPQ~

4.35

V

2.8

.. Includes open drain rllgh current dri'y'ers at VOL:' OAV

36

~A

rr:VV

=

Icc1 Max
'cez Max ••

I

TIMING DIAGRAMS

~'---

AD. CS

OACK, LOCQ
l"'~_-- t

____________~.~14~-t3--_4------

1

QD
t

5

DATA VALID

DATA

t

6

IQQ

min

Parameter
t,

AO.~.~.~
Set Up to m5' low

t2

Jrn' Width

~

AO.~.~.~
Hold from Jrn' High

t.

Data Access Time from

ts

Data to Float Delay from ~ High

t.

IRQ Reset Delay from

typ

max

units

0

ns

90

ns

0

ns

m5 low

1m High

90

ns

65

ns

X + (150ns)·

• X specifies one MClK period. It is dependent upon selected data rate (see Table 1.0).

FIGURE 5 - MICROPROCESSOR READ TIMING

37

~

----'

----------------------------------~!~
I

1

----------------~\I~~~------- ~2

__________

~

~~3

, .. !

~~~-~

________________

------------~~~I~----~----

~\I~
~_t4 -_-_-_-_-_-_~._~~~t_5~
__

\;

DAiA

)\
____________________________

~/

\~

OATA VALID
________________

~----J

t

5

min

Parameter

t,

AO. CS. ITACK. ~. ~
Set Up time to

WR

typ

max

units

0

ns

60

ns

0

ns

Low

t2

WR

t)

AO.cs.OACK.~.~
Hold from WR High

t.

Data Set Up Time to

WR

High

80

ns

ts

Data Hold Time from

WR

High

0

ns

ts

IRQ Reset Delay from

Width

WR

X + (150ns,-

High

• X specifies one MCLK period. It is dependent upon selected data rate (see Table 10).

FIGURE 6 - MICROPROCESSOR WRITE TIMING

38

!~

'1

I

t

()..AA

------------------------.~~(

\

I~

t2

I
I

CAel(

~

QO

or

wQ

ts. S

1---

QATA

min

t,

DMA Cycle Time

52

X·

tz

~ Delay Time from DMA High

0

ns

t3

DMA Reset Delay from

t.

~Width

ts

R15 or ~ Response From DMA High

t,

rm Delay from DMA High

0

ns

t,

ViR Delay from

0

ns

t.

Data Access Time from

t.

Data Set Up Time to ~ High

t,o

Data to Float Oalay from

t"

Data Hold Time from

l5Aa< Low

typ

max

units

Parameter

140
90

ns

48

DMA High

Rn Low

90
80

rm High

10

WIt High

0

ns

X·

ns
ns

65

nl

ns

• X specifies one MCLK period. It is dependent upon selected data rate (see Table 10).

FIGURE 7 - DMA TIMING
39

OMA

0"-

IRQ

j

~I
I

,...<4.-------

·1 __----_._---\

!
i

~

r:

------------------------~--------~

I·

Parameter

min

~

.!~

'3

typ

max

units

t,

TC Delay from Last DMA or IRa. ~

0

192

X

t2

TC Delay from Last DMA or IRa.

WR

0

384

X

t)

TC Width

60

ns

• X specifies one MCLK period. It is dependent upon selected data rate (see Table 10).

FIGURE 8 - TERMINAL COUNT TIMING

QESET

/

!l

i"

t,

.~

\

~j

\

I

j

I
I

\
\

(5

1\
...

t

3 . ~.

~

~.\

Parameter

min

typ

max

t,

RESET Width - TTL Driven CLK1

250

ns

t2

RESET Width - Software Reset

5

X·

t)

Chip Access Oelay from RESET Low - TTL

32

X•

t,

Chip Access Delay from Software RESET Low

40

X·

t!

Chip Access Delay from RESET Low - XTAL 1 at 16
MHz

500

Iols

til

XTAL2 Access Delay after Reset 9.6 MHz

1000

Ils

units

... X specifies one MCLK period. It is dependent upon selected data rate (see Table 10).
FIGURE 9 - RESET TI MI NG

40

}

OI~C

/

Ii

I

,'4

"I

~.

STEP

1'4

\

\

I

'

t2

t

t4

.~
\

ts

I

051-4

..

':.]

.. 1

1

\

~t6~

\
1
~t7~
\
1
~tB~
\
1

lOX

OOD

~D

Parameter

min

t,

~ Set Up to ~ Low

~

typ

max

units

4

X·

~ Active time Low

24

X·

~

~ Hold Time After ~

96

X·

t.

~CycleTime

132

X·

t,

~ Hold Time from ~ Low

20

X·

t,

rnx Pulse Width

2

X·

t7

t.

m5t5 Active Time Low
wt5 Write Data Width Low

40

ns

.5

y.

• X specifies one MCLK period. It is dependent upon selected data rate (see Table 10) .
•• Y specifies one WClK period. It Is dependent upon selected data rate (see Table 10)

FIGURE 10 - DISK DRIVE TIMING

41

I
CLOCK

t:=_t_1--------.1
i/

r-

t2

\i

/

;.....- . . - - - t 4

;

---I.~!~----

----.,~.

.!

;~

min

Parameter
Clock Rise Time (VIN

t 4

I

i

t,

\

f'·-----------/ i

_ _ _ _ _........J/;

typ

=0.8 TO 2.0)

Clock Fall Time (VIN = 2.0 to 0.8)

max

units

2

ns

2

ns

Clock Period

31.0

ns

Clock Active (High or Low)

13.5

ns

FIGURE 11 - CLOCK TIMING

Table 16 - PROGRAMMING VALUES FOR FLOPPY DISK CONTROLLERS
(IBM PC AND PC/AT COMPATIBLE SYSTEMS)
HEX VALUES TO BE PROGRAMMED

Parameter
1.44 MB
3.5"

720 KB

Bytes/Sector {N}

02

02

02-.

SectorslTrack {Se}
Gap Length (1) {GPL 1}

12

09

OF

09

1B
6C

2A

1B
54

2A
50

I

l

360 KB
5.25"
02

Head Settle Time (ms)

15

50
15

15

15

Motor Start Up (118 sec)

08

08

08

Cylinders
Tracks

80
160

80
160

80
160

08
40
80

Tracks/Inch

135

135

96

48

Gap Length (2).(3){GPL2,3}

I

1.2 MB
5.25"

3.5-

Heads

02

RPM

300

Trans~er

(KB/s)

Q1990 STANDARD MICROSYSTEMS
CORP.

STANDARD MICROSYSTEMS
CORPORATION
55 ~ IfwC ~
'5'161 m

' IClO

NY",..

,~ 'S'6I 231 6001

500

~

02

02

02

300

360

300

500

250

250

t

Circuit diagrams utilizing SMC products are included as a means of illustrating
typical applications; consequently complete information sufficient for construction
purposes IS not necessarily given. The Information has been carefully checked and
is believed to be entirely reliable. However, no responsibility is assumed for
inaccuracies. Furthermore, such information does not convey to the purchaser of
the semiconductor devices described any licenses under the patent nghts of SMC
or others. SMC reserves the right to make changes at any time in order to improve
design and supply the best product possible.
10/4/90

lillY lN8
EdItion 1.0

MB87030
MB87031

FUJrr5U FUJITSU MICROELECTRONICS. INC.

Product Profile

SCSI Protocol Controller (SPC)
GENERAL DESCRIPnON
The M887030 and M8I7031 SCSI Protocol ContraIer (SPC) ... CMOS LSI cfrcub epecIfIcaIy cfMigned to control a
SInaI Computer ~.". Interface (SCSI). In terme of ,....... functional operation. and eIectrtcaI epecIftcatIone. the
two devlc. . .e identical. Howe • • the M887030 II houNd In . , Ia-pIn cerMIIc
grid array package ......... the
M887031 Ie deelgned for lWface mountfng and .. houNd In • 1~ ptutIc flat package.

'*'

The SPC can ..,.,. .. either . , INITlATOR or TARGET for the SCSI: tt... It can be UMd . . In 110 controller or . . a
hem adapter. To ...e the ~e In the mo8t effectIYe manner. It II reco;iI.WiIded that the UHr' be thoroughly famIIar
with the SCSI and Interlace control procec:Uea. For detailed information In theM . . . . . the UHI" ehouId contact the
nearnt Sales Offtce of FuJtsu.
The SPC Ie designed to control .. SCSI Interlace efonaI8 and vIrtuaIy .. Interface control procedure•• UHd . . .n 8- or
16-bft peripheral, the device provtde. high-level control for Unoat" SCSI ~atJona.
To acNeve opttnun performance and Interface ftexl)llty. the $PC cent. . an I-byte FIrat In FIrat Out (FIFO) data
buffer register and a 24-b1t transfer byte COU1ter. Independent data bun.. for the CPU and the OM" controler pIua
separate Input/output pint tor .. control slgnala gr. .tty reducn the pouIbIIty of a -busy- condition. Data tranef.,.. can
be executed In either the -vnchronout or uynchronoua mode with a maxIm.m offHt of 8-byte••

SCSI Compatibility

Selectable Transfer Modes

e Suppa", AI mandatory commanda, many optional
corrvnanda, and some extended cornmanda of SCSI
Speclftcatlon (ANSI X3.131/1986)

• OM" tranafer
e Program tranafer

e Serves a, either INITIATOR or TARGET

•

ManJaI trarwter

Interface Connections

e Both synchronous and asynchronous operation

•

SIngle ended or differential options

e Software compatible wtth MB87033

•

TTL-compatlble 110

Clock Requirement.

a MHz clock with 33% to 66% duty cycle

Data Busses

e

e Independent busses for CPU and OMA controller

Technology/Power Requirements

e Synchronous data transfers wtth programmable offset of up to eight bytes

e Sllcon-oate CMOS

Available Packaging

Data Transfer Speed
•

e

up to.a maximum of 4-rnegabytes-per-second

A8~OlUTE

e SIngle +SY power supply

88-pm ceramic

repeated quad-in-line

e 100-pin plastic flat package

MAXIMUM RATINGS1

Rating

Valu••

Symbol
Min

Unit
Mex

Supply Voltage

Veo

YSS2-.05

7.0

V

Input Voltage

VI

Vss2-.05

Yeo + 0.5

V

Output Voltage 2

Vo

Vss2-.05

Veo + 0.5

V

Storage Temperature (Ceramic)

T STO

-65

+1S0

·C

Temperature Under Bias (Ceramic)

T BIAS

-40

+125

·C

I OS

-40

+70

rnA

Output Current 3

NOTES:
,.
Permanent device damage may occur If the above Ab.olut. Maximum Ratings are exceeded. Functional
operation should be restricted to the conditions a. detaled In the operational sections of thI, data sheet.
Exposure to absolute maximum rating condition. for extended periods may affect device reUabWty.

= OV.

2.

Vss

3.

Not more than one output may be shorted at a time for a maxJmum duration of one second.

CopyrlOht. 1;88 by FUJrTSU UMTTEO and FujItsu Mtcroelctronlcs. Ire.

6-3

May 1988
Edition 1.0

MB87030/31
PIN ASSIGNMENTS (Continued)
FPT-lOOP-MOl

o

Pin
No.
1

I

a

0

3
4
5
6
7

-

Veo
Vss

I

HIN
HOBO
HOBl

8

1/0

33

9
10
11
12
13
14
15
16

110
I/O

HOB2
HOB3
HOB4·

1/0

110
110

110
110
110
110

HOB5
HOB6
HOB7
HOBP

-

Vss

I

17

I

18

I

19
20

I

21
22
23
24
25

Designator
ORESP
OREQ

CD<

cs
WT
Wffi

1

AD

I
0

ROG

I/O
110

INTR
N/C
00
01

Pin
No.
26
27
28
29

110
I/O
110

Designator
02
03

o

Pin
No.
51
52

Pin
1/0

0
0

-

-

Veo
Vss

54

-

30

110

04

55

1

31
32

I/O

05
06
07

56

0

57

OP
AO
Al

5D
60
61

A2.

62

110

53

sa

Designator
TARG
INIT

Veo
Vss

No.
76

1/0

77

0
0

78

-

79

-

so

D.slgnator
SOBE5
SOB05

Voo
Vss

ACKJ
ACKO
HIC

-

N/C

81

I

12

HIC

83

1

8SYI

14

0

16

0

BSYO
ATNI
ATNO

0
0
I
0
0

87

I

0
0

SOBI4
SOBE4
SOB04
SOBI3
SOBE3
SOB03
SOBI2
SOBE2
SOB02

-

-

34

110
I/O

35
36
37

I
I
I

38

I

A3

63

...

AST1

sa

39
40
41

1

RST

84

0

RSTO

II

-

Vss

IS

-

Va

10

-

Vss

I

REQI

66

1

11

42
43

0
I
0

REQO
1101

87

0
0

•

88

$OBIP
S08EP
SOBOP

1/00

81

I

SOBI7

ClOt
C/OO

70
71

0

SD8E7

IS

0

0

18

0

SEU
SELO
MSG1
MSGO

72

1

i7

73

0
0
I

SOB07
SOBI6
$OBE6

-

SOBEl
SOBEl
SOBOl
SOBIO
SOBEO
SOBoo
HIC
N/C
N/C
N/C

44

45
46
47
48
49
50

I

0
I
0
I
0

74
75

I

SOB06
SDBJ5

as

D2

"

lot

U

19
100

0
0
I

-

Mil'( 1988
Edition 7.0

MB87030/31
PIN :DESCRIPTIONS (Continued)
Pin No.
MB 17030
64
65
27
29
70
32
72
36
23

M887031
71

o..lgnator

93

SOB07
S0806
SOBOS
SOB04
SOB03
SOB02
SOB01

96
68

SOBOP

7.

n

83
85

ei

soeoo

Function

OUtput. for the SCSI data bus. Moat ~ant bft (MSB) .. SOB07;
leaat aIgnIftcant bit Ie SOBOO. soeop Is an odd partty bft.
If the bua drtYw .. an open colector devica. the.a .lgnaJ. should be
appled clrectly to the drtver crcutt. If the bw drtYer Is a thrae-atata
device. the. . eIonaJa ara usad .a data and SOB07-SOBOO and SOBOP
are used a. drtv--.nable eIgnaJs.
- -

~ctIon

~~ register

37

17

CS

In SPC. When
CS Ie ac:ttve. Input/output eIgnals RD. ROG. WT. WTG. OP. "'O-A3. and
00-07 ara active.

38

16

CD<

Input clock for controlling Internal operation and data transfer speed of
SPC.

enable .1gnaI for access.!!:!i

Input .trobea used for rea~ out contents of Intarnal raglstar: strobea
are affective onty when CS Is .ctIYe Low.
39
40

20
21

R6
RDG

-

When Ri5Ci Ie active Low. the contenta of an Internal reglstar selected
by 1Iddr. . . Inputa AO-A3 .,.e placed on data bus In"a DO-07 and DP.
For • cia!!.,tran8f., cycle In the program transfer mode. th4t tralHng
aclga of RO Ie used a• • tlmIno .Ignal to lncIcate the end of data read.
OWIng a data t r . . t . cycle In the OMA mode. ORESP Is a response

eIQnaI to the data tran8fer raqueat atgnal OREQ. The ORESP pm
be re"aahed with an
farred.
41

1

~

must

pulaa after aach byte of data Is trans-

ORESP
In output operatlona. the fallng edge of ORESP Is used for sampling
data on HOBO-HOB7 and HOBP bus line.; In Input operation.. the SPC
holes. data to be tran8ferred onto HOBO-HOB7 and HDBP untU the fallng
edge of ORESP ocan.

51
50
49
.8

33
32
31
30

07
06
05

80

27

79
.3

•2

26
25
24

52

~

03
02
01
00
OP

04

U.ed for wrttIng-or-re.dIng data Into-or-from an Intemal register In
SPC; the.a bus Ina. are thr. .-Itata and bidirectional. The Most SlgnHIcant BIt (MSB) II 07: the Laast Significant Bit (LSB) Is ~O. DP Is an
odd partty bit.

When the CS and ROO Input. are acttve Low. cont.nt. of the Internal
reglst. are output to the data bU8 (r. .d operation). In operation•
other than read. the. . bus h . are kept In • high-impedance state.

Addrasl Input aIgnaJe for ,electlng an lntarnaJ register In the SPC. The
Moat Slgnlftcant BIt (MSB) Is A3; the least SIgnificant BIt elSB) la AO.
44-47

35-38

AO-A3

When Cs • active Low. read/wrlte Is .nabled and a Internal regt.ter Is
....ct.d by the.e addre •• Input. via data bus Ones 00-07 and OP.
Requell. an Interrupt to indicate completion of an SPC Internal operation or the occurrence of an error.

53

22

INTR
Interrupt masldng .. alloWed axcept for an Interrupt caused by the RSTI
Input (re.et conditIon of SCSI). When an Interrupt Is permitted. the
INTR signal remain, acttve untO the Interrupt Is cleared.

56
61
58
60
57
55
54
62
59

.7
59
41
55
49
45

SEU
BSYl

43

1101

61

ATNI
BSTI

63

REOt
ACKI
MSGI
C/OI

U.ed for recelYtng SCSI control Ilgnats: output. of the SCSI receiver
can be directly connected. (Waveform distortion or any other dlsturbane. should not OCCU'" In the REal and ACKI algnal8 which are used as
for 8equenclng data transfer•. )
tlrr*1g control

.1gnaI.

May 1H8
Edition 1.0

£
rwrrsv
£

MB87030131

PIN ASSIGNMENTS
PGA-I8c-A01

o 0 0 0 0 0 0 0 0 0 0 0
34 33 32 31 30 21 28 27 2S 25 24 23
o 0 0 0 0 0 0 0 0 0 0 0
35

72 71

o 0
38 73
o 0
~ ~
o38 0 75

70

40

41

0

Ii

IS

0

~

II 15

0

2

~

10

0
0

13 51

78

1

12

0

0

INDEX PIN

0

'1

0

22

21
~

19

000
84 59 ,.
000

(TOP VIEW)

0
0/
42 78
o 0
80

0

as

n ..

43

14 13

0

000
- 31 71'7
000

o 0

G

57

17

0

16

058015
0 0

82

55

14

11

12

o 0 0 0 0 0 0 0 0 0 0 0
~
45 46 47 48 48 50 51 52 53 54 13
o 0 0 0 0 0 0 0 0 0 0 0

Pin
No.

1/0

Designator

Pin
No.

110

1

I

HIM

23

0

2

1/0

HOBOO

24

3

..

1/0

HOB01

25

1/0

HOB02

S

1/0

6

3

4

De.lgnator

5

6

Pin
No.

7

110

8

g

10

De.lgnator

Pin
No.

1/0

Oe.lgnator

SOBOP

45

I

10.1

67

0

$OBES

0

SOBE7

46

I

A2

68

0

SOBE"

I

SOBI7

47

I

A3

69

I

SOBI..

26

0

SOBE6

48

110

04

70

0

SOB03

HOB03

27

0

SOBOS

49

110

05

71

I

SOBI2

110

HOB04

28

I

SOBI5

50

1/0

06

72

0

SOB01

7

110

HOBOS

29

0

SOB04

51

110

07

73

0

SOB EO

8

I/O

HOBOS

30

0

SOBE3

52

110

OP

74

I

SOBIO

9

I/O

HOB07

31

I

SOBI3

53

0

INTR

75

I

RST

10

I/O

HOBOP

32

0

SOB02

54

I

1/01

76

0

OREQ

11

0

INIT

33

0

SOBE2

55

I

CIOI

n

I

12

0

TARG

3<4

I

SOBI1

56

I

SEU

78

I

WT
WTG

13

0

1100

35

0

SOBE1

57

I

MSG1

79

1/0

02

14

0

C/OO

36

0

soeoo

51

I

REQI

80

I/O

03

15

0

SELO

37

I

cs

59

I

RSTI

81

Power Supply

16

0

MSGO

38

I

Cu<

60

I

ACKI

82

Power Supply

17

0

REOO

39

I

R5

61

I

BSYI

83

Power Supply

18

0

RSTO

40

I

RGO

62

I

ANTI

84

Power Suppty

Vss
Veo
Veo
Vss
Vss
Veo

19

0

ACKO

41

I

ORESP

63

I

SOBIP

85

Pow.r Suppty

20

0

BSYO

42

I/O

00

64

0

SOB07

86

Power Suppty

21

0

ATNO

43

I/O

01

65

0

SOB06

87

Pow.r Supply

22

0

SOBEP

44

I

AD

66

I

SOBI6

88

Power Supply

CopyrIQht • 1888 by Fujitsu MIcroelectrOnIcs. Inc.

6-5

Veo
Vss

May 7988
Edition 1.0

MB87030/31
c:n=r.nMMENDED

QPERA~TlNG

Param.ter

l ; l 'Nt

.-

IIUN~

Valu.a

Oe.lgnator
Min

Supply Vottage

Voo

Input High Voitag.

VH

Input Low Vottage

Vl.

Operating T amperatura

TA

4.75
2.2

Unit

Typ
5.0

Max

5.25

V

V

0.8
70

0

V

·C

MB87030/87031 BLOCK DIAGRAM

g:,-oo.==::=:==:

..----~----~~a

~~------------------

I----~~OO

ct---.ACKJ
I----~ ACKO

... ~~~

'---..)---.....---

~~--~~--------~~-----~.~

A3-AO--. ADDRESS

cs

A5.

DECOOE

~~ce

May 1988
Edition 1.0

FUJITSU

MB87030/31

PIN DESCRIPTIONS
Pin No.

MB 87030

MB 87031

5

Designator

HIN

Function
Indicates direction of transmission along data bus lines HoBO-HoB7 and
HOBP in the oMA transfer mode. To be executed, direction of transmission must be propeny coordinated with Internal operation of the
SPC.
When HIN 18 Low, the data bus Unes are placed In the high-Impedance
state (Input model. When HIN Is High, aU bus lines are switched to the
output mode.
Three-state bidirectional data bus 10r transferring data to-or-from the
external buffer memory In the oMA mode. As shown below. the direction of data transmission depends on the HIN Input signal.

2-9
10

6-13
14

HoBO-HoB7
HoBP

HIN

HoBn

Oporatlon

Input Mode
Output Mode

L
H

Output
lnpu~

These two signals Indicate operating state of SPC: they are also available as control signals for the SCSI driver/receiver elr ::ulls

11
12

52
51

INIT
TARG

Initiator

Target

L
L

L
H

H

L

--

Status

..

SPC is not corYlecttd tu SCSI
SPC Is oxecutlng resel6ctlon phase or Is
operatlnQ as a target.
SPC IS ~xecuting selection phase or Is

oceratlno as an Initiator
44
46
48
50
42
64
56
60
62

1/00
CloO
SELO
MSGO
REOO
RSTO
ACKO
BSYO
ATNO

Used to output SCS control signals. REOO. MSGO. CI ~O. and 1/00
are active High only when the SPC serves as a target. ACKO and
A TNO are active High only when the SPC serves as an Initiator.

67
68
30

67
70
73
76
82
85

SoBEP
SOBEl
SoBE6
SoBE5
SoBE4
SoBE3

Drive enable signals (corresponding to respective bit positions I when a
three-state buffer is used for the SCSI data bus SOBE7-S0BEO and
SOBEP correspond to SOB07-SoBOO and SoBOP. respectively Relationships with respect to the SCSI bus are shown below.

33
35
73

88
92
95

SoBE2
SOBEl
SoBEO

13
14
15

16
17
18
19
20
21
22

24
26

Bus Free
Arbitration
Selectlon/Reselection
Information Transfer
SPC -+ SCSI
SCSI +- SPC

SoBEn

SoBOOn

SCSI Bus Status
10

10

L

L
L

H
0

0

10

10

L

L
L

H
H

H

H

H

L

L

----.

0

L

0
L

Noles:
_
1. ·10· indicates bit positions corresponding to the SCSI bus device 10:
10 indicates the other bit position.
.
2. ·0· indicates transfer of valid information.

25
66
28
69
31
71
34

74
63

69

72
75
81
84
87
91
94
66

SOBI7
SOBI6
SOBI5
SOBI4
SOBI3
SOBI2
SOBI1
SOBIO
SOBIP

Copyright • HI88 by Fujitsu MIcroelectronics, Inc.

Inputs for the SCSI data bus. Most significant bit (MSB) Is SOBI7; least
slgnfficant bit (L5B) Is 50B10. 5DBIP Is an odd parity blt: parity checking
for the SCSI data bus Is programmable.

fi..7

May 1988
Edition 1.0

MB87030/31
PIN DESCRIPTIONS (Continued)
Pin No.

MS 17030
78

MB 17031
2

FunctIon

o.a'gnator

OREQ

When executing a data tr..ter cycle In the OMA mode. OREO Is wed
to indicate a requut fOf' data tranet.... be~ the SPC .nd external
buffer memory. In the OMA mode. routing of data Is as .tKrNn below.
Output Operatton.:
From External Buffer Memory to HOBO-HOB7/HOBBP to SPC Internal Data Buff.,. ReQIat.... (eight Byte.) to SOBOO-SOB07/S0BOP to

SCSI.
Input Operatton.:
From SCSI to SOBI9-S0BI7/SDBIP to SPC Internal Data Buffer Regtllter (eight byte.) to HOBO-HOB7IOHOBP to External Buffer Mem-

ory.
In an output operation. OREO becomes active to request a data transfer from the extemal buffer memory when the SPC Internal data buffer
register has fr.e .pace avaJlable. In an Input operatton. OREQ becomes
active to request a data transfer to the extemal buffer memory when
the SPC Internal buffer memory contains valid data.
Input .trobe used for writing data Into an SPC Internal register; UW. sigcny when CS Is active Low. On the trdlng edge of WT .
data placed on data but line. OO-07/0P II loaded Into the Internal regi.ter .elected by addr... Input. AO-A3. except when .. addre.. anel are
High (AO-A3 H).

nal Is asserted

n

18

WT

=

Fora data tranafer cycle In the program transfer rnoc:Ie. the trailing
edge of WT II used as a ttrNng aJgnaI to indicate a data-ready stat•.

18

19

81,84.
85,88

4. 15. 29.
40, 54, 65,
79.90

WTG

When WTG Is acttv. Low. data appear1nO on data bus h . 00-07/0.P Is
output to HDBO-HOB7/HOBP If the foBowing Input concltlona are ott.fled:
CS z l
AO-A3. H
HIN H

=

82,83

3,28,

86.81

53.78

-

23. 57. 58
80, 97. 98

99. 100

Vss

Power .upp!y ground.

Voo

+5V Power .upp!y.

-

Not used.

Copyright • 1H1 by Fujitsu M~. ft.

May 1988
EdlClon 1.0

FUJITSU

MB87030/31
ADDRESSING OF INTERNAL REGISTERS

Both the MB87030 and the MB87031 contain slxt • ." (t6) byt.-wld. registers that are externaJly accessible. Th ••• reolsters are
used to control Internal operatlona of the SPC and also to indicate processlnQ/r.sutt .tatus. A unique address. identified by
addresl bits A3-AO. Is asslgn.d to each of the slxt • .., r.olster.. Thes. addr..... are deftned In Tabl. 1. (Note. The phase
aens. (PSNS) and SPC diagnostic (SOGC) regl.t• • hay. the ume h.xadeclmal addr••I; however, dep.ndlng upon whether a
read or writ. convnand '- .xecuted, the r.gt8t.... prOYlde two .eparat. functions.)

Table 1. Intema' Regllter Addressing
Register

Bus OeYie. 10

Mnemonic

-

Operation

Chip Select (CS)

R
BOlO

Address Bits
A3 A2 A1 AO

0

a

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

1

1

0

0

1

0

0

0

0

1

0

t

0

0

,

1

0

0

0

1

1

1

0

1

0

0

0

0

1

0

0

1

0

1

0

1

0

0

1

0

1

1

0

1

1

0

0

0

1

1

0

1

0

1

1

1

0

0

1

1

1

1

W
SPC Control

scn

R
W

R
Command

SCMO
W

R
TraMf. Mode

TMOO
W

Interrupt S."s.

R
INTS

Re.et Interrupt

Pha. . S....
. SPC Dlagnoltlc Control
SPC Statua

W
PSNS

R

SOGe

W

SSTS

R

SPC Error Status

W
SERA

-

R

W
R

Phas. Control

PCTl
W

Modified Byt. Counter

MBC

-

R

W
R

Data Register

DREG
W
R

Temporary Register

TEMP
W

R
Transfer COtM'rter High

TCH
W

R
Transfer Counter Middle

TCM
W
R

Transf. Counter low

TCl
W

R
External Butter

EXBF
W

6-10

May 1988

Edition 1.0

MB87030/31
BIT ASSIGNMENTS
Table 2 1st. the bit ...Iorments fat' the MYenteen 1ntema1 reQiatera deftn.d In Table 1. 0urInQ read/writ. acce•• of ., Internal
register. the folowlnQ rUe. are mooked:

•

1ntema1 registers Include only tho.e registers lcIenttfted In Table 1.

•

A write comrT'W1d to a read-only register ta Ignored.

•

For writ. operations, all bit positions with a

•

AI bit positions with . ,

a_.

(blank) designator can be written u a ·0· or as a ·1·.

uslgned ·0· are atway. raad u a zero (OJ.
Table 2. Bit Assignments For Internal Registers

HEX

Register

Address

Oper-

Mnemonic

7

eticn

(MSB)

Bus
Device 10
(BOlO

R

0

and

.R/W

II'S

.7

1

2

Command
(SCMO)

R
W

SCSI Bus Device ,10

1'5

1.4

..

Transfer
Mode
(TMOO)

Interrupt
Sense
(INTS)

R••et
lOisable

Control
Res.t

W

Xf.r

t.d

R

Enable

Enable

RST

Intercept
Xfer

Transfer Modifier
PRG
Xfer
0

Min. Tranafer
Period

6

SPC
Status
(SSTS)

8

9

SPC
Error
Status
(SERR)

Phase
Control
(PCTL)
Modified
Byte
Counter
(MBC)

Re.et
CondItlcn

P

Command
Complet.

SerTIme
vice Re-

Hard

qulred

Error

ACK

REO

1

Out

-

ATN

SEL

BSY

C/O

MSG

110

Olag.
REO

01a0·
ACK

-"

TARG

Oata Error
SCSI
SPC

I

Olag.

-

I
I

BSY

Olag.
MSG

OIaO.
C/O

TCaO

DREG Sjatus

SPC

XFER
In Pro-

SCSI

BSY

or..•

RST

0

TC

Ful

I

W

Bus
Fr.e
Interrupt
Enable

-

Phase

Copyrlgrlt • 19as by Fujitsu Microelectronics. InC.

Short

Offset

MSG
Out
IBIt2

I~ I~
MBC
I Blt1

I BltO

6-1'

P

-

Transfer Pha.e

Blt3

-

P

Empty

I ~~ I Error I PAMod I Error

a

0

-

R
W

CIaO.
110

a

P

-

-

Connected

w

SPC

Olsco-

R

R

P

Resel-

R

R

0

2

W

7

P

a

1

meet

-

P

2

ected

0

Enable

Reset lntemJPt

INIT

Parity

Term
Mode

4

W

W

INT

Enable

5
SPC Olag
Control
(SOGC)

Reselect
Enable

Select

W
Phase
Sense
(PSNS)

101

Mod.

Max. Transf.r
Off.et

Selec-

102

Parity

Out
Sync.

104

ARBIT

. Command Code

R

0

'.1 1.0
'It?
SCSI Bus Oevlc. 10

Olag

R

R

~

-

W

3

1

2

3

(LSB)

W

SPC
Control
(SCTL)

4

5

8

p

P

Nflly

1988

Edition 1.0

FUJITSU

MB87030/31
Table 2.

HEX
Address

A

B

C

0

E

Register
and
Mnemonic
Data
Register
(DREG)
Temporary
Regllter
(TEMP)

Transfer
Counter
High
(TCH)
Transfer
Counter
Mid.
ITCM)

Bit Assignments For Internal Registers (Continued)

R/W
Oper7
ation (MSB)

6

5

Blt7

I

6

,

Blt7

}

6

J

Blt7

I

6

I

W

I

R
Blt23

Blt15

Transfer
Counter

R

Low

W

5

Blt7

6

4

!

2

!:

3

2

I0
I

0

12

I'

I0

I

I

I

I

I

I
I

I

I

,

I

17

I

16

I

I

I

I
9

8

~

I

1

I

I

I

F

ExternaJ
Buffer
(EXBF)

W

I

I
I

!

I

I

I

"

P

I
P

I

I

1

0

.. -

1

0

p

2

3

I

I

I

I

Ii

I

P

I

External Buffer

I

P

p

Transfer Counter High (LSB)
4
5
3
2

5

P

I

(TCl)

A

1--

I

1

!3

I

Parity

0
(LSB)

14

I

I

6

3

Temporary Data (Output: to SCSI)

5

I

Blt7

I

Transfer Counter High (2nd Byte,
10
13
12
11

14

I

4

Tempo,1lI'Y Data flnput: Flom SCSI),

I
I

I

I

Transfer Counter High (MSBJ
18
20
19
21

22

I

R

5

I

I

W

II

Intemal Data Register (11 Byte FIFO)

R

W

1

I

R

W

2

3

4

May 1988
Edition 1.0

MB87030131
DC CHARACTERISTICS
(Recommended operating conditions. unle•• otherwise specified)

De.lon.tor

Parameter
Power Supply Current

loos

Condition

Po
VOH

I OH • -G.4rnA

Output Low Voltage

Va.

teL. 3.2rnA

Input High Voltage

VIH

Input Low Vottage

VL

Input Leaicage Current

lu

VIS 0 - Veo

il.Z

Tn-State
VIS 0 - Voo

No!e:
1. VIM

z

100

4.2
Vss

6-13

Unit
~

mW
Veo

0.4

2.2

Voo.VL • Vss

Copyright • 1888 by Fujitsu Microelectronics, Inc.

Max

300

Power Dissipation

j
j

Valu ••
Typ

Steady Stata 1

Output High Voltage

Input Leakage Current

Min

V

V
V

0.8

V

-10

10

JLA

-10

10

J!A

May 1988
Ed:tJon 1.0

FUJI'J'SU

MB87030/31
I

AC CHARACTERISTICS
(Recommended operating condition. un leal otherwiu noted)

MPU INTERFACE

Unit

I
i.

I

tCL,F -----..j.~1

~--~\~__-JJ---------\~__~t~------

Parameter

Unit

r--

tRSTW---'1

~------------~)

Parameter

I.~---------------

Value.

De.lgnator

Unit
Max

Typ

MIn

tAWS

40

tcws

25

nl

tCWH

10

nl

Data Bus Setup

tows

25

Data Bus Hold

toWH

2Q

nl

so

nl

Address Setup

5

Address Hold

CS Setup

Cs

Hold

'WT Pulse Width

A3-AO

____~t~______________________~--~x~-----~tAWS

. . . - t AWH

---..

:

--------~\:
:___ tcwe

---.:

J~~-----------

• iI. t CWH~,1

i
.,,

--------------------~I\Io.....-_ _ _ _~,I~-----------------I

t

__--

,toWH,

I....~-- DW! - -.............-;;.....-.~,

07-00, OP

--------------~,

l~---------

Air( 1988
Edition t.O

MB87030131
AC CHARACTERISTIC'S (Continued)

WfG Low to OMA Oata au.

twuc)

H087-HOBO. HOBP

WfG High to OMA Oata au.

tWt+l)

HOB7-HOBO. HOSP

10

30

25

MPU Oata Bu. (07-00. OP)
OMA Data Bus
(HOB7.HOBO. HOBP)

t,OtoC)

5

HIN High to OMA Oata Bus
(HOB7 -HOBO. HOBP)

t....a

10

HIN·
A3-AO

____

1/

====~r

-w!X~

ntI

50

na

..0

nl

I~_ _ _ _ _ __ _

~X~

------~--~I,

I'

a..-t AwtJE.-':
I

I

~tCWHE-..'

------~----------~I\
I

t

I~-------I---------------

..... t"".~
..... ~I

I'" HNZ......

l.t
M Wt+I).,

I

--------------~I----~[
I

Jw---------------

II

,...tcw~

HOB7-HOBO. HOBP

ntI

______________________________________ __________

j.-- tAWSE --.J

07-00,OP

60

<40

]~-t---.:------------------

' . tQHQ

.,

l~

~~:____U_nd
__
~fln
__._d__-'¥,~_____________(____~'r'~_-_-_-_-_-_-_-___
-_-_-_-_~-__
-

CopyrIaM • , . by FujIt8U MIcrc.' :aOllCa, Inc.

6-15

May 1988
ec'/tlon 1.0

FUJITSU

MB87030/31
AC CHARACTERISTICS (Continued)
Parameter

Value.

Designator

Typ

Min

Unit

Max

Address Setup

tARS

40

Address Hold

tARM

5

nl

CS Setup (AD)

t~s

10

n.

CS Hold

tCRM

5

na

AD Pulae Width

tRO

50

nl

RDG Low to Data Outllut

tRLNZ

10

RDG Hlgt1 to 07·00; OP
High Z

tRI+I%

RD Low to Data Establlih

tRI..O

RD High to Data Hold

tRMO

10

CS Setup (RDG)

tCRGS

5

A3-AO

n•...

45
40

as

______~Ir_------------------------------------------~I,.-----------

------~~

~~-----------

. . . . - tAAS~

t + - - tAAM--"

------~\:

,4-:t.I

J~-----------

,4-- tCRM -..0,

'

I ,

tCRS - - . .

\ :

:1

t
~\""i--------------ii-",
_ __________________
RO
I
CR
I t
' ..

________________________

~'~,.

'II

------I~!,

\ •______________, .... , •. tFIHMZ •

, ..-- tAl..O --'
~

07-00, DP

It I
I

I tAlNZ.,...."

-------------------------~

6-16

RMC.

.~

I

.

VaRd

.
I

I

v--"\

~~----------------

May 1088
Edition 1.0

FUJI'I'SU

MB87030/31
AC CHARACTERISTICS (Continued)
a.;j:W~lif:!l~$E\a,gt.li.Klt&Wm@tffr#'jf~f:M~~1l§~@mtm~HN1HJ1!@i#@1gtmW~!~m@~!M!mM!~@@!~~tllM*¥lm{fi#'if#MWM!!&@~@@@@

a..

Param.t.r

Valu••

O•• lgnator

tARse
tARHE

40
10

CS Hold

teRSE
tCAME

ROG Low to Oata Output

tRLNZ

10

ROG High to 07-00, OP
High Z

tRt+lZ

OMA Data BUI (HOB7-HoBO,
HoBP) to MPU Data Bus
(07-00,OP)

tH:)O

Addr••s Setup
Address Hold
CS Setup

HIN Low to HDS7-HOBO.
HoBP High

HIN

Typ

Min

Unit

Max

5

ns
ns

10

na

5

tHINZ

45

ns

40

ns

50

ns

40

~~---------------

*

t ____________________________________________
tAASE
tARHE-.,

A3-AO

----~_J~·

_JI~-----------

~

---.,I

__

:

----~----~\:

;.---------------:. . tCRHE"':
J~------------------------

I.... teRse....!
~,
iI
~ tHNZ ~
,

HOB7-HOBO. HOBP

\I

I

I

Ir---------------~~I------------------------________~:J:)~------~~~(~--------------~I
I
,~.i-t~R-HHZ-------------------t
j4" HOD"
~,
I

,..

'tHOO'

.'

I

_____________________
'_tR_LN
__
Z<::::X~-------r~.~~.Jc:::)~---------------07-00, OP
I

Not.:

1. Th••• two algnaIa may b. apphd stmuItaneously.

~t •

,;88 by FuJitsu MtcroeleCtronlca. Inc.

6-17

May 1988
EdItIon 1.0

FUJITSU

MB87030/31
tinued)
Parameter

De.lgnator

Unit

tet.F+ 10

2tCLF+ 80

ns

Not•• :

1. R.fer to -Clock SI;n-'- timing for definition of tCLF'
2. Cycle tm. for Vif when lnteJ"Npt II contlnuoU8.

i+-tCLF-'

m~~
1
1

tCHA-..

1...-

________~(~----~,'~l------------~Nj~--~~---------------------------INTR

I

j....- t'NHR---'1
1

Wf

\

(
'4
I

\
tWRCY

..I

1

1

May 1988
Edition 1.0

MB87030/31
AC CHARACTERIST1CS (Continued)
DMA Interface

~i?m$tria::tt?:j}~}f:!%1t!~Hti~Wl~N{Nt~:f:!:/~~t~!~@J~!@li:!~!!!;!:i~~1j{i!i~~!i::!tiM!lijiW!!~i!!!jji!~r~i~){tfMW~;:!~lWmrm:~:t!Ml!!~@f:!j!MiimIt!~iWWi~!~~j~!!i;~!!!i@it%MtM*)j)~mjj:)j):t;J:~~tItI~~lfnj!j
Valuea

De.lgnator

Parameter

Min
OREO HIOh to ORESP High

tORRP

tCl,F (Nota,

ORESP High to OREO Low

tRPeR

10

OREQ Low to DREO High

tOlD'"

ORESP PuI•• WIdth

tRPSW

0
50

DRESP Cycle Time (')

tRPCY

ORESP Cycle Time (2)

tRLRH

Typ

Max

~5

80

Unit

ns
ns

ns
nl
ns
ns

2tcI.F
3tcI.F

Note:

1. Refer to ·Clock Signal- timing for definition of tCI.F'
I

OREQ
----{

tRPeR

I.-..JW
I

!..- tORq~
ORESP

1

I

,...........
l
I t rtO~H
- - - - - - -______,_________________________________

I

I

J

I
.....~-I

tRPCY---~.1
(,

\___~I

I

"

1_

-----~I

I~

I

\-.._-

_ _ _.JI

~ tRPSW-..I...~----- t;:u;:tH _ _ _ _-'.~l
I

Parameter

I

I

Value.

De.lgnator

HIN High to HOB7-HOBO.
HOBP Oata Output

t...a

OREO High to Data EstabDsh

tORDv

DRESP Low to Oata Chang.

tRPOV

REOI or ACKI High to
OREQ HIgh'

tRAOR

Unit

Typ

Min

Max

40

n.

60
90

n.
ns

3tCLF' + 70

na

10

15
55

15

Not•• :
1. When SPC recelv" REO (Initiator) or ACK (Target) with an empty FIFO durin; OMA (harc:tware ) transfer.
2. Refer to ·CIock Signal- tImIno tor definition of tc::u:.

REQI

or ACKJ

----________________

~v

-.1

OREQ

DRESP

HIN

I

tRAeR

J'!:::

'

--------------------------------~~t~

I

--_____________________' ____~~r--\~-------------------------~('----------------------~------~;-----------------'-'1
t-t

HOB7-HOBO. HOBP

~ • 1111 by Fujltsu~. Inc.

I

tAPOV

I• ...a ~I,_--------~I-_-------~I-----J
1

I

I

~

Unpredictable

6-19

~

OAT A 1

OAT A 2

May 19BB
Edition 1.0

FUJrrSU

MB87030/31
AC CHARACTERISTICS (Continued)
Paramet.r

Oeslgnator

Typ

Min
HIN Low to HOB7-HOBO.
HDBP (High Z)

t!-IIHZ

Oata Bus Setup

tHOSS

20

Oata Bu. Hold

tHOBH

20

OREQ Low to ORESP (Note)

t~p

ORESP Low to REQO or
ACKO HI~

tDRAA

UnIt

Max

40

ns

n.
4tc~

+ 11S

Not •• :

1. Refer to ·Clock Signal- timing for definition of tCLF.
2. The Indicated timing Is Invoked If SPC receive. DRESP when the Internal data buffer Is empty dur1ng a OMA (hardware)
transfer. The timing parameter Is waived for ACKO when the last byte Is transferred with the SPC serving as an initiator.

It4 tDRRA..,1,.-_ _ _ __
I

REOO or
ACKO
DREQ

DRESP

HIN

----------------~I

~

Y

!

(Note)

1'----------1
.. ,
~tOlAP

------------------------~I

\~___________
,
I

--------------~I

~~----------------------------~1----------------.J
I

',.t...,.z . .',

HDB7-HOBO, HOBP

'... tH08S ........
t H08H
I
,

______Jj~----------------~<

I

DATA 1

Note: In the following ca.e•• the OREQ .lgnaJ become. inactive aeynchronoully wtth the ORESP
"gnal to .top refetcNng data during an output operation:
• The Transfer Pause command I. Issued when the SPC I••ervtng a. a TARGET
•
The Transfer Phase Is changed when the SPC I. serving as an INITIATOR
In the •• case., the last OAESP signal response mlBt not exce.d tOl.JVl"

>~---------

May 1988
EdItIon 1.0

FUJI'rSU

MB87030131
AC CHARACTERISTICS (Continued)
SCSI Interface (Selection Phase)

Parameter

Valu••

O•• lgnator
Mln'·2

Bus Free TIme

tBF80

BSYO High to ID Bit High

tSHIO

BSYO HIgh to Prioritize

tARB

Data Bus Valid (HIOh Priority
Bit 1 to PrIoritize

0

Max

Unit

ns

"teu:+ 50
(6 + n) x
teu: + 5

tSFR

BSYI Lew to BSYO High
(Start of arbitration)

Typ

(7 + n) x
t etr+ 65

20

55

ns

32tcu:- "0

ns

70

ns

S

ns

tAlOv

Data Bus ValId (Low Priority
Bit I to Prioritlz.
Bus Usage Permission Granted
to SELO High

tAWSO

0

"5

na

SELO High to Data Bus (lD) Send

tsoio

, 1tC'..F- 30

ns

SELO High to INIT High

tSCIT

11tCLF- 30

nl

IMT High to A TNO High

tlTAT

5

Data Bus (Io) Send to BSYO Low

5

25

BSYO Low to BSYI Low

teoBI

0

BSYI High to SELO Low

tBISO

2tC\.F+ 5

ns

BSYI High to Data BUI (lo) Hold

tBICH

2tcLF+ 5

ns

SELO Low to INTR High

tSCIA

35

ns

SELl HIOh to BSYO. 10 Bit Low

tSBcR

3tCLF+ 115

na

Prioritize to eSYo. 10 Bit Low

tpsCA

125

nl

Copyr1ont •

,;&8 by Fujitsu

MicroeleCtronics. Inc.

ns

o

Notes:
1. Refer to -Cloek Signal" timing for deflnltlon of
2. n = TeL register set yawe

2tCLF+25

ns

tICaL

2tCLF- 50

teu:.

6-21

May 1PB8
Edition 1.0

FUJITSU

MB87030/31
AC CHARACTERISTICS (Continued)

I

\

BSYt

I

,...... taFR
I

'!linn

~

"

taFBo

~

t saCJil

taoBl --.;

I

tAWSO-"

,4-- tARS~:

1

I

S080 (10 bit)

I

~,.
--.:.....J
,
I

tBHO

,r-.....____~----------I:~-~ltBISO

I
I

1

I

1

t.

~

1""'--------

.:

~~----~------'
tacH
'i
,I
,....------------- ,----I

_____

\""_ _ _ _ __

.. I

-----~---------~~i~(,....-tSOID--I

,

~.

===-____~~--~A~--~--~:-JI:

SELO

a..I

:
~ __I
,\ - - ,
,"""- - - - - - - ' - - - - - - - - - - - - - - I
~ _____
tPBCR .....
,......,
tIDal
" - -'
I
_...;.________
.l.._____

_ _ _ _..J,
1
I

SEW

/1,.------

",, _ _ _.I.

ir----~'~~~~------~,~---------W\

BSYO

\

,

I

1

"

:\~-:

~ -- l.--

I

I

I
I
,"

~-)----

~~------~(-*I.....i--~\~----i

SOBe (10 bit)

\,_1

t --

S080 (Except 10 bit)

sose (Except 10 bit)

:::x--------:-...:.--.. .X.
I

SOBI7-S0BIO, SOBIP

I.

""'-------------------------~""'----

,

,.......---- tAlOV---"

1100

i

I

~ t SOIT---+t

______________________________________

--J(r-I------------~~---------

INIT
~I

ATNO

I
I

(

Ir-----------~--------t

t SCIR
INTR (Command Complete)

t

t

,..--..,

,
----------------------------------~,--~y----

JAay

1_

Edlrlon 1.0

MB87030J31
AC CHARACTERISTICS (ContInued)
u1EJAilllc~aZJ!kjI~lf~Y,~:': ::::::~::~~ -::~',.'~::~~j:~!:Z;~~7~~Diid§02;;t~~
Parameter

au.

au.

Free to Data
Send

Valuea

Dealgnetor
(10)

Mint,.

Unit

Typ

Max
(7 + n) x
t arlS

,.

tfIIIID

(I + nJ x
teur + 5

ID Send to SELO HIgh

tlD8C)

11tcur- 50

11tcur- 15

l1tcur+ 25

M

10 Send to IN1T HIgh

tar

11teur- 50

11tcur

11tcur+ 40

INIT High to ATHO HIgh

tlTAT

-5

BSYJ HIgh to SELO Lew

tllSO

2teur+ 5

,.
,.

tBICH

2teur+ 5

BSY1 HIgh to Data

au. (10) HOld

SElO Low to INTR HIgh

5

25

0

35

na

na

tsaR

na

Not.a:
1 .. Refer to - 00cIc sap- t.rrq for deftn.'tIon of t eLF.
2. n. TCl register let value

BSYt

..........________________________~(r--------------..........----.....--

~~

BSYO

I

SEU

SELO

.'•-

\

•

J

1
tDSo-----.,

I-

~I.

~

(10)

tBIOH

I

I

1

S09E7-S0BEO. SOBEP

-II

:X

1

S0907-S0900, SOBOP

1
• I tBlSO

I

'I

9(

I

1100
I

INIT

" - - - - tDIT ----..~I
1

......------------------~(-......----~----------------'1
I

ATNO

:~

trTAT

.....________________________ __
~l

--.,a
INTR (Command Complete)

I

6-23

I

...- t selR

1

May 7988

Edition 7.0

FUJITSU

MB87030/31
AC CHARACTERISTICS (Continued)
Parameter

Value.

De.lgnator
Min

SEW High to BSYI Low

tSIBI

Data Bus (10) VaRd to BSYI Low

tlO8l

0

1/01 Low to BSYI Low

t_

O

BSYI Low to BSYO HIgh
(Response time)

tSLBO

"'CL,F' + 5

tsoo

20

BsVO High to sEU Low

taoSi

0

ATNI High to SEU Low

tATSI

0

tSLTG

3tCLF+ 5

T ARG High to Phaee Signal Output

tTGPH

-s

1/00 HIQh to Data Bus Enable'

tlODE

"tCLF- 30

SEW Low to INTR Htoh

tSUR

-

Unit

Max

0

BSYO High to Data Bul (IDJ Hold

SEW Low to T ARG Htoh

Typ

Note.:
1. Refer to ·Clock Signal- timing for deftnttlon of tCLF
2. In cas. of bit a (110 out) of PeTL reQister Is .et In advanc•.

StCLF+ 60
.M

4tCLF+ 60

10
4teLF+ 20

30
4tar+ 70

ns

May 7He
Edition 7.0

MB87030131
AC CHARACTERISTICS (Continued)

:'--____-.1'
.11

"I

1

I

tlO8l

~

I

~~• 1I~------------------------I
•

x::::

I

I

----~~----~·-'·~i-----------

--~,~----------~-----------~
(

ATNI

_________________~? 1u u u u
_u

tATS! ....--.,..

__________________________________ __

", tSLTG

I

TARO

~

I
_Jl~---,-----------

,

, t

I~I

_______________________________________ ________
TGPH

l~

MSGO

I

C/OO

1100

____________________________ ______
~

____________________________

I
~A~

,

~------~l~--------

~
I

SOB07-S0BOO, SOBOP

_______

I

----------------------~----------~~------------------------------~I----------~~~------I

I

SOBE7-S0BEO, SOBEP

I

t~~1

___________________________1
I

INTR (Selected)

eq,yrlght •

,gas

tlOOE

by Fujitsu Mk::roet.c:1ronics. Inc.

&25

May 7988
Edition 7.0

FUJrr5U

MB87030/31
AC CHARACTERISTICS (Continued)
Parameter

Values

Designator
Min

Typ

Unit
Max

ns
ns

Data Bua (10) Valid to SEU Hiott

toSi

0

1/01 Low to SELl Hiott

tlSi

0

SEU High to BSYO High
(Response time)

tSLBO

2tCLF' + 5

BSYO Hiott to Data Bu. (10) Hold

taco

20

ns

BSYO Hiott to SEU Low

taos

0

n.

tATS!

I)

SEU Low to TARa High

tSLTG

3teu:+ 5

T ARQ High to Phase SlQnaI Outputl

tTGPH

-5

1/00 Hloh to Data Bus Enable

tlOOE

"teu:- 30

SEU Low to INTR High

tSLA

A TNI

HIoh to

SEW Low

Note.:
1. Refer to -Clock SIQnaI- tIrnIno for deftnltlon of teu:
2. In case bit 0 (1/0) of PeTL reolster Is s.t In advance.

3teu:+ 65

.. teu:+ 60

10

n.

ns

30
3tCLF+ 65

ns
ns

M'I18ea
Edmon 1.0

MB87030131
AC CHARACTERISnCS (Continued)

BSYI

________________________

~I

I~t~~

BSYO

"I.

:
------------~~).
,_1--".'

It----.!.. taos

i

I

SEU

.....

I

__
____________x:::
::::1~__________________~-----------~
:::x~~

--.J•

1101

ATNI

\~----------------

,

tBOlO •-...-.-..,,,..:.,___________________

tl)8l ,
..
I

S08l7-S0BI0. S081P

_________________________________

"-I

~(I~O)_ _ _ _~X,~~,

tIS!

-----------------------------...rr? --_1_ ----- -tATS! •. - - . . . ' .

• I tSl.TG

__________________________________
•

TARG

I
-Jl~------------

I

I

.'--"',

MSGO

____________________________ ______
~

t

-JI~

TGPH

_________

I

C/OO

______________________________

~----

__

-J~~--------I

1100

____________________________~------Jl~-------~' : -_
tlOOE_ __

I

SDe07-S08~,

SOBOP

SOBE7-S0eEO. SOBEP

--------------------~-----------,~----

____________________

t~

INTR (Selected)

I

~----------A------I
I
"'I
..t--~.
I __________________ _

________________________

CopvrIQM • 1888 by Fujitsu Mlc:raetectronles. Inc.

6-27

~

~l

May 7988
Edition 7.0

FUJITSU

MB87030/31
AC CHARACTERISTICS (Continued)
SCSI Interfac~ (Reselection Phase)

BSYI low to BSYO High
(Start of arbitration)

(7 + nJ x
t
+ 85

Data Bus VaJld (High Prlortty

Bit) to Prlorttlze

70

"'

tAlOT

Data Bus Valid (low Prlortty

5

Bit) to Priorttlze
tAWSO

Notes:
,. Refer to "Oock Signal" timing for def1nltlon of tClF.
2. n = Tel register set value

0

n.

M

45

n.

May 18"
Edition 1.0

MB87030131
AC CHARACTERISTICS (Continued)

. .

I
..

~

BSVI

...r

I
.... t8FA

~

:

__....!__rI':.l

BSYO

~

:

~ tsacA
\_ _

•

tARa

S080 (10 bit)

SOBE (10 bit)

~ tBHO

I

---l.·

·

sose

(Except 10 bit)

I..- taeo

-! !-

2 teu: + 6 (MIn)

l.~i-----:

1 + teu:

tlO8L
•
~'." II-----'!-'• ---i-:-----~-il

:•

!\,.-+;----

i..... tsoo--1
,~-: '-- l--.. '
.. .
~

.J ~

~ tK)H

• ~

: J I

.i_~_____

. ..

~""'---'f"\"""'"!-+!-"",------r- _

L~----

~-:-'AWSO

SOBO (Except 10 bit)

..

.....

:

. !

..i

8081

1:--------!':....1.".- - - - - - !.i i.
~
'NC -I j. }~--

~ __

I-tBFBO :

r - .

SELO

I·

:

"1
~ tPBCA
--~:___1....-_-_ ....~ ....It'
j.

SEU

... "t

.
m~Yh~'l~------~----~l
-I

:

------------~i----------~~~------------------~*~---.
..

________~~----~l--~---------t---~

SDS~~DB~.SDB!P ~~_ _ _ _ _ _~~_ _ _X~

~ tlCBl

__ ·__________
~~

~~

tAlOT ----.i I" t SOTa+1
'---~!------------~------­
--------------------------~ltTGPH:
~ ~
t-

TARG

MSGO

C/OO

·

------------------------------~------------------­

··

--------------------------------1~---------~-----­
_________________________ ··
~i

1/00

INTR (Command Complete)

tSCIA-..t

~

---------------------------------~y--

Copyright • 1;aa by FuJitsu Microelectronics. Inc.

~29

/

May 1988
Ea/rion 1. 0

MB87030/31
AC CHARACTERISTICS (Continued)
Parameter

Value.

Oe.lgnator
Min

Unit

Max

Typ

SEU High to BSYI low

tSIBI

0

ns

Data Bus (10) Valid to BSYI low

tCBI

0

1101 low to BSYI low

tlBl

ns
ns

BSYI low to BSYO High
(Response tlmel

tSlBO

BSYO High to Data Bus (10) Hold

tBOlO

0
4ta,F+ 5
(Note)

nl

n.

20

BSYO High to SEli low

taoS!

0

SEU low to BSYO low

tseo

2ta,F+ 5

SELl Low to 1101 Hold

t5IM

4ta,F+ 20

SEU Low to INTR High

tSLA

SEll low to INIT High

tSllT

3tCl,F+ 5

ns
ns
ns

INIT High to Data Bus Enable
(WIth 1101 at low level)

tfTOE

10

ns

3tCLF+ 60

"'ns

3tct,F+ 65

Note:
1. Ref.r to -Clock Signal- timing for deftnltlon of ta,F

BSYI

,
,'-+--tslBI
,

BSYO

SEll

--l.

~
•

I

~4---t&B~(~

I

__________ _______________
I

~\~

,

1+---+'
I

tBOlD '..........
I

I

,

~

,

"I~ tSIBO~

t80S! , .

,

I

I,

:::X--~i~------------------~~---Ti----------------------:
X:

SOB17-S0810, SOBIP

--..

1101

/
•

I~ tlBl

ts.. ~

_________.....l'-----------;.:--t~- ---------.- r--- SlIT----,
__________________________
~
,
'.,...---_____________________________~---------------4~---I

INIT

t

'

~-----JJ~---------

trroe

SOB07-S0BOO, SOBOP

SOBE7-S08EO, SOBEP

____________________
t SUR

INTR (Reselected)

,,

~---------~r------

.11-0---1".'
"
~-----------------,....

---------------------------~I

May 1988
EdItIon 1.0

FUJITSU

M887030/31
AC CHARACTERISTICS (Continued)
SCSI Interface (Transfer Phase)

Values·

Oeslgnator

Parameter

Typ

Min

1100 H10h to Data Bus Enable

tlooe

Data Bus Valid to REQO H10h

to~c

ACKI High to Data BUI Hold

tAKOv

15

REQO High to ACKI HIOh

tFl.HAH

20

ACK! HiC;;h to REOO Low

tAHRL

10

REOO Low to ACKI Low

tRLAL

0

ACKL Lew to AEOO H:.;h

tAlFlH

10

~Ion

tAHRH

2tc:"'1: + 3

-

AC>

"0

m

3

0-

~

(D

CO
C1I
05698A

CONNECTION DIAGRAM
Top View

Wcc
DAL.
DAL.
DAL ..
DAL..
DAL,.
DAL. a
OAL ..
DAL ••

.....
"'n
.........

....
~

-"'a

Au

aJl
TJI

CUlt

ac:uc

T CUl

c0001450

Note: Pin 1 is martted for orientation

TYPICAL ETHERNETICHAEPERNET NODE

TII#

I
I

I

I

... - A"~"'_ACf

l-----L..J

L1

DTI.-DATa~~

MAU -

_cu. ACCESS UIII'f

OTt

~

__ ~________ ~L _________ --,

I

I

I
I
I
I

l~""

--

I

UIOCI

II--~----~------~­
~~

L_______________________

I

~

AFOOO473

ORDERING INFORMATION
AMD products are available In several packages and operating ranges. The order number IS formed by a combination of the following:
Device number, speed opllon (if applicable), package type, opera ling range and screening option (if desired)
Am 7990

Device Type----.J

g~~LL

Valid Combinations
Screening Option
B = Burn-In
Blank = Standard processing
Temperature
C - Commercial

aoc

to 70°C

Package
o - SIDE BRAZED
P - plastic
L a lead less chip carrier

2

Am7990

DC

Valid Combinations
Consult the local AMD sales office to confirm
availability of specific valid combinations, to
check on newly released valid combinations,
and to obtain additional data on AMD's standard
military grade products.

PIN DESCRIPTION

DALooDAL15

Deta/Addre.. UnM (Input/Output 3-Stllte)
The time multiplexed Address/Data bus. During
the address portion of a memory transfer.
DALoo - DAL 15 contains the Iowef 16 bits of the
memory address. The upper 8 bits of address
are contained in A,S-A23.

Byte selection may also be done using the BYTE
line and DAloo line, latched during the address
portion of the bus cycle. The LANCE drives
BYTE onty as a Bus Master and ignores it when
a Bus Slave setection is done (similar to §MO.

mJ1).

Byte selection is done as outlined in the following table.

During the data portion of a memory transfer.
DAloo - DAl, 5 contains the read or write data.
depending on the type of transfer.

BYTE DALoo

The LANCE drives these lines as a Bus Master
and as a Bus Slave.

lOW
LOW
HIGH
HIGH

High Order Addresa Bus (Output 3-Stllte)
The additional address bits necessary to extend
the DAl lines to access a 24-bit address. These
lines are driven as a Bus Master only.

READ

in the current bus cycle. This signal IS an output
when the LANCE is a Bus Master

In an effort to be compatible WIth the variety of 16-bit
microprocessors available to the designer. the LANCE may be
programmed to swap the position of the upper and lower order
byles on data involved in transfers with the internal FIFO.

low - Data is placed on the DAL by the chip
The sagnal is an input when the LANCE is a Bus
Slave.

Byte swapping is done when BSWP - 1. The most significant
byte of the word in this case will appear on DAL lines 7-0 and
the least significant byte on DAL tines 15-8.

High - Data is placed on the DAL by the chip
Low - Data is taken off the DAL by the chip

When BYTE = H (indicating a byte transfer) the table Indicates
on which part of the 16-bit data bus the actual data will
appear

(Output 3-stllte)
Pins 15 and ,6 are programmable through bit
(OO) of CSR3

Whenever byte swap is activated, the only data that is
swapped is data traveling to and from the FIFO.

Iii1

If CSR3 (00) BCON - 0
PIN 15 - ~ (Output 3-state)
PIN 16 - IDJ1 (Output 3-state)

Mode BIts

byte(s) on the DAl are to be read or written
during this bus transaction. The LANCE drives
these lines only as a Bus Master. It ignores the
Byte Mask lines when it is a Bus Slave and
assumes word transfers.
IS

done as

Iiii1 I1iO
lOW
lOW
HIGH
~IGH

LOW
HIGH
LOW
HIGH

BSWP=O
and BCON= 1

BSWP= 1
and BCOH 1

BYTE = Land
DALoo so L

Word

Word

BYTE'"' L and
DALoo "" H

Illegal

Illegal

BYTE'"' H and
DALoo '" H

Upper Byte

Lower Byte

BYTE'" Hand
DALoo '"' L

lower Byte

Upper Byte

Signal Une

eM; (Byte Mask). This indIcates the

Byte selection using Byte Mask
described by the following table.

Lower Byte
Upper Byte

Byte Swapping

High - Data is taken off the DAL by the chip

Wo.

Whole Word
Illegal Condition

~ is a bus request daisy chain output. If
the chip is not requesting the bus and it receives
HLDA. ~ will be driven Low. If the
LANCE is requesting the bus when it receives
RrnA. ~ will remain High.

(Input/Output 3-StIIte)
Indicates the type of operation to be performed

BMo.

LOW
HIGH
LOW
HIGH

Whole Word
Upper Byte
lower Byte
None

=

Chip Select (Input)
Indicates, when asserted, that the LANCE is the
slave device of the data transfer. CS must be
valid throughout the data portion of the bus
cycle. ~ must not be asserted when HLDA is
Low.

If CSR3 (00) BcaN = 1

PIN 15 - BYTE (Output 3-state)
PIN 16 os B'O'SAi {OYTPUT
~_l"NC(1

WF004540

Figure 4. Bus Slave Write Timing

WRITE SEQUENCE

READ SEQUENCE

The write cycle IS SImilar to the read cycle except that the
DALoo-DAL15 hnes change from containIng addresses to data
after either ALE or AS goes InactIve. After data IS valid on the
bus. l>AS goes active Data to memory is held valid after [)AS
goes inactive. Refer to Figure 5b.

At the beginning of a read cycle. ~. READ. and DAS are
asserted ADR also must be valid at thiS time (If ADA IS a "1,
the contents of AAP are placed on the DAL hnes Otherwise
the contents of the eSA register addressed by AAP are placed
on the DAL lines,) Atter the data on the DAL hnes become
valid, the LANCE asserts~,~. READ.~. and ADA
must remain stable throughout the cycle Refer to Frgure 3

LANCE IN BUS SLAVE MODE

WRITE SEQUENCE

The LANCE enters the Bus Slave Mode whenever CS
becomes active. This mode must be entered whenever writtng
or reading the four status control registers (CSRo. CSA,.
eSA2. and CSA3) and the Register Address POInter (PAP).
RAP and eSRo may be read or written to at anytime. but the
LANCE must be stopped (by settlrtg the stop bit", eSRO) lor
CSR 1. CSA2, and eSR3 access

This cycle is similar to the read cycle, except that dUring thiS
cycle. READ is not asserted (READ IS Low). The DAL buffers
are tnstated which confrgures these hnes as Inputs The
assertIOn of READY by LANCE Indicates to the memory
deVice that II",e data on the OAL hnes t\ave been stored by
LANCE In ItS appropnate eSR register. es. READ DA'S. ADR,
and DAL < 1500> must remal r , stable throughout the write
cycle Refer to Figure 4

10

.. ..

•

OAS----~

DALo-OAL,S
(MAD)

0iU5
(MAO)

DiU
(MAD)

----~iI'lII'I III/IJ

-----"1

------"l

:;,----WFoo.551

Figure Sa. Bus Master Read TIming

11

T,

o

100

500

100

TeLK

~-----..."

OALo- OAl,S
(WRITE)

-----CY

OAlO _ _ _ _ _~
(WAITE)

~---~----~----~

OAll

~E) --------~
READ
(WRITE)

WFOO4561

Figure 5b. Bus Master Write Timing

12

J
~

~Ir-------~

MlSllASlVI
DlWEIIIS

-----------0(1~

~----------------~~~------------~~
WFOO4570

Figure 6. Bus Acquisition TIming
Note: 1. ~ is an asynchronous input to the LANCE and is not part of the Bus Acquisition timing.
When ~ is asserted, the LANCE becomes a Bus Slave.

I

I

DIFFERENCES BETWEE~ ETHERNET
VERSIONS 1 AND 2

DIFFERENCES BETWEEN IEEE·802.3 AND
ETHERNET

a. Version 2 specifies that the collision detect of the transceiver must be activated during the interpacket gap time.

a. IEEE-802.3 specifIeS a 2-byte length field rather than a type
field. The length field (802.3) described the actual amount of
data in the frame.
.

b. Version 2 specifies some network management functions.
such as reporting the occurrence of collisions, retries and
deferrals.

·b. IEEE-802.3 allows the use of a PAD field in the data section
of a frame, while Ethernet specifies the minimum packet
size at 64 bytes. The use of a PAD allows the user to send
and receive packets which have less than 46 bytes of data.

c. Version 2 specifies that when transmIssion IS terminated,
the differential transmit lines are driven OV diff. (half step).

A partIal list of significant differences between Ethernet and
IEEE-802.3 at the physical layer include the following:

I

Ethernet

IEEE-802.3

I

I End of Transmission State

Half Step

High State (Rev 1)
Half Step (Rev 2)

Mode
I Common
Voltage

±5.5V

0- +5V

Less than
1mA

1.6mA ±40%

Input Threshold

±16OmV

t175mV

Fault Protection

16V

OV

I

Common Mode
Current
Receive±. CoIlision±

13

Of

PROGRAMMING SPECIFICATION

port (RAP) during a bus slave transaction. During a subse-

quent bus slave transaction, the data being read from (or

This section defines the control and Status Registers and the
memory data structures required to program the Am7990
(LANCE).

written into) the data port (RDP) is read from (or written into)
the GSA selected in the RAP.

PROGRAMMING THE Am7990 (LANCE)

Once written, the address in RAP remains unchanged until
rewntten.

The Am7990 (LANCE) is designed to operate in an environment that includes close coupling with a local met'nOfY and a
mICroprocessor (HOSn. The Am7990 LANCE is programmed
by a combination of registers and data structures resident
within the chip and in memory. There are four Control and
Status Registers (CSRs) within the chip which are programmed by the HOST device. Once enabled, the chip has the
ability to access memory locations to acquire additional
operating parameters.
The Am 7990 has the ability to do independent buffer management as well as tranSfer data packets to and from the Ethernet.
There are three memory structures accessed by the Chip:

To distinguish the data port from the address port, a discrete

110 pin is provided.
ADA 1/0 Pin
L
H

Port
Register Data Port (RDP)
Register Address Port (RAP)

Regiater Data Port (RDP)
15
CSROATA

1. Initialization Block - 12 words in contiguous memory starting
on a word boundary. It also contains the operating parameters necessary for device operation. The initialization block
is comprised of:
•
•
•
•
•

Bit

Mode of Operation
Physical Address
Logical Address Mask
Location to Receive and Transmit Descriptor Rings
Number of EntrieS in Receive and Transmit
Descriptor Rings

15:00

CSR Data

2. Receive and Transmit Descriptor Rings - Two ring structures, one each for incoming and outgoing packets. Each
entry in the rings is 4 words long and each entry must start
on 8 quadword boundary. The ~tor Rings are comprised of:

Writing data into RDP writes the
data into the GSR selected in
RAP. Reading the data from the
ROP reads the data from the CSR
selected in RAP. GSR" GSR2
and GSR3 are accesSIble only
when the STOP bit of CSAo is
set.
If the STOP bit is not set whtle
attemphng to access eSA"
eSR2 or eSR3, the chip will
return READY, but a READ
operation Will return undefined
data. WRITE opera lion IS ignored

• The address of 8 data buffer
• The length of that data buffer
• Status Information associated with the buffer

3 Data Buffers - ContiguouS portions of memory reserved for
packet buffering Data buffers may begin on arbitrary byte
boundaries.

Register Addre.. Port (RAP)

In general, the programming sequence of the chip may be.
summarized as'
1 Programming the chip's CSRs by a host device to locate an
InlllalizatlOft block in memory. The byte control, byte addressing,
and address lalch enable modes are defined here also.

L

CSII •

o

~------------~----~5

AFOO1490

2. The chip loading itself with the information contained within
the Initialization block.

Bit

3. The chip accessing the descriptor rings for packet handling.

15:02

AES

CONTROL AND STATUS REGISTERS

01:00

eSR(1:0)

There are lour Control and Status Registers (CSRs) resident
Within the chip. The CSRs are accessed through two bus
addressable ports, an address port (RAP) and a data port
(ADP)

ACCESSING THE CONTROL AND STATUS
REGISTERS

Name

DeKrlptlon
Reserved and read as zeroes
eSR address select. READ!
WAITE. Selects the eSA to be
accessed through the RDP RAP
IS cleared by Bus RESET
eSA(1:0)

eSA

00

eSAo
eSA,
eSA2
eSA3

01
10
11

The eSAs are read (or written) in a two step operation. The
address of the eSR to be accessed is written into the address

'4

CONTROL AND STATUS REGISTER
DEFINITION

BIt
CERR is READ/CLEAR ONLY
and is set by the chip and cleared
by writing a "" , into the bit.
Writing a "0" has no effect. It is
cleared by R'EID or by setting
the STOP bit. CERR error will not
cause an interrupt to occur
(tNTR - 0).

Control and Status Aegiater 0 (CSAo)

....-

CIIJIIt

_-----.J

12

MISS

MISSED PACKET is set when the

receiver loses a packet because
it does not own any receive
buffer. indicating loss of data.
Silo overflow is not reported
because there is no receive ring
entry in which to write status.
MISS is not valid in internal
loopback mode.

The LANCE updates CSRo by logical
"ORING" the previous and present value of

CSRo·
Description

BIt
15

ERR

When MISS is set, an interrupt
will be generated if INEA = ,.

ERROR summary IS set by the
"OM" of BABl, CERR, MISS and
MERR ERR remains set as long
as any of the error flags are true.

MISS is READ/CLEAR ONLY.

and is set by the chip and cleared
by writing a .. ,,, into the bit.
Writing a "0" has no effect. It is

ERR is read only; writing it has no
effect. It IS cleared by Bus
~, by setting the STOP bit,
or clearing the individual error
flags.
14

BABl

cleared by ~ or by setting
the STOP bit
11

MERR

BABBLE is a transmitter timeout
error. It indicates that the
transmitter has been on the
channel longer than the time
required to send the maximum
length packet.

When a Memory Error IS
detected, the receiver and
transmitter are turned off (CSRo.
TXON =- O. RXON = 0) ana an
interrupt is generated If INEA = ,.

BABl IS a flag which indicates
excessive length in the transmit
buffer. It will be set after 1519
data bytes have been
transmitted; the chip will continue
to transmit until the whole packet
is transmitted or until there is a
failure before the whole packet IS
transmitted. When BABl error
occurs, an mterrupt will be
generated if INEA = 1.

MERR is READ/CLEAR ONLY,
and is set by the chip and cleared
by wntlng a ··1'· Into the bit
Writing a ·'0·' has no effect. It IS
cleared by RESET or by setting
the STOP bit

10

RINT

BABl is READ/CLEAR ONLY
and is set by the chip, and
cleared by writing a "'" into the
bit. Wnllng a "0" has no effect. It
is cleared by RESET or by setting
the STOP bit.

13

CERR

MEMORY ERROR IS set when
the chip is the Bus Master and
has not receIved READY within
25.611-s after assertIng the
address on the DAl hnes

RECEIVER INTERRUPT IS set
when the chip updates an entry In
the Receive Descnplor Ring for
the last buffer received or
reception is stopped due to a
failure.
When RINT is set. an Interrupt IS
generated If INEA = 1
RINT is READ/CLEAR ONLY.
and is set by the chip and cleared
by writing a "1" Into the bit .
Writing a "0'· has no effect. It is
cleared by RESET or by setting
the STOP bit.

COLLISION ERROR indicates
that the colhSlon Input to the chip
. failed to activate within 211-s after
a chip-initiated transmission was
completed. The collision after
transmission is a transceiver test
feature. This funcllon is also
known as heartbeat or SQE
(Signal Quality Error) test.

09

15

TINT

TRANSMITIER INTERRUPT is
set when the chip updates an
entry in the transmit descriptor
ring for the last buffer sent or
transmission is stopped due to a
failure.

Bit

Description

DHcrIptton

Bit

When TINT is set. an interrupt is
generated if INEA" t.

05

RXON

RECEIVER ON indicates that the
receiver is enabled. RXON is set
when STRT is set if DRX - 0 in
the MODE register in the
initialization block and the
initialization blOCk has been read
by the chip by setting the IN IT bit.
RXON is cleared when IDON is
set from setting the INIT bit and
DRX - , in the MODE register. or
a memory error (MERR) has
occurred. RXON is READ ONLY;
writing thfs bit has no effect.
RXON·is cleared by RmT or by
setting the STOP bit.

04

TXON

TRANSMITTER ON indicates
that the transmitter is enabled.
TXON IS set when STRT is set it
DTX - 0 in the MODE register in
the initialization block and the
INIT bit has been set. TXON is
cleared when IDON is set and
DTX - , in the MODE register. or
an error. such as MERR. UFLO or
BUFF, has occurred during

TINT is READ/CLEAR ONLY and
is set by the chip and cleared by
writing a "'" into the bit. Writing a
.. 0" has no effect. It is cleared by
~ or by setting the STOP
bit.

08

IDON

INITIALIZATION DONE indicates
that the chip has completed the
initialization procedure started by
setting the INIT bit. When lOON IS
set. the chip has read the
Initialization Block from memory
and stored the new parameters
When IDON is set. an interrupt is
generated if INEA - ,.
IDON is READ/CLEAR ONLY.
and is set by the chip and cleared
by writing a "t" Into the bit.
Writing a "0" has no effect. It IS
cleared by ~ or by setting
the STOP bit.

07

INTR

transmission

INTERRUPT FLAG is set by the
"OR" of BABL. MISS. MERR.
RINT. TINT and lOON. If
INEA - 1 and INTR .. '. the INTR
I/O pin will be Low.

TXON IS READ ONLY; writing thfs
bit has no effect. TXON is cleared
by ~ or by setbng the STOP
bit.

INTR IS READ ONLY; writing thfs
bit has no effect. INTR is cleared
by RESET. by setting the STOP
bit. or by clearing the condition
causing the interrupt.

06

INEA

03

TOMD

INTERRUPT ENABLE allows the
INTR 1/0 pin to be driven Low
when the Interrupt Flag is set. If
INEA - 1 and INTR - 1. the INTR
110 pin will be Low. If INEA - O.
the INTR 1/0 pin will be High.
regardless of the state of the
Interrupt Flag.

TRANSMIT DEMAND. when sel.
causes the chip to access the
TransmIt Descriptor Ring without
waiting for the poIltime interval to
elapse. TDMD need not be set to
transmit a packet; il merely
hastens the chip's response to a
Transmit Descriptor Ring entry
inSertIOn by the host.
TDMD IS WRITE WITH ONE
ONL Y and is cleared by the
microcode after it IS used It may
read as a "'" for a short time
after It IS written because the
microcode may have been busy
when TOMO was set. It is also
cleared by ~ or by setting
the STOP btt. Writrng a "0" in thiS
bit has no effect.

INEA IS READ/WRITE and
cleared by RESET or by setting
the STOP bit.
INEA cannot be set while STOP
bit is set. INEA can be set In
parallel or after INIT andlor
STRT bit are set.

02

'6

STOP

STOP disables the Chip from all
external aCllvl1y when set and
clears the Internal logIC. Setting
STOP IS the equivalent ot
asserting ~. The chip
remains Inactrve and STOP
remains set until the STRT or
INIT bit IS set. It STRT. IN IT and
STOP are all set together. STOP
will override the other bits and
only STOP Will be set.

BIt

•

STOP is READ/WRITE WITH
ONE ONLY and set by RESET.
Writing a "0" to this bit has no
effect. STOP is cleared by setting
either INIT or STRT. eSR1.
CSR2. and eSR3 must be
reloaded when the STOP bit is
set.

01

STRT

L-L-_____________________________

1AOR (23:1II
~

AFOOO920

BIt

START enables the chip to send
and receive packets. perform
direct memory acCess. and do
buffer management. The STOP
bit must be set prior to setting the
STRT bit. Setting STRT clears
the STOP bit.

RES

Reserved.

IAOR

The high order 8 bits of the address of the first word (lowest
address) in the Initialization
Block.

CSR3 allows redefinition of the Bu Master interface.
RAP=3

STRT IS READ/WRITE and is set
with orte only. Writing a .. 0" into
this bit has no effect. STRT is
cleared by ~ or by setting
the STOP bit.
INIT

15:08
07:00

Control and Status Register 3 (CSR3)

If STRT and INIT are set
together. the INIT function will be
executed first.

00

READ/WRITE: Accessible only when the STOP bit of CSRo is
ONE. CSR3 is cleared by R'Em or by setting
the STOP bit in CSRo.

INITIALIZE. when set, causes the
chip to begin the initialization
procedure and access the
Initialization Block. The STOP bit
must be set prior to setting the
INIT bit Setting INIT clears the
STOP bit

I·----'m=
15

3

Bit
15:03

02

Name
RES
BSWP

=1

READ/WRITE: Accessible only when the STOP bit of CSRo is
a ONE. GSR, IS unaffected by RESET.
1

I_ _ _ _

'~,

AF000970

15:01

00

.

Name

Description

IADR

The low order 16 bits of the
address of the first word (lowest
address) in the Initialization
Block.

0

Description
Reserved and read as "0."
BYTE SWAP allows the chip to
operate if) systems that consider
bits (15:08) of data to be pointed
by an even address and bits
(07:00) to be pointed by an odd
address.
When BSWP .. 1, the chip will
swap the high and low bytes on
OMA data transfers between the
silo and bus memory. Only data
from silo transfers is swapped;
the Initialization Block data and
the Descriptor Ring entries are
NOT swapped.

0

L . . - - - - - - - _ I A D R (15:01)

Bit

1

AFOOO9OO

Control and Status Register 1 (CSR,)

15

2

L----------____ MS

If STRT and IN IT are set
together, the INIT function will be
executed first. INIT is READ/
WRITE WITH" 1" ONL Y Writing
a "0" Into thiS bit has no effect.
INIT IS cleared by ~ or by
setting the STOP bit

RAP

o

1

BSWP is READ/WRITE and
cleared by ~ or by setting
the STOP bit in CSRO

01

Must be zelo.

Control and Status Register 2 (CSR2)
RAP=2
READ/WRITE: Accessible only when the STOP bit of CSRo IS
a ONE. CSR2 IS unaffected by ~

AeON

ALE CONTROL defines the assertive state of ALE when the
chip is a Bus Master. ACON is
READ/WRITE and cleared by
~ and by setting tre STOP
bit in eSRo·
ACON

o

17

ALE
Asserted High
Asserted Low

00

BCON

BYTE CONTROL redefines the
Byte Mask and Hold I/O pins.
BCON is READ/WRITE and
cleared by R'EID or by setting
the STOP bit in CSRo.
BCON Pin16

o

~1

Pin15

Pin17

mlo

HOi])

~BYTE

Bit
06

INTl

~

All data transfers from the LANCE in the Bus Master mode are
in words. However, the LANCE can handle odd ~ess
boundaries and/or packets with an odd number of bytes.

INITIALIZA TION

The Lance will not receive any
packets externally when it is in
internal Ioopback mode.

INITIALIZA TION BLOCK

EXTERNAL lOOP BACK allows
the LANCE to transmit a packet
through the SIA transceiver cable
out to the Ethernet coax. It IS
used to determine the operability
of all Circuitry and connections
between the LANCE and the coaxial cable. Multicast addreSSing
in external loopback is valid only
when DTCR .. 1 (user needs to
append the 4 bytes CRG)

Chip InitializatIOn includes the reading of the initialization block
in memory to obtain the operating parameters. The following is
a definition of the Initialization Block.
The InitializatIOn Block is read by the chip when the INIT bit in
The INIT 'lit should be set before or concurrent
with the STRT bit 10 insure proper parameter initialization and
chip operation. After the chip has read the Initialization Block,
lOON IS set In CSRo and an interrupt is generated if INEA - 1.

GSRo is set.

TLEN-TDAA (23:16)
TDRA (15:00)
RlEN-RDAA (23:16)
RDAA (15:00)
LAORF (63:48)
LADAF (47:32)
LADAF (31:16)
LAORF (15:oo)
PAOR (47:32)
PAOR (31:16)
PADR (15:oo)

Higher Addresses

Base Address of Block

MODE

IADA
IADA
IADA
IADA
IADA
IADA
IADA
IADR
IADA
IADA
IADA

+22
+20
+ 18
+16
+ 14
+ 12
+10
+08
+06
+04
+02

In external loopback, the LANCE

also receives packets from other
nodes.
INTl IS only valid if lOOP = 1.
Otherwise, it IS tgnored

LOOPINTL LOOPBACK
o X No Ioopback. normal
o External
Internal

IADR +00

05

DATV

DISABLE RETRY When
DRTV = 1. the chip Will at1empt
only one transmission of a pack·
et. If there is a colliSion on the
first transmiSSion at1empt. a Retry
Error (RTRY) Will be reported In
Transmit Message Descriptor 3
(™D3)

04

COll

FORCE COLLISION ThiS btt allows the colliSion logiC to be tec;t·
ad. The chip must be in Internal
loopback mode for Call to be
valid If Call = 1. a COlliSion will
be forced during the subsequent
transmISSion attempt. This Will result In 16 total transmissIOn al·
tempts With a retry error reported
in TMD3

03

DTCR

DISABLE TRANSMIT CRC
When DTCR = O. the transmtner
will generate and append a CRC
to the transmitted packet. When
DlCR .. 1, the CRC logic is allocaled 10 the receiver and no CRe
is generated and sent With the
transmitted packet.

Mode
The Mode Register allows alt&ratton of the chlp's operating
parameters Normal operatIOn is With the Mode Register clear
15

14

ORl

on
L~
L..-----OT~

L..-_ _ _ _ _

cou.

L..-_ _ _ _ _ _ _ _ _ ORTY

L...._____________ Nn
L-_____________________ MS

L-___________________________________

~

AFOOO510

Btt

Name

Description

15

PROM

PROMISCUOUS mode. When
PROM - 1, a/l incoming packets
are accepted.

14:07

RES

INTERNAL looPBACK is used
with the lOOP bit to determine
where the Ioopback is to be done.
Internal loopback allows the chip
to receive its own transmitted
packet. Since this represents full
duplex operation, the packet size
is limited to 8-32 bytes. Internal
Ioopback in the LANCE is operational only when the packets are
addressed to the node itself.

RESERVED

18

0Img Joopback, OTCA - 0 will
cause a CRC to be generated on
the transmitted packet. but no
CAC check will be done by the
receiver since the CRC logic is
shared and camot generate and
check CAC at the same time. The
generated CAC will be written
into memory with the data and

00

packets and not access the Receive Descriptor Ring. ORX - 1
will clear !he RXON bit in the
CSRo when initialization is com-

pfete.
1

~--------11"ADR(47:01)

AFOOO520

any errors.
LOOPBACK allows the chip to

operate in full duplex mode for
test purposes. The packet size is
1imiter1 to 8-32 bytes. The received packet can be up to 36

Name
PAOR

PHYSICAL ADDRESS is the
unique 48-bit physical address
assigned to the chip. PAOR (0)
must be zero.

AFOOO5OO

Dncrfptor

BIt
63:00

LOOP - 1 allows simultaneous
transmission and reception for a
message constrained to fit within
the silo. The chip waits until the
entire message is in the silo before serial transmission begins.
The incoming data stream fills the
silo from behind as it is being
emptied. Moving the received
message out of the silo to mem0ry does not begin until reception
has ceased.

LAORF

The 54-bit mask used by the chip
to accept logical addresses.

If the first bit of an incoming address is a",,, [PADR (0) 11.
the address is deemed iogical and is passed through the
logical address filter.
OK

The logical address filter is a 64-bit mask composed of four
sixteerl-bit registers. LAORF (63:00) in the initialization block,
that is used to accept incoming Logical Addresses. The
incoming address is sent through the CRC circuit. Atter all 48
bits of tt.e address have gone through the CRG CIrcuit. the
high order 6 bits of the resultant CRC (32-bit CRG) are strobed
into a register. Ths register is used to select one of the 64-bIt
positions in the Logical Address Filter. If the selected filter bit
is a "1," the address is accepted and the packet will be put in
memory. The logical address filter only assures that there is a
possibility that the incoming logical address belongs to the
node. To determine if it belongs to the node. the incoming
Iog4caI address that is stored in main memory is compared by
software to the list of logical addresses to be accepted by this

In Ioopback mode, transmit data
chaining is not possible. Receive
data chaining is posstMe if receive buffers are 32 bytes long to
allow time for Iookahead.
DTX

BIt
47:00

L.ogJcaI Addr... Filter

+..

bytes (32
bytes CRG) when
OTCA-O. During Ioopback, the
runt packet filter is disabled because the maximum packet is
forced to be smaller than the
minimum size Ethernet packet
(54 bytes).

01

•

_ _-..-_ _I~w

H OTCA - 1 during Ioopback, the
host software must append a
CAC value to the transmit data.
The receiver will check the CRC
on the received data and report

LOOP

DISABLE THE RECEIVER caus-

ORX

es the chip to reject all incoming

can be checked by the host software.

02

D••alpllcM

BIt

BIt

DISABLE THE TRANSMITIER
causes the chip to not access the
Transmitter Descriptor Ring. and
therefore. no transmissions are
attempted. DTX - 1 will clear the
TXON bit in CSRo when initialization is complete.

node.
The task of mapping a logical address to one of 54-bit
positions requires a simple computer program (see Appendix
A) which uses the same CRC algorithm (used in LANCE and
defined per Ethernet) to calculate the HASH (see FlQUl'e 7).
The Broadcast address, which is all ones. does not go through
the Logical Address Filter and is always enabled. If the Logical
Address Fitter is loaded with all zeroes. all incoming logical
addresses except broadcast will be rejected. The multicast
addressing in external Joopback is operational only when
OTCR in the mode register is set to 1.

19

TLEN
0
1

FilTER

2

4

3

8

4
5
6

32
64

7

128

12:08

RES

07:00

TDRA

15:03
AFOO2510

02:00

Figure 7. Logical Address Filter Operation

:M 23

21

) 2 0

II
L···,--,J

L- Ms

RDRA (23:03)

' - - - - - RLEN

AFOOO490

Bit

Name

o..crtptton

15:13

RLEN

RECEIVE RING LENGTH is the
number of entries in the receive
ring expressed as a power of two.
Number
of Entries

RLEN

12:08

RES

0700
1503

RDRA

0

1

1

2

2
3
4
5
6
7

4
8

TRANSMIT DESCRIPTOR Rlt~G
ADDRESS IS the base address
(lowest address) of the Transmit
03scripto; Ring.

BUFFER MANAGEMENT
Buffer Management is accomplished through message descriptors organized in ring structures m memory Each message descriptor en~ is four words long. There are two rings
allocated for the device: a Receive ring and a Transmit ring.
The device is capable Of polling each ring for buffers to either
empty or fill With packets to or from the channel. The device is
also capable of entering status information In the descriptor
entry. Chip polling is limited to looking one ahead of the
descriptor entry the chip is currently working with

The Chip communicates with a HOST deVICe (probably a
mircoprocessor) through the ring structures in memory. Each
entry in the ring is either "owned" by the chip or the HOST
There is an ownership bit (OWN) In the message deSCriptor
entry. Mutual exclusion is accomplished by a protocol which
states that each device can only relinqUIsh ownershIp 01 the
descriptor entry to the other device; It can never take
ownership, and no device can change the state of any field In
any entry after It has rellflqUlsheO ownershIp

64
128

RESERVED
RECEIVE DESCRIPTOR RING
ADDRESS is the base address
(lowest address) of the Receive
Descriptor Ring

DESCRIPTOR RINGS
Each descriptor In a ring in memory IS a 4·word entry. The
following is the format of the receive and the transmIt
descriptors.

Receive Message Descriptor Entry

3:r 0

L- AES

RESERVED

16

32

Transmit Descriptor Ring Pointer

L..-_ _ _ Tl£N

16

The location of the descriptor rings and thetr length are found
in the initialization block, accessed during the initialization
procedure by the chip. Writing a "ONE" mto the STRT btt of
CSRo will cause the chip to start accessmg the descriptor
rings and enable it to send and receive packets.

MUST BE ZEROES. These bits
are RDRA (02:00) and must be
zeroes because the Receive
Rings are aligned on quadword
boundanes

0200

2

MUST. BE ZEROES. These bits
are TORA (02:00) and must be
zeroes because the Transmit
Rings are aligned on quadwofd
boundaries.

Receive Descriptor Ring Pointer
~

1

lOGICAL ADOIU;SS

"Match· '. the packet IS accepted.
Malch . 0 me packel IS ,elected

31

Number of Entries

II
Lv"",---J

Receive Message Descriptor 0 (RMDO)
15

TOAA(23:03)

AF000940

AF000480

Bit

Name

Description

1513

TLEN

TRANSMIT RING LENGTH IS the
number of entnes In the Transmit
Ring expressed as a power 01
two.

20

Bit

Name

Description

15:00

LAOR

The LOW ORDER 16 address
bits of the buffer poInted to by
thIS descriptor. LADR is written by
the host and unchanged by the
Chip.

ReceIve IIeauge DescrIptor 1 (RMDd
11

•

l 11 I I I I I I

l

Name

DncrIption

OWN

This bit indicates that the
descriptor entry is owned by the
host (OWN - 0) or by the chip
(OWN'" 1). The chip clears the
OWN bit after filling the buffer
pointed to by the descriptor entry.
The tlost sets the OWN bit after
emptymg the buffer. Once the
chip or host has relinquished
ownership of a buffer. It must not
change any field in the four words
that comprise the descriptor
entry.

14

ERR

ERROR summary IS the'· OR" of
FRAM. OFLO. CRC or BUFF
ERR IS set by the chip and
cleared by the host

13

FRAM

FRAMMING ERROR Indicates
that the mcommg packet
contained a noninteger multiple
of eight bits and there was a CRC
error. If there was not a CRC
error on the Incoming packet.
then FRAM will not be set even If
there was a nonlnteger muillple
of eight bits In the packet. FRAM
IS not valid In Internal loopback
mode FRAM IS set by the crap
and cleared by the host.

11

CRC

BUFF

BUFFER ERROR is set any time
the chip does not own the next
buffer while data chaining a
received packet. This can occur
in either of two ways: 1) the OWN
bit of the next buffer is zero. or 2)
silo overflow occurred before the
chip received the next STATUS.
BUFF is set by the chip and
cleared by the host.

I

15

OHO

10

J

BIt

12

BIt

•

7

If a Buffer Error occurs, an
Overflow Error may also occur
internally in the SILO. but will not
be reported in the descriptor
status entry unless both BUFF
and OFLO errors occur at the

same time.
09

STP

START OF PACKET indicates
that this is the first buffer used by
the chip for this packet It is used
for data chaining buffers. STP is
set by the chip and cleared by the
host.

08

ENP

END OF PACKET indicates that
this is the last buffer used by the
chip for this packet. II IS used for
data chaining buffers. If both STP
and ENP are st3l. the packet fits
into one buffer and there IS no
data chaining. ENP is set by the
chip and cleared by the host

HADR

The HIGH ORDER 8 address bits
of the buffer pointed to by this
deSCriptor. This field is written by
the host and unchanged by the
chip

07:00

Receive Message Descriptor 2 (RMD2)
'5

12

11

'---------8CJfT

'-----------------1IUST1lE0NES

OVERFLOW error Indicates that
the receiver has lost ail or part of
the Incoming packet due to an
inability to store the packet in a
memory buffer before the internal
srlo overllowed. OFLO IS set by
the chip and cleared by the host.

AF000930

Bit

Name

11:00

CRC indicates that the receiver
has detected a CRC error on the
Incoming packet. CRC is set by
the chip and cleared by the host.

21

Description
MUST BE ONES. ThIS fiela IS
written by the host and
unchanged by the chIp.

15:12

BCNT

BUFFER BYTE COUNT is the
length of the buffer pointed to by
this descriptor, expressed as a
two's complement number. ThiS
field is written by the host and
unchanged by the chip. Minimum
buffer size is 64 bytes for the first
buffer of packet

Receive Message Descriptor 3 (RMD3)
12

11

0

BIt

Name

I

13

RES

RESERVED bit. The chip will
write this bit with a "0."

12

MORE

MORE indicates that more than
one retry was needed to transmit
a packet. MORE is set by the chip
and cleared by the host.

11

ONE

IICNr

IIIU

AFOOO9SO

BIt

De8Criptlon

15:12

RES

RESERVED and read as zeroes.

'1:00

MCNT

MESSAGE BYTE COUNT is the
length in bytes of the received
message. MCNT IS valid only
when ERR is clear and ENP is
set. MCNT is written by the chip
and cleared by the host.

I

packet. ONE is set by the chip
and cleared by the host. One flag
is net valid '#hen LOOL is set

10

DEF

DEFERRED indicates that the
chip had to defer while trying to
transmit a packet. This condition
occurs if the channel is busy
when the chip is ready to
transmit. DEFER is set by the
chip and cleared by the host.

09

STP

START OF PACKET indicates
that this is the first buffer to be
used by the chip for this packet. It
is used for data chaining buffers.
STP is set by the host and
unchanged by the chip. The STP
bit must be set in the first buffer
of the packet. or the LANCE will
skip over this descriptor and poll
the next descriptor(s) until the
OWN and STP bit are set.

0

----'l

_L.ADR
_ _

AF000940

Bit

Name

Dncrtptlon

15:00

LADR

The LOW ORDER 16 address
bits of the buffer pointed to by
this descriptor. LADR is written by
the host and unchanged by the
Chip.

•

ENP

END OF PACKET indicates that
this is the last buffer to be used
by the chip for this packet. It is
used for data chaining buffers. If
both STP and ENP are set. the
packet fits into one buffer and
there is no data chaining. ENP IS
set by the host and unchanged by
the chip.

07:00

HADR

15:12

ONES

The HIGH ORDER 8 address bits
of the buffer pointed to by thiS
deSCriptor. ThiS held is written by
the host and unChanged by the
Chip.
Must be ones. ThiS held IS set by
the host and unchanged by the
chip.

08

Transmit Message Descriptor 1 (TMD 1)
11

7

l 1JIll 1 I I
l

I

- - ,- -

HADA

" ' - - - - - - - - - - - - EfIIP

~------------------s~
~---------------------DU

~-------------------------ONE
~--------------------------~
~-----------------------MS
~------------------------ERA

~-----------------------------------OWN
AFOOO880

Bit

Name

Description

15

OWN

This bit indicates that the
descriptor entry IS owned by the
host (OWN = 0) or by the chip
(OWN'" 1). The host sets the
OWN bit after filling the buffer
pointed to by this descriptor The
chip clears the OWN btt after
transmitting the contents of the
buffer. Both the host and the chip
must not alter a descriptor entry
after it has relinquished
ownership.

14

ERR

ONE indicates that exactly one

retry was needed to transmit a

Transmit Message Descriptor Entry
T[ansm't M....ge Descriptor 0 (TUDO)

Dacrlptlon

Transmit Message Descriptor 2 (TMD2)
tS

12

I

0

"

I
I

I
I

BeNT

ONES

AFOOO980

ERROR summary IS the "OR" of
LeOL. LCAR. UFlO or RTRY
ERR is set by the chip and
cleared by the host

22

I

BIt

BIt

Name

11:00

13

RES

BCNT

BUFFER BYTE COUNT ~ ~
usable length in bytes of the
buffer pointed to by this
descriptor expressed as a two's
complement number. This ~ the
number of bytes from this buffer
that will be transmitted by the
chip. This field is written by the
host and unchanged by the chip.
The first buffer of a packet has to
be at least 100 bytes minimum
when data chaining and 64 bytes
(DTCA - 1) or 60 bytes
(OCTR - 0) when not data
chaining.

12

LCOl

LATE COLLISION indicates that
a collision has occurred after the
slot time of the channel has
elapsed. The chip does not retry
on late collisions. LCOL is set by
~ chip and cleared by the host

11

LCAR

LOSS OF CARRIER is set when
the carrier input (RENA) to the
chip goes false during a chipinitiated transmission. The chip
does not retry upon loss of

carrier. It will continue to transmit
the whole packet until done.
LCAR is no1 valid in INTERNAL
LOOPBACK MODE. LCAR is set
by the chip and cleared by the

Transmit Menage DescrIptor 3 (TUD3)

,..

11

If

IIIIII

I

host.
10

fL-_______________________
~I--------- ~
L-__________________________
L-____________________________
L-______________________________

RTRY

RETRY ERROR indicates that
the transmitter has failed in 16
attempts to successfully transmit
a message due to repeated
collisions on the medium. If
DRTY - 1 in the MODE register.
RTRY will set after 1 failed
transmission attempt. RTRY is
set by the chip and cleared by the
host.

TOR

TIME DOMAIN
REFLECTOMETRY reflects the
state of an internal chip counter
that counts from the start of a
transmission to the occurrence of
a collision. This value IS useful in
determining the approximate
distance to a cable fault. The
TOR value is written by the chip
and is valid only if RTRY is set.

~

L~

~

N5

L----------------------------------~o

L -___________________________________

~

AFOOO890

BIt

Name

15

BUFF

09:00
BUFFER ERROR is set by the
chip during transmiSSK>n when
the chip does not find the ENP
flag in the current buffer and does
not own the next buffer. This can
occur in either of two ways: either
the OWN bit of the next buffer is
zero, or SILO L.:nderflow occurred
before the chip received the next
STATUS signal. BUFF is set by
the chip and cleared by the host
BUFF error will turn off the
transmitter CCSRo. TXON - 0)

DETAILED DESCRIPTION
RING ACCESS MECHANISM IN THE
LANCE

If a Buffer Error occurs. an
Underflow Error will also occur
internally in the SILO. An
Underflow Error will not be
reported in the descriptor status
entry unless both BUFF and
UFLO errors occur at the same
time.

14

UFLO

RESERVED bit. The chip will

write this bit with a "0."

Once the LANCE is initialized through the initialization block
and started, the CPU and the LANCE communicate via
transmit and receive rings. for packet transmission and
reception.
There are 2 sets of RAM locations (four 16-bit register per set.
corresponding to the 4 entries in each descriptor) in the
LANCE. The first set points to the current buffer, and they are
the working registers which are used for transferring the data
for the packet. The second set contains the pointers to the.
next buffer in the nng which the LANCE obtained from the
lookahead operation.

UNDERFLOW ERROR indicates
. that the transmitter has truncated
a message due to data late from
memory. UFLO indicates that the
SILO has emptied before the end
of the packet was reached.

There are three types of ring access in the LANCE. The first
type is when the LANCE polls the rings to own a buffer. The
second type is when the buffers are data chained. The LANCE
does a Iookahead operation· between the time that it is
transferrrng data to/from the SILO; thiS lookahead is done
only once. The third type is when the LANCE tries to own the
next deSCriptor in the ring when It clears the OWN bit for the
current buffer.

Upon UFLO error, transmitter is
turned off (CSRo. TXON ~ 0).
UFLO is set by the chip and
cleared by the host.

23

Transmit Ring Buffer Management

Receive Ring Buffer Management
Recerve Ring access is similar to the transmrt flng access.
Once receiver is enabled, the LANCE will always try to have a
receIVe buffer available, should there be a packel addressed
to this node for reception. Therefore, when a packet has not
arrived. the LANCE will poll the receive ring entry, once every
1.6ms, until it owns the current receive OTE. Once the LANCE
owns the buffer, it will read RMDo and RMD2 to get the rest of
buffer address and buffer byte count. When the packet arrives
from the cable, the LANCE will first check to see if it owns a
buffer. If not. it will poll the receive ring once for a buffer. I! it
does not own the buffer, it will set the MISS error in CSRo and
will not poll the receive ring until the packet ends.

When there is no Ethernet activity, the LANCE will automatically poll the transmit ring in the memory once it has started
(CSAo, STAT = 1). This polling occurs every 1.6ms, (CSRo
TOMO bit - 0) and consists of reading the status word of the
transmit Ring, TM01, until the LANCE owns the descriptor.
The LANCE will read TMDo and TM02 to get the rest of the
buffer address and the buffer byte count when It owns the
descriptor. Each of these memory reads IS done separately
with a new arbitration cycle for each transfer

It the transmit buffers are data chained (current buffer
ENP '" 0), the LANCE will Iookahead the next descriptor in the
ring while transferring the current buffer Into the SILO (see
Figure 8a). The LANCE does this lookahead only once It it
does not own the next transmit DeSCriptor Table Entry COTE)
(2nd TX ring for this packet) it will transmit the current buffer
and updates the status of current Aing WIth the BUFF and
UFlO error bits set. If the LANCE owns the 2nd DTE, it will
also read the buffer address and the buffer byte count of this
entry. Once the LANCE has finished emptyIng the current
buffer, it clears the OWN bit for this buffer, and immediately
starts loading the SilO from the next (2nd) buffer. Between
OMA bursts, starting from the 2nd buffer, the LANCE does a
lookahead again to check if it owns the next (3rd) buffer. This
activity goes on until the last transmIt DTE indicates the end of
the packet (TMD" ENP ., .1). Once the last part of the packet
has been transmitted out from the SILO to the cab/e, the
LANCE will update the status in TMD" TMD3 (TMD3 is
updated only w~n there is an error) and relinquishes the last
buffer to the CPU. The LANCE tries to own the next buffer
(first buffer of the next packet), Immediately after it relinquishes troe last buffer of the current packet. This guarantees
the back-ta-back transmission of the packets. If the LANCE
does not own the next buffer, it then polls the T x ring every
1.6ms.

Assuming the LANCE owns a receive buffer when the packet
arrives, it will perform a Iookahead operattOn on the next OTE
between periods when it is dumping the received data from
the SILO to the first receive buffer in case the current buffer
requrres data chaining. When the LANCE owns the buffer, the
look ahead operation consists of 3 separate single word DMA
reads: RMD" RMOo, and RMD2. When the LANCE does not
own the nelCt buffer, the Iookahead operation conSIsts of only
one SIngle DMA read, RMD1. Either lookahead operation is
done only once. Following the Iookahead operation. whether
LANCE owns the next buffer or not, the LANCE will transfer
the data from SilO to the first receive buffer for this packet In
burst mode (8 word transfer per 01'18 DMA cycle arbitration).

If the packet being received requires data chaining. and the
LANCE does not own the 2nd DTE. the LANCE will update the
current buffer status. RMD1. with the BUFF and/or O"Fl error
bits set. If the LANCE does own the next buffer (2nd DTE)
from previous lookahead, the LANCE will relinquish the
current buffer and start filling up the 2nd buffer for this packet.
Between the time that the LANCE is transferring data from the
SILO to 2nd buffer, it does a Iookahead operation again to see
if it owns the next (3rd) buffer. If the LANCE does own the third
OTE. it wiN also read RMOc, and RM02 to get the rest of buffer
pointer address and buffer byte count.

When an error occurs before all of the buffers get transmitted,
the status. TMDJ, is updated in thl'! current OTE. own bit IS
cleared in TMD1, and TINT bit is set In CSRO which causes an
interrupt if INEA - 1. The LANCE will then skIp over the rest of
the descriptors for this packet (clears the OWN bIt and sets
the TINT bit In CSRO) untIl It finds a buffer With both the STP
and OWN bit betng set (it indicates the first buffer for the next
pa.::ket).

This activity continues on until the LANCE recognIzes the end
of the packet (cable is idle); it then updates the current buHer
status with the end of packet bit (ENP) set. The LANCE will
also update the message byte count (RMD3) with the total
number of bytes received for this packet In the current buHer
(the last buffer for this packet).

When the transmit butters are not data chained (current
descnptor's ENP = 1), the LANCE Will not perform any lookahead operatIOn. It WIll transmit the current buffer. update the
TM 0 3 if any error, and then update the status and clear the
OWN bit tn TMO,. The LANCE Will then Immediately check the
next deSCriptor in the flng to see If It owns It. If It does .. the
LANCE will also read the rest of the entries from the descnptor
lable. If the LANCE does not own it. it will poll the ring once
every 1.6ms until it owns It. User may set the TOMO bit In
CSRo when it has relinquIshed a buffer to the LANCE ThIS Will
force the LANCE to check the OWN bIt at thIS buffer without
waitIng for the polling tIme to elapse

'77

Oll'PUT~.

P"C"fl~

DFOO1850

Figure Sa. Data Chaining (Transmit)

24

Receive
Data is loaded into the SilO from the serial input shift register
during reception. Data leaves the SilO under microprogram
control. The LANCE microcode wit wait until there are at !Iul
~ of data in the SilO before initiating a OMA burst
transfer. Preambte (including the synch) is not loaded into the
SilO.
Note: SilO is used as an alternative name for FIFO.

SILO - Memory Byte AlIgnment

0F001860

Memory buffers may begin and end on arbitrary byte b0undaries. Parallel data is byte aligned between the SilO and DAl
lines (DALo-DAl1 s). Byte alignment can be reversed by
setting the Byte Swap (BSWP) bit in CSR3.

figure ab. Buffer Management Descriptor
Rings

x.

Notes: ,. W.
Y. Z are the packets
queued for transmission.
2. A, B. C. 0 are the packets received by the lANCE.

TRANSMISSION ADDRESS
BSWP - 0: SilO
SilO
BSWP - 1: SilO
SilO

LANCE DMA TRANSFER (BUS MASTER
MODE)

WORD READ FROM EVEN MEMORY
BYTE
BYTE
BYTE
BYTE

n
n+1
n
n+1

gets
gets
gets
gets

DAl
DAl
DAl
DAl

<07:00>
<15:08>
< 15:08>
<07:00>

TRANSMISSION - BYTE READ FROM EVEN MEMORY
ADDRESS
gets DAL <07:00>
BSWP - 0: SILO BYTE n
BSWP - 1: SILO BYTE n
gets DAL <15:08>

There are two types of DMA Transfers with the lANCE:
- Burst mode DMA

TRANSMISSION - BYTE READ FROM 000 MEMORY
ADDRESS
gets DAl <15:08>
BSWP - 0: SilO BYTE n
BSWP "" 1: SILO BYTE n
gets DAl <07:00>

- Single word OMA

Burat Mode DMA

RECEPTION - WORD WRITE TO EVEN MEMORY ADDRESS
BSWP ., 0: DAl <07:00> gets SILO BYTE n
BSWP - ,: DAl < 15:08> gets SilO BYTE n + 1

Burst DMA is used for Transmission or Reception of the
Packets. (Read/Write from/to Memory).
The Burst T ransters are 8 consecutive word reads (transmit)
or writes (receive) that are done on a single bus arbitration
cycle. in other words. once the LANCE receives the bus
acknowledge. (HlDA - low). it will do 8 word transfers (8
OMA cycle. min. at 600ns per cycle) without releasing the bus
request signal (FK5CI5 - low). If there are more than 16 bytes
empty in the SilO. in transmit mode, or at least '6 bytes of
data. in the SilO in receive mode. when the LANCE releases
the bus (Hrn:D deasserted). the LANCE will request the bus
again within 700ns. (FKXD dwell time). Burst DMAs are always
8 cycle transfers unless there are less than 8 words left to be
transferred in to/from the SILO.

RECEPTION - BYTE WRITE TO EVEN MEMORY ADDRESS
BSWP - 0: DAL <07:00> gets SILO BYTE n
DAL < 15:08> - don't care
BSWP ., 1: DAL <1 5:08> gtes SILO BYTE n
DAL <07:00> - don't care
RECEPTION - BYTE WRITE TO 000 MEMORY AD·
DRESS
BSWP - 0: DAL <07:00> - don't care
DAL < 15:08> gets SilO BYTE n
BSWP = 1: DAL <15:08> - don't care
DAL <07:00> gets SILO BYTE n

Single Word DMA Transfer
The LANCE initiates SIngle word DMA transfers to access the
transmit. receive rings or initialization block. The LANCE will
not initiate any burst DMA transfer between the time that it
gets to own the descriptor. and accessing the descriptor
entries in the ring (an average of 3 - 4 separate OMA cycles
for a multibuffer packet) or reading the initialization block.

THE LANCE RECOVERY AND
REINITIALIZATION
The transmitter and receiver section of the LANCE are turned
on via the initialization block (MODE REG: ORX. DTX bits).
The state of the transmitter and the receiver are monitored
through the CSRo register (RXON, TXON bits). The lANCE
must be reinitialized If the transmitter and/or the receiver has
not been turned on during the original initialization. and later it
is desired to have them tumed on. Another reason why it may
be d8Slrabie to reinitialize the LANCE. to tum the transmitter
and/ or receiver back on again, is when either section shuts off
because of an error (MERR. UFlO. TX BUFF error). Care
must be taken when the lANCE is reinitiahzed. The user
should rearrange the descriptors in the transmit or receive ring
prior to reinitialization. This is necessary since the transmit and
receive descriptor pointers are reset to the beginning of the
ring upon initialization.

SILO OPERATION
The SilO provides temporary buffer storage for data being
transferred between the parallel bus I/O pins and serial bus 1/
pins. The capacity of the SilO is 48 bytes.

o

Transmit
Data is loaded into the SilO under internal microprogram
control. SilO has to be more than 16 bytes empty before the
LANCE requests the bus (HOlD is asserted). The LANCE will
start sending the preamble (if the line is idle) as soon as the
fIrSt byte is loaded to the SILO from memory. Should transmitter be required to back off. there could be up to 32 bytes of
data in the SilO ready for transmission. Reception has priority
over transmission during the time that the transmitter is
backing off.

Another way of starting the LANCE, once it has stopped
(STOP - 0 in CSRO). is by setting the STRT bit in CSRo. The
STRT puts the LANCE in operation in accordance with the

25

parameters set up in the mode register. If OTX and/or DAX
are set to 0 In the mode register, the transmitter and I or
receiver will be turned on again when STRT bit is set.

-!t th6
BITS

•
BITS

~

______

6
BYTES

~

,
BYTES

__

~

2
BYTES

RECEIVE BASED COLLISION

I(A

___ J

-'-I!>OO
BYTES

If CLSN becomes asserted during the reception of a packet.
this reception IS Immediately terminated. Depending on the
timIng of COLLISION OETECTION, the following will occur. A
collision that occurs within 6 byte limes (4.8ms) will result in
the packet belOg rejected because of an address mIsmatch
WIth the SILO wrtte pointer being reset. A collision that occurs
wlthtn 64 byte times (51 .2ms) will result in the packet being
rejected SInce it is a runt packet. A collision that occurs after
64 byte times (late colilSlOf'I) will result in a truncated packet
being written to the memory buffer with the CRC error bit most
Itkely being set in the Status Word of the Receive Ring. Late
collision error is not recognized in receive mode.

FCS

•
BYTES

DFOO1880

Figure 9b_ IEEE 802.3 MAC Frame Format

FRAMING ERROR (DRIBBLING BITS)
The LANCE can handle up to 7 dribbling bits when a received
packet terminates; the input to the LANCE, RCLK, stops,
following the deassertion of RENA. During the reception, the
CRC is generated on every serial bit (including the dribbling
bits) coming from the cable, and it gets stored internally on
byte boundary. The framing error is reported to the user as
tollows:

TRANSMIT BASED COLLISION
When a transmission attempt has been terminated due to the
assertion of CLSN, (a collision that occurs within 64 byte
times). the LANCE will attempt to retrieve it 15 more times.
The LANCE does not try to reread the descriptor entries from
the T X rinQ upon each Collision. The descriptor entries for the
current buffer are internally saved. The scheduling of the

-If the number of the dribbling bits are 1 to 7 bits and there is
no CRC error, then there is no Framing error (FRAM - 0).

26

value to the outgoing bit stream as in Transmission but does
not perform the CRC check of the incoming bit stream.

retransmissions is determined by a controlled randomized
process called "truncated binary exponential backoff." Upon
the negation of the COUISION JAM interval, the LANCE
calculates a delay before retransmitting. The delay is an
integral multiple of the SLOT TIME. The SLOT TIME is 512 bit
times. The number of SLOT TIMES to delay before the nth
retransmission is chosen as a uniformly distributed random
integer in the range: 0 ~ r ~ 2k where k - min (n. 10).

4. LQOPBACK - MODE <02> LOOP - 1 MODE <03>
DTRC - 1. LANCE performs the CRC check on the incoming bit stream as in Reception, but does not generate or
append the CRC value to the outgoing bit stream during
transmission.

LOOP BACK

If all 16 attempts fail, the LANCE sets the RTRY bit in the
current Transmit Message Descriptor 3, TMD3. in memory.
gives up ownership (sets the own bit to zero) for this packet.
and processes the next packet in transmit ring for transmission. If there is a late collision (collision occurring after 64 byte
times), the LANCE will not transmit again; it will terminate the
transmission, note the LCOL error in TMD3, and transmit the
next packet in the ring.

The normal operation of the LANCE is as a half-duplex device.
However, to provide an on-line operational test of the LANCE,
a pseudo-full duplex mode is provided. In this mode simuttaneous transmission and reception of a Ioopback packet are
enabled with the following constraints:
1. The packet length must be no longer than 32 bytes, and
less than eight bytes, exclusive of the CRe.

COLLISION - MICROCODE INTERACTION

2. Serial transmission does not begin until the SILO contains
the entire output packet.

The microprogram uses the time provided by COLLISION
JAM, INTER PACKET DELAY. and the beckoff interval to
restore the address and byte counts internally and starts
loading the SILO in anticipation of retransmission. It is
important that LANCE be ready to transmit when the backoff
interval elapses to utilize the channel properly.

3. Moving the input packet from the SILO to the memory does
not begin until the serial Input bit stream terminates.
4. CRC may be generated and appended to the output serial
bit stream or may be checked on the input senal bit stream.
but not both in the same transaction.

TIME DOMAIN REFLECTOMETRY

5. In internal loopback, the packets should be addressed to
the node itself.

The LANCE contains a time domain reflectometry counter.
The TOR counter is ten bits wide. It counts at a 10MHz rate. It
is cleared by the microprogram and counts upon the assertion
of RENA during transmission. Counting ceases if CLSN
becomes true. or RENA goes inactive. The counter does not
wrap around; once all ONEs are reached in the counter, that
value is held until cleared. The value in the TOR is written into
memory following the transmission of the packet. TDR is used
to determine the location of suspected cable faults.

6. In externalloopback, multicast addressing can be used only
when DTCR'"' 1 IS in the mod'!! regtster. In this case, the
user needs to append the bytes CRC.
loopback is controlled by bits <06, 03. 02> INTL, OTCR, and
lOOP of the MODE register.

SERIAL TRANSMISSION
Senal transmiSSion conSists of sending an unbroken bit stream
from the T X 1/0 ptn consisting of:

HEARTBEAT
During the INTERPACKET DELAY follOwing the negation of
TENA. the CLSN input is asserted by some transceivers as a
self-test. If the CLSN input is not asserted within 21JS following
the completion of transmission (after TENA goes low), then
the LANCE will set the CERR bit in GSRo. CERR error will not
cause an interrupt to occur (INTR - 0).

1. Preamble/Start bit· 62 alternating ONES and ZEROES
terminating with the synch in two ONEs. The last ONE is the
Start bit.
2. Data: The senalized byte stream from the SilO Shifted out
WIth LSB first.
3. CRG- The inver1ed 32 bit polynomial calculated from the
Data, address. and type field CRC is not transmitted if:

CYCLIC REDUNDANCY CHECK (CRC)
The LANCE utilizes the 32 bit CRC functIOn used in the
Autodin-II network. Refer to the Ethernet specification (section
6.2.4 Frame Check Sequence Field and Appendix C; CRC
Implementation) for more detail. The LANCE requirements for
the CRC logic are the following:

i. Transmission of the Data field is truncated for any reason.
II.

CLSN becomes asserted any time during transmission.

iii. MODE <03> DTCR = 1 In a normal or loopback transmission mode.

1. TRANSMISSION - MODE <02> LOOP - 0, MODE <03>
OTCR - O. The LANCE calculates the CRC from the first bit
following the Start bit to the last bit of the data field. The
CRC value inverted is appended onto the transmission in
one unbroken bit stream.

The Transmission is indicated at the 110 pin by the assertion
of TENA with the first bit of the preamble and the negation of
TENA after the last transmItted bit.
The LANCE starts transmitting the preamble when the follow:
ing are satisfied:

2. RECEPTION - MODE <02> LOOP'"' O. The LANCE performs a check on the input bit stream from the first bit
following the Start bit to the last bit in the frame. The LANCE
continually samples the state of the CRC check on framed
byte boundaries, and, when the incoming bit stream stops,
the last sample determines the state of the CRC error.
Framing error (FRAM) IS not reported if there is no CRC
error.

1. There is at least one byte of data to be transmitted in the
SILO.
2. The interpacket delay has elapsed.
3. The backoff interval has elapsed, if a retransmission.

SERIAL RECEPTION

3. LooPBACK - MODE <02> LOOP - 1, MODE <03>
DTRC - O. The LANCE generates and appends the CRC

Serial reception consists of receiving an unbroken bit stream
on the Rx 110 pin consisting of:

27

1. Preamble/Start bit: Two ONES occurring a minimum of 8 bit
times after the assertion of RENA. The last ONE is the Start
bit.

When the microprogram returns from the transmit poHing
routine, the microprogram enters a timing loop, and repeats
the routine upon timeout. The timer is set around 1.6ms. The
timing loop can be overridden by setting the TOMO bit in
CSRo· This will force the microprogram to fall ttvough the wait
loop The TDMO bit is cleared immediately after leaving the
wa.t loop. Therefore, to be effectiye, TOMO should be set after
a buffer has been inserted on the transmi1 ring (own bit has
been sel).

2. Destination Address: The 48 bits (6 bytes) following the
Start bit.
3. Data: The serialized byte stream following the Destination
Address. The last 4 complete bytes of data are the CRC.
The Destination Address and the Data are framed into bytes
and enter the SILO. Source Address and Type fiefd are part
of the data which are transparent to the LANCE.

During this' routine, should the receiver become active, the
microprogram traps to the receive routine.

Reception is indicated at the I/O pin by the assertion of RENA
and the presence of clock on RCLK while TENA is mctive.
The LANCE does not not sample the received data until about
800ns after RENA goes high.

Receive Polling Routine
The Receive Polling Routine is called by the main polling
routine to check to see if th.e chip ~s the ~ bL.offer :!
the current pojnter address. The microprogram first reads the
status word from the current receive ring descriptor. If the chip
does not own the buffer, the microprogram reuns to the
polling routine. If the chip does own the buffer. the microprogram reads in the rest of the descriptor entry, namely the rest
of the buffer address and the buffer byte count The chip only
reads in 3 of the 4 words in the descriptor entry. The message
byte count is not read because it is not used by the chip. The
message byte count is written by the chip during the status
update at the end of a reception. This routine will then return
to the polling routine.

MICROPROGRAM OVERVIEW
The Ethernet protocol chip is controlled by a set of semiindependent hardware functions and a microprogram. The
following are some of the routines asSOCiated with the
operation of the LANCE.

Switch Routine
Upon power-up. the microprogram finds itself in a routine to
evaluat6 the INIT. STRT, and STOP bits of CSRo. INIT and
STRT are cleared and STOP is set by the hardware by Bus
~. Setting either INIT or STAT thrOugh an I/O transfer to
CSRo will clear STOP. Setting STOP through an 110 transfer
will clear INIT and STRT. After seeing STOP cleared, the
microprogram tests the state of INIT. If set, it branches to the
initialization routine, returns. and tests the state of STAT. If
INIT is clear and the STAT is set, the mOopIogram will go on
to the Polling routine without going to the Initialization routine.
If, while the STOP bit is set, an 110 transfer to CSA" CSR2, or
CSR3 occurs, the microprogram traps to the CSR service
routine.

Receive Routine
The Receive Routine is entered when the receiver is en.bIecI
and the address of the incoming j)tICket has passed address
recognition. Once the ReceNe Routine is entered, the micr0program checks to see if the chip owns the cunent receive
buffer. If it does not own the buffer. the microprogram wiI
check the ownership bit in memOry once for a buffer. If it does
not own the buffer, the microprogIam wiI set the miss error in
CSRo and clear the SILO. The microprogram wiI thM reun to
the polling routine once the current packet ends.

:nltlallzatlon Routine

If the chip acquired bufter ownership while the receiver was
still active, the microprogram will acquire the rest of the

This routine is entered only from the switch routine upon the
setting of the INIT bit. Its function is to load the Chip with the
data from the initialization block in memory. The routine
accesses the initialization block through the address loaded
Into the LANCE by a trap to CSR, and CSR2 that should have
occurred prior to the INIT bit being set This routine simply
sequentially reads the initialization block, in separate single
word OMA cycles. and stores the information away in the
appropriate elements of the Chip.

descriptor, namety the bun. address and buffer length. The
microprogram will then back up the buffer Midress and byI8
count In case the packet is a runt. This is where the
microprogram would have come if it had owned • receive
buffer when it originally entered the receive routine.

Receive Buffer Lookllhead
ReceIVe lookahead .s always done during the reception since
the LANCE will not know the length of the receive p8cket. The
Iookahead is done during the time that SILO is being filled with
data from the cable. The microprogram checks to see if there
was onty one receive buffer. If there is more than one receive
buffer, the microprogram checks the ownership of the next
buffer. If the chip owns the buffer. it reads the rest of the
DeSCrtptor into the internal RAM. If it does not own the buffer.
it will continue with the receive routine. trapping to the RX
OMA routine whenever there are 16 or more bytes available in
the SILO. Lookahead is only done once whenever there is a
trap to the rece.ve routine.

When done, the microcode returns to the switch routine

Polling Routine
This routine is entered from:
1 The switch routine upon the setting of the STRT btt.

2. The receive routine after a packet has been received.
3. The transmit routine after a packet has been transmitted.
4. The transmit routine if a TX Abort occurs.

5. The Memory Error Trap routine (MERR error) after the trap
is ·serviced.

When the LANCE does not own the next buffer and receive is
still active after the current buffer is filted. the LANCE will
update the status with BUFF error being set. OFLO (overflow)
error may also get set if SILO overflows.

The routine begins by testing to see if the receiver is disabled,
and, if not, tests the current receiver buffer ownership bit to
see If it owns a buffer. If the Chip had not acquired a buffer
previously. the microprogram goes to the receive polling
routine to acquire one. Then the microprogram returns from
the receive polling routine, or if the Chip had acquired a buffer
previously, .t tests to see if the transmitter is disabled. and if
not, goes to the transmit polling routine to test .f there is a
buffer to be transmitted,

Receive Done
When recetVer goes inactive (Done), the last byte of data has
been read out of the SILO. The I1lICroprogram will check to
see if the packet was a runt. If it is a runt. the receive butter
address pointer and byte count parameters are restored from

28

the previously loaded backup locations in the internal RAM.
The microprogram then reb.l"ns to the Polling routine. If the
pecket is not a runt, the receive status is updated in the ring
descriptor.

any bad transmit buffers on the ring, until it finds a buffer
with both the OWN and STP bit being set.

0V8f

If STP - 1, the microprogram performs memory transactions

to acquire and store the address and byte count of the buffer

Data Chain

in the Internal RAM. It then goes to the transmit routine to
allow the transmission of the buffer.

If Byte Count of Current Buffer Equal 0 becomes true, it
indicates that the receive buffer is full and the packet is not yet
finished, which is the data chain case. The microprogram will
update the receive status in the descriptor ring. and relinqUish
the buffer to the CPU. It witt then check the next own bit If the
next own is false, which would be the case if there was only
one buffer or if there was more than one buffer but the chip did
not own the next one, the microprogram will wait for the
receiver to go inactive. This indicates that no more data is
arriving from the Ethernet. When the receiver goes inactive.
the current RX status is updated, and the own bit is cleared.

The receive active trap is enabled during this routine to allow
for processing of an incoming packet and termination of the
transmit process.

Transmit Routine
The transmit routine is entered from the transmit polling
routine wben the microcode finds a buffer that it owns,
indicating a message is scheduled to be transmitted. The
routine is divided into three sections of microprogram, an
initialization section, a buffer Iookahead section, and a descriptor update section.

If the chip owned the next buffer, the current receive buffer
parameters in the internal RAM are updated from the next
receive buffer parameters that had previously been loaded
into the internal RAM. The microprogram will then check for
end of the ring and update the address pointers accordingly.
The microprogram will then go through the receive buffer
look ahead section once, to try to acquire another receive
buffer if one is available The microprogram will finally get back
to the wait loop until either receiver goes inactive, SILO
overflOW, or receive buffer overt low becomes true. There are
two flags provided in the descriptor, STP (Start of Packet), and
ENP (End of Packet), which allow the chip to mark the first and
last buffers filled by the message. RMD3 is not updated if its
buffer IS not the last buffer in the chain.

Upon entering the initialization section, the first thing the
microprogram does is back up the buffer address and byte
count in the event of a retry. It then enables the DMA engine
to start filling the SILO and send the pr&aIllbIe. It then enters a
wait loop until the transmitter is actually sending the bit
stream. It then proceeds to the Iookahead section. If the
receiver became active while the microprogram was waiting
for the transmitter to start, the transmission attempt is stopped
and the microprogram goes to the receive routine via a TRAP.

Transmit Buffer Lookahead
Transmit look ahead occurs only when data Chaining, and is
.done while the message is being transmitted from the SILO. In
the lookahead section, the microprogram tests to determine if
the current buffer it is transmitting has been marked with the
end of the packet flag (ENP)_ If so, data chaining is not
required. The microprogram enters a wait loop until either TX
ERROR or TX DONE occurs. When DONE or ERROR or both
finally set. the microprogram will report the error, if necessary,
and then update the status word, update the nng address
pointer and set the TINT bit in CSRQ. It will then return to the
polling routine.

Receive DMA Routine
The Receive DMA routine is entered whenever there are 16 or
more bytes of data in the SIl.O for transfer to memory during
the reception. The routine is also entered when there are less
than 16 bytes In the SILO and the receiver has gone inactive.
ThiS IS to allow the SILO to empty at the end of the reception.
Once entered, the Receive DMA routine will transfer 16 bytes
of data to memory by doing 8 word transfers. These transfers
are done on a single memory bus acquisition. This means that
the chip will arbitrate through the HOLD-HLDA sequence and
then keep HOLD asserted for the duration of 8 transfers. The
READY Signal from the bus slave device is used to control the
IndiVidual word transfers_

Transmit Data Chaining
There are two flags provided in transmit message descriptor 1
(TMD1), STP (Start of Packet) and ENP (End of Packet) which
mark the first and last buffers in the chain. The LANCE will,
under rrncroprogram control, continue to chain buffers pointed
to by the sequential descriptors In the ring until the ENP flag is
encountered. If the end of packet flag (ENP) IS not set. data
chaining is indicated. The microprogram first checks to see if it
owns the next buffer. If not, the rrucroprogram enters the
descriptor update section and walts for TX DONE or TX
ERROR. Eventually, an undertlow error will occur because
byte count overt low will occur without DONE having been set.
Since there is no more data being written into the SILO and
the transmitter is continuously reading data out of the SILO.
the SILO will become empty and undertlow Will be set. This will
cause the microprogram to branch out of the wait loop and
update the descriptor with both BUFF and OVFL betng set.
When an undertlow error occurs, the transmitter IS disabled.

If the memory buffer starts on an odd address boundary, the
first transfer will be 1 byte rather than 1 word (2 bytes). This
rOutine IS also used to transfer less than 16 bytes at the end of
a reception depending upon the packet Size, buffer addresses
and data chaining

Transmit POlling Routine
The tran~mit polling routine is entered from the polling routine
to determine If a message has been scheduled on the transmit
descriptor flng.
The routine begins by waiting for the TX Abort condition to
finish if a TX Abort had occurred earlier. It then tests the status
word of the flng deSCriptor entry. The routine tests the
ownership of the ring buffer by reading the status word in the
flng descriptor. If the Chip does not own the buffer, the
mIcroprogram returns to the polling routine. If it does own the
buffer. thiS Indicates a message is to be transmitted. The
microprogram then tests the STP flag_ If STP = 0, thiS buffer
could be a fragment of a data chained packet that got an error
In a previous buffer. The chip Will release the buffer to the host
by cleanng the OWN bit It will then update the ring address
pointer and return to polling. In this manner, the chip skipS

The LANCE owns the next buffer; the microprogram attempts
to obtain the next buffer descriptor status. address. and byte
count before entering a wait loop that looks for byte count
overtlow or TX ERROR. When byte count overflow does
occur, the microprogram updates the descriptor and updates
the internal current transmit buffer parameters The rrucroprogram will then return to the microcode that checks for the end
of packet flag to sequence through the rest of the buffers in
the data chain. If an error had occurred, the mICroprogram
would report the error before updating the status word

29

to n,s:ore the read and write pointers. If there is a TX error. it
indicates that 15 retransmissions have occwred (16 total
attempts) or that the Disable Retry bit (DATY) is set in the
mode register. The microprogram then writes the status into
the transmit descriptor ring. and returns to the polling routine
to transmit the next packet. If there is no TX Error. the byte
count is restored and the microprogram retuns to the start of
the transmit routine to attempt another transmission.

If an error ne&ds to be reported, an error status word is written
into the ring descriptor prioI' to writing the status word
containing the "OWN" bit which releases the buffer. It no error
is to be reported, the single word containing the "OWN" bit is
written. The microprogram returns to the polling routine if the
"ENP" flag is found or an error was reported. Otherwise, the
microprogram returns to the Iookahead sections.

Transmit DMA Routine
ThiS routine is entered ttvough a mlCrotrap in the Iookahead
section of the transmit routine. The function of the routine is to
move data out of local memory into the SILO. The trap IS
active when there are more than 16 free locations in the SILO
and SilO underflow has not occun-ed.

CSA Trap Routine
The CSR trap routine is entered onty during the switch routine
when the STOP bit of the CSRo is set. The function of the
routine is to allow the access of CSR, and CSR2 through an 1/
transaction. The routine determines which CSR is being
accessed, read or write, moves the data between the MDA
and COP RAM. and generates a Bus R'EAt5Y signal.

o

Once entered, the transmit DMA routine will transfer 16 bytes
oj data from memory to the SilO by doing 8 word transfers.
These transfers are done on a single memory bus acquisition.
If the memory buffer starts on an odd addressing boundary,
the first transfer will be 1 byte rather than 1 word (2 bytes).
This routine is also used to transfer less than 16 bytes at the
end of transmission depending upon the packet size. buffer
addresses, and data chaining.

Memory TImeout Trap Routine
This trap is invoked whenever a memory transfer times out.
That is, it does not receive ~ within 25.S"sec after the
assertion of the address on the bus.

Retry Trap Routine
This routine is entered when a collision has been detected.
The buffer address pointer is restored and the SILO is cleared

The routine disables the receiver and transmitter by clearing
the RXON and TXON bits in CSRo·

30

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

Storage Temperature ......................... -65°C to + 150°C
Ambient Temperature with
Power Applied ............................... -25°C to + 125°C
Supply Voltage to Ground Potential
Continuous ........................................ -O.3V to + 7V
Power Dissipation .............................................. 2.0W

Commercial (C) Devices
Temperature ..................................... O°C to + 70°C
Supply Voltage ............................ + 4.75V to + 5.25V

Vss ............................................................ oV
Operating ranges define those limits over which the function·
ality of the device is guarant88d.

Strf1SS6S above those listed under ABSOLUTE MAXIMUM
RA rINGS may cause petmlJnent device fal1ure. Functionality
at or above these limits is not implied. Exposure to absolute
maximum ratings for extended periods may affect cI8vice
teliBbility.

DC CHARACTERISTICS TA - 0 to + 70 o e, Vee - + 5V ±5% unless otherwise
PM1tmeter.

TntCondttlona

o..crtptlon

spedfied

Typ

Min

Max

Untt.

VIL

Input LOW Voltage

-05

0.8

VIH

Input HIGH Voltage

2

Vex; + O.SV

Volts
Vo!ts
Volts
Volts

VOl

Output LOW Vottage

VOH

Output HIGH Voltage

IlL

Input LUkage

CtN

Input Capacitance

CooT

Clutput Capacitance

Cto

Capacitance

Iol- 3.2mA
IoH - -O.•mA
VIN - o.•v to Vee

0.5

2.•
!10

F -1MHz

pF

10

pf

20

pf

TEST LOAD DIAGRAMS FOR FUNCTIONAL AND
AC TESTING

2.IN
-~

~-o----4

~o-----.

TCOO1660

TCOO1670

Test Load for All the Outputs
and 1/0 Pins Except Pins 11, 17, 22

Test Load for Open Drain Outputs
and Pins 11, 17,22

Cl - l00pF for all pins except pins 26, 29.
~ - 50pF

for pins 26, 29.

31

",.A

10

'~-".'.".~

3

TA '"' 0 to 70°C, Vee - + 5V ±5% unless otherwise specified

BUS MASTER AND BUS SLAVE TIMING PARAMETERS
Number

Parameters

Test

Description

.....

Typ

Max

Unit.

99

tOl

45

55

TCLK HIGH Tme

45

55

ns
ns
ns

Rise Time of TClK

0

8

ns

0

8

ns
ns

Condition.

t

ITCT

TCLK Period

2

ITCl

TCLK LOW Tme

3

ITCH

4

tTCA

5

ITCF

Fall Time of TCLK

6

tTEP

TENA Propagation Delay After the Rising Edge of TClK

Ct. Ct. Ct. Ct. -

95

50pF

7

tTEH

TENA Hold Time After the Rising Edge of TClK

8

tTOP

TX Data Propagation Delay After the Rising Edge of TCLK

9

'TDH

TX

10

tACT

RCLK Period

11

IRCH

RCLK HIGH Time

12

tACL

RClK LOW Time

13

IRCA

Rise Time of RlCK

14

IReF

Fell Time of RCLK

15

IROR

RX Data Rise Tme

16

IROF

RX Data Fall Time

17

'IRDH

RX Data Hold Tme (RCLK to RX Data Change)

18

tAOS

RX Data Setup Tme (RX Data Slable to the Rising Edge of
RClK)

60

ns

19

I tOPl

RENA lOW Tme

120

ns

20

!cPH

CLSN HIGH Time

80

21

tOOFF

Bus Master Driver Disable After Riling Edge of

22

Data Hold Tme After the Rising Edge of TCLK

50pF

50pF

85
38
38
0
0
0
0
5

0

lOON

Bus Master Driver Enable After Falling Edge of ~

0

23

tHHA

Delay to Falling Edge of
(Bus Master)

24

tAW

from Falling Edge of

HOrn

R$

95

ns
ns

118

ns

5

FK::X:D

HIl5A

I

5

50pF

ns
ns
8

ns

8

ns

8

ns

8

ns
ns

50
250

ns
ns
ns

0

ns

~ Pulse Width LOW

200

600
35

ns
ns
ns
ns
ns

25

!cYCLE

Read/Write. Address/Data Cycle Tme

26

IXA5

AddreSs Setup Tme to the Falling Edge of ALE

27

IXAH

Address Hold Time After the Rising Edge of

75

DAS

28

lAS

Address Setup Time to the Falling Edge of ALE

75

29

IAH

Address Hold Ttme After the Falling Edge 01 ALE

35

ns

IAOAS

Data Setup Time to the Rilling Edge of
Read)

50

ns

0

ns

0

ns

200

ns

35

ns

30

j

I

~

I'RDA"

32

1'00A5

~----+
33

twos

34

IWOH

35

i 15001

m

Data Hold Ttme Atter the RISing Edge 01
Read)

(Bus Master

'OAS

(Bus Master

Data Setup Time 10 the faIling Edge Of ~ (Bus Master
I Write)

m (Bus Masler
Data Hold Time After the RISIng Edge of m (Bus Master
Wntel
Dala Dover Delay After the Failing Edge of m (Bus Slave
, Read)
Data Selup TIme 10 the RIsing Edge of
Wnte)

tSOO2

Dala Dover Delay Afte the Failing Edge of ~ (Bus Slave
Read)

ISAoH

Data Hold Time After the Rising Edge Of ~ (Bus Slave
Read)

38

tSWoH

Data Hold TIme After the RISing Edge of
Wnte)

39

tswOS

Wnte)

36
37

m (Bus Slave
Data Setup Tune 10 the Failing Edge of m (Bus Slave

!
32

fCRS 0, 3. RAP)

400

ns

(CSR 1.2)

1200

ns

0

35

ns

0

ns

0

ns

3 (Cont.) T A = 0 to 70°C, Vee'" + 5V ±5% unless otherwise specified
BUS MASTER AND BUS SLAVE TIMING PARAMETERS
Number

Parameters

40

tALEW

ALE Width HIGH

4'
42

toALE

Delay from Rising Edge of

43

IADAS

44

!RIOF

45

tROVS

46

tosw

!ROlF

47

IRIS

48

tRIH

49
50

tRIOF

tos

51

tROH

52

tWOSI

53

teSH

54

tess

55

tSAH

56

I$AS

57

; IARYD

58
59

m

8lr

ConcIttIona

to the Rising Edge of ALE

from the Falling Edge of ALE to the Felling Edge of

~ from the Rising Edge of

OAlO to the F8IIing Edge 01

~ from the Rising Edge of

0Arn

m (Bus Master Read)
Delay from the Falling Edge of ~ to the Rising Edge 01
m
All (Bus Master Read)

m (Bus Master
Read)
l5AiJ Hold Time After the Rising Edge of m (Bus Master

Read)
l

'C5Arn

mJ

to the Falling Edge of

Setup Time to the Falling Edge of AlE (Bus Master

Read)

'C5Arn

Hold Time After the Falling Edge of ALE (Bus Master

Read)

grab
l

from the Rising Edge 01
(Bus Master Write)

m

to the Rising Edge of

m (Bus Slave)
~ Setup Time to the Falling Edge of m (Bus Slave)
ADR Hold Time After the Rising Edge 01 m ~Bus Slave)
ADR Setup Time to the FaIIlfl9 Edge of m (Bus Slave)
~ Hold TIIM After the Rising Edge of

IRDYH

ISR02
ISRYH

m

ns

80

ns

15

ns

75

250

m (Bus
~ Onver Turn On After the Falling Edge of m (Bus
Slave Read)
~ Hold Time After the Rising Edge of m (Bus Slave)
READ Hold Time After the Rising Edge of m (Bus Slave)
READ Setup Time to the Falling Edge of m (Bus Slave)

~ Onver Turn On After the Falling Edge of
Slave Read)

ns

15

ns

135

ns

0

ns

55

ns

110

ns

35

ns

35

ns

0

ns

0

ns

0

ns

0

ns

80

(Bus

Unlta

200

A Y to Insure a MirllfTlUm Bus Cycle Tme (SOOns)

~ Hold Time After the Rising Edge of
Master)

6'

lIa.

ns
ns

~a~ from the Falling Edge of ALE to the Falling Edge of

ISROS

! ISRO'

tARYO - 300ns

to the Falling Edge 01

l5A[j Selup Time to the Rising Edge of

from the Rising Edge of
(Bus Master Read)

Typ

70

Width lOW

grab

lIin
120

m

Data Setup Time to the Falling Edge of Ready (Bus Slave
Read)

60

62

Tnt

DncrIption

ns

75

ns

0

ns

(CSR 0, 3, RAP)

ns

600

(CSR 1,2)

ns

1400
0

35

ns

TCLK Rising Edge to Control Signals AcliYe

165

ns
ns
ns
ns
ns

TCLK Falling Edge to ALE lOW

150

ns

teOl

TCLK Falling Edge to DAS Falling Edge

150

tRCS

Ready Setup Time to TClK

63

tSRH

64

,ISRS

65

teHl

66

teAIi

67

teeA

68

' teALE

69

70

0
0

200
150

TClK Rising Edge to Hold lOW or HIGH Delay
; TCLK to Address Valid

71

teCH

TClK Rising Edge to DAS HIGH

72

IHcs

HlDA Setup to TClK

50

ns
ns
ns
ns

73

tRENH

RENA Hold Time After the RIsing Edge of RClK

''0

ns

50
150

Notes 1 Parameter # 25 IS not shown in the timing diagrams_ h specifies the ITIininun bus cycle for a single OMA transfer
1$ a function of the synchronization lime of ~. The synchronizatIOn must occur
2 The A!Al5Y setup tIme before negation of
WIthin lOOns Therefore. the setup time is lOOns plus any accumulated propagation deIIIys_ Ready slips occur on lOOns Increments

m

I

33

SERIAL LINK TIMING

MIlA

---J

iiiiT

___ r~------------~'------------~i .
'i~_ _ _ _ _y

WFOO1S31

Timing measurements are made at the following voltages, unless otherwise specified

Output
Input
Float

High

Low

2.0V
2.0V
V

O.8V
O.8V
O.SV

34

APPENDIX A
8086 computer program example to generate the hash filter, for multicast addressing in the LANCE.

6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

34
35
36
37

38
39
40
41
42
43
44
45
46
47
48
49
50
51

52
53
54
55

SUBROUTINE TO SET A BIT IN THE HASH FilTER FROM A
GIVEN ETHERNET lOGICAL ADDRESS
ON ENTRY SI POINTS TO THE lOGICAL ADDRESS WITH lSB FIRST
01 POINTS TO THE HASH FilTER WITH LSB ARST
ON RETURN SI POINTS TO THE BYTE AFTER THE lOGICAL ADDRESS
ALL OTHER REGISTERS ARE UNMODIFIED
PUBLIC SETHASH
ASSUME CS:CSE61
;
POlYL
POLYH.

-1086
-04Cl

CSE61
;
SETHASH

0000

Eau
Eau

lOB6H
04C1H

;CRC POL YNOMINAL TERMS

SEGMENT PUBLIC 'CODE'

50
53
51
52
55

PROC
PUSH
PUSH
PUSH
PUSH
PUSH

NEAR
AX
BX
CX
OX
BP

0005 B8 FFFF
0008 BA FFFF
OOOB B5 03

MOV
MOV
MOV

AX.OFFFFH
DX,OFFFFH
CH.3

;AX,DX - CRC ACCUMULATOR
;PRESET CRC ACCUMULATOR TO ALL 1'S
;CH - WORD COUNTER

MOV
ADD
MOV

8P;[S1]
SI,2
CL.16

;GET A WORD OF ADDRESS
;POINT TO NEXT ADDRESS
;Cl - BIT COUNTER

MOV
ROl
XOR
SAL
RCL
AND
JZ

BX,DX
BX.l
BX.BP
AX,l
DX,l
BX,0001H
SETH30

;GET HIGH WORD OF CRC
;PUT CRC31 TO LSB
;COMBINE CRC31 WITH INCOMING BIT
;LEFT SHIFT CRC ACCUMULATOR

0000
0000
0001
0002
0003
0004

0000 8B 2C
OOOF 83 C602
0012 Bl 10
0014
0016
001e
oolA
00lC
oolE
0022

8B
01
33
01
01
81
74

OA
C3
DO
EO
02
E3 0001
07

;
SETH10:

SETH2O:

;SAVE ALL REGISTERS

;BX - CONTROl BIT

;00 NOT XOR IF CONTROL BIT - 0

PERFORM XOR OPERATION WHEN CONTROL BIT - 1
0024 35 1086
0027 81 F2 04Cl
002B
0020
002F
0031
0033
0035

OB C3
01 CD
FE C9
75 E1
FE CD
75 D6

SETH30:

XOR
XOR

AX,POlYl
DX,POLYH

OR
ROR
DEC
JNZ
DEC
JNZ

AX,BX
BP.1
CL
SETH20
CH
SETH 10

;PUT CONTROL BIT IN CRGO
;ROTATE ADDRESS WORD
;DECREMENT BIT COUNTER
;DECREMENT WORD COUNTER

FORMATION OF CRC COMPLETE. AL CONTAINS THE REVERSED HASH
CODE

56
57

58
49
60
61
62

0037
003A
003C
003E

89000A
DO EO
DO DC
E2 FA

63
64
65

66
67

68

SETH40:

MeV
SAL
RCR
LOOP

CX.10
AL.l
AH,1
SETH40

;REVERSE THE ORDER OF BITS IN AL
;AND PUT IT IN AH

AH NOW CONTAINS THE HASH CODE
00408A
0042 Bl
0044 02
0046 eo

DC
03
EB
01

MeV
MOV
SHR
MeV

BL,AH
Cl,3
Bl.Cl
AL.01H

35

;Bl - HASH CODE, ·BH IS ALREADY ZERO
;OIVIDE HASH CODE BY 8
;TO GET TO THE CORRECT BYTE
;PRESET FILTER BIT

69
70
71
72
13
74
75

76
77
78
19
80
81
82
83
84

0048 80 E4S 07
004B 8A CC
0040 02 EO
004F 08 01
0051 50
0052 SA
0053 59
0054 58
005558

0056 C3
0057

AND

MOV
SHL

OR
POP
POP
POP
POP
POP

.

AH,7H

. Cl.AH

Al,CL
[01 + BXJ,AL
BP
OX
CX
BX

;EXTRACT BIT

COUNT

;SHIFT BIT TO CORRECT POSITION

;SET IN HASH FILTER

AX

RET

SETHASH ENOP

:
0057

CSEG1

ENOS

END

Basic computer program example to generate the hash fitter. for multicast addressing. in the LANCE.

100
110
120
130
140
150

160
170
180
190
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
360
370
380
390
400
410
420
430
440
450
460
470
480
490
500
510
520
530
540
550
560

REM
REM
PROGRAM TO GENERATE A HASH NUMBER GIVEN AN ETHERNET ADDRESS
REM
OEFINT A-Z
DIM A(47) : REM ETHERNET ADDRESS - 48 BITS
DIM C(32) : REM CAC REGISTER - 32 BITS
PRINT "ENTER STARTING ADDRESS'; : INPUT AS
IF LEN (AS) < > 12 THEN 160 : REM THE INPUT ADDRESS STARTING MUST BE 12
REM
REM
UNPACK STARTING ADDRESS INTO ADDRESS ARRAY
REM
M- 0
FOR I - 0 TO 47 : All) - 0 : NEXT I
FOR N - 12 TO 1 STEP -1
Y$ - MID$ (AS.N.1)
IF Y$ - "0" THEN 420
:F Y$ - "1" THEN A(M) - 1 : GOTO 420
IF Y$" "2" THEN A(M + 1) - 1 : GOTO 420
IF Y$ '" "3" THEN A(M + 1) -1 : A(M) - 1 : GOTO 420
IF Y$" "4" THEN A(M + 2) -1 : GOTO 420
IF YS" "5" THEN A(M + 2) - 1 : A(M) - 1 : GOTO 420
IF Y$" "6" THEN A(M + 2) - 1 : A(M + 1) - 1 : GOTO 420
IF Y$ - "7" THEN A(M + 2) - 1 : A(M + 1) - 1 : A(M) - 1 : GOTO 420
A(M + 3) "" 1
IF Y$ = "8" THEN 420
IF Y$" "9" THEN A(M) - 1 : GOTO 420
IF Y$" "A" THEN A(M + 1) - 1 ; GOTO 420
IF Y$ = "B" THEN A(M + 1) - 1 : A(M) - 1 : GOTO 420
IF Y$" "C" THEN A(M + 2) - 1 : GOTO 420
IF Y$" "0" THEN A(M + 2) - 1 : A(M) - 1 : GOTO 420
IF YS .. "E" THEN A(M + 2) - 1 : A(M + 1) - 1 : GOTO 420
IF Y$z"F" THEN A(M+2)-1 : A(M+l)-l : A(M)-1
M .. M + 4
NEXT N
REM
REM
PERFORM CRC ALGORITHM ON ARRAY A(0-47)
REM
FOR 1- 0 TO 31 : C(I) - 1 : NEXT I
FOR N - 0 TO 41
REM LEFT CRC REGISTER BY 1
FOR I - 32 TO 1 STEP - 1 : C(') - C(I - 1) : NEXT I
C(O)" 0
T - C(32) XOR A(N) : REM T - CONTROL BIT
IF T < > THEN 600 : REM JUMP IF CONTROL BIT - 0
C(l)" C(1) XOR 1 : C(2) - C(2) XOR 1 : C(4) - C(4) XOR 1
C(5) - C(5) XOR 1 : C(7) - C(7) XOR 1 : C(8) - C(e) XOR 1
C(10)-C(10) XOR 1: C(11)-C(11) XOR 1: C(12)-C(12) XOR 1

36

CHARS

570
580
590

600
610
620

630
640
650
660

C(16) - C(16)
C(26) - C(26)
C(O) - 1
NEXT N
REM
REM
CRC
REM
HH - 32-C(0)
PRINT "THE
GOTO 160

XOR 1 : C(22) - C(22) XOR 1 : C(23) - C(23) XOR 1
XOR 1

COMPUTATION COMPLETE. EXTRACT HASH NUMBER FROM C(O) TO C(5)

+ 16-C(1) + 8-C(2) + 4·C(3) + 2·C(4) + C(5)
HASH NUMBER FOR ";A$;" IS ";HH

MAPPING OF LOGICAL ADDRESS TO FILTEA MASK
LAF

LAF

DHtInetIon

Reg
BIts

Loe

Addreu Accepted

LAF
Reg

LAF
Loc

Set

Dec

(Hex)

BIt.
Set

Dec

0
L
A
F
0

0
1
2
3
4
5
6
7
8
9
10
11
12

13
15

0

L

A
F
1

14
15
16
17
18
19
20
21
22
23
24
25

26

15

27
28
29
30
31

0000
0000
0000
0000
0000
0000
0000

0000
0000
0000
0000
0000
0000
0000

0000
0000
0000
0000
0000
0000
0000

0000
0000
0000
0000
0000
0000
0000

0085
OOA5
00E5
OOC5
0045
0065
0025
0005
002B
OOOB
004B
006B
OOES
OOCB
008B
OOBS

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

0000
0000
0000
0000
0000
0000
0000
0000

OOC7
00E7
OOA7
0087
0007
0027
0087
0047

0000 0000
0000 0000

0
L
A
F

0000
0000
0000
0000
0000
0000
0000

36

15

37
38
39
40
41
42
43
44
45
46
47

0

48

2

49
50
51
52

l
A

53
54

F

0000 0069

32
33
34
35

55
56
57
58

3

0049
0009

59

0029
OOA9
0089

00C9
15

OOE9

37

60
61
62
63

DfttInation
AddreM Accepted
(Hex)

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

0021
0001
0041
0071
OOE 1
OOC1
0081
OOA 1
OO8F
OOBF
OOEF
OOCF
004F
OO6F
002F

OOOF
0063
0043
0003
0023
OOA3
0083

00C3
OOE3

OOCO
OOEO
OOAO
0080
0000
0020

0060
0040

The International Standartl of
Quality guarantees a OOOOk AQL on all
electrical parameters, AC and DC
over the entire _...,~. .

38

Am7992B
Serial Interface Adapter (SIA)

DISTINCTIVE CHARACTERISTICS
•

• Input signal conditioning ~ transient noise
- Transients < 10 ns for coI~ detector inputs
- TransientS < 20 ns tor carrier detector inputs
• ReceiYer decodes Manchester data with worst case
±19 ns of clock jitter (at 10 MHz)
• TTL compatible host interface

Compatible with EthernetlCheapernetIlEEE-802.3

specifications
•
•

•

Crystal controlled Manc:hesta' Encoder
Manchester Decoder acquires clock and data within fOU'
bit times with an acancy of i3 ns
Guaranteed carrier and c:oIision detection squek:h
threshold limits
- Carrier/collision detected for inputs. greater than
-275 mV
- No carrier/collision for inputs less than -175 mV

•

Transmit accuracy ±O.01 % (without adjustments)

GENERAL DESCRIPTION
The Am7992B Serial Interface Adapter (SIA) is a Manchester Encoder/Decoder compatible with IEEE~2.3, Cheapemet and Ethernet specifications. In an IEEE-802.3/Ethernet application, the Am7992B interfaces the Am7990 Local
Area Network Controller for Ethernet (LANCE) to the
Ethernet transceiver cable, acquires clock and data within

four bit times. and decodes Manchester data with worst
case ±19 ns phase jitter at 10 MHz. SIA provides both
guaranteed signal threshold limits and transient noise
suppression circuitry in both data and collision paths to
minimize false start conditions.

II

I

BLOCK DIAGRAM
__.... De.. IU)
__ eive CIocIl (KLIl)

c.rier ~t

•
u
•
•!

1""'1

't

~ICUII)

;

!
i

U

r __....IM I
I

hcMM

T~

I ....
1'-

a.ject

.....

I=- I
I

Inu,

I ,-

...t - t

XTAL t

..L.

L

I

_ _....IM

EftCMM

J

CIecfI (TCUU

8l-=-

1

".c.iv.

+

1"-"-

f
Ie..- I
I Detect I

Tr........ De.. 'TX'
Tr.-Nt E..-..

1-

I

I

Itec..... -

Collisioft •
CoIIiIlioft -

Tr-...it

+

Tr......t -

1

....

~

• .... CJ
--r

OK
XTAL2

80002071

RELATED PRODUCTS
IWt No.

De8Cllption

Am7990

Local Area Network Controller for Ethernet (LANCE)

Am7996

IEEE-802.3/EthemetlCheapemetlTransceiver

o
(')

o
cr
~

Order # 03378E

CON.NECTION DIAGRAM
Top VIew

DIP

CL.SN

CoIIieion+

AX

~

RENA

Receive+

RCU<

~

TSEL

Tiii

GNO.

Vc:c:.

GNO,

Vea

X,

PF

XI

RF

TX

GND,

TCLK

TrMMIit+

TENA

T..........
(X)001521

Note: Pin 1 .. martted for O......D'

ORDERING INFORMATION
dO STANDARD PRODUCTS
AMO products are available in several packages and operating ranges. The order number (Valid CombiIIdon) ..
formed by a combination of: A. DevIce Number
8. Speed OptIon (If applicable)
C. PIIckage Type

D.T...................
E. OptIonal PrOCllling

L-.____________

~~~~

c-~ (010

L - . - - - - - - - - - - c . PACKAGE

+7o-c)

TYPE

p - 2<4-Pin (Slim) PIMtic: 0fP (P030241
(Slim) Cerwnic DIP (a)3024)

o - 28-Pin

'---------------•. SP£ED OPTION
Not Applicable

A. DEVICE NUMBER/DESCRIPTION
Am79928

Serial Interlace Adapter

VIdId CornbInetIoI_
Am79928

Consutt the local AMO sales office to confirm 8VIIiIabiIity of
specific valid combinations, to check on newty reIeued
valid combinations, and to obtain additional data on AMO's
standard military grade products.

pc, PCB
DC, DC8

2

PIN DESCRIPTION

......,...

CLSN CoIIeIon (Output, TTL ActIve HIGH)
Signals at the Collision ±terminals meeting ttveshold and
pulse width requirements wiD produce a logic HIGH at
CLSN output When no signal is present at Collision!,
CLSN output will be LON.

RIC I"""

ReceIver (Inputs)

A differential input A pair of internally biased line receivers
consisting of a carrier detect receiYer with offset threshoki
and noise filtering to detect the tine activity, and a data
recovery receiver with no offset for Manchester data
decoding.

RX ReceIve o.ta (Output)
A MOSITIl output. recovered data. When there is no
signal at Receive± and TEST is HIGH, RX is HIGH. RX is
actuated with RCLK and remains active lM'1tiI RENA is deasserted at the end of message. During reception, RX is

CoIIeIon+

CoIII8ton (Inputa)

~

A differential input. An internally biased line receiver input
with offset threshold and noise filtering. Signals at
Collision! have no effect on data-path functions.

synchronous with RCLK and changes after the rising edge
of RCLK. When ~ is LOW. RX is enabled.

RENA
AeceIYe Enable (Output. TTL ActIve HIGH)
When there is no signal at Receive! RENA is LOW.
Signals meeting threshold and pulse width "on"
requirements will produce a logic HIGH at RENA. When
RENA is HIGH, Receive± signals meeting ttveshold and
pulse width "off' requirements will produce a LOW at
RENA.

TSEL

ACLK
ReceIYe Clock (Output)
A MOS/TTL output. recovered clock. When there is no
signal at Receive! and mT is HIGH, RClK is LOW.
RCLK is activated 1/4 bit time after the second negative
Manchester preamble clock transition at Receive±, and
rema;ns active until end of message. When test is LOW,
RCLK is enabled and meets minimum pulse width
specifications.

When connected with an RC network. TSEL is held LOW
during transmission. At the end of transmission the open
collector output is disabled, allowing TSEL to rise and
provide a smooth transmission from logic: HIGH to "zero"
differential idle. Delay and output return to zero .-e
externally controlled by the RC network at TSEL and
Transmit± lOad inductance.

T....,.,.,n Mode Select (Output. Open
Collector, Input, SenM AmplIfIer)
TSEL LOW: Idle transmit state Transmit+ is positive
with respect to Transmit-.
TSEL HIGH: Idle transmit state Transmit+ and Transmitare equal. providing "zero" differential to
operate transformer coupled loads.

Xl. X2 BlaNd CryWd OscIII8tor (Input)
Xl is the input and X2 is the bypass port. When connected
for crystal operation, the system clock which appears at
TClK is half the frequency of the crystal oscillator. Xl may
be driven from an external source of two times the data
rate.
RF
Frequency Setting YoItIIge Controlled
Oactllator (Yeo) Loop filter (Output)
This loop filter output is a reference voltage for the receive
path phase detector. It also is a reference for timing noise
Immunity circuits in the collision and receive enable path.
Nominal reference Yeo gain is 1.25 TCLK frequency
MHzN.

TX

Transmit (Input)
TIL~mpatible input. When TENA is HIGH, signals at TX
meeting setup and hold time to TCLK will be encoded as
normal Manchester at Transmit+ and Transmit-.
TX HIGH: TransmiH is negative with respect to
Transmit- for first half of data bit cell.
TX LOW: Transmit+ is positive with respect to
Transmit- for first half of data bit cell.

TEN" Transmit Enable (Input)
TIL-compatible input. Active HIGH data encoder enable.
Signals meeting setup and hold time to TCLK will allow
encoding of Manchester data from TX to Transmit+ and
Transmit-.

PF Receive Path Yeo Pe...Lock Loop Flter (Input)
This loop filter input is the control for receive path loop
damping. Frequency of the receive Yeo is internally limited
to transmit frequency ± 12%. Nominal receive Yeo gain is
0.25 reference Yeo gain MHzlV.

TCLK
Transmit Clock (OUtput)
MOS/TIL output TCLK provides symmetrical HIGH and
LOW clock signals at data rate for reference timing of data
to be encoded. It also prOYides clock signals for the
controller chip (Am7990 - LANCE) and an internal timing
reference for receive path voltage controlled oscillators.

ftS'f

Test Control (Input)
A static input that is connected to Vee for Am7992B1
Am7990 operation and to Ground for testing of Receive!
path ttveshold and RCLK output high parameters. When
~ is grounded, RX is enabled and RCLK is enabled
except during Clock acquisition when RClK is HIGH.

T,..,.mt+
TrMemIt (Outputa)
TI'M8mItA differential line output. This line pair is intended to
operate into terminated transmission lines. For signals
meeting setup and hold time to TCLK at TENA and TX,
Manchester clock and data are outputted at Transmit+ I
Transmit-. When operating into a 78
terminated
transmission line, signaling meets the required output
levels and skew for both Ethernet and IEEE-802.3 drop
cables.

n

GN01

HIgh CWrent Ground

GN~

logic Ground

GN03

YCCl
YCC2

Yoltllge Controlled OecIIIator Ground
High Current 8nd logic Supply
YoItIIge Controled o.cIIator Supply

path. In addition, the SIA provides the interface between the
TIL logic environment of the Local Area Netwcrt Controller
for Ethernet (LANCE) and the differential signaling environment in the tran'iCeiver cable.

FUNCTIONAL DESCRIPTION
The Am7992B Serial Interlace Adapter (SlA) has ttvee basic
functions. It is a Manchester Encoder lline driver in the
transmit path, a Manchester Decoder with noise filtering and
quick Iock-on characteristics in the receive path. and a signal
detectlconverter (10 MHz differential to TIL) in the collision

3

Transmit Path
The transmit section encodes separate clock and NRZ data
input signals meeting the set-up and hold time to TCLK at
TENA and TX, into a standard Manchester II serial bit stream,
The transmit outputs (Transmit+ /Transmit-) are deIigned to
operate into terminated transmission lines. When operating
into a 78
termlll8ted transmission line, signaJing meets the
required output levels and skew for Cheepemet. Ethernet and
IEEE-802.3.

n

TI

IIAIOCMD'IWJI

,.....

~.

IIICOCI8

1
1 t

".~

~

10-MHz clocks are fed into the Manchester Encoder to
generate the transitions in the encoded data stream, The 10
MHz clock. TCLK. is used by the SIA to inWnIIIIy lYf'Chronize
Transmit (TX) data and Tranamit Enable (TENA), TCU< is also
used as a stable bit rate clock by the receive NCtion of the
SlA and by other devicee in the systa'n (the Am7990 lANCE
uses TCLK to drive its internal state rnec:tn). The oeciIIator
may use an external .005% crystal or an extemaI TTL.feveI
input as a reference. Transmit ac:ancy of .01 % is achieved
(no external act;ustments are required).
Transmission is enatHd when TENA • activated. Aa long as
TENA remains HIGH, IignaIs at TX will be encoded as
Manchea1er and will appear at Tr&nImit+ .net T,..,..
When TENA goes LOW. the dif*8ntiaI DnIrnit 0UIputa go to

one

Ole

AFOO3()oI()

of two idle states:

1. TSEL HIGH: The idle state of T........m:t yields "zero"
differential to operate transfonner-coupled
Ioad8 (Me Figure 2, TranIn'iIt8r TIning - End
of Trantmialion waveform diIIgram and Typical
~ CUrve dIegram).
2. TSEl LOW: In this idle state, Tr&nImit+ is poMive to
Transmit- (Iogicel HIGH) (Me F9H8 and
diagrams as ref_ad above).

FIgu.e 1. Transmit SectIon

T,.....mtter TImIng and Operdon
A 20 MHz fundamental mode crystal oeciIIator prOYides the
basic timing reference in the SlA. It is divided by two to aeate
the Transmit Oock reference (TCLK). Both 2O-MHz and

The End of Tranamission the external RX network

Return to Z.-o • detemal8d by
at TSEL and bV the toed at

Transmiti.

TSELl
PIN 5

c,
R,

510

*

R,

eeo pF
3K

TSEL
PIN 5

TCOOl9«1

8. TSEL HIGH

A.. TSEL LOW

Figure 2. Transmit Mode Select (TSEL) Connection

SptcI!Ication for Exttmll

SIA OecHlator

SptcIftcatJon 'or Extemtl

Cry.ta'

When using a crystal to drive the Am7992B oscillator. the
following crystal specification should be used to ensure a
transmit accuracy of 0.01 %:
UmH

M.tn. ft2m. MIl.

VnIII

+SO

PPM

1. Resonant FreQuency
Error with Cl - 50 pF

-so

2. Change in Resonant Frequency Tempereture with
CL-SOpF

-40

3. Parallel Resonant FreQuency
with CL - SO pF

4. Motional Crystal Capaci·
lance, C,

0

m

LIytI

When driving the oscillator from an external clock source. X2
must be left floating (unconnected). An external clock having
the following characteristics must b8 used to ensure less than
:to.S ns jitter at Transmitt (see the X1 Driven from External
Source waveform diagram):
Clock Frequency: 20 MHz ±0.01%
Rise/Fall Ttme (lA/IF):

<2

os from 0.8 V to 2.0 V

X, HIGH/LOW Time (lffiGH/tLOW):
+40

PPM
X, FaHing Edge to FaJlingEdgeJitter:

> 20 ns
< to.2 ns

at

1.5 V input
MHz

20
0.022

pF

Some crystal manufacturers have generated crystals to this
specification. One such manufacturer is Reeves·Hoffman.
Their ordering part number for this crystal is RH # 04-20423·
312.

Receiver P.th
The principle functions of the Receiver are to signal the
LANCE thet there is information on the receive pair. and
separate the incomtng Manchester-encoded data stream into
clock and NRZ data.
The Receiver section (see FIgUI'8S 3 and 4) consists of two
parallef paths. The receive data path is • zero threshold. wide
bandwidth line receiver. The carrier path is an offset threshold

_ _ _ dMecting line

r~.

Both

receivers share c:otn<

men bia networtcs to allow operation aver an input common
mode , . , . of 0 to 5.5 WIlts.

0F000173

AFOO305O

figure 4. Receiver SectIon Detail

figure 3. Receiver

may remain HIGH or change to lOW IIlate whenever RCLK is
enabled. At 1/4 bit time of clock transition in bit cell 5, RCLK
makes its first external transition. It also strobes the incoming
fifth bit Manchester "1." RX may make a transition after the

Input . . . . CocMltlol*tg
The CMier Receiver detects the presence of an incoming
data peckel by discerning and re;ecting noise from expected
Manchester data. It also controls the stop and start of the
pttue..Iock loop during clock acquisition. In the Am7992B,
clock ICqUiIition requires a valid Manchester bit pattern of
1010 to lock on the incoming message (see Receive Timing - Start of Reception Clock Acquisition waveform diagram).

RCLK rising edge in bit cell 5, but its state is still undefined.
The Manchester' '1 " at bit 5 is ctocked to RX output at 1/4 bit
time in bit cell 6.

PLL TrKklng

Transient noise pulses less than 20 ns wide are rejected by
the Carrier Receiver as noise and DC inputs more positive
than minus 175 mV are also suppressed. Carrier it detected
for input aignal wider than 45 os with ampfitude more negative
than rnnus 275 mV. When input amplitude and pufse width
concItionI . . met at Receive:t. RENA is asserted and a ciock
acquiIition Cycle is initiated.

After clock acquisition. the INTPLLCLK is compared to the
incoming transitions at Bce and the resulting phase error is
applied 10 a correction circuil This circuit ensures that
INTPLLClK remains lOCked on the received signal. Individual
bit cell phase corrections of the Vco are limited to 10% of the
phase difference between
and INTPllCLK. Hence, input
data jitter is reduced in RClK by 10 to 1.

sec

Clock AcquIlltIGn

c.m.r TrxIdng

When there is no actMty at Receive± (receiver is idle), the
receive oscillator is phase locked to TCLK. T~ first negative
clock transition (first valid Manchester "0") after RENA is
asserted interrupts the receive oscillator and presents the
INTRCLK (1IrtemaI clock) to the HIGH state. The oscillator is
then restarted at the second Manchester "0" (bit time 4) and
is phae locked to it. As a reeuIt, the SIA acquns the clock
from the inconing Manchester bit stream in four bit times with
"1010" ~ bit pattern. The 1o-MHz INTRCLK and
INTPLLClK . . derived from the internat OICiIIator which runs
at 4 timet the data rate (40.0 MHz). The three clocks
m.m.IIy are utilized in the following I'n8IWMW:

RENA deasserts (see Receive Tming - End ot Reception
(last Bit - 0) and Receive TIming - End of Reception (Last
Bit - 1) waveform ciagrams) and a RENA hold off timer
inhibits RENA assertion for at least 120 ns.

get_'"

INTRCLK: After clock acquisition. INTRCLK strobes the

om

inc:oc1W1g data at 1/4 bit time. Receive data path sets the
input to the data decode regis1er (Figure 4).

DecodIng

The data receiver is a comparator with clocked output to
minimize noise sensitivity to the Receive:t inputs. Input error
(VIRO) is less than i: 3S mV to minimize sensitMty 10 input rise
and fall time. RCLK strobes the data receiver output at 1/4 bit
time to determine the VIIIue of the M8nchester bit and cIoc:ka
the data out at RX on the following RCLK. The data receiver
also generates the signal used tor phase detector compIIIi8on
to the internal Am7992B Vro

INTPlLCLK: At clock acquisition, INTPLLCLK is phase
Jocked 10 the incoming Manchester clock transition at bit
cell c:em. (BCC). The transition at
is compared to
INTPLLCU< and phase correction it applied to maintain
INTRCLK at 1/4 bit time in the Manchester eel.

ace

INTCARR: From IWt to end of a mesuge, INTCARR is
acti¥e and ..a.bIishes RENA Tum-otf synchiOiIOUlly witt'
RCLK rising q.. Internal carrier goes active when there is
a negative tr8nIition that is more negative than -275 mV
and _ a puI8a width greater or equal 10 45 ns. Intemal
cerrier goes .inactive Within 165 ns of the last positive
~

Met End of .......

The carrier receiver monitors Receive:t input after RENA is
asserted for an end of message. INTCARR deasserts 145 ns
to 165 ns after the incoming message transitions positive. This
initiates the end of reception cycle. INTCARR is strobed at
3/4 bit time by the falling edge of INTRCLK. The time delay
from the last rising edge of the message to INTCARR deassert
allows the last bit to be strobed by RClK and transferred by
the LANCE without an extra bit at the end of message. When

Dtftetentlal I/O Terminatlona
The differential input for the Manchester data (Receivei:) is
externally terminated by two 4O.2-ohm :t 1% resistors and one
optional eommon-mode bypass c:apacitor. The ciffer8ntieI
input impedance, ZIOF. and the common-mode input, ZtcM.
are specified so that the Ethernet specification for cable
termination impedance is met using standard 1 % resistor
terminators. The CoUision:t differential inputs are terminated in
exactly the same way as the receive inputs (see Fagure 5).

at Receive±.

When TBT it str'IIpped HIGH, RCLK and RX are enabled 1/4
bit lime after clock acquisition in bit cell 5. RX is at HIGH state
when the receiver is idle and TEST is I1r8pped HIGH (no
RLCK). RX, however, is WlCIefined when clock is acquirad and

5

AFOOO452
Notes: 1. Cor.nect R,. R2. C" for 0 ~ noI ...... 18tnit.
2. Pin 2V shown for notTNI dNce operation.

Connect to ground for logic

1 ~ noIbllmil

3. The inclusion of C. end Cs ia ~ to r8duce the common-mode IoIIcIng on cert.IIin 1JaI .......
which • ..l dnct caup&ed.

2. Jitter tolerance within a message after the an.Iogue PlL
has reduced clock acquisition error to a rnnmum.

A transceiver detects collisions on the network and generates
a 10-MHz signal at the CoIIsion± inputs. This coIision signal
pessea through an input stage which det8ctl1ignaI _ _ and
pulse duration. When the signal is detec:ted by the Am79928 it
sets the CLSN line HIGH. This condition continues for
approximately 160 ns after the last LOW-to-HIGH IranIition on

The four cases to test are shown the Input Jitter Timing
Waveform diaIJ'am. They are: .
1. BCC

The test IignIJs utiIiad to jitter the input data ... wtific8I in
that they may not be reeIi:zabIe on networks (8ICIIfYIPIes are
cues 2. 3 and 4 at clock acquiIiIion). ~. 8IICh patI8m
relates to setup and hold time meaurements for the datil
decode register (FJgUr8 4). Receive+ and Receive- are driven
with the inputS shown to produce the zero CI'OSIing cIistortion
at the differential inputs tor the applicable test. Cue 4 and 8
require only a single zero to implement when tested at the end

Jitter Tolerance Deftnltlon and Teat
The Receive Timing - Start of Reception Clock Acquisition
waveform diagram shows the internal timing relationships
implemented for decoding Manchester data in the Am7992B.
The Am 7992B utilizes a clock capttn circuit to align its
Internal data strobe with an incoming bit stream. The clock
acquisition circuitry requires four valid bits with the valUes

0' message.

1010. Clock is phase locked to the negative transition at bit

cell center of the second "0" in the pattern.

levels used to test jitter are within the common-mode and
differential-mode range of the receive inputs and also are
available from automatic test equipment. It is assumed that
the incoming message is asynchronous with the local TCLK
frequency for the Am7992B. This ensures that proper clock
acquisition has been established with random phase and
frequency error in incoming message. An additional condition
placed on the jitter tolerance test is thtIt it must meet all test
requirements Within 10 ms after power is applied. This forces
the Am79928 crystal oscillator to start and lock the analogue
PLl to within acceptable limits for recaMnQ from a cold ItIIrt.

Since data is strobed at 1/4 bit time, Manchester transitions
which shift from their nominal plaCement through 1/4 bit time
will result in improperly decoded data. For. both IEEE-802.3
and Ethernet. this results in the loss of a message. With this as
the criteria for an error, a definition of "Jitter Handling" is:
That peak deviation from nominal input transition approaching or crossing 1/4 bit cell position for which the Am 7992B

data.

Four cases of signal are needed to adequately test the ability
of the Am7992B to property decode data from the Manchester
bit stream. For each of the four cases two time points within a
received message ..e tested:
1. Jitter tolerance at clock acquisition. the measure
capture.

I'

01 bit pattern

3. BCB Jtter for ., 11 bit pattern
4. BCB jitter for an XO bit pat1em

CoIIiaion± .

will propetty decode

Jtter for •

2. BCC ;tter for • 10 bit pat1em

Case 1 of the test corresponds to the expected Manchester
data after clock acquisition and average yakJes for clock
leading jitter tolerance are 21.5 ns. For C888I 5 through 8,
awrage values are 24.4 ns. CUes 5 through 8 .... Jttered at
bit times 55 or 56 as applicable. The Am7992B. then, ....
than 0.6 ns static phase error for the noiM-..... case.

of clock

6

APPLICATIONS

"Ul-"TT ACHMENT UNIT INTERFACE
OTE - [)Io.TA TERMINAL EQUIPMENT
MAU - MEOlA AC:a;SS UNIT

OTE

CHEAPERNET

/

,--------------------------,
I

I
I
I
I
I

I

I

LOCAl
CPU

LQC.Al

Am7V80

Am7gg~e

MEMORy

lANCE

SI'"

~~

I
Am7V98
TRANSCEIVER

L_______________ _______
~

Figure 6. Typical Ethernet Node

7

I

I
I
I

~

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES
Commercial (C) 0eYic:es

Storage Temperature ............................ -85 to + 1SO-C
Ambient Ternperatwe with
Power Applied ....................................... 0 to + 70·C
Suppty Voltage Continuous ............................... + 7.0 V
DC Voltage Applied to Outputs .......... -0.5 to + Vee Max.
DC Input Voltage (Logic Inputs) ......................... + 5.5 V
DC Input Voltage (Receive1/Co1Iision1) ....... -6 to + 16 V
Transmitt Output Current ................•.... -so to +25 rnA
DC ~ Current, Into Outputs ....................... 100 rnA
DC Input ewr.nt (Logic Inputs) ........................ 130 rnA
Transmitt Applied Voltage .......................... 0 to + 18 V

stresses

Temperature ........................................ 0 to + 70·C
Suppty Voltage .................................. + 5.0 V 110%
Operating ranges define thosB limits over which the function..
aIIty of the dfMce is (JUIII8tttBed.

aboWI thoN listed under ABSOLUTE MAXIMUM

"..n.

RATINGS may ~ ~f ~
FunctJoneJIty
.t or aboWI theN limits is not implied. Elq:JotILn 10 ~
fnIIXimum nltings kx fIJdeIJCIed periods may .Hect deMice
reIiMJiIity.

DC CHARACTERISTICS aver operating range unless otherwise specified
P8rwnet....

Output HIGH VoII8ge AX. RENA,

VOl

Output LOW VCIbge
RCLK. TSEL. TCLK, RENA,

a.sN.

I Vo
IVO

an.r.- 0uIput VoII8ge

Veo OFF

T,.,.,.. ~ Output Idle VoIIIIge

100 OFF

T,..,.,.. ~ Oueput Idle ewr.nt

V(;MT

TI'III'Iemit 0uIput Comrnon-Mode VoII8ge

(T1'III'Iemit+ ) - (Trw.NI- )

VOOI

~ Output V~ ImbeAence
(TlWI8mitt) IIVOI-IVOI

VIH

If1)UI HIGH VoIIIige TX. lENA

IIH

If1)UI HIGH ~ TX. TENA,

Vll

Input lOW VoIt8ge TX, TENA

III

Input LOW Current TX. TENA,

VIRVO

TCU<. AClK

AX. a.sN

Veo

VIAO

I

Deecllptlon

VOH

T... CondItIone
IoH --1.0 InA
lot. -11 InA
lot. - 1 InA (Hole 1)

2.4

V

0.38

0.25

0.4

550

870

0.5
V

-550

-870

Al-71S 0

(Hole 2)

-20

0.5

20

mV

TSEL- HIGH

(Hole 1)

-0.5

to.1

0.5

rnA

0

2.5

5

Al-78 0

Al-78 0
(NcU 2)

VIOC

mV

V

5

20

2.0

TE!f

Vee - Ma, VIN - 2.7 V

mT

Vee - MD., VIN - 0.4 V

V

+50
-270

-35

0

fAA

0.8

V

-400

fAA

+35

mV

t 1.5

(FleceMtt ICoIIiIiont)

Differential Input Threshold

Untt8

3.4

no
-no

OitterenU/ Input Thre8hokI (Aee Data)
I Differential Mode Input Vobge AwIge
I

Typ.- lID.

MIn.

-175

V

-275 i

-225

mV

Icc

Power ~ Current

VIS

Input Breakdown Voltage

VIC

Input Oamp Voltage

Voop

Undershoot Voltage ., Zero Ditferentilll Point on TI'MImit
Return to Zero (End of .......)

(Note 9)

ISC

Short Circuit Current
RCLK. RX. TCLK. CLSN. RENA

Vee - Max. (Note 6)

RIOF

Differential Input R8SlStance

Vee - 0 to Max. (Note 1)

6

8.4

RICM

Common Mode Input Resistance

Vee - 0 to Max. (Note 1)

1,5

21

VI(;M

A«:eIve and CoIIieion If1)UI Biu Vobge

lIN -0

1.5

IILO

ReceMt and CoIIiIion Input LOW Curren!

VIN --1 V

-1.06

-164

rnA

IIHO

Receive and CoIIiIion Input HIGH Currant

VIN -6 V

+0.6

+ 1.10

rnA

11HZ

Recerve and CoIIiIion Input HIGH Current

Vee - O. VIN - + 6 V

1.28

186

rnA

IIH

Crystal O8ciUalor (X 1) Input HIGH Current

Viti - 3.5 V (Notes 3 & S)

+ 1.2

rnA

IlL

Crystal o.c.tor (X,) Input lOW

Vil - 0 V (Notes 3 & 5)

-1.2

rnA

2.0

V

TENA,

mT)

11-1 rnA

Current

Crystal Oec:iIIator (X,) Input HIGH Vobge

(Notes 3. 4 & 5)

Crystal OeciIIator (X,) Input LOW Volatge

(Notes 3, 4 & S)

table.

-TypicaJ values liS1ed .e for Vee - 5.0 V
TA - + 25-C

8

I
1

-40

0.8

rnA

I
i

VIH

~tic:s

180

5.5

11N--18 rnA

VIL

Notes: See notes fOllOwing Switching

125

lose - 50 ns

CTX,

V

-100

mV

I -80 1-'50
I
'

1

3.5

V

-12

;

j 42

rnA

kn
kn
V

V

SWITCHING CHARACTERISTICS
No.

fNfW

operating range unless otherwise specifiedTeet CoIdIIoI.

DMcrIp1fon

P..........

MIn.

Typ. lID. UnIta

RECEIVER SPECIFICATION
1
2

3

C\'Cfe

RClK

IAcT
tAcH

15

TIrM

(NoeIe 7, • & 8)

RCLK HIGH TIrM

38

RCLK LOW TIrM

4

fAct.
IACR

5

IRcF

RCLK F.. TIrM

1

AX RiM Time

e

IRoA
fAoF
tAcH

AX Hold TIrM (RQ.K f 10 AX et.nge)

(NoIee 2 & 7)

g

fRos

RX Prop 0eI8)' (RCLK : to RX StIIbIe)

(Note 7)

10

toPH

RENA Tum-On
110 RENAH)

o.y

(VIDe Max. on ~

11

toPo

RENA Tum-OrI
to RENAL)

o.y

(VO:: Min. on ~%

12

toPL

RENA LOW TIrM

13

lAPWR

7

ACU< RiM Tme

AX

r-..

50

50

5

120

Receive:! Input PufM WIdIh 10 R.;.ct (Input < VIOC

2.5

2.5

8

14

tRPWO

15

IRLT

Decoder

11

tReOH
lRPWN

RENA Hold TIrM (RClH f to RENAtJ

8

45

~ TIrM

40
(Note 1)

Input PuIM WIdIh to Not Tum-Off INTCARR

nI
nI
nI
nI
nI

8

25

nI

50

eo

nI

265

300

nI

200

34

Min.)

nI

nI

e
e
a

2.5
(Hole 7)

TIrM

Reoeive%

118

38

2.5

Rec:ePte:! Input PuIee WiI:fth to Tum-On (Input> VIOC
M&x.)

11

100

".

20

34

".

nI

3eO

450

".

57

eo

".

155

165

nI

18

10

COLLISION SPECIFICATION
18

~ .npIr.

tcPwR

Pulse Width to RO\8Ct (Input < VIOC Min.)

CoIIiIion Input Pulse Widttl to Tum-On Collision!

19

tcPwo

20

tcPwe

21

tcPwN

Exceeds VIOC Max.)
CoIIi8ion Input 10 Tum-Oft CSl.N (Input < VIOC M&x.)
Collision Input to Noi Tur n.()f1 ClSN (Input> VICC MIn.)

22

tcPH

ClSN Tum-On Delay MOC Un. on Collision!
to ClSNH)

tcPo

ClSN T~
to CLSNLl

23

~

NIKr Min C'I"'

28
~1a8)

eo

I

CoIIision~

I

18

".
".

117

!'IS

117

180

".

33

50

".

133

160

".

TRANSllmER SPECIFICAnON

7); 8M

29

troH.

;X 8M TEN~ I1(JIc1 i .....

30

troce

S1
32

too
troA

33

trOF

Tranll"Wf

34

txrCH

,(,

35

tx"rCl

Al I:)

~

f(.;:

(:Inck A,c~.~ J-r.~

~7

Dr

';I!ter 1 CII8f:t".ce 4,."",

27

I
II

i

I
I

I

I

lOse - SO

28

26

I

TCU< LOW T,me

trCl
trCH
trCR
trCF
tros. ITEs

24
25

TClK Rise TIrM
TCL~

tm;

.Mr.. - 4.5 V. _

ns (Note 2)

TCU< IofIG'" Ti,.,..

-

Fall Ttrne

TEN/>

s.tuD

losc-50

Ierne 10 1 ClI<

110 TCLK

Tr.n!I1T'ot~

.• :».5

NQIas: 1. CooT""" 10

'yo

,1t;\PU' R0!'8 TtmI'
!

Output Fall

~irne

t
.-1_____
i

clt~ce

.~ ~ T

rnor..

!'IS

".

2.5

8

!'IS

2.5

8

!'IS

5

1.1

5

-1.1

49.5

SO

50.5

!'IS

80

100

ns

2

4

".

2

4

!'IS

8.2

18

".

9.6

18

!'IS

20-80'110

I

-4

. . . . ~~!"'r •. ~.:. ! .... ._,)W

-----T

55
55

j

.----.~

~.~~A.!.':'~~~ ~~..!.:!.KiH.
1~ ~

SO
SO

!'IS

(Note 2)

' :renan.t.t ~~(84 ~ .Arrte~~ Edgoil __
TC _>< ~!.GII .•~ "!";ens.l·1~ C'.•~

45
45

!

.

.

IN<)Ies 3 & 5)

L ___.

,

ns
".

16

21.5

!'IS

19

24.4

!'IS

·'l.So..; - :'" r':-

omer

t9:.1foO ~. "'~. . - ,,r:1 l~lWl d'-~.

"'C8S! or 1Ir!1ft. TOItSt aca;r~ not. ~ to allow tcreemng guardDendL
"1 m~ ecgtl. ir.J! ir1itIal slatto ')f TCu<. IS not defined. When TENA is HIG~. TIt data is ' . .nct.....
enc:oct.d on !he i*'G ~~ of Xl ener tne r"ISIt".g edge CIt TCL'"
4. X, V... Met X, VIL .... not saallCAlly teaId. 1.imiIa . . c:orreIMed to ..... ,..,. when operdng et 20 MHz under Cf'IS18I control.
When X, is c:tiYen by 811 ~ cIoc:il. X2 should be left ftoating 8M !he Xl iI1IUt must h8Ye the foIowing c::t.ac1eIisticS:
Clock F~ 20.0 MHz !0.C1"
RiM/Fai Tme (tR/IF): Less ttwt 2 ttl from 0.8 V to 2.0 V
X, HIGH/LOW Ttme ClttIGH/lLOwl: Gre.1er !han 20 ns
X, Feling Edge to F8IIing Edge JitI.er Less !han i 0.2 ns at 1.5 V input
6. Not men ~ one ouIpII. st'oOI.IId be Ihor'IeO at • .... O..ation of h Ihotl CIrQMt ..ac IhouId not exceecI one second..
i. AuumeI 5().pF capecilanCtt i08drng or. ACL~ and RX.
8. T....., under c:oncIitions not idenIic:aI 10 data shNl
8. T-.t c:annol be irnpIemv.1tad !IO da".a . . . requirWnenIa.

2. T..-,. but 10 ~ in
3. TW; cI'IengM mff! oro

s.

SWITCHING WAVEFORMS

WF0101!111

NcMa: A) Minimum WIdIh >.s ,.
B) ACU< - INTACLK wtwn TEST LOW
C) RX undefined untI bit lime 5 (1. decoded bit)
0) 08ciIIat0r InIerTupl 1M)' oc:cu at 2nd INTRCLK IftIr BIl 2 Clock TI'InIIIon
E) Timing o.gr.rn doea not indude ........ ~i DeIIIp
F) FnI VIiIid dIIta at RX C8'I 5)

Receive TImIng - SDrt of ReceptIon Clock AcquIaItIon

PU. CU<

WF010111
Notee: A) INTCARR .......,. 1.55 bit IImeI IftIr .... Aecehet ~ Edge
B) SWt of .... P8cket

Recetve TImIng - End of Reception (Uat BIt

10

=0)

SWITCHING WAVEFORMS (COnt.)

WF010701

Now.: A) INTCAAR deu8«'ta 1.55 bit tme. .... !at

~

RilIng Edge

Receive TIming - End of Reception (Last BIt

=1)

(NOTE A)

x,
TCLJ(

TX

TSEL
TrwwnIt+

T........

WF010710

Sine W..,. from Cryst8I 0aciIat0r or DrMn witt X, DrMn from ex..m.a Source W.-orm
B} TSEl connected .. Ihown in Fvn 28. For Fig&n 2A, Trw.1Iit+ • HIGH when TENA • LOW
C) When Idle T,..,.,mi Zero ~ ia 1/2 (YH + Va)

~ A) X, 2O-MHz

Tranamit TImIng - StIwt of P8cket

11

SWITCHING WAYEfORIIS (ConI.)
x,

TSEL
1)(

cu.~; 0) _ _ _ _ _ _...4,.'I"lii.iiliril"I'~..lrpl'I"

T,.,.,...+
TfIIfIMIiI-

r-------------......-J0.5 Vo" 2 ,.

1'--_.....!L.J

TIWWIIit+
T_ _ _

J

....... 1
T...-.b

~

Vo

L l I___
rl

'To -,---I

Ir--------------......,~, 0.5

LJ

Vo ..

2,.

WF010721

T.........mer TImIng - End of T,...", ••,on*
*TSEL Components (see F"9Jf828)
See Typical Performance Curve for Response at End of Transmission with Inductive loads

@

=1. ._.

V____
WFOO7191

CoIHaIon TIming

12

SwrrcHING WAVEFORMS (Cont.)

y.~

f-111

-V)

f-m

-V)

".IIIIIL.

----r------1:......----oIi----~----++-----~-

WF007202

Recelve:t Input PuIM WIdth TImIng

v.~

f-171

-V) _ _ _~-----"t..-----~--

"..... ---~----#i-------+l~-f-m
-V)

1----@--~-4r----­

_____II

2.OV

WF007211

CoIIIsIon± Input PuIM WIdth nmlng

1-------~0

WFOO7222

RCLK .nd RX nmlng

13

SWITCHI~ WAVEFORMS (Cont.)

TClJ(

TENA

WF007232

Tell( end TX TImIng

X,
ORIVING

INPUT
~.

TCLK

Transmit+, TransmiI(Note

Al

ace

BC8

(BIT CELL CENTER)

(BIT CELL BOUNDARy)

WF010730

• See Specification for External TIL Level in Functional Description section.
Notes: A) Encode Manchester clock transition (Bee) at Point 'A' and bit cell edge (BCB) at point '8:

X1 Drtven from External Source

14

SWITCHING WAVEFORMS (COnt.)

I'

flU.

1

cue:
4.5 V

..

3V----~------~------~----~--~
0.4.5 y.,.5 V
0-1.5 V-

.3 V
~

0+4.5 y-

~

.'.5 V

S

1

FIeceHe~

-4.5 vAX

~+

0+4.5 '1-

0

1

~

+1.5 \1-

.'.5 '1~

-1.5

0-

v-

AX

~

5

I

+3 V~
~

.'.5 V0-1.5 V-

AX

Notes: 1.)

c..

t, lOBI ......... 0. 1

Riling clock edge IIICIWd aow.d 1/4 bit cell ACU< dIda strobe. Cue
1 . . . bit 5,
5 . . . bit 55.
B)
2, • DMI ......... " 0
Filling clock edge IIICIWd aow.d 114 bit cell ACU< dIda strobe.
2 . . . bit ..
I . . . bit se.
C)
3. 7 DMI ......... " 1
Filling bit cell edge IIICIWd aow.d 1/4 bit eel ACLK dIda strobe.
3 . . . bit 8, cae 7 . . . tift se.
0)
4, • o.ta • P.n.m X. 0
Riling bit cell edge IIICIWd IDWW'd 1/4 bit cell ACU< dIda SWobe.
" u.s bit 5, cae 8 . . . bit 55.

c:a.

c..

c:a.

c:a.

c..

c:a.

c..

c:a.

Input Jitter TIming

15

TYPICAL PERFORMANCE CURVE
End of Tranamlaalon - otfferentlal Output Voltage-

~

too
~~~~~4--+--+--+--~~~~~~~

R,. 710@
~ -+---+--+--+--1---4

I-+--+-'\-+-+"r--,.'t-'- L =: •

I
~~~--~~~±R-710®~-4--+-+-~
L=75~

1.0

2.0

3.0

•. 0

5.0

1.0

TIllE

u.s)

0P00191 0

-Equivalent Load:

Notea:

1. 802.3 Te.t Load:

75 .. H NOlI.

75 ..H NOM.

"'"7996

2. 802.3 10 Base 5 Network Connection:

3. 802.3 10 Base 2 Network Connection:

DFOO503O

16

SWITCHING TEST CIRCUITS

TCDOO472

8. T.......at± Output

A. Test Load for AX, RENA, ACLI(,
TCLI(,CLSN

C. AeceIve± and CoIIIaion± Input

KEY TO SWITCHING WAVEFORMS

_VfFOllll

-..
lIIfff

H

.WUtI

~

IIUIT.
STEADY

STlAO'f

IllAYCICAIIIGI
~_"TOL

IllAYC......f
' _ L TO"

OOII"TCAAI.
Ml'tCMAlllGl
"_TT1D

WILL.

WILLIE

CMAIIGIIC

F _ .. TOL

WILLIE
C_IIIG
F_L TOM

--

CMAIIGIIC.
STAn

CIIITP
DOHIIOT
-.Y

L. . . . . . . .

_DUCI
"OIF-STAn

KS000010

17

PHYSI~AL DIMENSIONS

CD3024

PD3024

I-

~=

-I

~::::::::::Ii

~~.005M1N.

PID

18

'*' 0701tA

ADVANCED MICRO DEVICES
DOMESTIC SALES OFFICES
ALABAMA ...
ARIZONA.
Tempe ..
Tucson.
CALIFORNIA.
EI Segundo ..
Newpott Beach .

BELGIUM.
Bruxelles

TEL.
FAX
TLX:

(602) 242-«00
(602) 792·1200
(213)
(714)
(619)
(408)
(818)
(303)

San Diego ..
Sunnyvale .....
Woodland Hills.

COLORADO ....
CONNECTICUT.
Southbury ...
FLORIDA.
Altamonte Springs
Clearwater .
Ft. Lauderdale
Melbourne .
GEORGIA ..
ILLINOIS .... .
INDIANA .. .
KANSAS ................. ..
MARYLAND.
. ................... .
MASSACHUSETTS. . ........................ .
MINNESOTA...
. ...................... ..
NEW JERSEY..
. .................... ..
NEW YORK,
L.iverpooI ....
. .................................... .

Poughkeepsie ..
Woodbury ..
NORTH CAROLINA,

INTERNATIONAL SALES OFFICES

(205) 882·9122

CANADA, Ontario.
Kanata .
Willowdale

640·3210
752·6262
560·7030
720-8811
992-4155
691·5100

. ....... (02) 771 99 93
... 762·3716
... 61028

TEL.
. (613) 592·0060
TEL. . ........ (416) 224·5193
FAX ..
. ... (416) 224-0056

FRANCE.
Paris ...

TEL
FAX:.
TI )(.

...... (01) 687.36.66
. ... 6862185
.20253

(203)
(305)
(813)
(305)
(305)
(404)
(312)
(317)
(913)
(301)
(617)
(612)
(201)

EJ~~~ In HKOALNTRON
GRUPPE

m

BLEITER

8057 Eching bei Munchen, Breslauer Stra8e 16
Tel. (089) 31901-3n· Telex 5212467· Telefax (089) 31901-499
85 Ni.irnberg 20, Rennweg 60162. Te!efon (0911) 533306 Telex 626391
8057 Ectl/rlQ, Breslauer SlraBe 16, Telefon (089) 31901·367' Telex 52i2467
30, MaybachstraBe 39a, Telefon (0711) 8917.140 Telex 723061
rankfun 70. Kennedy·AlIee 34. Telefon (0691 6317.144' Telex 414881
; Dusseldorf " Ronsdorfer SIr 145 Telefon (0211) 7361"50,' Telex 8582675
Hannover 81. Hermann·Guthe·Str 3, Telelon (0511) 839051·57, Telex 923729
2 Hamburg 70. KOnl9srelhe 4. Teleton (040) 68295·122, Telex 211998

~ ~tuttgart

(315)
(914)
(516)
(704) 52>1875

"I'V\ .... .

ChaI1one.

TLX: .......... J24064 AMDTKOJ

Raleigh ........
OREGON
OHIO,
Columbus ..
PENNSYL VANIA.
Allentown .
Willow Grove
TEXAS.
Austin .
Dallas ..
Houston
WASHINGTON
WISCONSIN.

LATIN AMERICA.

Ft. Lauderdale, ..... .

(503) 245-0080

SWEDEN, Stockholm

(614) 891-&455
(215) 398-8006
(215) 657-3101
(512)
(214)
(713)
(206)
(414)

TEL:
FAX:
.... TEL: ..
FAX:
TLX:

UNITED KINGDOM,
Manchester area .

34&-7830
934·9099
785-9001
45>3600.
782·7748

. TEL
FAX.
TL)(

London area ......

TEl.
FAX: ..
TL)(

....... (305) 484·8600
... (305) 485·9736
.. (08) 733 03 50
7332285
11602
«()j,,25) 828008
827693
.626524
(04862) 22121
22179
859103

NORTH AMERICAN REPRESENTATIVES
CALIFORNIA
12 INC

NEW JERSEY
T AI CORPORA T!ON
NEW MEXICO
THORSON DESERT
NEW YORK
NYCOM. INC
OHIO
Day10n
OOLFUSS ROOT &
Strongsviile
OOLFUSS ROOT &
PENNSYLVANIA
OOLFUSS ROOT &
UTAH
R2 MARKETiNG.

.. OEM (408) 988·3400
DISTI (408) 498·6868

CONNECTICUT
SCIENTIFIC COMPONENTS.
IDAHO
INTERMOUNTAIN TECH MKGT.
INDIANA
SAl MARKETING CORP
IOWA
LORENZ SALES
MICHIGAN
SAl MARKETING CORP
NEBRASKA
LORENZ SALES

· (203) 272·2963
(208) 322·5022
.. (317) 241·9276
· (319) 377·4666
· (313) 227·1786
(402) 475·4660

(609) 933·2600
STATES

(505) 293·8555
(315) 437·8343

CO

(513) 433·6776

CO

(2 1 6) 238·0300

CO

(412) 221·4420
(80') 595·0631

...~ Iohcro o..oc:.s ,_ _ 1tle ngI'II to ...... ChenIIn WI lIS produc:1 -.out notice on order to tmpre»re  produce the highest levels
of quality, reliability. and cost effectiveness. The
Am28F010 electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.

Put:llicll1OM 11551

Issue Dale: ..kIM 1810

Rev. B

~menLO

BLOCK DIAGRAM

~

Vee ---.

Vss ---.

Erase
Voltage
Switch

Vpp

-..

State

Control

f

InputlOutput
Buffers

I

To Array

.,

£~
I---

.A

~

......

I

Command
Register

Program
Voltage
Switch

Chip Enable
Output Enable
Logic

•

r

I

•

Data

latch

"'"7
Y-Gating

V-Decoder

,

'7

.J:;

0

co

•
•
•

...J
CI)
CI)

V

Q)

-0
~
<

X-Decoder

1,048,576
Bit
Cell Matrix

......

•

11561~18

PRODUCT SELECTOR GUIDE
Am28F010

Family Part No.

Ordering part No:
± 19ro Vcc Tolerance
± 50/0 Vee Tolerance
Max Access Time (ns)
CE (E) Access (ns)
OE (G) Access (ns)

2

-90
-95
90
90

-120

-150

-200

-

-

-

120
120

150
150

40

50

65

200
200
75

Am28F010

CONNECTION DIAGRAMS
LCC/PLCC

DIP

N

In

to

co

a..
c..

0
.0

B
~

(,)

VPJ'

Vee

A1S

'NE(W)

A1S

NC

A12

A14

A7

A14

A7

A13

~

A13

As

As
Ag

As

As

As

~

An

A4

A9

A3

OE(G)

A3

A1l

A2

A,o

A2

OE(G)

Al

CE(E}

Al

Ala

IvJ

007
DOs

Ao

CE(E)

000
001

005

002

004
003

Vss

«{

<

<

>

~

Z

DOo

007

aQ

11559-0028

N

aQ

(/)
(/)

>

M

a

Q

...

aQ

In

aQ

co

aCI

11559-0038

Note: Pin 1 is marked for orientation

LOGIC SYMBOL

000- 007

- - -... CE(E)
-

__~OE(G)

---~

WE(W)

11559-OO4A

Am28F010

3

PIN DESCRIPTION

4

Symbol

Functional Description

Ao-A16

Address Inputs for memory locations. Intemallatches hold addresses during write cycles.

000-007

Data Inputs during memory write cycles. Intemallatches hold data during write cycles. Data
Outputs during memory read cycles.

CE (E)

The Chip Enable active low input activates the chip'sco'ntrollog4c and input buffers. Chip
Enable high will deselect the device and operates the chip in sta~-by mode.

OE(G)

The OUtput Enable active low input gates the outputs of the deviCe through the data buffers
during memory read cycles.

WE(W)

The Write Enable active low input controls the write function of the command register to the memory array. The target address is latched on the falling edge of the Write Enable pulse and the ap
propriate data is latched on the rising edge of the pulse.

Vpp

Power supply for erase and programming. Vpp must be at high voltage in orderto write to the command register. The command register controls all functions required to alter the memory array
contents. Memory contents cannot be altered when Vpp ~ Vee +2V.

Vee

Power supply for dev~ce operation. (5.0V ± 50/0 or 100/0)

Vss

Ground

NC

No Connect-corresponding pin is not connected internally to the die.

Am28F010

ORDERING INFORMATION
Standard Products
AMO standard products are available in several packages and operating ranges. The ordering number (Valid Combination)
is formed by a combination of:
a. Device Number
b. Speed Option
c. Reprogram Cycles
d. Package Type
e. Temperature Range
f. Optional Processing

I
J

T

195

AM28F010-

IC4.

TL.___ f. OPTIONAL PROCESSING

C

Blank - Standard processing
B- Bum-in

.......- - - - - e. TEMPERATURE RANGE
C - CommerdaJ (0 to +70°C)
I • Industrial (-40 10 + 85"C)
E - Extended (-55 to + 125°C)

I
.

~----------------d.PACKAGETYPE

011: 32-Pin Ceramic DIP (CD 032)
l = 32-Pin Rectangular Ceramic lead less
Chip Carrier (Cl 032)
P = 32-Pin Plastic DIP (PO 032)
J = 32-Pin Rectangular Plastic leaded
Chip Carrier (Pl 032)

~----------- c. REPROGRAM CYCLES (10x)
C4
C3
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

:0:

:0:

10,000 cycles minimum
1,000 cycles minimum

b. SPEED OPTION
See Product Selector Guide and
Valid Combinations

" - - - - a. DEVICE NUMBER/DESCRIPTION
Am28F010
_
1 Megabit (128K x 8"3it) CMOS Flash Memory

Valid Combinations
C4DC. C40CB. OWl,
C40IB. C40E. C40EB,
C4lC. C4lCB, C4l1,
AM28F010-95 , C4l1B. C4LE. C4l.EB.
AM28F010-90
C4PC. C4PI, Q4JC.
AM28FO 10-120 C4J1. C3DC, C3OCB.
AM28F010-150 c3bl. C30IB, C3QE,
AM28FO 10-200 C3DEB, C3LC. C3l.CB.
C311' C311B, C3lE.
C3lEB. C3PC. C3Pt,
C3JC. C3J1

Am28F010

Valid Combinations
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local AMO sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.

5

ORDERING INFORMATION
APL Products
AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APl
(Approved Products list) products are fully compliant with Mll-STD-883C requirements. The order number (Valid Combination) is formed by a combination of:
a. Device Number
b. Speed Option
c. Reprogram cycles
d. Device Class
e. Package Type
l Lead finish

AM28F010

-90

C4

/B

u

A

T'-____ f. LEAD FINISH
A - Hot Solder Dip

' - - - - - - - - e. PACKAGE TYPE
X - 32-Pin Ceramic DIP (CD 032)
U - 32-Pin Rectangular Ceramic
Leadless Chip Carrier (Cl 032)
- - - - - - - - - - - d. DEVICE CLASS
18 = Class B
- - - - - - - - - - - - - c. REPROGRAM CYCLES (1 Ox)
C4 = 10,000 cycles minimum
C3 = 1,000 cycles minimum
~------------------~SPEEDOFnON

See Produd Selector Guide and
Valid Combinations

~--

a. DEVlCE NUMBER/DESCRIPTION
Am28F010
1 Megabit (128K x 8-Bit) CMOS Flash Memory

Valid Combinations
AM28FOl0-9O
AM28F010-120
AM28F010-150
r

C41BXA. C418UA
C31BXA. C31BUA

Valid Combinations
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
SpecifIC valid combinations and to check on newty
released combinations.

AM28F010-200

Group A Tests
Group A tests CX)nsist of Subgroups
1.2.3,7,8.9. 10, ,,:

6

Am28F010

BASIC PRINCIPLES
The Am28F010 uses 100% TIL-level control inputs to
manage the command register. Erase and reprogramming operations use a fixed 12.0V ± 5·0/0 power supply.

Read Only Memory
Without high Vpp voltage, the Am28F010 functions as a
read only memory and operates like a standard
EPROM. The control inputs still manage traditional
read, standby, output disable, and Auto select modes.

Command Register
The command register is enabled only when high voltage is applied to the Vpp pin. The erase and reprogramming operations are only accessed via the register. In
addition, two-cycle commands are required for erase
and reprogramming operations. The traditional read,
standby, output disable, and Auto select modes are
available via the register.
The Am28F010's command register is written using
standard microprocessor write timings. The register
controls an internal state machine that manages all device operations. For system design Simplification, the
Am28F010 is designed to support either WE or CE
controlled writes. During a system write 9:£Ie. addresses are latched on the falling edge of WE or CE
whiChever occurs last. Data is latched on the rising edge
of WE or CE whichever occur first. To simplify the follow~
ing discussion, the WE pin is used as the write cycle control pin throughout the rest of this text. All setup and hold
times are with respect to the WE signal.

Overview of Erase/Program Operations
Erase Sequence
A multiple ~t~p command sequence is required to erase
the Flash device (a two-cycle Erase command and repeated one cycle verify commands).

Note:
The Flash memory array must be completely programmed prior to erasure. R~erto the Flasherase
Algorithm.
1. Set-up Erase: Write the Set-up Erase command to
the command register.

The second command initiates the erase operation.
The system software routines must now time-out the
erase pulse width (10 ms) prorto issuing the Eraseverify command.
3. Erase-verify: Writefhe Erase-verify command to
ttle command register. This command terminates
the" erase C)peration. ~fter the erase operation, each
byte of the array muSt be verified. Address information must be supplied with the Erase-verify command. This command verifies the margin and
outputs the addressed byte in order to compare the
array data with FFH data (Byte erased). After successful data verification the Erase-verify command
is written again with new address information. Each
byte of the array is sequentially verified in this
manner.
If data of the addressed location is not verified. thr
Erase sequence is repeated until the entire array is successfully verified or the sequence is repeated 1000
times.
Programming Sequence
A three step command sequence (a two-cycle Program
command and one cycle Verify command) is required to
program a byte of the Rash array. Refer to the Flashrite
Algorithm.
1. Set-up Program: Write the Set-up Program command to the command register.
2. Program: Write the Program command to the command register with the appropriate Address and
Data. The system software routines must now timeout the program pulse width (10 J1S) prior to issuing
the Program-verify command.
3. Program-verify: Write the Program-verify command to the command register. This command terminates the programming operation. In addition, thi~
command verifies the margin and outputs the byte
just programmed in order to compare the array data
with the original data programmed. After successful
data verification, the programming sequence is initiated again for the next byte address to be programmed.
If data is not ve,-ified,.the Program sequence is repeated
until a successful cPmparison is verified or the sequence is repeated 25times..

2. Erase: Write the Erase command (same as Set-up
Erase command) to the command register again.

Am28F010

7

FUNCTIONAL DESCRIPTION
Description Of User Modes
Table 1. Am28F010 User Bus Operations
Operation

Read-Only

CE

(E)

OE

WE

(G)

(W)-

Vpp
(Note 1)

Ao

Ag

110

Vp.~

Ag

Ao

Dour

Read

Vil

VI..

Vg.f

Standby

VIH

X

X.

Vp~

X
X

X
X

HIGHZ
HIGHZ

Output Disable

Va.

VIH

VlH

Vppt(

Auto-select Manufacturer
Code (Note 2)

Va.

Va.

Vt4

VpPl

Va.

VrJ
(Note 3)

CODe

Auto-select Device Code
(Note 2)

VL

Va.

VIH

VpPl

VIH

VJD
(Note 3)

CODE
(A7H)

Read

VIl.

VIl.

VIH

VPPH

Ao

Ag

(01 H)

Dour
(Note 4)

ReadJWrite

Standby (Note 5)

VIH

X

X

VPPH

Output Disable

Vtt

VIH

VIH

VPPH

Write

VIL

VIH

VIL

VPPH

X
X
Ao

X
X

HIGHZ
HIGHZ

Ag

DIN
(Note 6)

Legend:
X = Don't care, where oon"1 Care is either Vtt or VIH levels. VPPl = VPP < Vee + 2V, See DC Characteristics for voltage levels of VPPH, OV < An 

0

Data (DQ)

5.0 V

V:.c

OV
VPPH
Vpp

VPPL
11561·014A

Figure 6. A.C. Waveforms for Erase Operations

Program Command
latch Address &
"
Data • _. ,.~~g!~mmlng

Verify'
Com"2an~

Programming
Verification
A

•

A

Standbyl
Power-Down

a....--.---..

Addresses

CE (c)

-------+----..1-$$

nr: (0)

...

tWHWH1

1~

...

»

3t,)
())

~(W)

"T1

o
-I.

o

HIGHZ
Data (OQ)
tElOX (tLZ)

'tt

tnov (teE)

~~

5.0 V

Vee

ov

tVPEl

~

VPPH
Vpp
VPPL

11561-015A

Figure 7. A.C. Waveforms for Programming Operations
f',.)

-....

SWITCHING TEST CIRCUIT
2.7k.n

Device
U~ ~----------~~--<

Test

I~

Diodes ~ IN3064
or Equivalent

6.2 k.n

11561-012A

Ct. - 100 pF including jig capacitance (30 pF for Am28FO 10-95)

SWITCHING TEST WAVEFORMS
2.4 V

>
2.0 V

TEST POINTS

O.45"V

--..I

INPUT

0.8 V

:: ~~~~~~X:

<

2.0 V

·0.8 V

OUTPUT

.5- TEST POINTS-l.5X",,_ _

INPUT

OUTPUT "

All Devices Except Am28FO'O-95

For Am28F010-95

AC Testing: Inputs are driven at 2.4 V for a
logic ",. and 0.45 V for a logic "0·. Input pulse
rise and fall times are ~ '0 ns.

AC Testing: Inputs are driven at 3.0 V for a
logic .. ,. and 0 V for a logic "0". Input pulse rise
and fall times are ~ 10 ns.
08007-OO3A

28

Am28F010

ERASE AND PROGRAMMING PERFORMANCE
Limits
. I

Parameter

Min.

Chip Erase Time
Chip Programming Time

Typ.

Max.

0.5
(Note 1)

10

2
(Note 1)

24

s.
1-

S

I

Comments

Unit

ExCludes OOH programming
prior. to erasure
- ,
Excludes
system-level overhead
\.
".

Erase/Program Cycles

Am28FO 10-95C4JC

10,000

Cycles

Am28F010-95C3JC

1,000

Cycles

Note:
1. 25°C. 12V Vpp

LATCHUP CHARACTERISTICS
Input Voltage with respect to Vss on all pins except 110 pins
(Including Ag and Vpp)
Input Voltage with respect to Vss on all pins

va pins

Current

Min.

Max.

-1.0V

13.5 V

-1.0V

Vcc+ 1.0 V

-100 rnA

.+ 100 rnA

Includes all pins except Vee. Test conditions: Vee = 5.0 V. one pin at a time.

Am28F010

29

SYS68K1EAGLE-01C USER'S MANUAL

6. ORDERING INFORMATION
Name of Product

Description

SYS68K1EAGLE-OIC

EAGLE Module for the CPU board.

SYS68K1EAGLE-Ol C/UM

User's manual for the EAGLE-OIC.

Page 61

FORCE COMPUTERS

This page is intentionally left blank.

Page 62

SYS68K1EAGLE-OIC USER'S MANUAL

7. mSTORY OF MANUAL REVISIONS
Revision
No.

Description

Date of Last
Change

0

First Print

FEB/04/1991

1

Default Switch Setting in Figure 2-2 was
changed.

AUG/16/1991

Page 63

FORCE COMPUTERS

This page is intentionally left blank.

Page 64

SYS68K1EAGLE-OIC USER'S MANUAL

8. PRODUCTERRORREPORT
DEAR CUSTOMER,
ALTHOUGH FORCE COMPUTERS HAS ACHIEVED A VERY HIGH STANDARD
OF QUALITY IN PRODUCTS AND DOCUMENTATION, SUGGESTIONS FOR
IMPROVEMENT ARE ALWAYS WELCOME.
ANY FEEDBACK YOU CARE TO OFFER WOULD BE APPRECIATED.
PLEASE USE THE ATTACHED "PRODUCT ERROR REPORT" FORM FOR YOUR
COMMENTS AND RETURN IT TO ONE OF THE NEAREST FORCE COMPUTERS
OFFICES.

FORCE COMPUTERS GmbH

Page 6S

HARDWARFJSOFTWARFJSYSTEMS
PRODUCT:

SERIAL NO.:

DATE OF PURCHASE:

ORIGINATOR:

COMPANY:

POINT OF CONTACT:

ADDRESS:

TELEPHONE:
EXT:

PRESENT DATE:
THIS AREA TO BE COMPLETED BY FORCE COMPUTERS:
DATE:
PR#:
RESPONSIBLE DEPT.:

-

ENGINEERING
MARKETING
PRODUCTION

AFFECTED PRODUCT:

-

-

HARDWARE
SOFTWARE
SYSTEM

AFFECTED DOCUMENTATION:

-

-

HARDWARE
SOFrWARE
SYSTEM

ERROR DESCRIPTION:

Please send this product error report to one of our nearest FORCE COMPUTERS offices:

FORCE COMPUTERS Inc.
3165 Winchester Blvd.
Campbell, CA 95008-6557
U. S. A.

FORCE COMPUTERS Gmba
Prof.-Messerschmitt-Str. 1
D - 8014 NeubiberglMunich
West Germany

FORCE COMPUTERS FRANCE Sari
11, rue Casteja
92100 Boulogne
France

FORCE COMPUTERS UK Ltd.
No. 1 Holly Court
3 Tring Road
Wendover
Buckinghamshire HP22 6PE
England

SECTION 6:

SYS68K/EAGLE MODULE

PLEASE INSERT

THE EAGLE MODULE MANUAL
IN THIS SPACE

INTRODUCTION TO VMEPROM
IN USE WITH THE SYS68K/CPU-40/41

This page was intentionally left blank

TABLE OF CONTENTS
1.

GENERAL

1-1

1.1

1-1
1-1

1.4.5

General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features of VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Front Panel Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABORT Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Memory Usage of VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default EPROM Usage of VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.

DETAILS OF THE CPU BOARD

2.1
2.2
2.3
2.4
2.5

EPROM/RAM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-board I/O Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-board Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Off-board Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The On-Board Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.

CONCEPT OF VMEPROM

3.1

1.2
1.3

1.4
1.4.1

1.4.2
1.4.3
1.4.4

.................................... .

1-2
1-3
1-3
1-3
1-3
1-7
1-7

2-1

.
.
.
.
.

2-1
2-2
2-3
2-4
2-4

........................................ .

3-1
3-1
3-1

3.3

Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Line Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VMEPROM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.

SPECIAL VMEPROM COMMANDS FOR CPU BOARD . . . . . . . . . . . . . . . . . . . . . .

4-1

4.1
4.2

4-1

4.7
4.8
4.9

ARB - Set the Arbiter of the CPU Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONFIG - Search VMEbus for Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FGA - Change Boot Setup for Gate Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLUSH - Set Buffered Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FMB - Force Message Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FUNCTIONAL - Perform Functional Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEM - Set Data Bus Width of the VMEbus . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PROG - Program FLASH EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SELFTEST - Perform On-board Selftest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.

INSTALLING A NEW HARD DISK WITH THE ONBOARD SCSI CONTROLLER ..... .

3.2

4.3
4.4

4.5
4.6

.
.
.
.
.
.
.
.
.

3-1

4-2
4-3

4-4
4-5
4-6
4-7
4-8
4-9

5-1

LIST OF TABLES
Table 1:

RAM Disk Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-5

Table 2:

Program After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-5

Table 3:

Boot an Operating System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-5

Table 4:

Examples in Using the Rotary Switches . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-6

Table 5:

On-board I/O Devices

2-2

Table 6:

On-board Interrupt Sources

2-3

Table 7:

Off-board Interrupt Sources

2-4

...................................... .

!!

INTRODUCTION TO VMEPROM

SECTION 7

1. GENERAL
1 . 1 General Information
This CPU board operates under the control of VMEPROM, an EPROM resident real time multiuser
multitasking monitor program. VMEPROM provides the user with a debugging tool for single and
multitasking real time applications. This manual describes those parts of VMEPROM which pertains
to the hardware of the CPU. All general commands and system calls are described in the VMEPROM
User's Manual.

1.2 Features of VMEPROM
•

Line assembler/disassembler supporting all 68040 instructions.

•

Numerous commands for program debugging, including breakpoints, tracing, processor
register display and modify.

•

Display and modify floating point data registers of the (68040 versions only).

•

S-record up/downloading from any port defined in the system.

•

Time stamping of user programs.

•

Built-in Benchmarks.

•

Support of RAM-disk, floppy and Winchester disks, also allowing disk formatting and
initialization.

•

Serial I/O support for up to two S10-1 /2 or ISI0-1/2 boards in the system.

•

EPROM programming utility using the SYS68K/RR-2/3 boards.

•

Full Screen Editor.

•

Numerous commands to control the PDOS kernel and file manager.

•

Complete task management.

•

I/O redirection to files or ports from the command line.

•

Over 100 system calls to the kernel supported.

•

Data conversion and file management functions.

•

Task management system calls in addition to terminal I/O functions.

1-1

SYS68K/CPU~40/41

USER'S MANUAL

FORCE COMPUTERS

1.3 Power-up Sequence
After power-up, the 68040 retrieves the initial stack pointer and program counter from address
locations $0 and $4. These locations are the first 8 bytes of the EPROM area. They are mapped
down to address $0 for a defined start after reset or power-up. Control is transferred to the BIOS
modules to perform all the necessary hardware initialization of the CPU. The real time kernel is
started and the user interface of VMEPROM is invoked as the first task. This sequence also reads
the Real Time Clock (RTC) of the CPU board and initializes the software clock of the kernel. If a
terminal is connected to the terminal port of the CPU board, the VMEPROM banner and the
VMEPROM prompt ("? ") will be displayed upon power-up or reset.
The default terminal port setup is as follovvs:
Asynchronous communication
9600 Baud
8 data bits
1 stop bit
no parity
Hardware handshake protocol
If the above message does not appear, check the following:
1)

Baud rate and character format setting of the terminal (default upon delivery of the CPU board
is 9600 Baud, 8 data bits, 1 stop bit, no parity).

2)

Cable connection from the CPU board to the terminal (refer to the Hardware User's Manual
for the pinning of the O-Sub connector and the required handshake signals).

3)

Power supply, + 5V, + 12V, -12V must be present. See the Hardware User's Manual for the
power consumption of the CPU board.

If everything goes well, the header and prompt are displayed on the terminal and VMEPROM is now
ready to accept commands.

1-2

SECTION 7

INTRODUCTION TO VMEPROM

1.4 Front Panel Switches
1 .4.1 RESET Switch
Pressing the RESET switch on the front panel causes all programs to terminate immediately and
resets the 68040 processor and all 1/0 devices.
When the VMEPROM kernel is started it overwrites the first word in the user memory after the task
control block with an EXIT system call. If breakpoints were defined and a user program was running
when the RESET button was pressed the user program could possibly be destroyed.
t

t

Pressing reset while a program is running should only be used as a last resort when all other actions
(such as pressing AC twice) have failed.

1.4.2 ABORT Switch
The ABORT switch is defined by VMEPROM to cause a level 7 interrupt. This interrupt cannot be
disabled and is therefore the appropriate way to terminate a user program and return to the
command level of VMEPROM.
If ABORT is pressed while a user program is under execution all user registers are saved at the
current location of the program counter and the message "Aborted Task" is displayed along with the
contents of the processor register.
t

If ABORT is pressed while a built-in command is executed or the command interpreter is waiting for
input, only the message is displayed and control is transferred to the command interpreter. The
processor registers are not modified and are not displayed in this case.

1 .4.3 Control Switches
The two rotary switches on the front panel of the CPU board define the default behaviour and
actions taken by VMEPROM after power up or RESET.
The default definition of some of these switches can be patched in the EPROMs for the user's
convenience. Please refer to the Appendix of this manual for a description of the memory locations
to be patched.
The switch settings are read in by VMEPROM after reset and control various options.

1-3

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

The following describes the software definition for every switch:
Upper Rotary Switch (SW2):

Bit 3:

If this bit is set to "0", the RAM disk is initialized as defined by bit 0 and 1 of SW2.
When the disk is initialized, all data on the disk is lost.

Bit 2:

This bit defines the default data bus size on the VMEbus. If the bit is set to "0", 16
bits are selected, if it is set to "1 ", 32 bits are selected.

Bit 1:

and
Bit 0:

These two bits define the default RAM disk. See Table 1 for a detailed description.
If Autoboot is set by bit 2 and bit 3 of SW1, bit 1 and 0 of SW2 define which
operating system will be booted. See Table 3 for detailed description.

Lower Rotary Switch (SW1):

Bit 3:
and
Bit 2:

These two bits define which program is to be invoked after reset. Please refer to
Table 2 for a detailed description.

Bit 1:

If this switch is "0", VMEPROM tries to execute a startup file after reset. The default
filename is SY $STRT. If the bit is "1 ", VMEPROM comes up with the default banner.

Bit 0:

If this switch is set to "0", VMEPROM checks the VMEbus for available hardware after
reset. In addition VMEPROM waits for SYSFAIL to disappear from the VMEbus. The
following hardware can be detected:
Contiguous memory starting at the end of the on-board memory
ISI0-1/2
SI0-1/2
ISCSI-1
Please refer to Chapter 4.2 of this section for details.

1-4

INTRODUCTION TO VMEPROM

SECTION 7

Table 1: RAM Disk Usage
Bit 1
1
1
0
0

Upper Switch (SW2)

Bit 0
1
0
1
0

=
=
=
=

RAM DISK
RAM DISK
RAM DISK
RAM;DISK

AT
AT
AT
AT

TOP OF MEMORY (32 Kbytes)
$FFC10000 (64 Kbytes)
$40700000 (512 Kbytes)
$40800000 (51 2 Kbytes)

Table 2: Program After Reset
Bit 3

Lower Switch (SW1)

Bit 2

1

1

=

1
0
0

0
1
0

=
=
=

VMEPROM (OR USER PROGRAM at same
location)
USER PROGRAM AT $FFC10000
Autoboot System
USER PROGRAM AT $40800000

Table 3: Boot an Operating System
(Valid only if SW1 is set to Autoboot)
Bit 1
1
1
0
0

Upper Switch (SW2)

Bit 0
1
0
1
0

=
=
=
=

Boot PDOS
Boot UNIX
Boot another operating system
Setup for UNIX mailbox driver

1-5

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

Table 4: Examples in Using the Rotary Switches

I

Rotary Switches
Description
Upper

Lower

$F

$F

No RAM Disk initialization will be done.
The VMEbus data size is 32 bits.
The RAM Disk is on top of memory.
V~Y~EPRO~y~ vvi!! be started.
No start file will be executed.
The available hardware on the VMEbus will not be
checked.

$4

$C

RAM Disk intialization will be done.
The VMEbus data size is 32 bits.
The RAM Disk is located at address $40800000.
VMEPROM will be started.
VMEPROM tries to execute a startup file.
The available hardware on the VMEbus will be checked.

$8

$7

The VMEbus data size is 16 bits.
Autoboot System is enabled.
POOS will be booted.

I
I
!

I

1-6

INTRODUCTION TO VMEPROM

SECTION 7

1 .4.4 Default Memory Usage of VMEPROM
By default, VMEPROM uses the following memory assignment for the CPU board:

MEMORY LAYOUT OF THE ON-BOARD RAM
$00000
Vector Storage of the 68040

$00400
$00800
$01000

System configuration data
General purpose RAM, reserved
for system commands

Kernel System RAM

$07000
Task Control Block for
first task

$08000
User memory

Mail Array

Highest on-board
memory address

Hashing Buffer for Disk 1/0

Please note that the size of the first task cannot be extended beyond the highest on-board memory
address. However, the additional memory which can be installed may be used for data arrays or for
creating new tasks. The maximum memory which may be used for tasking is 64 Mbytes. If more
memory is available, it can only be used for data storage, but not for tasking memory.

1-7

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

1.4.5 Default EPROM Usage of VMEPROM
MEMORY LAYOUT OF THE SYSTEM EPROM

$FFOOOOOO

Initial Supervisor Stackpointer
$FF000004

Initial Program Counter
$FF000008

Pointer to VMEPROM Initialization
$FFOOOOOC

I

Pointer to User Alterable Memory Locations
$FF000010

Pointer to VMEPROM shell

I

II

BIOS Modules
Kernel
File Manager

!

EPROM resident installable devices and tables

!I
II
I

VMEPROM Intialization Code
User Alterable Memory Location
System Tools
VMEPROM Shell
System Tools
Debugging Tools
Line Assembler/Disassembler
$FF040000

Floating Point Software Library
$FF050000

UNIX Boot Program
$FF058000

Another Boot Program
$FF060000

PDOS Boot Program
$FF080000

1-8

I

I
IIIi

I I I
I

!

'

I

I

I

:}T

II

I

I
.. J

INTRODUCTION TO VMEPROM

SECTION 7

2. DETAILS OF THE CPU BOARD
2. 1 EPROM/RAM Layout

Device

Address
00000000

/

Local RAM

"

......... *
FFOO 0000
EPROM Area

"

FF7F FFFF
FFCO 0000
SRAM Area

"

FFC7 FFFF
FFC80000

"

FLASH EPROM Area

FFCF FFFF
FFEO 0000
EPROM Area

"

FFEF FFFF

• - Hightest On-board Memory Address

2-1

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

2.2 On-board 1/0 Devices
The following table shows the base addresses of the on-board I/O devices.

Table 5: On -board 1/0 Devices
BASE ADDRESS

DEVICE

$FF803000

RTC 72423

$FF802000

DUSCC 1 68562

$FF802200

DUSCC2 68562

$FF800COO

PI/T1 68230

$FF800EOO

PI/T268230

$FFDOOOOO

FGA-002

2-2

SECTION 7

INTRODUCTION TO VMEPROM

2.3 On-board Interrupt Sources
The following table shown is used for the on-board interrupt sources and levels which are defined
by VMEPROM. All interrupt levels and vectors of the on-board I/O devices are software
programmable via the FGA-002 Gate Array.

Table 6: On-board Interrupt Sources

DEVICE

INTERRUPT LEVEL

INTERRUPT VECTOR

Abort Switch

7

232

PI/T1

5

242

DUSCC1

4

244

DUSCC2

4

245

2-3

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

2.4 Off-board Interrupt Sources
VMEPROM supports several VMEbus boards. As these boards are interrupt driven the level and
vectors must be defined for VMEPROM to work properly. The following table shows the default
setup of the interrupt levels and vectors 'of the supported hardware. For a detailed description
of the hardware setup of the boards, please refer to the Appendix of this manual. The supported
I/O boards together with the base addresses and the interrupt level and vector are summarized
in Table 7. In order for these boards to work correctly with VMEPROM, the listed interrupt
vectors may not be used.

Table 7: Off-board Interrupt Sources

Board

Interrupt Level Interrupt Vector Board Base Address

SI0-1/2

4

64-15

$FCBOOOOO

IS10-1/2

4

76-83

'$iFC:9'SOOO:O

ISCSI-1

4

119

$FCAOOOOO

2.5 The On-Board Real Time Clock
During the power up sequence, the on-board real time clock of the CPU board is read and loaded
in the VMEPROM. This sequence is done automatically and requires no user intervention. If the
software clock of VMEPROM is set by the ID command as described in the VMEPROM User's
Manual, the RTC is set automatically to the new time and date values.

2-4

INTRODUCTION TO VMEPROM

SECTION 7

3. CONCEPT OF VMEPROM
3.1 Getting Started
After power-up or after RESET has been pressed, VMEPROM prints a banner showing the version
and revision being used and prints the prompt ("? ").
If the above message does not appear, check the following:
1)

Baud rate and character format setting of the terminal (default upon delivery of the CPU
board is 9600 Baud, 8 data bits, 1 stop bit, no parity).

2)

Cable connection from the CPU board to the terminal (refer to the Hardware User's Manual
for the pinning of the D-Sub connector and the required handshake signals).

3)

Power supply, + 5V, + 12V, -12V; must be present. See the Hardware User's Manual for
the power consumption of the CPU board.

If everything goes well, the header and prompt are displayed on the terminal and VMEPROM is
now ready to accept commands.

3.2 Command Line Syntax
All valid VMEPROM commands consist of the following:

? command < cr >
or
? command parameters < cr >
The underlined areas must be entered by the user. If more than one parameter will be entered,
they must be separated by a space or a comma.
For a detailed description of all functions of the command interpreter please refer to chapter 3 of
the VMEPROM User's Manual.

3.3 VMEPROM Commands
VMEPROM supports many commands. All of these commands are EPROM resident and are
available at any time. Most of these commands are common for all versions of VMEPROM. All
the common commands of VMEPROM are described in detail in the VMEPROM User's Manual.
Those commands which are specific for the hardware of the CPU board are described in the
following paragraphs of this manual. For a short description of one or all VMEPROM commands,
the HELP command can be used. Enter HELP for a description of all commands, or enter
HELP command < cr > for a description of a particular command.

3-1

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

This page was intentionally left blank

3-2

INTRODUCTION TO VMEPROM

SECTION 7

4. SPECIAL VMEPROM COMMANDS FOR CPU BOARD
The following commands are implemented on the CPU board in addition to those listed in the
VMEPROM User's Manual.

4. 1 ARB - Set the Arbiter of the CPU Board
Format:

ARB

The ARB command allows the user to set the arbitration mode of the CPU board for VMEbus.
This command is also used to select the Standard Access Mode for the VMEbus. Additionally,
the VMEbus interrupts can be enabled or disabled.
Example:
? ARB
Current arbiter mode: enab1ed, Mode = Prioritized ROUND ROBIN
Set arbiter mode? (Y,y/-) : Y
ROUND ROBIN mode? (Y,y/-) :Y
Prioritized ROUND ROBIN? (Y,y/-) : N
New arbiter mode = ROUND ROBIN
Set arbiter mode for VME-BUS:
STATUS:
SET:
SET:

ROR & RAT & RBClR & FAIR
Release on bus clear (RBClR)
Fair VME-BUS arbitration (FAIR)

(Y IN)
(Y IN)

?
?

Y
Y

Standard Access Mode (A24) for Slave Accesses currently disabled.
Enable A24 mode? (Y,y/-) : Y
A31-A24 = 80
Change interrupt mask? (Y, y/-) : Y
Enable(1) / Disable{O) VMEbus interrupts by level:

STATUS:

SET:

level:

Enter new interrupt mask:

?

4-1

7

6

5

4

3

2

1

1

1

111

1

1

1

1

1

1

0

1

1

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

4.2 CON FIG - Search VMEbus for Hardware
Format:

CONFIG

This command searches the VMEbus for'available hardware. It is useful if VMEPROM is started
and bit 0 of the lower rotary switch on the front panel is set to "1 ", so that VMEPROM does not
check the configuration by default.
In addition this command allows the user to install additional memory in the system .. Additional
memory can ONLY be installed with this command.
The fo!!ovving hardvvare is detected:
1.
2.
3.
4.

IS10-1/2
S10-1/2
ISCSI-1
Contiguous memory starting at the highest on-board memory address

The boards must be set to the default address for 32 bit systems. This setup is summarized for
all supported boards in the Appendix of this manual.
Additional memory must be contiguous to the on-board memory of the CPU board. This memory
is cleared by the config command to allow DRAM boards with parity to be used.
Please
remember that the installation of additional memory does not effect the RAM size of the running
task. However VMEPROM identifies this installed memory area and every time memory is
required (i.e. with CT or FM) it is taken from this area as long as there is enough free space.
I

The CONFIG command also installs Winchester disks in the system and initializes the disk
controller (if available). So if a SYSFAIL is active on the VMEbus (which can come for example
from the IS10-1/2 or ISCSI-1 controller during selftest) the command is suspended until the
SYSFAIL signal is no longer active.
Example:

?
CONFIG
UART FORCE 1510112 (U3) INSTALLED
ISCSI-1:
1
boards available
1510-1/2:
1
boards available
?

4-2

INTRODUCTION TO VMEPROM

SECTION 7

4.3 FGA - Change Boot Setup for Gate Array
Format:

FGA

Some registers of the gate array are definable by the user. The contents of this register is stored
in the on-board battery SRAM in a short form.
The boot software for the gate array will take these values after reset to initialize the gate array.
The FGA command may be used to enter an interactive mode for changing this boot table in the
battery SRAM.
The FGA command will show the actual value stored in the battery SRAM. To change any value,
a new one has to be entered in binary form. If only a  is entered, no change will be made.
To step backward a minus has to be entered. If a <. > or < ESC> is given, the FGA command
returns to the shell.
Example:

? FGA
> > > Setup for FGA-002 BOOTER

«<

REGISTER

FGA offset

value in SRAM

changed value

SPECIAL
CTL 01
CTL 02
CTL 05
CTL 12
CTL 14
CTL 15
CTL 16
MBX 00
MBX 01
MBX 02
MBX 03
MBX 04
MBX 05
MBX 06
MBX_07

$0420
$0238
$023C
$0264
$032C
$0354
$0358
$035C
$0000
$0004
$0008
$OOOC
$0010
$0014
$0018
$001C

%00011110
%00000100
%00000000
%00001100
%00000000
%00000000
%01001100
%00100000
%00000000
%00000000
%00000000
%00000000
%00000000
%00000000
%00000000
%00000000

%00011110
%00000100
%00000000
%00001100
%00000000
%00000000
%01000110
%00100000
%00001001
%00000000
%00000000

?

4-3

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

4.4 FLUSH - Set Buffered Write Mode
Format:

FLUSH
FLUSH?
FLUSH ON
FLUSH OFF

This command flushes all modified hashing buffers for disk write or enable or disable buffered
write mode for the local SCSI controller.
If no argument is entered, all modified hashing buffers are flushed. If an argument of "ON" or
"OFF" is given~ the buffered write mode will be enabled or disabled. By entering a question mark
as an argument, only a message will be displayed, whether the buffered write mode is enabled
or disabled.
Note:

This command only functions when an EAGLE Module which contains an SCSI
controller is installed.

Example:

? flush
All modified buffers are flushed
? flush ON
Buffered write is enabled

4-4

INTRODUCTION TO VMEPROM

SECTION 7

4.5 FMB - Force Message Broadcast
Format:

FMB < slotlist > , < FMB channel> , < message>
FMB [< FMB channel> 1

The FMB command allows sending a byte message to individual slots in the backplane, broadcast
to all the boards, and getting a pending message.
The first format is used to send a message. With this the first parameter is used to select the
slots to which a message should be sent. Each slot number can be separated with a '/' sign; a
'-' defines a range of slot numbers. Slot numbers can range from 0 to 21. A slot number of 0
sends the message to all slots. The second parameter defines which FMB channel should be
used. It can be '0' or ' 1'. The message is the byte to be deposited into the FMB channel (s).
The second format is used to get messages. If no parameter is given, one message of each FMB
channel is fetched and displayed. If a channel is specified only this channel is addressed and the
message will be displayed.
Example:
?FMB
FMB channel 0 is empty
FMB channel 1 is empty
? FMB 1-21 ,O,$EF
? FMB 1-21,1,%10100001
?FMB
FMB channel 0 = $EF
FMB channel 1 = $A 1
? FMB 1-21,1,$77
? FMB 1
FMB channel 1

= $77

? FMB 1/2/5/7-19/21,0,$1

?

4-5

FORCE COMPUTERS

SYS68K/CPU-40/4·1 USER'S MANUAL

4.6 FUNCTIONAL - Perform Functional Test
Format:

FUNCTIONAL

NOTE:

This command is not designed for the user, but instead for internal purposes by
FORCE COMPUTERS.

4-6

INTRODUCTION TO VMEPROM

SECTION 7

4.7 MEM - Set Data Bus Width of the VMEbus
Format:

MEM
MEM 16
MEM 32

This command can display or set the data bus width of the CPU board on the VMEbus.
If no argument is entered, the current data bus width is displayed. If an argument of '16' or '32'
is given, the data bus width is set to 16 or 32 bits respectively.
Example:

? MEM
Data bus width is set to 32 bits
? MEM 16

? MEM
Data bus width is set to 16 bits
? HEM 32
?

4-7

SVS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

4.8 PROG - Program FLASH EPROM
Format:

PROG [< source> [, < destination> [, < length> [, < width> ]]]]

This command is used to program FLASH EPROMs. All parameters may be specified on the
command line or may be entered interactively after the function has been invoked.
The first parameter
FLASH EPROM.

< source>

The second parameter

is the start address of the data which is to program into the

< destination> represents the base address of the FLASH EPROM.

The third parameter < length> specifies the length of the FLASH EPROM. If 0 is entered the
length and width is automatically calculated.
The fourth parameter < width> selects the data width of the FLASH EPROMs. Three values are
possible:
, 1 ':
, 2':
'4':

Byte width (8-bit)
Word width (1 6-bit)
Long width (32-bit)

Please note that the FLASH EPROM(s) must be completely programmed. Therefore programming
only parts of a FLASH EPROM is not possible.
Example:
? PROG $100000 $FFC80000 0
programming ..... .
FLASH EPROM successfully programmed

? PROG
Source base address
FLASH EPROM base address
Source length (0 for automatic select)
Width (1,2 or 4)
programming ..... .
FLASH EPROM successfully programmed

=
=

=
=

?

4-8

$40800000
$FFC80000
$20000
1

INTRODUCTION TO VMEPROM

SECTION 7

4.9 SELFTEST - Perform On-board Selftest
Format:

SELFTEST

This command performs a test of the on-board functions of the CPU board. It may only be run
if no other tasks are created. If there are any other tasks no selftest will be made and an error will
be reported. The self test tests the memory of the CPU board and all devices on the board.
The following tests are performed in this order:
1. 1/0 test

This function tests the access to and the interrupts from the DUSCC. If the DUSCC cannot
generate interrupts an error will be reported. This test also checks if reading from and writing to
the floppy disk controller and the SCSI controller proceeds as expected.'
2. Memory test on the memory of the current task.

The following procedures are performed:
1) Byte Test
2) Word Test
3) Long Word Test

All passes of the memory test perform pattern reading and writing as well as bit shift tests. If
an error occurs while writing to or reading from memory it will be reported.
3. Clock Test

If the CPU does not receive timer interrupts from the PlfT 68230 an error will be displayed. This
ensures that VMEPROM could initialize the PlfT 68230 properly and the interrupts from the PlfT
are working.

CAUTION: During this process, all memory is cleared.
Example:
? SELFTEST

VMEPROM Hardware Selftest
I/O test
Memory test
Clock test

. passed
. passed
passed

?

Only applicable when an EAGLE Module is installed which contains these devices.

4-9

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

This page intentionally left blank

4-10

INTRODUCTION TO VMEPROM

SECTION 7

5.

INSTALLING A NEW HARD DISK WITH THE ONBOARD SCSI CONTROLLER

NOTE:

The following is only possible if an EAGLE Module is installed which contains an
SCSI controller.

The hard disk must be set to 256 bytes per block. The FRMT command of VMEPROM may be
used to set all hard disk parameters, to format the Winchester and to divide the disk into logical
partitions. Before starting the FRMT command, the number of the last logical block of the
Winchester must be known. The number of physical blocks per track must be 32, the number
of bytes per sector must be 256. By using the following equation:
(# of Heads)

*

(# of Cylinders)

* (Blocks/Track)

= # of Last logical block

The number of Heads and the number of Cylinders may be calculated.
NOTE:

The maximum number of Heads is 16. The number of large and floppy partitions
are free definable by the user.

The following example aids in formatting a CDC 94211-5 Winchester.
? FRMT
68K PDOS Force Disk Format Utility 07-Sep-88
Possible Disk Controllers in this System are:
Controller #1 is not defined
Controller #2 is not defined
Controller #3 is a Force ISCSI-1
Controller #4 is a onboard CPU-40/41 SCSI
Drives that are currently defined in system are:
FO is controller #4 , drive select $82
F1 is controller #4 I drive seLect $83
WO is controller #4 , drive select $00

All not named drives are undefined
Select Menu: W,WO-W15=Winchi F,FO-F8=FloppYi Q=Quit
Select Drive: W
WO Main Menu: 1)Parm 2)BadT 3)Form 4)Veri 5)Part 6)Writ
P)Togl Q)Quit
Conmand: 1
WO Parameters Menu: A)lter, D)isplay, R)ead file, Q)uit
Conmand: A
# of Heads = 10
# of Cylinders = 1022
Physical Blocks per Track = 32
Physical Bytes per Block = 256
Shipping Cylinder = 0
Step rate = 0
Reduced write current cyl = 0
Write Precompensate cyl = 0
Current Winch Drive 0 Parameters:
# of Heads = 10
# of Cylinders = 1022
Physical Blocks per Track = 32
Physical Bytes per Block = 256
Shipping CyLinder = 0
Step rate = 0
Reduced write current cyl = 0
Write Precompensate cyL = 0'

5-1

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

(cont'd)

WO Parameters Menu: A)lter, D)isplay, R)ead file, Q)uit
Conmand: Q
WO Main Menu: l)Parm 2)BadT 3)Form 4)Veri 5)Part 6)Writ
P)Togl Q)Qui t
Conmand: 3
Sector Interleave = 0
Physical Tracks to FORMAT = 0,10219
Ready to FORMAT Winchester Drive 0 ? Y
Sector Interleave Table: 0,1,2,3,4,5,6,7,8,9,10,11,12,
13,14,15,16,17,18,19,20,21,22,
23,24,25,26,27,28,29,30,31
Issuing Format ,Drive Conmand.
FORMAT SUCCESSFUL !
WO Main Menu: 1)Parm 2)BadT 3)Form 4)Veri 5)Part 6)Writ
P)Togl Q)Qui t
Conmand: 5
Wo Partitions Menu: A)lter, D)isplay, R)ecalc, Q)uit
Conmand: A
# of Large partitions = 6
# of Floppy Partit'ions = 15
First track for PO OS Parts = 0
Last track for PO OS Parts = 10219
First PDOS disk # = 2
Current Winch Drive 0 Partitions:
# of Large partitions = 6
# of Floppy Partitions = 15
First track for PDOS Parts = 0
last track for PDOS Parts = 10219
First POOS disk # = 2
Total # of Logical Tracks = 10220
Disk #
2
3
4
5
6
7
9
10
11

12
13
14
15
16
17
18
19
20
21
22
23

Logical Trks Physical Trks
Base,Top
Base,Top
0,1502
0,1502
1503,3005
1503,3005
3006,4508
3006,4508
4509,6011
4509,6011
6012,7514
6012,7514
7515,9017
7515,9017
9018,9097
9018,9097
9098,9177
9098,9177
9178,9257
9178,9257
9258,9337
9258,9337
9338,9417
9338,9417
9418,9497
9418,9497
9498,9577
9498,9577
9578,9657
9578,9657
9658,9737
9658,9737
9738,9817
9738,9817
9818,9897
9818,9897
9898,9977
9898,9977
9978,10057
9978,10057
10058,10137 10058,10137
10138,10217 10138,10217

PDOS sectors
Total/{boot}
48064/47872
48064/47872
48064/47872
48064/47872
48064/47872
48064/47872
2528/2336
2528/2336
2528/2336
2528/2336
2528/2336
2528/2336
2528/2336
2528/2336
2528/2336
2528/2336
2528/2336
2528/2336
2528/2336
2528/2336
2528/2336

5-2

SECTION 7

INTRODUCTION TO VMEPROM

(cont'd)
WO Partitions Menu: A)lter, D)isplay, R)ecalc, Q)uit
Corrmand: Q
WO Main Menu: 1)Parm 2)BadT 3)Form 4)Veri 5)Part 6)Writ P)Togl
Q)Quit
Corrmand: 6
Write to Disk Y)es, N)o, F)ile : Y
Write to file (Y/N)?N
WO Main Menu: 1)Parm 2)BadT 3)Form 4)Veri 5)Part 6)Writ P)Togl
Q)Quit
Corrmand: Q
Exit to Select Drive. Update Param RAM (YIN) ? Y
System Parameter RAM Updated!!
Select Menu: W,WO-W15=Winch; F,FO-F8=Floppy; Q=Quit
Select Drive: Q
After formatting the disk, all logical partitions must be initialized using the INIT corrmand.
may be used to initialize the large logical partition number two.
? INlT

Enter Disk # :2
Directory Entries :1024
Number of sectors :47776
Disk Name :SYSTEM
Init: Disk # 2
Directory entries: 1024
Number of sectors: 47776
Disk name: SYSTEM
Initialize disk? Y
?

5-3

The example below

This page was intentionally left blank

APPENDIX TO THE
INTRODUCTION TO VMEPROM

This page vyas intentionally left blank

LIST OF APPENDICES
A.

VMEbus Board Setup

.......................................

A-1

A 1.
A2.
A3.
A4.
A5.

VMEbus Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYS68K/SIO-1/SIO-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYS68KIISIO-1/2..........................................
SYS68K/ISCSI-1 Disk Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Local FDC and SCSI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

A-1
A-1
A-3
A-4
A-5

B.

S-Record Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . ..

B-1

81 .
82.

S-Record Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S-Record Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

8-1
8-2

C.

System RAM Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C-1

D.

Task Control Block Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0-1

E.

Interrupt Vector Table of VMEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

E-1

F.

Benchmark Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F-1

G.

Special Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

G-1

H.

Generation of Applications in EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . .

H-1

H1.
General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
H 1 . 1 Replacing the User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

H-1
H-1

This page was intentionally left b'Jank

APPENDIX TO THE INTRODUCTION TO VMEPROM

SECTION 8

APPENDIX A
A. VMEbus Board Setup
This appendix summarizes the changes to be made to the default setup of additional VMEbus boards
so that they are VMEPROM compatible. Appendices A.2 through A.6 are available in EPROM, but
are not installed. All drivers may be installed with the INSTALL command. When INSTALL followed
by a question mark is entered, the following will appear: 1
? INSTALL?
THE FOLLOWING UARTS AND DISK DRIVER ARE ALREADY IN EPROM:
UART TYPE 1
UART TYPE 2
UART TYPE 3
UART TYPE 4
DISK DRIVER
DISK DRIVER

FORCE
FORCE
FORCE
FORCE
FORCE
FORCE

CPU-40/41/DUSCC
SI0-1/2
1510-1/2
UNIX MAIL
SCSI CPU-40/41
ISCSI-1

ADDR:
ADDR:
ADDR:
ADDR:
ADDR:
ADDR:

$FF004500
$ FF004800
$FF004COO
$FF005100
$FF005900
$FF007300

By typing in: INSTALL < file> , < address> < cr > , a specific driver may be loaded in the system.
The addressed file should be located in EPROM.

A 1. VMEbus Memory
In general, every FORCE memory board can be used together with VMEPROM. The base address
must be set correctly in order to use the board within the tasking memory of VMEPROM. The board
base addresses of any additional memory boards must be set to be contiguous to the on-board
memory. It is strongly recommended that only 32 bit memory boards are used because of speed
purposes.

A2. SYS68K/SIO-1/SIO-2
These two serial 1/0 boards are set to the base address $800000 by default. VMEPROM expects
the first S10-1 IS10-2 boards at $FC800000. This is in the standard VME address range (A24, 016,
08) with the address $800000. The address modifier decoder (AM-Decoder) of the S10-1 /2 boards
must be set to:
Standard Privileged Data Access
Standard Nonpriviledged Data Access

Please note that the printed UART and Disk Driver addresses are only examples. They may alternate according to software
versions.

A-1

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

Please refer to the SIO User's Manual for setup; If a second S10-1 /2 board will be used, the base
address must be set to FCB00200. The AM-decoder setup described above must again be used.
Please refer to the User's Manual of your SIO board for the address setup of the second SIO board.
Before using the driver for the SI0-1/2 board, the driver must be installed by using the INSTALL
command. The following must be entered:

? INSTALL U2,$FF004800
In order to install one of the ports of the SIO hoards in VMEPROM, the BP command can be used.
The S10-1 /2 boards use the driver type 2. To install the first port of a SIO board with a 9600 baud
rate, the following command line can be used:
? BP 4, 9600, 2, ·$FCBOOOOO

The port can then be used as port number 4. Please note that the hardware configuration must be
detected before a port can be installed. This can be done with the CONFIG command or by setting
a front panel switch on the CPU Board and pressing RESET. Please refer to the command
description in the VMEPROM User's Manual for a det~iled description of. the CONFIG and BP
commands. The base addresses of all ports of a SI0-1/2 board which must .be specified with the
BP command is as follows:
SIO port #

Address

1 (first SIO board)
2
3
4

$FCBOOOOO
$FCB00040
$FCB00080
$FCBOOOCO
$FCB00100
$FCB00140
$FCB00200
$FCB00240
$FCB00280
$FCB002CO
$FCB00300
$FCB00340

5
6
1 (second SIO board)
2

3
4

5
6

VMEPROM supports up to two serial I/O boards. These can be either the S10-1 /2 board, the ISIO1/2 board, or a mixture of both. Please note that the first board of every type must be set to the
first base address. In using one S10-1 board and one IS10-1 board, the base address of the boards
must to be set to:
S10-1
IS10-1

$FCBOOOOO
$FC960000

A-2

SECTION 8

APPENDIX TO THE INTRODUCTION TO VMEPROM

A3. SYS68K/ISIO-1/2
These serial I/O boards are set to the address $960000 in the standard VME address range by
default. VMEPROM awaits this board at this address (FC960000 for the CPU-40/41); no changes
need to be made to the default setup. An optional second board may be used. When used, the
address must be set to $980000. Read the SYS68K/ISI0-1/2 User's Manual for a description of
the base address setup. Before using the driver for the ISI0-1/2 board, the driver must be installed
by using the INSTALL command. The following must be entered:

? INSTALL U3,$FF004COO
In order to install one of the ports of an ISIO board in VMEPROM, the BP command can be used.
The ISI0-1/2 boards are driver type 3. In order to install the first port of an ISIO board with a 9600
baud rate, the following command line can be used:

? BP 4, 9600, 3, $FC968000
The port number is four. The hardware configuration must be detected before a port can be
installed. This is done with the CONFIG command, or by setting a front switch on the CPU board
and pressing RESET. Read the command description in the 'VMEPROM User's Manual for a
description of the CONFIG and BP commands. The base address of all ISI0-1/2 ports, specified by
the BP command, is as follows:
ISIO port #

Address

1 (first ISIO board)
2

$FC968000
$FC968020
$FC968040
$FC968060
$FC968080
$FC9680AO
$FC9680CO
$FC9680EO
$FC988000
$FC988020
$FC988040
$FC988060
$FC988080
$FC9880AO
$FC9880CO
$FC9880EO

3
4
5
6

7
8
1 (second ISIO board)
2

3
4
5
6
7

8

VMEPROM supports two serial I/O boards. These can be the SI0-1/2 or ISI0-1/2 board or mixture
of both. The first board of each type must be set to the first base address. When using one S10-1
and one IS10-1 board, the base address of the boards must be set to:
S10-1
IS10-1

$FCBOOOOO
$FC960000

A-3

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

A4. SYS68K/ISCSI·' Disk Controller
VMEPROM supports up to two floppy disk drives and three Winchester disk drives together with the
ISCSI-1 disk controller. The floppy drives must be jumpered to drive select 3 and 4 and can be
accessed as disk number 0 and 1 out of VMEPROM. The floppy drives are installed automatically
when a ISCSI-1 controller is detected by the CONFIG command or after pressing RESET when the
front panel switch of the CPU board is set to detect the hardware configuration. Usable floppy
drives must support 80 tracks/side, and must be double sided/double density. The step rate used
is 3 ms. The Winchester drives are not installed automatically. The VMEPROM FRMT command
must be used for defining the following factors:
..

The physical structure of the drive (Le. number of heads, number of cylinders, drive select
number, etc.)

•

The bad block of the Winchester drive

•

The partitions to be used

If this setup is done once for a particular drive, the data is stored in the first sector of the Winchester
and is loaded automatically when the disk controller is installed in VMEPROM. The driver for the
ISCSI-1 may be installed by using the INSTALL command. The following must be entered:

? INSTALL W,$FF007300
The default base address of the ISCSI-1 controller is $AOOOOO in the standard VME address range.
This is the address $FCAOOOOO for the CPU board and no changes have to be made to this setup.
The ISCSI-1 driver uses interrupts by default. This cannot be disabled. Please make sure that the
interrupt daisy chain is closed so that the controller can work properly.

A-4

APPENDIX TO THE INTRODUCTION TO VMEPROM

SECTION 8

AS. Local FOC and SCSI Controller
NOTE:

The following chapter only applies to those CPU boards which contain an
installed EAGLE Module with a floppy and/or SCSI controller.

VMEPROM supports up to two floppy disk drives and three Winchester disk drives together with the
local FDC and SCSI Controller. The floppy drives are installed automatically.
Here are the required floppy drive settings:
•

Drive select 2(0) or 3(1); VMEPROM access drive select 2 as disk 0 and drive select 3 as disk
1

•

Head Load is to be executed if Motor On and Drive Select is TRUE.

•

Pin 34 of the floppy interface should select the Disk Change signal. 2

•

Pin 2 of the floppy interface selects high or normal density.3 When this signal is "low level",
it designates normal density mode. VMEPROM only operates under normal density.

•

Pin 4 should be the Eject signal. 4

The step rate used is 3 ms.
The Winchester drives are not installed automatically.
The VMEPROM FRMl command must be used for defining the following factors:
•

The physical structure of the drive (Le. number of heads, number of cylinders, drive select
number, etc.)

•

The bad block of the Winchester drive

•

The partitions to be used

If this setup is done once for a particular drive, the data is stored in the first sector of the Winchester
and is loaded automatically when the disk controller is installed in VMEPROM. Upon viewing the
VMEPROM Banner, the driver for the local FDC and SCSI controller is already installed. For this
driver, memory is needed for hashing. The storage for the hashing buffers is allocated at the top
of memory.

2

Only if the floppy drive is able to generate or read this signal.

30lTO
40lTO

A-5

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

This page intentionally left blank

A-6

APPENDIX TO THE INTRODUCTION TO VMEPROM

SECTION 8

APPENDIX B
B. S-Record Formats
B 1. S-Record Types
Eight types of 5-records have been defined to accommodate the needs of the encoding
transportation and decoding functions. VMEPROM supports 50, 51, 52, 53, 57, 58 and 59 records
(57 and 58 on load only).
I

An 5-record format module may contain 5-records of the following types:
SO

The header record for each block of 5-records.

S1

A record containing code/data and the 2-byte address at which the code/data is to reside.

S2

A record containing code/data and the 3-byte address at which the code/data is to reside.

83

A record containing code/data and the 4-byte address at which the code/data is to reside.

85

A record containing the number of 51, 52 and 53 records transmitted in a particular block.
The count appears in the address field. There is no code/data field. Not supported by
VMEPROM.

87

A termination record for a block of 53 records. The address field may optionally contain the
4-byte address of the instruction to which control is to be passed. There is no code/data
field.

88

A termination record for a block of 52 records. The address field may optionally contain the

3-byte address of the instruction to which control is to be passed. There is no code/data
field.

S9

A termination record for a block of 51 records. The address field may optionally contain the
2-byte address of the instruction to which control is to be passed.

Only one termination record is used for each block of 5-records. 57 and 58 records are usually used
only when control is to be passed to a 3 or 4 byte address. Normally, only one header record is
used, although it is possible for multiple header records to occur.

8-1

SVS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

82. S-Record Example
S214020000000004440002014660000CB241F8044CB1
S214020010203C0000020E428110C1538066FA487AE4
S214020020001021DF0008487A001221DFOOOC4E750E
S21402003021FC425553200030600821FC41444452C2

xx.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx---0200XX------------------------------------14-------------------------------------------S2-----------------------------------------------

Check-sum
Data
24 bit Address
Byte Count
Record Type

S9030000FC
FC------------------------------------0000--------------------------------------03--------------------------------------------

89--------------------------------------------

B-2

Check-sum
Data
Byte Count
Record Type

APPENDIX TO THE INTRODUCTION TO VMEPROM

SECTION 8

APPENDIX C
C. System RAM Definitions
/* SYRAM:H -- DEFINITION OF SYRAM BLOCK OF MEMORY

05-Jan-88 Revised to correspond to PO OS 3.3
BRIAN C. COOPER, EYRING RESEARCH INSTITUTE, INC.
Copyright 1985-1988

*/

#define
#define
#define
#define
#define
#define
#define
#define
#define
#define

NT
NM
NP
NO
NC
NF
NU
IZ
MZ
TZ

64
«NT+3)&OxFC)
16
«NT+3)&OxFC)

#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define

NTB
NTM
NTP
NCB
NFS
NEV
NIE
NPS
P2P
MMZ
TMZ

NT
NM
NP
NC
NF
NO
(NO!2)
(NU+1)
lZ
MZ
TZ

#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define

IMK
NCP
MPZ
MBZ
NMB
FSS
TaB
TOM
TQE
TOS
TBZ
BPS
NRO

(OxFF»(8-P2P»
«1«P2P)+2)
2048
(MMZ/MPZ)
(MBZ/8)
38
2
(1QB+4)
(1QM+2)
(1QE+2)
(10S+2+4)
256
4

8

64
15
6

Ox4000000
64

struct SYRAM{
1*000*/ char * bios·
1*004*/ char *-mail~
/*008*/ unsigned in! rdkn;
/*OOA*/ unsigned int -rdks;
/*OOC*/ char * rdka· /*010*/ char bflg;'
1*011*/ char -dflg;
/*012*/ int -f681;
/*014*1 char sram·
1*018*/ int spare1;'
1*01A*/ int fcnt;
/*01C*/ long -tics;
/*020*/ unsigned char _smon;
1*021*/ unsigned char sday;
1*022*/ unsigned char -syrs[2];
/*024*1 unsigned char =shrs;
/*025*/ unsigned char _smin;
1*026*/ unsigned char _ssec[2];
/*028*/ char --patb[16];
/*038*1 char brkf[16];
/*048*/ char =f8bt[16J;
/*058*/ char _utyp[16J;
/*068*/ char _urat[16J;

*

/* m.lnber of tasks
/* number of task messages
/* number of task message pointers
/* number of delay events
/* number of active channel buffers
/* number of file slots
/* number of I/O UART ports
/* input buffer size (2 A p2p.
/* maxinun memory size
/* task message size

*/
*/

*/
*/
*/
*/
*/
*/
,*/
*/

/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*

input buffer wrap around mask
(# characters/port) + 2
memory page size
memory bitmap size
m,mber of map bytes
fi le slot size
TCB index
map index
event #1 / event #2
scheduled event
TASK entry size
bytes per sector
number of RAM disks

*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/

/*
/*
/*
1*
/*
1*
/*
/*
/*
/*
1*
/*
/*
/*
/*
/*
/*
/*
/*
1*
/*
1*
/*

address of bios rom
*mail array address
*ram disk #
*ram disk size
*ram disk address
basic present flag
directory flag
68000/68010 flag
run module B$SRAM
reserved for expansion
fine counter
32 bit counter
month
day
year
hours
minutes
seconds
input port allocation table
input break flags
port flag bits
port uart type
port rate table

*/
*/

C-1

*/
*/
*/
*/
*/
*/

*1
*/
*/

*1
*/
*/

*/

*1
*/
*/
*/

*/
*/

*/
*/

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

C. System RAM Definitions (cont'd)
1* 0-79 event table
1*078*1 char evtb(10J;
1* 80-95 output events
1*082*1 char -evto(2J;
1* 96-111 input events
1*084*1 char -evti(2J;
1* 112-127 system events
1*086*1 char -evts[2];
1* task 128 events
1*088*1 char -ev128[16];
/* events 112-115 timers
1*098*1 long -evtm[4];
1* clock adjust constant
I*OA8*1 long -bclk;
1* task list pointer
/*OAC*I char *_tltp;
1* user tcb ptr
I*OBO*I char *_utcb;
1* supervisor interrupt mask
I*OB4*1 int _suim;
1* user interrupt mask
I*OB6*1 int usim;
1* spawn task no. (** must be even **)
I*OB8*1 char =sptn;
1* user task time
I*OB9*1 char utim;
1* task priority (** must be even **)
I*OBA*I char =tpry;
1* current task number
I*OBB*I char tskn;
1* reserved
I*OBC*I char spare2;
1* task queue offset flag/no
/*OBO*/ cha'" _tqux;
1* task lock/reschedule flags
I*OBE*I C/;-If' t lck [2] ;
1* batch task #
I*OCO*I d~" -e122·
1* spooler task #
I*OC1*1 cr " -e123:
I*OC2*/ cn ' -e124:
/*OC3*1 ch",i' -e125;
/* system checksum
/*OC4*/ lo,.} =cksm;
1* pnet node #
I*OC8*/ int _pnod;
1* bus error vector
I*OCA*/ char bser[6];
1* illegal vector
1*000*1 char iler[6];
/*006*/ char ccnt[16];
1* control C count
1* window id's
I*OE6*/ char * wind;
1* window addresses
I*OEA*I char *-wadr;
I*OEE*/ char *-chin;
1* input stream
I*OF2*/ char *-chot;
1* output stream
/*OF6*/ char *-iord;
1* i/o redirect
/*OFA*I char feet;
1* file expand count
I*OFB*/ char =pidn;
1* processor ident byte
/* abs addr of K1$BEGN table
/*OFC*I long * begn;
1*100*/ int rwcl[14];
1* port row/col 1.. 15
/*11C*/ char *_opip[15];
1* output port pointers 1.. 15
1* uart base addresses 1 .. 15
1*158*1 char * uart[16];
/* memory map bias
1*198*1 long jnapb;
1*
1* the following change with different configurations:
1* configuration for VMEPROM is defined to:
NT = 64, NF = 64, MZ = $400000
1*
1*
1* NOTE: the offset on top of each line is calculated only for this
1*
configuration
1*
1*019C*1 char _maps[NMB];
1* system memory bitmap
/*119C*/ char _port[(NPS-1)*NCP];
1* character input buffers
1*157A*/ char iout[(NPS-1)*NCP];
1* character output buffers
/*1958*/ char rdtb[16];
1* redirect table
1*1968*/ int _tque[NTB+1];
1* task queue
1*19EA*/ char tlst[NTB*TBZ];
1* task list
1*10EA*1 char -tsev[NTB*32];
1* task schedule event table
1*25EA*1 long -tmtf[NTM];
1* to/from/INOEX.W
1*26EA*1 char -tmbf[TMZ*NTM];
1* task message buffers
1*36EA*/ char =tmsp[NTP*6];
1* task message pointers
1*374A*1 char _deiq[2+8+NIE*10];
1* delay event insert queue
1*3894*1 char devt[2+NEV*10];
1* delay events
1*3B16*/ int -bsct[32];
1* basic screen command table
1* channel buffer queue
1*3B56*1 int -xchi[NCB];
1* channel buffers
1*3B66*1 char -xchb[NCB*BPS];
1*4366*1 char -xfsl[NFS*FSS1;
/* file slots
1* level 2 lock (file prims, evnt 120)
1*4CE6*/ char -l2lk;
1*4CE7*1 char -l3lk;
1* level 3 lock (disk prims, evnt 121)
1* driver link list entry point
1*4CE8*1 long - drvl;
1* utility link list entry point
1*4CEC*1 long -utll;
/*4CFO*/ int =rdkl[NRD*4 + 1];
1* RAM disk list
);

C-2

*1
*/

*1
*/

*1
*1
*/

*1
*1
*/

*1
*1
*1
*1
*1
*1
*1
*1
*/

*1
*/

*1
*/

*1
*/

*/
*/

*1
*/

*1
*1
*/

*1
*/
*/
*/
*/

*1
*1
*1
*/
*/
*/

*1
*1
*/
*/
*/

*1
*/
*/

*1
*1
*1
*1
*1
*/
*/

*1
*1
*1
*1
*1
*/

*1
*/

APPENDIX TO THE INTRODUCTION TO VMEPROM

SECTION 8

APPENDIX D
D. Task Control Block Definitions
#define
#define
#define
#define
#define

10
10

MAXARG
MAXBP
MAXNAME
TMAX
ARGLEN

5

64
20

/*
/*
/*
/*
/*

max argument count of the cmd line
max 10 breakpoints
max 5 names in name buffer
Max number of tasks
maximum argument length

/* special system flags for VMEPROM
#define
#define
#define
#define
#define
#define
#define

SOMEREG
T OISP
T-SUB
T-ASUB
T-RANG
REG INI
REj>IR

Ox0001
Ox0002
Ox0004
Ox0008
Ox0010
Ox0020
Ox0040

*/

/*
/*
/*
/*
/*
/*
/*
/*

display only PC,A7,A6,A5
no register display during trace(TC>1)
trace over subroutine set
trace over subroutine active
trace over range set
no register initialization if set
output redirection into file and
console at the same time

/* the registers are stored in the following order:
#define VBR
0
#define SFC
1
2
#define OFC
4
#define CACR
5
#define PC
6
#define SR
#define USTACK 7
#define SSTACK 8
#define MSTACK 9
10
/* 10-17
#define DO
#define AO
18
/* 18-24
#define N_REGS

25

#define BYTE
#define WORD
#define LWORO

uns gned char
uns gned int
uns gned long

*/
*/
*/
*/
*/

*/
*/
*/
*/
*/
*/
*/
*/
*/

=

00-07
AO-A6

*/
*/

struct TCB{
/*000*/
/*100*/
/*150*/
/*170*/
/*1AC*/
/*1B4*/
/*3BO*/
/*3B4*/
/*3B8*/
/*3BC*/
/*3BO*/
/*3BE*/
/*3FE*/
/*402*/
/*406*/

char
char
char
char
char
char
char
char
long
char
char
long
long
long
long

ubuf[256];
-clb[80];
-mwb[32];
=mpb[60];
cob[8];
-swb[508];
*_tsp;
* kilo
_sfp;'
svf;
=iff;
_trp[16];
zdv;
=chk;
_trv;

/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*

256 byte user buffer
80 byte monitor command line buffer
32 byte monitor parameter buffer
monitor parameter buffer
character out buffer
system work buffer/task pdos stack
task stack pointer
kill self pointer
RESERVED FOR INTERNAL POOS USE
save flag -- 68881 support (x881)
RESERVED FOR INTERNAL POOS USE
user TRAP vectors
zero divide trap
CHCK instruction trap
TRAPV Instruction trap

0-1

*/
*/
*/

*/
*/
*/
*/
*/
*/
*/

*/
*/
*/
*/
*/

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

D. Task Control Block Definitions (cont'd)
/*40A*/
/*40E*/
/*416*/
/*41A*/
/*41E*/
/*422*/
/*426*/
/*42A*/
/*42E*/
/*430*/
/*432*/
/*434*/
/*436*/
/*437*/
/*438*/
/*439*1
1*43A*/
/*43C*1
/*43E*1
1*441*1
1*442*1
/*446*1
/*44A*1
/*44B*1
/*44C*/
/*440*/
1*44E*1
/*44F*1
1*450*/
/*451*/
/*452*/
/*453*/
/*454*/
/*455*1
/*456*1

long
long
long
char
char
char
char
char
int
int
int
int
BYTE
BYTE
char
char
char
char
char
BYTE
char
char
char
BYTE
char
char
char
char
char
BYTE
char
char
char
char
char

_trc;
_fpa[2];
*_fpe;
*_clp;
*_bum;
*_eum;
* ead*-imp~
- ,

_aci;
_aci2;
- len-,
- sfi ,_f 19;
_slv;
fec:
-_sparel;
csc [2]
=psc [2]
sds[3]
=sdk;
*- ext-,
*- err-,
- cmd-,
_tid;
_ecf;
- cnt-,
- mmf-,
_prt;
_spu;
- unt-,
_ulp;
_u2p;
_u4p;
_u8p;
_spare2[261;

/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
1*
/*
/*
/*
1*
1*
1*
/*
/*
/*
/*
1*
/*
/*
1*
/*
/*
1*
/*
/*

trace vector
floating point accumulator
fp error processor address
command line pointer
beginning of user memory
end user memory
entry address
internal memory pointer
assigned input file 10
assigned input file lOis
last error number
spool fi le id
task flags (bit 8=command line echo)
directory level
file exoansion count
reserved for future use
clear screen characters
position cursor characters
alternate system disks
system disk
XEXT address
XERR address
command line delimiter
task id
echo flag
output column counter
memory modified flag
input port #
spooling unit mask
output unit mask
unit 1 port #
unit 2 port #
unit 4 port #
unit 8 port #
reserved for system use

*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*1
*1
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/

/************************************************************************************************/
1*
VMEPROM variable area
*1
/***********************************************************************************~************/

/*470*1
/*4C2*1
/*514*/
1*566*1
/*56A*/
/*56C*1
/*594*/
/*59C*1
/*5AO*/
/*5A4*/
/*5A8*/
/*5AA*/
/*502*/
/*5E6*/

char
char
char
int
int
char
char
int
char
LWORD
int
LWORD
WORD
char

linebuf[82];
alinebuf[82];
cmdl ine[82];
allargs, gotargs;
argc;
*argv[MAXARG];
*odir, *idir;
iport,oport;
*ladr;
offset;
bpcnt;
bpadr[MAXBP];
bpinst[MAXBP];
bpcmd [MAXBP] [11] ;

/*
/*
/*
1*
1*
1*
1*
/*
/*
/*
/*
/*
/*
/*

command line buffer
alternate line buffer
alternate cmdline for XGNP
argc save and count for XGNP
argument counter
pointer to arguments of the cmd tine
1/0 redirection args from cmd line
I/O port assignments
holds pointer to line in_mwb
base memory pointer
num of defined breakpoints
breakpoint address
breakpoint instruction
breakpoint command

0-2

*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/

APPENDIX TO THE INTRODUCTION TO VMEPROM

SECTION 8

D. Task Control Block Definitions (cont'd)
1*654*1 WORD bpocc[MAXBP];
1*668*1 WORD bpcocc[MAXBP];
1*67C*1 LWORD bptadr;
1*680*1 WORD bptinst;
1*682*1 WORD bptocc;
1*684*1 WORD bptcocc;
1*686*1
1*691*1
1*692*1
1*6BA*1
1*782*1
1*784*1
1*78C*1
1*7FO*1
1*7F2*1
1*7F4*1
1*7F6*1
1*7F8*1
1*7FC*1
1*8C6*1
I*BE8*1
I*FOA*I

I*F6A*1
I*F6E*1
I*F72*1
I*F76*1
I*FB2*1
I*FB4*1
I*FB6*1

I*FCO*I
I*FC4*1
I*FC8*1
I*FC9*1
I*FCA*I

char
char
char
char
WORD
LWORD
LWORD
WORD
WORD
WORD
WORD
LWORD
char
char
char
LWORD
LWORD
LWORD
LWORD
BYTE
BYTE
BYTE
char
long
long
BYTE
BYTE
WORD

bptcmd[11l;
outflag;
namebn[MAXNAMEl [8];
namebd[MAXNAMEl [40];
errcnt;
times,timee;
pregs[N_REGSl;
tflag;
tcount;
tacount;
bpact;
savesp;
VMEMSP[202l;
VMESSP[802l;
VMEPUSP[802];
f_fpreg[3*8];
f_fpcr;
f_fpsri
f_fpiar;
f save[Ox3c];
cleos[2l;
cleol[2l;
u-prompt[10];
c_save:
exe_cnt;
nokill;
u_mask;
sysflg;

I*FCC*I LWORD t_range[2l;
I*FD4*1 LWORD ex_regs;
I*FD8*1 BYTE sparend[Ox1000-0xFD8]:
char _tbe[Ol:

1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*

# of times the breakpoint should be

skipped
# of times the breakpoint is already
skipped
temp. breakpoint address
temp. breakpoint instruction
# of times the temp. breakpoint should
be skipped
# of times the temp. breakpoint is
already skipped
temp. breakpoint command
output messages (yes=1,no=0)
Name buffer, name
Name buffer, data
error counter for test ••
startlend time
storage area of processor regs
trace active flag
trace count
active trace count
break point active flag
save VMEprom stack during GO/T etc
Master stack, handle wI care
supervisor stack, handle wI care
vmeprom internal user stack
floating point data regs
FPCR reg
FPSR reg
FPIAR reg
FPSAVE for null and idle
clear to end of screen parameter
clear to end of line parameters
user defined prompt sign
save Cache control register
execution count
kill task with no input port
unit mask for echo
system flags used by VMEPROM
bit 0: display registers short form
bit 1: trace without reg. display
bit 2: trace over subroutine
bit 3: trace over subroutine active
bit 4: trace over range
bit 5: no register initialization
bit 6: output redirection into file
and console at the same time
start/stop PC for trace over range
pointer to area for saved regs
make tcb size $1000 bytes
task beginning

}:

0-3

*1
*1
*1
*1
*1
*1
*1
*1
*/

*1
*1
*/

*1
*/
*/

*1
*1
*/
*/
*/
*/

*1
*/
*/
*/

*1
*1
*1
*/

*1
*1
*/

*1
*1
*1
*/
*/

*1
*1
*1
*1
*1
*/
*/

*1
*1
*1
*1
*1
*1

This page was intentionally left blank

APPENDIX TO THE INTRODUCTION TO VMEPROM

SECTION 8

APPENDIX E
E. Interrupt Vector Table of VMEPROM
Vector
Numberls

Vector
HEX

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
THROUGH
23
24
25
26
27
28
29
30
31
32
THROUGH
47
48
49
50
51
52
53
54
55
56
57
58
59
THROUGH
63
64
THROUGH
75
76
THROUGH

000
004
008
OOC
010
014
018
01C
020
024
028
02C
030
034
038
03C
040

83

Assignment
Reset: Initial Interrupt Stack Pointer
Reset: Initial Program Counter
Bus Error
Address Error
Illegal Instruction
Zero Divide
CHK, CHK2 Instruction
FTRAPcc, TRAPcc, TRAPV Instructions
Privilege Violation
Trace
VMEPROM System Calls
Coprocessor Instructions
(Unassigned, Reserved)
Not used by MC68040
Format Error
Uninitialized Interrupt

-,
t-~

05C
060
064
068
06C
070
074
078
07C
080

-.J

OBC
OCO
OC4
OC8
OCC
000
004
008
ODC
OEO
OE4
OE8
OEC

-.J

(Unassigned, Reserved)

Spurious Interrupt
AV1
AV2
AV3
AV4
AV5
AV6
AV7

-,
t-~ TRAP #0-15 Instruction Vectors

OFC
100
12C
130

FPCP Branch or Set on Unordered Condition
FPCP Inexact Result
FPCP Divide by Zero
FPCP Underflow
FPCP Operand Error
FPCP Overflow
FPCP Signaling NAN
FPCP Unimplemented Data Type
PMMU Configuration
PMMU Illegal Operation
PMMU Access Level Violation

-,
t-~ Unassigned, Reserved
-.J

-,
t-~ S10-1/2 Interrupt Vectors
.J

-,
t-~ ISI0-1/2 Interrupt Vectors

14C

-.J

E-1

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

confd .....

Vector
Numberls

Vector
HEX

84
THROUGH
118
119
120
THROUGH
191

150

-,

108
IDC
1 EO

~

192
193
194
195
196
197
198
199
200
THROUGH
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
THROUGH
254
255

Assignment

1-"

User Defined

Disk Interrupt Vector

-,

1-"

2FC
300
304
308
30C
310
314
318
31C
320

~

37C
380
384
388
38C
390
394
398
39C
3AO
3A4
3A8
3AC
3BO
3B4
3B8
3BC
3CO
3C4
3C8
3CC
300
304
30S
30C
3EO

~

3F4
3FC

~

User Defined

Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailbox

0
1
2
3
4
5
6
7

-,

1-"

Reserved

Timer
Reserved
Reserved
Reserved
FMB 1 Refused
FMBO Refused
FMB 1 Message
FMBO Message
ABORT
ACFAIL *
SYSFAIL *
OMA Error
OMA Normal
PARITY Error
Reserved
Reserved
LOCAL 1
LOCAL2
LOCAL3
LOCAL4
LOCAL5
LOCAL6
LOCAL7
LOCALS

-,

1-"

Reserved

Empty Interrupt

E-2

APPENDIX TO THE INTRODUCTION TO VMEPROM

SECTION 8

APPENDIX F
F. Benchmark Source Code
***************************************************************
** Module name: Assembler benchmarks
Version: 1.0
**
** date started: 20-Apr-87 M.S. last update: 23-Apr-87 M.S. **
**
Copyright (c) 1986/87 FORCE Computers GmbH Munich
**
***************************************************************

*

section
opt
xdef
xdef
xdef
xdef
xdef
xdef
xdef
xdef
xdef
xdef
xdef
xdef
xdef
xdef
xdef
page

o
alt,P=68020,P=68881
.benchex
.BEN1BEG,.BEN1END
.BEN2BEG,.BEN2END
.BEN3BEG,.BEN3END
.BEN4BEG,.BEN4END
.BEN5BEG,.BEN5END
.BEN6BEG,.BEN6END
.BEN7BEG,.BEN7END
.BEN8BEG,.BEN8END
.BEN9BEG,.BEN9END
.BEN10BEG,.BEN10END
.BEN11BEG,.BEN11END
.BEN12BEG,.BEN12END
.BEN13BEG,.BEN13END
.BEN14BEG,.BEN14END

*

* benchmark execution: benchex(address)

*

movem.l
move. 1
jsr
movem.l
rts

d1-a6,-(a7)
15*4(a7),aO
(aO)
(a7)+,d1-a6

*

* BENCH #1: DECREMENT LONG WORD IN MEMORY 10.000.000 TIMES

*
@020
@010

LEA.L
MOVE.L
SUBQ.L
BNE.S
RTS
DS.L

@010(PC),AO
#10000000, (AO)
#1, (AO)
@020
1

*

* BENCH #2: PSEUDO DMA 1K BYTES 50.000 TIMES

*
@001
@002

@010

MOVE.L
MOVE.W
LEA.L
MOVE.L
DBRA
SUBQ.L
BNE.S
RTS
NOP
NOP
PAGE

#50000,D2
#$FF,D3
@010(PC) ,AI
(A1),(A1)+
D3,@002
#1,D2
@001

DO 50000 TRANSFERS
EACH IS 1K BYTES
Al POINTS TO SOURCE AND DESTINATION

F-1

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

(cont'd)

*
*
*

BENCH #3: SUBSTRING CHARACTER SEARCH 100.000 TIMES TAKEN FROM EON 08/08/85

*

@002

MOVE.L
MOVE.L
MOVE.L
LEA.L
LEA.L
BSR.S
SUBQ.L
BNE.S
RTS

#100000,04
#15,00
#120,01
EON10AT(PC),A1
EON10AT1 (PC) , AO
EON1
#1,04
@002

*

****** BEGIN EON BENCH #1 *******
EON1
MOVEM.L 03/04/A2/A3,-(A7)
SUB.W
00,01
MOVE.W 01,02
SUBQ.W #2,00
MOVE.B (AO)+,03
@010
CMP.B
(A1)+,03
@012
OBEQ
01,@010
BNE.S
@090
MOVE.L AO,A2
MOVE.L A1,A3
MOVE.W 00,04
BMI.S
@030
@020
CMP.B
(A2)+,(A3)+
OBNE
04,@020
BNE.S
@012
@030
SUB.W
01,02
@032
MOVEM.L (A7)+,03/04/A2/A3
RTS
@090
MOVEQ.L #-1,02
BRA.S
@032
******* ENO EON BENCH #1 *******
EON10AT OC.B
'000000000000000000000000000000'
OC.B
'000000000000000000000000000000'
EON10ATl OC.B
'HERE IS A MATCHOOOOOOOOOOOOOOO'
PAGE

*
*
*

BENCH #4: BIT TEST/SET/RESET 100.000 TIMES TAKEN FROM EON 08/08/85

@010

MOVE.L
LEA.L
MOVEQ.L
MOVEQ.L
BSR.S
MOVEQ.L
MOVEQ.L
BSR.S
MOVEQ.L
MOVE.W
BSR.S
MOVEQ.L
MOVEQ.L
BSR.S

#100000,04
EON20AT(PC),AO
#1,00
#10,01
EON2
#1,00
#11,01
EON2
#1,00
#123,01
EON2
#2,00
#10,01
EON2

TEST

SET

F-2

SECTION 8

APPENDIX TO THE INTRODUCTION TO VMEPROM

(cont'd)
MOVEQ.L
MOVEQ.L
BSR.S
MOVEQ.L
MOVE.W
BSR.S
MOVEQ.L
MOVEQ.L
BSR.S
MOVEQ.L
MOVEQ.L
BSR.S
MOVEQ.L
MOVE.W
BSR.S
SUBQ.L
BNE.S
RTS

#1,00
#11,01
EON2
#1,00
#123,01
EON2
#3,00
#10,01
EON2
#1,00
#11,01
EON2
#1,00
#123,01
EON2
#1,04
@010

SUB.W
BEQ.S
SUBQ.W
BEQ.S

#2,00
@020
#1,00
@030

BFTST
OC.W
oC.W
SNE
RTS

(AO){Ol:l}
$E800
$0841
02

BFSET
OC.W
oC.W
SNE
RTS

(AO){Ol:l}
$EEOO
$0841
02

BFTST
OC.W
oC.W
SNE
RTS
EON20AT OC.L
PAGE

(AO){Ol:l}
$E800
$0841
02

*

EDN2

RESET

@010

*

@020

*

@030

*

0,0,0,0

*
* BENCH #5: BIT MATRIX TRANSPOSITION 100.000 TIMES
TAKEN FROM EON 08/08/85
*
*
@002

MOVE.L
LEA.L
MOVE.L
MOVEQ.L
BSR.S
SUBQ.L
BNE.S
RTS

#100000,04
EON30AT(PC),AO
#7,00
#0,01
EON3
#1,04
@002

F-3

FORCE COMPUTERS

SYS68K/CPU-40/41 USER'S MANUAL

(cont'd)

*

EDN3

@010

MOVEM.L
MOVE.L
MOVE.W
SUBQ.W
ADOQ.L
MOVE.L
ADO.L
MOVE.L

D1-D7,-(A7)
D1,D2
00,D7
#2,D7
#1,01
D1,03
DO,02
02,04

@020
BFEXTU (AO){03:1},D5
BFEXTU (AO){04:1},D6
BFINS
D5, (AO) {O 4 : 1}
D6,(AO){03:1}
BFINS
DO,D3
ADD.L
ADDQ.L #1,D4
03,04
CMP.L
@020
BNE.S
07,@010
DBRA
MOVEM.L (A7)+,D1-D7
RTS
%01001001
EDN3DAT DC.B
DC.B
%01011100
%10001110
DC.B
DC.B
%10100101
%00000001
DC.B
%01110010
DC.B
%10000000
OC.B
EVEN
PAGE

*

* BENCH #6: CACHE TEST - 128KB PROGRAM IS EXECUTED 1000 TIMES

*
*

CAUTION: THIS BENCHMARK NEEDS 128 KBYTE MEMORY

LEA.L
@010(PC),A2
MOVE.L #$203AOOOO,D1
OPCODE FOR MOVE.L ($O,PC),DO
LENGTH IS 128 KBYTE
MOVE.L #$20000/4,02
@004
MOVE.L D1,(A2)+
LOAD OPCODE TO MEMORY
SUBQ.L #1,D2
BNE.S
@004
; APPEND RTS
MOVE.W #$4E75,(A2)
* PROGRAM IS NOW LOADED -- START 1000 TIMES
MOVE.L #1000,03
@008
BSR.S
@010
SUBQ.L #1,D3
BNE.S
@008
RTS

*

@010

*
*

DC.L
PAGE

o

; PROGRAM WILL START HERE

BENCH #7: FLOATING POINT 1.000.000 ADDITIONS

*
@010

MOVE.L
FMOVE.L
FMOVE.L
FAOD.X
SUBQ.L
BNE.S
RTS

#1000000,05
#O,FPO
#1 / FP1
FPO,FP1
#1,05
@010

F-4

APPENDIX TO THE INTRODUCTION TO VMEPROM

SECTION 8

(cont'd)

** BENCH #8: FLOATING POINT 1.000.000 SINUS
*
MOVE.L #1000000,05
@010

FMOVE.L
FSIN.X
SUBQ.L
BNE.S
RTS
PAGE

#1,FP1
FP1
#1,05
@010

*
* BENCH #9: FLOATING POINT 1.000.000 MULTIPLICATIONS
*
MOVE.L #1000000,05
@010

**

FMOVE.L
FMOVE.L
FMUL.X
SUBQ.L
BNE.S
RTS
page

#l,FPO
#1,FP1
FPO,FP1
#1,05
@010

PO OS BENCHMARK #1: CONTEXT SWITCHES

*
@OOO

MOVE.L #100000,06
XSWP
SUBQ.L #1,06
BGT.S @OOO
RTS
PAGE

*
* POOS BENCHMARK #2: EVENT SET
*
*

@OOO

iCONTEXT SWITCH
iOONE?
iN

MOVEQ.L #32,01
MOVE.L #100000,06

iSELECT EVENT 32

XSEV
SUBQ.L #1,06
BGT.S @OOO
RTS
PAGE

iSET EVENT
iOONE?
iN

*
* POOS BENCHMARK #3: CHANGE TASK PRIORITY
*

*

@OOO

MOVEQ.L #-1,00
MOVEQ.L #64,01
MOVE.L #100000,06

iSELECT CURRENT TASK
iSET PRIORITY TO 64

XSTP
SUBQ.L #1,06
BGT.S @OOO
RTS

iSET PRIORITY
iOONE?
iN

F-5

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

(cont'd)

*

* PDOS BENCHMARK #4: SEND TASK MESSAGE
*
CLR.L
LEA.L
MOVE.L

*

@OOO

MES01

**
*

DO
MES01(PC),A1
#100000,D6

XSTM
XKTM
SUBQ.L #l,D6
BGT.S @OOO
RTS
DC.B
'BENCH #13',0
EVEN
PAGE

;SELECT TASK #0
;POINT TO MESSAGE
;SEND MESSAGE
;READ MESSAGE BACK
;DONE?
;N

PDOS BENCHMARK #5: READ TIME OF DAY

@OOO

MOVE.L #100000,D6
EQU
*
XRTP
SUBQ.L #l,D6
BGT.S @OOO
RTS
end

;DONE?

;N

F-6

APPENDIX TO THE INTRODUCTION TO VMEPROM

SECTION 8

APPENDIX G
G. Special Locations
The following table describes some special locations in the EPROM. These locations define the
default setup of the name of the startup file, user program location and RAM disk addresses. These
options can be selected by front panel switches.
The locations shown in the table can be changed by the user to adapt VMEPROM to every
environment. To make the necessary changes, please conduct the following steps:
1. Read the EPROMs with an EPROM programmer
2. Modify the code
3. Burn new EPROMs and keep the old ones in a safe location
4. Insert the new EPROMs in the CPU board and test the changes

G-1

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

The address of the following table is located at address $C relative to the begin of the EPROM):
Offset

Size

Default

$00

DS.B 22

'SY$STRT',O

$16

DS.W 1
DS.W 1
DS.L 1
DS.W 1
DS.W 1
DS.L 1
DS.W 1
DS.W 1
DS.L 1

$2E

DS.B 18

$40

DS.L
DS.L
DS.L
DS.L

$50
$54

Description
Name of the startup file. It has to be a O-terminated string.

8
2048
$40800000
8
2048
$40700000
8
256
$FFC10000
'SY$DSK',O

Disk no. of first RAM disk entry.
No. of 256 byte sectors.
Start address of first RAM disk.
Disk no. of second RAM disk entry.
No. of 256 byte sectors.
Start address of second RAM disk.
Disk no. of third RAM disk entry.
No. of 256 byte sectors.
Start address of third RAM disk.
Default name of initialized RAM disk. It must be a O-terminated string.

$40800000
$ ........
$FFC10000
$ ........

These four entries contain the address which is jumped to after kernel
intialization. The second entry contains the address of the BOOT
command. The fourth address is the start address of the VMEPROM
shell. These values depend on the VMEPROM version.

DS.B 4

'USER'

Disk drivers need this ident to make sure that below data is valid.

DS.B 1

$03

1
1
1
1

Bit 0:

If this bit is "0", no message occurs indicating that VMEPROM
is waiting until the hard disk is up to speed. This bit is only
considered if bit 1 is set to "1".

Bit 1:

If it is "0", VMEPROM will not wait until hard disk is up to
speed.

Bit
Bit
Bit
Bit
Bit
Bit

Reserved,
Reserved,
Reserved,
Reserved,
Reserved,
Reserved,

2:
3:
4:
5:
6:
7:

should
should
should
should
should
should

be
be
be
be
be
be

"0".
"0".
"0".
"0".
"0".
"0".

$55

DS.B 7

7 * $FF

Reserved

$5C

DS.W 1

16

This entry defines the number of hashing buffers. Valid entries are
numbers from 1 to 32. The hashing buffers are used to improve disk
access speed. Each buffer can hold 16 Kbytes of data.

Example on how to find this table:

? M $FFOOOOOC L

FFOOOOOC

.

FF008AOO

? MD $FF008AOO 60
FF008AOO: 53 59 24
FF008AI0: 00 00 00
FF008A20: 08 00 40
FF008A30: 24 44 53
FF008A40: 40 80 00
FF008A50: 55 53 45

53
00
70
4B
00
52

54
00
00
00
FF
03

52
00
00
00
00
FF

54
00
00
00
FO
FF

00
08
08
00
EA
FF

00
08
01
00
FF
FF

00
00
00
00
Cl
FF

00
40
FF
00
00
FF

?

G-2

00
80
Cl
00
00
FF

00
00
00
00
FF
00

00
00
00
00
00
10

00
00
53
00
88
00

00
08
59
00
A4
00

Sy$STRT .........
•••••••••• @•••••
.@.p •••••••••• Sy

$DSK ............
@•••••••• p ••••••

USER ......•.....

APPENDIX TO THE INTRODUCTION TO VMEPROM

SECTION 8

APPENDIX H
H. Generation of Applications in EPROM
H 1. General Information
In general, there are three ways to bind an application program in EPROMs to the VMEPROM kernel.
In all cases the application program is executed in user mode. The XSUP system call can be used
to switch to supervisor mode. The first way keeps the original EPROMs of VMEPROM. The
application can be put into an external RR-2 or RR-3 board on the VMEbus. In this case, the front
panel switches of the CPU board must be set so that the application program is started after
VMEPROM is booted. In this instance, the user stack is located at the top of the tasking memory
and the supervisor stack is located within the task control block. The supervisor stack has a size
of 500 bytes. No registers are predefined. If the reserved supervisor stack space is not sufficient,
the stack pointer has to be set to point to an appropriate address in RAM.

H 1 . 1 Replacing the User Interface
The following section describes how an application program can be put into EPROMs, replacing the
user interface of VMEPROM. This method gives nearly 180 Kbytes of EPROM space to the
application. Two general ways are possible:

8.

Removing All Setups:

If no setups are required, the application can be put into EPROMs at an address which is located in
address $8 relative to the EPROM start address (real address $FF000008). The code is started in
user mode, directly after the kernel has been initialized. The supervisor stack is located in the task
control block (size is about 500 bytes) and the user stack is located at the top of the task's memory.
Only bit 2 of SW2 of the rotary switches on the front panel is used. It defines the data bus width
on the VMEBus. All other bits are insignificant.

H-1

SYS68K/CPU-40/41 USER'S MANUAL

FORCE COMPUTERS

b. Keep All Setups:
To keep all setups the user program can be put into EPROM at an address which is located in
address $10 relative to the EPROM start address (real address $FFOOOO 10). In this case, the front
panel switches are defined as described in the "Introduction to VMEPROM". Both the user and the
supervisor stack are located in the task control block. The user stack has a reserved space of 800
bytes and the supervisor stack a space of 800 bytes. The program is started in user mode. The
following values are available on the stack:
Long word containing the begin address of the TCB
Long word containing the begin address of the system RAM (SYRAM).

4(A7)
8(A7)

A C-program at this address could look like this:
main (tcbp, syramp)
struct TCB *tcbp;
struct SYRAM *syramp;

{

H-2

USERS NOTES

This page was intentionally left blank

OPTIONS/APPLICATIONS/MODIFICATIONS

This page was intentionally left blank

Dear Customer,
·When using the SYS68K1CABLE MICRO-9 SET 2 (See Section "
INTRODUCTION; Chapter 4, ·Ordering Information" please adhere to the
following connection diagram.

c:

o

13
(1)
c:

c:
o

o

e

~

~
III

•

J

Q.,

0
~
~

~

c·

8

.,

©

•

0000

©

10

- 1-

This page was intentionally left blank
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date                     : 2015:10:12 11:39:36-08:00
Modify Date                     : 2015:10:12 11:31:11-07:00
Metadata Date                   : 2015:10:12 11:31:11-07:00
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:76289286-8b79-b548-a1b1-4ae389d858d5
Instance ID                     : uuid:5a368bac-80a1-3445-b4a4-f5f7773152be
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 756
EXIF Metadata provided by EXIF.tools

Navigation menu