GA34 0022 1__3_4953_Processor_Description_Mar77 1 3 4953 Processor Description Mar77
GA34-0022-1__3_4953_Processor_Description_Mar77 GA34-0022-1__3_4953_Processor_Description_Mar77
User Manual: GA34-0022-1__3_4953_Processor_Description_Mar77
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-------- ------'---- ---_ --.----- ,, Series/1 GA34-0022-1 File No. S1-01 IBM Series/1 Model 3 4953 Processor and Processor Features Description lfe: cello o II 11111111111111111111111111111111111111111111111 o [] 111111111111111111111111111111111111111111111111 o []) 1111111111111111111 o [(])I 0 II] ~ _111111111111111111111111111111111111111111111111 :u V -------- -- ------------_.- Series/1 GA34-0022-1 File No. 51-01 IBM Series/1 Model 3 4953 Processor and Processor Features Description c o o " Second Edition (March 1977) This is a major revision of, and obsoletes GA34-0022-O. Significant changes in this new edition include (1) rearrangement of chapters to provide a more logical flow of information and (2) removal of 4 chapters that are now included in other publications. Changes are periodically made to the information herein; any such changes will be reported in subsequent revisions or Technical Newsletters. Before using this publication in connection with the operation of IBM systems, have your IBM representative confirm editions that are applicable and current. Requests for copies of IBM publications should be made to your IBM representative or the IBM branch office serving your locality. A form for readers' comments is provided at the back of this publication. If the form has been removed, send your comments to IBM Corporati<1n, Systems Publications, Department 27T, P. O. Box 1328, Boca Raton, Florida 33432. Comments become the property of IBM. ©Copyright International Business Machines Corporation 1976, 1977 ii GA34-0022 Contents c Preface vii Summary of Publication vii Related Publications vii Chapter 1. Introduction I-I IBM 4953 Processor 1-3 Processor Options 1-3 Processor Description 1-3 Input/Output Units and Features 1-6 Communications Features 1-6 Sensor Input/Output Options 1-6 Packaging and Power Options 1-6 Other Options 1-6 [ ) Chapter 2. Processing Unit Description 2-1 Main Storage 2-1 Addressing Main Storage 2-3 Arithmetic and Logic Unit (ALU) 2-3 Numbering Representation 2-3 Registers 2-6 Per-system Registers 2-6 Per-level Registers 2-6 Indicator Bits 2-7 Even, Negative and Zero Result Indicators 2-7 Even, Carry, and Overflow Indicators - Condition Code for Input/Output Operations 2-8 Carry and Overflow Indicators - Add and Subtract Operations 2-8 Carry and Overflow Indicators - Shift Operations 2-8 Indicators - Compare Operations 2-8 Indicators - Multiple Word Operands 2-9 Testing Indicators with Conditional Branch and Jump Instructions 2-10 Supervisor State Bit 2-11 In-process Bit 2-11 Trace Bit 2-11 Summary Mask Bit 2-11 Program Execution 2-11 Instruction Formats 2-11 Effective Address Generation 2-13 Processor State Control 2-20 Initial Program Load (lPL) 2-22 Sequential Instruction Execution 2-23 Jumping and Branching 2-23 Level Switching and Interrupts 2-23 Stack Operations 2-23 Chapter 3. Interrupts and Level Switching 3-1 Introduction 3-1 Interrupt Scheme 3-1 Automatic Interrupt Branching 3-2 I/O Interrupts 3-3 Prepare I/O Device for Interrupt 3-3 Present and Accept I/O Interrupt 3-3 Class Interrupts 3-5 Priority of Class Interrupts 3-5 Present and Accept Class Interrupt 3-5 Summary of Class Interrupts 3-8 Recovery from Error Conditions 3-8 Program Check 3-8 Storage Parity Check 3-8 CPU Control Check 3-8 I/O Check 3-9 Soft Exception Trap 3-9 Processor Status Word 3-9 Program Controlled Level Switching 3-10 Selected Level Lower Than Current Level and In-process Flag On 3-11 Selected Level Equal to Current Level and In-process Flag On 3-11 Selected Level Higher Than Current Level and In-process Flag On 3-11 Selected Level Lower Than Current Level and In-process Flag Off 3-12 Selected Level Equal to Current Level and In-process Flag Off 3-12 Selected Level Higher Than Current Level and In-process Flag Off 3-12 Interrupt Masking Facilities 3-13 Summary Mask 3-13 Interrupt Level Mask Register 3-13 Device Mask (I-bit) 3-13 Chapter 4. Input/Output Operations 4-1 Operate I/O Instruction 4-1 Immediate Device Control Block (lDCB) 4-3 Device Control Block (DCB) 4-5 I/O Commands 4-6 DPC Operation 4-9 Cycle Steal 4-10 Start Operation 4-10 Start Cycle Steal Status Operation 4-12 Cycle-steal Device Options 4-13 Burst Mode 4-13 Chaining 4-1 3 Programmed Controlled Interrupt (PCI) 4-13 Suppress Exception (SE) 4-13 Cycle-steal Termination Conditions 4-15 I/O Condition Codes and Status Information 4-15 10 Instruction Condition Codes 4-19 Interrupt Condition Codes 4-19 I/O Status Information 4-20 Chapter 5. Console 5-1 Basic Console 5-2 Keys and Switches 5-2 Indicators 5-2 Programmer Console 5-3 Console Display 5-3 Indicators 5-4 Combination Keys/Indicators 5-5 Keys and Switches 5-8 Displaying Main Storage Locations 5-12 Storing Into Main Storage 5-12 Displaying Registers 5-13 Storing Into Registers 5-13 Contents iii Chapter 6. Instructions 6-1 Exception Conditions 6-1 Program Check Conditions 6-1 Soft Exception Trap Conditions 6-1 Instruction Termination or Suppression 6-2 Compatibility 6-2 Soft Exception Trap 6-2 No Operation 6-2 Program Check 6-2 Instruction Descriptions 6-3 Add Byte (AB) 6-3 Add Byte Immediate (ABO 6-3 Add Carry Register (ACY) 6-4 Add Double Word (AD) 6-5 Register/Storage Format 6-5 Storage/Storage Format 6-5 Add Word (AW) 6-6 Register/Register Format 6-6 Register/Storage Format 6-6 Storage to Register Long Format 6-7 Storage/Storage Format 6-7 Add Word With Carry (AWCY) 6-8 Add Word Immediate (AWl) 6-9 Register Immediate Long Format 6-9 Storage Immediate Format 6-9 Branch Unconditional (B) 6-10 Branch and Link (BAL) 6-10 Branch and Link Short (BALS) 6-11 Branch On Condition (BC) 6-12 Branch On Condition Code (BCC) 6-13 Branch On Not Condition (BNC) 6-14 Branch On Not Condition Code (BNCC) 6-15 Branch On Not Overflow (BNOV) 6-16 Branch On Overflow (BOV) 6-16 Branch Indexed Short (BXS) 6-17 Compare Byte (CB) 6-18 Register/Storage Format 6-18 Storage/Storage Format 6-18 Compare Byte Immediate (CBI) 6-19 Compare Double Word (CD) 6-20 Register/Storage Format 6-20 Storage/Storage Format 6-20 Compare Byte Field Equal and Decrement (CFED) 6-21 Compare Byte Field Equal and Increment (CFEN) 6-21 Compare Byte Field Not Equal and Decrement (CFNED) 6-22 Compare Byte Field Not Equal and Increment (CFNEN) 6-22 Complement Register (CMR) 6-23 Copy Current Level (CPCL) 6-23 Copy Console Data Buffer (CPCON) 6-24 Copy Interrupt Mask Register (CPIMR) 6-24 Copy In-process Flags (CPIPF) 6-25 Copy Level Block (CPLB) 6-26 Copy Level Status Register (CPLSR) 6-27 Copy Processor Status and Reset (CPPSR) 6-27 Compare Word (CW) 6-28 Register/Register Format 6-28 Register/Storage Format 6-28 Storage/Storage Format 6-28 Compare Word Immediate (CWI) 6-29 Register Immediate Long Format 6-29 Storage Immediate Format 6-29 Divide Byte (DB) 6-30 Divide Doubleword (DD) 6-31 Diagnose (DIAG) 6-32 Disable (DIS) 6-33 Divide Word (DW) 6-34 iv GA34-0022 Enable (EN) 6-35 Fill Byte Field and Decrement (FFD) 6-36 Fill Byte Field and Increment (FFN) 6-36 Operate I/O (10) 6-37 Interchange Registers (IR) 6-37 Jump Unconditional (J) 6-38 Jump and Link (JAL) 6-38 Jump On Condition (JC) 6-39 Jump On Count (JCT) 640 Jump On Not Condition (JNC) 641 Level Exit (LEX) 6-41 Load Multiple and Branch (LMB) 6-42 Multiply Byte (MB) 6-43 Multiply Doubleword (MD) 6-44 Move Address (MVA) 6-45 Storage Address to Register Format 6-45 Storage Immediate Format 6-45 Move Byte (MVB) 6-46 Register/Storage Format 646 Storage/Storage Format 6-46 Move Byte Immediate (MVBI) 6-47 Move Byte and Zero (MVBZ) 6-47 Move Doubleword (MVD) 648 Register/Storage Format 6-48 Storage/Storage Format 6-48 Move Doubleword and Zero (MVDZ) 649 Move Byte Field and Decrement (MVFD) 6-50 Move Byte Field and Increment (MVFN) 6-50 Move Word (MVW) 6-51 Register/Register Format 6-51 Register/Storage Format 6-51 Register to Storage Long Format 6-51 Storage to Register Long Format 6-52 Storage/Storage Format 6-52 Move Word Immediate (MVWI) 6-53 Storage to Register Format 6-53 Storage Immediate Format 6-53 Move Word Short (MVWS) 6-54 Register to Storage Format 6-54 Storage to Register Format 6-54 Move Word and Zero (MVWZ) 6-55 Multiply Word (MW) 6-56 No Operation (NOP) 6-57 And Word Immediate (NWI) 6-57 OR Byte (OB) 6-58 Register/Storage Format 6-58 Storage/Storage Format 6-58 OR Doubleword (OD) 6-59 Register/Storage Format 6-59 Storage/Storage Format 6-59 OR Word (OW) 6-60 Register/Register Format 6-60 Register/Storage Format 6-60 Storage to Register Long Format 6-61 Storage/Storage Format 6-61 OR Word Immediate (OWl) 6-62 Register Immediate Format 6-62 Storage Immediate Format 6-62 Pop Byte (PB) 6-63 Pop Doubleword (PD) 6-63 Push Byte (PSB) 6-64 Push Doubleword (PSD) 6-64 Push Word (PSW) 6-65 Pop Word (PW) 6-65 Reset Bits Byte (RBTB) 6-66 Register/Storage Format 6-66 Storage/Storage Format 6-66 c Reset Bits Double Word (RBTD) 6-67 Register/Storage Format 6-67 Storage/Storage Format 6-67 Reset Bits Word (RBTW) 6-68 Register/Register Format 6-68 Register/Storage Format 6-68 Storage to Register Long Format 6-69 StGr:lbe/Stcr~ge F~r!n~! c 6-69 Reset Bits Word Immediate (RBTWI) 6-70 Register Immediate Long Format 6-70 Storage Immediate Format 6-70 Subtract Byte (SB) 6-71 Subtract Carry Indicator (SCY) 6-71 Subtract Doubleword (SD) 6-72 Register/Storage Format 6-72 Storage/Storage Format 6-72 Set Console Data Lights (SECON) 6-73 Set Interrupt Mask Register (SEIMR) 6-73 Set Indicators (SEIND) 6-74 Set Level Block (SELB) 6-75 Scan Byte Field Equal and Decrement (SF ED) 6-76 Scan Byte Field Equal and Increment (SFEN) 6-76 Scan Byte Field Not Equal and Decrement (SFNED) 6-77 Scan Byte Field Not Equal and Increment (SFNEN) 6-77 Shift Left Circular (SLC) 6-78 Immediate Count Format 6-78 Count in Register Format 6-78 Shift Left Circular Double (SLCD) 6-79 Immediate Count Format 6-79 Count in Register Format 6-80 Shift Left Logical (SLL) 6-81 Immediate Count Format 6-81 Count in Register Format 6-81 Shift Left Logical Double (SLLD) 6-82 Immediate Count Format 6-82 Count in Register Format 6-82 Shift Left and Test (SLT) 6-83 Shift Left and Test Double (SLTD) 6-83 Shift Right Arithmetic (SRA) 6-84 Immediate Count Format 6-84 Count in Register Format 6-84 Shift Right Arithmetic Double (SRAD) 6-85 Immediate Count Format 6-85 Count in Register Format 6-85 Shift Right Logical (SRL) 6-86 Immediate Count Format 6-86 Count in Register Format 6-86 Shift Right Logical Double (SRLD) 6-87 Immediate Count Format 6-87 Count in Register Format 6-87 Store Multiple (STM) 6-88 Stop (STOP) 6-89 Supervisor Call (SYC) 6-89 Subtract Word (SW) 6-90 Register/Register Format 6-90 Register/Storage Format 6-90 Storage to Register Long Format 6-91 Storage/Storage Format 6-91 Subtract Word With Carry (SWCY) 6-92 Subtract Word Immediate (SWI) 6-93 Register Immediate Long Format 6-93 Storage Immediate Format 6-93 Test Bit (TBT) 6-94 Test Bit and Reset (TBTR) 6-94 Test Bit and Set (TBTS) 6-95 Test Bit and Invert (TBTY) 6-95 Test Word Immediate (TWI) 6-96 Register Immediate Long Format 6-96 Storage Immediate Format 6-96 !!!v'='!! R,=,g!<5!'='! (VR) f..-Q7 Exclusive OR Byte (XB) 6-97 Exclusive OR Doubleword (XD) 6-98 Exclusive OR Word (XW) 6-99 Register/Register Format 6-99 Register/Storage Format 6-99 Storage to Register Long Format 6-100 Exclusive OR Word Immediate (XWI) 6-100 Appendix A. Instruction Execution Times Appendix B. Instruction Formats B-1 Appendix C. Assembler Syntax C-l Coding Notes C-l Legend for Machine Instruction Operands Appendix o. A-I C-l Numbering Systems and Conversion Tables Binary and Hexadecimal Number Notations Binary Number Notation D-l Hexadecimal Number System 0-1 Hexadecimal - Decimal Conversion Tables Appendix E. Character Codes D-l D-l 0-2 E-l Appendix F. Carry and Overflow Indicators Signed Numbers F-l Unsigned Numbers F-2 Carry Indicator Setting F-4 Add Operation Examples F-4 Subtract Operation Examples F-4 Overflow Indicator Setting F-5 Examples F-6 F-l Appendix G. Reference Information G-l Condition Codes G-l I/O Instruction Condition Codes G-l Interrupt Condition Codes G-l General Registers G-2 Interrupt Status Byte (ISB) G-2 DPC Devices G-2 Cycle Steal Devices G-2 Level Status Register (LSR) G-2 Process Status Word (PSW) G-2 Index X-I Index of Instructions by Format Index of Instructions by Name X-IO X-13 Contents v ( ( vi GA34-0022 \. i Preface This publication describes the functional characteristics of the IBM 4953 Processor and the features associated with this processor. It assumes that the reader understands data processing terminology and is familiar with binary and hexadecimal numbering systems. The publication is intended primarily as a reference manual for experienced programmers who require machine code information to plan, correct, and modify programs written in the assembler language. Summary of Publication [ • Chapter 1. Introduction is an introduction to the system architecture. It contains a general description of the processor, storage, features, and a list of attachable I/O devices. • Chapter 2. Processing Unit Description contains a description of the processor hardware including registers and indicators. The section on indicators includes examples of indicator results when dealing with signed and unsigned numbers. Main storage data formats and addressing are presented in this chapter. A section titled "Program Execution" is included and covers: Basic instruction formats Effective address generation Processor state control Initial program load (lPL) Jumping and branching Level switching and interrupts Stack operations • Chapter 3. Interrupts and Level Switching describes the priority interrupt levels and the interrupt processing for (I) I/O devices, and (2) class interrupts. Related topics are: Program controlled level switching - Interrupt masking facilities - Recovery from error conditions • Chapter 4. Input/Output Operations describes the I/O commands and control words that are used to operate the I/O devices. Condition codes and status information relative to the I/O operation are also explained. Specific command and status-word bit structures are contained in the I/O device description books. • Chapter 5. Console describes the keys, switches, and indicators for the basic console and the optional programmer console. Typical manual operations such as storing into and displaying main storage are presented. • Chapter 6. Instructions describes the basic instruction set, including indicator settings and possible exception conditions. Individual instruction word formats are included and contain bit combinations for the operation code and function fields. The instructions are arranged in alphabetical sequence based on assembler mnemonics. • Appendixes: Instruction execution times Instruction formats Assembler instruction syntax Numbering systems and conversion tables Character codes Carry and overflow indicators Reference information Related Publications • IBM Series/1 System Summary, GA34-0035. • IBM Series/1 Installation Manual - Physical Planning, GA34·0029. • IBM Series/1 4962 Disk Storage and 4964 Diskette Unit Description, GA34-0024. • IBM Series/1 4973 Line Printer Description, GA34-0044. • IBM Series/1 4974 Printer Description, GA34-0025. • IBM Series/1 4979 Display Station Description, GA34·0026. • IBM Series/1 4982 Sensor Input/Output Unit Description, GA34-0027. • IBM Series/1 Communications Features Description, GA34-0028. • IBM Series/1 Attachment Features Description, GA34-0031. • IBM Series/1 Battery Backup Unit Description, GA34-0032. • IBM Series/1 User's Attachment Manual, GA34-0033. Preface vii ( viii GA34-0022 Chapter 1. Introduction Four models of the 4953 Processor are available. • Model A 1/2 rack width unit 16K bytes main storage Additional storage in 16K byte increments 64K bytes maximum • Model B Full rack width unit - 16K bytes main storage - Additional storage in 16K byte increments - 64 K bytes maximum • Model C 1/2 rack width unit 32K bytes main storage Additional storage in 16/32K byte increments 64K byte maximum • Model D Full rack width unit 32K bytes main storage Additional storage in 16/32K byte increments 64K bytes maximum The IBM 4953 Processor is a compact, general purpose computer and has the following general characteristics: • Four priority interrupt levels - independent registers and status indicators for each level. Automatic and program controlled level switching. • Main storage - read or write time is 600 nanoseconds maximum (minimum 800 nanoseconds required between two storage access cycles). Odd parity by byte is maintained throughout storage. • TTL (transistor-transistor logic) processor technology • Microprogram control- micro cycle time: 200 nanoseconds. • Instruction set that includes: stacking and linking facilities, multiply and divide, variable field-length byte operations, and a variety of arithmetic and branching instructions. • Supervisor and problem states. • Packaged in a 19-inch rack mountable unit - full width or half width. • Basic console standard in processor unit. Programmer console optional. • Channel capability Asynchronous, multidropped channel - 256 I/O (input/output) devices can be addressed - Direct program control and cycle steal operations Maximum burst data rate is 666K words per second (1.332 megabytes if transmitted in pairs). When multiple cycle stealing devices are interleaved, the aggregate data rate is also 666K words. The processor unit contains power and space for additional features and storage. The IBM 4959 Input/Output Expansion Unit is also available for additional features. The processor is described in the following sections of this chapter. Introduction 1-1 IBM 4953 Processor Processor f ,. Channel Repower Channel Storage (64K maximum) Console , I/O Attachment I/O Device I/O Device I/O Attachment I/O Attachment I/O Device Figure 1-1. Block diagram of IBM 4953 Processor and an IBM 4959 I/O Expansion Unit ( 1-2 GA34-0022 IBM 4953 Processor Processor Options • Storage Addition - 16,384 bytes Provides additional storage in 16K byte increments for all models 64K byies maximum • Storage Addition - 32,768 bytes Provides additional storage in 32K byte increments for models C and D 64K bytes maximum • Programmer Console Processor Description The basic IBM 4953 Processor includes the processor, 16K bytes of storage for models A and B (32K bytes of storage for models C and D), and a basic console. These items are packaged in a unit, called the processor unit. Figure 1-1 shows a block diagram of an IBM 4953 Processor and an IBM 4959 Input/Output Expansion Unit. The processor is microprogram controlled, utilizing a 200 nanosecond microcycle. Circuit technology is TTL. Four priority interrupt levels are implemented in the processor. Each level has an independent set of machine registers. Level switching can occur in two ways: (1) by program control, or (2) automatically upon acceptance of an I/O interrupt request. The interrupt mechanism provides 256 unique entry points for I/O devices. The processor instruction set contains a variety of instruction types. These include: shift, register to register, register immediate, register to (or from) storage, bit manipulation, multiple register to storage, variable byte field, and storage to storage. Supervisor and problem states are implemented, with appropriate privileged instructions for the supervisor. The basic console is intended for dedicated systems that are used in a basically unattended environment. Only minimal controls are provided. A programmer console can be added as a feature; this console provides a variety of indicators and controls for operator-oriented systems. Basic storage supplied is 16K bytes for models A and B; 32K bytes for models C and D. Models A and B can add additional storage in 16K byte increments up to 64K bytes maximum. Models C and D can add additional storage in 16K and/or 32K byte increments up to 64K bytes maximum. The maximum read/write access time for main storage is 600 nanosec()nd~ However; the minimum duration of time between successive storage cycles is 800 nanoseconds. I/O devices are attached to the processor through the processor I/O channel. The channel directs the flow of information between the I/O devices, the processor, and main storage. The channel accommodates a maximum of 256 addressable devices. The channel supports: • Direct program control operations. Each Operate I/O instruction transfers a byte or word of data between main storage and the device. The operation may' or may not terminate in an interrupt. • Cycle steal operations. Each Operate I/O instruction initiates multiple data transfers between main storage and the device (65,535 bytes maximum). Cycle steal operations are overlapped with processing operations and always terminate in an interrupt. • Interrupt servicing. Interrupt requests from the devices, along with cycle steal requests, are presented and polled on the interface concurrently with data transfers. The processor is packaged in a standard 48.3 cm (19 inch) rack-mountable unit, called the processor unit. All processor units contain an integral power supply, fans, and the basic console. Refer to the Series/l Installation Manual-Physical Planning, GA34-0029, for environmental characteristics. Four processor models are available. Figure 1-2 shows the IBM 4953 Processor Model A, Figure 1-3 shows the IBW 4953 Processor Model B, Figure 1-4 shows the IBM 4953 Processor Model C, and Figure 1-5 shows the IBM 4953 Processor Model D. Introduction 1-3 IBM 4953 Processor Model A This model occupies one-half the width of the standard rack and has 16K bytes of storage. It has the capacity for storage cards and/or I/O feature cards in any combination up to 4 additional cards. See Figure 1-2. IBM 4953 Processor Model B Note. Additional storage may be added in 16K byte Note. Additional storage may be added in 16K byte jncrements up to 64K bytes maximum. increments up to 64K bytes maximum. This model occupies the full width of the standard rack and has 16K bytes of storage. It has the capacity for storage cards and/or I/O feature cards in any combination up to 13 additional cards. See Figure 1-3. ( ) . _ 1111111111111111111111" I" I"" III/ 1/ 1111"""1/11111 III111I1IIIII111111111111 ABCDE FGHJK I/O~rds ~\'-Processor ~Storage 16KB LMNPQ ~ -----t t t Any I/O or 16KB storage card Processor Storage 16KB If the A position is not used for the Channel Repower card, the following feature cards may be plugged in this position: Any I/O or 16KB storage card • • Repower card or any I/O card Hgure 1-2. IBM 4953 Processor Model Awith a Programmer Console • • • • Teletypewriter Adapter Feature using TTL voltage levels Teletypewriter Adapter Feature using isolated current loop where user supplies external ± 12V power Timer Feature Customer Direct Program Control Adapter Feature 4982 Sensor Input/Output Unit Attachment Feature Integrated Digital Input/Output Non-Isolated Feature Hgure 1-3. IBM 4953 Processor Model B with a Programmer Console 1-4 GA34-0022 ( j c IBM 4953 Processor Model C IBM 4953 Processor Model D This model occupies one-half the width of the standard rack and has 32K bytes of storage. It has the capacity for storage cards and/or I/O feature cards in any combination up to 4 additional cards. See Figure 14. This model occupies the full width of the standard rack and has 32K bytes of storage. It has the capacity for storage cards and/or I/O feature cards in any combination up to 13 additional cards. See Figure 1-5. Note. Additional storage may be added in 16K/32K byte Note. Additional storage may be added in 16K/32K byte increments up to 64K bytes maximum. increments up to 64K bytes maximum. 111111111111111111111111111" 11111111111111111111111111 I1I1II1111111111111111111 ABCDE FGHJK storage card LMNPQ storage card If the A position is not used for the Channel Repower card, the following feature cards may be plugged in this position: Repower card or any I/O card storage card Figure 1-4. IBM 4953 Processor Model C with a Programmer Console • • • • • • Teletypewriter Adapter Feature using TTL voltage levels Teletypewriter Adapter Feature using isolated current loop where user supplies external ± 12V power Timer feature Customer Direct Program Control Adapter Feature 4982 Sensor Input/Output Unit Attachment Feature Integrated Digital Input/Output Non-Isolated Feature Figure 1-5. IBM 4953 Processor Model D with a Programmer Console Introduction 1-5 Input/Output Units and Features • IBM 4962 Disk Storage Unit (4 models) - Requires 4962 Disk Storage Unit Attachment Features • IBM 4964 Diskette Unit - Requires 4964 Diskette Unit Attachment Feature • IBM 4979 Display Station - Requires 4979 Display Station Attachment Feature • IBM 4973 Line Printer (2 models) - Requires 4973 Printer Attachment Feature • IBM 4974 Printer - Requires 4974 Printer Attachment Feature • Timers Feature (2 timers) • Teletypewriter Adapter Feature • Customer Direct Program Control Adapter Feature The feature cards for attaching the I/O units can be housed in either the processor unit or the I/O expansion unit. Information about these units and features can be found in separate publications. The order numbers for these publications are listed in the preface of this manual. Communications Features • Asynchronous Communications Single Line Control • Binary Synchronous Communications Single Line Control • Binary Synchronous Communications Single Line Control/High Speed • Synchronous Data Link Control Single Line Control • Asynchronous Communications 8 Line Control • Asynchronous Communications 4 Line Adapter • Binary Synchronous Communications 8 Line Control • Binary Synchronous Communications 4 Line Adapter • Communications Power Feature • Communications Indicator Panel The integrated digital input/output non-isolated feature provides digital sensor I/O and simple attachment for nonIBM equipment. This feature card can be housed in either the processor unit or the I/O expansion unit. The 4982 sensor input/output attachment unit feature card is housed in either the processor unit or the I/O expansion unit. Refer to the publication IBM Series/1, 4982 Sensor Input/Output Unit Description, GA34-0027 , for a description of the 4982 and associated features. ( Packaging and Power Options • • • • IBM IBM IBM IBM 4959 4999 4997 4997 Input/Output Expansion Unit Battery Backup Unit Rack Enclosure (I-metre) - 2 models Rack Enclosure (l.8-metre) - 2 models The IBM 4959 Input/Output Expansion Unit is available for adding I/O feature cards beyond the capacity of the processor unit. The capacity of the I/O expansion unit is either (1) fourteen I/O cards, or (2) thirteen I/O cards plus a channel repower card. A channel repower card is required to power each additional I/O expansion unit. The IBM 4999 Battery Backup Unit permits the processor unit (excluding external devices) to operate from a usersupplied battery when a loss or dip in line power occurs. Other Options Additional options such as communications cables, customer access panel, and a channel socket adapter are also available. For a list and description of system units and features, refer to the IBM Series/1 System Summary, GA34-0035. Refer to the publication IBM Series/1 Communications Features Description, GA34-0028, for a description of these features. Sensor Input/Output Options • Integrated Digital Input/Output Non-Isolated Feature • IBM 4982 Sensor Input/Output Unit - 4982 Sensor Input/Output Unit Attachment Feature • Features for the 4982 Sensor I/O Unit Digital Input/Process Interrupt Non-Isolated Digital Input/Process Interrupt Isolated Digital Output Non-Isolated Analog Input Control Amplifier Multirange Analog Input Multiplexer - Reed Relay Analog Input Multiplexer - Solid State Analog Output ( 1-6 GA34-0022 Chapter 2. Processing Unit Description Figure 2-1 shows the general data flow for the IBM 4953 Processor. The major functional units shown in the data flow are discussed in the following sections. Main Storage Main storage holds data and instructions for applications to be processed on the system. The data and instructions are stored in units of information called a byte. Each byte consists of eight binary data bits. Associated with each byte is a parity bit. Odd parity by byte is maintained throughout storage ~ even parity causes a machine check error. Formats shown in this manual exclude the parity bit(s) because they are not a part of the data flow manipulated by the instructions. The bits within a byte are numbered consecutively, left to right, 0 through 7. When a format consists of multiple bytes, the numbering scheme is continued~ for example, the bits in the second byte would be numbered 8 through 15. Leftmost bits are sometimes referred to as high-order bits and rightmost bits as low-order bits. Bytes can be handled separately or grouped together. A word is a group of two consecutive bytes, beginning on an even address boundary, and is the basic building block of instructions. A doubleword is a group of four consecutive bytes beginning on an even address boundary. o 7 Word I 10 0 o 0 000 010 o 0 0 0 0 1 o 7 15 0 8 Doubleword 10 0 o 000 o 0 010 7 8 o 0 0 0 0 0 010 15 16 0 o 0 000 010 2324 0 000 1 0 01 31 Processing Unit Description 2-1 Processor Bus Local. Storage Bus Reg l Level 0 IAR LSR Registers 0-7 Display A Reg SDR Levell IAR LSR Registers 0-7 I Level 2 IAR LSR Registers 0-7 I I I I Level 3 IAR LSR Registers 0-7 ,------, I I I I I I Console L--r--_-.1 SAR ALU .- Channel Address CIAR Main Storage PSW Channel Data Mask Reg SARBU Bus Reg Status Reg Console Data Buffer OP Reg Address Compare Bus ALU - Arithmetic and logic unit IAR - Instruction address register LSR - Level status register Mask - Interrupt level mask register OP - Operation register PSW - Processor status word SAR - Storage address register SAR BU - Storage address back-up register SDR - Storage data register Figure 2-1. Data flow for the IBM 4953 Processor ( 2-2 GA34-0022 (~ Addressing Main Storage Arithmetic and Logic Unit (ALU) Each byte location in main storage is directly addressable. Byte locations in storage are numbered consecutively, starting with location zero; each number is considered the address of the corresponding byte. Storage addresses are 16-bit unsigned binary numbers. This permits a direct addressing range of 65,536 bytes: The arithmetic and logic unit (ALU) contains the hardware circuits that perform: addition; subtraction; and logical operations such as AND, OR, and exclusive OR. The ALU performs address arithmetic as well as the operations required to process the instruction operands. Operands may be regarded as signed or unsigned by the programmer. However, the ALU does not distinguish between them. Numbering representation is discussed in a subsequent section of this chapter. For many instructions, indicators are set to reflect the result of the ALU operation. The indicators are discussed in a subsequent section of this chapter. Address Range 16-bit binary address 0000 0000 0000 0000 to 1111111111111111 Hexadecimal 0000 to FFFF Decimal o to 65,535 Note. Addresses that overflow or underflow the addressing range address wrap modulo 65,536. Numbering Representation Instruction and Operand Address Boundaries As previously stated, all storage addressing is defined by byte location. Instructions can refer to bits, bytes, byte strings, words, or doublewords as data operands. All word and doubleword operand addresses must be on even byte boundaries. All word and doubleword operand addresses point to the most significant (leftmost) byte in the operand. Bit addresses are specified by a byte address and a bit displacement from the most significant bit of the byte. To provide maximum addressing range, some instructions refer to a word displacement that is added to the contents of a register. In these cases, the operand is a word and the register must contain an even byte address for valid results. Effective address generation is described in a subsequent section of this chapter. All instructions must be on an even byte boundary. This implies that the effective address for all branch type instructions must be on an even byte boundary to be valid. If any of the aforementioned rules are violated, a program check interrupt occurs with specification check set in the processor status word (PSW). The instruction is terminated. Operands may be signed or unsigned depending on how they are used by the programmer. An unsigned number is a binary integer in which all bits contribute to the magnitude. A storage address is an example of an unsigned number. A signed number is one where the high-order bit is used to indicate the sign, and the remaining bits define the magnitude. Signed positive numbers are represented in true binary notation with the sign bit (high-order bit) set to zero. Signed negative numbers are represented in two's complement notation with the sign bit (high-order bit) set to one. The two's complement of a number is obtained by inverting each bit of the number and adding a one to the low-order bit position. Two's complement notation does not include a negative zero. The maximum positive number consists of an all-one integer field with a sign bit of zero; whereas, the maximum negative number (the negative number with the greatest absolute value) consists of an all-zero integer field with a one-bit for the sign. The following examples show: (1) an unsigned 16-bit number, (2) a signed 16-bit positive number, and (3) a signed 16-bit negative number. Processing Unit Description 2-3 Example of an unsigned 16-bit number: 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 o 15 Binary number Bit position Decimal value 65535 (The largest unsigned number Hexadecimal value FFFF representable in 16 bits.) Example of a signed 16-bit positive number: 10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 15 o L Binary number Bit position sign (+) Decimal value +32767 (The largest positive signed Hexadecimal value 7FFF number representable in 16 bits.) When the number is positive, all bits to the 1eft of the most significant bit of the number, including the sign bit, are zero: 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 o L 15 Binary number Bit position sign (+) Decimal value +1 Hexadecimal value 0001 Example of C:l signed 16-bit negative number: 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 o L 15 Binary number Bit position sign (-) Decimal value -32768 (The largest negative signed Hexadecimal value 8000 number representable in 16 bits.) Note. This form of representation yields a negative range of one more than the positive range. 2-4 GA34-0022 c When the number is negative, all bits to the left of the most significant bit of the number, induding the sign bit, are set to one: 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 o L 01 15 Binary number Bit position sign (-) Decimal value -2 Hexadecimal value FFFE When a signed-number operand must be extended with high-order bits, the expansion is achieved by prefixing a field in which each bit is set equal to the high-order bit of the operand. Example of an 8-bit field extended to a 16-bit field: 11 1 1 1 1 1 0 o 7 L c 11 1 1 1 1 1 1 1 1 1 Binary number Bit position Sign (-) Decimal value -3 Hexadecimal value FD 1 o L 11 1 1 1 0 11 15 Binary number Bit position Sign (-) Decimal value -3 Hexadecimal value FFFD I t must be emphasized that when performing the add and subtract operations, the machine does not regard the number as either signed or unsigned, but performs the designated operation on the values presented. Whether a given add or subtract operation is to be regarded as a signed operation or an unsigned operation is determined by the programmer's view of the values being presented as operands. The carry indicator and the overflow indicator of the LSR are changed on various operations to reflect the result of that operation. This allows the programmer to make result tests for the number representation involved. The carry and overflow indicator settings are explained in a subsequent section. c Processing Unit Description 2-5 Registers Registers in the processor are provided in two categories: 1. 2. Per-system register (the register is provided only once and is used by all priority interrupt levels) Per-level register (the register is duplicated for each priority interrupt level) Information that must be saved when a level is preempted is retained in registers supplied for a specific level. Information that pertains only to the current process is kept in registers common to all levels. The registers in each category are listed in this section. Descriptions for each of the registers appear in subsequent sections. Only registers accessible to the program or the operator (via console operations) are discussed. Registers supplied on a per-system basis: • • • • • Console data buffer Current-instruction address register (CJAR) Mask register (interrupt level) Processor status word (PSW) Storage address register (SAR) Registers supplied on a per-level basis: • General registers (8 per level) • Instruction address register (JAR) • Level status register (LSR) Note. For a specific level, the contents of the JAR, LSR, and the general registers are known as a level status block (LSB). The LSB is a 22 byte entity used by hardware and software for task control and task switching. Per-system Registers Console Data Buffer The console data buffer is a 16-bit register associated with the programmer console feature. Details of how the buffer is used are explained in the programmer console section of Chapter 5. The contents of the console data buffer can be loaded into a specified general register by using the Copy Console Data Buffer (CPCON) instruction (see Chapter 6). A one bit enables interrupts on a level, while a zero bit disables interrupts. For example if bit 3 is set to a one, interrupts are enabled on level 3. Processor Status Word (PSW) The processor status word (PSW) is a 16-bit register used to (1) record error or exception conditions that may prevent further processing, and (2) hold certain flags that aid in error recovery. Error or exception conditions recorded in the PSW result in a class interrupt. Each bit in the PSW is described in detail in Chapter 3. The PSW can be accessed by using the Copy Processor Status and Reset (CPPSR) instruction (see Chapter 6). Storage Address Register (SAR) The storage address register (SAR) is a 16-bit register that contains the main-storage address for the last attempted processor storage cycle. This register is addressable by the Diagnose instruction and may be altered or displayed from the optional programmer console. Per-level Registers General Registers Subsequently referred to simply as registers, the general registers are 16-bit registers available to the program for general purposes. Eight registers are provided for each level. The Rand RB fields in the instructions control the selection of these registers. Instruction Address Register (JAR) The instruction address register (JAR) is a 16-bit register that holds the main storage address used to fetch an instruction. After an instruction has been fetched, the IAR is updated to point to the next instruction to be fetched. Note. These registers are sometimes referred to as IARO, IARI, IAR2, and IAR3. The numbers represent the priority level associated with the register. Level Status Register (LSR) Current-Instruction Address Register (CIAR) The level status register (LSR) is a 16-bit register that holds: When the processor enters the stop state, the current-instruction address register (CJAR) contains the address of the last instruction that was executed. The CIAR is not addressable by software. It may be displayed from the optional programmer console. Refer to Stop State in this chapter for methods of entering stop state. • Indicator bits - Set as a result of arithmetic, logical, or I/O operations • A supervisor state bit • An in-process bit • A trace bit • A summary mask bit. Mask Register The mask register is a 4-bit register used for control of interrupts. Bit controls level 0, bit 1 controls level 1, and so on. ° 2-6 GA34-0022 These bits are further discussed in the following sections. Seven other bits in the LSR are not used and are always set to zero. ( : c. Indicator Bits The indicators are located in bits 0-4 of the level status register (LSR). Figure 2-2 shows the indicators and how they are set for arithmetic operations. The indicator bits are changed or not changed depending on the instruction being executed. Some instructions do not affect the indicators, other instructions change all of the indicators, and still other instructions change only specific indicators. Refer to the individual instruction descriptions in Chapter 6 for the indicators changed by each instruction. Level status register (LSR) o c 1 2 3 J 4 I Lzero - Set to 1 if result otherwise, set to O. LNegative - Set to 1 if bit-O of result is I; otherwise, set to O. '----Overflow - Set to 1 if result of arithmetic operation (with the operands regarded as signed numbers) cannot be represented as a signed number in the operand size specified; otherwise set to O. Carry - Set to 1 if the result of add or subtract operations (with the operands regarded as unsigned numbers) cannot be represented as an unsigned number in the operand size specified; otherwise, set to O. Even - Set to 1 if the low-order bit of the result is 0; otherwise, set to O. 1 . -_ _ _ _ 1-..._ _ _ _ _ IS all zeros; Figure 2-2. How indicators are set for signed and unsigned (logical) operations The indicators are changed in a specialized manner for certain operations. These operations are described briefly. Additional information is provided in subsequent sections for those operations where more detail is required. • Add, subtract, or logical operations. The even, negative, and zero indicators are result indicators. For add and subtract operations, the carry and overflow indicators are changed to provide information for both signed and unsigned number representations. • Multiply and divide operations. Signed number operands are always assumed for these operations. The carry indicator is used to provide a divide by zero indication for the divide instruction. The overflow indicator defines an unrepresentable product for multiply operations. Refer to the individual instruction descriptions in Chapter 6. • Priority interrupts and input/output operations. The even, carry and overflow indicators are used to form a three-bit condition code that is set as a binary value. • Compare operations. The indicators are set in the same manner as a subtract operation. • Shift operations. The carry and overflow indicators have a special meaning for shift left logical operations. • Complement operations. The overflow indicator is set if an attempt is made to complement the maximum negative number. This number is not representable. • Set Indicators (SEIND) and Set Level Block (SELB) instructions. All indicators are changed by the data associated with these instructions. Even, Negative, and Zero Result Indicators The even, negative, and zero indicators are called the result indicators. A positive result is indicated when the zero and negative indicators are both off (set to zero). These indicators are set to reflect the result of the last arithmetic, or logical operation performed. A logical operation in this sense includes data movement instructions. See the individual instruction descriptions in Chapter 6 for the indicators changed for specific instructions. c Processing Unit Description 2-7 Even, Carry, and Overflow Indicators - Condition Code for Input/Output Operations The even, carry, and overflow indicators contain the I/O condition code: (1) following the execution of an Operate I/O instruction and (2) following an I/O interrupt. These indicators are used to form a 3-bit binary number that results in a condition code value. For additional information about condition codes, refer to: 1.. 2. Branch on Condition Code (BCC) and Branch on Not Condition Code (BNCC) instructions in Chapter 6. Condition codes in Chapter 4. Carry and Overflow Indicators - Add and Subtract Operations A common set of add and subtract integer operations performs both signed and unsigned arithmetic. Whether a given add or subtract operation is to be regarded as a signed operation or an unsigned operati~n is determined by the programmer's view of the values being presented as operands. The carry and overflow indicators are set to reflect the result for both cases. Carry Indicator Setting The carry indicator is used to signal overflow of the result when operands are presented as unsigned numbers. Overflow Indicator Setting Indicators - Compare Operations A compare operation sets the indicators in the same manner as a subtract operation. The even, negative, and zero indicators reflect the result·. The carry and overflow indicators are set as described previously. Compare instructions provide a test between two operands (without altering either operand) so that conditional branch and jump instructions may be used to control the programming logic flow. The conditions specified in branch and jump instructions are named such that, when the condition of the "subtracted from" operand relative to the other operand is true the jump or branch occurs. Otherwise, the next sequential instruction is executed. This is illustrated in the following example. • Compare operation example Instruction name Assembler mnemonic Operands Compare word CW R3, R4 Operation code Function o 1 1 1 0 o 4 001 5 7 ---.---... 8 R3 for signed and unsigned numbers. The appendix also provides examples for setting the carry indicator and for setting the overflow indicator. Carry and Overflow Indicators - Shift Operations The carry and overflow indicators are changed for shift left logical operations and shift left and test operations. These operations affect the indicators as follows: 1. 2. The carry indicator is set to reflect the value of the last bit shifted out of the target register (register where bits are being shifted). The overflow indicator is set to one if bit-O of the target register was changed during the shift. Otherwise it is set to zero. 15 R4 In this example, the contents of register 3 are subtracted from register 4: Decimal The overflow indicator is used to signal overflow of the result when the operands are presented as signed numbers. Note. Appendix F explains the meaning of these indicators 0 10 11 R4 contents 0000 0000 0000 0010 Unsigned Signed 2 +2 R3 contents 1111111111111011 65531 Subtract result -65529 ..=L +7 Machine operation: 0000 0000 0000 0010 Minuend Subtrahend 0000000000000100 Constant Result 0000 0000 0000 0111 one's complement for two's complement Indicator Settings: E o c o N z 000 I I LResult Is not zero. ~ Result is positive. Result fits operand size as a signed number. L - -_ _ _ _ _ _ _ _ A negative result for an unsigned number. ' - - - - - - - - - - - - Result is not even (low-order bit = 1). 2-8 GA34-0022 c If the programmer is comparing unsigned numbers, such as storage addresses, he should use the logical conditional tests (refer to Figure 2-3). In this example, assuming unsigned number representation, R4 is logically less than R3 and unequal to R3. Therefore, the following branch instructions would cause a transfer to symbolic location A (assuming register values shown in the example). CW BLLT R3,R4 A Example 1. (Equal length operands) Rl R2 R3 I R4 R5 !?6 II _..-_._u_ - Operand l/Result ()"",,.,,nrl " Program steps: or CW BNE R3,R4 A The complementary tests (BLGT and BE) would not cause a transfer in this case. If the programmer is comparing signed numbers, he should use the arithmetic conditional tests (refer to Figure 2-3). In the previous compare word example, assuming signed number representation, R4 is greater than R3 and unequal to R3. The following branch instructions would cause a transfer to symbolic location A. CW BGT or R3,R4 A cw R3,R4 A BNE c AW AWCY AWCY R6,R3 R5,R2 R4,Rl Explanation: The contents of R6 are added to the contents of R3. The contents of R5 are added to the contents of R2 plus any carry from the previous operation. The contents of R4 are added to the contents of Rl plus any carry from the previous operation. Step 1: Step 2: Step 3: Example 2. (Unequal length operands) Rl The complementary tests (BLT and BE) would not cause a transfer. R3 R5 R6 I I Operand l/Result Operand 2 Note. Jump instructions are also available for the logical and arithmetic conditional tests. Note. In this example, operand 2 must be an unsigned number or must be positive. It must be emphasized again that the machine does not regard the numbers as either signed or unsigned. The compare word instruction results in a subtract operation being performed on the values presented. The programmer must then choose the correct conditional test (logical or arithmetic) for the number representation involved. Program Steps: AW AWCY ACY A programmer may desire to work with numbers that cannot be represented in one word or in a doubleword. It may take three or more words to renresent the number. Certain register to register instructions allow the programmer to add or subtract these multi-word operands and then have the indicators reflect the multi-word result. These instructions are: Add Carry Register (ACY) Add Word With Carry (AWCY) Subtract Carry Register (SCY) Subtract Word With Carry (SWCY) R6,R3 R5,R2 Rl Explanation: Step 1: Step 2: Indicators - Multiple Word Operands c R2 Step 3: The contents of R6 are added to the contents of R3. The contents of R5 are added to the contents of R2 plus any carry from the previous operation. Any carry from the previous operation is added to the contents of Rl. Note. In both examples the final indicator settings reflect the status of the 3-word result. Even Set on if the result low-order bit of R3 is zero. Carry Set on if the result cannot be represented as an unsigned 3-word number. Overflow Set on if the result cannot be represented as a signed 3-word number. Negative Set on if the result high-order bit of R 1 is one. Zero Set on if all three result registers contain zeros. The following two examples show how the add instructions are used. A subtract operation would be similar. See Chapter 6 for details of the individual instructions. Processing Unit Description 2-9 Testing Indicators with Conditional Branch and Jump Instructions The indicators are tested according to a selected condition when a conditional branch or a conditional jump instruction is executed. The conditions and the indicators tested for each condition are shown in Figure 2-3. The conditional instructions are: • • • • Branch on Condition (BC) Branch on Not Condition (BNC) Jump on Condition (JC) Jump on Not Condition (INC) The assembler also provides extended mnemonics for the conditions shown in Figure 2-3. Refer to the individual instructions in Chapter 6. Condition tested by conditional branch or jump instruction Assembler extended mnemonics Zero or equal BE, BZ, JE, J Z Not zero or unequal BNE, BNZ, JNE, JNZ Positive and not zero BP,JP Not positive BNP, JNP Indicators tested 0 1 2 3 4 E C 0 N Z 1 0 0 0 1 1 Negative BN,JN 1 Not negative BNN,JNN 0 Even BEV,JEV 1 Not even BNEV,JNEV 0 Arithmetically less than BLT, JLT 0 1 1 0 Arithmetically less than or equal BLE, JLE 0 1 1 0 Arithmetically greater than or equal BGE, JGE 1 1 0 0 Arithmetically greater than BGT, JGT 1 1 0 0 0 0 Logically less than or equaL BLLE, JLLE 1 Logically less than (carry) BLLT, JLLT 1 Logically greater than BLGT,JLGT 0 Logically greater than or equal (no carry) BLGE,JLGE 0 1 1 Legend: Figure 2-3. 2-10 LSR bit Indicator 0 1 2 3 4 E - Even C - Carry 0- Overflow N - Negative Z - Zero 0 Indicators tested by conditional branch and jump instructions GA34-0022 c Supervisor State Bit Program Execution LSR bit 8, when set to one, indicates that the processor is in the supervisor state. This state allows privileged instructions to be executed. It is set by any of the following: Instruction Formats 1. 2. 3. c Class interrupt a. M~whine check condition b. Program check condition c. Power/thermal warning d. Supervisor Call (SVC) instructio11. e. Soft exception trap condition f. Trace g. Console interrupt I/O interrupt Initial program load OPL) The processor instruction formats are designed for efficient use of bit combinations to specify the operation to be performed (operation code) and the operands that participate. Some formats also include (1) an immediate data field or word, (2) an address displacement or address word, and (3) a function field that further modifies the operation code. Various combinations of these fields are used by the individual instructions. Some typical instruction formats are presented in this section. All formats are shown in the section InstructiQn Formats in Appendix B. One Word Instructions The basic instruction length is one word (16 bits). The operation code field (bits 0-4) is the only common field for all formats. This field, unless modified by a function field, specifies the operation to be performed. For a format without a function field, bits 5-15 specify the location of operands or data associated with an operand: When LSR bit 8 is set to zero, the processor is in problem state. For a selected priority level, the supervisor can alter the supervisor state bit by using a Set Level Block (SELB) instruction. For additional information, refer to Processor State Control in this chapter. Class interrupts and I/O interrupts are described in Chapter 3. IPL is discussed in a subsequent section of this chapter. Example: In-process Bit Instruction name Assembler mnemonic Syntax Add Byte Immediate ABI byte,reg LSR bit 9, when set to one, indicates that a priority level is currently active or was preempted by a higher priority level before completing its task. Bit 9 is turned off by a Level Exit (LEX) instruction. Bit 9 can also be turned on or off by a Set Level Block (SELB) instruction. The in-process bit also affects level switching under program control. Refer to Chapter 3. Interrupts and Level Switching. Io Operation code 0 0 0 0 045 LSR bit 10, when set to one, causes a trace class interrupt at the beginning of each instruction. The bit can be turned on or off with the Set Level Block (SELB) instruction. The trace bit aids in debugging programs. See Class Interrupts in Chapter 3. Immediate R 7 8 15 Bits 0-4 Operation code (specifies ABI instruction). Bits 5-7 General register (0-7). This register contains data for the second operand. Immediate data for the first operand. Bits 8-15 Trace Bit I In some cases the operation code is the same for a group of instructions. The format for this group includes a function field. The bit combinations in the function field then determine the specific operation to be performed. Summary Mask Bit LSR bit 11, when set to zero (disabled), inhibits all priority interrupts on all levels. When this bit is set to one (enabled), normal interrupt processing is allowed. Refer to Summary Mask in Chapter 3 for details relating to control of the summary mask. c Processing Unit Description 2-11 Example: Instruction name Assembler mnemonic Syntax Add Word AW reg, reg Operation code Function o 01110 o 4 5 Bits 0-4 Bits 5-7 Bits 8-10 Bits 11-15 7 8 1 000 10 11 15 Operation code for a group of instructions. General register (0-7). This register contains data for the· first operand. General register (0-7). This register contains data for the second operand. Function field. Modifies the operation code to specify the Add Word instruction. Note. For other instruction groups, the function field may vary as to location within the format, and also the number of bits used. Two Word Instructions The first word of this format is identical to the one-word format. The second word (bits 16-31) contains either immediate data, an address, or a displacement. This word is used to (1) provide data for an operand, or (2) provide a main storage address or displacement for effective address generation (see Effective Address Generation in this chapter). Variable Length Instructions Some instructions use a selectable encoded technique for generating effective addresses. This method is referred to as an address argument technique in subsequent sections. These instruction formats contain a base register (RB) field and an address mode (AM) field. If both operands are using this technique, the format contains an RB and associated AM field for each. These fields are in the first instruction word. The AM field consists of two bits and is referred to in binary notation (AM=OO, 01, 10, or 11). If AM is equal to 10 or 11 an additional word is appended to the normal instruction word. For a format that contains two AM fields, two additional words may be appended. See Effective Address Generation in this chapter for a description of the appended words and how they are used. For instructions with a single storage address argument, the RB field consists of two bits. An RB field of two bits with its associated AM field of two bits are referred to as a 4-bit address argument or addr4 in assembler syntax. Example: Instruction name Assembler mnemonic Syntax Compare byte CB addr4, reg , Operation code 1 1 000 o 4 5 789101112 , 15 Example: Appended word, AM=10 or 11 Instruction name Assembler mnemonic Syntax Branch and Link BAL longaddr ,reg 16 Operation code o 1 101 o 7 8 15 Address or displacement 16 31 Bits 0-4 Bits 5-7 Bits 8-10 Bit 11 Bits 12-15 Bits 16-31 Operation code General register (0-7) for the second operand General register (0-7) for the first operand I ndirect addressing bit Function field A main storage address used for the first operand Note. In this example, the register designated Rl is associated with the second operand in assembler syntax. 2-12 GA34-0022 Bits 0-4 Bits 5-7 Bits 8-9 Bits 10-11 Bits 12 -15 Bits 16-31 31 Operation Code. General register (0 - 7) for the second operand. Base register (0-3). Address mode. Function. Appended word for the first operand. Note. The register specified by the RB field is a general register that is used as a base register for effective address generation. Some instruction formats have two storage address arguments. In this case, the first operand has a 3-bit RB field giving a 5-bit address argument (addrS in assembler syntax) and the second operand has a 4-bit address argument. <-: c Example: Instruction name Assembler men monic Syntax Add Word AW addr5,addr4 Uperation code 010 o Appended word for operand 1 16 Effective Address Generation 31 Appended word for operand 2 47 32 Bits 0-4 Bits 5-7 Bits 8-9 Bits 10-11 Bits 12-13 Bits 14-15 Bits 16-31 Bits 32-47 Operation code. Base register (0-7) for the first operand. Base register (0-3) for the second operand. Address mode for the first operand. Address mode for the second operand. Function. Appended word for the first operand. Appended word for the second operand. Notes. 1. If there is no appended word for the first operand (AM1=00 or 01), the second operand word is appended to the instruction word in bits 16-31. 2. Registers specified by the RB fields are general registers. Names of Instruction Formats Names have been established for several categories of instructions. Each category has the same basic instruction format, therefore, the name is related to the format. In most cases, the name indicates the location of the operands or the type of instruction. o • Shift Instructions with Immediate Count This is a shift instruction with the count field contained within the instruction word. • Storage Immediate Instructions One operand is in main storage. The other operand uses an immediate data field. The immediate data field is the second ward 0f a tW0-W 0 rlj fnrTl1~t • Parametric Instructions For this instruction format, a parameter field (bits 8-15) is contained within the instruction word. For purposes of storage efficiency, certain instructions formulate storage operand addresses in a specialized manner. These instructions have self-contained fields that are used when generating effective addresses. Standard methods for deriving effective addresses are included in this section. Other methods such as bit displacements, are explained in the individual instruction descriptions in Chapter 6. Programming Note. For certain instructions, the effective address points to a control block rather than an operand. These instructions are: • • • • • • • • • • Copy Level Block (CPLB) Load Multiple and Branch (LMB) Pop Byte (PB) Pop Ooubleword (PO) Push Byte (PSB) Push Doubleword (PSD) Push Word (PSW) Pop Word (PW) Set Level Status Block (SELB) Store Multiple (STM) Base Register Word Displacement Short Instruction format WD o 4 8 9 11 15 ~ Examples: Base register - - - - - - - - ' • Register/Register Instructions General registers are used by both operands. • Storage/Storage Instructions Both operands reside in main storage. • Register/Storage Instructions One operand uses a general register. The other operand resides in main storage. • Register Immediate Instructions One operand uses a general register. The other operand uses an immediate data field. The immediate data field is the low order byte of a one-word format or the second word of a two-word (long) format. 00 01 10 11 Register 0 Register 1 Register 2 Register 3 Word displacement - - - - - - - - - ' Range 0 to 31 (decimal) The five-bit unsigned integer (WD) is doubled in magnitude to form a byte displacement then added to the contents of the specified base register to form the effective address. The contents of the base register must be even. Processing Unit Description 2-13 Example: I Opnation Example: codel WD 1 1 o 4 8 9 11 o 15 Contents of register 1 (RB) 0000 0000 0110 0000 Word displacement (WD) doubled + a 1000 0000 0000 a11 a 1000 Effective address Hex Dec 0060 0096 8 8 0068 0104 Base Register Word Displacement 4 5 a 1 a 15 78 Note. This example uses a negative word displacement (-17 hex) shown in two's complement. Hex Dec Contents of register 6 (RB) 0000 0000 1000 0110 0086 0134 Word displacement (WD) doubled (sign bit is propagated left) + 111111111101 0010 - 2E- 46 0000 0000 0101 1000 0058 0088 Effective address Instruction format Four-Bit Address Argument Instruction forma t I Operation code 000 001 010 all 100 101 110 111 Register Register Register Register Register Register Register Register a 1 2 3 4 5 6 7 Word displacement -----~ Range +127 to -128 (decimal) The eight-bit signed integer (WD) is doubled in magnitude to form a byte displacement then added to the contents of the specified base register to form the effective address. The contents of the base register must be even. The word displacement can be either positive or negative; bit 8 of the instruction word is the sign bit for the displacement value. If this high-order bit of the displacement field is a 0, the displacement is positive with a maximum value of +127 (decimal). If the high-order bit of the displacement field is aI, the displacement is negative with a maximum value of -128. The negative number is represented in twos-complement form. 2-14 GA34-0022 o I 4 RB 8 9 T Base register AM 1011 ---....- 15 00 Register a (AM=OO or 01) 00 No register (AM=10 or 11) 01 Register 1 10 Register 2 11 Register 3 Address mode -------~ The Address Mode (AM) has the following significance: AM=OO. The contents of the selected base register form the effective address. AM=Ol. The contents of the selected base register form the effective address. After use, the base register contents are incremented by the number of bytes in the operand. For some instructions the effective address points to a control block rather than an operand. When the effective address points to a control block, the base register contents are incremented by two. c: Example: I Opemtion code I RB AM 0 0 0 8 4 9 10 11 15 Hex Effective address (contents of register 1) Contents of register 1 after instruction execution Byte operand Word operand Double word operand c Dec 0000000010000000 0080 0128 0000 0000 1000 0001 00000000 10000010 0000 0000 1000 0100 0081 0129 0082 0130 0084 0132 Notes. 1. For register to storage instructions, if the register specified is the same for both operands then the register will be incremented prior to using it as an operand. 2. Certain instructions (storage-to-storage) have two address arguments. Operand 1 has a 3-bit RB field with its associated AM field. Operand 2 has a 2-bit RB field with its associated AM field. If both RB fields specify the same register and both AM fields are equal to 01 , the base register contents are incremented prior to fetching operand 2 and again after fetching operand 2. Assuming the same conditions but with the operand 2 AM field not equal to 01, the base register contents are incremented prior to calculating the effective address for operand 2. 3. If the effective address points to a control block rather than an operand, the base register contents are incremented by two. AM=10. An additional word is appended to the instruction. The word has the following format. Address or displacement 16 31 • If RB is zero, the appended word contains the effective address . • If RB is non-zero, the contents of the selected base register and the contents of the appended word (displacement) are added to form the effective address. o Processing Unit Description 2-15 Example: Address 1 Operation code a a a a a a a o 8 4 Contents of register 3 Contents of appended word Effective address 9 101112 a a a a a a a a 31 15 16 Hex Dec 0800 2048 0000 1000 0000 0000 + 0000 000 1 0000 0000 0100 0256 0900 2304 0000 100 1 0000 0000 AM=ll. An additional word is appended to the instruction . • If RB is zero, the appended word has the format: Indirect address 16 31 This address points to a main storage location, on an even byte boundary, that contains the effective address. Example: Indirect address Operation code o o 4 8 9 10 11 12 a 0 0 001 0 1 0 a 0 0 31 15 16 Hex Contents of appended word Effective address equals contents of storage at address 0080 (decimal) 0 0 0 l , Dec 0000 0000 0101 0000 0050 0080 0000 0100 0000 0000 0400 1024 • If RB is non-zero, the appended word has the format: Displacement 1 16 Displacement 2 2324 31 The two displacements are unsigned eight-bit integers. Displacement 2 is added to the contents of the selected base register to generate a main storage address. The contents of this storage location are added to Displacement 1 resulting in the effective address. ( ," .. 2-16 GA34-0022 c Example: Operation code 000 o 89101112 4 15 16 2324 Contents of register 2 Displacement 2 Storage address 00000101 0011 0101 + 01000010 0000 0101 0111 0111 Dec 0535 1333 42 66 0577 1399 Contents of storage at address 1399 (decimal) Displacement 1 Effective address + 0000 0100 0001 0000 00100101 000001000011 0101 0410 1040 25 37 0435 1077 0 31 Hex Note. This example is invalid for other than a byte operand. Programming Note. This addressing mode (AM = 11, RB is non-zero) is useful for the directorized data concept. For the addr4 or addr5 assembler syntax, the programmer codes the form displacement 1 (register, displacement 2)*. For addr4, the specified register is 1-3. For addrS, the specified register is 1-7. The asterisk denotes indirect addressing. I Address of directory Data sets Directory Register I I • , I I displacement 2 I I A Address of data set A Address of data set B Address of data set C B • ~ c I I displacement 1 I I t Data c Processing Unit Description 2-17 Five-Bit Address Argument I Instruction format loperation code o Base 000 000 001 010 011 100 101 11 0 111 4 RB 15 1011 5 7 -....- register~ Register 0 (AM=OO or 01) No register (AM=10 or 11) Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Address mode -------~ Operation of this mode is identical to the four-bit argument, but provides additional base registers. Base Register Storage Address Instruction format Operation code o 4 Base register 000 001 010 011 100 101 110 111 No register Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Address/displacement 8 101112 ~ 15 16 31 ---------------~~-----------------Address field I 0 = direct address 1 1 = indirect address • If RB is zero, the address field contains the effective address. • If RB is non-zero, the contents of the selected base register and the contents of the address field are added together to form the effective address. Note. Bit 11, if a one, specifies that the effective addressing is indirect. ( -~»- -~> 2-18 GA34-0022 Example: Indirect address Address Operation code 00000 1 0 0 000 1 000 0 o 1011 12 8 4 31 15 16 Hex Contents of register 4 Address field Storage address Effective address Contents of storage at address 1296 (decimal) Dec 0000 0001 0000 0000 + 0000 0100 0001 0000 00000101 0001 0000 0100 0256 0410 1040 0510 1296 0000011001000000 0640 1600 Instruction Length Variations for Address Arguments • One-word instructions that contain a single AM field become two words in length if AM is equal to 10 or 11. The AM appended word follows the instruction word. Example: AM=OO or 01 IInstruction word o c AM=IO or 11 IInstruction No appended word 15 word o lAM appended wmd 31 15 16 • Two-word instructions that contain a single AM field become three words in length if AM is equal to 10 or 11. The AM word is appended to the first instruction word. The data or immediate field then becomes the third word of the instruction. Example: AM=OO or 01 IInstruction word 0 AM=10 or 11 Instruction word 0 IImmedia te field 15 16 AM appended word 15 16 31 Immediate field 31 32 47 • One-word instructions that contain two AM fields (AMI and AM2) may be one, two, or three words in length depending on the values of AMI and AM2. The AMI word is appended first, then the AM2 word is appended. o Processing Uni t Description 2-19 Example: AMl=OO or 01 AM2=00 or 01 IInstruction AMl=10 or 11 AM2=00 or 01 IInstruction 15 word o AMl=OO or 01 AM2=10 or 11 IInstruction lAM 1 appended word 15 16 word o AMl=10 or 11 AM2=10 or 11 No appended word word o Instruction word o IAM2 31 appended word 15 16 AMI appended word The processor is always in one of the following mutually exclusive states: Power off Stop Load Wait Run - when in run state, programs can be executed in either: Supervisor state or - Problem state AM2 appended word 31 32 15 16 Processor State Control • • • • • 31 47 While the processor is in the stop state: (I) the Stop light on the programmer console is on, (2) the functions provided on the console can be activated, and (3) no interrupt requests can be accepted by the processor. If, when accessing main storage through the console while in stop state, a check condition arises: 1. Program check is suppressed. 2. The PSW bit(s) is set. 3. The check light is turned on. 4. The Display Register will be set to a default value of 0025. The processor exits the stop state when: Stop State The stop state is entered when: 1. 2. 3. 4. S. 6. 7. The Stop key on the programmer console is pressed. The STOP instruction is executed and the mode switch on the basic console is in the Diagnostic position. An address-compare occurs and the rate control on the programmer console is in the Stop on Address position. An instruction has completed execution and the rate control on the programmer console is in the Instruction Step position. An error occurs and the error control on the programmer console is in the Stop on Error position. The Reset key on the programmer console is pressed. Power-on reset occurs. For conditions 1-6, the display buffer contains the contents of the IAR. 1. 2. The Load key on the basic console is pressed. The Start key on the programmer console is pressed. When the Start key is pressed, the processor returns to the state that was exited before entering stop state. If the run state is entered, one instruction is executed before interrupts are accepted by the processor. If the stop state was entered because of a reset (power-on reset or reset key), pressing the Start key causes program execution to begin on level zero with the instruction in location zero of main storage. If the stop state was entered because of an error, with the Stop on Error switch turned on, (I) a system reset clears the error condition, or (2) pressing the Start key allows the error interrupt to be handled as if the Stop on Error switch were not on. For more information about system reset, see State of Processor Following a Reset. Note. Any manual entry into Stop State is via the programmer console. The STOP instruction performs no operation if the programmer console is not installed. (:: 2-20 GA34-0022 c Wait State The processor enters wait state when: (1) Level Exit (LEX) instruction is executed and no other level is pending, or (2) a Set Level Block (SELB) instruction is executed that sets the current in-process bit off and no level is pending. While the processor is in the wait state, (1) the Wait light on the basic console IS on and (2) mterrupts can oe accepted under control of the system mask register and the summary mask as defined by the LSR of the last active level. The processor exits the wait state when: 1. 2. 3. 4. The Stop key on the programmer console is pressed. The Reset key on the programmer console is pressed. An I/O interrupt is accepted (the level must be enabled by the mask register). A class interrupt occurs. (See Class Interrupts in Chapter 3.) Load State The processor enters the load state when initial program load (lPL) begins. This occurs: 1. When the Load key on the basic console is pressed. 2. After a power-on reset if the Mode switch is in the Auto IPL position. 3. A signal from a host system. c While the processor is in load state, the Load light on the basic console is on. The processor exits the load state and enters the run state upon successful completion of the IPL. See Initial Program Load (IPL). Run State The processor enters the run state when not in the stop, wait, or load state. Run state is entered: 1. 2. 3. From load state upon successful completion of IPL. From wait state when an interrupt is accepted. From stop state when the start key is pressed. (See Stop State.) The processor exits run state when entering stop, wait, or load states as previously described. Supervisor State and Problem State While in run state, instructions can be executed in either supervisor state or problem state. This is determined by bit 8 of the level status register (LSR): State Supervisor Problem c LSR bit 8 1 o Supervisor and problem states are discussed in the following sections. Supervisor State. The processor enters supervisor state when: 1. 2. 3. A class interrupt occurs. This type of interrupt is caused by the following: a. Machine check condition b. Program check condition c. Power/Thermai warning d. Supervisor Call (SVC) instruction e. Soft exception trap condition f. Trace bit (LSR bit 10) set to one g. Console Interrupt key on the programmer console. An I/O interrupt is accepted. After initial program load (lPL) has completed. Class interrupts and I/O interrupts are discussed in Chapter 3. Initial program load is discussed in a subsequent section of this chapter. When the processor is in supervisor state, the full instruction set may be executed. The following privileged instructions may only be executed in supervisor state: Copy Console Data Buffer (CPCON) Note 1 Copy Current Level (CPCL) Copy In-Process Flags (CPIPF) Copy Interrupt Mask Register (CPIMR) Copy Level Status Block (CPLB) Copy Processor Status and Reset (CPPSR) Diagnose (DIAG) Disable (DIS) Enable (EN) Level Exit (LEX) Operate I/O (10) Set Console Data Lights (SEC ON) Note 2 Set Interrupt Mask Register (SEIMR) Set Level Status Block (SELB) Notes. 1. The resultant data is unpredictable if the programmer console feature is not installed. 2. Performs no operation if the programmer console feature is not installed. Problem State. This is a state that does not allow the processor to execute the privileged instructions. The processor enters the problem state when the supervisor state bit (LSR bit 8) is turned off. This can be accomplished with a Set Level Status Block (SELB) instruction. This instruction can change the contents of the registers for a selected processor level. While the processor is in problem state, privileged instructions cannot be executed. If a privileged instruction execution is attempted, the instruction is suppressed and a program check class interrupt occurs, with privilege violate (bit 2) set in the processor status word. Processing Unit Description 2-21 State of Processor Following a Reset The term reset used in the following sections denotes the reset action that occurs during: 1. 2. 3. Power-on reset Initial program load (lPL) reset System reset initiated by pressing the Reset key on the programmer console The following registers and conditions are not initialized by a reset and require program or operator action before they become valid: • • • • • Console data buffer (programmer Console Feature) General registers IAR on levels 1-3 Main storage (above 16K) Address Compare Register The following registers and conditions are initialized by a reset: • • • • • • • • • • • • • • Level Zero Indicator (turned on) CIAR - set to zeros IAR on level zero - set to zeros Mask register - set to ones (all levels enabled) LSR on level zero Indicators - set to zeros - Supervisor state (bit 8) - set on - In-process (bit 9) - set on Trace (bit 10) - set to zero (disabled) - Summary mask (bit 11) - set on (enabled) - All other bits - set to zeros PSW - set to zeros except as noted Auto-IPL (bit 13) - set to zero unless the reset was caused by an Auto-IPL Power/Thermal (bit 15) reflects the status of the power/thermal condition LSR on levels 1-3 - set to zero SAR - set to zeros Display buffer - set to all ones by Power-on Reset only (programmer Console Feature) Main storage (0-16K, verified good parity Power-on Reset only) Check Restart (Note 1) Instruction Step (Note 1) Stop on Address (Note 1) Stop on Error (Note 1) Note 1. This condition is reset by a Power-on Reset. 2-22 GA34-0022 Initial Program Load (IPL) An initial program load function is provided to (1) read an IPL record (set of instructions) from an external storage media, and (2) automat,ically execute a start-up program. An IPL record is read into storage from a local I/O device or host system. The I/O attachments for the desired IPL sources are prewired at installation time. Two local sources, primary and alternate, can be wired and either can be selected by using the IPL Source switch on the console. IPL can be started by three methods: 1. 2. 3. c Manually, by pressing the Load key on the console. Automatically, after a power-on condition. Automatically, when a signal is received from a host system. The host system can be connected through a communications adapter. The automatic power-on IPL is selected by a mode switch on the console. When the Mode switch is in the Auto-IPL position, IPL occurs whenever power turns on (either initially or after a power failure). Power must be good to all attachments before the IPL sequence begins. Auto IPL is useful for unattended systems. A manual IPL can be initiated at any time by pressing the load key on the console (even when in run state). The mode switch has no effect on the manual IPL. For Auto-IPL and manual IPL, the local IPL source (primary or alternate) is selected. IPL from a host system can occur at any time and is initiated by the host system. The IPL record is transferred through the host-system device; for example, the communications adapter. When an auto-IPL occurs, bit 13 of the PSW is turned on to indicate the condition to the software. When a manual or host-system IPL occurs, this bit is set to zero. During IPL main storage is loaded starting at location zero. The length of the IPL record depends on the media used by the IPL source. Upon successful completion of an IPL, the processor enters supervisor state and begins execution on priority level zero. The summary mask is enabled and all priority interrupt levels in the mask register are enabled. The first instruction to be executed is at main storage location zero. The IPL source has a pending interrupt request on level zero. The system program must: 1. Perform housekeeping; for example, load vector table addresses in the reserved area of storage (see Automatic Interrupt Branching in Chapter 3). 2. Issue a Level Exit (LEX) instruction. This allows the processor to accept the interrupt from the IPL source. When the interrupt is accepted, a forced branch is taken using the device-address vector table. The vector table entry is determined by the device address of the IPL source and results in a branch to the proper program routine for handling the interrupt. The device address of the IPL source is set into bits 8-15 of register 7 on level zero. Condition code 3, device end, is reported by the IPL source. For additional information, see I/O Interrupts in Chapter 3. , t , A system reset always occurs prior to an IPL. However, if any errors occur during the IPL. the results are unpredictable. Sequential Instruction Execution Normally, the operation of the processor is controlled by Instructlons taken in sequence. An instruction is fetcheu from the main storage location specified in the instruction address register OAR). The instruction address in the IAR is then increased by the number of bytes in the instruction just fetched. The IAR now contains the address of the next sequential instruction. After the current instruction is executed, the same steps are repeated using the updated address in the IAR. A change from sequential operation can be caused by branching, jumping, interrupts, level switching, or manual intervention. Jumping and Branching The normal sequential execution of instructions is changed when reference is made to a subroutine; when a two-way choice is encountered; or when a segment of coding, such as a loop, is to be repeated. All of these tasks can be accomplished with branching and jumping instructions. Provision is also made for subroutine linkage, permitting not only the introduction of a new instruction address, but also the preservation of the return address and associated information. The conditional branch and jump instructions are used to test the indicators in the LSR. These indicators are set as the result of I/O operations and most arithmetic or logical operations. Single or multiple indicators are tested as determined by the value in a three-bit field within the instruction. Refer to: (I) Indicators and (2) Testing Indicators with Conditional Branch and Jump Instructions. Jumping Jump instructions are used to specify a new instruction address relative to the address in the IAR. The new address must be within -256 to +254 bytes of the byte following the jump instruction. Note. The jump instruction contains a word displacement that is converted to a byte displacement when the instruction is executed. However, when using the assembler, the programmer specifies a byte value that is converted to a word displacement by the assembler. Branching Branch instructions are used to specify a new full-width 16-bit address. A 16-bit value, range to 65535, is contained in the second word of the instruction or in a register. The value in the second word can be used as the effective branch address or added to the contents of a base register to form an effedive auuless. (St:t: DU:)t: Register Storage Address in this chapter.) ° Level Switching and Interrupts The processor can execute programs on four different interrupt priority levels. These levels, listed in priority sequence, are numbered 0, 1, 2, and 3 with level having highest priority. The processor switches from one level to another in two ways: ° 1. 2. Automatically, when an interrupt request is accepted from an I/O device operating on a higher priority level than the current level. Under program control, by using the Set Level Block (SELB) instruction. Both types of level switching are discussed in detail in Chapter 3. Qass Interrupts and Interrnpt Masking Facilities are also discussed in Chapter 3. Stack Operations The processing unit provides two types of stacking facilities. Each facility is briefly described in this section. Additional information appears in subsequent sections. The two types of stacking facilities are: 1. Data Stacking. This facility provides an efficient and simple way to handle last-in first-out (LIFO) queues of data items and/or parameters in main storage. The data items or parameters are called stack elements. For a given queue (or stack), each element is one, two, or four bytes wide. Instructions for each element size (byte, word, or doubleword) are provided to: a. Push an element into a stack (register to storage). b. Pop an element from a stack (storage to register). 2. Linkage stacking. This facility provides an easy method for linking subroutines to a calling program. A word stack is used for saving and restoring the status of general registers and for allocating dynamic work areas. The Store Multiple (STM) instruction stores the contents of the registers into the stack and reserves a designated number of bytes in the stack as a work area. The Load Multiple and Branch (LMB) instruction reloads the registers, releases the stack elements, and causes a branch via register 7 back to the calling program. c Processing Unit Description 2-23 Data S tacking Description Any contiguous area of main storage can be defined as a stack. Each stack is defined by a stack control block. Figure 2-4 shows a data stack and its associated stack control block. Stack control blocks must be aligned on a word boundary. The words in the stack control block are used as follows: High Limit Address (HLA). This word contains the address Qf the first byte beyond the area being used for the stack. All data in the stack has a lower address than the contents of the HLA. Note that the HLA points to the first byte beyond the bottom of an empty stack. Low Limit Address (LLA). This word designates the lowest storage location that can be used for a stack element. Note that the LLA points to the top of a stack. Top Element Address (TEA). This word points to the stack element that is currently on top of the stack. For empty stacks, the TEA points to the same location as the high limit address (HLA). Note. For word stacks or double word stacks, the HLA, LLA, and TEA must all contain an even address to ensure data alignment on a word boundary. Main Storage Address 0000 l~----tl Stack control block - Top element address (TEA) Word 0 High limit address (HLA) Word 1 Low limit address (LLA) Word 2 Stack ----- _F~ll_s~c~ ~ I.Ei Empty stack TEA ~ Stack element Stack element 0 The TEA for an empty stack points to the same place as the HLA Figure 2-4. 2-24 GA34-0022 \ 15 Stack clement shown is 1 word; element can be 1, 2, or 4 bytes wide Relationship of stack control block to data stack c Push Operation. When a new element is pushed into a stack, the address value in the TEA is decremented by the length of the element (one, two, or four bytes) and compared against the LLA. If the TEA is less than the LLA, a stack overflow exists. A soft exception trap interrupt occurs with stack exception set in the PSW. The TEA is unchanged. If the stack does not overtlow, the TEA IS updated and the new element is moved to the topic location defined by the TEA. The following diagram shows how elements are pushed into a stack. Note that each push operation always places an element at a lower address in the stack than the preceding element. LLA---.. Empty Stack TEA Push TEA Push TEA c ~ and HLA Refer to Chapter 6 for descriptions of the following instructions: • Push Byte (PSB) • Push Word (PSW) • Push Doubleword (PSD) Pop Operation. When an element is popped from a stack, the TEA is compared against the HLA. If it is equal to or greater than the HLA, an underflow condition exists. A soft exception trap interrupt occurs with stack exception set in the PSW. If the stack does not underflow, the stack element defined by the TEA is moved to the specified register and the TEA is incremented by the length of the element. The following diagram shows how elements are popped from a stack. c Processing Unit Description 2-25 LLA TEA Empty Pop stack Pop Pop TEA --..: HLA~ Refer to Chapter 6 for descriptions of the following instructions: • Pop Byte (PB) • Pop Word (PW) • Pop Doubleword (PD) Data Stacking Example - Allocating Fixed Storage Areas Many programs require temporary main storage work areas. It is very useful to be able to dynamically assign such workarea storage to a program only when that storage is needed. Conversely, when work-area storage is no longer needed by a program, it is desirable to free that resource so it may be used by other programs. Use of the stacking mechanism can assist in the programming of the dynamic storage management function. The following is an example of how storage areas could be allocated using the stacking mechanism. A stack is initialized with addresses that point to a fixed area of storage. Each element in the stack represents the starting address of a block of storage consisting of 512 bytes; e.g., addresses 0200 through 03FF. As storage is needed, the starting address for a block of storage is popped from the stack. When the block of storage is no longer needed, the starting address is pushed back into the stack. The stack control block, stack, and storage areas appear initially as follows: 2-26 GA34-0022 C Stack control block Stack control block TEA~ OBOO TEA~ HLA OB08 HLA LLA---1 OBOO ~08 LLA--1 ----.. rI TEA after 1 Pop ------l L - - - Full stack TEA = LLA = OBOO 0B0 2 OBOO I Stack 0200 LLA = OBOO 0400 TEA = OB02 ;:;:::::::t-...... 0600 0600 0800 0800 To the register specified by Pop instruction HLA = OB08 --.. HLA=OB08~ Storage areas Storage areas 0200 0200 Available storage Cr 0400 0400 Available storage 0600 0800 0600 Available storage Available storage Notice that each stack element is one word long; addresses of storage areas are the stack elements; the TEA points to the lowest location of the last element because the initialized stack is full. Contrast this with an empty stack, in which the TEA points to the same location as the HLA. Available storage 08""'--.-1 Available storage The word element popped is placed in the register specified by the pop word instruction executed by program A. This is the address of the 512-byte storage area beginning at address 0200. Now assume that program A requires a block of storage. Program A (or a storage management function at the request of program A) issues a pop word instruction against the stack control block. The TEA is updated as follows: c Processing Unit Description 2-27 At this time, assume that program B (operating on a different hardware level than program A) also requires a storage area. It too executes a pop word instruction against the stack. The next element is moved to the register specified and points to the next available storage area and the TEA is updated: Stack control block TEA OB02 HLA OB08 LLA OBOO TEA after program A Push operation (~J Stack control block Stack TEA- OB04 HLA- OB08 LLA = OBOO LLA - OBOO TEA = OB02 - T E A after second Pop 0600 Stack 0800 HLA = OB08 .---.. LLA=OBOO_ Storage areas TEA = OB04 ----+- 0600 0800 t HLA=OB08- .. "' Storage areas Available storage Available storage A similar operation will be performed by program B when it releases its storage to the stack, popping address 0400 into location OBOO. While the addresses are obviously shuffled in the stack (from the values initially established), this presents no problem since each program requires only an area of storage - it is not important where that area is located. Now, before any further requests occur, program A terminates its need for a work area. Program A then issues a push word instruction against the stack and returns the address of the area it was using for use by other programs: (: 2-28 GA34-0022 c 11 iii tI c m Linkage Stacking Description As previously described a word-stack mechanism may be used for subroutine linkage. This mechanism saves and restores registers and allocates dynamic work areas. The letters in the following description correspond to the letters in Figure 2-5. The Store Multiple (STM) instruction specifies: Stack control block TEA HLA LLA Stack control block address Limit register (RL) number Stack II Number (N) of words to allocate for work areas When the STM instruction is executed, the allocate value (N) plus the number of registers saved plus one control word is the requested block size in words. This times 2 is the size in bytes. The block size is used to decrement the TEA before an overflow check is made. If no overflow occurs the operation proceeds. The link register (R 7) and register o through the specified limit register (RL) are saved sequentially in the stack. If register 7 is specified as the limit register, only register 7 is stored in the stack. The dynamic work space is allocated and a pointer to the work area is returned in register RL. If no work area is specified, the returned pointer contains the location of R7 in the stack. The values of RL and N are saved as an entry in the stack. The TEA is updated to point to the new top of the stack location. When a Load Multiple and Branch (LMB) instruction is executed, the values of RL and N are retrieved from the stack and an underflow check is made. The value of RL controls the reloading of the registers; the values of RL and N are used to restore the stack pointer (TEA) to its former status. The contents of register 7 are then loaded into the instruction address register, returning program control to the calling routine. N New TEA ----+- RLl o 2 3 15 New RL----+Dynamic work area J N I R7 contents RO contents • • • • RL contents Old TEA and HLA ~ Figure 2-5. Word stack for subroutine linkage o Processing Unit Description 2-29 Linkage Stacking Example - Reenterable Subroutine A subroutine may be used by programs that operate on different interrupt levels. Rather than providing copies of the subroutine, one copy for each program that needs it, the subroutine can be made reenterable. Here, only one copy of the subroutine is provided; the single copy is used by all requesting programs. Two items must be considered in the reenterable subroutine code: • Saving the register contents of each calling program. The subroutine is then free to use the same registers, restoring their contents to the calling-program's values just prior to returning to the calling program. • Preserving the applicable variable data (generated by the subroutine) that is related to each call of the subroutine. That is, data associated with one call must not be disturbed when subroutine execution is restarted due to another call from a higher priority program. The stacking. mechanism, by means of the STM and LMB instructions, handles the two items just mentioned. As an example, operation could proceed as follows: 1. 2. Program A calls the subroutine by means of a branch and link instruction (return address is in R7). BAL SUBRT,7 The subroutine, in this example, uses registers R3 and R4 during its execution. The subroutine receives (from program A) a parameter list address in RO and the address of the stack control block in Rl. Also, the subroutine requires 20 bytes of work space. Thus, the subroutine executes, upon entry, the following store mul ti pIe instruction: SUBRT STM 4,(1 ),20 After execution of the STM, the stack contains the following: c Stack 20 bytes R7 RO Rl R2 R3 R4 HLA~ * The last word contains a value that specifies the last register stored (e.g., R4 in this example) and the size of the dynamic work area (in words). 3. , f , R4 (the last register stored in the stack) is automatically loaded, during the STM operation, with the address of the work area to be used by the subroutine to hold its work data. When subroutine processing for this call is completed, the subroutine executes a single load multiple instruction in order to reload the registers and return (via R7) to the calling program: LMB (1) If a second call to the subroutine has occurred prior to execution of the LMB, action similar to that just stated would occur again. However, another stack area would be used. Then, when subroutine execution is completed for the second call, and all higher priority interrupt level processing is completed, a return would be made to the interrupted subroutine for completion of processing for the first call. Thus, multiple calls to a single subroutine are processed without interfering with the integrity of data associated with any other call to the subroutine. (: 2-30 GA34-0022 Chapter 3. Interrupts and Level Switching c Introduction c Efficient operation of a central processor depends on prompt response to I/O device service requests. This is accomplished by an interrupt scheme that stops the current processor operation, branches to a device service routine, handles device service, then returns to continue the interrupted operation. One processor can control many I/O devices~ therefore, an interrupt priority is established to handle the more important operations before those of lesser importance. Certain error or exception conditions (such as a machine check) also cause interrupts. These are called class interrupts and are processed in a manner similar to I/O interrupts. Both I/O and class interrupts are explained further in the following sections. Interrupt priority is established by four priority levels of processing. These levels, listed in priority sequence, are numbered 0, I, 2, and 3 with level 0 having highest priority. Interrupt levels are assigned to I/O devices via program control. This provides flexibility for reassigning device priority as the application changes. Each of the four priority levels has its own set of registers. These consist of a level status register (LSR), eight general registers (RO-R7), and an instruction address register (lAR). Information pertaining to a level is automatically preserved in these hardware registers when an interrupt occurs. Processor level switching, under program control, may be accomplished by use of the Set Level Block (SELB) instruction. Details of this method are presented in a separate section of this chapter. I/O and class interrupts cause automatic branching to a service routine. Fixed locations in main storage are reserved for branch addresses or pointers which are referenced during interrupt processing. This storage allocation is shown in the section Automatic Interrupt Branching in this chapter. Interrupt masking facilities provide additional program control over the four priority levels. System and level masking are controlled by the Summary Mask and the Interrupt Level Mask Register. Device masking is controlled by the Device Mask. Manipulation of the mask bits can enable or disable interrupts on all levels, a specific level, or for a specific device. See Interrupt Masking Facilities in this chapter. Interrupt Scheme As previously stated, four priority interrupt levels exist. Each I/O device is assigned to a level, dependent on the application. When an interrupt on a given level is accepted, that level remains active until (l) a Level Exit (LEX) instruction is executed, (2) a Set Level Block (SELB) instruction causes a level switch, or (3) a higher priority interrupt is accepted. In the first two cases, the active level at the time is cleared. In the latter case, the processor switches to the higher level, completes execution (including a LEX instruction), then automatically returns to the interrupted-from level. This automatic return can be delayed by other higher priority interrupts. If an interrupt request is pending on the currently active level, it will not be accepted until after execution of a LEX instruction by the current program. If no other level of interrupt is pending when a Level Exit instruction is executed, the processor enters the wait state. In the wait state no processing is performed, but the processor can accept interrupts that are expected to occur. See Figure 3-1. Qass interrupts do not change priority levels. They are processed at the currently active level. If the processor is in the wait state when a class interrupt occurs, priority level 0 is used to process the interrupt. o Interrupts and Level Switching 3-1 Requests for interrupts Level 0 Levell Level 2 Level 3 __________________ ____________ ______ ~rl~ ~rl~ ~Il~ _________________________________ _________________________________________ _____________________________________________ nl.......-----------......II * Priority level processing Priority level 0 LEX LEX Priority level 3 -- -- - - - .........____..........."'"T'""'II~- - - - - - - - - - - - __ - - ___ - - ~ ; . . ; ; ; ; . L . . . . . L ................-----. - I--L...L...I....L.J _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ L .............,.....,~-------- - Priority level 2 . Priority level 1 --1--r-"T"'"I'--r"T""">......-.....-r-r--~ Wait state * This interrupt request cannot be honored until after a LEX instruction has been executed on level 3 to clear the previous interrupt service. Figure 3-1. Interrupt priority scheme Automatic Interrupt Branching Hardware processing of an interrupt includes automatic branching to a service routine. The processor uses a reserved storage area for branch information. The reserved area begins at main storage address 0000. The total size of the area depends on the number of interrupting devices attached. One word (two bytes) is reserved for each interrupting device and is related to a particular device by the device address. For example: device 00 causes a reference to location 0030, device 01 to location 0032, and so on. The device area begins at address 0030 (Hex); the reserved area is 0000 through 022F (Hex) if 256 devices (maximum number) are attached. These storage locations and contents are shown in Figure 3-2. Main storage address (Hex) Contents of word 022E ~ Device FF DDB pointer ;.~ 0032 0030 002E 002C 002A 0028 0026 0024 0022 0020 OOlE OOlC OOlA 0018 0016 0014 0012 0010 OOOE OOOC OOOA 0008 0006 0004 0002 0000 Figure 3-2. 3-2 GA34-0022 t ~;,. Device 01 DDB pointer Device 00 DDB pointer Reserved Reserved Reserved Reserved Reserved Reserved Soft exception trap SIA Soft exception trap LSB pointer Console interrupt SIA Console interrupt LSB pointer Trace SIA Trace LSB pointer Power failure SIA Power failure LSB pointer SVC SIA SVC LSB pointer Program check SIA Program check LSB pointer Machine check SIA Machine check LSB pointer Reserved Reserved Restart instruction word 2 Restart instruction word 1 Reserved storage locations ", ( -', The reserved storage locations are described as follows: Storage Location (Hex) 0000-0003 0004--0005 0006-0007 0008-0023 0024-002F 0030-022F Contents Restart instruction. Following IPL a forced branch is made to location 0000. Reserved. Reserved. Addresses used for class interrupts. The Level Status Block (LSB) pointer is the first address of an area where a level status block will be stored. The Start Instruction Address (SIA) points to the first instruction of a service routine. Reserved. Addresses used for I/O interrupts. The Device Data Block (DDB) pointer is the address of the first word of a device data block. This word is used to obtain the start instruction address for the service routine. See I/O Interrupts in this chapter. Note. The area reserved for I/O devices varies in size depending on the number of devices. The device address determines the fixed location to be accessed. For example: Interrupts for device 01 always vector to main storage address 0032. A device address is established by installing the appropriate connectors on the I/O feature card for the device. c I/O Interrupts Prepare I/O Device for Interrupt I/O device interrupt parameters are established via program control. The Operate I/O (IO) instruction initiates the device operation and in conjunction with the "Prepare" I/O command tells the device: 1. 2. If the device can interrupt. What priority level to use for interrupts. See Chapter 6 Instructions and Chapter 4 Input/Output Operations for details of the Operate I/O instruction. Execution of the Prepare command transfers a word to the addressed device that controls its interrupt parameters. This word has the format: Zero o Bits 0-10 11-14 15 c Level 10 11 bI 14 15 Contents Set to zeros. Level. A four-bit encoded field that assigns an interrupt priority level to the device (see note). Example: 0000 - level 0, 0001 - levell, 0010 -level 2, 0011 - level 3. Device mask or I-bit. This bit sets the interrupt mask in the device. When set to one, the device can interrupt. When set to zero, the device cannot request an interrupt. Note. The 4953 Processor does not recognize priority levels other than zero through three; therefore, bits 11 and 12 must always be set to zero or the interrupt is lost. An interrupting device is always able to accept and execute a Prepare command, even if it is presently busy or has an interrupt request pending from a previous command. This allows the software to change the device mask and interrupt level at any time. Any pending interrupt request is then serviced on the new interrupt level. Present and Accept I/O Interrupt The I/O device presents an interrupt request on its assigned priority level. This request is applied to the interrupt algorithm for acceptance determination. For an I/O interrupt to be serviced, the following conditions must exist: 1. 2. The summary mask must be on (enabled). The mask bit (Interrupt Level Mask Register) for the interrupting level must be on (enabled). 3. For I/O interrupts the device must have its Device Mask bit on (enabled). 4. The interrupt request must be the highest priority of the outstanding requests and higher than the current level of the processor. 5. The processor must not be in the stop state. Supervisor state is entered upon acceptance of all priority interrupts. Following acceptance, the device sends an interrupt ID word and a condition code to the processor. The condition code is placed in the even, carry, and overflow indicators for the interrupted-to level. The ID word is placed into register 7 of the interrupted-to level. The interrupt ID word consists of an interrupt information byte (lIB) and the device address. Bits 0-7 of this word contain the interrupt information; bits 8-15 contain the device address. See Chapter 4 for condition codes and interrupt information byte (lIB) details. Hardware causes the following events to occur after the processor receives the interrupt ID word and the condition code (Figure 3-3): • The processor hardware switches from the registers and status of the interrupted-from level to those of the interrupted-to level. • The interrupt ID word is placed in register 7 of the interrupted-to level. • The condition code is placed in LSR positions 0-2. • Supervisor state is entered (LSR bit 8 is set to one). • The processor executes an automatic branch. The device address is used by hardware to fetch the DDB pointer from reserved storage. The DDB pointer is placed in register 1 of the interrupted-to level. The DDB pointer is used by hardware to fetch the start instruction pointer. The Start Instruction Address (SIA) is loaded into the IAR of the interrupted-to level. • Execution begins on the new level. Interrupts and Level Switching 3-3 ------r------r------r------r----Device 01 interrupts on level 2 I I New level 2 registers I I I Main storage I Next instruction address I I Interrupted level 3 -------'-------L------~------4----I IAR3 I 8············0 I Interrupt ID I I I I DDB OiOO~(SlA) r L IAR2 II . I/O routme '--__. . . . . "1"0200£ 1-. ···f·····G :0240~""":""'G I I I I I I I I I I I I IAR3 0900 Figure 3-3. Example of I/O interrupt with automatic branching 3-4 GA34-0022 0900 ( --~ ; Oass Interrupts System error or exception conditions can cause seven types of class interrupts: 1. Machine check, caused by a hardware error. 2. Program check, caused by a programming error. 3. Pcvler/therma! "'.'~rning, c~used b~' ::! po'.~'.'er 0! the!!TIal irregulari ty . 4. Supervisor call, caused by execution of an SVC instruction. 5. Soft exception trap, caused by software. 6. Trace, caused by instruction execution (trace enabled in the current LSR). 7. Console, caused by a console interrupt when the optional programmer console is installed. c Machine check, program check, soft exception trap, and power/thermal warning are defined by bits in the processor status word. Software can refer to the processor status word for a specific condition and any related status information. See Processor Status Word in this chapter. Class interrupts do not cause a change in priority level. The interrupt is serviced on the level that lS actlve when the condition occurs. If the processor is in the wait state, the interrupt is serviced on priority level zero. Independent routines are used to handle each type of class interrupt regardless of priority level. All class interrupts cause the processor to enter supervisor state. Refer to a subsequent section, Present and Accept Qass Interrnpt, for details of the hardware processing. Programming Notes. 1. Two class interrupts (power/thermal warning and console) can be disabled by the summary mask. 2. If the optional programmer console is installed and Check Restart or Stop on Error are selected, machine check, power/thermal warning, and program check interrupts do not occur. See Programmer Console Feature in Chapter S. Priority of Class Interrupts Although class interrupts are serviced on the current priority level, they are serviced according to an exception condition priority. The following table lists the exception conditions in priority sequence with zero being the highest priority. Two exception conditions of the same priority, such as invalid storage address and specification check, may be reported to the PSW simultaneously. The table also shows the associated class interrupt vector for the exception conditions. c Priority Exception Condition 0 CPU control check I/O check Class Interrupt Routine Machine check I Invalid function (Note 1 ) 2 Privilege violate 3 Invalid function (Note 2) 4 Not applicable on 4953 Processor 5 Invalid storage address Specification check 6 Storage parity Machine check 7 Power warning Thermal warning Power / thermal warning 8 Supervisor call Supervisor call 9 10 Program check Invalid function (Note 3) Not applicable on 4953 Processor Soft exception trap 11 Stack exception 12 Trace Trace 13 Console Console Note 1. Caused by an illegal operation code or function combination. Note 2. A Copy Segmentation Register (CPSR) or Set Segmentation Register (SESR) instruction is attempted. The translator feature is not available in the 4953 Processor. Note 3. A floating-point instruction is attempted. The floatingpoint feature is not available on the 4953 Processor. Present and Accept Class Interrupt When a class interrupt occurs, it is serviced on the currently active level or on level zero (if in the wait state). Hardware processing of the interrupt causes the following: • • • • • Register contents are saved Supervisor state is entered (LSR bit 8 is set to one) Trace is reset (LSR bit lOis set to zero) Summary mask is disabled (LSR bit 11 is set to zero) An automatic branch is taken to a service routine. Each type of class interrupt has an associated LSB pointer and SIA in the reserved area of main storage (see Figure 3-2). Reference is made to the reserved area to: 1. 2. Store current level IAR, registers, and LSR into a level status block (LSB) in main storage. Automatically branch to a service routine by using the start instruction address (SIA). Note. Priority level zero is forced active when a class interrupt occurs in the wait state. The level zero LSB is stored into main storage. The in-process flag (LSR bit 9) is zero in the stored LSB. Interrupts and Level Switching 3-5 Contents of the level status block are as follows: Machine Check A machine check interrupt is caused by a hardware malfunction and is considered a system-wide inciden t. The three types are: Main storage address (LSB) pointer) Instruction address register Zero Level status register Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 +14 (Hex) Register 7 o 1. 2. 3. 15 The instruction address (contents of IAR) stored in the LSB depends on the type of class interrupt and is shown in the following chart. Storage parity check (pSW bit 08) CPU control check (pSW bit 10) I/O check (pSW bit 11) A level status block is stored, starting at the location in main storage designated by the machine check LSB pointer (contents of storage locations hex 0008 and 0009). The contents of the storage address register (SAR) are loaded into register seven. The machine check SIA (contents of storage locations hex OOOA and OOOB) is then loaded into the IAR, becoming the address of the next instruction to be fetched. Note. When the error condition occurs, the IAR contains the true address of the first word of the instruction; it is not incremented if the error occurs in the second or third word of a long instruction. Type of Class Interrupt Contents of IAR (Stored in LSB) Program Check A program check interrupt is caused by a programming error. The types are: Program check Address of instruction that caused the interrupt. 1. 2. 3. 4. Soft exception trap Supervisor call Trace Address of the next instruction. Console Power/thermal warning Machine check (with Sequence indicator off) Address of instruction that caused the interrupt. Machine check (with Sequence indicator on) Address of instruction that was being executed at the time of the error. Specification check (pSW bit 00). Invalid storage address (pSW bit 01). Privilege violate (pSW bit 02). Invalid function (pSW bit 04). A level status block is stored, starting at the location in main storage designated by the program check LSB pointer (contents of storage locations hex OOOC and OOOD). The contents of the storage address register (SAR) are loaded into register seven. The program check SIA (contents of storage locations hex OOOE and OOOF) is then loaded into the IAR, becoming the address of the next instruction to be fetched. Note. A program check interrupt condition on one priority level does not affect software on other levels. 3-6 GA34-0022 ( ~ c Power/Thermal Warning (PSW Bit 15) A power/thermal warning class interrupt is initiated by: 1. 2. c A power warning signal that is generated when the power line decreases to about 85% of its rated value. A thermal warning that occurs if the temperature limits inside the closure are exceeded. In both cases, the instruction address that is stored in the LSB points to the next instruction to be executed. A level status block is stored, starting at the location in main storage designated by the power failure LSB pointer (contents of storage locations hex 0014 and 0015). The power failure SIA (contents of storage locations hex 0016 and 0017) is then loaded into the IAR, becoming the address of the next instruction to be fetched. A power/thermal warning interrupt can occur when the system is running or in the wait state, assuming (1) the summary mask is enabled and (2) the programmer console is not set to Check Restart or Stop on Error. These interrupts are not taken by the processor if either of the two conditions are not met. If the optional battery backup unit is installed and a power warning occurs, PSW bit 15 remains on as long as power is supplied by the battery. If a thermal warning occurs, the processor will power down regardless of the battery backup unit. The minimum time before the processor powers down is 20 milliseconds. The IBM 4999 Battery Backup Unit is explained in a separate publication; IBM Series/l Battery Backup Unit Description, GA34-0032. Power/thermal warning interrupts are not taken by the processor until the first instruction is executed following a power-on reset, an IPL, or exit from stop state. Note. If the processor is in the wait state when the power/thermal condition occurs: 1. The interrupt is serviced on priority level O. The level Additional power/ thermal interrupts are disabled at this time because the summary mask is set to zero by the class interrupt. The instruction address stored in the LSB is unpredictable. o LSB is stored into main storage. 2. o Supervisor Call A supervisor call class interrupt is initiated by executing an SVC instruction. The SVC instruction is described in Chapter 6. A level status block is stored, starting at the main storage location designated by the supervisor call LSB pointer (contents of storage locations hex 0010 and 0011). The supervisor call SIA (contents of storage locations 0012 and 0013) is then loaded into the IAR, becoming the address of the next instruction to be fetched. Soft Exception Trap A soft exception trap interrupt is caused by software. The types are: 1. 2. Invalid function (pSW bit 4) Stack exception (pSW bit 6) These exception conditions may be handled by software; therefore, they do not constitute an error condition. A level status block is stored, starting at the location in main storage designated by the soft-exception-trap LSB pointer (contents of storage locations hex 0020 and 0021). The contents of the storage address register (SAR) are loaded into register seven. The soft-exception-trap SIA (contents of storage locations hex 0022 and 0023) is then loaded into the IAR, becoming the address of the next instruction to be fetched. Note. The contents of register seven are unpredictable. Trace The trace class interrupt provides an instruction trace facility for software debugging. Instruction tracing may occur on any priority level, and is enabled by the trace bit (LSR bit 10). The tracing occurs when bit 10 of the current LSR is set to one. When trace is enabled, a trace class interrupt occurs at the beginning of each instruction. A level status block is stored, starting at the location in main storage designated by the trace LSB pointer (contents of storage locations hex 0018 and 0019). The trace SIA (contents of storage locations hex 001A and 001 B) is then loaded into the IAR, becoming the address of the next instruction to be fetched. Note. After the LSB is stored, and before the next instruction is fetched, supervisor state is set on (LSR bit 8), trace is turned off (LSR bit 10), and the summary mask is disabled (LSR bit 11). Programming Note. When trace is enabled, a trace class interrupt occurs prior to executing each instruction. Hardware processing of the interrupt provides an automatic branch to the programmer's trace routine. To prevent retracing the same instruction, the program should exit the trace routine by using the Set Level Block (SELB) instruction with the inhibit trace (IT) bit set to one. The inhibit trace bit prevents a trace interrupt from occurring for the duration of one instruction (see SELB instruction in Chapter 6). A double trace of an instruction can also occur when the instruction is interrupted and must be reexecuted. For example: a class interrupt occurs during execution of a variable field length instruction. Under this condition, exit from the class interrupt routine should be via a SELB instruction with the inhibit trace bit set to one. The occurrence of any class interrupt or priority interrupt causes the trace bit (LSR bit 10) to be set to zero. This action permits tracing only problem state code. If the programmer desires to trace supervisor code, he must make provisions within the service routine to enable the trace bit. Interrupts and Level Switching 3-7 The following three conditions inhibit a trace class interrupt: 1. A Set Level Block (SELB) instruction sets the trace bit on and the in-process bit on in the LSR of a selected level lower than the current level; then, when the selected level becomes active, the first instruction executed is not preceded by a trace interrupt. 2. The programmer console is in diagnose mode and a stop instruction is encountered while tracing; then, when the Start Key is depressed, a trace interrupt does not occur prior to executing the first instruction. 3. When a level is exited by either a LEX or a SELB instruction and processing is to continue on a pending level, one instruction is executed on the pending level prior to sampling for a trace interrupt. Console A console interrupt function is provided when the optional programmer console is installed. To recognize the interrupt, the processor must have the summary mask enabled and be in the run state or wait state. A level status block is stored, starting at the main storage location designated by the console interrupt LSB pointer (contents of storage locations hex ODIC and OOID). The console interrupt SIA (contents of storage locations hex ODIE and OOIF) is then loaded into the IAR, becoming the address of the next instruction to be fetched. Note. If the processor is in the wait state when a console interrupt occurs, the interrupt is serviced on priority level O. Summary of Class Interrupts The following chart is a summary of class interrupt processing. Each class interrupt is fully explained in separate sections of this chapter. ~r exce~~on Error condItIon • • • • H HH LSB Set R7 Branch to service routine • • • • • • • • • • • • LSB Store SLA Recovery from Error Conditions Error recovery procedures, initiated by software, depend on several factors: 1. 2. 3. Application involved. Type of error. Number of recommended retries. The error class interrupt provides an automatic branch to a service routine. This routine can interrogate the PSW for specific error and status information. The routine can then initiate corrective action or retry the failing instruction(s). If an error occurs during a priority interrupt sequence, the priority level switch is completed before the error class interrupt is processed. This facilitates automatic register retention. A reset is generated by machine check class interrupts caused by an I/O check or a CPU control check. No reset is generated by program check or P9wer/thermal warning class interrupts. Error conditions along with error recovery information are presented in the following sections. Program Check A program check is caused by a programming error and initiates a program check class interrupt. Error retry depends on the application. All necessary parameters are made available for locating and, if required, correcting the invalid condition. There is no change to operands or priority level during a program check class interrupt. The stored LSB reflects conditions at the time the interrupt occurred and contains: • The contents of all general registers. • Status information (LSR contents). • The address of the failing instruction (IAR contents). The contents of the storage address register (SAR) are loaded into R7. The programmer must reference the PSW to determine the type of program check. Storage Parity Check A storage parity error initiates a machine check class interrupt. The error may occur when accessing a storage location that has not been validated since power on. Any retry procedure should include refreshing data in the failing location. Two unsuccessful retries are considered a permanent failure and the storage location should not be used. An IPL should be initiated. Class Interrupt Pointer Reg 7 Pointer Machine check 0008-0009 SAR OOOA-OOOB CPU Control Check Program check OOOC-OOOD SAR OOOE-OOOF Po wer / thermal warning 0014-0015 0016-0017 SVC 0010-0011 0012-0013 Soft exception trap 0020-0021 Trace 0018-0019 0OlA-OOlB Console 0OlC-OOlD 0OlE-001F A CPU control check occurs if hardware detects a malfunction of the processor controls. It is a machine-wide error and initiates a machine check class interrupt. A reset is generated to the channel, the I/O attachment features, and all attached I/O devices. The processor, sensor-based output points, and timer values are not reset. The generated reset (. ';. should clear the error condition, but validity of any previous' execution is not guaranteed. No retry is recommended. An IPL should be initiated. 3-8 GA34-0022 SAR 0022-0023 c I/O Check An I/O check condition occurs if a hardware error is detected that may prevent further communication with I/O devices. A machine check class interrupt is initiated and a reset is generated to the I/O attachment features, the channel, and all I/O devices. Error recovery from an I/O check depends on the sequence indicator setting (pSW bit 12). Sequence Indicator Set to Zero. The error occurred during an Operate I/O instruction. The address of the failing instruction (lAR contents) is available in the stored LSB. Retry should be attempted twice. After two unsuccessful retries, use of the device should be discontinued. Sequence Indicator Set to One. The error occurred during an interrupt or cycle steal operation. The instruction address (lAR contents) stored in the LSB is not related to the error. The sequence of events leading to the I/O check is lost, along with all pending interrupt requests within the devices. Retry is not recommended. Soft Exception Trap c A soft exception trap interrupt is the result of an exception condition that software may choose to handle dynamically. All necessary parameters are available to locate and correct the condition. The address of the instruction (lAR contents) causing the exception is preserved in the level status block in main storage. The processor is not reset. The programmer must reference the PSW to determine the soft-exception type. Processor Status Word The processor status word (PSW) is used to record error or exception conditions in the system that may prevent further processing. It also contains certain status flags related to error recovery. Error or exception conditions recorded in the PSW cause four of the possible seven class interrupts to occur. These are machine check, program check, soft exception trap, and power/thermal warning. See Qass Interrnpts in this chapter. The Copy Processor Status and Reset (CPPSR) instruction can be used to examine the PSW. This instruction stores the contents of the PSW into a specified location in main storage. The PSW is contained in a 16-bit register with the following bit representation: 04 Condition Specification check I nvalid storage address Privilege violate Not used Invalid function 05 06 07 08 09 10 11 12 13 14 15 Not used Stack exception Not used Storage parity check Not used CPU control check I/O check Sequence indicator Auto-IPL Not used Power/thermal warning Bit 00 01 02 OJ Class Interrupt Program check Program check Program check Remarks 1 __________._L.\;av Program check or Soft exception trap always zero Soft exception trap always zero Machine check always zero Machine check Machine check None None Power / thermal Status flag Status flag always zero Note 1 Note 1. The power/thermal warning class interrupt is controlled by the summary mask. Bit 00 Specification Check. Set to one if the storage address violates the boundary requirements of the specified data type. Bit 01 Invalid Storage Address. Set to one when an attempt is made to access a storage address outside the storage size of the sylitem. This can occur on an instruction fetch, an operand fetch, or an operand store. Bit 02 Privilege Violate. Set to one when a privileged instruction is attempted in the problem state (supervisor state bit in the level status register is not on). Bit 04 Invalid Function. Set to one by one of the following conditions: 1. Attempted execution of an illegal operation code or function combination. These are: Op code 00111 01000 01011 01011 01100 01110 01111 10110 11011 11101 Function All 0001,0010,0011,0101,0110,0111 0001, 1001 (When in supervisor state) 0101,0111 111 11000,11010,11011,11100,11110,11111 1X1XX, 01XXX, 1X011, 10001 All All 1100,1101,1110,1111 Note. The preceding illegal conditions cause a program check class interrupt to occur. 2. o The processor attempts to execute reserved operation codes or function combinations. These are: Op code 00100 01011 Function All 0011, 1011 (When in supervisor state) Note. The preceding condition causes a soft-exception-trap class interrupt to occur. Interrupts and Level Switching 3-9 Bit 06 Stack Exception. Set to one when an attempt has been made to pop an operand from an empty main storage stack or push an operand into a full main storage stack. A stack exception also occurs when the stack cannot contain the number of words to be stored by a Store Muliple (STM) instruction. Bit 08 Storage Parity. Set to one when a parity error has been detected on data being read out of storage by the processor. This error may occur when accessing a storage location that has not been validated since power on. Bit 10 CPU Control Check. A control check will occur if no levels are active but execution is continuing. This is a machine-wide error. (See I/O check note.) Bit 11 I/O Check. Set to one when a hardware error has occurred on the I/O interface that may prevent further communication with any I/O device. PSW bit 12 (sequence indicator) is a zero if the error occurred during an Operate I/O instruction and is set to one if the error occurred during a non-DPC transfer. The sequence indicator bit is not an error in itself but reflects the last interface sequence at any time. An I/O check cannot be caused by a software error. (See note.) Note. The hardware LSB consists of the following hardware registers for the selected level: 1. 2. 3. Instruction address register Level status register Eight general registers (0-7) The system programmer should become thoroughly familiar with other effects on the processor caused by execution of the SELB instruction. These effects are determined by three factors: 1. 2. 3. The current execution level. The selected level specified in the SELB instruction. The state of the in-process flag (Bit 9 of the LSR) contained in the main storage LSB. Note. Interrupt masking, provided by the summary mask and the interrupt level mask register, does not apply to program controlled level switching. The main storage LSB and the location of the in-process flag bit are shown in the following diagram: Main storage effective address Note. The machine check class interrupt initiated by a CPU control check or I/O check causes a reset. The I/O channel and all devices in the system are reset as if a Halt I/O (channel directed command) had been executed. The processor, sensor-based output points, and timer values are not reset. Bit 12 Sequence Indicator. This bit reflects the last I/O interface sequence to occur. See "I/O Check" described above. Bit 13 Auto IPL. Set to one by hardware when an automatic IPL occurs. Bit 15 Power Warning and Thermal Warning. Set to one when these conditions occur (see Power/Thermal Warning class interrupt in this chapter). The power/thermal class interrupt is controlled by the summary mask. IAR Zero LSR Register 0 Register 1 Register 2 Register Register Register Register EA+14 (Hex) 1* r 3 , , 4 5 6 Register 7 *In-process flag (bit 9) o 1 off = on Execution of the SELB instruction may result in level switching or a change in the pending status of a level as described in the following sections. Program Controlled Level Switching Level switching under program control may be accomplished by using the Set Level Block (SELB) instruction. This instruction is covered in detail in Chapter 6,Instrnctions, and in general it will: • Specify the location of a level status block (LSB) at an effective address in main storage. • Specify a selected priority level associated with the main storage LSB. • Load the main storage LSB into the hardware LSB for the selected level. 3-10 GA34-0022 ( .~. . .1" c Selected Level Lower Than Current Level and In-process Flag On These conditions cause the selected level to be pending. The main storage LSB is loaded into the hardware LSB for the selected level. Execution of a LEX instruction on the current level causes the selected level to become active providing no higher priority interrupis are being requeSltal. LEX Load LSB Selected level (-- 1I-- - - - - - Pe;dj;;g- - - - - - - - +--r---r--~-r-~-r--'-~--r~-""......, \ .... ., Ii.. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ..........--'---'-......................................---a.---'--'L.....-"'--"'---' Selected Level Equal to Current Level and In-process Flag On These conditions cause the selected level to become the current level. The main storage LSB is loaded into the hardware LSB for the selected level. ~ c Current and Selected level 9 I I Selected Level Higher Than Current Level and In-process Flag On These conditions cause the selected level to become the current level. The main storage LSB is loaded into the hardware LSB for the selected level. This is a level switch to the higher (selected) level and causes the lower level to be pending. Selected level r-r--r--~-r--r--,--r--r--r~---~------~------------ Current level L...-"--L--'--~-'-~--L.--L--L-.&._ _ _ _ _ _ _ _...... ____ -I ~n~n! _ _ _ _ _ ...J o Interrupts and Level Switching 3-11 Selected Level Lower Than Current Level and In-process Flag Off These conditions cause the selected level to be not pending. The main storage LSB is loaded into the hardware LSB for the selected level. Curren t level Load LSB r - - - - - - - - - - - - 1(-' Selected level L _ _ _ .!e!!..d~ _ _ _ _ _ _ ~ ) Not pending -" Selected Level Equal to Current Level and In-process Flag Off These conditions cause an exit from the current level. This exit is identical to executing a LEX instruction with the exception that the main storage LSB is loaded into the hardware LSB for the selected level. See LEX instruction in Chapter 6. , I ' Selected Level Higher Than Current Level and In-process Flag Off The main storage LSB is loaded into the hardware LSB for the higher (selected) level. r--------------~~~----------------, J ____ ~o!"'p~~~ _ _ _ _ _ _ ~ Selected level L _ _ _ _ _N~t E.e~d~g_ _ _ _ _I~ Load LSB ( 3-12 GA34-0022 -~ .. -' c Interrupt Masking Facilities Interrupt Level Mask Register Three levels of priority interrupt masking are provided to the programmer for control of the interrupt processing. These consist of: The interrupt level mask register is a 4-bit register used for control of interrupts on specific priority levels. Each level is controlled by a separate bit of the mask register as shown below: 1. 2. 3. Summary Mask (LSR bit 11) Interrupt Level Mask Register Device Mask (I-bit) Each masking facility has specific control as explained in the following sections. IntpTTlIpt l.pvp\ M::t~k Regi~ter Bit position o I I Priority level o 1 2 3 I I 123 Summary Mask The summary mask provides a masking facility for priority interrupts and certain class interrupts. The state of the summary mask (enabled or disabled) is controlled by bit 11 in the level status register (LSR) of the active priority level. When bit 11 is set to zero, the summary mask is disabled and prevents (1) all priority interrupts regardless of priority level, and (2) power/thermal and console class interrupts. All other class interrupts are not masked. When bit 11 is set to one, the mask is enabled and the interrupts are allowed. The summary mask is disabled and enabled as follows: c • Disabled (Set to Zero) 1. When a Supervisor Call (SVC) instruction is executed, the summary mask for the active level is disabled. 2. Execution of a Disable (DIS) instruction, with bit 15 of the instruction equal to one, causes the summary mask for the active level to be disabled. 3. All class interrupts disable the active level summary mask. 4. The summary mask for a selected level is disabled by executing a Set Level Block (SELB) instruction with bit 11 of the LSR to be loaded equal to zero. S. The summary mask bits for priority levels 1-3 are set to zero by a system reset, power-on reset, or IPL. • Enabled (Set to One) 1. Execution of an Enable (EN) instruction, with bit 15 of the instruction equal to one, causes the active level summary mask to be enabled. 2. The summary mask for a selected level is enabled by executing a Set Level Block (SELB) instruction with bit 11 of the LSR to be loaded equal to one. 3. The level zero summary mask is enabled by a system reset, power-on reset, or IPL. 4. The summary mask for the interrupted-to level is enabled by a priority interrupt. With a bit position set to one, the corresponding priority level is enabled and permits interrupts. With a bit position set to zero, the corresponding priority level is disabled. The Set Interrupt Mask Register (SEIMR) instruction is used to control bit settings in the interrupt level mask register. The Copy Interrupt Mask Register (CPIMR) instruction may be used to interrogate the register. Note. All levels are enabled (set to one) by a system reset, power-on reset, or IPL. Device Mask (I-bit) Each interrupting device contains a one-bit mask called the device mask or interrupt bit (I-bit). Interrupts by the device are permitted when its device mask is enabled (set to one). With the device mask bit disabled (set to zero), that device cannot cause an interrupt. The device mask is controlled by a Prepare command in conjunction with an Operate I/O instruction. See Chapter 6, Instructions, and Chapter 4, Input/Output Operations. Note. If the processor is in the wait state, the summary mask is enabled or disabled as defined by bit 11 in the LSR of the last active priority level. C" = Interrupts and Level Switching 3-13 c t 3-14 GA34-0022 Chapter 4. Input/Output Operations c Input/output (I/O) operations involve the use of input/output devices. These devices are attached to the processor and main storage via the I/O channel with the channel directing the flow of information. The I/O channel can accommodate a maximum of 256 addressable devices. The general data flow is shown in Figure 4-1. Processor Channel Controls I/O Device 01 Main Storage I/O Device FF I/O Channel Figure 4-1. Block diagram of Series/1 Model 3 system The channel supports three basic types of operations: c • Direct Program Control (DPC) Operations - An immediate data transfer is made between main storage and the device for each Operate I/O instruction. The data may consist of one byte or one word. The operation mayor may not terminate with an interrupt. • Cycle Steal Operations - An Operate I/O instruction can initiate cycle-stealing data transfers of up to 65,535 bytes between main storage and the device. Cycle steal operations are overlapped with processing operations. Word or byte transfers, DCB chaining, burst mode, and program controlled interrupt can be supported. All cycle stealing operations terminate with an interrupt. • Interrupt Servicing - Four preemptive priority interrupt levels are available to facilitate device service. The device interrupt level is assignable by the program. In addition, the device interrupt capability may be masked under program control. Interrupt requests, along with cycle steal requests, are presented and polled concurrently with DPC and cycle-steal data transfers. The channel provides comprehensive error checking including time-outs, sequence checking, and parity checking. Error, exception, and status reporting are facilitated by: (1) recording condition codes in the processor during execution of Operate I/O instructions, and (2) recording condition codes and an Interrupt Information Byte (lIB) in the processor during interrupt acceptance. Additional status words may be used by the device as necessary to describe its status (see I/O Condition Codes and Status Information in this chapter). o Input/Output Operations 4-1 Operate I/O Instruction (~) The Operate I/O instruction initiates all I/O operations from the processor. It is a privileged instruction and is independent of specific I/O parameters. The generated effective address points to an immediate device control block (lOCB) in main storage. The IOCB consists of two words that contain an I/O command, a device address, and an immediate data field. For DPC operations, the immediate data field is used as a device data word. For cycle steal operations, the immediate data field points to a device control block (OCB) that provides additional information needed for the operation. For more details of the Operate I/O Instruction refer to Chapter 6. Operate I/O Instruction o 0 Effective address IDCB Device address Command o 7 8 Immediate data field 15 16 31 ~~--------------~v--------------~ I Cycle steal operations I r-----------------------------------~ I + DCB 1 1 *Indirect addressing bit 4-2 GA34-0022 ( " ", Immediate Device Control Block (IDCB) The location in storage specified by the Operate I/O instruction contains the first word of the IDCB. The IOCB contains an I/O command that describes the specific nature of the I/O operation. This command is used by the channel for execution of the operation. The IOCB must always be on a word address boundary and has the following format: I I o 7 8 IDeB (immediate device control block) Command field Device address field 15 I Immediate data field 16 c 31 Command field (bits 0- 7) Channel directed. If this bit is equal to one, the I/O Bit 0 command is directed to the channel rather than to a specific device. The Halt I/O command is the only valid channel directed command. Any other command with bit 0 set to one causes a command reject exception condition. Bit 1 Read/Write. If this bit is equal to one, the data contained in the immediate field is transferred to the addressed I/O device. If this bit is equal to zero, the immediate field contains the data received from the I/O device at the conclusion of the 10 instruction. Bits 2-3 . Function. This field specifies the general type of I/O operation to be performed (see Figure 4-2). Modifier. This field contains four bits for further Bits 4-7 specification of a function, if required (see Figure 4-2). Device address field (bits 8-15) This byte contains the I/O device address. The address range is 00 through FF (hex). Immediate data field (bits 16-31) This field contains a device data word for DPC operations. It contains the address of a device control block for cycle steal operations. Figure 4-2 shows the relationship of the IDCB and the Operate I/O instruction. It also contains a chart of the various I/O commands. The Start command and the Start Cycle Steal Status command are used to initiate cycle steal operations. The remaining commands are used for DPC operations only. c Input/Output Operations 4-3 Operate I/O Instruction R2 \0 o 0 \ Address 1 0 1\ 0 0 0 \ o 4 5 7 8 15 16 1011 12 31 Effective address l IDCB (immediate device control block) Immediate field 31 15 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 Read 01 Read 10 Read sta tus 10 Read status 11 00 Write 01 Write 10 Control 10 Control 10 Control 11 Start 11 Start II Channel XXXX XXXX 0000 XXXX XXXX XXX X 0000 XXXX 1111 XXXX 1111 0000 Hex Specific command OX IX 20 2X 3X 4X 5X 60 6X 61; 7X 71-' FO Read DPC Read DPC Read ID DPC Read status DPC Unused Unused *** Write DPC Write DPC Prepare DPC Control DPC Device reset DPC Cycle stcal Start Start cycle steal status Cycle steal Halt I/O Channel Type of operation I ~ *Indirect addressing bit **Modifier XXXX is device dependent. Other modifiers are system defined. ***To avoid future code obsolescence, this command format must not be used. Figure 4-2. IDeB and I/O commands ( 4-4 GA34-0022 c Device Control Block (DCB) The DCB words have the following meanings: TWs section describes the device control block that is used for a cycle steal operation. The actual cycle steal operation is explained in a later section of this chapter. The DCB is an eight-word control block residing in the supervisor area of main storage. It contains the specific parameters of a cycle steal operation. The device fetches the DCB using the cycle steal mechanism. The format of the DCB is shown in Figure 4-3. Control word Word Bit 0* Bit 1* Bit 2 DCB (device L'ontrol block) Control word II ~ Device parameter word 1 Bit 3 Device parameter word 2 Bit 4* 3 Device parameter word 3 4 Device parameter word 4 5 Device parameter word 5 Bits 5-7 Bits 8-15 Count Data address 7 c () *Chaining, PCI, and SE are device options that are available on a device feature basis. Any bit not used by the device should be set to zero although it is not checked by the device. Refer to the Cycle-Steal Device Options section of this chapter. 15 Control word format (DCB word 0) Addr key \lodlfier hils ------ II IlbkL:~;'~,:;~~::ePliO" 1 ] 3 ../ 5 7 14 S - Chaining flag. If this bit is equal to one, a DCB chaining operation is indicated. Programmed controlled interrupt (PCI). If this bit is equal to one, the device presents a programmed comroiieu ini.errUl'l (cCI) at. the C0iiiplctivii Gf th::: DCB fetch. Input flag. The setting of this bit tells the device the direction of data transfer. 0= Output (main storage to device) 1 = Input (device to main storage) For bidirectional data transfers under one DCB operation, this bit must be set to one. For control operations involving no data transfer, this bit must be set to zero. Reserved. This bit must be set to zero to avoid future code obsolescence. Suppress exception (SE). If this bit is equal to one, the device is allowed to suppress the reporting of certain exception conditions. The device can then take alternative action depending on the condition. Cycle steal address key. Not used on the 4953 Processor. Modifier. These are device dependent bits with one exception. When a device uses burst mode, it is specified in bit 15. These bits may be used for functions that are unique to a particular device. I~ 15 Device Parameter Words 1-2 These parameter words are device-dependent control words and are implemented as required. Refer to the individual device publications for definition. (SH)' LRcscrl'cd Input flax Proxram controlled intcrmpt (PCI) * L...-_ _ _ _ _ _ Chainint( flat( * * Device op tion bits Figure 4-3. Device control blo.:.:k Device Parameter Word 3 When PCI is specified, the high-order byte (bits 0-7) of this word is used for a DCB identifier. The device places the identifier in the interrupt information byte when the PCI is processed. The low-order byte (bits 8-15) is always device dependent. The high-order byte is device dependent when PCI is not specified. c Input/Output Operations 4-5 Device Parameter Word 4 If suppress exception (SE) is used by a device, this word specifies a 16-bit main storage address called the status address. This address points to a residual status block that is stored by the device following completion of the DeB operation. If suppress exception is not used by a device, a residual status block is not stored. In this case, parameter word 4 is device dependent. Refer to Cycle-Steal Device Option in this chapter. Read IDCB (immediate device control block) Command field o Device address field 0 0 X X X X X X X X X X X X X ~, ______~ _____ J7 ~, ______~ ____~J5 OX OO-FF 01 IImmediate data field Device Parameter Word 5 If the DeB chaining bit (bit 0 of the control word) is equal to one, this word specifies a 16-bit main storage address of the next DeB in the chain. If chaining is not indicated, this parameter word is device dependent. Count The count word contains a 16-bit unsigned integer represent· ing the number of data bytes to be transferred for the current DeB. Count is specified in bytes with a range of 0 through 65,535. The count specification must be even for word-only devices. Data Address This word contains the starting main storage address for the data transfer. Data word 16 This command transfers a word or byte from the addressea device to the data word of the IDCB. If a single byte is transferred, it is placed in bits 24-31 of the data word with bits 16-23 set to zeros. Correct parity is always maintained and checked for both bytes on the I/O channel. The individual devices may use either the OX or IX type of read command. The two commands operate the same in the channel. Read ID IDCB (immedia te device control block) Command field 001 o ~' Device address field 0 0 0 0 0 X X X X X X X X ______ Programming Considerations When Using the OCB Only those words required for the cycle stealing operation are fetched by the device and they may be fetched in any order. Contents of the words must be specified correctly; if not, the device records a DCB specification check in the interrupt status byte and terminates the cycle steal operation with an exception interrupt. 2. The DeB address (in the DeB), the chain address, and the status address must be even (word boundary). If the DeB address is odd, the device records a command reject condition code and terminates the cycle steal operation. An odd chain address or status address results in a DCB specification check. 31 y~ ____ ~ 7 8 ~' ____ 20 1. ~~ ____ 15 ~J OO-FF IImmediate data field Data word 16 31 This command transfers an identification (lD) word from the device to the data word of the IDCB. The device identification word contains physical information about the device and may be used to determine the devices that are attached to the system. This word is not related to the interrupt ID word associated with interrupt processing. The device ID word format is: Note. Condition code and status recording are explained in detail in a separate section of this chapter. I/O Commands This section describes each I/O command and shows the related IDCB. The command field (bits 0-7) of the IDCB contains the binary value of the command. An X in this field means the value is device dependent. Assigned code a Bits 0-12 Bit 13 Bit 14 Bit 15 4-6 GA34-0022 12131415 Unique identification code for the device Zero - not a controller device or the device does not report delayed command reject One - controller device or any device that reports delayed command reject Zero - not a cycle steal device One - cycle steal device Zero - IBM device One - OEM device ,, c Note. A controller may control more than one I/O device and is not directly addressable, but is not transparent to software. That is, the controller may cause busy or exception conditions as opposed to those caused by an attached I/O device. Prepare IDCB (immediate device control block) Command field o ~,- ____~____~J Read Status IDCB (immediate device control block) ____~~_____}5 OO-FF IImmediate data field Device address field 001 0 X X X X X X X X X X X X ______~______~7 ~, ______~----~}5 2X OO-FF rlmmediate data field Data word 16 31 This command transfers a device status word from the device to the data word of the IOCB. Contents of the status word are device dependent. Level Zeros 16 26 27 30 31 This command transfers a word (to the addressed device) that controls the device interrupt parameters. The word is transferred from the immediate data field of the IDCB in the format shown. A priority interrupt level is assigned to the device by the level field. The I-bit (device mask) controls the device interrupt capability. If the I -bit equals 1, the device is allowed to interrupt. If the I-bit equals 0, the device cannot interrupt. See Prepare I/O Device for Interrnpt in Chapter 3. Note. The IBM 4953 Processor does not recognize a priority level other than 0-3. Lost interrupts result if a device is prepared for a level other than 0-3. Write c ~, 60 Command field ~, Device address field 1 1 0 0 0 0 0 X X X X X X X X IDCB (immediate device control block) Command field Control Device address field o lOX X X X X X X X X X X X X O'-____~~----_J ~, ______~----~!5 o OO-FF 4X 5X IDCB (immediate device control block) Command field Device address field 1 lOX X X X X X X X X X X X ~'------Vv------~! ~'-____-vv______~}5 6X OO-FF Data word 16 31 This command transfers a word or byte to the addressed device from the data word of the IDCB. The individual device may use either format of the command. If a single byte is to be transferred, it must be placed in bits 24-31 of the data word and bits 16-23 must be set to zero. A byte oriented device may ignore bits 16-23 (including the parity bit on the I/O channel) but these bits should be zeros to avoid future code obsolescence. Note. Both bytes of the IDCB data word are fetched by the channel and placed on the I/O data bus (in good parity) even if not required by the device. Ilmmediate data field Data word 16 31 This command initiates a control action in the addressed device. A word, or byte, transfer from the data word of the IDCB to the addressed device mayor may not occur, depending on device requirements. If a single byte is to be transferred it must be placed in bits 24-31 of the data word and bits 16-23 must be set to zero. Note. Both bytes of the IOCB data word are fetched by the channel and placed on the I/O data bus (in good parity) even if not required by the device. c Input/Output Operations 4-7 Start Cycle Steal Status Device Reset Command field Command field Device address field o 1 101 1 1 X X X X X X X X ~~_ _ _ _ _ _~y_ _ _ _ _ _~l ~~ ______ ~v_ _ _ _ _ _~}5 Device address field 01111111XXXXXXXX () 7 '~----v-----~ 6F (: IDCB (immediate device control block) IDCB (immediate device control block) OO-FF 8 ~~ 7F IImmediate data field ____ 15 -v____~J OO-FF 11mmediate data field DCB address Zeros 31 16 This command resets the addressed device. A pending interrupt from this device (or a busy condition) is cleared. The device mask (I-bit) is not changed. A device must always accept and execute this command. There is no change to the assigned priority level for the device. The residual address (device status) and output sensor points are not affected. Parity checking of the IDCB data word is not performed. 16 31 This command initiates a cycle steal operation for the addressed device. Its purpose is to collect status information from the addressed device. The second word of the IDCB is transferred to the device and contains a 16-bit lOgical address of a device control block (DCB). See Start Cycle Steal Status Operation in this chapter. Halt I/O Start IDCB (immediate device control block) Command field IDCB (immediate device control block) 1 1 1 100 0 0 Command field ~,-_____v~____~7 o ~, Device address field 1 1 1 X X X X X X X X X X X X ______ ~ ______l ~' ______ 8 15 FO ~y_ _ _ _ _ _~}5 I OO-FF 7X Device address field Immediate data field 31 16 IImmediate data field DCB address 16 31 This command initiates a cycle steal operation for the addressed device. The second word of the IDCB is transferred to the device. It contains a 16-bit logical storage address of a device control block (DCB) to be used by the device. See Cycle Steal in this chapter. This is a channel directed command that causes a halt of all I/O activity on the I/O channel and resets all devices. No data is associated with this command. All pending device interrupts are cleared. Device priority-interrupt-Ievel assignments and device masks (I-bits) are unchanged. The residual address (device status) and output sensor points are not affected. Notes. I. 2. 4-8 GA34-0022 The channel is always able to accept and execute this command. Halt I/O is the only valid channel directed command. c DPe Operation Notes. A DPC operation causes an immediate transfer of data or control information to or from an I/O device. An Operate I/O instruction must be executed for each data transfer and causes the following events to occur (refer to Figure 4-4). 1. 1. 2. 3. 4. 2. The Oper~te I/O i!!.strl..!ct!o!!. r0!ntl: to ~n TnrR in main storage. The I/O channel uses the IOCB to select the addressed device and to determine the operation to perform. II The I/O channel sends data to the device from main storage, or from the device to main storage. II The device sends an 10 instruction condition code to the level status register (LSR) in the processor. m The OPC operation may end with a priority interrupt if the device has this capability. Refer to I/O Interrnpts in Chapter 3. There are two types of condition codes: the first is an I/O instruction condition code and is available Immedlateiy after compielioll of all Optaak I/O ifl~liuc tion; the second is an interrupt condition code and is presented upon acceptance of a priority interrupt. The code significance is different for the two cases. Refer to I/O Condition Codes and Status Infonnation in this chapter. m Operate I/O Instruction Llolloool R2 Address I () 0 \_ Effective address m C Hex Command IDCB immediate field OX, IX 20 2X 4X,5X Read Read ID Read status Write Prepare Control Device reset Data (word or byte) Device ID word Device status word Data (word or byte) Interrupt parameters Data (word or byte) Zero 60 6X 61" Immediate field Device address ~_ _ _ _ _ _ _ _ _ _ _ _ _ ~_ _ _ _ _ _ _ _ _ _ _ _ _ _J 7 H ~~ 15 10 ______________ ~_ _ _ _ _ _ _ _ _ _ _ _ _ _J 31 I/O device II II (note I) 0 '1 - 1 SS t Note 1 10 instruction CC Ii) LSR Bit () even indicator Hit I carry indica tor Bit 2 overflow indicator hgure 4-4. Direct program control I/O operation c Input/Output Operations 4-9 Cycle Steal The cycle steal mechanism allows data service to or from an I/O device while the processor is processing instructions. This overlapped operation allows multiple data transfers to be started by one Operate I/O instruction. The processor executes the Operate I/O instruction, then continues processing instructions while the I/O device steals main storage data cycles when needed. The channel resolves contention among multiple devices requesting cycle steal transfers. The operation always ends with a priority interrupt from the device. The cycle steal operation includes certain capabilities that are provided on a device feature basis: 1. Burst mode 2. OC B chaining 3. Programmed controlled interrupt (PCI) 4. Suppress exception (SE) 5. Storage addresses and data transfers by byte or word See the Cycle-Steal Device Options section of this chapter for details of these facilities. All cycle steal operations terminate with a priority interrupt, providing, the device has executed a successful Prepare command, with the device mask (I-bit) enabled. If the device mask is disabled, the interrupt presentation is blocked and the device remains busy until (1) the condition is cleared by a reset, or (2) the proper Prepare command is executed. All cycle steal operations are started by an Operate I/O instruction that points to an IDCB. The immediate data field of the IOCB contains the address of a device control block (DeB). The OCB is fetched by the device using the cycle-steal mechanism. Within the DeB are specific parameters of the cycle steal operation. See Device Control Block in this chapter. There are two types of cycle steal commands: • Start • Start Cycle Steal Status. The command modifier (X) is device dependent. The OCB address always specifies a word boundary and is the starting storage address of the OCB. This address is used by the device to fetch the OCB, using the cycle steal mechanism. A cycle steal operation is presented in the following chart. Use Figure 4-5 in conjunction with this chart. Condition codes used in the chart are fully explained in the section I/O Condition Codes and Status Information in this chapter. Note. An I/O device must be properly prepared (using a Prepare command), before it is allowed to interrupt. Cycle steal major steps Start cycle steal Device fetches OCB Data transfer Termination (no error condition) Termination (Exception condition) Program Controlled interrupt Suppress exception Command field Device address field 0 1 I I X X X X X X X X X X X X 0 15 7 8 .... " .... 7X " OO-FF IImmediate data field DCB address 31 GA34-0022 1. Device completes the current DCB operation but does not present an interrupt request. 2. Device fetches next DCB in the chain. 1. Device fetches DCB (PCI bit = 1). 2. Device initiates an interrupt and sends an interrupt ID word and interrupt condition code 1 (PCI). 1. Device completes current operation. 2. Device stores status at the main storage location defined by DCB parameter word 4. II IDCB (immediate device control block) 4-10 II Note. Other events that might occur during the cycle steal operation are: Start Operation 16 Remarks 1. Execute 10 instruction. 2. IOCB contains Start command and points to a DCB. The DCB address is sent to the device. 3. Device presents condition code 7 (bits 0-2 in the LSR).1iI 1. Device uses cycle steal mechanism to fetch OCB. 1. Data is transferred to or from the device in word or byte format.1D 2. Transfer continues until count in OCB is exhausted. 1. Device presents interrupt request. 2. Channel polls I/O attachment feature and accepts request. 3. Device sends interrupt ID word and interrupt condition code 3 (device end). 1. Device presents interrupt request. 2. Channel polls I/O attachment feature and accepts request. 3. Device sends interrupt ID word and interrupt condition code 2 (exception). 11 Chaining A cycle steal operation begins after successful execution of the Start command. The IDCB, pointed to by an Operate I/O instruction, has the format: ( I " .~ j Operate I/O Instruction c 100 Effective address ! 0200 IOCB ICommand Device address DCB address 0500 o 7 8 15 16 31 , LSR I 0 I 2 3 ~D m 15 Device '-y-' m c DeB 05 00 II Control word ~ ~ 05 OA 0600 Count 05 OE 0800 m Data area ~-l ()~()() I I ::::;::: -1 I .::~ II I I I I I I L_ - Chained DCB --~ 0600 --.... -,-, *Indirect addressing bit o Figure 4-:". Fxamp\e of cycle steal control information Input/Output Operations 4-11 Start Cycle Steal Status Operation The purpose of this operation is to obtain data from the device if the previous cycle steal operation terminates due to an error or exception condition. The operation is initiated by a Start Cycle Steal Status command. The IOCB format is: lOeB (immediate device control block) Command field Device address field o 7 '~----~----~~ 7F 8 1. 2. 3. 4. s. X X X X X X X X 0111111 Programming Note. Concerning the OCB for the start cycle steal status operation: 15 ~~----~~----~~ OO-FF 6. rmmedMte data field DeB address 16 31 This command uses a special DeB format with some words and fields to set to zeros (see Figure 4-6). Word DeB (device control block) Control word o 0 0 1 0 010 0 010 0 Not used (zeros) 3 Not used (zeros) 4 Not used (zeros) 5 Not used (zeros) 6 Byte count 7 Data address o Bits designated as zero are not checked by hardware (see Figure 4-6). The count is specified in bytes. The maximum count is device dependent. The validity of a count value less than the maximum value is device dependent. If the maximum count is exceeded, or a count value is specified that indicates the partial storing of a word length parameter, the device records a DeB specification check in the ISB and terminates the operation. An odd data address also results in a DeB specification check. Data is transferred to main storage starting at the data address specified in the DCB. This data consists of residual parameters and device dependent status information and has the following format: Word 0 Resid ual address Word 1 Device cycle steal status word 1 Word 2 Device dependent status word 0 0 0 0 0 0 Not used (zeros) 2 () 0 ,V 15 Figure 4-6. DeB for start cycle steal status operation 15 V ! ,, Residual Address. This word contains the main storage address of the last attempted cycle steal transfer associated with a Start command. It may be a data address, a DCB address, or a residual-status-block address. It is updated to the current cycle-steal storage address upon execution of cycle steal transfers. For word transfers, the residual address points to the high-order byte of the word. If an error occurs during a start cycle steal status operation, this address (as contained within the device) is not altered. Device reset, Halt I/O, machine check, and system reset have no effect on the residual address in the device. It is cleared by a power-on reset. Following a power-on reset the residual address is: • 0000 (Hex) for a byte-oriented device . • 0001 (Hex) for a word-oriented device. (~ 4-12 GA34-0022 c Device Cycle-Steal-Status Word 1. This word contains the residual byte count of the previous cycle steal operation associated with a .start command. The byte count is initialized by the count field of a OCB associated with a Start command, and is updated as each byte of data is successfully transferred via a cycle steal operation. It is not updated by cycle-steal transfers into the residual status block. The residual byte count is not altered if an error occurs during a start cycle steal status operation. It is reset by (l) power-on reset, (2) system reset, (3) device reset, (4) Halt I/O, and (5) machine check condition. Note. The contents of the device cycle-steal-status word 1 are device dependent if the device does not: (l) implement suppress exception (SE), or (2) store a residual byte count as part of its cycle-steal status. Device Dependent Status Words. The number and contents of these words are specified by the individual device. Three conditions can cause bits to be set in the device dependent status words (refer to individual device publications). 1. 2. 3. Execution of an I/O command that causes an exception interrupt. Asynchronous conditions in the device that indicate an error, exception, or a state condition. As defined by the individual device. The bits are reset as follows: c 1. For the first condition listed above, the bits are reset by the acceptance of the next I/O command (except Start Cycle Steal Status) following the exception interrupt. These bits are also reset by a power-on reset, system reset, or execution of a Halt I/O command. 2. For the second condition, the bits are reset on a device dependent basis. 3. For the third condition, the bits are reset as defined by the individual device. Cycle-steal Device Options The I/O channel supports operations such as burst mode and chaining when required by individual devices. Bits in the OCB control word are used to activate these operations. Refer to the individual device publications for the device options used. The following sections explain the operations. Burst Mode o Burst mode, when used by a device, is specified in bit 15 of the OCB control word. If bit 15 is equal to one, the transfer of data takes place in burst mode. This mode dedicates the I/O channel to the device until the last data transfer for the OCB is completed. Cycle steal interleave, by other devices, is prevented. Burst mode also prevents any priority interrupt request from being accepted by the processor. The maximum burst rate for the 4953 channel is 1.332 megabytes per second. Chaining The purpose of chaining is to allow the programmer to sequence an I/O device through a set of operations by using a chain of OCBs. Bit 0 of the OCB control word (when set to one) indicates a chaining operation. This means that the chained OCB, fetched by the device, is interpreted as a new operation (or function) to be performed. The DCB may hp p(l11::l1 to hllt not ::l rontinll::ltl0n of thp onpr::ltlon <:npri_ - - --1.---- . . , ---. ----.- ---------.-.---- - - , ---- -r-------- . . r--- fied by the previous OCB. When the current OCB indicates a chaining operation, device parameter word 5 of the OCB must contain a main storage address that points to the next OCB in the chain. The device completes the current operation but does not present an interrupt request (excluding PCI) to the processor. Instead, the device fetches the next DCB in the chain and continues operation. Note. The chaining operation has no effect on programmed controlled interrupt (PCI). These interrupts, when specified in the OCB, still occur at the completion of the DCB fetch operation. Programmed Controlled Intermpt (PCI) Bit 1 of the OCB control word (when set to one) tells the device to present a PCI to the processor at the completion of the OCB fetch prior to data transfer. When the PCI is serviced, a OCB identifier byte is returned to the processor in the interrupt information byte (lIB). Refer to OCB device parameter word 3 in this chapter. Two conditions should be noted by the programmer: 1. 2. Chaining and data transfers associated with the OCB may commence even if the PCI is pending. If the PCI is pending when the device encounters the next interrupt causing condition, the PCI condition is discarded by the device and replaced with the new interrupt condition. Suppress Exception (SE) When a device uses this option it is allowed to suppress the reporting of certain exception conditions that would normally cause an exception interrupt. The device is then allowed to take alternative action depending on the condition. The suppressed exception conditions are reported to the programmer as status information upon completion of the operation. Refer to a subsequent section, Suppression of Exceptions, for details of the various actions a device might take. The suppress exception option also provides for automatic logging of status information (including suppressed exceptions) into main storage. When the SE bit for a OCB is set to one, the device always stores a residual status block into main storage after successful completion of the data transfer for the OCB. Device parameter word 4 of the OCB Input/Output Operations 4-13 must be used to specify the starting main storage address for the residual status block. Note that a residual status block is stored even if there are no exception conditions to be suppressed. The following section shows the residual status block that is stored. 1. • A status flag for this exception is set to one. • If the DCB specifies chaining, then the EOC bit is set to zero. Otherwise, it is set to one. • The NE bit is set to zero. Residual Status Block The residual status block is stored into main storage at the location pointed to by the status address (DCB word 4). The size of a residual status block is fixed for each device with a limit of 8 words total. The format is: Word~ o status flags 7 8 T- - I t~~ ~e~~d~'i~~::: =: := =~~if r: := := o s The device may then continue with the next DCB if chaining is specified. 8 15 Contains the residual byte count associated with the DeB. EOC is the End of Chain bit and is set to one for all conditions that would terminate a chaining operation. NE is the No Exception bit and is set to one when the operation is completed and no exceptions are reported. The Status Flags are device dependent flags that indicate suppressed exception conditions. Any additional words are device dependent as to number and content. Refer to the individual device publications for the additional status information and, also, the bit significance of the status flags. Suppression of Exceptions An exception condition can be suppressed by a device only when it occurs during a data transfer operation. It cannot be suppressed if it occurs during (1) a DCB fetch, (2) storing of a residual status block, or (3) a cycle steal status operation. A second requirement of a suppressible exception is that the device be capable of continuing operation in a normal and predictable manner after occurrence of the exception. If these conditions are not met, the exception condition causes an exception interrupt. When a suppressible exception is encountered, the device initiates one of a possible three types of action depending on the device and the exception condition. Note that the number of action types used by a device and the suppressible exceptions for each type are a device specification. Refer to the individual device publication. The three action types are: The device may then continue with the next DCB if chaining is specified. Suppress Exception and Terminate Data Transfer. Upon detecting the exception condition, the device terminates the data transfer for this DCB. It then stores a residual status block containing: • A status flag for the exception condition. • EOC bit set to zero, if chaining. Otherwise, set to one. • NE bit set to zero. 15 I 1M . I aXlmum I Word 0 Word 1 2. ______________________________--, reserved Suppress Exception and Continue. The exception condition occurs but data transfer is allowed to proceed. At the completion of the data transfer (defined by the DCB) a residual status block is stored with word one set as follows: 3. Programming Note. For some devices, the most common exception condition of this type is incorrect length record (ILR). For example, the data transfer is completed prior to the count reaching zero. In certain communications devices a short ILR is considered normal operation. When a short ILR occurs in this type device, the residual byte count is sufficient to indicate the condition; therefore, the NE bit may be set to indicate no exception. Suppress Exception and Terminate Chain. Upon detecting this exception condition, the device terminates the data transfer for this DCB. It ignores any commands specifying further chaining. The device stores a residual status block containing: • A status flag for the exception condition • EOC bit set to one • NE bit set to zero. The device then presents a device end interrupt. Refer to Interrupt Condition Codes in a subsequent section of this chapter. Programming Note. In certain communication devices a change-of-direction character is considered normal operation. When a change-of-direction character occurs in this type device, the EOC bit is sufficient to indicate the condition; therefore, the NE bit may be set to indicate no exception. (: 4-14 GA34-0022 c Priority of Suppress Exception Actions. Multiple exceptions that are suppressible can occur during an operation. They are noted.in the residual status block by setting multiple status flags. The type of action taken by a device depends on the exception/action combination with highest priority. The priority sequence is type 3, type 2, and type Cycle-steal Termina tion Conditions The following chart shows the action that occurs at the end of a DCB operation depending on the function specified and the exception conditions encountered: CHN 0 0 SE 0 1 0 1 Suppressible exception I (XCT) I (PDE) I (XCT) *1 (PDE)/CC Non-Suppressible exception I (XCT) I (XCT) I (XCT) I (XCT) No exception I (DE) I (DE) CC I (DE) CC - DCB chaining CRN - Chaining flag (bit 0 of the DCB control word) 1 (DE) - Device end interrupt I (PDE) - Permissive device end interrupt (see device end interrupt) I (XCT) - Exception interrupt SE - Suppress exception (bit 4 of the DCB control word) c *Dependent on the specific exception condition in the individual device. I/O Condition Codes and Status Information Each time an Operate I/O instruction is issued, the device, controller, or channel immediately reports to the processor one of seven condition codes pertaining to execu tion of the I/O command. These codes are called 10 instruction condition codes. Three bits are used to encode a condition code value (range U through '/). The bits are recorded in the even, carry, and overflow positions of the LSR and may be interrogated by specific instructions such as Branch on Condition Code and Branch on Not Condition Code. (See BCC and BNCC in Chapter 6.) For interrupting devices, condition codes are also reported during a priority interrupt. These codes are called Interrupt condition codes and pertain to operations that continue beyond execution of the Operate I/O instruction (such as cycle stealing of data). The interrupt condition codes are recorded in the LSR and interrogated in the same manner as the I/O instruction codes. Along with the interrupt condition code, the device also transfers an interrupt ID word to the processor. Bits 0 through 7 of the interrupt ID word contain status information related to the interrupt processing and are called the interrupt information byte (see Interrupt ID Word in this chapter). Figure 4-7 presents an overall view of condition code reporting along with status information. Details of the condition codes and status information are discussed in the following sections. Note that there are two unique sets of condition codes (10 instruction and interrupt) and that most status information is device dependent. o Input/Output Operations 4-15 Operate I/O (IO) instruction Device dependent status word •••••• Returned by the device if this is a Read Status operation LSR bits 0-2 •••••• Device reports 10 instruction condition code No CC 0 Device not attached 1 Busy 2 Busy after reset 3 Command reject 4 Intervention required 5 Interface data check 6 Controller busy 7 Satisfactory End operation Figure 4-7. Condition codes, status words, and status bytes received from a device (Part 1) 4·16 GA34-0022 c DPC Cycle steal DCB word 7 Resid ual parameters and device dependent status Returned by the device if this is a Start Cycle Steal Status operation ••••• residual address cycle steal status word 1 I device dependent status I device dependent status r- - - - - - - - - - I -I I X----------~ o c 15 DeB word 4 Residual status block Stored into main storage if the device uses SE and the SE bit is set to one ••••• :L I device dependen t status r-----------,...... o 15 Figure 4-7. Condition codes, sta tus words, and status bytes received from a device (Part 2) o Input/Output Operations 4-17 ( LSR bits 0-2 ~_J~~n~~u.!:.t _____ _ The device reports an interrupt condition code 1 2 3 4 5 6 7 •••••• CC Interrupt ID word o CC •••••• ~-------------- Presen ted by the device and placed in register 7 of the interrupted-to level *The available status is returned by the device when the following commands are used: Read Status-DPC Start Cycle Steal Status-cycle steal •• •• • • • • • ••• • •• • •• • •• ••• =1= Controller end PCI Exception Device end Attention Attention and PCI Attention and exception Attention and device end 2 or 6 (DPC or cycle steal) I device address I lIB o 78 CC = 2 or 6 (DPC) I device address ISB 7 8 0 Bit GA34-0022 15 0 Device status available * Delayed command reject 2- 7 Device dependent CC = 2 or 6 (cycle steal) I device address ISB 0 7 8 Bit 0 1 2 3 4 5 6 7 15 Device status available * Delayed command reject Incorrect length record DCB specification check Storage data check Invalid storage address Not used Interface data check Figure 4-7. Condition codes, status words, and status bytes received from a device (Part 3) 4-18 15 Bits 0- 7 Device dependent status or special meaning for CC2, CC3, and CC7 \ ; c 10 Instruction Condition Codes These codes are reported during execution of an Operate I/O instruction. Condition code (CC) value o 1 2 3 4 5 6 7 CC=O CC=l CC=2 c CC=3 CC=4 CC=5 CC=6 CC=7 c LSR position Even 0 0 0 0 1 1 1 1 Carry 0 0 1 1 0 0 1 1 Overflow 0 1 0 1 0 1 0 Reported by channel device device chan/dev device chan/dev controller chan/dev Meaning Device not attached Busy Busy after reset Command reject Intervention required Interface data check Controller busy Satisfactory Device not attached. Reported by the channel when the addressed device is not attached to the system. Busy. Reported by the device when it is unable to execute a command because it is in the busy state. The device enters the busy state upon acceptance of a command that requires an interrupt for termination. It exits the busy state when the processor accepts the interrupt. Certain devices also enter the busy state when an external event occurs that results in an interrupt. When this condition code is reported, a subsequent priority interrupt from the addressed device always occurs. Busy after reset. Reported by the device when it is unable to execute a command because of a reset and the device has not had sufficient time to return to the quiescent state. No interrupt occurs to indicate termination of this condition. Command Reject. Reported by the device or the channel when: 1. A command is issued (in the IDCB) that is outside the device command set. 2. The device is in an improper state to execute the command. 3. The IDCB contaJns an incorrect parameter. For example: an odd byte DCB address, or an incorrect function/modifier combination. When a cycle-steal device reports command reject, it does not fetch the DCB. Intervention required. Reported by the device when it is unable to execute a command due to a condition requiring manual intervention to correct. Interface data check. Reported by the device or the channel when a parity error is detected on the I/O data bus during a data transfer. Controller busy. This condition is reported by a device controller, not the addressed device, when the controller is busy. It is reported only by controllers that have two or more devices attached (each device having a unique address). When this condition code is reported, a subsequent controller-end interrupt always occurs. Satisfactory. Reported by the device on the channel when it accepts the command. These condition codes are mutually exclusive and have a priority sequence. That is, beginning with CC=7, each successive condition code through CC=O takes precedence over the previous code. For example, if a device cannot accept a command because it is busy, it reports CC=l, irrespective of error conditions encountered. Note. The only exception is CC=6 (controller busy). This condition code may have a variable priority depending on the particular controller. Interrupt Condition Codes These condition codes are reported by the device or controller during priority interrupt acceptance. Condition code (CC) value o 2 3 4 5 6 7 CC=o CC=l CC=2 CC=3 LSR position OverEven Carry flow 0 0 0 0 0 Reported by controller device 0 0 1 1 1 device device device device device 1 0 0 0 1 0 1 0 device Meaning Controller end Program controlled interrupt (PCI) Exception Device end Attention A ttention and PCI Attention and exception Attention and device end Controller end. Reported by a controller when controller busy (10 instruction condition code) has been previously reported one or more times. It signifies that the controller is now free to accept I/O commands for devices under its control. The device address reported with controller end is always the lowest address (numerical value) of the group of devices serviced by the controller. The interrupt information byte, in the interrupt 10 word, is set to zero. Program controlled interrupt. Reported when the interrupt indicates that a DCB with the PCI bit set to one has been transferred by cycle steal to the device and no error or exception condition has occurred. The device places a DCB identifier into the interrupt information byte. Exception. Reported when an error or exception condition is associated with the interrupt. The condition is described in the interrupt status byte (lSB) or in device dependent status words. Device end. Reported when no error, exception, or attention condition has occurred during the I/O operation, and the interrupt is not the result of a PCI. For example: an operation has terminated normally. Note. If the device has come to a normal end while using suppress exception (SE bit set to one) and an exception was suppressed since the last Start command, then bit zero of the interrupt status byte is set to one. The condition is called permissive device end (POE) and indicates that errors or exceptions have been suppressed. Related status information is contained in the residual status block. Input/Output Operations 4-19 CC=4 A ttention. Reported when the interrupt was caused by an external event rather than execution of an Operate I/O instruction. Additional status information is not provided unless the event requires further definition; for example, code bits for a keyboard function. Attention and PCI. Reported when attention and PCI are both present. In this case the interrupt information byte contains the DeB identifier, and the attention must be singular in meaning. A ttention and exception. Reported when attention and exception are both present. A ttention and device end. Reported when attention and device end are both present. For this condition code, device end could also mean permissive device end. Refer to interrupt condition code 3. CC=5 CC=6 CC=7 The interrupt condition codes are mutually exclusive with each other but have no priority sequence. I/O Status Information Some form of status information is transferred from the device to the processor as a result of: • A read status operation (see Read Status command in this chapter). • A start cycle steal status operation (see Start Cycle Steal Status Operation in this chapter). • Storing a residual status block (see Cycle-Steal Device Options in this chapter). • A priority interrupt. The interrupt status information is detailed in the following two sections (Interrnpt ID Word and Interrup t Status Byte). Interrupt ID Word Acceptance of an I/O interrupt causes the device to present an interrupt ID word to the processor. Presentation of the interrupt ID word is explained in Chapter 3 (see I/O Interrupts). This word has the following format: Interrupt ID word 1. 2. 7 8 The ISB is never reported as zero unless the condition code presentation of 2 or 6 is singular in meaning for devices that do not cycle steal. After the processor has accepted the interrupt request, the device resets the ISB. Bits 0- 7 of the two special formats are explained in the following sections. ISB (devices that do not cycle steal): Bit 0 Device dependent status available. This bit set to one signifies that additional status information is available from the device. The information content and method of reading is described in the individual device publications. Bit 1 Delayed Command reject. This bit is set to one if the device cannot execute the command (specified in the lDeB) due to an incorrect parameter in the IOCB, or it cannot execute the command due to its present state. For example: (1) the IOCB specifies an incorrect function/modifier combination, or (2) the device is temporarily not ready. The operation in progress is terminated. Command reject is set in the ISB only if the device cannot report 10 instruction condition codes for the condition. Bits 2-7 Device dependent. These bits, if used, are described in the individual device publications. ISB (cycle stealing device): Bit 0 Device dependent status available. This bit, when set to one, signifies that: (1) additional status information is available from the device, or (2) the device is in an improper state to execute a function specified by a DeB. The operation is terminated. The content and method of reading the additional status information is described in the individual device publications. 15 Bit 1 Bits 0-7 1nterrnpt information byte (lIB). For interrupt condition codes 2 and 6, the lIB has a special format and is called an interrupt status byte (lSB). Refer to interrnpt status byte in this section. For most other interrupt condition codes, implementation of the lIB is device dependent. Exceptions are: 1. CC=O. The lIB is set to zero. 2. CC=3 or 7. Bit zero may be set to one if suppress exception is in effect. Bits 8-15 4-20 Device address. This byte contains the address of the interrupting device. GA34-0022 (; Status errors that occur during a DPC operation that cannot be indicated via a condition code. Status errors that occur during a cycle steal operation. Device address lIB o Interrupt Status Byte (ISB) The ISB is a special format of the interrupt information byte (lIB) and contains detailed information on the nature of the interrupt. The ISB is reported only for error or exception conditions (interrupt condition codes 2 or 6). The ISB bits are normally set as a result of: Note. When bit 0 of the ISB is equal to one and bits 2-7 are zeros, the contents of the residual-address word (cycle steal status) are defined by the device. Delayed command reject. This bit is set to one if the device cannot execute the command due to one of the following conditions: 1. The IDCB contains an incorrect parameter. Examples are (a) an odd-byte DCB address, or (b) an incorrect function/modifier combination. 2. The present state of the device, such as a not ready condition, prevents execution of an I/O command specified in the IOCB. Delayed command reject is set in the ISB only if the device cannot report 10 instruction condition codes for the condition. The operation is terminated. The DCB is not fetched. ", c Bit 2 Bit 3 Bit 4 c Bit 5 Incorrect length record. This bit is set to one when the device encounters a mismatch between byte count and actual record length after beginning execution of the DeB. For example: the byte count is reduced to zero (with chaining flag off) and no end of record encountered. Incorrect length record is not reported when the SE bit in the control word is set to one. dependent feature and may be implemented regardless of the suppress exception feature. The operation is terminated. DeB specification check. This bit is set to one when the device cannot execute a command due to an incorrect parameter specification in the DeB, Examples are (1) an odd-byte DeB chaining or status address, (2) the byte count is odd for a word-only device, (3) an odd-byte data address for a word-only device, (4) an invalid command or invalid bit settings in the control word, or (5) an incorrect count. The operation is terminated. Storage data check. This error condition applies to cycle steal output operations only. If the bit is set to one, it indicates that the main storage location accessed during the current output cycle contained bad parity. Parity in main storage is not corrected. The device terminates the operation. The bad parity data is not transferred to the I/O data bus. No machine check condition occurs. See Figure 4-8 for other bits that may be present. Invalid storage address. When set to one, this bit indicates that, during a cycle steal operation, the device has presented a main storage address that is outside the storage size of the system. Invalid storage address can occur on a data transfer or on a DeB fetch operation. In either case, the cycle steal operation is terminated. See Figure 4-8 for other bits that may be present. Bit 6 Bit 7 Not used. Interface data check. This bit set to one indicates that a parity error has been detected on the I/O data bus during a cycle steal data transfer. The condition may be detected by the channel or the I/O device. In either case, the operation is terminated. See Figure 4-8 for other bits that may be present. Conditions I/O operation Invalid storage address Incorrect data parity Bit results 4 5 7 Write No No 0 0 0 Write Yes No 0 I 0 Read No No 0 0 0 Read Yes No 0 I 0 Write No Yes 0 0 1 Write Yes Yes 0 I 1 Read No Yes 1 0 1 Read Yes Yes 1 1 1 * *This condition not possible. Figure 4-8. Bit result chart o Input/Output Operations 4-21 () c 4-22 GA34-0022 Chapter 5. Console c ThpTP ::lTP two- ('onfiOl1T::ltiom: of ('om: 01 PI: ::lV::libhlp fOT thp -----0- --------- - - - - - - - - - - - - - - - - - - - - - - - - ---- IBM 4953 Processor. The Basic Console is standard, and remains with the processor. The Programmer Console is an optional feature that is added to the processor when the option is selected. Configuration 2 Basic Console and Programmer Console Configuration 1 Basic Console 000 ~Ej~ LOdd O W .. ,t IPL Source ~ Run Prlrl1d r y Alterndte LOdd Mode Auto IPL ~urrndl Dldqno<.,tll ~ ~R L:J lPL SOtHO' PrU1WY Altern"te ~ U Mode AutolPL Norll1dl ~ Dldqno<;tlc ~R L:J c a heCk LJeset o evel 0 Detore Ddtd Buffer +t+ ~evel 1 rJevel2 rJevel 3 o 0 ~ 0 0 On Address Stop 0 uuDLJODDD LJLJLJ ~,~:'"' DODD LJDLJLJOOOD LJLJLJLJODOD o Console 5-1 Configuration 1 is primarily intended for those systems that are totally dedicated to a particular application, where operator intervent~on is not needed during the execution of the application. Configuration 2 is aimed at operator oriented systems where various programs are entered and executed during the day. This type of environment requires a more versatile console arrangement for program and machine problem determination, and for manual alteration of data and programs in storage. m Mode Basic Console Each IBM 4953 Processor comes equipped with the standard Basic Console. The Basic Console provides the following capabilities: • • • • Power On/Off switch for the processor card file Load key for IPL (initial program load) Load, Wait, Run, and Power On indicators Mode switch to select: Diagnostic mode, Auto IPL, or Normal mode • IPL source switch to select a primary or alternate IPL device. This switch has the following positions: • Auto IPL - In this position, an IPL is initiated after a successful power-on sequence. Bit 13 of the PSW is set to indicate to the software that an automatic IPL was performed. In this mode STOP instructions are treated as no-ops. • Normal - This position is for attended operation. In this mode STOP instructions are treated as no-ops. • Diagnostic - This position has no function without the Programmer Console. This position places the processor in a diagnostic mode if the Programmer Console is attached. When the processor is in diagnostic mode, STOP instructions cause the processor to enter stop state. ( lJ Indicators II Power On II Load II Wait m Run On when the proper power levels are available to the system. On when the machine is performing an initial program load (IPL). On when an instruction that exits the active level has been executed and no other levels or interrupts are pending. On when the machine is executing instructions. Keys and Switches II Power On/Off iii IPL Source EI Load When this switch is placed in the On position, power is applied to the processor card file. After all power levels are up, the Power On indicator is turned on. When this switch is placed in the Off position, power is removed from the processor card file and the Power On indicator is turned off. This switch selects the I/O device to be used for program loading. In the Primary position, the device that was pre-wired as the primary IPL device is selected. In the Alternate position, the device that was prewired as the alternate IPL device is selected. Pressing this key causes a system reset, then the initial program load (IPL) sequence is· started. The Load indicator is turned on and remains on until the IPL sequence is completed. When the IPL is completed, instruction execution begins at location zero on level zero. (: 5-2 GA34-0022 c Programmer Console The Programmer Console is an optional feature that can be ordered with the IBM 4953 Processor or may be field installed at a later date. The Programmer Console provides the following capabilities: • • • • • • • • • • • • Start and stop the processor. Display or alter any storage location. System reset. Select any of the four interrupt levels for display or alter purposes. Display or alter the storage address register (SAR), instruction address register (IAR), console data buffer, or any general purpose register. Display but not alter the level status register (LSR), current instruction address register (CIAR), op register, or processor status word (PSW). Stop-on-address. Stop-on-error. Instruction step. Check restart. Request a console interrupt. Check indicator, on when a machine check or program check class interrupt has occurred. c IPl AutotPL '\J(lfrndl SOUIU ~ [)Idqrl()"tll The Programmer Console is touch sensitive with a tone generator providing an audio response tone whenever a key depression has been accepted and serviced by the processor. Console Display When the processor is in run state or wait state, the console uata uUllt:l i~ Ji::>played in the data display indicatcr:;. The only exception to this is when in run state a Set Console Data Lights instruction writes a message to the data display. This message remains displayed until the processor enters stop state or the Data Buffer Key is pressed. When the Data Buffer Key is pressed, the console data buffer is again displayed in the data display indicators. When the processor enters stop state, the IAR is displayed in the data display indicators. Any system resource that has a corresponding select key on the console can be displayed while in stop state. Once data has been entered into the console data buffer, it remains there until other data is entered. The console data buffer can be displayed at any time, during either run state, wait state, or stop state, by pressing the Data Buffer key. After a power-on reset, the data display indicators are all set on, and the level indicators are set off. ~R L:J In run state and wait state, displayed all the time. In stop state, displayed when the Data Buffer key is pressed. Display Buffer heCk ~ LJeset o o rJ evelO LJtare Data Buffer +++ ~evell uevel2 bJevel3 0 0 0 Stop On Andress 0 Console Data Buffer IAR displayed in Stop state uuLJDDOOD LJLJLJ ~,~:'" DOOD o LJOLJOOODO I DLJ[JLJODOD Displayable areas or Message from Set Console Data Lights Instruction. Console 5-3 Indicators II Data Display iii Check • When the processor is in run state, the console data buffer is displayed in the data display indicators. • When the processor enters stop state, the IAR is displayed unless another system resource is selected. • To display the contents of the console data buffer after a system resource has been displayed, press the Data Buffer key·1I On when a machine check, program check, or power/thermal warning class interrupt has occurred while in process mode or in stop-on-error mode. The check indicator remains on until either the check condition is cleared, or any console key is pressed while in the stop state. The check condition is cleared by the Reset key, Load key, or the execution of a Copy Processor Status and Reset instruction (which resets the check bits). If a main storage display of a location causes a parity error, an invalid storage address, or a specification check, the check indicator is turned on, or appears to stay on. ~~~ O'' M lPL Source Prlrlldry AllPfflcltl-' ~ Mode ",,0'"' ~ Nornldl D1dqnostlc [J .~ " Of! LJLJLJLJODDO FlFlFl DOOD LJLJLJ Main. Storaqe LJCJ[][]ODDD LJLJLJLJODOD 5-4 GA34-0022 I ; c Combination Keys/Indicators There are nine combination key/indicators: • • • • • • lPL Source Level 0, 1, 2, and 3 Stop Stop On Address Instruct Step Check Restart Stop On Error 11 Level 0-3 iii Stop AI!ern"!e ~ U Mode Au!oIPL Norr1lcll Dld4nostiC ~ n I Off I ~J The current active level is always displayed by one of the level indicators. When in the stop state, pressing any of the level keys causes that level to be selected and the associated indicator is turned on. This indicator is on when the processor is in the stop state. Stop state is entered in the following ways: • • • • c P""'dry • • • By pressing the Stop key. In run state the current instruction is completed. In wait state, stop state is entered directly. By execution of the Stop instruction (diagnostic mode only). When an address compare occurs in stop-on-address mode. When an error occurs in stop-on-error mode. By pressing the Reset key. When a power-on reset occurs. By selecting the Instruction step mode while in run state. uLJLJLJDODD U[]U ~,~;.~ DODD LJDDLJDDDD DOLJLJDDOD o Console 5-5 The Stop On Address key and the Instruct Step key are mutually exclusive. When one is pressed, the other is reset if it was on. II II IPL Source P"mdry Stop on Address Instruct Step This key places the processor in stop on address mode. Pressing the Stop On Address key a second time resets stop on address mode and turns off the indicator. Pressing the Instruct Step key places the processor in instruction step mode and turns the Instruct Step indicator on. The Stop On Address indicator is turned off if it was on. Alternate ~ U Mode Auto IPL ~~ormal Dlaljnosttc ~ ~R ~ If the processor is in run state, pressing this key causes the processor to enter stop state. Pressing the Instruct Step key a second time resets instruction step mode, the processor remains in stop state. To operate in instruction step mode: • Key the desired starting address and store into the IAR. • Press the Instruct Step key. • Press the Start key. The instruction located at the selected address is executed, the processor returns to stop state. The IAR is updated to the next instruction address, this address is displayed in the data display indicators. • Each subsequent depression of the Start key causes one instruction to be executed and the IAR is updated to the next instruction address. Stop On Address Mode Processor must be in stop state to set the compare address. CJLJLJDODOD LJLJLJ ~,~::"' DODD OLJLJLJDDDD I LJLJLJDODOD 1. Press Stop On Address Key. 2. Key in selected address. 3. Press Store Key. The selected address is placed in the stop on address buffer. 4. Press Start Key. Execution begins at current IAR address on the current level. When the selected address is loaded into the IAR, the processor enters stop state. To exit stop state press the Start key; execution begins at the next sequential address. Note. When running in Stop on Address Mode, instruction execution time is increased by 7.8 microseconds per instruction. c 5-6 GA34-0022 C·--.~ ~ The Check Restart key and the Stop On Error key are mutually exclusive. When one is pressed the other is reset if it was on. II \PL SOUfCt' Prlmarv Check Restart Pressing this key places the processor in check restart mode. While in this mode, a program check, or machine check, or a puwcr! iilcIlIlai warning dass illicIIUpi causes the processor to be reset and execution to restart at address zero on level zero. n Altf:'rndtt' LOdd Mode l~ fl LJj Note. The power/thermal warning class interrupt is controlled by the summary mask. II Stop On Error Pressing the Stop On Error key places the processor in stop on error mode. Any program check, machine check, or power/ thermal warning causes the processor to enter stop state. To determine the cause of the error, display the PSW (see table). To restart the processor, press the Reset key then the S tart key. Pressing only the Start key allows the processor to proceed with the class interrupt as if stop mode has not occurred. Note that the check indicator may have been turned off while in stop state. After the class interrupt routine is completed, control may be returned to the instruction that caused the error and an attempt to reexecute the instruction may be made. Note that some instructions are not re-executable because operand registers or storage locations were changed before the instruction was terminated because of the initial error. In these cases, the operator must be familiar with the program because manual restoration of affected locations must be made before restart is attempted. 1"'Ck o ~ o U evelO LJeset LJ-tore LJdtd Bulfer ." bJevell (J"veI2 0 0 ~evel3 0 StopOn Address 0 DLJDDDODD FlFl~ DODD LJLJLJ Maln_ Stordlje DLJLJODDDD OLJOLJDDDD Note. The power/thermal warning class interrupt is controlled by the summary mask. Processor Status Word (PSW) Table Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Meaning Specification check Invalid storage address Privilege violate Not used Invalid function (may be program check) Not used Stack exception Not used Storage parity check Not used CPU control check I/O check Sequence indicator Auto-IPL Not used Power/thermal warning Category Program check Program check Program check Soft exception Soft exception Machine check Machine check Machine check Status flag Status flag Power /Thermal Bits not used are always zero. 0 Console 5-7 Keys and Switches II Reset This key initiates a system reset that performs the following functions: • • • • • • • Interrupt mask set to all levels enabled. LSR on level zero - indicators set to zero, summary mask enabled, supervisor state and in-process flag turned on, trace disabled. LSRs for levels 1-3 set to zeros. PSW set to zero. SAR set to zeros. CIAR set to zeros. IAR on level zero - set to zeros. IPL Source Primary Alternate ~ U Mode Auto IPL Normal Dld4nostlc ~ t;~'O"l () .1 R L:J After the system reset is completed, the processor is placed in the stop state with stop indicator on. The following resources are not effected by system reset: • • • • • General registers (all levels) lARs (levels 1-3) Main storage Console data buffer Stop on Address buffer. iii Store II Data Buffer II Console Interrupt This key is effective only when the processor is in stop state. Pressing this key causes the last data entry to be stored in the last selected resource. Pressing this key causes the contents of the console data buffer to be displayed in the data display indicators. The effect of this key depends on the state of the processor. If the processor is in the stop or load states, this key has no effect. If the processor is in the run or wait state and the summary mask is enabled, a console class interrupt occurs. Note. If the summary mask is enabled by the program while the key is being activated, a console class interrupt occurs. II Start Effective in stop state only. Stop state is exited and the processor resumes execution at the address in the IAR on the current level. If stop state was entered from system reset, execution begins at address zero, level zero. If stop state was entered from wait state, the processor returns to wait state. Note. The Reset and Console Interrupt keys have an indication (+++) on the face of the keys. This signifies that additional pressure must be used to activate these keys. This is to minimize the possibility of the operator inadvertently activating these functions. 5-8 GA34-0022 CJLJLJDDDOD LJLJCJ ~,~;.'" DODD LJDLJLJOODD DLJCJLJODDD II C m Op Reg m CIAR II SAR 13 c PSW Main Storage Pressing this key selects the processor status word. The contents of the PSW are displayed in the data display indicators. Data cannot be stored into the PSW from the console. Pressing this key selects the Op register and displays the contents in the data display indicators. Data cannot be stored into the up regist~r frum tht: \';ull:.ui~. Pressing this key after entering stop state causes the address of the instruction just executed to be displayed. Data cannot be stored into the CIAR from the console. Pressing this key while in stop state displays the contents of the storage address register. An address can be stored into the SAR to address main storage for display or store operations. Bit 15 of the SAR cannot be set from the console. Pressing this key selects main storage as the facility to be accessed by the console. When this key is pressed, the contents of the main storage location addressed by the SAR is displayed in the data display indicators. Procedures for displaying and storing main storage are provided in subsequent sections of this chapter. IPL Source Pflnldfy Alternate Auto IPL l"Jurrlldl ~ Mode U N ~ I CJeset Off I ~J Oldqnostlc LJtorc DJtd ~ o 0 0 0 0 ~ LiJ~liJLiJOODD LJLJCJ ~i DODD 'heCk o evel 0 Butter +++ ~evel 1 bJevel2 bJevel3 StOll On Address DDLJLJOODD DLJLJLJDDDD c Console 5-9 Level Dependent Keys The following keys select registers that are duplicated in hardware for each of the four interrupt levels: • LSR • IAR • General purpose registers 0-7 Pressing any of these keys, once a level has been selected, causes the contents of that register to be displayed in the data display indicators. The level status register (LSR) is displayable only; data cannot be stored into this register. The AKR key is not functional on the 4953 Processor and does not respond with an audio tone when pressed. Bit 15 of the lARs cannot be changed from the console. Pressing the Store key after selecting an LSR or AKR results in no action taken and no audio tone response. 5-10 GA34-0022 c Data Entry Keys The sixteen data entry keys are used to enter data into the selected resource. c Example: Data to be entered: F3A8 Action Data display indicators Press data entry key F Press data entry key 3 Press data entry key A Press data entry key 8 o Legend: • - Indicator on 0- Indicator off Console 5-11 Displaying Main Storage Locations Storing Into Main Storage • Processor must be in stop state. • Processor must be in stop state. Press the SAR key. II The contents of the SAR are displayed in the data display indicators. 2. Key in the selected address (four hex characters). This address is displayed in the data display indicators. 3. Press the Store key. II The address that is displayed is stored into the SAR. 4. Press the Main Storage key. II The contents of the addressed storage location are displayed in the data display indicators. To display sequential main storage locations, continue pressing the Main Storage key. The storage address is incremented by +2 each time the Main Storage key is pressed, and the contents of the addressed location are displayed. 1. Press the SAR key. II The current contents of the SAR are displayed in the data display indicators. 2. Key in the selected address (four hex characters). The address is displayed in the data display indicators. 3. Press the Store key. iii The address displayed in the data display indicators is stored into the SAR. 4. Press the Main Storage key.1I The contents of the addressed storage location are displayed in the data display indicators. 5. Key in the data that is to be stored into main storage. This data is displayed in the data display indicators. 6. Press the Store key.1iI The data that is displayed is stored at the selected storage location. Each subsequent pressing of the Store key causes the SAR to be incremented by +2, and the data stored at that location is displayed. 1. tPL Source P"mary Alterrtdtp ~ U Mode Auto IPL Normdl ~ Dldqno<;tlc ~ wevell uevel2 bJevel3 o ~ heCk LJeset o t;I ~R L:J Buffer 0 0 Stop On Address 0 LJLJuriJOOOO LJLJLJ ~'ii DODD LJDDDOODDI LJDDDODDO GA34-0022 i ~ evelO 5-12 , LiJtore Oata tH 0 ( . c c Displaying Registers Storing Into Registers • Processor must be in stop state. • Processor must be in stop state. 1. 1. 2. Select the proper level by pressing the appropriate Level key. a The contents of any register associated with the selected level can now be displayed by pressing the regIster key. Press the desired register key. The contents of that register are displayed in the data display indicators. 2. 3. m 4. Select the proper level by pressing the appropriate Level key.a Press the key for the register where data is to be stored. The contents of that register are displayed in the data display indicators. iii Key in the data that is to be stored. This data is displayed in the data display indicators. Press the Store key. II The data that is displayed is stored into the selected register. IPL SOUr( t' ~R !\1o!lt, 'I1Cl" ~ Om 0 ~ o evelo ~tl)n' 1:31 odtd Buffer D"'''t ,., ~"V"ll L:J Co",ol" Interrupt g >j' U"V"12 b]!'v!' I StopD" Addres~ I",truet Step 0 0 0 3 0 D~ [jtoi> CII,'ek ReSidrt o 0" Errut 0 LJLJDDDDDO PI FlFl8DD"OJ0 LJLJLJO LJDLJLJODDD I DLJLJLJDDDD j o Console 5-13 5-14 GA34-0022 Chapter 6. Instructions c The instructions for the IBM 4953 Processor are described in this chapter. A complete listing of instruction formats is contained in Appendix B. Instruction timings are contained in Appendix A. Indicator settings are listed for each instruction. For additional indicator information, refer to Indicators in Chapter 2. Exception Conditions Exception conditions that might occur during instruction execution are shown in abbreviated form with each instruction description. Refer to the following sections for a detailed description of these conditions. Program Check Conditions Invalid Function (1) An illegal operation code or function combination is encountered during instruction execution, or (2) while in supervisor state, the processor attempts to execute one of the following instructions; operation code 01011 with a function of 0001 or 1001. A program check class interrupt occurs with invalid function (bit 4) set in the PSW. See Processor Status Word in Chapter 3 for a list of invalid functions. Specification Check Operand Address. The generated effective address has violated an even-byte boundary requirement. Indirect Address. When using addressing mode (AM=II), the indirect address is not on an even-byte boundary. The instruction is suppressed unless otherwise noted in the individual instruction description. A program check class interrupt occurs with specification check (bit 0) set in the PSW. Note. A specification check can also occur during a Supervisor Call (SVC) instruction if the SVC LSB pointer or the SVC SIA pointer violates an even-byte boundary requirement. Soft Exception Trap Conditions Invalid Function (1) Operation code 00100 is attempted (2) operation code 10110 is attempted or (3) in supervisor state, operation code 01011 with a function of 0011 or 1011 is attempted. The instruction is suppressed. A soft-exception-trap class interrupt occurs with invalid function (bit 4) set in the PSW. See Processor Status Word in Chapter 3 for a list of invalid functions. Invalid Storage Address Instruction Word or Operand. One or more words of the instruction or the effective address is outside the installed storage size of the system. The instruction is suppressed unless otherwise noted in the individual instruction description. A program check class interrupt occurs with invalid storage address (bit 1) set in the PSW. Privilege Violate Privileged Instruction. A privileged instruction is encountered while in problem state. The instruction is suppressed. A program check class interrupt occurs with privilege violate (bit 2) set in the PSW. See Processor Status Word in Chapter 3 for a list of privileged instructions. Stack Exception (1) The stack is full and a Push instruction or a Store Multiple (STM) instruction is attempted, (2) the stack is empty and a Pop instruction or a Load Multiple and Branch (LMB) instruction is attempted, or (3) the stack cannot contain the number of words to be stored by a Store Multiple instruction. The instruction is suppressed. A soft-exception-trap class interrupt occurs with stack exception (bit 6) set in the PSW. Note. When the AM field is equal to 01, the register specified by the RB field is incremented before the class interrupt occurs. o Instructions 6-1 Instruction Termination or Suppression No Operation Exception conditions that occur during instruction processing might cause the instruction to be terminated or suppressed. When an instruction is terminated, partial execution has taken place and may have caused a change to registers, indicators, or main storage. When an instruction is suppressed, there has been no execution, therefore, no changes. Refer to Exception Conditions in the previous section. In supervisor state the following instructions are recognized and executed as a No Operation instruction. Op Code Function 01011 01100 01111 0010,0100,1010,1100 110 10010, 11010 Program Check 1. Compatibility The IBM 4955 Processor has more features and instructions than the IBM 4953 Processor. Consideration should be given to the differences between the processors when writing programs to permit possible future replacement with a larger system. , The following section describes the action taken by the IBM 4953 Processor when instructions that apply to the IBM 4955 Processor are encountered. Soft Exception Trap The following instructions cause a soft exception trap class interrupt with invalid function, bit 04 in the PSW, set to 1. Op Code 00100 01011 (} 2. In supervisor state the following instructions cause a program check class interrupt with invalid function, bit 04 in the PSW, set to 1. Op Code Function 01011 10110 0001, 1001 all In problem state the following instructions cause a program check class interrupt with privilege violate, bit 02 in the PSW, set to 1. Op Code Function 01011 0001,0010,0011,0100,1001,1010,1011, 1100 110 10010, 11010 01100 01111 Function all 0011, 1011 (supervisor state only) (~ 6-2 GA34-0022 AB ABI c Instruction Descriptions Add Byte Immediate (ABI) The following descriptions are in alphabetical sequence based on assembler mnemonics. However, extended mnemonics are listed under the appropriate machine instruction. For example: branching and jumping instructions. ABI byte,reg Io I Operation code 0 0 0 0 () Add Byte (AB) AB reg,addr4 addr4,reg 4 ~ R Immediate 7 R 1~ The immediate field is expanded to 16 bits by sign propagation to the eight high-order bits. The field is then added to the contents of the register specified by the R field. The result is placed in the register specified by the R field. Opera tion Code Indicators 1 1 0 0 0 o storage}~ 1 = result to result to register () = c An add operation is performed between the least significant byte of the register specified by the R field and the location specified by the effective address in main storage. (See Effective Address Generation in Chapter 2.) Bit 12 of the instruction specifies the destination of the result. The source operand and high-order byte of the register are unchanged. Carry. Turned on if a carry is detected out of the highorder bit position of the word. If no carry is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the sum cannot be represented in one word; i.e., if the sum is less than _2 15 or greater than +2 15 -1. If an overflow occurs, the result contains the correct low-order 16 bits of the sum; the carry indicator contains the high-order (sign) bit. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions No program checks occur. Indicators Carry. Turned on if a carry is detected out of the highorder bit position of the byte. If no carry is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the sum cannot be represented in one byte; i.e., if the sum is less than _27 or greater than +2 7 -1. If an overflow occurs, the result contains the correct low-order eight bits of the sum; the carry indicator contains the high-order (sign) bit. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions Invalid Storage Address. Instruction word or operand. Specification Check. Even byte boundary violation (indirect address). o Instructions 6-3 ACY Add Carry Register (ACY) ACY reg () Operation code o Function 1 1 1 0 o 4 5 0 1 100 7 8 10 11 15 The value of the carry indicator on entry is added to the contents of the register specified by the R2 field, and the result is placed in the register specified by the R2 field. Bits 5-7 of the instruction are not used and must be set to zero to avoid future code obsolescence. Programming Note. This instruction can be used when adding multiple word operands. See Indicators - Multiple Word Operands in Chapter 2. Indicators Carry. Turned on if a carry is detected out of the highorder bit position of the word. If no carry is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the sum cannot be represented in one word; i.e., if the sum is less than _2 15 or greater than +2 15 _1. If an overflow occurs, the result contains the correct low-order 16 bits of the sum; the carry indicator contains the high-order (sign) bit. Even. Unchanged. Negative. Changed to reflect the result. Zero. If on at entry, changed to reflect the result. If off at entry, it remains off. Program Check Conditions No program checks occur. c: 6-4 GA34-0022 AD c Add Doubleword (AD) Storage/Storage Format Register/Storage Format AD AD reg,addr4 addr4,reg addrS ,addr4 Operation code 1 0 1 0 () 1 4 5 7 8 9 10 11 12 13 14 15 Operation Code 1 101 0 o 1 = result to storage } o = result to register c ~ An add operation is performed between the register pair specified by the R field (R and R+ 1) and the doubleword in main storage specified by the effective address. (See Effective Address Generation in Chapter 2.) Bit 12 of the instruction specifies the destination of the result. The source operand is unchanged. If the R field equals 7, register 7 and register 0 are used. Indicators Carry. Turned on if a carry is detected out of the high-order bit position of the doubleword. If no carry is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the sum cannot be represented in the doubleword; i.e., if the sum is less than _2 31 or greater than +2 31 -1. If an overflow occurs, the result contains the correct low-order 32 bits of the sum; the carry indicator contains the high-order (sign) bit. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions Invalid Storage Address. Instruction word or operand. Specification Check. Even byte boundary violation (indirect address or operand address). The address arguments generate the effective addresses of two operands in main storage. (See Effective Address Generation in Chapter 2.) Doubleword operand 1 is added to doubleword operand 2. The result replaces operand 2. Operand 1 is unchanged. Indicators Carry. Turned on if a carry is detected out of the highorder bit position of the doubleword. If no carry is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the sum cannot be represented in the doubleword; i.e., if the sum is less than _2 31 or greater than +2 31 -1. If an overflow occurs, the result contains the correct low-order 32 bits of the sum; the carry indicator contains the high-order (sign) bit. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions Invalid Storage Address. Instruction word or operand. The instruction is terminated. If RBI and RB2 specify the same register and AM 1=01, the register is incremented before the program check interrupt occurs. Specification Check. Even byte boundary violation (indirect address or operand address). o Instructions 6-5 AW Add Word (AW) Register/Storage Format Register/Register Format AW AW reg,reg Operation code o o reg,addr4 addr4,reg 1 1 1 0 4 5 Operation Code Function o 7 8 10 11 () 1 000 15 The contents of the register specified by the Rl field are added to the contents of the register specified by the R2 field. The result is placed in the register specified by the R2 field. The contents of the register specified by the Rl field remain unchanged if Rl and R2 do not specify the same register. 1 100 1 o 1 = () = result to storage } result to register ~ c==~~=~~~~~~~~~~~~-~ Displacement 1 ] DIsplacement 2 .J L 16-- - - - - --2324- - - - - - - 3 1 Indicators Carry. Turned on if a carry is detected out of the highorder bit position of the word. If no carry is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the sum cannot be represented in one word; i.e., if the sum is less than _2 15 or greater than +2 15 _1. If an overflow occurs, the result contains the correct low-order 16 bits of the sum; the carry indicator contains the high-order (sign) bit. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions No program checks occur. An add operation is performed between the register, specified by the R field and the location specified by the effective address in main storage. (See Effective Address Generation in Chapter 2.) Bit 12 of the instruction specifies the destination of the result. The source operand is unchanged. Indicators Carry. Turned on if a carry is detected out of the highorder bit position of the word. If no carry is detected, the carry indicator is reset. , I '\ \ , Overflow. Cleared, then turned on if the sum cannot be represented in one word; i.e., if the sum is less than _2 15 or greater than +2 15 _1. If an overflow occurs, the result contains the correct low-order 16 bits of the sum; the carry indicator contains the high-order (sign) bit. Even, Negative, and Zero. Changed to reflect the result. Program ·Check Conditions Invalid Storage Address. Instruction word or operand. Specification Check. Even byte boundary violation (indirect address or operand address). c 6-6 GA34-0022 AW c Storage to Register Long Format Storage/Storage Format AW AW longaddr ,reg Operation code o addrS ,addr4 Operation code 1 101 010 1 5 rI V 0= direct address } 1 = indirect address '7 B 9 !a!! 1213!4!5 ~ Address 31 16 The contents of the main storage location specified by an effective address are added to the contents of the register specified by the RI field. The result is placed in the register specified by the Rl field. The effective main storage address is generated as follows: 1. c 2. The address field is added to the contents of the register specified by the R2 field. I[ the R2 field equals zero, no register contributes to the address generation. Instruction bit 11 is tested for direct or indirect addressing: Bit 11=0 (direct address). The result from step 1 is the effective address. Bit 11=1 (indirect address}. The result from step 1 is the address of the main storage location that contains the effective address. Indicators Carry. Turned on if a carry is detected out of the highorder bit position of the word. I[ no carry is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the sum cannot be represented in one word; i.e., if the sum is less than _2 15 or greater than +2 15 -1. I[ an overflow occurs, the result contains the correct loworder 16 bits of the sum; the carry indicator contains the high-order (sign) bit. The address arguments generate the effective addresses of two operands in main storage. (See Effective Address Generation in Chapter 2.) Word operand 1 is added to word operand 2. The result replaces operand 2. Operand 1 is unchanged. Indicators Carry. Turned on if a carry is detected out of the highorder bit position of the word. I[ no carry is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the sum cannot be represented in one word; i.e., if the sum is less than _2 15 or greater than +2 15 _1. If an overflow occurs, the result contains the correct low-order 16 bits of the sum; the carry indicator contains the high -order (sign) bit. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions Invalid Storage Address. Instruction word or operand. The instruction is terminated. I[ AMI equals 01 and the operand 2 effective address is invalid, RBI is incremented. Specification Check. Even byte boundary violation (indirect address or operand address). Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions Invalid Storage Address. Instruction word or operand. o Specification Check. Even byte boundary violation (indirect address or operand address). Instructions 6-7 AWCY Add Word With Carry (AWCY) AWCY () reg,reg Operation code o 1 1 1 0 Function o 1 0 0 o 15 This instruction adds three terms together: (Rl) (R2) e the contents of the register specified by the Rl field. the contents of the register specified by the R2 field. the value of the carry indicator at entry. The contents of the register specified by the RI field are unchanged if R 1 and R2 do not specify the same register. The final result replaces the contents of the register specified by the R2 field. Programming Note. This instruction can be used when adding multiple word operands. See Indicators - Multiple Word Operands in Chapter 2. Indicators Carry. Turned on if a carry is detected out of the highorder bit position of the word. If no carry is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the sum cannot be represented in one word; i.e., if the sum is less than _2 15 or greater than +2 15 _1. If an overflow occurs, the result contains the correct low-order 16 bits of the sum; the carry indicator contains the high-order (sign) bit. Even. Unchanged. Zero. If on at entry, set to reflect the result. If off at entry, remains off. Negative. Changed to reflect the result. Program Check Conditions No program checks occur. c 6-8 GA34-0022 AWl o Add Word Immediate (AWl) Storage Immediate Format Register Immediate Long Format AWl AWl word,reg[,reg] IIUf!pe~ati:,n ~od: II 1 word,addr4 1 o 1 R2 Rl 1 4 5 1 (\ IV 7 8 ~un~tio: v v 10 11 V • I i' 15 Format without appended word for effective addressing (AM = 00 or 01) I t Operation ~Od~ ~ fU 1 U U UIU 045 31 The immediate field is added to the contents of the register specified by the Rl field. The result is placed in the register specified by the R2 field. The contents of the register specified by the Rl field are unchanged if Rl and R2 do not specify the same register. Indicators Carry. Turned on if a carry is detected out of the highorder bit position of the word. If no carry is detected, the carry indicator is reset. c Overflow. Cleared, then turned on if the sum cannot be represented in one word~Le., if the sum is less than _2 15 or greater than +2 15 -1. If an overflow occurs, the result contains the correct low-order 16 bits of the sum~ the carry indicator contains the high-order (sign) bit. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions Invalid Storage Address. Instruction word. ! 9 I liVV.a., 101112 15 Immediate Immediate 16 ~ 1 RB 1 AM I. Fu::ct~on, OU! 7 8 16 31 Format with appended word for effective addressing (AM = 10 or 11) Operation code o o 100 0 4 5 7 8 9 10 11 12 15 Address/ Displacement -Displa~m-;nti - - -DTsplac~m;nt2- 16 2324 31 Immediate 32 47 The immediate field is added to the contents of the location specified by the effedive address. (See Effective Address Generation in Chapter 2.) The result replaces the contents of the storage location specified by the effective address. Bits 5-7 of the instruction are not used and must be set to zero to avoid future code obsolescence. The immediate operand is unchanged. Indicators Carry. Turned on if a carry is detected out o(the highorder bit position of the word. If no carry is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the sum cannot be represented in one word ~ Le., if the sum is less than _2 15 or greater than +2 15 _1. If an overflow occurs, the result contains the correct low-order 16 bits of the sum; the carry indicator contains the high-order (sign) bit. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions o Invalid Storage Address. Instruction word or operand. Specification Check. Even byte boundary violation (indirect address or operand address). Instructions 6-9 iB BAL Branch Unconditional (B) Branch and Link (BAL) B BAL longaddr Extended Assembler Mnemonic BX vcon Branch External Extended Assembler Mnemonic BALX vcon,reg Branch and Link External Operation code o o o ~ direct address 1 = indirect address ~ l~ o = direct address 1 ~I. 31 An effective branch address is generated and loaded into the instruction address register, becoming the next instruction to be fetched. The effective branch address is generated as follows: 1. The address field is added to the contents of the register specified by the R2 field to form a main storage address. If the R2 field equals zero, no register contributes to the address generation. The contents of R2 are not changed. 2. Instruction bit 11 is tested for direct or indirect addressing: Bit 11=0. The result from step 1 is a direct address and is loaded into the instruction address register. Bit 11=1. The result from step 1 is an indirect address. "The contents of the main storage location specified by the result are loaded into the instruction address register. Bits 5-7 of the instruction are not used and must be set to zero to avoid future code obsolescence. Indicators No indicators are changed. Program Check Conditions Invalid Storage Address. Instruction word or effective branch address. Specification Check. Even byte boundary violation (indirect address or branch address). } ~ = indirect address Address- ________________ 16 101 o f A_d_d_re_~ _____________ 16 31 The updated value of the instruction address register (the address of the next sequential instruction) is stored into the register specified by the Rl field. An effective branch address is then generated and loaded into the instruction address register, becoming the next instruction to be fetched. The effective branch address is generated as follows: 1. The address field is added to the contents of the register specified by the R2 field to form a main storage address. If the R2 field equals zero, no register contributes to the address generation. The contents of R2 are not changed. 2. Instruction bit 11 is tested for direct or indirect addressing: Bit 11 =0. The result from step 1 is a direct address and is loaded into the instruction address register. Bit 11=1. The result from step 1 is an indirect address. The contents of the main storage location specified by the result are loaded into the instruction address register. GA34-0022 ,, ( ~ Programming Note. If RI and R2 specify the same register the initial contents are used in effective address computation and subsequently overwritten by the return data. Indicators No indicators are changed. Program Check Conditions Invalid Storage Address. Instruction word or effective branch address. No branch is taken, but the contents of the register specified by the RI field are still changed. Specification Check. Even byte boundary violation (indirect address or branch address). No branch is taken but the contents of the RI register are changed. 6-10 o Operation code 1 1 0 o longaddr ,reg c BALS c Branch and Link Short (BALS) BALS (reg,jdisp)* (reg)* addr* Operation code Word displacement 1 1 1 o 4 5 7 8 15 The updated contents of the instruction address register (the location of the next sequential instruction) are stored in register 7. Bit 8 of the word displacement field is propagated left by 7 bit positions and a zero is appended at the low order end, resulting in a 16-bit word. (Word displacement is converted to a byte displacement.) This value is added to the contents of the register specified by R to form an effective address. The contents of the storage location specified by the effective address are stored into the instruction address register, and become the address of the next instruction to be fetched. Programming Note. If the implied register (R7) is used as a c base register, the initial contents of R7 are used in effective address computation and subsequently overwritten by the return data. Indicators No indicators are changed. Program Check Conditions Invalid Storage Address. Effective address. Branching does not occur but storing of the updated instruction address into R7 does occur. Specification Check. Even byte boundary violation (effective address). Branching does not occur but storing of the updated instruction address into R7 does occur. o Instructions 6-11 Be Branch On Condition (BC) Mnemonic BC Operand syntax cond,longaddr Extended Mnemonic BE BOFF BZ BP BMIX BN BON BEV BLT Operand syntax longaddr longaddr longaddr longaddr longaddr longaddr longaddr longaddr longaddr BLE longaddr BLLE longaddr BCY BLLT longaddr longaddr Instruction name Branch on Condition Instruction name Branch on Equal Branch if Orf Branch on Zero Branch on Positive Branch if Mixed Branch if Negative Branch if On Branch on Even Branch on Arithmetically Less Than Branch on Arithmetically Less Than or Equal Branch on Logically Less Than or Equal Branch on Carry Branch on Logically Less Than Operation code Condition field bits (see Any value listed below 11) a 101 o 4 100 101 110 111 111 7 = indirect address 8 } 1011 12 15 ~ Address II) all 11 0= direct address 1 Condition field bits (see 000 000 000 001 001 010 010 5 16 31 This instruction tests the condition of the various indicators (LSR bits 0-4). If the condition tested is met, the effective branch address is loaded into the instruction address register and becomes the next address to be fetched. If the condition tested is not met, the next sequential instruction is fetched. The effective branch address is generated as follows: 1. The address field is added to the contents of the register specified by the R2 field to form a main storage address. If the R2 field equals zero, no register contributes to the address generation. The contents of R2 are not changed. 2. Instruction bit 11 is tested for direct or indirect addressing: Bit 11 =0. The result from step 1 is a direct address and is loaded into the instruction address register. Bit 11 =1. The result from step 1 is an indirect address. The contents of the main storage location specified by the result are loaded into the instruction address register. Indicators All indicators are unchanged. Program Check Conditions Invalid Storage Address. Instruction word or effective address. Specification Check. Even byte boundary violation (indirect address or branch address). 6-12 GA34-0022 (J Bee c Branch On Condition Code (BCC) Bec Indicators No indicators are changed. cond,longaddr Extended mnemonic BNER longaddr Program Check Conditions Branch on Not Error (CC field = 111) Specification Check. Even byte boundary violation (indirect address or branch address). Operation code o 1 1 0 o 1 4 0= direct address I/O Condition Codes The I/O condition codes are summarized in the following tables. Refer to Chapter 4 for a detailed description of each condition code value. Also refer to the specific I/O device descriptions because some devices do not report all condition codes. }~ 1 = indirect address Address 31 16 The value of the CC field is compared to the even, carry, and overflow indicators. These indicators hold the I/O condition code: (1) following an I/O instruction or (2) following an I/O interrupt. c CC bit 5 6 7 Invalid Storage Address. Instruction word or effective address. Indicator Even Carry Overflow If the conditions match, an effective branch address is generated and loaded into the instruction address register, becoming the next instruction to be fetched. If the conditions do not match the next sequential instruction is fetched. The effective branch address is generated as follows: The address field is added to the contents of the register specified by the R2 field to form a main storage address. If the R2 field equals zero, no register contributes to the address generation. The contents of R2 are not changed. 2. Instruction bit 11 is tested for direct or indirect addressing: Bit 11 =0. The result from step 1 is a direct address and is loaded into the instruction address register. Bit 11=1. The result from step 1 is an indirect address. The contents of the main storage location specified by the result are loaded into the instruction address register. Condition Codes Reported After I/O Instruction. Condition Code 0 1 2 3 4 5 6 7 Indicators Even 0 0 0 0 1 1 1 Carry 0 0 1 1 0 0 1 Overflow 0 1 0 1 0 1 0 Meaning Device not attached Busy Busy after reset Command reject Intervention required Interface data check Controller busy Satisfactory Condition Codes Reported During an I/O Interrupt. Condition Code 0 1. 2 3 4 5 6 7 Indicators Even 0 0 0 0 Carry Overflow Meaning Controller end 0 0 PCI (program control 0 1 interrupt) Exception 1 0 Device end 1 1 Attention 0 0 0 1 Attention and PCI 0 Attention and exception 1 Attention and device end o Instructions 6-13 BNC Branch On Not Condition (BNC) Mnemonic BNC Operand syntax cond,longaddr Extended Mnemonic BNE BNZ BNOFF BNP BNMIX BNN Operand syntax longaddr longaddr longaddr longaddr longaddr longaddr BNON BNEV BGE longaddr longaddr longaddr BGT longaddr BLGT longaddr BLGE longaddr BNCY longaddr Instruction name Branch on Not Condition Condition field bits (see Any value listed below It) Condition field bits Instruction name (see Branch on Not Equal 000 Branch on Not Zero 000 Branch if Not OFF 000 Branch on Not Positive 001 Branch on Not Mixed 001 Branch on Not 010 Negative 010 Branch if Not On Branch on Not Even 011 Branch on Arith100 metically Greater Than or Equal Branch on Arith101 metically Greater Than 110 Branch on Logically Greater Than Branch on Logically 111 Greater Than or Equal Branch on No Carry 111 It ) o 1 0 1 4 8 0= direct address } 1 = indirect address 101112 15 ~ (\,~( . 1. The address field is added to the contents of the register specified by the R2 field to form a main storage address. If the R2 field equals zero, no register contributes to the address generation. The contents of R2 are not changed. 2. Instruction bit 11 is tested for direct or indirect addressing: Bit 11 =0. The result from step 1 is a direct address and is loaded into the instruction address register. Bit 11=1. The result from step 1 is an indirect address. The contents of the main storage location specified by the result are loaded into the instruction address register. Indicators All indicators are unchanged. Program Check Conditions Invalid Storage Address. Instruction word or effective address. Operation code 0 This instruction tests the various indicators (LSR bits 0-4). If the condition tested is met, the effective branch address is loaded into the instruction address register and becomes the next address to be fetched. If the condition tested is not met, the next sequential instruction is fetched. The effective branch address is generated as follows: ! ." \ , Specification Check. Even byte boundary violation (indirect address or branch address). Address 16 31 c 6-14· GA34-0022 BNCC c Branch On Not Condition Code (BNCC) BNCC cond,longaddr Extended mnemonic BER longaddr Operation code o 1 1 0 1 o 4 5 Program Check Conditions Branch on Error (CC Field=l11) Invalid Storage Address. Instruction word or effective address. Specification Check. Even byte boundary violation (indirect address or branch address). 7 8 o = direct address } 101112 15 ~ I/O Condition Codes The I/O condition codes are summarized in the following tables. Refer to Chapter 4 for a detailed description of each condition code value. Also refer to the specific I/O device descriptions because some devices do not report all condition codes. 1 = indirect address Address 16 31 The value of the CC field is compared to the even, carry, and overflow indicators. These indicators hold the I/O conditions code: (1) following an I/O instruction or (2) following an I/O interrupt. c CCbit 5 6 7 Indicator Even Carry Overflow If the conditions do not match, an effective branch address is generated and loaded into the instruction address register, becoming the next instruction to be fetched. If the conditions match, the next sequential instruction is fetched. The effective branch address is generated as follows: 1. Indicators No indicators are changed. The address field is added to the contents of the register specified by the R2 field to form a main storage address. If the R2 field equals zero, no register contributes to the address generation. The contents of R2 are not changed. 2. Instruction bit 11 is tested for direct or indirect addressing: Bit 11 =0. The result from step 1 is a direct address and is loaded into the instruction address register. Bit 11=1. The result from step 1 is an indirect address. The contents of the main storage location specified by the result are loaded into the instruction address register. Condition Codes Reported After I/O Instruction. Condition Code 0 1 2 3 4 5 Indicators Even 0 0 0 0 1 1 6 7 Carry Overflow Meaning 0 0 Device not attached Busy 0 1 1 0 Busy after reset 1 Command reject 1 0 0 Intervention required 0 Interface data check 1 1 0 Controller busy Satisfactory 1 1 Condition Codes Reported During an I/O Interrupt. Condition Code 0 1 Indicators Even 0 0 2 3 0 0 4 5 6 7 1 Carry Overflow Meaning Controller end 0 0 PCI (program controlled 0 1 interrupt) Exception 0 1 Device end 1 Attention 0 0 0 Attention and PCI 1 1 Attention and Exception 0 Attention and device end 1 o Instructions 6-15 BNOV BOV Branch On Not Overflow (BNOV) Branch On Overflow (BOV) BOV longaddr BNOV Operation code Operation code o 1 101 o 4 o o 5 10 11 12 7 8 o = direct address } 15 ~ 1 101 4 5 7 0= direct address 10 11 12 8 } 15 ~ 1 = indirect address 1 = indirect address Address Address 16 () longaddr 31 16 31 The overflow indicator is tested. If the indicator is off, the effective branch address is loaded into the instruction address register and becomes the next address to be fetched. If the overflow indicator is on, the next sequential instruction is fetched. The effective branch address is generated as follows: The overflow indicator is tested. If the indicator is on, the effective branch address is loaded into the instruction address register and becomes the next address to be fetched. If the overflow indicator is off, the next sequential instruction is fetched. The effective branch address is generated as follows: 1. The address field is added to the contents of the register specified by the R2 field to form a main storage address. If the R2 field equals zero, no register contributes to the address generation. The contents of R2 are not changed. 2. Instruction bit 11 is tested for direct or indirect addressing: Bit 11=0. The result from step 1 is a direct address and is loaded into the instruction address register. Bit 11=1. The result from step 1 is an indirect address. The contents of the main storage location specified by the result are loaded into the instruction address register. Bits 5-7 of the instruction are not used and must be set to zero to avoid future code obsolescence. 1. The address field is added to the contents of the register specified by the R2 field to form a main storage aq.dress. If the R2 field equals zero, no register contributes to the address generation. The contents of R2 are not changed. 2. Instruction bit 11 is tested for direct or indirect addressing: Bit 11=0. The result from step 1 is a direct address and is loaded into the instruction address register. Bit 11=1. The result from step 1 is an indirect address. The contents of the main storage location specified by the result are loaded into the instruction address register. Bits 5-7 of the instruction are not used and must be set to zero to avoid future code obsolescence. Indicators All indicators are unchanged. Indicators All indicators are unchanged. Program Check Conditions Program Check Conditions Invalid Storage Address. Instruction word or effective address. Invalid Storage Address. Instruction word or effective address. Specification Check. Even byte boundary violation (indirect address or branch address). Specification Check. Even byte boundary violation (indirect address or branch address). ( ". /' 6-16 GA34-0022 BXS c Branch Indexed Short (BXS) (reg l -7 jdisp) (reg l - 7 ) addr BXS Operation code o o Word displacement 1 010 4 5 7 ..--.,..- 8 15 1 - 7 Bit 8 of the word displacement field is propagated left seven bit positions and a zero is appended at the low order end, resulting in a 16-bit word. (Word displacement is converted to a byte displacement.) This value is added to the contents of the register specified by the R field, and the result is stored into the instruction address register, becoming the address of the next instruction to be fetched. Note. The hardware format of this instruction is identical to the format used for the Jump Unconditional (1) and No Operation (NaP) instructions. Indicators No indicators are changed. c Program Check Conditions Invalid Storage Address. Effective address. Specification Check. Even byte boundary violation (branch address). o Instructions 6-17 CB. Compare Byte (CB) Storage/Storage Format Register/Storage Format CB CB addrS ,addr4 addr4,reg Operation code 1 000 0 Operation code o 1 1 0 0 0 o - - - -~ddress/Displac.:!..!!!en~ - - - - ------, r -___ _ _ --I Displacemen.!....! _ T Displaceme~ 2_ _ ...J L__ 16 23 24 31 The contents of the location specified by the effective address in main storage are subtracted from the least significant byte of the register specified by the R field. (Effective Address Generation is explained in Chapter 2.) Neither operand is changed. Bit 12 of the instruction is not used and must be set to zero to avoid future code obsolescence. The address arguments generate the effective addresses of the two operands in main storage. (Effective Address Generation is explained in Chapter 2.) Byte operand 1 is subtracted from byte operand 2. Neither operand is changed. Indicators Carry. Turned on by the detection of a borrow beyond the high-order bit position of the byte. If no borrow is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the difference cannot be represented in one byte; i.e., if the difference is less than _27 or greater than +2 7-1. Even, Negative, and Zero. Changed to reflect the result. Indicators Carry. Turned on by the detection of a borrow beyond the high-order bit position of the byte. If no borrow is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the difference cannot be represented in one byte; i.e., if the difference is less than _27 or greater than +2 7-1. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions Invalid Storage Address. Instruction word or operand. Program Check Conditions Specification Check. Even byte boundary violation (indirect address). Invalid Storage Address. Instruction word or operand. The instruction is terminated. If AMI equals 01 and the operand 2 effective address is invalid, RB 1 is incremented. Specification Check. Even byte boundary violation (indirect address). 6-18 GA34-0022 o CBI c Compare Byte Immediate (CBI) CBI byte,reg I I Ope,ation code 1 1 1 1 0 R Immediate !5 The immediate field is extended to 16 bits by sign propagation to the eight high-order bit positions. The result is subtracted from the contents of the register specified by the R field. Neither operand is changed. Indicators Carry. Turned on by the detection of a borrow beyond the high-order bit position of the word. If no borrow is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the difference cannot be represented in one word~ i.e., if the difference is less than _2 15 or greater than +2 15 _l. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions No program checks occur. c o Instructions 6-19 CD Compare Doubleword (CD) Storage/Storage Format Register/Storage Format CD CD (1 addrS ,addr4 addr4,reg Operation code 10010 o 4 5 Operation code 1 1 0 1 0 4 5 o 7 8 9 10 11 12 15 r - ~ -- ---, r- ________ Displac~e-;rt I ..l '_________ - Displace~t2 --I L ,- -- - 789101112131415 - - - A ddress/ Displacement - - L - - - - ___ - - - - -- - - - Address/Displa:!!!,~ Displacement 1 16 - - - - - - - 23 C 24 - _ - - - Displacement 2 - - - - -, _ _" - - I 31- ~ 16 23 24 31 The contents of the doubleword in main storage specified by the effective address are subtracted from the contents of the register pair specified by the R field and R+ 1. (Effective Address Generation is explained in Chapter 2.) Neither operand is changed. Bit 12 of the instruction is not used and must be set to zero to avoid future code obsolescence. If the R field equals 7, register 7 and register 0 are used. - - - ---- - - -- - - - - - - - - -, ~ _ _ _ ~dressIDisPlace!!!!!.!!t_ __ ~ Displacement 1 Displacement 2 J L I --------------------3940 47 32 The address arguments generate the effective addresses of two operands in main storage. (Effective Address Generation is explained in Chapter 2.) Doubleword operand 1 is subtracted from doubleword operand 2. Neither operand is changed. Indicators Indicators Carry. Turned on by the detection of a borrow beyond the high-order bit position of the doubleword. If no borrow is detected, the carry indicator is reset. Carry. Turned on by the detection of a borrow beyond the high-order bit position of the operand. If no borrow is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the difference cannot be represented in the doubleword; i.e., if the difference is less than _2 31 or greater than +2 31 _1. Overflow. Cleared, then turned on if the difference cannot be represented in one doubleword; i.e., if the difference is less than _2 31 or greater than +2 31 _1. Even, Negative, and Zero. Changed to reflect the result. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions Program Check Conditions Invalid Storage Address. Instruction word or operand. Invalid Storage Address. Instruction word or operand. The instruction is terminated. If AMI equals 01 and the operand 2 effective address is invalid, RBI is incremented. Specification Check. Even byte boundary violation (indirect address or operand address). Specification Check. Even byte boundary violation (indirect address or operand address). 6-20 GA34-0022 CFED CFEN c Compare Byte Field Equal and Decrement (CFED) Compare Byte Field Equal and Increment (CFEN) CFED CFEN (reg),(reg) (reg),(reg) loperation code 00101 o I byte count specified in register 7. R2 R1 45 78 o for CFED or CFEN o for CFED; decrement! =J 101112131415 contents of R1 & R2. 1 for CFEN; increment contents of R1 & R2. c This instruction compares two fields in main storage on a byte for byte basis. Register 7 contains the number of bytes to be compared. This number is decremented after each byte is compared. The register specified by Rl contains the address of operand 1. The register specified by R2 contains the address of operand 2. Operand 1 is subtracted from operand 2, but neither operand is changed. After each byte is compared, the addresses in Rl and R2 are incremented or decremented (determined by bit 13 of the instruction). The operation terminates when either: 1. 2. Notes. 1. If the specified count in R7 is zero, the instruction performs no operation (No-op). 2. Variable field length instructions can be interrupted. When this occurs and the interrupted level resumes operation, the processor treats the uncompleted Indicators Carry. Turned on by the detection of a borrow beyond the high-order bit position of the byte. If no borrow is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the difference cannot be represented in one byte; i.e., if the difference is less than _27 or greater than +2 7 -1. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions Invalid Storage Address. Operand. The instruction is terminated. An equal condition is detected, or The number of bytes specified in register 7 has been compared. When an equality occurs, the addresses in the registers point to the next operands to be compared, but the count in R7 is not updated. Bit 11 of the instruction is not used and must be set to zero to avoid future code obsolescence. See Scan Byte Field Equal and Decrement (SF ED) and Scan Byte Field Equal and Increment (SFEN) for other versions of this machine instruction. o Instructions 6-21 CFNED CFNEN Compare Byte Field Not Equal and Decrement (CFNED) Compare Byte Field Not Equal and Increment (CFNEN) (reg),(reg) (reg),(reg) CFNED CFNEN loperation code o 0 1 0 1 o 4 I 5 1. If the specified count in R7 is zero, the instruction performs no operation (no-op). 2. Variable field length instructions can be interrupted. When this occurs and the interrupted level resumes operation, the processor treats the uncompleted instruction as a new instruction with the remaining byte count specified in register 7. Indicators R1 R2 7 8 o for CFNED or CFNEN ofor CFNED; decrement 1011 12131415 ~ contents of R1 & R2. 1 for CFNEN; increment contents of Rl & R2. This instruction compares two fields in main storage on a byte for byte basis. Register 7 contains the number of bytes to be compared. This number is decremented after each byte is compared. The register specified by R1 contains the address of operand 1. The register specified by R2 contains the address of operand 2. Operand 1 is subtracted from operand 2, but neither operand is changed. After each byte is compared, the addresses in R1 and R2 are incremented or decremented (determined by bit 13 of the instruction). The operation terminates when either: 1. 2. Notes. Carry. Turned on by the detection of a borrow beyond the high-order bit position of the byte. If no borrow is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the difference cannot be represented in one byte; i.e., if the difference is less than _27 or greater than +2 7 -1. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions Invalid Storage Address. Operand. The instruction is terminated. ", An unequal condition is detected, or The number of bytes specified in register 7 has been compared. When an inequality occurs, the addresses in the registers point to the next operands to be compared, but the count in R7 is not updated. Bit 11 is not used and must be set to zero to avoid future code obsolescence. See Scan Byte Field Not Equal and Decrement (SFNED) and Scan Byte Field Not Equal and Increment (SFNEN) for other versions of this machine instruction. (~ 6-22 GA34-0022 CMR CPCL o Complement Register (CMR) Copy Current Level (CPCL) CMR CPCL reg [,reg] Operation code Function Operation code Function o 00110 o 1 1 0 0 o 1 1 1 0 4 5 7 8 10 11 15 The contents of the register specified by the Rl field are converted to the two's complement. The result is placed in the register specified by the R2 field. The contents of the register specified by the Rl field are unchanged if Rl and R2 do not specify the same register. Indicators Carry. Reset. Then turned on if the number to be complemented is zero. c reg o 1 1 1 4 5 / ?j lU 11 i5 The register specified by the R2 field is loaded as follows: • Bits 0-13 are set to zero. • Bits 14-15 are set to the binary-encoded current level. F or exam pIe if the current level is three, bits 14-15 are set to 11. Bits 5-7 of the instruction are not used and must be set to zero to avoid future code obsolescence. Indicators All indicators are unchanged. Overflow. Reset. Then turned on if the number to be complemented is the maximum negative number representable. Program Check Conditions Even, Negative, and Zero. Unchanged. Privilege Violate. Privileged instruction. Program Check Conditions No program checks occur. o Instructions 6-23 CPCON CPIMR Copy Console Data Buffer (CPCON) Copy Interrupt Mask Register (CPIMR) CPCON CPIMR reg Operation code Function o Operation code 1 1 0 0 0 o 1 011 o 4 1 111 o 15 The contents of the console data buffer are loaded into the register specified by the R2 field. The contents of the buffer are unchanged. Bits 5-7 of the instruction are not used and must be set to zero to avoid future code obsolescence. If the programmer console is not installed, the data loaded into the specified register is undefined. Indicators Carry and Overflow. Unchanged. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions Privilege Violate. Privileged instruction. () addr4 5 789101112 15 The contents of the interrupt mask register are stored at the word location in main storage specified by the effective address. (See Effective Address Generation in Chapter 2.) The interrupt mask register is unchanged. Bits 5-7 of the instruction are not used and must be set to zero to avoid future code obsolescence. The mask is represented in a bit significant manner as follows: Mask bit Interrupt level o o 1 2 3 1 2 3 Bits 4-15 are set to zero. A mask bit set to "1" indicates that the level is enabled. A mask bit set to "0" indicates that the level is disabled. \. , Indicators Carry and Overflow. Unchanged. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions Invalid Storage Address. Instruction word or operand. Privilege Violate. Privileged instruction. Specification Check. Even byte boundary violation (indirect address or operand address). c 6-24 GA34-0022 CPIPF c Copy In-process Flags (CPIPF) CPIPF addr4 Operation code o o 1 011 4 r - - - - t--- - - - 5 789101112 Address/DispTace;nfflt - - - L _ Displace~n.!....!. 16 15 - - -I - - - - - - -----4 _1 __ D~l~~!1_...J 23 24 31 The in-process flags for each level are stored at the word location in main storage specified by the effective address. (Effective Address Generation is explained in Chapter 2.) The in-process flags are not changed. The flags are stored in a bit significant manner with bit zero representing level zero, and so on. Bits 4-15 are set to zero. Bits 5-7 of the instruction are not used and must be set to zero to avoid future code obsolescence. This instruction permits the supervisor on the current level to inspect the in-process flags of the other levels. The in-process flag, bit 9 of the level status register, is on when a level is active or pending (previously interrupted by a higher level). c Indicators All indicators are unchanged. Program Check Conditions Invalid Storage Address. Instruction word or operand. Privilege Violate. Privileged instruction. Specification Check. Even byte boundary violation (indirect address or operand address). o Instructions 6-25 CPLB Copy Level Block (CPLB) Program Check Conditions CPLB Invalid Storage Address. Instruction word or the 11 word main storage area. The instruction is terminated. If the main storage area being accessed is partially outside the installed storage size, a partial data transfer occurs. reg,addr4 Operation code o 1 011 o 4 5 789101112 15 (1 Privilege Violate. Privileged instruction. Specification Check. Even byte boundary violation (indirect address or operand address). Level Status Block Format EA This instruction stores a level status block (LSB) into 11 words of main storage beginning with the location specified by the effective address. (Effective Address Generation is explained in Chapter 2.) The contents of the LSB are not changed. The register specified by the R field contains the binary encoded level of the LSB to be stored. The binary encoded level is placed in bits 14-15 of the register. Bits 0-13 are not used and must be zero. Using this one instruction, the supervisor can copy the information contained in the hardware registers assigned to a program operating on any level. Most instructions are restricted to the registers associated with the current level. After executing a CPLB instruction, the supervisor can: 1. Use the information just stored; for example, the contents of the general registers or the LSR. 2. Assign the level to another task by executing a Set Level Block (SELB) instruction that points to a different level status block. In the second case, the supervisor can restart the preempted program at a later time by executing another SELB instruction that points to the previously stored level status block. EA+20 IAR Zeros LSR Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 (+ 14 hex) EA=effective address Format of Register Specified by R in CPLB Instruction I Reserved .0 0 0 0 0 0 0 0 0 0 0 0 0 o o ILevel I , ; 1314 15 Level 0 Levell Level 2 Level 3 o o 0 1 1 0 1 1 Programming Note. If the AM field equals 01, the contents of the register specified by the RB field are incremented by 2. Indicators All indicators are unchanged. c 6-26 GA34-0022 CPLSR CPPSR c Copy Level Status Register (CPLSR) CPLSR Indicators All indicators are unchanged. reg Program Check Conditions Operation code o Function o 1 1 1 0 o 7 8 1 1 1 0 10 11 15 The level status register is loaded into the register specified by the R2 field. The level status register is unchanged. Bits 5-7 of the instruction are not used and must be set to zero to avoid future code obsolescence. Privilege Violate. Privi1eged instruction. Specification Check. Even byte boundary violation (indirect address or operand address). Program Status Word (PSW) Format PSW bit Meaning Indicators All indicators are unchanged. o Program Check Conditions No program checks occur. 4 5 6 Specification check I nvalid storage address Privilege violate Not used Invalid function Not used Stack exception Not used Storage parity check Not used CPU control check I/O check Sequence indicator Auto-IPL Not used Power/thermal warning 1 2 3 Copy Processor Status and Reset (CPPSR) CPPSR addr4 7 8 9 10 11 12 13 14 15 Operation code o c Invalid Storage Address. Instruction word or operand. 1 0 1 o 10 11 12 15 -J r---------------~ - -:- - _Address/ DisPlace'!!..e~ - L- DIsplacement 1 r Displacement 2 16-- - - -2324- - - - - 31 The contents of the processor status word (pSW) are stored at the word location in main storage specified by the effective address. (Effective Address Generation is explained in Chapter 2.) This instruction resets bits 0-12 of the PSW. Bits 13-15 are unchanged. Bits 5-7 of the instruction are not used and must be set to zero to avoid future code obsolescence. o Instructions 6-27 cw Compare Word (CW) Program Check Conditions Register/Register Format Invalid Storage Address. Instruction word or operand. CW Specification Check. Even byte boundary violation (indirect address or operand address). reg,reg Operation code Function o 1 1 1 0 o 4 001 0 5 7 8 10 11 Storage/Storage Format 15 The contents of the register specified by the RI field are subtracted from the contents of the register specified by the R2 field. The contents of both registers are unchanged. CW addrS ,addr4 Operation code 1 000 1 o 4 5 789101112131415 Indicators Carry. Turned on by the detection of a borrow beyond the high-order bit position of the word. If no borrow is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the difference cannot be represented in one word; i.e., if the difference is less than _21S orgreaterthan+2 1S -I. t= L ==__ 32 - - Address/DisPlacement Displacement 1 - - - T 39 40- ---=-= =-JI Displacement 2 - - - - 47 Even, Negative, and Zero. Changed to reflect the result. The address arguments generate the effective addresses of two operands in main storage. (See Effective Address Generation in Chapter 2.) Word operand 1 is subtracted from word operand 2. Neither operand is changed. Program Check Conditions No program checks occur. Register/Storage Format CW Indicators addr4,reg Carry. Turned on by the detection of a borrow beyond the high-order bit position of the word. If no borrow is detected, the carry indicator is reset. Operation code 1 1 0 0 o 1 4 5 789101112 15 ~----------------I I- _ _ _ _ Overflow. Cleared, then turned on if the difference cannot be represented in one word; i.e., if the difference is less than _21 S or greater than +21 S-1. Address/Displacement _ _ - - I L _ Displaceme~ 1_ 16 r_ 23 24 Displac~ent 2 _-.I Even, Negative, and Zero. Changed to reflect the result. 31 Program Check Conditions The contents of the word in main storage specified by the effective address are subtracted from the contents of the register specified by the R field. (Effective Address Generation is explained in Chapter 2.) Both operands are unchanged. Invalid Storage Address. Instruction word or operand. The instruction is terminated. If AMI equals 01 and the operand 2 effective address is invalid, RBI is incremented. Specification Check. Even byte boundary violation (indirect address or operand address). Indicators Carry. Turned on by the detection of a borrow beyond the high-order bit position of the word. If no borrow is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the difference cannot be represented in one word; i.e., if the difference is less than _21 S or greater than +21 s_1. Even, Negative, and Zero. Changed to reflect the result. 6-28 GA34-0022 (: CWI Compare Word Immediate (CWI) Storage Immediate Format Register Immedia~e Long Format CWI eWI word, reg IOperation code IU 1 word,addr4 1 1 o 1 4 I I 5 Rl I IU 7 8 Format without appended word for effective addressing (AM = 00 or 01) I Function U UIU U 10 11 1 I Operation code 1 U 15 IU o 1 I _ _I I IFuncti~n RB U U UIV 4 5 Immediate 16 31 AM I 9 111 _ 11 10 11 12 15 16 Carry. Turned on by the detection of a borrow beyond the high-order bit position of the word. If no borrow is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the difference cannot be represented in one word; i.e., if the difference is less than _2 15 or greater than +2 15 -1. Even, Negative, and Zero. Changed to reflect the result. 31 Format with appended word for effective addressing (AM = 10 or 11) Operation code o o 1 0 0 0 4 5 ___ Indicators Invalid Storage Address. Instruction word. VI 7 8 Immediate The immediate field is subtracted from the contents of the register specified by the R1 field. The contents of the register specified by the R1 field are unchanged. Bits 8-10 are not used and must be set to zero to avoid future code obsolescence. Program Check Conditions (j ~ddress/Displace'!!!!..!:~ Displacement 1 16 15 789101112 _ _ _ Displacement 2 2324 31 Immediate 32 47 The immediate word is subtracted from the contents of the location specified by the effective address. (Effective Address Generation is explained in Chapter 2.) Bits 5-7 are not used and must be set to zero to avoid future code obsolescence. Both operands are unchanged. Indicators Carry. Turned on by the detection of a borrow beyond the high-order bit position of the word. If no borrow is detected, the carry indicator is reset. Overflow. Cleared, then turned on if the difference cannot be represented in one word; i.e., if the difference is less than _2 15 or greater than +2 15 _1. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions Invalid Storage Address. Instruction word or operand. Specification Check. Even byte boundary violation (indirect address or operand address). o Instructions 6-29 DB Divide Byte (DB) DB addr4,reg Operation code 1 1 101 o 4 5 7 8 9 10 11 12 15 A divide operation is performed between the word dividend contained in the register specified by the R field and the byte divisor at the location specified by the effective address. (Effective Address Generation is explained in Chapter 2.) The I-word quotient replaces the contents of the specified register while the I-word remainder is placed in the register specified by R+ I. If the R field specifies register 7, the remainder is placed in register O. EA I R I: I Dividend 0 I R Quotient 0 Divisor • 15 0 R+l IRemainder 15 0 Indicators Overflow. Cleared, then turned on if division by zero is attempted, or if the quotient cannot be represented in one word. If overflow occurs, the remaining indicators and the contents of the specified register are undefined. Carry. Cleared, then turned on (together with the overflow indicator) if the overflow was caused by an attempt to divide by zero. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions Invalid Storage Address. Instruction word or operand. If the AM field equals 0 I, the contents of the register specified by the RB field are incremented. Specification Check. Even byte boundary violation (indirect address). 6-30 GA34-0022 7 15 DD o Divide Doubleword (DO) DD addr4,reg Operation code 1 1 101 o 4 5 r - - - -Addr-;;sIDi;Pia~ement I-- - - - - - - - _ D~1a~en.1..l _, _ L 16 15 789101112 - - - - - - -, -I Qig>lacement 2_ J 23 24 31 A divide operation is performed between the doubleword dividend contained in the registers, specified by the R field and R+ 1, and the word divisor at the location specified by the effective address. (Effective Address Generation is explained in Chapter 2.) The doubleword quotient replaces the contents of the specified registers (least significant word is in R+l). The one-word remainder is placed in the register specified by R+2. The R field wraps from 7 to 0; e.g., if R specifies register 6, registers 6, 7, and 0 are used. R C I 0 31 I • • EA I Divisor 0 15 I I R I 0 I ~Z R+ 1 Quotient R+2 ~ I 31 :0 0 Remainder U 15 Programming Note. If the AM field equals 01, the contents of the register specified by the RB field are incremented by 2. Indicators Overflow. Cleared, then turned on if division by zero is attempted, or if the quotient cannot be represented in a doubleword. If overflow occurs, the remaining indicators and the contents of the specified registers are undefined. Carry. Cleared, then turned on (together with the overflow indicator) if the overflow was caused by an attempt to divide by zero. Even, Negative, and Zero. Changed to reflect the result. o Program Check Conditions Invalid Storage Address. Instruction word or operand. Specification Check. Even byte boundary violation (indirect address or operand address). Instructions 6-31 DIAG Diagnose (DIAG) DIAG Bits 26 ubyte Parameter o 4 5 7 8 15 The Diagnose instruction is used for controlling or testing various hardware functions in a machine dependent manner. The parameter field has the following bit significance. Bits Functions Storage select - word Storage select - byte Local storage register select I/O interface select Must be set to zero Must be set to zero Storage to register Register to storage Set system ID Disable Enable Must be set to zero 8&9 = 00 = 01 = 10 =11 10 11 12 = unused = unused =0 =1 13 =1 14 =0 15 = 1 = unused Functions Storage Select - Word. Storage Select - Byte. These functions, with bit 14 (enable/disable function), allow the inhibiting of storage parity generation or parity checking for the data cycle executed within the instruction. Bit 12 (storage to register/ register to storage function) specifies the direction of the data transfer. The storage address for this storage cycle is contained in register 7 of the current active level. The data is contained in register 0 of the current active level. Local Storage Register Select. This function transfers data between main storage and any local storage location by directly addressing local storage. Two additional words are appended to the Diagnose instruction when this function is specified. Additional words when accessin local storage Stack address 000 16 0 0 0 0 0 0 2526 I 31 47 Significance Must be set to zero Local storage address Immediate data field Bit 12 of the Parameter field specifies the direction of the data transfer. Bit 12 =0 =1 Immediate data field to local storage Local storage to immediate data field The following chart shows the addresses for the registers in local storage. 6-32 GA34-0022 29 o o o o 1 1 1 1 o 0 0 0 0 o 1 1 1 o 1 1 1 011 1 000 000 000 000 100 1 o 100 100 100 101 101 101 101 101 1 0 1 0 1 1 1 0 0 0 0 30 o o 1 1 0 1 1 0 1 0 1 1 0 1 o o o 1 1 o o 1 1 1 0 I 0 1 0 1 o o 0 1 0 I I 0 1 0 o o I I 1 1 o 0 1 0 o 1 1 0 o I o 1 0 1 1 o o 0 1 0 1 1 0 1 o o 1 I o o I 0 1 0 1 o I I 1 0 0 100 1 0 0 101 31 0 o o o 1 1 100 The bits in these words are defined as follows: Bits 16-25 26-31 32-47 28 o Immediate dat. 32 27 000 0 o 0 0 0 o 0 0 0 0 0 0 000 1 000 1 000 1 000 1 001 0 001 0 001 0 001 0 001 1 001 001 001 1 o 1 0 0 o 1 0 0 000 000 001 001 o 0 1 001 I o o 1 1 0 1 0 I 0 1 0 1 1 o o 0 I 0 o o o 1 1 1 1 1 1 1 1 1 0 0 0 0 o o 0 I 0 1 1 1 1 111 1 1 1 1 1 o o 0 I I I o I Register Selected Work Reg 2 Work Reg 3 PSW Mask SAR LvI 0 IAR Work Reg C LvI 0 LSR Lvi 0 Reg 0 LvI 0 Reg 1 Lvi 0 Reg 2 Lvi 0 Reg 3 LvI 0 Reg 4 Lvi 0 Reg 5 Lvi 0 Reg 6 Lvi 0 Reg 7 Address Compare Reg Spare CIAR Console Data Reg Spare Lvi 1 IAR Work Reg D LvII LSR LvII Reg 0 LvII Reg 1 LvII Reg 2 LvII Reg 3 LvII Reg 4 LvII Reg 5 Lv!! RegJi LvII Reg 7 Work Reg 0 Data Buffer Spare Spare Spare Lv12 IAR Work Reg E Lvi 2 LSR Lvi 2 Reg 0 Lvi 2 Reg 1 Lvi 2 Reg 2 Lvi 2 Reg 3 Lvi 2 Reg 4 LvI 2 Reg 5 Lvi 2 Reg 6 Lvi 2 Reg 7 Work Reg 1 Work Reg 4 Spare Spare Spare LvI 3 IAR Work Reg F LvI 3 LSR Lvi 3 Reg 0 Lvi 3 Reg 1 LvI 3 Reg 2 Lvi 3 Reg 3 Lvi 3 Reg 4 Lvi 3 Reg 5 LvI 3 Reg 6 Lvi 3 Reg 7 ( \. " ; DIS o I/O Interface Select. This function, with bit 14 equal to 0, disables and logically isolates the interrupt and cycle steal request lines on the I/O interface from the channel. When bit 14 equals 1, these lines are enabled. Thi~ function snecifies the direction of data transfer for storage and local storage functions. ~tOl'~OP to ~tornop -- - - - - - " C ' - - ...... - - 0 - .... Set System ID. This function sets the system model number into bits 14-15 of register 0 of the current active level. Bits 0-13 are set to zeros. If this function is specified, all other functions in the parameter field are ignored. The system ID for the 4953 processor is 03 (hex) and register 0 is set as follows: Register 0 0 0 0 0 0 0 0 0 0 0 o 1 11 131415 Disable. Enable. This function disables or enables parity generation checking. See functions Storage Select and I/O Interface Select. c DIS ubyte Operation code Storage to Register. 1000 0 Disable (DIS) o 1 1 0 0 o 4 Parameter 5 7 8 15 The facilities designated by one bits in the parameter field are disabled. The bits in the parameter field have the following significance: Bit 8 9 10 11 12 13 14 15 Facility Not used Not used Not used Not used Not used Not used Not used Summary mask Note. Bits not used must be set to zero to avoid future code obsolescence. Indicators No indicators are changed. Program Check Conditions Program Check Conditions Privilege Violate. Privileged instruction. Privilege Violate. Privileged instruction. o Instructions 6-33 DW Divide Word (OW) OW addr4,reg Operation code 1 1 0 o 4 5 789101112 15 A divide operation is performed between the word dividend contained in the register specified by the R field and the word divisor at the location specified by the effective address. (Effective Address Generation is explained in Chapter 2.) The one word quotient replaces the contents of the specified register. The one word remainder is placed in the register specified by R+ 1 . The R field wraps from 7 to 0; that is, if R specifies register 7, registers 7 and 0 are used. +1 R Dividend 15 0 EA Divisor 0 t '" \ , I n R+i L' Quotient Remaind., 15 0 0 Indicators Overflow. Cleared, then turned on if division by zero is attempted, or if the quotient cannot be represented in one word. If overflow occurs, the remaining indicators and the contents of the specified registers are undefined. Carry. Cleared, then turned on (together with the overflow indicator) if the overflow was caused by an attempt to divide by zero. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions Invalid Storage Address. Instruction word or operand. Specification Check. Even byte boundary violation (indirect address or operand address). 6-34 15 GA34-0022 15 EN o Enable (EN) EN ubyte Operation code o Parameter 1 1 0 0 The facilities designated by one bits in the parameter field are enabled. The bits in the parameter field have the following significance: Bit 8 9 10 11 12 13 14 15 Facility Not used Not used Not used Not used Not used Not used Not used Summary mask Note. Bits not used must be set to zero to avoid future code obsolescence. Indicators No indicators are changed. C Program Check Conditions Privilege Violate. Privileged instruction. o Instructions 6-35 FFD· FFN Note. Variable field length instructions can be interrupted. When this occurs and the interrupted level resumes operation, the processor treats the uncompleted instruction as a new instruction with the remaining byte count specified in register 7. Fill Byte Field and Decrement (FFD) Fill Byte Field and Increment (FFN) FFD FFN reg,(reg) reg,(reg) I I Operation code 00101 o 4 5 for FFD or FFN o Indicators Carry . Unchanged. R1 R2 Overflow. Unchanged. 7 8 10 11 12 13 14 15 --~ Program Check Conditions for FFD; decrement contents of R2 for FFN; increment contents ofR2 Invalid Storage Address. Operand. The instruction is terminated. This instruction fills all bytes of a field in main storage with the same bit configuration in each byte. Register 7 contains the number of bytes to be filled (field length). If a field length of zero is specified, the instruction is a no-op. The register specified by Rl contains, in bits 8-15, the byte used to fill the field. The register specified by R2 contains the starting address of the field in main storage. After each byte in the field is filled: 1. The address in R2 is either incremented 2. determined by bit 13 of the instruction. This permits filling the field in either direction. The length count in R7 is decremented. 01 del.:H::mt:nlt:u, The operation ends when the specified field length has been filled (contents of R7 equal zero). At this time, the address in R2 has been updated and points to the byte adjacent to the end of the field. Bits 11 and 15 of the instruction are not used and must be set to zero to avoid future code obsolescence. See Move Byte Field and Decrement (MVFD) and Move Byte Field and Increment (MVFN) for other versions of this machine instruction. 6-36 GA34.-0022 Even, Negative, and Zero. Changed to reflect that result of the last byte moved. o 10 IR c Operate I/O (10) Indicators Refer to Chapter 4 for a detailed description concerning the operation of this instruction. longaddr 10 Even, Carry, and Overflow. Changed to reflect the condition code. See Branch on Condition Code (BCC) or Branch on Not Condition Code (BNCC) instructions. Negative and Zero. These indicators are not changed. Opera tion code o 1 1 0 o 1 4 5 Program Check Conditions 7 8 o = direct address } 1 = indirect address 10 11 12 15 ~ Invalid Storage Address. Instruction word or operand. Privilege Violate. Privileged instruction. Specification Check. Even byte boundary violation (indirect address or operand address). Address Interchange Registers (IR) 31 16 An effective main storage address is generated as follows: c 1. The address field is added to the contents of the register specified by the R2 field. If the R2 field equals zero, no register contributes to the address generation. 2. Instruction bit 11 is tested for direct or indirect addressing: Bit 11 =0 (Direct Address). The result from step 1 is the effective address. Bit 11=1 (Indirect Address). The result from step 1 is the address of the main storage location that contains the effective address. Bits 5-7 of the instruction are not used and must be set to zero to avoid future code obsolescence. The effective address specifies the location of a twoword control block, called the immediate device control block (lOCB). The IDCB contains the command, device address, and a one-word immediate data field: IR reg,reg Operation code Function o 1 110 o 4 5 001 7 8 10 11 1 15 The contents of the register specified by the Rl and R2 fields are interchanged. Indicators Carry and Overflow. Unchanged. Even, Negative, and Zero. Changed to reflect the operand moved from Rl to R2. Program Check Conditions No program checks occur. IDeB (immediate device control block) I I Device address field Command field o 7 8 15 IImmediate data field 16 31 The immediate data field serves two purposes: 1. o For direct program control (DPC) operations, it holds the data transferred to or from the I/O device. 2. For cycle steal operations, it holds the address of the device control block (DCB). Refer to Chapter 4 for additional information. Instructions 6-37 J, '; JAL Jump Unconditional (J) Jump and Link (J AL) J JAL jdisp jaddr Operation code o o Operation code Word displacement Word displacement 10011 1 010 4 ( .J) jdisp,reg jaddr,reg 5 7 ~ 8 15 o 4 5 15 Zero Bit 8 of the word displacement field is propagated left seven bit positions and a zero is appended at the low order end, resulting in a 16-bit word. (Word displacement is converted to a byte displacement.) This value is added to the updated value of the instruction address register becoming the address of the next instruction to be fetched. Note. The hardware format of this instruction is identical to the format used for the Branch Indexed Short (BXS) instruction. Indicators No indicators are changed. Program Check Conditions Invalid Storage Address. Effective address. Specification Check. Even byte boundary violation (branch address). The updated value of the instruction address register (the location of the next sequential instruction) is stored into the register specified by the R field. Bit 8 of the word displacement field is propagated left by seven bit positions and a zero is appended at the low order end, resulting in a 16-bit word. (The word displacement is converted to a byte displacement.) This value is added to the updated contents of the instruction address register, and the result is stored in the instruction address register, becoming the address of the next instruction to be fetched. Indicators No indicators are changed. Program Check Conditions Invalid Storage Address. Effective address. The instruction is terminated. Branching does not occur, but the storing of the updated instruction address into the register specified by the R field still occurs. c 6-38, GA34-0022 JC -, C Jump On Condition (JC) a Mnemonic JC Operand syntax condjdisp condjaddr Instruction name Jump on Condition Operation code Condition field bits (see Any value listed below 11) Condition Extended Mnemonic JE JOFF JZ JMIX JP JON IN JEV JLT JLE c JLLE JCY JLLT Operand syntax jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jield 11) 000 I o bits (see 000 Jump if Off 000 Jump on Zero 000 Jump if Mixed 001 Jump on Positive 001 Jump if On 010 Jump on Negative 010 Jump on Even 011 Indicators No indicators are changed. Jump on Arithmetically Less Than Jump on Arithmetically Less Than or Equal Jump on Logically Less Than or Equal Jump on Carry 100 Program Check Conditions Jump on Logically Less Than 15 This instruction tests the condition of the various indicators set by a previously executed instruction (for example: an arithmetic, compare, test bit, or test word type of instruction) . If the condition tested is met, bit 8 of the word displacement field is propagated left by seven bit positions and a zero is appended at the low-order end resulting in a 16-bit word. (Word displacement is converted to a byte displacement.) This value is added to the updated value of the instruction address register, becoming the address of the next instruction to be fetched. If the condition tested is not met, the next sequential instruction is fetched. For additional information about the indicator settings for the various conditions, see Chapter 2. Instruction name Jump on Equal 101 Word displacement 0 Invalid Storage Address. Effective address. 110 111 111 o Instructions 6-39 JeT Note. When the register contents are not zero, the word displacement is converted to a byte displacement as follows. Bit 8 of the word displacement field is propagated left by seven bit positions, and a zero is appended at the low-order end. This results in a 16-bit word that has been doubled in magnitude. Jump On Count (JCT) JeT jdisp,reg jaddr,reg Operation code Word displacement 10111 o 4 5 7 8 Indicators No indicators are changed. 15 This instruction tests the contents of the register specified by the R field. If the register contents are not zero, the contents are decremented by one. If the register contents are still not zero, the word displacement is converted to a byte displacement and added to the updated contents of the updated instruction address register (JAR). This value indicates the location of the next instruction to be fetched. If the register contents are zero when initially tested, no decrementing occurs. In this case, or when the register contents are zero after decrementing, the next sequential instruction is fetched. Program Check Conditions Invalid Storage Address. Effective address. The jump does not occur, but the contents of the register specified by the R field are still decremented by one. JeT No Yes Subtract 1 from reg contents Yes Add the byte displacement to the IAR No jump Jump (~ 6-40 GA34-0022 JNC LEX Jump On Not Condition (JNC) G ,- Mnemonic JNC Extended Mnemonic JNE JNOFF JNZ JNMIX JNP JNON JNN JNEV JGE C JGT JLGT JLGE JNCY Operand syntax condjdisp condjaddr Operand syntax jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr jdisp jaddr Operation code Condition field bits (see Any value listed below 11) Instruction name Jump on Not Condition Condition field bits (see iii) Instruction name Jump on Not Equal 000 Jump if Not Off 000 Jump on Not Zero 000 Jump on Not Mixed 001 Jump on Not Positive 001 Jump if Not On 010 Jump on Not Negative 010 Jump on Not Even 011 Jump on Arithmetically Greater Than or Equal Jump on Arithmetically Greater Than Jump on Logically Greater Than Jump on Logically Greater Than or Equal Jump on No Carry 100 101 110 111 111 Word displacement 000 1 o 15 Indicators No indicators are changed. Program Check Conditions Invalid Storage Address. Effective address. Level Exit (LEX) LEX fubyte] Parameter 15 When this instruction is executed, the processor exits the current level. The in-process flag (LSR bit 9) for the current level is turned off. Next the instruction tests for (1) pending levels or outstanding priority interrupt requests, (2) the condition of the summary mask (LSR bit 11), and (3) the condition of the level mask bits. • If pending levels or outstanding requests exist and the summary mask and level mask is enabled: A branch is executed to the address contained in the IAR of the highest pending or requesting level. This level then becomes the current level and processing resumes. • If processing levels or outstanding requests exist and the summary mask is disabled: The priority interrupts are not allowed. The highest pending level becomes the current level and processing resumes. If no levels are pending, the processor goes to the wait state. • If no levels are pending and no interrupt requests are outstanding, the processor goes to the wait state. For additional information on level switching, refer to Chapter 3. Programming Note. When a level is exited by a LEX o This instruction tests the condition of the various indicators set by a previously executed instruction (for example: an arithmetic, compare, test bit, or test word type of instruction). If the condition tested is met, bit 8 of the word displacement field is propagated left by seven bit positions and a zero is appended at the low-order end resulting in a 16-bit word. (Word displacement is converted to a byte displacement.) This value is added to the updated value of the instruction address register, becoming the address of the next instruction to be fetched. If the condition tested is not met, the next sequential instruction is fetched. For additional information about the indicator settings for the various conditions, see Chapter 2. instruction .and processing is to continue on a pending level, one instruction is executed on the pending level prior to sampling for a trace class interrupt. Indicators No indicators are changed. Program Check Conditions Privilege Violate. Privileged instruction. Instructions 6-41 LMB Load Multiple and Branch (LMB) Refer to Stack Operations in Chapter 2 for a detailed description concerning the operation of this instruction. The LMB instruction is used in conjunction with the Store Multiple (STM) instruction described later in this chapter. LMB· addr4 Opera (ion code o o 1 000 4 5 7 8 9 10 11 12 The contents of the registers for the current level are loaded from the stack defined by the stack control block pOinted to by the effective address. (Effective Address Generation is explained in Chapter 2.) The registers to be loaded are defined by the stack entry previously stored by a Store Multiple (STM) instruction. The next instruction is fetched from the storage address contained in register 7. Bits 5-7 of the instruction are not used and must be set to zero to avoid future code obsolescence. Programming Note. If the A..M. field equals 01 the contents of the register specified by the RB field are incremented by 2. Indicators No indicators are changed. Program Check Conditions Invalid Storage Address. Instruction word or stack control block. The instruction is terminated. Specification Check. 1. Even byte boundary violation (indirect address, stack control block, or stack element). 2. Address in R7 is odd. Soft Exception Trap Condition Stack Exception. Stack is empty. If the AM field equals 01, the contents of the register specified by the RB field are incremented. The instruction is terminated. 6-42 GA34-0022 MB o Multiply Byte (MB) MB addr4,reg Operation code 1 1 1 0 1 A multiply operation is performed between the word multiplicand contained in the register specified by the R field and the byte multiplier at the location specified by the effective address. (Effective Address Generation is explained in Chapter 2.) The word product replaces the contents of the register. EA R x Multiplicand o c 15 Multiplier o 7 R Product o 15 Indicators Carry. Reset. Overflow. Cleared, then turned on if the result cannot be represented in 16 bits. If overflow occurs, the contents of the specified register are undefined. Even, Negative, and Zero. Set to reflect the result. Program Check Conditions Invalid Storage Address. Instruction word or operand. If the AM field equals 01, the contents of the register specified by the RB field are incremented. Specification Check. Even Byte boundary violation (indirect address). o Instructions 6-43 MD Multiply Doubleword (MD) MD o addr4,reg Operation code 110 o 15 A multiply operation is performed between the doubleword multiplicand contained in the registers specified by the R field and R+ 1 and the word multiplier at the location specified by the effective address. (Effective Address Generation is explained in Chapter 2.) The doubleword product replaces the contents of the registers with the least significant word in R+ 1. The R field wraps from 7 to 0; that is, if R specifies register 7, registers 7 and 0 are used. EA x I o Multiplier 41] 1~ Programming Note. If AM=OI, the register specified by the RB field is incremented by 2. Indicators Carry. Reset. Overflow. Cleared, then turned on if the result cannot be represented in 32 bits. If overflow occurs, the contents of the specified registers are undefmed. Even, Negative, and Zero. Set to reflect the result. Program Check Conditions Invalid Storage Address. Instruction word or operand. Specification Check. Even byte boundary violation (indirect address or operand address). 6-44 GA34-0022 c MVA Move Address (MV A) Storage Immediate Format Storage Address to Register Format MV A MVA raddr ,addr4 aqdr4,reg Format without appended word for effective addressing (AM = 00 or 01) Operation code I G 1 G G o I Operation code 10 1 0 o 0 I I 010 4 5 0 RB 01 7 I AM 1 8 9 I I Function 10 10 11 12 0 0 01 15 Immediate 16 The effective address is loaded into the register specified by the R field. (Effective Address Generation is explained in Chapter 2.) 31 Format with appended word for effective addressing (AM = 10 or 11) Operation code 010 Indicators o 4 5 7 8 9 Carry and Overflow. Unchanged. Even, Negative, and Zero. Changed to reflect the operand loaded into the register specified by the R field. Address/ Displacement -------Displacement 1 -------Displacement 2 2324 Program Check Conditions c Immediate Invalid Storage Address. Second Instruction word. Specification Check. Even byte boundary violation (indirect address). 32 47 The operand in the immediate field replaces the contents of the location specified by the effective address. (Effective Address Generation is explained in Chapter 2.) Bits 5-7 of the instruction are not used and must be set to zero to avoid future code obsolescence. The immediate operand is not changed. Indicators Carry and Overflow. Unchanged. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions Invalid Storage Address. Instruction word or operand. Specification Check. Even byte boundary violation (indirect address or operand address). o Instructions 6-45 MVB Move Byte (MVB) Storage/Storage Format Register/Storage Format MVB MVB reg,addr4 addr4,reg addrS ,addr4 (:; Operation code o o 0 0 0 4 5 789101112131415 Operation code o 000 4 5 J = () = 7 8 result to storage } result to reKister , 9 10 11 12 13 15 ~ A byte is moved between the least significant byte of the register specified by the R field and the location specified by the effective address in main storage. (Effective Address Generation is explained in Chapter 2.) Bit 12 of the instruction specifies the direction of the move: Bit 12 = O. The byte is moved from storage to register. The high-order bit of the byte (sign) is propagated to the eight high order bits of the register. This permits the Compare Byte Immediate (CBI) instruction to be used for byte compare operations. The operand in storage is unchanged. Bit 12 = 1. The byte is moved from register to storage. The contents of the register specified by the R field are not changed. Indicators Carry and Overflow. Unchanged. Even, Negative, and Zero. Changed to reflect the operand moved. Program Check Conditions Invalid Storage Address. Instruction word or operand. Specification Check. Even byte boundary violation (indirect address). 6-46 GA34-0022 The address arguments generate the effective addresses of two operands in main storage. (Effective Address Genera-' tion is explained in Chapter 2.) A byte is moved from operand 1 to operand 2. Operand 1 is unchanged. Indicators Carry and Overflow. Unchanged. Even, Negative, and Zero. Changed to reflect the byte moved. Program Check Conditions Invalid Storage Address. Instruction word or operand. The instruction is terminated. If AMI equals 01 and the operand 2 effective address is invalid, RBI is incremented. Specification Check. Even byte boundary violation (indirect address). !' \. , MVBI MVBZ o Move Byte Immediate (MVBI) Move Byte and Zero (MVBZ) MVBI MVBZ I byte ,reg Ope ,",ion code o 0 0 o 0 1 4 I 5 R Immediate 7 8 Operation code 15 The register specified by the R field is loaded with the immediate operand. The immediate field of the instruction forms the operand to be loaded. The immediate field is expanded to a sixteen bit operand by propagating the sign bit value through the high order bit positions; this operand is loaded into the register specified by the R field. Indicators Carry and Overflow. Unchanged. Even, Negative, and Zero. Changed to reflect the operand loaded into the register. Program Check Conditions No program checks occur. addr4,reg 1 1 0 0 0 o 4 5 7 8 9 10 11 12 15 The byte specified by the effective address is loaded into the least significant byte of the register specified by the R field. (Effective Address Generation is explained in Chapter 2.) The high order bit of the byte (sign) is propagated to the eight high order bits within the register. The byte specified by the effective address is then set to zeros. Bit 12 of the instruction is not used and must be set to zero to avoid future code obsolescence. Indicators Carry and Overflow. Unchanged. c Even, Negative, and Zero. Changed to reflect the operand loaded into the register. Program Check Conditions. Invalid Storage Address. Instruction word or operand. Specification Check. Even byte boundary violation (indirect address). o Instructions 6-47 MVD Move Doubleword (MVD) Storage/Storage Format Register/Storage Format MVD addr4,reg reg,addr4 MVD addr5,addr4 Operation code 10010 4 5 o 789101112131415 Operation Code 1 1 0 1 0 o I = result to storage } to register o = result ~ ~~~=~~~~~;~;~~====I Displacement 1 J Displacement 2 -I L 16------------------~ 23 24 31 A doubleword is moved between the contents of the register pair specified by the R field (R and R+ 1) and the doubleword location specified by the effective address in main storage. (Effective Address Generation is explained in Chapter 2.) The source operand is unchanged. The R field wraps from 7 to 0; that is, if R specifies register 7, registers 7 and 0 are used. Bit 12 of the instruction specifies the direction of the move: Bit 12 = O. The doubleword is moved from storage to the register pair. Bit 12 = 1. The doubleword is moved from the register pair to storage. Indicators The address arguments generate the effective addresses of two operands in main storage. (Effective Address Generation is explained in Chapter 2.) A doubleword is moved from operand 1 to operand 2. Operand 1 is unchanged. Indicators Carry and Overflow. Unchanged. Even, Negative, and Zero. Changed to reflect the doubleword moved. Program Check Conditions Invalid Storage Address. Instruction word or operand. The instruction is terminated. If AMI equals 01 and the operand 2 effective address is invalid, RBI is incremented. Specification Check. Even byte boundary violation (indirect address or operand address). Carry and Overflow. Unchanged. Even, Negative, and Zero. Changed to reflect the operand moved. Program Check Conditions Invalid Storage Address. Instruction word or operand. Specification Check. Even byte boundary violation (indirect address or operand address). c 6-48 GA34-0022 MVDZ c Move Doubleword and Zero (MVDZ) MVDZ addr4,reg Operation code 101 0 n 7 R Q If) 11 12 15 The doubleword specified by the effective address is loaded into the register pair specified by the R field (R and R+l). (Effective Address Generation is explained in Chapter 2.) The R field wraps from 7 to 0; that is, if R specifies register 7, registers 7 and 0 are used. The doubleword specified by the effective address is then set to zeros. Bit 12 of the instruction is not used and must be set to zero to avoid future code obsolescence. Indicators Carry and Overflow. Unchanged. c Even, Negative, and Zero. Changed to reflect the operand loaded into the register pair. Program Check Conditions Invalid Storage Address. Instruction word or operand. Specification Check. Even byte boundary violation (indirect address or operand address). o Instructions 649 1\IVFD MVFN Move Byte Field and Decrement (MVFD) Move Byte Field and Increment (MVFN) MVFD MVFN (reg),(reg) (reg),(reg) Io I Operation code 0 101 o o Indicators Carry and Overflow. Unchanged. R2 R1 045 7 Note. Variable field length instructions can be interrupted. When this occurs and the interrupted level resumes operation, the processor treats the uncompleted instruction as a new instruction with the remaining count specified in register 7. 8 1011 1213 14 15 for MVFD or MVFN ~ for MVFD; decrement contents} of Rl & R2 for MVFN; increment contents ofRl&R2 Even, Negative, and Zero. Changed to reflect the result of the last byte moved. Program Check Conditions Invalid Storage Address. Operand. The instruction is terminated. This instruction moves a specified number of bytes (one byte at a time) from one storage location to another. Register 7 contains the number of bytes to be moved (field length). If a field length of zero is specified, the instruction is a no-op. The register specified by Rl contains the address of operand 1; the register specified by R2 contains the address of operand 2. Operand 1 is moved to operand 2. After each byte is moved: 1. The addresses in Rl and R2 are either incremented or decremented, determined by bit 13 of the instruction. This allows the field to be moved in either direction. 2. The length count in R7 is decremented. •... ,. The operation ends when the specified field length has been filled (contents of R7 equal zero). At this time, the addresses in Rl and R2 have been updated and point to the next operands. Bits 11 and 15 of the instructions are not used and must be set to zero to avoid future code obsolescence. See Fill Byte Field and Decrement (FFD) and Fill Byte Field and Increment (FFN) for other versions of this machine instruction. (: 6-50 GA34-0022 MVW o Move Word (MVW) Register to Storage Long Format Register/Register Format MVW regJongaddr reg,reg MVW Operation code Operation code () 1 1 o 1 0 4 o Function 00100 5 7 8 10 11 15 0= direct address } 1 = indirect address The contents of the register specified by the RI field replace the contents of the register specified by the R2 field. The contents of the register specified by the RI field are unchanged. Indicators Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions No program checks occur. Address reg,addr4 addr4,reg Operation Code 1 0 0 1 o 1 = result to storage } () = result to register 31 The contents of the register specified by the RI field are stored into the main storage location specified by an effective address. This effective address is generated as follows: 1. Register/Storage Format c ~ 16 Carry and Overflow. Unchanged. MVW 1 101 o ~ The address field is added to the contents of the register specified by the R2 field. If the R2 field equals zero, no register contributes to the address generation. 2. Instruction bit 11 is tested for direct or indirect addressing: Bit 11 = 0 (direct address). The result from step 1 is the effective address. Bit 11 = 1 (indirect address). The result from step 1 is the address of the main storage location that contains the effective address. Indicators r------------------I Addressj Displacement ~~~~~~=- 23l-_D~~c~m~ I ~ ~31j 16 24 t = A word is moved between the contents of the register specified by the R field and the location specified by the effective address in main storage. (Effective Address Generation is explained in Chapter 2.) The source operand is unchanged. Carry and Overflow. Unchanged. Even, Negative, and Zero. Changed to reflect the result stored from the register specified by the Rl field. Program Check Conditions Invalid Storage Address. Instruction word or operand. Specification Check. Even byte boundary violation (indirect address or operand address). Indicators Carry and Overflow. Unchanged. Even, Negative, and Zero. Changed to reflect the operand moved. Program Check Conditions o Invalid Storage Address. Instruction word or operand. Specification Check. Even byte boundary violation (indirect address or operand address). Instructions 6-51 MVW Storage to Register Long Format Storage/Storage Format MVW MVW longaddr ,reg Operation code Operation code o 1 101 1 000 1 o o o= 1 addrS ,addr4 direct address } = indirect address 4 5 7 8 9 10 11 1213 14 15 ~ Address 31 16 The register specified by the Rl field is loaded with the contents of the main storage location specified by an effective address. This effective address is generated as follows: The address field is added to the contents of the register specified by the R2 field. If the R2 field equals zero, no register contributes to the address generation. 2. Instruction bit 11 is tested for direct or indirect addressing: Rit 11 = 0 (dire('t address). The result from step! is the effective address. Bit 11 = 1 (indirect address). The result from step 1 is the address of the main storage location that contains the effective address. The address arguments generate the effective addresses of two operands in main storage. (Effective Address Generation is explained in Chapter 2.) A word is moved from operand 1 to operand 2. Operand 1 is unchanged. 1. Indicators Carry and Overflow. Unchanged. Even, Negative, and Zero. Changed to reflect the result loaded into the register specified by the Rl field. Program Check Conditions Invalid Storage Address. Instruction word or operand. Specification Check. Even byte boundary violation (indirect address or operand address). 6-52 GA34-0022 Indicators Carry and Overflow. Unchanged. Even, Negative, and Zero. Changed to reflect the word moved. Program Check Conditions Invalid Storage Address. Instruction word or operand. The instruction is terminated. If AM 1 equals Oland the operand 2 effective address is invalid, RBI is incremented. Specification Check. Even byte boundary violation (indirect address or operand address). MVWI o Move Word Immediate (MVWI) Storage Immediate Format Storage to Register Format MVWI MVWI word ,reg I Operation lUI word ,addr4 U o c_Od~ U I R UI 4 5 7 \ RB \ AM I I 8 9 I r. I v 10 11 12 ~unc:io~ 1. V v I I 15 Format without appended word for effective addressing (AM = 00 or 01) IOperati~n ~od~ IU 1 U U \ _\ RB ulU 045 0 ul I InFu~ct~on I AM I IV 789101112 v v " VI 15 Immediate 16 The effective address value is loaded into the register specified by the R field. (Effective Address Generation is explained in Chapter 2.) This value is equal to the value of word as specified by the programmer. 31 Format with appended word for effective addressing (AM = 10 or 11) Operation code o 100 0 o Indicators Carry and Overflow. Unchanged. Even, Negative, and Zero. Changed to reflect the operand loaded into the register specified by the R field. Address/ Displacement -------Displacement 1 2324 Program Check Conditions c Invalid Storage Address. Second instruction word. Specification Check. Even byte boundary violation (indirect address). -------Displacement 2 31 Immediate 32 47 The operand in the immediate field replaces the contents of the location specified by the effective address. (Effective Address Generation is explained in Chapter 2.) Bits 5-7 of the instruction are not used and must be set to zero to avoid future code obsolescence. The immediate operand is not changed. Indicators Carry and Overflow. Unchanged. Even, Negative, and Zero. Changed to reflect the result. Program Check Conditions Invalid Storage Address. Instruction word or operand. Specification Check. Even byte boundary violation (indirect address or operand address). o Instructions 6-53 MVWS Move Word Short (MVWS) Storage to Register Format Register to Storage Format MVWS MVWS shortaddr ,reg ( reg,shortaddr Operation code 1 1 1 0 Operation code X Wd displacement o X 4 5 7 8 o 1 0 0 o 4 5 78 o = direct address 1 = indirect address } 9 1011 J 15 The contents of the register specified by Rl are stored into the main storage location specified by the effective address. The contents of the register are unchanged. The effective address is generated as follows: o= Wd displacement 0 direct address 1 = indirect address } 9 10 11 J 15 The contents of the main storage location specified by the effective address are loaded into the register specified by the Rl field. The contents of the main storage location remain unchanged. The effective address is generated as follows: The five bit unsigned integer (word displacement) is doubled in magnitude (converted to a byte displacement). 2. The result from step 1 is added to the contents of the base register (RB) to form a main storage address. 3. Instruction bit lOis tested for direct or indirect addressing: Bit 10 = 0 (direct address). The result from step 2 is the effective address. Bit 10 = 1 (indirect address). The result from step 2 is the address of the main storage location that contains the effective address. The five bit unsigned integer (word displacement) is doubled in magnitude (converted to a byte displacement). 2. The result from step 1 is added to the contents of the base register (RB) to form a main storage address. 3. Instruction bit lOis tested for direct or indirect addressing: Bit 10= 0 (direct address). The result from step 2 is the effective address. Bit 10= 1 (indirect address). The result from step 2 is the address of the main storage locatio!l that l;uulains the effective address. Indicators Indicators Carry and Overflow. Unchanged. Carry and Overflow. Unchanged. Even, Negative, and Zero. Changed to reflect the operand stored into main storage. Even, Negative, and Zero. Changed to reflect the operand loaded into the register specified by the Rl field. Program Check Conditions Program Check Conditions Invalid Storage Address. Operand. Invalid Storage Address. Operand. Specification Check. Even byte boundary violation (indirect address or operand address). Specification Check. Even byte boundary violation (indirect address or operand address). 1. 6-54 GA34-0022 1. -"\ J MVWZ Move Word and Zero (MVWZ) MVWZ addr4,reg Operation code 1 0 0 o 789101112 15 .-------------------. t- ____ _ _ _ __ ~d1 5.4 4.8 6.6 5.4 4.8 6.6 See JC See JC See JC See JNC See JNC See JC See JNC See JNC See JC Instruction Execution Times A-5 Mnemonic JLLT JLT JMIX IN Instruction name Jump on Logically Less Than Jump on Arithmetically Less Than Jump if Mixed Jump on Negative Syntax (; SeeJC SeeJC See JC JNC Jump on Not Condition JNCY JNE JNEV JNMIX JNN JNP JNZ JOFF JON JP JZ LEX Jump on No Carry Jump on Not Equal Jump on Not Even Jump if Not Mixed Jump on Not Negative Jump on Not Positive Jump on Not Zero Jump if Off Jump if On Jump on Positive Jump on Zero Level Exit [ubyte] Load Multiple and Branch addr4 LMB Execution time (microseconds) See JC condjdisp condjaddr Test Condition No Branch Branch 4.2 6.0 4.2 6.0 See JNC See JNC See JNC See JNC See JNC See JNC See JNC See JC See JC See JC See JC 8.8 Minimum 19.6 Maximum 17.2+RS LNQte) Note. For each specified register from 0 through 6, add an additional 3.2 per register. MB Multiply Byte addr4,reg MD Multiply Doubleword addr4,reg MVA Move Address MVB Move Byte MVBI MVBZ MVD Move Byte Immediate Move Byte and Zero Move Doubleword MVDZ MVFD (reg),(reg) 8.4+(5.4 x CT) MVW Move Doubleword and Zero Move Byte Field and Decrement Move Byte Field and Increment Move Word addr4,reg addr5,addr4 reg,addr4 addr4,reg addr5,addr4 byte,reg addr4,reg reg,addr4 addr4,reg addr5,addr4 addr4,reg (reg),(reg) 11.2+RS Minimum 26.2+RS Maximum 10.0+RS Minimum 98.2+RS Maximum 5.2+RS 5.4+RS 6.6+RS 8.2+RS 5.4+AM1+AM2 3.6 8.8+RS 8.4+RS 7.6+RS 8.4+AMI +AM2 9.6+RS 8.4+(5.4 x CT) MVWI Move Word Immediate reg,reg reg,addr4 addr4,reg addr5,addr4 reg,longaddr reg,longaddr* longaddr ,reg longaddr* ,reg word,reg word,addr4 4.2 5.4+RS 5.2+RS 4.8+AM1+AM2 7.6 8.2 7.2 7.8 5.2 5.4+RS MVFN A-6 GA34-0022 ! \ , Note 3 Note 3 Note 3 Note 3 Note 3 Note Note Note Note Note 3 1 2 1 2 (C~ 0 Mnemonic MVWS MVWl. MW C C Instruction name Move Word Short lviove woru anu Zt!fU Multiply Word NOP No Operation NWI OB And Word Immediate OR Byte OD OR Doubleword OW OR Word OWl OR Word Immediate PB PD PSB PSD PSW PW RBTB Pop Byte RBTD Reset Bits Doubleword RBTW Reset Bits Word RBTWl Reset Bits Word Immediate SB Subtract Byte SCY Subtract Carry Indicator SD Subtract Doubleword SECON SEIMR SEIND SELB Set Console Data Lights Set Interrupt Mask Register Set Indicators Set Level Block SFED Scan Byte Field Equal and Decrement Scan Byte Field Equal and Increment SFEN Pop Doubleword Push Byte Push Doubleword Push Word Pop Word Reset Bits Byte Syntax reg,shortaddr reg,shortaddr* shortaddr ,reg shortaddr* ,reg Execution time (microseconds) 6.0 6.6 5.4 6.2 dUU14,1t;b G.2:RS addr4,reg 9.4+RS 40.6+RS 4.2 word,reg [,reg 1 reg,addr4 addr4,reg addrS ,addr4 reg,addr4 addr4,reg addr5,addr4 reg,reg reg,addr4 addr4,reg addr5,addr4 longaddr ,reg longaddr* ,reg word,reg [ ,reg 1 word,addr4 addr4,reg addr4,reg 5.4 8.8+RS 8.8+RS 7.8+AM1+AM2 9.0+RS 7.6+RS 9.8+AM1+AM2 4.2 5.8+RS 5.2+RS 6.0+AMl +AM2 7.2 7.8 5.4 6.6+RS 11.2+RS 10.4+RS reg,addr4 reg,addr4 reg,addr4 addr4,reg reg,addr4 addr4,reg addr5,addr4 reg,addr4 addr4,reg addr5,addr4 reg,reg reg,addr4 addr4,reg addr 5 ,addr4 longaddr ,reg longaddr* ,reg word,reg[ ,reg 1 word,addr4 reg,addr4 addr4,reg reg 10.6+RS 11.0+RS 9.8+RS reg,addr4 addr4,reg addr 5 ,addr4 reg addr4 reg reg,addr4 Minimum Maximum 9.2+RS 8.8+RS 8.8+RS 8.0+AMl +AM2 9.0+RS 8.0+RS 9.8+AMl +AM2 4.2 5.8+RS S.8+RS 6.6+AM1+AM2 7.2 7.8 5.4 6.6+RS 11.0+RS 10.6+RS 4.8 9.4+RS 8.8+RS 11.2+AM1+AM2 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 6.0 8.0+RS reg,(reg) 6.0 24.4 Minimum Maximum 43.6 8.4+(6.0 x CT) reg,(reg) 8.4+(6.0 x CT) Note Note Note Note 1 2 1 2 Instruction Execution Times A-7 Mnemonic SFNED SFNEN SLC Instruction name Scan Byte Field Not Equal and Decrement Scan Byte Field Not Equal and Increment Shift Left Circular Syntax reg,(reg) Execution time (microseconds) 8.4+(6.0 x CT) reg,(reg) 8.4+(6.0 x CT) cntl6,reg 6.6 7.8 6.6 9.0 15.0 18.0 15.0 18.0 5.4 12.0 5.4 10.8 6.6 18.6 6.6 18.6 7.2 37.2 7.8 105.6 6.6 10.2 6.6 10.2 10.8 16.8 10.8 16.8 5.4 9.0 5.4 9.0 10.2 16.2 10.2 16.2 21.8+RS reg,reg SLCD Shift Left Circular Double cnt31,reg reg,reg SLL Shift Left Logical cnt16,reg reg,reg SLLD Shift Left Logical Double cnt31,reg reg,reg SLT Shift Left and Test reg,reg SLTD Shift Left and Test Double reg,reg SRA Shift Right Arithmetic cnt16,reg reg,reg SRAD Shift Right Arithmetic Double cnt31,reg reg,reg SRL Shift Right Logical cnt16,reg reg,reg SRLD Shift Right Logical Double cnt31,reg reg,reg STM Store Multiple reg,addr4 [,abcnt] Note Note Note Note 1 2 1 2 Minimum Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum Maximum () ,I ~. •\ , (Note) Note. For each specified register from 0 through 6, add an additional 3.0 per register. STOP Stop [ubyte] 4.2 (Note) Note. Time given is for execution as a No-Op. SVC SW Supervisor Call Subtract Word SWCY SWI Subtract Word With Carry Subtract Word Immediate TBT TBTR TBTS Test Bit Test Bit and Reset Test Bit and Set On A-8 GA34-0022 ubyte reg,reg reg,addr4 addr4,reg addr5,addr4 longaddr,reg longaddr* ,reg reg,reg word,addr4 word,reg[ ,reg] (reg,bitdisp) (reg,bitdisp) (reg, bitdisp ) 26.0 4.2 6.2+RS 5.8+RS 6.8+AMl+AM2 7.8 8.4 4.8 6.6+RS 5.4 8.4 9.6 9.6 ( , ..• 0 Mnemonic TBTV TWI Instruction name Test Bit and Invert Test Word Under Mask Immediate word,addr4 Execution time (microseconds) 9.6 7.2 7.8 All bits 7.0+RS reg[,reg] reg,addr4 addr4,reg reg,addr4 addr4,reg reg,reg reg,addr4 addr4,reg longaddr ,reg longaddr* ,reg word,reg [,reg] 4.8 8.8+RS 8.8+RS 9.0+RS 8.2+RS 4.2 5.8+RS 5.2+RS 7.2 7.8 5.4 Syntax (reg,bitdisp) word,reg 7.~+HS VR XB Invert Register Exclusive OR Byte XD Exclusive OR Doubleword XW Exclusive OR Word XWI Exclusive OR Word Immediate An hits =1 =1 Note Note Note Note 3 3 3 3 c o Instruction Execution Times A-9 A-I 0 GA34-0022 Oxxx o Appendix B. Instruction Formats The following instruction formats are shown in ascending sequence based on operation code. Bits zero through four of the first instruction word comprise the operation code field. Bit combinations are shown for each operation code along with the hexadecimal representation. Some instructions contain a function field that modifies the operation code to form individual instructions within a group. Each chart shows the function field bit combinations in hexadecimal and in ascending sequence. The assembler mnemonic, assembler syntax, and instruction name are listed for the individual instructions. The asterisk shown with the assembler syntax indicates indirect addressing. Refer to Chapter 2, Effective Address Generation, for a description of the Address Mode (AM) appended words. c o 4 5 7 8 15 ~~~~ o 0-7 X ABI o 4 5 X byte,reg 7 Add Byte Immediate 8 15 ~~~~ o 8-F MVBI X X byte,reg Move Byte Immediate o Instruction Formats B-1 lxxx 2xxx Word displa~ement Operation code 00010 o 15 ~~~~ 1 0-7 X X JC cond,jdisp Jump on Condition JC cond,jaddr Jump on Condition Extended mnemonics: JCY, JE, JEV, JLE, JLLE, JLLT, JLT, JMIX, IN, JOFF, JON, JP, JZ Word displacement Operation code 00011 o 4 7 8 5 15 JNC cond,jdisp Jump on Not Condition cond,jaddr Jump on Not Condition Extended mnemonics: JCE, JCT, JLCE, JLCT, JNCY, JNE, JNEV, JNMIX, JNN, JNP, JNZ ~~~'- 2 0-3 O-F X V ./ AM appended word Illegal operation code (invalid 'function) I~pet~on ;Od; 11 IRJ IR2 I 0 0 o 4 5 6 7 8 9 IFun< 101112 n 14 15 ~~~~ 2 2 4-7 14-71 X I X I X O-F Illegal operation code (invalid function) (~ B-2 CA34-0022 2xxx 3xxx o Io Operation code .0 0 1 ° I R1 R2 1. 4 5 7 1011 12 13 14 15 8 ~~~~ 2 8-F xl X ~1'.'PD 0 O-F (!eg),(y~g) ~,1~'.'~ ~j'te Fie!d :!!'!d !)e~!"e!!!e!"!t (unused) C 2 CFNED (reg),(reg) Compare Byte Field Not Equal and Decrement 3 CFED (reg),(reg) Compare Byte Field Equal and Decrement 4 MVFN (reg),(reg) Move Byte Field and Increment 5 (unused) 6 CFNEN (reg),(reg) Compare Byte Field Not Equal and Increment 7 CFEN (reg),(reg) Compare Byte Field Equal and Increment 8 FFD reg,(reg) Fill Byte Field and Decrement 9 (unused) A SFNED reg,(reg) Scan Byte Field Not Equal and Decrement B SFED reg,(reg) Scan Byte Field Equal and Decrement C FFN reg,(reg) Fill Byte Field and Increment D (unused) E SFNEN reg,(reg) Scan Byte Field Not Equal and Increment F SFEN reg,(reg) Scan Byte Field Equal and Increment Io Operation code 0 1 1 0 I 4 0 I R 7 5 Count I Functionl 12 13 8 15 ~~''-'-~~/ 0-7 3 X O-F 0,8 SLC cnt16,reg Shift Left Circular 1,9 SLL cnt16,reg Shift Left Logical 2,A SRL cnt16,reg Shift Right Logical 3,B SRA cnt16,reg Shift Right Arithmetic 4,C SLCD cnt31,reg Shift Left Circular Double 5,D SLLD cnt31,reg Shift Left Logical Double 6,E SRLD cnt31,reg Shift Right Logical Double 7,F SRAD cnt31,reg Shift Right Arithmetic Double o Instruction Formats B-3 3xxx 4xxx I I Operation code 00111 o 4 5 15 ~~~~ 3 8-F X X Illegal operation code (program check condition) AM appended word Io Operation code 1 000 0 I 4 0 Io 1 4 1 000 I 4 8 I R 7 5 Operation code 0 7 5 I Operation code I o 1 000 8 7 I 8 I Function 15 16 I 15 16 15 16 '-~~/'----v~~~ 0-7 4 X ~D 31 ~LJ 31 I )~ AM IFUnCtiOn 101112 9 IImmediate AM-IFunction 101112 9 RB /~ 101112 9 RB I R 5 AM RB R O-F Immediate 31 32 sO 47 '-------~ AM appended word .~ \.. 0 MVA addr,addr4 Move Address 0 MVWI word,addr4 Move Word Immediate ,. (invalid) 2 (invalid) 3 (invalid) 4 MVA addr4,reg Move Address (Note 1) 4 MVWI word ,reg Move Word Immediate (Note 1) 5 (invalid) 6 (invalid) 7 (invalid) 8 STM reg,addr4 [,abcnt 1 Store Multiple 9 AWl word,addr4 Add Word Immediate A LMB addr4 Load Multiple and Branch (Note 1) B TWI word,addr4 Test Word Under Mask Immediate C OWl word,addr4 OR Word Immediate D RBTWI word,addr4 Reset Bits Word Immediate E SWI word,addr4 Subtract Word Immediate F CWI word,addr4 Compare Word Immediate Note 1. Use format without immediate field. B-4 GA34-0022 (: 4xxx 5xxx c Bit displacement Operation code o o 1 001 4 5 7 8 9 10 15 ~~~~ 4 8-F o X TBT (reg,bitdisp) Test Bit TBTS (reg,bitdisp) Test Bit and Set On TBTR (reg,bitdisp) Test Bit and Reset TBTV (reg,bitdisp) Test Bit and Invert Word displacement Operation code o O-F 1 0 1 0 4 5 15 ~~~~~ 5 I5 c 0-7 X X 0 0 0 NOP No Operation 0 X X J jdisp J jaddr 1-7 X X BXS (reg l BXS (reg l BXS addr Jump Unconditional - - Jump Unconditional 7 7 ,jdisp) Branch Indexed Short ) Branch Indexed Short Branch Indexed Short o Instruction Formats B-5 5xxx Io 1 011 o 4 Operation code I I I K 5 RB 7 8 AM 9 ~D IFunctiOn 10 11 12 15 16 31 (1 ~~ l~pe;a,:;n~Od:1 o 4 I I R 5 7 AM appended word AM 8 101112 9 7D IFunctiOn RB 15 16 31 ~~~~~ 8-F 5 0 SEIMR X O-F AM appended word addr4 Set Interrupt Mask Register reg,addr4 Set Level Status Block addr4 Copy Interrupt Mask Register (Note 2) 2 (Note 3) 3 (Note 4) 4 (Note 3) 5 (invalid) 6 SELB 7 (invalid) 8 CPIMR 9 (Note 2) A (Note 3) B (Note 4) C (Note 3) D CPIPF addr4 Copy In-Process Flags E CPLB reg,addr4 Copy Level Block F CPPSR addr4 Copy Processor Status and Reset Note 2. Supervisor state: program check, invalid function Problem state: program check, privilege violate Note 3. Supervisor state: No-{)p Problem state: program check, privilege violate Note 4. Supervisor state: soft exception trap, invalid function Problem state: program check, privilege violate (~ B-6 GA34-0022 6xxx o Operation code o 1 1 0 0 o ~~~~ 6 0-7 X X SVC ubyte Supervisor Call LEX [ubyte] Level Exit 2 EN ubyte Enable 3 DIS ubyte Disable 4 STOP [ubyte] Stop 5 DIAG ubyte Diagnose 6 (Note 5) 7 (invalid) Note 5. Supervisor state: No-op Problem state: program check, privilege violate c o Instruction Formats B-7 6xxx . . . . - - - - - - - - - Rl, condition, or condition code I O=Direct address, 1 =Indirect address D Operation code o 1 1 0 1 o 4 '--------L..---.-JL....---.L...-------'~ 5 7 8 15 16 101112 31 ~~~~ 6 8-F I O-F .. , ! Note 6. Extended mnemonics: BCY, BE, BEV, BLE, BLLE, BLLT,BLT,BMIX,BN,BOFF,BON,BP,BZ Note 7. Extended mnemonics: BGE, BGT, BLGE, BLGT, BNCY, BNE, BNEV, BNMIX, BNN, BNOFF, BNON, BNP, BNZ Note 8. Extended mnemonic: BX Note 9. Extended mnemonic: BALX Note 10. Extended mnemonic: BNER Note 11. Extended mnemonic: BER B-8 GA34-0022 6xxx o R 1, condition, or condition code O=Direct address, 1=Indirect address D Operation code o 1 1 0 1 L------~---L....-J,----L~ o 4 7 8 5 1011 12 15 16 31 ~~~~ 6 I 8-F O-F 1, 3, 5, 7, 9, B, D, F "- :Fz: 'V ./ t BC cond )ongaddr* Branch on Condition BNC cond )ongaddr * Branch on Not Condition 2 B longaddr* Branch Unconditional 3 BAL longaddr * ,reg Branch and Link 4 BCC cond)ongaddr * Branch on Condition Code 5 BNCC cond ,10 ngaddr * Branch on Not Condition Code 6 BOV longaddr* Branch on Overflow 7 BNOV longaddr* Branch on Not Overflow 8 MVW longaddr* ,reg Move Word 9 OW longaddr * ,reg OR Word A RBTW longaddr* ,reg Reset Bits Word B XW longaddr * ,reg Exclusive OR Word C 10 longaddr* Operate I/O D MVW reg)ongaddr* Move Word E AW longaddr* ,reg Add Word F SW longaddr* ,reg Subtract Word 0 C o Instruction Formats B-9 (: B-10 GA34-0022 o Instruction Formats B-ll 7xxx Operation code o 1 1 1 1 o 4 Function 5 7 8 10 11 (~ 15 16 ~~~~ 7 I 8-F O-F 0, 2, 4, 6, 8, A, C, E "- ./ t NWI word ,reg [,reg] And Word Immediate AWl word ,reg [ ,reg] Add Word Immediate 2 SWI word ,reg [ ,reg] Subtract Word Immediate 3 OWl word,reg[ ,reg] OR Word Immediate 4 RBTWI word,reg[ ,reg] Reset Bits Word Immediate 5 XWI word ,reg [,reg] Exclusive OR Word Immediate 6 CWI word ,reg Compare Word Immediate 7 TWI word ,reg Test Word Under Mask Immediate 8 (invalid) 9 (invalid) A (invalid) B (invalid) C (invalid) D (invalid) E (invalid) F (invalid) 0 ,,; t.. 't c B-12 GA34-0022 7xxx 8xxx 0 I R2 loperation code 011 1 1 0 0 4 5 0 IOperation code I K 1"\ IV 0 1 ..L 1 ..L 1 ..L 1 4 8 7 I Function I 7 5 15 10 11 R I I ..L 1Function 01 I I 8 I 15 10 11 ~~~~ 7 I 8-F , O-F 1, 3, 5, 7, 9, E, D, F ~ I 0 SECON reg Set Console Data Lights (invalid) C 2 (Note 12) 3 (invalid) 4 (invalid) S (invalid) 6 (invalid) 7 (invalid) 8 CPCON reg Copy Console Data Buffer 9 CPCL reg Copy Current Level A (Note 12) B (invalid) C (invalid) D (invalid) E (invalid) F (invalid) Note 12. Supervisor state: No-op Problem state: program check, privilege violate ~o~l_p_e~_a_t~_o_n_~_o_dO~e~~ ~~~~~~~~~~~~~ __ o 4 ______ ~f7L____~~____~L]~ 31 32 47 ~~~~-"""-------....-------8 0-7 X O-F AM appended words o MVB addrS ,addr4 Move Byte OB addrS ,addr4 OR Byte RBTB addrS ,addr4 Reset Bits Byte CB addrS ,addr4 Compare Byte Instruction Formats B-13 8xxx 9xxx ~~_p_e_;_a_t~_on~_o_~_e~ __ ~ ____ ~ ____ ____L -__ ~ ~~ __ ________ ~~ ~~I~______9~~ __ o 45 78910111213141516 3132 47 ~~~~~,-------------v------------~ 8 8-F X O-F AM appended words ~~pe_;_a_~_o_n_;_o_d;~ __ o MVW addrS ,addr4 Move Word OW addrS ,addr4 OR Word RBTW addrS ,addr4 Reset Bits Word CW addrS ,addr4 Compare Word ______L -__- L_ _ _ _ 45 ~ _ _- L_ _ ~~ 78910111213141516 ________ I ~~ IJ~ 3132 47 ~~~~'-------------v-------------~ 9 0-7 X O-F AM appended words 0,4 SC 1,S 9.D MVD addrS ,addr4 Move Double Word OD addr S ,addr4 OR Double Word RBTD addrS ,addr4 Reset Bits Double Word CD addrS ,addr4 Compare Double Word Operation code Word displacement 10011 o 4 5 7 8 15 ~~~~ 9 9 IS-FI X 8-F I X I X X J AL jdisp,reg Jump and Link JAL jaddr,reg Jump and Link ( -' --,-~ B-14 GA34-0022 I IOperation code I Rl o 4 5 7 8 O=Direct address; I=Indirect address II 0 RB 10100 Axxx Bxxx 10 11 9 I Word disp 15 ~~~~ 4 ! V-I v 0, I, 4, 5, 8, 9, C, D '- 7'>'v ./ I x Move Word Short reg,shor taddr MVWS iO=Direct address; 1 =Indirect address Operation code I.1 I Rl 045 7 I RB 1 8 10 11 0 1 0 0 . 9 I Word disp 15 ~~~~ A I 0-7 X 2, 3, 6, 7, A, B, E, F ~ I reg,shortaddr * c L~p_e~_a_t~_o_n_~_o_~_e~____~____ __ ~ - L_ _ _ _ o 4 5 7 8 9 Move Word Short _ _- L _ _ _ _L -________ 1011 12 13 14 15 16 ~ L ____ ~ ________ ~4~ 31 32 47 ~~~~~~------------~~----------~ A 8-F I X AM appended words O-F AW addrS ,addr4 Add Word SW addrS ,addr4 Subtract Word AD addrS ,addr4 Add Double Word SD addrS ,addr4 Subtract Double Word I Operation code Function 10110 o 4 B o 5 15 0-7 I B 10- 71X 1X I X X Unsupported operation code (Soft exception trap condition) I nstruction Formats B-lS "Bxxx lCXXX Operation code 10111 Word displacement o ~~~~ B 8-F B!S-F! X!X! X X JCT jdisp,reg Jump on Count JCT jaddr,reg Jump on Count , - O=Storage to register; l=Register to storage II...-~p_e;a_~n_;o_~-L-.I_R--L.-IR_Jj~1A_M~lx~IF_un_ctio---,-nl_~~D o 4 5 7' 8 9 10 11 12 13 15 16 31 ~~~~~ C 0-7 X O-B, E, F AM appended word MVB addr4,reg Move Byte OB addr4,reg OR Byte 2 RBTB addr4,reg Reset Bits Byte 3 XB addr4,reg Exclusive OR Byte 4 CB addr4,reg Compare Byte 5 MVBZ addr4,reg Move Byte and Zero 6 AB addr4,reg Add Byte 7 SB addr4,reg Subtract Byte 8 MVB reg,addr4 Move Byte 9 OB reg,addr4 OR Byte A RBTB reg,addr4 Reset Bits Byte B XB reg,addr4 Exclusive OR Byte E AB reg,addr4 Add Byte F SB reg,addr4 Subtract Byte 0 ," ~ ( B-16 GA34-0022 c Cxxx I I Operation code 1 1 0 0 o 1 I 4 R 7 5 O=Storage to register; 1=Register to storage II I X Function RB AM 8 10 11 12 13 9 SO 15 16 31 ~~~~~ o--F \.- 0 ( r\ A T"Io v-~v, T"" .L..J, ~ J.' Ai.,,; UIlIlt::",it::u WUfU MVW addr4,reg Move Word OW addr4,reg OR Word 2 RBTW addr4,reg Reset Bits Word 3 XW addr4,reg Exclusive OR Word 4 CW addr4,reg Compare Word 5 MVWZ addr4,reg Move Word and Zero 6 AW addr4,reg Add Word ? SW addr4,reg Subtract Word 8 MVW reg,addr4 Move Word 9 OW reg,addr4 OR Word A RBTW reg,addr4 Reset Bits Word B XW reg,addr4 Exclusive OR Word E AW reg,addr4 Add Word F SW reg,addr4 Subtract Word D Instruction Formats B-1? Dxxx I I Operation code 1 1 0 1 0 o I 4 R 5 RB 7 8 9 AM O=Storage to register; I=Register to storage I X IFUnCtiOn 10 11 12 13 I 40 15 16 ~~~~'- D 0-7 X O-B, E, F addr4,reg Move Double Word OD addr4,reg OR Double Word 2 RBTD addr4,reg Reset Bits Double Word 3 XD addr4,reg Exclusive OR Double Word 4 CD addr4,reg Compare Double Word 5 MVDZ addr4,reg Move Double Word and Zero 6 AD addr4,reg Add Double Word 7 SD addr4,reg Subtract Double Word 8 MVD reg,addr4 Move Double Word 9 OD reg,addr4 OR Double Word A RBTD reg,addr4 Reset Bits Double Word B XD reg,addr4 Exclusive OR Double Word E AD reg,addr4 Add Double Word F SD reg,addr4 Subtract Double Word 4 15 5 ~~~~ D I D 18-FIX B-18 / AM appended word IOp"ation code I 1 1 0 1 1 o 8-F I X I GA34-0022 X .J 31 V" MVD 0 ( --'.' X lllegal operation code (Program check condition) f ,. Exxx c I O=Direct address; 1 =Indirect address ~-::-p-e;-a-t-~o-n-~-o-d":",;"""I--::R:-:1:--""""T-R-::-::B~I-o--'l-:'w-:'o-r~d:-d":"'i:-sp----, "'1 o 4 5 7 8 9 10 11 15 ~~~~ p I n_7 y 0, 1, 4, 5, 8, 9, C, D " 'v"--'./ Move Word Short shortaddr ,reg I O=Direct address; 1=lndirect address ~1~-p-e-;-a-n-:-n-~-O-d-;-rI-R-l-~-R-B-'I~l~I-W-o-r-d-d-i-SP--~I 7 045 8 9 15 10 11 ~~~~ E I 0-7 X 2,3,6, 7, A, B, E, F " V ./ I c ---II_o-.1--'--1 .... X-.J1 E L..- MVWS shortaddr* ,reg Move Word Short o Instruction Formats B-19 Exxx Fxxx 1~~_p_e_~_t_~_n_~_o_d;~I___R__~R__B~I_A_M__LIF_u_n_cti_.o_n__~I~_______S~~ o 4 5 7 8 10 11 12 9 15 16 ~~~~ '- E 8-F AM appended word O-F PSB reg,addr4 Push Byte MB addr4,reg Multiply Byte 2 DB addr4,reg Divide Byte 3 PB addr4,reg Pop Byte 4 PSW reg,addr4 Push Word 5 MW addr4,reg Multiply Word 6 DW addr4,reg Divide Word 7 PW addr4,reg Pop Word S PSD reg,addr4 Push Double Word 9 MD addr4,reg Multiply Double Word A DD addr4,reg Divide Double Word B PD addr4,reg Pop Doubleword C (invalid) D (invalid) E (invalid) F (invalid) 0 o X 31 -..,,------/ 4 5 7 t \. 8 , 15 ~~~~ F F 0-7 10-71 X I X I X o 4 byte,reg CBI Operation code 1 1 111 X Compare Byte Immediate Word displacement 5 7 8 15 ~~~~ F I F 8-F IS-FI X 1X I B-20 GA34-0022 X X BALS (reg,jdisp )* Branch and Link Short BALS (reg)* Branch and Link Short BALS addr* Branch and Link Short ( "'' ' _. :J Appendix C. Assembler Syntax c (reg 1-3 ,waddr) Coding Notes 1. 2. 3. 4. 5. The effective address is the contents of the register reg 1-3 , added to the value of waddr. (AM=10) displ (reg 1-3,disp 2)*fhe effective address is calculated as follows: The contents of the register reg are added to the value of the displacement disp2 to form an address. The contents of that storage location are added to the value of dis pI to form the effective address. (AM=l1) disp (reg 1-3 )* The effective address is the contents of storage at the address 3 defined by the contents of reg 1- , added to the value of disp. (AM=l1) (reg 1-3)* The effective address is the contents of storage at the address defined by the contents of reg 1-3 . (AM=l1) 1 3 (reg - ,disp)* The contents reg 1-3 are added to disp, forming an address. The contents of storage at that address form the effective address. (AM=l1) Data flow, when it modifies a field, is always from left to right. Registers used in effective address calculations are always in parentheses. An address specification followed by an asterisk indicates indirect addressing. Here, the effective address is the contents of the addressed storage location. The (reg)+ format indicates that, after use, the contents of reg are increased by the number of bytes addressed. AM indicates address mode. Legend for Machine Instruction Operands abcnt c addr addr4 An absolute value or expression representing the size of a work storage area to be allocated by the Store Multiple (STM) instruction. The value you code must be an even number in the range 0-16382. An address value. Code an absolute or relocatable expression in the range 0-65535. An address value that you code in one of the following forms: (reg O- 3 ) The effective address is the contents of the reg 0-3. (AM=OO) addr addr* o The effective address is the contents of the register reg O- 3 . After an instruction uses it, the contents of the register are increased by the number of bytes addressed by the instruction. (AM-Ol) The effective address is the value of addr, unless the instruction and addr are within the range of the same USING statement. If they are, the assembler computes the effective address as a displacement (-32768 to +32767 or 0 to 65535) from the base register, which must be reg 1-3. (AM = 10) The effective address is the contents of storage at the address defined by addr, unless the instruction and addr are within the domain and range of the same USING statement. If they are, the assembler computes the effective address as the contents of storage at the address defined by a displacement (0 255) from the base register, which must be reg 1-3. (AM=I1) addr5 For the byte addressing, the effective address can be even or odd. For word or doubleword addressing, the effective address must be even. An address value that you code in one of the following forms: (reg) The effective address is the contents of the register reg. (AM=OO) (reg) + The effective address is the contents of the register reg. After an instruction uses it, the contents of the register are increased by the number of bytes addressed by the instruction. (AM=Ol) addr The effective address is the value of addr, unless the instruction and addr are within the domain and range of the same USING statement. If they are, the assembler computes the effective address as a displacement (-32768 to +32767 or 0 to 65535) from the base register, which must be reg 1-7. (AM=10) Assembler Syntax C-l addr* The effective address is the contents of storage at the address defined by addr, unless the instruction and addr are within the domain and range of the same USING statement. If they are, the assembler computes the effective address as the contents of storage at the address defined by a displacement (0-255) from the base register, which must be reg 1-7. (AM=ll) jaddr jdisp longaddr (reg 1 -7, waddr) bitdisp byte cnt16 cnt31 cond disp freg The effective address is the contents of reg l - 7 , added to the value of waddr. (AM=10) displ(reg l - 7 ,disp2)* The effective address is calculated as follows: The contents of the register reg l - 7 are added to the value of the displacement disp2 to form an address. The contents of that storage location are added to the value of displ to form the effective address. (AM=l1) disp(reg l - 7 )* The effective address is the contents of storage at the address defined by the contents of 1-7 reg , added to the value of disp. (AM=ll) (reg l - 7 )* The effective address is the contents of storage at the address defined by the contents of reg 1-7 . (AM=l1) l 7 (reg - ,disp)* The contents of reg l - 7 are added to disp, forming an address. The contents of storage at that address form the effective address. (AM=ll) For byte addressing, the effective address can be even or odd. For word or doubleword addressing, the effective address must be even. A displacement into a bit field. Code an absolute value or expression in the range 0-63. A byte value. Code an absolute value or expression in the range -128 to +127 or 0 to 255. A single word (one register) shift count. Code an absolute value or expression in the range 0-16. A doubleword (register pair) shift count. Code an absolute vall!~ or expression in the range 0-31. A condition code value. Code an absolute value or expression in the range 0-7, A byte address displacement. Code an absolute value or expression in the range 0-255. A floating-point register. Code either a predefined floating register symbol (FRO-FR3) or a symbol that is equated to the desired register number (0, 1, 2, or 3). Symbols are equated with EQUR statements, which must precede the instruction using the register symbol. raddr reg reg 0-3 The address of an instruction that is within -256 to +254 bytes of the byte following a jump instruction. Code a relocatable expression. A displacement from the byte following a jump instruction. Code an absolute value or expression in the range -256 to +254. An address value that you code in one of the following forms: The effective address is the value addr of addr, unless the instruction and addr are within the domain and range of the same USING statement. If they are, the assembler computes the effective address as a displacement (-32768 to +32767 or 0 to 65535) from the base register, which must be reg l - 7 The effective address is the addr* contents of storage at the address defined by addr, unless the instruction and addr are within the domain and range of the same USING statement. If they are, the assembler computes the effective address as the contents of storage at the address defined by a displacement (-32768 to +32767 or 0 to 65535) from the base register, which must be reg 1-7 . (reg l - 7 ,waddr) The effective address is the contents of reg l - 7 , added to the value of waddr. (reg l - 7 ,waddr)* The contents of the reg l - 7 , plus waddr, form an address. The contents of storage at that location form the effective address. (reg l - 7 ) The effective address is the 1-7 contents of the register reg (reg l - 7 )* The effective address is the contents of storage at the address defined by the contents of reg 1-7 . An address value. Code a relocatable expression in the range 0-65535. A general-purpose register. Code either a predefined register symbol (RO-R7) or a symbol that is equated to the desired register number (0,1,2,3,4, 5,6, or 7). Symbols are equated with EQUR statements, which must precede the instruction using the register symbol. A general-purpose register. Code either a predefined register symbol (RO-R3) or a symbol that is equated to the desired register number (0, 1, 2, or 3), Symbols are equated with EQUR statements, which must precede the instruction using the register symbol. (~ f " ~ (: C-2 GA34-0022 C reg 1-3 reg 1-7 shortaddr (~ A general-purpose register. Code either a predefined register symbol (RI--R3) or a symbol that is equated to the desired register number (1, 2, or 3). Symbols are equated with EQUR statements, which must precede the instruction using the register symbol. A general-purpose register. Code either a predefined register symbol (Rl- R 7) or a symbol that is equated to the desired register number (1, 2, 3, 4, 5, 6, or I). Symbols are equated with EQUR statements, which must precede the instructions using the register symbol. An address value that you code in one of the following forms: (regO- 3 ,wdisp) The effective address is the value of wdisp added to the contents of reg 0-3 . 3 (reg O- ,wdisp)* The effective address is the contents of storage at the address defined by the value of wdisg added to the contents of reg -3. (reg O- 3 ) The effective address is the contents of (reg O- 3 ). O 3 (reg - )* The effective address is the contents of storage at the address defined by the contents of reg O- 3 • To use this form, the instruction addr and addr must be in the domain and range of the same USING statement. The assembler computes a displacement (0-62) and register combination that refers to the requested location. Same as addr, except the addr* assembler computes the effective address as the contents of storage at the address defined by a displacement (0-62) and register combination. Note: For addr and addr*, the base register must be reg O- 3 ubyte vcon waddr wdisp word An unsigned byte value or mask. Code an absolute value or expression in the range 0-255. An ordinary symbol that is defined externally from the current source program. A one-word address value. Code an absolute or relocatable expression in the range -32768 to +32767 or 0 to 65535. An even byte address displacement. Code an absolute value or expression in the range 0-62. A word value. Code an absolute value or expression in the range -32768 to +32767 or 0 to 65535. register sym bo 1 (R o o Assembler Syntax C-3 C-4 GA34-0022 o Appendix D. Numbering Systems and Conversion Tables Hexadecimal Number System Binary and Hexadecimal Number Notations Binary Number Notation A binary number system, such as is used in Series/I, uses a base of two. The concept of using a base of two can be compared with the base of ten (decimal) number system. c Decimal number Binary number 0 1 2 3 4 5 6 7 8 9 =0 =1 = 10 = 11 = 100 = 101 = 110 = 111 = 1000 = 1001 Example of a decimal number: 2 , I + 3 \+ . ~+ ~+ '1-..... 0", ""'0 .;> .". 0" 0 a 9 units position=:J 1 30 tens position 200 hundreds position !or + + 1000 thousands position 1239 = decimal number As shown above, the decimal number system allows counting to ten in each position from units to tens to hundreds to thousands, etc. The binary system allows counting to two in each position. Register displays in the Series/1 are in binary form: a bit light on is a 1; a bit light off is a 0. It has been noted that binary numbers require about three times as many positions as decimal numbers to express the equivalent number. This is not much of a problem to the computer; however, in talking and writing or in communicating with the computer, these binary numbers are bulky. A long string of 1's and O's cannot be effectively transmitted from one individual to another. Some shorthand method is necessary . The hexadecimal number system fills this need. Because of the simple relationship of hexadecimal to binary , numbers can be converted from one system to another by inspection. The base or radix of the hexadecimal system is 16. This means there are 16 symbols: 0,1,2,3,4,5,6,7, 8,9, A, B, C, D, E, and F. The letters A, B, C, D, E, and F represent the 10-base system values of 10, 11,12, 13, 14, and 15, respectively. Four binary positions are equivalent to one hexadecimal position. The following table shows the comparable values of the three number systems. Decimal Binary Hexadecimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 a 2 3 4 5 6 7 8 9 A B C D E F Example of a binary number: o J 1 +0001 = decimal 01 jJ l +0000 = decimal --.J /+~'" ~~.;> ~~" +~o\ or _+00_00_=de_cim_al_ 0- - - - - ' \ \ \ , 1000 = decimal 8 o 1001 = decimal 9 At this point, all 16 symbols have been used, and a carry to the next higher position of the number is necessary. For example: Decimal Binary Hexadecimal 16 17 18 19 20 21 0001 0001 0001 0001 0001 0001 10 11 12 13 14 15 0000 0001 0010 0011 0100 0101 -and so on- Numbering Systems and Conversion Tables D-1 Remember that as far as the internal circuitry of the computer is concerned, it understands only binary. But an operator can look at a series of lights on the computer console showing binary 1's and O's, for example: 0001 11100001 0011, and say that the lights represent the hexadecimal value lE13, which is easier to state than the string of 1's and O's. For numbers outside the range of the table, add the following values to the tables figures: Hexadecimal-Decimal Conversion Tables Hexadecimal Decimal 1000 2000 3000 4000 5000 6000 7000 8000 4096 8192 12288 16384 20480 24576 28672 32768 (; The table in this appendix provides for direct conversion of decimal and hexadecimal number in these ranges: Hexadecimal Decimal 000 to FFF 0000 to 4095 r----- 9 r---- E 0000: 000.: ••• 0:I . 0 0 . 0 r---- 1 ~I ~I ~I ~ I I I I I I-------------------------~ I Ir-------------------------------J __________ ...JI II II II II 0 2 3 4 5 6 7 8 9 A B C 0001 0002 0003 0000 0004 0005 0006 0007 0010 0011 0012 0016 0017 0018 0019 0020 0021 0022 0023 0026 0027 0028 0032 0033 0034 0035 0036 0037 0038 0039 0042 0043 0044 0048 0049 0050 0051 0052 0053 0054 0055 0058 0059 0060 0064 0065 0066 0067 0074 0075 0076 0068 0069 0070 0071 OL 0080 0081 0082 0083 0090 0091 0084 0085 0086 0087 0092 05_ 0096 0097 0098 0099 0108 06_ 0100 0101 0102 0103 0106 0107 0112 0113 0114 0115 0122 0123 0124 0116 0117 0118 0119 OL 0128 0129 0130 0131 08_ 0132 0133 0134 0135 0138 0139 0140 09_ 0144 0145 0146 0147 0148 0149 0150 0151 0154 0155 0156 0160 0161 0162 0163 0164 0165 0166 0167 0170 0171 0172 OAOB_ 0176 0177 0178 0179 0180 0181 0182 0183 0186 0187 0188 OC_ 0192 0193 0194 0195 0196 0197 0198 0199 0202 0203 0204 OD_ 0208 0209 0210 0211 0218 0219 0212 0213 0214 0215 0220 OE_ 0224 0225 0226 0227 0228 0229 0230 0231 0234 0235 0236 OF_ 0240 0241 0242 0243 0244 0245 0246 0247 0250 0251 0252 10_ 0256 0257 0258 0259 0260 0261 0262 0263 0266 0267 0268 0272 0273 0274 0275 0276 0277 0278 0279 0282 0283 0284 1L 0288 0289 0290 0291 0292 0293 0294 0295 0298 0299 0300 1L 13_ 0304 0305 0306 0307 0314 0315 0316 0308 0309 0310 0311 14_ 0320 0321 0322 0323 0330 0331 0332 0324 0325 0326 0327 15_ 0336 0337 0338 0339 0346 0347 0348 0340 0341 0342 0343 16_ 0352 0353 0354 0355 0356 0357 0358 0359 0362 0363 0364 0368 0369 0370 0371 1L 0378 0379 0380 0372 0373 0374 0375 18_ 0384 0386 0389 0394 0395 0396 19_ 0400 0402 0405 0410 0411 0412 1A_ 0416 0418 0421 0426 0427 0428 1B_ 0432 0434 0437 0442 0443 0444 0458 0459 0460 0474 0475 0476 0492 0490 0491 0506 0507 0508 D-2 GA34-0022 D E F 0013 0029 0045 0061 0077 0093 0109 0125 0141 0157 0173 0189 0205 0221 0237 0253 0014 0030 0046 0062 0018 0094 0110 0126 0142 0158 0174 0190 0206 0222 0238 0254 0270 0286 0302 0318 0334 0350 0366 0382 0398 0414 0430 0446 0462 0478 0494 0510 0015 0031 0047 0063 0079 0095 0111 0127 0143 0159 0175 0191 0207 0223 0239 0255 0269 0285 0301 0317 0333 0349 0365 0381 0397 0413 0429 0445 0461 0477 0493 0509 0271 0287 0303 0319 0335 0351 0367 0383 0399 0415 0431 0447 0463 0479 0495 0511 , \ .. ; o c r7- 0 1 2 3 4 5 6 7 8 9 A B C D E F 0513 0529 0545 0561 0577 0593 0514 0530 0546 0562 0578 0594 0515 0531 0547 0563 0579 0595 0516 0532 0548 0564 0580 0596 0517 0533 0549 0565 0581 0597 0518 0534 0550 0566 0582 0598 0520 0536 0552 0568 0584 0600 0521 0537 0553 0569 0585 0601 0523 0539 0555 0571 0587 0603 06.it; 0635 0651 0667 0683 0699 0715 0731 0747 0763 0524 0540 0556 0572 0588 0604 06:2.0 0636 0652 0668 06'84 0700 0716 0732 0748 0764 0525 0541 0557 0573 0589 0605 06:2.1 0637 0653 0669 0685 0701 0717 0733 0749 0765 0526 0542 0558 0574 0590 0606 0527 0543 0559 0575 0591 0607 0779 0795 0811 0827 0843 0859 0875 0891 0907 0923 0939 0955 0971 0987 1003 1019 0780 0796 0812 0828 0844 0860 0876 0892 0908 0924 0940 09.56 0972 0988 1004 1020 0781 0797 0813 0829 0845 0861 0877 0893 0909 0925 0941 0957 0973 0989 1005 1021 2tL OtiOtl OOU\:.I Uti1U UtH! UtHlI. UtH-i UtH'l 2L 28_ 29_ 2A_ 2B_ 2C_ 2D_ 2E_ 2F_ 0624 0640 0656 0672 0688 0704 0720 0736 0752 0625 0641 0657 0673 0689 0705 0721 0737 0753 0626 0642 0658 0674 0690 0706 0722 0738 0754 0627 0643 0659 0675 0691 0707 0723 0739 0755 0628 0644 0660 0676 0692 0708 0724 0740 0756 0629 0645 0661 0677 0693 0709 0725 0741 0757 0630 0646 0662 0678 0694 0710 0726 0742 0758 0519 0535 0551 0567 0583 0599 06la 0631 0647 0663 0679 0695 0711 0727 0743 0759 30_ 3L 32_ 33_ 3L 35_ 36_ 3L 38_ 39_ 3A_ 3B 3C_ 3D_ 3E_ 3F_ 0768 0784 0800 0816 0832 0848 0864 0880 0896 0912 0928 0944 0960 0976 0992 1008 0769 0785 0801 0817 0833 0849 0865 0881 0897 0913 0929 094.'5 0961 0977 0993 1009 0770 0786 0802 0818 0834 0850 0866 0882 0898 0914 0930 0946 0962 0978 0994 1010 0771 0787 0803 0819 0835 0851 0867 0883 0899 0915 0931 0947 0963 0979 0995 1011 0772 0788 0804 0820 0836 0852 0868 0884 0900 0916 0932 0948 0964 0980 0996 1012 0773 0789 0805 0821 0837 0853 0869 0885 0901 0917 0933 0949 0965 0981 0997 1013 0774 0790 0806 0822 0838 0854 0870 0886 0902 0918 0934 0950 0966 0982 0998 1014 0775 0791 0807 0823 0839 0855 0871 0887 0903 0919 0935 0951 0967 0983 0999 1015 0 1 2 3 4 5 6 7 8 9 A B C D E F 40_ 4L 42_ 43_ 4L 45_ 46_ 4L 48_ 49_ 4A_ 4B_ 4C_ 4D_ 4E_ 4F_ 1024 1040 1056 1072 1088 1104 1120 1136 1152 1168 1184 1200 1216 1232 1248 1264 1025 1041 1057 1073 1089 1105 1121 1137 1153 1169 1185 1201 1217 1233 1249 1265 1026 1042 1058 1074 1090 1106 1122 1138 1154 1170 1186 1202 1218 1234 1250 1266 1027 1043 1059 1075 1091 1107 1123 1139 1155 1171 1187 1203 1219 1235 1251 1267 1028 1044 1060 1076 1092 1108 1124 1140 1156 1172 1188 1204 1220 1236 1252 1268 1029 1045 1061 1077 1093 1109 1125 1141 1157 1173 1189 1205 1221 1237 1253 1269 1030 1046 1062 1078 1094 1110 1126 1142 1158 1174 1190 1206 1222 1238 1254 1270 1031 1047 1063 1079 1095 1111 1127 1143 U59 1175 1191 1207 1223 1239 1255 1271 1032 1048 1064 1080 1096 1112 1128 1144 1160 1176 1192 1208 1224 1240 1256 1272 1033 1049 1065 1081 1097 1113 1129 1145 1161 1177 1193 1209 1225 1241 1257 1273 1034 1050 1066 1082 1098 1114 1130 1146 1162 1178 1194 1210 1226 1242 1258 1274 1035 1051 1067 1083 1099 1115 1131 1147 1163 1179 1195 1211 1227 1243 1259 1275 1036 1052 1068 1084 1100 1116 1132 1148 1164 1180 1196 1212 1228 1244 1260 1276 1037 1053 1069 1085 1101 1117 1133 1149 1165 1181 1197 1213 1229 1245 1261 1277 1038 1054 1070 1086 1102 1118 1134 U50 1166 1182 1198 1214 1230 1246 1262 1278 1039 1055 1071 1087 1103 1119 1135 1151 1167 U83 1199 1215 1231 1247 1263 1279 50_ 5L 52_ 53_ 54_ 55_ 56_ 5L 58_ 59_ 5A_ 5B_ 5C_ 5D_ 5E_ 5F_ 1280 1296 1312 1328 1344 1360 1376 1392 1408 1424 1440 1456 1472 1488 1504 1520 1281 1297 1313 1329 1345 1361 1377 1393 1409 1425 1441 1457 1473 1489 1505 1521 1282 1298 1314 1330 1346 1362 1378 1394 1410 1426 1442 1458 1474 1490 1506 1522 1283 1299 1315 1331 1347 1363 1379 1395 1411 1427 1443 1459 1475 1491 1507 1523 1284 1300 1316 1332 1348 1364 1380 1396 1412 1428 1444 1460 1476 1492 1508 1524 1285 1301 1317 1333 1349 1365 1381 1397 1413 1429 1445 1461 1477 1493 1509 1525 1286 1302 1318 1334 1350 1366 1382 1398 1414 1430 1446 1462 1478 1494 1510 1526 1287 1303 1319 1335 1351 1367 1383 1399 1415 1431 1447 1463 1479 1495 1511 1527 1288 1304 1320 1336 1352 1368 1384 1400 1416 1432 1448 1464 1480 1496 1512 1528 1289 1305 1321 1337 1353 1369 1385 1401 1417 1433 1449 1465 1481 1497 1513 1529 1290 1306 1322 1338 1354 1370 1386 1402 1418 1434 1450 1466 1482 1498 1514 1530 1291 1307 1323 1339 1355 1371 1387 1403 1419 1435 1451 1467 1483 1499 1515 1531 1292 1308 1324 1340 1356 1372 1388 1404 1420 1436 1452 1468 1484 1500 1.516 1532 1293 1309 1325 1341 1357 1373 1389 1405 1421 1437 1453 1469 1485 1501 1517 1533 1294 1310 1326 1342 1358 1374 1390 1406 1422 1438 1454 1470 1486 1502 1518 1534 1295 1311 1327 1343 1359 1375 1391 1407 1423 1439 1455 1471 1487 1503 1519 1,535 201 2L 22_ 23_ 24_ 25_ 0512 0528 0544 0560 0576 0592 06.i6 VOl/ 0632 0648 0664 0680 0696 0712 0728 0744 0760 0633 0649 0665 0681 0697 0713 0729 0745 0761 0522 0538 0554 0570 0586 0602 ---V010 0634 0650 0666 0682 0698 0714 0730 0746 0762 0776 0792 0808 0824 0840 0856 0872 0888 0904 0920 0936 0952 0968 0984 1000 1016 0777 0793 0809 0825 0841 0857 0873 0889 0905 0921 0937 0953 0969 0985 1001 1017 0778 0794 0810 0826 0842 0858 0874 0890 0906 0922 0938 0954 0970 0986 1002 1018 - --- 0622- 0623 0638 0654 0670 0686 0702 0718 0734 0750 0766 0639 0655 0671 0687 0703 0719 0735 0751 0767 0782 0798 0814 0830 0846 0862 0878 0894 0910 0926 0942 0958 0974 0990 1006 1022 0783 0799 0815 0831 0847 0863 0879 0895 0911 0927 0943 0959 0975 0991 1007 1023 o Numbering Systems and Conversion Tables D-3 r-'-o 601 6L 6L 63_ 6L 65_ 66_ 6L 68_ 69_ 6~ 6B_ 6C_ 6D_ 6E_ 6F_ 70_ 7L 72_ 73_ 74_ 75_ 76_ 7L 78_ 79_ 7A_ 7B_ 7C_ 7D_ 7E_ 7F_ 80_ 8L 82_ 83_ 8L 85_ 86_ 8L 88_ 89_ 8A_ 8B_ 8C_ 8D_ 8E 8F 90_ 91 9L 93_ 9L 95_ 96_ 9L 98_ 99_ 9A_ 9B_ 9C_ 9D_ 9E_ 9F_ D-4 GA34-0022 1 2 3 4 5 6 7 8 9 A B C D E F 1536 1552 1568 1584 1600 1616 1632 1648 1664 1680 1696 1712 1728 1744 1760 1776 1537 1553 1569 1585 1601 1617 1633 1649 1665 1681 1697 1713 1729 1745 1761 1777 1538 1554 1570 1586 1602 1618 1634 1650 1666 1682 1698 1714 1730 1746 1762 1778 1539 1555 1571 1587 1603 1619 1635 1651 1667 1683 1699 1715 1731 1747 1763 1779 1540 1556 1572 1588 1604 1620 1636 1652 1668 1684 1700 1716 1732 1748 1764 1780 1541 1557 1573 1589 1605 1621 1637 1653 1669 1685 1701 1717 1733 1749 1765 1781 1542 1558 1574 1590 1606 1622 1638 1654 1670 1686 1702 1718 1734 1750 1766 1782 1543 1559 1575 1591 1607 1623 1639 1655 1671 1687 1703 1719 1735 1751 1767 1783 1544 1560 1576 1592 1608 1624 1640 1656 1672 1688 1704 1720 1736 1752 1768 1784 1545 1561 1577 1593 1609 1625 1641 1657 1673 1689 1705 1721 1737 1753 1769 1785 1546 1562 1578 1594 1610 1626 1642 1658 1674 1690 1706 1722 1738 1754 1770 1786 1547 1563 1579 1595 1611 1627 1643 1659 1675 1691 1707 1723 1739 1755 1771 1787 1548 1564 1580 1596 1612 1628 1644 1660 1676 1692 1708 1724 1740 1756 1772 1788 1549 1565 1581 1597 1613 1629 1645 1661 1677 1693 1709 1725 1741 1757 1773 1789 1550 1566 1582 1598 1614 1630 1646 1662 1678 1694 1710 1726 1742 1758 1774 1790 1551 1567 1583 1599 1615 1631 1647 1663 1679 1695 1711 1727 1743 1759 1775 1791 1792 1808 1824 1840 1856 1872 1888 1904 1920 1936 1952 1968 1984 2000 2016 2032 1793 1809 1825 1841 1857 1873 1889 1905 1921 1937 1953 1969 1985 2001 2017 2033 1794 1810 1826 1842 1858 1874 1890 1906 1922 1938 1954 1970 1986 2002 2018 2034 1795 1811 1827 1843 1859 1875 1891 1907 1923 1939 1955 1971 1987 2003 2019 2035 1796 1812 1828 1844 1860 1876 1892 1908 1924 1940 1956 1972 1988 2004 2020 2036 1797 1813 1829 1845 1861 1877 1893 1909 1925 1941 1957 1973 1989 2005 2021 2037 1798 1814 1830 1846 1862 1878 1894 1910 1926 1942 1958 1974 1990 2006 2022 2038 1799 1815 1831 1847 1863 1879 1895 1911 1927 1943 1959 1975 1991 2007 2023 2039 1800 1816 1832 1848 1864 1880 1896 1912 1928 1944 1960 1976 1992 2008 2024 2040 1801 1817 1833 1849 1865 1881 1897 1913 1929 1945 1961 1977 1993 2009 2025 2041 1802 1818 1834 1850 1866 1882 1898 1914 1930 1946 1962 1978 1994 2010 2026 2042 1803 1819 1835 1851 1867 1883 1899 1915 1931 1947 1963 1979 1995 2011 2027 2043 1804 1820 1836 1852 1868 1884 1900 1916 1932 1948 1964 1980 1996 2012 2028 2044 1805 1821 1837 1853 1869 1885 1901 1917 1933 1949 1965 198J 1997 2013 2029 2045 1806 1822 1838 1854 1870 1886 1902 1918 1934 1950 1966 1982 1998 2014 2030 2046 1807 1823 1839 1855 1871 1887 1903 1919 1935 1951 1967 1983 1999 2015 2031 2047 0 1 2 3 4 5 6 7 8 9 A B C D E F 2048 2064 2080 2096 2112 2128 2144 2160 2176 2192 2208 2224 2240 2256 2272 2288 2049 2065 2081 2097 2113 2129 2145 2161 2177 2193 2209 2225 2241 2257 2273 2289 2050 2066 2082 2098 2114 2130 2146 2162 2178 2194 2210 2226 2242 2258 2274 2290 2051 2067 2083 2099 2115 2131 2147 2163 2179 2195 2211 2227 2243 2259 2275 2291 2052 2068 2084 2100 2116 2132 2148 2164 2180 2196 2212 2228 2244 2260 2276 2292 2053 2069 2085 2101 2117 2133 2149 2165 2181 2197 2213 2229 2245 2261 2277 2293 2054 2070 2086 2102 2118 2134 2150 2166 2182 2198 2214 2230 2246 2262 2278 2294 2055 2071 2087 2103 2119 2135 2151 2167 2183 2199 2215 2231 2247 2263 2279 2295 2056 2072 2088 2104 2120 2136 2152 2168 2184 2200 2216 2232 2248 2264 2280 2296 2057 2073 2089 2105 2121 2137 2153 2169 2185 2201 2217 2233 2249 2265 2281 2297 2058 2074 2090 2106 2122 2138 2154 2170 2186 2202 2218 2234 2250 2266 2282 2298 2059 2075 2091 2107 2123 2139 2155 2171 2187 2203 2219 2235 2251 2267 2283 2299 2060 2076 2092 2108 2124 2140 2156 2172 2188 2204 2220 2236 2252 2268 2284 2300 2061 2077 2093 2109 2125 2141 2157 2173 2189 2205 2221 2237 2253 2269 2285 2301 2062 2078 2110 2126 2142 2158 2174 2190 2206 2222 2238 2254 2270 2286 2302 2063 2079 2095 2111 2127 2143 2159 2175 2191 2207 2223 2239 2255 2271 2287 2303 2304 2320 2336 2352 2368 2384 2400 2416 2432 2448 2464 2480 2496 2512 2528 2544 2305 2321 2337 2353 2369 2385 2401 2417 2433 2449 2465 2481 2497 2513 2529 2545 2306 2322 2338 2354 2370 2386 2402 2418 2434 2450 2466 2482 2498 2514 2530 2546 2307 2323 2339 2355 2371 2387 2403 2419 2435 2451 2467 2483 2499 2515 2531 2547 2308 2324 2340 2356 2372 2388 2404 2420 2436 2452 2468 2484 2.500 2516 2532 2548 2309 2325 2341 2357 2373 2389 2405 2421 2437 2453 2469 2485 2501 2517 2533 2549 2310 2326 2342 2358 2374 2390 2406 2422 2438 2454 2470 2486 2502 2518 2534 2550 2311 2327 2343 2359 2375 2391 2407 2423 2439 2455 2471 2487 2503 2519 2535 2551 2312 2328 2344 2360 2376 2392 2408 2424 2440 2456 2472 2488 2504 2520 2536 2552 2313 2329 2345 2361 2377 2393 2409 2425 2441 2457 2473 2489 2505 2521 2537 2553 2314 2330 2346 2362 2378 2394 2410 2426 2442 2458 2474 2490 2506 2522 2538 2554 2315 2331 2347 2363 2379 2395 2411 2427 2443 2459 2475 2491 2507 2523 2539 2555 2316 2332 2348 2364 2380 2396 2412 2428 2444 2460 2476 2492 2508 2524 2540 2556 2317 2333 2349 2365 2381 2397 2413 2429 2445 2461 2477 2493 2509 2525 2541 2557 2318 2334 2350 2366 2382 2398 2'tl4 2430 2446 2462 2478 2494 2510 2526 2542 2558 2319 2335 2351 2367 2383 2399 2415 2431 2447 2463 2479 2495 2511 2527 2543 2559 ~094 c r+ o Aol 2 3 4 5 6 7 8 9 A B C D E F 2562 2578 2,594 2610 2626 2642 2563 2579 2595 2611 2627 2643 2564 2580 2596 2612 2628 2644 2,565 2581 2597 2613 2629 2645 2566 2582 2598 2614 2630 2646 2568 2584 2600 2616 2632 2648 2569 2585 2601 2617 2633 2649 2570 2586 2602 2618 2634 2650 2571 2587 2603 2619 2635 2651 2572 2588 2604 2620 2636 2652 2573 2,589 260.'5 2621 2637 2653 2574 2590 2606 2622 2638 2654 2575 2591 2607 2623 2639 2655 2uu'-:; ..::;..uuu _UUj 1'"1""0 n~nr\ (\a"'11'\ ~e7l 2680 2696 2712 2728 2744 2760 2776 2792 2808 2681 2697 2713 2729 2745 2761 2777 2793 2809 2682 2698 2714 2730 2746 2762 2778 2794 2810 2683 2699 2715 2731 2747 2763 2779 2795 2811 2684 2700 2716 2732 2748 2764 2780 2796 2812 2685 2701 2717 2733 2749 2765 2781 2797 2813 2686 2702 2718 2734 2750 2766 2782 2798 2814 2687 2703 2719 2735 2751 2767 2783 2799 2815 2824 2840 2856 2872 2888 2904 2920 2936 29,52 2968 2984 3000 3016 3032 3048 3064 282,5 2841 2857 2873 2889 290,5 2921 2937 29,5,3 2969 2985 3001 3017 3033 3049 3065 2826 2842 2858 2874 2890 2906 2922 2938 29,54 2970 2986 3002 3018 3034 3050 3066 2827 2843 2859 2875 2891 2907 2923 2939 29,5,5 2971 2987 3003 3019 3035 3051 3067 2828 2844 2860 2876 2892 2908 2924 2940 2956 2972 2988 ,3004 3020 3036 3052 3068 2829 2845 2861 2877 2893 2909 292,5 2941 2957 2973 2989 3005 302.1 3037 3053 3069 2830 2846 2862 2878 2894 2910 2926 2942 2958 2974 2990 3006 3022 3038 3054 3070 2831 2847 2863 2879 2895 2911 2927 2943 2959 297,5 2991 3007 3023 3039 3055 3071 A5 A6_ A7 A8 A9_ AA AB_ AC_ AD AE AF :!.b,S{j :!.6bl ~bo1:i ~bo\:J ~bb\l 2001 ~oo~ 2672 2688 2704 2720 2736 2752 2768 2784 2800 2673 2689 2705 2721 2737 2753 2769 2785 2801 2674 2690 2706 2722 2738 2754 2770 2786 2802 2675 2691 2707 2723 2739 2755 2771 2787 2803 2676 2692 2708 2724 2740 2756 2772 2788 2804 2677 2693 2709 2725 2741 2757 2773 2789 2805 2678 2694 2710 2726 2742 2758 2774 2790 2806 BO Bl B2 B3 BL B5_ B6 B7 B8_ B9 BA BB BC BD BE BF 2816 2832 2848 2864 2880 2896 2912 2928 2944 2960 2976 2992 3008 3024 3040 3056 2817 2833 2849 2865 2881 2897 2913 2929 2945 2961 2977 2993 3009 3025 3041 30,57 2818 2834 2850 2866 2882 2898 2914 2930 2946 2962 2978 2994 3010 3026 3042 3058 2819 2835 2851 2867 2883 2899 2915 2931 2947 2963 2979 2995 3011 3027 3043 3059 2820 2836 28,52 21)68 2884 2900 2916 2932 2948 2964 2980 2996 3012 3028 3044 3060 2821 2837 28,53 2869 288S 2901 2917 2933 2949 296,5 2981 2997 3013 3029 3045 3061 2822 2838 2854 2870 2886 2902 2918 2934 29,50 296fi 2982 2998 3014 3030 3046 3062 2823 2839 2855 2871 2887 2903 2919 2935 2951 2967 2983 2999 301.5 3031 3047 3063 0 1 2 3 4 5 6 7 8 9 A B C D E F CO Cl C2 C3 C4 Co5 C6 C7 C8 C9 CA CB CC CD CE CF 3072 3088 3104 3120 31.36 31.52 3168 3184 3200 3216 3232 ,3248 3264 3280 3296 3312 3073 3089 3105 3121 3137 3153 3169 3185 3201 3217 3233 3249 326,5 3281 3297 3313 3074 3090 3106 3122 3138 3154 3170 3186 3202 3218 3234 32,50 ,3266 3282 3298 3314 3075 3091 3107 3123 3139 3155 3171 3187 3203 3219 3235 3251 3267 3283 3299 3315 3076 3092 3108 3124 3140 3156 3172 3188 3204 3220 32,36 3252 3268 32H4 3,300 3316 3077 3093 3109 3125 ,3141 3157 3173 3189 3205 ,3221 3237 32,53 3269 3285 3301 3317 3078 3094 3110 3126 3142 3158 3174 3190 3206 3222 3238 3254 3270 3286 3302 3318 3079 3095 3111 3127 3143 3159 3175 3191 ,3207 3223 3239 3255 3271 3287 3303 3319 3080 3096 3112 3128 3144 3160 3176 3192 3208 ,3.224 3240 32,5fi 3272 3288 3304 3320 3081 ,,}O97 3113 3129 314S 3161 3177 3193 3209 3225 3241 3257 3273 321)9 3305 3321 3082 3098 3114 3130 3146 3162 3178 3194 3210 ,3226 3242 32,58 3274 3290 3306 3322 3083 3099 3115 3131 3147 3163 3179 319S 3211 3227 3243 3259 327,5 3291 3307 3323 3084 3100 3116 3132 ,3148 3164 3180 3196 3212 ,3228 3244 3260 ,3276 ,3292 3308 3324 308,5 3101 3117 3133 3149 3165 3181 3197 3213 3229 324,5 3261 ,3277 3293 ,3,309 332.5 ,3086 3102 3118 3134 3150 3166 3182 3198 3214 3230 3246 3262 3278 3294 3310 3326 3087 3103 3119 3135 3151 3167 3183 3199 3215 3231 3247 3263 3279 329.5 3311 3327 DO Dl D2 D3 D4D5 D6 D7 D8 D9_ DA -DB DC DD-DE DF ,3328 3344 3360 3376 3392 3-408 3424 3440 3456 3472 3488 3504 3520 3536 3552 3568 3329 334,5 3361 3377 3393 3409 3425 3441 34.57 3473 3489 3505 3521 3537 35,53 3569 3330 3346 3362 3378 3394 3410 3426 3442 3458 3474 3490 3506 3522 3538 3554 3570 3331 3347 3,363 3379 3395 3411 3427 3443 3459 3475 3491 3507 3523 3539 3555 3571 3332 3348 3364 3380 3396 3412 3428 3444 3460 3476 3492 3.508 3524 3540 3,556 3572 ,3333 3349 336.5 3381 3397 3413 3429 3445 3461 3477 3493 3,509 3525 3541 3557 3573 3334 33.50 3366 3382 3398 3414 3430 3446 3462 ,3478 3494 3510 3526 3542 3558 3574 3335 3351 3367 3383 3399 3415 3431 3447 3463 3479 349,5 3.511 3527 3543 3559 3575 3336 33,52 ,3368 3384 3400 3416 3432 3448 3464 3480 3496 3.512 3528 3.544 3560 3576 3337 3353 3369 338.5 3401 3417 3433 3449 3465 3481 3497 3513 3.'529 ,354.5 3561 3577 3338 33,54 3370 ,3386 3402 3418 3434 3450 3466 3482 3498 3514 35,30 3546 3562 3578 3339 33.5,5 3371 3387 3403 3419 343,5 3451 3467 3483 3499 3515 3531 3547 3563 3.579 3340 ,3,3.56 3372 3388 3404 3120 3436 34,52 3468 3484 3500 3516 3.532 ,3548 3.564 3580 3341 3,3.57 3.373 3389 340.5 3421 3437 3453 3469 348,5 3.501 3,517 3,533 3,549 3,56,5 3581 3342 33.58 3374 3390 3406 3422 3438 3454 3470 3486 3,502 3,518 3,534 3.5.50 3,566 3.582 3343 3359 3375 3391 3407 3423 3439 345.5 3471 3487 3503 3519 3.535 3,551 3,567 3583 AL A2 A3 -A4 - - - c 1 2561 2577 2593 2609 2625 2641 2567 2583 2599 2615 2631 2647 2660 2679 2695 2711 2727 2743 2759 2775 2791 2807 - - - - -- --, - - - 2560 2576 2592 2608 2624 2640 ---- 2uu-t o Numbering Systems and Conversion Tables D-5 rT-35840 1 2 3 4 5 6 7 8 9 A B C D E F 3586 3602 3618 3634 3666 3682 3698 3714 3730 3746 3762 3778 3794 3810 3826 3587 3603 3619 3635 3651 3667 3683 3699 3715 3731 3747 3763 3779 3795 3811 3827 3588 3604 3620 3636 3652 3668 3684 3700 3716 3732 3748 3764 3780 3796 3812 3828 3589 3605 3621 3637 3653 3669 3685 3701 3717 3733 3749 3765 3781 3797 3813 3829 3590 3606 3622 3638 3654 3670 3686 3702 3718 3734 3750 3766 3782 3798 3814 3830 3591 3607 3623 3639 3655 3671 3687 3703 3719 3735 3751 3767 3783 3799 3815 3831 3592 3608 3624 3640 3656 3672 3688 3704 3720 3736 3752 3768 3784 3800 3816 3832 3593 3609 3625 3641 3657 3673 3689 3705 3721 3737 3753 3769 3785 3801 3817 3833 3594 3610 3626 3642 3658 3674 3690 3706 3722 3738 3754 3770 3786 3802 3818 3834 3595 3611 3627 3643 3659 3675 3691 3707 3723 3739 3755 3771 3787 3803 3819 3835 3596 3612 3628 3644 3660 3676 3692 3708 3724 3740 3756 3772 3788 3804 3820 3836 3597 3613 3629 3645 3661 3677 3693 3709 3725 3741 3757 3773 3789 3805 3821 3837 3598 3614 3630 3646 3662 3678 3694 3710 3726 3742 3758 3774 3790 3806 3822 3838 3599 3615 3631 3647 3663 3679 3695 3711 3727 3743 3759 3775 3791 3807 3823 3839 3842 3858 3874 3890 3906 3922 3938 3954 3970 3986 4002 4018 4034 4050 4066 4082 3843 3859 3875 3891 3907 3923 3939 3955 3971 3987 4003 4019 4035 4051 4067 4083 3844 3860 3876 3892 3908 3924 3940 3956 3972 3988 4004 4020 4036 4052 4068 4084 3845 3861 3877 3893 3909 3925 3941 3957 3973 3989 4005 4021 4037 4053 4069 4085 3846 3862 3878 3894 3910 3926 3942 3958 3974 3990 4006 4022 4038 4054 4070 4086 3847 3863 3879 3895 3911 3927 3943 3959 3975 3991 4007 4023 4039 4055 4071 4087 3848 3864 3880 3896 3912 3928 3944 3960 3976 3992 4008 4024 4040 4056 4072 4088 3849 3865 3881 3897 3913 3929 3945 3961 3977 3993 4009 4025 4041 4057 4073 4089 3850 3866 3882 3898 3914 3930 3946 3962 3978 3994 4010 4026 4042 4058 4074 4090 3851 3867 3883 3899 3915 3931 3947 3963 3979 3995 4011 4027 4043 4059 4075 4091 3852 3868 3884 3900 3916 3932 3948 3964 3980 3996 4012 4028 4044 4060 4076 4092 3853 3869 3885 3901 3917 3933 3949 3965 3981 3997 4013 4029 4045 4061 4077 4093 3854 3870 3886 3902 3918 3934 3950 3966 3982 3998 4014 4030 4046 4062 4078 4094 3855 3871 3887 3903 3919 3935 3951 3967 3983 3999 4015 4031 4047 4063 4079 4095 Eol EL E2_ E3_ EL E5_ E6 E7 E8_ E9_ EA_ EB EC_ ED_ EE EF_ 3600 3616 3632 3648 3664 3680 3696 3712 3728 3744 3760 3776 3792 3808 3824 3585 3601 3617 3633 3649 3005 3681 3697 3713 3729 3745 3761 3777 3793 3809 3825 FOF1 F2 F3F4 F5F6 -F7 F8_ F9_ FAFBFC_ FDFE FF- 3840 3856 3872 3888 3904 3920 3936 3952 3968 3984 4000 4016 4032 4048 4064 4080 3841 3857 3873 3889 3905 3921 3937 3953 3969 3985 4001 4017 4033 4049 4065 4081 ~50 \ D-6 GA34-0022 ;. C C 0 Powers of Two Table 2n n 2- n 1 2 0 1 2 3 1.0 0.5 0.25 0.125 16 32 64 128 4 5 6 7 0.0625 0.03125 0.01562 5 0.00781 25 256 512 1,024 2,048 9 10 11 0.00390 0.00195 0.00097 0.00048 625 3125 65625 82812 4,096 8,192 16,384 32,768 12 13 14 15 0.00024 0.00012 0.00006 0.00003 41406 20703 10351 05175 25 125 5625 78125 65,536 131,072 262,144 524,288 16 17 18 19 0.00001 0.00000 0.00000 0.00000 52587 76293 38146 19073 89062 94531 97265 48632 5 25 625 8125 1,048,576 2,097,152 4,194,304 8,388,608 20 21 22 23 0.00000 0.00000 0.00000 0.00000 09536 04768 023811 01192 711316 37158 18579 09289 40625 20312 5 10156 25 55078 125 16,777,216 33,554,lI32 67,108,864 134,217,728 211 25 26 27 0.00000 0.00000 0.00000 0.00000 00 59 6 00298 001119 00071.1 046411 02322 01161 50580 77539 38769 193811 59692 0625 53125 76562 5 38281 25 268,435,lI56 536,870,912 1,073,741,824 2,147,483,648 28 29 30 31 0.00000 0.00000 0.00000 0.00000 00037 00018 00009 OOOOll 25290 62645 31322 65661 29846 14923 57461 28730 19140 09570 54785 77392 625 3125 15625 57812 4,294,967,296 8,589,934,592 17,179,869,18l1 34,359,738,368 32 33 34 35 0.00000 0.00000 0.00000 0.00000 00002 00001 00000 00000 32830 16415 58207 29103 64365 32182 66091 83045 38696 69348 34674 67337 28906 141153 0722 6 03613 25 125 5625 28125 68,719,476,736 137,438,953,lI72 274,877,906,944 549,755,813,888 36 37 38 39 0.00000 0.00000 0.00000 0.00000 00000 00000 00000 00000 14551 07275 03637 01818 91522 95761 97880 98940 83668 lI1834 70917 35458 51806 25903 12951 56475 64062 32031 66015 83007 5 25 625 8125 1,099,511,627,776 2,199,023,255,552 4,398,046,511,104 8,796,093,022,208 40 41 42 lI3 0.00000 0.00000 0.00000 0.00000 00000 00000 000 00 00000 00909 00454 00227 00113 lI9470 74735 37367 68683 17729 08864 54432 77216 28237 64118 32059 16029 91503 95751 47875 73937 90625 95312 5 97656 25 98828 125 17,592,186,Oll4,416 35,184,372,088,832 70,368,744,177,664 140,737,488,355,328 411 lI5 46 lI7 0.00000 0.00000 0.00000 0.00000 00000 00000 00000 00000 00056 00028 000111 00007 84341 42170 21085 10542 88608 94304 47152 73576 08014 04007 02003 01001 86968 lI3484 717112 85871 99414 49707 211853 121126 0625 03125 51562 5 75781 25 281,474,976,710,656 562,949,953,421,312 l,125,899,906,8l12,62l1 2,251,799,813,685,248 48 49 50 51 0.00000 0.00000 0.00000 0.00000 00000 00000 00000 00000 00 00 3 00001 00 000 00000 55271 77635 88817 44408 36788 68394 811197 92098 00500 00 250 00125 50062 92935 lI6467 23233 61616 56213 78106 89053 94526 37890 689115 34472 67236 625 3125 65625 32812 4,503,599,627,370,496 9,007,199,254,740,992 18,014,398,509,481,984 36,028,797,018,963,968 52 53 54 55 0.00000 00000 00000 22204 0.00000 0000 a 00000 11102 0.00000 00000 00000 05551 O.noooo 00000 00000 02775 46049 ?3024 11512 55756 25031 62515 31257 15628 30808 6540ll 82702 91351 47263 23631 11 815 05907 33618 66809 83404 91702 16406 08203 54101 27050 25 125 5625 78125 72,057,594,037,927,936 144,115,188,075,855,872 288,230,376,151,711,7l14 576,460,752,303,423,488 56 57 58 59 0.00000 0.00000 0.00000 0.00000 00000 00000 00000 00000 00000 0('1000 00000 00000 01387 00693 00346 00173 77878 88939 941169 lI7234 07814 03'107 51953 75976 45675 22837 611118 80709 52953 76476 88238 411119 95851 97925 lI8CJ62 24481 13525 56762 78381 39190 39062 69531 311765 67382 5 25 625 8125 l,152,921,504,606,8l16,976 2,305,843,009,213,693,952 4,611,686,018,427,387,904 9,223,372.036.85l1.775.808 60 61 62 63 0.00000 0.00000 0.00000 0.00000 00000 00000 00000 00000 00000 00000 00000 00000 00086 00043 00021 00010 73617 36808 681104 811202 37988 68 0 9 II 34497 17248 40354 20177 100 8 8 55044 72059 36029 68014 34007 622110 81120 90560 45280 69595 311797 17398 08699 33691 66845 83422 41711 40625 70312 5 85156 25 42578 125 18.446,744.073.709.551,616 64 0.00000 00000 00000 00005 42101 08624 27522 17003 726110 04349 70855 71289 0625 Numbering Systems and Conversion Tables D-7 Powers of Two Table n 18.446.744.073.709.551.616 36.893.488.147.419.103.232 73.786.976.294.838.206.464 147.573.952.589.676.412.928 64 65 66 67 295.147.905.179.352.825.856 590.295.810.358.705.651.712 1.180.591.620.717.411.303.424 2.361.183.241.434.822.606.848 68 69 70 71 4.722.366.482.869.645.213.696 9.444.732.965.739.290.427.392 18.889.465.931.478.580.854.784 37.778.931.862.957.161.709.568 72 73 74 75 75.557.863.725.914.323.419.136 151.115.727.451.828.646.838.272 302.231.454.903.657.293.676.544 604.462.909.807.314.587.353.088 76 77 78 79 1.208.925.819.614.629.174.706.176 2.417.851.639.229.258.349.412.352 4.835.703.278.458.516.698.824.704 9.671.406.556.917.033.397.649.408 80 81 82 83 19.342.813.113.834.066.795.298.816 38.685.626.227.668.133.590.597.632 77.371.252.455.336.267.181.195.264 154.742.504.910.672.534.362.390.528 84 85 86 87 309.485.009.821.345.068.724.781.056 618.970.019.642.690.137.449.562.112 1.237.940.039.285.380.274.899.124.224 2.475.880.078.570.760.549.798.248.448 88 89 90 91 4.951.760.157.141.521.099.596.496.896 9.903.520.314.283.042.199.192.993.792 19.807.040.628.566.084.398.385.987.584 39.614.081.257.132.168.796.771.975.168 92 93 94 95 79.228.162.514.264.337.593.543.950.336 158.456.325.028.528.675.187.087.900.672 316.912.650.057.057.350.374.175.801.344 633.825.300.114.114.700.748.351.602.688 96 97 98 99 1.267.650.600.228.229.401.496.703.205.376 5.070.602.400.912.917.605.986.812.821.504 10.141.204.801.825.835.211.973.625.643.008 100 101 102 103 20.282.409.603.651.670.423.947.251.286.016 40.564.819.207.303.340.847.894.502.572.032 81.129.638.414.606.681.695.789.005.144.064 162.259.276.829.213.363.391.578.010.288.128 104 105 106 107 324.518.553.658.426.726.783.156.020.576.256 649.037.107.316.853.453.566.312.041.152.512 1.298.074,214.633.706.907.132,624.082.305.024 2.596.148.429.267.413.814.265.248.164.610.048 108 109 110 111 5.192.296.858.534.827.628.530,496.329.220.096 10.384.593.717,069.655.257.060.992.658.440.192 20.769.187.434.139.310.514.121.985.316.880.384 41.538.374.868.278.621.028.243.970.633.760.768 112 113 114 115 83.076.749.736.557.242.056.487,941.267,521.536 166,153.499.473.114.484.112.975,882.535.043.072 664.613.997.892.457.936.451,903.530.140.172.J88 116 117 118 119 1.329.227.995.784.915.872.903,807,060.280.344.576 2.658,455.991.569.831.745.807.614.120.560.689.152 5.316.911.983,139,663.491.615.228,241.121,378.304 10.633.823.966.279.326.983.230.456.482.242.756.608 120 121 122 123 21.267.647.932.558.653.966.460.912,964.485.513.216 42.535.295.865.117.307.932.921.825.928.971,026.432 85.070.591.730.234.615.865.843.651,857.942.052.864 170.141,183.460.469.231,731,687,303,715,884,105,728 124 125 126 127 340.282.366.920.938.46~.463.374.607.431.768.211.456 128 2.535.301.200.456.458.802.993.406.41~.752 332.306.998~946.228.968.225,951,765.070.086.144 D-8 GA34-0022 Appendix E. Character Codes Decimal Hex Binary EBCDIC ASCll 0 1 2 3 4 5 6 7 8 9 10 11 12 00000000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 00010000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 00100000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0011 0000 0001 0010 0011 0100 0101 0110 NUL SOH STX ETX PF HT LC DEL 14 15 16 17 11 18 19 20 21 22 23 24 25 26 12 27 o 04 05 06 07 08 09 OA OB OC OD OE OF 10 13 c 00 01 02 03 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 13 14 15 16 17 18 19 1A 1B 1C 1D IE IF 20 21 22 -23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 RLF SMM VT FF CR SO SI DLE DC1 DC2 TM RES NL BS IL CAN EM CC CUI IFS IGS IRS IUS DS SOS FS BYP LF ETB ESC NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US space ! " # $ % Eight bit data interchange NUL NUL ENQ ACK BFL P (even parity) P (odd parity) a (even parity) o (odd parity) H (even parity) H (odd parity) ( (even parity) ( (odd parity) SYN PN RS UC space 1,] 2 2 3 4 3 5 5 7 6 7 6 8 8 4 9 0 0 z @ (EOA) @ upper case upper case (EOA),9 X 8 /\ © (EOT) EOT D (even parity) D (odd parity) S (even parity) S (odd parity) , + , T - 4 / 0 1 2 3 4 5 6 space 1 space & * PTTC/ Correspondence @ ( ) SM CU2 PTTC/EBCD form feed form feed © @ t / x s t n u u v e d w k x c y 1 h z (EOT) L , Character Codes E-1 E-2 Decimal Hex Binary 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 0011 0111 EOT 1000 1001 1010 1011 CU3 1100 DC4 1101 NAK 1110 1111 SUB 01000000 space 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 < 1101 ( 1110 + 1111 J 0101 0000 & 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 ! 1011 $ 1100 * 1101 ) 1110 ; 1111 --, 01100000 0001 / 0010 0011 0100 0101 0110 0111 1000 1001 1010 II 1011 , 1100 % 1101 1110 > 1111 ? 0111 0000 0001 0010 0011 0100 GA34-0022 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 SA 5B 5C 5D 5E SF 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 EBCDIC ASCII ¢ Eight bit data interchange 7 8 9 : ; \ (even parity) \ (odd parity) < (even parity) < (odd parity) < = > PTTC/EBCD PTTC/ Correspondence ® b (SOA), comma index ® index (EOB) ? @ N EOA B (even parity) B (odd parity) " (even parity) " (odd parity) A B C D E F G H I J - ,- i m k 1 v m n K L M N 0 2 P Q line feed line feed ! , r R R S T U V W a i p a q r a s t , J * $ w CRLF CRLF backspace idle backspace idle & a j g X y Z [ Z (even parity) Z (odd parity) : (even parity) : (odd parity) \ J A - ACK a b c d e f F b & c d g h i j k 1 m n a V (even parity) V (odd parity) 6 (even parity) 6 (odd parity) . P q r s t shift out N (even parity) N (odd parity) . (even parity) f P e g q comma h / i y f ( ' c c o Decimal Hex Binary 117 118 119 01110101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 10000000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1001 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1010 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1011 0000 0001 0010 75 76 77 11C 7~ 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F AO Al A2 A3 A4 AS A6 A7 A8 A9 AA AB AC AD AE AF BO B1 B2 EBCDIC ASCII Eight bit data interchange PTTC/EBCD . (odd parity) u v w ® ,period PTTC/ Correspondence - .. : # @ , y z { t } > I = ,... " DEL a b c d e horiz tab tab lower case lower case delete SaM A (even parity) A (odd parity) ! (even parity) ! (odd parity) space space = ±, [ < @ X-ON ; : % Q % & f g h i # ~ 1 > * horiz tab horiz tab * $ j k I I ( ) ) ) m n a p q r @ Y (even parity) Y (odd parity) 9 (even parity) 9 (odd parity) upper case © ,.." (EOA)," ~ WRU (even) WRU (odd) (EOn Z ( upper case © (EaT) T s t u v w x y z E ? X % S T N U U V E D W K X C U (even parity) U (odd parity) 5 (even parity) 5 (odd parity) return M (even parity) Y L Z H Character Codes E-3 E-4 Eight bit data interchange Decimal Hex Binary 179 180 B3 B4 1011 0011 0100 M (odd parity) - (even parity) 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 B5 B6 B7 B8 B9 BA BB BC BD BE BF CO C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF DO Dl D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF EO E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 11000000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1101 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 11100000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 - (odd parity) GA34-0022 EBCDIC ASCII { A B C D E F G H I PTTC/ Correspondence ® B (SO A), I ] index = ® (EOB) EOM (even) EOM (odd) ® ,- C J # K index M L V M N " R 0 I P A Q R 0 ! W [ CRLF CRLF ; backspace idle backspace idle X-OFF S (even parity) S (odd parity) 3 (even parity) 3 (odd parity) J PTTC/EBCD } J K L M N vertical tab K (even parity) K (odd parity) + (even parity) + (odd parity) S 0 P Q R PAD \ S T U V bell G (even parity) G (odd parity) , (even parity) , (odd parity) + J A G B + C D F P W X y ,, f Y Z W E 7 F G rf Q comma Decimal Hex Binary EBCDIC ASCII 240 241 242 1111 0000 0001 0010 0 1 2 FO F1 F2 243 1'3 UUl! j 244 245 246 247 248 249 250 251 252 253 254 255 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4 5 6 7 8 9 LVM Eight bit data interchange PTTC/EBCD PTTC/ Correspondence shift in (even) shift in (odd) H ? U i -x- / (even parity) (odd parity) ? (even parity) ? (odd parity) -<= ®,--, - horiz tab tab lower case lower case -<= delete rub out delete c o Character Codes E-5 E-6 GA34-0022 Appendix F. Carry and Overflow Indicators This appendix explains the meaning of the carry and overflow indicators for signed and unsigned numbers. Examples for setting these indicators are also provided. c SIGNED NUMBERS ADD OPERATION-All possible results (l6-bit example) Result value Indicators Overflow Carry Hexadecimal Decimal Signed Numbers 1 1 0000 -65536 F or signed addition and subtraction, the overflow indicator signals a result that exceeds the representation capability of the system for the result operand size. When overflow is indicated, the carry indicator and the resulting operand together form a valid result with the carry indicator being the most significant bit. For addition, the carry indicator is the sign (high-order bit) of this result. For subtraction, the carry indicator is the complement of the sign (highorder bit) of the result. A negative result appears in two's complement form. When no overflow is indicated, the carry indicator provides no information about the result. Figure F-l shows how the carry and overflow indicators are set for an add operation when using 16-bit operands. Figure F-2 provides the same information for a subtract operation. t 1 } 7FFF --- -f--8~OO (Note 2) (See Note I) -32769 -32768 . ____l_EEFJ: FFFF -----r --0000- 16-bit representable range -2 -1 o (Note 2) ____l_}!:~~ 8000 1 l +32767 +32768 } FFFE (See Note 1) +65534 Notes. 1. When overflow occurs, the carry indicator and the result together form a valid 17-bit signed number, of which the carry is the sign, and the result is the magnitude. A negative result is in two's complement from. When no overflow occurs, no useful information is provided by the carry indicator. 2. The carry indicator may be on or off depending on the operands. Figure F-I. All possible results of an add opera tion regarding the operands as signed 16-bit numbers o Carry and Overflow Indicators F-l Unsigned Numbers SIGNED NUMBERS SUBTRACT OPERATION-All possible results (l6-bit example) Result value Indicators Overflow Carry Hexadecimal Decimal 0001 -65535 I 1 1 1. } (See Note 1) 7FFF ---t---~~~~ -32769 -32768 -32767 (Note 2) __ -'___ FFFF 0000 - - -,- - - 0001 (Note 2) 1 ~ __ J___ 1 ! 1 7FFF 8000 -1 o 16-bit representable range +1 +32767 +32768 } (See Note 1) FFFF +65535 Notes. 1. When overflow occurs, the carry indicator and the result form a valid 17-bit signed number, of which the carry is the complement of the correct sign, and the result is the magnitude. A negative result is in two's complement form. When no overflow occurs, no useful information is provided by the carry indicator. 2. The carry indicator may be on or off depending on the operands. Figure F-2. All possible results of a subtract operation regarding the operands as signed 16-bit numbers F-2 GA34-0022 For unsigned addition and subtraction, the carry indicator signals that: On an add instruction, a carry out of the high-order bit position has occurred (result exceeds result operand size). The carry indicator and the resulting operand together form a valid result of which the carry indicator is the most significant bit. 2. On a subtract operation, a borrow beyond the highorder bit position has occurred. A borrow during a subtract operation is defined as either of the following: -No carry is generated out of the high-order bit position when a two's complement of the subtrahend and add is performed to accomplish the subtract operation. - The most significant digit of the minuend must be made larger to generate a difference of zero or one when subtracting the most significant digit of the subtrahend; for example, 1 subtracted from O. When a borrow is signalled on a subtract operation, the result is in two's complement form. The overflow indicator provides no useful information about unsigned operations. Figure F -3 shows ho~ the carry and overflow indicators are set for an add operation when using 16-bit operands. Figure F 4 provides the same information for a subtract operation. I'iI · , I' ·~ C " UNSIGNED NUMBERS UNSIGNED NUMBERS ADD OPERATION-All possible results (16-bit example) Overflow Carry (Note 2) 1 I SUBTRACf OPERATION-All possible results (16-bit example) Indicators Result value Indicators Hexadecimal Decimal Overflow 0000 o (Note 2) 7FFF 8000 32767 32768 FFFE FFFF 0000 65534 65535 65536 7FFF 8000 FFFE 98303 98304 16-bit representable range 17-bh range using carry bit (See Note 1) 131070 Carry Result value Hexadecimal Decimal 0001 -65535 7FFF 8000 8001 -32769 -32768 -32767 FFFF 0000 0001 -1 7FFF 8000 +32767 +32768 FFFF +65535 17-bit negative range (See Note 1) o +l 16-bit representable range Notes. 1. With the carry indicator on, the result and carry form a valid 17-bit unsigned number of which the carry is the most significant bit. 2. The overflow indicator may be set; however, it provides no useful information. c Figure F-3. All possible results of an add operation regarding the operands as unsigned 16-bit numbers Notes. 1. With carry (borrow) on, the result and carry indicator form a valid 17-bit negative number of which the carry is the sign and result is the magnitude in normal two's complement form. 2. The overflow indicator may be set; however, it provides no useful information. Figure F-4. All possible results of a subtract operation regarding the operands as unsigned 16-bit numbers o Carry and Overflow Indicators F-3 Carry Indicator Setting Subtract Operation Examples The carry indicator is used to signal overflow of the result when operands are presented as (unsigned) numbers. (The machine does not regard the numbers as either signed or unsigned, but performs the designated operation (add or subtract) on the values presented. The programmer must interpret the condition of the result for the number representation involved.) The machine detects the carry condition during the operation in two ways: The processor performs subtraction by using the complement addition method. The second operand is complemented (two's complement) then an add operation is performed. This is actually a three-way add operation between the minuend, the subtrahend (one's complement), and a constant of one. To provide the correct carry (borrow) indication for the subtraction, the carry result of the complement add operation must be inverted to determine the carry indicator setting. The following examples use a four-bit operand with an unsigned number range of 0 to 15. 1. Add operation - when a carry out of the high-order bit position of the result operand occurs. Subtract operation - when a borrow beyond the highorder bit position of the result operand occurs. 2. Desired operation: Machine operation: Add Operation Examples A four-bit operand size is used in the following examples. Note that the unsigned number range for this operand is 0 to 15. No other unsigned number values may be represented for this size operand. • Addition (carry indicator is not set) Desired operation: Machine operation: 6 + 9 = 15 Augend 0110 Addend 1001 Result 1111 High-order bit carry = 0 The result fits as an unsigned number. The carry indicator is not set (C=O). • Addition (carry indicator is set) Desired operation: Machine operation: 15 + 1 = Augend Addend Result 16 1111 0001 0000 High-order bit carry = 1 The result does not fit as an unsigned number. The carry indicator is set (C=l). • Addition (carry indicator is set) Desired operation: Machine operation: 15 + 15 = 30 Augend 1111 Addend 1111 Result 1110 High-order bit carry = 1 Result does not fit as an unsigned number. The carry indicator is set (C=l). Note. The result of adding the two largest numbers can be contained in the operand size and the carry indicator. The carry indicator represents the most significant bit. F-4 GA34-0022 • Subtract (carry indicator is not set) 15 - 1 = 14 Minuend Subtrahend Constant Result 1111 111 0 one's complement 1 for two's complement 1110 High-order bit carry = 1 invert for carry indicator The result fits as an unsigned number. The carry indicator is not set (C=O). Note. The carry indicator setting (C=O) for this subtract operation was determined by inverting the complement-add carry. • Subtract (carry indicator is not set) Desired operation: Machine operation: 15 - 15 = 0 Minuend 1111 Subtrahend 0000 one's complement Constant 1 for two's complement Result 0000 High-order bit carry = 1 invert for carry indicator The result fits as an unsigned number. The carry indicator is not set (C=O). • Subtract (carry indicator is set) The following two examples show the case of a negative result (subtrahend greater than minuend). This negative result cannot be represented in the operand width because all operand bits are used to represent the unsigned number. To flag this condition the carry indicator is set. t \. '" o Overflow Indicator Setting Example 1: Desired operation: Machine operation: 0-1 = -1 Minuend 0000 Subtrahend 1110 one's complement Constant 1 for two's complement Result 1111 invert for carry High-order bit carry = 0 indicator The result does not fit as an unsigned number. The carry indicator is set (C=l). Example 2: 0- 15 = -15 Minuend 0000 Subtrahend 0000 one's complement Constant 1 for two's complement 0001 Result High-order bit carry = 0 invert for carry indicator The result does not fit as an unsigned number. The carry indicator is set (C=l). Desired operation: Machine operation: The overflow indicator is used to signal overflow of the result when the operands are presented as signed numbers. The machine does not regard the numbers as either signed or unsigned, but performs the designated onpr~ti()f1 - r - - -_.-" _. (~rlrl ,-- _. - or 'mhtr~rt).I on thp. V~l11P.C;: nrec;:enten ..l. The programmer must interpret the condition of the result for the number representation involved. The machine detects this condition by inspection of any carry into and out of the high-order bit (sign position) of the result operand during the operation. The overflow indicator is set (0 = 1) for the two cases where the carries disagree: 1. 2. A carry into, but no carry out of the sign position. No carry into, but a carry out of the sign position. The overflow indicator is not set (0 = 0) for the remaining two cases where the carries agree: 1. 2. A carry into and out of the sign position. No carry into and no carry out of the sign position. Note. When a negative result occurs on a subtract operation, the values may be useful to the programmer. The carry indicator and the result form a signed number. The carry indicator is the sign and the result is the number in two's complement form (see Figure F4). c o Carry and Overflow Indicators F-5 • Subtraction (overflow indicator is not set) Examples +7 - (+2) = +5 A four-bit operand size is used in the following examples. Note that the signed number range for a four-bit operand is -8 to +7. No other signed number values may be represented. Desired operation: Machine operation: • Addition (overflow indicator is not set) Carry into sign position = 1 carries agree Carry out of sign position = 1 The result fits as a signed number. The overflow indicator is not set (0 = 0). +5 + (+2) = +7 Augend 0101 Addend 0010 Result 0111 Carry into sign position = 0 Carry out of sign position = 0 carries agree The result fits as a signed number. The overflow indicator is not set (0 = 0). Desired operation: Machine operation: Desired operation: Machine operation: 1100 two's complement 1100 two's complement 1000 two's complement Carry into sign position = 1 carries agree Carry out of sign position = 1 The result fits as a signed number. The overflow indicator is not set (0 = 0). • Addition (overflow indicator is set) Desired operation: +4 + (+4) = +8 Machine operation: Augend Addend Result Carry into sign position = 1 Carry out of sign position = 0 The result does not fit as a signed indicator is set (0 = 1). Desired operation: Machine operation: -4 + (-5) Augend Addend Result Carry into sign position = 0 Carry out of sign position = 1 The result does not fit as a signed indicator is set (0 = 1). F-6 GA34-0022 Result Desired operation: 0100 0100 1000 carries disagree number. The overflow = -9 1100 two's complement 1011 two's complement 0111 carries disagree number. The overflow 0101 +5 - (-1) = +6 Note. -1 is equal to 1111 Machine operation: -4+(-4)=-8 Augend Addend Result Minuend 0111 Subtrahend 1101 one's complement Constant 1 for two's complement Minuend Subtrahend Constant Result 0101 0000 one's complement 1 for two's complement 0110 Carry into sign position = 0 Carry out of sign position = 0 carries agree The result fits as a signed number. The overflow indicator is not set (0 = 0). • Subtraction (overflow indicator is set). Desired operation: +7 - (-2) = +9 Note. -2 is equal to 1110 Minuend 0111 Subtrahend 0001 one's complement 1 for two's complement Constant Result 1001 Carry into sign position = 1 Carry out of sign position = 0 carries disagree The result does not fit as a signed number. The overflow indicator is set (0 = 1). Machine operation: Desired operation: Machine operation: -3-(+6)=-9 Minuend 1101 two's complement Subtrahend 1001 one's complement Constant 1 for two's complement Result 0111 Carry into sign position = 0 carries disagree Carry out of sign position = 1 The result does not fit as a signed number. The overflow indicator is set (0 = 1). Appendix G. Reference Infonnation o This appendix contains the following reference information: • • • • • Condition codes General registers Interrupt status byte Level status register (LSR) Processor status word (PSW) Condition Codes I/O Instruction Condition Codes These codes are reported during execution of an Operate I/O instruction. Condition code (CC) value 0 1 c 2 3 4 5 6 7 LSR position Even Carry 0 0 0 0 1 0 1 0 0 0 1 1 Overflow Reported by Meaning 0 1 0 1 0 1 0 1 channel device device chan/dev device chan/dev controller chan/dev Device not attached Busy Busy after reset Command reject Intervention required Interface data check Controller busy Satisfactory Interrupt Condition Codes These condition codes are reported by the device or controller during priority interrupt acceptance. Condition code (CC) value LSR position Even Carry Overflow 0 0 0 0 0 0 2 3 4 0 0 1 1 0 0 1 0 1 0 5 6 7 1 0 Reported by controller device device device device device device device Meaning Controller end Program controlled interrupt (PCI) Exception Device end Attention A tten tion and PCI Attention and exception Attention and device end o Reference Information G-l General Registers R or RB * field value Register selected Register 0 000 Register 1 001 Register 2 010 Register 3 011 Register 4 100 Register 5 101 Register 6 110 Register 7 111 *The RB field sometimes contains only the two low-order bits. In this case, registers 4 through 7 cannot be specified. Interrupt Status Byte (ISB) DPCDevices Bits 0 1 2 3 4 5 6 7 Contents Device status available Delayed command reject Device dependent Device dependent Device dependent Device dependent Device dependent Device dependent Cycle Steal Devices Bits 0 1 2 3 4 5 6 7 G-2 Contents Device status available Delayed command reject Incorrect length record DCB specification check Storage data check Invalid storage address (not used, always zero) Interface data check GA34-0022 Level Status Register (LSR) Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Contents Even indicator Carry indicator Overflow indicator Negative result indicator Zero result indicator (not used, always zero) (not used, always zero) (not used, always zero) Supervisor state In process Trace Summary mask (not used, always zero) (not used, always zero) (not used, always zero) (not used, always zero) (; Processor Status Word (PSW) Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Contents Specification check Invalid storage address Privilege violate (not used, always zero) Invalid function (not used, always zero) Stack exception (not used, always zero) Storage parity check (not used, always zero) CPU control check I/O check Sequence indicator Auto-IPL (not used, always zero) Power/thermal warning f l " Index o ,~~~-...~ V ... "" ... "-...."j,l./Jt.4.lU.l" 1...._", .... ,."h c o add byte immediate (ABI) instruction 6-3 add carry register (ACY) instruction 6-4 add double word (AD) instruction register/storage format 6-5 storage/storage format 6-5 add word (A W) instruction register/register 6-6 register/storage format 6-6 storage/storage format 6-7 storage to register long format 6-7 add word immediate (AWl) instruction register immediate long format 6-9 storage immediate format 6-9 add word with carry (A WCY) instruction 6-8 address generation, effective 2-13 address mode (AM) 2-14 assembler syntax, conversion to A-2 AKR key, console 5-10 alternate IPL source, console switch 5-2 ALU (see arithmetic and logic unit) AM (see address mode) and word immediate (NWI) instruction 6-57 arithmetic and logic unit (ALV) 2-3 assembler syntax, summary of C-l attention and device end condition code 4-20 attention and exception condition code 4-20 attention and PCI condition code 4-20 attention condition code 4-20 auto IPL, bit in PSW 3-10 auto IPL mode, console switch 5-2 base register (RB) used for effective address generation 2-13,2-14 basic console 5-2 branch and link (BAL) instruction 6-10 branch and link external (BALX) instruction 6-10 branch and link short (BALS) instruction 6-11 branch external (BX) instruction 6-10 branch if mixed (BMIX) instruction 6-12 branch if negative (BN) instruction 6-12 branch if not off (BNOFF) instruction 6-14 branch if not on (BNON) instruction 6-14 branch if off (BOFF) instruction 6-12 branch if on (BON) instruction 6-12 branch indexed short (BXS) instruction 6-17 branch/jump instructions branch and link (BAL) 6-10 branch and link external (BALX) branch and link short (BALS) 6-11 branch indexed short (BXS) 6-17 branch on condition (BC) 6-12 branch if mixed (BMIX) branch if negative (BN) branch if off (BOFF) .. ;_..,+_~ '""+; . . . . _.., ... ..I.J.o,)\...I. ..... ""'-.1.V4J.0 (,..,." ....... ;_ .... ,..,...:1\ \ ...... ....., ..... \.. ... ..1.& ............. , branch on condition (BC) (continued) branch if on (BON) branch on arithmetically less than (BL T) branch on arithmetically less than or equal (BLE) branch on carry (BCY) branch on equal (BE) branch on even (BEV) branch on logically less than (BLL T) branch on logically less than or equal (BLLE) branch on positive (BP) branch on zero (BZ) branch on condition code (BCC) 6-13 branch on not error (BNER) branch on not condition (BNC) 6-14 branch if not off (BNOFF) branch if not on (BNON) branch on arithmetically greater than (BGT) branch on arithmetically greater than or equal (BGE) branch on logically greater than (BLGT) branch on logically greater than or equal (BLGE) branch on no carry (BNCY) branch on not equal (BNE) branch on not even (BNEV) branch on not mixed (BNMIX) branch on not negative (BNN) branch on not positive (BNP) branch on not zero (BNZ) branch on not condition code (BNCC) 6-15 branch on error (BER) branch on not overflow (BNOV) 6-16 branch on overflow (BOV) 6-16 branch unconditional (B) 6-10 branch external (BX) jump and link (JAL) 6-38 jump on condition (JC) 6-39 jump if mixed (JMIX) jump if off (JOFF) jump if on (JON) jump on arithmetically less than (JTL) jump on arithmetically less than or equal (JLE) jump on carry (JCY) jump on equal (JE) jump on even (JEV) jump on logically less than (JLLT) jump on logically less than or equal (JLLE) jump on negative (IN) jump on positive (JP) jump on zero (JZ) jump on count (JCT) 6-40 jump on not condition (JNC) 6-41 jump if not off (JNOFF) jump if not on (JNON) jump on arithmetically greater than (JGT) jump on arithmetically greater than or equal (JGE) jump on logically greater than (JLGT) Index X-I branch/jump instructions (continued) jump on not condition (JNC) (continued) jump on logically greater than or equal (JLGE) jump on no carry (JNCY) jump on not equal (JNE) jump on not even (JNEV) jump on not mixed (JNMIX) jump on not negative (JNN) jump on not positive (JNP) jump on not zero (JNZ) jump unconditional (J) 6-38 no operation (NOP) 6-57 branch on arithmetically greater than (BGT) instruction 6-14 branch on arithmetically greater than or equal (BGE) instruction 6-14 branch on arithmetically less than (BL T) instruca tion 6-12 branch on arithmetically less than or equal (BLE) instruction 6-12 branch on carry (BCY) instruction 6-12 branch on condition (BC) instruction 6-12 branch on condition code (BCC) instruction 6-13 branch on equal (BE) instruction 6-12 branch on error (BER) instruction 6-15 branch on even (BEV) instruction 6-12 branch on logically greater than (BLGT) instruction 6-14 branch on logically greater than or equal (BLGE) instruction 6-14 branch on logically less than (BLLT) instruction 6-12 branch on logically less than or equal (BLLE) instruction 6-12 branch on no carry (BNCY) instruction 6-14 branch on not condition (BNC) instruction 6-14 branch on not condition code (BNCC) instruction 6-15 branch on not eq ual (BNE) instruction 6-14 branch on not error (BNER) instruction 6-13 branch on not even (BNEV) instruction 6-14 branch on not mixed (BNMIX) instruction 6-14 branch on not negative (BNN) instruction 6-14 branch on not overflow (BNOV) instruction 6-16 branch on not positive (BNP) instruction 6-14 branch on not zero (BNZ) instruction 6-14 branch on overflow (BOV) instruction 6-16 branch on positive (BP) instruction 6-12 branch on zero (BZ) instruction 6-12 branch unconditional (B) instruction 6-10 burst mode 4-13 busy, condition code 4-19 busy after reset, condition code 4-19 carry indicator defined 2-8 how used 2-8 setting F-4, 2-1 0 example, add operation F-1, F-3 example, subtract operation F-2, F4 chaining 4-5, 4-13 chaining flag bit in DCB 4-5,4-13 character codes E-1 check indicator 5-4 check restart key, console 5-7 X-2 GA34-0022 ClAR (see current instruction address register) ClAR key, console 5-9 class interrupts 3-5 console 3-8 execution of 3-5 machine check 3-6 power/thermal warning 3-7 priority of 3-5 program check 3-6 soft exception trap 3-9 summary of 3-8 supervisor call 3-7 trace 3-7 codes, character E-1 command field, IDCB 4-3 command reject, condition code 4-19 commands, I/O, general communications features, description 1-6 compare byte (CB) instruction register/storage format 6-18 storage/ storage format 6-18 compare byte field equal and decrement (CFED) instruction 6-21 compare byte field equal and increment (CFEN) instruction 6-21 compare byte field not equal and decrement (CFNED) instruction 6-22 compare byte field not equal and increment (CFNEN) instruction 6-22 compare byte immediate (CBI) instruction 6-19 compare double word (CD) instruction register/storage format 6-20 storage/storage format 6-20 compare operation example 2-8 indicator settings 2-8 testing results 2-10 compare word (CW) instruction register/register format 6-28 register/storage format 6-28 storage/storage format 6-28 compare word immediate (CWI) instruction register immediate long format 6-29 storage immediate format 6-29 compatibility 6-2 no operation 6-2 program check 6-2 soft exception trap 6-2 complement register (CMR) instruction 6-23 condition codes, defined interrupt 4-19 10 instruction 4-19 console 5-1 basic 5-2 indicators 5-2 keys and switches 5-2 programmer 5-3 combination keys/indicators 5-5 display 5-3 displaying main storage 5-12 displaying registers 5-13 indicators 54 ( \. I' o device mask (I -bit) 3-13, 4-7 device not attached, condition code device options, cycle steal 4-13 burst mode 4-13 chaining 4-1 3 program control interrupt (PCI) suppress exception (SE) 4-13 console (continued) programmer (continued) keys and switches 5-8 storing into main storage 5-12 storing into registers 5-13 console data buffer 2-6,5-3 console interrupt 3-8 ron<;nlf' intf'rrllnt kf'V rlevi~e '\-R control command 4-7 controller busy condition code 4-19 controller end condition code 4-19 conversion tables, numbering systems and 0-1 copy console data buffer (CPCON) instruction 6-24 copy current level (CPCL) instructiorr 6-23 copy in-process flags (CPIPF) instruction 6-25 copy interrupt mask register (CPIMR) instruction 6 24 copy level block (CPLB) instruction 6-26 copy level status register (CPLSR) instruction 6-27 copy processor status and reset (CPPSR) instruction 6-27 count residual byte 4-12 restrictions for the start cycle steal status operation 4-12 word in DCB 4-6 CPU control check, bit in PSW 3-10 current-instruction address register (CIAR) 2-6 cycle steal description 4-10 device options 4-13 interrupt status byte (ISB) 4-20 start cycle status operation 4-12 start operation 4-10 status words 4-13 termination conditions 4-15 cycle steal, typical operation 4-10 o data buffer key, console 5-8 data display indicators 5-4 data entry keys (O-F), console 5-11 data stacking 2-24 example, allocating fixed storage areas 2-26 pop operation 2-25 push operation 2-25 DCB (see device control block) DCB specification check status bit 4-21 delayed command reject status bit 4-20 device address field, IDCB 4-3 device control block (DCB) 4-5 control word 4-5 coun t word 4-6 data address word 4-6 device parameter word 3 4-5 device parameter word 4 4-6 device parameter word 5 4-6 device parameter words 1- 2 4-5 for start cycle steal status command, summary of specification check status bit 4-21 device cycle-steal-status word 1 4-13 device dependent <;tatus available statu" hit 4-20 device dependent status words 4-13 device end condition code 4-19 device 10 word 4-6 reset ~omm;mrl 4-19 4-13 4-R diagnose (DIAG) instruction 6-32 diagnostic mode, console switch 5-2 direct program control (DPC) operation 4-9 disable (DIS) instruction 6-33 displaying main storage 5-12 displaying registers 5 -13 divide byte (DB) instruction 6-30 divide double word (DO) instruction 6-31 divide word (OW) instruction 6-34 DPC (direct program control) operation 4-9 EA (see effective address) effective address 2-13 effective address generation 2-13 base register storage address 2-18 base register word displacement 2-14 base register word displacement short 2-13 five-bit address argument 2-18 four-bit address argument 2-14 address mode (AM) 2-14 enable (EN) instruction 6-35 end of chain bit 4-14 EOC (see end of chain bit) error conditions recovery from 3-8 that cause class interrupts 3-5 even indicator 2-8 exception condition code 4-19 exception conditions, during instruction execution program check basic instructions 6-1 soft exception trap basic instructions 6-1 exceptions, suppression of 4-14 exclusive OR byte (XB) instruction 6-97 exclusive OR double word (XD) instruction 6-98 exclusive OR word (XW) instruction register/register format 6-99 register/storage format 6-99 storage to register long format 6-100 exclusive OR word immediate (XWI) instruction 6-100 fill byte field and decrement (FFD) instruction fill byte field and increment (FFN) instruction 4-12 general registers 6-36 6-36 G-2, 2-6 halt I/O command 4-8 high limit address (HLA) 2-24 HLA (see high limit address) Index X-3 I-bit, device mask 3-13 I-bit (device mask), field in IDCB 4-7 I/O check, bit in PSW 3-10 I/O commands, general control 4-7 device reset 4-8 halt I/O 4-8 prepare 4-7 read 4-6 read ID 4-6 read status 4-7 start 4-8 start cycle steal status 4-8 summary chart 4-4 write 4-7 I/O condition codes and status information, general 4-15 I/O status information 4-20 interrupt status byte (IS B) 4-20 interrupt condition codes 4-19 interrupt information byte (lIB) 3-3 interrupt status byte (ISB) 4-20 10 instruction condition codes 4-19 summary of 4-19 I/O interrupts 3-3 prepare I/O device for 3-3 present and accept 3-3 IAR (see instruction address register) IAR key, console 5-10 IBM 4953 processor 1-3 ID word device 4-6 interrupt 3-3,4-20 IDCB (immediate device control block) 4-3 lIB (see interrupt information byte) ILR (see incorrect length record) immediate data field, IDCB 4-3 immediate device control block (I DC B) 4-3 in-process bit 2-11 effect on program controlled level switching 3-10 incorrect length record (ILR) status bit 4-21 suppression of reporting 4-14 indicator bits in LSR 2-7 indicators arithmetic 2-7 basic console 5-2 programmer console 5-4 sequence 3-10 indicators, add and subtract operations (carry and overflow) F-l,2-8 signed numbers F-l add operation F-l subtract operation F-2 unsigned numbers F-2 add operation F-3 subtract operation F-3 indicators, compare operations 2-8 indicators, condition code for I/O operations 2-8 indicators, multiple-word operands 2-9 indicators, result (even, negative, and zero) 2-8 indicators, shift operations (carry and overflow) 2-8 indicators, testing with branch and jump instructions 2-10 X-4 GA34-0022 indirect address 2-16 inhibit trace (IT) bit effect on SELB instruction 6-75 how used, programming note 3-7 initial program load (IPL) 2-22 au to IPL, bit in PSW 3-12 auto IPL mode, console switch 5-2 source switch, console 5-2 input flag in DCB 4-5 input/output (see also I/O) commands (see I/O commands) condition codes and status information 4-15 interrupt status byte (ISB) 4-20 operate I/O (10) instruction 4-2,6-37 input/output operations 4-1 instruct step key/indicator 5-6 instruction exception conditions 6-1 formats 2-11 index of X-I0 names 2-13 one word 2-11 summary of B-1 two word 2-12 variable length 2-12,2-19 index of, by name X-13 privileged 2-21 termination or suppression 6-2 instruction address register (lAR) 2-6 instruction execution times A-I additional time for adJressing mode A-2 instruction formats B-1, 2-11 interchange registers (IR) instruction 6-37 interface da ta check, condition code 4-19 interface data check status bit 4-21 interrupt automatic branching 3-2 class 3-5 I/O 3-3 masking facilities 3-13 device mask (I-bit) 3-13 mask register, in terru pt level 3-13 summary mask 3-13 priority scheme 3-2 interrupt ID word 3-3,4-20 interrupt information byte (lIB) 3-3 interrupt level mask register 3-13 interrupt scheme 3-1 interrupt status byte (ISB) 4-20 defined 4-20 for cycle stealing devices 4-20 for devices that do not cycle steal 4-20 interrupts and level switching, introduction 3-1 intervention required, condition code 4-19 invalid function, bit in PSW 3-9 invalid function, program check condition 6-1 invalid function, soft exception trap condition 6-1 invalid storage address 6-1 invalid storage address, bit in PSW 3-9 invalid storage address status bit 4-21 invert register (VR) instruction 6-97 IO (operate I/O) instruction 4-2,6-37. IPL (see initial program load) o LSB (see level status block) LSB pointer, class interrupts 3-5 LSR (see level status register) LSR key, console 5-10 IPL source switch 5-2 ISB (see interrupt status byte) IT bit (see inihibit trace bit) jump and link (J AL) instruction 6-38 jump if mixed (JMIX) instruction 6-39 c o jump if not on (JNON) instruction 6-41 jump if off (JOFF) instruction 6-39 jump if on (JON) instruction 6-39 jump on arithmetically greater than (JGT) instruction 6-41 jump on arithmetically greater than or equal (JGE) instructio 6-41 jump on arithmetically less than (JLT) instruction 6-39 jump on arithmetically less than or equal (JLE) instruction 6-39 jump on. carry (JCY) instruction 6-39 jump on condition (JC) instruction 6-39 jump on count (JCT) instruction 6-40 jump on equal (JE) instruction 6-39 jump on even (JEV) instruction 6-39 jump on logically greater than (JLGT) instruction 6-41 jump on logically greater than or equal (JLGE) instruction 6-41 jump on logically less than (JLLT) instruction 6-39 jump on logically less than or equal (JLLE) instruction 6-39 jump on negative (IN) instruction 6-39 jump on no carry (JNCY) instruction 6-41 jump on not condition (JNC) instruction 6-41 jump on not equal (JNE) instruction 6-41 jump on not even (JNEV) instruction 6-41 jump on not mixed (JNMIX) instruction 6-41 jump on not negative (JNN) instruction 6-41 jump on not positive (JNP) instruction 6-41 jump on not zero (JNZ) instruction 6-41 jump on positive (JP) instruction 6-39 jump on zero (JZ) instruction 6-39 jump unconditional (J) instruction 6-38 level exit (LEX) instruction 6-41 level status block (LSB) 2-6 level status register (LSR) 2-6, 6-2 level switching priority interrupt 3-3 program controlled 3-10 level 0 key/indicator 5-5 level 1 key/indicator 5-5 level 2 key/indicator 5-5 level 3 key/indicator 5-5 linkage stacking description 2-29 example, reenterable subroutine 2-30 . LLA (see low limit address) load indicator 5-2 load key 5-2 load mUltiple and branch (LMP) instruction load state 2-21 low limit address (LLA) 2-24 machine check conditions 3-6 mll~hine che~k interruot 3-6 main storage 2-1 address boundaries, instruction operand 2-3 addressing 2-3 main storage key, console 5-9 mask register 2-6, 3-13 mode switch 5-2 move address (MV A) instruction storage address to register format 6-45 storage immediate format 6-45 move byte (MVB) instruction register/storage format 6-46 storage/storage format 6-46 move byte and zero (MVBZ) instruction 6-47 move byte field and decrement (MVFD) instruction 6-50 move byte field and increment (MVFN) instruction 6-50 move byte immediate (MVBI) instruction 6-47 move double word (MVD) instruction register/storage format 6-48 storage/storage format 6-48 move double word and zero (MVDZ) instruction 6-49 move word (MVW) instruction register/register format 6-51 register/storage format 6-51 register to storage long format 6-51 storage/storage format 6-52 storage to register long format 6-52 move word and zero (MVWZ) instruction 6-55 move word immediate (MVWI) storage immediate format 6-53 storage to register format 6-53 move word short (MVWS) instruction register to storage format 6-54 storage to register format 6-54 multiple register/storage instructions load multiple and branch (LMB) 6-42 store multiple (STM) 6-88 multiply byte (MB) instruction 6-43 multiply double word (MD) instruction 6-44 multiply word (MW) instruction 6-56 NE bit (see no exception bit) negative indicator 2-8 no exception bit 4-14 no operation (NOP) instruction 6-57 normal mode, console switch 5-2 numbering representation 2-3 signed numbers 2-3 unsigned numbers 2-3 numbering systems and conversion tables D-1 6-42 Index X-5 op reg key, console 5-9 operate I/O (10) instruction 4-2,6-37 options, cycle steal device 4-13 OR byte (OB) instruction register/ storage format 6-58 storage/storage format 6-58 OR double word (OD) instruction register/storage format 6-59 storage/storage format 6-59 OR word (OW) instruction register/register format 6-60 register/ storage format 6-60 storage/storage format 6-61 storage to register long format 6-61 OR word immediate (OWl) instruction register immediate format 6-62 storage immediate format 6-62 overflow indicator how used 2-8 setting F-l processor status word (PSW) 2-6, 3-9 program check 3-6 program check conditions basic instructions 6-1 program check conditions in PSW 3-9 program check interrupt 3-6 program controlled interrupt condition code 4-19 program controlled level switching 3-10 program execution 2-11 jumping and branching 2-23 level switching and interrupt 2-23 sequential instructions 2-23 programmed controlled interrupt (PCI) 4-5,4-13 programmer console 5-3 PSW (see processor status word) PSW key, console 5-9 push byte (PSB) instruction 6-64 push double word (PSD) instruction 6-64 push operation 2-25 push word (PSW) instruction 6-65 parametric instructions diagnose (DIAG) 6-32 disable (DIS) 6-33 enable (EN) 6-35 level exit (LEX) 6-41 stop (STOP) 6-89 supervisor call (SYC) 6-89 PCI (see program controlled interrupt) pop byte (PB) instruction 6-63 pop doubleword (PD) instruction 6-63 pop operation 2-25 pop word (PW) instruction 6-65 power on indicator 5-2 power on/off switch 5-2 power-on reset, effects of 2-22 power/thermal warning, bit in PSW 3-10 power/thermal warning condition 3-7 power/thermal warning interrupt 3-7 prepare command 4-7 primary IPL source, console switch 5-2 privilege violate 6-1 privilege violate, bit in PSW 3-9 privileged instructions, list of 2-21 problem state 2-21 processing unit description 2-1 processor data flow 2-2 description 1-3 features communications 1-6 input/output units 1-6 optional 1-3 standard 1-3 introduction 1-1 models 1-4, 1-5 options miscellaneous 1-6 packaging and power 1-6 sensor input/output 1-6 processor, 4953 1-3 processor state control 2-20 RB (see base register) read command 4-6 read ID command 4-6 read status command 4-7 recovery from error conditions 3-8 reference information G-l condition codes G-l I/O instruction G-l interrupt G-1 general registers G-2 cycle steal devices G-2 DPC devices G-2 interrupt status byte (ISB) G-2 level status register (LSR) G-2 processor status word (PSW) G-2 register immediate instructions add byte immediate (ABI) 6-3 add word immediate (AWl) 6-9 AND word immediate (NWI) 6-57 compare byte immediate (CBI) 6-19 compare word immediate (CWI) 6-29 exclusive OR word immediate (XWI) 6-100 move byte immediate (MYBI) 6-47 OR word immediate (OWl) 6-62 reset bits word immediate (RBTWI) 6-70 subtract word immediate (SWI) 6-93 test word immediate (TWI) 6-96 register/register instructions add carry register (ACY) 6-4 add word (AW) 6-6 add word with carry (AWCY) 6-8 compare word (CW) 6-28 complement register (CMR) 6-23 copy level status register (CPLSR) 6-27 exclusive OR word (XW) 6-99 interchange registers (IR) 6-37 invert register (VR) 6-97 move word (MVW) 6-51 OR word (OW) 6-60 reset bits word (RBTW) 6-68 set indicators (SElND) 6-74 X-6 GA34-0022 register/ register instructions (con tinued) subtract carry indicator (SCY) 6-71 subtract word (SW) 6-90 subtract word with carry (SWCY) 6-92 register/ storage instructions add byte (A B) 6-3 add double word (AD) 6-5 ~rL.j t,.4 ....... '-"" c o ••• ~~'" {A 'U\ ~,'-'..<- ....... \." a. •• J C. C. compare byte (CB) 6-18 compare double word (CD) 6-20 compare word (CW) 6-28 divide byte (DB) 6-30 divide double word (DD) 6-31 divide word (DW) 6-34 exclusive OR byte (XB) 6-97 exclusive OR double word (XD) 6-98 exclusive OR word (XW) 6-99 move address (MV A) 6-45 move byte (MVB) 6-46 move byte and zero (MVBZ) 6-47 move double word (MVD) 6-48 move double word and zero (MVDZ) 6-49 move word (MVW) 6-51 move word and zero (MVWZ) 6-55 move word immediate (MVWI) 6-53 multiply byte (MB) 6-43 multiply double word (MD) 6-44 multiply word (MW) 6-56 OR byte (OB) 6-58 OR double word (OD) 6-59 OR word (OW) 6-60 pop byte (PB) 6-63 pop double word (PD) 6-63 pop word (PW) 6-65 push byte (PSB) 6-64 push double word (PSD) 6-64 push word (PSW) 6-65 reset bits byte (RBTB) 6-66 reset bits double word (RBTD) 6-67 reset bits word (RBTW) 6-68 subtract byte (SB) 6-71 subtract double word (SD) 6-72 subtract word (SW) 6-90 register/ storage long instructions add word (A W) 6-7 exclusive OR word (XW) 6-100 move word (MVW) 6-52 operate I/O (10) 6-37 OR word (OW) 6-61 reset bits word (RBTW) 6-69 subtract word (SW) 6-91 register/ storage short instruction move word short (MVWS) 6-54 registers console data buffer 2-6 current-instruction address (CIAR) 2-6 general 2-6 instruction address (IAR) 2-6 level status (LSR) 2-6 mask 2-6 processor status word (PSW) 2-6 storage address (SAR) 2-6 reserved storage locations 3-2 reset 2-22 reset bits byte (RBTB) instruction register/storage format 6-66 storage/storage format 6-66 reset bits double word (RBTD) instruction register/storage format 6-67 storage/storage format 6-67 rp~pt hit~ morn (R RTW) in~trllrti()n register/register format 6-68 register/storage format 6-68 storage/storage format 6-69 storage to register long format 6-69 reset bits word immediate (RBTWI) instruction register immediate long format 6-70 storage immediate format 6-70 reset key, console 5-8 residual address 4-12 after power-on reset 4-12 updating 4-12 residual byte count 4-12 residual status block size of 4-14 storing 4-14 restrictions instruction and operand address boundaries 2-3 programming, DCB 4-6 programming, DCB (start cycle steal status) 4-12 when in problem state 2-21 result indicators (even, negative, and zero) 2-8 run indicator 5-2 run state 2-21 RO key, console 5-10 R1 key, console 5-10 R2 key, console 5-10 R3 key, console 5-10 R4 key, console 5-10 R5 key, console 5-10 R6 key, console 5 -1 0 R7 key, console 5-10 SAR key, console 5-9 satisfactory, condition code 4-19 scan byte field equal and decrement (SFED) instruction 6-76 scan byte field equal and increment (SFEN) instruction 6-76 scan byte field not equal and decrement (SFNED) instruction 6-77 scan byte field not equal and increment (SFNEN) instruction 6-77 sensor input/output options, description 1-6 sequence indicator, bit in PSW 3-10 set console data lights (SECON) instruction 6-73 set indicators (SEIND) instruction 6-74 set interrupt mask register (SEIMR) instruction 6-73 set level block (SELB) instruction 6-75 shift instructions shift left and test (SL T) 6-83 shift left and test double (SLTD) 6-83 shift left circular (SLC) 6-78 shift left circular double (SLCD) 6-79 shift left logical (SLL) 6-81 Index X-7 shift instructions (continued) shift left logical double (SLLD) 6-82 shift right arithmetic (SRA) 6-84 shift right arithmetic double (SRAD) 6-85 shift right logical (SRL) 6-86 shift right logical double (SRLD) 6-87 shift left and test (SL T) instruction 6-83 shift left and test double (SLTD) instruction 6-83 shift left circular (SLC) instruction count in register format 6-78 immediate count format 6-78 shift left circular double (SLCD) instruction count in register format 6-80 immediate count format 6-79 shift left logical (SLL) instruction count in register format 6-81 immediate count format 6-81 shift left logical double (SLLD) instruction count in register format 6-82 immediate count format 6-82 shift righ t arithmetic (SRA) instruction count in register format 6-84 immediate count format 6-84 shift right arithmetic double (SRAD) instruction count in register format 6-85 immediate count format 6-85 shift righ t logical (SRL) instruction count in register format 6-86 immediate count format 6-86 shift righ t logical double (SRLD) instruction count in register format 6-87 immediate count format 6-87 SIA (see start instruction address) signed numbers defined 2-3 examples 2-4 single bit manipulation instructions test bit (TBT) 6-94 test bit and invert (TBTV) 6-95 test bit and reset (TBTR) 6-94 test bit and set (TBTS) 6-95 soft exception trap conditions 6-1 basic instructions 6-1 soft exception trap conditions, in PSW 3-7 soft exception trap interrupt 3-9 specification check 6-1 specification check, bit in PSW 3-9 stack control block, relationship to data stack 2-24 stack exception 6-1 stack exception, bit in PSW 3-10 stack operations 2-23 stacking data, description 2-24 linkage, description 2-29 start command 4-8,4-8 start cycle steal command 4-8,4-10 start cycle steal status operation 4-12 DCB format 4-12 DCB restrictions 4-12 residual parameters (status) 4-12 start instruction address (SIA) 3-3 start key, console 5-8 states, processor following a reset 2-22 load 2-21 problem 2-21 run 2-21 stop 2-20 supervisor 2-21 wait 2-21 status address, DCB word 4 4-6 status after resets, processor 2-22 status block, residual 4-14 status flags, in PSW 3-9 status flags in residual status block 4-14 status information, I/O 4-20 status words, cycle steal 4-13 stop (STOP) instruction 6-89 stop key/indicator 5-5 stop on address key/indicator 5-6 stop on address mode 5-6 stop on error key, console 5-7 stop state 2-20 storage address register (SAR) 2-6 storage data check status bit 4-21 storage immediate instructions add word immediate (AWl) 6-9 compare word immediate (CWI) 6-29 move address (MV A) 6-45 move word immediate (MVWI) 6-53 OR word immediate (OWl) 6-62 reset bits word immediate (RBTWI) 6-70 subtract word immediate (SWI) 6-93 test word immediate (TWI) 6-96 storage parity, bit in PSW 3-10 storage/ storage instructions add double word (AD) 6-5 add word (A W) 6-7 compare byte (CB) 6-18 compare byte field equal and decrement (CFED) compare byte field equal and increment (CFEN) compare byte field not equal and decrement (CFNED) 6-22 compare byte field not equal and increment (CFNEN) 6-22 compare double word (CD) 6-20 compare word (CW) 6-28 move byte (MVB) 6-46 move byte field and decrement (MVFD) 6-50 move byte field and increment (MVFN) 6-50 move double word (MVD) 6-48 move word (MVW) 6-52 OR byte (OB) 6-58 OR double word (OD) 6-59 OR word (OW) 6-61 reset bits byte (RBTB) 6-66 reset bits double word (RBTD) 6-67 reset bits word (RBTW) 6-69 subtract double word (SD) 6-72 subtract word (SW) 6-91 store key, console 5-8 store multiple (STM) instruction 6-88 storing into main storage 5-12 storing into registers 5-13 6-21 6-21 ( X-8 GA34-0022 c c subtract byte (SB) instruction 6-71 subtract carry indicator (SCY) instruction 6-71 subtract double word (SD) instruction register/storage format 6-72 storage/ storage format 6-72 subtract word (SW) instruction register/register format 6-90 rel!ister/storal!e - format 6-90 storage/ storage format 6-91 storage to register long format 6-91 subtract word immediate (SWI) instruction register immediate long format 6-93 storage immediate format 6-93 subtract word with carry (SWCY) instruction 6-92 summary mask 3-13 summary mask bit 2-11 summary of assembler syntax C-l summary of character codes E-l summary of instructions by format X-I0 by name X-13 supervisor call (SVC) instruction 6-89 supervisor call interrupt 3-7 supervisor state 2-21 su pervisor state bit 2-11 suppress exception (SE) 4-5,4-13 suppression of instructions 6-2 SXV chaining 4-13 syntax, assembler (summary of) C-l system register/register instructions copy console data buffer (CPCON) 6-24 copy current level (CPCL) 6-23 set console data lights (SECON) 6-73 system register/ storage instructions copy in-process flags (CPIPF) 6-25 copy interrupt mask register (CPIMR) 6-24 copy level block (CPLB) 6-26 copy processor status and reset (CPPSR) 6-27 set interrupt mask register (SEIMR) 6-73 set level block (SELB) 6-75 TEA (see top element address) termination of instructions 6-2 test bit (TBT) instruction 6-94 test bit and invert (TBTV) instruction 6-95 test bit and reset (TBTR) instruction 6-94 test bit and set (TBTS) instruction 6-95 test word immediate (TWI) instruction register immediate long format 6-96 storage immediate format 6-96 testing indicators with conditional instructions top element address (TEA) 2-24 trace bit 2-11 trace interrupt 3-7 variable field length byte instructions compare byte field equal and decrement (CFED) 6-21 compare byte field equal and increment (CFEN) 6-21 compare byte field not equal and decrement (CFNED) 6-22 compare byte field not equal and increment (CFNEN) 6-22 fill hvte field :md de~rement (FFn) li-1li fill byte field and increment (FFN) 6-36 move byte field and decrement (MVFD) 6-50 move byte field and increment (MVFN) 6-50 scan byte field equal and decrement (SFED) 6-76 scan byte field equal and increment (SFEN) 6-76 scan byte field not equal and decrement (SFNED) 6-77 scan byte field not equal and increment (SFNEN) 6-77 variable length instructions defined 2-12 examples for address arguments 2-20 wait indicator 5-2 wait state 2-21 WD (see word displacement) word displacement (WD) 2-13,2-14 write command 4-7 zero indicator 2-8 2-10 unsigned numbers defined 2-3 examples 2-4 o Index X-9 Index of Instructions by Format (; branch/jump instructions branch and link (BAL) 6-10 branch and link external (BALX) branch and link short (BALS) 6-11 branch indexed short (BXS) 6-17 branch on condition (BC) 6-12 branch if mixed (BMIX) branch if negative (BN) branch if off (BOFF) branch if on (BON) branch on arithmetically less than (BLT) branch on arithmetically less than or equal (BLE) branch on carry (BCY) branch on equal (BE) branch on even (BEY) branch on logically less than (BLLT) branch on logically less than or equal (BLLE) branch on positive (BP) branch on zero (BZ) branch on condition code (BCC) 6-13 branch on not error (BNER) branch on not condition (BNC) 6-14 branch if not off (BNOFF) branch if not on (BNON) branch on arithmetically greater than (BGT) branch on arithmetically greater than or equal (BGE) branch on logically greater than (BLGT) branch on logically greater than or equal (BLGE) branch on no carry (BNCY) branch on not equal (BNE) branch on not even (BNEY) branch on not mixed (BNMIX) branch on not negative (BNN) branch on not positive (BNP) branch on not zero (BNZ) branch on not condition code (BNCC) 6-15 branch on error (BER) branch on not overflow (BNOY) 6-16 branch on overflow (BOY) 6-16 branch unconditional (B) 6-10 branch external (BX) jump and link (JAL) 6-38 jump on condition (JC) 6-39 jump if mixed (JMIX) jump if off (JOFF) jump if on (JON) jump on arithmetically less than (JLT) jump on arithmetically less than or equal OLE) jump on carry (JCY) jump on equal (JE) jump on even (JEY) jump on logically less than (JLLT) jump on logically less than or equal (JLLE) jump on negative (IN) jump on positive (JP) jump on zero (JZ) X-I0 GA34-0022 branch/jump instructions (continued) jump on count (JCT) 6-40 jump on not condition (JNC) 6-41 jump if not off (JNOFF) jump if not on (JNON) jump on arithmetically greater than (JGT) jump on arithmetically greater than or equal (JGE) jump on logically greater than (JLGT) jump on logically greater than or equal (JLGE) jump on no carry (JNCY) jump on not equal ONE) jump on not even (JNEY) jump on not mixed (JNMIX) jump on not positive (JNP) jump on not zero (JNZ) jump unconditional (J) 6-38 no operation (NOP) 6-57 multiple register/storage instructions load multiple and branch (LMB) 6-42 store mUltiple (STM) 6-88 parametric instructions diagnose (DIAG) 6-32 disable (DIS) 6-33 enable (EN) 6-35 level exit (LEX) 6-41 stop (STOP) 6-89 supervisor call (SYC) 6-89 register immediate instructions add byte immediate (ABI) 6-3 add word immediate (AWl) 6-9 AND word immediate (NWI) 6-57 compare byte immediate (CBI) 6-19 compare word immediate (CWI) 6-29 exclusive OR word immediate (XWI) 6-100 move byte immediate (MVBI) 6-47 OR word immediate (OWl) 6-62 reset bits word immediate (RBTWI) 6-70 subtract word immediate (SWI) 6-93 test word immediate (TWI) 6-96 register/register instructions add carry register (ACY) 6-4 add word (AW) 6-6 add word with carry (AWCY) 6-8 compare word (CW) 6-28 complement register (CMR) 6-23 copy level status register (CPLSR) 6-27 exclusive OR word (XW) 6-99 interchange registers (IR) 6-37 invert register (YR) 6-97 move word (MYW) 6-51 t \. , o C o register/ register instructions (continued) OR word (OW) 6-60 reset bits word (RBTW) 6-68 set indicators (SEIND) 6-74 subtract carry indicator (SCY) 6-71 subtract word 6-90 subtract word (SW) subtract word with carrv (SWCY) 6-92 register/ storage instructions add byte (AB) 6-3 add double word (AD) 6-5 add word (A W) 6-6 compare byte (CB) 6-18 compare double word (CD) 6-20 compare word (CW) 6-28 divide byte (DB) 6-30 divide double word (DD) 6-31 divide word (DW) 6-34 exclusive OR byte (XB) 6-97 exclusive OR double word (XD) 6-98 exclusive OR word (XW) 6-99 move address (MVA) 6-45 move byte (MVB) 6-46 move byte and zero (MVBZ) 6-47 move double word (MVD) 6-48 move double word and zero (MVDZ) 6-49 move word (MVW) 6-51 move word and zero (MVWZ) 6-55 move word immediate (MVWI) 6-53 multiply byte (MB) 6-43 multiply double word (MD) 6-44 multiply word (MW) 6-56 OR byte (OB) 6-58 OR double word (OD) 6-59 OR word (OW) 6-60 pop byte (PB) 6-63 pop double word (PD) 6-63 pop word (PW) 6-65 push byte (PSB) 6-64 push double word (PSD) 6-64 push word (PSW) 6-65 reset bits byte (RBTB) 6-66 reset bits double word (RBTD) 6-67 reset bits word (RBTW) 6-68 subtract byte (SB) 6-71 subtract double word (SD) 6-72 subtract word (SW) 6-90 register/storage long instructions add word (A W) 6-7 exclusive OR word (XW) 6-100 move word (MVW) 6-52 operate I/O (10) 6-37 OR word (OW) 6-61 reset bits word (RBTW) 6-69 subtract word (SW) 6-91 register/storage short instruction move word short (MVWS) 6-54 shift instructions shift left and test (SL T) 6-83 shift left and test double (SLTD) shift left circular (SLC) 6-78 shift instructions (continued) shift left circular double (SLCD) 6-79 shift left logical (SLL) 6-81 shift left logical double (SLLD) 6-82 shift right arithmetic (SRA) 6-84 shift right arithmetic double (SRAD) 6-85 shift right logical (SRL) 6-86 shift right logical double (SRLD) 6-87 single bit manipulation instructions test bit (TBT) 6-94 test bit and invert (TBTV) 6-95 test bit and reset (TBTR) 6-94 test bit and set (TBTS) 6-95 storage immediate instructions add word immediate (AWl) 6-9 compare word immediate (CWI) 6-29 move address (MV A) 6-45 move word immediate (MVWI) 6-53 OR word immediate (OWl) 6-62 reset bits word immediate (RBTWI) 6-70 subtract word immediate (SWI) 6-93 test word immediate (TWI) 6-96 storage/ storage instructions add double word (AD) 6-5 add word (AW) 6-7 compare byte (CB) 6-18 compare byte field equal and decrement (CFED) compare byte field equal and increment (CFEN) compare byte field not equal and decrement (CFNED) 6-22 compare byte field not equal and increment (CFNEN) 6-22 compare double word (CD) 6-20 compare word (CW) 6-28 move byte (MVB) 6-46 move byte field and decrement (MVFD) 6-50 move byte field and increment (MVFN) 6-50 move double word (MVD) 6-48 move word (MVW) 6-52 OR byte (OB) 6-58 OR double word (OD) 6-59 OR word (OW) 6-61 reset bits byte (RBTB) 6-66 reset bits double word (RBTD) 6-67 reset bits word (RBTW) 6-69 subtract double word (SD) 6-72 subtract word (SW) 6-91 system register/register instructions copy console data buffer (CPCON) 6-24 copy current level (CPCL) 6-23 set console data lights (SEC ON) 6-73 system register/storage instructions copy in-process flags (CPIPF) 6-25 copy interrupt mask register (CPIMR) 6-24 copy level block (CPLB) 6-26 copy processor status and reset (CPPSR) 6-27 set interrupt mask register (SEIMR) 6-73 set level block (SELB) 6-75 6-21 6-21 6-83 Index X-II variable field length byte instructions compare byte field equal and decrement (CFED) 6-21 compare byte field equal and increment (CFEN) 6-21 compare byte field not equal and decrement (CFNED) 6-22 compare byte field not equal and increment (CFNEN) 6-22 fill byte field and decrement (FFD) 6-36 fill byte field and increment (FFN) 6-36 move byte field and decrement (MVFD) 6-50 move byte field and increment (MVFN) 6-50 scan byte field equal and decrement (SFED) 6-76 scan byte field equal and increment (SFEN) 6-76 scan byte field not equal and decrement (SFNED) 6-77 scan byte field not equal and increment (SFNEN) 6-77 f \. X-12 GA34-0022 Index of Instructions by Name c ~rlrl hytp (AR) imtmrtion h-~ add byte immediate (ABI) instruction 6-3 add carry register (ACY) instruction 6-4 add double word (AD) instruction register/storage format 6-5 storage/storage format 6-5 add word (A W) instruction register/register 6-6 register/storage format 6-6 storage/storage format 6-7 storage to register long format 6-7 add word immediate (A WI) instruction register immediate long format 6-9 storage immediate format 6-9 add word with carry (A WCY) instruction 6-8 and word immediate (NWI) instruction 6-57 c o branch and link (BAL) instruction 6-10 branch and link ex ternal (BALX) instruction 6-10 branch and link short (BALS) instruction 6-11 branch external (BX) instruction 6-10 branch if mixed (BMIX) instruction 6-12 branch if negative (BN) instruction 6-12 branch if not off (BNOFF) instruction 6-14 branch if not on (BNON) instruction 6-14 branch if off (BOFF) instruction 6-12 branch if on (BON) instruction 6-12 branch indexed short (BXS) instruction 6-17 branch on arithmetically greater than (BGT) instruction 6-14 branch on arithmetically greater than or equal (BGE) instruction 6-14 branch on arithmetically less than (BLT) instruction 6-12 branch on arithmetically less than or equal (BLE) instruction 6-12 branch on carry (BCY) instruction 6-12 branch on condition (BC) instruction 6-12 branch on condition code (BCC) instruction 6-13 branch on equal (BE) instruction 6-12 branch on error (BER) instruction 6-15 branch on even (BEV) instruction 6-12 branch on logically greater than (BLGT) instruction 6-14 branch on logically greater than or equal (BLGE) instruction 6-14 branch on logically less than (BLL T) instruction 6-12 branch on logically less than or equal (BLLE) instruction 6-12 branch on no carry (BNCY) instruction 6-14 branch on not condition (BNC) instruction 6-14 branch on not condition code (BNCC) instruction 6-15 branch on not equal (BNE) instruction 6-14 branch on not error (BNER) instruction 6-13 branch on not even (BNEV) instruction 6-14 branch on not mixed (BNMIX) instruction 6-14 hr!lnl'h on not np~!ltivp ~RNN) in<:tT111'tion h-14 branch on not overflow (BNOY) instruction 6-16 branch on not positive (BNP) instruction 6-14 branch on not zero (BNZ) instruction 6-14 branch on overflow (BOY) instruction 6-16 branch on positive (BP) instruction 6-12 branch on zero (BZ) instruction 6-12 branch unconditional (B) instruction 6-10 compare byte (CB) instruction register/storage format 6-18 storage/storage format 6-18 compare byte field equal and decrement (CFED) instruction 6-21 compare byte field equal and increment (CFEN) instruction 6-21 compare byte field not equal and decrement (CFNED) instruction 6-22 compare byte field not equal and increment (CFNEN) instruction 6-22 compare byte immediate (CBI) instruction 6-19 compare double word (CD) instruction register/storage format 6-20 storage/storage format 6-20 compare word (CW) instruction register/register format 6-28 register/storage format 6-28 storage/storage format 6-28 compare word immediate (CWI) instruction register immediate long format 6-29 storage immediate format 6-29 complement register (CMR) instruction 6-23 copy console data buffer (CPCON) instruction 6-24 copy current level (CPCL) instruction 6-23 copy in-process flags (CPIPF) instruction 6-25 copy interrupt mask register (CPIMR) instruction 6-24 copy level block (CPLB) instruction 6-26 copy level status register (CPLSR) instruction 6-27 copy processor status and reset (CPPSR) instruction 6-27 diagnose (DIAG) instruction 6-32 disable (DIS) instruction 6-33 divide byte (DB) instruction 6-30 divide double word (DD) instruction divide word (DW) instruction 6-34 6-31 enable (EN) instruction 6-35 exclusive OR byte (XB) instruction 6-97 exclusive OR double word (XD) instruction 6-98 exclusive OR word (XW) instruction register/register format 6-99 register/storage format 6-99 storage to register long format 6-100 exclusive OR word immediate (XWI) instruction 6-100 Index X-13 fill byte field and decrement (FFD) instruction 6-36 fill byte field and increment (FFN) instruction 6-36 interchange registers (IR) instruction 6-37 invert register (VR) instruction 6-97 jump and link (JAL) instruction 6-38 jump if mixed (JMIX) instruction 6-39 jump if not off (JNOFF) instruction 6-41 jump if not on (JNON) instruction 6-41 jump if off (JOFF) instruction 6-39 jump if on (JON) instruction 6-39 jump on arithmeticall greater than or equal (JGE) instruction 6-41 jump on arithmetically greater than (JGT) instruction 6-41 jump on arithmetically less than (JL T) instruction 6-39 jump on arithmetically less than or equal (JLE) instruction 6-39 jump on carry (JCY) instruction 6-39 jump on condition (JC) instruction 6-39 jump on count (JCT) instruction 6-40 jump on equal (JE) instruction 6-39 jump on even (JEV) instruction 6-39 jump on logically greater than (JLGT) instruction 6-41 jump on logically greater than or equal (JLGE) instruction 6-41 jump on logically less than (JLLT) instruction 6-39 jump on logically less than or equal (JLLE) instruction 6-39 jump on negative (IN) instruction 6-39 jump on no carry (JNCY) instruction 6-41 jump on not condition (JNC) instruction 6-41 jump on not equal (JNE) instruction 6-41 jump on not even (JNEV) instruction 6-41 jump on not mixed (JNMIX) instruction 6-41 jump on not negative (JNN) instruction 641 jump on not positive (JNP) instruction 6-41 jump on not zero (JNZ) instruction 6-41 jump on positive (JP) instruction 6-39 jump on zero (JZ) instruction 6-39 jump unconditional (J) instruction 6-38 level exit (LEX) instruction 6-41 load multiple and branch (LMB) instruction 6-42 move address (MV A) instruction storage address to register format 6-45 storage immediate format 6-45 move byte (MVB) instruction register/storage format 6-46 storage/storage format 6-46 move byte and zero (MVBZ) instruction 6-47 move byte field and decrement (MVFD) instruction 6-50 move byte field and increment (MVFN) instruction 6-50 move byte immediate (MVBI) instruction 6-47 move double word (MVD) instruction register/storage format 6-48 storage/storage format 6-48 move double word and zero (MVDZ) instruction 6-49 X-14 GA34-0022 move word (MVW) instruction register/register format 6-51 register/ storage format 6-51 register to storage long format 6-51 storage/ storage format 6-52 storage to register long format 6-52 move word and zero (MVWZ) instruction 6-55 move word immediate (MVWI) storage immediate format 6-53 storage to register format 6-53 move word short (MVWS) instruction register to storage format 6-54 storage to register format 6-54 multiply byte (MB) instruction 6-43 multiply double word (MD) instruction 6-44 multiply word (MW) instruction 6-56 no operation (NOP) instruction 6-57 operate I/O (10) instruction 6-37 OR byte (OB) instruction register/storage format 6-58 storage/ storage format 6-58 OR double word (OD) instruction register/storage format 6-59 storage/storage format 6-59 OR word (OW) instruction register/register format 6-60 register/storage format 6-60 storage/ storage format 6-61 storage to register long format 6-61 OR word immediate (OWl) instruction register immediate format 6-62 storage immediate format 6-62 pop byte (PB) instruction 6-63 pop doubleword (PD) instruction 6-63 pop word (PW) instruction 6-65 push byte (PSB) instruction 6-64 push double word (PSD) instruction 6-64 push word (PSW) instruction 6-65 reset bits byte (RBTB) instruction register/storage format 6-66 storage/storage format 6-66 reset bits double word (RBTD) instruction register/storage format 6-67 storage/storage format 6-67 reset bits word (RBTW) instruction register/register format 6-68 register/storage format 6-68 storage/storage format 6-69 storage to register long format 6-69 reset bits word immediate (RBTWI) instruction register immediate long format 6-70 storage immediate format 6-70 l ( /1 c c o scan byte field equal and decrement (SFED) instruction 6-76 scan byte field equal and increment (SFEN) instruction 6-76 scan byte field not equal and decrement (SFNED) instruction 6-77 scan byte field not equal and increment (SFNEN) instruction 6-77 set console data lights (SECON) instruction 6-73 set indicators (SEIND) instruction 6-74 set interrupt mask register (SEIMR) instruction 6-73 set level block (SELB) instruction 6-75 shift left and test (SLT) instruction 6-83 shift left and test double (SLTD) instruction 6-83 shift left circular (SLC) instruction count in register format 6-78 immediate count format 6-78 shift left circular double (SLCD) instruction count in register format 6-80 immediate count format 6-79 shift left logical (SLL) instruction count in register format 6-81 immediate count format 6-81 shift left logical double (SLLD) instruction count in register format 6-82 immediate count format 6-82 shift righ t arithmetic (SRA) instruction count in register format 6-84 immediate count format 6-84 shift right arithmetic double (SRAD) instruction count in register format 6-85 immediate count format 6-85 shift right logical (SRL) instruction count in register format 6-86 immediate count format 6-86 shift right logical double (SRLD) instruction count in register format 6-87 immediate count format 6-87 stop (STOP) instruction 6-89 store multiple (STM) instruction 6-88 subtract byte (SB) instruction 6-71 subtract carry indicator (SCY) instruction 6-71 subtract doubleword (SD) instruction register/storage format 6-72 storage/ storage format 6-72 subtract word (SW) instruction register/register format 6-90 register/storage format 6-90 storage/storage format 6-91 storage to register long format 6-91 subtract word immediate (SWI) instruction register immediate long format 6-93 storage immediate format 6-93 subtract word with carry (SWCY) instruction 6-92 supervisor call (SVC) instruction 6-89 test test test test test bit (TBT) instruction 6-94 bit and invert (TBTV) instruction 6-95 bit and reset (TBTR) instruction 6-94 bit and set (TBTS) instruction 6-95 word immediate (TWI) instruction register immediate long format 6-96 storage immediate format 6-96 Index X-I5 X-16 GA34-0022 IBM Series/1 Model 3 4953 Processor and Processor Features Description GA34-0022-1 c READER'S COMMENT FORM YOUR COMMENTS, PLEASE . .. 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Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:01:01 09:28:04-08:00 Modify Date : 2013:01:01 10:19:29-08:00 Metadata Date : 2013:01:01 10:19:29-08:00 Producer : Adobe Acrobat 9.52 Paper Capture Plug-in Format : application/pdf Document ID : uuid:47095251-eabb-4661-b918-5d3358e0dfc2 Instance ID : uuid:d0e37e59-02c0-4c5d-9abd-4b9b918d3e27 Page Layout : SinglePage Page Mode : UseNone Page Count : 270EXIF Metadata provided by EXIF.tools