GA34 0034 5_Series_1_Reference_Summary_Sep85 5 Series 1 Reference Summary Sep85
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GA34-0034-5
File No. 51-16
IBM Series/1
Reference Summary
Series/1
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- ----- - ---------
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GA34-0034-5
File No. 51-16
IBM Series/1
Reference Summary
Series/1
Sixth Edition (September 1985)
This is a major revision of, and obsoletes, GA34-0034-4.
New information includes:
4950 Processor
New and modified instructions
Modified address key register (AKR).
4950/5170 Model 495 Asynchronous Communications
4950/5170 Model 495 Disk/Diskette Attachment
4971 Printer and the 4201 Proprinter
Series/Ito PC channel attachment.
This publication is intended as a convenient reference source
for experienced programmers, engineers/technicians, and
service personnel.
Changes are periodically made to the information herein; any
such changes will be reported in subsequent revisions or
Technical Newsletters.
It is possible that this material may contain reference to, or
information about IBM products (machines and programs),
programming, or services which are not announced in your
country. Such references or information must not be
construed to mean that IBM intends to announce such IBM
products, programming, or services in your country.
Publications are not stocked at the address given below.
Requests for copies of IBM publications should be made to
your IBM representative or the IBM branch office serving
your locality.
This publication could contain technical inaccuracies or
typographical errors. A form for readers' comments is
provided at the back of this publication. If the form has been
removed, address your comments to IBM Corporation,
Information Development, Department 28E, Internal Zip 1803,
P. O. Box 1328, Boca Raton, Florida 33429-1328. IBM may
use and distribute any of the information you supply in any
way it believes appropriate without incurring any obligation
whatever. You may, of course, continue to use the
information you supply.
© Copyright International Business Machines Corporation
1977, 1978, 1979, 1983, 1984, 1985
Contents
Section 1. Series/l Processor 1-1
Instructions 1-2
List of Instructions by Mnemonic 1-2
Hexadecimal List of Instructions 1-15
Assembler Syntax 1-27
Instruction Format Types 1-37
Type 1 1-37
Type 2 1-37
Type 3 1-37
Type 4 1-38
Type 5 1-38
Type 6 1-38
Type 7 1-38
Type 8 1-39
Type 9 1-39
Type 10 1-39
Type 11 1-39
Type 12 1-40
Type 13 1-40
Type 14 1-40
Type 15 1-40
Type 16 1-41
Type 17 1-41
Type 18 1-41
Type 19 1-41
Type 20 1-42
Type 21 1-42
Type 22 1-42
Type 23 1-42
Type 24 1-43
Type 25 1-43
Type 26 1-43
Type 27 1-43
Type 28 1-44
Code Conversion Table 1-45
Class Interrupt Priority 1-59
Control Blocks 1-60
Level Status Block 1-60
Stack Control Block 1-61
Contents
iii
Indicators Tested by Conditional Branch and Jump
Instructions 1-62
Registers 1-63
Address Key Register (AKR)~Standard* 1-63
Address Key Register (AKR)-4956 Processor Models E
and 60E (4-Bit Mode) 1-64
Address Key Register (AKR)-4950 Processor (5-Bit
Mode) 1-64
Level Status Register (LSR) 1-65
Mask Register-Interrupt Level 1-65
Processor Status Word (PSW) 1-66
Segmentation Register* 1-66
Reserved Storage Locations 1-67
Section 2. Common I/O 2-1
Condition Codes 2-2
I/O Instruction Condition Codes 2-2
Interrupt Condition Codes 2-3
Device ID Word 2-4
Device ID Word Format 2-4
List of Device ID Words 2-5
Immediate Device Control Block (IDCB) 2-8
Interrupt ID Word 2-9
Interrupt Status Byte (ISB) 2-10
DPC Devices 2-10
Cycle-Steal Devices 2-10
Section 3. I/O Devices and Features 3-1
Communications Feature-Asynchronous 3-3
I/O Commands 3-3
Device Control Block (DCB) 3-3
Cycle-Steal Status Words 3-4
Interrupt Condition Codes Reported 3-5
Interrupt Information Byte (lIB) 3-5
Interrupt Status Byte (ISB) 3-6
Communications Feature-BSC 3-7
I/O Commands 3-7
Device Control Block (DCB) 3-7
Cycle-Steal Status Words 3-8
Interrupt Condition Codes Reported 3-9
Interrupt Information Byte (lIB) 3-9
Interrupt Status Byte (ISB) 3-9
Customer Direct Program Control Adapter Feature 3-10
iv
GA34-0034
I/O Commands 3-10
Device Status Word 3-10
Interrupt Condition Codes Reported 3-11
Interrupt Information Byte (lIB) 3-11
Integrated DI/DO Non-Isolated Feature 3-12
I/O Commands 3-12
Device Status Word 3-12
Interrupt Condition Codes Reported 3-13
Interrupt Information Byte (lIB) 3-13
Local Communications Controller Attachment Feature 3-14
. I/O Commands 3-14
Device Control Block (DCB) 3-14
Cycle-Steal Status Words 3-15
Residual Status Block (RSB) 3-16
Interrupt Condition Codes Reported 3-17
Interrupt Information Byte (lIB) 3-17
Interrupt Status Byte (ISB) 3-18
Multidrop Workstation Attachment 3-19
I/O Commands 3-19
Device Control Block (DC B)-General Format 3-19
Device Control Block (DCB)-Start Control
Command 3-20
Cycle-Steal Status Words 3-21
Interrupt Condition Codes Reported 3-25
Interrupt Information Byte (lIB) 3-25
Interrupt Status Byte (ISB) 3-25
Multifunction Attachment Feature 3-26
I/O Commands 3-26
Device Control Block (DCB) 3-26
Cycle-Steal Status Words* 3-27
Interrupt Status Byte (ISB) 3-29
Printer Attachment-5200 Series 3-30
I/O Commands 3-30
Device Control Block (DCB)-Data Stream Mode 3-30
Device Control Block (DCB)-Emulation Mode 3-32
Device Control Block (DCB)-Start Coritrol
Command 3-33
Cycle-Steal Status Words 3-35
Interrupt Condition Codes Reported 3-38
Interrupt Information Byte (lIB) 3-38
Interrupt Status Byte (ISB) 3-38
Communications Feature-Programmable Multiline
Attachment 3-39
Contents
v
I/O Commands 3-39
Device Control Block (DCB)-General Format 3-39
Device Control Block (DCB)-Set Mode and Set Control
(Asynchronous) 3-40
Device Control Block (DCB)-Set Mode
(Synchronous) 3-41
Cycle-Steal Status Words 3-44
Interrupt Condition Codes Reported 3-45
Interrupt Information Byte (lIB) 3-45
Interrupt Status Byte (ISB) 3-45
Programmable Two-Channel Switch Feature 3-46
I/O Commands 3-46
Device Status Word 3-47
Interrupt Condition Codes Reported 3-47
Interrupt Information Byte (lIB) 3-47
Communications Feature-SDLC 3-48
I/O Commands 3-48
Device Control Block (DCB) 3-48
Cycle-Steal Status Words 3-49
Residual Status Block (RSB) 3-50
Interrupt Condition Codes Reported 3-51
Interrupt Information Byte (lIB) 3-51
Interrupt Status Byte (ISB) 3-51
Series/l to PC Attachment 3-52
I/O Commands 3-52
Device Control Block (DCB) for the Start Control Store
Command (Hex 7C) 3-52
Control Word (DCB Word 0) for the Start Control Store
Command (Hex 7C) 3-53
Operation Dependent Information (DCB Word 2) 3-53
Device Control Block (DCB) for the Start Write
Command (Hex 70) 3-54
Control Word (DCB Word 0) for the Start Write
Command (Hex 70) 3-54
Device Control Block (DCB) for the Start Read Command
(Hex 71) 3-55
Control Word (DCB Word 0) for the Start Read
Command (Hex 71) 3-55
Device Control Block (DCB) for the Start Diagnostics
Command (Hex 7D) 3-56
Control Word (DCB Word 0) for the Start Diagnostics
Command (Hex 7D) 3-56
vi
GA34-0034
Device Control Block (DCB) for the Start Cycle Steal
Status Command (Hex 7F) 3-57
Control Word (DCB Word 0) for the Start Cycle Steal
Status Command (Hex 7F) 3-57
Cycle-Steal Status Words (Loaded Microcode
Control) 3-58
Cycle-Steal Status Words (ROS Control) 3-59
Residual Status Block (RSB) under Loaded Microcode
Control 3-60
Interrupt Condition Codes Reported 3-60
Interrupt Information Byte (IIB)* 3-61
Interrupt Status Byte (ISB) 3-61
Series/1-System/370 Channel Attachment Feature 3-62
Series/1 I/O Commands 3-62
Series/1 Device Control Block (DCB) 3-63
Series/1 Device Status Word 3-64
Series/1 Cycle-Steal Status Words 3-64
Series/1 Residual Status Block (RSB) 3-65
Series/1 Interrupt Condition Codes Reported 3-65
Series;i Interrupt Information Byte (lIB) 3-65
Series/1 Interrupt Status Byte (ISB) 3-66
System/370 I/O Commands 3-66
System/370 Data for a Sense Command 3-66
System/370 Data for a Sense I/O Command 3-67
System/370 Status Byte 3-67
Synchronous Communications Single-Line Control 3-68
I/O Commands 3-68
Device Control Block (DCB)-SDLC/HDLC 3-69
Device Control Block (DCB)-BSC 3-70
Device Control Block (DCB)-Leased
Operation-SDLC/HDLC/BSC 3-71
Device Control Block (DCB)-X.21 Switched
Operation 3-73
Cycle-Steal Status Words-SDLC/HDLC 3-74
Cycle-Steal Status Words-BSC 3-75
Interrupt Condition Codes
Reported-SDLC/HDLC/BSC 3-77
Interrupt Information Byte
(IIB)-SDLC/HDLC/BSC 3-77
Interrupt Status Byte (ISB)-SDLC/HDLC/BSC 3-77
Telephone Communications Attachment Feature 3-78
I/O Commands 3-78
Device Control Block (DCB) 3-79
Contents
vii
Cycle-Steal Status Words 3-80
Interrupt Condition Codes Reported 3-81
Interrupt Information Byte (lIB) 3-81
Interrupt Status Byte (ISB) 3-81
Teletypewriter Adapter Feature 3-82
I/O Commands 3-82
Device Status Word 3-82
Interrupt Condition Codes Reported 3-82
Interrupt Information Byte (lIB) 3-82
Timer Feature 3-83
I/O Commands 3-83
Device Status Word 3-83
Interrupt Condition Codes Reported 3-83
Interrupt Information Byte (lIB) 3-83
Two Channel Switch Feature 3-84
I/O Commands 3-84
Device Status Word 3-84
Interrupt Condition Codes Reported 3-85
Interrupt Information Byte (lIB) 3-85
Interrupt Status Byte (lSB) 3-85
4950/5170 Model 495 Asynchronous 3-86
I/O Commands 3-86
Device Control Block (DCB) with Word 0', Bit 8 Off 3-86
Device Control Block (DCB) with Word 0, Bit 8 On 3-88
Device Control Block (DCB)-Start Control Command in
set expanded mode 3-89
Cycle-Steal Status Words 3-89
Interrupt Condition Codes Reported 3-90
Interrupt Information Byte (lIB) 3-90
Interrupt Status Byte (lSB) 3-91
4950/5170 Model 495 Disk/Diskette Adapter 3-92
I/O Commands 3-92
Device Control Block (DCB) 3-92
Cycle-Steal Status Words 3-93
Interrupt Condition Codes Reported 3-96
Interrupt Information Byte (lIB) 3-96
Interrupt Status Byte (lSB) 3-96
4962 Disk Storage Unit 3-97
I/O Commands 3-97
Device Control Block (DCB) 3-97
Cycle-Steal Status Words 3-98
Interrupt Condition Codes Reported 3-100
Interrupt Information Byte (lIB) 3-100
viii
GA34-0034
Interrupt Status Byte (ISB) 3-100
4963 Disk Subsystem 3-101
I/O Commands 3-101
Device Control Block (DCB) 3-102
Cycle-Steal Status Words 3-105
Residual Status Block (RSB) 3-109
Interrupt Condition Codes Reported 3-111
Interrupt Information Byte (lIB) 3-111
Interrupt Status Byte (ISB) 3-111
4964 Diskette Unit 3-112
I/O Commands 3-112
Device Control Block (DCB) 3-112
Cycle-Steal Status Words 3-113
Interrupt Condition Codes Reported 3-115
Interrupt Information Byte (lIB) 3-115
Interrupt Status Byte (ISB) 3-115
4965 Storage and I/O Expansion Unit (Modell) 3-116
1/0 Commands 3-116
Device Control Block (DCB) 3-116
Cycle-Steal Status Words 3-118
Residual Status Block (RSB) 3-121
Interrupt Condition Codes Reported 3-123
Interrupt Information Byte (lIB) 3-123
Interrupt Status Byte (ISB) 3-123
4965 Storage and I/O Expansion Unit (Models 30D and
60D) 3-124
I/O Commands 3-124
Device Control Block (DCB) for a Start Command 3-124
Cycle-Steal Status Words 3-126
Residual Status Block (RSB) 3-132
Interrupt Condition Codes Reported 3-133
Interrupt Information Byte (lIB) 3-133
Interrupt Status Byte (ISB) 3-133
4966 Diskette Magazine Unit 3-134
I/O Commands 3-134
Device Control Block (DCB) 3-134
Cycle-Steal Status Words 3-136
Residual Status Block (RSB) 3-139
Interrupt Condition Codes Reported 3-140
Interrupt Information Byte (lIB) 3-141
Interrupt Status Byte (ISB) 3-141
4967 High-Performance Disk Subsystem 3-142
I/O Commands 3-142
Contents
ix
Device Control Block (DCB)-Physical Operations 3-143
Device Control Block (DCB)-Logical Operations 3-144
Device Control Block (DCB)-Scan Operations 3-145
Cycle-Steal Status Words 3-146
Interrupt Condition Codes Reported 3-151
Interrupt Information Byte (lIB) 3-151
Interrupt Status Byte (ISB) 3-151
4968 Magnetic Tape Unit 3-152
I/O Commands 3-152
Device Control Block (DCB) 3-152
Cycle-Steal Status Words 3-153
Start Status (Current Status Word) 3-155
Residual Status Block (RSB) 3-155
Interrupt Condition Codes Reported 3-157
Interrupt Information Byte (lIB) 3-157
Interrupt Status Byte (ISB) 3-157
4969 Magnetic Tape Subsystem 3-158
I/O Commands 3-158
Device Control Block (DCB) 3-158
Cycle-Steal Status Words 3-160
Residual Status Block (RSB) 3-162
Interrupt Condition Codes Reported 3-164
Interrupt Information Byte (lIB) 3-164
Interrupt Status Byte (ISB) 3-164
4971 Printer and the 4201 Proprinter 3-165
I/O Commands 3-165
Device Control Block (DCB) 3-165
Cycle-Steal Status Words 3-166
Interrupt Condition Codes Reported 3-168
Interrupt Information Byte (lIB) 3-168
Interrupt Status Byte (ISB) 3-168
4973 Line Printer 3-169
I/O Commands 3-169
Device Control Block (DCB) 3-169
Cycle-Steal Status Words 3-170
Interrupt Condition Codes Reported 3-172
Interrupt Information Byte (lIB) 3-172
Interrupt Status Byte (ISB) 3-172
4974 Printer 3-173
I/O Commands 3-173
Device Control Block (DCB) 3-173
Cycle-Steal Status Words 3-174
Interrupt Condition Codes Reported 3-176
x
GA34-0034
Interrupt Information Byte (lIB) 3-176
Interrupt Status Byte (ISB) 3-176
4975 Printer 3-177
.
I/O Commands 3-177
Device Control Block (DCB) 3-177
Cycle Steal Status Words 3-178
Interrupt Condition Codes Reported 3-181
Interrupt Information Byte (lIB) 3-181
Interrupt Status Byte (ISB) * 3-181
4978 Display Station Attachment 3-182
I/O Commands 3-182
Device Control Block (DCB)-Start Commands 3-182
Cycle-Steal Status Words 3-184
Interrupt Condition Codes Reported 3-184
Interrupt Information Byte (lIB) 3'-184
Interrupt Status Byte (ISB) 3-185
4979 Display Station 3-186
I/O Commands 3-186
Device Control Block (DCB) 3-186
Cycle-Steal Status Words 3-187
Interrupt Condition Codes Reported 3-188
Interrupt Information Byte (lIB) 3-188
Interrupt Status Byte (ISB) 3-188
4982 Sensor I/O Unit 3-189
I/O Commands 3-189
Device Status Words 3-190
Interrupt Condition Codes Reported 3-192
Interrupt Information Byte (lIB) 3-192
Interrupt Status Byte (ISB) 3-192
4987 Programmable Communications Subsystem 3-193
I/O Commands 3-193
Device Control Block (DCB)-General Format 3-194
Device Control Block (DCB)-Extended 3-195
Cycle-Steal Status Words 3-196
Residual Status Block (RSB)-General Format
DCB 3-198
Residual Status Block (RSB)-Extended DCB 3-199
Interrupt Condition Codes Reported 3-199
Interrupt Information Byte (lIB) 3-199
Interrupt Status Byte (ISB) 3-200
5250 Information Display System Attachment Feature 3-201
I/O Commands 3-201
Device Control Block (DCB) 3-201
Contents
xi
Cycle-Steal Status Words 3-202
Residual Status Block (RSB) 3-204
Interrupt Condition Codes Reported 3-205
Interrupt Information Byte (lIB) 3-205
Interrupt Status Byte (ISB) 3-206
xii
GA34-0034
Section 1. Series/1 Processor
Instructions 1-2
Code Conversion Table 1-45
Class Interrupt Priority 1-59
Control Blocks 1-60
Indicators Tested By Conditional Branch and Jump
Instructions 1-62
Registers 1-63
Reserved Storage Locations 1-67
Section 1. Series/l Processor
1-1
Instructions
List of Instructions by Mnemonic
The instructions are in alphabetical sequence based on
assembler mnemonics. See "Assembler Syntax" in this section
for syntax definitions.
Symbols used in the list are:
*
**
***
#
t
tt
ttt
FT
&
&&
&&&
1-2
Indirect address
This instruction is treated as a NOP on the 4954 and
4956 processors.
This instruction is modified for 4-bit mode operation
.on the 4956 processor models E and 60E. See IBM
Series/l 4956 Processor Model E (60E) and Processor
Features Description, GA34-0289 (GA34-0293).
This instruction applies to the 4956 processor models
E and 60E only. It is intended to be used exclusively
by the operating system, and, therefore, does not
represent an assembler mnemonic. However, it may
be entered in machine code if necessary. See
"Hexadecimal List of Instructions" in this section and
IBM Series/l 4956 Processor Model E (60E) and
Processor Features Description, GA34-0289
(GA34-0293).
This instruction applies to 4950, 4954, 4955, and
4956 processors that have the floating-point feature
installed.
This instruction is not used on the 4953 processor.
This instruction applies to the 4950, 4952, 4954, and
4956 processors only.
Format type. The number in this column can be used
to find the correct hardware format for the instruction.
See "Instruction Format Types" in this section.
4950 Emulated Instruction
4950 Emulated Instruction in this syntax only
4950 Emulated Instruction for storage protect, EOS,
and address translation
GA34-0034
Mnemonic
Instruction name
Syntax
Ft
AA
Add Address
AB
Add Byte
ABI
ACY
AD&
Add Byte Immediate
Add Carry Register
Add Doubleword
raddr,reg[,reg]
raddr,addr4
reg,addr4
addr4,reg
byte,reg
reg
reg,addr4
addr4,reg
addr5,addr4
15
8
23
23
1
14
24
24
ARIB
#
AW
Address Resolution
with Indirect
Branch
Address Resolution
with Indirect
Branch-On
Address Resolution
with Indirect
Branch-Off
Add Word
AWCY
AWl
Add Word With Carry
Add Word Immediate
14
23
23
21
13
14
15
8
B
BAL
BALS
Branch Unconditional
Branch and Link
Branch and Link
Short
BALX
Branch and Link
External
Branch on Condition
Branch on Condition
Code
Branch on Carry
reg,reg,
reg,addr4
addr4,reg
addr5,addr4&&
longaddr,reg
reg,reg
word,reg[,reg]
word,addr4
longaddr
longaddr,reg
(reg,jdisp) *
(reg)*
addr*
See BAL
ARIBON
#
ARIBOFF
#
BC
BCC
BCY
cond,longaddr
cond,longaddr
21
13
13
28
28
28
13
13
See BC
Section 1. Series/l Processor
1-3
Mnemonic
Instruction name
Syntax
BE
BER
BEV
BGE
Branch on Equal
Branch on Error
Branch on Even
Branch on
Arithmetically
Greater Than
or Equal
Branch on
Arithmetically
Greater Than
Branch on
Arithmetically
Less Than or Equal
Branch on Logically
Greater Than
or Equal
Branch on Logically
Greater Than
Branch on Logically
Less Than or Equal
Branch on Logically
Less Than
Branch on
Arithmetically
Less Than
Branch if Mixed
Branch on Negative
Branch on
Not Condition
Branch on
Not Condition Code
Branch on No Carry
Branch on Not Equal
Branch if Not Error
Branch on Not Even
Branch if Not Mixed
See BC
See BNCC
See BC
See BNC
BGT
BLE
BLGE
BLGT
BLLE
BLLT
BLT
BMIX
BN
BNC
BNCC
BNCY
BNE
BNER
BNEV
BNMIX
1-4
GA34-0034
Ft
See BNC
See BC
See BNC
See BNC
SeeBC
SeeBC
SeeBC
See BC
SeeBC
cond,longaddr
13
cond,longaddr
13
See BNC
See BNC
See BCC
See BNC
See BNC
Mnemonic
Instruction name
Syntax
BNN
See BNC
BNZ
BOFF
BON
BOV
BP
BX
BXS
Branch on
Not Negative
Branch if Not Off
Branch if Not On
Branch on
Not Overflow
Branch on
Not Positive
Branch on Not Zero
Branch if Off
Branch if On
Branch on Overflow
Branch on Positive
Branch External
Branch Indexed Short
BZ
CA
Branch on Zero
Compare Address
CB
Compare Byte
CBI
Compare Byte
Immediate
Compare Doubleword
BNOFF
BNON
BNOV
BNP
CD&
CFED
CFEN
CFNED
Compare Byte Field
Equal and
Decrement
Compare Byte Field
Equal and
Increment
Compare Byte Field
Not Equal and
Decrement
See BNC
See BNC
longaddr
Ft
13
See BNC
See BNC
See BC
SeeBC
longaddr
See BC
vcon (See B)
(reg l -7,jdisp)
(reg l -7 )
addr
SeeBC
raddr,reg
raddr,addr4
addr4,reg
addr5,addr4&&
byte,reg
15
8
23
17
27
addr4,reg
addr5,addr4
(reg),(reg)
24
18
5
13
10
10
10
(reg),(reg)
5
(reg),(reg)
5
Section L Series/l Processor
1-5
Mnemonic
Instruction name
Syntax
CFNEN
Compare Byte Field
Not Equal and
Increment
Complement Register
Copy Address
Key Register
Copy Current Level
Copy Clock
(reg),(reg)
reg[,reg]
addr4
reg
reg
reg
14
11
16
16
16
Copy Comparator
reg
16
Copy Console Data
Buffer
Copy Floating level
Block
Copy Interrupt Mask
Register
Copy In-Process Flags
Copy Instruction
Space Key
Copy Level Block
Copy Level
Status Register
Copy Operand 1 Key
reg
16
freg,addr4
11
addr4
11
addr4
addr4
reg
reg,addr4
reg
11
11
16
11
14
addr4
reg
addr4
reg
addr4
11
16
11
16
11
reg,addr4
11
reg,addr4
11
reg,reg
add4,reg
ad drS ,addr4&&
14
23
17
CMR
CPAKR
tt***
CPCL
CPCLK
ttt&
CPCMP
ttt&
CPCON&
CPFLB
t&
CPIMR
CPIPF&
CPISKtt
CPLB
CPLSR
CPOOK
tt
CPOTK
tt
CPPSR
***
CPSK
tt**&
CPSR
tt***&
CW
1_t:.
n. A '111
Copy Operand 2 Key
Copy Processor Status
and Reset
Copy Storage Key
Copy Segmentation
Register
Compare Word
nn'lll
Ft
5
Mnemonic
Instruction name
Compare Word
Immediate
Divide Byte
DB&
Divide Doubleword
DD&
Diagnose
DIAG
DIS***&&& Disable
Divide Word
DW&
EN***&&& Enable
Floating Add
FAt&
CWI
FADt&
FCt&
FCDt&
FDt&
FDDt&
FFD
FFN
FMt&
FMDt&
FMVt&
FMVCt&
FMVCD
t&
FMVDt&
Floating Add
Double
Floating Compare
Floating Compare
Double
Floating Divide
Floating Divide
Double
Fill Byte Field and
Decrement
Fill Byte Field and
Increment
Floating Multiply
Floating Multiply
Double
Floating Move
Floating Move and
Convert
Floating Move and
Convert Double
Floating Move
Double
Syntax
Ft
word,reg
word,addr4
addr4,reg
addr4,reg
ubyte
ubyte
addr4,reg
ubyte
addr4,freg
freg,freg
addr4,freg
freg,freg
freg,freg
freg,freg
15
8
26
26
12
12
26
12
3
4
3
4
4
4
addr4,freg
freg,freg
addr4,freg
freg,freg
reg,(reg)
3
4
3
4
reg,(reg)
5
addr4,freg
freg,freg
addr4,freg
freg,freg
addr4,freg
freg,freg
freg,addr4
addr4,freg
freg,addr4
addr4,freg
freg,addr4
addr4,freg
freg,freg
freg,addr4
3
4
3
4
3
4
3
3
3
3
3
3
4
3
Section 1. Series/l Processor
5
1-7
Mnemonic
Instruction name
Syntax
Ft
FSt&
Floating Subtract
FSDt&
3
4
3
4
13
12
IR
J
Floating Subtract
Double
Operate I/O
Interchange Operand
Keys
Interchange Registers
Jump Unconditional
addr4,freg
freg,freg
addr4,freg
freg,freg
longaddr
JAL
Jump and Link
JC
Jump on Condition
JCT
Jump on Count
14
10
10
19
19
2
2
"22
22
JCY
JE
JEV
JGE
Jump on Carry
Jump on Equal
Jump on Even
Jump on
Arithmetically
Greater Than
or Equal
Jump on
Arithmetically
Greater Than
Jump on
Arithmetically
Less Than or Equal
Jump on Logically
Greater Than
or Equal
Jump on Logically
Greater Than
Jump on Logically
Less Than or Equal
reg,reg
jdisp
jaddr
jdisp,reg
jaddr,reg
cond,jdisp
cond,jaddr
jdisp,reg
jaddr,reg
SeeJC
See JC
SeeJC
SeeJNC
10
IOPKtt
JGT
JLE
JLGE
JLGT
JLLE
1-8
GA34-0034
See JNC
SeeJC
See JNC
See JNC
SeeJC
Mnemonic
Instruction name
Syntax
JLLT
SeeJC
MB&
MD&
MVA
Jump on Logically
Less Than
Jump on
Arithmetically
Less Than
Jump if Mixed
Jump on Negative
Jump on
Not Condition
Jump on No Carry
Jump on Not Equal
Jump on Not Even
Jump if Not Mixed
Jump on
Not Negative
Jump if Not Off
Jump if Not On
Jump on Not Positive
Jump on Not Zero
Jump if Off
Jump if On
Jump on Positive
Jump on Zero
Level Exit
Load Multiple and
Branch
Multiply Byte
Multiply Doubleword
Move Address
MVB
Move Byte
MVBI
Move Byte
Immediate
Move Byte and Zero
JLT
JMIX
IN
JNC
JNCY
JNE
JNEV
JNMIX
JNN
JNOFF
JNON
JNP
JNZ
JOFF
JON
JP
JZ
LEX
LMB
MVBZ
Ft
SeeJC
SeeJC
SeeJC
cond,jdisp
cond,jaddr
See JNC
See JNC
See JNC
See JNC
See JNC
2
2
SeeJNC
SeeJNC
SeeJNC
See JNC
SeeJC
SeeJC
SeeJC
SeeJC
[ubyte]
addr4
12
7
addr4,reg
addr4,reg
addr4,reg
raddr,addr4
reg,addr4
addr4,reg
addrS ,addr4
byte,reg
26
26
7
8
23
23
17
1
addr4,reg
23
Section 1. Series/1 Processor
1-9
Mnemonic
Instruction name
Syntax
Ft
MVD
Move Doubleword
MVDZ&
Move Doubleword
and Zero
Move Byte Field and
Decrement
Move Byte Field and
Increment
Move Word
reg,addr4&&
addr4,reg&&
addr5,addr4
addr4,reg
24
24
18
24
MVFD
MVFN
MVW
MVWI
MVWS
Move Word
Immediate
Move Word Short
MVWZ
MW&
NOP
NWI
OB
Move Word and Zero
Multiply Word
No Operation
And Word Immediate
OR Byte
OD&
OR Doubleword
OW
OR Word
OWl
OR Word Immediate
PB
Pop Byte
1-10
GA34-0034
(reg) ,(reg)
5
(reg),(reg)
5
reg,reg
reg,addr4
addr4,reg
addr5,addr4
reg,longaddr
longaddr,reg
word,reg
word,addr4
reg,shortaddr
shortaddr4,reg
addr4,reg
addr4,reg
word ,re g[,re g]
reg,addr4
addr4,reg
addr5,addr4&&
reg,addr4
addr4,reg
addr5,addr4
reg,reg
reg,addr4
addr4,reg
addr5,addr4&&
longaddr,reg
word,reg[ ,reg]
word,addr4
addr4,reg
14
23
23
17
13
13
7
8
20
25
23
26
10
15
23
23
17
24
24
18
14
23
23
17
13
15
8
26
Mnemonic
Instruction name
Syntax
Ft
PD
PSB
PSD
PSW
PW
RBTB
Pop Doubleword
Push Byte
Push Doubleword
Push Word
Pop Word
Reset Bits Byte
RBTD&
Reset Bits
Doubleword
RBTW
Reset Bits Word
RBTWI
SA
Reset Bits Word
Immediate
Subtract Address
SB
Subtract Byte
SBTB
Set Bits Byte
SBTD
Set Bits
Doubleword
SBTW
Set Bits Word
SBTWI
Set Bits Word
Immediate
Subtract Carry
Indicator
addr4,reg
reg,addr4
reg,addr4
reg,addr4
addr4,reg
reg,addr4
addr4,reg
addr5,addr4&&
reg,addr4
addr4,reg
addr5,addr4
reg,reg
reg,addr4
addr4,reg
addr5,addr4&&
longaddr,reg
word,reg[ ,reg]
word,addr4
raddr,reg[,reg]
raddr,addr4
reg,addr4
addr4,reg
reg,addr4
addr4,reg
addr5,addr4
reg,addr4
addr4,reg
addr5,addr4
reg,reg
reg,addr4
addr4,reg
addr5,addr4
longaddr,reg
word,reg[,reg]
word,addr4
reg
26
26
26
26
26
23
23
17
24
24
18
14
23
23
17
13
15
8
15
8
23
23
23
23
17
24
24
18
14
23
23
17
13
15
8
14
SCY
Section 1. Series/l Processor
1-11
Mnemonic
Instruction name
Syntax
Ft
SD&
Subtract Doubleword
SEAKR
tt***
SECLK
ttt&
SECMP
ttt
SECON&
Set Address Key
Register
Set Clock
reg,addr4
addr4,reg
addr5,addr4
addr4
reg
reg
24
24
21
11
16
16
Set Comparator
reg
16
Set Console Data
Lights
Set Floating Level
Block
Set Interrupt Mask
Register
Set Indicators
Set Instruction
Space Key
Set Level Block
Set Operand 1 Key
reg
16
reg;addr4
11
addr4
11
reg
addr4
reg
reg,addr4
addr4
reg
addr4
reg
reg,addr4
14
11
16
11
11
16
11
16
11
reg,addr4
11
reg,(reg)
5
reg,(reg)
5
reg,(reg)
5
SEFLB
t&
SEIMR
SEIND
SEISKtt
SELB
SEOOK
tt
SEOTK
tt
SESK
tt**&
SESR
tt***&
SFED
SFEN
SFNED
1-12
Set Operand 2 Key
Set Storage Key
Set Segmentation
Register
Scan Byte Field
Equal and
Decrement
Scan Byte Field
Equal and
Increment
Scan Byte Field
Not Equal and
Decrement
GA34-0034
Mnemonic
Instruction name
Syntax
SFNEN
Scan Byte Field
Not Equal and
Increment
Shift Left Circular
reg,(reg)
5
cnt16,reg
reg,reg&&
cnt31,reg
reg,reg
cnt16,reg
reg,reg
cnt31,reg
reg,reg
reg,reg
reg,reg
6
14
6
14
6
14
6
14
14
14
cnt16,reg
reg,reg&&
cnt31,reg
reg,reg
cnt16,reg
reg,reg&&
cnt31,reg
reg,reg
reg,
addr4[,abcnt]
[ubyte]
ubyte
reg,reg
reg,addr4
addr4,reg
addr5,addr4&&
longaddr,reg
reg,reg
6
14
6
14
6
14
6
14
8
12
12
14
23
23
21
13
14
word,addr4
word,reg[,reg]
(reg,bitdisp)
(reg,bitdisp)
8
15
9
9
SLC
SLCD&
SLL&
SLLD&
SLT&
SLTD&
SRA
SRAD&
SRL
Shift Left Circular
Double
Shift Left Logical
Shift Left Logical
Double
Shift Left and Test
Shift Left and Test
Double
Shift Right
Arithmetic
Shift Right
Arithmetic Double
Shift Right Logical
STM
Shift Right Logical
Double
Store Multiple
STOP
SVC
SW
Stop
Supervisor Call
Subtract Word
SWCY
Subtract Word
With Carry
Subtract Word
Immediate
Test Bit
Test Bit and Reset
SRLD&
SWI
TBT
TBTR
Section 1. Series/l Processor
Ft
1-13
Mnemonic
Instruction name
Syntax
TBTS
TBTV
TWI
Test Bit and Set
Test Bit and Invert
Test Word
Immediate
Invert Register
Exclusive OR Byte
(reg,bitdisp)
(reg,bitdisp)
word,reg
word,addr4
reg[,reg]
reg,addr4
addr4,reg
reg,addr4
addr4,reg
reg,reg
reg,addr4
addr4,reg
longaddr,reg
word,reg[,reg]
VR
XB
XD&
XW
XWI
1-14
Exclusive OR
Doubleword
Exclusive OR Word
Exclusive OR Word
Immediate
GA34-0034
Ft
9
9
15
8
14
23
23
24
24
14
23
23
13
15
Hexadecimal List of Instructions
The hexadecimal equivalent (four digits) for the first
instruction word is shown in the list.
Symbols used in the list are:
(*)
**
***
There are two versions of an instruction: direct
address and indirect address.
This instruction is treated as a NOP by the 4954 and
4956 processo rs.
This instruction is modified for 4-bit mode operation
on the 4956 processor models E and 60E. See IBM
Series/l 4956 Processor Model E (60E) and Processor
Features Description, GA34-0289 (GA34-0293).
#
This instruction applies to the 4956 processor models
E and 60E only. It is intended to be used exclusively
by the operating system, and, therefore, does not
represent an assembler mnemonic. However, it may
be entered in machine code if necessary. See IBM
Series/l 4956 Processor Model E (60E) and Processor
Features Description, GA34-0289 (GA34-0293).
%
@
X
t
tt
ttt
FT
Even hexadecimal digit
Odd hexadecimal digit
Any hexadecimal digit
This instruction applies to the 4950, 4954, 4955, and
4956 processors that have the floating-point feature
installed.
This instruction is not used on the 4953 processor.
This instruction applies to the 4950, 4952, 4954, and
4956 processors only.
The number in the Ff column refers to an instruction
format type. See "Instruction Format Types" in this
section.
Some of the branch and jump instructions have versions of the
assembler syntax that are not shown. See" Assembler
Syntax" in this section for syntax definitions.
Extended mnemonics are not shown in the chart. See the list
on the following page.
Section 1. Series/l Processor
1-15
Instruction
B
BAL
Extended mnemonics
BX
BALX
BC
BCY, BE, BEV, BLE, BLLE, BLLT, BLT,
BMIX, BN, BOFF, BON, BP, BZ
BNER
BGE, BGT, BLGE, BLGT, BNCY, BNE,
BNEV, BNMIX, BNN, BNOFF, BNON,
BNP,BNZ
BER
CPISK, CPO OK, CPOTK
JCY, JE, JEV, JLE, JLLE, JLLT, JLT, JMIX,
IN, JOFF, JON, JP, JZ
JGE, JGT, JLGE, JLGT, JNCY, JNE, JNEV,
JNMIX, JNN, JNOFF, JNON, JNP, JNZ
SEISK, SEOOK, SEOTK
BCC
BNC
BNCC
CPAKR
JC
JNC
SEAKR
1-16
GA34-0034
Hexadecimal digits
Mnemonic
Syntax
FT
0 0-7
0 8-F
X
X
X
X
ABI
MVBI
byte,reg
byte,reg
1
1
1 0-7
1 8-F
X
X
X
X
JC
JNC
condjdisp
condjdisp
2
2
0-3
0-3
0-3
0-3
0-3
0-3
0-3
0-3
0-3
0-3
0-3
0-3
0-3
0-3
0-3
0-3
4-7
4-7
4-7
4-7
4-7
4-7
4-7
4-7
4-7
4-7
4-7
4-7
4-7
4-7
X
X
0
1
FAt
FADt
FSt
FSDt
FMt
FMDt
FDt
FDDt
FMVq
FMVCDt
FMVt
FMVDt
FMVCt
FMVCDt
FMVt
FMVDt
FAt
FADt
FSt
FSDt
FMt
FMDt
FDt·
FDDt
FMVt
FMVDt
FCt
FCDt
invalid
invalid
addr4,freg
addr4,freg
addr4,freg
addr4,freg
addr4,freg
addr4,freg
addr4,freg
addr4,freg
addr4,freg
addr4,freg
addr4,freg
addr4,freg
freg,addr4
freg,addr4
freg,addr4
freg,addr4
freg,freg
freg,freg
freg,freg
freg,freg
freg,freg
freg,freg
freg,freg
freg,freg
freg,freg
freg,freg
freg,freg
freg,freg
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
X
2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
Section 1. Series/l Processor
1-17
Hexadecimal digits
2 4-7
2 4-7
2 8-F
2 8-F
2 8-F
2 8-F
2 8-F
2 8-F
2 8-F
2 8-F
2 8-F
2 8-F
X
X
X
X
X
X
X
X
X
X
X
X
2 8-F X
2 8-F X
2 8-F X
2 8-F X
2 8-F X
2 8-F X
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
1-18
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
8-F X
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
Mnemollic
E
F
invalid
invalid
0
1
MVFD
2
3
CFNEDCFED
MVFN
4
5
6
7
8
invalid
A
SFNED
SFED
FFN
C
D
E
F
C
D
E
F
X
invalid
8
9
A
B
GA34-0034
cnt16,reg
cnt16,reg
cnt16,reg
cnt16,reg
cnt31,reg
cnt31,reg
cnt31,reg
cnt31,reg
cntl6,reg
cnt16,reg
cnt16,reg
cnt16,reg
cnt31,reg
cnt31,reg
cnt31,reg
cnt31,reg
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
(reg),(reg)
(reg),(reg)
(reg),(reg)
(reg),(reg)
(reg),(reg)
reg,(reg)
reg,(reg)
reg,(reg)
reg,(reg)
invalid
SFNEN
SFEN
SLC
SLL
SRL
SRA
SLCD
SLLD
SRLD
SRAD
SLC
SLL
SRL
SRA
SLCD
SLLD
SRLD
SRAD
0
1
2
3
4
5
6
7
reg,(reg)
reg,(reg)
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
(reg),(reg)
invalid
CFNEN
CFEN
FFD
FT
4
invalid
9
B
Sylltax
Mnemonic
Syntax
FT
0
0
MVA
MVWI
addr,addr4
word,addr4
I
2
invalid
invalid
invalid
8
8
8
8
8
raddr4,rcg
word,reg
7
7
Hexadecimal digits
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
0
0
0-7
0-7
0--7
0-7
0-7
0-7
0-7
0-7
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
3
4
4
5
6
7
8
9
9
A
13
C
C
0
E
E
F
F
8-F 0-3 X
8-£0' 4-7 X
8-F 8-13 X
8-F C-F X
5 0
5 0
5 1-7
5 8
5 8-F
MVA
MVWI
invalid
invalid
invalid
STM
AWl
AA
LM13
TWI
OWl
S13nVI
RBTWI
SWI
SA
CWI
CA
T13T
TBTS
TBTR
TBTV
0
0
Nap
X
X
X
X
X
X
0
J
BXS
SEIMR
SESR
1
reg,addr4 [ ,abcnt J
word,addr4
raddr ,addr4
addr4
word,addr4
word,addr4
word,addr4
word,addr4
word,addr4
raddr,addr4
word,addr4
raddr ,addr4
(reg,bitdisp)
(reg,bitdisp)
(reg,bitdisp)
(reg,bitdisp)
jdisp
(reg l -7 ,jdisp)
addr4
reg,addr4
8
8
8
8
8
8
7
8
8
8
8
8
8
8
8
9
9
9
9
10
10
10
11
11
tt***
5
8-B
X
2
SEAKR
addr4
11
reg,addr4
reg,addr4
11
11
11
11
tt*"
5
5
5
5
5
8-F
8-F
8-F
8-F
8-F
X
X
X
X
X
3
4
5
6
7
SEFLBt
SESKtt **
invalid
SELB
invalid
reg,addr4
11
Mnemollic
Syntax
FT
addr4
reg,addr4
II
II
addr4
11
B
C
D
E
F
CPIMR
CPSR
tt***
CPAKR
tt***
CPFLBt
CPSKtt**
CPIPF
CPLB
CPPSR***
reg,addr4
reg,addr4
addr4
reg,addr4
addr4
II
II
II
11
II
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
2
3
4
5
6
7
8
9
9
A
B
C
D
E
F
SVC
LEX
EN***
DIS***
STOP
DIAG
IOPKtt
invalid
BC
BNC
B
BAL
BCC
BNCC
BOV
BNOV
MVW
OW
SBTW'
RBTW
XW
10
MVW
AW
SW
ubyte
[ubytej
ubyte
ubyte
[ubytej
ubyte
cond,longaddr(*)
cond,longaddr( *)
longaddr(*)
longaddr(*),reg
cond,Iongaddr(*)
cond.longaddr(*)
Iongaddr(*)
longaddr(*)
Iongaddr(*),reg
Iongaddr(*),reg
longaddr(*),reg
Iongaddr(*),reg
Iongaddr(*),reg
longaddr(*)
reg,longaddr(* )
Iongaddr(*) ,reg
Iongaddr(*),reg
12
12
12
12
12
12
12
12
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
%
%
%
%
0
1
1
2
RBTW
OW
SBTW
SCY
reg,reg
reg,reg
reg,reg
reg
14
14
14
14
Hexadecimal digits
5
5
8
8-F
?,.
8
9
5
8-B
X
A
5
5
5
5
5
8-F
8-F
8
8-F
8
X
X
X
X
X
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
0
1
2
3
4
5
6
7
8-F
8-F
8
8-F
8-F
8-F
8
8
8-F
8-F
8-F
8-F
8-F
8
8-F
8-F
8-F
7
7
7
7
0-7
0-7
0-7
0
1-20
X
GA34-0034
Hexadecimal digits
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
0--7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0
0-7
0
0
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
8
8
8
8-F
8-F
8-F
8-F
8-F
8-F
8-F
8-F
%
%
%
%
4
5
%
%
7
8
%
9
%
%
%
A
B
C
D
%
%
%
@'
3
6
E
F
0
@
1
@
(a>
2
3
@
@
4
5
@
6
@
7
8
Cal
@
(a")
A
invalid
invalid
invalid
R
C
D
E
@
8
8
8
F
E
E
F
%
0
%
%
%
%
%
%
%
1
I
2
2
3
3
4
Syntax
FT
reg,reg
reg, reg
reg,reg
reg[ ,reg)
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
reg,reg
reg,reg
reg.reg
reg.reg
reg.reg
reg
reg( .reg)
reg
reg
reg.reg
reg.reg
reg.reg
reg,reg
reg.reg
reg.reg
reg.reg
reg.reg
invalid
SLT
Ca'
@
XW
MVW
CW
CMR
IR
AW
AWCY
SW
SWCY
ACY
VR
CPLSR
SEIND
SLC
SLL
SRL
SRA
SLCD
SLLD
SRLD
SRAD
9
@
@
Mllemonic
SLTD
reg.reg
reg,reg
invalid
invalid
ARIBON#
ARIBOFF#
ARIB#
NWI
AWl
AA
SWI
SA
OWl
SBTWI
RBTWI
word .reg ( .reg)
word ,reg ( .reg)
raddr ,reg (.reg)
word.reg( .reg) .
radd r .reg ( ,reg)
word .reg ( .reg I
word .reg ( .reg)
word .reg ( .reg)
Section 1. Series/l Processor
15
15
15
15
15
15
15
15
1-21
Mnemonic
Syntax
FT
7
XWI
TWI
word,reg [ ,reg I
word,reg
15
15
Hexadecimal digits
7 8-F
7 8-F
7 8-F
7 8-F
7 8-F
7 8-F
7 8-F
7 8-F
7 8-F
7 8-F
7 8
7 8-F
7 8-B
%
0
%
%
%
%
%
%
%
%
5
8
9
A
B
C
0
E
F
invalid
invalid
invalid
invalid
invalid
invalid
invalid
invalid
@
@
0
I
invalid
@
2
SECON
SEAKR
reg
reg
15
15
15
15
15
15
15
15
16
16
16
tt···
7
7
7
7
7
7
7
7
7
7
8-F
8
8-F
8
8-F
8-F
8-F
8
8
8-B
7
7
7
7
7
7
7
8-F
8
8-F
8
8-F
8-F
8-F
@
8
8
8
8
8
8
8
8
8
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
X
X
X
X
X
X
X
X
X
1-22
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
3
4
4
5
5
6
7
invalid
SECLKttt reg
invalid
SECMPttt reg
invalid
invalid
invalid
8
9
A
CPCON
CPCL
CPAKR
tt···
B
C
C
0
0
E
F
invalid
0
1
I
2
3
4
5
5
6
GA34-0034
reg
reg
reg
CPCLKttt reg
invalid
CPCMPttt reg
invalid
invalid
invalid
MVB
OB
SBTB
RBTB
CB
MVB
OB
SBTB
RBTB
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addi4
addr5,addr4
addr 5 ,addr4
addr5,addr4
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
17
17
17
17
17
17
17
17
17
Hexadecimal digits
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
8 0-7 X
8 0-7 X
8 0-7 X
8 8-F X
8 8-F X
8
8
8
8
8
8
8
8
8
8
8
8
8
8-F
8-f
8-F
8-f
8-F
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
9
9
9
9
9
9
9
0-7
0-7
0-7
0-7
0-7
0-7
0-7
X
X
X
X
X
X
X
8 8-F
8
8
8
8
8-F
8-F
8-F
8-F
8 8-F
8
8
8
8
8
8
8-f
8-F
8-F
8-F
8-F
8-F
8 8-F
7
8
9
9
A
B
C
0
D
E
f
0
1
1
2
3
4
5
5
6
7
8
9
9
A
B
C
D
D
E
f-
Mnemonic'
Syntax
FT
CB
MVB
OB
SBTB
RBTB
CB
MVB
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
18
18
18
18
18
18
18
08
SBTB
RBTB
CB
MVW
OW
SBTW
RBTW
CW
MVW
OW
SBTW
RBTW
CW
MVW
OW
SBTW
RBTW
CW
MVW
OW
SBTW
RBTW
CW
0
MVO
1
00
1
SBTD
RBTO
CO
MVD
2
3
4
5
aD
Section 1. Series/l Processor
1-23
Hexadecimal digits
Mnemonic
Syntax
FT
SBTD
RBTD
CD
MVD
OD
SBTD
RBTD
CD
MVD
OD
SBTD
RBTD
CD
JAL
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5.addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
jdisp,rcg
18
18
18
18
18
18
18
18
18
18
18
18
18
F
MVWS
AW
SW
AD
SD
AW
SW
AD
SD
AW
SW
AD
SD
AW
SW
AD
SD
reg,shortadd r(*)
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
addr5,addr4
20
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
X
X
JCT
jdisp,rcg
22
MV13
013
addr4,rcg
addr4,rcg
23
23
9
9
9
9
9
9
9
9
9
9
9
9
9
9
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
~-F
X
X
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0-7
8-F
8-F
8-F
8-F
8:-F
8-F
8-F
8-F
8-F
8-F
8-F
8-F
8-F
8-F
8-F
8-F
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B 0-7
B 8-F
X
X
C 0-7
C 0-7
X
X
1-24
5
6
7
8
9
9
A
B
C
D
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
0
I
GA34-0034
19
invalid
Hexadecimal diKits
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0--7
0-7
0-7
0-7
0-7
8-fo
8-F
8-F
8-F
8-F
8-F
8-F
8-F
8-1-'
8-F
8-F
8-F
8-F
8-F
8-F
8-F
8-F
8-F
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
I
2
3
4
D 0-7
D 0-7
D 0-7
X
X
X
0
('
('
C
('
('
('
('
C
('
('
('
('
C
('
C
C
C
('
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
('
5
6
7
8
9
9
A
B
C
D
/Illl(,l1lOliic
Syntax
FT
SBTB
RBTB
XB
CB
MVBZ
AB
SB
l\IVB
OB
SBTB
RBTB
XB
addr4,reg
addr4,reg
addr4,reg
addr4,reg
addr4,reg
addr4,reg
addr4,reg
reg,addr4
reg,addr4
reg,addr4
reg,addr4
reg,addr4
AW
SW
reg,addr4
reg,addr4
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
MVD
aD
SBTD
addr4,reg
addr4,reg
addr4,reg
24
24
24
unused
unused
I
I
2
3
4
AB
SB
MVW
OW
SBTW
RBTW
XW
CW
5
~tVWz
6
AW
SW
MVW
OW
SBTW
RBTW
XW
E
F
0
7
8
9
9
A
B
C
D
E
F
I
I
reg,addr4
reg,addr4
addr4,reg
addr4,reg
addr4,reg
addr4,reg
addr4,reg
addr4,reg
addr4,reg
addr4,reg
addr4,reg
reg,addr4
re.g,addr4
reg,addr4
reg,addr4
reg,addr4
unused
unused
Section 1. Series/1 Processor
1-25
Hexadecimal digits
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
0-7 X
8-F X
E
E
E
E
E
E
E
E
E
E
E
E
E
0-7
8-F
8-F
8-F
8-F
8-F
8-F
8-F
8-F
8-F
8-F
8-F
8-I-'
8-F
8-F
8-F
8-F
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
F 0-7
F 8-F
X
X
E
E
E
E
1-26
2
3
4
5
6
7
8
9
9
A
B
C
D
E
F
X
Mnemollic
Sylltax
FT
RBTD
XD
CD
addr4,reg
addr4,reg
addr4,reg
addr4,reg
addr4,reg
addr4,reg
reg,addr4
reg,addr4
reg,addr4
reg.addr4
reg,addr4
14
24
14
24
14
14
14
24
14
14
14
24
24
14
24
24
~fVDZ
AD
SD
~fVD
OD
SBTD
RBTD
XD
unused
unused
AD
SD
invalid
reg.addr4
reg.addr4
shortaddr( *).rcg
reg.addr4
addr4,reg
addr4.reg
addr4,reg
reg,addr4
addr4.reg
addr4,reg
addr4.reg
reg,addr4
addr4,reg
addr4,reg
addr4,reg
F
MVWS
PSB
MB
DB
PB
PSW
MW
DW
PW
PSD
\tD
DD
PD
invalid
invalid
invalid
invalid
15
26
16
26
26
26
26
26
26
26
26
26
26
26
26
26
26
X
X
CBI
BALS
byte,reg
(reg,jdisp)*
27
28
X
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
GA34-0034
Assembler Syntax
Coding Notes
1.
Data flow, when it modifies a field, is always from left to
right.
2.
Registers used in effective address calculations are always
in parentheses.
3.
An address specification followed by an asterisk indicates
indirec t addressing. Here, the effective address is the
contents of the addressed storage location.
4.
The (reg)+ format indicates that, after use, the contents of
reg are increased by the number of bytes addressed.
Legend for Machine Instruction Operands
abcnt
addr
addr4
An absolute value or expression representing the
size of a work storage area to be allocated by the
Store Multiple (STM) instruction. The value you
code must be an even number in the range 0 to
16382.
An address value. Code an absolute or
relocatable expression in the range 0 to 65535.
An address value that you code in one of the
following forms:
(rego-3 )
The effective address is the
contents of the register
rego- 3 •
(rego- 3)+
The effective address is the
contents of the register
rego- 3• After an instruction
uses it, the contents of the
register are increased by the
number of bytes addressed
by the instruction.
Section 1. Series/1 Processor
1-27
addr
addr*
disp(addr)*
1-28
GA34-0034
The effective address is the
value of addr, unless the
instruction and addr are
within the range of the same
USING statement. If they
are, the assembler computes
the effective address as a
displacement (-32768 to
+32767 or 0 to 65535) from
the base register, which must
be reg l -3 •
The effective address is the
contents of storage at the
address defined by addr,
unless the instruction and
addr are within the domain
and range of the same
USING statement. If they
are, the assembler computes
the effective address as the
contents of storage at the
address defined by a
displacement (0 to 255)
from the base register, which
must be reg l -3•
If the instruction is in the
domain of a USING
directive and the operand is
in the range of the same
USING directive, then the
assembler will compute the
displacement and register
combination which will
reference the requested
location; that is, the resulting
addressing mode will be
displ (reg l - 3 ,disp2)* .
(reg l -3 ,waddr)
The effective address is the
contents of the register
reg l -3 , added to the value of
waddr_
displ (reg l -3,disp2)*
addrS
The effective address is
calculated as follows: The
contents of the register reg l -3
are added to the value of the
displacement disp2 to form
an address. The contents of
that storage location are
added to the value of dispJ
to form the effective
address.
disp(reg l -3 )*
The effective address is the
contents of storage at the
address defined by the
contents of reg H , added to
the value of disp.
(reg l -3 )*
The effective address is the
contents of storage at the
address defined by the
contents of reg l -3• .
(reg l -3,disp) *
The contents of reg l -3 are
added to disp, forming an
address. The contents of
storage at that address form
the effective address.
For byte addressing, the effective address can be
even or odd. For word or double word
addressing, the effective address must be even.
An address value that you code in one of the
following forms:
(reg)
The effective address is the
contents of the register reg.
Section 1. Series/l Processor
1-29
(reg)+
The effective address is the
contents of the register reg.
After an instruction uses it,
the contents of the register
addr
addr*
1-30
GA34-0034
are increased by the number
of bytes addressed by the
instruction.
The effective address is the
value of addr, unless the
instruction and addr are
within the domain and range
of the same USING
statement. If they are, the
assembler computes the
effective address as a
displacement (-32768 to
+32767 or 0 to 65535) from
the base register, which must
be reg l -7•
The effective address is the
contents of storage at the
addressed defined by addr,
unless the instruction and
addr are within the domain
and range of the same
USING statement. If they
are, the assembler computes
the effective address as the
contents of storage at the
address defined by a
displacement (0 to 255)
from the base register, which
must be reg l -7•
If the instruction is in the
disp(addr)*
(regl -7,waddr)
domain of a USING
directive and the operand is
in the range of the same
USING directive, then the
assembler will compute the
displacement and register
combination which will
reference the requested
location; that is, the resulting
addressing mode will be
displ(reg l -7,disp2)*.
The effective address is the
contents of reg l -7 , added to
the value of waddr.
disp 1(reg l -7 ,disp2)*
disp(reg l - 7 )*
The effective address is
calculated as follows: The
contents of the register reg l -7
are added to the value of the
displacement disp2 to form
an address. The contents of
that storage location are
added to the value of dispJ
to form the effective
address.
The effective address is the
contents of storage at the
address defined by the
contents of reg l -7 , added to
the value of disp.
Section 1. Series/1 Processor
1-31
(reg t -7 )*
bitdisp
byte
cnt16
cnt31
cond
disp
freg
1-32
The effective address is the
contents of storage at the
address defined by the
contents of reg l - 7 •
(reg t -7,disp)*
The contents of reg t -7 are
added to disp, forming an
address. The contents of
storage at that address form
the effective address.
For byte addressing, the effective address can be
even or odd. For word or doubleword
addressing, the effective address must be even.
A displacement into a bit field. Code an absolute
value or expression in the range 0-63.
A byte value. Code an absolute value or
expression in the range -128 to +127 or 0 to 255.
A single word (one register) shift count. Code an
absolute value or expression in the range 0-16.
A doubleword (register pair) shift count. Code
an absolute value or expression in the range
0-31.
A condition code value. Code an absolute value
or expression in the range 0-7.
A byte address displacement. Code an absolute
value or expression in the range 0 to 255.
A floating-point register. Code either a
predefined floating register symbol (FRO-FR3)
or a symbol that is equated to the desired register
number (0, 1, 2, or 3). Symbols are equated with
EQUR statements, which must precede the
instruction using the register symbol.
GA34-0034
jaddr
jdisp
longaddr
The address of an instruction that is within the
range -256 to +254 bytes of the byte following a
jump instruction. Code a relocatable expression.
A byte address displacement. Code an even
absolute value or expression in the range -256 to
+254.
An address value that you code in one of the
following forms:
addr
The effective address is the
value of addr, unless the
instruction and addr are
within the domain and range
of the same USING
statement. If they are, the
assembler computes the
effective address as a
displacement (-32768 to
+32767 or 0 to 65535) from
the base register, which must
be reg l -7 •
The effective address is the
addr*
contents of storage at the
address defined by addr,
unless the instruction and
addr are within the domain
and range of the same
USING statement. If they
are, the assembler computes
the effective address as the
contents of storage at the
address defined by a
displacement (-32768 to
+32767 or 0 to 65535) from
the base register, which must
be reg l - 7•
Section 1. Series/! Processor
1-33
(reg l -7 ,waddr)
raddr
reg
rego- 3
reg l -3
1-34
The effective address is the
contents of reg l -7 , added to
the value of waddr.
(reg l -7 ,waddr)*
The contents of the reg l -7 ,
plus waddr, form an address.
The contents of storage at
that location form the
effective address.
(regl -7 )
The effective address is the
contents of the register
reg l -7 •
(reg l -7 )*
The effective address is the
contents of storage at the
address defined by the
contents of reg l -7 •
An address value. Code a relocatable expression
in the range 0 to 65535.
A general-purpose register. Code either a
predefined register symbol (RO-R7) or a symbol
that is equated.to the desired register number (0,
1,2,3,4,5,6, or 7). Symbols are equated with
EQUR statements, which must precede the
instruction using the register symbol.
A general-purpose register. Code either a
predefined register symbol (RO-R3) or a symbol
that is equated to the desired register number (0,
1,2, or 3). Symbols are equated with EQUR
statements, which must precede the instruction
using the register symbol.
A general-purpose register. Code either a
predefined register symbol (R 1-R3) or a symbol
that is equated to the desired register number (1,
2, or 3). Symbols are equated with EQUR
statements, which must precede the instruction
using the register symbol.
GA34-0034
reg l -7
shortaddr
A general-purpose register. Code either a
predefined register symbol (RI-R7) or a symbol
that is equated to the desired register number (1,
2, 3, 4, 5, 6, or 7). Symbols are equated with
EQUR statements, which must precede the
instruction using the register symbol.
An address value that you code in one of the
following forms:
(rego-3, wdisp)
The effective address is the
value of wdisp added to the
contents of reEf-3.
(regO- 3, wdisp)*
The effective address is the
contents of storage at the
address defined by the value
of wdisp added to the
contents of reEf-3.
(rego- 3 )
The effective address is the
contents of (reEf-3).
(rego-3 )*
The effective address is the
contents of storage at the
address defined by the
contents of reEf-3.
addr
To use this form, the
instruction and addr must be
in the domain and range of
the same USING statement.
The assembler computes a
displacement (0-62) and
register combination that
refers to the requested
location.
Section 1. Series/l Processor
1-35
addr*
ubyte
vcon
waddr
wdisp
word
1-36
Same as addr, except the
assembler computes the
effective address as the
contents of storage at the
address defined by a
displacement (0-62) and
register combination.
Note: For addr and addr*, the base register must
be rego· 3 •
An unsigned byte value or mask. Code an
absolute value or expression in the range 0 to
255.
An ordinary symbol that is defined externally
from the current source program.
A one-word address value. Code an absolute or
relocatable expression in the range -32768 to
+32767 or 0 to 65535.
An even byte address displacement. Code an
absolute value or expression in the range 0-62.
A word value. Code an absolute value or
expression in the range -32768 to +32767 or 0 to
65535.
GA34-0034
Instruction Format Types
x
Within instruction word (binary 0 or 1)
Beneath bracket (any hexadecimal digit)
Function field
X
Fun
Type I
I Operation code I
o
0
I
R
Immediate
0 0 X
o
4
5
7
X
/5
~~~~
o
O-F
X
X
Type 2
Operation code
0 0 1 X
Word displi1cement
o
o
4
7 8
5
15
~~~~
1
O-F
X
X
Type 3
I~p~at:on
o
;od;1 0
I
R
456
RB
78
AM IFun
Y 101112
Ip
I
1415
~~~
2
0-3
X
O-F
See note 1 (end of this list).
Section 1. Series/1 Processor
1-37
Type 4
R2
o
4
5
6
7
8
9
1011 12
14 15
~~~~
2
4-7
X
O-F
Type 5
I
Operation code
,0 0
I
0
o
I R1
R2
I,
4
5
7
8
1011 12 13 14 15
~~~~
2
8-F
X
O-F
Type 6
Count
Operation coue
o
0
I
()
I
0
4 5
7 8
'-
O-F
X
()- 7
3
15
12 13
Type 7
I Operation code I
o
I 000
()
4
..-
4
-
R
5
RB
0-7
GA34-0034
--
IFunction
789101112
"-,,-
See note 1 (end of this list).
1-38
AM
X
..-
-
O-F
15
Type 8
IOperation code I
o
1 000
o
I
-
RB
I ?D
AM IFunction
-.---x
4
4
R
5
7 8
In JJ 12
9
0-7
15 16
O-F
31
Immediate
word
See note 2 (end of this list).
Type 9
Bit displacement
Operation code
o
1 001
o
4
5
7
8
9
15
10
Type 10
Word displacement
Operation code
o
1 010
()
,"-,,'_'
4 5
' - ' ..
----
7 8
0-7
5
15
'-',-"'---'--'
x
x
Type II
r KorR
I I I
IOperation code I
o
101
AM
RB
I
---- --
0
4
5
5
7
8-F
8
Function
10 IJ 12
9
X
15
O-F
See note 1 (end of this list).
Section 1. Series/l Processor
1-39
Type 12
IS
~~~~
6
0-7
X
X
Type 13
r
R I, condition, or condition code
O=Direct address, / =Indirect address
~
I~pe;at~on ~o~el
o
4
5
7
I
I
Ix
R2
Address
IS 16
10 II 12
8
I )[]
IFunction
3/
~~~~
6
8-F
X
O-F
Type 14
o
4
5
7
10 II
8
15
~~~~
7
0-7
O-F
X
Type 15
'Immediate
1~~_p_e_;_a_tl_;_n_;_o_d_;-LI~R__/~~~R__2__~I~F~u_n_c_ti_o_n__~~1~5~
o
4
5
7
10 II
8
IS 16
~~~~
7
8-F
I
0,2,4,6,8, A, C, E
1-40
GA34-0034
O-F
31
Type 16
rK or 000
[tEion code
o 1 1 1 1
o
I
4
I
R
5
7
Function
10 11
8
15
~~~~
7
I
8-F
O-F
I, 3, 5, 7, 9, B, D, F
Type 17
Operation code
1 0 0 0 X
()
4
~.,~~~
O-F
8
O-F
X
See note 3 (end of this list).
Type 18
Operation code
10010
o
4
5
7 8
9
10 11 12 13 14 15
~~~~
9
0-7
X
O-F
See note 3 (end of this list).
Type 19
Operation code
100 1
Word displacement
o
15
~~~~
9
8-F
X
X
Section 1. Series/1 Processor
1-41
Type 20
Operation co~e
Io
I
RI
5
7
8
O=Direct address
1=lndirect address
X
Word disp
II
RB
.10100.
4
I
I
10 11
9
I
15
~~~~
A
0-7
X
X
Type 21
Operation code
10101
o
4
5
7
H
IV II 12 IJ 14 15
~
~~~~
A
8-F
X
V-F
See note 3 (end of this list).
Type 22
Operation code
Word displacement
10111
o
4
5
7
8
15
~~~~
B
8-F
X
X
Type 23
O=Storage to register _ _ _ _ _ _ _....,
I
I=Register to storage
Io
Operation code
.1
I
R
RB
AM
1 0 0 X.
4
5
7
8
9
10 II 12 IJ
15
~~~~
C
O-F
See note 1 (end of this list).
1-42
GA34-0034
X
O-F
Type 24
O=Storage to register - - - - - - - - "
I=Register to storage
o
4
5
7 8
9
10 II 1213
15
~~~~
D
0-7
X
O-F
See note 1 (end of this list).
Type 25
()=Direct address
I =llldirect address
Operation code
Io
.1
I
I
I
Rl
RB
I X IWord disp
0 O.
4
7
5
8
10 II
9
15
~~~~
E
X
0-7
X
Type 26
I
Operation code
1 1 101
o
4
I
R
5
RB
I
AM IFunction
789101112
15
~~~~
E
8-F
X
O-F
See note 1 (end of this list).
Type 27
()
4
5
7
15
8
"'-v-/~~~
F
(}··7
X
X
Section 1. Series/l Processor
1-43
Type 28
Word displacement
Operation code
1 1 1 1
1
o
4
15
8
~~~~
F
8-F
X
X
Notes:
1. An addressing mode (AM) word, when required, is
appended to the instruction word in bit positions 16-3l.
2. An addressing mode (AM) word, when required, is
appended to the instruction word in bit positions 16-3l.
The immediate word is then moved to bit positions 32-47.
3. One or two addressing mode (AM) words may be appended
to the instruction word. If one word is appended, bit positions 16- 31 are used. If a second word is also appended,
it appears in bit positions 32-47.
1-44
GA34-0034
Decimal
Hex
Binary
EBCDIC ASCII
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
00
01
02
03
00000000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
00010000
0001
0010
NUL
SOH
STX
ETX
PF
HT
LC
DEL
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
RLF
SMM
VT
FF
CR
SO
SI
OLE
OCt
OC2
NUL
SOH
STX
ETX
EOT
ENQ
ACK
BEL
BS
HT
LF
VT
FF
CR
SO
SI
OLE
0C'l
0('2
Eight bit
data interchange
PTTC/EBCD
PTTC/
Correspondence
NUL
NUL
space
space
1
1,]
2
2
@
space
P (even parity)
P (odd parity)
o (even parity)
o (odd parity)
H (even parity)
3
3
4
5
5
7
6
7
6
8
8
4
Decimal
Hex
Binary
EBCDIC ASC/l
19
20
21
22
23
24
25
26
27
28
29
30
31
13
14
15
16
17
18
19
lA
18
Ie
ID
IE
IF
20
21
22
23
24
25
0011
0100
0101
OlIO
Dill
1000
IDOl
1010
lOll
1100
1101
1110
1111
DOlO 00,00
0001
0010
DOli
DIDO
0101
TM
RES
NL
BS
IL
CAN
EM
CC'
CUI
IFS
IGS
IRS
IUS
DS
SOS
FS
32
33
34
35
36
37
DC'3
DC4
NAK
SYN
ETB
CAN
EM
SUB
ESC'
FS
GS
RS
US
H (odd parity)
( (even parity)
( (odd parity)
!
"
$
':l
PTTC/EBCD
PTTC/
Correspondence
9
0
0
z
@ (EOA)
@ (EOA),9
upper case
upper case
X
8
1\
©
space
+*
BYP
LF
Eight bit
data interchange
EOT
D (even parity)
D (odd parity)
S (even parity)
S (odd parity)
(EOT)
©
(a'
t
I
x
s
n
(EOT)
Decimal
Hex
3H
39
40
41
42
43
44
45
46
47
26
27
48
'"d
a
g
tI.I
tI.I
o....
I
~
-.J
49
50
51
52
53
54
55
56
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
Biliary
0110
01 I I
1000
1001
1010
lOll
1100
1101
I I 10
1111
00110000
0001
0010
0011
0100
0101
OliO
0011 01 I ~
1000
I::BCDIC ASCII
ETB
ESC
Eight bit
data inter·
change
PTTCI
&
,
PTTC/J::BCD
Corrcspolldcllcc
t
u
u
v
e
d
w
k
:\
c
(
)
SM
CU2
ENO
ACK
BEL
*
+
T
.
4
/
0
I
SYN
2
PN
RS
UC
EOT
4
5
6
7
3
8
form feed
form feed
y
I
z
h
(SOA), comma
b
L
®
.....
I
~
00
Decimal
Hex
Binary
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
1001
1010
1011
1100
1101
1110
1111
01000000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
72
73
74
75
EBCDIC ASCII
Eight bit
data interchange
PTTC/EBCD
PTTC/
Correspondence
index
index
9
CU3
DC4
NAK
:
;
<
=
\ (even parity)
\ (odd parity)
< (even parity)
< (odd parity)
>
SUB
space
®
(EOH)
.)
eli;
A
H
C
D
E
-
N ,
EOA
B (even parity)
B (odd parity)
i
" (even parity)
" (odd parity)
k
F
1
!
rn
v
G
¢
H
I
J
K
III
n
R
r
Decimal
Hex
Binary
76
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
1100
1101
1110
1111
0101 0000
0001
0010
0011
0100
0101
77
"C
a
(')
(tI
CIl
CIl
..,o
78
79
80
81
82
.83
84
85
86
87
88
89
90
91
92
93
94
SA
58
5C'
5D
51.::
EBCDIC ASCII
<
(
+
N
I
0
P
&
Q
R
OlIO
0111
1000
1001
1010
1011
1100
1101
1110
L
M
Eight bit
data interchange
line feed
line feed
S
J
*
W
X
Y
Z
*
\
I
)
I
:
.\
PTTC/
Correspondence
0
i
p
a
q
r
s
S
w
eRLJ.'
eRH'
bal:kspal:c
idle
bal:kspal:c
idle
2
T
l'
V
!
S
PTTC/EBCD
Z (even parity)
Z (odd parity)
: (even parity)
: (odd parity)
0
I
VI
o
Decimal
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
III
112
113
Hex Binary
SF
1111
60
01100000
61
0001
62
0010
63
0011
64
0100
65
0101
66
OliO
67
0111
68
1000
69
1001
1010
6A
6B
1011
6C
liOn
6D
1101
6E
1110
61:
III1
70 . 0111 0000
71
0001
EBCDIC
Eight bit
data interchange
PTTC/EBCD
PTTC/
Correspondence
:.J
&
j
b
:.J
<-
ASCII
--,
/
ACK
l:
I:
d
e
"
b
&
f
eo
l:
f
It
d
P
"
I
I
i
j
,
k
%
-
I
III
>
n
.)
V (even parity)
V (odd parity)
6 (even parity)
6 (odd parity)
e
<-
"
f
q
comma
It
I
0
P
q
shift out
Decimol Hex
Binary
114
72
lIS
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
0010
0011
0100
01110101
0110
0111
1000
1001
1010
116
-I
VI
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
lOll
lIDO
1101
1110
1111
10000000
0001
0010
0011
0100
EBCDIC
ASCII
Eight hit
data interchange
r
s
t
N (even parity)
N (odd parity)
. (even parity)
u
. (odd parity)
v
w
PTTC/E'f)CD
PTTC/
Correspondence
i
y
® ,period
-
horiz tab
tab
lower case
lower case
x
:
#
@-
y
z
{
t
}
>
I
=
,..,
"
DEL
a
b
c
d
delctc
SOM
A (even parity)
A (odd parity)
! (even parity)
space
=
space
±, [
<
Ca.
....
I
VI
tv
Decimal
Hex
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
85
86
87
88
89
8A
8B
8e
8D
8E
lSI
",-",
0101
0110
0111
1000
1001
1010
l:.'BCDIC
e
f
g
h
i
lOll
1100
1101
1110
II11
1001 0000
0001
0010
0011
0100
0101
8F
90
91
92
93
94
95
96
97
Binary
.
--
ASCII
l:.'ight hit
data inter.
change
PTTC/
Correspondence
PTTC/l:.'BCD
! (odd parity)
;
#
X-ON
:
%
Q
~f
&
¢
I
>
*
horiztab
horiz tab
*
$
I
I
(
)
m
n
)
)
Z
.i
k
OlIO
0
0111
p-
@ (EOA),"
,'-
(
" ......
,~
-
......
en
(1)
::1.
(1)
CIl
...........
I
VI
Vol
Decimal
Hex
Biliary
EBCDIC ASCII
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
16H
169
170
98
99
9A
9B
9C
9D
9E
9F
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
AA
1000
1001
1010
lOll
1100
1101
1110
11I1
10100000
0001
00 III
0011
q
oH)O
otol
OliO
0111
1000
1001
tolO
Eixht hit
data illterchallxe
PTTC/EBCD
PTTC/
Correspolldellce
upper case
upper case
r
Y (even parity)
Y (odd parity)
9 (even parity)
9 (odd parity)
©
¢
(LOT)
<0
T
,....
WRU (even)
WRL: (oud)
s
t
E
.)
X
(.,
(
S
T
N
U
V
E
1I
v
w
L1
:\
y
z
U (even parity)
D
(EaT)
Decimal
Hex
Biliary
171
172
173
174
175
176
177
All
1011
1100
1101
1110
1111
10110000
0001
In
179
180
132
B3
B4
1011 0011
0100
181
182
183
184
185
186
.187
188
B5
B6
B7
B8
B9
BA
BB
Be
0101
0110
OlIl
1000
1001
1010
1011
1100
.-
....
AC
AD
AE
AF
130
III
HBCDIC
PTTC/HBCD
PTTC/
Correspondence
\V
K
X
C
Y
Z
L
II
U (odd parity)
5 (even parity)
5 (odd parity)
return
l\t (even parity)
M (odd parity)
• (even parity)
nolO
,.
ASCII
Hight hit
data illterchange
- (odd parity)
®
I
--
(SO A), I
index
B
index
""d
"1
oo
~
en
en
o"1
I
VI
VI
Decimal
Hex
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
BD
BE
BF
CO
CI
('2
('3
('4
('5
('6
C'7
Binary
EBCDIC ASCII
1101
1110
IIII
11000000
0001
0010
0011
0100
{
A
B
('
E
G
CA
0111
1000
1001
1010
('13
lOll
('('
(,D
('I:
1100
1101
1110
CF
IIII
C8
PTTC/EBCD
=
®
EOM (even)
EOM (odd)
®
C
J
M
::;:
K
L
V
PTTC/
Correspondence
(EOS)
-
D
OWl
OliO
('9
Eight hit
data interchange
F
H
I
x-orr
J
S (even parity)
S (odd parity)
3 (even parity)
3 (odd parity)
~1
"
N
R
0
I
P
A
Y
I
VI
0\
Decimal
Hex
Binary
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
DO
01
02
03
04
05
06
07
08
09
DA
DB
DC
DO
DE
OF
EO
EI
E2
1101 0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1110 0000
0001
0010
.---...
.... ,
EBCDIC ASCII
J
K
L
M
N
Eight hit
data inter.
change
PTTC/EBCD
PTTC/
Correspondence
}
vertical tab
K (even rarity)
K (odd parity)
+ (even parity)
+ (odd parity)
Q
R
0
S
!
W
[
CRLF
CRLF
:
backspace
idle
backspace
idle
+
J
G
0
P
Q
R
PAD
\
S
bell
G (even parity)
A
.....
I
UI
.....,J
Decimal
Hex
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
E3
E4
E5
E6
E7
E8
E9
EA
E13
EC'
ED
EE
EF
1'0
FI
1-'2
F3
F4
F5
Binary
0011
0100
0101
OlIO
0111
1000
1001
1010
1011
1100
1101
1110
1111
11110000
0001
0010
0011
0100
O)() I
EBCDIC
T
U
V
\V
ASCII
Eight hit
data interchange
G (odd parity)
• (even parity)
, (odd parity)
X
Y
Z
PTTC/EBCD
PTTC/
Correspondence
13
+
C
D
F
P
W
E
7
F
G
Q
comma
shift in (even)
shift in (odd)
\I
.,
0
I
Y
rt
0
I
2
3
4
5
I
I
VI
00
Decimal
246
247
248
249
250
251
252
253
254
255
Hex
F6
F7
F8
F9
FA
FB
FC'
FD
FE
FF
Binary
OlIO
0111
1000
1001
10IO
1011
1100
I IO I
1110
1111
EBCDIC ASCII
6
7
Eight hit
data interchange
PTTC/EBCD
PTTC/
Correspondence
®,
-
-,
H
9
LVM
(even parity)
(odd parity)
'! (even parity)
'! (odd parity)
<=
horiz tab
tab
lower case
lower case
<=
delete
rub out
delete
Class Interrupt Priority
Priority
0
Exception condition
Class interrupt
routine
CPU control check
Machine check
1/0 check
1
Invalid function (Note 1)
2
Privilege violate
3
Invalid function (Notes 2 and 3)
4
Protect check (Note 4)
5
Invalid storage address
Specification check
6
Storage parity
Machine check
7
Power warning
Thermal warning
Power1thermal
warning
8
Supervisor call
Supervisor call
9
Invalid function (Note 5)
10
Floating-point exception
(Notes 3 and 4)
Program check
Soft exception
trap
11
Stack exception
12
Trace
Trace
13
Clock (Note 6)
Clock
14
Console
Console
Notes:
1. Caused by an illegal operation code or function combination.
2.· A Copy Segmentation Register (CPSR) or Set Segmentation
Register (SESR) instruction is attempted and the translator
feature is not installed. The translator feature is not available on the 4953 processor.
3. Not applicable on the 4952 processor
4. Not applicable on the 4953 processor.
5. A floating-point instruction is attempted and the floatingpoint feature is not installed. The floating-point feature is
not available on the 4952 and 4953 processors.
6. Applies to the 4950, 4952, 4954, and 4956 processors only.
Section 1. Series/l Processor
1-59
Control Blocks
Level Status Block
Main storage
address (LSB
pointer)
Instrlll:tion address register
Address key register *
Level status register
Register
()
Register I
Register 2
Register 3
Register 4
Register 5
Register 6
+14 (lie,,)
Register 7
()
* This word
1-60
is zero for the 4953 processor
GA34-0034
15
Stack Control Block
Effectlve a dd ress
- ~o
Stack control block
Top element address (TEA)
r-
Word
High limit address (HLA)
Word
LO\\! limit address (LLA)
Word 2
Stack*
f-
I'. ull stack TEA
'--- Stack element
f - - - - - -'"-. .
Empty
stack TEA
'"
Stack element
The TEA for an empty
stack points to the
same place as the HLA
0
\
15
Stack element shown is 1
word; element can be I,
2, or 4 bytes wide
*The size of the stack (in elements) is equal to HLA- LLA.
Section 1. Series/1 Processor
1-61
Indicators Tested by Conditional Branch and
Jump Instructions
Indicators
tested
01234
Extended mnemonics
COl/d
field
Jump
Branch
.bits*
ECONZ
000
BE, BOFF, BZ
BNE, BNOFF, BNZ
JE, JOFf-, JZ
XXXXI
JNE, JNOFF, JNZ XXXXO
001
BMIX,BP
BNMIX,BNP
JMIX, JP
JNMIX, JNP
XXXOO
XXXXI
XXXIX
010
BN, BON
BNN,BNON
IN,JON
JNN, JNON
XXXIX
XXXOX
011
BEV
BNEV
JEV
JNEV
1XXXX
OXXXX
BLT
JLT
BGE
JGE
XXO 1 X
XX lOX
XX 1 I X
XXOOX
BLE
JLE
BGT
JGT -
BLLE
JLLE
BLGT
JLGT
X1XXX
XXXXI
XOXXO
BCY,BLLT
BLGE,BNCY
JCY, JLLT
JLGE, JNCY
X1XXX
XOXXX
100
XXO 1 X
XX lOX
XXXXI
X XII 0
XXO 0 0
101
110
III
*Bits 5 - 7 of the instruction word for: LSR bit
Branch on Condition (13(,)
o
Branch on Not Condition (BNC)
I
Jump on Condition (J(')
2
Jump on Not Condition (IN(,)
3
X - The indicator is not tested
1-62
GA34-0034
4
Indicaior
E - even
C - carry
0- overflow
N - negative
Z - zero
Registers
Address Key Register (AKR)-Standard*
Bit
o
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Contents
Equate operand spaces
Not used; always 0
Not used; always 0
Not used; always 0
Not used; always 0
Operand-1 key (bit 0)
Operand-1 key (bit 1)
Operand-1 key (bit 2)
Not used; always 0
Operand-2 key (bit 0)
Operand-2 key (bit 1)
Operand-2 key (bit 2)
Not used; always 0
Instruction space key (bit 0)
Instruction space key (bit 1)
Instruction space key (bit 2)
*Not applicable on the 4950 processor, 4953 processor, nor
on the 4956 processor models E and 60E in 4-bit mode
Section 1. Series/1 Processor
1-63
Address Key Register (AKR)-4956 Processor
Models E and 60E (4-Bit Mode)
Bit
o
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Contents
Equate operand spaces
Not used; always 0
Not used; always 0
Not used; always 0
Operand-l key (bit 0)
Operand-l key (bit 1)
Operand-l key (bit 2)
Operand-l key (bit 3)
Operand-2 key (bit 0)
Operand-2 key (bit 1)
Operand-2 key (bit 2)
Operand-2 key (bit 3)
Instruction space key (bit 0)
Instruction space key (bit 1)
Instruction space key (bit 2)
Instruction space key (bit 3)
Address Key Register (AKR)-4950 Processor
(5-Bit Mode)
Bit
o
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1-64
Contents
Equate operand spaces (E.O.S.)
Operand-l key (bit 0)
Operand-2 key (bit 0)
Instruction space key (bit 0)
Operand-l key (bit 1)
Operand-l key (bit 2)
Operand-l key (bit 3)
Operand-l key (bit 4)
Operand-2 key (bit 1)
Operand-2 key (bit 2)
Operand-2 key (bit 3)
Operand-2 key (bit 4)
Instruction space key (bit 1)
Instruction space key (bit 2)
Instruction space key (bit 3)
Instruction space key (bit 4)
GA34-0034
Level Status Register (LSR)
Bit
o
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Contents
Even indicator
Carry indicator
Overflow indicator
Negative result indicator
Zero result indicator
Not used; always 0
Not used; always 0
Not used; always 0
Supervisor state
In process
Trace
Summary mark
Not used; always 0
Not used; always 0
Not used; always 0
Not used; always 0
Mask Register-Interrupt Level
Bit
o
1
2
3
Priority level
0
1
2
3
Note: If a bit position is set to 1, the corresponding level is
allowed to interrupt.
Section 1. Series/l Processor
1-65
Processor Status Word (PSW)
Bit
o
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Contents
Specification check
Invalid storage address
Privilege violate
Protect check·
Invalid function
Floating-point exception··
Stack exception
Not used; always Ot
Storage parity check
Double bit storage error (ECC)·"
Not used; always 0
CPU control check
I/O check
Sequence indicator
Auto-IPL
Translator enabled·
Power/thermal warning
·Not used by the 4953 processor; always 0
··Not used by the 4952 and 4953 processors; always 0
·"Used by the 4956 processor only
tlndicates 4-bit mode enabled on the 4956 processor
models E and 60E
Segmentation Register*
Bit
0-5
6
7-12
13
14
15-31
Meaning
Zeros··
Segment address"·
S-bit··
Segment address·"
Segment address
Valid bit
Read-only bit
Zeros
·Not applicable on the 4953 processor
•• Applies to the 4952 processor only
••• Applies to the 4950, 4954, 4955, and 4956 processors only
1-66
GA34-0034
Reserved Storage Locations
Main storage
address (Hex)
Contents of word
Device FF DDB pointer
022E
-::~
~
~~
0032
Device 01 DDB pointer
0030
002E
002C
002A
Device 00 DDB pointer
Reserved
Reserved
0028
I/O Handler SIA **
I/O LSB pointer**
0026
Clock interrupt SIA *
0024
Clock interrupt LSB pointer*
0022
Soft exception trap SIA
0020
Soft exception trap LSB pointer
001E
Console interrupt SIA
Console interrupt LSB pointer
001C
001A
0018
0016
0014
Trace SIA
Trace LSB pointer
0012
SVC SIA
0010
OOOE
OOOC
SVC LSB pointer
Program check SIA
Program check LSB pointer
OOOA
0008
Machine check SIA
Machine check LSB pointer
0006
Reserved
0004
0002
Reserved
0000
Restart instruction word 1
Power failure SIA
Power failure LSB pointer
Restart instruction word 2
*Applies to the 4950, 4952, 4954, and 4956 processors only.
**Applies to the 4950 processor only.
Section 1. Series/1 Processor
1-67
1-68
GA34-0034
Section 2. Common I/O
Condition Codes 2-2
Device ID Word 2-4
Immediate Device Control Block (lDCB) 2-8
Interrupt ID Word 2-9
Interrupt Status Byte (lSB) 2-10
Section 2. Common I/O
2-1
Condition Codes
110 Instruction Condition Codes
These codes are reported during execution of an Operate I/O
instruction.
Condition
code (CC)
Even
LSR position
Over- Reported
by
Carry flow
0
0
0
0
channel
1
2
0
0
0
1
1
0
device
device
3
0
chan/dev
4
0
5
0
device
chan/de v
0
6
controller
chan/dey
7
2-2
0
GA34-0034
Meaning
Device
not
attached
Busy
Busy
after
reset
Command
reject
Intervention
required
Interface
data
check
Controller
busy
Satisfactory
Interrupt Condition Codes
These condition codes are reported by the device or controller
duri ng priority interrupt acceptance.
Condition
code (CC)
Even
LSR position
Over- Reported
Carry flow
by
0
0
0
0
0
2
3
4
5
6
7
0
0
0
0
0
controller
device
0
1
device
device
0
1
device
device
0
device
device
Meaning
Controller
end
Program
controlled
interrupt
(PCI)
Exception
Device
end
Attention
Attention
and PCI
Attention
and
exception
Attention
and
device
end
Section 2. Common I/O
2-3
Device ID Word
Device ID Word Format
I
II
0
Class
o
Bits 0-3
Bit 4
Bits 5-13
Bit 14
Bit 15
2-4
Assigned code
345
III
1314 15
Assigned class code
Reserved-always zero
Assigned code
Zero--not a cycle-steal device
One--cycle-steal device
Zero--IBM device
One-OEM device
GA34-0034
List of Device ID Words
ID word
(hex)
Device or feature
Communications feature-Asynchronous
Single line
Two line
Four line
Six line
Eight line
Communications feature-BSC
Single line
Two line
Four line
Six line
Eight line
Customer Direct Program Control
Adapter feature
Integrated DI/DO Non-Isolated feature
Digital input
Digital output
Local Communications Controller
Attachment Feature
Multidrop Workstation Attachment
1 Domain
2 Domain
4 Domain
8 Domain
Multifunction attachment feature
Model 1
Model 2
Printer Attachment-5200 Series
1 Domain
2 Domain
4 Domain
8 Domain
lOOE
2lOE
220E
230E
200E
1006
2106
2206
2306
2006
*
COlO
C018
320E
203E
213E
223E
233E
020B
020A
202E
212E
222E
232E
*See IBM Series/l Attachment Features Description,
GA34-0031, for the format of this word.
Section 2. Common I/O
2-5
ID word
Device or feature
Communications feature-Programmable
Multiline Attachment
Two line
Four line
Six line
Eight line
Programmable Two-Channel Switch feature
Communications feature-SDLC
Series/ 1-Personal Computer
Attachment feature
Series/1-System/370 Channel
Attachment feature
Synchronous Communications
Single-Line Control
Teletypewriter Adapter feature
Timer feature
Two Channel Switch feature
4950/5170 Model 495 Disk/Diskette Adapter
4962 Disk Storage Unit
Models 1 and 2
Models IF and 2F
Models 3 and 4
4963 Disk Subsystem
1-2 Devices
3-4 Devices
4964 Diskette Unit
4965 Storage and I/O Expansion Unit
Modell
Models 30D and 60D
4966 Diskette Magazine Unit
4967 High-Performance Disk Subsystem
1-2 Drives
3-4 Drives
2-6
GA34-0034
(hex)
2116
2216
2316
2016
003C
1016
321E
4002
5042
0010
0028
0030
3212
OOAA
OOBA
OOCA
3106
3206
0106
5212
5152
0126
3116
3216
ID word
(hex)
Device or feature
4968 Magnetic Tape Unit
4969 Magnetic Tape Subsystem
1-2 Devices
3-4 Devices
4971/4201 Proprinter
4973 Line Printer
4974 Printer
4978 Display Station Attachment
4979 Display Station
4982 Sensor I/O Unit
AI with multirange amplifier
AI without multirange amplifier
Analog output
Digital output
Isolated DI/PI
Nonisolated DI/PI
Reed relay multiplexer
Solid state multiplexer
4987 Programmable Communications
Subsystem
1-4 Devices
5-8 Devices
9-16 Devices
17 - 3 2 Devices
5250 Information Display System
Attachment
7880 Audio distribution system
0102
3186
3286
0403
0306
0206
040E
0406
8028
8020
8040
8018
8008
8010
8030
8038
221E
231E
241E
251E
0416
2412
Section 2. Common I/O
2-7
Immediate Device Control Block (IDCB)
Command
o
De~'ice
address
7 8
Immediate field
15 16
Hex·
Specific
command
Type of
operation
OX
IX
20
2X
3X
4X
5X
60
6X
6F
7X
7F
FO
Read
Read
ReadID
Read Status
Unused
Write
Write
Prepare
Control
Device Reset
Start
Start Cycle-Steal Status
Halt I/O
DPC
DPC
DPC
DPC
Unused
DPC
DPC
DPC
DPC
DPC
Cycle-Steal
Cycle-Steal
Channel
*The hexadecimal X is a device dependent value other than
the values defined by the system.
2-8
GA34-0034
[J
31
Interrupt ID Word
Device address
lIB
(}
Bits 0-7
Bits 8-15
of
7 8
15
Interrupt information byte (lIB). For interrupt
condition codes 2 and 6, the lIB has a special
format and is called an interrupt status byte
(ISB). For other interrupt condition codes,
implementation of the lIB is device dependent.
Exceptions are:
The lIB is set to zero.
CCO
CC1, CC5
The lIB contains a DCB
identifier.
Bit 0 may be set to one if
CC3, CC7
suppress exception is in
effect.
Device address. This byte contains th e address
the interrupting device.
Section 2. Common 1/0
2-9
Interrupt Status Byte (ISB)
DPC Devices
Bit
~eanmng
o
Device status available
Delayed command reject
Device dependent
Device dependent
Device dependent
Device dependent
Device dependent
Device dependent
1
2
3
4
5
6
7
Cycle-Steal Devices
Bit
~eanmng
1
2
3
4
5
6
7
Device status available
Delayed command reject
Incorrect record length
DCB specification check
Storage data check
Invalid storage address
Protect check*
Interface data check
o
*Zero for a device attached to a 4950, 4952, or 4953
processor
2-10
GA34-0034
Section 3. I/O Devices and Features
Communications Feature-Asynchronous 3-3
Communications Feature-BSC 3-7
Customer Direct Program Control Adapter Feature 3-10
Integrated DI/DO Non-Isolated Feature 3-12
Local Communications ControUer Attachment Feature 3-14
Multidrop Workstation Attachment 3-19
Multifunction Attachment Feature 3-26
Printer Attachment-5200 Series 3-30
Communications Feature-Programmable Multiline
Attachment 3-39
Programmable Two-Channel Switch Feature 3-46
Communications Feature-SDLC 3-48
Series/l- Personal Computer Channel Attachment Feature 3-52
Series/l-System/370 Channel Attachment Feature 3-62
Synchronous Communications Single-Line Control 3-68
Telephone Communications Attachment Feature 3-78
Teletypewriter Adapter Feature 3-82
Timer Feature 3-83
Two Channel Switch Feature 3-84
4950/5170 Model 495-Asynchronous 3-86
4950/5170 Model 495-Disk/Diskette 3-92
4962 Disk Storage Unit 3-97
4963 Disk Subsystem 3-101
4964 Diskette Unit 3-112
4965 Storage and I/O Expansion Unit (Modell) 3-116
4965 Storage and I/O Expansion Unit
(Models 30D and 60D) 3-124
4966 Diskette Magazine Unit 3-134
4967 High-Performance Disk Subsystem 3-142
4968 Magnetic Tape Unit 3-152
4969 Magnetic Tape Subsystem 3-158
Section 3. I/O Devices and Features
3-1
4971/4201 Proprinter 3-165
4973 Line Printer 3-169
4974 Printer 3-173
4975 Printer 3-177
4978 Display Station Attachment 3-182
4979 Display Station 3-186
4982 Sensor I/O Unit 3-189
4987 Programmable Communications Subsystem 3-193
5250 Information Display System Attachment
Feature 3-201
3-2
GA34-0034
Communications Feature-Asynchronous
I/O Commands
Hex
Command
I/O instruction
CCs reported
20
60
6F
70
7C
7D
7E
7F
ReadID
Prepare
Device Reset
Start
Start Control
Start Diagnostic 1
Start Diagnostic 2
Start Cycle-Steal Status
0,1*,2*,5,7
0,1 **,5,7
0,7
0,1,2* ,5,6**,7
0,1,2* ,5,6**,7
0,1,2* ,5,6**,7
0,1,2* ,5,6**,7
0,1,2* ,5,6**,7
*Not reported by the multiple-line attachments
**Not reported by any single-line communications attachment
Device Control Block (DCB)
Word
o
Control word
1
Not used
2 Timer 1
3 Timer 2
4
Not used
5 Chain address-must be even address
6
Byte count
7
Data address
o
15
Section 3. I/O Devices and Features
3-3
Asynchronous
Control Word (DCB Word 0)
Bit
Meaning
Chaining flag
Not used-zero
Input flag-data cycle-steal to storage
Not used-zero
Not used-zero
Cycle-steal address key
Not used-zeros
Operation
000000
Transmit
Transmit end
000001
Transmit allow break
000010
000011
Transmit end allow break
Receive
000100
Receive with time-out
OOOlOl
Receive response
100lO0
Receive response with time-out
lOOlOl
Ring enable
000110
Ring enable with time-out
000111
DTRenable
OOlOOO
DTR enable with time-out
001001
001010
DTR enable with tone/generate
answertone
001011
DTR enable with tone and
time-out/ generate answertone with
time-out
DTR disable
001lO0
001lOl
Set control PTTC
Set control 8-bit interchange
011101
Program delay
001110
Reset
001111
o
1
2
3
4
5-7
8-9
10-15
Cycle-Steal Status Words
Word 0
Bit
0-15
3-4
Meaning
Residual address
GA34-003°4
Asynchronous
Word 1
Bit
0
1
2
3
4
5
6
7
8
9
10-15
Meaning
Overrun
Time-out
Block check error
DCB reject
EOB, count not zero
VRC error
Break detected
Stop-bit error
Not used-zero
Modem interface error
Not used-zeros
Word 2
Bit
0
1
2
3
4
5
6-15
Meaning
Data terminal ready
Data set ready
Request to send
Clear to send
Ring indicator
Receive mode
Not used-zeros
Interrupt Condition Codes Reported
CCO*, CC2, CC3
*Not reported by single-line attachments
Interrupt Information Byte (lIB)
Condition code
0,3
2
DB Contents
Always zeros
Cycle-steal interrupt status byte (ISB)
Section 3. I/O Devices and Features
3-5
Asynchronous
Interrupt Status Byte (ISB)
Bit
o
1
2
3
4
5
6
7
ISB meaning
Device status available
Delayed command reject
Incorrect record length
DeB specification check
Storage data check
Invalid storage address
Protect check*
Interface data check
*Zero for a device attached to a 4952 or 4953 processor
3-6
GA34-0034
Communications Feature-BSC
110 Commands
110 instruction
CCs reported
Hex
Command
20
60
6F
70
7C#
7D#
7E#
7F
FO
Read ID
Prepare
Device Reset
Start
Start Control
Start Diagnostic 1
Start Diagnostic 2
Start Cycle-Steal Status
Halt I/O
0,1 *,2*,5,7
0,1**,5,7
0,7
0,1,2* ,5,6**,7
0,1,2*,5,6**,7
0,1,2* ,5,6**,7
0,1,2*,5,6**,7
0,1,2*,5,6**,7
N/A
# Not supported by the 4950 processor
* Not reported by multiple-line attachments
** Not reported by single-line attachments
Device Control Block (DCB)
Word
o
Control word
Not used
2
3
4
5
6
7
Not used
Not used
Not used
Chain address
Byte count
Data address
o
15
Section 3.
I/O Devices and Features
3-7
BSC
Control Word (DCB Word 0)
Bit
Meaning
o
Chaining flag
Not used-zero
Input flag
Not used-zero
Not used-zero
Cycle-steal address key
Half rate
ASCII mode
Enable terminal (DTR)
Disable terminal (DTR)
Start timer
Transmit operation
Exit transparent
Not used-zero
1
2
3
4
5- 7
8
9*
10
11
12
13
14
15
* Not supported on the 4950 processor
Cycle-Steal Status Words
Word 0
Bit
Meaning
0-15
Residual address
Word 1
Bit
o
1
2
3
4
5*
6
7*
8-15
Meaning
Overrun
Time-out
Modem interface error
Block check error
Multipoint transmit error
Answertone jumper installed
Multipoint tributary jumper installed
Internal clock jumper installed
Multipoint address
*Not used for a device attached to a 4950 processor
3-8
GA34-0034
BSC
Word 2
Bit
o
1
2
3
4
5
6
7
8-15·
~eanrnng
Data terminal ready
Data set ready
Request to send
Clear to send
Ring indicator
Half rate selected
Transmit mode latch
Not used-zero
Indicator panel switch setting
·Not used for a device attached to a 4950 processor
Interrupt Condition Codes Reported
cco·#, CC2, CC3, CC4#, CC6#, CC7#
·Not reported by single-line attachments
#Not reported by the 4950 processor
Interrupt Information Byte (1m)
Condition code
0,3,4,7
2,6
liB Contents
Always zeros
Cycle-steal interrupt status byte (ISB)
Interrupt Status Byte (lSB)
Bit
o
1
2
3
4
5
6
7
ISB meanrnng
Device status available
Delayed command reject
Incorrect record length
DCB specification check
Storage data check
Invalid storage address
Protect check·
Interface data check
·Zero for a device attached to a 4950, 4952, or 4953
processor
Section 3.1/0 Devices and Features
3-9
Customer Direct Program Control Adapter
Feature
I/O Commands
1/0 instruction
Hex
Command
CCs reported
OX
1X
20
2X
2E
Read Data
Read Data
Read ID
Read Status
Read Adapter
Status Word
Read Adapter
Diagnostic Data
Write Data
Write Data
Prepare
Set Diagnostic Mode
Reset Diagnostic Mode
Write Control
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
0,5,7
0,1,2,3,4,5,6,7
0,5,7
2F
4X
5X
60
61
62
6X
0,5,7,
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
0,5,7
0,5,7
0,5,7
0,1,2,3,4,5,6,7
Device Status Word
Bit
~eaEdng
1
2
3
4
5
6
7
8-15
Local diagnostic mode
External diagnostic mode
Output parity error
Input parity error
Parity option selected
Eight device addresses
Four device addresses
Diagnostic interrupt masking
Zeros
o
3-10
GA34-0034
Customer DPC
Interrupt Condition Codes Reported
cco, CC2, CC3, CC4, CC6, CC7
Interrupt Information Byte (lIB)
Condition code
0,3,4,7
2,6
liB contents
Device dependent*
DPC interrupt status byte*
*Device dependent status is defined by the I/O device
designer.
Section 3.1/0 Devices and Features
3-11
Integrated DIlDO Non-Isolated Feature
I/O Commands
Hex
Command
00
01
02
20
21
28
48
60
68
69
69
6A
6B
6B
Read DI
Read PI
Read PI With Reset
Read ID
Read DO
Read Status
Write DO
Prepare
Arm PI
Arm DI External Sync
Arm DO External Sync
Set Test
Set Test 1 (DI/PI)
Set Diagnostic External
Sync (DO)
Disable DO
Device Reset
6C
6F
°
110 instruction
CCs reported
0,1,5,7
0,5,7
0,1,5,7
0,5,7
0,5,7
0,5,7
0,1,5,7
0,5,7
0,1,5,7
0,1,5,7
0,1,5,7
0,1,5,7
0,1,5,7
0,1,5,7
0,1,5,7
0,7
Device Status Word
DI Status Word
Bit
~eaEdng
0, 1
2
3
4
5
6, 7
8-15
Zero
PI mode is armed
External sync mode is armed
Set-test-1 mode is set
Set-test-O mode is set
Interrupt state
Zero
3-12
GA34-0034
DIlDO
DO Status Word
Bit
0, 1
2
3
4
5
6, 7
8-15
~ean[ng
Zero
Disable mode is set
External sync mode is armed
Diagnostic external sync was set
Zero
Interrupt state
Zero
Interrupt Condition Codes Reported
CC4
Interrupt Information Byte (lIB)
DIGroup
Condition code
4
lIB contents
Same as bits 0-7 of the DI status word
DO Group
Condition code
4
lIB contents
Same as bits 0- 7 of the DO status word
Section 3.1/0 Devices and Features
3-13
Local Communications Controller Attachment
Feature
I/O Commands
1/0 instruction
Hex
Command
CCs reported
20
40
41
42
43
44
45
46
60
6F
Read ID
Initiate Diagnose
Set Bypass
Reset Bypass
Clear Ring
IPL Request
Disable Frame Capture
Enable Frame Capture
Prepare
Device Reset
0,5,7
0,1,2,3,5,6,7
0,1,2,3,5,6,7
0,1,2,3,5,6,7
0,1,2,3,5,6,7
0,1,2,3,5,6,7
0,1,2,3,5,6,7
0,1,2,3,5,6,7
0,5,7
0,7
Device Control Block (DCB)
Word
o
DCB control word
1
Ring address
2
Attachment micro controller
storage address
3 DCBID
I
Reserved
I Reserved
4 Status address
5
Chain address
6 Data byte count
7 Data address
o
3-14
GA34-0034
15
Local Communications
Control Word (DCB Word 0)
Bit
Meaning
o
Chaining flag
Program-controlled interrupt (PCI)
Input flag
Extended DCB (XD)
Suppress exception
Cycle-steal address key
RAS diagnostic monitor mode
Reserved
Modifier bits
Burst mode (not supported, always 0)
1
2
3
4
5-7
8
9
10-14
15
Cycle-Steal Status Words
Word 0
Bit
0-15
MeanUng
Residual address
Word 1
Bit
0-15
MeanUng
Residual count
Word 2
Bit
0-15
Meaning
Start cycle-steal device status
Word 3
Bit
MeanUng
0-15
Hardware status
Section 3. I/O Devices and Features
3-15
Local Communications
Word 4
~eaning
Bit
0-15
Frame byte count
Word 5
Word 5 is the DCB address contained in the IDCB.
Word 6
Word 6 contains the subchannel current DCB address.
Words 7-14
These words contain the current DCB.
Residual Status Block (RSB)
Word 0
~eaning
Bit
0-15
Residual count
Word 1
Bit
~eaning
o
End of chain
Not used-zeros
No exception
1-14
15
Word 2
Bit
0-15
3-16
~eaning
Residual address
GA34-0034
Local Communications
Word]
Bit
~eanrnng
0-7
8-15
Ring address (word 1 of DCB)
DCB byte 0 (bits 0-7 of current DCB control word)
Word 4
Bit
~eaning
0-15
Data address (word 7 of DCB)
Interrupt Condition Codes Reported
CCO, CC1, CC2, CC3, CC4
Interrupt Information Byte (lIB)
Condition code
o
1
2
3
4
5-7
liB contents
Zeros
DCB identifier
Cycle-steal interrupt status byte (ISB)
Bit 0 may be set to 1 if suppress
exception is in effect
Bit
Meanrnng
0-4
Not used
5
Cable open/short condition
detected
Accumulator error overflow
6
Set IPL frame was received
7
and the ring remote IPL
jumper is not installed
Not used
Section 3. I/O Devices and Features
3-17
Local Communications
Interrupt Status Byte (ISB)
Bit
o
1
2
3
4
5
6
7
3-18
ISB meaning
Device-dependent status available
Delayed command reject
Incorrect-length record
DCB specification check
Storage data check
Invalid storage address
Protect check
Interface data check
GA34-0034
Multidrop Workstation Attachment
110 Commands
Hex
Command
I/O instruction
CCs reported
20
60
6F
70-73
7C
7F
Read ID
Prepare
Device Reset
Start
Start Control
Start Cycle-Steal Status
0,3,5,7
0,3,5,7
0,3,7
0,1,2,3,5,6,7
0,1,2,3,5,6,7
0,1,2,3,5,6,7
Device Control Block (DCB)-General Format
Word
o
Control word
1
Operation dependent parameters
2
Operation dependent parameters
3
Opera tion dependent parameters
4
Operation dependent parameters
5
DCB chain address
6
Byte count
7
Data address
o
15
Section 3. I/O Devices and Features
3-19
Multidrop Workstation
Device Control Block (DCB)-Start Control
Command
Word
o x
0 X 0
o
I KEY I
1
Operation dependent parameters
2
Operation dependent parameters
3
Operation dependent parameters
4
Operation dependent parameters
5
DeB chain address
6
Byte count
7
Data address
o
3-20
GA34-0034
Operation
15
Multidrop Workstation
Control Word (DCB Word O}-Start Control
Command
Bit
o
1
2
3,4
5- 7
8-15
~eanUng
Chaining flag
Set to 0
Input flag
Set to 0
Cycle-steal address key
Attachment control operation:
10100000
Enable options
10100001
Disable options
10110000
Read error log
Read error log and clear
10110001
11010000
Start diagnostic 0
Initialize attachment
11100010*
Read attachment storage
11100100
Load attachment storage
11101000
11101010*
Load attachment storage and
initialize
11101100*
Execute attachment storage
11101110
Write device definition data
11110010
Clear attachment storage
11111101
Read attachment definition
11111110
Read device definition data
11111111
Start cycle-steal read ID
*Chaining not supported
Cycle-Steal Status Words
Word O-Residual Address
Bit
~eanUng
0-15
Address of last-attempted data transfer
Section 3. I/O Devices and Features
3-21
Multidrop Workstation
Words 1-2
Device dependent. See device description manual.
Word 3-Attachment Status
Bit
~eanWng
1
2
3
4
5- 7
8-11
12
13
14
15
Initialized
Attachment storage checksum error
Device defined
Storage incompatibility error
Device ready
Residual address key
Not used-zeros
Attachment hardware error
Read-only storage checksum error
Attachment storage data error
Not used
o
Word 4-Device ID
Hex 0402 for 4980
Hex FFFF for Null
WordS
Not used
Words 6-7
Device dependent. See device description manual.
3-22
GA34-0034
Multidrop Workstation
Word 8-Device Definition Errors
Bit
o
1
2
3
4
5
6-15
Meaning
Invalid device ID
Invalid line speed
Invalid port address
Device station address conflict. The device station
address is assigned to another device on the same
port.
Line speed conflict. A different line speed is
assigned to another device on the same port.
Invalid device station address
Not used
Word 9-Software Recoverable Error
Bit
Meaning
o
Invalid operation from the attachment. The device
does not recognize the operation from the
attachment. The invalid operation is stored in word
11.
Incorrect operation from the attachment. The device
received an operation that was not allowed or was
out of sequence.
Not used
2-15
Section 3.1/0 Devices and Features
3-23
Multidrop Workstation
Word IO-Software Unrecoverable Error
Bit
o
1
2
3-5
6
7
8
9
10
11
12-15
Meaning
Invalid operation from the device. The invalid
operation is stored in word 11.
Incorrect operation from the device
Data security violation
Not used
Device power-on-reset failure. The POR diagnostic
word received from the device is in word 11.
Device disconnect/failure. The device is incorrectly
responding to orders. It is either disconnected,
powered-off, or has a hardware failure.
Not used
Receive error. The attachment ends the operation
with an exception interrupt due to unrecoverable
receive errors such as frame check sequence, end
operation, and overrun.
Frame reject. The device received invalid frames
from the attachment.
Transmit error. The attachment ends the operation
with an exception interrupt due to unconfirmed
transmit errors.
Not used
Word II-Diagnostic/Failing Order
This word contains one of the following:
Invalid order from attachment (if word 9 bit 0 is set to 1)
Invalid order from the device (if word 10 bit 0 is set to 1)
Power-on-reset diagnostic word (if word 10 bit 6 is set to
1).
3-24
GA34-0034
Multidrop Workstation
Word 12-Device Read-Only Storage Level
A hexadecimal number in the device read-only storage that
defines the device read-only storage compatibility with the
storage load residing on the device diskette.
Word 13
Device dependent
Interrupt Condition Codes Reported
cco, CC2, CC3, CC4
Interrupt Information Byte (lIB)
Condition code
o
2
3
4
lIB contents
Hex FF-Request to Read Attachment
Error Log Interrupt
Cycle-steal interrupt status byte (ISB)
Always zero
Key interrupt codes
Interrupt Status Byte (ISB)
Bit
o
1
2
3
4
5
6
7
ISB meaning
Device dependent status available
Delayed command reject
Incorrect length record
DCB specification check
Storage data check
Invalid storage check
Protect check
Interface data check
Section 3.1/0 Devices and Features
3-25
Multifunction Attachment Feature
I/O Commands
Hex
Command
20
60
6P
70*
7C
7P*
ReadID
Prepare
Device Reset
Start
Start Control
Start Cycle-Steal Status
*4975 Printer command
Device Control Block (DCB)
Word
o
Control word
1 Start address
2 Not used
3 Not used
4 Not used
5 Chain address
6 Byte count
7 Da ta address
3-26
GA34-0034
Multifunction
Control Word (DCB Word 0)
Bit
Meaning
o
Chaining flag*
Reserved
Input flag
Reserved
Reserved
Cycle-steal address key
Attachment-directed operation
FF
Start cycle-steal read ID
FD
Start cycle-steal attachment status
EC
Execute attachment storage
E8
Load attachment storage
E2
Initialize attachment
EA
Load attachment storage and initialize
E4
Read attachment storage
DO
Start diagnostic
1
2
3
4
5-7
8-15
*Chaining is supported for all Start Control commands except
Start Diagnostic (DO). See start CS attachment status.
Cycle-Steal Status Words*
Word O-Residual Address
Bit
0-15
Meaning
Address of last-attempted data transfer
*Listed for the Multifunction Attachment Feature when used
with Asynchronous/Synchronous Communications. See also
cycle-steal status words for the 4975 Printer and Binary
Synchronous Communications.
Section 3. I/O Devices and Features
3-27
Multifunction
Wordl
Bit
~eanWng
o
Overrun error
Time-out
Not used
DCB reject
Not used
Communications error
Break
Communications error
Not used
Communications interface error
Not used
Not used
Not used
Not used
Not used
Not used
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Word 2
Bit .
~eanWng
o
Data terminal read (DTR)
Data set read (DSR)
Request to send (RTS)
Clear to send (CTS)
Not used
Not used
Echoplex
Receive data lead (when set to 1 = space state)
Communications panel switch settings
1
2
3
4
5
6
7
8 -15
3-28
GA34-0034
Multifunction
Interrupt Status Byte (ISB)
Bit
ISB meaning
o
Device-dependent status available
Delayed command reject
Incorrect-length record
DeB specification check
Storage data check
Invalid storage address
Protect check
Interface data check
1
2
3
4
5
6
7
Section 3. I/O Devices and Features
3-29
Printer Attachment-5200 Series
I/O Commands
Hex
Command
I/O instruction
CCs reported
20
60
6F
70
7C
7F
ReadlD
Prepare
Device Reset
Start I/O
Start Control
Start Cycle-Steal Status
0,3,5,7
0,3,5,7
0,3,7
0,1,2,3,5,6,7
0,1,2,3,5,6,7
0,1,2,3,5,6,7
Device Control Block (DCB}-Data Stream Mode
Word
o
Control word
1
Not used (O's)
2
Not used (O's)
3
Mode control
4
Not used (O's)
5
Chain address
6
Byte count
7
Data address
o
1-10
I
Not used (O's)
7 8
GA14-0014
15
5200 Series
Control Word (DCB Word 0)
Bit
Meaning
o
Chaining flag
Not used
Input flag
Not used
Cycle-steal address key
Print complete attention interrupt
Not used
Data transfer mode
Not used
1
2
3,4
5-7
8
9-12
13
14, 15
~p('tinn
1 T/0 Devices and Features
3-31
5200 Series
Device Control Block (DCB)-Emulation Mode
Word
o
Control word
1
Forms length
Not used (O's)
2
Skip modifier
Space modifier
3
Mode control
Not used (O's)
4
Character set selection
Not used (O's)
5
Chain address
6
Byte count
7
Data address
o
7 8
Control Word (DCB Word 0)
Bit
~ean[ng
o
Chaining flag
Not used
Input flag
Not used
Cycle-steal address key
Forms parameter
Not used
Forms spacing control
Data transfer mode
Use words 3 and 4
Not used
1
2
3,4
5-7
8
9-11
12
13
14
15
3-32
GA34-0034
15
5200 Series
Device Control Block (DCB)-Start Control
Command
Word
o
Control word
1
Attachment storage start address/summary mask
2
Not used
3
Not used
4
Not used
5
Chain address
6
Byte count
7
Data address
o
15
Section 3. I/O Devices and Features
3-33
5200 Series
Control Word (DCB Word 0)
Bit
o
1
2
3,4
5- 7
8 -15
3-34
Meaning
Chaining flag
Not used
Input flag
Not used
Cycle-steal address key
Attachment control operation:
Start Cycle-Steal Read ID
11111111
11111110
Read Device Definition Data
11111101
Read Attachment Definition
11110010
Clear Attachment Storage
11101100
Execute Attachment Storage
Load Attachment Storage
11101000
11101010
Load Attachment Storage and
Intialize
11101110
Write Device Definition Data
11100100
Read Attachment Storage
Initialize Attachment
11100010
11010000
Start Diagnostic 0
Enable Options
10100000
Disable Options
10100001
Read Error Log
10110000
10110001
Read Error Log and Clear
GA34-0034
5200 Series
Cycle-Steal Status Words
Word O-Residual Address
Bit
Meaning
0-15
Address of last-attempted data transfer (security
mode only)
Word I-Program Status
Bit
o
1
2
3
4-7
8
9-11
12
13-15
Meaning
Not ready
Device error
Not used
Wait
Not used
Communications error
Not used
End of forms or forms jam
Not used
Word 2-Printer Status/Printer Return Code·
Bit
o
1
2
3-7
8-15
Meaning
Mode
Status available (bits 8-15)
Debug/security mode
Not used
Printer return code·
·See IBM Series/l Printer Attachment-5200 Series
Description, GA34-0240.
Section 3.1/0 Devices and Features
3-35
5200 Series
Word 3-Attachment Status
Bit
~eaning
o
Initialized
Attachment storage checksum error
Device defined
Storage incompatibility error
Device ready
Residual key
Not used
Attachment hardware error
Attachment read-only-storage checksum error
Attachment storage data error detected
Not used
1
2
3
4
5- 7
8-11
12
13
14
15
Word 4-Printer ID
Bit
0-7
8-15
~eaning
Defined printer ID
Hardware printer ID
Word 5-Forms Length/Line Density
Bit
0-7
8 -15
~eaning
Forms length-Emulation Mode
Line density-Emulation Mode
Hex
~eaning
09
8 LPI
OC
6 LPI
In Data Stream mode, Status Word 5 is not used.
3-36
GA34-0034
5200 Series
Word 6-Character Demity/ Character Set
Bit
~eanrnng
0- 7
Character density-Emulation Mode
Hex
~eanrnng
OA
10 CPI
OF
15 CPI
Character set-Emulation Mode
~eanrnng
Hex
0
International
1
United States/Canada
2
Austria/ Germany
Belgium
3
4
Brazil
French Canadian
5
Denmark/Norway
6
Finland/Sweden
7
France
8
Italy
9
Japan
A
B
Katakana
Portugal
C
Spain
D
Spanish speaking
E
F
United Kingdom
8-15
In Data Stream mode, Status Word 6 is not used.
Section 3.1/0 Devices and Features
3-37
5200 Series
Word 7
Not used
Interrupt Condition Codes Reported
cco, CC2, CC3, CC4, CC7
Interrupt Information Byte (lIB)
Condition code
o
2
3
4
lIB contents
FF (hex), Request to Read Attachment
Error Log Interrupt
Cycle-steal interrupt status byte (ISB)
Always zero
A printer return code
Interrupt Status Byte (lSB)
Bit
o
1
2
3
4
5
6
7
3-38
ISB meaning
Device dependent status available
Delayed command reject
Not used
DCB specification check
Storage data check
Invalid storage
Protect check
Interface data check
GA34-0034
Communications Feature-Programmable
Multiline Attachment
110 Commands
Hex
Command
I/O instruction
CCs reported
20
50
60
6F
70
7C
7D
7E
7F
Read ID
Write Data
Prepare
Device Reset
Start
Start Control
Start Diagnostic 1
Start Diagnostic 2
Start Cycle-Steal Status
0,5,7
0,1,5,6,7
0,1,5,7
0,7
0,1,5,6,7
0,1,5,6,7
0,1,5,6,7
0,1,5,6,7
0,1,5,6,7
Device Control Block (DCB)-General Format
Word
o
Control word
1
Not used
2
Timer 1
3
Timer 2*
4
Not used
5
Chain address-must be even address
6
Byte count
7
Da ta address
I
Not used
o
15
*Dual function word. In transmit, it contains Timer 2 and PCI
information. In receive, it contains only PCI information.
Section 3. I/O Devices and Features
3-39
Multiline
Device Control Block (DCB)-Set Mode and Set
Control (Asynchronous)
Word
o
Control word
1
Bit rate constant
Line control character
2
Line control character
Line control character
3
Line control character
Line control character
4
Line control character
Line control character
5
Chain address
6
Byte count
7
Data address
o
3-40
7 8
GA34-0034
15
Multiline
Device Control Block (DCB)-Set Mode
(Synchronous)
Word
o
Control word
1
Bit rate constant
Line control character
2
Line control character
Line control character
3
Line control character
Line control character
4
Line control character
Line control character
5
Chain address
6
Quantity of synchronization characters (1 or 2)
7
Address of synchronization character
o
7 8
Section 3. I/O Devices and Features
15
3-41
Multiline
Control Word (DCB Word 0)
Bit
Meaning
o
Chaining flag
Program-controlled interrupt
Input flag
Not used-zeros
Cycle-steal address key
Operation
00000000
Transmit
00000001
Transmit end
00010001
Transmit end with pre-receive
00000010
Transmit allow break
00000011
Transmit end allow break
Transmit end allow break with
00010011
pre-receive
Receive
00000100
00000101
Receive with time-out
00010100
Receive with block check character
00010101
Receive with time-out and block
check character
Receive with echo-plex
00100100
00100101
Receive with time-out and echo-plex
00110100
Receive with echo-plex and block
check character
Receive with echo-plex, time-out,
00110101
and block check character
Receive transparent
01000100
Receive transparent with timer
01000101
01100100
Receive transparent with echo-plex
01100101
Receive transparent with echo-plex
and timer
Read adapter buffer
01110100
Ring monitor
00000110
Ring monitor with time-out
00000111
Data terminal ready (DTR) enable
00001000
00001001
DTR enable with time-out
DTR enable with answertone
00001010
00001011
DTR enable with answertone and
time-out
1
2
3,4
5-7
8-15
3-42
GA34-0034
Multiline
00001100
00011101
00001110
00001111
00001101
DTRdisable
Set control*
Program delay
Reset
Not supported. If issued, ISB bit 3
(DeB specification check) is set
equal to 1.
*The attachment is placed in asynchronous mode with 8 data
bits, no parity, and 2 stop bits.
'
Section 3. I/O Devices and Features
3-43
Multiline
Cycle-Steal Status Words
Word 0
~eaning
Bit
0-15
Residual address
Wordl
Bit
~eaning
o
Overrun
1
Time-out
2
Not used
DCB reject
3
4
Not used
Parity error detected on receive
5
Break
6
Stop bit error
7
Not used
8
Modem interface error
9
10,11 Not used-zeros
12
Error during pre-receive
13-14 Not used-zeros
15
Adapter buffer status
Word 2
Bit
~eaning
o
Data terminal ready
Data set ready
Request to send
Clear to send
External clocks
Data carrier detect
Echo-plex
Receive data lead (when set to 1, equals the mark
state)
Indicator panel setting
1
2
3
4
5
6
7
8-15
3-44
GA34-0034
Multiline
Interrupt Condition Codes Reported
cco, CCI, CC2, CC3
Interrupt Information Byte (lIB)
Condition code
0,3
1
2
lIB contents
Always zeros
Program-controlled interrupt identifier
Cycle-steal interrupt status byte (ISB)
Interrupt Status Byte (ISB)
Bit
°
I
2
3
4
5
6
7
ISB meaning
Device status available
Delayed command reject
Incorrect record length
DCB specification check
Storage data check
Invalid storage address
Protect check*
Interface data check
*Zero for a device attached to a 4952 or 4953 processor
Section 3. I/O Devices and Features
3-45
Programmable Two-Channel Switch Feature
110 Commands
Hex
Command
20
21
60
6F
Read Device ID
Read Device Status
Word
Read Sync Word
Read Diagnostic Wrap
Word
Write Common I/O
Release
Write Request
Connection
Write Sync Word
Write Resume
System Reset to
CommonI/O
Write Console Ack
Write Emergency
Release
Write Emergency
Connect Enable
Write Emergency
Connect
Write Diagnostic Sync
Word
Block Operate I/O to
CommonI/O
Write Diagnostic Wrap
Word
Prepare
Device Reset
3-46
GA34-0034
22
23
40
41
42
43
44
4F
50
51
52
53
54
5F
I/O instruction
CCs reported
0,7
0,7
0,7
0,7
0,3,4,7
0,3,4,7
0,5,7
0,3,4,7
0,3,7
0,5,7
0,3,4,7
0,3,4,7
0,3,4,7
0,3,5,7
0,3,7
0,5,7
0,5,7
0,7
PTCS
Device Status Word
Bit
~eanWng
o
Configuration information
Status of switch
Program/manual mode
IPL from remote source
System reset from remote system
IPL designation
Request for connection received and pending
Request for connection interrupt pending
Request for connection received and pending
Service mode
Block operate I/O mode
Reserved
1, 2
3
4
5
6-9
10
11
12
13
14
15
Interrupt Condition Codes Reported
CC4
Interrupt Information Byte (lIB)
Condition code
4
lIB contents
Write sync word command
Bit 0
Bit 1
Read sync word command
Bit 2
Write diagnostic sync word
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
command
Write request connection
command
Write common I/O release
Write emergency connect
command
Write emergency release
command
IPL, system reset, or input
from console received
Section 3. I/O Devices and Features
3-47
Communications Feature-SDLC
I/O Commands
Hex
Command
110 instruction
CCs reported
20
60
6F
70
7D#
7E#
7F
FO
Read ID
Prepare
Device Reset
Start
Start Diagnostic 1
Start Diagnostic 2
Start Cycle-Steal Status
Halt I/O
0,1,2,5,7
0,5,7
0,7
0,1,2,5,6,7
0,1,2,5,6,7
0,1,2,5,6,7
0,1,2,5,6,7
N/A
#Not supported by the 4950 processor
Device Control Block (DCB)
Word
(J
Control word
Timer I
I Timer 2
Not used (zeros)
Not used (zeros)
..;
Status address
5
Chain address
Byte count
Data address
15
II
3-48
GA34-0034
SDLe
Control Word (DCB Word 0)
Bit
~eanWng
o
Chaining flag
Not used-zero
Input flag
Not used-zero
Suppress exception (SE)
Cycle-steal address key
Half rate
NRZI coding
Enable terminal
Disable terminal
Pad (leading)
Secondary/primary
Transmit operation
Hold line active (HLA)
1
2
3
4
5- 7
8
9
10
11
12
13
14
15
Cycle-Steal Status Words
Word 0
Bit
~eanWng
0-15
Residual address
Word 1
Bit
~eanWng
0-15
Residual byte count
Section 3. I/O Devices and Features
3-49
SDLC
Word 2
Bit
~eanrnng
o
Overrun
Abort
Long frame
Block check error
Time-out
Idle detected
Modem interface error
Not used-zeros
Business machine clock selected
Answertone jumper installed
Modem delay jumper installed
1
2
3
4
5
7
8 -12
13
14
15
Word 3
Bit
~eanrnng
1
2
3
4
5
6
7
8-15
Data terminal ready
Data set ready
Request to send
Clear to send
Ring indicator
Half rate selected
Transmit mode latch
Not used-zero
Secondary station address
o
Residual Status Block (RSB)
Word 0
Bit
~eanrnng
0-15
Residual byte count
3-50
GA34-0034
SDLC
Wordl
Bit
o
1-7
8
9
10
11
12-14
15
Meaning
End of chain (EOC)
Not used-zero
Overrun
Abort
Long frame
Block check error
Not used-zero
No exception (NE)
Interrupt Condition Codes Reported
CC2, CC3, CC4#, CC6#, CC7
# Not reported by the 4950 processor
Interrupt Information Byte (lIB)
Condition code
2,6
3
4, 7
lIB contents
Cycle-steal interrupt status byte
Bit 0 suppressed exception;
bits 1-7 are zeros
Always zeros
Interrupt Status Byte (ISB)
Bit
o
1
2
3
4
5
6
7
ISB meaning
Device status available
Delayed command reject
Incorrect (ecord length
DCB specification check
Storage data check
Invalid storage address
Protect check*
Interface data check
*Zero for a device attached to a 4950, 4952, or 4953
processor
Section 3. I/O Devices and Features
3-51
Series/1 to PC Attachment
110 Commands
Hex
Command
I/O instruction
CCs reported
20
43*
44*
60
6F
70*
71*
7C
7D#
7F
FO
Read ID
Clear Interface
IPL Request
Prepare
Device Reset
Start Write
Start Read
Start Control Store
Start Diagnostics
Start Cycle Steal Status
Halt I/O
0,7
0,1,2,5,6,7
0,1,2,5,6,7
0,5,7
0,7
0,1,2,5,6,7
0,1,2,5,6,7
0,1,2,5,6,7
0,1,2,5,6,7
0,1,2,5,6,7
N/A
* Used only under loaded microcode control
# Used only under ROS control
Device Control Block (DCB) for the Start Control
Store Command (Hex 7 C)
Word
o
DeB control word
Attachment storage start address
2 Operation dependent information
3 Not useod (O's)
4 Not used (O's)
5 Chain address
6 Data byte count
7 Data address
o
3-52
15
GA34-0034
Series/1 to PC
Control Word (DCB Word 0) for the Start Control
Store Command (Hex 7 C)
Bit
o
1
2
3-4
5- 7
8-15
Meaning
Chaining flag
Not Used (0)
Input flag
Not Used (0)
Cycle-steal address key
Attachment Control Operation
Hex
Attachment Control Operation
E8
Load Attachment Storage
E2
Initialize Attachment
EA
Load Attachment Storage
And Initialize
FO
Read Attachment Definition
E4
Read Attachment Storage
F2
Clear Attachment Storage
DO*
Start Diagnostic 0
* Used under ROS control only
Operation Dependent Information· (DCB Word 2)
DCB word 2 is used only for E2, E4, E8, and EA operations.
Bit
o
1
2
3-4
5-7
8-11
12-15
Meaning
Reverse inhibit
Checksum inhibit
Clear storage
Reserved (must be zero)
Function ID
Reserved (must be zero)
Paging
Section 3. I/O Devices and Features
3-53
Series/l to PC
Device Control Block (DCB) for the Start Write
Command (Hex 70)
Word
o
DCB control word
1
Station address
2
Not used
3 DCBID
I
Reserved
I
Reserved
4 Not used
5 Chain address (must be even address)
6 Data byte count
7 Data address
o
15
Control Word (DCB Word 0) for the Start Write
Command (Hex 70)
Bit
o
1
2
3-4
5- 7
8-15
3-54
Meaning
Chaining flag
Program-controlled interrupt (PCI)
Input flag
Not Used (0)
Cycle-steal address key
Device Control Operation
Hex
Device Control Operation
00
No-op
02
Set IPL
04
Status Request
08
Read Request
06
Write Request
OC
Write Data End
OE
Broadcast Message
GA34-0034
Series/1 to PC
Device Control Block (DCB) for the Start Read
Command (Hex 71)
Word
o
DCB control word
1 Station address
2
I
Reserved
Not used (O's)
I
3 DCBID
Reserved
4 Residual station block address (must be even)
5
DCB chaining address (must be even)
6
Data byte count
7 Data address (must be even, bit 15=0)
o
15
Control Word (DCB Word 0) for the Start Read
Command (Hex 71)
Bit
o
1
2
3
4
5- 7
8-15
~eanUng
Chaining flag
Program-controlled interrupt (PCI)
Input flag
Not Used (0)
Suppress Exception Flag
Cycle-steal address key
Device Control Operation
Hex
Device Control Operation
00
No-op
02
Specific Read
12
Non-specific Read
Section 3. I/O Devices and Features
3-55
Series/l to PC
Device Control Block (DCB) for the Start
Diagnostics Command (Hex 7D)
Word
o
DeB control word
1
Not used (O's)
2
Not used (O's)
3 Not used (O's)
4
Not used (O's)
5
Not used (O's)
6
Data byte count (must be 8)*
7 Data address (must be even)*
o
15
*used only when word 0, bit 13 is set to 1.
Control Word (DCB Word 0) for the Start
Diagnostics Command (Hex 7D)
Bit
0-1
2
3-4
5- 7
8-12
13
14
15
~eanWng
Not Used (0)
Input flag
Not Used (0)
Cycle-steal address key
Not used
Cable Wrap Test
On-Card Wrap Test
Internal Card Test
Note: Bit 15 is highest priority test, followed by bit 14, then
bit 13.
3-56
GA34-0034
Series/Ito PC
Device Control Block (DCB) for the Start Cycle
Steal Status Command (Hex 7F)
Word
o
DCB control word
1 Not used
2
Not used
3 Not used
4
Not used
5 Not used
6 Data byte count
7 Data address
o
15
Control Word (DCB Word 0) for the Start Cycle
Steal Status Command (Hex 7F)
Bit
~e~
0-1
Not Used (0)
Input flag
Not Used (0)
Cycle-steal address key
Not used
2
3-4
5- 7
8-15
Section 3. I/O Devices and Features
3-57
Series/1 to PC
Cycle-Steal Status Words (Loaded Microcode
Control)
Word 0
Bit
0-15
~eanWng
Residual address
Word 1
Bit
0-15
~eanWng
Residual count
Word 2
Bit
~eanWng
o
Station not found
Data transfer parity error
Frame refused
Not Used
Attachment buffer full
Busy, no specific response
Receive error
Not used
1
2
3-4
5
6
7
8-15
Word 3
Bit
0-5
6
7
8-15
~eanWng
Not used
Receive enable
Receive frame in buffer
Not used
Word 4
Bit
0-15
~eanWng
Frame byte count
Word 5
Word 5 is the DCB address contained in the IDCB.
3-58
GA34-0034
Series/1 to PC
Word 6
Word 6 contains the subchannel current DCB address.
Words 7-14
These words contain the current DCB.
Cycle-Steal Status Words (ROS Control)
Word 0
Bit
0-15
Meaning
Residual address
Word 1
Bit
o
1
2
3
4
5-7
8-11
12
13
14-15
Meaning
Initailized
Attachment storage checksum error
Attachment storage parity error
Storage compatibility error
Attachment hardware error
Residual key
Not used
Attachment storage address error
Function ID compare error
Not used
Word 2
Bit
0-3
4
5- 7
8-11
Meandng
Not used
Deviced defined
Function ID
ROS level
Word 3
Bit
0-15
Meaning
Last DCB Address
Section 3. I/O Devices and Features
3-59
Series/1 to PC
Wonb4-l4
These words are not used and are all FF (all bits on).
Residual Status Block (RSB) under Loaded
Microcode Control
Word 0
Bit
0-15
~ean[ng
Residual count
Wordl
Bit
~ean[ng
o
End of chain
Not used-zeros
No exception
1-14
15
Word 2
Bit
0-15
~ean[ng
Residual address
Word 3
Bit
0-7
8-15
~ean[ng
Station address (word 1 of DCB)
DCB byte 0 (bits 0-7 of current DCB control word)
Word 4
Bit
0-15
~ean[ng
Data address (word 7 of DCB)
Interrupt Condition Codes Reported
CCO, CC1, CC2, CC3
3-60
GA34-0034
Series/Ito PC
Interrupt Information Byte(IIB)*
Bit
o
1-7
ISB meaning
Suppress Exception
Not Used
• Used only with CC3
Interrupt Status Byte (ISB)
Bit
o
1
2
3
4
5
6
7
ISB meaning
Device-dependent status available
Delayed command reject
Incorrect-length record
DCB specification check
Storage data check
Invalid storage address
Protect check
Interface data check
Section 3. I/O Devices and Features
3-61
Series/l-System/370 Channel Attachment
Feature
Series/1 I/O Commands
Hex
Command
20
21
60
62
6F
70
71
7F
Read ID
Read Status
Prepare
Disable System/370
Device Address
Enable System/37O
Device Address
Set System/370
Device End
Set Attention to
System/37O
Device Reset
Start
Start Diagnostic
Start Cycle-Steal Status
3-62
GA34-0034
63
64
65
I/O instruction
CCs reported
0,5,7
0,1,2,5,7
0,5,7
0,1,2,3,5,7
0,1,2,3,4,5,7
0,1,2,3,4,5,7
0,1,2,3,4,5,7
0,7
0,1,2,3,4,5,7
0,1,4,5,7
0,1,2,5,7
Series/l-S/370
Series/l Device Control Block (DCB)
Word
o
Control word
1 Not used (not fetched)
2
Not used (not fetched)
3
Not used (not fetched)
4
Device parameter word 4 (status address)
5 Not used (not fetched)
6 Count
7 Data address
o
15
Control Word (DCB Word 0)
Bit
0, 1
2
3
4
5- 7
8-15
Meaning
Not used-must be zeros
Input flag
Not used-must be zero
Suppress exception
Cycle-steal address key
Not used-must be zeros
Section 3. I/O Devices and Features
3-63
Series/l-S/370
Series/1 Device Status Word
Bit
Meaning
Not used-zero
Online
System/370 busy or chaining
System/370 reset
System/370 interface disconnect
Time-out
System/370 error
Attention command
System/370 device address
System/370 command
o
1
2
3
4
5
6
7
8-12
13-15
Series/1 Cycle-Steal Status Words
Word 0
Bit
0-15
Meaning
Residual address
Wordl
Bit
0-15
Meaning
Residual byte count
Word 2
Bit
0-3
4-15
Meaning
Residual data indicator (RDI)
Not used-zeros
Word 3
Same as Series/I Device Status Word
3-64
GA34-0034
Series/l-S/370
Series/1 Residual Status Block (RSB)
Word 0
Bit
~eanWng
0-15
Residual byte count
Word 1
Bit
~eanWng
o
Always set to 1
Not used-zeros
No exception
2-14
15
Word 2
Bit
~eanWng
0-3
4-15
Residual data indicator (RDI)
Not used-zeros
Series/1 Interrupt Condition Codes Reported
CC2, CC3, CC4, CC7
Series/1 Interrupt Information Byte (lIB)
Condition code
2
3,4,7
lIB contents
Cycle-steal interrupt status byte
Bit
~eanWng
o
Permissive device end
Online
Chaining device end
System/370 reset
System/370 interface
disconnect
Time-out
Chaining attention
Attention command
1
2
3
4
5
6
7
Section 3. I/O Devices and Features
3-65
Series/l-S/370
Series/l Interrupt Status Byte (ISB)
Bit
o
1
2
3
4
5
6
7
ISB meaning
Device status available
Not used
Incorrect record length
DCB specification check
Storage data check
Invalid storage address
Protect check*
Interface data check
*Zero for a device attached to a 4952 or 4953 processor
System/370 I/O Commands
Hex
00
01
02
03
04
05
06
OB
00
OE
OF
33
E4
Command
Test I/O
Write
Read Buffer
No-Operation
Sense
Erase/Write
Read Modified
Select
Diagnostic Write
Diagnostic Read
Erase All Unprotected
Subsystem Load Enable
Sense I/O
System/370 Data for a Sense Command
Bit
~eaning
o
Command reject
Intervention required
Bus out check
Not used-zero
Data check
Unit specify
Control check
Not used-zero
1
2
3
4
5
6
7
3-66
GA34-0034
Series/l-S/370
System/370 Data for a Sense I/O Command
Byte
o
1
2
3
Data (hex)
FF
49
50
OX
x=
0, Inhibit IPL jumper installed
X = 1, Inhibit IPL jumper not installed
System/370 Status Byte
Bit
0
1
2
3
4
5
6
7
Meaning
Attention
Status modifier
Control unit end
Busy
Channel end
Device end
Unit check
Not used-zero
Section 3. I/O Devices and Features
3-67
Synchronous Communications Single-Line
Control
I/O Commands
1/0 instruction
Hex
Command
CCs reported
20
60
6F
70
71
72
7D
7E
7F
Read ID
Prepare
Device Reset
Start
Start Control
Start Modification
Start Diagnostic 1
Start Diagnostic 2
Start Cycle-Steal Status
0,1,2,5,6,7
0,5,7
0,7
0,1,2,5,6,7
0,1,2,5,6,7
0,1,2,5,6,7
0,1,2,5,6,7
0,1,2,5,6,7
0,1,2,5,6,7
3-68
GA34-0034
SCSLC
Device Control Block (DCB)-SDLC/HDLC
Word
o
Control word
1
Timer 1
2
Not used (O's)
3
DCBID
4
Status address
5
Chaining address
6
Byte count
7
Data address
I
Timer 2
INot used (O's)
o
15
Control Word (DCB Word O}--SDLC/HDLC
Bit
o
1
2
3
4
5- 7
8
9
10
11
12
13
14
15
Meaning
Chaining flag
Program-controlled interrupt (PCI)
Input flag
Not used-zero
Suppress exception (SE)
Cycle-steal address key
Not used-zero
NRZI coding
Enable
Disable
Pad/control
Secondary/primary
Transmit operation
Hold line active (HLA)
Section 3. I/O Devices and Features
3-69
SCSLC
Device Control Block (DCB)-BSC
Word
o
Control word
1
Not used
2
Not used
3
DCB ID
4
Not used
5
Chaining address
6
Byte count
7
Data address
I
Not used (O's)
o
15
Control Word (DCB Word O)-BSC
Bit
~ean1ng
o
Chaining flag
Program-controlled interrupt (PCI)
Input flag
Not used-zero
Not used-zero
Cycle-steal address key
Not used-zero
Set ASCII mode
Enable
Disable
Start timer
Transmit operation
Exit transparent
Not used-zero
1
2
3
4
5- 7
8
9
10
11
12
13
14
15
3-70
GA34-0034
SCSLC
Device Control Block (DCB)-Leased
Operation-SDLC/HDLC/BSC
Word
o x
0 0 0 0 K E Y 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 X X X 0 0
2
Not used
3
Not used
4
Not used
5
Chaining address
6
Not used
7
Not used
o
15
Section 3. I/O Devices and Features
3-71
SCSLC
Control Words (DCB Words
O-lj-SDLC/HDLC/BSC
Word 0
Bit
~eaning
o
Chaining
Not used-zeros
Cycle-steal address key
Not used-zeros
1-4
5- 7
8-15
Wordl
Bit
~eaning
0-10
11
12
13
14
15
Not used-zeros
PCI
Duplex mode
Installation test
Not used-zero
Not used-zero
3-72
GA34-0034
SCSLC
Device Control Block (DCB)-X.21 Switched
Operation
Word
o x
0
X
0
XIK
E YIO 0 0 0 0 X
XX
Operation dependent
2
Not used (O's)
3
Not used (O's)
4
Operation dependent
5
Operation dependent
6
Operation dependent
7
Operation dependent
o
15
Control Word (DCB Word 0) Switched
Line-SDLC/HDLC/BSC
Bit
~eanWng
0-4
Operation (used with bits 8-15)
XOOOO
Set mode (bit a = chaining flag)
00101
Network provided information
00 1a1
Auto-answer
00000
Clear
Cycle-steal address key
Modifier bits
00000000
Set mode
00000001
Network provided information
00000010
Auto-answer
00000100
Clear
5- 7
8-15
Section 3. I/O Devices and Features
3-73
SCSLC
Cycle-Steal Status Words-SDLC/HDLC
Word 0
Bit
0-15
~eaning
Residual address
Wordl
Bit
0-15
~eaning
Residual byte count
Word 2
Bit
~eaning
o
Overrun
Abort
Long frame
Block check error
Time-out
Idle detected
Nonproductive receive time-out
DCE interface error
Not used-zeros
Local attach 1
Not used-zeros
1
2
3
4
5
6
7
8-12
13
14, 15
Word]
Bit
~eaning
o
Data terminal ready
Data set ready
Request to send
Clear to send
Not used-zeros
Transmit mode
Not used-zero
Secondary station address
1
2
3
4, 5
6
7
8 -15
3-74
GA34-0034
SCSLC
Word 4
Bit
~eanUng
0-8
9
10
11
12
13
14
15
Not used-zeros
X.21 switched operation
V.35 operation
Not used-zero
Local attach 2 operation
Not used-zero
IPL allowed
BSC operation
Word 5
Bit
~eanUng
0-7
8
9
10
11
12
13-15
X.21 interface state
Transmit interface line (X.21)
Receive interface line (X.21)
Indicator interface line (X.21)
Control interface line (X.21)
Not used-zero
DTE time-out (X.21)
Cycle-Steal Status Words-BSC
Word 0
Bit
~eanUng
0-15
Residual address
Word 1
Bit
o
1
2
3
4
5
6
7
8-15
~eanUng
Overrun
Time-out
DCE interface error
Block check error
Multipoint transmit error
Not used-zero
Multipoint tributary jumper installed
Improper configuration
Multipoint address
Section 3. I/O Devices and Features
3-75
SCSLC
Word 2
Bit
Meaning
Data terminal ready
Data set ready
Request to send
Clear to send
Not used-zeros
Transmit mode
Not used-zero
Indicator panel switch setting
o
1
2
3
4,5
6
7
8-15
Word 3
Bit
0-8
9
10
11
12
13
14
15
Meaning
Not used-zeros
X.21 switched operation
V.35 operation
Not used-zero
Local attach 2 operation
Not used-zero
IPL allowed
BSC operation
Word 4
Bit
0-7
8
9
10
11
12
13-15
3-76
Meaning
X.21 interface state
Transmit interface line (X.21)
Receive interface line (X.21)
Indicator interface line (X.21)
Control interface line (X.21)
Not used-zero
DTE time-out (X.21)
GA34-0034
SCSLC
Interrupt Condition Codes
Reported-SDLC/HDLC/BSC
cco,
CC1, CC2, CC3, CC4
Interrupt Information Byte
(IIB)-SDLC/HDLC/BSC
Condition code
0-1
2
3*
4
lIB contents
DCB identifier
Cycle-steal interrupt status byte (ISB)
Bit 0 on = Permissive device end
Bit 0 on = Successful DCE initiated clear
Bit 7 on = Unsuccessful DCE initiated
clear
*Applies to SDLC/HDLC only
Interrupt Status Byte (ISB)-SDLC/HDLC/BSC
Bit
o
1
2*
3
4
5
6
7
ISB meaning
Device status available
Delayed command reject
Incorrect record length
DeB specification check
Storage data check
Invalid storage address
Protect check
Interface data check
*Applies to BSC only
Section 3. I/O Devices and Features
3-77
Telephone Communications Attachment
Feature
I/O Commands
1/0 instruction
Hex
Command
CCs reported
20
50
0,1,3,5,6,7
0,1,3,5,6,7
7F
Read ID
Write Initial Attachment
Storage Load
Prepare
Device Reset
Start Cycle-Steal
Load Adapter
Parameters
Display Adapter
Control Block
Diagnostic Check Sum
Controller Storage
Load
Start Cycle-Steal Status
3-78
GA34-0034
60
6F
70
71
72
7D
7E
0,1,3,5,6,7
0,1,3,5,6,7
0,1,3,5,6,7
0,1,3,5,6,7
0,1,3,5,6,7
0,1,3,5,6,7
0,1,3,5,6,7
0,1,3,5,6,7
Telephone Comm.
Device Control Block (DCB)
Word
o
Control Word
Operation modifier
Function ID
2 Timer 1
Timer 2 (pace)
3 DCB ID
Audio output level
4
Key response index pointer
5 Chaining address
6
Byte count
7
Data address
o
15
Section 3. I/O Devices and Features
3-79
Telephone Comm.
Control Word (DCB Word 0)
Bit
~eanrnng
o
Chaining flag
PCI
Input flag
Not used-zeros
Cycle-steal address key
Not used-zeros
Key response flag
1
2
3,4
5- 7
8-14
15
Cycle-Steal Status Words
Word O-Residual Address
Bit
~eaning
0-15
Address of last-attempted data transfer
Word I-Residual Count
Bit
~eaning
0-15
Number of bytes remaining to be transferred when
the error occurred
Word 2-Device Status
Bit
~eaning
o
On hook
Coupler cut-through not detected
Invalid dial digit
No dial tone
Number busy
Dialing error
No answer
Disconnected
Received time-out
Invalid generate programmed tone
Disconnect error
Key tone received
Key tone codes
1
2
3
4
5
6
7
8
9
10
11
12-15
3-80
GA34-0034
Telephone Comm.
Word 3-Device Status
Bit
0-7
8,9
10
11
12-15
Meaning
Not used
Checksum error
Audio output level selected
Automatic gain control locked
Audio input level
Interrupt Condition Codes Reported
CCO, CC1, CC2, CC3, CC4
Interrupt Information Byte (lIB)
Condition code
3,4
lIB contents
Cycle-steal interrupt status byte (ISB)
Interrupt Status Byte (ISB)
Bit
o
1
2
3
4
5
6
7
ISB meaning
Device status available
Delayed command reject
Incorrect-length record
DCB specification check
Storage data check
Invalid storage address
Protect check
Interface data check
Section 3. I/O Devices and Features
3-81
Teletypewriter Adapter Feature
I/O Commands
1/0 instruction
Hex
Command
CCs reported
10
Read
Read
ReadID
Write
Write
Prepare
Reset to Diagnostic
Wrap
Device Reset
0,1,3,5,7
0,1,3,5,7
0,5,7
0,1,3,5,7
0,1,3,5,7
0,5,7
0,1,3,5,7
11
20
50
51
60
6E
6F
0,1,3,5,7
Device Status Word
Device status is reported via condition codes.
Interrupt Condition Codes Reported
CC2, CC3, CC4, CC6, CC7
Interrupt Information Byte (liB)
Condition code
2,3,4,6,7
3-82
lIB contents
Always zeros
GA34-0034
Timer Feature
110 Commands
1/0 instruction
Hex
Command
CCs reported
20
24
25
60
64
Read ID
Read Timer Value
Read Timer Mode
Prepare
Set Timer Period and
Initial Value
Set Timer Mode
Set Timer Periodic
Set Timer Aperiodic
Stop Timer
Device Reset
0,5,7
0,1,3,5,7
0,1,3,5,7
0,5,7
0,1,3,5,7
65
66
67
6E
6F
0,1,3,5,7
0,1,3,5,7
0,1,3,5,7
0,1,3,5,7
0,7
Device Status Word
Device status is reported via condition codes.
Interrupt Condition Codes Reported
CC2, CC3, CC4, CC6, CC7
Interrupt Information Byte (lIB)
Condition code
2,3,4,6,7
lIB contents
Always zeros
Section 3. I/O Devices and Features
3-83
Two Channel Switch Feature
110 Commands
1/0 instruction
Hex
Command
CCs reported
20
23
50
53
60
63
66
Read ID
Read Status Word
Console Acknowledge
Reserve
Prepare
Reset and Connect
Start Operations
Monitor
Reset Operations
Monitor
Device Reset
0,5,7
0,1,5,7
0,1,5,7
0,1,3,4,5,7
0,5,7
0,1,3,5,7
0,1,3,4,5,7
6C
6F
0,7
0,7
Device Status Word
Bit
°
1
2
3
4
5
6, 7
8
9
10
11
12,13
14,15
3-84
Meaning
CIO connected
Control mode in effect
Operations monitor time-out
Reserve
Operations monitor run
Operations monitor time-out incurred
Zeros
CIO connection alert
Control mode alert
IIPL blocked
Polarity
Operations monitor initial period
Operations monitor warning period
GA34-0034
TCS
Interrupt Condition Codes Reported
CC2, CC3, CC4, CC6, CC7
Interrupt Information Byte (lIB)
Condition code
2
3
4
6
7
lIB contents
DPC interrupt status byte (ISB)
Always zero
Bits 0, 1
Always zeros
Bit 2
Connect go-ahead
Bit 3
Ready
Bit 4
Operations monitor
warning
Bit 5
Always zero
Bit 6
Console attention
Bit 7
Console reset
Same as CC4
Same as CC4
Interrupt Status Byte (ISB)
Bit
0, 1
2
3
4
5
6
7
ISB meaning
Always zeros
Connect go-ahead
Ready
Operation monitor warning
Always zero
Console attention
Console reset
Note: Bits 0- 7 are always zeros for CC2
Section 3. I/O Devices and Features
3-85
4950/5170 Model 495 Asynchronous
I/O Commands
Hex
Command
I/O instruction
CCs reported
20
50*
60
6F
70
7C#*
7D*
7F
Read ID
DPC Write
Prepare
Device Reset
Start
Start Control
Start Diagnostic 1
Start Cycle-Steal Status
Halt I/O
0,5,7
0,1,5,7
0,5,7
0,7
0,1,5,7
0,1,5,7
0,1,5,7
0,1,5,7
N/A
Fa
# Supported by the 4950 processor for
set expanded mode only
* Not supported by the IBM Personal Computer Display
Device Control Block (DCBfwith Word 0, Bit 8
orr
Word
o
Control word
Not used
2 Timer 1
3 Timer 2
4
Not used
5 Chain address (must be even address)
6
Byte count
7 Data address
o
3-86
15
GA34-0034
4950/5170 Asynch
Control Word (DCB Word 0) with Bit 8 Off
Bit
o
1
2
3-4
5-7
8-15
Meaning
Chaining flag
Not used-zero
Input flag-data cycle-steal to storage
Not used-zero
Cycle-steal address key
Operation
00
Transmit
01
Transmit end
02#
Transmit allow break
03#
Transmit end allow break
04
Receive
05
Receive with time-out
06*
Ring monitor (RS232 only)
07*
Ring monitor with time-out (RS232 only)
08
DTR enable
09
DTR enable with time-out
DTR enable with answertone
OA+
DTR enable with answertone and time-out
OB+
OC
DTRdisable
OE
Program delay
OF
Reset
1D
Set control
74
Read adapter buffer
11*## Transmit end with pre-receive
13*## Transmit end, allow break with pre-receive
44*## Receive transparent
45*## Receive transparent with time-out
* Not supported by the IBM Personal Computer Display
+ Answertone will not be generated
# Break ignored on the IBM Personal Computer Display
## Supported by the 5170 Model 495 (terminal/host adapter)
only
Section 3.1/0 Devices and Features
3-87
4950/5170 Asynch
Device Control Block (DCB) with Word 0, Bit 8
On
Word
o
Control word
1
Bit-rate constant
Line-control character
2
Line-control character
Line-control character
3 Line-control character
Line-control character
4 Line-control character
Line-control character
5 Chain address (must be even)
6 Not used (0)
7 Not used (0)
o
II
Control Word (DCB Word 0) with Bit 8 On
Bit
Meaning
o
Chaining flag
Not used-zero
Input flag--data cycle-steal to storage
Not used-zero
Cycle-steal address key
Bit 8 is on (1)
mode:
o
Asynchronous mode
1
Synchronous mode (not supported)
Character size:
00
5 bits
01
6 bits
10
7 bits
11
8 bits
Stop bits (in asynchronous mode)
1
2
3-4
5-7
8
9
10-11
12-13
3-88
GA34-0034
4950/5170 Asynch
01
1 stop bit used
11
2 stop bits used
Parity type (O-odd; I-even)
Parity (O-disabled; I-enabled)
14
15
Device Control Block (DCB)-Start Control
Command in set expanded mode
Word
o
Contains the value X'OI'
1 Not used
2 Not used
3
Bit 14 - Atte~tion interrupt
Bit 15 - Continuous receive
4 Not used
5 Not used
6 Must contain all zeros (0)
7 Not used
o
15
Cycle-Steal Status Words
Word 0
Bit
0-15
Meaning
Residual address
Section 3. I/O Devices and Features
3-89
4950/5170 Asynch
Wordl
Bit
Meaning
Overrun
Time-out
Not used
DCB reject
Not used
VRC error
Break detected
Stop-bit error
Not used-zero
Modem interface error
Not used-zeros
Error during pre-receive, adapter buffer overflow
Not used-zeros
Characters in adapter buffer
o
1
2
3
4
5
6
7
8
9
10-11
12
13-14
15
Word 2
Bit
o
1
2
3
4-15
Meaning
Data terminal ready
Data set ready
Request to send
Clear to send
Not used-zeros
Interrupt Condition Codes Reported
CC2, CC3, CC4, CC6
Interrupt Information Byte (lIB)
Condition code
2,6
3
4
3-90
lIB Contents
Cycle-steal interrupt status byte (ISB)
Always zeros
Attention Character
GA34-0034
4950/5170 Asynch
Interrupt Status Byte (ISB)
Bit
ISB meaning
1
2
3
4
5
6
7
Device status available
Delayed command reject
Incorrect record length
DCB specification check
Storage data check
Invalid storage address
Protect check (always zero)
Interface data check
o
Section 3. I/O Devices and Features
3-91
4950/5170 Model 495 Disk/Diskette
Adapter
I/O Commands
Hex
Command
20
60
6F
70
7F
FO
Read ID
Prepare
Device Reset
Start
Start Cycle Steal Status
Halt I/O
110 instruction
CCs reported
0,5,7
0,5,7
0,7
0,1,5,7
0,1,5,7
N/A
Device Control Block (DCB)
Word
o
Control word
1 Not used
2
RBA (bits 4-19)
3
RBA 0-3) Not used
(bits
I
4 Residual status byte address
5 Chain address
6 Byte count
7 Data address
o
3-92
GA34-0034·
15
4950 Disk/Diskette
Control Word (DCB Word 0)
Bit
o
1
2
3
4
5- 7
8-15
~eaEWng
Chaining flag
Not used (0)
Input flag
Not Used (0)
Suppress exception flag
Cycle-steal address key
Cycle steal operation command
Hex
Command
01
Recalibrate
10
Read data
16
Read media parms
20
Write data
21
Write data with read verify
26
Load media parms
27
Format diskette
Cycle-Steal Status Words
Word 0
Bit
~eaEWng
0-15
Residual address
Wordl
Bit
~eaEWng
0-15
Residual count
Word 2
Bit
0-3
4-11
12
13
14
15
~eaEWng
Number of soft error retries (CRC or ECC check)
Reserved
Data unsafe
File not ready
Reserved
Soft error retry
Sectinn
~_
T/0
nevice~
and
Feature~
3-93
4950 Disk/Diskette
Word 3
Bit
0-3
Meaning
Number of retries (no-record-found error)
Storage data check
Invalid storage address
Protect check
Interface data check
Attachment interface parity check
Reserved
Common adapter ROS parity check
Reserved
Common adapter RAM parity check
Reserved
Write error retries
4
5
6
7
8
9
10
11
12
13
14-15
Word 4
Bit
o
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
3-94
Meanrnng
Hard error
Attachment-detected interface parity check
Attachment global timeout
Control mark
Interrupt code
Write fault
Attachment equipment check
Write error
Adapter storage parity error
Data error in data field
Bad cylinder
Missing address mark in data field
Cycle-steal status error
End of disk or diskette
Interrupt code
No data
GA34-0034
4950 Disk/Diskette
Word 5
Bit
Meaning
o
CRC or ECC check
Overrun
No index
Not writable
Wrong cylinder
Invalid command parameter
Missing address mark
Disk unit timeout or hardware check
Head address
Unit select
Seek incomplete
Home
Not ready
1
2
3
4
5
6
7
8-10
11-12
13
14
15
Word 6
Bit
0- 1
2
3
4
5- 6
7
8-15
Meaning
Reserved
Cache write through
Reserved
Cache enabled
Reserved
Cache installed
Read hit percentage (BCD coded)
Word 7
Bit
0-15
Meaning
Reserved (all zeros)
Word 8
Bit
0-15
Meaning
Last DCB address
Words 9-10
Bit
0-15
Meaning
Logical record number
Section 3. I/O Devices and Features
3-95
4950 Disk/Diskette
Words 11-12
Bit
~eaning
0-15
Reserved
Word 13
Bit
~ean[ng
1
2-15
Sector Size Invalid
Maximum RBA Address Invalid
Reserved
o
Interrupt Condition Codes Reported
CC2, CC3
Interrupt Information Byte (lIB)
Bit
~eaning
o
Permissive Device End
Always zeros
1-7
Interrupt Status Byte (ISB)
Bit
~eaning
1
2
3
4
5
6
7
Device status available
Delayed command reject
Not used
DCB specification check
Storage data check
Invalid storage address
Protect check (always zero)
Interface data check
o
3-96
GA34-0034
4962 Disk Storage Unit
I/O Commands
1/0 instruction
Hex
Command
CCs reported
20
Read ID
Prepare
Device Reset
Start
Start Cycle-Steal Status
0,5,7
0,5,7
0,7
0,1,3,5,7
0,1,3,5,7
60
6F
70
7F
Device Control Block (DCB)
Word
o
Control word
Seek control word
2
3
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