GMS 1011TM_UNIVAC_60_120_Service_Manual_21 1011TM UNIVAC 60 120 Service Manual 21
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User Manual: GMS-1011TM_UNIVAC_60_120_Service_Manual_21
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ELECTRONIC COMPUTOR
UNIVAC 60 & 120
Service Manual 21
-
DIVISI O / l
O f
SP ERRY
RA ND
CORPORA T IO N -
~
315 FOURTH AVENUE
NEW YORK, N. Y.
~~~~------------------~
ELECTRONIC COMPUTER
UNIVAC 60 & 120
Service -Manual 21
-
DIVISION
OF SPERRY RAND CORPORA:TION - .
315 FOURTH AVENUE
NEW YORK, N. Y.
GMS -lOll TM
FOREWORD
The material contained in this Manual describes the Mechanical
and Electronic functions of the Electronic Computers, Univac
60 & 120.
The description of the machine has been divided into sectj.ons
covering; Specifications, Mechanical Description, Circuit
Description, Adjustments and Preventive Maintenance.
The plate drawings associated with each section will be found
immediately following the section to which they pertain. A
code letter suffix has been included with the plate drawing
number to indicate its associated section. When reference is
made to a plate number, unless otherwise indicated by a suffix
letter, that reference is made to the plate number associated
with the section therein.
ELECTRONIC COMPUTER
UNIVAC 60 & 120
CONTENTS
Plate Drawing Index
General Description ••••••••••••••••••••••••••
Mechanical Description (Punch) •••••••••••••••
Circuit Description (Computer) •••••••••••••••
Adjustment s •......•..••...•......•••.••...•••
Preventive Maintenance •••••••••••••••••••••••
Printed in U. S. A.
Section
Section
Section
Section
Section
A
B
C
D
E
ELECTRONIC COMPUTm
UNIVAC
(fJ &
120
PLATE DRAWINGS
Section -B(Mechanical Description)
Title
Plate No.
1B
2B
Punch, Front View •••••••••••••••••••••••••••••••••••••••••••
Punch, Rear View ••••••••••••••••••••••••••••••••••••••••••••
Punch, Cross Sectional View •••••••••••••
Motor Drive and Clutch ••••••••••••••••••••••••••••••••••••••
Card Feed & Card Conveyor Mechanism •••••••••••••••••••••••••
Sensing 1800 ••••••••• " ••••••••••••••••••••••••••••••••••••••
~
Sensing
Sensing
8B
•• t.' • • • • • • • • • • • • • • • •
513
6B
'7B
2930 •
36oa ••••••••••••••••••••••••••••••••••••••••••••••••
P1ln.ching
P1ln.chin.g
P1lIlching
t, • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • ,t • • • • • • •
1800.............................,..................
3470
9B
100
11B
• • • • • • • • . • • • • • • • • • . ' • • • • • • • • • • • • • • • • • • • ,• • • • • • • • • •
81 0 •• , • • • • • • • • • • • • • • • • • • • • • • • • • • •, • • • • • • • •,. ')'"
••. ,11
•••
Terminal Boards Left Side ...........•......................
Terminal Boards Right Side ••••••••••••••••••••••••••••••••••
Punch Power Supply ••••••••••••••••••••••••••••••••••••••••••
12B
~~
1513
Timing Chart •••.•••••••• _. '.' ••••••••••••••••••••••••• , ••••••••
Section -C(Circuit Description)
Title.
Plate No.
Addition and Subtraction ••••••••••••••••••••••••••••••••••••
1C
2C
ACC1lDlula tor Shift Mechanism •••••••••••••••••••••••••••••••••
Carry Input .Gen.er.ator •••••••• ',,' ............................. .
Decimal Registration and Shift Operation ••••••••••••••••••••
Registration Input Generator '.' ••••••••••••••••••••••••••••••
Input Circuit •.•••••••••••••••.•••••••••••••• '•••••••••••••••••
Double Input (Alpha) Check ••••••••••••••••••••••••••••••••••
~g
Output Deo.oder •.•• '••••••••••• " .. '.' •••••••• ~ •••••••••••••••••••
8c
Storage Bit Controls ••••••••••••••••••••••••••••••••••••••••
Storage Contro~ ••••••••,•••••••••••••
Caloulator Zeroize •••••••••••• ~ •••••••••••••••••••••
5c
6c
7C
9C
o• • • • • • • • • • • • • • • • • • • • • • • •
0'1- . . . . . .
Clam.p Ciro'll1.ts •• ~.' ••••••••• '•••••••••••••••••••••••••••••••••
Minidend Registration •••••••••••••••••••••••••••••••••••••••
Subvisor Registration •••••••••••••••••••••••••••••••••••••••
Resul.t to Storage.•.•••·••••••••••.••
Proof Minidend - Storage Registration ••••••••••••••••••••• ~.
to • • • • • • • • • • • • • • • • • • • • ;. • • • • •
..
10C
11 C
12C
13C
1lfc
150
16c
Proof Subvisor - Subvisor Registration •••••••••••••••••••••••
Minidend Subtration ••••••••••••••••••••••••••••••••••••••••••
Zero Check •••••••••••••••••••••••••••••••••••••••••••••••••••
Complementize.e ••••••••••••••••••••••••••••••••••••••••••••••
Multiplication Division Counter ••••••••••••••••••••••••••••••
l1ultiplication Process Call ••••••••••••••••••••••••••••••••••
Multiplication Process ••••••••••••••••• ~ •••••••••••••••••••••
Division Process Call ••••••••••••••••••••••••••••••••••••••••
Division Process •••••••••••••••••••••••••••••••••••••••••••••
0F Multiplication - Division •••••••••••••••••••••••••••••••••
Zero Factor - Sort and Trip ••••••••••••••••••••••••••••••••••
Sort I, Set I and Clear ••••••••••••••••••••••••••••••••••••• a
Select I Stepo.o •• e • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
Trip Circuit ••••• a • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
Selector Relay Control •••••••••••••••••••••••••••••••••••••••
Test Counter •••••••••••••••••••••••••••••••••••••••••••••••••
Voltage Abnormality Detector ••••••••••••••••••••••
Automatic Circuit Timer •••••••••••••••••••••••••••
Program Test Panel Operation •••••••••••••••••••••••••••••••••
B2 - B5 Zeroize ••••••••••••••••••••••••••••••••••••••••••••••
KB Recovery and Decimal Control ••••••••••••••••••••••••••••••
Plugboard Control ••••••••••••••••••••••••••••••••••••••••••••
......................
Control Ring ••••••• ~ ••••••••••• " •••••••••••••••••••••••••••••
Process Control •••
a •••
Conditioning CCT for Shifts ••••••••••••••••••••••••••••••••••
8
••••••••••••••••••••••••••••••••••••••
Sign Bias ••••••••••••••••••••
Cl • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
Sign Bias - Addition and Subtraction •••••••••••••••••••••••••
Minus Factor - Addition and Subt.raction ••••••••••••••••••••••
Sign Bias - Division and Multiplication ••••••••••••••••••••••
(-) storage Bit Operation ••••••••••••••••••••••••••••••••••••
.-lfov Regulated Supply.· ••
(t
G
• . • • • • • • • • • • • • • • It • • • • • • • • • • • • • • • • • • •
Cathode Controls on ex •••.•••.•••••••••••••••.••••.•••••.••••
Step Trigger and Gate ••••••••••••••••••••••••••••••••••••••••
Calculator Crank Up ••.••••••••••••••••••••••
Power Supply Minus Voltages ••••••••••••••••••••••••••••••••••
Power Supply Plus Voltages •••••••••••••••••••••••••••••••••••
Punch Power Supply •••••••••••••••••••••••••••••••••••••••••••
Punch Clutch and Brake, Operation •••••••••••••••••••••••••••••
It • • • • • • • • • • • • • • • • •
Sor·t, Skip and Set Hold-. o
ea . . . . . . . . . . . . . . . . . . . . . . . . .
/I • • • • • • • • •
Reproduce and Secondary Reproduce ••••••••••••••••••••••••••••
Calculator Front View ••••••••••••••••••••••••••••••••••••••••
Calculator Rear View* ••••••••••••••••••••••••••••••••••••••••
Power Supply •••••••
ft • • • • • • • • 0
••
e _ ••••••••••••••••••• _ ••••••••
DC Interlock Relay Assembly ••••••••••••••••••••••••••••••••••
PTP and Power Control ••••••••••••••••••••••••••••••••••••••••
Power Control - Upper ...
P-ower-· Contr·o"l-··_;;;,.···· Lower·~ ••••••••••.-••••••• e . , • • ~- • • • • • • • • e· • • • • • • •
Filament Transformers and Fan Motors •••••••••••••••••••••••••
Computer Wiring Distribution •••••••••••••••••••••••••••••••••
Q •••••••••••••••••••••••••••••••••••••
STA eMs s1 So.
Storage Door
Qo • •
0 ••••••••••••••••••••••• "
••••••••••••••••••••
Ii • • • . • It • • • • -• • • • • • • • to • • • • • • • • • • • • • • • • • • • • • • • • • "
••••
60 and 120 Field Input Heons •••••••••••••••••••••••••••••••••
Decimal Neon Mixer Board •••••••••••••••••••••••••••••••••••••
Constant Neon Panel ••••••••••••••••••••••••••••••••••••••••••
Selector Relay Assembly ••••••••••••••••••••••••••••••••••••••
Restart Switch and TCR Panel •••••••••••••••••••••••••••••••••
17C
18c
19C
20C
21C
22C
23C
24c
25'C
26c
ZlC
28c
29C
30C
31C
32C
33C
34c
35'C
36C
37C
38c
39C
40c
41C
42C
43C
44c
45'C
46c
47C
48c
49C
5'OC
5'1 C
5'2C
5'3C
54c
5'5'c
5'6C
?7C
58c
5'9C
60C
61C
62c
63C
64c
65'C
66c
67C
68c
69C
70C
71C
72C
73C
74C
75C
76C
7.7C
78C
79C
80C
81C
82C
83C
84C
85C
86C
87C
88C
89C
90C
91C
92C
93C
94C
95C
96C
97C
Chas sis Removal ••••••••••••••••••••••••••••••••••••••••••••
.AccUIilUlator ••••••••••••••• , , •••••• , , (ACe) ••• ., • , ••••• , ••••••
Check Counter ..••..•...••.•...•••••• (CCT) •••••..•••••••••••
Control ••••••••••••••••••••••••••••• (CTL) ••••••••••••••••••
Decimal Control ••••••••••••••••••••• (DCL) ••••••••••••••••••
Decimal Counter ..••....•••••.••••••• (DCR) •••••••••.••••••..
Input-Output ••••• ., ••••••••••••• a , . , ' (10) , ••• , ••••••••••••••
Keyboard Bias ••••••• ,. •••••••••••••••• (KB) •••••••••••••••••••
Multiplication - Division ••••••••••• (MD) •••••••••••••••••••
Output Control ·1 •••••••••••••••••••• (OCLl) •••••••••••••••••
Output Control II •••••••••••.••••••• (OCL2) •••••••••••••••••
Zero Factor •••••••••••.••••••••••••• (¢F) •••••••••••••••••••
Registration Input Generator .••••••• (RIG) ••••••••••••••••••
Sign Bias ............................ (SB) •••••••••••••••••••
STA ••••••••••••••••••••••••••• ~ ••••• (STZ) ••••••••••••••••••
Selector Power •••••••••••••••••••••• (SEP) ••••••••••••••••••
Step Control •••.••••.•••••••.••••••• (SeL) ••••••••••••••• ~ •••
Step Sequence ••••••••••••••••••••••• (SS) ••••••••••••••.•••••
Storage Control ••••••••••••••.•••••• (S·TL) ••••••••••••••••••
Test Counter ••••••••.•••••.••••••••• (TCR) ••••••••••••.•••••
Voltage Abnormality Detector .••••••• (VAD) ••••••••••••••••••
Zeroize Control ••••••••••••.•••••••• (ZCL) •••••••••••
<
• • • • • • •
Schematic Diagram - Storage and Control ••••••••••••••••••••
Field Board Explanatory Drawing ••••••••••••••••••••••••••••
Program Board Explanatory Drawing ••••••••••••••••••••••••••
Section -D(Adjustment Figure Drawings)
·........... . D-IO
D-IO
Feed Magazine Adjustments •••••••••••••••••••• 1
Dummy Cam & Pin Lock Adjustments ••••••••••••• 2
Tower Retract Bail & Eccentric Adjustment •••• 3
Non-Restore Bail Adjustment •••••••••••••••••• 4 • ••••••••••••
Set Bar Retract, Skip Interposer Eccentrjc & Die
Section Card Stop ••••••••••••••••••••••••• 5
Card Jam & Sort Micro Switch & Shutter Fingers
Adjustment •••••.•••••••••.••.••••••••••••• 6 • ••••••••••••
Clutch & Brake Assembly, Phenolic Cams, Cam Contacts
& Main Shaft Adjustments •••••••••••••••••• 7 .•••••••....•
Machine Speed, Belt Tension & Electrical System
Adjustment ~ . . • • .. . . . . . . . • • . • • • • • . • . . . . • • . •. S •••••••••••••
·........... . D-ll
D-Il
·........... . D-12
D-12
D-13
D-13
Section -E(Preventive Haintenance)
Plate No.
Punch Base (Front View).......................................
Punch Base (Lower Left Side)~ ••••••••••••••••••••••••••••••••
Punch Base (Lower Right Side) ••••••••••••••••••••••••••••••••
Upper and Lower Sensing Pin Box (Front View) •••••••••••••••••
Upper and Lower Sensing Pin Box (Rear View).............. •.•••
Set Bar Section and Die Section (Front View) •••••••••••••••••
Set Bar Section and Die Section (Rear View) ••••••••••••••••••
Punch Tower (Left Side) ••••••••••••••••••••••••••••••••••••••·
Plugboard Depressor Mechanism ••••••••••••••••••••••••••••••••
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3E
4E
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TC' :)('l'reot thi,$ oonciiticn, the Cnuik Up Motw 6'Uppll' La. bs.s been transten-ed
trom the B-2 leg to the A-2 leg. The A-2 leg is more atable Wn the 8-2 leg
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CARD FEED LINK
PICKER KNIFE
THROAT BLOCK
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FRONT FEED ROLL (UPPER)
FRONT FEED ROLL (LOWER)
TENSION SPRING
INTERMEDIATE FEED ROLLS
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A-30
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FEED EJECT ROLL (UDWER)
INTERMEDIATE FEED ROLLS
INTERMEDIATE PRESSURE ROLLS
PUNCHING CHAMBER CARD STOP
EJECT ROLL (UPPER)
EJECT ROLL (LOWER)
RECEIVER FEED ROLLS
FRONT RECEIVER SHUTTER FINGER
FRONT CARD RECEIVER
REAR CARD RECEIVER
CARD PLATFORM
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DIAL READING 1320
FEED MAGAZINE IS IN FULL FEED POSITION.
A-32-="'~--------~
PARTS NOMENCLATURE
Q
l
A-91
A-90
A-3
A-14
A-15
A-19
A-2.0
A-21
A-34
A-35
A-3E)
A-"S(
A-58
A-39
A-40
A-41
A-42
A-43
A-44
A-45
A-46
A-47
A-51
A-52
A-S6
A-87
A-88
A-S9
A-9Q
A-91
A-92
A-93
A-94
FRONT MAIN SHAFT
FRONT FEED ROLL (UPPER)
FRONT FEED ROLL (LOWER)
SENSING CHAMBER CARD STOP
FEED EJECT ROLL (UPPER)
FEED EJECT ROLL lLOWER)
LOWER· SENSING PIN BOX
SELECTING PIN (LOWER PIN BOX)
LOCK SLIDE (LDWER PIN BOX)
DUMMY CAM
PIN LOCK MECHANISM
PIN LOCK TORSION SPRING
NO CARD SENSING PWNGER
PIN LOCK CONTROL LEVER
UPPER SENSING PIN BOX
SET- UP PIN (UPPER PIN BOX)
LOCK SLIDE (UPPER PIN BOX)
CARD STOP CAM (SENSING)
CARD STOP MECHANISM
TENSION SPRING
COMB SPRING
CELL PLATE
SENSING SWITCH BOX
INTERMEDIATE SENSING PIN
- COMPRESSION SPRING
PIN CAP
CONTACT PIN (NYl.ON)
CONTACT PIN SPRING
CONTACT (R.H.)
CONTACT (L.H.)
REMOVABLE CONNECTOR
---~"""'Jf
A-S8
45
'-'-'~_ _ _--...
0
~---A-37
DIAL READING AT 1800
LOWER SENSING PIN BOX AT
ITS LOW LIMIT - NO SELECTION.
SENSING
1800
PLATE 6B
PARTS NOMENCLATURE
A-3
A-'14
A-15
A-19
A-34
A-35
A-36
A-37
A-38
A-94
A-40
A-41
A-42
A-43
A-44
A-48
A-49
A- 50
A-51
A- 52
A-B6
A- 87
A-B8
A-B9
A-90
A-91
A-92
A-93
A-94
------1-+
A-
A-90-----~iWt!jtnuulr
A-91
I I
I I
I I
FRONT MAIN SHAFT
FRONT FEED ROLLS (UPPER)
FRONT FEED ROLLS (LOWER)
SENSING CHAMBER CARD STOP
LOWER SENSING PIN BOX
SELECTING PIN (LOWER PIN BOX)
LOCK SLIDE (LOWER PIN BOX)
DUMMY CAM
PIN LOCK MECHANISM
NO CARD SENSING PWNGER
PIN LOCK CONTROL LEVER
UPPER SENSING PIN BOX
SET - UP PIN (UPPER PIN BOX)
LOCK SLIDE (UPPER PIN BOX)
RETRACT BAIL
RETRACT CAM (UPPER PIN BOX)
RETRACT MECHANISM
COMB SPRING
CELL PLATE
SENSING SWITCH BOX
INTERMEDIATE SENSING PIN
COMPRESSION SPRING
PIN CAP
CONTACT PIN (NYLON)
CONTACT PIN SPRING
CONTACT (R.H,)
CONTACT (L.H,)
REMOVABLE CONNECTOR
r--------------
I
I
DIAL READING 293 0
SELECTING PINS ARE JUST CONTACTING
SET - UP PINS.
SENSING
293 0
PLATE
78
PARTS NOMENCLATURE
A-3
A-14
A'-15
A-19
A-20
A-21
A-34
A-35
A-36
A-37
A-38
A-39
A-40
A-41
A-42
A-43
A-44
A-46
A- 51
A-52
A-86
A-87
A-88
A-89
A-90
A-91
A-92
A-93
A-94
A-1l7
FRONT MAIN SHAFT
FRONT FEED ROLLS (UPPER)
FRONT FEED ROLLS (LOWER)
SENSING CHAMBER CARD STOP
FEED EJECT ROLL (UPPER)
FEED EJECT ROLL (LOWER)
LOWER SENSING PIN BOX
SELECTING PiN (LOWER PIN BOX)
LOCK SLIDE
(.
•
.)
DUMMY CAM
PIN LOCK MECHANISM
PIN LOCK TORSION SPRING
NO CARD SENSING PLUNGER
PIN LOCK CONTROL LEVER
UPPER SENSING PIN BOX
SET-UP PIN (UPPER PIN BOX)
LOCK SLIDE ( .
..)
CARD STOP MECHANISM
COMB SPRING
CELL PLATE
SENSING SWITCH BOX
INTERMEDIATE SENSING PIN
COMPRESSION SPRING
PIN CAP
CONTACT PIN (NYLON)
CONTACT PIN SPRING
CONTACT (R.H.)
CONTACT (L.H.)
REMOVABLE CONNECTOR
ECCENTRIC STRAP
DIAL READING AT 360°
LOWER SENSING PIN BOX AT
ITS UP LIMIT-SELECTION IS'
COMPLETED.
SENSING
PLATE 89
A-53
----11-4-
A-54
----II-+_
A-55
----II--l-'-
A-56
----ll--l-
A-57
---.:..u--l-::
PARTS NOMENCLATURE
A-53
A-54
A-55
A-56
M~
A -76
A-77
A-78
ARM
DIE SECTION
STRIPPER PLATE:
DIES
STRIPPER
PUNCHING
1800
PLATE
98
PARTS NOMENCLATURE
A-20
A-21
A-24
A-25
A-26
A-53
A-54
A-55
A-56
A-fi1
A-58
A-59
A-SO
A-61
A-52
A-53
A-54
A-55
A-66
A-67
A-SB
A-69
A-70
A-73
A-74
A-75
A-76
A-77
A-78
A-79
A-IIO
A-III
A"1I2
A -113
A-1I4
A-liS
A-1I6
A-liB
A-1I9
A-I20
PUNCHING
FEED E.ECT ROLL (UPPER)
FEED EJECT ROLL (LOWER)
PUNCHING CHAMBER CARD STOP
EJECT ROLL (UPPER)
EJECT ROLL (lOWER)
ACTUATOR
ACTUATOR ARMATURE
INTERPOSER ASSEMBLY
SCREW
ROCKER ARM
TOWER ROD
SET BAR. SECTION
TOWER ROD ASSEMBLY
SET BAR RETRACT CAM
CAM FOLLOWER ARM
LINK
LINK
RETRACT SHAFT
RETRACT BAIL OPERATING ARM
RETRACT BAIL
LOCK SLIDE
SET BAR PIN
COMB SPRING
TOWER RETRACT BAIL
INTERPOSER ASSEMBLY RESTClaE LINK
PUNCHES
DIE SECTION
STRIPPER PLATE
DIES
NON RESTORE ACTUATOR
MAIN SHAFT (REAR)
SKIP SOLENOID (L6)
LINK
SKIP INTERPOSER
STUD
SPRING
INTERPOSER ECCENTRIC
DIE SECTION CARD STOP CAM
CARD STOP MECHANISM
CAM FOLLOWER ARM
PLATE 10 B
PARTS NOMENCLATURE
A-20
A-21
A-24
A-25
A-26
A-53
A-54
A-55
A-56
A-57
A-58
A-59
A-60
A-68
A-69
A-71
A-72
A-73
A-74
A-75
A-76
A-77
A-78
A-79
A-80
A-81
A-82
A-83
A-84
A-85
A-IIO
FEED EJECT ROLL ~PPER~
FEED EJECT ROLL
LOWER
PUNCHING CHAMBER
RD S P
EJECT ROLL (UPPERl
EJECT ROLL (LOWER
ACTUATOR
ACTUATOR ARMATURE
INTERPOSER ASSEMBLY
SCREW
ROCKER ARM
TOWER ROD
SET BAR SECTION
TOWER ROD ASSEMBLY
LOCK SLIDE
SET 8AR PIN
TOWER RETRACT CAM
RETRACT MECHANISM
RETRACT BAIL
INTERPOSER ASSEM. RESTORING LINK
PUNCHES
DIE SECTION
STRIPPER PLATE
DIES
NON-RESTORE ACTUATOR
RESET SOLENOID (L 3)
YIELD SPRING
RESET BAIL
NON- RESET SOLENOID (L5)
TOWER RETRACT LATCH
LINK
REAR MAIN SHAFT
.,..,1-------- A-72
A-24--------·----------~f_------~--~1
A-II
DIAL READING 81°
PUNCHING 81°
PLATE liB
READY
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CALCULATE
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TERMINAL BOARD- LEFT SIDE
128
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PRINTS 1940317
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1940321
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TERMINAL BOARDS - RIGHT SIDE
PLATE
138
TOP
TOP
PUNCH POWER SUPPLY
PLATE
14 B
,
DIE CAR[} STOP
- - --c:At;:fI40Of20-SET 8AR RETRACT
CAM IQSe1e1
CAM
I~OOI22
C-ALCULATOR
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CIRCUIT DESCRIPTION
of the
ELECTRONIC COMPUTER
UNIVAC 60 & 120
COMPUTER
SECTION C
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DIVISION
OF
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RAND CORPORATION - .
315 FOURTH AVENUE
NEW YORK, N. Y.
ELECTRONIC COMPUTER
UNIVAC 60 & 120
Section -CCONTENTS
BASIC CIRCUIT DESIGNATIONS AND BLOCK CIRCUIT DIAGRAMS •••••••
Direct Coupled Amplifier •••••••••••••••••••••••••••••••
Positive Pulse Amplifier •••••••••••••••••••••••••••••••
Negative Pulse Amplifier •••••••••••••••••••••••••••••••
Gate •••••••••••••••••••••••••••••••••••••••••••••• ~ ••••
Trigger ••••••••••••••••••••••••••••••••••••••••••••••••
Flip - Flop •••••••••••••••••••••••••••., ••••••••••••••••
Multi-Vibrator •••••••••••••••• ; ••••••••••••••••••••••••
Scbm.itt Trigger •••••••••••••••••••••••••••••••• ·••••••••
A.C. Cathode Follower ••••••••••••••••••••••••••••••••••
D.C. Cathode Follower ••••••••••••••••••••••••••••••••••
Block Schematic Examples •••••••••••••••••••••••••••••••
WORK. CIRCU"ITS ••••••••••••••••• '•••••••••••••••••••.•••••••••••
C-1 - C-20
C-3
c-4
C-6
C-7
C-9
C-12
c-14
C-16
C-18
C-19
C-20
C-21 C-21
Electronic Accumulator •••••••••••••••••••••••••••••••••
Accumulator Shirt Operation ••••••••••••••••••••••••••••
Carry Input Generator ••••••••••••••••• , ••••••••••••••••
Decimal Registration and Shift Operation •••••••••••••••
Registration Input Generator (R.I.G.) ••••••••••••••••••
Input." Cirouit •••••••••••, •••••••••••••••••••••••••••••••
Double Input Check Circuit (Alpha Input) •••••••••••••••
C-Zl
Output Decoder •••••••••••••••••••• ·•••••••••••••••••••••
Storage ................................................ .
C-42
ADDITION AND SUBTRACTION CONTROL CIRCUITS •••••••••••••••••••
Addition Process (Work Sheet) ••••••••••••••••••••••••••
Subtraction Process (Work Sheet) •••••••••••••••••••••••
Calculator Zeroize •••••••••••••••••••••••••••••••••••••
Clamp . Circuits •••••••••••••••••••••••••••••••••••••••••
Minidend Registration ••••••••••••••••••• .' ••••••••••••••
Subvisor Registration ••••••••••••••••••••••••••••••••••
Result to Storage ••••••••••••••••••••••••••••••••••••••
Proof Minidend - Storage Registration ••••••••••••••••••
Proof Subvisor - Subvisor Registration •••••••••••••••••
Minidend Subtraction •••••••••••••••••••••••••••••••••••
Zero Check ••••••••••••••••••••••••••••••••••••••••.
I
••••
c-45
c-24
c.;..25
C-32
C-35
C-38
c.Jfo
e-46 - C-71
c-46
C-51
c-54
C-56
c-ry;
c-59
c-61
C-63
c-EM-
C-65
c-68
Com.plementize •••••••••••••.••••••••• "•••••••••••••••••••••
C-72 - 0-78
C-72
MULTIPLICATION CONTROL CIRCUITS ••••••••••••••••••••••••••••••
MUltiplication Process (Work Sheet) •••••••••••••••••••••
MUltiplication-Division Counter •••••••••••••••••••••••••
MUltiplication Process Call •••••••••••••••••••••••••••••
Multiplicat,ion Process .................................. _.
Sign CODlputation •••••••••••••••• "••••••••••••••••••••••••
C-79 - C-93
0-79
0-87
c-87
0-88
C-93
DIVISION CONTROL CIRCUITS ••••••••••••••••••••••••••••••••••••
Division Process (Work Sheet) •••••••••••••••••••••••••••
Division Process Call ••••••••••••••••••••••••.•••••••••••
Division Process ......................................... .
c-94 - 0-1 cY9
0-9+
0-102
C';:lO+
ZERO FACTOR CONTROL CIRCUIT •.•.••••••••••••••••••••••••••••••••
Zero Factor ............................................. .
Sort or Stop (N + 0 or 0 + 0) .......................•...
0-110 - C-118
0-110
0-117
FllN'CTION CIRCUITS ••••.
C-119 - c-l24
0-119
0-124
COMPLl!J.fl!:NTIZE CONTROL CIRCUITS •••••••••••••••••••••••••••••••
8
0
••••••••0
• • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
Output Chassis #1 and =/12 ••••••••••••••••••••••••••••••••
Selector Relay Control ••••••••••••••••••••••••••••••••••
INTEGRATED CIRCUITS ••••••••••••••••••••••••••••••••••••••••••
Te st COllIlter. -• •••••••••••• "••••••••••••••••••••••••••••••
Voltage Abnormality Detector ••••••••••••••••••••••••••••
Automatic Circuit Timer •••••••••••••••••••••••••••••••••
Program Test Panel (P.T.P.) •••••••••••••••••••••••••••••
B2 ~ B5 Zeroize •••••••••• ·•••••••••••••••••••••••••••••••
KB Recovery and Decimal Control •••••••••••••••••••••••••
Plugboard Control ••••••••••••,•••••.••••••••••••••••••••••
Control Ring ............................................ .
Process Control •••••••••••••••••••••••••••••••••••••••• ~
Conditioning CCT for Shifts ••·•••••••••••••••••••••••••••
Sign Bias-Addition and Subtraction ••••••••••••••••••••••
Minus Factor - Addition and Subtraction •••••••••••••••••
Sign Bias-Division and Multiplication •••••••••••••••••••
(-) Storage Bit Operation •••••••••••••• ·•••••••••••••••••
-40v Regulated Supply •••••••••••••••••••••••••••••••.••••
Cathode Controls on GX ••••••••••••••••••••••••••••••••••
Step Trigger ar:.d Gate ••••••••••••••••••••••••••• '••••••••
Flip - Flop Delays •• ~ •••••••••••••••••••••••••••••••••••
Calew.ator Crank-Up ••••••••••••••••••••••••••••••••• ,••••
Power Supply Voltages •••••••••••••••••••••••••••••••••••
Punch Power Supply •••••••••••••••"•••••••••••••••••••••••
and Brake Operation ••••••••••••••••••••••••
Sort - Skip and Set .Hold ••••••••••• '•••••••••••••••••••••
Reproduce and Secondary Reproduce •••••••••••••••••••••••
Pun.ch~Clutch
.Power S-upply •••••••••••••••••••••••••••••••••• ·•••••••• ~ •
Power Control •••••••••••••••••••••••••••••••••••••••••••
Computer Wiring Distribution ••••••••••••••••••••••••••••
.AI.,PHA STAGE INDEX ••••••••••••••••••••••••••••.••••••••••••••••
0-125 - 0-170
0-125
0-1'Zl
0-129
0-130
0-133
C-134
C-136
0-138
0-139
C-11+1
0-143
0-1lf4
0-145
c-148
0-149
0-150
0-151
0-152
C-153
C-156
0-159
0-160
0-163
0-165
0-167
0-169
C-170
0-171 - C-176
PLATE DRAWING INDEX
Plate No.
Addition and Subtraction ••••••
Accumulator Shift Mechanism ••••
Carry Input Generator •••••.•••••••••••••••
Decimal Registration and Shift Operation ••
Registration Input Generator •.•••••
1C
2C
3C
4c
5c
6c
Input Circu:tt .............. .
Double Input (Alpha) Check ••
Output Decoder ••••••••..•••
Storage Bit Controls •••••••
7C
8c
9C
Storage Control ...........•......
10C
Calculator Zeroize •••
Clamp Circuits •••••••
Minidend Registration ••••.•••••
Subvisor Registration ••
11 C
Result to Storage .................. .
15C
16c
12C
13C
14c
Proof Minidend - Storage Registration •••••.••
Proof Subvisor - Subvisor Registration ••••••••••
Minidend Subtraction ••••••••••••••••••••••
17C
18c
19C
Zero Check ............................ .
Complementize ••••••••••••••••••••
Multiplication Division Counter ••••••
Multiplication Process Call •••
Multiplication Process ••••••••
Division Process CalL •••••
Division Process ••••••••••.•
0F MUltiplication - Division •••••.•••••
Zero Factor - Sort and Trip ••••••••••••••••
Sort I, Set I and Clear ••••
Select I Step •••••••••••••••
.....
Trip Circuit ........... '.- ... .
Selector Relay Control •••.••
Te st C01l11ter ...•....•.
Co
0
20C
21C
22C
..
............ .
...... ....
23C
2)+C
250
·...
.....
26c
27C
28c
29C
30C
31C
32C
•••
Voltage Abnormality Detector •••
Automatic Circuit Timer ••••••••
Program Test Panel Operation •.•••••.
B2 - B5 Zeroize ••••••.••••••••
KB Recovery and Decimal Control ••
Plugboard Control ••••
Control Ring .••••••••
Process ControL ••
Conditioning CCT for Shifts.
Sign Bias •.••.•••••••••••.•••••
Sign Bias - Addition and Subtraction •••
Minus Factor - Addition and Subtraction.
Sign Bias - Division and Multiplication.
(-) Storage Bit Operation.
-40v Regulated Supply •••
Cathode Controls on CX •.
Step Trigger and Gate •••
.............. .
Calculator Crank Up ••••••.••••
Power Supply Minus Voltages •.•
Power Supply Plus Voltages ••••
33C
34c
..... ... ....... ...
.......
·.....
'
42C
43C
44c
.... ...... ·.....
... .....
....
.
....
35c
36c
37C
38c
39C
ltoc
41C
45c
46c
47C
48c
49C
.,..
50C
51 C
52C
Punch Power Supply •••••••••••••••• ,. ••.••••••••••••••••••• 53C
Punch Clutch and Brake Operation ••••••••••••••••••••••••
Sort, Skip and Set Hold •••••••••••••••••••••••••••••••••
Reproduce and Secondary Reproduce •••••••••••••••••••••••
Calculator Front View •••••••••••••••••••••••••••••••••••
Calculator Rear,View ••••••••••••••••••••••••••••••••••••
P ower Supply ................................ '••••• '••••••••
DC Interlock Relay Assembly •••••••••••••••••••••••••••••
:PTP and Power Control •••••••••••••••••••••••••••••••••••
Power Control - Upper •••••••••••••
ea • . • • • • • • • • • • • • • • • • • • •
Power Control - Lower •••••••••••••••••••••••••••••••••••
Filament Transformers and Fan Motors ••••••••••••••••••••
Computer Wiring Distribution ••••••••••••••••••••••••••••
STA Chassis •••••••••••••••••••.••••••••••••••••••••••••••
Storage Door ••••••••••••••••• ,•••••''••••••••••••••••••••••
60 and 120 Field Input Neons ••••••••••••••••••••••••••••
Decimal Neon Mixer Board •••••••••••••••••••••• '••••••••••
Constant Neon Panel ••••••••••· •••••••••••••••••••••••••••
Selector Relay Assembly •••••••••••••••••••••••••••••••••
Restart Switch and TCR Panel ••••••••••••••••••••••••••••
Chassis Removal •••••••••••••••••••••••••••••••••••••••••
Accumulator •••••••••••••••••••••••••••• ACC ••••••••••••••
Check Counter •••••••••••••••••••••••••• CCT ••••••••••••••
Control •••••••••••••••••••••••••••••••• CTL .............. .
Decimal Control •••••••••••••••••••••••• DCL ••••••••••••••
Decimal Counter ••••.•••••••••••••••••••• DCR ••••••••••••••
Input-Output ••••••••••••••••••••••••••• 10 •••••••••••••• -.
Keyboard Bias •••••••••••••••••••••••••• KB •••••••••••••••
RultiplicatJon - Division •••••••••••••• MD •••••••••••••••
Output Control I •••••.•.....•..•••••.•• OCL1 •••••••••••••
Output Control II •••••••••••••••••••••• OCL2 •••••••••••••
Zero Factor ••••••• eo • • • • • • • • • • • • • • • • • • • • ¢F •••••••••••••••
Registration Input Generator ••••••••••• RIG ••••••••••••••
Sign Bias •••••••••••••••••••••••••••••• SB~ ••••••••••••••
STA~ ••••••••••••••••••••••••••••••••••• STA ••••••••••••••
Selector Power ••••••••••••••••••••••••• SEP ••••••••••••••
Step Control ••••••••••••••••••••••••••• SCL ••••••••••••••
Step Sequence •••••••••••••••••••••••••• SS •••••••••••••••
Storage Control ••••••••••••••••••••• '••• STL ••••••••••••••
Test Counter ••••••••••••••••••••••••••• TCR ••••••••••••••
Voltage Abnormality Detector ••••••••••• VAD ••••••••••••••
Zeroize Control •••••••••••••••••••••••• ZCL ••••••••••••••
Schemat~c Diagram - Storage and Control •••••••••••••••••
Field Board Explanatory Drawing •••••••••••••••••••••••••
Program Board Explanatory Drawing •••••••••••••••••••••••
Printed in U. S. A.
54C
55C
56C
57C
58C
59C
60C
61C
62C
63C
64C
65C
66C
67C
68C
69C
70C
71C
72C
73C
74C
75C
76C
77C
78C
79C
80C
81C
82C
83C
84C
85C
86C
87C
88C
89C
90C
91C
92C
93C
94C
95C
96C
97C
+ 150
+150
10K
10K
t---RA
LA.--4
10K
!OK
Lp----'~
K
RID RESISTOR';
RARELY SHOWN
LC---:-1
LI
20 UUF J50K
270K
150K
160K
.J60K
RA
LP
LC
~RC
20 UUf
270K
___..NVV----,f
LO--.J
LA
I+-~-RP
RP
RC
LI
RI
L O----'--.,.--.--~~R 0
LB K RB
RI
"----RO
RB
LB
FIGURE A
BASIC CIRCUIT DESIGNATIONS
AND
BLOCK SCHEMATIC DIAGRAMS
1. Cage type designation":
A)
Letters represent a general cage type and the number represents a variation
of the general cage type.
B)
Letter definitions:
LETTER
NOTES
STAGE
Grid return to -15 Volts unless
otherwise specified.
A
Pulse Amplifier
C
A.C. Cathode follower
D
D.C. Amplifier
F
Flip-Flop
G
Gate
Divider return to -150 Volts
unless otherwise specified.
K
D.C. Cathode follower
Divider return to -150 Volts
unless otherwise specified.
L
Limiter
M
Multi-Vibrator
C-1
Divider return to -150 Volts
unless otherwise specified.
R
Regulator Type
RC
MISC.
S
Schmitt Trigger
T
Trigger
Any cage not defined by other cage
. types.
x
Designates tube with no associated
cage.
(.:.)
C.
A (-)-1
Designates unused cage section.
Combination of letter denotes combination of various cage types.
1.
2.
3.
4.
5.
GG DA L (-) (-) A S
-
Double Gate
D.C. and A.C. Amplifier
Single Limiter
Single A.C. Amplifier
Schmitt Trigger
D.
Left letter designates section of cage used with left tube section.
E.
Right letter designates section of cage used with right tube section.
F.
Single letter with (-) designates cage design to be used with half section of tube.
G.
Single letter designates both section of
tion.
H.
Left and right sections of tubes a.re defined as follows:
TUBE
LEFT SECTION
RIGHT SECTION
TYPE
G K P H
G K P H
598+
6 7
~
4
524
6AL5
I.
and tube are used for a single func-
~age
5 7 2 3
-
1 7 3
Grid Resistor Designations
47KD330K(G'VEN)
680nD22K
No Symbol indicates a 680
A T~iangle Symbol
Q
indicat~s
Grid Resistor.
a 22K Grid Resistor
A Square Symbol indicates a 471\ Grid Resistor
A Dot Symbol is always accompanied by the given Grid Resistor Value.
C-2
+150
22K
PLATE LOAD
r.
---1 'LI
1- 5964
160 K
OUTPU~
"B" LP
'~\
NON-CONDUCTING +150
PLATE VOLTAGE
AT POINT liB"
INPUT
270K
CONDUCTING +40
CONDUCTING LEVEL 0 GRID VOLTAGE
AT POINT "A\\
-150
BIAS POINT
CUTOff LEVEL -30
LP
LI
00- 8
FIGURE CI
DIRECT COUPLED AMPLIFIER
The .D. C. Amplifier utilizes one half of a dUal triode tube and is connected as shown
, on Figure 1. Since the input to the grid is a resistive input, a pulse or short
duration voltage change will have no effect upon the grid. Any change at the grid
will be maintained for a definite length of time.
Assuming the input to the grid is low, the level of the grid is below cutoff, which
will prevent any conduction between the cathode and plate. In this state, the plate
potential will be +150 volts, since there is no current flow in the plate circuit and
subsequent'vo1tage drop. By raising the level of the grid to a point above cutoff,
conduction will occur. With a current flow in the plate circuit and resulting voltage drop across the plate load resistor, the potential of the plate will drop to about
+40 volts. Now, by lowering the grid below cutoff, the plate will rise again to +150
volts. See Figure 1 for plate levels.
The D. C. Amplifier has two stable states:
1.
Conduction and current flow
Grid high - Plate low
2.
No conduction - no current flow
Grid Ibw- Plate high
C-3
+150
~5964
OR
-'
22K
PLATE LOAD
LP
OUTPU;:-Y-
"B" 22 UUFD tiE"
I I - - -.......--If-
>
NON- CONDUCTING + 1.50
PLATE VOl.TAGE
AT POINT "A"
LC
INPUT
CONDUCTING +40 ---- --------------
1.50K
CONDUCTING LEVEL 0 ---
"C"
-1.5
BIAS POINT
-
--------- - --GRID VOLTAGE
AT POINT"E"
CUTOFF LEVEL-15
LP
LC
AA- 6
FIGURE C2
POSITIVE PULSE AMPLIFI ER
A Positive Pulse Amplifier consists of a triode tube and other components as drawn in
Figure 2.
First, to analyze its normal or non-conducting state, note that its cathode is tied to
ground (0 voltage). The grid is tied to -15 volts through a l50K resistor. In this
state, the grid voltage is of low enough potential to suppress or repel any electron
emission from the cathode.
The plate is tied to a +150 volts through a 22K resistor and, in turn, to an external
circuit which it is to control~ Since the grid was of sufficient potential to suppress any electron flow i'rom the cathode to the plate, there is no electron flow in
the plat, circuit. At this state, the plate circuit has no current flow andthe potential voltage) is present, but inactive. A +150 volt source is located at Point A.
In the Computer, the function this amplifier is to accomplish will operate only on a
change of potential; therefore, the condition of the tube previously explained will
be of no value to us at this time.
It is necessary to chauge the voltage level of the plate to make use of the tube, let
us see how this is done. At Point B, a rising potential, step wave or pulse, is applied.
In a condenser, an equal and opposite charge will develop when a potential is applied.
This positive potential is reflected on the grid, causing its level to be positive
with respects to the cathode and thereby, allow conduction to occur. The electrons
now flow through the l5OKresistor to the opposite side of the condenser to equalize
its plates.
The plate of the capacitor on the grid side now wants to return to its original value
of -15 volts; but, because of the 150K resistor in the circuit, this recovery is
C-4
delayed. This delay allows the grid to pass electrons from the cathode to the plate
for a longer period of time than if the 150K resistor were not in the circuit. The
electrons flowing from the cathode to the plate cause current to flow in the plate
circuit. The plate is tied to +150 volts through a 22K resistor. The current flowing in this plate circuit causes a voltage drop through the 22K resistor which, in
Computer tubes, drops the value at Point nAn from +150 volts to about +40 volts.
The above condition was only momentary while the condenser was attempting to equalize
its plates. Eventually (time being in micro seconds) the condenser will equalize
and there will be no electron flow through the 150K resistor in the grid circuit.
Without this electron flow, there will be no loss of potential through the resistor
and, therefore, Point E will return to its original value (-15). The grid is now
lowered to a negative value SUfficient to stop the flow of electrons from the cathode
to the plate. Since there will be no electron flow through the 22K resistor to the
+150 volt source at the plate, there will not be any 108s of potential through it and
consequently, Point! will rise to +150 volts.
A negative pulse or step wave at Point B will only succeed in driving the grid more
negative than normal. The tube was normally cutoff so the more negative value on
the grid causes no reflection at the plate. This negative pulse is said to be
rejected.
C-5
+150
NON-CONDUCTING+1S0
--
22K
PLATE LOAD~
!S964
L
OR
Y
I~
>
UB" LP
22UUFD
LC
I
----------PLATE VOLTAGE
AT POI NT "6"
~'-
OUTPUT
CONDUCTI NG
+40
I----r---j
CONDUCTING LEVELO
INPUT
GRID VOLTAGE
AT POINT II Ell
CUT OFF LEVEL -15 -+150
BIAS POINT
LP
LC
AA-I0
I
B+
FIGURE 03
NEGATIVE PULSE AM PLI FI ER
A Negative Pulse Amplifier is basically the same as the Positive Pulse type, except
that its "bias point" is connected to a positive voltage source as shown in Figure 3.
By connecting its grid to a positive source, conduction is maintained continuously.
(The Positive Pulse Amplifier was normally non-conducting). A voltage change or pulse
at Point A to a lower voltage than that normally applied would bring the grid to a
value low-enough to stop conduction. This voltage change on the grid occurs due to the
electron flow through the 150K grid resistor while the condenser is attempting to
equalize its plates. The loss of potential through the resistor is reflected on the
grid recovery rate.
It was stated before that the tube was normally conducting, but now the grid was lowered and stopped this conduction. During its conduction range, the current flowed
through the plate load resistor of 22K Ohms and caused a voltage drop.
Point B during this period will maintain a potential of about +40 volts, a drop of
110 volts through this resistor. Now with the grid value low enough to stop conduction, there will be no electron flow through the 22K resistor in the plate circuit.
With no electron flow here, there will not be any voltage drop and Point B will rise
to a +150 volts.
The condenser will eventually equalize its plates and there will be no loss of voltage through the 150K grid resistor due to no electron flow through it. The grid will
now rise and allow conduction to take place. Again, there will be a loss through the
plate resistor and Point ~ will drop to about +40 volts.
C-6
·
I
NON-CONDUCTING+150f----,
PLATE VOLTAGE
ATPOINT'~'
CONDUCTING+40 _----
~5964
CONDUCTING LEVELO
OPEN GATE LEVEL-25
22K
PLATE LOAD
LP
OUTPUTr
GRID VOLTAGE
AT POINT "E"
J.50K
CLOSED GATE LEVEL -60
~
LI
INPUT
l80K
160K
-150
LP
LC
LI
GG-10
FIGURE 04
GATE
A Gate utilizes one half of a dual triode and its internal connections are shown in
Figure 4.
With the cathode connected to ground and the plate to +150 volts,it can be seen
that by controlling the grid potential, conduction of the tube may be controlled. By
connecting the grid to -150 volts, the tube is normally cutoff. In this state, there
will be no current flow and no voltage drop across the plate load resistor which will
maintain a plate level of +150 volts at Point A.
The first controlling factor applied to the grid is the input at the resistive input
point. By raising the potential level at this point, the current flow through·the
bias resistor will cause a voltage drop across it to raise the bias point from -150
volts to about -25 volts. Since the cutoff point of the tube is about -8 volts, the
grid level now is still capable of stopping any current flow from cathode to plate.
It is this resistive point that is the controlling factor of the Gate. By raising the
level at the resistive point of one Gate, we may have a common pulse at the capacitive point hit a series of Gates. Since only one Gate has been conditioned, only that
plate wIll show a pulse while all the other Gates will not have any changes reflected
at their plate.
When the capacitive input receives a positive potential change at one of its plates,
the opposite plate starts to charge itself. During this charging time the grid
potential is raised above cutoff to .about 0 volts. The combination of a high
resistive input and a positive pulse at the capacitive point allows the grid to permit
conduction to occur.
.
0-7
The voltage rise caused b,y the charging of the capacitor will be only momentary and
governed by the (R-C) resistive and capacitive component values. This means that the
grid level will rise to a volts only for an instant then drop to -25 volts again.
This momentary change at the grid will allow conduction to take place between the cathode and plate allowing current to flow in the plate circuit. The current flow through
the plate load resistor will cause a voltage drop across it, lowering the potential
level of the plate to about +40 volts. Since the current will flow only for an instant, the drop across the plate load resistor willJVentually decrease and the plate
level will rise to +150 volts again.
1.
Resistive point level raised causing grid to rise to -25
volts - no conduction.
2.
Pulse at capacitive point - grid level raised to 0 volts. Conduction oCcurs.
3.
Capacitor charging - grid level gradually going more negative.- Conduction still takes place.
4.
Capacitor fully charged - grid level lowers to -25 volts, no conduction.
5.
Grid level at -25 volts - plate at +150 volts.
C-8
+150
I
I
VOLTS
LG
RG
0:
GRID CUTOFF
-10 ------- ---------------------------_ 30 R G
I'----=L::.,;G:-_ _
20K
100
UUFD
100
UUFD
150K
2~2
UUFD
1 UUFD
-90
INPUT
150K
FjP
-90
ZEROIZING
CONTROL
INPUT
FIGURE C5
TRIGGER
The Trigger is a double triode tube with added circuit components to control its conduction periods as shown in Figure 5. The tube itself is under a common envelope with
component parts connected to it, each independent of the other.
Each triode has its cathodes connected together, then to ground. Its individual
plates are, in turn, connected to a +150 volt source through individual 20K resistors.
As in any circuit, to maintain a current flow there must be a potential difference to
cause th~ electrons to flow. In this case, there is a difference of ground (0 volts),
the cathode potential, and a +150 volt source at the plate.
By referring to the circuit diagram, there are many resistors and
condenser~ added
to form what is called a Trigger. From each plate a line has been connected to a -90
volt source, through two re$listors. Discarding the condenser at this time, the potential values at Points.A and B can be found. A Trigger has two stable states. The
first stable state is with the left triode conducting. This means that the left
grid must have a positive value of about 0 volts. How is that value maintained? A
sequence of voltage changes at certain points, due to voltage loss through resistors,
must be followed to find the two grid values. The left plate conducting holds the
right grid below cutoff and the right side is not conducting.
1. When the left side conducts, there is .current flow. This current
flow, through the 20K resistor, results in a voltage drop, which
will bring the plate potential to a plus .40 volt value.
0-9
2.
Between the +40 volt plate point and the -90 volt bias point, 130
volts must be lost. If this is so, an equal amount must be lost in
each resistor since their values are the same, l50K. This maintains
Point~B at about -25 volts.
3.
The right grid is below cutoff, therefore, the right plate must be
high, since there is no voltage drop across the plate load resistor.
Two l50K resistors are in series between +150 volts and -90 volts,
therefore, voltage lost will be such that Point C will maintain
a level of about +30 volts. This in turn, connected to the left
grid maintaining its level so that conduction will take place.
The Trigger is now in one of its stable states and will remain this way unless pulsed
from some external source.
With the Trigger in this stable state, its left plate is at +40 volts and its right
plate at +150 volts. These voltage levels are used to control the input point of a
gate or will enable a neon to fire, showing the Trigger's position.
Assume a negative pulse is received at the input point. This pulse will create a
potential difference across the condenser, which will charge it. During the charging
period of both condensers, current will flow. The subsequent current flow, during the
charging period of the condenser, will result in Points B and C dropping. These points
will drop to a point where both grids will be cutoff. As shown in Figure 5, the more
negative potential will rise sooner than that negative potential which was controlling
the left grid. At point 1 on the graph, the condensers are fully charged and Points
B and C will begin to recover. Point Bor the right grid, had a more negative charge
than Point C, or the left grid. The operation of the circuit is such that the more
negatively charged condenser has a faster recovery rate.
Point B reaching cutoff causes the right plate to start conduction which causes a drop
in voltage on the right divider at Point C. Therefore, before Point C could recover
to the cutoff level its voltage is lowered because of conduction in the right plate
circuit. The right grid, allowing conduction to take place, causes Point D to drop
to +40 volts due to the current flow through the 20K plate load resistor resulting in
a 110 volt drop across it. The voltage drop between Point D (+40 volts) and the bias
point (-90 volts) must equal the 130 volt difference. Since both resistors are equal,
the drops will be equal. The left grid is now cutoff.
A summary of the past operation will show that a pulse at the input point lowered both
grid levels below cutoff. Since the most negative value had a more rapid rise than
the other, the right grid allowed conduction to occur. This in turn, created a drop
across the 20K plate load resistor, lowers Point D to +40 volts, which in turn, lowered Point C to about -25 volts. The left grid being tied to Point C is now cutoff,
allowing conduction to be maintained on the right side. This is the other stable state
which the Trigger will maintain.
If the input point were pulsed again, Points B and C would have the opposite values
impressed upon them and result in Point C rising more rapidly. This would allow the
left grid to rise and conduction would occur. The subsequent drop across the plate
load resistor for the left p1ate would result in Point B maintaining a -25 volts.
The Trigger would now be conductL~g on the left side and be in its original stable
state.
C-10
The condensers which are connected between Points D and C and Po~ts A and B are to
create a faster reflection of any voltage changes to Points Band C. This condenser
action is necessary due to the time required for a voltage to drop across the 150K
resistor.
NOTE:
It is also possible to trigger this circuit b.r a negative pulse input on the non-conducting side of the Trigger at either plate;
Only a negative pulse, or negative step wave at a capacitive point,
or a negative pulse at a plate or divider point will trigger this
circuit.
C-ll
+150
+150
20K
20K
+40
---_
...
OUTPUT RP
150K
"RII
~
7
UUFD
270K
.•~---I I
GRID LEVEL
-15
-90
+150
,
,,
(IJ
LP
RP
F-I
-8
Be
-100
I
---
lOISCHARGE
CURVE OF "RC"
COMPONENTS
FIGURE C6
FLIP FLOP
A Flip-Flop is a double triode tube with connected components to maintain the two triodes in different states as shown in Figure 6:
The basic principle is to cause one side (one triode) to conduct for a predetermined
time while the other side (one triode) is not conducting, then the two triodes will
revert back to their original condition. The time that the opposite side conducts
varies with the application it is to be used for.
In the normal state of a Flip-Flop, the left plate is conducting and is of a +40 volt
value due to the current flow through the 20K resistor and subsequent voltage drop
across it. Due to the current flow through the l50K resistor, the potential is further decreased low enough to maintain the right grid below cutoff, the right plate is
not conducting and is at a +150 volt potential. In its normal state, the right plate
(right triode) is ~intained at +150 volts. At the same time condenser CIS plates are
equalized, the +150 volts is impressed at resistor "R1t. Due to the small current flow
from the left grid to the +150 volt supply there will be a voltage drop across ''R''.
This drop will keep the left grid just above cutoff, maintaining. the left side (left
triode) conducting.
Under the above conditions the Flip-Flop is said to be in a normally stationary state,
i.e. conduction between the left cathode and plate with the right side not conducting.
A n~gative pulse (a drop of potential to a lower value than it originally was) at the
47 uufd. condenser, will cause the plates of this condenser to become unequal. Since
the opposite plate must have an equal and opposite charge, electrons must travel in
an attempt to adjust the other plate. The electron flow now created will cause a
C-12
voltage drop across resistor
grid to drop below cut.off.
"R."
"Which will cause the potential applied to the left
The left side is now not conducting. With the current flow through the 20K plate load
resistor and 150K bias resIstor extremely sm.all, the +150 volts will ra1.se the divider
point, which in turn
raise the right grid.
The value of the right grid is now high enough to alloy conduction. The electron floy
between the cathode and plate now causes electron flow through the 20K plate load
resistor which will cause a voltage drop across it. This will bring the right plate
down to about +40 volts.
NOTE~
The 1!'lip-l"lop bas been 'iKicked n
Since the condenser "C n plates noy have become unequalized electrons must floy through
resistor 'taft in an attempt. to adjust its plates. The electron flow through nR"
causes the +150 volts to drop to a
value which will in turn be impressed at
the left grid bringing it below cut-off9 The electron flow through "Rn and the subsequent voltage drop will last only as long as i t ta.'lces condenser ne n to discharge
and equalize its plates.
The current flow through
returns the condenser to its original state and raises
the left grid above cutoff. The time necessary for condenser HC n to regain its
original static condition depends upon the size of URWf and nC tt •
Assuming condenser nC!' has become discharged, there 'Will be less voltage drop across
tlR" (exclud1ng the normal grid to plate current flow) and the left grid will rise
above cutoff al101,.ring conduction to occur at the left plate. Current flow through the
left platets 20K resistor and the 150K resistor yill now bring the right grid below
cutoff cutting off conduction.. The right plate1s potential noy rises to +150 volts
due to no current floy. A change of +40 volts to +150 volts is now impressed at one
plate of condenser nC".
Since the plates of the condenser are attempting to rise to +150 volts, the voltage
drop across "Rn will not be sttfflclent to
the grid left grid below cutoff.
NOTE:
The Flip-li'lop has now "Ret,llrnedn
By following the above
l..
the follm..l.ng results were obtained.
(
A
2.
wmchwas at +40 volts, stopped conducting and rose to
3.
4.
NOTE:
was received at the right condenser.
was at
After a
condj:tions
It 1.8 also pos,sible
, started conducting and dropped
tton discharging rate) the above
a negati.ve pulse input on
the right plat:e or
On!l: a negative
or negative
Vdve at th'e right capacitive point,
or a negative pulse at
right plate or divider point will trigger this
cireuit.
LEFT
PLATE
+150
"A"
20K
-CPI
"~.
C2
I
20K
:'r'-
- --+-------'
+150 ---+40
160K
"0"
RP
RIGHT
PLATE
"0 1'
270
UUFO
160K "B"
INPUT
270K
270K
~~~'--.-=M_-....:'_--,
-150
RP
FIGURE C7
MULTIVIBRATOR
A Multi-Vibrator is designed to generate voltage variations (Square Wave Forms) at
specific intervals. These square waves are the result of a plate conducting or not
conducting, since a plate conducting will cause it to drop to +40 volts and a nonconducting plate will maintain a +150 volts potential.
The pulses generated are referred to as the "frequency output." This is shown by the
figure below which denotes the change of voltage per second, and is governed by the
R. C. (Resistive-Capacitive) components in a Multi-Vibrator.
l~_
The inoperative state of this circuit will be explained to show the various potential
values at the controlling points.
With a low input, the Multi-Vibrator is considered inoperative. At the left input
point a +40 volts is applied. This will hold Point B at a -30 volts, the right grid
being below cutoff allows the right plate to maintain a +150 volts. Assuming the
input to have been constant with Cl in a discharged state, Point C will maintain a
+39 volts through the 160K shunt resistor. This will in turn hold the left grid above
cutoff and allow conduction at the left plate. This current flow through the plate
load resistor drops Point A to a +40 volts. Since this condition has existed for a
time interval, condenser C2 is in a charged state and will have no effect upon Point B.
These are the conditions which exist when a low input is applied.
is actually shut off.
C-14
The Multi-Vibrator
By applTlng a high potential at the input point, the Multi-Vibrator will generate
pulses at its designed frequency. With the input at a high potential, Point B will
be raised to +30 volts which will in turn, raise the right grid above cutoff. This
will create a current flow in the right plate circuit dropping Point D to +40 volts.
This change of potential on the right plate will charge condenser C1. The condenser
C1 will charge to the potential now applied, and while charging, will cause a further drop across the 160K shunt resistor. Due to increased current flow and subsequent drop, Point C will lower the left grid below cutoff. Point C will maintain
the left grid below cutoff as long as C1 is charging. The left plate has .been cutoff and Point A rises to a +150 volts. The potential now impressed at Point A will
tend to maintain Point B at a positive value through condenser C2.
Condenser 01 eventuallybecames charged and the added current flow through the shunt
resistor ceases, raising Point C back to a +39 volts. Since the left grid is connected to this point it will be raised above cutoff allowing conduction to occur.
Current flow in the left plate circuit will cause Point A to drop to a +40 volts.
This drop at Point A will be reflected upon the lower plate of condenser C2 as a
110 volt decrease. (This is the equal and opposite value which was changed on the
upper plate). The value impressed upon the lower plate will create a current flow
in its attempt to equalize itself. This current will maintain Point B at a potential sufficient to cutoff the right grid. Point B will hold the right grid below
cutoff as long as condenser C2 is charging.
When the condenser 02 becomes charged Point B will rise to +30 volts and the MultiVibrator will revert to conducting on the right side as previously explained. The
conditions described will continually change providing a high input is maintained.
This will result inthe changing of the right and left plates values to form a square
wave output at Points A and. D.
c15
FIGURE C8
SCHMITT TRIGGER
The Schmitt Trigger differs from the regular type Trigger in that its input point is
resistive rather than capacitive as shown in Figure 8. Its input must also be maintained at one level and since it has a resistive input, a pulse will not effect it.
This type Trigger is designed to change a slowly rising input to a sharply risjng output.
The first stable condition to be considered is with a high input resulting in a high
left plate and a low right plate. A low input will result in a low left plate and
a high right plate.
After studying this Trigger circuit, the first stable condition will be reviewed.
Assuming the input to be high, Point B will maintain a +30 volt potential. This
+30 volts which controls the right grid will, in turn, allow conduction to occur at
the right plate. The current flow at the right plate through the 20K plate load
resistor to +150 volts, will drop Point D to about +40 volts. This drop to +40 will
create a subsequent loss lowering Point C to a -28 volts. This in turn, is connected
to the left grid which will cutoff the left side allowing the left plate to maintain
a +150 volts.
Under the above conditions, the results below occurred.
1.
2.
39
Input high (+150 volts)
Right grid high (+30 volts)
Right plate low (+40 volts)
C-16
4. Left grid. low (-28 volts)
5. Left plate high (+150 volts)
The second stable state of this Trigger will occur when the input point drops to
about +40 volts. This change will drop Point B to a -28 volts which will in turn
cutoff the right side.
The lowering of the right grid results in the right plate rising to a +150 volts since
there is no current flow in the plate circuit and no drop across the plate load resistor. The right plate has risen from +40 to +150 volts/which will charge Point C to
+33 volts. The 47 mmfd condenser is inserted to reflect this change more rapidly
than through the resistor. Point C rising rapidly to +33 volts will bring the left
grid high enough to allow conduction at the left plate. The subsequent drop across
the 20K plate load resistor will drop Point A to a +40 volts. The 22 mmfd condenser
is inserted to create a sharper rise at Point B.
Under the above conditions, the results below occurred.
1. Input low (+40 volts)
2. Right grid low (-28 volts)
3. Right plate high (+150 volts)
4. Left grid high (+33 volts)
5. Left plate low (+40 volts)
NOTE:
It is possible to trigger a Schmitt Trigger b.r controlling the voltage
level on the right plate. Assume a voltage level of +40 volts is impressed on the right plate when the left resistive input is also +40
volts. The +40 volt level on the right plate will pull down the right
voltage divider and cause the left grid to drop below cutoff resulting
in a high level, +150 volts, on the left plate. This condition is similar
to that which occurs when the left resistive input is high, +150 volts.
C-17
+1.50
LC
INPUT
LC
.lOOUUF
~
I
680 Jl
~NP~
CATHODE~
220K
10K
!\
OUTPUT
K
33K
J.2K
.1.0 K
-1.50
LC
-90
I
I
C-2
I
I
K
FIGURE C9
A.C. CATHODE FOLLOWER
The A. C. Cathode Follower generally employs both sides of a duo-triode as show in
Figure 9.
In this circuit the input is capacitive and reflected on the grids. The output is
reflected at the cathode instead of at the plate. The load resistor for the tube is
in the cathode circuit. The tube has slightly less than unity amplification factor
when used as shown. It has a low impedance output and is usually used where the output signal is to be used in many stages.
The A. C. Cathode Follower, in its stable state, has a grid control which is usually
sufficient to maL~tain the tube cutoff. This means that Point K will maintain approximately the cathode return level.
A positive pulse or step wave applied at the capacitive point will ralse the grids
of the tube causing conduction to occur. The length of time the tube conducts, is
controlled by the capacitive resistive components of the circuit.
When the grid is raised electron flow can occur from -90, through the 12K resistor,
through the tube to the +150 supply. The current flow through the 12K resistor causes
a voltage drop so that point K will rise, releasing a positive pulse at the output
approximately equal in magnitude to the input voltage magnitude.
C-18
+1.50
LI
9.1K
47
INPUT
OUTPUT K
220K
8.2K
2W
-1.50
IN52
-60
LI
I
I
K-3
I
I
I
K
FIGUREC 10
D.C. CATHODE· FOLLOWER
The D. C. Cathode Follower generally employs both sides of a duo-triode
Figure 10.
~s
shown in
In this circuit, the input is resistive and reflected on the grids. The output is reflected at the cathode instead of at the plate. The load resistor for the tube is in
the cathode circuit. The tube has. slightly less than unity amplification factor when
used as shown. This circuit is generally employed to control the cathode level of
other stages. The input and output waveform is a step wave.
This Cathode Follower is controlled, at all times, by the level of the resistive
input. The cathode or output is said to follow the grid level. If the grid is
high the output is high and vice versa.
In the circuit of Figure 10, the IN52 germanium diode is used as a limiter. The output point cannot go below zero potential because of action of IN52. If the grid
is lowered below ground, the tube stops conducting and the cathode remains at ground.
When the grid is raised above ground, the tube conducts, IN52 stops
conducting, and the cathode follows the grid level •.
0-19
L..-f-l--4 3
A. CAGE WITH NO ASSOCIATED TUBE.
B. NUMBERED CONNECTIONS TO CAGE ONLY.
-375
A, 621 I TUBE IS USED.
B. NUMBERED CONNECTIONS TO CAGE ONLY.
PIN
4
A. DIODE TUBE IS USED.
B. NUMBERED CONNECTIONS TO CAGE ONLY.
A. THYRATRON TUBE IS USED,
B. NUMBERED CONNECTIONS TO CAGE ONLY:
C. SG IS THE SCREEN GRID.
(TiEPT.)
A. 6AU5 TUBE IS USED.
B. NO ASSOCIATED CAGE.
C. SG IS THE SCREEN GRID.
A. 5964 TUBE IS USED.
B. NUMBERED CONNECTIONS TO CAGE ONLY.
FIGURE ell
BLOCK SCHEMATIC
EXAMPLES
Standard Notations on Block Schematics
1.
A small (D) in upper left corner designates a Diode Tube is used.
20 A small (T) in upper left corner designates a Thyratron is used.
3. A small (N) in upper left corner designates no tube is used.
4.
All numbers on Block Schematics refer to cage pin connections •
5.
Tube pin numbers are not shown on Block Schematics.
.
6. A number in the RP, LP orK location generally indicates a cage
connection which also connects to the corresponding tube points.
7.
Lack of a number in any location indicates the connection to the tube
only.
8. If two leads connect to the same location, the numbered lead is the cage
pin connection and the unnumbered lead is the tube pin connection.
9. Any bias return to other than standard voltage is specified at the bias
position.
C-20
ELECTRONIC ACCUMULATOR
Plate1C
The purpose of an Accumulator is to add one digit to another or subtract one digit
from another. There are 22 such Accumulators in the Computer connected so as to
form a ring. In other words, Accumulator lA is connected to 2A, 2A to 3A, llA to
J.M--IlM to lAo This connection is neces~ary to handle the carry operation, 5 plus
7, and enable the Computer to shift the digits to different Accumulator positions.
The Accumulator does not use the 90 column code, instead a combination of~, 1, 2,
4, 6, and 8 is used. Each number is represented by a Trigger Circuit. A Trigger
conducting on the right side will represent a value but when the Trigger is conducting on the left side .it has no value. When the Accumulator has no value the
~ Trigger is right to so .indicate.
The same Accumulator Trigg~rs are used whether the';Computer adds or subtracts. The
add or subtract control within the Accumulator is the bias level of the Trigger
Amplifiers. Each Trigger has its associated Amplifdler, with its bias so controlled
that a Trigger pulsing the Amplifier will increase the value in Addition or decrease
the value in Subtraction. The Amplifier biases ha~e a high or -15 volt level when
effective and a low or -90 volt level when normal d:r ineffective.
The general operation of the Accumulator is to progress from Trigger to Amplifier to
Trigger. In Addition, when a Trigger is pulsed left, its signal is fed through an
Amplifier" add side, then to the next higher Trigger value to pull it right. In
Subtraction, when the Trigger is pulsed left,. its signal is fed through an Amplifier,
subtract side, then to the next lower Trigger value to pull it right.
There are two wys in which a counter of the Accumulator may add or subtract. A
negative pulse can be incoming on the Odd or Carry Line which denotes a value of one
for each pulse. The maximum pulses incoming on this line is limited to two during
one registration. The second method is by an incoming pulse on the Even Line which
denotes a value of two for each pulse. The maximum incoming pulses on this line are
limited to four during one registration.
The Accumulator has a value of zero when all Numerical Triggers are conducting left
and the ~ Trigger is conducting right. These Triggers are conditioned by a Zeroize
Pulse or Operation. In a Zeroize Operation either the right or left bias of the
Trigger is raised to approximately ground while the other bias is retained at -90
volts. This will cause the Trigger to conduct on one side or the other depending
upon which bias was raised. To Zeroize a Trigger on the left, the right bias of the
Trigger is ra,i,sed which results in raising the left grid so that the circuit conducts
on the left. When the bias is returned to normal the Trigger Circuit is retained in
this condition. To Zeroizea Trigger on the right, the left bias is raised which
results in raising the right grid so that the circuit conducts on the right. Plate
shows the Zeroize Line connected to the right bias of all Triggers except T,l) which has
its left bias connected. This means that all Triggers except ~ are Zeroized on the
l~.
'
Addition Operation
The right bias of the Amplifier stages will be raised to -15 volts by the operation
C-21
of the Sign Bias circuit, and the left bias will be retained at -90 volts. The Sign
Bias circuit controls all 22 Accumulators with respect to raising the Add or Subtract
Bias. This raised right bias will allow any positive pulse or step wave to pass through
the right side of the Amplifiers but the left side of the Amplifiers will reject any
and all pulses. The Accumulator has been Zeroized and a value of six is to be registered.
A six is composed of a pulse on the Odd Line, two pulses on the Even Line, and then another pulse on the Odd Line.
The first pulse is a negative pulse on the Odd Line which hits the ~Tl Trigger at
both the RC and LC points. This will trigger ~Tl to the right. The RP of ~Tl goes
low to the RC of Rl where it is rejected. The LP of ~Tl goes high to the LC of Rl
where it is rejected because of a low bias.
The second pulse is a negative pulse on the Even Line which hits the LC points of the
T~, T8, T6, T4 and T2 Triggers. A Trigger which is non-conducting on the left is the
only one which can be triggered. The ~ is triggered left by this negative pulse.
The RP of ~ goes high to the RC of R2 which releases a negative pulse at its RP
which, in turn, hitting the RP of T2, pulls T2 Trigger right. The high from the RP
of ~ to the LC of He is rejected because of a low bias. The negative step from the
RP of T2 to the RC of R4'is rejected.
The third pulse is another negative pulse on the Even Line which hits the LC points
of ~, T8, T6, T4, and T2. This time T2 Trigger is non-conducting on the left so the
Trigger is pulled left. The RP of T2 goes high to the RC of R4 which releases a negative pulse from its RP to the RP of T4, pulling T4 right. The negative step from the
RP of T4 to the RC of R6 is rejected as is the high from the RP of T2 to the LC of ~.
The final pulse is another negative pulse on the Odd Line. Trigger ~Tl was right when
this pulse occurs, so hitting ~Tl at the RC and LC points triggers ~Tl left. The LP of
~Tl goes low to the LC of Rl and is rejected. The RP of~Tl goes high to the RC of Rl
releasing a negative pulse at the RP of Rl. This negative pulse from the RP of Rl is
released on the Even Line and, as before, hits the LC of all Triggers. Trigger T4 is
on the right so the negative pulse to its LC point returns T4 left. The RP of T4 goes
high to the RC of R6 releasing a negative pulse from the RP of R6 to the RP of T6,
triggering T6 right. The high from the RP of T4 to the LC of R2 is rejected because of
low bias,
At the completion of the 4 pulses all Triggers are left except T6 which is right to
indicate a value of 6.
Subtraction Operation
The left bias of the Amplifiers will be raised to -15 volts and the right bias will
remain at -90 volts by the operation of the Sign Bias circuit. This raised left bias
will allow any positive pulse or step wave to pass through the left side of the Amplifier but the right side of the Amplifier will reject any and all pulses. The
Accumulator, for example, has a value of six, T6 right, and the Computer is going to
subtract 3. A 3 is composed of a pulse on the Even Line then a pulse on the Odd Line.
The first negative pulse is released on the Even Line to the LC point of ~, T2. T4, T6
and T8. The only Trigger non-conducting on the left is T6 so this negative pulse at
its LC point will pull T6 left. The RP of T6 goes high to the LC of R4 which releases
a negative pulse at the LP of R4 to the RP of T4, pulling T4 right. The high from the
C-22
RP of T6 to the RC of R8 is rejected because of a low bias.
The next and last pulse is a negative pulse on the Odd Line. This pulse is applied
to the RC and LC point of fjTl to pull it right. The RP of ,.elTl going low to the RC
of Rl is rejected. The LP of ,.elTl goes high to the LC of Rl releasing a negative
pulse from the LP of Rl onto the Even Line. This negative pulse on the Even Line
hits the 1C point of ~, T8, T6, T4 and T2. Trigger T4 is right so the negative
pulse at its 1C point will pull T4 left. The RP of T4 goes high to the 1C of R2
releasing a negative pulse from the LP of R2 to the RP of T2, pulling Trigger T2
right. The high from the RP of T4 to the RC of R6 is rejected because of a low bias.
The Computer has now subtracted a value of 3 from a value of 6.
Tr1gger T2 and Trigger ,elTl on the right for a total of 3.
The Accumulator has
Accumulator Over carry Operation
An over carry occurs when:
1.
Accumulator exceeds 9 in Addition.
2.
A number is subtracted from zero.
3. A number is subtracted from a smaller number.
An over carry in an Accumulator is present when the TC Trigger is right. This TC
Trigger is pu.lled r1ght when T8 returns left in Addition or T,.el returns left in
Subtraction. In either case the pulse from the plate of RC will kick Trigger TC
right. The Overcarry Condition 1s not corrected at the instant it occurs, but
rather, after all pu.lses required to register a number from zero to nine have been
generated.
The 1P of TC goes high to the RI of AC, DC Amplifier, causing its RP to go low to
the L1 of CB. The RP of CB goes high opening the right side of Gate CX to condition
for carries. All the AC stages, except III and 11M, have their right plates
connected to the 11 of CB so that the Computer cannot tell where the carry is needed.
As shawn on plate 3, the carries are released to all 22 TC triggers LC point.
Whichever TO Trigger or 'I'riggers are right will be returned left by the Carry Pulse
from the plate of CA. The return of the TC Trigger to the left will do two things:
1.
LP of TC returns low to the RI of AC to stop the call for
carries from that Accumulator.
2. liP of TC returns high to the LC of AC releasing a negative
pulse from the LP of AC which goes to the Odd and Carry
In~lt Line of the next higher order adjacent Accumulator,
1. to 2, 2 to 3, etc. This negative pulse on the Odd and
Carry Input Line will either add one or subtract one from
this Accumulator depending upon which Sign Bias is high
at the time.
C-23
ACCUMULATOR SHIFT OPERATION
Plate
2C
The purpose of the Accumulator Shift Operation is to shift a value from one Accumulator to another, shifting from lA toward lIM. Shifting is necessary to place
numbers in decimal alignment, place a digit in a specific Accumulator or shift a
number a predetermined number of Accumulator positions.
The Shi~t Pulses are originated in the Decimal Counter as shown on plate 4.
Each of the 22 Accumulator values shift simultaneously. Each of the 22 Accumulator
operations are identical in theory of operation.
Operation
Each numerical Trigger in an Accumulator controls an associated Shift Gate. Each
plate of the Trigger controls one side of a Double Gate Circuit. This means that
one side of the Double Gate Circuit is always open to accept and pass a Shift Pulse.
For example, assume that #1 Accumulator has a value of 4 when a shift occurs.
Trigger T4 is right and all other Triggers including TJ1 are left. The RP of T4
is low to the LI of S4 (Gate closed). The LP of T4 is high to the RI of S4 (Gate
opened). Wnen the Shift Pulse hits Gate S4 the RP of S4 releases a negative pulse
to the RP of T4 in #2 Accumulator, pulling T4 Trigger right. At the same time #1
Accumulator is shifting its value into #2 Accumulator~ #11 Accumulator is shifting
its value into ·#1 Accumulator, etc. in each of the 22 Accumulators. Trigger T2 in
#1 Accumulator is left so the LP of T2 is low to the RI of S2 (Gate closed) and the
RP of T2 is high to the LI of S2 (Gate open). The Shift Pulse to S2 releases a
negative pulse on the LP of S2 to the LP of T2 in #2 Accumulator. If Trigger T2 of
#2 Accumulator is left no change is noted but if T2 had been on the right T2 would
be brought back left.
The Trigger in #1 Accumulator controls a Gate in #2 Accumulator. The resistive
components of the Gate circuit are located in #1 Accumula.tor but the tube is in
Accumula.tor.
C-24
#2
CARRY INPUT GENERATOR
PLATE 3C
This oirouit is employed whenever an Aooumulator or Aocumulators exceeds its
oapacity. Whenever an Accumulator, by Addition or Subtraction, creates a call for
carry, this oircuit will create Carry Pulses to,enable the Accumulator to carry out
to the next adjacent higher order Accumulator. This circuit can be employed in any
prooess. Every time a cycle of RIG is required this circuit is checked automatically-to see if carries are required before the control circuits can continue. If
carries are required then the control circuits wait until all carries are satisfied.
An Acoumulator overcarry condition is not automatically corrected as soon as the
overcarryoccurs. -After a cycle of RIG is completed, as shown on plate 5, all
Accumulators are automatically checked for overcarries. One over carry may, upon
being satisfied, create an overcarry in the next Accumulator. If such is the case
the Carry Input Generator continues to run until all overc.arries are satisfied.
Operation
Assume that no Carry Triggers (TC) are right. At the same time that the RIG1 pulse
is released on the completion of a cycle of RIG:
Trigger R1 is returned left, causing its LP to go low which will
trigger the Flip-Flop CD to the right for a time delay of 50
microseconds. This. delay is necessary to allow the RIG1 pulse to
be regis tered in the Accumulators.
'
After 50 microseconds, CD returns left and its LP will release a
negative step wave to the LG point of the Negative Pulse Amplifier
CDA. The LP of CDA releases a positive pulse to the RCand LC points
of Gate CX which at this time is open on the left. The Gate CX
has its inputs controlled by the Schmitt Trigger GE. The input to
GE is controlled by the 22 TC Triggers of the Accumulators through
their respective AC stage.
NOTE:
Acoumulators 11A and ,11M do not have their AC stage connected
direotly to the LI of aB. The RP of AC of Aocumulator 11A
is oonn~oted to the LI of PS11 as shown on plate 20. The RP
of PS11 is conneoted to the LI of P11C. The LP of P11C is
oonnected to the LI of CE. The RP of AC of Accumulator 11M
is oonnected to the LI of C11M as shown on plate 20. The RP
of C11M is connected to the LI of CCM as shown on plate 41.
The LP of CCM is connected to the LI of CB.
The negative pulse released from the LP of CX is called the CX, or
Carries Satisfied, Pulse and indicates the completion of carries.
Assume that one or more of the Carry Triggers (TC) are right when the RIG1 Pulse
is released indicating oompletion of RIG:
Trigger R1 is returned left, causi~g its LP to go low which will
trigger the Flip-Flop CD to the right for a time delay of 50
C-25
microseconds. This delay is necessary to allow the RIG1
registered in the Accumulators.
pulse to be
After 50 microseconds, CD returns left, its LP releasing a negative step
wave to the LC point of CDA. The L? of CDA will release a positive pulse
to the RC and LC points of Gates CX. Since there is a call for carries, the
input to Schmitt Trigger CB is low. The LP of CB andL1 point of CX are
low. The RP of CB and the R1 of CX are high. The positive pulse from CDA
finds Gates CX open on the right, releasing a negative pulse from its RP.
The negative pulse from the RP of cx will pull Trigger cr to the right.
The RP of Trigger CT goes low to the L1 point of the DC Amplifier CMA.
Tne LP of CVlA will then go high to the L1 point of the Multi-Vibrator CM,
causing it to operate. The Multi-Vibrator CM, going right, sends its
LPhigh to the L1 point of DC Amplifier CA. The plates of CA will release
a negative step which is sent to the LC points of all 22 TO Triggers. Any
TC Triggers that are right will be returned left. The Multi-Vibrator then
returns left, causing its RP to go high and read the Gate CS. Gate CS is
controlled by the LP of Schmitt Trigger GB. Gate CS left input will remain
low until all carries are satisfied.
The Multi-Vibrator continues to send out Carry Pulses as long as a TO
Trigger is right. When the last TO Trigger returns left, Gate CS does
not open soon enough to stop the Multi-Vibrator C~ until one additiona.l
Carry Pulse has been released.
Multi-Vibrator CM returns left, causing its RP to go high to the LC
point of Gate CS. Gate CS, ha.ving a high input at this time, p'3.sse:3 the
positive pulse releasing a negative pulse at its LP. This negative pulse
hits Trigger CT and returns it left. The RP of CT goes high to:
The L1 point of the DC Amplifier CMA, causing its LP to go
low to the L1 point of eM and shut off the Multi-Vibrator CM.
The RC point of Positive Pulse Amplifier CMA resulting in a
negative pulse from its RP which is theCX Pulse indicating
all carries are satisfied.
Stages SCK, SCK'I, CS (right side) and CSK are used in the Test Counter open Hon.
0-26
DECIMAL REGISTRATION AND SHIFT OPERATION
Plate 4c
When the Decimal Locator is plugged, the Input Lines (True and Complement) have been
selected and their numerical value is determined with respect to the Calc. Decimal
Reference Point (6/5).
The Decimal System Code is shown in the following chart.
DECIMAL INPUT CODE
DECIMAL
POSITION
TRUE
TaC
I
2
4
8
I/O
2/1
X
3/2
4/3
5/4
X
6/5
X
7/6
8/7
9/8
X
10/9
X
16
2'
4'
X
X
X
10
I
8'
16'
TRUE
COMP.
X
16
6
X
15
7
X
X
X
X
X
X
X
14
8
X
X
X
13
9
X
X
X
X
12
10
X
X
X
X
II
II
X
X
X
X
10
12
X
X
X
9
13
X
X
X
8
14
X
X
X
7
15
6
16
X
II",
NOTE:-
COMPLEMENT
DECIMAL
REFERENCE
VALUES
X
X
X
X
USED FOR TRUE
X
a
COMPLEMENT
DECIMAL CODING
SYSTEM
The K. B. rises and the Input Lines (True and Complement) selected through the Decimal
Locator will raise the Input to the True and Complement Gates. To open the True or
Complement Gates, the following requirements must be met to pass a positive pulse:
A..
B.
High Input.
Low Cathode.
When registering a Decimal Complement, the DBC cathode line will be low.
registering a True Decimal, the DBT cathode line will be low.
When
Decimal Registration is called for when DE! Flip-Flop returns left, pulling DP1 right.
C-Z1
A cycle of Decimal Registration consists of 5 pulses generated by the following FlipFlops in the order listed: DP1, DP2, DP4,' DP8, DP16. '
The Decimal Counter is composed of five Triggers with a numerical value corresponding
to its stage name. Triggers DC2 and Dc8 each have a negative value. The value of
the Decimal Counter ~s obtained by adding or subtracting the value of the Triggers
conducting on the right.
Decimal Registration is completed when DP16 returns left.
An overcarry occurring during a Decimal Registration will be corrected at the
completion of the Decimal RIG. ,DP16 returning left sends its RP high to DIC which,
in turn, will return-Trigger DCC left, sending out the Correction Pulse.
The Decimal Counter is also employed in a Shift Operation. Shifting is required to
align one decimal position with another. The Decimal Registration prepares the
Decimal Counter as to the location 'of a specific decimal. A count of 22 in the
Decimal Counter indicates decimal alignment. Whenever the control circuit calls for
shifting for decimal alignment a Shift Operation will result, even though the
decimals may be already aligned. Shifting occurs from right to left.
Decimal Registration Operation
The Decimal Registration Circuit is used whenever a Decimal Registration is called for
regardless of whether it is,a True or Complement Registration. This circuit is
also used in conjunction with the Constant 17, which is empla,yed in the Multiplication and D:ivi,sion process. ,
The Decimal Registration circuit begins when Flip-Flop DEA is pulled right. FlipFlop DEA is a 150 us delay. The delay is necessary to allow the Keyboard Bias to
rise prior to the time the circuit'begins its operation. When DBA returns left, its
LP goes low to the RC point of Flip-Flop DP1, pulling.it right. The LP of DP1 will
go high to the LC and RC points of Gate DI1. After 25 us, DP1 returns left sending
its LP low to the LC point of the Negative Pulse Amplifier DA1-16. The LP of DA1-16
will release a positive pulse to the LC and RC points of DKG.
NOTE:Oti a Constant 17 Registration, Trigger DK will be right and its
LP will be high to the left side of Gate DKG. The positive pulse
from DA1-16 will then pass through the left side of DKG ,and pull
Flip-Flop DP16 to the right registering the 16 which thereby completes
'the registration of 17. .
. ..,
On a Decimal Registration (True or Complement), Trigger DK will be left; its RP will
go high to the right side of Gate DKG. The positive pulse from DA1-16 will now pass
through the right side of DKG and pULl Flip-Flop DP2 right. DP2 going right sends its
LPhigh to theRC poirtt of D2~T and the LC po:int of D2~C. After 25 us, DP2 returns
left, sending its LP low to the RC point of :Flip-Flop DP4. DP4 going right will send
its LP high to the LC point of D2~T and the RC of D2-4c.
After 25 us, DP4 returns left sending its LP low to the RC point of DPB and kick
DPd right. The LP of DP8 will go high to the RC Point of D8-16T and the tC point of
D6-16c.
After 25 us, DP8 returns left, sending its LP low to the RC point of Flip-Flop DP16.
DP16 going right will send its LP high to the LC point of D8-16T and RC point of
D;~-t6c.
c-28
When DP16 returns le~t, it indicates the completion o~ Decimal Registration, (True
or Complement) or Constant 17. The RP o~ DP16 will go high to the RC o~ the Positive
Pulse Ampli~ier DIC. The negative pulse ~rom the RP o~ DIC goes to the ~ollowing
places:
(a)
The RC point o~ Negative Pulse Ampli~ier DA1-16, which will indicate to
the control circuits completion o~ Decimal Registration.
(b)
The LC point o~ Trigger DCC, to check ~or overcarry. I~ an overcarry
is present, DCC right, this will return DCC le~t and initiate the
correction operation as described under "Decimal Counter Shi~t Operation".
Decimal Counter
Shi~t
Operation
Assume that the Decimal Counter has a count o~ 11 at the time a call ~or shi~ts begins.
A call ~or shi~ts ia caused b.Y either Trigger DRS or DAS going right. The LP o~ the
Trigger going right will raise the input to the Multi-Vibrator SM.
Because o~ a bac~eed fiom the M-V SM, when in operation, it has become necessary to
isolate the plates o~ the Shi~t Call Triggers. A call ~or shi~ts ~rom either Diode
SI1, SI2 or ENM1 will cause the cathodes o~ these diodes to go high. This raises the
le~ grid o~ stage SMC Cathode Follower.
The cathode of SMC is also raised and since
the right grid of SMC is fixed at ground (0) potential the RP of SMC stops conducting
and raises the input to the M-V SM, starting it in operation. When the cathodes of
the Diodes SI1, SI2 and :ENM1 are again lowered, the le~t grid of SMC also is lowered.
The cathode of SMC returning low allows the right side of the tube to conduct which
lowers the voltage on the RP and shuts off the M-V SM.
The Decimal Counter, with a count of 11, will have the following Triggers right.
DC1, DC2, Dc4, DeB and DC16.
The high input to the MUlti-Vibrator causes it to begin its operation. When itreturns le~, its RP will send a positive step to the LC point-of the Positive Pulse
Amplifier SMa. The negative pulse from the LP of SMG hits the Negative Pulse Amplifier
SMA at its RC point, resulting in a positive pulse fiom the RA point of SMA to the
LC point o~ Gates SG and DIC. .
NOTE:
The Gates SG and DIC ar& controlled b.Y the Overcarry Trigger
DCC. Trigger DCC is normally left except when the count of
22 is reached or exceeded in the Decimal Counter. With DCC
left at this time, its LP will be low to the LI point o~ Gate
DIC holding it closed. The RP of DCC will be high to the
LI point of Gate SG, conditioning it open.
Since Gate SG is open, the positive pulse fram SMA will pass throughSG resulting in
a negative pulse from its LP to the RC point of the Negative Pulse Amplifier SG.
The positive pulse from theRP o~SG is passed through the AC Cathode Follower SK1.
(There are 3 of these Cathode Followers --2 in parallel to insure a strong shi~
pulse) • This pulse is the Shift Pulse which goes to all 22 Accumulators. This will
: advance each digit one Accumulator position.
positive pulse from the cathode of SK1 also goes to the LC point of the Positive
Pulse Ampli~ier DB4, resulting in a negative pulse from its LP. This negative pulse
goes to the RC and LC points o~ Trigger DC1. Trigger DC1 will always be triggered
and in this case, it will be returned left. The RP of DC1 will go high to the LC
point of DB2, resulting in a negative pulse from the LP o~DB2. This negative pulse
will trigger DC2 and return it left. The LP o~ DC2, going low to the RC point of a
Th~
C-29
Positive Pulse Amplifier, is rejected. This leaves the following Triggers right:
Ddt, Dc8 and DC16 -- indicating a count of 12.
Shift Pulses will continue to be released by the shift Multi-Vibrator increasing
the DCR to a value of 21 with the following Triggers right: DC1, Ddt and DC16.
The next shift pulse into the Decimal Counter will trigger DCi left. The RP of
DC1 will go high to the LC point of DB2, resulting in a negative pulse from the LP •
of DB2 which triggers DC2 right. The LP of DC2 goes high to the RC point of DB4,
resulting in a negative pulse from the RP of DB4 which will trigger Ddt left. The
RP of DOt will go high to the LC point of DB8, resulting in a negative pulse from
its plate which will trigger De8 right.
The LP of Dc8 will go high to the RC point of DB16, resulting in a negative pulse
from its plate which will return DC16 left. The LP of DC16 will go low to the RC
point of Trigger DCC, pulling Trigger DCC to the right. 'ltrigger DCC going right
sends its RP low to the LC points of Triggers DRS and DAS, returning whichever Trigger that was right back to the left. This Trigger returning left will lower the input
to the Multi-Vibrator stopping its operation. No more Shift Pulses will be re1-eased
and the Counter is now in the Overcarry Condition with Triggers DC2 and Dc8 on the
right.
Correction Operation
Following a cycle of Decimal Registration, it is necessary to check whether or not
the Decimal Counter is in an Overcarry Position. Flip Flop DP16, returning left,
indicates the completion of a cycle of Decimal Registration. The RP of DP16 goes
high to the RC point of the Positive Pulse Amplifier DIC, resulting in a negative
pulse from its RP. This negative pulse from the RP of DIC goes to two places:
1.
'Ito the RC of DA1-16 to continue machine operation.
2.
To the LC point of Trigger DCC to check for an Overcarry Condition.
If DCC is on the right, there is an Overcarry Condition and the
negative pulse from DIC will return Trigger DCC left. Trigger DCC,
returning left, sends out the Correction Pulse as follows:
(a)
The RP of Trigger DCC goes high to the RC point of the
Positive Pulse Amplifier DB8, resulting in a negative
pulse fro.m its plate to trigger Dc8.
(b)
The RP of DCC will also go high to the Positive Pulse
Amplifier SMG, resulting in a negative pulse from its
RP which pulls the Flip-Flop DCCD right for 25 us.
This delay is necessary to allow the -8 Correction
Pulse to accomplish. its operation. Flip-Flop DCCD,
returning left, causes its RP to go high to the RC
point of the Positive Pulse Amplifier DB2, resulting
in a negative pulse from its RP which triggers DG2.
(c)
The Decimal Counter is now in a corrected condition with
the proper Triggers right.
Correction Operation When Decimal Counter Shifts Beyond a Count of :22
In Multiplication or Division it becomes necessary to cont.inue shift:i rlr:
beY0Ih1
t.he
count of 22. At the count of 22, Trigger DCC is pulled right. Trigger DCC being
right causes its RP to go low to the LI point of Gate SG, closing the Gate. The LP
of Trigger DCC will go high to the LI point of Gate DIC opening the Gate.
The n~xt potential Shift Pulse coming from the RA point of SMA will now be blocked
at Gate SG, preventing a shift of the digits in the Accumulators and also any increase
in the count in the Decimal Counter. Gate DIC will pass this positive pulse from
SMA, resulting in a negative pulse from the LPof DIC. This negative pulse from DIC
will trigger DCC back left. DCC returning left sends out the Correction Pulses in the
exact manner as described in the previous Correction Operation. At this time, when
the Correction Pulses are completed, all Triggers will be left, indicating a zero
value in the Decimal Counter. The next positive pulse from SMA will now pass through
Gate SG and shifting will continue in the normal way.
Decimal Input Lines Limiters
The purpose of the Limiter Circuit is to prevent the grid level of the True and
Complement Gates from being raised above -15 volts by the Input Lines coming from the
Decimal" Locator. The reason these Input Lines must be controlled is because the neons
in the line can cause too great a variance in the line level when fired.
The Limiter Circuit is composed of two decimal diodes connected in series. The plate
of Diode #1 is controlled by a Decimal Input Line. The cathode of Diode #1 is
returned through a Resistor ,to -60 Volts, but is also tied to the plate of Diode #2.
The cathode of Diode #2 is tied directly to -15 Volts. A rise in the input voltage
will raise the plate of Diode #1, which causes it to conduct, raising the voltage
on the cathode of #1 Diode through the Resistor. The plate of Diode #2 is raised,
but since the cathode of Diode #2 is tied to -15 Volts, the high limit of this
circuit is restricted to -15 Volts because of conduction of Diode #2.
Keyboard Bias Detector Circuit
The purpose of this circuit is to sense the presence of a Keyboard Bias and thereby
prevent a CX Pulse if no Keyboard Bias is present. The control for this circuit is
tied in with the Decimal Input Limiter Circuit. Whenever the Limiter Circuit cathode
line is raised to -15 volts, the tube DCCL will conduct, its plate voltage will then
lower the input to the Cathode Follower SCK, whose cathode will then hold the
cathode of Gate CX to low (zero potential).
When the Limiter cathode lines. are not raised but are approximately -45 Volts
because of no Keyboard Bias, tube DCCL will not conduct and, therefore, Gate CX will
end up with.a high cathode which will reject all positive pulses on its grid.
NOTE:
In the case of a non-0 CK in Multiplication or Division
it is necessary to add the additional 1 into 1A but no
Keyboard Bias is present. This is bypassed by raising the
Limiter cathode line from the LP of Trigger C9T.
C-31
RIDISTRATION INPUT GENERATOR (R.I.G.)
Plate 5C
The Generator (R~I.G.) isa composition of various stages, designed to generate a
predetermined amount of pulses at c~rtain intervals. These pulses are sent to the
Input & Output Chassis which will pass the required pulses necessary to register a
digit. In passing through the 10 chassis these pulses are inverted.
A eomplete set of pulses are generated in one cycle. Each cycle is generated within
a total time of 125 micro seconds. The sequence in which they are generated is
shown in Figure 12
QperatiQn
The Registration Input Generator is started by pulsing the RP of RD with a negative
pulse. The RP of RD will go low which holds the left grid low while the condenser is
charging. This conduction will exist for 100 micro seconds which allows Sign Bias
tL~e to rise.
When RD yent right its LP went high hitting the R.C. point of FlipFlop RS, which merely raised the left grid of this Flip-Flop higher allowing it to
remain in its stable state. After 100 micro seconds RD returns left and its LPgoes
low. This drop is reflected at the capacitive input to RS which will lower its left
grid allowing it to conduct on the right side for 25 micro seconds as determined by
the condenser. The RP of RS going low hits the left capacitive input of RI'8, a
Negative Pulse Amplifier, which will lower its grid momentarily. A positive pulse
is created on the LP. This plate is connected to the two grid inputs of Cathode
Follower RI'l' and will reflect a positive pulse off the cathode of Rl'l'. As
shown on the graph, the first pulse generated is the RIGI' Pulse. The positive
change on the LP of RS will be rejected at the capacitive input of Rl since it will
only" raise the left grid higher •
.After 25 micro seconds RS will return left and its LP will go loW'.
This change, being connected to the right capacitive input of Rl, will trigger Rl
right allowing its RP to go low. The low o~tput from the RP to the L1 point of the
DC Amplifier RIM, causes the LP of RIM to go high. Its LP is connected to the MultiVibrator R8 which will cause the Multi-Vibrator to oscillate. With a high input the
Multi-Vibrator will conduct on the right side lowering its RP. This drop is reflected at the RC of RI'8 as a negative pulse. A positive pulse results from its
RP through the Cathode Follower R8B. This is the first RIG 8 Pulse generated as
shown in Figure
After its designed.time interval Multi;..Vibrator R8 returns to conducting on the
left side resulting in its LP going low. This negative drop hits the double capacitive input of Trigger R4 reverting it to conducting on the right side. The RP of
R4 drops and is reflected as a negative pulse at R42, a Negative Pulse Amplifier.
A positive pulse from its LP hits the input points of Cathode Followers R44 and R66
resulting in both cathode points showing a positive pulse. At this time, as shown
on the graph, RIG4 and RIG6 Pulses are generated.
Multi-Vibrator R8 returns right since its input is still high causing its RP to
drop. This drop hits the Negative Pulse Amplifier Rlt8 resulting in a positive
C-32
pulse from its RP. This pulse through Cathode Follower R88 is the second RIG 8 Pulse
generated as shown on the graph.
RS now returns left again lowering its LP which results in a negative pulse at the
double capacitive input of R4, triggering it back left. The positive pulse from the
RP of RS is rejected by the Negative Pulse Amplifier Rl'8.
R4, now returning left, allows its LP to drop which will in turn trigger R2 right.
The RP of R2 going low to the Negative Pulse Amplifier R42 results in a positive pulse
from its RP. This positive pulse hits the input points of Cathode Followers R22 and
R66 which will in turn show a positive pulse at their cathodes. These two pulses are
the RIG 2 and RIG 6 Pulses as shown on the graph.
Since the Multi-Vibrator still has a high input it will now return to conducting on
its right side. Its RP going low, through Amplifier Rl'8 to the input point of
Cathode. Follower R8S results in the third RIG S Pulse as shown on the graph.
Upon the return of R8 left, its LP will drop, reflecting a negative pulse at capacitive
points of R4 triggering it right. The RP of R4 goes low to the Negative Pulse
Amplifier R42. The positive pulse from its LP hits.the Cathode Follower R44and R66
resulting in RIG 4 and RIG 6 Pulses as shown. on the O~
'2 \
:3
3
3.9
5
5,9
(IY, 2
4
5
6
7.
8
9
7
7,9
9
PULSES REQUIRED
ON ODD LINE
\Il.4
II
II
~
II
6
(1'\
6
8
(l),8
PULSES REQUIRED
ON EVEN LINE
RIG I
II
1/ II .-'
II
4
\
II
If
II
J
1/1'
I
1/11
,.,
1/'1'
, 'I i
'-"
0-34
RIG
II
II
II
II
II
II
2
2
4
4
6
6
8
INPUT CIRCUIT
Plate 6C
The INPUT 'DECODER is one-half of the Input-Output Chassis. There ar~ ten of these
chassis -- one for each of the lA to lOA Accumulators. The Input Lines to the
INPUT DECODER may come from anyone of three places:
1.
Card Field Input
2. Constants
3.
Storage
The level of the Input Lines is controlled by K.B.
low and become high from a signal from K.B.
The Input Lines are normally
, The Il, 13, 15 and 17 Input Lines all control the -60 cathode line; anyone of these
coming high will raise the -60 cathode line whose high voltage is limited to -15
Volts through the left side of IA9 conducting. The grid or left bias point of
stage I09 will then be at -15 Volts which will allow it to pass a positive pulse.
The grid or left bias point of stage IA9 will also be at -15 Volts, and since its
cathode is tied to -15 Volts, this tube will conduct. The LP of IA9 will drop its
voltage and, through a Voltage Divider, will pull the RG andRP of IA9to approximately -60 Volts. This point is tied to the LD point of stage 19, holding its
grid also at -60 Volts, preventing it from passing a positive pulse (RIGS). If the
19 Line is raised in conjunction with any other Input Line (~ven number), the only
additional change is that aate 179 is open on the right to pass the RIG1' Pulse.
In the event only the 19 Line is raised, the -60 cathode line will ~ be raised.
The LD of stage I09 will be returned to -60 Volts preventing the passage of a
positive pulse, RIG1. The LD of IA9 will also be returned to -60 and the tube will
not conduct. The LP of IA9 will be high and through a Voltage Divider and the
) limiter action of the right side of IA9, will hold the LD of 19 from rising above
-15 Volts. The Input Line I9 through the right side of diode C09, will hold the RD
of r09 from· rising above -15 Volts when the I9 Input Line is high. The RIGS Pulse
is now free to pass through the Decoder to be released on the Even Input Line.
In the event none of the Input Lines come high (zero), the circuit is similar to the
condition created when only the 19 Input Line is high with this exception -The right side of stage I09 will have a low grid,and, therefore reject
positive pulses (RIGS).
The only out-going lines in this circuit are the/Even Input, 'Which increased the
Accumulator value by 2 and the Carry and Odd Input Line which changes the Accumulator value by one. The Input Line indicates what value is going to register and
the RIGls when it will be registered.
NOTE:
RIGS ,can be blocked at 19 or I09.
Any number ~~'and,~ will raise the cathode line (-60 Volts).
Operation
Assume a figure is to be registered from a closed contact of the pin box.
C-35
Keyboard Bi.as, as determined by the plugboard will rise and sense any closed contacts
of the designated field. At this time assume that a contact is closed, designating
number 1 to be registered. The high potential raises the plate of the II neon
creating a voltage differential allowing it to fire. This will raise the plate
potential of diode C17. By raising the plate potential of C17 to a more positive
value than its cathode the tube will conduct. The plate current flow now-causes a
further drop across the 470K bias resistor raising the cathode line to a more positive value. This line cannot rise above a -15 yolts. If it does, Limiter IA9 will
conduct and maintain this line at -15 volts. This is due to the fact that if the
left grid of IA9 becomes more positive with respect to its cathode, current will··
flow and keep this line at its cathode potential. The cathode of 017 is connected
to 109 (left side) maintaining its grid level at a point just below cutoff.
At this time only the grid of the 109 tube was raised enough to allow an RIG Pulse
to affect its grid. The grid level of the other tubes are way belo1.-l cutoff and an
RIG Pulse is unable to raise their respective grids high enough to allow them to
conduct.
The RIG I Pulse hitting the left grid of 109- is sufficient to raise it high enough
for conduction to occur. The LP of 109 releases a negative pulse to its respective
Accumulator Odd Line.
The pulse on the Odd Line will trigger the ~Tl Trigger right
in the Accumulator, showing a one registered.
Reading a 1f3Vf selection will fire the 13 neon, which would raise the LP of C35. With
the plate more positive than its cathode, conduction occurs and the cathode line
would rise to a -15 volts as controlled by Limiter IA9.
Since the left input of Gate I35 is high, the RIG 2 Pulse will be able to raise the
grid momentarily to allow conduction to take place.
The LP of 135 releases a negative pulse which will be sent out on the Even Line to
register a two in the AcclTInulator.
The left grid of I09 is at -15 volts which allovJS the RIG I Pulse to raise the grid
high enough for conduction, resulting in a negative pulse on the Odd Line to register
a one. The RIG 1 Pulse is the last pulse generated and a three has been registered.
If a high input (Keyboard Bias) 1.-rere main-cained at lines I5 or 17 the S&"Ile condition
would occur as previously stated. The only exception would be that the Input Line
would condition either the right grid of 135 or the left grid of I79 which would
pass the RIG 4 Pulses or the RIG 6 Pulses on to the Even Line. The RIG 1 Pulse
would always pass with the selection of II, B, I5 or 17.
The registration of a nine is accomplished by passing four RIG 8 Pulses and also
the RIG 11 Pulse'T"C"~.---+--+--t---+--t-.,--+-_+__+_-+-+--t11...L~+ -+-+--_+__+_-+--+--+--+._+-l-,~noi-+'_ _-+-_--+--~
ST 0 R ~ l!i t-.-IDllt.llIIIIlLE:(-'~.LIL11M,...I.c::lI'
A ...
L"------+--t--_t_-t---I---I---I---I-___i--+----il-'-'-l ~--I--+_-+_+--t-_+_-+_-+-_+_-+---+---+--_+----1
1
CAL.P. ZEROIZE
.....D~_-_-,-+---+---_l___+_-__+_--+--+-_+__+_+-__t___i-I__t__+_+__t__t__t-_+_-_+__+
?
M' n nRC COMPT
PI\.C-R.
---lh--'
,_.+----+---1
3. MID JIDM------R""'EG-.,.<--_____r.9::-·+-:::-9-+-::-9--t-:;:9---r.::9--t-::9:-+-,~9+-=9:+-:9~9=+--::-9~9-r-:::8~4+-:9:_+-,-,9 9 9 9 9 9 -L9-+--.=16"'----+-_ _+--_---I
.~
SIR 1.1EG~
9 9 9 9 9 9
9 9 9 9 9 9 8 4 9 9 9 9 .9 9, 9'9
9
5. M' D SHIF~ED DCR AT ??
4 9 9 9 9 9
9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 8
22
CTll
~_ S'R DEC. COMPL.
4 9 9 9 9 9
9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 8 _7"-___t__--t-....".C:..a..T'....
I.I......-I
7 • S'R NOM. REG.
5
_a 7
C'T'11
R
STOR .. DECIMAl,
5
PA -L
S
1
CTll
1-~9--'R.....
:E.....
~S~S"""'lHI
....
:F.........
TED"-.........
DCR--.Aa.,lTI.--L.L??_--t-==S,,",+-,5,,-'_+--+--'.--_t_-f-_-+-_+-+,--+___i~I-_-I-_+-_+_-+--+--+--+.__ I-__+---I--2"'-'-'-2_+-_--i--l'CL.l.:''T'...&...11~
~ 10. TEST RIG
8 5
__ .__ - __t_I__+---I--+--+--i--+--+--t-_-t--t-_+___i_'f--I__+--2__
2-+ _ _-+-Cl:<.4~T....l~1
~ 11. ~,.><..Q-",S,""",,TO~B.Io.L'_______ 8 5
??
C'T'11
~ __ B-2 ZEROIZE
82
22
CTll
13. PR. MID DEC. COMPL. "_'_--I--=-8--+-=5-+--+--+_-+--+--+--1f--~+---I--+--+--+--+--+--+--I---+___i--lI-_~->o6!.---+-_ ___i--.:!.CTII
14. PRo M'D NUM. REG.
8 5
6
CTl1
15
PR • .s.:R DEC~~~L_ _ _ _ '__-I-;=-8-+-5-+--+---I--+_+_+--I~I__+--+--+--+-_t_-+-_+--+--+--+--+_+-=+- .....2==1,--+--_-+-=C=Tl=l~
16
PR ~1'D ~R AT??
5
8
22
CT11
tl.7. PRo SIR DEC._YOMPL.
5
i
PAt -R
R
7
CTl1
~_8. PR. SIR WJM. REG.
4 9 9 9 9 9
9 SJ 9 9 9 9 9 9 9 9 9 _99 9 _9 a
7
CTl1
19. M'D DECIMAL
4. 9 9 9 9 9
9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 8
13
CTll
9:--r+-~9'~~9~:9~:9~:."'-9,--f+---'.....::9:=9,-+_9",+-",,-9r-79~9-t-::8'-+-:4!-t-'9~9.::..;-.::..;9--,9"-t-9",-/-.:::..9~9+-,9-1-""""'"
~ • PR. RES. '-""S"""H-IF-T-E-D--DC-R-A-T-.::2;:2:_
22--1f--_-+--=-CT=I=1'--!
21. M' D N.:Ul:L.... REG.
+ 1 + 1 5
CT11
~)... MID NU.t-1. REG.
0 0 n 0 0 0
0 0 0 01 0 0 0 0 OU 0 1) 0 0 n ??
CT11
[)2_
~'RRO CH'RCK
pjC-I??
OT11
D3 SHIFT 10
1
10
CT10
~A • ZEROQ=HE=C=.K--------+-I---4---1-1--1--+-+-+-+--+--+--+-I--+---+---I--i1--+--I-+-+--I--=1:.::::,.0_t-_-t..;::C...::.:Tl=0=---t
hJ.....·
i
~"---------------"--------4---1--~-+-+-+-4-4-~-+"-+-+-4---1--i~~-~+-+-~1--r-r----~----4----~
§-.
- - , - - - - - - - - - r--"
--+-+-+--t--f----f----+-+--+--+---I--+---+--+-+-+-4J-I~+--+--+-----i----t-----
M-SECTION
PROCESS
CALC. DEC.
REF. POINT
II 10 9 8 7 6 5 4 3 2 I II
N IN II)I~ N )
A-SECTION
INPUT
10 9 8 7 a 5 4 3 2
1n
h
7
f)
J
h
h
COUNTER
I 0 EC M-D
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r: AT.r:
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M'D NUMREG.
6 6 6 6
L1
.C: I H nF.r.TMAT.
h
5.
M'D SHIFTED DCR AT 22
6 6 6 6
6.
SIR DEC. COMPL.
SIR NUM RFn
6
6
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4 5 1
S'T'OH
h
4
7
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9
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15
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4
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9.
PO.
Pl.
RES blHl'" 'JSU DCR AT ??
TEST RIG
RF.sITLT TO STOR
B-2 ZEROIZE
PRo M'D DEC. COMPL
PRo W D NUM. RID.
PRo SIR DECIMAL
PR. M'nSHIFTED DCR AT 22
PRe SIR DEC COMPL
PR. SIR HUM. RID.
MID DECIMAL
PR. RES. SHIFTED DCR AT 22
MID SUBTRACTION
0'1
SHIFT 10
10
eTla
?Ll
'7.F.HO r.HF.r:K
10
r:'Pln
& ttL
w
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1
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7.
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5
5
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1
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o
000
a a a a a
0
a
3
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3
22
£I
3
6
6
4
13
6 4 5 1
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6
15
15
4
5
1
6 6 6 6
666 6
6 6 6 6
a a a a
3
22
??
??
CALCULATOR ZEROIZE
Plate 11C
This circuit is employed at the beginning of a Program or Program Step. The circuit
controls the signal required to clear the Computer before beginning a new calculation. The ciTcuit also shows the origination of the signals required to
progress from. one Program Step to another.
Operation
This circuit starts its operation when Cam A in the Punch is closed and a card is
in the Sensing Section. Cam A closes at 334° and opens at 30°. The closing of
Cam A is called the Start Pulse and is applied to the RC or.R. EP is a 5MS delay
which is used to prevent contact bounce from creating more than one Start Pulse.
The LP of EP goes high to the RI of ESBl. The RP of ESBl goes low to the RC of ESD
pulling it right for a delay of 150 us,'and also to.the RC of ~3 pulling it right.
EP3 going right removes the cutoff ,lled
by the condition of Trigger PAC. The control of PAC is show on plate 20.
"",,,
If PAC is right then the left side of MCl is open for Camplementize. If PAC is
left, as this circuit assumes, then the right side of MCl is open. A negative
pulse from the RP of MCl triggers ER to the right. The RP of ER goes low to the
LC of EBS, (-) Branch Trigger. This is the only means by which EBS is Zeroized.
This method is necessary because use of the PTP prevents EBS being Zeroized by B2
or B5. The LP of ER goes high to the LI of ERA. The LP of ERA goes low to the LI
of ERK. The K-ERK goes low to all ERF stages and theERF stage with the high input
has its plate lowered to pull dow the R position on the Plugboard. R going low is
plugged to a Storage KB Call. This lowers the input to an FA stage as show on
plate 10.
The LD of ERA tapa off high to the LD of DRP. The LP of DRP goes high to the RI of
DMG, to open this Gate, and high to the RC of DPG1. The RP of DPGl releases a
negative pulse to the RP of DEA, kicking DE! right. DEA has a 150 us delay for KB
to rise and while DE! is right the Input Recovery Circuit functions as show on
pla te 1 3. After 150 us DE! returns left and the LP of DE! goes low to the RO of
DP1. This starts a cycle of Decimal Regist.ration as show on plate 4. This is
the Result Decimal because the Result or Storage KB is raised. The decimal value
will be the True value because the DBT cathode line is low as conditioned during the
ES operation.
.
C-6l
A negative pulse to the RC of DAl-16 from the RP of DIC signifies completion of a
Decimal Registration. The RP of DAl-16 sends a positive pulse to the RC of the open
Gate !MG. The RP of IMG releases a negative pulse to the. RP of DRS triggering DRS
right. The LP of DRS goes high to the RP of diode SI-2. The K-SI2 goes high to the
LD of SMC to start the Shift Operation for decimal alignment as shown on plate 4.
Decimal alignment is achieved when the Decimal Counter reaches 22 and DCC goes right.
The RP of DCC goes low to the LC of DRS re"turning DRS left. The LP of DRS going low
stops the Shift Operation. The LP of DRS also goes low to the RC of MST, triggering
MST right. The RP of MST goes low to the L1 of MSI. The plates of MSI are tied
together so both inputs pf MSI must be low in order for the plates of MS1 to go high.
The RI of MSI is controlled by the LP of EM~. ~ is a Flip Flop of 5M3 delay which
was kicked by the return of EZB5, plate 11. The purpose of ~ delay is to delay
the Test RIG Operation until the Storage Clear Operation is completed. When EMZ returns
left the LP of EM~ goes low to the RI of MSI so now both sides of MSI are cutoff. The
plates of MSI are free to go high. The high from MSI raises the LI of MSA. The LP
of MSA goes low to the RC of M~T, triggering GT right. The LP of M~T goes high to
the L1 of M6R. The LP of M~R goes low to the L1 of PABA to raise the Add Bias and
call for the Test RIG as shown on plate 43.
The completion of a Numerical Registration is signified by a CX Pulse.
to the LC of MZT returns M~T left. The LP of ~T going low lowers SB.
The LP of MZT goes low to the RC of MS, kicking MS right. MS is
Flop which originates the Storage Set Signal. The RP of MS goes
Xhe K-l-tSK goes low to the LC of MSKA as shown on plate 10. The
lA-lOA, is now placed in Storage. The LP of MS goes high to the
for (-) Branching as shown on plate 38.
The CX Pulse
a 150 us delay Flip
low to the L1 of MSK.
result, in Accumulators
LC of EBG to check
After 150 us, MS returns left to complete the Storage Set Pulse. The RP of MS returns
high to the RC of DPG2. The RP of DPG2 releases a negative pulse onto the Control
Ring and ER is returned left. This is a Control Ring Pulse so the KB Recovery Circuit
again functions as shown on plate 37.
The LP of ER returns low. to the ltC of
Storage Set Lines time to recover.
EDP~.
EDpg is a 14 us delay to allow the
After 14 us, EDPZ returns left. The 1P of EDPZ returns low to the RC of EPZ, kicking
EPZ right. EPZ is a 450 us delay to allow sufficient time for the B2 Zeroize. The
LP of EPZ goes high to the RC of EZG. The RP of EZG releases a negative pulse to
trigger EZB2 right. The RP of EZB2 goes low to initiate the B2 Zeroize as shown on
plate 36. EZB2has a 300 us delay_
After 450 us, EPg returns left. The LP of EPg returns low to the RC of EPM, triggering
EPM right. The Computer now proceeds into the Proor Mlnidend Control Circuit Operation.
C-62
PROOF MINIDEND - STORAGE REGISTRATION
Plate 16C
This plate illustrates the controls required to perform the Proof Minidend functions
which are:
1.
Proof Minidend (Storage) Decimal Complement Registration.
2.
Proof Minidend (Storage) Numerical Registration.
This circuit is employed in every Process. The control circuits from this circuit
through and including Zero Check are employed for proof purposes only. The answer
for the step has been calculated and placed in Storage~ The following sequence of
control circm,ts are an automatic check on the calculation.
Operation
Flip Flop EPg returning left goes low to the RC of EPM, triggering EFM right. The
RP of EPM goes low to the diode ENMl to check for Minus Factor as shown on plate 20.
The LP of EPM goes bigh to the RI of ERA. The RP of ERA goes low to the LI of ERK.
The K~ERK goes low to all ERF stages and the ERF stage with the high input has its
plate lowered to pull doW;n the R position on the Plugboard. R going low is plugged
to a Storage KB Call. This lowers the input to a FA stage as shown on plate 10.
The LP of EPM goes high to the LI of EPMA..
The LP of IMP goes high to the following:
The LP of EPMA goes low to the RP of
I:HP.
1. LP of diode EIA3 raising its left cathode to prepare SB.
am
2.
L1 of Gate
to condition this Gate open for future use.
3.
L1 of DMD lowering the LP of !lID.
The LP of llID goes low to the RP of D]M, pulling DI!M right. The RP of Dl!M goes low
to the LI of DBC conditioning the Decimal Complement Gates in the Decimal Counter.
as shown on plate 4. The LP of DEM goes high to the RC of DEAL The RP of DEAl
releases a negative pulse to the RP of DEA, kicking DE! right. DE! has a 150 us
delay for KB to rise and while DE! is right the Input Recovery Circuit functions as
shown on plate 13 • After 150 us DEAreturns left and the LP of DEA goes low to the
RC of DPI. This starts a cycle of Decimal Registration as shown on plate 4. This
is the Storage Decimal because' the Storage KB is raised at this time. The decimal
value will 'be the Complement as explained above.
A negative pulse to the He of DAl-16 from the RP of DIC signifies completion of
Decimal Registration. The RP of DAl-16 sends a positive pulse to the LC of the
open Gate DMG. The LP of DMG releases a negative pulse to the RP of DRB, triggering
DRB right.
The RP of DRB goes low to the RI of PSAC to unc18Jllp SB and start a cycle of RIG as
shown on plates 43 and 5. The Add Bias will always be raised at this time. , The
C-63
completion of a Numerical Registration is signified by a ex Pulse. The ct Pulse to
the LC of DRB returns DRB to the left. The RP of DRB returns high to lowerSB and
also high to the LC of EPG. The LP of EPG releases a negative pulse to the Control
Ring. This Control Ring Pulse returns EPM left. This Control Ring Pulse also causes
the KB Recovery Circuit to function by kicking ~FDI as shown on plate 37 • The
Computer now proceeds into the Proof Subvisor Control Circuit Operation.
PROOF BUBVISOR - SUBVISOR RmISTRATION
Plate 17C
This plate illustrates the controls required to perform the Proof Subvisor (Subvisor)
functions in Addition or Subtraction. These functions are:
1.
Proof Subvisor (Subvisor) True Decimal Registration.
2.
Shift Operation to align the Proof H'd Dec1mal with the
Proof Sir Decimal.
3.
Proof Subvisor (Subvisor) Decimal Complement Registration.
4.
Depending upon the Process the Proof Sir is either added
or subtracted.
Operation
Trigger EPM is returned left by a Control Ring Pulse and the LP of EPM going low to the
RC of EPS triggers EPS right.
The circuit operation is identical to the Subvisor Registration on plate 14.
are only two exceptions which are:
1.
The right side of ESA is used.
2.
The Check Counter is not opened to shifts because the right
side of ESA is used.
There
The Control Ring Pulse from the LP of EPG returns EPS left. This Control Ring Pulse
also causes the 103 Recovery Circuit to function by' kicking ~FDI as shown on plate 37.
The Computer now proceeds into the Minidend Subtraction Control Circuit Operation.
C-64
MINIDEND SUBTRACTION
Plate 18C
This plate illustrates the controls required to perform Minidend Subtraction
functions in the various Processes. The functions are as follows:
1. Minidend True Decimal Registration.
2.
Shift Operation to align the Proof SIr Decimal with
the Mid Decimal.
NOTE:
In x or + Process the Shift Pulses are also
counted in the Check Counter.
3. The Minidend Numerical Registration is made,
generally subtraction.
NOTE:
In x or + Process a Carry Block is
established between Accumulators ]K and 2M.
In + or - process if Trigger PAC is right
a one is added in Accumulator ]K.
Operation
Trigger EPS is returned left by a Control Ring Pulse and the LP of EPS going low
to the RC of EPP triggers EPP right. The LP of EPP goes high to the LI of ECB1.
The LD of ECBl taps off high to the RD of 1lMA. The RP of :EMA goes low to tl1e LI
of EM[{. The K-EMK goes low to all EMF stages, as shown on plate 38, and lowers
the Vl position on the Plugboard. Vl being lowered raises KB for the M'd. K:a
conditions Input Decoder Gates, Decimal Gates and checks for Minus Indication.
The RPof EPP. goes low to the .R! of ECB1.
following:
~
TheRP of ECBl goes lligh to the
1. LI of Gate DG to open this Gate for future use.
2.
Plates of diode EPPM to raise its cathodes to prepare
SB and open Gate DPG2 for future use.
3.
The RC of MBA.
The RP of MBA releases a negative pulse to the RP of DEA, kicking DEA 'right. DEA
has .a 150 us delay for KB to rise and while DEA is right the Input Reoovery Cirouit
functions as shown on plate 13. After 150 usDEA returns left and the LP of DEA
goes low to the RC of DPI. This starts a C7cle of Decimal Registration as shown on
plate 4. This is the Mfd Decimal because the M'd KB is raised. The decimal
Value will be the True value because the DBT oathode will be low as conditioned
during'the EPS operation.
A negative pulse to the RC of DAI-16 from the RP of DIC signifies completion of a
Decimal Registration. The RP of DAl-16 sends a positive pulse ~o the LO of the open
C-65
Gate DPG2. The LP of DPG2 releases a negative pulse to the RC and LC points of
Trigger DAX to kick DAI right. The RP of DAX goes low to the RC of DAS pulling DAS
right. The LP of DAS goes high to the LP of diode SI-2. The K-SI-2 goes high to the
LDof SMC to start the Shift Operation for decimal alignment as shown on plate 4.
NOTE:
In X or + Process only, the Check Counter is opened to count
shifts as shown on plate 41. The I or + Process from the LD
of FPI goes low to the RD of CPMD. This cuts off the RP of
CPMD. The RP of EPP is low to the RI of ECBl. The LD of
ECBl taps off low to the LD of
The LP of DfZ' is cut
'Off. The LP of EMZ' and RP of: CPMD are free to go high to
the LI of CPMD. The LP of CPMD goes low to the LI of CGA.
The LP of CGAis cut off. CTlO and OTll are both always
left at this time. The RP of CTII is high to the RD of ·DCK2. The
RP of DCK2 is low to the RI of COM. The RP of CCM is cut off.
The LP of CGA and RP of· COM are free to go high to the LI of CTSG,
opening this Gate. The Shift Pulses occurring during EPP in X or
+ Process will pass through the open CTSG Gate and accumulate in
the CCT.
l!XZ'.
Decimal alignment is achieved when the Decimal Counter reaches 22 and DCC goes right.
The RP of DCC goes low to the LO of DAS returning DAS left. The LP of DAS going low
stops the Shift Operation. The RP of DAS going high pulses the RC and LC of Gate DG.
The LI of DG is high since EPP is right. The LP of DG releases a negative pulse to
the RP of DRB, pulling DRB right.
TheRP of DRB goes low to theRI ofPSAO to raise SB and call for a cycle of RIG as
shown on plates 43 and 5.
NOTE:
In + or - Process PAC may be right. PAC would go right if an
overcarry at l1A or lIM occurs during EPS Control Circuit time.
Whenever this over carry occurs, legitimately, the Add Bias will
be raised during EPP Numerical Registration. The RP of PAC
being low cuts off the left side of OI5DE. The right side of cllDE
is cutoff from the low level off the RD of ECBl. The plates of
CI5DE are free to go high to the RP of diode C9R. This raises the
right cathode of diode C9R and raises the LI of Gate 11-11. The
RIG1' Pulse occurring during the EPP Numerical Registration passes
through this open 11-11 Gate to put a negative pulse on the 1M
Odd Line. The M Section would be all nines so a series of overcarries
would result leaving the A Section zero and a 1 in the Accumulatqr
1M when all carries are satisfied.
.
In X or + Process the LP of EMZ and RP of CPMD are free to go
high as previously shown. The LI of CPMD goes high and the LD
of CPMD taps off high to the LD of ECB2. The LP tap point, pin 8,
goes low to the left bias of Accumulator 1M AC stage. This blocks
carries from Accumulator 1M to 2M •.
The completion of a Numerical Registration
to the LC of DRB returns DRB to the left.
also high to theLO of EPG. The LP of EPa
Ring. This Control Ring Pulse returns EPP
is signified by a OX Pulse. The CX Pulse
The RP of DRB returns high to lower SB and
releases a negative pulse to the Control
to the left. At this time the AcCUIlIlllators
0-66
1A to lOA must be zero in + or - and may be zero or all nines in x or + in orde~
to be able to prove a good calculation. This check is indicated in the Zero Check.
Zero Check is the next control circuit operation.
C-67
ZERO CHIDK
Plate 19C
This plate illustrates the controls required, in all processes, to determine if a
calculation has been successfully performed. Addition and Subtraction controls
vary, somewhat, from the Multiplication and Division controls.
I
Addition and Subtraction
A.
Zero Check (lA-lOA)
B.
10 Shifts
C• Zero Check (lA-lOA)
D.
EGD (Step Advance and Step Zeroize)
NOTE:
If either Zero Check is unsuccessful the
Computer does not continue until that step
has been repeated and successful Zero Checks
made.
II Multiplication and Division
A.
Shift' to bring CCT to count of 10 (if necessary)
B.
Zero Check
1. Successful
a.
EGD .
2. Unsuccessful
a.
Adds a one to Accumulator lA.
b.
Zero Check
(1)
Successful
(a)
(2)
EGD
Unsuccessful
(b)
Computer cannot continue.
Step repeat.
Zero Check Control Operation
Each 10 Chassis has an Output Decoder Section.and it is from this section that the
Zero or non-zero indication is derived. Each Aecumulator, lA through lOA, has its
T¢ and Tl Trigger indication fed to the Output Decoder. When Tl is left and T¢ right
the Accumulator is at zero.
C-68
Trigger Tl being left is low to MO and the K-MO is low to the K-MA9. Trigger!¢ being
right is high to MA9. MA9 now has a high grid and low cathode so the LP of MA9 is
free to conduct and lower the right grid of ~CC. The above control is present in
each 10 Chassis. The right cathodes of the ~CC stage of each 10 Chassis are tied
together. When all 10 10 Chassis are zero this cathode line is low but anyone 10
Chassis decoding a value will raise this cathode line.
The ri~ht cathodes O.f all ~CC stages, Zero Check (lA-lOA), are fed low to the LI.Of
¢9C. ~9a and ¢9Cl are in parallel so both stages are cutoff. The plates of ¢9C and
¢9Cl go high to the L1 of .t59M The LP of .o9M is low to the LI of ¢9SM and ¢9SMI.
The left sides of ~9SM and ¢9SMI are cutoff. The right sides of .o9SM and ¢9SMI are
also cutoff by the low level from the LP of PAT. (PAT is the Sign Check Trigger used
in x or +. See plate 20). The plates of ¢9SM and ¢9SMI are free to go high. This
is always the case when a true Zero Check occurs. Whenever a Zero Check occurs the
high level from the plates of ¢9SM and ¢9SMI will open the following Gates:
0
1.
C¢PG - left side
2. C9G - left side
3.
c¢G -
right side
Regardless of the process the preceding controls and operations are the same.
Addition and Subtraction
Zero Check Operation
This explanation is given with the assumption a Zero Check occurs.
Trigger EPP is returned left by a Control Ring Pulse. The LP of EPP returns low to
the RC of c¢D. c¢D goes right for 100 us. The purpose of this 100 us delay is to
allow time for the Zero Check lines to stabilize. After 100 us GOD returns left.
The RP of C¢D goes high to the RC and LC of Gate C¢PG. The right side of c¢FG is
closed by x and + Process. The left side of C¢PG is opened by Zero Check. The LP of
C0PG releases a negative pulse to the RC and LC of the Diode Gate C¢DG. Gate C¢DG is
controlled by the condition of CTIO iri the Check Counter.
NOTE:
The count in the Check Counter at this time is always zero
in a + or - Process. CTIO is left so the LP of CTIO is
low to RI of CGA.. The RP of CGA is high to the L1 of c¢DD
and RI of C¢DG. The LP of GODD is low to the LI of GODG.
The left side of ~DG is open and the right side closed.
The LP of ~DG releases a negative pulse to the RD of Qdcs, triggering Qdcs right.
The LP of ~C5 goes high to the LP of diode ElMl. The left cathode of ENMI raises
the LD of SMC to st&rt a Shift Op~ration.
NOTE:
The purpose of this Shift Operation is to shift exactly' 10
times. These 10 shifts bring the values of Accumulators
2M to 1lM into Accumulators lA to lOA. The values are zero
when the step is correct. The Decimal Counter is of no
value to .indicate a total of 10 so the CheCk Counter and
Trigger CTIO is employed.
C-69
The RP of Ct)CS goes low to the RI of Ct)DD. The RP of C,0DD goes high to the RI of
CTSG to open the Gate. Th~s Gate is pulsed by Shift Pulses and the output of the
Gate goes to CTI which is part of the Check Counter. The Check Counter counts
each Shift Pulse. At the lath Shift Pulse CT10 is pulled right. The LP of CT10
goes high to the RI of CGA. The RP of CGA goes low to the LC of cms, triggering
cms left. Ct)CS returning left stops the Shift Operation and closes Gate CTSG.
Exactly 10 shifts have occurred.
The LP of cms returns low to the RC of C,0DA, kicking C,0DA right. Ct)DA has a 100
'lis delay to allow the Zero Check lines to stabilize. After 100 us C,0DA returns
left. The LP of Ct)DA goes low to the RC of C9G. The RP of C9G releases a positive
pulse to the RC and LC of Ct)G. The left side of C,0G is closed by x and + Process.
The right side of C,0G is opened by Zero Check. The RP of C,0G releases a negative
; :pulse to the RP of EGD. EGD being pulsed advances the Computer into the next
Program Step (as shown on plate 11 .)
In Addition or Subtraction both Zero Checks must be present in order for the circuits
to continue fUnctioning. Lack of either Zero Check,will cease circuit operation
until a repeat signal is given from the Timer Circuit.
Multiplication and Division
Zero Check Operation
Trigger EPP is returned left by a Control Ring Pulse. The LP of EPP returns low to
the RC of Ct)D. Ct)D goes right for 100 us. The purpose of this 100 us delay is to
allow time for the Zero Check lines to stabilize. After 100 us C,0D returns left.
The RP of C.oD goes high to the' RC and LC of Gate C.oDG.
NOTE:
Both sides of C,0PG are open. The left side is opened by
Zero Check. The right side is Qpened by x or + Process.
The x or + Process Line is low to the RD of ERA.i. The
RP of ERA.i is high to the RI of Ct)PG opening the Gate. In this particular example both sides are open but only the right side is
always open in x or + Process.
The plates of Ct)PG release a negative pulse to the RC and LC of the Diode Gate C,0DG.
NOTE:
The Diode Gate C,0DG is conditioned on both sides by the
Check Counter Trigger CT10. If CTIO is left the left side
of Ct)DG is open and if CT10 is right the right side of C,0DG
is open as shown on plate 19. The CCT is opened to count
shifts during EPP in x or + only. As shown on the problem
sheet, the Proof Result always ~s its first digit in 11,M when
shifting starts during EPP. The number of shifts required during
EPP can vary from zero (22) up to a total of 10. The object of
this proof system is to have the Proof Result shifted a total of
10 times before a Zero Check is attempted. This total of 10 is
indicated when CTIO goes right. If CTIO is right, the total of
10 shifts has occurred so the right side of C,0DG being open
pulses C,0DA directly. The following is an explanation assuming
CTIO iastill to be left.
The left side of the Diode Gate Ct)DG is open so the LP of C,0DG releases a negative
pulse to the RD of C,0CS, triggering CmSright. TheLP of,C,0CS goes high to the
LP of diode ENMI. The left cathode of ENMl raises the LD of SMC to start a Shift
C-70
Operation.
NOTE:
This time the CCT may have some count already present so the
number of shifts required will vary depending upon the MId value
and MId decimal position.
The RP of C~CS goes low to the RI of C~DD. The RP of C~DD goes high to the RI of
the Gate CTSG. This open Gate, CTSG, passes the Shlft Pulses into the CCT. A
count of 10 in the CCT is indicated by CTIO going right. The LP of CTlO goes high
to the RI of CGA. The RP of CGA goes low to the LC of c..elcs, triggering C~CS left.
C~CS returning left stops the Shift Operation and closes Gate CTSG.
The LP of C~CS returns low to the RC of C~DA, kicking C~DA right. C~DA has a 100
us delay to allow the Zero Check lines to stabilize. After 100 us, C~CS returns
left. The LP of C~DA goes low to the RC of C9G. The RP of C9G releases a positive
pulse to the RC and LC of Gate C~G.
Up to this point the circuitry has made no deflnite attempt to differentiate because of lack of a Zero Check. At Gate c..elG this attempt is made.
First, assume the lA-lOA Accumulators are zero and the right side of C~G is open.
The left side of c..elG is also opened by the X or + Process. The negative pulse released from the RP of C~G kicks EnD to bring about Step Advance and Step Zeroize.
The EGD operation will nullify any operations begun by a pulse from the LP of C~G.
Secondly, assume the A Section does not indicate all zeros. The right side of C~G
is closed so EGD cannot be yulsed. The negative pulse released from the LP of C~G
is effective and kicks C9T right. The LP of C9T goes high and the following results
occur:
1.
A neon in SK2 is fired to raise the RD of DCCL and lower the cathode
of CX as shown on plate 48. This will nullify the KB Detector Circuit.
C9T does not raise a KB so a falseKB, v~a SK2 is required to open cx.
2.
The grids of F;1CB are raised so both plates of E;elCB conduct. The LP
of ~CB lowers the left bias of Accumulator 1M AC stage to prevent
Carry Out to Accumulator 2M. The RP of Ee\CB lowers the LI of PABA
to raise Add Bias and call for a cycle of RIG.
3.
The left bias of E;elCB taps off high to the LD of Ee\CA to open the
Gate. The RIGl' Pulse from the cycle of RIG goes through this open
Gate to put a negative pulse on the lA Odd Line.
Assuming the A Section to be all nines the negative pulse to Accumulator lA will
bring these nines to zero. The completion of a Numerical Registration is signified
by a CX Pulse. The ex Pulse to the RC of C9D pulls C9D right. C9D has a 100 us
delay to allow the Zero Check lines to stabilize.
After 100 us C9D returns left, the LP of C9D goes low to the La of C9T, triggering
C9T left. The RP of C9T returns high to the LC of Gate C9G. The LI of C9G is
controlled by the Zero Check Line. Assuming Accumulators lA-lOA to be zero this
Gate is open. The LP of C9G releases a negative pulse to the RP of EGD. EGD being
pulsed advances the Computer into the next Program Step as shown on plate 11.
In the event Gate C9G has been closed because of a Non-Zero Check the circuit
operation would cease until a repeat signal occurs from the Timer Circuit.
C-71
COMPLEMENTIZE
Plate 20C
Complementize is the term employed, in an Addition or Subtraction Process, when the
numerical result is negative. The actual value, not the complement, must be placed
in Storage. Whenever the answer is negative, because of a subtraction, the normal
Computer operation gives a complement answer. A subtraction is the difference
between two numbers. For example: 8-5
3 or 5-8 -3. The difference between
the two subtractions is the sign of the answer. In Complementize this fact is used
so that when an answer is negative the signs of the two numbers are reversed giving
a true value instead of a complement value. The negative sign of the answer is retained to go with the true value.
=
=
Operation
The operation of this circuit covers the entire control circuit time from EM to
EPP. To assist in tracing this circuit the Work Sheet problem will be used as a
typical example of the circuit operation.
Line I
Calculator Zeroize - All Triggers on this circuit are Zeroized left.
Line 2
Minidend Decimal Complement - At this time EM is right so the LP-EM is high
to theLI-EMA. The LP-EMA goes low through the diode ENM to pull PAMD
right. PAMD is a 250 us delay for KB to rise.
conditions the Minus Neon Common Line low (no negative value). MC4 is
cut off because of this low line. The LP..,MC4 is high to LI-MC5 so the
plates of MC5 are low to the RP-MCX. The RP-MC4 is tied to the LP-MC6.
MC6 has a low plate since the RP ofMC2 is high to the LI of MC6. This
holds the LP-MCI low. Both plates of diode MCX are low so the cathodes
of MOX are low to Gate PSIG, holding this Gate closed. After 250 us
PAMD returns left sending its RP high to the LC of the closed Gate PSIG.
PSIG being closed stops the circuit operation at this point.
KB
Line 3
Minidend Numeric Registration - This registration has no function in
this circuit at this time.
Line 4
Subvisor Decimal - This operation is the same as line 2 except ES and ESA
are used instead of EM and EMA. The subvisor is a positive number even
though it is to be subtracted (Subtract Process).
Line 5
Minidend Shifted until the Decimal Counter reaches 22 - This Shift
C-72
Operation requires 21 shifts, according to the work sheet. The first 16 of
these shifts are counted in the Check Counter (see plate 41). These shifts
will cause CTII to go right. CTII controls the conditioning of Gate PSOC.
CTII will be right, and will open the left side of PSOC and close the right
side of PSOC.
Line 6
Subvisor Decimal Complement - This operation has no function in this circuit.
Line 1
Subvisor Numeric Registration - The Subvisor value is larger than the
Minidend Value so when the subtraction t.akes place a series of overcarr·ies
will occur. Accumulator l1A goes into over carry and when the TC Trigger in
llA is returnQd left the RP-AC returns high to the LI of PSII. The RP-PSll
returns low to the RC and RI points of PllC. The RP of PllC releases a
positive pulse to pin 6 and out pin 5 to theLC of PSOC. This Gate was
previously conditioned open. The LP-PSOC releases a negative pulse to the
RC and LC of PAC, triggering PAC right. PAC going right closes the ~ight
side of MCI and opens the left side of MCI.
The overcarries continue around to Accumulator lIM. The TC Trigger in lIM
goes right and the RP-AC goes low to the LI of ClIM. The RP-ClIM goes high
to the RC of PSOC. The right side of PSOC was previously conditioned closed
(CTII is right).
The SIr Numerical Registration is completed (CX Pulse) and a Control Ring
Pulse is released. The Control Ring Pulse returns ES left. The. RP-ES
returns high to the RC and LC of Gate MCI. As previously stated, the left
side of MCl is open (PAC right). The LP~l releases a negative pulse to
the RP of MC2, triggering MC2 right.
Line· 8
CalculatorZeroize -MC2 goes right and the LP~C2 goes bighto the RC of
MC6. The RP~C6 releases a negative pulse to the RP of Fi. When Fi is
pulsed the step is started over and all Triggers, except MC2, in this
circuit are Zeroized left.
Line 9
Minidend Deoimal Complement - As stated under line 2 PAMD is pulsed right
for 250 us. The Minus Neon Common Line is still low which holds the RP of
MC4 cutoff. MC2 being on the right holds the LP of MC6 cutoff. The high
from the .RP-MC4. and LP-MC6 raises the LP of diode MCX. The cathOdes of .
MOl go high to theLI of PSIG and open this Gate.
After 250 usPAND returns left and the RP-PAND goes high to theLC of the open
Gate PSIG. The LP-PSIG releases a negative pulse to the IC-PSIG. The
RP-PSIG releases a positive pulse to the RC and LC of Gate PS.
NOTE: The Process is Subtraction so the HI-PIAS is low. The
lIP-PIAS i8 low to the RI-FPI. The RP-FPI is high to
the LI-PS opening this side of the Gate. The right side
of PS is closed because of no x or + Process
C-13
The LP-PS releases a negative pulse to the RC of PAM, triggering PMf
right. PAM being on the right will reverse the normal SB procedure
as shown on plate 44.
Line 10
Minidend Numeric Registration - The MId is normally added but because
PAM is right, as explained under line 9, the Subtract Bias 'will be
raised. The Accumulators were zero so when the MId was subtracted a
series of over carries will occur. Accumulator J.ll goes into over carry
and when the TC Trigger in llA is returned left the RP-TC returns high
to the LI of PSll. The RP-PSll returns low to the RC, RI points of
PIIC. The RP-PIIC releases a positive pulse to pin 6 and out pin 5 to
the LC of PSOC. The Gate is closed.
NOTE:
CTll was Zeroized left on line 8. This opens the
right side of PSOC arm closes the left side.
The overcarries continue around to Accumulator 11M. The TC Trigger in
IlM goes right and the RP-TC goes low to the LI of CllM. The RP-CIlM
'goes high to the RC of PSOC. This side of the Gate is open so the RPPSOC releases a nega.tive pulse to the RC and LC of PAC, triggering PAC
right.
The Mid Numerical Registration is completed (CX Pulse) leaving the M'd
complement value in the Accumulators. DRB returns left to kick PDAti
right for 25 us. PDAM returns left sending its LP low to return PAM
left.
Line 11
Subvisor Decimal - This operation is the same as line 9.
will be triggered right.
PAM again
Line 12
Minidend Shifted until the Decimal Counter reaches 22 - This operation
is the same as line 5. CTll again will be triggered right.
Line 13
Subvisor Decimal Complement - This operation has no function in this
circuit.
Line 14
Subvisor Numerical Registration - The S'r value is larger than the M'd
value so when the addition takes place (PAM is right) another series
of overcarries will occur. Accumulator llA goes into overcarry and
when the TC Trigger in llA is returned left the RP-TC returns high to
the LI of PSll. The RP-·PSll returns low the RI, RC points of PIIC.
The RP of PIIC releases a positive pulse to pin 6 and out pin 5 to the
LC of PSOC. This Gate was conditioned open on line 12 when CTll went
right. The LP-PSOC releases a negative pulse to the RC and LC of PAC,
C-74
triggering PAC back left (went right on line 10). PAC returning left opens
the right side of MCI and closes the left side of MCI.
The overcarries continue around to Accumulator llM. The TC Trigger in llM
goes right and the RP-TC goes low to the LI of CllM. The RP-CllM goes high
to the RC of PSOC. The right side of PSOC was previously conditioned closed
(CTll is right).
The SIr Numerical Registration is completed (CX Pulse) and a Control Ring
Pulse is released • At this same time DRB kicks PDAM right for 25 us. PDAM,
on its return, goes low to the LC of PAM returning PAM left. The Control
Ring Pulse returns ES left. -The RP-ES returns high to the RC and LC of
Gate MCI. As previously stated, the right side of MCI is open (PAC is left).
The RP-MCI releases a negative pulse to the RP of ER, triggering ER right.
Line 15
Storage Decimal - This operation has no fUnction in this circuit.
Line 16
Result is shifted until the Decimal Counter reaches 22 - This operation has
no fUnction in this circuit.
Line 17
Test RIG - This operation has no function in this circuit.
Line 18
Result is placed in Storage - The numerical value has been aligned with the
Storage Decimal and is held in the Accumulators ready to be set in Storage.
Flip Flop MS goes right to set Storage. The value is correct in the
Accumulators but a negative sign must accompany this value. MC2 is right and
'the RP~C2 is low to the LI-MC6. The LD of MC6 goes low to the RD of MC7.
The RP of MC? is cutoff but is. connected to the LP of ¢C2 which must also be
cutoff in order for this line to be free to go high. The result has a
numerical value so the Zero Check lines to the grids of ¢9C will be high.
The plates of ¢9C are low to the LI of ¢9M, tapping off low to the LD of ¢C2.
¢C2 is cutoff so the LP..¢C2 and RP-MC7 are free to go high to the LI of MC8.
The LP~C8 goes low to the LIof SSRD to condition firing the Minus Bit as
shown on plate 46. The LP~C8 also goes low to the LI of MC7. The LP-MC7
goes high to open the Minus Branch Gate EBG as shown on plate 38.
NOTE:
In the event the result, in the A Section, is zero at
this time, both Minus Branching and conditioning the
Minus Bit would be defeated. Any zero answer will always
be a positive indication.
Line 19
B-2 Zeroize - This operation has no function in this circuit.
NOTE:
CTll is not B-2 Zeroized.
C-75
Line 20
Proof Minidend Decimal Complement - This operation is the same as
line 9 except EPM and ENM1 are employed to kick PAMD. PAM is again
triggered right.
.
Line 21
Proof Minidend Numerical Registration - The result is a negative value
but PAM is left so the Add Bias will be raised and the Result value
. added into the Accumulators. When the cycle of RIG is completed
(CX Pulse) DRB returns left to kick PDAM. PDAM returns left after 25
us to return PAM left.
Line 22
Proof Subvisor Decimal - Same as line 11.
Line 23
shifted until the Decimal Counter reaches 22 - This
operation has no function in this circuit.
Proof~linidend
Line 24Proof Subvisor Decimal Complement - Same as line 13.
Line 25
Proof Subvisor Numerical Registration - The Proof Subvisor value will
be subtracted since PAM is on the right. The Proof SIr value is
larger than the Result value so a series of overcarries viII result.
Accumulator 11 A goe s into overc8....""TY and when the TC Trigger in 11 A is
returned left the RP-TC returns high to the LI of PS11. The RP-PS11
returns low to the RI, RC points of P11C. The RP-P11C releases a
positive pulse to pin 6 and out pin 5, to the LC of PSOC. This Gate
was conditioned open on line 12 when CT11 went right. The LP-PSOC
releases a negative pulse to the RC and LC of PAC, triggering PAC
right.
The overcarries continue around to Accumulator 11M. The TC Trigger in
11M goes right and the RP-TC goes low to the LI of C11M. The RP-C11M
goes high to the RCof PSOC. The right side of PSOC was previously
conditioned closed (CT11 is right).
The completion of the Proof Srr Numerical Registration (ex Pulse) returns
DRB left to kick PDAM., After 25 us PDAM returns left to kick PAM back left.
Line 26
Minidend Decimal - This operation 1s the same as line 9 except EPP is used
instead of EM.
Line 27
Proof Result Shifted until the Decimal CotUlter reaches 22 - This
operation has no function in this circuit.
0-76
Line 28
Minidend Numerical Registration - This operation does not have a direct
bearing on this circuit but some explanation will be given to show how
the Accumulators become zero. As shown on plate 18 , the fact that PAC
and EPP are both right, allows the RIGl'l Pulse to be ·released onto the
1M Odd Line. 1M has a nine value so the addition of the one creates an
overcarry. All other Accumulators are nines so this overcarry is
extended to all other Accumulators. The carries are finally satisfied
when llA completes its carry-out to put a one in 1M • . This enables the
AccumMlators to be zero when the Zero Check Operation is called for.
Line 29
Zero Check - This operation has no function in this circuit.
Line 30
Shift 10 - This operation has no function in this circuit.
Line 31
Zero Check - This operation has no function in this circuit.
C-77
M-SECTION
PROCESS
A-SECTION
INPUT
CALC. DEC.
REF. POINT
II 10 9 8 7 6 5 4 3 2 I II 10 9 8 7
N II ~ 10 c:. ND
SiT JR l
~~.
12
DECIMAL
1
CALC
')
MI n nw.n
nnMPT.
~
MID NUM
REn
1
1
a
1
COUNTER
543 2 I DEC M-D
1
1h
ZEROIZE
M' n !=lHTli''I'w.n nr.R A'!'??
SIR DEC ___ COMPL.
7. SIR NUM. REX}
R CA.LC ZEROIZE
g
MI D -.DEG.COMPL
C') ~ n
MI D NUM RtiG
~ l l S I R nw,r.TMAT.
co h.2. MID SHIFTED DCR AT 22
'1
!=ll R m~r..COMPL
L4
SIR NUM REG
5
STaR
J~: IMAT.
L6 • RES SHIFTED DCR AT 22
7. TEST R
R
Rw'!=l '1'0 STOR
g
B_? 7.W,ROTZE
;>0
PR MI D DEC COMPL
:>1
PR Min NTTM
Rm
::>?
PR SIR nw,r.TMAT.
;'1
PR MI D ~H Y .~: nCR A'1' ??
24PR SIR DEC COMPL
~5.
PR. SIR NUM. REG.
~h
MID DECIMAL
'?7
PR RES ~1i ..Ii" "J:!j DCR AT ??
DR MI D NUM REX}
P8 MID NUMREG
bg
7.F.RO CHF.CK
RO SHIli'T 10
tn. ZERO CHECK
CCT
In
1
~
PA~-R
h.
9
9
9 9
9
9
9
0
0
n n n
P lC-R
51 9
9 9 9
99
9 9
g
g
9
9
9
9
9
9
9 9
9 9
9
9
9
g
9
9
9
9
9 9
9 9
n n non
9
g
9
9
9
9 9
9 9
9
g
9
1()
1
1
1
1
1
1
1
1
1
7
7
7
7 9
??
-.9
9
9
0
0
0
non non n n
g
9
9
9
9
g
9 9
99
9
1
9
9
9
1
R
R
9
9 9
9 !l
P dj-
R R R .g
R RR g
R R R R
R R R R
? ? ? ?
? ? ? ?
?
9
9
9
g
2
?
2
I G ?
2
0 0 0 0 0 0 0 0
0
?
2
2
2
2
2
PAC-R
9 9 9 9 9 9 9
9 9 9 9 9 9 9
9 9 9 9 9 9 9
2
2
2
2
00
0
9 9
10
0
100
1
_0
9 9
??
C'1'11
9 9
9
CTl1
9
C'1'l1
~
C'1'11
2 ?
??
r.'I'11
? ?22
C'1'll
2 2
22
CT11
0 0
22
CT11
6
CT11
??
h
CT11
2 2
19
CT11
22
CT11
g
g
g
g
9
9 9 9 9 9 9 9 9 8 8 8 8 9 9 9
~
~
9 9 9 9 9 9 8 8 8 8 9 9 9
C;
C;
9 9 9 9 9 8 8 8 8 9 9 9 9
0 0 0 0 0 DOC
1
1
2 2
9
C'1'll
C'1'11
a
0
1
1
1
a a a
1
0
1
a
1
0
1
a a a
0
0
9
21
22
22
22
22
10
10
CT11
CT11
CT11
CT11
CT11
CT11
CT10
r.'T'1 n
MULTIPLICATION PROCESS
Work Sheet
This work sheet shows the procedure the Computer follows in order to multiply two
numbers together, store the result and prove the answer. The procedure will be
the same in any Multiplication Problem where both the multiplier and multiplicand
are values other than zero. The only variations will occur in the numerical values
and decimal position •
•
e
The problem used as an example has the following values:
Minidend
Subvisor
Result
VI
V2
R
-33.33
33.88
6/5 Decimal
4/3 Decimal
1/0 Decimal
CALCULATOR ZEROIZE
Plate 11C
Line 1
Calculator Zeroized - All Triggers are normalized including Accumulators,
Counters and Control Triggers. Storage is Zeroized.
MINIDENDREGISTRATION
Plate 13C
Line 2
Minidend Decimal Complement ie registered in the Decimal Counter.
Line 3
Mihidend Numerical Registration is made (cycle of RIG).
registered in the Accumulators.
The M'd value is
MULTIPLICATION PROCESS CALL
Plate 22C
Line 4
Subvisor Decimal Complement is added in the Decimal Counter.
Line 5
The M-D Constant of 17 is added in the Decimal Counter.
C-79
MULTIPLICATION PROCESS
Plate'23C
Line 6
The Minidend is shifted until its, first digit reaches Accumulator lIM. All
,shifts are ,counted in the Decimal Counter. Only the first 11 shifts are
counted in the M-D Counter.
Line 7
First Subvisor Addition is made. The Sir Numerical Registration is made
(cycle of RIG). A one is subtracted from the MId digit in 11M.
Line' B and 9
The Subvisor Additions continue until the digit in lIM reaches zero.
Line 10
Shift until a digit reaches lIM.
M-D Counter.
This shift is counted in both the Decimal and
Line 11,12 and 13
The Subvisor is added until the digit in lIM reaches zero.
Line 14 to 21
Shifts occur until a digit reaches lIM. The SIr is added until lIM reaches
zero. This operation of shifts and Sir Additions will continue until the M-D
Counter reaches 22. Any number that reaches lIM after the M-D Counter reaches
22 must be a Result digit.
Line 22
Shift until a digit reaches lIM. By this time the M-D Counter has reached
22 so the digit that arrives in 11M ,must be a Result digit. This is the
completion of Multiplication.
Line 23
B-2 Zeroize. The A Section and M-D Counter are Zeroized leaving a maximum of
11 Result digits.
RESULT TO STORAGE
Plate 15C
Line 24
The Storage Decimal is added in the Decimal Counter.
C-BO
Line 25
The Result is shifted to align with the Storage Decimal.
indicated by the Decimal Counter reaching 22.
This alignment is
Line 26
Test RIG. A numerical registration (cycle of RIG) of' Storage is made.
This 'value is zerO.
Line 27
Result to Storage. Any digits in Accumulators lA to lOA will be set in
Storage.
Line 28
B-2 Zeroize. Accumulators lA-llA are Zeroized leaving the Result in
~torage.
PROOF MINIDEND REGISTRATION
Plate 16C
Line 29
Proof Minidend Decimal Complement is registered in the Decimal Counter.
Line 30
Proof Minidend Numerical Registration is made (cycle of RIG).
value is added in the A Section.
The Result
DIVISIONPRQCESS CALL
Plate 240
Line 31-96
See Division Work Sheet for this operation from line
operation.
MINIDEND SUBTRACTION
Plate 180
Lin~
97
Minidend Decimal is added in the Decimal Counter.
C-81
4~1
for theory of
Line 98
Proof Result is shifted to align with the MId Decimal. This alignment is
indicated by the Decimal Counter reaching 22. These shifts are also counted
in the Check Counter.
Line 99
Minidend Numerical Registration is made (cycle of RIG). The value in the
Accumulators is now zero in this problem. It is possible, in some problems,
for the Accumulators to have a value of nines.
ZERO CHECK
Plate 19C
Line 100
A Shift Operation occurs to bring the count in the Check Counter to 10.
In this particular problem 3 shifts are required. The number of shifts will
vary from zero to ten depending upon the problem.
Line 101
A Zero Check is now made in Accumulators lA to IDA. In this particular
problem the Zero Check is successful. If the Zero Check is not successful,
because of nines, a one is added to lA t() create a Zero Check condition.
C-82
A-SECTION
INPUT
M-SECTION
PROCESS'
CALC. DEC.
REf. POINT
II 1019 8 7 6 5 4 3 2 I II 10 9 8 7
f-j II~ 10:. ND
11
1')
~T
1
?
3.
~R ~ I.:i ~. DECIMAL
CALC 7.F.HOT7.F.D
M'D DEC COMPL.
M' D NUM. RID.
4
SIR DEC COMI'L.
I)
CONSTANT 17
6
SHIFT 1st DIGIT IN IJM
2 1 s t S'R ADD
R
?nn S'R Ann
(3
COUNTER
5 4 3 2 IDEO M-D
-3333
'i1, R
CCT
R
1h
3
?
3 3
'i1
3
'i
3
3
3
3
3
3
3
3
3
3
3
3
11
11
20
15
8
8
8
C'1'll
CTl1
1 1 1 1
F. 7 7 I'F.
11
G'1'l1
g
1,.ti ~ I R Ann
n 1 1 3
1 0 1 6 4
R
11
C'1'11
~~W~~S~H~~'-~DIGf~:IT~IN~1~_JM~____~3~3~~3~-;~~r-r-+-+-;-1-~-r-r1~~O~1~~bc~·~4~-r-+__L9-1__~12~~C~TIyLl~
~ 11
hIt. ~ I R Ann
? 1 1
1
n '=i 0 ? 8
9
I?
C'1'11
il?
?nd S'R A D n 1 1 1
1 0 8 4 1 6
9
I?
CT11
[13
3rd S'R ADD
0 3 .3
1 1 1 8 0 4
9
12
CTn
114
SHIFT-DIGIT IN 11M
3 3 1 .~ 1 8 0 4
10
13
CTll
tL5. 1st SIR ADD
2 3
1 1 2 1 4 2 8
10
13
CT11
L6. 2nd SIR ADD
1 3
1 1 2 4 8 1 6
10
13
CT11
7. 3rd S'R ADD
0 3
1 1 2 8 2 0 4
10
13
CTn
8. SHIFT-DIGIT IN 11M
3
1 1 ? 8 2
0. A
11
14
CTll
_9
1st S' R A D D ?
1 1 ? 8 I) 4 ? R
11
14
(;'1'11
::>0. 2nd SIR ADD
1
II? R R R 1 6
11l4.
C'1'11
?1
1,.ti ~IR Ann
0
1 1 2 9 2 2 0 4
11
14
CT11
22. SHIFT-DIGIT IN IJM
1 1 2
9 2 2 0 4
2
22
CTll
tn R-? ZEROIZE
II? 9 2 2 0 4
2
0
fJ
P4
STOR DECIMAL
1 1 2 9 2 2 0 4
18
0
~5. RES. SHIFT DCR AT 22
2 2 0 4
1 1 2 9
22
~6 • TEST RIG
2 2 0 4
1 1 2. 9
22
/7 • RES. TO STOR.
2 2 0 4
1 1 2 9
22
;>8. B-2 ZEROIZE
2 2 0 4
0 0 0 0 0 0 0 0 0 0 0
22
;>9. PRo M'.D DEC. COMPL.
2 2 0 4
6
30 • PR. WiD NUM. RID.
2 2 0 4
1 1 2 9
6
31. PRo S"R DECIMAL
2 2 0 4
1 1 2 9
19
82. CONSTANT 17
2 2 0 4
1 1 2 9
14
3
3
8
8
11
11
-
·.M-SECTION
CALC. DEC.
PROCESS
N II
!= J
~
I~':!
i':lJ1
85.
11~
37.
38.
39.
40.
41
Q
I
42.
~ 41
44.
45.
46.
~7.
~8.
~9.
50
51
52.
n1
54
r)~
Ii~
':)7..
58
59..
;0
1
i2.
;1
64.
II )~
:~ !~
Nil")
JR
f l l!i:l.. Ul:.l;lMAL
SH woo,' T1TflT·'T'IN 11M
1!'It; PR SIR 'T'RIAl, SURI'T'
PR. SIR ADD BACK
SHTF'T' 1 POSI'T'ION,
1st PRSIR TRIAL SUBT
PR. SIR ADD BACK
SHIFT 1 POSITION
1st PRo SIR TRIAL SUBIT
PR SIR ADD BACK
SHIFT 1 POSITION
1st PR SIR TRIAL SUBT~
PR. S'R ADD BACK
SHIFT 1 POSITION
1st PRo SIR TRIAL SUB'T.
PRo SIR ADD BACK
SHIFT 1 POSITION
1st PRo SIR TRIAL SUBIT
PRo SIR ADD BACK
SHIFT 1 POSITION
1st PR SIR TRIAL SUBIT
?1'lt'l PR S'R 'T'RIAl, SUR' 'T'
3rd PRo SIR TRIAL SUBIT
4t.h PR S'R TRIAL SUBIT
PR SIR ADD RACK
SHIFT 1 .POSITION
1st PR SIR TRIAL SUBIT
?nd PR S'R TRIAL SUB 1 T
::lrd PR SIR TRIAL. SUB'T
4th PRo SIR TRIAL SUBIT
PR. S'R ADD BACK
SHIFT 1 POSITION
1st PRo SIR TRIAL SUB'T
A-SECTION
INPUT
REF. POINT
II 10 9 8 1 6 5 4 3 2 I II 10 9 8 7
11
- ~
-
a
1
1':l
COUNTER
5 4 3 2 I DEC M-D CCT
~
~
~
':l
R
R
6
6
1
?
1h
1
1
1
1
1 1
1 2
1 2
1 2
2 9
2 9
? 9
9 2
?
?
9
9
2
9
9
9
2
2
9
2
?
9
2
2
2
2
2
2
2
0
0 4
0 4
4
4
4
4
4
4
2
2
0
0
n
0
0
n
?
?
n 4
n 4
2 2 0
2 0 4
2 2 0 4
2 2 0 4
2 0 4
2 0 4
2 2 0 4
2 0 4
? 0 4
2 0 4
0 4
0 4
0 4
4
9
2
?
?
?
9
9
9
9
9
9
4
1
2
9
9
9
9
9
9
6
6
1
2
9
9
9
9
9
9 6
6
1
2
9
9
9
9
9
2
9
9
9
9
9
?
q
q
q
q
q
1
9
6 2
1
1 1
9 Q 7 2
1 1
6
q
1
7
1
1
1
1
2
::l
~
9
q
9
9
9
9
')
4
3
4
1
3 2
1
')
4
4
"l
"l
4
4
3
3
3
5
':
1
')
':
9
9
9
9
9
9
'"l
1
1
7
1
1
1 1
1 1
1 1
1 2
3 2
1 2
2 9
4 9
2 9
2
?
.~.
?
Ll
1
"2
1 2
2 9
7 9 0
4 5 1
1 1 2
7 7 4
1 1 2
1 2 8
7 8 9
4 5 0
1 1 1
7 7 3
1 1 1
1 1 8
4
6
8
0
8
2
4
6
8
0
C
-::
'"l
'"l
9
" "2
2
2
2
?
0
0
0
0
0
8 0
0 4
.d
10
10
10
11
11
11
12
12
12
13
13
13
14
14
14
I?
I?
12
12
12
12
12
12
12
12
12
12
12
12
I?
11;
,1;
1"
15
16
16
16
12
12
12
12
12
12
12
13
13
13
13
13
13
14
14
16
16
16
17
17
17
17
17
17
18
1R
,,,
M-SECTION
A-SECTION
CALC. DEC.
PROCESS
INPUT
REF. POINT
COUNTER
II 10 9 8 7 6 5 4 :3 2 I II 10 9 8 7 6 5 4 :3 2 I 0 EC M-D
NH"IDE~D
11
_
':i
':i
3 2
il
Ll
()
Ll
Ll
1R
lLl
~
1
0
6
0
1
7
3
0
6
1
2
1
6
7
8
0
1
h
4
14
8
4
4
18
18
18
19
19
19
19
19
1g
S;TOR~~~DECIMAl
':i
':i
1~
hI).
?nd PR. SIR TRIAL SUB IT.
3
~~
':iT't1 PH ~IH THTAT. mTRI'I'
':i
67. 4th PR SIR TRIAL SUB'T
3
68. PR SIR ADD BACK
3
69. SHIFT 1 POSITION
3 3
70. 1st PR SIR TRIAL SUB'T
3 3
3 3
71. 2nd PR SIR TRIAL SUBIT
72. 3rd PR SIR TRIAL SUB'T
3 3
3 3
73. 4th PR SIR TRIAL SUB'T
(") 74 • PR SIR ADD BACK
3 3
cb 7r; ~HT1i'T 1 POSTTTON
':i ':i 1
U1
7h
1st PR SIR TRIAL SUB'T
1 ':i1
77
PH SIH ADn RACK
~
~':i
7P.
SHIFT 1 POSITION
1 1 .1 1
79. TRIAL SUB'T
3 3 3 3
80. ADD BACK
1 3 3 3
81. SHIFT
1 3 3 3
82 • TRIAL SUB I T
3 3 3 3
81. ADD BACK
1 1 1 1
84 • SHIFT
3 3 3 3
185 • TRIAL SUB I T
1 1 1 1
86. ADD BACK
3 3 3 3
87. SHIFT
3 3 3 3
88. TRIAL SUB'T
3 3 3 3
89. ADD BACK
3 3 3 3
90. SHIFT
3 3 3 3
91. TRIAL SUBIT
3 3 3 3
~9~2~.-=AD=D~BA=C=K____________-+-4~3~~3~3~3~4-4
93. SHIFT 1 POSITION
3 3 3 3
94 • TRIAL SUB I T
3 3 3 3
95. ADD BACK
3 3 3 3
Igh
R-? 7.F.ROT7.F.
. . 3 1 ':i
':i
3 5 9
3 3
3
3
3
3
3
1
2
3
5
3
3
1
1
1
?
2
9 9 9 9 7
1
1 0
6
3
0
9 9 9 9 9 9 6
9
9
9
9
9 9 9
9
9
g
9
q
9
h
h
h
h
h
4
6
8
0
2
l?
~
_9
9
9
h
h
1"1
1h
1h
lh
1?
?1
?1
17
17
17
1?
??
??
1R
??
1P.
I
2 9 9
?n
?n
?n
?1
14
14
15
15
15
15
15
1P.
1
?
9
9
9
9
q
q
h
h
1?
1
1
?
9
9
9 9 9
g
h
h
1?
2 9 9 9 9 9 9 h
h
1
?
?
?
':i
?O
?n
?n
?1
?1
?1
':i
?1
2 9 9 9 9 9 9 h h 1 2
4
4
4
4
??
??
??
n
CC T
A-SECTION
INPUT
M-SECTION
CALC. DEC.
REF. POINT
PROCESS
II 10 9 8 7 6 5 4 3 2 I II 10 9 8 7 8 5 4 3 2
N N :O::ND
.~
"e R
-
"'l
3
i"'l
~ ~...
DECIMAL
3
3
"'J
"'l
8
DEC M-D CCT
8
l~
M'D DECIMAL
9R
PR
99.
M'D NUM. REG.
0
22
7
3
CTlfi
SHIFU.",>:";CC",",,,-T=_:l=-O---i--t-+_+__+__+_+--I-t-__t_---+--+-+--t--t--j---t--;-+-t---t--+--t----.L--j----+----""-"-'~
RES
SHIFTED DCR AT
3
?~
3
3
15
97.
tIaa.
101.
oI
11
i
,
COUNTER
3
3 3
0 0
3
a
3
??
7
ZERO CHECK
r-------------------~-+--t--~-r-~--j-~_;_+-"i-4-+_+__;__+_~~__t__+_---_+_--__t_--~·
~~--------------~-+-+--+-4-~~-+--t--+-+--~-+--t--+-+-~-+-+--;-----t----+---~
MULTIPLICATION DIVISION COUNTER
Plate 21C
This Counter is employed in the Multiplication or Division processes only. The
method of reading the Counter is the same as the Decimal Counter. The Counter
receives its count from Shift Pulses and is conditioned opened or closed to accept
these pulses. The actual operation of this Counter will be explained when it is
used in Multiplication or Division, see plates 23 or 25. The main purpose of
the Counter is to keep track of the Result value so the Computer knows when the
actual Multiplication or Division process is completed.
General Operation
Gate PGMD controls the admission of Shift Pulses into the M-D Counter. This Gate
has a cathode control which is conditioned by the Multiplication or Division
Process. The left input to the Gate is controlled by the RP of Trigger PDB 80
that the Gate can be opened or closed during the Process. The M-D Counter has a
capacity of 22.
MULTIPLICATION PROCESS CALL
Plate 22C
This circuit is the prelude to the actual Multiplication Process. The Process
Call Circuit prepares Gates, KB and makes the proper Decimal Registrations. This
circuit is the preliminary for plate 23.
Operation
Trigger EM is returned left by a Control Ring Pulse. The LP of EM returns low to
the RC of ES, triggering ES right. The LP of ES goes high to the LI of ESA.The
LP of ESA goes low to LI of ESK and to diode ENM to check for Minus Factor. The
K of ESK goes low to all ESF stages finding one stage which conducts to raise IB
as shown on plate 38.
The RP of ES goes low to the L1 of EP2 to check on Process. The LP of EP2 is
cutoff and connected to the LP of EIM which is also cutoff (X Process). The LP of
EP2 and LP of EIM raise the plates of diode EIMI. The LK of EIMl raises the LI of
DPGl, opening the Gate. The RIC of EIMI raises the RI of IMD, tapping off the RD
of DMD to the LD of IMP as shown on plate 23. TheRP of DMD goes low. to the RP of
DPl1. The RP of DPl1 going low lowe.rs theDBC cathode line to condition for a Deciinal
Complement Registration. The LP of DEM goes high to the RC of DEAl and also high to
DBT raising the DBT cathode line. The RP of DEAl releases a negative pulse to tbe
RP of DEA, kicking DEA right.
After 150 us DEA returns left and the LP of DEA returns low to the RC of DPl
starting a cycle of Decimal Registration. This will be a Decimal Complement
Registration since the DBC cathode line is low.
C-87
After 25 us DP1 ret.urns left and the LP of DP1 goes low to the LC of DAl-16. The LP
of DAl-16 releases a positive pulse to the LC and RC points of Ga~e DKG. DKG is open
on the right since Trigger DK is left at this time. The RP of DKG releases a negative
pulse to the RP of DP2 to continue the Decimal Registration.
The completion of a Decimal Registration is signaled by a negative pulse from the RP
of DIC to the RC of DAl-16. The RP of DAl-16 releases a positive pulse to the LC of
the open Gate DPGl. The LP of DPGl releases a negative pulse to the RC and LC points
of DK, triggering DK right. The RP of DK goes low to the RI Of DKG, closing the
right Gate. The LP of DK goes high to the LI of DKG, opening the left Gate. The LD
of DKGtaps off high to open DII andDB16, as shown on plate 4, to condition the
Decimal Counter Gates fora. Constant 17 Registration. The LP of DK also goes high to
the LC of DEAl. The LP of DEAl releases a negative pulse to the RP of DEA, kicking
DEli. right.
After 150 us DEA returns left and the LP of DEA returns low to the RC of DP1 starting
a cycle of Decimal Registration. This registration will be to register the M-D
Constant of 17. The value of 17 is a correction factor needed because of the Calculator Decimal Reference Point Location.
After 25 us DPl returns left sending the LP of DP1 low to the LC of DAl-16. The LP
of DA1-16releases a positive pulse to the RC and LC points of Gate DKG. The left
side of DKG is open (UK is right). The LP ~f DKG releases a negative pulse to the
RP of DP16. The only decimals registered were the 1 and 16 for a total of 17.
The completion of a Decimal Registration is signaled by a negative pulse from the
RP of DIC to the RC of DAl-16. The RP of DAl-16 releases a positive pulse to the LC
of the open Gate DPG1. The LP of DPG1 releases a negative pulse to the RC and LC
points of DK,.returning DK left. DK returning left reconditions DKG open on the
right.and closed on the left. The RP of DK returns high to the LC of PMM to start
shifting theM' d to 11M. This operation is shown on plate 23.
MULTIPLICATION PROCESS
Plate 23C
This circuit shows the controls required to perform the Mu1tip1ica.tion Operation.
Computer does this operation as follow:
1.
2.
3.
4.
5.
6.
7.
Shift the first Mfd digit to lIM.
Add the SIr in the A Section and for each addition decrease the lIM
digit by one.
When the 11M digit reaches zero, shift the next digit into 11M.
Add the SIr in the A Section as before.
Continue this process counting each shif.'t in the M-D Counter.
When a· digi t arrives in 11M and the M-D Counter has reached or
exceeded 22 the Multiplication Operation has been completed.
Zeroizethe A Section so only a maximum of 11 Result digits remain.
Operation
This circuit is best explained when a specific problem is employed as an example.
C-88
The
The Work Sheet problem, line at a time, will be this example.
Lines 1 to 3 are not shown in this circuit.
Line 4
Subvisor Decimal Complement Registration - This operation is shown on
plate 22. The preparation on plate 22 will raise the LD of PMP. The
LP of PMP goes high to the following.
1.
The RI of PSG - The RP of PSG goes low to the L1 of PSGK.
The K of PSGK goes low tg the K of PGMD, opening this Gate.
2.
The RI· of PMG opening this Gate. The RD of PMG taps off
high to RD of PDX, RD of PDMSand the right bias of P~G.
PDX ,and P~ are now opened but PDMS still has a high cathode.
These Gates will remain open 'all during the ES Control Circuit Operation.
Line 5
Constant 17 is registered in the Decimal
shown on this circuit (DK right).
COUht~r.
This operation is not
Line 6
Shift Operation '!lIltil the first Mtd digit arrives in 11M. Trigger DK
returns left sending the RP of DK high to theLC of PMM. The LP of PMM
releases a negative pulse to the BP of PMD2, kicking PMD2 right. PMD2
has a 25 us delay which at this. time serves no purpose.
After 25 us PDM2 returns left. The LP of PMD2 returns low to the RC of
PMl, triggering PMl right. TheLP of PMl goes high to the LP of diode
S1-l. The cathodes of S1-l go high to the LD of SMC, starting the Shift
Operation.
On line 4 it was stated that the M-D Counter Gate PGMD was opened to .
receive shifts into this Counter. The entire Counter is shown on plate 21
but in this circuit enough is shown to represent the control it employs.
After 6 shifts PC16 goes right and the RP of PC16 goes low to trigger PDT
right. At a count of 10, PC4 goes right and the LP of PC4 goes high to
open the left side of PCG. At a count o£ 11, PCl again goes right sending
the LP of PCl high to the LCof the open GatePCG. The LP of PCG releases
a negative pulse to the LC of PDT, .triggering PDT back left. The LP of PDT
going. low does the following:
1.
Triggers PI1S right. The BP of PIIS lowers the L1 of PIIG. The
K of PllG goes low to the K of PDMS. PDMS is now fully open.
NOTE:
The cathode control on PDMS is necessary to prevent
the Shift Operation from being stopped too soon. This
condition could arise in the proof. Shifting is to
be stopped when the first digit reaches 11M. In the
C-89
proof, some digits may already be in the M Section when
shifting starts. These digits, should n9t stop shifts •.
Since the Result is never larger than 11 digits the
.
Gate PDMS doesn't open until +1 shifts are cOlllple.ted.'
2.
Triggers PDB right. The RP of PDB goes low to the LI of PGMD. Thifl
low level closes the M-D Counter to prevent counting any more shifts
at this -time.
Shifting continues until the first M'd digit arrives .in lIM., This
digit will, in the work sheet, trigger Tl right and ~ left in
AccU1llUlatorl1M.,The RP of.'1¢ and LP of Tl go high to theinpP.ts
ofPMS. The plates of ,PMS go low to the LI o:f PlvW., The LP of PlvW
goes low to the LI of PM12 closing the left side of this Gate. The
RP of PM£i goes high to the RC of the open Gates PDX and. POO • The
RP of PDXreleases.a negative pulse to the LP ofPDB, triggering PDB
back left. The RP of PDB returning high to the L1 of PGMD reopens
the M-D Counter to count shifts. The RP of PDMS releases a negative
pulse to the· LP of PMl, returning PMl left. The LP ofPMl returns
low through SI-l stopping shifts.
Line 7
The First Subvisor Addition is made. The RP of PMl returns high to the RC of
PMG. Gate PMG was opened by the Process so the RP of PMG releases a negative
pulse to the RP of PMDl, ki-cking PMDI right. The LP of PMDI goes high to the LC
of the open Gate PMG. The LI of PMG is high from the LP of PC16 since PC16 is
right. , The LP ofPMG releas.es a negative pulse to the, RP o.f PMBT,triggering
. PMBT right. The LP·of' BmT goes h1,gh to the RI o.f. PM12 opening the.right side o.f
this Gate.
,,
After 14 us PMDI returns left and sends the LP of PMDI low to. the LC o.f PDM3.
The LA of PIN3 releases ·~po.sitive pulse to the RC o.f the open Gate PM12
(PMBT is right). The RP of PM12, releases a negative pulsfl to the ~. of PM2,
,triggering ~2 right.
The RP of PM2 goes low to. theLI of PM23. The LP o.f PM23 goes high to raise
SB and oa+.l for a cycle of RIG. ··The SB operation is shown o.n plate 45, The
LP of PM2 goeS,higJI to the LI of PMDRto. open the left side of this Gate. The
. LD of PMDR taps off high to the RI of Gate II-II to .allow the RIG I' Pulse to
enter AccUlllUlator 11M as shown on plate 5.
Line 8,
The Se90nd Subvisor Addition is made. '. The completion o.f the first Sir Addition
is signified by a CX Pulse to. the RCof PM3,_.kicking PM3 right., The LA of PM3
goes high to the LC of the closed Gate PM12 (digit in 11M so t4eLP·o.f PMI.I .is lo.w).
After 25 us PM3 returns left and the LP of, PM3 returns low to the RC of PM23.
The RA .. o.f pti23 r,elea,sesa positive pulse to the, I.C of the open Gate PMDR (PM2 is
right). The LP o.f PMDR releases a negative pulse to the RP of RS to start ano.ther
cycle of RIG. ' SB is still high:since PM2. is right.
C-90
Line 9
The Third Subvisor Addition is made.
This operation is identical to line 8.
Line 10
Shift until a digit arrives in lIM. The completion of the third SIr
Addition is signified by a CX Pulse to the RC of PM3, kicking PM3 right.
The LA of PM3 goes high to the LC of the now opened Gate PM12.
Accumulator lIM is now zero so both inputs of PMS are low cutting off
both plates of PMS. The plates of PMS go high to the LI of PM¢. The
LP of PM¢ goes high to the LI of PM12, opening this Gate. The LP of
PM12 releases a negative ~ilse to the LP of PM2, triggering PM2 back
left. The LP of PM2 returns low to close Gates PMDR and II-II. The
RP of PM2 returns high to lower SB.
The RP of PM2 also goes high to the RC of PMM. The RP of PMM releases
a negative pulse to the RP of PMD2, kicking PMD2 right. PMD2 has a
25 us delay to give SB time to lower. After 25 us PMD2 returns left
and the LP of PMD2 goes low to the RC of PMl, triggering PMl right.
The LP of PMl goes high to the LP of diode SI-l. The cathodes of SI-l
go high to the LD of SMC starting the Shift Oper[;r~ion.
The next digit arrives in lIM. The shifts are counted in both the M-D
and Decimal Counters. The Input to PMS goes high causing the plates of
PMS to· go low. The plates of PMS go low to the LI of PMf\. The LP of
pM¢ goes low to the LI of PM12 closing the left side of this Gate. The
RP of PM¢ goes high to the RC of the open Gate PDMS.The RP of PDMS
releases a negative pulse to the LP of PMl, returning PMl left. The
LP of PMl returns low through SI-l stopping shifts.
Line 11
First Subvisor Addition is made.
This operation is identical to line 7.
Line 12
Second Subvisor Addition is made.
This operation is identical to line 8.
Line 13
Third Subvisor Addition is made.
This operation is identical to line 8.
Line 14
Shift until a digit arrives in 11M.
This operation is identical to line 10.
Lines 15 through 21
Follow identical patterns which have been explained on lines 7, 8 and 10.
Line 22
Shift until a digit arrives in lIM.
C-91
At this time the M-D Counter has
reached a COlUlt of 22. When the count of 22 was reached Trigger PC16
returned left. The LP of PC16 going low does the following:
1.
2.
3.
PMDZ is kicked right:.
Gate PMG is closed on the left side.
PMBT is returned left. LP of PMBT goes low to the RI of
PM12 closing the right side of this Gate.
Even though the M-D Counter reaches 22, shifting can continue since the Shift
Operation is controlled only by a digit arriving in IlM. At this time the digit
that will'now arrive in 11M will be a Result digit as proven by the fact that
the M-D Counter has', reached 22. The digit in 11M causes the plates of PMS to go
low. The low from PMS lowers the LI of PMjj. The RP ofPMJ6 goes high to the RC
of the open Gate PDMS. The RP of PDMS releases a negative pulse to the LP of
PMl, returning PMl lef't stopping shifts.
The RP of' PM.O also goes high to the RC of the open Gate Amplifier PZG. The RP
of PZG releases a negative
to the RP of ~D, kicking PM¢D right. ~D
has a 25 us delay to allowPMDZ time to operate if the Result di~lt arrives in
11M at the same time, theM-D Counter re8.ch~s 22. Arter 25 us p)f)D returns left
sending its LP low to the LC of PMDZ, returning PMDZ left.
pUlse
NOTE:
Stage PM22 clamps PMBT lef't when the M-D Counter
reaches 22. The clamping action on PMBT prevents
retriggering PMBT back right in the event the left
side of Gate PMG is slow in closing at the time the
M-D Counter reaches 22 when the first' Result digit
arrives in lIM. If PMBT were retriggered an additional
RIG and shift would occur and the first Result digit,
would be lost.
Line 23
B-2 Zeroize. After PMDZ returns left the RP of PMDZ goes high to the LC of the
open Gate EMDC (EZB2 is left). The LP of DIDO releases a negative pulse to the
RP of FlIDZ, kicking EMDZ right. The LP of 1lMDZ goes high to the RC of ECS. The
RP of ECS releases 8. negative pulse to the RP of' EZB2, kicking EZB2 right. The
RP of EZB2 goes low to perf'orm the B2 Zeroize as shown on plate 36 • This
operation will Zeroize the A Section of the Accumulators, M-D Counter and the
Check C0unter. The B-2 Zeroize is completed when EZB2 returns left after a 300
us delay.
After 450 us EMDZ returns left. The RP of EMDZ returns high to the RC of EMDC.
The RP of EMDC releases a negative pulse onto the Control Ring. This Contro+
Ring Pulse returns ES left and pulls ER right. The ER or Result Operation is
shown on plate 15. ,
C-92
SIGN COMPUTATION
Plate 20C
The writeup for Complementize explains the method used to determine the sign of the
answer in Addition or Subtraction Process. In Multiplication or Division the sign
of the Result is minus if only one of the factors is negative. If both factors are
negative the sign of the result will be positive.
Operation
The example on the Multiplication Process Work Sheet uses a negative MId in the
calculation resulting in a negative answer. This problem will be used as an example.
Trigger EM goes right to raise the MId Keyboard Bias. The MId is a negative number
so the Minus Neon Common Line comes high to raise the grids of MC4. The LP of MC4
goes low to the LI of MC5. The RI of MC5 is also low since MC2 is left. The plates
of MC5 going high raise the RP of MCX. The cathodes of MCX go high to the LI of
PSIG, opening the Gate.
The LP of EM goes high to the LI of EMA causing the LP of EMA to go low to the LC
of diode ENM. The LP of ENM releases a negative pulse to the RD of PAMD, kicking
PAMD right. PAMD has a time delay to give KB time to rise. PAMD returning left
sends its RP high to the LC of the open Gate PSIG. The LP of PSIG releases a
negative pulse to the RC of PS1G. The RP of PS1G releases a positive pulse to the
RC and LC of Gate PS.
NOTE:
The Process is Multiplication so the LK of diode PIMD
is low. The plates of PIMD go low to the L1 of PPI. The
LP of PPI goes high to the R1 of PS opening the Gate.
The RP of PS releases a negative pulse to the RC and LC of PAT, triggering PAT right.
The return of EM kicks ES right to raise the SIr KB. The S'r is a positive number
so the Minus Neon Common is not raised and Gate PS1G is closed. During ES time,
therefore, PAT remains on the right.
PAT, being right during ER time, indicates a negative answer. The Result Storage
Minus Bit and Minus Branch Gate are conditioned as follows. The LP of PAT goes
high to the RI of MC8. The RP of MC8 goes low to:
1.
The L1 of SSRO to condition the Minus Bit as shown on plate 46.
2.
The L1 of MC? causing the LP of MC? to go high and raise the
L1 of EBG, the Minus Branch Gate.
C-93
DIVISION PROCESS
Work Sheet
This work sheet shows the procedure the Computer follows in ord.er to divide one
number b,ythe other, store the result and prove the answer. The procedure will be
the .same in any Division problem where both the divisor and dividend are values .
other than' zero. The only variations will occur in the numerical values and decimal
position. The problem used as an example has the following values:
Minidend
Vl
44.44
5/4 Decimal
Subvisor
V2
2.2
6/5 Decimal
Result'
R
1/0 Decimal
C.AI.CULA TOR ZERO IZE
Plate 110
Line I
CalculatorZeroized. All Triggers are normalized including Accumulators,
Counters &ld Control Triggers. Storage isZeroized.
MINIDEND REGISTRATION
Plate 13C
Line 2
'Minidend'Decimal Complement is registered in the Decimal Counter.
Minidend Numerical Registration is made (cycle of RIG).
registered in t~e Accumulators.
DIVISION PROCESS CALL
'Plat~ 24C'
Line 4
Subvisor Decimal is added in the Decimal Counter.
Line 5
The M-D Constant of 17 is added in the Decimal Counter.
C-94
The Mid is
DIVISION PROCESS
Plate 25C
Line 6
The Minidend is shifted until its first digit reaches Accumulator 11M.
All shifts are counted in the Decimal Counter. Only the first 11 shifts
and one extra count (total of 12) are counted in the M-D Counter.
Line 7
First Subvisor Trial Subtraction is made. The SIr Numerical Registration
is made (cycle of RIG). This Trial Subtraction is unsuccessful and so
indicated by an overcarry in Accumulator 1IA. A one is also added in
Accumulator 1M from RIG 11. A Section raises Subtract Bias, M Section raises
Add Bias. 1M Accumulator has a value of 2.
Line 8
Subvisor is Added Back. The S'r Numerical Registration is made (cycle
of RIG). The A Section is returned to zero. 1M is returned to zero.
A Section raises Add Bias, M Section raises Subtract Bias.
Line 9
Minidend is shifted one position. The Decimal Counter counts this shift.
The M-D Counter remains closed to shifts.
Line 10
Same as line 7.
Line 11
Same as line 8.
Line 12
Same as line 9.
Lines 13 through 24 inclusive continue in a similar sequence.
Line 25
First Subvisor Trial Subtraction is made. The S'r Numerical Registration
is made (cycle of RIG). The Mid has been Shifted into a position so that
when the Sir is subtracted no llA over carry occurs. A one is added in
Accumulator 1M by the RIG1' Pulse. The M-D Counter is now opened to
count shifts.
Line 26
Second Subvisor Trial Subtraction is made.
C-95
The SIr Numerical Registration
is again made (cycle of RIG). Again no llA overcarry occurs.
Another one is added to Accumulator]M making a total of 2.
Line 27
Third Subvisor Trial Subtraction is made. Another Sir Numerical
Registration is made (cycle of RIG). An llA over carry occurs
indicating an Unsuccessful Trial Subtraction. A one is added
to IMby RIGI'and the overcarry making a total of 4 in
Accumulator IM.
Line 28
Subvisor Add Back is made. A Sir Numerical Registration is made
(cycle of RIG). The Sir is added in the A Section which returns
the A Section and Accumulator ]M to the values prior to the last
Trial Subtraction. Accumulator 1M is now 2.
Line 29
Shift one position. All digits are shifted one position.
shift is counted in both the Decimal and M-D Counter.
This
Line 30
Same as line 7.
Line 31
Same as line 8.
Line 32
Same as line 9 except the M-D counts this shift.
Lines 33-36
Same as lines 25-28.
Lines 37-57 continue with Trial Subtractions, Add Back and shifts.
Line 58
Shift one position. The digits are shifted one position. The
M-D Counter reaches a count of 22 indicating the completion of
Division. The first Result digit is in 11M.
Line 59
Same as line 7.
Line 60
Same as line 8.
C-96
Line 61
B-2 Zeroize. The A Section and M-D Counter are Zeroized leaving a maximum
of 11 Result digits.
RESULT TO STORAGE
Plate. 15C
Line 62
The Storage Decimal is added in the Decimal Counter.
Line 63
The result is shifted to align with the Storage Decimal. This
alignment is indicated by the Decimal CQunter reaching 22.
Line 64
Test RIG. A Numerical Registration (cycle of RIG) of Storage is
made. This value is zero.
Line 65
Result to Storage.
set in Storage.
Any digit in Accumulators lA to lOA will be
Line 66
B-2 Zeroize. Accumulators lA-llA are Zeroized leaving the Result in
Storage.
PROOF MINIDEND REGISTRATION
Plate 16C
Line 67
Proof Minidend Decimal Complement is registered in the Decimal
Counter.
Line 68
Proof Minidend Numerical Registration is made (cycle of RIG).
Result value is added in the A Section.
The
MULTIPLICATION PROCESS CALL
Plate 22C
Lines 69-78--See Multiplication Work Sheet for this operation from line 4-23 for
C-97
theory of operation.
MINIDEND SUBTRACTION
Plate 18C
Line 79
Minidend Decimal is added in the Decimal Counter
Line 80
Proof Result is shifted to align with the M'd Decimal. This
alignment is indicated by the Decimal Counter reaching 22.
These shifts are also counted in the Check Counter.
Line 81
Minidend Numerical Registration is made (cycle of RIG). The value
in the Accumulators is now zero in this problem. It is possible, in
some problems, for the Accumulators to have a value of nines.
ZERO CHECK
Plate19C
Line 82
A Shift Operation occurs to bring the count in the Check Counter to
10. In this particular problem 4 shifts are required. The number of
shifts will vary from zero to ten depending upon the problem.
Line 83
A Zero Check is now made in AccUImllatorB lA-lOA. In this particular
problem the Zero Check is' successful. If the Zero Check is not
successful because of nines, a one is added to lA to create a Zero
Check condition.
..C-98
·
A-SECTION
INPUT
M-SECTION
CALC. DEC.
PROCESS
f"
REF. POINT
II 10 9 8 7 6 5 4 3 2 I II 10 9 8 7
I II
II
J
l'F
)::
~ [)
~
n~
[ ~ ~
UECIMAL
1. CALC. ZEROIZE
? loP nnli'r. r.OMPT,
3. M'D BUM. REn.
.1
~'R nli'r.TMAT.
~
6.
7.
B.
9.
n
I
\0
\0
110.
111
12.
13.
14.
[5.
Q.6.
117.
118.
11q
bn
I?L
b?
b~
?4
~5.
D~
D7
DB.
~9.
~O.
BL
bl'\
CON~TANT
1
'1'
IN
4 3 2 I DEC
.1
11
1t::
" "
4 4 4 4
4 -4 i -4
4 4 4 4
4
4
4
4
4
4 4
4 4
4 4
4
4
4
4
4
111
1h
1h
16.
16
1h
17
4' 4
17
1~
1Q
1.1
f"'l'11
2 9 9 9 9 9 7 8
4
2 9 9 9 9 9 7 8
4 4
4 4
4
4
4
4
4
4
4
4
A
A
4
4
2 9 9 9 9 9 7 8
4 4
4
4
4
4
4
4- 4
2 9
9 9
9
9
7
2 9 9 9 q
q
7 R 4 4 4 4
8
A
4
4
4' 4' 14'
q
A
4
4
? 4 ·4 4
.1 .1 4
4 4 4 4
? ? ·4 4
1
0 0 4 4
2
4 9 9 9 9 9 7 8 4 4
2
0 0 A -i
2 9
9
9
9
R
.1
2
2 2 9
2 0
?
0
.9
9
9
9
8
10
10
?l
1h
10
10
10
11
i1
11
12
CT11
CT11
CTli
CT11
CT11
CTl1
CT11
CT11
CTll
CT11
CTll
CTll
r.T11
r.Tll
CTl1
r.Tll
CT11
CTl1
r.T11
CTll
CTll
CTll
eT11
CTl1
CTll
CT11
4
4 4 4 4
4 4 4 4
M-D CCT
4 .4 4
J.'J
17
SHIFT-DIGIT IN lIM
1st S'R TRIAL SUB'T
S'R ADD BACK
SHIFT 1 POSITION
1st S'R TRIAL SUB'T
S'R ADD BACK
SHIFT 1 POSITION
1st SIR TRIAL SUB'T
S'R ADD.BACK
SHIFT 1 POSITION
1st S'R TRIAL SUB'T
SIR ADD BACK
SHIFT 1 POH HIN
1 A+. ~ I 'R 'l''RT AT ~TTR' T
~''R Ann R.d(!Ir
SHIFT 1 POSITION
1FIt. HI R TRIAl STIR'T
~''R Ann RAr:tc
~'H 'WT 1 pnR IT TIlN
1st SIR TRIAL SUB'T
?nn ~'R TRIAL SUR'T
'.:!.,.n S'R TRTAT. SUB'T
S'R ADD BACK
SHIFT 1 POSITION
1st SIR TRIAL SUBIT
SIR ADD BACK
e 5
COUNTER
4
2 4
4 4
4
12
1?
13
13.
13
1A
14
14
1J;j
Fi
17
12
12
I?
12
12
12
12
12
1?
12
1?
12
1?
I?
I?
1?
1?
1?
1?
1?
12
12
I?
1'.:!
13
~,.
-_....
-
--
- -..
A-SECTION
I
INPUT
M-SECTION
CALC. DEC.
PROCESS
1--'----
REF·POINT
. . . .-
II 10 9
~ II~ ID i-
NIJ
'lR
~U ~V '~
~ 1 ~R :\ l!il..,
DECIMAL
...
'1....:l
~~
':u::
37.
~,
I
----
,-
..
--
I
~OSITION
TRIAL SUBI~
-
i _ ....,
2
(")
BACK
?
?
?
0
?
~~IET 1 ~OSITIQN
41. 1st S'R TRIAIL SUB' T _____
~-"---.S~f-i
4i
SHIFT 1 POSITlQL
o
o I-~_lli Si 1l...'!RIAL__SJJ..B..!j,'___,_
?
.,-
SH..IFT 1 POSI'W1N_,_____
38.. 1st SIR TRIAL SUBIT
39. SIR ADD BACK
SIR ADD
46. SHIFT 1
_4.7. 1st st~
48. SiR ADD
..4-~~HIF:..'t. -,l
50. 1st SIR
51. SIR ADD
~ SHIFT 1
-I
~
--SlJl..--AI)I) ~CK
r~
1'=
1
---- - - -
SUB I ~
TRUr. .llUB..'...T__.,.
'
_.
.--~
-f=
?
2
a
a
2
2
2
BACK _.
? a
0
2
2_ ~
POSITION
---....TRIAL SUB'T
2 0 2
BACK2 0 2
o
2 _.- .
2
POSITION
1-- 2
=02".
53.,~t_~'R TRIAL SUB'T
-.54. SIR ADD BACK
~ o 2
55. SHIFT 1 POSITION
2 0 2,_ t--~'. 1st SIR TRIAL SUB'T
'L"' 0 2
SIR
ADD
BACK
57.
2 0 2
1---._----r-~JLJHIFLl.....£.QSITIQN
..2. 0 ?
2~. 1st SIR TRIAL SUB'T
2 0 2
? n ?
1-60. SiR ADD~
? 0 ?'
nl. BLZEB,QIZE
h?
STOR DECIMAT
? 0 ?
h1
?
RF..Cl
RHTET.EILD.CJL.AT 22
TEST RIG
64
""
.-1---t=r-
0
0
4 9_ 9
I
--
-~
Q
9
9
"
6
?.
At
.-?-
Jl.
7
-
9 ,...9
~, 9
g
--
7
R
9} 9
7
R
9
9
1-- --
18
.lB-_
18
1R
'9
-
19
1':.
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?O
?()
?1
.2..L.
1----
..2. 9 9 9 9
2 9
>---< 1--
W1
9
9
-
8
9
"I-- .lL - ..
9 19 --7
?~
??
??
8
??
2 9
9
9
9
9
7
8
2 9
9
9
9
9
7
8
1
1
1
-
2
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2
9
9
9
9 ,-.2. 7
3
RI
')
3.
L1
2
9
9
9
9
9
7._
M-D CCT
-
'2
.- i - -
9
.-~
I---
l..:l
--2 ~-t,
-
?
0 2 2
0 2
...2.
0 2
? 0 ?
2.... 0 2
2 0 2
2 0
?
~
-g
?
,
- -- ---
1
2
~
COUNTER
5 4 3 2 i II 10 9 8 7 8 5 4 3 2 I DEC
I---
C! R--~L
3rd S' R
Sl7 6
~
c---33...--l.s.t-.q I R TRIAIL-..3UB I T
_":1.<1
r
8
4
4
4
-
"2
0
0
?O
??
??
14
14
CT11
r.Tl1
CT11
14
CT]~
14
111
1'1
15
CTll
CTn
CTll
_lh
CTll
lh
r.Tl1
lh
r.T11
17
r.Tll
17
CTn
17
r.T11
1R
CTL1
lR
CTl1
1R
CTll
10
CT1l
f!T11
19..
CT].l
19
?O
CTll
?O I CT11
?O
CTll
?1
CTn
?1 I CT11
?1
CTll
1')1')
r.T'1
22
cm "
??
CT11
0
~
PI
A-SECTION
INPUT
M-SECTION
PROCESS
~
II
44
12
11
?
4~
2
H? 7.F.ROT7.R
?
67.
PR
hR
h9
PH
M'D DEC COMPL
M' n NtJMREG
on??
0
h
? 0
h
PR
SIR nF.C
71
7?
7~
~.
75-
76 •
77.
78.
79.
80 •
81.
82.
83.
IR
Ih
0
20
2 0
2
202
102
o 0 ?
2
4 4
1
4
4
4
4
o
22
o
2
?
COMPT~
CONSTANT 17
SHIFT-DIGIT IN 11M
lst PR SIR ADDl.'l'J.U.N
2nd PR SIR .ADDITION
SHIFT DIGIT IN 11M
1st SIR ADDITION
2nd S' R ADDITION
SHIFT-DIGIT IN 11M
B2 ZEROIZE
M'D DECIMAL
RES. SHIFTED DCRAT 22
M'D SUBTRACTION
SHIFT - CCT IS 10
ZERO CHECK
CC T
?
hh
70
~
5 4 3 2 IDE C M -0
2
.65.
~
ID~ND
e
COUNTER
~ Hf- DECIMAL
RF.STILT TO S'PORAGF.
~T
C')
CALC. DEC.
REF. POINT
I i 10 9 8 7 6 5 4 3 2 I II 10 9 8 7
~7
I?
2
2
10
10
4
4
10
?
4
?
4
4 4 4 4
444 4
4 444
11
11
11
1?
1?
11
12
4
4
13
1~
22
o
16
4 4 4 4
a
0
0
0
22
??
4
4
10
DIVISION PROCESS CALL
Plate 24C
This circuit is the prelude to the actual Division Process. The Division Process
Call Circuit prepares Gates, KB and makes the proper Decimal Registrations. This
circuit is the preliminary for plate 25.
Operation
Trigger EM is returned left by a Control Ring Pulse. The LP of EM returns low to
the RC of ES, triggering ES right. The LP of ES goes high to the LI of ESA. The
LP of ESA goes low to the LI of ESK and to diode ENM to check for Minus Factor.
The K-ESK goes low to all ESF stages finding one stage which conducts to raise KB
as shown on plate 38.
The RP of ES goes low to the LI of EP2 to check on Process. The RP of EP2 is
cutoff and connected to the LP of EID which is also cutoff (+ Process). The RP
of EP2 and LP of EID raise the plates of diode EID2. The LK of .EID2 raises the LI
of DPGl, opening the Gate. The RK of EID2 goes high to the LI of PDP which is shown
on plate 25. The RK of EID2 also goes high to theI RC of DEA2. The RP of DEA2
releases a negative pulse to the RP of DEA, kicking DEA right.
After 150 us DEA returns left and the LP of DEA returns low to the RC of DPI
starting a cycle of Decimal Registration. This will be a True Decimal Registration
since the DBT line is low.
After 25 us DPI returns left and the LP of DPI goes low to the LC of DAl-16. The
LP of DAl-16 releases a positive pulse to the LC and RC points of Gate DKG. DKG is
open on the right side since Trigger lJ{ is left at this time. The RP of DKG releases a negative pulse to the RP of DP2 to continue the Decimal Registration. The
completion of a Decimal Registration is signaled by a negative pulse from the RP of
DIC to the RC of DAl-16. The RP of DAl-16 releases a posi ti ve pulse to the LC of
the open Gate DPGl. The LP of DPGl releases a negative pulse to the RC and LC points
of DK, triggering DK right. The RP of DK goes low to the RI of DICG, closing the
right Gate. The LP of DKG goes high to the LI of DKG, opening the left Gate. The
LD of DKG taps off high to open DII and DB16, as shown on plate 4. This conditions
. 'the Decimal Counter Gates for a Constant 17 Registration. The LP of DK goes high to
the LC of DEAl also. The LP of DEAl releases a negative pulse to the RP of DEA,
kicking DEA right.
After 150 us DE! returns left and the LP of DEA returns low to the RC of DPI
starting a cycle of Decimal Registration. This registration will be to register the
'M-D Constant of 17. The value of 17 is a correction factor needed because of the
Calculator Decimal Reference Point Location.
After 25 us DPl returns left se~~ing the LP of DPI low to the LC of DAl-16. The LP
of DAl-16 releases a negative pulse to the RC and LC points of Gate DKG. The left
side of DKG is open (DK is right). The LP of DKG releases a negative pulse to the
RP of DP16. The only decimals registered were the 1 and 16 for a total of 17.
The completion of a Decimal 'Registration is signaled by a negative pulse from the
C-l02
RP of DIC to the RC of DAl-16. The RP of DAl-16 releases a positive pulse to the
LC of the open Gate DPGl. The LP of DPGl releases a negative pulse to the RC and
LC points of DK, returning DK left. DK returning left reconditions DKG open on
the right and closed on the left. The RP of DK returns high to the LC of PMM to
start shifting the MId to lIM. This operation is shown on plate 25.
C-103
DIVISION PROCESS
Plate 25C
This circuit shows the controls required to perform the Division Operation.
Computer does this operation as follows.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
The
Shift the first MId digit to 11M.
Subtract the SIr in the A Section (Trial Subtraction).
An llA to 1M overcarry indicates an Unsuccessful Trial
Subtraction.
The SIr is Added Back.
Shift one position. Count in Decimal Counter only.
Steps 2, 3, 4 and 5 continue until no llA to 1M over carry
occurs on a Trial Subtraction. A one is registered in 1M
for each Trial Subtraction. The Trial Subtractions continue
until an llA to 1M over carry occurs.
The Sir is Added Back.
Shift one position. This shift is counted in both the M-D
and Decimal Counters.
Each individual shift from now on is added in the M-D
Counter until this Counter reaches 22. At a count of 22
the first Result digit is always in lIM.
Sir Trial Subtraction.
Sir Add Back.
Zeroize the A Section so only a maximum of 11 Result digits
remain.
Operation
This circuit is best explained when a specific problem is employed as an example.
The Work Sheet problem, line at a time, will be this example. Lines 1 to 3 are
not shown in this circuit.
Line 4
Subvisor Decimal Registration. This operation is shown on plate 24.
The preparation on plate 24 will raise the LI of PDP. The LP of
PDP goes high to the LI of PDMS, opening this Gate. The LP of
PDP also goes high to the LI of PSG whose plate goes low through
PSGK to lower the cathode on PGMD as shown on plate 21 • These
Gates will remain open all during the ES Control Circuit Operation.
Line 5
Constant 17 is registered in the Decimal Counter.
is not shown on this circuit (DK right).
This operation
Line 6
Shift Operation until the first Mid digit arrives in 11M.
C-104
Trigger
DK returns left sending the RP of DK high to the LC of PMM. The LP of
PMM releases a negative pulse to the RP of PMD2, kicking PMD2 right.
PMD2 has a 25 us delay which at this time serves no purpose.
After 25 us PMD2 returns left. The LP of PMD2 returns low to the RC
of PM1, triggering PM1 right. The LP of PM1 goes high to the LP of
diode SI-1. The cathodes of SI-1 go high to the LD of SMC, starting
the Shift Operation.
On line 4 it was stated that the M-D Counter Gate PGMD was opened to
receive shifts into this Counter. The entire Counter is shown on
plate 21 but in this circuit enough is shown to represent the control
it employs.
After 6 shifts PC16 goes right and the RP of PC16 goes low to trigger
PDT right. At a count of 10 PC4 goes right and the LP of PC4 goes high
to open the left side of PCG. At a count of 11 PC1 again goes right
sending the LP of PC1 high to the LC of the open Gate PCG. The LP of
PCG releases a negative pulse to the LC of PDT, triggering PDT back
left. The LP of PDT going low does the following.
1.
Triggers P1lS right. The RP of P11S1owers theLI of
P11G. The K of P11G goes low to the K of PDMS. PDMS
is now fully open.
NOTE:
2.
The cathode control on PDMS is necess~ry to
prevent the Shift Operation from being stopped
too soon. This condition could arise in the
proof. Shifting is to, be stopped when the first
digit reaches lIM. In the proof, some digits
may already be in the M Section when shifting
starts. These digits should not stop shifts.
Since the Result is never larger than 11 digits
the Gate PilMS doesn't open until 11 shifts are
completed.
Triggers PDB right. The RP ofPDB goes low to the L1
of PGMD. This low level closes the M-D Counter to prevent
counting any more shifts at this time.
Shifting continues until the first M'd digit arrives in lIM.
will, in the work sheet, trigger T.0 left in Accumulator lIM.
T~ goes high to the RI of PMS.
This digit
The RP of
The plates of PMS go low to the LI of~. The RP of~ goes high to
the LC of the open Gate PDMS, The RP of PDMS releases a negative pulse to
the RC of PDND and RP of PDN kicking both stages right.
TheLP of PDN goes high to
a negative pulse to the LP
The plates of PGMDre1ease
count in this counter to a
the RC of peG and PGMD. The RP of PCG releases
of PM1, returning PM1 left and stopping shifts.
a negative pulse to the M-D Counter to bring the
value of 12.
C-105
Line 7
First SubvisorTrial Subtraction. After 25 us PDND returns left.
The RP of PDND returns high to the RC of PDM and the RP of PDM
releases a negative pulse to the RP of PDl, triggering PDl right.
The RP of PDl goes low to the RI of PDA. The RP of PDA goes high
to raise the Trial Subtraction Bias (lA-llA-, lM-IO+, IlM+).
Raising Sign Bias automatically calls for a cycle of RIG as shown
on plate 45. The RD of PDA taps off low to the RD of PDlM. The
RP of PDlM goes high to the RP'of diode PX as shown on plate 5.
The high from PI opens Gate II-II to allow the RIGl' Pulse to
pass into lM. The LP of PDl goes high to raise the LI of PDX,
opening this Gate. The LD of PDXtaps off high to the RD of
PMDR, opening this Gate.
The subtraction of the SIr, A Section is zero, results in a
series of overcarries. The llA over carry through PSll goes low
to the RC of PDS, triggering PDS right. Accumulator lM has a
value of 2. The completion of this SIr Registration is indicated
by a CX Pulse. The CX Pulse to the RC of PM3 kicks PM3 right.
The RP of PM3 goes low to the LC of PDS, returning PDS left. The
LP of PDS returns low to the LC of PDl and PD2, returning PDl
left. PDl returning left sends its LP low to close Gates PDX and
~IDR.
The RP of PDl gOp.s high to PDA to lower Sign Bias.
After 25 us PM3 returns left sending its LP low to the RC of PM23.
The RP of PM23 releases a positive pulse to the LC of PDX and RC of
PMDR. Both Gates are closed so the pulse is rejected.
The LP of PDl also returns low to the RC of PD2, triggering PD2
right.
Line 8
Subvisor Add Back. PD2 was triggered right by the return of PDl
so the RP of PD2 goes low to the L1 of PDA. The LP of PDA goes
high to raise Add Back Sign Bias (lA-llA+, lM-IOM-, IlM-). Raising
Sign Bias automatically calls for a cycle of RIG as shown on
plate 45. The LD of PDA taps off low to the LD of PDlM. The-. LP
of PDlM goes high to the LP of diode PX as shown on plate 5.
The high from PX opens Gate II-II to allow the RIGl' Pulse to
pass intolM.
The Add Back of the Sir results in a series of overcarries. The
llA overcarry through PSll goes low to the RC of PDS, triggering
PDS right. The count in Accumulator 1M is now zero.
The completion of this Sir Registration is indicated by a CX Pulse.
The CX Pulse to the RC of PM3 kicks PM3 right. The RP of PM3 goes
.low to the LCof PDS,triggering PDS left. The LP of PDS goes low
to the LC of PDl and PD2, triggeringPD2 left. The return of PD2
left causes the RP of PD2 to return high to PDA and lower Sign Bias.
After 25 us PM3 returns left but as on line 7 the Gates are closed.
The LP of PD2 returns low to the RC of PD2D, kicking PD2D right.
C-106
Line 9
Shift one position. After 25 us PD2D returns left. The purpose
of the delay of PD2D is to allow Sign Bias to lower before
starting shifts. The LP of PD2D returns low to the RC of PDM3.
The RA of PDM3 releases a positive pulse to the LC of open Gate
PDM (PC16 is right). The LP of PDM releases a negative pulse
to the RP of PD3, triggering PD3 right.
The LP of PD3 goes high to the RP of diode SI-l. The I-SIl goes
high to the LD of SMC to call for shifts as shown on plate 4.
The signal that a shift occurs comes from the LP of SG. The LP
of SG releases a negative pulse to the LC of PD3, triggering PD3
back left.
The LP of PD3 returns low to SI-l to stop shifts (only one occurred)
and low to the RC of PD1, triggering PDl right.
Line 10
Same as line 7 after PD1 goes right.
Line 11
Same as line 8.
Line 12
Same as line 9.
Lines 13-24
These operations are similar to lines 7, 8 and 9.
Line 25
First Sir Trial Subtraction. PDl was triggered right when PD3
returned left on line 24. The RP of PDl goes low to the RI of
PDA. The RP of PDA goes high to raise the Trial Subtraction
Sign Bias (lA-llA-, lM-1OM+, llM+). Raising Sign Bias automatically calls for a cycle .of RIG as shown on plate 45. The RD
of PDA taps off low to the RD of PDlM. The RP of PDlM goes high
to the RP of diode PI as show. on plate 5. The high trom PI
opens Gate I1-1l to allow the RIGl' Pulse to pass into lH. The
LP of PDl goes high to the L1 of PDI, opening this Gate. The LD
of PDI taps off-high to the RD of PMDR, opening this Gate.
This time when the Sir is subtracted the number present in the A
Section is larger than the Sir value so no 1lA to 1M over carry
occurs. Accumulator 1M has a value of one as a result of the .RIGlI
Pulse.
The completion of the S'r Registration is indicated by a CI Pulse.
The CX Pulse to the RC of PM3 kicks FM3 right. The RP of PM3 goes
C-107
low to the LC of PDS but is rejected since PDS is left.
After 25 us PM3 returns left. The LP of PM3 returns low to
the RC of PM23. The RA of PM23 releases a positive pulse to
the LC of open Gate PDX and RC of open Gate PMDR.
The LPof PDX releases a negative pulse to theLP of PDB"
trigge:r1ng PDB back left. The RP of PDB returns high to the
LI of PGMD to reopen the M-D Counter to accept any forthcoming Shift Pulses. The RP of HIDR releases a negative
pulse to the RP of RS starting another cycle of RIG. Sign
Bias for Trial Subtraction is still raised since PDl is on
the right.
Line 26
Same as line 25 except PDB remains left.
Line 27
This subtraction of the Sir results in a series of overcarries.
The III over carry through PSII goes low to the RC of' PDS"
triggering ~DS right.
The CX Pulse kicks PM3 right. The RP of PM3 goes low to the
LC of PDS" triggering PDS back left.
The LP of PDS goes low to the LC
left. PDl returning left closes
PM3 is nullified. The RP of PDI
Bias. The L'P of PDI goes low to
Accumulator JM bas a value of 2.
of PDI and PD2, triggering PDl back
PDX and PMDR so that the return of
goes high to PDA to lower Sign
the RC of PD2" triggering PD2 right.
Line 28
Same as line 8.
Line 29
Same as line 9.
Line 30
Same as line 7.
Line 31
Same as line 8.
Line .32
Same as line 9.
Line 33
Same as line 25.
C-108
Line 34
Same as line 26.
Line 35
Same as line 27.
Lines 36-57
These operations are similar to lines 7, 8 and 9.
Line 58
Shift one position. This Shift Pulse brings the count in the M-D
Counter to 22. .A count of 22 is indicated by PC16 returning left.
The RP of PC16 goes high to the LI of PZG, opening the Gate. The
LP of PC16 goes low to the LI of FilM, closing this Gate and low to
the RC of PMDZ, triggering PMDZ right.
Line 59
Same as line 7.
Line 60
Same as line 8.
Line 61
B-2 Zeroize. PD2 returns left sending its LP low to the Re of PD2D,
kicking PD2D, right. After 25 us PD2D returns left. The LP of PD2D
goes low to the RC of PDM3. The RA of PDM3 releases a positive pulse
to the LC of the closed Gate PDM and LC of the open Gate PZG. The LP
of PZG releases a negative pulse to the LP of PMDZ, triggering PMDZ
back left.
The RP of PMDZ goes high to the LO of the open Gate EMDC (EZB2 is left).
The LP of »IDC releases a negative pulse to the RP of HMDZ, kicking
EMDZ right. The LP of EMDZ goes high to the RC of EGS. The RP of ECS
releases a negative pulse to the RP of EZB2, kicking EZB2 right. ~he
RP of EZB2 goes low to pel'form the B-2 Zeroize as shown on plate 36.
This operation will Zeroize the A Section of the Accumulators, M-D
Counter and the Check Counter. The B-2 Zeroize is completed when EZB2
returns left after a 300 us delay. After 450 us EMDZ returns left. The
RP of EMDZ returns high to the RC of 1!MDC. The RP of l!MDC releases a
negative pulse onto the Control Ring. This Control Ring Pulse returns
ES left and pulls ER right. The ER or Result Operation is shown on
plate 15.
0-109
ZERO FACTOR
Plate 26C
Zero Factor is the term employed in Multiplication or Division Process when either
or both factors are zero. A special circuit is required to handle Zero Factor
because the method the Computer uses in Multiplication or Division of digits is not
prepared to handle a zero value. For example if the Mid is zero there is no way to
stop shifts when the Mid is shifted until the first digit arrives in lIM.
There are three basic Zero Factor operations: Mid is zero, Sir is zero or both are
zero. The basic theory of operation is the same in either Multiplication or Division.
The general procedure followed in Zero Factor is as follows. If either or both
factors are zero, the result mUst be zero. Therefo~e, i f the Proof Mfd Numerical
Registration is zero the step is repeated~ This repeat is a form of proof to see
if the Proof MId is again zero. If the repeat of the step shows the Proof Mfd to
again be zero a Step Advance can be realized to progress to the next step.
All cases of Zero Factor in Multiplication and ~ +N are numerically a true zero.
+ ,0 is an indeterminate and N + fJ is infinity. The Computer cannot give either
result so zero is given instead. In case the Programmer does not wish to accept
a zero answer for either or both cases (N + ~, ,0 +~) the alternative of Stop or
Sort and Trip may be employed as shown on plate 27. It is common practice in
programming to use a,0 +,0 step plugged to Stop to indicate a card out of sequence,
etc.
~
Operation
N
+ ,0 or N x
•
. t
~
•
The only time this circuit is affected is during the registration of a zero value.
This 'cQndition first arises during the Sir NUlIlerical Registration. At this time
the M'dhas been shifted into the M Section leaving the A Section zero. After the
SIr Registration the A Section is still zero and that is where this circuit begins
to function.
Trigger Rl is returned left following the SIr cycle of· RIG. The LP of Rl goes low
to the RC of CD, kicking CD right. After 50 us CD returns left sending its LP low
to the LC of aDA.; The LP of CDA. releases a positive puIs e to the LC of the open
Gate~F2. (Either xor + Process lol.ters the plates ofPIMD. .The LI of PPI is low
so the LP of PPI is high to the LI of ,0F2, opening ·theGate). The LPof ~F2 releases
a negative pulse to the RP of OFl, triggering OFI right. The LP of tJFl goes high to
theLC of Gatest\F3, ,~F4 and. ~F5.,", The RCof ~F4 is also pulsed by this high level.
The input to the thre'e Gates, ,0F3, /1F4 and tJF5 is controlled by the Zero pheck Line.
Since the Sir was zero, the A Section, at this time has no value. The LI of /19C has
a low input so both ~9C and /19Cl are cutoff. The LP of ~9C and /19Cl go high to the
LI of ~F4. TheLD of ~F4 taps off high to the LD of ,0F3 and /1F5. All three Gates
now have high grids. Each Gate also has a cathode control, EMK, ESK or ERIC. Since
the Computer is functioning during ES time, only the ESK line is low. Therefore,
only Gate ~F4 has both a high grid and low cathode which is required to enable a
.C,..110
Gate to be open. The RI of ¢F4 is low since .fIMD is lefte The LP of ¢F4 releases
a negative pulse to the RP of ~SR, triggering ¢SR right. The LP of ¢SR goes high
to the L1 of ¢EZ1, opening the Gate, and to the RC of ¢F2. 'l'he RP of ¢F2 releases
a negative pulse to the RP of ¢FS, kicking ¢FS right.
The LP of ¢FS goes high to the LC of ¢ESP. The LP of ¢ESP releases a negative
pulse to the Control Ring, returning ES left, and to the RC of ¢FD1, kicking ¢FDl
right •. ES returning left triggers ER right. The RP of ¢FS also goes low to the RP
of 0FZD, kicking 0FZD right. 0FZD is.-a 5 MS delay to replace EMZ guard delay. The
LP of ¢FZD goes high to the RI of .el9M and RBK. The RP of .el9M goes low to the LP of
DMP to prevent the Proof'M'd Numerical Registration until Storage has been cleared.
RBK prevents further RIG cycles until EPM time.
After 25 us ¢FS returns left. TheRP of ¢FS returns high to the RC of ¢ESP. The RP
of ¢ESP releases a second negative ~llse to the Control Ring. This second pulse
returns ER back left. ER returning left kicks EDPZ righto
¢FDl returns left sending its LP low to the I.e of ¢Fl, triggering ¢Fl back left.
By pulsing ER within 25 us the Computer performed no normal Result functions as
shown on plate 15. There was no Storage Set. Pulse so once Storage has been cleared
its value will remain zero.
The Computer now proceeds through the B-2 Ze;l"oize (EPZ) ~ndthen EPM .is brought
.
right •. At the completion of the Proof M'd Numerical Registration Trigger Rl returns
left. The LP of Rl goes low to the RC of CD, kicking CD right. After 50 us CD
returns left sending its LP low to the LC of CDA. The LP of eDA releases a positive
pulse to the LC of the open Gate ¢F2. The LP of ¢F2 releases a negative pulse to the
RP of .£1Fl, triggering .£1Fl right. The LP of .f\Fl goes high to the LC of Gates ¢F3,
.£1F4 and ¢F5.
The value in the A Section is zero so the grids of the three Gates are high. The
Computer is in EPM time so the ERK line is low. Only Gate .£1F5 now has a high ~rid
and low cathode. The LP of ¢F5 releases a negative pulse to the RC and LC of ~RS,
triggering ¢RS right. The LP of ~RS ~oes high to the LC of the closed Gate ¢EZ (¢MD
is left) and the LC of the open Gate ~EZl (¢SR is right). The LP of ¢EZl releases a
negative pulse to the RP of EZ to restart the step over again.
EZ going right initiates a B-2, B-5 Zeroize.
left except ¢RS which remains on the right.
This Zero.ize will return all Triggers
The repeat of this step follows the same procedure as previously explained. The only
exception occurs during EP.M when .£1F5 again releases a negative pulse to the RC and
LC of ¢RS.
¢RS was still o~the right so the negative pulse from ¢F5 to the RC and LC of ¢RS,
triggers ¢RS back left. The RP of ¢RScgoes high to the RC of the closed Gate ¢EZ
and the RC of the open Gate ¢EZ1. The RP of .0EZl releases a negativ.e pulse to the
RP of :roD, kicking EGD right. EnD going right will advance the Computer into the
next step as shown on plate 11.
In the Division Process the Programmer may want to prevent any continued calculation
from a N +¢ step. This can be accomplished by plugging the N +¢ hub on the Program/Plugboard to Stop or Sort. The control on this Plugboard hub is as follows.
'l'he Process being Division lowers the grids of ¢FD3.
C-111
In N + ¢, 'frigger ¢SR is right
and ~ is left. The LP of J1MD is low to the LI of £lFRl. The RP of j'jSR is low to
the RI of j'jFRl. The plates of £lFRl are tied to the LP of £lFD3. All three plates
are cutoff so they are free to go high to the RP of the diode £l~M. The RK of £lFM
goes high to the N 7J1 hub on the plugboard. Further explanation of this control
is shown on plate 27.
J1
7 N
or
J1
x N
The first time a zero value is registered
The problem encountered with a zero value
prevent continuous shifting an Artificial
The problem cannot be allowed to continue
is during the M'd Numerical Registration.
for the Mid is stopping shifts. To
One will be inserted for this purpose.
because a false answer would result.
The completion of the MId cycle of RIG is indicated by the return of Trigger Rl.
The LP of Rl returns low to theRC of CD, kicking CD right. After 50 us CD returns
left sending its LP low to the LC of CDA. The LP of CDA releases a positive pulse
to the RC of the open Gate £lF2. (This Gate is opened by the low process through
PIMD and out high through PPI). The LP of £lF2 releases a negative pulse to the RP
of £lFl, triggering £lFl right.
The LP of £lFl goes high to the LC of Gates £lF3, J1F4 and £lF5. Since the value in
the A Section is zero at this time the LI of .09C is low. The LP of £l9C and £l9Cl
will be high to the L1 of £lF4. The LD of J1F4 taps off high to the LD of £lF3 and £lF5.
All three Gates have high ~rids. The Computer is in EM time so the EMK line is low.
This means that only Gate ~F3 has both a high grid and low cathode.
The LP of Gate £lF3 releases a negative pulse to the RP of £jMD, triggering,0MD right.
The LP of £lMD goes high to the LI of £lF4, conditioning this Gate. The LD of £lF4
taps off high to £lEZ, opening this Gate. The LP of £lMD also goes high to the RC of
£lF3. The RP of £lF3 releases a negative pulse to the llA Accumulator Odd Line. This
gives Accumulator llA a value of one. This value of one will be used to stop
shifting, during ES, when this digit reaches lIM.
EM is returned left by a Control Ring Pulse which also kicks £lFDl right. After 25 us
£lFDl returns left sending its LP low to the 1C of .£jFl, triggering £lFl back left.
EM returning left triggers ES to the right. The Srr is a numerical value so the Zero
Factor circuit supposedly should not be affected. Since an artificial one va.lue
was inserted during EM the problem cannot be allowed to continue in a normal pattern.
The completion of the SIr RIG pulses CD, which through CDA and open Gate £lF2,
triggers ;1Fl right. The LP of .f!Fl goes high to the LC of jjF3, £lF4 and £lF5 and also
to the RC of jjF4. The A Section is no longer zero (Sir RIG) so the LI of £l9C is
high. The LP of jj9C and J19Cl is low to the LI of J1F4. The LD of J1F4 taps off low
to the LD of £lF3 and J1F5. The grids of all three Gates are low so the Gates are
closed. The RI of J1F4 is high (~ is right) and, since the ESK line is low during
ES, the right side of jjF4 is open. The RP of J1F4 releases a negative pulse to the
RP of£lFS, kicking J1FSright • .
The operation of £lFS throughj'jESP results in two Control Ring Pulses being released.
These Control Ring Pulses return ES to bring ER right and 25 us later ER is returned
left to bring up EDPZ.
The release of the low level from the RP of J1FS kicks £lFZD.
C-112
J1FZD is a guard delay
to prevent reading out from Storage during EPM before the Zeroize of Storage is
completed.
After the B-2 Zeroize EPM goes right. This operation is fully explained under the
N +~ write up. The only exception is that the left side of Gate ~EZ is used instead
of the left side of Gate ~EZI.
The step is then repeated following the same procedure as previously stated. When
is pulsed the second time the RP of ~RS pulses the RC of ~EZ. ~EZ releases a
negative pulse to the RP of EnD to advance to the next step.
~RS
- No provision is made in ~ + N to prevent the Step Advance Operation since ~ + N is
mathematically zero.
~
+ ~ or
~ x ~
This operation is a combination of N +~ and ~ + N.
will explain this operation.
Combining these two writeups
II). the Division Process the Programmer may want to'prevent any continued calculation
·from ~ + ~ step. This can be. accomplished by plugging the ~. + tJ hub on the Plugboard
to Stop or Sort. The control on this Plugboard hub is as follows:
ThePtocessbeingDi;ision l~~erst1ie ~id8 of~FD3·.:th,t1 +~, Triggers bID and tJSR
are right. The RP of ~ is low to theLI of tJFR2."The RP of ~SR is low to the RI
of J}FRl. The RD of ~FRI taps off low to the RD of ~FR2 • The plates of J}FR2 and the
RP of ~FD3 are tied together. All three plates are cutoff so they are free to go
high to the LP of diode ~FM. The LK of J}FM goes high to the ~ + ~ hub on the Plugboard. Further explanation of this control is shown on plate 27.
In the event the Computer does not show Zero Factor on the repeat of the step the
Trigger ~RS would still be right. ~RS would be returned left by the ESI pulse
through the diode tJRSZ. Any time the ste]) is repeated by the Timer, stage MC3 would
also return ~RS left as shown on plate 20.
C-113
M-SECTION
A-SECTION
CA Le. DEC.
REF-POINT
PROCESS
N
N
+ tJ
x
INPUT
II 10 9 8 1 6 5 4 3 2 I II 10 9 8 7
N INID~
~IJ
111
11h
16
2
M' n NTTM Rm
SIR ItI:l lMAI.
2
?
2
?
.ANT 17
2
2
ST"lR
~
4
o
.....
~..-IE. DECIMAL
OAIJC ZEROIZED
M'D DEC COMPL
I=i
';U.NL:S'
h
7
SHTli'T M' n '1'0 1 TM
~'R 'l'RTAT. ~TTRr'l'
,;UN 'HI
lUNG
?
?
?
~
,
,h
1e::
,?
1'J
B-? ZEROIZE
?
?
1
1h
II
PRM' n n1i'l'! r.OMPT,
PR M' n NTTM lHi'fl.
'J
?
'J
?
1
1
F.7.
M'D DEC GOMEL
n n
n
,
l'
1?
1.'1
1\
II
.'
PI
SIR DECIMAL
?
?
~
CONSTANT 17
SHIFT M'D _TO 11M
SIR TRIAL SUB'T
CONTROL RING
B-2 ZEROIZE
PR M'D DF..c COMPI..
PR M'D NDM. REG.
?
?
PI
?1
22.
r.'l'1'
r.T' ,
CT11
CTll
l'
16
17..
19
20.
CTl1
CT11
n / l . . f ' l
15
18
CCT
11
11
5
R
9
I;::I
5 4 3 2 I DEC M-D
2
SUBV S lR
1
?
e
COUNTER
2
2
?
?
2
1 e::
, 'J
0'1'1'
,
If;
1?
2
1
1
1
16
.f'l
£}
_2 2
2 2
CTll
C'1'11
CTll
CTl1
CT11
.f'l
M-SECTION
A-SECTION
.fj+N
.fjXN
INPUT
CALC. DEC.
REF. POINT
PROCESS
COUNTER
II 10 9 8 7 6 5 4 3 2 I II 10 9 8 7 6 5 4 3 2 I DEC M-D
1
?
A
0
l6
!; JtIV!; )R
!;
R :\ I.:i~. DECIMAL
CCT
'J
11
2
1t::
7,F.ROIZED
MID DEC CaMPL
r.AT.r.
~IR
1
1
1
nli'r.TMAT,
6
6
17
12
1
1
CT11
CT11
7
2 9 9 9 9 9 7 8
CT11
8
CT11
0
o
q
'A_? 7.w.ROT7.R
1
1
2
CT11
7
!... 10. PR. MID DEG .. COMPL
1
2
CT11
1
2
~~.l~l~~FR~M·~ID~~~~~
__________r-r-+-+-~~~~-+-+~~~r-~r-+-+-~~~-r-+-+
__7~~~~~~=;
.fj
0
0
0
1?
EZ
0
13. MI D DEC COMPL
6
6
14. MID NUM. REG
1
1,
15. SIRDEGIMAL
1116. CONSTANT 17
1
12
17. SHIFT M'D TO llM
1
1
CT11
12
18. 1st SIR TRIAL SUBIT
1
l'J
1
? 9 9 9 q q 7 R
I'!"'"
h
SHIFT M'D TO 1JM
1 Rt; SIR TRIA.L SUB''l'
CU1\!' .'1tt
RING
1
1
12
12
,
.19.
20.
(jUl'ITJ:(.Ul RING
B-2 ZEROIZE
?1
PR M'
Dli'.r. r.OMPT,
1
1
22.
PR MI D NUM. RID.
1
123
EGD
n
?
?
')
1
7
7
n
I'!"'"
I'!'I" ,
1'!"'11
r.Tll
"
A-SECTION
,ej +,ej
,ejx.f}
INPUT
M-SECTION
CALC. DEC.
PROCESS
REF. POINT
II 10 9 8 7 6 5 4 3 2 I II 10 9 8 7
14
~
~
1
'1
~
/I
I:;
t::
7
R
q
In
11
1?
1i
14.
15.
16.
17.
.18.
19.
20.
21.
22.
23.
.~
01 ~ ~J
JI V I!; )R
RJ ~
:oi E
CCT
It::
1t::
DECIMAL
re7.
nrec COMPL
M'DNUM
5 4 3 2 I DEC M-D
16
~ L\ T.~
'7.w''R()T'7.w'n
MIn nw.0. (,!()MPT.
MIn NTTM Rli'.G
alt) nw.0.TMAT.
IN),;' '/\ NT 17
,qHTli''T' MIn '1'0 11M
.c: ''R T'RT AT !=lTTR I T
IN "Rr
'RTNf1.
"R_? '7.w''R()T'7.w'
Pi? MI n DEC. CQMPL o.
Pi? MI n NTTM· RFfl.
MI D
a
COUNTER
6
1
1
1
1
1
1
1
1
1
1
1
n
0
1
1
1
1
1
1
1
6
12
12
h
1'.1
1?
1?
PI
0
CT11
CT11
CT11
CT11
(1'1'1'
(1'1'11
if
1
1
1
1
1
tJ
17
6
1
RID.
SIR DECIMAL
CONSTANT 17
SHIFT M' D TO 11M
SIR TRIAL SUB'T
CONTROL RING
B-2 ZEROIZE
PRo MI D DEC. COMPL.
PRo MI D NOM. RID.
EGD
6
h
£j
17
h
h
h
l?
12
I?
C'I'l1
C'I'll
PI
C'T'l1
C'T'll
1?
CTl1
CTll
PI
SORT OR STOP: - (N +
/J
01'
!J + .0)
Plate 27C
Sort (N + /J or
/J + /J)
A problem of N + /J or /J + /J in Zero Factor as show. on plate 26 may be plugged to
Sort on the Cons·t.ant and Program Plugboard. The control on diode ilFM is shown on
plate 26. The high level from either cathode of/Jlt'M raises the L1 of' ARG and ARZ.
The high input to ARG opens this Gate. The LP of ARZ goes low to the R1 of ARG
to close this Gate •. The RD of ARG taps off low to the RB of ARM to block any
pulses at the RC of ARM.
The completion of the Zero· Factor step is signalled by pulsing EnD. The RP of EnD
goes low to the RC of the Negative Pulse Amplifier ARGl.The RP of ARGl releases
a positive pulse to pin 6 and out pin 9 of ARAl to the RC of ARM and the RC and
LC of ARG. The positive pulse is rejected at the RC of ARM and· ARG but accepted
at the LC of ARG. The LP of ARG releases a negative pulse to the RP of ART,
triggering ART right. ARG and ARM rejecting the positive pulse prevents branching to
a new step, ES1, or zeroizing the present Step Trigger, ESZ.
The LP of ART goes high to the LC of ARM. The LP of ARM releases a negative pulse
to the RC of AGT on plate 28 to initiate the 20 MS Guard Delay used in Function
steps.
The LP of ART also goes high to the L1 of ABAI. TheLD of AHAl taps off high to the
LD of !RA2, LD of !RA3 and RI of AGTZ. The stages vHh the high grids will do the
following:
1. ABAl - The thyratron in AHAl will fire when the Ready Line is
grounded and energize the Sort Pulse Relay which is
shown on plate 55.
2. ARA2 - The thyratron in ARA2 will fire when the Ready Line is
grounded and energj.ze the Trip Pulse Relay which is
shown on plate 54.
3. ARA.3 - The plates of ARA3 go low to the L1 of ·AP3 shown on
plate 30 re·sulting in cutting off the Timer.
4. AGTZ - The RP of AGTZ goes low to the RI of ARG which taps
off low to the RB of ARM. This low level on ARG and
ARM is necessary in case the Trip Signal originated
clears Selectors which might remove the high level
from the L1 of !HZ. For example, opening the Division
Process Call would do this or breaking the Zero Factor
Sort Line itself.
The Computer will not continue to calculate but instead the card will be ejected
and sorted.
Stop (N
+,
or fJ + .f!)
A problem of N + /J or
/J + /J in Zero Factor as shown on plate 26 may" be plugged to
C-117
Stop on the Constant and Program Plugboard. The control on diode £11M is shown on
plate 26. The high level from the LK of £1m raises the LI of ARY. The high level
from the RK of £1m raises the RI of ARZ. The RP of ARZ and LP of ARY are tied
together so either N +£1 or £I + £I results in lowering the RI of ARG. The RD of ARG
taps off low to the RB of ARM.
The completion of the Zero Factor step is signalled by pulsing EGD. The RP of EGD
goes low to the RC of the Negative Pulse Amplifier ARGI. The RP of ARGI releases a
positive pulse to pin 6 and out pin 9 of ARAI to the RC of ARM and RC and LC of ARG.
The positive pulse is rejected at all points due to low grid levels. The rejected
pulse prevents branching to a new step, ESI, or zeroizing the present Step Trigger,
ESZ. The Computer cannot continue calculating so the operator must manually remove
the card.
The Step Switch on the PTP, when operative, will put a high level to the RI of ARY.
The RP of ARY goes low to the RI of ARG which prevents branching and zeroize as
explained above.
C-118
OUTPUT CONTROL: - Chassis #1 & f/!2
Plates 28C, 29C
& 30C
The various special Function Program and Step Triggers are located in Output
Control Chassis - they are in OCLl (a)
APTl through APT4 controlling Select I through Select IV.
(b)
AATl and AAT2 controlling Punch Actuator Set I and II.
(c)
ASTl and AST2 controlling Punch Sort I and II.
(d)
ACT controlling Program Storage Clear.
(e)
AT~
controlling Punch Trip.
and in OCL2 (f)
ART which controls the Zero Factor Reject Operation for
Sort and Trip.
(g)
AGT initiates the guard time for the foregoing stages "b"
through tlftl except tid" when the Punch Ready Signal is present.
The branching into and out of "aft through "e" is exactly like the branching for
the Numerical Steps. One function only of each type is described for the Triggers
themselves.
C-119
Sort I, Set I and Clear Operation
(P~te 28 )
This plate shows the circuitry of three of the Function Steps. Each Function Step
can be branched In from either a Numerical Step or a different Function Step. The
Out branclt ,f!,om.th,ese Function Steps Can go to either a Numerical Step or a
different Function Step. Each Function Step is 20 MS in dur.ation. 'In each step
the Function is separate from the delay and Out Branch of the Step. This leaves the
possibility of branching out of a Function Step without perfol'Jlling th~ Funct,ion.
Sort I
Branching In the Sort I Step 'lowers the LI of the Diode Gate ASG. The ESI pulse to
ASG causes a negative pulse to be released from the,LP of ASG to trigger ASTI right.
The LP of ASTI goes high to the L1 of ASD. The,LP of ApD goes low to pull dow the
Sort I Out Line to condition the branching to the next step. The LD of ASD taps off
high to the LD of thyratron ASAI. This fires the thyratron ASAI resulting in energizing the Sort Pulse Relay in the Punch. The thyratron ASAI cannot fire until the
Ready Line, liam C, is closed.
The LP of ASTI also goes high to the LC of ASM. The LP of ASM releases a negative
pulse to the RC of'AGT, triggering AGT ,right. ,This starts the Guard Delay of the
step which iSi,explained under a separate hea,ding.
,Set I
Branching In the Set I Step lowers the LI of the Diode Gate AAG. The ESI pulse to
AAG causes a negative pulse to be released from the LP of AAG to trigger AATI right.
The LP of AATI goes high to the L1 of AAD. The LP of AAD goes low to pull dow the
Set I Out Line to condition the branching to the next step. The LD of AAD taps off
high to the LD of AAR. The high grid of AAR and the Ready Line, Cam C, being closed,
allows the LP of AAR to go low to the RC of AUI. kicking AUI right. AAFI bas a
10Ms delay. While AAFI is right its LP goes high to the L1 of AAK!. The K-AAKI goes
high to the Set I Common on the Plugboard. The operation of this circuit on the
Storage Bits is shown on plate 10 • After lOMs AAFI returns left and the Set Pulse
is completed.
The LP of AATI also goes high to the LC of AAM. The LP of AAM releases a negative
pulse to the RC of AGT, triggering AGT right. This starts the Guard Delay of the
step which is explained under a separate heading.
Clear
Branching In the Clear Step lowers the LI of the Diode Gate ACG. The low In line also
lowers the LI of ASC. The K-ASC goes low to the Clear Common on the Plugboard. The
additional conditioning of the Storage Circuit is shown on plate 10.
The ESI pulse to ACG causes a negative pulse to be released from the LP of ACG to
trigger ACT right. The RP of ACT goes low to the LC of ACI. The LP of ACI releases
a poQitive pulse to the RC of ACI. (AC1' operates in parallel with the right side of
C-120
ACI). The RP of ACI releases a negative pulse to the LC and RCof all MC Diode Gates.
These Gates were conditioned by the K-ASC.
The LP of ACT goes high to the LI of ACM. The LP of ACM goes low to pull down the
Clear Out Line to condition the branching to the next step. The LP of ACT also goes
high to the RC of ACM. The RP of ACM releases a negative pulse to the RP of AGFI to
start the Guard Delay of the step which is explained under a separate heading.
Guard Delay of Function Steps
A11 Function Steps, Set, Sort, Select, Clear and Trip, use the same Guard Delay.
Those Functions, which directly operate in the Punch, start with AGT for Ready Line
protection.
Assuming AGT is right the LP of AGT goes high to the LI of AGD. AGD has a Ready Line
control on its cathode but wher: the Ready Line is closed AGD conducts. The LP of
AGD goes low to the RC of AGFl, kicking AGFI right. AGFI has a lOMS delay and, on
its return left, the LP of AGFI returns low to the RC of AGF2 kicking AGF2 right.
The LP of AGF2 goes high to the LC of AGTZ. The LP of AGTZ releases a nega tive
pulS'e to the LP of AGT, returning AGT left. AGT is normally returned left by this
method instead of ESZ in order to set up this Trigger for a possible immediate
Function Step following this one.
After lOMS, AGF2 returns left, and the RP of AGF2 goes high to the RC of AGA. The
RP of AGA releases a negative pulse to the RC of ARGI. The plates of ARGI release
a positive pulse to the RC of ARM and LC and RC of ARG. The RI of ARG and RB of ARM
are high except when the PTP Switch is in Step or ~F (N +~ or ~ +~ Stop) is present.
The RP of ARG releases a negative pulse to the RC of ESIA and LC of ESZA creating an
ESZ and ESI Pulse. The RP of ARM releases a negative pulse to the RP of EZto start
the next step. A more detailed explanation of the controls on ARG are shown on
plate 27.
Select Step (Plate 29C)
The purpose of the Select Step is to energize Selector Relays by means of a Select
Thyratron. No control holes are necessary as the Program Branching Control governs
when the Select step is to be used. There are four separate Select Steps, I, II,
III and IV, each performing separate but similar functions, energiz.ing Selector
Relays. The thyratrons are fired in their Select Step but are generally extinguished
by Punch Control. The cathode of each Select Thyratron is returned to ground
through the Select Cam and the energized Manual Clear Relay Contacts or the energized
cSelect Control Relay Contacts in series with the de-energized Trip Pulse Relay Contacts and the energized Manual Clear Relay Contacts.
The Manual Clear Relay is normally energized and only drops out if B+ is removed
or in a Trip Step with the Punch Motor .tur:ned off. A Manual Clear will also deenergize the Manual Clear Relay. At 324 c Punch time the Select Cam closes, then at
75° the Trip Pulse Relay de-energizes and at.135° the Select Control Relay energizes.
At 200 0 the Select Cam opened so a Trip Pulse will break the cathode circuit when
the Trip Pulse Relay energizes. The Select Thyratron can also be extinguished if the
plate is grounded by Control Common or Selector Hold. At this time the Selector
Relays do not drop out and the PTP neon indicator stays fired even though the
C-121
thyratron is technica.lly extinguished.
load (relay) is removed.
The Thyratron can also be extingUished if its
It is ,not necessary to fire the thyratron in order to branch out of a Select Step_
The function of the thyratron is independent from the branching. One Select
Thyra tron can pull in all the Selector Relays if the program requires such an
application. Each Select Thyratron plate has a six hole bus on the plugboard from
which the Selector Relay Pull Up is plugged. An additional bus may be used if more·
than six Selector Relays are to be energized.
Each Selector Relay has its ow. half wave 115 volt DC Power Supply. The half wave
gives high voltage for pull in and lower voltage for holding. The Power Supply for
these relays are in the Selector Power Chassis (SEP). The Select Thyratrons are
located under the meter papel in the Power Control end of the Computer.
Operation
A branch, + or -,into a Select I Step is indicated by lowering the LI of diode APGA.
The ESI pulse to APGA releases a negative pulse at the LP of APGA to trigger APTI
right •. ~he LP of APTI goes high to the LI of APDl and LC of APMA. The LP of APDl
lowers the Select I branch Out Line. The LP of APMA releases a negative pulse to
AGFI to give the 20 millisecond Guard Delay of the step as shown on plate 28.
The RP of APT1 goes low to the RI of APDl. The RP of APDl goes high to the grid of
the Select I Thyratron causing this thyratron to fire. Any Selector Relays whose
Pull Up is plugged will be energi'Zed. The indicator neon on the PTP will fire and
remain fired until the thyratron is extinguished.
The. Manual Clear will Zeroize the Select Step Triggers. This is necessary to prevent
leaving a Select Thyratron fired if the Computer hangs up in a Select Step and it is
desired to Clear and Restart the problem.
Trip (Plate 30C)
Trigger ATT is pulled right through ACG when branching i
ATT raises the
left grid of ATMI to fire the Thyratron and operate th Trip Pulse Relay in the.
ch w
Read Line and cathode oto grounq~' he left uivider of ATMI also
raises the grids of A w c
es the epro nce Power Relay in a Reproduce
Operation. The high from the LP of ATT to the RCof ATM2 causes the RP of ATM2 to
release a negative pulse to AGT to start the Guard Delay for this step as show. on
Plate 28 • The plates of ATA also 'Operate AP3 to pulse the master control on the
Timer left since the Trip Signal indicates the end of the'problem. The, input from
the plates of ATA into APCl is for certain test conditions. Whenever a Trip Signal
is received; the left grid of APCl is cut off. The right grid of APCl is controlled
by the Punch Motor Switch. When the Motor Switch is Qn, a+70R Supply is available
to the right grid so APCl relliains conducting during a Trip. When the Motor Switch is
Off i the right side of APCl does not conduct; therefore, when a...~Trip Pulse occurs,
APCl is cut off on both sides causing the Manual Clear Relay to de-energize. This
relay dropping out will Zeroize all 12 Storages, break :?e~ector Hold and the Control
Common. The same result, APClcut off, can be accomplished manuaTly. When the
Clear Switch on the PTP or Unit and Clear Switch on the Punch is operated, the
Cathode Circuit of APCl is broken and the tube stops conducting.
C-122
When the Trip Pulse is received with the Motor Switch Off and the Timer Cut-off
blocked, a Test Problem can be run in the Calculator which will be completely
cleared every time a Trip Pulse occurs. All Selector Relays will drop out ~nd all
Storages will be cleared. Since the Timer Cut-off is blocked, problem repeat being
plugged will cause calculation to start from the beginning. ATT may be operated
directly from the Punch Non-Calculate Cam Switch through the filter of ATR for the
purpose of tr'-pping the first card fed through the sensing cycle for that card.
C-123
. SELECTOR RELAY CONTRoL
. Plate 31C
. ).
This circuit shows the varioUs coritrolsava:1lable :t'optlll·inor hold in Selector
Relays "and ·tne Se'J.:ect Thyratrons. TheO'6nim.on Buss·es are located on the Field
Plugboard and the Selector Hold Bus is located on the Program Plugboard. The
Manual Clear Relay is located in the Power Control end of the Computer. The
Select Cam, Select Control and Trip Pulse Relays are located in the Punch.
Control Common
The Control Common and Select Thyratron cathodes are returned to ground through the .
energized Manual Clear Relay contacts and either the Select Cam or the energized
Select Control Relay contacts in series with the de-energized Trip Pulse Relay
contacts.
The Control. Common is normally broken when the Trip Pulse Relay is energized. This
gives the Selector Relays the maximum drop out time before the sensing switches break.
When a card is manually released, Card Release Operation, the Trip Pulse Relay is
not energized. The Select Control Relay, being cam controlled, will therefore break
the Control Common before the sensing switches break •
. Selector Hold
The Selector Hold Bus is returned to ground through the energized Manual Clear Relay
contacts. The Manual Clear Relay remains energized from card to card so therefore
the Selector Hold is a constant ground. Use of the Selector Hold Bus enables a
Selector Relay to be held in from card to card.
Delayed Control Common
The Delayed Control Common is returned to ground during the short interval after the
Trip Pulse Relay energizes until the Select Control Relay de-energizes. The purpose
of this line is to delay using the Control Hole in a card until that card has been
completely calculated (Trip Pulse). A Selector Relay which is energized by the
Delayed Control Common will not remain energized until the following card is sensed
unless Selector Hold is used.
.-'.
C-124
TEST COUNTER
Plate 32C
The Test Counter is controlled in its operation from the Test Counter Panel which is
located in the center rear of the Computer. The purpose of the Counter and Panel is
to assist in servicing the Computer. By use of the Counter and Panel it is possible
to stop the Computer calculation after a predetermined quantity of shifts, carries
or RIGS. The operation of the Off-On switch enables the Counter to be effective.
The Panel can be set to stop the Computer in any calculating step by use of the Step
switches.
Input
The source of input to the Test Counter is controlled by the setting on the Panel
Stop Switch.
Post or Pre RIG - RIGl' in the RIG (plate 5).
Pre SIG - SK2 in the Decimal Counter (plate 4).
Pre eIG - CSK in the Carry Input Generator (plate 3).
Output
The destination of output from the Test Counter is controlled by the setting on the
Panel Stop Switch.
Post RIG - CX in Carry Input Generator (plate 3).
~F2 in Zero Factor (plate 26 ).
Pre RIG - RB in Sign Bias (plate 43 ).
PMDR in Multiplication and Division (plate 23 and 25 ).
Pre SIG - SMG in the Decimal Counter (plate 4).
Pre CIG - SCKl' in Carry Input Generator (plate 3).
The Test Counter has a capacity of 400. At a count of 400 all Count Triggers are
left. Trigger TB is right raising the cathode of TK through the Off-On switch. The
Counter, therefore, becomes effective when its count becomes 400.
There are three Count Set switches on the Test Counter Panel,. Units, Tens and
Hundreds. The Count Set switches are set toa value which represents the number of
pulses permitted before the Test Counter becomes effective. For Example: The
Computer is to be stopped before the 21st shift pulse is released. The Stop switch
is set to Pre SIG. The Count Set switch has a zero Unit setting and a two tens
setting. The TCR is set at Pre SIG 20. This setting indicates that 20 shift pulses
may occur prior to the TCR reaching 400. .
The value set in the Count Set switches is placed into the Counter as the complement
of 399. If the value in the switches is 20, the Counter value would be 399-20 or
379. This complement value is placed into the C~unter by the B-5 Zeroize. The letters
under the Counter Triggers refer to connections made to the Panel for use with the
B-5 Zeroize. This Zeroize is effective on the Counter whether the Off-On switch is
effective or not. Even though the Counter has a capacity of 400 the Complement of
399 is placed in the counter. The operation of DEA, Decimal Registration, adds one
C-125
more to the Counter bringing its value to the complement o£ 400. This is necessary
in case the Count Set is set at zero. If the complement of 400 were used the complement of zero is 400 which to the Counter would be zero. Using 399 instead, enables
the Counter to go to 400 by DEA which then makes the Counter 400 before any Stop
switch pulses can occur.
The Test Counter Triggers have the following values.
Digit
4
2
'2
1
1
1
2
'2
3
'2
4
2
'2
5
2
'2
6
4
'2
7
4
'2
8
4
2
'2
9
4
2
'2
1
1
1
1
0
Over carry occurs from Units to Tens and from Tens to Hundreds.
The Test Counter is only ef£ective in the step set on the Step switches. When the
selected step is reached the LP of this selected Step Trigger goes high to the LB of
TSA. The LP of TSA goes low to the RI of TG, a Cathode Follower on the right side.
This lowers the cathode of Gate TG. When DEA returns left its LP goes low to the RC
of TS, triggering TS right. The LP of TS goes high to the LI of TG, opening the Gate.
The LP of TS also goes high to the RC of TSA. The RP of TSA releases a negative pulse
to the RC and LC of Tl to increase the count in the Test Counter by one. This brings
the count in the Counter to the complement of 400.
Gate TG being open allows the selected pulses from the Stop switch to be accumulated
in the Counter.
The SD position on the TCR Panel is connected to the LP of TSP. When the Computer is
in the step selected by the Step switch the LP of TSP goes low to the SD jack. This
SD jack can be plugged into the oscilloscope using the (-) input. This is the same as
triggeripg from a Step Trigger. The TCR input on the Sweep Delay is not required.
C-126
VOLTAGE ABNORMALITY DETECTOR
Plate 33C
The purpose of the VAD .Chassis is to provide:
(1)
a visual indication on the Operator's Panel which will
persist until manually reset
(2)
and stop the operation of the Punch
whenever the power line voltage variations cause the D.C. Supply voltages to exceed
a predetermined safe operating range. The circuit has been made failsafe by
arranging it so that an indication is provided not only when the supply voltages
exceed a safe operating range, but also in the case of a D. C. supply voltage
failure or an open interlock switch.
The circuit contains a Detector, Mixer, Inverter and an Output stage. The Detector
consists of two self-extinguishing Thyratron Circuits, THY1 and THY2. The Control
Grid Resistor of each Thyratron is returned to individually adjustable reference
voltages. By adjusting these reference voltages, an output indication can be
provided at any desirable plus or minus supply voltage variation. The power supply
voltage -150, which is monitored, is applied to the oathode of Thyratron, THI1, and
to the control grid of Thyratron, THY 2, so that any variation in the power supply
voltage appears directly in both of the Thyratron grid-to-cathode circuits but of
opposite polarity. If the magnitude of the supply voltage should increase, the
grid-to-cathode voltage of Thyratron, THY1, will become more positive while the gridto~cathode voltage of Thyratron, THY2, will become more negative.
Should the magnitude of the supply voltage increa.se beyond the safe operating limit (150 + 8%)
Thyratron, THI1, will fire. If the magnitude of the supply voltage should decrease,
the grid-to-cathode voltage of Thyratron, THY 2, will become more positive while the
grid-to-cathode voltage of Thyratron, THYl, will become more negative. Should the
magnitude of the supply voltage decrease beyond the safe operating limit (150 - 8%),
Thyratron, THY2, will fire.
Operation
The plates of the Thyratrons are direct coupled to the grids of a Mixer stage, MIR.
Both triodes of the Mixer stage are normally conducting. When a Thyratron fires,
one of the triodes of the MIR stage will become cut-off. This will cause the
Inverter stage, INV, which is normally non-conducting to go into conduotion. The
Inverter plates now being low, cut-off the normally conducting Output stage, OTP,
and the relay in the plate circuit of OTP becomes de-energi.zed and its contacts
provide the necessary output. The relay is then locked-out by one of its own contacts so that it cannot be energized again until the Clear Punch Switch, located on
the Operator's Panel in the Punch Unit, or Service Switch under the TCR Panel, is
closed.
When the Power supply voltages exceed the safe operating limits, one of the Thyratrons will fire and then extinguish itself, the red Voltage Indicator Light on the
Operator's Panel will go On and the Punch Operation will stop. The mac.hine will
remain in this condition until the operator manually resets the VAD with the Clear
C-127
Punch Switch. If the operator tries to reset the VAD while the line voltage is still
beyond the safe operating limit, the red Voltage Indicator Light will go out while the
Clear Punch Switch is closed, but it will immediately come back on wh~n the switch is
released indicating an abnormal voltage condition. If the line voltage had come back
within the safe operating range and then the operator tries to reset the VAD, the red
Voltage Indicator Light will go out when the Clear Punch Switch is closed and it will
stay out when it is released indicating that the machine is now ready for normal use.
The relays affected by the +150 volt supply to the punch are:
K2
IV
IW
18
I~
17
1211
B+ Failure
Select Control
Calc. In Progress
Secondary Reproduce
Trip Pulse
Sort Pulse
Reproduce Power
C-128
AUTOMATIC CIRCUIT TIMER
Plate 34C
The Automatic Circuit Timer is a device to start the Computer over again in case an
incorrect result or a transient pulse prevents the Computer from reaching the Trip
or end of computation step. The Restart Signal is pre-controlled by the Programmer
from the Plugboard. When plugged to Restart Step only the step in which the stoppage
occurred is restarted. If plugged to Restart Problem the Automatic Timer has the
same effect as the initial calculator Start Signal.
Circuit
The Restart Circuit is contained in the SCL Chassis, and operates as follows:
Trigger EP3 is the master control which is kicked right by EP thru ESBI to unlock
the Timer on a calculator Start Signal. EP3 going right cuts off the right side of
EPX. The left side of EPX is normally cut off, therefore the plate starts to rise,
delayed by a large capacitor and high resistance plate load. If allowed to continue
the plate voltage would rise far enough to fire two neons and apply a positive pulse
to the two ltC't inputs of EP5, however, EP4 is operated by EZ at the start of every
step to recharge the capacitor in the plate circuit of EPX and prevent the neons
from firing. The time for the plates of EPX to rise to the neon firing potential is
approximately 300 milliseconds or roughly three times the duration of the longest
problem. If a step is not completed within this time the pulse at .the inputs of
EP5 is passed thru the side which is held open by Plugboard Program which connects
the bias input to ground. The left side of EP5 kicks EP to restart the problem and
the right side of EP5 kicksEZ to restart the step. The Trip Signal through AlMl
or ATM2 in OCL returns EP3 to lock the Timer during the intervals between problem
calculations.
In restarting a step, the left grid of EP4' is in parallel to the right grid of EP5
. and therefore passes the same pulses as EP5 in order to return MC2 and tlRS in tlF
should either be on the right. EP3 is also returned by the right .side of EP4' when
the Program Test Panel switches are in use. EP3C is a diode and RC circuit to
insure that the Master Timer Trigger EP3 is on the left when the Computer D. Co
voltages come on during the turn on period. The Minus Voltages coming on first
apply a clamping voltage to the right grid of EP3 and then when the Plus Voltages
follow, the cathodes of the diodes EP3C rise slowly above the plates and the diodes
cease to conduct.
C-129
PROGRAM'TEST PANEL
Plate 35C
In addition to serving to indicate the various digits in the Accumulator, elements
called (Keyboard Biases), etc., the Program Test Panel provides the means to advance
to any step of the program and to call VI, V2 or the Result as desired with its
identity (Nl---N36 dr Sl---S12Jdecimal and such indicated. Briefly the sequence
of operation of the switch is:
Step, Clear, Start, then to Dial, if other than the first step is
desired, or to Read. Then VI, V2 or R may be depressed in any
order and more than once if desir~d.
The functions of the switches and associated circuitry are described.
Program Test Panel Operation
The Automatic Circuit Timer is made inoperative by returning
its Master Control Trigger EP3 whenever Switch #1 is placed in
either the Step or Read positions. The opening of C2 or C3
Contacts allows the.right grid of EP4' to go from -90 Volts
to ground and the right plate of EP4', in turn, clamps EP3 left.
The Step Zeroize and Advance Pulses ESZ and ESI are blocked by
the right grid of ARI being raised to ground through Cl which,
in turn, closes the right gate of ARG. Therefore, if a step
is started, it can go to -completion but no branching will take
place. The Step Trigger for the step just completed will
remain on the right.
Clear
C2 clears all the Storages and Select Circuits including the
Program Board Hold Common by de-energizing the Manual Clear
Relay. This Clear Operation may be performed regardless of
the position of Switch #1.
Start
CI calls for a normal Start Signal by grounding the Start Line.
Contacts C2 allow EGD to operate the Program Test Check Trigger PTI.
An incorrect result will fail to operate PTI and prevent advancing
from the step in which the error occured.
When Switch #1 is in the normal position, the Check Trigger has
no function although the Check Indicator will light if switch
#3 is held up. The Start Function is independent of Switch #1
and may be operated for trouble shooting with the Test Counter
Panel.
C-130
Dial
When Switch #1 is in the Step position, the Dial is operated to
give the desired number of steps to be advanced. The A Contacts
on the Dial are closed while the Dial is operating to open the
right Gate of PT2 which ~llows the Program Test Check Trigger
PT1 to be operated. Dialing a 1 opens the Interrupter Contacts
once allowing PT4 to go to the left. The .022 mfd. Capacitor,
in ES13, prevents contact bounce in the Dial Interrupter Contacts
from operating PT4 more than once per interruption.
The LA point of PT4 pulses the right grid of ARY below cut-off
which" in turn, opens the right Gate of ARG. The left plate on
the same negative pulse, operates PT3 which allows the Gate of
ARG time to open. The return of PT3 to the left operates EGD through
the left side of Gate PT2, which is held open on a correct result by
PTl. EGD, in turn, initiate.s an ESI and ESZ pulse which returns the
present Step Trigger and operates the next step in the branch.
The interval between pulses from the Dial is 200 miI1l-seconds
which is longer than any step; therefore, the Computer can finish one
step before an Advance Pulse is received to go to the next step_
Read
Contacts C3 (a & b) open to hold the Automatic Restart Control
Trigger EP3 off the same as the Step position does.
The call for Storage is blocked to prevent clearing of the Result
during the reading operation because Contacts C3 (c &d) allow the
cathode of ERIC to go to ground during Zeroize Guard Time, EZ,
without calling the Result through the ERK bus.
C4 raises the cathode of CX through a 5K Resistor to block the
Computer immediately after the RIG cycle called for to read V1,
V2 or R. No carries are allowed if a Negative Factor is read on
an Addition or Subtraction step; therefore, each negative digit
will be the complement of 10 instead of 9.
V1
C3 closes to start the step by klcking EZ. MC2 is also returned
to the left, if it should be on the right, in order that V1" V2
or the Result can be read wtth its proper sign on Addition or
Subtraction.
V1 is registered into the Accumulator in the normal manner and
left there since further operation of the step is blocked by Switch #1.
C4 (d & e) open to prevent calling VI through the EMK Bus. The ESK
Bus is transferred by C4 Ca, b, & c) to the cathode of EMK" therefore,
V2 is substituted in place of Vl and is registered into the Accumulator
C-131
when EZ is operated by C3 (a & b) which close after C4
contacts have completed their transfer operation.
R
The Result Bus ERK which is disconnected from the cathode of
ERK by the Read Switch is connected to the cathode of EMK by
C4 (a &b) and then contacts C3 (a & b) close to register the
Result into the Accumulator.
NOTE:
When V1, V2 or :a is depressed in an Addition
or Subtraction Process, a minus value will be
subtracted, resulting in its 10's complement
being read on the PTP.
C-132
B2-B5 ZEROIZE
Plate 36C
Maintaining B5 at -90
The plate level of VTB5 governs the grid level on the right side of ZR5. This grid
will control the cathode level. A rise or fall of this grid level will therefore
affect the cathode level similarly. Since the left grid is maintained at -90 any
change on the cathode will affect the left plate. The voltage level change on the
left plate will be fed back to the control grid of VTB5 to adjust its conduction to
bring its plate level back to -90.
B-5 Zeroize
When EZB5 goes right its LP, through the 220 uuf capacitor, will hold the grid of
ZD52 high for approximately 60 us. The RP of EZB5, going low, ' will then cutoff
ZD52 causing its plate to go high. Through the 1000 uuf capacitor, the grid of
ZB52 is raised and the tube conducts. ZB52 -conducting will disable ZR5 and also
lower the control grid of VTB5 enough to cutoff this tube. This allows the plate
of VTB5 to go to approximately ground potential and give the Zeroize effect.
Trigger Zeroize
B2 - Acc. (lA-llA incl.), M-D chassis, OCT except CTll
B5 - All other Triggers except those listed below
ESZ - Step Trig~ers, Function Triggers &AGT.
ESI - MC2, ~RS (also by step repeat)
EBS is Zeroized when ER goes ri~ht
EP3 - Trip Pulse, Clear Switch {Punch and PTP), Step & Read Switch (PTP)
C-133
!{B RECOVERY AND DECIMAL CONTROL
Plate 37C
In the Computer, a means is provided in order to read the Numerical Value, Decimal
Value and sign of the Numerical Value. A reading voltage is employed for thi.s
purpose and is called KB, Keyboard Bias.
There are 36 Elements in a full capacity Univac 120. Each Element may represent a
Constant or a Card Field. Each Element has its own Decimal Location. It is not
possible to use all the Elements at once so each must have its own reading voltage
which can be called upon when required. This reading voltage is called KB.
There are 12 Storages in a Univac 120. Each Storage has its own associated circuitry
which is referred to as KB but the voltage levels and the circuitry are not the same
as that gmployed by Elements. When a specific Storage i.s called for the reference
is made that the Storage KB is raised.
This plat~ gives an example of how KB is raised and shows the KB Recovery Operation.
KB Recdvery Operation is, as the name implies, used to lower a KB more rapidly than
if it recovered from its own circuitry.
Operation
In the center of the plate are three circles labeled VI, V2 and R. VI represents
the first factor, Minidend (EM), V2 the second factor, Subvisor (ES), and R the
Result, Storage (ER). As the various control circuits are encountered at various
times Vl., V2 or R will be pulled low. On this plate when VI is pulled low the LI
of KBA is lowered causing the LP of KBA to go high. Since VI was plugged on the
Program Board to Nl the KBA stage that is cutoff represents Element Nl. The high
level from the LP of KBA raises the grids and cathode of KB (1). This high level
from the K-KB (1) is called Keyboard Bias. The high level from K~B (1) goes to
the following.
1.
Plate of a diode located above the Plugboard Mechanism. The
cathode of the diode is raised and is connected to the Nl
Decimal Locator on the Plugboard. Here the Nl position is
plu~ged to any of the 11 decimal positions.
This plate uses
a 2/1 decimal for Nl. This 2/1 decimal is permanently connected
to a group of neons, as shown, which are located on a panel
located behind the DCL chassis. The KB level fires the neons
which in turn condition the Decimal Counter Gates as shown on
plate 4. There is one group of neons for each decimal
posi tion 11/10 to 1/0. Each Element uses one half of a
diode. This diode prevents backfeed in the event two Elements
use the same decimal.
2.
The Plugboard position, marked Element Designators, at the Nl
position. This high level at this point on the Plugboard is
available to be wired to a Card Field or a Constant selection.
If a Card Field is chosen the KB level is carried to the
Punch Plugboard by means of a Transfer Line. If a Constant is
chosen the KB level is plugged to one of the constant, C, hubs.
If the value of the Element is to be negative then the HI
C-134
position must also be plugged to the Minus position which
is located next to the Nl hub.
At the top right of the plate is stage ~FD1. This stage functions whenever a Control
Ring Pulse occurs and when Eg goes left. In a normal step these times would be when
the following stages return left:
Eg, EM, ES, ER, EPM, EPS and EPP. ~FDl remains
right for 25 us ana during tnis interval the KB Recovery Circuit is in operation. The
LP of ~FDl goes high to ~LDl & ,0LD2. The high level from the K of ~LDl and K~LD2
raises the plates of all KBR and FD diodes. These diodes, in turn, raise their
cathodes and any cathode that had been low, KB call, will be returned high. Any
cathode going low will be held up until .0FDl returns left. This insures a rapid return
of the KB level so that the next rising KB level will not be able to temporarily keep
two KB levels high at the same time. This will reduce the possibility of wrong Decimal
Registration and false Double Input Operation.
Each of the 40 Program Steps has its own associated Vl and V2 and R as shown on
plate 38. Vl and V2 can be plugged to any Element or Storage. The same Element or
Storage can be used twice in one step or in any other step. The R position can only
be plugged to a Storage. That storage cannot be used as a Vl or V2 in that same step.
The KB level is normally a low level and is raised only when that KB is called for.
The call is controlled by one of the various Control. Triggers.
C-135
PLUGBOARD CONTROL
Plate 38C
The Plugboard Control Plate shows the various connections required in order to
perform the fUnctions necessary in a calculating step.
The basic control is the Step Trigger, such as 2ES.
associated group of Amplifiers.
l.
ESF Subvisor Control (V2)
2~
D1F
3.
ERF Result Control
Minidend Control (VI)
4. EPF Process.Control
5.
This Trigger conditions an
(R)
(PROC)
EBP Plus Branch Control
6 • EBM Minus Branch Control
The Amplifiers enable the Computer to perform any of the four mathematical processes,
handling each factor, V, V2and R, independently.
Step Control
There are 40 calculating steps in the Computer, each step being controlled by a
Step Trigger. Each Step Trigger, through its associated Amplifier controls the
Process, VI, V2, and R and Out branch hubs of that particular step. The VI
(Minidend), V2 (Subvisor), and R (Result) cannot all be used simultaneously so
each Amplifier controlling these hubs has a cathode control so that their values
can be called upon at specific times during a calculating step. This means that
only one of the three values, VI' V2 or R, can be read at a time. This is the
source of control as to which KB is to be raised. The plugging of the plugboard
hubs are on plate 37.
Branching Control
Each Step Trigger is kicked from one side of a Diode Gate. There is one side of a
Diode Gate for each Step Trigger. The Diode Gate is conditioned from the In hub
of the Plugboard _ There is an In hub for each Diode Gate. The Diode Gates are
pulsed by the ESI, Step Advance Pulse, at the beginning of each step_ At the same
time the ESg, Step Zeroize Pulse, is released to return the previous Step Trigger
left.
The In hub is plugged from the (+) or (-) Out hub of another step_ The Out hubs
are controlled by the EBP and EBM Amplifiers. The sign of the Result of a step is
indicated by the position of Trigger EBS. If the Result is positive or zero, EBB
is conducting on the left, and, through the Cathode Follower EBP, lowers all EBP
Amplifier cathodes. The Amplifier with a high grid conducts and lowers its
C-136
respective (+) Out hub. If the Result of the step is negative the low into the LI
of MC? and high from the LP of MC? opens LI of Gate EBG. Trigger ER going right
Zeroized EBS, if EBS was right. During ER time MS goes right and the LP of MS reads
Gate EBG. A Minus Result finds the Gate open so the LP of EBG releasing a negative
pulse pulls EBS right. The EBP cathode is raised and the EBM cathode is lowered.
This causes the (-) Out bub to be pulled low for Minus Branching.
C-137
CONTROL RING
Plate 39C
This circuit shows the various means the Control Triggers in a calculation step are
operated. Only one Control Trigger can be right at any specific time. Each time a
Control Trigger is returned left the KB Recovery Circuit functions as shown on
plate 37. The following is a general sequence of operation.
1. EZ 450 us delay to allow B2, B5 and Storage Zeroize. Timer is reset.
2. EM Minidend Operation
A.
B.
3.
M'd Decimal Complement Registration
M'd Numerical Registration
ES Subvisor Operation
A. Sir Decimal Registration
B. Shifts
C. SIr Decimal Complement Registration
D. SIr Numerical Registration
4. ER Result Operation
A. Result Decimal Registration
B. Shifts
C. Test RIG
D. Result set in Storage
5. EDpg 14 us delay for Storage Set Recovery
6. EPg 450 us delay to obtain a B2 Zeroize
7. EPM Proof Minidend (Storage) Operation
A. Storage Decimal Complement Registration
B. Storage Numerical Registration
8.
EPS Proof Subvisor (Subvisor) Operation
A.
B.
C.
D.
9.
EPP
S'r Decimal Registration
Shifts
S'r Decimal Complement Registration
Sir Numerical Registration
Minidend Subtraction Operation
Mid Decimal Registration
Shifts
C. M'd Numerical Registration
A.
B.
10.
C~D
100 us delay to allow
~
Check lines to normalize
Each of the above Control Triggers operations are shown on other plates in detail.
C-138
PROCESS CONTROL
Plate 40C
This circuit is employed by all four of the Processes, +, -, x and +. The circuit
is only employed during ES and EPS Control Circuit Time. The circuit has two basic
functions:
1.
During ES time pre-condition SB and gating control for the
Process plugged.
2.
During EPS time pre-condition SB and gating for the reverse
of the Process plugged.
Operation
Addition Process
The + Process line controlled from EPF through the Plugboard wire lowers the Ll of
EIA. This cuts off the LP of EIA during the entire step but the plate level cannot
rise until the LP of EP1 also is cutoff. The LP of EP1 is cutoff whenES is right,
plate 14. The RP of ES goes low to the Ll of EP2. The grids of EPI and EP2 are all
tied together so both stages are cutoff. All plates of EP1 and EP2, except the LP
of EP1, are connected to plates of tubes which are conducting so no appreciable
change can oC'cur on their plates. The LP of EP1 can go high in conjunction with the
LPof EIA to raise the plates of diode EIA2. The left cathode of EIA2 raises the Ll
of Gate DPG2 to hold this Gate open during all of ES time. The right cathode of
EIA2 raises the Ll of PSA so that when DRB goes right during ES time the Add Bias
will be raised. SB' is not raised when ES goes right, but merely.prepared for future
use in ES time.
During EPS time the RP of EPS goes low to the Ll of EPP2. The grids of EPP2 and
EPP1 are tied together so that both stages are cutoff. Only the RP of EPPI, which
is connected to the RP of EIA, it:! free to go high. The high from the RP of EIA
and EPP1 raises the plates of diode ElSI. The left cathode of EIS1 raises ~he L1
of Gate DPG2 to hold this Gate open during all of EPS time. The right cathode of
ElS1 raises the RI of PSA so that when DRB goes right during EPS time the Subtract
Bias (proof process) will be raised. SB is not raised when EPS goes right but
merely prepared for future use in EPS time.
Subtraction Process
The ~ Process line controlled from EPF through the Plugboard wire lowers the Ll of
ElS. This cuts off the LP of EIS during the entire step but the plate level cannot
rise until theRP of EP1 also is cutoff. The RP of EPI is cutoff when ES is right,
plate 14. The RP of ES goes low to the L1 of EP2. The grids of EPI and EP2 are
all, tied together so both stages are cutoff. All plates of EPI and EP2, except the
RP of EPl, are connected to plates of tubes which are conducting so no appreciable
change can occur on their plates. The RP of EPI can go high in conjunction with the
LP of E1S to raise the plates of diode E1S2. The left cathode of E1S2 raises the L1
of Gate DPG2 to hold this Gate open during all of ES time. The right cathode of
C-139
E1S2 raises the R1 of PSA so that when DRB goes right during ES time the Subtract
Bias will be raised. SB is not raised when ES goes right but merely prepared for
future use in ES time.
During EPS time the RP of EPS goes low to the L1 of EPP2. The grids of EPPl and EPP2
are tied together so that both stages are cutoff. Only the LP of EPP1, which is
connected to the RP of E1S, is free to go high. The high from the RP of E1S and LP
of EPPl raises the plates of diode EIA1. The left cathode of EIAl raises the 11 of
DPG2 to hold this Gate open during all of EPS t'ime. The right cathode of EIAl raises
the L1 of PSA so that when DRB goes right during EPS time the Add Bias (proof process)
will be raised. SB is not raised when EPS goes right but merely prepared for future
use in EPS time.
Multiplication Process
The x Process line controlled from EPF through the Plugboard wire lowers the L1 of
EIM. This cuts off the LP of EIM during the entire step but the plate level cannot
rise until the LP of EP2 also is cutoff. The LP of EP2 is cutoff whenES is right,
plate 22. The RPof ES goes low to the LI of EP2. The grids of EPl and EP2 are tied
together so both stages are cutoff. All plates of EPl and EP2, except the LP of EP2,
are connected to plates of tubes which are conducting so no appreciable change can
occur on their plates. The LP of EP2 can go high in conjunction with the LP of EIM to
raise the RP of diode EIM1,! The right cathode of EIMl raises the RI of IMD and from
the RD of DMD raises the LD of PMP to prepare for Multiplication Process as shown o~
plate 23.
During EPS time the ,RP of EPS goes low to the LI of EPP2. The
are tied together so that both stages are cutoff. Only the RP
connected to the RP of EIM,is free to go high. The high from
raises the RP of diode EID1. The right cathode of E1Dl raises
prepare for Division Process as shown on plate 25.
grids of EPP2 and EPPl
of EPP2, which is
the RP of EIM and EPP2
the L1 of PDP to
Division Process
The + Process line controlled from EPF through the Plugboard wire lowers the L1 of EID.
This cuts off the LP of EID during the entire step but the plate level cannot rise
until the RP of EP2 also is cutoff. The RP of EP2 is cutoff when ES is right, plate 24.
The RP of ES goes low to the LI of EP2. The grids of EPl and EP2 are tied together so
both stages are cutoff. All plates of EPl and EP2, except the RP of EP2, are connected
to plates of tubes which are conducting so no appreciable change can occur on their
plates. The RP of' EP2 can go high in conjunction with the LP of E1D to raise the RP
of diode EID2. The right cathode of E1D2 raises the L1 of PDP to prepare for Division
Process as shown on plate 25.
During EPS time the RP of EPS goes low to the LI of EPP2. The grids of EPP2 and EPPI
are tied together so that both stages are cutoff. Only the LP of EPP2, which is
connected to the RP of EID, is free to go high. The high from thg RP of E1D and LP
of EPP2 raises RP of diode EIM2. The right cathode of EIM2 raises the RI of DMD and
from theRD of IMD raises the LD of PMP to prepare for Multiplication Process as
sho'WIl on plate 23.
C-140
CONDITIONING CCT FOR SHIFTS
Plate 41 C
The Check Counter (CCT) receives its count from Shift Pulses but only under limited
conditions. The Counter is opened to count Shift Pulses under the following
conditions:
1.
2.
3.
ES time for Complementize indication.
EPF time in Multiplication or Division only.
Zero Check time to bring the CCT Count to 10.
The Counter counts shifts during ES when the M'd and S'r are being aligned, and it
indicates whether or not the Mid is shifted 11 times or more.
The reason for the count of 11 can be explained by inspection of possible cases
that can occur. The farthest place to the left in the Accumulator that a number
may be entered is lOA. For the first- 11 shifts it is impossible for any number to
arrive in lIM. Therefore, carry indications would be true indications coming from
11M up till this time. However, if the Mid is shifted 11 times or more to align,
then there can not possibly be a number in Ill, and there is a possibility of a
number in lIM that would not give an over carry indication should there be one due
to a negative number. Therefore, the indication is taken from Ill. The most
shifts that can occur to align is 22, making it impossible for the first digit of
the M'd to get into llA again. Thus the indication can be taken from III after 11
shifts. Actually because of the decimal input positions the count is never 11, but
may be more or less than 11.
CTll is Zeroized by B5 so that the rest of the counter may be Zeroized by B2 to be
used in the Zero Check Operations and still retain the 'over 11 shiftsl indication
for use in the rest of the problem.
The CCT counts shifts during EPP in Multiplication or Division to record the
number of shifts required to align the proof result with the M'd. During Zero
Check additional shifts can be generated to bring the times the Proof Result was
shifted to a total of 10. This will insure checking 10 Proof Result digits for
zero.
The CCT counts shifts during Zero Check in any Process when the count in the CCT at
this time is less than 10. In Addition or Subtraction the CCT count will always
be zero so a total of 10 shifts are required to reach a count of 10 in the CCT.
This extra 10 shifts allows a total of 20 digits to be Zero Checked. In Multiplication or Division there generally is some count, from EPP time, in the CCT. If
this count is less than 10, shifts will occur to reach a count of 10.
Operation
ES Time. ES
ESA taps off
LP of CGA is
so its RP is
CCM cutoff).
is on the right so the LP of ES is high to
high to the RD of EMZ. The RP of EMZ goes
tied to the RP of CCM and the RP of CCM is
high to the RDof DCK2. The RP of DCK2 is
C-141
the LI of ESA. The LD of
low to the LI of CGA. The
also cutoff. (CTll is left
low to the RI of CCM holding
The high from the RP of CCM and 1P-of CGA raises the 11 of CTSG to open this Gate to
shifts during ES. The Count Triggers in the CCT indicate count as their stage names
state. At a count of 10, CTlO, CT8 and CT2 are right. At a count of 11, CTll, CTlO,
CT8, CT2 and CTI are right. If the number of shifts exceeds 16 the CCT is closed to
any shifts after 16. At a count of 16 only CTll is right. The RP of CTll is low to
the RD of DCK2. DCK2 is cutoff so its plates are high to the RI of CCM causing the
RP of CCM to go low and close CTSG to any further shifts. The purpose of counting
shifts during ES is strictly to see i f the shifts required are more or less than 11.
EPP Time in Multiplication or Division Process. EPP is on the right so the RP of EPP
is low to the RI of ECBl. The RD of ECBl taps off low to the 1D of EMZ', cutting off
the 1P of EMZI. The 1P of EMZt is tied to the RP of CPMD which is also cutoff. (The
Process of Multiplication or Division lowers the plates of the diode PIMD). The low
from PIMD lowers the 11 of PPI and taps off the 1D of PPI to the RD of CPMD. The RP
of CPMD is cutoff. The high from the RP of CPMD and 1P of EMZ' raises the 11 of CPMD.
The 1P of CPMD goes low to the 11 of CGA, cutting off the 1P of CGA. At this time,
CTIO and CTll are both left so DCK2 has a low plate to the RI of CCM, cutting off the
RP of CCM. The RP of CCM and LP of CGA go high to the 11 of CTSG opening this Gate
to shifts during EPP.
Zero Check. If the count in the CCT is less than 10, CT10 left, Trigger C¢CS (Plate 19)
will go right and lower the RI of C~DD. The RP of C¢DD goes high to the RI of CTSG
to open the CCT to count shifts. When CT10 goes right, Trigger C~CS will be returned
left to again close the CCT to shifts.
C-142
SIGN BIAS
Plate 42C
This plate is a schematic representation of the circuit shown on plate 43. The
explanation of this circuit is written up under Sign Bias - Addition and Subtraction.
SIGN BIAS - ADDITION AND SUBTRACTION
Plate 43C
This plate illustrates the method employed in controlling the Accumulator Amplifier
Biases. These Biases are shown on plate 1 and referred to as Add and Subtract Bias.
The raising of Sign Bias requires two steps. The control circuit first prepares
which Sign Bias, Add or Subtract" is to be raised. At the proper time the clamp is
released and Sign Bias rises. One control tells which Bias and the second control
tells the proper time.
Raising SB automatically starts a cycle of RIG.
Operation
This circuit shows the controls required to raise either the Add or Subtract Bias.
Each control will be explained separately.
Add Bias
The control circuits will condition the 11 of PSA high from either EIAl, EIA2, or
EIA3. At this time DRB is left so the RP of DRB is high to the RI of PSAC. The
plates of PSAC are conduct.ing and therefore take precedence to maintain the left
grid of PSA low. This condition will remain until DRB is triggered right. DRB
going right cuts off PSAC, removing the clamp on PSA. The left grid of PSA is
raised and the LP of PSA conducts. The low from the LP of PSA lowers the 11 of
PABA. The RD of PABA is low since Trigger PAM is on the left (no negative number).
Both sides of PABA are cutoff so the plates are free to go high. The high from the
plates of PABA go to BA+l, BM+l and Bll+l. In the three latter stages two neons in
series, as shown on plate
are fired which raises the grids of BA+ and BA+l,
BM+ and BM+l and Bll+ and Bll+l. These stages are Cathode Followers and control
the Amplifier Add Biases of Accumulators lA-llA, IM-1OM and lIM respectively.
The grid of BA+ is connected, through a resistor, to the lC of RB. The high from
BA+ causes RB to conduct, releasing a negative pulse from the lP of RB. This
negative pulse from RB starts a cycle of RIG as shown on plate 5.'
SB will remain high until the cycle of RIG is completed (CX Pulse).
left and reclamps PSA resulting in lowering SB.
DRB returns
The Test RIG, during ER Control Circuit Time, does not require any SB preparation.
When the lP of M~R goes low the Add Bias is raised.
C-143
Subtract Bias
The control circuits will condition the RI of PSA high from either EISl, EIS2 or
EPPM. At this time DRB is left so the RP of DRB is high to the RI of PSAC. Tha
plates of PSAC are conducting therefore they take precedence to maintain the right
grid of PSA low. This condition will remain until DRB is triggered right. DRB, going
right, cuts off PSAC removing the clamp on PSA. The right grid of PSA is raised and
the RP of PSA conducts. The low from the RP of PSA lowers the LI of PABAI. The LD
of PABAI taps off low to the RD of PABSI. The LI of PABSI is low since Trigger PAM
is on the left (no negative number). Both sides of PABSI are cutoff so the plates are
free to go high. The high from the plates of PABSl go to BA-l, EM-I and Bll-l. In
the three latter stages two neons in series, as shown on plate 42, are fired which
raises the grids of BA- and BA-l, EM- and EM-I, and Bll- and Bll-l. These stages are
Cathode Followers and control the Amplifier Subtract Biases of Accumulators lA-llA,
1M-10M and 11M respectively.
The grid of BA- is connected, through a resistor, to the RC of RB. The high from BAcauses RB to conduct, releasing a negative pulse from the RP of RB. This negative
pulse from RB starts a cycle of RIG as shown on plate 5.
SBwill remain high until the cycle of RIG is completed (CX Pulse).
and reclamps PSA resulting in lowering SB.
DRB returns left
MINUS FACTOR - ADDITION AND SUBTRACTION
Plate 44C
This plate shows the method employed for controlling the Accumulator Amplifier Biases.
These Biases are shown on plate 1 and are referred to as Add and Subtract Bias.
This circuit is employed in the event the number has a negative value.
The raising of Sign Bias in dealing with Minus Factor requires 3 steps. The control
circuit first prepares which Sign Bias, Add or Subtract, is to be raised. Secondly,
the control circuit, by means of Keyboard Bias, reads to check for Minus Factor. This
operation is shown on plate 20. If a number proves to be negative Trigger PAM is
kicked right.
NOTE:
.
.
An exception to this occurs in Complementize where the reverse is
true. A positive number kicks PAM.
Last, the Trigger DRB goes right to release the clamp and raise Sign Bias. In this
case, because PAM is right, the opposite Sign Bias to the one originally prepared
will be raised.
Raising
S~
automatically starts a cycle of RIG.
Operation
Add Bias - Subtraction with Minus Factor
This operation would occur during ES, EPS or EPP Control Circuit Time. The control
circuits will condition the RI of PSA high from either EISl, EIS2 or EPPM. At this
C-144
time DRB is left so the RP of DRB is high to the RI of PSAC. The plates of PSAC
are conducting so therefore take precedence to maintain the right grid of PSA low.
This condition will remain until DRB is triggered right. DRB, going right, cuts
off PSAC, removing the clamp on PSA. The right grid of PSA is raised and the RP
of PSA conducts. The low from the RP of PSA lowers the LI of PABAI. The RD of
PABAI is low since Trigger PAM is on the right (negative number). Both sides of
PABAI are cutoff so the plates are free to go high. The high from the plates of
PABAI go to BA+l, EM+l, and Bll+l. In the three latter stages two neons in
series, as shown on plate 42 J are fired which raises the grids of BA+ and BA+l,
BM+ and BM+l and Bll+ and Bll+l. These stages are Cathode)Followers and control
the Amplifier Add Biases of Accumulators, lA-llA, IM-IOM and lIM respectively.
The grid of BA+ is connected, through a resistor, to the LC of RB. The high from
BA+ causes RB to conduct, releasing a negative pulse from the LP ofRB. This
negative pulse from RB starts a cycle of RIG as shown on plate 5.
SB will remain high until the cycle of RIG is completed (CX Pulse).
left and reclamps PSA resulting in lowering SB.
DRB returns
Subtract Bias - Addition with Minus Factor
This operation could occur during any control circuit time except ER or !PM. The
control circuits will condition the LIof PSA high from either EIAl, EU2 or EIA3.
'At this time DRB is left 'so the'RPot DRB is ,high to the RI of PSAC. The ,plates
of PSAC are conducting, therefore they take precedence in maintaining the left
grid of PSA low. This. condition will remain until DRB is triggered right. DRB,
going right, cuts off PSAC, removing the clamp on PSA. The left grid of PSA is
raised and the LP of PSA conducts. The low from the LP of PSA lowers the Llof
PABA and taps off the LD of PABA low to lower the RD of PASS. The LI of PABS is
low since PAM is right (negative numb$r). Both sides of PABS are cutoff so the
plates are free to go high. The high from the plates or PABS go to BA-l, EM-I
and Bll-l. In the three latter stages, two neons in series, as shown on plate 42
are fired which raises the grids of BA- and BA-l, BM- and EM-I and Bll- and Bll-l.
These stages are Cathode Followers and control the Amplifier Subtract Biases of
Accumulators lA-llA, 1M-10M and lIM respectively.
The grid of BA- is connected, through a resistor to the RC of RB. The high from
.BA- causes RB to conduct, releasing a negative pulse from the RP of RB. This
negative pulse fromRB starts a cycle of RIG as shown on plate 5.
SB will remain high until the cycle of RIG is completed (CX Pulse)~
left and reclamps PSA resulting in lowering SB.
DRB returns
SIGN BIAS - DIVISION AND MULTIPLICATION
Plate 45C
This plate shows the method employed for controlling the Accumulator Amplifier
Biases in Multiplication or Division. These Biases are shown on plate 1 and
referred to as Add and Subtraot Bias.
C-145
This circuit is employed only during ES or EPS Control Circuit Time. No preparation
is necessary, as in Addition or Subtraction, since negative numbers do not affect this
circuit.
Raising SB automatically starts a cycle of RIG.
Operation
This circuit is composed of three parts, Multiplication, Trial Subtraction, and Add Back.
Each operation is covered separately.
Multiplication
Trigger PM2 goes right in Multiplication whenever a number is to be registered (cycle
of RIG). The RP of PM2 going low cuts off the LP of PM23. The LP of PM23 goes high
to BA+l, BM+l and Bll-l. In the three latter stages two neonsin series, as shown
on plate 42, are fired which raises the grids of BA+and BA+l, BM+ and BM+l and Blland Bll-l. These stages are Cathode Followers and control the Amplifier Add or
Subtract Biases of Accumulators lA-llA, 1M-10M and 11M respectively.
The grid of BA+ is connected, through a resistor, to the LC of RB. The high from BA+
causesRB to conduct, releasing a negative pulse from the LP of RB. This negative
pulse from RB starts a cycle of RIG as shown on plate 5.
This combination of Sign Biases allows a number to be added in Accumulators lA-llA and
lM-IOM. AccumulatotllM has the Subtract Bias raised so any pulses in this Accumulator
will cause subtraction.
This SB is not necessarily lowered at the completion of one cycle of RIG(CX Pulse).
The length of time this SB combination is raised is controlled by PM2 which is in turn
controlled by the presence of a digit inllM. This operation is shown on plate 23.
Division - Trial Subtraction
Trigger PDl goes right in Division whenever a Trial Subtraction is required (cycle of
RIG). The RP of PDl going low cuts off the RP of PDA. The RP of PDA goes high to BA-l,
BM+l and Bll+l. In the latter three stages, two neons in series, as shown on plate 42
are fired which raises the grids of-BA- and BA-l, BM+ and BM+l, and Bll+ and Bll+l.
These stages are Oathode Followers and control the Amplifier Add or Subtract Bias of
Accumulators lA-llA, 1M-10M and 11M respectively.
The grid of BA- is connected, through a resistor, to the RC of RB. The high from BAcauses RB to conduct, releasing a negative pulse from the RP of RB. This negative
pulse from RB starts a cycle of RIG as shown on plate 5.
This combination of Sign Biases permits a number to be subtracted in lA-llA and added
in 1M-10M and 11M.
This SB is not necessarily lowered at the completion of one cycle of RIG (CX Pulse).
The length of time this SB combination is raised is controlled by PDl which in turn
is controlled by the llA to 1M overcarry. This operation is shown on plate 25.
C-146.
Division - Add Back
Trigger PD2 goes right in Division whenever an Add Back is required (cycle of
RIG). The RP of PD2 going low cuts off the LP of PDA. The LP of FDA goes high to
BA+l, BM~l and Bll-l. In the latter three stages two neons in series, as shown On
plate 42 , are fired which raises the grids ofBA+l and BA+, EM-I andBM- and Bll-l
and Bll- •. These stages are 'Cathode Followers and control the Amplifier Add or
Subtract Bias of AccUlllUlatol's lA-IU, lM-lOMand IlM respectively.
The grid of BA+. is connected, through a resistor, to the LC of RB.The high from'
BA+ causes RB to conduct, releasing a negative pulse from the LP of RB. This
negative pulse from RB starts a cycle of RIG as shown on plate 5~
This combination of Sigh Biases allows a number to be added in Accumulators lA-llA
and subtracted in lM-IOM and IlM.
This SB is lowered after one cycle of RIG is completed (CX Pulse). Trigger PD3
controls this SB and is in turn controlled by the llA to 1M overcarry which occurs
on every Add Back Operation. This operation is shown on plate 25.
0-147
(-) STORAGE BIT OPERATION
Plate 46C
Any minus Result in x or + and a numerical minus Result in + or - will result in
lowering the plates of MCB. This, in turn, raises the LP-MC7 to condition Gate
EBG for Minus Branching. The same low from MC8 cuts off the LP:"SSRO to raise the
cathodes of SSK conditioning the starter electrode of the Minu.s B:tts so that the
Storage Set Pulse can fire the proper tube. When the Minus Bit is fired its indication is read, by the Read Out Driver, thru the right side of SSROresulting in
raising the RP-SSRO and firing the minus neon for Storages. Whenever the A
Section is zero during MS time and MC2 is right, Minus Branching & Minus Result to
Storage are defeated. Stage ~9C would be cut off and the high from its LP keeps
the LI-MCB low preventing conduction in this tube as shown on plate 20.
C-148
-40V REGULATED SUPPLY
Plate 47C
The -40V supply is employed in the Storage Circuit. It is used as a high voltage
limit on the cathode of the FK stages. The tubes and circuit components used to
make up this supply are located in the Power Control Section behind the Meter
Panel. The supplyis self regulating.
Operation
Tube OB2, a Voltage Regulator, is placed in parallel with three resistors. This
means that the voltage drop across these three resistors is constant and regulated.
One of these resistors is a potentiometer, R2l2. R2l2 adjusts the control grid of
the pent ode 6AU6. It is this potentiometer which is adjusted to obtain a -40
reading. The amount of conduction thru the 6AU6 and therefore the plate voltage
of the 6AU6 will control the grid level of the 6AS7 tube. The plate of the 6AU6
uses a l20K resistor to +150 as a load resistor. The voltage drop across this
resistor, through the l14V neon, controls the grid voltage of the 6AS7. The plate
of the 6AS7 controls the o11tput voltage level which is adjusted at R2l2 to be -40
volts.
The regulation of this -40 volt supply is obtained by the 6AU6 tube. Any variation
of the -40 volt level will affect conduction in the 6AU6 since the cathode of the
6AU6 is connected to this -40 volt line. Suppose the -40 volt supply attempts to
go to -38 volts. This rise in voltage raises the cathode of the 6AU6 lessening
conduction in this tube. The plate of the 6AU6 will rise and because of amplification some of the change on the plate is fed back to the control grid through the
4-7 uuf. capacitor. The amount of plate rise is then-fed to the grid of the 6AS7
which causes this tube to conduct more and bring the -40 volt line back to normal.
The inverse would be true if the -40 volt supply was momentarily lowered.
C-149
CATHODE CONTROLS ON CX
Plate 48C
The CX Gate cathode control is used to stop the Computer operation under the
following conditions:
1.
The Test Counter reaching 400 when used on Post RIG. This
enables the Service Technician to read the Accumulator
values at various times.
2.
Alpha or Double Input Check in the Input Decoder. The decoding
system combined with a cycle of RIG would enable the Computer
to register a number value when a Double Input is present.
This cathode control prevents the Computer from continuing
calculation whenever this occurs.
3.
PTP when Read switch is operative. The Read switch is used
whenever the Vl, V2, or R values are to be read. This
prevents the Computer from calculating beyond EM time.
4.
KB
5.
C9T time must nullify the KB Detector Circuit since C9T has
no decimal but does register a 1 in Accumulator lA.
Detector Circuit. Whenever a KB is raised some
detection is necessary since a zero numerical value is
permissible. Every value, zero included, must have a decimal.
The lack of any Decimal Input Line being raised will block
CX to indicate that KB -is missing.
C-150
STEP TRIGGER AND GATE
Plate 49C
This circuit is a schematic representation of the method used to bring a Step
Trigger right.
Branching into a new step is controlled from stage EBP for a Positive Result or
from stageEBM for a Minus Result. The plate of one stage will conduct sending
its plate low, through the Plugboard, to the resistive input of a Diode Gate,
opening the Gate. When the previous step is completed an ESI Pulse is released.
This ESI Pulse pulses the open Diode Gate. The plate of the Diode Gate releases
a negative pulse to the RD of a Step Trigger, triggering this stage right.
This method is employed in branching into Function Steps as well as Calculating
Steps.
C-151
FLIP - FLOP DELAYS
NAME
TYPE
RS
F-l
£JFD1F-l
£JFS
F-l
PMD2
F-l
PM3F-l
DELAY
TIME
25
25
25
25
·25
us
us
us
us
us
PDND
F-l
25 Us
PD2D
F-l
F-l
F-l
25 us
25 us
25 us
25 us
25 us
25 us
100 us
100 us
100 us
100 us
100 us
300 us
300 us
450 us
450 us
5ms
5ms
~O ms
...l{) ms
flO ms ')
!lOms
1~00 us
5ms
150 us
150 us
150 us
2ms
14 us
14 us
14 us
PM0D
PDAM
DCCD
DP1-DP16
PT3
RD
C£JD
c£JDA
C9D
ICL
EZB5
EZB2
EPZ
EMDZ
~FZD
1!MZ
AGFl
AGF2
AAFl
AAF2
EP4
EP
ESD
MS
DEA
MZ (1)~Z(12)
EGD
PHDl
EDPZ
F~l
F-l
F-l
F-2
F-2
F-2
F-2
F-2
F-2
F-2
F-3
F-3
F-3
F-3
~-3
F-3
F-3
F-3
F-3
F-3
F-3
F-3
F-3
F-3
F-4
F-4
F-4
CD
F-5
PAMD
F-6
EZ
F-6
I
50 us
250 us
450 us
C-152
T.D. between RIG1' & RIGS
··T.D. for retUrn of£JF1. KB Recovery
T.D. between Ctl. Ring Pulses
T.D. lower SB before shifts (M-D)
T.D. to condition circuit for a £J
or 'digit in IlK
T.D. to stop shifts before 1st Trial
Subtraction
T.D. to lower SB before Shifts
T.D. 'for M-D CTR. to be conditioned
T.D. to return PAM
Delays the (-2) Corr. Pulse in DCR
Decimal Registration delay
Allow ABa to open before pulsing EGD
T.D. for SB to rise
T.D. for £J Check Lines to normalize
.
"
"
n"
" " "
"
"
" "
Operates Input Recovery
B5 Zeroize
B2 Zeroize
T.D. for B2 Zeroize
"
"
"T.D. "for "Storage
" Zeroize
" ""
"
Function Step delay
"
"
"
Set I Pulse
Set II Pulse
Timer recharge time
Absorb Cam A contact bounce
Delay between ESZ & ESI
T.D. to Set Storage'
T.D. for KB to rise o~ fall
Generate Store Clear Pulse
Calls for ESI, ESZ & EZ
T.D. to condition a Gate (M-D)
T.D. to allow Store Set Lines to
normalize
T.D. to a+low RIGl to be registered
T.D. to allow KB to rise
T.D. for Zeroize
CALCULATOR CRANK UP
Plate 50C
This circuit is located in the Power Control end of the Computer. The term crank
up refers to the sequence of operation necessary to turn on the fans, bring up the
tube filaments and supply the D C voltages once the On button is depressed. The
A1' B1, C1 , A2, B2 and C2 lines represent the AC supply required to operate the
Computer. In a single phase system the A1, B1 and C1 lines are all connected. In
a three phase system the AI' Bl and Cl lines are separate.
K201
Line C2 through fuse F209 is connected to the On button. Depression of the On
button supplies this AC voltage through the Off button to the coil of K20l. K20l
is energized and the AC line returns through F2l0 to line Bl. Contacts 4 and 5
and 7 and 8 make on K20l. Contacts 4 and 5 on K20l become a holding circuit
through the Off button for K20l.
Fans
Line A2 through F203, F20l and contacts 7 and 8 of K20l energizes K204. K204 AC
supply returns on line Al' The contacts on K204 transfer so the AC from line A2
through F203 will pass 'through the closed contacts on K204 to operate the Fan Motors.
K202
Line A2 through F203, F20l contacts 7 and 8 on K20l, and 1 and 3 contacts on the
Thermostat energizes K202. K202 AC supply returns on line Al' The contacts on
K202 are used as the return for all transformer primaries used in the filament
supply and DC voltage supply. Line C2 through F208 passes through 'a 17 ohm 300
watt resistor to supply the primaries of the filament transformers T26 and T27.
Lines B2 and A2 in a like manner supply filament transformers T26C, T28, T21, T26A
and T26B. The supply to these transformer primaries is reduced through the 17 ohm
resistors so that the filament voltage is only partial. Transformer T29 on line
B2 is used to supply 115 volt AC to the outlet, Lumi1ines and Selector Relays.
TD2.Q!
Line A2 through F203, 1201, contacts 7 and 8 on K201 and 1 and 3 contacts on the
Thermostat energizes the Hold Coil for TD 201 and through the 120 second contact
energizes TD2010 TD201 is a time delay unit which completes a series of 3 circuits
over a preset time interval. The Hold Coil is a mechanical hold to prevent the
contacts closed by TD201 from reopening when TD201 is de-energized by the 120 second
contact.
1.
Circuit #1,- 10 seconds
10 seconds after TD201 is energized these contacts transfer.
C-153
2.
The same AC supply as that to TD201 passes through these
contacts to energize K203. The contacts on K203 will .
shunt out the 17 ohm resistors which allows the filament
voltages to rise to their proper value.
Circuit #3 - 60 seconds
60 seconds after TD201 energizes. these contacts are
transferred. Line A2 through F202 contacts 3 and 4 of
K203 and circuit #3 contacts on TD201 energizes K205.
The contacts of K205 transfer preparing for the circuit
operation.
'
3.
Circuit
~
#2
- 90 seconds
90 seconds after TD201 energizes these contacts are
transferred. Line B2_ through F204 contacts 5 and 6 of·
K203, F206, circuit #2 contacts on TD201, K205 contacts,
Plugboard and Service Interlocks energizes TD202. This
same AC supply passes through the closed 5 second contact
on TD202 to energize K206. The contacts on K206 transfer
so that line C2, through F207, will energize the primaries
of tne transforme~s T22, T24, and T25. These transformers
supply the minus DC voltage circuits. Each DC voltage,
upon reaching its proper value, pulls in a relay. These relays, Kl15, Kl14, Kl13, Kl12, Kl18, Klll and K210, have an
AC supply, from the 5 second TD202 contact, pass through their
contacts to energize K207. All minus voltages must be up to
their proper level in order for K207 to be energized. K207
has its contacts transfer so that line B2 through F205 can
energize the primaries of the transformers T23 and T30. These
transformers supply the plus DC voltage circuits. The two
plus DC voltages, upon reaching their proper value, energize
Kl16 ·and Kl17. The AC supply to TD202 now bypasses the 5
second contact on TD202 to the Plus Voltage Check. The AC
supply passes through the Plus Voltage Check to the Common
Voltage Check. The AC supply at the Common Voltage Check holds
in K206 and also goes through the minus voltage contacts to
the Minus Voltage Check to hold in K207. The 5 second contact
on TD202 now opens but the DC voltages are now kept available
through their own interlock. Any of the DC voltages dropping
out will automatically drop out all the other DC voltages. In
case of a blown fuse in anyone of the DC voitage circuits the
tuse neon will only be lit for approximately 5 seconds due to
the supply to K206 and K207 being removed by the 5 second contact TD202. TD202 remains energized. In order for the fuse neon
to refire either the Service or Plugboard Interlock must be
broken and remade so TD202 can drop out and then pull in again
to resupply the' DC voltage circuits.
4.
120 seconds
120 seconds after TD201 is energized this contact opens.
TD201 is de-energized but circuits 1, 2 and 3 remain closed by
the mechanical action of the Hold Coil.
C-154
The crank up is completed, the Ready light is lit on the
Punch Operators Panel and the Computer is ready to
calculate.
C-155
POWER SUPPLY VOLTAGES
Plates
51C and 52C
These plates show the connections and components required to rectify the positive
and negative DC voltages. All DC voltages are full wave rectified. The voltage
check system as explained on plate 50is shown so the relay operation can be seen.
The -165, -90, -15, -375, +75 and +150 volt supplies have their filter capacitors
partially charged through resistors. Each voltage supply when at their proper
. level pulls ina relay whose contacts shunt out the charging resistor.
The control circuit mounted at the top of the -165V Capacitor assembly is for the
purpose of eliminating overloads on the EL3C Rectifier tube, which would otherwise
be present when the filter capacitor bank charges.
At the instant T-22 becomes energized, charging current flows to capacitor C203,
through resistors R20l, R202 and R203. These resistors limit the current flow to
a safe value for the tube.
As the -165V line on the output of F2l9 increases its voltage in a negative direction,
R207 passes current to C20l, charging same. As the charge reaches the voltage required to operate K209, the relay closes, and shorts out R203. At this time, an
increased current flows through R201 and R202, charging the capacitor C203 further.
The closing of K209 also starts a new charging time interval when contacts 7 and 8
close. This permits C202 to be charged through R208 and K2l0 theh operates. Contacts 3 and 5 (paralleled) and 4 and 6 (paralleled) then short out R20l and R202,
allowing full current charge of capacitor bank C203.
K208 contacts are used to discharge C20l and C202 through R204 and R205 so that full
charging time is available in the following charging cycle, should it follow
immediately.
These circuits are checked as follows:
1. All relay contacts should be clean and have proper wiping action.
make very good contact.
They must
2.
Resistors R20l, R202, R203, R207 and R208 should be checked.
3.
Timing of K209 and K210 should be checked, and if found to be short,
C201 and C202 should be changed. K209 should pull in approximately .2
seconds after T-22 is energized. K210 should pull in .9 seconds after
K209 closes.
Relay Kl19 contacts 4 and 5 and Kl12 contacts 5 and 6 are used to break the 115
volt AC supply to the Selector Power Chassis whenever the Service or Plugboard
Interlocks are broken.
The transformer primary windings for both filament and D.C. supplies have an
auxiliary winding which permits closer adjustment of the output voltage on the
C-156
secondary side. All transformer primaries are numbered similarly; therefore, any
transfoI'li1er adjustment, filament or D.C. can be made according to plate 51 or 52.
The Line voltage should first be measured and then' the transformer primaries may be
connected using plate 51 or 52 as a guide •. Some corrections may be necessary to
offset transformer variations.
gne Voltage
5 - 6 Coil
230
226
224
220
216
212
208
Do not use
use
use
Do not use
use
use
Do not use
Primary Connections
Line
Line
Line
Line
Line
Line
Lihe
to
to
to
to
to
to
to
4
5, 6 to 4
6', 5 to 3
3
5, 6 to 3
6, 5 to 2
2
When it is not necessary to use Terminals #5 or 16, leave one en~ of the jumper wire
connected to Tap #5 or 16 and the other to a tap not being used for the line.
CAUTION:
Never connect the jumper wire from Terminal
#5 to 16.
The filament voltages should be at 6.3 Volts ~ .2 Volts at the chassis male contacts
or at the socket of the Rectifier or Thyratron Tube x:equiring a 6.3 Volt filament
supply. The Rectifier Tubes requiring a 2.5 Volt filament supply shou.ld have 2.5
Volts + .01 Volts at their socket.
No adjustment should be attempted without the use of a low scale A.C. meter of 2%
accuracy or better since the usual accuracy of the field service meters is not better
than 5%.
The D. C. voltages should be adjusted within
2%
except -60 which is allowed 10%.
The current available to the Punch Actuators can be increased from 2 to 3 mao by
adjustment of the -165 Volt Supply so that with a maximum value in Storage the -165
Volt value will still. be very near -165 Volts.
The following procedure should be observed when adjusting the -165 Volt Supply:
1.
The line voltage should be at its nominal value, all Storages cleared, and
the Field Board removed.
2. p-nivac - 120
Set the -165 Volt Supply to -169 plus (+) ,or minus (-) 2 Volts.
Univac - 60
Set the -165 Volt Supply to -167 plus (+) or minus (-) 2 Volts.
3. When all Storages in all columns have an even value, the -165 Volt
supply should read very close to -165 Volts.
0-157
4.
If the line voltage is above or below the nominal value, then the
plus (+) or minus (-) 150 Volt line can be used as a guide. If,
for example, both read very nearly the same and are 2 Volts low,
then the -165 Volt Supply reading will also be 2 Volts low.
Therefore, if adjustment is be~ made on a Univao 120 the -165
line would be set at -167 Volts {plus (+) or minus ( ...) 2 Volts)
and when all Storages are set it would then drop to -163 Volts.
C-158
PUNCH POWER SUPPLY
Plate 53C
The Punch has two transformers and two selenium rectifier bridges to give a 70 volt
full wave rectified DC supply. These supplies are 70 R for Punch Relays and 70 C
for Punch Clutch and Brake circuits. The motor is driven by a 230 volt supply.
Line 1 and line 2 are used to operate the AC solenoids in the Punch.
The motor and 70 volt supplies are operative only when the On switch is effective
on the Operators Panel.
Plate 14B shows the physical location of the Power Supply and Punch Relays.
section is located on a hinged door on the left hand side of the Punch.
This
PUNCH CLUTCH AND BRAKE OPERATION
Plate 54C
Clutch
The Clutch used in the Punch is electro-mechanical. There must be a voltage supply
to the Clutch in order to function. The Clutch can be energized by three methods.
1.
Card Feed Start Switch when the Computer is not calculating.
2.
Trip Pulse at the completion of a calculation.
3.
Card Release and Unit Switch joint operation at all times.
Each of the three methods will be explained individually. The Brake Release Relay
Kll is energized in parallel to the Clutch, excluding resistor R50.
Card Feed Start Switch
The operation of the Start Switch applies ground through the switch to contacts 10
and lIon K4 to charge C3l and energize the Single Cycle Relay, K3, while C3l is
charging. The 70C volt supply goes through R6 to Ll to contacts 5 and 6 ot Kl (Kl
is energized whenever the Punch Motor is running and no card jam is present) to
contacts 3 and 4 of K3 to contacts 5 and 6 of K18 (K18 is de-energized when no
calculation is occuring) to contacts 4 and 5 of KIO to ground. Clutch, Ll, is now
energized and the Punch will cycle. K3, being capacitively energized, will not
remain energized so an alternate method must· be provided to keep the Clutch, Ll,
energized when K3 de-energizes.
The Clutch is retained energized by the 70C supply through R6 to Ll to contacts 5 and
60f Kl to Cam M (290-116) then Cam N (28-214) to ground. Cams M and N are both
needed so that the stopping time of the Puncb can be altered without affecting the
pickup time of Cam M. The Punch does not stop as soon as Cam N breaks since the
Brake must be applied. The. Brake operation is explained under a later heading.
The operation of the Start Switch can also energize the Shut Off Relay, K5. There is
an On-Off switch on the Operators Panel called Auto Start. This swit-ch is generally
in the On position. The On position assures the PunCh. of automatic cycling by a
Trip Pulse. In the event only one card at a time is to be fed, the Auto Start switch
is placed in the Off position. When the Auto Start. switch is in the On position and
the Start Switch is operated, ground is supplied to the Shut Off Relay, K5, causing
K5 to energize. K5 sets up its own holding circuit. A 10R volt supply through K5
to contacts 3 and 4 on K5 to contacts 7 and 8 on K3 to Full Receiver contacts, to
FUll Chip Basket contacts, to No Card Sensing contacts, to Stop Switch contacts, to
ground enables K5 to remain energized. Any condition which breaks this hold circuit
de-energizes K5 and prevents a Trip Pulse from energizing the Clutch. Releasing the
St&rt Switch discharges C3l through R12.
Trip Pulse
A
Trip Pulse is released from the Computer whenever the calculation of a card is
C-160
completed. The Trip Thp-atron Pulse passes through contact 3 and 4 of Kl to
contacts 6 and 5 of K2 tK2 is energized by Cam K when the Punch cycles and the DC
voltages are present in the Computer with the VAD Relay reset and held through the
Unit-Clear Switches) to K16 to +150 volts to energize the Trip Pulse Relay, K16.
K~6 sets up a holding circuit from +150 volts through K16 to contacts 9 and 10 on
K16 through Cam L (114-75) through Unit-Clear switches to ground.
The Clutch can now be energized by a 70C volt supply throu.gh R6 to L1 to contacts·
5 and 6 on Kl (Cams M and N.. usually are broken at this time) to contacts 6 and 7
on K5 (energized by Start Switch operation) to contacts 12 and 13 on K16 to ground.
This enables the PWlch to again cycle and at 290 0 of Punch Time Cams M and N continue
to hold the Clutch energized.
Card Release and Unit Switch
The Card Release and Unit Switches must be operated jointly to be effective in
energizing the Card Release Relay, K4. The contacts on K4 not only enable the
Clutch to energize but also energizes the Skip Solenoid and prevents a Sort
Solenoid and Non-Reset Solenoid operation.
The Card Release Relay, K4 is energized by groUD.d through operated Unit and Card
Release Switches through K4 to 70R volt supply. Contacts 9 and 10 on K4 charge
C3l to energize K3 while C3l is charging. The Clutch C4n now be energized. The
70C supply through R6 to L1 to contacts 5 and 6 on Kl (Cams M and N are open) to
contacts 3 and 4 on K3 to contacts 12 and 13 on K4 to contact 6 on K18 to contacts
4 and 5 on KIO to ground allow the Clutch to energize. Once the Punch has started
to cycle, Cams M and N keep the Clutch energized.
Brake
The Brake Magnet is energized automatically whenever the Clutch is de~energized.
The Brake Magnet does not remain energized once the Punch is stopped. The Brake
Release Relay is energized in parallel with the Clutch and it is the Brake Release
Relay, Kll, de-energizing that signals the Brake is to be applied.
The Brake Release Relay, Kll, is energized together with the Clutch and contacts
3 and 4 on III enable whatever charge may be present on C3 to discharge through R16.
The Clutch and III wtll de-energize when Cam N opens and no Trip Pulse has occurred.
C3 will charge through contacts 4 and 5 of Kll at a Time Constant determined by R5.
KIO is in parallel with R5 and will be energized while C3 is cha.rging. The 70C volt
supply through R6 to L2 to conte,cts 14 and 15 of K16 to contacts 3 and 4 of KIO to
ground "will enable the Brake Magnet to energize. As soon as C3 is charged KI0 deenergizes and the circuit for the Brake Magnet is broken causing the Brake Magnet to
de-energize. The Punch is now stopped • Any incoming Trip Pulse will again energize
the Clutch and Brake Release Relay. The Brake Release Relay being energized will
discharge C3.
In the event the StOop Switch was operated to prevent any fUrther Punch cycling a
Trip Pulse would still energize the Tl'ipPulse Relay, K16, so another path is required to operate the Brake Magnet, L2. The Stop Switch operation will de-energize
K5 so the 70C supply through R6 to L2 to contacts 14 and 15 on K5, instead of 14 and
15 on K16, to contacts 3 and 4 on KIO to ground will energize the Brake Magnet.
C-161
Unit and Clear Switches to Punch Position
The operation of these two switches jointly will break the hold circuit for the Trip
Pulse Relay, K16, and the B+ Failure Relay, K2, as well as reset the Hi-Lo Relay in the
VAD Chassis. In the event a problem is to be repeated after a Trip Pulse was received at K16, all Selector Relays, except any on Selector Hold, will not remain
energized since the Control Common is broken. Operation of the Unit and Clear
Switches de-energizing the Trip Pulse Relay, K16, causes the Control Common to again
become effective.
Unit and Clear Switches to Calc. Position
The operation of these two switches jointly
energize as long as these switches are held
being de-energized, will clear all Storages
Relays and Select Thyratrons and cutoff the
causes the Manual Clear Relay to deoperative. The Manual Clear Relay,
as well as de-energize all Selector
Timer.
Start Pulse
This pulse is used to signal the Computer that a card has been sensed and, therefore,
calculation can begin.
Ground through.Cam A (334-30) to the no card sensing switch to the RC of EP in the
Computer, kicking EP right.
When no card is sensed the No Card Sensing Switch opens from 310 0
nullH'ies any attempt from Cam A to start a calculation.
-
60 0 which
Non-Calculate Pulse
Two cycles of the Punch are required before a card is sensed after being fed from
the Feed Magazine. The first cycle of the Punch comes from operation of the Start
Switch. The second cycle comes from the Non-Calculate Pulse. This is the only
time the Non-Calculate Pulse can occur.
On the first cycle of the Punch, when Cam A closes, the No Card Sensing Switch is
transferred because no card is in the Sensing Section.
The transferred contacts of the No Card Sensing Switch are connected to the Empty
Magazine Switch. Cards are in the Feed Magazine so the Empty Magazine Switch is
closed. The ground from Cam A will now go to the RC of ATT, triggering ATT right
as shown on plate 30. ATT, going right creates a Trip Pulse to automatically trip
the Punch into its second cycle at which time this first card will be sensed. In
the event a misfeed occurs at the throat the Non-Calculate Pulse will not be effective
because the Shut Off Relay, K5, would de-energize preventing the Clutch, Ll, from
being energized even though the Trip Pu~se Relay, K16, may energize.
C-162
SORT, SKIP AND SET HOLD
Plate 55C
Sort
The Sort operation is begun in the Computer when either the Sort I (ASA1), Sort II
(ASA2) or tJF Sort (ARA1) Thyratrons are fired. A Sort Operation is controlled by
branching in the Program. The plates of all three Sort Thyratrons are connected to
the Sort Pulse Relay, K7.
The final result is to energize the Sort Solenoid which opens the Front Receiving
Magazine.
A Sort Pulse will energize the Sort Pulse Relay, K7, transferring its contacts.
Contacts 5 and 6 of K7 are used as a holding circuit for K7 through contacts 9 and
10 of K13.
The card whose calculation created the Sort Pulse is released by a Trip Pulse
between 268° - 275°. At 334° of the next card cycle Cam E closing supplies ground
through contacts 3 and 4 of K7 to 113, energizing the Sort Relay" 113. The contacts
of K13 transfer. Contacts 9 and 10 of 113 open to break the hold circuit for the
Sort Pulse Relay, K7, causing 17 to de-energize. The Sort Relay, K13, is held
energized by contacts 5 and 6 of 113, contacts 4 and 50f K4 and the contacts controlled by L7 to ground.
At 139° Cam F closes. The Sort Solenoid, L7, is energized from Line 1 to contacts
7 and 8 of K4 to contacts 3 and 4 of K13; to L7, to Cam F, to Line 2. L7 energizing
mechanically transfers two sets of contacts. One set of contacts opens to break the
hold circuit on K13. The Sort Solenoid, L7, is now held in from Line 1 to contacts
7 and 8 of K4, to L7, to Cam F, to Line 2.
Cam F opens at 235° to break the hold circuit on L7 causing L7 to de-energize.
This two step procedure is required in a Sort Operation because the card is a
complete Base Cycle away from the Receiving Magazine when the Sort Signal is
released. This procedure also allows cards in sequ.ence to all use Sort.
The purpose of Skip is to prevent punching by retaining the Set Bar Section in a
retracted condition. This is'done whenever the Skip Solenoid is energized.
The Skip Field is generally plugged from 70R through a Sensing Switch to the Bus.
Cam H closes at 140 0 to pass the 70R voltage supply to the Skip Relay, K14, causing
K14 to energize through Cam J which closed at 133 0 • Cam H is used to protect the
Sensing Switches from making hot. The contacts on K14 transfer and contacts 7 and 8
on 114 are used to.hold the Skip Relay, K14, energized through Cam J.
Line 1 through contacts 3 and 4 of 114 energizes the Skip Solenoid, L6, when Cam I
closes at 287° which is the beginning of the next Punch Cycle. At 287 0 Cam I
closes to energize the Skip Solenoid, L6. At this time the Punch is using the high
0-163
part of the Set Bar Retract Cam so operation of L6 locks the mechanism in this
position. Cam I breaks at 73° but by this time the pressure prevents restoration
of L6 linkage until the Punch arrives at the high part of the Set Bar Retract Cam.
At 94° Cam J opens and the Skip Relay, K14, de-energizes.
Skip Program
This operation is identical to Skip Field as to the end result. In this operation
Cam H is not used since Skip Program does not use a Sensing Switch. Skip Program is
located on the Program Board. Selector Relay contacts are to be used to carry the
70R volt supply across the Skip Program hub. This operation could be used to prevent
punching from the Program Control in place of a Control Hole.
Set Hold
The purpose of Set Hold is to prevent any Tower Retraction. The Non-Reset Solenoid,
when energized, disables the Tower Retraction Linkage. The Set Hold generally
operates in conjunction with Skip but could be operated independently.
The Set Hold hub has a 70R volt supply if Skip is operative and Cam H is closed.
Set Hold can use either a Sensing Switch or a direct jumper to supply the 70R volts
to K15. Cam J was closed at 133° so the Non-Reset Relay, K15, will energize.
The Non-Reset Relay, K15, is held energized by its transferred contacts 7 and 8
through Cam J to ground.
Line 1 through contacts 3 and 4 of K15 and contacts 14 and 15 of K4 energizes the
Non-Reset Solenoid L5, when Cam I closes at 287 0 which is the beginning of the next
Punch Cycle. At 287° Cam I closes to energize the Non-Reset Solenoid, L5. At this
time the Punch is on the low part of the Tower Retract Cam so the retract linkage is
free to be disabled. Cam I breaks at 73° but by this time the Tower Retract Cam is
fully operative so the retract linkage remains disabled. At 94° Cam J opens and the
Non-Reset Relay, K15, de-energizes.
In the event Set Hold is to be used independent of Skip, only a Selector Relay
contact should be used. The common of the relay contact should be plugged to a 70R
volt bus (Skip Field) and the select contact to the K15 side of the Set Hold bus.
C-164
REPRODUCE AND SECONDARY REPRODUCE
Plate 56C
plate shows the circuitry required to perform a Reproduce or Secondary
Reproduce Operation. Relays K8, K12, K7, K2 and K9 are located in the Punch.
lays K2l1 and K213 are located in the Power Control.
~his
Re-
A Reproduce Operation will clear all old Reproduce information by energizing the
Reset Solenoids and then set up new information by pulsing the R hubs.
A Secondary Reproduce will only add in new information by pulsing the Secondary
Reproduce Common.
The two types of Reproduce Operations enable information to be picked up from two
cards but only one Reproduce Field is set up from each card.
In the event one card had both Reproduce and Secondary Reproduce controls only
Secondary Reproduce would be effective •
.Reproduce
The Reproduce hub can be plugged directly or, as shown, through a Sensing Switch.
Once the Sensing Switch has closed there is a 70R voltage supply through contacts
4 and 5 of K8 to K12, through contacts 9 and 10 of K7 to Cam E to ground. Cam E
is closed from 334° - 70°. Once Cam E closes the Reproduce Clear Relay, K12, is
energized. Contacts 3 and 4 of K12 transfer to put an AC supply (Line 1) to the
Reset Solenoids. The Reset Solenoids perform a mechanical operation to insure all
Actuators will be reset by normal Tower Retraction.
Normally ,the B+ Failure Relay, K2, is energized but whenever B+ is removed in the
Computer K2 drops out. K2 being de-energized, automatically, through its contacts
7 and 8, operates the Reset Solenoids L3 and L4. Whenever Plugboards are changed
L3 and L4 pull in to automatically clear the Tower of any Reproduce lnformat'ion.
At 70° Cam E opens and the Reproduce Clear Relay, K12, de-energizes. The same 70R
voltage supply from the Rapr. hub also goes through K9 to Cam D to ground. Cam D is
closed from 89° - 280°. Between 70° and 89° the Tower is retracted leaving all
Actuators in the Tower normalized. At 89° Cam D closes to energize the Reproduoe Set
Relay, K9. Contacts 5 and 6 of K9 transfer t~ put +150 volts to K2ll.
A Trip Pulse from the Computer starts with stages ATT or ART, Either ARA3 or ATA
will then oonduct and since K9 is 'energized the Reproduoe Power RelaY', K2ll, will now
energize. The contacts of 1211 transf.er ohanging the primary of T31 from ground to
-165 volts. This change on the primary of T3l induces a lesser voltage (8:1) on the
secondary of T31. The positive pulse on the secondary of T31 is fed to the oommon
contacts of K213. 1213 is de-energized so the positive pulse is released on the
non-se1eot oontacts of K213 to the R position on the Field Board.
The R hub is plugged to the 0 hub of the column that is to be reproduced from. The
R hub can also be plugged to the H position of the columns reproduced 'into, if the
Reproduce information is to be retained for more than one oard.
0-165
Secondary Reproduce
The Secondary Reproduce hub is plugged through a Sensing Switch to the Control Common.
The closing of the Sensing Switch allows the Sec. Repr. hub to be grounded when Cam
B is closed. Grounding the Sec. Repr. hub energizes the Repr. Transfer Relay, K213,
and the Secondary Reproduce Relay, K8. K8 being energized transfers its contacts to
prevent operation of K12, Reproduce Clear. Contacts 3 and 4 of K8 puts a 70R voltage
supply through K9 to Cam D to ground. Cam D is closed from 89° - 280 0 • Any Reproduce
information in the Tower is not retracted during this operation. At 89° Cam D closes
to energize the Reproduce Set Relay, K9. Contacts 5 and 6 ofK9 transfer to put +150
volts to K2ll.
A Trip Pulse from the Computer starts with stages ATT or ART. Either ARA3 or ATA will
then conduct and since K9 is energized the Reproduce Power Relay, K2ll, will now
energize. The contacts of K21l. transfer changing the primary of T3l from ground to
-165 volts. This change on the primary of T3l induces a lesser voltage (8:1) on the
secondary of T3l. The positive pulse on the secondary of T31 is fed to the common
contacts of K2l3. K2l3 is energized during Secondary Reproduce so the select contacts
of K2l3 feed the positive pulse to the Secondary Reproduce Common on the Field Board.
The Sec. Repr. Common is plugged to the C hubs of the columns to be reproduced from.
The Repr. Common can also be plugged to the H hubs of the columns to be reproduced
into if the information is to be held for more than one card.
The Sec. Repr. Common should never be plugged to the R hub as this would defeat the
separation of the two operations.
C-166
POWER SUPPLY
Plate 59C
The Power Supply is located on the right end of the Computer. This section contains
the components required to rectify the DC Voltages required in the Computer Circuitry.
The Power Supply is shown on plate 59. Above TB114 is where all the rectifier tubes
are located. Transformer T21 is the filament transformer for these rectifier tubes.
TB117 is the terminal for adjustment of the primary of T21 for proper rectifier
filament voltage.
TB113 has the secondary connections for T25 for -375 and -60 volt supplies.
TB112 has the primary connections for;
1. T25 for adjustment of -15, -60, -375 and
~25
v.olt supplies.
2.
T24 for adjustment of -90 and -150 volt supplies.
3.
T30 and the rest of T30 is on TB111 for adjustment of the
+75 volt supply.
TB111 has the primary connections for;
1.
Remainder of T30 for adjustment of the +75 volt supply.
2.
T22 for adjustment of the -165 volt supply.
3.
T23 for adjustment of the +150 volt supply.
The primary adjustments are shown on plate 51, 52.
A blown resistor on this panel generally indicates a filament to cathode short in a
tube supplied fram the filament voltage which had used the blown resistor.
TB118 has the. secondary connections for T24 for
-90 and -150 volt supplies.
TB119 has the secondary connections for;
1. T30 for the +75 volt supply.
2.
T22 for the -165 volt supply.·
3.
T23 for the +150 volt supply •
.TB122 is used to connect the -15 volt and -25 volt selenium rectifiers.
TB110 has one side of the -165.volt supply choke L22, terminals for the Plus and
Minus Voltage Check and all DC voltage terminals except -165 and ~ volts.
The Fuse Panel contains the fuses for the DC voltage supplies except -165 whose fuse
is behind the Fuse Panel in the Power Control. The Fuse Panel is hinged to swing
forward and behind this Panel are the relays used in the Plus and Minus Voltage
C-167
Check as explained on plate 50. K119 is also located in this section. K119 breaks
the 115 volt AC supply to the Selector Relays whenever the DC Voltages are not present.
TB121 contains the DC voltage connections from the various chokes before being fused.
L'Z/ (-15), 123 (-90), 124 (-150) and 122 (-165) choke connections are on TB121 •
TB120 contains the connections far 128 (+75), 121 (+150), L26 (-375) and 125 (-60)
chokes.
C-168
POWER CONTROL
Plates 61C and 62C
The Power Control section of the Computer is located at the left end below the PTP
Panel.
Directly below the PTP Panel on plate 61 is ~he Voltmeter Panel. On this panel are
located an AC Voltmeter (M203), Running Time Meter (M202) and a Voltmeter (M201).
Below the meters are two switches S2~ and S203. S2~ is used to read the AC
voltages and S203 is used to read the DC voltages.
The Voltmeter Panel is hinged to swing forward. Behind the Voltmeter Panel, on the
left, is the Reference Regulator Chassis which is the ~ Volt regulated supply.
R212 is used to adjust for ~ volts. Behind the Voltmeter Panel, on the right, is
the Timing Assembly which is used in the Calculator Crank Up and is explained in
detail on plate 50.
On plate 62 the Power Control Section continues showing the RCS Chassis Assembly
located below the Voltmeter Panel. V211, V212, V213 and V214 are the Select Thyratrons 1 to 4 respectively. Cages 00203 and OO2dt are the grid bias and cathode
returns for the Select Thyratrons. K211 is the Reproduce Power Relay. K212 is the
Manual Clear Relay. K213 is the Reproduce Transfer Relay. K214 is a spare relay.
T28 is the Filament Supply Transformer for the Select Thyratrons and ~ volt supply
tubes. T31 Transformer is the Reproduce Pulse Transformer and CR203 is a selenium
rectifier across the primary of T31. TB2dt on terminals 10 through 15 are the primary taps for T28 to adjust for proper filament voltage.
.
Relays K202 and K203 are on the rear deck and K2dt, K206 and K2CJ7 on the front deck.
These relays are used in the Calculator Crank Up and are explained in detail in plate
50.
The Fuse Panel from F201 to F210 are also shown in detail in the Calculator Crank Up
on plate 50.
The Fuse Panel is hinged to swing forward and behind this Fuse Panel, though not
shown, are components used in the -165 volt supply which are shown on plate 51
within the dotted line area.
Below the Fu.se Panel is the filter capacitor assembly for the -165 volt supply.
TB208 and TB209 are connected b.r cable to the Punch.
Factory print 1940250 shows the wiring on the Power Control.
C-169
COMPUTER WIRING DISTRIBUTION
Plate 65C
This plate shows the w~r~ng to the various sections of the Computer. The detailed
wiring in the various sections can be found on the factory prints as labeled. The
chassis that the various sections control are shown on plates 57 and 58. By use
of this plate, plates 57 and 58 and the factory prints, it is possible to trace the
wiring within the Computer.
The factory print numbers each contain 3 prints.
a specific section.
The 3 prints show all wiring within
This plate is for reference purposes to assist in tracing the Computer w~r~ng. For
example, suppose all J Section connections are to be traced. Factory print #1940400
will show all J Section wiring. This plate shows that;
1.
T26D and T27 transformers supply the filaments of J section.
2.
J section connects to E section via the J Blocks.
3.
J section connects to J429 in the D section.
4.
J section connects to the Storage Door.
5.
J Blocks in J Section connect to the Minus and Input Neons.
6.
J Section connects to J Block 430 in Power Supply to pick
up D.C. supply.
C-170
ELECTRONIC COMPUTER
UNIVAC 60 & 120
ALPHA STAGE INDEX
STAGE
NAME
0'9c
0'9C1
09M
0'9SM
09SM1
0'c2
0'EsP
0'Ez
0EZ1
0F1
0F2
0F3
0F4
. 0F5
0FD1
0FD3
0FM
0FR1
0FR2
0Fs
0Fzn
0FZT
0LD1
((JLD2
~
0RS
0'Rsz
0'SR
liD
AAF1
A.AF2
AAF21
AAG
AAGL
AAK1
AAK2
AAM
AAR
AAT1
AAT2
AO
AOG
AOI
ACI'
AOM
CAGE
TYPE
DD-20
X
DD-1
DD-1
DD-7
GA-7
AA-1
GG-21
GG-2
T -1
GA-l
GA-1
GG-18
G(.;..)-2
F -1 '
X
RO-17
DD-1
DD-'7
F -1
F -3
RO-19
RO-1
x
T -1
T-5
GG-4
T -1
DD-1
F -3
F -3
RO-13
GG-4
RO-2
DD-7
DD-7
AA-2
RC-13
T -1
T -1
DA-2
GG-4
AA-2
X
DA-5
CHASSIS
LOCATION
STAGE
NAME
CAGE
TYPE
ACT
AGA
AGD
AGF1
AGF1 1
AGF2
AGF2 1
AGK
AGT
AGTZ
ANRI
0F
.0F
0F
0F
0F
0F
0F
0F
0F
0F
0F
0F
0F
T -1
AA-2
DD-7
F -3
RC-13
F -3
RC-13
K -3
T-4
DA-2
RC-42
RO-42
S -1
RO-14
RO-22
RO-14
DD-1
DD-1
DD;...1
DD-1
GG-4
GG-4
R0-2
R0-2
AA-2
AA-2
T -1
T -1
T -1
T -1
DD-7
R0-31
ANR2
AP3
AP01
AP02
APC3
APD1
APD2
APD3
APn4
APGA
0F
0F
0F
0F
0F
.0F
0F
0F
0F
APGB
¢F
0F
0F
0'F
0F
0F
00L1
0011
00L1
0011
,0011
00L1
00L1
00L1
00L1
00L1
00L1
0011
AOO
0011
00L1
00L1
00L1
APGL
APGM
APMA
APMB
APT 1
APT2
APT3
APT4
ARA1
ARA2
ARA3
X
ARG
GG-1
AA-2
AA-15
RG-1
T -1
DD-7
DD-1
RG-2
RC-2
DD-1
DD-1
GG-4
ARGI
ARM
ARR
ART
ARY
ARZ
ASA1
ASA2
ASO
ASD
ASG
0-171
"
CHASSIS
LOCATION
OCL1
OCL2
OCL2
OCL2
OCL2
OCL2
OCL2
OCL2
OCL2
00L2
OCL1
00L1
OCL2
00L2
OCL2
00L2
00L1
OCL1
OCL1
OCL1
OCL1
00L1
00L1
OCL1
00L1
0011
0011
OCL1
OCL1
00L1
OCL2
00L2
00L2
00L2
00L2
00L2
OCL2
0012
00L2
00L2
00L1
OCL1
00L1
00L1
00L1
STAGE
NAME
ASM
AST1
AST2
ATA
ATM1
ATM2
ATR
ATT
B11+
B11B11+1
B11-1
BA+
BABA+1
BA-1
BM+
BMBM+1
BM-1
C0CS
C0D
C0DA
C0DD
C0DE
C0DG
C0G
C0PG
c11M
C17
C35
C9D
C9G
C9R
G9T
CA
CA1
CAS
CB
CCC
CCM
CD
CDA
CGA
CM
CMA
c09
CHID
CS
CSK
CT
CT1
CT2
CAGE
TYPE
CHASSIS
LOCATION
AA-2
T -1
T -1
X
DA-5
AA-2
Rc-14
T -4
K -2
K -2
RC-27
RC-27
K -2
K -2
RC-27
RC-27
K -2
.K -2
RC-27
RC-27
T -1
F -2
F -2
DD-1
DD-7
00-1
GG-21
GG-1
S -1
LL-3
X
F -2
GA-1
X
T -1
DD-S
RC-1
Rc-1
S -1
DD-1
DD-1
F -5
AA-10
DD-24
M -2
DA-1
X
DD-7
00-2
C -1
T -1
T -3
T -3
OCL1
OCL1
OCL1
OCL1
OCL1
OCL1
OCL1
OCL1
SB
SB
SB
SB
SB
sa
SB
SB
SB
SB
SB
SB
CTL
CTL
CTL
CTL
CTL
CTL
CTL
CCTL
CCT
10
10
CTL
CTL
RIG
CTL
DCR
DCR
CCT
DCR
CCT
CCT
RIG
RIG
CCT
DCR
DCR
10
CTL
DCR
DCR
DCR
CCT
CCT
C-172
STAGE
NAME
CAGE
TYPE
CT4
CTS
CT10'
CT11
CTG
CTSG
CX
D2-14
D2-4C
DS-16C
DS-16T
DA1-16
DAM
DAS
DAX
DB2
DB4
DBS
DB16
DBC
DBT
Dc1
DC2
DC4
DCS
Dc16
DCC
DCCD
DCCL
DCK
DCK1
DCK2
DE!
DEA1
DEA2
DEN
DG
DI1
DIC
DK
DKG
DMD
DMG
DMP
DN12'
DN2-16'
DN4'
DN4S'
DNB-16
DP1
DP2
DP4
DPS
T -3
T -3
T -1
T -1
GG-1
GG-22
GG-6
GG-24
GG-24
GG-24
00-24
AA-16
T -4
T -4
T -3
AA-1
AA-15
AA-1
GA-3
K -3
K -3
T -3
T -3
T -3
T -3
T -3
T -4
F -1
X
RC-49
RC-49
RC-49
F -3
AA-2
AA-2
S -1
GG-29
GG-23
GA-7
T -3
GG-22
DD-1
GG-1
S -1
RC-22
X
X
RC-50
X
F -1
F -1
F -1
F -1
CHASSIS
LOCATION
CCT
GCT
CCT
CCT
CCT
CCT
DCR
DCR
DCR
DCR
DCR
DCL
DCL
DCL
DCL
DCR
DCR
DCR
DCR
DCL
DCL
DCR
DCR
DCR
DCR
DCR
DCR
DCR
DCR
CCT
CCT
CCT
DCL
DCL
DCL
DCL
DCL
DCR
DCR
DCL
DCL
DCL
DCL
DCL
DCR
DCR
DCR
DCR
DCR
DCR
DCR
DCR
DCR
STAGE
NAHE
DP16
DPG1
DPG2
DRB
DRP
DRR1
DRR2
DRR3
DRR4
DRS
WCA
E0CB
EBG
EBM
(1 , 2) EBM
( 3, 4) EBM
ESP
(1, 2) ESP
(3, 4) ESP
EBS
(1, 4) EC
ECB1
ECB2
ECS
(1, 2) ED
(3, 4) ED
EDPZ
EGD
EIA
EIA1
EIA2
ErA3
EID
EID1
EID2
EIM
EIMl
EIM2
EIS
EIS1
EIS2
EM
EM!
EMDC
EMDZ
( 1, 2) EMF
( 3, 4) EMF
EMK
EMZ
EMZ'
ENM
ENM1
CAGE
TYPE
CHASSIS
LOCATION
F -1
GA-11
GA-11
T -4
S -.1
RC-53
DCR
DCL
DCL
DCL
DCL
VAD
VAD
VAD
VAD
DCL
SB
X
X
RC-53
T -1
GA-6
DD-12
GG-6
K -3
X
X
K -3
X
X
T --I
RC-23
DD-1
RC-54
AA-1
GG-4
GG-4
F -4
F -4
DD-7
X
X
X
DD-7
X
X
DD-7
X
X
DD-7
X
X
T -4
DD-7
GA-9
F -3
RC-2
RC-2
K -3
F -3
RC-19
AA-6
AA-6
SB
ZCL
ZCL
SS
SS
ZCL
SS
SS
ZCL
SS
CTL
CTL
CTL
SS
SS
c'rL
SCL
DCL
DCL
DCL
DeL
DCL
DCL
DCL
DCL
DCL
DCL
DCL
DOL
DCL
CTL
CTL
CTL
CTL
SS
SS
CTL
OTL
CTL
CTL
OTL
STAGE
NAME
EP
EP'
EP1
EP2
EP3
EP3C
EP4
EP4'
EP5
(1, 2) EPF
(3, 4) EPF
EPG
EPM
EPMA
EPP
EPp1
EPP2
EPFM
EPR
EPS
EPX
EPX'
EPZ
EPZC
ER
ERA
ERAZ
(1, 2) ERF
(3, 4) ERF
ERK
ES
(1)
ES
( 2)
ES
(3)
ES
( 4)
ES
ESA
ESB1
ESCG
ESD
(1 , 2) ESF
( 3, 4) ESF
ESI1
ESI2
ESI3
ESIA
ESK
ESZ
ESz1
ESZA
EZ
EZB2
EZB5.
C-173
CAGE
TYPE
F -3
RC-19
DD-7
DD-7
T -4
RC-16
F -3
RC-11
GG-28
X
X
AA-11
T -4
DD-7
T -4
DD-7
DD-7
X
RC-14
T -4
DD-4
RC-9
F -3
RC-11
T -4
DD-1
DD-7
X
X
K -3
T -4
T -1
T -1
T -1
T -1
DD-1
DD-1
GA-9
F -3
DD-9
DD-9
AA-11
RC-1
RC-19
AA-16
K -3
AA-2
AA-2
AA--16
F -6
F -2
F -2
CHASSIS
LOCATION
SCL
SCL
DCL
DCL
SCL
SCL
SCL
SCL
SCL
SS
SS
CTL
CTL
CTL
CTL
DCL
DCL
DCL
SCL
CTL
SCL
SCL
CTL
CTL
CTL
CTL
CTL
SS
SS
eTL
CTL
SS
SS
SS
SS
CTL
SCL
OTL
SCL
SS
SS
SCL
SCL
SCL
SOL
CTL
SCL
SCL
SCL
CTL
CTL
CTL
STAGE
NAME
EZB5'
EZG
FA (1, 2)
FB (1, 2)
FC (1)
FC (2)
FD (1, 2)
FK-1
FK-2
1-1-11
135
179
19
IA9
ICC
ICL
ICP
INV
109
CAGE
TYPE
RC-55
AA-2
DD-14
DD-17
DD-22
RC-45
X
K -13
K -13
00-7
00-28
GG-28
AA-4
DL-1
RC-40
F -2
RC-23
DD-1
AA-3
roc
RC-48
roCK
D -3
IS-1
DK-1
18-3
DK-1
IS-5
DK-1
IS:.. 7
DK-1
IS-9
DK.-1
KB (1)
K -8
KB (2)
K -8
KB (3)
K -8
KB (4)
K -8
KB ( 5)
K -8
KB (6)
K -8
KB ( 7)
K -8
KB (8)
K -8
KB (9)
K -8
KB (10)
K -8
KB (11)
K -8
KB ( 12)
K -8
KBA (1, 2)
DD-14
KBA (3, 4)
DD-14
KBA (5, 6)
DD-14
KBA (7, 8)
DD-14
KBA (9, 10)
DD-14
KBA (11, 12) DD-14
KBR (1, 2)
X
KBR (3, 4)
X
KBR (5, 6)
X
KBR (7, 8)
X
KBR (9, 10)
X
KBR (11, 12) X
M (S1 )
RC-40
M (S1) A
RC-40
CHASSIS
LOCATION
STAGE
NAME
CAGE
TYPE
CHASSIS
LOCATION
CTL
CTL
STL
STL
STL
STL
STL
STL
STL
RIG
10
10
10
10
ZCL
ZCL
ZCL
VAD
M (S2)
M (S2) A
WCC
M9
M'13
M17
M35
M57
MA (1, 2)
MA9
MC (1 )
MC (2)
MC1
MC2
MC3
MC4
MC4L
MC5
MC6
MC?
MC8
MCp1
MCP2
MCX
RC-40
RC-40
STL
STL
10
10
10
10
10
10
8TL
10
STL
STL
0F
0F
0F
0F
rtF
0F
10
CCT
CCT
10
10
10
10
10
ME
MF
(1, 2)
MKD (1)
ML (S1, 2)
MO
MR (S1, 2)
KB
KB
KB
KB
MS
MS'
KB
KB
KB
KB
KB
MSA
MSD
MSI
MSK
KB
MSKA
KB
KB
KB
KB
KB
KB
KB
KB
KB
MSKK
MSKP
MST
MXR
MXR3
MZ
(1)
MZ ( 2)
MZ (A)
MZR
MZT
OTP
OTP1
p115
P11C
p11G
KB
KB
KB
KB
KB
8TL
STL
c-174
X
X
X
X
X
RC-30
K -12
D -3
RC-31
RC-31
00-20
T -1
00-4
DD-7
X
DD-1
DA-1
DD-7
DD-7
RC-14
RC-14
X
j{ -14
RC-39
RC-37
RC-46
K -14
DD-18
F -3
X
DA-5
DD-14
DD-1
K -6
RC-14
C -3
RC-45
T -2
DD-7
RC-16
F -3
F -3
GG-8
DD-7
T -4
RC-45
DD-7
T -2
DA-7
K -3
0F
0F
0F
RIG
RIG
0F
10
STL
STL
STL
10
STL
DCL
DCL
DCL
CCT
DCL
DCL
ZCL
ZCL
ZCL
DCL
VAD
VAD
STL
STL
STL
DCL
DCL
VAD
VAD
MD
MD
MD
STAGE
NAME
PABA
PABA 1
PABS
PABS1
PAC
PAM
PAMD
PAT
PC1
PC2
PC4
PC8
PC16
PCG
PD1
PD1M
PD2
PD2D
PD3
PDA
PDAM
pna
PDM
PDM3
PDMS
PDN
PDND
PDP
PDS
PDT
PDX
PGMD
PIAS
PIMD
PMIO
PMIOD
PM1 ,.
PM2
PM3
PM12
PM22
PM23
PMBT
PMD1
PMD2
PMDR
PMDZ
PMG
PMM
PMP
PMS
CAGE
TYPE
DD-7
DD-7
DD-7
DD-7
T -3
T -1
F -6
T -3
T -3
T -3
T -3
T -3
T -3
GA-7
T -4
RC-1
T -4
F -1
T -1
DD-13
F -1
T -2
GA-6
AA-9
GG-2
T -2
F -1
S -1
T -4
T -4
GG-2
GA-4
RC-17
RC-17
S -1
F -1
T -2
T -1
F -1
GG-6
DD-12
DA-6
T -1
F -4
F -1
GG-2
T -4
GG-1
AA-2
S -1
DD-3
CHASSIS
LOCATION
SB
SB
SB
SB
¢F
SB
CTL
!OF
MD
MD
MD
MD
MD
MD
MD
MD
MD
MD
MD
STAGE
NAME
PPI
PS
PS11
PSA
PSAC
PSG
PSGK
PSIG
PSOC
PT1
PT2
PT3
PT4
PT5
(1, 4) PTR
PI
PZG
B¥!
MD
R1
R1
R1 t l'
R1' 8
R1M
R2
R2
R4
R4
R6
R8
R8
R42
R11
R22
R44
R66
R88
MD
RB
MD
SB
MD
MD
MD
MD
MD
MD
MD
MD
MD
MD
MD
!OF
!OF
MD
RBK
RC
MD
MD
MD
MD
MD
MD
MD
RD
RS
S¢
3 (1)
S (2)
s1
32
34
36
38
SCK
SCK1
MD
MD
MD
MD
MD
MD
MD
C-175
CAGE
TYPE
-_
..
DD-21
GG-1
S -1
DD-1
LL-2
DD-1
K -3
GA-1
GG-1
T -4
GG-22
F -1
S -1
Rc-14
RC-42
X
GA-7
AA-6.
AA-13
T -4
K -4
AA-8
DA-3
AA-6
T-3
AA-6
T -3
AA-6
AA-6
M -2
AA-10
K -4
K -4
K -4
K-4
K -4
AA-14
RC-18
AA-6
F -2
F -1
GG-12
X
X
GG-19
GG-12
GG-12
GG-12
GG-12
RC-16
RC-1
CHASSIS
LOCATION
!OF
!OF
MD
SB
SB
MD
MD
¢F
CCT
SCL
SCL
SCL
SCL
ZCL
SS
RIG
MD
ACC
ACC
RIG
RIG
RIG
RIG
ACC
RIG
ACC
RIG
ACC
ACC
RIG
RIG
RIG
RIG
RIG
RIG
RIG
SB
SB
ACC
RIG
RIG
ACC
3TL
3TL
ACC
ACC
ACC
ACC
ACC
DCR
DCR
STAGE
NAME
SG
SI-1
SI-2
SK1
SK2
SK3
SKBH
SKBK
SM
SMA
SMC
.'
SMG
SRC (1)
SRC (2)
SRC (A)
SSG (S1, 2)
SSK
SSRO
SZK
T91
T1
T1
T2
T2
T2
T4
T4
T6
T8
T1.0
T20
T2.0
T4.0
TB
TC
TC1
TC2
TOO
TG
THY1
THY 2
TK
TS
TSA
TSAL
TSP
TUG
VTB2
VTB5.
VTIC '
ZB52····
CAGE
TYPE
GA;..8
RC-11
X
C -2
RC-52
RC-51
DD-14
K -14
M -1
-A-3
X
AA-1
RC-35
RC-35
R -5
KK-1
RC-23
DK-1
C -1
T -1
T -3
T -3
T'-1
T ..,1
T -3
T -1
T -3
T -1
T -1
T -3
T -3
T -1
T-3
;r -2 .
T -1
T -3
T -3
GG-14
GK-1
RC-46
RC-9
K -3
T -2
AA-1
RC-1
S -1
GG-14
X
X
X
.R
-1
CHASSIS
LOCATION
STAGE
NAME
ZD52
ZR2
ZR5
DCR
MD
DCL
DCR
DCR
DCR
CCT
CCT
DCR
DCR
DCR
DCR
STL
STL
STL
STL
CCT
CCT
CTL
ACC
ACC
TCR
ACC
TCR
TCR
ACC
TCR
ACC
ACC
TCR
TCR
TCR
TCR
TCR
ACC
TCR
TCR
TCR
TCR
VAD
VAD
TCR
TCR
TCR
TCR
TCR
TCR
ZCL
ZCL
ZCL
ZCL
.c-t76
TYPE
CHASSIS
LOCATION
DD-23
R -3
R -3
CTL
ZCL
ZCL
CAGE
1--
R2
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PL.36
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PL.20
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PL.38
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160 K
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330 K
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-90
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B. PTp'o..CLEAR SWITCH
C. PUNCH-CLEAR SWITCH
D. PUNCH-UNIT SWITCH
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6
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7
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6
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OF SWITCH
CONTACT
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V
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ACC. EX..e:. CO...llM +1501 RETURN
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TEST PANEL OPERA TION
PLATE 35
c
85
470 K
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560 K
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68
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430 K
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82 K
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270 K
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160 K
300 US
E~85
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F-2
B-2 DOES NOT USE THE 220 UUF CAPACITOR.
60-US TO ALLOW THE
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8-5 START IS DELAYED APPROXIMATELY
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8
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J.50K
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Section -DCONTENTS
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Non-Re store Bail .....•.............................•....,....
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Skip Interposer Eccentric .•.....••...•.•.•.•....•..••••.••••
Die Section Card stop ...................................... .
Front Card Receiver Shutter Fingers •••••••••••••••••••••••••
Sort Micro Switch .............................•.............
Ca.rd Jam Micro Swi teh ••.•.....•....••....•••...••.•......•. ~
Full Chip Pan Mic~o Switch ..........•.•..••.•.••.••......•.•
Full Receiver Micro Switch •••••.••••••••••••••••••••••••••••
Cam Contacts .••••.......... '.....••..•.....•• '..•.....••.•....
Phenolic Cams ...... '.•........ ".............•.....•.....•.....
Shafts, Gear Trains and Timing ••••••••••••••••••••••••••••••
Clutch and Brake As sembly ... '...,.............•....•.... ,.....•
Single and Three Phase Connections ••••••••••••••••••••••••••
Belt Tension and Machine Speed •.••••••••••••••••••••••••••••
No Card Sensing Plun.ger .................................... .
Brake Potentiometer ................•.....•..•..•.•.....•....
Feed and Eject Roll Tension .......•.•.......................
Empty Feed Magazine Micro Switch ••••••••••••••••••••••••••••
Output Voltage Adjustment •••••••••••••••••••••••••••••••••••
-165 Surge Limit Control ................................... .
D-3
D-3
D-3
D-3
D-4-
D-4
D-4-
D-5
D-5
D-5
D-5
D-5
D-5
D-6
D-6
D-6
D-6
D-7
D-7
D-7
D-7
D-S
D-8
D-S
D-S
D-9
FIGURE DRAWING INDEX
Fig.
Feed Magazine Adjustments ••••••. • • • • • • • • • • • • • • • • • • • • •• 1 ••
Dummy Cam & Pin Lock Adjustments •••••••••••••••••••••• 2
Tower Retract Bail &Eccentric Adjustment •••••••••••••
Non-Restore Bail Adjustment: ••••••••••••••••••••••••••
Set Bar Retract, Skip Interposer Eccentric & Die ••••••
D-10
D-10
D-11
D-11
Card Jam & Sort Micro Switch & Shutter Fingers Adj •••• 6
Clutch & Brake Assembly, Phenolic Cams, Cam Contacts ••
& Main Shaft Adjustments •••••••••••••••••••••••••••• 7S ••
Machine Speed, Belt Tension & Electrical System Adj •••
-D-12
~
Sec ti on Card Stop ........ ~ . . . . . . . . . . . . . . . . . . . . . . . . ..
Printed In U. S. A.
5
D-12
n-13
D-13
UNIVAC 60 & 120 PUNCH & COMPUTER
ADJUSTMENTS
THROAT BLOCK
Fig. 1A
The Throat Knife should have .010 to .020 inch overlap with the Throat Block.
Be sure the Throat Block and Throat Knife are parallel.
THROAT KNIFE
Fig. 1A
The Throat Knife is adjusted to obtain .008 inch clearance between the
Throat Knife and Throat Block. This clearance is obtained as follows:
1.
Loosen set screw on the right side of the Throat Knife Assembly.
2.
Turn Throat Knife Adjustment Screw on top of Throat Knife Assembly unMl
.008 inch is obtained.
3. Tighten set screw on side of Throat Knife Assembly.
PICKER KNIFE
Fig. 1B
The Picker Knife is adjusted to obtain a
card.
.005
inch bite on the trailing edge of the
1.
Turn machine until the Card Feed Slide is in full feed position.
2.
Through access slots in Card Feed Slide Guard, loosen the 3 Picker Knifs
set screws.
3. Loosen the 2 Picker Knife Adjustment Screw Lock Nuts.
4.
Adjust Picker Knife for .005 inch height by turning the 2 adjustment screws.
The heads of the adjustment screws must contact the top of the slot in the
Picker Knife. Check for .005 inch height across the width of the Picker Knife.
NOTE:
The Picker Knife has two useable edges and can be inverted when one edge
becomes worn.
CARD FEED SLIDE
Fig. 1B
This adjustment is obtained with the Card Feed Slide Eccentric which is located under
the Card Feed Slide.
D-1
1.
Position the Card Feed Slide in.full restored position.
2.
Place a card in the Feed Magazine and position the card so its trailing edge
is contacting the rear Card Stacking Guides.
3.
Adjust the Card Feed Slide Eccentric to
throw behind trailing edge of the card.
4.
Position the Card Feed Slide in full feed position. Place 'a card in the Feed
Magazine to just contact the Feed Rolls. The Picker Knife must overthrow
the trailing edge of the card with a minimum of .062 inch to insure a positive feed.
ob~in
.031 inch Picker Knife over-
CARD FEED SLIDE SIDE PLAY
Fig. 1C
The Card Feed Slide Side Play is controlled
qy an adjustable Gib.
1.
Loosen 3 set screws under left side of the Feed Magazine.
frammachine) •
(Magazine removed
2.
Adjust 3 screws on left side of Feed Magazine for a minimum Card Feed Slide
Side Play condition.
3.
Check for minimum side play with Card Feed Slide in .full feed and restored
positions.
4.
The Card Feed Slide must be free to fall by its own weight when the Feed
Magazine is tilted.
5.
Secure adjustment
qy tightening 3 set screws under left side of Feed
Magazine~
FEED MAGAZINE ALIGNMENT
Fig. 1
The Feed Magazine is aligned so that cards feeding into the Sensing Section are
sensed in the center of the punched hole.
1.funch a card with alternate 7 and 9 positions punched in the Lower Field.
2. Feed the card into the Sensing Section until the pins in the Lower Sensing
Pin Box indicate sensing of the card has begun.
3.
Gently tap the non-selected pins of the Lower Sensing Pin Box.
NOTE:
Too heavy a blow on the pins could puncture the card and cause a card
jam.
4. Remove the card, check the pimpled card for proper alignment.
5~
, In
case the alignment is not correct, the magazine is to be moved in a direction determined qy the hole nearest the pimpled mark. For ~xample: if the
pimpled mark is nearest the hole on its left, move the Feed Magazine to the
D-2
left. The Feed Magazine is moved, after loosening the 4 Magazine Mounting
Screws, by adjusting the screw and lock nut which extends through the base
casting to the left of the Feed Magazine.
DUMMY CAM
Fig. 2A
1 • No cards in the machine.
2.
Lower Sensing Pin Box bottom dead center.
3. Holding the Pin Lock Mechanism unlatched, cycle the machine manually until
the first sign of pin movement in the Upper Sensing Pin Box is observed;
CAUTION: All Sensing Pins are in a locked position.
4. Gently tap the pins in the Lower Sensing Pin Box while backing off the Machine until all movement just disappears from the pins in the Upper Sensing
Pin Box.
5. Adjust height of DUIIllIIiY
Cam to leave .001 inch clearance between cam surface
and Follower Roll. NOTE: Manually latch the Pin Lock Mechanism to prevent
locking all 540 Upper Set Up Pins.
PIN LOCK TORSION SPRINGS
Fig. 2A
The Pin Lock Torsion Springs are adjusted with approximately 1t turns for tension.
Be sure spring is free.
PIN LOCK ECCENTRIC
1.
Lower Sensing Pin Box at bottom dead center.
2.
Adjust Pin Lock Eccentric to obtain a minimum passing clearance with the Pin
Lock Mechanism Locking Extension, as .shownin 2B •
. 3.
The Lower Sensing. Pins should remain fr·ee, unlatched, when the Lower Pin Box
is raised and no card is sensed, as shown in 20.
SENSING SWITCH BOX
Fig. 30
A selected Upper Sensing Pin must just contact its corresponding Sensing Switch Box
Intermediate Sensing Pin at 301 0 • This timing is obtained by shimming the Sensing
Switoh Box using Laminated Shims #1100101 & #1100102.
1.
Feed a card with "0" positions punched Upper Field columns 1 through 45 and
"9", positions punched Lower Field columns 46 through 90, manually into the
machine.
D-3
2.
Observe when the selected Upper Sensing Pins just contact their corresponding Sensing Switch Box Intermediate Sensing Pins. The machine timing
dial must read 301 0
3.
To obtain condition described in Paragraph 2 above, raise or lower the
Sensing Switch Box by removing or inserting shims under the Switch Box
Mounting Rails.
'?
NOTE:
Check all 4 corners of the Sensing Switch Box, Columns 1,45,46
and 90.
TOWER RETRACT BAIL AND ECCENTRIC
Fig. 3
1. Machine on low part of Tower Retract Cam.
2. Adjust clamp on Retract Bail Shaft so bail just contacts all Actuator
Retract Links, as shown in 3A.
3.
Adjust Tower Retract Link Eccentric to give approximately .030 inch overthrow on Non-Reset Latch as shown in 3B.
4.
Turn machine to high part of Retract Cam as shown in Figure 4. Check to see
that the Actuator Interposer Assembly does not limit motion of the Actuator
Retract Links as shown in 4A. If limit occurs, increase the gap on the NonReset Latch.
5.
Check to be sure the Interposer Assembly relatches with overthrow.
NON-RESTORE BAIL
Fig. 4
1. Manually release several Non-Restore Actuator Interposer Assemblies.
2.
With Reset Solenoids normal adjust Non-Restore Bail C~amp for .030 inch
clearance above Non.,.Restore Actuator Interposer Assembly as show in 4B.
3.
Check that the Non-Restore Actuator Interposer Assembly does not limit when
Reset Solenoid is fully operative.
SET BAR RETRACT ECCENTRIC
Fig. 5A
1.
Turn machine to the.high part of the Set Bar Section Retract Cam.
2.
Adjust Eccentric to Retract the Lock Slides in the Set Bar Section within
.005 inch of a limit.
D-4
SKIP INTERPOSER ECCENTRIC
Fig. 5B
1. Hold the Skip Interposer in an operative condition while the machine is on
the high part of the Set Bar Section Retract Cam.
2.
Adjust Eccentric on Skip Interposer so there is .005 inch clearance between
Stud and Skip Interposer.
DIE SECTION CARD STOP
Fig. 5C
1.
Turn machine to the high part of the Die Section Card Stop Cam.
2.
Position and secure the 2 Card Stop Operating Arms on the Card Stop
Operating Shaft to open the Card Stops .025 inch below the Punching Chamber.
3.
Check to be sure Card Stops close evenly when turning machine to low part
of Die Section Card Stop Cam.
FRONT CARD RECEIVER SHUTTER FINGERS
Fig. 6A & 6B
1. Hold Shutter Finger Shaft in a fully operated
po~ition.
2.
Tip of Shutter Fingers should be set .750 inch above plane of card travel.
3.
Set Limit Eccentric so that Shutter Fingers close slightly below plane of
card travel
SORT MICRO SWITCH
Fig. 6
The Micro Switch should be fully operated when the Front Receiver Shutter Fingers
are fully opened.
CARD JAM MICRO SWITCH
Fig. 6
A oard under either Card Jam Micro Switch Plunger, when the Set Bar Section is at its
low limit, should fully operate the Micro Switoh.
FULL CHIP PAN MICRO SWITCH
3/4 Full Chip Pan should fully operate Full Chip Pan Micro Switch.
D-5
(Switch is
located under Chip Pan).
FULL RECEIVER MICRO SWITCH
Full Receiver should fully operate Receiver Micro Switches.
Card Receivers).
(Switch located under
CAM CONTACTS
Fig. 7A
Adjust Cam Contacts for .025 inch clearance when on the low part of the Phenolic Cams.
PHENOLIC CAMS
Fig. 7
There are -j 4 Phenolic Cams with 7 cams on the Front Main Shaft and 7 cams on the Rear
Main Shaft. The cams are not keyed but held in place by pressure exerted by the
Phenolic Cam Adjustment Nut. Any of the 7 cams on the Shaft may be adjusted by
loosening the Phenolic Cam Adjustment Nut and turning the Phenolic Cams by hand. The
Timing Adjustments for the 14 cams are as follows:
CAM
A
B
C
D
E
F
G
H
I
J
K
L
M
N
NAME
MAKE
BREAK
Calc. Start
Select
Ready
Reproduce Set
'Reproduce Clear and
Sort Storage
Sort Pocket
Count
Skip Pulse
Skip Cycle
Skip Reset
Relay Reset
Trip Reset
Clutch Start
Clutch Stop
334 0
324 0
1340
89 0
30 0
200 0
280 0
280 0
334 0
139 0
350 0
1400
287 0
1330
75 0
114 0
290 0
280
70 0
235 0
46 0
196 0
73 0
94 0
1310
75 0
116 0
214 0.
APPRO!.
Cam Nisadjusted to stop the Punch between 2680 and 275 0
SHAFTS, GEAR TRAINS AND TIMING
Fig •. 7
The Clutch controls the cycling of the Punch. The shaft coupled to the Clutch is
called the Line Shaft. All mechanical motion of the Punch is driven from the Line
Shaft. There are two basic shafts which are called Front and Rear Main Shafts. All
Punch Timing is based on the Front Main Shaft. The Rear Main Shaft.Dial reads 180 0
D-6
when the Front Main Shaft Dial reads 0°. The Front Main Shaft controls the Feed
Magazine Feed, Lower Sensing Pin Box vertical motion, Upper Sensing Pin Box Card Stop
and Retract and Tower Retraction. The Re.ar Main Shaft controls the Tower Rod and Set
Bar Section vertical motion, Set Bar Section Retract, Stripper Plate Motion and
Punching Chamber Card Stop.
The Feed Rolls, Intermediate Feed Rolls and Eject Rolls are driven direotly from the
Line Shaft. There is no timing involved in their operation.
CLUTCH AND BRAKE ASSEMBLY
Fig. 7
The following procedure must be used when installing a Clutch and Brake Assembly:
1.
Loosen the Clutch Field Housing Mounting Screws so that the
Housing moves freely.
2.
Remove Male Coupling.
3. Mount the Assembly
Clu~ch
Field
in the base.
4.
Attach Male Coupling and Female Coupling and position assembly with .025
inch clearance between Coupling and Drive Coupling. This clearance is obtained b.1 use of shims between Casting and Clutch Mounting Bracket.
5.
Three.oo8 inoh Shims should be equally spaced about the Clutch Field Housing •
. 6.
The Clutch Field Housing Mounting Screws should be tightened and the
inch Shims removed.
.008
SINGLE AND THREE PHASE CONNECTIONS
Fig. 8
1.
Single and Three Phase Connections are as shown in Figure 8A. Section A of
the Manual shows 5 5,Ystems but they must be either Single or Three Phase.
BELT TENSION AND MACHINE SPEED
Fig. 8
1. Belt Tension is obtained through adjustment of the M9tor Hanger Bolt.
2.
Machine Speed of either 150 CPM or 125 CPM is obtained b.1 the proper Flywheel and Pulley.
NO CARD SENSING PLUNGER
1.
No cards in machine.
D-7
2.
Turn machine until Lower Sensing Pin Box is top dead center.
3. Adjust No Card Sensing Operating
Arm to fully operate Micro Switch.
(Switch is located on left side of Base Casting).
4. Adjust Limit Arm to rest against Upper Pin Box Casting. This Limit
Arm
prevents Plunger from positioning itself out of its Guide Hole in the Card
Chamber.
BRAKE POTENTIOMETER
Adjust Potentiometer to operate Brake sufficiently to stop the Punch.
should be sufficient.
One second
FEED AND EJECT ROLL TENSION
Adjust Tension Springs on both sides of roll for an even and heavy pull on the card.
EMPTY FEED MAGAZINE MICRO SWITCH
Adjust the Micro Switch to fully operate when cards and Card Weight are placed in
the Feed Magazine.
OUTPUT VOLTAGE ADJUSTMENT
Fig. 9
The Transformer Primary Windings for both filament and D. C. supplies have an
auxiliary winding which permits closer adjustment of the output voltage on the
secondary side. All Transformer Primaries are numbered similarly, therefore, any
Transformer Adjustment, filament or D.C. can be made according to the sketch.
1.
The line voltage should first be measured and then the Transformer Primaries
may be connected using Figure 9 as a guide. Same corrections may be necessary to offset Transformer variations.
2.
When it is not necessary to use Terminals. #5 or #6J leave one end of the
Jumper Wire connected to Tap #5 and #6 and the other to a Tap not being
used for the line. CAUTION: Never connect the Jumper Wire from Terminal
#5 to #6.
3. The filament voltages should
be 6.3 volts.:!:. .2 volts at the chassis male
contacts or at the socket of the Rectifier or Thyratron Tube requiring a 6.3
volt filament supply. The Rectifier Tubes requiring a 2.5 volt filament
supply should have 2.5 volts.:!:. .01 volts at their socket.
4. No adjustment should be attempted without the use of a low scale A.C. meter
of ~ accuracy or better since the usual accuracy of the field service meters
is not better than ~.
.
.
The D.C. voltages should be adjusted within
allowed 1~.
D-8
2% except
-60 V.D.C. which is
-165 SURGE LIMIT CONTROL
Fig. 10
The control circuit mounted at the top of the -165 V. Capacitor Assembly is for the
purpose of eliminating overloads which would otherwise be present on the EL3C Rectifier Tube, when the filter capacitor ~ank charges.
At the instant T-22 becomes energized, charging current flows to capacitor C203,
through Resistors R201, R202 and R203. These Resistors limit the current flow to
a safe value for the tube.
As the -165 V. line on the output of F219 increases its voltage in a negative direction, R2CJ7 passes current to C201, charging same. As the charge reaches the voltage required to operate K209, the relay closes, and shorts out R203. At this time,
an increase current flows through R201 and R202, charging the capacitor C203 further.
.
The closing of K209 also starts a new charging time interval when contacts 7 and 8
close. This permits C202 to be charged through R208. K210 then operates. Contacts 3 and 5 (paralleled) and 4 and 6 (paralleled) then short out R201 and R202,
allowing full current charge of capacitor bank C203.
K208 is used to discharge C201 and C202 through R20t and R205 so that full charging
time is available in the following charging cycle, should it follow immediately.
These circuits are checked as follows:
1.
All relay contacts should be clean and have proper wiping action.
must make very good contact.
2.
Resistors R201, R202, R203, R2CJ7 and R208 should be checked.
3.
Timing of K209 and K210 should be checked, and if found to be short, 0201
and 0202 should be changed. K209 should pull in approximately .2 seconds
after T-22 is energized. K210 should pull in .9 seconds after K209 closes.
D-9
They
AG.IA
FIG. I
PUNCH BASE
CASTING
FEED MAGAZINE
ALIGNMENT ADJUSTMENT
SCREW
THROAT KNIFE
RELEASE LEVER
PICKER KNIFE
SET SCREWS
FEED
MAGAZINE
ADJUSTMENTS
FIG. \
Q
(3)
.031 CARD
ADJUSTMENT
SCREW
~
·?~~L
-DO'
BRASS
PIN
04---
.;
@
SET
SCREW
GIS
CARD FEED SLIDE
FULLY RESTORED
FIG.IC
CARD FEED SLIDE
IN FULL FEED POSITION
2A
2B
.....f--DU~IMY CAM
ADJUST HEIGHT
TO OBTAIN .001
DIMENSION
DUMMY CAM a PIN LOCK
ADJUSTMENTS
FJG.2
0-10
2C
oI
- II
-
I
~,
_
I
NON-RESTORE '
BAIL ADJUSTMENT
FIG. 4
TOWER RETRACT BAIL
a
ECCENTRIC ADJUSTMENT
FIG. 3
SKIP INTERPOSER
MACHINE
ONTHE
HIGH
PART Of
DIE SECTION
CARD STOP CAM
ADJUST HERE
CL[~ANCE
SET BAR RETRACT , SKIP
INTERPOSER ECCENTRIC
DIE SECTION CARD STOP
a.
FIG . 5
r
~STOP
~
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\p-U
;::fflCl
~
l>
Z r ,-.
-oc
Zra
.
'~
I~
~6:J:
l>Cl\P
"'TI
Gi
-.J
"l>tD
-l~~
l>- ::><
OCl rTl
<..l>
C;::l>
(/)Cl(/)
-lo(/)
;::zrTl
rTl-l;::
Zl>tD
-lClr
(/)-l-<
(/) -
.1
oI
VI
v'
THREE
--- PHASE
6
r
or
,,0
..,""
~~
~~
oZ~
~5
",,,,,
~
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-<
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=*
t
.
2
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J
PREVENTIVE MAINTENANCE
for the
ELECTRONIC COMPUTER
UNIVAC 60& 120
SECTION E
-;;j/IIT
-
DIVISION
OF SPERRY RAND CORPORATION -
315 FOURTH AVBNUE
NEW YORK, N. Y.
FOREWORD
The preventive maintenance section of this manual is designed
to establish a standard scheduled preventive maintenance procedure for the Electronic Computer Univac 60 & 120.
Punch
The Sensing and Punching Machine Inspection and LUbrication
Procedure should be exercised every 30 days or after 350 hours
usage, whichever comes first. This ordinarily would be performed
during the Computer Corrective Inspection Period.
Computer
The intervals of scheduled maintenance for the Computer section
are classified into three periods, Collective, Corrective and
Connective.
The Collective inspection is scheduled bi-weekly as a rapid
check to insure proper basic Computer operation.
The Corrective inspection is scheduled monthly as a ~omplete
check on circuits and voltages required to give optimum machine
performance.
The Connective inspection is scheduled semi-annually as a check
of all associated components and terminals for electrical as
well as mechanical fitness.
The General inspectIon is a visual check on components and
wiring as bhanges are necessitated and should be included
during each of the Collective, Corrective and Connective
inspections.
ELECTRONIC COMPUTER
UNIVAC
(jJ & 120
CONTENTS
Foreword
UNIVAC EIJ & 120 PUNCH, PREVENTIVE MAINTENANCE PROCEDURE ••••••• E-1 - E-4
Cleaning ••••••••••••••••••••••••••••••••••••••••••••••••• E-1
Inspection Check List •••••••••.•••••.••.•..•••..•••••.... E-1
Lubrication. ~ ...........•...•....•......•..•.............
UNIVAC EIJ & 120 COMPUTER, PREVENTIVE MAINTENANCE PROCEDURE ••••
Bi-Weekly (Collective) •••••••••••••••••••••••••••••••••••
Monthly (Corrective) •••••••••••••••••••••••••••••••••••••
Semi-Annual ( Connective) •••••••••••••••••••••••••••••••••
General Inspection ..•...••..........•....................
Preventive Maintenance Sticker •••••••••••••••••••••••••••
Te at
Pro~am •••••••••••••••••••••• '•••••••••••••••••••••••
E-3
E-5 - E-17
E-5
E-5
E-8
E-9
E-12
E-13
Selector Chart Explanation ••••••••••••••••••••••••••••••• E-15
PLATE DRAWING INDEX
Lubricating Guide
Punch Base (Front View)........................................
Punch Base (Lower Left Side)..................................
Punch Base (Lower Right Side).................................
Upper and Lower Sensing Pin Box (Front View)..................
Upper and Lower Sensing Pin Box (Rear View)...................
Set Bar Section and Die Section (Front View)..................
Set Bar Section and Die Section (Rear View)...................
Punch Tower (Left Side) •••••••••••••••••••••••••••••••••••••••
Plugboard Depressor Mechanism.................................
Plate
1E
2E
~
~~
5E
6E
?ESE
9E
UNIVAC 60 & 120 PUNCH
PREVENTIVE MAINTENANCE PROCEDURE
Frequency:
Every 30 days or 350 hours of usage, whichever comes first.
Machine Covers
Remove covers from machine and put them in a convenient place so that the operators
or personnel in the Tabulating Room will not trip over them.
Cleaning
Clean the entire machine by removing accumulated dirt, card lint and various substances. Also, remOve displaced grease from all cams, rollers, gears and bearings.
The entire machine must be cleaned throughout before lubrication is started.
InsEeciion Check List
1. Check Motor Belt Tension and Pulley Alignment.
2.
Check Cam Contact gap for .025 inch.
3.
Check Phenolic Cam Timings using an Ohm Meter to check Make and Break
continuity on cam contacts.
Front Shaft
-Cam
-Make
Break
Cam
A
B
C
D
E
F
3'34 0
324 0
134 0
89 0
334 0
139 0
350 0
30 0
200 0
280 0
280 0
70 0
235 0
46°
H
I
.G
*
J
K
L
M
N
-Make
140
0
287 0
133 0
75 0
114 0
290 0
* 28°
Break
196°
73 0
94 0
1310
75 0
116°
*214°
Cam N is adjusted to stop Punch between 2680 and 275°.
4.
Check Set Bar Section retract, All Set Bars must retract by 282°. At
full retrp.ct, 3020 to 313° , Retract Bar must not lim1 t.
5.
Check Upper Sensing Pin Box Retract, all Upper Sensing Pins must retra,ctby 283°. At full retract, 2910 to 345°, Retract Bar must not limit.
6.
Check Sensing Switch Box ~im1ng. Selected Upper Sensing Pins must contact
Sensing Switch Box Intermediate Pins at 301°.
7.
(a)
(b)
(c)
I(d)
Remove Upper Sensing Pin Box and check for broken Cell Plate Screws.
Check for sticky slides.
Check for binds in card stop action.
Check Comb Springs for wear and broken comb tines.
E-1
8.
(a)
(b)
9.
(a)
(b)
Check Set Bar Section Comb Springs for wear and broken comb tines.
This can be checked with Upper Sensing Pin Box removed. Remove Comb
Spring protecting plate and check Comb Springs.
Check for sticky slides.
Check clearance between Set Bar Section and Tower Rods. Maximum. clearance
.030 inch.
Check set up of Set Bar Section for set bar latching overthrow.
10. Check Die Section Card Stops.
(a)
(b)
(c)
Card Stops must not bottom.
Must open even and .025 inch below bottom surface of die plate.
Must not bind.
11. Check Micro Switch Operation.
(a)
(b)
(c)
(d)
(e)
Empty Feed Magazine Micro Switch.
No card in Sensing Micro Switch.
Card Jam Micro Switches.
Full Chip Pan Micro Switch.
Full Receiver Micro Switches.
12. Check Card Feed l>1agazine.
(a)
(b)
(c)
(d)
(e)
Picker Knife Adjustment .0045 inch go - .006 inch no go.
Throat Knife Adjustment .008 inch go - .010 inch no go.
Throat Knife release.
Card Feed Slide Side Play.
Magazine Alignment.
13. Check Clutch and Brake.
(a)
(b)
.025 inch to .035 inch clearance between Coupling and Drive Coupling.
Machine must stop between 2680 and 275°. / J
"
14. Check all linkage for wear and all rolls for binds.
15. Check Non Restore Mechanism.
(a)
(b)
(c)
Reset Solenoids energized. Non Restore Actuator Interposer Assemblies
must have maximum latching overthrow and not limit.
Reset Sol.enoids de-energized. Non Restore Actuators in a reset position
must have .022 inch to .030 inch between N0n Restore Bail and Non Restore
Actuator Interposer Assemblies.
Non R,estore Actuators in a tripped position must have .010 inch to .015
inch between Non Restore Bail and Non Restore Actuator Interposer Assemblies.
16., Check Set Up Actuators and Mechanism.
Set Up Actuators in a tripped position must have .031 inch + .010 inch
clearanc;:e between Rocker Arms and Interposer Assemblies.
Rocker Arms and Interposer Assemblies must align.
Set Up Actuators, in a latched .position, must have passing clearance
between Rocker Arm and Interposer Assemblies.
Machine dial reading 76° to 81°. Set Up Actuator Interposer Assemblies
must have maximum latching overthrow and not limit.
E-2
(e)
Check Set Hold Latch for proper bite and latching overthrow.
17· Machine dial reading 302° to 313°. When the Skip Interposer is in an
operative position (Skip Solenoid energized) there must be
clearance between Skip Interposer and Stud.
.005 inch
18. Check Clear and Unit Switch Operation.
19.
Check Card Release and Unit Switch Operation.
20.
Check Skip Cycle Operation.
21.
Check Non Restore Operation.
22.
Check Sort Operation.
23. Check Reproduce Clear Operation.
Lubrication
After the machine has beenthorougbly cleaned and generally inspected, it should be
lubricated with lubricants prescribed for the various parts that appear in the
plate drawings 1E through SE.
Illustrations are provided with the intent that you familiarize yourself with the
parts that require lubrication. The type of lubricants to be used is identified by
code numbers on each plate drawing. The letter S included with same code numbers
indicates that the lubricant should be applied as a Spray.
While it would be impossible to illustrate each part that requires lubrication,
sufficient units of the machine are shown to establish identity of parts to be
oiled or greased within the area of the unit.
The numbers 1, 2 and 3 on each illustration represent the code number of the three
types of oil. Code #4 and #5 represent the type of grease to be used.
In all instances where parts are not illustrated or where parts are shown with
the absense of a eode number, it is assumed that the serviceman will use his own
good judgment in selecting one of the five following types of lubricant prescribed
for use on Tabulating equipment. This may easily be determined by observing the
type of lubricant used on parts that are illustrated in the various drawings.
TX]es of Lubricant to Use
Three types of oil and two types of grease have been selected as standard for
purpose of lubricating Tabulating equipment. Under no circumstances are lubricants
other than those five standard types to be used. Experiments have proved that
satisfactory lubrication results have been obtained using the following three types
of oil and two types of grease.
CODE #.1
Velocite "Eff Oil - SXmbol #§VC-325L - To be used on all light mechanisms operating
with extremely close tolerances.
E-3
CODE =JIg
3
18 White Industrial Oil - To be used on Shaft Casting Bearings
"in diameter or lesR or parts operating under light friction.
CODE #3
Rubrex Medium Oil - SYmbol #§VC-113L - To be used on Pivot Points, Hubs and general
Shaft Casting Bearings with a diameter 7/16" and above or parts operating under
excessive friction.
CODE
#+
Lubriplate #130AA Grease - Symbol #§YC-370L - To be used on all Gears, Follower Rolls,
Cams and sliding surfaces not lubricated with above oils.
CODE #5
Gargoyle BRB #± Grease - SYmbol #$VC-146L - To be used for machines equipped with a
Transmission.
When lubricating the machine, it is suggested that you establish a ~stematic method
of lubrication. The machine should be completely lubricated with each one of the five
types of lubricants.
Start lubricating the machine by using Grease ~ on all parts listed
illustrations; then proceed bw using Oil #3 first, then Oil~. Use
all light mechanisms operating with extremely close tolerances. Old
must be removed from parts that require grease; otherwise, the newly
will not stick to the parts.
and shown in the
Oil ~ last for
grease and oil
applied grease
The purpose of this machine outline should not be misconstrued. Its purpose is to aid
you in formulating a habit of systematically lubricating the entire machine by beginning with one section and proceeding until the machine is completely lubricated. The
serviceman should follow this theoretical machine procedure outline until such time as
he is thoroughly familiar with the proeedure and can systematically lubricate the
entire machinswithout its use.
E-4
UNIVAC 60 & 120 COMPUTER
PREVENTIVE MAINTENANCE PROCEDURE
BI-WEEKLY (COLLECTIVE)
Inspection Time -
1t Hours
Clean Dust Filters
Run Test Problem to check Input-Output, Storage, Shifts, Elements, Processes
and Decimals. This Program should run vi thout repeat for 30 Minutes ..
Check Filament DC return Resistors for Burn-Out or Discoloration. These
Resistors are located on a Terminal behind the Pover Supply and are easily
accessible once the Storage Door is opened. These Resistors burn-out due to
Filament Cathode short which leaves the Filament Supply Floating
Resistors within the cages vhen seriously discolored should be checked for
proper value.
MONTHLY (CORRECTIVE)
Inspection Time - 3 Hours
DC Voltages
1. Adjustment:
The DC Voltages should be set with the line voltage at its normal
value. If a regulator is not used then the DC Voltages should be
changed by the peroentage that the line voltage is off. For example,
if the line is temporarily low by 3.% then all the DC Voltages could
be expected also to be 3% low when properly adjusted.. However, if
the line is observed to always be slightly low by a line voltage
recording an adjus~ent couldJJe made for the normal DC Voltages.
2. Meter Accuracy:
a. The Computer Panel Meter should be calibrated at least onoe a
year against a standard meter of at least 0.5% accuracy. The
Panel Meter should indicate within! 3%.
b.
The Computer Panel Meter maybe used for adjustment of the
voltages or a portable meter which is calibrated every 30 days
against the standard meter,at the exact voltage pOints to be .
usea, may be employed. An Oscilloscope may be used to measure
the ripple by using the peak-to-peak readings. Excessive ripple
is usually an indioation of lowering of the effective capacity of
the filter units. It should be noted, however, that the surge
protective relays must be closed to shunt out the surge resistors
in the pOwer supplies.
For Example: The -165V supply pulls in Relay 209 which shunts
out R203, then Relay 210 pulls in to shunt out R201 and R202 so
that C203 is now returned directly to Gnd.
E-5
3.
DC Voltage Levels and Ripple:
SUPPLY
MAX. RIPPLE R.M.S.
NOMINAL
PEAK-TO-PEAK
a.
+150V
+2 V
1.5 V
3.6 V
b.
+ 75V
+2 V
O.35V
0.B5V
c.
- 15V
+1 V
0.06V
0.15
d.
- 40V
+1 V
o.on
0.17
e.
- 60V
+2 V
0.9 V
2.2
f.
- 90v
+2 v***
O.55V
1 .4 V
g.
-150V
+2 V
O.B V
2.0
h.
-165V
+2 v*
O.OBV
0.2 V
i.
-375V
-
+10v
O.B V
2.0
j.
-400V
(25V Bias
Supply)
+2 v**
0.3 V
0.73
~--.,-,,~.
* The -165 Volt level is given for a maximum number of storage bits
set. The nominal with all storages cleared is -167 Volts for the
Univac 60 and -169 Volts for the Univac 120.
** Note that the -400 Volt supply is measured with respect to the -375
Volts supply and not to ground.
*** The B2 and B5 levels should be + 2 volts within the -90 volt supply.
AC Voltages
1.
With nominal line voltage the heater voltages should be within the
following limits:
a.
All Chassis (at the chassis male contacts) 6.3V.:!:. 0.2V
b.
All 6.3 volt tubes mounted in the frame 6.3V + 0.2V
c.
All 6.3 vol trectifiers (measured at the socket) 6. 3V .:!:. O. 2V
d.
All 2.5V rectifiers
& thyratrons (measured at the socket) 2.5V
Filament Supply
1. Measure at chassis clips unless otherwise specified.
a.
ABC - Acc. 4A to 11A incl., 1M to 8M incl.
E-6
+
0.1V
2.
b.
DEF - Acc.1A to 3A incl., 9M to 11M incl., SB, CTL, 0F, CCT, RIG,
MD, OCL-'i & OCL-2.
c.
GHI - SS1 to SS10 incl., SC1, ZCL, DCL, DCR, TCR.
d.
K1M - I01 to IO'iO incl., KBI to KB4 incl., VAD, STL1 to STL6 incl.
e.
NO - STL1
f.
PQ - I01 to I010 incl.
g.
RS - STL1 to STL6 incl.
h.
T-21 - Rectifier Tubes (See Print 1940237) Measure at tube socli:et.
i.
T-28 - -40V supply, select thyratrons (See Print 1940249) Measure
a t tube socket.
t~
•
STL6 incl., STA1 to STA6, (6AS7's) incl., VAD.
Suggested Check Points:
Filament
Trans.
Chassis
CliE Connection
ABC
T26A
5A
6-8, 8-10
DEF
T26B
3A
6-8, 8-10
GHI
T26C
SS4
45-47, 47-49
K1M
T26D
ST1
40-42, 42-44
NO
T27
STL
36-38
PQ
T27
IO
12-14
RS
T27
STL
2-4
Full Chip Pan Detector Operation Check
Card Jam Device Operation Check
Input-Output Recovery Circuit
The Input-Output Recovery Circuit may be checked by observing the operation
of stage ICL in the ZCL chassis. Each and every operation of DEA operates
stage rCL, which in turil generates the voltage to return the Input-Output
. lines to normal through the assigned diodes (left side of (2) C09) i~ the
individual IO chassis. This discharges all the gate grids to prevent any
undesirable Alpha-Check indications while the Keyboard biases are changing.
Check this on Cage Pin #7 of L1-30f all IO Chassis.
Keyboard Bias Reset Circuit
This may be checked by observing the cathode of 0LD( 1 & 2) in the 0'F
chassis. All keyboard bias lines are rapidly returned to normal by this
circuit.
E-7
Storage Read Out Blocking Bias
This has been incorporated to prevent false Alpha-Check indications during the
zeroizing of the selected storage. Its operation is controlled from stage EZ,
CTL chassis, and maybe observed on the cathode of stage SKBK, CCT chassis.
Storage Hold and Clear
Each Storage Clear Line of storages S1 through S12 shall be observed with
Oscilloscope for proper operation as shown on Dwg. 1940409.
Zero Check Line
This is to be checked. through cage pin "one" of stage 09C in Zero Factor chassis.
This is a grid point and should operate from approximately -25 Volts to slightly
above zero. The operation maybe checked as follows:
1.
Select N1 as V1 of Step 1 - plug for a one in Column 1A in the Accumulator.
2.
Test counter set to pre-shift zero.
3.
Observe the grid point, allowing shifting one position at a time until
the digit reaches Column 11A. While the digit remains in Columns 1A
through 10A, the grid should remain slightly above zero. When the digit
reaches Column 11A, the grid voltage will change to -25 Volts.
Keiboard Bias Detector Circuit
This is to be checked by removing the element call line from a normal step
and observing. the stopping of the step on the CX pulse for the RIG cycle
associated with that element registration.
Plugboard Mechanism Check
SEMI-ANNUAL (CONNECTIVE)
Inspection Time - 8 Hours
Relays
1 •. Relay contacts should be dusted whenever it is necessary to remove their
dust covers or otherwis,e inspect them. For those which are covered,
this should be done at least once every six months. Those which have no
., dust covers should be dusted at least every 60 days. The movable contacts
of relays should never be adjusted : if this contact spring requires .,
adjustment the relay is to be replaced.
2.
The mercury plunger type relays in the 'power control section should be
che.cked to see th,at the glass tube is at the correct height ,within the
operating poil. This height is indicated by a mark on the tube.
Screw Type Terminals
All screw type termirials should be checked at least once every six months to
E-8
insure that they are mechanically tight. A loose terminal in a high
current circuit can cause burning of the terminal block if allowed to
continue.
Installation Test Board Operation
Every six (6) months each machine shall be checked with the installation
test boards; this is to include Alpha-Check of Input-Output Section and
"Service Boards" test as described in the Installation Procedure. The
Step, Storage, and Branchi~~ Program should be run with simulated high
and low line conditions (+8%). This requires one external jumper on the
VAD chassis. (Lug #34 to-Lug #3).
Switches and Lights Check
All switches, lights, etc. shall be tested for proper operation.
Spare Chassis Check
All spare chassis shall be checked on related programs of above.
VAD Chassis Setting Check
The Grid Level of the Thyratron #1 (Pin 1 of RC-46 high level * adjustment)
is set to -162 Volts. The grid level of Thyratron #2 (Pin 1 of RC-9 low
level * adjustment) is set according to the relatio~ of +138+E, where E
is the actual meter reading of the -150 volt supply.' If the -150 volts
supply is normal, then the voltage level would be -12 Volts. The operation
of this chassis for voltage fluctuations is checked by blocking the -150
lug to the VAD chassis and supplying an external DC voltage of-150 Volts
to the chassis. This voltage is then varied from -162 to -138. At both
the high and low voltage variations, the relay operated from stage OTP will
de-energize and open the B+ (+150) to the Punching Sensing Unit, Reproduce
transfer relay and light the Voltage Indicator Light on the Control Panel
of the Punching-Sensing Unit. Blo.cking of the -150V lug may be done by
removing the chassis and inserting a strip of paper around the chassis lug
and reinsert!ng the chassis. When the voltage is returned to normal the
relay is res~t by operating the Clear-Punch Switch or ground lug #19 on
the VAD Chassis.
* If a regulator or a Variac is not available at the installation, two 6
Volt lantern batteries may be connected in series aiding to obtain -162
Volts or in series bucking to optain -138 Volts.
GENERAL INSPECTION
Chassis Contacts
When Chassis are removed and any dust is present, the Chassis Contacts and
the frame contacts should be dusted with a typewriter cleaning brush to
remove any dust that might interfere with contact when the Chassis is
reinserted. If the environment should cause any greasy film to accumulate,
this should be removed with a cloth saturated with perchlorethylene. Never
use an abrasive material on the contacts. The black discoloration which
forms on silver is a good conductor; therefore, it ie ,not necessary that the
E-9
material be bright. Both the chassis and frame contacts should be checked for
distortion in a direction which would cause either light pressure or misalignment
when the Chassis is inserted.
Disconnect Contacts (only when disconnects need to be opened)
All disconnect contacts should be inspected visually for.distortion prior to
closing the block, and as the block is closed a light should be used to insure
that a small misalignment does not cause the contact blade to fall outside the
contact springs.
Wiring
During the course of trouble shooting at all times the serviceman should be on
the lookout for possible trouble due to wires under tension which might cause
failure due to pull-out of the wire from the pressure type connector, or
chafing through the insulation to ground against the fr~e. If necessary
these wires can be tied back or taped with "Scotch Electrical" tape to relieve
this condition.
Cage Components
Whenever a cage must be handled a visual inspection should be made for mechanical
shorts or for spacing~ which are so close that a metallic dust particle could
cause a short. This is especially true of the STB-1 cages because of the large
number of components contained and of the construction of the small diodes used.
Excessive bending of these diodes leads should be avoided since the diode will
fracture. A slight spacing is sufficient if a few drops of glyptol are placed
into the spaces.
Chassis Internal Wiring
If a trouble appears and disappears when a cage or tube is moved the Chassis
should be opened and visually inspected for unsoldered or poorly soldered
conne.ctions, broken wires, broken resistors, or shorting of wires.
Punch Actuators'
Actuators should be kept free of dust by keeping the punch covers on at all
times except when actual service of the tower is required. Adjustment of
actuators should never be made in the field since special test equipment is
necessary for this purpose.
Cooling System
The Univac 60-120 Computer Cooling SystemE require that the covers of the
computing unit be kept in place at all times except when actual service is
taking place. These covers are an integral part of the cooling system.
Fan Motors
The fan motor bearings 'are life-time grease packed and should .not require
attention. After a days run,however, the motor housings and bearing ends
should be checked for excessive heating by placing the hand on each motor.
E-10
Marginal Operation
1. At norlDB.l voltages
A measure of the operating oondition of the computer ~~y be obtained
by plugging any program that uses a reasonable part of the capabilities
of the machine, so that instead of branching to "Trip" the oomputer
will continue to calculate by branohing back to the first step. If
this is done with the ''Restart'' not plugged, then the computer should
cyole itself for a period of from at least ten minutes up to eight
hours or more. A line transient may OaUse the computer to stop, how
ever, even though no lDB.rginal condition exists. The point of stopping
each time should be recorded from the Program Test Panel in order to
pin point the common trouble pOint if possible.
2. At high or low line voltage
If no common trouble pOint oan be arrived at, then a slight lowering
or raising of the line voltage by means of the voltage regulator w~ll
sometimes help to lDB.ke the trouble appear frequently enough to be
located with the scope. Should the change in line voltage fail tOlDB.ke
a notioeable differenoe in the frequency of hangups, then the voltage
should be returned to normal.
E-11
PREVENTIVE MAINTENANCE STICKER
MACHINE INSPECTION RECORD
'.
!!!!
DATE
PHASE
:Co llectlve
Corrective
Connective
+150 . ·+75·
D. C~ Supply
-15
-40
-60
-165
-375
--400
D. C. Actual
-90
D. C. Supply
-150
D. C. Actual
" Fil;"""nt
A. ~.
ABC
DEY
GHI
JK
LM
6;3
6.3
6.3
6.3
6.3
-'ctual
'.
Filament A. C.
NO
6.3 ,
PQ
RS
6~3
6.3
T-:-21.
T-~
Actual
REMARKS:
Serrice Technician
REMIllGTON RAND DIVISION
SPERRY RAND CORPORATION
This sticker is to be mounted on the Power Control frame to the left of the meter panel.
The sticker is to be replaced after each collective or bi-weekly inspection. The
date and RTM (running time meter) values should be recorded at each inspection.
The voltage values required should be measured at the Power Supply on TB 110 except
-165 volts and -40 volts which can be measured at the STL chassis. The Filament
voltages are to be measured at the chassis clips except those so designateato be
measured at the tube sockets.
Any variation over + 2 volts between the 90 volt readings and the B2 or B5 voltage
readings should be so noted under remarks.
The sticker is to be
s~gned
by the technician performing the inspection.
E-12
TEST PROGRAM
This test program is designed to check the fundamental circuits of the computer.
All storage digits as well as minus indication are checked.
are checked. All decimals are checked.
The various processes
The following is the sequence of the program.
1.
The V1 of step 1 is N1 (all Relays de-energized).
2. Branch of step 20 fires Select I Thyratron and ener.gizes Relay 1 •
3. The V1 of step 1 is N2 (Relay 1 energized).
4. Branch of step 20 fires Select II Thyratron and energizes Relay 3.
1 de-energized).
5.
(Relay
The V1 of step 1 is N3 (Relay 3 energized).
6. Branch of step 20 fires Select III Thyratron and energizes Relays 5 and 2.
(Relay 3 de-energized).
7.
The V1 of step 1 is N4 (Relay 3 energized).
8. Branch of step 20 fires S.elect I Thyratron and energizes Relay 9.
energized) •
9.
Start to Select step IV (Relay 9 energized).
10. Select IV Thyratron energizes Relay 7.
11.
(Relay 2
(Relays 5, 2
&9
are de.energized).
The V1 of Step 1 is N5 (Relay 7 energized).
12. Branch of step 20 goes to trip and problem is ready to repeat.
energizes Relay 7).
(Trip de-
This program can also be used to check the punching oirouitry. A suggested method
would be as follows.
1.
The + and - branch of step 12 should be wired to COM 1-2 (present
of step 20).
2.
Plug all. storages for Set 1.
3.
Plug storages S1 through S9 on the plugboard to oolumns 1-90.
4.
Plug storage S10 and 8 columns of storage S11 to the zero positions of
columns 1-90.
5.
Plug Clear to Trip instead of Start.
6.
Plug S 7-2 to Set I instead or Trip.
7. Use blank cards.
E-13
+
branoh
8.
Five cards must "be fed for every tower set up actuator to be operated.
NOTE:
In a Univac 60 it would require replugging the punch plugboard in
order to check" all tower actuators; The branch of step 6 would be
plugged to COM 1-2.
E-14
SELECTOR CHART EXPLANATION
1. Relay Contacts
A.
COM 3-1
(1)
This refers to the fact that this position is wired on line 3-1 under
the common position.
B. NS 5-2
(1)
C.
This refers to the fact that this position is wired on line 5-2 under
the non-select position.
S 1-3
(1)
This refers to the fact that this position is wired on line 1-3 under
the select position.
2. ,Relays
A.
P.U. Ry 9
(1)
3.
This refers to the fact that this position is wired to the pick up
of Relay 9.
Select Step
A.
SEL. III
(1)
B.
This refers to the fact that this position is wired to the "IN" hub
of the Select Step III.
P. S. III THY.
(1)
This refers to the fact that this position is wired to the PRQ·3-. SEL.
III bus on the plugboard. This bus represents the plate of the
Select III Thyratren which is fired during a Select III Step.
UNIVAC 60 &.120
SELECTOR CHART NO.:
PUNCHED-CARD ELECTflONIC: COMPUTERS
APPL'ICATION:
TABULATING MACHINES
ELEMENTS
CONST"NT F"CTORS,
CUtU FACTORS:
ELEM
DES II;
,.
NEG. CONT.
.ce
COL POS LTI:F£ ('OC
.1
I
N2
-
.3
N4
-
N5
N6
N7
ACCUMULATOR COLUMNS
10
9
1
3
8
~
7
6
5
7
9
1
I
1
5
"
7
.3
5
9
9
1
~
9
1
1
~
7
7
9
7
9
1
1
~
N23
0
a a
0
a a
0
a a a
N24
2
I
I
h
N15
1
N16
Ie 9
N17
II
N 18
.0
[5l
?
1
1
3
3
9
_
I
I
I
COU;~N
I
...
COr-;ffl(;L
-;:·L'::C TRFR
TGR L INI<:
P leI( UP
POSI 11 ON ANC CotUWII
INOIC~TE
~[L~Y
CON
1
10
9
8
6
7
4
5
3
2
1
A5
8
N28
8
A7
N29
3
A8
N30
3
N31
h
r;
h
9
9
8
3
2 6
N32
0
a
?
3
9
N33
.9
Al0
9
N34
All
N35
0
A12
"36
TI.2.
SELECT
TI.3.
TI.".
D U C E
I I
I I I I
I I I
I I I I I I I I I I I I IIL~jJI I I I
I I I I I I I I I I I I I I I I I I I I I I
T2.
ETC.
COMMON
SEL.
'".
. . ".
NON. SELECT
..
,
"I.E
~
~
~
1.4
12
2
..'2:2
F!-
~
~
13-4
...
14
II II I I I I I
I I I I I I I I
I I I I I J I I
U~l
II I I I I I
I I I I I I I
COhTROL CHART
SELECT • • •
8R ANCH • • •
PROCESS
11i
1ti
~
F3.4
VALUE I
VALUE 2
RE5UL T
TRFR
LINE
•••
•••
•••
PI CX UP
POSI TI OH ANI! CO!.UMN
I NOltA Tf DELAY CONT
SELECT
COM. 1-3
P.S.
THY.
P.S. 2 THY.
53-4
V1
IN
Sel. II
COM 1-1
l> IT
N3
Sel III IN
P.U
1
+ Br. Sten 70
r.nM <_1
COl\i-?
P.U. Ry 1
q
",
!'It.~n
ETC.
NON_ SELECT
COMMON
WJ
NS Ry 2
M3. ETC.
53. ETC.
P.S.I. P. 5 .2.
Rv 3
P.S. 1 THY.
NSl-l
NS 1-7
S 1-3
COM 5-3
P U Rv
iCnN
,,_,
COM ~-?
COM 5-3
4
~
~
16
ELEhlENTS • • • NI. N2.
STORAGE
• • • 51. 52.
PROGRAM SELECTOR • • •
VI
V2
RES.
_1M
~
5·2
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7
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FOR A UNIVAC 60 OM T ~Tl! I'S
23
7 TIIRU 12 INCLUSIVE.
24
25
26
FOR A UNIVAC WITH NL OiE B CHASSIS OMIT STEPS 1
DECIMALS WOULD BE ..EF U OK !eKED 2/1, 8/7, 9/S, 10 9
27
19 & 20. THE FOLLOWING
11/10.
28
29
PLl!G FOR PROGRAM R ~ T, BL ~K CLIP #18 OF SCL CHA SI
CONTINUOUSLY RECYC Em: T IE PUNCH MOTOR IS TURNE
30
A ~ PROGRAM WILL
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31
32
33
34
35
36
37
38
39
III
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52
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READ Y
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LUBRICATION CHART
1.
2.
3..
4
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White Industrial Oil
Modi urn Oll
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NOTE ,
(8)
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( FRONT)
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3
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4.
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(eFt:)
PLATE
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\
\
3
LUBRICATION C!L\RT
1.
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White Industr ial Oil
3.
4.
Medium Oil
Luhr1plate #1)OAA Gr ease
NOTE:
(8) m:J!£Lwith designat ed oil
SET BAR SECTION
a DIE SECTION
(FRONT VIEW)
PLATE
6E
LUBRICATION CHART
1.
2.
3.
4.
Velocite "E" Oil
White Industr ial Oil
Medium Oil
Lubriplate #l30AA Grease
NarE:
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SPRAY with designated oil
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NOTE :
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CLEAN PLUGBOARD
SILVER CONTACTS
WITH
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LUBRICATION CHART
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2.
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White Industr ial Oil
3.
I*,dium Oil
Lubr iplate #130AA Grease
4.
NOTE:
{S)
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PLUGBOARD DEPRESSOR
PLATE
9E
ELECTRONIC COMPUTER
UNIVAC 60& 120
SUPPLEMENT I
CONSTANT VOLTAGE
TRANSFORMER
C.V..T.
-
DIVISION Of SPERRY RAND CORPORATION -
315 FOURTH AVENUE
NEW YORK, N. Y.
FOREWORD
We have standardized on the use of the Sola Constant
Voltage Transformer Regulator. for Univac 60 & 120
Computers. The complete specifications and installation instructions for this C.V.T. Regulator are
explained in the following pages.
These instructions have been prepared in sections
as follows:
Section
Section
Section
Section
Section
AB C DE -
Description & Specifications
Service Technician Instructions
Electrical Contractor Instructions
C. V. T. Service Information
Changes Necessary when Removing C.V.T.
ELEC1RONIC COMPUTER
UNIVAC 60 & 120
CONSTANT VOLTAGE 1RANSFORMER
CONTENTS
Foreword
Plate Drawing Index
DESCRIPTION & SPECIFICATIONS •••••.•••••••••.••••.•••••••••••••••••••••••••••
When Used •.•...••..••.•..••.•.•••••••••••••••••.•••••.••.•••••.•••.••.•••
Electrical Circuits ..•••••••••.•••..••.•..•••.••••.•••.••••••••••..••••••
Where Located .•...••..•...••..••••.•••••.••.•.•••••••..•.•.•••••••.•••••.
Adapters .t'A tf & "'B" ............................................................................................................ "
Al - A2
Al
Al
A2
A2
SERVICE TECHNICIAN I NS1RUCTI ONS •.•••.•••..•..•••••••.••••••••••••••••••...••
Changes - Sensing-Punching Uni t ••••••••••.••••••••••••••••••••••••.•••.••
Servi ce Entrance Box •.•.••••.••••.•.•••••••••••.•••••••••••••.•.••••••
Power Distribution Box ••••••.••.•••••••.••••••••••••••••. " .•••••••••••
Operating Panel Terminal Board TBIO •..•.•.••••.••••.•••••••••••.•••.••
Changes - Electronic Calculator Unit ••••••.•••••.••••.•••••••••••••••••••
Power Control Chassi s Fuse Panel •••••.•.•••.•••••••••••.••••••••••••••
Adapter "'A" .......................................... " ....._.................................................................. .
Adapter ·'B'· .................................................................................................................... .
Bottom Rear Cover ........................................................................................................ .
Parts Ordering ••.....•..•.•.•.••.....•.••••••••••••••••.•.•.•••••••.•••••
Bl - B4
Bl
K.
Bl
B2
B3
B3
B3
B4
B4
B4
ELEC1RICAL CON1RACTOR INS1RUCTIONS •••.•••••••••••••••••••••••••.•••.••••..•• Cl
C. V. T • Specifications •••••••..•.•....•••••.•••••.••.••••.•••..••••.••••. CI
Dl - D3
Dl
DI
Dl
Dl
DI
DI
D2
D2
D2
D2
No Olltput Voltage ..........
Guarantee . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . : . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . • . D2
Li st of Sola Electric Co. Representa ti ves ••...••••••••.•••••••••••••••••• D2
SOLA C. V. T. SERVICE INFORMATION •••...••.••.•.•••••••••.••••••.••••.••.•••.••
Safety Notice .••..•.•..........•...••..•••.•••.••.•••.•••••••••.•••..••••
No 'Routine Maintenance Necessary .•...•.••••.•••••.•••.•••••••••.••••••••.
Check List of Factors Effecting Performance ..•.•..•••••.•••••.•..••••••••
Probable Trouble .................................................................................. " ...................... .
Ca'paci tor Short Test .................................................................................................. .
Capaci tor Open Test ................................................. ., .... .
Damaged Transformer Winding •••••.•.•••••••••••••••••••••••••.••.••••••
Output Voltage Too High ••.•.•.••.•.•.••...•••••••.••••••.•..•••••••.••
Output Voltage Too Low ••••••..•...••.•.•••.••••••.••••••••••.•••.•••••
II
••••••••••••••••••••••••••••••••••••••••••
CHANGES NECESSARY WHEN REMOVING C. V. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electronic Calculating Unit ••••.••••.•••.•••.••••••••••.•••••.•••••••••••
Sensing-Punching Unit •..•.•.••...••.•••••..•.••••••••••••.•.••••.•••••••.
Power Distribution Box ••..•...•.•..••.••.•••••••.•••••..•••••.•..•••••
Service Entrance Box .•••...•.•..•••...••..••••••••.••.••.••••••••••••.
Printed In U. S. A.
1957
El
El
EI
El
El
E2
~
E2
PlATE DRAWING INDEX
FIGURE TITLE
FIG.
PlATE
C.V.T. Assembly
Service Entrance Box Installation
1
2
1
1
Left Rear Base Casting
Wiring - Sensing-Punching Unit
3
4
2
2
Service Entrance Box & Power Distribution Box
5
3
Operating Panel Terminal Board
Power Control Chassis
6
7
4
4
Adapter "A" Installation
Adapter "B" Installation
8
9
5
5
Calculator Crank-Up Schematic with Adapter "A" Included
10
6
Power Supply-Minus Supply Schematic with Adapters "A" &
liB" Included
11
7
Wiring - Power Control In Computer
12
8
Punch-Rear Cover Modification
13
9
C.V.T. Wiring - All Systems
14
10
C.V.T. Top View
C.V.T. Front View
15
16
11
11
C.V.T. Installation Specifications
17
12
18
13
19
13
Power Distribution Box After C.V.T. has been
Power Distribution Box After C.V.T. has been
Single Phase Connections
Removed
Three Phase Connections
Removed
Description & Speci fications
for the
ELECTRONIC COMPUTERS
UNIVAC 60&120
CONSTANT VOLTAGE
TRANSFORMER
SECTION A
,,--::l/II'_._-....,...
...._---_.
' - DIVISION OF $pe IIV IAN D COtPOIAT ION -
31$ FOUR.TH AVENUE
NEW YOR.K. N. Y.
DESCRIPTION and SPECIFICATIONS
When the C.V.T. is installed, it is necessary to change the Computer Power Distribution Wiring and to install two adapters in the Computer section. These changes
will be made by the Service Technician. The actual C.V.T. installation must be
made by a local Electrical Contractor. The C.V.T. is connected to conform with
the customer Power System specifications.
When Used:
Constant Voltage Transformers are used with Univac 60 or 120 when power input varies
more than plus or minus five percent and not more than plus or minus fifteen percent
of one of the listed nominal voltages; 208, 220 or 230 volts. In addition to the
listed nominals, these CV Transformers may be used on nominal input voltages of 240
and 250 volts. The maximum plus tolerance voltage input is 276 volts for either of
these nominals. When the 220 volt tap is employed as being closest to nominal, the
lower limit of regulation is 187 volts. I f the 208 volt tap is used, then the lower
limit is 177 volts.'
In any event, the excursions for the power line, whether steady, semi-steady, varying
or transient in nature, when added together must not exceed the aformentioned limits.
In the event a system varies more than 15% from nominal, i3.ddi tional means of regulation must be employed.
The steady and semi-steady excursions of the power line can be measured and recorded
by commercial line voltage recorders of the disk type. The varying condition can be
measured by roll type recorders of medium-speed paper feed. The transients can be
recorded only on a fast paper feed "Brusht ' , c;>r equivalent, High Speed Pen Recorder.
If the transients are frequent enough, they may be observed and measured on an Oscil,;Joscope.
Electrical Circuits:
The Constant Voltage Transformer is designed for operation on a single or three phase
system, referred to in "Specifications Manual" as Systems I, II, III, IV and V. It
is not designed for 50 cycle operation, although it can be used as in System VI if on
60 cycles.
The C.V.T. construction is in the form of three separate single phase transformers of
the resonant winding type. The primaries are for 220,' 230, 240 volts on the full
winding, with a tap for 208 volts operation. These primaries are connected the same
as the Computer would be connected on these systems. The secondaries are connected
individually to the Service Entrance Box in the right rear base of the Sensing-Punching Section. They are interconnected in the Computer Power Distribution Box as a
Wye Connection with 220 volts from neutral to line. Neutral is grounded to frame
ground.
Provision has been made for the C.V.T. section to be energized by a Magnetic Contactor,
size 2, having a 230 volt AC coil. One side of the coil circuit is closed to the line
by the Circuit Breaker on the front of the Sensing-Punching Section. This allows
simple automatic control in nc;>rmal machine ope~ation sequence. Of course, the C.V.T.
may be energized by a wall switch if desired for special reasons. In either case, it
is necessary to push the ·'Start·' Button on the Calculating section before the Computer
is energized.
A-I
Where Located:
The C.V.T. section should be located as close to the Computer as it is practical.
This will insure minimum installation cost. The working area of four feet around
the Computer should not be, infringed upon by th:i.sSection.
speaking, the C.V.T. section should .belocated outside of air-conditioned
spaces, and in close proximity to a window, exhaust fan, or air shaft. It may be
mounted on the floor above or below that on which the Computer is located. Since
the conditions change with each installation, it is necessary for the electrical
wiring installation to be made by a local Electrical Contractor.
Ge~erally
Adapters ·'A'· & "Btl :-Figs. #10 & #11
Application -- All installations of the Univac 60 or 120 which have Constant Voltage
Transformer Regulation for the power line will require modification of the Calculating Section.
This modification is made by the addition of two small chassis identified as Adapter
"A", which mounts in the Power Control Section; and Adapter tlB", which mounts in the
Power Supply Section.
These Adapters are required to prevent alternating current control relays from opening during partial collapse of the Constant Voltage Transformer output voltage.
This occurs when certain transformers are energized during the first few cycles of
alternating current. Their function is to change the alternating current to direct
current so that it may be stored for a short time, or until the voltage comes back
to normal.
The control relays affected and operated by Adapter "A-' are K201 (Start); K208
(-165V Surge Limit); and K215, which has been added as a filament checking relay on
the ·'C t ., phase filament line. Adapter "B" operates Kl19 (-375V Surge Limit). These
relays are now operating on approximately 80 volts direct current and have a drop
out time of 125 milliseconds.
A-2
Service Technician Instructions
for the
ELECTRONIC COMPUTER
UNIVAC 60&120
CONSTANT VOLTAGE
TRANSFORMER
SECTION B
~-~-
r_
-
-::III'
-
..._---_.
,- ~
DIVISION Of SPEIIY lAND CO.POUlION -
315 POUR. TH AVENUE
NEW YOR.K. N. Y.
SERVICE TECHNICIAN INSTRUCTIONS
Changes - Sensing-Punching Unit:
A.
Service Entrance Box:
()
Check each step when completed:
()
1.
Remove Card Receiver Assembly.
()
2.
Remove 4 Conductor Service Entrance Cable and Bracket. Fasten connectors
to Service Cable Lead~ and retain cable with machine for future use.
()
3.
Remove Service Entrance Box.
()
4.
Disconnect Cond1"lit and Straight Conduit Fitting from Service Entrance Box.
Remove Straight Conduit Fitting from Conduit. Install new 90 0 angle Conduit Fitting #1660172 on this Conduit.
()
5.
Drill and tap 4 new holes as shown on Fig. #3 using a #22 Drill and 10-30
tap.
()
6.
Install new Service Entrance Box #1200587 (hinge to the right) with screws
#5518 and Washer #MX6690. Install Buchanan Connector Block #1660407
with Screws #5127 and Washer #MX6690 as shown in Fig. #2. (Use washers or
spacers on top fastenings to prevent breakage of Connector Block as screws
are tightened. Connector Block is fragile.)
()
7.
Install existing Conduit Cable (from Circuit Breaker) in center right side
of Service Entrance Box as shown in Fig. #2.
()
8.
Install new f lexi ble Conduit #1660406 with 6 wires, in lower right side of
Service Entrance Box as shown in Fig. #2.
NOTE: Use 6 black wires from Bundle #1701050, wires EZ coded #3 and
46" length, #5 and #6, 44 tt length; and #7 and #8, 42" length.
()
9.
#4~
Connect the wires to Buchanan Connector Block as shown in Fig. #4 and #5.
Make new ground connection with 8" length of #10 wire from Bundl~ #1701050
from Buchanan Connector Terminal #1 to Service Entrance Box Mounting Screw.
( ) 10.
Remove old ground connection from TB14-l
back of Punch Circuit Breaker.
_ . in
r
( r) 11.
Install 900 angle Conduit Fitting #1660403 at lower left of Service Entrance
Box as shown in Fig. #2. (This fitting will receive wires from C.V.T.).
B.
()
Power Distribution Box - Figs. #4 and #5
1.
On TB23 and TB24 make changes as in a or b to c below.
a.
( b.
\,
I.f machine was connected as 3 Phase Load; then rei:nove all 3 jumpers V ~
from TB24. Move wire EZ coded #~ at TB2~ coming from Pun~h Circuit
Breaker to TB24-2.
j
I.f machine was connected as a Single Phase . Load, then remove 2 jumpers;
one from A2 to B2 and one from B2 to C2.
\.
---'
B-1
c.
Connect these jumpers as follows:
from Bl to Cl.
NOTE:
Connect from Al to Bl.
Connect
~
Extra jumper wires must be retained with machine for future
use.
(
)
2.
Disconnect wire on TB24-3 coming from Fuse F5 and connect to TB24-1.
(
)
3.
Disconnect wire on TB24-4 coming from Fuse F6 and connect to TB24-2.
(
)
4.
Disconnect wire (EZ code 1) from TB24-1 (top) and connect to TB23-4 (top) •
(
)~~.
'--"-"<""~---
Disconnect wire (EZ code 1) from TB24-1 (bottom) and connect to TB23-4
..,,----,.-'
lr'v' ,,)~
(bottom) .
_ .. _-•.
(
)
6.
Disconnect wire (EZ code 5) from TB24-4 or TB24-5 and connect to TB24-2.
(
)
7.
Disconnect wire (EZ code 6) from TB24-6 and connect to TB24-1.
()
8.
Remove #14 brown wire (EZ code TBIO-5) from side terminal of Fuse F5 and
connect to TB24-5. Change wire EZ coding to read TBIO-l.
()
9.
Remove and tape #14 orange wire (EZ code TBIO-3) from TB23-2. Connect a
new wire (from Bundle #1701050) size #14, 10-1/2" length, from Fuse
F5 side terminal to TB23-2. Remove metal jumper between TB23-2 and TB23-3.
( ) 10.
Connect a new wire (from Bundle #1701050) size #14, 9-1/2·' length, from
TB24-6 to TB23-3.
( ) 11.
Connect a new wire (from Bundle #1701050) size #14, 9-1/2" length, from
TB24-7 to TB23-4.
( ) 12.
Connect a new flexible Conduit (previously installed in Service Entrance
Box) with a 90 0 angle Conduit Fitting #1660172 to lower right side of
Power Distribution Box, as shown in Fig. #5.
( ) 13.
Connect the 6 wires (EZ coded
numbered terminals on TB24.
C.
#g~
#4, #5, #6, #7 and #8) to corresponding
-~_
Operating Panel Terminal Board TBIO - Figs. #4 and #6
()
1.
At TBIO-3 disconnect and tape #14 orange wire (EZ coded TB23-2).
(
2.
At TBIO-4 disconnect #14 white wire (EZ coded F6-2) and connect to TBIO-3.
)
"
(
)
3.
At TBIO-l disconnect #14 black wire (EZ COded F3-2) and connect to TBIO-4.
(
)
4.
At TBIO-5 disconnect #14 brown wire (EZ COded F5-2) and connect to TBIO-l.
(The destination of the other end of this wire is also being changed, therefore, the EZ code should now be changed to read TB24-5).
()
5.
At TBIO-7 disconnect #14 brown wire (EZ coded TB23-1) and connect to TBIO-5.
NOTE:
Punch Power Supply is now fused separat'ely from motor. This allows
the Punch Power Supply to be operated wit'l:l the Motor "Oftt' by pulling out the·Motor Fuse.
B-2
Changes A.
Ele~tronic
Calculator Unit:
Power Control Chassis Fuse Panel - Figs. #7 and #12
()
1.
Remove the smaller of the side wires from Fuse F-203 (the other end of this
wire is connected to Fuse F-2~,rear). Connect this wire to Fuse F-204 rear.
It will reach this terminal i{ pulled througl). cable sufficiently.
,d-
()
2.
Remove wire (EZ code F-202R) from F-203R and tape well.
()
3.
Connect new wire (from Bundle #1701050) size #14, 34-1/2" length, between
F-203R and TB201-7. Follow contour of cable and secure to cable where
necessary.
( )
4.
Remove lower wire from TB202-3 and tape. Connect new wire (from Bundle
#1701050) size #14, II' length, to TB202-3 lower side. Run this wire
through tunnel to the Sensing-Punching Unit and connect to T~~l in Power
Distribution Box.
I) : ~.S·
B.
;;).
..
Adapter t'A&'- Figs. tl8 and tl12
()
1.
Remove cover screen below Program Test Panel.
()
2.
Loosen 2 top Regulator Chassis Phillip Mounting Screws and mount Adapter
"At. (tl1701053) behind flange of Chassis . Tighten screws.
()
3.
Remove wire from TB203-5 left side and splice to 4" extension wire connected
to TB203A-7.
()
4.
Remove wire from TB203-3 and connect to TB203A-6.
()
5.
Connect orange wire, coming from Rectifier CR205 in Adapter "At. to TB203-3.
()
6.
Connect the 8 t1 wire, connected to TB203A-8, to TB203-8 right side.
()
7.
Disconnect wire connected to Relay K205 terminal tl8 (top normally open contact) and splice to 5" extension wire coming from TB203A-4.
()
8.
Connect 11" extension wire coming from TB203A-5 to Relay K205 terminal 8.
()
9.
Connect upper end of red wire on Adapter "At. Cab Ie to TB20 3- 5.
( ) 10.
Run cable coming from Adapter "At< q,own between Timer and Regulator and to
the left rear of the RCS Chassis. The shortest section goes out to the
meter panel. The orange wire coming from TB203A-3, connects to TB206-5.
The red wire, coming from TB203-5, connects to TB206-6. The remaining cable
section is run down to the -165 Chassis and terminates on TB207. The
green wire, coming from TB203A-l, connects to TB207-1. The yellow wire
coming from TB203A-2 connects to TB207-3. Tape or tie cable to existing
cables where necessary.
( ) 11.
Disconnect wire coded tl227 connected to TB207-3 (inside); splice 5" extension wire to wire tl227 and connect to TB207-l.
( ) 12.
Replace cover screen and check for adequate clearance between Adapter "A"
and screen.
B-3
C.
Adapter ·'B" - Fig. 119
()
1.
Mount Adapter ·'B" #1701054, with attached cable, in Power Supply Chassis
under Choke L-22 by loosening Lower 1/4-20 mounting screws of L-22 and
sliding Chassis between L-22 feed and the flat washers.
()
2.
Remove two terminal screws, on right side of TBIIO-5 and TBIIO-7, located
opposite Cl-220 and 1-115.
()
3.
Mount new Terminal Board TBIIO-A on these two terminals using the jumper
strips provided. Replace the wires removed in step 2 on top of the strips.
()
4.
Remove wire coded #79 from TBIIO-6 (C2) and connect it to TBIIOA-2 (center
terminal) •
()
5.
Connect third wire of new cable (C2) to TBIIO-6 opposite wire coded #85.
D.
Bottom Rear Cover - Fig. #13
()
1.
A section of the cover must be cut out, as shown in the Fig. #11, to provide
power cable clearance.
()
2.
An 8 t ' piece of insulation #6860-8-76310400 is inserted over the cut surface
to protect the power cable.
Parts Ordering:
The C.V.T. and necessary parts are not available on the Standard Factory Parts Order.
These items must be ordered through the Sales Department on the regular Sales Order.
B-4
Electrical Contractor Instructions
for the
ELECTRONIC COMPUTERS
UNIVAC 60&120
CONSTANT VOLTAGE
TRANSFORMER
SECTION C
-
.
-,~-------.--..,.---~
-_
DIVISION
Of SPERRY .... ND CO.PO .... lION -
31$ FOURTH AVENUE
NEW YORK. N. Y.
ELECTRICAL CONTRACTOR INSTRUCTIONS
The C. V. T. section should be located as close to the Computer as is practical..
This will insure minimum installation cost. The working area of four feet around the
Computer should not be infringed upon by this section (see Fig. #17).
Generally speaking, the C.V.T. section should be located outside of air-conditioned
spaces, and in close proximity to a window, exhaust fan, or air shaft. It may be
mounted on the floor above or below that on which the Computer is located. Since
the conditions change with each installation, it is necessary for the Electrical
Wiring installation to be made by a local Electrical Contractor.
The C.V.T. is designed for operation on a Single or Three Phase System referred to
in Fig. #14 as Systems I, II, III, IV and V. It is not designed for 50 cycle operation, although it can be used as in Systems VI if on 60 cycles.
Provision has been made for the C.V.T. section to be energized by a Magnetic Contactor,
size 2, having a 230 volt AC coil. One side of the coil circuit is closed to the line
by the circuit breaker on the front of the Sensing-Punching Section. This allows
simple automatic control in normal machine operation sequence. Of course, the C.V.T.
may be energized by a wall switch if desired for special reasons.
C.V.T. Specifications:
Output rating:
300 volt-amperes, each section.
Total 9KVA.
Output voltage:
220 volts, single phase, each section.
(A) Input voltage:
240 volt primary with tap at 208 volts, each section.
Frequency:
60 cycles.
Surge:
Load starting surge 25 amperes, each section. Additional
random surge up to 75 amperes maximum for one half cycle.
Load power factor:
95% inductive, each section.
Regulation:
Output ± 1% with input variations of 30% and load variations
from 66 to 100%. No-load voltage and voltage at loads under
66% may be + or - 5%. The input variations of 3aro should be
as close as possible to + or - 15% of the input nominal.
Correction must be made within two cycles.
Harmonic content:
Not more than 3% total harmonic content from 66% load to full
load for each section.
Terminals:
Pressure, - screw type, clearly marked 'lPrimary", "Secondary",
and tape voltages, to receive AWG #4 max.
Ambient:
40 0 C.
Dimensions:
Height - 47 inches;
Weight 1228 Ibs.
Heat Dissipation:
Variable, max. estimated 6800 BTU/HR.
Rise 60 0 maximum.
Width - 24 inches; Length - 28 inches;
C-l
Sola C.Y.T. Service Information
for the
ELECTRONIC COMPUTER
UNIVAC 60&120
CONSTANT VOLTAGE
TRANSFORMER
SECTION 0
'--_~_
__
'-:7
-
'lIPlt_____ •
-.....,....
DIVISION OF SPERRY RAND CORPORAl ION -
315 FOURTH
AV~NUE
NEW YORK. N. Y.
SOLA C.V.T. SERVICE INFORMATION
SAFETY NOTICE:
THIS EQUIPMENT EMPLOYS VOLTAGES WHICH ARE DANGEROUS AND MAY BE FATAL IF CONTACTED.
EX'IREME CAUTION SHOULD BE EXERCISED WHEN WORKING WITH THE C. V. T . 00 NCYI' TOUCH ANY
INTERNAL CONNECTIONS WHILE PRIMARY CIRCUIT IS ENERGIZED. OPERATING VOLTAGE AT CAPACITOR TERMINALS IS APPROXIMATELY 700 VOLTS. ALWAYS REMOVE POWER BEFORE ATTEMPTING
ANY MAINTENANCE.
No Routine Maintenance Necessary:
Since the C.V.T. is a simple rugged device without moving parts or manual adjustments,
no "Service" or "Maintenance" is needed in the ordinary sense; and the per cent of
possible poor performance or failure is exceedingly low. In any case of apparent
poor performances, the user is urged to check the following points immediately:
Check List of Factors Effecting Performance:
Checking with Voltmeters: All checks on .the AC output voltage of the C.V.T. should
be made with a Dynamometer type Voltmeter. A certain amount of harmonics in the
output may cause other types (particularly Rectifier types) to give inaccurate readings; for instance: Some Vacuum Tube Voltmeters, Multi-Meters, etc., may read as
much as 8% high on Sola RMS output of 115 volts.
1.
Probable Trouble -- If the output voltage is too low and it has been established
that the unit is not overloaded and that the load power factor is correct, either
a defective Capacitor or Transformer Winding is indicated. A defective Capacitor
is the most likely trouble. To check, proceed as follows:
De-energize the C.V.T. and remove the C.V.T. front cover as shown in Fig. #16.
Disconnect the load and connect a 0-300 Volt AC Voltmeter across the output terminals. Re-energize the C.V.T. and check meter reading. If meter reads about
20 volts, a shorted Capacitor is indicated. If the meter reads a little below
the normal value voltage, an open capacitor or a damaged transformer winding
may be the cause of trouble.
2.
Capacitor Short Test -- To determine which Capacitor is shorted, de-energize
the C.V.T. and disconnect Capacitor C-l by removing 1 terminal connection. Energize the C.V,T. and check the meter reading. If output voltage does not rise
to approximately normal value, de-energize the C.V.T., re-connect C-l and disconnect C-2. Continue with each succeeding Capacitor until voltage does rise to
near the rated value.
REMEMBER TO DE-ENERGIZE EQUIPMENT BEFORE CONNECTING OR DIS-CONNECTING ANY CAPACITOR.
3.
Capacitor Open Test -- To determine whether a Capacitor is open or a Transformer
winding is damaged, a new Capacitor having approximately the same capacity and
voltage rating must be connected in parallel with the existing Capacitors. If
one Capacitor is open, adding a new Capacitor in parallel will bring the voltmeter reading to a normal value. If the meter reading does not return to approximately normal value, a damaged Transformer Winding is indicated. To determine
which Capacitor is open, de-energize the C.V.T. and disconnect C-l. Energize
the C.V.T~ If reading of voltage meter drops somewhat below normal value, deenergize the C.V.T., re-connect C-l and disconnect C-2. Continue with the
D-l
other Capacitors until voltage reading of meter does not drop.
4.
Damaged Transformer Winding -- If all checks indicate a damaged Transformer
Winding, the C.V.T. must be returned to the factory for repair. If after two
Capacitors have been replaced, a third Capacitor becomes defective, the entire
unit should also be returned to the factory to be repaired. Since the total
capacitance is matched to the coils, replacing more than 1 or 2 Capacitors with
Capacitors of only approximate value may cause improper functioning of the Voltage Regulator.
5.
Output Voltage Too High:
6.
7.
a.
Load may be considerably less than normal.
b.
Load may have leading power factor.
c.
Line frequency high.
Output Voltage Too Low:
a.
Unit may be overloaded.
b.
Primary voltage below 190 volts.
c.
Line frequency low.
d.
Defective Transformer Winding.
e.
Defective Capacitor.
No Output Voltage:
a.
Open terminal connection.
b.
Open Primary or Secondary Transformer Winding.
GUARANTEE
Sola Constant Voltage Transformers are guaranteed against failure due to faulty
materials or workmanship for a period of one year from date of sale.
LIST OF SOIA ELEC':rnIC CO. REPRESENTATIVES
SOIA ELECI'RIC CO.
Plant & General Offices
4633 West 16th Street
Chicago 50, Illinois
BOSTON, Massachusetts
Sola Electric Co.
272 Centre St.
Newton 58, Massachusetts
ATLANTA 5, Georgia
James Millar Associates
1036 W. Peachtree St. NE
BUFFALO 3, New York
R. W. Mitscher
487 Ellicot Square Bldg.
D-2
CHARLOTTE 2, North Carolina
Ranson, Wallace & Co.
116-1/2 E. Fourth St.
NEW YORK 35, New York
Sola Electric Co.
103 E. 125 St.
CLEVELAND 15, Ohio
Sola Electric Co.
1836 Euclid Avenue
PHILADELPHIA, Pennsylvania
Sola Electric Co.
Comm.ercial Trust Building
15th & Market Streets
DALLAS, Texas
J. B. Stuart
4401 Caruth St.
PITTSBURGH 18, Pennsylvania
Burke Electrical Equipment Co.
416 Maple Avenue
DENVER 4, Colorado
Slaybough & Thompson
100 W. 13th Avenue
PORTLAND 10, Oregon
Marshall B. James
2941 NW Quimby St.
KANSAS CITY 2, Missouri
Sola Electric Co.
406 West 34th St.
SAN FRANCISCO, California
Joseph M. Smith
3625 South Grand Avenue
Los Angeles 7, California
LOS ANGELES 27, California
Edward S. Sievers
1662 Hi11hurst Avenue
SEATTLE 4, Washington
Northwestern Agencies
4130 First Avenue, South
D-3
Changes Necessary When Removing
the,
CONSTANT VOLTAGE
TRANSFORMER
ELECTRONIC
COMPUTERS
UN"IVAC 60 & 120
SECTION E
,,_ _ 1_
-
•
-:::JIf- -
'
"Rand..
'-,
DIVISION Of SPERRY RAND CORPORATION -
315 FOURTH AVENUE
NEW YORK, N. Y.
CHANGES NECESSARY WHEN REMOVING C.V.T.
1.
In the event a Computer having a Constant Voltage Transformer is re-shipped to
an installation not requiring the Transformer, certain changes are necessary, but
not all of the original yhanges.
2.
The Calculating Section will operate with Adapters A and B, regardless of whether
or nQt there is a regulator of any type on the input line.
They should not bE:) removed once installed, for they tend to improve the reliability of the control relays concerned. In addition. there is a "e Line~t filament
failure check circuit 1ncorporated which is of possible benefit.
Electronic Calculating Unit:
There are no changes to be made in this section.
Sensing-Punching Unit:
Changes in this section are
follows:
A..
~onfined
to those which are absolutely necessary as
Power Distribution Box
()
1.
Wire coming from TB202-3 in Computer, now on TB24-l (D-l), is disconnected
and re-connected to TB24-3 (A-I).
()
2.
Wire coming from TB201-7 in Computer, now on TB24-2 (EZ coded 2), is disconnected and re-connected to TB24-4 (A-2).
()
3.
Wire coming from Fuse F-5 is disconnected from TB24-l (D-l) and is re-connected to TB24-3 (A-I).
()
4.
Wire coming from Fuse F-6 is disconnected from TB24-2 (D-2) and is re-connected to TB24-4 (A-2).
()
5.
Remove Jumper between TB24-7 (C-l) and TB23-4 (ground).
in machine for future use.
6.
Three of the four AWG #8 wires coming from the Punch Unit Circuit Breaker and
TB14 are now connected in the normal manner for the Power System employed.
If Single Phase System is employed, make connections as in (a) below.
If
Three Phase Sxstem is employed, make connections as in (b) "below.
a.
Retain this Jumper
Single Phase - Fig. #18
)
1.
Disconnect wire (EZ cOded #5) from TB24-2 and re-connect to TB24-5.
( )
2.
Disconnect wire (EZ coded #6) from TB24-1 and re-connect to TB24-6.
( )
3.
Connect jumper wires between TB24-4 (A2), TB24-6 (B2), and TB24-8
(
(C2).
Wire EZ coded #1 remains on TB23-4 ground.
E-l
b.
( )
(
Three Phase - Fig. #19
1.
Disconnect
or 5.
wir~:~:~··~~~)·,,:f~om TB24-2
...'.
.,:,
and re-connect to
TB2~-4
:··,·",,,,,-,,:"i·\
)
( )
3.
Disconnect wire (EZ coded #2) from TB24-2 and re-connect to TB24-8.
~~""-"-.~'
•."""---''--'.'"
',. ,., ..,_,_.-,r;.,.""...,.. ~'
( )
4.
Disconnect jumper wires between T!324-3. ,(AI), TB24-5 (Bl) and TB24-7
(Cl).
--
( )
5.
Connect jumper wire between TB24-3 (AI) and TB24-8 (C2) .
( )
6.
Connect jumper wire between TB24-4 (A2) , and TB24-5 (Bl) .
( )
7.
r'·
Connect jumper wire between TB24-6 (B2) and TB24-7 (Cl) .
_. "..-
os
_.
",--,
,.".....,"'"-.,
Wire EZ coded #1 remains on TB23-4 grbund.
B.
Service Entrance Box
At the Service Entrance BOX, the AWG #8 wires are terminated at Buchanan Block Terminals #9 (Dl), #10 (D2), #1 (Ground) and #2 (D2C).
1.
Terminal #9 (Dl) becomes line A.
2.
Terminal #10 (D2) becomes line B.
3.
Terminal #2 (D2C) becomes line C, used in both three phase systems.
4.
Three Phase Circuit Breaker would, of course, be required as in standard Three
Pr~se connection.
5.
Terminals #3, #4, #5, #6, #7 and #8 are left as is, connected only to TB24
identical terminals.
(Red wire)
(Black wire)
(White wire)
Four wire power cable now may be connected using standard entrance bracket and
clamp or going through opening in left side cover. It should enter Service Entrance
Box through 1-1/4" hole in bottom by use of reducing washers, or may be passed through
1-1/4" right angle conduit clamp.
E-2
J
•
CONSTANT VOLTAGE
TRANSFORMER
·CVT· ASSEMBLY
FIG.I
-
CONSTANT VOLTAGE TRANSFORMER INSTALLATION
,.
Iii
,.
Iii
O"t-+-_ _ _ ~~(4fpDIA.lIlRlLL
4 HOLES
6.750
6.750
FIG. 3
LEFT REAR
BASE CASTING
4.000
4.000
L
TWO SECTION
BASE
SINGLE SECTION
BASE
OPERATING PANEL
TB-IO
TERMINAL BOARD
r---------------------v----(SEE FIG 6)
RG4
[~
t~-- rf=__fin
r~
tr,:
f l
WIRING
SENSING- PUNCHING
UNIT
a>tifi:
~~'
en
(I)
I
I-
IL.
~
~
l
E
:!!
~
SENSING- PUNCHING
II'IIT CIRCUIT BREAKER
(SEE'FIG'.'~
.
MAY BE SINGLE {50 AWl OR THREE
PHASE (30 AMP.) CIRCUIT ~AKER.
1
r----------,
:~J.\ I
1
I -
I I
1-
!
I L ___ .,.;:(,___
I
I
TB-23
at.D 'lMTER
GROI.Nl
PlPEr-c;:~~""l4-1I-=-___1f_____'.+_+./
I
I
I --<2_ _---Jf-+__'
,. MAGf\ETIC ~. "'(!,)-"D"'2"-C+
COIL
r
I
200~
REGUl~TED
~.
REGULATED
""'.
(SEE FIG.121
~
4-TBJ-"I--",,--='
201-:.!-7----'-_ _ _, /
I
~~A~I_}:~3---1-t_-------------------------~
I
lr.-.
A2, I 4
II r®'~_},~--1--+--------~----------------------------~
i
81
5
1 '-@.-'8"'2_}'!C6---1--t_---------------'-------------------------'
I
~,~C~I_+'~7---___1f_____'.+_------------------------------------~
ZOBV. 10 240V.
II
I
NOT REGULATED
L_,,_~_-l~!ll2_-Ji---'~5_ _ _~
-REGULATED
T8II"-8
CABLE TO
~~II'llllVJll'~ ..4(- .-lC'-l2-+;~.----j-t_--------------------------------/
'9' 01
: 6
BUCHANAN CONNECTOR
BLOCK
{SEE FlG..2J
CONSTANT VOLTAGE TRANSFORMER INSTALLATION
PLATE 2
JUNCTIOI\i BOX (FRONT)
EXISTING FLEXIBLE CONDUIT
POWER
DISTRIBUTION BOX
5118 SCREW
MX6690 WASHER
--~~~
HINGE SlOE
1200587
SERVICE ENTRANCE
BOX
o
EXISTING FLEXIBLE CONDUIT
----/
1660407
~~~~~~-~-tir~~~t-~~
)
BLOCK
2 { 5121 SCREWS
MX 6690 WA?HERS
"
_____ ..:.J
1660172 - 90° ANGLE
CONDUIT FITTING
o
"
----"-1660406 125")
5118 SCREW
MX 6690 WASHER
NEW FLEXIBLE
CONDUIT
SERVICE
ENTRANCE BOX
INSTALLATION
1660406~
FLEXIBLE CONDUIT
LEFT REAR BASE CASTING
(SEE F1G.!)
l,
:
-_~
TB20I-8
TB
-1
III 202-3
TO COMPUTER UNIT
{SEE FIG. 12)
POWER
CONTROL
CHASSIS
FIG .7
~.
CLEAR
READY
MAGAZINE
INPUT CHECK
CARD FEED
MOTOR
51/.,· -
TB 10
FOR WIR·NG
SEE FIG. 4
,
,~
FIG. 6
CONSTANT VOLTAGE TRANSFORMER INSTALLATION
PLATE 4
CONSTANT VOLTAGE TRANSi='ORMER INSTALLATION
PLATE 5
~~F~2~0~3
____
~
__________________________________________________________
~
~----------------------~
~~·.1A
~209.
SA
300W
17jl.A
v
F207
17fi300W
H VOLTAGE
T22,24,25
PL.51
T26D
T-27
~
.J
(Me)
'~
",,'----------+---~------+4_1
(MC)
r K256
~
--: ~
a
M
01
~
. - - - 1 i'1r-A_ _ _ _-++-+-+..... ;"',S""'O""-M""-M-"".O""'"N-,-iK116 KU7
vg~I~~E
F210
R~~~kNG·V0LJ:~ETER
+75 +150
TB
<> R254
-;;2K-20W
'I~
CR
205
'IZ 65MA.
P'SD.SERY.
INTERLOCK
115 V.
.
$ib,
(-JVOLTAGE
CHECK
(+)VOL
CHECK.\
AG~\'
;rB203A WiIOllf
;:f;C224
I TB203A- 8 leov. 2
..
~~if~if~vi:
--
.fA
·203A·6
(MC)
. tJ
M
.
,-----'-I--+--I@~I-~>-!--.--. ~("--
~~)SWITCH
F201
ON~
--!OFF
~_ _ _-4---.J.J(5 SEC.}
T29
:I
L _ _"-"....J
5=b HK207
K203
METER
r - -
T2.3,30
PL.52
'---_--J
I
ON
INDICATOR
(+) VOLTAGE
!.
v=:
..
1 eHERMOSTAT
3
K1l5 K1l4 K1l3 K1l2 KllB Kill K210
-15 -60 -90 -150 -375 -400-165
METER
t-to
Nit) N
CQ
~ ~ ~g ~
L-.----------\-\------+-....lL:!:L-==3==:(6:::.,:0::....::::.SE:::;C::::;.:!..)_--+_____-,
3A
\
'.f
8 I- N m N 10
111--- ----+------'-<.>A':=2~(9~0<....:::::.S:::;EC"'".:!..)- - 1 - - - - - ,
_--~...-.N N , N
F206
~
___--------+~7.Jl." 6 r- I- C\l I-~
A:-'1~(c::.10=-=S=-=E:.:::C;:.:..P~.'"-'-+-----t--t-+----'
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t--1--_ _ _ _ _---4+~5~A
~
-
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~ «
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I-
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TB203IH
'---I~"'!'?l:::~~ 7~ !~FA);'O%R~
L- - '-: : .:.-_: :_~______________
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Y_F_O_R_T_D_2_0-J'
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CI
2
7
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COM-
FROM T29
'l-139
10 K
10 iN
22
~-I-------.-
[
Te-IIS
30url~OV
-40°0
FIG.II
POWER SUPPLY MINUSVOLTAGES WITH ADAPTER
A a B
INCLUDED.
CONSTANT VOLTAGE TRANSFORMER INSTALLATION
PLATE 7
I
I
r--..l--~
i (i)
iEJ EJ EJ
§:I
DO
00
TIMING
ASSEMBLY
I
~':
:
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I
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L__ -t
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r--------~~-------------------------.,
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a
:
TD201
I
:
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L____________________ J
:
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I
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~~~
XI .
INSTALL NEW WIRE
GROUND WIRE ALREADY IN CAB!.£
SPARE WIRE ALREADY IN CABLE
-
TB 24-1
}
IS 23.-4 ..
_ _ _~
V
IN
SENSI NG
PUNCH Ui'lII
(SEE FIG.4
a 5)
r-----------------------------------------------,
I
FUSE PANEL
~ri'-i-ii-~~-~~-~--+-I
L _______ , ___
~
aD DDDDDDD
~
J
i
_______________________________________ I
r-
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GREEN
YELlOW
®- @®-®-0-@-®-@-®®@-®@®®1
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L_ _____________~~______________ J
FIG.12
3
WIRING
COMPUTER
lJIIIT
1
'227
CAPACITOR ASSEMBLY
1700603
L ________________ _______________
~
CONSTANT VOLTAGE TRANSFORMER INSTALLATION
~
PLATE
8
FIG. 13
PUNCH-REAR
COVER MODIFICATION
8z
~
)::i
Z
-I
~
!;i
g
O-I----T---------------------------------r----I-~
fTl
-I
::0
1>
Z
(J)
II
I
1I
II
11II
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II
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0
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6z
6860-8-76310400
8 INCHES ( APPROX.l
II
II
Ii
II
IU
14
-
-u
r
~
fTl
(O
USE MAR80N COLD SETTING ADHESIVE (R.S.2G8)
NOTE'- ALL SURFACES TO BE CEMENTED
MUST BE CHEMICALLY CLEANED.
II
II
::
II
11
i
I
II11
II
II
II
!i
IiII
d
,I
~
r
r
I
II
II
II
II
jl"
(J)
I
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L
II
fTl
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IL ___ ...,
* **
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I
II~-...:::
*
....i I
'F
'1'
1
1
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II
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I
II
~2rl3rJ
II
II
II
'I
.-_-~I
'* * * I
1* * *JI
-1:;---1)
FOR NC*IINAL VOLTAGES OF'
ATOB = 208
wtEN CONDUCTOR
LENGTH IS:
BTOC~208
CToA=208
MAXIMUM TOTAL VARIATION INCLUDING
TRANSIENTS NOT LOWER THAN 177 V.
OR HIGHER THAN 239 VOLTS.
50 FT. OR LESS
51 FT. TO 100
101 FT. TO 200
= 220TO 250
B TOC ~ 22OT025O
C TO A = 22010250
A TO B
MINIMUM WIRE
AWG
IS:
SIZE
F
G
H
10
10
10
10
8
14
8
6
I"I.
MAXIMUM TOTAL VARIATION INQ..UDfNG
TRANSIENTS NOT LOWER THAN 187 V.
OR HIGHER THAN 276 VOLTS.
COLD WATER PIPE
GROUNO
F
D1STANCE DETERM.INED
BY CUSTOMER
NOTE (SEE CHART FOR
WIRE SIZES.)
I
: :~--=--=-~-=:l:
I--it-
Z
.-i
P
l?i
G')
rr1
-l
::0
l>
z
;:g
;;!
::0
3:
rr1
::0
Z
en
CONSTANT VOLTAGE TRANSFORMER
I
I"
1'4 CONDUIT
INPUT
24"
I
en
!:j
(5
z
en
!:j
(5
z
=Ti
HEIGHT
44"
WEIGHT
1228 LBS
12"
I"
14 CONDUIT
OUTPUT
1
--
I
II
DISSIPATION: VARIABLE
MAX. ESTIMATED 6,800 BTU/HR
r
r
;;!
rr
I
I
"
=:J
~
I'T· 18".'N----1
I
I
I
Z
en
r
18'""---1
~I(----------------F~~T--------------~)I
5'6"
"0
~
(5
~
z
(J)
(5
36" MIN.
I
3 FEET MIN. CLEARANCE IS REQUIRED ABOVE
UNIT FOR AIR EXAUST OUT THRU TOP. INTAKE
IS IN FRONT COVER AND THRU BOTTOM OF THE
UNIT. CONVECTION COOLED.
~
I
WALL OR OTHER
INTERFERENCE
L ______ _
-
ro
~
_I
>j
_______________________________l_____J
------.------------7'10"------------------------~~
--'------~---.----.----
FIG. 18
TO
PUNCH UNIT
CIRCUIT
BREAKER
AND TOTB 14
POWER
DISTRIBUTION BOX
SINGLE PHASE CONNECTIONS AFTER CVT HAS BEEN REMOVED
II
II
C)
C)
o
C)
FIG. 19
PUNC~OUNIT {~~~~~~~~~~~~~~~)~
CIRCUIT
BREAKER
AND TO TBI4
POWER
DISTRIBUTION BOX
THREE PHASE CONNECTIONSAFTER CVT HAS BEEN REMOVED
C)
C)
o
1660406
FLEXIBLE CONDUIT
TO
COMPUTER UNIT
CONSTANT VOLTAGE TRANSFORMER REMOVAL
PLATE 13
ELECTRONIC COMPUTER
UNIVAC 60& 120 .
SUPPLEMENT II
BUCK BOOST TRANSFORMER
-
DIVISION
OF
SPERRY
RAND CORPORATION -
315 FOURTH AVENUE
NEW YORK, N. Y.
FOREWORD
In some customer installations, computers are expected
to operate on 240 or 250 volts either single or three
phase. Where this condition exists, high voltage
conditions can be corrected through the use of the
Buck Boost Transformer, pr.ovided the line fluctuation is within plus or minus 5%.
The Buck Boost Transformer is not to be used where
the constant voltage transformer regulator is employed.
The complete installation instructions for the Buck
Boost Transformer are explained in the following
pages.
PLATE DRAWING INDEX
FIGURE TITLE
E!2.:.
PLATE
Buck Boost Transformer Assembly
1
1
Power Distribution :Sox - Single Phase Connection:
Power Distribution Box - Three Phase Connection
2
2
3
2
Buck Boost Transformer Connections - Single Phase
Three Phase
Buck Boost Transformer Connections
4
3
3
5
ELEC'IRONIC COMPUTER
UNIVAC 60
& 120
BUCK BOOST 'IRANSFORMER
CONTENTS
Foreword
Plate Drawing Index
Installation Instructions ...•....••..•.•...•.......•....................
Application ......................•.................................•..
Btlcking. " .. " ... " " " . " ... " . " .. " " . , " .... " " ........ " . " " " " " .. " " .... " ...... "
Boost ing" . " . " .. " .... " " . " ... " . " " " " ... " " . " ... " . " " ... " ... " ... " . " ... . " .. " .
Single or Three Phase •...............................•....••....•.....
Description .. " ...... " .. " . " ... "" . " " . " . " ..... " .. " " .. " " " " . " .. " " " . " . " . " . " .
Parts Ordering."" ......... " .. "" ... " .. "."" .. ""."." .. " ....... ""." .... " ..
Installation Instructions ......•....•.•....•.•..•........•............
Testing .. " .. " . "..... " " " . " . " " .. " .. " .. " " "" """ " " " " " " " " " " " " " " . " " " " "" " " " . " "
Printed in U. S. A.
1957
1 1
1
1
1
1
2
2
3
3
INSTALLATION INSTRUCTIONS
for the
ELECTRONIC COMPUTER
UNIVAC 60& 120
BUCK BOOST TRANSFORMER
-
DIVISION
OF SPERRY RAND CORPORATION -
315 FOURTH AVBNUB
NBW YORK, N. Y.
INSTALLATION INSTRUCTIONS
Application:
Buck Boost Transformers are used to lower or raise the line voltage a given percentage below or above the nominal voltage. Although they change the voltage. they
are not regulators and are not constant voltage transformers. They may be likened
to step-down. or filament transformers, which have one or more low voltage secondaries.
In some customer installations, machines are expected to operate on 240 or 250 volts,
either Single or Three Phase power. This condition exists where a customer is close
to a sub-station or where new power distribution lines are installed to replace older
obsolete systems.
These high voltage conditions can be corrected through the use of Buck Boost Transformers. In such cases, variations of the line must be measured and if found to
have a variation of not more than plus or minus 4% from a listed nominal, then this
method of correction may be employed.
Bucking:
In addition to the Univac 60 and 120 nominals of 208, 220 and 230 volts, we can take
advantage of the 4 volt adjustment windings (which in themselves are Buck Boost Win ...
dings) and operate the c.omputer on 204, 212, 216, 224, 226 and 234 volts. The use.
of these taps in conjunction with the Buck Boost Transformers now allows adjustments
to 235, 240, 245, 250 and 255 volts. We now have a range of nominal input volts
from 208 to 255 volts.
Boosting:
This unit could also be used to boost low voltages by the same percentages as bucking.
This is not generally recommended because low voltage conditions are associated with
high power line drops, which result in poor (outside of specifications) voltages.
In such cases, regulation is required.
Single or Three Phase
The Transformer Assembly may be used for single phase 2t three phase operation of
the Computer on 50 or 60 cycle power. IT SHOULD NOT BE USED IN CONJUNCTION WITH
CONSTANT VOLTAGE TRANSFORMERS.
Description:
The Suck Boost Transformer Assembly consists of three transformers fastened to a
mounting plate. Each'has its own terminal box for connections. The center box is
connected by a cable to the Power Distribution Box, into which the calculating Section power lines are connected to the SenSing-Punching Unit.
The assembly is fastened across the rear of theSensin~Punching Base Casting, underneath the Receiving Pockets. There are no holes to drill.
Since the location of the Transformers interferes with the mount~ng of skids during
shipment, it must be mounted after the skids are removed by the Maintenance Department.
-1-
Parts Ordering:
The Buck Boost Transformer and necessary parts are not available on the standard
factory parts order. These items must be ordered through the Sales Department on
the regular sales order.
INSTALLATION. INS'IRUCT I ONS
()
Check each step when completed:
Figure #1
()
1.
Turn off all power to the machine or remove plug from power source.
( ) . 2.
Remove lower right side and lower left side covers.
()
3.
Remove two lower-left cover supports.
()
4.
Open Service Entrance Box and disconnect 4 power leads.
()
5.
Remove flexible conduit from bottom of Service Entrance Box.
()
6.
Remove straight conduit fitting and replace with 900 right angle fitting
#1660172.
()
7.
Reconnect the four leads, in the Service Entrance BOX, as they were and
tape proper ly •
()
8.
Mount Transformer Assembly #1800171 on base as shown in Figure #1 using
longer screws #402528.
NOTE: . Transformer mounting plate must be placed underneath angle bracket
to prevent interference of screws above. Loosen screws and drop
vertical Unistrut members down to base casting to prevent interference with the Receiving Pocket door.
Figures #2 & #3
()
9.
.pnright sideoimachine open proper size lmockout slug in Power Distribution Box. Use care to remove only the smaller slug.
( ) 10.
Install cable coming from.Transformer Assembly as shown in Figure #2 & #3.
( ) 11.
a.
For Single Phase operation, connect leads in Power Distribution Box
as shown in Figure #2.
b.
For Three Phase operation, connect leads in Power Distribution Box as
shown in Figure #3.
a.
For Single Phase connections of the Buck Boost Transformer connection
Boxes, refer to Figure #4.
b.
For Three PhaS.e' Connections of the Buck Boost Transformer Connection
Boxes, refer to Figure #5.
( ) 12.
-2-
NOTE:
One lead, #12, is used only in Single Phase connections. This lead
will be found in one of the Buck Boost Transformer Connection Boxes.
Testing
( ) 13.
Turn power on and operate circuit breaker to the "ON" position. Check
for correct voltages on TB24. TB24 terminals 3 and 4 are the ·'N' line;
5 and 6 the ttB" line; and 7 and 8 the .. c .. line. Each pair should now
have similar voltages to the others. This may drop slightly due to
line impedence when the computer is on.
( ) 14.
Depress Computer "ON" button and allow Computer to ··Crank Up". Wi th DC "ON"
and Punch Motor ·'ON" I check voltages again. When the voltages are correct,
make necessary adjustments to the Filament and Plate Transformers to achieve
correct filament and D.C. voltages.
~3-
FIG. I
BUCK BOOST
TRANSFORMER ASSEM .
BUCK BOOST TRANSFORMER INSTALLATION
PLATE
POWER
DISTRIBUTION BOX
SINGLE PHASE CQIINECTIONS
FIG.2
C)
}
C)
o
C)
CABLE COMING FROM BUCK
BOO5f TRANSRRo£R ASSEM.
POWER
DISTRIBUTION BOX
THREE PHASE CONNECTIONS
FIG.3
o
C)
o
C)
CABLE COMING FROM BUCK
BOOST TRANSFORMER ASSEM.
BUCK BOOST TRANSFORt.£R INSTALLATION
PLATE 2
10
CONNECTION FOR
10% BUCKINGVOLTAGE (250VOLT
OPERATION)
X3
X4 t---f-1
HI
HZ
H3
H4
CONNECTIONS FOR
5% BUCKINGVOLTAGE (240 VOLT
OPERATION)
c
FIG. 4
BUCK BOOST TRANSFORMER
CONNECTIONS-SINGLE PHASE
7
~
N
C(
::I
r;-
~
m
....
~
0
~
m
....
*
3
N
N
tm
....
N
N
m
U
If
~
~
BB-A
CONNECTIONS FOR
10% BUCKING VOLTAGE ( 250VOLT
OPERATION)
BB-C
XI
X2
X3
X4
HI
H2
H3
H4
XI
X2
X3
X4
HI
H2
H3
II
6
7
8
N_
3
N_
UC(
mu
1ft;
~~
BB-C
~~
XI
X2
X3
X4
HI
.H2
H3
H4
CONNECTIONS FOR
5% BUCKINGVOLTAGE (240 VOLT
OPERATION)
II
FIG. 5
6
BUCK BOOST TRANSFORMER
CONNECTIONS-THREE PHASE
N_
C(m
7
N_
IIlU
8
3
N_
UC(
'\0 .....
o 0
~~
mm
........
BUCK BOOST TRANSFORMER INSTALLATION
PLATE 3
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