GM Series/GM Series Detailed Service Manual 6864115B62 B

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Professional Radio
GM Series
Detailed Service Manual
6864115B62-B
ii
WLS EMEA Publications Department, Jays Close, Viables Industrial Estate, Basingstoke, Hampshire, RG22 4PD, UK.
Issue : August 2002 iii
Professional Radio
GM Series
Detailed Service Manual
6864115B62-B
Contents
Section 1 Service Maintainability
Section 2 Controlhead Service Information
Section 3 Controller Service Information
Section 4 VHF Service Information
Section 5 UHF Service Information
Section 6 Lowband Service Information
iv
Professional Radio
GM Series
Service Maintainability
Issue: August 2002
ii
Computer Software Copyrights
The Motorola products described in this manual may include copyrighted Motorola computer programs stored
in semiconductor memories or other media. Laws in the United States and other countries preserve for
Motorola certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or
reproduce in any form, the copyrighted computer program. Accordingly, any copyrighted Motorola computer
programs contained in the Motorola products described in this manual may not be copied or reproduced in
any manner without the express written permission of Motorola. Furthermore, the purchase of Motorola
products shall not be deemed to grant, either directly or by implication, estoppel or otherwise, any license
under the copyrights, patents or patent applications of Motorola, except for the normal non-exclusive
royalty-free license to use that arises by operation of law in the sale of a product.
iii
Table of Contents
Chapter 1 INTRODUCTION
1.0 Scope of Manual ..................................................................................................1-1
2.0 Warranty and Service Support.............................................................................1-1
2.1 Warranty Period and Return Instructions .......................................................1-1
2.2 After Warranty Period .....................................................................................1-1
2.3 European Radio Support Centre (ERSC).......................................................1-2
2.4 Parts Identification and Ordering ....................................................................1-2
2.5 EMEA Test Equipment Support......................................................................1-2
2.6 Technical Support...........................................................................................1-3
2.7 Related Documents ........................................................................................1-3
3.0 Radio Model Information......................................................................................1-4
Chapter 2 MAINTENANCE
1.0 Introduction ..........................................................................................................2-1
2.0 Preventive Maintenance ......................................................................................2-1
2.1 Inspection .......................................................................................................2-1
2.2 Cleaning .........................................................................................................2-1
3.0 Safe Handling of CMOS and LDMOS..................................................................2-2
4.0 General Repair Procedures and Techniques.......................................................2-2
5.0 Notes For All Schematics and Circuit Boards ......................................................2-5
Chapter 3 SERVICE AIDS
1.0 Recommended Test Tools...................................................................................3-1
2.0 Test Equipment....................................................................................................3-2
iv
v
SAFETY AND GENERAL INFORMATION
IMPORTANT INFORMATION ON SAFE AND EFFICIENT OPERATION
Read this infomation before using your radio.
The information provided in this document supersedes the general safety information contained in user guides
published prior to July 2000. For information regarding radio use in a hazardous atmosphere please refer to the
Factory Mutual (FM) Approval Manual Supplement or Instruction Card, which is included with radio models that
offer this capability.
Radio Frequency (RF) Operational Characteristics
To transmit (talk) you must push the Push-To-Talk button; to receive (listen) you must release the Push-To-Talk
button. When the radio is transmitting, it generates radio frequency (RF) energy; when it is receiving, or when it
is off, it does not generate RF energy.
PORTABLE RADIO OPERATION AND EME EXPOSURE
Your Motorola radio is designed to comply with the following national and international standards and guidelines
regarding exposure of human beings to radio frequency electromagnetic energy:
●United States Federal Communications Commission, Code of Federal Regulations; 47 CFR part 2 sub-part J
●American National Standards Institute (ANSI) / Institute of Electrical and Electronic Engineers (IEEE)
C95. 1-1992
●Institute of Electrical and Electronic Engineers (IEEE) C95.1-1999 Edition
●National Council on Radiation Protection and Measurements (NCRP) of the United States, Report 86, 1986
●International Commission on Non-Ionizing Radiation Protection (ICNIRP) 1998
●Ministry of Health (Canada) Safety Code 6. Limits of Human Exposure to Radiofrequency Electromagnetic
Fields in the Frequency Range from 3 kHz to 300 GHz, 1999
●Australian Communications Authority Radiocommunications (Electromagnetic Radiation - Human Exposure)
Standard 1999 (applicable to wireless phones only)
To assure optimal radio performance and make sure human exposure to radio frequency electromagnetic energy
is within the guidelines set forth in the above standards, always adhere to the following procedures:
Phone operation
When placing or receiving a phone call, hold your phone as you would a wireline telephone. Speak directly into
the microphone.
Two-way radio operation
When using your radio hold the radio in a vertical position with the microphone 2.5 to 5 cm away from the lips.
Body-worn operation
To maintain compliance with FCC RF exposure guidelines, if you wear a radio on your body when transmitting,
always place the radio in a Motorola approved clip, holder, holster, case, or body harness for this product. Use of
non-Motorola-approved body worn accessories may exceed FCC RF exposure guidelines. If you do not use a
Motorola approved body-worn accessory and are not using the radio in the intended use positions along side of
the head in the phone mode or in front of the face in the two-way radio mode, then ensure the antenna and radio
is kept the following minimum distances from the body when transmitting:
●Phone or Two-way radio mode: 2.5 cm (one inch)
●Data operation using any data feature with or without an accessory cable: 2.5 cm (one inch) .
Antenna Care
Use only the supplied or an approved replacement antenna. Unauthorized antennas, modifications, or
attachments could damage the radio and may violate FCC regulations.
DO NOT hold the antenna when the radio is "IN USE". Holding the antenna affects call quality and may cause
the radio to operate at a higher power level than needed.
Approved Accessories
For a list of approved Motorola accessories please contact your dealer or local Motorola representative.
vi
ELECTROMAGNETIC INTERFERENCE/COMPATIBILITY
Facilities
To avoid electromagnetic interference and/or compatibility conflicts, turn off your radio in any facility where posted
notices instruct you to do so. Hospitals or health care facilities may be using equipment that is sensitive to
external RF energy.
Aircraft
When instructed to do so, turn off your radio when on board an aircraft. Any use of a radio must be in accordance
with applicable regulations per airline crew instructions.
Medical Devices
Pacemakers
The Health Industry Manufacturers Association recommends that a minimum separation of 15 cms
(6 inches) be maintained between a handheld wireless radio and a pacemaker.These recommendations are
consistent with those of the U.S. Food and Drug Administration.
Persons with pacemakers should:
●ALWAYS keep the radio more than 15 cms (6inches) from their pacemaker when the radio is turned ON.
●not carry the radio in the breast pocket.
●use the ear opposite the pacemaker to minimize the potential for interference.
●turn the radio OFF immediately if you have any reason to suspect that interference is taking place.
Hearing Aids
Some digital wireless radio products may interfere with some hearing aids. In the event of such interference, you
may want to consult your hearing aid manufacturer to discuss alternatives.
Other Medical Devices
If you use any other personal medical device, consult the manufacturer of your device to determine if it is
adequately shielded from RF energy. Your physician may be able to assist you in obtaining this information.
Safety and General
Use While Driving
Check the laws and regulations on the use of radios in the area where you drive. Always obey them.
When using your radio while driving, please:
●Give full attention to driving and to the road.
●Use hands-free operation, if available.
●Pull off the road and park before making or answering a call if driving conditions so require.
NOTE Nearly every electronic device is susceptible to electromagnetic interference (EMI) if
inadequately shielded, designed, or alternately configured for electromagnetic compatibility.
vii
OPERATIONAL WARNINGS
For Vehicles With An Air Bag
Potentially Explosive Atmospheres
Blasting Caps And Areas
OPERATIONAL CAUTIONS
Antennas
Do not use any portable radio that has a damaged antenna. If a damaged antenna comes into contact with your
skin, a minor burn can result.
Batteries
All batteries can cause property damage and/or bodily injury such as burns if a conductive material such as
jewellery, keys, or beaded chains touch exposed terminals. The conductive material may complete an electrical
circuit (short circuit) and become quite hot. Exercise care in handling any charged battery, particularly when
placing it inside a pocket, purse, or other container with metal objects.
MOBILE RADIO OPERATION AND EME EXPOSURE
To assure optimal radio performance and that human exposure to radio frequency electromagnetic energy is
within the guidelines referenced earlier in this document, transmit only when people outside the vehicle are at
least the minimum lateral distance away from a properly installed, externally-mounted antenna. Table 1 lists the
minimum distance for several different ranges of rated radio power.
WARNING: Do not place a portable radio in the area over an air bag or in the air bag
deployment area. Air bags inflate with great force. If a portable radio is placed in the air bag
deployment area and the air bag inflates, the radio product may be propelled with great force
and cause serious injury to occupants of vehicle.
NOTE The areas with potentially explosive atmospheres referred to above include fueling areas
such as below decks on boats, fuel or chemical transfer or storage facilities, areas where the
air contains chemicals or particles, such as grain, dust or metal powders, and any other
area where you would normally be advised to turn off your vehicle engine. Areas with poten-
tially explosive atmospheres are often but not always posted.
WARNING: Turn off your radio prior to entering any area with a potentially explosive
atmosphere, unless it is a radio type especially qualified for use in such areas as
"Intrinsically Safe" (for example, Factory Mutual, CSA, UL or CENELEC Approved). Do not
remove, install, or charge batteries in such areas. Sparks in a potentially explosive
atmosphere can cause an explosion or fire resulting in bodily injury or even death.
WARNING: To avoid possible interference with blasting operations, turn off your radio when
you are near electrical blasting caps, in a “blasting area” or in areas posted
“Turn off two-way radio”. Obey all signs and instructions.
Ta b l e 1 : Table 1 Rated Power and Lateral Distance
Radiated Power of
Vehicle-installed
Mobile Two-way
Minimum Lateral
Distance From
Transmitting
Less than 7 Watts 20 cm (8 Inches)
!
!
!
viii
ANTENNA INSTALLATION
Mobile Antennas
Recommended mobile antenna installations are limited to metal body vehicles at the centre of the roof and centre
of the trunk deck locations.
The antenna installation must additionally be in accordance with:
a) The requirements of the antenna manufacturer/supplier
b) Instructions in the Radio Installation Manual
Fixed Site Antennas
Mobile radio equipment is sometimes installed at a fixed location and operated as a control station or as a fixed
unit. In such cases the antenna installation must comply with the following requirements in order to assure
optimal performance and make sure human exposure to radio frequency electromagnetic energy is within the
guidelines set forth in the above standards:
●The antenna must be mounted outside the building
●Mount the antenna on a tower if at all possible
●If the antenna is to be mounted on a building then it must be mounted on the roof.
As with all fixed site antenna installations, it is the responsibility of the licensee to manage the site in accordance
with applicable regulatory requirements and may require additional compliance actions such as site survey
measurements, signage, and site access restrictions in order to insure that exposure limits are not exceeded.
7 to 15 Watts 30 cm (1 Ft)
16 to 50 Watts 60 cm (2 Ft)
More than 50 Watts 90 cm (3 Ft)
Table 1: Table 1 Rated Power and Lateral Distance
Radiated Power of
Vehicle-installed
Mobile Two-way
Minimum Lateral
Distance From
Transmitting
Chapter 1
INTRODUCTION
1.0 Scope of Manual
This manual is intended for use by service technicians familiar with similar types of equipment. It
contains service information required for the equipment described and is current as of the printing
date. Changes which occur after the printing date may be incorporated by a complete Manual
revision or alternatively as additions.
2.0 Warranty and Service Support
Motorola offers long term support for its products. This support includes full exchange and/or repair
of the product during the warranty period, and service/ repair or spare parts support out of warranty.
Any "return for exchange" or "return for repair" by an authorised Motorola Dealer must be
accompanied by a Warranty Claim Form. Warranty Claim Forms are obtained by contacting an
Authorised Motorola Dealer.
2.1 Warranty Period and Return Instructions
The terms and conditions of warranty are defined fully in the Motorola Dealer or Distributor or
Reseller contract. These conditions may change from time to time and the following notes are for
guidance purposes only.
In instances where the product is covered under a "return for replacement" or "return for repair"
warranty, a check of the product should be performed prior to shipping the unit back to Motorola.
This is to ensure that the product has been correctly programmed or has not been subjected to
damage outside the terms of the warranty.
Prior to shipping any radio back to the appropriate Motorola warranty depot, please contact
Customer Resources (Please see page 2 and page 3 in this Chapter). All returns must be
accompanied by a Warranty Claim Form, available from your Customer Services representative.
Products should be shipped back in the original packaging, or correctly packaged to ensure no
damage occurs in transit.
2.2 After Warranty Period
After the Warranty period, Motorola continues to support its products in two ways.
1. Motorola's Radio Aftermarket and Accessory Division (AAD) offers a repair service to both
end users and dealers at competitive prices.
2. AAD supplies individual parts and modules that can be purchased by dealers who are techni-
cally capable of performing fault analysis and repair.
NOTE Before operating or testing these units, please read the Safety Information Section in the
front of this manual.
1-2 INTRODUCTION
2.3 European Radio Support Centre (ERSC)
The ERSC Customer Information Desk is available through the following service numbers:
Austria: 06 60 75 41 Italy: 16 78 77 387
Belgium: 08 00 72 471 Luxemburg: 08 00 23 27
Denmark: 80 01 55 72 Netherlands: 60 22 45 13
Finland: 08 00 11 49 10 Norway: 80 01 11 15
France: 05 90 30 90 Portugal: 05 05 49 35 70
Germany: 08 00 18 75 240 Spain: 90 09 84 902
Greece: 00 80 04 91 29 020 Sweden: 02 07 94 307
UK: 08 00 96 90 95 Switzerland: 1 55 30 82
Ireland: 18 00 55 50 21 Iceland: 80 08 147
Or dial Customer Care Centre:
Tel: +49 6128 70 2618
Please use these numbers for repair enquiries only.
2.4 Parts Identification and Ordering
Request for help in identification of non-referenced spare parts should be directed to the Customer
Care Organisation of Motorola’s local area representation. Orders for replacement parts, kits and
assemblies should be placed directly on Motorola’s local distribution organisation or via Motorola
Online (Extranet).
2.5 EMEA Test Equipment Support
Information related to support and service of Motorola Test Equipment is available via Motorola
Online (Extranet), through the Customer Care Organisation of Motorola’s local area representation
or by calling the Motorola switchboard in Germany on telephone number: +49 6128 700.
Warranty and Service Support 1-3
2.6 Technical Support
Motorola Product Services is available to assist the dealer/distributors in resolving any malfunctions
which may be encountered.
2.7 Related Documents
The following documents are directly related to the use and maintainability of this product.
UK/Ireland - Richard Russell
Telephone: +44 (0) 1256 488 082
Fax: +44 01256 488 080
Email: BRR001@email.mot.com
France - Lionel Lhermitte
Telephone: +33 1 6929 5722
Fax: +33 1 6929 5904
Email: TXE037@email.mot.com
East Europe, Turkey and Central Asia
Siggy Punzenberger
Telephone: +49 (0) 6128 70 2342
Fax: +49 (0) 6128 95 1096
Email: TFG003@email.mot.com
Russian Regional Repair Operations:
Telephone: +7 095 785 01 89
Italy - Ugo Gentile
Telephone: +39 0 2822 0325
Fax: +39 0 2822 0334
Email: C13864@email.mot.com
Scandinavia
Telephone: +46 8 735 9282
Fax: +46 8 735 9280
Email: TCW275X@email.mot.com
Middle East & Africa - Ralph Schubert
Telephone: +33 (0) 4 4230 5887
Fax: +33 (0) 4 4230 4784
Email: ralph.schubert@motorola.com
Central Europe (Germany, Benelux,
Austria & Switzerland) - Customer Connect
Telephone: +49 (0) 6128 70 2248
Fax: +49 (0) 6128 95 1082
Email: cgiss.emea@europe.mot.com
Motorola Support Centre South Africa:
Telephone: +27 11 254 4000
Title Language Part Number
GM100 Series Product Manual English ENLN4147
GM300 Series Product Manual English
German
French
Italian
Spanish
Russian
ENLN4137
ENLN4138
ENLN4139
ENLN4140
ENLN4141
ENLN4142
GM600/GM1200 Series Product Manual English
German
French
Russian
ENLN4143
ENLN4144
ENLN4145
ENLN4146
1-4 INTRODUCTION
3.0 Radio Model Information
The model number and serial number are located on a label attached to the back of your radio. You
can determine the RF output power, frequency band, protocols, and physical packages. The
example below shows one mobile radio model number and its specific characteristics.
Table 1-1 Radio Model Number (Example: MDM25KHC9AN1AE)
Type of
Unit
Model
Series
Freq.
Band
Power
Level
Physical
Packages
Channel
Spacing Protocol Feature
Level
Model
Revision
Model
Package
MD M 25 K
VHF
(136-
174MHz)
H
1-25W
C
GM140,
GM340,
GM640
9
Program-
mable
AN
Conventional
5 Tone
1
GM140
GM340
GM640
AE
R
UHF 1
(403-
470MHz)
K
25-40W
40-60W
N
GM380,
GM1280
AA
Conventional
MDC
O
Databox
(5Tone)
S
UHF 2
(450-
527MHz)
F
GM160
GM360
GM660
CK
MPT
5
GM160
GM360
GM660
B
LB1
29-36MHz
A
Databox
8
GM380
GM1280
C
LB2
36-42MHz
7
Databox
(MPT)
D
LB3
42-50MHz
MD = Motorola Internal Use
M = Mobile
Chapter 2
MAINTENANCE
1.0 Introduction
This chapter of the manual describes:
■■ preventive maintenance
■■ safe handling of CMOS devices
■■ repair procedures and techniques
2.0 Preventive Maintenance
The radios do not require a scheduled preventive maintenance program; however, periodic visual
inspection and cleaning is recommended.
2.1 Inspection
Check that the external surfaces of the radio are clean, and that all external controls and switches
are functional. It is not recommended to inspect the interior electronic circuitry.
2.2 Cleaning
The following procedures describe the recommended cleaning agents and the methods to be
used when cleaning the external and internal surfaces of the radio. External surfaces include the
front cover, housing assembly, and battery case. These surfaces should be cleaned whenever a
periodic visual inspection reveals the presence of smudges, grease, and/or grime.
The only recommended agent for cleaning the external radio surfaces is a 0.5% solution of a mild
dishwashing detergent in water. The only factory recommended liquid for cleaning the printed
circuit boards and their components is isopropyl alcohol (70% by volume).
1. Cleaning External Plastic Surfaces
The detergent-water solution should be applied sparingly with a stiff, non-metallic, short-
bristled brush to work all loose dirt away from the radio. A soft, absorbent, lintless cloth or
tissue should be used to remove the solution and dry the radio. Make sure that no water
remains entrapped near the connectors, cracks, or crevices.
2. Cleaning Internal Circuit Boards and Components
Isopropyl alcohol may be applied with a stiff, non-metallic, short-bristled brush to dislodge
embedded or caked materials located in hard-to-reach areas. The brush stroke should
direct the dislodged material out and away from the inside of the radio. Make sure that
controls or tunable components are not soaked with alcohol. Do not use high-pressure
air to hasten the drying process since this could cause the liquid to collect in unwanted
places. Upon completion of the cleaning process, use a soft, absorbent, lintless cloth to
dry the area. Do not brush or apply any isopropyl alcohol to the frame, front or back cover.
NOTE Internal surfaces should be cleaned only when the radio is disassembled for servicing or
repair.
CAUTION: The effects of certain chemicals and their vapors can have harmful results on
certain plastics. Aerosol sprays, tuner cleaners, and other chemicals should be avoided.
!
2-2 MAINTENANCE
3.0 Safe Handling of CMOS and LDMOS
Complementary metal-oxide semiconductor (CMOS) devices are used in this family of radios.
CMOS characteristics make them susceptible to damage by electrostatic or high voltage charges.
Damage can be latent, resulting in failures occurring weeks or months later. Therefore, special
precautions must be taken to prevent device damage during disassembly, troubleshooting, and
repair.
Handling precautions are mandatory for CMOS circuits and are especially important in low
humidity conditions. DO NOT attempt to disassemble the radio without first referring to the CMOS
CAUTION paragraph in the Disassembly and Reassembly section of the manual.
4.0 General Repair Procedures and Techniques
Parts Replacement and Substitution
When damaged parts are replaced, identical parts should be used. If the identical replacement
component is not locally available, check the parts list for the proper Motorola part number and
order the component from the nearest Motorola Communications parts center listed in the “Piece
Parts” section of this manual.
Rigid Circuit Boards
The family of radios uses bonded, multi-layer, printed circuit boards. Since the inner layers are not
accessible, some special considerations are required when soldering and unsoldering
components. The through-plated holes may interconnect multiple layers of the printed circuit.
Therefore, care should be exercised to avoid pulling the plated circuit out of the hole.
When soldering near the 18-pin and 40-pin connectors:
■■ avoid accidentally getting solder in the connector.
■■ be careful not to form solder bridges between the connector pins
■■ closely examine your work for shorts due to solder bridges.
NOTE Always use a fresh supply of alcohol and a clean container to prevent contamination by
dissolved material (from previous usage).
General Repair Procedures and Techniques 2-3
Chip Components
Use either the RLN4062 Hot-Air Repair Station or the Motorola 0180381B45 Repair Station for
chip component replacement. When using the 0180381B45 Repair Station, select the TJ-65 mini-
thermojet hand piece. On either unit, adjust the temperature control to 370 °C (700 °F), and
adjust the airflow to a minimum setting. Airflow can vary due to component density.
■
■To remove a chip component:
1. Use a hot-air hand piece and position the nozzle of the hand piece approximately 0.3 cm
(1/8") above the component to be removed.
2. Begin applying the hot air. Once the solder reflows, remove the component using a pair
of tweezers.
3. Using a solder wick and a soldering iron or a power desoldering station, remove the
excess solder from the pads.
■
■To replace a chip component using a soldering iron:
1. Select the appropriate micro-tipped soldering iron and apply fresh solder to one of the
solder pads.
2. Using a pair of tweezers, position the new chip component in place while heating the
fresh solder.
3. Once solder wicks onto the new component, remove the heat from the solder.
4. Heat the remaining pad with the soldering iron and apply solder until it wicks to the
component. If necessary, touch up the first side. All solder joints should be smooth and
shiny.
■
■To replace a chip component using hot air:
1. Use the hot-air hand piece and reflow the solder on the solder pads to smooth it.
2. Apply a drop of solder paste flux to each pad.
3. Using a pair of tweezers, position the new component in place.
4. Position the hot-air hand piece approximately 0.3 cm (1/8” ) above the component and
begin applying heat.
5. Once the solder wicks to the component, remove the heat and inspect the repair. All
joints should be smooth and shiny.
2-4 MAINTENANCE
Shields
Removing and replacing shields will be done with the R1070 station with the temperature control
set to approximately 215°C (415°F) [230°C (445°F) maximum].
■
■To remove the shield:
1. Place the circuit board in the R1070 circuit board holder.
2. Select the proper heat focus head and attach it to the heater chimney.
3. Add solder paste flux around the base of the shield.
4. Position the shield under the heat-focus head.
5. Lower the vacuum tip and attach it to the shield by turning on the vacuum pump.
6. Lower the focus head until it is approximately 0.3 cm (1/8”) above the shield.
7. Turn on the heater and wait until the shield lifts off the circuit board.
8. Once the shield is off, turn off the heat, grab the part with a pair of tweezers, and turn off
the vacuum pump.
9. Remove the circuit board from the R1070 circuit board holder.
■
■To replace the shield:
1. Add solder to the shield if necessary, using a micro-tipped soldering iron.
2. Next, rub the soldering iron tip along the edge of the shield to smooth out any excess
solder. Use solder wick and a soldering iron to remove excess solder from the solder
pads on the circuit board.
3. Place the circuit board back in the R1070 circuit board holder.
4. Place the shield on the circuit board using a pair of tweezers.
5. Position the heat-focus head over the shield and lower it to approximately 0.3 cm (1/8”)
above the shield.
6. Turn on the heater and wait for the solder to reflow.
7. Once complete, turn off the heat, raise the heat-focus head and wait approximately one
minute for the part to cool.
8. Remove the circuit board and inspect the repair. No cleaning should be necessary.
Notes For All Schematics and Circuit Boards 2-5
5.0 Notes For All Schematics and Circuit Boards
* Component is frequency sensitive. Refer to the Electrical Parts List for value and usage.
1. Unless otherwise stated, resistances are in Ohms (k = 1000), and capacitances are in picofarads
(pF) or microfarads (µF).
2. DC voltages are measured from point indicated to chassis ground using a Motorola DC
multimeter or equivalent. Transmitter measurements should be made with a 1.2 µH choke in
series with the voltage probe to prevent circuit loading.
3. Interconnect Tie Point Legend:
16_8MHz 16.8MHz Reference Frequency
3V3 Regulated 3.3V Supply Voltage for Voice Storage
5V Regulated 5V Supply Voltage for RF Circuitry
5V Regulated 5V Supply Voltage (Control Head)
5V RF Regulated 5V Supply Voltage for RF Circuitry
5V SOURCE 5V Signal to Switch On Control Head
5VD Regulated 5V Supply Voltage for Digital Circuitry
9V3 Regulated 9.3V Supply Voltage
9V3FLT Filtered 9.3V Supply Voltage
A+ 13.2V Supply Voltage
ADDR *P Address Lines
AN Analog Lines to Analog to Digital Converter
ANALOG INPUT 2 External Keypad Matrix Column Signal
ANALOG INPUT 3 External Keypad Matrix Row Signal
BATTERY VOLTAGE Battery Voltage Sense Line
BL A GREEN Back Light Anode Green
BL A RED Back Light Anode Red
BL GREEN Green Back Light Control
BL K GREEN Back Light Cathode Green
BL K RED Back Light Cathode Red
BL KP Green Green Keypad Back Light Control
BL KP RED Red Keypad Back Light Control
BL LCD GREEN Green Display Back Light Control
BL LCD RED Red Display Back Light Control
BL RED Red Back Light Control
BOOT CNTRL Bootstrap Mode Enable Signal
BOOT MODE Boot Mode Select
BOOT PWR ON Control Head Switch On Signal
BOOT SCI RX Serial Communication Interface Receive Line
BOOT SCI TX Serial Communication Interface Transmit Line
BOOT VPP Boot Mode Select
BUS+ Bi-directional Serial Communication Line
BWSELECT Signal to select between the Ceramic Filter Pairs
2-6 MAINTENANCE
CH ACT Channel Activity Indicator Signal (Fast Squelch)
CH KP ID Control Head Keypad ID (Data) Lines
CH REQUEST Control Head Request from Control Head *P
CLK Clock Signal
CNTLVLTG PA Power Control Voltage
CNTR AUDIO Audio Lines of the Controller
COL x Keypad Matrix Column x
CSX Chip Select Line PCIC / FRACN
DATA Data Signal
DC POWER ON Electronic Switching On or Off of the Radio's Voltage Regulators
DISCAUDIO Audio Output Signal from the Receiver IC
ECLK Clock (not used)
EE CS EEPROM Chip Select
EMERGENCY CONTROL Emergency Line to switch on the Radio's Voltage Regulators
EXP BD REQ Service Request Line from Expansion Board
EXP1 CS Expansion Board Chip Select 1
EXP2 CS Expansion Board Chip Select 2
EXT KP COL External Keypad Matrix Column Signal
EXT KP ROW External Keypad Matrix Row Signal
EXT MIC External (from Accessory Connector) Microphone Input
EXT SWB+ External Switched 13.2V Supply Voltage
F1200 Interrupt Line from ASFIC CMP
FECTRL 1 Control Voltage for Front End Filter
FECTRL 2 Control Voltage for Front End Attenuator Switch
FLASH CE Flash Chip Select
FLASH OE Flash Output Enable
FLAT RX SND Option Board Audio Output Signal
FLAT TX RTN Flat TX Input from Option Board and Accessory Connector
FLT A+ Filtered 13.2 V Supply Voltage
GP x IN General Purpose Input x
GP x IN ACC y General Purpose Input x from Accessory Connector Pin y
GP x IN OUT ACC y General Purpose Input /Output x from Accessory Connector Pin
y
GP x OUT General Purpose Output x
GP x OUT ACC y General Purpose Input x from Accessory Connector Pin y
GPIO General Purpose Input Output Lines
HANDSET AUDIO Handset Audio Output
HOOK Hang-up Switch Input
HSIO High Speed Clock In / Data Out
IF First Intermediate Frequency Signal
IGNITION CONTROL Ignition Line to switch on the Radio's Voltage Regulators
Notes For All Schematics and Circuit Boards 2-7
IN 5V RF REG Supply Voltage for 5V Regulator in RF Section
INT KP COL Internal Keypad Matrix Column Signal
INT KP ROW Internal Keypad Matrix Row Signal
INT MIC Internal (from Control Head) Microphone Input
INT SWB Internal Switched 13.2V Supply Voltage
INT SWB+ Internal Switched 13.2V Supply Voltage
IRQ Interrupt Request from Control Head
K9V1 9.1V in Transmit Mode
KEYPAD ID Keypad Identification Line
LCD A0 LCD Control / Display Data Select
LCD CS LCD Chip Select
LCD DATA LCD Data Lines
LCD E RD LCD Enable Read
LCD RW WR LCD Read Write Control
LED CNTRL LED Control Lines
LED GREEN Green LED Control
LED RED Red LED Control
LED YELLOW Yellow LED Control
LOCK Lock Detect Signal from Synthesizer
LSIO Low Speed Clock In / Data Out
LVZIF CS LVZIF Chip Select (not used)
MIC Microphone Input
MISO Serial Peripheral Interface Receive Line
MODIN Modulation Signal into the Synthesizer
MOSBIAS 2 PA Bias Voltage for second Stage
MOSBIAS 3 PA Bias Voltage for third Stage
NOISE BLNKR Noise Blanker Enable (Low Band only)
ON OFF CONTROL Service Request Line from Control Head / Manual Switching On
of the Radio's Voltage Regulators
ON OFF SENSE (Control Head)On Off Sense Line to Control Head *P
ON OFF SENSE (Controller) Service Request Line from Control Head
OPT CS Option Board Chip Select
OPT PTT PTT from Option Board
PA PWR SET ASFIC Output Voltage to set the Transmitter Power
PA SWB Switches Supply Voltage for PA Current Control Circuitry
PASUPVLTG 13.2 V Supply Voltage of the Transmitter PA
PCIC MOSBIAS 1 PA Bias Voltage for first Stage
PRESC Prescaler Signal from VCO to Synthesizer
PTT IRDEC Microphone PTT Input
PTT IRDECODER Microphone PTT Input
R W Read Write Signal for RAM / Flash
2-8 MAINTENANCE
RAM CS RAM Ship Select
RDY Service Request Line from Option Board
REF CS Reference Chip Select (not used)
RESET Reset Line
ROW x Keypad Matrix Row x
RSSI Received Signal Strength Indicator
RX ADAPT Flat TX Path Disable during Transmitter Key-up
RX AUD RTN Option Board Input / Output of Receiver Audio Path
RX FLAT FILTERED AUDIO Flat or Filtered Audio to Accessory Connector
RXIN RF Signal from Antenna Switch into the Receiver
RXINJ RF Signal from the VCO into the Mixer
SCI RX Serial Communication Interface Receive Line
SCI TX Serial Communication Interface Transmit Line
SPI Serial Peripheral Interface Bus
SPKR- Negative Audio PA Speaker Output
SPKR+ Positive Audio PA Speaker Output
SQ DET Squelch Detect Signal
SYN *P Clock Signal
TEMP SENSE Temperature Sense Line for LCD
TEMPSENSE Temperature Sense Line from PA to *P
TRB TX/RX VCO Switch Signal
TX AUD RTN Option Board Output to Transmit Audio Path
TX AUD SND Microphone Audio to Option Board
TXINJ RF Signal from the VCO into the Transmitter PA
U DRIVER Supply Voltage for PA Driver
U PREDRIVER Supply Voltage for PA Pre-driver
UNSW 5V Permanent 5V Supply
URX SND Filtered Audio Signal to Option Board
VAG 2.5V Reference Voltage for Analog Circuitry
VCOBIAS 1 Switch Signal from Synthesizer
VCOBIAS 2 Switch Signal from Synthesizer
VCOMOD Modulation Signal into VCO
VCTRL VCO Frequency Control Voltage
VDDA Regulated 5V for Digital Circuitry in RF Section
VOLTAGE SENSE Voltage Sense Line from LCD
VOLUME Volume Pot Output
VOX Voice Operated Transmit Level
VPP Boot Mode Select
VS AUDIOSEL Switch Signal to Enable Option Board Audio Output Signal
VS GAINSEL Voice Storage Gain Select Line
VS INT Voice Storage Interrupt Line
Notes For All Schematics and Circuit Boards 2-9
VS MIC Voice Storage Audio Signal into Microphone Path
VS RAC Voice Storage Row Address Clock Signal
VSF Voltage Super Filtered (5V)
VSTBY 5V Supply for *P when the Radio is switched off
4-LAYER CIRCUIT BOARD DETAIL VIEWING
COPPER STEPS IN PROPER LAYER SEQUENCE
LAYER 1 (L1)
LAYER 2 (L2)
LAYER 3 (L3)
LAYER 4 (L4)
INNER LAYERS
SIDE 1
SIDE 2
2-10 MAINTENANCE
Chapter 3
SERVICE AIDS
1.0 Recommended Test Tools
Table 3-1 lists the service aids recommended for working on the radio. While all of these items are
available from Motorola, most are standard workshop equipment items, and any equivalent item
capable of the same performance may be substituted for the item listed.
Table 3-1 Service Aids
Motorola Part
Number Description Application
RLN4460_ Portable Test Set Enables connection to audio/accessory jack.
Allows switching for radio testing.
RKN4081_ Programming Cable with
Internal RIB Includes radio interface box (RIB) capability.
RLN4853_ 10 to 20 Pin Adapter Connects RKN4081_ to the radio accessory
connector.
RKN4083_ Mobile Programming/Test
Cable Connects radio to RIB (RLN4008_).
GTF374_ Program Cable Connects RIB to Radio microphone input
RLN4008_ Radio Interface Box Enables communications between radio and
computer’s serial communications adapter.
HLN8027_ Mini UHF to BNC Adaptor Adapts radio antenna port to BNC cabling of
test equipment.
GPN6133_ Power Supply Provides the radio with power when bench
testing.
EPN4040_ Wall-Mounted Power Supply Used to supply power to the RIB (UK).
EPN4041_ Wall-Mounted Power Supply Used to supply power to the RIB (Euro)
8180384J59 Housing Eliminator (short) Test Fixture used to bench test the radio pcb
8180384L95 Housing Eliminator
(short + top) Test Fixture used to bench test the radio pcb.
(Radio using pressure pads to retain pcb)
8180384J60 Housing Eliminator
(medium) Test Fixture used to bench test the radio pcb
8180384J61 Housing Eliminator (long) Test Fixture used to bench test the radio pcb
3080369B71 Computer Interface Cable Connects the RIB to the Computer (25-pin)
3080369B72 Computer Interface Cable Connects the RIB to the Computer 9-pin
(Use for IBM PC AT - other IBM models use
the B71 cable above)
6686119B01 Removal Tool Assists in the removal of radio control head.
3-2 SERVICE AIDS
2.0 Test Equipment
Table 3-2 lists test equipment required to service the radio and other two-way radios.
Table 3-2 Recommended Test Equipment
Motorola Part
Number Description Characteristics Application
R2600_NT Comms System Analyzer
(non MPT) This monitor will
substitute for items
with an asterisk*
Frequency/deviation
meter and signal
generator for
widerange
troubleshooting and
alignment
R2680_NT Comms System Analyzer
( MPT1327) to be ordered
with
RLN1022_ (H/W)
RLN1023_ (S/W)
This monitor will
substitute for items
with an asterisk*.
Frequency/deviation
meter and signal
generator for
widerange
troubleshooting and
alignment
*R1072_ Digital Multimeter AC/DC voltage and
current
measurements
*R-1377_ AC Voltmeter 100µV to 300V, 5Hz -
1MHz, 10Megohm
input impedance
Audio voltage
measurements
WADN133 Delay Oscilloscope 2 Channel 40MHz
bandwidth,
5mV/cm - 20 V/cm
Waveform
measurements
R1440_
0180305F17
0180305F31
0180305F39
RLN4610
T1013_
Wattmeter,
Plug-in Elements
Plug-in Elements
Plug-in Elements
Carry case
RF Dummy Load
Thruline 50-Ohm,
±5% accuracy
100W, 25 - 60MHz
25W, 100-250MHz
10W, 200-250MHz
Wattmeter and
6 elements
Transmitter power
output
measurements
S1339_ RF Millivolt Meter 100mV to 3 VRF.
10kHz to 1.2GHz RF level
measurements
R1011_/220V 220V Power Supply 0 - 40V 0 - 40A Programmable
Professional Radio
GM Series
Controlhead
Service Information
Issue: August 2002
ii
Computer Software Copyrights
The Motorola products described in this manual may include copyrighted Motorola computer programs stored
in semiconductor memories or other media. Laws in the United States and other countries preserve for
Motorola certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or
reproduce in any form, the copyrighted computer program. Accordingly, any copyrighted Motorola computer
programs contained in the Motorola products described in this manual may not be copied or reproduced in
any manner without the express written permission of Motorola. Furthermore, the purchase of Motorola
products shall not be deemed to grant, either directly or by implication, estoppel or otherwise, any license
under the copyrights, patents or patent applications of Motorola, except for the normal non-exclusive royalty-
free license to use that arises by operation of law in the sale of a product.
iii
Table of Contents
Chapter 1 MODEL OVERVIEW
1.0 GM140/GM340/GM640 Models...........................................................................1-1
2.0 GM160/GM360/GM660 Models...........................................................................1-1
3.0 GM380/GM1280 Models......................................................................................1-2
Chapter 2 THEORY OF OPERATION
1.0 Introduction ..........................................................................................................2-1
2.0 Controlhead Model for GM140, GM340 and GM640 ...........................................2-1
2.1 Power Supplies...............................................................................................2-1
2.2 Power On / Off................................................................................................2-1
2.3 Microprocessor Circuit....................................................................................2-1
2.4 SBEP Serial Interface.....................................................................................2-1
2.5 Keypad Keys ..................................................................................................2-1
2.6 Status LED and Back Light Circuit..................................................................2-3
2.7 Microphone Connector Signals ......................................................................2-3
2.8 Speaker ..........................................................................................................2-4
2.9 Electrostatic Transient Protection...................................................................2-4
3.0 Controlhead Model for GM160, GM360 and GM660 ...........................................2-4
3.1 Power Supplies...............................................................................................2-4
3.2 Power On / Off................................................................................................2-4
3.3 Microprocessor Circuit....................................................................................2-5
3.4 SBEP Serial Interface.....................................................................................2-5
3.5 Keypad Keys ..................................................................................................2-6
3.6 Status LED and Back Light Circuit..................................................................2-6
3.7 Liquid Crystal Display (LCD) ..........................................................................2-6
3.8 Microphone Connector Signals ......................................................................2-6
3.9 Speaker ..........................................................................................................2-7
3.10 Electrostatic Transient Protection ...................................................................2-8
4.0 Controlhead Model for GM380 and GM1280.......................................................2-8
4.1 Power Supplies...............................................................................................2-8
4.2 Voltage Regulator Circuit................................................................................2-8
4.3 Power On / Off................................................................................................2-9
4.4 Microprocessor Circuit....................................................................................2-9
4.5 SBEP Serial Interface...................................................................................2-10
4.6 Keypad Keys ................................................................................................2-10
4.7 Status LED and Back Light Circuit................................................................2-10
4.8 Liquid Crystal Display (LCD) ........................................................................2-11
4.9 Microphone Connector Signals ....................................................................2-11
4.10 Speaker ........................................................................................................2-12
4.11 Electrostatic Transient Protection .................................................................2-12
iv
Chapter 3 TROUBLESHOOTING CHARTS
1.0 Troubleshooting Chart for Controlhead GM140/340/640 ....................................3-1
1.1 On/Off ................................................................................................................. 3-1
1.2 Microprocessor ...................................................................................................3-2
2.0 Troubleshooting Chart for Controlhead GM160/360/660 ....................................3-3
2.1 On/Off ................................................................................................................. 3-3
2.2 Microprocessor ...................................................................................................3-4
2.3 Display ................................................................................................................3-5
2.4 Backlight .............................................................................................................3-6
3.0 Troubleshooting Chart for Controlhead GM380/1280 .........................................3-7
3.1 On/Off ................................................................................................................. 3-7
3.2 Microprocessor ...................................................................................................3-8
3.3 Microprocessor ...................................................................................................3-9
3.4 Display ..............................................................................................................3-10
3.5 Keypad Backlight ..............................................................................................3-11
3.6 Display Backlight ..............................................................................................3-12
Chapter 4 CONTROLHEAD PCB/SCHEMATICS/PARTS LISTS
1.0 Allocation of Schematics and Circuit Boards .......................................................4-1
2.0 Controlhead GM140/340/640 - PCB 8486146B07 / Schematics.........................4-3
2.1 Controlhead PCB 8486146B07 - Parts List ......................................................... 4-6
3.0 Controlhead GM160/360/660 - PCB 8486155B06 / Schematics ........................4-7
3.1 Controlhead PCB 8486155B06 - Parts List ...................................................... 4-12
4.0 Controlhead GM380/1280 - PCB 8486178B03/04 / Schematics....................... 4-13
4.1 Controlhead PCB 8486178B03/04 - Parts List .................................................. 4-18
Chapter 1
OVERVIEW
1.0 GM140/GM340/GM640 Models (GCN6112_)
The Controlhead contains the internal speaker, the on/off/volume knob, the microphone connector,
several buttons to operate the radio and several indicator Light Emitting Diodes (LED) to inform the
user about the radio status. To control the LED’s and to communicate with the host radio the control
head uses the Motorola 68HC11E9 microprocessor.
2.0 GM160/GM360/GM660 Models
(GCN6114-GM160 / GCN6120-GM360/660)
The Controlhead contains the internal speaker, the on/off/volume knob, the microphone connector,
several buttons to operate the radio, several indicator Light Emitting Diodes (LED) to inform the user
about the radio status, and a 14 character Liquid Crystal Display (LCD) for alpha - numerical
information e.g. channel number or call address name. To control the LED’s and the LCD, and to
communicate with the host radio the control head uses the Motorola 68HC11E9 microprocessor
1-2 overview
3.0 GM380/GM1280 Models (GCN6121_)
The Controlhead contains the on/off/volume knob, the microphone connector, several buttons to
operate the radio, several indicator Light Emitting Diodes (LED) to inform the user about the radio
status, and a Liquid Crystal Display (LCD) with 21 pre - defined symbols and a 32*96 dot matrix for
graphical or alpha - numerical information e.g. channel number, select code, call address name. To
control the LED’s and the LCD, and to communicate with the host radio the control head uses the
Motorola 68HC11K4 microprocessor.
4.0 Databox Models (GCN6116_)
The Databox radios are transceiver models that have a databox radio blank head (a non-functional
plastic cover) instead of a control head. These models are planned for special applications to be
used mainly in conjunction with a radio modem.
Chapter 2
THEORY OF OPERATION
1.0 Introduction
This Chapter provides a detailed theory of operation for the Controlhead circuits. For details of the
trouble shooting refer to the related Section of this manual.
2.0 Controlhead Model for GM140, GM340 and GM640
The controlhead contains the internal speaker, the on/off/volume knob, the microphone connector,
several buttons to operate the radio and several indicator Light Emitting Diodes (LED) to inform the
user about the radio status. To control the LED’s and to communicate with the host radio the control-
head uses the Motorola 68HC11E9 microprocessor.
2.1 Power Supplies
The power supply to the controlhead is taken from the host radio’s FLT A+ voltage via connector
J0801 pin 3 and the regulated +5V via connector J0801 pin 7. The voltage FLT A+ is at supply
voltage level and is used for the LED’s, the back light and to power up the radio via on / off / volume
knob. The stabilized +5 volt is used for the microprocessor and the keypad buttons. The voltage USW
5V derived from the FLT A+ voltage and stabilized by the series combination of R0822, VR0822 is
used to buffer the internal RAM of the microprocessor (U0831). C0822 allows the supply voltage
level to be disconnected for a couple of seconds without losing RAM parameters. Dual diode D0822
prevents radio circuitry from discharging this capacitor. When the supply voltage is applied to the
radio, C0822 is charged via R0822 and D0822. To avoid, that the µP enters the wrong mode when
the radio is switched on while the voltage across C0822 is still too low, the regulated 5V charge
C0822 via diode D0822.
2.2 Power On / Off
The On/Off/Volume knob when pressed switches the radio’s voltage regulators on by connecting line
ON OFF CONTROL to line UNSW 5V via D0821. Additionally, 5 volts at the base of digital transistor
Q0822 informs the controlhead’s microprocessor about the pressed knob. The microprocessor
asserts pin 62 and line CH REQUEST low to hold line ON OFF CONTROL at 5 volts via Q0823 and
D0821. The high line ON OFF CONTROL also informs the host radio, that the controlhead’s
microprocessor wants to send data via SBEP bus. When the radio returns a data request message,
the microprocessor will inform the radio about the pressed knob. If the radio was switched off, the
radio’s µP will switch it on and vice versa. If the On/Off/Volume knob is pressed while the radio is on,
the software detects a low state on line ON OFF SENSE, the radio is alerted via line ON OFF
CONTROL and sends a data request message. The controlhead µP will inform the radio about the
pressed knob and the radio’s µP will switch the radio off.
2.3 Microprocessor Circuit
The controlhead uses the Motorola 68HC11E9 microprocessor (µP) (U0831) to control the LED’s
and to communicate with the host radio. RAM and ROM are contained within the microprocessor
itself.
The microprocessor generates it’s clock using the oscillator inside the microprocessor along with a 8
MHz ceramic resonator (U0833) and R0920.
2-2 THEORY OF OPERATION
The microprocessor’s RAM is always powered to maintain parameters such as the last operating
mode. This is achieved by maintaining 5V at µP pin 25. Under normal conditions, when the radio is
off, USW 5V is formed by FLT A+ running to D0822. C0822 allows the battery voltage to be
disconnected for a couple of seconds without losing RAM parameters. Diode D0822 prevents radio
circuitry from discharging this capacitor.
There are 8 analogue to digital converter ports (A/D) on the µP . They are labeled within the device
block as PE0-PE7. These lines sense the voltage level ranging from 0 to 5V of the input line and
convert that level to a number ranging from 0 to 255 which can be read by the software to take
appropriate action.
Pin VRH is the high reference voltage for the A/D ports on the µP . If this voltage is lower than +5V
the A/D readings will be incorrect. Likewise pin VRL is the low reference for the A/D ports. This line is
normally tied to ground. If this line is not connected to ground, the A/D readings will be incorrect.
The microprocessor can determine the used keypad type and the controlhead ID by reading the
levels at ports PC0 – PC7. Connections JU0852/3/4 are provided by the individual keypads.
The MODB / MODA input of the µP must be at a logic „1" for it to start executing correctly. The XIRQ
and the IRQ pins should also be at a logic „1".
Voltage sense device U0832 provides a reset output that goes to 0 volts if the regulated 5 volts goes
below 4.5 volts. This is used to reset the controller to prevent improper operation.
2.4 SBEP Serial Interface
The host radio (master) communicates to the controlhead µP (slave) through its SBEP bus. This bus
uses only line BUS+ for data transfer. The line is bi-directional meaning that either the radio or the
controlhead µP can drive the line. The microprocessor sends serial data via pin 50 and D0831 and
it reads serial data via pin 47. Whenever the microprocessor detects activity on the BUS+ line, it
starts communication.
When the host radio needs to communicate to the controlhead µP , it sends data via line BUS+. Any
transition on this line generates an interrupt and the µP starts communication. The host radio may
send data like LED and back light status or it may request the controlhead ID or the keypad ID.
When the controlhead µP wants to communicate to the host radio, the µP brings request line CH
REQUEST to a logic „0" via µP pin 62. This switches on Q0823, which pulls line ON OFF
CONTROL high through diode D0821. A low to high transition on this line informs the radio, that the
controlhead requires service. The host radio then sends a data request message via BUS+ and the
controlhead µP replies with the data it wanted to send. This data can be information like which key
has been pressed or that the volume knob has been rotated.
The controlhead µP monitors all messages sent via BUS+, but ignores any data communication
between host radio and CPS or Universal Tuner.
2.5 Keypad Keys
The controlhead keypad is a 6 - key keypad. All keys are configured as 2 analogue lines read by µP
pins 13 and 15 . The voltage on the analogue lines varies between 0 volts and +5 volts depending on
which key has been pressed. If no key is pressed, the voltage at both lines will be 5 volts. The key
configuration can be thought of as a matrix, where the two lines represent one row and one column.
Each line is connected to a resistive divider powered by +5 volts. If a button is pressed, it will connect
one specific resistor of each divider line to ground level and thereby reduce the voltages on the
analogue lines The voltages of the lines are A/D converted inside the µP (ports PE 0 - 1) and specify
the pressed button. To determine which key is pressed, the voltage of both lines must be considered.
Controlhead Model for GM140, GM340 and GM640 2-3
An additional pair of analogue lines and A/D µP ports (PE 3 – 2) is available to support a keypad
microphone, connected to the microphone connector J0811. Any microphone key press is processed
the same way as a key press on the controlhead.
2.6 Status LED and Back Light Circuit
All indicator LED’s (red, yellow, green) are driven by current sources. To change the LED status the
host radio sends a data message via SBEP bus to the controlhead µP . The controlhead µP
determines the LED status from the received message and switches the LED’s on or off via port PB
7 – 0 and port PA4. The LED status is stored in the µP ’s memory. The LED current is determined by
the resistor at the emitter of the respective current source transistor.
The back light for the keypad is controlled by the host radio the same way as the indicator LED’s
using µP port PA 5. The µP can switch the back light on and off under software control. The keypad
back light current is drawn from the FLT A+ source and controlled by 2 current sources. The LED
current is determined by the resistor at the emitter of the respective current source transistor.
2.7 Microphone Connector Signals
Signals BUS+, PTT IRDEC, HOOK, MIC, HANDSET AUDIO, FLT A+, +5V and 2 A/D converter
inputs are available at the microphone connector J0811. Signal BUS+ (J0811-7) connects to the
SBEP bus for communication with the CPS or the Universal Tuner. Line MIC (J0811-5) feeds the
audio from the microphone to the radio’s controller via connector J0801-4. Line HANDSET AUDIO
(J0811-8) feeds the receiver audio from the controller (J0801-6) to a connected handset. FLT A+,
which is at supply voltage level, and +5V are used to supply any connected accessory like a
microphone or a handset.
The 2 A/D converter inputs (J0811-9/10) are used for a microphone with keypad. A pressed key will
change the dc voltage on both lines. The voltages depend on which key is pressed. The µP
determines from the voltage on these lines which key is pressed and sends the information to the
host radio.
Line PTT IRDEC (J0811-6) is used to key up the radio’s transmitter. While the PTT button on a
connected microphone is released, line PTT IRDEC is pulled to +5 volts level by R0843. Transistor
Q0843 is switched on and causes a low at µP port PA2. When the PTT button is pressed, signal PTT
IRDEC is pulled to ground level. This switches off Q0843 and the resulting high level at µP port PA2
informs the µP about the pressed PTT button. The µP will inform the host radio about any status
change on the PTT IRDEC line via SBEP bus.
When line PTT IRDEC is connected to FLT A+ level, transistor Q0821 is switched on through diode
VR0821 and thereby pulls the level on line ON OFF CONTROL to FLT A+ level. This switches on the
radio and puts the radio’s µP in bootstrap mode. Bootstrap mode is used to load the firmware into
the radio’s flash memory (See controller subsection for more details).
The HOOK input (J0811-3) is used to inform the µP when the microphone´s hang-up switch is
engaged. Dependent on the CPS programming the µP may take actions like turning the audio PA on
or off. While the hang up switch is open, line HOOK is pulled to +5 volts level by R0841. Transistor
Q0841 is switched on and causes a low at µP port PA1. When the HOOK switch is closed, signal
HOOK is pulled to ground level. This switches off R0841and the resulting high level at µP port PA1
informs the µP about the closed hang up switch. The µP will inform the host radio about any status
change on the HOOK line via SBEP bus.
2-4 THEORY OF OPERATION
2.8 Speaker
The controlhead contains a speaker for the receiver audio. The receiver audio signal from the
differential audio output of the audio amplifier located on the radio’s controller is fed via connector
J0801-10, 11 to the speaker connector P0801 pin 1 and pin 2. The speaker is connected to the
speaker connector P0801. The controlhead speaker can be disconnected if an external speaker,
connected on the accessory connector, is used.
2.9 Electrostatic Transient Protection
Electrostatic transient protection is provided for the sensitive components in the controlhead by
diodes VR0811 VR00812 VR0816 - VR0817. The diodes limit any transient voltages to tolerable
levels. The associated capacitors provide Radio Frequency Interference (RFI) protection.
3.0 Controlhead Model for GM160, GM360 and GM660
The controlhead contains the internal speaker, the on/off/volume knob, the microphone connector,
several buttons to operate the radio, several indicator Light Emitting Diodes (LED) to inform the user
about the radio status, and a 14 character Liquid Crystal Display (LCD) for alpha - numerical
information e.g. channel number or call address name. To control the LED’s and the LCD, and to
communicate with the host radio the controlhead uses the Motorola 68HC11E9 microprocessor.
3.1 Power Supplies
The power supply to the controlhead is taken from the host radio’s FLT A+ voltage via connector
J0801 pin 3 and the regulated +5V via connector J0801 pin 7. The voltage FLT A+ is at battery level
and is used for the LED’s, the back light and to power up the radio via on / off / volume knob. The
stabilized +5 volt is used for the microprocessor, the display, the display driver and the keypad
buttons. The voltage USW 5V derived from the FLT A+ voltage and stabilized by the series
combination of R0822, VR0822 is used to buffer the internal RAM of the microprocessor (U0831).
C0822 allows the battery voltage to be disconnected for a couple of seconds without losing RAM
parameters. Dual diode D0822 prevents radio circuitry from discharging this capacitor. When the
supply voltage is applied to the radio, C0822 is charged via R0822 and D0822. To avoid that the µP
enters the wrong mode when the radio is switched on while the voltage across C0822 is still too low,
the regulated 5V charge C0822 via diode D0822.
3.2 Power On / Off
The On/Off/Volume knob when pressed switches the radio’s voltage regulators on by connecting line
ON OFF CONTROL to line UNSW 5V via D0821. Additionally, 5 volts at the base of digital transistor
Q0822 informs the controlhead’s microprocessor about the pressed knob. The microprocessor
asserts pin 62 and line CH REQUEST low to hold line ON OFF CONTROL at 5 volts via Q0823 and
D0821. The high line ON OFF CONTROL also informs the host radio, that the controlhead’s
microprocessor wants to send data via SBEP bus. When the radio returns a data request message,
the microprocessor will inform the radio about the pressed knob. If the radio was switched off, the
radio’s µP will switch it on and vice versa. If the On/Off/Volume knob is pressed while the radio is on,
the software detects a low state on line ON OFF SENSE, the radio is alerted via line ON OFF
CONTROL and sends a data request message. The controlhead µP will inform the radio about the
pressed knob and the radio’s µP will switch the radio off.
Controlhead Model for GM160, GM360 and GM660 2-5
3.3 Microprocessor Circuit
The controlhead uses the Motorola 68HC11E9 microprocessor (µP) (U0831) to control the LED’s
and the LCD and to communicate with the host radio. RAM and ROM are contained within the
microprocessor itself.
The microprocessor generates it’s clock using the oscillator inside the microprocessor along with a 8
MHz ceramic resonator (U0833) and R0920 .
The microprocessor’s RAM is always powered to maintain parameters such as the last operating
mode. This is achieved by maintaining 5V at µP pin 25 . Under normal conditions, when the radio is
off, USW 5V is formed by FLT A+ running to D0822. C0822 allows the battery voltage to be
disconnected for a couple of seconds without losing RAM parameters. Diode D0822 prevents radio
circuitry from discharging this capacitor.
There are 8 analogue to digital converter ports (A/D) on the µP . They are labeled within the device
block as PE0-PE7. These lines sense the voltage level ranging from 0 to 5V of the input line and
convert that level to a number ranging from 0 to 255 which can be read by the software to take
appropriate action.
Pin VRH is the high reference voltage for the A/D ports on the µP . If this voltage is lower than +5V
the A/D readings will be incorrect. Likewise pin VRL is the low reference for the A/D ports. This line is
normally tied to ground. If this line is not connected to ground, the A/D readings will be incorrect.
The microprocessor can determine the used keypad type and the controlhead ID by reading the
levels at ports PC0 – PC7. Connections JU0852/3/4 are provided by the individual keypads.
The MODB / MODA input of the µP must be at a logic „1" for it to start executing correctly. The XIRQ
and the IRQ pins should also be at a logic „1".
Voltage sense device U0832 provides a reset output that goes to 0 volts if the regulated 5 volts goes
below 4.5 volts. This is used to reset the controller to prevent improper operation.
3.4 SBEP Serial Interface
The host radio (master) communicates to the controlhead µP (slave) through its SBEP bus. This bus
uses only line BUS+ for data transfer. The line is bi-directional, meaning that either the radio or the
controlhead µP can drive the line. The microprocessor sends serial data via pin 50 and D0831 and it
reads serial data via pin 47. Whenever the microprocessor detects activity on the BUS+ line, it starts
communication.
When the host radio needs to communicate to the controlhead µP , it sends data via line BUS+. Any
transition on this line generates an interrupt and the µP starts communication. The host radio may
send data like display information, LED and back light status or it may request the controlhead ID or
the keypad ID.
When the controlhead µP wants to communicate to the host radio, the µP brings request line CH
REQUEST to a logic „0" via µP pin 62. This switches on Q0823, which pulls line ON OFF CONTROL
high through diode D0821. A low to high transition on this line informs the radio, that the controlhead
requires service. The host radio then sends a data request message via BUS+ and the controlhead
µP replies with the data it wanted to send. This data can be information like which key has been
pressed or that the volume knob has been rotated.
The controlhead µP monitors all messages sent via BUS+, but ignores any data communication
between host radio and CPS or Universal Tuner.
2-6 THEORY OF OPERATION
3.5 Keypad Keys
The controlhead keypad is a 6-key kepad (Model B) or a 10- key keypad (model C). All keys are
configured as 2 analogue lines read by µP pins 13 and 15. The voltage on the analogue lines varies
between 0 volts and +5 volts depending on which key has been pressed. If no key is pressed, the
voltage at both lines will be 5 volts. The key configuration can be thought of as a matrix, where the
two lines represent one row and one column. Each line is connected to a resistive divider powered
by +5 volts. If a button is pressed, it will connect one specific resistor of each divider line to ground
level and thereby reduce the voltages on the analogue lines The voltages of the lines are A/D
converted inside the µP (ports PE 0 - 1) and specify the pressed button. To determine which key is
pressed, the voltage of both lines must be considered.
An additional pair of analogue lines and A/D µP ports (PE 3 – 2) is available to support a keypad
microphone, connected to the microphone connector J0811. Any microphone key press is
processed the same way as a key press on the controlhead.
3.6 Status LED and Back Light Circuit
All the indicator LED’s (red, yellow, green) are driven by current sources. To change the LED status
the host radio sends a data message via SBEP bus to the controlhead µP . The controlhead µP
determines the LED status from the received message and switches the LED’s on or off via port PB
7 – 0 and port PA4. The LED status is stored in the µP ’s memory. The LED current is determined by
the resistor at the emitter of the respective current source transistor.
The back light for the LCD and the keypad is controlled by the host radio the same way as the
indicator LED’s using µP port PA 5. This port is a Pulse Width Modulator (PWM) output. The output
signal charges capacitor C0843 through R0847. By changing the pulse width under software control,
the dc voltage of C0843 and thereby, the brightness of the back light can be changed in four steps.
The keypad back light current is drawn from the FLT A+ source and controlled by transistor Q0933.
The current flowing through the LED’s cause a proportional voltage drop across the parallel resistors
R0947, R0948. This voltage drop is amplified by the op-amp U0931-2. U0931-2 and Q0934 form a
differential amplifier. The voltage difference between the base of Q0934 and the output of U0931-2
determines the current from the base of the LED control transistor Q0933 and in turn the brightness
of the LED’s. The µP can control the LED’s by changing the dc level at the base of Q0934. If the
base of Q0934 is at ground level, Q0934 is switched off and no current flows through Q0933 and the
LED’s. If the base voltage of Q0934 rises a current flows through Q0934 and in turn through Q0933
causing the LED’s to turn on and a rising voltage drop across R0947, R0948. The rising voltage
causes the output of the op-amp to rise and to reduce the base to emitter voltage of Q0934. This
decreases the current of Q0933 until the loop has settled.
3.7 Liquid Crystal Display (LCD)
The LCD H0971 uses the display driver U0971. The display is a single layer super twist nematic
(STN) LCD display. It has 14 characters with a 5*8 dot matrix for displaying alpha - numerical
information and a line with 21 pre - defined icons above the dot matrix
The driver contains a data interface to the µP, an LCD segment driver, an LCD power circuit, an
oscillator, data RAM and control logic. At power up the driver’s control logic is reset by a logic „0" at
input SR2 (U0971-15). The driver’s internal oscillator is set to about 20 kHz and can be measured at
pin 22. The driver’s µP interface is configured to accept 8 bit parallel data input (U0971-D0-D7) from
the controlhead µP (U0831 port PC0-PC7).
To write data to the driver’s RAM the µP sets chip select (U0971-20) to logic „0" via U0831-11, RD
(U0971-18) to logic „1" via (U0831-10) and WR (U0971-17) to logic „0" via U0831-9. With input A0
(U0971-21) set to logic „0" via U0831-12 the µP writes control data to the driver. Control data
Controlhead Model for GM160, GM360 and GM660 2-7
includes the RAM start address for the following display data. With input A0 set to logic „1" the µP
then writes the display data to the display RAM. When data transfer is complete the µP terminates
the chip select, RD and WD activities.
The display driver’s power circuit provides the voltage supply for the display. This circuit consists of a
voltage multiplier, voltage regulator and a voltage follower. The external capacitors C0971 - C0973
configure the multiplier to double the supply voltage. In this configuration the multiplier output VOUT
(U0971-8) supplies a voltage of -5V (2* -5V below VDD). The multiplied voltage VOUT is sent to the
internal voltage regulator. To set the voltage level of the regulator output V5 (U0971-5) this voltage is
divided by the resistors R0973 and R0974 and fed back to the reference input VR (U0971-6). In
addition the regulator output voltage V5 can be controlled electronically by a control command sent
to the driver. With the used configuration the voltage V5 is about –2V. The voltage V5 is resistively
divided by the driver’s voltage follower to provide the voltages V1 - V4. These voltages are needed for
driving the liquid crystals. The level of V5 can be measured by one of the µP’s analogue to digital
converters (U0831-20) via resistive divider R0975, R0976. To stabilize the display brightness over a
large temperature range the µP measures the temperature via analogue to digital converter (U0831-
18) using temperature sensor U0834. Dependent on the measured temperature the µP adjusts the
driver output voltage V5, and in turn the display brightness, via parallel interface.
3.8 Microphone Connector Signals
Signals BUS+, PTT IRDEC, HOOK, MIC, HANDSET AUDIO, FLT A+, +5V and 2 A/D converter
inputs are available at the microphone connector J0811. Signal BUS+ (J0811-7) connects to the
SBEP bus for communication with the CPS or the Universal Tuner. Line MIC (J0811-5) feeds the
audio from the microphone to the radio’s controller via connector J0801-4. Line HANDSET AUDIO
(J0811-8) feeds the receiver audio from the controller (J0801-6) to a connected handset. FLT A+,
which is at supply voltage level, and +5V are used to supply any connected accessory like a
microphone or a handset.
The 2 A/D converter inputs (J0811-9/10) are used for a microphone with keypad. A pressed key will
change the dc voltage on both lines. The voltages depend on which key is pressed. The µP
determines from the voltage on these lines which key is pressed and sends the information to the
host radio.
Line PTT IRDEC (J0811-6) is used to key up the radio’s transmitter. While the PTT button on a
connected microphone is released, line PTT IRDEC is pulled to +5 volts level by R0843. Transistor
Q0843 is switched on and causes a low at µP port PA2. When the PTT button is pressed, signal PTT
IRDEC is pulled to ground level. This switches off Q0843 and the resulting high level at µP port PA2
informs the µP about the pressed PTT button. The µP will inform the host radio about any status
change on the PTT IRDEC line via SBEP bus.
When line PTT IRDEC is connected to FLT A+ level, transistor Q0821 is switched on through diode
VR0821 and thereby pulls the level on line ON OFF CONTROL to FLT A+ level. This switches on the
radio and puts the radio’s µP in bootstrap mode. Bootstrap mode is used to load the firmware into the
radio’s flash memory (See controller sub section for more details).
The HOOK input (J0811-3) is used to inform the µP when the microphone´s hang-up switch is
engaged. Dependent on the CPS programming the µP may take actions like turning the audio PA on
or off. While the hang up switch is open, line HOOK is pulled to +5 volts level by R0841. Transistor
Q0841 is switched on and causes a low at µP port PA1. When the HOOK switch is closed, signal
HOOK is pulled to ground level. This switches off R0841 and the resulting high level at µP port PA1
informs the µP about the closed hang up switch. The µP will inform the host radio about any status
change on the HOOK line via SBEP bus.
2-8 THEORY OF OPERATION
3.9 Speaker
The controlhead contains a speaker for the receiver audio. The receiver audio signal from the
differential audio output of the audio amplifier located on the radio’s controller is fed via connector
J0801-10, 11 to the speaker connector P0801 pin 1 and pin 2. The speaker is connected to the
speaker connector P0801. The controlhead speaker can be disconnected if an external speaker,
connected on the accessory connector, is used.
3.10 Electrostatic Transient Protection
Electrostatic transient protection is provided for the sensitive components in the controlhead by
diodes VR0811 VR00812 VR0816 - VR0817. The diodes limit any transient voltages to tolerable
levels. The associated capacitors provide Radio Frequency Interference (RFI) protection.
4.0 Controlhead Model for GM380, and GM1280
The controlhead contains the on/off/volume knob, the microphone connector, several buttons to
operate the radio, several indicator Light Emitting Diodes (LED) to inform the user about the radio
status, and a Liquid Crystal Display (LCD) with 21 pre - defined symbols and a 32*96 dot matrix for
graphical or alpha - numerical information e.g. channel number, select code, call address name. To
control the LED’s and the LCD, and to communicate with the host radio the controlhead uses the
Motorola 68HC11K4 microprocessor.
4.1 Power Supplies
The power supply to the controlhead is taken from the host radio’s FLT A+ voltage via connector
J0801 pin 3. The voltage FLT A+ is at battery level and is used for the LED’s, the back light, to power
up the radio via on / off / volume knob and to supply the voltage regulator circuitry. The regulator
circuitry provides the stabilized +5 volts which is used for the microprocessor circuitry, the display,
the display driver and the keypad buttons. The regulated +5V taken from the host radio via connector
J0801 pin 7 (line 5V SOURCE) is only used to switch on or off the voltage regulator in the control-
head.
4.2 Voltage Regulator Circuit
Voltage regulator U0861provides 5V for the controlhead. The supply voltage FLT A+ for the voltage
regulator is fed via parallel resistors R0861/2 and dual diode D0861 to pin 8 of U0861. The +5 volt
output is switched on and off by the host radios’s 5 volt source via line 5V SOURCE and control
transistor Q0866. When the host radio is switched off the voltage on line +5V SOURCE is at ground
level and switches off transistor Q0866. Pull up resistor R0863 pulls input SHUTDOWN (pin 3) of the
voltage regulator U0861 to FLT A+ level and switches off the output of U0861 (pin 1). When the host
radio is switched on the voltage on line 5V SOURCE of about +5 volts switches on transistor Q0866
which in turn pulls input SHUTDOWN (pin 3) to ground and switches on the output of U0861. Input
and output capacitors (C0861 / C0862 and C0864 / C0865) are used to reduce high frequency noise
and provide proper operation during battery transients. Diode D0861 prevents discharge of C0862
by negative spikes on the FLT A+ voltage. This regulator provides a reset output (pin 5) that goes to
0 volts if the regulator output goes out of regulation. This is used to reset the microprocessor
(U0871) and the display driver (J0821-5) to prevent improper operation.
The voltage USW 5V derived from voltage FLT A+ is stabilized using resistor R0855 and diode
VR0855 This voltage is used to buffer the microprocessor’s internal RAM. C0856 allows the battery
voltage to be disconnected for a couple of seconds without losing RAM parameters. Diode D0855
Controlhead Model for GM380, and GM1280 2-9
prevents radio circuitry from discharging this capacitor. The +5V at the second anode of D0855
speeds up charging of C0856, when the host radio is turned on by a high level at the ignition input
while the supply voltage is applied to the radio. This prevents the microprocessor from accidently
entering bootstrap mode.
4.3 Power On / Off
The On/Off/Volume knob when pressed switches the radio’s and the controlhead‘s voltage regulators
on by connecting line ON OFF CONTROL to line UNSW 5V via D0852. Additionally, 5 volts at the
base of digital transistor Q0853 informs the controlhead’s microprocessor about the pressed knob.
The microprocessor asserts pin 8 and line CH REQUEST low to hold line ON OFF CONTROL at 5
volts via Q0852 and D0852. The high line ON OFF CONTROL also informs the host radio, that the
controlhead’s microprocessor wants to send data via SBEP bus. When the radio returns a data
request message, the microprocessor will inform the radio about the pressed knob. If the radio was
switched off, the radio’s µP will switch it on and vice versa. If the On/Off/Volume knob is pressed
while the radio is on, the software detects a low state on line ON OFF SENSE, the radio is alerted via
line ON OFF CONTROL and sends a data request message. The controlhead µP will inform the
radio about the pressed knob and the radio’s µP will switch the radio off. If the radio is switched on
either manually or automatically it’s +5V source switches on the controlhead’s voltage regulator
U0861 via line 5 SOURCE and transistor Q0866 and the controlhead’s microprocessor starts
execution.
4.4 Microprocessor Circuit
The controlheadcontrolhead uses the Motorola 68HC11K4 microprocessor (uP) (U0871) to control
the LED’s and the LCD and to communicate with the host radio. RAM and ROM are contained within
the microprocessor itself.
The microprocessor generates it’s clock using the oscillator inside the microprocessor along with a 8
MHz ceramic resonator (U0873) and R0873.
The microprocessor’s RAM is always powered to maintain parameters such as the last operating
mode. This is achieved by maintaining 5V at µP pin 76. Under normal conditions, when the radio is
off, USW 5V is formed by FLT A+ running to D0855. C0856 allows the battery voltage to be
disconnected for a couple of seconds without losing RAM parameters. Diode D0855 prevents radio
circuitry from discharging this capacitor.
There are 8 analogue to digital converter ports (A/D) on the µP. They are labeled within the device
block as PE0-PE7. These lines sense the voltage level ranging from 0 to 5V of the input line and
convert that level to a number ranging from 0 to 255 which can be read by the software to take
appropriate action.
Pin VRH is the high reference voltage for the A/D ports on the µP. If this voltage is lower than +5V the
A/D readings will be incorrect. Likewise pin VRL is the low reference for the A/D ports. This line is
normally tied to ground. If this line is not connected to ground, the A/D readings will be incorrect.
The microprocessor can determine the used keypad type by reading the level at port PE5.
Connections S0931 – S0935 are provided by the individual keypads.
The MODB / MODA input of the µP must be at a logic „1" for it to start executing correctly. The XIRQ
and the IRQ pins should also be at a logic „1".
4.5 SBEP Serial Interface
The host radio (master) communicates to the controlhead µP (slave) through its SBEP bus. This bus
uses only line BUS+ for data transfer. The line is bi-directional, meaning that either the radio or the
2-10 THEORY OF OPERATION
controlhead µP can drive the line. The microprocessor sends serial data via pin 79 and D0872 and it
reads serial data via pin 78. Whenever the microprocessor detects activity on the BUS+ line, it starts
communication.
When the host radio needs to communicate to the controlhead µP, it sends data via line BUS+. Any
transition on this line generates an interrupt and the µP starts communication. The host radio may
send data like display information, LED and back light status or it may request the
controlheadcontrolhead ID or the keypad ID.
When the controlhead µP wants to communicate to the host radio, the µP brings request line CH
REQUEST to a logic „0" via µP pin 8. This switches on Q0852, which pulls line ON OFF CONTROL
high through diode D0852. A low to high transition on this line informs the radio, that the controlhead
requires service. The host radio then sends a data request message via BUS+ and the controlhead
µP replies with the data it wanted to send. This data can be information like which key has been
pressed or that the volume knob has been rotated.
The controlhead µP monitors all messages sent via BUS+, but ignores any data communication
between host radio and CPS or Universal Tuner.
4.6 Keypad Keys
The controlhead keypad is a 25 - key keypad. All keys are configured as 2 analogue lines read by µP
pins 49 and 48. The voltage on the analogue lines varies between 0 volts and +5 volts depending on
which key has been pressed. If no key is pressed, the voltage at both lines will be 5 volts. The key
configuration can be thought of as a matrix, where the two lines represent one row and one column.
Each line is connected to a resistive divider powered by +5 volts. If a button is pressed, it will connect
one specific resistor of each divider line to ground level and thereby reduce the voltages on the
analogue lines The voltages of the lines are A/D converted inside the µP (ports PE 0 - 1) and specify
the pressed button. To determine which key is pressed, the voltage of both lines must be considered.
An additional pair of analogue lines and A/D µP ports (PE 3 – 2) is available to support a keypad
microphone, connected to the microphone connector J0811. Any microphone key press is
processed the same way as a key press on the controlhead.
4.7 Status LED and Back Light Circuit
All the indicator LED’s (red, yellow, green) are driven by current sources. To change the LED status
the host radio sends a data message via SBEP bus to the controlhead µP. The controlhead µP
determines the LED status from the received message and switches the LED’s on or off via port PA
6 - 4. The LED status is stored in the µP’s memory. The LED current is determined by the resistor at
the emitter of the respective current source transistor.
The back light for keypad is controlled by the host radio the same way as the indicator LED’s using
µP port PH 3. This port is a Pulse Width Modulator (PWM) output. The output signal charges
capacitor C0943 through R0945. By changing the pulse width under software control, the dc voltage
of C0943 and thereby, the brightness of the back light can be changed in 16 steps. The keypad back
light current is drawn from the FLT A+ source and controlled by transistor Q0941. The current flowing
through the LED’s cause a proportional voltage drop across the parallel resistors R0955, R0957.
This voltage drop is amplified by the op-amp U0941-1. U0941-1 and Q0943 form a differential
amplifier. The voltage difference between the base of Q0943 and the output of U0941-1 determines
the current from the base of the LED control transistor Q0941 and in turn the brightness of the
LED’s. The µP can control the LED’s by changing the dc level at the base of Q0943. If the base of
Q0943 is at ground level, Q0943 is switched off and no current flows through Q0941 and the LED’s.
If the base voltage of Q0943 rises a current flows through Q0943 and in turn through Q0941 causing
the LED’s to turn on and a rising voltage drop across R0955, R0957. The rising voltage causes the
Controlhead Model for GM380, and GM1280 2-11
output of the op-amp to rise and to reduce the base to emitter voltage of Q0943. This decreases the
current of Q0941 until the loop has settled.
The back light for the LCD module uses a similar circuitry. The only differences are that µP port PH2
controls the back light brightness and that the LED’s are located on the LCD module which is
connected via J0821. Control line BL A GREEN connects to the anodes and control line BL K
GREEN connects to the cathodes of the LED’s.
4.8 Liquid Crystal Display (LCD)
The LCD module consists of the display and the display driver and is connected via connector
J0821. The display is a single layer super twist nematic (STN) LCD display. It has a dot matrix of 32 *
96 dots for displaying graphics and alpha - numerical information and a line with 21 pre - defined
icons above the dot matrix
The driver contains a data interface to the µP, an LCD segment driver, an LCD power circuit, an
oscillator, data RAM and control logic. At power up the driver’s control logic is reset by a logic „0" via
pin 5 of J0821. The driver’s µP interface is configured to accept 8 bit parallel data input (J0821-D0-
D7) from the controlhead µP (U0871 port PC0-PC7).
To write data to the driver’s RAM the µP sets chip select (J0821-6) to logic „0" via U0871-26, RD
(J0821-10) to logic „1" via (U0871-40) and WR (U0821-9) to logic „0" via U0871-33. With input A0
(J0821-8) set to logic „0" via U0871-34 the µP writes control data to the driver. Control data includes
the RAM start address for the following display data. With input A0 set to logic „1" the µP then writes
the display data to the display RAM. When data transfer is complete the µP terminates the chip
select and the clock activities.
The display driver’s power circuit provides the voltage supply for the display. This circuit consists of a
voltage multiplier, voltage regulator and a voltage follower. The regulator output voltage for the
display can be controlled electronically by a control command sent to the driver. The voltage level
can be measured by one of the µP’s analogue to digital converters (U0871-42) via J0821-21. To
stabilize the display brightness over a large temperature range the µP measures the temperature via
analogue to digital converter (U0871-43) using a temperature sensor on the module (J0821-4).
Dependent on the measured temperature the µP adjusts the driver output voltage, and in turn the
display brightness, via parallel interface.
4.9 Microphone Connector Signals
Signals BUS+, PTT IRDEC, HOOK, MIC, HANDSET AUDIO, FLT A+, +5V and 2 A/D converter
inputs are available at the microphone connector J0811. Signal BUS+ (J0811-7) connects to the
SBEP bus for communication with the CPS or the Universal Tuner. Line MIC (J0811-5) feeds the
audio from the microphone to the radio’s controller via connector J0801-4. Line HANDSET AUDIO
(J0811-8) feeds the receiver audio from the controller (J0801-6) to a connected handset. FLT A+,
which is at supply voltage level, and +5V are used to supply any connected accessory like a
microphone or a handset.
The 2 A/D converter inputs (J0811-9/10) are used for a microphone with keypad. A pressed key will
change the dc voltage on both lines. The voltages depend on which key is pressed. The µP
determines from the voltage on these lines which key is pressed and sends the information to the
host radio.
Line PTT IRDEC (J0811-6) is used to key up the radio’s transmitter. While the PTT button on a
connected microphone is released, line PTT IRDEC is pulled to +5 volts level by R0880. Transistor
Q0871 is switched on and causes a low at µP port PA2. When the PTT button is pressed, signal PTT
IRDEC is pulled to ground level. This switches off Q0871 and the resulting high level at µP port PA2
2-12 THEORY OF OPERATION
informs the µP about the pressed PTT button. The µP will inform the host radio about any status
change on the PTT IRDEC line via SBEP bus.
When line PTT IRDEC is connected to FLT A+ level, transistor Q0851 is switched on through diode
VR0851 and thereby pulls the level on line ON OFF CONTROL to FLT A+ level. This switches on the
radio and puts the radio’s µP in bootstrap mode. Bootstrap mode is used to load the firmware into
the radio’s flash memory (See controller sub section for more details).
The HOOK input (J0811-3) is used to inform the µP when the microphone´s hang-up switch is
engaged. Dependent on the CPS programming the µP may take actions like turning the audio PA on
or off. While the hang up switch is open, line HOOK is pulled to +5 volts level by R0883. Transistor
Q0872 is switched on and causes a low at µP port PA1. When the HOOK switch is closed, signal
HOOK is pulled to ground level. This switches off R0883 and the resulting high level at µP port PA1
informs the µP about the closed hang up switch. The µP will inform the host radio about any status
change on the HOOK line via SBEP bus.
4.10 Speaker (Remote Mount Configuration only)
The remote mount controlhead contains a speaker for the receiver audio. The receiver audio signal
from the differential audio output of the audio amplifier located on the radio’s controller is fed via
connector J0801-10,11 to the speaker connector P0801 pin 1 and pin 2. The speaker is connected
to the speaker connector P0801. The controlhead speaker can be disconnected if only an external
speaker, connected on the accessory connector, should be used. If the controlhead is mounted
directly on the radio, an external speaker is required.
4.11 Electrostatic Transient Protection
Electrostatic transient protection is provided for the sensitive components in the controlhead by
diodes VR0811 - VR0814. The diodes limit any transient voltages to tolerable levels. The associated
capacitors provide Radio Frequency Interference (RFI) protection.
Chapter 3
TROUBLESHOOTING CHARTS
1.0 Controlhead GM140/340/640 Troubleshooting Chart
1.1 On/Off
Radio can not be switched on via ON/OFF Volume
NO
YES
YES
NO
R0823 Pin TAB
= 5V ?
R0823 Pin TAB1
when pressed
= 5V ?
Check / Replace
Volume Pot R0823
Check / Replace
R0822 / VR0822 /
D0822
NO
YES
J0801 Pin 2
> 10V ?
Check / Replace
Q0821
Check / Replace
Q0822 / R0821
YES
NO
J0801 Pin 2
=5V ?
Check / Replace
D0821 / R0852
Press and hold
On/Off Volume Knob
3-2 TROUBLESHOOTING CHARTS
1.2 Microprocessor
Power Up Alert Tone is OK but volume knob
does not operate and no indicator is on
NO
YES
YES
NO
YES
NO
YES
NO
YES
EXTAL
U0831 Pin 31
= 8.00 MHz ?
RESET
TP0833
= HIGH ?
Check / Replace
C0833 / R0832 / U0831
Check radio controller
Data Signal
on J0801 Pin 5
BUS+ ?
Data Signal
on TP0836
SCI_RX ?
NO
Data Signal
on TP0837
SCI_TX ?
Check / Replace
R0831 / U0833 / U0831
Check / Replace
R0837 / R0836
Check / Replace
U0831
Check / Replace
D0831 / R0838
Measure with scope
while rotating Volume
Controlhead GM160/360/660 Troubleshooting Flow Chart 3-3
2.0 Controlhead GM160/360/660 Troubleshooting Flow Chart
2.1 On/Off
Radio can not be switched on via ON/OFF Volume Knob
NO
YES
YES
NO
R0823 Pin TAB
= 5V ?
R0823 Pin TAB1
when pressed
= 5V ?
Check / Replace
Volume Pot R0823
Check / Replace
R0822 / VR0822 /
D0822 / C0822
NO
YES
J0801 Pin 2
> 10V ?
Check / Replace
Q0821
Check / Replace
Q0822 / R0821
YES
NO
J0801 Pin 2
=5V ?
Check / Replace
D0821 / R0852
Press and hold
On/Off Volume Knob
3-4 TROUBLESHOOTING CHARTS
2.2 Microprocessor
Power Up Alert Tone is OK but volume knob does
not operate and no indicator is on
NO
YES
YES
NO
YES
NO
YES
NO
YES
EXTAL
U0831 Pin 31
= 8.00 MHz ?
RESET
TP0833
= HIGH ?
Check / Replace
C0833 / R0832 /
Check radio controller
Data Signal
on J0801 Pin 5
BUS+ ?
Data Signal
on TP0836
SCI_RX ?
NO
Data Signal
on TP0837
SCI_TX ?
Check / Replace
R0831 / U0833 / U0831
Check / Replace
R0837 / R0836
Check / Replace
U0831
Check / Replace
D0831 / R0838
Measure with scope while
rotating Volume Pot
Controlhead GM160/360/660 Troubleshooting Flow Chart 3-5
2.3 Display
Power Up Alert Tone is OK, volume knob does operate,
indicator/backlight is on but nothing on display
YES
NO
YES
NO
V5 (against 5V)
TP0973 between
-6V and -7V ?
Activity on
Address & Data lines
A0 / D0..D7 / CS1
of U0971?
Check for shortage
U0831 / U0971
Check LCD Assembly
Check / Replace
C0971 / C0973 / R0972
R0973 / R0974 / U0971
3-6 TROUBLESHOOTING CHARTS
2.4 Backlight
Power Up Alert Tone is OK, volume knob does operate,
indicator/display is on but no backlight
NO
YES
YES
NO
U0831 Pin 58
is toggling ?
Base of
Q0934
> 0.7V ?
Check / Replace
R0847 / C0843 / R0943
Check for shortage
U0831
YES
NO
Collector of
Q0934
>5V and < 11V ?
Check / Replace
Q0934 U0931 /R0941 /
R0942 / R0944 / R0945
Check / Replace
Q0933 / R0947 / R0948
Controlhead GM380/1280 Troubleshooting Flow Chart 3-7
3.0 Controlhead GM380/1280 Troubleshooting Flow Chart
3.1 On/Off
R0854
Pin TAB1
when pressed
=5V ?
J0801 PIN2
> 10V ?
J0801 PIN2
=5V?
Check / Replace
Q0853 / R0853
YES
NO
YES
NO
YES
NO Check / Replace
D0852 / R0852
Check / Replace
Volume Pot R0854
Check / Replace
Q0851
Radio can not be switched on via ON/OFF Volume Knob
YES
R0854
Pin TAB
= 5V?
NO Check / Replace
R0855 / VR0855 / D0855
C0856
Press and hold
On / Off
Volume Knob
3-8 TROUBLESHOOTING CHARTS
3.2 Microprocessor
Power Up Alert Tone is audible on external speaker but volume
knob does not operate and no indicators are on
TP0876
=5V ?
NO
YES
U0871
Pin 73 EXTAL
= 8 MHz
TP0866
= 0V
NO
Check / Replace
R0873 / U0873 /
U0871
Check / Replace
R0866 / C0866 /
Q0866 / R0863
Check / Replace
R0861 / R0862 / D0861
C0861 / C0862 / U0861
C0863 / C0864 / C0865
1
NO
YES YES
Controlhead GM380/1280 Troubleshooting Flow Chart 3-9
3.3 Microprocessor
1
Data Signal
on J0801
Pin 5 BUS+
?
Data Signal
on TP0877
SCI_RX
?
Data Signal
on TP0878
SCI_TX
?
Check / Replace
D0872 / R0887
YES
YES
YES
NO
NO
NO Check / Replace
U0871
Check
Radio Controller
Check / Replace
R0888 / R0889
Measure with scope
while rotating
Volume Pot
3-10 TROUBLESHOOTING CHARTS
3.4 Display
TP0973
Voltage Sense
between
2V and 2.4V
?
Activity on
Address & Data lines
A0 / D0...D7 / CS1
of U0971
?
NO
YES
YES
NO
Check / Replace
Flex connection
Resistors on Address & Data
lines and LCD Module
Check / Replace
LCD Module
Check for shortage
U0871
Power Up Alert Tone is audible, volume knob does operate,
indicator/backlight is on but nothing is seen on the display.
Controlhead GM380/1280 Troubleshooting Flow Chart 3-11
3.5 Keypad Backlight
U0871 Pin 25
is toggling ?
Base of Q0943
> 0.7V ?
Collector of
Q0943
>5V & < 11V
?
Check / Replace
Q0941 / R0955 / R0957
YES
YES
YES
NO
NO
NO
Check / Replace
Q0943 / U0941 / R0941
R0943 / R0949 / R0951
Check for shortage
U0871
Check / Replace
R0945 / C0943 / R0947
Power Up Alert Tone is audible, volume knob does operate,
display is on but no keypad backlight.
3-12 TROUBLESHOOTING CHARTS
3.6 Display Backlight
U0871 Pin 24
is toggling ?
Base of Q0963
> 0.7V ?
Collector of
Q0963
>5V & < 11V
?
Check / Replace
Q0961 / R0975 / R0977
YES
YES
YES
NO
NO
NO
Check / Replace
Q0963 / U0941 / R0961
R0963 / R0969 / R0971
Check for shortage
U0871
Check / Replace
R0965 / C0963 / R0967
Power Up Alert Tone is audible, volume knob does operate,
display is on but no display backlight.
Chapter 4
CONTROLHEAD PCB / SCHEMATICS / PARTS LISTS
1.0 Allocation of Schematics and Circuit Boards
.
Table 4-1 Controlhead Diagrams and Parts Lists
PCB :
Controlhead GM140/340/640
8486146B07 Main Board Top Side
8486146B07 Main Board Bottom Side
Page 4-3
Page 4-3
SCHEMATICS
Sheet 1 of 2
Sheet 2 of 2
Page 4-4
Page 4-5
Parts List
8486146B07 Page 4-6
Table 4-2 Controlhead Diagrams and Parts Lists
PCB :
Controlhead GM160/360/660
8486155B06 Main Board Top Side
8486155B06 Main Board Bottom Side
Page 4-7
Page 4-7
SCHEMATICS
Sheet 1 of 4
Sheet 2 of 4
Sheet 3 of 4
Sheet 4 of 4
Page 4-8
Page 4-9
Page 4-10
Page 4-11
Parts List
8486155B06 Page 4-12
Table 4-3 Controlhead Diagrams and Parts Lists
PCB :
Controlhead GM380/1280
8486178B03/04 Main Board Top Side
8486178B03/04 Main Board Bottom
Side
Page 4-13
Page 4-13
SCHEMATICS
Sheet 1 of 4
Sheet 2 of 4
Sheet 3 of 4
Sheet 4 of 4
Page 4-14
Page 4-15
Page 4-16
Page 4-17
Parts List
8486178B03/04 Page 4-18
4-2 controlhead PCB / Schematics / Parts lists
Professional Radio
GM Series
Controller
Service Information
Issue: August 2002
ii
Computer Software Copyrights
The Motorola products described in this manual may include copyrighted Motorola computer programs stored
in semiconductor memories or other media. Laws in the United States and other countries preserve for
Motorola certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or
reproduce in any form, the copyrighted computer program. Accordingly, any copyrighted Motorola computer
programs contained in the Motorola products described in this manual may not be copied or reproduced in
any manner without the express written permission of Motorola. Furthermore, the purchase of Motorola
products shall not be deemed to grant, either directly or by implication, estoppel or otherwise, any license
under the copyrights, patents or patent applications of Motorola, except for the normal non-exclusive royalty-
free license to use that arises by operation of law in the sale of a product.
iii
Table of Contents
Chapter 1 THEORY OF OPERATION
1.0 Controller Circuits ................................................................................................1-1
1.1 Overview.........................................................................................................1-1
1.2 General...........................................................................................................1-1
1.3 Radio Power Distribution ................................................................................1-2
1.4 Electronic ON/OFF .........................................................................................1-3
1.5 Emergency .....................................................................................................1-4
1.6 Mechanical ON/OFF.......................................................................................1-4
1.7 Ignition............................................................................................................1-5
1.8 Microprocessor Clock Synthesizer .................................................................1-5
1.9 Serial Peripheral Interface (SPI).....................................................................1-5
1.10 SBEP Serial Interface.....................................................................................1-6
1.11 General Purpose Input/Output.......................................................................1-6
1.12 Normal Microprocessor Operation..................................................................1-7
1.13 FLASH Electronically Erasable Programmable Memory ................................1-8
1.14 Electrically Erasable Programmable Memory (EEPROM)..............................1-9
1.15 Static Random Access Memory (SRAM) .......................................................1-9
1.16 Universal Asynchronous Receiver Transmitter (UART) .................................1-9
2.0 Controller Board Audio and Signalling Circuits....................................................1-9
2.1 General - Audio Signalling Filter IC with Compander.....................................1-9
2.2 Transmit Audio Circuits ................................................................................1-10
2.3 Transmit Signalling Circuits..........................................................................1-12
2.4 Receive Audio Circuits .................................................................................1-14
2.5 Receive Signalling Circuits...........................................................................1-17
2.6 Voice Storage...............................................................................................1-18
iv
Chapter 2 TROUBLESHOOTING CHARTS
1.0 Controller ............................................................................................................2-1
Chapter 3 CONTROLLER SCHEMATICS
1.0 Allocation of Schematics and Circuit Boards.......................................................3-1
2.0 T2 Controller .......................................................................................................3-3
3.0 T5 Controller .....................................................................................................3-10
4.0 T6/7 Controller ..................................................................................................3-19
5.0 T9 Controller .....................................................................................................3-29
6.0 T11 Controller ...................................................................................................3-35
7.0 T12 Controller ...................................................................................................3-42
Chapter 1
THEORY OF OPERATION
1.0 Controller Circuits
1.1 Overview
This section provides a detailed theory of operation for the radio and its components. The main radio
is a single board design, consisting of the transmitter, receiver, and controller circuits. The main
board is designed to accept one additional option board. This may provide functions such as secure
voice/data, voice storage or signalling decoder.
A controlhead is either mounted directly or connected by an extension cable. The controlhead
contains, LED indicators, a microphone connector, buttons and dependant of the radio type, a
display and a speaker. These provide the user with interface control over the various features of the
radio.
If no controlhead is mounted directly on the front of the radio, an expansion board containing circuitry
for special applications can be mounted on the front of the radio. An additional controlhead can be
connected by an extension cable.
In addition to the power cable and antenna cable, an accessory cable can be attached to a connector
on the rear of the radio. The accessory cable provides the necessary connections for items such as
external speaker, emergency switch, foot operated PTT, and ignition sensing, etc
1.2 General
The radio controller consists of 3 main subsections:
■
■Digital Control
■
■Audio Processing
■
■Voltage Regulation.
The digital control section of the radio is based upon an open architecture controller configuration.It
consists of a microprocessor, support memory, support logic, signal MUX ICs, the On/Off circuit, and
general purpose Input/Output circuitry.
The controller uses the Motorola 68HC11FL0 microprocessor (U0101). In addition to the
microprocessor, the controller has 3 external memory devices. The 3 memory devices consist of a
32Kbyte SRAM (U0122), a 512Kbyte FLASH EEPROM (U0121), and a 16Kbyte EEPROM (U0111).
Note: From this point on the 68HC11FL0 microprocessor will be referred to as µP. References to a
controlhead will be to the controlheads with display.
1-2 THEORY OF OPERATION
Figure 1-1 Controller Block Diagram
1.3 Radio Power Distribution
The DC power distribution throughout the radio board is shown in Figure 2-1. Voltage regulation for
the controller is provided by 4 separate devices; U0651 (MC78M05) +5V, U0641 (LM2941) +9.3V,
U0611 (LM2941) SWB+ limited to 16.5V and VSTBY 5V (a combination of R0621 and VR0621). An
additional 5V regulator is located on the RF section.
The DC voltage applied to connector J0601 supplies power directly to the electronic on/off control,
RF power amplifier, 16.5V limiter, 9.3V regulator, Audio PA and 5.6V stabilization circuit. The 9.3V
regulator (U0641) supplies power to the 5V regulator (U0651) and the 6V voltage divider Q0681.
Regulator U0641 is used to generate the 9.3 volts required by some audio circuits, the RF circuitry
and power control circuitry. Input and output capacitors (C0641 and C0644 / C0645) are used to
reduce high frequency noise. R0642 / R0643 set the output voltage of the regulator. If the voltage at
pin 1 is greater than 1.3 volts the regulator output decreases and if the voltage is less than 1.3 volts
the regulator output increases. This regulator output is electronically enabled by a 0 volt signal on pin
2. Q0661, Q0641 and R0641 are used to disable the regulator when the radio is turned off.
Voltage regulation providing 5V for the digital circuitry is done by U0651. Operating voltage is from
the regulated 9.3V supply. Input and output capacitors (C0651 / C0652 and C0654 / C0655) are
used to reduce high frequency noise and provide proper operation during battery transients. Voltage
sense device U0652 or alternatively U0653 provides a reset output that goes to 0 volts if the
regulator output goes below 4.5 volts. This is used to reset the controller to prevent improper
operation. Diode D0651 prevents discharge of C0652 by negative spikes on the 9V3 voltage.
Transistor Q0681 and resistors R0681 / R0682 divide the regulated 9.3V down to about 6 volts. This
voltage supplies the 5V regulator, located on the RF section. By reducing the supply voltage of the
regulator, the power dissipation is divided between the RF section and the controller section.
External
Microphone
Internal
Microphone
External
Speaker
Internal
Speaker
SCI to
Controlhead
Audio
PA
Audio/Signalling
Architecture
To Synthesizer
Mod
Out
16.8 MHz
Reference Clock
from Synthesizer
Recovered Audio
To RF Section SPI
Digital
Architecture
µP Clock
5V
Regulator
(5VD)
RAM
EEPROM
FLASH
HC11FL0
ASFIC_CMP
Accessory &
5V
from Synthesizer
Section (5V_RF)
Connector
Controller Circuits 1-3
The voltage VSTBY, which is derived directly from the supply voltage by components R0621 and
VR0621, is used to buffer the internal RAM. C0622 allows the battery voltage to be disconnected for
a couple of seconds without losing RAM parameters. Dual diode D0621 prevents radio circuitry from
discharging this capacitor. When the supply voltage is applied to the radio, C0622 is charged via
R0621 and D0621. To avoid that the µP enters the wrong mode when the radio is switched on while
the voltage across C0622 is still too low, the regulated 5V charges C0622 via diode D0621.
Figure 2-1 DC Power Distribution Block Diagram
The voltage INT SW B+ from switching transistor Q0661 provides power to the circuit controlling the
audio PA output. The voltage INT SW B+ voltage is monitored by the µP through voltage divider
R0671 / R0672 and line BATTERY VOLTAGE. Diode VR0671 limits the divided voltage to 5.6V to
protect the µP.
Regulator U0611 is used to generate the voltage for the switched supply voltage output (SWB+) at
the accessory connector J0501 pin 13. U0611 is configured to operate as a switch with voltage and
current limit. R0611 / R0612 set the maximum output voltage to 16.5 volts. This limitation is only
active at high supply voltage levels. The regulator output is electronically enabled by a 0 volt signal
on pin 2. Q0661, Q0641 and R0641 are used to disable the regulator when the radio is turned off.
Input and output capacitors (C0603 and C0611 / C0612) are used to reduce high frequency noise.
Diode VR0601 acts as protection against transients and wrong polarity of the supply voltage.
Fuse F0401 prevents damage of the board in case the FLT A+ line is shorted at the controlhead
connector.
1.4 Electronic ON/OFF
The radio has circuitry which allows radio software and/or external triggers to turn the radio on or off
without direct user action. For example, automatic turn on when ignition is sensed and off when
ignition is off.
Q0661 is used to provide INT SW B+ to the various radio circuits and to enable the voltage
regulators via transistor Q0641. Q0661 contains an pnp and an npn transistor and acts as an
electronic on/off switch. The switch is on when the collector of the npn transistor within Q0661 is low.
When the radio is off the collector is at supply voltage level. This effectively prevents current flow
VCOBIC
FRACTN
VSTBY
5V_RF
9V3
FLT_A+
5VD
SWB+
Option Board
40 Pin Connector
PA, Driver
Antenna Switch
Controlhead
12 Pin Connector
Accessories
20 Pin Connector
J0601
13.2V
PASUPVLTG
FLT_A+
16.5V
Limiter
ON / OFF
Control
ASFIC_CMP
5.6V
Ignition
Emergency
ON/OFF
9.3V
Regulator
Audio PA
6V
Regulator 5V
Regulator
5VD
5V
Regulator 5V/
VDDA
MCU
µP, RAM,
FLASH & EEPROM
PCIC,
TX Amp
Temp Sense
RX RF Amp
IF Amp
F0401
1-4 THEORY OF OPERATION
from emitter to collector of the pnp transistor. When the radio is turned on the voltage at the base of
the npn transistor is pulled high and the pnp transistor switches on (saturation). With voltage INT
SWB+ now at supply voltage level, transistor Q0641 pulls pin 2 of the voltage regulators U0611 and
U 0641 to ground level and thereby enables their outputs.
The electronic on/off circuitry can be enabled by the microprocessor (through ASFIC CMP port
GCB2, line DC POWER ON), the emergency switch (line EMERGENCY CONTROL), the
mechanical On/Off/Volume knob on the controlhead (line ON OFF CONTROL), or the ignition sense
circuitry (line IGNITION CONTROL). If any of the 4 paths cause a low at the collector of the npn
transistor within Q0661, the electronic "ON" is engaged.
1.5 Emergency
The emergency switch (J0501 pin 9), when engaged, grounds the base of Q0662 via line
EMERGENCY CONTROL. This switches Q0662 off and resistor R0662 pulls the collector of Q0662
and the base of Q0663 to levels above 2 volts. Transistor Q0663 switches on and pulls the collector
of the npn transistor within Q0661 to ground level and thereby enables the voltage regulators via
Q0641. When the emergency switch is released R0541 pulls the base of Q0662 up to 0.6 volts. This
causes the collector of transistor Q0662 to go low (0.2V), thereby switching Q0663 off.
While the radio is switched on, the microprocessor monitors the voltage at the emergency input on
the accessory connector via pin 60 and line GP5 IN ACC9. Three different conditions are
distinguished, no emergency, emergency, and open connection to the emergency switch. If no
emergency switch is connected or the connection to the emergency switch is broken, the resistive
divider R0541 / R0512 will set the voltage to about 4.7 volts. If an emergency switch is connected, a
resistor to ground within the emergency switch will reduce the voltage on line GP5 IN ACC9 to inform
the microprocessor that the emergency switch is operational. An engaged emergency switch pulls
line GP5 IN ACC9 to ground level. Diode D0179 limits the voltage to protect the microprocessor
input.
While EMERGENCY CONTROL is low, INT SW B+ is on, the microprocessor starts execution, reads
that the emergency input is active through the voltage level of line GP5 IN ACC9, and sets the DC
POWER ON output of the ASFIC CMP pin 13 to a logic high. This high will keep Q0661 and Q0641
switched on. This operation allows a momentary press of the emergency switch to power up the
radio. When the microprocessor has finished processing the emergency press, it sets the DC
POWER ON line to a logic 0. This turns off Q0661 and the radio turns off. Notice that the
microprocessor is alerted to the emergency condition via line GP5 IN ACC9. If the radio was already
on when emergency was triggered then DC POWER ON would already be high.
1.6 Mechanical ON/OFF
This refers to the typical on/off/volume knob, located on the controlhead, and which turns the radio
on and off.
If the radio is turned off and the on/off/volume knob is pressed, line ON OFF CONTROL (J0401 pin
11) goes high and switches the radio’s voltage regulators on as long as the button is pressed. The
microprocessor is alerted through line ON OFF SENSE (U0101 pin 6) which is pulled to low by
Q0110 while the on / off / volume knob is pressed. In addition, an interrupt is generated at µP pin 96.
The µP asserts line DC POWER ON via ASFIC CMP, pin 13 high which keeps Q0661 and Q0641,
and in turn the radio, switched on. When the on/off/volume knob is released again the controlhead
informs the µP via SBEP bus about the knob release. (See SBEP Serial Interface subsection for
more details). This informs the µP to keep the radio switched on and continue with normal operation.
If the on/off/volume knob is pressed while the radio is on, the controlhead informs the µP via SBEP
bus about the knob status. (See SBEP Serial Interface subsection for more details). After a short
delay time the microprocessor switches the radio off by setting DC POWER ON to low via ASFIC
CMP pin 13.
Controller Circuits 1-5
1.7 Ignition
Ignition sense is used to prevent the radio from draining the vehicle’s battery because the engine is
not running.
When the IGNITION input (J0501 pin 10) goes above 5 volts Q0661 is turned on via line IGNITION
CONTROL. Q0661 turns on INT SW B+ and the voltage regulators by turning on Q0641 and the
microprocessor starts execution. The microprocessor is alerted through line GP6 IN ACC10. The
voltage at the IGNITION input turns Q0181 on, which pulls microprocessor pin 74 to low. If the
software detects a low state it asserts DC POWER ON via ASFIC pin 13 high which keeps Q0661
and Q0641, and in turn the radio switched on.
When the IGNITION input goes below 3 volts, Q0181 switches off and R0181 pulls microprocessor
pin 74 to high. This alerts the software to switch off the radio by setting DC POWER ON to low. The
next time the IGNITION input goes above 5 volts the above process will be repeated.
1.8 Microprocessor Clock Synthesizer
The clock source for the microprocessor system is generated by the ASFIC CMP (U0221). Upon
power-up the synthesizer IC (FRAC-N) generates a 16.8 MHz waveform that is routed from the RF
section to the ASFIC CMP pin 34. For the main board controller the ASFIC CMP uses 16.8 MHz as a
reference input clock signal for its internal synthesizer. The ASFIC CMP, in addition to audio circuitry,
has a programmable synthesizer which can generate a synthesized signal ranging from 1200Hz to
32.769MHz in 1200Hz steps.
When power is first applied, the ASFIC CMP will generate its default 3.6864MHz CMOS square
wave UP CLK (on U0221 pin 28) and this is routed to the microprocessor (U0101 pin 90). After the
microprocessor starts operation, it reprograms the ASFIC CMP clock synthesizer to a higher UP
CLK frequency (usually 7.3728 or 14.7456 MHz) and continues operation.
The ASFIC CMP may be reprogrammed to change the clock synthesizer frequencies at various
times depending on the software features that are executing. In addition, the clock frequency of the
synthesizer is changed in small amounts if there is a possibility of harmonics of this clock source
interfering with the desired radio receive frequency.
The ASFIC CMP synthesizer loop uses C0245, C0246 and R0241 to set the switching time and jitter
of the clock output. If the synthesizer cannot generate the required clock frequency it will switch back
to its default 3.6864MHz output.
Because the ASFIC CMP synthesizer and the µP system will not operate without the 16.8 MHz
reference clock it (and the voltage regulators) should be checked first in debugging the system.
The microprocessor uses XTAL Y0131 and associated components to form a Real Time Clock
(RTC). It may be used to display the time on controlheads with display or as time stamp for incoming
calls or messages. The real time clock is powered from the voltage VSTBY to keep it running while
the radio is switched off. When the radio was disconnected from it’s supply voltage, the time must be
set again.
1.9 Serial Peripheral Interface (SPI)
The µP communicates to many of the IC’s through its SPI port. This port consists of SPI TRANSMIT
DATA (MOSI) (U0101-100), SPI RECEIVE DATA (MISO) (U0101-99), SPI CLK (U0101-1) and chip
select lines going to the various ICs, connected on the SPI PORT (BUS). This BUS is a synchronous
bus, in that the timing clock signal CLK is sent while SPI data (SPI TRANSMIT DATA or SPI
RECEIVE DATA) is sent. Therefore, whenever there is activity on either SPI TRANSMIT DATA or SPI
RECEIVE DATA there should be a uniform signal on CLK. The SPI TRANSMIT DATA is used to send
serial from a µP to a device, and SPI RECEIVE DATA is used to send data from a device to a µP.
1-6 THEORY OF OPERATION
On the controller there are two ICs on the SPI BUS, ASFIC CMP (U0221-22), and EEPROM
(U0111-5). In the RF sections there are 2 ICs on the SPI BUS, the FRAC-N Synthesizer, and the
Power Control IC (PCIC). The SPI TRANSMIT DATA and CLK lines going to the RF section are
filtered by L0481 / R0481 and L0482 / R0482 to minimize noise. The chip select line CSX from
U0101 pin 2 is shared by the ASFIC CMP, FRAC-N Synthesizer and PCIC. Each of these IC‘s check
the SPI data and when the sent address information matches the IC’s address, the following data is
processed. The chip select lines for the EEPROM (EE CS), Voice Storage (VS CS), expansion board
(EXP1 CS, EXP2 CS) and option board (OPT CS) are decoded by the address decoder U0141.
When the µP needs to program any of these IC’s it brings the chip select line CSX to a logic 0 and
then sends the proper data and clock signals. The amount of data sent to the various IC’s are
different, for example the ASFIC CMP can receive up to 19 bytes (152 bits) while the PCIC can
receive up to 6 bytes (48 bits). After the data has been sent the chip select line is returned to logic 1.
The Option board interfaces are different in that the µP can also read data back from devices
connected.The timing and operation of this interface is specific to the option connected, but
generally follows the pattern:
1. an option board device generates a service request via J0551-29, line RDY and µP pin 79,
2. the main board asserts a chip select for that option board device via U0141-14, line OPT CS,
J0551-30,
3. the main board µP generates the CLK (J0551-3),
4. the main board µP writes serial data via J0551-15 and reads serial data via J0551-16 and,
5. when data transfer is complete the main board terminates the chip select and CLK activity.
1.10 SBEP Serial Interface
The SBEP serial interface allows the radio to communicate with the Customer Programming
Software (CPS), or the Universal Tuner via the Radio Interface Box (RIB). This interface connects to
the microphone connector via controlheadcontrolhead connector (J0401-8) and to the accessory
connector J0501-17 and comprises BUS+. The line is bi-directional, meaning that either the radio or
the RIB can drive the line. The microprocessor sends serial data via pin 98 and D0101 and it reads
serial data via pin 97. Whenever the microprocessor detects activity on the BUS+ line, it starts
communication.
In addition, the SBEP serial interface is used to communicate with a connected controlhead. When a
controlhead key is pressed or the volume knob is rotated, the line ON OFF CONTROL goes high.
This turns on transistor Q0110 which pulls line ON OFF SENSE and µP pin 6 to ground level. In
addition, an interrupt is generated at µP pin 96. This indicates that the controlhead wants to start
SBEP communication. The microprocessor then requests the data from the controlhead. The
controlhead starts sending and after all data has been send, the ON OFF CONTROL line goes low.
The controlheadcontrolhead ignores any data on BUS+ during SBEP communication with the CPS
or Universal Tuner.
1.11 General Purpose Input/Output
The controller provides eight general purpose lines (DIG1 through DIG8) available on the accessory
connector J0501 to interface to external options. Lines DIG IN 1,3,5,6, are inputs, DIG OUT 2 is an
output and DIG IN OUT 4,7,8 are bidirectional. The software and the hardware configuration of the
radio model define the function of each port.
DIG IN 1 can be used as external PTT input, DATA PTT input or others, set by the CPS.
The µP reads this port via pin 77 and Q0171.
Controller Circuits 1-7
DIG OUT 2 can be used as normal output or external alarm output, set by the CPS. Transistor Q0173
is controlled by the µP via ASFIC CMP pin 14.
DIG IN 3 is read by µP pin 61 via resistor R0176
DIG IN 5 can be used as normal input or emergency input, set by the CPS. The µP reads this port via
R0179 and µP pin 60. Diode D0179 limits the voltage to protect the µP input.
DIG IN 6 can be used as normal input, set by the CPS. The µP reads this port via pin 74 and Q0181.
DIG IN OUT 4,7,8 are bi-directional and use the same circuit configuration. Each port uses an output
transistor Q0177, Q0183, Q0185 controlled by µP pins 46, 47, 53. The ports are read by µP pins 75,
54, 76. To use one of the ports as input the µP must turn off the corresponding output transistor.
In addition the signals from DIG IN 1, DIG IN OUT 4 are fed to the option board connector J0551 and
the expansion board connector J0451.
1.12 Normal Microprocessor Operation
For this radio, the µP is configured to operate in one of two modes, expanded and bootstrap. In
expanded mode the µP uses external memory devices to operate, whereas in bootstrap operation
the µP uses only its internal memory. In normal operation of the radio the µP is operating in
expanded mode as described below.
In expanded mode on this radio, the µP (U0101) has access to 3 external memory devices; U0121
(FLASH EEPROM), U0122 (SRAM), U0111 (EEPROM). Also, within the µP there are 3Kbytes of
internal RAM, as well as logic to select external memory devices.
The external EEPROM (U0111) space contains the information in the radio which is customer
specific, referred to as the codeplug. This information consists of items such as: 1) what band the
radio operates in, 2) what frequencies are assigned to what channel, and 3) tuning information. (See
the particular device subsection for more details.)
The external SRAM (U0122) as well as the µP’s own internal RAM space are used for temporary
calculations required by the software during execution. All of the data stored in both of these
locations is lost when the radio powers off (See the particular device subsection for more details).
The FLASH EEPROM contains the actual Radio Operating Software. This software is common to all
open architecture radios within a given model type. For example Trunking radios may have a different
version of software in the FLASH EEPROM than a non Trunking radio (See the particular device
subsection for more details).
The µP provides an address bus of 16 address lines (ADDR 0 - ADDR 15), and a data bus of 8 data
lines (DATA 0 - DATA 7). There are also 3 control lines; CSPROG (U0101-38) to chip select U0121-
30 (FLASH EEPROM), CSGP2 (U0101-41) to chip select U0122-20 (SRAM) and PG7 R W (U0101-
4) to select whether to read or to write. The external EEPROM (U0111-1), the OPTION BOARD and
EXPANSION BOARD are selected by 3 lines of the µP using address decoder U0141. The chips
ASFIC CMP / FRAC-N / PCIC are selected by line CSX (U0101-2).
When the µP is functioning normally, the address and data lines should be toggling at CMOS logic
levels. Specifically, the logic high levels should be between 4.8 and 5.0V, and the logic low levels
should be between 0 and 0.2V. No other intermediate levels should be observed, and the rise and fall
times should be <30ns.
The low-order address lines (ADDR 0 - ADDR 7) and the data lines (DATA 0-DATA 7) should be
toggling at a high rate, e. g. , you should set your oscilloscope sweep to 1us/div. or faster to observe
individual pulses. High speed CMOS transitions should also be observed on the µP control lines.
1-8 THEORY OF OPERATION
On the µP the lines XIRQ (U0101-48), MODA LIR (U0101-58), MODB VSTPY (U0101-57) and
RESET (U0101-94) should be high at all times during normal operation. Whenever a data or address
line becomes open or shorted to an adjacent line, a common symptom is that the RESET line goes
low periodically, with the period being in the order of 20msecs. In the case of shorted lines you may
also detect the line periodically at an intermediate level, i.e. around 2.5V when 2 shorted lines
attempt to drive to opposite rails.
The MODA LIR (U0101-58) and MODB VSTPY (U0101-57) inputs to the µP must be at a logic 1 for
it to start executing correctly. After the µP starts execution it will periodically pulse these lines to
determine the desired operating mode. While the Central Processing Unit (CPU) is running, MODA
LIR is an open-drain CMOS output which goes low whenever the µP begins a new instruction (an
instruction typically requires 2-4 external bus cycles, or memory fetches). However, since it is an
open-drain output, the waveform rise assumes an exponential shape similar to an RC circuit.
There are 8 analogue to digital converter ports (A/D) on U0101. They are labelled within the device
block as PE0-PE7. These lines sense the voltage level ranging from 0 to 5V of the input line and
convert that level to a number ranging from 0 to 255 which can be read by the software to take
appropriate action.
For example U0101-67 is the battery voltage detect line. R0671 and R0672 form a resistor divider on
INT SWB+. With 30K and 10K and a voltage range of 11V to 17V, that A/D port would see 2.74V to
4.24V which would then be converted to ~140 to 217 respectively.
U0101-69 is the high reference voltage for the A/D ports on the µP. Capacitor C0101 filters the +5V
reference. If this voltage is lower than +5V the A/D readings will be incorrect. Likewise U0101-68 is
the low reference for the A/D ports. This line is normally tied to ground. If this line is not connected to
ground, the A/D readings will be incorrect.
1.13 FLASH Electronically Erasable Programmable Memory (FLASH EEPROM)
The 512KByte FLASH EEPROM (U0121) contains the radio’s operating software. This software is
common to all open architecture radios within a given model type. For example Trunking radios may
have a different version of software in the FLASH EEPROM than a non Trunking radio. This is, as
opposed to the codeplug information stored in EEPROM (U0111) which could be different from one
user to another in the same company.
In normal operating mode, this memory is only read, not written to. The memory access signals (CE,
OE and WE) are generated by the µP.
To upgrade/reprogram the FLASH software, the µP must be set in bootstrap operating mode. This is
done by pulling microprocessor pins MODA LIR (U0101-58) and MODB VSTBY (U0101-57) to low
during power up. When accessory connector pin 18 is at ground level, diode D0151 will pull both
microprocessor pins to low. The same can be done by a level of 12 volts on line ON OFF CONTROL
from the controlhead. Q0151 pulls diode D0151 and in turn both microprocessor pins to low. Diode
VR0151 prevents entering bootstrap operating mode during normal power up.
In bootstrap operating mode the µP controls the FLASH EN OE (U0121-32) input by µP pin 86. Chip
select (U0121-30) and read or write operation (U0121-7) are controlled by µP pins 38 and 4.
The FLASH device may be reprogrammed 1,000 times without issue. It is not recommended to
reprogram the FLASH device at a temperature below 0°C.
Capacitor C0121 serves to filter out any AC noise which may ride on +5V at U0121.
Controller Board Audio and Signalling Circuits 1-9
1.14 Electrically Erasable Programmable Memory (EEPROM)
The external 16 Kbyte EEPROM (U0111) contains additional radio operating parameters such as
operating frequency and signalling features, commonly know as the codeplug. It is also used to store
radio operating state parameters such as current mode and volume. This memory can be written to
in excess of 100,000 times and will retain the data when power is removed from the radio. The
memory access signals (SI, SO and SCK) are generated by the µP and chip select (CS) is generated
by address decoder U0141-15.
1.15 Static Random Access Memory (SRAM)
The SRAM (U0121) contains temporary radio calculations or parameters that can change very
frequently, and which are generated and stored by the software during its normal operation. The
information is lost when the radio is turned off.
The device allows an unlimited number of write cycles. SRAM accesses are indicated by the CS
signal U0122-20 (which comes from U0101-CSGP2) going low. U0122 is commonly referred to as
the external RAM as opposed to the internal RAM which is the 3 Kbytes of RAM which is part of the
68HC11FL0. Both RAM spaces serve the purpose. However, the internal RAM is used for the
calculated values which are accessed most often.
Capacitor C0122 serves to filter out any ac noise which may ride on +5V at U0122.
2.0 Controller Board Audio and Signalling Circuits
2.1 General - Audio Signalling Filter IC with Compander (ASFIC CMP)
The ASFIC CMP (U0221) used in the controller has 4 functions;
1) RX/TX audio shaping, i.e. filtering, amplification, attenuation
2) RX/TX signalling, PL/DPL/HST/MDC/MPT
3) Squelch detection
4) Microprocessor clock signal generation (see Microprocessor Clock Synthesizer Description).
The ASFIC CMP is programmable through the SPI BUS (U0221-20/21/22), normally receiving 19
bytes. This programming sets up various paths within the ASFIC CMP to route audio and/or
signalling signals through the appropriate filtering, gain and attenuator blocks. The ASFIC CMP also
has 6 General Control Bits GCB0-5 which are CMOS level outputs and used for NOISE BLANKER
(GCB0) in Low Band radios, EXTERNAL ALARM (GCB1) and DC POWER ON (GCB2) to switch the
voltage regulators (and the radio) on and off. GCB3 controls U0251 pin 11 to output either RX FLAT
AUDIO or RX FILTERED AUDIO on the accessory connector pin 11. GCB4 controls U0251 pin 10 to
use either the external microphone input or the voice storage playback signal. GCB5 is used to
switch the audio PA on and off.
1-10 THEORY OF OPERATION
2.2 Transmit Audio Circuits
Refer to Figure 3-1 for reference for the following sections.
Figure 3-1 Transmit Audio Paths
2.2.1 Mic/Data Input Path
The radio supports 2 distinct microphone paths known as internal (from controlhead) and external
mic (from accessory connector J0501-2) and an auxiliary path (FLAT TX AUDIO, from accessory
connector J0501-5). The microphones used for the radio require a DC biasing voltage provided by a
resistive network.
These two microphone audio input paths enter the ASFIC CMP at U0221-48 (external mic) and
U0221-46 (internal mic). Following the internal mic path; the microphone is plugged into the radio
controlhead and is connected to the controller board via J0401-9.
From here the signal is routed via R0409 and line INT MIC to R0205. R0201 and R0202 provide the
9.3VDC bias. Resistive divider R0205 / R0207 divide the input signal by 5.5 and provide input
protection for the CMOS amplifier input. R0202 and C0201 provide a 560 ohm AC path to ground
that sets the input impedance for the microphone and determines the gain based on the emitter
resistor in the microphone’s amplifier circuit.
C0204 serves as a DC blocking capacitor. The audio signal at U0221-46 (TP0221) should be
approximately 14mV for 1.5kHz or 3kHz of deviation with 12.5kHz or 25kHz channel spacing.
The external microphone signal enters the radio on accessory connector J0501 pin 2 and is routed
via line EXT MIC to R0206. R0203 and R0204 provide the 9.3VDC bias. Resistive divider R0206 /
R0208 divide the input signal by 5.5 and provide input protection for the CMOS amplifier input.
R0204 and C0202 provide a 560 ohm AC path to ground that sets the input impedance for the
microphone and determines the gain based on the emitter resistor in the microphone’s amplifier
circuit.
MIC
IN
MOD IN TO
RF
SECTION
(SYNTHESIZER)
36
44
33
40
J0501
ACCESSORY
CONNECTOR
J0401
CONTROL HEAD
CONNECTOR
MIC
EXT MIC
FLAT TX
AUDIO
42
32
5
48
46
9
2
IN OUT
OPTION
BOARD
FILTERS AND
PREEMPHASIS
HS SUMMER
SPLATTER
FILTER
LS SUMMER
LIMITER
ATTENUATOR
VCO
ATN
TX RTN
TX SND
MIC
INT
AUX
TX
ASFIC_CMP
U0221
TP0221
TP0222
MIC
EXT
J0451 J0551
18
FLAT
TX RTN
EXPANSION BOARD
31 IN/OUT
39 OUT
FROM
µP Pin3
U0211-4
Controller Board Audio and Signalling Circuits 1-11
C0254 serves as a DC blocking capacitor. Multi switch U0251 controlled by ASFIC CMP port GCB4
selects either the external microphone input signal or the voice storage playback signal for entering
the ASFIC CMP at pin 48. The audio signal at U0221-48 (TP0222) should be approximately 14mV
for 1.5kHz or 3kHz of deviation with 12.5kHz or 25kHz channel spacing.
The FLAT TX AUDIO path is used for transmitting data signals and has therefore no limiter or filters
enabled inside the ASFIC CMP. When this path is enabled via CPS and DATA PTT is asserted, any
signal on this path is directly fed to the modulator. Signals applied to this path either via accessory
connector J0501, expansion board connector J0451 or option board connector J0551 must be
filtered and set to the correct level externally or on the option board in order not to exceed the
maximum specified transmit deviation and transmitted power in the adjacent channels. The
attenuator inside the ASFIC CMP changes the FM deviation of the data signal according to the
channel spacing of the active transmit channel.
The FLAT TX AUDIO signal from accessory connector J0501-5 is fed to the ASFIC CMP (U0221)
pin42 through C0541 and line FLAT TX RTN, switch U0251 and buffer U0211-4. When the radio
switches from receive to transmit mode the µP opens switch U0251 for a short period to prevent that
any applied signal can cause a transmit frequency offset. Buffer U0211-4 sets the correct DC level
and ensures a short settle period when the radio is switched on. Inside the ASFIC CMP the signal is
routed directly to the attenuator, which sets the FM deviation according to the channel spacing of the
active transmit channel and emerges from the ASFIC CMP at U0221-40, at which point it is routed to
the RF section.
The ASFIC has an internal AGC that can control the gain in the mic audio path. The AGC can be
disabled / enabled by the µP. Another feature that can be enabled or disabled in the ASFIC is the
VOX. This circuit, along with the capacitor at U0221-7, provides a DC voltage that can allow the µP to
detect microphone audio. The ASFIC can also be programmed to route the microphone audio to the
speaker for public address operation.
2.2.2 PTT Sensing and TX Audio Processing
Microphone PTT coming from the controlhead is sent via SBEP bus to the microprocessor. An
external PTT can be generated by grounding pin 3 on the accessory connector if this input is
programmed for PTT by the CPS. When microphone PTT is sensed, the µP will always configure the
ASFIC CMP for the "internal" mic audio path, and external PTT will result in the external mic audio
path being selected.
Inside the ASFIC CMP, the mic audio is filtered to eliminate frequency components outside the 300-
3000Hz voice band, and pre-emphasized if pre-emphasis is enabled. The signal is then limited to
prevent the transmitter from over deviating. The limited mic audio is then routed through a summer,
which is used to add in signalling data, and then to a splatter filter to eliminate high frequency
spectral components that could be generated by the limiter. The audio is then routed to an
attenuator, which is tuned in the factory or the field to set the proper amount of FM deviation. The TX
audio emerges from the ASFIC CMP at U0221-40 MOD IN, at which point it is routed to the RF
section.
Dependent on the radio model, input pin 3 on the accessory connector can be programmed for DATA
PTT by the CPS. When DATA PTT is sensed, the µP will always configure the ASFIC CMP for the flat
TX audio path. Limiter and any filtering will be disabled. The signal is routed directly to the attenuator,
which sets the FM deviation according to the channel spacing of the active transmit channel and
emerges from the ASFIC CMP at U0221-40, at which point it is routed to the RF section.
2.2.3 TX Secure Audio (optional)
The audio follows the normal transmit audio processing until it emerges from the ASFIC CMP TX
SND pin (U0221-44), which is fed to the Secure board residing at option connector J0551-33. The
1-12 THEORY OF OPERATION
Secure board contains circuitry to amplify, encrypt, and filter the audio. The encrypted signal is then
fed back from J0551-32 to the ASFIC CMP TX RTN input (U0221-36). The signal level at this pin
should be about 65mVrms. The signal is then routed through the TX path in the ASFIC CMP and
emerges at MOD IN pin 40.
2.2.4 Option Board Transmit Audio
The audio follows the normal transmit audio processing until it emerges from the ASFIC CMP TX
SND pin (U0221-44), which is fed to the option board residing at option connector J0551-33. The
option board contains circuitry to process the audio. The processed signal is then fed back from
J0551-32 to the ASFIC CMP TX RTN input (U0221-36). The signal level at this pin should be about
65mVrms. The signal is then routed through the TX path in the ASFIC CMP and emerges at MOD IN
pin 40.
2.3 Transmit Signalling Circuits
Refer to Figure 4-1 for reference for the following sections.
Figure 4-1 Transmit Signalling Paths
From a hardware point of view, there are 3 types of signalling:
1) sub-audible data (PL / DPL / Connect Tone) that gets summed with transmit voice or signalling,
2) DTMF data for telephone communication in trunked and conventional systems, and
3) Audible signalling including Select 5, MPT-1327, MDC, High speed Trunking.
NOTE: All three types are supported by the hardware while the radio software determines which
signalling type is available.
2.3.1 Sub-audible Data (PL/DPL)
Sub-audible data implies signalling whose bandwidth is below 300Hz. PL and DPL waveforms are
used for conventional operation and connect tones for trunked voice channel operation. The trunking
connect tone is simply a PL tone at a higher deviation level than PL in a conventional system.
Although it is referred to as "sub-audible data," the actual frequency spectrum of these waveforms
19
18
40
MOD IN
TO RF
SECTION
(SYNTHESIZER)
80
44 HIGH SPEED
CLOCK IN
(HSIO)
LOW SPEED
CLOCK IN
(LSIO)
ASFIC_CMP U0221
MICRO
CONTROLLER
U0101
HS
SUMMER
5-3-2 STATE
ENCODER
DTMF
ENCODER
SPLATTER
FILTER
PL
ENCODER LS
SUMMER
ATTENUATOR
85
82
SPI
BUS
Controller Board Audio and Signalling Circuits 1-13
may be as high as 250 Hz, which is audible to the human ear. However, the radio receiver filters out
any audio below 300Hz, so these tones are never heard in the actual system.
Only one type of sub-audible data can be generated by U0221 (ASFIC CMP) at any one time. The
process is as follows, using the SPI BUS, the µP programs the ASFIC CMP to set up the proper low-
speed data deviation and select the PL or DPL filters. The µP then generates a square wave which
strobes the ASFIC PL / DPL encode input LSIO U0221-18 at twelve times the desired data rate. For
example, for a PL frequency of 103Hz, the frequency of the square wave would be 1236Hz.
This drives a tone generator inside U0221 which generates a staircase approximation to a PL sine
wave or DPL data pattern. This internal waveform is then low-pass filtered and summed with voice or
data. The resulting summed waveform then appears on U0221-40 (MOD IN), where it is sent to the
RF board as previously described for transmit audio. A trunking connect tone would be generated in
the same manner as a PL tone.
2.3.2 High Speed Data
High speed data refers to the 3600 baud data waveforms, known as Inbound Signalling Words
(ISWs) used in a trunking system for high speed communication between the central controller and
the radio. To generate an ISW, the µP first programs the ASFIC CMP (U0221) to the proper filter and
gain settings. It then begins strobing U0221-19 (HSIO) with a pulse when the data is supposed to
change states. U0221’s 5-3-2 State Encoder (which is in a 2-state mode) is then fed to the post-
limiter summer block and then the splatter filter. From that point it is routed through the modulation
attenuators and then out of the ASFIC CMP to the RF board. MPT 1327 and MDC are generated in
much the same way as Trunking ISW. However, in some cases these signals may also pass through
a data pre-emphasis block in the ASFIC CMP. Also these signalling schemes are based on sending
a combination of 1200 Hz and 1800 Hz tones only. Microphone audio is muted during High Speed
Data signalling.
2.3.3 Dual Tone Multiple Frequency (DTMF) Data
DTMF data is a dual tone waveform used during phone interconnect operation. It is the same type of
tones which are heard when using a "Touch Tone" telephone.
There are seven frequencies, with four in the low group (697, 770, 852, 941Hz) and three in the high
group (1209, 1336, 1477Hz).
The high-group tone is generated by the µP (U0101-44) strobing U0221-19 at six times the tone
frequency for tones less than 1440Hz or twice the frequency for tones greater than 1440Hz. The low
group tone is generated by the ASFIC CMP, controlled by the µP via SPI bus. Inside U0221 the low-
group and high-group tones are summed (with the amplitude of the high group tone being
approximately 2 dB greater than that of the low group tone) and then pre-emphasized before being
routed to the summer and splatter filter. The DTMF waveform then follows the same path as was
described for high-speed data.
1-14 THEORY OF OPERATION
2.4 Receive Audio Circuits
Refer to Figure5-5 for reference for the following sections.
Figure 4-1 Receive Audio Paths
2.4.1 Squelch Detect
The radio’s RF circuits are constantly producing an output at the discriminator (IF IC). This signal
(DISC AUDIO) is routed to the ASFIC CMP’s squelch detect circuitry input DISC (U0221-2). All of
the squelch detect circuitry is contained within the ASFIC CMP. Therefore from a user’s point of view,
DISC AUDIO enters the ASFIC CMP, and the ASFIC CMP produces two CMOS logic outputs based
on the result. They are CH ACT (U0221-16) and SQ DET (U0221-17).
The squelch signal entering the ASFIC CMP is amplified, filtered, attenuated, and rectified. It is then
sent to a comparator to produce an active high signal on CH ACT. A squelch tail circuit is used to
produce SQ DET (U0221-17) from CH ACT. The state of CH ACT and SQ DET is high (logic 1) when
carrier is detected, otherwise low (logic 0).
CH ACT is routed to the µP pin 84 while SQ DET is routed to the µP pin 83.
SQ DET is used to determine all audio mute / unmute decisions except for Conventional Scan. In
this case CH ACT is a pre-indicator as it occurs slightly faster than SQ DET.
FLT/FLAT RX AUDIO
J0501
11
16
1EXTERNAL
SPEAKER
INTERNAL
SPEAKER
ACCESSORY
CONNECTOR
CONTROLHEAD
CONNECTOR
HANDSET
AUDIO
7
2
3
J0401
INT
SPKR-
SPKR +
SPKR -
1
9
2
J0551
4110
INT
SPKR+
4
6
DISC
ASFIC_CMP
U0221
AUDIO
PA
U0271
IN
OPTION
BOARD
IN
OUT VOLUME
ATTEN.
FILTER AND
DEEMPHASIS
17
MICRO
CONTROLLER
U0101
80
FROM
RF
SECTION
(IF IC) LIMITER, RECTIFIER
FILTER, COMPARATOR
SQ DET
SQUELCH
CIRCUIT
16
PL FILTER
LIMITER
CH ACT
AUX RX
43
18
LS IO
U IO AUDIO
83
84
39
URX OUT
17
J0451
EXPANSION
BOARD
DISC
AUDIO
34
28
35
85
IN
7
Controller Board Audio and Signalling Circuits 1-15
2.4.2 Audio Processing and Digital Volume Control
The receiver audio signal enters the controller section from the IF IC on DISC AUDIO. The signal is
DC coupled by R0228 and enters the ASFIC CMP via the DISC pin U0221-2.
Inside the ASFIC CMP, the signal goes through 2 paths in parallel, the audio path and the PL/DPL
path.
The audio path has a programmable amplifier, whose setting is based on the channel bandwidth
being received, then a LPF filter to remove any frequency components above 3000Hz and then an
HPF to strip off any sub-audible data below 300Hz. Next, the recovered audio passes through a de-
emphasis filter if it is enabled (to compensate for Pre-emphasis which is used to reduce the effects of
FM noise). The IC then passes the audio through the 8-bit programmable attenuator whose level is
set depending on the value of the volume control. Finally the filtered audio signal passes through an
output buffer within the ASFIC CMP. The audio signal exits the ASFIC CMP at pin AUDIO (U0221-
41).
The µP programs the attenuator, using the SPI BUS, based on the volume setting. The minimum /
maximum settings of the attenuator are set by codeplug parameters.
Since sub-audible signalling is summed with voice information on transmit, it must be separated from
the voice information before processing. Any sub-audible signalling enters the ASFIC CMP from the
IF IC at DISC U0221-2. Once inside it goes through the PL/DPL path. The signal first passes through
one of 2 low pass filters, either PL low pass filter or DPL/LST low pass filter. Either signal is then
filtered and goes through a limiter and exits the ASFIC CMP at LSIO (U0221-18). At this point the
signal will appear as a square wave version of the sub-audible signal which the radio received. The
microprocessor U0101-80 will decode the signal directly to determine if it is the tone / code which is
currently active on that mode.
2.4.3 Audio Amplification Speaker (+) Speaker (-)
The output of the ASFIC CMP’s digital volume pot, U0221-41 is routed through dc blocking capacitor
C0265 to a buffer formed by U0211-1. Resistors R0265 and R0268 set the correct input level to the
audio PA (U0271). This is necessary because the gain of the audio PA is 46 dB, and the ASFIC CMP
output is capable of overdriving the PA unless the maximum volume is limited. Resistor R0267 and
capacitor C0267 increase frequency components below 350 Hz.
The audio then passes through R0269 and C0272 which provides AC coupling and low frequency
roll-off. C0273 provides high frequency roll-off as the audio signal is routed to pins 1 and 9 of the
audio power amplifier U0271.
The audio power amplifier has one inverted and one non-inverted output that produces the
differential audio output SPK+ / SPK- (U0271-4/6). The inputs for each of these amplifiers are pins 1
and 9 respectively; these inputs are both tied to the received audio. The audio PA’s DC biases are
not activated until the audio PA is enabled at pin 8.
The audio PA is enabled via the ASFIC CMP (U0221-38). When the base of Q0271 is low, the
transistor is off and U0271-8 is high, using pull up resistor R0273, and the Audio PA is ON. The
voltage at U0273-8 must be above 8.5VDC to properly enable the device. If the voltage is between
3.3 and 6.4V, the device will be active but has its input (U0273-1/9) off. This is a mute condition which
is used to prevent an audio pop when the PA is enabled.
The SPK+ and SPK- outputs of the audio PA have a DC bias which varies proportionately with FLT
A+ (U0271-7). FLT A+ of 11V yields a DC offset of 5V, and FLT A+ of 17V yields a DC offset of 8.5V.
If either of these lines is shorted to ground, it is possible that the audio PA will be damaged. SPK+
and SPK- are routed to the accessory connector (J0501-16 and 1) and to the controlhead (connector
J0401-2 and 3).
1-16 THEORY OF OPERATION
2.4.4 Handset Audio
Certain hand held accessories have a speaker within them which require a different voltage level
than that provided by U0271. For those devices HANDSET AUDIO is available at controlhead
connector J0401-7.
The received audio from the output of the ASFIC CMP’s digital volume attenuator and buffered by
U0211-1 is also routed to U0211-3 pin 9 where it is amplified 20 dB; this is set by the 10k/100k
combination of R0261 and R0262. This signal is routed from the output of the op amp U0211-3 pin 8
to J0401-7. The controlhead sends this signal directly out to the microphone jack. The maximum
value of this output is 6.6Vp-p.
2.4.5 Filtered Audio and Flat Audio
The ASFIC CMP has an audio whose output at U0221-39 has been filtered and de-emphasized, but
has not gone through the digital volume attenuator. From ASFIC CMP U0221-39 the signal is routed
via R0251 through gate U0251-12 and AC coupled to U0211-2. The gate controlled by ASFIC CMP
port GCB3 (U0221-35) selects between the filtered audio signal from the ASFIC CMP pin 39
(URXOUT) or the unfiltered (flat) audio signal from the ASFIC CMP pin 10 (UIO). R0251 and R0253
determine the gain of op-amp U0211-2 for the filtered audio while R0252 and R0253 determine the
gain for the flat Audio. The output of U0253-7 is then routed to J0501-11 via dc blocking capacitor
C0542 and R0531. Note that any volume adjustment of the signal on this path must be done by the
accessory
2.4.6 RX Secure Audio (optional)
Discriminator audio, which is now encrypted audio, follows the normal receive audio processing until
it emerges from the ASFIC CMP UIO pin (U0221-10), which is fed to the Secure board residing at
option connector J0551-35. On the Secure board, the encrypted signal is converted back to normal
audio format, and then fed back through (J0551-34) to AUX RX of the ASFIC CMP (U0221-43).
From then on it follows a path identical to conventional receive audio, where it is filtered (0.3 - 3kHz)
and de-emphasized. The signal URX SND from the ASFIC CMP (U0221-39), also routed to option
connector J0551-28, is not used for the Secure board but for other option boards.
2.4.7 Option Board Receive Audio
Unfiltered audio from the ASFIC CMP pin UIO (U0221-10) enters the option board at connector
J0551-35. Filtered audio from the ASFIC CMP pin URXOUT (U0221-39) enters the option board at
connector J0551-28. On the option board, the signal may be processed, and then fed back through
J0551-34 to AUX RX of the ASFIC CMP (U0221-43). From then on it follows a path identical to
conventional receive audio, where it may be filtered (0.3 - 3kHz) and de-emphasized.
Controller Board Audio and Signalling Circuits 1-17
2.5 RECEIVE SIGNALLING CIRCUITS
Refer to Figure 5-6 for reference for the following sections.
Figure 4-2 Receive Signalling Paths
2.5.1 Sub-audible (PL/DPL) and High Speed Data Decoder
The ASFIC CMP (U0221) is used to filter and limit all received data. The data enters the ASFIC CMP
at input DISC (U0221-2). Inside U0221 the data is filtered according to data type (HS or LS), then it
is limited to a 0-5V digital level. The MDC and trunking high speed data appear at U0221-19, where
it connects to the µP U0101-82
The low speed limited data output (PL, DPL, and trunking LS) appears at U0221-18, where it
connects to the µP U0101-80.
The low speed data is read by the µP at twice the frequency of the sampling waveform; a latch
configuration in the ASFIC CMP stores one bit every clock cycle. The external capacitors C0236, and
C0244 set the low frequency pole for a zero crossings detector in the limiters for PL and HS data.
The hysterisis of these limiters is programmed based on the type of received data.
2.5.2 Alert Tone Circuits
When the software determines that it needs to give the operator an audible feedback (for a good key
press, or for a bad key press), or radio status (trunked system busy, phone call, circuit failures), it
sends an alert tone to the speaker. It does so by sending SPI BUS data to U0221 which sets up the
audio path to the speaker for alert tones. The alert tone itself can be generated in one of two ways:
internally by the ASFIC CMP, or externally using the µP and the ASFIC CMP.
The allowable internal alert tones are 304, 608, 911, and 1823Hz. In this case a code contained
within the SPI BUS load to the ASFIC CMP sets up the path and determines the tone frequency, and
at what volume level to generate the tone. (It does not have to be related to the voice volume setting).
For external alert tones, the µP can generate any tone within the 100-3000Hz audio band. This is
accomplished by the µP generating a square wave which enters the ASFIC CMP at U0221-19.
Inside the ASFIC CMP this signal is routed to the alert tone generator
The output of the generator is summed into the audio chain just after the RX audio de-emphasis
block. Inside U0221 the tone is amplified and filtered, then passed through the 8-bit digital volume
attenuator, which is typically loaded with a special value for alert tone audio. The tone exits at U0221-
41 and is routed to the audio PA like receive audio
DET AUDIO
DISCRIMINATOR AUDIO
FROM RF SECTION
(IF IC)
19
18
25
2
82
80
DISC
PLCAP2
LSIO
HSIO
DATA FILTER
AND DEEMPHASIS LIMITER
FILTER LIMITER
ASFIC_CMP
U0221
MICRO
CONTROLLER
U0101
85
44
8
PLCAP
1-18 THEORY OF OPERATION
2.6 Voice Storage (optional)
The Voice Storage (VS) option can be used to store audio signals coming from the receiver or from
the microphone. Any stored audio signal can be played back over the radio’s speaker or sent out via
the radio’s transmitter.
The Voice Storage option can by placed on the controller section or on an additional option board
which resides on option board connector J0551. Voice Storage IC U0301 provides all required
functionality and is powered from 3.3 volts regulator U0351 which,is powered from the regulated 5
volts. Dual shottky diode D0301 reduces the supply voltage for U0301 to 3 volts. The microprocessor
controls U0301 via SPI bus lines CLK (U0301-8), DATA (U0301-10) and MISO (U0301-11). To
transfer data, the µP first selects the U0301 via address decoder U0141, line VS CS and U0301 pin
9. Then the µP sends data through line DATA and receives data through line MISO. Pin 2 (RAC) of
U0301 indicates the end of a message row by a low state for 12.5 ms and connects to µP pin 52. A
low at pin 5 (INT), which is connected to µP pin 55 indicates that the Voice Storage IC requires
service from the µP.
Audio, either from the radio’s receiver or from one of the microphone inputs, emerges the ASFIC
CMP (U0221) at pin 39, is buffered by op-amp U0341-1 and enters the Voice Storage IC U0301 at
pin 25. During playback, the stored audio emerges U0301 at pin 20. To transmit the audio signal it is
fed through resistive divider R0344 / R0345 and line VS MIC to input selector IC U0251. When this
path is selected by the µP via ASFIC CMP port GCB 4, the audio signal enters the ASFIC CMP at
pin 48 and is processed like normal transmit audio. To play the stored audio over the radio’s speaker,
the audio from U0301 pin 20 is buffered by op-amp U0341-2 and fed via switch U0342 and line FLAT
RX SND to ASFIC CMP pin 10 (UIO). In this case, this ASFIC CMP pin is programmed as input and
feeds the audio signal through the normal receiver audio path to the speaker or handset. Switch
U0342 is controlled by the µP via ASFIC CMP port GCB 4 and feeds the stored audio only to the
ASFIC CMP port UIO when it is programmed as input.
Chapter 2
TROUBLESHOOTING CHARTS
1.0 Controller Troubleshooting Chart
Controller Check
Power Up
Alert Tone
OK?
Speaker &
Control
Head OK?
U0101
EXTAL=
7.3728 MHz/
14.7456
MHz?
BUS+
activity when
volume knob
rotated?
MCU is OK
Not able to
program
RF Board ICs
Before replacing
MCU, check SPI
clock, SPI data,
and RF IC select
Replace
Speaker / Con-
trol Head
U0221 Pin 34 =
16.8 MHz?
Check
FGU
Reprogram the
correct data. &
Check ASFIC
and MCU
Check Control
Head and MCU
(U0101, U0121,
U0122, U0111)
Press PTT. No
RF Output Pow-
er.
Red LED
lights up?
Check
Control
Head
Check
FGU &
Transmitter
Audio
at Pin 41
U0221?
Enable External PTT
with CPS
External PTT en-
abled with CPS?
Radio could
not PTT
externally
DC
at as-
signed Acc.
Con. Pin
DC chang-
es?
Check Components
between U0221 and
U0271
Check Con-
nection to uP
port
PTT
NO
YES
NO
YES YES
YES
YES
NO
NO
YES
NO
YES
NO
YES
NO
YES
EXT
PTT
RX
AUDIO
Check
Accessories
J0501
Audio at Pin
16 &
Pin 1
Check Spk.
Flex Connec-
tion & Control
Audio
at Audio PA
(U0271)
input
Check AS-
FIC U0221
Check
Audio PA
(U0271)
Check Re-
ceiver &
IF IC
Audio at
Pin 2
U0221?
NO
NO
NO
YES
YES
NO
YES
NO
Before troubleshooting the controller section ac-
cording to this chart please check the following:
1. Check tuning and CPS settings
2. Check if Alert Tones are enabled
3. Check if Control Head is OK
4. Check board visually
9.3V
DC at Pin 5
of U0641?
YES
NO
5V DC at
Pin OUT of
U0651?
YES
NO
Check U0641, Q0641,
Q0661, D0660 &
D0661
Check U0651, D0651,
D0621
2-2 TROUBLESHOOTING CHARTS
Chapter 3
CONTROLLER SCHEMATICS / PARTS LIST
1.0 Allocation of Schematics and Circuit Boards
1.1 Controller Circuits
This Chapter shows the Schematics and the the Parts Lists for the Controller circuits.
1.2 Voice Storage Facility
The Voice Storage is fitted on all MPT radios GM640/660/1280 and on GM380 as standard.
The schematics, component layout and parts list for these circuits are shown in this chapter.
The Voice Storage schematic is shown in Tables below.
.
.
Table 3-1 Controller T2 Diagrams and Parts Lists
Controller T2 used on PCB :
8486172B04 VHF, 1-25W
SCHEMATICS
Controller Overall
Supply Voltage
Audio
I/O
Microprocessor
Page 3-3
Page 3-4
Page 3-5
Page 3-6
Page 3-7
Parts List
Controller T2 Page 3-8
Table 3-2 Controller T5 Diagrams and Parts Lists
Controller T5 used on PCB :
8486172B06 VHF, 1-25W
SCHEMATICS
Controller Overall
Supply Voltage
Audio
I/O
Microprocessor
Voice Storage (if fitted)
Page 3-10
Page 3-11
Page 3-12
Page 3-13
Page 3-14
Page 3-15
Parts List
Controller T5 Page 3-16
Table 3-3 Controller T6/7 Diagrams and Parts Lists
Controller T6/T7 used on PCB :
T6 on 8486206B06 LB1, 25-60W
T6 on 8486207B05 LB2, 25-60W
T6 on 8486140B12 VHF, 25-45W
T6 on 8480643z06 UHF B1, 25-40W
T7 on 8486172B07 VHF, 1-25W
T7 on 8485670z02 UHF B1, 1-25W
SCHEMATICS
Controller Overall
Supply Voltage
Audio
I/O T6
I/O T7
Microprocessor
Voice Storage (if fitted)
Page 3-18
Page 3-19
Page 3-20
Page 3-21
Page 3-22
Page 3-23
Page 3-24
Parts List
Controller T6/T7 Page 3-25
3-2 Controller schematics / parts list
.
.
.
Table 3-4 Controller T9 Diagrams and Parts Lists
Controller T9 used on PCB :
8486172B08 VHF, 1-25W
8486140B13 VHF, 25-45W
8485670z03 UHF B1, 1-25W
8485908Z02 LB3, 25-60W
SCHEMATICS
Controller Overall
Supply Voltage
Audio
I/O
Microprocessor
Voice Storage (if fitted)
Page 3-27
Page 3-28
Page 3-29
Page 3-30
Page 3-31
Page 3-32
Parts List
Controller T9 Page 3-33
Table 3-5 Controller T11 Diagrams and Parts Lists
Controller T11 used on PCB :
8486206B08 LB1, 25-60W
8486207B07 LB2, 25-60W
8485908Z04 LB3, 25-60W
SCHEMATICS
Controller Overall
Supply Voltage
Audio
I/O
Microprocessor
Page 3-35
Page 3-36
Page 3-37
Page 3-38
Page 3-39
Parts List
Controller T11 Page 3-40
Table 3-6 Controller T12 Diagrams and Parts Lists
Controller T12 used on PCB :
8486127B01 UHF, 25-40W
8486140B15 VHF, 25-45W
SCHEMATICS
Controller Overall
Supply Voltage
Audio
I/O
Microprocessor
Voice Storage (if fitted)
Page 3-42
Page 3-43
Page 3-44
Page 3-45
Page 3-46
Page 3-47
Parts List
Controller T12 Page 3-48
Professional Radio
GM Series
VHF (136-174MHz)
Service Information
Issue: August 2002
ii
Computer Software Copyrights
The Motorola products described in this manual may include copyrighted Motorola computer programs stored
in semiconductor memories or other media. Laws in the United States and other countries preserve for
Motorola certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or
reproduce in any form, the copyrighted computer program. Accordingly, any copyrighted Motorola computer
programs contained in the Motorola products described in this manual may not be copied or reproduced in
any manner without the express written permission of Motorola. Furthermore, the purchase of Motorola
products shall not be deemed to grant, either directly or by implication, estoppel or otherwise, any license
under the copyrights, patents or patent applications of Motorola, except for the normal non-exclusive royalty-
free license to use that arises by operation of law in the sale of a product.
iii
Table of Contents
Chapter 1 MODEL CHART AND TECHNICAL SPECIFICATIONS
1.0 GM140/GM160 Model Chart................................................................................1-1
2.0 GM340/GM360/GM380 Model Chart ...................................................................1-1
3.0 GM640/GM660/GM1280 Model Chart .................................................................1-2
4.0 Technical Specifications ......................................................................................1-3
Chapter 2 THEORY OF OPERATION
1.0 Introduction ..........................................................................................................2-1
2.0 VHF (136-174MHz) Receiver...............................................................................2-1
2.1 Receiver Front-End .......................................................................................2-1
2.1 Front-End Band-Pass Filters & Pre-Amplifier .................................................2-2
2.2 First Mixer and High Intermediate Frequency (IF)..........................................2-2
2.3 Low Intermediate Frequency (IF) and Receiver Back End.............................2-2
3.0 VHF (136-174MHz) Transmitter Power Amplifier (PA) 25 W.....................2-3
3.1 First Power Controlled Stage..........................................................................2-3
3.2 Power Controlled Driver Stage .......................................................................2-4
3.3 Final Stage......................................................................................................2-4
3.4 Directional Coupler.........................................................................................2-4
3.5 Antenna Switch...............................................................................................2-5
3.6 Harmonic Filter ...............................................................................................2-5
3.7 Power Control.................................................................................................2-5
4.0 VHF (136-174MHz) Frequency Synthesis ...........................................................2-6
4.1 Reference Oscillator.......................................................................................2-6
4.2 Fractional-N Synthesizer ................................................................................2-6
4.3 Voltage Controlled Oscillator (VCO) ...............................................................2-7
4.4 Synthesizer Operation....................................................................................2-8
5.0 VHF (136-174MHz) Transmitter Power Amplifier (PA) 45 W ....................2-9
5.1 Power Controlled Stage..................................................................................2-9
5.2 Pre-Driver Stage ...........................................................................................2-10
5.3 Driver Stage..................................................................................................2-10
5.4 Final Stage....................................................................................................2-10
5.5 Directional Coupler.......................................................................................2-10
5.6 Antenna Switch.............................................................................................2-11
5.7 Harmonic Filter .............................................................................................2-11
5.8 Power Control...............................................................................................2-11
iv
Chapter 3 TROUBLESHOOTING CHARTS
1.0 Troubleshooting Flow Chart for Receiver (Sheet 1 of 2) .....................................3-1
1.1 Troubleshooting Flow Chart for Receiver (Sheet 2 of 2) .....................................3-2
2.0 Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 3) .........................3-3
2.1 Troubleshooting Flow Chart for 25W Transmitter (Sheet 2 of 3) .........................3-4
2.2 Troubleshooting Flow Chart for 25W Transmitter (Sheet 3 of 3) .........................3-3
3.0 Troubleshooting Flow Chart for 45W Transmitter (Sheet 1 of 2) .........................3-4
3.1 Troubleshooting Flow Chart for 45W Transmitter (Sheet 2 of 2) .........................3-4
4.0 Troubleshooting Flow Chart for Synthesizer........................................................3-5
5.0 Troubleshooting Flow Chart for VCO...................................................................3-6
Chapter 4 VHF PCB/SCHEMATICS/PARTS LISTS
1.0 Allocation of Schematics and Circuit Boards .......................................................4-1
1.1 Controller Circuits ................................................................................................4-1
2.0 VHF 1-25W PCB 8486172B04 / Schematics.......................................................4-3
2.1 VHF 1-25W PCB 8486172B04 Parts List .........................................................4-10
3.0 VHF 1-25W PCB 8486172B06 / Schematics.....................................................4-13
3.1 VHF 1-25W PCB 8486172B06 Parts List ..........................................................4-20
4.0 VHF 1-25W PCB 8486172B07 / Schematics.....................................................4-23
4.1 VHF 1-25W PCB 8486172B07 Parts List ..........................................................4-27
5.0 VHF 1-25W PCB 8486172B08 / Schematics.....................................................4-31
5.1 VHF 1-25W PCB 8486172B08 Parts List ..........................................................4-38
6.0 VHF 25-45W PCB 8486140B12 / Schematics................................................... 4-41
6.1 VHF 25-45W PCB 8486140B12 Parts List ........................................................4-44
7.0 VHF 25-45W PCB 8486140B13 / Schematics................................................... 4-47
7.1 VHF 25-45W PCB 8486140B13 Parts List ........................................................4-49
8.0 VHF 25-45W PCB 8486140B15 / Schematics................................................... 4-52
8.1 VHF 25-45W PCB 8486140B15 Parts List ........................................................4-59
Chapter 1
MODEL CHART AND TECHNICAL SPECIFICATIONS
1.0 GM140/GM160 Model Chart
GM Series VHF 136-174 MHz
Model Description
MDM25KKC9AA1_E GM140, 136-174 MHz, 25-40W, 4 Ch
MDM25KKF9AA5_E GM160, 136-174 MHz, 25-40W, 128 Ch
MDM25KHC9AA1_E GM140, 136-174 MHz, 1-25W, 4 Ch
MDM25KHF9AA5_E GM160, 136-174 MHz, 1-25W, 128 Ch
Item Description
X X GCN6112_ Control Head GM140
X X GCN6114_ Control Head GM160
X IMUD6011_ Tanapa, GM140
X IMUD6011_ Tanapa, GM160
XIMUD6010_ Tanapa, GM140
X IMUD6010_ Tanapa, GM160
XXXXENBN4056_ Packaging, Waris Mobile Radio
XXXXGLN7324_ Low Profile Mounting Trunion
X X HKN9402_ 12V Power Cable, 25-45W
X X HKN4137_ 12V Power Cable, 1-25W
XXXXMDRMN4025_ Enhanced Compact Microphone
X X 6864110B86_ User Guide, GM140
X X 6864110B87_ User Guide, GM160
X = Indicates one of each is required
1-2 MODEL CHART AND TECHNICAL SPECIFICATIONS
2.0 GM340/GM360/GM380 Model Chart
GM Series VHF 136-174 MHz
Model Description
MDM25KHC9AN1_E GM340, 136-174 MHz, 1-25W, 6 Ch
MDM25KHF9AN5_E GM360, 136-174 MHz, 1-25W, 255 Ch
MDM25KHC9AN8_E GM380, 136-174 MHz, 1-25W, 255 Ch
MDM25KHA9AN0_E Databox, 136-174 MHz, 1-25W, 16 Ch
Item Description
XGCN6112_ Control Head GM340
X GCN6120_ Control Head GM360
XGCN6121_ Control Head GM380
X GCN6116_ Databox Radio Blank Head
XIMUD6013_S Field Replaceable Unit (Main Board) GM340
X IMUD6013_S Field Replaceable Unit (Main Board) GM360
XIMUD6024_S Field Replaceable Unit (Main Board) GM380
X IMUD6015_A S/T 136-174 MHz 1-25 SEL5
XXXXENBN4056_ Packaging, Waris Mobile
XXXXGLN7324_ Low Profile Mounting Trunnion
XXXXHKN4137_ 12V Power Cable 1-25W
X X X MDRMN4025_ Enhanced Compact Microphone
X6864110B80 User Guide GM340
X 6864110B81 User Guide, GM360
X6864110B82 User Guide, GM380
X = Indicates one of each is required
GM640/GM660/GM1280 Model Chart 1-3
3.0 GM640/GM660/GM1280 Model Chart
GM Series VHF 136-174 MHz
Model Description
MDM25KHC9CK1_E GM640, 136-174 MHz, 1-25W, 6 Ch
MDM25KHF9CK5_E GM660, 136-174 MHz, 1-25W, 255 Ch
MDM25KHN9CK8_E GM1280, 136-174 MHz, 1-25W, 255 Ch
MDM25KHA9CK7_E Databox, 136-174 MHz, 1-25W, 16 Ch
Item Description
XGCN6112_ Control Head GM640
X GCN6120_ Control Head GM660
XGCN6121_ Control Head GM1280
X GCN6116_ Databox Radio Blank Head
XIMUD6018_S Field Replaceable Unit (Main Board) GM640
X IMUD6018_S Field Replaceable Unit (Main Board) GM660
XIMUD6018_S Field Replaceable Unit (Main Board) GM1280
X IMUD6018_S S/T 136-174 MHz 1-25 SEL5
XXXXENBN4056_ Packaging, Waris Mobile Radio
XXXXGLN7324_ Low Profile Mounting Trunnion
XXXXHKN4137_ 12V Power Cable, 1-25W
X X X MDRMN4025_ Enhanced Compact Microphone
X6864110B83_ User Guide, GM640
X 6864110B84_ User Guide, GM660
X6864110B85_ User Guide, GM1280
X = Indicates one of each is required
1-4 MODEL CHART AND TECHNICAL SPECIFICATIONS
4.0 Technical Specifications
Data is specified for +25°C unless otherwise stated.
General Specifications
Channel Capacity
GM140
GM160
GM340
GM360
GM380
GM640
GM660
GM1280
Databox
4
128
6
255
255
6
255
255
16
Power Supply 13.2Vdc (10.8 - 15.6Vdc)
Dimensions: H x W x D (mm) Depth excluding knobs GM140/340/640
56mm x 176mm x 177mm (1 - 25W)
56mm x 176mm x 189mm (25 - 45W)
(add 8mm for Volume Knob)
Dimensions: H x W x D (mm) Depth excluding knobs GM160/360/660
59mm x 179mm x 186mm (1 - 25W)
59mm x 179mm x 198mm (25 - 45W)
(add 9mm for Volume Knob)
Dimensions: H x W x D (mm) Depth excluding knobs GM380/1280
188mm x 185mm x 72mm
(add 8mm for Volume Knob)
Dimensions: H x W x D (mm) Depth excluding knobs Databox
44mm x 168mm x 161mm
Weight GM140/340/640 1400gr
Weight GM160/360/660 1400gr
Weight GM380/1280 1500gr
Weight Databox 1220gr
Sealing: Withstands rain testing per
MIL STD 810 C/D /E and IP54
Shock and Vibration: Protection provided via impact
resistant housing exceeding MIL STD
810-C/D /E and TIA/EIA 603
Dust and Humidity: Protection provided via environment
resistant housing exceeding MIL STD
810 C/D /E and TIA/EIA 603
Technical Specifications 1-5
*Availability subject to the laws and regulations of individual countries.
Transmitter VHF
*Frequencies - Full Bandsplit VHF 136-174 MHz
Channel Spacing 12.5/20/25 kHz
Frequency Stability
(-30°C to +60°C, +25° Ref.) ±2.5 ppm
Power 1-25W / 25-45W
Modulation Limiting ±2.5 @ 12.5 kHz
±4.0 @ 20 kHz
±5.0 @ 25 kHz
FM Hum & Noise -40 dB @ 12.5kHz
-45 dB @ 20/25kHz
Conducted/Radiated Emission (ETS) -36 dBm <1 GHz
-30 dBm >1 GHz
Adjacent Channel Power -60 dB @ 12.5 kHz
-70 dB @ 25 kHz
Audio Response (300 - 3000Hz) +1 to -3 dB
Audio Distortion
@1000Hz, 60%
Rated Maximum Deviation <3% typical
Receiver VHF
*Frequencies - Full Bandsplit VHF 136-174 MHz
Channel Spacing 12.5/20/25 kHz
Sensitivity (12 dB SINAD) 0.30 µV (0.22 µV typical)
Intermodulation (ETS) >65 dB
Base Mode: >70dB
(1-25W model only)
Adjacent Channel Selectivity (ETS) 65 dB @ 12.5 kHz
75 dB @ 20 kHz
80 dB @ 25 kHz
Spurious Rejection (ETS) 75 dB @ 12.5 kHz
80 dB @ 20/25 kHz
Rated Audio 3W Internal
13W External
Audio Distortion @ Rated Audio <3% typical
Hum & Noise -40 dB @ 12.5 kHz
-45 dB @ 20/25 kHz
Audio Response (300 - 3000Hz @ 20/25kHz)
(300 - 2550Hz @12.5kHz) +1 to -3 dB
Conducted Spurious Emission (ETS) -57 dBm <1 GHz
-47 dBm >1 GHz
1-6 MODEL CHART AND TECHNICAL SPECIFICATIONS
Chapter 2
THEORY OF OPERATION
1.0 Introduction
This Chapter provides a detailed theory of operation for the VHF circuits in the radio. For details of
the theory of operation and trouble shooting for the the associated Controller circuits refer to the
Controller Section of this manual.
2.0 VHF (136-174MHz) Receiver
2.1 Receiver Front-End
The receiver is able to cover the VHF range from 136 to 174 MHz. It consists of four major blocks:
front-end bandpass filters and pre-amplifier, first mixer, high-IF, low-IF and receiver back-end. Two
varactor-tuned bandpass filters perform antenna signal pre-selection. A cross over quad diode mixer
converts the signal to the first IF of 44.85 MHz. High-side first injection is used.
Figure 2-1 VHF Receiver Block Diagram
Demodulator
1. Crystal
Filter
Mixer
Varactor
Tuned Filter
RF Amp
Varactor
Tuned Filter
Antenna
Control Voltage
from PCIC First LO
from FGU
Recovered Audio
RSSI
IF
Second LO
2. Crystal
Filter
455kHz Filter
(25kHz)
455kHz Filter
(25kHz)
455kHz Filter
(12.5kHz)
455kHz Filter
(12.5kHz)
Switch
Switch
Switch
Switch
Limiter
1. IF Amp
2. IF Amp
Filter Bank Selection
from Synthesizer IC
Pin Diode
Antenna
Switch
RF Jack
Harmonic
Filter
2-2 THEORY OF OPERATION
There are two 2-pole 44.85 MHz crystal filters in the high-IF section and 2 pairs of 455 kHz ceramic
filters in the low-IF section to provide the required adjacent channel selectivity. The correct pair of
ceramic filters for 12.5 or 25kHz channel spacing is selected via control line BWSELECT. The
second IF at 455 kHz is mixed, amplified and demodulated in the IF IC. The processing of the
demodulated audio signal is performed by an audio processing IC located in the controller section.
2.2 Front-End Band-Pass Filters & Pre-Amplifier
The received signal from the radio’s antenna connector is first routed through the harmonic filter and
antenna switch, which are part of the RF power amplifier circuitry, before being applied to the
receiver pre-selector filter (C3001, C3002, D3001 and associated components). The 2-pole pre-
selector filter tuned by the dual varactor diode D3001 pre-selects the incoming signal (RXIN) from
the antenna switch to reduce spurious effects to following stages. The tuning voltage (FECNTL_1)
ranging from 2 volts to 8 volts is controlled by pin 20 of PCIC (U3501) in the Transmitter section. A
dual hot carrier diode (D3003) limits any inband signal to 0 dBm to prevent damage to the pre-
amplifier.
The RF pre-amplifier is an SMD device (Q3001) with collector-base feedback to stabilize gain,
impedance, and intermodulation. Transistor Q3002 compares the voltage drop across resistor
R3002 with a fixed base voltage from divider R3011, R3000 and R3012, and adjusts the base
current of Q3001 as necessary to maintain its collector current constant at approximately 15-20 mA.
Operating voltage is from the regulated 9.3V supply (9V3). During transmit, 9.1 volts (K9V1) turns off
both transistors Q3002 and Q3001. This protects the RF pre-amplifier from excessive dissipation
during transmit mode. A switchable 3dB pad (R3022, R3024, R3016 and R3018) controlled via Line
FECNTL_2 and Q3021 stabilizes the output impedance and intermodulation performance.
A second 2-pole varactor tuned bandpass filter provides additional filtering of the amplified signal.
The dual varactor diode D3004 is controlled by the same signal FECNTL_1, which controls the pre-
selector filter.
2.3 First Mixer and High Intermediate Frequency (IF)
The signal coming from the front-end is converted to the high-IF frequency of 44.85 MHz using a
cross over quad diode mixer (D3031). Its ports are matched for incoming RF signal conversion to the
44.85 MHz IF using high side injection. The high-side injection signal (RXINJ) from the frequency
synthesizer circuitry has a level of approximately 13 dBm and is injected via matching transformer
T3002.
The mixer IF output signal (IF) from transformer T3001 pin 2 is fed to the first two pole crystal filter
FL3101. The filter output in turn is matched to the following IF amplifier.
The IF amplifier Q3101 is actively biased by a collector base feedback (R3101, R3106) to a current
drain of approximately 5 mA drawn from the voltage 5V. Its output impedance is matched to the
second two pole crystal filter FL3102. The signal is further amplified by a preamplifier (Q3102)
before going into pin 1 of IFIC (U3101).
A dual hot carrier diode (D3101) limits the filter output voltage swing to reduce overdrive effects at
RF input levels above -27 dBm.
2.4 Low Intermediate Frequency (IF) and Receiver Back End
The 44.85 MHz high-IF signal from the second IF amplifier feeds the IF IC (U3101) at pin1. Within
the IF IC, the 44.85 MHz high IF signal mixes with the 44.395 MHz second local oscillator (2nd LO)
to produce the low-IF signal at 455 kHz. The 2nd LO frequency is determined by crystal Y3101. The
VHF (136-174MHz) Transmitter Power Amplifier (PA) 25 W 2-3
low IF signal is amplified and filtered by an external pair of 455 kHz ceramic filters FL3112, FL3114
for 20/25 kHz channel spacing or FL3111, FL3113/F3115 for 12.5 kHz channel spacing. These pairs
are selectable via BWSELECT. The filtered output from the ceramic filters is applied to the limiter
input pin of the IF IC (pin 14).
The IF IC contains a quadrature detector using a ceramic phase-shift element (Y3102) to provide
audio detection. Internal amplification provides an audio output level of 120 mV rms (at 60%
deviation) from U3101 pin 8 (DISCAUDIO) which is fed to the ASFIC_CMP (U0221) pin 2 (part of
the Controller circuitry).
A received signal strength indicator (RSSI) signal is available at U3101 pin 5, having a dynamic
range of 70 dB. The RSSI signal is interpreted by the microprocessor (U0101 pin 63) and in addition
is available at accessory connector J0501-15.
3.0 VHF (136-174MHz) Transmitter Power Amplifier (PA) 25 W
The radio’s 25 W PA is a three stage amplifier used to amplify the output from the VCOBIC to the
radio transmit level. All three stages utilize LDMOS technology. The gain of the first stage (U3401)
and the second stage (Q3421) is adjustable, controlled by pin 4 of PCIC (U3501) via U3402-1 and
U3402-2. It is followed by an LDMOS final stage (Q3441).
Figure 2-1 VHF Transmitter Block Diagram
Devices U3401, Q3421 and Q3441 are surface mounted. A pressure pad between board and the
radio's cover provides good thermal contact between the devices and the chassis.
3.1 First Power Controlled Stage
The first stage (U3401) is a 20dB gain integrated circuit containing two LDMOS FET amplifier
stages. It amplifies the RF signal from the VCO (TXINJ). The output power of stage U3401 is
controlled by a DC voltage applied to pin 1 from the op-amp U3402-1, pin 1. The control voltage
simultaneously varies the bias of two FET stages within U3401. This biasing point determines the
overall gain of U3401 and therefore its output drive level to Q3421, which in turn controls the output
power of the PA.
PCIC
Pin Diode
Antenna
Switch RF Jack
Antenna
Harmonic
Filter
Power
Sense
PA-Final
Stage
From VCO
Controlled
Stage
Controlvoltage
Bias 2
To Microprocessor
Temperature
Sense
SPI BUS
ASFIC_CMP
PA
PWR
SET
To Microprocessor
PA
Driver
2-4 THEORY OF OPERATION
Op-amp U3402-1 monitors the drain current of U3401 via resistor R3444 and adjusts the bias
voltage of U3401 so that the current remains constant. The PCIC (U3501) provides a DC output
voltage at pin 4 (INT) which sets the reference voltage of the current control loop. A raising power
output causes the DC voltage from the PCIC to fall, and U3402-1 adjusts the bias voltage for a lower
drain current to lower the gain of the stage.
In receive mode the DC voltage from PCIC pin 23 (RX) turns on Q3442, which in turn switches off
the biasing voltage to U3401.
Switch S3440 is a pressure pad with a conductive strip which connects two conductive areas on the
board when the radio's cover is properly screwed to the chassis. When the cover is removed, S3440
opens and the resulting high voltage level at the inverting inputs of the current control op-amps
U3402-1 & 2 switches off the biasing of U3401 and Q3421. This prevents transmitter key up while
the devices do not have proper thermal contact to the chassis.
3.2 Power Controlled Driver Stage
The next stage is an LDMOS device (Q3421) providing a gain of 12dB. This device requires a
positive gate bias and a quiescent current flow for proper operation. The bias is set during transmit
mode by the drain current control op-amp U3402-2, and fed to the gate of Q3421 via the resistive
network R3429, R3418, R3415 and R3416.
Op-amp U3402-2 monitors the drain current of U3421 via resistors R3424-27 and adjusts the bias
voltage of Q3421 so that the current remains constant. The PCIC (U3501) provides a DC output
voltage at pin 4 (INT) which sets the reference voltage of the current control loop. A raising power
output causes the DC voltage from the PCIC to fall, and U3402-2 adjusts the bias voltage for a lower
drain current to lower the gain of the stage.
In receive mode the DC voltage from PCIC pin 23 (RX) turns on Q3422, which in turn switches off
the biasing voltage to Q3421.
3.3 Final Stage
The final stage is an LDMOS device (Q3441) providing a gain of 12dB. This device also requires a
positive gate bias and a quiescent current flow for proper operation. The voltage of the line
MOSBIAS_2 is set in transmit mode by the ASFIC and fed to the gate of Q3441 via the resistive
network R3404, R3406, and R3431-5. This bias voltage is tuned in the factory. If the transistor is
replaced, the bias voltage must be tuned using the Customer Programming Software (CPS). Care
must be taken not to damage the device by exceeding the maximum allowed bias voltage. In receive
mode U3402-2 pulls the bias voltage to low via D3401. The device’s drain current is drawn directly
from the radio’s DC supply voltage input, PASUPVLTG, via L3436 and L3437.
A matching network consisting of C3441-49, L3443, and two striplines, transforms the impedance to
50 ohms and feeds the directional coupler.
3.4 Directional Coupler
The directional coupler is a microstrip printed circuit, which couples a small amount of the forward
power delivered by Q3441. The coupled signal is rectified by D3451. The DC voltage is proportional
to the RF output power and feeds the RFIN port of the PCIC (U3501 pin 1). The PCIC controls the
gain of stage U3401 and Q3421 as necessary to hold this voltage constant, thus ensuring the
forward power out of the radio to be held to a constant value.
VHF (136-174MHz) Transmitter Power Amplifier (PA) 25 W 2-5
3.5 Antenna Switch
The antenna switch consists of two PIN diodes, D3471 and D3472. In the receive mode, both diodes
are off. Signals applied at the antenna jack J3401 are routed, via the harmonic filter, through
network L3472, C3474 and C3475, to the receiver input. In the transmit mode, K9V1 turns on Q3471
which enables current sink Q3472, set to 96 mA by R3473 and VR3471. This completes a DC path
from PASUPVLTG, through L3437, D3471, L3472, D3472, L3471, R3474 and the current sink, to
ground. Both diodes are forward biased into conduction. The transmitter RF from the directional
coupler is routed via D3471 to the harmonic filter and antenna jack. D3472 also conducts, shunting
RF power and preventing it from reaching the receiver port (RXIN). L3472 is selected to appear as a
lambda / 4 wave transmission line, making the short circuit presented by D3472 appear as an open
circuit at the junction of D3472 and the receiver path.
3.6 Harmonic Filter
Components L3491-L3493 and L3472, C3491-C3499 form a Chebychev low-pass filter to attenuate
harmonic energy of the transmitter to specifications level. R3491 is used to drain electrostatic
charge that might otherwise build up on the antenna. The harmonic filter also prevents high level RF
signals above the receiver passband from reaching the receiver circuits, improving spurious
response rejection.
3.7 Power Control
The transmitter uses the Power Control IC (PCIC, U3501) to control the power output of the radio. A
portion of the forward RF power from the transmitter is sampled by the directional coupler and
rectified, to provide a DC voltage to the RFIN port of the PCIC (pin 1) which is proportional to the
sampled RF power.
The ASFIC (U0221) has internal digital to analog converters (DACs) which provide a reference
voltage of the control loop to the PCIC via R3505. The reference voltage level is programmable
through the SPI line of the PCIC. This reference voltage is proportional to the desired power setting
of the transmitter, and is factory programmed at several points across the frequency range of the
transmitter to offset frequency response variations of the transmitter’s power detector circuit.
The PCIC provides a DC output voltage at pin 4 (INT) which sets the drain current of the first
(U3401) and second (Q3421) transmitter stage via current control op-amps U3402-1 and U3402-2.
This adjusts the transmitter power output to the intended value. Variations in forward transmitter
power cause the DC voltage at pin 1 to change, and the PCIC adjusts the control voltage above or
below its nominal value to raise or lower output power. Capacitors C3502-4, in conjunction with
resistors and integrators within the PCIC, control the transmitter power-rise (key-up) and power-
decay (de-key) characteristic to minimize splatter into adjacent channels. U3502 is a temperature-
sensing device, which monitors the circuit board temperature in the vicinity of the transmitter driver
and final devices, and provides a dc voltage to the PCIC (TEMP, pin 30) proportional to temperature.
If the DC voltage produced exceeds the set threshold in the PCIC, the transmitter output power will
be reduced so as to reduce the transmitter temperature.
2-6 THEORY OF OPERATION
4.0 VHF (136-174MHz) Frequency Synthesis
The frequency synthesizer subsystem consists of the reference oscillator (Y3261 or Y3263), the
Low Voltage Fractional-N synthesizer (LVFRAC-N, U3201), and the voltage-controlled oscillators
and buffer amplifiers (U3301, Q3301-2 and associated circuitry).
4.1 Reference Oscillator
The reference oscillator (Y3263) contains a temperature compensated crystal oscillator with a
frequency of 16.8 MHz. An analog to digital (A/D) converter internal to U3201 (LVFRAC-N) and
controlled by the microprocessor via serial interface (SRL) sets the voltage at the warp output of
U3201 (pin 25) to set the frequency of the oscillator. The output of the oscillator (U3263 pin 3) is
applied to pin 23 (XTAL1) of U3201 via R3263 and C3235.
In applications were less frequency stability is required, the oscillator inside U3201 is used along
with an external crystal Y3261, varactor diode D3261, C3261, C3262 and R3262. In this case,
Y3263, R3263, C3235 and C3251 are not used. When Y3263 is used, Y3261, D3261, C3261,
C3262 and R3262 are not used, and C3263 is increased to 0.1 uF.
4.2 Fractional-N Synthesizer
The LVFRAC-N synthesizer IC (U3201) consists of a pre-scaler, a programmable loop divider,
control divider logic, a phase detector, a charge pump, an A/D converter for low frequency digital
modulation, a balance attenuator to balance the high frequency analog modulation and low
frequency digital modulation, a 13V positive voltage multiplier, a serial interface for control, and
finally a super filter for the regulated 5 volts.
Figure 2-1 VHF Synthesizer Block Diagram
DATA
CLK
CEX
MODIN
VCC, DC5V
XTAL1
XTAL2
WARP
PREIN
VCP
REFERENCE
OSCILLATOR
VOLTAGE
MULTIPLIER
DATA (U0101 PIN 100)
CLOCK (U0101 PIN 1)
CSX (U0101 PIN 2)
MOD IN (U0221 PIN 40)
+5V (U3211 PIN 1)
7
8
9
10
13, 30
23
24
25
32
47
VMULT2 VMULT1
BIAS1
SFOUT
AUX3
AUX4
IADAPT
IOUT
GND
FREFOUT
LOCK 4
19
6, 22, 33, 44
43
45
3
2
28
14 15
40
FILTERED 5V
STEERING
LOCK (U0101 PIN 56)
PRESCALER IN
FREF (U0221 PIN 34)
39
BIAS2
41
48
5, 20, 34, 36
+5V (U3211 PIN 1)
AUX1
VDD, DC5V MODOUT
U3201
LOW VOLTAGE
FRACTIONAL-N
SYNTHESIZER
AUX2
BW SELECT
TX RF INJECTION
(1ST STAGE OF PA)
LO RF INJECTION
VOLTAGE
CONTROLLED
OSCILLATOR
LINE
2-POLE
LOOP
FILTER
1
TRB
TO IF SECTION
VHF (136-174MHz) Frequency Synthesis 2-7
A voltage of 5V applied to the super filter input (U3201 pin 30) supplies an output voltage of 4.5 VDC
(VSF) at pin 28. It supplies the VCO, VCO modulation bias circuit (via R3363) and the synthesizer
charge pump resistor network (R3251, R3252). The synthesizer supply voltage is provided by the
5V regulator U3211.
In order to generate a high voltage to supply the phase detector (charge pump) output stage at pin
VCP (U3201-47), a voltage of 13 VDC is being generated by the positive voltage multiplier circuitry
(D3201, C3202, C3203). This voltage multiplier is basically a diode capacitor network driven by two
(1.05MHz) 180 degrees out of phase signals (U3201-14 and -15).
Output LOCK (U3201-4) provides information about the lock status of the synthesizer loop. A high
level at this output indicates a stable loop. IC U3201 provides the 16.8 MHz reference frequency at
pin 19.
The serial interface (SRL) is connected to the microprocessor via the data line DATA (U3201-7),
clock line CLK (U3201-8), and chip enable line CSX (U3201-9).
4.3 Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator (VCO) consists of the VCO/Buffer IC (VCOBIC, U3301), the TX
and RX tank circuits, the external RX buffer stages, and the modulation circuitry.
Figure 2-1 VHF VCO Block Diagram
Presc
RX
TX
Matching
Network Low Pass
Filter
Attenuator
Pin8
Pin14
Pin10
(U3211 Pin1)
VCC Buffers
TX RF Injection
U3201 Pin 32
AUX3 (U3201 Pin2)
Prescaler Out
Pin 12Pin 19
Pin 20
TX/RX/BS
Switching Network
U3301
VCOBIC
Rx
Active Bias
Tx
Active Bias
Pin2
Rx-I adjust
Pin1
Tx-I adjust
Pins 9,11,17
Pin18
Vsens
Circuit
Pin15
Pin16
RX VCO
Circuit
TX VCO
Circuit
RX Tank
TX Tank
Pin7
Vcc-Superfilter
Collector/RF in
Pin4
Pin5
Pin6
RX
TX
(U3201 Pin28)
Rx-SW
Tx-SW
Vcc-Logic
(U3211 Pin1)
Steer Line
Voltage
(VCTRL)
Pin13
Pin3
TRB IN
LO RF INJECTION
Q3304
Q3301
2-8 THEORY OF OPERATION
The VCOBIC together with the Fractional-N synthesizer (U3201) generates the required frequencies
in both the transmit and receive modes. The TRB line (U3301 pin 19) determines which tank circuits
and internal buffers are to be enabled. A high level on TRB enables the TX tank and TX output (pin
10), and a low enables the RX tank and RX output (pin 8). A sample of the signal from the enabled
RF output is routed from U3301 pin 12 (PRESC_OUT), via a low pass filter, to pin 32 of U3201
(PREIN).
A steering line voltage (VCTRL) between 2.5V and 11V at varactor diode D3361 will tune the full TX
frequency range (TXINJ) from 136 MHz to 174 MHz, and at varactor diode D3341 will tune the full
RX frequency range (RXINJ) from 181 MHz to 219 MHz. The RX tank circuit uses a Hartley
configuration for wider bandwidth. For the RX tank circuit, an external transistor Q3304 is used for
better side-band noise.
The external RX buffers (Q3301 and Q3302) are enabled by a high at U3301 pin 7 (RX_SWITCH)
via transistor switch Q3303. In the TX mode, the modulation signal (VCOMOD) from the LVFRAC-N
synthesizer IC (U3201 pin 41) is applied to varactor diode D3362, which modulates the TX VCO
frequency via capacitor C3362. Varactor D3362 is biased for linearity from VSF.
4.4 Synthesizer Operation
The complete synthesizer subsystem consists of the low voltage FRAC-N (LVFRACN), the
reference oscillator (a crystal oscillator with temperature compensation), charge pump circuitry, loop
filter circuitry and a DC supply. The output signal PRESC from the VCOBIC (U3301 pin 12) is fed to
U3201 pin 32 (PREIN) via a low pass filter (C3318, L3318 and C3226) which attenuates harmonics
and provides the correct level to close the synthesizer loop.
The pre-scaler in the synthesizer (U3201) is a dual modulus type with selectable divider ratios. The
divider ratio of the pre-scaler is controlled by the loop divider, which in turn receives its inputs via the
SRL. The output of the pre-scaler is applied to the loop divider. The output of the loop divider is
connected to the phase detector, which compares the loop divider´s output signal with the reference
signal. The reference signal is generated by dividing down the signal of the reference oscillator
(Y3261 or Y3263).
The output signal of the phase detector is a pulsed DC signal which is routed to the charge pump.
The charge pump outputs a current at U3201 pin 43 (IOUT). The loop filter (which consists of
R3221-R3223 and C3221-C3224) transforms this current into a voltage that is applied to the
varactor diodes (D3361 for transmit, D3341 for receive) to alter the output frequency of the
appropriate VCO. The current can be set to a value fixed within the LVFRAC-N IC, or to a value
determined by the currents flowing into BIAS 1 (U3201-40) or BIAS 2 (U3201-39). The currents are
set by the value of R3251 and R3252 respectively. The selection of the three different bias sources is
done by software programming.
To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer, the
magnitude of the loop current is increased by enabling the IADAPT pin (U3201-45) for a certain
software programmable time (adapt mode). The adapt mode timer is started by a low to high
transient of the CSX line. When the synthesizer is within the lock range, the current is determined
only by the resistors connected to BIAS 1 and BIAS 2, or by the internal current source. A settled
synthesizer loop is indicated by a high level signal at U3201-4 (LOCK).
The LOCK signal is routed to one of the µP´s ADC inputs (U0101-56). From the measured voltage,
the µP determines whether LOCK is active.
In order to modulate the PLL, the two spot modulation method is utilized. Via U3201 pin 10 (MODIN),
the audio signal is applied to both the A/D converter (low frequency path) as well as the balance
attenuator (high frequency path). The A/D converter changes the low frequency analog modulating
VHF (136-174MHz) Transmitter Power Amplifier (PA) 45 W 2-9
signal into a digital code that is applied to the loop divider, thereby causing the carrier to deviate. The
balance attenuator is used to adjust the VCO’s deviation sensitivity to high frequency modulating
signals. The output of the balance attenuator is present at the MODOUT port (U3201-41) and
connected to the VCO modulation diode D3362 via R3364.
5.0 VHF (136-174MHz) Transmitter Power Amplifier (PA) 45 W
The radio’s 45 W PA is a four stage amplifier used to amplify the output from the VCOBIC to the
radio transmit level. The line-up consists of three stages which utilize LDMOS technology, followed
by a final stage using a bipolar device. The gain of the first stage (U3401) is adjustable, controlled by
pin 4 of PCIC (U3501) via Q3501 and Q3502 (VCONT). It is followed by an LDMOS pre-driver stage
(Q3421), an LDMOS driver stage (Q3431) and a bipolar final stage (Q3441).
Figure 2-1 VHF Transmitter Block Diagram
Devices U3401 and Q3421 are surface mounted. The remaining devices are directly attached to the
heat sink.
5.1 Power Controlled Stage
The first stage (U3401) is a 20dB gain integrated circuit containing two LDMOS FET amplifier
stages. It amplifies the RF signal from the VCO (TXINJ). The output power of stage U3401 is
controlled by a DC voltage applied to pin 1 from the power control circuit (U3501 pin 4, with
transistors Q3501 and Q3502 providing current gain and level-shifting). The control voltage
simultaneously varies the bias of two FET stages within U3401. This biasing point determines the
overall gain of U3401 and therefore its output drive level to Q3421, which in turn controls the output
power of the PA.
In receive mode the voltage control line is at ground level and turns off Q3501-2, which in turn
switches off the biasing voltage to U3401.
Antenna
To Microprocessor
PCIC
Pin Diode
Antenna
Switch RF Jack
Harmonic
Filter
Power
Sense
PA-Final
Stage
PA
Driver
From VCO
Controlled
Stage
Vcontrol
Bias 1
Bias 2
To Microprocessor
Temperature
Sense
SPI BUS
ASFIC_CMP
PA
PWR
SET
To Microprocessor
Pre
Driver
2-10 THEORY OF OPERATION
5.2 Pre-Driver Stage
The next stage is an LDMOS device (Q3421) providing a gain of 13 dB. This device requires a
positive gate bias and a quiescent current flow for proper operation. The voltage of the line
PCIC_MOSBIAS_1 is set during transmit mode by the PCIC pin 24, and fed to the gate of Q3421
via the resistive network R3410, R3415, and R3416. The bias voltage is tuned in the factory.
5.3 Driver Stage
The following stage is an enhancement-mode N-Channel MOSFET device (Q3431) providing a gain
of 10dB. This device also requires a positive gate bias and a quiescent current flow for proper
operation. The voltage of the line MOSBIAS_2 is set in transmit mode by the ASFIC and fed to the
gate of Q3431 via the resistive network R3404, R3406, and R3431-5. This bias voltage is also tuned
in the factory. If the transistor is replaced, the bias voltage must be tuned using the Customer
Programming Software (CPS). Care must be taken not to damage the device by exceeding the
maximum allowed bias voltage. The device’s drain current is drawn directly from the radio’s DC supply
voltage input, PASUPVLTG, via L3431 and L3432.
5.4 Final Stage
The final stage uses the bipolar device Q3441. The device’s collector current is also drawn from the
radio’s DC supply voltage input. To maintain class C operation, the base is DC-grounded by a series
inductor (L3441) and a bead (L3442). A matching network consisting of C3446-52, C3467, L3444-5,
and two striplines, transforms the impedance to approximately 50 ohms and feeds the directional
coupler.
5.5 Directional Coupler
The directional coupler is a microstrip printed circuit, which couples a small amount of the forward
and reflected power delivered by Q3441. The coupled signals are rectified by D3451-2 and
combined by R3463-4. The resulting DC voltage is proportional to RF output power and feeds the
RFIN port of the PCIC (U3501 pin 1). The PCIC controls the gain of stage U3401 as necessary to
hold this voltage constant, thus ensuring the forward power out of the radio to be held to a constant
value.
An abnormally high reflected power level, such as may be caused by a damaged antenna, also
causes the DC voltage applied to the PCIC to increase, and this will cause a reduction in the gain of
U3401, reducing transmitter output power to prevent damage to the final device due to an improper
load.
VHF (136-174MHz) Transmitter Power Amplifier (PA) 45 W 2-11
5.6 Antenna Switch
The antenna switch consists of two PIN diodes, D3471 and D3472. In the receive mode, both diodes
are off. Signals applied at the antenna jack J3401 are routed, via the harmonic filter, through
network L3472, C3474 and C3475, to the receiver input. In the transmit mode, K9V1 turns on Q3471
which enables current sink Q3472, set to 96 mA by R3473 and VR3471. This completes a DC path
from PASUPVLTG, through L3473, D3471, L3477, L3472, D3472, L3471, R3474 and the current
sink, to ground. Both diodes are forward biased into conduction. The transmitter RF from the
directional coupler is routed via D3471 to the harmonic filter and antenna jack. D3472 also
conducts, shunting RF power and preventing it from reaching the receiver port (RXIN). L3472 is
selected to appear as a broadband lambda/4 wave transmission line, making the short circuit
presented by D3472 appear as an open circuit at the junction of D3472 and the receiver path.
5.7 Harmonic Filter
Components L3491-L3494 and C3489-C3498 form a nine-pole Chebychev low-pass filter to
attenuate harmonic energy of the transmitter to specifications level. R3490 is used to drain
electrostatic charge that might otherwise build up on the antenna. The harmonic filter also prevents
high level RF signals above the receiver passband from reaching the receiver circuits, improving
spurious response rejection.
5.8 Power Control
The transmitter uses the Power Control IC (PCIC, U3501) to control the power output of the radio. A
portion of the forward and reflected RF power from the transmitter is sampled by the directional
coupler, rectified and summed, to provide a DC voltage to the RFIN port of the PCIC (pin 1) which is
proportional to the sampled RF power.
The ASFIC contains a digital to analog converter (DAC) which provides a reference voltage of the
control loop to the PCIC via R3517. The reference voltage level is programmable through the SPI line
of the PCIC. This reference voltage is proportional to the desired power setting of the transmitter, and
is factory programmed at several points across the frequency range of the transmitter to offset
frequency response variations of the transmitter’s power detector circuitry.
The PCIC provides a DC output voltage at pin 4 (INT) which is amplified and shifted in DC level by
stages Q3501 and Q3502. The 0 to 4 volt DC range at pin 4 of U3501 is translated to a 0 to 8.5 volt
DC range at the output of Q3501, and applied as VCONT to the power-adjust input pin of the first
transmitter stage U3401. This adjusts the transmitter power output to the intended value. Variations
in forward or reflected transmitter power cause the DC voltage at pin 1 to change, and the PCIC
adjusts the control voltage above or below its nominal value to raise or lower output power.
Capacitors C3502-4, in conjunction with resistors and integrators within the PCIC, control the
transmitter power-rise (key-up) and power-decay (de-key) characteristic to minimize splatter into
adjacent channels.
U3502 is a temperature-sensing device, which monitors the circuit board temperature in the vicinity
of the transmitter driver and final devices, and provides a dc voltage to the PCIC (TEMP, pin 29)
proportional to temperature. If the DC voltage produced exceeds the set threshold in the PCIC, the
transmitter output power will be reduced so as to reduce the transmitter temperature.
2-12 THEORY OF OPERATION
Chapter 3
TROUBLESHOOTING CHARTS
1.0 Troubleshooting Flow Chart for Receiver (Sheet 1 of 2)
Bad SINAD
Bad 20dB Quieting
No Recovered Audio
START
Audio at
pin 8 of
U3101 ?
Check Controller
(in the case of no audio)
OR ELSE go to “B”
Yes
No
Spray or inject 44.85MHz
into XTAL Filter FL3101
Audio heard ?
BYes
No
Check 2nd LO
(44.395MHz) at C3135
LO present ?
BYes
Check voltages on
U3101
Biasing OK ?
No
No
A
Yes
Check Q3102 bias
for faults
Replace Q3102
Go to B
Yes
No
Check circuitry
around U3101.
Replace
U3101 if defect
Check circuitry around Y3101 Re-
place Y3101 if defect
Voltages
OK?
3-2 TROUBLESHOOTING CHARTS
1.1 Troubleshooting Flow Chart for Receiver (Sheet 2 of 2)
IF Signal at
C3035?
No
RF Signal at
T3001?
RF Signal at
C3012?
No
RF Signal at
C3008?
No
RF Signal at
C3474?
No or
Check Harmonic Filter
J3401 and
Antenna Switch
D3471,D3472,L3472
Check filter between C3474
& C3008. Check tuning
voltage at R3019
Inject RF into J3401
Is tuning
voltage OK?
No
Yes
Check RF amp
(Q3001) Stage
Check filter between
C3012 & T3001
Yes
Check T3001, T3002,
D3031, R3030-R3034,
L3032, C3034 and C3035
Yes
1st
LO level OK?
Locked?
Yes
Check FGU
Yes
Trace IF signal from
C3035 to Q3101.
Check for bad XTAL
filter
No
Yes
IF signal at Q3102
collector?
Before replacing
U3101, check
U3101 voltages
Yes
Check for 5VDC
Is 9V3 present?
Check Supply Voltage
circuitry. Check Q0681,
U3211 and U0641
No
No
No
Check U3501
Check varactor filter
No
Yes
Yes
Yes
A
A
B
weak RF
Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 3) 3-3
2.0 Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 3)
Current
increase
when keyed?
NO
YES
START
Check if Pressure Pad closes S3440
Check Components between
Q3441 and RF Output,
Antenna Switch
D3471,D3472,Q3472
>500mA & <4A
>4A
<500mA
Check PA Stages
Control
Voltage at
TP3402
>1V
Short TP3403 to
Ground
NO
YES
Voltage at
TP3402
rises?
Check PA Stages NO
YES
PCIC U3501
Pin 14 9.3V
DC?
Check 9.3 V Regulator
U0641
NO
YES
PCIC U3501
Pin 16 >4V
DC
Replace PCIC U3501
NO
YES
TP3404
9.1V DC
If U3201 Pin 2 is high,
replace PCIC
U3501,otherwise
check controller and
FGU
YES
NO
TP3403
>0.5V DC?
Replace PCIC U3501
Check Forward Power
Sense Circuit (D3451)
Check Forward Power
Sense Circuit (D3451)
NO
YES
PCIC U3501
Pin 5 > 1V
DC?
Check Power Setting,
Tuning & Components
between PCIC Pin 5
and ASFIC (U0221)
Pin 4 before replacing
ASFIC
No or too low Power when keyed
3-4 TROUBLESHOOTING CHARTS
2.1 Troubleshooting Flow Chart for 25W Transmitter (Sheet 2 of 3)
Check PA Stages
No or too low Power when keyed
Measure DC Voltage at Pin 2 & 3 of U3401
>6
YES
DC Voltage
at U3501
Pin 23 =0?
2-6
DC Voltage
at U3402-1
Pin 1?
YES
Pin 2 Voltage
0.62 *
Voltage at
Pin 1?
If U3201 Pin 2 is high,
replace PCIC
NO Replace U3401
YES
NO DC
Voltage at
U3402-1 Pin
3 = 8.8V?
Check S3440,
R3442 and R3443
YES
Pin 3 Voltage
0.51 *
Voltage at
Pin 1?
NO Replace U3401
<2V DC Voltage at
U3402-2 Pin
7?
>6V
Check Components
between U3402-2 Pin7
and Q3421. Check
Resistive Network at
Pins 5 & 6 before repla-
cing Q3421
YES
DC Voltage at
U3402-2 Pin
5 <8.8V?
Check Components bet-
ween U3402-2 Pin7 and
Q3421. Check Resistive
Network at Pins 5 & 6
before replacing Q3421
NO
Check Q3422
NO
Check Final PA Stage
2-6V
<2V Check Resistive Net-
work at Pins 2 & 3 of
U3402-1 before repla-
cing U3401
Check Q3442 and
Resistive Network at
U3402-1 Pin 3
before replacing
U3401
Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 3) 3-5
2.2 Troubleshooting Flow Chart for 25W Transmitter (Sheet 3 of 3)
Check Final PA Stage
NO
0V
1-4V
Bias 2 DC
Voltage at
TP3406?
YES
RF Voltage
at TP3401
>100mV?
YES
RF Voltage
U3401 Pin 6
>3V?
Supply
Replace Q3441
Check FGU (U3301)
NO Check Components
between TP3401 &
C3417
NO
YES ASFIC
U0221 Pin 6
1-4V DC?
Check Bias Tuning
before replacing ASFIC
U0221
Check Components
between ASFIC and
Q3441 before repla-
cing Q3441
YES
RF Voltage
Q3421 Gate
>1V?
NO Check Components
between C3417 &
Q3421
YES
RF Voltage
Q3441 Gate
>4V?
NO Check Components
between Q3421 &
Q3441
Check Components
between Q3441 &
Antenna Connector
Voltage
3-6 TROUBLESHOOTING CHARTS
3.0 Troubleshooting Flow Chart for 45W Transmitter (Sheet 1 of 2)
Current in-
crease when
keyed?
NO
YES
START
No or too low Power when keyed
Check Components between
Q3441 and RF Output, Antenna
Switch D3471,D3472
>500mA & <5A
>5A
<500mA
Check PA Stages
Control
Voltage at
TP3402
>1V
>1V
<1V Check
Voltage at
PCIC U3501
Pin 4
Check Components
between TP3402 and
U3501 Pin 4
Short TP3403
to Ground
NO
YES
Voltage at
TP3402 ris-
es?
Check PA Stages NO
YES
PCIC U3501
Pin 15 9.3V
DC?
Check 9.3 V Regulator
U0641
NO
YES
PCIC U3501
Pin 16 >4V
DC
Replace PCIC
U3501
NO
YES
TP3404
9.1V DC
If U3201 Pin 3 is high,
replace PCIC
U3501,otherwise
check controller and
FGU
YES NO
TP3403
>0.5V DC?
Replace PCIC U3501 Check Forward & Reverse
Power Sense Circuitry
(D3451 & D3452)
Check Forward & Reverse
Power Sense Circuitry
(D3451 & D3452)
NO
YES
PCIC U3501
Pin 5 > 1V
DC?
Check Power Setting,
Tuning & Components
between PCIC Pin 5
and ASFIC (U0221)
Pin 4 before replacing
ASFIC
Troubleshooting Flow Chart for 45W Transmitter (Sheet 1 of 2) 3-7
3.1 Troubleshooting Flow Chart for Transmitter (Sheet 2 of 2)
Pin 2
Voltage 0.62
* Voltage at
Pin 1?
NO
YES
Check PA Stages
No or too low Power when keyed
NO
YES
Replace U3401
Pin 3
Voltage 0.51
* Voltage at
Pin 1?
2-4V
Supply
0V Bias 1 DC
Voltage at
TP3406?
NO
YES PCIC U3501
Pin 24 2-4V
DC?
Check Bias Tuning be-
fore replacing
PCIC U3501
Check Voltage at Pin 2 & 3 of U3401
Replace U3401
Replace Q3421
NO
0V
1-4V
Bias 2 DC
Voltage at
TP3407?
YES
RF Voltage
at TP3401
>100mV?
YES
RF Voltage
U3401 Pin 6
>3V?
Replace
Q3421
Supply
Replace Q3431
Check FGU (U3301)
NO Check Components
between TP3401 &
C3417
NO
YES ASFIC
U0221 Pin 6
1-4V DC?
Check Bias Tuning be-
fore replacing
ASFIC U0221
Check Components
between ASFIC and
Q3431 before re-
placing Q3431
YES
RF Voltage
Q3421 Gate
>1V?
NO Check Components
between C3417 &
Q3421
YES RF Voltage
Q3431 Gate
>4V?
NO Check Components
between Q3421 &
Q3431
YES
RF Voltage
Q3441 Base
>5V?
Check Components
between Q3431 &
Q3441
NO
Check Components
between Q3441 & An-
tenna Connector
Voltage
Voltage
3-8 TROUBLESHOOTING CHARTS
4.0 Troubleshooting Flow Chart for Synthesizer
+5V at
U3201 Pin’s
13 & 30?
5V
at pin 6 of
D3201
Is information
from µP U0101
correct?
Is U3201
Pin 47
= 13VDC ?
Is U3301 Pin 19
<40 mVDC in RX &
>4.5 VDC in TX?
(at VCO section)
Start
Visual
check of the
Board OK?
Correct
Problem
Check 5V
Regulator
U3211
Is 16.8MHz
Signal at
U3201 Pin
19?
Check
Y3261, Y3263 and
associated Parts
Are signals
at Pin’s 14 &
15 of U3201?
Check
R3201
Check C3319
Is U3201 pin 2
>4.5 VDC in Tx &
<40 mVDC in Rx
Replace
U3201
Remove
Shorts
Is there a short
between Pin 47 and
Pins 14 & 15 of
U3201?
Replace or resolder
necessary components
Is RF level at
U3201 Pin 32
-12 < x <-25
dBm?
Are
R3221,
R3222, R3223,
C3221, C3222,
& C3224
OK?
Replace
U3201
If R3227, C3226 & C3227
are OK, then see VCO
troubleshooting chart
Are Waveforms
at Pins 14 & 15
triangular?
Do Pins
7,8 & 9 of
U3201 toggle
when channel is
changed?
Check programming
lines between U0101
and U3201 Pins 7,8 & 9
Replace
U3201
Check µP U0101
Troubleshooting
Chart
No
Yes
No
Yes
No
Yes
No
No
No
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Yes
No
No
No
No
Yes
No
Yes
Yes
Check D3201,
C3202, C3203,
C3205 & C3206
5V at
U3201 pins 5,
20, 34 & 36
Check 5V
Regulator
U3211, R3211
Is
16.8MHz
signal at
U3201 pin
23?
Replace
U3201
Yes
No
No
Yes
No
Yes
Troubleshooting Flow Chart for VCO 3-9
5.0 Troubleshooting Flow Chart for VCO
Are Q3301
Base at 0.7V
Collector at 4.5V
Emitter at 110mV
Are Q3304
Base at 2.4V
Collector at 4.5V
Emitter at 1.7V
Are U3301 Pins
13 at 4.4V
15 at 1.1V
10 at 4.5V
16 at 1.9V
Low or no RF Signal
at TP3001
Visual check
of board
OK?
35mV DC at
U3301 Pin 19
NO
YES
at base of Q3301
NO
NO
NO
NO
NO
YES
YES
YES
YES
YES
Low or no RF Signal
at input to PA
5V DC at U3301
Pin 14&18 OK ?
4.8V DC at
U3301 Pin 19
Is RF available
at TP3401
YES
YES
YES
YES
YES
NO
NO
NO
NO
NO
Audio =180mVRMS
at “-” side of
D3362
2.5VDC
at D3362
If C3362 and R3363 are OK,
then replace D3362
Replace R3363
Replace R3364
NO
NO
YES
YES
If R3402 and
C3315 are OK,
replace U3301
TX VCO
RX VCO
Correct
Problem
Visual check
of board
OK?
Make sure U3211 is working
correctly and runner
between U3211 Pin 1 and
U3301 Pin 14 & 18 is OK
Check runner
between U3201 Pin 2
and U3301 Pin 19
Is RF available If all parts from U3301 Pin 8
to Base of Q3301 are OK,
replace U3301
If all parts associated
with the pins are OK,
replace Q3301
Check parts between
T3001 and Q3301 Power OK but
no modulation
If all parts from TP3401 of
U3401 Pin 16 are OK,
replace U3401
If all parts
associated
with the pins
are OK,
replace U3301
4.5V DC at
U3301 Pin 3 OK?
YES
NO 4.5V DC at
U3301 Pin 3 OK?
YES
NO
Make sure Synthesizer is
working correctly and runner
between U3201 Pin 28 and
U4301 Pin 3 is OK
5V DC at U3301
Pin 14&18 OK ?
OK? OK?
If all parts associated
with the pins are OK,
replace Q3301
3-10 TROUBLESHOOTING CHARTS
Chapter 4
VHF PCB/SCHEMATICS/PARTS LISTS
1.0 Allocation of Schematics and Circuit Boards
1.1 Controller Circuits
The VHF circuits are contained on the printed circuit board (PCB) which also contains the Controller
circuits. This Chapter shows the schematics for the VHF circuits only, refer to the Controller section
for details of the related Controller circuits . The PCB component layouts and the Parts Lists in this
Chapter show both the Controller and VHF circuit components. The VHF schematics and the related
PCB and parts list are shown in the tables below.
Table 4-1 VHF 1-25W Diagrams and Parts Lists
PCB :
8486172B04 Main Board Top Side
8486172B04 Main Board Bottom Side
Page 4-3
Page 4-4
SCHEMATICS
Power Amplifier 1 - 25W
FRACN
Voltage Controlled Oscillator
Receiver Front End
IF
Page 4-5
Page 4-6
Page 4-7
Page 4-8
Page 4-9
Parts List
8486172B04 Page 4-10
Controller version is T2
Table 4-2 VHF 1-25W Diagrams and Parts Lists
PCB :
8486172B06 Main Board Top Side
8486172B06 Main Board Bottom Side
Page 4-13
Page 4-14
SCHEMATICS
Power Amplifier 1 - 25W
FRACN
Voltage Controlled Oscillator
Receiver Front End
IF
Page 4-15
Page 4-16
Page 4-17
Page 4-18
Page 4-19
Parts List
8486172B06 Page 4-20
Controller version is T5
Table 4-3 VHF 1-25W Diagrams and Parts Lists
PCB :
8486172B07 Main Board Top Side
8486172B07 Main Board Bottom Side
Page 4-23
Page 4-24
SCHEMATICS
Power Amplifier 1 - 25W
Voltage Controlled Oscillator
Receiver Front End
IF
FRACN
Page 4-15
Page 4-17
Page 4-18
Page 4-25
Page 4-26
Parts List: 8486172B07 Page 4-27
Controller version is T7
4-2 VHF PCB/SCHEMATICS/PARTS LISTS
Table 4-4 VHF 1-25W Diagrams and Parts Lists
PCB :
8486172B08 Main Board Top Side
8486172B08 Main Board Bottom Side
Page 4-31
Page 4-32
SCHEMATICS
Power Amplifier 1 - 25W
FRACN
Voltage Controlled Oscillator
Receiver Front End
IF
Page 4-33
Page 4-34
Page 4-35
Page 4-36
Page 4-37
Parts List: 8486172B08 Page 4-38
Controller version is T9
Table 4-5 VHF 25-45W Diagrams and Parts Lists
PCB :
8486140B12 Main Board Top Side
8486140B12 Main Board Bottom Side
8486140B13 Main Board Top Side
8486140B13 Main Board Bottom Side
Page 4-41
Page 4-42
Page 4-47
Page 4-48
SCHEMATICS
Power Amplifier 25 - 45W
FRACN
Voltage Controlled Oscillator
Receiver Front End
IF
Page 4-43
Page 4-26
Page 4-17
Page 4-18
Page 4-37
Parts List: 8486140B12
Parts List: 8486140B13
Page 4-44
Page 4-49
Controller T6 is used on PCB 8486140B12
Controller T9 is used on PCB 8486140B13
Table 4-6 VHF 25-45W Diagrams and Parts Lists
PCB :
8486140B15 Main Board Top Side
8486140B15 Main Board Bottom Side
Page 4-52
Page 4-53
SCHEMATICS
Power Amplifier 25 - 45W
FRACN
Voltage Controlled Oscillator
Receiver Front End
IF
Page 4-54
Page 4-55
Page 4-56
Page 4-57
Page 4-58
Parts List: 8486140B15 Page 4-59
Controller version is T12
Professional Radio
GM Series
UHF (403-470MHz)
Service Information
Issue: August 2002
ii
Computer Software Copyrights
The Motorola products described in this manual may include copyrighted Motorola computer programs stored
in semiconductor memories or other media. Laws in the United States and other countries preserve for
Motorola certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or
reproduce in any form, the copyrighted computer program. Accordingly, any copyrighted Motorola computer
programs contained in the Motorola products described in this manual may not be copied or reproduced in
any manner without the express written permission of Motorola. Furthermore, the purchase of Motorola
products shall not be deemed to grant, either directly or by implication, estoppel or otherwise, any license
under the copyrights, patents or patent applications of Motorola, except for the normal non-exclusive royalty-
free license to use that arises by operation of law in the sale of a product.
iii
Table of Contents
Chapter 1 MODEL CHART AND TECHNICAL SPECIFICATIONS
1.0 GM140/GM160 Model Chart................................................................................1-1
2.0 GM340/GM360/GM380 Model Chart ...................................................................1-1
3.0 GM640/GM660/GM1280 Model Chart .................................................................1-2
4.0 Technical Specifications ......................................................................................1-3
Chapter 2 THEORY OF OPERATION
1.0 Introduction ..........................................................................................................2-1
2.0 UHF (403-470MHz) Receiver .............................................................................2-1
2.1 Receiver Front-End .......................................................................................2-1
2.2 Front-End Band-Pass Filters & Pre-Amplifier .................................................2-2
2.3 First Mixer and High Intermediate Frequency (IF)..........................................2-2
2.4 Low Intermediate Frequency (IF) and Receiver Back End.............................2-2
3.0 UHF (403-470MHz) Transmitter Power Amplifier (PA) 25 W....................2-3
3.1 First Power Controlled Stage..........................................................................2-3
3.2 Power Controlled Driver Stage .......................................................................2-4
3.3 Final Stage......................................................................................................2-4
3.4 Directional Coupler.........................................................................................2-4
3.5 Antenna Switch...............................................................................................2-5
3.6 Harmonic Filter ...............................................................................................2-5
3.7 Power Control.................................................................................................2-5
4.0 UHF (403-470MHz) Frequency Synthesis ..........................................................2-6
4.1 Reference Oscillator.......................................................................................2-6
4.2 Fractional-N Synthesizer ................................................................................2-6
4.3 Voltage Controlled Oscillator (VCO) ...............................................................2-7
4.4 Synthesizer Operation ....................................................................................2-8
5.0 UHF (403-470MHz) Transmitter Power Amplifier (PA) 45 W....................2-9
5.1 Power Controlled Stage..................................................................................2-9
5.2 Pre-Driver Stage .............................................................................................2-9
5.3 Driver Stage..................................................................................................2-10
5.4 Final Stage....................................................................................................2-10
5.5 Directional Coupler.......................................................................................2-10
5.6 Antenna Switch.............................................................................................2-10
5.7 Harmonic Filter .............................................................................................2-10
5.8 Power Control...............................................................................................2-11
iv
Chapter 3 TROUBLESHOOTING CHARTS
1.0 Troubleshooting Flow Chart for Receiver (Sheet 1 of 2) ..................................... 3-1
1.1 Troubleshooting Flow Chart for Receiver (Sheet 2 of 2) ..................................... 3-2
2.0 Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 3) .........................3-3
2.1 Troubleshooting Flow Chart for 25W Transmitter (Sheet 2 of 3) .........................3-4
2.2 Troubleshooting Flow Chart for 25W Transmitter (Sheet 3 of 3) .........................3-5
3.0 Troubleshooting Flow Chart for 40W Transmitter ...............................................3-6
4.0 Troubleshooting Flow Chart for Synthesizer........................................................3-7
5.0 Troubleshooting Flow Chart for VCO...................................................................3-8
Chapter 4 UHF PCB/SCHEMATICS/PARTS LISTS
1.0 Allocation of Schematics and Circuit Boards .......................................................4-1
1.1 Controller Circuits ................................................................................................4-1
2.0 UHF 1-25W PCB 8485670z02 / Schematics .......................................................4-3
2.1 UHF 1-25W PCB 8485670z02 Parts List...........................................................4-10
3.0 UHF 25-40W PCB 8480643z06 / Schematics ................................................... 4-13
3.1 UHF 25-40W PCB 8480643z06 Parts List.........................................................4-20
4.0 UHF 1-25W PCB 8485670z03 / Schematics ..................................................... 4-23
4.1 UHF 1-25W PCB 8485670z03 Parts List...........................................................4-30
5.0 UHF 1-25W PCB 8486127z01 / Schematics ..................................................... 4-33
5.1 UHF 1-25W PCB 8486127z01 Parts List...........................................................4-40
Chapter 1
MODEL CHART AND TECHNICAL SPECIFICATIONS
1.0 GM140/GM160 Model Chart
GM Series UHF 403-470 MHz
Model Description
MDM25RKC9AN1_E GM140, 403-470 MHz, 25-40W, 4 Ch
MDM25RKF9AN5_E GM160, 403-470 MHz, 25-40W, 128 Ch
MDM25RHC9AA1_E GM140, 403-470 MHz, 1-25W, 4 Ch
MDM25RHF9AA5_E GM160, 403-470 MHz, 1-25W, 128 Ch
Item Description
X X GCN6112_ Control Head GM140
X X GCN6120_ Control Head GM160
X IMUE6012_ Tanapa, GM140
X IMUE6012_ Tanapa, GM160
X IMUE6021_ Tanapa, GM140
X IMUE6021_ Tanapa, GM160
XXXXENBN4056_ Packaging, Waris Mobile Radio
XXXXGLN7324_ Low Profile Mounting Trunion
X X HKN9402_ 12V Power Cable, 25-45W
X X HKN4137_ 12V Power Cable, 1-25W
XXXXMDRMN4025_ Enhanced Compact Microphone
X X 6864110B86_ User Guide, GM140
X X 6864110B87_ User Guide, GM160
X = Indicates one of each is required
1-2 MODEL CHART AND TECHNICAL SPECIFICATIONS
2.0 GM340/GM360/GM380 Model Chart
GM Series UHF 403-470 MHz
Model Description
MDM25RHC9AN1_E GM340, 403-470 MHz, 1-25W, 6 Ch
MDM25RHF9AN5_E GM360, 403-470 MHz, 1-25W, 255 Ch
MDM25RHC9AN8_E GM380, 403-470 MHz, 1-25W, 255 Ch
MDM25RHA9AN0_E Databox, 403-470 MHz, 1-25W, 16 Ch
Item Description
XGCN6112_ Control Head GM340
X GCN6120_ Control Head GM360
XGCN6121_ Control Head GM380
X GCN6116_ Databox Radio Blank Head
XIMUE6015_S Field Replaceable Unit (Main Board) GM340
X IMUE6015_S Field Replaceable Unit (Main Board) GM360
XIMUE6038_S Field Replaceable Unit (Main Board) GM380
X IMUE6015_A S/T 403-470MHz 1-25 SEL5
XXXXENBN4056_ Packaging, Waris Mobile
XXXXGLN7324_ Low Profile Mounting Trunnion
XXXXHKN4137_ 12V Power Cable 1-25W
X X X MDRMN4025_ Enhanced Compact Microphone
X6864110B80 User Guide GM340
X 6864110B81 User Guide, GM360
X6864110B82 User Guide, GM380
X = Indicates one of each is required
GM640/GM660/GM1280 Model Chart 1-3
3.0 GM640/GM660/GM1280 Model Chart
GM Series UHF 403-470 MHz
Model Description
MDM25RHC9CK1_E GM640, 403-470 MHz, 1-25W, 6 Ch
MDM25RHF9CK5_E GM660, 403-470 MHz, 1-25W, 255 Ch
MDM25RHN9CK8_E GM1280, 403-470 MHz, 1-25W, 255 Ch
MDM25RHA9CK7_E Databox, 403-470 MHz, 1-25W, 16 Ch
Item Description
XGCN6112_ Control Head GM640
X GCN6120_ Control Head GM660
XGCN6121_ Control Head GM1280
X GCN6116_ Databox Radio Blank Head
XIMUE6009_AS/T 403-470MHz 1-25 SEL5
X IMUE6009_S Field Replaceable Unit (Main Board) GM640
XIMUE6009_S Field Replaceable Unit (Main Board) GM660
X IMUE6009_S Field Replaceable Unit (Main Board) GM1280
XXXXENBN4056_ Packaging, Waris Mobile Radio
XXXXGLN7324_ Low Profile Mounting Trunnion
XXXXHKN4137_ 12V Power Cable, 1-25W
X X X MDRMN4025_ Enhanced Compact Microphone
X6864110B83_ User Guide, GM640
X 6864110B84_ User Guide, GM660
X6864110B85_ User Guide, GM1280
X = Indicates one of each is required
1-4 MODEL CHART AND TECHNICAL SPECIFICATIONS
4.0 Technical Specifications
Data is specified for +25°C unless otherwise stated.
General Specifications
Channel Capacity
GM140
GM160
GM340
GM360
GM380
GM640
GM660
GM1280
Databox
4
128
6
255
255
6
255
255
16
Power Supply 13.2Vdc (10.8 - 15.6Vdc)
Dimensions: H x W x D (mm) Depth excluding knobs GM140/340/640
56mm x 176mm x 177mm (1 - 25W)
56mm x 176mm x 189mm (25 - 40W)
(add 8mm for Volume Knob)
Dimensions: H x W x D (mm) Depth excluding knobs GM160/360/660
59mm x 179mm x 186mm (1 - 25W)
59mm x 179mm x 198mm (25 - 40W)
(add 9mm for Volume Knob)
Dimensions: H x W x D (mm) Depth excluding knobs GM380/1280
72mm x 185mm x 188mm
(add 8mm for Volume Knob)
Dimensions: H x W x D (mm) Depth excluding knobs Databox
44mm x 168mm x 161mm
Weight GM140/340/640 1400gr
Weight GM160/360/660 1400gr
Weight GM380/1280 1500gr
Weight Databox 1220gr
Sealing: Withstands rain testing per
MIL STD 810 C/D /E and IP54
Shock and Vibration: Protection provided via impact
resistant housing exceeding MIL STD
810-C/D /E and TIA/EIA 603
Dust and Humidity: Protection provided via environment
resistant housing exceeding MIL STD
810 C/D /E and TIA/EIA 603
Technical Specifications 1-5
*Availability subject to the laws and regulations of individual countries.
Transmitter UHF
*Frequencies - Full Bandsplit UHF 403-470 MHz
Channel Spacing 12.5/20/25 kHz
Frequency Stability
(-30°C to +60°C, +25° Ref.) ±2.0 ppm
Power 1-25W/25-40W
Modulation Limiting ±2.5 @ 12.5 kHz
±4.0 @ 20 kHz
±5.0 @ 25 kHz
FM Hum & Noise -40 dB @ 12.5kHz
-45 dB @ 20/25kHz
Conducted/Radiated Emission (ETS) -36 dBm <1 GHz
-30 dBm >1 GHz
Adjacent Channel Power -60 dB @ 12.5 kHz
-70 dB @ 25 kHz
Audio Response (300 - 3000 Hz) +1 to -3 dB
Audio Distortion
@1000Hz, 60%
Rated Maximum Deviation <3% typical
Receiver UHF
*Frequencies - Full Bandsplit UHF 403-470 MHz
Channel Spacing 12.5/20/25 kHz
Sensitivity (12 dB SINAD) 0.30 µV (0.22 µV typical)
Intermodulation (ETS) >65 dB
Base Mode: >70dB
(1-25W model only)
Adjacent Channel Selectivity (ETS) 65 dB @ 12.5 kHz
70 dB @ 20 kHz
75 dB @ 25 kHz
Spurious Rejection (ETS) 70 dB @ 12.5 kHz
75 dB @ 20/25 kHz
Rated Audio 3W Internal
13W External
Audio Distortion @ Rated Audio <3% typical
Hum & Noise -40 dB @ 12.5 kHz
-45 dB @ 20/25 kHz
Audio Response (300 - 3000Hz @ 20/25kHz)
(300 - 2550Hz @12.5kHz) +1 to -3 dB
Conducted Spurious Emission (ETS) -57 dBm <1 GHz
-47 dBm >1 GHz
1-6 MODEL CHART AND TECHNICAL SPECIFICATIONS
Chapter 2
THEORY OF OPERATION
1.0 Introduction
This Chapter provides a detailed theory of operation for the UHF circuits in the radio. For details of
the theory of operation and trouble shooting for the the associated Controller circuits refer to the
Controller Section of this manual.
2.0 UHF (403-470MHz) Receiver
2.1 Receiver Front-End
The receiver is able to cover the UHF range from 403 to 470 MHz. It consists of four major blocks:
front-end bandpass filters and pre-amplifier, first mixer, high-IF, low-IF and receiver back-end . Two
varactor-tuned bandpass filters perform antenna signal pre-selection. A cross over quad diode
mixer converts the signal to the first IF of 44.85 MHz. Low-side first injection is used.
Figure 2-1 UHF Receiver Block Diagram
Demodulator
1. Crystal
Filter
Mixer
Varactor
Tuned Filter
RF Amp
Varactor
Tuned Filter
Pin Diode
Antenna
Switch
RF Jack
Antenna
Control Voltage
from PCIC First LO
from FGU
Recovered Audio
RSSI
Second LO
2. Crystal
Filter
455kHz Filter
(25kHz)
455kHz Filter
(25kHz)
455kHz Filter
(12.5kHz)
455kHz Filter
(12.5kHz)
Switch
Switch
Switch
Switch
Limiter
1. IF Amp
2. IF Amp
Filter Bank Selection
from Synthesizer IC
Harmonic
Filter
BWSELECT
2-2 THEORY OF OPERATION
There are two 2-pole 44.85 MHz crystal filters in the high-IF section and 2 pairs of 455 kHz ceramic
filters in the low-IF section to provide the required adjacent channel selectivity .The correct pair of
ceramic filters for 12.5 or 25KHz channel spacing is selected via control line BWSELECT. The
second IF at 455 kHz is mixed, amplified and demodulated in the IF IC. The processing of the
demodulated audio signal is performed by an audio processing IC located in the controller section.
2.2 Front-End Band-Pass Filters & Pre-Amplifier
The received signal from the radio’s antenna connector is first routed through the harmonic filter and
antenna switch, which are part of the RF power amplifier circuitry, before being applied to the
receiver pre-selector filter (C4001, C4002, D4001 and associated components). The 2-pole pre-
selector filter tuned by the varactor diodes D4001 and D4002 pre-selects the incoming signal
(RXIN) from the antenna switch to reduce spurious effects to following stages. The tuning voltage
(FECTRL_1) ranging from 2 volts to 8 volts is controlled by pin 20 of PCIC (U4501) in the
Transmitter section. A dual hot carrier diode (D4003) limits any inband signal to 0 dBm to prevent
damage to the pre-amplifier.
The RF pre-amplifier is an SMD device (Q4003) with collector base feedback to stabilize gain,
impedance, and intermodulation. The collector current of approximately 11-16 mA is drawn from the
voltage 9V3 via L4003 and R4002. A switchable 3dB pad (R4066,R4007,R4063, R4064 and
R4070), controlled via line FECTRL_2 and Q4004 stabilizes the output impedance and
intermodulation performance.
A second 2-pole varactor tuned bandpass filter provides additional filtering of the amplified signal.
The varactor diodes D4004 and D4005 are controlled by the same signal FECTRL_1, which
controls the pre-selector filter. A following 1 dB pad (R4013 - R4015) stabilizes the output
impedance and intermodulation performance.
2.3 First Mixer and High Intermediate Frequency (IF)
The signal coming from the front-end is converted to the first IF (44.85 MHz) using a cross over
quad diode mixer (D4051). Its ports are matched for incoming RF signal conversion to the 44.85
MHz IF using low side injection via matching transformers T4051 and T4052. The injection signal
(RXINJ) coming from the RX VCO buffer (Q4332) is filtered by the lowpass filter consisting of
(L4053, L4054, C4053 - C4055) followed by a matching transformer T4052 and has a level of
approximately 15dBm.
The mixer IF output signal (IF) from transformer T4501pin 2 is fed to the first two pole crystal filter
FL3101. The filter output in turn is matched to the following IF amplifier.
The IF amplifier Q3101 is actively biased by a collector base feedback (R3101, R3106) to a current
drain of approximately 5 mA drawn from the voltage 5V. Its output impedance is matched to the
second two pole crystal filter FL3102. The signal is further amplified by a preamplifier (Q3102)
before going into pin 1 of IFIC (U3101).
A dual hot carrier diode (D3101) limits the filter output voltage swing to reduce overdrive effects at
RF input levels above -27 dBm.
2.4 Low Intermediate Frequency (IF) and Receiver Back End
The 44.85 high IF signal from the second IF amplifier feeds the IF IC (U3101) at pin1. Within the IF
IC the 44.85 MHz high IF signal mixes with the 44.395 MHz second local oscillator (2nd LO) to
UHF (403-470MHz) Transmitter Power Amplifier (PA) 25 W 2-3
produce the low IF signal at 455 kHz. The 2nd LO frequency is determined by crystal Y3101. The
low IF signal is amplified and filtered by an external pair of 455 kHz ceramic filters FL3112, FL3114
for 20/25 kHz channel spacing or FL3111,FL3113/F3115 for 12.5 kHz channel spacing. These pairs
are selectable via BWSELECT. The filtered output from the ceramic filters is applied to the limiter
input pin of the IF IC (pin 14).
The IF IC contains a quadrature detector using a ceramic phase-shift element (Y3102) to provide
audio detection. Internal amplification provides an audio output level of 120 mV rms (at 60%
deviation) from U3103 pin 8 (DISCAUDIO) which is fed to the ASFIC_CMP (U0221) pin 2 (part of
the Controller circuitry).
A received signal strength indicator (RSSI) signal is available at U3101 pin 5, having a dynamic
range of 70 dB. The RSSI signal is interpreted by the microprocessor (U0101 pin 63) and in addition
is available at accessory connector J0501-15.
3.0 UHF (403-470MHz) Transmitter Power Amplifier (PA) 25 W
The radio’s 25W PA is a three stage amplifier used to amplify the output from the VCOBIC to the
radio transmit level. All three stages utilize LDMOS technology. The gain of the first stage (U4401) is
adjustable, controlled by pin 4 of PCIC (U4501) via U4402-1. It is followed by an LDMOS stage
(Q4421) and LDMOS final stage (Q4441).
Figure 2-2 UHF Transmitter Block Diagram
Devices U4401, Q4421 and Q4441 are surface mounted. A pressure pad between board and the
radio's cover provides good thermal contact between the devices and the chassis.
3.1 First Power Controlled Stage
The first stage (U4401) is a 20dB gain integrated circuit containing two LDMOS FET amplifier
stages. It amplifies the RF signal from the VCO (TXINJ). The output power of stage U4401 is
PCIC
Pin Diode
Antenna
Switch RF Jack
Antenna
Harmonic
Filter
Power
Sense
PA-Final
Stage
From VCO
Controlled
Stage
Vcontrol
Bias 1
Bias 2
To Microprocessor
Temperature
Sense
SPI BUS
ASFIC_CMP
PA
PWR
SET
To Microprocessor
PA
Driver
2-4 THEORY OF OPERATION
controlled by a DC voltage applied to pin 1 from the op-amp U4402-1, pin 1. The control voltage
simultaneously varies the bias of two FET stages within U4401. This biasing point determines the
overall gain of U4401 and therefore its output drive level to Q4421, which in turn controls the output
power of the PA.
Op-amp U4402-1 monitors the drain current of U4401 via resistor R4444 and adjusts the bias
voltage of U4401 so that the current remains constant. The PCIC (U4501) provides a DC output
voltage at pin 4 (INT) which sets the reference voltage of the current control loop. A raising power
output causes the DC voltage from the PCIC to fall, and U4402-1 adjusts the bias voltage for a lower
drain current to lower the gain of the stage.
In receive mode the DC voltage from PCIC pin 23 (RX) turns on Q4442, which in turn switches off
the biasing voltage to U4401.
Switch S5440 is a pressure pad with a conductive strip which connects two conductive areas on the
board when the radio's cover is properly screwed to the chassis. When the cover is removed, S5440
opens and the resulting high voltage level at the inverting inputs of the current control op-amps
U4402-1 & 2 switches off the biasing of U4401 and Q4421. This prevents transmitter key up while
the devices do not have proper thermal contact to the chassis.
3.2 Power Controlled Driver Stage
The next stage is an LDMOS device (Q4421) providing a gain of 12dB. This device requires a
positive gate bias and a quiescent current flow for proper operation. The bias is set during transmit
mode by the drain current control op-amp U4402-2, and fed to the gate of Q4421 via the resistive
network R4429, R4418, R4415 and R4416.
Op-amp U4402-2 monitors the drain current of U4421 via resistors R4424-27 and adjusts the bias
voltage of Q4421 so that the current remains constant. The PCIC (U4501) provides a DC output
voltage at pin 4 (INT) which sets the reference voltage of the current control loop. A raising power
output causes the DC voltage from the PCIC to fall, and U4402-2 adjusts the bias voltage for a lower
drain current to lower the gain of the stage.
In receive mode the DC voltage from PCIC pin 23 (RX) turns on Q4422, which in turn switches off
the biasing voltage to Q4421.
3.3 Final Stage
The final stage is an LDMOS device (Q4441) providing a gain of 12dB. This device also requires a
positive gate bias and a quiescent current flow for proper operation. The voltage of the line
MOSBIAS_2 is set in transmit mode by the ASFIC and fed to the gate of Q4441 via the resistive
network R4404, R4406, and R4431-2. This bias voltage is tuned in the factory. If the transistor is
replaced, the bias voltage must be tuned using the Golbal Tuner. Care must be taken not to
damage the device by exceeding the maximum allowed bias voltage. The device’s drain current is
drawn directly from the radio’s DC supply voltage input, PASUPVLTG, via L4436 and L4437.
A matching network consisting of C4441-49 and striplines transforms the impedance to 50 ohms
and feeds the directional coupler.
3.4 Directional Coupler
The directional coupler is a microstrip printed circuit, which couples a small amount of the forward
power delivered by Q4441. The coupled signal is rectified by D4451. The DC voltage is proportional
to the RF output power and feeds the RFIN port of the PCIC (U4501 pin 1). The PCIC controls the
gain of stages U4401 and Q4421 as necessary to hold this voltage constant, thus ensuring the
forward power out of the radio to be held to a constant value.
UHF (403-470MHz) Transmitter Power Amplifier (PA) 25 W 2-5
3.5 Antenna Switch
The antenna switch consists of two PIN diodes, D4471 and D4472. In the receive mode, both diodes
are off. Signals applied at the antenna jack J4401 are routed, via the harmonic filter, through
network L4472, C4474 and C4475, to the receiver input. In the transmit mode, K9V1 turns on Q4471
which enables current sink Q4472, set to 96 mA by R4473 and VR4471. This completes a DC path
from PASUPVLTG, through L4437, D4471, L4472, D4472, L4471, R4474 and the current sink, to
ground. Both diodes are forward biased into conduction. The transmitter RF from the directional
coupler is routed via D4471 to the harmonic filter and antenna jack. D4472 also conducts, shunting
RF power and preventing it from reaching the receiver port (RXIN). L4472 is selected to appear as a
broadband lambda/4 wave transmission line, making the short circuit presented by D4472 appear as
an open circuit at the junction of D4472 and the receiver path.
3.6 Harmonic Filter
Components L4491-L4493 and L4472, C4491, C4496-98 form a Butterworth low-pass filter to
attenuate harmonic energy of the transmitter to specifications level. R4491 is used to drain
electrostatic charge that might otherwise build up on the antenna. The harmonic filter also prevents
high level RF signals above the receiver passband from reaching the receiver circuits, improving
spurious response rejection.
3.7 Power Control
The transmitter uses the Power Control IC (PCIC, U4501) to control the power output of the radio. A
portion of the forward RF power from the transmitter is sampled by the directional coupler and
rectified, to provide a DC voltage to the RFIN port of the PCIC (pin 1) which is proportional to the
sampled RF power.
The ASFIC (U0221) has internal digital to analog converters (DACs) which provide a reference
voltage of the control loop to the PCIC via R4505. The reference voltage level is programmable
through the SPI line of the PCIC. This reference voltage is proportional to the desired power setting
of the transmitter, and is factory programmed at several points across the frequency range of the
transmitter to offset frequency response variations of the transmitter’s power detector circuit.
The PCIC provides a DC output voltage at pin 4 (INT) which sets the drain current of the first
(U4401) and second (Q4421) transmitter stage via current control op-amps U3402-1 and U3402-2.
This adjusts the transmitter power output to the intended value. Variations in forward transmitter
power cause the DC voltage at pin 1 to change, and the PCIC adjusts the control voltage above or
below its nominal value to raise or lower output power.
Capacitors C4502-4, in conjunction with resistors and integrators within the PCIC, control the
transmitter power-rise (key-up) and power-decay (de-key) characteristic to minimize splatter into
adjacent channels.
U4502 is a temperature-sensing device, which monitors the circuit board temperature in the vicinity
of the transmitter driver and final devices, and provides a dc voltage to the PCIC (TEMP, pin 30)
proportional to temperature. If the DC voltage produced exceeds the set threshold in the PCIC, the
transmitter output power will be reduced so as to reduce the transmitter temperature.
2-6 THEORY OF OPERATION
4.0 UHF (403-470MHz) Frequency Synthesis
The synthesizer subsystem consists of the reference oscillator (Y4261 or Y4262), the Low Voltage
Fractional-N synthesizer (LVFRAC-N, U4201), and the Voltage Controlled Oscillator VCO.
4.1 Reference Oscillator
The reference oscillator (Y4262) contains a temperature compensated crystal oscillator with a
frequency of 16.8 MHz. An Analogue to Digital (A/D) converter internal to U4201 (LVFRAC-N) and
controlled by the microprocessor via serial interface (SRL) sets the voltage at the warp output of
U4201 pin 25 to set the frequency of the oscillator. The output of the oscillator (pin 3 of Y4262) is
applied to pin 23 (XTAL1) of U4201 via a RC series combination.
In applications where less frequency stability is required the oscillator inside U4201 is used along
with an external crystal Y4261, varactor diode D4261, C4261, C4262 and R4262. In this case,
Y4262, R4263, C4235 and C4251 are not used. When Y4262 is used, Y4261, D4261, C4261,
C4262 and R4262 are not used, and C4263 is increased to 0.1 uF.
4.2 Fractional-N Synthesizer
The LVFRAC-N synthesizer IC (U4201) consists of a pre-scaler, a programmable loop divider,
control divider logic, a phase detector, a charge pump, an A/D converter for low frequency digital
modulation, a balance attenuator to balance the high frequency analogue modulation and low
frequency digital modulation, a 13V positive voltage multiplier, a serial interface for control, and
finally a super filter for the regulated 5 volts.
Figure 2-3 UHF Synthesizer Block Diagram
DATA
CLK
CEX
MODIN
VCC, DC5V
XTAL1
XTAL2
WARP
PREIN
VCP
REFERENCE
OSCILLATOR
VOLTAGE
MULTIPLIER
DATA (U0101 PIN 100)
CLOCK (U0101 PIN 1)
CSX (U0101 PIN 2)
MOD IN (U0221 PIN 40)
+5V (U4211 PIN 1)
7
8
9
10
13, 30
23
24
25
32
47
VMULT2 VMULT1
BIAS1
SFOUT
AUX3
AUX4
IADAPT
IOUT
GND
FREFOUT
LOCK 4
19
6, 22, 33, 44
43
45
3
2
28
14 15
40
FILTERED 5V
STEERING
LOCK (U0101 PIN 56)
PRESCALER IN
FREF (U0221 PIN 34)
39
BIAS2
41
48
5, 20, 34, 36
+5V (U4211 PIN 1)
AUX1
VDD, DC5V MODOUT
U4201
LOW VOLTAGE
FRACTIONAL-N
SYNTHESIZER
AUX2 1 (NU)
BWSELECT
VCO Bias
TRB
To IF
Section
TX RF INJECTION
(1ST STAGE OF PA)
LO RF INJECTION
VOLTAGE
CONTROLLED
OSCILLATOR
LINE
2-POLE
LOOP
FILTER
UHF (403-470MHz) Frequency Synthesis 2-7
A voltage of 5V applied to the super filter input (U4201 pin 30) supplies an output voltage of 4.5
VDC(VSF) at pin 28. It supplies the VCO, VCO modulation bias circuit (via R4322) and the
synthesizer charge pump resistor network (R4251, R4252). The synthesizer supply voltage is
provided by the 5V regulator U4211.
In order to generate a high voltage to supply the phase detector (charge pump) output stage at pin
VCP (U4201-47), a voltage of 13 VDC is being generated by the positive voltage multiplier circuitry
(D4201, C4202, C4203). This voltage multiplier is basically a diode capacitor network driven by two
(1.05MHz) 180 degrees out of phase signals (U4201-14 and -15).
Output LOCK (U4201-4) provides information about the lock status of the synthesizer loop. A high
level at this output indicates a stable loop. IC U4201 provides the 16.8 MHz reference frequency at
pin 19.
The serial interface (SRL) is connected to the microprocessor via the data line DATA (U4201-7),
clock line CLK (U4201-8), and chip enable line CSX (U4201-9).
4.3 Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator (VCO) consists of the VCO/Buffer IC (VCOBIC, U4301), the TX
and RX tank circuits, the external RX buffer stages, and the modulation circuitry.
Figure 2-4 UHF VCO Block Diagram
Presc
RX
TX
Matching
Network Low Pass
Filter
Attenuator
Pin8
Pin14
Pin10
(U4201 Pin28)
VCC Buffers
TX RF Injection
U4201 Pin 32
AUX3 (U4201 Pin 2)
Prescaler Out
Pin 12Pin 19
Pin 20
TX/RX/BS
Switching Network
U4301
VCOBIC
Rx
Active Bias
Tx
Active Bias
Pin2
Rx-I adjust
Pin1
Tx-I adjust
Pins 9,11,17
Pin18
Vsens
Circuit
Pin15
Pin16
RX VCO
Circuit
TX VCO
Circuit
RX Tank
TX Tank
Pin7
Vcc-Superfilter
Collector/RF in
Pin4
Pin5
Pin6
RX
TX
(U4201 Pin 28)
Rx-SW
Tx-SW
Vcc-Logic
(U4201 Pin 28)
Steer Line
Voltage
(VCTRL)
Pin13
Pin3
TRB IN
LO RF INJECTION
Q4301
Q4332
2-8 THEORY OF OPERATION
The VCOBIC together with Fractional-N synthesizer (U4201) generates the required frequencies in
both transmit and receive modes. The TRB line (U4301 pin 19) determines which tank circuits and
internal buffers are to be enabled. A high level on TRB enables TX tank and TX output (pin 10), and
a low enables RX tank and RX output (pin 8). A sample of the signal from the enabled output is
routed from U4301 pin 12 (PRESC_OUT), via a low pass filter, to pin 32 of U4201 (PREIN).
A steering line voltage (VCTRL) between 3.0V and 10.0V at varactor diode CR4311 will tune the full
TX frequency range (TXINJ) from 403 MHz to 470 MHz, and at varactor diodes CR4301, CR4302
and CR4303 will tune the full RX frequency range (RXINJ) from 358 MHz to 425 MHz. The tank
circuits uses the Hartley configuration for wider bandwidth. For the RX tank circuit, an external
transistor Q4301 is used in conjunction with the internal transistor for better side-band noise.
The external RX buffers (Q4332) are enabled by a high at U4201 pin 3 (AUX4) via transistor switch
Q4333. In TX mode the modulation signal (VCOMOD) from the LVFRAC-N synthesizer IC (U4201
pin41) is applied modulation circuitry CR4321, R4321, R4322 and C4324, which modulates the TX
VCO frequency via coupling capacitor C4321. Varactor CR4321 is biased for linearity from VSF.
4.4 Synthesizer Operation
The complete synthesizer subsystem comprises mainly of low voltage FRAC-N (LVFRACN) IC,
Reference Oscillator (crystal oscillator with temperature compensation), charge pump circuitry, loop
filter circuitry and DC supply. The output signal PRESC_OUT of the VCOBIC (U4301 pin12) is fed to
pin 32 of U4201 (PREIN) via a low pass filter (C4229, L4225) which attenuates harmonics and
provides the correct level to close the synthesizer loop.
The pre-scaler in the synthesizer (U4201) is basically a dual modulus pre-scaler with selectable
divider ratios. This divider ratio of the pre-scaler is controlled by the loop divider, which in turn
receives its inputs via the SRL. The output of the pre-scaler is applied to the loop divider. The output
of the loop divider is connected to the phase detector, which compares the loop divider´s output
signal with the reference signal.The reference signal is generated by dividing down the signal of the
reference oscillator (Y4261 or Y4262).
The output signal of the phase detector is a pulsed DC signal which is routed to the charge pump.
The charge pump outputs a current at pin 43 of U4201 (IOUT). The loop filter (which consists of
R4221-R4223, C4221-C4225,L4221) transforms this current into a voltage that is applied to the
varactor diodes CR4311 for transmit, CR4301, CR4302 & CR4303 for receive and alters the output
frequency of the VCO .The current can be set to a value fixed in the LVFRAC-N IC or to a value
determined by the currents flowing into BIAS 1 (U4201-40) or BIAS 2 (U4201-39). The currents are
set by the value of R4251 or R4252 respectively. The selection of the three different bias sources is
done by software programming.
To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer the
magnitude of the loop current is increased by enabling the IADAPT (U4201-45) for a certain
software programmable time (Adapt Mode). The adapt mode timer is started by a low to high
transient of the CSX line. When the synthesizer is within the lock range the current is determined
only by the resistors connected to BIAS 1, BIAS 2, or the internal current source. A settled
synthesizer loop is indicated by a high level of signal LOCK (U4201-4).
The LOCK (U4201-4) signal is routed to one of the µP´s ADCs input U101-56. From the voltage the
µP determines whether LOCK is active. In order to modulate the PLL the two spot modulation
method is utilized. Via pin 10 (MODIN) on U4201 the audio signal is applied to both the A/D
converter (low freq path) as well as the balance attenuator (high freq path). The A/D converter
converts the low frequency analogue modulating signal into a digital code that is applied to the loop
divider, thereby causing the carrier to deviate. The balance attenuator is used to adjust the VCO’s
deviation sensitivity to high frequency modulating signals. The output of the balance attenuator is
present at the MODOUT port (U4201-41) and connected to the VCO modulation diode CR4321 via
R4321, C4325.
UHF (403-470MHz) Transmitter Power Amplifier (PA) 40W 2-9
5.0 UHF (403-470MHz) Transmitter Power Amplifier (PA) 40W
The radio’s 40 W PA is a four stage amplifier used to amplify the output from the VCOBIC to the radio
transmit level. It consists of the following four stages in the line-up. The first stage is a LDMOS
predriver (U4401) that is controlled by pin 4 of PCIC (U4501) via Q4473 (CNTLVLTG). It is followed
by another LDMOS stage (Q4421), an LDMOS stage (Q4431) and a bipolar final stage (Q4441).
Figure 2-1 UHF Transmitter Block Diagram
Device Q4401 is surface mounted. Q4421, Q4431 and Q4441 are directly attached to the heat sink.
5.1 Power Controlled Stage
The first stage (U4401) amplifies the RF signal from the VCO (TXINJ) and controls the output power
of the PA. The output power of the transistor U4401 is controlled by a voltage control line feed from
the PCIC pin4(U4501). The control voltage simultaneously varies the bias of two FET stages within
U4401. This biasing point determines the overall gain of U4401 and therefore its output drive level to
Q4421, which in turn controls the output power of the PA.
In receive mode the voltage control line is at ground level and turns off Q4473 which in turn switches
off the biasing voltage to U4401.
5.2 Pre-Driver Stage
The next stage is a 13dB gain LDMOS device (Q4421) which requires a positive gate bias and a
quiescent current flow for proper operation. The voltage of the line PCIC_MOSBIAS_1 is set in
transmit mode by PCIC pin 24 and fed to the gate of Q4421 via the resistive network R4480, R4416
and R4415. The bias voltage is tuned in the factory.
PCIC
Pin Diode
Antenna
Switch RF Jack
Antenna
Harmonic
Filter
Power
Sense
PA-Final
Stage
PA
Driver
From VCO
Controlled
Stage
Vcontrol
Bias 1
Bias 2
To Microprocessor
Temperature
Sense
SPI BUS
ASFIC_CMP
PA
PWR
SET
To Microprocessor
Pre
Driver
2-10 THEORY OF OPERATION
5.3 Driver Stage
The following stage is an enhancement-mode N-Channel MOSFET device (Q4431) providing a gain
of 10dB. This device also requires a positive gate bias and a quiescent current flow for proper
operation. The voltage of the line Bias_2_UHF_PA_1 is set in transmit mode by the ASFIC and fed to
the gate of Q4431 via the resistive network R4632, R4631, R4485 and R4486. This bias voltage is
also tuned in the factory. If the transistor is replaced, the bias voltage must be tuned using the
Customer Programming Software (CPS). Care must be taken not to damage the device by exceeding
the maximum allowed bias voltage. The device’s drain current is drawn directly from the radio’s DC
supply voltage input, A+, via L4421.
5.4 Final Stage
The final stage uses the bipolar device Q4441. The device’s collector current is also drawn from the
radio’s DC supply voltage input. To maintain class C operation, the base is DC-grounded by a series
inductor (L4441) and a bead (L4440). A matching network consisting of C4441-C4444, C4491 and
two striplines transforms the impedance to 50 Ohms and feeds the directional coupler.
5.5 Directional Coupler
The Bi-directional coupler is a microstrip printed circuit, which couples a small amount of the forward
and reverse power of the RF power from Q4441. The coupled signal is rectified to an output power
proportional DC voltage by the diodes D4451 & D4452 and sent to the RFIN of PCIC. The PCIC
controls the gain of stage U4401 as necessary to hold this voltage constant, thus ensuring the
forward power out of the radio to be held to a constant value.
5.6 Antenna Switch
The antenna switch consists of two PIN diodes, D4471 and D4472. In the receive mode, both
diodes are off. Signals applied at the antenna jack J4401 are routed, via the harmonic filter, through
network L4472, C4474 and C4475, to the receiver input. In the transmit mode, K9V1 turns on
Q4471 which enables current sink Q4472, set to 96 mA by R4511 and VR4471. This completes a
DC path from PASUPVLTG, through L4437, D4471, L4472, D4472, L4473, R4496 and the current
sink, to ground. Both diodes are forward biased into conduction. The transmitter RF from the
directional coupler is routed via D4471 to the harmonic filter and antenna jack. D4472 also
conducts, shunting RF power and preventing it from reaching the receiver port (RXIN). L4472 is
selected to appear as a broadband Lambda/4 wave transmission line, making the short circuit
presented by D4472 appear as an open circuit at the junction of D4472 and the receiver path.
5.7 Harmonic Filter
Inductors L4491, L4492, L4493 and capacitors C4448, C4492,C4494, C4496 and C4498 form a
low-pass filter to attenuate harmonic energy of the transmitter to specifications level. R4491 is used
to drain electrostatic charge that might otherwise build up on the antenna. The harmonic filter also
prevents high level RF signals above the receiver passband from reaching the receiver circuits,
improving spurious response rejection.
UHF (403-470MHz) Transmitter Power Amplifier (PA) 40W 2-11
5.8 Power Control
The transmitter uses the Power Control IC (PCIC, U4501) to control the power output of the radio. A
portion of the forward RF power from the transmitter is sampled by the bi-directional coupler and
rectified, to provide a DC voltage to the RFIN port of the PCIC (pin 1) which is proportional to the
sampled RF power.
The PCIC has internal digital to analog converters (DACs) which provide the reference voltage of the
control loop. The reference voltage level is programmable through the SPI line of the PCIC. This
reference voltage is proportional to the desired power setting of the transmitter, and is factory
programmed at several points across the frequency range of the transmitter to offset frequency
response variations of the transmitter s power detector circuitry.
The PCIC provides a DC output voltage at pin 4 (INT) which is applied as CNTLVLTG to the power-
adjust input pin of the first transmitter stage U4401. This adjusts the transmitter power output to the
intended value. Variations in forward transmitter power cause the DC voltage at pin 1 to change, and
the PCIC adjusts the control voltage above or below its nominal value to raise or lower output power.
Capacitors C4502-4, in conjunction with resistors and integrators within the PCIC, control the
transmitter power-rise (key-up) and power-decay (de-key) characteristic to minimize splatter into
adjacent channels.
U4502 is a temperature-sensing device, which monitors the circuit board temperature in the vicinity
of the transmitter driver and final devices, and provides a dc voltage to the PCIC (TEMP, pin 29)
proportional to temperature. If the DC voltage produced exceeds the set threshold in the PCIC, the
transmitter output power will be reduced so as to reduce the transmitter temperature.
2-12 THEORY OF OPERATION
Chapter 3
TROUBLESHOOTING CHARTS
1.0 Troubleshooting Flow Chart for Receiver (Sheet 1 of 2)
Bad SINAD
Bad 20dB Quieting
No Recovered Audio
START
Audio at
pin 8 of
U3101 ?
Check Controller
(in the case of no audio)
OR ELSE go to “B”
Yes
No
Spray or inject 44.85MHz
into XTAL Filter FL3101
Audio heard ?
BYes
No
Check 2nd LO
(44.395MHz) at C3135
LO present ?
BYes
Check voltages on
U3101
Biasing OK ?
No
No
A
Yes
Check Q3102 bias
for faults
Replace Q3102
Go to B
Yes
No
Check circuitry
around U3101.
Replace
U3101 if defect
Check circuitry around Y3101 Re-
place Y3101 if defect
Voltages
OK?
3-2 TROUBLESHOOTING CHARTS
1.1 Troubleshooting Flow Chart for Receiver (Sheet 2 of 2)
IF Signal at
C3101?
No
RF
Signal at
T4051?
RF
Signal at
C4015?
No
No
RF
Signal at
C4025?
No or
Check harmonic filter
L4491-L4493, C4492, J4401
and ant.switch
D4471, D4472, L4472.
Check filter between
C4025 & C4009.
Check tuning voltage
at R4060.
Inject RF into J4401
Is
tuning voltage
OK?
No
Yes
Check RF amp (Q4003)
Stage.
Check filter between
C4015 & T4051.
Yes
Check T4051, T4052,
D4051, R4052, L4008.
Yes
1st LO level
OK?
Locked?
Yes
Check FGU
Yes
Trace IF signal
from C3101 to
Q3101. Check for
bad XTAL filter.
No
Yes IF
signal at Q3102
collector?
Before replacing
U3101, check
U3101 voltages.
Yes
Check for
5VDC
Is 9V3
present?
Check Supply Voltage
circuitry. Check Q0681,
U4211 and U0641.
No
No
No
Check U4501.
Check varactor filter.
No
Yes
Yes
Yes
A
A
B
weak RF
RF
Signal at
C4009?
Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 3) 3-3
2.0 Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 3)
Current
increase
when keyed?
NO
YES
START
Check if Pressure Pad closes S5440
Check Components between
Q4441 and RF Output,
Antenna Switch
D4471,D4472,Q4472,
>500mA & <4A
>4A
<500mA
Check PA Stages Control Volt-
age at
TP4402
>1V
Short TP4403 to
Ground
NO
YES
Voltage at
TP4402
rises?
Check PA Stages NO
YES
PCIC U4501
Pin 14 9.3V
DC?
Check 9.3 V Regulator
U0641
NO
YES
PCIC U4501
Pin 16 >4V
DC
Replace PCIC U4501
NO
YES
TP4404
9.1V DC
If U4201 Pin 2 is high,
replace PCIC
U4501,otherwise
check controller and
FGU
YES
NO
TP4403
>0.5V DC?
Replace PCIC U4501
Check Forward Power
Sense Circuit (D4451)
Check Forward Power
Sense Circuit (D4451)
NO
YES
PCIC U4501
Pin 5 > 1V
DC?
Check Power Setting,
Tuning & Components
between PCIC Pin 5
and ASFIC (U0221)
Pin 4 before replacing
ASFIC
No or too low Power when keyed
3-4 TROUBLESHOOTING CHARTS
2.1 Troubleshooting Flow Chart for 25W Transmitter (Sheet 2 of 3)
Check PA Stages
No or too low Power when keyed
Measure DC Voltage at Pin 2 & 3 of U4401
>6
YES
DC Voltage
at U4501
Pin 23 =0?
2-6
DC Voltage
at U4402-1
Pin 1?
YES
Pin 2
Voltage 0.62
* Voltage at
Pin 1?
If U4201 Pin 2 is high,
replace PCIC
NO Replace U4401
YES
NO
DC
Voltage at
U4402-1 Pin
3 = 8.8V?
Check S4440,
R4442 and R4443
YES
Pin 3
Voltage 0.51
* Voltage at
Pin 1?
NO Replace U4401
<2V DC
Voltage at
U4402-2
Pin 7?
>6V
Check Components
between U4402-2 Pin7
and Q4421. Check
Resistive Network at
Pins 5 & 6 before
replacing Q4421
YES
DC
Voltage at
U4402-2 Pin 5
<8.8V?
Check Components
between U4402-2 Pin7
and Q4421. Check Resis-
tive Network at Pins 5 & 6
before replacing Q4421
NO
Check Q4422
NO
Check Final PA Stage
2-6V
<2V Check Resistive Net-
work at Pins 2 & 3 of
U4402-1 before replac-
ing U4401
Check Q4442 and
Resistive Network at
U4402-1 Pin 3
before replacing
U4401
Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 3) 3-5
2.2 Troubleshooting Flow Chart for 25W Transmitter (Sheet 3 of 3)
Check Final PA Stage
NO
0V
1-4V
Bias 2 DC
Voltage at
TP4406?
YES
RF Voltage
at TP4401
>100mV?
YES
RF Voltage
U4401 Pin 6
>3V?
Supply
Replace Q4441
Check FGU (U4301)
NO Check Components
between
TP4401 &C4417
NO
YES ASFIC
U0221 Pin 6
1-4V DC?
Check Bias Tuning
before replacing ASFIC
U0221
Check Components
between ASFIC and
Q4441 before
replacing Q4441
YES
RF Voltage
Q4421 Gate
>1V?
NO Check Components
between
C4417 & Q4421
YES
RF Voltage
Q4441 Gate
>4V?
NO Check Components
between
Q4421 & Q4441
Check Components
between Q4441 &
Antenna Connector
Voltage
3-6 TROUBLESHOOTING CHARTS
3.0 Troubleshooting Flow Chart for UHF 40W Transmitter
No
Is Q4441 OK ?
Yes
Is drive from VCO
>+4dBm?
No
Is voltage drop across
R4497 >4.5V ?
No
Check Q4431 gate(open)
and drain resistances
(11kohm)
No
Check Q4421 gate(open)
and drain resistances
(11kohm)
No
Check
PCIC_MOSBIAS_1
No
No
Change
Q4473
START
No power
Is Vctrl
there?
Is Q4473
OK?
Check voltage
on Pin 5 U4501
Check R4422-5
and go back to top
Troubleshoot
ASFIC
Check voltage
on TP4531
Change
PCIC
Check R4409 &
R4473 and go back
to top
Check
MOSBIAS_2 Check
ASFIC
Are D4471 &
D4472 OK? Change
D4471 &
D4472
No No
No
Yes
Yes
Yes
Yes
Yes Yes
Yes
Yes
No Check
PCIC
Yes
Change Q4421
Change Q4431
Yes
Change U4401
Yes Do visual check
on all components
No
Change Q4441
Troubleshoot
VCO
No
Check voltage
Check voltage
on Pin 4 U4501
OK?
OK?
OK?
OK? OK?
OK?
OK?
Troubleshooting Flow Chart for Synthesizer 3-7
4.0 Troubleshooting Flow Chart for Synthesizer
5V
at pin 6 of
D4201
Is
information
from mP U0101
correct
?
Is
U4201 Pin 47
at = 13VDC
?
Is
U4301 Pin 19
<40 mVDC in RX &
>4.5 VDC in TX?
(at VCO section)
?
Start
Visual
check of the
Board
OK?
Correct
Problem
Check 5V
Regulator
U4211
+5V
at U4201
Pin’s
13 & 30
?
Is
16.8MHz
Signal at U4201
Pin 19
?
Check
Y4261 / Y4262 and
associated Parts
Are
signals
at Pin’s 14 &15
of U4201
?
Check
R4201 Check C4381
Is
U4201
Pin 2 >4.5 VDC in
Tx & <40 mVDC
in Rx
?
Replace
U4201
Remove
Shorts
Is
there a short
between Pin 47 and
Pins 14 & 15 of
U4201
?
Replace or
resolder
necessary
components
Is
RF level at
U4201 Pin 32
-12 < x <-25
dBm
?
Are
R4221,R4222,
R4223,C4221,
C4222,& C4223
OK?
Replace
U4201
If L4225, C4229 & C4227
are OK, then see VCO
troubleshooting chart
Are
Waveforms
at Pins 14 & 15
triangular
?
Do
Pins 7,8 & 9
of U4201 toggle
when channel is
changed?
Check programming
lines between
U0101 and U4201
Pins 7,8 & 9
Replace
U4201
Check uP U0101
Troubleshooting
Chart
NO
YES
NO
YES
NO
YES
NO
NO
NO
YES
YES
NO
YES
YES
NO
YES
YES
YES
NO
NO
NO
NO
YES
NO
YES
YES
Check D4201,
C4202, C4203, &
C4206
5V
at U4201
pins 5, 20, 34
& 36
Check 5V
Regulator
U4211
Is
16.8MHz
signal at
U4201 Pin
23?
Replace
U4201
YES
NO
NO
YES
NO
YES
3-8 TROUBLESHOOTING CHARTS
5.0 Troubleshooting Flow Chart for VCO
Are Q4332
Base at 0.7V
Collector at 4.5V
Emitter at 110mV
Are Q4301
Base at 2.4V
Collector at 4.5V
Emitter at 1.7V
Are U4301 Pins
13 at 4.4V
15 at 1.1V
10 at 4.5V
16 at 1.9V
Low or no RF Signal
at TP4003
Visual check
of board
OK?
35mV DC at
U4301 Pin 19
NO
YES
Replace Q4301
at base of Q4332
NO
NO
NO
NO
YES
YES
YES
YES
Low or no RF Signal
at input to PA
4.8V DC at
U4301 Pin 19
Is RF available
at C4402
YES
YES
YES
YES
NO
NO
NO
NO
NO
Audio =180mVRMS
at “-” Side of
4.5VDC
at CR4321
If C4321 and R4321 are OK,
then replace CR4321
Replace C4322
Replace C4325
NO
NO
YES
YES
If parts between
R4402 & U4301 Pin10
are OK, replace U4301
TX VCO
RX VCO
Correct
Problem
Visual check
of board
OK?
Check runner
between U4201 Pin 2
and U4301 Pin 19
Is RF available If all parts from U4301 Pin 8
to Base of Q4332 are OK,
replace U4301
If all parts associated
with the pins are OK,
replace Q4332
If all parts from collector
of Q4332 to TP4003 are
OK, Replace Q4332
Power OK but
no modulation
Check parts from
R4402 to U4401 Pin16
If all parts
associated
with the pins
are OK,
replace U4301
YES YES
Make sure Synthesizer is
working correctly and runner
between U4201 Pin 28 and
U4301 Pin 14 & and is OK
4.5V DC
OK ?
OK? OK?
C4325
at U4301 Pin 14 & 18 4.5V DC
OK ?
at U4301 Pin 14&18
NO
Chapter 4
UHF PCB/SCHEMATICS/PARTS LISTS
1.0 Allocation of Schematics and Circuit Boards
1.1 Controller Circuits
The UHF circuits are contained on the printed circuit board (PCB) which also contains the Controller
circuits. This Chapter shows the schematics for the UHF circuits only, refer to the Controller section
for details of the related Controller circuits . The PCB component layouts and the Parts Lists in this
Chapter show both the Controller and UHF circuit components. The UHF schematics and the
related PCB and parts list are shown in the tables below.
Table 4-1 UHF 1-25W Diagrams and Parts Lists
PCB :
8485670z02 Main Board Top Side
8485670z02 Main Board Bottom Side
Page 4-3
Page 4-4
SCHEMATICS
Power Amplifier 1 - 25W
FRACN
Voltage Controlled Oscillator
Receiver Front End
IF
Page 4-5
Page 4-6
Page 4-7
Page 4-8
Page 4-9
Parts List
8485670z02 Page 4-10
Controller version is T7
Table 4-2 UHF 25-40W Diagrams and Parts Lists
PCB :
8480643z06 Main Board Top Side
8480643z06 Main Board Bottom Side
Page 4-13
Page 4-14
SCHEMATICS
Power Amplifier 25 - 40W
FRACN
Voltage Controlled Oscillator
Receiver Front End
IF
Page 4-15
Page 4-16
Page 4-17
Page 4-18
Page 4-19
Parts List
8480643z06 Page 4-20
Controller version is T9
4-2 UHF PCB/Schematics/parts lists
Table 4-3 UHF 1-25W Diagrams and Parts Lists
PCB :
8485670z03 Main Board Top Side
8485670z03 Main Board Bottom Side
Page 4-23
Page 4-24
SCHEMATICS
Power Amplifier 1 - 25W
FRACN
Voltage Controlled Oscillator
Receiver Front End
IF
Page 4-25
Page 4-26
Page 4-27
Page 4-28
Page 4-29
Parts List
8485670z03 Page 4-30
Controller version is T9
Table 4-4 UHF 25-40W Diagrams and Parts Lists
PCB :
8486127z01 Main Board Top Side
8486127z01 Main Board Bottom Side
Page 4-33
Page 4-34
SCHEMATICS
Power Amplifier 1 - 25W
FRACN
Voltage Controlled Oscillator
Receiver Front End
IF
Page 4-35
Page 4-36
Page 4-37
Page 4-38
Page 4-39
Parts List
8486127z01 Page 4-40
Controller version is T12
Professional Radio
GM Series
LB1 (29.6 - 36.0MHz)
LB2 (36.0 - 42.0MHz)
LB3 (42.0 - 50.0MHz)
Service Information
Issue: August 2002
ii
Computer Software Copyrights
The Motorola products described in this manual may include copyrighted Motorola computer programs stored
in semiconductor memories or other media. Laws in the United States and other countries preserve for
Motorola certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or
reproduce in any form, the copyrighted computer program. Accordingly, any copyrighted Motorola computer
programs contained in the Motorola products described in this manual may not be copied or reproduced in
any manner without the express written permission of Motorola. Furthermore, the purchase of Motorola
products shall not be deemed to grant, either directly or by implication, estoppel or otherwise, any license
under the copyrights, patents or patent applications of Motorola, except for the normal non-exclusive royalty-
free license to use that arises by operation of law in the sale of a product.
iii
Table of Contents
Chapter 1 MODEL CHART AND TECHNICAL SPECIFICATIONS
1.0 GM360 Model Chart.............................................................................................1-1
2.0 Technical Specifications ......................................................................................1-1
Chapter 2 THEORY OF OPERATION
1.0 Introduction ..........................................................................................................2-1
2.0 Low Band Receiver.............................................................................................2-2
2.1 Receiver Front-End .......................................................................................2-2
2.2 Front-End Band-Pass Filters & Pre-Amplifier .................................................2-3
2.3 First Mixer ......................................................................................................2-3
2.4 High Intermediate Frequency (IF) and Receiver Back End ............................2-3
2.5 Low Intermediate Frequency (IF) and Receiver Back End.............................2-4
2.6 "Extender" (Noise Blanker).............................................................................2-4
3.0 Low Band Transmitter Power Amplifier (PA) 25-60 W ........................................2-5
3.1 Power Controlled Stage..................................................................................2-5
3.2 Driver Stage....................................................................................................2-5
3.3 Final Stage......................................................................................................2-6
3.4 Antenna Switch...............................................................................................2-6
3.5 Harmonic Filter ...............................................................................................2-6
3.6 Power Control.................................................................................................2-6
3.7 TX Safety Switch ............................................................................................2-6
4.0 Low Band Frequency Synthesis .........................................................................2-7
4.1 Fractional-N Synthesizer ................................................................................2-7
4.2 Voltage Controlled Oscillator (VCO) ...............................................................2-9
4.3 Synthesizer Operation..................................................................................2-10
Chapter 3 TROUBLESHOOTING CHARTS
1.0 Troubleshooting Flow Chart for Transmitter .......................................................3-1
2.0 Troubleshooting Flow Chart for Receiver (Sheet 1 of 2)......................................3-2
2.1 Troubleshooting Flow Chart for Receiver (Sheet 2 of 2)......................................3-3
3.0 Troubleshooting Flow Chart for Synthesizer........................................................3-4
4.0 Troubleshooting Flow Chart for VCO .................................................................3-5
iv
Chapter 4 Low Band PCB/SCHEMATICS/PARTS LISTS
1.0 Allocation of Schematics and Circuit Boards .......................................................4-1
1.1 Controller Circuits ................................................................................................4-1
2.0 LB1 25-60W PCB 8486206B06 / Schematics .....................................................4-5
2.1 LB1 25-60W PCB 8486206B06 Parts List ......................................................... 4-15
3.0 LB2 25-60W PCB 8486207B05 / Schematics ...................................................4-18
3.1 LB2 25-60W PCB 8486207B05 Parts List ......................................................... 4-28
4.0 LB3 25-60W PCB 8485908z03 / Schematics ....................................................4-31
4.1 LB3 25-60W PCB 8485908z03 Parts List..........................................................4-41
5.0 LB1 25-60W PCB 8486206B08 / Schematics ...................................................4-44
5.1 LB1 25-60W PCB 8486206B08 Parts List ......................................................... 4-48
6.0 LB2 25-60W PCB 8486207B07 / Schematics ...................................................4-51
6.1 LB2 25-60W PCB 8486207B07 Parts List ......................................................... 4-53
7.0 LB3 25-60W PCB 8485908z04 / Schematics ....................................................4-56
7.1 LB3 25-60W PCB 8485908z04 Parts List..........................................................4-58
Chapter 1
MODEL CHART AND TECHNICAL SPECIFICATIONS
1.0 GM360 Model Chart
2.0 Technical Specifications
Data is specified for +25°C unless otherwise stated.
GM Series Low Band 29-50 MHz
Model Description
MDM25BKF9AN5_E GM360 LB1, 29.0-36.0 MHz, 25-60W, 255 Ch
MDM25CKF9AN5_E GM360 LB2, 36.0-42.0 MHz, 25-60W, 255 Ch
MDM25DKF9AN5_E GM360 LB3, 42.0-50.0 MHz, 25-60W, 255 Ch
Item Description
XXXGCN6114_ Control Head, GM360
XIMUB6003_S Field Replaceable Unit (Main Board) GM360
X IMUB6004_S Field Replaceable Unit (Main Board) GM360
XIMUB6005_S Field Replaceable Unit (Main Board) GM360
XXXENBN4056_ Packaging, Waris Mobile
XXXHKN9402_ 12V Power Cable
XXXMDRMN4025_ Enhanced Compact Microphone
XXXRLN4774_ 3 Point Mount
XXX6864110B81_ User Guide, GM360
X = Indicates one of each is required
General Specifications
Channel Capacity
GM360 255
Power Supply 13.2Vdc (10.8 - 15.6Vdc)
Dimensions: H x W x D (mm) Height excluding knobs GM360
59mm x 179mm x 250mm
(add 9mm for Volume Knob)
Weight 2064gr
Sealing: Withstands rain testing per
MIL STD 810 C/D /E and IP54
Shock and Vibration: Protection provided via impact
resistant housing exceeding MIL STD
810-C/D /E and TIA/EIA 603
Dust and Humidity: Protection provided via environment
resistant housing exceeding MIL STD
810 C/D /E and TIA/EIA 603
1-2 MODEL CHART AND TECHNICAL SPECIFICATIONS
*Availability subject to the laws and regulations of individual countries.
Transmitter LB1 LB2 LB3
*Frequencies - Full Bandsplit LB1 29.7-36.0 MHz LB2 36.0-42.0 MHz LB2 42.0-50.0 MHz
Channel Spacing 12.5/20/25 kHz 12.5/20/25 kHz 12.5/20/25 kHz
Frequency Stability
(-30°C to +60°C, +25° Ref.) ±5.0 ppm ±5.0 ppm ±5.0 ppm
Power 25-60W 25-60W 25-60W
Modulation Limiting ±2.5 @ 12.5 kHz
±4.0 @ 20 kHz
±5.0 @ 25 kHz
±2.5 @ 12.5 kHz
±4.0 @ 20 kHz
±5.0 @ 25 kHz
±2.5 @ 12.5 kHz
±4.0 @ 20 kHz
±5.0 @ 25 kHz
FM Hum & Noise -40 dB @ 12.5kHz
-45 dB @ 20/25kHz -40 dB @ 12.5kHz
-45 dB @ 20/25kHz -40 dB @ 12.5kHz
-45 dB @ 20/25kHz
Conducted/Radiated Emission (ETS) -26 dBm -26 dBm -26 dBm
Adjacent Channel Power -60 dB @ 12.5 kHz
-70 dB @ 25 kHz -60 dB @ 12.5 kHz
-70 dB @ 25 kHz -60 dB @ 12.5 kHz
-70 dB @ 25 kHz
Audio Response (300 - 3000 Hz) +1 to -3 dB +1 to -3 dB +1 to -3 dB
Audio Distortion
@1000Hz, 60%
Rated Maximum Deviation <3% typical <3% typical <3% typical
Receiver LB1 LB2 LB3
*Frequencies - Full Bandsplit LB1 29.7-36.0 MHz LB2 36.0-42.0 MHz LB2 42.0-50.0 MHz
Channel Spacing 12.5/20/25 kHz 12.5/20/25 kHz 12.5/20/25 kHz
Sensitivity (12 dB SINAD) 0.30 µV
(0.22 µV typical) 0.30 µV
(0.22 µV typical) 0.30 µV
(0.22 µV typical)
Intermodulation (ETS) >65 dB >65 dB >65 dB
Adjacent Channel Selectivity (ETS) 65 dB @ 12.5 kHz
75 dB @ 20 kHz
80 dB @ 25 kHz
65 dB @ 12.5 kHz
75 dB @ 20 kHz
80 dB @ 25 kHz
65 dB @ 12.5 kHz
75 dB @ 20 kHz
80 dB @ 25 kHz
Spurious Rejection (ETS) 75 dB @ 12.5 kHz
80 dB @ 20/25 kHz 75 dB @ 12.5 kHz
80 dB @ 20/25 kHz 75 dB @ 12.5 kHz
80 dB @ 20/25 kHz
Rated Audio 3W Internal
13W External 3W Internal
13W External 3W Internal
13W External
Audio Distortion @ Rated Audio <3% typical <3% typical <3% typical
Hum & Noise -40 dB @ 12.5 kHz
-45 dB @ 20/25 kHz -40 dB @ 12.5 kHz
-45 dB @ 20/25 kHz -40 dB @ 12.5 kHz
-45 dB @ 20/25 kHz
Audio Response
(300 - 3000Hz @ 20/25kHz)
(300 - 2550Hz @12.5kHz) +1 to -3 dB +1 to -3 dB +1 to -3 dB
Conducted Spurious Emission (ETS) -57 dBm <1 GHz
-47 dBm >1 GHz -57 dBm <1 GHz
-47 dBm >1 GHz -57 dBm <1 GHz
-47 dBm >1 GHz
Chapter 2
THEORY OF OPERATION
1.0 Introduction
This Chapter provides a detailed theory of operation for the LowBand circuits in the radio. For details
of the theory of operation and trouble shooting for the the associated Controller circuits refer to the
Controller Section of this manual.
2-2 THEORY OF OPERATION
2.0 Low Band Receiver
2.1 Receiver Front-End
The low band receiver is bandsplit into three ranges depending on radio model, covering frequencies
from 29.7 to 36.0 MHz, 36.0 to 42.0 MHz, or 42.0 to 50.0 MHz. The circuitry of the three models is
identical except for component value differences. The receiver consists of five major blocks: front-end
bandpass filters and pre-amplifier, first mixer, high-IF and blanker switches, low-IF and receiver back-
end, and “Extender” (noise blanker). Two fixed-tuned bandpass filters perform antenna signal pre-
selection. A cross over quad diode mixer converts the signal to the high - IF of 10.7 MHz. High-side
first injection is used.
Figure 2-1 Low Band Receiver Block Diagram
Demodulator
Delay
Filter
Mixer
Fixed
Tuned Filter
RF Amp
Tuned Filter
Pin Diode
Antenna
Switch
RF Jack
Antenna
First LO
RXINJ
Recovered Audio
RSSI
IF
Second LO
Crystal
Filter
455kHz Filter
455kHz Filter
455kHz Filter
(12.5kHz)
455kHz Filter
(12.5kHz)
Switch
Switch
Switch
Switch
Limiter
IF Amp
IF Amp
Filter Bank Selection
from Synthesizer IC
Blanker
Noise
Blanking Pulses
Gate
Buffer
Enable
1st
Fixed
(25/20kHz)
BWSELECT
(U1201 Pin 48)
4-pole
(25/20kHz)
Low Band Receiver 2-3
There are two 2-pole 10.7 MHz crystal filters in the high-IF section and two switched pairs of
455 kHz ceramic filters in the low-IF section to provide the required adjacent channel selectivity.
The second IF at 455 kHz is mixed, amplified and demodulated in the IF IC. The processing of the
demodulated audio signal is performed by an audio processing IC located in the controller section.
2.2 Front-End Band-Pass Filters & Pre-Amplifier
The received signal from the radio’s antenna connector is first routed through the harmonic filter and
antenna switch, which are part of the RF power amplifier circuitry, before being applied to the
receiver 5-pole antenna filter (L1001-L1005 and associated components). This filter configuration
provides more rapid attenuation above the passband to provide better rejection of the half-IF
spurious response. A dual hot carrier diode (D1001) limits any inband signal to 0 dBm to prevent
damage to the RF pre-amplifier
The RF pre-amplifier is an SMD device (Q1001) with collector-base feedback to stabilize gain,
impedance, and intermodulation. Transistor Q1002 compares the voltage drop across resistor
R1005 with a fixed base voltage from divider R1006 and R1007, and adjusts the base current of
Q1001 as necessary to maintain its collector current constant at 25 mA. Operating voltage is from
the regulated 9.3V supply (9V3). During transmit, 9.1 volts (9T1) turns on both transistors in U1001,
turning off Q1003 and therefore Q1001-2. This protects the RF pre-amplifier from excessive
dissipation during transmit mode.
A second 5-pole fixed-tuned bandpass filter provides additional filtering of the amplified signal. This
filter configuration also provides steeper attenuation above its passband for best half-IF attenuation.
2.3 First Mixer
The signal coming from the front-end is converted to the high-IF frequency of 10.7 MHz using a
cross over quad diode mixer (U1051). The high-side injection signal (RXINJ) from the frequency
synthesizer circuitry is filtered by a 7-pole low-pass filter (L1012-14 and associated circuitry) which
removes second harmonic content from the injection signal and improves half-IF rejection. The 50-
ohm output of the first mixer is applied to the input of the high-IF circuit block.
2.4 High Intermediate Frequency (IF) and Blanker Switches
The first mixer IF output signal (IF) is applied to a diplexer network consisting of L1101, L1111 and
associated components. This network has three functions: it terminates the mixer output at
frequencies other than 10.7 MHz into 51-ohm resistor R1101; it matches the 50-ohm mixer output to
the first IF amplifier (Q1101) input; and it provides bandpass filtering at 10.7 MHz to prevent the 5.35
MHz half-IF component of the mixer output from creating a second harmonic at 10.7 MHz in Q1101,
which degrades half-IF rejection.
The IF amplifier Q1101 uses ac and dc feedback to stabilize gain and quiescent current
(approximately 28 mA). Operating voltage is from the regulated 9.3V supply (9V3). Its output is
applied to a 10.7 MHz ceramic filter FL1101 which has a 3 dB bandwidth of 270 kHz and provides a
time delay of 2.6 usec. This delay allows enough time for the “Extender” to respond to impulse noise
present at the input of Q1101 and operate the blanker switches Q1102 and Q1103, muting the IF
signal for the duration of the noise pulse. L1104 and L1105 also provide additional selectivity and
time delay. Operation of the “Extender” circuit is explained in Section 8.5 below.
When the blanker switches turn “on” to mute the IF signal, they momentarily change the impedance
of resonant circuits L1104 and L1105 from high to very low. This abrupt impedance change, if
2-4 THEORY OF OPERATION
presented to the high-Q crystal filters FL1102 and FL1103, would cause ringing of the filter
response, stretching an otherwise narrow impulse into a long and audible output waveform.
Therefore, source follower stage Q1104 isolates the blanker switches from the crystal filters,
providing a consistent source impedance via matching network L1106, L1107 and associated
components. Q1104 has unity voltage gain in this configuration.
Crystal filters FL1102 and FL1103 are 2-pole, 10.7 MHz units configured to provide an overall 4-
pole response having a 3 dB bandwidth of approximately 12 kHz. The output is amplified by second
IF amplifier Q1106 and applied to the low-IF circuitry, pin 1 of IF IC (U1103). A dual hot carrier diode
(D1101) limits the amplifier output voltage swing to prevent overdriving the IF IC at RF input levels
above -27 dBm.
2.5 Low Intermediate Frequency (IF) and Receiver Back End
The 10.7 MHz high-IF signal from the second IF amplifier feeds the IF IC (U1103) at pin1. Within the
IF IC, the 10.7 MHz high -IF signal mixes with the 10.245 MHz second local oscillator (2nd LO) to
produce the low-IF signal at 455 kHz. The 2nd LO frequency is determined by crystal Y1101. The
low -IF signal is amplified and filtered by external pairs of 455 kHz ceramic filters (FL1105 and
FL1107 for 20 kHz channel spacing, or FL1104 and FL1106 for 12.5 kHz channel spacing).
Selection of the appropriate filter pair is accomplished by U1101 and U1102, controlled by the
BWSELECT line from pin 48 of the synthesizer IC U1201. The filtered output from the ceramic filters
is applied to the limiter input pin of the IF IC (pin 14).
The IF IC contains a quadrature detector using a ceramic phase-shift element (Y1102) to provide
audio detection. Internal amplification provides an audio output level of 120 mV rms (at 60%
deviation) from U1103 pin8 (AUDIOOUT) which is fed to the ASFIC_CMP (U0221) pin 2 (part of the
Controller circuitry).
A received signal strength indicator (RSSI) signal is available at U1103 pin 5, having a dynamic
range of 70 dB. The RSSI signal is interpreted by the microprocessor (U0101 pin 63) and in addition
is available at accessory connector J0501-15.
2.6 “Extender” (Noise Blanker)
The 10.7 MHz output from the first mixer, which is present at the input of first IF amp Q1101, is also
routed to the input of the “Extender” (noise blanker) circuitry and amplified by FET Q1610. The high
input impedance of the FET stage minimizes loading of the signal in the receiver path. The output of
Q1610 is further amplified by U1601, which is a wide-bandwidth, high gain differential amplifier
(used in a single-ended configuration) incorporating an AGC gain control input. This gain block
provides linear amplification of the instantaneous amplitude of the 10.7 MHz signal at the first mixer
output. The output of U1601 is coupled to biased-detector Q1603. The bias is set so that noise
impulses of a sufficient amplitude cause Q1603 to conduct. The following stages (Q1604 through
Q1606) provide additional gain and pulse shaping which slows the turn-on and turn-off waveform
applied to IF blanker switches Q1102 and Q1103. The result is that, for each noise impulse, the IF
signal is smoothly ramped off and then on again, preventing the pulse from reaching the narrow IF
selectivity, where ringing would cause an objectionable spike at the detector of a much longer
duration than the original impulse.
If the repetition rate of noise impulses is so rapid that the noise blanker can no longer blank them
individually, as indicated by a large increase in high-frequency content at the output of Q1604, stage
Q1607 amplifies this level and turns on level detector Q1609. Its output is highly filtered into a DC
voltage level which is proportional to the repetition rate of the noise impulses, and this is applied to
the AGC input pin 5 of U1601, reducing its gain and therefore the amount of noise pulses which are
detected and processed.
Low Band Transmitter Power Amplifier (PA) 25-60 W 2-5
3.0 Low Band Transmitter Power Amplifier (PA) 25-60 W
The radio’s 60 W PA is a three-stage amplifier used to amplify the output from the VCO to the radio
transmit level. The line-up consists of three stages which utilize LDMOS technology. The first stage
is pre-driver (U1401) that is controlled by pin 4 of PCIC (U1503) via Q1504 and Q1505
(CNTLVLTG). It is followed by driver stage Q1401, and final stage utilizing two devices (Q1402 and
Q1403) connected in parallel. Q1402 and Q1403 are in direct contact with the heat sink.
To prevent damage to the final stage devices, a safety switch has been installed to prevent the
transmitter from being keyed with the cover removed.
Figure 2-2 LowBand Transmitter Block Diagram
3.1 Power Controlled Stage
The first stage (U1401) is a 20dB gain integrated circuit containing two LDMOS FET amplifier
stages. It amplifies the RF signal from the VCO (TXINJ). The output power of stage U1401 is
controlled by a DC voltage applied to pin 1 from the power control circuit (U1503 pin 4, with
transistors Q1504-5 providing current gain and level-shifting). The control voltage simultaneously
varies the bias of two FET stages within U1401. This biasing point determines the overall gain of
U1401 and therefore its output drive level to Q1401, which in turn controls the output power of the
PA.
3.2 Driver Stage
The next stage is an LDMOS device (Q1401) providing a gain of 13dB. This device requires a
positive gate bias and a quiescent current flow for proper operation. The voltage of the line
MOSBIAS_1 is set during transmit mode by the PCIC pin 24, and fed to the gate of Q1401 via
resistors R1402, R1447, R1449, R1458, R1459 and R1463, The bias voltage is tuned in the factory.
The circuitry associated with U1402-2 and Q1404 limits the variation in the output power of the
driver stage resulting from changes in the input impedance of the final stage due to changes at the
Pin Diode
Antenna
Switch RF Jack
Antenna
Harmonic
Filter
PA-Final
Stage
PA
Driver
From VCO
Controlled
Stage
BIAS
To Microprocessor
Temperature
Sense
DC AMP
PASUPLVLTG
(2 Lines)
SPI Bus
TXINJ
Sense
Current
Sense
Current
ASFIC_CMP
PCIC
INT
24
429 56
BIAS
Power
2-6 THEORY OF OPERATION
antenna of the radio. The variation in the driver’s output power is limited by controlling its DC
current. The driver’s DC current is monitored by measuring the voltage drop across current-sense
resistors R1473-6, and this voltage is compared to a reference voltage on pin 6 of U1402-2. If the
current through the sense resistors decreases, the circuit increases the bias voltage on the gate of
Q1401 via Q1404. If the current increases, then the bias voltage decreases in order to keep the
driver’s current constant. Since the current must increase with increasing control voltage, an input
path is provided to U1402-2 pin 5 from control line VCNTRL to enable this.
3.3 Final Stage
The final stage uses two LDMOS FET devices operating in parallel. Each device has its own
adjustable gate bias voltage, MOSBIAS_2 and MOSBIAS_3, obtained from D/A outputs of the
ASFIC. These bias voltages are also factory-tuned. If these transistors are replaced, the bias
voltage must be tuned using the Tuner Software. Care must be taken not to damage the device by
exceeding the maximum allowed bias voltage. The device’s drain current is drawn directly from the
radio’s DC supply voltage input, PASUPVLTG, via current-measurement resistor R1409.
A matching network combines the output of the two devices and provides a 50-ohm source for the
antenna switch and harmonic filter.
3.4 Antenna Switch
The antenna switch is operated by the 9T1 voltage source which forward biases diodes D1401 and
D1402 during transmit, causing them to appear as a low impedance. D1401 allows the RF output
from final stages Q1402 and Q1403 to be applied to the input of the low-pass harmonic filter
(L1421-3 and associated components). D1402 appears as a short circuit at the input of the receiver
(RXINJ), preventing transmitter RF power from entering the receiver. L1420 and C1456 appear as a
broadband _-wave transmission line, making the short circuit presented by D1402 appear as open
circuit at the junction of D1401 and the harmonic filter input.
During receive mode, the 9T1 voltage is not present, and D1401 and D1402 do not conduct and
appear as open circuits. This allows signals from the antenna jack to pass to the receiver input, and
disconnects the transmitter final stages from this path.
3.5 Harmonic Filter
Components L1421-L1423 and C1449-C1455 form a seven-pole elliptic low-pass filter to attenuate
harmonic energy of the transmitter to specifications level. R1411 is used to drain electrostatic
charge that might otherwise build up on the antenna. The harmonic filter also prevents high level RF
signals above the receiver passband from reaching the receiver circuits, improving spurious
response rejection.
3.6 Power Control
The transmitter uses the Power Control IC (PCIC, U1503) to control the power output of the radio. A
differential DC amplifier U1502-1 compares the voltage drop across current-measuring resistor
R1409, which is proportional to the transmitter final stage DC current, with the voltage drop across
resistor R1508 and R1535, which is proportional to the current through transistor Q1503. This
transistor is controlled by the output of the differential amplifier, which varies the transistor Q1503.
This transistor is controlled by the output of the differential amplifier, which varies the transistor
Low Band Frequency Synthesis 2-7
current until equilibrium of the two compared voltages is reached. The current through Q1503
develops a voltage across R1513 which is exactly proportional to the DC current of the final stages.
This voltage is applied to the RF IN port of the PCIC (pin 1).
The PCIC has internal digital to analog converters (DACs) which provide a reference voltage of the
control loop. The reference voltage level is programmable through the SPI line of the PCIC. This
reference voltage is proportional to the desired power setting of the transmitter, and is factory
programmed at several points across the frequency range of the transmitter to offset frequency
response variations of the transmitter’s power detector circuitry.
The PCIC provides a DC output voltage at pin 4 (INT) which is amplified and shifted in DC level by
stages Q1504 and Q1505. The 0 to 4 volt DC range at pin 4 of U1503 is translated to a 0 to 8 volt
DC range at the output of Q1505, and applied as VCNTRL to the power-adjust input pin of the first
transmitter stage U1401. This adjusts the transmitter power output to the intended value. Variations
in antenna impedance cause variations in the DC current of the final stages, and the PCIC adjusts
the control voltage above or below its nominal value to reduce power if current drain increases, or
raise power if current drain decreases.
Capacitors C1503-4 and C1525, in conjunction with resistors and integrators within the PCIC,
control the transmitter power-rise (key-up) and power-decay (de-key) characteristic to minimize
splatter into adjacent channels.
U1501 is a temperature-sensing device which monitors the circuit board temperature in the vicinity
of the transmitter circuits and provides a dc voltage to the PCIC (TEMP, pin 29) proportional to
temperature. If the DC voltage produced exceeds the set threshold in the PCIC, the transmitter
output power will be reduced so as to reduce the transmitter temperature.
3.7 TX Safety Switch
The TX Safety Switch consists of S1501, Q1506, and diode pairs D1502 and D1503 providing
protection to the Þnal stage divices Q1402 and Q1403. These Þnal stage devices can be degraded
or destroyed if the radio is keyed without the cover in place due to the lack of a good thermal path to
the chassis.
Switch S1501 is closed when the radio´s cover is screwed in place by means of the carbonized
reqion on the cover´s pressure pad making contact with the Þnger plating on the radio´s PCB. With
the cover in place, transistor Q1506 is off, back-biasing diodes D1502 and D1503, enabling proper
transmitter operation. When the cover is not in place, S1501 opens, causing Q1506 to rurn on,
pulling the cathodes of D1502 and D1503 to ground, resulting in the shorting of the transmitter´s
bias lines and control voltage.
4.0 Low Band Frequency Synthesis
The frequency synthesizer subsystem consists of the reference oscillator crystal (Y1201), the Low
Voltage Fractional-N synthesizer (LVFRAC-N, U1201), and the receive and transmit VCOs and
buffers (Q1303 through Q1308 and associated components).
4.1 Fractional-N Synthesizer
The LVFRAC-N synthesizer IC (U1201) consists of a reference oscillator, pre-scaler, a
programmable loop divider, control divider logic, a phase detector, a charge pump, an A/D converter
2-8 THEORY OF OPERATION
for low frequency digital modulation, a balance attenuator to balance the high frequency analog
modulation and low frequency digital modulation, a 13V positive voltage multiplier, a serial interface
for control, and finally a super filter for the regulated 9.3 volt supply.
Regulated 9.3 volts DC applied to the super filter input (U1201 pin 30) delivers a very low noise
output voltage of 8.3 volts DC (VSF) at pin 28. External device Q1201 allows greater current
sourcing capability. The VSF source supplies the receive and transmit VCOs and first buffer stages.
The synthesizer IC supply voltage is provided by a dedicated 5V regulator (U1250) to minimize
power supply noise.
In order to generate a high voltage to supply the phase detector (charge pump) output stage at pin
VCP (U1201 pin 47), a capacitive voltage multiplier circuit (CR1202 and C1209) generates a voltage
of 13 volts DC. This multiplier is driven by two 1.05 MHz clock signals from U1201 pins 15 and 14
(VMULT1 and VMULT2) which are 180° out of phase.
Figure 2-3 LowBand Synthesizer Block Diagram
Output LOCK (U1201-4) provides information about the lock status of the synthesizer loop. A high
level at this output indicates a stable loop. A buffered output of the 16.8 MHz reference frequency is
provided at pin 19.
The operating frequency of the synthesizer is loaded serially from the microprocessor via the data
line (DATA, U1201-7), clock line (CLK, U1201-8) and chip select line (CSX, U1201-9).
The reference oscillator circuit within U1201 uses an external 16.8 MHz crystal (Y1201). Varactor
CR1201 allows software-controlled frequency adjustment (warp) and temperature compensation of
the oscillator frequency. Warp adjustment is performed using serial data from the microprocessor.
This controls the setting of an A/D converter, with its output (WARP, pin 25) applied to CR1201.
DATA
CLK
CEX
MODIN
SFIN
XTAL1
XTAL2
WARP
PREIN
VCP
REFERENCE
OSCILLATOR
VOLTAGE
MULTIPLIER
DATA (U0101 PIN 100)
CLOCK (U0101 PIN 1)
CSX (U0101 PIN 2)
MOD IN (U0221 PIN 40)
9,3V (U641 PIN 5)
7
8
9
10
30
23
24
25
32
47
VMULT2 VMULT1
BIAS1
SFOUT
AUX3
AUX4
IADAPT
IOUT
GND
FREFOUT
LOCK 4
19
6, 22, 33, 44
43
45
3
2
28
14 15
40
FILTERED 8,3V
STEERING
LOCK (U0101 PIN 56)
PRESCALER IN
FREF (U0221 PIN 34)
39
BIAS2
41
48
5, 13, 20, 34, 36
+5V (U3211 PIN 1)
AUX1
VDD, DC5V MODOUT
U1201
LOW VOLTAGE
FRACTIONAL-N
SYNTHESIZER
AUX2
TX RF INJECTION
(1ST STAGE OF PA)
LO RF INJECTION
VOLTAGE
CONTROLLED
OSCILLATOR
LINE
2-POLE
LOOP
FILTER
1
Q1202
BUFFER
BWSELECT
VCTRL
N.C.
N.C.
Low Band Frequency Synthesis 2-9
4.2 Voltage Controlled Oscillator (VCO)
Separate VCO and buffer circuits are used for receiver injection and transmitter carrier frequency
generation. Since the receiver uses high-side injection, the receiver VCO frequency range is 10.7
MHz above the transmit VCO range. The VCO/buffers are bandsplit into three ranges depending on
radio model, covering radio operating frequencies of 29.7 to 36.0 MHz, 36.0 to 42.0 MHz, or 42.0 to
50.0 MHz. The corresponding three frequency ranges for the receive VCO are 40.4 to 46.7 MHz,
46.7 to 52.7 MHz, and 52.7 to 60.7 MHz.
The VCOs, together with Fractional-N synthesizer U1201, generate the required frequencies for
transmit and receive mode. The TRB line (U1201 pin 2) determines which VCO/buffer circuit is to be
enabled. A high level on TRB will turn on the transistors in U1378 to turn on via R1376, applying the
8.3 volt VSF source to the receiver VCO and first buffer. The second buffer in each string operates
from the 9V3 source and become active when RF is applied to their inputs.
The RF signal at the bases of the second buffers are combined and fed back to the Fractional-N
synthesizer via PRE_IN where it is compared to the reference frequency as described below in
“Synthesizer Operation”. The Fractional-N IC provides a DC steering voltage VCTRL to adjust and
maintain the VCO at the correct frequency.
With a steering voltage from 2.5V to 11V at the appropriate varactor diode (CR1302 for the RX VCO,
or CR1310 for the TX VCO), the full VCO tuning range is obtained. Each VCO uses and AGC circuit
to maintain a constant VCO output level across the frequency band. A diode (CR1306 in the receive
VCO, or CR1314 in the transmit VCO) is configured as a voltage doubler which rectifies the RF level
sampled at the VCO drain and applies a proportional negative DC voltage to the VCO gate.
Increased RF level reduces the VCO gain to compensate.
Figure 2-4 LowBand VCO/Buffer Block Diagram
STEERING
LINE
(VCTRL)
RXVCO
Q1303
Q1306
TXVCO
AGC
AGC
Q1304
Q1307 Q1308
Q1305
BUFFER BUFFER
BUFFER
BUFFER
1ST RX 2ND RX
2ND TX
1ST TX
TXINJ
RXINJ
TO Q1202
PRESCALER BUFFER
(TO 1ST MIXER)
(TO U1401 PIN16)
SFOUT
(U1201 PIN28)
U1377-8
DC SWITCH
RX (TO Q1303-5)
TX (TO Q1306-8)
(U1201 PIN2)
~
~
2-10 THEORY OF OPERATION
The VCO output is taken from the source and applied to the first buffer transistor (Q1304 receive,
Q1307 transmit). The first buffer output is further amplified by the second buffer transistor (Q1305
Rx, Q1308 Tx) before being applied to the receiver first mixer or transmitter first stage input.
In TX mode the modulation signal coming from the LVFRAC-N synthesizer IC (MODOUT, U1201 pin
41) is superimposed on the DC steering line voltage by capacitive divider C1215, C1208 and
C1212, causing modulation of the TX VCO using the same varactor as used for frequency control.
4.3 Synthesizer Operation
The complete synthesizer subsystem comprises mainly of low voltage LVFRAC-N synthesizer IC,
Reference Oscillator (crystal oscillator with temperature compensation), charge pump circuitry, loop
filter circuitry, and voltage-controlled oscillators and buffers. A sample of the VCO operating signal
PRE_IN is amplified by feedback buffer Q1202, low-pass filtered by L1205, C1222 and C1224, and
fed to U1201 pin 32 (PREIN).
The pre-scaler in the synthesizer (U1201) is basically a dual modulus pre-scaler with selectable
divider ratios. This divider ratio of the pre-scaler is controlled by the loop divider, which in turn
receives its inputs via the serial interface to the microprocessor. The output of the pre-scaler is
applied to the loop divider. The output of the loop divider is connected to the phase detector, which
compares the loop divider´s output signal with the reference signal. The reference signal is
generated by dividing down the signal of the reference oscillator, whose frequency is controlled by
Y1201.
The output signal of the phase detector is a pulsed DC signal which is routed to the charge pump.
The charge pump outputs a current at pin 43 of U1201 (I OUT). The loop filter (which consists of
R1205-6, R1208, C1212-14) transforms this current into a voltage that is applied to the varactor
diodes (CR1310 for transmit, CR1302 for receive) and alters the output frequency of the appropriate
VCO. The current can be set to a value fixed in the LVFRAC-N IC or to a value determined by the
currents flowing into BIAS 1 (U1201-40) or BIAS 2 (U1201-39). The currents are set by the value of
R1211 or R1207 respectively. The selection of the three different bias sources is done by software
programming.
To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer the
magnitude of the loop current is increased by enabling the IADAPT (U1201-45) for a certain
software programmable time (Adapt Mode). The adapt mode timer is started by a low to high
transient of the CSX line. When the synthesizer is within the lock range the current is determined
only by the resistors connected to BIAS 1, BIAS 2, or the internal current source. A settled
synthesizer loop is indicated by a high level of signal LOCK (U1201-4).
In order to modulate the PLL the two spot modulation method is utilized. Via pin 10 (MODIN) on
U1201, the audio signal is applied to both the A/D converter (low frequency path) and the balanced
attenuator (high frequency path). The A/D converter converts the low frequency analog modulating
signal into a digital code that is applied to the loop divider, thereby causing the carrier to deviate.
The balance attenuator is used to adjust the VCO’s deviation sensitivity to high frequency
modulating signals. The output of the balance attenuator is present at the MODOUT port (U1201-
41) and superimposed on the VCO steering line voltage by a divider consisting of C1215, C1208
and C1212.
Chapter 3
LOW BAND TROUBLESHOOTING CHARTS
1.0 Troubleshooting Flow Chart for Transmitter
No
DC
@ Gate of
Q1401
Voltage
?
No
Ye s
START
No or Low
TX
DC
@Drains of
Q1402 &
Q1403
Voltage
?
@ Cathode of
D1401 &
D1402
DC
Voltage
?
Drains of Q1402 &
AC
Q1403 both sine or
both distorted
Voltages @
?
Check 9T1 and
Diode Bias Circuit
Verify RF Continuity
to gates of
Q1402 & Q1403
Check circuitry
between Q1402 &
Q1403 and
Antenna Port
Check
MOSBIAS_1
Supply and
Feed Network
No
<<18V pp
Yes
No
Yes
< 1A
No
Check
Q1401
Device
Yes
CURRENT
RF @
Junction
R1413 &
DC
@ TP1402 &
TP1403
Yes
Check
MOSBIAS_2
MOSBIAS_3
and Feed Networks
Check DC/AC
Gate Circuits of
Q1402 & Q1403
Check Supply Feed
and/or PowerControl
Circuits.
No
>18V pp
Check
U1401
Device
AC
@ Gate of
Q1401
Voltage
?
Ye s
DC
@ U1401
Voltage
?
Ye s
No
Power Out
> 1A
Look for
short on
Supply Line
R1414
Voltage
?
TX
Safety
Switch
Check Pressure Pad
and/or
Switch Circuitry
3-2 Low Band TROUBLESHOOTING CHARTS
2.0 Troubleshooting Flow Chart for Receiver
(Sheet 1 of 2)
Audio
at pin 8 of
U1103
?
Audio
heard
?
Check
voltages on
U1103.
OK?
Bad SINAD
Bad 20dB Quieting
No Recovered Audio
START
Check Controller (in the case of no audio).
Or else go to “B”
Yes
No
Spray or inject 10.7MHz
into XTAL Filter FL1102.
BYe s
No
Check 2nd LO
(10.245MHz) at C1129.
LO
present
BYe s
Biasing
OK
No
No
A
Ye s
Check Q1106 bias
for faults.
Replace Q1106.
Go to B
Ye s
No
Check
circuitry
around
U1103.
Replace
U1103 if
defect.
Check circuitry around Y1101.
Replace Y1101 if defect.
Troubleshooting Flow Chart for Receiver 3-3
Troubleshooting Flow Chart for Receiver (Sheet 2 of 2)
Check for detailed mixer.
Is
9V3 present
?
RF
Signal at
pin 3 of
U1051
?
RF
Signal at
C1002
?
RF
Signal at
C1013
?
IF
Signal at
pin 2 of
U1051
?
No
RF
Signal at
C1017
?
No
No
No or
Check harmonic filters J1401
and ant.switch
Check preselector
and RF amp.
Inject RF into J1401
No
Ye s
Check RF amp (Q1001)
Stage.
Check filter between
C1017 & mixer U1051
Yes
Yes
1st
LO level OK?
Locked
?
Ye s
Check FGU
Yes
Trace IF signal
from C1036 to
Q1106. Check for
bad XTAL filter.
No
Yes IF
signal at
Q1106
collector
?
Before replacing
U1103, check
U1103 voltages.
Ye s
Check Supply Voltage
circuitry. Check U0681,
U3211 and U0641.
No
No
Yes
A
B
weak RF
3-4 Low Band TROUBLESHOOTING CHARTS
3.0 Troubleshooting Flow Chart for Synthesizer
Is
U1201 pin 2
>4.5 VDC in Tx &
<.1 VDC in Rx
?
+9.3V
at U1201
Pin 30
?
Is
U1201 Pin 47
at = 13VDC
?
Are
signals
at Pin’s 14 &
15 of U1201
?
Is
RF level at
U1201, Pin 32
-5 < x < 0 dBm
?
5V
at pin 6 of
CR1202
Is
information
from uP U0101
correct?
Is
U1377, Pin 2
<.1VDC in RX &
>4.5 VDC in TX?
(at VCO section)
Start
Visual
check of the
Board OK
?
Correct
Problem
Check 9.3V
Regulator
U0641
Is
16.8MHz
Signal at
U1201 Pin
19?
Check Y1201,
C1204,
C1206,C1207,
CR1201. & R1203
Check
R1218 Check C3319
Replace
U1201
Remove
Shorts
Is
there a short
between Pin 47 and
Pins 14 & 15 of
U1201?
Replace or
resolder
necessary
components
Are
R1205, R1206,
R1208, C1212,
C1213 & C1214
OK?
Replace
U1201
If Q1202
Feedback Amp stage is OK,
Then see VCO
troubleshooting chart
Are
Waveforms
at Pins 14 & 15
triangular
?
Do
Pins 7,8 & 9
of U1201 toggle
when channel is
changed
?
Check programming
lines between U0101
and U1201 Pins 7,8 & 9
Replace
U1201
Check uP U0101
Troubleshooting
Chart
NO
YES
NO
YES
NO
YES
NO
NO
NO
YES
YES
NO
YES
YES
NO
YES
YES
YES
NO
NO
NO
NO
YES
NO
YES
YES
5V at
U1201 pins 5,
13, 20, 24 &
36 ?
Check 5V
Regulator U1250,
L1201 & R1201
Is
16.8MHz
signal at
U1201 Pin
23?
Replace
U1201
YES
NO
NO
YES
NO
YES
Check D3201,
C3203, C3205, &
C3206
Troubleshooting Flow Chart for VCO 3-5
4.0 Troubleshooting Flow Chart for VCO
Low or no RF Signal
at U1051
Visual Check
of Board
OK?
8.5V DC
Pin 3
<,1 V DC at
U1377 Pin 2
8.5V DC AT
U1378 PIN 4
Correct
Problem
NO
YES
Make sure Synthesizer is
working correctly and
runner between U1201 Pin
3 of U1377 & U1378.
Check runner
between U1201 Pin 2
and U1377 Pin 2
Is RF
Q1304 ?
Troubleshoot
Oscillator Stage
Is RF
Check parts between
NO
NO
NO
NO
NO
YES
YES
YES
YES
YES
Low or NO RF Signal
at Input to PA
Visual Check
of Board
OK?
8.5V DC at
U1378 Pin 3
4.5V DC at
U1377 Pin 2
8.5V DC at
U1377 Pin 4
Is RF
YES
YES
YES
YES
YES
NO
NO
NO
NO
NO
U1051 and Q1305
Q1305 ?
Troubleshoot
Buffer Stage
Make sure U1377 and U1378
are working correctly.
Is RF
Q130
8 ?
NO
YES
Check parts between
U1401 and Q1308
RX - VCO TX - VCO
at U1378
available at Base of
available at Base of
Q1307 ?
available at Base of
available at Base of Q1303
Circuitry
Q1304
Circuitry
Oscillator Stage
Troubleshoot
Troubleshoot
Q1306
Circuitry
Q1307
Buffer Stage
Circuitry
3-6 Low Band TROUBLESHOOTING CHARTS
Chapter 4
LOW BAND PCB/SCHEMATICS/PARTS LISTS
1.0 Allocation of Schematics and Circuit Boards
1.1 Controller Circuits
The Low Band circuits are contained on the printed circuit board (PCB) which also contains the
Controller circuits. This Chapter shows the schematics for the Low Band circuits only, refer to the
Controller section for details of the related Controller circuits . The PCB component layouts and the
Parts Lists in this Chapter show both the Controller and Low Band circuit components.
The Low Band schematics and the related PCB and parts list are shown in the tables below.
Table 4-1 LB1 25-60W Diagrams and Parts Lists
PCB :
8486206B06 Main Board Top Side
8486206B06 Main Board Bottom Side
Page 4-5
Page 4-6
SCHEMATICS
Power Amplifier 25-60W (Sheet 1 of 2)
Power Amplifier 25-60W (Sheet 2 of 2)
Voltage Controlled Oscillator
Receiver Front End
IF (Sheet 1 of 2)
IF (Sheet 2 of 2)
Noise Blanker
FRACN
Page 4-7
Page 4-8
Page 4-9
Page 4-10
Page 4-11
Page 4-12
Page 4-13
Page 4-14
Parts List
8486206B06 Page 4-15
Controller version is T6
Table 4-2 LB2 25-60W Diagrams and Parts Lists
PCB :
8486207B05 Main Board Top Side
8486207B05 Main Board Bottom Side
Page 4-18
Page 4-19
SCHEMATICS
Power Amplifier 25-60W (Sheet 1 of 2)
Power Amplifier 25-60W (Sheet 2 of 2)
Voltage Controlled Oscillator
Receiver Front End
IF (Sheet 1 of 2)
IF (Sheet 2 of 2)
Noise Blanker
FRACN
Page 4-20
Page 4-21
Page 4-22
Page 4-23
Page 4-24
Page 4-25
Page 4-26
Page 4-27
Parts List
8486207B05 Page 4-28
Controller version is T6
4-2 Low band pcb/schematics/parts lists
Table 4-3 LB3 25-60W Diagrams and Parts Lists
PCB :
8485908z03 Main Board Top Side
8485908z03 Main Board Bottom Side
Page 4-31
Page 4-32
SCHEMATICS
Power Amplifier 25-60W (Sheet 1 of 2)
Power Amplifier 25-60W (Sheet 2 of 2)
Voltage Controlled Oscillator
Receiver Front End
IF (Sheet 1 of 2)
IF (Sheet 2 of 2)
Noise Blanker
FRACN
Page 4-33
Page 4-34
Page 4-35
Page 4-36
Page 4-37
Page 4-38
Page 4-39
Page 4-40
Parts List
8485908z03 Page 4-41
Controller version is T9
Table 4-4 LB1 25-60W Diagrams and Parts Lists
PCB :
8486206B08 Main Board Top Side
8486206B08 Main Board Bottom Side
Page 4-44
Page 4-45
SCHEMATICS
Power Amplifier 25-60W (Sheet 1 of 2)
Power Amplifier 25-60W (Sheet 2 of 2)
Voltage Controlled Oscillator
Receiver Front End
IF (Sheet 1 of 2)
IF (Sheet 2 of 2)
Noise Blanker
FRACN
Page 4-7
Page 4-8
Page 4-9
Page 4-10
Page 4-46
Page 4-47
Page 4-13
Page 4-14
Parts List
8486206B08 Page 4-48
Controller version is T11
Allocation of Schematics and Circuit Boards 4-3
Table 4-5 LB2 25-60W Diagrams and Parts Lists
PCB :
8486207B07 Main Board Top Side
8486207B07 Main Board Bottom Side
Page 4-51
Page 4-52
SCHEMATICS
Power Amplifier 25-60W (Sheet 1 of 2)
Power Amplifier 25-60W (Sheet 2 of 2)
Voltage Controlled Oscillator
Receiver Front End
IF (Sheet 1 of 2)
IF (Sheet 2 of 2)
Noise Blanker
FRACN
Page 4-20
Page 4-21
Page 4-22
Page 4-23
Page 4-46
Page 4-47
Page 4-26
Page 4-27
Parts List
8486207B07 Page 4-53
Controller version is T11
Table 4-6 LB3 25-60W Diagrams and Parts Lists
PCB :
8485908z04 Main Board Top Side
8485908z04 Main Board Bottom Side
Page 4-56
Page 4-57
SCHEMATICS
Power Amplifier 25-60W (Sheet 1 of 2)
Power Amplifier 25-60W (Sheet 2 of 2)
Voltage Controlled Oscillator
Receiver Front End
IF (Sheet 1 of 2)
IF (Sheet 2 of 2)
Noise Blanker
FRACN
Page 4-33
Page 4-34
Page 4-35
Page 4-36
Page 4-46
Page 4-47
Page 4-39
Page 4-40
Parts List
8485908z04 Page 4-58
Controller version is T11
4-4 Low band pcb/schematics/parts lists
Professional Radio
GM Series
Controller
Service Information
Issue: September 2000
ii
Computer Software Copyrights
The Motorola products described in this manual may include copyrighted Motorola computer programs stored
in semiconductor memories or other media. Laws in the United States and other countries preserve for
Motorola certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or
reproduce in any form, the copyrighted computer program. Accordingly, any copyrighted Motorola computer
programs contained in the Motorola products described in this manual may not be copied or reproduced in
any manner without the express written permission of Motorola. Furthermore, the purchase of Motorola
products shall not be deemed to grant, either directly or by implication, estoppel or otherwise, any license
under the copyrights, patents or patent applications of Motorola, except for the normal non-exclusive royalty-
free license to use that arises by operation of law in the sale of a product.
iii
Table of Contents
Chapter 1 THEORY OF OPERATION
1.0 Controller Circuits ................................................................................................1-1
1.1 Overview.........................................................................................................1-1
1.2 General...........................................................................................................1-1
1.3 Radio Power Distribution ................................................................................1-2
1.4 Electronic ON/OFF .........................................................................................1-3
1.5 Emergency .....................................................................................................1-4
1.6 Mechanical ON/OFF.......................................................................................1-4
1.7 Ignition............................................................................................................1-5
1.8 Microprocessor Clock Synthesizer .................................................................1-5
1.9 Serial Peripheral Interface (SPI).....................................................................1-5
1.10 SBEP Serial Interface.....................................................................................1-6
1.11 General Purpose Input/Output.......................................................................1-6
1.12 Normal Microprocessor Operation..................................................................1-7
1.13 FLASH Electronically Erasable Programmable Memory ................................1-8
1.14 Electrically Erasable Programmable Memory (EEPROM)..............................1-9
1.15 Static Random Access Memory (SRAM) .......................................................1-9
1.16 Universal Asynchronous Receiver Transmitter (UART) .................................1-9
2.0 Controller Board Audio and Signalling Circuits....................................................1-9
2.1 General - Audio Signalling Filter IC with Compander.....................................1-9
2.2 Transmit Audio Circuits ................................................................................1-10
2.3 Transmit Signalling Circuits..........................................................................1-12
2.4 Receive Audio Circuits .................................................................................1-14
2.5 Receive Signalling Circuits...........................................................................1-17
2.6 Voice Storage...............................................................................................1-18
iv
Chapter 2 TROUBLESHOOTING CHARTS
1.0 Controller ............................................................................................................2-1
Chapter 3 CONTROLLER SCHEMATICS
1.0 Allocation of Schematics and Circuit Boards.......................................................3-1
2.0 T2 Controller .......................................................................................................3-3
3.0 T5 Controller .....................................................................................................3-10
4.0 T6/7 Controller ..................................................................................................3-19
Chapter 1
THEORY OF OPERATION
1.0 Controller Circuits
1.1 Overview
This section provides a detailed theory of operation for the radio and its components. The main radio
is a single board design, consisting of the transmitter, receiver, and controller circuits. The main
board is designed to accept one additional option board. This may provide functions such as secure
voice/data, voice storage or signalling decoder.
A controlhead is either mounted directly or connected by an extension cable. The controlhead
contains, LED indicators, a microphone connector, buttons and dependant of the radio type, a
display and a speaker. These provide the user with interface control over the various features of the
radio.
If no controlhead is mounted directly on the front of the radio, an expansion board containing circuitry
for special applications can be mounted on the front of the radio. An additional controlhead can be
connected by an extension cable.
In addition to the power cable and antenna cable, an accessory cable can be attached to a connector
on the rear of the radio. The accessory cable provides the necessary connections for items such as
external speaker, emergency switch, foot operated PTT, and ignition sensing, etc
1.2 General
The radio controller consists of 3 main subsections:
■
■Digital Control
■
■Audio Processing
■
■Voltage Regulation.
The digital control section of the radio is based upon an open architecture controller configuration.It
consists of a microprocessor, support memory, support logic, signal MUX ICs, the On/Off circuit, and
general purpose Input/Output circuitry.
The controller uses the Motorola 68HC11FL0 microprocessor (U0101). In addition to the
microprocessor, the controller has 3 external memory devices. The 3 memory devices consist of a
32Kbyte SRAM (U0122), a 512Kbyte FLASH EEPROM (U0121), and a 16Kbyte EEPROM (U0111).
Note: From this point on the 68HC11FL0 microprocessor will be referred to as µP. References to a
controlhead will be to the controlheads with display.
1-2 THEORY OF OPERATION
Figure 1-1 Controller Block Diagram
1.3 Radio Power Distribution
The DC power distribution throughout the radio board is shown in Figure 2-1. Voltage regulation for
the controller is provided by 4 separate devices; U0651 (MC78M05) +5V, U0641 (LM2941) +9.3V,
U0611 (LM2941) SWB+ limited to 16.5V and VSTBY 5V (a combination of R0621 and VR0621). An
additional 5V regulator is located on the RF section.
The DC voltage applied to connector J0601 supplies power directly to the electronic on/off control,
RF power amplifier, 16.5V limiter, 9.3V regulator, Audio PA and 5.6V stabilization circuit. The 9.3V
regulator (U0641) supplies power to the 5V regulator (U0651) and the 6V voltage divider Q0681.
Regulator U0641 is used to generate the 9.3 volts required by some audio circuits, the RF circuitry
and power control circuitry. Input and output capacitors (C0641 and C0644 / C0645) are used to
reduce high frequency noise. R0642 / R0643 set the output voltage of the regulator. If the voltage at
pin 1 is greater than 1.3 volts the regulator output decreases and if the voltage is less than 1.3 volts
the regulator output increases. This regulator output is electronically enabled by a 0 volt signal on pin
2. Q0661, Q0641 and R0641 are used to disable the regulator when the radio is turned off.
Voltage regulation providing 5V for the digital circuitry is done by U0651. Operating voltage is from
the regulated 9.3V supply. Input and output capacitors (C0651 / C0652 and C0654 / C0655) are
used to reduce high frequency noise and provide proper operation during battery transients. Voltage
sense device U0652 or alternatively U0653 provides a reset output that goes to 0 volts if the
regulator output goes below 4.5 volts. This is used to reset the controller to prevent improper
operation. Diode D0651 prevents discharge of C0652 by negative spikes on the 9V3 voltage.
Transistor Q0681 and resistors R0681 / R0682 divide the regulated 9.3V down to about 6 volts. This
voltage supplies the 5V regulator, located on the RF section. By reducing the supply voltage of the
regulator, the power dissipation is divided between the RF section and the controller section.
External
Microphone
Internal
Microphone
External
Speaker
Internal
Speaker
SCI to
Controlhead
Audio
PA
Audio/Signalling
Architecture
To Synthesizer
Mod
Out
16.8 MHz
Reference Clock
from Synthesizer
Recovered Audio
To RF Section SPI
Digital
Architecture
µP Clock
5V
Regulator
(5VD)
RAM
EEPROM
FLASH
HC11FL0
ASFIC_CMP
Accessory &
5V
from Synthesizer
Section (5V_RF)
Connector
Controller Circuits 1-3
The voltage VSTBY, which is derived directly from the supply voltage by components R0621 and
VR0621, is used to buffer the internal RAM. C0622 allows the battery voltage to be disconnected for
a couple of seconds without losing RAM parameters. Dual diode D0621 prevents radio circuitry from
discharging this capacitor. When the supply voltage is applied to the radio, C0622 is charged via
R0621 and D0621. To avoid that the µP enters the wrong mode when the radio is switched on while
the voltage across C0622 is still too low, the regulated 5V charges C0622 via diode D0621.
Figure 2-1 DC Power Distribution Block Diagram
The voltage INT SW B+ from switching transistor Q0661 provides power to the circuit controlling the
audio PA output. The voltage INT SW B+ voltage is monitored by the µP through voltage divider
R0671 / R0672 and line BATTERY VOLTAGE. Diode VR0671 limits the divided voltage to 5.6V to
protect the µP.
Regulator U0611 is used to generate the voltage for the switched supply voltage output (SWB+) at
the accessory connector J0501 pin 13. U0611 is configured to operate as a switch with voltage and
current limit. R0611 / R0612 set the maximum output voltage to 16.5 volts. This limitation is only
active at high supply voltage levels. The regulator output is electronically enabled by a 0 volt signal
on pin 2. Q0661, Q0641 and R0641 are used to disable the regulator when the radio is turned off.
Input and output capacitors (C0603 and C0611 / C0612) are used to reduce high frequency noise.
Diode VR0601 acts as protection against transients and wrong polarity of the supply voltage.
Fuse F0401 prevents damage of the board in case the FLT A+ line is shorted at the controlhead
connector.
1.4 Electronic ON/OFF
The radio has circuitry which allows radio software and/or external triggers to turn the radio on or off
without direct user action. For example, automatic turn on when ignition is sensed and off when
ignition is off.
Q0661 is used to provide INT SW B+ to the various radio circuits and to enable the voltage
regulators via transistor Q0641. Q0661 contains an pnp and an npn transistor and acts as an
electronic on/off switch. The switch is on when the collector of the npn transistor within Q0661 is low.
When the radio is off the collector is at supply voltage level. This effectively prevents current flow
VCOBIC
FRACTN
VSTBY
5V_RF
9V3
FLT_A+
5VD
SWB+
Option Board
40 Pin Connector
PA, Driver
Antenna Switch
Controlhead
12 Pin Connector
Accessories
20 Pin Connector
J0601
13.2V
PASUPVLTG
FLT_A+
16.5V
Limiter
ON / OFF
Control
ASFIC_CMP
5.6V
Ignition
Emergency
ON/OFF
9.3V
Regulator
Audio PA
6V
Regulator 5V
Regulator
5VD
5V
Regulator 5V/
VDDA
MCU
µP, RAM,
FLASH & EEPROM
PCIC,
TX Amp
Temp Sense
RX RF Amp
IF Amp
F0401
1-4 THEORY OF OPERATION
from emitter to collector of the pnp transistor. When the radio is turned on the voltage at the base of
the npn transistor is pulled high and the pnp transistor switches on (saturation). With voltage INT
SWB+ now at supply voltage level, transistor Q0641 pulls pin 2 of the voltage regulators U0611 and
U 0641 to ground level and thereby enables their outputs.
The electronic on/off circuitry can be enabled by the microprocessor (through ASFIC CMP port
GCB2, line DC POWER ON), the emergency switch (line EMERGENCY CONTROL), the
mechanical On/Off/Volume knob on the controlhead (line ON OFF CONTROL), or the ignition sense
circuitry (line IGNITION CONTROL). If any of the 4 paths cause a low at the collector of the npn
transistor within Q0661, the electronic "ON" is engaged.
1.5 Emergency
The emergency switch (J0501 pin 9), when engaged, grounds the base of Q0662 via line
EMERGENCY CONTROL. This switches Q0662 off and resistor R0662 pulls the collector of Q0662
and the base of Q0663 to levels above 2 volts. Transistor Q0663 switches on and pulls the collector
of the npn transistor within Q0661 to ground level and thereby enables the voltage regulators via
Q0641. When the emergency switch is released R0541 pulls the base of Q0662 up to 0.6 volts. This
causes the collector of transistor Q0662 to go low (0.2V), thereby switching Q0663 off.
While the radio is switched on, the microprocessor monitors the voltage at the emergency input on
the accessory connector via pin 60 and line GP5 IN ACC9. Three different conditions are
distinguished, no emergency, emergency, and open connection to the emergency switch. If no
emergency switch is connected or the connection to the emergency switch is broken, the resistive
divider R0541 / R0512 will set the voltage to about 4.7 volts. If an emergency switch is connected, a
resistor to ground within the emergency switch will reduce the voltage on line GP5 IN ACC9 to inform
the microprocessor that the emergency switch is operational. An engaged emergency switch pulls
line GP5 IN ACC9 to ground level. Diode D0179 limits the voltage to protect the microprocessor
input.
While EMERGENCY CONTROL is low, INT SW B+ is on, the microprocessor starts execution, reads
that the emergency input is active through the voltage level of line GP5 IN ACC9, and sets the DC
POWER ON output of the ASFIC CMP pin 13 to a logic high. This high will keep Q0661 and Q0641
switched on. This operation allows a momentary press of the emergency switch to power up the
radio. When the microprocessor has finished processing the emergency press, it sets the DC
POWER ON line to a logic 0. This turns off Q0661 and the radio turns off. Notice that the
microprocessor is alerted to the emergency condition via line GP5 IN ACC9. If the radio was already
on when emergency was triggered then DC POWER ON would already be high.
1.6 Mechanical ON/OFF
This refers to the typical on/off/volume knob, located on the controlhead, and which turns the radio
on and off.
If the radio is turned off and the on/off/volume knob is pressed, line ON OFF CONTROL (J0401 pin
11) goes high and switches the radio’s voltage regulators on as long as the button is pressed. The
microprocessor is alerted through line ON OFF SENSE (U0101 pin 6) which is pulled to low by
Q0110 while the on / off / volume knob is pressed. In addition, an interrupt is generated at µP pin 96.
The µP asserts line DC POWER ON via ASFIC CMP, pin 13 high which keeps Q0661 and Q0641,
and in turn the radio, switched on. When the on/off/volume knob is released again the controlhead
informs the µP via SBEP bus about the knob release. (See SBEP Serial Interface subsection for
more details). This informs the µP to keep the radio switched on and continue with normal operation.
If the on/off/volume knob is pressed while the radio is on, the controlhead informs the µP via SBEP
bus about the knob status. (See SBEP Serial Interface subsection for more details). After a short
delay time the microprocessor switches the radio off by setting DC POWER ON to low via ASFIC
CMP pin 13.
Controller Circuits 1-5
1.7 Ignition
Ignition sense is used to prevent the radio from draining the vehicle’s battery because the engine is
not running.
When the IGNITION input (J0501 pin 10) goes above 5 volts Q0661 is turned on via line IGNITION
CONTROL. Q0661 turns on INT SW B+ and the voltage regulators by turning on Q0641 and the
microprocessor starts execution. The microprocessor is alerted through line GP6 IN ACC10. The
voltage at the IGNITION input turns Q0181 on, which pulls microprocessor pin 74 to low. If the
software detects a low state it asserts DC POWER ON via ASFIC pin 13 high which keeps Q0661
and Q0641, and in turn the radio switched on.
When the IGNITION input goes below 3 volts, Q0181 switches off and R0181 pulls microprocessor
pin 74 to high. This alerts the software to switch off the radio by setting DC POWER ON to low. The
next time the IGNITION input goes above 5 volts the above process will be repeated.
1.8 Microprocessor Clock Synthesizer
The clock source for the microprocessor system is generated by the ASFIC CMP (U0221). Upon
power-up the synthesizer IC (FRAC-N) generates a 16.8 MHz waveform that is routed from the RF
section to the ASFIC CMP pin 34. For the main board controller the ASFIC CMP uses 16.8 MHz as a
reference input clock signal for its internal synthesizer. The ASFIC CMP, in addition to audio circuitry,
has a programmable synthesizer which can generate a synthesized signal ranging from 1200Hz to
32.769MHz in 1200Hz steps.
When power is first applied, the ASFIC CMP will generate its default 3.6864MHz CMOS square
wave UP CLK (on U0221 pin 28) and this is routed to the microprocessor (U0101 pin 90). After the
microprocessor starts operation, it reprograms the ASFIC CMP clock synthesizer to a higher UP
CLK frequency (usually 7.3728 or 14.7456 MHz) and continues operation.
The ASFIC CMP may be reprogrammed to change the clock synthesizer frequencies at various
times depending on the software features that are executing. In addition, the clock frequency of the
synthesizer is changed in small amounts if there is a possibility of harmonics of this clock source
interfering with the desired radio receive frequency.
The ASFIC CMP synthesizer loop uses C0245, C0246 and R0241 to set the switching time and jitter
of the clock output. If the synthesizer cannot generate the required clock frequency it will switch back
to its default 3.6864MHz output.
Because the ASFIC CMP synthesizer and the µP system will not operate without the 16.8 MHz
reference clock it (and the voltage regulators) should be checked first in debugging the system.
The microprocessor uses XTAL Y0131 and associated components to form a Real Time Clock
(RTC). It may be used to display the time on controlheads with display or as time stamp for incoming
calls or messages. The real time clock is powered from the voltage VSTBY to keep it running while
the radio is switched off. When the radio was disconnected from it’s supply voltage, the time must be
set again.
1.9 Serial Peripheral Interface (SPI)
The µP communicates to many of the IC’s through its SPI port. This port consists of SPI TRANSMIT
DATA (MOSI) (U0101-100), SPI RECEIVE DATA (MISO) (U0101-99), SPI CLK (U0101-1) and chip
select lines going to the various ICs, connected on the SPI PORT (BUS). This BUS is a synchronous
bus, in that the timing clock signal CLK is sent while SPI data (SPI TRANSMIT DATA or SPI
RECEIVE DATA) is sent. Therefore, whenever there is activity on either SPI TRANSMIT DATA or SPI
RECEIVE DATA there should be a uniform signal on CLK. The SPI TRANSMIT DATA is used to send
serial from a µP to a device, and SPI RECEIVE DATA is used to send data from a device to a µP.
1-6 THEORY OF OPERATION
On the controller there are two ICs on the SPI BUS, ASFIC CMP (U0221-22), and EEPROM
(U0111-5). In the RF sections there are 2 ICs on the SPI BUS, the FRAC-N Synthesizer, and the
Power Control IC (PCIC). The SPI TRANSMIT DATA and CLK lines going to the RF section are
filtered by L0481 / R0481 and L0482 / R0482 to minimize noise. The chip select line CSX from
U0101 pin 2 is shared by the ASFIC CMP, FRAC-N Synthesizer and PCIC. Each of these IC‘s check
the SPI data and when the sent address information matches the IC’s address, the following data is
processed. The chip select lines for the EEPROM (EE CS), Voice Storage (VS CS), expansion board
(EXP1 CS, EXP2 CS) and option board (OPT CS) are decoded by the address decoder U0141.
When the µP needs to program any of these IC’s it brings the chip select line CSX to a logic 0 and
then sends the proper data and clock signals. The amount of data sent to the various IC’s are
different, for example the ASFIC CMP can receive up to 19 bytes (152 bits) while the PCIC can
receive up to 6 bytes (48 bits). After the data has been sent the chip select line is returned to logic 1.
The Option board interfaces are different in that the µP can also read data back from devices
connected.The timing and operation of this interface is specific to the option connected, but
generally follows the pattern:
1. an option board device generates a service request via J0551-29, line RDY and µP pin 79,
2. the main board asserts a chip select for that option board device via U0141-14, line OPT CS,
J0551-30,
3. the main board µP generates the CLK (J0551-3),
4. the main board µP writes serial data via J0551-15 and reads serial data via J0551-16 and,
5. when data transfer is complete the main board terminates the chip select and CLK activity.
1.10 SBEP Serial Interface
The SBEP serial interface allows the radio to communicate with the Customer Programming
Software (CPS), or the Universal Tuner via the Radio Interface Box (RIB). This interface connects to
the microphone connector via controlheadcontrolhead connector (J0401-8) and to the accessory
connector J0501-17 and comprises BUS+. The line is bi-directional, meaning that either the radio or
the RIB can drive the line. The microprocessor sends serial data via pin 98 and D0101 and it reads
serial data via pin 97. Whenever the microprocessor detects activity on the BUS+ line, it starts
communication.
In addition, the SBEP serial interface is used to communicate with a connected controlhead. When a
controlhead key is pressed or the volume knob is rotated, the line ON OFF CONTROL goes high.
This turns on transistor Q0110 which pulls line ON OFF SENSE and µP pin 6 to ground level. In
addition, an interrupt is generated at µP pin 96. This indicates that the controlhead wants to start
SBEP communication. The microprocessor then requests the data from the controlhead. The
controlhead starts sending and after all data has been send, the ON OFF CONTROL line goes low.
The controlheadcontrolhead ignores any data on BUS+ during SBEP communication with the CPS
or Universal Tuner.
1.11 General Purpose Input/Output
The controller provides eight general purpose lines (DIG1 through DIG8) available on the accessory
connector J0501 to interface to external options. Lines DIG IN 1,3,5,6, are inputs, DIG OUT 2 is an
output and DIG IN OUT 4,7,8 are bidirectional. The software and the hardware configuration of the
radio model define the function of each port.
DIG IN 1 can be used as external PTT input, DATA PTT input or others, set by the CPS.
The µP reads this port via pin 77 and Q0171.
Controller Circuits 1-7
DIG OUT 2 can be used as normal output or external alarm output, set by the CPS. Transistor Q0173
is controlled by the µP via ASFIC CMP pin 14.
DIG IN 3 is read by µP pin 61 via resistor R0176
DIG IN 5 can be used as normal input or emergency input, set by the CPS. The µP reads this port via
R0179 and µP pin 60. Diode D0179 limits the voltage to protect the µP input.
DIG IN 6 can be used as normal input, set by the CPS. The µP reads this port via pin 74 and Q0181.
DIG IN OUT 4,7,8 are bi-directional and use the same circuit configuration. Each port uses an output
transistor Q0177, Q0183, Q0185 controlled by µP pins 46, 47, 53. The ports are read by µP pins 75,
54, 76. To use one of the ports as input the µP must turn off the corresponding output transistor.
In addition the signals from DIG IN 1, DIG IN OUT 4 are fed to the option board connector J0551 and
the expansion board connector J0451.
1.12 Normal Microprocessor Operation
For this radio, the µP is configured to operate in one of two modes, expanded and bootstrap. In
expanded mode the µP uses external memory devices to operate, whereas in bootstrap operation
the µP uses only its internal memory. In normal operation of the radio the µP is operating in
expanded mode as described below.
In expanded mode on this radio, the µP (U0101) has access to 3 external memory devices; U0121
(FLASH EEPROM), U0122 (SRAM), U0111 (EEPROM). Also, within the µP there are 3Kbytes of
internal RAM, as well as logic to select external memory devices.
The external EEPROM (U0111) space contains the information in the radio which is customer
specific, referred to as the codeplug. This information consists of items such as: 1) what band the
radio operates in, 2) what frequencies are assigned to what channel, and 3) tuning information. (See
the particular device subsection for more details.)
The external SRAM (U0122) as well as the µP’s own internal RAM space are used for temporary
calculations required by the software during execution. All of the data stored in both of these
locations is lost when the radio powers off (See the particular device subsection for more details).
The FLASH EEPROM contains the actual Radio Operating Software. This software is common to all
open architecture radios within a given model type. For example Trunking radios may have a different
version of software in the FLASH EEPROM than a non Trunking radio (See the particular device
subsection for more details).
The µP provides an address bus of 16 address lines (ADDR 0 - ADDR 15), and a data bus of 8 data
lines (DATA 0 - DATA 7). There are also 3 control lines; CSPROG (U0101-38) to chip select U0121-
30 (FLASH EEPROM), CSGP2 (U0101-41) to chip select U0122-20 (SRAM) and PG7 R W (U0101-
4) to select whether to read or to write. The external EEPROM (U0111-1), the OPTION BOARD and
EXPANSION BOARD are selected by 3 lines of the µP using address decoder U0141. The chips
ASFIC CMP / FRAC-N / PCIC are selected by line CSX (U0101-2).
When the µP is functioning normally, the address and data lines should be toggling at CMOS logic
levels. Specifically, the logic high levels should be between 4.8 and 5.0V, and the logic low levels
should be between 0 and 0.2V. No other intermediate levels should be observed, and the rise and fall
times should be <30ns.
The low-order address lines (ADDR 0 - ADDR 7) and the data lines (DATA 0-DATA 7) should be
toggling at a high rate, e. g. , you should set your oscilloscope sweep to 1us/div. or faster to observe
individual pulses. High speed CMOS transitions should also be observed on the µP control lines.
1-8 THEORY OF OPERATION
On the µP the lines XIRQ (U0101-48), MODA LIR (U0101-58), MODB VSTPY (U0101-57) and
RESET (U0101-94) should be high at all times during normal operation. Whenever a data or address
line becomes open or shorted to an adjacent line, a common symptom is that the RESET line goes
low periodically, with the period being in the order of 20msecs. In the case of shorted lines you may
also detect the line periodically at an intermediate level, i.e. around 2.5V when 2 shorted lines
attempt to drive to opposite rails.
The MODA LIR (U0101-58) and MODB VSTPY (U0101-57) inputs to the µP must be at a logic 1 for
it to start executing correctly. After the µP starts execution it will periodically pulse these lines to
determine the desired operating mode. While the Central Processing Unit (CPU) is running, MODA
LIR is an open-drain CMOS output which goes low whenever the µP begins a new instruction (an
instruction typically requires 2-4 external bus cycles, or memory fetches). However, since it is an
open-drain output, the waveform rise assumes an exponential shape similar to an RC circuit.
There are 8 analogue to digital converter ports (A/D) on U0101. They are labelled within the device
block as PE0-PE7. These lines sense the voltage level ranging from 0 to 5V of the input line and
convert that level to a number ranging from 0 to 255 which can be read by the software to take
appropriate action.
For example U0101-67 is the battery voltage detect line. R0671 and R0672 form a resistor divider on
INT SWB+. With 30K and 10K and a voltage range of 11V to 17V, that A/D port would see 2.74V to
4.24V which would then be converted to ~140 to 217 respectively.
U0101-69 is the high reference voltage for the A/D ports on the µP. Capacitor C0101 filters the +5V
reference. If this voltage is lower than +5V the A/D readings will be incorrect. Likewise U0101-68 is
the low reference for the A/D ports. This line is normally tied to ground. If this line is not connected to
ground, the A/D readings will be incorrect.
1.13 FLASH Electronically Erasable Programmable Memory (FLASH EEPROM)
The 512KByte FLASH EEPROM (U0121) contains the radio’s operating software. This software is
common to all open architecture radios within a given model type. For example Trunking radios may
have a different version of software in the FLASH EEPROM than a non Trunking radio. This is, as
opposed to the codeplug information stored in EEPROM (U0111) which could be different from one
user to another in the same company.
In normal operating mode, this memory is only read, not written to. The memory access signals (CE,
OE and WE) are generated by the µP.
To upgrade/reprogram the FLASH software, the µP must be set in bootstrap operating mode. This is
done by pulling microprocessor pins MODA LIR (U0101-58) and MODB VSTBY (U0101-57) to low
during power up. When accessory connector pin 18 is at ground level, diode D0151 will pull both
microprocessor pins to low. The same can be done by a level of 12 volts on line ON OFF CONTROL
from the controlhead. Q0151 pulls diode D0151 and in turn both microprocessor pins to low. Diode
VR0151 prevents entering bootstrap operating mode during normal power up.
In bootstrap operating mode the µP controls the FLASH EN OE (U0121-32) input by µP pin 86. Chip
select (U0121-30) and read or write operation (U0121-7) are controlled by µP pins 38 and 4.
The FLASH device may be reprogrammed 1,000 times without issue. It is not recommended to
reprogram the FLASH device at a temperature below 0°C.
Capacitor C0121 serves to filter out any AC noise which may ride on +5V at U0121.
Controller Board Audio and Signalling Circuits 1-9
1.14 Electrically Erasable Programmable Memory (EEPROM)
The external 16 Kbyte EEPROM (U0111) contains additional radio operating parameters such as
operating frequency and signalling features, commonly know as the codeplug. It is also used to store
radio operating state parameters such as current mode and volume. This memory can be written to
in excess of 100,000 times and will retain the data when power is removed from the radio. The
memory access signals (SI, SO and SCK) are generated by the µP and chip select (CS) is generated
by address decoder U0141-15.
1.15 Static Random Access Memory (SRAM)
The SRAM (U0121) contains temporary radio calculations or parameters that can change very
frequently, and which are generated and stored by the software during its normal operation. The
information is lost when the radio is turned off.
The device allows an unlimited number of write cycles. SRAM accesses are indicated by the CS
signal U0122-20 (which comes from U0101-CSGP2) going low. U0122 is commonly referred to as
the external RAM as opposed to the internal RAM which is the 3 Kbytes of RAM which is part of the
68HC11FL0. Both RAM spaces serve the purpose. However, the internal RAM is used for the
calculated values which are accessed most often.
Capacitor C0122 serves to filter out any ac noise which may ride on +5V at U0122.
2.0 Controller Board Audio and Signalling Circuits
2.1 General - Audio Signalling Filter IC with Compander (ASFIC CMP)
The ASFIC CMP (U0221) used in the controller has 4 functions;
1) RX/TX audio shaping, i.e. filtering, amplification, attenuation
2) RX/TX signalling, PL/DPL/HST/MDC/MPT
3) Squelch detection
4) Microprocessor clock signal generation (see Microprocessor Clock Synthesizer Description).
The ASFIC CMP is programmable through the SPI BUS (U0221-20/21/22), normally receiving 19
bytes. This programming sets up various paths within the ASFIC CMP to route audio and/or
signalling signals through the appropriate filtering, gain and attenuator blocks. The ASFIC CMP also
has 6 General Control Bits GCB0-5 which are CMOS level outputs and used for NOISE BLANKER
(GCB0) in Low Band radios, EXTERNAL ALARM (GCB1) and DC POWER ON (GCB2) to switch the
voltage regulators (and the radio) on and off. GCB3 controls U0251 pin 11 to output either RX FLAT
AUDIO or RX FILTERED AUDIO on the accessory connector pin 11. GCB4 controls U0251 pin 10 to
use either the external microphone input or the voice storage playback signal. GCB5 is used to
switch the audio PA on and off.
1-10 THEORY OF OPERATION
2.2 Transmit Audio Circuits
Refer to Figure 3-1 for reference for the following sections.
Figure 3-1 Transmit Audio Paths
2.2.1 Mic/Data Input Path
The radio supports 2 distinct microphone paths known as internal (from controlhead) and external
mic (from accessory connector J0501-2) and an auxiliary path (FLAT TX AUDIO, from accessory
connector J0501-5). The microphones used for the radio require a DC biasing voltage provided by a
resistive network.
These two microphone audio input paths enter the ASFIC CMP at U0221-48 (external mic) and
U0221-46 (internal mic). Following the internal mic path; the microphone is plugged into the radio
controlhead and is connected to the controller board via J0401-9.
From here the signal is routed via R0409 and line INT MIC to R0205. R0201 and R0202 provide the
9.3VDC bias. Resistive divider R0205 / R0207 divide the input signal by 5.5 and provide input
protection for the CMOS amplifier input. R0202 and C0201 provide a 560 ohm AC path to ground
that sets the input impedance for the microphone and determines the gain based on the emitter
resistor in the microphone’s amplifier circuit.
C0204 serves as a DC blocking capacitor. The audio signal at U0221-46 (TP0221) should be
approximately 14mV for 1.5kHz or 3kHz of deviation with 12.5kHz or 25kHz channel spacing.
The external microphone signal enters the radio on accessory connector J0501 pin 2 and is routed
via line EXT MIC to R0206. R0203 and R0204 provide the 9.3VDC bias. Resistive divider R0206 /
R0208 divide the input signal by 5.5 and provide input protection for the CMOS amplifier input.
R0204 and C0202 provide a 560 ohm AC path to ground that sets the input impedance for the
microphone and determines the gain based on the emitter resistor in the microphone’s amplifier
circuit.
MIC
IN
MOD IN TO
RF
SECTION
(SYNTHESIZER)
36
44
33
40
J0501
ACCESSORY
CONNECTOR
J0401
CONTROL HEAD
CONNECTOR
MIC
EXT MIC
FLAT TX
AUDIO
42
32
5
48
46
9
2
IN OUT
OPTION
BOARD
FILTERS AND
PREEMPHASIS
HS SUMMER
SPLATTER
FILTER
LS SUMMER
LIMITER
ATTENUATOR
VCO
ATN
TX RTN
TX SND
MIC
INT
AUX
TX
ASFIC_CMP
U0221
TP0221
TP0222
MIC
EXT
J0451 J0551
18
FLAT
TX RTN
EXPANSION BOARD
31 IN/OUT
39 OUT
FROM
µP Pin3
U0211-4
Controller Board Audio and Signalling Circuits 1-11
C0254 serves as a DC blocking capacitor. Multi switch U0251 controlled by ASFIC CMP port GCB4
selects either the external microphone input signal or the voice storage playback signal for entering
the ASFIC CMP at pin 48. The audio signal at U0221-48 (TP0222) should be approximately 14mV
for 1.5kHz or 3kHz of deviation with 12.5kHz or 25kHz channel spacing.
The FLAT TX AUDIO path is used for transmitting data signals and has therefore no limiter or filters
enabled inside the ASFIC CMP. When this path is enabled via CPS and DATA PTT is asserted, any
signal on this path is directly fed to the modulator. Signals applied to this path either via accessory
connector J0501, expansion board connector J0451 or option board connector J0551 must be
filtered and set to the correct level externally or on the option board in order not to exceed the
maximum specified transmit deviation and transmitted power in the adjacent channels. The
attenuator inside the ASFIC CMP changes the FM deviation of the data signal according to the
channel spacing of the active transmit channel.
The FLAT TX AUDIO signal from accessory connector J0501-5 is fed to the ASFIC CMP (U0221)
pin42 through C0541 and line FLAT TX RTN, switch U0251 and buffer U0211-4. When the radio
switches from receive to transmit mode the µP opens switch U0251 for a short period to prevent that
any applied signal can cause a transmit frequency offset. Buffer U0211-4 sets the correct DC level
and ensures a short settle period when the radio is switched on. Inside the ASFIC CMP the signal is
routed directly to the attenuator, which sets the FM deviation according to the channel spacing of the
active transmit channel and emerges from the ASFIC CMP at U0221-40, at which point it is routed to
the RF section.
The ASFIC has an internal AGC that can control the gain in the mic audio path. The AGC can be
disabled / enabled by the µP. Another feature that can be enabled or disabled in the ASFIC is the
VOX. This circuit, along with the capacitor at U0221-7, provides a DC voltage that can allow the µP to
detect microphone audio. The ASFIC can also be programmed to route the microphone audio to the
speaker for public address operation.
2.2.2 PTT Sensing and TX Audio Processing
Microphone PTT coming from the controlhead is sent via SBEP bus to the microprocessor. An
external PTT can be generated by grounding pin 3 on the accessory connector if this input is
programmed for PTT by the CPS. When microphone PTT is sensed, the µP will always configure the
ASFIC CMP for the "internal" mic audio path, and external PTT will result in the external mic audio
path being selected.
Inside the ASFIC CMP, the mic audio is filtered to eliminate frequency components outside the 300-
3000Hz voice band, and pre-emphasized if pre-emphasis is enabled. The signal is then limited to
prevent the transmitter from over deviating. The limited mic audio is then routed through a summer,
which is used to add in signalling data, and then to a splatter filter to eliminate high frequency
spectral components that could be generated by the limiter. The audio is then routed to an
attenuator, which is tuned in the factory or the field to set the proper amount of FM deviation. The TX
audio emerges from the ASFIC CMP at U0221-40 MOD IN, at which point it is routed to the RF
section.
Dependent on the radio model, input pin 3 on the accessory connector can be programmed for DATA
PTT by the CPS. When DATA PTT is sensed, the µP will always configure the ASFIC CMP for the flat
TX audio path. Limiter and any filtering will be disabled. The signal is routed directly to the attenuator,
which sets the FM deviation according to the channel spacing of the active transmit channel and
emerges from the ASFIC CMP at U0221-40, at which point it is routed to the RF section.
2.2.3 TX Secure Audio (optional)
The audio follows the normal transmit audio processing until it emerges from the ASFIC CMP TX
SND pin (U0221-44), which is fed to the Secure board residing at option connector J0551-33. The
1-12 THEORY OF OPERATION
Secure board contains circuitry to amplify, encrypt, and filter the audio. The encrypted signal is then
fed back from J0551-32 to the ASFIC CMP TX RTN input (U0221-36). The signal level at this pin
should be about 65mVrms. The signal is then routed through the TX path in the ASFIC CMP and
emerges at MOD IN pin 40.
2.2.4 Option Board Transmit Audio
The audio follows the normal transmit audio processing until it emerges from the ASFIC CMP TX
SND pin (U0221-44), which is fed to the option board residing at option connector J0551-33. The
option board contains circuitry to process the audio. The processed signal is then fed back from
J0551-32 to the ASFIC CMP TX RTN input (U0221-36). The signal level at this pin should be about
65mVrms. The signal is then routed through the TX path in the ASFIC CMP and emerges at MOD IN
pin 40.
2.3 Transmit Signalling Circuits
Refer to Figure 4-1 for reference for the following sections.
Figure 4-1 Transmit Signalling Paths
From a hardware point of view, there are 3 types of signalling:
1) sub-audible data (PL / DPL / Connect Tone) that gets summed with transmit voice or signalling,
2) DTMF data for telephone communication in trunked and conventional systems, and
3) Audible signalling including Select 5, MPT-1327, MDC, High speed Trunking.
NOTE: All three types are supported by the hardware while the radio software determines which
signalling type is available.
2.3.1 Sub-audible Data (PL/DPL)
Sub-audible data implies signalling whose bandwidth is below 300Hz. PL and DPL waveforms are
used for conventional operation and connect tones for trunked voice channel operation. The trunking
connect tone is simply a PL tone at a higher deviation level than PL in a conventional system.
Although it is referred to as "sub-audible data," the actual frequency spectrum of these waveforms
19
18
40
MOD IN
TO RF
SECTION
(SYNTHESIZER)
80
44 HIGH SPEED
CLOCK IN
(HSIO)
LOW SPEED
CLOCK IN
(LSIO)
ASFIC_CMP U0221
MICRO
CONTROLLER
U0101
HS
SUMMER
5-3-2 STATE
ENCODER
DTMF
ENCODER
SPLATTER
FILTER
PL
ENCODER LS
SUMMER
ATTENUATOR
85
82
SPI
BUS
Controller Board Audio and Signalling Circuits 1-13
may be as high as 250 Hz, which is audible to the human ear. However, the radio receiver filters out
any audio below 300Hz, so these tones are never heard in the actual system.
Only one type of sub-audible data can be generated by U0221 (ASFIC CMP) at any one time. The
process is as follows, using the SPI BUS, the µP programs the ASFIC CMP to set up the proper low-
speed data deviation and select the PL or DPL filters. The µP then generates a square wave which
strobes the ASFIC PL / DPL encode input LSIO U0221-18 at twelve times the desired data rate. For
example, for a PL frequency of 103Hz, the frequency of the square wave would be 1236Hz.
This drives a tone generator inside U0221 which generates a staircase approximation to a PL sine
wave or DPL data pattern. This internal waveform is then low-pass filtered and summed with voice or
data. The resulting summed waveform then appears on U0221-40 (MOD IN), where it is sent to the
RF board as previously described for transmit audio. A trunking connect tone would be generated in
the same manner as a PL tone.
2.3.2 High Speed Data
High speed data refers to the 3600 baud data waveforms, known as Inbound Signalling Words
(ISWs) used in a trunking system for high speed communication between the central controller and
the radio. To generate an ISW, the µP first programs the ASFIC CMP (U0221) to the proper filter and
gain settings. It then begins strobing U0221-19 (HSIO) with a pulse when the data is supposed to
change states. U0221’s 5-3-2 State Encoder (which is in a 2-state mode) is then fed to the post-
limiter summer block and then the splatter filter. From that point it is routed through the modulation
attenuators and then out of the ASFIC CMP to the RF board. MPT 1327 and MDC are generated in
much the same way as Trunking ISW. However, in some cases these signals may also pass through
a data pre-emphasis block in the ASFIC CMP. Also these signalling schemes are based on sending
a combination of 1200 Hz and 1800 Hz tones only. Microphone audio is muted during High Speed
Data signalling.
2.3.3 Dual Tone Multiple Frequency (DTMF) Data
DTMF data is a dual tone waveform used during phone interconnect operation. It is the same type of
tones which are heard when using a "Touch Tone" telephone.
There are seven frequencies, with four in the low group (697, 770, 852, 941Hz) and three in the high
group (1209, 1336, 1477Hz).
The high-group tone is generated by the µP (U0101-44) strobing U0221-19 at six times the tone
frequency for tones less than 1440Hz or twice the frequency for tones greater than 1440Hz. The low
group tone is generated by the ASFIC CMP, controlled by the µP via SPI bus. Inside U0221 the low-
group and high-group tones are summed (with the amplitude of the high group tone being
approximately 2 dB greater than that of the low group tone) and then pre-emphasized before being
routed to the summer and splatter filter. The DTMF waveform then follows the same path as was
described for high-speed data.
1-14 THEORY OF OPERATION
2.4 Receive Audio Circuits
Refer to Figure5-5 for reference for the following sections.
Figure 4-1 Receive Audio Paths
2.4.1 Squelch Detect
The radio’s RF circuits are constantly producing an output at the discriminator (IF IC). This signal
(DISC AUDIO) is routed to the ASFIC CMP’s squelch detect circuitry input DISC (U0221-2). All of
the squelch detect circuitry is contained within the ASFIC CMP. Therefore from a user’s point of view,
DISC AUDIO enters the ASFIC CMP, and the ASFIC CMP produces two CMOS logic outputs based
on the result. They are CH ACT (U0221-16) and SQ DET (U0221-17).
The squelch signal entering the ASFIC CMP is amplified, filtered, attenuated, and rectified. It is then
sent to a comparator to produce an active high signal on CH ACT. A squelch tail circuit is used to
produce SQ DET (U0221-17) from CH ACT. The state of CH ACT and SQ DET is high (logic 1) when
carrier is detected, otherwise low (logic 0).
CH ACT is routed to the µP pin 84 while SQ DET is routed to the µP pin 83.
SQ DET is used to determine all audio mute / unmute decisions except for Conventional Scan. In
this case CH ACT is a pre-indicator as it occurs slightly faster than SQ DET.
FLT/FLAT RX AUDIO
J0501
11
16
1EXTERNAL
SPEAKER
INTERNAL
SPEAKER
ACCESSORY
CONNECTOR
CONTROLHEAD
CONNECTOR
HANDSET
AUDIO
7
2
3
J0401
INT
SPKR-
SPKR +
SPKR -
1
9
2
J0551
4110
INT
SPKR+
4
6
DISC
ASFIC_CMP
U0221
AUDIO
PA
U0271
IN
OPTION
BOARD
IN
OUT VOLUME
ATTEN.
FILTER AND
DEEMPHASIS
17
MICRO
CONTROLLER
U0101
80
FROM
RF
SECTION
(IF IC) LIMITER, RECTIFIER
FILTER, COMPARATOR
SQ DET
SQUELCH
CIRCUIT
16
PL FILTER
LIMITER
CH ACT
AUX RX
43
18
LS IO
U IO AUDIO
83
84
39
URX OUT
17
J0451
EXPANSION
BOARD
DISC
AUDIO
34
28
35
85
IN
7
Controller Board Audio and Signalling Circuits 1-15
2.4.2 Audio Processing and Digital Volume Control
The receiver audio signal enters the controller section from the IF IC on DISC AUDIO. The signal is
DC coupled by R0228 and enters the ASFIC CMP via the DISC pin U0221-2.
Inside the ASFIC CMP, the signal goes through 2 paths in parallel, the audio path and the PL/DPL
path.
The audio path has a programmable amplifier, whose setting is based on the channel bandwidth
being received, then a LPF filter to remove any frequency components above 3000Hz and then an
HPF to strip off any sub-audible data below 300Hz. Next, the recovered audio passes through a de-
emphasis filter if it is enabled (to compensate for Pre-emphasis which is used to reduce the effects of
FM noise). The IC then passes the audio through the 8-bit programmable attenuator whose level is
set depending on the value of the volume control. Finally the filtered audio signal passes through an
output buffer within the ASFIC CMP. The audio signal exits the ASFIC CMP at pin AUDIO (U0221-
41).
The µP programs the attenuator, using the SPI BUS, based on the volume setting. The minimum /
maximum settings of the attenuator are set by codeplug parameters.
Since sub-audible signalling is summed with voice information on transmit, it must be separated from
the voice information before processing. Any sub-audible signalling enters the ASFIC CMP from the
IF IC at DISC U0221-2. Once inside it goes through the PL/DPL path. The signal first passes through
one of 2 low pass filters, either PL low pass filter or DPL/LST low pass filter. Either signal is then
filtered and goes through a limiter and exits the ASFIC CMP at LSIO (U0221-18). At this point the
signal will appear as a square wave version of the sub-audible signal which the radio received. The
microprocessor U0101-80 will decode the signal directly to determine if it is the tone / code which is
currently active on that mode.
2.4.3 Audio Amplification Speaker (+) Speaker (-)
The output of the ASFIC CMP’s digital volume pot, U0221-41 is routed through dc blocking capacitor
C0265 to a buffer formed by U0211-1. Resistors R0265 and R0268 set the correct input level to the
audio PA (U0271). This is necessary because the gain of the audio PA is 46 dB, and the ASFIC CMP
output is capable of overdriving the PA unless the maximum volume is limited. Resistor R0267 and
capacitor C0267 increase frequency components below 350 Hz.
The audio then passes through R0269 and C0272 which provides AC coupling and low frequency
roll-off. C0273 provides high frequency roll-off as the audio signal is routed to pins 1 and 9 of the
audio power amplifier U0271.
The audio power amplifier has one inverted and one non-inverted output that produces the
differential audio output SPK+ / SPK- (U0271-4/6). The inputs for each of these amplifiers are pins 1
and 9 respectively; these inputs are both tied to the received audio. The audio PA’s DC biases are
not activated until the audio PA is enabled at pin 8.
The audio PA is enabled via the ASFIC CMP (U0221-38). When the base of Q0271 is low, the
transistor is off and U0271-8 is high, using pull up resistor R0273, and the Audio PA is ON. The
voltage at U0273-8 must be above 8.5VDC to properly enable the device. If the voltage is between
3.3 and 6.4V, the device will be active but has its input (U0273-1/9) off. This is a mute condition which
is used to prevent an audio pop when the PA is enabled.
The SPK+ and SPK- outputs of the audio PA have a DC bias which varies proportionately with FLT
A+ (U0271-7). FLT A+ of 11V yields a DC offset of 5V, and FLT A+ of 17V yields a DC offset of 8.5V.
If either of these lines is shorted to ground, it is possible that the audio PA will be damaged. SPK+
and SPK- are routed to the accessory connector (J0501-16 and 1) and to the controlhead (connector
J0401-2 and 3).
1-16 THEORY OF OPERATION
2.4.4 Handset Audio
Certain hand held accessories have a speaker within them which require a different voltage level
than that provided by U0271. For those devices HANDSET AUDIO is available at controlhead
connector J0401-7.
The received audio from the output of the ASFIC CMP’s digital volume attenuator and buffered by
U0211-1 is also routed to U0211-3 pin 9 where it is amplified 20 dB; this is set by the 10k/100k
combination of R0261 and R0262. This signal is routed from the output of the op amp U0211-3 pin 8
to J0401-7. The controlhead sends this signal directly out to the microphone jack. The maximum
value of this output is 6.6Vp-p.
2.4.5 Filtered Audio and Flat Audio
The ASFIC CMP has an audio whose output at U0221-39 has been filtered and de-emphasized, but
has not gone through the digital volume attenuator. From ASFIC CMP U0221-39 the signal is routed
via R0251 through gate U0251-12 and AC coupled to U0211-2. The gate controlled by ASFIC CMP
port GCB3 (U0221-35) selects between the filtered audio signal from the ASFIC CMP pin 39
(URXOUT) or the unfiltered (flat) audio signal from the ASFIC CMP pin 10 (UIO). R0251 and R0253
determine the gain of op-amp U0211-2 for the filtered audio while R0252 and R0253 determine the
gain for the flat Audio. The output of U0253-7 is then routed to J0501-11 via dc blocking capacitor
C0542 and R0531. Note that any volume adjustment of the signal on this path must be done by the
accessory
2.4.6 RX Secure Audio (optional)
Discriminator audio, which is now encrypted audio, follows the normal receive audio processing until
it emerges from the ASFIC CMP UIO pin (U0221-10), which is fed to the Secure board residing at
option connector J0551-35. On the Secure board, the encrypted signal is converted back to normal
audio format, and then fed back through (J0551-34) to AUX RX of the ASFIC CMP (U0221-43).
From then on it follows a path identical to conventional receive audio, where it is filtered (0.3 - 3kHz)
and de-emphasized. The signal URX SND from the ASFIC CMP (U0221-39), also routed to option
connector J0551-28, is not used for the Secure board but for other option boards.
2.4.7 Option Board Receive Audio
Unfiltered audio from the ASFIC CMP pin UIO (U0221-10) enters the option board at connector
J0551-35. Filtered audio from the ASFIC CMP pin URXOUT (U0221-39) enters the option board at
connector J0551-28. On the option board, the signal may be processed, and then fed back through
J0551-34 to AUX RX of the ASFIC CMP (U0221-43). From then on it follows a path identical to
conventional receive audio, where it may be filtered (0.3 - 3kHz) and de-emphasized.
Controller Board Audio and Signalling Circuits 1-17
2.5 RECEIVE SIGNALLING CIRCUITS
Refer to Figure 5-6 for reference for the following sections.
Figure 4-2 Receive Signalling Paths
2.5.1 Sub-audible (PL/DPL) and High Speed Data Decoder
The ASFIC CMP (U0221) is used to filter and limit all received data. The data enters the ASFIC CMP
at input DISC (U0221-2). Inside U0221 the data is filtered according to data type (HS or LS), then it
is limited to a 0-5V digital level. The MDC and trunking high speed data appear at U0221-19, where
it connects to the µP U0101-82
The low speed limited data output (PL, DPL, and trunking LS) appears at U0221-18, where it
connects to the µP U0101-80.
The low speed data is read by the µP at twice the frequency of the sampling waveform; a latch
configuration in the ASFIC CMP stores one bit every clock cycle. The external capacitors C0236, and
C0244 set the low frequency pole for a zero crossings detector in the limiters for PL and HS data.
The hysterisis of these limiters is programmed based on the type of received data.
2.5.2 Alert Tone Circuits
When the software determines that it needs to give the operator an audible feedback (for a good key
press, or for a bad key press), or radio status (trunked system busy, phone call, circuit failures), it
sends an alert tone to the speaker. It does so by sending SPI BUS data to U0221 which sets up the
audio path to the speaker for alert tones. The alert tone itself can be generated in one of two ways:
internally by the ASFIC CMP, or externally using the µP and the ASFIC CMP.
The allowable internal alert tones are 304, 608, 911, and 1823Hz. In this case a code contained
within the SPI BUS load to the ASFIC CMP sets up the path and determines the tone frequency, and
at what volume level to generate the tone. (It does not have to be related to the voice volume setting).
For external alert tones, the µP can generate any tone within the 100-3000Hz audio band. This is
accomplished by the µP generating a square wave which enters the ASFIC CMP at U0221-19.
Inside the ASFIC CMP this signal is routed to the alert tone generator
The output of the generator is summed into the audio chain just after the RX audio de-emphasis
block. Inside U0221 the tone is amplified and filtered, then passed through the 8-bit digital volume
attenuator, which is typically loaded with a special value for alert tone audio. The tone exits at U0221-
41 and is routed to the audio PA like receive audio
DET AUDIO
DISCRIMINATOR AUDIO
FROM RF SECTION
(IF IC)
19
18
25
2
82
80
DISC
PLCAP2
LSIO
HSIO
DATA FILTER
AND DEEMPHASIS LIMITER
FILTER LIMITER
ASFIC_CMP
U0221
MICRO
CONTROLLER
U0101
85
44
8
PLCAP
1-18 THEORY OF OPERATION
2.6 Voice Storage (optional)
The Voice Storage (VS) option can be used to store audio signals coming from the receiver or from
the microphone. Any stored audio signal can be played back over the radio’s speaker or sent out via
the radio’s transmitter.
The Voice Storage option can by placed on the controller section or on an additional option board
which resides on option board connector J0551. Voice Storage IC U0301 provides all required
functionality and is powered from 3.3 volts regulator U0351 which is powered from the regulated 5
volts. Dual shottky diode D0301 reduces the supply voltage for U0301 to 3 volts. The microprocessor
controls U0301 via SPI bus lines CLK (U0301-8), DATA (U0301-10) and MISO (U0301-11). To
transfer data, the µP first selects the U0301 via address decoder U0141, line VS CS and U0301 pin
9. Then the µP sends data through line DATA and receives data through line MISO. Pin 2 (RAC) of
U0301 indicates the end of a message row by a low state for 12.5 ms and connects to µP pin 52. A
low at pin 5 (INT), which is connected to µP pin 55 indicates that the Voice Storage IC requires
service from the µP.
Audio, either from the radio’s receiver or from one of the microphone inputs, emerges the ASFIC
CMP (U0221) at pin 39, is buffered by op-amp U0341-1 and enters the Voice Storage IC U0301 at
pin 25. During playback, the stored audio emerges U0301 at pin 20. To transmit the audio signal it is
fed through resistive divider R0344 / R0345 and line VS MIC to input selector IC U0251. When this
path is selected by the µP via ASFIC CMP port GCB 4, the audio signal enters the ASFIC CMP at
pin 48 and is processed like normal transmit audio. To play the stored audio over the radio’s speaker,
the audio from U0301 pin 20 is buffered by op-amp U0341-2 and fed via switch U0342 and line FLAT
RX SND to ASFIC CMP pin 10 (UIO). In this case, this ASFIC CMP pin is programmed as input and
feeds the audio signal through the normal receiver audio path to the speaker or handset. Switch
U0342 is controlled by the µP via ASFIC CMP port GCB 4 and feeds the stored audio only to the
ASFIC CMP port UIO when it is programmed as input.
Chapter 2
TROUBLESHOOTING CHARTS
1.0 Controller Troubleshooting Chart
Controller Check
Power Up
Alert Tone
OK?
Speaker &
Control
Head OK?
U0101
EXTAL=
7.3728 MHz/
14.7456
MHz?
BUS+
activity when
volume knob
rotated?
MCU is OK
Not able to
program
RF Board ICs
Before replacing
MCU, check SPI
clock, SPI data,
and RF IC select
Replace
Speaker / Con-
trol Head
U0221 Pin 34 =
16.8 MHz?
Check
FGU
Reprogram the
correct data. &
Check ASFIC
and MCU
Check Control
Head and MCU
(U0101, U0121,
U0122, U0111)
Press PTT. No
RF Output Pow-
er.
Red LED
lights up?
Check
Control
Head
Check
FGU &
Transmitter
Audio
at Pin 41
U0221?
Enable External PTT
with CPS
External PTT en-
abled with CPS?
Radio could
not PTT
externally
DC
at as-
signed Acc.
Con. Pin
DC chang-
es?
Check Components
between U0221 and
U0271
Check Con-
nection to uP
port
PTT
NO
YES
NO
YES YES
YES
YES
NO
NO
YES
NO
YES
NO
YES
NO
YES
EXT
PTT
RX
AUDIO
Check
Accessories
J0501
Audio at Pin
16 &
Pin 1
Check Spk.
Flex Connec-
tion & Control
Audio
at Audio PA
(U0271)
input
Check AS-
FIC U0221
Check
Audio PA
(U0271)
Check Re-
ceiver &
IF IC
Audio at
Pin 2
U0221?
NO
NO
NO
YES
YES
NO
YES
NO
Before troubleshooting the controller section ac-
cording to this chart please check the following:
1. Check tuning and CPS settings
2. Check if Alert Tones are enabled
3. Check if Control Head is OK
4. Check board visually
9.3V
DC at Pin 5
of U0641?
YES
NO
5V DC at
Pin OUT of
U0651?
YES
NO
Check U0641, Q0641,
Q0661, D0660 &
D0661
Check U0651, D0651,
D0621
2-2 TROUBLESHOOTING CHARTS
Chapter 3
CONTROLLER SCHEMATICS / PARTS LIST
1.0 Allocation of Schematics and Circuit Boards
1.1 Controller Circuits
This Chapter shows the Schematics and the the Parts Lists for the Controller circuits.
1.2 Voice Storage Facility
The Voice Storage is fitted on all MPT radios GM640/660/1280 and on GM380 as standard.
The schematics, component layout and parts list for these circuits are shown in this chapter.
The Voice Storage schematic is shown in Tables below.
.
Table 3-1 Controller T2 Diagrams and Parts Lists
Controller T2 used on PCB :
8486172B04 VHF, 1-25W
SCHEMATICS
Controller Overall
Supply Voltage
Audio
I/O
Microprocessor
Page 3-3
Page 3-4
Page 3-5
Page 3-6
Page 3-7
Parts List
Controller T2 Page 3-8
Table 3-2 Controller T5 Diagrams and Parts Lists
Controller T5 used on PCB :
8486172B06 VHF, 1-25W
SCHEMATICS
Controller Overall
Supply Voltage
Audio
I/O
Microprocessor
Voice Storage (if fitted)
Page 3-10
Page 3-11
Page 3-12
Page 3-13
Page 3-14
Page 3-15
Parts List
Controller T5 Page 3-16
3-2 Controller schematics / parts list
.
Table 3-3 Controller T6 Diagrams and Parts Lists
Controller T6/T7 used on PCB :
T6 on 8486206B06 LB1, 60W
T6 on 8486140B12 VHF, 25-45W
T6 on 8480643z06 UHF B1, 25-40W
T7 on 8486172B07 VHF, 1-25W
T7 on 8485670z02 UHF B1, 1-25W
SCHEMATICS
Controller Overall
Supply Voltage
Audio
I/O T6
I/O T7
Microprocessor
Voice Storage (if fitted)
Page 3-19
Page 3-20
Page 3-21
Page 3-22
Page 3-23
Page 3-24
Page 3-25
Parts List
Controller T6/T7 Page 3-26

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