GX20 1850 7_System_370_Reference_Summary_Feb89 7 System 370 Reference Summary Feb89
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System/370
Reference Summary
GX20-1B50-7
File No. 8370/4300-01
IBM Corporation. Product Publications. Dept . B97.
PO Box 950, Poughkeepsie, NY, USA 12602
Eighth Edition (February 19891
This major revision obsoletes and replaces GX20-1850-6.
Additions include information about new printer, DASO, and
tape devices and command codes. Minor technical and editorial
changes have been made.
References in this publication to IBM products, programs, or
services do not imply that IBM intends to make these available
in all countries in which IBM operates. Any reference to an IBM
program product in this publication is not intended to state or
imply that only IBM's program product may be used. Any
functionally equivalent program may be used instead.
Requests for copies of this and other IBM publications should be
made to your IBM representative or to the IBM branch office
serving your locality.
Please direct any comments on the contents of this publication
to IBM Corporation, Product Publications, Department B97, PO
Box 950, Poughkeepsie, NY, USA 12602. IBM may use or
distribute whatever information you supply in any way it
believes appropriate without incurring any obligation to you.
© Copyright International Business Machines Corporation
1986, 1989. All rights reserved.
PREFACE
This publication is intended primarily for use by System/370
assembler language application programmers. It contains basic
machine information summarized from the IBM System/370
Principles of Operation, GA22-7000, about System/370 Models
115 through 195; the 3031, 3032, 3033, 3081, 3083, 3084,
3090, and ES/3090™ Processor Complexes; the 4321, 4331,
4341, 4361, 4381, and ES/4381 ™ Processors; and the
ES/9370™ Information System. It also contains frequently used
information from IBM Enterprise Systems Architecture/370™
and System/370 Vector Operations, SA22-7125, and the
OS/VS, DOS/VSE, and VM/370 assembler language manual,
GC33-4010, command codes for various 1/0 devices, and a
multicode translation table. This publication will be updated
from time to time. However, the above publications and others
cited in this publication are the authoritative reference sources
and will be first to reflect changes.
The floating-point instructions, as well as the instructions listed
below, are not provided on every model. For instructions that
are provided on a particular model, either as standard or
optional features on that model, the user should refer to the
appropriate System Library publication.
Facility
Instructions
Branch and save
Channel-set switching
Conditional swapping
CPU timer and clock
comparator
Direct control
Dual address space
BAS, BASA
CONCS, DISCS
CS, CDS
SCKC,SPT, STCKC, STPT
Extended facility
Extended-precision
floating point
Move inverse
Multiprocessing
PSW-key handling
Storage-key-instruction
extensions
Suspend and resume
Test block
Translation
Vector
ROD, WRD
EPAR, ESAR, IAC, IVSK, LASP,
MVCP, MVCS, MVCK, PC, PT,
SAC,SSAR
IPTE, TPROT
AXR, LRDR, LRER, MXR, MXDR,
MXD, SXR
MVCIN
SPX, SIGP, STAP, STPX
IPK, SPKA
ISKE, RABE, SSKE
RIO
TB
LRA, PTLB, RRB, STNSM, STOSM
(All instructions with mnemonics
that start with "V")
The operation of the following 1/0 instructions may differ
depending on the model, the designated channel, and the
installed facilities: CLRCH, CLRIO, HOV, and SIOF. To
determine the operation, the user should refer to the appropriate
System Library publications.
ES/3090, Enterprise Systems Architecture/370, ES/9370, and
ESl4381 are trademarks of the International Business Machines
Corporation.
For information about System/370 extended architecture, refer
to IBM System/370 Extended Architecture Principles of
Operation, SA22-7085, IBM System/370 Extended Architecture
Interpretive Execution, SA22-7095, and IBM System/370
Extended Architecture Reference Summary, GX20-0157.
For information about Enterprise Systems Architecture/370,
refer to the IBM Enterprise Systems Architecture/370 Principles
of Operation, SA22-7200, and IBM Enterprise Systems
Architecture/370 Reference Summary, GX20-0406.
CONTENTS
Machine Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . .
Machine Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
By Mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
By Operation Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembler Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mnemonic Instructions . . . . . . . . . . . . . . . . . . . . .
CNOP Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fixed Storage Locations . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Vector-Status Register ............................
Program-Status Word (EC Mode) . . . . . . . . . . . . . . . . . . . . .
Program-Status Word (BC Mode) . . . . . . . . . . . . . . . . . . . . .
External-Interruption Codes . . . . . . . . . . . . . . . . . . . . . . . . .
Program-Interruption Codes . . . . . . . . . . . . . . . . . . . . . . . .
Exception-Extension Code . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Address Translation . . . . . . . . . . . . . . . . . . . . . . .
Dynamic-Address-Translation Format . . . . . . . . . . . . . . . .
Segment-Table Entry ............................
Page-Table Entry (4K) ...........................
Page-Table Entry (2K) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Translation-Exception Identification . . . . . . . . . . . . . . . . . . .
Dual-Address-Space Control . . . . . . . . . . . . . . . . . . . . . . . .
Program-Call Number. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linkage-Table Entry .............................
Entry-Table Entry ..............................
ASN-First-Table Entry ...........................
ASN-Second-Table Entry .........................
Trace-Table-Entry Header ........................
Machine-Check Interruption Code . . . . . . . . . . . . . . . . . . . .
External-Damage Code . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel-Address Word . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel-Command Word . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel-Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limited Channel Logout. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1/0 Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Command-Code Assignments . . . . . . . . . . . . . .
Standard Meanings of Bits of First Sense Byte . . . . . . . . . .
Console Printer Channel Commands . . . . . . . . . . . . . . . . .
Card Reader and Card Punch Channel Commands . . . . . . .
Printer Channel Commands . . . . . . . . . . . . . . . . . . . . . . .
Magnetic-Tape Channel Commands . . . . . . . . . . . . . . . . .
Direct Access Storage Devices . . . . . . . . . . . . . . . . . . . .
DASO Channel Commands . . . . . . . . . . . . . . . . . . . . . . .
Code Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CodeTables ..................................
Two-Character BSC Data Link Controls . . . . . . . . . . . . . . .
Commonly Used Editing Pattern Characters . . . . . . . . . . .
ANSI-Defined Printer Control Characters . . . . . . . . . . . . . .
Control Character Representations . . . . . . . . . . . . . . . . . .
Formatting Character Representations . . . . . . . . . . . . . . .
Hexadecimal and Decimal Conversion . . . . . . . . . . . . . . . . .
Powers of 2 and 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
4
4
12
14
18
19
19
19
20
21
21
22
22
22
23
23
24
24
24
24
24
24
25
25
25
25
25
25
25
26
26
27
27
27
27
28
28
28
28
28
29
30
31
32
34
34
38
38
38
38
38
39
40
NOTES
MACHINE INSTRUCTION FORMATS
FIRST HALFWORD
RR
Op Code
I I
0
R,
SECOND HALFWORD
I
R2 I
12 15
8
I
I
I
QST
I I I I
Op Code
QR3
16
0
RT2
20
VR1
24
RS2I
28 31
I
I
I
av
I E22I
Op Code
QR3
0
16
I
I
I
I
Op Code
0
16
I
I
I
I
0
28 31
24
I
I
I
I R2 I
28 31
I
I
I
RS
24
I
I
~R1
I
RRE
20
I
VR1 I VR2I
Op Code I
R, I RJ
12
8
I I
62
16
D2
20
31
I
I
I
RX
Op Code I
0
R, I X2
8
12
I
62 I
D2
20
16
31
I
I
I
s
I
Op Code
D2
62 I
0
20
16
31
I
I
I
SI
12
Op Code I
0
8
I I
D,
6,
16
31
20
I
I
I
I
VR
Op Code
0
2
I QR3
E22I I
16
20
VR1
24
I
I
GR2 I
28 31
MACHINE INSTRUCTION FORMATS (Cont'd)
FIRST HALFWORD
SECOND HALFWORD
I
I
I
VS
I
~~Rs2I
Op Code
0
16
I
I
I
I
I
I
VST
I
28 31
I I I I
Op Code
VR3
16
0
RT2
20
VR1
24
I
RS2I
28 31
I
I
I
vv
I
I
I
Op Code
0
VR3
16
~
20
VR,
24
I
I
Op Code
R3
r-0'.j
I
I
I
I
VR2I
28 31
I
I
RSE
VR1
16
I
I
I
I
I
28
Op Code
I
0
R,
8
R3
12
I
81
16
Li
8
Op Code
0
SSE
L2
12
I
81
Di
16
20
16
20
36
47
I
82
D2
32
36
47
32
36
47
36
47
Di
Op Code
0
D2
82
I
I
I
8
47
I
I
Op Code I
D2
36
32
I
0
I
Di
20
I
SS
82
32
I
I
I
I
20
24
I
I
I
~
0
I
THIRD HALFWORD
81
16
Di
20
82
32
1. 2. 3:
Denotes association with first, second, or third operand
81, 82:
D,, D2:
GR2:
Base register designation field
12:
Immediate operand field
Length field
Register designation field (equivalent to GR3 if general register, or
FR3 if floating-point register)
L, L1, L2:
QR3:
R1, R2, R3:
RS2:
RT2:
VR1, VR2, VR3:
X2:
Displacement field
Register designation field (general register)
Register designation field
Register designation field (starting address of vector)
Register designation field (stride of vector)
Register designation field (vector register)
Index register designation field
3
MACHINE INSTRUCTIONS
By Mnemonic
For-
Mnemonic
Operands
A
AO
ADR
AE
AER
AH
AL
ALR
AP
AR
AU
AUR
AW
AWR
AXR
BAL
BALR
BAS
BASR
BC
BCR
BCT
BCTR
BXH
BXLE
R,,D2(X2,B2)
R,,D2(Xz.B2J
R1,R2
R1,D2(Xz.B2J
R1.R2
R,,02(X2,B2)
R, ,D2(Xz.B2J
R,,Rz
01 (L1 ,B, ),D2(Lz.B2)
R,,R2
R, ,D2(Xz.B2)
R,,R2
Ri.D2(Xz.B2J
Ri.Rz
R,,Rz
R, ,D2(X,.B2J
R,,R2
R,,D2(Xz.B2J
R,,Rz
M,,D2(Xz.B2J
M,,R2
Ri,D2(Xz.B2)
Ri,R2
R,,R,,D2(82J
Ri ,R3,D2(B2J
c
Ri,D2(X,.B2J
Ri .D2IXz.B2J
Ri,Rz
R,,Ra,D2IB2J
Ri,D2!Xz.B2J
R1,R2
R1 ,D2IXz.B2)
R1 ,D2IXz,B2J
D,(L,B1J,D2IB2J
Ri,R2
D1(B1J,l2
R, ,M3,D2(B2J
CD
CDR
CDS
CE
CER
CH
CL
CLC
CLCL
CLI
CLM
CLR
CLRCH
CLRIO
CON CS
CP
CR
cs
CVB
CVD
D
DD
DOR
DE
DER
DISCS
DP
DR
ED
EDMK
EPAR
ESAR
EX
4
Ri,R2
D2(B2J
D2(B2J
D2(B2J
D1 (L1 ,B1 ),D2IL,.B2J
R1,R2
R,,R3,D2IB2)
R, ,D2IXz.B2J
Ri,D2IXz.B2J
R1,D2IXz.B2J
R1 ,D2IXz.B2J
R1,R2
R1,D zlXz. B21
Ri,R2
D2IB2J
D1 IL1 ,B1 J,D2IL,.B2J
Ri,Rz
o, (l,B1 J,D2(B2J
D1 (L,B1 ),D2(B2)
R,
Ri
R, ,D2IX2.B2J
mat
Name
Add
Add
Add
Add
Add
Add
Add
Add
Normalized
Normalized
Normalized
Normalized
Halfword
Logical
Logical
(LJ
(LJ
(SJ
(SJ
Add Decimal
Add
Add Unnormalized {S)
Add
Add
Add
Add
Unnormalized (SJ
Unnormalized (l)
Unnormalized (LI
Normalized !El
Branch and Link
Branch and Link
Branch and Save
Branch and Save
Branch on Condition
Branch on Condition
Branch on Count
Branch on Count
Branch on Index High
Branch on Index Low
or Equal
Compare
Compare (LI
Compare (LI
Compare Double and Swap
Compare (SJ
Compare (SJ
Compare Halfword
Compare Logical
Compare Logical
Compare Logical Long
Compare Logical
Compare Logical Characters under Mask
Compare Logical
Clear Channel
Clear 1/0
Connect Channel Set
Compare Decimal
Compare
Compare and Swap
Convert to Binary
Convert to Decimal
Divide
Divide
Divide
Divide
Divide
Ill
Ill
(SJ
(SJ
Disconnect Channel Set
Divide Decimal
Divide
Edit
Edit and Mark
Extract Primary ASN
Extract Secondary ASN
Execute
Op
Code
RX
RX
RR
RX
RR
RX
RX
RR
SS
RR
RX
RR
RX
RR
RR
RX
RR
RX
RR
RX
RR
RX
RR
RS
RS
5A
6A
2A
7A
3A
4A
5E
lE
FA
lA
7E
3E
6E
2E
36
45
05
40
OD
47
07
46
06
86
87
RX
RX
RR
RS
RX
RR
RX
RX
SS
RR
SI
RS
59
69
29
BB
79
39
49
55
05
OF
95
BD
RR
15
9F01
9001
B200
F9
19
BA
4F
4E
50
60
20
70
30
B201
FD
10
DE
DF
B226
B227
44
s
s
s
SS
RR
RS
RX
RX
RX
RX
RR
RX
RR
s
SS
RR
SS
SS
RRE
RRE
RX
Class
& Notes
i c
c
pc
pc
pc
pc
q
q
MACHINE INSTRUCTIONS (Cont'd)
By Mnemonic (Cont' di
Mnemonic
Name
Operands
HOR
HOV
HER
HIO
IAC
Ri,R2
02(82)
Ri,R2
02(82)
Ri
IC
ICM
Ri ,02IX2,B2)
Ri ,Ma,02IB2)
IPK
IPTE
Ri,R2
ISK
ISKE
Ri,R2
Ri,R2
IVSK
L
LA
LASP
Ri,R2
Ri ,02iX2,B2)
Ri ,02IX2,B2)
01IB1),02IB2)
LCOR
LCER
LCR
LCTL
LO
LOR
LE
LER
LH
LM
LNOR
LNER
LNR
LPDR
LPER
LPR
LPSW
LR
LRA
LROR
Ri,R2
Ri,R2
Ri,R2
Ri ,Ra,02(82)
R1 ,D2IX2,B2)
Ri,R2
Ri ,02IX2,B2)
Ri,R2
Ri ,02(X2,B2)
Ri,Ra,02(82)
Ri,R2
Ri,R2
Ri,R2
Ri,R2
Ri,R2
Ri,R2
02(82)
Ri,R2
Ri,02IX2,B2)
R1,R2
Halve IL)
Halt Device
Halve IS)
Halt 1/0
Insert Address Space
Control
Insert Character
Insert Characters
under Mask
Insert PSW Key
Invalidate Page Table
Entry
Insert Storage Key
Insert Storage Key
Extended
Insert Virtual Storage Key
Load
Load Address
Load Address Space
Parameters
Load Complement (L)
Load Complement IS)
Load Complement
Load Control
Load IL)
Load (L)
Load (S)
Load IS)
Load Halfword
Load Multiple
Load Negative (L)
Load Negative IS)
Load Negative
Load Positive IL)
Load Positive (S)
Load Positive
Load PSW
Load
Load Real Address
Load Rounded (Ell)
Floating-point operand lengths:
(E)
Extended source and result.
(Ell) Extended source, long result.
ILIEl Long source, extended result.
(L)
Long source and result.
!LIS) Long source, short result.
!SIL) Short source, long result.
IS)
Short source and result.
For-
Op
mat
Code
RR
RRE
24
9E01
34
9EOO
8224
RX
RS
43
BF
s
RRE
8208
8221
q
p
RR
RRE
09
8229
p
p
RRE
RX
RX
SSE
8223
58
41
E500
q
RR
RR
RR
RS
RX
RR
RX
RR
RX
RS
RR
RR
RR
RR
RR
RR
23
33
13
87
68
28
78
38
48
98
21
31
11
20
30
10
82
18
81
25
s
RR
s
s
RR
RX
RR
Class
& Notes
pc
pc
qc
pc
c
c
c
p
pn
pc
Notes:
c. Condition code set.
Interruptible instruction.
n. New condition code loaded.
p. Privileged instruction.
q. Semiprivileged instruction.
x. Execution in problem state and
supervisor state differs.
y. Condition code may be set.
Class (for instructions subject to vector-control bit, CR 0 bit 14)
Interruptible; IVCT - VIX) elements processed.
IC:
Interruptible; either (bit count in a general register) elements or
IG:
(section-size - VIX) elements processed, whichever is fewer.
Interruptible; (VCT - VIX) elements processed, vector-mask mode.
IM:
Interruptible; (partial-sum-number - VIX) elements processed.
IP:
Interruptible; (section-size) elements processed.
IZ:
NC: Not interruptible; (VCT) elements processed.
Not interruptible; (section-size) elements processed.
NZ:
NO: Not interruptible; no elements processed (VSRIVAC housekeeping).
N1: Not interruptible; one element processed.
5
MACHINE INSTRUCTIONS (Cont'd)
By Mnemonic (Cont'd)
Mnemonic
LRER
LTDR
LTER
LTR
M
MC
MD
MOR
ME
MER
MH
MP
MR
MVC
MVCIN
MVCK
MVCL
MVCP
MVCS
MVI
MVN
MVO
MVZ
MXD
MXDR
MXR
N
NC
NI
NR
0
QC
01
OR
PACK
PC
PT
R1,R2
R1,R2
R1,R2
R1,R2
R1 ,D2(X2.B2)
D1(B1l.l2
R1 ,D2(X2.B2)
R1.R2
R1 .D2(X2,B2)
R1,R2
R1 .D2(X2.B2)
D1 (L1 .B1 ),D2(L2,B2)
R1,R2
D1 (L,B1 l.D2(B2)
D1 (L,B1 ),D2(B2)
D1 (R1 .B1 l.D2(B2),Ra
R1.R2
D1 (R1 .B1 ).D2(B2),Ra
D1 (R1 ,B1 ),D2(B2),R3
D1(B1l.12
D1 (L,B1 ),D2(B2)
D1 (L1 .B1 ).D2(L2.B2)
D1 (L,B1 ),D2(B2)
R1 ,D2(X2,B2)
R1,R2
R1,R2
R1 ,D2(X2,B2)
D1(L,B1 ),D2(B2)
D1(B1).l2
R1.R2
R1 ,D2(X2,B2)
D1 (L,B1 ),D2(B2)
D1(B1l.l2
R1,R2
D1 (L1 ,B1 l.D2(L2,B2)
D2(B2)
R1,R2
PTLB
ROD
RIO
RRB
RABE
D1(B1l.12
D2(B2)
D2(B2)
R1,R2
s
SAC
SCK
SCKC
SD
SOR
SE
SER
SH
SIGP
SIO
SIOF
SL
SLA
SLDA
SLDL
SLL
SLR
SP
6
Name
Operands
R1 ,D2(X2,B2)
D2(B2)
02(82)
02(82)
R1,D2(X2,82)
R1.R2
R1 .D2(X2,82)
R1,R2
R1,D2(X2,B2)
R1,Ra,D2(B2)
02(82)
02(82)
R1 ,D2(X2,B2)
R1,D2(B2)
R1,D2(82)
R1,D2(82)
R1.D2(B2)
R1,R2
D1 (L1 ,81l.D2(L2,82)
Load Rounded (LIS)
Load and Test (L)
Load and Test (S)
Load and Test
Multiply
Monitor Call
Multiply (L)
Multiply (L)
Multiply (S/L)
Multiply (S/L)
Multiply Halfword
Multiply Decimal
Multiply
Move
Move Inverse
Move with Key
Move Long
Move to Primary
Move to Secondary
Move
Move Numerics
Format
Op
Code
RR
RR
RR
RR
RX
SI
RX
RR
RX
RR
RX
SS
RR
SS
SS
SS
RR
SS
SS
SI
SS
SS
SS
RX
RR
RR
RX
SS
SI
RR
RX
SS
SI
RR
SS
35
22
32
12
5C
AF
6C
2C
7C
3C
4C
FC
1C
02
EB
09
OE
DA
DB
92
01
Fl
03
67
27
26
54
04
94
14
56
06
96
16
F2
B21B
B22B
B20D
B5
9C02
B213
B22A
Move with Offset
Move Zones
Multiply (L/E)
Multiply (L/E)
Multiply (E)
AND
AND
AND
AND
OR
OR
OR
OR
Pack
Program Call
s
Program Transfer
RRE
Purge TLB
Read Direct
Resume 1/0
Reset Reference Bit
Reset Reference Bit
Extended
Subtract
Set Address Space Control
Set Clock
Set Clock Comparator
Subtract Normalized (L)
Subtract Normalized (L)
Subtract Normalized (S)
Subtract Normalized (SI
Subtract Halfword
s
SI
s
s
RRE
RX
s
s
s
Signal Processor
RX
RR
RX
RR
RX
RS
Start 1/0
Start 1/0 Fast Release
Subtract Logical
Shift Left Single
Shift Left Double
Shift Left Double Logical
Shift Left Single Logical
Subtract Logical
Subtract Decimal
RX
RS
RS
RS
RS
RR
SS
s
s
5B
B219
8204
8206
68
28
7B
38
48
AE
9COO
9C01
5F
BB
BF
BO
B9
1F
F8
Class
& Notes
c
c
qc
i c
qc
qc
c
c
c
c
c
c
q
q
p
p
pc
pc
pc
c
q
pc
p
c
c
c
c
c
pc
pc
pc
c
c
c
MACHINE INSTRUCTIONS (Cont'd)
By Mnemonic (Cont'd)
For-
Mnemanic
Name
Operands
mat
Op
Code
SPKA
02IB2i
Set PSW Key from
Address
s
B20A
SPM
SPT
SPX
SR
SRA
SRDA
SRDL
SRL
SRP
SSAR
SSK
SSKE
SSM
ST
STAP
STC
STCK
STCKC
STCM
Rt
D,IB2I
D,(B2I
Ri.R2
Ri,D2IB2I
Ri,D2IB2I
Ri,D2(B2I
Ri,D2IB2I
Di (Li.Bi l.D2IB2),l3
Rt
Ri,R2
Ri,R2
D,IB2I
Rt ,D2IX2,B2)
D,(B2)
Rt ,D2IX2,B2I
D,IB2I
D,(B2I
R1,M3,D2IB2I
Set Program Mask
RR
Set CPU Timer
s
s
04
B20B
B210
1B
BA
BE
BC
BB
FO
B225
OB
B22B
BO
50
B212
42
B205
B207
BE
STCTL
STD
STE
STH
STIDC
STIDP
STM
STNSM
Rt ,R3,D21B2i
Ri,D2IX2,B2I
Rt ,D2IX2,B2I
Ri,D2IX2,B2I
D,(B2i
D,(B2i
Rt ,R3,D2IB2I
DilB1l,l2
STOSM
DilB1l,l2
Store Then AND
System Mask
Store Then OR
D,(B2)
D,(B2)
Rt ,D2IX2,B2I
Ri,R2
I
Rt ,D2IX2,B2I
Ri,R2
Ri,R2
System Mask
Store CPU Timer
Store Prefix
Subtract Unnormalized (S)
Subtract Unnormalized (S)
Supervisor Call
Subtract Unnormalized (l)
Subtract Unnormalized (l)
Subtract Normalized (El
STPT
STPX
SU
SUR
SVC
SW
SWR
SXR
Set Prefix
Subtract
Shift
Shift
Shift
Shift
Short source, long result.
(S)
Short source and result.
Single
Double
Double Logical
Single Logical
Shift and Round Decimal
Set Secondary ASN
Set Storage Key
Set Storage Key Extended
RR
RS
RS
RS
RS
SS
RRE
RR
RRE
Set System Mask
Store
Store CPU Address
s
Store Character
RX
Store Clock
s
s
Store Clock Comparator
Store Characters
under Mask
Store Control
RX
s
RS
& Notes
q
p
p
q
p
p
p
p
Store Halfword
RS
RX
RX
RX
Store Channel ID
Store CPU ID
s
s
Store Multiple
RS
SI
B6
60
70
40
B203
B202
90
AC
SI
AD
p
s
s
B209
B211
7F
3F
OA
6F
2F
37
p
p
Store ILi
Store ISi
Floating-point operand lengths:
(E)
Extended source and result.
lE/L) Extended source, long result.
(L/E) Long source, extended result.
(L)
Long source and result.
(L/Sl Long source, short result.
IS/LI
Right
Right
Right
Right
Class
RX
RR
RR
RX
RR
RR
p
pc
p
p
Notes:
c. Condition code set.
Interruptible instruction.
n. New condition code loaded.
p. Privileged instruction.
q. Semiprivileged instruction.
x. Execution in problem state and
supervisor state differs.
y. Condition code may be set.
Class (for instructions subject to vector-control bit, CR 0 bit 14)
IC:
Interruptible; IVCT - VIX) elements processed.
IG:
Interruptible; either (bit count in a general register) elements or
(section-size - VIX) elements processed, whichever is fewer.
Interruptible; (VCT - VIX) elements processed, vector-mask mode.
Interruptible; (partial-sum-number - VIX) elements processed.
Interruptible; (section-size) elements processed.
Not interruptible; (VCT) elements processed.
Not interruptible; (section-size) elements processed.
Not interruptible; no elements processed (VSR/VAC housekeeping).
Not interruptible; one element processed.
IM:
IP:
IZ:
NC:
NZ:
NO:
N1:
7
MACHINE INSTRUCTIONS (Cont'd)
By Mnemonic (Cont'd)
Mnemonic
For-
Operands
vcs
Ri,R2
D2(B2)
D2(B2)
D1(B1).i2
D1 (B1 ),D2(B2)
D1 (L,B1 ),D2(B2)
D1 (L,B1 ),D2(B2)
D2(B2)
D1 (L1 ,B1 ),D2(Li.B2)
VR1, VRa,RS2(RT 2)
VR1,RS2(RT2)
VR1,VR2
VR1,RS2(RT2)
VR1.VR2
D2(B2)
D2(B2I
VR1,VRa,RS2(RT21
VR1 ,FR,, VR2
VR1,VRa,VR2
VR1,FR3,RS2(RT2)
VR1,VRa,RS2!RT2i
VR1,FRa,VR2
VR1, VR3,VR2
VR1,FRa,RS2!RT2)
VR1 ,GRa, VR2
VR1,VR3,VR2
VR1,GRa,RS2(RT21
Mi, VR3,RS2(RT 21
Mi, VRa,RS2(RT 21
M1,FR3,VR2
Mi,VR3,VR2
M1,FR3,RS2(RT2)
M1,VRa,RS2(RT2I
Mi,FR3,VR2
Mi,VRa,VR2
Mi,FR3,RS2(RT2I
GR1
Mi,GR3,VR2
Mi.VRa,VR2
Mi,GRa,RS2(RT2I
VCVM
VCZVM
VDD
VDDQ
VDDR
VDDS
VOE
VDEO
VDER
VOES
VL
VLBIX
VLCDR
VLCER
VLCR
VLCVM
VLD
VLDO
VLDR
VLE
VLEL
VLELD
GR1
VR1, VRa,RS2!RT 2)
VR1,FRa,VR2
VR1 .VRa, VR2
VR1,FRa,RS2(RT21
VR,,VR3,RS2(RT 2)
VR1,FRa,VR2
VR1,VR3,VR2
VR1,FRa,RS2(RT21
VR1,RS2(RT21
VR1 ,GRa,D2(B2i
VR1,VR2
VR1,VR2
VR1,VR2
RS2
VR1,RS2(RT21
VR1,FR2
VR1,VR2
VR1,RS2(RT21
VR1 ,GRa,GR2
VR1 ,FR3,GR2
TB
TCH
TIO
TM
TPROT
TR
TRT
TS
UNPK
VA
VACD
VACDR
VACE
VACER
VACRS
VACSV
VAD
VADO
VADR
VADS
VAE
VAEO
VAER
VAES
VAO
VAR
VAS
VC
VCD
VCDQ
VCDR
VCDS
VCE
VCEQ
VCER
VCES
VCOVM
VCO
VCR
8
Name
Test Block
Test Channel
Test 110
Test under Mask
Test Protection
Translate
Translate and Test
Test and Set
Unpack
Add
Accumulate (l)
Accumulate (l)
Accumulate (Sil)
Accumulate (S/L)
Restore VAC
Save VAC
Add (L)
Add (LI
Add (LI
Add (LI
Add (Si
Add (SI
Add (S)
Add (SI
Add
Add
Add
Compare
Compare (LI
Compare (LI
Compare (Li
Compare (Li
Compare (Si
Compare (SI
Compare (SI
Compare (Si
Count Ones in VMR
Compare
Compare
Compare
Complement VMR
Count Left Zeros in VMR
Divide (Li
Divide (Li
Divide (Li
Divide (Li
Divide (Si
Divide (S)
Divide (Si
Divide (SI
Load
Load Bit Index
Load Complement (LI
Load Complement (S)
Load Complement
Load VMR Complement
Load (L)
Load (LI
Load (l)
Load (SI
Load Element
Load Element (LI
mat
RRE
s
s
SI
SSE
SS
SS
s
SS
VST
VST
vv
VST
vv
s
s
VST
QV
vv
OST
VST
QV
vv
OST
OV
vv
OST
VST
VST
OV
vv
OST
VST
OV
vv
OST
RRE
OV
vv
OST
RRE
RRE
VST
OV
vv
OST
VST
QV
vv
OST
VST
RSE
vv
vv
vv
vs
VST
OV
vv
VST
VR
VR
Op
Code
B22C
9FOO
9000
91
E501
DC
DD
93
F3
A420
A417
A517
A407
A507
A6CB
A6CA
A410
A590
A510
A490
A400
A580
A500
A480
A5AO
A520
A4AO
A428
A418
A598
A518
A498
A408
A588
A508
A488
A643
A5A8
A528
A4A8
A641
A642
A413
A593
A513
A493
A403
A583
A503
A483
A409
E428
A552
A542
A562
A681
A419
A599
A519
A409
A628
A618
Class
& Notes
ipc
pc
pc
pc
c
c
IM
IM
IM
IM
IM
NO p
NO p
IM
IM
IM
IM
IM
IM
IM
IM
IM
IM
IM
IC
IC
IC
IC
IC
IC
IC
IC
IC
NC
IC
IC
IC
NC
NC
IM
IM
IM
IM
IM
IM
IM
IM
IC
IG
c
IM
IM
IM
NC
IC
IC
IC
IC
N1
N1
MACHINE INSTRUCTIONS (Cont'd)
By Mnemonic (Cont'd)
Mne-
For-
Operands
monic
VLELE
VLEQ
VLER
VLH
VLI
VLID
VLIE
VLINT
VLM
VLMD
VLMDQ
VLMDR
VLME
VLMEO
VLMER
VLMQ
VLMR
VLNDR
VLNER
VLNR
VLPDR
VLPER
VLPR
VLQ
VLR
VLVCA
VLVCU
VLVM
VLY
VLYD
VLYE
VLZDR
VLZER
VLZR
VM
VMAD
VMADQ
VMADS
VMAE
VMAEQ
VR1 ,FRa,GR2
VR1.FR2
VR1,VR2
VR1,RS2IRT2I
VR1, VR3,D2IB2)
VR1,VR3,D2IB2l
VR1, VR3,D2(82)
VR1,RS2IRT2)
VR1,RS2(RT21
VR1,RS2IRT2I
VR1,FR2
VR1,VR2
VR1,RS2IRT2)
VR1,FR2
VR1,VR2
VR1,GR2
VR1,VR2
VR1,VR2
VR1,VR2
VR1,VR2
VR1,VR2
VR1,VR2
VR1,VR2
VR1,GR2
VR1,VR2
D2(82I
GR1
RS2
VR1,RS2IRT2)
VR1,RS2(RT2)
VR1,RS2(RT2)
VR1
VR1
VR1
VR1,VRa,RS2(RT2l
VR1,VRa,RS21RT2l
VR1,FRa,VR2
VR1,FRa,RS2IRT2l
VR1,VRa,RS2(RT2)
VR1,FR3,VR2
Name
Load
Load
Load
Load
Load Indirect
Load Indirect ILi
Load Indirect IS)
Load Integer Vector
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load Positive
Load
Load VCT from Address
Load VCT and Update
Load VMR
Load Expanded
Load Expanded (L)
Load Expanded (S)
Load Zero (L)
Load Zero ISi
Load Zero
Multiply
Multiply and Add Ill
Multiply and Add (l)
Multiply and Add (l)
Multiply and Add (Sill
Multiply and Add (Sill
Extended source, long result.
(L)
Long source, extended result.
Long source and result.
(L/S)
Long source, short result.
Short source, long result.
IL)
ISi
Load
(LIE)
Short source and result.
(LI
(L)
IL)
IS)
IS)
IS)
Load Positive Ill
Load Positive ISi
(E/LI
(5)
Matched
Matched
Matched
Matched
Matched
Matched
Matched
Matched
Matched
Negative
Negative
Load Negative
Floating-point operand lengths:
(E)
Extended source and result.
(5/L)
Element ISi
ISi
IS)
Halfword
mat
VR
QV
vv
VST
RSE
RSE
RSE
VST
VST
VST
QV
vv
VST
QV
vv
av
vv
vv
vv
vv
vv
vv
vv
av
vv
s
ARE
vs
VST
VST
VST
vv
vv
vv
VST
VST
QV
OST
VST
QV
Op
Code
A608
A589
A509
A429
E400
E410
E400
A42A
A40A
A41A
A59A
A51A
A40A
A58A
A50A
A5AA
A50A
A551
A541
A561
A550
A540
A560
A5A9
A509
A6C4
A645
A680
A40B
A41B
A40B
A51B
A50B
A50B
A422
A414
A594
A494
A404
A584
Class
& Notes
N1
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IM
IM
IM
IM
IM
IM
IC
IC
NO
NO
NC
IC
IC
IC
IC
IC
IC
IM
IM
IM
IM
IM
IM
Notes:
c. Condition code set.
Interruptible instruction.
n. New condition code loaded.
p. Privileged instruction.
q. Semiprivileged instruction.
x. Execution in problem state and
supervisor state differs.
y. Condition code may be set.
Class (for instructions subject to vector-control bit, CR 0 bit 14)
IC:
Interruptible; IVCT - VIX) elements processed.
IG:
IM:
IP:
IZ:
NC:
NZ:
Interruptible; either (bit count in a general register) elements or
(section-size - VIX) elements processed, whichever is fewer.
Interruptible; (VCT - VIX) elements processed, vector-mask mode.
Interruptible; (partial-sum-number - VIX) elements processed.
Interruptible; (section-size) elements processed.
Not interruptible; (VCT) elements processed.
Not interruptible; (section-size) elements processed.
NO:
Not interruptible; no elements processed IVSR/VAC housekeeping).
N1:
Not interruptible; one element processed.
9
MACHINE INSTRUCTIONS (Cont'd)
By Mnemonic (Cont'd)
Mnemonic
VMAES
VMCD
VR1 ,FRa,RS2(RT2)
VR1,VRa,RS2IRT2)
VMCDR
VR1, VRa, VR2
VMCE
VR1,VRa,RS2(RT2)
VMCER
VR1,VRa,VR2
VMD
VMDa
VMDR
VMDS
VME
VMEQ
VMER
VMES
VMNSD
VMNSE
VMa
VMR
VMRRS
VMRSV
VMS
VMSD
VMSDa
VMSDS
VMSE
VMSEa
VMSES
VMXAD
VMXAE
VMXSD
VMXSE
VN
VR1,VRa,RS2lRT2)
VR1,FRa,VR2
VR1,VRa,VR2
VR1,FRa,RS2(RT2)
VR1,VRa,RS2(RT2)
VR1,FRa,VR2
VR1,VRa,VR2
VR, ,FRa,RS2(RT 2)
VR1,FRa,GR2
VR1,FRa,GR2
VR1 ,GR a, VR2
VR1,VRa,VR2
D2(82)
D2(B2)
VR1,GRa,RS2(RT2)
VR1, VRa,RS2(RT2)
VR1 ,FRa, VR2
VR1,FRa,RS2(RT2)
VR1, VRa,RS2(RT 2)
VR1 ,FRa, VR2
VR1,FRa,RS2(RT2)
VR1,FRa,GR2
VR1 ,FRa,GR2
VR1,FRa.GR2
VR1 ,FRa,GR2
VR1,VRa,RS2IRT2)
VR1,GRa,VR2
VR1, VRa,VR2
VR1,GRa,RS2(RT2)
RS2
VR1, VRa,RS2(RT 2)
VR1,GRa,VR2
VR1,VRa,VR2
VR1,GRa,RS2(RT2)
RS2
D2(82)
GR1
GR1
GR1
VR1,VRa,RS2(RT2)
VR1,VRa,RS2(RT2)
VR1,FRa,VR2
VR1,VRa,VR2
VR1,FRa,RS2(RT2)
VR1,VRa,RS2(RT2)
VR1,FRa,VR2
VR1,VRa,VR2
VR1,FRa,RS2IRT2)
VR1, VRa,D2IB2I
VR1,FR2
VR1 ,GRa, VR2
VR1,VRa.VR2
VR1, VRa,D2IB2I
VNa
VNR
VNS
VNVM
VO
voa
VOR
VOS
VOVM
VRCL
VRRS
VRSV
VRSVC
vs
VSD
VSDa
VSDR
VSDS
VSE
VS Ea
VSER
VSES
VSLL
VSPSD
vsa
VSR
VSRL
10
mat
Op
Code
a ST
VST
A484
A416
IM
IM
vv
A516
IM
VST
A406
IM
vv
A506
IM
For-
Name
Operands
Multiply and Add (Sil)
Multiply and
Accumulate (L)
Multiply and
Accumulate (L)
Multiply and
Accumulate (SIL)
Multiply and
Accumulate ISiL)
Multiply (L)
Multiply (L)
Multiply (L)
Multiply (L)
Multiply (Sil)
Multiply (Sil)
Multiply (Sil)
Multiply (Sil)
Minimum Signed (l)
Minimum Signed (S)
Multiply
Multiply
Restore VMR
Save VMR
Multiply
Multiply and Subtract (L)
Multiply and Subtract (L)
Multiply and Subtract (L)
Multiply and Subtract (Sil)
Multiply and Subtract (Sil)
Multiply and Subtract (Sil)
Maximum Absolute (L)
Maximum Absolute IS)
Maximum Signed (l)
Maximum Signed (S)
AND
AND
AND
AND
AND to VMR
OR
OR
OR
OR
OR to VMR
Clear VR
Restore VA
Save VR
Save Changed VR
Subtract
Subtract IL)
Subtract IL)
Subtract (L)
Subtract (l)
Subtract (S)
Subtract (S)
Subtract IS)
Subtract ISi
Shift Left Single Logical
Sum Partial Sums ILi
Subtract
Subtract
Shift Right Single Logical
VST
av
vv
a ST
VST
av
vv
a ST
VR
VR
av
vv
A412
A592
A512
A492
A402
A582
A502
A482
A611
A601
A5A2
A522
A6C3
A6C1
a ST A4A2
VST A415
av A595
a ST A495
VST A405
av
A585
aST A485
VR
A612
VR
A602
A610
VR
VR
A600
VST A424
av A5A4
vv A524
a ST A4A4
vs A684
VST A425
av A5A5
vv
A525
a ST A4A5
vs A685
A6C5
s
RRE A648
RRE A64A
RRE A649
VST A421
VST A411
av A591
vv
A511
a ST A491
VST A401
av
A581
vv A501
a ST A481
RSE E425
VR
A61A
av
A5A1
vv
A521
RSE E424
s
s
Class
& Notes
IM
IM
IM
IM
IM
IM
IM
IM
IM
IM
IM
IM
NZ
NZ
IM
IM
IM
IM
IM
IM
IM
IM
IM
IM
IM
IM
IM
IM
IM
NC
IM
IM
IM
IM
NC
IZ
IZ XC
IZ
c
IZ pc
IM
IM
IM
IM
IM
IM
IM
IM
IM
IM
IP
IM
IM
IM
MACHINE INSTRUCTIONS (Cont'd)
By Mnemonic (Cont'd)
Mnemonic
For-
Operands
VSRRS
VS RSV
vss
VST
VSTD
VSTE
VSTH
VSTI
VSTIO
VSTIE
VSTK
VSTKO
VSTKE
VSTM
VSTMO
VSTME
VSTVM
VSTVP
VSVMM
VTVM
vx
VXEL
VXELO
VXELE
VXQ
VXR
VXS
vxvc
VXVM
VXVMM
VZPSO
WRO
x
XC
XI
XR
ZAP
02IB2I
02IB2I
VR1 ,GRa,RS2IRT 21
VR1,RS2IRT21
VR1,RS2IRT21
VR1,RS2IRT21
VR1,RS2IRT21
VR1,VR3,02IB2I
VR1,VR3,02IB2I
VR1 ,VR3,02IB2I
VR1,RS2IRT21
VR1,RS2IRT21
VR1,RS2IRT21
VR1,RS2IRT2)
VR1,RS21RT2)
VR1,RS2IRT2)
RS2
02IB2I
02IB2I
VR1, VR3,RS2(RT 21
VR1 ,GRa,GR2
VR1 ,FR3,GR2
VR1 ,FR3,GR2
VR1,GR3,VR2
VR1,VR3,VR2
VR1,GRa,RS2(RT21
GR1
RS2
GR1
VR1
01(B1l,l2
Ri,02(X2,B2I
01 (L,B1 ),02(82)
01(B1l.l2
R,,R2
01 (L1 ,B1 l.02(L2,B2I
Model-dependent
s
s
Restore VSR
Save VSR
Subtract
Store
Store Ill
Store ISi
Store Halfword
Store Indirect
Store Indirect Ill
Store Indirect ISi
Store Compressed
Store
Store
Store
Store
Store
Store
Compressed Ill
Compressed ISi
Matched
Matched ILi
Matched ISi
VMR
Store Vector Parameters
Set Vector Mask Mode
Test VMR
Exclusive OR
Extract Element
Extract Element (LI
Extract Element (SI
Exclusive OR
Exclusive OR
Exclusive OR
Extract VCT
Exclusive OR to VMR
Extract Vector Mask Mode
Zero Partial Sums ILi
Write Direct
Exclusive OR
Exclusive OR
Exclusive OR
Exclusive OR
Zero and Add
OST
VST
VST
VST
VST
RSE
RSE
RSE
VST
VST
VST
VST
VST
VST
vs
s
s
RRE
VST
VR
VR
VR
av
vv
OST
RRE
vs
RRE
VR
SI
RX
SS
SI
RR
SS
Diagnose
Floating-point operand lengths:
(El
Extended source and result.
(Elli
(LIE)
(L)
(LIS)
(Sill
IS)
mat
Name
Extended source, long result.
Long source, extended result.
Long source and result.
Long source, short result.
Short source, long result.
Short source and result.
Op
Code
A6C2
A6CO
A4A1
A400
A410
A400
A42D
E401
E411
E401
A40F
A41F
A40F
A40E
A41E
A40E
A682
A6C8
A6C6
A640
A426
A629
A619
A609
A5A6
A526
A4A6
A644
A686
A646
A618
84
57
07
97
17
F8
83
Class
& Notes
IZ
NO x
IM
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
IC
NC
NO
NO
NC c
IM
N1
N1
N1
IM
IM
IM
NO
NC
NO
IP
p
PY
Notes:
c.
n.
p.
q.
x.
y.
Condition code set.
Interruptible instruction.
New condition code loaded.
Privileged instruction.
Semiprivileged instruction.
Execution in problem state and
supervisor state differs.
Condition code may be set.
Class (for instructions subject to vector-control bit, CR 0 bit 14)
IC:
IG:
IM:
IP:
IZ:
NC:
NZ:
NO:
N1:
Interruptible; (VCT - VIX) elements processed.
Interruptible; either (bit count in a general register) elements or
(section-size - VIX) elements processed, whichever is fewer.
Interruptible; (VCT - VIX) elements processed, vector-mask mode.
Interruptible; (partial-sum-number - VIX) elements processed.
Interruptible; {section-size) elements processed.
Not interruptible; (VCT) elements processed.
Not interruptible; (section-size) elements processed.
Not interruptible; no elements processed (VSR/VAC housekeeping).
Not interruptible; one element processed.
11
MACHINE INSTRUCTIONS !Cont'd)
By Operation Code
12
Op
Code
Mnemanic
Op
Code
Mnemonic
04
05
06
07
OB
09
OA
OD
OE
OF
10
11
12
13
14
15
16
17
1B
19
1A
1B
1C
10
1E
1F
20
21
22
23
24
25
26
27
2B
29
2A
2B
2C
20
2E
2F
30
31
32
33
34
35
36
37
3B
39
3A
3B
JC
30
3E
3F
40
41
42
43
44
45
46
SPM
BALA
BCTR
BCR
SSK
ISK
SVC
BASA
MVCL
CLCL
LPR
LNR
47
4B
49
4A
4B
4C
40
4E
4F
50
54
55
56
57
5B
59
5A
5B
5C
50
5E
5F
60
67
6B
69
6A
6B
6C
60
6E
6F
70
7B
79
7A
7B
7C
70
7E
7F
BO
B2
BJ
B4
B5
B6
B7
BB
B9
BA
BB
BC
BD
BE
BF
90
91
92
93
94
95
96
97
9B_
BC
LH
CH
AH
SH
MH
BAS
CVD
CVB
ST
N
CL
LTR
LCR
NA
CLR
OR
XR
LR
CR
AR
SR
MR
DR
ALA
SLR
LPDR
LNDR
LTDR
LCDR
HOR
LADA
MXR
MXDR
LOR
CDR
ADA
SOR
MOR
DOR
AWA
SWR
LPER
LNER
LTER
LCER
HER
LRER
AXA
SXR
LEA
CEA
AER
SER
MER
DER
AUR
SUR
STH
LA
STC
IC
EX
BAL
BCT
0
x
c
A
S
M
D
AL
SL
STD
MXD
LO
CD
AD
SD
MD
DD
AW
SW
STE
LE
CE
AE
SE
ME
DE
AU
SU
SSM
LPSW
Diagnose
WAD
ADD
BXH
BXLE
SAL
SLL
SRA
SLA
SRDL
SLDL
SADA
SLDA
STM
TM
MVI
TS
NI
CLI
01
XI
LM
Op
Code
Mnemonic
9COO
9C01
9C02
9000
9001
9EOO
9E01
9FOO
9F01
A400
A401
A402
A403
A404
A405
A406
A407
A40B
A409
A409
A40A
A40A
A40B
A40B
A40D
A40D
A40E
A40E
A40F
A40F
A410
A411
A412
A413
A414
A415
A416
A417
A41B
A419
A41A
A41B
A41D
A41E
A41F
A420
A421
A422
A424
A425
A426
A42B
A429
A42A
A42D
A4BO
A4B1
A4B2
A4B3
A4B4
A4B5
A4BB
A490
A491
A492
SIO
SIOF
RIO
TIO
CLRIO
HIO
HOV
TCH
CLRCH
VAE
VSE
VME
VOE
VMAE
VMSE
VMCE
VACE
VCE
VL
VLE
VLM
VLME
VLY
VLYE
VST
VSTE
VSTM
VSTME
VSTK
VSTKE
VAD
VSD
VMD
VDD
VMAD
VMSD
VMCD
VACD
VCD
VLD
VLMD
VLYD
VSTD
VSTMD
VSTKD
VA
VS
VM
VN
VO
VX
VC
VLH
VLINT
VSTH
VAES
VSES
VMES
VOES
VMAES
VMSES
VCES
VADS
VSDS
VMDS
MACHINE INSTRUCTIONS (Cont'd)
By Operation Code (Cont'd)
Op
Mne-
Op
Code
monic
Code
A493
A494
A495
A49B
A4AO
A4A1
A4A2
A4A4
A4A5
A4A6
A4AB
A500
A501
A502
A503
A506
A507
A50B
A509
A509
A50A
A50A
A50B
A50B
A510
A511
A512
A513
A516
A517
A51B
A519
A51A
A51B
A520
A521
A522
A524
A525
A526
A52B
A540
A541
A542
A550
A551
A552
A560
A561
A562
A5BO
A5B1
A5B2
A5B3
A5B4
A5B5
A5BB
A5B9
A5BA
A590
A591
A592
A593
A594
A595
VDDS
VMADS
VMSDS
VCDS
VAS
A59B
A599
A59A
A5AO
A5A1
A5A2
A5A4
A5A5
A5A6
A5A8
A5A9
A5AA
A600
A601
A602
A60B
A609
A610
A611
A612
A61B
A619
A61A
A618
A62B
A629
A640
A641
A642
A643
A644
A645
A646
A64B
A649
A64A
A6BO
A6B1
A6B2
A6B4
A6B5
A6B6
A6CO
A6C1
A6C2
A6C3
A6C4
A6C5
A6C6
A6CB
A6CA
A6CB
AC
AD
AE
vss
VMS
VNS
VOS
vxs
vcs
VAER
VSER
VMER
VDER
VMCER
VACER
VCER
VLER
VLR
VLMER
VLMR
VLZER
VLZR
VADR
VSDR
VMDR
VDDR
VMCDR
VACDR
VCDR
VLDR
VLMDR
VLZDR
VAR
VSR
VMR
VNR
VOR
VXR
VCR
VLPER
VLNER
VLCER
VLPDR
VLNDR
VLCDR
VLPR
VLNR
VLCR
VAEO
VSEO
VMEO
VDEO
VMAEQ
VMSEQ
VCEO
VLEO
VLMEQ
VADQ
VSDQ
VMDQ
VDDQ
VMADQ
VMSDQ
AF
B1
8200
B201
B202
B203
B204
B205
B206
B207
Mnemonic
VCDQ
VLDQ
VLMDQ
VAQ
VSQ
VMQ
VNQ
VOQ
VXQ
VCQ
VLQ
VLMQ
VMXSE
VMNSE
VMXAE
VLELE
VXELE
VMXSD
VMNSD
VMXAD
VLELD
VXELD
VSPSD
VZPSD
VLEL
VXEL
VTVM
VCVM
VCZVM
VCOVM
vxvc
VLVCU
VXVMM
VRRS
VRSVC
VRSV
VLVM
VLCVM
VSTVM
VNVM
VOVM
VXVM
VS RSV
VMRSV
VSRRS
VMRRS
VLVCA
VRCL
VSVMM
VSTVP
VACSV
VACRS
STNSM
STOSM
SIGP
MC
LRA
CONG&
DISCS
STIDP
STIDC
SCK
STCK
SCKC
STCKC
Op
Mne-
Code
monic
820B
8209
B20A
B20B
B20D
B210
B211
B212
B213
B218
B219
B221
B223
B224
B225
B226
B227
B22B
B229
B22A
B22B
B22C
B6
B7
BA
BB
BD
BE
SPT
STPT
SPKA
IPK
PTLB
SPX
STPX
STAP
RRB
PC
SAC
IPTE
IVSK
IAC
SSAR
EPAR
ESAR
PT
ISKE
RRBE
SSKE
TB
STCTL
LCTL
BF
01
02
03
04
05
06
07
09
DA
DB
DC
DD
DE
OF
E400
E400
E401
E401
E410
E411
E424
E425
E42B
E500
E501
EB
FO
F1
F2
F3
FB
F9
FA
FB
FC
FD
cs
CDS
CLM
STCM
ICM
MVN
MVC
MVZ
NC
CLC
QC
xc
MVCK
MVCP
MVCS
TR
TRT
ED
EDMK
VLI
VLIE
VSTI
VSTIE
VLID
VSTID
VSRL
VSLL
VLBIX
LASP
TPROT
MVCIN
SRP
MVO
PACK
UNPK
ZAP
CP
AP
SP
MP
DP
13
CONDITION CODES
Condition Code -
0
1
2
3
Mask Bit Value -
8
4
2
1
Binary and Logical
Instructions (See Note)
Add
Zero
Zero
Overflow
Add Halfword
Zero
Zero
Overflow
Add Logical
Zero,
Not zero,
no carry
Zero,
carry
carry
no carry
Not zero,
AND
Zero
Not zero
--
--
Compare
Equal
First op
low
First op
high
--
Compare and Swap
Equal
Not equal
Equal
Not equal
---
--
Compare Double and Swap
Compare Halfword
Equal
First op
low
First op
high
--
Compare Logical
Equal
First op
low
First op
high
--
Compare Logical Characters
under Mask
Equal, or
mask is
zero
First op
low
First op
high
--
Compare Logical Long
Equal, or
lengths
both = 0
First op
low
First op
high
--
Exclusive OR
Zero
Not zero
--
--
Insert Characters under Mask
All zero,
Leftmost
bit = 1
Not zero,
but with
leftmost
bit = 0
--
or mask
is zero
--
Load and Test
Zero
Zero
--
Load Complement
Zero
Zero
Overflow
Load Negative
Zero
Zero
Overflow
Move Long
Operand
lengths
First op
shorter
First op
Overlap
longer
equal
OR
Zero
Not zero
--
--
Set Program Mask
See Note
See Note
See Note
See Note
Shift Left Double
Zero
Zero
Overflow
Shift Left Single
Zero
Zero
Overflow
Shift Right Double
Zero
Zero
--
Shift Right Single
Zero
Zero
--
Subtract
Zero
Zero
Overflow
Subtract Halfword
Zero
Zero
Overflow
Subtract Logical
--
Not zero,
no carrry
Zero,
carry
Not zero,
carry
Test and Set
Leftmost
bit zero
Leftmost
bit one
--
--
Test under Mask
All zeros,
or mask
is zero
Mixed O's
and 1's
--
All ones
Translate and Test
All zeros
Not zero,
scan
incomplete
Not zero,
scan
complete
--
Note: Vector instructions with binary or logical operands do not set the condition code.
For Set Program Mask, the condition code is loaded from bits 2 and 3 of the first operand.
14
CONDITION CODES (Cont'd)
Condition Code -
0
1
2
3
Mask Bit Value -
8
4
2
1
Decimal Instructions
Add Decimal
Zero
Zero
Overflow
Compare Decimal
Equal
First op
low
First op
high
--
Edit
Zero
Zero
--
Edit and Mark
Zero
Zero
--
Shift and Round Decimal
Zero
Zero
Overflow
Subtract Decimal
Zero
Zero
Overflow
Zero and Add
Zero
Zero
Overflow
Add Normalized
Zero
Zero
--
Add Unnormalized
Zero
Zero
--
Compare
Equal
First op
low
First op
high
--
Load and Test
Zero
Zero
--
Load Complement
Zero
Zero
--
Load Negative
Zero
Zero
--
Subtract Normalized
Zero
Zero
--
Subtract Unnormalized
Zero
Zero
--
Active
Active
--
Active
bits all
zeros
bits O's
and 1's
Active
bits all
zeros
Active
bits O's
and 1 's
--
Load Bit Index
VCT = 0
and bit
count = 0
VCT = 0
and bit
count< 0
VCT =
section size
and bit
count> 0
VCT> 0
and bit
count
not> 0
Load VCT and Update
VCT = 0
and new
count = 0
VCT = 0
and new
count< 0
VCT =
section size
and new
count> 0
VCT>O
and new
count = 0
Load VCT from Address
VCT = 0
and elf
addr = 0
VCT = 0
and elf
addr < 0
VCT =
section size
and elf
addr >
section size
VCT>O
and elf
addr ~
section size
Floating-Point Instructions
(See Note)
General Instructions
Count Left Zeros in VMR
Count Ones in VMR
bits all
ones
Active
bits all
ones
Note: Vector instructions with floating-point operands do not set the condition code.
15
CONDITION CODES (Cont'd)
Condition Code ...
0
1
2
3
Mask Bit Value ...
8
4
2
1
General Instructions
(Continued)
Restore VR
VR14-pair
examined
and not
loaded
VR-pair
(other than
VR14-pairl
VR14-pair
loaded
examined
and not
VA-pair
(other than
VR14-pair)
loaded
loaded
Save VR
VR14-pair
examined
and not
stored
VR-pair
(other than
VR14-pair)
VR14-pair
stored
examined
VR-pair
(other than
VR14-pair)
stored
and not
stored
Store Clock
Test VMR
Set state
Not-set
state
Error
state
Active
Active
--
bits all
bits O's
and 1 's
zeros
Stopped
state or
not oper
Active
bits all
ones
Control Instructions
Connect Channel Set
Successful
Connected
to other
CPU
--
Not oper
Diagnose
See Note
See Note
See Note
See Note
Disconnect Channel Set
Successful
Connected
--
Not aper
to other
CPU
Insert Address Space Control
Zero
One
--
--
Load Address Space
Parameters
Primary
Secondary
Space-
Parameters
loaded
not
available
not auth-
switch
event
orized
or not
available
Load PSW
See Note
See Note
See Note
See Note
Load Real Address
Translation
available
Segmenttable
Pagetable
Table
length
entry
invalid
entry
invalid
exceeded
--
--
Move to Primary
Length
"' 256
Move to Secondary
Move with Key
Length
s256
--
Length
--
---
Length
> 256
Length
> 256
Length
> 256
,,;256
Reset Reference Bit
Ref = 0,
Chg= 0
Ref = 0,
Chg= 1
Ref = 1,
Chg= 0
Ref = 1,
Chg= 1
Reset Reference Bit Extended
Ref = 0,
Chg= 0
Ref = 0,
Chg= 1
Ref= 1,
Chg= 0
Ref= 1,
Chg= 1
Note: For Diagnose, the resulting condition code is model-dependent'. For Load PSW,
the condition code is loaded from a field of the second operand (the new PSW' s
condition code field).
16
CONDITION CODES (Cont'd)
Condition Code -
0
1
2
3
Mask Bit Value -
8
4
2
1
Control Instructions
(Continued}
Save Changed VR
VR14-pair
VR-pair
VR14-pair
examined
and not
(other than
VR14-pair)
examined
stored
stored
VA-pair
(other than
VR14-pairl
stored
and not
stored
Set Clock
Set
Secure
--
Not aper
Signal Processor
Accepted
Status
Busy
Not aper
stored
Test Block
Usable
Unusable
--
--
Test Protection
Fetch and
Fetch
allowed;
No fetch
or store
allowed
Translation
store
allowed
no store
allowed
not
available
Input/Output Instructions
Clear Channel
Reset
signaled
--
Channel
busy
Not aper
Clear 1/0
No aperation in
progress
CSW stored
Channel
busy
Not aper
Halt Device
Busy or
interruption
pending
CSW stored
Channel
Not aper
Interruption
pending
CSW stored
Halt 1/0
working
Burst op
Not aper
stopped
Successful
--
--
Not aper
Successful
CSW stored
Busy
Not aper
Start 1/0 Fast Release
Successful
CSW stored
Busy
Not aper
Store Channel ID
Chan ID
CSW stored
Busy
Not aper
Resume 1/0
Start 1/0
stored
Test Channel
Available
Interruption
pending
Working in
burst mode
Not aper
Test 1/0
Available
CSW stored
Busy
Not aper
17
ASSEMBLER INSTRUCTIONS
Function
Mnemonic
Meaning
Data definition
DC
DS
CCW
CCW1**
Define
Define
Define
Define
Define
Program
sectioning
and linking
START
LOCTR**
CSE CT
DSECT
DXD*
CXD*
COM
AMODE**
RMODE**
ENTRY
EXTRN
WXTRN
Start assembly
Specify multiple location counters
Identify control section
Identify dummy section
Define external dummy section
Cumulative length of external dummy section
Identify blank common control section
Specify addressing mode
Specify residence mode
Identify entry-point symbol
Identify external symbol
Identify weak external symbol
Base register
assignment
USING
DROP
Use base address register
Drop base address register
Control of listings
TITLE
EJECT
SPACE
PRINT
Identify assembly output
Sta rt new page
Space listing
Print optionaJ data
Program Control
ICTL
ISEQ
PUNCH
RE PRO
ORG
EQU
OPSYN*
PUSH*
POP*
LTORG
CNOP
COPY
END
Input format control
Input sequence checking
Punch a card
Reproduce following card
Set location counter
Equate symbol
Equate operation code
Save current PRINT or USING status
Restore PRINT or USING status
Begin literal pool
Conditional no operation
Copy predefined source coding
End assembly
Macro definition
MACRO
MEXIT
MEND
AREAD**
Macro definition header
Macro definition exit
Macro definition trailer
Assign card to SETC symbol
Conditional
assembly
ACTR
AGO
AIF
ANOP
GBLA
GBLB
GBLC
LCLA
LCLB
LCLC
MNOTE
MHELP**
SETA
SETB
SETC
Conditional assembly loop counter
Unconditional branch
Conditional branch
Assembly no operation
Define global SETA symbol
Define global SETB symbol
Define global SETC symbol
Define local SET A symbol
Define local SETB symbol
Define local SETC symbol
Generate error message
Trace macro flow
Set arithmetic variable symbol
Set binary variable symbol
Set character variable symbol
ccwo··
constant
storage
channel command word
format-0 channel command word
format-1 channel command word
Source: GC33-4010 for the OS/VS, VM/370, and DOS/VSE Assembler, and
GC26-4037 for Assembler H Version 2.
*Not for use with the DOS/VSE Assembler.
**Assembler H Version 2 only.
18
EXTENDED MNEMONIC INSTRUCTIONS
Extended Mnemonic* (RX or RR)
Meaning
(RX or RR)
General
B or BR
NOP or NOPR
Unconditional Branch
No Operation
BCorBCR15,
BC or BCR 0,
After
BH or BHR
BL or BLR
BE or BER
BNH or BNHR
8NL or BNLR
BNE or BNER
Branch on A High
Branch on A Not Equal B
BC or BCR 2,
BC or BCR 4,
BC or BCR 8,
BCorBCR13,
BCorBCR11,
BC or BCR 7,
After
Arithmetic
Instructions
BP or BPR
BM or BMR
BZ or BZR
BO or BOR
BNP or BNPR
BNM or BNMR
BNZ or BNZR
BNO or BNOR
Branch
Branch
Branch
Branch
Branch
Branch
Branch
Branch
on
on
on
on
on
on
on
on
BC
BC
BC
BC
BC
BC
BC
BC
or
or
or
or
or
or
or
or
BCR
BCR
BCR
BCR
BCR
BCR
BCR
BCR
2,
4,
B,
1,
13,
11,
7,
14,
After Test
under Mask
Instruction
BO or BOR
BM or BMR
BZ or BZR
BNO or BNOR
BNM or BNMR
BNZ or BNZR
Branch
Branch
Branch
Branch
if Ones
BC
BC
BC
BC
BC
BC
or
or
or
or
or
or
BCR
BCR
BCR
BCR
BCR
BCR
1,
4,
8,
14,
11,
7,
Use
Compare
Instructions
IA:BI
Machine Instr.*
Branch on A Low
Branch on A Equal B
Branch on A Not High
Branch on A Not Low
Plus
Minus
Zero
Overflow
Not Plus
Not Minus
Not Zero
No Overflow
if Mixed
if Zeros
if Not Ones
Branch if Not Mixed
Branch if Not Zeros
Source: GC33-4010 for the OS/VS, VM/370, and DOS/VSE Assembler, and
GC26-4037 for Assembler H Version 2.
*Second operand, not shown, is D2(X2,B2) for RX format and R2 for RR format.
CNOP ALIGNMENT
DOUBLEWORD
WORD
HALFWORD
BYTE '
BYTE
I
'
HALFWORD
BYTE
I
I
• BYTE
WORD
I
HALFWORD
BYTE '
BYTE • BYTE
HALFWORD
' BYTE
I
~
0,4
~
2,4
~
0,4
~
2,4
0,8
2,8
4,8
6,8
Source: GC33-4010 for the OS/VS, VM/370, and DOS/VSE Assembler, and
GC26-4037 for Assembler H Version 2.
SUMMARY OF CONSTANTS
Type
c
G**
x
Implied
Length,
Bytes
characters
(even)
-
byte
byte
4
2
4
word
8
doubleword
doubleword
byte
byte
hexadecimal digits
binary digits
fixed-point binary
fixed-point binary
short floating-point
long floating-point
extended floating-point
packed decimal
zoned decimal
value of address
value of address
address in base-displacement form
externally defined address value
symbol naming a DXD or DSECT
16
p
-
z
-
A
y
4
2
2
4
4
Q*
Format
Alignment
byte
byte
-
B
F
H
E
D
L
s
v
Trunca-
halfword
word
word
halfword
halfword
word
word
graphic (double-byte) characters
ti on/
Padding
right
right
left
left
left
left
right
right
right
left
left
left
left
left
left
Source: GC33-4010 for the OS/VS, VM/370, and DOS/VSE Assembler, and
GC26-4037 for Assembler H Version 2.
•Not for use with the DOS/VSE Assembler.
**Assembler H Version 2 only.
19
FIXED STORAGE LOCATIONS
dee.
Addr
type
0- 7
0- 7
B- 15
B- 15
16- 23
24- 31
32- 39
40- 47
4B- 55
56- 63
64- 71
72- 75
BO- B3
B4- B7
BB- 95
96-103
104-111
112-119
120-127
128-131
132-133
A
R
A
R
A
R
R
R
R
R
R
R
R
L
R
R
R
R
R
R
R
0
0
B
B
10
1B
20
2B
30
3B
40
4B
50
54
5B
60
6B
70
78
BO
B4
132-133
R
B4
x
134-135
136-139
R
R
86
88
x
x
140-143
R
BC
x
Program interruption {0-12 zeros, 13-14 ILC, 15:0,
144-147
14B-149
150-151
152-155
156-159
168-171
R
R
R
x
Translation-exception ID (see table)
Monitor class (0-7 zeros, 8-15 class number)
x
x
PER code (0-3 code, 4-15 zeros)
R
R
90
94
96
98
9C
AB
172-175
R
AC
176-179
1B5
186-187
216-223
216-223
224-231
224-231
232-239
244-247
24B-251
252-255
256-263
256-351
264-267
26B-271
352-3B3
352-3B3
3B4-447
384-447
44B-511
44B-511
795
R
R
R
A
R
A
R
R
R
R
R
A
R
A
A
A
R
A
R
A
R
L
80
89
BA
DB
Area,
Hex
EC
addr
only
Function
Initial-program-loading PSW
Restart new PSW
Initial-program-loading CCW 1
Restart old PSW
lnitia_l-program-loading CCW2
External old PSW
Supervisor-call old PSW
Program old PSW
Machine-check old PSW
Input/output old PSW
Channel-status word (see diagram)
Channel-address word (see diagram)
Interval timer
Trace-table designation (0 control, 8-31 address)
External new PSW
Supervisor-call new PSW
Program new PSW
Machine-check new PSW
Input/output new PSW
External-interruption parameter for service signal
CPU address associated with external interruption, or
unchanged
CPU address associated with external interruption, or
zeros
External-interruption code (see table)
SVC interruption (0-12 zeros, 13-14 ILC, 15:0, 16-31
code)
16-31 code)
R
DB
EO
EO
EB
F4
FB
FC
100
100
108
10C
160
160
180
180
1CO
1CO
318
PER address {0-7 zeros, 8-31 address)
Monitor code (0-7 zeros, 8-31 code)
Channel ID (0-3 type, 4-15 model, 16-31 max. IOEL
length)
1/0-extended-logout address (0-7 unused, B-31
x
x
address)
Limited channel logout (see diagram)
Measurement byte (0-1 delay, 2-4 count, 5-7 zeros)
1/0 address
Store-status CPU-timer save area
Machine-check CPU-timer save area
Store-status clock-comparator save area
Machine-check clock-comparator save area
Machine-check-interruption code (see diagram)
ExternalMdamage code (see diagram)
Failing-storage address (0-5 zeros, 6-31 address)
Region code*
Store-status PSW save area
Fixed-logout area*
Store-status prefix save area
Store-status model-dependent save area*
Store-status floating-point-register save area
Machine-check floating-point-register save area
Store-status general-register save area
Machine-check general-register save area
Store-status control-register save area
Machine-check control-register save area
CPU identity for DAS tracing
A= Absolute address
L =Logical address
R ~Real address
*Contents may vary among models; see System Library manuals for specific model.
20
CONTROL REGISTERS
~
Bits
0
0
1
2
3
4
5
7
8-12
14
16
17
18
19
20
21
22
24
25
26
1
Name of Field
Associated with
Block-multiplexing control
$SM-suppression control
TOD-clock-sync control
Low-address-protection control
Block multiplexing
SSM instruction
Multiprocessing
Low-address protection
lnit*
Clock comparator
CPU timer
Service signal
Interval timer
Interrupt key
External signals
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
Dynamic address translation
Dynamic address translation
Program interruptions
0
0
0
Extraction-authority control
Instruction authorization
Secondary-space control
Storage-key exception control
Translation format
Instruction authorization
Storage-key 4K-byte block
Dynamic address translation
Vector control
Vector operations
Malfunction-alert subclass mask
Emergency-signal subclass mask
External-call subclass mask
TOD-clock sync-check subclass mask
Clock-comparator subclass mask
CPU-timer subclass mask
Service-signal subclass mask
Interval-timer subclass mask
Interrupt-key subclass mask
External-signal subclass mask
Multiprocessing
Multiprocessing
Multiprocessing
0-7 Primary segment-table length
8-25 Primary segment-table origin
31
Space-switch-event control
Multiprocessing
2
0-31 Channel masks
1/0 interruptions
1
3
0-15 PSW-key mask
16-31 Secondary ASN
Instruction authorization
Address spaces
0
0
4
0-15 Authorization index
16-31 Primary ASN
Instruction authorization
Address spaces
0
0
5
Subsystem-linkage control
0
8-24 Linkage-table origin
25-31 Linkage-table length
Instruction authorization
PC-number translation
PC-number translation
0
0
0
Dynamic address translation
Dynamic address translation
0
0
MC instruction
0
7
0-7 Secondary segment-table length
8-25 Secondary segment-table origin
8 16-31 Monitor masks
9
0
1
2
3
16-31
Successful-branching-event mask
Instruction-fetching-event mask
Storage-alteration-event mask
GR-alteration-event mask
PER general-register masks
Program-event
Program-event
Program-event
Program-event
Program-event
recording
recording
recording
recording
recording
0
0
0
0
0
10
8-31 PER starting address
Program-event recording
0
11
8-31 PER ending address
Program-event recording
0
14
0
1
2
4
5
6
7
8
Machine-check handling
Machine-check handling
1/0 extended logout
Machine-check handling
Machine-check handling
Machine-check handling
Machine-check handling
Machine-check handling
Machine-check handling
Instruction authorization
ASN translation
1
1
0
0
0
1
0
0
0
0
0
8-28 MCEL address
Machine-check handling
512
1-§
Check-stop control
Synchronous-MCEL control
1/0-extended-logout control
Recovery subclass mask
Degradation subclass mask
External-damage subclass mask
Warning subclass mask
Asynchronous-MCEL control
Asynchronous-fixed-logout control
9
ASN-translation control
12
20-31 ASN-first-table origin
*Value after initial CPU reset.
VECTOR-STATUS REGISTER
joooo 0000 0000 ooojMj
0
VCT
1516
VIU
VIX
32
48
VCH
56
63
15 IMI Vector-mask-mode bit
16-31 (VCT) Vector count
32-47 (VIX) Vector interruption index
48-55 (VIUI Vector in-use bits
56-63 (VCH) Vector change bits
21
PROGRAM-STATUS WORD (EC Mode)
Program
mask
0000 0000
24
0000 0000
31
Instruction address
32
40
63
1 ( R) Program-evenuecording mask
5 (T = 1) DAT mode
6 (I) Input/output mask
7 ( E) External mask
12 (C = 11 Extended-control mode
13 (Ml Machine-check mask
14 (W = 1) Wait state
15 (P = 1) Problem state
16 (S = 1) Secondary-space mode
18-19 (CCI Condition code
20 Fixed-point-overflow mask
21 Decimal-overflow mask
22 Exponent-underflow mask
23 Significance mask
PROGRAM-STATUS WORD (BC Mode)
Channe! masks E
7 8
0
ILC
32
PSW
key
cc
34
Interruption code
12
Program
Instruction address
mask
36
31
16
63
40
0-5 Channel 0 to 5 masks
6 Mask for channel 6 and up
7 (E) External mask
12 IC= 0) Basic-control mode
13 (M) Machine-check mask
14 (W = 1) Wait state
15 (P = 11 Problem state
32-33 (I LC) Instruction-length code
34-35 (CC) Condition code
36 Fixed-point-overflow mask
37 Decimal-overflow mask
38 Exponent-underflow mask
39 Significance mask
EXTERNAL-INTERRUPTION CODES
For EC mode, at real storage address 134-135 (hex 86-871
For BC mode, at real storage address 26-27 (hex 1A-1 Bi
Code (binary)
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
Condition
Code (binary)
1eeoeeee Interval timer 00010010 00000000
e 1eeeeee Interrupt key 00010010 00000001
ee 1eeeee External sig 2 00010010 00000010
eee 1eeee External sig 3 00010000 00000011
eeee 1eee External sig 4 00010000 00000100
eeeee 1ee External sig 5 00010000 00000101
eeeeee 1e External sig 6 00100100 00000001
eeeeeee 1 External sig 7
Condition
Malfunction alert
Emergency signal
External call
TOD-clock-sync check
Clock comparator
CPU timer
Service signal
e- if 1, the bit indicates a concurrent external interruption condition.
22
PROGRAM-INTERRUPTION CODES
For EC mode, at real storage address 142-143 (hex BE-BF)
For BC mode, at real storage address 42-43 (hex 2A-2Bl
Code
(hex)
Condition
0001
0002
0003
0004
0005
0006
0007
Operation exception
Privileged-operation exception
Execute exception
Protection exception
Addressing exception
nn08*
nnOF*
Fixed-point overflow exception
Fixed-point divide exception
Decimal-overflow exception
Decimal-divide exception
Exponent-overflow exception
Exponent-underflow exception
Significance 0'xception
Floating-point divide exception
0010
0011
0012
0013
0017
0019
001C
nn1E*
001F
0020
0021
0022
0023
0024
0025
0040
0080
Translation-specification exception
Special-operation exception
ASN-translation specification exception
Vector-operation exception
Space-switch event
Unnormalized-operand exception
PC-translation specification exception
AFX-translation exception
ASX-translation exception
LX-translation exception
EX-translation exception
Primary-authority exception
Secondary-authority exception
Monitor event
PER event (code may be combined with another code)
0009
OOOA
0008
nnOC*
nnOD*
nnOE*
Specification exception
Data exception
Segment-translation exception
Page-translation exception
*Use the Exception-Extension Code table below for bits 0-7 (nn) of the programinterruption code.
EXCEPTION-EXTENSION CODE
I
I
0
7
av w w r r r r
Bit
Meaning
O(a)
Arithmetic-partial-completion bit
0 Completion or suppression of instruction and bits 1-7 of the
exception-extension code are also zero
Partial completion of vector instruction
1 (v)
Arithmetic-result location
0 Scalar register
1 Vector register
2-3(ww) Arithmetic-result width
01 4-byte result
1 0 B-byte result
4-7(rrrr) Register number of result designated by the interrupted instruction
23
DYNAMIC ADDRESS TRANSLATION
Dynamic-Address-Translation Format
Virtual -Address Fields
Cntl Reg 0
Bits8-12
Segment
Size
Page
Size
0
0
1
1
64K
1M
64K
1M
2K
2K
4K
4K
1
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
["" l
0-7
are
ignored
Segment
Index
Page
Index
Byte
Index
8-15
8-11
8-15
8-11
16-20
12-20
16-19
12-19
21-31
21-31
20-31
20-31
Any other combination of bits 8-12 of control register 0 is invalid for translation.
1M-byte segments are not provided on some models; 2K-byte pages are not provided
on some models.
Segment-Table Entry
I
PT length
0
I
0000'
I
4
Page-table origin
29
8
30
31
29 (P) Segment-protection bit.
30 IC) Common-segment bit
31 (I) Segment-invalid bit
*Normally zeros; ignored on some models.
Page-Table Entry (4K)
Page-frame real address
I 1 I EA t?'.J
12 13
0
15
1 2 (I) Page- invalid bit
13-14 (EAi Extended-address bits
Page-Table Entry (2K)
I
Page-frame real address
0
i I 12/J
1
13
O
14
15
13 (I) Page-invalid bit
TRANSLATION-EXCEPTION IDENTIFICATION
At real storage location 144-147 (hex 90-93)
Interruption
Code
0010
0010
0011
0011
001C
0020
0021
0022
0023
0024
0025
24
14K
(2K
(4K
12K
Format of the Information Stored
pg)
pg)
pg)
pg)
0 secondary address, 1-7 zeros, 8-19 address, 20-31 unpredictable
0 secondary address, 1-7 zeros, 8-20 address, 21-31 unpredictable
0 secondary address, 1-7 zeros, 8-19 address, 20-31 unpredictable
0 secondary address, 1-7 zeros, 8-20 address, 21-31 unpredictable
0 old space-switch-event control., 1-15 zeros, 16-31 old PASN
0-1 5 zeros, 16-31 address-space number
0-1 5 zeros, 16-31 address-space number
0-11 zeros, 12-31 program-call number
0-11zeros,12-31 program call number
0-1 5 zeros, 16-31 address-space number
0-1 5 zeros, 16-31 address-space number
DUAL-ADDRESS-SPACE CONTROL
Program-Call Number
Linkage
Entry
index
index
0
12
24
31
Linkage-Table Entry
I I 0000000 I
1
I
Entry-table origin
1
0
8
ETL
26
31
0 Ill LX-invalid bit
26-31 (ETL) Entry-table length
Entry-Table Entry
Authorization
Entry instruction
address
ASN
ke mask
p
16
0
63
Entry
key mask
Entry parameter
64
112
96
127
63(P) Entry problem state
ASN-First-Table Entry
II
ooo 0000
0
I
ASN-secondtable origin
00001
28
8
31
0 ( 11 AFX-invalid bit
ASN-Second-Table Entry
000000
B
0
72
90
48
32
x v
table origin
Authoritytable length
Authorization
index
00
30
Segment-
STL
64
Authoritytab1e origin
Linkagetable origin
000 0000
95 96 97
0000
60
104
63
LTL
121
127
0 (II ASX-invalid bit
64-71 (STL) Segment-table length
95 (XI Space-switch-event bit
96 (V) Subsystem-linkage control
121-127 (LTL) Linkage-table length
Trace-Table-Entry Header
First-entry
control
Current-entry
control
0
32
Last-entry
control
64
95
25
MACHINE-CHECK INTERRUPTION CODE
At real storage address 232-239 (hex E8-EF)
S P S T C EVD
V
SSKDWMPIFRE
GCLS
0 0 S B D E C E S P S M A A C C P R R G T
DDRDDDFGWO
0
10
13
31
MCEL Length
0 0 0 0 0 0 0 0 0
32
34
46
48
63
Bit
Meaning
0
1
(SD) System damage
(PD) Instruction-processing damage
(SR) System recovery
(TD) Interval-timer damage
(CD) Timing-facility damage
(ED) External damage
(VF) Vector-facility failure
(DG) Degradation
(W) Warning
(SP) Service-processor damage
(VS) Vector-facility source
(B) Backed up
(D) Delayed
(SE) Storage error uncorrected
(SC) Storage error corrected
2
3
4
5
6
7
8
10
13
14
15
16
17
18
19
(KE) Storage-key error uncorrected
20
21
22
23
24
25
26
27
28
29
30
31
32
34
46
47
48-63
(OS) Storage degradation
(WP) PSW-CMWP validity
(MS) PSW mask and key validity
(PM) PSW program-mask and condition-code validity
(IA) PSW-instruction-address validity
(FAI Failing-storage-address validity
(RC) Region-code validity
(EC) External-damage-code validity
(FP) Floating-point-register validity
(GR) General-register validity
(CR) Control-register validity
(LG) Logout validity
(ST) Storage logical validity
(IE) Indirect storage error
(DA) Delayed access exception
(CTI CPU-timer validity
ICC) Clock-comparator validity
Machine-check-extended-logout (MCEL) length
EXTERNAL-DAMAGE CODE
At real storage address 244-247 (hex F4-F7)
OO ECC S T
S NC T T
0
2
0000
8
0000
10
Bit
Meaning
2
3
4
5
6
8
9
(ES) External secondary report
(CN) Channel not operational
(CC) Channel-control failure
(ST) 1/0-instruction timeout
(TT) 1/0-interruption timeout
(XN) Expanded storage not operational
(XFI Expanded storage control failure
26
0000
0000
0000
31
CHANNEL-ADDRESS WORD
At real storage address 72-75 (hex 48-4BJ
I Key isl ooo
Channel-Program Address
4
0
8
31
4 (SJ Suspend-control bit
CHANNEL-COMMAND WORD
I Command code
0
Data address
8
31
Byte count
Flags
32
48
39 40
63
CO - bit 32 (80) causes use of data-address portion of next CCW.
CC - bit 33 (40) causes use of command code and data address of next CCW.
SLI - bit 34 (20) causes suppression of possible incorrect-length indication.
Skip -
bit 35 ( 10) suppresses transfer of information to main storage.
PCI - bit 36 .(08) causes a channel-program-controlled interruption.
\DA - bit 37 (04) causes bits 8-31 of CCW to specify location of first \DAW.
Suspend - bit 38 (02) causes suspension before execution of this CCW.
CHANNEL-STATUS WORD
At real storage address 64-71 (hex 40-471
IL Icc
I Key
is
0
4 5 6
Unit status
32
j
CCW address
8
31
j Channel status
40
Byte count
48
4 Suspended (only in CSW stored by PC\)
5 Logout pending
6- 7 Deferred condition code
32 (801 Attention
33 (40) Status modifier
34 1201 Control-unit end
35 1101 Busy
36 (081 Channel end
37 (041 Device end
38 (021 Unit check
39 101 I Unit exception
63
40 (80) Program-controlled interruption
41 (40) Incorrect length
42 1201 Program check
43 I 1 OJ Protection check
44 (08) Channel-data check
45 (04) Channel-control check
46 (021 Interface-control check
47 (01 J Chaining check
48-63 Residual byte count for the
last CCW used
LIMITED CHANNEL LOGOUT
At real storage address 176-179 (hex BO-BCJ
I0 I SCU id IDetect I Source loo !Field validity flags! TT IO I1A j
0
1
4
8
CPU
Channel
Main-storage control
Main storage
8 CPU
9 Channel
10 Main-storage control
11 Main storage
12 Control unit
15 Full channel logout
16-18 Reserved (000)
19 Sequence code
4
5
6
7
13 15
24
26 27
29
Seq_
31
20 Unit status
21 CCW address and key
22 Channel address
23 Device address
24-25 Type of termination
00 Interface disconnect
01 Stop, stack or normal
1 0 Selective reset
11 System reset
27 (I) Interface inoperative
28 IA) 1/0-error alert
29-31 Sequence code
27
1/0 COMMAND CODES
Standard Command-Code Assignments (CCW bits 0-71
xx xx
mmmm
mm mm
0000
mm mm
0000
0000
mm01
mml 0
0010
mml 1
00 1 1
mm mm 0 100 Sense
0000 0 100 - Basic Sense
111 0 0 100 - Sense ID
xx xx
000 Transfer in Channel
mm mm 1 100 Read Backward
Invalid Command
Write
Read
-Read IPL
Control
- Control No
Operation
x - Bit ignored
m - Modifier bit for specific type of 1/0 device
Standard Meanings of Bits of First Sense Byte
Bit
0
1
2
3
Designation
Command reject
Intervention required
Bus-out check
Equipment check
Bit
Designation
4
5
6
Data check
Overrun
(Device-dependent)
7
(Device-dependent)
Console Printer Channel Commands
Write, No Carrier Return
Write, Auto Carrier Return
Read Inquiry
01
09
OA
04
OB
03
Sense
Audible Alarm
No Operation
Card Reader and Card Punch Channel Commands
3504, 3505 Card Readers/3525 Card Punch (GA21-91241
Channel Commend
Binary
Sense
Feed, Select Stacker
Read Only*
Diagnostic Read (invalid for 35041
Read, Feed, Select Stacker•
Write RCE Format*
0000
SS10
11 DO
1 101
SSDO
0001
0100
F 011
F010
0010
F010
0001
3504, 3505 only
Write OMR Formatt
0011
0001
Bit MeaninQa
SS
Stacker
--100
01/10
2
F
Format Mode
0
Unformatted
Formatted
D
Data Mode
1-EBCDIC
2-Card image
0
3525 only
Write, Feed, Select Stacker
Print Line*
1
SSDO
LLLL
0001
L 101
Lirie Position
l5-bit binary value)
*Special feature on 3525.
28
tSpecial feature.
1/0 COMMAND CODES (Cont'd)
Printer Channel Commands
COMMANDS VALID FOR ALL PRINTERS
(Except 3800-3, -6 when in Page Model
No Operation
Space 1 Line Immediate
Space 2 Lines Immediate
Space 3 Lines Immediate
Block Data Check
Allow Data Check
Skip to Channel 1 Immediate
Skip to Channel 2 Immediate
Skip to Channel 3 Immediate
Skip to Channel 4 Immediate
Skip to Channel 5 Immediate
Skip to Channel 6 Immediate
Skip to Channel 7 Immediate
Skip to Channel 8 Immediate
Skip to Channel 9 Immediate
Skip to Channel 10 Immediate
Skip to Channel 11 Immediate
Skip to Channel 12 Immediate
03
OB
13
1B
73
7B
BB
93
9B
A3
AB
B3
BB
C3
CB
03
DB
E3
Write Without Spacing
Write and Space 1 Line
Write and Space 2 Lines
Write and Space 3 Lines
Write and Skip to Channel
Write and Skip to Channel
Write and Skip to Channel
Write and Skip to Channel
Write and Skip to Channel
Write and Skip to Channel
Write and Skip to Channel
Write and Skip to Channel
Write and Skip to Channel
Write and Skip to Channel
Write and Skip to Channel
Write and Skip to Channel
01
09
11
19
B9
91
99
A1
A9
B1
B9
C1
C9
01
09
E1
1
2
3
4
5
6
7
8
9
10
11
12
Basic Sense
04
3B00~3,
-6 PAGE MODE COMMANDS
(See Note Y)
No Operation
Load Font Index
Load Font Control
Load Font
Execute Order Any State
load Font Equivalence
Delete Font
Begin Page Segment
Delete Page Segment
Include Page Segment
Execute Order Home State
Set Home State
Load Copy Control
Begin Page
End Page
Load Page Description
Begin Overlay
Delete Overlay
03
OF
1F
2F
33
3F
4F
5F
6F
7F
BF
97
9F
AF
BF
CF
OF
EF
Write Factored Text Control
Write Text
Write Image Control
Write Image
End
Load Page Position
OD
Basic Sense
Sense Intermediate Buffer
Sense Error Log
Sense ID
04
14
24
E4
20
30
40
50
60
IMPACT PRINTERS - ADDITIONAL COMMANDS
Column Reference
Printer
1403-Nl
GA24~331 2
A
GA33-1515
3203-1' -2
B
3203-4
c GA33-1515
3203-5
c GA33-1529
3211
c GA24-3543
4248-1<3211 mode>
c GA24-3927
4248-2<3211 mode:>
c GA24-3991
3262-1' -11
D
GA24-3733
3262-5 <3262-1 mode>
GA24-3936
D
4245-1
GA33-1541
D
4245- 1 2, -20
D
GA33-1579
4245-01 2, ~020
D
GA33-15B6
3262-5 <4248 mode>
E
GA24-3936
4248-1
E
GA24-3927
4248 .. 2
GA24-3991
E
6262-014
GA24A134
E
Use column A, B, C, D, or E.
Unfold
Execute Order
Fold
Advance to End of Sheet
Load Forms Control Buffer
Raise Cover
Signal Attention
Skip to Channel 0 Immediate
Clear Printer
UCS Gate Load
Load UCS Buffer and Fold
Verify Band ID
Load UCS Buffer (No Fold)
Verify Band 10
Release CU and Device
Sense Intermediate Buffer
Release CU, Reserve Device
Reserve CU, Release Device
Reserve CU and Device
Release Device
Reserve Device
Release CU
Sense ID
Reserve CU
Read Band ID
ABC DE
23
33
43
5B
63
[6B
6B
B3
B7
EB
F3
F3
c
c
c ~:
F8
FB
.xxx
.x
.XXX
. x.
.xxxx
, 2
3
- 4 . 2
.xx
X2.
xx.
.x
xx xx
x
5 .
.
5 .
5 .
5
5
5
5
E4
F4
- X . XX
5 .
l.OA
x
.
.
.
Diagnostic Read PLB
02 X.X62
Diagnostic Write
05 7 . B 6 2
Diagnostic Check Read
06 X.XX2
Diagnostic Gate
07
.XX2
Diagnostic Read UCS Buffer
OA
Diagnostic Read FCB
12
X = Valid; . = Invalid; Blank = NIA
1 = No action occurs {except 3211 ).
2 = No action occurs.
3 = No action occurs on 3262-5.
4 = 3211 only (no action occurs on 4248
<3211 mode> and 3203-4).
5 = Two-channel switch feature only.
6 = No action occurs (except 4245).
7 = 1403-N1 also uses command codes OD, 15,
1 D, BO, 95, 90, A5, AD, 65, SD, C5, CD, 05,
DD, and E5.
8 == 3211 and 4248 < 3211 mode> only.
.xx
_xxx
3BOO ~ ADDITIONAL COMMANDS
(Except 3800-3, -6 when in Page Mode; see Note X)
End of Transmission
Mark Form
Load Copy Number
Execute Order Any State
Initialize Printer
Load~Forms Overlay Seq Control
07
17
23
33
37
43
3800-1 Reference: GA26-1635
3800-3, -6 Reference: GA32-0050
Select Translate Table O
47
Select Translate Table 1
57
Note X: For 3800-3, -6 only, Set Home
State (97) command will be accepted,
but with command retry; the retry will
succeed because Page Mode will have
been set.
Load Forms Control Buffer
63
Select Translate Table 2
67
Select Translate Table 3
Load Translate Table
Clear Printer
Load Graphic Char Modification
load Copy Modification
Sense Intermediate Buffer
Sense Error Log
Sense ID
77
83
B7
25
35
14
24
E4
--------------<
Note Y: Other 3800-3, -6 commands
accepted, but with command retry; the
retry wilt succeed because Page Mode
will have been reset.
x
34
54
74
94
B4
04
Load Writable Char Gen Module
53
29
1/0 COMMAND CODES (Cont'd)
Magnetic-Tape Channel Commands
3420-3 3420-4
Hex
3410 3420-5 3420-6 3422
8809
Code 3411 3420-7 3420-8 3430 3480 9347
03
07
OF
Modeset-1 (200/0dd/OC)
(a)
lb)
(cl
le)
r::13
Set Long Gap
13
Erase Gap
17
Request Track-In-Error
1B
(d)
Write Tape Mark
1F
Modeset-1 1200/Even/Normal)
(al
(bl
lei
lei
c::23
Set Normal Gap
23
Backspace Block
27
Modeset-1 (200/Even/TRI
2B
(al
lb)
(cl
lei
Backspace File
2F
Modeset-1 1200/0dd/Normall
la)
(c)
(bl
lei
c:33
Set High Speed/Normal Gap
33
Forward Space Block
37
Modeset-1 1200/0dd/TR)
3B
(al
lb)
lei
lei
Forward Space File
3F
Synchronize
43
Locate Block
4F
Modeset-1 (556/0dd/DCI
la)
(al
lei
lei
c53
Set Low Speed/Long Gap
53
Suspend Multipath Reconnection
5B
lei
Modeset-1 (556/Even/Normall
(a)
(al
le)
lei
c:63
Set Low Speed/Normal Gap
63
(a)
Modeset-1 1556/Even/TRI
6B
(al
lei
lei
Modeset-1 1556/0dd/Normal)
la)
(c)
(al
73
lei
Modeset-1 (556/0dd/TRI
la)
la)
(c)
7B
lei
Set Low Speed
83
Modeset-1 (800/0dd/DC)
(a)
(al
lei
lei
c:93
Set High Speed/Long Gap
93
Data Security Erase
97
Load Display
9F
Modeset-1 (800/Even/Normall
la)
A3 (a)
(cl
lei
Modeset-1 (800/Even/TRI
(a)
AB (a)
lei
lei
Set Path Group ID
AF
(a)
Modeset-1 (800/0dd/Normal)
(c)
B3
(al
lei
Assign
B7
(a)
Modeset-1 (800/0dd/TRI
BB
(al
lei
lei
Modeset-2 (1600 bpi PEI
le)
If)
lei
lei
c:C3
Set Tape-Write-Immediate
C3
Channel Command
No Operation
Rewind
Rewind Unload
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Unassign
Modeset-2 (800 bpi NRZI)
Modeset-2 16250 bpi GCRI
Mode Set
Cl
CB
D3
DB
c:E3
E3
lei
Write
01
Read
x
x
x
x
x
x
Read Block ID
02
12
22
x
x
x
x
x
x
x
x
x
x
lg)
(g)
(g)
lg)
(g)
lg)
x
x
x
x
x
x
(di
Control Access
Set High Speed
Read Buffer
Read Backward
oc
Basic Sense
Read Buffered Log
Sense Path Group ID
Read/Reset Buffered Log
Release
Sense ID
Reserve
04
24
34
A4
D4
E4
F4
Diagnostic Mode Set
Set Diagnose
Loop Write-To-Read
OB
4B
8B
lei
lei
If)
x
x
x
lei
lei
x
x
-
x
x
x
x
x
x
x
x
x
-
x
x
x
x
x
x
x
x
x
Notes:
a No action occurs unless 7-track feature is installed.
b No action occurs unless 7-track feature is installed; if present, density set is 200
bpi by 3803-2 Tape Control, 556 bpi by 3803-1.
c Valid command, but no action occurs.
d Invalid command for 3422.
No action occurs unless 800 bpi density feature is installed.
No action occurs unless 1600 bpi density feature is installed.
g Requires two-channel switch feature; invalid for 3430.
Where arrows appear, the meaning of the hex code depends on the machine type;
hyphens signify that the alternative meaning is used.
Modeset-1 command (for 7-track drives): density (200, 556, 800 bpi)/parity (even,
odd)/mode (Normal, DC=data converter, TR=translator). Modeset-2 command (for
9-track drives): density 1800, 1600, 6250 bpi).
Sources:
3410/3411 IGA32-0022l
3420-3, -5, -7 IGA32-00201
3420-4, -6, -8 IGA32-0021 I
30
3422 IGA32-00891
3430 IGA32-00761
3480 iGA32-0042)
8809 IGA26-1659)
934 7 ISA24-4096)
1/0 COMMAND CODES (Cont'd)
Direct Access Storage Devices
Use these charts to find the proper column in the DASO Channel Commands table
and to find order numbers for DASO reference manuals. See DASO manuals for
the restrictions and details of operations.
Count/Key/Data Devices
2305
Controller
DASD-A4
DASD-A6
DDA-30
DDA-40
IFA
ISC
ISC-SA
2835-2
3380-CJ2
3830-1
3830-2
3830-3
3880-1
3880-2
3880-3
3880-4
3880-11 IND)
3880-11 (PD)
3880-11 (PP)
3880-13
3880-21 (PD)
3880-21 !PP)
3880-23
3990-1,2,3
3380
-0-A
3380
-D-E
-J-K
col2
col2
col2
col2
co12
col2
col2
col2
col2
col2
col2
col1
*col5
*col2
col2
col2
col2
col2
col2
col2
col2
col2
col2
col2
co12
col4
col4
col4
col4
col4
col4
col2
col2
col2
col3
col5
col2
col3
*col5
*col5
col5
col5
Controller
Manual
GA33-1526
GA33-1566
GA33-1510
GA33-1506
GA24-3632
GA26-1620
GA32-0036
GA26-1589
GC26-4497
GA26-1592
GA26-1617
GA32-0036
GA26-1661
GA26-1661
GA26-1661
GA26-1661
GA32-0061
GA32-0061
GA32-0061
GA32-0067
GA32-0081
GA32-0081
GA32-0083
GA32-0099
4321/4331 DASO Adapter for 3340/3344
4361 DASO Adapter for 3340/3344
S/370 125-0, -2 3330/3333 Direct Disk Attachment
S/370 115-0, -2, 125-0, -2 3340/3344 Direct Disk Attachment
S/370 138 Integrated File Adapter
Integrated Storage Controller
Integrated Storage Controller with Staging Adapter
Nonpaging director
Paging director, direct mode
Paging director, paging mode
3380 Direct Access Storage Models AA4, A04, and 804
= 3380 Direct Access Storage Models AD4, AE4, 804, and BE4
= 3380 Direct Access Storage Models AJ4, AK4, BJ4, and BK4
= 3333 does not attach to 3830-1; 3380-A04 does not attach to
3880-23 or 3990; only 3380-BJ4 and -BK4 attach to 3380-CJ2
3310
DASD-A1
DASD-A7
DTSC
3880-1
3880-2
3880-4
col6
Device
3375
=
=
=
=
=
=
=
=
=
=
=
Controller
Manual
3350
GA26 GA26 GA26 GA26 GA26 GC26 GC26
1589 1615 1619 1638 1666 4491 4491
Device
Manual
DASD-A4
DASD-A6
DDA-30
DDA-40
IFA
ISC
ISC-SA
ND
PD
PP
3380-0-A
3380-D-E
3380-J-K
3330 3340
3333 3344
FBA Devices
9332 9332
-400 -402
3370 -600 -602 9335
col6
col6
col6
col6
col6
col6
col6
Controller
Manual
GA26-1660
GA33-1539
SA24-4096
GA26-1661
GA26-1661
GA26-1661
GA26 GA26 GA21 GA21 SA33
1660 1657 9837 9545 3143
DASD-A1 = 4321/4331/4361 DASO Adapter for 3310
DASD-A7 = 4321/4331/4361 DASO Adapter for 3370
DTSC
= ES/9370 DASO/Tape Subsystem Controller
31
1/0 COMMAND CODES (Cont'd)
DASO Channel Commands
3310
3370 Typlcal
3375
9332 Tranafer
3380 3380 9336 Count
3330
Hex
3340
Code 2305 3350
~50
1
2
3
4
6
8
03
07
OB
OF
13
17
1B
1F
23
27
27
2B
3B
43
47
5B
63
87
BB
BF
AF
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1•F1I
29
31
39
49
51
69
71
Read Initial Program Load
Read Data
("86)
Read Key & Data
1•8EI
Read Count
1•921
Read Record Zero
1"961
(•9AI
Read Homa Address
Read Count Key & Data
(*9El
Read Sector (3340 RPS is optional)
Read Subsystem Data
Read
Read Message ID
Read Multiple Count Key & Data
Read Track
Read Configuration Data
02
06
OE
12
16
1A
1E
22
3E
42
4E
5E
DE
FA
Channel Commend
Control
No Operation
Seek
Seek Cylinder
Space Count
Recalibrate (No Op on 2305-2)
Restore (executed as No-Op)
Seek Head
Set File Mask
Set Sector (3340 RPS is optional)
Vary Sensing
Perform Subsystem Function
Orient (No-Op on 2305-2)
Set High Performance Storage Limits
Locate
locate Record
Suspend Multipath Reconnection
Define Extent
Set Subsystem Mode
Set Paging Parameters
Discard Block
Set Path Group ID
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
6
6
3
None
None
6
1
1
1
(x)
x
lal
lb)
ldl
(bl
la)
x
(C)
x
x
x
(u)
x
x
(d)
x
x
x
x
x
None
Variable
None
10
8
16
None
16
2
10
2+(5xn)
12
Search
Search
Search
Search
Search
Search
Search
Key Equal
ID Equal
Home Address Equal
Key High
ID High
Key Equal or High
Search ID Equal or High
1•A91
1·B11
1•B91
1·c91
1•011
(*E9)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
KL
5
4
KL
5
KL
5
x
x
x
x
Read
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Ix)
x
(f,gl
x
x
x
x
(y)
x
(w)
(x)
DL or 512
DL
KL+DL
8
B+KL+DL
5
B+KL+DL
1
Variable
512 xn
11
nx(B+KL+DLI
Variable
256
Write
Write
Write
Write
Erase
Write
Write
Write
Write
Write
Write
Write
Special Count Key & Data
Data
Key & Data
Record Zero
Home Address
Count Key & Data
Update Data
Update Key & Data
Count Key & Data Next Track
01
05
OD
11
15
19
10
41
85
80
90
x
x
x
x
x
x
x
x
x
x
x
x
x
1
32
x
x
2
3
x
x
x
x
x
x
x
x
(b)
(bl
lb)
lei
(el
lei
4
5
x
x
x
x
x
8
B+KL+DL
DL
KL+DL
B+KL+DL
B+KL+DL
5, 7, or 11
B+KL+DL
512 xn
DL
KL+DL
8+KL+DL
1/0 COMMAND CODES (Cont'd)
DASO Channel Commands (Cont'd)
3310
3370 Typical
3330
3340
3375
9332 Transfer
Hex
Code 2305 3350 fil50 3380 3380 9335 Count
Channel Command
1
2
3
x
x
4
5
6
x
x
x
(m,p)
Sense
Basic Sense
Unconditional Reserve
(h,j,kl
Read Buffered Log
Sense Path Group ID
Reset Allegiance
Sense Subsystem Status
Read Device Characteristics
Sense Subsystem Counts
Device Release
Read and Reset Buffered Log
Device Reserve
Sense ID
(g,j)
(gl
(g,j)
04
14
24
34
44
54
64
74
94
A4
B4
lf,gl
E4
(kl
(kl
(kl
09
OA
44
53
73
C4
F3
x
(d,m,
(m,p)
x
(di
x
lwl
(q)
x
(q)
(V(
lei
lpl
lm,p)
(d,m,
pl
x
lpl
x
24 or 32
24 or 32
p)
x
x
x
x
x
x
x
x
x
x
(d,m,
(m,p)
x
x
p)
128
12
32
40
x 32
80
(m,p) 24
x
(m,p)
x
24 or 32
24 or 32
7
Diagnostic
Diagnostic Write Home Address
Diagnostic Read Home Address
Diagnostic Sense II
Diagnostic Load
Diagnostic Write
Diagnostic Sense/Read
Diagnostic Control
x
x
x
Valid only for 3880-13
Speed matching buffer feature
Not valid for 3880-13
Dynamic path selection (only valid on
3380-AA4, -AD4, -AE4, -AJ4, -AK4 strings)
Valid only for 3880-21
Not valid for 3330/3333 on ISC-SA or
3830-1; 3830-2, -3, DDA-40, IFA, and
ISC require 3344/3350 microcode
Not valid on DDA-30
Not valid on IFA, !SC-SA, or 3830-1;
not valid on 3330/3333, 3340/3344
Executed as Basic Sense on DASO-A 1,
-A4, -A6, -A 7 if no string switch (for
Unconditional Reserve, see note g)
Not valid on DDA-30, -40, DASD-A4, -A6
27 or 28
16 or 512
1
i'l
1,1
x
Isl
(ti
1
27 or 28
(')
3
2
m
p
q
u
v
w
x
#
(ti
x
x
x
x
4
5
6
8 or 512
Variable
4+n
String-switching feature
Channel-switching feature
Valid only for 3880- 11 paging director and
3880-21
Not valid on 3880-21
Valid only for 3880-1, -2, -11, -21
Valid only for 3330/3350 on 3880-1, -2, and
for 3380 on 3880-2, -3 without 3380-speedmatching-bufter feature
Valid only for 3880-13, -23, and 3990-3
Valid only for 3880-13, -23
Not valid for 3880-13, -23
Valid only for 3990
Valid only for 3990-3
Multitrack command codes (standard)
Also called "Read Diagnostic Status 1"
33
CODE ASSIGNMENTS
Code Tables
Dec.
Hex
Graphics and Controls
BCDIC EBCDIC
ASCII
7~Track
Tape
BCDIC
Card Code
EBCDIC
Binary
0
1
2
3
00
01
02
03
NUL
SOH
STX
ETX
NUL
SOH
STX
ETX
12-0-1-8-9
12-1-9
12-2-9
12-3-9
0000
0000
0000
0000
0000
0001
0010
0011
4
5
6
7
04
05
06
07
SEL
HT
RNL
DEL
EQT
ENO
ACK
BEL
12-4-9
12-5-9
12-6-9
12-7-9
0000
0000
0000
0000
0100
0101
0110
0111
8
9
10
11
08
09
OA
OB
GE
SPS
RPT
BS
HT
LF
VT
VT
12-8-9
12-1-8-9
12-2-8-9
12-3-B-9
0000
0000
0000
0000
1000
1001
1010
1011
12
13
14
15
QC
OD
OE
OF
so
so
SI
SI
12-4-8-9
12-5-8-9
12-6-8-9
12-7-8-9
0000
0000
0000
0000
1100
1101
1110
1111
16
17
18
19
10
11
12
13
OLE
DC1
DC2
DC3
OLE
DC1
OC2
DC3
12-11-1-8-9
11-1-9
11-2-9
11-3-9
0001
0001
0001
0001
0000
0001
0010
0011
20
21
22
23
14
15
16
17
RES/ENP
NL
BS
POC
DC4
NAK
SYN
ETB
11-4-9
11-5-9
11-6-9
11-7-9
0001
0001
0001
0001
0100
0101
0110
0111
24
25
26
27
18
19
1A
1B
CAN
EM
UBS
CU1
CAN
EM
SUB
ESC
11-8-9
11-1-8-9
11-2-8-9
11-3-8-9
0001
0001
0001
0001
1000
1001
1010
1011
28
29
30
31
1C
10
1E
1F
IFS
IGS
IRS
ITB/IUS
FS
GS
RS
11-4-8-9
11-5-8-9
11-6-8-9
11-7-8-9
0001 1100
0001 1101
0001 1110
0001 1111
32
33
34
35
20
21
22
23
DS
SP
11-0-1-8-9
0-1-9
0-2-9
0-3-9
0010
0010
0010
0010
0000
0001
0010
0011
36
37
38
39
24
25
26
27
BYP/INP
LF
ETB
ESC
0-4-9
0-5-9
0-6-9
0-7-9
0010
0010
0010
0010
0100
0101
0110
0111
40
41
42
43
28
29
2A
2B
SA
SFE
SM/SW
CSP
0-8-9
0-1-8-9
0-2-8-9
0-3-8-9
0010
0010
0010
0010
1000
1001
1010
1011
44
45
46
47
2C
20
2E
2F
MFA
ENO
ACK
BEL
0-4-8-9
0-5-8-9
0-6-8-9
0-7-8-9
0010
0010
0010
0010
1100
1101
1110
1111
48
49
50
51
30
31
32
33
0011
0011
0011
0011
0000
0001
0010
0011
52
53
54
55
34
35
36
37
SYN
IR
pp
TRN
NBS
EQT
12-11-0-1-8-9
1-9
2-9
3-9
4-9
5-9
6-9
7-9
0011
0011
0011
0011
0100
0101
0110
0111
56
57
58
59
38
39
3A
3B
SBS
IT
RFF
CU3
8-9
1-8-9
2-8-9
3-8-9
0011
0011
0011
0011
1000
1001
1010
1011
60
61
62
63
3C
30
3E
3F
DC4
NAK
4-8-9
5-8-9
6-8-9
7-8-9
0011
0011
0011
0011
1100
1101
1110
1111
34
FF
CR
sos
FS
wus
FF
CR
us
I
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#
$
%
&
.
(
I
+
-
I
0
1
2
3
4
5
6
7
8
9
:
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<
~
>
SUB
?
CODE ASSIGNMENTS (Cont'd)
Code Tables (Cont'd)
Dec.
Hex
64
65
66
67
40
41
42
43
6B
69
70
71
44
45
46
47
72
4B
49
4A
4B
73
74
75
Graphics and Controls
BCDIC EBCDIC(1) ASCII
SP
X1)
7B
79
BO
B1
B2
B3
50
51
52
53
&+
B4
B5
B6
B7
54
55
56
57
BB
B9
90
91
5B
59
5A
58
92
93
94
95
5C
50
5E
5F
77
96
97
9B
99
60
61
62
63
100
101
102
103
64
65
66
67
104
105
106
107
6B
69
6A
6B
10B
109
110
111
6C
60
6E
6F
112
113
114
115
70
71
SP
(3)
c
0000
0001
0010
0011
0
E
F
G
12-0-4-9
12-0-5-9
12-0-6-9
12-0-7-9
0100
0100
0100
0100
0100
0101
0110
0111
H
12-0-B-9
12-1-B
12-2-B
12-3-B
0100
0100
0100
0100
1000
1001
1010
1011
12-4-B
12-5-B
12-6-B
12-7-B
0100
0100
0100
0100
1100
1101
1110
1111
12
12-11-1-9
12-11-2-9
12-11-3-9
0101
0101
0101
0101
0000
0001
0010
0011
12-11-4-9
12-11-5-9
12-11-6-9
12-11-7-9
0101
0101
0101
0101
0100
0101
0110
0111
12-11-B-9
11-1-B
11-2-B
11-3-B
0101 1000
0101 1001
0101 1010
0101 1011
11-4-B
11-5-B
11-6-B
11-7-B
0101
0101
0101
0101
1100
1101
1110
1111
11
0-1
11-0-2-9
11-0-3-9
0110
0110
0110
0110
0000
0001
0010
0011
11-0-4-9
11-0-5-9
11-0-6-9
11-0-7-9
0110
0110
0110
0110
0100
0101
0110
0111
11-0-B-9
0-1-B
12-11
0-3-B
0110
0110
0110
0110
1000
1001
1010
1011
0-4-B
0-5-B
0-6-B
0-7-B
0110
0110
0110
0110
1100
1101
1110
1111
12-11-0
12-11-0-1-9
12-11-0-2-9
12-11-0-3-9
0111
0111
0111
0111
0000
0001
0010
0011
12-11-0-4-9
12-11-0-5-9
12-11-0-6-9
12-11-0-7-9
0111
0111
0111
0111
0100
0101
0110
0111
12-11-0-B-9
1-B
2-B
3-B
0111 1000
0111 1001
0111 1010
0111 1011
4-B
5-B
6-B
7-B
0111
0111
0111
0111
¢
J
K
<
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L
M
N
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BAB4
BAB4
1
BAB42
BAB421
p
BA
[
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BAB
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v
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x
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4
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72
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116
117
11B
119
74
75
76
t
120
121
122
123
7B
79
7A
78
124
125
126
127
7C
70
7E
7F
2 1
u
v
w
77
x
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0100
0100
0100
0100
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EBCDIC
no punches
12-0-1-9
12-0-2-9
12-0-3-9
@
A
B
I
4C
40
4E
4F
76
SP
RSP
7-Track Tape
BCDIC(2)
-
DEL
1100
1101
1110
1111
35
CODE ASSIGNMENTS (Cont'd)
Code Tables (Cont'd)
Graphics and Controls
Dec.
Hex
12S
129
130
131
so
S1
S2
S3
a
b
c
132
133
134
135
S4
S5
S6
B7
d
d
e
e
f
g
f
g
136
137
13B
139
BB
B9
BA
BB
h
i
h
i
140
141
142
143
BC
SD
BE
SF
144
145
146
147
90
91
92
93
14B
149
150
151
94
95
96
97
152
153
154
155
9B
99
9A
9B
156
157
15B
159
9C
9D
9E
9F
160
161
162
163
AO
A1
A2
A3
164
165
166
167
BCDIC
EBCDIC(l)
ASCII
7-Track Tape
BCDIC
Binary
12-0-1-S
12-0-1
12-0-2
12-0-3
1000
1000
1000
1000
0000
0001
0010
0011
12-0-4
12-0-5
12-0-6
12-0-7
1000
1000
1000
1000
0100
0101
0110
0111
12-0-B
12-0-9
12-0-2-B
12-0-3-B
1000
1000
1000
1000
1000
1001
1010
1011
+
12-0-4-B
12-0-5-S
12-0-6-B
12-0-7-S
1000
1000
1000
1000
1100
1101
1110
1111
j
k
I
j
k
I
12-11-1-8
12-11-1
12-11-2
12-11-3
1001
1001
1001
1001
0000
0001
0010
0011
m
m
n
n
0
0
12-11-4
12-11-5
12-11-6
12-11-7
1001
1001
1001
1001
0100
0101
0110
0111
12-11-B
12-11-9
12-11-2-B
12-11-3-B
1001
1001
1001
1001
1000
1001
1010
1011
12-11-4-B
12-11-5-B
12-11-6-B
12-11-7-B
1001
1001
1001
1001
1100
1101
1110
1111
11-0-1-B
11-0-1
11-0-2
11-0-3
1010
1010
1010
1010
0000
0001
0010
0011
11-0-4
11-0-5
11-0-6
11-0-7
1010
1010
1010
1010
0100
0101
0110
0111
11-0-B
11-0-9
11-0-2-B
11-0-3-S
1010
1010
1010
1010
1000
1001
1010
1011
11-0-4-B
11-0-5-S
11-0-6-S
11-0-7-B
1010
1010
1010
1010
1100
1101
1110
1111
12-11-0-1-B
12-11-0-1
12-11-0-2
12-11-0-3
1011
1011
1011
1011
0000
0001
0010
0011
12-11-0-4
12-11-0-5
12-11-0-6
12-11-0-7
1011
1011
1011
1011
0100
0101
0110
0111
12-11-0-S
12-11-0-9
12-11-0-2-S
12-11-0-3-S
1011
1011
1011
1011
1000
1001
1010
1011
12-11-0-4-S
12-11-0-5-S
12-11-0-6-S
12-11-0-7-S
1011
1011
1011
1011
1100
1101
1110
1111
a
b
c
{
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)>
2
c
cm
(")
5
1,342,177,280
5
83,886,080
5
5,242,880
5
327,680
5
20.480
5
1,280
5
80
5
5
6
1,610,612,736
6
100,663,296
6
6,291,456
6
393,216
6
24,576
6
1,536
6
96
6
6
7
1,879,048,192
7
117.440,512
7
7,340,032
7
458,752
7
28,672
7
1,792
7
112
7
7
....)>
31:
B
2, 147,483,648
8
134,217,728
B
8,388,608
8
524,288
8
32,768
8
2,048
8
128
8
8
(")
9
2.415,919, 104
9
150,994,944
9
9.437, 1 B4
9
589,824
9
36,864
9
2,304
9
144
9
9
0
A
2,684,354,560
A
167,772, 160
A
10,485,760
A
655,360
A
40,960
A
2,560
A
160
A
10
B
2,952, 790,016
B
184,549,376
B
11 ,534,336
B
720,896
B
45,056
B
2.B16
B
176
B
11
c
3,221,225.472
c
201,326,592
c
12,582,912
c
786,432
c
49,152
c
3,072
c
192
c
12
D
3.489,660,928
D
218.103,808
D
13,631,488
D
851,968
D
53,248
D
3,328
D
208
D
13
E
3,758,096,384
E
234,881 ,024
E
14,680,064
E
917,504
E
57,344
E
3,584
E
224
E
14
F
4,026,531 ,840
F
251 ,658,240
F
15,728,640
F
983,040
F
61,440
F
3,840
F
240
F
8
co
BYTE
0123
Decimal
~
HALFWORD
HALFWORD
7
6
5
4
3
2
15
1
z
<
m
:a
en
5
z
HEXADECIMAL AND DECIMAL CONVERSION (Cont'd)
Powers of 2 and 16
m
n
2'" and 16"
m
n
2'" and 16"
0
1
2
3
0
1
2
4
8
32
33
34
35
8
4
8
17
34
294
589
179
359
967
934
869
738
296
592
184
368
4
5
6
7
1
16
32
64
128
36
37
38
39
9
68
137
274
549
719
438
877
755
476
953
906
813
736
472
944
888
8
9
10
11
2
256
512
1 024
2 048
40
41
42
43
10
1
2
4
8
099
199
398
796
511
023
046
093
627
255
511
022
776
552
104
208
12
13
14
15
3
4
8
16
32
096
192
384
768
44
45
46
47
11
17
35
70
140
592
184
368
737
186
372
744
488
044
088
177
355
416
832
664
328
16
17
18
19
4
65
131
262
524
536
072
144
288
48
49
50
51
12
281
562
1 125
2 251
474
949
899
799
976
953
906
813
710
421
842
685
656
312
624
248
20
21
22
23
5
1
2
4
8
048
097
194
388
576
152
304
608
52
53
54
55
13
4
9
18
36
503
007
014
028
599
199
398
797
627
254
509
018
370
740
481
963
496
992
984
968
24
25
26
27
6
16
33
67
134
777
554
108
217
216
432
864
728
56
57
58
59
14
72
144
288
576
057
115
230
460
594
188
376
752
037
075
151
303
927
855
711
423
936
872
744
488
28
29
30
31
7
268
536
1 073
2 147
435
870
741
483
456
912
824
648
60
61
62
63
15
152
305
611
223
921
843
686
372
504
009
018
036
606
213
427
854
846
693
387
775
976
952
904
808
Symbol
Value
K lkilol
M lmegal
G lgigal
1,024=2 10
1,048,576 = 2 20
1,073, 741,824 = 2 30
40
1
2
4
9
GX20-1850-7
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Source Exif Data:
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