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GRAPHIC
PROCESSORS
DATABOOK
1st EDITION

MARCH 1989

TABLE OF CONTENTS

INTRODUCTION

Page

4

GENERAL INDEX

5

PRODUCT GUIDE

7

ALPHANUMERICAL and SEMI-GRAPHIC
CRT CONTROLLERS

11

GRAPHICS CONTROLLERS

105

COLOR PALETTE

213

APPLICATION NOTES

247

3

INTRODUCTION

The SGS-THOMSON Graphics data book contains comprehensive data on three
groups of graphics products: alphanumeric/semigraphics processors, full graphics
processors and colour palettes. The optimised price/performance characteristics of
the proven HMOS 2 technology, coupled with SGS-THOMSON's six years of successful participation in the graphics market, makes these products particularly suitable for low- to mid-range applications such as video games, home computers and
CAD workstations.
The alphanumeric/semigraphic range is based around the highly successful EF9345
architecture. For applications requiring flexible character display with simple graphics support, these devices provide a low-cost, single-chip solution that includes
a built-in character generator and attribute controller.
For applications requiring direct pixel addressing, with screen resolutions from
256 x 256 up to 2048 x 2048, SGS-THOMSON offers several products based on the
established EF9367 and the TS68483 advanced graphics processor. With integral
drawing processors and character generators, these products combine high performance with cost-effectiveness.
Colour palette devices are now widely used to increase the number of displayable
colours and to provide a direct interface with monitors. SGS-THOMSON is established in the low-end market with a number of devices that allow 16 of 4096 colours
to be selected.

---------------------4

L,/~~~~~~9~

GENERAL INDEX
Page

PRODUCT GUIDE ....................................................................................................

7
9

SELECTION GUIDE. ...........................................................................................................

ALPHANUMERIC and SEMI·GRAPHIC
CTR CONTROLLERS ................................................................................ .
EF9345 .........................................................................................
TS9347

GRAPHICS CONTROLLERS

11
13
63

105
107
137
171

EF9365/EF9366 .....
EF9367 ..................................................................
TS68483 ..............................................................

COLOR PALETTE ...........................................................................................................

213
EF9369..........................
...............................................................
........ 215
TS9370 ..................................................................................................................................................................... 231

APPLICATION

NOTES..................................................................... ...................... 247

EF9369 COLOR PALETTE ................................ ....................... .
EF9345 GENERAL APPLICATION PRINCIPLES

-------------------

......... 249
.......... 261

L,/~~~~~~~~~ ~----------------5

PRODUCT GUIDE

7

SELECTION GUIDE
ALPHANUMERIC and SEMI-GRAPHIC CRT CONTROLLERS
Format

Package

Page

Single Chip Color CRT Controller
On-Chip Attributes Controller
On-Chip Character Generator
R,G,B,I Video Shift Registers
Page Memory up to 16K x 8 Bits

25/21 Rows

DIP40
PLCC44

13

Single Chip Color or B/W
CRT Controller
On-Chip Attributes Controller
On-Chip Character Generator
R,G,B,I Video Shift Registers
Analog Output: 8 Grey Levels
Page Memory up to 32K x 8 Bits

25/21 Rows

DIP40
PLCC44

63

Part Number

Description

EF9345

TS9347

of 40 or 80
Characters

of 40 or 80
Characters

GRAPHICS CONTROLLERS
Format

Package

Page

EF9365
EF9366

Graphics Coprocessor
DRAMs Interface
On-Chip ASCII Character Generator
High-Speed Vector Drawing

512(256) x 512
Pixels
50 Hz

DIP40

107

EF9367

Graphics Coprocessor
DRAMs Interface
On-Chip ASCII Character Generator
High-Speed Vector Drawing

512 x 1024
Pixels
50 Hz, 60 Hz

DIP40

137

2048 x 2048
8-Bit Pixels

DIP64

171

Part Number

TS68483

Description

Alphanumeric and Graphic Drawing Capabilities
Upto 256 Colors
Four Video Shift Registers
For Video rate Less than 18 Md/s
Command Set: Vector, Are, Circle
Area Filling, Character

COLOR PALETTE
Format

Package

Page

EF9369

4-Bit DACs with Gamma Law Correction
Marking Bit
Upto 30 Mdots/s

16 Colors
Among 4096

DIP28
PLCC28

215

TS9370

4-Bit DACs
Marking Bit
Upto 45 Mdots/s

16 Colors
Among 4096

DIP28
PLCC28

231

Part Number

Description

9

ALPHANUMERIC and SEMI·GRAPHIC
CRT CONTROLLERS

11

EF9345
HMOS2 SINGLE CHIP SEMI-GRAPHIC
DISPLAY PROCESSOR
• SINGLE CHIP LOW-COST COLOR CRT CONTROLLER
• TV STANDARD COMPATIBLE (50 Hz or 60 Hz)
• 2 SCREEN FORMATS:
• 25 (or 21) ROWS OF 40 CHARACTERS
• 25 (or 21) ROWS OF 80 CHARACTERS
• ON-CHIP 128 ALPHANUMERIC AND 128 SEMI-GRAPHIC CHARACTER GENERATOR
THREE STANDARD OPTIONS AVAILABLE
FOR ALPHANUMERIC SETS
• EASY EXTENSION OF USER DEFINED ALPHANUMERIC OR SEMI-GRAPHIC SETS
(> 1 K characters)
• 40 CHARACTERS/ROW ATTRIBUTES:
foreground and background color, double height,
double width, blinking, reverse, underlining,
conceal, insert, accentuation of lower case characters
• 80 CHARACTERS/ROW ATTRIBUTES:
Underlining, blinking, reverse, color select
• PROGRAMMABLE ROLL-UP, ROLL DOWN,
AND CURSOR DISPLAY
• ON-CHIP R, G, B, I VIDEO SHIFT REGISTERS
• EASY SYNCHRONIZATION WITH EXTERNAL
VIDEO SOURCE: ON-CHIP PHASE COMPARATOR
• ADDRESS/DATA MULTIPLEXED BUS DIRECTL Y COMPATIBLE WITH STANDARD
MICROCOMPUTERS SUCH AS 6801, 6301,
8048,8051
• ADDRESSING SPACE: 16 K x 8 OF GENERAL
PURPOSE PRIVATE MEMORY
• EASY USE OF ANY LOW COST MEMORY
COMPONENTS: ROM,SRAM, DRAM
• UPWARD COMPATIBLE WITH EF9340/41
CHIPSET

December 1988

P
DIP40
(Plastic Package)

FN
PLCC44
(Plastic Chip Carrier)

(Ordering information at the end of the datasheet)

DESCRIPTION
The EF9345, new advanced color CRT controller,
in conjunction with an additional standard memory
package allows full implementation of the complete
display control unit of a color or monochrome lowcost terminal, thus significantly reducing IC cost and
PCB space.

1/50

13

EF9345
TYPICAL APPLICATION

Low cost personal terminal

2Kx81016Kx8
memory

1
/

EF9345

MODEM
EFG7515
EFB7513
EF7910

I+-

•

MCU
EF6801

..... /

D

IIll.fI###~tns}/J

l:>o;$UI

E88 EF9345-03

PIN CONNECTION
PLCC44

DIP40

ADMO

VSS

01'

ADMl

WE

ADM2

ASM

ADMJ

HVS/HS

ADM4

pc/vs

ADM5

B

ADM6

G

ADM7

R

AM8
AM9

HP
elK
SYNC IN

o

39

ADMt

AM9

G

•

R

••

HP

12

34

cuc[ 13

:tJ

AM10
AM11

AMl2

AM11

AS

AM13

DS

CS

R/IN

AD7

ADO

AD6

ADl

AD5

AU:2

AD4

Vee

ADJ

E88 EF9345-01

2/50

14

31 DAM12

os "
R/W

17

3D

~AM13

~ ~ "P'"

E88 EF9345-02

EF9345
BLOCK DIAGRAM

,,,- ADIO,71

-

-

-

-

--

-

-

-,,
,

I

ROW BUFFER
120)( 8

,

'\.-..8:........,.rr'v-~

,

~

1

os
8

ROM

ATTRIBUTE
LOGIC

'":0

-----1

...'"

MAT

~

PAT

1
1

,
1

1

I

1

1
,,
,,1

TRANSCODEA

~::'===~RF~S~H~ GE~I:'~:~OR

ADDRESS UNIT

HP

HVS/HS

PC/VS
SYNC. IN

1

1__ - _ - - - - - - - ,

H6
AM(8:131

8
ADM(o:7J

~M

DE

WE

CLK

E88 EF9345-04

3/50

15

EF9345
ABSOLUTE MAXIMUM RATINGS
Value

Unit

Vee *

Supply Voltage

- 0.3 to 7.0

V

Vin *

Input Voltage

- 0.3 to 7.0

Symbol

Parameter

TA

Operating Temperature Range

T gIg

Storage Temperature

PDm

Max Power Dissipation

V

°

'C

to + 70

55 to + 150

'C

0.75

W

• With respect to v".
Stresses above those hereby listed may cause permanent damage to the device. The ratings are stress ones only and functional operation of the device at these or any conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. Standard MOS circuits handling procedure should be used
to avoid possible damage to the device.

ELECTRICAL CHARACTERISTICS (Vee = 5.0 V ± 5 %, V ss = 0, TA = 0 to 70 °e)
Min.

Typ.

Max.

Unit

Vee

Supply Voltage

4.75

5

5.25

V

VIL

Input Low Voltage

- 0.3

0.8

V

VIH

Input High Voltage CLK
Other Inputs

Vee
Vee

V

lin

Input Leakage Current

-

10

f.lA

Symbol

2.2
2

-

-

-

VOH

Output High Voltage (lioad = - 500 IlA)

2.4

VOL

Output Low Voltage Iload = 4 mA ; AD (0:7), ADM (0:7), AM (8:13)
Other Outputs
Iload = 1 mA;

0.4
0.4

PD

Power Dissipation

-

250

-

mW

Cin

Input Capacitance

-

15

pF

ITSI

Three State (off state) Input Current

-

-

10

f.lA

4/50

16

Parameter

V
V

-

EF9345
MEMORY INTERFACE
Vee = 5.0 V ± 5 %, TA = 0° to + 70°C.
Clock: fin = 12 MHz; Duty Cycle 40 to 60 % ; t" tf < 5 ns
Reference Levels: V 1L = 0.8 V and V1H = 2 V, VOL = 0.4 V and VOH
Symbol

Ident.
Number

= 2.4 V.

Parameter

Min.

Typ.

Max.

Unit

-

500

-

ns

60

ns

120

-

-

ns

tELEL

1

Memory Cycle Time

to

2

Output Delay Time from ClK Rising Edge (ASM, OE, WE)

tEHEL

3

ASM High Pulse Width

tELOV

4

Memory Access Time from ASM low

-

-

290

ns

tOA

5

Output Delay Time from ClK Rising Edge
(ADM (0:7), AM (8:13))

-

-

80

ns

tAvEL

6

Address Setup Time to ASM

30

-

-

ns

tELAX

7

Address Hold Time from ASM

55

-

-

ns

tCLAZ

8

Address Off Time

-

-

80

ns

tGHOX

9

Memory Hold Time

10

-

ns

toz

10

Data Off Time from OE

-

-

60

ns

tGLOV

11

Memory OE Access Time

-

-

150

ns

tOVWL

12

Data Setup Time (write cycle)

30

-

ns

tWHOX

13

Data Hold Time (write cycle)

30

tWLWH

14

WE Pulse Width

110

-

-

ns
ns

TEST LOAD

VDO
Symbol AD (0:7), AM (8:13) Other
ADM (0:7)
Outputs

Test
pOint

MMD7000
or equiv_

C

100 pF

50 pF

RL

1 KQ

3.3 KQ

R

4.7 KQ

4.7 KQ

E88 EF9345·05

5/50

17

EF9345
MEMORY INTERFACE TIMING DIAGRAM

eLK

ADMIO:71
AMIB.13J

DE - - - - - - - _ .

WE

EBB EF9345-06

MICROPROCESSOR INTERFACE
EF9345 is motel compatible. It automatically selects
the processor type by using AS input to latch to state
of the OS input.

EF9345

No external logic is needed to adapt bus control signals from most of the common multiplexed bus
microprocessors.

AS
OS
RiW

6/50

18

6801

INTEL Family

Timing 1

Timing 2

AS
OS, E,  2
R/W

ALE
RO
WR

EF9345
MICROPROCESSOR INTERFACE TIMING AD (0:7), AS, DS, RiW, CS
Vee = 5.0 ± 5 %, TA = 0" to + 70 DC, C L = 100 pF on AD (0:7)
Reference Levels: V IL = 0.8 V and VIH = 2 V on All Inputs ; VOL
Symbol

Ident.
Number

= 0.4 V and VOH on All Outputs.

Parameter

Min.

Typ.

Max.

Unit

400

tCYC

1

Cycle Time

ns

2

DS Low to ASJ::Iigh (timing 1)
DS High or RIW High to AS High (tming 2)

30

-

-

tASO

-

ns

tASEO

3

AS Low to DS High (timiQg 1)
AS Low to DS Low or RIW Low (timing 2)

30

-

-

ns

tPWEH

4

Write Pulse Width

200

-

tPWASH

AS Pulse Width

100

tRWS

6

100

-

ns

tRWH

7

RIW to DS Setup Time (timing 1)
RIW to DS Hold Time (timing 1)

-

ns

tASL

8

Address and CS Setup Time

20

9

Address and CS Hold Time

20

tosw

10

Data Setup Time (write cycle)

100

tOHW

11

Data Hold Time (write cycle)

10

-

-

ns

tAHL

-

-

ns

5

-

150

ns

10

tOOR

12

Data Access Time from DS (read cycle)

-

tOHR

13

DS Inactive to High Impedance State Time (read cycle)

10

tACC

14

Address to Data Valid Access Time

-

ns

ns
ns
ns

80

ns

300

ns

MICROPROCESSOR INTERFACE TIMING DIAGRAM 1 (6801 type)

os

AS

RIW

WRITE CYCLE

AOIO,71-------,

READ CYCLE

®

AOIO,71--------<

R.G.B.I.
4Ochar/row

Typ.

10
50
30
30

\

\

-.-I

Min.

~
tHO

tsu

'0

'0

~

HP

to

X

R.G.B.I.
BO char/row

I

A

><

'0

'D

X

HVS/HS

PCNS

INPUTCLK

eLK

)

_

__'

Reference level Vil

: -.

=0.8 V, VIH =2.0 V

~~

••=PVVCL-=:(
EBB EF9345·1 0

9/50
21

~

<
m

o
0;
o

"II
CO

0

en

-I

l>

r

....

84 ••

HORIZONTAL IV_RO

-~

l>

~
U __ ~~f~m~~~~ ____I_~~~f~m~1~~I~-.J
~

h

HVS

Z

C
:J:

0

::D

32 ..

H blanking

R.G.B.I
40 ctwr ./row

8O ....'.I'ow

10,..
9.96 ..

IMarginl

J

6,.11

16 .. I

§
_____

~~k______

40,..
40,..

IMo,gi"!

-'- 8"'1
I

6,..

I

Z
-I

H blanking

l>

2,.1
2.04 ..

r

en

-<
z

VERTICAL IV_RO

~

0
:J:
::D

NoN INTERLACED

!!lin

0

z

HVS ITGS4 - 11

I~

N

TGSg -0

l>

-I

TGSg - 1

II

(5

2 lin.

Z

0

VS (TClS4 - 01

~.

c::

INTERLACED

---------------------------------~

Event,..,.

----------------------------------~

HVS ITGS4 - 11
OcIdk_"

-I

"tI

c::

-I

en
0r
A

312.5 linea (TGSg .01

I•

E..n lrome

m

g:

m

~

2.5 lin..

I

•I

VS CTGS4 - 0)

Odd I,....

~L_ _ _ _-'

262.5 lin.. (TGSg =11

I

.----~I
I

I\)

I

m

::D

s::

I

!:!-

Co)

.1=0

EF9345
EF 9345 PIN DESCRIPTION
All the input/output pins are TTL compatible.
MICROPROCESSOR INTERFACE
Name

Pin
Type

N°

Function

AD (0:7)

I/O

17-19
21 - 25

Multiplexed
Address/Data
Bus

AS

I

14

Address
Strobe

The falling edge of this control signal latches the address on the
AD (0:7l.J!!1es, the state of the Data Strobe (OS) and Chip
Select (CS) into the chip.

OS

I

15

Data Strobe

When this input is strobed high by AS, the o!!!put buffers are
selected while OS is low for a read cycle (R/W = 1).
In write cycle, data present on AD (0:7) lines are strobed by Rm
low (see timing diagram 2).
_
When this input is strobed low by AS, RIW gives the direction of
data transfer on AD (0:7) bus, QS high strobes the data to be
written during a write cycle (R/y!!' = 0) or enables the output
buffers during a read cycle (RIW = 1). (see timing diagram 1).

RIW

I

16

Read/Write

This ipnut determines whether the internal registers get written
or read. A write is active low ("0").

CS

I

26

Chip Select

The EF9345 is selected when this input is strobed low by AS.

Description
These 8 bidirectional pins provide'communication with the
microprocessor system bus.

MEMORY INTERFACE
Name

Pin
Type

N°

Function

Description

ADM(0:7)

I/O

40- 43

Multiplexed
Address/Data
Bus

lower 8 bits of memory address appear on ~us when ASM
is high, It then becomes the data bus when ASM is low.

AM (8:13)

0

32- 27

Memory
Address Bus

These 6 pins provide the high order bits of the memory address.

OE

0
0

2

Output Enable

WE

3

Write Enable

ASM

0

4

Memory
Address
Strobe

Name

Pin
Type

N°

Function

ClK

I

12

Clock Input

Vss

S

1

Power Supply

Ground.

Vce

S

20

Power Supply

+5V

When low, this output selects the memory data output buffers.
This output determines whether the memory gets read or
written, A write is active low ("0").
This signal cycles continuously. Address can be latched on its
falling edge.

OTHER PINS
Description
External TTL clock Input. (nominal value: 12 MHz,
duty cycle : 50 %),

11/50

23

EF9345
VIDEO INTERFACE
Name

Pin
Type

N°

Function

Description

R
G
B

7
8

These outputs deliver the video signal. They are low during the
vertical and horizontal blanking intervals.

9

Red
Green
Blue

I

0
0
0
0

10

Insert

This active high output allows to insert R: G : B : in an external
video signal for captioning purposes, for example. It can also be
used as a general purpose attribute or color.

HVS/HS

0

5

Sync. Out

PCNS

0

6

Phase
Comparator /
Vertical Sync

When TGS4 = 1, this signal is the phase comparator output.
When TGS 4 = 0, this output delivers the vertical synchro signal.

SYNC IN

I

13

Synchro In

This input allows vertical and/or horizontal synchronizing the
EF9345 on an external signal. It must be grounded if not used.

HP

0

11

Video Clock

This output delivers a 4 MHz clock phased with the R, G, B, I
signals

This output delivers either the composite synchro (bit TGS4
or the horizontal synchro signal (bit TGS4 = 0).

= 1)

GENERAL DESCRIPTION
The EF9345 is a low cost, semigraphic, CRT controller.
It is optimized for use with a low cost, monochrome
or color TV type CRT (64 J.IS per line, 50 or 60 Hz
refresh frequency).
The EF9345 displays up to 25 rows of 40 characters or 25 rows of 80 characters.
The on-chip character generator provides a 128
standard, 5 x 7, character set and standard semigraphic sets.
More user definable (8 x 10) alphanumeric or semigraphic sets may be mapped in the 16 K x 8 private
memory addressing space.
These user definable sets are available only in 40
characters per row format.
MICROPROCESSOR INTERFACE.
The EF9345 provides an 8-bit, address/data multiplexed, microprocessor interface.
It is directly compatible with popular (6801, 8048,
8051, 8035 ... ) microprocessors.
REGISTERS.
The microprocessor directly accesses 8 registers:
• RO: Command/status register
• R1, R2, R3 : Data registers
• R4, R5 } : Each of these register pairs points
R6, R7
into the private memory.
Through these registers, the microprocessors indirectly accesses the private memory and 5 more registers:
12/50

24

• ROR, DOR : Base address of displayed page
memory and of used external character generators.
• PAT, MAT, TGS : Used to select the page attributes and format, and to program the timing generator option.
PRIVATE MEMORY
The user may partition the 16 K x 8 private memory addressing space between:
• pages of character codes (2 K x 8 or 3 K x 8),
• external character generators,
• general purpose user area.
Many types of memory components are suitable:
• ROM, DRAM or SRAM,
• 2 K x 8,8 K x 8,16 K x 4 organizations,
• Modest 500 ns cycle time and 250 ns access time
is required.
40 CHARACTERS PER ROW: CHARACTER
CODE FORMATS AND ATTRIBUTES.
Once the 40 characters per row format has been selected, one character code format out of three must
be chosen:
• 24-bit fixed format:
All the attributes are provided in parallel.
• 8/24-bit compressed format:
All the attributes are latched.
• 16-bit fixed format:
Some parallel attributes, other are latched.
The 16-bit fixed fomnat
EF9340/41 CRT controller.

is

compatible

with

EF9345
Character attributes provided:
_ Background and foreground color (3 bits
each),
Double height, double width,
Blinking,
Reverse,
Underlining,
Conceal,
Insert,
Accentuation of lowercase characters
3 x 100 user definable character generator in
memory
8 x 100 semi-graphic quadrichrome characters.
80 CHARACTERS PER ROW FORMAT: CHARACTER CODE FORMAT AND ATTRIBUTES.
Two character code formats are provided:
o Long (12 bits) with 4 parallel attributes:
_ Blinking,
_ Underlining,
_ Reverse,
_ Color select.
o Short (8 bits) : no attributes.
TIMING GENERATOR.
The whole timing is derived from a 12 MHz main
clock input.
The RGB outputs are shifted at 8 MHz for the 40
character/row format and at 12 MHz for the 80 character/row.
Besides, the user may select:
o 50 Hz or 60 Hz vertical sync. frequency,
o Interlaced or not,
o Separated or composite vertical and horizontal
sync. outputs.
Furthermore, a composite sync. input allows, when
it is required:
o An on-chip vertical resynchronization,
o
An on-chip crude horizontal resynchronization,
o An off-chip high performance horizontal resynchronization by use of a simple external VCXO
controlled by the on-chip phase comparator.

MEMORY ORGANIZATION
LOGICAL AND PHYSICAL ADDRESSING.
The physical 16-Kbyte addressing space is logically partitioned by EF9345 into 40-byte buffers (figure
1). More precisely, a logical address is given by an
X, Y, Z triplet where:
o X = (0 to 39) points to a byte inside a buffer,
o Y = (0, 1 ; 8 to 31) points to a buffer inside a 1
Kbyte block,
o Z = (0 to 15) points to a block.
Obviously, 1 K = 2 10 = 1024 cannot be exactly divided by 40. Consequently, any block holds 25 full
buffers and a 24-byte remainder. Provided that the
physical memory is a multiple of 2 Kbytes, the remainders are paired in such a way as to make available:
o a full buffer (Y = 1) in each even block,
o a partial buffer (Y = 1 ; X = 32 to 39) in each odd
block.
POINTERS.
Each X, Y and Z component of a logical address is
binary encoded and packed in two 8-bit registers.
Such a register pair is a pointer (figure 2). EF9345
contains two pointers:
o
R4, R5 : auxiliary pointer,
o
R6, R7 : main pointer.
R5 and R7 have the same format. Each one holds
an X component and the two LSB's of a Z component. This packing induces a partitioning of Z in 4 districts of 4 blocks each.
R5, R7 points to a block number in a district. R4 and
R6 have a slightly different format: Each one holds
a Y component and the LSB of the district number.
But R6 holds both district MSB.
Figure 4 gives the logical to physical address transcoding scheme performed on chip.

13/50

25

EF9345
Figure 1 : Memory Row Buffer.

x
D

I

Figure 2: Pointer Auto Incrementation.

X

)'

DISTRICT

D

l!

I

1

Y '" (0,1 ;8 to 31)
J2

l!

1

Id'ld"ldOl- 13 I 2 I' 1° I

R6
MAIN

X=Oto39

I bO I

b'

I

5

I- I

3

I

2

I' 1° I

POINTER

R7

} BLDCKO{
{1 KbyreJ

y' =(0,1 ;8t0311

1-1-l d'01-1

} BLDCK1 {

3

I

2

I' 1°

R_
AUXILIARY

X' =Oto39

I

b'O, b'l

I

5

I

4

}

} BLOCK2{

} BLOCK 3{

I

3

I

2

I' 1 0

POINTER

R5

Z

= (0 to 15)

"

D

r=r
r~ISTRICT--t

120-8VTE ROW BUFFER

8O·BYTE ROW BUFFER

E88 EF9345-12

• Row buffers lay inside a district.
• At two or three successive block addresses
(modulo 4).
• First block address is even.
DATA STRUCTURES IN MEMORY.
A page is a data structu re displayable on the screen
up to 25 rows of characters. According to the character code format, each row on the screen is associated with 2 (or 3) 40-byte buffers. This set of 2 (or
3) buffers constitutes a row buffer (figure 1). The
buffers belonging to a row buffer must meet the following requirements:
• they have the same Yaddress,
• they have the same district number,
• they lie at 2 (or 3) successive (modulo 4) block
addresses in their common district.
Consequently, a row buffer is defined by its first buffer address and its format.
A page is a set of successive row buffers:
• with the same format,
• with the same district number,
14/50

26

X incrementation

Y incrementation

Modulo 40

Modulo 24

Z incrementationl
decrementation
Modulo 4 on the
block number onlv

E88 EF9345-13

• with the same block address of first buffer. This
block address must be even.
• lying at successive (modulo 24) Yaddresses.
Consequently, a page should not cross a district
boundary. General purpose memory area may be
used but should respect the buffer or row buffer
structure. See figure 2 for pointer incrementation implied by these data structures.
MEMORY TIME SHARING (see figure 3).
The memory interface provides a 500 ns cycle time.
That is to say a 2 Mbyte/s memory bandwidth. This
bandwidth is shared between :
• reading a row buffer from memory to load the internal row buffer (up to 120 bytes once each row),
• reading user defined characters slices from memory (1 byte each I1s),

EF9345
• indirect microprocessor read or write operation,
• refresh cycles to allow DRAM use, with no overhead.

3. The microprocessor may indirectly access the
memory once every f1S, except during the first
and the last line of a row, when the internal buffer must be reloaded.

A fixed allocation scheme implements the sharing.

During these lines, no microprocessor access is provided for 104 fIS ; this hold too when no user defined character slices are addressed.

Notes on Figure 3.
1. Dummy cycles are read cycles at dummy addresses.
2. RFSH cycles are read cycles performed by an 8bit auto-incrementing counter. Low order address byte ADM (0:7) cycles through its 256
states in less than 1 ms.
Figure 3 : Memory Cycle Allocation .

-r----3121262

40 ... - - -

....f - - - - - -

----t-----

24 ... ___

I

-,---

"r~~L_L____D_A~_C~_ :_~

lONE ROW

= 10 TV LINES

_ _ _ _.L-_ _ _ _ _..J

MEMORY CYCLE

I
I

INACTIVE LINE

DUM

LAST ROW LINE

UDS

I
I
I

LD

LO

FI RST ROW LINE

UDS I

LD

RFSH

OTHER ROW LINE

UOS

RFSH:

"p

I
I
I "p

DUM: dummy cycle

I
I LO
I
I "p
I

pP : indit'1!lCt aiXeU to memory
R FSH : refresh cycle

U OS

sl ice read cycle

lD : read cycle to load the intema!
row buffer.

----1"._
RFSH:

1 p.s'-----------"

4--

"p

pP

40J.l,s

E88 EF9345-14

Figure 4: Logical to Physical Address Transcoding Performed On-chip.

-----I
I I
D

x (0 to 391

V(0.1 ;Bto311

Z (0 to 151

B

-----~

LOGICAL ADDRESS

3

2

I

1

I

0

4

3

I

2

I

1

I

0

I

TRANSCODING

PHYSICAL ADDRESS

------------------------E88 EF9345-15

15/50

27

EF9345

PHYSICAL ADDRESS AM (3:10)

X and Y
Condition

Y;o,8

Y<8

X5 =0
X5 = 1
YO = 0

,-

1

YO = 1 I bO = 0
bO -1

10

9

8

7

6

5

4

3

bO
bO
bO
X3

Y4
0
0
0
0

Y3
0
0
0
0

Y2
Y2
X5

Y1
Y1
X4
X5
X5

YO
YO
X3
X4
X4

X4
Y4
0
0
0

X3
Y3
0
0
0

I

I
I

SCREEN FORMAT AND ATTRIBUTES

The screen format and attributes are programmed
through 5 indirectly accessible registers : ROR,
TGS, PAT, MAT and DOR. IND command allows
accessing these registers. TGS is also used to select the timing generator options (see Screen Format Table).
ROW AND CHARACTER CODE FORMAT
PAT? ; TGS(6:7).
Two row formats and 5 character code formats are
available but cannot be mixed in a given screen.
DOR register interpretation is completely row format
dependent and is discussed in the corresponding
40 char/row and 80 char/row section.
SCREEN PARTITION - PAGE POINTER ROR
(see top of the Screen Format Table).
The screen is partition ned into 3 areas:
• the margin,
• the service row,
• the bulk of remaining rows.
MAT(a:3) declares the color of the margin and the value 1M of its insert attribute.
ROR register points to the page to be displayed and
gives the 3 MSB's of the Z address: Za = 0 implicitly ;thepage block address must be even. YOR gives
the first row buffers to be displayed at the top of the
bulk area. The next row buffers to be displayed are
fetched sequentially by incrementing the Y address
(modulo 24). This address never gets out of the origin block. Incrementation of YOR by the microprocessor yields a roll up.
SERVICE ROW: TGSs - PATa.
The service row is displayed for 10 TV lines on top
of the screen and does not roll. Following TGSs, it
is fetched from the origin block at either Y = 0 or Y
= 1. The Y = 1 is a partial row buffer. It can be used
only with variable 40 char.lrow and an 8 byte attribute file. The service row may be disabled by PATa
= 0 ; it is then displayed as a margin extension.

16/50

28

BULK: TGSa ; PAT(1:2) ; MAT?
It is displayed after the service row for 200 or 240
TV lines according to TGSa. Each row buffer is
usually displayed for 10 TV lines. However, MAT? =
1 doubles this figure. Then every character appears
in double height (double height characters are quadrupled).
PAT1 = 0 and/or PAT2 = 0 disables respectively the
upper 120 lines and/or the lower 80/120 lines of the
bulk.
When disabled, the corresponding TV lines are displayed as a margin extension.
CURSOR MAT(4:6)
To be displayed with the cursor attributes, a character must be pointed by the main pointer (R6, R7) and
MAT6 must be set. The cursor attributes are given
by MAT(4:s) :
• Complementation: the R, G and B of each pixel
is logically !:!.e@t~d.
R, G, B ~ R, G, B
• Underline: the underline attribute of this character is negated.
• Flash: the character is periodically displayed
with, then without, its cursor attributes (50 % / 50
%; = 1 Hz).
FLASH ENABLE (PAT6) - CONCEAL ENABLE
(PAT3).
Any character flashing attribute is a "don't care"
when PAT6 = o. When PAT6 = 1, a character flashes
if its flashing attribute is set. It is then periodically
displayed as a space (50 % / 50 % ; = 0.5 Hz).
PAT3 is a "don't care" for 80 char.lrow formats.
When any 40 char.lrow format is in use:
• if PAT3 = 0, the conceal attribute of any character is a don't care.
• if PAT3 = 1, the conceal attribute of each character is interpreted: a concealed character appears
as a space on the screen.

EF9345
INSERT MODES: PAT(4:5).
During retrace, margin and extended margin periods, the I output pin delivers the value of the insert
margin attribute.
I = 1M = MAT4.
During active line period, the I output state is controlled by the Insert Mode and i, the insert attribute
of each character. The I output pin may have several uses: (see figure below) :
• As a margin/active area signal in the active area
mark mode.

• As a character per character marker signal in the
character mark mode.
• As a video mixing signal in the two remaining
modes, provided that the EF9345 has been vertically and horizontally synchronized with an external video source: the I pin allows mixing RGB
outputs (I = 1) and the external video signal (I =
0). This mixing can be achieve by switching or
ORing. It may occur for the complete character
window (Boxing Mode) or only for the foreground
pixels (Inlay Mode).

VIDEO OUTPUTS DURING ACTIVE PERIODS
Char. Level

Insert Mode

I

Pixels (1)

Active Area Mark

-

Character Mark

0
1

Boxing

0
1

Inlay

Outputs
I

R, G, B (2)

-

1

-

0
1

X
X
X

0
1

BLACK
X

-

0

-

0

BLACK

1

BACKGND
FOREGND

0
1

BLACK

X

TIMING GENERATOR OPTIONS :TGS (0:4)
TGS(o:1) select the number of lines per frame:

NOTES:
(1) PIXEL TYPE
- : Don't care
FOREGND = A foreground pixel is :
• Any pixel of a quad rich rome character,
• A Pixel of a bichrome character generated from a
"1" in the character generator cell.
(2) RGB OUTPUTS
X : Not affected.
BLACK : forced to low level.

TGS4 controls the SYNC OUT pins configuration:
TGS4

HVS I HS

TGS1

TGSa

LINES

1

Composite Sync

PC

0

0

312

0

H Sync Out

V Sync Out

0

1

262

1

0

312.5

1

1

262.5

PC / VS

NON INTERLACED

INTERLACED

r----------------------------

The composite incoming SYNC IN signal is separated into 2 internal signals:
• Vertical Synchronization In (VSI),
• Horizontal Synchronization In (HSI).
TGS3 enables VSI to reset the internal line count.
SYNC IN input is sampled at the beginning of the
active area of each line. When the sample transits
from 1 to 0, the line count is reset at the end of the
current line.

HVS/HS

TGS2 enables HSI to control an internal digital
phase lock loop. HSI and on-chip generated HS Out
are considered as in phase if their leading edges
match at ±1 clock period.

PC is the output of the on-chip phase comparator.

When they are out of phase, the line period is lengthened by 1 clock period ( = 80 ns).

An external VCXO allows a smoother horizontal
phase lock than the internal scheme.

EBB EF9345·16

17/50

29

EF9345
SCREEN FORMAT TABLE

-

MEMORY

~

0

TGSs 01

39

-

BLOCK ORIGIN
""-1._1

-

'.

8

-

_..

~

YOR ---.
YOR .1--'

I-

31

7

-

6

5

•

L

SERVICE ROW

4

Y ORIGIN

.
i

.

Y ORIGIN + 1
•

-

o

3

-------------•

~

ROR(, =]1

I

Dng.n

Block Orl!)1n levenl

~~

r--

\

\

\

,,

" ............ -----"

CHAR CODE

PAT1

TGS1

TGSt;

40 CHAR LONG

0

0

0

40 CHAR VAR

0

,

0

,

40 CHAR SHORT

0

0

110 CHAR LONG

0

110 CHAR SHORT

0

,

0

INSERT MODE

,

PAT5

PAT4

0

0

BOXING

0

ACTIVE AREA MARK

,

,

l

4

,

Service row select
IY,1I01

r-'-

o

I

TGS (, = 1)

1111

Interlaced

Horizontal rosyne; enable
Vertical resync enable

Sync Oul pins configuration
1 : Composite sync +
phase comparator

I

O:Vsvnc+Hsvnc

,

INLAY

CHARACTER MARK

J-

,ow_,..

YOR ,18 10311

._____ I

•

BULK

i

i

- --. - - - - _ _ _ -------..

+,

MARGIN

I
I
1

6

3

2

1

0

0

,

MAT(, = 21
Margin color
Margin insert

CURSOR DISPLAY MODE
FIXED COMPLEMENTEO

Cursor display enable

MAT5

MAT4

0

,

0

FLASH COMPLEMENTED
FIXED UNDERLINED

0

,

FLASH UNDERLINED

,

Double height

,

0

NOTE

PROGRAMMING BIT VALUE

1 .- True
0- False
EBB EF9345-17

18/50

~

".,1 SGS·THOMSON

iIIIUlCmJl!J!.lWii'mJlIIlIC$

30

EF9345
40 CHAR/ROW CHARACTER CODES
To display pages in 40 character per row format,
one out of three character code formats must be selected:
• Fixed long (24 bits) code: all parallel attributes.
• Fixed short (16 bits) code: mix of parallel and latched attributes.
• Variable (8/24 bits) code: all latched attributes.
Fixed short and variable codes are translated into
fixed long codes by EF9345 during the internal row
buffer loading process. The choice of the character
code format is obviously a display flexibility/memory size trade off, left up to the user.
FIXED LONG CODES.

4. Bichrome and quadrichrome characters use two
different coloring schemes.
For bichrome characters, character code byte A defines a two color set by giving directly two color values (figure 6). The negative attribute exchanges the
two values. Each bit of the slice byte selects one color value out of two.
The "A" byte in a quadrichrome character code defines an ordered 4 color set (figure 7). When more
than 4 bits are set, higher ranking bits are ignored.
When less than 4 bits are set, the color set is completed with implicit "white" value. The slice byte is
shifted 2 bits at once at half the dot frequency (~4
MHz).

This is the basic 40 char.lrow code. Each 8 pixels x
10 lines character window, on the screen is associated with a 3-byte code in memory, namely the C,
B and A bytes (figure 5). A row on the screen is associated with a 120 byte row buffer in memory.

Each bit pair designates one color out of the 4 color
sets.

3-BYTE CODE STRUCTURE.

By programming the R attribute in byte B, one may
chose to keep the full vertical resolution (1 slice per
line) or to halve it (each slice is repeated twice). In
any case, it is possible to change the color set freely from window to window and to mix freely all the
character types. So, fairly complex pictures may be
displayed at low memory cost.

1. C7 is a don't care. Up to 128 characters may be
addressed in each set. Each user definable set
holds only 100 characters: C byte value ranges
from 00 to 03 and 20 to 7F (hexa).
2. B(4:7) give the type and set number of the character.
3. All the bichrome characters have the same attributes except that alphanumerics may be underlined, semi-graphics cannot. Accentuated alphanumerics allow orthogonal accentuating of any
one of the 32 lower case ROM characters with
any of 8 accents (see figure 19).

Quadrichrome characters allow displaying up to 4
different colors (instead of 2) in any 8 x 10 window
at the penalty of an halved horizontal resolution.

HANDLING LONG CODES.
The KRF command allows an easy X, V random access or an X sequential access to/from the microprocessor from/to a memory row buffer (figure 8).

Figure 5: 40 Char / Row Fixed Long Codes.
QUADRICHRQME CODE

BICHROME CODE

6

5

4

3

1-I

I

o

765432

I

Lim

IHI, I

0

I-I

C BYTE

B BYTE

~l 1~:
L~=~~

1 ~'LI~
~

1

Double width

'---_ _ _ _ _ _ _
~ Type and set

- i
1 1

Set number

A BYTE

1 N I BI I GI I RI I F

4 COLOR PALETTE
I

t----.

Bilckground color

Low Resolution

Subset index
(low resolution only)

I

!

I

Co

:.. Flash (Blink)

~O,egIUUlld c.;oIur C,
'---_ _ _ _ _ _ _ _ _
- Negative (Rewene video)

'-________

liii
SGS·ntOMSON
~I ~D©Iiil@rnn.rn©'Illiil@IlI8©i!i

E88 EF9345-18

19/50

31

EF9345
Figure 5 : (continued).
Type and Set
Code: B(4:7)
7

0

Set
Name

6

5

4

C(0:6)

0

1
1

0
1

128 Standard Mosa'ics
32 Strokes

G 10
G 11

0

0

U
N
0
E
R
L

128 Alphanumerics

Go.

0
1

1

1

Number of Character
Per Set

0

0

0

1
1

0
1

X

B
I
C
H
R
0
M
E

ALPHA

1Q


m

."
<0
W

...

'",(,
'"

1. Translation Process.
The 1ranslatlon process operates ltirough 3 elementary operations:
• Field-to-field: a character code or an attnbute value (Le : Co, ~ashing) is directiy loaded from short to long code.
• Field-to-constant' ltie decoding of a short code forces the value of the equivalent long code attribute, For example, semigraphic short craracters forces
normal size (H • n, L. 0) attributes.
• Latcher,; attributes: at the beginning of each row, these attributes are reset (no underline, not concealed, Ijack background). Then, they keep their current valJe unti modified by either a field to field or field to constant operation,
2, EF9340 41 Compatibility,
~ is binary ~ode compatible with few exception~ :
• Flashing attribute Is negated,
• A7 is negated in delimitors,
It is also display compatible with 2 exceptions concerning the underling:
• An alphanumeric belonging to G'o may be underlined,
• Any alphanumeric following a semigraphlc cannot be underlined.

0
0
a.
CD

--I

Pl
::J
Ul

f[

0"

?

"T1

W
01:0

UI

EF9345
USED DEFINED CHARACTER GENERATOR IN MEMORY: DOR REGISTER
With 40 char lrow, the elementary window dimensions on the screen are 10 slices x 8 pixels. Thus,
a character cell holds 10 bytes in memory and 4 character cells are packed in one 40-byte buffer (fi-

gure 13). However, 5 bytes of a low resolution quadrichrome cell are enough to fill up to window. In this
case, 8 character cells can be packed in one 40-byte
buffer.

Figure 13: Packing UDS Cells in Memory.

1

1
Character ..and
t ""'" address
character set numbrr

t

Z block eddreu ~~------=""I
0
39

1-4-C-H-AR-A-C""T-E-R-C-E-L-LS~

, KOBN;TE

g9_
:

IC61 c51 C41 C31 c21 Ico I
Cl

~

j

_

y

BLOCK
~

_ _ _ _ _--131
Slice number (0 to 9)

o

I
MEMORY
PIXELS

o

Or'r2r!r5 lr--

SLICE
NUMBER
(0 t091
NT

1

2

345

I

I

N,T

I

I

~

x

---

I

A CHARACTER SET LAYS IN ONE BLOCK
(Up to 100 characters per sed

6 7

4

6

o

3

I°

'-j'-j---iH-+--l ONE SLICE
----I
..~.
--l--l--lH-+--l ONE BYTE

II-

SLICES ARE SHIFTED lSB FI RST

91Window on screen

\

Character code C byte (0 to 3 ; 32 to 127)

Window on screen

0

°
SLICE
NUMBER
101041
NT

I
t-----------j

3

3
4

IC61 C51 C41 C31 C21±1,~
TWOSLICES
ONE BYTE (repeated)

5

~H21'
+_-.

01

NT

-~

NT"

4

A SPECIAL CASE. LOW RESOLUTION OUADRICHROME CELL (R "1)
(Up to 200 characters per set)

NT·

=0

5 k + NT

k '" subset index

E88 EF9345-26

25/50

37

EF9345
The cells of one given character set should be layed
in one block.

each type of set, it gives the MSB(s) of the Z block
address. EF9345 reads the Z LSB(s) in the B byte
of the (equivalent) long code. As usual, the character code is read in the C byte. NT is derived from the
TV line rank in the row and the double height status.

Up to 100 character cells may be addressed in each
set (or 200 for low resolution quadrichrome only).
The location in memory, where to fetch the sets in
use, are declared by DaR register (figure 14). For

Figure 14: UDS Fetch to Display.

MEMORY

r----:-i' ..L

..L

t

DOR G'O (alpha UDS)

I Kbyt.

• l---=-l
!
I
1------1 G'IO

2 Kbytes

1
t

6

G'l1

4

3

0

IZ3! Z3! Z2! Zl !Z3! Z2! Zl !Zo I

DOR G'l (Semii/faphic

DOR register

UDS)
DOR G'l

DOR Q

Eve" block

~------t

5

!

DOR G'O

Odd block

6

t--------i
~---___j

5

o

4

CHARACTER
LONG CODE B
BYTE

. - - OOR 0 (Quadrichrome)

8 Kbytes

10
l'

'I

UDS Set

Z Address

85
0

1

86
0
0

1

DOR 6 DOR 5 DOR 4

1

1

X

DOR 7

#

87

G'o

1

G'11

0 0 -0 7

Z3

Z2

Z1

Zo

DOR 3 DOR 2 DOR 1 DORo

85

83

84
84

EBB EF9345·27

LOADING USER DEFINED CHARACTER SET.
Before loading a character set into RAM, the user
must:
Assign a name to the set:
_ G'o, G'10 or G'11 for bichrome characters.
_ From 00 to 07 for quadrichrome characters.
Assign a character number to each character belonging to this set, character numbers range from
o to 3 and 32 to 127.
_ It is binary coded into 7 bits C(0:6) - C(0:6)
will be loaded later on into a C byte character

26/50

38

code in order to display the character.
• A pointer to a character slice in memory is then
manufactured from:
_ the character number C(0:6)
_ the slice number NT(0:3)
_ the block number assigned to the set Z(0:3).
Figure 15 shows how to proceed with the auxiliary
pointer and the OCT command.
Note: The main pointer may be also used. When
sequentially accessing slices of a given character, auto incrementation is helpless.

EF9345
Figure 15: Accessing a Character Slice in Memory Using OCT Command with Auxiliary Pointer.

R1

Shce

R2

-

R3

-

R4
AS

R6

-

R7

I

I
I

-

-

I

I

Zo I Zl

I -I

I

I

z2

I

Z31
-

! C6

I C5 I C4 I C3 I C21

I

NT
I

C1 I CO

I

I

-

-

-

-

-

-

-

-

-

-

-

-

ON-CHIP CHARACTER GENERATOR.
• Go set is common to 40 and 80 char./row modes
(figure 16 and figure 25).
• GlO is the standard mosaIc set for videotex (figure 17).
• G11, G20 and G21 cannot be reached from the 16bit short fixed codes (figure 18 and figure 19).
DISPLAYING THE ATIRIBUTES.

1. For normal operation, a double height and/or
double width character must be repeated in memory in two successive Y and/or X positions. The
user may otherwise freely mix any character
size.

I

I
I

Y

x

~

I I

•
E88 EF9345·28

• Underline or underline cursor: foreground forced
on the last slice (NT = 9).
• Flash : background periodically forced on the
whole window ( 0.5 Hz). The phase depends on
the negative attribute.
• Conceal: background forced permanently on the
whole window. A concealed character neither
blinks nor is underlined.
• Negative: exchange the background and foreground color values when set.
• Coloring.
• Complemented cursor mode.
• Insert: black color forced when required.

3. Basic pixel shift frequency:

!eLK

x 2/3

= 8 MHz.

2. The attributes are logically processed in the following order:

27/50

39

EF9345
Figure 16: Go Alphanumeric Character Set in 40 Character/Row Mode - EF9345.

C3

(:2

CI

CO

0

0

0

0

C&

0

0

0

0

I

I

I

I

CS

0

0

I

I

0

0

I

I

C4

0

I

0

I

0

I

0

I

•• ~~
~IJ ••
~t
lliili -II
~
:,

0

0

0

I

0

I

0

0

0

I

I

0

I

0

0

0

I

0

I

0

I

I

0

0

I

I

I

I

0

0

0

I

0

0

I

I

0

I

0

I

0

I

I

I

I

0

0

I

I

0

I

I

I

I

0

I

I

I

I

Co

RilHHl

.

....
klli •
- •
;, •
htt 1I1I
.
•• m
......

..,

"

••••••••
••••••••
11 ••• 111
••••••••
•••• 111 ••
••••••••
••••••••
••••••••
•• 1 •••••
••••••••
••••••••
••••••••
••••••••
••••••••
•

0

•

<-,

t

~··I

EBB EF9345·29

40

EF9345
Figure 16 bis : Go Alphanumeric Character Set in 40 Character/Row Mode.- EF9345 R003.

C3

C2

Cl

CO

D

D

D

D

D

D

D

1

D

D

1

D

D

D

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

D

0

0

1

D

D

1

1

D

1

D

1

D

1

1

1

1

D

D

1

1

o

1

1

1

1

0

1

1

1

1

C8

D

D

D

D

1

1

1

C6

D

D

1

1

D

D

1

1

Cot

D

1

D

1

0

1

0

1

1

1 ••11.1.
1111111.

••••••••

11.111 ••
11111111.
1111111.
••• 111 ••
•• 1111.1

••••••••
•• 1 •• 111

••• 11•••

IIIIIIII

.1111 ••••

••••••••

11111 ••••
111111 •••

EBB EF9345-30

-

- - - L.'1
OJ<

SGS·1HOMSON _ _ _
29/50
~o«:llR@rnl!.Wii'IlB@OOOO:iI!

41

EF9345
Figure 16 ter : Go Alphanumeric Character Set in 40 Character/Row Mode - EF9345 R005.

C6
C5

C4
CJ

C2

C1

CO

a

a

a

0

a

0

0

1

a

a

1

a

0

a

1

1

0

1

a

a

a

1

a

1

a

1

1

a

e

1

1

1

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

0

a

1

1

0

1

1

1

1

0

1

1

1

1

a
a
a

a
a

a

a

1

1

1

1

1

1

a

1

1

1

a

1

a
a

1

a

1

•••••••
11 ••••• 1 •
II
•••••••
•
••••••••
•
•••••••
•
.11
•••••
II
1111111 •••
•
•••••••
••••• 11 •
II
II
•••••••
II
•••••••
•••••••
•
•••••••
•
•
•••••••
•••••••
•• 11 •••• •
•
EB8 EF9345·31

42

EF9345
Figure 17 : GlO Semigraphic Character Set.

MOSAIC Semi·graphic

C3

C2

C'

CO

0

0

0

0

0

0

0

,

0

0

,

0

0

0

, ,

0

,

0

0

,

0

0

, ,

0

, , ,

,

0

0

0

,

0

0

,

,

0

,

0

,

0

, ,

1

,

0

0

1

1

0

1

,

1

1

0

, ,

1

1

0

C6

,

,

C5

0

0

C4

0

,

,

,

0

SEPARATEO Semi·graphic

,
,
,

0

0

0

0

,

0

0

0

0

,

,

,

••••• 11.

••••••••

•••• 11 ••
•••• 111.
[iljj mi II'II lu1l'i'jBa .11
~
~r",,' IIIlII'

1'1 .• " ....
rr"'I[J,nTIl~
~-,

I

I

t

,
0

iji,
!"i
t'
~:;:.·l';.·
IIUI·"~I~.

••••• 11.
11.lllla
••••• 11.

B••• II ••

••••• 11.
••••• 11.
11 ••• 11.

••••••••
••••• 11.
••••••••

E88 EF9345-32

- - - - L"'II ~~~~~~=:il~~

---31/50

43

EF9345
Figure 18: G11 Stroke Set.

C3

C2

Cl

CO

0

0

0

0

0

0

0

I

0

0

1

0

0

0

I

1

0

1

0

0

0

1

0

1

0

I

0

I

I

I

I

0

0

0

I

0

0

I

1

0

I

0

I

0

I

I

I

I

0

0

I

I

0

I

I

I

I

0

I

I

I

I

1

0

C51

oro

C41

o

I

1

••
••
••
••
••
'.
fl.
••
••
••
••
••I
I

I
I

III.~

.1
II

E88 EF9345-33

32/50

44

EF9345
Figure 19 : G20 and G21 Accentued Character Sets for 9345.

csl o I a I 1 I 1 I
c51 a I 1 I a I 1 I

-

85

CJ

III.
I •••

0

r---

1
'---

C2 Cl CO

0

0

0

0

0

0

0

1

0

0

1

0

0

0

I

I

0

1

0 0

E..mpI. :

1 0
I x loll1 0 10lolo111
lolll o lolxlxlxlxl
7

BvteC

Byte B

Byte A

6

5

4

3

2

I I I I xl I I I I
X

X

=

X

X

X

X

X

X

l-

0 1

0

1

0

1 1

0

0

1

1

1

1

0

0

0

1

0

0

1

I

0

I

0

I

0

I

I

I

I

0

0

I

I

0

I

I

I

I

0

I

I

I

I

bits deflOed by user.

•

I

C4

I o I 1I

.\I~
I~I~

I-

••
••I
I
••
••
••
••I
I
••
••
••
••
II

et.

E88 EF9345·34

33/50

45

EF9345
Figure 19 bis : G20 and G21 Accentued Character Sets for 9345 - R003.

C61
csl
~
0

f---

•
'--

E .....pI.:

7

By'eC
Byte B

By'. A

6

o I o I '
o I , I o

I ,, II
I

••••
••••
5

4

3

2

,

0

Ixlol'lolololol'l
10 1, 10 1olxlxlxlxl
Ixlxlxlxlxlxlxlxl
x '* bib defined by user.

II

!-

I C4 I
C3

C2

C,

co

0

0

0

0

0

0

0

I

0

0

I

0

0

0

,

I

0

,

0

0

0

,

0

,

0

1

1

0

0

I

,

I

I

0

0

0

I

0

0

I

I

0

I

0

I

0

I

I

I

I

0

0

I

I

0

I

I

I

I

0

I

I

I

I

o

I ' I

I •

••
••
••I
I
••
••
••
••I
I
II
••
II.
••
.1

I.

EBB EF9345-35

34/50

46

Figure 19 ter : G20 and G21 Accentued Character Sets for 9345 - R005.

c61
CIII

~

o
o

I
I

T

o

I

1

1

,

o

I

1

1

•• 11

0

I--

•• 11

1
'--

I C4 I

I

1

C3

C2

Cl

CO

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

Exampl. :
7

6

5

4

3

2

1

0

Byte C

I xlol'l ololoI01'1

Byte B

lol'1 010lxlxlxlxl

Byte A

Ixlxlxlxlxlxlxlxl
X

!~

=bits defined by user.

n

o

I

1

,

I •

••
••I
I

II

r:i'.
~I
~

lil

hltiilll

0

I

1

1

1

0

0

0

1

0

0

1

I

0

1

0

1

0

I

1

I

I

0

0

1

1

0

I

I

I

I

0

I

1

1

1

III

.11

••
••I
I
••
••
••
.1

ESS EF9345·36

35/50

47

EF9345
80 CHAR/ROW CHARACTER CODES
To display pages in 80 character per row format,
one of two character code formats must be selected:
• Long (12 bits) code : 4 parallel attributes and
large on-chip 1024 semigraphic character set,
• Short (8 bits) code: no attribute, no semigraphic
set.
Both formats address the on-chip Go set (128 characters 6 x 10). None allows UDS addressing.
LONG CODES.
Each 6 pixels x 10 lines character window on the
screen is associated with a 12-bit code in memory,
namely a C byte and an attribute nibble A (figure
10). C7 bit designates the set.

o.

• Alphanumeric set: C7 =
C(0:6) designates one out of 128 alphanumeric
characters in the Go on-chip set. This set is common to the 40 char/row format, with the 2 right
most columns truncated (see figure 25).
A(0:3) gives 4 parallel attributes.
• Mosa"ic set: C7 = 1.
A(1 :3) and C(0:6) address a dedicated mosa·le
character. Each ofthese address bits controls the
foreground/background status of a 3 pixels x 2
lines sub-window: foreground when the bit is set.
AO provides a color select attribute.

Figure 20 : 80 Char/Row Character Code.

76543210

3

2

1

0

2

1

0

MOSAIC CHAR CODE

ALPHANUMERIC CHAR CODE
N = Negative
F = Flash
U .'" Underline
0= CoJorset

3

76543210

..

..

.,..

!3pel'!3pel'!

1
2

128 ALPHANUMERICS

3

In GO set.

4

5
6

co

Cl

C2

C3

C4

C5

DEDICATED

MOSAIC
SET

C6

Al

A2

A3

EBB EF9345·37

SHORT CODES.

ACCESS TO THE CODES IN MEMORY.

They are derived from the long code by giving a 0
implicit value to each bit of the A nibble: positive,
not underlined, not flashing.

KRL command transfers 12 bits from/to the R1 and
R3 registers to/from memory. The read modify write
operation, necessary to write the A nibble in memory, is automatically performed provided that the A
nibble is repeated in the R3 register (figure 22). Dedicated auto-incrementation is also performed when
required.

PACKING THE CODES IN MEMORY.
Long codes are paired. A pair is packed in a 3-byte
word. Therefore, the 80 codes of a row fill a 120byte row buffer (figure 21). The left most position on
the screen is even. Its corresponding C byte is at
the beginning of the first buffer. The next position on
the screen is odd. Its corresponding C byte is at the
beginning of the second buffer. Both nibbles are
packed in the third buffer. With short codes, the
same scheme yields 80-byte row buffers.

36/50

48

KRC command does a similar job forthe short codes
(figure 23).
A very simple scheme allows the microprocessor to
transcode an horizontal screen location into a pointer (figure 24). The joint use of this scheme with the
dedicated command alleviates all the packing/unpacking troubles.

EF9345
Figure 21 : 80 Char/Row Code Packing.

6

5

4

o

3

6

5

o

4

r---------------~

I

C
PACKING 1 CODES
IN:I BYTES
IN MEMORY

I

L_~_~_~_J_~_J_J_J

I

r-----------I

~ --I--I~

,

L_J_~_~_~_~_~_~_~

------...,

----------

I

A

~_.J._J_J

I

~

EVEN POSITION

B (eyp.n)

B + ,

B .2

ODD POSITION

E88 E F9345·38

Figure 22 : KRL Command: Sequential Access to Long Codes.

....- 0 district number

--

~'1'~-,
/

'.I

,

,
,
,,

,

KRL COMMAND

Rl
R2
R3
R4
R5
R6
R7

\

C
A
-

y

Beven ..... __ even position

\

- .......

,

r·t

/

B

-t-

1 odd ............. odd position

D, Y

B. X

IAI

~

B +1

x
R3

7

6

5

4

3

2

N

F

u

o

N

F

The A nibble should be respected.

u

o
o
E88 EF9345-39

37/50

49

EF9345
Figure 23 : KRC Command: Sequential Access to Short Codes.

4------

J-I-

KRC COMMAND
/

/

C
-

Rl
R2
R3
R4
R5
R6
R7

B (evenl

.\
\

I

\
I

I

,

,

\
\

D. Y

I

,

,

1;t

B.X

0 distr let number

/

B

+

1 (oddl

x
E88 EF9345-40

Figure 24 : Transcoding an Horizontal Screen Location into a R7 Pointer.
6

5

4

3

I I
bl

o

2

x51 x41 X3 1 X2 1 Xl

6

I

I XO I bO

Rotate right

11>0 I bl

5

4

I

X5 1 X4

o

3

3

I X3 1 X7 I Xl 1

~

Character pOSition (0 to 19)

X

J
Block parity

DISPLAYING THE ATTRIBUTES - DOR REGISTER.
Short code and mosaIc characters are not flashing,
not underlined and "positive".
The attributes are processed in the following order:
•

Underline or underlined cursor: foreground is forced on the last slice (NT = 9).
• Flash : background is periodically (0.5 Hz
- 50 %) forced on all the window. The phase depends on the negative attribute.

0

(010391

E88 EF9345·41

• Color select: a "positive" character is displayed
with a background color same as the margin color. The foreground color is selected in DOR register by the D attribute.
• Negative: when the character is negative, background and foreground colors are exchanged.
In complemented CURSOR position, these colors are complemented.
• Insert: the D attribute selects one insert value in
DOR register. This attribute is then processed up
to the current insertion mode (see screen format
and attribute insert section).

76543210

DOR

I i, I

61

I G, I R,!

c,

iO

ISo I

I
I
I
I

~D=l--'l~

Go

I AO

I

Co
D=O__.

I

MAT

I - - x x! - [B~
eM

The pixel shift frequency is fClK (12MHz).

38/50

50

D

N

BACKGND
COLOR

FOREGND
COLOR

i

0
0

0

1
1

0

CM
Co
CM
C1

Co
CM
C1
CM

iO
iO
il
il

1
1

E88 EF9345·42

EF9345
Figure 25 : Go Alphanumeric Character Set in 80 Character/Row Mode - EF9345.

C3

C2

C1

co

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

C7

0

0

0

0

0

0

0

0

C6

0

0

0

0

1

1

1

1

C5

0

0

1

1

0

0

1

1

C4

0

1

0

1

0

1

0

1

IIIIIIII

III1IIII

IIIIIIII
IIIIIIII
IIIIIIII

III1IIII

IIIIIIII
IIIIIIII
IIIIIIII
IIIIIIII
IIIIIIII
IIIIIIII
IIII IIII
IIII IIII

11111 1III
IIII IIII

E88 EF9345·43

51

EF9345
Figure 25 bis : Go Alphanumeric Character Set in 40 Character/Row Mode - EF9345 R003.

C3

C2

Cl

co

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

C7

0

0

0

0

0

0

0

0

C6

0

0

0

0

1

1

1

1

C5

0

0

1

1

0

0

1

1

C4

0

1

0

1

0

1

0

1

IIIIIIII
IIIIIIII
IIIIIIII
IIIIIIII
IIIIIIII

III1IIII

IIIIIIII
IIIIIIII

III1IIII

IIIIIIII
IIIIIIII
IIIIIIII
IIIIIIII
IIIIIIII
IIIIIIII
!ml~11111

.

.

:

:

:: ... :

~.

I.

., •. ~

·t

..

,,~.

;; I

::~::::

:

t!"1t

~

.

:!:::::

E88 EF9345·44

40/50

~

- - - """'I
. 52

SCS.THOMSON _ _ _
~~Il:L'J@rn~rn©1rL'J@IIl~Il:~

EF9345
Figure 25 ter : Go Alphanumeric Character Set in 40 Character/Row Mode - EF9345 R005.

C3

C2

Cl

CO

0

0

o

0

0

0

o

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

C7

0

0

0

0

0

0

0

0

C6

0

0

0

0

1

1

1

1

C5

0

0

1

1

0

0

1

1

C4

0

1

0

1

0

1

0

1

IIIIIIII

III1IIII

IIIIIIII

III1IIII

IIIIIIII
1111111111

III1IIII

IIIIIIII
IIIIIIII
IIIIIIII
IIIIIIII
IIIIIIII
IIIIIIII
IIIIIIII
IIIIIII I
IIIIIII I

EBB EF9345-45

53

EF9345
MICROPROCESSOR ACCESS COMMANDS
A microprocessor bus cycle may transfer one byte
from/to the microprocessor to/from a directly addressable register. These registers provide an indirect access :
o to/from 5 on-chip indirect registers: ROR, DOR,
MAT, PAT and TGS.
o to/from the private memory.
Due to address/data multiplexing, a bus cycle is a 2
phase process (see Timing diagram 1 or Timing diagram 2).

A8 = LCS
This is the latched value of CS input pin.

o

EF9345 is selected when the following condition is
met: ASN = 2 (Hexa) and LCS = O.
Therefore, EF9345 is mapped in the hexadecimal
microprocessor addressing space from XX20 to
XX2F, where XX is up to the user. When EF9345 is
not selected, its AD bus pins float and no register
can be modified.

ADDRESS PHASE.
The falling edge of AS latches to AD(O:7) bus state
and CS signal into the temporary A address register (figure 26).
o A(O:2) = i
This register index designates one out of 8 direct
access registers Ri.
o A3 = XQR
This is the execution request bit.
o A(4:7) = ASN
This is the Auto-Selection Nibble.

876543210

I I

I

I

I

1I

IADOOEg

1'1

-,- L ~I~~I:':'~~~,

~I

.

Execution request (XQR)

L ._ _ _ _ _ _ . -

Auto select nibble
(compared 1000101

L -_ _ _ _ _ _ _ _ _

lCS (Latched

CS)

EBB EF9345·46

Figure 26 : Direct Access Registers.

6

5

4

2

I

R2
R3

R4

0

..-~

Rl

, D',

RS

B'
I

RS

10 1

RI

B
I

I Y'I
X'

I

IY
X
I

6
DATA
REGISTERS

II~

2

0

COMMAND
REGISTER

I

C~DE

I

I

PAR

) IwritHullly)

I

RO

I
It
I

4

6

AUXILIARY

3

2

0

STATUS

l 11

POINTER

MAIN

' - -_ _ _ _ _ _ _ _.... Alarm
' - - -_ _ _ _ _ _ _ _ _ BusV

POINTER

EBB EF9345-47

42/50

54

EF9345

o : without auto-incrementation.

DATA PHASE - REGISTERS.
When EF9345 is selected and while AS input is low,
the Ri register is accessed.
RO designates a write-only COMMAND register or
a read-only STATUS register.

p:

Pointer select
1 : auxiliary pointer
main pointer

o:
s, s :

Source, destination select
01 : source: MP ; destination: AP
10 : source: AP ; destination: MP

a, a :

Stop condition
01 : stop at end of buffer
10: no stop.

R1 to R7 hold the arguments of a command. They
are read/write registers.
R1, R2, R3 are used to transfer the data.
R4, R5 hold the Auxiliary Pointer (AP).
R6, R7 hold the Main Pointer (MP).
(see memory organization; pointer section for pointer structure).

STATUS REGISTER
This is a read-only, direct access register.
S7 : BUSY

COMMAND REGISTER.
This register holds a 4-bit command type and 4 bits
of orthogonal parameters (see command table).

S6 :AI

Type
There are 4 groups of command:
• The IND command which gives access to on-chip
resources,
• The fixed format character code transfer commands,
• The variable character code handling commands,
• The general purpose commands.

J

LXm or LXa is set when respectively
the main pointer or the auxiliary pointer holds X = 39 before a possible incrementation.
The alarm bit S6 is set when LXm or
LXa is set and an incrementation
is performed after access.

S5:LX m
S4: LXa

S3:

Gives the MSB value of R1.

S2 :

Gives the vertical synchronization signal
state.
This is maskable by the VRM command.

Parameters.
R/W :

BUSY is set at the beginning of any
command execution. It is reset at completion.

S1 = SO = 0

Direction
1 : to DATA registers (R1, R2, R3)
from DATA registers.

Not used.

S3 to S6 are reset at the beginning of any command.

o:
r:

Internal resource index (see figure 27).

I:

Auto-incrementation
1 : with post auto-incrementation

The COMMAND TABLE shows every command
able to set, each of these status bits, after completion.

Figure 27: Indirect On-chip Resource Access.
16543210

I, I I !:o::EJwL:--L.J
L
0

x

Rl

0

R1
R3

R'

Register
ROM,,)

1

TGS

1

MAT

3

PAT

A5

,
5

-

DOA

)

,
I

6

-

In

,
a

R6
R)

• Note" A stice

INDCOMMAND

ROR

iI

40C only can be read from the Internal character generalor The slice address muST be Initial lied In Rfi. R7

R1

E88 EF9345-48

43/50

55

EF9345
NOTES ON COMMAND EXECUTION.
1. The execution of any command starts at the trailing edge of DS when (and only when) :
_ EF9345 has been selected,
_ XOR has been set,
at the previous AS falling edge.
This scheme allows loading a command and its argument in any order. For instance, a command,
once loaded, may be re-executed with new or partly new arguments.
2. At power on, the busy state is undeterminated.
It is recommanded to load first a dummy command with XOR = 1 before any effective command.
3. While Busy is set, the current command is under
execution. Register access is then restricted.
Register access with XQR = 0
_ Read STATUS is effective.
_ Write COMMAND or any other register access are ineffective.

That is to say, the microprocessor reads undetermined values and may not modify a register.
Register access with XQR = 1
_ Read STATUS or write COMMAND are effective,
_ Access to other registers is ineffective.

However, the previous command is aborted and the
new command execution launched (with an initial
state undetermined for registers and memory locations handled by the aborted command).
4. Execution suspension.
The execution of any com mand (except VRM, VSM)
is suspended during the last and first TV line of an
active row. This is because the memory bus cannot
be allocated for microprocessor access during 'this
104 !lS period.

44/50

56

This holds too for internal resource access because
on-chip data transfer uses intemal data memory
bus.
IND COMMAND (see figure 27).
This command transfers one byte between R1 and
an internal resource. The r parameter designates
one on-chip indirect register.
FIXED FORMAT CHARACTER CODE ACCESS:
KRF, KRG, KRL KRC
Each of these commands is dedicated to transfer
one complete character code between DATA registers and memory. MP is exclusively used.
KRF transfers 24 bits.
KRG transfers 16 bits.
KRL transfers 12 bits.
KRE transfers 8 bits.
Code packing, pointer and data structures are explained in the corresponding character code section.
When auto-incrementation is enabled, MP is automatically updated after access so as to point to the
next location. This location corresponds to the next
right position on screen. When last position (X = 39)
is accessed, LXm is set. When last position is accessed with auto-incrementation, alarm is also set. MP
is then pointing back at the beginning of the row :
there is no automatic Y incrementation.
VARIABLE CODE HANDLING COMMANDS:
KRV EXP, CMP, KRE
An overview on these commands is given in "handling the variable codes" (40 char./row section).
KRV uses R5 to point the attribute file. LXa is set
when this file is full (the last attribute pair has been
accessed).

EF9345
EXP and CMP use MP and R5 in the same way as
KRV. Furthermore, R4 points to a working double
buffer. These two commands process a whole row
buffer and stop either at the end of the row buffer or
when the file overflows. In the last case, the alarm
bit is set.
KRE uses MP to point to a buffer and R4 to point to
a working double buffer. R5 is unused. In other respects, KRE is identical to KRL.
For these commands, R4(5:7) hold the LSB's block
dress of the working buffer W.

765432

0

C:?1~zT I-I~Y-I-I

J

R4

------~

zw

YW

MVB transfers a byte from source to destination,
post-increments the 2 pointers and iterates until the
stop condition is met. MVD and MVT are similar but
work respectively with 2 byte word and 3 byte word.
That is to say, MVB works on buffers, MVD on double buffers and MVT on triple buffers. If the parameter a = 1, the process stops when either source or
destination buffer end is reached. If the parameter
a = 0, the process never stops until aborted. In this
case, main pointer overflow yields to a Y incrementation in MP. So, a whole block or page may be initialized.
MISCELLANEOUS COMMANDS: INY, VRM and
VSM.
INY command increments Y in MP.

ZW3 is given by bit 6 of R6

GENERAL PURPOSE ACCESS TO A BYTEOCT.
This command uses either MP

MOVE BUFFER COMMANDS: MVB, MVD, MVT.
These are memory to memory commands which
use R1 as working register.

or AP pointer.

When MP is in use, an overflow yields to a Y incrementation.

VRM and VSM respectively reset and set a vertical
synchronization status mask. When the mask is set,
status bit S2 remains at o. When the mask is reset,
status S2 follows the vertical sync. state : it is reset
for 2 TV lines per frame and stays at 1 during the remaining period. It becomes readable by the microprocessor from the status register. After power on,
the mask state is undetermined.

45/50

57

(}l

""

m

0)

OJ

();

o

"T1
CD

COMMAND TABLE
Type
Indirect

INO

Parameter

Code

Memo
7

6

S

4

3

1

0

0

0

RfIN

2

1

0

r

Status

Arguments

AI LX m LX. R17 R1 R2 R3 R4 RS R6 R7
0

0

0

0

0

-

- - -

40 Characters - 24 Bits

KRF

0

0

0

0

RfIN 0

0

I

X

X

0

0

C

B

40 Characters - 16 Bits

KRG

0

0

0

0

RfIN 0

1

I

X

X

0

0

A·

B·

80 Characters - 8 Bits

KRC

0

1

0

0

RfIN 0

0

I

X

X

0

0

C

-

- -

80 Characters - 12 Bits

KRL

0

1

0

1

RfIN 0

0

I

X

X

0

0

C

-

A

-

-

40 Characters Variable

KRV

0

0

1

0

RfIN 0

0

I

X

X

X

X

C

B

A

-

Expansion

EXP

0

1

1

0

0

0

0

0

X

0

X

0

C

B

A

Compression

CMP

0

1

1

1

0

0

0

X

0

X

0

C

B

A

Expanded Characters

KRE

0

0

0

1

RfIN 0

0
0

I

X

X

0

0

C

B

Byte

OCT

0

0

1

1

RfIN P

I

X

X

X

0

D

Move Buffer

MVB

1

1

0

1

s s

a

a

0

0

0

0

W

Move Double Buffer

1

1

1

0

s s

a

a

0

0

0

0

W

~~

MVD

Move Triple Buffer

MVT

1

1

1

1

s s

a

i!li;!

Clear Page (4) - 24 Bits

ClF

0

0

0

0

0

~

i!5cn
@.

i'lo
~I:
@cn
~O
:&liz

1

0

MP

(2) 3 + 3 + j

3.5 + 6 • j

MP

(3) < 247

-

PWXF

MP

(3) < 402

-

A

PW -

MP

4

7.5

-

-

AP

MP

4

4.5

-

-

AP

MP

(2) 2 + 4. n

-

AP

MP

(2) 2 + 8. n

-

0

0

0

W

X

X

0

0

C

B

A

W

ClG

0

0

0

0

0

1

1

1

X

X

0

0

A·

B·

1

0

a

1

1

0

a

1

0

a

0

0

-

Vertical Sync Mask Reset

VRM

1

0

1

0

1

0

1

-

-

-

-

Increment Y

INY

1

a
a

1

1

0

a

0

0

0

~ Operation

NOP

1

0

a

1

a a 0
a 0 a

-

-

-

-

s

a, a:

Source. destination
01 : source = MP ; destination = AP
10 : source - AP ; destination = MP
Stop condition
01 : stop at end of buffer
10 : no stop
Indirect register number

7.5

XF

VSM

S,

7.5

5.5

PW XF

0

(2) n

4

MP

9.5

a

(1) Unit

MP

11.5

1

Not affected
W
: Used as working register
PW (Z, YW) : Working buffer
X
: Set or Reset
XF
: X File
I
Pointer incrementation
D
Data
MP
Main pointer
AP
: Auxiliary pointer

3.5

9

0

-

Read

2

12.5

- - -

1_ -

Write

MP

Clear Page (4) - 16 Bits

Pointer select
t : auxiliary pointer
a : main pointer.

A W

MP

-

AP
-

- - - - -

-

- -

MP

(2) 2 + 12. n

MP

< 4700 (1 K code)

MP

Y

-

< 5800 (1 K code)

-

(,)

"'"

(JI

MP

Vertical Sync Mask Set

P

Execution Ti me (1)

1
1
2
1

-

12 clock periods (= 1 ~) without possible suspension.
: total number of words,; 40 ; j = 1 for long codes, j = 0 for short
codes.

(3)

: Worst case (20 long codes + 20 short codes).

(4)

: These commands repeat KRF or KRG with Y incrementation when X
overflows. When the last position is reached in a row. Y is
incremented and the process starts again on the next row

EF9345
INTERFACE WITH EF6801

~

('.....,

PORTe

ADIO:71

EF9345

EF6801

SCI

AS

E

05

SC2

R/W

lOS

cs
E88EF9345-49

MINIMUM APPLICATION WITH 2K X 8 MEMORY
One page memory terminal in 16-bit fixed format or 24-bit compressed format.

.l'\.

V

00-D7

ADM 10:71

VL- L-1\
"

EF9345
ASM

AM (8:101

V

74LS
373

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-V

1

AO-A7

RAM
cs

~

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2K x 8
ET2128

ABA10

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E88EF9345-50

47/50

59

EF9345
TYPICAL APPLICATION WITH 8 K X 8 DYNAMIC OR PSEUDO-STATIC RAM
Multipage terminal with possibility of multiple user definable character sets.

ADM 10:71

"-

A

...

.....

~

00-07

AO-A7

RAM

EF9345

8Kx8

AsM

CE

Oe

OE

We

M

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AM 18:121

.....

E88EF9345·51

MAXIMUM APPLICATION WITH 16 K X 8 MEMORY
Multipage terminal with user definable character sets and buffer areas.

ADM (0,7)

Vt--

II

1!7
04·07

:i~

y

-"

!2~
w ...

AO-Al

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AM (8,,31

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.-

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~

D

Q

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EF9345

00-03

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ASM

n

" -;-

CK

D

Q

CAS

DRAM·

~
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16K .4

CK

'-'

AAS

,

WE

W

-

c-

DE

ClK

T

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12MHz

CLOCK

E88EF9345·52

48/50

60

EF9345
ORDERING INFORMATION
Part Number

Package

Character
Generator

EF9345PRYYY
EF9345FNRYYY

DIP40
PLCC44

RYYY
RYYY

PACKAGE MECHANICAL DATA
40 PINS - PLASTIC DIP

Lll
3.9

,
~
15~

0.38
0.508

(1

- I

t

Nominal dimension

(21 True geometrical position

14
(1)

W
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40

PINS

49/50

SCS·THOMSON
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61
-

----~----~---~-~-

EF9345
PACKAGE MECHANICAL DATA (continued)

44 PINS - PLASTIC CHIP CARRIER
Pin 1 .

t fication

16510

I¥62l

1740
17,65

~
min.

50150

62

44 pins

TS9347
SINGLE CHIP SEMI-GRAPHIC DISPLAY PROCESSOR
• SINGLE CHIP LOW-COST CRT CONTROLLER
• UP TO 60 Hz SCREEN REFRESH RATE
• 32 KBYTE DEDICATED MEMORY ADDRESSING SPACE
• 2 SCREEN FORMATS:
25 ROWS OF 40 CHARACTERS
25 ROWS OF 80 CHARACTERS
• ON-CHIP 154 ALPHANUMERIC AND 128 SEMIGRAPHIC CHARACTER GENERATOR
• EASY EXTENSION OF USER DEFINED ALPHANUMERIC OR SEMI-GRAPHIC SETS
(> 1K characters)
• 40 CHARACTERSIROW ATTRIBUTES:
FOREGROUND AND BACKGROUND COLOR,
DOUBLE HEIGHT, DOUBLE WIDTH, BLINKING, CONCEAL, INSERT
• 80 CHARACTERS/ROW ATTRIBUTES:
UNDERLINING, BLINKING, REVERSE, COLOR SELECT
• PROGRAMMABLE ROLL-UP, ROLL-DOWN,
UPPER OR LOWER SERVICE ROW
• ON-CHIP R, G, B SHIFT REGISTERS
• ANALOG COMPOSITE LUMINANCE SIGNAL
OUTPUT
• VERSATILE 1/0 CONFIGURATION: VIDEO
AND SYNC OR GENERAL PURPOSE 1/0
PORTS
• ADDRESS/DATA MULTIPLEXED BUS DIRECTL Y COMPATIBLE WITH STANDARD
MICROCOMPUTERS SUCH A 6801, 6301,
8048,8051

P
DIP40

(Plastic package)

FN
PLCC44

(Plastic Chip Carrier)

DESCRIPTION
A complete display control unit may be implemented with TS9347 and a single standard memory
package. This new advanced CRT controller drastically reduces IC cost and PCB area for low-end color or monochrome terminal.
January 1989

1/42

63

TS9347
TYPICAL APPLICATION

2Kx8to32Kx8
memory

*

L

to

TS9347

;
MODEM

TSG7515

-- /hgm

MCU
EF6801

~

TSG7514

j

j

#t/J

E88TS9347-01

PIN CONNECTIONS
TS9347
CP/lROO

v ss

B

64

TS9347
CFN/ROO

ADMO

V ss

40

ADMO

ADM1

V sse

39

ADM1

ADM2

6E

3

38

ADM2

ADM3

WE

4

37

ADM3

ADM4

ASM

5

36

ADM4

ADM5

V DD

6

35

ADM5

ADM6

Y

7

34

AM9

35PAM8

,.

33pAM10

"

31PAM12

11

30

AM10

eLK

12

29

AM11

SYNC IN

ClK

AM12

SYNC IN

13

AM12

AS

SYNC IN

AM13

AS

,.

28

OS

AD7

DS

15

PAM13
26 PAM14
25 PAD7
24 PAD6
23 PAD5
22 PAD4
21 PAD3

18

AD2

CS

CS[

20

,.

34PAM9

ClK

AD2 [ 19

:;;

11

XTAl

AD1

~

12

AM11

AD3

~

XTAL

AM10

AD4

~

CLKOUT

XTAl

AD1

>~ ~ ~ ~ ~

36PADM7

31

ADO

-

G 10

AM8

10

17

~

>

ADM7

G

16

N

39~ADM4

AM9

R!W

M

37PADM6

32

ADO

o:t

3SPADM5

9

AD5

1(1

B 8

R

AD6

<.0

R 9

B

DS

>81i I~ ~~

ADM6

AM8

R!W

>'5
Y 7

ADM7

33

'-'

ClKOUT

AS

2/42

TS9347
CP/2ROO

27

Gi
':fI SGS·THOMSON
"'DO::lIR@m~I<©'ii'Ill@~DI:lI

13

32PAM11

16

30PAM13

Rm 17

29PAM14
~

~

~

~

~

~

~

re

§

~

~ ~ 1l

~

~ ~ 1l i!i

[:;

N

l(l

!Il

" " "

TS9347
BLOCK DIAGRAM

ROW BUFFER
40.24 BITS

DATA BUS

AS

T--~-

os

ROM

CHARACTER

cs

GENERATOR

R,G.R

ATTRIBVTE LOGIC

[

DOR
TRANSOODER

PAT

MAT

VDOC
OAC

vssc

XTAl
ClJ(

CLKOII

E88TS9347-02

Gi
SCiS-THOMSON
~/IililUICIII@I--- 241lS - - - I

312
SCAN LINES

1

t

AC2T%E
SCAN LINES

lONE ROW = 10 SCAN LINES
ACTIVE
DISPLAY
TIME

.___ L___ L----~----'--_-----'
MEMORY CYCLE

I

I "p

INACTIVE LINE

DUM

LAST ROW LINE

UDS

I
I

LD

LD

FIRST ROW LINE

UDS I

LD

RFSH

OTHER ROW LINE

UDS:

"p

RFSH:

I

I

I

"p

I

DUM: dummy cycle
liP : indirect access to memory

LD

I

I ~P
I

RFSH : refresh cycle
UDS : slice read cycle
LD : read cycle to load the internal
row buffer.

RFSH: "p
--lp..s________.

~lIlS--

- - - - - - 4 0 p.s

•

. . - - 24 J.lS -----..

E88TS9347-05

8/42

70

1~9::S4f

Figure 4 : Logical to Physical Address Transcoding Performed on-chip.

z (0 to 31)

----------_
..._----I I
D

LOGICAL ADDRESS

4

I

3

x (0 to 39)

Y (0. B to 31)

B

2

I

I

1

0

4

I

3

I

2

I

I

I

0

I I

5

I4 I3

I

2

I

I0

I

I

TRANSCODING

PHYSICAL ADDRESS 1'41'3 1'2

1"

----------~------------~

1'0 I

9

I

B

I

Y;;'B

6

5

I

4

I3

PHYSICAL ADDRESS AM (3 :10)

XandY
CONDITION

I

7

10

9

8

7

6

5

4

3

X5 =0

bO

Y4

Y3

Y2

YI

YO

X4

X3

X5 = I

bO

0

0

Y2

YI

YO

Y4

Y3

bO

0

0

X5

X4

X3

0

0

YO =0

E88TS9347 -06

SCREEN FORMAT AND ATTRIBUTES OUTPUTS CONFIGURATION
The screen format and attributes are programmed
through 5 indirectly accessible registers : ROR,
TGS, PAT, MAT, and DOR. IND command allows
accessing to these registers. TGS is also used to
select the timing generator options (see Screen Format Table).
ROW AND CHARACTER CODE FORMAT: TGS
(6:7)
Two row formats and 4 character code formats are
available but cannot be mixed in a given screen.
TIMING GENERATOR AND CONFIGURATION
OPTIONS: TGS (1 :5)

TGS3 = 1 enables VSI to reset the internal line
count: SYNC IN input is sampled at the beginning
of the active area of each line. When the sample
transits from to 1, the line count is reset at the end
of the current line.

a

=

=

TGS3 TGS2 1 enables HSI to control an internal digital PLL : HSI and on-chip generated H. SYNC
OUT are considered as in phase if their leading
edges match at plus or minus 1 clock period. When
they are out of phase, the line period is lenghtened
by 1 clock period (80 ns at 12 MHz).
Screen Format Table resumes the different combinations.

TGS1

= 0: noninterlaced mode, 312 lines/frame.

TGS (4,5) : output configuration

TGS1

= 1 : interlaced mode,

Three output pins may be configured to output either video signals or general purpose output ports.
The Screen Format Table summarizes the possible
configurations, with the following definitions:

312.5Iineslframe.

TGS (2,3) : input synchronization configuration.
The SYNC input may be interpreted as a synchronization signal or as a general purpose input port,
which state can be read by the microprocessor in
the status register (bit 2). Alternatively, the vertical
synchronization output from the timing generator
can be read in the same register.
The composite incoming SYNC IN signal is separated into two internal signals:
• Vertical Synchronization In (VSI)
• Horizontal Synchronization In (HSI)

R, V, B : Red, Green and Blue Video components
I

: Insert signal

HVS

: Composite H and V synchro output

P1, P2 : General purpose output ports
PAT2 gives the value of P1, PAT7 gives the value
of P2 : a logical "1" will cause a "high" on the corresponding output, while a "0" results in a "low" .

L..'1 SGS·THOMSON
rnilUil::IlIl@mI!.IO©"ii"Ii!©Il'lU@$

9/42

•h

71

TS9347
SCREEN PARTITION, PAGE POINTER ROR
(see top of the Screen Format Table)
The screen is partitioned in three areas:
• The margin
The service row
The bulk or remaining rows
MAT (0:3) declares the color of the margin and the
value 1M of its insert attribute.
DOR? and ROR register point to the page to be displayed : DOR? gives the MSB of the Z address,
ROR (?:5) three next bits, the LSB is implicitly ZO
= 0 (the page block address must be even). YOR
(= ROR (4:0)) gives the first row to be displayed at
the top of the bulk area. The next row buffers to be
displayed are fetched sequentially by incrementing
the Y address (modulo 24). This address never gets
out of the origin block. Incrementation of YOR by the
microprocessor yields a roll up.
SERVICE ROW: TGSO ; PATO

PAT1 =0 disables the bulk. When disabled, the corresponding scan lines are displayed as a margin extension.
CURSOR: MAT (4:6)
To be displayed with the cursor attribute, a character must be pointed by the main pointer (R6, R?) and
MAT6 must be set. The cursor attributes are given
by MAT (4,5) :
• Complementation :
The R, G, B or each pixel is logically negated:

R,G,B~ A,G,B
• Underline:
The underline attribute is negated
• Flash:
The character is periodically displayed with, then without the cursor attribute (50%/50% ~ 1 Hz).
FLASH ENABLE (PAT 6) - CONCEAL ENABLE
(PAT3)

The 10 scan line service row can be displayed at the
top or the bottom of the screen, depending on the
value of TGSO. The service row is fetched from the
origin block at Y = 0 ; it does not roll ; it may be disabled by PATO = 0 ; it is then displayed as a margin extension.

Any character flashing attribute is a "don't care"
when PAT6 = o. When PAT6 = 1, a character flashes
if its flashing attributes is set. It is then periodically
displayed as a space (50%/50% ~ 0.5 Hz).

BULK: PAT1 ; MAT?

* if PAT3 = 0, the conceal attribute of any character

The bulk is displayed for 240 scan lines. Each row
buffer is usually displayed for 10 scan lines. However, MAT? = 1 doubles this figure: then every character appears in double height (double height
characters are quadrupled).

10142

72

PAT3 is a 'don't care" for 80 char./row formats.
When any 40 char./row format is in use:
is a "don't care"
* if PAT3 = 1, the conceal attribute of each charac-

ter is interpreted : a concealed character appears
as a space on the screen.

TS9347
INSERT MODES: PAT (4:5)
These modes make sense only if the insert signal I
is available on the G pin, that is to say when
TGS4 = 1.
During retrace, margin and extended margin periods, the I signal outputs the value of the insert margin attribute: I = 1M = MAT3.
During active line period, the I output is controlled
by the insert mode, and 11 and 12, the insert attributes of each characters. The I output may have several uses: (See figure below).

As a margin/active area signal in the Active Area
Mark mode
As a character per character marker signal in the
Character Mark mode
As a video mixing signal in the other modes, provided that the TS9347 has been vertically and horizontally synchronized with an external video
source: the I output allows mixing TS9347 video
output (I = 1) and external video signal (I = 0). This
mixing may occur for the complete character window (Boxing mode) or only for the foreground pixels
(Inlay mode).

VIDEO OUTPUT DURING ACTIVE PERIODS
Insert Mode

11

12

Char. Level Pixels

I

Video Output

Active Area Mark

-

-

-

1

Unchanged

Character Mark

0

-

-

0

Unchanged
Unchanged

1

Inlay

1

-

0

Boxing and Inlay

Background
Foreground

1

-

0

-

1

0
1
1

1

1

1

-

Background
Foreground

Comments

Non Insert

1

Black
Black
Unchanged

0
1
0
1

Black
Unchanged
Black
Unchanged

Non Inserted
Boxed

0
0

Inlaid

Inlaid

SCREEN FORMAT TABLE

~

MEMORY

0

SERVICE ROW

-.

Y ORIGIN
Y ORIGIN + 1

,
,

,

i

I

8

~
31

.I

3

y 9RIGIN + 1

,

I

SERVICE ROW

i

LOWER SERVICE ROW

UPPER SERVICE ROW

765

><",1

Y ORIGIN

,/

o

2

.

~

L ________
..

ROR (r

I

= 7)

..

Ortgm row address
YO~ " 108 w 31)

Block origin leven)

Z4" 00R7

E88TS9347 ·07

11/42

73

TS9347
SCREEN FORMAT TABLE (continued)

SYNC. IN PIN FUNCTION
INPUT PORT

STATUS REG.

SYNCHRONIZATION

(BIT 21

TSG2

TSG3

INPUT PORT

NO SYNC.

0

0

V.SYNC. OUT

NOSYNC.

1

0

V.SYNC.

SYNC. IN

V.SYNC.

0

1

COMPOSITE SYNC. IN

V.SYNC. OUT

H.ANDV.SYNC.

1

1

OUTPUT PINS

TGS4

TG85

B

G

R

B

G

R

0

0

8

I

R

1

0

P2

PI

HVS

0

1

P2

I

HVS

1

1

-1
7

6

-------5

4

3

2

TGS Ir

~

1)

Service row low

I

Interlaced

CHAR CODE

! 40 CHAR LONG

~

CHARSHORT

7

6

5

4

3

2

BO CHAR LONG

PAT Ir

80 CHAR SHORT
--------~

------'---'-----'

INLAY

·IITl ~
~

BOXING AND INLAY
CHARACTER MARK

ACTIVE AREA MARK
-~--------,-----

1
~

CU RSOR DISPlAY MODE

FLASH COMPLEMENTED

FIXED UNDERLINED
FLASH UNDERLINED
~--------

40 CHAR/ROW CHARACTER CODES
To display pages in 40 character per row format,
one out of two character code formats must be selected:
Long (24 bits) code: all parallel attributes.
Short (16 bits) code: mix of parallel and latched
attributes.
Short codes are translated into long codes by the
TS9347 during the internal row buffer loading process. The chaise of the character code format is obviously adisplay flexibility/memory size trade off, left
up to the user.
LONG CODES
This is the basic 40 char/row code. Each 8 pixel x
10 lines character window on the screen is associated with a 3-byte code in memory, namely the C, B,

74

Bulk enable
PUll

1

Conceal enable

fla5h enable
Port 2

76543210
1

--

FIXED COMPLEMENTED

12142

..

= 3)

Service row enable

I 'M 1 8 M! GM

~llTI

I R~ MAT (r

c

2)

Margin color

Margin insert
Cursor displav enable

Double heighl
~

NOTE; PROGRAMMING BIT VALUE

1;;;: True
0:= False

E88TS9347-07/1

and A bytes (Figure 5). A rowan the screen is associated with a 120 byte row buffer in memory.

3-byte code structure
1. C7 is a don't care. Up to 128 characters may be
addressed in each set. Each user definable set
holds only 100 characters : C-byte value ranges
from 00 to 03 and 20 to 7F (hexa).
2. B (3:7) give the type and the set number of the
character.
3. When 12, U, L are not programmable, the default
value of these attributes is O.
4. Character code byte A defines a two color set giving directly (Figure 6) the two values (B1, G1, R1)
and (BO, GO, RO) respectively affected to the 1 's and
the O's of the character pattern. The negative attribute, when set, exchanges the two values.

TS9347
Figure 5 : 40 Character Long Codes.
7

6

5

4

2

J

0
C BYTE

L

I I lit I
m

B BYTE

H

~'m."

1
I

:

N I B1 I G1 I R1

1

l

F IBO

IGo

IRo

type and set

I

~

1

:==
A BYTE
Background color

:

Flash (Blinkl

Foreground color
Negative (Rewrse videol

Number of Character
Per Set

Type and Set
B (3:7)

Set
Name

Set
Type

G10
GOE

SEMI
GRAPH

B7

BS

B5

B4

B3

0

12
12

1
1

0
1

L
L

128 STANDARD MOSAIC
32 COMPLEMENT. CELLS

12

0

U

L

128 ALPHANUMERICS

GO

0

0

U

L

100 ALPHA UDS

G'O

0

1

0

L

100 SEMI-GRAPHIC UDS

G'10

1

L

100 SEMI-GRAPHIC UDS

G'11

1

X

X

X

800 SEMI-GRAPHIC UDS

aO:7

1

C (O:S)

E88TS9347-08

Cell
Location
ON CHIP
ROM

ALPHA

SEMI
GRAPH

EXTERNAL
RAM

L = Double width
U = Underlined
Nole 1 : Double height, double width: a correct operation assumes that the same character code had been repeated in the pege memory
(Twice for double height or double width, four times for double size).
2 : Double height: each slice of the character is repeated: twice to get a 8 x 20 pattern. However for the alphanumeric characters, these
scheme is slightly d~ferent : the upper slice (SN = 0) is tripled, the next (SN = 1 to 8) are doubled, and the last (SN = 9) is displayed onIyonce.

13/42

75

TS9347
Figure 6 : Coloring a Character.
B

G

°°
°°1
11
1

°°1
1
°°1
1

R

Color Value

1°
1°
1°
1°

BLACK
RED
GREEN
YELLOW
BLUE
MAGENTA
CYAN
WHITE

Figure 7 : Shifting a Slice.

7

6

543

°

2

1°111°111°1°

°

------------~

Shift Direction: LSB First
1 = Foreground
o = Background·

E88TS9347-09

SHORT CODES
These 16-bit codes achieve memory saving whith
some penalties:
• 00 to 07 and GOE cannot be reached.
• Some attributes are latched and can be changed
only while displaying a space (delimitor code).

They are fully compatible with EF9345 (binary code
and display interpretation) if the 12 attribute is given
'.
the value O.
Figure 10 gives the short to long translation process
which occurs for each row - while loading the internal row buffer - before display.

HANDLING SHORT AND LONG CODES
The TLM, TLA, TSM, and TSA, commands allow an easy X, Y random or an X sequential access to/from
the microprocessor from/to a memory row buffer.
Figure 8 : Long Codes in Memory Triple Row Buffer.

X

0
39
~
r--------,.....D district number

TLMCOMMAND

Rl
R2
RJ
R4
R5
R6
R7

C

B
A
B leven)

101

B +1

IAI

B +2

D,Y
B.X

Y
TLACOMMAND

Rl
R2
RJ
R4
R5
R6
R7

1C 1

C
B
A

D,Y
B,X

E88TS9347-11

14/42

76

Gi
SGS·11I0MSON
~I IlllDI!:II@IiIl.Ii©'ll'IiWIDI!:III

TS9347
Figure 9 : Short Codes in Memory Double Row Buffer.

TSMCOMMAND

Rl
R2
R3

AB-

R4
RS
R6
R7

-

x
p.O_ _ _

W

~.____3-,9 .....- DISTRICT

-

JA"I

D.Y

B (even)

B.X
Y

TSACOMMAND

Rl

A-

R2

s-

R3

W

R4

D.Y

RS

B.X

18·1

B +1

R6

R7
E88TS9347-12

15/42

77

.....

a:>

ca'
"
c

'"l>;

I\)

Cii
0

-n

x'

--------- -----7

Alpha

I I
0

6

5

4

3

2

1

a

X I X I X I X IX I X I X

7

6

5

4

3

H

F

2

I I I NIL I I I ,
0

1

0

c, ,

I- I

X , X I X I X , X , X I X

~

I I lli"a
0

0

~

a

L

p_ 'Il

~(I)

DEL

til 0

~Z

N

m

Don't care
Conceal

N
U

Negative
Undtrlina

F

Flash'

: 111

'Soxingl

X
DE L

Character code
Delimitor

seT

I C, I

j

121

=

L

DOLble width

H
Co

OOl.ble height
Background color
Foreground color

Cl

:::r

I U~
IF~~ !~
F

Go

101 ,C'I
101 ,C', IF~
I N I , c, , I F Ut;:LJ
1

~.

@(I)

".FIIi'

I I

c,

0

graphic

!o
",iii

[ij]

I I
I I

Semi·

~i!

H

F2J:h

Alpha

nm

(J)

A

Semigraphic

~

c.

c

A'

S'

CD

FIXED LONG CODE

FIXED SHORT CODE

I

C,

I I
Ia I
F

!

II

GIO

G'o

,Co,

I j~

Co

'Negative

G'IO

c.
CD

8"
-n

x'

CD

c.
r

0
!

j

5pace

Latched attribute

Inlay:

NOTES

l'

Translation process
The translation process operates throu~h 3 elementary operations:
• Field·to·field: a character code or an attribute value (i.e: CO, flashing) is directly loaded from short to long code.
• Field.to.constant the decoding of a short code forces the value of the equivalent long code attribute. For .xam~ Ie, semigraphic short characters forces normal size
(H = 0, l = 0) attributes.
• latched attributes: at the beginning of each row, these attributes are reset (no underline, not concealed, no insert, black background). Then, they keep their current
va ue until modified by either a field to field or field to constant operation.
2/1 n.ert attribute
12 is interpreted both in G'O and G',O, contrary to long code mode.

I~

g
()
0

::J

co

()
0

c.
CD

-I

iU

::J
(J)

iii
o·
;:>

-I

en
CO
Co)

01=0
.....

TS9347
USER DEFINED CHARACTER GERATOR IN
MEMORY: DOR REGISTER
With 40 char./row, the elementary window dimensions on the screen are 10 slices x 8 pixels. Thus,

a character cell holds 10 bytes in memory and 4 character cells are packed in one 40-byte buffer (Figure 11).

Figure 11 : Packing Uds Cells in Memory.

1
Character set base address
cha,acte:~~ numb.,

~

~

1
~~

0
39
Z block add,." .... F-------'~i
1 KOBN';TE

4 CHARACTER CELLS:

Y

BLOCI<

r------~31
Slice number CO to 9)

1

MEMORY

r

--------------PIXELS

4

!
x

I SN

o

3
I

I

I

I

~
A CHARACTER SET LAYS IN ONE BLOCK

!Up to 100 characters per sell

01234567

o _
2
SN
SLICE
NUMBER
(0 t09)

-_
6

3

432

o

4 5

6

-

-

-

8

--

9

-

SLICES ARE SHIFTEO LSB FIRST
Window on screen

E88TS9347·13

17/42

79

TS9347
For each type of set, it gives the MSB(s) of the Z
block address. TS9347 reads the Z LSB(s) in the B
byte of the (equivalent) long code. As usual, the character code is read in the C byte. SN is derived from
the scan line rank in the row and the double height
status.

The cells of one given character set should be layed
in one block.
Up to 100 character cells may be addressed in each
set.
The location in memory, where to fetch the sets in
use, are declared by DOR register (Figure 12).
Figure 12 : Uds Fetch to Display.

MEMORY

.1.,

,.L

t

~_

• ~

OOR G'O (alpha UDS)

1 Kbyte

I

G'w

2 Kbyte,
G'"

1

654

!
!

_DORG'1 (Semi-graphic
UDS)
Even block

a

3

DOR register

T~

DOR G'O

Page and set MSB

Odd block

65430
CHARACTER
LONG CODE B
BYTE

Go

1

Ql

B Kbyte,

lo
r

l'

l'

Uds Set

Z Address
Z4

Z3

Z2

Z1

ZO

#

87

86

85

G'o

1

a

DOR? DOR3 DOR2 DOR 1 DORa

G'1X

1

a
a

1

DOR? DOR s DOR 5 DOR 4

00 - a?

1

1

X

DOR?

PAGE

1

85

83

DOR? ROR? ROR 5 ROR s

84
84

a

E88TS9347·14

18/42

80

TS9347
LOADING USER DEFINED CHARACTER SET

_ the character number C (0.6)
_ the slice number SN (0.3)
_ the bloc number assigned to the set Z (0.4)

Before loading a character set into RAM, the user
must
• Assign a name to the set:
G'o, G'lO, G'11, or QO-7
• Assign a character number to each character belonging to this set. Character numbers range
from 0 to 3 and 32 to 127.
It is binary coded into 7 bits C (0.6) - C (0.6) will
be loaded later into a C byte character code in
order to display the character.
• A pointer to a character slice in memory is then
manufactured from

Note : Different sets may be mixed in the same
block, as long as the character have different code
numbers.
Figure 13 shows how to proceed with the auxiliary
pointer and the TBM and TBA commands.
Note : The main pointer may be also used. When
sequentielly accessing slices of a given character,
auto incrementation is helpless.

Figure 13: Accessing a Character Slice in Memory using TBA Command.

Rl

Slice

R2

-

R3

-

R4
R5
R6
R7
~

I

Z4 I Z31 Z21 C6 I C5 I C4 I C3 I C21

I I
I -I 1I
Zo I Zl

--

-

-

I

SN
I

Cl I CO

I

I

-

-

-

-

-

-

-

-

-

-

I
I
I

Y
X

~

I I

+

E88TS9347-15

ON-CHIP CHARACTER GENERATOR
• GO and GOE are common to 40 and 80 char./row
modes (Figure 14 and Figure 23).
• G10 is the standard mosa"ic set for videotex (Figure 15).
• GOE cannot be reached from the 16 bit short
codes (Figure 16).

1. For normal operation, a double height and/ordouble width character must be repeated in memory in
two successive Y and/or X positions. The user may
otherwise freely mix any character size.

• Underline or underline cursor: foreground forced
on the last slice (SN = 9).
• Flash : background periodically forced on the
whole window (= 0.5 Hz). The phase depends on
the negative attribute.
• Conceal: background forced permanently on the
whole window. A concealed character neither
blinks nor is underlined.
• Negative : exchange the background and foreground color values when set.
• Coloring.
• Complemented cursor mode.
• Insert: black color forced when required.

2. The attributes are logically processed in the following order:

3. Basic pixel shift frequency : fCLK x 2/3 = 8 to
10 MHz

DISPLAYING THE ATTRIBUTES

19/42

81

TS9347
Figure 14 : Go Alphanumeric Character Set in 40 Character/Row Mode-TS9347.
0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

,

C4

0

1

0

1

0

1

0

1

C3

C2

Cl

CO

o

0

a

a

a

a

a

1

a

a

1

a

a

a

1

1

a

1

a

0

o

1

a

1

a

1

1

a

a

1

1

1

• • • •

1

a

a

a

•••

1

a

a

1

• • • • • • • •

1

a

1

a

••••••••

1

a

1

1

• •

1

1

0

a

••••••

1101

82

C6
C5

1111
1111 •• 1111
111 ••••
.111111 ••••
1111 ••••
1111 •••••
.111111 ••••
•••••

••

• •

. •

B •••
11 ••••

IIIIIIIIIB

B.

ill •• III1 ••

1

1

1

a

••••••••

1

1

1

1

•

II II II II • II •

E88TS~47.'6

TS9347
Figure 15 : Gl0 Semigraphic Character Set.
SEPARATED Semi-graphic

MOSAIC Semi-graphic
C6

1

1

1

1

C5

a
a

a

1

1

1

a

1

C4
C3

C2

Cl

co

a

a

a

a

a

a

a

1

a

a

1

a

a

a

1

1

a

1

a

a

a

1

a

1

a

1

1

a

a

1

1

1

1

a

a

0

1

a

a

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

a
a
a

a

a
a

a
1

1

1

a

1

•...... ._. 1iIi·
.... . • •.
I. ....• ••
~II.I

••••••••
••
••••••••
••••••••
II ••• I.B
I •••••••
••••••••
••••••••
••••••••
I
I ••••••
III ••••••
••••••••
••••••••
••••• 11.
••••••••
III1~a.I
b::±ttiri

.~_

.

E88TS9347-17

83

TS9347
Figure 16 : GOE Extension Character Set.

o

0

I0

o

0

0

o

0

,

o

0

o

1

csJ

0

C4

0

I

I 0 I
I ' J

0

I'
1 0

I' I'
0

I

0

E88TS9347-18

84

TS9347
80 CHAR / ROW CHARACTER CODES
To display pages in 80 character per row format,
one of two character code formats must be selected:
• Long (12 bits) code: 4 parallel attributes

• Short (8 bits) code: no attribute.
Both formats address the on-Chip Go and GOE sets
(154 characters 6 x 10) sets. None allows UDS addressing.

Figure 17 : 80 Char/Row Character Code.
7

6

5

3

4

2

1

0

--------------

!>.

w

I\.)

:0;:

-I

(J)

COMMAND TABLE

co

I\.)

Memo

Type

Parameter

Code

Status

Arguments

5

4

2

1

0

IND

,

6

Indirect

0

0

0

RlW -

r

-

0

40 Characters - 24 Bits

TlM

0

0

0

0

RlW

0

0

40 Characters - 24 Bits

TlA

0

0

,

,

0

0

RIW

0

1

1

X
X

40 Characters - 16 Bits

TSM

0

1

1

0

RlW

0

0

1

X

40 Characters - 16 Bits

TSA

0

1

1

1

RlW

0

0

1

80 Characters -

8 Bits

KRS

0

1

0

0

RlW

0

0

1

X
X

80 Characters - 12 Bits

KRl

0

1

0

1

RIW

0

0

0

X

Byte

TBM

0

0

RIW

0

0

1

TBA

0

0

,

1

Byte

1

RIW

1

1

~

Move Buffer

MVB

1

1

0

1

s

-s

0
a

a

0

0

Move Double Buffer

MVD

1

1

1

0

s

s

a

0

0

Move Triple Buffer

MVT

1

1

1

1

s

S-

a

a
a

0

0

0

~UI
@.

Clear Page (4) - 24 Bits

Cll

0

0

0

0

0

1

0

1

X

X
X

0
0

7

fil~

1

3

AI LX m LX. R1 R2 R3 R4 RS R6 R7
0

D

X

0

C

- - - B A -

0

X

C

B

X

0

A'

B'

0

X A' B'
0

C

0

C

X

X
X
X

0

D

X

0

X

D

- - - AP
- - - - A - - - - - - AP

0

W

-

-

0

W
W

- - -

C

B

A

A'

B'

-

~;!

Clear Page (4) - 16 Bits

ClS

0

1

1

0

0

1

0

1

X

i~O
!!J1

Vertical Sync Mask Set

VSM

1

0

0

1

1

0

0

1

0

Vertical Sync Mask Reset

VRM

1

0

0

1

0

1

0

1

0

Increment Y

INY

1

0

1

1

0

0

0

0

0

No Operation

NOP

1

0

0

1

0

0

0

1

-

~O

~Z

s, s
a,a

: Source, Destination
01 : Source = MP ; Destination = AP
10 : Source =AP : Destination = MP
: Stop Condition
01 : Stop at End of Buffer
10: No Stop
: Indirect Register Number

W

X
I
D
MP
AP

Not Affected
Used as Working Register
Set or Reset Buffer
Pointer Incrementation
Data
Main Pointer
Auxil iary Pointer

A

- - 0
0
- - 0
0
- - - - - - 0

0

(1)
(2)
(3)

Write

Read

2

3.5

4

7.5

-

4

7.5

MP

3

5.5

-

3

5.5

MP

9

9.5

MP

12.5

11.5

MP

4

4.5

-

4

4.5

AP

MP

(2) 2 + 4.n

AP

MP

(2) 2 + 8.n

-

AP

-

MP
MP

AP

W
.Ilo

Execution Time (1 )

MP

- MP
- MP
- - - - - Y - - -

(2) 2 + 12.n
< 4700 (1 K code)
< 3500 (1 K code)

1
1
2
1

~

Unit: 12 clock periods (= 1 I1s) without possible suspension.
n: Total Number of Words S 40
These commands repeat TlM or KRO with Y incrementation
When X overflows. When the last position is reached in a row
Y is incremented and the progress starts again on the next
row these command stop only. They can also be used to
initialize the page 80 char/row by writing character pairs

.....

-

TS9347
ABSOLUTE MAXIMUM RATINGS
Symbol

.

Value

Unit

Vcc'

Supply Voltage

Parameter

0.3 to 7.0

V

Vin'

Input Voltage

0.3 to 7.0

V

TA

Operating Temperature Range

a to 70

°C

T s1g

Storage Temperature Range

- 55 to 150

°C

PO m

Max Power Dissipation

0.75

W

With respect to Vss.

Stresses above those hereby listed may cause permanent damage to the device. The ratings are
stress ones only and functional operation of the device at these or any conditions beyond those indicated in the operations (sections of this specification

is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Standard MOS circuits handling procedure
should be used to avoid possible damage to the device.

ELECTRICAL OPERATING CHARACTERISTICS Vee = 5.0 V ± 5 %, Vss = 0, Tamb = 0 to 70 'C
(unless otherwise specified)
Symbol

Parameter

Min.

Typ.

Max.

Unit

Vcc

Supply Voltage

4.75

5

5.25

V

V,L

Input low Voltage

- 0.3

-

0.8

V

V,H

Input High Voltage ClK (external ClK)
Other Inputs

Vee
Vee

V

10

IlA
V

0.4

V

500

mW

15

pF

-

10

-

1

IlA
ms

lin

2.2
2

-

Input leakage Current

VO H

Output High Voltage (I'oad = 500 1lA)

VOL

Output low Voltage I'oad = 4 mA : AD (0:7), ADM (0:7)
I'oad = 1 mA : Other Outputs Except Y

Po

Power Dissipation

Cin

I nput Capacitance

ITSI

Three State (off state) Input Current

tstart

-

2.4

350

-

Crystal Oscillator Start Time

ON CHIP OSCILLATOR

TYPICAL CRYSTAL PARAMETERS
• Parallel resonance fundamental mode AT CUT
f = 12 to 15 MHz
rs = 30 Q
Cs = O,001pF

c,
~ ....- - -...- - - - 0

eLK

CL:S;

7pF

Ct = C2 = 30 pF

•
XTAL

E88TS9347·30

E88TS9347-31

33/42

95

TS9347
MEMORY INTERFACE
Vee = 5.0 V ± 5 % Tamb = 0° to + 70 'C
Clock: Duty Cycle 40 to 60 % ; t r , t f < 5 ns V 1H = 2.2 V
Reference Levels: V 1L = 0.8 V and V1H = 2 V, VOL = 0.4 V and V OH
Ident.
Number

Symbol

= 2.4 V

Fin =12MHz

Parameter

Min.

Memory Cycle Time

Max.

F = 1fT
Min.

Max.
6T

500

Unit
ns

1

tELEL

2

to

3

tEHEL

ASM High Pulse Width

4

tELOV

Memory Access Time from ASM low

250

4 T - 43

ns

5

tOA

Output Delay Time from elK Rising
Edge ADM (0, 7), AM (8,14)

80

80

ns

6

tAVEL

Address Setup Time to ASM

30

T - 49

7

tELAX

Address Hold Time from ASM

55

T - 21

8

tCLAZ

Address off Time

9

tGHOX

Memory Hold Time

10

toz

11

Output...QgLay Tim~om ClK Rising
Edge (ASM ; OE, WE)

60

60
2 T - 33

120

80

ns

ns
-

ns

80

ns

10

10

ns

ns

Data off Time from OE

60

T - 19

ns

tGLDV

Memory OE Access Time

150

2 T - 16

ns

12

tOVWL

Data Setup Time (write cycle)

30

T - 49

ns

13

tWHOX

Data Hold Time (write cycle)

30

T - 49

ns

14

tWLWH

WE Pulse Width

110

2 T - 48

ns

TEST LOAD
ADM (0.7)
AD (0.7)

Test
point
MMD7000

or equlv.

E88TS9347 -32

34142

96

Other
Outputs Except Y

C

100 pF

50 pF

RL

1 kQ

3.3 kQ

R

4.7 kQ

4.7 kQ

TS9347
MEMORY INTERFACE TIMING DIAGRAM

T

elK

DOUT

ADMIO:71
AM18:141

DE

------------~

I

LCD

WE _ _ _ _ _ _ _ _ _ _ _ _ _ _-=®~2i---j~' I

0TI I
1

~'---.----';I
I

I~®

.

F,

®

I

E88TS9347-33

35/42

97

TS9347
MICROPROCESSOR INTERFACE
TS9347 is MOTEL compatible. It automatically selects the processor type by using AS input to latch
to state of the OS input.

6801

INTEL Family

Timing 1

Timing 2

AS
OS, E",. 2
R/W

ALE
RO
WR

TS9347
AS

No external logic is needed to adapt bus control signals from most of the common multiplexed bus
microprocessors.

O~

RIW

.c

MICROPROCESSOR INTERFACE TIMING AD (0:7), AS, OS, RiW, CS
Vcc = 5.0 ± 5 %, TA = 0° to 70°C, C L = 100 pF on AD (0 : 7)
Reference Levels: V 1L
Ident.
Number

Symbol

Inputs; VOL

Parameter

Min.

tCYC

Cycle Time

tASD

DS Low to ASJ::iigh (timing 1)
DS High or RIW High 10 AS High (timing 2)

3

tASED

AS Low to DS High (timi!}g 1)
AS low to DS LOw or RIW Low (timing 2)

30
200
93
100
10
20
20
100
10

4

tPWEH

Write Pulse Width

5
6

tPWASH

AS Pulse Width

tRWS

RIW to DS Setup Time (timing 1)

7

tRWH

RIW to OS Hold Time (timing 1)

8

tASL

Address and CS Setup Time

9
10
11
12
13

tAHL

Address and CS Hold Time

tosw

Data Setup Time (write cycle)

tOHW

Data Hold Time (write cycle)

tOOR

Data Access Time from DS (read cycle)

tOHR

DS Inactive to high Impedance State Time
(read cycle)

tACC

Address to Data Valid Access Time

36142

= 0.4 V and V OH = 2.4 Von All

1
2

14

98

= 0.8 V and V 1H = 2 V on All

Typ.

400
26

10

Max.

Outputs.
Unit
ns

-

ns

-

-

ns

-

-

ns
ns
ns
ns
ns
ns
ns

-

-

ns

-

150
63

ns

300

ns

-

ns

TS9347
MICROPROCESSOR INTERFACE TIMING DIAGRAM 1 (6801)

DS

AS

R/W

WRITE CYCLE
AD 1 0 : 7 ) - - - - - - - - - - <

INPUT DATA

@

READ CYCLE
AD ( 0 : 7 ) - - - - - - - - - <

DUTPUT
DATA

1"----->1"

®

E88TS9347 -34

MICROPROCESSOR INTERFACE TIMING DIAGRAM 2 (INTEL type)
READ CYCLE

READ CYCLE

AO(O:7)--------------{

'ACC

E88TS9347 -35

~

SGS·nlOMSON

37/42

~"I fl:jJn©Ii\I@~~~IiI@llln©@
99

T59347
WRITE CYCLE

ADIO:1)

--------------<

E88TS9347-36

VIDEO INTERFACE R.G.B.I.
Vee 5.0 V ± 5 % Tamb 0 0 to + 70 'C ClK Duty Cycle 50 %. C l 50 pF
Reference levels: Vil = 0.8 V and V 1H = 2.2 Von ClK Input VOL - 0.4 V and VOH

-

2.4 V All Outputs

Parameter
Output Delay from elK Edge

eLK

~
to

R.G.B,I,

40 char/row

to

0:

X

to

X

R,G,B,I.

80 char/row

to

X

to
HVS

38142

100

><

E88TS9347 -37

TS9347
INPUT ClK (case of external ClK generation)

tpWCH

elK
Reference level VIL = 0.8

v,

VIH

= 2.2 V
E88TS9347 -37

INPUT ClK (case of internal oscillator - fin

=

12M Hz)

tWCOH

~

L
~c0f--

CLKOUT

tleo

L

I

tWCOL

J

Refmence level VOL:;:- 0.4 V, VOH ':;: 2.4 V

E88TS9347-37/1

Symbol

Parameter

Min.

tPWCH

ClK High Pulse Width

25

tpWCl

ClK low Pulse Width

25

tre, tfc

ClK Rise and Fall Time

tWCOH

ClKOUT High Pulse Width

20

tWCOl

ClKOUT low Pulse Width

20

t reo ,

Unit
ns
ns

10

ClKOUT Rise and Fall Time

tfco

Max.

ns
ns
ns

20

ns

Y OUTPUT: Composite luminance.
REFERENCE lEVEL
Vooc

= Voo = 5 V; Vssc = Vss = 0 V

G

R

B

Signal

0
0
0
0
0
1
1
1
1

0
0
0
1
1
0
0
1
1

0
0
1
0
1
0
1
0
1

SYNC
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YEllOW
WHITE

level
0.06
0.50
0.80
0.92
1.03
1.15
1.26
1.38
1.50

V
V
V
V
V
V
V
V
V

39/42

101

TS9347
ELECTRICAL SPECIFICATION
Over Full Temperature Range: V DDC = V DD = 5 V (see note 1)
Vssc = Vss = OV; C L = 20 pF, RL > 100 Kto Vss or Voo
Parameter

Min.

Typ.

Max.

Monotonicity

Guaranteed

Output Level Dispersion

10

Unit

50

mV

Propagation Delay (clock edge to 50 % output)

60

ns

Rise and Fall Time (10 - 90 %)

30

ns

Output Static Impedance

600

Q

Note: 1.The DAC is a 9 output potentiometric divider: therefore, each voltage variation on Vooc is repercuted on the output with the same
relative value with respect to Vssc.

TYPICAL APPLICATION

TEST CONDITION

+5V

Y 0--.------,
CL

68 !2

= '10 ,,1-

HL=1001<..U
TS9347

vQ--+-I
vss

(VSSC)

E88TS9347-38

40/42

102

E88TS9347 -39

<

m

=I

(';
l>

r-

l>
Z

168T

HORIZONTAL SYNCHRO

C
::J:

54T

o

HVS __________________~

___;_~ye~f~~l!!.~I~J

XI

N

o

~

J84T

Bulk

R,G,a,1

40 char Jrow
80 char .trow

r-

en
-<
z
o

H blanking

480T
480T

::J:
XI

~

o
Z

y

!!:CII

I~

~

VERTICAL SVNCHRO
NQNINTERLACED

~:i!

Ii

oz

312 lines

g

HVS, Y

-I
"tJ

~IS

c:

!2z
I

INTERLACED

Evenfl'1lJlle

~
I

HVS,Y

-I

~I-

----------------------------------~

Qddframe

VS
(IN STATUS)

ul

~

312.51i~

J

m

00

00
....

......
0
W

.j>.

I~

ffl
w
:!:l

...

0

-I

(J)

ID
to)

~
.....

TS9347
PACKAGE MECHANICAL DATA
40 PINS - PLASTIC DIP
mm

15.24
(2)

..

(1)

Nominal dimension

(2)

True geomet!"ical pO"iition

Or

20

53

I

max.

40

pms

44 PINS - PLASTIC LEADED CHIP-CARRIER

16 10
16,662

~
17,65
0661
0.812

--M.L
min.

42142

104

0331
0.533

Gi
SGS·THOMSON
~I Ii1Aln©[ffi@~~rn©'U'[ffi@llIn©®

44 Outputs

GRAPHICS CONTROLLERS

105

EF9365
EF9366
MOS GRAPHIC DISPLAY PROCESSOR (GDP)
• SELECTABLE RESOLUTIONS IN BLACK AND
WH ITE OR COLOR:
EF9365: 512 x 512 (interlaced scan)
256 x 256,128 x 128, 64 x 64 (non
interlaced scan)
EF9366 : 512 x 256 (non interlaced scan)
• HIGH SPEED VECTOR PLOT WELL SUITED
TO ANIMATION (up to 1 500000 dots/so and an
average value of 900 000 dots/s.) 4 TYPES OF
LINES.
• MULTIPLEXED ADDRESS AND REFRESH
FOR 16 K OR 64 K DYNAMIC RAMs
• NO LIMITATION ON THE NUMBER OF SELECTABLE MEMORY PLANES (colors, grey levels
or any other attributes)
• MULTIPAGE APPLICATION CAPABILITY
• ON-CHIP FULL ASCII CHARACTER GENERATOR (96)
MAXIMUM ALPHANUMERIC
SCREEN DENSITY: 85 x 57 - PROGRAMMABLE SIZES AND ORIENTATIONS
• DIRECT INTERFACING WITH THE MONITOR
THROUGH THE COMPOSITE SYNCHRO AND
BLANKING SIGNALS
• AUTOMATIC ALLOCATION OF DISPLAY MEMORY IN REFRESH, WRITE, DUMP, AND DISPLAY CYCLES
• LIGHT PEN REGISTERS AND CONTROL SIGNALS
• THREE TYPES OF INTERRUPT REQUESTS
• FULLY STATIC DESIGN
• TTL COMPATIBLE I/O
• SINGLE + 5 VOLT SUPPLY.

DESCRIPTION
The GOP is a true high resolution graphic display
processor, which contains all the functions required
to process vector generation at a very high speed
and to generate all the timing signals required for interfacing interlaced or non interlaced video data on
a raster scan CRT display compatible with the CCIR
625 line 50 Hz standard.
The GOP flexibility results from its direct interfaCing
with any 8 bit MPU bus and its 11 internal registers.
December 1988

P
DIP 40
(Plastic Package)

ORDER CODE: EF9365P
EF9366P

PIN CONNECTIONS

vee

CK

OAD5
OA04
OA03
OAD6
MSLO
MSL2
FMAT
AO
A1
A2

A3
IRO

ow

DIN

VB
E

RtW
MFREE

vss

DAD1
DAD2
DADO
MSLl
MSL3

SYNC
R

DO
01
02
03
04
05
06

07
BLK
WHITE
WO
ALL
LPCK

E88 EF9365-01

1/29

107

EF9365·EF9366
TYPICAL APPLICATION

ADDRESS BUS IA.81. _ _ _- - - - DATA BUS

4

10.81

8

,
I

I

I

I

J

i

----h,
L----'=::;:~;¥=FF", ,.; . . . nL - - - -..
~~~L-~~

,

I

I
I

I
I
I

I
----I,
VIDEO I
Composite

_!:'!
G>
::c

"
BLOCK DIAGRAM

»
s:

!Tvl
MSLO
to
MSL3

~

Address
DO to 07

controller
and
buffers

DADO

~~

~'"

@.

[ei!
~o

iiill:

<,,'"
~O

~z

..

E
RIW
AOto A3

Decoding
ALL

m

'"'"m
'"'"
'"
8'"
"T1

VB

and
control

rr'"

m

"T1
<0
W
0'1

If

m
"T1

<0

o

CD

W
0'1
0'1

EF9365-EF9366
GENERAL DESCRIPTION
Developed using NMOS technology, the GDP is an
intelligent raster scan video display controller, fully
programmable via an eight-bit microprocessor bus.
Besides all the timing logic functions required to generate the video, sync and blanking signals, the
GDP includes two hardwired display processors: a
vector and a character generator.

Nevertheless, where direct exchange between the
microprocessor and the memory is necessary, the
on-chip allocation controller will allow this exchange
without display interference.
The GDP is programmable using 11 intemal registers occupying 16 consecutive addresses. These
registers can also be modified by the GDP's hardwired processors while a command is being executed.

This unique feature allows an ultrafast screen writing speed (the 512 dot diagonal may be written in
less than 700 ~) at almost no microprocessor processing cost.

Note: A summary of data codes and registers is given in the Register address table. Hexadecimal values are subscripted 16 and the register bits are
numbered as follows:

The GDP is particularly well-suited to all applications
in which the display memory is not directly addressed by the MPU. This feature allows a total asynchronism between the MPU and the GDP memory
cycles and preserves the whole MPU memory addressing space.

ABSOLUTE MAXIMUM RATINGS
Symbol

Value

Unit

Vee

Supply Voltage

- 0.3 to + 7.0

V

Vin

Input Voltage

- 0.3 to + 7.0

V

TA

Operating Temperature

o to + 70

cC

- 55 to + 150

cC

T stg

Parameter

Storage Temperature

The GDP inputs are protected against high static voltages and electric fields; nevertheless, normal precautions should be
taken to avoid voltages above the limit values on this high impedance circuit.

STATIC ELECTRICAL PARAMETERS 01ee

=

5 V ± 5 %, Vss = 0, TA = 0 to 70 'C unless otherwise

noted)
Symbol

Parameter

Min.

Typ.

Max.

Unit

Input Hgih Voltage Except CK

Vss + 2.2

Vec

V

Input High Voltage CK

Vss + 3.5

Vcc

V

VIL

Input Low Voltage

Vss - 0.3

lin

Input Leakage Current (V in = 0 to 5.25 V, Vcc = max)

VIH
VIHCK

V OH

Output High Voltage (iload = - 100 ~A, Vce = min)

VOL

Output Low Voltage (iload = 1.6 mA, Vec = min)

Ice

Supply Current t

Cin

Capacitance (V in = 0, T A = + 25 cC, f = 1.0 MHz)

C out

4/29

110

Vss + 0.8

V

1.0

2.5

f,lA

-

Vss + 0.4

V

Vss + 2.4
80

V
mA

12

pF

12

pF

EF9365-EF93titi

DYNAMIC OPERATING CONDITIONS (VDD = 5.0 V ± 5 % ; TA = 0 to + 70 "C unless otherwise
noted)
Symbol

Time (n5)

Min.

Max.

tCK

Clock Period

560

tCLK

CK Pulse Width, Low

330

tCKH

CK Pulse Width, High

190

CKLDAD

CK Low to Valid DAD

CKHDAD

CK High to Valid DAD

180

CKLSYNC

CK Low to Valid SYNC

300

CKLBLK

CK Low to Valid BLK

310

CKLVB

CK Low to Valid VB

500

CKLALL

CK Low to Valid ALL

300

CKLMSL

CK Low to Valid MSL

300

CKLDW

CK Low to Valid OW

310

CKLMFR

CK Low to Valid MFREE

500

CKLDIN

CK Low to Valid DIN

310

CKLlRQ

CK Low to Valid IRQ

1500

CKLWHI

CK Low to Valid WHITE

tEL

320

530

E Pulse Width, Low

450

tEH

E Pulse Width, High

430

tAS

Address Pre-Setup Time

160

tAH

Address Hold Time

tDSW

Data Pre-Setup Time (write)

tDDR

Data Setup Time (read)

tDHR

Data Hold Time (read)

tlR
LPHW

10
260
320
10

IRQ Release Time

1600

LPCK High to WHITE High (if command 0816)

1600

LPHIRQ

LPCK High to IRQ Low

tPCKH

LPCK High Hold Time

t,

CK and E Rise Times

20

tf

CK and E Fall Times

20

1600
150

5/29

111

EF9365-EF9366
CLOCK AND OUTPUT CHARACTERISTICS

,
CK 3.5V

CK 3.5V 1
2.2V ~_ _ _~

~2V

CK

I ~0.8 V
I I

E

0.8

4-+-

VA
I

I

\

L -_ __

+t-o

If

Outputs

\'-----EBB EF9365·05

IRQ RELEASE TIME

2.211
E

I

I

tlR

I·~·~----~·~~-------------

J24V
I

I
IRQ

------------------~I--------~

EBB EF9365·06

MICROPROCESSOR BUS, WRITE ACCES
tEL

___________

~

i••- - -'EH
- - - - -__

. I
I

~

I

AO ... A3

~

tAH
I

R/W

K

'05W

00 ... 07

EBB EF9365·07

6/29

112

EF9365-EF9366
MICROPROCESSOR BUS, READ ACCESS

tEL

AO. A3

R/W
tOOR

DO ... D7

E88 EF9365-08

SYNCHRONOUS SIGNALS WITH CK INPUT
'eK
eK

DAD
SYNC
BLK
VB

ALL
MSL

OW
MFREE
~
IRO
WHITE

E88 EF9365-09

LIGHT PEN SIGNALS

tLPCKH

LPCK

WHITE
IRQ

--f

lPHW

I

\'-----

I~_ ~"'"O ~'-

I

_____________
E88 EF9365-1 0

7/29

113

EF9365-EF9366
PIN DESCRIPTION
Power supplies

Vee

Display memory
controL

I

~ -----j

DO, .07

MF'REE __- - - j
AO, .A3
M.croprocessor

bu,
R/W

MSLO

to MSL3

EF9365

Display memory

addreSliing

____ E

iRa

EF9366

DADO
to
OAD6

AIL
~LPCK

Synchromzing

SYNC

"d
blanking

Light pen
control

BLK
VB

JJL

E88 EF9365-11

Clock Operating parameters

• FMAT should be connected to Vee in the EF9366.

POWER SUPPl V, CLOCK AND OPERATING PARAMETERS
Name

Pin
Type

N°

Function

Description

Vss

S

20

Power Supply

Ground

Vee

S

40

Power Supply

+5V

CK

I

1

Clock

Master Clock. All internal processor states are modified on the falling
edge of this signal. The whole circuit logic is static and the cycle of
this clock needs only to be ajusted according to the shape and
accuracy the synchronizing signals should feature.
DAD Memory Address Multiplexing Signal. If CK is low, low
addresses (or row addresses for the memory) are those that are
output on DAD. For SYNC to be in compliance with the applicable
CCIR standards (FMA T high) the input frequency on CK should be
1.750 MHz.
If FMAT is low or for the EF9366, the frame frequency equals 50 Hz
provided that the input frequency on CK is 1.7472 MHz.

FMAT

I

8

Format

EF9365 should be connected to Vcc for a 512 line vertical resolution
(interlaced scan) and to Vss for 256 lines or less (non-interlaced
scan). The shape of the synchronizing signals, the address
distribution on DAD and the MSL output functions are changed by
this input.

WO

I

23

Write Only

When WO is high, memory refresh nor display no longer exist. The
hard wired write proccessors may operate without being interrupted.
The ALL signals is always high.

EF9366 : not used (should be connected to Vcc).

8/29

114

EF9365-EF9366
SYNCHRONIZING AND BLANKING SIGNALS
Sync

0

34

Video Monitor
Synchronizing

BLK

0

25

Blanking

VB

0

16

Video Monitor Line and Frame Sync Signal.
The SYNC signal complies with CCIR 625-line 50 Hz standard
provided the CK frequency is 1.750 MHz and FMAT is high.
If FMAT is low or for the EF9366, the frames are no longer
interlaced and all comprise 312 lines. This output is not affected by
the WO input and CTRL 1 register.
This signal is high apart the display window (writing or refresh). It is
always high if bit 2 in register CTRL 1 is high, but it is not affected by
the WO input.

Vertical Blanking This signal is not affected by WO and register CTRL 1. High during
vertical blanking.

DISPLAY MEMORY ADDRESSING SIGNALS
DADO
to
DAD6

0

MSLO
to
MSL3

0

ALL

0

37,39, Display Address
38, 4
3, 2, 5
6, 36

Addresses that are multiplexed by the CK signal. Provided for the
Automatic Refresh of the 16 K or 64 K Dynamic Memories.

Memory Select

Pixel write select signals
(see section: display memory configuration).

Access to all
Memory Units

This signal makes it possible to discriminate between the collective
memory accesses to all chips (display, refresh or erease), and the
memory accesses to a single pixel for a vector or character writing
purposes. This signal is low for collective access.

7, 35
22

DISPLAY MEMORY CONTROL SIGNALS
DIN

0

15

Display In

DW

0

14

Display Write

Display memory write signal.
Active when Low

MFREE

0

19

Memory Free

Signal low during the next memory idle period following the OF 16
command.
This signal allows exchanges between the microprocessor and the X
and the Y flagged memory segment without affecting the display.

Selection of the memory data code corresponding to the display
screen in the 'off' condition (active when high). For a
black-and-white display (1 bit per pixel), DIN may directly be the
storage entry data.

MICROPROCESSOR BUS SIGNALS
DO-D7

I/O

33
to
26

Data Bus

AO/A3

I

9
to
12

Address Bus

RIW

I

18

Read/Write
Signal

E

I

17

Enable

IRQ

0

13

Interrupt
Request

I/O buffers..Qpening is controlled through E, and the related direction
through R/W.
Address of the register involved in microprocessor access.

Read/Write Signal. Write when Low.
Bus exchange synchronizing and enabling signal.
Interrupt request towards the microprocessor, programmable through
register CTRL 1. Open Drain Output

9/29

115

EF9365·EF9366
LIGHT PEN OPERATING SIGNALS
WHITE

0

24

LPCK

I

21

Forcing to White Forces white level on video signal, for use of the light pen.
Level
Active when Low.
Light Pen
Strobe

Light Pen Input. When the mechanism is set, a rising edge loads into
registers XLP and YLP the current display address and sets the XLP
register's LSB high.

REGISTER DESCRIPTION
X AND Y REGISTERS (Addresses: 816, 916, A16,
B16)
The X and Y registers are 12-bit read-write registers. They indicate the position of the next dot to be
written into the display memory. They have no
connection at all with the video signal generating
scan, but they point the write address, in the same
way as the pen address on a plotter.
These 2 registers are incremented or decremented,
prior to each write operation into the display memory, by the internal vector and character generators,
or they may be directly positioned by the microprocessor.
This 2 x 12 bit write address covers a 4096 x 4096
point addressing space. Only the LSBs are used
here, since the maximum definition of the picture actually stored is 512 x 512 pixels (picture elements).
The MSBs are either ignored or used to inhibit writing where the actual screen is regarded as being a
window within a 4096 x 4096 space.
The above features along with the relative mode
description of all picture component elements make
it possible to automatically solve the great majority
of edge cut-off problems.
DELTAX AND DELTAY REGISTERS (Addresses : 516,716).
The DELTAX and DELTAY registers are 8-bit readwrite registers. They indicate to the vector generator
the projections of the next vector to be plotted, on
the X and Yaxes respectively. Such values are unsigned integers. The plotting of a vector is initiated
by a write operation in the command register (CMD).
CSIZE REGISTER (Address: 316)
The CSIZE register is an 8-bit read-write register. It
indicates the scaling factors of X and Y registers for
the symbols and characters. 98 characters are generated from a 5 x 8 pixel matrix defined by an internal ROM. In the standard version, it contains the
alphanumeric characters in the ASCII code which
may be printed, together with a number of special
symbols.

10/29

116

MSB

P

Q

LSB

Each symbol can be increased by a factor P(X) or
Q(Y). These factors are independent integers which
may each vary from 1 to 16 and which are defined
by the CSIZE register. The symbol generation sequence is started after writing the ASCII code of the
symbol to be represented in the CMD register.
CTRL 1 REGISTER (Address: 116).
The CTRL1 register is a 7-bit read-write register,
through which the general circuit operation may be
fed with the required parameters.
Bit 0 : When low, this bit inhibits writing in display
memory (equivalent to pen or eraser up).
When high, this bit enables writing in display
memory (pen or eraser down).
This bit controls the OW output.
Bit 1 : When low, this bit selects the eraser.
When high, this bit selects the pen.
This bit controls the DIN output.
Bit 2 : When low, this bit selects normal writing mode
(writing apart from the display and refresh periods, which are a requirement for the dynamic storages) in display memory.
When high, this bit selects the high speed writing mode: the display periods are deleted.
Only the dynamic storage refresh periods are
retained.
Bit 3 : When low, this bit indicates that the 4096 x
4096 space is being used (the 12 X and Y bits
are significant).
When high, this bit selects the cyclic screen
operating mode.
Bit 4 : When low, this bit inhibits the interrupt triggered by the light pen sequence completion.
When high, this bit enables the interrupt.
Bit 5 : When low, this bit inhibits the interrupt release
by vertical blanking.
When high, this bit enables the interrupt.

EF9365-EF9366
Bit 6 : When low, this bit inhibits the interrupt indicating that the system is ready for a new command.
When high, this bit enables the interrupt.
Bit 7 : Not used. Always low in read mode.
CTRL2 REGISTER (Address: 216)
The CTRL2 register is a 4-bit read/write register,
through which the plotting of vectors and characters
may be denoted by parameters.
Bit 0, 1 : These 2 bits define 4 types of lines (continuous, dotted, dashed, dash-dotted).
Bit 2 : When low, this bit defines straight writing.
When high, it defines tilted characters.
Bit 3 : When low, this bit defines writing along an horizontal line.
When high, this bit defines writing along a vertical line.

When high, this bit indicates that the circuit is
ready for a new command.
Bit 3 : When low, this bit indicates that the X and Y
registers point within the display window.
When high, this bit indicates that the X and Y
registers are pointing outside the memory display.
This bit is the logic OR of the unused MSBs
of the X and Y registers.
Bit 4 : When high, this bit indicates that an interrupt
has been initiated by the completion of a light
pen running sequence. Such an interrupt is
enabled by bit 4 in CTRL 1 register.
Bit 5 : When high, this bit indicates that an interrupt
has been initiated by vertical blanking. Such
an interrupt is enabled by bit 5 in CTRL 1 register.

CMD COMMAND REGISTER (Address: 016)

Bit 6 : When high, this bit indicates that an interrupt
has been initiated by the completion of execution of a command. Such an interrupt is enabled by bit 6 in CTRL1 register.

The CMD register is an 8-bit write-only register.
Each write operation in this register causes a command to be executed, upon completion of the time
necessary for synchronizing the microprocessor access and the GDP's CK clock.

Bit 7 : When high, this bit indicates that an interrupt
has been initiated. It is the logic OR of bits 4,
5 and 6 in STATUS register. The IRQ output
state is always the opposite of the status of
this bit.

Several types of command are available:
_ vector plotting
character plotting
screen erase
light pen circuitry setting
access to the display memory through an external circuitry.
indirect modification of the other registers (commands that make it possible for the X, Y, DELTAX, DELTAY, CTRL 1, CTRL2 and CSIZE registers to be amended or scratched).

Note: Bits 4, 5, 6 and 7 are reset low by a read
of the STATUS register.

Bit 4, 5, 6, 7 : Not used. Always low in read mode.

STATUS REGISTER (Address 016)
The STATUS register is an 8-bit read-only register.
It is used to monitor the status of the executing statements entered into the circuit, and more specifically to avoid the need for modifying a register that
is already used for the command currently executing.
Bit 0 : When low, this bit indicates that a light pen sequence is currently executing.
When high, it indicates that no light pen sequence is currently executing.
Bit 1 : This bit is high during vertical blanking. It is
the VB signal recopy.
Bit 2 : When low, this bit indicates that a command
is currently executing.

XLP AND YLP REGISTERS (Addresses C16 and
D16)
The XLP and YLP registers are read-only registers,
with 7 and 8 bits respectively. Upon completion of a
light pen running sequence, they contain the display
address sampled by the first edge appearing rising
on the LPCK input. The use of such registers is discussed in section: Use of light pen circuitry.

Notes : 1. All internal registers may be read or
written at any time by the microprocessor. However, the precautions outlined
below should be observed:
_ Do not write into the CMD register if
execution of the previous command
is not completed (bit 2 of STATUS
register).
_ Do not alter any register if it is used
as an input parameter for the internal hardwired systems (e. g. : modifying the DEL TAX register while a
vector plotting sequence is in progress).
_ Do not read a register that is being
asynchronously modified by the internal hardwired systems (e. g. : rea11/29

117

E F9365-E F9366
ding the X register while a vector
plotting sequence is in progress may
be erroneous if CK and E are asynchronous).

command for the first time, it is necessary to wait until all functions cu rrently
underway are completed, which information can be derived from the STATUS register.

Note: 2. On powering up, the writing devices
may have any status. Before entering a

SYSTEM OPERATING PRINCIPLE
DISPLAY MEMORY CONFIGURATION
Assume a V x H pixel picture. Assume that each
pixel is able to adopt 2b different states. A V x H x b
bit display memory is thus required.

b planes

In those applications where H features a high value,
the video signal frequency exceeds the maximum
frequency of memory read access.

1 pixel
denoted by

Example: H = 512 with a television line frequency:
the pixel succession period on the video signal is 70
ns.

v

b bits
X

X

It is mandatory that a line of H dots be cut into h adjoining segments of n bits each, read at the same
time in the display memory, and thereafter converted to serial form to produce the video signal. h memory accesses per line are necessary. Each access
loads b n-bit shift registers. The memory contains V
x h x b n-bit words.

,.

(

X
bbits

..

H

E88 EF9365·12

b memory planes

1 through
V x h address
1 memory plane =

GOP

V x h "-bit words

--

Video signal
on b bits

Dot
frequency

clock

b n·bit
shift registers
E88 EF9365·13

12/29

118

EF9365-EF9366
EF9365
The EF9365 circuit is designed to accomodate the
following picture formats:
_ 1.V=H=5120ralowerof2
_ 2. h = 64
_ 3. n = 8, 4, 2 or 1
_ 4. Any value for b (the addressing is similar for all
memory planes. These planes are managed outside the actual ci rcuit).
Circuit operation in the various formats outlined
above occurs as described below:

=

=

=

512 x 512 pixel format (V 512, h 64, n 8).
The FMAT input should be high. The memory is
made up of V x h bytes = 32 K bytes per memory
plane.
The byte address is made up of 15 bits:
_ 14 are output in 2 runs on the DAD pins for the
purpose of using 16 K x 1 bit dynamic RAMs,
_ the 15th one is output on pin MSL3.
The 3 MSLO, 1 and 2 outputs allow to select one
pixel out of the 8 featuring the same address, for
pixel-to-pixel write applications. They issue the
number of the involved pixel, encoded on 3 bits.

=

=

SIGNALS OUTPUT THROUGH THE DAD AND
MSL PINS
The internal counters which address the display memory are made up of :
_ 6 horizontal address bits (h = 64)
ho, h1, h2, h3, h4, h5
_ 9 vertical address bits (V S; 512)
t, Va, V1, V2, V3, V4, V5, V6, V7
t is here the LSB. It denotes the line parity and
changes every frame because of interlaced scan.
Within a same frame, Va denotes the LSB.
The write address is made up of the 9 LSBs of the
X and Y internal registers.
Xo, X1, X2, X3, X4, X5, X6, X7, Xs
Yo, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Ys
The display address and write address are crossreferenced as follows:
EF9365
FMAT = 1

=

256 x 256 pixel format (V 256, h 64, n 4).
The FMAT input should be low. The memory is
made up of V x h x n bits, i. e. 16 K 4-bit words. The
address of a 4-bit word is made up of 14 bits, which
are output in 2 runs on the DAD pins.
Each of the 4 MSL pins is used to select one pixel
in a 4-bit word for writing purposes. The 2 LSBs in
the horizontal writing address are decoded before
being output on the MSL pins. Such outputs are active when low.

°

FMAT =

EF9366

Format less than 256 x 256 pixels (V = 128 or 64,
64, n 2 or 1).
Such formats are achieved in the same way as for
the 256 x 256 pixel format discussed above. Unrequired address bits are output on DAD?

DAD AND MSL OUTPUT STATUS TABLES

EF9366

EF9365

h

=

=

The EF9366 circuit is designed to accomodate a
(512 x 256) picture format: V 256, H 512, h
64, n = 8, b = any value.

=

=

=

The memory is made up of 16 K bytes per memory
plane. The byte address is made up of 14 bits which
are output in two runs on the DAD pins. The 3 MSLO,
MSL 1, MSL2 outputs are used to select one pixel
out of the 8 featuring the same address. They issue
the number of the pixel, encoded on 3 bits. MSL3 is
high, and is not used.

FMAT = 1

DAD

MSL
ALL

CK

0

0

0

1

1

0

1

1

0

1

2

3

0 1 2 3 4 5

6

Xo

h5 h4 h3 h2 h1 ho Vo
X1 X2 V1
V7 V6 Vs V4 V3 V2 t

Xo

X1 X2 Y2

Xa X7 X6 Xs X4 X3 Y1
Ya Y7 Y6 Ys Y4 Y3 Yo

13/29

119

EF9365-EF9366
EF9366

EF9365
FMAT = 0

MSL
MSL

ALL

CK

0

0

0

1

1

0

1

1

0

1

2

3

0

0

0

0

Xo and X1
decoded
(active low)

DAD
0 1 234 5

hs h4
V7 V6
X7 X6
Y7 Y6

h3
Vs
Xs
Ys

h2 h1 ho
V4 V3 V2
X4 X3 X2
Y4 Y3 Y2

ALL

CK

6

0

0

Vo
V1
Yo
Y1

0

1

1

0

1

1

1

1

If FMAT is high, the 128 refresh accesses are executed at 2 line intervals, for only one half of the memory, the 32 K-bytes being split into two 16 K-byte
blocks. The V1 output on MSL3 is used to switch
over from one block to the other at 2 line intervals.

0

1

2

3
1

XiJ X1 X2

1

DAD
234 5
hs h4 h3 h2 h1 ho
V7 V6 Vs V4 V3 V2
Xs X7 X6 Xs X4 X3
Y7 Y6 Ys Y4 Y3 Y2
0

1

6

Vo
V1
Yo
Y1

During vertical blanking, such a refresh is achieved
using 4 lines at 16 line intervals.
If FMAT is low or for the EF9366 : the 128 refresh
accesses are executed at 2 display line intervals.

MEMORY OPERATION SEQUENCE ALONG ONE FRAME
Apart from the window where the memory is used for display purposes exclusively, write operations may be
performed, except during 3 refresh periods.

R

Vertical blanking

R

Display
period

w

Vertical blanking

D

D : display
W : write
R : refresh

R

EBB EF9365·14

The three period types, D, Wand R, respectively,
are indicated outside the circuit through the BLK and
ALL signals:

BLK

ALL

D

0

0

W

1

1

R

1

0

Exceptions:
_ If bit 2 in register CTRL 1 is high (high speed
write), the display period is suppressed and 19

14/29

120

a...,I

~

refresh cycles of 4 lines each are executed during one frame.
_ As long as the WO input is high, the circuit is set
to write mode, and BLK retains the same outline
as it has under normal operating conditions.
Inthese two cases, executing codes 0416,0616,0716
and OC16 triggers a complete D sequence for a
highs peed scan of all addresses. This lasts two
frames if FMAT is high or one frame if FMAT is low
and for the EF9366 version.

SCS-THOMSON

[lIj)U©IiI@rn~reii"Iiil@I!lU©®

-n
JJ

»

~

m
(fJ

~

c

m

z

()

m

FMATO
Llo

1 DELTAXignored,DELTAY>O
lODELTAXignored,DELTAYO

CMD = 1316

x = 4710
Origin:

{
Y = 7510

CTRL 1 = 0316 Pen down.

DELTAX= 1710

CTRL2 = 116 Dotted vector:
2 dots on,
2 dots off.

Projection: {

DELTAY = 1310
Plotting cycle sequence: (it is assumed that the vector generator is not interrupted by the display or refresh cycle).

u

I II I I I I I I I I I I I I I I I I I I I I I I I I I
CK

II I I I I I I I I I I I I I IIJIIJ I I I I I I I I I

x

~~~~~~U~"~~~~D.V.~~Dnn~~~~~

y

Bit 2 of

",. 15""

15 1&

n n

I I
------.1

STATUS

IRa
if bit6
ofCTAL=l

"B

19

I

..

au

81

82

B4

I
85 Bol .. B1 BBIB'
BB

B8"

I

IIIII IIIIIIIIIIII IIIIII IIII
IIIIIIIIIIIIIIIIIIIII
I

I

I"

Sym;:

Actual plot

Initialization

EBB EF9365-19

18/29

124

EF9365-EF9366

y

~

End

"""{IIIII~~!f.--",.,~~:~,.M:~~.

'"_.

•

unmodified dOl

o

dot on

____~~LU~LULU~LU~-----------X

E88 EF9365-20
Nole: Plotting a vector with DELTAX = DELTAY = 0 writes the dot X, Y in memory. It occupies the vector generator for synchronization, initialization and one write cycle.

CHARACTER AND SYMBOL GENERATOR

Scaling factors

The character generator operates in the same way
as the vector generator, i. e. through incrementing
or decrementing the X, Y registers, in conjunction
with a DW output control.
It receives parameters from the CSIZE, CTRL2 and
CMD registers. The characters plotted are selected,
according to the CMD value, out of 98 matrices (97
8-dot high x 5-dot wide rectangular matrices, and
one 4 dot x 4 dot matrix) defined in an internal ROM.
Two scaling factors may be applied to the characters plotted using X and Y defined by the CSIZE register. The characters may be tilted, according to
the content of register CTRL2.

Each individual dot in the 5 x 8 basic matrix may be
replaced by a P x Q size block.
P : X co-ordinate scaling factor
Q : Y co-ordinate scaling factor
The character size becomes 5 P x 8 Q. Upon completion of the writing process, X is incremented by 6
P. The CK clock cycle count required is 6 P x 8 Q.
P and Q may each take values from 1 through 16.
They are defined by the CSIZE register. Each value
is encoded on 4 bits, value 16 being encoded as 016.
In register CSIZE, P is encoded on the 4 MSBs and
Q on the 4 LSBs.
Among the 97 rectangular matrices available in the
standard ROM, 96 correspond to CMD values ranging from 2016 to 7F16, and the 97th matrix to OA16.
In the standard version, these values correspond to
the 96 printable characters in the ASCII set. The
97th character is a 5 P x 8 Q block which may be
used for deleting the other characters.
The 98th code (OB16) is used to plot a 4 P x 4 Q graphic block. It locates X, Y, without spacing for the
next symbol. Such a block makes it possible to pad
uniform areas on the screen.

Basic matrix

Upon completion of a character writing process, the
X and Y registers are positioned for writing a further
character next to the previous one, with a 1 dot spacing, i. e. Y is restored to its original value and X is
incremented by 6.

Origin

•

o

I

Unchanged
Altered dots

' \ End
} jf CMD

~ 41

16

(in the ROM

standard version)

x Computed dots. not defined into the ROM (not modifiable).

E88 EF9365-21

~

Origin

o Modified dots
x Computed dot
not defined in
ROM (not modifiable)

End

E88 EF9365-22

19/29

125

EF9365-EF9366
Tilted characters
All characters may be modified to produce tilted characters or to mark the vertical co-ordinate with
straight or tilted type symbols. Such changes may
be achieved using bits 2 and 3 in register CTRL2.

Note: Scaling factors P and Q are always applied
within the co-ordinates of the character before conversion.

a status signal which is reset to the low state by reading register XLP or YLP.
The rising edge first received (LPCK or VB) sets bit
oin STATUS register high. An interrupt is initiated if
bit 4 bin CTRL 1 is high.
When commands 0816 or 0916 have been decoded,
bit 2 of the status register goes high (circuit ready
for any further command) and bit 0 goes low (light
pen operating sequence underway).

Character deletion
A character may be deleted using either the same
command code or command code OA16. In either
case, bit 1 in register CTRL 1 should be inverted, the
origin should be the same as prior to a character
plotting operation, as should the scaling factors.

Note: Vector generator and character generator
operate in similar ways:
Vector

Character

Dimensions

DELTAX, DELTAY

CSIZE, tilting

DW Modulation

Type of Line

Character Code

USE OF LIGHT PEN CIRCUITRY
A rising edge on the LPCK input is used to sample
the current display address in the XLP and YLP registers, provided that this edge is present in the
frame immediately following loading of the 0816 or
0916 code into the CMD register.
Here, the frame origin is counted starting with the
VB falling edge. With code 0816, the WHITE output
recopies the BLK signal from the frame origin up to
the rising edge on the LPCK input, orwhen VB starts
rising again, if the LPCK input remains low for the
entire frame. With code 0916, the WHITE output is
not activated.
The YLP address is 8-bit coded since there are 256
display lines in each frame. The XLP address is 6bit coded since there are 64 display cycles in each
line.
These 6 bits are left justified in the XLP register. XLP
and YLP register contents match the write address
if FMAT is low (or for the EF9366), but should be
multiplied by 2 if FMAT is high, so as to be able to
match the write address.
The address sampled into XLP corresponds to the
current memory cycle. Dots detected by the light
pen were addressed in the memory during the previous cycle. Hence, 1 should be subtracted from bit
2 in XLP register where the light pen electronic circuitry does not produce any additional delay.
If the rising edge on input LPCK occurs while VB is
low, then the LSB in XLP is set high. This bit acts as

20/29

126

SCREEN BLANKING COMMANDS
Three commands (0416, 0616, 0716) will set the
whole display memory to a status corresponding to
a "black display screen" condition. Another command (OC16) may be used to set the whole memory to a status other than black (this condition being
determined by bit 1 in register CTRL 1).
The 4 commands outlined above use the planned
scanning of the memory addresses achieved by the
display stage. The X and Y registers are not affected by commands 0416 and OC16. Hence, the time
required is that corresponding to one frame
(EF9366 or FMAT low) or two frames (FMAT high).
The time corresponding to the completion of the
frame currently executing when the CMD register is
loaded, should be added to the above time.
For the screen blanking process, the frame origin is
counted starting with the VB falling edge.
The only signals affected here are the OW output,
which remains low when VB is low, and the DIN output which is forced high where the 0416, 0616 and
0716 commands are entered.
Such commands are activated without requiring action by WO input or bit 2 in register CTRL 1. While
these commands are executing, bit 2 in STATUS register remains low.
EXTERNAL REQUEST FOR DISPLAY MEMORY
ACCESS (MFREE OUTPUT)
On writing code OF16 into the CMD register, the
MFREE output is set low by the circuitry, during the
next free memory cycle.
Apart from the display and refresh periods, this cycle is the first complete cycle that occurs after input
E is reset high.
During this cycle, those addresses output on DAD
and MSL~respond~ the X and Y register
contents: OW is high, ALL is high.
Should the memory be engaged in a di~y or refresh operation, (which is the case when ALL is I~
then this cycle is postponed to be executed after ALL
is reset high. The maximum waiting time is thus 64
cycles.

EF9365-EF9366
The MFREE signal may be used e. g. for performing
a read or write operation into a register located between the display memory and the microprocessor
bus.

The outputs from these three flip-flop circuits appear
in the STATUS register (bits 4, 5, 6). If one flip-flop
circuit isJ:!!9.h, bit 7 in the STATUS register is high,
and pin IRQ is forced low.

INTERRUPTS OPERATION

A read operation in the STATUS register resets its
4 MSBs low, after input E is reset high.

An interrupt may be initiated by three situations denoted by internal signals:
• Circuit ready for a further command
• Vertical blanking signal
• Light pen sequence completed.

The three interrupt control flip-flops are duplicated
to prevent the loss of an interrupt coming during a
read cycle of the status register.
The status of bits 4, 5 and 6 corresponds to the interrupt control flip-flop circuit output, before input E
goes low.

These three signals appear in real time in the STATUS register (bits 0, 1, 2). Each signal is cross-referenced to a mask bit in the register CTRL 1 (bits 4,
5,6).

An interrupt coming during a read cycle of the STATUS register does not appear in bits 4, 5 and 6 during this read sequence, but during the following
one. However, it may appear in bits 0, 1, 2 or on pin
IRQ.

If the mask bit is high, the first rising edge that occurs on the interrupt initiating signal sets the related
interrupt flip-flop circuit high.

Table 1 : Register Address.
Address Register

Register Functions

Binary

~ad

Write
RIW
D

=

=1

Number
of
Bits

A3

A2

A1

AD

Hexa

0

0

0

0

0

STATUS

0

0

0

1

1

CTRL 1 (write Control and Interrupt Control)

7

0

0

1

0

2

CTRL 2 (Vector and Symbol Type ContrOl)

4

0

0

1

1

3

CSIZE (Character Size)

8

0

1

0

0

4

Reserved

-

0

1

0

1

5

DELTAX

8

0

1

1

0

6

Reserved

8

RIW

CMD

8

0

1

1

1

7

DELTAY

1

0

0

0

8

X MSBs

4

1

0

0

1

9

X LSBs

8

1

0

1

0

A

Y MSBs

4

1

0

1

1

B

Y LSBs

8

1

1

0

0

C

XLP (light-pen)

Reserved

7

1

1

0

1

D

YLP (light-pen)

Reserved

8

1

1

1

0

E

Reserved

-

1

1

1

1

F

Reserved

-

Reserved: These addresses are reserved for future versions of the circuit. In read mode, output buffers DO-D7 force a high state on the data
bus.

21/29

127

EF9365-EF9366
Table 2 : Command Register.
b7
b6
b5
b4
b3 b2 b1 bO

0
0
0
0

0
0
0
1

0
0
1
0

0
0
1
1

0
1
0
0

0
1
0
1

0
1
1
0

0
1
1
1

1
0
0
0

0

1

2

3

4

5

6

7

8 9 A B C D E F

Space!

0

@

P

1
0
0
1

1
0
1
0

1
0
1
1

1
1
0
0

1
1
0
1

1
1
1
0

1
1
1
1

Vector Generation
(for b2, b1 , bO see small vector definition)
0

0

0

0

0

Set Bit 1 of CTRL 1 :
Pen Selection

0

0

0

1

1

Clear Bit 1 of CTRL 1 :
Eraser selection

!

1

A

Q

a

q

0

0

1

0

2

Set Bit 0 of CTRL 1 :
Pen/Eraser Down Selection

"

2

B

R

b

r

0

0

1

1

3

Clear Bit 0 of CTRL 1 :
Pen/Eraser up Selection

#

3

C

S

C

s

b7

0

1

0

0

4

Clear screen

$

4

D

T

d

t

1

0

1

0

1

5

X and Y Registers Reset to 0

%

5

E

U

e

u

0

1

1

0

6

X and Y Reset to 0 and Clear
Screen

&

6

F

V

f

v

0

1

1

1

7

Clear Screen, set CSIZE to
code "minsize".
All other registers reset to O.
(except XLP, YLP)

7

G

W

g

w

P

0

1

0

0

1

0

1

1

0

1

1

1

0

8

1

9

Lignt-Pen initialization

I

Y

i

Y

A

5 x 8 Block Drawing
(size according to CSIZE)

.

9

0

:

J

Z

j

z

1

B

4 x 4 Block Drawing
(size according to CSIZE)

K

[

k

{

0

C

Screen Scanning:
Pen or Eraser as defined by
CTRL1

L

\

I

I
I

1

0

1

D

X Register Reset to 0

1

1

0

E

Y Register Reset to 0

1

1

1

1

F

Direct Image Memory access
request for the next free
cycle.

22/29

128

(

1

I~XI

I~YI

Direction

Dimension

0
0
1

L~n initialization
(WHITE forced low)

1

b2
bl
bO

Vector
Length

or

8

0

b4
b3

b6

~Y

Special Direction Vectors
0

bS

~X

(for b2, b1, bO see small vector definition)
1

Small Vector
Definition

)

+
<

/

H

X

h

x

=

M

1

m

}

>

N

l'

n

~

?

0

+-

0

I

,

o Step
, Step
2 Steps
3 Steps

0

, ,
0

Direction

010

'::(-BOO~
11'~~'0'
100

EBB EF9365-23

EF9365-EF9366
OTHER REGISTERS
STATUS REGISTER (read only)

[7[6[5[4[3[2[1[O[
I

I

1-

I-'~••:

~

HIGH light-pen sequences ended.
} These 3 bits are not latched
HIGH ~ vertical blanking (Idem on pin VB)
and not masked
HIGH ~ ready for a new command; LOW ~ busy
HIGH ~ pen out of display window (logical OR of the 6 MSBs of the X and Y registers)
HIGH ~ light-pen sequence ended IRQ (if enabled) } These 3 bits are reset after a read
HIGH ~ vertical blanking IRQ (if enabled)
cycle of the status register at
, - - - - - - - - - - - - . HIGH ~ ready for a new command IRQ (if enabled)
1 - - - - - - - - - - - - - + . IRQ: logical OR of bits 4, 5, 6 ; HIGH when IRQ output is low.
I

CONTROL REGISTER 1 (read/write)

1-----+.

'-------..

' - - - - - - - - - -__
•

,-------------+.

HIGH ~ pen down: LOW ~ pen up (control DW output)
HIGH ~ pen
; LOW ~ eraser (control DIN output)
HIGH ~ high speed write: no video (BLK output is high, mini. of memory refresh cycles)
HIGH ~ cyclic screen (memory display write even if bit 3 of the status register is high)
HIGH ~ enable end of the light pen sequences IRQ }
HIGH ~ enable VB IRQ
Interrupt masks
HIGH ~ enable ready for a new command IRQ
Not used (Of or reading)

CONTROL REGISTER 2 (read/write)

[ [ [ [ [3 [2 [1 [0 [

1

[1_

b1 bO

~

Type of vectors

- - - - + . HIGH ~ tilted character

Not used
(always read as 0)

'--------+. HIGH

~

character on
vertical axis

Type of Vectors

a a --a 1 ---._-----1 a --1

1

----

Continuous
Dotted
2 dots on, 2 dots off
Dashed 4 dots on, 4 dots off
Dotted10 dots on, 2 dots off
Dashed 2 dots on, 2 dots off

Types of character orientations

,n",.,.

X,V
Final
regisl.er ~ X. ~ register
poslIIon

pOSitIOn

b3 ~ 0, b2 - 0
CSIZE = 11 16

b3 - 1, b2 = a
CSIZE = 11 16

E88 EF9365-24

b3 ~ 0, b2 ~ 1
CS!ZE = 11 16

E88 EF9365-25

I
E88 EF9365-26

b3= l,b2= 1
CSIZE = 11 16

E88 EF9365-27

23/29

129

EF9365-EF9366

I.
l _ _ -----.-l

b3

.~

0, b2 ~ 0
= 22"

b3

~

0, b2 ~ 1
~ 22"

CSIZE

E88 EF9365-28

CSIZE

E88 EF9365-29

C-SIZE REGISTER (read/write)
P : Scaling factor on X axis

a :Scaling factor on Y axis
a

P

P and Q may take any value between 1 and 16. This value is given by the leftmost or rightmost 4 bits for P
and Q respectively. Binary value (0) means 16.
X AND Y REGISTERS (read/write)

1XIXIXIXl31211EJ
1716 1514131211 10 I

MSBs

LSBs

The 4 leftmost MSBs are always O.

XLP AND YLP REGISTERS

l

Status bit indicating if a rising
edge has been applied on LPCK
during the first complete frame
following light-pen initialization.
This bit is reset by a read on
XLP or YLP.

I

8 bit YLP value
always 0
' - - - - _ ti bit XLP value

24/29

130

EF9365-EF9366
ASCII CHARACTER GENERATOR (5 x 8 matrix)

b1
b6
b5

Lb:l b

a

0

a

0
1

1

1
1

a

a

0

a

0
1

a
1

0
1
1

a

0
1
1
1

bl bO

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

----

IIIIII
IIIIII
IIIIII
IIIIII
IIIIII

1111111

IIIIII
IIIIII
IIIIII
IIIIII
IIIIII

1111111
IIIIII
IIIIII
IIIIII
IIIIII
lifi~~~~n':r~:9lt

E88 EF9365-30

25/29

---131

EF9365-EF9366
EXAMPLE OF AN APPLICATION OF THE EF9365 : 256 x 256 BLACK AND WHITE

I

¥

~

~

MSLOto3

RAS

Microprocessor

ONE MEMORY PLANE
256 )( 256 bits

A6
to
AD

07

DAD6
to
DADO

A

to

DO

4 x 16 K bit chips

A3
to
AO

(ET4116)

bus

•
Data

!

•

V

I

Address

GDP

DOUT

R/W

ow

DIN

DIN

CAS

~

RM
IRQ

Control

E

BLK CK SYNC

11 1-

I

4-bit shift
register

G_W
of 1.75
MHz clocks

y

.;- 2

Com posite
video output

Video

I

mixer

~

14 MHz crystal
high-speed clock

~

Note: FMAT = Vss
E88 EF9365-31

26/29

132

Gi
SCiS-niOMSON
~I ~U©iiI@~~~ll:1fiil@IIlU©®

EF9365-EF9366
EXAMPLE OF AN APPLICATION OF THE EF 9365 : 512 x 512 BLACK AND WHITE

I

-I

3 to 8 decoder

E

I

1

llllllllJ

!'.!~'!~'k:~

ONE MEMORY PLANE

512 x 512 bits
2 x 8 (16-K bit chips)

Mf~~to
AD

I-----

l- I-----

CAS.

1+-;:
I+- 01
I+-

1

ALL

Microprocessor bus
07
to
DADS
to
DADO

l

I Address

GOP
R/W
IRQ

Control

DIN
E
BLK CK SYNC

I

8-bit shift
register

Generator
of 1.75 MHz clocks

L-

1

14 MHz crvstal
high-speed clock

Q
Com posite
video output

A3
to
AD

OW

DOUT

Data

DO

1+- __

---------

-

MSL3 MSLO to 2

1

Video
mixer

~

Note; FMAT = VCC

E88 EF9365-32

~ SGS-THOMSON
"."
IiliIOlClI!@OOLmIC'il'li@1lI01:$

27/29

133

EF9365-EF9366
EXAMPLE OF AN APPLICATION OF THE EF9366: 256 x 512 COLOUR.
Eight colours may be obtained from the three basic colours red (R), green (G), blue (8).

I

-E·I~--------------------~

r

3 to 8 decoder

I

II Ll ..L.l..l..lJ

T T TTl IJ

V

3Iut:NI'l.;AL;1

MEMORY PLANES

/8

~

II
RAS

MEMORY PLANE

07

'000

A6~
'0

256:1e 512 bits

~;;

7

CAS

R

Microprocessor bus

ALL MSLO to 2

•

V

I"r--

DAD6

'0
DADO

1--'0
AO"r-A3

AO

1

-J
-

-

GOP

B x I 16 K bi1 chips)

iRci
__
R/W4-.CK

DIN

8

f-r--

,_

,------jH-+-I-+-++-iBlK
DIN

OW

SYNC

.iW
DOUT

3 IDENTICAL
REGISTERS

8

8

I

I
I

I
I

B-bit shift
register

J

I-

g
R

~

/

II r
G

h

J

Gen.rator
•
'-----~'-i of 1.75 MHz clocks~

14 MHze'V".'
hlgh-$p8ed c,cx:k

~

Svnchro

E88 EF9365-33

Note: FMAT

28129

134

= Vee.

EF9365-EF9366
PACKAGE MECHANICAL DATA
40 PINS - PLASTIC DIP

mm

4.57fT1ox

LI'ftOK

,
~
15~

0.2
0.3
15.24

~-----';12:2C"j-~

21
Datum
(1) Nominal dimension

- I
1111

-----J

~_ _ _ _--=53,-,m""a""x,,--.

(2) True geometrical position

14

111

40

PINS

ORDERING INFORMATION
Part Number

Temperature Range

Package

EF9365P
EF9366P

o to 70°C
o to 70°C

DIP 40
DIP 40

29/29

135

EF9367
MOS GRAPHIC DISPLAY PROCESSOR (GOP)
• SELECTABLE RESOLUTIONS IN BLACK AND
WHITE OR COLOR:
VERTICAL RESOLUTION : 525 LINE MONITOR (208 OR 416). 625 LINE MONITOR (256 or
512)
HORIZONTAL RESOLUTION: 256, 320*,384*,
512, 640*, 768*, 1024, FULL SCREEN.(*) with
external PROM
• HIGH SPEED VECTOR PLOT WELL SUITED
TO ANIMATION - 4 TYPES OF LINES
• MULTIPLEXED ADDRESS AND REFRESH
FOR 16 K OR 64 K DYNAMIC RAMs
• NO LIMITATION ON THE NUMBER OF SELECTABLE MEMORY PLANES (colors, grey levels
or any other attributes)
• MUL TIPAGE APPLICATION CAPABILITY
• ON-CHIP FULL ASCII CHARACTER GENERATOR (96) - MAXIMUM ALPHANUMERIC
SCREEN DENSITY: 170 x 57 - PROGRAMMABLE SIZES AND ORIENTATIONS
• DIRECT INTERFACING WITH THE MONITOR
THROUGH THE COMPOSITE SYNCHRO AND
BLANKING SIGNALS
• AUTOMATIC ALLOCATION OF DISPLAY MEMORY IN REFRESH, WRITE, DUMP, AND DISPLAY CYCLES
• LIGHT PEN REGISTERS AND CONTROL SIGNALS
• THREE TYPES OF INTERRUPT REQUESTS
• FULLY STATIC DESIGN
• TTL COMPATIBLE I/O
• SINGLE + 5 V SUPPLY

P
DIP 40
(Plastic Package)

ORDER CODE: EF9367P

PIN CONNECTIONS

CK
DAD5
DAD4
DAD3
DAD6
MSLO
MSL2
FMAT
AO
A1
A2
A3
IRO

vce
DAD1
DAD2
DADO
MSL1
MSL3

SYNC
DO
D1
D2

DW

DESCRIPTION
This GDP is a true high resolution graphic display
processor, which contains all the functions required
to process vector generation at a very high speed
and to generate all the timing signals required for interfacing interlaced or non interlaced video data on
a raster scan CRT display compatible with 525 line
or the CCIR 625 line standards.
December 1988

DIN

VB

BLK

E

MW

R/IN
X9

WO

vss

LPCK

ALL

E88 EF9367·01

1/33

137

EF9367
TYPICAL APPLICATION

ADDRESS BUS (A,BI
DATA BUS

4

(D,B

8

____l....,
VIDEO

I

_.!oQ.~~J
f*----~

/VIDEO
\ OUTPUTS

EBB EF9367-02

TEST LOADS

iRQ

ALL OTHER OUTPUTS

4.75 V

4.75 V

Test point

C

C·40pF
C=-130 pF for DO~D7

=::
~

J

24K

:~

lN916

::~

or Equiv.

:~

or Equiv.

lN4148

EBB EF9367 -04

2/33

138

o-x-

I

MSLD

to
MSL3

DO to 07

X9

~

~~

Ii
~.

Ii

E
RIW
Decoding
Bnd
contral

m

VB

00

'"m
."

!2
~
8

...

15

t5
'"

WD

LPCK

STATUS~
CTRL1

AD to A3

8-.,

EF9367
GENERAL DESCRIPTION
Developed using NMOS technology, the GOP is an
intelligent raster scan video display controller, fully
programmable via an eight-bit microprocessor bus.
Besides all the timing logic functions required to generate the video, sync and blanking signals, the
GOP includes two hardwired display processors: a
vector and a character generator.
This unique feature allows an ultrafast screen writing speed (the 1024 dot diagonal may be written in
less than 1.4 ms) at almost no microprocessor processing cost.
The GOP is particu larly well-su ited to all applications
in which the display memory is not directly addressed by the MPU. This feature allows a total asynchronism between the MPU and the GOP memory
cycles and preserves the whole MPU memory addressing space.

Nevertheless, where direct exchange between the
microprocessor and the memory is necessary, the
on-ch ip allocation controller wi II allow th is exchange
without display interference.
The GOP is programmable using 11 internal registers occupying 16 consecutive addresses. These
registers can also be modified by the GOP's hardwired processors while a command is being executed.
Note: A summary of data codes and registers is given in the Register address table. Hexadecimal
values are subscripted 16 and the register bits are
numbered as follows:

_7-L_6~L-5-L_4~L-3-L_2~__-L_o~ILSB

MSBLI

ABSOLUTE MAXIMUM RATINGS
Symbol

Value

Unit

Vee

Supply Voltage

- 0.3 to + 7.0

V

Vin

Input Voltage

- 0.3 to + 7.0

V

TA

Operating Temperature

o to + 70

°C

- 55 to + 150

°C

T stg

Parameter

Storage Temperature

The GOP inputs are protected against high static voltages and electric fields; nevertheless. normal precautions should be taken to
avoid voltages above the limit values on this high impedance circuit.

STATIC ELECTRICAL CHARACTERISTICS (Vee = 5 V ± 5 %, Vss = 0, TA = 0 to 70 'C unless
otherwise specified)
Symbol
VrH
VrHeK
VrL
lin

140

Parameter

Typ.

Max.

Unit

Vss + 2.2

-

Vee

V

Input High Voltage CK

Vss + 3.5

Vee

V

Input Low Voltage

Vss - 0.3

-

Vss+0.8

V

-

1.0

2.5

!!A

Vss + 2.4

-

-

V

Output Low Voltage (I road = 1.6 mA, Vee = min)

-

-

Vss+O.4

V

Supply Current

-

80

-

mA

Capacitance (V in = 0, T A = 25°C, f = 1.0 MHz)

-

-

12

pF

Input Leakage Current (Vin = 0 to 5.25 V, Vee = max)

VOH

Output High Voltage (iload =- 100 ~A, Vee = min)

VOL
Icc
Cin, Cout

4/33

Min.

Input High Voltage Except CK

EF9367
DYNAMIC OPERATING CONDITIONS
= 5.0 V ± 5 %, Vss = 0 V; TA = 0 to + 70 'C unless otherwise noted)

(VDD

Symbol
ICK

Time (ns)
Clock Period

ICKL

CK Pulse Widlh, Low

ICKH

CK Pulse Widlh, High

CKLDAD

CK Low 10 Valid DAD

CKHDAD

CK High 10 Valid DAD

CKLSYNC

Min.

320
180

CK Low 10 Valid SYNC

CKLBLK

CK Low 10 Valid BLK

CKLVB

CK Low 10 Valid VB

CKLALL

CK Low 10 Valid ALL

CKLMSL

CK Low 10 Valid MSL

CKLDW

CK Low 10 Valid DW

CKLMFRL

CK Low 10 Valid MFREE Low

CKLMFRH

CK Low 10 Valid MFREE High

CKLDIN

CK Low 10 Valid DIN

CKLlRQ

CK Low 10 Valid IRQ

CKLWHI

CK Low 10 Valid WHITE

300
310
500
300
300
310
330
500
310
1500
530

E Pulse Width, Low

450

IEH

E Pulse Widlh, High

lAS

Address Pre-Selup Time

430
160

IAH

Address Hold Time

IEL

IDSW

Dala Pre-Selup Time (wrile)

IDDR

Dala Selup Time (read)

IDHR

Dala Hold Time (read)

IrR
LPHW
LPHIRQ

Max.

560
330
190

10
195
320
10

IRQ Release Time

1600

LPCK High 10 WHITE High (if command 0816)

1600
1600

LPCK High 10 IRQ Low

150

ILPCKH

LPCK High Hold Time

Ir

CK and E Rise Times

20

If

CK and E Fall Times

20

5/33

141

EF9367

CLOCK AND OUTPUT CHARACTERISTICS
CK 3.5V

CK 3.5V;

2:i

~V
I 1_08 V

CK--------

E

I

I

++-

\

I
I

0.8 V

I

..f-.t.

If

I,

Outputs

\

24;
\0.4V

EBB EF9365-05

IRO RELEASE TIME

227:
I

I

'IR

1.....- - - -..... - - - - - - - -

I

/2.4V

IRQ ---------~I-----~·

I
EBB EF9365-06

MICROPROCESSOR BUS. WRITE ACCESS
IEL

IEH

I--

\
AO ... A3

R/W

~

1\

j{

lAS

IAH

,.:-:::-

K

---A

tDSW

DO ... D7

X
EBB EF9365-07

6/33

142

EF9367

MICROPROCESSOR BUS, READ ACCESS

AO ... A3

R/W

00 ... 07

E88 EF9365-08

SYNCHRONOUS SIGNALS WITH CK INPUT

tCKL

CK

CKLDAD

DAD
SYNC
BlK
VB

CKl...

AU

MSl

OW
MFREE

DIN

iRa
WHITE

E88 EF9365-09

LIGHT PEN SIGNALS

tLPCKH

LPCK

/
LPHW

I

- -______- r____~fi
LPHIRQ
IRQ

'\l1'----_____
E88 EF9367-04

7/33

143

EF9367
PIN DESCRIPTION

Power supplies

VCCl

r~

DIN

Display memory
control

/'-

DW

) 00, .. 07

MW'
AD, .. A3
Mlcroprtx.-e:;:,ul

bus

MSlO
to MSL3

EF9367

X9

Display memory
addressing

DADO

Synchronizing

SYNC

..

A/W

E

IRa

to
DAD6

..

ill
and
blanking

LPCK
Light pen

BLK

control

VB

Clock Operating parameters

E88 EF9367-05

• This pin outputs two items of data multiplexed by signal ALL,

POWER SUPPLY, CLOCK AND OPERATING PARAMETERS
Pin
Name Type

N°

Function

Description

Vss

S

20

Power Supply

Ground

Vcc

S

40

Power Supply

+5V

CK

I

1

Clock

FMAT

I

8

Format

WO

I

23

Write Only

8/33

144

Master Clock, All internal processor states are modified on the falling edge
of this signal. The whole circuit logic is static and the cycle of this clock
needs only to be adjusted according to the shape and accuracy the
synchronizing signals should feature,
DAD Memory Address Multiplexing Signal. If CK is low, low addresses (or
row addresses for the memory) are those that are output on DAD,
The frequency of CK is a multiple of the image refresh frequency:
- Interlaced scanning: f (CK) = f (112 frame) x (625 or 525) x 96
- Non-interlaced scanning: f (CK) = f (frame) x (312 or 262) x 96,
This pin is connected to Vcc, Vss, CK or CK and sets the number of
monitor and image lines:
Vcc : 625 line monitor, interlaced synchronization, 512 lines displayed
CK : 525 line monitor, interlaced synchronization, 416 lines displayed
CK : 525 line monitor, non-interlaced synchro, 208 lines displayed
Vss : 625 line monitor, non-interlaced synchro, 256 lines displayed
When WO is high, memory refresh nor display no longer exist TheMd
wired write processors may operate without being interrupted, The ALL
signal is always high,

EF9367
SYNCHRONIZING AND BLANKING SIGNALS
Name

Pin
Type

N°

Function

Description

SYNC

0

34

Video Monitor
Synchronizing

Video Monitor Line and Frame Synchronization Signal. For example, if CK
is at 1.5 MHz and FMAT is high, signal SYNC is to CCIR 625 line 50 Hz
standard.
This output is independent of input WO and of register CTRL1.

BLK

0

25

Blanking

This signal is high apart from the display window (writing or refresh). It is
always high if bit 2 in register CTRL 1 is high, but it is not affected by the
WO input.

VB

0

16

Vertical
Blanking

This signal is not affected by WO and register CTRL 1. High during vertical
blanking.

DISPLAY MEMORY ADDRESSING SIGNALS
Name

Pin
Type

N°

Function

Description

DADO
to
DAD6

0

37,39
38,4
3,2,5

Display
Address

Adresses that are multiplexed by the CK signal. Provided for the automatic
refresh of the 16 K or 64 K dynamic memories.

X9

0

19

Memory
Address

Horizontal pointer extension bit for write operations (horizontal resolution
greater than 512).

MSLO
to
MSL3

2

ALL

0

6, 36 Memory Select Pixel write select signals (see section: display memory configuration).
7, 35
22

Access to all
Memory Units

The signal makes it possible to discriminate between the collective memory
access to all chips (display, refresh or erase), and the memory accesses to
a single pixe for vector or character writing purposes.
The signal is low for collective access.

DISPLAY MEMORY CONTROL SIGNALS
Name

Pin
Type

N°

Function

Description

DIN

0

15

Display In

Selection of the memory data code corresponding to the display screen in
the "off" condition (active when high). For a black-and-white display (1 bit
per pixel), DIN may directly be the storage entry data.

DW

0

14

Display Write

MW

0

24

Memory
Available

Display memory write signal.
Active when Low.
This pin outputs MFREE and WHITE signals which are externally
demult~xed by signal ALL: MFREE = MW + ALL; WHITE =
MW + ALL
--Memory Free (MFREE) :
Signal low during the next memory idle period following the OF16
command.
This signal allows exchanges between the microprocessor and the X and
the Y flagged memory segment without affecting the display.
ForCing to White Level (WHITE) :
Forces white level on video Signal, for use of the light pen.
Active when Low.

9/33

145

EF9367
MICROPROCESSOR BUS SIGNALS
Name

Pin
Type

N°

Function

Description

DO-D7

I/O

33
to
26

Data Bus

1/0 buffers..QPening is controlled through E, and the related direction
through RIW.

AO - A3

I

9
to
12

Address Bus

RIW

I

18

ReadlWrite
Signal

E

I

17

Enable

IRQ

0

13

Interrupt
Request

Address of the register involved in microprocessor access.

ReadlWrite Signal. Write when Low.
Bus exchange synchronizing and enabling signal.
Interrupt request towards the microprocessor, programmable through
register CTRL 1. Open drain output.

LIGHT PEN OPERATING SIGNALS
Name

Pin
Type

N°

Function

Description

LPCK

I

21

Light Pen
Strobe

Light Pen Input. When the Mechanism is set, a rising edge loads into
registers XLP and YLP the current display address and sets the XLP
register's LSB high.

REGISTER DESCRIPTION
X AND Y REGISTERS (addresses: 816, 916, A16,
B16)

DELTAX AND DEL TAY REGISTERS (addresses
516,716)

The X and Y registers are 12-bit read-write registers. They indicate the position of the next dot to be
written into the display memory. They have no
connection at all with the video signal generating
scan, but they point the write address, in the same
way as the pen address on a plotter.

The DEL TAX and DELTAY registers are 8-bit readwrite registers. They indicate to the vector generator
the projections of the next vector to be plotted, on
the X and Y axes respectively. Such values are unsigned integers. The plotting of a vector is initiated
by a write operation in the command register (CMD)

These 2 registers are incremented or decremented,
prior to each write operation into the display memory, by the internal vector and character generators,
or they may be directly positioned by the microprocessor.
This 2 x 12 bit write address covers a 4096 x 4096
point addressing space. Only the LSBs are used
here, since the maximum definition of the picture actually stored is 512 x 1024 pixels (picture elements).
In practice, the GOP assumes that it has a memory
space of 1024 x 512 (fMAT = Vee or CK) or 1024
x 256 (FMAT = Vss or CK) and disables writing outside this space, unless bit 3 of CTRL 1 is set.
The above features along with the relative mode
description of all picture component elements make
it possible to automatically solve the great majority
of edge cut-off problems.

10133

146

CSIZE REGISTER (address: 316)
The CSIZE register is an 8-bit read-write register. It
indicates the scaling factors of X and Y registers for
the symbols and characters. 98 characters are generated from a 5 x 8 pixel matrix defined by an intemal ROM. In the standard version, it contains the
alphanumeric character in the ASCII code which
may be printed, together with a number of special
symbols.

MSBiL

P____

_____

~L_

Q____

____

~i

LSB

Each symbol can be increased by a factor P(X) or
Q(Y). These factors are independent integers which
may each vary from 1 to 16 and which are defined
by the CSIZE register. The symbol generation se-

EF9367
quence is started after writing the ASCII code of the
symbol to be represented in the CMD register.
CTRL 1 REGISTER (address: 116)
The CTRL 1 register is a 7-bit read-write register,
through which the general circuit operation may be
fed with the required parameters.
Bit 0 : When low, this bit inhibits writing in display
memory (equivalent to pen or eraser up).
When high, this bit enables writing in display
memory (pen or eraser down).
This bit control the OW output.
Bit 1 : When low, this bit selects the eraser.
When high, this bit selects the pen.
This bit controls the DIN output.
Bit 2: When low, this bit selects the normal writing
mode (writing apart from the display and refresh periods, which are a requirement forthe
dynamic storages) in display memory.
When high, this bit selects the high speed writing mode: the display periods are deleted.
Only the dynamic storage refresh periods are
retained.
Bit 3 : When low, this bit indicates that the 4096 x
4096 space is being used (the 12 X and Y bits
are significant).
When high, this bit selects the cyclic screen
operating mode.
Bit 4 : When low, this bit inhibits the interrupt triggered by the light per sequence completion.
When high, this bit enables the interrupt.
Bit 5 : When low, this bit inhibits the interrupt release
by vertical blanking.
When high, this bit enables the interrupt.
Bit 6 : When low, this bit inhibits the interrupt indicating that the system is ready for a new command.
When high, this bit enables the interrupt.
Bit 7 : Not used. Always low in read mode.
CTRL2 REGISTER (address: 216)
The CTRL2 register is a 4-bit read-write register,
through which the plotting of vectors and characters
may be denoted by parameters.
Bit 0,1 : These 2 bits define 4 types of lines (continuous, dotted, dashed, dash-dotted).
Bit 2 : When low, this bit defines straight writing.
When high, it defines tilted characters.
Bit 3 : When low, this bit defines writing along an horizontal line.
When high, this bit defines writing along a vertical line.

Bit 4,5,6,7: Not used. Always low in read mode.
CMD COMMAND REGISTER (address: 016)
The CMD register is an 8-bit write-only register.
Each write operation in this register causes a command to be executed, upon completion of the time
necessary for synchronizing the microprocessor access and the GOP's CK clock.
Several types of command are available:
_ vector plotting
_ character plotting
_ screen erase
_ light pen circuitry setting
_ access to the display memory through an external circuitry
_ indirect modification of the other registers (commands that make it possible for the X, Y, DELTAX, DELTAY, CTRL1, CTRL2, and CSIZE registers to be amended or scratched).
STATUS REGISTER (address 016, F16)
The STATUS register is an 8-bit read-only register.
It is used to monitor the status of the executing statements entered into the circuit, and more specifically to avoid the need for modifying a register that
is already used for the command currently executing.
Bit 0 : When low, this bit indicates that a light pen sequence is currently executing.
When high, it indicates that no light pen sequence is currently executing.
Bit 1 :This bit is high during vertical blanking. It is
the VB signal recopy.
Bit 2 : When low, this bit indicates that a command
is currently executing.
When high, this bbit indicates that the circuit
is ready for a new command.
Bit 3 :This bit when low indicates that registers X
and Yare pointing within the assumed memory space.
This bit is obtained by applying the logical OR
function to the unused must significant bits of
registers X and Y.
If FMAT = Vce or CK, the assumed memory
space is 1024 x 5~
If FMAT = Vss or CK, the assumed memory
space is 1024 x 256.
Bit 4 : When high, this bit indicates that an interrupt
has been initiated by the completion of a light
pen running sequence and that this interrupt
has been enabled by bit 4 in CTRL 1 register.
Bit 5 : When high, this bit indicates that an interrupt
has been initiated by vertical blanking and that

11/33

147

EF9367
this interrupt has been enabled by bit 5 in
CTRL 1 register.
Bit 6 : When high, this bit indicates that an interrupt
has been initiated by the completion of execution of a command and that this interrupt
has been enabled by bit 6 in CTRL 1 register.
Bit 7 : When high, this bit indicates that an interrupt
has been initiated. It is the logic OR of bits 4,
5 and 6 in STATUS register. The IRQ output
state is always the opposite of the status of
this bit.

Notes: Bits 4, 5, 6 and 7 are reset low by reading
the STATUS register at address 016. Reading at address F16 does not modify their
state.
XLP AN YLP REGISTERS (addresses C16 and
016)
The XLP and YLP registers are read-only registers,
with 7 and 8 bits respectively. Upon completion of a
high pen running sequence, they contain the display
address sampled by the first edge appearing rising
on the LPCK input. The use.of such registers is discussed in section: Use of light pen circuitry.

Notes :1. All internal registers may be read or written at any time by the microprocessor.
However, the precautions outlined below should be observed:
_ Do not write into the CMD register if
execution of the previous command is
not completed (bit 2 of STATUS register).
_ Do not alter any register if it is used as
an input parameter for the internal
hardwired systems (e.g. : modifying
the DEL TAX register while a vector
plotting sequence is in progress).
_ Do not read a register that is being
asynchronously modified by the internal hardwired systems (e.g. : reading
the X register while a vector plotting
sequence is in p.!:..ogress may be erroneous if CK and E are asynchronous).
2. On powering up, the writing devices may
have any status. Before entering a command for the first time, it is necessary to
wait until all functions currently underway
are completed, which information can be
derived from the STATUS register.

SYSTEM OPERATING PRINCIPLE
DISPLAY MEMORY CONFIGURATION
Assume a V x H pixel picture. Assume that each
pixel is able to adopt 2b different states. A V x H x b
bit display memory is thus required.

b planes

In those applications where H features a high value,
the video signal frequency exceeds the maximum
frequency of memory read access.
Example: H = 512 with a television line frequency:
the pixel succession period on the video
signal is 83 ns.
It is mandatory that a line of H dots be cut into h adjoining segments of n bits each, read at the same
time in the display memory, and thereafter converted to serial form to produce the video signal, h memory accesses per line are necessary. Each access
loads b n-bit shift registers. The memory contains
V x h x b n-bit words.

12/33

148

.--1--------1 pixel

denoted bV
(

v,

bbits

V·
X

X

X

bbits

E88 EF9367-06

EF9367
The EF9367 is designed for the following stored
image formats:
V = 512 or 256 (50 Hz)
V' = 416 or 208 (60 Hz)
H = h xn
H = 1024 or lower multiples of 64
h = 64
n = 16,8,4,2,1 (or any value below 16 using ex
ternal PROM encoding)
b = any value (addressing is same for all memory
planes, management of these planes is external to the GDP).
In so far as the overflow tests are concerned, the

"

circuit assumes that it still has the maximum memory space for X (1024) . The test for Y is effected in
the folowing memory spaces:
512 if FMAT = Vee or CK
256 if FMAT = Vss or CK
512 or 256 vertical resolution: the displayed space
is identical to the space in memory (unless a greater memory capacity is deliberately selected).
416 or 208 vertical resolution: the displayed space
is smaller than the memory space.
Lines not displayed are displayable using an external adder to dejustify the display addresses (this arrangement may be used for smooth roll-up/roll down.

b memory planes

1 thr-ough

V x h address

GDP

1 memory plane ==

V x h n-bit words

Dot
frequency
clock
Video signal

b n-bit

on b bits

shift registers

EBB

DAD AND MSL STATUS TABLE
The internal cou nters which address the display memory are made up of :
_ 6 horizontal address bits (h = 64)
ho, h1, h2, h3, h4, hs,
(ho = LSB)
_ 9 vertical address bits (V ,,; 512)

t, Va, V1, V2, V3, V4, V5, V6, V7
t is here the LSB. It denotes the line parity and
changes every frame because of interlaced scanWithin a same frame, Vo denotes the LSB.

Xg

MSL

a a
a 1
1
a
1

1

a

The write address is made up of the LSBs of the X
and Y internal registers.
Xc, X1, X2, X3, X4, X5, X6, X7, XB,X9
Yo, Y1, Y2, Y3, Y4, Y5, Y6, Y7, YB
The GDP produces addressing signals in the sequences shown in the following tables:

FMAT = Vss or CK

FMAT = Vee or CK

ALL CK

DAD

a

ALL CK

h5 h4 h3 h2 h1 ho Vo
Xo X1 X2 V1 Xg
V7 V6 V5 V4 V3 V2 t
Xa X7 X6 X5 X4 X3 Y1
Xo X1 X2 Y2 Xg
Ya Y7 Y6 Y5 Y4 Y3 Yo

a a
a 1
1
a

2

3

1 234 5

Xg

MSL

6

1

EF936S-13

1

1

a

1

2

3

Xo X1 X2 1
Xo X1 X2 1

DAD

a

1 234 5

6

h5 h4 h3 h2 h1 ho Vo
Xg
V7 V6 V5 V4 V3 V2 V1
Xa X7 X6 X5 X4 X3 Yo
Xg
Y7 Y6 Y5 Y4 Y3 Y2 Y1
13/33

149

EF9367
DESCRIPTION OF DISPLAYABLE FORMATS

Interlaced Scanning

Non Interlacing Scanning
256 x 512 or 208 x 512 pixel formats (H = 51~n
= 8). Input FMAT must be low or connected to CK.
The memory is made up of 16 K bytes per memory
plane. The byte address is made up of 14 bits which
are output on two runs on the DAD pins. The three
MSLO, MSL 1,MSL2 outputs are used to select one
pixel out of the eight featuring the same address.
They issue the number of the pixel, encoded on three
bits. MSL3 is high, and is not used.
256 x 384 or 208 x 384 pixel formats (H = 38~n
= 6). Input FMAT must be low or connected to CK.
The memory is organized as 16 K words x 6 bits.
The signals produced by the chip in the sequence
indicated for the 256 x 512 format are transcoded
externally as shown in the opposite diagram.
256 x 320 or 208 x 320 pixel formats (H = 320, n
= 5). The same schematic as for 384 horizontal resolution should be used with a memory organized
in 5 bit words.
256 x 256 or 208 x 256 pixel formats (H = 25~n
= 4). Input FMAT must be low or connected to CK.
The memory is made up of 16 K words x 4 bits. The
word address up of 14 bits which are output in two
runs on the DAD pins. One of the four chips is selected by decoding pins MSL 1 and MSL2 (that leads
to ignore Xo : the X computation space is changed
to 2048 pixels horizontal overflow detected at 512
pixels).

512 x 1024 or 416 x 1024 pixel formats (H = 1024,
n = 16).lnput FMAT must be connected to Vcc or
CK
The memory comprises 32 K words x 16 bits, organized in two blocks of 16 K words each.
The signals produced by the circuit in the sequence
indicated for the 512 x 512 format are combined externally as shown at the end of the data sheet.

=

512 x 768 or 416 x 768 pixel formats (H 768, n
= 12). Input FMAT must be connected to Vce or CK.
The memory comprises 32 K words x 12 bits, organized in two blocks of 16 K words each.
The signals produced by the chip in the sequence
indicated for the 512 x 512 format are transcoded
externally as shown in the diagram below.
512 x 640 or 416 x 640 pixel formats (H = 640, n
=10). The same schematic as below should be used
with a memory organized in 10 bit words.
512 x 512 or 416 x 512 pixel formats (H = 512, n
= 8). The FMAT input should be tied to Vee or CK.
The memory is made up of V x h bytes = 32 K bytes
per memory plane.
The byte address is made up of 15 bits:
_ 14 are output in 2 runs on the DAD pins for the
purpose of using 16 K x 1 bit dynamic RAMs.
_ the 15th one is output on pin MLS3.
The MLSO, 1 and 2 outputs allow to select one pixel
out of the 8 featuring the same address, for pixel-topixel write applications. They issue the number of
the involved pixel, encoded on 3 bits.

Xo
Bit

address
PROM
256 x 8

Word
address

VI/YO

EBB EF9367-07

Y1/YO

EBB EF9367-0B

14/33

150

EF9367
MEMORY OPERATION SEQUENCE ALONG ONE FRAME
Apart from the window where the memory is used for display purposes exclusively, write operations may be
performed, except during 3 refresh periods.

R

Vertical blanking

R

D : display

Display
period

w

o

W : write
R : refresh

Vertical blanking

R

E88 EF9365-13

The three period types, D, Wand R, respectively,
are indicated outside the circuit through the BLK and
ALL sig nals :
BLK

ALL

D

0

0

W

1

1

R

1

0

The refresh of dynamic RAMs is automatically performed by the GDP. During display, the memory is
entirely refreshed each 4 lines (256 accesses).
During vertical blanking, 3 refresh cycles of 4 lines
each are executed.

Exceptions:
_ If bit 2 in register CTRL 1 is high (high speed
write), the display period is suppressed and 19
refresh cycles of 4 lines each are executed during one frame.
_ As long as the WO input is high, the circuit is set
to write mode, and BLK retains the same outline
as it has under normal operating conditions.
In these two cases, executing codes 0416, 0616, 0716
and OC16 triggers a complete D sequence for a
high-speed scan of all addresses. This last two
frames if FMAT is high (or tied toCK) and one frame
if FMAT is low (or tied to CK).

15/33

151

"11
:II

~
I en
I\)
W
w

l>

s:
m

en

m
c
m

"z
0

m

-

",,---,---,--,----,!TTl

1(u..(I-L-,-1......
1~I,JJ,I

'r

I

FMAT = CK
SYNC

~~_I~)I

TV line number

u:

I I

I(fl
,.

VB

@.

1,,1
,I

I lui
It

r
Ir

I I

Inl

Iii I I

I

I

1:;1

YJlr,fL' --'--~....

even frame

LLLUTTlLL.L.LL.)1 I

~en

L((I
I'

odd frame

FMAT - CK

~

I I I

I

I If;1 I

i

I I I Irll I I I I I I I I I I I IJII I I I lUi I I I IIII I I

I

!

1,1'1+1,1.1'11++1"1 11++1"1 111++H++H++III,,,I,..I,,,1 :'"1'' 1",1",11",1, ,1, ,1' '1

- --------1"
,

"
;f

Ii

(~,----f5

J/.\------,\

en
N
en
r
Z

m

en
-<
z

0
::I:

:II

0
Z

N

l>

~;!

!o
~I:
",en

B,LKlif
bit
2m
CTRL1- 01

!;Ii

ALL (If
bit 2 in
CTRL1=OI

11

CTRL1=ll

Note

m

CP
CP

m

"
en
6"
<0
W

<0

AIl signal high denotes write period5.

0

/1

Z

--

'~r---u-u-u-u-'~~>--uvLnP')~'
~
i----J
I.
..I
1-------1
Refresh

~,~~:~

-I

"

) (~:n-uu-" )

JJ

R.fresh

Display

rh~"",~rl~~~"",,..........(~)
'UUUU'
UUUU .

Refresh

Jh....,n~rlif---. UUUU'

--I

i---I

I..----..j

i------l

Refresh

Refresh

Refresh

Refr.esh

m

"11
<0

(,J

Ol

"'"

EF9367
FRAME SEQUENCE - 625 LINE SYNCHRONIZATION

~

g

!

§

>

>

u

•

!(
~

~

~:>

~

~

-----

I:

<5

Gl

~.~
",00

aL~

;..!:~

[...INa:

~:Et

:=£
1...100

eta

"z~

EBB EF9367-10

- - - - - - 1t."'!1 ~~~;~~'t:9:£

_ _ _ _ _1_7/33
153
-----~-=

EF9367
COMPOSITE SYNC AROUND FRAME SYNC

T : CK input period (667 ns in typical application where TV line duration is 64 ,us)

Vertical sync pulses

SYNC

J

r;

End of odd ' ..me

Beginning of even frame

End of even frame

Beginning of odd frame

SYNC

Note: If FMAT is low or tied to CR, the pattern of the second line is repeated for each frame.
E88 EF9367-11

DETAILED LINE DIAGRAM

96T

Line sync

----f-J

SYNC
Vertical

VB

ALL
BLK
WHITE

23T

-I-

64T

ow

MFREE _ _ _ _ _ _ _ _ _ _ _ _ _

~

E88 EF9367-12

18133

154

EF9367
HARDWIRED WRITE PROCESSOR OPERATION IN DISPLAY MEMORY
The hardwired write processors are sequenced by
the master clock CK. They receive their parameters
from the microprocessor bus. Th~ntroL.!.IJ..g X, Y
write address, and the DIN, DW, MW and IRQ outputs.
These hardwired processors operate in continuous
mode. In the event of conflicting access to the display memory, the display and refresh processors
have priority.
Since command decoding is synchronous with the
CK master clock, any write operation into the (CM D)
command register triggers a synchronizing mechanism which engages-.Jhe circuit for a maximum of 2
CK cycles when the E input returns high. The circuit
remains engaged throughout command execution.
No further command should be entered as long as
bit 2 in STATUS register is low.

DW sequencing during the plotting process is always the same, irrespective of vector origin and of
the nature of previous plots. This feature guarantees
that a specified vector can be deleted by plotting it
again after moving X and Y to the starting point, and
complementing bit 1 in register CTRL 1.
Since the vector plotting initiation command defines
the sign of the projections onto the axes, all vectors
may be plotted using 4 different commands.
For increased programming flexibility, the system incorporates 16 different commands, supplemented
by a set of 128 commands which make it possible
to plot small size vectors by ignoring the DELTAX
and DELTAY registers.
Such commands are as follows:
• Basic commands
lololol'lolxlxl'l

I l. DEL TAX sign I
~ DE L TA Y sign

VECTOR PLOTTING
The internal vector generator makes it possible to
modify, within the display memory, all the dots which
form the approximation of a straight line segment.
All vectors plotted are described by the origin dot
and the projections on the axes.
The starting point co-ordinates are defined by the X,
Y register value, prior to the plotting operation.
Projections onto the axes are defined as absolute
values by the DELTAX and DELTAY registers, with
the sign in the command byte that initiates the vector plotting process.
The vector approximation achieved here is that established by J.F. BRESENHAM ("Algorithm for computer control of a digital plotter"). This algorithm is
executed by a hardwired processor which allows for
a further vector component dot to be written in each
CK clock cycle.

• commands which allow ignoring the DEL TAX or
DELTAY registers by considering them as of zero value

9

~

:0

All vectors may be plotted using any of the following
line patterns: continuous, dotted, dashed, dash-dotted, according to the 2 LSBs in register CTRL2.
Irrespective of such pattems, the plotting speed remains unchanged. The "pen down-pen up" statement required foL..Q!.otting non-continuous lines is
controlled by the DW output.
For a specified non-continuous line plotted vector,
defined by DELTAX, DEL TAY, CTRL2, CMD, the

a DELTAY ignored, DEL TAX> a

0 ' DELTAXignored, DELTAY >0

, a DELTAXignored,DELTAYO

CTRL 1 = 0316 Pen down,

DELTAX= 1710

CTRL2 = 116 Dotted vector:
2 dots on,
2 dots off.

Projection: {
DELTAY = 1310

Plotting cycle sequence: (it is assumed that the vector generator is not interrupted by the display or refresh cycle).

u

I I I I I I I I I I I I I I I I I I I I I I I I I I I I
CK

1 ~1~1~1~1~1~IUI~I"I~I~I~I~I~I.IDI~IHI~lnlul~lwlmlmlmlml

x

15

y

75

1!t

15

1!t

15 16

11

I I

STATUS

78

19

I

------.1
Bit 2 of

71

10 80

B1

82

8J BJ

14 85

86

iii

87

SB

II

88

88

88

I

IIIII III II IIIIIII I IIIII IIII

IRQ
it bit 6
of CTRL= 1

I II III II III IIII III III
I

I
/

Sync

'-

Actual plot

Initialization

E88 EF9365·19

20/33

156

EF9367

y

~

DElTAY

End

l',·.~

Dots "origin" and "end"
are modified

~

Display shows :

•

unmodified dot

o

dolan

_______ 0';9;n

41

~

DEL TAX

E88 EF9365-20
Note: Plotting a vector with DELTAX = DEL TAY
zation, initialization and one write cycle.

=

0 writes the dot X, Y in memory. It occupies the vector generator for synchroni

CHARACTER AND SYMBOL GENERATOR

SCALING FACTORS

The character generator operates in the same way
as the vector generator, i.e. through incrementing or
decrementing the X, Y registers, in conjunction with
a DW output control.
It receives parameters from the CSIZE, CTRL2 and
CMD registers. The characters plotted are selected,
according to the CMD value, out of 98 matrices
(97 8-dot high X 5-dot wide rectangular matrices,
and one 4 dot X 4 dot matrix) defined in an internal
ROM. Two scaling factors may be applied to the
characters plotted using X and Y defined by the
CSIZE register. The characters may be tilted, according to the content of register CTRL2.

Each individual dot in the 5 x 8 basic matrix may be
replaced by a P x Q size block.

BASIC MATRIX
Upon completion of a character writing process, the
X and Y registers are positioned for writing a further
character next to the previous one, with a 1 dot spacing, i.e. Y is restored to its original value and X is
incremented by 6.

P : X co-ordinate scaling factor

Q : Y co-ordinate scaling factor
The character size becomes 5 P x 8 Q. Upon completion of the writing process, X is incremented by
6P. The CK clock cycle count required is 6 P x 8 Q.
P and Q may each take values from 1 through 16.
They are defined by the CSIZE register. Each value
is encoded on 4 bits, value 16 being encoded as 016.
In register CSIZE, P is encoded on the 4 MSBs and
Q on the 4 LSBs.
Among the 97 rectangular matrices available in the
standard ROM, 96 correspond to CMD values ranging from 2016 to 7F16, and the 97th matrix to OAI6.
In the standard version, these values correspond to
the 96 printable characters in the ASCII set. The
97th character is a 5 P x 8 Q block which may be
used for deleting the other characters.
The 98th code (OBI6) is used to plot a 4 P x 4 Q graphic block. It locates X, Y, without spacing for the
next symbol. Such a block makes it possible to pad
uniform areas on the screen.

~

Origin

I

•
Unchanged
(~ Altered dots

' \ End
} if CMD - 41

(in the ROM
standard version)

J6

x Computed dOIS, not defined into the ROM (not modifi-

;It(
Origin

@ Modified dots
x Computed dot
not detlned In
ROM (not modifiable)
End

able).

E88 EF9365-21

E88 EF9365-22

21/33

157

EF9367
TILTED CHARACTERS
All characters may be modified to produce tilted characters or to mark the vertical co-ordinate with
straight or tilted type symbols. Such changes may
be achieved using bits 2 and 3 in register CTRL2.

Note: Scaling factors P and Q are always applied
within the co-ordinates of the character before
conversion.
CHARACTER DELETION
A character may be deleted using either the same
command code or command code OA16. In either
case, bit 1 in register CTRL 1 should be inverted, the
origin should be the same as prior to a character
plotting operation, as should the scaling factors.

Note: Vector generator and character generator
operate in similar ways:
Vector

Character

Dimensions

DELTAX, DELTAY

CSIZE, tilting

DW Modulation

Type of Line

Character Code

USE OF LIGHT PEN CIRCUITRY
A rising edge on the LPCK input is used to sample
the current display address in the XLP and YLP registers, provided, that this edge is present in the
frame immediately following loading of the 0816 or
0916 code into the CMD register.
Here, the frame origin is counted starting with the
VB falling edge. With code 0816, the MW output recopies the BLK signal from the frame origin up to
the rising edge on the LPCK input, orwhen VB starts
rising again, if the LPCK input remains low for the
entire frame. With code 0916, the MW output is not
activated.

The rising edge first received (LPCK or VB) sets bit 0
in STATUS register high. An interrupt is initiated if
bit 4 in CTRL 1 is high.
When commands 0816 or 0916 have been decoded,
bit 2 of the status register goes high (circuit ready
for any further command) and bit 0 goes low (light
pen operating sequence underway).
SCREEN BLANKING COMMANDS
Three commands (0416, 0616, 0716) will set the
whole display memory to a status corresponding to
a "black display screen", condition. Another command (OC16) may be used to set the whole memory to a status other than black (this condition being
determined by bit 1 in register CTRL 1).
The 4 commands outlined above use the planned
scanning of the memory addresses achieved by the
display stage. The X and Y registers are not affected by commands 0416 and OC16. Hence, the time
required is that corresponding to one frame (FMAT
= 0 or CK) or two frames (FMAT = 1 or CK). The
time corresponding to the completion of the frame
currently executing when the CMD register is loaded, should be added to the above time.
For the screen blanking process, the frame origin is
counted starting with the VB falling edg~
The only signals affected here are the OW output,
which remains low when VB is low, and the DIN output which is forced high where the 0416, 0616 and
0716 commands are entered.
Such commands are activated without requiring action by WO input or bit 2 in register CTRL 1. While
these commands are executing, bit2 in STATUS register remains low.
EXTERNAL REQUEST FOR DISPLAY MEMORY
ACCESS (MW output)

The YLP address is 8-bit coded since there are 256
display lines in each frame. The XLP address is 6bit coded since there are 64 display cycles in each
line.

One writing code OF16 into the CMD register, the
MW output is set low by the circuitry, during the next
free memory cycle.

These 6 bits left-justified in register XLP indicate the
number of the segment (h = 0 to 63) to which the
point indicated by the light pen belongs.

Apart from the display and refresh periods, this cyQ]e is the first complete cycle that occurs after input
E is reset high.

The address sampled into XLP corresponds to the
current memory cycle. Dots detected by the light
pen were addressed in the memory during the previous cycle. Hence, 1 should be subtracted from bit
2 in XLP register where the light pen electronic circuitry does not produce any additional delay.

During this cycle, those addresses output on DAD
and MSL ~respond-.JQ.. the X and Y register
contents: OW is high, ALL is high.

If the rising edge on input LPCK occurs while VB is
low, then the LSB in XLP is set high is set high. This
bit acts as a status signal which is reset to the low
state by reading register XLP or YLP.

22/33

158

Should the memory be engaged in a di~y or refresh operation, (which is the case when ALL is IQW,.
then this cycle is postponed to be executed after ALL
is reset high. The maximum waiting time is thus 64
cycles.
The MW signal may be used e.g. for performing a
read or write operation into a register located be-

EF9367
tween the display memory and the microprocessor
bus.

in the STATUS register (bits 4, 5, 6). If one flip-flop
circuit is.lli.9.h, bit 7 in the STATUS register is high,
and pin IRQ is forced low.

INTERRUPTS OPERATION

A read operation in the STATUS reg is.1e r at address
016 resets its 4 MSBs low, after input E is reset high
(a read at address F16 maintains their value).

An interrupt may be initiated by three situations denoted by internal signals:
o
Circuit ready for a further command.
o
Vertical blanking signal.
o
Light pen sequence completed.

The three interrupt control flip-flops are duplicated
to prevent of an interrupt coming during a read cycle of the STATUS register.

These three signals appear in real time in the STATUS register (bits 0, 1, 2). Each signal is cross-referenced to a mask bit in the register CTRL 1 (bits 4,

The status of bits 4, 5 and 6 corresponds to the iQ.:
terrupt control flip-flop circuit output, before input E
goes low.

5,6).

An interrupt coming during a read cycle of the STATUS register does not appear in bits 4, 5 and 6 during this read sequence, but during the following
one. However, it may appear in bits 0, 1, 2 or on pin
IRQ.

If the mask bit is high, the first rising edge that occurs on the interrupt initiating signal sets the related
interrupt flip-flop circuit high.
The outputs from these three flip-flop circuits appear
Table 1 : Register Address.
Address Register

Register Functions

Binary

liead
R/W = 1

Hexa

Write
R/W = 0

Number
of
Bits

A3

A2

A1

AO

a
a
a
a
a
a
a
a

a
a
a
a

a
a

a

a

STATUS

1

1

CTRL 1 (Write Control and Interrupt Control)

7

1

a

2

CTRL 2 (Vector and Symbol Type Control)

4

1

1

3

CSIZE (Character Size)

8

1

a

4

Reserved

-

1

a
a

1

5

DELTAX

8

1

1

a

6

Reserved

-

1

1

1

7

DELTAY

8

1

a
a

a

8

x MSBs

4

1

9

X LSBs

8

1

a

A

Y MSBs

4

1

a
a
a
a

1

1

B

Y LSBs

1

1

a

C

XLP (light-pen)

Reserved

7

1

1

a
a

1

D

YLP (light-pen)

Reserved

8

1

1

1

a

E

Reserved

1

1

1

1

F

STATUS

1
1

Reserved:

CMD

8

8

-

Reserved

8

These addresses are reserved for future versions of the circuit. In read mode, output buffers 00-07 force a high state on the data
bus.

23/33

159

EF9367
Table 2 : Command Register.
b7
b6
b5
b4
b3 b2 b1

bO

0
0
0
0

0
0
0
1

0
0
1
0

0
0
1
1

0
1
0
0

0
1
0
1

0
1
1
0

0
1
1
1

1
0
0
0

1
1
1
0

1
1
1
1

0

1

2

3

4

5

6

7

8 9 A B C D E

F

Space 0

1
0
0
1

1
0
1
0

1
0
1
1

1
1
0
0

1
1
0
1

Vector Generation
(for b2, b1 , bO see small vector definition)
0

0

0

0

0

Set Bit 1 of CTRL 1 :
Pen Selection

@

P

!

1

A

Q

a

q

"

2

B

R

b

r

#

3

C

S

c

s

P

0

0

0

1

1

Clear Bit 1 of CTRL 1
Eraser selection

0

0

1

0

2

Set Bit 0 of CTRL 1 :
Pen/Eraser Down Selection

0

0

1

1

3

Clear Bit 0 of CTRL 1 :
Pen/Eraser up Selection

$

4

D

T

d

t

0

1

0

0

4

Clear screen

%

5

E

U

e

u

0

1

0

1

5

X and Y Registers Reset to 0

&

6

F

V

f

v

0

1

1

0

6

X and Y Reset to 0 and Clear
Screen

7

G

W

g

w

0

1

1

1

7

Clear Screen, set CSIZE to
code "minsize".
All other registers reset to O.
(except XLP, YLP)

b7

0

1

0

0

1

1

0

1

0

1

0

1

1

B

4 x 4 Block Drawing
(size according to CSIZE)

1

1

0

0

C

1

1

0

1

1

1

1

0

1

1

1

1

24/33

160

0

lilXI lilYI Direction

DIMENSION
Vector
Length

or

Lignt-pen initialization
(WHITE forced low)

(

8

9

Lignt-Pen initialization

I

Y

i

Y

5 x 8 Block Drawing
(size according to CSIZE)

.

9

A

:

J

Z

j

z

+

;

K

[

k

{

Screen Scanning:
Pen or Eraser as defined by
CTRL1

<

L

\

I

I
I

D

X Register Reset to 0

=

M

1

m

}

E

Y Register Reset to 0

>

N

t

n

~

F

Direct Image Memory access
request for the next free
cycle.

?

0

f-

0

~

8

b2
bl
bO

b4
b3

ilY

(for b2, b1, bO see small vector definition)
0

1

b6
bS

ilX

Special Direction Vectors
1

SMALL VECTOR
DEFINITION

)

/

H

X

h

x

0
0
1
1

0
1
0
1

o Step
1 Step
2 Steps
3 Steps

DIRECTION

010

':{f"jOO~
111~tJl0l
100

E88 EF9365-23

EF9367
OTHER REGISTERS
STATUS REGISTER (read only)

• HIGH = light-pen sequences ended.
} These 3 bits are not latched
HIGH = vertical blanking (Idem on pin VB)
and not masked
HIGH = leady for a new command: LOW = busy
' - - - - _ _ + . HIGH = pen out of display window (logical OR of the 6 MSBs of the X and V registers)
HIGH = light-pen sequence ended IRQ (if enabled) } These 3 bits are reset after a read
HIGH = vertical blanking IRQ (if enabled)
cycle of the status register at
, - - - - - - - - - - - - - . . HIGH = ready for a new command IRQ (if enabled)
address 0,6.
, - - - - - - - - - - - - - + . IRQ : logical OR of bits 4, 5, 6, ; HIGH when IRQ output is low.

,-----+.

CONTROL REGISTER 1 (read/write)

• HIGH = pen down; LOW = pen up (control OW output)
HIGH = pen
; LOW = eraser (control DIN output)
,-----+. HIGH = high speed write: no video (BLK output is high, mini. of memory refresh cycles)
,------+. HIGH = cyclic screen (memory display write even if bit 3 of the status register is high)
HIGH = enable end of the light pen sequences IRQ
} Interrupt masks
HIGH = enable VB IRQ
'-----~--------.. HIGH = enable ready for a new command IRQ
, - - - - - - - - - - - - - + . Not used (0 for reading)

CONTROL REGISTER 2 (read/write)

b1 bO
Type of vectors
Not used
(always read as 0)

, - - - - . . HIGH

=

tiltedcharacter

, - - - - - - . . HIGH = character on
vertical axis

0
0
1
1

0
1
0
1

Type of Vectors
----------------

---

Continuous
Dotted
2 dots on, 2 dots off
Dashed 4 dots on, 4 dots off
Dotted10 dots on, 2 dots off
Dashed 2 dots on, 2 dots off

Types of character orientations

II

Initial
X,V
Final
regj~t.er ~ X. V. .register
position

pOSItion

b3 = 0, b2 ~ 0
CSIZE = 11 16

b3 = 0, b2 = 1
CSIZE = 11 16
E88 EF9365-24

E88 EF9365-25

25/33

161

EF9367
Types of character orientations

I

=

0
b3 =1, b2
CSIZE = 11 16

b3 = 1, b2 = 1
CSIZE = 11'6

EBB EF9365-26

b3

~

0, b2

~

b3~O b2~

0

1

CSIZE'~ 22'6

EB8 EF9365-28

CSIZE ~ 22'6

E88 EF9365-27

E88 EF9365-2S

C-SIZE REGISTER (read/write)
P : Scaling factor on X axis

o : Scaling factor on Yaxis
P

0

P and Q may take any value between 1 and 16. This value is given by the leftmost or rightmost 4 bits for P
and Q respectively. Binary value (0) means 16.
X AND Y REGISTERS (read/write)

1X1XMXJ

3 12 11 10

1

17161514131211101

MSBs

LSBs

The 4 leftmost MSBs are always O.
XLP and YLP REGISTERS

l

Status bit indicating if a rising
edge has been applied on LPCK
duri ng the first complete frame
following light-pen initialization.
This bit is reset by a read on
XLP or YLP.

j
8 bit Y LP value

always 0
' - - - - - - - - j...

26/33

162

6 bit XLP value

EF9367
ASCII CHARACTER GENERATOR (5 x 8 matrix)

b7

0

0

b6

0

0

b5
1
1
b401

0

0

0

0

1

1

1

1

0
0
1
1
0101

ib:;b2blbO

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1 0.1

0

1011

1100

1101

1110

1111

IIIIII
IIIIII
IIIIII
IIIIII
IIIIII
IIIIII
IIIIII
1111111
IIIIII
IIIIII
IIIIII
1111111
IIIIII
1111111
IIIIII
IIIIII

E88 EF9365-30

163
--------

----~-----"

_._-- ---------..-

.""'.--~-----,,---------~---

-

---~-~---- .~-, --"~---

----=~-----=-=

EF9367
EXAMPLE OF A MONOCHROME APPLICATION: 512

r

3 to a decoder

E

1

1
I

~

~~'~
CAS,

ONE MEMORY PLANE
512 x 512 bits

x 512 or416 x 512

---

c-J
~

r--

ALLMS L3 MSLO to 2

Mf~~
10

AO

2 x a {16-K bit chips}

01
to
DO

DAD6
to
DADO

~ ~

I-I-

~

a or 16 bit
microprocessor bus

I-----

A3
to
AU

)

Data

I

Address

GDP

I--L-

R/W

-

-ow

IRQ

Control

DIN
E
BLK CK SYNC

DOUT
~

~

I

a-bit shift
register

Generator
'-J

Com posite

..

~

12 MHz crystal
high·speed clock

(:J
video output

of 1.5 MHz clocks

Video

.~

mixer

EBB EF9367·13

Notes: FMAT
FMAT

28/33

164

= Vee: 512 x 512 resolution· 50 Hz 625 line non inlerlaced scanning.
= CK : 416 x 512 resolution· 60 Hz 525 line non interlaced scanning.

EF9367
EXAMPLE OF A COLOR APPLICATION: 208

x 512 or 256 x 512

Eight colours may be obtained from the three basic colours red (R), green (G), blue (8).

--

l

I

3 to 8 decoder

EJ

I

T
J IDENTICAL ;
MEMORY PLANES

11)

TT

T

I

T

A

H

V

/

8

I{
256

x

L

./t

~

8or16bn

(.

RAS

MEMORY PLANE

8

CAS

R

AO

to

512 b;ts

A6

8 x 116 K-bit chipsl

I-Y

7

'7
7/

07
10

IV--

DO

7

I

DAD6
'0

OADO
A3 1f - ~Ol\ -

-

GOP
RIW
CK

DIN

8

~-

BLK
DIN

Rfw
°OUT

3 IDENTICAL
REGISTERS

I
I

I
I

B-bil shift
register

J--

g

tz

/

J

~
I----I-----

--

IRa r-~
E. -

OW SYNC

~l~

8

8

I

microprocessor bus

ALL MSLO to 2

~ ~j .:.-J
L---

I

J

Generator

of 1.5 MHz clocks

4

~

12MH"->->-Z

_r.::J.....I:LC: r::L.J::L1:I .. "--1::I.Il
i_.t:1 .. r'1 noM M n n
~."
-w~g~~~w~

04 [ 10

a

OJ

AOM15

05 [ 11

AOMI4

06 [ 12

ADM13

07 [ 13

AOM12

08 [ 14

'"

09 [ 15

55

010 [ 16

53
52

Vss [ 19

Yl
YO

02

.1005

03
04

.1004
.1003
Al>Il2

05

D6

ADM!!

.1001

.1000

07
08

ADM10
ADM9

Dl1 ( 17

012 [ 18

DO
01

AlO6

D9

ADM8

'IOC

010

.....

ADCI

011

20

,.

ADM7

NC

AOM6

012

NC

21

49

ADM5

V55

AllIfi

013

22

48

ADM4

013

Al>I4

014

23

47

AOM3

014

015

24

46

AOM2

CS

25

55

26

51

....,

APe

ADM!
44

.100

os

ADMO

AlJI)

~

UK
P3
P2

At
A7

E88TS68483-0 1

Figure 1.1

A6
AS

PI

A4

iiii

A3

AD

A2

Al

PO

E88TS68483-02

Typical Application.

1"---

--------,

r---~~--~S~Y~NC~~

~~Sy-N~c~I---__~
I
MONITOR

I

I
I
I

I
I

I

L _____________ J

E88TS68483-03

2/41

172

TS68483

TABLE OF CONTENTS
1.

GENERAL OPERATION

2.

COMMANDS

3.

MICROPROCESSOR INTERFACE

4.

THE VIDEO TIMING GENERATOR RAM REFRESH AND DISPLAY PROCESS

5.

MEMORY ORGANIZATION

6.

TIMING DIAGRAM

7.

REGISTER MAP AND COMMAND TABLE

8.

ORDERING INFORMATION AND PACKAGE MECHANICAL DATA

~

...."

SGS-THOMSON

3/41

iIIlUl!:lIII@rnl!K'li'lII©OOUI:$

173

TS68483
1. GENERAL OPERATION
1.1. INTRODUCTION
The TS68483 is an advanced color graphics controller chip. It is directly compatible with most popular 8 or 16-bit microprocessors.
Its display memory, containing the frame buffer and
the character generators, may be assembled from
standard dynamic RAM components.

4/41

174

On-chip video shift registers and fully programmable Video Timing Generator allow the TS68483 to
be used in a wide range of terminals or computer
design.
Additional informations on applications can be
found in the TS68483 User's Manual.

TS68483
BLOCK DIAGRAM

MICROPROCE:.SSOR INTERFACE

/

r-~~--------~.~------------~,
AE, OS
'
Rfji f.S

0(015)

~4

AIO 7)

~8

A
16

t

,

g
RO

R4

R1

I
I

R2

I
I
I

R12

VSS

I
I
I
I

---+

BlK

I

R3

vee

elK

PC/HS

Rl0

HVS/IIS

I

VIDEO

R23

INTERFACE
VIDEO

-;::::=

~

SYNC IN

TIMING

GENERATOR

*'"
0
0

DRAWING

~

AND
ACCFSS
PROCESSOR

VIDEO

10-

SHiFf REGISTERS

21

~

DATA

.J.I

32

"

7

...>
....

DATA
32

DISPLAY MEMORY LOGIC

2

V

eys

7

3

2

V

' V7
y 102)

16

V

7

ADMIO.15)

~~----------------."r----------------'/
DISPLAY MEMORY INTERFACE

E88TS68483-04

5/41

175

TS68483
PIN DESCRIPTION
MICROPROCESSOR INTERFACE
Name

Pin Type

0(0: 15)

I/O

A (0: 7)

Function

Description

Data Bus

These sixteen bidirectional pins provide communication with
either an 8 or 16-bit host microprocessor data bus.

I

Address Bus

These eigth pins select the internal register to be accessed.
The address can be latched by AE for direct connection to
address/data multiplexed microprocessor busses.

AE

I

Address Enable

When TS68483 is connected to a non-multiplexed
microprocessor bus, this input must be wired to VCC.
For direct connection to a multiplexed microprocessor bus,
the fallin.9...§dge of AE latches the address on A (0 : 7) pins
and the CS input. With an Intel type microprocessor, AE is
connected to the processor Address Latch Enable (ALE)
signal.

OS

I

Data Strobe

Active Low
- In non-multiplexed bus mode, OS low enables the
bidirectionnal data buffers and latches the A (0 : 7) lines on
its high to low transition. Data to be written are latched on
the rising edge of this signal.
- In multiplexed bus mode, this signal low enables the
output data buffers during a read cycle. With intel
microprocessors, this pin is connected to the RD signal.

R/W

I

Read/Write

- In non-multiplexed bus mode, this signal controls the.
direction of data flow through the bidirectional data bufiers.
- In multiplexed bus mode, this signal low enables the input
data buffers. The entering data are latched on its rising
edg~ith Intel microprocessors, this pin is connected to
the WR signal.

CS

I

Chip Select

This input selects the TS68483 registers for the current bus
cycle. A low level corresponds to an asserted chip select.
In multiplexed mode, this input is strobed by AE.

IRQ

0

Interrupt Request

This active-low open drain output acts to interrupt the
microprocessor.

MEMORY INTERFACE
Name

Pin Type

Function

ADM (0: 15)

I/O

Address/Data Memory

These multiplexed pins act as address and data bus for
display memory interface.

CYS

0

Memory Cycle Start

The falling edge of this output indicates the beginning of a
memory cycle.

Y (0: 2)

0

Memory Address

These outputs provide the least significant bits of the Y
logical address.

B (0: 1)

0

Bank Number

These outputs provide the number of the memory bank to
be accessed during the current memory cycle.

CYF (0: 1)

0

Memory Cycle Status

These outputs indicate the nature of the current memory
cycle (Read, Write, Refresh, Display).

6/41

176

Description

TS68483
VIDEO INTERFACE
Name

Pin Type

P (0: 3)

0

Video Shift Register
Outputs

These four pins correspond to the outputs of the internal
video shift registers.

PC/HS

0

Phase Comparator/
Horizontal Sync.

This output can be programmed to provide either the phase
comparator output or the horizontal sync. signal.

HVSNS

0

Composite or Vertical
Sync.

This output can be programmed to provide either the
composite sync. signal or the vertical sync. signal.

SYNC IN

I

External Sync Input

This input receives an external composite sync. signal to
synchronize TS68483.
This input must be grounded if not used.

BlK

0

Blanking

This output provides the blanking interval information.

Function

Description

OTHER PINS
Name

Pin Type

VCC

S

Power Supply

+ 5 V Supply

VSS

S

Ground

Ground

ClK

I

Clock

Clock Input

Function

Description

1.2. TYPICAL APPLICATION BUILDING BLOCKS
In a typical using TS68483, a host processor drives
a display unit which drives in turn a color CRT monitor.
The display unit consists of four hardware building
blocks:
_ an TS68483 advanced graphics controller,
_ a display memory (dynamic RAM),
_ a display memory interface, comprising a few
TTL parts,
_ a CRT interface of CRT drivers.
For enhanced graphics, the CRT interface may include a color look-up table circuit such as EF9369.
For high pixel rate (over 18 Mpixels/s), the CRT interface must include high speed video shift registers.
The display memory interface and organization are
discussed in full details in the User's Manual.
1.3. TS68483 FUNCTIONS.
All the TS68483 functions are under the control of
the host microprocessor via 24 directly accessible
16-bit registers. These registers are referred to by
their decimal index (RO-R23). See figure 1.2.
1. Video timing and display processor (R4 to R10).

any popular horizontal scanning period from 20 !1S
to 64 !1S may be freely combined with any number
of lines per field (up to 1024). The address of the
display viewport (this part of the display memory to
be actually displayed on the screen) is fully programmable. The display processor provides the display
dynamic RAM refresh (see video timing generator
section for details).
2. Drawing and access commands (RO to R3, R12
to R23).
The 16 remaining registers are used to specify a
comprehensive set of commands. The highly orthogonal drawing command set allows the user to
"draw" in the display memory such basic pattems
as lines, arcs, polylines, polyarcs, rectangles and
characters. Efficient procedures are available for either area filling and tiling or line drawing and texturing. Lines may be drawn with a PEN in orderto get
thick strokes. Any drawing is specified in a 213 X 2 13
drawing coordinate system.
To access the display memory, the host microprocessor has an indirect, sequential access to any
"window". Access commands can be used to load
the character generators as well as to load or save
arbitrary windows stored in the frame buffer.

The video timing generator is fully programmable:

7/41

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TS68483
Figure 1.2. : Register Map.

8 7

15
RD
Rl

I
I

Sx

R2
R3
R4

I

R15

R16

R17
R18
RIg

Rn
R23

I

DWY

-

CONF

-

STATUS

I
I
Yd
Xd
DYd

I
I

R20
R21

8KY

8KX

I

VIDEO
TIMING
GENFRATOR

FPY

DWX

R13
R14

I

8PY

H

R9

R12

MARGIN COLOR

YOR

FPX

COMMAND, DRAWING ATTRIBUTES

I

TEXLIN

XOR

RI

Rll

CO
Cl

R6

RIO

MODE

Sy

R5

R8

D

COMMAND

DXc1
RAD
STOP

c1y

I

I

c1x

SHORT RELATIVE REGISTER

DESTINATION
POINTFR

I

I

AUXILIARY GFOMFTRIC
ARGUMENTS

Ys

I
I

Xs

I

DYs
DXs

SOURO
POINTER

I
E88TS68483-05

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TS68483
1.4. DATA TYPE DEFINITIONS.
PIXEL: this is the smallest color spot displayable on
the CRT.

VIEWPORT:
This is any rectangular array of pels located in the
display memory.

PEL: a Picture Element is the coding of a PIXEL in
the display memory. The TS68483 can handle 4 different PEL formats:
_ 4 color bits - short
_ 4 color bits + 1 mask bit - short masked
_ 8 color bits - long
_ 8 color bits + 1 mask bit - long masked

FRAME BUFFER:
This is the biggest viewport which can be held in the
display memory. The frame buffer maps a window
at the origin of the drawing coordinates. A short pel
frame buffer may be located in any bank. A long pel
frame buffer must be located in the "bank 0, bank 1"
pair.

DRAWING COORDINATES: (see figure 1.3).
The drawing commands are specified and computed in a2 13 x 213 cyclical coordinate system. The drawing coordinates are clipped and mapped into the
211 x 211 display memory addressing space. Further
clipping to the actual frame buffer size may be performed by the user designed memory interface.

DISPLAY VIEWPORT:
This is the viewport which is displayed on screen.
MASK BIT PLANE:
When masked pels are used, a mask bit plane must
be associated to a frame buffer. Mask bit planes may
be located in any plane of bank 3.

DISPLAY MEMORY:
This is the private memory dedicated to the display
unit. This memory is addressed as four banks of 4bit plane each.

CELL:
A CELL is any pattern stored in the display memory as a rectangular array of bit mapped elements.
The drawing of any CELL may be specified with a
scaling factor.

BIT PLANE:
Each bit plane has a maximu m capacity of 211 x 211
bits. A byte wide organization of each bit plane is required.

CHARACTER:
This is a one bit per element CELL. It may be stored
in any bit plane, then colored and drawn in a frame
buffer by use of PRINT CHARACTER command.

MEMORY ADDRESS: (see figure 1.4).
In order to address one bit in the display memory,
the user must specify:
_ A bank number (2 bits) B = 0 to 3
_ A bit plane number (2 bits) Z = 0 to 3
_ A Y address (11 bits) Y = 0 to 2047
_ An X address (11 bits) X = 0 to 2047

OBJECT:
This is a one short pel per element CELL. It may be
drawn or loaded in a frame buffer. A source mask
bit may be associated to each element. An OBJECT
may then be printed in another location by use of a
PRINT OBJECT command.

MEMORY WORD: (see figure 1.4).
A 32-bit memory word can be either read or written
during each memory cycle (8 CLK periods), one byte
at a time in each bit plane in the addressed bank.
The memory bandwidth is in the 6 to 8 Mbytes/s
range.

PEN:
This is the pattern which is repeatedly drawn along
the coordinates defined by either a LINE or an ARC
command.
The PEN may be a DOT (single pel), a CHARACTER or an OBJECT.

9/41

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TS68483
Figure 1.3. : Cyclical Drawing Coordinates to Display Memory Mapping.

Y

2" t - - r - - - - - - - - - - - ,

\

\

\

r~~SSK

M

2"r-----,
.

.,. ..- "

~
4

,,
,
2'3

7

,

L-_ _ _

5

..:;.L._.2~ ~
3

LONG PELS

SHORT PELS

,

\

\

E88TS68483·06

Figure 1.4. : The Display Memory Addressing Space.

BANK 0

THE MFMORY WORD

BANK 1

BI\NK /

8J\r\K

:~

" BANKS Of " I:3lf PI ANlS J-J\CH

E88TS68483-07

10/41

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TS68483
~.

COMMANDS

2.1. INTRODUCTION
The command set is strongly organized in five sub5et or command types.
DRAWING COMMANDS:
_ LINEAR (line, arc)
_ AREA (rectangle, trapezium, polygon, polyarc)
_ PRINT CELL (print character, print object)
ACCESS COMMANDS
CONTROL COMMANDS (move cursor, abort).
The commands are parametered; this means that
any command can be executed with options freely
selected out of a given option set. This option set is
common for any command of a given type. For
example, any drawing command may be parametered for destination mask bit use.
The command code also defines the command type
and its parameters. A command is completely defined when a value has been set for each of its arguments.

These arguments are:
_ the geometric arguments given in the drawing coordinate system for every drawing command.
They are automatically mapped into the destination frame buffer;
_ the parametric values are the values required by
the selected parameters ;
_ the attribute values are the other values required
by a drawing command; colors or scaling factors
for example ;
_ the display memory addresses.
The command code is specified in register RO. Before initiating a command execution, each argument
must be specified in its dedicated register: - an Xd,
Yd drawing coordinate pair for example, is always
located in registers R14, R15.
The monitoring of a command execution is done by
reading the status register R12 or using the IRQ signal.

Figure 2. 1. : Command Set Structure.
Command

Drawing Mode

Type

Line
Arc

Up to the Pen

Linear

Rectangle
Trapezium
Polygon
Polyarc

Monochrome

Area

Print Char
Print Object

Bichrome
Polychrome

Group

Drawing

Cell

Load Viewport
Save Viewport
Modify Viewport

Access

Move Cursor Abort

Control

2.2. POINTERS AND GEOMETRIC ARGUMENTS.
Pointers are used to specify main geometric arguments and display memory addresses.
2.2.1. Display Memory Address. A bit in the display memory is addressed by :
_ a bank number
B = 0 to 3
_ a plane number
Z = 0 to 3
_ an X address
X = 0 to 2047
_ a Y address
Y = 0 to 2047
2.2.2. Destination Pointer: Registers R14 to R17.
This pointer gives the coordinate (Xd, Yd) and di-

Management

mension (DXd, DYd) of either a line or a window in
the drawing coordinate system. These drawing coordinates are easily mapped into a PEL DISPLAY
MEMORY address.
(X, Y) coordinates are clipped to 11 bits in order to
get the Xd, Yd destination pel addresses.
A bank number Bd must be explicitly provided to address a destination frame buffer. When long pels are
used, Bd must be even.
When masked pels are used, the destination mask
plane number Zd (implicitly in bank 3) must also be
provided.

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TS68483
Figure 2.2.

15

R14

Pointers.

14

~
'-y---I

12

13

10

11

Yd

'\

~------------------~vr------------------~/
1 3-bll posllive vahJP

tlank number

Pel
iHicjrr'SS

R15

'\~---------------------,V
Plane number

/
Df-STJNATIO\l
POINTER

13 bit positiVe v;)lur:

R1B

I

DYd

V

/

Absulute value

R17~

DXd

J

~L,::::::~~::::::~:::::::::~:::::::::~:::::::::~_....L.._-'-_"-_.L-_'-....J
V
Absolute vulue

R20

R21

'~'~----~---v---------_J
For

TRA~IUM

cOrnMnd

SOURer
POINTeR

R22

Absolute value

R23

a

NOTE Sign value. S ~
POSitive
• S ~ 1 negative + absolute VilhH'!

E88TS68483-08

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TS68483
2.2.3. Source Pointer: Registers R20 to R23. A
:,ource cell such as a character, a pen or an object,
IS addressed by the source pointer in the display memory.
A source pointer specifies:
_ a bank number Bs = 0 to 3
_ a Ys address Ys = 0 to 2047
_ an Xs address; this address is a byte address so
that the 3 LSBs are not specified Xs = 0 to 255
_ a cell dimension DXs, DYs
_ a bit plane address Zs.
When a character is addressed, Zs gives the plane
number Into the bank Bs. When an object is addressed Zs gives the source mask plane number in the
bank B3.
2.2.4. Notes :
1. The TRAPEZIUM command makes a special use
of R21. In this case, R21 holds an X1 drawing coordinate which has the same format as Xd.
2. The ARC and POLYARC commands require two
extra geometric parameters (RAD and STOP).
They are specified in the drawing coordinates
system and stored in registers R18, R19.
3. Any drawing command may be parametered to
use short incremental dimensions, DXY in register R13 instead of the standard DXd, DYd in the
"R16, R17" register pair (see figure 2.3).
4. The access commands use the destination pointer location as a data buffer. The memory addresses and dimension of the access viewport
are then specified in the source pointer, independently of the data transfer.
5. DXd, DYd and DYs may specify a negative value. In this case, they must be coded by a sign
(0 = positive, 1 = negative) and an 11-bit absolute value.
Figure 2.3. : Short Dimension Register R13.

4

R131 s

o

3

I I I IsI I I I

~~
dy

dx, dy

~

dx

- 7 to + 7 (sign + absolute value)
E88TS68483-09

2.3. DESTINATION MASK AND SOURCE MASK.
A mask bit may be associated to any pel stored in
the display memory.
2.3.1. Destination Mask Use (DMU). Any drawing
command may be parametered for destination
mask use. In this case, any destination pel cannot
be modified when its mask bit is reset.
In other words:
When the destination mask use (DMU) parameter
is set:
_ a pel may be modified when its mask bit is set
_ a pel cannot be modified when its mask bit is reset.
When the destination mask use (DMU) parameter
is cleared:
_ a pel may be modified, independently of its mask
bit value.
This provides a very flexible clipping mechanism not
restricted to rectangular windows. (See destination
pointer section for destination mask bit addressing).
2.3.2. Source Mask Use (SMU), A PRINT OBJECT
command may be parametered for source mask
use. In this case, the source mask bit associated
with any source pel is read first. When its mask bit
is cleared, a source pel is considered as transparent. (See source pointer section for source mask
bit addressing).
In other words:
When the SMU parameter is set, the color of a destination pel, mapped by a given source pel, may take
this source color value only when this source bit
mask is set. The destination pel keeps its own color
value when the source bit mask is cleared.
When the SMU parameter is cleared, a source pel
color may be mapped into destination pel color independently of the source bit mask value.
The source bit mask acts as a TRANSPARENCY/OPACITY flag which is enabled by SMU. A
PRINT OBJECT command may be independently
parametered by both SMU and DMU. This provides
a very powerful tiling, print object or move mechanism.
2.4. DRAWING ATTRIBUTES.
The general drawing attributes are the colors, the
drawing mode, and the scaling factor.
2.4.1. Colors : Registers R1 and R2 (see figure 2 .4.). Two a-bit color values, CO and C1, may be
specified in registers R1 and R2. The low order 4-

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TS68483
bit nibble of a color value is drawn in an even bank.
The high order color nibble is drawn in an odd bank.
When long pels are used, banks 0 and 1 are generally addressed as the frame buffer. When short pels
are used, any bank may hold a frame buffer. In this
case, the bank parity selects the color nibble used.
(See destination pointer section for bank addressing).
Figure 2.4. : Color Register.

I I I' I I I I I I
I

6

4

3

2

1

RI R2

0

E88TS68483-10

2.4.2. Drawing Mode: Register RO. The drawing
mode defines the transforms to be applied to the
pels designated by the drawing commands. There
are three drawing modes.
2.4.3. Monochrome Mode. Any AREA drawing
command, RECTANGLE for instance, defines
through its geometric arguments an active set of
destination pels, that is to say a set of pels to be modified.
When DMU = 1, this active set is further reduced by
the masking mechanism to only these destination
pels with a bit mask set.
The active destination pels are then modified according to two elementary transforms coded in RO.

COLOR TRANSFORM:
The color value C of each active pel is modified according to one color transform selected out of four:
_ 00 - printed in CO : C ~ CO
_ 01 - printed in C1 : C ~ C1
_ 10 - printed in "transparent" : C~ C
_ 11 - complemented : C~ C
This yields to a reversible marker mode.
MASK BIT TRANSFORM:
The destination mask bit of each active pel is modified according to one mask transform selected out
of four :
_ 00 - reset bit mask: M ~ 0
_ 01 - set bit mask: M ~ 1
_ 10 - no modification: M ~ M
_ 11 - complement bit mask: M ~ M
This scheme allows the color bits and the mask bit
of any pel belonging to the active set to be modified
independently. The color transform is performed
first.
2.4.4. Bichrome Mode. A PRINT CHARACTER
command is more complex because it involves two
different active sets: FOREGROUND and BACK
GROUND.
The FOREGROUND is that set of destination pels
printed from set elements in the character cell. The
BACKGROUND is made of all the remaining pels
belonging to the destination window.
When DMU = 1, the FOREGROUND and BACK
GROUND are further reduced by the destination
masking mechanism. (see figure 2.6).

A bichrome drawing mode is defined by 4 elementary and independent transforms: (see figure 2.5)
_ a color transform
_ a mask transform

For the FOREGROUND PELS

_ a color transform
_ a mask transform

For the BACKGROUND PELS

Figure 2.5. : Drawing Mode RegisterRO.
BACKGROUND

FOREGROUND

~
f

I

I

I

BACKGROUND

REGISTER RO

TTI{ooc.co
I co~ HEr
L -_ _ _ _

~---"'M::::AS"'-K-

__

{~~: ~: t
11.M---r:;J

14/41

184

rOREGROlJND

~~
o

6

I

I

I

-

-

I

x

x

x

x

x

x

x

x

x

x

x

X

1

0

-

-

1

0

-

-

Monochrome

Polychrome

E88TS68483-11

TS68483
Figure 2.6. : Print Character Command.
DESTINATION WINDOW

(Xd. Yd)

[)xd

CHARACTER CELL

>a

Sf-T f-I FMFNT

(Xs. Ys!

DYs

1

<0
_.,..-~lLLMLNr ~

()

MASK IllT -= 1

MASK Hil

= ()

E88TS68483·12

E88TS68483·13

MAPPED CHARACTER WINDOW

MAPPED CHARACTER WINDOW
(Xd. Yd)

__

/
-.-.
I

~J

-~

__

Xd

I
I

I

~

I

I

I

I

I

_J

_J

~--- FOREGROUND

BACKGROUND

DMU -" 0

E88TS68483·14

2.4.5. Polychrome Mode. A print object command
defines a source window through the source pointer :

2.4.6. The Linear Drawing Command Case. A
LINE or ARC drawing command may be executed
in any drawing mode depending on the PEN.

When SMU = 0, any pel of this window is active,
mapped and clipped to the destination window dimension.

When the pen is a DOT, this pel is printed at each
active coordinate according to monochrome mode.

When SMU = 1, only pels which have a source mask
bit set are active, mapped and clipped to the destination window dimension.
In both cases, when DMU = 1, the active source pels
are further reduced by the destination masking mechanism.
Both mask transforms must be programmed at "NO
MODIFICATION" for correct operations. (see figure 2.5).

When the pen is a CELL, this cell is printed at each
active coordinate. In the bichrome mode when the
cell is a character, and in the polychrome mode
when the cell is an object.
For each active coordinates, the active destination
set is defined by the cell dimensions (DXs, DYs).
Note : when the cell is an object, SMU is not programmable and is implicitly set. A calculated coordinate is active when the rotated LSB linear texture
bit in (R3) is set.
15/41

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TS68483
2.4.7. Scaling Factor and Cell Mapping: (see figure 2.7 and 2.8). Any cell may be printed with a
scaling factor.

CESS or LINEAR (DOT) commands are never scaled.
The LINEAR (PEN) command should be used with
a scaling factor of 1 because the pen is clipped at
DXs, DYs.
The scaling factor is first applied to the source cell
before mapping and drawing. The drawing and
mapping is processed with sign bit of DYd and DYs
values. (see figure 2.8).

This scaling factor is an integer pair Sx, Sy = 1 to

16.
This scaling factor is interpreted with the PRINT
CHARACTER, PRINT OBJECT and LINEAR commands when the pen is a cell. The AREA or ACFigure 2.7. : Scaling Factor.
15

R1LI__

14

13

12

11

10

~_s~:__~~__~~S~Y~~~

SX or SY

S

0001

1

0010

2

I
I
I

I
I

1111

I
1 :)

0000

16

E88TS68483-15

Figure 2.8. : Cell Mapping Versus DYd, DYs SIGN.

Xd Yd

DYd

>a

-'L--~~

I

DYd0

Xd. Yd

DXd

>

ox::, > 0

r
DXd

f-

>0
I

i

- - - -l

0

--,

- - - - -...... x

I
I
I
I
Xd. Yd

DXd

DYd< 0

>0

E88TS68483-16

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TS68483
Note:
_ DXs is always positive
_ The DYs sign mirrors the cell
_ DXd must be positive with a PRINT CELL command
_ DXd and DYd may get any sign with a LINEAR
DRAWING command. If a pen is used, these
signs are then irrelevant to the pen drawing. The
pen is mapped with positive increment values.

When dXd, dYd is much larger than DXs, DYs the
command may be parametered for repeat drawing.
These commands may also be parametered for
destination mask use.
Further more the PRINT OBJECT command may
be parametered for source mask use.
These commands have a wide range of applications: text drawing, area tiling, print or move objects, scale and move viewports.
Note: an underlined cell is drawn when the MSB of
R23 is set.
2.5.4. Access Commands.
_ LOAD VIEWPORT (Xs, Ys, DXs, DYs)
_ SAVE VIEWPORT (Xs, Ys, DXs, DYs)
_ MODIFY VIEWPORT (Xs, Ys, DXs, DYs)

E88TS68483-17

2.5. COMMAND SET OVERWIEW
2.5.1. Linear Drawing. LINE (Xd, Yd, DXd, DYd).
ARC (Xd, Yd, DXd, DYd, RAD, STOP).
The curve may be drawn with any pen and with any
linear texture (register R3). For each set of computed coordinates, R3 is right rotated and the pen is
printed when the shifted bit is set.
2.5.2. Area Drawing.
_ RECT (Xd, Yd, DXd, DYd)
_ TRAPEZIUM (Xd, Yd, DXd, DYd, X1)
_ POLYGON (Xd, Yd, DXd, DYd)
_ POL YARC (Xd, Yd, DXd, DYd, RAD, STOP)
Either RECT or TRAPEZIUM allows to draw directly all the pels inside the boundary.
Any other closed boundaries may be filled by a 3step process:
1. The mask bits inside a boundary box must be reset by a RECT command.
2. A sequence of mixed POLYGON and POLYARC
commands describing the closed boundary sets the
mask bits of the pels inside this boundary.
3. This area may then be painted by a RECTANGLE
command defined for a bounding box, with destination masking. It may also be tiled by use of a PRINT
CELL command.
Note: the mask bit of any pel lying on the boundary itself is not guaranteed to be set by step 2.
2.5.3. Print Cell Commands. PRINT CELL (Xd, Yd,
DXd, DYd ; Xs, Ys, DXs, DYs).
The cell addressed by Xs, Ys, DXs, DYs is scaled
then printed at location Xd, Yd and clipped at the
dXd, dYd dimensions.

These commands provide sequential access to a
viewport in a frame buffer from the microprocessor
data base.
Data are transferred to/from the display memory,
word sequentially.
The R14 to R17 registers are used as a two memory word FIFO (memory word is 8 short pels, i.e. 4
bytes).
The source pointer (R20-R23) is used to address
the viewport for all access commands.
When long pels are used, the command must be
executed once more when the bank number in R20
has been updated.
2.5.5. Command Execution. Each on-chip 16-bit
register has four addresses. One address is used
for plain read or write. The other addresses are used
to initiate command execution automatically on
completion of the register access.
This scheme allows the command code and its arguments to be loaded or modified in any other. An
incremental line drawing command, for example,
may be executed again and again with successive
incremental dimensions and whithout need to reload the command code itself.
As soon as a command execution is started, the
FREE bit is cleared in the STATUS register. This bit
is automatically set when the execution is completed.
The commands are generally executed only during
retrace intervals. However full time execution is possible when either the display is disabled or video
RAM components are used.

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TS68483
2.5.6. Status Register (see figure 2.9). This register holds four read-only status bits:
_ FREE: this status bit is set when no execution is
pending
_ VS : vertical synchronization state
_ SEM : this status bit is set when the FIFO memory word is inacessible to the microprocessor du-

ring a viewport transfer
_ NSEM : this status bit is set when the FIFO memory word is accessible to the microprocessor
during a viewport transfer.
Each of these status bits is maskable. The masked
status bits are NORed to the IRQ output pin.

Figure 2.9. : Status Register.

STATUS REGISTER H12
L - _....~
L.-----li~

L-------t-.
L -_ _ _ _ _ _ _

L -_ _ _ _ _ _ _ _ _

~~

~~

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

MASKSEM
SEM
MASKVS

READ ONLY

VS
MASK FREE

~

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _

---I~

MASK NSEM
NSE M

~

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....

FREE

R12

E88TS68483-18

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T568483
3. MICROPROCESSOR INTERFACE
3.1. INTRODUCTION
The TS68483 is directly compatible with any popular 8 or 16-bit host microprocessor; either Motorola type (6809, 68008, 68000) or Intel type (8088,
8086).

_ A(l :5) select one out of 24 registers.
_ AO selects the low order by1e (AO ; 1) or the high
order byte (AO =0) of the selected register.
_ A(6 :7) provide the command execution condition.

The host microprocessor has direct access to any
of the twenty four 16-bit on-chip registers through
the microprocessor interface pins :
_ 0(0:15) : 16 bidirectional data pins.
- ~:ZL 8 aI

O{O:7IK:=========~>I

. A{1:71l==========::::::>1

TS68000

TS68483
E88TS68483-20

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TS68483
Figure 3.4. : Interface with TS68000/68008 MPU (continued).

AIO 7)

t============!":>1

TS68008
. TS68483

E88TS68483-21

Figure 3.5. : Interface with 8086/8088 MPU.

8

8086
TS68483

E88TS68483-22

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TS68483
Figure 3.5. : Interface with 8086/8088 MPU (continued).

8
IIlf

cs
flS

flD

H/W

WR

8088
TS68483
E88TS68483-23

4. THE VIDEO TIMING GENERATOR RAM REFRESH AND DISPLAY PROCESS
4.1. INTRODUCTION
The Video Timing Generator is completely synchronous with the ClK input, which provides a pixel shift
frequency (up to 18 MHz). The Video Timing Generator:
_ delivers the blanking signal (BlK), the horizontal
(HS) and vertical (VS) synchronization signals on
respective output pins,
_ schedules the memory time allocated to the display process, dynamic RAM refresh and command execution,
_ is fully programmable
_ can be synchronized with an external composite
video sync signal connected to the SYNC IN input:
4.2. SCAN PARAMETERS (see table 1 and timing diagram 5)

4.2.1. Timing Units. The time unit of any vertical
parameter is the scan line.
The time unit of any horizontal parameter is the memory cycle, which is 8 periods of the ClK input signal.

22/41

192

These two parameters are internally programmed:
_ Horizontal sync pulse duration = 7 cycles
_ Vertical sync pulse duration = 2.5 lines.

4.2.2 Blanking Interval. The blanking interval
starts:
_ at the leading edge of the vertical sync pulse. Vertical blanking interval actual duration is 2.5 lines
more than the programmed value.
_ two cycles before the leading edge of the horizontal sync pulse. The actual horizontal blanking interval duration is 3 cycles more than the programmed value.

Note: During the programmed blanking interval, the
video output pins P(0:3) are forced low.
4.2.3. Porch and Margin Color. During the porch
interval, the programmable margin color is displayed on the P(0:3) outputs.
The display process may be disabled by setting
DPD flag. This will be interpreted as a porch extension.

"T1
cOo
I:

+F1
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't
-+TL

i-IQRIZOr-.TAl

7T

I

.j2T

3T

"I

2H

BKX

BLANK,NG

-1
~ FPX

---l:

iiJ
~

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<

r--

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01 BACK PORCH

L

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oJ
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spy
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en
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TS68483
4.2.4. Memory Time Sharing (see figure 4.1). The
Video Timing Generator allocates memory cycles to
either the display process, RAM refresh or command execution. In this respect, the scan lines per
field are split between :
_ the DWY displayable lines.
When VRE = 0, Video RAMs are not used.
The DWY x DWX cycles in the display interval are
allocated to the display process when it is enabled
(DPD = 0). When the display process is disabled,
these cycles are allocated as for non displayable
lines.
When VRE = 1, one cycle per display line is allocated to the display process. Other cycles are allocated as for non displayable lines. The last period of
the BLKX signal may be used to load the internal video RAM shift register.
_ the non displayable lines. In one out of nine non
displayable lines, DWX cycles are allocated to the
refresh process when it is enabled (RFD = 0).
_ In Float cycle, an external X address must be provided. The Y address is still provided on ADM(0:7)
and Y(0:2), while ADM(8:15) are in high impedance state.

4.2.5. Command Access Ratio. This allocation
scheme leaves about 50 % of the memory bandwidth for command access when programming a
standard TV scan. This ratio drops to the 30 % range
when a better monitor is in use (32 !JS out of 43 !!s
displayable per line, 360 lines out of 390 for a 60 Hz
field rate). The higher resolution means more memory accesses in order to edit a given percentage
of the screen area. In this case Video RAMs are very helpful to keep 90 % of the memory bandwidth
available for command access.
4.3. DISPLAY PROCESS
The Video Timing Generator allocates memory cycles to the Display Processor in order to read the
Display Viewport from memory. The Display Viewport upper left corner address is programmable
through DIB, YOR and XOR. The display viewport
dimensions are related to the display interval of
DWY lines by DWX cycles per field.

4.3.1. Y Addresses. When INE = 0, the fields are
not interlaced. The Y Display Viewport address is

initialized with YOR at the first displayable line then
decremented by 1 at each scan line. The Display
Viewport is thus DWY pel high.
When INE = 1, the fields are interlaced. The Y Display Viewport address is initialized as shown in the
table below. It is then decremented by two at each
scan line. The viewport is thus 2 x DWY pel high.

Vor Even
Vor Odd

Even Field
Vor
Vor - 1

Odd Field
Vor + 1
Vor

= 1.
4.3.2. X Addresses and MODX Flags. The X Dis-

Y Display Viewport address initialization when INE

play Viewport address is initialized with XOR at the
first displayable cycle of each displayable line. It is
then incremented at each subsequent cycle according to MODX flags.(see table 4.3.2)
_ In internal mode, the Display Viewport is 8. DWX
pel wide. The on-chip video shift register are
used.
_ In Dummy read, the memory is read but the onchip video shift registers are not loaded, instead
they retain their margin color. External video shift
registers are presumed to be loaded by either 8
pels or 16 pels per cycle according to the programmed increment value.
_ In Float cycle, an external X address must be provided. The Y address is still provided on ADM(0:7)
and Y(0:2), while ADM(8:15) are in high impedance state.
Note : See Memory Organization and Memory Timing for further details on the memory cycles.

4.3.3. The Video RAM Case (VRE = 1). In this case,
the last cycle of the horizontal blanking interval is
systematically allocated to the display process for
DWY scan lines per field.
This cycle bears the scan line address, the bank
number and the X address which is always XOR.
MODX must be programmed to use external shift
register (Dummy read).

4.3.4. PAN and TILT. The host can tilt or pan the
Display Viewport through the frame buffer by modifying YOR or XOR arguments. Panning is performed on 8 pel boundaries.

Table: 4.3.2.
MODX1

MODXO

XINCR

0

0

+ 1

24/41

194

0

1

+ 1

1

0

+2

1

1

Video Shift Register
Internal
External
External
External

Memory Cycle Type
Read
Dummy Read
Dummy Read
Float

TS68483
4.4. DYNAMIC RAM REFRESH
No memory cycles are explicity allocated to the RAM
refresh when RFD = 1.
When VRE = 0 and DPD = 0, the Display Process
is supposed to be able to over-refresh dynamic components. This can be done by careful logical to component address mapping. During the remaining non
displayable lines, the Display Viewport address
continues to be incremented : Y address on each
line according to INE, X address initialized by XOR
then incremented according to MODX. This Display
viewport address is allowed to address the memory for DWX cycles in only one line out of nine for refresh purposes.
When VRE = 1 or DPD = 1, any line is processed
as a non displayable line with respect to the refresh
process.
4.5. CONFIGURATION AND EXTERNAL SYNCHRONIZATION

_ NPC, NHVS, NBlK : these three flags invert the
PC/HS, HVS/vS and BlK outputs respectively.
(Ex. : When NBlK = 1 blanking is active high).
The SYNC IN input pin provides an extemal composite synchronization signal input from which a
Vertical Sync In (VSI) signal is extracted. The SYNC
IN signal is sampled on-chip at ClK frequency. Its
rising sampled edge is compared to the leading
edge of HS. A PC comparison signal is externally
available (see SSP and NPC flags).
VSIE : this flag enables VSI to reset the internal line
count.
HSIE : this flag enables the rising edge of SYNC IN
to act directly on the Video Timing Generator. When
the leading edge of HS does not match at 1 clock
period a rising edge of SYNC IN, one extended cycle is performed (nine clock periods instead of
eight).

The R10 register holds eight configuration flags. Six
of these flags are dedicated to the Video Timing Generator.
_ SSP: this flag selects the synchronization output
pin configuration:

Output Pins
Flag

PC/HS

HVSIVS

SSP = 1

HS

VS

SSP =0

PC

HVS

Table 1.
Name

Number
of Bits

Mininmum
Values

Register

DWY

10

1

R9

INE

1

BKY

5

FPY

5

BPY
H

Description
Number of Display lines per Field

R8

Interlace Enable when INE = 1

1

R8

Number of Lines in Vertical Blanking - 2.5

1

R7

Number of Lines in Vertical Front Porch

8

3

R6

Number of Lines in Vertical Back Porch + 2.5

6

19

R6

Number of Double Cycles per Line

FPX

4

3

R8

Number of Cycles in Horizontal Front Porch

BKX

4

4

R8

Number of Cycles in Horizontal Blanking - 3

DWX

7

3

R7

Number of Cycles of the Display Window

XOR

8

R4

YOR

11

R5

DIB

2

R4

X, Y, and bank logical address in the display
memory of the display viewport upper left
corner

MODX

2

R9

Selection of the X Addressing Mode

MC

4

R4

Margin Color

RFD

1

R7

RAM Refresh Disable when RFD = 1

DPD

1

R7

Display Process Disable when DPD = 1

1

R8

Video RAM Enable When VRE = 1

VRE
Note: one cycle

=

Function

Vertical Scan

Horizontal
Scan

Display
Process

Memory Time
Sharing

8 periods of ClK Clock.

25/41

195

TS68483
5. MEMORY ORGANIZATION
5.1. INTRODUCTION

5.3. DISPLAY MEMORY DESING OVERVIEW

The display memory is logically organized as four
banks of 4-bit planes. Thus a bit address in the display memory is given by the quadruplet:
_ B = bank number, from 0 to 3
_ Z = plane number, from 0 to 3
_ X = bit address into the plane, from 0 to 2047
_ Y = bit address into the plane, from 0 to 2047.

The display memory implementation is application
dependant. The basic parameters are:
_ the number of pixels to be displayed Nx.Ny
_ the number of bits per pel
_ the vertical scanning frequency, which must be
picked in the 40 Hz to 80 Hz range (non interlaced) or in the 60 Hz to 80 Hz range (interlaced).

In one memory cycle (8 ClK periods), the controller can access a memory word. This 32-bit memory word holds one byte from each plane in a given
bank. In order to address this memory word, the
controller supplies:
_ B(0:1) : binary value of the bank number
_ X(3:1 0) : binary value of the word address
_ Y(0:1 0) : binary value of the word address.

This yields a rough estimate of the pixel frequency.
When the pixel frequency is in the 15 to 18 MHz
range and 4 bits per pixel or least are required, the
on-chip video registers and standard dynamic RAM
components may be used. When higher pixel rates
or up to 8 bits per pixel are required, the designer
must provide external shift registers. Video RAM
components may also be considered.

Z and X(0:2) are not supplied. They give only a bit
address in a memory word.

In either case, the user must design:
_ A memory block. This is the hardware memory
building block. It includes the video shift registers
if on-chip VSR cannot be used. It implies a RAM
component choice.
_ An Address Mapper, which maps the logical address into hardware address : block selection,
Row Address (RAD), Column Address (CAD).
_ A memory cycle controller. This controller monitors the CYF and CYS output pins from TS68483
and block address from the Mapper. It provides:
• The ClK signal to the TS68483 and a shift clock
SClK when external video shift registers are
used
• RAS, CAS, OE, RI W signals to the memory
blocks
• RAD and CAD Enable signals to the Mapper.

5.2. MEMORY CYCLES
24 pins are dedicated to the memory interface.
_ ADM(0:15) : these 16 bidirectional pins are mUltiplexed three times during a memory cycle (see
Timing Diagram 3) :
TA : address period. Output of the X(3:11) and
Y(3:11) address
TO : even data period. The even Z bytes are either
input or output.
T1 : odd data period. The odd Z bytes are either input or output.
_ Y(0:2) : three lSB Y address output pins (nonmultiplexed)
_ B(0:1) : two bank address output pins (non-multiplexed)
_ CYS : Cycle start strobe output (non-multiplexed).
CYS is at ClK/8 frequency. A CYS pulse is delivered only when a command, display or refresh cycle
is performed.
_ CYF(0:1) : Two cycle status outputs (non-multiplexed). Four cycle types are defined:
Command read
Command write
RAM refresh
Display access.
Because several options may be selected for RAM
refresh and display access by the MODX and VRE
flags (see Video Timing Section), there are more
than four memory cycle types (see Timing Diagram 3 and table 2).

26/41

196

5.3.1. Frame Buffer (see figure 5.1.). A byte wide
organization of each bit plane is required. Obviously a bit plane must contain the Display Viewport size.
A straight organization implements only one bit
plane per block.
It may be cost effective to implement several bit
planes per block. Two basic schemes may be used:
_ One block, one Z : several bit planes, belonging
to different banks, but addressed by the same Z,
share a given block. There is little time constraint
if any.
_ One block, two Z : two bit planes, belonging to the
same bank share a given block. In this case, this
block must be accessed twice during a memory
cycle. This can be solved by two successive page
mode accesses.

5.3.2. Masking Planes. Masking planes are very
useful for general purpose area filling or clipping. It

TS68483
ONE BLOCK-ONE Z

ADMIO Ii

ADMIS1"1

!!(101

81TOI

BO---.

B2---.

13

11

17

10

E88TS68483-25

ONE BLOCK-TWO Z

ADM (8 15)

ADM (0 71

8

8

(TO T1) - Page rnode

l3

Z2

Il

IO
E88TS684B3-26

27/41

197

TS68483
Figure 5.1. : Frame Buffer Organization.
16 k x 8

32 k x 8

64 k x 8

256 k x 8

One Block-one Bit Planes

512 x 256

512 x 512

1024x512

2048 x 1024

One Block-two Bit Planes

256 x 256

512 x 256

512 x 512

Typical Block Size

COMPONENTS:
64K BITS: 16K x 4 or 64K x 1
256K BITS: 32K x 8. 64K x 4. 256K x 1
VIDEO RAM: 64K x 1. 64K x 4

Table 2 : Memory Cycle Types.
Modx
Flags
1
0

Output Pins
Function

Cycle Type

TA

TO

T1

Command Read

V,X

ZO,Z2

ZI,Z3

Read

Command Write

V,X

ZO,Z2

Zl,Z3

Write

0
1

V,X
V,X

ZO,Z2

Z1,Z3

Read
Dummy Read + 1

0
1

V,X
V,Hi-Z

CYF1

CYFO

1

0

1

1

0

1

Display

0
0

0

0

Refresh

1
1

Refresh: dummy read cycle

Multiplexed ADM

IS

Dummy Read + 2
Float X

performed.

A MFMOAY WORO

/

X'D 21

E88TS68483-27

Figure 5.2. : The Multiplexing Scheme.
HIGHER BYTES
ADMS Multiplexed Pins

15

I

14

I

13

I

12

I

11

I

10

I

9

I

X

8

TA : Address Period

10

TO : Even Z Byte Period

7

Z =2

3
0

Tl : Odd Z Byte Period

7

Z =3

0

LOWER BYTES
ADMS Multiplexed Pins

7

I

6

I

5

J

4

1

3

I

2

I

1

I

0

TA : Address Period

10

TO : Even Z Byte Period

7

Z =0

0

T1 : Odd Z Byte Period

7

Z=1

0

28/41

198

V

3

TS68483
may be practical to use one or two planes smaller
than the color bit plane if they cyclically cover a
frame buffer.

5.4. EXAMPLES
Figure 5.3. gives the schematic for a 512 x 384 non
interlaced application. A ClK signal in the 15 to 18
MHz range should produce a 50 to 60 Hz refresh
rate. The on-chip video shift registers may be used
if no more than four bits per pixel are required. One
64 K x 8 memory block may be implemented using
either eight 64 K x 1 or two 64 K x 4 components.
One memory block holds two 512 x 384 color bit
planes.

The masking planes must be in bank 3.
5.3.3. Objects and Characters. Objects may be located in unused parts of the frame buffer.
Character generators can be implemented in any
plane of any bank. They can also be implemented
in ROM. In this case, plane Z = 1 or 3 offer relaxed
access time requirements.

Figure 5.3. : Memory Organization for 512 x 384 Application.

BIO 1)

ADM(S 151

Y(O 2}

AOMIO l)

r~'l~
I

I

I

I

I x
I

BANK !:NABLE
CADO

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::L
I:
LATCH

MUX

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CYCLE CONTROLLER

.
~

1
OATA

64K

x8

DATA
lOil7

8

Zl/Z3

Ie-"==:
===='"
MEMORY

64K x 8

ADDRESS

tt

HAS

1

CAS

tj

DE
WE

E88TS68483·28

"~'" 1'

71 + 2

1

64K x 8 ME MORY BLOCK

384

2 BI T MAP PLANE

____ ONE BLOCK THROUGH PAGE MODE
'28

BANK 3 {

}

SPARED ARFA

.

!4----512

E88TS68483-29

29/41

199

TS68483
6. TIMING DIAGRAM
6.1. MICROPROCESSOR INTERFACE
TS68483 has an eight bit address bus and a sixteen
bit data bus. Little external logic is needed to adapt
bus control signals from most of the common multiplexed or non-multiplexed bus microprocessors.

Vee = 5.0 V ± 5 %, TA = TL to TH, CL = 100 pF on
0(0:15)
Reference levels: VIL
inputs

= 0.8 V and VIH = 2 V on

all

VOL = 0.4 V and VOH = 2.4 V on all outputs

MicrQQl:ocessor J!)terface timing : A(0:7), 0(0:15),
AE, OS, CS, R! W

UNMUX MODE
Id.
Numb.

Parameter

1
2
3

Address Set up Time from CS

4

Data Strobe Width-low (read cycle)

5
6

Address Hold Time from DS

7

DS Inactive to High Impedance State (read cycle)

8

R/W Set up Time from DS

9

DS Width-low (write cycle)

10
11
12

CS Set up Time from DS Active (write Cycle)

30141

200

Data Strobe Width (high)
AS Set up Time from CS

Min.

0
65
0
160
0

Data Access time from CS (read cycle)

Data in Set up Time from DS active (write cycle)
Data in Hold Time from DS Inactive (write cycle)

Max.

10
20
80
0
10
15

Unit
ns
ns
ns
ns
ns

130
80

ns
ns
ns
ns
ns
ns
ns

TS68483
UNMUX MODE
READ CYCLE

AID I)

AS IMPU)

eli

......

------~f-

us

~-+--CD------~
R(VII

------I

DATA OUT
01015)

E88TS68483-30

WRITE CYCLE

AIDI) - - - ( I

AS

IMPU)

E -------------_

os

'~------,CD------~~~--~

R~ ---------~

DATA IN
01015)

E88TS68483-31

31/41

201
----

--- --

-------

TS68483
MUX MODE
Microprocessor Interface Timing: A (0: 7), 0 (0: 15), AE, OS, CS, RiW
Vee = 5.0 V ± 5 %, TA = T l to T H, C l = 100 pF on 0 (0 : 15)
Reference levels: V 1l = 0.8 V and V 1H = 2 V on All Inputs
Val = 0.4 V and VOH = 2.4 V on All Outputs
Id.
Numb.

Parameter

Min.

Max.

Unit

1

AE Width High

90

2

Address Set up Time to AE Inactive

55

ns

3

Address and CS Hold Time to AE Inactive

55

ns

ns

4

CS Set up Time to AE Inactive

40

ns

5

DS and RfW High

150

ns

6

DS Width-low (read)

240

ns

7

R/W Width-low (write)

110

8

Data Access Time From DS (read)

9

Data in Set up time from R/W Inactive (write)

150

10

DS Inactive to High Impedance State (read)

10

ns
210

ns

100

ns

ns

11

Data in Hold Time from RfW Inactive (write)

30

ns

12

AE Inactive to DS Active

20

ns

13

AE Inactive to R/W Active

20

ns

14

DS Inactive to AE Active

10

ns

15

RfW Inactive to AE Active

10

ns

16

R/W Inactive to Next Address Valid

100

ns

17

DS Inactive to Next Address Active

100

ns

18

Data in Set up Time from RfW Active (fast write cycle)

10

ns

6.2. MEMORY INTERFACE
ADM (0 : 15), B (0: 1), CYF (0: 1), Y (0: 2), CYS
Vec = 5.0 V±5%, TA = Tl to TH
ClK Duty Cycle = 50 %, Period T
Reference levels: V 1l = 0.8 V and V 1H = 2 V, Val = 0.4 V and VOH = 2.4 V
Indent
Number

Parameter

TS68483·18

Min.

Max.

Min.

Max.

66

166

55

166

Unit

1

TClK Clock Period

2

Memory Cycle Time (T = 8 X TClK)

3

Output Delay Time from ClK

40

35

ns

4

Output Data HI-Z Time from ClK

40

35

ns

5

Output Hold Time from ClK

10

10

ns

6

Input Data Hold Time from ClK (read cycle)

10

6

ns

7

Input Data Set up Time from ClK (read cycle)

20

10

8

Input Data HI-Z Time from ClK

Note: All timing is referenced to the rising edge of elK (see timing diagram 3).

32/41

202

TS68483·15

ns
ns

TClK

ns
TClK

ns

TS68483

MUX MODE
READ CYCLE

AE

cs
6s

CD
RtW

@

AID

E88TS68483-32

WRITE CYCLE

AE _ _ _ _oJ

~ -------~

os
A/W -+---------+----~

11.14---

AiD

-------<

FAST WRITE

E88TS68483-33

~ SGS·1HOMSON
At..,
I !il,j]D©IRI@~~IWii'IiI©IllD©®

33/41

203

I\)

o
.J:lo.

I "'
W

~

ClK

--1fL]--Lr----LrU~rL"LJ~ rL
. 1f5'r-

~ 0~

~

CYS

~

B(O

CYF

/

r-- ----- r.\
\

'x'
/\
~1-0 ~

.~

""0
@.

"

./

~

/

'I
~

AD

WR

(015)

~

CyCLE

Ei!
~O

~

0

~0

fc

A(XY)

AD
REA

(0151
CYCLE

Du

1Y READ CYCLE

./

~

I.DMfO 15)

./
'I

A(XYI

1--(7)-- bfc
1'-"--

A(XY)

~

"
DI
FLO

C

ADVIO 7)

AY
I~G

_E

---ADM,9 ·51

----

./
'I

-

,,
;

...J

A(Y)

I"-

./

It'

'"

I\.
1/

0- foe

D

r-

I)

D(EVEN ZI

• CDi-C

ill!:

~IS
Ilz

Z
-I

m
::D
"T1

l>

m

I

Y(O

-<

o

0'"

J

11

s:
s:
o
::D

m

>-<
..10. .

D(EVEN Z)

"I-®~

~
D(ODD Z)

~(7)D(ODD Z)

I"-

V

"0~

. .. ®f.o

0

-I

(IJ

Ol

(Xl
.j:>
(Xl

W

TS68483
6.3. VIDEO INTERFACE
PO, P1, P2, P3, BlK, HVS/vS, PC/HS
Vee

= 5.0 V ± 5 %, TA = TL to TH, ClK duty cycle = 50 %
= 0.8 V and VIH = 2 V, VOL = 0.4 V and VOH = 2.4 V, CL = 50 pF

Reference levels: VIL

TIMING DIAGRAM 4.

14------8----~
/14---

(2) - ___-t\

0-~1

ClK

-+_______"'"

PI031 _ _

BLK
HVS/VS
PC/HS

..---0)----.t
E88TS68483·35

Indent
Number

Parameter

TS68483·15

TS68483·18

Min.

Max.

Min.

Max.

166

55

166

1

TClK : ClK Period

66

2

elK High Pulse Width

28

3
4

Output Delay from ClK Rising Edge
ClK low Pulse Width

5

Output Hold Time

23
40

28
10

ns
ns

30
23
10

Unit

ns
ns
ns

35/41
205 .

o
N
 . i E S E V b

!O
,.iiI

-I-- -----

@en
~o

DWY

=:f:---IU

F.ELD

8Py-----1

~z

vs

~~

, - 2 5 _'NES

r.;-ERlA(f0

EXAMPLE:
------~8KY+,:PY-tDWY+8PY .. 3'2

-------

FOR 6;;5 liNES

:

I.

ODD f",ELJ BKY+FPY-DWY-6pv+1 2 L,\ES

~~-----F:JY-

m

'"'"
Ul
0)

'"
~
w
0)

CW'

.,L

!:vE~ ~IElO

.r.= 3,,_1

LJL

--I

en

en

co
.1:>0
co
w

TS68483
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc '
V in ,
TA

Value

Unit

Supply Voltage

Parameter

- 0.3 to 7.0

V

Input Voltage

- 0.3 to 7.0

V

T L to T H
o to 70

°c

- 55 to 150

°c

1.5

W

Operating Temperature Range

T slg

Storage Temperature Range

PDm

Max Power Dissipation

, With respect to Vss.
Stresses above those hereby listed may cause permanent damage to the device. The ratings are stress ones only and functional operation of the device at these or any conditions beyond those indicated in the operational sections of this specifications is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability. Standard MOS circuits handling procedure
should be used to avoid possible damage to the device.

ELECTRICAL CHARACTERISTICS
(Vee = 5.0 V ± 5 %, V S5 = 0, T A = T L to T H) (unless otherwise specified)
Min,

Typ.

Max.

Unit

Vcc

Supply Voltage

4.75

5

5.25

V

VIL

Input Low Voltage

- 0.3

0.8

V

VIH

Input High Voltage

2

Vec

V

10

IlA
V

Symbol

lin

Parameter

Input Leakage Current

=-

VOH

Output High Voltage (lioad

VOL

Output Low Voltage
Iload = 4 mA ; ADM (0 : 15)
Iload = 1 mA ; other Outputs

500 IlA)

2.4

V
0.4

PD

Power Dissipation

Gin

Input Capacitance

700
15

mW
pF

ITSI

Three State (off state) Input Current

10

!lA

37/41

207

TS68483
SECTION 7
7.1. REGISTER MAP AND COMMAND TABLE
15

13

14

R1

12

11

10

9

8

6

5

sx

2

4

o

MODE
Sy

R2

R3

7

COMMAND

RO

Odd bank

Even bank

Odd bank

Even bank

TEXLIN

~

z

~
w

u
no
.J

o

E88TS68483·37

38/41

208

Don't care
Used or not. accordmg to the command

7.2. COMMAND TABLE
TYPE

MNEM

CODE

L
I
N
E
A
R

D
R
A
W
I
N
G
S

~
11:cn

A
R
E
A
C
E
L
L

ACCESS

ifin
~C(»

~;!
!il0
,.:!I
@cn

CURSOR

~Z

CONTROL

~O

3

2

1

0

RO

Rl

R2

EXECUTION TIME
POINTERS
END COMMAND
Per
R3 R13 Rla R1S R14 R15 R1B R17 R20 R21 R22 R23 CURSOR POSITION INIT LOOP

PARAMETERS

765

4

ARGUMENTS

DOT LINE

DLI

000

0

0

DMU

SP

SRU

X

X

X

X

X

X

X

X

X

PEN LINE

PLI

000

POL

PEN

DMU

SP

SRU

X

X

X

X

X

X

X

X

X

DOT ARC

DAR

0

DMU

SP

SRU

X

X

X

X

X

X

X

X

X

X

X

PAR

o
o

0

PEN ARC

POL

PEN

DMU

SP

SRU

X

X

X

X

X

X

X

X

X

X

X

RECTANGLE

REC

1 1 1

1

0

DMU

SP

SRU

X

X

X

X

X

X

X

X

TRAPEZIUM

TRA

0 1 0

1

0

DMU

SP

SRU

X

X

X

X

X

X

X

X

POLYGON

FLL

0 1 0

0

BEG

DMU

SP

SRU

X

X

X

X

X

X

X

X

POLYARC

FLA

0 1 1

0

BEG

DMU

SP

SRU

X

X

X

X

X

X

X

X

XF

YF

PRINT CHARACTER

PCA

1

1

REP

DMU

SP

SRU

X

X

X

X

X

X

X

X

X

X

X

X

Xd+DXd

Yd

PVS

1

o
o
o

O'SMU

REP

DMU

1

SRU

X

X

X

X

X

X

X

X

X

X

X

Xd+DXd

Yd

X

X

X

PRINT OBJECT

0

1

0 1

1

INC= 0
INC~ 1
REP

=1

SMU= 1
DWN=l
LEF= 1
I\)

o

<.0

w

~

X

X

X

X Xd+DXd Yd+DYd

X

X

X

X

YF

15T

YF

15T CEll+IOT

Xd

1

0

REP

DMU

1

SRU

X

X

X

X

X

X

X

X

Xd+DXd

1 1 1

0

XFT

0

0

INC

X

X

X

X

X

X

X

X

Xs

SAVE VIEWPORT

SAV

1 1 1

0

XFT

0

1

INC

X

X

X

X , X

X

X

X

Xs

MODIFY VIEWPORT

RMV

1 1 1

0

XFT

1

0

INC

X

X

X

X

X

X

X

UP-DOWN MOVE

UDM

1 1 0

0

0

1

OWN

SRU

X

X

X

X

LEFT -RIGHT MOVE

LRM

1 1 0

1

LEF

0

0

SRU

X

X

X

DIAGONAL MOVE

COM

1 1 0

1

LEF

1

OWN

SRU

X

X

X

NO OPERATION

NOP

1 1 0

0

0

0

0

ABORT

BRT

1

1

1

1

1

0
1

POL = 1· the pen is the oblect associated with a source mask addressed
by the source pOinter
Initiate a polygon or polyarc filling
This parameter should be reset only when the second draWing IS not Identical
to the first one (Ex: first polygon. then polyarc)
The source pOinter is not autO-Incremented
XFT= 1: the source pOinter is auto-incremented. X direction first
XFT = O· The source pOinter is auto-incremented or auto-decremented. Y direction first
The cell IS stepped and repeated through the destination Window
When REP=O. only one cell IS pnnted
The source mask IS used
The cursor IS moved down (up If DWN=O).
The cursor is moved left (fight If LEF=O)

,
I

Yd+DYd lOT

X

,

,
i

X
X

I
I

I

DOT
CELL

AREA
MEMORY
4T
(NOTE 11 WORD

15T
I
4T

I

6T

MEMORY
WORD

Yd

,

Ys

2T

5T

Ys

2T

4T

Ys

2T

lOT

Xs'

,

Xd

Yd+DYd 3T

Xd+DXd

DOT
CELL

4T

Xd+DXd Yd+DYd lOT

1

I

lOT

Xd+DXd Yd+DYd lOT

X

PVF

'1'1

4T

5T CEll+4T

XF

LDV

X

5T

XF

LOAD VIEWPORT

DMU= 1
Destination mask use
SP= 1
Short pel: long pel when SP=O
SRU = 1 . Short relative register use (A13).
PEN = 0 : The pen IS a single pel
PEN = 1
POL=O. the pen IS the character cell addressed by the source pOinter
BEG= 1

X

Xd+DXd Yd+DYd

X

Yd

MEMORY,
WORD
I

I

3T

Xd+DXd Yd+DYd 4T

I

TT
TTl

NOTE' With PVF command. any pel with color different trom 0 has Its source mask Implicitly set and
used In other words. pels with color value 0 are transparent
- OXd. DYd. and DYs are signed values
- DXs IS always pOSItive
- T = memory cycle:::: 8 elK clock periods.
- For execution time. add to the short pel loop In the table:

- 1T 'f DMU=l
- 1T ,f SMU=l
. 2T If long pen are used
2T If mask printing IS required
Command execution IS performed only out of the display periods
NOTE 1 for FlL and FLA commands. add 4T and 8T respectively per pel belonging to the boundary.

-I
en
en
CO

.j:>.

CO

(,)

TS68483
8. ORDERING INFORMATION AND MECHANICAL DATA
8.1. ORDERING INFORMATION
Part Number
TS68483CP15
TS68483CP18
TS68483CFN15
TS68483CFN18

Package

Clock

o DC to + 70 DC

DIP 64

15 MHz
18 MHz

o DC to + 70 DC

PLCC 68

15 MHz
18 MHz

Temperature Range

8.2 PACKAGE MECHANICAL DATA
68 PINS - PLASTIC LEADED CHIP CARRIER

60

0.812 -

-Qm~~ . .

40/41

210

0331

68,'Jutputs

,

"el\lon~

AI a

TS68483
64 PINS - PLASTIC DIP

2,54
4,19

0,38
0,53

i

~II-----'-"---""'''''-i'''''''

0,76
1,40

33

Datum

32

81.28

22.479

22 .987

41/41

211

I
I
I
I
I
I
I
I
I
I
I
I
I
I

I
I
I

I
I
I
I

I
I
I
I
I

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

I
I
I
I

I
I
I
I

I
I
I
I

I
I
I
I
I
I
I
I
I
I
I
I
I
I

I
I
I

I
I
I
I

I
I
I
I

I
I
I
I

I
I
I
I
I
I
I
I
I
I

I
I
I

I
I
I
I

I

~I

COLOR PALETTE

213

EF9369
HMOS2 - SINGLE CHIP COLOR PALETTE
• ON CHIP COLOR LOOK-UP TABLE
• 4096 COLOR PALETTE (16 colors selected from
4096)
• ON-CHIP THREE 4-BIT RESOLUTION VIDEO
DACs WITH YLAW CORRECTION
• DOT RATE UP to 30 MEGADOTS PER SECOND
• MARKING BIT FOR INLAY PURPOSE
• VERSATILE MICROPROCESSOR
INTERFACE:
_ DIRECTLY COMPATIBLE WITH ADDRESS/DATA
MULTIPLEXED
8-BIT
MICROPROCESSOR BUS SUCH AS 6801,
8051 ...
_ DIRECTLY COMPATIBLE WITH NON-MULTIPLEXED 8 OR 16-BIT MICROPROCESSOR BUS (6809, 6502, 68008 ... ).
• SINGLE 5 V SUPPLY
• HMOS 2 TECHNOLOGY

P
DIP28

(Plastic Package)

FN
PLCC28

(Plastic leaded chip carrier)
(see the ordering information at the end of the datasheet)

DESCRIPTION
The EF9369 single chip palette provides a low cost,
yet remarkable enhancement for any low to midrange color graphics application. It allows displaying
up to 16 different colors, each of these colors being

freely selected out of 4096 preset values. EF9369
contains a 16 register color look-up table, three 4bit D/A converters and a microprocessor interface
for color loading.

PIN CONNECTIONS
DIP28

PLCC28

Vss

HP

Vooe

PJ

u
0

0
0

.

P2

i0 >gj
M

...

-

...
:I:

~

...'"

1'1

...

1II

~

0

P'

PI

PO

PO

BLK

BLK

AS

AS

RM
os
cso

a

AD'

AD7

Ace

21
RESET

RM

05

!!

~ ~

...0 ...0

~

!!! !!!

::

"'0 8

0

~

c c c c « «

cso

!!

rJ

A05
E88-EF9369·02
E88·EF9369·01

November 1988

1/15

215

EF9369
TYPICAL APPLICATION

IMICROf'ROCESliOR J

DIGITAL
VIDEO

DOT CLOCK
CRT
CONTROLLER
BLANKING

~
EF9369
COLOR
PALETTE

ANALOG
VIDEO
R

EJ

G

B

t

SYNC

E88-EF9369-03

ABSOLUTE MAXIMUM RATINGS

.

Symbol
Vee

Vin*

TA

Value

Parameter

Unit

Supply Voltage

- 0.3 to 7.0

V

Input Voltage

- 0.3 to 7.0

V

Operating Temperature Range

TOl9

Storage Temperature Range

PO m

Max Power Dissipation

o to 70

°C

-55t0150

OC

0.45

W

Stresses above those hereby listed may cause permanent damage to the device. The ratings are stress ones only and functional operation of the device at these or any conditions beyond those indicated in the operational sections of this specification is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability. Standard MOS circuits handing procedure
should be used to avoid possible damage to the device.
• With respect to Vss.

ELECTRICAL OPERATING CHARACTERISTICS 0/cc = 5.0 ± 5 %, Vss = 0, TA
Parameter

Symbol
Vec

Supply Voltage

Vooe

Analog Supply Voltage

loDe

Analog Supply Current

VIL

Input Low Voltage

VIH

Input High Voltage

lin

Input Leakage Current

VOH

Output High Voltage (iload = - 500 I1A)

VOL

Output Low Voltage (iload = 1.6 mA)

RESET
All Other Inputs

Typ.

Max.

4.75

5

5.25

V

-

Vee

TSD

V

-

20

-

mA

-0.3

-

0.8

V

Vce
Vee

V

-

20

~

-

V

3
2

2.4

Cin

Input Capacitance

-

IrSI

Three State (off state) Input Current

-

Po

2/15

216

Power Dissipation

= 0 to 70°C)

Min.

-

Unit

-

0.4

V

250

-

mW

-

15

pF

-

10

~

EF9369
Test Load for Analog Output

Test Load for Digital Output

Tel1
potnt

AD (0 :7)

M

100 pF

50 pF

RL

1 kO

3,3 kO

R

4,7 kO

4,7 kO

C

MICROPROCESSOR INTERFACE TIMING AD (0 : 7), AS, DS, RiW, CS, CSO
Vcc = 5,0 ± 5 %, T A = 0 'C to + 70 DC, C L = 100 pF on AD (0 : 7)
TTL inputs are 0 to 3 volts, with input riselfall time ~ 3 ns, measured between 10 % and 90 % points,
Timing reference at 50 % for inputs and outputs,
Indent.
Number

Symbol

Parameter

Min.

Typ.

Max.

Unit

1

tCYC

Cycle Time

400

-

-

ns

1b

tpEWX

OS Pulse Width High Time

200

-

-

ns

1c

tPEWL

OS Pulse Width Low Time (timing 3)

100

10000

ns

30

-

-

ns

-

-

ns

2

tASO

DS Low to AS High (timing 1)
OS High or R/w high to AS high (timing 2)

3

tASEO

AS Low to DS High (timiQ.g 1)
AS Low to OS Low or R/W Low (timing 2)

30

4

tpwEH

Write Pulse Width

200

-

-

ns

5

tPAWSH

AS Pulse Width

100

-

ns

6

tRWS

R/W to OS Setup Time (timing 1)

100

-

-

ns

R/W, AS, CS, CSO to OS Setup Time
(timing 3)

100

-

-

ns

6b
7

tRwH

R/W to OS Hold Time (timing 1)

10

-

-

ns

8

tASL

Address and CS, CSO Set Up Time

20

-

-

ns

9

tAHL

Address and CS, CSO Hold Time

20

-

-

ns

10

tosw

Data Setup Time (write cycle)

100

-

-

ns

11

tOHW

Data Hold Time (write cycle)

10

-

-

ns

12

tOOR

Data Access Time from OS (read cycle)

-

-

150

ns

13

tOHR

OS Inactive to High Impedance State Time
(read cycle)

10

-

80

ns

14

tACC

Address to Data Valid Access Time

-

-

300

ns

3/15

217

EF9369
TIMING DIAGRAM 1 - MULTIPLEXED MODE - MOTOROLA TYPE (SMI

os

--', ..1-1-0

0

1\

AS

RIW

/

-- I

Vss)

CD
'Pwl:x

r\

®

:\

(i)

=

.

•

}

~

f-@

V
~0

K
,...-

~~<
) '-- r-LI
0
WRITE CYCLE

I

ADID:7 I

(i)
READe YCLl

AOIO:7I

'\

.

®

.....- 1--

--0

ADDjEj»

Xj (XI)

d

-UT
DATA

\

I
E88-EF9369-06

4/15

218

EF9369
TIMING DIAGRAM 2 - MULTIPLEXED MODE - INTEL TYPE (8MI = Vss)
READ CYCLE

iW (Pin OSI

-L~~.L.LLI.J

WR

IPm R/WI

®
'DDR

A D I O : 7 1 - - - - - - - - - - - - { 1 ADDRESS

®
'ACC

E88-EF9369-07

WRITE CYCLE

ALE IPi_n_A.;.:SI_ _ _ _ _ _--:~.JJ

Q)
RO

IPin 051

'ASD

'PWEH

cs
COO

ADIO:71------------<

'osw
Din

E88-EF9369-08

5/15

219

EF9369
TIMING DIAGRAM 3 - NON-MULTIPLEXED MODE (SMI = Vee)

'PWEX

'DSW
WRITE CYCLE
ADIO,7)

INPUT DATA
'DDR

2

READ CYCLE
ADIO,7)

E88-EF9369-09

DIGITAL VIDEO SIGNALS - HP, P(O : 3), BLK, M, RESET
Vee = 5,0 ± 5 %, TA = 0 'C to + 70°C, C L = 50 pF on M,
TTL inputs are 0 to 3 volts, with input rise/fall time :0; 3 ns, measured between 10 % and 90 % points,
Timing reference at 50 % for inputs and outputs,
Symbol
tp

EF9369

Parameter

EF9369-30

Min.

Max.

Min.

Max.

Unit

HP Clock Period

58

1000

33

1000

ns

tPEWH

HP High Pulse Width

25

13

-

ns

tPEWL

HP Low Pulse Width

25

-

13

-

ns

tsu

BLK and P(O : 3) Set Up Time to HP

5

-

5

-

ns

tHO

BLK and P(O : 3) Hold Time from HP

10

-

10

-

ns

tD

M Output Delay from HP

-

45

-

45

ns

tPWRL

RESET High Pulse Width

400

-

400

-

ns

6/15

220

EF9369
TIMING DIAGRAM 4

tPWEH

HP

BLK

PO
P3

tD
M

E88-EF9369-10

ANALOG VIDEO OUTPUTS - CA, CB, CC
Vocc > 5 V, TA =O°C to + 70°C, CL = 20 pF, RL = 100 kQ

Table 1.
Analog Output (V)

Binary Input
Low Level

Min.

Typ.

Max.

0_8

-

0001

-

1.18

-

0010

-

1.28

-

0011

-

1.36

-

0100

-

1.42

-

0101

1.47
1.52

-

0110

-

0111

-

1.56

1000

1.60
1.66

-

1011

-

1.69

-

1100

-

1.72

1101

-

1.75

1110

-

1.78

1111

-

1.80

-

0000

1001
1010

High Level

1.63

-

Nole: The internal AID converters deliver on CA, CB and CC outputs 16 levels with y law correction (y = 2.8). The typical transfer cha-

racteristic is given by :

1
N VDDC
V= ( - ) 2.8 . - - +O.16VDCC
15
5
Where N is the binary input value.
The typical analog video output impedanoe is 300 Q for EF9369-30 and 400 Q for EF9369.

7/15

221

EF9369
Parameter
CA, CB, CC Outputs from HP

TIMING DIAGRAM 5

PIO:31

/

J

HP

~

:xxxxx;

tDA

I

'!Y;i

CA,CB. CC

E88-EF9369-11

BLOCK DIAGRAM
ADDRESSICONTROL BUS

FROM
MICROPROCESSOR

DATA/ADDRESS BUS

SUI

BUS
CONTROL

Vee

Vss
DIGITAL
VIDEO

INPUTS
HP
0-

16
BlK

COLOR
INDEX

CA

CB

cc

OECOOER

FJELD

FIELD

FIELD

m

"it
Z

.

a:

::Ii

'--_-+~U

RESET
~o---_-+.

CA

CB

Vooc

cc
E88-EF9369-12

8/15

222

)IN DESCRIPTION
vllCROPROCESSOR INTERFACE
!l,1I the input/output pins are TIL compatible.
Name

Pin
Type

AD(0:7)

1/0

SMI

I

3

Interface Mode
Select

When this input is connected to Vcc, the EF9369 is in the non
multiplexed mode.
When this input is connected to Vss (ground), the EF9369 is in
a multiplexed mode to provide a direct interface with either
Motorola or Intel Type Microprocessor.

AS

I

22

Address Strobe

In non-multiplexed mode, this input selects either the address
register (AS = 1) or the data register (AS = 0) to be accessed. In
multiplexed mode, the falling edge of this control signal latches
on the AD(O:ZL!ines, the state of the Data Strobe (DS) and Chip
Select lines (CS, CSO). When using Intel type microprocessor,
this input must be connected to the ALE control line.

DS

I

20

Data Strobe

In non multiplexed mode, this active high control signal enables
the AD(0:7) input/output buffers and strobes data to/from the
EF9369. This signal is usually derived from the processor E
(02) clock.
In multiplexed mode, the input is strobed by the falling edge of
AS. The strobe value selects either Motorola or Intel type. When
usin.\l..2n Intel type microprocessor, DS must be connected to
the RD control line. With a Motorola type microprocessor, DS
must be connected to E(02) clock.

RIW

I

21

Read/write

Thi.§..control signal deter[!!!nes whether the EF9369 is read
(R/W = 1 ) or written (RIW = 0). When using Intel tYPL
microprocessor, this input must be connected to the WR control
line.

CS
CSO

I

18
19

Chip Select

CS must be low and CSO must be high to select the EF9369. In
non multiplexed mode, the EF9369 remains selected as long as
the selection condition is met.
In multiplexed mode, the selection condition is latched when AS
is low.

N°

Function

Description

N°

Function

8·11-14
Multiplexed
15-17 Address/data Bus

Description
These 8 bidirectional pins are to be connected to the
microprocessor system bus.

OTHER PINS
Name

Pin

Type

Vcc

S

9

Power Supply

+5V

Vooc

S

2

Analog Power
Supply

Power supply for the internal DACs. This input can be connected
to Vcc.

Vss

S

1

Power Supply

Ground

9/15

223

EF9369
VIDEO INTERFACE
Name

Pin
Type

N°

Function

P(0:3)

I

24-27

Pixel Inputs

HP

I

28

Dot Clock

The rising edge of this input latches the P(0:3) and BlK inputs
into the EF9369 and the data out of color look-up table into the
output registers.

M

0

7

Marking

This output is synchronised by HP and delivers the marking bit
value from the color look-up table.

CA
CB
CC

0

5
6
4

Color Outputs

BlK

I

23

Blanking

RESET

I

10

Reset

Description
These four TTL compatible inputs are strobed by HP into the
color index register to address the color look-up table.

These three analog high impedance outputs deliver the color
signal levels from the internal DIA converters (DAC). The delay
between CA, CB, CC outputs and the latched value P(0:3) is one
HP clock period plus tDA (see timing diagram 5).
A high level on this input forces the CA, CB, CC and M outputs
to low level.
This active high input forces the CA, CB, CC, outputs to low
level until the next microprocessor access to the device.

FUNCTIONAL DESCRIPTION
EF9369 contains a 16 register Color-Look Up Table
(CLUT). Each of these 13-bit register holds three 4bit color fields CA (0:3), CB (0:3) and CC (0:3) and
a marking bit M.

• Multiplexed mode for address/data multiplexed
8 bit microprocessor bus.
• Non-multiplexed mode for non-multiplexed 8 or
16-bit microprocessor bus.

These registers can be accessed (read or write) by
the microprocessor through the microprocessor interface. These registers are also read by the video
process: a 4-bit pixel value and a clock must be provided at pixel rate to the P (0:3) and HP input pins.
These signals may be delivered either by 4 video
shift registers and the shifting clock of a bit map CRT
controller or by an alphanumeric or semigraphic
CRT controller. The pixel value, after clock resynchronization, is used as a color index: it selects one
out of the 16 CLUT registers. Each color field of the
selected register is converted to an analog signal
and delivered to one of the CA, CB or CC output.
The marking bit is directly routed to the M output.
When the CA, CB and CC outputs are used as RGB
analog signals, one color out of 4096 is associated
to each pixel value. In short this process freely maps
a 16 color index set into a 4096 color set.

MULTIPLEXED MODE (SMI connected to Vss).

MICROPROCESSOR INTERFACE.
The 8-bit microprocessor interface gives access
(read or write) to the CLUT which is addressed as
a 32 byte table. The 13-bit color register # N (N = 0
to 15) is accessed at address 2N and 2N + 1. Even
address holds CA (0:3) and CB (0:3), odd address
holds CO (0:3) and M (see fig. 1).
EF9369 provides two bus modes through the SMI
programming pin:

10/15

224

In this mode, EF9369 can be directly connected to
popular address/data multiplexed microprocessor, either Motorola type (6801...) or Intel type
(8048,8051,8088 ... ). In this last case the EF9369
AS, DS and RIW inputs must be connected respectively to the ALE, RD and WR microprocessor
control lines.
In this mode, EF9369 maps into the microprocessor
addressing space as 32 CLUT byte address. Random access to one byte takes one cycle: on the failing edge of the AS input, EF9369 latches AD (0:7)
into the on-chip address register, the DS and chip
select lines into dedicated flip,flops. The strobed
value of DS allows recognition of Intel or Motorola
type for further processing. (See pin description section and microprocessor timing diagrams for details). When the EF9369 chip select lines enable selection, the addressed byte is accessed during the
data phase of the cycle.
NON MULTIPLEXED MODE (SMI connected to
Vcc).
In this mode EF9369 can be directly connected to
any 8 or 16-bit, non multiplexed, microprocessor bus
(6800, 6809, 6502, 68008 ... ).
This mode provides an indirect, auto-incremented
addressing scheme. EF9369 maps into the micro-

~ SGS·THOMSON
. .. , / Ii\lJO©Ii@llI!.rnlC'li'li@Il'lO©iII

EF9369
Figure 1 : Clut Adressing
7

Color Look-up Table (CLUT)
6
4
2
1
5
3

CB3 CB2 CB1

X

X

X

CB3 CB2 CB1

X

X

X

CB3 CB2 CB1

X

X

X

0

7

6

CLUT Byte Adress
4
2
5
3

1

0

CAO

X

X

X

0

0

0

0

0

CC3 CC2 CC1

CCO

X

X

X

0

0

0

0

1

CBO CA3 CA2 CA1

CBO CA3 CA2 CA1

M

CAO

X

X

X

0

0

0

1

0

CC3 CC2 CC1

CCO

X

X

X

0

0

0

1

1

CBO CA3 CA2 CA1

CAO

X

X

X

1

1

1

1

0

CC3 CC2 CC1 CCO

X

X

X

1

1

1

1

1

M

M

Register Index
#
0
1

15

x ~ Don't Care.
processor addressing space as 2 byte address only. AS is used to select one out of 2 registers:
• the write only address (5 bits) addressed when
AS = 1.
• the read/write data register (8 bits) addressed
when AS = O.
Random access to a CLUT byte takes two bus cycles:
1/ Load the CLUT address into the address register.
2/ Access (read or write) the value in the data register.
After each access to the data reg ister, the add ress
register is automatically incremented modulo 32.
This scheme allows sequential addressing to the
CLUT without address reloading, the complete
CLUT can so be reloaded in 33 bus cycles.
VIDEO PROCESS.
The CRT controller sends to EF9369 a pixel value on
pins P (0:3), a pixel rate clock on HP input and a blanking signal on pin BLK. The pixel value is latched into the color index register by the rising edge of HP.
The color index register selects one register in the
CLUT. The color fields of the selected register are
routed to 3 DACs and M is directly routed to the M digital output.
After impedance matching, the CA, CB, and CC outputs can be used to drive a RGB analog color monitor. Alternatively one of these outputs can be used
to drive a monochrome monitor thus providing up to
t 6 grey levels. The marking digital output can be
used to drive analog video switches, thus providing
video overlay facility on a color per color basis.

The blanking input forces the analog outputs and
the M output to low level thus allowing the beam to
be switched off during retrace intervals .
Notes: 1. Each 4 bit-D/A converter is ycorrected in
order to linearize the luminance driven on
the screen versus the digital value. The
typical digital to voltage conversion law is
given table 1. The output voltages are proportionnal to the analog supply voltage
Vooc. When required, setting Vocc allows
a gain adjustment. But in most applications, Vooc and Voo can be derived from
the same supply through independent decoupling.
2. CA, CB and CC are high impedance outputs (500 Q typical) which require proper
adaptation in most applications. SGSTHOMSON TEA5114 provides such a
1 V - 75 Q low cost adaptation (See fig.
2).
3. As the CLUT is shared between microprocessor access and video access, a
low level is forced on the CA, CB, CC and
M outputs during any chip select periods.
To avoid to spoil the screen with black
strokes it is recommended to access the
CLUT from the microprocessor only during the retrace periods.
4. RESET - This input forces CA, CB, CC
and M outputs to a low level until the next
microprocessor access. At power on or at
the beginning of a session RESET allows
to keep a clean black screen proper initialization.

11/15

225

EF9369
NON-MULTIPLEXED BUS INTERFACE

v CC
D(O:7)

SMI

K

)

AO

AD(O:15)

AS

EF9369

MPU

"-

A(O:15)

/

-

ADDRESS

CS

DECODER

E

DS

R/W

R/W

E88-EF9369-13

MULTIPLEXED BUS INTERFACE

v S8

PORTC

MPU

A(8:1S)

ALE

8MI

AD(O:7)

ADDRESS
DECODER

I

CSO

-

EF9369

CS

AS

RD

DS

WR

RrW

E88-EF9369-14

12/15

226

EF9369
Figure 2 : Typical 1 V - 75

n Video Interface

BLK~--------------

__

HPii--------------__
FROM

~ia--------------.

CRT CONTROlLE R

p,~----------------.
P2~--------------4
P3~--------------4

EF9369

68n

68n

TO
_'TOR

680

E88-EF9369-15
Note: Each digital or analog ground must be separately connected to EF9369 pin 1.

13115

227

EF9369
ORDERING INFORMATION
Part Number
EF9369P
EF9369P30
EF9369FN

Temperature

Package

o to 70°C
o to 70°C
o to 70°C

DIP28
DIP28
PLCC28

PACKAGE MECHANICAL DATA
28 PINS - PLASTIC DIP
mm

e.2.54

4.57max.
16.1 max.
0.51

min.

r--"'-""'--' ~

...

15.24
(2)

Datum

(1) Nominal dimension

(2) True geometrical position

14
6

14/15

228

28

SGS·1HOMSON
a...,Irnii~ICII@~II@IlIJ~lCiII
~

PINS

EF9369
28 PINS - PLASTIC LEADED CHIP CARRIER
Pin 1 identification

11430

~
25

0661
0,812
~
min.

28 Outputs

0331
0,533

15/15

229

TS9370
HMOS2 - SINGLE CHIP COLOR PALETTE
• ON CHIP COLOR LOOK-UP TABLE
• 4096 COLOR PALETTE (16 colors selected from
4096)
• ON-CHIP THREE 4-BIT RESOLUTION VIDEO
DACs
• DOT RATE UP TO 45 MEGADOTS PER SECOND
• MARKING BIT FOR INLAY PURPOSE
• VERSATILE MICROPROCESSOR INTERFACE:
_ DIRECTLY COMPATIBLE WITH ADDRESS/DATA
MULTIPLEXED
8-BIT
MICROPROCESSOR BUS SUCH AS 6801,
8051 ...
_ DIRECTLY COMPATIBLE WITH NON-MULTIPLEXED 8 OR 16-BIT MICROPROCESSOR BUS (6809, 6502, 68008 ... )
• SINGLE 5 V SUPPLY
• LOW POWER DISSIPATION
• 28 PINS DIP AND PLCC PACKAGE

DESCRIPTION
The TS9370 single chip palette provides a low cost,
yet remarkable enhancement for any low to midrange color graphics application. It allows displaying

P
DIP28

(Plastic Package)

FN
PLCC28

(Plastic leaded chip carrier)
(see the ordering information at the end of the datasheet)

up to 16 different colors, each of three colors being
freely selected out of 4096 preset values. TS9370
contains a 16 register color look-up table, three 4bit D/A converters and a microprocessor interface
for color loading.

PIN CONNECTIONS
DIP28

PLCC28
HI'

u

1'3

U

.i

1'2

80 II ..
%

> >
N

1"

-

P:I

.." ..
N

...
N

P:I

0

PO

PI

PO

BU:

BLK

AS

AS

.. oW
os
aD

a

..J9iI
RESET

D5

CSD
~

:!

~

N

"0

~

0

0
00(

E88·TS9370·01

November 1988

. 8 ::...

~

00(

00(

00(

~

0

00(

00(

~

rl

E88· TS9370·02

1/16

231

TS9370
TYPICAL APPLICATION

HOST
MICROPROCESSOR

I

J

U

H
GRAPHICS

VIDEO INTERFACE

~

PROCESSOR

~.
~~

VIDEO
MEMORY

PIXEL
DATA

TS9370

ANALOG
VIDEO

COLOR
PALETTE
SYNC.

EJ
J

E88-T89370-03

2/16

232

TS9370
BLOCK DIAGRAM

AOORESSICONTROL BUS

)

FROM
MICROPROCESSOR

DATA/ADDRESS BUS

<

)

III
« rl ~
a: ~

~DIO'11

r

I

PO<;
P3.o!

.....,0-- I

r--"Xw
a

~

a:

0
-'
0
u

DIGITAL
VIDEO
INPUTS
H~_

r--

3/

)
ADDRESS REGISTER

./J t1

'"

BLK_ I-

MUX

t)4

J

DATA REGIS:ER

r

>-'SMI
BUS
CONTROL

f- Vce
f-

"...8

/

J

/'

COLOR
INDEX
DECODER

§

~

. . rCA

CB

ce

FIELD

FIELD

FIELD

iii

":::::
"
'"

a:
:;

•

4

4

r-M6
OUTPUT REGISTERS

RESET

J

~

CONTROLLER

4

4

4

eA

CB

ee

J
M

I

M

E88-TS9369-12

3/16

233

TS9370
PIN DESCRIPTION
MICROPROCESSOR INTERFACE
All the input/output pins are TTL compatible.
Name

Pin
Type

AD(0:7)

I/O

SMI

I

3

Microprocessor
Interface Mode
Select

When this input is connected to Vcc, the TS9370 is in the non
multiplexed mode.
When this input is connected to Vss (ground), the EF9370 is in
a multiplexed mode to provide a direct interface with either
Motorola or Intel Type Microprocessor.

AS

I

22

Address Strobe

In non-multiplexed mode, this input selects either the address
register (AS = 1) or the data register (AS = 0) to be accessed. In
multiplexed mode, the falling edge of this control signal latches
the address on the AD(0:7) lines, the state of the Data Strobe
(OS) and Chip Select lines (CS, CSO). When using Intel type
microprocessor, this input must be connected to the ALE control
line.

OS

I

20

Data Strobe

In non multiplexed mode, this active high control signal enables
the AD(0:7) input/output buffers and strobes data to/from the
TS9370. This signal is usually derived from the processor E
(02) clock.
In multiplexed mode, the input is strobed by the falling edge of
AS. The strobe value selects either Motorola or Intel type. When
uSin.9.J!n Intel type microprocessor, OS must be connected to
the RD control line. With a Motorola type microprocessor, OS
must be connected to E(02) clock.

RIW

I

21

Read/write

Thi~control

CS
CSO

I

18
19

Chip Select

CS must be low and CSO must be high to select the TS9370. In
non multiplexed mode, the TS9370 remains selected as long as
the selection condition is met.
In multiplexed mode, the selection condition is latched when AS
is low.

4116

234

N°

Function

8-11-14
Multiplexed
15-17 Address/data Bus

Description
These 8 bidirectional pins are to be connected to the
microprocessor system bus.

signal deter[1JJnes whether the TS9370 is read
(RIW = 1 ) or written (RIW = 0). When using Intel type
microprocessor, this input must be connected to the WR control
line.

TS9370
VIDEO INTERFACE
Name

Pin
Type

N°

Function

P(0:3)

I

24-27

Pixel Inputs

HP

I

28

Dot Clock

The rising edge of this input latches the P(0:3) and BLK inputs
into the TS9370 and the data out of color look-up table into the
output registers.

M

0

7

Marking

This output is synchronised by HP and delivers the marking bit
value from the color look-up table.
The logical delay between M output and the latched value P(0:3)
is one HP clock period.

CA
CB
CC

0

5
6
4

Color Outputs

These three analog outputs deliver the color signal levels from
the internal D/A converters (DAC). The delay between CA, CB,
CC outputs and the latched value P(0:3) is one HP clock period
(see timing diagram 5).

BLK

I

23

Blanking

A high level on this input forces the CA, CB, CC and M outputs
to low level.

RESET

I

10

Reset

Function

Description
These four TTL compatible inputs are strobed by HP into the
color index register to address the color look-up table.

This active high input forces the CA, CB, CC, outputs to low
level until the next microprocessor access to the device.

OTHER PINS
Name

Pin
Type

N°

Description

Vcc

S

9

Power Supply

+5V

Vooc

S

2

Analog Power
Supply

Power supply for the internal DACs. This input can be connected
to Vce.

Vss

S

1

Power Supply

Ground

FUNCTIONAL DESCRIPTION
TS9370 contains a 16 register Color-Look Up Table
(CLUT). Each of these 13-bit register holds three
4-bit color fields CA (0:3), CB (0:3) and CC (0:3) and
a marking bit M.
These registers can be accessed (read or write) by
the microprocessor through the microprocessor
interlace. These registers are also read by the video
process: a 4-bit pixel data and a clock must be
provided at pixel rate to the P(0:3) and HP input pins.
These signals may be delivered either by 4 video
shift registers and the shifting clock of a bit map CRT
controller or by an alphanumeric or semi-graphic
CRT controller. The pixel value, after clock resynchronisation, is used as a color index: it selects one
out of the 16 CLUT registers. Each color field of the
selected register is converted to an analog signal
and delivered to one of the CA, CB or CC output.
The marking bit is directly routed to the M output.
When the CA, CB and CC outputs are used as RGB
analog signals, one color out of 4096 is associated
to each pixel value. In short this process freely maps
a 16 color index set into a 4096 color set.

MICROPROCESSOR INTERFACE
The 8-bit microprocessor interlace gives access
(read or write) to the CLUT which is addressed as a
32 by1e table. The 13-bit color register # N
(N = 0 to 15) is accessed,at address 2N and 2N +
1. Even address holds CA (0:3) and CB (0:3), odd
address holds CC (0:3) and M (see fig. 1).
TS9370 provides two bus modes through the SMI
programming pin:
• Multiplexed mode for address/data multiplexed 8bit microprocessor bus.
• Non-multiplexed mode for non-multiplexed 8 or
16 bit microprocessor bus.
MULTIPLEXED MODE (SMI connected to Vss)
In this mode, TS9370 can be directly connected to
popular address/data multiplexed microprocessor,
either Motorola type (6801) or Intel type (8048,
8051, fill88 ... ). In this last case the TS9370 AS, DS
and R/W loQuts must be connected respectively to
the ALE, RD and WR microprocessor control lines.

5/16

235
------------ - - - - - - - - - - - - - - - - - -

TS9370
Figure 1 : Clut Adressing.
7

Color Look-up Table (CLUT)
6
5
4
3
2
1

CB3 CB2 CB1

X

X

X

CB3 CB2 CB1

X

X

X

CB3 CB2 CB1

X

X

X

6

5

4

3

2

1

0

CAO

X

X

X

0

0

0

0

0

CC3 CC2 CC1 CCO

X

X

X

0

0

0

0

1

CAO

X

X

X

0

0

0

1

0

CC3 CC2 CC1 CCO

X

X

X

0

0

0

1

1

CAO

X

X

X

1

1

1

1

0

CC3 CC2 CC1 CCO

X

X

X

1

1

1

1

1

CBO CA3 CA2 CA1
M

CBO CA3 CA2 CA1
M

Register Index

7

CBO CA3 CA2 CA1
M

CLUT Byte Adress

0

#
0
1

15

x = Don't Care.
In this mode, TS9370 maps into the microprocessor
addressing space as 32 CLUT byte address. Random access to one byte takes one cycle: on the faIling edge of the AS input, TS9370 latches AD (0:7)
into the on-chip address register, the DS and chip
select lines into dedicated flip-flops. The strobed value of DS allows recognition of Intel or Motorola type
for further processing. (See pin description section
and microprocessor timing diagrams for details).
When TS9370 chip select lines enable selection, the
addressed byte is accessed during the data phase
of the cycle.
NON MULTIPLEXED MODE
(SMI connected to Vcc)
In this mode TS9370 can be directly connected to
any 8 or 16-bit, non-multiplexed, microprocessor
bus (6800, 6809, 6502, 68008 ... ).
This mode provides an indirect, auto-incremented
addressing scheme. TS9370 maps into the microprocessor addressing space as 2 byte address only. AS is used to select one out of 2 registers:
• the write only address register (5 bits) addressed
when AS = 1.
• the read/write data register (8 bits) addressed
when AS = O.
Random access to a CLUT byte takes two bus cycles:
1/ Load the CLUT address into the address register.
2/ Access (read or write) the value in the data register.
After each access to the data register, the address
register is automatically incremented modulo 32.
This scheme allows sequential addressing to the
CLUT without address reloading, the complete
CLUT can so be reloaded in 33 bus cycles.
VIDEO PROCESS
The CRT controller sends to TS9370 a pixel value
6/16

236

on pins P (0:3), a pixel rate clock on HP input and a
blanking signal on pin BLK. The pixel value is latched into the color index register by the rising edge
of HP. The color index register selects one register
in the CLUT. The color fields of the selected register are routed to 3 DACs and M is directly routed to
the M digital output. After impedance matching, the
CA, CB, and CC outputs can be used to drive a RGB
analog color monitor. Alternatively one of these outputs can be used to drive a monochrome monitor
thus providing up to 16 grey levels. The marking digital output can be used to drive analog video
switches, thus providing video overlay facility on a
color per color basis.
The blanking input forces the analog outputs and
the M output to low level thus allowing the beam to
be switched off during retrace intervals.
Notes: 1.The output voltages are proportionnal
to the analog supply voltage VDDC.
When required, setting VDCC allows a
gain adjustment. But in most applications, VDDC and VDD can be derived
from the same supply through independent decoupling.
2.As the CLUT is shared between microprocessor access and video access, a
low level is forced on the CA, CB, CC
and M outputs during any chip select
periods. To avoid to spoil the screen
with black strokes it is recommended
to access the CLUT from the microprocessor only during the retrace periods.
3.RESET - This input forces CA, CB, CC
and M outputs to a low level until the
next microprocessor access. At power
on or at the beginning of a session RESET allows to keep a clean black
screen until proper initialization.

TS9370
NON MULTIPLEXED MODE

VCC

-

0(0:7)

SMI

AD(0:7)

AS

1
MPU

A(0:1S)

ADDRESS

I

DECODER

,

-

CS

E

TS9370

OS

-

RNV

RNV

MULTIPLEXED MODE - INTEL TYPE

VSS

AD(0:7)

MPU

A(B:1S)

ALE

-

SMI

AD(0:7)

ADDRESS
DECODER

I

CSO
-

TS9370

CS

AS

-

RD

OS

WR

R/W

-

E88-EF9369-12

7/16

237

TS9370
ABSOLUTE MAXIMUM RATINGS
Symbol

Parameter

Value

Unit

Vee *

Digital Power Supply

- 0.3 to 7.0

V

Vin*

Input Voltage

- 0.3 to 7.0

V

o to 70

°C

TA

Operating Temperature Range

T stg

Storage Temperature Range

- 55 to 150

°C

Analog Power Supply

- 0.3 to 9.0

V

Vooe *

Stresses above those hereby listed may cause permanent damage to the device. The ratings are stress ones only and functional operation of the device at these or any conditions beyond those indicated in the operational sections of this specification is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability. Standard MOS circuits handing procedure
should be used to avoid possible damage to the device.
* With respect to Vss.

ELECTRICAL OPERATING CHARACTERISTICS
(Vee = 5.0 ±5%, Vss = 0, TA =-25 OC to + 85 °C)
Symbol

Parameter

Vee

Supply Voltage

Vooc

Analog Supply Voltage

loDe

Analog Supply Current

V,L

Input Low Voltage

V,H

Input High Voltage

RESET
All Other Inputs

Input Leakage Current

lin

Min.

Typ.

Max.

Unit

4.75

5

5.25

V

-

Vee

7

V

20

-

mA

-0.3

-

0.8

V

3
2

-

Vee
Vee

V

-

-

20

~
V

0.4

V

300

500

mW

2.4

-

VOH

Output High Voltage (I'oad = - 500 !-LA)

VOL

Output Low Voltage (I'oad = 1.6 mAl

Po

Power Dissipation

-

Cin

Input Capacitance

-

-

15

pF

ITSI

Th ree State (off state) Input Cu rrent

-

-

10

~

Test Load for Digital Output

Test Load for Analog Output

Tn,
point

1 ..... '

or equiv.

E88·TS9370-06

AD (0 :7)

M

100 pF

50 pF

RL

1 kQ

3.3 kQ

R

4.7 kQ

4.7 kQ

CL

8/16

238

E8B-TS9370·05

TS9370
MICROPROCESSOR INTERFACE TIMING AD (0 : 7), AS, OS, RiW, CS, csa
Vee = 5.0 ± 5 %, T A = - 25 'C to + 85°C, C L = 100 pF on AD (0 : 7)
TTL input values are 0 to 3 volts, with input rise/fall time :s; 3 ns, measured between 10 % and 90 %
points. Timing reference at 50 % for inputs and outputs.
Indent.
Number

Symbol

Parameter

Min.

Typ.

Max.

Unit

-

ns

-

ns

1

tCYC

Cycle Time

400

1b

tpEWX

DS Pulse Width High Time

200

1c

tPEWL

DS Pulse Width Low Time (timing 3)

120

2

tAso

DS Low to ASJ::Iigh (timing 1 and 3)
DS High or RIW high to AS high (timing 2)

20

-

3

tASEO

AS Low to DS High (timilJ.!l 1)
AS Low to DS Low or RIW Low (timing 2)

20

-

-

ns

4

tPWEH

Write Pulse Width

200

tpWASH

AS Pulse Width

100

6

tRWS

RIW to DS Setup Time (timing 1)
RIW, AS, CS, CSO to DS Setup Time

20

-

-

ns

5

20

-

-

ns

6b

ns
ns

ns
ns

(timing 3)

7

tRWH

RIW to DS Hold Time (timing 1)

10

-

-

ns

8

tASL

Address and CS, CSO Set Up Time

20

-

ns

9

tAHL

Address and CS, CSO Hold Time

20

10

tosw

Data Setup Time (write cycle)

50

-

-

ns

11

tOHW

Data Hold Time (write cycle)

10

-

-

ns

12

to OR

Data Access Time from DS (read cycle)

-

150

ns

13

tOHR

DS Inactive to High Impedance State Time
(read cycle)

10

-

80

ns

14

tACC

Address to Data Valid Access Time

-

-

300

ns

ns

9/16

239

TS9370
TIMING DIAGRAM 1 - MULTIPLEXED MODE - MOTOROLA TYPE (8MI = Vss)

(i)
os

--\- t-~

0 I---

\

/

'PwEx

'\

®

r - ~0

I
AS

RNi

V[

V

r-...

0

I

.. -0

!)-

X

}
I-

) ' - ~K
(!)
WRITE CYCL.E
.0.010,1 I

-

,.

J
'\ ADDjEj

K) 000

(!)~~
READe YClE
"'DIO:7I

<

.

r-@)

-

\

@

r--0

INPUT DATA

@

ADDRESS

®

--

OVTl'UT
DATA

r--@

J

E88-TS9369-06

10/16

240

TS9370
TIMING DIAGRAM 2 . MULTIPLEXED MODE· INTEL TYPE (SMI = Vss)

o

READCYCLI

'eYC

Ill) IPin DIll

ViRCPinRIW

®
'DDR

AO(0.71-------------{

ADDRESS

®
'ACC

EBB·TS9369·07

1m IPin OSI

ES
CSD

AOIOo7l------------{

EBB· TS9369·0B

11/16

241

T59370
TIMING DIAGRAM 3 - NON-MULTIPLEXED MODE (SMI = Vee)

'PwEx

os
Rlii - - - - - - ' "

cs
CSIl

_ _ _ _ _ _J

'OSW
WRITE CYCLE
AOIO:71

INPUT OATA

'DDR

'OHR 1

2

READ CYCLE
ADID:71

OUTPUT DATA

E88·TS9369-09

DIGITAL VIDEO SIGNALS - HP, P(O:3), BlK, M, RESET
= 5.0 ± 5 %, TA = - 25 'C to + 85 ae. TS9370-20 and TS9370-30

vee

TA = 0 'C to 70 ae. TS9370-45
TTL input values are 0 to 3 volts, with inputs rise/fall time S; 3 ns, measured between 10 % and 90 %
points. Timing reference at 50 % for inputs and outputs.
Symbol

Parameter

TS9370-20

TS9370-30

TS9370-45

Min.

Max.

Min.

Max.

Min.

Max.

Unit

HP Clock Period

50

1000

33

1000

22.5

1000

ns

tPEWH

HP High Pulse Width

20

-

11

-

6

-

ns

tPEWL

HP Low Pulse Width

20

11

-

ns

BLK and P(0:3) Set Up Time to HP

5

5

-

ns

tHO

BLK and P(0:3) Hold Time from HP

10

-

10

-

6

tsu

-

5

-

ns

tD

M Output Delay from HP

-

30

-

30

-

22.5

ns

tPWRL

RESET High Pulse Width

400

-

400

-

400

-

ns

\p

12/16

242

5

TS9370
TIMING DIAGRAM 4

HP

BLK

PO
P3

'0

M

EBB· TS9369·1 0

ANALOG VIDEO OUTPUTS CA,

ca, CC

Vooc = 5V, C L = 20 pF, RL = 100 kO
T A =- 25 'C to + =85 cC, TS9370-20, TS9370-30
o 'C to + 70 cC, TS9370-45
8ymbol

Parameter
Analog Outputs
V White
V Black
Output Impedance
Differential non linearity

189370-20

189370-30

189370-45

Min.

Min.

Min.

Max.

Max.

Unit

2.10

2.16

2.10

2.16

2.10

2.16

V

0.76

0.82

0.76

0.82

0.76

0.82

-

440

-

290

-

230

V
g

- 1/2

+ 1/2

- 1/2

+ 1/2

- 1/2

+ 1/2

LSB

20

ns

Monotonicity

Guaranted

Propagation Delay
CA, CB, CC Outputs from HP

-

tR

10 to 90 % Rise Time

ts

Output Setting Time to 1/2 LSB

tpd

Max.

30

-

30

-

16

-

12

-

8

ns

-

20

-

15

-

10

ns

-

13116

243

159370
TIMING DIAGRAM 5

CA,.C8.CC

EBB-TS9370-07

VIDEO INTERFACE
The function of the video amplifier is to match up the
output impedance of TS9370 with a 75 Q Monitor
input. With the example of video amplifier shown in
figure 2, the output video signal is compatible with
the RS170 video standard.

A lot of care is needed when linking the TS9370 colors outputs to video amplifier.
Currently: 3.4 RC < 0.7 tp
R = output impedance of TS9370 DAC
C = input capacitance of video amplifier
tp = video clock period

Figure 2 : Typical Low Cost Video Interface

TSII370

ct---H

750 __

EBB. TS9370-0B

TSII370

c t - - -....
75fl-...-"lm

EBB-TS9370-09

14116

244

TS9370
ORDER INFORMATION
Part Number
TS9370lP20
TS9370lFN20
TS9370lP30
TS9370lFN30
TS9370CP45

-

Temperature

Package

25 OC to + 85 OC
25°C to + 85 OC
25 OC to + 85°C
25 OC to + 85°C
o °C to 70°C

DIP28
PLCC28
DIP28
PLCC28
DIP28

PACKAGE MECHANICAL DATA
28 PINS - PLASTIC DIP
mm

e:2,54

4.57mox.

Datum
(1)

Nominal dimension

(2) True geometrical position

14

6

28

PINS

15116

245

TS9370
28 PINS - PLASTIC LEADED CHIP CARRIER

mm
11430

~
25

0661
0,812
~
min.

16/16

246

~

4"/

0331
0,533

SGS·THOMSON
IJliJU©~l@m~Iil@IlJU©iI!

28

Outputs

APPLICATION NOTES

247

APPLICATION NOTE

EF9369 COLOR PALETTE
By J.F. FEVRE

DISPLAY UNIT AND MEMORY PLANE
On a monitor, the screen is partitioned into X dots
and Y lines. This number of dots and lines gives the
definition. For example 256 x 256, 640 x 480, etc.

sociated to a gun. So we get a red plane, a green
plane and a blue plane which give eight fixed colors
on the screen.
If more colors are needed on the screen at the same
time, more memory planes must be used.

Each dot or pixel is associated with a bit in a memory plane. On a monochrome monitor, each pixel will
be on or off according to its value in the memory
plane. That kind of monitor has got only one gun to
drive the screen.

With n planes it will be possible to get 2n colors on
the screen at the same time. But in this case, the
problem is to deal with the three red, green and blue
inputs of a color monitor.

A color monitor owns three guns (a red, a green and
a blue) since it is known that all the colors are available with these three primary colors.

Another problem is that all these sets of colors are
fixed, and most of the time, in a graphic application
much more colors are needed.

To drive these three guns, at least three memory
planes are needed. Each memory plane can be as-

All these problems can be solved by using the
EF9369 single chip color palette.
r-------::1

n,

1
1

I
1
I
I

~L-_ _ _..,2

I

T--..J
I

1

L--,-----.....,.-,-...J

___ 1_.
~

,n I

t-----,

.....-1H---X---::~:-)

1

____ J,
VIDEO

I

~Q

A

ADOAD7

A8·A16

~

~

ADI071

ADDRESS
DECODER

CS
EF9345

AL~

AS

AD

OS

WR

R/W

-

E88-AN44T-02

3/38

263

APPLICATION NOTE
Figure 3 : Interface with EF6800/6809 by Multiplexing Address and Data Bus.

A8
A9
Al0
All
A12
A13
A14
A15

ADDRESS

12 MHZ CLOCK

DECODER
74 LS D2

~D2
04~
~
Q2 ~
6
9 I
10

1

~

R/Vii

DO
01
D2
D3

D4
D5
D6
D7

E

RIW

6 D3"l
13
03 ;t D5

&

5

E

74lS00

~
2

&

9

19
1I
18
B1
A1
17 B2
A2
16 B3
A3
15 B4
A4
14 B5
~ A5
13 B6 ;t A6
12 B7
A7
11 B8
A8

~

CK~

2 01

&

2

3
4
5
6
7
8

9

~

1104

~~122~1

&

12

ADO
AD1
AD2
AD3
AD4
ADS
AD6
AD7

u:i:

>

/

/
/
/

G
16

26

DS

AS

A/iN

ClK

14

-12

CS

/
/
/
EF9345

EF 68OO/faJ9

AD
Al
A2
A3
A4
AS
A6
A7

2
4
6
8
11
13
15
17

18
1Yl
1A1
16
1Y2
1A2
14
1A3 ~ 1Y3
12
1A4 N 1Y4
9
2A1 ~ 2Y1
7
2A2 .... 2Y2
5
2Y3
2A3
3
2Y4
2A4

TI

11

/
/
/
/

/
/
/

17
18
19
21
22
23
24
25

ADO
AD1
AD2
AD3
AD4
ADS
AD6
AD7

TI

119
E88-AN44T-03

4/38

264

APPLICATION NOTE
Figure 4: Timing Diagram Associated with Figure 3.

-

---

--..------

-

..---

-

,---

-

-

---

-~

w

-/
...-

"

/-

'----

v--

7--

~

../

~

..,
0

C'i

II~
E88-AN44T-04

5138

265

APPLICATION NOTE
Figure 5 : Interface with EF6800/6809 without Multiplexing Address and Data Bus.

eso

J

5

IORO

6

A7

E2

Y6

9

E3

RD

A6

~

A5

T

G

4
3
2
1

YO
El
A2
A1

15
16

Y2
15

WI1

CSl

13

74LS138

CSO

~J>

(}1

CLK

DS

26

.1
OV

~

CD

s:~-

AS

~

CS

N

eX>

0

~s:
0

AD

s.
s:
c

!lien

"n
~C(J

Z-80A

~i!

RESET
CLK

!li0
~!I
",en

EF9345

II

HPI4 MHz)

»
a.
a.

17
DO
18
D1
19
D2
21
D3
D4

22
23

D5

24

m
00

06

»
z

07

'f

""

"
o

--J

'"
ex>

ro
x

S-

~z

I::::J

;:+

-6<0

-0

I\)
m
-..j

OJ

::::j,

14

.--

12 MHz

m

~/W

25

m
ADO

(fl
(fl

~

OJ

AD1

a.

AD2

0

El~

AD3

OJ

c
AD4

~

I~
'tI
r

AD6

n
~

AD7

0

AD5

-I

Z
Z

0
-I
m

APPLICATION NOTE
MEMORY INTERFACE
The EF9345 can be used with a wide variety of
standard memories and manages up to 16 kbytes
of private memory.

As previously, refresh operation is performed by the
EF9345.

PROGRAMMING THE EF9345 - GENERAL
PRINCIPLES

The memory interfaces is made by :
an S-bit address/data multiplexed bus ADM(0:7)
a 6-bit high order address bus AM(S:13)
three control signals: OEJQutput Enable), ASM
(Address Strobe Memory), WE (Write Enable).
During each memory cycle, the EF9345 outputs to
ADM(0:7) low order address byte while ASM is high.
The high order address bits are provided on
AM(S:13) during the whole memory cycle. When
ASM goes low, the ADM(0:7) lines become the memory data bus. For a read operation, the OE signal
is active low to enable the memQfY. output buffers.
A write operation is made when WE is low.
INTERFACE WITH 2K*S STATIC MEMORY
As the address lines are generally not latched by
static RAMs, an externalS-bit latch (74LS373) must
be used to store the low order address bits
ADM(0:7) on the falling edge of ASM signal.

DIRECT ACCESS REGISTERS
As described in the microprocessor interface
chapter, the EF9345 is accessed by the microprocessor at 16 consecutive locations from address
XX20 to XX2F (hexadecimal), where XX is determined by the user's address decoding. These 16 addresses correspond to S internal registers RO to R7
(see figure 10). Each register can be accessed at
two addresses: a lower address (bit 3 = 0) and an
upper address (bit3 = 1). Forexample, if the EF9345
is mapped in the microprocessor addressing space
from F420 to F42F, register R1 can be read or written at both addresses F421 and F429.
However, a command present in register RO is executed only after an access to a register at an upper
address. This scheme allows re-executing a same
command by loading only one argument into an upper address register.
COMMAND EXECUTION

INTERFACE WITH SK* S PSEUDO-STATIC RAM
The EF9345 can be directly connected to an SK*S
pseudo-static RAM (NEC fLPD 416S, INTELl1S7,
INMOS 2630 ... ). The ASM signal is fed to the CE input which latches the address lines. As the EF9345
performs DRAM refresh, the memory internal refresh circuitry is not use.
The schematic diagram of figure S gives a design
example which allows interfacing the EF9345 to
2K*S or SK*S memory. With static memory, the S
jumpers of SS are connected to provide the low order address lines from the S-bit latch 74LS373. With
pseudo-static memory, the 74LS373 is useless and
the S jumpers of S7 are connected. Jumpers S1 to
S6 are set in position 2 for 2K*S RAMs, and in position 1 for SK*S RAMs.
INTERFACE WITH 16K*S DRAM (see figure 9)
When using 16K*4 dynamic RAMs, the address provided by the EF9345 must be multiplexed to obtain
the Rowand Column address. ASM can be used directly as the RAS (Row Address Strobe) signal, but
the CAS signal must be externally generated. Figure
9 shows an example of generating CAS and the multiplexer command signals from ASM.

8/38

268

RO is a write command register and a read status
register. A command present in RO is executed with
the arguments in the other direct access registers
after any access to a register at an upper address
(from XX2S to XX2F).
Before any access to a register, the Busy status in
the Status register bit 7 must be tested to check a
command is not currently executing. However, after
power-up a NOP command should be executed
without testing the Busy state to set the circuit into
a determined state before further operation. A move
command with no stop condition can also be aborted by executing a NOP command.
INDIRECT ACCESS REGISTER (figure 11)
The EF9345 has 5 indirect access registers which
define the various operating modes of the circuit:
TGS, MAT, PAT, DOR, ROR. Each of these registers is assigned an index r and is indirectly accessed through register R1 . Data is transfered between
R1 and an indirect access register with the INDcommand, which specifies the transfer direction (bit
R/W) and the register index r (bits 0 to 2).
Flowchart of figure 12 gives an example of indirect
access register loading.

APPLICATION NOTE
Figure 8: EF9345 Interface with 2K x 8 and 8K x 8 Memory.

·5· CAPO.

".m

c-Ie,

""Ea"'"
... .
a?...

:

-

-=

.."

rt

••-

Ie.

..
,.

lCO

2.

IC7

2.

Ie<

'"

as

c.
Cf

es

c.
eB
coo

...
IJ"

--7

..
7

1

c.

..
..... .. ..~.
s-

+.4.7......

AU

... .
. .. . ..._....
.
•

..

ao<

~t50

---..1:
rt

~i~
slot-'

..

G

U""'vW

"'
-

R'

Ie",

;j

~

rE,lc;~

to

I:

-~
"C$fv«.

..

~

59

n,

"

~a·

.:!.

I

CL

11'8/11$:-

~I!'
!

~

L---~~~--~~_r_r~~

i. . ---+

~ ~
fz~r~
... ':.
5.

""1

.n,F

(1'

'150...

pq,..~
~

6

..."' ...

'"

5.3

t. _ i

ES8-AN44T-OS

9/38

269

APPLICATION NOTE
Figure 9: Interface with 16 x 4 Dram.

.Y

15
3

AOMO
ADM 1
AOM2
AOMJ

18
S 28
10 38
13
48

~

lV~
2V~
9 A2
3v
4V 112 A3

~

2A 74LS157
3A
1
4A
SEL I-ovr-l lA
16
ov 81
5V
OV
15
ADM4 3
lB
lY
AOM5 6
28
2V
AOM6 10
3B
3Y
I-AOM7 13
48
3Y P"- I-AA
2A74LS151
AMID 14

1

12 MHz CLOCK

f4.f-f- ~
~

~

~

elK 12
_
4
ASM

OV~

~

~
~
~
~

AM"
AM91
AM10
AMIl
AMI2
AMI3

WE

~
~

~
~
3

OE 2

~

SEL

,~~

~

AOMD
AOMI
AOM2
AOM3
AOM4
AOM5
AOMS
AOM7 32

3A
4A

OV

5V

OV

5V

7T
ASM

2

3 CKI

_

~

11

5V

T14

74lS 74
01
01

CK2

02
Q2

'l"l1{13J

~
13

~
rir4

r-i
r1o'

r-=

2
3
15
A2 ~ OQ3
17
A3" OQ4
1
AO
Al

~

A4
A5

CD

001
002

~ ~
W

AOMO
AOMI
AOM2
AOM3

-

-

4

AS-AilS 5
AI
CAS 16

1

ov 18

19

5V

14

AD
Al :;;
12 A2 
LOAD AND EXECUTE COMMAND.

=

00127A
00128A
00129A
00130A

00139A 1068 33

LOAD VALUE INTO R1

CLEAR PAGE MEMORY WITH ALPHANUMERIC SPACES
FOREGROUND AND BACKGROUND COLORS
BLACK

A
A

00124
00125

BUSY
I/S08
Rl
I/S87
R0+8

O,U
II SO 4
ET2

BLOCK NUMBER ZC3:0>
INITIAL CHA R CODE C BYTE
SAVE ACC. A &B INTO U STACK
SLICE BUFFER ADDRESS
GET ARGUMENTS FOR WR SLAL
SLICES LOADED FOR 4 CHAR?
YES, BRANCH
NO, LOAD TEN SLICES
INCREMENT CHAR CODE C BYTE

UPDATE U POINTER

WRITE THE 4 UDS CHAR CODES INTO PAGE MEMORY.
BACKGROUND = BLACK, FOREGROUND = WHITE: A BYTE = $70

00144A 106D BD
00145A 1070 86
00146A 1072 B7

lODB
01
F420

A
A
A

JSR
LDA
STA

00148A 1075 86

26
F427

A

LDA

1138

INIT MAIN POINTER TO [OLI..J'II:N 38". ON THE Fl

A

R7

ROW AFTER SERVICE ROW

08

A

F426

A

STA
LDA
STA

00149A 1077 B7
00150A 107A 86
00151A 107C B7

22/38

282

BUSY
IlS01
RO

LOAD "KRF" COMMAND WITH CURSOR INCREM.
NO EXECUTI ON !

118
R6

Gi
SGS·THOMSON
~I ilim©DiI@rn~rn©1i'DiI@1Il0©$

APPLICATION NOTE

PAGE

004

EF40

.SA:O
STnRE CHAR CODE B BYTE INTO R2

00153A
00154A
00155A
00156A

107F
1081
1084
1086

86
87
86
87

80
F422
70
F423

A
A
A
A

LOA
STA
LOA
STA

#S80
R2
#S70
R3

00158A
00159A
00160A
00161 A
00162A
00163A

1089
1088
108E
1091
1092
1095

86
87
BD
4C
B7
BO

00
F429
1008

A
A
A

#SOO
Rl+8
BUSY

F429
10DB

A
A

LOA
STA
JSR
INCA
STA
JSR

1098 86
00166A 109A B7
00167A 1091> 86
00168A 109F B7

26
F427

LOA
STA
LOA
STA

11311

INIT MAIN POINTER FOR THE 2 LOWER CHAR

F426

A
A
A
A

R7
#9
R6

Y=9

02
F429
1008

A
A
A

#S02
Rl+8
BUSY

F429

A

LOA
STA
JSR
INCA
STA

0016~A

00170A
00171 A
00172A
00173A
00174A

10A2
10A4
10A7
10AA
HlAB

86
B7
BO
4C
B7

09

*

00176
00178A
00179A
00180A
00181A

10AE
1080
10B2
10B5

86
C6
8E
BO

03

4B
118F
1149

LOA
LOB
LOX
JSR

*
*

*

*

WRITE THE UPPER RIGHT CHAR
Rl+8
BUSY

IlS03
IIS4B
#QUADRI
WRSLAL

Bo
86
B7
86
B7

100B
14
F427
14
F426

A
A
A
A
A

JSR
LOA
STA
LOA
STA

BUSY
1120
R7
1120
R6

00194A
00195A
00196A
00197A
00198A
00199A
00200A
00201 A

10C5
10C7
10CA
10CC
10CF
1001
1004
1006

86
B7
86
B7
86
B7
86
87

01
F420

A
A
A
A
A
A
A
A

LOA
STA
LOA
STA
LOA
STA
LOA
STA

#SOl
RO
#S4B
Rl
#SDII
R2
11502
R3+8

BRA

HERE

00203A 1009 20

FE

BLOCK NUMBER Z<3:Ol
CHAR CODE C BYTE
SLICE BUFFER ADDRESS

WRITE THE QUADRICHROME CHAR COOE INTO PAGE MEMORY
PALETTE = RED-BLUE-CYAN-WHITE : A BYTE = S02
QUAORICHROME SET Q3, HIGH RESOLUTION (R=O) : B BYTE
C BYTE = S4B

10B8
10BB
lOBO
lOCO
10C2

F421
08
F422
02
F42B

WRITE THE 2 LOWER CHAR

Rl+8

00188A
00189A
00190A
00191 A
00192A

4B

WRITE THE UPPER LEFT CHAR

LOAD THE 10 SLICES FOR THE QUAORICHROME CHARACTER

A
A
A
A

00183
00184
00185
00186

CHAR CODE A BYTE INTO R3

1009 HERE

INIT MAIN POINTER

S08

X=20

Y=20

LOAD "KRF" COMMAND
LOAD CHAR CODE C 8YTE INTO
CHAI/ CODE B

iHI~

Rl

INIO 1/2

CHAR CODE A BYTE INTO R3 AND
EXECUTE TRANSFER COMMAND

23/38

283

APPLICATION NOTE

PAGE

005

EF40

.SA:O

00205
00206
00207
00209
00210A 10DB 7D
00211A 10DE 2B
00212A 10EO 39

**

BUSY: TEST BUSY STATE IN STATUS REGISTER BIT 7.

*
10DB
A BUSY
F420
A
FB
10DB

00214
00215
00216
00217
00218
00219
00220

EQU
TST
Bill
RTS

*

• IIPFIll

*
*
*
*
*

*RO
BUSY

lOOP IF BIT 7

=1

FIll THE 3-BlOCK PAGE IIEIIORY STARTING FROII BLOCK 0
WITH THE SAllE lONG CHARACTER CODE
ENTRY : THE 1RST BLOCK IS FILLED WITH ACC. A CONTENTS
THE 2ND BLOCK WITH X REG. (IISB) CONTENTS
THE 3RD BLOCK WITH X REG. (lSB) CONTENTS.

00222

10E1

A MPFIll EQU

*

00224A 10E1 BD
00225A 10E4 B7
00226A 10E7 BF

10DB
f421
F422

A
A
A

JSR
STA
STX

BUSY
R1
R2

00228A 10EA 4F
00229A 10EB B7
00230A 10EE B7

F426
F427

A
A

ClRA
STA
STA

R6
R7

00232A 10F1 86
00233A 10F3 B7

05
F428

A
A

lDA
STA

II SO 5
R0+8

o0235A

10F6 8E
00236A 10F9 30
00237A 10FB 26

0700
A
lDX
1F
II FIlL30 lEA X
FC
10F9
IlNE

112000
-1,X
FllL30

WAIT ABOUT 15 IIIlLISECONDS

00239A 10FD 86
00240A 10F F B7

91
F428

IIS91
R0+8

EXECUT E II "NOP" COl'lllAND
TO ABORT "ClF"

00242A 1102 39

24/38

284

A
A

lDA
STA
RTS

TEST BUSY STATUS
STORE CHAR CODE INTO R1,R2,R3

INIT llAIN POINTER TO THE BEGINNING
OF THE SERVICE ROW : R6 = R7 = O.

lOAD AND EXECUTE "ClF" COllllAND

APPLICATION NOTE

PAGE

006

EF40

00244
00245
00246
00247
00248
00249
00250
00251
00252
00253
00254
00255
00256
00257
00258

.SA:O

1103

*
* AXPNT AUXILIARY POINTER SET SUBROUTINE
* ENTRY ACC.A = o-o--O-0-Z3-Z2-l1-z0
ACC.B = o-C6-C5-C4-C3-C2-C1-CO, WHERE C(0:6)
*
IS BYTE C OF CHAR. CODE
*
* EXIT : R4 = YA = G-O-Z2-C6-C5-C4-C3-C2
R5 = XA" = Zo-Z1-o--0-0-0-C1-CO
*
** OPERATIONR6(6)=YPC6)=z3
TEMPORARY STORAGE ~
I'ICO,S) = zo--Z1-o--o--0·-o--0-0
*
1m,S) - o-o--Z2-o--o--0-o--0
*
I'IC2,S) = 0-0-0-0-z3-Z2-Z1-Z0
*
M(3,S) = o-C6-C5-C4-C3-C2-C1-CO
*
*
A AXPNT EQU
*
-4,S
2,S

RESERVE 4 BYTE TEMPORARY STORAGE
SAVE ARGUMENT A & B.

A
A

LEAS
STO

98

A

CLRB
RORA
RORA
RORA
RORB
ROLA
RORB
ROLA
RORB
TFR

B,A

B7=ZO,B6=Z1,B5=l2
DUPLICATE RESULT INTO ACC.A

00274A 1112 C4
00275A 1114 84
00276A 1116 ED

20
E4

A
A
A

ANOB
ANOA
STO

"120
lISCO
O,S

B = 0-0-Z2-0-0-0-0-0
A = zo--Z1-o--0-0-0-0-0
SAVE A & B

00278A
00279A
00280A
00281A
00282A
00283A
00284A
00285A
00286A
00287A

100B
63
03
E4
F425
63

A
A
A
A
A
A

BUSY
3,S
"$(]3
O,S
R5
3,S

RESTORE INITIAL ARGUMENT
KEEP ONLY THE 2 LSB
B = zo--Z1-o--0-o--0-C1-CO
STORE INTO R5=XA

61
F424

A
A

JSR
LOB
ANOB
ORB
STB
LOB
LSRB
LSRB
ORB
STB

00260A 1103 32
00261 A 1105 ED
00263A 1107
00264A 1108
00265A 1109
00266A 110A
00267A 110B
o 026 SA 110C
00269A 1100
00270A 110E
00271 A 110F
00272A 1110

1118
111B
1110
111F
1121
1124
1126
1127
1128
1i2A

5F
46
46
46
56
49
56
49
56
1F

BO
E6
c4
EA
F7
E6
54
54
EA
F7

7C
62

co

CY=Z2,A7=Z1,A6=ZO.
B7=Z2
B7=Z1,B6=Z2

1,S
R4

B = 0-0-0-C6-C5-C4-C3-C2
B = 0-0-Z2-C6-C5-C4-C3-C2
STORE INTO R4 = YA

25/38

285

APPLICATION NOTE

PAGE

007

EF40

.SA:O
A
A
113E
F426
A
40
A
F426
A

LOA
ANDA
BEQ
LDA
ORA
STA

2,S
11$08
AXPNT5
YP
11$40
YP

RESTORE Z3-Z0 ARGIJt1ENT
TEST Z3

00296A 113B 32
00297A 1130 39

64

A

LEAS
RTS

4,S

UPDATE STACIC POINTER

00299A 113E B6
0030DA 1141 84
00301A 1143 B7

F426
BF
F426

A AXPNT5 LOA
A
ANDA
A
STA

YP
IISBF
YP

Z3=0 : YP(6)=0.

00303A 1146 32
00304A 1148 39
00305
00306
00307
00308
00309
00310
00311
00312
00313
00314
00315
00316

64

A

4,S

UPDATE STACIC POINTER

00318A 1149 BD

1103

A WRSLAL JSR

00320A 114C 86
00321A 114E B7
00322A 1151 C6

34
F420
OA

A
A
A

00324A 1153 A6
00325A 1155 B7
00326A 1158 BD

80
F429
10DB

A WRSLA1 LDA
A
STA
JSR
A

00328A 115B 86
00329A 1150 BB
00330A 1160 B7

04
F425
F425

A
A
A

LDA
ADDA
STA

R5
R5

00332A 1163 5A
00333A 1164 26

ED

1153

DECB
BNE

WRSLA1

00289A
00290A
00291A
00292A
00293A
00294A

1120
112F
1131
1133
1136
1138

A6
84
27
B6
SA
B7

00335A 1166 39

26/38

286

62

08
DB

LEAS
RTS

**
*
*
*
*
**
*
*
*
*

Z3=1 : YP( 6)=1.

WRSLAL : WRITE 10 UDS SLICES.
ACC.A = 0-0-O-o-Z3-Z2-Z1-Z0, WHERE z(3:0) IS
ENTRY
BASE ADDRESS FOR UDS SLICES.
ACC.B = o-C6-C5-C4-C3-C2-C1-CO, WHERE C(0:6) IS
BYTE C OF CHAR CODE
X POINTS TO THE SLICE BUFFER.
A & B DESTROYED
EXIT
X = X + 10.
AUXILIARY POINTER IS USED : BIT 2 = p OF
"BYTE LOAD" COMMAND =1

LDA
STA
LDB

RTS

AXPNT

SET AUXILIARY POINTER.

11$34

"BYTE WRITE COMMAND "
STORE COMMAND WITHOUT EXEC.
INIT LOa> COUNTER FOR 10 SLICES.

RO

1110
O,X+
R1+8
BUSY

STORE A SLICE AND EXECUTE
TRANSFER INTO MEMORY

11504

INC. SLICE CNTER = R5(5:2)

DEC. LOa> COUNTER

APPLICATION NOTE

PAGE 008 EF40
00337
00338
00339
00340A
00341A
00342A
00343A
00344
00345
00346
00347A

.SA:O

**
1167
1171
117B
1185

118F

SlICE VAlUES FOR UOS CHARACTERS OF FIGlRE 15

*

20
04
07
EO

A CAR1
A CAR2
A CAR3
A CAR4

9r

** SLICE VALUES FOR QUADRICHROME CHARACTER (FIGlRE 16)
*
S9C,S5A,SA3,S6A,SA9,SBE,S92,SEB,S29,SB6
A QUADRI FCB

00349
TOTAL ERRORS 00000--00000
TOTAL WARNINGS OOOPO--oOOOO

FCB
FCB
FCB
FCB

S20,S38,S3C,S3E,S3F,S3F,S1F,S1F,SOF,SOF
S04,S1C,S3C,S7C,SFC,SFC,SF8,SF8,SFO,SFO
S07,SC7,SE3,SF3,SF9,SFC,SFC,SF8,SEO,S80
SEO,SE3,SC7,SCF,S9F,S3F,S3F,S1F,S07,S01

END

PROGRAMMING THE EF9345 IN 80
CHAR/ROW MODE

CHARACTER CODE (figures 20 and 21)
In 80 char/row mode, the screen is made of 25 or
21 rows of 80 characters.
Each character is displayed in a 6 pixels by 10 lines
window, which is associated with a character code
in a page memory.
For a page, one of two character code formats must
be selected:
• Long codes (12 bits), which consist of a C byte
and an attribute A nibble.
• Short codes (8 bits), which consist of only a C byte
(see figure 20).

PAGE MEMORY
With long character code format, a page memory
consists of three 1 Kbyte blocks. The same rules as
in 40 char/row mode apply to page memory selection.
The first (resp. second) block holds the C bytes of the
characters in even (resp. odd) position on the rows.
Every two consecutive characters have their A nibble
concatened to make a byte stored in the third block.
Short character codes are similarly packed in two
consecutive blocks which hold only C bytes.
ACCESS TO CHARACTER CODE
KRL command performs long character code transfer between registers R1-R3 and the memory. R1 is
used for C byte transfer and R3 for A nibble transfer. When loading a character code, the A nibble
must be repeated in R3.

With short codes, the C byte selects one of the 128
intemal alphanumeric characters (Go set), and characters are displayed without attributes.

KRC command is similarly used for short character
code access between R1 and the memory.

Long code format provides an additional 1024 mosaic character set and four attributes: D (color select), N (negative), U (underline) and F (flash). For
each character, the foreground/background colors
and the insert attribute are selected by bits D and N
from the values programmed in DOR and MAT
registers.

Both KRL and KRC commands use the Main Pointer (R6, R7) for memory addressing. With a page
memory starting from block number Z(0:3), R6 holds
the Y row number and Z3-Z2. As the character position on a row is given by X(0:5) and ZO, it must be
transcoded to obtain the R7 value with ZO-Z1 in the
most significant bits (see figure 22).

27/38

287

APPLICATION NOTE
Figure 20 : 80 Char/Row Character Code.

4

6

o

3

o

3

---------------

6

5

o

4

3

~

A

C

C

ALPHANUMERIC CHAR CODE

o

2

MOSAIC CHAR CODE

I...

N = Negative
F = Flash

U ~ Underline
D = Color set

o

128 ALPHANUMERICS
In GO set.

3

I

2
4

5
6
7

8
9

....I

3 pels

3 pels

co

CI

C2

C3

C4

C5

C6

Al

A2

A3

... I
i
DEDICATED
MOSAIC
SET

E88-AN44 T-21

Figure 21 : Color Selection.

65432
DaR

i,

I

B,

I G, I R,

I I
io

--------I
Cl
I

0

So I Go I RO

I

Co

I
_0=' __1
_0=0_
I
I

The pixel shift frequency is fClK (12 MHz).

288

N

~

I
I

28/38

0

BACKGNO

FOREGNO

COLOR

COLOR

i

0

0

CM

Co

iO

0

1

Co

CM

,0

0

CM

Cl

il

1

C,

CM

il

,
,

E88-AN44T-22

APPLICATION NOTE
Figure 22 : Transcoding an Horizontal Screen Location into a R7 Pointer.

7

6

I I
bl

543

o

2

I

------X5 , X41 X3, X2 1 XI

I XO I bO

Character position (0 to 79)

Rotate right

...

I

7

6

bO

I bl

!

Block parity

5

I

4

X5, X4

3

2

o

I X3 1 X2 I XI I XO

I

X.~'o'"
E88-AN44 T-23

29/38

289

APPLICATION NOTE
PROGRAMMING THE EF9345 IN 80 CHAR/ROW MODE
PAGE

001

EF80

.SA:O
OPT

00001

LLE=110

,.

00003
00004
00005
00006
00007
00008
00009

,. EF9345 PROGRAMMING EXAMA...E IN 80 CHAR/ROW
THIS PROGRAM IS WRITTEN IN 6809 ASS8'lBlER LANGtMGE.
AFTER INDIRECT REGISTERS INITIALIZATION, TWO
CHARACTER STRINGS ARE DISPLAYED AND A ROLL-UP
OPERATION IS MADE.

*
*
*
*
*
*

00011

EF9345 REGISTER ADDRESS

00013
00014
00015
00016
00017
00018
00019
00020

F420
F421
F422
F423
F424
F425
F426
F427

A RO
A R1
A R2
AR3
A R4
A R5
A R6
A R7

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

SF420
R[)fo1
R[)fo2
R[)fo3
R[)fo4
R[)fo5
R[)fo6
R[)fo7

00022
00023
00024
00025

F425
F424
F427
F426

A
A
A
A

EQU
EQU
EQU
EQU

R5
R4
R7
R6

00027
00028

4000
3F80

A STACK EQU
A STACKU EQU

XA
YA
XP
YP

0OO3OA 1000
00032

1000

00034A 1000 10CE 4000
00035A 1004 CE
3F80
00037A 1007 86
0OO38A 1009 B7

91
F428

A MAIN

EQU

,.

A
A

LDS
LDU

'STACK
.STACKU

STACK INITIALIZATION

A
A

LDA
STA

.S91
R[)fo8

LOAD AND EXECUTE A "NOP" COMMAND
WITHOUT TESTING BUSY

**
,.
*
,.
*
*
*
,.
,.*

TGS REGISTER INITIALIZATION :
TGSO = 0
625.LINES (50 HZ)
TGS1 = 0
NOT INTERLACED
TGS2 = 0
HORIZONTAL RESYNC. DISABLED
TGS3 = 0
VERTICAL RESYNC. DISABLED
TGS4 = 0
HORIZONTAL SYNC. ON HVS/HS PIN AND
VERTICAL SYNC. ON PC/VS PIN
TGS5
0 : SE~ICE ROW Y = 0
TGS(7:6) = 11 : 80 CHAR/ROW MODE, LONG CHAR CODE (12 BITS)

=

cO

A
A

JSR
LDA

00054A 1011 B7
00055A 1014 86
00056A 1016 B7

F421
81
F428

A
A
A

STA
LDA
STA

290

$4000
STACK-128
$1000

00052A 100t BD
00053A 100F 86

30/38

AUXILIARY POINTER (Y)
AUXILIARY POINTER (X)
MAIN POINTER (Y)
MAIN POINTER (X)

ORG

00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
10D2

COMMAND/STATUS REGISTER
DATA REGISTERS

L'W'I
OJ,

BUSY

.seD

LOAD VALUE INTO R1

R1

.$81
R[)fo8

"IND" COMMAND TO LOAD TGS (r=1)
LOAD AND EXECUTE COMMAND.

SGS·THOMSON

IiiIOcmmn.IiC'II!j@ll!]OC3

APPLICATION NOTE

PAGE

002

.SA:O

EF80

00058
00059
00060
00061
00062
00063
00064
00065
00067A
00068A
00069A
00070A
00071A

**
*
*
*
*
*
*
1019
101 C
101 E
1021
1023

BD
86
B7
86
B7

10D2
4C
F421
82
F428

A
A
A
A
A

00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00085A
00086A
00087A
00088A
00089A

BD
86
B7
86
B7

10D2
7F
F421

83
F428

A
A
A
A
A

00091
00092
00093
00094
00095
00096
00098A
00099A
00100A
00101A
00102A

JSR
LDA
STA
LDA
STA

**
*
*
*
*
*
**
*
*
1026
1029
102B
102E
1030

BD
86
B7
86
B7

10D2
8F
F421
84
F428

A
A
A
A
A

BUSY
IISitC
R1
. IIS82
R0+8

LOAD VALUE INTO R1
"IND" COMMAND TO LOAD MAT (r=2)
LOAD AND EXECUTE COMMAND.

PAT REGISTER INITIALIZATION :
SERVICE ROW ENABLED
PATO = 1
PAT1 = 1 : UPPER BULK ENABLE'
PATZ = 1 : LOWER BULK ENABLED
PAT3
1 : CONCEAL ENABLED
PAT(5:4)
11 : I SIGNAL IS HIGH DliUNG THE
ACTIVE DISPLAYED AREA.
FLASHING ENABLED
PAT6
1
80 CHAR/ROW MODE, LONG CODE
PAT7

=

=

=
=a

JSR
LDA
STA
LDA
STA

**
*
*
*
*
1033
1036
1038
103B
103D

MAT REGISTER INITIALIZATION :
MAT(2:0) = 100 : MARGIN COLOR = BLUE
MAT3 = 1 : I SIGNAL IS HIGH DURING MARGIN PERIOD
MAT(5:4) = 00 : FIXED COMPLEMENTED CURSOR
MAT6 = 1 : CURSOR DISPLAY ENABLED
MAT7 ~ 0 : NO ZOOM MODE

BUSY
IIS7F
R1
11$83
R0+8

LOAD VALUE INTO R1
"IND" COMMAND TO LOAD PAT (r=3)
LOAD AND EXECUTE COMMAND.

DOR REGISTER INITIALIZATION :
DOR(3:0)
1111 : COLOR
WHITE
DOR(7:4)
1000 : COLOR C1
BLACK
INSERT ATTRIBUTE ; IS SET FOR ANY CHARACTER.

=
=

JSR
LDA
STA
LDA
STA

co =

=

BUSY
IIS8F
R1
IIS84
-R0+8

LOAD VALUE INTO R1
"IND" COMMAND TO LOAD DOR (r=4)
LOAD AND EXECUTE COMMAND.

31/38

291

APPLICATION NOTE

PAGE

003

EF80

.SA:O

00104
00105
00106
00107
00108
00110A
00111A
00112A
001BA
00114A
00116
00117
00118
00119
00120A
00121A
00122A
00123A

**
*
*
*
1040
1043
1045
1048
104A

104D
104F
1052
1054

BD
86
B7
86
B7

86
8E
C6
BD

10D2
28
F421
87
F428

20
2000
04
1008

ROR REGISTER INITIALIZATION :
ROR(4:0)
01009 : ORIGIN ROW
8
001 : DISPLAYED PAGE JIIEMORY STARTS FROM BLOCK 0
ROR(7:5)

=
=

JSR
LDA
STA
LDA
STA

A
A
A
A
A

**
*
*
A

*
*
*
*

BUSY

11$28

LOAD VALLE INTO R1

R1

11$87
R0+8

"IND" COM""'ND TO LOAD ROR (r=7)
LOAD AND EXECUTE COM""'ND.

CLEAR PAGE JllEJIIORY WITH ALPHANUMERIC SPACES
BACKGROUND COLOR = CM (MARGIN COLOR)
LOA
LDX
LDB
JSR

A
A
A

00125
00126
00127
00128

=

11$20
11$2000

114

C BYTE FOR EVEN POSITION CHAR.
C BYTE FOR ODD POSITION AND A Nmll..ES
PAGE JllEJIIORY FIRST BLOCK NUMBER

JIIPFILL

WRITE "ABCD ..... WITH FLASH AND NEGATIVE ATTRIBUTES
ATTRIBUTE BITS (D,N)=01 :
BACKGROUND COLOR
CO DEFINED IN DOR
FOREGROUND COLOR = CM (MARGIN COLOR)

=

00130A 1057 BD
00131A 105A 86
00132A 105C B7

10D2
51
F420

A
A
A

JSR
LDA
STA

00134A
00135A
00136A
00137A

86
B7
86
B7

28
F426
00
F427

A
A
A
A

LOA
STA
LOA
STA

R6
IlSOO
R7

00139A 1069 86
00140A 1068 B7

CC
F423

A
A

LOA
STA

IISCC
R3

LOAD ATTRIBUTE NIBBLE (REPEATED
INTO R3).

00142A 106E C6
00143A 1070 86

OA
41

A
A

LDB
LDA

1110
li'A

LOOP COUNTER FOR 10 CHARACTERS
FIRST CHAR CODE C BYTE

00145A1072
00146A 1075
00147A 1076
00148A 1079
00149A 107A

F429

A LOOP

10D2

A

STA
INCA
JSR
DEeB
BNE

105F
1061
1064
1066

B7
4C
BD
5A
26

F6

1072

BUSY

11$51
RO

LOAD "KRL" COMI'IIINO WITH
CURSOR INCREMENTATION

11$28

INIT ""'IN POINTER (CURSOR)

R1+8

STORE C.C. C BYTE AND EXEC COMJllAND
INCREMENT C BYTE

BUSY
DEe LOOP COUNTER
LOOP

32/38

292

(

APPLICATION NOTE

PAGE

004

.SA:O

EF80

*
*

00151
00152
00153

*

WRITE '"KLI'I •••• '" WITH UNDeRLINING
(D,N) = (0,0) : BACKGROUND COLOR = CM
FOREGROUND COLOR = CO

86
B7
86
B7

2A
F426
00
F427

A

LOA
STA
LOA
STA

#S2A
R6
II$(] 0
R7

INIT CURSOR

A
A
A

00160A 1086 86
00161 A 1088 B7

22
F423

A
A

LOA
STA

1IS22
R3

ATTRIBUTE Nmlll.E INTO R3

00163A 1088 C6
00164A 108D 86

OA

4B

A
A

LDB
LOA

1110
II'K

00166A
00167A
00168A
00169A
00170A

STA
INCA
JSR
DECB
BNE

R1+8

00155A
00156A
00157A
00158A

107C
107E
1081
1083

B7
4C
BD
5A
26

F429

A LOOP1

1002

A

00174A 1099 BD

10D2

A

JSR

BUSY

00176A 109C 86
00177A 109E B7

8F
F428

A
A

LOA
STA

IIS8F
R0+8

EXECUTE "IND" COMMAND TO READ ROR REGISTE

00179A 10A1 BD
00180A 10M B6

10D2
F421

A
A

JSR
LOA

BUSY
R1

COMMAND EXECUTED?
READ RESULT FROM R1

00182A 10A7 C6
00183A 10A9 F7

87
F420

A
A

LDB

#S87
RO

STORE "IND" COMI'IAND FOR LOADING ROR

00185

10AC

A LOOP3

EQU

*

F429
1002
10C6

A
A
A

R1+8
BUSY
WAIT

02
1F
1F
02
EC

A

STA
JSR
JSR
INCA
PSHS
ANOA
CMPA
PULS

BNE

LOOP3

ANDA
ADDA
BRA

IISEO

108F
1092
1093
1096
1097

F6

108F

*

00172

00187A
00188A
00189A
00190A
00191A
00192A
00193A
00194A
00195A

10AC
10AF
1082
1085
1086
1088
10BA
10BC
lOBE

B7
BD
BD
4C
34

84
81
35
26

00197A 10CO 84
00198A 10C2 88
00199A 10C4 20
Oft201
00202A
00203A
00204A
00205A
00206A
00207A

10C6
10C8
10CB
10CD
10CF
1001

34
8E
30
26
35
39

A

A
10AC

EO

A

A

E6

10AC

10C6
10

A WAIT
A
A WAIT1
A WAIT2
10CB
A

FfFF
1F
FC
10

LOOP1

ROLL-UP OPERATION EXAMPLE

A

08

BUSY

STB

EQU
PSHS
LOX
LEAX

BNE
PULS
RTS

STORE VALUE TO BE LOADED INTO ROR

TEMPO

A

flS1F

YOR = ROR(4:0> = 31 ?

1131
A

IF YOR=31, SET YOR=8

fl8
LOOP3

*X
#SFFFF

-1,x
WAlT2
X

33/38

293

APPLICATION NOTE

PAGE

005

.SA:O

EF80

**

00209
00210
00211
00213
00214A 10D2 7D
00215A 10D5 2B
00216A 10D7 39

BUSY : TEST BUSY IN STATUS REGISTER RO(7)

*
1002
A BUSY
F420
A
FB
1002

00218
00219
00220
00221
00222
00223
00224

**
*
*

EQU
TST
BMI
RTS

MPFlLL

*

*

*

RO
BUSY

*
10D8

A MPFlLL EQU

*

00228A 10D8 BD
00229A 10DB B7
00230A 10DE BF

10D2
F421
F422

A
A
A

JSR
STII
STX

BUSY
R1
R2

00232A 10E1 4F
00233A 10E2 B7
00234A 10E5 B7

F426
F427

II
A

CLRA
STA
STA

R6
R7

LDA
STA

0023611 10E8 86
0023711 10EII B7

05

A

F428

A

00239A 10ED 8E
0024011 10FO 30
00241A 10F2 26

0700
A
LOX
A FlLL30 lEAX
1F
FC
10FO
BNE

00243A 10F4 86
00244A 10F6 B7

91
F428

A
II

LDII
STII

0024611 10F9 39

RTS

00248
TOTAL ERRORS OOOOQ--{)OOOO
TOTAL WARN INGS OOOOQ--{)OOOO

END

294

=1

FILL THE 3-BLOCK PAGE MEMORY STARTING FROM BLOCK 0
WITH THE SAME LONG CHARACTER CODE
ENTRY: ·THE 1RST BlOCK IS FILLED WITH ACC. A CONTENTS
THE 2ND BLOCK WITH X REG. (MSB) CONTENTS
THE 3RD BLOCK WITH X REG. (LSB) CONTENTS.

00226

34/38

LOOP IF BIT 7

(lS05

TEST BUSY STATUS
STORE CHAR CODE INTO R1,R2,R3

INIT MAIN POINTER TO THE BEGINNING
OF THE SERVICE ROW : R6
R7
O.

= =

LOAD AND EXECUTE "ClF" COM MAN D

ROt8
(12000
-1,X
FllL30
(1$91

ROt8

WAIT ABOUT 15 MILLISECONDS

EXECUTE A "NOP" COMMAND
TO ABORT "CLF"

COMMAND TABLE
Type

~

R~

",(It

@.

~i!

!O
~I
~O
~Z

Status

Arguments

AI LX m LX, R 17

R1 R2 R3 R4 R5 R6 R7

Parameter

Code

Memo

7

6

5

4

3

Irdirect

INO

I

0

0

0

2
R/W-

40 Characters - 24 Bits

KRF

0

0

0

0

A/W 0

1

0

r

-

0

0

0

0

D

0

I

X

X

0

0

C

Execution Time (1)
Write

R.. d

40 Characters - 16 Bits

KRG

0

0

0

0

R/WO

1

1

X

X

0

0

A'

80 Characters - 8 Bits

KRC

0

1

0

0

R/W 0

0

1

X

X

0

0

C

80 Characters - 12 Bits

KRL

0

1

0

1

R/W 0

0

1

X

X

0

0

C

40 Characters Variable

KRV

0

0

1

0

R/W 0

0

1

X

X

X

X

C

- B A B' W - - - - A - B A - XF

MP

(2) 3 + 3 + j

3.5+S*j

Expansion

EXP

0

1

1

0

0

0

0

0

X

0

X

0

C

B

A PW XF

MP

(3) < 247

Compression

CMP

0

1

1

1

0

0

0

0

X

0

X

0

C

B

A PW XF

MP

(3) < 402

Expanded Characters

KRE

0

0

0

1

R/W 0

0

I

X

X

0

0

C

B

A PW

-

-

Byte

OCT

0

0

1

1

R/W P

0

I

X

X

X

0

D

Move Buffer

MVB

1

1

0

1

S

!

a

a

0

0

0

0

W

-

-

Move Double Buffer

MVD

1

1

1

0

s

i

a

a

0

0

0

0

W

Move Triple Buffer

MVT

1

1

1

1

S

t

11:

a

0

0

0

0

W

Clear Page (4) - 24 Bits

CLF

0

0

0

0

0

1

0

1

X

0

0

Clear Page (4) - 16 Bits

CLG

0

0

0

0

0

1

1

1

VerticeJ Sync Mask Set

VSM

1

0

0

1

1

0

0

1

Vertical Sync Mask Reset

VRM

1

0

0

1

0

1

0

1

IrcrementY

INY

1

0

1

1

0

0

0

0

No Operation

NOP

1

0

0

1

0

0

0

1

B••

Pointer Select
, : Auxiliary Pointer
o : Main POinter.
Source Destination

01 : Source. MP ; Destination. AP

a.a

1 0 : Scuree • AP ; Destination. mP
Stop Condition
0' : Slap at End of Buffer
, 0 : No Stop
Indirect Register Number

X

X

XF
I

D

Data

MP
AP

Main Pointer
Auxiliary Pointer,

PW(~.

X

YW)

-

- - B

A

-

0
0
- 0
0 - - - - - - - - 0
0
0 - 0
- - - - - - - - X

Not Afflocted
Used as Working Register
Workln, BuNer
Sat or R86et
X File
Pointer Incremantation

W

C

-

0

0

A'

(I)
(2)
(3)
(4)

B'

W

MP

2

3.5

MP

4

7.5

MP

5.5

7.5

MP

9

9.5

MP

12.5

11.5

MP

4

7.5

AP

MP

4

4.5

AP

MP

(2) 2 + 4.n

-

AP

MP

(2) 2 + B.n

AP

MP

(2) 2 + 12.n

MP

< 4700 (1 K code)

-

- MP
- - - - - y - - -

< 5800 (1 K code)

-

1

-

1

-

TBD
1

Unit: 12 clock periods (- 1 .,.5) without possible suspension.
n: total number of words s 40 ; J _ , lor long codes. j _ 0
for short codas.
Worst case (20 long code. + 20 .hon cod•• ).
These commands repeat KRF or KRG with V incr.mentatlon
when X overflows. When the lasl position ia reached In a
row. Y is incremented and tha process starts again on the
next row. These commands SlOp only with abOrt.

-

»
"tJ

...
"tJ

~

-I

(5
Z
Z

I}l
c.n

'"

~
ClO

o-I

m

APPLICATION NOTE

POINTERS
y' '" (0,1 ; 8 to 311

y =10,1 ;810311

I

dl

I d'l I dO

I, I

3

R6

I 2 I' 10

MAIN

X "'0 to 39

I

bO

I bl

15

I'

1 3 12

AUXILIARY
X' ""Ol039

POINTER

I

R7

I' 10

b'OI b'l

I

5

I ' 13 I

2

POINTER

I' 1 0

R5

INDIRECT REGISTERS
7

I

6

z31 z,

5

I 221

~

ROR Ir
~

•

~

I

71

Origin row address
YOR ,,-(8 t0311

'--_ _ _ _ _ _ _ _~,..,..

Block origin levenl

Ir-------....~ I IV ~ '/01
•5

Service row select

TGS (r

0

11

__
1 1"'' ' 'J I L~L.
~

Interlaced

Horizontal resVnc enable

CHAR CODe

PAT7

TGS7

TGSs

40 CHAR LONG

0

0

0

40 CHAR VAA

0

40 CHAR SHORT

,

a
a

0

so CHAR LONG

0

1

1

80 CHAR SHORT

a

1

0

INSERT MODE

,

PATS

PAT4

INLAY

0

0

BOXING

0

CHARACTER MARK

,

1

ACTIVE AREA MARK

CU RSOR DISPLAY MODE
FIXED COMPLEMENTED

FIXED UNDERLINED

MAT,

0

0

0

FLASH UNDERLINED

Sync oul pins configuration
1 : Composite sync i'
phase comparator
o V sync + H sync

l

1

I

...

lTL~

0

MAT5

,
,

FLASH COMPLEMENTED

,
,

Vertl!:al resync enable

PAT Ir

~

31

Service row enable

Upper bulk enable
Lower bulk enable

Conceal enable
F lash enable

MAT Ir = 21

.1[_1-~

Margin color
Margin insert
Cursor displav enable
Double height

0

,

NOTA: PROGRAMMING BIT VALUE

1 = True

1

0= False

DOR in 80 chilrlrow

DOR in 40 char/row

o

4

6
'1

-...DOR Q

~

DOR G',

DOA G'o

I

B,

I G, 1Rl

!

Cl:

'0

I

BO

I Go I AO

I

Co
E88-AN44T-25

36/38

296

APPLICATION NOTE
40 Char/Row Fixed Long Codes

6

BICHROME CODE
5
4
3
2

o

I-I
I

OUAORICHROME CODE
6
5
4
3

I

ILlmlHlil

r

BBYTE

11~::-

-------1 ~:
I I I
;

I
N

Bl

Gl I Rl

F

c:::::-..

II

Doublewidth

1 ~'-'
II~
~

Low R.olution

Subset index
(low resolutIon onlv)

Set number

TVpe end set

4 COLOR PALETTE

A BYTE
Background color

0

I-I

caYTE

«

!

!

!

Co

" - - _ : : Flaoh (Blinkl
Foreground color C1

'--_ _ _ _ _ _ _ _ _ _ Negative (Reverse video)

E88-AN44T-26

Type and Set
Code: B (4: 7)

7

Set
Name

6

5

4

C (0:6)

0

1
1

0
1

128 Standard Mosarcs
32 Strokes

G10
G 11

0

0

128 Alphanumerics

GO

1

0
1

0

1

U
N
D
E
R
L
I
N
E

0

1

Number of Character
Per Set

0

1
1

1
0

1

X

X

Accentued Lower Case Alpha

G20
G21

100 Alpha UDS

G'O

100 Semi-graphic UDS
100 Semi-graphic UDS

G'10
G'11

8 Sets of 100

QO
to
Q7

Quadrichrome Character

Set
Type

Cell
Location

SEMI-GR.

ALPHA

B
I
C
H
R
0
M
E

SEMI-GR.

ON-CHIP
ROM

EXTERNAL
MEMORY

QUAD RICH ROME

Nota: Programming bit value
1 = True
0= False.

37/38

297

APPLICATION NOTE
80 Char/Row Character Code
6

5

4

3

2

o

3

o

2

6

5

4

3

o

2

3

o

2

--------- ---

I\XIXIX,XIX,XIXIIX,XIXIDI

-

C
-----~~-------

C

A

ALPHANUMERIC CHAR CODE
N=
F=
U
D=

A

MOSAIC CHAR CODE

Negative

I

Flash

= Underline

o

Color set

I

2
3
4
5
6
7

128 ALPHANUMERICS
In GO .et.

8
9

.. .... ..
3 pelS

1

3peb

CO

CI

C2

C3

C4

C5

C6

AI

A2

AJ

I
DEDICATED
MOSAIC
SET

E88-AN44T-27

COLOR SELECTION
D

N

0
0

0

1
1

0

(Co,

1
1

BACKGND FOREGND
COLOR
COLOR
CM
Co
Co
CM
CM
CI
C,
CM

i
iO
iO
i1
i1

c"

iO, il) : defined in DOR
CM : margin color defined in MAT

38/38

Gi'l SGS·ntOMSON
• Jj

298

IliIUI:OO~I!.IiC'ITIiiI@OOUC$

NOTES

AUSTRALIA

INDIA

SINGAPORE

NSW 2027 EDGECLIFF
Suite 211, Edgecliff centre
203-233, New South Head Road
Tel. (61-2) 327.39.22
Telex: 071 126911 TCAUS
Telefax: (61-2) 327.61.76

NEW DELHI 110048
Liason Office
S114, Greater Kailash Part 2
Tel. (91) 6414537
Telex: 31-62000 SGSS IN

SINGAPORE 2056
28 Ang Mo Kio - Industrial Park 2
Tel. (65) 4821411
Telex: RS 55201 ESGIES
Telefax: (65) 4820240

ITALY

SPAIN

20090 ASSAGO (MI)
V.le Milanofiori - Strada 4 - Palazzo A/4/A
Tel. (39-2) 8244131 (10 !inee)
Telex: 330131 - 330141 SGSAGR
Telefax: (39-2) 8250449

BARCELONA
Calle Platon, 64°/5'
Tel. (34-3) 2022017-2020316
Telefax: (34-3) 2021461

BRAZIL
05413 SAO PAULO
R. Henrique Schaumann 286-CJ33
Tel. (55-11) 883-5455
Telex: (39-11) 37988 "UMBR BR"

CANADA
BRAMPTON, ONTARIO
341 Main St. North
Tel. (416) 455-0505
Telefax: 416-455-2606

CHINA
BEIJING
Beijing No. 5 Semiconductor
Device Factory
14 Wu Lu Tong Road
Da Shang Mau Wai
Tel. (861) 2024378
Telex 222722 STM CH

DENMARK
2730 HERLEV
Herlev Torv, 4
Tel. (45-2) 94.85.33
Telex: 35411
Telefax: (45-2) 948694

FRANCE
94253 GENTILL Y Cedex
7 - avenue Gallieni - BP. 93
Tel.: (33-1) 47.40.75.75
Telex: 632570 STMHQ
Telefax: (33-1) 47.40.79.10
67000 STRASBOURG
20, Place des Hailes
Tel. (33) 88.25.49.90
Telex: 870001 F
Telefax: (33) 88.22.29.32

HONG KONG
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22nd Floor - Hopewell centre
183 Queen's Road East
Tel. (852-5) 8615788
Telex: 60955 ESGIES HX
Telefax: (852-5) 8656589

40033 CASALECCHIO 01 RENO (BO)
Via R. Fucini, 12
Tel. (39-51) 591914
Telex: 226363
Telefax: (39-51) 591305
00161 ROMA
Via A. Torlonia, 15
Tel. (39-6) 8443341/2/3/4/5
Telex: 620653 SGSATE I
Telefax: (39-6) 8444474

28027 MADRID
Calle Albacete, 5
Tel. (34-1) 4051615
Telex: 46033 TCCEE
Telefax: (34-1) 4031134

SWEDEN
S-16421 KISTA
Borgarfjordsgatan, 13 - Box 1094
Tel. (46-8) 7939220
Telex: 12078 THSWS
Telefax: (46-8) 7504950

JAPAN

SWITZERLAND

TOKYO 141
Shinagawa-Ku, Nishi Gotanda
8-11-7, Collins Bldg 8
Tel. (81-3) 491-8611
Telefax: (81-3) 491-8735

1218 GRAND·SACONNEX (GENEVE)
Chemin FranQois-Lehmann, 18/A
Tel. (41-22) 7986462
Telex: 415493 STM CH
Telefax: (41-22) 7984869

KOREA

TAIWAN

SEOUL 121
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Tel. (82-2) 552-0399
Telex: SGSKOR K29998
Telefax: (82-2) 552-1051

KAOHSIUNG
7FL-2 No
5 Chung Chen3rd Road
Tel. (886-7) 2011702
Telefax: (886-7) 2011703

NETHERLANDS
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Tel.: (31-40) 550015
Telex: 51186
Telefax: (31-40) 528835

TAIPEI
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285 Chung Hsiao E. Road - SEC, 4
Tel. (886-2) 7728203
Telex: 10310 ESGIE TW
Telefax: (886-2) 7413837

UNITED KINGDOM
MARLOW, BUCKS
Planar House, Parkway
Globe Park
Tel.: (44-628) 890800
Telex: 847458
Telefax: (44-628) 890391

U.S.A.
NORTH & SOUTH AMERICAN
MARKETING HEADQUARTERS
1000 East Bell Road
Phoenix, AZ 85022
(1)-(602) 867-6100
SALES & REPS COVERAGE BY STATE

AL
Huntsville - (205) 533-5995
Huntsville (Rep) - (205) 881-9270

AZ
Phoenix - (602) 867-6340
CA
Fountain Valley (Rep) - (714) 545-3255
Irvine - (714) 250-0455
Los Angeles (Rep) - (213) 879-0770
San Diego (Rep) - (619) 693-1111
San Jose - (408) 452-8585
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CO
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NC
Charlotte (Rep) - (704) 563-5554
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FOR RF AND MICROWAVE
POWER TRANSISTORS CONTACT
THE FOLLOWING REGIONAL
OFFICES IN THE U.S.A.

NJ

CA
Hawthorne - (213) 675-0742

Voorhees - (609) 772-6222

NY
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OH
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PA
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Austin - (512) 339-4191
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UT
Salt Lake City (Rep) - (801) 269-0419

WA
Bellevue (Rep) - (206) 451-3500
Seattle, (206) 524-6421

CANADA
Burnaby (Rep) - (604) 421-9111
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Quebec (Rep) - (514) 337-5022
Winnipeg (Rep) - (204) 783-4387
COLUMBIA
Bogota (Rep) - (011) 57-1-257-8824
MEXICO
Mexico City (Rep) - (905) 577-1883

MI
Southfield - (313) 358-4250
Southfield (Rep) - (313) 358-4151

PUERTO RICO
Rio Piedras (Rep) - (809) 790-4090

MN
Bloomington (Rep) - (612) 884-6515

URUGUARY
Montevideo (Rep) - (011) 598-2-594-888

MO
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Kansas City (Rep) - (816) 436-6445

NJ
Totowa - (201) 890-0884
PA
Montgomeryville - (215) 362-8500
TX
Carrollton - (214) 466-8844

WEST GERMANY
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- Tel. (49-69) 6708191
Telex: 176997 689
Telefax: (49-69) 674377
Teletex: 6997689 =csfbef
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Tel.: (49-89) 460060
Telex: 528211
Telefax: (49-89) 4605454
Teletex: 897107 =STDISTR
3000 HANNOVER 1
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Tel. (49-511) 634191
Telex 175118418
Teletex: 5118418 csfbeh
Telefax: (49-511) 633552
8500 NORNBERG 20
Erlenstegenstrasse, 72
Tel.: (49-911) 597032
Telex: 626243
Telefax: (49-911) 5980701
5200 SIEGBURG
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Tel. (49-2241) 660 84-86
Telex: 889510
Telefax: (49-2241) 67584
7000 STUTTGART 1
Oberer Kirchhaldenweg 135
Tel. (49-711) 692041
Telex: 721718
Telefax: (49-711) 691408

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for
the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems
without express written approval of SGS-THOMSON Microelectronics.
© 1989 SGS-THOMSON Microelectronics -

Printed in Italy -

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