H 23_parallel Drum_Jul64 23 Parallel Drum Jul64
H-23_parallelDrum_Jul64 H-23_parallelDrum_Jul64
User Manual: H-23_parallelDrum_Jul64
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H-23
PARALLEL
DRUM
TYPE
-.'.-.. ~"~.~"
-_•...'.
DIGITAL EQUIPMENT CORPORATION
•
MAYNARD, MASSACHUSETTS
PARALLEL DRUM
TYPE 23
INSTRUCTION MANUAL
COpy NO. 0164
Th is manua I conta i ns proprietary i nformotion. It is prov ided to the customers of Digital Equipment Corporation to help them properly use and
maintain DEC equipment. Revealing the contents to any person or
organization for any other purpose is prohibited.
Copyright 1964 by Digital Equipment Corporation
II
PREFACE
This manual contains information on the principles of operation, and
procedures for installation, operation, programming, and maintenance of the Digita! Equipment Corporation Type 23 Parallel Drum.
The parallel drum is designed for use as a data storage device to augment the main memory of a PDP-l D computing system. Section 1
of this manual presents information of a general nature which is
applicable to the entire machine. Section 2 explains the principles
of operation of the parallel drum as a system and of each functional
element of the system. Sections 3 through 6 present information and
procedures which allow personnel to install, operate, program, and
maintain the equipment. Appendixes contain information on the
diagnostic program used to test the parallel drum, circuit data for
modules which are unique to drum systems, and engineering drawings.
iii
CONTENTS
Sect ion
2
Page
INTRODUCTION ........................................
1-1
Functional Description..................... . . . . . . . . . . . . . . .
1-1
Physical Description.......... . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2
Specifications ...........................................
1-4
Symbols and Terminology ..................................
1-4
Circuit Blocks .......................................
1-8
Si g na Is. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8
Subscripts .................................... , . . . . . .
1-10
Superscripts .........................................
1-10
Other Notations .....................................
1-1 0
Pertinent Documents ......................................
1-10
Pub Iications .........................................
1-10
Engineering Drawings .................................
1-11
Power Supply and Control .........................
System Modules ..................................
logic and Wiring ................................
1-11
1-11
1-12
PRINCIPLES OF OPERATION ............................. .
2-1
Recording and Playback Technique .........................
2-1
Block Diagram Discussion .................................
2-1
Index and Clock Readers ..............................
2-3
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3
Control .............................................
2-4
Drum Counter (DC) ...................................
2-4
Initial location Register (ll) ...........................
2-5
Comparator .........................................
2-5
Word Counter (WC) ..................................
2-5
Drum Core location Counter (DCl) .....................
2-6
Read Control and Read Field Buffer (RFB) ................
2-7
Write Contro I and Write Field Buffer (WFB) ..............
2-8
v
CONTENTS (continued)
Page
Section
Drum Field Select ....•.••..•..•••.•..........•.....•.
2-8
Pulsed Bus Transce iver .•••.••••••.•••....•............
2-9
In Buffer (IB) ..............•.•.••........•..•....•...
2-9
Out Buffer (OB)
2-10
Parity Formation .............•...•.•••.....••.....•..
2-11
Parity Check ..............•...•..••..•..•.........•.
2-12
Data Writers .•..•.. . . . . . . . • • • • • . • . • . • . . • . . . • . . . . . . • . .
2-12
Data Readers .•.•....•..•...•...•...•••..............•
2-13
Data Head Selection and Drum Memory .•..••............
2-13
Power Supply and Distribution ••••.•.•....•.............
2-15
Read-Write Cycle........................................
2-18
Read On Iy Cyc Ie ...•..........•..•••..•••.••••.•......•..
2-21
Write Only Cycle ..•...........•.•••••••..••.............
2-22
3
INTERFACE .•...•...................•.•....•........•...
3-1
4
INSTALLATION AND OPERATION
•..•••.•...............•
4-1
Site Requirements ..........••.•....•...•.................
4-1
Signa I and Power Connections ....•..•••....•.....•........•
4-1
Controls and Indicators ......•.......•.....•.•.•.•.•.......
4-2
Equipment Turn-On and Turn-Off
.•.......•................
4-6
PRO GRAMM IN G ....•.....................•.............
5-1
MAINTENANCE ...........................•.............
6-1
Drum Housing Locations and Wiring .....................
6-2
Preventive Maintenance ............................ . . . . . . .
6-5
Mechanical Checks .......•.........•.................
6-6
Power Supply Checks .................................
6-7
Timing Checks
6-7
6
vi
CONTENTS (continued)
Sect ion
Page
Drum Sense Amplifier Checks .........................
6-8
Index and Clock Head Spacing Checks. . . . . . . . . . . . . . . . . .
6-8
Data Head Spac ing Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-9
Marginal Checks ....................................
6-11
Corrective Maintenance ..................................
6-14
Preliminary Investigation.............................
6-14
System Troubleshooting .......
6-15
Diagnostic Program ...
Signal Tracing
Aggravation Tests
0.00
0
••
••
Circuit Troubleshooting.
0
0
00
••
0
0
•
0
•
00'
Validation Tests o.
Log Entry.
0
0
0
0
0
0
•
0
0
0
0
••
0
0
••
0
•
0
0
•
•
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.00
.0
0
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••••
000
0
0
•
0000000
••
0
•
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0
0
0
0
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•
0
000
••
0
0
•
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0
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00.
0
•
••
0.0
0
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•
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0
0
0
0
0000000
0
0
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0
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0
•
••
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0
0
0
•
•
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o.
00.00
••••••••••••
00
••
0.00.
0.0
••
•••••••
,
•
00000000.0.
0
0
0
0
00000000000.00
••
0
0
0
0
0
0
0
0
0
0
••••
0000.0
••
0
0
••
0
0
••
0
0
0
••
0
0
0
••
000.000.0000.
0
0
0
0
0
•
0
0
0
00000
000
0000
•
00
Repair
•
••
••
••••
0
0.0.00.000
00
0
0
•••
0
•
•
0.000.00
•
0
0
0
Module Circuits
In-L ine Dynam ic Tests
In-Line Marginal Tests .
Static Bench Tests
Dynamic Bench Tests
•
••••
0
0
0
000
0.
00
000
000000
••
00.
0
0
0
••
0
0
0
•
•
0
0
0
0
0
••
0
0
0
0
0
•
•
0
0
0
•••
••
0
0
0
0
•
6-15
6-16
6-17
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-23
6-24
Appendix
TYPE 23 PARALLEL DRUM DIAGNOSTIC PROGRAM
2
DRUM MODULES
0
•••
000
0
0
0
•
0
Type 1537 Drum Sense Amplifier
Controls
Input
o.
Output
Power
0
0
0
••
00.0.00
0
0
0000
••••
•
0
•
••
0
•
0
.00.00.0
0
•••
0
0
••
•••••
00
Type 4518 Drum NRZ Writer
0
•
0
00000.
000.
o.
0
0
0
0
0
•
0
0
000000.000
•
0
00
•••
'0'
••••••••
••
0
0
0
••
••••••••
.0.
0
0
•
0
•
0
00.
••••
••
0
0
•
•••
00.00.0.000000000.
••••••
•••••
0
000.0.
0
0
0
••
0
•
0
••
0
0
••••
o
0000.0
•
•
•
•
•
•
•
0
•
•
•
•
•
•
0000.0.0.00..
0
00.00
00.000..
0.0.
•••••••
••
•••
••
0
•
0
•
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0
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0
••••
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•••
vii
0
•
0
0
•••
0
•
0
•
0
•
0
•••
0
•••
00.
Input ..........................................
Output
000
•
•
to
•
•
•
•••••
0
•
•
A 1-1
A2-1
A2-1
A2-1
A2-1
A2-2
A2-2
A2-2
A2-3
A2-3
CO NTE NTS:( conti n u e d)
Page
Appendix
3
Power ............................................ .
A2-3
Type 4519 Drum Field Select.............................
A2-3
Input .............................................
A2-4
Output ............•...........•....•.... . . • . . . . . . .
A2-4
Power ..............................................
A2-5
A3-1
ENGINEERING DRAWINGS
TABLES
Page
Table
3-1
Inputs to Drum from PDP-1D ...................•..........
3-2
3-2
Outputs from Drum to PDP-1D ........................... .
3-4
3-3
Inputs to Drum from Memory Contro I ..............••.......
3-5
3-4
Outputs from Drum to Memory Control .................... .
3-6
4-1
Controls and Indicators ...•.................•............
4-2
5-1
I nstruc t ions ........................................... .
5-1
6-1
Maintenance Equipment ................................ .
6-1
A1-1
Diagnostic Program Switch Usage ........................ .
A1-1
Al-2
Error Printouts ......................................... .
Al-1
ILLUSTRATIONS
Figure
Page
1-1
Typical Parallel Drum System Type 23 .................... .
xii
1-2
Component Locat ions ................................... .
1-3
1-3
Logic Symbols ........................................•.
1-6
2-1
Typical Recording and Playback Timing ...•................
2-2
2-2
Data Head Selection ................................... .
2-16
2-3
Drum Power C ircu it .................................... .
2-17
4-1
Indicator Panels ....................................... .
4-2
viii
ILLUSTRATIONS (continued)
Page
Figure
6-1
Pad Location •...•.......................................
6-2
6-2
Head Wiring ..•.........................................
6-3
6-3
Diode Board Wir i ng ...•..................................
6-3
6-4
Read/Write Head Components .........•...................
6-4
A2-1
Type 1537 Logic Diagram
A2-1
A2-2
Type 4518 Logic Diagram
A2-2
A2-3
Type 4519 Logic Diagram
A2-4
ENGINEERING
DRAWINGS
Page
Drawing
RS-728
Power Supply ...................•.................
A3-1
RS-813
Power Control ................................... .
A3-1
PW-D-23-0-8
AC-DC Wiring ..........•........................
A3-3
RS-1000
Clamped Load Resistors ..........••................
A3-5
RS-1l30
Three-Bit Parity Circu it ........................... .
A3-5
RS-1304
De lay ..•...•.........•........•....•............
A3-6
RS-1310
Delay Line ••.................•...................
A3-6
RS-1410
Pulse Generator .•.............•.•.................
A3-7
RS-1537
Drum Sense Amplifier ........•.....................
A3-7
RS-1607
Pulse Amplifier ......•.••.....•.•..•.•............
A3-8
RS-1665
Pulsed Bus Transceiver ....•........................
A3-9
RS-1684
Bus Driver ...•................••.•................
A3-11
RS-4127
Capac itor-Diode-Inverter .....•..........•.........
A3-11
RS-4141
Diode Un it ........•...••.....•...................
A3-12
RS-4151
Binary-to-Octal Decoder .•........................
A3-12
RS-4217
Four-Bit Counter .......•..........................
A3-13
RS-4218
Quadruple FI ip-Flop ............................. .
A3-13
RS-4301
Delay
A3-14
RS-4401
Clock
A3-14
IX
ENGINEERING
DRAWINGS (continued)
Page
Drawing
RS-4518
Drum NRZ Writer ................................ .
A3-15
RS-4519
Drum Field Select ................................ .
A3-15
RS-4604
Pulse Amplifier .................................. .
A3-16
RS-6102
Inverter
A3-16
RS-6104
Inverter
A3-17
RS-6113
Diode Unit ...................................... .
A3-17
UML-D-23-0-7
Utilization Module List (Sheet 1) ................... .
A3-19
UML-D-23-0-7
Util ization Module List (Sheet 2) ................... .
A3-21
BD-D-23-0-17
Interface and Block Diagram ....................... .
A3-23
TFD-D-23-0-1
Timing and Flow Diagram .......................... .
A3-25
BS-D-23-0-2
Control, Error Detection, Time Chain ............... .
A3-27
BS-D-23-0-3
In Out Buffers and Pu Ised Bus Transceiver ............ .
A3-29
BS-D-23-0-4
Sense Amplifiers, Write Amplifiers, and Parity ....... .
A3-31
8S-D-23-0-5
Read/Write Field Buffers and Field Select ............ .
A3-33
BS-D-23-0-6
Core Location, Drum Counter, Initial Location
and Word Counter ................................ .
A3-35
CL-A-23-0-13
Reader Output from Drum Housing (2CJ6) ............ .
A3-37
CL-A-23-0-14
Field Select Input to Drum Housing (2CJ4) ........... .
A3-38
CL-A-23-0-15
Writer Input to Drum Housing (2CJ3) ................ .
A3-39
CL-A-23-0-16
PDP-l D Interface With Drum (2CJ1) ................ .
A3-40
x
Figure 1-1
Typical Para llel Drum System Type 23
x ii
SECTION 1
INTRODUCTION
The Digital Equipment Corporation (DEC) Type 23 Parallel Drum serves as auxiliary data storage for the core memory of a Programmed Data Processor - 1 D and faci Iitates time shared use
of the computer.
Information in the computer can be stored (written) in the parallel drum and
retrieved {readL or can be simultaneously read and written in a swap or data exchange.
drum contains 32 fields; each field is capable of storing 4096 words.
information bits and an odd parity bit.
The
Each word contains 18
The parity bit is generated within the drum during
write operations and is checked during read operations to provide a means of check ing the
18-bit information transfer between the drum and the computer. All transfers are completely
automatic as controlled by the computer program.
Transfers of from 1 to 4096 words can be
executed at a rate of 8.5 microseconds per word, exclusive of set-up and access time.
Trans-
fer or exchange of 4096 words is accompl ished in approximately 35 mi II iseconds.
FUNCTIONAL DESCRIPTION
The basic functions of the Type 23 Para Ilel Drum are data storage and retrieva I, computer
core memory address control, drum track and field selection, data request and transfer control,
error checking, and power supply and distribution.
Functional operation of the machine is
initiated by receipt of lOT pulses from the computer.
Three computer instructions produce
all of the lOT pulses required to enact a transfer between the computer memory control and
the para lie I drum, regard Iess of the word Iength of the transfer.
A power supply and distribution network within the parallel drum produces and controls the
operating voltages required by all circuits of the machine. One source of external ac power
is required to energize the machine; control of this source within the machine can be exercised
loca Ily or remotely at the computer.
In response to lOT pulses from the computer the parallel drum receives the drum address from
the computer, receives the number of words to be transferred and the read/write/exchange
status of the transfer, and receives the core memory address of the transfer from the computer.
1-1
The transfer is then enacted in either the program interrupt or sequence break computer modes.
Eighteen iJ;ts are simultaneously read from or written on the surface of the continually rotating
drum and are transferred to or from the computer memory control element by means of a bidirectional pulse bus transceiver.
During a write operation, a parity bit is generated within
the drum for each word received from the computer so that 19- bit words are written on the drum
surface.
In reading data from the drum, the parity of the word is checked to assure proper
transmission.
Error circuits in the machine check for parity error during read cycles and check
for data transm iss ion timing during both read and write cycles.
If bits are picked up or dropped
out, if data received from the computer is late during a write cycle, or if data is late in being
stored in the computer core memory during a read cycle, an error flag is set and a signal is
sent to the computer and the transfer is ha Ited.
The computer program can interrogate the
drum to determ ine the error status and the type of error detected when the error flag is set.
Control circuits within the parallel drum initiate the computer break status for the transfer,
indicate the completion of a transfer by means of a flag, and signal the detection of an error,
in addition to performing the normal internal control operations.
PHYSICAL DESCRIPTION
The parallel drum is constructed of two standard DEC computer cabinets bolted together to form
a cabinet 60-1/8 inches high, 47 inches wide, and 27-1/16 inches deep. All indicators and
the power control switch are located on panels at the front of the machine. Additional controls,
used to inhibit writing in each of the drum fields independently and to force an incorrect parity
bit as a check of the error circuits, are located on a switch panel inside the front doors of the
right-hand cabinet.
Eight casters allow mobility of the 900-pound machine.
Each cabinet is constructed of a welded steel frame covered with sheet steel. Double rear
doors are held closed by magnetic latches. A full-width plenum door provides mounting for
the Type 813 Power Control and two Type 728 Power Supplies inside the double rear doors.
The plenum doors are latched by a spring-loaded pin at the top.
Plug panels, which accept
the signal cables from the computer, and module mounting panels are located in the front of
the mach ine with the wiring side outward. A fan mounted in the bottom of each cabinet draws
cooling air through a dust filter in the bottom, passes it over the electronic components, and
exhausts it through louvered panels and openings in the cabinet.
1-2
A coordinate system is used to locate cabinets, module mounting panels, modules and signal
cable connectors, and terminals within the machine. As viewed from the front, cabinet 1 is
on the left and cabinet 2 is on the right.
Each 5-1/4 inch position on the front of the cabinet
is assigned a capital letter, beginning with A at the top. Modules are numbered from 1 through
25 from left to right in a mounting panel, as ·viewed from the wiring side. Connectors on a
plug panel are numbered from 1 through 6, from left to right as viewed from the front of the
machine.
Blank module and connector locations are numbered.
nector are designated
by capita I letters from top to bottom.
omitted from module and terminal designations.
Terminals on a module con-
The letters G, I, 0, and Q are
Therefore, 1C06J is in cabinet one (1), the
third component location from the top (C), the sixth module from the left (06), and the ninth
terminal from the top of the module
identified by location.
(J). Components mounted on the plenum door are not
Figure 1-2 indicates the location of components within the parallel
drum.
BAY 1
BAY 2
INDICATOR PANEL
IA
AUXILIARY INDICATOR PANEL
2A
LOGIC
IB
LOGIC
2B
LOGIC
lC
PLUG PANEL
2C
LOGIC
J0
FIELD LOCKOUT SWITCH PANEL
20
LOGIC
IE
BLANK
LOGIC
IF
LOGIC
IH
BLANK
LOGIC
!J
BLANK
BLANK
I
I
BLANK
BLANK
I
I
I
u
U
U
FRONT VIEW
Figure 1-2
Component Locations
1-3
U
SPECIFICATIONS
Dimensions
47 inches wide, 27-1/16 inches deep,
69-1/8 inches high
Service Clearances
8-3/4 inches in front
14-7/8 inches in back
Weight
1000 pounds
Power Required
115 volts, 60 cycles, single phase, 10-ampere
starti ng current, 9-amperes runn i ng current
Power Dissipation
750 watts
Power Contro I Po i nt
loca I or remote (computer)
Initia I Starting Delay
20 minutes
Heat Dissipation
2558 BTU/Hours
Signal Cables
Three 50-wire shielded and one 18-wire
coaxial
Temperature
32 to 105 degrees F operating range
Drum Motor
115 volts, single phase, 4-pole induction
capacitor start and run
Magnetic Head Interference
Maximum interchannel read cross talk at least
25 db below nominal signal level. Maximum
noise in any channel at least 25 db below
nominal signal level.
Wri te Current
1.75 amperes at - 14 volts for 19 heads
Read Current
20 mill iamperes at + 4 vo Its for 19 heads
Pulse Repetition Rate
8.5 microseconds
Drum Revolution Time
35 mill iseconds
SYMBOLS AND TERMINOLOGY
Engineering drawing numbers for this equipment contain five pieces of information, separated
by hyphens. Read from left to right these bits of information are a 2-letter code specifying
the type of drawing, a 1-letter code specifying the size of the drawing, the type number of
the equipment: the manufacturing series of the equipment, and a 2-digit number specifying
the number of a drawing within a particular series.
a.
BS, block schematic or logic diagram
b.
el, cable list
1-4
The drawing type codes are:
c.
PW, power wiring
d.
RS, repiacement schematic
e.
TFD, timing and flow diagram
f.
UML, util ization modu Ie list
g.
WD, wiring diagram
Symbols used on engineering drawings to represent basic logic circu its are defined in Figure 1-3.
Symbol
Definition
---I>
Standard DEC Positive Pulse or positive-going transition
Standard DEC Negative Pulse or
negative-going transition
Standard DEC Ground Level signal
Standard DEC Negative Level (- 3
vdc signa I)
•
Load resistor clamped at - 3 vdc
COLLECTOR
BASE~ORD
Transistor inverter
EMITTER
SET-TO-
CLEAR-TO-
ONE
ZERO
Figure 1-3
Bistabl e mul tivibrator (fl ip- flop
constructed of two cross-coupled
inverters.
Logic Symbols
1-5
Definition
Symbol
OUTPUTS
t
GROUND IN
ZERO STATE
GROUND IN
ONE STATE
-3 VOLTS IN
ZERO STATE
-3 VOLTS IN
ONE STATE
~~--+-r.
DIRECT CLEAR - ..r~____~~.........,
INPUTS
FI ip-flop constructed of fixed connections within a systems modu Ie.
GATED CLEAR-TO-ZERO
COMPLEMENT - - - - '
GATEDSET-TO-ONE--------~
DIRECT SET - - - - - - - - - '
Pulse inverter
DIODE PULSE
CAPACITOR-f OUTPUT
PULSE
INPUT
Capacitor-diode gate (negative or
positive as indicated by signal Inputs) .
RESISTOR LEVEL
INPUT
Inverting diode gate used as an AND
circuit for ground-level signals.
Inverting diode gate used as an AND
circuit for negative-level signa Is.
Figure 1-3
Logic Symbols (continued)
1-6
Definition
Symbol
Inverting diode gate used as an OR
circuit for negative-level signa Is.
Inverting diode gate used as an OR
circuit for ground-level signa Is.
Diode OR and AND circuit followed
by inverter.
Inverting diode gate used to trigger
a pulse amplifier.
Figure 1-3
Logic Symbols (continued)
1-7
Abbreviations and conversions used in this manual, on the engineering drawings, or on panel
markings are defined in the following list.
Circuit Blocks
ACT
Active fl ip-flop
DBA SYNC
Drum break address fl ip-flop
DC
Drum counter
DCl
Drum core location
DRA SYNC
Drum read address fl ip-flop
ERROR SYNC
Error synchronization fl ip- flop
Il
Initio I location
PA
Pulse amplifier circuit
PE
Pari ty error fl ip- flop
PI
Pulse inverter circuit
RFB
Read field buffer
RQ
Request fl ip-flop
SA
Sense amplifier {reader}
TRA
Transfer status flip-flop
TRANS ERROR
Transfer error fl ip-flop
WC
Word counter
WFB
Write field buffer
Signa Is
ACT
ADRS ACK
Active fl ip-flop or level
Ad cress aCKnow Ieage pu Ise
DBA
Drum break address instruction or fl ip-flop
DC=ll
level indicating C{DC} = C(ll)
DC => 10 STROBE
Pulse which strobes C(DC) => C(lO)
DCl
Drum core location instruction or register
DCT CLEAR
Drum control clear pulse
DCT DISABLE
Drum control disable level
I
1-8
,
I
,
Signa Is (conti nued)
DIA
Drum initial address instruction
DRA
Drum request address instruction or fl ip-flop
DWC
Drum word counter instruction
IB
In buffer register or level
10
Input-output register or level
lOB ADRS ACK
Input-output buffered address acknowledge
pulse
MA
Memory address register or levels from
the DCl to this register
OB
Out buffer register or levels
PBT
Pu Ised bus transceiver
PWR ClR
Power clear pulse
MB
Memory buffer register or input-output levels
of the PBT
RD RS
Read restart pu Ise
RD REQ or RD RQ
Read request level
RFBH
Read field buffer high digit level
RFBl
Read field buffer low digit level
RQ
Request level
RQB
Request level buffered
SA
Sense ampl ifier circuit (reader) or pu Ises
SBS RETURN
Sequence break signal return pulse
TE or TR ER
Transfer error level
TP
Timing pulse
WC
Word counter register or level
WFBH
Write field buffer high digit level
WFBl
Write field buffer low digit level
WFD
Write field disable buffer
WFlO
Write field lockout switch or level
WR REQ or WR RQ
Write request leve I
WR WS
'vVri te restart pu Ise
1-9
Subscripts
o through 6
Individual bit numbers of a register,
counter I or fl ip-flops
Superscripts
Signal condition for flip-flop binary 1 status
o
Signal condition for flip-flop binary 0 status
Other Notations
V
Inclusive OR
-¥-
Exclusive OR
A
AND
C(A)
Contents of register A
A
=> B
C(A)O_5
A replaces B or B is set to A
=> C(B) 6- 11
The contents of bits 6 through 11 of
register B are set to correspond with
the contents of bits 0 through 5 of
register A.
PERTINENT DOCUMENTS
Publ ications
The following DEC documents serve as source materia I and complement the information in
this manua I:
a.
Digital Modules Catalog, A-705. This book presents information pertaining to
the function and specifications for the basic systems modules and accessories comprising
the Type 23 Parallel Drum.
b.
Silicon Modules Catalog C-6000.
Information on the function and specifications
for the 6000 series system modules is contained in this book.
c.
PDP-1 Handbook, F- 15.
Programming information for the Programmed Data Pro-
cessor - 1 is presented in this document.
1-10
d.
PD P - 1 Supplements, F - 15 (1 D - 45) and F - 15 (1 D - 48).
• I
. I
•
I..
• •
n
n~
"I..I
Crtbe rne speCial InstrUCTions aooeo TO Tne
,
rlJr-
I
I
I
wnen usea
These documents des•
I
•. •
a Typical
In
nf"\ n
rur-
1
i
f"\
u
configuration, such as that at Bolt Beranek ard Newman, Inc. (45) and at Stanford
University (48).
e.
PDP- 1 Maintenance Manual, F- 17.
Installation, operation, and maintenance
of the standard PDP- 1 and its central processor options are covered in this manual.
f.
Parallel Drum Diagnostic Program Tape, DEC - 1 - 137 - M. A perforated- paper
tape and program resume of a routine which tests the data reading, writing, and
sw(]pping operations of the drum system.
Eng i neer i ng Draw i ngs
Engineering drawings in the following list are reproduced in Appendix 3 of this manual as an
aid to understanding and maintaining the Type 23 Parallel Drum. A complete set of formal
engineering drawings is supplied separately with each system. Should any discrepancy exist
between the drawings in this manual and those supplied with the equipment,
assume the formal
drawings to be correct.
Power Supply and Control
Power Supply ..••
Power Con trol
0
0
o.
•
000
.0.
o.
0
••
00
••••••••••••••••••
AC-DC Wi ring ••••
0
•
0
0
••
•
0
0
••
0
o.
•••••
0
0
•••••
••
0
0
o •••
•••
0
00
00
o.
•••••••
••••••••••••••••••••••••••••••
0
0
0
•
o.
•••••
o.
••••
00
0
RS-728
RS -813
PW -D -23 -0-8
System Modules
RS-1000
Clamped Load Resistors
Three-Bit Parity Circuit.
0
.00.0
0
.0
0.0.0
Delay (monostable multivibrator) .•••.•
Delay Line.
000
•••
0.0.0000.00.000
Pulse Generator ••.•••
0
•••••••••
:~;"
D I~··U I I I .C,,""S"
J C I I C "A_
l l l t.....
JII I
I I C I.. f\... e,..,.Je"\
uu I ,
••
0.0
0
00
.0.000
•••••
•••••••••••
••
••••
0
0
•••
••
0
••
0
0.0000
0.
0
o.
0
0.0.00
•••
•••
000
00
00.0.
••
•••
••••
0.0.
00.000.
0
••••••
000.0.0
RS-1130
RS-1304
RS-1310
RS-1410
R' 1517
• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • ....,- •
1- 11
..."
System Modules (continued)
Pu Ise Ampl i fi e r ..
0
•••
0
••••••••
Pulsed Bus Transceiver .•..
0
••
0
••
00.0
0
•
••
0
•
0
•
0
••••••
0
•••
0
••
0
•
0
••••••
RS -1607
_
00.00.000000.00000.0000000000
RS-1665
Bus Driver .......•.................•.........•..........•...... RS -1684
Capac i tor-Diode-Inverter
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Diode Unit .....................................
Binary-to-Octal Decoder
Four-Bit Counter
000000
00
00000000000
0
00
000000000000000000000000000
Quadruple Flip-Flop
0
$
000
•••••
0
0
0
0 _
0
0
0
•
0
0
0
0
••••••••••••••
00000.00000
0.0.0
000.00000.000000.000000000.000
•••
•••
00
••
000
00
0
0
000.0.0.0.0
RS -4127
RS-4141
RS-4151
RS-4217
RS-4218
Del a y •.•••••••••••••••••.••••••.•••••• • • • • • • • • • • • . • • • • • • • • ••• RS -43 01
Clock ........................................................ RS-MOl
Drum NRZ Writer.. .. . .. . ..... ..... .. . .. . .. .. . .. . .. .. . .. . ...... RS-4518
Drum Field Select
0000
00000000
••
0
000
••
o •• o •••
00.
0
00.000000.000
00
RS-4519
Pulse Ampl ifier ...... . .. . .. .• . .. . .. . . . .. . .. .. . .. . .. .. . .. . . . .. .. RS-4604
Inverter. . . .. .. . . . . . . . . . .. . .. .. . .. . .. .. . .. . . . .. . . . . .. . . . .. . ... RS-6102
Inverter.. . . . .. . .. . . . . . . .. . . . .. . .. . .. .. . .. . .. .. . .. . .. .. . .. . ... RS-6104
Diode Unit.. . .. . . . . . . .. . . . .. . .. . . . .. . .. .. . .. . .. .. . .. . .. . . . . ... RS-6113
Util ization Module List.
0
0
00
0
0
0
0
•
0
o.
.0
0
00
0
0
••
0
•
00
.00
•
0
0
0
0
UML-D-23-0-7
Logic and Wiring
Interface and Block Diagram
Timing and Flow Diagram
0
0
0
•
0
00000.00
0
••
••
Control, Error Detection Ti me Cha in
0
•
0
•
0
0
00000.
0
0
•
0
In Out Buffers and Pulsed Bus Transceiver.
0
0
0
0
00
0
0
0
0
0
.0
0
0
••
••
Sense Amplifiers, Write Amplifiers, and Parity
Read/Write Field Buffers and Field Select
•
0
•
0
0
•
•••
0
0
•
00
•
00
0.'
0
0
0
0
0
•••
••
00
0
•
o.
0
BD -0 -23 -0-17
TFD-D-23-0-1
o.
000.
0
••
0
0
0
0
00
0000.000
00000.0.0000......
BS -D -23 -0-2
BS-D-23-0-3
BS-D-23-0-4
BS-D-23-0-5
Core Location, Drum Counter, In itia I Location and
Word Counter
000
••
00
Reader Output from Drum Housing (2CJ6) ...
Field Select Input to Drum Housing (2CJ4)
Writer Input to Drum Housing (2CJ3)
o. o.
PDP-1 D Interface With Drum (2CJ1)
o.
0
•
00.00000.
0
•
0
o.
0
0
••
0
0
0
0
••
••
0.000.0.00.00000
0
0
0
•••
•••
••
1-12
0
0
•••
00
000
•••
00
•
0
0
0
•
0
00_
•
0'0
BS-D-23-0-6
CL-A ... 23-0-13
CL-A-23-0-14
CL-A-23-0-15
CL-A-23-0-16
SECTION 2
PRINCIPLES OF OPERATION
RECORDING AND PLAYBACK TECHNIQUE
The Type 23 Parallel Drum utilizes return-to-bias recording techniques which lend themselves
to the simultaneous read and write, or exchange, operation required of the drum.
In each bit
cell the new information to be written in a field is available just before the information is to
be read from another field.
Because of noise considerations, the read strobe must precede the
write strobe. The effective advance of the read strobe over the write strobe, which previously
wrote the information to be read, is possible because of the fringing of flux ahead of the data
head gap.
Before a transfer begins the read and write head select circuits are enabled. At the
beginning of a transfer bias current is applied to the write-selected heads so that all transients
occur and damp out before the occurrence of the read strobe.
In a data exchange operation
the read strobe is followed by the write strobe, and write noise is induced in the sense amplifier.
This noise is commonly of greater amplitude than the read signal; however, this noise
damps out before the next read strobe occurs. The read and write current waveforms and the
timing of the read strobe and write strobe are indicated in Figure 2-1 .
BLOCK DIAGRAM DISCUSSION
Functional elements of the parallel drum are shown on engineering drawing BD-D-23-0-17.
This drawing indicates all signals which flow between the elements of the drum, and between
drum elements and the PDP-1 D and the Memory Control. The only signals which are not in-dicated are the phase signals out of the timing element which go to all logical blocks and the
operating voltages which also are supplied to all elements from the power supply and distribution
element.
Detailed information on each of the functional blocks is indicated in block schematic
engineering drawings BS-D-23-0-2 through 6, and complete information transfer flow in timing
operations is indicated in engineering drawing TFD-D-23-0- 1. The distribution and wiring of
the power circuits within the parallel drum are indicated in engineering drawing PW-D-23-0-S.
As reference is made to these drawings in the following text, only the final portion of the engineering drawing number will be used.
Reference will also be made by means of the coordinates
2-1
TIMING
WRITE
ENABLE
WRITE
STROBE
READ
STROBE
(PRECEDES WRITE
STROBE BY a.lpSEC)
LOAD
CLEAR
IN BUFFER
(EXAMPLE OF BIT
X IN FOUR
SUBSEQUENT
WORD LOCATIONS)
0
tv
1
tv
WRITE CURRENT
FOR ONE HEAD 0
(WRITE FIELD Y)
READ HEAD VOLTAGE
(READ FIELD Z)
(1,0,0,1, PREVIOUSLY
WRITTEN IN FOUR
SUBSEQUENT
LOCATIONS)
GROUND SLICE OUTPUT
-3-+----'
S A OUTPUT -+----""""\1
TIME
pSEC
0
"'--------If---------------If--------------i------_I . . -------t---
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2
3
4
5
6
7
80
2
3
4
5
6
7
80
Figure .2-1
I
2
I
3
I
4
I
5
Typical Recording and Playback Timing
I
6
I
7
I
80
I
2
I
3
I
4
I
5
I
6
I
7
I
88.5
on the drawing.
These coordinates are A through D from top to bottom and 1 through 8 from left
to right; so zone A 1 is in the upper left hand corner, and zone D8 is in the lower right hand
corner.
Note that register bits are numbered to correspond with the computer register bits to
which they transfer data.
Therefore, most register bits are numbered so that the least signifi-
cant bit is designated bit 17.
Index and Clock Readers
In addition to the normal data tracks recorded on the drum surface, two tracks provide timing
information used in the control of normal drum operations.
These two tracks are the index and
the clock tracks. The information on these tracks is prerecorded and is read from the index
track by the Type 1537 Drum Sense Amplifier module at location 286 and is read from the
clock track by the Type 1537 module at location 2B5. One index bit is recorded on the surface of the drum to indicate the starting address of all words written on the data tracks.
The
output signa I level from the index sense ampl ifier initiates operation of a Type 1304 Delay
modu Ie whose negative pu Ise output clears the drum counter and signifies the start of each
new drum cycle. The delay is provided to allow adjustment of the timing relationship of an
index pulse so that it occurs exactly in the center of the time between the first and last clock
pulse. The output of the clock sense amplifier initiates operation of a Type 1410 Pulse Generator module at location 2B4 to produce a standard DEC 70-nanosecond clock pulse which initiates operation of the timing element and controls the timing of all operations in the parallel
drum.
There are 4096 clock bits recorded around the surface of the drum; each clock pu Ise
signifies a data bit cell location.
Engineering drawing 4 contains this logic in the lower
left hand corner.
Timing
The timing element consists of a timing chain generator composed of delay lines, delays, and
pulse amplifiers which produce the read strobe, write strobe, phase 1, phase 2, phase 3, phase
4, and phase A pulses.
The timing chain is initiated by receipt of a clock pulse from the clock
reader element. Transistor gating circuits allow generation of the read strobe signal only when
the drum is in the read mode and in the active status. The phase 1 signal can be generated
only when the drum is in the write mode and in the active status. The phase 2 and phase 3
2-3
signals are enabled only when the drum is in the active status. The phase 4 and phase A pulses
cannot be disabled. In addition to these pulses the timing element produces the DCT disable
signal, which is a constant - 3 vdc level produced by clamped load resistors.
wherever constant enabling or disabling - 3 vdc levels are required.
This level is used
The phase 3 signal initiates
operation of the Type 4604 Pulse Ampl ifier in location 1 F4 whose output is the write restart
0NR RS) signal, which is supplied to the memory control and to the parity formation element.
Control
The control element contains nine flip-flops (TRA, RQ, ACT, ERROR SYNC, TRANS ERROR,
PE, DRA SYNC, DBA SYNC, and busy) which determine and control the status of the parallel
drum.
This element is shown on engineering drawing 2, above the timing element and the
parity check element. When power is initially applied to the parallel drum, the Type 4401
Clock at location 1 F2 is enabled by a ground level suppl ied to terminal B and produces repeated
power clear pulses. The power clear pulses clear the parity formation element and various
registers of parallel drum in addition to all of the flip-flops in the control element. After an
initial delay period of approximately 30 seconds, the normally closed contacts of time-delay
relay D2 of the Type 813 Power Control open to remove the ground potential from the integrating circuit at the input of the clock module to disable it.
The nine control flip-flops are also cleared by receipt of the DIA 7-4 command pulse, which
is received during the first instruction in the initializing sequence. All of the flip-flops except
the busy fl ip- flop are set to one or c Ieared to zero by the phase A pu Ise, as a function of the
condition of level signals suppl ied to capacitor-diode gates. The busy fl ip-flop is constructed
of two cross-coupl ed inverters wh i ch function as an unbuffered fl ip- flop.
Th is fl ip- flop is
cleared to zero by power clear pulses, the DIA 7-4 pulse, or a sequence break signal return
and is set to 1 by the Del 10-4 puise. The function of the other ft ip-flops can be determ ined
by the control signal or lOT pulse inputs required to set or clear them.
Drum Counter (DC)
The DC is a 12-bit counter which keeps track of the angular position of the continually rotating drum. This register is cleared by the index pulse provided by the index reader, and is incremented
2-4
by one by each phase A pu Ise.
Both the 1 and 0 outputs from each bi t of th is reg ister are
suppl ied to a comparCltor so that a data transfer is requested when the drum reaches the position, or drum address, set into the initial location register.
The contents of this register can
also be set (read) into the PDP-1 D 10 register to monitor the angular position of the drum.
The logic circuits for the DC are shown on zone B of engineering drawing 6.
Initial Location Register (lL)
The IL is a simple set-and-reset 12-bit register which is used to store the initial address or first
address at which the drum is to read or write.
During either a DIA or DBA instruction, the
register is cleared at computer 7 time and is set to the address contained in 10 bits 6 through
17 at computer 10 time.
Both the 1 and 0 outputs from this register are continuaiiy supplied to
a comparator for comparison with the contents of the DC. This register is shown on zone C of
engineering drawing 6.
Comparator
The comparator, shown on zone B8 and C8 of eng ineering drawing 6, continua lIy mon itors the
contents of the DC and the IL. The circuit provides a bit-by-bit exclusive OR comparison of
the contents of these two registers and supplies the negative DC = IL signal to the control circuit when the two registers contain the same drum address. This signal causes the control circuit to set the request flip-flop to the 1 status if the transfer flip-flop is also in the 1 status.
The output of this flip-flop is then supplied to memory control to request a transfer. When using
the DBA instruction, the DC = IL signal also initiates generation of the sequence break signal
return pulse which is supplied to the computer to initiate a transfer through the sequence break
mode, and clears the busy flip-flop.
Word Counter (WC)
The WC is a 12-bit binary counter which controls the number of words transferred during any
drum operation.
The WC logic is shown on zone A of engineering drawing 6.
During a DWC
instruction, the contents of the computer 10 register are set into the write control, the write
field buffer, and the word counter. At this time the 10 register information contained in bits
o through 5 determines
if writing is to occur in the following transfer and the write field to
2-5
be enabled.
The contents of bits 6 through 17 of the 10 register specify the number of words
to be transferred. The l's complement of the contents of bits 6 through 17 of the computer
10 register is set into the contents of the word counter at computer time 10 (the WC is cleared
at computer 7 time by the DWC instruction). During the ensuing DCl instruction, the contents
of the WC are incremented by one by the DCl 7 - 4 lOT pulse; therefore when the transfer is
initiated by the DCl instruction, the word counter holds the 2's complement of the number of
words to be transferred. As each word is transferred, the wri te strobe pu Ise increments the
contents of the WC. The write strobe pulse is used for this operation since both reading and
writing have been completed at the current drum address when this pulse occurs.
Therefore,
when the specified number of words have been transferred, the most significant bit of the WC
changes from the 1 state to the 0 state.
The
WC~
signal clears the request flip-flop in the
control element to signify to the computer that the transfer is complete.
Drum Core location Counter (DCl)
The DCl is a 16-bit register which specifies the computer core memory address to or from which
the next word is to be transferred.
The contents of the DCl are sampled by the memory control
and set into the contents of the core memory address register for each word of a transfer.
Bits
6 through 17 of the DCl function as a setable counter which is automatically incremented by
receipt of the lOB address acknowledge pulse from memory control.
Bits 2 through 5 of the
DCl are always transferred into the memory address register as they are set by computer 10
register bits during the DCl instruction program initialization.
Bits 2 and 3 specify one of
four 16, 384-word memory banks to be used for the transfer,and bits 4 and 5 specify one of
four 4096-word memory modules within the memory bank. Therefore, the parallel drum is
capable of operating with a computer containing 65,536 words of core memory with a maximum
transfer word length of 4096 words.
The Del is shown on zones C and D of engineering
drawing 6.
Before normal drum transfer operations, the DCl is cleared by the power clear pulses.
During
the third lOT instruction of the drum initialization program, the DCl instruction clears the
DCl at computer 7 time and sets the contents of the 10 register into the contents of the DCl
at computer 10 time.
Bits 6 through 17 of the DCl are incremented at the comp letion of each
word transfer by the lOB address acknowledge pulse. All outputs from the DCl to the memory
control are buffered by a non-inverting Type 1684 Bus Driver module.
2-6
Read Control and Read Field Buffer (RFB)
Read control is a single flip-flop which determines if reading from the drum is enabled or disabled during any data transfer.
The flip-flop is set to the 1 status (to enable reading) or to
the 0 status (to disable reading) by the contents of 10 register bit 0 during the first instruction
of the drum initialization program (DIA or DBA instruction).
The 0 output from the read flip-
flop is buffered by circuit HJ on the Type 6102 Inverter module at location 1 F22 to produce
the read buffered (B) signal.
This buffered signal, supplied to the timing element and to the
control element, is a - 3 vdc level when the flip-flop is in the 0 status and is a ground level
signal when the flip-flop is in the 1 status. When the read flip-flop is in the 1 status, transistor gating circuits in the timing element are enabled to produce the read strobe pulse, thereby
allowing read operations to take place. When the read flip-flop is in the 1 status, the read
buffer signal supplies one input to the UVW circuit of the Type 6113 Diode Unit module at
location 1 E15 whose output is buffered by the Type 1684 Bus Driver at location 1 F3 to provide
both the read request (RD RQ) and write request 0NR REQ) signa Is suppl ied to the memory
control.
The 5-bit RFB specifies one of the 32 read fields which is to be activated during the ensuing
transfer.
The contents of the RFB designate a drum read field address of the transfer and are '
specified as a 2-digit octal number.
Bits 1 and 2 of the RFB output are decoded to form the
most significant bit of the octal number or the read field buffer high (RFBH) portion of the
octal number which may run from 0 through 3.
Bits 3 through 5 of the RFB are decoded to form
the least significant bit or read field buffer lower (RFBL) portion of the octal drum address which
may run from 0 through 7.
Both the read control flip-flop and the RFB are cleared by the DCT clear pulse, which is produced by the control element when the drum receives a DIA 7-4 command pu Ise.
Both the
read control fl ip-flop and the RFB are set to correspond with the contents of computer 10
register bits 0 through 5 upon receipt of either a DIA 10-4 or DBA 10-4 command pulse from
the computer.
Note that the circuit contains inverters KL and UV on the module in location
1 F8 which provide the required inversion for operation of the negative capacitor-diode gates
at the input to the read control and RFB1 flip-flops.
The read control and RFB are shown on
the lower right hand portion of engineering drawing 5.
2-7
Write Control and Write Field Buffer (WFB)
The write control and WFB determ ine the write status of the drum and control the drum write
field address.
Both the write control and WFB flip-flops are cleared by the DCT clear pulse,
which is produced when the control element receives a DIA 7-4 command pulse.
Both the
write control and WFB are set to correspond to the contents of the computer 10 register bits 0
through 5 by the receipt of a DWC 10-4 command pu Ise from the computer. As in the read
control and RFB, the output from the write control fl ip-flop is suppl ied to the control element
to produce the read request and write request signals, and the five bits of the WFB are divided
to produce a 2-digit octal number varying from 0 through 37.
The 0 output of the write control
flip-flop is buffered by two parallel-connected bus drivers in the module at location 1 E3.
This
buffered output is supplied to each gate in the drum field select element to assure that writing
does not occur when the write control fl ip-flop is in the 0 status.
This logic is shown on the
lower left hand corner of engineering drawing 5.
Drum Field Select
Selection of the drum field, or address, of a transfer is performed by decoding and gating circuits shown in zones A, B, and C of engineering drawing 5.
The decoding involves negative
AND gates which combine the appropriate outputs of the most significant bits of the WFB and
RFB to produce the WFBH 0 through 3 signals and the RFBH 0 through 3 signals.
Normal binary-
to-octal decoders are used to combine the outputs of the four least significant bits of the WFB
and RFB to produce the eight WFBL and RFBL signals (Type 4151 modules at location 1 E16 and
1 E21, respectively).
Each of the 32 field select lines supplied to the data head selection diode
matrix within the drum housing is connected to the output of two negative AND diode gates
within a Type 4519 Drum Field Select module.
Therefore, each line is selected by diode gating
which combines the appropriate RFBH and RFBL information or which combines the appropriate
WFBH and WFBL information with the condition that the write control fI ip-flop is in the 1 status
and the appropriate WRITE FIELD LOCKOUT (WFLO) switch is in the down or enable position.
The WRITE FIELD LOCKOUT switches are located on panel 2D at the front of the parallel drum
and are used to inhibit writing in fields containing data which is not to be destroyed.
Placing
any of these octally numbered switches in the up position supplies the DCT disable - 3 vdc level
signal to terminal R of the appropriate drum field select module, thus inhibiting writing. With
2-8
the switches in the down position a ground level is supplied to terminal R and the gating is
enabled.
Pulsed Bus Transceiver
The pulsed bus transceiver provides a means of transmitting bidirectional data between the
parallel drum and the memory control.
The transceiver is a quadruple size standard DEC
Type 1665 module located in positions 1H24 and 1J24. This module consists of two sets of 18
2-input negative AND diode gates and 18 output pulse amplifiers.
Each of the pulse ampli-
fiers is triggered by one of the diode gates. The 18 input diode gates all receive one input
from a different bidirectional signal line which is connected by a coaxial cable to a similar
pulsed bus transceiver within the memory control.
The second input to each of the input
diode gates is common to allow sampl ing of the information of the signa I I ines when the address acknowledge pulse is received from the memory control. The output from these diode
gates provides a direct set input to the in buffer.
Each of the 18 output diode gates receives
an input from the output of one bit of the out buffer.
The second input to each of the output
diode gates is common and is connected to a pulse amplifier output which is triggered by the
phase 3 pulse. The output from each of these diode gates triggers a pulse amplifier, causing
it to pulse a bidirectional signal line.
Therefore, when the phase 3 pulse occurs, the contents
of the out buffer bits containing a 1 cause a negative pulse to be applied to the appropriate
bidirectional signal line of the pulsed bus transceiver.
Coaxial cables connect the pulsed
bus transceiver in the parallel drum to a pulsed bus transceiver within the memory control,
providing an efficient link of memory buffer register information between the two units.
The
pulsed bus transceiver module and the two pulse amplifier modules which functionally operate
as the pulsed bus transceiver are shown in zones A and B of engineering drawing 3.
I n Buffer (l B)
Data to be written on the drum is received in parallel from the 18 bits of the pulsed bus transceiver.
The in buffer stores this information temporarily and supplies it to the data writers and
to the p(Jrity formation circuit. When parity is formed, the write parity bit is a Iso suppl ied to
the data writer so that 19-bit words are written.
The in buffer also functions in exactly the
same manner during data reading so that the 19 information bits read by the data reader are
2-9
transferred to the out buffer, then are transferred from the out buffer to the pulse bus transceiver and then are transferred to the in buffer.
The in buffer suppl ies the 18 bits of the word
just read to the parity formation circuit, and a new write parity bit is formed.
This bit is
compared with the parity bit just read by the data reader and causes an error signal to be produced in the control element if the parity bit read in the new write parity bit formed is not
identi ca I .
Engineering drawing 3 shows the in buffer in zone A to consist of 18 fl ip-flops, each composed
of two cross-coupled transistor inverters.
Each flip-flop is set to the 1 status by a positive pulse
from the output of the associated input diode gate in the pulsed bus transceiver, and is cleared
by an inverted negative pulse produced at phase 2 time or when the address acknowledge pulse
is received.
Out Buffer (OB)
The out buffer provides temporary storage of data, wh i ch has been read by the data readers I
until the information can be sent to the memory control via the pulsed bus transceiver. Since
the memory control uses a split memory cycle, information read from core memory is not rewritten automatically.
Data transfer from memory control to the in buffer during a write only
operation is transferred to the data writer and to the out buffer.
in core memory from the out buffer.
The data can then be restored
This operation takes place as follows. At phase 1 time
instead of strobing new information from the data readers into the out buffer I the word wh ich
was read from the memory control exists in the in buffer and is transferred to the out buffer.
Writing takes place in the normal fashion, and at the end of the write strobe the in buffer is
cleared. Then at phase 3 time the word in the out buffer is returned to memory control to restore the word which was previously read from computer core memory and written into the in
buffer.
The out buffer is composed of 18 unbuffered fl ip- flops constructed of two cross- coup Ied trans istor inverters and appropriate gating for set and clear inputs. This logic is shown on zone C of
engineering drawing 3.
Each bit of the out buffer is cleared by the inverted negative pulse
produced by the lOB address acknowledge pulse.
During a read operation, the data reader
information (designated SAO through SAl?) is a negative pulse to signify a binary 1. The positive pu ises produced by inverting SAO through SAl? provide a direct set for the appropriate
2-10
bit of each out buffer flip-flop.
During a write only operation, the contents of the in buffer
are supplied to the level input of a Type 4127 Capacitor-Diode-Inverter moduie, which is
triggered at phase 1 time to produce the positive pulse required to set the appropriate bit of
the out buffer.
Parity Formation
The parity formation circuit continually generates the write parity signal according to the
contents of the in buffer and supplies this signal to the control element and to the write parity
bit of the data writer {for bit P}.
The write parity signal is generated by combining the out-
puts of eight Type 1130 Three- Bit Parity Circuit modules, each of which provides a parity
check of three input bits.
The first six Type 1130 modules compare the contents of three bits
of the in buffer. The output from three Type 1130 modu les is compared aga in in another Type
1130 module, and the output of the last two Type 1130 modules is combined in negative AND
gates formed by three of the circuits on the Type 6113 Diode Unit at location 1C3. The write
parity signa I is at - 3 vdc if the in buffer contains an even number of ones or is at ground
potential if the in buffer contains an odd number of ones.
The status of the write parity signal
is compared with the status of the write bad parity flip-flop to determine the status of the
write parity bit suppl ied to the data writer P.
The write bad parity fl ip-flop is composed of
two cross-coupled transistor inverters, which are cleared by receipt of power clear pulses or
by the wri te restart signa I, and is set to the 1 status by press i ng the WR ITE BAD PAR ITY pushbutton on the write field lockout switch panel before the transfer commences. When this
pushbutton is pressed, the fl ip-flop is set to 1, pin V of the negative AND gate at location
1E8 becomes a ground level, and pin K of the - AND gated location 1F7 becomes a - 3 vdc
level.
This gating inverts the signal supplied to the drum writer. After the first word has
been transferred, the write restart pulse is received from the memory control to clear the write
bad parity flip-flop and restore the normal conditions for generating the odd parity bit. The
WRITE BAD PARITY pushbutton is a maintenance device which allows diagnostic programs to
be written with an incorrect parity bit in the first word transferred; so a diagnostic program
can check the operation of the parity error circuits of the drum, or a programmer can use this
switch to test the error check routines within a given program. This switch is not used in norI
I..
,.
ma I aara rransrers.
2- 11
Parity Check
The parity check element compares the contents of the parity bit read from the drum with the
status of the write parity signal and generates a parity error set signal if an error is detected
when the drum is active and in the read status. This signal is a standard DEC positive pu Ise
which sets the parity error (PE) flip-flop in the control element. The logic which performs this
operation is shown in the lower right hand corner of engineering drawing 2.
When bit P of the data reader detects a 1, the SAp signal is a negative pulse which is supplied
to the set-to-one gate of the read parity fl ip-flop. This fl ip-flop is cleared by receipt of the
read restart signal from the memory control. The status of the read parity flip-flop is then compared with the write parity signal by the Type 6113 Diode Unit at location 1 E15 and 1 E8. The
output at terminal H of module 1 E8 becomes a ground level to indicate an error condition if the
write parity signal is even, and if a 0 is read from the parity bit. The output from the module
at location 1 E15 is negative to indicate an error if the write parity signal is odd and the parity data reader detected a 1. This ground level error signal supplies one input to a 3-inverter
ground-level AND gate. The output from this AND gate is a - 3 vdc error signa I only when
an error is detected, when the drum is in the active state, and the read control is active.
This
error signal is gated again by the negative AND gate which produces the positive parity error
set signal when the output of the transistor AND gate is negative at phase 4 time.
Data Writers
The 18 bits of data to be written are stored in the in buffer. The binary 1 output from each
flip-flop of the in buffer is supplied to a 2-input negative AND diode gate. The second input
to each of these AND gates is provided in common by the write strobe - write active signal.
This signal is generated by negative AND gates and is negative for the 2.6 microsecond duration of the write strobe pulse when the drum is in the active status and in the write mode.
The
output from each of the 2-input negative AND gates supplies the input to one side of one bit
of a Type 4518 Drum NRZ Writer module.
The inverted output of the 2-input negative AND
gate supplies the input to the second half of each bit of a Type 4518 module.
Each half of
each writer module is enabled by the write enable signal, which is a ground level signal produced by the drum being in the active state and in the write mode.
The complementary outputs
from each writer are suppiied, through the data-head seiection diode matrix, to opposite sides
2-12
of the read/write heads, through half of the head winding to the center tap.
This logic is
shown in zone A of engineering drawing 4.
Da ta Readers
Data read from the drum surface by the read/write heads is supplied, through the data-head
selection diode matrix, to the input terminals of the 19 data readers, or Type 1537 Drum
Sense Amplifier modules.
If the data read is in the 1 status at read strobe time, the sense am-
plifiers provide a Standard DEC negative Pulse which sets the 18 data bits into the contents of
the out buffer and sets the parity bit into the contents of the read parity flip-flop of the parity
check circuit. This logic is shown on zone C of engineering drawing 4.
Data Head Selection and Drum Memory
The drum housing mounted within cabinet 2 of the Type 23 Parallel Drum contains the data-head
selection diode matrix, the read/write heads mounted on a shroud, and the rotating drum memory
on which data is recorded.
Panels attached to each side of the drum housing by means of
captive screws are easily removed to allow access without disassembly or disconnection of
power and signal connections. Thus, drum maintenance can be undertaken under system operating conditions.
The drum housing is designed so that the fan action of the drum circulates air
around the drum and head mounts, keeping the temperature differential within the housing to a minimum.
Due to aerodynamic head suspension, thermal expansion is inconsequential; therefore, this
interna I circu lation, together with the externa I discharge from the fan motor, a Iso tends to
maintain a minimum differential temperature from inside to outside, so that repeated stops and
starts can be made wi thout danger of head eontact. The motor, wh i ch turns the drum, is of
special design to provide the fastest starting time compatable with minimum power input and
power losses at nearly synchronous speed. The fan for this single-phase, four-pole, induction,
capacitor-start and run motor is fastened to the bottom of the spindle. Ambient air is drawn
through a shroud and over the finned motor housing.
This air current takes heat away from the
motor, preventing loca Iized temperature rise.
The rotating drum assembly is designed with minimum cross-section for proper heat transfer and
dissipation.
It is mounted on separable inner-ring angular-contact bearings, which are prelubri-
cated for life.
Preloading is accomplished by springs at the top end of the unit.
2-13
The magnetic
coating on the surface of the drum is Grimaco 6037 - X high-density dispersion, heat-cured and
lapped to its final finish.
Dynamic runout is less than 0.0001 inch total indicated reading.
All data, index, and clock heads are mounted in pads of eight.
The pads are suspended from
the shroud surrounding the drum rotor, by flexible metal reeds. When the drum rotor reaches
approximately 90 per cent of synchronous speed, a 60-cycle current is applied to a heater
surrounding a bimetal strip, which in turn forces the head pad toward the drum surface.
travel of the bimetal strip is limited by a stop screw.
Total
The final running clearance between head
pole piece gap and the drum surface is set by the action of the precision flat ground head pad
aerodynamically flying on the liminal air film which surrounds the drum surface when at
nominal speed.
Initial factory adjustments are made by two differential screws which torque
the reed mounting to ensure that the pad is parallel to the drum surface and tangent at the
pole piece gap.
A printed-wiring board contains a 32-diode matrix used to select the eight heads on an associated pad. The connection of these diodes to a read/write head and connection to the logic
elements of the drum system is indicated in Figure 2-2. This figure indicates the equivalent
circuit of the logic elements as seen by the diode matrix, and indicates the flow of current
using an example where field select 0 is in the read state, field select 1 is in the write state,
and the balance of the field select circuits are deselected. When reading, a Type 4519 Field
Select module supplies 20 milliamperes to the common field select line connected to all head
centertaps for the appropriate field. A 1 mi II iampere current enters the centertap of each head
and divides, 1/2 mi II iampere going through each of the forward biased diodes to the input of
Type 1537 Drum Sense Ampl ifier {reader}. The division of current is assured by the 1K equivalent resistance at each input terminal of the sense amplifier. This rise of 1/2 milliampere
causes a 1/2 volt rise across each 1K resistor and places the common field select I ine at a
read potential of +4 volts. When a field select circuit is in a write state, the centertap of
the 19 common heads is returned via the field select to -14 volts. When a field selector is in
the write state, - 14.0 volts are applied to the center tap of the associated heads in the field.
Since no current limiting exists, a short circuit between any potential more positive than -14.0
volts and either an outside head winding terminal or a write bus selected in this manner destroys
{open}the head winding and/or the selection diodes.
When the Type 4518 Drum NRZ Writers
are gated on, each head returns approximately 90 mil!iamperes to this bus, for a toto! current
2-14
of approximately 1 .75 amperes. A head in the read select status is isolated from the write
•
!
J
e!
~
•
~
~
~
~.
~
~
~ ~
,..
,.
,-., "
bus by diodes whiCh are baCk blasea by a vOlTage ot trom :) to
1'1
I •
VOlTS.
A
A
I
I
I· _ I
• _
neaa wnlcn is
•
In
the write select state is disconnected from the read bus by diodes which are back biased by
a voltage of from 5 to 19 volts also.
Heads which are not selected are disconnected from the
read bus by diodes which are back biased at 3.5 volts and are disconnected from the write bus
by diodes which are back biased by a voltage from 1/2 to 15 volts, depending on the state of
the writer.
In this manner it is possible to connect any of the bit sense ampl ifiers to a head for the same
bit number in one of 32 fields, to connect the writer to one of the remaining 31 fields, and
to have the remaining 30 fields back biased.
Note that the common write bus for a bit is
essentially coupled to a read bus by many back biased diodes.
noise spikes being induced in the read bus at write time.
This coupiing resuits in iarge
Because of the recording technique
and timing used within the system, however, it is possible to strobe information from the sense
ampl ifier before the write strobe is created, thereby storing the data in the out buffer before
the large write transients occur.
Power Supp Iy and Distribution
The parallel drum operates from a single source of 115-volt, 60-cycle, single-phase power.
Control and overload protection for this power within the machine are exercised by a Type 813
Power Control. Operation of the power control can be controlled by the REMOTE ON/OFF/
LOCAL ON switch located on the indicator panel at the front of the machine, or by means of
a contact closure provided from the computer when the computer is energized.
The ac output
of the power control operates the two cabinet fan motors, the two Type 728 Power Supplies,
and the drum motor.
Primary ac voltage is also supplied to a step down transformer through
the normally closed contacts of a time-delay relay or (after the relay time has expired) through
a voltage dropping resistor.
This configuration provides a heater voltage to the bimeta I strips
in the drum of approximately 25 vac for the first 20 minutes of drum operation (current supplied
to the transformer primary through the normally closed relay contacts) and suppl ies a heater
voltage from 19.5 to 20.0 vac when the drum is ready for data transfers (current suppl ied to
the primary of the transformer through the voltage dropping resistor).
The primary of this
transformer is also protected by a 5-ampere indicating type fuse and is interrupted if the vane
2-15
....
__---------------------------------------------19BITS
~4
+~.:.4V
SENSE AMPLIFIER 0
AA
A
·1-VYIK
·VVV
IK
+3.5V
~--~
FIELD
READ
IK
IK
~~
1.0ma
r--
t
I
1
IK
IK
READ/WRITE HEAD
..... 1
II .....
READ/WRITE HEAD
~~ I--
..... 1
~~
r--
,
90ma
IK
+3.5V
I .....
~
1...1
~
........
A......
+3.5V
READ/WRITE HEAD
READ/WRITE HEAD
0.5ma ..... 1
t
AAA
V
+3.5V
~0.5ma
20ma CURRENT
SOURCE _
.....
J
IK
SENSE AMPLIFIER P
AAA
SENSE AMPLIFIER 17
SENSE AMPLIFIER I
+0.4V
I--
r--
~~
i---<
1
SELECT 0
......
~
~~
- ...
00 'ttf1'-.
I
..~
lJ....1...
~
r---'
32
FIELDS
..... 1
~~
f---<
J
-14·0 VOLTS
WRITE
FIELD
SELECT I
.~:::I.75amp
::
=r-- ~"-
:-
:: ::'
I
~
OFF
I
I
~
::
~
1 \
I
I
~
....;
~
-150~
N
I....
i---<
~
r~
--
:---::; .... ~
.....
READ/WRITE HEAD
READ/WRITE HEAD
READ/WRITE HEAD
ilA
I'V
_..-----
~
I--
READ/WRITE HEAD
N
I .....
~~ -...
>--'~
~
~
~or
.......
+0.5 VOLTS
FIELD
o CURRENT
..1 l
r
SELECT.':'
READ/WRITE HEAD
READ/WRITE HEAD
.....
~
....... 1
~~
o 5 VOLTS
o CURRENT
11.A
'--
..........
l>-
- --
J'oo....I
~O'
1I1~ t--
~
READ/WRITE HEAD
READ/WRITE HEAD
I....
".
~~
l...- I - -
I--
lvt
...J"-.L
....-- ~TI ~
f-
+
OFF
FIELD
SELECT 37
-
)
~--
-I V
1.5~
AI.5K
~@.:
120ll
WRITE I
ON
120ll
WRITE 0
~ .A1.5AK
I
~ ~
120ll
vv
-15V
-5V
1
120n
WRITE 0
o OFF
ON
1.5K
1.5!
~
WRITE I
oOFF
\
A
~E
WRITE I
ENABLE
ENABLE
1.5 K
ON
WRITE 0
0
WRITER
Figure 2-2
I
Data Head Selection
1.5K
1
YVV
12~n ~
f
'B
1.5K
120ll
WRITE I
ON
WRITE 0
o OFF
ENABLE
-=WRITER 0
OFF
-15V
;
WRITER 17
ENABLE
-=WRITER P
j
air switch on the top of the drum housing opens, indicating low drum speed. The bimetal
heater voltage is supplied in parallel to all of the bimetal strip heaters. The - 15 volt output
of the Type 728 Power Supply, which operates the indicator panel, is controlled by the normally open contact of the 20-minute time-delay relay. Therefore, the indicators do not
light until the drum has been en·ergized for 20 minutes, at which time the drum has reached
synchronous speed and thermal stability and is ready to transfer data. All ac and dc wiring
within the paralle! drum is indicated on engineering drawing PW-D-23-0-8 and on Figure 2-3.
FROM TYPE 728
-15 VDC
~~_______ TO
POWER SUPPLY --~----........ 1 2
• INDICATORS
3
TIME DELAY
RELAY SET TO
APPROXIMATELY
20 MINUTES
TERMINAL
STRIP
10./\. 160 W SET TO SUPPLY
20 VOLTS AT TRANSFORMER
__--~r~- -o-I____-
____SE-C-ON-D-AR-Y-W-IT-H-A-LL-BI-ME-TA'V'LI/'v
TO BIMETAL HEAD ACTUATORS.
APPROXIMATELY 25.0 VAC
INITIALLY, AND 19.5 TO 20.0 VAC
AFTER POWER IS APPLIED FOR
20 MINUTES.
AIR-VANE ON TOP
OF DRUM HOUSING
CLOSES AT MOTOR
SPEED OF 1670 RPM,
OPENS AT 1400 RPM.
Q-4----~~~Ir__4
WHITE
RED
DRUM HOUSING
GROUND
Figure 2-3
Drum Power Circuit
The normal module operating voltages of+10 and -15 vdc are supplied to each rack of logic
through a color-coded connector at the right side of each rack, as seen from the module side.
Marginal-check terminals on these connectors are connected in common on all module mounting
panels within the machine so that the + 10 volt mc can be used to marginal check the + 10 vdc
voltages· supplied to any mounting panel within the machine. The color-coding of these connectors is as follows, from top to bottom.
c.
Green, + 10 v mc from the computer
Red, +10 vdc internal supply
Black, ground
d.
..... • ...,"'" ,
e.
Yellow, -15 vdc external marginal-check supply (unused)
a.
b.
RIII.:a
_ 1"
• ...,
,,~,.
y,.".""
i..,+.:a,...,,..,1
1111'-'"
~II ........ I"
II .........
""t-'t".,
2-17
Three single-pole double-throw switches at the end of each rack of logic allow selection of
either the normal internal + 10 vdc power or an external marginal-check source of power for
distribution to the logic.
The top switch selects the + 10 vdc supply routed to terminal A of
all modules in that mounting panel.
In the down position the fixed internal + 10 volt supply
connected to the red terminal is routed to all of the modulesi in the up position the marginalcheck voltage connected to the green terminal is supplied to terminal A of all of the modules.
The center switch performs the same selection as the top switch for connection of a + 10 volt
supply to terminal B of all modules within a mounting panel.
The bottom switch selects the
- 15 volt supply to be routed to terminal C of all modules in a mounting panel.
In the down
position the fixed - 15 volt output of the internal power supply, received at the blue terminal,
is supplied to all of the modules; in the up position a marginal-check voltage, supplied by an
external supply connected to the yellow terminal, is supplied to terminal C of all modules.
However, since the - 15 volt supply is the collector load potential in most DEC modules and is
normally clamped at - 3 volts, marginal checking of this source has very little effect upon the
logical operation of the machine. Marginal checking of this line, however, does vary the
output of modules containing an output pulse amplifier, and is therefore useful in checking the
operation of circuits employing pulse amplifiers or in checking the operation of circuits which
follow them.
READ-WRITE CYCLE
Three computer lOT instructions initial ize and initiate a complete transfer.
are the DIA or DBA, DWC, and DCl, and must occur in this order.
These instructions
Each of these instructions
causes two 0.4 microsecond pulses to be supplied to the parallel drum, one at computer 7 time
(TP7) and one at computer 10 time (TP10).
The DIA instruction, for example, produces a DIA
7 -4 pu Ise at computer 7 time and a D fA 10=4 pu Ise at computer 10 time.
Norma!! y the pu Ise
supplied at computer 7 time clears a register and the pulse at computer 10 time, which is approximately 2.2 microseconds later, strobes information into or out of registers.
In the three
instruction sequence mentioned previously, the first command pulse received is a DIA 7-4
pulse, which clears all necessary control flip-flop registers.
The DIA 10-4 puise ioads the
read control flip-flop, loads the RFB, and loads the Il from the contents of the computer 10
register.
This same operation occurs during a DBA instruction except that the DBA 7-4 pulse
also sets the DBA sync flip-flop.
The second instruction clears the WC with a DWC 7-4 pulse,
2-18
then loads the write control fl ip-flop, loads the WFB, and loads the WC from the contents of the
computer 10 register by means of the DWC 10-4 puise.
ihe third instruction increments the
contents of the WC by one and clears the DCl by means of a DCl 7-4 pulse, then loads the
contents of the computer 10 register into the DCl and sets the busy flip-flop by means of the
Del 10-4 command pulse. This command pulse also initiates operation of the 2S0-microsecond
delay (Type 4301 module at location 1 F11) which eventually initiates the data transfer. After
giving the DCl instruction, the computer continues in the main program.
Engineering drawing
1 shows the timing of control signals and the flow of information during a transfer.
The 250-microsecond delay is necessary for the read and write field select circuits to assume
their respective states. Settling time for the readers is between SO and 100 microseconds.
Therefore I the 2S0-m icrosecond delay a Ilows a II transients to settle before the transfer commences.
When the 2S0-microsecond delay expires, the transfer request (TRA) flip-flop is set to 1, and the
timing of the transfer is now in the control of the drum timing and control elements.
Every 8.S microseconds the timing element produces a phase A pulse which increments the contents of the DC so that it keeps track of the angu lar position of the drum. When the drum position arrives at the drum address or initial location of the transfer, the DC=ll signal is produced.
The next phase A pulse sets the request (RQ) flip-flop to the 1 state. The request flip-flop then
signals the memory control that a transfer cycle is requested by the drum.
The change of state
of the request fl ip-flop from 0 to 1 sets the error sync fl ip-flop to the 1 status. When the request
is honored by memory control, the address acknowledge pu Ise is returned from the memory control to the drum.
This pulse immediately clears the error sync flip-flop.
If the request is
honored within approximately 5.1 microseconds, the next phase A pulse sets the active (ACT)
flip-flop to the 1 state, and data transfers occur within the current clock cycle.
If the address
acknowledge pulse is not received more than 2 microseconds before the phase A time occurs,
indicating that the request was not honored by memory control, the request fl ip-flop is cleared
and the parallel drum goes into a waiting loop. The TRA flip-flop remains in the 1 status and
again initiates a request when the DC= Il signal is generated. This takes one drum revolution
or approximately 35 mi \I iseconds.
Since the drum usually has the highest request priority, a drum request is normally honored by
memory co ntro I. When a drum request is made, memory contro I usua \I y comp Ietes the current
cycle and then honors the drum request by supplying an address acknowledge pulse after a period of from O. 1 to S. 1 microseconds.
2-19
On receipt of an address acknowledged pulse, the in buffer and the out buffers are cleared.
After a persod of 1 microsecond the error sync flip-flop is cleared, indicating that an address
acknowledge pulse has been received. At this time the DCl is incremented by 1.
Information
which has been read out of core memory is available in the memory buffer register and is strobed
into the drum in buffer via the pulsed bus transceiver 1.4 microseconds after the address acknowledge pulse is received. Memory control also supplies the read restart (RD RS) signal which
clears the read parity flip-flop approximately 1.4 microseconds after the address acknowledged
pulse is received. At the next phase A time the active flip-flop is set to 1 and the actual
transfer of information to and/or from the drum surface commences.
When the active fl ip- flop is set to 1, the interface tim i ng pu Ises, phase 1 through phase 3,
are generated by the tim ing element. At phase 1 time the read strobe pu Ise is produced to
read information from the read field selected and set it into the out buffer. The write strobe
begins O. 1 microseconds later and immediately writes the contents of the in buffer on the drum
surface and increments the contents of the WC by 1. At phase 2 time the writing operation
is completed and the in buffer is cleared. At phase 3 time the out buffer, which stored the
information previously read, sends the information back to memory control and to the in buffer
by means of the pulsed bus transceiver. At this time the write restart (WR RS) pulse is sent to
memory control, allowing the word which has iust been placed on the pulsed bus transceiver
MB lines to be rewritten in the computer core memory. As the word that was previously read
from the drum surface is now contained in the in buffer, the parity formation element receives
this information to generate the write parity bit. At phase 4 time the write parity bit just
formed is compared with the contents of the read parity fl ip-flop.
If the read parity bit and
the write parity bit are not equal, the parity error (PE) flip-flop is set to 1 at phase 4 time.
At the start of the next drum clock cycle, the phase A pulse sets the error sync flip-flop, and
the drum waits for an address acknowledge pulse to continue in a normal transfer.
If the most significant bit of the word counter overflowed during the previous transfer, that is,
is incremented to the point where it changes from the 1 to the 0 state, the request flip6
flop is immediately cleared. At the next phase A time fe! !ewing clearing of the request flip-
WC
flop, the active flip-flop is cleared, the busy flip-flop is cleared, and the sequence break
signal return pulse is supplied to the memory control to terminate the transfer.
If the WC did
not overflow during the previous transfer, the request fl ip-flop remains in the 1 status, and the
2-20
memory control passes into the first half of the next memory cycle.
The cycle repeats as
before; an address acknowledge signal must be received to continue the transfer.
If the ad-
dress acknowledge is not received within the allotted time, the next phase A pulse sets the
transfer error flip-flop and clears the request flip-flop.
The subsequent phase A pulse clears
the active flip-flop, generates a sequence break signal return pulse, and clears the busy flipflop.
Th is action term inates an unsuccessfu I transfer wh ich shou Id not occur in norma I opera-
tion, and so is indicative of equipment malfunction.
If the address acknowledge signa I is received, the transfer continues. When the correct number of words has been transferred, the
WC~
overflows and clears the request flip-flop. At
the subsequent phase A time the active fl ip-flop is cleared, a sequence break signa I return
pulse is generated and returned to the computer, and the busy flip-flop is cleared indicating
the end of a successful transfer.
At the end of any transfer the DRA instruction must be executed and the status of thE; error
flip-flops must be evaluated by the program before the data transferred can be deemed valid.
During the DRA instruction, the inclusive OR of the status of the parity error and transfer error
flip-flops is set into the contents of the computer 10 register bit 0, and the contents of the
parity error and the contents of the transfer error are set directly into the contents of the computer 10 register bits 1 and 2, respectively. A parity error indicates that data bits have
been picked up or dropped out during the transfer.
If the address acknowledge pu Ise is not re-
ceived for the initial word of a transfer, the transfer is never undertaken.
indicated by both the TRA and ERROR SYNC indicators being lit.
This condition is
If the address acknowledge
pulse is not received at any time during a transfer, both the TE indicator and the ERROR SYNC
indicator are lit. This is an abnormal condition which indicates equipment malfunction.
READ ONLY CYCLE
A read only cycle is simi lar to a read-write cycle except that the information is read out of
the computer core memory and placed in the contents of the in buffer. Generation of the write
current is inhibited and no writing takes place. At phase 2 time the in buffer is cleared and
the information that was received from core memory is lost, and the contents of core memory
remains all zeros.
New information which is read from the drum surface is then available in
the out buffer and is sent back to the memory control at the proper time and is written into
2-21
the vacant core memory address.
Parity checking occurs during a read only cycle. All timing
remains the same as in the read-write cycle.
WRITE ONLY CYCLE
The write only cycle is similar to the read-write cycle. However, at phase 1 time the word
which was read out of core memory exists in the in buffer and is transferred into the out buffer,
instead of strobing new information from the drum surface into the out buffer. Writing takes
place in the normal fashion, and the in buffer is cleared at the end of the write strobe pulse.
At phase 3 time the contents of the out buffer are sent back to memory control, thereby, restoring the word in core memory which was previously read (from the same address).
checking occurs during a write only cycle.
2-22
No parity
SECTION
3
INTERFACE
All logic signals which pass between the PDP-l D computer or the memory control and the
Type 23 Parallel Drum are standard DEC levels or standard DEC pu Ised. A standard DEC level
is either ground potential (O.O to -0.3 volts) or -3 volts (-3.0 to -4.0 volts). Standard DEC
pulses are 2.5 volts in amplitude (2.3 to 3.0 volts) and are referenced to the standard negative
level. The standard pulse duration is 70 nanoseconds for pulses originating in Series 1000
modules! and 400 nanoseconds for Series 4000 modules.
In addition to the logic signal inputs a contact closure in the computer power control circuit
provides the remote turn on signal to the power supply and distribution network in the parallel
drum.
In normal operation this signal is used to energize or de-energize the parallel drum
from the computer. The effect of this signa I can be disabled during maintenance operations
to control power application and removal via a switch on the indicator panel of the parallel
drum.
The adjustable + 10 volt mc voltage from the computer marginal check panel is also
supplied to the power supply and distribution element in the parallel drum to simplify drum
maintenance.
Interface signals which pass between the parallel drum and the PDP-1 D are listed in Tables
3-1 and 3-2 and on engineering drawing Cl-A-23-0-16. All of the interface signals which
flow between the parallel drum and the memory control are listed in Tables 3-3 and 3-4.
The
memory buffer register connections are made to the inside (handle) end of the pulsed bus transceiver in the drum and are shown on zone 1 B of engineering drawing BS-D-23-0-3. All other
interface connections from memory control are made to connectors
1 EO 1 or 1E02 on the drum.
All interface signal connections between the drum and the PDP-1 D are made to connector
2CO 1 on the drum.
Note that 10 input signa I levels to the WFB, RFB, DCl, and WC must be present for at least
1 microsecond before receipt of the lOT pulse which strobes the data contents into the fl ipflops.
This delay is required to a !low set up of the capacitor-diode gate at the input of each
flip- flop on the Type 4217 modu Ies.
3-1
TABLE 3-1
Signal
Cf
N~bal
INPlJTS TO DRUM FROM PDP-1D
From PDP-1D
Logic
To Parallel Drum
Connector
I
Logic
I
Drawing
1°0 .
--0
10 REG
2C01-l
WRITE,WFB
READ, RFB
5
5
1°1
--<>
10 REG
2COl-2
WRITE, WFB
READ, RFB
5
5
1°2
--<>
10 REG
2COl-3
DCL
READ, IFB
WRITE, WFB
6
5
5
1°3
--<>
10 REG
2COl-4
DCL
WRITE, WFB
READ, RF8
6
5
5
1°4
--<>
10 REG
2COl-5
DCL
WRITE, WFB
READ, RFB
6
5
5
1°5
--<>
10 REG
2CDl-6
DCL
WRITE, WFB
READ, RFB
6
5
5
"-l
10
6
0
10 REG
2COl-7
DCL, IL, WC
6
10
7
0
10 REG
2C01-S
DCL, IL, WC
6
10 REG
2COl-9
IL,
we
6
10 REG
2C01-10
IL,
we
6
lOS
1°2
---<>
---<>
TABLE 3-1
Signal Name
1°10
l°ll
1°12
1°13
1°14
w
I
1°15
w
1°'6
1°17
Symbol
<>
<>
<>
<>
<>
<>
<>
<>
I NPUTS TO DRUM FROM PDP-l D (continued)
To Parallel Drum
From PDP-l D
I
Logic
Drawin!~
Logic
Connector
10 REG
2C01-11
Il, WC
6
10 REG
2COl-12
IL, WC
6
10 REG
2COl-13
IL, WC
6
10 REG
2COl-14
IL, WC
6
10 REG
2COl-15
IL, WC
6
10 REG
2COl-16
IL, WC
6
10 REG
2COl-17
IL, WC
6
10 REG
2C01-·18
IL, WC
6
10 CONTROL
2COl-39
IL
CONTROL
6
2
DIA 7-4
-.
DIA 10-4
~
10 CONTROL
2COl-40
IL
READ, RFB
6
5
DWC 7-4
-..
10 CONTROL
2COl-41
WC
6
DWC 10-4
~
10 CONTROL
2COl-42
WC
WRITE, WFB
READ, RFB
6
5
5
TABLE 3-1
Signal
N:~~bal
To Parallel Drum
From PDP-1 D
Connector
logic
I
logic
I
Drawing
DCl7-4
----+
10 CONTROL
2COl-43
DCl
WC
6
6
DCl 10-4
----+
10 CONTROL
2COl-44
DCl
CONTROL
6
DRA 7-4
-~
lOT
2COl-45
CONTROL
2
DBA 7-4
-~
lOT
2COl-46
CONTROL
2
+ lOY Me
-~
MARGINAL CHECK
2COl-47
PS I DIS1
8
REMOTE ON
--~
POWER CONTROL
2COl-48
2COl-49
PS, DIST
8
w
I
~
I NPUTS TO DRUM FROM PDP-1 D (continued)
TABLE 3-2
Signal
Nam~bOI
ERROR STATUS
PE
TR ER
--
2
OUTPUTS FROM DRUM TO PDP-1 D
To PDP-1 D
From Parallel Drum
logic
I
Drawing
I
Connector
logic
CONTROL
2
2COl-19
10 CONTROL
CONTROL
2
2COl-20
10 CONTROL
CONTROL
2
2COl-21
10 CONTROL
TABLE 3-2
slignal
Name
OUTPUTS FROM DRUM TO PDP-l D {continued}
Logic
BUSY
DC
To PDP-l D
From Parallel Drum
Symbol
=> 10 STROBE
SBS RETURN
TABLE 3-3
wI
I
Drawing
I
Logic
Connector
CONTROL
2
2COl-22
STATUS REG
CONTROL
2
2COl-37
1M
CONTROL
2
2COl-38
SEQ BREAK
INPUTS TO DRUM FROM MEMORY CONTROL
From Memory
<.Jl
Signal Name
Symbol
Control
Logic
RD RS
~
To PCJrallel Drum
Connector
I
Logic
Drawin~J
MBI
1 El C
Parity Check
2
ADRS ACK
-.
MBI
1 El B
IB
PBT
3
3
MBO
~
MBI
1030-1
PBT
3
MBl
~
MBI
1030-2
PBT
3
MB2
~
MBI
1030-3
PBT
3
MB3
~
MBI
1030-4
PBT
3
TABLE 3-3
INPUTS TO DRUM FROM MEMORY CONTROL (continued)
From Memory
Signal Name
Symbol
Logic
,
Connector
I
Logic
I
Drawing
MB4
-~
MBI
1030-5
PBT
3
MB5
~
MBI
1030-6
PBT
3
MB6
-----..
MBI
1030-7
PBT
3
MB7
~
MBI
1030-8
PBT
3
MB8
~
MBI
1030-9
PBT
3
MBI
1030-10
PBT
3
MBI
1030-11
PBT
3
MBI
1030-12
PBT
3
MBI
1030-13
PBT
3
MBI
1030-14
PBT
3
MBI
1030-15
PBT
3
MBI
1030-16
PBT
3
w
0-
To Parallel Drum
Control
MB9
MB
10
MB11
---+
---+
---+
15
-.
-----..
-4
-----..
16
-4
MBI
1030-17
PBT
3
MB17
-4
MBI
1030-18
PBT
3
MB12
MB
13
MB14
MB
MB
TABLE 3-4
OUTPUTS FROM DRUM TO MEMORY CONTROL
From Parallel
Signal Name
Symbol
Drum
logic
O
DCl
2
l
DCl
2
O
DCl
3
DCl
wI
'-J
l
3
DCl
4
DCl
5
DCl
6
DC~
DCl
DCl
DCl
DCl
a
9
lO
l1
-.-----
To Memory Control
Connector
I
logic
Drawing
DCl
lE'OlK
MBI
6
DCl
lEOll
MBI
6
DCl
1 E01M
MBI
6
DCl
1 EOl N
MBI
6
DCl
lE02B
MBI
6
DCl
1 E02C
MBI
6
DCl
1 E02D
MBI
6
DCl
1 E02E
MBI
6
DCl
1 E02F
MBI
6
DCl
1 E02H
MBI
6
DCl
1 E02K
MBI
6
DCl
1 E02L
MBI
6
TABLE 3-4
OUTPUTS FROM DRUM TO MEMORY CONTROL {continued}
From Parallel
Signal Name
S)'mbol
logic
-
DCl
DCl
DCl
DCl
00
Connector
=
DCl
wI
To Memory Control
Drum
12
13
14
15
16
DCl l ?
RQ
RD REQ
WR REQ
WR RS
MBO_l?
~
.......
- .......
-
----
-.
------.
I
logic
I
Drawing
DCl
1E02M
MBI
6
DCl
1 E02N
MBI
6
DCl
1 E02P
MBI
6
DCl
1 E02R
MBI
6
DCl
1E02T
MBI
6
DCl
1E02U
MBI
6
CONTROL
1EOl F
MBI
2
CONTROL
1E02V
MBI
2
CONTROL
1 E02W
MBI
2
TIMING
2EOl D
MBI
2
PBT
See Table 3-3
MBI
3
SECTION 4
INSTALLATION AND OPERATION
SITE REQU IREMENTS
The insta Ilat ion site must prov ide floor space at least 47 inches w ide and 28 inches deep to
accommodate the parallel drum. At least 9 inches must be provided in front of the cabinet
and 15 inches at the back of the cab inet to a II ow open ing of the doors for rna intenance •
A source of 115-volts (±17 volts), 60 cycle, single-phase power must be suppl ied by the
site. This source must be capabie of suppiying the lO.O-ampere starting surge current and
9.0-ampere runn ing current required by the drum.
Ambient temperature at the installation site can vary between 32 and 105 degrees Fahrenheit (0 to 41 degrees centigrade) without deleterious effect upon equipment operation. For
norma I operat ion an amb ient temperature range from 70 to 85 degrees Fahrenhe it is
recommended.
Shipping weight of a Type 23 Parallei Drum is approximately 1090 pounds.
SIGNAL AND POWER CONNECTIONS
Signa I connec t ions to the Type 23 Para II e I Drum from the PD P-1 D are made at connec tor
2C01 on the plug panel at the front of the machine. Signal connections to the drum from
the memory control are made at connectors 1EOl and 1 E02 at the front of the machine. To
mate with these connectors, a cable should conta in an Amphenol connector of the 115-114P
series with a housing 1391 and wire clamp 3057. Signal cable I·ength should not exceed
25 feet. The input and output signals are defined in Tables 3-1 and 312 and their wiring
connections are given on sheets 1 and 2 of the engineering drawing A-24614. Data
connections to the drum from the memory control are made to the back of the Type 1665
Pulsed Bus Transceiver at location 1 H24. The data cable must be 18-conductor coaxial,
term inated in a Type 1031 or 1032 module.
4-1
A grounded, three-wire power cable is permanently attached to the machine. A standard
3-prong male power plug at the end of this cable allows connection to a power source 18
feet from the cabinet.
CONTROLS AND INDICATORS
Manual control of the parallel drum is exercised by means of switches on the indicator panel
(lA) and on the field lockout switch panel (2D). Visual indications of the machine status
and register contents is given on the indicator panel and the auxil iary indicator panel (2A)
shown in Figure 4-1. The function of all machine controls and indicators is given in
Table 4-1 .
Figure 4-1
TABLE 4-1
Indicator Panels
CONTROLS AND INDICATORS
Control or
Ind icator
Function
Indicator Panel
REMOTE ON/OFF/LOCAL ON switch
Allows local or remote control of mach ine
.....
I"'h
..
energlZQlion.
n I e RJ:MO TC
IL f""\N
'-'I
position
the machine is energized by a contact
closure in the computer. The OFF and
LOCAL ON positions function as a normal
power sw itch.
L.
TRA ind icator
\
Lights to acknowledge rece ipt of DC L transfer lOT pu Ises and ind icates that the drum
is waiting for the drum counter to arrive at
the starting address of the transfer spec ified
by the contents at the initial location
reg ister.
4-2
TABLE 4-1
CONTROLS ANO INO ICATORS (continued)
Control or
Indicator
Function
RQ ind icator
Lights to indicate that a t:equest signal has
been sent to the memory control to request a
transfer. This indicator remains lit for the
duration of a transfer.
ACT ind icator
Lights to indicate that the drum is actively
transferring data with the memory control.
ERROR SYNC indicator
Lights to ind icate the 1 status of the error
sync fl ip-flop. Th is fl ip-flop is set at the
time the request signai is sent to the memory
control and should be turned off within 6
microseconds by rece ipt of an address acknowledged signal from the memory control.
If th is ind icator is Iit and the TRA ind icator
is I it, the first acknowledged pulse has not
been rece ived from the memory control and
no transfer has occurred. If th is ind icator
is I it and the TE indicator is I it, a transfer
was started and erroneously interrupted.
ORA ind icator
Lights to ind icate the binary 1 status of the
ORA sync fl ip-flop. Th is fl ip-flop is set to
1 by receipt of a ORA 7-4 pulse which causes
the current address conta ined in the drum
counter to be strobed into the input-output
(10) register of the PDP-1 D, therefore allowing a rap id transfer of 4096 words beg inn ing
at an address determ ined by the current
drum position and a program-added constant.
DBA ind icator
Ind icates the binary 1 status of the drum break
address (DBA) sync fl ip-flop. Th is fl ip-flop
is set to 1 by receipt of a DBA 7-4 lOT pulse
from the PDP-l D. The next phase A clock
pulse clears th is fl ip-flop and causes generation of a sequence break signal return wh ich
is suppl ied to the PDP-1 D when the drum
counter equa Is the location reg ister. Th is
pulse also clears the busy fl ip-flop.
4-3
TABLE 4-1
CONTROLS AND IND ICATORS (continued)
Control or
Indicator
Function
RP ind icator
Lights to indicate the binary 1 status of the
read parity fl ip-flop wh ich stores the parity
b it just read from the drum. The contents
of th is fl ip-flop are compared with a reformed
par ity b it for the word just read as a par ity
error check.
WRITE and FIELD indicators
Light to ind icate the 1 status of the write
and write-field buffer fl ip-flops wh ich are
set by the contents of bits 0-5 of the 10
register during DWC 10-4 instruction. The
contents of the buffer ind icate the wr ite
field currently selected.
READ and FIELD ind icators
Light to indicate the binary 1 status of the
read fl ip-flop and the read field buffer
reg ister fl ip-flops. These fl ip-flops are set
by the contents of 10 register bits 0-5 during
a D IA 10-4 instruc t ion. The contents of the
buffer ind icate the read field currently
selected.
PE ind icator
Lights to ind icate that the mach ine has detected a read parity error (b its have been
pic ked up or dropped ou t of the word jus t
read, the READ BAD PAR ITY pushbutton has
been pressed prior to the transfer, or the
parity formation or check circuits are
defec t ive) •
TE ind icator
Lights to ind icate that the mach ine has detected a transfer error in wh ich a transfer was
interrupted before it was comp!eted.
INITIAL LOCATION indicators
Light to ind icate the binary 1 status of bits
in the location register. The word in the
location register spec ifies the first address
of a transfer.
WORD COUNTER indicators
Light to ind icate the binary 1 status of the
word counter fl ip-flops. The contents of the
word counters spec ify the number of words to
be transferred.
4-4
CONTROLS AND IND ICATORS (continued)
TABLE 4-1
Control or
Indicator
Function
Light to indicate the binary 1 status of bits
of the drum counter. The contents of the
drum counter indicates the angular position
of the drum as divided into 4096 positions.
DRUM COUNTER ind icators
Aux iI iary lnd icator Pane I
MEM SEL ind icators
Light to ind icate the bi nary 1 status of the
two most sign ificant b its of the drum core
location counter. Th is number spec ified the
bank of computer core memory to or from
which data is transferred with the drum.
CORE ADDRE SS ind icators
Light to ind icate the binary 1 status of bits
in the drum core locat ion counter. Th is
number ind icates the address of core memory
to or from which data is being transferred.
DRUM WR ITE BUFFER ind icators
Light to ind icate the binary 1 status of eac h
b it of the in buffer. The contents of th is
reg ister are written on the drum during a wr ite
operation and are used to form the parity bit.
Dur ing read operat ion, the contents of th is
reg ister are used to generate a par ity bit
wh ich is compared with the contents of the
read parity fl ip-flop for parity error checking.
DRUM READ BUFFER ind icators
Light to ind icate the binary 1 status of bits
of the out buffer. The contents of th is reg ister ind icate the contents of the word just read
from the drum during a read operation. During
a write operation, the contents of this register
are returned to the memory control to restore
the same information core memory.
Fie Id Lockou t Sw itc h Pane I
WRITE FIELD LOCKOUT
SW ITCHE S FO through F37
Each switch allows 1 field {4096 words} to be
inhibited during writing. Therefore, the information stored in a field cannot be acc identally destroyed by writing new information
over that presently conta ined in the field.
4-5
TABLE 4-1
CONTROLS AND INDICATORS (continued)
Control or
Indicator
Function
Allows the first word of the next transfer to
be written with an incorrect parity bit so
that a routine can check the operation of
the error parity c ircu its. A programmer can
use this switch to test his error check programs.
WR ITE BAD PAR lTV pushbutton
EQUIPMENT TURN-ON AND TURN-OFF
Operation of the Type 23 can be controlled locally by operation of a switch, or remotely
from a circuit closure in the computer. Control point is selected at the REMOTE ON/OFF/
LOCAL ON switch on the indicator panel.
In normal use this switch is left in the REMOTE
ON position. For maintenance operations this switch is set to the LOCAL ON position
to apply power and to the OFF pos ition to remove power.
Note that the c ircu it breaker
on the Type 813 Power Control must be in the ON position to allow either local or remote
control of primary power in the parallel drum.
4-6
SECTION 5
PROGRAMMING
The PDP-1D lOT instructions which operate the Type 23 Parallel Drum are listed in Table 5-1.
Octal codes containing
XiS
indicate bits which are not appl icable and can be either ones or
zeros. Octal codes specifying zeros must contain zeros.
TABLE 5-1 INSTRUCTIONS
Octal
Code
72XX61
Mnemonic
Code
DIA
Name and Function
Drum Initia I Address. load read control,
read field buffer, and initial location.
C(lO)~ => C(Read) 1 to specify reading
1
1
C(lO)l_5 =>C(RFB)1_5 to select read
field
C(lO) !-17 => C(I l) !-17 to specify initial drum address.
72XX62
DWC
Drum Word Count. load write control,
write-field buffer, and word counter.
C(lO)~ =>C(Write) 1 to specify writing
C(l0)~_5=> C(WFB)~ -5 to select write
field
C(l0)~_17=>C(WC)!_17 to specify the
number of words to be transferred.
72XX63
DCl
Drum Core location. load drum core location register with Memory Select and computer address of initial transfer; then initiate
a transfer. The transfer begins when the drum
reaches the address contained in the initial
location register.. When the transfer is complete, the drum c Iears the request fl ip-flop.
5-1
TABLE 5-1
Octal
Code
72XX63 (cont'd)
INSTRUCTIONS (continued)
Mnemonic
Code
DCl
Name and Function
1
1
C(l0)2_17 =>C(DCL)2_17
Bits
10~-3
select a memory bank as fol-
lows:
o
0
o
1
Bank 0 = 102 and 103
Bank 1 = 102 and 103
1
0
Bank 2 = 102 and 103
1
1
Bank 3 = 102 and 103
Bits
10~-17 specify
the address set into the
memory control memory address register.
722061
DBA
Drum Break Address. Same as DIA instruction; when C(DC) = C(lL) the drum gives
a sequence break return signal which indicates that the drum is ready to be reinitialized for another transfer and initiates a sequence break.
732062
DRA
Drum Request Address. The current drum address is transferred from the drum counter to
the computer 10 register. This number can
then be incremented by 778 and set into the
initial location counter during a DIA instruction for effecient transfer of 4096 words.
1
1
C(DC)6_17 =>C(lO)6_17
1
C(Error Status) =>C(lO)O
1
C(PE) =>C(lO):
C(TE)
5-2
1
=>C(lO)~
A program to initial ize and initiate a transfer of data between the memory control and the
parallel drum consist of the instructions DIA, owe, and Del in that sequence.
If the program
uses the sequence break facilities of the computer, the program sequence is DBA, owe, and
Del. When a transfer of 4096 words is planned, the ORA instruction can be used to save computer time. Since in a 4096-word transfer all addresses of a fie Id are used, the transfer can
begin and end at any address. Therefore, the ORA instruction is used to locate the current address of the drum. Thisaddress can be incremented by a predetermined value to form a number
which represents the predicted drum address when the transfer will be initiated. The number
added to the drum address is based on the drum changing addresses every 8.5 microseconds and
is calculated to use drum time equal to the computer program time required to reach the Del
instruction. This number has been determined empirically, in a typical program, to be 77 •
8
Transfers from 1 to 4096 words can be executed at a.rate of one word every 8.5 microseconds,
exclusive of program initial ization and from address access time. Reading and writing can
occur simultaneously, allowing the exchange of 4096 words in approximately 35 milliseconds.
After a program has been completed, the program must perform a ORA instruction and check the
error status of the drum to assure the validity of the data transferred. If the error status is a
0, the transfer is valid and the program can continue or a new initialization can be initiated.
If the error status is a 1, check the contents of PE and TE. If the PE is a 1, one or more data
words were transferred incorrectly (bits were picked up or dropped out). If the TE is a 1, the
transfer was terminated prematurely or was not enacted (addresses in core memory which were
to be read from the drum or drum addresses which were to be written in may be cleared or contain
previous information).
In either case, repeat the transfer or commence drum corrective main-
tenance procedures.
5-3
SECTION
6
MAINTENANCE
Maintenance of the Type 23 Parallel Drum consists of procedures repeated periodically as preventive maintenance, and tasks performed in the event of equipment malfunction as corrective
maintenance. The procedures presented here assume that the reader understands the function
of the controls and indicators described in Table 4-1, and is familiar with PDP-l D and drum
programming described in the PDP-l handbook and in Section 5 of this manua I. Maintenance
activities require use of the equipment listed in Table 6-1, or equivalent, as well as the use
of standard hand tools, cleansers, and test cables and probes.
TABLE 6-1
MAINTENANCE EQUIPMENT
Manufacturer
Model
Multimeter
Triplett or Simpson
630-NA or 260
Oscilloscope
Tektron ix
540 Series
Parallel Drum Diagnostic
Program Tape
DEC
DEC-1-137-M
System Modu Ie Extender*
DEC
1954
System Modu Ie Pu II er*
DEC
1960
Equipment
*One suppl ied with the equipment
If it is necessary to remove modules during either preventive or corrective maintenance, the
Type 1960 System Modu Ie Pu II er shou Id be used. Turn off a II power before extract i ng or i nserting modules. Carefully hook the small flange of the module puller over the center of the
module rim, and gently pull the module from the mounting panel.
Use a straight even pull
to avoid damage to plug connections or twisting of the printed-wiring board.
Since the puller
does not fasten to the module, grasp the rim of the module to prevent it from falling.
Access
to controls on the module for use in adjustment, or access to points used in signal tracing can
be gained by removing the moduie, connecting a Type 1954 System Moduie Extender into the
mounting panel, and then inserting the module into the extender.
6-1
ABC
D
E
F
G
H
I~~~~~~~~
II~~~~
"----.r---'''---y--J''---y--J''-y---J''-y---J''-y---J''---y--J''---y--J
FIELDS
FIELDS
FIELDS
FIELDS
FIELDS
FIELDS
FIELDS
30-37
20-27
10-17
0-7
30-37
20-27
10-17
y
y
FRONT
RIGHT SIDE
Figure 6-1
y
BACK
FIELDS
0-7
y
LEFT SIDE
Pad Location
Drum Housing Component Locations and Wiring
Around the surface of the drum shroud are 8 columns; each column contains 11 horizontal rows
of read/write head mounting pads. The location of these pads is indicated in Figure 6-1. The
columns are lettered A through H around the periphery of the drum and are suitably engraved.
The rows are numbered from 1 through 11 from top to bottom, row 6 being used primarily to hold
spare read/write heads.
fields.
Four of these pads are required to contain 1 bit from each of the 32
For example, to locate a pad containing bit 2 of field 12 it is necessary to remove the
right side panel of the drum housing.
By inspection, locate column C and count down for the
third pad for bit 2. This pad contains bit 2 for fields 10 through 17.
6-2
PAD OF 8
HEADS
0
RECEPTACLE
MOUNTED ON
HEAD BAR
\~ ~
2
3
4
\
6
HEAD
TERMINAL CONNECTIONS
HEAD WIRING COLOR
RED
BLACK
0
A2
Bt
At
t
Dt
C2
D2
2
GREEN
\~~\
3
\
4
2
A4
B3
A3
5
3
D3
C4
D4
4
A5
B5
A6
5
D6
C6
D5
7
6
A7
87
A8
8
7
D8
C8
D7
\
\~ ~
\
5
\
\
RECEPTACLE
\~ ~
\
D
C
B
\
\
\
\
6
A
7
Figure 6-2
Head Wiring
HEAD NUMBER
FROM ONE PAD
-..,-_x::-..,_ READ
o.
DIODE AND GATE CONNECTIONS
BROWN
ORANGE
GREEN
WHITE
b. DIODE BOARD PLUG WIRING OF FIELD SELECT LINES TO
HEAD CENTER TAPS. EACH COLOR IS USED FOUR TIMES
FOR THE 32 FIELDS
Figuie 6=3
Diode Board
6-3
BUS (TWISTED PAIR
1
DIFFERENTIAL ADJUSTMENT
(LOW FIELD)
BIMETAL STRIP - - -
DIFFERENTIAL
ADJUSTMENT
(HIGH FIELD)
Figure 6-4
Read/Write Head Components
CAUTION
When a field selector is in the write state, -14.0 volts are applied
to the centertap of the associated heads in the field. Since no
current limiting exists, a short circuit between any potential more
positive than -14.0 volts and an outside winding terminal or a write
bus of a head selected in this manner results in destruction (opening) of the head winding and/or the select diodes.
Heads are numbered from 0 through 7 from top to bottom within a pad as indicated in Figure 6-2.
This figure also indicates the wiring from the heads to the receptacle mounted on the head bar.
This wiring connects to the plug in the center of the printed-wiring boards containing the head
selection diode matrix. This wiring is color coded by field number so that black refers to field
0; la, 20, or 30; brown to field 1! 11! 21, or 31; red to field 2, 12, 22, or 32, etc. This
color coding and the wiring and positions of diodes within a head selection board are indicated
in Figure 6-3.
Note that there are 32 diodes on each board, 4 associated with each head.
The field select lines attached to the centertap of each head are located by the wiring color
code. At the top of each head selection board is a twisted pair of red and green wires which
make up the write bus. At the bottom of each board is another red and green twisted pair of
wires which are the read bus.
Both these bus lines are tagged for identification.
6-4
The component parts of a pad of read/write heads are identified in Figure 6-4. The two differentiai adjustment screws provide a fine adjustment for the distance between the pad and the
drum surface. Turning the upper differential adjustment ofa pad counterclockwise moves one
end of the pad toward the drum surface so that the displacement of head
displacement of head 7 is the least.
a is
greatest, and the
Differential movement of each head as the adjustment is
turned is inversely proportional to the distance of each head from the adjusting screw. Therefore, turning the lower differential screw clockwise moves the pad nearer to the drum surface
in a manner which increases the output vo Itage read from head 7 a greater amount than head O.
Turning both differential screws the same amount in the same direction should effect the output
voltage from all heads by the same amount. The flying position stop limits the minimum head-
.
to-drum surface distance. The course head osition adiustment is factory-set
so that field
,
0.
adjustment should not be necessary. The bimetal strip increases and decreases the pressure on
the head, and therefore changes the head-to-drum surface distance as a function of interna I
drum housing temperature and drum speed of rotation.
At all times during any adjustmentofa pad, listen carefully to assure that the pad does not
come in contact with the drum surface. Any contact noise indicates a maladjustment.
Imme-
diately reverse direction of all adjustments and readjust the stop screw. After an adjustment
has been made, stop the drum motor and Iisten for contact no isei then restart the motor and
Iisten carefully again.
If it is necessary to gain access to the right side of the drum housing for maintenance of bits
through 9 of fields
a through
a
7 or 10 through 17, the end panels of the parallel drum system
cabinet must be removed. These panels are removed simply by Iifting them above the frame
on which they are hooked at top and bottom.
PREVENTIVE MAINTENANCE
Preventive maintenance consists of tasks performed prior to the initial operation of the equipment and periodically during its operating life to ensure that it is in satisfactory operating
condition.
Faithful performance of these tasks forestalls possible future failure by correcting
minor damage and discovering progressive deterioration at an early stage. A log book used to
record data found during the performance of each preventive maintenance task will indicate
the rate of circuit operations deterioration and provide information to determine when components
6-5
should be replaced to prevent failure of the equipment. These tasks consist of mechanical
checks, which include cleaning and visual inspections; checks of specific circuit elements
such as the power supplies, clock and delay module timing, sense amplifiers, and magnetic
heads; and marginal checks which aggravate border line conditions or intermittent failure so
that they can be detected and corrected. All preventive maintenance tasks should be performed
as a function of conditions at the insta lIation site and the down-time Iimitations of equipment
use.
Perform the mechanical checks at least once each month or as often as required to allow
efficient functioning of the air filters. All other tasks should be performed on a regular schedule,
at an interval determined by the reliability requirements of the system.
For a typical applica-
tion a schedule of every four months or 700 equipment operating hours, whichever occurs first,
is suggested.
Mechanical Checks
Assure good mechanical operation of the equipment by performing the following steps and the
indicated corrective action for any substandard conditions found:
1. Clean the exterior and the interior of the equipment cabinet using a
vacuum cleaner or clean cloths moistened in nonflammable solvent.
2. Clean the air filter at the bottom of each cabinet. Remove the filter by
removing the fan and housing, which are held in place by two knurled and
slotted captive screws. Wash the filters in soapy water, dry in an oven or
by spraying with compressed gas, and spray with Filter-Kote (Research
Products Corporation, Madison, Wisconsin) before replacing them in the
cabinets.
3. Lubricate door hinges and casters with a I ight machine oil. Wipe off
excess oil.
4.
Visually inspect the equipment for completness and general condition.
Repaint any scratched or corroded areas with DEC blue enamel, number
5150-565.
5.
Inspect all wiring and cables for cuts, breaks, fraying, deterioration,
'K:nK's
I
I
,
st ..,..: ....
.\wIIII,
0"",..1 ",,",0,..\....,....,,;,..,..1 v"
Co"'''r·,f-u
...... '"
IIY
. . . ""' ..... 11 ...... 111""..."..
I,.
fective wiring.
6-6
6.
Inspect the following for secutiry: switches, knobs, jacks, connectors,
transformers, fan, capacitors, iamp assembiies, etc. Tighten or replace as
required.
7.
Inspect all mounting panels of logic to assure that each modu Ie is se-
curely seated in its connector.
8.
Inspect power supply capacitors for leaks, bulges, or discolorations.
Replace any capacitors giving these signs of malfunction.
Power Supply Checks
Check the output voltage and ripple content of the Type 728 Powe.r Supplies and assure that
j
they are within tolerance. Use the multimeter to make the output voltage measurements without disconnecting the load.
Use the osc illoscope to measure the peak-to-peak ripple content
on dc outputs of the supplies. These supplies are not adjustable; so if the output voltage or
ripple content is not within the tolerance spec ified, the supply is considered defective and
troubleshooting procedures should be undertaken.
Check the +10 volt output between the black (-) and the red (+) terminals to assure that it is
between 9.5 and 11.0 volts with less than 800 millivolts ripple. Check the -15 volt output
between the black (+) and blue (-) terminals to assure that it is between 14.5 and 16.0 volts
with less than 400 millivolts ripple.
Note that the black terminals are common with the power
supply chassis.
Tim ing Checks
There are four variable timing adjustments in the Type 23 Parallel Drum.
Using the oscilloscope
and referring to engineering drawings BS-D-23-0-2 and BS-D-23-0-4, check the timing of the
Type 4401 Variable Clock at location 1 F2, the Type 4301 Delay at location 1 F11, and the two
Type 1304 Delay modules at locations lH6 and 2B3.
If necessary, the timing of these modules
can be adjusted by turning the potentiometer screw, which is accessible through a hole in the
handle.
Check the timing of the variable clock to assure that standard DEC positive pulses occur at
termina I 1 F2F every 2 to 5 microseconds when the module is uninhibited. The c lock can be
6-7
made free-running for this check by grounding the cathode of the diode input at terminal 1 E83J.
Be sure to remove this ground connection at the completion of this check or subsequent data
transfers will be invalid.
Check the timing of the write strobe delay at location lH6. The output at terminal 1 H6J
should be a negative level for 2.6 microseconds, occurring approximately every 8.5 microseconds
as long as the drum is rotating. The oscilloscope can be synchronized on the negative leading
edge of the clock pulse at location 1 H5X when making this measurement.
Check the timing of the TRA delay at location 1 F11 to assure that it is set for a minimum of
250 microseconds. To perform this check the delay can be initiated repeatedly by connecting
the input terminal 1 F11Y to the clock pulse at location 1 H5X or the delayed clock pulse at
1 H6E. The delay can be measured as the time between the negative initiating pulse and the
negative output pulse at location 1 Fll E, or can be measured as a 250-microsecond negative
level at output terminal 1 F11 J.
Check the timing of the index delay at location 2B3. This delay should be adjusted for a
minimum delay which will place the index pulse at location 2B3E between successive phase A
clock pu Ises, which can be observed at location 1 H 1OV .
Drum Sense Amplifier Checks
The Type 1537 Drum Sense Ampl ifier modules (or readers) are checked for proper sl ice or threshold level by observing the amount the dc output base I ine at terminal S shifts with respect to
ground when the input signal is received. The index reader at location 2B6, the clock reader
at location 2B5, and the data readers at successive locations 2B7 through 2B25 are shown on
engineering drawing BS-D-23-0-4. The clock track reader slice level output should shift by
+100 millivolts. The index and data track sense amplifier slice level should shift by +275 milli-
volts. Adjustment of the slice level can be achieved by turning the potentiometer screw which
is accessible through a hole in the module handle.
Index and Clock Head Spacing Checks
Mechanical adjustment of the index and clock heads can be checked by measuring the preamplifier output of the appropriate Type 1537 Drum Sense Amplifier modules at terminals 2B6S
6-8
{index} and 2B5S {clock}. This output should be approximately 1.4 volts peak-to-peak, as
measured on an osci Iloscope. Adjustment of the head shouid be undertaken only if the preamplifier output is less than 1.0 volt, if the head has been replaced, or when operationl tests
clearly indicate that it is required. Adjustment is made by means of the stop screw.
In any changes of the leads to the index or clock readers or to the index or clock heads, care
must be taken to avoid any transients caused by soldering irons, static charges, etc. as they
inadvertantly erase or destroy the prerecorded information on these tracks. The input terminals
to the index and clock readers are normally protected with insulation to avoid inadvertant
grounding.
Grounding of any of the leads at the input of either the index or c lock reader
erases the prerecorded information on that track if drum power is on.
No danger exists to the
prerecorded information on the index and clock tracks when the parallel drum is de-energized
and soldering of leads can be accompl ished by means of a soldering iron containing an isolation
transformer.
Data Head Spac ing Checks
Check the mechanical spacing of each data head by measuring the output voltage of the appropriate Type 1537 Drum Sense Amplifier at the output of the preamplifier, which is terminal S.
The readers for bits
a through
17 are found in locations 2B8 through 2B25, respectively, and
the parity bit is in location 2B7. The best method of making this check is to run a program in
which patterns of all ones or alternate ones and zeros are written on a selected track, then
continuously read as data is monitored on an oscilloscope.
In this manner the contents of the
read field buffer can be changed by means of the program to check the output from each head
and all fields.
If test data patterns are to be written during this check, and if the data on the
drum surface is to be retained, it should be read into the computer core memory, the check
performed on a specific field, and the data rewritten into that field at the end of the check.
If the check is to be performed without the use of the computer, the read control fl ip-flop and
the read field buffer flip-flops can be cleared or set manually by momentarily supplying a
ground potential to the appropriate flip-flop output.
6-9
CAUTION
When a field selector is in the write state, -14.0 volts are applied
to the centertap of the associated heads in the field. Since no
current limiting exists, a short circuit between any potential more
positive than -14.0 volts and an outside winding terminal or a write
bus of a head selected in this manner results in destruction (opening) of the head winding and/or the select diodes.
Binary ones should produce an output of 1 .4 volts peak-to-peak in any data patterns. Adjustment of the head should be undertaken only if the reader output is substantially less than
1 .4 volts, if the head has been replaced, or when operational tests clearly indicate that it is
required.
To determine if a pad of read/write heads needs be adjusted, connect the oscilloscope to terminal S of the appropriate reader module for the bit to be checked, and read and record the
output obtained as the bit is read from each of the 7 heads selected by the contents of the read
field buffer. The average output obtained from fields 0 through 3 should equal the average
output obtained from fields 4 through 7.
If fields 0 through 3 produce a lower output than
fields 4 through 7, turn the upper differential screw clockwise or turn the lower differential
screw counterclockwise.
If a higher output is obtained from fields 0 through 3 than is obtained
from fields 4 through 7, turn the upper differential screw counterclockwise or turn the lower
differential screw clockwise.
For example, if the lower numbered fields are providing an out-
put lower than 1.4 volts and the higher fields are producing an output of no less than 1.4 volts
adjust the upper screw clockwise.
However, if the low numbered fields produce an average
output which is no less than 1.4 volts and the high order fields produce an average output
voltage much greater than 1.4 volts, turn the lower differential screw counterclockwise.
If
both high and low order fields produce average voltages which are approximately equal but
less than 1.4 volts, turn the stop screw counterclockwise.
If thisdoes not result in higher
average output signals, adjust both differential screws clockwise or counterclockwise by the
same amount.
After every adjustment rewrite the information passed by the adjusted pads and
then read it again.
6-10
Marginal Checks
Marginal checks are performed to aggravate borderl ine circuit conditions within the control
logic to produce observable faults. Therefore, conditions caused by marginal components can
be corrected during scheduled preventive maintenance to forestall possible future equipment
failure. These checks can also be used as a troubleshooting aid to locate marginal or interm ittent components, such as deteriorating transistors.
The checks are performed by operating the logic circuits from an adiustable external power
supply such as the + 1Ov mc level adjusted at the computer marginal check switch panel or
a separate external supply such as a DEC Type 730 Dual Variable Power Supply. Raising the
bias voltage above + 10 increases the transistor cut-off bias that must be overcome by the previous driving transistor; therefore low-gain transistors fail. Lowering the bias voltage below
+ 10 reduces transistor base bias and noise rejection and thus provides a test to detect highleakage transistors and to simulate high temperature conditions (to check for thermal runaway).
Raising and lowering the -15 volt supply has Iittle effect upon the logic circuits, since it is
the collector load voltage which is clamped at -3 volts in most modules. It does, however,
increase and decrease the output pulse amplitude of pulse amplifier circuits (such as in delay
modules) and so provides a check of the sensitivity of circuits which follow.
By recording the level of bias voltage at which circuits fail, progressive deterioration can be
plotted and expected failure dates predicted. Therefore, these checks provide a means of
planned replacement. Varying the + lOA supply to module mounting panel 2A changes the
slice level of all of the Type 1537 Drum Sense Amplifier modules. Therefore, the margins give
a ~od indication of drum read capability. A positive margin can be used to locate the lowest
output signal which can be read, and a negative margin can be used to detect the presence of
a high noise level or low noise reiection level of a module. Failure to obtain a reasonable
margin when lowering the + lOA supply indicates that the sl ice level is too low and the ampl ifier is not rejecting noise or that noise is being picked up as a data signal. A margin of ±3 volts
should be obtained on the +10 A line in mounting panel 2A. A margin of ±2.5 volts should be
attainable on the +10 8 mounting panel in location 1C. All other mounting panels should be
able to operate properly with both +10 A and +108 lines biased ±4.0 volts. The -15 volt
margin should be approximately + 3 and - 5 volts. It is important that the +10 volt A and B lines
6-11
should not be biased more than ±4 volts (especially on panels 1C and 1 D containing the field
select circuits) and the -15 volt supply line not be increased above -18 volts or damage can
result within the logic.
Refer to the Power Supply and Distribution discussion in Section 2 for an explanation of the
color-coded connector at the right side of each module mounting panel and for the function of
the normal/marginal-check switches at the end of each panel.
During marginal checking,
operating voltages for a mounting panel are supplied to the color-coded connector from either
the computer marginal check panel or from a separate supply and are selected by means of the
toggle switches. To use the computer marginal check voltage to marginal check the parallel
drums, set the +10MC/OFF/-15MC selector switch on the marginal check switch panel to the
desired voltage, and adjust the potential to the nominal level of + 10 or -15 vdc as indicated
on the MARGINAL CHECK voltmeter on the computer marginal-check supply (Type 734
Variable Power Supply). To supply the marginal check voltage from a separate external power
supply I connect the +10 output between the green (+) and black (-) color-coded connector and
connect the -15 vdc marginal check supply between the yellow (-) and black (+) color-coded
connectors. To mate with the color-coded connector, the power supply outputs should be provided with a spade-lug, such as an AMP 42025-1 Power Connector. Terminals of the colorcoded connectors on each mounting panel are wired in common so that the external supply
need be connected only once to check all suppl ies.
Selection of the normal internal power
supply or the external marginal-check power supply is accompl ished by means of the three
normal/marginal-check toggle switches on each mounting panel. These switches select the
source (normal internal or marginal external) of the service voltage suppl ied to terminals A,
B, and C, respectively, of all modules in a panel.
To perform the check:
1. Assure that all of the normal/marginal-check switches on all panels of
the parallel drum are in the down position; then connect the external marginal supply (or suppl ies) to the color-coded connector from either the computer or a separate external supply as described previously.
2.
Energize the external marginal-check power supply and adjust its out-
puts to supply the nominal +10 vdc and -15 vdc.
6-12
3
Set the top normal/marginal sheet switch on the mounting panel to be
checked to the up position.
4. Start operation of the parallel drum in a repetitive program or in a routine
which fully utilizes the circuits in the mounting panel to be tested. The
diagnostic program described in Appendix 1 is excellent for this check.
5. Lower the +10 volt marginal-check power supply output in small increments until normal parallel drum operation is halted. Record the marginalcheck voltage. At this point marginal transistors can be located and replaced
if desired. Return the margina I-check power supply output to the nominal
+ 10 vdc Ieve I .
6. Restart operat ion of the para II el drum program. Then decrease the
+10 volt marginal-check supply output until the parallel drum program halts
again. Again, marginal transistors can be located and replaced. Record
the marginal check voltage and return the bias voltage to the nominal
+ 10 vdc level.
7. Return the top normal/marginal-check switch to the down position.
8. Repeat steps 2 through 7 for the center normal/marginal-check switch
on the mounting panel being checked.
9. Repeat steps 2 through 8 for each mounting pane I to be checked for
positive and negative margins on the + 10 vdc line.
If the -15 vdc service
I ines are to be marginal tested, proceed to step 10, if not proceed to step 11 .
10. Set the bottom normal/marginal-check switch to the up position, restart
the program, and adjust the -15 vdc external marginal-check supply output
until the parallel drum program is halted.
Perform this operation to bias
the -15 vdc I ine first positive and then negative, recording the levels
attained in each direction. Return the lower normal/marginal-check switch
to the down position. Repeat this step for each mounting panel to be checked
for -15 vdc margins.
11. De-energize and disconnect the external marginal-check power supplies.
6-13
CORRECTIVE MAINTENANCE
The Type 23 Parallel Drum system is constructed of highly reliable transistorized modules and
standard circuits.
Use of these circuits and faithful performance of the preventive maintenance
tasks ensure relatively little equipment down time due to failure.
Should a malfunction occur,
the condition should be analyzed and corrected as indicated in the following procedures.
No
special tools or test equipment are required for corrective maintenance other than a broad
bandwidth oscilloscope and a standard multimeter. The best corrective maintenance tool is a
thorough understanding of the physical and electrical characteristics of the system.
Persons
responsible for maintenance should become thoroughly famil iar with the system concept as described in Section 2, specific circuit modules as described in Appendix 2 and the Digital
Modules Catalog, the engineering drawings presented in Appendix 3, and the location of
mechanical and electrical components as described in Section 1 and in the beginning of this
section.
Diagnosis and remedial action for a fault condition are performed in the following phases:
a.
Prel iminary investigation to gather all information and to determine the
physical and electrical security of the drum system.
b. System troubleshooting to locate the fault to within a module through the
use of diagnostic programming, signal tracing, or aggravation techniques.
c. Circuit troubleshooting to locate defective parts within a module.
d. Repairs to replace or correct the cause of a mal function.
e. Val idation test to assure that the fault has been corrected.
f.
Log entry to record pertinent data.
Prel iminary Investigation
It is virtually impossible to outline any specific procedures for locating faults within a complexed digital system such as the parallel drum.
Before commencing troubleshooting procedures,
explore every possible source of information. Ascertain all possible information concerning
any unusual function of the system prior to the fault and all possible program information such
as routine in progress, condition of indicators, etc. Seoich the maintenance log to determine
6-14
if this type of fault has occurred before or if there is any cyclic history of this kind of fault,
and determine how this condition was previously corrected. When the entire drum system fails,
perform a visual inspection to determine the physical and electrical security of all power sources,
cables, connectors, etc. Assure that the power suppl ies are working properly and that there
are no power short circuits by performing the Power Supply Checks as described under Preventive Maintenance.
System Troubleshooting
Do not attempt to troubleshoot the parallel drum system without first gathering all informatio'n
possible concerning the fault, as outlined under Preliminary Investigation.
Commence troubleshooting by performing that operation in which the malfunction was initially
observed, using the same program. Thoroughly check the program for proper control settings,
and note all indicator Iight operations before and at the time of the error. Careful checks
should be made to assure that the drum system is actually at fault before continuing with corrective maintenance procedures. Loose or faulty cable connections can give indications very
similar to those caused by drum malfunction.
equipment are a common source of trouble.
Faulty ground connections between pieces of
From the portion of the program being performed
and the general condition of the controls and indicators, a logical section of the machine at
fault can usually be determined if the parallel drum is not functioning properly.
If the fault has been determined to lie within the Type 23 Parallel Drum, but cannot be localized to a spec ific logic function, perform the diagnostic program procedure. When the location
of the fault has been narrowed to a logic element, continue troubleshooting to locate the defective module or component by means of signal tracing.
If the fault is intermittent, a form of
aggravation tests should be employed to locate the source of the fau It.
Diagnostic Program
The most efficient means of troubleshooting the parallel drum makes use of the parallel drum
diagnostic program tape described in Appendix 1. This routine provides a test of the reading,
writing, or exchange operations of the parallel drum.
Use of this program, combined with the
tV\arginal Checks procedures described under Preventive Maintenance, provides a complete test
of the data transfer operations of the parallel drum.
6-15
A valuable test of playback voltages from the read/write heads can be obtained when running
the diagnostic program. Observe the outputs of the various read/write heads at terminal S of
the appropriate Type 1537 Drum Sense Amplifier module. The output at this terminal provides
a means of mon itoring the actual output vo Itage of the read/head as ampl ified approximately
30-to-33 times. This output voltage at terminal S should appear as a peak-to-peak voltage of
between 1 .4 and 2.0 volts during a read operation. Any large descrepancies from this voltage
indicate that a minor adjustment of the read/head is required as described under Data Head
Spac ing Checks described under Preventive Maintenance.
Another valuable test of playback voltages from the read/write heads can be obtained by running the diagnostic program and performing a marginal check of the +10 A voltage supplied to
mounting panel 2A. This test varies the sl ice level of the Type 1537 Drum Sense Ampl ifier
modules.
If the program runs error free with margins of ±3 volts, no head adjustment should
be attempted.
Failure to obtain a margin of ±3 volts indicates that the heads are not adjusted
properly or slice level may be too low, the sense amplifier is not rejecting noise, and the noise
is being picked up as a data signal.
Under these conditions perform the Drum Sense Ampl ifier
checks spec ified under Preventive Maintenance.
Signal Tracing
If the fault has been located within a functional logic element, program the parallel drum to
repeat some operation in which all functions of that logic element are utilized.
If this test is
to be performed without the use of the computer, control fl ip-flops or register fl ip-flops can be
cleared or set manually by momentarily supplying a ground potential to the appropriate flipflop output terminals. Counting operations of registers can be checked by supplying count
pulses to the register from the output of the variable clock at location 1 F2F and enabling the
c lock by supplying a ground connection to terminal 1 F2V.
If this output is too fast (every 2
to 5 microseconds), slower count pulses can be obtained from the c lock signal at terminal 2B4E
(every 8.5 microseconds) or from the index pulse at location 2B3E (every 35 milliseconds).
Under these conditions, use the oscilloscope to trace signal flow through the suspected logic
element. Oscilloscope sweep may be synchronized with any drum control signal by connecting
the trigger input to the appropriate module terminal on the wiring side (front) of the equipment.
The circuits most likely to encounter difficulty are those sending or receiving signals with the
6-16
PDP-l D or memory control. Trace output signals from the connector back to the origin, and
trace input signals from the connector to its finai destination. The signai tracing method can be
used to determine with absolute certainty the quality of pulse amplitude, duration, and rise
time and the correct timing sequence of this signal.
If an intermittent malfunction occurs, sig-
nal tracing must be combined with an appropriate form of aggravation test.
There are four recorded index tracks and four recorded c lock tracks.
In the event any present Iy
implemented index or clock tracks become destroyed, change the sense amplifier input wires
from the presently implemented read/head to one of the spare heads. Read/write heads 0
through 3 of the pad at location H6 are recorded with an index mark, and heads 4 through 7
at position H6 are recorded with the 4096-bit clock track information.
Aggravation Tests
Intermittent faults should be traced through aggravation techniques.
Intermittent logic mal-
functions are located by performance of the marginal-check procedures as described under
Preventive Maintenance.
If this procedure locates the fault to within a spec ific module, mar-
ginal checking of that specific module alone can be performed as described under Circuit
Troub leshooti ng.
Intermittent failures caused by poor wiring connections can often be revealed by vibrating the
modules while running a repetitive routine, such as the diagnostic program. Often, wiping
the handle of a screwdriver across the back of a suspect row of modules is a useful technique.
By repeatedly starting the program and vibrating fewer and fewer modules, the malfunction can
be localized to within one or two modules. After isolating the malfunction in this manner,
check the seating of the modules in the connector, check the module connector for wear and
misalignment, and check the module wiring for cold solder joints or wiring kinks.
Circuit Troubleshooting
The procedure followed for troubleshooting and correcting the cause of faults within modules
and power supplies depends upon the down time limitations of parallel drum use. Where down
time must be kept at a minimum, it is suggested that a provisioning parts program be adopted
to maintain one spare module or power supply which can be inserted into the cabinet when
System Troubleshooting procedures have traced the fault to a particular component. A I ist of
6-17
modu Ies and power suppl ies can be compil ed from the I ist of drawings presented in Appendix 3
of this manual. Component troubleshooting procedures can be performed within the equipment
as in-line dynamic tests or can be performed at a bench as either static or dynamic tests.
Module Circuits
Circuit schematics of each module are supplied in Appendix 3 of this manual and should be
referred to for detailed circuit information. The basic functions and specifications for standard
modules are presented in the Digital Modules Catalog, A-705, and the functions of modules
pecu I iar to drum systems are described in Appendix 2. The fo Ilowing design considerations
may also be helpful in troubleshooting standard DEC modules.
a.
Forward-biased silicon diodes are used in the same manner as zener
diodes, usually to provide a voltage differential of 0.75 volts.
For instance,
a series string of four diodes is used to produce the - 3 vdc c lamp voltage
used in most modules.
b. The state of DEC fl ip-flops is changed by an incoming pulse which turns
off the conducting transistor ampl ifier. Since fl ip-flops use PNP transistors,
the input pulse must be positive and must be coupled to the base of the transistor.
Flip-flop modules that accept negative pulses to change the state
invert this pulse by means of a normal transistor inverter circuit.
c.
Each Type 1304 and Type 4301 Delay module consists of an input buffer
amplifier which is transformer-coupled to a monostable multivibrator. The
multivibrator output is directly coupled to a level ampl ifier and transformercoupled to an output pulse amplifier.
d. The Type 4604 Pulse Amplifier module contains three independent circuits, each containing a monostable multivibrator and an output pulse ampi ifier. The period of the monostable multivibrator is determined by an RC
time constant which is determined by external connections to the module.
The output from the pulse ampl ifier is determined by the period of the monostable multivibrator and therefore ranges between 0.4 and 1 microsecond.
6-18
e. The Type 1607 Pulse Amplifier module contains three independent pulse
ampl ifiers, each with its own input gating inverter. Output pu ise duration
is determined by the time required to saturate the interstage coupling transformer.
No multivibrators or other RC timing circuits are used in this pulse
amp Iifier.
f. The Type 4519 Drum Field Select module is a 3-state device which
places a field of read/write heads in either the read, write, or deselected
condition.
In the read state the module serves as a 20 mi II iampere current
source for the read/write heads.
In the deselected state the module provides
a +0.5 volt bias for the head selection diode matrix.
In the write state the
module output is at -14 volts and accepte currents from the Type 4518 Drum
NRZ Writer. These three conditions may be observed at terminal W. This
circuit uses silicon control rectifiers to place the output terminal at -14 volts
and accept 1 .75 amperes of write current. With elevated temperatures, it
is possible for the silicon controlled rectifiers to be turned on during a write
state and unable to be deselected after the state has passed. This condition
may be observed by runn ing the diagnostic program, and stopping the program
to monitor the output at terminal W with a voltmeter. An error is indicated
if any output terminal is found at -14 volts which is not selected for the
write state, as indicated by the contents of the write field buffer. This
condition a Iso causes the preampl ifier output voltage at term inal S of the
Type 1537 Drum Sense Amplifier modules to be considerably less than the
normal 1 .4 to 2.0 volt peak-to-peak signal.
In-Line Dynamic Tests
Where down time is not critical, the spare parts list can be reduced and signal tracing techniques can be utilized to troubleshoot modules within the buffer. This practice involves module
removal by means of a Type 1906 System Module Puller, insertion of a Type 1954 System Module Extender into the logic panel, insertion of the suspect module in the module extender, and
oscilloscope signal tracing of the module with the equipment operating in some test routine
which exercises the module.
6-19
In-Line Marginal Tests
Marginal checks of individual modules can be performed within the parallel drum to test specific modules of questionable reliability, or to further localize the cause of an intermittent
failure which has been localized to within one module by the normal marginal checking method.
These checks are performed with the aid of a modified Type 1954 System Module Extender. To
modify an extender for these checks, disconnect the small wire leads from terminals A, B, and
C of the connector block, and solder a 3-foot test lead to each of the three wires. Attach a
spade lug, such as an AMP 42025-1 Power Connector to the end of each test lead, and label
each to correspond to the A, S, or C terminal from which the wire was disconnected. To
marginal check a module within the parallel drum:
1. De-energize the parallel drum.
2. Remove the module to be checked from the module mounting panel,
replace it with the modified extender, and insert the module in the extender.
3. Connect test leads A, B, and C to the appropriate terminals of the colorcoded connector at the end of the mounting panel. The module being checked
can then draw power from the external marginal-check power supply via the
green (+10 vdc) or yellow (-15 vdc) terminals, or from the normal internal
power supplies via the red (+10 vdc) or blue (-15 vdc) terminals.
Note that
the normal/marginal-check switches at the end of the mounting panel should
remain in the down position during the entire procedure.
4. Restore machine power I adjust the marginal-check power supply to provide nominal voltage outputs, and start operation of a routine which fully
utilizes the module being checked.
5.
Increase or decrease the output of the marginal-check power supply unti I
the routine stops, indicating module failure.
Record each bias voltage at
which the module fails. Also record the condition of all operator console
controls and indicators when a failure occurs. This information indicates
the module input conditions at the time of failure and is often essential to
tracing the cause of a fault to a particular component.
6-20
6. Repeat steps 1 and 3 through 5 for each of the three bias vo Itages.
If
margins of ±4 voits on the ±10 vdc supplies, and +3 and -5 volts on the
-15 vdc suppl ies can be obtained without adversely affecting the logic
function of the module, it can be assumed to be operating satisfactorily.
If the module fails before these margins are obtained, use normal signal
tracing techniques within the module to locate the source of the fault.
If a dual-voltage variable power supply is available; perform steps 1 and 2; connect test leads
A, B, and C to either the normal machine power suppl ies at the red (+ 10 vdc) and blue (-15 vdc)
terminals at the end of the module panel or directly to output at this supply; then continue the
procedure from step 4. When using this connector, the ground connectors of the dual-voltage
supply must be connected to buffer signai ground. ihis connection can be made to the black
connector at the end of either module mounting panel.
Stat ic Benc h Tests
Visually inspect the module on both the component side and the printed-wiring side to check
for short circuits in the etched wiring and for damaged components.
If this inspection fails to
reveal the cause of trouble or to confirm a fault condition observed, use the multimeter to
measure resistances.
CAUTION
Do not use the lowest or highest resistance ranges of the mu Itimeter
when checking semiconductor devices. The X10 range is suggested.
Failure to heed this warning may result in damage to components.
Measure the forward and reverse resistances of diodes.
20 ohms forward and more than 1000 ohms reverse.
Diodes should measure approximately
If readings in each direction are the same,
and no parallel paths exist, replace the diodes.
Measure the emitter-collector and emitter-base resistances of transistors. Most catastrophic
failures are caused by short circuits between the collector and the emitter or are caused by an
open circuit in the base-emitter path. A good transistor indicates an open circuit in both
6-21
directions between collector and emitter.
Normally 50 to 100 ohms exist between the emitter
and base or between the collector and the base in the forward direction, and open-circuit
conditions exist in the reverse direction. To determine forward and reverse directions a transistor can be considered as two diodes connected back-to-back.
In this analogy PNP transistors
are considered to have both cathodes connected together to form the base, and both the emitter
and collector assume the function of an anode.
In NPN transistors the base is assumed to be
a common-anode connection, and both the emitter and collector are assumed to be the cathode.
Multimeter polarity must be checked before measuring resistances, since many meters (including the Triplett 630) apply a positive vo Itage to the common lead in the resistance mode. Note
that although incorrect resistance readings are a sure indication that a transistor is defective,
correct readings give no guarantee that the transistor is functioning properly. A more rei iable
indication of diode or transistor malfunction is obtained by using one of the many inexpensive
in-circuit testers commercially available.
Damaged or cold-solder connections can also be located using the multimeter. Set the multimeter to the lowest resistance range and connect it across the suspected connection. Poke at
the wires or components around the connection, or alternately rap the module I ightly on a
wooden surface, and observe the multimeter for open-circuit indications.
Often the response time of the multimeter is too slow to detect the rapid transients produced
by the intermittent connections. Current interruptions of very short durations, caused by an
intermittent connection, can be detected by connecting a 1 .5-volt flashlight battery in series
with a 1500-ohm resistor across the suspected connection. Observe the voltage across the
1500-ohm resistor with an osc i Iloscope wh i Ie probing the connection.
Dynamic Bench Tests
Dynamic bench testing of modules can be performed through the use of special equipment. A
Type 922 Test Power Cable and either a Type 722 or Type 765 Power Supply can be used to
energize a system module. These supplies provide both the +10 vdc and -15 vdc operating
power for the module as well as ground and -3 volt sources which may be used to simulate signal inputs. The signal input potentials can be connected to any terminal normally wired to
receive logic level signals by means of eyelets provided on the power cable. Type 911 Patch
Cords may be used to make these connections between eyelets on the plug.
In this manner
logic operations and voltage measurements can be made throughout the circuit. When using
the Type 765 Bench Power Supply, marginal checks of an individual module can also be obtained.
6-22
Repair
In all soldering and unsoldering operations in the repair and replacement of parts, avoid placing excessive solder or flux on adjacent parts or service lines. When soldering sem iconductor
devices (transistors, crystal diodes, and metallic rectifiers) which may be damaged by heat,
the following special precautions should be taken:
a.
Use a heat sink, such as a pair of pi iers, to grip the lead between the
device and the joint being soldered.
b.
Use a 6-volt soldering iron with an isolation transformer.
Use the
smal iest soidering iron adequate for the work.
c. Perform the soldering operation in the shortest possible time to prevent
damage to the component and delamination of the module etched wiring.
When any part of the equipment is removed for repair and replacement, make sure that all
leads or wires which are unsoldered, or otherwise disconnected, are legibly tagged or marked
for identification with their respective terminals. Replace defective comments on Iy with parts
of equal or greater qual ity or narrower tolerance.
When replacing a Type 4518 Drum NRZ Writer, remove the two wire jumpers near the center
of the component side of the printed wiring board. This operation disconnects 1000 picofarad
capac itors C4 and C5 from the c ircu it and prevents the ir shunting the output to ground.
Val idation Test
Following the replacement of any electrical component in the equipment, a test should be
performed to assure the correction of the fault condition and to make any adjustment of the
timing or signal levels affected by the replacement. This test should be taken from the Preventive Maintenance procedure most appl icable to the portion of the system in which the fault
was found.
For example, if a filter capacitor was replaced in one of the power supplies, the
ripple check for that power supply should be repeated as specified under Power Supply Checks.
Or, if a delay module is repaired or replaced, the Timing Checks should be repeated.
If re-
pairs or replacement are made in an area which is not checked on preventive maintenance, an
appropriate operational test should be devised.
Normally the diagnostic program serves this
purpose if the error was found in a logic element pertaining to data transfer functions.
6-23
If the
fault occurred in the addressing or control elements of the machine, such as a fl ip-flop replacement, the register or control function performed by the flip-flop should be completely
checked by manually setting and clearing or by programmed exercise of that function.
When time permits, it is suggested that the entire preventive maintenance tasks be performed
as a val idation test. The reasons for this are:
a.
If one fault occurred and was corrected, other components may be marginal.
b. While the equipment is down and available, preventive maintenance can
be performed and need not be scheduled again for four months (or the normal
period) .
Log Entry
Corrective maintenance activities are not completed until they are recorded in the maintenance
log. Record all data indicating the symptoms given by the fault, the method of fault detection,
the component at fault, the resu Its of the val idation tests, and any other information which
would be helpful in maintaining the equipment in the future.
6-24
APPENDIX 1
TYPE 23 PARALLEL DRUM DIAGNOSTIC PROGRAM
This program is designed as a diagnostic test of the Type 23 Parallel Drum, and can be obtained
from the DEC Program Library as symbol ic tape DEC-1-137-M*. The program uses the computer
switches as outlined in Table A 1-1.
TABLE A1-1
DIAGNOSTIC PROGRAM SWITCH USAGE
Switch
Function
Test Word 0-5
Select core bank for drum data (bank
"0 II not va lid)
Sense Switch 1
Rejects errors
Tes t Address = 100
S ta rt i ng address for fu II tes t
Test Address = 101
Data list, 4096 words
Test Address = 102
16 channel break system used
The program employs error stops and error printouts in check ing the drum. All error stops ask the
question, "ls a core band selected?" Data errors are_ printed in the following format: memory
address, correct word, error word (in red) ,read_~i_:~_~, drum wor~ count.
For example, (PAR
RD WR X) means a parity error occurred during a drum data exchange, with X indicating the
contents of the DCl when the error was detected. Table A 1-21 ists the error printouts and causes.
TABLE A 1-2
ERROR PRINTOUTS
Printout
Cause
DRA
The DRA instruction failed.
DBA
No sequence break. Instruction DBA or
sequence break system failed.
*The program as described in this appendix was accurate at the time of publ ication. However, programs in the library are continually being revised, so periodic checks should be
made to assure that the most recent program is used in a diagnostic test.
A 1-1
TABLEAl-2 ERROR PRINTOUTS (continued)
Printout
Cause
PAR
Parity error
TIM
Timing error
RD
Reading error
WR
Writing error
Figures Al-l, Al-2, and Al-3 are three flow charts which diagram the test. A program listing for the entire test follows the flow charts.
STARTING ADDRESS
100
A
NO
Figure Al-1
Parallel Drum Type 23 Test
Al-2
SEQUENCE
BREAK
TO HERE
STARTING
ADDRESS 102
B
PRINT
ERROR
Figure
Al-2
Sequence Break
STARTING
ADDRESS 101
C
YES
Figure
Al-3
4096 Word Transfer Starting with Field Zero
A 1-3
DIAGNOSTIC PROGRAM LISTING
/ drum
eem=724074
dzm t1T
dzm cT
dzm cnt
dzm iT
dzm
we
dia=720061
dba=722061
dwc=720062
dcI=720063
dra=722062
define
busy A
cks
rir 1
epi
jrnp A
term
define
bank
lat
and (770000
sza i
hIt
dac e1
term
define
update A
lac A
add (1001
dac A
term
define
error
dra
dio t4
spi
jsp err
term
define
space
e11
tyo
term
define
return
110
tyo
term
(77
Al-4
DIAGNOSTIC PROGRAM LISTING (continued)
define
typred
110 (35
tyo
term
define
black
lio (34
tyo
term
define
movec A,B
lac A
and (7777
sza ""...r...
ior (10000
ema
dae B
term
define
f1eldr
lac 11
add (10000
dac 11
term
define
f1eldw
lac wc
add (10000
dac we
term
/drum -1
100/
ste,
jmp
jmp
lot
iot
iot
lot
lot
11
sta
dzm
110
dio
idx
sas
jrnp
tern
/store jsp in break
(jsp sc2
i tern
tern
56
55
53
/elear break system
/enter seq mode
/clear channels
551
4074 /set ext mode
(100
.-3
Al-5
DIAGNOSTIC PROGRAM LISTING (continued)
sc1"
sc2,
dzm tern
load t~,700000
110 tern
dba
count t2,.
iot 54
lac (flexo dba
return
jda tya
Jmp ste
/no seq break
10t 54
and (7777
sad (30
jmp sc3
dac t"1+
/seq to wro~ channel
lac (flexo seq
return
jda tya
space
law 1 3
add
t4
and (77
jda opt
jmp stc
sc3,
iot 56
dra
dio t4
dra
swap
sas t4
jmp sta
/pr1nt pc storage
/ok if diffirent
return
lac (flexo dra
jda tya
sta,
jmp stc
/dra failed
724074
/enter extend mode
dzm tern
dzm t~
dzm tj
cIa -o.£r elf 7
dae 11
bank
dzm we
dzm ent
/in1t1a11ze pro~ram
Al-6
DIAGNOSTIC PROGRAM LISTING (continued)
st1,
st2,
st3,
jsp cou
stf 6
jsp drm
/load core with counter
/write
error
busy st2
JsP com
fieldw
stf 5
jsp drm
/read n, write n+1
error
busy st3
elf 7
jsp chk
/check core for count
/complement pattern
stf 5
fleldr
stf 4
foo,
st4,
jsp drm
/read n+1
error
busy foe
jsp chk
/check comp count
update cnt
elf 7
law 1
7777
and 11
sas
jmp
cIa
dip
dip
jmp
11,
(370000
st1
wc
11
st1
724074
elf 7
dzm cnt
dzm
dzm 11
bank
jsp cou
/load core with count
stf 6
jsp drm
/wr1te core
we
Al-7
DIAGNOSTIC PROGRAM LISTING (continued)
xk1,
xk3,
xk2,
error
busy xk1
jsp com
elf 6
stf 5
idx wc
/1nc word count
sad (4001
Jmp xk4
jsp drrn
error
busy xk2
jsp chk
jmp xk3
xk4,
dzm
11
1
xk6,
law
dac
jsp
1dx
xk5,
/comp core
/clear write
/set read
/read
/check for errors
/test core locat1on
wc
com
/comp core
cl
and (7777
/test for last
sad (7777
jmp stc
jsp drm
error
busy xk5
lac cnt
sad 1 cnt
jmp xk6
/read 1 word
/test for error
lac (flexo c1
return
jeia tya
lac cl
Jda opt
Jmp xk6
/core error
drm,
dap dr
/d~um subrout1ne
busy drm 1
lac 11
szf 5
ior {400000
swa.p
dia
/drum initial address
lac wc
sz£ 6
/set for write
ior (400000
A 1-8
DIAGNOSTIC PROGRAM LISTING {continued}
dr,
com,
cmi,
crn2,
swap
dwc
110 cl
dcl
Jrop •
/drum word count
dap cm2
/complement core
movec wc,tem
move cl,t2lac 1 t2
cma
dac 1 t2
idx t2
count tern, cmi
jmp •
chk,
dap ck2
/check core
movec wc,tem
move cl,t2
move cnt,t3
cki,
lac 1 t2
szf 4
cma
sas t3
/error rout1ne
JsP er
1dx t2
update t3
count tem,cki
law 7777
and wc
sza 1
Jmp ck2
lac 1 t~
szf 4
cma
sas tj
ck2,
Jmp •
lac (flexo wce
Jda tya
return
Jrnp ck2
cou,
cu,
cu2,
dap cu2
/core counter
movec wc,tem
move cl,t2
move cnt,t3
lac t3
dac 1 t2
1dx t2
update t3
count tem,cu
jmp •
Al-9
DIAGNOSTIC PROGRAM LISTING (continued)
tya"
ta,
err,
o
/type alpha
dap ta
lac tya
repeat 3"rcl 77
tyo
space
jmp •
dap er2
szs 10
jmp er2
return
110
rll
lac
api
Jda
/error pr1nter
/reject errors
t7T
1
(flexo par
tya
/pr1nt par
110 t4
r1l
lac Iflexo tim
spi
jda tya
/prlnt tim
lac
szf
Jda
lac
szf
jda.
(flexo rd
5
tya
~flexo wr
tya
/print read,wrlte
lac t4
and
(77777
er2,
Jda opt
jmp •
/print drum counter , exit
er i
dap ee
/data error printer
szs 10
jmp ee
return
lac t2
jda opt
space
/print mem address
Al-1O
DIAGNOSTIC PROGRAM LISTING (continued)
lac t3
szf 4
cma
jda opt
space
typred
lac 1 t2
Jda opt
space
black
/prlnt correct word
/pr1nt error word
law 1 7777
and 11
ral 77
Jda opt
/pr1nt f1eld
space
ee,
lac wc
jda opt
jmp •
/pr1nt word count
A 1-11
OCTAL PRINTOUT SUBROUTINE LISTING FOR
DIAGNOSTIC PROGRAM
foetal print subroutine -- revised 2 June 62
/unsigned, leading zero elImInatIng.
opt,
o
op1"
opo,
dap
law
dae
stf
szf
tyo
opx
opx,
cIa
reI 3s
d10 opt
sza
elf 1
sza 1
law 20
reI 95
reI 98
1sp op2
Jmp op1
xct opo
jmp •
op2,
o
1 6
op2
1
1 1
110 opt
constants
variables
start 11
A 1-12
Call: number in ac, jda opt
APPENDIX 2
DRUM
MODULES
The Type 23 Parallel Drum employs three types of standard DEC system modules which
are unique to drum systems.
These modules are described here in an effort to present all in-
formation pertinent to the parallel drum within one document.
TYPE 1537 DRUM SENSE AMPLIFIER
The Type 1537 module contains a preampl ifier with a
difference gain of 33, which produces linear ampl ification of drum head playback voltages of 30 millivolts
peak-to-peak to an output voltage of 1 volt peak-topeak.
R
STROBE
The preampl ifier (Q 1 through Q4) precedes a
sl icer (Q5, Q6, Q7) with a variable threshold; the output of the sl icer is used as an enabl ing level for the pu Ise
Figure A2-1
Type 1537 Logic Diagram
amplifier (Q8, Q9) contained in the module. When
the input signal is of sufficient amplitude to produce a binary 1 output from the slicer, a strobe
pulse at the input of the pulse amplifier produces a pulse at the output.
The Type 1537 is suitable for use with return-to-bias techniques within the pulse repetition
frequency range of 50 ki locyc les to 500 ki locyc les.
Controls
A variable resistor controls the slice level, which may be adjusted from O. 1 to 0.4 volts at the
output of the preamplifier .. The preamplifier gain may be varied from 0 to 200 by substituting
an appropriate value of resistance for the lug-mounted 300-ohm 1 per cent resistor. Gain is
inversely proportionate to the value of this feedback resistor.
The nominal input voltage for a selected magnetic head is 30 millivolts peak-to-peak. The
A2-1
difference input impedance is approximately 1800 ohms. The common mode input impedance is
approximah.ly 480 ohms. Thus/if terminals Hand F are connected through diodes to a drum
head which has 1 milliampere bias current applied to its center tap, terminals Hand F will rise
to +4 volts from their quiescent +3.5 volt level. If the input voltage at terminal H is negative
relative to that at terminal F, the circuit detects a binary 1.
The strobe is a DEC standard 70-nanosecond negative pulse. There must be a 200 microsecond
settling time allowed from the selection of the magnetic head to the first strobe pulse.
Output
The output is a DEC standard 70-nanosecond pulse which occurs at the output every time the
input signal meets the input requirement. Each output is capable of driving 16 units of pulse
load.
Terminal M is at ground level when the input exceeds the slice level
Q
The output at terminal
M is capable of driving a DEC Type 1410 or 4410 Pulse Generator when an external 2200-ohm
resistor is returned from terminal M to -15 volts. This function is useful in deriving clock pulses
from a c lock track.
Power
Sources of -15 volts/85 milliamperes, +10 volts (A)/0.2 milliamperes, and +10 volts (B)/20
milliamperes power are required for operation of this module.
TYPE 4518 DRUM NRZ WRITER
The Type 4518 module contains the circuit used to
MAGNETIC HEAD
generate the write pulses in the read/write head of
amagneticdrum.
The circuit can supply a 100 mil-
liampere pulse with a rise time between 0.50 and
FIELD
SELECT ---+----'
CIRCUIT L
o.75 microseconds to a center- tapped record j ng
head
E
of approximately 75 microhenries inductance.
The
H
F
circuit operates in the non-return to zero (NRZ) mode
Figure A2-2
Type 4518 Logic Diagram
A2-2
producing positive-going pulses from -15 volts to ground. A 3-input ground-level AND gate
controls the write pulse generating circuit.
Input
Signal inputs must be DEC standard levels or equivalent. The load is 1 unit of base load shared
among the inputs with -3 volts on them. Each input must be at ground potential or disconnected
to enable the gate and produce output current.
Output
Each output terminal (K and R) is grounded through 120 ohms when the input gate is properly
enabled. When connected to a read/write head whose centertap is a nominal =14 volts, each
output can supply approximately 100 milliamperes of writing current. When the input is disabled, the outputs are returned to -15 volts through 1500 ohms.
The rise time of the output pulse is variable from 0.50 to 0.75 microseconds. The module as
shipped is set for the longer rise time, which minimizes noise in the writing pulse when both
reading and writing occur simultaneously in a parallel drum system. An intermediate rise time
can be obtained by connecting terminals K and L (and terminals P and R) together. This places
a 4700 picofarad capac i tor across the 120 ohm output resi stor • The fastest ri se time requ ires
removing a jumper in each circuit, as well as connecting the output terminals together. This
removes a 1000 picofarad capacitor from the output to ground.
Power
Operating power for the module is -15 volts/35 milliamperes, +10 volts (A)/O.16 milliamperes,
and + 10 vol ts (B)/5. 2 mill iamperes.
TYPE 4519 DRUM FIELD SELECT
The Type 4519 module contains a single drum field select circuit and two ground-level NAND
gates. The drum field select circuit is a 3-state device that provides the mode selection bias
for a group of parallel magnetic drum read/write heads. The two NAND gates are used to
select one of the three stable states of the drum field select circuit.
A2-3
As long as both NAND gates are disabled, the drum
field select circuit is in the nonselected state. When
MONITOR
READ SELECT
READ SELECT
the 2-input read select gate is enabled, the drum
J 0--10""-,
field select circuit is switched to the read select
state and a disabling bias is applied to the write
w
WRITE SELECT
select gate. When the 3-input write select gate is
enabled, the drum field select circuit is switched
WRITE SELECT
MONITOR
(after a 1 microsecond delay) to the write select
state. The output of each NAND gate is avai lable
for monitoring the status of the gate or as a direct
Figure A2-3
Type 4519 Logic Diagram
input of the drum field select circuit.
After the circuit has been switched to the read select state, 200 microseconds must be allowed
to stabilize the reading current before the resulting information from the read/write heads is
available. A reader or sense amplifier, such as the Type 1537, must be used to obtain the information from the read/write heads.
The 1 microsecond delay of the write select gate prevents the drum field select circui t from
being immediately switched to the write select state. This delay allows the selecting circuits
to completely settle into their enabling states. After the circuit is switched to the write select
state, a minimum of 200 microseconds must be allowed before it can be changed to another
state. After it is changed, a drop-out time of 100 microseconds must be allowed for.
Input signals are DEC standard levels or equivalent. Each input must be at ground potential
or disconnected to enable a gate. A single -3 volt level will disable a gate. The load is 1
uni t of base load for eac h gate, shared among any negative i npu ts.
Output
The output can exist in one of the following three stable states:
Nonselected State - When neither NAND gate is enabled, a positive level of 1.0 volt (clamped
by 7 milliamperes internally) is produced at the output, but no current flows in the select bus
1.1
"..
I
I'"
.•
I
I.
and the tleld ot magneTIc neaas
IS
•
I
•
I
nOT seleCTea.
A2-4
Read Select State - When the 2-input gate is enabled, the output terminal is at +4.0 volts and
a positive current of 20 miliiamperes flows from the output. This current is sufficient to connect a field of 20 read/write heads to the read bus, via their selection diodes. When less than
20 heads are used, the output must be loaded with a series resistor and diode to ground. The
value of the resistor is
4000
20-n ohms,
Wheie n is the number of heads used.
Write Select State - When the 3-input gate is enabled, the output terminal is at -14 vol ts and
accepts a current of up to 2.0 amperes of write current from the read/write heads, via their
selection diodes and write circuits (such as the Type 4518 module).
Power
The following power is required for operation of each module:
+ 10 vol ts (A)/O. 16 mill iamperes, +10 vol ts (B)/48 mill iamperes.
A2-5
-15 volts/2.0 amperes max,
APPENDIX 3
ENGINEERING DRAWINGS
TI
DEC
T-41513
CINCH
D4
IN3208
r -____. -__________~~----------~~------~R~E~D~--------~+IOV
_-4~-----,
JONES
0--------...
NO. 141
03
IN3208
TERMINAL STRIP
INPUl'
115V AC
60 N
02
iN320B
BWE-
01
ql'~
iN3208
-+
________ ________ ____________4-____________
__
~
~
~
__________
~
______
~~-15V
BRN
* HEYMAN
NOTE:
IN ORDER TO KEEP OUTPUT VOLTAGE WITHIN
+:0\1: +9.5
TAB
MFG. CO.
TERMINALS
THE FOLLOWING LIMITS'
TO +iiV
- 15 V: - 14.5 TO -16 V
THE LOADING SHOULD BE WITHIN THE FOLLOWING LIMITS·
BOTH SIDES
+ 10 V 0 TO 7.0 AMPS
LOADED
- 15 V 1.0
TO
8.0
AMPS
ONE SIDE
+ 10 V 0
TO
7.5
AMPS
LOADED
-15V 1.0
TO
B.5
AMPS
SUM OF THE OUTPUT CURRENTS ARE LIMITED BY THE FOLLO ..... I NG
EQUATION' 5! 10 + 6115 ~ 53
TRANSISTOR !Ie DIODE CONVERSION CHART
""'~
~
EIA--i~_
If
DEC
+- _
EIA
11
Power Supply RS-728
HOT , - - -
-
BLACK,
''',,{
l
........
'__tl-----lo-Cr
~TI
WHITE
r-----'
I. A
I
~
I_<......~-;..I..
!;t;
;t;:
1------1
'------CR""ED:;-----------+--------,
~14B
o-------~------~------~-------------._------._----+_--~I_<~~~I~
I
14
WHITE
FL 4
p;
l;r FL I '1'1
L _____ ...J
K~
RED
I
FL 5
X:
RED
r-------t
i
'*10
(7)7)7)7f')
t-------(:!.
IIOV
:;r
i ~4£ RED
v v v v ~
FL 6
Xl
L __ ~--...J
r---"- .,
I
I
o-~~----i-------------i-----------=====---~~--_i 1--__#...;./0'----'-1,fOO.. ~
, WHITE
220V
l;r
FL 7 .X,
L ______ J
K4
st~KI
TI...._ _
..1""4'--__---j0 BROWN / WHITE
@]
r-----'
CB3
25 AMPS
:
.......,..-4~,---O'
I;};
1'1
L _____ J
,r-----',
II~II
___________~----------------------~~I~
VYVV~
K,3
o
RED" 10 .
o
I
BLACK
GREEN
------J
' _________y __
JONES TERMINAL ST!"IP
INTJ;:RLOCK
TERMINAL JUNCTIONS
TRANSISTOR !Ie DIODE CONVERSION CHART
DEC
EIA
DEC
I
FL8
XI
L ______ J
UNLESS OTHERWISE INDICATED' WIRE IS** 18
K I IS FAST PULL IN! DELAYED RELEASE
K2 IS DELAYED PULL IN, FAST RELEASE
MI IS AN ELAPSED TIME METER
o
#10
,;r
KI
FL 3
....--.....,..=-14-----0 BROWN/WHIT!
1
l
(IA
1---.
r------t--·-------l~.------~--------
Power Control RS-813
A3-1
AC-DC Wiring PW-D-23-0-8
A3-3
'O"'('~~
AMP
-t IOV
2CJl
FROO VIEW
IOO~~ l
iiiflj
RN
HT
..:L REMOTE POWER "HOOOV
SWITCH FILTER 2.
~
-=
DRUM MOTOR CONTROL
Me
(te
PANEL)
FROO VI EW (f" REM DOllS
813PC
RIll
1IIIIILJ~---'
't
1.. _____ ..I
I
POWER
SWITCH
(1A PANEL)
I
II
1E
II
TO a2B
POWER
WHT
I
RECEPTAeLE~~~~~~~~~s=======~::::::::::~~~
<
TO LOGIC
PANELS
IB,IC,IO,
ITREM
r +10V
IND.
FU SE
-r-
HOLDER LEFT
GNIl
l-15V
FRCNT UNDER
BOTTOM OF CAB
AND AGA
RELAY PIN 1
BAY 2
1F
lACC ESS
)
i FROM FRONT
\OF DEC CABINET
.
SA
RED
)
AGA RELAY
DE B -II'
GNIl
TOPAIUS
L(x;IC {+IOV
lE,IF,IH,1J
-15V
==~~~~~~~~~~~:::::~=~
-=
5)Jfd-40GV
I
I
IOIl.. 160W
ADJ RES ISTOR
I
SLIDER
BLANK
MOTOR
CONN.
I
RES ISTOR
lH
.JISTRIP
_
SET TO SUPPLY 20V
WITH ALL BIMETAL
ACTUATORS ON.
NoOoAIR VANE SWITCH
ON TOP OF DRUM
UNDER TOP COVER
CLOSES AT 1670 RPM
OPE NS AT 1400 RPM
~IIII
TO
BIMETAL
WINDINDS
------
NOTE:
I BIMETAL POWER -=:: 25 OVAC WHEN DRUM
'FIRST REACHES_SPEEE:.
AFTER
200V
2 BIMETAL POWER- 19.5
R
'POWER ON FOON
~ INDICATORS
0
lJ
.a.c
0
lFOTM~~U~6SMINUTES
BLANK
r
~INBLOCK
I
1t{)lcnT~
'OOI\ _ _S~
rOTTQl.l VIEW
i
i
--..r::~
- - - -------AG.-"E'LAy-l
DEB-II
I
-15 PICKUP
.------l-;--l
l
DELAYED
(f"~Ct\B~ltU~_ _ _ _ _ _ _ _ _ _
ON
728
1C
I4
1lOV DC
I
-15V
I
'-7I'F--0
C1
I
I
"I~-~~r---~
I
FAN
I
I
I
I
SIDE VIE1I
I
!
I
I
I
IN WAVE
FIL TER
DRUM PLUG
BOTTOM VIEW
OF AGASTAT
RELAY
I
I
I
L_________________ .JI
I
FR OM
AGA RELA Y
PIN 2
-15V
IN ~r
-+--......,
'0----
r-O D
q
)
)
GND
~'~~~2
~, DI9
D-662
}~~~
"
018
0-662
,,~1~2
"
~
<
RI
<
5%
~,
01
~
< R2
< 1,500
., 5%
< 1,500
02
I
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>R3
<'1.500
< 5%
~. 04
~
<
R4
>1,500
5%
~------4-------~----.---4--
~oo
~I~~O
<
______
5%
~
______
,
~,
I
011
"
~i~lt ~ -j
R6
>'~
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R8
'>'~
4-----~~
______
<
5%
-4~
012
"
~'.'
OJ3
> RII
RIO
~1,500
1,500
<
< 50".
______
~
______
~
5%
<
RI2
< 1,500
< 5%
______-+______
( RI3
<1,500
< 50".
~~
I
< RI4
< 560
< 1/2W
______
4-~~C-15V
UNLESS OTHEWISE INDICATED:
RESISTORS ARE 1/4W; 10%
CAPACITORS ARE
M FP
DIODES ARE 0-664
TRANSISTOR Be DIODE CONVERSION CHART
IA
DEC
D-664
...
IN 6
Clamped Load Resistors RS-1000
~----------------------------------~B+~BI
'------+---.......--...... ---..._--......-------00 0
GND
01
MA90
'-----~-------------~------------~~--------~~---------4------------~--~~~--~~_oC-15V
I
TRANSISTOR III DIODE CONVERSION CHART
I
Ii l;jgE
Three- Bit Parity Circuit RS- 1130
A3-5
r:-- - - - - - - - - - - - - - - . . . . . , - R 9 - - - - - - - - - - - - - - - -.....- - - - - - - - - - - - - - - - - O A + I O \ , I A ;
RI
~OOO
6~OOO
--~t----r-------_i-----~r_----~-----~-~~--~--~r_-----._-_1~D
GND
05
DEC2894-3
C7
150
DI3
D-662
100,000
C6
f"
D5
R7
1,500
5%
DI5
DI4
D-662
47
D2
R6
03
~OOO
RIO
2,200
04
RI2
08
3,300
!I'll.
5%
RI5
820
1/2W
CIO
.0IMFD
~~--------~~--t_--1r--~------~-----------~--+----4-~------OC-15V
UNLESS OTHERWISE INDICATED:
RESISTORS ARE 114W; 10%
CAPACITORS ARE MMFD
DIODES ARE 0-664
CONVERSION CHART
oc
EIA
Delay RS-1304
~
__------------~----~~------~------~~------~------~------~----~---------------------------------f~D~
RI
10,000
R3
330
R4
I
I
I
I
J
K
TRANSISTOR II DIODE CONVERSION CHART
0..005
EIA
DE'
~::e:1
11
~
v
L M
UNLESS OTHERWISE INDICATED:
RESISTORS ARE 112W; 10%
DE 1= TECHNITROL 0.21-' sec DELAY LINE 330 OHMS
TAPPED AT 0.051-' sec. INTERVAL
DE2= DEI' TECHNTROL 0.2 J.I sec. DELAY LINE
DEC
68
1 1 1 1 1 1 1
1111 1
11 !
I
01
0·003
R5
68
.,"
.-
II
I!
Delay Line RS- 1310
A3-6
W
.--_ _ _ _ _- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - o A + I O V {AI
.-----1---~~---------------------------OB+IOV.{B)
~-------~--~-------~------~----------~~~--~------~----~~~----~DGND
R2
4,700
RI5
220
5%
IIZW
L __________________________________--..l-______________
~
____+_--_o C -l'v
UNLESS OTHEWISE INDICATED:
RESISTORS ARE II.. ",; !0%
CAPACITORS ARE MMFD
TRANSISTOR 8t DIODE CONVERSION CHART
DEC
EIA
- e
(
II
,I
z
DEC
EIA
914
Pu Ise Generator RS- 1410
~---------------------------------_oA+IO~AI
~------.-----------~~~--~----------~-----------------_o8+Q~18'
r---4-------------------4-----------------------------------0S·
- PRE AfIP
OUT
• +LEVEL
R4
.---4_ _ _ _~-----------------~MWT
R33
H
D3
R36
0-662
220
112W.5%
L------------+_----~--~+_---~---~-~-~----~--+--t----~--+--~--_t---oD~GND
------~-_o -15V
UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W; 10%
CAPACITORS ARE MMFD
DIODES .ARE 0-001
TRANS!STOR !: D!ODE CONVERS!ON
C
MD9
2NI30!1
R
STROlE IN
CHA~T
A
~
2~'~48~9~~r----+2NI3D!I
Drum Sense Ampl ifier RS-1537
A3-7
r----------------------------------------------------.------------------------------------------~A+~(A)
~------------------------------~------------------------------------------OB+~V(8)
R30
150
:S'lfo I12W
UNLESS OTHERWrSE INDICATED:
~!~l~W~~s
~~~A 10%
?REE
OIOO£S ARE 0 -664
Pulse Amplifier RS-1607
A3-8
Puised Bus Transceiver RS- i665
A3-9
,--__~-----'.---··----1'r--------------1If>-----------------o.....- - - - - - - - - - - - - - - . O C - I S V
~----------------+_----------
__------__
------+__.~--------------------~----------
__
------~----------__oA+lOV~
r-------~------+_~~------+_------+_------+_~r_------._------._----_+--~------_+------_+------------OBHOV~)
L------+--~--------~~~~~--+-_+--_+--------~~~~~----~--~------4_--~--._~~--~E-3V
TRANSiSTOR & DIODE CONVERSION CHART
DEC
DEC2894-1
DE!: 2894 - 2
IA
II
DE
EIA
DEC 21194
. DEC 2894
H
--
Bus Driver RS-1684
r-----------------------------~------------------------------~------------------------------------~A+~,~
r-------------_;--------------~--------------_r--------------~----------------------08+0V(~
t-------r-----~~----~------_.-------+------~------_r------~------4_------+_------_.----._<)o 6ND
+ ell
3.9 MFD
-
lOY
~----_;-------4------_t------~------~------~------;_------+-------+_------~--~--~----~DC-~v
M
v
N
UNLESS
OTHERWISE
INDICATED:
RESISTORS
ARE
114W, 10%
ARE
MMFD
CAPACITORS
Capac i tor- Diode-I nverter RS-4127
A3-11
y
017
C'I
"0
~
...-------------+---------<)A+IOv(A)
0-/
/
D2
J
~
cf
~
0--
KO 03
RIO
68,000
/
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LO 04
~
if
MO 05
~
0--
NO D6
~
CI
.01 MFD
E
013
wO
DI4
XO
DI5
yO
zO
UNLESS OTHERWISE INDICATED:
RESISTORS ARE 114W; 10·.4
"'ODES ARE 0-664 •
~
0--
016
C3
.01
MFD
029
0-662
/
/
.1
.1
.1
.1
.1
012
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if
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0-662
021
0--
022
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030
0-662
C2
01 MFD
D26
/
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d
GNO
027
D-662
R4
12,000
if
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010
TO
/
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09
SO
0--
~
08
RO
D25
D-662
020
D7
PO
~--~--~------OD
Q
023
0-/
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1,500
5%
if
024
RII
560
1/2W
O-~
/
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d
~~Ar~
_____________
4_--------------------~-----~--_oC-15V
TRANSISTOR II< DIODE CONVERSION CHART
0-662
0-864
1N64~
I'
IN3606
JL
Il
Diode Unit RS-4141
r-------~-----~-----~-----~----~------~----~------------~~A+10VIAl
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040
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O~O---+_--~------+_~~----~----------_r----------_r--~----~r_~
UNLESS OTHERWISE INDICATED
RESISTORS ARE 114W, 10 %
DIODES ARE 0- 001
TRANSISTOR lit DIODE CONVERSION CHART
Binary- to- Octo I Decoder RS-4151
A3-12
~
I r-(
::_E~,q, 2C2~0
DI
1
t
f - - - (_ _ _ _ _
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330
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02
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FFID OUTPUT
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330
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330
1500
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1
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TRANSISTORS ARE DEC 2894-4
f
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DEC
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ONE
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DIODES ARE 0-664
~--------------~--------------------------~------~----------6---------------~--~~~------oC-15V
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DEC
DIODE CONVERSION CHART
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Clock RS-440 1
A3-14
OUT
r-------------~~--------------~------~------------~------_;----------------._------~~------_oA+1~{AJ
r---~----+_--------------_+~~--_+--------------~--_.--r_--------------~----~--r_----.__oB+IDV{~
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18,000
18,000
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RI8
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120,000
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120,000
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1,2005%
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2,200
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TRANSISTOR I!c DIODE CONVERSION CHART
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DEC
DEC
0-003
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DE: 2894
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~5~%~~5~%~~_~_ _ _~~V~2~W~,5~%~________.~>_·'5_%__~>~"_5%
_____~_ _ _~~ln~W~,~5~~.________~~5%~~~5~%~_ _ _~_ _ _+-~1I~2_W~,5_%_ _ _~C_15V
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r---~~-1---+-+---~--~~--__1~~-+----'---+-~--~--4-4---~---+-+--~~~~----1-----+---'---~---9~~GNO
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UNLESS OTHERWISE INDICATED
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DIODES ARE 0-664
TRANSISTOR I> DIODE CONVERSION CHART
DEC
2894-1
-
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------------------.-----------------------------------------------------------~----------OB+IOV(BI
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56
r---......- - -.....---oO GNO
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T
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R!3
560
II2W
~------------~--------------------~------------------~~------------------~---------------~~--_o C
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TRANSISTORS ARE DEC 2894-1
DOOES ARE 0-664
-15V
TRANSISTOR It DIODE CONVERSION CHART
tlA
II
2112894
N64&
IN914
II
II
II
"~,,
D£C2894-1
,0-882
: 0-684
EIA
DEC
C2
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o------OT
OUT
02
R 0-----....1--+
IN
S
.T~I~~ ~2~1
TRANSISTOR
a
DEC
EIA
I 8=1\1
IN
cr----.....---..
DEC 2894-1
D9
022
IN
011
019
021
D29
~------------------------~----~------------------------~----~--------------------~--~~C~~
DIODE CONVERSION CHART
DE
OUT
x 0---.....11----+
uo---II*-.......
01
UNLESS OTHERWISE INDICATED
RESISTORS ARE 114 W> 10%
. CAPACITORS ARE MMFD
DIODES ARE 0-664
12,000
cr-----
0 ISA BLE
____________ WR.iTE SA D
DCl 4
ClR DCL
DCL 8
DCl 12
DCl1b
DClB 5
DClB 9
DCLB 13
DCL8 17
I-PE
DCl5
DCl9
DCl 13
DCl 17
6113R
4151
4217
4217
l4'BHO
CLR FLO SEl ------------W'FBH1
DCl 15
PARITY
SEL 1
4b04
DIS.Il.BLE
---------- RE-iD- FfE-ci) -----------SEL 0
4519
4519
4519
I
4519
I
I
nELD SELECT FIELD SELECTi FIELD SELECT FIELD SELECT FIELD SEl[CTI FIELD SELECT FIELD SELECT IFIELD SELECT
30
31
i
32
I
33
34
I
35
3b
I
37
I
:
1684
4519
.
I
READ
\-FD 1
4519
I
,FIELD SELECT kIELD SELECT
I 20
21
PARITY
15-17
4519
I
rtEMJRY
CONTROL
PLUG
13
1810 -) WR10 IB16 -) WR1b __ ~!I~.J?__
----------- ---------WR I 1£ 1b
IB5 -) WR5 1811 -) hRl1 1817 --) WR17
184 -) WR4
WRITE 7
4519
25
__ 2__
I
I
1130
I
FIELD SELECT F I ELO SELECT FIELD SELECT FIELD SElECI FIELD SELECT FIELD SELECT FIELD SELECT FIELD SELECT FIELD SELECTj FIELD SELECT FIELD SELECT FIELD SELECT FIELD SELECT FIELD SELECT FIELD SELECT FIELD SELECT
1
2
3
4
5
b
7
15
lb
17
13
12
14
10
I
11
PAR I TY
•
---- ---
4519
14
b113R
180 -) WRO 18b -) WRb IB12 -) WR12 __ ~J.~
---------- ----------- ------------ 1-111 TE 10
181 -) WRl
187 -) WR7 IS13 -) WR13
_~!~_~_
WRITE 8
b113R
I
bl13R
-hRITE-S-- 183 -) WR3 IB9 -) t-Jl9 IB15 -) WR15 --~ITE-14--------- 1----------- ------------ ------------ -------------------.-
6102R
13
WFB 4
RFB 2
b113R
4151
RF8HO
4217
4217
4217
W::b
helQ
we
W::7
W::ll
he 15
W::8
w::
12
WC 16
w::
13
we
14
RFBHl
WFBH2
--------------
IHl
WFBH3
0-7
RD/\-.R/RQ
DRA RESTART -----------RE.4D PAR ITY
4217
I
\~FB
1
W'F85
RFB 3
RF84
RFBH2
RFBL
RFBH3
0-7
SPARE
WFB3
RFB 1
RF3 5
DRU'4 ERROR
17
Utilization Module List UML-D-23-0-7
(Sheet 2)
A3-21
2
3
4
5
6
7
8
9
10
II
12
13
4401
1684
4604
4127
421S
6113
6102R
6102
4218
4301
4217
4141R
RQ
POWER
CLEAR
IF
o PAR
CLEAR
TRli
CONTROL
RD
RO
SBS RETURN
RQ
i,£ 1NDEX
------------ -------- ----
SPA R E
1
PAR
TRA ER
-> Pel
PULL READ
---------ROB 0
RD PAR
I
WR
WR RS
RQ
-------------ERROR SY!~C
ER SYNC
1310
1304
ClJ'1P' 61
PAR ER
DC 7
----~---- I --~~~-~~~~- 1
~~~2;;~~r~C
DBA SYNC
1~DBA SYNC
1310
6104
1607
4217
4217
IL 6
DC 10
--;:;';;-70ClJ'lP 71
DC 8
4604
ClJ'lP 81
1------------
I
IL 7
18
4217
19
4141
4217
20
21
22
23
4217
4604
6102R
6102R
6102R
b102R
6102
25
24
--[-[("P--90-
DC 9
CO"lP 101
DC 11
C~P 111
----------- -crnp-120-IL 8
DC 12
-----------
DC 13
----------CO"l" 131
I--~~-- -----------I-~~~-~~~--
6102
1000
4604
6102R
' 6102R
6102
__ !~_Q~Qt_ __!~_Qilt_
I CLEAR IB
I
____ 9___
i _!§ __ ~i9t
18 3(0)
18 3(1)
E
3
10
C
Ia 12(0)
ADR ACK
---------- ----------IB 8(0)
4604
!
61 02
L1 02R
bl02R
6102
o
S
A
IJ
IB+OB
I
I
____________ 1
f
i
3
0
4
B
5
IS 17(0)
I
6102
61D2R
B
7
8
I
I
~ ~=-!~~~~
Hl 15(1)
-----------
16
IB 17(1)
17
-----------
6102rl
r
PULSED BUS
I
14
I -------B
15
IS 16(1)
I
6102
9
12
:=n
10
10
I
15
11
I
11
TRANSCEIVE
12
-I
9
I
o -------- i
6
DB OUT
1I127
6
-----------
IS 8(1)
4127
4127
Hl 14(0)
---------_!§_~~i9L
18 16(0)
5
I -------8
6
7
11
L -------E
12
I IB STROBE ~~~~~~~~2~~ ~~~~~~i~2~~ I ~. ~~~~~~~~ j~~~~ig2~
IB 5(8)
18 5(1)
----------- ----------__ ~~_~~91__ __~~_~~~l__
IS 7(8)
18 7(1)
1665
9
::iijm= ::~:mt I [___:___ :~i:;mt
I-----------
I Tlfv£ CHAIN
IH
17
16
4141
-cC;;p-"O
--CO::iP-SO-
TRA DELAY
ACT
ZERO REQ
DC 6
TRA
1- ----- -I------------I-~~~~~-;~~-I-----------
15
RD
PAR RD 0
----------- WRI TE
RFB 1
14
13
14
-------1
DB 161
---08-17'-
j
16
17
!
~------~------~------~------r_----~r_------r_------r_----~------~------~------~------~r_----~------~------~------_+------~------_+------_+------~------~------~------~------~---~
1304
1537
1410
1537
1537
1537
1537
1537
1537
1537
1537
1537
1537
1537
1537
1537
1537
1537
1537
SA 11
SA 12
SA 13
1537
1537
1537
1537
SA 15
SA 16
SA 17
INDEX
28
CLOCK PA
DELAY
CLeeK Sli
INDEX SA
SA PAR
SA 0
SA 1
SA 2
SA 3
SA 4
SA 5
SA 6
SA 7
SA 9
SA 8
SA 10
!
!
,
!
I
I
I
I
I
I
I
l
I
I
j
I
I
I
I
I
I
I
I
Interface and Block Diagram BD-D-23-0-17
A3-23
Timing and Flow Diagram TFD-D-23-0-1
A3-25
7-4
10-4
--+---------.-,-- - . - - , - - - - - - + - - - Del
.
,I
TRA
---------
1.01.15- 3~1n S
(DC=Il ) d ¢ A I - - - - - - - - - - - - - - - - - - - -- -- -------1------- ---------
RQ
.- - - - - - - - - - - - - - - - - - -------+-------ACT lyE
-
-
-----
-
,-- - - -
---------------
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+ .1 .. 9':'5
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Source Exif Data:
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