H 24_serial Drum_Nov65 24 Serial Drum Nov65
H-24_serialDrum_Nov65 H-24_serialDrum_Nov65
User Manual: H-24_serialDrum_Nov65
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H-24
SERIAL.' DRUM
24
t. ..
I NSTRUCTI() N
DIGITAL EQUIPMENT CORPORATIION
MANUAL
•
MAYNARD, MASSACHUSETTS
ICOpy NO.
This manual contains proprietary information. It is provided to the
customers of Digital Equipment Corporation to help them properly
use and maintain DEC equipment. Reveal ing the contents to any
person or organ iza'tion for any other purpose is proh ibited.
Copyright 1965 by Digital Equipment Corporation
ii
CONTENTS
Chapter
Page
IN TR 0 DU CTION . . . . . • . . • . • . . • . • . . . . . • • • . . . • . . • . . . • • • . • • • • . . . . • • . • . • • • .
Functional Description ••••••••.•••••••••••••••••••••••••••••••••••••
1-1
Physical Description •••.••.....•••••...•••..••.••......••.•....•....
1-2
..••.•.••••.•.•••••••••.•.•••••...•.•••..••.•••••
1-3
Abbreviations ......................................................
1-4
Reference Conventions ••••••••••••••••••••••••••••••••••••••••.•••••
1-6
Reference Documents ••••••••••••••••••••••••••••.•••..•.•••••••••.•
1-7
PRINCIPLES OF OPERATION ••••••••••••••••••••••••••••••••••••••••••••
2-1
Recording and Playback Technique. • • • • • • • • • • • • • • • • • • • • • • • . • • • • • • • • • • •
2-1
Drum Format .................................. ••••.••••••••...•
2-2
Specificatiol1S
2
1- 1
CI
•
•
•
•
•
•
Block Diagram Discussion............................. • • • • • • • • • • • • • • • •
2-5
Drum Core location Counter (DCl) • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
2-5
Drum Track Address Register (DTR) ••••••••••••••••••••••••••••••••
2-5
Drum Track Address Decoder (DTD) • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
2-5
Drum Head Se lection •••••.•••••••••••••••••••••••••••••••••••••
2-7
Drum Sense Amplifiers ••.•••••••••••••••••••••••••••••••••••••••
2-7
Drum Control (DCT) ••••••••••••••••••••••••••••••••••••••••••••
2-7
Drum Data Control (DDC) •••••••••••••••••••••••••••••••••••••••
2-7
Drum Final Buffer (DFB) •••••••••••••••••••••••••••••••••••••••••
2-7
Drum Serial Buffer (DSB) ••••••••••••••••••••••••••••••••••••••••
2-8
Read/Write Parity (R/WP) •••••••••••••••••••••••.•••••••••••••••
2-8
Drum Write Cycle ......••..•..••.....•......•..•...•...•.•.•.•....•
2-8
Writing One Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-9
Writing Two Consecutive Sectors •••••••••••••••••••••••••••••••••
2-12
Read CY'cle ••.•.•••.••••••••..••••••••••••••••••.••••••••••••••••••
2-13
Reading One Sector •••••... •••••••••••••••••••.•••••••••••••••••
2-13
Reading Two Consecutive Sectors •••••••••••••••••••••••••••••••••
2-15
Parity Check ............
2-15
I,
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Data Error and Parity Error ••••• ".....................................
2-15
Maintenance Switch Control of PE· DE .............................
2-16
Drum Track Selection Circuits
••
h
•••••••••••••••••••••••••••••••••••••
2-16
Power Supply and Distribution
•
II
•••••••••••••••••••••••••••••••••••••
2-16
,
iii
CONTENTS (continued)
Chapter
2 (cont)
Page
Drum Mechanical Description ••••••••••••••••••••••••••••••••••••••••
2-17
Drum Head Mounting Description •••••••••••••••••••••••••••••• • • •
2-17
Mechan ica I Actuator •••••••••••••••••••••••••••••••••••••••••••
2-18
Analysis of Instructions •••••••••••••••••••••••••••••••••••••••••••••
2-19
3
INTERFACE •••••••
4
INSTALLATION AND OPERATION
0
•••••••••••••••••••••••••••••••••••••••••••••••••••
......................................
Site Requirement:s ••••••••••••••••••••••••••••••••••••••••••••••••••
Signal and Power Connections ••••••••••••••••••••••••••• ':' •••••••••••
Contro Is and Indi cators
Equipment Turnon and Turnoff ••••••••••••••••••••••••••••••••••••••••
5
6
PROGRAMMI NG ••
f)
••••••••••••••••••••••••••••••••••••
'.'
•••••••••••••
4-1
4-1
4-1
4-1
4-3
5-1
Instruction Codes.
5-1
Drum Format and Program Ti mi ng •••••••••••••••••••••••••••••••••••••
5-2
Programming Subroutines ••••••••••••••••••••••••••••••••••••••••••••
5-3
Program Sequence Example A
5-3
Program Sequence Examp Ie B ••••••••••••••••••••••••••••••••••••
5-5
Field Lockout Switches •••••••••••••••••••••••••••••••••••••••••••••
5-7
MAINTENANCE
6-1
Ad iustments •••.' •••••••••••••••••••••••••••••••••••••••••••••••••••
6-1
Timing Checks and Adjustments ••••••••••••••••••••••••••••••••.••
6-1
Drum Sense Amplifier Check and Adjustment •••••••••••••••••••••••
6-1
Drum Head IAounting Adjustments •••••••••••••••••••••••••••••••••
6-2
Pad
Levelin~1
Adjustment ••••••••••••••••••••••••••••••••••••••••
6-3
Marginal Checks •••••••••••••••••••••••••••••••••••••••••••••••••••
6-3
Diagnostics
........................................................
Head Pad Replacement ••••••••••••••••••••••••••••••••••••••••••
7
3-1
ENGINEERING DRAWiNGS •••••••••••••••••••••••••••••••••••••••••••••
Drawing Numbers
..................................................
iv
6-6
6-13
7-1
7-1
CONTENTS (continued)
Chapter
7 (cont)
Page
Circuit Symbols •••••••••••••••••••••••••••••••••••••••••••••••••••
7-1
Logic Signal Symbols ••••••••••••••••••••••••••••••••••••••••••••••
7-2
Coordinate System •••••••••••••••••••••••••••••••••••••••••••••••••
7-2
Module Identification •••••••••
7-2
fI
••••••••••••••••••••••••••••••••••••
Example •••••••••••••••••••••••••••••••••••••••••••••••••••••••••
7-3
TELEPRINTER SUBROUTINES FOR PDP-4 ••••••••••••••••••••••••••••••••••
A 1-1
TELEPRINTER SUBROUTINES FOR PDP-1 ••••••••••••••••••••••••••••••••••
A2-1
Appendix
2
ILLUSTRATIONS
Figure
1-1
Component Locations •••••••••••••••••••••••••••••••••••••••••••••••••••
1-3
2-1
Simplified Timing of NRZ Writing ••••••••••••••••••••••••••••••••••••••••
2-1
2-2
Simplified Logic of Writing Circuits ••••••••••••••••••••••••••••••••••••••
2-2
2-3
Typical Recording and Playback
•••••••••••••••••••••••••••••••••••
2-3
2-4
Drum Surface Format •••••••••••••••••••••••••••••••••••••••••••••••••••
2-4
2-5
Sector Word Format ••••••••••••••••••••••••••••••••••••••••••••••••••••
2-5
2-6
Type 24 Serial Drum Block Diagram ••••••••••••••••••••••••••••••••••••••
2-6
2-7
Write Cyc Ie Tim ing ••••••••••••••••••••••••••••••••••••
2-11
2-8
Read Cycle Timing ••••••••••••••••••••••••••••••••••••••••••••••••••••
2-14
2-9
Drum Head Mounting •••••••••••••••••••••••••••••••••••••••••••••••••••
2-18
2-10
Operating Position of Head Pad •••••.••••••••••••••••••••••••••••••••••••
2-18
6-1
Stop Screw Position ••••••••••••••••••••••••••••••••••••••••••••••••••••
6-2
6-2
Operating Positions of Head Pad •••••••••••••••••••••••••••••••••••••••••
6-4
7-1
7-2
Timin~~
0
•••••••••••••••
....................................................
Typical Digital Logic Block Diagram .....................................
DEC Logic Symbols
7-4
7-6
TABLES
Table
2-1
Analysis of Instructions for Write Cyc Ie ••••••••••••••••••••••.••••••••••••
2-19
2-2
Analysis of Instructions for Read Cycle ••••••••••••••••••••••••••••••••••••
2-21
v
TABLES (continued)
Page
Table
3-1
Inputs to 24 from PDP-4 ••...••.••••••••••••••••.••••••••••••
3·-2
3-2
Outputs from 24 to PDP-4 •••••.••••••••••••••
••••
3-4
3-3
I nputs to Drum -1 Seri es from PDP- 1 •••
3-5
3-4
Outputs from Drum-1 Series to PDP-1 ••
5-1
Type 24 Serial Drum Instruction List (PDP-4) ••.•
5-2
Type 24 Serial Drum Instruction List (PDP-1) •••.•••••••••••••••
5-2
7-1
Semiconductor Substitution •••••••••
ENGINEERING
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DRAWINGS
Drawings
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E-10208
Digital Cable and Component Numbering
BS-D-24604
Drum Core Location Counter
BS-D-24-EFG-0-7
Drum Track Address Register and Decoding (X and Y)
BS-D-24-EFG-0-8
Drum Control (DCT) •
BS-D-24-EFG-0-9
Drum Final Buffer and Data Channel ••••••••••••••
BS-D-24-EFG-0-10
DSB, Control and Parity •
BS-D-24-EFG-0-11
Drum DClta Channel (DDC) ••••••••••••••
BS-D-24-EFG-0-14
Write Field Lock Out Select •••••••••••••
BS-E-24-EFG-0-13
Drum X and Y Select and Drum Heads ••••••••••••
BS-D-24-EFG-0-2
Flow Diagram ....•••••••••••••••••••••
BS-D-24-EFG-0-31
Timing ()iagram ••.••••.••••••••••
PW-D-24-EFG-0-29
Power Wiring •.•.•
WD-D-24-EFG-0-3
Wiring Diagram (Sheet 1) •
WD-D-24-EFG-0-3
Wiring Diagram (Sheet 2) ••.
CD-D-24613
Indicator Cable Breakout and Junction ••••
WL-A-24-EFG-0-12
Field Lock Out Switch Panel (Sheet 1) ••••••
WL-A-24-EFG-0-12
Field Lock Out Switch Panel (Sheet 2) •••
CL-A-24-EFG-0-21
Control Logic to Indicator Panel ••.••••••••••••••••
CL-A-24-EFG-0-22
Drum Track Address to Indicator Panel ••••
CL-A-24-EFG-0-23
Core Location Register to Indicator Panel
CL-A-24-EFG-0-24
Serial Buffer Register to Indicator Panel •
CL-A-24-EFG-0-25
Final Buffer to Indicator Panel ..••
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ENGINEERING DRAWINGS (continued).
Page
Drawing
CL-A-24-EFG-0-26
F3 to Logic Drum Side (Sheet 1) ••••••••••••••••••••••••••••••
7-44
CL-A-24-EFG-0-26
F4 to Logic Drum Side (Sheet 2) ••••••••••••••••••••••••••••••
7-45
CL-A-24-EFG-0-26
Head Sel ection (Sheet 3) ••••••••••••••••••••••••••••••••••••
7-46
CL-A-24-EFG-0-26
Clock Track (Sheet 4) ••••••••••••••••••••••••••••••••••••••
7-47
WL-A-24-EFG-0-27
lOT and 10 Skip, Computer Side ••••••••••••••••••••••••••••.
7-48
CL-A-24-E FG-0-28
Selection Cable ••••••••••••••••••••••••••••••••••••••.••••
7-49
UML-D-24-EFG-0-4
Util ization Modul e List ••••••••••••••••••••••••••••••.••••••
7-51
RS-779
Power Suppl y ••••••••••••••••••••••••••••••••••••••••••••••
7-53
RS-832
Power Control Panel ••••••.•••••••••••••••.•••••••••••••••••
7-53
RS-1011
Diode ................
•••••••••••••••••••••••••••••••••••
7-54
RS-1201
FI ip-Flop ................................................ .
7-54
RS-1304
Delay .•••••••••••••••••••••••••••••••••••••••••••••••••••
7-55
RS-1410
Pulse Generator •••••••••••••••••••••••••••••••••••••••••••
7-55
RS-1537
Drum Sense Ampl ifier ••••.••••••••••••••••••••••••••••••••••
7-56
RS-4102
Inverter
7-56
RS-4105
Inverter
7-57
RS-4110
Diode Unit ••••••••••••••••••••••••••••••••••••••••••••••••
7-57
RS-4112
Diode ................................................... .
7-58
RS-4113
Diode ................................................... .
7-58
RS-4115
Diode ................................................... .
7-59
RS-4127
Capacitor-Diode-Inverter •••••••••••••••••••••••••••••••••••
7-59
RS-4215
4-Bit Counter ••.•••••••••••••••••••••••••••••••••••••.••••
7-60
RS-4216
Quadruple FI ip-Flop .••••.••••••••••••••••.••••••••••.•.•••
7-60
RS-4217
4-Bit Counter •••••••••••••••••••••••••••••••••••••••••••••
7-61
RS-4301
Delay •••••.•••••••••••••••••••••••••••••••••••••.••.••••.
7-61
RS-4303
Integrating One-Shot •••••••••.•••••••••••••••••••••••••••••
7-62
RS-4401
Clock ••••••••••••••••.•••••.••••••••••••••.••••••••.•.•••
7-62
RS-4529
Drum NRZ Writer •••••••••••••••••••••••••••••••••••••••••.
7-63
RS-4530
Drum X Sel ect ••••••••.••••••••••••••••••••••••.••••.••••••
7-63
RS-4531
Drum Y Sel ect •••••••••••••••••••••••••••••••••••••••••••••
7-64
RS-4604
Pulse Amp'ifier ••••••••.••••••••••••••••••••.•••••••...••••
7-64
RS-4606
Pulse Amp'ifier •••••••• ,••••••••••••••••••••••••••••••••••••
7-65
RS-4912
FLIP CHIP Adapter •••••••••••••••••••••••••••••••••••••••••
7-65
vi'i
II
ENG I N EERI NG 0 RAWI NGS (co nti n ued).
Page
prawing
RS-6102
I'nverter .......................•...................•..•.•••••..••.••.•
7-66
RS-6115
Diode
.....................•................•...•......•...•......•..
7-66
IRS-B104
Inverter .....••.........••...••.••.•..•••.....•.•••.••••.•.••••••••.•.
7-67
IRS-W505
Low Voltage Detector .••••••••••.••.•••••.••.••••••••••.•••••••••••••••
7-67
viii
Serial Drum Type 24
ix
CHAPTER 1
INTRODUCTION
The Digital Equipment Corporation (DEC) Type 24 Serial Drum System serves as an auxi liary data storage
device for programmed data processor PDP-1, PDP-4 l and PDP-7. Information in the computer can be
stored (written) in the serial drum and retrieved (read) in blocks of 256 computer words. After programmed
initial ization, 256-word blocks (sectors) of data are transferred automatically between the computer and
the serial drum; transfer of each word is interleaved with the running computer program. Serial drums can
store either 128, 256, or 512 data blocks, providing a memory capabil ity of up to 131,032 computer words.
Each word is transferred between the computer and the serial drum in parallel (18 bits at a time) and is
written or read on the drum surface in seri es.
Since applications of the serial drum are more commcln in a PDP-4 computing system, this manual and the
engineering drawings assume the machine is connected to a PDP-4. When the serial drum is connected to
another computer, all references in this manual to si!~nal origins and destinations and to data interrupt
functions in the PDP-4 can be interpreted to refer to circuits performing simi lar functions.
FUNCTIONAL DESCRIPTION
The basic functions of the Type 24 Serial Drum are d'Jta storage and retrieval, core memory address control, track selection, data request and transfer control, error checking, and power supply distribution.
Under program control, the lOT (input-output transfer) instructions set up the drum control to transfer data.
When the instructions specify the write cycle, a memory start address is set into a register in the serial
drum. The memory address is incremented automatically after each word transfer to the serial drum from
the computer. The track and sector address is also SE3t into a register in the serial drum. The setup instruction initiates a data break cycle to transfer an 18-bit word to the serial drum from the addressed core memory location. A parity bit is generated for each 18-bit word so that a 19-bit word is written on the drum
surface. After the 19-bit word is written, the data break cycle is entered to obtain the next word.
Following the writing of the 256 words of the addressed sector, a flag is set to signify the completion of
the sector transfer. The track and sector address register is incremented by one to simpl ify programming
of continuous sector transfers.
When the program specifies a read cycle, a similar routine sets up the serial drum. The memory start
address is set into the serial drum memory address re~Jister and the track and sector address is set into the
serial drum track and sector address register. After
10
1-,1
word is ~ead from the addressed drum location, the
data break cycle,.is entered to transfer the word to core memory in the computer. When all 256 words of the
addressed sector have been transferred, a flag is set to indicate the completion of the sector transfer.
Error circuits in the serial drum check for parity error during the read cycle and check data transmission
timing errors during both read and write cycles. If bits are picked up or dropped out, if data received from
the computer is late during a write cycle, or if data is late being stored in the core memory during a read
cycle, an error signal is sent to the computer (when sensed by the program).
PHYSICAL DESCRIPTION
The Type 24 Serial Drum System is contained in a DEC computer cabinet 21-5/8 inches wide, 25-3/4 inches
deep, and 67-7/16 inches high. All indicators are located on a panel at the front of the machine. Maintenance controls are located on the plenum door inside the double rear doors. Power and signal cables
enter the cabinet through a port in the bottom. The power cable is permanently wired to the equipment,
and the two signal cables mate with connectors which are mounted on the front of the cabinet, fac ing the
center of the machine. Four casters allow mobil ity of the machine (which weighs 550 pounds). The cabinet
is constructed of a welded steel frame covered with sheet steel. Double front and read doors are held closed
by magnetic latches. A full-width plenum door .provides mounting for the power control, power supply, and
switch panel inside the double rear doors. The plenum door is latched by a spring-loaded pin at the top.
The indicator panel, racks of logic, and cable connector panel are attached to the front of the cabinet.
Module racks are mounted on the front of the cabinet with the wiring side forward, so that modules are
accessible for insertion or extraction by opening the plenum door at the rear. A fan mounted at the bottom
of the cabinet draws cooling air through a dust filter and passes it over the electronic components.
The
memory drum housing is mounted on Ibraces above the fan assembly.
A coordinate system is used to locate racks, modules, cable connectors, and terminals. Each 5-1/4 inch
position on the front of the cabinet is assigned a capital letter, beginning with A at the top, as indicated
on Figure 1-1. Modules are numbered from 1 through 25 from left to right in a rack, as vie~ed from the
wiring side (front). Connectors are numbered from 1 through 6, from left to right as viewed from the front
of the machine. Blank module and connector locations are not numbered. Terminals on a module connector are designated by capital letters from top to bottom. Therefore, D09E is in the fourth location from the
top (D), the ninth module from the left (9), and the fifth terminal (E) from the top of th~ module. Components mounted on the plenum door are not identified by location.
Engineering drawing E-l0208
(Chapter 7) shows the system for locating terminal blocks and standoffs mounted on the logic racks.
1-2
INDICATOR PANEL
TYPE 832
POWER
CONTROL
BLANK
LOGIC 1 C
LOGIC t D
TYPE 779
POWER
SUPPLY
LOGIC tE
SWITCH PANEL
PLUG PANEL
BLANK
BLANK
BLANK
BLANK
BLANK
FRONT VIEW
BACK VIEW
Figure 1-1
Dimensions
Component Locations
23-1/2 inches wide
27-1/16 inches deep
69-1/8 inches high
1-·3
Service Clearances
8-3/4 inches in front
14-7/8 inches in back
Weight
550lbs
Power Required
115v, 60 cps, single phase, 8-amp starting
current, 5-amp running current
Power Dissipation
450 watts
Power Control Po i nt
Local or remote (computer)
Initial Starting Delay
5 min
Signal Cables
2, 50 wire, shielded
Temperature
32 to 105°F operating range
Drum Motor
115v, single phase, 2 pole, induction,
capac itor start and run
Magnetic Head Interference
Maximum interchannel read cross talk at
least 25 db below nominal signal level.
Maximum noise in any channel at least 25 db
below nominal signal level.
Write Current
100 ma
Pulse Repetition Rate
1 .70 J.lsec
Word Transfer Time
66.5 fJsec
Block Transfer Cycle
(1 drum revol ution)
17.3 msec
ABBREVIATIONS
The following abbreviations are used throughout this manual-and on engineering drawings:
AC
Accumulator in computer
ACB
Buffered outputs of accumulator in computer
ACT
Active
AMP
Amplifier
AMPH
Amphenol connector
ANS
Answered
1-4
B
Break (computer state)
COMP
Complement
COND
Conditioned or enabled
DCl
Drum core location counter in serial drum
OCT
Drum control element in serial drum
DOC
Drum data channel in serial drum
DE
Data error
OF and DFB
Drum final buffer in serial drum
DIC
Data interrupt control in computer
ER SYNC
Error sync fl ip-flop
OS
Device selector in computer
DSB
Drum serial buffer in serial drum
DT and DTR
Drum track address register in serial drum
DTD
Drum track address decoder in serial drum
EXT
External
F
As a subscript means final or last bit of
information; the bit after the least significant
data word bit
FL
Field lockout
lOS
Input/output skip facility in computer
lOT
Input/output transfer
MA and MAR
Memory address register in computer
MB
Memory buffer register in computer
PA
Pulse ampl ifier
PAR
Parity
PC
Power control (Type 832)
PE
Parity error
PG
Pulse generator
1·-5
PIC
Program interrupt control in computer
R
Read
RD/WR
Read/write fl ip-flop
RQ
Request flip-flop
R/WP
Read/write parity element in serial drum
S
As a subscript means the first or initial bit
of information; the bit preceding the most
significant data word bit
SA
Sector address
SEC CNT
Sector cou nter
STR ADD
Sector address
TRA
Transfer
WD
Write data fl ip-flop
WRENA
Write enabl e
XA
Most significant octal digit of X address
XB
Least significant octal digit of X address
YA
Most significant octal digit of Y address
YB
Least significant octal digit of Y address
REFERENCE CONVENTIONS
The Digital Equipment Corporation engineering drawing conventions and instruction manual referencing
should be understood at this point. A study of the material contained in Chapter 7 and the following
paragraphs before proceeding with detailed descriptions will save considerable reference time and preserve
thought continuity when reading the text that follows.
Any reference to an illustration by a chapter-oriented figure number indicates that the figure is to be
found in text following the reference. Any reference to an engineering drawing number indicates that
the drawing is to be found in a spec iial drawing section or chapter.
enced first by the full drawing number.
Example: BS-D-24EFG-O-8
1-6
All engineering drawings are refer-
To locate a specific signal or function on a drawing, a system of coordinates is used. As shown on the
drawings of Chapter 7, coordinates are designated by a number and letter. Thus, in any drawing reference,
coordinate location appears immediately after the number separated by a colon.
Example: BS-D-24E FG-0-8:D 1
To avoid needless repetition of the full drawing number, in-text references can use a short designation
form that includes only the difference modifier(s) of 1~he drawing designation plus the coordinates.
Example: -8:D1
One last text reference convention must be noted. Occasionally it is desirable to indicate the condition
of a circuit' within a logic description. As shown on the drawings of Chapter 7, circuit locations are
identified. For reference in text, this designation
i~i
noted; for example, CB24.
If the condition of the
circuit is to be stated, the reference becomes either CB24(1) or CB24(0).
REFERENCE DOCUMENTS
Systems Modules Catalog, C-100
by Digital Equipment Corp.
FLIP CH IP Modules Catalog, C-105
by Digital Equipment Corp.
1--7
CHAPTER
2
PRINCIPLES OF OPERATION
RECORDING AND PLAYBACK TECHNIQUE
The record ing and playback techn ique employed by the Type 24 Serial Drum is NRZ (non-return-to-zero)
phase modulation. This techn ique records binary lis and OIS by controlling the direction of flux change
on the drum surface. For example, a flux change in one direction represents a 1, and a flux change in the
opposite direction represents a O.
BITS TO BE WRITTEN
0A
t--- 1 "I-
"I-
0 -
~850L
-IO~
r
nsee
_______~I
0B
1.7
I
U :
100-1:.
i
nsee
0B DELAYED
I I
--p.see
I
I-!-I
U
U
I
0 _____
-,--
U-
U
U
U
U
Lf
I
I
U--':'-LJ~
I
I
I
0
I
~:u
14- nsee
-I-
I
U
U
U
I
WRITE DATA FLlP- FLOP ---------iL.J~----'
______
DRUM FLUX
I
I
I
~--~
________.
I
~r--l
Figure 2-1
Simpl ified Timing of NRZ Writing
To clarify this point consider the timing diagram Figure 2-1 and the simplified logic diagram Figure 2-2.
As shown on these drawings, a positive voltage swin~J (identified by the arrow) from the write fl ip-flop
produces a flux change to write a 1, and a negative voltage swing produces a flux change in the opposite
direction to write a
o.
The read/write circuits are synchronized so that recording occurs on the phase A
time pulse. The write fl ip-flop must be in a state (reset to write a 0 or set to write a 1) so that the phase A
pulse can complement the fl ip-flop to write the spec ified bit. The phase B pulse shifts the bit to be written
into the last bit of the data register I the DSBO fl ip-flop. The delayed phase B pulse senses the DSBO bit
to put the write fl ip-flop into the proper state so that the next phase A pulse compl ements the write fl ipflop to write the bit specified by DSBO.
Obviously, when the state of the write fl ip-flop is switched by the delayed phase B pulse, it causes a
flux change on the drum surface. This flus change, however, is not sensed (two flux reversals per bit)
because during playback (reading) the drum is sensed for a flux change only at phase A time.
information on the principle of NRZ recording using phase modulation is shown in Figure 2-3.
2-1
Detailed
DSB
DSBO
(SHIFT REGISTER)
SHIFT DIRECTION
DSBt
4
DSB!!
t
o B SHIF"r PULSE
DRUM READ I WRITE HEAD
NRZ
WRITER
DSBO'
WRITE
FF
0B DELAYED
0B DELAYED
o A PULSE
Figure 2-2
Simplified Logic of Writing Circuits
DRUM FORMAT
Data from the computer is written on drum tracks that circumscribe the drum cyl inder as shown in Figure 2-4. The 24 Serial Drum Systems are available with 8, 16, 32, 64, 128, 192, or 256 tracks.
Each data track contains 2 sectors, and each sector contains 256 19-bit words. The 19-bit word consists
of 18 data bits pi us a parity bit (used only in the drum system).
The words within a sector are not stored consecutively on the track; rather, every other word is pecul iar
to the same sector as shown in Figure 2-4. Each word is transferred to the drum serial buffer in approximately 34 jJsec; a sector transfer is completed in approx imately 17.3 msec.
The drum also contains a clock pulse track. The clock pulse track suppl ies clock pulses to the drum control logic at 1 .7-jJsec intervals to synchronize writing and reading of the drum. A 300-jJsec gap, where
no clock pulses exist, separates the beginning and the end of each track.
Figure 2-5 shows a closer view of a typical 19-bit word. The word shown is the first word of the track,
word 1 of sector
o.
The first clock pulse (index pulse) following the 300-jJsec gap does "not write a bit;
it alerts the drum control circuits of the beginning of timing pulses. The next 18 drum clock pulses write
the 18 data bits of the word. After 18 bits are written, an odd parity bit is written; i. e., if the 18 bits
contain an even number of l's, a ptJrity bit of 1 is written to indicate odd parity. To separate words
written on the drum, every 20th drum clock pulse does not write a bit, thereby providing a 3.5-jJsec-gap
2-2
'IME IN
MICROS!CONlS
o
I I I I I I
-t
Ie
12
I I I
24
I I I I I I I I I I
I
,JAM TRANSFER
DSB o
(Example of
__--'1
~-'
0
o
0
o
L
word to be
written)
WRITE DATA
FLIP-FLOP
HEAD
CURRENT
+0
DRUM
SURFACE
FLUX
SATURATE
~'-------\~'-I--(---\-\;------...,~
-0 SATURATE
HEAD VOLTAGE
(Input to Sense
Amplifier at terminals
F and H) AND SENSE
AMPLIFIER SLICE
LEVEL (terminal S)
READ
STROBE
"
SLICE / \ "
~
-t
"=7~V ' V
t
/\
~'
t
t
~
t
t
0
«
ILl
ex:
SENSE AMPLIFIER
LEVEL
(terminal M)
J
SENSE AMPLIFIER
OUTPUT
(t erminal L)
---t
I
~'
DSBs
Figure 2-3
Typical Recording and Playback Timing
2-3
/ \
A
~\
t
t-
300#sl!c
GAP
~
CLOCK
TRACK
DATA TRACKS
AND 1
o
SEC 1
SEC 0
WO 0
WO 0
INDEX
65,536
DATA TRACKS
,76-'77
131072
DATA TRACKS
376-377
DATA TRACKS
776-777
·1
Figure 2-4
Drum Surface Format
between words. There are 20 drum clock pulses per word throughout the entire drum track. This remains
true even though the first clock pulse does not record a bit. The last word written does not contain a gap
and consequently no clock pulse is needed; therefore, it requires only 19 clock pulses. This makes up for
the index pulse so that there are 20 clock pulses per word throughout the drum track.
2-4
r
DRUM CLOCK PULSES
INDEX PULSE
I I I I
BIT WRITTEN
1
I I I
1 1 1.,,1 1 1 1 1 1
t t t 1 t t 1 t t t \-1--1....L-.1
~t~t
...&-t
BIT
I
BIT
2
BIT
3
BIT
4
BIT
5
~
BIT
6
BIT
1
BIT
8
BIT
9
BIT\ \ BIT
10
SECTOFI O. WORD 1
Figure 2-5
11
BIT
18
P
'J ~~--""'."'I.""
GAP
GAP
BIT
I
BIT
2
SECTOR 1
WORD 1
Sector Word Format
BLOCK DIAGRAM DISCUSSION
Major functional elements of the Serial Drum are shown in Figure 2-6. Complete information transfer
flow and timing of operations in the serial drum are indicated in engineering drawings FD-D-24EFG-0-2
and TD-D24EFG-0-31 .
Drum Core locat iron Counter (DCl)
The DCl is shown on engineering drawing BS-D-24604 to be a 16-bit fl ip-flop register which contains the
computer core memory address to or from which the next word is to be transferred. Before transfer of the
initial word in a block, the address of the first word is set into the DCl from the computer accumulator.
As each word is transferred, the DCl is automatically incremented by one.
Drum Track Address Register (DTR)
The DTR is a 9-bit fl ip-flop register which contains 1rhe address of the drum track selected for transfer of
a data block. The least significant bit is the sector address. The drum track (which may be considered
as the data block address in the drum) is set into the serial drum, during program initialization, from the
O
accumulator of the computer. At the completion of a successful block transfer (if the DE • PEO flag is a 0)
the DTR is incremented by one to simpl ify programming of continuous transfers at successive drum tracks.
Engineering drawing BS-D-24EFG-0-7 shows the DTR.
Drum Track Addr,ess Decoder (DTD)
Half of the drum track selection is performed by dec,oding of the DTRfl ip-flop outputs in the DTD. As
shown on engineering drawing -7, the DTD consists ,of two groups of eight 2-input diode gates, one group
for the X address and one for the Y address. The ei~~ht X address outputs function as a 2-digit octal
address which is further decoded in the drum X select logic. The eight Y address outputs serve a similar
function.
2-·5
ACB
FROM
ACCUMULATOR
~
THROUGH ACB
MB6 THROUGH MB
FROM MEMORY
BUFFER REGISTER
I~
~
DRUM CORE
LOCATION COUfHER
(DeL)
DCL
THROUGH DCL 117 _ _ •_
L.. _ _--.;;...;.;;;..a,_...,.;..;.;.;..;..;:;..;;.;;;;.;..;..-~;;..u._:._
DFB ~ THROUGH DFB
17
TO
MEMORY
ADDRESS
REGISTER
t'!'---<11
.
TO MEMORY
. .a.. . BUFFER
REGISTER
...--_ _ _ _ _ _......;V!L..._ _ _ _ _lJ.
..... UNDER CONTROL OF
DATA INTERRUPT
DRUM FINAL
BUFFER
(DFB)
~. DSB 1
6
rN~O~R~~~~
DATA REQUEST ANSWERED.TO
CONTROL
o
DFB
THROUGH
g~k
DFB
DOC
THROUGH
DSBI~
t~o
DRUM SERIAL
BUFFER
(DSS)
""
DSB~ _
READ/WRITE
PARITY
(R/WP)
OVERFLOW
(2)
R PARITY
(2)
WRITE
ENABLE - - - - ,
READ
DATA
~~---_..&(.&-(.-.,
ACB,'o
THROUGH
WRITE DATA
AND
WRITER
ACB"7
FROM
ACCUMULATOR
UJ
READ
... STROBE
READER
(DRUM S.A.)
~
6""
!:;
a:
0
a:
a:
0
a:
0
~
UJ
-
>-
I-
UJ
ir
READ/WRITE
BUSSUS
(2)
DRUM TRACK
ADDRESS
REGISTER
(DTR)
)
TRANSFER
DRUM CONTROL
TO I/O SKIP
PROGRAM
INTERRUPT
AND DATA
COLLECTOR
(OCT)
DT XAO_3
DTXBO_3
DRUM X SELECT
(8)
DRUM
TRACK
ADDRESS
DECODER
(DTD)
l-
r----L.-~--'--__ DONE FL AG
DT7
THROUGH
DTI7
}
~
C(
"J.
0
DTYA _
O 3
DTYB 0-3
(8)
32
.....
a:
a: «
0
UJ Oa:
a: ..J a: «
a: 0 OUJ
UJ
a: ~..J
0
IJJ
«
I- ~ ~o
« 0 «0
0
a.. 1-0
IJJ
DRUM
Y
SELECT
I/)
(
..J
~
a..
~
DIODE
MATRIX
.!!.e
0
0
..J
0
H
I/)
o
«
REMOTE
FROM POWER TURN ON
CONTROL
.
~
~s,...}
-15 VDe
TO
POWER
LOGIC
SUPPLY
~~
AND
-15 VDC Dc:LAYED..... TO
.....- - - - 1... DISTRIBUTION
-20 VDC
TO
- INDICATORS
.....-------I~~WRITER
CLOCK
TRACK
AMPLIFIER
(DRUM SA)
CD
It)
N
a:
o
CD
~
wi
CD
(
CLOCK TRACK'
(2)
DRUM MEMORY
r---~~""-'''''''''
PDP-4
TIME
PULSES
BEGIN
{
~T~7B~__________________________________________~:~
-
Figure 2-6
DRUM DATA
CHANNEL
(DOC)
Type 24 Serial Drum Block Diagram
2-6
SC· SA } BRK_ REQ
REQUEST
}
....
TO DATA
DATA IN
INTERRUPT
....
Drum Head Selection
Final selection of a drum head is performed in the drum X and Y select circuits shown on engineering
drawing BS-E-24EFG-0-13 and in the diode matrix within the drum housing.
Each of the 32 field lockout
switches inhibits the writing on 8 tracks or 4096 words of drum memory.
Drum SensE~ Amplifiers
Two Type 1537 Drum Sense Ampl ifier modules convert information sensed by the magnetic heads of the
drum into digital pulse data.
Information recorded on a clock track is sensed by the clock head and sup-
pi ied to the sense ampl ifier shown on drawing BS-D-24EFG-0-8 as the clock track ampl ifier. The output
from this sense ampl ifier is appl ied to the drum control (OCT) to establ ish the basic clock rate of all drum
operations. The sense ampl ifier shown on drawing BS-D-24EFG-0-l 0 as the READER samples the signals
picked up by the selected data head and produces a pulse to set a 1 into the drum serial buffer (DSB) when
the read strobe signal occurs during the maximum ne~~ative excursion of the head signal.
Drum Control (OCT)
The basic timing pulses for the machine are generated in the OCT from pulses received from the clock track
ampl ifier. The OCT contains the sector counter and sector equal ity logic. The OCT also contains a 4-state
device consisting of four negative diode gates. Each state of this device corresponds with and initiates one
of the four machine control states: idle, transfer, active, or transfer done. This logic is shown on engineering drawing -8.
Drum Data Control (DOC)
Engineering drawing -11 shows the DDC. Circuits within the DDC control the transfer of each word between the computer and the drum serial buffer. The DOC establ ishes the read/write status of the machine,
makes the data break request for a computer break c'ycle, indicates the detection of an errori and designates the direction of the ensuing data transfer.
Drum Final Buffer (DFB)
The DFB is an 18-bit register which serves as a buffer between the computer memory buffer register and
the drum serial buffer. Words are transferred in pamllel (18 bits at a time) under control of the computer
data interrupt control.
During drum writing, the DrB holds the next word.
During drum reading, the
DFB is empty and is prepared to accept information read from the DSB and place it into core memory under
control of the data interrupt control. The logic circ:uits which compose the DFB are shown on engineering
drawing D-24EFG-0-9.
2··7
Drum Serial Buffer (DSB)
As shown on the top and left side of engineering drawing -10, the DSB is an la-bit shift register which is
(I
serial-to-parallel converter during drum reading, and a parallel-to-serial converter during drum writing.
Information is read from the drum into the DSB serially and transferred to the DFB in parallel. During
drum writing, a word is read from the DFB into the DSB and written serially around the drum.
Read/Write Parity (R/VVP)
As each bit of a word is written on the surface of the drum, the R parity flip-flop counts the number of
binary l's and produces a 19th bit to provide odd parity. When data is read from the drum, this fl ip-flop
c::ounts the l's again and sets the parity error fl ip-flop if an even number is detected in anyone word. The
c::ondition of the parity error flip-flop is indicated in the OCT as one of the two possible causes of an error
c::ondition. These circuits are shown on engineering drawing -10:C4,C5.
DRUM WR ITE CYCLE
In general, the DRlCWR instruction (see Table 5-1, Chapter 5) initiates a drum write cycle in the drum
AC (10)
--<>
AC (10)
---+
I
I
INPUTS TO 24 FROM PDP-4
To Serial Drum
Drawing
logic
Function
OTR
-7:C
Provides track address to be strobed
into OTR by lOT 6104 pulse.
0-4-00-01-03
0-4-00-01-04
0-40004-3
DCl
-4:B
Provides initial address of data
transfer into DCl.
Keys
0-4-oo-C1-01
DOC
-1: B1
-11: B1
0-4-00-01-04
0-40004-3
I
Produces DOC CLEAR signal.
Data Request Answered
(Equals Data. B· Tl)
(Data Address => MA)
---+
DIC
0-40004-1
OCl
DOC
OFB
-4:C2
-11:82
-9:01
Produces OCl + 1 signal which increments DCl.
Clears REQUEST (RQ) flip-flop.
Produces OF CLEAR signal in write
mode.
lOT 6002
---+-
OS
0-40004-4
DCl
DOC
DFB
-4:C1
-11: B1
-9:01
Produces DCl CLEAR signal.
Produces ODC CLEAR signal.
Produces OF CLEAR signal.
lOT 6004
----.
OS
0-40004-4
OCl
-4: B1
DOC
-11: B2
OSB
-10:C1
Strobes AC~-17 information into
OCl.
1
Strobes MB into RD/WT, RQ, and
ONG flip- ops.
:roduces TAKE WORD signal if MB12
IS a 1 .
R/WP
OCT
OTR
DOC
-10:C5
-8: B1
-7:Cl
-11:83
lOT 6102
- ---+
-
OS
0-40004-4
1fc
OR to clear par error flip-flop.
OR to set IDLE to 1 .
Produces DT CLEAR signal.
OR to cI ear data error (DE) fli p-flop •
TABLE 3-1
Signal Name
Symbol
---+
lOT 6104
Logic
DS
I NPUTS TO 24 FROM PDP-4 (continued)
From PDP-4
Drawing
D-40004-4
To Serial Drum
Drawing
Logic
OCT
-10:C1
DCT
-10:D3
DCT
-8:C1
DTR
-7:C2
-10:C5
-11: B3
-8:B2
Function
Produces TAKE WORD signal in
write mode.
Produces DSB INITIAL CONDITION
signal in read mode.
Sets transfer request (TRA) to a 1
after 200-J-lsec delay.
Strobes ACB 0-17 information into
1
DTR.
--+
OS
0-40004-4
R/WP
DOC
OCT
--<>
MB
D-4-00-0 1-06
DFB
1
MB12
--<>
MB
0-4-00-01-06
DDC
-11: B2
Controls setting of RO/WR 1, RQ,
and ERROR SYNC flip-flops by
lOT 6004 pulse.
Remote Turnon
Contact
Closure
Power
Control
PSD
None
Energizes drum from computer START
key.
T7B
---+
Timing
DOC
-11 :D3
Produces a T7C pulse which clears
the DFB in the read mode,
MB-+ DFB in the write mode,
and clears the ERROR SYNC flipflop in the DDC.
lOT 6204
OR to clear par error flip-flop.
OR to clear data error (DE) flip-flop
OR to set TRA to a 1 .
W
I
W
1
1
MBO through MB17
I
0-4-00-01-01
I
-9:C
I
Provides data read from core memory
to be written on the drum.
TABLE 3-2
Signal Name
Symbol
OUTPUTS FROM 24 TO PDP-4
From Seri 01 Drum
Drawing
logic
logic
To PDP-4
Drawing
Function
Data In
•
DOC
-11 :C2
DIC
0-40004-1
Indicates the direction of data trCl1Sfers. Data passes into the computer
from the drum when this signal is at -3v
Data Request
•
DOC
-11:C2
DIC
0-40004-1
Indicates the serial drum is ready for
data transfer.
1
1
OCl through OCl
17
2
•
DCl
-4:B
O
•
OCT
-8:03
lOS
0-40004-1
Indicates that no data errors and no
parity errors have occurred when at
the -3v level.
1
1
DFBO through OFB
17
•
DFB
-10: B
MB(DIC)
0-4-00-01-06
Provides data read from drum which is
to be written in core memory.
Transfer Done Flag
•
OCT
-8:A4
105
0-4004-1
Signals completion of a block transfer when reverting to -3v (Nominally
ground level).
DE
O
. PE
MAR(OIC) 0-4-00-01-05
PIC
Holds the core memory address for the
next word to be transferred.
TABLE 3-3
I NPUTS TO DRUM-1 SERIES FROM PDP-1
From
PDP-1
To
Drum
Name
Symbol
- 10
--<>
10
D-20011
DCl
Provides drum with initial core address
10 - 10
16
9
--<>
10
D-20011
DTR
Provides track address to be strobed
into DTR by lOT 0162 pulse
10
--<>
10
D-20011
Sector
Address
DTR
Provides sector address to be jammed
into SA by X162-7 pulse
---+
General
Control
D-20007
DATA
RE Q ANSWERED
(DRA)
TO- HSC BREAK
----+
High speed
channel
D-21303
TP10
--+
10
10
17
17
START CLEAR
i
Function
Produces DDC clear signal
DCl
DDC
DFB
Indexes DCl
Clears REQ
Clears DFB (Write)
General
control
D-2007
DDC
Forms T1 OC during break to strobe
The MB ~DFB (Write)
lOT X161-7
---+
DS
DCl
DDC
DFB
Clears DCl
Produces DDC clear
Clears DFB
lOT X161-10
--+
DS
DCl
DDC
Strobes 10 --;:..DCl
Sets RE Q (Write)
lOT 0162-7
--+
DS
DT
DCT
DSB
DDC
Jams 1017 into sector address
Produces DT clear
Sets idle
Clears parity error
Clears data error
DSB
DSB
DTR
DCT
Produces DSB INI cond
Produces TAKE WORD (Write)
Strobes 10 data into DTR
After 200-llsec delay sets TRA
lOT 0162-10
--+
DS
3-5
TABLE 3-3
I NPUTS TO DRUM-1 SERIES FROM PDP-1 (continued)
Name
lOT 162
lOT 1163
MBO - MB17
MBa
Symbol
!
From
PDP-1
To
Drum
Function
---+
DS
DET
DSB
DDC
Sets TRA
Clears parity error
Clears data error
,.
DS
DSB
DDC
DCT
Clears parity error
Clears data error
Clears flag and set idle
MB
DFB
Provides data from core memory to
be written on drum
MB
DDC
Controls setting of RD/WT FF by
lOT X162-7
Power
Supply
836
Power
control
Enables drum to energize from remote
station
•
•
REMOTE TURN ON
-15v
TABLE 3-4
Name
Symbol
OUTPUTS FROM DRUM-1 SERIES TO PDP-1
From
Drum
To
PDP-l
Function
DATA IN
•
DDC
HSR
Indicates direction of transfer
DATA REQUEST
•
DDC
HSC
Indicates drum is requesting a data
break
DCl
HSC
Indicates memory address of next break
DFB
MB
Provides data read from drum which
is to be wri tten into core memory
DCT
New logic
Sensed by T. lOT 720163, indicates
completion of transfer
DCT
SQ BRK
Indicates completion of transfer
•
DSB
New logic
Sensed by IOT721164, indicatesthe
presence of a parity error on the last
track read
---<>
DCT
New logic
Sensed by lOT 720164
DCL~ -
1
17
DFBl _ 1
o 17
DRUM DONE FLAG
DRUM DONE PULSE
PARI TY ERROR
PEG . DEO
•
•
•
---+
3-6
CHAPTER 4
INSTALLATION AND OPERATION
SITE REQUIREMENTS
The installation site must provide floor space at least 14 inches wide and 28 inches deep to accommodate
the serial drum.
At least 9 inches must be provided in front of the cabinet and 15 inches at the back of
the cabinet to allow opening of the doors for maintencmce.
A source of l'I5v (±17v), 60 cps, single-phase power must be supplied by the site. This source must be
capable of supplying the 8. O-amp starting surge current and 5 .O-amp running current required by the serial
drum.
Ambient temperature at the installation site can vary between 32 and 105° F (0 to 41°C) without deleterious
effect upon equipment operation.
For normal operati()n an ambient temperature range from 70 to 85°F is
recommended.
SIGNAL AND POWER CONNECTIONS
All signal connections from the computer to the Type 24 Serial Drum are made at connectors F3 and F4 on
the plug panel at the front of the mach ine. To mate with these connectors, a cable shou Id contain an
Amphenol connector of the 115-114P series with a HOllsing 1391 and Wire Clamp 3057. Maximum signal
cable length shou Id not exceed 25 ft.
The input and output signals are defined in Tables 3-1 and 3-2 and
their wiring connections are given on sheet A-24EFG-·O-26.
A grounded, 3-wire power cable is permanently attached to the machine. A standard 3-prong male power
plug at the end of this cable allows connection to a power source at least 18 ft from the cabinet.
CONTROLS AND INDICATORS
Toggle switches on the switch panel at the rear of the machine provide all manual control of the serial drum.
The function of these switches is as follows:
MAINT ON/OFF
Allows maintenance personnel to select the normal or stop-on-error
mode of operation. In the OFF position the equipment functions
normally and data errors or parity errors can be detected by the
error flag only at j"he end of a 256-word block. In the ON position detection of data error or parity error by the machine inhibits
generation of clock signals (0 AI Read Strobe, and DB) so that all
data transfer stops and the contents of all regi ste rs can be observed
to locate the cause of the error.
REMOTE ON/OFF/LOCAL ON
Allows local or remote control of machine energization. In
the REMOTE ON position the machine is energized by a contact closure in the computer. The OFF and LOCAL ON positions function as a normal power switch.
FIELD LOCKOUT
(0-37)
Each switch allows a group of 16 consecutive address (4096
words) to be inhibited during writing so that the information
stored on those tracks cannot be acidentally destroyed.
Visual indication of the machine status and register contents is given on the indicator panel. The functions
denoted by these lamps are as follows:
TRACK ADDRESS
(9)
Light to indicate lis in the drum track address register.
CORE LOCATION
( 16)
Light to indicate lis in the drum core location counter.
FI NAL BUFFER
( 18)
Light to indicate lis in the drum final buffer.
SERIAL BUFFER
( 18)
Light to indicate lis in the drum serial buffer.
READY (RD and WR)
(2)
Indicate the machine is in either the read or write mode.
RD READY light indicates that the initial delay following
energization of the power control has elapsed and the machine is ready for use.
TRA
Lights to acknowledge receipt of lOT pulses and indicates
that the machine has been taken out of the idle state and is
waiting for clock pulses to be read from the drum to assure that
the drum is in the correct position before initiating a transfer.
ACT
Lights to indicate that the machine has been taken out of
the transfer state and is actively engaged in a data transfer.
FLAG
Lights to indicate that a block transfer has
and the machine has been taken out of the
machine remains in this state until the flag
the machine is set to either the idle or the
OVERFLOW
Lights to indicate that a 19-bit word has been assembled in
the DSB and is ready for transfer to the DFB in the read mode,
or that a 19-bit word has been transferred from the DSB to the
drum in the write mode.
REQUEST
Lights to indicate that a data request signal has been sent to
the computer to request a data break to transfer a word.
4-2
been completed
active state. The
is cleared when
transfer state.
PE
Lights to indicate that the machine has detected a parity error
after readin from drum to core. If the MAl NT ON/OFF switch
is OFF when a parity error occurs, the drum error flag is set to
1; if the swi'tch is ON, the flag is set to 1 and the transfer is
term i nated •
DE
Lights to indicate that the machine has detected a data error,
in that the data request signal from the drum was not answered
within the b6-!-,sec period required. (When reading a data
word is therefore incorrect in the computer core memory or when
writing the next word to be written has not been received by
the DFB.) Ilf the MAINT ON/OFF switch is OFF when a data
error occurs, the drum error flag is set to 1; if the switch is
ON, the flc::lg is set to 1 and the transfer is terminated. This
condition occurs either because devices with higher priority
are connected to the data interrupt control, or because the instruction being executed at the time of the data request takes
longer than 66 !-,sec for completion.
EQUIPMENT TURNION AND TURNOFF
Operation of the Type 24 can be controlled locally by operation of a switch, or remotely from a signal received from the computer. Control point is selected at the REMOTE ON/OFF/LOCAL ON switch on the
switch panel.
In normal use this switch is left in the REMOTE ON position with the circuit breaker in the
ON position.
For maintenance operations this switc:h is set to the LOCAL ON position to apply power and
to the OFF position to remove power. Power is not controlled by manual operation of the circuit breaker.
Note that the circuit breaker must be in the ON position to allow either local or remote control of primary
power in the serial drum by means of the switch; setting the switch to the REMOTE ON position alone is
not suffic ient for remote operation.
4-3
CHAPTER 5
PROGRAMMING
INSTRUCTilON CODES
The instructions that are used with the serial drum are I isted in Table 5-1 for the PDP-4 and Table 5-2
for the PDP-1. Simi lar instructions are used for the PDP-7 {refer to PDP-7 programming documentation}.
TABLE 5-1
TYPE 24 SERIAL DRUM INSTRUCTION LIST (PDP-4)
Octal
Code
Mnemonic
Code
706006
DRLCRD
Load the drum core location counter with the core memory location
information in acc:umulator bits 2-17. Prepare to read one block of
information from the drum into the specified core location. *
706046
DRLCWR
Load the drum core location counter with the core memory location
information in accumulator bits 2-17. Prepare to write one block
of information int,o the drum from the specified core location. *
Clears all flags.
706101
DRSF
Skip next instruction if the drum transfer done flag is a 1. (The
block transfer is complete.)
706102
DRCF
Clear the drum trclnsfer done flag and the DE ·PE
706106
DRLBLK
Load the drum track address register with the contents of accumulator blIs 10 through 17. Clear the drum transfer done flag, clear
the DE . PEO error flag, and begin a transfer (reading or writing). *
706201
DRSOK
Skip next instruction if the drum transfer done flag is not a 1 .
706204
DRCONT
Clear the drum tmnsfer done flag, clear the DE . PE
and begin a transfer.
Operation
o
o
0
error flag.
0
error flag
*The drum core location counter is incremented afte~r each word transfer and the drum track address
register is advanced to the next position at the end of each block transfer if the drum error flag is not
set to a 1 and the MAl NT ON/OFF switch is in the OFF position.
5-1
TABLE 5-2
Octal
Code
TYPE 24 SERIAL DRUM INSTRUCTION LIST (PDP .. l)
Mnemonic
Code
Operation
721161
DWR
Load core location from I/O bits 2-17 to drum control.
wr ite on drum.
720161
DRD
Load core location from I/O bits 2-17 to drum control. Set mode to
read from drum.
720162
DBL
Load drum track address from I/O bits 9-17 and initiate drum transfer. Clears all flags.
721162
DCN
Cont inue a transfer (do not reset addresses).
720163
DTD
Drum transfer done. Execute the next instruction if the transfer
has not been completed; skip the next instruction if the transfer is
completed.
720164
DSE
Execute the next command if any error flag exists after a transfer
is complete. Skip the next instruction if no error flag exists after
a transfer is compl ete. (Error flags are reset with a drum transfer
begin command).
721164
DSP
Execute the next command if the parity flag is on.
command if the parity flag is off.
Set mode to
Skip the next
DRUM FORMAT AND PROGRAM TIMING
Chapter 2 explained the drum format and showed diagrams of the drum format and word format.
A sector
transfer begins when the continuously rotating drum reaches the index mark, 1.7 fJsec before the beginning
of the data in a selecterl track and sector.
A 300-fJsec interval seporates the end of the last sector from
the beginning of the first sector on each track.
Because the selection of the track read-write read requires 200 fJsec stabil ization time, for continuous
transferring a new trac.k must be specified during the first 100 fJsec of the 300-~sec interval.
If selected
tracks and sectors are consecuti'!e, uninterrupted transferring may be programmed merely by specifying
continuation since the sector and/or track number and core memory location are automatically incremented.
However, if a data timing or parity error occurs, the track and sector number are not advanced and operat ions stop at the concl usion of the sector transfer. Th is feature allows the program to sense for error conditions and to locate the track and sector at which transmission fails.
can be given any time within 200 tJsec after the completion flag is set.
5-2
In general, the continuation command
The drum completion flag is set upon completion of a sector transfer, causing a program interrupt. The
flag is cleared either by a clear flag (DRCF) or automatically when one of two transfer instructions
(DRLBL K, DRCONT) is given.
The error flag, which should be checked at the completion of each transfer, indicates either of the following conditions:
1 '. A parity error has been detected after reading from drum to core memory.
2. The data break request signal from thE~ drum was not answered within the required
66-!-,sec period. This condition occurs either because other devices with higher priority
are connected to the data break facil ity, or because an instruction requiring longer
than 66 !-,sec for compl etion was in progress when the break request was made. Thus,
in reading from the drum, the data word stored in core memory is incorrect; in writing
on the drum, the next word has not been received from the computer.
PROGRAMMING SUBROUTINES
The following program examples indicate the operation of the drum system in multiple sector transfers. The
subroutines are for the PDP-4; however, simi lar routines exist for the PDP-l.
For the PDP-7, in simi lar
routines the LAW instructions are changed to LAC (see PDP-7 programming documentation). The explanation of example A is explained following its listing. Example B is a more sophisticated routine in which
frequent error checks are made; this example wi II not be explained.
Program Sequence Example A
ISUBRounNE TO READ OR WRITE n BLOCKS.
ICORE LOCATION A, DRUM BLOCK LOCATION B.
ICALLING SEQUENCE:
I
I
I
I
LAW A
LAM -n+1
IBLOCK NUMBER
DRUMRD,
o
IREAD ENTRY
DRLCRD
IGIVE READ COMMAND
LAC DRUMRD
ISETUP TO USE COMMON
JMS DRUMRD
lOR DRUMWR
LAW B
DCA DRUMWR
JMP
DRUMWR,
CO~AMON
o
IWRITE ENTRY
5-3
DRLCWR
COMMON,
XCT I DRUMWR
/FETCH BLOCK NUMBER, LOAD
DRLBLK
/BEGIN FIRST BLOCK TRANSFER
ISZ DRUMWR
XCT I DRUMWR
/GET NUMBER OF BLOCKS
DAC TEMP
DRCON,
DRSF
/WAIT TILL TRANSFER IS DONE
JMP DRCON
DRSOK
/CHECK FOR VALID TRANSFER
HLT
/STOP IF NOT GOOD
ISZ TEMP
/INDEX BLOCK NUMBER
JMP .+2
JMP DRDONE
DRCONT
/GIVE CONTINUE FOR MORE BLOCKS
JMP DRCON
DRDONE,
DRCF
ISZ DRUMWR
/ ADVANCE RETURN
JlV\P I DRUMWR
/END OF DRUM READ OR WRITE SUBROUTINE
The LAW A instruction loads the accumulator with the address of the initial core memory location which
contains the first word of the sector transfer. The JMS DRUMWR jumps to the write entry point and deposits the contents of the program counter + 1 (which addresses the LAW B instruction) into the DRUMWR
location.
Note that the accumulator, which contains the core memory address, remains unchanged;
therefore, the next instruction (DRLCWR) can transfer the accumulator contents which contain the core
memory address into the drum core memory address register (DCL register). The next instruction is an
execute instruction (XCT I) indirectly addressed to DRUMWR.
Since the DRUMWR location contains the
cJddress of the LAW B instruction, ,the LAW B instruction is executed, loading the accumulator with the
track address. The DRLBLK is then executed to transfer the accumulator contents, which contain the
track address, into the drum track register and start the sector transfer.
Data transfer begins between the
drum and core memory; data is transferred automatically (without further intervention by the program); each
word transfer takes the word in core memory spec ified by the drum memory address and writes it on the
spec ified track and sector.
Following a word transfer, the drum memory address is incremented so that the
next transfer takes the word from the next sequential memory location.
5-4
The ISZ DRUMWR instruction increments the contents of the DRUMWR location so that the DRUMWR
location contains the address of the next sequential instruction {following LAW B} which is the LAM -n+1
instruction. The LAM -n+ 1 instruction specifies thle number of block transfers in 2 1 s complement form.
The XCT I DRUMWR instruction loads the accumulator with the number of block transfers; the OAC TEMP
stores the number of block transfers into location TEMP.
The DRSF {skip if transfer done} senses the status of the drum FLAG and if the sector transfer is complete,
the program skips to the DRSOK instruction; if not, the program loops back to the DRSF instruction and
continues in this loop until the sector transfer is cOlTlplete.
The ORSOK instruction {skip if no error} senses the error flag for errors occurring during the previous sector
transfer. If an error occurs, the next instruction is executed which halts the program. If no error occurs,
the program skips to the ISZ TEMP instruction.
OIS
ThE~
ISZ TEMP instruction senses the TEMP location for all
which signifies that the block transfer is complete. If not 0, the block transfer is not complete; there-
fore, the TEMP location is incremented and the ne>d instruction (JMP +.2) is performed. The JMP +.2
(jump to this location +2) advances the program to DRCONT which initiates another block {sector} transfer.
The JMP DRCON instruction returns the program bClck to the DRSF instruction to wait till the sector transfer is compl ete.
When the block transfer is complete, the ISZ TEMP instruction senses a 0 in TEMP; consequently, the
next instruction is performed which jumps the progrcJm to DRDONE. The DRCF instruction clears all flags
in the drum. The ISZ DRUMWR instruction increments the DRUMWR location so that it will address the
advance return location. This permits the JMP I DRUMWR to return the program control to the main
program.
Program Sequence Example B
IDRUM SUBROUTINES
IA::::
INITIAL CORE MEMORY ADDRESS
B:::: INITIAL DRUM ADDRESS
lOR LAW (A)
ICALLING SEQUENCE:
LAC (A)
I
I
I
I
JMS DRUMRD OR DRUMWR
I
LAW B
lOR LAC (B)
LAM -n+1
In::::
JMP SUBR
IRETURN TO DRSUB + 1, FOR
IMUL TIPROGRAMMING
JMP ERR
DRLCRO :::: 706006
DRLCWR :::: 706046
5-5
NO. OF BLOCKS TO WRITE
DRLBL K = 706106
DRCONT
DRSF
= 706204
= 706101
DRSOK = 706201
DRCF = 706102
DRUMWR,
o
DRLCWR
/DRUiA WRITE
DAC DRUMTl
LAC DRUMWR
DAC DRUMRD
Jlv\P DR UMCM
DRUMRD,
o
/DRUM READ
DRLCRD
DAC DRUMTl
DRUMCM,
XCT I DRUMRD
DAC DRUMT2
DRLBLK
/ST ART TRANSFER
ISZ DRUMRD
XCT I DRUMRD
/BLOCK COUNTER
DAC DRUMT3
ISZ DRUMDR
LAC I DRUM DR
DAC DRSUB
ISZ DRUMRD
/POINTS TO ERROR RETURN
.JMP DRSUB
DRCON,
DRCONT
ISZ DRUMT2
LAC DRUMTl
ADD DEC IMAL (256 ) OCTAL
DAC DRUMTl
DRSUB,
o
DRSF
IMP .-1
[lRSOI<
JMP DREXIT
ISZ DRUMT3
5-6
JMP DRCON
ISZ DRUMRD
DREXIT ,
DRCF
JMP I DRUMRD
DRUMT1,
o
/CURRENT CORE ADDRESS
DRUMT2,
o
o
/DRUM ADDRESS
DRUMT3,
/COUNTER
START
FIELD LOCKOUT SWITCHES
The programmer should be aware of the settings of the FIELD LOC KOUT switches to avoid attempting to
write at track addresses which are inhibited by switches in the up position. The octal addresses inhibited
by each switch are as follows:
Switch
Addresses
Switch
Addresses
0
0000 to 0017
20
0400 to 0417
0020 to 0037
21
0420 to 0437
2
0040 to 0057
22
0440 to 0457
3
0060 to 0077
23
0460 to 0477
4
01 00 to 0117
24
0500 to 0517
5
0120 to 0137
25
0520 to 0537
6
1040 to 0157
26
0540 to 0557
7
0160 to 0177
27
0560 to 0577
10
0200 to 0217
30
0600 to 0617
n
0220 to 0237
31
0620 to 0637
12
0240 to 0257
32
0640 to 0657
13
0260 to 0277
33
0660 to 0677
14
0300 to 0317
34
0700 to 0717
15
0320 to 0337
35
0720 to 0737
16
0340 to 0357
36
0740 to 0757
17
0360 to 0377
37
0760 to 0777
5-7
CHAF'TER 6
MAINTENANCE
The maintenance techniques for the serial drum consiist of the normal maintenance and troubleshooting techniques employed on digital equipment; these techniques include visual inspections, cleaning air fi Iters,
fault isolation, etc.
Any techniques peculiar to the 24 Serial Drum are described in this chapter.
ADJUSTMENTS
Timing Checks and Adjustments
Using the osci Iloscope and referring to engineering drawing -8, check the timing of the Type 4303 Integrating Single Shot at location 1 C9, and the Type 1:304 Delay at location 1 D24.
If necessary, adjust the
timing of these modules by turning the potentiometer screw which is accessible through a hole in the handle.
Check the single-shot by observing the 1 output at lC9W while triggering the oscilloscope on 1C9K.
Dur-
ing each revolution of the drum the sing Ie shot i s tri!~gered every 1 .7 jJsec for approximately 17 msec during
data reading and receives no pulses during the 300-~lsec gap. The output at terminal 1C9W shou Id be at
ground level during the gap, drop to - 3v at the first triggering pu Ise, and remai n at - 3v unti I 3.4 jJsec
after the last triggering pulse is received before revE~rting to ground potential.
Check the timing of the 1304 Delay module (1 D24) by observing the negative read strobe pulse at terminal
1 D24E while triggering the oscilloscope on the lOA pulse. Read strobe pulses should follow lOA pulses by
approximately 0.3 jJsec. Observe t'he read strobe pulses and the amplified output of a magnetic read head
by connecting the second input of the dual-trace oscilloscope to terminal 1E24S. It is important that the
read strobe pulses occur at the negative peak of the sinusoidal read signal. Measurements should be made
using several different head outputs, and the read strobe pulse should be adjusted for an average of the
measurement's to el im inate large di fferences in peak playback time.
Drum Sense Amplifier Check and Adjustment
The Type 1537 Drum Sense Amplifier modules at loc(ltions 1 E25 (clock track) and 1 E24 (data track) are
checked for proper slice or threshold level at terminl:::!1 S. This measurement can be made with the oscilloscope by measuring the amount the base line shifts above ground when the signal is connected to the input.
The clock track sense amplifier slice level should be +100 mv. The data track sense amplifier slice level
should be +150 mv. Adjustment of the slice level c(m be achieved by turning the potentiometer screw
which is accessible through a hole in the module handle.
6-1
l)rum Head Mounti ng Ad justments
Adjustment of the magnetic heads is provided by the stop screw for each pad of heads and its actuating arm,
as shown in Figure 6-1 .
Figure 6-1
Stop Screw Position
With this stop screw properly positioned, the actuating arm moves the pad to a position where the read is
sl ightly bent and the pad is tangent to the drum surface at the Iine of head gap.
These ad justments are made
Cit the factory and ordinari Iy need no't be changed, at least no more than a minor adjustment.
should adjustment be necessary, proceed as follows:
1. Connect an osc i lIoscope to 1 E25S to observe the preampl i fi er output for the drum
head in question.
6-2
However,
2.
Set the DTA to address the drum head in question.
Engineering drawing -13 shows
the bar and pad location and the octal address of each drum head.
3" Set the drum control status to read.
4. Using a 5/64 hexagonal for socket heClds, adjust the stop screws unti I a maximum
output is noted on the osci Iloscope as shown in Figure 6-2. The adjustment screw is
located on the right side of each bar viewing the drum as shown in Figure 6-1 .
CAUTION
If head adjustment is attempted with diode boards in place, make sure that
the adjustment wrench is placed, and/or insulated to prevent shorting connections or components to ground.
The best method of making this check is to run a program in which the patterns of all OIS, all lis, or alternate lis and OIS are written on the selected track, then read the data and monitor the output of the
selected track.
If data on the selected track is to be retained, it should be read into core memory before
proceeding with this adjustment. Rewrite the selec:ted track and read the recorded signal after every
ad justment.
Pad Level ing Adjustment
The amplitude of head playback signals among the eight heads in each pad is set as uniformly as possible
by using the pad leveling screws which are accessible at the outer surface of each bar, roughly adjacent
to the upper and lower edges of each pad. This mClY be checked on heads 1 and 8 (top and bottom heads)
with secondary reference to heads 2 and 7 .. Clockwise rotation of a pad leveling screw tends to increase
signal amplitude at that end of the pad. Continuously write and read the selected heads, always alternating
between the two.
MARGINAL CHECKS
Marginal checks are performed to aggravate borderline conditions within the logic to reveal observable
faults. The checks are performed by operating the equipment logic circuits from an external, adjustable
power source, such as the DEC Type 734 Variable Power Supply. (See Chapter 2, Power Supply and Distributions for descriptions of marginal check terminals and switches.)
6-3
J{A"
~
~
1. HEAD PAD RETRACTED
~nlllP)
...
~.
CENTER OF INITIAL
~~ HYDRODYNAMIC
\\~\\\ ,\\\"\\~,,,\,,\-
FILM
.
__~_
i
I
~~ I ,
:
--
I
_--L --
I
2. HEADS APPROACHING ROTATING DRUM
HEAD GAP TANGENT,
MAXIMUM SIGNAL
AMPLrrUDE
3. OPERATING POSITION
I
'
- - l--_. -,
i
!
\
~~~" ,:\\~
CENTER OF FILM
HEAD GAP NO LONGEH TANGENT,
SIGNAL AMPLITUDE REDUCED
4. ADJUST STOP BACKED OFF TOO FAR
Figure 6-2
Operating Positions of Head Pad
6-4
'
-
-~
Raising the bias voltage above +10 is equivalent to lowering the amount of base drive on a particular
transistor. This in turn simulates a lower gain driving transistor. Raising the bias voltage thus tends to
indicate low gain transistors.
Lowering the bias vcdtage below +10v simulates a condition where the vol-
tage drop across the previous driving transistor (V CE) has increased; this tends to indicate high V CE drop
(leakage) transistors or low gain driving transistors. The -15v supply margins are not checked in the serial
drum because raising or lowering the -15v does nol' affect the majority of control logic, since it is the
collector load voltage and is usually clamped to -3v. The +10v margin should be about ±5v.*
By recording the level of bias voltage at which circuits fail, progressive deterioration can be plotted and
expected fai lure dates predicted. Therefore, these~ checks provide a means of planned replacement. Marginal checks of the +10 (A) supply (top switch at the left of the rack) to rack E varies the slice level on
the drum sense amplifier modules and so is a valuable tool in verifying the capability of the machine to
read and write on the drum surface.
Normally increasing the + 10 (A) supply by 5 or 6v also increases the
slice level and causes bits to be dropped out.
Decreasing the +10 (A) source by 5 or 6v usually lowers the
slice level and causes bits to be picked up.
To perform marginal checks, proceed as follows:
1. Connect the external marginal-check power supply to the colored connector on any
rack between the green (+) and the black (ground) terminal.
2. Energize the marginal-check power supply and adjust the outputs to supply the nominal
+10 vdc.
3 . Start equipment operation in a repetitive pattern or in a routine which fully utilizes
the circuits in the rack to be tested.
4. Set the top switch on the rack to be clhecked to the up position.
5. Lower the +10v marginal-check power supply until normal system operation is interrupted. Record the marginal-check voltage. At this point marginal transistors can
be located and replaced.
6, Start equ ipment operation. Then decrease the + 1Ov marg inal-check supply unti I
normal operation is interrupted, at which point record the marginal-check voltage.
Transistors can again be replaced.
*The 1537 Sense Amplifier, 1C1 and lE25, has only ±2v margins on +10B.
6-5
7.
Stop operation and return the top switch to the down position.
8. Repeat steps 2 through 7 for the center switch on the logic rack being checked.
9. Repeat steps 2 through 8 for each rack of logic to be checked.
10. De-energize and/or disconnect the external marginal-check power supply.
DIAGNOSTICS
Tlhe diagnostic program is a test procedure designed to check the basic control functions performed by the
mach ine and to determ i ne the rei iabil ity of recording on various tracks.
Speci fically the program performs
the following:
1. Writing and checking of any desired pattern on the entire drum, writing one track
at a time.
2. Writing and checking of specific patterns on the entire drum, writing one track at a
time.
3. Writing and checking of ramdon numbers over the entire drum, writing four tracks at
a time.
Prepare a perforated tape or other vehic Ie for loading the following program into the computer.
24/
WRA
= 2000
RDA = 4000
BEGI N,
LAC DLNGTH
CMA
ADD (1)
DAC DLOOP1 +3
DAC DWRITE+1
ADD (3)
DAC D3A
DO,
LAS
SMA
JMP D1
HL.T
6-6
LAS
JMS DLOOP1
JMP DO
D1,
LAM TB-TBE
DAC T2
LAW TB-1
DAC 17
D2,
LAC I 17
JMS DLOOP1
ISZ T2
JMP D2
D3,
/TEST RANDOM 2000 WD PATTERNS
LAC (736425)
DAC RNK
LAC (NOP)
DAC DRSUB+4
D3A,
/MODIFIED, -DLNGTH+4
LAM
DCA Tl
DZM DK1
D4,
LAM -17777
DAC T2
LAW WRA-1
DAC10
D5,
JMSRN
OAC I 10
ISZ T2
JMP 05
06,
LAC (WRA)
JMS ORUMWR
LAC OK1
LAM -3
JMP ORSUB+1
.JMP WZE
07,
JMS OCMP
LAM -3
LAM -1777
ISZ OK1
6-7
I SZ 11
JMP 04
JMP D3A
DCMP,
/COMPARE READ AREA AGAI NST WRITE AREA
0
LAC (RDA)
JMS DRUMRD
LAC DKl
XCT I DCMP
JMP DRSUB+l
JMP .+1
ISZ DCMP
XCT I DCMP
DAC DCTl
LAC (LAC WRA-l)
DAC10
LAC (LAC RDA-l)
DAC 11
DCMP2,
LAC I 10
SAD I 11
JMP .+2
JMS DCMPE
ISZ DCT1
JMP DCMP2
ISZ DCMP
JMP I DCMP
Dell,
0
DK1,
0
DK2,
0
DK3,
0
DCMPE,
0
/TYPE OUT DRUM ERROR
TIN
LAC DKl
DAC DK2
/CHANNEL NO.
LAC (LAC RDA)
CMA
ADD 11
6-8
DCMPE1,
ADD (DECIMAl., 255 OCTAL)
SPA
JMP DCMPE2
ADD (-1)
ISZ DK2
JMP DCMPE1
DCMPE2,
ADD (DECIMAL, 255 OCTAL)
SPA
CMA
DAC DK3
/WORD NO.
LAC DK2
/TRACK t-.JUMBER
TWORDZ
6
TAB
LAC DK3
/WORD NUMBER
TV/ORDZ
6
TAB
XCT 10
/WORD WRITTEN
TWORD
6
TSP
XCT 11
/WORD READ
TWORD
6
JMP I DCMPE
DLOOP1,
0
/DO WRITING AND CHECKING
JMS DSPRD
JMS DWRITE
LAM
/MODIFIED, -DLNGTH+1
DAC T1
DZM WRA
DZM DKl
DLOOP2,
JMS DCMP
LAM
LAM DECIMAL, 255 OCTAL
6-9
ISZ DKl
ISZ WRA
ISZ Tl
JMP DLOOP2
JMP I DLOOPl
Tl,
T2,
DSPRD,
o
o
o
/SPREADS 256 WORDS IN WRA
DAC DSPRDA
LAM DECIMAL, 255 OCTAL
DAC DSPRDC
LAW WRA-l
DAC 10
LAC DSPRDA
DAC I 10
ISZ DSPRDC
JMP .-2
DZM WRA
DZM DK1
JMP I DSPRD
DSPRDC,
o
DSPRDA,
o
DWRITE,
o
/WRITES ALL CHANNELS
LAM
/MODIFIED, -DLNGTH+l
DAC DWC
LAC (JMP DREXI T)
DAC DRSUB+4
DW1,
LAC (WRA)
JMS DRUMWR
LAC DK1
LAM
JMP DRSUB+1
JMS WZE
ISZ WRA
ISZ DK1
ISZ DWC
6-10
DCMPE1,
ADD (DECIMAL, 255 OCTAL)
SPA
JMP DCMPE2
ADD (-1)
ISZ DK2
JMP DCMPE1
DCMPE2,
ADD (DECIMAL, 2'55 OCTAL)
SPA
CMA
DAC DK3
/WORD NO.
LAC DK2
/TRACK NUMBER
TWORDZ
6
TAB
/WORD NUMBER
LAC DK3
TWORDZ
6
TAB
XCT10
/WORD WRITTEN
TWORD
6
TSP
XCT 11
/WORD READ
TWORD
6
JMP I DCMPE
DLOOP1,
0
/DO WRITING AND CHECKING
JMS DSPRD
JMS DWRITE
LAM
/MODIFIED, -DLNGTH+1
DAC Tl
DZM WRA
DZM DK1
DLOOP2,
JMS DCMP
LAM
LAM DECIMAL, 255 OCTAL
6-9
ISZ DKl
ISZ WRA
ISZ Tl
.JMP DLOOP2
.JMP I DLOOPl
Tl,
T2,
DSPRD,
o
o
o
/SPREADS 256 WORDS IN WRA
DAC DSPRDA
LAM DECIMAL, 255 OCTAL
DAC DSPRDC
LAW WRA-l
DAC 10
LAC DSPRDA
DAC I 10
ISZ DSPRDC
JMP .-2
DZM WRA
DZM DKl
JMP I DSPRD
DSPRDC,
DSPRDA,
DWRITE,
o
o
o
/WRITES ALL CHANNELS
LAM
/MODIFIED, -DLNGTH+l
DAC DWC
LAC (J MP DREXI T)
DAC DRSUB+4
DW1,
LAC (WRA)
JMS DRUMWR
LAC DKl
LAM
JMP DRSUB+l
JMS WZE
ISZ WRA
ISZ DKl
ISZ DWC
6-10
JMP DWl
JMP I DWRITE
DWC,
RN,
o
o
/RANDOM NUMBER GENERATOR
lAC RNK
Cll V RAR
SZl
XOR (400000)
XOR (335671)
ADD (335671)
DAC RNK
JMPIRN
RNK,
o
WZE,
o
/WORKING NUMBER
TIN
LAC DKl
TWORDZ
6
TSP
LAC (FLEX WRE)
TY3
JMP I WZE
TB,
o
777777
525252
252525
666666
TBE,
111111
DlNGTH,
400
/256 TRACKS DECIMAL
START
This program assumes that DEC Readin Mode loader program and standard teleprinter subroutines are stored
in core memory.
If the subroutines are not in the computer, prepare routines as listed in Appendix 1, or
equivalent, and load them into the computer.
6-11
To use this program set the ADDRESS switches to 7770, load the tape in the reader, and depress the START
key. When the program is in the computer press the STOP key, set the ADDRESS switches to 24, then
press the START key.
!hase a - If bit 0 of the ACCUMULATOR switches is a 1, the program will halt.
Put the pattern desired
to be written on the drum in the ACCUMULATOR switches and press CONTI NUE. The pattern will be
written on all tracks and checked.
Note that during this phase and during phase b below, the first word
wri tten on each track is the track number.
After the entire drum (tracks 0-127
or 0-255 ) has been checked, the program will continue with
10
10
phase b unless bit 0 of the ACCUMULATOR switches is a 1, in which case the machine will halt again
and the entire process can be repeated. The switches can be changed any time after CONTINUE is pressed"
If bit 0 of the ACCUMULATOR switches is a 0 when starting the program, phase b will begin immediately.
!hase b - During this phase the following patterns are written and checked over the entire drum, writing
one track at a time:
000000
777777
525252
666666
111111
(The fi rst word on each track wi II bE! the track number)
Phase c - When phase b is completed, the program wi II generate pseudo-random numbers and write and
check the enti re drum wri ti ng and reading, four tracks at a time (i . e. 0-3, 1-4, 2-5, 3-6 etc. through
124-127
10
or 252-255
10
), This phase will continue indefinitely until the machine is stopped.
If information is misread from the drum, the following typical message wi II be typed, and the program wi II
continue checking the next channel:
000100
000236
525252
525250
Where: word one = the track number (octal 0-255)
word two = word number (octal 0-377)
word three
= the
word wri tten on the drum
word four = the word read from the drum (in this example bit 16 was dropped)
6-12
If an error occurs during writing, the message 000100 WRE will be typed, indicating a write error on track
100 (octal). The program will continue; however, if this error occurs during phase c, start the program
over manually.
Normally this error cannot occur,
CIS
parity is not checked during writing, and no timing
problems are imposed by the programming.
The program has been assembled for a 256
change register DLNGTH to 200 ,
8
track drum. To use the same program for a 128
track drum,
10
10
DLNGTH = 313 (memory location).
Head Pad Replacement
This replacement should be preformed only by qualified personnel. To replace the head pads, the following tools are required:
1. Surface plate (at least 3 ft by 2 ft)
2. Two 2-inch machinist's parallels
3.
Aligning pin, VRC (Vermont Research Corp.) part no. 59P7
4. Steel scale, 1/32-inch calibrations
5.
Height comparator with 0.000050 inch calibration (or finer), with less than 5 gram
contact pressure. The "Electroprobe" manufactured by Federal Products, Providence,
R.I., is suggested.
6. Adjustable height gage, 3 to 4 inch micrometer caliper
Replacement of the head pad must be done with the head mounting bar removed from the drum.
This is
done by removing the four socket head cap screws a1' the ends of the bar, disconnecting the matrix wiring,
and setting the head mounting bar on the two parallels on the surface plate. Place the bar with the bearing surface of the pads upward, and the stop adjusting screws accessible at the edge of the surface plate.
Remove the head pad by removing screws at the pad and those holding the leads with a strain relief and
the associated connector.
Insert the new pad, bending the leads gently. Replace all screws. Check
polarization of connector locating pins (which also s,erve as mounting screws) to ensure proper mating with
other half.
Before tightening head pad mounting screws, insert aligning pin through corresponding hole
in bar and up into aligning hole in the loose pad.
6-13
Insert aligning pin into pad carefully making sure that no leads are caught at the pin hole. With the pin
in place, scale the distance from eac:h end of the pad to the reed mount and adjust the parallel within 1/64
inch. Tighten pad mounting screws (2nd recheck parallelism. Remove the aligning pin and proceed to
height ad justment.
Using housing flat-to-drum dimensions and the required drop allowance, measure the thickness of the bar
and parallels in use and calculate the height setting for the height gage as follows:
HOUSING-TO-DRUM DIMENSION - DROP ALLOWANCE = REQUIRED BAR-TO-HEAD DIM
REQUIRED BAR-TO-HEAD PAD DIM + PARALLEL THICKNESS + BAR THICKNESS
HEIGHT GAGE SETTING
=
Set the height gage to size using the micrometer caliper; then use the height gage to set the comparator to
zero or center range. Rotate the actuator Iink and allow the head pad to move into actuated position.
Using a hexagonal wrench in the corresponding stop screw, lower the pad being adjusted until the height
comparator reads approximately zero at the center of the pad. Check elevation of the entire pad. Using
the two differential pad leveling screws bptween the reed mount and bar, and the stop screw for over all
elevation, set the pad level within 0.0001 inch (leading to trailing edge) and 0.0002 inch (end to end).
6-14
CHAIPTER 7
ENGINEERING
DRAWINGS
This chapter contains reduced copies of the block schematics, circuit schematics, and other engineering
drawings necessary for understanding and maintaining this equipment. Only those drawings which are
essential and are not available in the referenced pertinent documents are included. Refer to the table of
contents for a list of these drawings.
A complete set of engineering drawings is supplied with the equipment. Should any discrepancy exist
between the drawings in this chapter and those suppl ied, the assumption is that the latter drawings are
correct.
DRAWING NUMBERS
Engineering drawing numbers contain five pieces of information, separated by hyphens. This information
consists of a 2-letter code specifying the type of drawing; a 1-letter code spec ifying the size of the drawing; and variable-length codes specifying the type number of the equipment, the manufacturing series of
the equ ipment, and a serial number for the
drawin~,.
The drawing type codes are:
BS, block schematic or logic diagram
CD, cable diagram
CS, circuit schematic
FD, flow diagram
PW, power wiring
RS, replacement schematic
TO, timing diagram
UML, uti! ization module list
'NO, wiring diagram
CIRCUIT SYMBOLS
The block schematics of Digital equipment are mulHpurpose drawings that combine signal flow, logical
function, circuit type and location, wiring, and ol,her pertinent information.
Individual circuits are
shown in block or semiblock form, using special symbols that define the circuit operation. These symbols
are similar to those in the Digital System Modules Catalog but are often simplified. Figure 7-1 illustrates
most of the symbols used in Digital engineering drawings.
7-1
NON- STANDARD SIGNAL
GROUND LEVEL PULSE
NEGATIVE PULSE
-----0
GROUND LEVEL
•
NEGATIVE LEVEL
-----OC>
LEVEL TRANSITION USED AS A PULSE
OR TRIGGERING ON THE LEADING EDGE
OF A GROUND LEVEL
----~t4>
TRIGGERING ON THE TRAILING EDGE
OF A PULSE
-t!5V LOAD RESISTOR CLAMPED AT -3V
,-+
2
or
or
,~
3
or
PNP TRANSISTOR INVERTER
t BASE
2. COLLECTOR
3. EMITTER
3
.... v
or
GROUND -LEVEL NAND, NEGATIVE-LEVEL
NOR DIODE GATE
2
DELAY (ONE-SHOT MULTIVIBRATORl
I. INPUT PULSE
2. OUTPUT LEVEL. -3V DURING DELAY
3,4. TRANSFORMER-COUPLED PULSE
OUTPUT. EITHER TERMINAL MAY
BE GROUNDED
DE
Figure 7-1
DEC Logic Symbols
7-2
GROUND-LEVEL NOR, NEGATIVE -LEVEL
NAND DIODE GATE
or
or
3
'-i
1. PULSE INPUT
2. CONDITIONING LEVEL INPUT
3. PULSE OUTPUT
2
CAPACITOR-DIODE
GATE
PULSE INVERTER
'-1
PA
~:
PULSE AMPLIFIER
t. PULSE INPUT, POLARITY INDICATED
BY INPUT SIGNAL
2,3. TRANSFORMER - COUPLED PULSE
OUTPUT. EITHER TERMINAL MAY
BE GROUNDED
FLIP-FLOP (MOST FLIP-FLOPS HAVE ONLY SOME
OF THE FOLLOWING):
I. 01 RECT· CLEAR I N PUT
2. GATED~LEAR INPUT
3. DIRECT-SET INPUT
4. GATED-SET INPUT
~. COMPLEMENT INPUT
6. OUTPUT LEVEL, -3 V IF 0,0 V IF ,
1. OUTPUT LEVEL, 0 V IF 0, -3 V IF t
8. CARRY PULSE OUTPUT, UPON BEING CLEARED
o
2
5
4
Figure 7-1
DEC Logic Symbols (continued)
LOGIC SIGNAL SYMBOLS
A Digital logic signal symbol is shown at the input of almost all circuit symbols to specify the assertive
conditions required to produce a desired output.
All logic signals are either standard Digital logic levels or standard Digital pulses. A standard Digital
logic
I
iis either a ground (0 to -0.3v) or -3v (-2.5 to -3.5v). Logic signals are generally given
mnemonic names which indicate the condition repre:sented by assertion of the signal. An open diamond
7--3
(-----<» indicates that the signal is a level and that ground represents assertion; a sol id diamond (
.)
indicates that the signal is a level and that - 3v represents assertion.
The standard Digital negative pulse is indicated by a sol id triangle ( - -... ) and goes from ground to - 2.5
or -3v (-2.3 to -3.5v tolerances). The standard Digital positive pulse, indicated by an open triangle
(---1», goes either from -3v to ground or from ground to+2.5v (+2.3 to+3.0v). The width of the
stcmdard pulses are used in this equipment is either 1.0, 0.4, orO.07jJsec, depending on the module and
appl ication.
Occasionally, the transition of the level is used at an input where a standard pulse is otherwise expected
and a composite symbol (
~) is drawn to indicate this fact.
The triangl e is drawn open or sol id de-
pending, respectively, on whether the positive (- 3v to ground) or the negative (ground to - 3v) transition
triggers circuit action. The shading of the diamond either is the same as that of the triangle to indicate
triggering on the leading edge of a level, or is opposite that of the triangle to indicate triggering on the
trail ing edge. Any other signal is nonstandard and is indicated by an arrowhead (
direction of signal flow.
• )pointing in the
Figure 7-2 illustrates the use of many 6f these symbols.
COORDINATE SYSTEM
Each engineering logic drawing is divided into 32 zones (4 horizontal, and 8 vertical) by marginal map
coordinates. Figure references in the text are usually followed by a letter and a digit specifying the zone
in which the referenced circuit is lo,:ated.
MODULE IDENTIFICATION
Two numbers appear in or near each circuit symbol or inside the dotted I ine surrounding multiple circuit
symbols. The upper number designates the module type and is usually four digits long. Standard modules
are identified by this number in the Digital System Modules or FLIP CH IP Modules Catalog. Nonstandard
modules are described in this manual or in the referenced pertinent documents.
The lower number is the module location code. Sometimes this code is just the 1- or 2-digit basic number
indicating the module connector location within a mounting panel, as shown in Figure 7-2. Usually this
basic number is preceded by a number to identify the cabinet and a letter to indicate the mounting panel
within the cabinet. Mounting panels are usually identified alphabetically, with A in the upper location.
Module connector terminals are identified by letters next to the circuit symbol. To identify any particular
terminal, the terminal letter is added to the module location as a suffix. These letters run in alphabetical
order, with the letters G, I, 0, and Q omitted. (See Figure 7-2 for examples.)
7-4
Some modules have the suffix II JII or IIRII followingl the normal 4-digit module type number. II JII indicates
that some of the jumpers have been removed. An .:>ctal code may follow the module number to indicate
which jumpers are connected, but in general the block schematic must be consulted. "R" indicates that
all the output collectors have clamped load resistors jumpered to them. A number and suffix such as
4112-70R" indicates that the first three outputs (H" L, and P), counting octally in alphabetical order,
have clamped load resistor jumpers and that the last three outputs (T, W, and Z) do not.
EXAMPLE
Figure 7-2 illustrates Digital symbols and nomenclclture. The circuit shown is a Type 4303 Integrating
Single Shot used to control the enabl ing time of several gates. The module is located in the twelfth position from the left (when viewed from the front, or wiring side) of mounting panel B (the second from the
top) in cabinet 1, specified by the module location code 1B12. The symbol marked DELAY is a monostable
multivibrator with two complementary outputs, terminals U and W each shown twice.
In the stable state
these terminals are at ground and - 3v as shown by the diamonds inside the symbol on the left. The - 3v
from terminal U is the assertive level for a gate in 2D18 and is applied to terminal F as the SAFE signal.
When the rnultivibrator is triggered, it momentarily goes to the 1 state and terminals U and W reverse
their voltage levels, as shown by the diamonds replresenting the 1 state conditions. Terminal U now provides a ground assertive level to terminal M of a gl:lte in 1 B15, and terminal W provides a - 3v assertive
level to terminal F of a gate in 1 D02. The time the multivibrator remains in the 1 state is a function of
the capacitor selected by jumpering terminal D to jrerminal E and the setting of the external variable resistor between terminals X and Z.
.....
---<>
SAFE
-- ----_. __
TO 2D18F
: 4303-
u w
- ---
1B12
u
W
-
-
-
DELAY
VARIABLE
I
I
TO 1D02F
I
-kJ--!--k"., s I
I
I
TO lB1SM
GO
lC12H
START
1BllJ
D
KI
----
L-
-RS
X
Z
lOKQ
OPEN
1B13H
TIME
Figure 7-2
T
Typical [)igital Logic Block Diagram
7-5
I
_J
SAMPLE
lC21Z
The multivibrator is triggered to the 1 state when anyone of three signals occurs. One of these is a
positive pulse named GO from a pu~se amplifier in 1C12. Another is a negative pulse named SAMPLE
from a NOR gate in 1C21, which is applied to the base of an inverter. The third is the positive transition
a"t the trailing edge of the START si~~nal, a negative level from a delay in 1 Bll. This will only trigger
the capacitor-diode gate when a gmund signal designated OPEN from a flip-flop in 1 B13 has been present
for at least 1 ~sec.
SEMICONDUCTOR SUBSTITUTION
The majority of DEC semiconductors used in modules of the 24 Drum can be replaced with standard EIA
components as specified in Table 7-·1. Exact replacement is recommended for semiconductors that are
not listed.
TABLE 7-1
DEC
SEMI CON DUCTOR SU BSTITUTI ON
DEC
EIA
EIA
D-001
1 N276
DEC 1754
2N1499A or 2N1754
D-003
1 N994
DEC 3009
2N3009
D-007
1 N277
DEC 3639
2N3639
D-662
1 N645
MA90
2N2451
D-664
1 N914
MD95
2N2489
D-668
Two 1 N3606 in Series
MDl14
2N1499A
D-670
1 N3653
1/4 M6.8 Az 5
1 N4099
DEC 999
MM999
7-6
NOTES:
BASI~HRU
I. NUMBERc "()'
CALLED
:25' ARE
2.WHEN h
NUMBERS
MUUNTEg ~~ CONNECTOR IS
OF PANEL IT RIGHT SIDE
IS "26 WHEN
MOUNTED
PANEL IT ~~ L EFT SIDE
3.WHEN 22
COMES ;29
ARE MOU:+~DCONNECTORS
SIDE OF PA
ON LEFT
'28 g, '29 W NEL THEY AR
RIGHT
MOUNTED 6N
BECOME ""2G &~ PANEL THEY
SIDt~N
A
y
SEE NOTE 1& 8
l
4. AT NO TIME
27
A 50 PIN
OUNT ON TH
PIN CONN.
5. WHEN BLO
E SAME SIDE
OVER POSI~~IS VERTICALLY
BASIC NUMBE~ ADD 30 TO
~ONNECTOR &W~~L
I
6. ON
WHEN BLO
TOP O~K~;N HORIZONTAL
TO BASIC NUM EL ADD 60
WHEN f:1LOCK
SER.
~~ BOTTOM ~~ ~ORIZONTAL
TO BASIC NUM NEL ADD
7. WHEN ST
BER
ADO 100 ~~oOFF IS ON TOP
WHEN STANg~SIC NUMBER
BOTTOM ADD FF IS ON TH'E
NUMBER
130 TO BASIC
i\SEE NOTE 4
1\
/
8. NUMBERS
READ FRO:~L
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TO RIGHT
\
SEE NOTE 6---1
SEE NOTE
SEE NOTE 3
2
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co4
I
2
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3
Drum Data Channel (DOC) BS-D-24-EFG-O-l1
Write Field Lock Out Select BS-D-24-EFG-O-14
7-21
3
2
4
5
6
7
A
8
A
r- -
B
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10
11
12
U
14
15
16
17
OCTAL
TRACKS
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0-17
20-37
40-57
60-77
100-117
1JO--137
140-157
160-177
200-217
220-237
240-257
260-277
300-317
320-337
340-357
360-377
FIELD
LOCK
OLT
SW
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37
OCTAL
TRACKS
PROTECTED
8
400-417
420-417
440--457
460-477
500-517
520-537
5lIO-557
560-577
bOO-b17
620-637
b40-t>57
6bO-b77
700-717
720-737
740-757
760-777
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DTYS 2
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DTYA2
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I
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REPRESENTS THE TRACKS ASSOCIATED WITH
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Drum X and Y Select and Drum Heads BS-E-24-EFG-O-13
7-23
2
3
6
7
Flow Diagram BS-D-24-EFG-O-2
7-25
_+______ ______________ ._L__._._________
~
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7-27
3
2
I"
I
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3
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4
Timing Diagram BS-D-24-EFG-O-31
Power Wiring PW-D-24-EFG-O-29
7-29
t
3
2
!
4
5
7
6
8
,I
DC WIRING
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7-31
Wiring Diagram WD-D-24-EFG-O-3 (Sheet 2)
7-33
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NOTE:
ALL WIRES RUNNING FROM 098 AND
078 ARE TO BE RUN IN BACK.
Wiring Diagram WD-D-24-EFG-O-3 (Sheet 2)
DIODES ARE
OR 0664 R
CAPAC I TORS
4700 PUF
Indicator Cable Breakout and Junction CD-D-24613
7-35
3
2
4
5
8
7
6
RFAR. VIFW
INDICATOR CABLE LOCATION
I
A
I
: IIA02
n
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INDICATORS
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2
3
4
Indicator Cable Breakout and Junction CD-D- 24613
T--~
NAME
COLOR
PIN
PIN
1----.
REMARKS
" •••
RED WET
.4t.
J~
-
---
..,,.
RED/WHT
1E15M
sw oLe OM
sw 1
L
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2
V
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3
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1E16M
4
5
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5
6
V
6
7
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3
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10
11
L
11
12
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12
13
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13
14
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14
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21
22
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23
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25
26
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26
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27/eOM
Field Lock Out Switch Panel WL-A-24-EFG-O-12 (Sheet 1)
7-37
_._.
A_
COLOR
NAME
PIN
PIN
REMARKS
-RED/WIlT
Jl
J~
RED/WHT
'\
T
32
V
32
33
U
33
34
lE22M
34
35
L
35
36
V
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FLO SW 37
U
SW 37/COM
RED
T
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~
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36
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832/PIN 2
JONES STRIP
832/PIN 3
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lC20W
SW 361
lC20X
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POWER SWo LOCA
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1---
BLU/WHT
BLU!WIlT
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0-7
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10-17
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N/O EVEN NUMBER" D
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N 0 ODD NUM.SWS
1--1---
Field Lock Out Switch Panel WL-A-24-EFG-O-12 (Sheet 2)
7-38
JACK
~
PLUGD
FEMALE
~
MALED
COLOR
PIN
LOCATION, LENGTH, ROUTE
MARK
lAOl
33" LONG
PIN
NAME
W/BLK (x)
W/BRN (z)
B82H
B82J
A
B
'lIRA
W/RED (R)
B82K
C
FLAG
W/ORN (0)
B82L
D
OVERFLOW
W/YEL (Y)
B82M
E
REQUEST
W/GRN (N)
B82N
F
PARITY ERROR
W/BLU (B)
B82P
II
DATA ERROR
E29/6R
K
-lSV
E29/1SR
L
GND.
REMARKS
TO CONNECI
THIS CABLE IS A 10
PLUG~D
ACT
PIN AMPHENOL.
.-
--~-
--
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D AND
BLACK
I( TWP
ARE TO BE
53" LONG
~~
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en
trj
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Control Logic to Indicator Panel CL-A-24-EFG-O-21
7-39
,........'
JACK
GJ
FEMALE
[i]
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LOCATION, LENGTH, ROUTE
PLUGD
MARK
lA02
50 11 LONG
MALED
--
COLOR
F=:
-- - W/ BLK (X)
-WI BRN (Z)
PIN
WI RED(R)
--
W/ORN (0)
W/YEL
(Y)
---------
W/GRN (N)
----:-W/ BLU (B)
--
W/VIO
(V)
---'_.-.- - -
W/GRY (G)
---_..-
WHT
NAME
C
D
--
--
E
---
L
C98E
F
DTRO
C98F
H
C98H
J
C98J
K
DTRI
I
DTR2
I
DTR3
(W)
L
L
C98K
M
C98L
N
1
W/ BLK (X)
-W/ BRN (Z)
-WI RED (R)
C98M
W/ORN (0)
C98N
R
DTRj
C98P
S
STR 1
--
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REMARKS
B
--
-----------
PIN
-A
(Y)
W/GRN (N)
DTR4
_.
P
-----
DTR~
r
DTR6
T
~-
WI BLU
(B)
U
r - - - - . - - - - - t----
, W/VIO
(V)
~--------
W/GRY (G)'
WHT
B82F
V
READ
B82E
W
WRITE
(W)
BLUEl'
AND
BLK ' ) '
TWP
r--
X
E29/7R
Y
E29/14R
Z
--
-15
GND
Drum Track Address to Indicator Panel CL-A-24-EFG-0-22
7-40
JACK
[iJ
PlUGD
FEMALE
L~J
MALED
COLOR
PIN
LOCATION, l:-ENGTH, ROUTE
4411 L()NG
PIN
WI BLK (X)
A
WI BRN (Z)
B
NAME
C90H
C
DCL~
W/ORN (0)
C90J
D
DCL3
W/YEL (Y)
C90K
E
DCL 4
f
DeL 5
WI RED (R)
W/GRN (N)
cc}Or.
WI BLU (B)
C90M
H
DCL 6
(V)
C90N
J
C90P
K
DeL 7
1
DCLS
W/VIO
W/GRY (G)
WHT
(W)
C90R
M
DCL~
WI BRN (Z)
N
(R)
C90S
C90T
P
DCL 10
DCL 11
W/ORN (O)
C90U
R
DCL 12
'W/YEL (Y)
C90V
S
DCL 13
W/GRN (N)
T
U
DCL 14
DCL 1 .)c-
WI BLU
(B)
C90w
C90X
W/VIO
(V)
C90Y
V
W/GRY (G)
C90X
W
WHT
(W)
BLUE~
AND
BLACK)
TWP
REMARKS
L
WI BLK (X)
WI RED
MARK
lA03
DCL 16
I
DeL17
X
E29/SR
Y
-lSV
E29/l3R
Z
GND
Core Location Register to Indicator Panel CL-A-24-EFG-O-23
7-·41
'--
EJ
JACK
0
MALE 0
LOCATION, LENGTH, ROUTE
PLUG
FEMALE ~
PIN
COLOR
38 11 LONG
PIN
NAME
WI BLK (X)
WI BRN (Z)
C82E
A
1
DSBO
C82F
B
DSB 1
WI RED (R)
C82H
C
DSB 2
W/ORN (0)
C82J
D
DSB 3
W/YEL (Y)
C82K
E
DSB 4
W/GRN (N)
C82L
F
DSB 5
C82M
H
DSB 6
(V)
C82N
J
DSB 7
W/GRY (G)
C82p
K
DSB~
-------- r----
--
WI BLU (B)
1---------
W/VIO
--WHT
- - - - - - - -1 - - - -
(W)
C82R
M
1
DSB9
WI BRN (Z)
C82S
N
DSB 10
WI RED (R)
C82T
-----
P
DSB 11
W/ORN (0)
C82U
R
DSB 12
W/YEL (Y)
C82V
S
W/GRN (N)
C82W
T
DSB 13
DSB 14
WI BLU (B) __ C82X
U
DSB 15
C82Y
V
C82Z
W
DSB 16
1
DSB17
1--1--------
W/VIO
(V)
1---
W/GRY (G)
WHT
(W)
BLUE?
AND
BLACK)
TWP ...
REMARKS
L
WI BLK (X)
1---
MARK
lA05
X
E29/9R
Y
-15V
E29/12R
Z
GND
Serial Buffer Register to Indicator Panel CL-A-24-EFG-O-24
7-42
[iJ
JACK
FEMALE [~
---
LOCATION, LEN :JTH. ROUTE
PLUGD
44" LONG
PIN
PIN
WI BLK (X)
WI BRN (Z)
WI RED (R)
D82E
A
1
DFB 0
D82F
B
DFB 1
DFB 2
NAME
D82H
C
W/ORN (0)
D82J
D
DFB 3
W/YEL (Y)
D82K
E
DFB 4
W/GRN (N)
D82L
F
DFB 5
WI BLU (B)
D82M
H
DFB 6
(V)
D82N
J
D82P
K
DFB 7
DFB 1
8
W/GRY (G)
WHT
(W)
WI BLK (X)
WI BRN (Z)
WI RED (R)
-
D82S
N
D82T
P
DFB 11
R
W/YEL (Y)
D82U
D82V
S
DFB 12
DFB 13
W/GRN (N)
D82W
T
DFB 14
WI BLU (B)
D82X
U
DFB 15
W/VIO
(V)
D82Y
V
W/GRY (G)
D82Z
W
DFB 16
1
DFB
17
BLAC~
.1
X
-15
Z
GND
E29/11R
---
--
L
E29/10R Y
=1
..
DFB 91
1
DFB 10
TWP
REMARKS
-l
M
(W)
WHT
BLUE,
AND
~"l
-
D82R
W/ORN (0)
--
MARK
1A04
MALED
COLOR
W/VIO
---
Final Buffer to Indicator Panel CL-A-24-EFG .... O-25
7-43
...--
JACK
FEMALE
---
--
~
PLUG D
~
MALED
- -
LoCATION, LENGTH, ROUTE
F3
-
PIN
COLOR
PIN
;:::=:--=---== F=---
~~-~£
1
~~
------ ------ --
J
2
--
L
WHITE
f-----------, - - - -
r-----------
------
3
4
N
---------- f - - - - 1------
-----f--
R
f-----------
- - - --
T
,-
1--.
5
6
7
8
V
X
f--------
- - - - 1----
1-------
- - - f--~~
----
~-----
-------
~-------
~-----
~---
C23F
:~~~:-
- - - - t-----
-~
~-----
1------- ~-
1------
- - - - 1----
--
NAME
PIN
PIN
NAM~
E04T
26
MBD7------. DF7
COLOR
DF~BO
WH TE
~.
1
2
M
" H
ROn H
L
4
5
M
T
Y
"
E08Y
6
7
9
8
10 ___ 9
11
10
r---12
11
13
12
~--
14
r----
---
18 DFI 7---MB1 7
__ r-----f.-li.z___ --19
EOIT
1------- MBD~DFO
20
Y
1
1--21
E03H
2
1--22
M
3
---- 1 - - - - - - 1 - - - - - - - - - - 23 _____4...._
1 - - - - - - ------ f - - - - - - -~---- f - - - 24
Y
~----- --.5
25
MBD~FO
WHITE
E04Y
'----
I
,
,.
M
WH
BLACK
16
MBDl 7----e-DF I'
DCL5~S
J
L
43
11
N
44
1?
V
6
7
8
9
10
13
X
C25Z
49
17
T
V
GND. LUG
F3 to Logic Drum Side CL-A-24-EFG-O-26 (Sheet 1)
7-44
15
45
46
47
48
.,
:TE
36
37
11
12
13
14
38
39
40
41
42
R
.,
10
35
X
C24Z
C25F
15
14
----16
15
f - - - - -------17
16
9
29
30
31
32
T
H
,..
8
33
34
"
C24T
13
27
28
50
14
15
1n
GND
1 JACK
[~J
0
MALE 0
FEMALE ~J
COLOR
LOCATION, LENGTH, ROUTE
PLUG
PIN
*ONLY USED IF SPECIFIED
F4
PIN
NAME
COLOR
PIN
PIN
1
26
2
27
NAME
WHIT~E~__~~__~D~13~L~__r-3_+_A_C_B_2_~
___
DC~L~2_~________~__________r-28-+________~
~l
3
29
V
4
5
4
30
z
6
5
31
D14z
7
6
V
8
7
R
9
8
R
,r
"
32
33
I
34
1
L
10
9
WHT
D1SL
11
10
BLK \
R
12
11
V
13
12
RED)
z
14
13
WHT
D16Z
15
14
BRN
V
16
15
R
17
16
L
18
ACB17 ....DCL1
C04Z
19
DRUM FLAG
TWP
TA/PIN 1
35
TEM SW (TA) ~
TA/PIN 2
36
TA GND*
--~---~~--~--~--~----~·~--~~v---1~~~~---+---~~~----~
"
37
mT&Tn
r- - -
flg~~
38
836PC-S
39
836PC-1
40
+10 MC
~Bd~WE
Tt~R~or,rE
./
"
C12X
21
41
GRY/BLK!TW
E09Y
42
DATA REO AN:;
~l
C10E
43
BEGIN
C11X
44
T7B
45
lOT 6002
46
lOT 6004
DATA REQ.
D13F
~~~__~~O~t4~~:N~-+_2_2~!~
DA~~A~I~::N~~,~__~___~_~D.~:12~:E~____+-4_7~~I:~IQT~6~,1~.O~,.2~~
..
C24L
23
DCL 2
C24N
24
DCL 3
WHITE
C24R
25
DCL4~MA4
-'I'
I
GRY/BLK/TW
BLK
i)
Dll Y
48
lOT 6104
C06X
49
lOT 6204
GND LUG
50
GND
F4 to Logic Drum Side CL·-A-24-EFG-O-26 (Sheet 2)
7-·45
JACK
W
I
LOCATION, LENGTH, ROUTE
PLUG D
FEMALE ~
F5
MALED
-
PIN
COLOR
RED
GREEN
RED
GREEN
RED
GREEN
RED
El5 J
~
H
Y
El5 Z
El6 J
4~
., ..
H
Y
GREEN
Ei6 Z
RED
GREEN
El7 J
~~
RED
GREEN
RED
GREEN
RED
H
Y
El7 Z
El8 J
• If.
H
Y
GREEN
El8 Z
RED
El9 J
,j-
GREEN
RED
;
GREEN
I--
Y
~
El9 Z
RED
SPARE
E20 J
I
I
GREEN
RED
GREEN
0
H
H
Y
E20 Z
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NAME
PIN
PIN
NAME
E21 J
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Xl4
COLOR
RED
XO
~~
XO
Xl
Xl
X2
X2
X3
GREEN
RED
GREEN
RED
GREEN
RED
X3
GREEN
E22 Z
X4
X4
BLACK
~Il
Ell E
H
Y
E21 Z
E22 J
•
H
Y
~~
X5
L
R
~
X5
X6
Ell V
El2 E
l~
X6
X7
L
R
~
X7
El2 V
XIO
El3 E
4~
XIO
XII
XII
L
,..i'
El3
R
V
...
L
El4 E
Xl2
Xl2
Xl3
.
Xl3
BLACK
R
El4 V
""II'
GND LUG
Head Selection CL-A-24-EFG-O-26 (Sheet 3)
7-46
Xl4
Xl5
Xl5
Xl6
Xl6
Xl7
Xl7
YO
YI
Y2
Y3
Y4
Y5
Y6
Y7
YIO
YII
Yl2
Yl3
Y14
Yl5
Yl6
Yl7
GND
r - - - -..........- ......-
JACK
FEMALE
. - - - -.... - - _..... _
...... - ...._ .
[=J
PLUG [~]
[_-J
MALE
LOCATION, LENGTH, ROUTE - AT PLUG END.
USE TRIPLE CONDUCTOR SHIELDED. JUMPER IN SPARES
'xl
AS NEEDED. PLUG END MUST NOT BE CONNECTED WHli:.E
SOLDERING LOGIC END.
~
COLOR
PIN
PIN
NAME
II:
1=====:==t======t==t===~==::::U'
E25H
1
RED
STARTl
BLACK
~~ E
2
CT
F
3
FIN
-~~~~~--_4---+~~-
GREEN
:J'
TAPER PIN CONNECTION
_.................. .
'c..LOCK
.7;1
SHIELD
GND
4
GND.J
RED
H
5
STA~
BLACK
E
GREEN
F
6
7
CT
CLOCK
COLOR
PIN
PIN
..
NAME
-- I
-cd
26
STAR~
E
27
CT
GREEN
F
28
FIN. (
fl:L... _. ~
SHIELD
GND
29
GND)
i
RED
H
30
STAR:r1 ...___ _
BLACK
E
31
CT
n F
32
FIN.
33
GND
RED
E2SH..
~~
BLACK
GREEN
SHIELD
E25GND
SHIELD
GND
8
GND
RED
H
9
STA~
34
BLACK
E
10
CT
bLOCK
35
GREEN
F
11
FIN.
j3
36
GND
12
GND
37
H
13
STA~
38
~
~CLOC.!5~
.. 1eLOcK
(#8
)
.....
- ..--.------4---+-------~-4----~~---~.----------+_----------~~----------~
SHIELD
-4---+--~--_+--_4--=~~-----------------+_----------~~----------~
RED
~B~LA~C~K~.-~--_+~EL---_+-l-4_+-~CT~J~L-~l~dAT·.~~I,~~~.----------~---------_+-3-9~---__------~
GREEN
11 F
15
FIN. ~4
40
SHIELD
E25GND
16
RED
BLACK
GREEN
41
~
42
18
STA~
E
19
CT
F
20
FIN.
E25H
4~
J
GND
17
43
lc;LOCK
1#5
GND J
SHIELD
GND
21
RED
H
22
STA~
BLACK
E
23
CT
NOTEz
SA~LE
ALL
CLOC~~4
HEADS AND INITIALLY
USE HEAD WITH
l CLOCK
45
HIGHEsr~ 46
OUTPUT
)(#6
47
48
GREEN
•
F
24
FIN.
49
SHIELD
E25GND
25
GND
50
~--------+_~,~~----~_4.
Clock Track CL-A-24-EFG-O-26 (Sheet 4)
7-47
,---
COLOR
GRAY
GRAY
1---------
PIN
NAME
lOT 6101
r---
PIN
2F20E
2H07E/Fl
SKIP ON DRUM
2F21E
2H07H/Fl
SKIP ON PEG DEo
DRUM FLAG'
2H05P/F2
2H07F/Fl
DRUM FLAG'
2H07F/F2
2H25L/F2
lOT 6201
1---
1---
WHITE
1--f--
BLUE
MBO
~~
~~ 1
1---
--
REMARKS
____lE25A/F3
~~
2E24E
~~
B
H
2
C
K
3
D
M
4
E
P
5
F
S
6
G
U
7
H
8
J
2E24Y
9
K
10
L
2E25E
~~ H
11
M
K
12
N
M
13
P
P
14
R
S
15
S
U
••
V 16
BLUE
MB17
,J
"
,r
T
lE25U/F3
W
W
2E25Y
1..--
lOT and 10 Skip, Computer Side WL-A-24-EFG-O-27
7-48
FL~
[J
FEMALE [J
PLUG
JACK
J1~E
1
RED")
"J."vvr
2
GRNJ
- .•-
3
4
.•-
5
6
.Lnc
GRNJ
RED?
-~
.Lnc
GRNJ
RED?
GRNJ
RED3
7
rnT......
.. ' ..
8
9
'PW::-
10
GRN
RED'"')
11
12
13
14
.............
J.L"r.-
GRN
RED?
rnr.......
rJ ....
GRN
RED?
_._
J
GRN
"J."nr
RED'")
mLTn
RED"')
rm.Tn
GRN5"
~
sMJ ..JtlHT
RED -;
I·
-
rftY.......
rJ ... '...
GRN
RED
2
.)
GRN
LOCATION, LENGTH, ROUTE
MALE~
COLOR
RED?
[!]
15
16
17
18
19
20
21
22
23
24
.Lur
25
10" INSIDE DXMENSION
F5-J2
CABLE
I~E
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NAME
COLOR
L. __
RED
XO
GRN
Xl
Xl
X2
X2
RED") _,.•
X3
X3
X4
X4
5
GRN
.LVYC
GRN
REDi.
GRN --;
,..
T.T ...
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
X14
32
_n
.&..".
33
34
II
35
/
,36
37
38
39
40
41
42
43
X7
X7
X10
Y10
X11
X11
26
28
29
30
31
B~ JK
X5
X5
X6
X6
NAME
27
.L'~
-- . . .-RED'")
l:f".&.....
PIN
~
XO
"}
PIN
..
44
45
X12
X12
46
47
48
X13
49
SPARE
X13
B~
Selection Cable CL-A-24-EFG-O-28
7·-49
50
.0.
.".._--:::
X14
X15
X15
X16
'X16
X17
X17
YO
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
GND
Utilization Module List UML-D-24-EFG-O-4
7-5i
3
2
2
t
11127-117
11216
4
5
111132-777
4115R-17
ACT~WO
DSBS
A
3
11127
R
6
7
4112-30
DATA REQ
lj
4303
4110
4604
12
11127-17
111132-173
RQ
DSB 17
R
t--WRITE~
R
RQ
DATA IN
ERROR SYNC
TAKE WORD
-
TRA
R
R
READ
OVERFLOW
ACT
&
DT/ST
R
CWMP
R PAR I TY
DE
DNG
ACT
SET RQ
R
R
R
PAR ERROR
R
DE
FLAG
11216
116011
OLe + I
R
11216
11127-20
B
11217
6115-12
4301
r--
t
I
R
R PARI TY
OSB
DSB
DSB
DSB
DSB
I
i
I
I
DSBS
WRITE
EN 1
FL
R
WR ENA
RQ
FL
PARI TY
ERROR
SET S. A.
R PARITY
BLANK
SC ;i SA
1m DATA
a
R
11217
11217
11217
4217
4112-77
11216
4127
4216
I
4216
I
OV ERFLOW O
i
PA2
DELAY
lOT 61011
OLC CLR
OLC
DLe
I
I
DLC
Ole
IjRITE
I
DFB
r--
I
c--
---'
-
11112-77
-
~
TI ME
CHAI N
WR ENA
4217
R
4217
4113-77
OF
OF
r--
I
t--
-
I
-i
-l
11113-76
1160'6
13134
11110
I
R
-
-I-
R
OT
DT
R
~"'"
-
R
R
- r--
4606
4531
11531
4531
4530
11531
11530
WR I TE ENABLE
R
-
R
SPARE
I
READ STAD" CLOC:, >RA"
R
READ
TAKE
WORD
R
SC=SA
PAR ERROR
11530
0A
R
R
CLOCK TRACK
ERRO
R
I
R
R
t--
- t-- OTXB
I
R
-
R
R
115313
11530
11530'
11530'
0B
SC=SA
R
11530'
11529
1537
·1537
c
PAl
DFMBI-DF
OSB SHI FT
1
r--
OF
DF
I
i
i
i
E
DCLS
9-17
621311
TAKE
WORD
fl
DT YA t-- DT YB --E
T7C
I
I
DCLB
0-8
LOCK
OUT
10-17
-.B
B..I-
DE' PAR
11606
A
I
i
r--
-
f---
DFB
9-17
0-8
R
DATA I -
PAl
I
61132R
I
LOCK
CUT
9-7
R
c
61132R
B
~
DT CLR
I
PAR ERROR
4216
11127
6HJ2R
R
I_BLANK
PAR ERROR
4216
25
LOW
VOL TAGE
DETECTOR
WRITE DATA
1I127
24
R
R
1I60'1I
""'l
OV~RFLOWi
DSB CLEAR
LOCK
OUT
113-17
R
R
j
I
R
FL
o -ER SYNC
DATAO
DSB
I
0-7
6102R
23
PAl
OV ERFLOW
0- DSBS
D
R
22
B 1134
491'2
11311
FL
SEC
CNT
O--BLANK
OVERFLOW
1
DSB s
FL
21
LOCK
OUT
FL
STR
STR
ADD O
/,
C
111132-776
4215
ADD RI
SET I
DSB 17
20
19
R
T7B
11216
4127
STR
ADOI
SET 0
DSB 17
R
11216
12131
18
8
DSB-WD
R
R
11216
17
7
DT + I
PA 3
DE
R
POWER
CLEAR
OPTI CtlAL
W5135
LOW
VOL TAGE
DETECTION
FLAG
FLAG
R
R
T7C
ACT
TAKE WORD
~
R
COMP
R
PAR ITY
111135
I
-R
R
DF CLEAR
ACT
TRA
r--
CLEAR
16
~REQ
06
TRA
DSB I NIT
-.R
DC
COMP
SEC CTR
OVERFLOW
SET REG
R
5002
AND
I
.-B-
4401
6
15
~R
O-CTR
TAKE WORD
14
W505
4912
REO
DRUM
POWER
DOC CLEAR
R
13
LQ....
62011
TAKE WORD
IDLE
RD / WT
R
11
DISABLE
IDlE
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10
9
8
110
5
4
PA2
I
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I
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1
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-
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i
PA2
DSBDFI-DSB "Y" AXES
OSDSBI-DF
"Y" AXES
"Y" AXES
"Y" AXES
IIX
32K WORDS MA IMUM
Il
AXES
nXI!
AXES
"X" AXES
"X" AXES
"X" AXES
"X" AXES
"K"
AXES
"X" AXES
"X" AXES
WR ITER
CLOCK TRACK
AMP
...... E
65K WORDS MA IMUM
F
I
131 K MAX I MUM
PA3
G
I
r--
-
~
1
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DF-CLR
-
I
I
I
I
i
J
D
i
I
I
I
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2
3
4
Utilization Module List UML-D-24-EFG-O-4
TI
T41!113
100-X-1016 BROWN
01
IN3208
*
ORANGE
3
INO.141Io--......-:-.....
ORANGE
02
IN3208
+
I!I
3!1,OOO
MFO
2!1V
INPUT
II!lV AC
25W
YELLOW
601\.1
+
04
IN3208
-
CI
35
,000
MFD
2!1V
10V
RI
C!I
+
+
-
C2
135,000
MFO
2!1V
+
-
1
C3
35
,000
MFO
25V
6
1
REO-WHT
TWISTED
+
15V
r---O
.. ,~~~~--~~------~--.------~~--------~~~------~---------*~--~
BLUE
05
IN3208
*
YELLOW
BLUE*
RED
.I"
-
*
RED
35,000
MFO
25V
+
I!lV
YELLOW
~
*
t---------;------+--.------~~----------~~~--------------~~~--~ YELLOW
+
15V
08
IN3208
GREEN
GREEN
UNLESS OTHERWISE INDICATED
HEYMAN MFG CO TABTERMINAL IN PLASTIC BUSHING
*
*
c:::J CINC:H
.JONES TERMINAL
STRIP.
r-----------------------------------------------------------------------------------------------.-----QGN0
CI
REOr - -
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}
O~~:_4~~--~~~~ O~.-----_T------------------------------+_--------------~~--------------~~+_~+_4-+_0 ~:~~:~FF
WHT\
#14 WHT
03
NOTES:
-6 TERM
JONES STRIP
#541-6
Power Supply RS-779
Power Control Panel RS-832
7-53
0C
C6
.001 MFO
UI2
E 0
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Ill' --cr-- -
.,
.,Ill'
II
I
, 0~
........-O
D9
I
1<
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08
Ill'
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Ill'
Ill'
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L 0
-
I~
.,
.,
T
I
I
014
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E
OUT "1" IN
C
C
T
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68,000'
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I
1
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A
68,000
5600
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013 J-662
I
I
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N
68,0'00'
!4 5600
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r
.; 0"---"'--Cj>-- --
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~
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02
UNLESS OTHERWISE INDICATED
RESISTORS ARE 1/4 W, 10%.
DIODES ARE 0-001
.., W
1
V'
TOl5
I
0 ~111--6
01
.
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I
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r
P 0I - -......._Cj>---O:!-
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v
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I
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NO
I
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I
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v
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06
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1
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I
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I
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I
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A
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68,000
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100,000
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0-662
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~
UNLESS OTHERWISE INDICATED:
RorSI STORS ARE 114 W; 10 'II.
CAPACITORS ARE M M FO
DIODES ARE 0-664
,.RANSISTOR5 ARE DEC 2894-1
C16, \ 68
I CI7 1l 68
--'t:--~I~
_~~--==-...~-.-~~~========--=-====------------~
~!~!!!l!~!!!!!!!~~:!!!
I
Diode RS-10ll
Flip-Flop RS-1201
7-54
--------------------------------------~._----------aA+IOV(A)
R5
68,00,:.0_ _ _ _ _-+________________-.
RI7
68,000
-+---"--41----0 D, V GN D
C6
220
C3
150
CKH
3 00
roN
C4
50~ M .....---l__- -....._...-J
R8
750
5%
R6
3,900
RII
3,300
RI2
100
5%
RI4
220
5%
RI5
820
112W
5%
C8
100
T
' - - - - 0 C-15V
UNLESS OTHERWISE IN DICATED:
TRANSISTORS ARE DEC 2894-1
CAPACITORS ARE MMFD
RESISTORS ARE 1/4 W ,10%
DIODES ARE 0- 664
RI9 IS A 80URNS POT
,---------------------------------------------------<0 A+IOV (A)
.-----+------_-------------------------------------------------<08 +IOV (8)
R7
3,900
5%
RS
2,200
5%
RIO
22,000
-------~--~--------+_------+_------------~~--+_------._-------<.-~~--~D
u
GND
~~~--_+--+_---UE
Z~------~
K
n..---------.
~o
ca
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L-_________________________________- "_ _ _ _ _ _ _ _ _ _ _ _ _ _ _I---Q
UNLESS OTHEWISE INDICATED:
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CAPACITORS ARE MM FD
I ••••••••••••
0
I:
>< >-
N
r---------~--------~~--------1_----.----~----------1_--------_.--------~~--------~--------------------~A+I~~)
NO
R28
~
R29
R31
I~~
L-------~~------~~------~.-------~~------~~------~~------~~------~~--~--~--_+--~~-_4~'C
-IIIV
UNLESS
OTHERWISE
INDICATED
RESISTORS
ARE
1/4Yt\ 10%
CAPACITORS
ARE
MMFD
USE THE E~l:tf:p__BOAR~OF~~~ __
[!! ~ ~!! t ! ! ! ! ! ! ! ! ! ~! I!! !J
Drum Sense Amplifier RS-1537
Inverter RS-4102
7-56
-----------...,.--------------------------------------,-----oa+10\1(8)
r----,------t---------.....
+IOV(A)
-·---------~OA
th
E,.
CI
3,000
680
5%
0
GNO
04
0-662
L
P
K
V
U
O~
0-662
C6
.01
01
0-001
0-662
MFO
R
RII
1,500
5%
OS
Z
V
RI2
1,500
5%
02
0-001
07
0-662
RI3
1,500
5%
D3
0,-001
C7
.01
MFO
RI4
560
112W
C-15V
UNL.ESS OTHERWISE INDICATED:
RESISTORS ARE 114Wj 10%
CAPACITORS ARE M M F 0
~
L~
...........
c
'"
\I.
:J:
"'"'
'"
-'
•
Z
IL
a:
-;-~~
~ ~~~
1/1
...
r-------------~-----._-----------·-----------------------------------------~OA+IOV(A)
~------------+--------~~-----~---------~----------------------------------<>B+IOV(B)
r----~~-~--_oO
Q2
2NI305
O~I
K O-----M14~---~~~A,Ar~+H
L.
GNO
016
0-662
O-----fl~.....~-:~--I-1- t
C4
017
0-662
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MFD
0 .. 001
N
o----.....~--...
N
o___"14.0_-_00_1~
05
018
0-662
C3
06
.01
0-,001
RIO
01
1,1500
O-OO!
07
0-,001
5%
MFO
08
0-001
D9
0-001
V
RII
560
V2W
010
O--O-O,-I--t
O------tlt-I......
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0-001
W
0"001
013
0-001
014
Z
---~----------~~-_--------~___<>C-I!5V
O------~~~-0-12----~
--_14.-
0 ___
0 001
------'
UNL.ESS OTHERWISE INDICATED:
~~~l~r,9tR~ ~~~ 1~~1b
10%
1!!~!!H!!!!!n!!'~!n~
L:
______________ .__~ .
Inverter RS-4105
Diode Unit RS-4110
7-·57
, - - - - - - - - - - , - - - - - - - - ? - - - - - - - - - - - - - - - - - - ' p - - - - - - - - - - - . . , . . - - - - - - - - - - O A + 1 0 .... (A)
.----------.---I--_.--------------1f---.----------+----------oB+IOV(Bl
...------------+--4--_---------+--+----.-----+-I-...---+--+--.--QD
G~ID
ROO
120,000
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IZopo
D4
NO--~~__t
IN
IN
IN
D3
R25
560
M()---!III~--'
Fo--~~--'
112W
C8
.01
MFD
,
02
T
D2
IN
S
DI4
OUT INU :7
DI
R5
UNLESS OTHERWISE INDICATED:
RESISTORS ARE 114W 10%
CAPACITORS ARE MMFD.
DIODES ARE D-66<:'
I,~O
D5
x n---NlII---"
IN
DI3
DI7
V
.----------~-+----------------~r_~--------~
......- - - - - - - - - - -.....-----oC -I~,V
·-------~~--------------
----_-------------------f~----------------_{)A-t«:lV(A)
....-~-------OIB
..ICIV(B)
-----I--~t_-------------_4--_4~-----~_+-~-~-~~D
RI2
(lND
"l000
CI
.01
MFD
t > - - -.........np
OUT
DI6
IN
IN
DI5
M o----IIOI-~
D3D
RI9
560
112W
C2
.01
Q4
DEC 2894-4
MFD
O----~T
R o----IIII-~
IN
OUT
DI2
U 0----Il0l--4
IN
v 0----Il0l--....
D9
OUT
XO---IW--~
uw
50---_811-.......,
01
UNLESS OTHERWISE INDICATED
I~ESISTORS ARE 114W. 10·4
oCAPACITO:1S ARE MMFD
DIODES ARE D-864
O------nz
(}------N
----------------------------.--------------------------------.---------------------------------------0
A+IOV(~
r-------------__
r_------------~~·--------------r_------------~~----------------~8+IOV(8)
IIlI
33,000
t-------+-------+-------+-------t-------+--------+_------+-------+_------~----~+_------_.---4~OO
+
C2
.01
MFO
CI3
3.9 lIFO
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01
0-001
r
UNLESS
OTHERWISE INDICATED:
RESISTORS
ARE
1/4W, 10%
CAPACITORS
ARE MMFD
ONO
M
N
v
R
1
1 .0(
••
••
III •
U •
0 •
......
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I
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•
Diode RS-4115
Capac itor-Diode-Inverter RS-4127
7-59
y
~·I
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(;E (;H
)J
ONE
OUT
FFO
ADD ZERO
FFO OUT
FFO
ce
2.Z00
o----t (
CLEAR
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~:.I.ooo
>
~~
k()'
>
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01
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<-
.
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68,~~1>
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>
C
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···
···
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~ f-
R26~
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4 ~.
4~
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........
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···
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<
.....
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;,,000
150
~
•
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&!I..
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4~
4
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024
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1"028
0-662
GND
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o-"'e62L...~~
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I~O
I"'C~
B
~~~
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0-668
O-~
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R20
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~
CII
1M
RI9
3,000
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......... ~RII
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017
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0:-662
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0-~8
03
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30
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~~
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I
0;..66B
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08
R 30
1,500
5%..
vv
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~
0'20
[)-668
CI7
330
027
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1,500
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0~66B
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51" ..
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(
5%
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v
1,500
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RI7
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%
vv
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0.:"668
T
330
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R31
T
'lcl8
330
1,500
5%
oJt Zfj~t Z~~O
8ii
LEVEL
FFB
o~~
ZJJ~
FF8
4-Bit Counter RS-4215
Quadruple FI ip-Flop RS-4216
7-60
st;
o
E
LEVEL
FFA
D.
J•
0-S68
f~
T~
,.
,.
..
..
N.
o•
s.
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OUT
FFC
c.
H.
O!,
>N&
>5%
( H
( E
SET
ZERO
IN
ONE
OUT
OUT
IN OUT
FF 0
LEVEL
FF 0
LEVEL
FF 0 FF 0 FF C
FFo
FFC
UNLESS OTHERWISE INDICATED. RESISTORS ARE 114W, 10%.
CAPACITORS ARE MMFO. DIODES ARE 0-664. TRANSISTORS ARE DEC 1754
~~ 0-668
R40
v
T.
U.
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~ 1011
~~
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8
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2200
01
,
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330
~
3000
~,
>
~
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K
I
FO
I OUTPUT
-.
~-~,
..
--
---
\I
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>S8,OOO
03 ~,
--- '--
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>
R7
SB,OOO
~
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68,000",>
~ S8,OOO
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~
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R)9
3p00
5%
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Q5
Q9
Q8
Q7
Q6
~
~ .. 026
RII
• 3,000
>
>
RI2
3,000
5%
5%
4 ~7
68
C3
.
150' .
06 ~
psJ
I:;:I"IC~
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~
R5
S8,OOO?
>68%0
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0
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R20
1,5~0 5%
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.--~
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Q2
~~
F
>
R3
?
S8,OOO
---~
-
~
5%
r
> R2
~S8000
HI
68000
..
I'--~
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1500
5%
>
-- 1
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4~016
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~
5%
..
~
-b
'i~
~S\1,·~
500
i~~J..
CII,.J. 1500
330
11%
I
UNLESS OTHERWISE INDICATED
RESISTORS ARE 1/4 W,IO%
CAPACITORS ARE MMFIl
DIODES ARE 0-664
TRANSISTORS ARE DEC 2894-4
o
Ol
)H
FFo
I IN
FFO
CI3 , 1500V'
330- 5%
CI4
330
1
N
COMPLEMENY
C
4 .. 020
•
u
0
......
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560
II2W
•
~-15
C
J..
1500 5%1
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cle -b-
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330
5')10
330
z
....... :I
Z
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FFB.
III
Rl~
ci~411o
CI7.J. 1500
330.
5'l1o
II
Y
IOIJT FFA
)R39
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V
.......
~
> I:
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330
R40
1500
5%
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I ---------------------.
c
[).662
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1511~
R34
T
COMPLEMENT
B
U
lOUT
FFB
I~' 029
0214 110
R35
~
R39
1500
( M R(
OUT I IN
FFC
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A
I
o
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R28
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5" ~
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330
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0668
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>
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3,000
5%
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>,R25
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8%
R12
> RI7
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110011
0194110
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5%
1
,
CIS
330
J
COMPLEMENT
5".1
~~
~~
4~018
I
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1500 "50101
~
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3,000
5% )
RI5
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5%
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330
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...
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A
W
o OUT
FFA
z
I IN
FFA
~------------------~------------------_4~--,------------------~r_----------------------------------~A+IO(A)
~,OtJO
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__
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Dli
0-662
Dl2
0-662
013
0-ee2
R24
3,000
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R4
15,000
5%
R3
3,~0
R!!
os
15,000
5'l1o
UNLESS OTHERWISE INOICATED
RESIS10RS ARE 1/4 WI IO'llo
CAPACITORS ARE MMFO
DIOOES ARE 0-864
~4-------_1~---~----------------------
____
~~
______ __________ __
~
4-Bit Counter RS-4217
Delay RS-4301
7--61
~
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.
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2894-1
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DEC
De
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W
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014
ZERO OUT
1!!~1!!'!!~1!!!!!1!:!!!
C2
~OOO
4~---T---'-------""'---'-------T-----"1"-""-O
R4
20,000
C9
,~
((
R9
10
C8
.01
MfD
3·~!2...0R
C5
.39M1'D
o.L,Z GND
.01
MFD
R7
22
C3
... ( - ~9M~M
CI
.01
MFO
'>R22
+r-~:D
"~F~
+
9
E
-_ CIO
C9
MFD
0
X
Z
,......-
tl~9
~7
-
"
CI3
D-664
~~
5%
Q2
56
A~D8
RIO
y~
f--
<
R2
>' 5%
Q6
QII
~
:
~
: 6~
D-6G4
36
Q7
OEC28
• AllI
~~D4
~~ 0111
>
(>~
A~~
...
.g622 MFO
~~ '" . ,,-,
<'82
5%
0-!64
QIO
t;;-
~O C!I ,flRIl
C~
1,000
:
%
TI50
5%
>R
64
-
''''OGNO
'r~
oe
DEC
2894-3
2894-1
0
P
C6
( .027MEQ..oN
C7
( .0027~U
ll~F
T3~E
T2021
T2021
R6
120
112W, 5%
T2019
120
1/2~5%
,------~-----~~~---~-------------~---~~,~-~-~C-15V
UrLESS OTHERWISE INDICATED:
RESISTORS
ARE 114W; 10%
CAPACITORS ARE MMFD
1
l__~1.-.-;...u' ... -'-~--;~-~·.I
f - .:
0
..,
II..
I I I I I I • -;
....
Z
II.
II[
<011
..
::')
"-;-;-;1
~
•
JC
)-
N
Integrating One-Shot RS-4303
Clock RS-4401
7-62
r---------------~--------------_;~----_;r_------------;,------;,--------------~~------_.--------~A+I~(A)
r---~----_r----------------t_~----!_--·----------~----.__+----------------!_--~._~----~.__oB+~W~
RI?
I B,OOO
RIB
18,000
RI9
IB,OOO
RI4
120,000
R20
IB,OOO
RI6
120,000
09
0-003
WRITE{::~F
''oNE''
~loo
2,~
1tt8----...I--.................
....-J
150
~---f----------------~------+-----~"""--------------~----~------------4I~----~OO
R4
560
5%
RI3
C7
5%
MFD
SOV
560
IW
GND
.01
IW
~·-----------------------~-----------------------4~~--------------~~----~C-15V
x
(-ZOV)
UNL.ESS OTHERWISE
INDICATED'
RESISTORS ARE 1/4W; 10%
CAPACITORS ARE MMFD
H
'fc57
100~600 >
.AA
r6J
oy
?Z
~
I---
OZO
A
OU TPUT
B OUTPUT(+)
B OUTPUT (-)
A OUTPUT (+)
OH
R9
112W
~
y
IJ
-"
A
vvv
RII
1,200
Jo.
> R7
R13~
RI2
112W
r-RI5
100,000
100,000
RI4
1/2W
A
v
~
112W
~
~
-A
~;4
fP 09
1,200
R2B
4,700
112W
4,700~
112W
>
>>
>
4~ 011
0-007
O-g~7 4~
(
R!5
R6
3,300
RI W BUSS
+FO
.~
>
R21
.120,000
.
2NI305
D3~'
)
04f
"1
M
o·f
07
q
I"~,,
~
013
"014
)
to" to" to"
w
4700ph
TRANSISTORS ARE OEC 3009
Drum NRZ V/riter RS-4529
Drum X Select RS-4530
7-·63
..., D GND
~
2NI305
...
- E
NLESS OTHERWISE INDICATED:
RESISTORS ARE 114 W: 10%
DIODES ARE 0-003
INDUCTORS ARE ESSEX RFC· L
>
R22
3,300
• 1
D~ri~7··
50V
.. y
vvv
-AR3~
~r-~FO
R20
120,000
.AA A
Y
~O,OOO
R31
I00,000
~
lC2
< 6'~2~
010 .. I ~IFD*
0-662 50V
~
R29
>100,000
100,000
RI6
t-
R4
120,000
['ELI'>«>
D~b~7 ~,
R27
1,200
-A
R23 '
v
L4
-"YV~
~'D~6~7
RIB
100,000
~OO,OOO
.~DI
0-007
"00
112W
-A
A+IOV(A)
..., B+IOV(B)
~~02
R26
3,900
L3
RI9
100,000
A
4,700
>4,700
YR2
100,000
(?04
R25
~?
~
FlI7
10Cl,ooo
D?~07 "
RB
1,200
~
R3
100,000
06
liZ,!
vvv
A
"O~~07
Y
~~ 022
"00 ~
" ~o...,
3,900
LI
.4~OZI
RIO
INPUTS
A
R3
120,0 00
~+IO VIA)
.,
B
R2
120,000
R9
120,000
R4
'-----<
if
IW
~
R6
10,000
01
CI
2NI30!1
2200
E
(~
04
...
-
__ C2
...
02
...
09
N ..
R5
2,200
..
-
07"
-
I
RII
2,200
~
P'
~
05
2NI30!1
"014
0-670
.
P'
-
~'
"--'
......... ......-0
W 0:4
...
...
X O!!I
...
......
"
2~~~0 >
017
023
> R24
~2,200
..... y 0~6
P-67C
.....
027
......
0
~
~G NO
C6
'M",:IO
R22 •
6800 :
!lOV
,Ir 019
0-662
,,020
0-662
1
<,
DlJ"
L9"~D:'OO
02
G4 330
...
~
C3,133O
~
R7
10 ,000
:;: ..
O~ ~FO
!IOV
~
> RI9
RI3
10,000
10,000
~Z
---I~-
NOT E:
RESISTORS ARE 1/4W; 10%
CAPACITORS ARE MMFO
DIODES ARE 0-003
~C-I5V
..
08
CIO 330
_~-H
' U , R I4700
9
....
~
"
fR33
4700
018
~
....
=9'~'~D'
CI5 330
1
+Y~I
R30
1,!lOO
!I%
Rle
I,!loo
!I%
5%':
014
CI6 330
!~,
=9,~j~D'
~~30
+IN
~~'>
"030
0-67o
...
018
RI
10,000
fi(l
)10,000
I'
0-662
016
U
> R2!1
r,(p
'r
028_'r~~O
~-
...
1,800
IW ~
R20
0~::2
R
2200
'---
~T
>
C4
~ R23~
~
> RIB
> 10,000
IW
S 0~5
+
01
K
r...
...
010
..... p ..
cr670
:;:
0~:J2"
~~
~8
>'~
~
022,0
0-662
L~
P'
~3
.....J
03
2NI30!1
"--'
M
"--'
RI2
10,000
'" -2200
P'
H
>
IW
~
0~~!2 "
0~~~2"
~~
"------'
F
K:
L-----4
R21
120,000 >
+10 V (8)
.--
>
> RI4
RI!I
120,000
RIO
~
~
\.!!.
'r
O!l
0-6 62
06
0-66 2"
RB
120,000
~
~A+IOVIA)
-oB+IOV(B)
>r~
:'~tvf> ~>.RI3
'~'> ~ 68,000
'>"Mr:'
>,RI7
>~
..--
,]24
n'
> R27
6~~~~«
'>R31
':J@.O
r--
.000, :>68,000
05
08
•
68,R4oool
•
~ ~~!I%"""-28-:;~~=-:-C'--IH-~-R-(&o-t-+~-~"""2-~-~-""""~-:~~f.~4:-C-~""""""'-2-~~A..::'C:-t---H:se:-R-:~-0+-tI-~""'2--N-99~-9"""-+0-OE=-7C-~""''''''''-2-8~~~~C''''''''-+<-l:>68-R-b-7-+-+I-~~2-:r~-13-0-9"""++--oO
~ 2894-1
~~
L..C2
R7
>
3~00>
'1'" 120
%?
'n
'-
h
R8
1,5O<1c>
!I%;>
*.~5
,1,000
--'
1..1
~: .~
j~03
> RI
~
2894jl,
.W;
.l,CB
MFO
120
TI
DEC
PI"\)
~
'-'
,CT
2037
RI2 •
~<
•
~~
RZI
3,000>
5% >
RZ2
h
I~; ~
,~--
% >
__
~~ II~'
":,.~
~
04~ ~
3000
I ~ 5%
R~
.~09
,t1
~~> I~ ~
~
06 ~\~&
?" 5%
R
I,5
5%
UNLESS OTHERWISE IN ICATEO
RESISTORS ARE 1/4W,10%
CAPACITORS ARE MMFO
DIODES ARE 0- 664
~zg>
5'Mo~
II2W"
5'Mo
1/2 W
>.RI9
>I,~oo
~ 5%
< R25
<:80'"
~ II2W,5% ,
• R20
• 1,500
"i
5'"
U!!!!!I!!!I)l!!!!!:!!!
Drum Y Select RS-4531
Pulse Amplifier RS-4604
7-64
1,
>
.l,CI4
120
we..l~
R2~.>I~ ~T
010. ~
RI!!
~~-
MFO ...
T2
DEC
T2037
D""~ II~'
'H~
1
::: 289
R35
3,000,)
5% ?
~
D
013.~
A~015
~ R29
R36
iCI7
MFO
,1,000 T3
DEC
__
iT2037
DO' ~:IIFV
~
R40,) 11)1
_ CI9
'021 M9JO
0-682
~~i~
"1
~~
016h
~ 3~
...--
~6t8- ~~~
h
t,SOO~;
5'Mo.
GNO
~
R4~.
,--
~
•
r----
~
1/2W
(R32
< R34
5%
5'"
< I,~OO < 1,500
< R39
<
~ ~ 43
IBO
?1/2W,5%
3000
5 %
C-15V
01
CI 330
- IN
E
0··003
o-j ~--._-,
A
r------------------~--~~~~----_..----------------------~~~~--4_----~----------------~+~(A\
r--------------------;--------~----_+.~--------------------~--------~----~~--------------~~IOV(B)
o
R5
3,OOQ
5%
RI2
R34
R52
3,000
1,500
5%
~
~
~
~~~~~~----~-4--~------------~--~~~~~~--~~-~------~--------~--~4_~~--4_--~~4_--------------~-I5V
LEVEL
IN
UNLESS OTHERWISE INOICm-EO'
~~~i~W~~s A:iE I~~~~O%
TRANSISTORS ARE DEC2894-1
DIODES ARE 0-664
FLIP
CHIP
SYSTEM
MODULE
SOCKET
PLUG
A 0------0 A
08
80------0C
Co---E O------OE
F O-----0F
HO-----OH
J o-----OJ
K O-----0K
L o-----oL
MO-----<>M
No------oN
PO-----OP
Ro-----oR
So-----oS
To------o-r:
U 0------<) U
V 0-----<> V
w
Pulse Amplifier RS-4606
FLI P CHI P Adapter RS-4912
7-·65
+IOV (AI
T:A
CI3
.01
MFD
.01
MFD
0
GND
CI2
DI
MFD
015
012
0-662 0-662
CI
56
010
017
0-662 0-662
CII
.01
MFD
R7
1,500
5%
RI6
1,1100
11%
~--------~--------~--------~--------~--------~--------~--------~--------~--------~----~--~--~--~--~C
-1l5V
UNLESS OTHERW ISE INDICATED
f'ESISTORS ARE 114 W, 10%
CAPACITORS ARE MMFD
TRANSISTORS ARE DEI: 2894-1
DIODES ARE 0-664
---------------------c:. u
Q
......
::J:
........
I
z ........
;:).>
I:
1'(
..
N
--------------------~----------------------------------------------------OA+~VW
r------------------------4------------------------~--------------------------~8+IOV~
--~----------------~------._----------------+_----~~------~--~--~--oO
GND
030
0-662
02t
0-662
021
0-662
CII
M~O
021
0-662
04
017
Oil
C6
01
023
FO
wu---tlll---.
03
M
02
01
010
16
Tv---t..--t
09
R3
1,500
5%
07
22
Dill
014
021
020
OM
RI
12,000
UNLESS OTHERWISE INDICATED:
~~~~JOMEAc:8~:W, 10%.
TRANSISTORS ARE DEC 2894-1
~--------------+-----~~--------------~~----~----------------~------~----------~~~~_oC-ISV
~!~!!U!!!!!l!!!~!:!!!
Inverter RS-6102
Diode RS-6115
7-66
'
4 4
CI
56
RI
3,000
C2
F
5l--
OEC2894-1
ol~S6
L02
DEC 2894-1
R2
K
E
C5
1$6
C3
3POO
R5
3POO
P
o
R03
EC2894-1
V
4
4
R8
U
J
DEC2894-1
3POO
...-------......
T
.....
--.----t_-------e---
--oB-15v
-3V
01
02
0-664
R3
0-664
I,!IOO
R4
R6
I,!IOO
~soo
C4
1
MFO
H
M
D6
0-882
05
0-662
C8
.01
MFO
04
0-662
~--~~----e---~c
GNO
r---.----------------~.--------~----------------------OA+IOV(A)
r------------+---------+----------~---------QC
D4
IN 964 A
R2
7,500
GNO
R6
3,000 07
Q2
TRIMPOT
BOURNS
DEC 2894- 21
03
RI
5,000
• 01
114M 6.8 AZ5
R3
68,000
10%
R4
61300
10%
R5
1,000
-4'--------------------------0 B - 15 V
UNLESS OTHEI~WISE INDICATED:
RESISTORS ARE 114W, 5%
DIODES ARE Ct-664
Inverter RS-B104
NOTE: 1 N964A -13v I 10%
Low Voltage Detector RS-W505
7-67
APPENDIX 1
TELEPRINTER SUBROUTINES FOR
PDP-4
The diagnostitc test given as a corrective maintenance tool in Chapter 6 is for use with a PDP-4 computer
wh ich has the following standard subroutines stored in core memory. The routines allow automatic printing
of test results on the Type 65 Printer-Keyboard. These routines are presented here to allow generation of
a binary tape to store them in the PDP-4 if they are not present, or to allow comparison to determine the
extent of modifications required in the diagnostic prclgram to allow it to function with existing subroutines.
/TElETYPE SUBROUTINES, OCTAL AND DECIMAL FRACTIONAL PRINTS
/TURNS INTERRUPT OFF
/OCTAl PRINT, WITH ZERO SUPPRESSION
/FORMAT
lAC WD
/
TWORDZ
/
n
/n=NUMBER OF DIGITS TO PRINT FROM
/lEFT END OF WORD
OCTAL
TWORDZ=JMS
o
DAC DCPNUM
lAC (SZA)
DAC TWORDZ+ 17-JMS
LAC I TWORDZ-JMS
CMA
DAC DCPCNT
ISZ DCPCNT
ISZ TWORDZ-JMS
LAC DCPNUM
RTL
RAL
DAC DCPNUM
RAL
AND (7)
SZA
/MODIFIED
JMP TWORDZ+25-JMS
A 1-1
ISZ DCPCNT
JMP TWORDZ+ ll-JMS
TDIGIT
JMP I TWORDZ-JMS
DAC DCPDTG
LAC (JMP TWORDZ+31-JMS)
DAC TWORDZ+17-JMS
LAC DCPDIG
TDIGIT
ISZ DCPCNT
JMP TWORDZ+ll-JMS
JMP I TWORDZ-JMS
/OCTAL PRINT, NO ZERO SUPPRESSION
IFORMAT SAME AS TWORDZ
TWORD=JMS
a
DAC DCPNUM
LAC TWORD-JMS
DAC TWORDZ-JMS
LAC (JMP TWORDZ+31-JMS)
JMP TWORDZ+3-JMS
ITABLE FOR OCTAL TO DECIMAL CONVERSION
DECIMAL
DCPTAB,
100000
10000
1000
OCTAL
ITELETYPE OUTPUT PAC KAGE 0-1 9-26-62
EXT=JMP I-JMS
TTAB=lO
ITYPE 1 CHARACTER FROM AC BITS 12-17
TY1=JMS
a
RAR
JMS Ty'lA
EXT TYl
ITYPE 1 CHARACTER (5 BIT), L~ N KIN DICATES CASE
Al-2
100
10
TY1A,
o
DAC T'E"MY
AND (37
SNA
JMP TY2
lAC OCl
SPl
lAC OCU
SAD OCS
JMP .3
JMS OTY
DAC OCS
lAC TEMY
JMS OTY
ISZ TaC
TY2,
lAC TEMY
JMP I TY1A
/TYPE 3 CHARACTERS FROM AC 0-5, 6-11, 12-17' RESPECTIVELY
TY3=JMS
o
JMS R16
JMS TY1A
JMS R16
JMS TY1A
JMS R16
JMS TY1A
EXT TY3
/TYPE A CARRIAGE RETURN, AND LINE FEED
TCR = JMS
o
lAW 2
JMS OTY
LAW 10
JMS OTY
DZM TBC
EXT TCR
Al-3
/TELETYPE OUTPUT PACKAGE - PAGE 2
/TYPE A SPACE
TSP=JMS
o
LAW 4
JMS OTY
ISZ TBC
EXT TSP
/TYPE A TABULATION
TYT=JMS
TAB=TYT
o
LAC TBC
ADD (-TTAB-1
SMA
JMP .-2
ADD (1
SMA
LAC (-TTAB-1
ADD (-1
DAC TEM
TSP
ISZ TEM
JMP .'-2
EXT TYT
/TYPEWRITER INITIALIZE
TIN=JMS
o
LAC OCL.
DAC OCS
JMS OTY
TCR
EXT TIN
/TYPE THE DIGIT IN THE AC
TDIGIT-JMS
Al-4
o
AND (17
ADD (LAC NCT
DAC • 1
XX
TYl
EXT TDIGIT
/TELETYPE OUTPUT PAC KAGE - PAGE 3
/TYPE A STRING OF CHARACTERS
TSR=JMS
o
DAC TEMYl
LAC (JMP TSR 1
DAC TY1A 4
LAC I TEMYl
TY3
ISZ TEMYl
JMP .-3
TSR1,
LAC (JMP TY2
DAC TY1A 4
LAC TEMYl
EXT TSR
/OUTPUT ONE FIVE-BIT CHARACTER
OTY,
o
IOF
DAC TWORD-JMS
/SAVE
LAW
/COUNTER
DAC R16
LAC TWORD-JMS
TSF
SKP
JMP .+3
ISZ R16
JMP .-4
TLS
JMP I OTY
/ROTATE LEFT 6
R16,
0
RTL
RTL
RTL
JMP I R16
/TABLE OF DIGITS
NCT,
33
73
63
41
25
3
53
71
31
7
/CASE STORAGE
OCU,
33
OCL,
37
OCS,
0
/DECIMAL FRACTIONAL PRINT SUBROUTINE
fUSES TELETYPE OUTPUT PAC KAGE
/SUPPRESSES UNNECESSARY ZEROS
/FORMAT
LAC NUMBER
/
DECFR
/
X
/NUMBER OF DECIMAL PLACES (0-6)
DECFR=JMS
o
SMA VCCL
CMA
vell
/MAKE WORD NEGATIVE
DAC DCPNUM
LAW CHAR R
/SPACE
SZL
LAW CHAR R-
/MINUS
TY1
LAC (ADD DCPT AB)
DAC DEC FR 1+2
LAM -5
DAC DCPCNT
LAC I DECFR-JMS
ISZ DECFR-JMS
/-5
ADD .-4
Al-6.
DAC DCPCNl
SMA
/WR ITE I NIT IAL ZER 0
JMP DECFR6
LAC (SZA)
DAC DECFR2
DZM DCPDTG
/VALUE COUNTER
LAC DCPNUM
JMP .+3
DECFR1,
DAC DCPNUM
ISZ DCPDIG
ADD DCPTAB
/MODIFIED
SPA
JMP DECFRl
ISZ DECFR1+2
LAC DCPDIG
DECFR2,
SZA
/MODIFIED TO JMP DECFR3
JMP DECFR3
ISZ DCPCNl
JMP DECFR5
CLC
DAC DCPCN1
CLA
DECFR3,
TDIGIT
ISZ DCPCNT
SKP
JMP I DECFR-JMS
DECFR4,
LAC DECFR2+1
ISZ DCPCN1
JMP DECFRl-4
LAW CHAR R.
/PERIOD
TY1
JMP DECFR4
DECFR5,
ISZ DCPCNT
JMP DEC FR 1··2
TDIGIT
/SHOULD NEVER REACH HERE
Al-7
JMP I DECFR-JMS
DECFR6,
CLA
TDIGIT
JMP DEC FR4+3
START
Al-8.
APPENDIX 2
TELEPRINTER SUBROUTINES FOR PDP-1
type 24 drum test - pdp 1- 11 dec 64
define
rcr 777
rcr 777
term
swap
define
isp A
jmp B
term
count A,B
define
law i B
dac A
term
setup A,B
/octal typeout - suppresses leading zeros
/calling sequence: lac number, jda opt
100/
opt,
0
dap opx
setup op2,- 6
stf 1
opl,
szf i 1
tyo
lio opt
cla
rcl 3s
dio opt
sza
clf 1
sza i
law 20
swap
count op2, opl
tyo
opx,
jmp
.
ott,
0
dap ot1
setup op2,6
ot2,
lio ott
cla
rcl 3s
dio ott
sza i
A2-1
law 20
swap
tyo
count op2,ot2
ot1,
jmp •
/drum test 3
beg,
jmp rng-3
law pta
dac pha
clf 7
law 1 10
dac cfF
szs 10
jsp tst
jsp spd
jmp wrl
boo,
jmp .-3
law 1 2
dac ctr
stf 4
rng,
dzm wat
rbI,
dac t'iii3
rcn,
dac rnu
dac 1 tm3
Idx tm3
sas wrn
jmp rcn
110 wca
dwr
110 wdt
dbl
jsp wtl
e1,
jsp wtl
e2,
110 rca
drd
110 rdt
dbl
jsp wtl
e3,
jsp wtl
e4,
Id.x rdt
sas drs
jmp rbl
szs 40
jmp rng
lsp ctr
jmp rng
jmp beg
szs 40
lsp ctr
dzm rat
lac wca
jsp rad
dcn
Id.x wdt
dcn
jsp rcm
A2-2
rad,
lac
lio
rcr
xor
dac
dio
b,
dap b
hi
/random number generator routine
10
7s
10
10
hi
jmp
wtl,
dtd
jmp .-1
dse
jmp par
wtx,
dap wtx
/test for drum done
rcm,
lac
dac
lac
dac
law
dac
rdd,
sas
jsp
idx
idx
sas
jmp
szf
jmp
rcx,
big,
sas
jsp
idx
idx
sas
jmp
jmp
dap rcx
'W'ca
tm3
rca
tm6
1. 6
opp
/test for errors after transfer
jmp
/data error test routine
/initialize for limited error printouts
lac i tm6
1. tm3
ert
tm6
tm3
wrl
rdd
4
big
/random number routine?
jmp
lac i tm6
i tm3
ert
tm6
tm3
wrn
b1.g
rcx
/done with second block yet?
tst,
hIt
lat
dac tml
hIt
lat
dac dta
tsx,
dap tsx
spd,
lac
dac
dzm
lio
dio
idx
dap spx
/routine to use TW switches for data
jmp
wca
tm2
dta
dta
i tm2
tm2
A2-3
mdo,
szs 10
110 trn1
d10 1 trn2
Idx trn2
sas wrl
jrnp .-3
spx,
110 1 pha
wr1,
jrnp
dzrn
goo,
dwr
110
db1
jsp
szs 10
e5,
jrnp
/wr1te rout1ne
goo
dta
110 wca
dta
/load track address and go
wt1
szs 20
jrnp
1dx
szs
jsp
dac
sas
jrnp
jrnp
tsw,
lat
dac
tax,
rea,
jrnp
dzrn
lac
dac
doo,
drd
110
dbl
jsp
rea
dta
10
tsw
1 wca
drs
goo
rea
dap tax
dta
jmp
szs 20
doo
dta
dta
1 wca
110 rca
dta
wtl
e6,
/start read1ng
jsp rcm
1dx
szs
jsp
szs
jrnp
dac
sas
jmp
1dx
jrnp
dta
20
tsw
10
wr1
1 wca
drs
doo
pha
boo
/error rout1ne
A2-4
par,
szs 30
jmp wtx-2
dsp
jmp prt
lio (flexo par
repeat 3,ril 6s
jmp pr1
prt,
lio (flexo mis
repea.t 3,ril 6s
pr1,
lac wtx
and (7777
jda opt
lio (36
tyo
lac wtx
and 4(7777
szf
jmp pr2
lac dta
jmp pr3
pr2,
sub (e3-1
spa
/skip if e3 or e4
jmp pr4
lac rdt
jda opt
pr3,
lio (77
tyo
jmp wtx
pr4,
lac wdt
jmp pr3
ert,
szs
jmp
lio
tyo
rir
tyo
lac
szf
lac
jda
lio
tyo
lac
and
jda
lio
tyo
/parity error
tyo
/mi:3s error
tyo
/prlnt out the err loc
dap erx
30
erx
(7734
68
dta
4
rdt
opt
(36
/track address
/random routine?
tm6
ran
opt
(36
/word number
md2,
szs 10
lac
jda
lio
tyo
rir
tyo
lac
jda
/swrpress printout
tm1
ott
(3635
lac i tm3
/get data word written
68
i tm6
ott
/drum word
A2--5
szs i 60
jmp • 4
isp opp
jmp • 2
xx
erx,
/eonstants
wea,
wrl,
wrn,
rca,
reI,
drs,
pto,
ptl,
pt2,
pt3,
pt4,
pt5,
pt6,
pt7,
pha,
ran,
hi,
10,
/pritn out more than 6 errors?
jmp •
2000
2400
3000
4000
4400
1000
777777
000000
111111
222222
333333
444444
555555
666666
pto
777
365273
141053
dwr=721161
drd=720161
dbl=720162
dse=720164
dtd=720163
den=721162
dsp=721164
constants
variables
start beg
A2-6
APPENIDIX 3
SERIAL DRUM TYPIE 24 INTERFACE
WITH
PDP-7 COMPUTER
For adaptation of some peripheral equipment the PDP-7 computer has a special adapter panel shown in
Figure A3-1.
PDP-7.
Figure A3-2 details the conversion circuits for connection of Type 24 Drum signals to the
The interface tables that follow detail all computer and drum connections to the interface panel.
TABLE A3-1
Color
Pin
WHT
3G11-R1-C
WHT
3G11-R1-E
2
WHT
3G11-R1-G
3
WHT
3G11-R1-J
WHT
Pin
SERIAL DRUM 24D JACK F1 TO ADAPTER PANEL. PLUG.J1
Name
Color
Pin
Pin
DFBO--•• MBO
WHT
3G11-R2-V
18
DFB
WHT
3G4-F
19
MBB
2
WHT
3G4-J
20
4
3
WHT
3G4-L
21
2
3G11-R1-L
5
4
WHT
3G4-N
22
3
WHT
3G11-R1-N
6
5
WHT
3G4-R
23
4
WHT
3G11-R1-R
7
6
WHT
3G4-T
24
5
WHT
3G11-R1-T
8
7
WHT
3G4-V
25
MBB 6 -____
.DF 6
WHT
3G11-R1-V
9
8
WHT
3G4-X
26
MBB7
WHT
3G11-R2-C
10
9
WHT
3G4-Z
27
8
WHT
3G11-R2-E
11
10
WHT
3G5-F
28
9
WHT
3G11-R2-G
12
11
WHT
3G5-J
29
10
WHT
3G11-R2-J
13
12
WHT
3G5-1
30
11
WHT
3G11-R2-L
14
13
WHT
3G5-N
31
12
WHT
3G 11-R2-N
15
14
WHT
3G5-R
32
13
WHT
3G11-R2-R
16
15
WHT
3G5-T
33
14
WHT
3Gll-R2-T
17
16
WHT
3G5-V
34
15
A3-·1
Name
17
_ _".MB
O
.. DFO
.. DF7
17
----
~
-
.-
3G
0
,
2
3
4
5
6
r--
r--
r--
r--
r--
•
HOA
0
w
a:
w
a:
e/)
e/)
: :
Fa
~
t •t
0
CD
CD
e/)
e/)
W
CD
0
0
I&.
I&.
....
~
CD
t
-- -
0
CD
CD
C(
CD
CD
2
- 2
0
-15
10
0
CD
2
.t t .t t
12
11
.-
CD
u
~
a:
w
I&.
I&.
t t.t
•
t •t •
2
9
~
,
,,
a:
::)
C(
8
7
CD
~0
I-
+108
0
•
~
w
a:
i
f.-
w
a::
f
e/)
•
CD
2
e/)
i
lIS
-'
0
a:
l-
~
u
0
;:::
o.
CD CD
22
.t::
14
N •
C(C(
.-
N
w
a:
:
e/)
• t::
~
t
•
u-'
0
w
a:
0
1 f.-
:en
•
t
tt tt
o . -'-'
1&.1&.
16
•
u-'
22
N
15
t
11 1f
00
FigUie A3-1
13
.-
•
•
u
C(
U
C(
00
J2
J1
;
N
uu
...
21
PDP-7 to Type 24 Drum Adapter Panel
r----------------------------------~
i
,
l.
I
~MBBOl~f}
E
M8BO(O
F
H
-
MBB9(1)
-=
4:MBB9I1~)
E
L __
M88
K 1 [ (L* )
M882(1)
-=
1,1
J
MB81(1l
F
H
M881O(1)
J
MBB2I(~) MB831(~) MBB41(~)
M
N
MB83(1)
-=
-=
-= ___ __ _= ___
MU
BB51(
ST
V* )
R
M885(1)
6102
P
R
~~~_=
M886(1)
y
z
MBB8(1)
-=
':'
_uu
I
~
MBB161~11.-mJ
M88131*') M8814*11) M8815*11)
STU
V
W
x
MB815(1)
MBB16(1)
MBB17(1)
MB814(1)
y
z
I
I
___ ~ __ _= ___ ~ __ _= __ _.J
PA
4604
A3
~s
-DATA
ADO
-+ MA(8)
"---...,j
Figure A3-2
x
W
':'
DATA
ADOiN
--+ MA
T7
MB86I(~) MBB71(~)
M887(1)
-=
':'
~:'4:')
MB81014:'1 MBB1114:')
K
L
MN
M8812(1)
MB813(1)
MB811(1)
~
P
M8M(1)
l
Type 24 Drum Interface to PDP-7
T
+
TABLE A3-1
SERIAL DRUM 24D JACK F1 TO ADAPTER PANEL PLUG J1 (continued)
Color
Pin
Pin
Name
Color
Pin
Pin
Name
WHT
3G5-X
35
16
WHT
3G12-R2-G
43
11
WHT
3G5-Z
36
MBB17
WHT
3G12-R2-J
44
12
WHT
3G12-R1-N
37
DCLB
WHT
3G12-R2-L
45
13
WHT
3G12-R1-R
38
6
WHT
3G12-R2-N
46
14
WHT
3G12-R1-T
39
7
WHT
3G12-R2-R
47
15
WHT
3G12-R1-V
40
8
WHT
3G12-R2-T
48
16
WHT
3G12-R2-C
41
9
WHT
3G12-R2-V
49
DCLB 17
WHT
3G12-R2-E
42
10
BLK
GNDLUG
40
GND
TABLE A3-2
Color
Pin
Pin
"-DF
5
17
.. MA
5
17
SERIAL DRUM 24F JACK J2 COMPUTER SIDE
Name
Color
2
ACB
.MA
2
2
Pin
Pin
Name
WHT
3G16-Rl-J
13
12
WHT
3G16-R1-L
14
13
WHT
3G16-R1-N
15
14
WHT
3G15-R1-G
3
WHT
3G15-R1-J
4
3
WHT
3G16-R1-R
16
15
WHT
3G15-R1-L
5
4
WHT
3G16-R1-T
17
16
WHT
3G15-R1-N
6
5
WHT
3G 16-R1-V
18
ACS
WHT
3G15-R1-R
7
6
WHT
3G10-R2-G
19
DRUM FLAG
WHT
3G15-R1-T
8
7
WHT
3G10-R2-J
20
PEO·DEO
WHT
3G15-R1-V
9
8
WHT
3G 1O-R2-L
21
DATA REQ
WHT
3G16-R1-C
10
9
WHT
3G10-R2-N
22
DATA IN
WHT
3G16-R1-E
11
10
WHT
3G12-R1-G
23
DeL
WHT
3G16-R1-G
12
11
WHT
3G 12-R1-J
24
DCl
.DCL
A.3-3
17
2
3
... DCl 17
"MA
.MA
2
3
TABLE A3-2
Pin
Color
Name
Pin
Pin
Color
SERIAL DRUM 24F JACK J2 COMPUTER SIDE {continued}
Name
Pin
======r===========--=··-=-==-=·--=--::"-=-=='::::.=c.
3G 12-R 1-L
WHT
25
DCL 4_--.... MA
4
39
26
40
27
41
28
29
30
31
GRY l TWP
BLK (
3G3-S
42
DATA REQ AN5
GRYlTWP
BLK (
3G10-R1-N
43
BEGIN
GRY l TWP
BLK (
3G3-J
44
T7B
GRYlTWP
BLK (
3G10-R1-C
45
lOT
GRY l TWP
BLK (
3G10-R1-E
46
lOT
GRY l TWP
BLK (
3G10-R1-G
47
lOT
GRYlTWP
BLK (
3G10-R1-J
48
lOT
GRY l TWP
BLK (
3G10-R1-L
49
lOT
32
33
34
WHj TWP
BLK
3G10-R2-C
35 TEMP:,W (T A)
3G10-R2-E
36
TA GND
37
RED
3G10-R2-R
38 +10 MC
.-------------_.__.__......•._..
TABLE A3-3
Color
BLK
_...-
--~
.
GND
50 GND
----------.-------.---
SERIAL DRUM 24D INTERFACE COMPUTER SIDE MB INVERSIONS
Name
Pin
Pin
.=========
___====--===c.:_---..=-...:=-c:·=::.c==c:_ _ _ _ _ _ _ _ ...
Remarks
__ .._ ...._... _._ ......._. __... __ ._..
---=. ::-:..-=
WHT
3G6-R1-C
3G4-E
BUSS PINS
WHT
3G6-Rl-E
3G4-H
B, 0, F, H, K, M,
WHT
2
3G6-Rl-G
3G4-K
P, 5, U, & W to
WHT
3
3G6-R1-J
3G4-M
GROUND.
WHT
4
3G6-R1-L
3G4-P
A3-4
~
TABLE A3-3 SERIAL DRUM 240 INTERFACE
COMPUTER SIDE MB INVERSIONS (continued)
Color
Name
Pin
Pin
WHT
5
:3G6-Rl-N
3G4-S
WHT
6
:3G6-Rl-R
3G4-U
WHT
7
:3G6-Rl-T
3G4-W
WHT
8
:3G6-Rl-V
3G4-Y
WHT
9
:3G7-Rl-C
3G5-E
WHT
10
:3G7-Rl-E
3G5-H
WHT
11
:3G7-Rl-G
3G5-K
WHT
12
:3G7-Rl-J
3G5-M
WHT
13
:3G7-Rl-L
3G5-P
WHT
14
~3G7-R1-N
3G5-S
WHT
15
:3G7-R1-R
3G5-U
WHT
16
:3G7-R1-T
3G5-W
WHT
1
MB17
:3G7-R1-V
3G5-Y
T7
3Gl O-R2-T
3G3-E
~IG1
3G3-N
DATA ADD
TABLE A3-4
Color
.. MA
0-R2-V
Remarks
I/O INFO FROM DRUM INTERFACE F10(R2) TO 1N10
Name
Pin
Location
Remarks
A
BLANK
B
BLANK
W/BLK
GND
C
W/BRN
lOT 6101
D
W/RED
GND
3G10-R2-C
M13K
3G1O-R2-D
--~,~---
A3-5
-
TABLE A3-4
I/O INFO FROM DRUM INTERFACE F10(R2) TO lN10 (continued)
Pin
Name
Color
Location
Remarks
W/ORN
lOT 6201
E
3G 10-R2-E
W/YEL
GND
F
3G10-R2-F
W/GRN
DRUM FLG.
H
3G10-R2-G
W/BLU
J
3G10-R2-H
W/VIO
K
3G 10-R2-J
M13N
L17U
W/GRY
GND
L
WHT
DATA REQ
M
3G10-R2-L
W/BLK
GND
N
3G10-R2-M
W/BRN
DATA IN
P
3G10-R2-N
W/RED
GND
R
3G 1O-R2-P
5
3G 10-R2-R
W/ORN
GND
W/GRN
T7
T
3Gl 0-R2-T
W/BLU
GND
U
3G10-R2-U
W/VIO
DATA ADD
v
3G10-R2-V
W/GRY
GND
Color
W/BLK
W/BRN
Pin
ACBl
L 16H
_ __
.....
Location
Remarks
A
BLANK
B
BLANK
C
<>ACB 0
W/ORN
K15N
ACB 0-8 FROM CPU TO DRUM INTERFACE
GND
GND
Ll8F
-_._-----_.. -._-----_._-- _. __.... - ... _.. _.._. __.._..•
Name
W/RED
M13L
3G10-R2-S
W/YEL
TABLE A3-5
M13M
D
E
A3-6
3G15C
R2
3G15D
R2
3G15E
R2
._ ..._--_ ..
__._-
TABLE A3-5
Color
ACB 0-8 FROM CPU TO DRUM INTERFACE (continued)
Name
Pin
Location
Remarks
W/VEL
GND
F
3G15F
R2
W/GRN
ACB 2
H
3G15G
R2
W/BLU
GND
J
3G15H
R2
W/VIO
ACB 3
K
3G15J
R2
W/GRY
GND
L
3G15K
R2
WHT
ACB 4
M
3G15L
R2
W/BLK
GND
N
3G15M
R2
W/BRN
ACB 5
P
3G15N
R2
W/RED
GND
R
3G15P
R2
W/ORN
ACB 6
5
3G15R
R2
W/YEL
GND
3G15S
R2
W/GRN
ACB 7
T
3G15T
R2
W/BLU
GND
U
3G15U
R2
W/VIO
ACB 8
V
3G15V
R2
W/GRY
GND
TABLE A3-6
Color
AC 9-17 FROM CPU TO DRUM INTERFACE
Name
Pin
Remarks
A
BLANK
B
BLANK
W/BLK
GND
C
W/BRN
ACB 9
D
W/RED
GND
W/ORN
ACB 10
W/YEL
GND
A~I-7
Location
3G16C
Rl
3G16D
Rl
E
3G16E
R1
F
3G16F
R1
TABLE A3-6
AC 9-17 FROM CPU TO DRUM I NTERFACE {continued}
Color
Name
Pin
Location
Remarks
W/GRN
ACB 11
H
3G16G
R1
W/BLU
GND
J
3G16H
R1
W/VIO
ACB 12
K
3G16J
R1
W/GRY
GND
L
3G16K
R1
WHT
ACB 13
M
3G16L
R1
W/BLK
GND
N
3G16M
R1
W/BRN
ACB 14
P
3G16N
R1
W/RED
GND
R
3G16P
R1
W/ORN
ACB 15
S
3G16R
R1
W/YEL
GND
3G16S
R1
W/GRN
ACB 16
T
3G16T
R1
W/BLU
GND
U
3G16U
R1
W/VIO
ACB 17
V
3G16V
R1
W/GRY
GND
TABLE A3-7
Color
Name
DFB 0-17 TO MB 0-17
Pin
Location
A
BLANK
B
BLANK
W/BLK
GND
C
W/BRN
DFB 0
D
W/RED
GND
W/ORN
DFB 1
E
3Gl1-R1-E
W/YEL
GND
F
3G11-R1-F
3Gl1-R1-C
3Gll-R1-D
A3-8
Remarks
TABLE A3-7
DFB 0-17 TO MB 0-17 (continued)
Color
Name
Pin
Location
W/GRN
DFB 2
H
3Gll-R1-G
W/BLU
GND
J
3G11-R1-H
W/VIO
DFB 3
K
3G11-R1-J
W/GRV
GND
L
3Gll-Rl-K
WHT
DFB 4
M
3Gll-R1-L
W/BLK
GND
N
3Gll-Rl-M
W/BRN
DFB 5
P
3Gll-Rl-N
W/RED
GND
R
3Gl1-Rl-P
W/ORN
DFB 6
S
3Gll-Rl-R
W/VEL
GND
~/GRN
DFB 7
T
3Gll-Rl-T
W/BLU
GND
U
3Gll-Rl-U
W/VIO
DFB 8
V
3Gl1-Rl-V
W/GRV
GND
Remarks
3G11-Rl-S
A
BLANK
B
BLANK
W/BLK
GND
C
W/BRN
DFB 9
D
W/RED
GND
W/ORN
DFB 10
E
3G 11-R2-E
W/VEL
GND
F
3G 11-R2-F
W/GRN
DFB 11
H
3Gl1-R2-G
W/BLU
GND
J
3Gll-R2-H
W/VIO
DFB 12
K
3G ll-R2-J
3Gll-R2-C
3Gl1-R2-D
A:3-9
TABLE A3-7
Color
Name
DFB 0-17 TO MB 0-17 (continued)
Pin
Location
W/GRY
GND
L
3G11-R2-K
WHT
DFB 13
M
3G11-R2-L
W/BLK
GND
N
3G11-R2-M
W/BRN
DFB 14
P
3G11-R2-N
W/RED
GND
R
3G11-R2-P
W/ORN
DFB 15
S
3G11-R2-R
W/YEL
GND
W/GRN
DFB 16
T
3Gll-R2-T
W/BLU
GND
U
3G11-R2-U
W/VIO
DFB 17
V
3Gll-R2-V
W/GRY
GND
TABLE A3-8
Color
Remarks
3G11-R2-S
MBB 0-17 FROM CPU TO DRUM INTERFACE
Name
Pin
Location
Remarks
A
BLANK
B
BLANK
W/BLK
GND
C
3G6B
Rl
W/BRN
MBB 0(1)
D
3G6C
Rl
W/RED
GND
3G6D
Rl
W/ORN
MBB 1
E
3G6E
R1
W/YEL
GND
F
3G6F
Rl
W/GRN
MBB 2
H
3G6G
R1
W/BLU
GND
J
3G6H
R1
W/VIO
MBB 3
K
3G6J
Rl
A3-10
TABLE A3-8
MBB 0-17 FROM CPU TO DRUM INTERFACE (continued)
Color
Name
Pin
Location
W/GRV
GND
L
3G6K
R1
WHT
MBB 4
M
3G6L
R1
W/BLK
GND
N
3G6M
R1
W/BRN
MBB 5
P
3G6N
R1
W/RED
GND
R
3G6P
R1
W/ORN
MBB 6
S
3G6R
R1
W/VEL
GND
3G6S
R1
W/GRN
MBB 7
T
3G6T
R1
W/BLU
GND
U
3G6U
R1
W/VIO
MBB 8
V
3G6V
R1
W/GRV
GND
Remarks
A
BLANK
B
BLANK
W/BLK
GND
C
W/BRN
MBB 9
D
W/RED
GND
W'/ORN
MBB 10
W/VEL
3G7C
R1
3G7D
R1
E
3G7E
R1
GND
F
3G7F
R1
W'/GRN
MBB 11
H
3G7G
R1
W/BLU
GND
J
3G7H
Rl
W/VIO
MBB 12
K
3G7J
Rl
W/GRV
GND
L
3G7K
Rl
WHT
MBB 13
M
3G7L
Rl
W/BLK
GND
N
3G7M
R1
TABLE A3-8
MBB 0-17 FROM CPU TO DRUM INTERFACE (continued)
Remarks
Color
Name
Pin
location
W/BRN
MBB 14
P
3G7N
R1
W/RED
GND
R
3G7P
R1
W/ORN
MBB 15
S
3G7R
R1
W/YEl
GND
3G7S
R1
W/GRN
MBB 16
T
3G7T
R1
W/BlU
GND
U
3G7U
R1
W/VIO
MBB 17
V
3G7V
R1
W/GRY
GND
TABLE A3-9
Color
Name
DCl 2-17 TO MA 2-17
Pin
location
A
BLANK
B
BLANK
W/BlK
GND
C
3G12-R1-B
W/BRN
Del
D
3G12-R1-C
W/RED
GND
W/ORN
DCl
E
3G12-R1-E
W/YEl
GND
F
3G12-R1-F
W/GRN
DCl2
H
3G12-R1-G
W/BlU
GND
J
3G12-R1-H
W/VIO
DCl3
K
3G12-R1-J
W/GRY
GND
l
3G12-R1-K
WHT
DCl4
M
3G12-R1-l
W/BlK
GNI)
N
3G12-Rl-M
3G12-R1-D
A3-12
Remarks
TABLE A3-9
DCl 2-17 TO MA 2-17 {continued}
Color
Name
Pin
location
W/BRN
DCl5
P
3G12-R1-N
W/RED
GND
R
3G12-Rl-P
W/ORN
DCl6
S
3G12-R1-R
W/YEl
GND
W/GRN
DCl7
T
3G12-R1-T
W/BlU
GND
U
3G12-R1-U
W/VIO
DCl8
V
3G12-R1-V
W/GRY
GND
Remarks
3G12-Rl-S
3G12-R1-W
A
BLANK
B
BLANK
W/BlK
GND
C
3G12-R2-B
W/BRN
DCl9
D
3G12-R2-C
W/RED
GND
W/ORN
DCl 10
E
3G12-R2-E
W/YEl
GND
F
3G12-R2-F
W/GRN
DCl 11
H
3G12-R2-G
W/BlU
GND
J
3G12-R2-H
W/VIO
DCl 12
K
3G12-R2-J
W/GRY
GND
l
3G12-R2-K
WHT
DCl 13
M
3G12-R2-l
W/BlK
GND
N
3G12-R2-M
W/BRN
Del 14
P
3G12-R2-N
W/RED
GND
R
3G12-R2-P
W/ORN
DCl 15
S
3G12-R2-R
3G12-R2-D
A3-·13
TABLE A3-9
Color
DCl 2-17 TO MA 2-17 (continued)
Pin
Name
location
W/YEl
GND
W/GRN
DCl 16
T
3G12-R2-T
W/BlU
GND
U
3G12~R2-U
W/VIO
DCl 17
V
3G12-R2-V
W/GRY
GND
TABLE A3-10
Color
Remarks
3G12-R2-S
3G12-R2-W
I/O INFO TO DRUM INTERFACE TO D16 DS
Name
Pin
location
A
BLANK
B
BLANK
W/BLK
GND
C
W/BRN
lOT 6002
D
W/RED
GND
W/ORN
lOT 6004
E
3G10-R1-E
W/YEL
GND
F
3G10-R1-F
W/GRN
lOT 6102
H
3G10-R1-G
W/BLU
GND
J
3G10-R1-H
W/VIO
lOT 6104
K
3G10-R1-J
W/GRY
GND
L
3G 10-R1-K
WHT
lOT 6204
M
3G 1O-Rl-l
W/BLK
GND
N
3G10-R1-M
W/BRN
BEGIN
P
3G10-R1-N
W/RED
GND
R
3G10-R1-P
W/ORN
lOT 6101
S
3G10-R1-R
W/YEL
GND
3G10-R1-C
3G10-R1-D
3G10-R1-S
A3-14
Remarks
TABLE A3-10
Color
I/O INFO TO DRUM INTERFACE TO D16 DS (continued)
Name
Pin
Location
W/GRN
lOT 6204
T
3G10-Rl-T
W/BLU
GND
U
3G10-Rl-U
V
W/VIO
W/GRY
GND
A3-15
Remarks
5536
PRINTED
IN
U.S.A
1.5-11/65
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