H 80 0444_Vistagraphic_3000_Graphic_8_Programmers_Reference_Feb_1981 0444 Vistagraphic 3000 Graphic 8 Programmers Reference Feb 1981
H-80-0444_Vistagraphic_3000_Graphic_8_Programmers_Reference_Feb_1981 H-80-0444_Vistagraphic_3000_Graphic_8_Programmers_Reference_Feb_1981
User Manual: H-80-0444_Vistagraphic_3000_Graphic_8_Programmers_Reference_Feb_1981
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H-SO-0444
Vistagraph]c7~il . 3COO/
Graphic 8™
COMl=UTS}:; GJ:2APH1CS
CIS1=1.A Y SYSTEM
SS~I15S axcc
S=~OGRAMMEJ:;'S R5Fe~SNC5
MANUAL
FESJ:;UA~Y
CALCOMP
A Sancers Gracncs CJmcany
~SANDERS
(,JOYf1gnr 1~81 Sancers ..4SSoc :3ces. rc
,:j r 3cn :c S IS a uacemark or Sanaers ":'sscc :ac;!s. ' nc o
\" ! stagraon~c .S 3 'r~aeman~ or ·":a:Cvmo
1981
H-90-0444
,
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Vista
raphic™ SOC : /
Graphi,c a™
COI'JII=UTER GRAJ:JHICS
CISPLA Y SYSTEM
SERIES
exoc
PROGRAMMER'S REFERENCE MANUAL
FEBRUARY 1981
CALCOMP
A Sanders GraphICS Company
~SANDERS
COPYright 1981 Sanders Assoc[ates, inc.
GraphIc 8 [5 a trademark of Sanders Assoc[ates, Inc.
V[stagraphlc [s a trademark of CalComp
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Sanders Associates,Inc. reserves the right to make corrections or alterations
to this manual at fny time without notice.
~
Original issue: February 1981
Reprint: August 19~1
Reprint: November L981
.-.;\~....
- -
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-
Reprint: February {gaZ
Reprint: AprU 198Z
Change 1:, September 1982
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Reprint: September" 1982
Reprint:
January 1983
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RECORD OF CHANGES
CHANGE NO.
1
DATE
Sept 82
TITLE OR BRIEF
OeSCRIPTION
Correct errors, general
update
ENTERED BY
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TABLE OF CONTENTS
Section
1
Page
GRAPHIC 8 SYSTEr1 DESCRIPTION
1.1
1.2
1. 2.1
1.2.1.1
1.2.1.2
1.2.1.3
1.2.1.4
1.2.1.5
1.2.1.6
1.2.1.7
1.2.1.8
1.2.1.9
1.2.1.10
1.2.1.11
1. 2.1.12
1. 2.1.13
1. 2.2
1.2.2.1
1.2.2.2
1.2.2.3
1. 2.3
1.2.3.1
1.2.3.2
2
Introduction
Component Description
Terminal Controller
Display Processor
Read/Write Memory
ROM/Status Logic
Multiport Serial Interface
Parallel Interface
Digital Graphic Controller
Video Controller
Mapping Memory
Timing Module
Charac ter Generator
2-o/3-D Coordinate Converter
Data Converter
EPROM Expansion Module
Input Devices
Keyboards
Trackball, Forcestick, and Data Tablet
Maintenance Data Input Devices
Output Devices
Display Moni tors
Hardcopy Units
OPERATING MODES
2.1
2.2
2.2.1
2.2.1.1
2.2.1.2
2.2.2
2.2.2.1
2.2.2.2
2.2.2.3
2.2.2.4
2.2.2.5
2.2.2.6
General
Local Mode
Verification Test Pattern and Diagnostics
Hardcopy Generation
Data Tablet Testing
Lo cal Me d e Command s
Memory Commands
Displaying a Refresh File
Transfer of Program Control
Transfer to System Mode
Teletypewriter Emulation
Additional Local Mode Commands
1-1
1-1
1-1
1-4
1-4
1-4
1-7
1-7
1-7
1-8
1-8
1-8
1-10
1-10
1-10
1-11
1-11
1-11
1-11
1-12
1-12
1-12
1-12
1-12
2-1
2-1
2-1
2-3
2-6
2-6
2-6
2-8
2-8
2-9
2-9
2-9
2-9
)
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TABIoE OF CONTENTS (Cont)
Page
GRAPHIC 8 INSTRUCTIONS
3-1
3.1
.3.2
3.3
3.3.1
3.3.1.1
3.3.1.2
3.3.1.3'
3.3.1.4
3.3.1.5
3.3.2
3.3.2.1
3.3.2.2
3... 1
.3-1
3-2
3.3.2.3
3.3.2.4
3.3.2.5
3.3.3
3.3.4
4
5
General
Display Processor Instruc tiona
.
Digital/Graphic Controller Instructions
Pi:lCel Po si eion Instruc tions
toad Instructions
Move Instructions
Draw Instructions
'text Instruc: tions
ConiC: Instructions
Sequence. Control Instruc tions
tTncondi tional J'tllllP Ins true tions
Conditional Jump Instructions
Subroutine Instructions
Linkage Instruction
Halt and 'W'ait Instructions
Register Instructions
Display Control Instructions'
3-3
3.... 3
3-4
3-.5
3-9
3-11
3-12
3-12
3-14
3-15
:3-19
3-20
3...22
3-25
GaAPHIC 8 REGIsTERS
4-1
4.1
4.2 .
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.4
4.4.1
4.4.2
4-1
4-1
General
Display Processor Registers
Digital Graphic Controller Registers
Processor Registers
Function Registers
Sense and Mask Registers
Function Conttol Registers
Display Control Registers
Configuration Registers
Interface Bagi.sters
Serial Interface Registers
Parallel .Interf4ce kgisters
4-1
4-2
4-4
4...14
4-16
4-17
4....21
4-22
4-23
4-32
GRAP1UC CONTROLPROGaAM (GCP)
5-1
5.1
5-1
5... 2
5-2
5-6
5-6
5-6
5.2
5.2.1
5.2.2
5 .. 3
5.3.1
5.3.2
3 • .3.3
5.3.4
5.3.5
5.3.6
Description and Purpose
'. Host/GRAPHIC 8 C01llll1uuic.ations
Sedal Interface COmmunications
Parallel Interface Counnunieations
Host/GRAPHIC 8 MeSsages
Initialize and Error Messages
Establish I/O Transmission Mode (Polling/
Non-Polling)
. Memory Related Messages
Interrupt Related Messages
Keyboard Related Messages
Positional Entry Device Related Messages
5-11
5-16
5-27
5-33
5...40
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TABLE ;OF CONTENTS (Cont)
Page
Section
5.3.7
5.3.8
5.3.8.1
5.3.9
5.3.9.1
5.4
6
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5-72
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6-1
6-1
6-1
6-1
6-1
6.S
7
5-68
6-1
6.3.1
6.3.2
6.3.3
6.4
6.4.1
6.4.2
;
5-49
5-53
5-63
5-67
GRAPHIC CONtROL PROGRAM USAGE
6.3
'r:
Extended Device :Control Message
Fortran Support~(FSP) Messages
Packed Vector Mode
Option Support
Option Messages,
Programming the ';3-D Coordinate Converter
General
Startup Procedures
GRAPHIC 8 Turned On Aft'er Host Computer
GRApHIC 8 Turned On Before Host Computer
Power Failure Startup
Startup with GRAPHIC 8 in Teletypewriter Ettlulation
Mode
Refresh Files
Refresh File Generation
Refresh rile Transmission
Refresh File Alteration
Optional Equipment Usage
Keyboards
PEDs
Multistation Usage
6-2
6-2
6-2
6-6
6-7
6"'8
6-8
6-10
6-11
ADVANCED GRAPHIC CONTROL PROGRAM USAGES
7-1
7.1
7-1
7-1
7-2
7-4
7-4
7-7
7-7
7-8
7-8
7-1i
7-16
7-16
7-16
7-17
7-18
7-18
7-18
7-18
7-19
7-10
7.2
7.2.1
7.2.2
7.2.3
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.4
7.5
7.5.1
7.5.2
7.6
7.6.1
7.6.2
7.6.2.1
7.6.2.2
7.6.2.3
Introduction
RAM Linkages
Unknown Command Reader Sent by Host Computet
Beginning of GCP Executi'l1e Loop
Message Ready to Send to Host Computer
Link !nstruction
Basic Instruction Operation
Synchronized Linkage
Sync Unk
Super Sync
The Digital Graphic Controller as a Device
The Parallel Interface as a Device
Programming Examples
Interrupt Operation
The Serial Interface as a Device
ROM and Status Logic Card Port
Multiport Serial Interface Ports
Host Computer
Keyboards
PEDs
iii
{
TABLE OF CONTENTS (Cont)
Page
Section
1.7
7.7.1
7.7.2
Appendix A
Appendix
B
Append:.l.x C
Programming Examples
Programming the Color Display Monitor
Use of Blink and LOT
7-21
7-21
7-21
SL"MMARY INFORMATION
A-I
GR.:-\PHIC 8r1AC'RO DESCRIPTION
PROGRAMMING CAUTiON'S
~IST
1-3
1-4
1-5
1-6
2-1
2-2
4-1
6-1
7-1
7-2
7--3
7-4
7-5
7-6
7... 7
7-8
.0.-1
A-2
C-1
OF ILLUSTRATIONS
Page
NUlllber
I-I
1-2
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.
GRAPHIC 8 System Components
Cl;!lComp Nodel 31 Color Graphic System Specifications
GR.,L\.PHIC 8 Terlllinal Controller Functional Block Diagram
GRAPHIC 8 System Nemory Map
Addressable va. Disphyable Areas for Low Screen Re.solution
Representative GRAPH1C 8 System Configuration
Verification Test Pattern
Summary of GRAPHIC 8. Operating ~1:ldes
Addressable ve. Displayable Happing Menory Areas for
1024 x 1024 Screen
Display Created by Sample Refresh File No. 1
GCP ExeCutive Loop Flowchart
Synchroni zed Linkage Program Coding E;tample
Synchronized Linkage Flow Chart Example
Sync Link Program Coding Example
Sync Link Flow Chart Example
Super Sync Program Coding Exaanple
Super Sync Flow Chart Example
Relationship Between PDR and LUT
GRAP!UC 8 System Memory Map
Model 5784 Keyboard Layout and Code Assignments
1-2
1-3
1-5
1-6
1-9
1-13
2-4
2-12
4... 5
6-3
7-5
7-9
7-10
7-12
7-13
7-14
7-15
7-22
A-2
A-71
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- 1
LIST OF - TABLES
Number
2-1
2-2
2-3
5-1
5-2
5-3
6-1
6-2
,-. -
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1,-·,
!,
7-1
A-I
A-2
A"'3
A-4
A-5
A-6
A-1
A-a
A-9
A-IO
A-ll
A-I 2
A-13
A-14
A-IS
B-1
B-2
B-3
Page
Serial Interface Port Codes
Local Mode Command Summary
Standard Transfer Table
Data Word Translation Codes
GCP Extended Device Control
Byte Transmission Requirements
Sample Refresh File No.1
Sample Refresh File No. 2
Ma P LU'l' S1 ze
GRAPHIC 8 Local Mode Command Summary
Graphic 8 Controller Instruction ~ary
Graphic Controller Register Format Summary
Serial Interface iegister Format Summary
Parallel Interface Register Format Summary
Register Designations and Address Assignments
Display Proces6or Trap Addresses
Alphabetical Index of Messages Between Host and GRAPH!C 8
Character Generator Code Assignments
MUltiport Serial Interface Port Assignments
Standard Transfer Table
Charac tar Font Summary
7-Bit ASCII Code
GRAPHIC 8 Registers
GRAPHIC 8 Instruction Timing
GRAPHIC 8 Display Macros
Detailed Macro Descriptions
Typical Program Structures
2....5
2-7
2-11
5-4
5-50
5-65
6-4
6-13
7-22
A-3
A-4
A-20
A-26
A...28
A-29
A-34
A-36
A-67
A-68
A-69
A-70
A-72
A-75
A-78
B-3
B-5
B-19
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Summary of Controller Instruc. tions
MNEMONIC
PAGE
DESCRIPTION
.. -"
ADDI
CALL
CALLE
CALR(E)
CHAR
CLEM
DRKY
DRSR
,=.'-
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DRXA
ORXR
ORYA
ORYR
FLPG
HREF
INI'!
IZPR
JMPM
J'MPR
JMPZ
JMPZE
it
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:
JPRZ
JRMP
JUMP
JUMPE
LDCG
LDOI
LOOP
LDOZ
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LDKX
LOPD
,
URI
LDS1'
LOOPE
LOT!
LOU
LDXR
LlNK
LINKE
MDLU
'.
MODE
,
MPVD
MVSR
:
MVXA
MVXR
MVYA
.:oJ
MVYR
NOOP
Add to di splay regi ster immedi.a te
Call subroutine
Call extended subroutine
Call relative
Draw single character
Clear mapping memory
Draw conic Y
Draw short relative
Draw X absolute
Draw X relative
Draw Y absolute
Draw Y relative
Fill a convex polygon
Halt refresh
Initialize
Initialize
Jump and mark.
Jump sho~t relative
Jump if display register 0 contents
Jump extended if display regist.er 0
contents ia 0
Jump relative if display register 0
contents ia 0
Jump relative
Jump
Jump extended address
Load character generator
Load display register immediate
, Load display parameter register
Load display Z register
Load conic X register
Load pixel data register
Load device register immediate
Load stack pointer
Load extended stack point.er
Load text increment register
Load X absolute
Load X relative
Synchronized linkage
Synchronized linkage extended
Modify lookup table
Load instruction mode register
Move pixel data
Move short relative
Move X absolute
Move X relative
Move Y absolute
Move Y relative
No operation
3-23
3-15
3-15
3-16
3-9
3-28
3-11
3-6
3-5
3-5
3-6
3-6
3-32
3-20
3-28
3-27
3-18
3-i3
:fr.
0
3-14
3-14
3-15
3-13
3-12
3-12
3-23
3-22
3-25
3-26
3-11
3-28
3-23
3-22
3-22
3-27
3-3
3-3
3-19
3-19
3-31
3-28
3-29
3-5
3-4
3-4
3-4
3-4
3-13
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Change 1
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Summary of Controller Instructions (Cont)
MNEMONIC
DESCRIPTION
Po i. nt plot relative
Point plot tabular absolute
Point plot tabular relative
Point plot Y absolute
Point plot Y relative
Restore display register
Return
Save dis play register
Draw two tabular characters
Update video controller registers
Wait
PPLR
PPTA
PPTR
PPYA
pm
RESD(E)
RTRN
SAVD(E)
TXT
UPDT
i.J'ATE
PAGE
3-6
3-7
3-8
3-7
3-7
3-24
3-17
3-.24
3-10
3-21
ORlGIN
Gt
GO
GP
GR
Rost
Rost
Host
Bost
Host
PoOst
Host
as
aT
GU
HI
KT
GRAPHIC 8
Host
Host
Host
Bost
GRAl'!lIC 8
Host
Host
Host
Host
Host
Host
Host
Host
GRAPHIC 8
KY
GRAPHIC 8
L1<.
LT
Host
Host
Host
Host
Host
EP
IG
II<
TI1
IN
IP
IS
IT
IV
IX
rr
'f
1Z
KP
Mt
MS
MU
NM
GRAPHIC 8
NN
NO
Bost
Host
Host
Host
NP
OT
'11iii
Change 1
DESCRIPTION
Give image
Give option status
Give PED No. 1
Give register
Geft status of PEDs
Give PED No. 2
Graphic update
Halt interrupt
Halt picture
Initialize FSP support
Interrupt control
Initialize I/O message formats
Input device
Initi,alize FED No. 1
Enable selected interrupts
Initialize PED No. 2
Initialize device
EnterEDC mode
Ini ti alize 2
Initialize
Continue picture
Alphanumeric keyboard No. Z
Alphanumeric keyboard No. 1
Light keys on function keyboard No. 1
Light keys on function keyboard No. 2
MoV'e image
Memorv blank select
Memory update
No messages ready
Enable error numbe'r
No operation
Enable box display
Request to device
PAGE
5-71
5-26
5-45
5-47
5-57
5... 31
5-21
5-54
5-28
5-11
5-51
5-42
5... 29
5-42
5...,51
5-50
5-71
5-7
5-22
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5-37
5-37
5-36
5-36
Ir
5-58
5-17
1:
5-18
5-16
5-61
5-16
5-59
5-51
,
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5-23
5-47
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Summary of Host-GRAPHIC 8 Messages
MESSAGE
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Summary of Host-GRAPHIC 8 Messages (Cont)
MESSAGE
ORIGIN
PL
PV
RG
RI
Host
Host
RK
RL
RO
RP
GRAPHIC 8
GRAPHIC 8·
GRAPHIC 8
GRAPfIIC 8
GRAPHIC 8
GRAPHIC 8
GRAPHIC 8
GR.4.PHIC S
RR
RT
RU
Host
RW
GR.4.PHIC 8
SP
SU
Host
Host
TK
Host
1M
Rost
Host
TN'
TS
VL
VI
XJl
GRAPHICS
GRAPHIC 8
GRAPHIC 8
GRAPHIC 8
GRAPHIC 8
x.x
GRAPHIC S
ZI
Rost
ZN
Host
ZP
ZR
Host
Host
ZS
ZT
Host
ZU
Host
Rost
DESCRIPTION
PAGE
Poll GRAPHIC 8 for next message
Packed vector'
Return FSP table address
Re t urn image
Function keyboard No. 1
Function keyboard No. 2
Return option
Return PED No. 1
Return register
Return PED status
Register update
Return PED No. 2
Start picture
Selective update
Transfer control
Assign data tablet as PED No.1
As sign data table t as PED No. 2
2D/3D coordinate converter status
Variable length (follows 1.1 or RO)
x. or Y position overflow interrupt
Scratchpad ready for alphanumeric
keyboard No. 1
Scratchpad ready for alphanumeric
keyboard No. 2
Error status
Disable selected interrupts
Di sable error number
Disable box display
Initialize scra~chpad for
alphanumeric keyboard No. 1
Zero scratchpad No. 1
Ini tialize scra tchpad for
alphanumeric keyboard No. 2
Zero scratchpad No. 2
Change 1
5-15
5-65
5-55
5-24
5-39
5-39
5-72
5-48
5-27
5-46
5-20
5-48
5-21
5-19
5-23
5-41
5-41
5-75
5-25
5-32
5-38
5-38
5-8
5-30
, 5-62
5-60
5-34
5-35
5-34
5-35
ix! (x blank)
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SECTION 1
\.:
GRAPHIC 8 SYSTEM DESCRIPTION
..
1.1
l'
INTRODUCTION
The Sanders Associates, Inc. GRAPHIC 8- is a high-performance, intelligent
computer graphics terminal system incorporating refreshed raster display technology.
The Graphic 8 combines sophisticated display processing techniques, developed by
Sanders in the popular GRAPHIC 7- refreshed stroke graphics product line, wtth new
CRT raster graphics features. It is designed to interface a host computer and to
support operator CRT display monitor stations configured with interactive devices,
such as keyboards, trackballs, forcesticks, and data tablets. Also, it can produce
permanent hard copy records of displayed data.
the. GRAPHIC 8 system utilizes many of the key features of the GRAPHIC 7 system.
For instance, the GRAFRIC 8 can use any of the existing GRAPHIC 7 high-speed,
parallel host computer interfaces or the as-232C port. Existing GRAPHIC 7 software,
including the Sanders' FORTRAN Support Package (FSP), may be used with the GRAPHIC
8. And both systems use a common display processor instruction set.
I
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The axoo series GRAPHIC 8 features a dynamic display update via a double
refresh buffer memory te~hnique. From one up to four CRT display monitors are
supported by the 8XOO series configurations. Resolutions of 512 x 512, 640 x 480,
1024 x 768 (interlaced) or 1024 x 1024 (interlaced) are available. Both color and
monochrome ve rs ions are offe red wi th up to 8 bi ts pe r pixel to provide as many as
256 simultaneous colors or monochrome intensities (or 128 plus blink).
The GRAPHIC 8 display processor is a general purpose digital computer with a
set of oV'er 400 instructions that controls avat'iety of functions, which reciuce the
loading on the host computer. In combination with the host computer, the GllAPHIC 8
system permits the user to display digital data in a visual format on the CRT
display monitor and to interact with the displayed image by means of keyboards,
forcesticks, trackballs, and data tablets. Its high performance and intelligence
make it well suited to a variety of applications, such as, CAD/CAM, simulation and
training, command and control, cartography, and many others.
1.2
.. ....J
,
COMPONENT DESCRIPTION
The basic GRAPHIC 8 system consists of a terminal controller and a monitor.
The basic system can be expanded to include a wide variety of options and
enhancements.
....'
"'GRAPHIC 8 and GRAPHIC 7 are trademarks of Sanders Associates, Inc.
1-1
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COLOR DISPtAY MONITOR
AND .KEYBOARD
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TERMINAL CONTROLLER
Figure 1-1.
1-2
GRAPHIC 8 System Components
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DESCRI~T10N
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SPECIFICATIONS AND CHARACTERISTICS:
The CatComp Model 31 is a stand-atone recording
system for making 8 x 10 inch color or black and white
prints and 35 mm color slides of any data presented on
its self-contained, highresotution raster scan CRT. With
Polaroid Type 808 Potareolor 2 Land film. the Model 31
makes color prints instantly available.
Video Monitor:
'"
Nominal resolution of 1400 lines center screen
100
cd/m2 (30 fL) on flat-face CRT.
Pixel position error is<0.5% within a- 9 em eirclei":
".~
•
Standard
a
For use w.ith aI/ raster scan computer graphics and
digital image processing applications
•
Microprocessor controlled to assure consistent
exposure. retiable operation
•
Separation mode for automatic three-color separation
exposures
•
Switchable raSter blending for high color Saturation
prints
•
Fully automated 35 mm slide capability with remote
control (optional)
SYS1EMSINTERCONNECT
a • 10 POLAROID
COLOR OR BiloW "LM
HOST
COMPUTER
CALCOMP
..,OOEL
)
31
COLOR VIDeo
GRAPHICS
DISPLAY
1-~3L~U;e~.....j
JREEN
SYNC
Figure 1-2.
Optional
(all units single phase. line to
neutral):
120 VAC ± 10%. 60/60 Hz. 0.8 amps. 110
watts (max)
100 VAC ± 10%. 50/60 Hz. 1.0 amps. 220
or 240 VAC ± 10%. 50/60 Hz. 0.5 amps
Video Input: .
Separate Red. Green. Blue. and Sync video Signals of
0.35 to 2.0 peak to peak voltage required.
Standard-Handles horizontal line rate of 500 to 650.
Optional-High Line- Handles horizontal line rate of 800
to 1100 at 60 Hz or 1300 at
50 Hz.
Operating Environment:
Temperature-20o
lOoC
Relative HUl1"lidity-15% to 90% non-condensing
Altitude-Sea level to 4500 meters
Operating Noise-Negligible
e ::
Cables:
Power: 3 meter power cord.
Interface:
Four 74 Ohm. RG-69 coaxial cables of 3
meters each. BNC Plug on each end will mate'"
to BNC Bulkhead Receptacle.
8·10
COLOR OR BiloW FILM
35 mm
COLOR SLIDES
CalComp Model 31 Color Graphics System Specifications
,,"
1-3
1. 2.1 TEru.fINAL CONTROLLER. The GRAPHIC 8 system contains a terminal controller
which consists of a rack mountable card cage and a power supply. As shown in figure
1-3, the cards are interconnected via either a processor bus or a graphic bus. The
size of controller selected is based on the four folloWing Il1ajor considerations:
1.
Color or monochrome
{'
2.
Number of dmul taneOU$ c010rsor intend ties •.
3.
Resolution of the display :!mage
f· 'j
4.
N'Ull1ber of display stations per controller
···~'l
The GaA,PHIC 8 terminal controller accOt!lll1odates 11 cards and a power supply_
The controller eonSists of a card cage with slots for 17 cards. Six of the slots
are for the processol; caJ;'ds, one slot is for the digital graphics controller, one
slot is for the timing module. and the remaining nine slots ue for the mapping
memory and video controller cards.
1.2.1.1 Dh21ay Procenor.the display processor card is a general purpose digital
couputer that runs the CCl? atld acta as master control for all 4.eviees connected to
the processo"t' bus. It cQtttainsluUtiple high-speed general""'put"pose registers that
can be use, generates vectors, characters, conics,
point plots, fills and stores these in mapping memory in raster-scan format. It
executes all 40 display instructions of Sanders' stroke~writing (random position)
product line graphics terminal, the GRAPHIC 7. Additional display instructions have
been added to implement features unique to digital TV.
These digital graphic controller instru,ctions are describe.d in detail in
Section 3. The complete series of sequential instructions that defines any
particular display image is referred to as a refresh file.
The digital graphic controller may be considered as a de'Tice on the processor
bus of the terminal controller. It contains its one set of registers that maintain
instruction address, control fetch operations, and perform any branching that may be
specified by non-graphic instructions. It also calculates relative data when
required ~ loads data into appropriate registers, and initiates eJtecution of refresh
file instructions.
Status bits of the digital graphic controller are maintained by circuits on the
ROM and status logic card (paragraph 1.2.1.5). These bits plus the graphic
controllerregiste:r;"s aloe accessible to the display processor (paragraph 1. 2 .1. L;)
which maintains control over the entire terminal controller.
1.2.1.7
Video Controller. The video controller obtains data from the mapping
memory and formats it for presentation on the display monitor(s). Outputs are
provided as either RGB color or monochrome and as composite video.
External video may be accepted by the video controller and logically ORad with
internally-generated video. A single video ~ontroller can accommodate up to eight
bits per pixel.
The video controller generates one non-destructive, full-screen, crosshair
cursor and contains the cursor address registers which are accessible to the user.
It controls the split screen function which allows the user to divide the display
face into up to three variable-height horizontal bands and fill these bands with
data f:C'Olll anywhere in addressable mapping memory. This feature allows the user to
simultaneously view up to three separate areas of mapping memory which are not
necessa.rily contiguous<
The video controller contains a 256 x a-bit word Rfu'1 look-up-table (LOT) which
allows pseudo-color or pseudo-gray 1e'7e1 transformation to be made.
1. 2. L 8 Mapping i'1emory. The mapping memory contains pixel data in a format ~.hich
allows display refreSS-in a raster scan mode. The mapping memory may be configured
for 1rarious resolutions up to 1024 'it 1024 and for interlace or non-interlace
refresh. A single memory board c.an be supplied wi th a c.apaci ty of over four million
bits. Up to eight bits can be combined per pixel to provide 256 possible colors or
intensity levels.
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(1023, ! 023)
DISPLAYABLE
AREA
(-512, -512)
1024X76S
1024 X 1024
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512 X 512
640 X 480
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Figure 1-5.
Addressable
VSe
Displayable Areas for the Four Screen Resolutions
1-9
A dual mapping memory configuration is for high-speed dynamic update of data.
The dual memory concept a.l1owsthe hardware to clear and update one memory while the
second mentory is refreshing the display. When the next update occurs, the roles of
the two memories are reversed SO that the previously updated memory now b.ecomes the
refresh memory.
"
1.2.1.9 Timing Moqule • The timing board generates all display-related timing
signals as weI!. as die necessary synchronization signals for the monitors. On-boa.rd
switches allow selection for cQ1J.Ipatible opera.tionWtth the possible resolutions and
refresh frequencies.
. .
1.2.1.10 Character Generation. Character generation is perform.ed by the· Digital
Graphic Controller. The basic set of characters $11pp1 ied is a standard set of 96
ASCIl characters. When the ASCII code cort'esponding to. the dedred character is
applied to the read-only mE!1llory, the character is drawn a.t the position determined
by the current/position for X and Y.
.
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ltead-ca.ly memory for s:L.x groups of 16 eharacters can be added to provide a
total of up to 192 standal;'d. aec1 special characters that can be prod.uced by the
G'R.APltIC 8 ..
I
1.2.1.11 2"'0/3-1) Coordinate Con.erter. The Model 575.3 2...0/3 ..n coordinate converter
converts a Sanders graphic· display into a three dimenSional display capable of
independent dyna+l1c manipulation of objects in apparenl: spaee. Among the functions
provided by theMQde1 5753 at'e t'1'anslation, sc:ali.ng, rotation, IlIindowing, independent display coordiIJ.<;lte mapping, perspective, and zooming with perspective.
I
the pel:spective feature is espeeially useful for realistic viewing of an
object. Utilizing perspective, the location of the viewer is defined relative to
the Utage space, and alllihes an!! objects within the image spalle are then viewed at
the proper perspective for that location. The view may be completely orthographic:
i f the viewer does not nsh to use th,e perspective feature.
Objectsc:aa be defined within a 64K (X), 64K CO. by 32K (Z) i3n..age spaee and
presented on a lit by IK s.ereen or any portion thereof. Translations can be made
within the limits of the image space and scaling range is 64 to 1. Rotation c:an be
provided about any axis.
3 ...D WindoWing, in conjunction with independent screen coordinate mapping,
allows the presentation of any data withitt a software definable X, Y, Z image space
to be presented on the full screen or any portion of the screen. Zooming is
accommodated by scaling and changing the user's apparent perspective viewpoint.
.
,
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The 5753 provides for both homogeneous and non-homogeneous matrix operation.
Also, transform.at1ons of 2-D :lInages can be accomplished 1ncludingtranslation,
rotat1on, scaling, and windOwing.
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AlphanUll1eric ·data can be moved about the screen with vector defined data
Without sealing and rotation.
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deeem:lnedby instl'uctions from the digital graphic controller, characters
of three different dZescan bes~erated. Character. may also be rotated 90
degreeS! cout11:ereloekwise to aceommodate vertical writing requirmuents. Both normal
and rotated characters can be made to blink.
As
"'
,
1. 2.1.12 Data Converter. The modelS 744 data converter option transforms incoming
floating point binary numbers into displayable numbers. The displayable numbers may
be in any of sixteen formats selected by the host. The bi-directional converter
also converts the displayed numbers into floating-point binary for transmission back
to the host.
The data converter saves host computer time and storage resources by performing
these conversions within the graphic terminal. It allows data to be transmitted to
and from the host in its most compact form and frees the host programmer from the
conversion programming task.
The data converter can perform more than 500 conversions per second, which
allows it to be used in high data-rate applications resulting in significant
off-loading of the host computer.
The dita converter is not supported by the standard Graphic Control Program.
1.2.1.13 EPROM E~g>ansion Module. As options are added to the GRAPH!C 8, the
addi tional software required to handle the options will be stored on the model 7750
expansion module (EM).
. .J
The expansion module may contain up to 321< 16-bit words of non-volatile
read-only mem.ory (EPROMS). The data may be loaded from the EM automatically by
pressing the SYStEM button or when so instructed by the host, depending on the
options stored •
1. 2. 2 INPUT DEVICES. Optional data input devices for the GRAPHIC 8 give the
operator two-way interaction with the display and processing system. Input devices
available include two types of keyboards; a trackball, a forcestick, and a data
tablet. The GCP in firmware can support up to eight keyboards, or eight position
entry devices (trackball, forcestick, or data tablet). In addition to the foregoing, a teletypewriter or paper tape reader can be connected to the GRAPHIC 8 for
the input of maintenance da tao
1.2.2.1 Ki!yboards. Standard keyboards available for the GRAPHIC 8 are the Hodel
5783 and Model 5784 keyb"oards. The keyboards c.ontain a main block of alphanumeric
keys plus a matrix and a row of function keys.
c.
The Model 5783 keyboard offers an alphanumeric. block of 58 keys. These keys
generate standard seVen-bit ASCII codes fN'ith an eighth (MSB) bit always set to l.
The alphabetic keys generate both upper and lower case codes. A four-by-four matrix
of function keys is located to the right of the alphanumeric block and a row or 16
runction keys is located immediately above the alphanumeric block. Each function
key generates a single eight-bit octal code from 000 to 037.
An added feature of the Model 5784 keyboard is that each function key contains
a LED that can be lighted or turned off as required under program control. The
Hodel 5784 also has provisions for additional keys to the basic board. These keys
are for future expansion and are located on both sides of the space bar.
The keyboards operate at a rate of 9600 baud and interface to the terminal
controller via ports on the multipart serial interface card. Refer to Appendix A
for layouts of the two keyboards and the specific codes generated by each key.
1-11
l -,
1.2.2.2 Trackball, For~est:ick, and Data Tablet. The trackball, forcestick~ and
data tablet are referred to as PEDs (position entry devices). These devices are
used as determined by program control to move a cursor and/or data displayed on the
CRT screen. Movement initiated by the trackball is proportional to the speed and
direction in which the trackball is rolled. Movement initiated by the forcestick is
proportional to the direction and force ~<1ith which the forces tick is deflected.
Movement initiated by a data tablet is proportional to the speed and direction in
which the data tablet pen is moved along the data tablet surface. PEDs are
connected to the system via ports on the multiport serial interface card(s) in the
terminal controller.
1.2.2.3 Maintenance Data Input Devices. A teletypewriter and/or a paper tape
reader can be connected to the &'RAPH!G 8 to input data for maintenance purposes.
The teletypewriter is normally connected to a port on the ROM and status card in the
terminal controller while the paper tape reader is connected to one of the ports on
a multipart serial interface card. The teletypewriter serves basically as a
troubleshooting aid. The ,paper tape reader is used to load special user or
diagnostic programs into the GRAPHIC 8.
1. 2.3 OUTPTJ'!' DEVICES. The standard output de'1ice for the GRAPHIC 8 is the CRT
display monitor. A hard copy unit is available as an optional output ~evice. Using
the same signals that go to a statldard display monitor, the hard copy unit can
produce a duplicate on paper of any static image displayed on the CRT of the display
monitor. Operation of the hard copy unit is controlled manually.
An option~l hard copy multiplex switch is available. The multiplex switch is
capable of interfacing up to four GR.,<\PHIC 8 displays to a single hardcopy unit.
1.2.3.1 Display Monitors. The GRAPHIC 8 offers the user a choice of configuration
of eight Ca.T monitors (four monochrome and four color) to provide the right monitor
for the intended application.
Positions on the screen are specified in terms of a matrix containing 2048
coordinates in the X dimension and 2048 coordinates in the Y dimension. Two's
complement notation is used to designate the coordinates with location 0,0 being
defined as the center of the screen. Of the 2048 by 2048 addressable locations, the
displayable area comprises the field of coordinates centered about the middle of the
screen. Refer to figure 1-5 for different screen resolutions.
1. 2.3.2 Hard Copy. Both monochrome and color hard copy devices are available for
use with the GRAPHIC 8. Refer to figures 1-1 and 1-2_.
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~ CONTROLLER I--!-I
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GRAPHICSMULTIPlE STATION -
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GAAPHIC 8STANDARDTERMII'iAL
-
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HOST
COMPUTER
MODEM
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CONTROLLER -
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GiiAPHic iREMOTE"'TERMTI'I.~:L
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f~_ ________
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__________ ---tI
KeD - KEYBOARD
TRACKBALL·r·FO~R~C;ES~T1=C:K:'======---------~:__---__1
PED - DATA rABlErt'"
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SERIAL I/O PORTS
DATA ENTRY DEVices
Figure 1-6.
REAOI
WRITE
MEMORY
TIMING
MODULE
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0::
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MAPPING
MEMORY
~
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L.... SERIAL
'"""-- 0,
,.... INTERFACE ,--- il:
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HOST
DISPLAY
PROCESSOR
DIGITAL
GRAPHIC
CONTROLLER
~
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t.:!
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VIDEO
CONTROLLER
l
DISPLAY
MONITOR
EXTERNAL SYNC
ROM &
STATUS
t
SERIAL DIAGNOSTIC
PORT
Representative GRAPHIC 8 System Configurations
1-13/1-14
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SECTION 2
OPERATING MODES
2.1
GENERAL
•
The GRAPHIC 8 system can be operated in either the local or the system mode.
In the local mode, the GRAPHIC 8 operates as a stand-alone system; in the system
mode, the GRAPHIC 8 operates on-line to the host computer. Initialization in either
mode causes built-in diagnostic routines to be performed automatically.
2. 2
LOCAL MODE
After primary power has been .applied to the GRAPHIC 8, the system may be
init:Lalized in the local mode by pressing the LOCAL pushbutton swi tch on the front
of the terminal controller. Pressing this Swl. tch causes a 1terification test pattern
to be displayed on each of the associated display indicators, causes the built-in
diagnostic routines to be performed, aM enables local 1J1dde ccmmands to be executed.
The following t:aragraphs discuss these operations as they relate to software.
NOTE
When the LOCAL swi tch is pressed, the built-in
.memory diagnostic exercises the complete memory
system. For systems containing JlX)re than 32K of
memory, it may take several seconds before the
terminal verification pattern is displayed. As
part of the memory diagnostic, the memory configuration installed in the terminal controller is
saved and can be examined if des:1red. Address 736
contains the RAM configuration word and address
750 contains the .RCM co~iguration 'NOrd.
the RAM and RCM configuration words are defined as
follows:
RAM CONFIGURATION WORD
I
15 14 13 12 11 10
MEMORY SYSTEM.
9 8
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7 6
0
o
5 4 3
000
Address 670 contains a copy of the system
uration register (see page page 4-22).
2
o
1
0
0
01
config~
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Change 1
2-1
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ll1emory Sys tem (64K cards)
(16K word 1/2 banks)
0
a
0
0
0
0
0
0
OK
0
0
0
0
0
0
0
1
16K
0
0
'0
0
0
0
1
1
32K
0
0
0
0
0
1
1
1
48K
0
0
a
0
1
1
1
1
64K
0
a
0
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1
1
1
1
80K
0
0
1
1
1
1
1
1
96K
0
1
1
1
1
1
1
1
1l2K
1
1
1
1
1
1
1
1
128K
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Banks
'-'
Be
B15 B14 Bl3 Bl2 Bll BIO B9
1
ROM CONFIGURATION WORD
15
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12
13
11
10
9
8
7
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4
5
3
2
1
0
0
0
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0
0
0
o
0
0
0
0
0
1 0
No optional ROM
4K optional ROM
1
8K optional ROM
1
0
0
ROM
0
0
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2-2
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2.2.1 VERIFICATION TEST PATTEmT &~D DIAGNOSTICS. Figure 2-1 is the verification
test pattern that is displayed on each display monitor when the GRAPHIC 8 is
initialized in the local mode. This pattern remains displayed unti1 terminated by
the proper command (paragraph 2.2.2) or \mtil a period of 45 minuteS has elapsed
since an operation affecting the pattern was last performed.
'
Components of the verification test pattern that are primarily associated with
software and the operation of peripheral devices are identified in figure 2-1. w~en
the system is first initialized in the local mode, "XX" appears in the small box in
the lower right portion of the pattern. The "XX" indicates that thE; code appearing
in the same box contains the results of the built-in diagnostic routines that were
automatically performed. The diagnostic code is a three-digit octal representation
of an eight-bit binary code that indicates the results of each diagnostic routine.
Bits in the binary code are assigned as follows:
MSB
7
6
5
4
3
2
1:
LSB
0
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GRAPHIC CONTROLLER ________________________________________ I
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NOT USED
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3-D COORDINATE CONVERTER _ _ __
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DIAGNOSTIC
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PARALLEL INTERFACE DIAGNOSTIC ______
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SERIAL INTERFACE D!AGNOS! IC
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READ/WRITE MEMORY DIAGNOSTIC ____________- __ I
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DISPLAY PROCESSOR DIAGNOSTIC ____________________ I
----------------
DIGIL~
DIAGNOSTIC
A checksum calculation routine performed whenever the GRAPHIC 8 is initialized
in the local mode is a checksum calculation based on all GCE stored in read only
memory. rne result is deposited in mernor! location - 500 (octal). Location 500 can
also be examined as described in paragraph 2.2.2.1.
When a diagnostic routine detects a malfunction, the corresponding bit in the.
error code is set to a 1; if no malfunction is detected, the bit is set to a O. The
octal code displayed in the verification test pattern then indicates the results of
all the diagnostic tests. For example, 000 indicates all tests passed, 002
indicates the display processor diagnostic test failed, 030 indicates the serial and
the parallel interface diagnostic tests failed, and 077 indicates that all
diagnostic tests failed.
2-3
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Verification Test Pattern
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As soon as any input is received by the terminal controller via a serial
interface port, the "XX" in the small box is replaced by a code that indicates the
port to which the input device is connected. Codes associated with each serial
interface port are shown in table 2-1.
Table 2-1.
CODE
Serial Interface Port Codes
•
SERIAL
INTERFACE
PORT
DEVICE
ASSOCIATED CONNECTOR
TT
TTY
Console teletypewriter
J2 on ROM and Status card
Fl
3
Function keyboard 1
J5 on multi port serial interface
card III .
F2
7
Function keyboard 2
J5 on multipart serial interface
card #2
F3
2
Function keyboard 3
J4 on multi port serial interface
card til
F4
9
Function keyboard 4
J3 on multipart serial interface
card tl3
51
1
Serial host
J2 on multiport serial interface
card til
1*
4
PED #1
J6 on card 1F1
2*
8
PED #2
J6 on card 112
3*
6
PED 113
J 4 on card IF2
4*
10
PED 114
J4 on card 113
PED
Indicators
... :;
Trackball (or forces tick) indicators appear in the upper left corner of the
verification test pattern. The "1*" indicator is associated with the device
normally connected to serial interface port 4 (J6 on mu1tiport serial interface card
no. 1) while the "2*" is associated wi th the device normally connected to serial
interface port 8 (J6 on multiport serial interface card no. 2). These indicators n*
displayed on the test pattern are only those that are included in the system
c.onfiguration (Display P'rocessor II switch settings) regardless of whether the
trackball or forcestick is physically connected to the system. If a trackball or
forces tick is connected to port 4 or 8, it can be manipulated to move its associated
indicator about the screen of the CRT as desired. (See paragraph 2.2.1.2 for data
tablet.)
2-5
When the serial interface port designation is displayed in the small box ~ the
three digit octal code in the box indicates the code last transmitted to the
terminal controller. Additionall y, if the code represents a displayable charac ter,
the character appears in the upper left corner of the box. If the code does not
represent a displayable character, the upper left corner of the box is blank. In
systems using SI (shift in) 'and SO (shift out) codes to identify characters in an
extended set, the SI character is displayed over the left hand digit o.f the code and
the SO character is displayed over the right hand digit.
The I-digit numeral in the upper center of the ver:1ficatirOn test pattern
indicates the monitor (1-4).
A filled Polygon positioned beneath the blinking Monitor Number will display
the default Colors/Gray levels. The o timber of Colors/Gray levels i~ a function of
the configuration and can be 8. 16, 128, or 256.
2.2.1.1
Hardcopy Generation.
A hardcopy of the terminal verification pattern can
. be generated by pressing function key FOte freeze the pattern .aIld then the hardcopy
initiate button located on the hardcopy unit.
2.2.1.2 Data Tablet Testing. The data tablet can be tested by pressing function
key F1. thIs causes dienn "trackball! forcestick indicators to change to n/;. The ltf
and 2# symbols indicate that all messages received via potts 4 and 8 are in data
tablet format. (Dat.atabletmessages consist of 10 character messages, whereas the
trackball a,nd forcestick generate 2.... character messages.) When the data tablet pen
switch is pressed and the pen is moV"edalong the active area of the data table
sur face, the appropriate cursor symbol (111 or 21ft) moves at a rate proportional to
the mO'7ettlent of the p.en. The If; symbol is associated with the data tablet connected
to port 4 and the 2ilsymbol is ,associated with the data tablet cOnnected to port 8.
NOn:
Successively pressing function key Fl causes the
terminal verification pattern to swi tch f'r'om
processing data tablet messages to trackball/
forcestick messages and vice versa.
2.2 • .2 LOCAL MODE CO~1MANDS. After the GRAPHIC 8 has been initialized in the local
mode the verification test pattern is no long.er required, display of the pattern may
be term:!.nated by pressing the RETURN key on the keyboard. The p.attern then
disapp~!ars and the letters "EO M" are displayed on the center of the CRT screen as
an indication that the system is in the local monitor mode. At this point, the
operator carl perform any of several operations that permit h1.m to monitor or debug a
program, transfer c()ntrol, or communicate with the host computer.
I
f
{
(
{
1
{
f
I
f
I
I
I
I
NOTE
Commands are executed when the RETURN key on the
keyboard is pressed.
The following paragraphs discuss commands that can be executed when the system
is in the local monitor mode. A summary of the commands is given in table 2-2.
I
{
Table 2-2.
Local Mode Command Summary
KEYBOARD
ENTRY
........
OPERATION
RE'l'URN
Executes local mode command or returns system to local monitor level.
nnnnnn/
Displays contents of memory address nnnnnn (octal).
/
Increments memory address counter by two and displays address
contents.
or
Bn
Decrements memory address counter by two and displays address
contents.
(BO 0-32K; Bl 32-64Kj B2 64-96K;
Select different memory bank.
B3 96-l28K; and B4 l6-32K RAM).
~ ..
I
I
f
I
S
Transfers GRAPaIC 8 to system mode operation.
T RETURN
Transfers to
L RETURN
Loads memory from paper tape reader.
nnnnL
REn:JRN
Loads selected option from expansion module.
U RE'lURN
Luload all options.
o
Display status of all options loaded.
_
1
RE'l'URN
theverifi~ation
test
pa.ttern~
Q
Decrements contents of display processor Q register by two and
displays result. Used with diagnostics to indicate address at which
display processor halted.
nnnnnnD
RETURN
Directs graphic controller to display refresh file beginning at
address nnnnnnn (octal).
nnnnnnG
RETURN
Transfers control of display processor to program beginning at memory
address nnnnn (octal).
Y RETURN or
Calls teletypewriter emulation program. After entering emulation
program, function key FO clears CRT screen. Function key Fl selects
full or half duplex operation; receipt of octal code 035 from the
host computer or pressing function key F13 transfers GRAPHIC 8 to
system operating mode. (Y = serial, P = parallel)
P RETURN
... j
)
RUB OUT
Deletes last octal entry from keyboard.
Change 1
2-7
I
2.2.2.1 ~1emot'y Commands. The content of a memory locat.ion is displayed by typing
the octal address (typing of leading zeros is not required) followed by a slash (/),
As soon as the slash is typed. the content of the memory location is displayed
immediately to the right ·of the address. Succ.essive memory locations can then be
examined simply by pressing the slash key~ Each time the slash key is pressed, the
memory address is incremented by two and its content displayed immediately to the
right of the slash •
...
After the slash key has been used to examine the content of a memory location,
the up arrow (t or t\) key may be used in a similar manner to examine preceding
memory locations. Each time the up arrow key is pressed. the memor] address is
decremented by two and its content displayed immediately to the right of the slash.
The content of a memo ry location may be cl1a nged af tel' it ha s been exa.mined by
the neW data. (typing of leading zeros is not required) before pressing the
slash or up arrow key. The new data 1s displayed to the right of the old data and
is automati~a1ly subs tituted when the slash or up arrow key is pressed.
ty~ing
Memory locations in other banks can be examined or changed via the bank (B)
select command. Typing BO, Bl, B2, B3, or B4 c.allses the memory bank selection to be
changed to bank 0, bank. 1,. baIlk 2, bank 3, or bank 4 respectively. Below is a table
representing the associated 'lirtual and physical addresses for each bank.
Bank Number
Virtual Addre,!!
0*
000000 ... 177777
Physical
Addr~
000000""177777
Pages
00-07
1
000000-177777
200000-377777
10-17
2
000000-17777 7
400000-577777
20-27
3
000000-177777
600000-777771
30-37
4*
000000-177777
100000-177777
04-07
I
f
f.
~-.
{
I
I
Return to the monitor level is acccmplished by pressing the RETURN key. When
this key is pressed, any specified memory content change is completed and the system
returns to IllOnitor level as indicated by letters "Bn t1" displayed at the c.enter of
the CRT screen.
2.2.2.2 Displaying a Refresh File. Imen the system is in the local monitor mode)
the contents of a refresh filernay be displayed by typing the starting address of
the file (in octal notation) followed by :a "n" and then pressing the RETURN key.
This cOtfimand instructs the graphic controller to display the entire refresh file
that begins at the specified address. Display of the refresh file c.ontinues until
the RE'l'tJRJ.'\I key is pressed again, at whic.h time the system returns to the local
monitor level. This command is subject to the bank argument presently- displayed.
2-8
"i :
-~
'°'1
f
,,""':"'i;I
f
I
I
I
-,
NOTE
*Addrasses in the range of 140000-177777 (pages 4,
5, 6, and 7) for banJ:r. o correspond to ROM and I/O
device registers. Addresses in the range of
140000-177777 for bank 4 correspond to ~~.
!,
f
I
I
f
r
I
I
..
,\
2.2.2.3 Transfer of Program Control. Program control may be transferred from local
monitor level to any desired address location in bank 0 by typing the address
location in octal notation followed by a "G" and then pressing the RETIJRN key. The
display processor then executes instructions beginning with the instruction at the
specified address. Any further operations depend on the program to which control is
transferred.
2.2.2.4 Transfer to System Mode. To transfer tq the system mode of operation from
monitor level, type "S". This command has the same effect as pressing the SYSTEM
switch on the terminal controller (paragraph 2.3). After transferring to the system
mode, operation in the local mode can be reestablished only by a message from the
host computer or by pressing the LOCAL switch on the terminal controller.
,
·'1
2.2.2.5 Teletypewriter Emulation. For purposes of communicating with a host
computer, the GRAPHIC 8 can be made to emulate the functions of a teletypewriter.
In this mode, the keyboard operates like the keyboard of a teletypewriter and the
display monitor serves as the printout device. Scrolling of data on the display
monitor is handled on a half-page basis. That is, when the CRT screen is full, the
top half of the data is deleted from. the display and the bottom half of the data
moves up to take its place.
.J
.
If a parallel interface card is installed in the terminal cQntroller, the
Graphic Control Program assumes that communications with the host computer are to be
handled over the parallel interface. In this case, teletypewriter emulation signals
are transmitted in parallel using only the low order byte (bits 0-7) of the 16-bi t
interface. If a parallel interface card is not installed, a standard 8-bit serial
interf ace via serial interf ace po rt 1 is assumed. In either case, bi t 7 is always
equal to zero •
.;
The emulation program is entered from the moni tor level by typing the letter
"Y" or "P" followed by RETURN.* Full-duplex of half-duplex emulation may then be
selected by pressing function key Fl which changes the selection each time it is
pressed. The type of emulation selected is indicated by the "tTY F" (full duplex)
or "TTY ROO (half duplex) that is displayed at the top of the screen at all times
during emulation. Switching between full and half duplex operation may be·
accomplished at any time during emulation by pressing function key Fl. Pressing
function key Fa during teletypew~iter emulation causes the screen to be cleared.
I
Exit from the teletypewriter emulation program occurs when octal code 035
(ASCII control character GS Group Separator) is received from the host computer.
This code, which can also be generated by pressing function key F13, immediately
causes the GRAPHIC 8 to transfer to the system mode of operation. Return to the
local monitor level can be achieved only by a command from the host computer or by
pressing the LOCAL pushbutton switch on the terminal controller.
i
2.2.2.6 Additional Local Mode Commands. Additional commands that can be used when
the GRAPHIC 8 is in the local mode at the monitor level are the· L, U, 0, T, Q, and
RUB OUT commands. The L command enables the meoory to be loaded from a paper tape
reader connected to the terminal controller. After the tape has been placed in the
reader, loading is initiated by typing the letter "L" followed by RETURN.
*y
a
serial, P
= parallel
I
Change 1
2-9
{
{
NOTE
A paper tape reader may be connected to multipart
serial interface card ports 1, 2, or 3 or to the
serial "interiace port on the ROM and status logic
card.
The L command can also be usod to load in options from the expansion module.
The. option command format is as follows:
nnnnL RETURN
where nnnn is the optioq nurn.beli.
3777 and 4001 to 7777. "
Valid option numbers are in the ranges of . 1 to
NOTE
{
{
I
(
-'\
"I
~
' .3
J
I' .>,1
The optional expansion module can store a variety
of option types.
The U command is used to unload all options.
will cause all OptiOl~S to be unloaded.
Typing"U" followed by RETURN
The 0 command is used to detect the· presence and status of all loaded options.
Typing 0 followed by RE1'URN causes the display of the first option loaded. Succes'"
5ive1y pressing the R.ETlJRN key causes the display of a~l other options loaded~ The
option status is displayed in the following format.
nnnn ss
Where nnnn is the option number
and SS is the option status
I
I
I
r
The option status code is as follows:
00
01
11
02
12
03
13
04
14
Detected but unloaded
Unloaded, checksum error (local)
Unloaded, checksum error (system)
Unloaded, checksum OK, hardware not present (local)
Unloaded, Checksum OK, hardware not present (system)
Unloaded, checksum OK., self test .. no go (local)
Unloaded, checksum OK., self test "". no go (system)
Loaded, chec.ksum OK, sel.f test"" go (local)
Loaded, checksum OK, self test'" go (system)
The T command is used to recall the verification test pattern when the system
is at the local monitor level. This command is executed by typing the letter "T"
followed by RETURN. The effect is the same as pressing the LOCAL switch on the
terminal controller. Pressing RETURN a ,second time causes the system to return to
the moni tor level.
2 .... 10
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[
J
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t
Table 2-3.
ADDRESS
(OCTAL)
1
..J
Standard Transfer Table
INFORMATION OR ROUTINE
REMARKS
157700
GCP date (year and month)
High order byte indicates month
in octal form. Low order byte
indicates last two digits of year
in octal form (e. g., 003115
indicates June 1977).
157702
GCP date (day)
Day of month is indicated in
octal form.
157704
GCP release number
Release number is indicated in
octal form.
157706
Number of GCP field changes
Number of field changes is
indicated by the number of bits
set to 1 (e.g., 000007 indicates
three field changes).
157710
ZERO
Maintenance routine. Graphic
controller sets X and Y positions
at zero (center of screen) and
then halts.
157720
PLUS
Maintenance routine. Graphic
controller sets X and Y positions
at maximum on-screen positions
(upper and right corner) and then
halts.
157730
MINUS
Maintenance routine. Graphic
controller sets X and Y positions
at minimum on-screen positions
(lower left corner) and then
halts.
157740
LOADER
Enables a file to be loaded into
read/write memory from various
input devices.
157750
MONITOR MODE
Enables local mode commands to be
executed.
157760
SYSTEM MODE
Enables system mode.
157770
TEST PATTERN
Transfers to verification test
pattern.
.• J
2-11
(
I
f
J
1.-
•
l'~l
.J
(
'.}
LOCAL BUTTON
I
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l
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r
J--_.
~_ _
A~U
·SE.! TRANSPER TABlli 2..3.
035 FROM HOST
POWfiR
ON
IZFROM
HOST
SYSTEM
BUTTON
I
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[
f
I
Figure 2-2.
2-12
Summary of GRAPRIC 8 Operating Modes
(
{
.. -
SECTION 3
GRAPHIC 8 INSTRUCTIONS
3. 1
GENEHAL
Instructions used by the GRAPHIC 8 can be divided into two categories: those
executed by the display processor and those executed by the digital graphic controller. The two microcontrollers operate independently of one another and share
common memories via the controller bus (see figure 1-3). Running of GCP is controlled by the display processor while generation of the display image is controlled
by t.he digital graphic controller. The following paragraphs provide details
concerning the instructions executed by each microprocessor.
NOTE
In the octal codas shown for each instruction,
unused bits are indicated by X. Bits representing
variable data are indicated by d.
3.2
DISPLAY PROCESSOR INSTRUCTIONS
.
The display processor emulates a minicomputer of the PDP-II type manufactured
by Digital Equipment Corporation (DEC). As such, the display processor is capable
of e..'tecuting the standard set of instructions used for the PDP-1l/34 minicomputer
and user software may be prepared using standard DEC mnemonics. Other PDP-II
instructions that can be executed are the MUL, DIV, ASH, ASHC, and SPL instructions.
Details concerning PDP-II instructions are contained in the DEC PDP-II/04/34/45/
55/60 Processor Handbook which should be used as a supplement to this manual.
.
An additional instruction that can be executed by the display processor is the
EXCQ (exchange register Q) instruction. The format and operation of this
instruction are as follows:
15
14
13
12
I 0
I
I 1
1
1
I
Octal code:
.EXCHANGE REGISTER Q
IEXCQI
0767dd
11
10
9
8
7
6
5
4
3
2
1
0
I 1
1
0
1
1
1
d
d
d
d
d
d
I
The EXCQ instruction causes the contents of register Q to be exchanged with the
contents of the general register specified by bits 0-5. Its primary purpose is to
provide a means of retrieving the contents of the program counter following the
execution of a HALT instruction. When a HALT instruction is executed, the contents
of the program counter (HALT instruction address + 2) is stored in register Q. The
EXCQ instruction can then be used to move the value to a general register so that it
can be processed as required. The EXCQ instruction is used in conjunction with the
Q command of the local operating mode to enable the operator to determine the
address at which the display processor halted (refer to paragraph 2.2.2.6).
3-1
Operation:
'i,e
<-
(REG Q)
(REG DD)
<-
(REG DD)
(REG Q)
Condition Codas:
3.3
< 0;
N:
Set i f valus in Q reg
Z:
Set if value in Q reg =0, cleared oehetwi.se
V:
Cleared
C:
Not
cleared otherwise
affected
DIGITAL/GRAJ'RIC CONTROLLER
INSTRUCtIO~S
The primary functions of the digital graphic controller are to retrieve the
display instructions from. the refresh file, calculate the addresses of the pixels
that are to be illuminated and to write the pixel data into the mapping memory.
The digital graphic controller (DGC) instruction set comprises more than 60
insttuctiolts that are used to control the presentation of the image to be displayed.
These instructions can be broken down into four basic categodes: Pixel position
::i.nstructions, sequence control instructions, register instr-uctions, and display
control instructions. Pixel position instructions determine which pixels will be
displayed for the purpose of presenting vectot"s, conics, and chat"aCters" Sequence
control instructions direct the graphic controllet" to jump,hranch, halt, ot" wait as
required for pro pet" pt"Og!"atn execution. Register instr-uctions permit data to be
manipulated using the four general purpose registet"s and the stack pointer of the
graphiccontt'oller. Display instructions enable various parameters to be
established or modified as :required to achieve the desired display image
chat"actedstics.
NOTE
Macros W1:'itten in MACRO-ll assembly language are
available for GRAPHIC 8 users. These macros can
be used to assemble all the graphic controller
instructions plus some useful instruction
sequences. Refe:t to Appendix B for description of
the macros.
The cO'1llplete set of instructions and data that defines a particular display
image is referred to as a refresh file. An Extended lnstruction Mode (ElM) bit
permits more instructions than would normally be possible with a given set of opcode
bits. 'the EIM bit is set or cleared by the Load Mode bits instruction, MODE.
For example, 18 bit addressing is used for most sequence control instructions
when the ElM bit is on.
3-2
An indicator (EIM) appears~ whenever the ins truction being described is for ElM
bit on.
Instructions are fetched by the digital graphic controller via the processor
bus, acted upon, and the resulting cia ta placed on the graphic bus for application to
appropriate circuits Crefer to figure 1-3). The following paragraphs describe the
format and function of each instruc.tion in each category of digital graphic
controller instructions. A summary of the instructions is contained in AppendiX A.
'C
Instructions with bit:: X means that the bit is ignored by the instruction
processor. However, since future systems may utilize these X bits, never use an X
bit for information storage.
,
.-
3.3.1 PIXEL POSITrON INSTRUCTIONS. Twenty-five instructions are used to determine
the intensified Pixels in the display ~onitor. These instructions include load.
move, draw, text, and Callie instructions.
3.3.1.1 Load Instructions. Load instructions specify X-axis positions on the
screen in terms of absolute data (specific coordinates) or relative data (lengths
alo ng X axi s ) •
Except for short relative moves or draws, if both X- and Y-axis data are to be
changed, a load instruction must precede a move or draw instruction.
ILDXAI
15
I
I
I
0
LOAD X ABSOLUTE
14
I
I
I
13
12
1
0
0
I
I
I
11
0
10
8
9
I
7
I +
I
6
Octal code:
5
4
3
2
02dddd
1
J.
0
X COORDINATE
Bits 0-10 define absolute X-axis coordinate in two's complement fa rm.
bits (sign extended) replace contents of X position register.
Operat~on:
(DXR)
<-
X COORDINATE
LOAD X RELATIVE
15
I
I
14
13
12
I
11
These
I
10
101010111+
9
8
7
6
Octal code:
5
4
3
2
024ddd
1
o
X INCREMENT
I--~I------~!--~I--~----------------------Bits 0-10 define increment in X-axis coordinate in two's complement form.
These bits (sign extended) are added to contents of X position register.
Operation:
(DXR)
<-
(DXR)
+ X INCREMENT
3-3
{
3.3.1.2 MO'lTe Instructions. Move instruc tions specify X-' and! or Y-axis oel;7 pixel
positions on the CRT screen in terms of absolu.te data (specific coordinates) or
relative data (lengths along X and/or Yaxis). Except for a move short relative
instruction, a load instruction (paragraph 3.3.1.1) must precede Ii move instruction
when both X- and Y-axis data are to be changed.
IMV~l
MOVE X ABSOLUTE
15 14 1.3
"'j
I
T
I 0 I 1 0
I
12
10
11
r
I
I
I
9
8
7
1 I 0 I + I
I
6
I
I
.
Octal code;
,-5
3
4
2
0
I
X COORDINATE
.
1
Bits 0 ...10 define absolute X-a:ds coordinate in tTHO'S complement form. These
hi ts (sign extended) replace conte!lts of X po sf tion reg ister • NOTE: Mode 0 only
Oc tal code:
MOVE X RELATIVE
r._.,
{
05dddd
1
t
I
"'7\
~I
{
I ""
05Addd
f
o
,."-...,
I
. I
____________~~------------------------------_I
Bits 0-10 define incr€!U1ent in X-axis coordinate in two! s complement form.
These bits (sign extended) are added to contents of X pOsition register. NOTE: Hode
o only
Operatio.!!.:
-15
(DXR)
<-
(DXR) + X INCREME:r.7T
I~WY.A'
I
HOVE "I. ABSOLT.J'!E
14
!
I
13 .- 12
.....
I a I 1.
-
1
0
I
I
11
I
I
9
10
8
I
0
I
7
Octal code:
.5
6
3
4
2
06dddd
1
0
I
I
' I
I +
I
Y COORDINA'I'E
Bi ts 0-10 define .absolute Y-axis c:oorciinatEls in t~o I S complement form.
bits (sign e.."ttended) replace contents of Y position register.
Opera.~:
(DYR)
<-
15
r
I 0
I
l'fOVE Y REl.ATIVE
14
13
I
I 1
I
1
11
10
0 I 1
,+
12
I. I
I
These
Y COORDINATE
IMVYRI
9
8
7
6
Octal code:
5
4
3
2
064ddd
1
3-4
(DYR)
Y INCREMENT'
I
<. .- Y
INCREMENT
f
(
o
Bits 0-10 define increment in Y-axis coordinate in two's complement form.
ThesE! bits (s ign e.."ttended) are added to contents of Y po.sition register.
.Operati.9n:
I
I
I
I
Jr
-----.-. I
I
I
I
I
I
I
lMVS~1
15
Octal code:
MOVE SHORT RELATIVE
14
13
I
I
I
1 1 1 0 1+
1 1
,-
12
11
10
9
8
Y INCREMENT
7
6
0
1
5
+
4
:3
2
Iddldd
1
0
X INCREMENT
Bits 0-5 define increment in X-axis coordinates; bits 8-13 define increment in
Y-axis coordinate. Both sets of bits are in two's complement form. These bits are
added (sign extended) to contents. of X and Y position registers, respectively.
Operation:
<-
(DXR)
(DXR) + X INCREMENT
(DYR) + Y INCREMENT
<-
(DYR)
3.3.1.3 Draw Instructions. Draw instructions are similar to move instructions
(paragraph 3.3.1.2) except that they cause appropriate pixels to be illuminated from
the current X and Y positions to the specified X and/or Y positions. A point plot
relative instruction is also included in the draw instructions. This instruction
defines a dot represented by an intensified pixel.
-
DRAW X ABSOLUTE
IDRXAI
,15 ,14
I, 0 I 0
I
13
1
, ,10 I 9
I, 0 ,, + ,
I
12 .. 11
1
8
7
6
Octal code:
5
3
4
2
03dddd
1
0
X COORDINATE
Bits 0-10 define absolute X-axis coordinate in two's complement form. These
bits (sign extended) replace contents of X position register. NOTE: Mode 0 only
Operation:
<-
(DXR)
X COORDINATE
Octal code:
DRAW X RELATIVE
034ddd
-"
15
,
I
14
13
12
1
1
101 0
I
I
I
11
,
9
10
I
I
I 1 1+'
I-I
8
7
6
5
4
.'3
2
1
0
X INClEMENT
Bits 0-10 define increment in X-axis coordinate in two's complement form.
These bits (sign extended) are added to contents of X position register. NOTE: Mode
o only
Operation:
(DXR)
<-
(DXR) + X INCREMENT
. .:-j
3-5
(
r
IDRYAI
15
II
101
I I
DRAW Y ABSOLUTE
14
13
12
1
0
0
I
I
I
11
0
I
10
-
I
I + I
I I
7
8
9
,.
Octal code:
,
6.
5
4
,.
3
04dddd
1
2
I
I
I
Y COORDINATE
Pi
g.
~
-=q,
Bits 0-10 define absoluteY"'uis coordinate 'in two's comple1l1entfotm~,Tne13e
b1ts (sign extended) replace cont.ents of Y position 1;'e818ter..
(DYR)
q,eeration:
<- Y COORO!NA'l'E
IDRnl
15
I' r
I 0 I 1
I I
13
i
11
12
,.
10
i I ' .r
o
0
I
1
8
9
"
6
5
.4
044ddd
2
.,
1
<.....
-
IDiSiI
1
I
I
I
ORAW SHORT :RELATIVE
0
I
9
8
6
7
"
I +
1-
o
Y INCR£MENT
I
Octal code:
5
1
I
I
I
X INCREMENT
I
_,B11:s0"'5 define inc.rement in X-axis c.oordinate; bits 8"'13 define increment in
Y-a.::d.s coordinate. Both sets of bits are in two' s complement ,form. These bits are
added (sign extended) to contents of X and Y position
reg1stet:s) respec.tively ..
,
.
0;e,rat;ion:, (DXll) <- (On) + x tNCRFMENT
(Dn) (-,. (DYR) ... 1. INCREMENT
II
I 1
I
I
I
14
I
1 1
l~.
+
,-
11
12
1.
10
9
"
INCREMENT
8
I
I
'I
7
5
6
I
0
0
4
3
I
-
I+
I
2
'.
,
1
0
X INCREMENT
Bits 0-5 define increment in X-aXis coordinate; bits 8-13 define increment in
Y"'uis coot'dinate. Both sets of bits a.re in t140'$ com.plement fot'lll .. These bits are
added (s1i1l extended) to contants of X and Y position registers, respectively. A
dot is displayed as one intensified pi."'(el.
(Dxa)
(DYR)
<<_
r'
;",:,,.1
(DXB-)
(Dn)
+
+
X INCREMENT
'l INCREMENT
f
I
I
(
lmil
15
"
I '. .'
lddOdd
432
01+
"
-
"
(Dn.) + Y INCREMENT
15 14 13 11 11 10
I
I
I
(
','!
-0
I 1 I ... I
I I-I
(DYR)
"
,
Octal code:
Bits 0-10 define increment in Y-aXis coordinate in two' scomplement form.
These bits (sign extended) are added to contents of Y position register.
02eration:
" .i
{
(
DRAW Y RElATIVE
14
l'~~
0
,
r
I
l
I ,-,
IpPYAI
15
I
I
I
0
(ElM) Octal code:
POINT PLOT Y ABSOLUTE
14
I
13
I 1
I
0
12
11
I
I
1 I 0
!
10
9
8
7
I +
I
5
6
4
3
2
1
05dddd
0
Y COORDINATE
The Point Plot Y Absolute instruction provides the ability to point plot along
the Y direction without the need for the MVYA instruction. The Point Plot is
displayed as one pixel. Normally, LDXA precedes this instruction.
(DYR)
Operation:
-
<- Y COORDINATE
paIN! PLOT Y RELATIVE
IpPYRI
15
II
14
13
12
I
11
I
10
9
8
7
4
3
2
1
o
i__~I_______I~~I__~~______________~____~
~
t"
5
6
054ddd
Y INCREMENT
101101111+
__ I. - -
I
(ElM) Octal code:
The Point Plot Y Relative instruction provides the ability to point plot in the
Y direction without the need for the MVYR instruction. The plotted point is
displayed as one pixel.
Operation:
(DYR)
<-
(DYR)
+
Y INCREMENT
POINT PLOT TABULAR ABSOLUTE
15
I
I
I
I
I
I
l ' :,
0
I
I
I
F
I
I
I
14
0
x:
13
0
x:
12
0
X
I
I
I
11
l'
X
10
I
9
1
8
1
7
1
6
I
4
3
2
1
0076dd
0
I
0 IROTI
I
-+
5
(ElM) Octal code:
TAB INCR
I
COORDINATE
The PPTA instruction specifies a sequence of X or Y coordinate depending on the
orientation.
Bits 0-4 represents the X or Y Tabular Increment between successive points.
Bit 5
a
~
0 indicates horizontal orientation. Coordinates are Y values.
1 indicates vertical orientation. Coordinates are X values.
Bit 15 (in the data words)
= 0 indicates an intermediate point.
'" I indicates the final plotted point and the end to the variable length
instruction.
3-7
J
.Q.P.el:a ti.9p::
For horizontal orientation:
I :.
(ROT'" 0)
... 1
(DXR)
(DYR)
<<-
(DXR) + tabular increment
Coordinate
For vert,ical orientation:
(
(ROT" 1)
I
(DYR)<- (DYE.) + tabular increment
(DXR) <- Coordinate
····1
[
(ElM) Octal code:
POINT PLOT TABULAR RELATIVE
15
I
I
I
I
I
I
I
I
I
0
F
14
I
I
I
13
0
X
0
X.
12
0
X
I
I
I
11
10
1
L
9
1
8
1
7
1
6
I
5
+
3
2
1
, .. J'
0
I
1 IROTI
I
X
4
0077dd
TAB INCR.
I
INCREMENT
I
I
I
I
I
I
I
I
I
The PP'l'A instruction specifies a sequence of X or Y increment depending on the
orientation.
Bits 0-4 represents the X or Y Tabular Increment between successive points.
Bit 5 .. 0 indicates horizontal orientation. Increments are Y values.
.. 1 indicates vertical orientation. Increments are X. values.
Bit 15 (in the data words)
:: 0 indicates ,an intermediate point.
:I 1 indicates the final plotted point and the end to the variable length
ins truction.
Operation:
For horizontal orientation:
(DXR)
(D,("R)
<<-
(DXR)
3-8
<<-
= 0):
(DXR) + tabular inc.rement
(DYR) + increment
For vertical orientation:
(DYR)
(ROT
(ROT:I 1):
(DYR) + tabular increment
(DXR) + increment
I
I
r
I
I
r
I
r
I
3.3.1.4 Text Instructions. Two instructions are used to draw characters. One
instruction causes a single steady or blinking character to be drawn at the current
position. The second instruction enables two characters to be drawn and the
position incremented automatically when each is complete. Character size and
orientation data are not included in the text instructions. These parameters as
well as the values used to increment the X~ Y position are determined by display
control instructions (paragraph 3.2.4).
'-;'-.
-
I CHARI
15
I
I
I
1
DRAW SINGLE CHARACTER
I
14
I 0
I
13
0
12
1
I
I
I
11
1
10
9
1
B
I
8
I
I S I
I I
7
1
6
Octal code:
5
4
3
2
116ddd (blink)
117ddd (steady)
1
CHARACTER ASCII CODE
0
I
I
I
Bits 0-6 specify ASCII code of character to be drawn at location defined by
contents of X and Y position registers. Bit 9 specifies whether the character is to
blink or be steady (1 indicates steady). Bits 0... 6 replace contents of character
register. Bit 8, the shift bit, indicates either the standard character set (1) or
the extended optional character set (0). This shift bit, applies only to the
character specified in the CHAR instruction. It has no effect on subsequent text
instructions. Bit 9 replaces blink bit in display Z register. After a character is
presented, the starting location is returned in X and Y position registers and the
previous state of the blink bit is restored in the display Z register.
Operation:
(DCR) <- CHARACTER ASCII CODE
OZR (blink bit) <- Bit 9
DZR blink bit is restored following instruction execution
NOTE
On customer systems containing special characters
or speCial symbols, the shift out code (character
code octal 16) can be used to display these
symbols. This is done by executing a CHAR
instruction containing the shift out code.
FolloWing the shift out code is a group of TEXT
instructions to display the selected special
symbols. After displaying special symbols, the
shift in code (character code octal 17) must be
used to permit display of the standard characters
again.
3-9
i
i.->
-
r
Inti
15
r
DRAW TWO TABULAR CHARACTERS
14
I
I 1 I
I .1.
13
12
I
i
11
9
10
8
CRAUCTER 2 ASCII CODE
7
I
1
It ..
6
I
I
5
Octal code:
4
3
·2
1
Idd2dd
I····
0
CltARAC'rER 1 ASCII CODE
I '.
"Ojo".
~
Bits 0-6 specify ASCII code of first character to be drawn; bits 8-14 specify
ASCII code of second character to be drawn. Beginning loeation for each charaeter
(O(
is defin~ by X and Y posit1on registers. Bits 0-6 reylace the contents .of eharactar register. ,'The charac:ter is presented. Then bits 8-14 replace contents of
charaeter reg1stet:. When a charaeter is completed, the X position register (Y
position register £lor rotated characters) is autol'llatically incremented by the contents of text increment register. If ASCII code for a NULL character is specified,
no character is drawn and the X (or y) pOsition register is not incremented.
[
0psl:'.ation:
~raw
character 1 at position
(on)
<-
(Dxa)
+
on,
OYR
<-
(DYR)
(DTI) [(Dn.)
+
(DTI) for
.rotated tut]
R.epeated above for character 2
Three control characters are used in the ·CHAR or '.tXT insttuetiQntodetermine
text posit1on on the screen (see table A-9).
TheSn character defines the left urgin' of screen as the present X pod tion
(Y position for rotated text).
(um)
[(L..'1R.)
<- (on)
<- (on)
(
of rota ted text J
The Carriage letum CR character sets the X position (Y position for rotated
text) to the previously defined left margin.
<-
(
"
[(OYR) <-(L..'iR) for rots. ted text]
(
'The Line Feed LF character dect.ements the current Y position (or increments the
current X position for rotated tut) by the am.ount previously defined as the line
increment (see theLDTI instruction).
I
(DXR)
(LMR)
(on) <- (on) - (DLI)
[(Dxa) <- (DXa) + (DLI)
for rotated text]
(
(
[
(.
3-10
t
TI1e follOwing information describes the RAl1 character generator.
Summary of features:
1.
The font size of the standard character set determines the font size which
must be used in the extended and RAM character sets. Vertical misalignment of the characters will result i f this concii tion is not met.
2.
In the RAM set, 32 character codes (00°8-0378) are reserved for
control functions; 96 character codes (04°8-1778) are for displayable
characters.
3.
Multiple character tables are possible.
4.
All standard character sizes and rotation apply to RAM characters.
5.
ASCII code 0338 is the cont.rol code used to enter the R.'lli character set.
6.
The base address for the RAM table must be loaded prior to using RAM
characters for the first time. Reloading is necessary only when multiple
tables are in use.
7.
The "building" of the RAM character table must conform to the guidelines
that follow.
8.
The character table must be based at 4K boundaries and may be placed in
any bank of memorJ. Care must be taken not to violate any reserved areas
of memory in bank O.
9.
RAM Control Characters
"
NULL (0008) performs same funct.ion as in standard and extended sets.
SO (0168) exits RAM character set and enters entended set.
51 (0178) exits RAM character set and enters standard set.
Guidelines
The RAM address of a specific character is determined by shifting the 7-bit
ASCII code four places to the left, filling the four least significant bits with the
LSB of the ASCII code, and "oring" this value with the base address loaded by the
LDCG (load character generator) instruction (see page 3-23). The equation to
calculate the RAM address of a character in decimal is:
ASCIIIO + base address1Q (+15 if ASCII1Q is odd)
character
= address
of RAM
Change 1
3-10A
f
e. g.
~
1001000
= ASCII
c
OOOOOlOOl!OOOOOO
Modified ASCII code
OOlOOl001!000000
RAM address assuming base address of 200008'
Base
addre.ss
The digi ta.l gra.phic can troller microcode checks the LSB of the RAJ.'1 addre~s s to
determine the direction to proceed through the RAM. If the address is even, the
digi tal graphic con troller increments the aAI.'1 address by 1 to fetch the succeedi.ng
c.haracter da.ta. If the address is odd, the digital graphic controller decre!llents
the RAM address. This .implies that the character definition is referenced to the
initial character address calculated. An e...-x:ample oihow the Land Mcharacters
would apr..ear in a RAM table based.at 200008 using their assigned ASCII eodes is
shown below.
1001100
""
0010010011000000
1001101
0010010011011111
L character ASCII code
..
R..Ui addr as s for L character 2230°8
""
M charac.ter ASCI I code
""
RAM address for M character 22337 8
The m1lPtimUtll width of a character is fixed at 7 "pixels. Bit 0 of the 8-hi t byte
is a. flag that informs the digital gtaphic controller that the character i'9
ccmplete. Character length may be up to 16 pixels and may be shifted as in the ease
of lower case char,acters.
(
(
[
I
f
{
I
r
The load character generator address instruction loads the base address of the
The character table must be based at 4K boundaries in memory.
I
Allowable character table base addresses (Batik: ¢):
[;
R.&'1 character set.
4000
10000
14000
20000
24000
30000
34000
40000
44000
50000
54000
60000
64000
70000
74000
100000
104000
110000
114000
120000
124000
130000
134000
f
,
f
I
3-10B
Change 1
r
I
,.
Example of a refresh file using the
4700
30000
117601
140301 }
174201
100277
117600
.-.t
117601
112217 }
130711
141674
117600
RA~
character set:
Load character table address
Base address
Enter RAM character set
RAM characters
Exit RAM character set
Enter
RJu~
character set
RAM characters
Exit RAM character set
Change 1
3-10C
[
r
(
RAM
ADDRESS a
RAM
CATAS
r
200
I
7 6 54 3 2 1 0
22300
20.0
2JXl
r
200
1
200
200
I
200
200
377
f
(
I
[
203
2.02
I
Z]2
202
202
1
22337
222
f
25,2
306
t
202
I
END OF CHARACTER BIT
H·8()'0444-1 00
Example Clf Two 7 X 9 Characters in RAM
(
r
(
r
J-10D
Change 1
[
3.3.1.5 Conic Instructions. Two conic instructions are used to specify 90-degree
segments and axis lengths of ellipses to be displayed. One is a load instruction
that specifies X-axis data. The second is a draw instruction that specifies Y-axis
data and presents the ellipse. Bits in both instructions specify what combination
of 90-degree segments will be unblanked when an ellipse is drawn. Axes of all
ellipses drawn using these instructions alone lie parallel to the X and Y axes of
the display indicator •
•
NOTE
Both conic instructions are required to define
each ellipse even when parameters specified by one
instruction must precede the draw instruction. If
the draw instruction is used alone, a circle will
be d1splayed with a radius equal to the length
specified for the semi-Y axis.
ILBiXI
.............
15
"
.'
I
I
I
0
I
I
I
LOAD CONIC X aEGISl'ER
14
13
1
1
I
1
I I
8
7
I 0 IQIIIIQII
I I
I I
65
Octal code:
43· 2
07dddd
1 .0
X SEMI-AXIS LENGTH
-.'
Bits 0-8 define semi-axis length of ellipse (distance from ellipse center to
its perimeter) along X axis of CRt. Bits 9 and 10 s,pecify unblanking (l indicates
unblank) in quadrants QI (upper right) and QIII (lower left), with respect to the
.major and minor axes (if rotated) of the ellipse. All of bits 0-10 replace contents
of X conic register.
Operation:
-
(KXR) X SEMI-AXIS LENGTH plus QI and QIII bits
IDRKYI
15
0
c~J
I
I
I
DRAW CONIC Y
14
13
12
1
1
1
11
I
I
I
I
10
I
9
I
8
7
Octal code:
6
5
4
3
21
07dddd
0
I
1 IQIVIQIIIY SEMI-AXIS LENGtH (OR CIRCLE RADIUS) I
I
I
I
I
Bits 0-8 define semi-axis length of ellipse (distance from ellipse center to
its perimeter) along Y axis o~ CRT. Bits 9 and 10 specify unblanking (1 indicates
unblanking) in quadrants QII (upper left) and QIV (lower right), with respect to the
major and minor axes (if the ellipse is rotated). All of bits 0-10 replace contents
of conic Y register. The ellipse is drawn as defined in conic X and Y registers
with ellipse center at location defined by X and Y position registers. The ellipse
is unblanked in quadrants specified by bits 9 and 10 in the conic X and conic Y
registers. If a DRKY instruction is not preceded by an LDKX instruction, bits 0-10
of the DRKY instruction replace the contents of the conic X as well as the conic Y
register. The result is that a circle with a radius equal to the length specified
3-11
--....:.
by bits 0-8 is created. Bits 9 and 10 then specifyunblanldng for the upper and
lower semicircles, respectively.
Operation:
Preceded byLDKX instruction:
(KYR)
<- Y;
SEMI"'A.XIS LENGTH plus QII and QIV bits
Not preceded by LDKX instruction:· .
(KYlt)
(IaR)
<- Y
<- Y
f.
SEMI"A.,.,{I.S LENGnt plus Q!I and QIV bits
SEMI-AXIS LENGTH plus QI! and QIV bits
3.3.2 SEQUENCE CONTROL INSTRUCTIONS. Thirteen instructions are used to control the
sequence of program execution an4. timing by thedigit.a.l graphic controller. These
instructions include unconditional jUlllP,conditiona1jump, subroutinet linkage,
halt, wait, and update instructions.
The.JllMP, J'MPZ, Jl?U , CALL, CALlt and R'l'RN utiliZe an 18-bit addres iii if the E1M
bit is on. In this case it is reComll1ended that you use the utendedform of the
Il1nemon1c for clad ty.
.
.
3.3.2.1 Uncond1ti.91.'lat, ~~p!nstrue.'tions. Uneondit:l.oaal jump instrUctions permit
program control of the graphic controller to be transferred directly or indirectly
to a speCific address in memory (absolut.e jump) or to an addreu remoVed from the
current loeation by a speCified increm~iU1t (relative Jump). The jump short relative
inettu¢.tion (JMPtt) can also be used as a np"'opera.tion instruction (NOOP) by.
specifying a jump inere1l1ent of 2.ero bytes.
IJ'IJW'(E~1
1S
lli""!"'''''''''
I
14
13
I 0 I 0 0
I
I
I I 1
I (AlS) IA14 AI3
I
I
12
0
I
I
I
11
0
10
0
,
9
8
I
I
I
I
0010Xd dddddd
Octal code:
JUMP
0
7
6
0
()
~
'
X
4
3
X
XI
.
I
I
u.
,
.
At
I
I
AO I
I
JUMP is a two-word instruction used for unconditional transht' of program
control (direct or ind1rect) to aspeeif1¢. location in memory. The fir!lJt word
identifies the instruction. 'The second word spee1fiesa direct or indireet address
(for ElM ... 0) to which program contrQ1 is to be transferred. The JUMPE, jump
extended address instruction, uti.,liz.es bits 0""1 of the first word as bits A16-A17 of
the extended 18 bit addrQss" Also, when in extended mode bit 15 represents address
bit 15 (A15) not the indirect bit !.
'the specified address may be the address of any even....numbered byte from 00000
to 777776 (octal). If bit 15 of the second word is set to 0 (direct addrelllsing) and
ElM'" 0, control is transferred to the address speCified by bits AO-A14. If bit 15
is a 1 (indirect addressing) and ElM
0, bits AO-A14 specify the 1l1emQryaddress
that contains the required data. In this case, the contents of the specified
:;I
(
..""
T,
(
l
[
I·"!
r. .
1
2
0
. I . I'
I
,
X A17 A161
A2
JUMP ADDRESS
[ .~
[
.,....
.,-:
..
(~
r
.~.:
[
.-
(
{,
[
address are used as the location to which program control is transferred. Note that
direct addressing canrtot be used for addresses greater than 777776 (octal). Multilevel indirect addressing may be used.
Operation:
•
<
,1
Direct:
Indirect:
IJRMP(E) I
14
13
I
+
.
<- JU~1P
<-
(JUMP
I
I
0
0
ADDRESS
ADDRESS)
.
JUMP RELATIVE
15
0
(DPC)
(DPC)
OOllX."{ dddddd
Octal code:
11
10
9
8
7
6
5
4
3
2
1
0
a I a
a
1
a
a
1
x
X
x
x
x
x
12
I
I
I
JUMP INCREMENT (IN EVEN
IA14
Al
BY'l'ES)
AO
I
JRMP is a two-word instruction that causes unconditional tranSfer of program
control to a relative location in memory. The first word identifies the instruction, the second word specifies an even number of bytes by which the program counter
is to be incremented. The jump increment is added modulo 2 16 (any carry is
ignored) ~o the contents of the program counter which is pointing to the address
following the location of the jump increment word. The result is used as the
address of the next instruction to be ~~ecuted by the digital graphic controller.
Relative jurnps from -100000 to 77776 (octal) bytes can be accomplished using this
instruction.
If EIM = 1, the JRMP(E) instruction utilizes 18-bit addressing. If the
causes the 16-bit program counter to overflow, the bank register PGR is
incremented or decremented appropriately.
incremen~
Operation:
(DPC)
<-
(OPC) + JUMP INCREMENT
Octal code:
JUMP SHORT RELA!IVE or NO OPERATION
005ddd (JMPR)
005000 (NOOP)
or
INOOP I
15
14
13
I
o I a
a
3·
2
11
10
9
8
7
0 I 1
0
1
+
JUMP INCREMENT (IN EVEN
12
I
6
5
4
1
a
I
a I
____~I___________~I________~____________________B_Y_T_ES~)~____ I
Bits 0-8 specify, in two's complement form, an even number of bytes by which
the program counter is to be incremented (or decremented). These bits are added to
the contents of the program counter which is pointing to the address following the
location of the JMPR or NOOP instruction. The result is used as the address of the
n~~t instruction to be executed by the digital graphic controller.
Relative jumps
from -400 to 376 (octal) bytes in either direction can be accomplished using this
3-l3
(
instruction.
instruction.
Specifying a relative jump of 0 bytes results in a. no-operation
Operation:
<-
(DPe)
(DPe)
I
+ JUMP INCRltMENT
3.3.2.2 Conditional JumE Instructions. Two conditional jump instructions are
provided to permit progtam control to be transferred or to continue in normal
sequence as deteZ'lllined by testing the contents of general purpose register O. Jumps
are executed when the con·tents of this register are not equal to zero. One instruction causes a conditional jump, d.irect or indirect, to a specific addre.ss in memory
(absolute jUlnp), The second instruetion causas a conditional jUlnpto an address
removed from the current location by a specified increment (relative Jump).
Q
I t
I
I
I
I
14
., 1,
0
0
12
11
I
,10
0 I 0
I
0
8
9
I
1 .I
7
6
0
1
,
5
0
I
I
4
X
JUMl? AnDRESS
!(AU) lA14 AU
!
3
1
2
0
t
X
(
Octal code: 0012X dddddd
I
I
[
(
JUMP IF DISPLAY REGISTER 0 CON'l'ENTS #J
15
[
I
(
X Al7 A16!
X
A2
Al
!
I
I
AO I
!
JMPZ is a t'Wl)"'word instruetion used for the ·condit'ional t1;.'ansfer (direct at
ind.1ract) or program. control to a speeific me!llory location. The first word identi'"
fies the instruction and causes the o,ontents of general register 0 (DRO) to be
tested. The seo,.ond word spee:f.fi.es a direct or indirect addl'ess to which program
eontrol 1s conditionally to be transferred.
The JMPZ!, conditional jt.ml.p extended addr~u;s instruction, uses bits 0-1 of the
fint word as bits A16-A11, respectively, of the extended 18 bit: address. Note that
for ElM "" 1 bit 15 represents the addreSS bit: (Al5 ) not the indirect bit I.
The speo,iUed address utay be the address of any even-nmbered byte frout' 00000
to 77776 (oo,ul). Program o,ontt01 is transferred only when (ORO) J. O. If bit 15
of the second wotd is set toO and EIM "" 0 (direct addressing), control is transfet'red to the address specified by bits AO-A14. If bit 1S is a 1 and EIM-O
(!ndireet addreuing), bits AO-Al4 specify the memory address tha.tcont-ai.ns· tha
required data. tn this case, the contents of the speo,ified address is used as the
10o,ation to which program control is t;:rat'lsferred. If (nRO) "" 0, prograJ;ll control is
not: transferred and the progralll continues by eXecuting the instruo,tion at en€!
addtess that Uunedia.tely follows the seo,ond word of theJMPZ(E) instruc Uon (this is
the address to wnj;o,h the program counter is point.ing). Note that direct addressing
cannot be used for addresses greater than (7) 77116 (oo,tal). Multilevel indirect
addnsssing lllay be used.
012eration:
Direct:
Indirect:
(ORO) " 0:
(ORO) "" 0:
(ORO) '" 0:
(DRO) "" 0:
(DPC <(Ope)
I
r
r
(
JUMP
(
<<-
I
<-
(OPC)
(OPC)
I·
ADDRESS
(DPC)
(JUMP ADDRESS)
(DPe)
(
IJpRZ(E) I
JUMP
RELATIVE IF DISPLAY REGISTER 0 CONTENTS ,. 0
Octal code:
14
15
13
I
'J
0
+
0
I 0
I
I
11
10
9
I
0 I 0
I
0
1
12
IA14
8
7
6
5
4
3
2
1
0
I 0
I
1
1
X
X
X
X
X
X !~
I
I
INCREMENT (IN EVEN BYTES)
JUMP
0013X.X dddddd
A1
I
I
I
AO !
I
JPRZ is a two-word instruction that causes a conditional transfer of program
control to a.·relative location in memory. The first word identifies the instruction
and causes the contents of general purpose register 0 (DRO) to be tested. The
second word specifies an even number of bytes by which th~ program counter is
conditionally to be inc'1'emented. Prog'1'am control is transferred only when (DRO) {t
O. When (DRO) {t O. the jump incr$1l1ent is adde-d mo-dulo 216 (any carry is
ignored) to the contents of the program counter which is pointing to the address
follonnl the location of the jump increment word. The result is used as the
address of the next,instrUction to be executed by the graphic controller. When
(DRO) ,. 0, program control is not tl'ans.ferred and the program continues by executing
the instruction that immediately follows the second word of the JPRZ instruction.
Conditional relative jumps from. "'100000 to 77776 (octal) bytes can be accomplished
using this instruction.
.-
If ElM" 1, then the JPRZE instruction utilizes 18-bit addressing. If the
increment causes the 16-bit program counter to overflow, the bank. register PGR is
incremented or decremented appropriately.
Operation:
(DPC)
(DPC)
(DRO) " 0:
(DRO) "" 0:
<<-
(DPe)
+ JUMP INCREMENT
(DPC)
3.3.2.3 Subroutine ItlS1:ructions. Four subroutine instructions are provided to
permit calls to and returns from subroutines as required. Calls may be made to
subroutines located at a specific address in memory (absolute calls) or to sub- routines at an address removed frOm the current location by a specified increment
(relative calls). The digital graphic controller is capable of calling subroutines
between different me1llOry banks by the use of the extended address instructions
CALLE. A jump-and-lllark instruction is also included which permits direct or
indirect-calls to be made to subroutines at specific memory locations.
!CALL(E) !
.;
15
0
I
.•)
Al5
'.:"l-f
CALL SUBROUTINE
14
13
I 0
I
0
I
A14
Octal code:
0021Xd dddddd
11
10
9
8
7
6
5
4
3
2
0 I 0
!
1
a
0
0
1
X
X
X
X A17 A16!
!
12
I
SUBROUTINE ADDRESS
1
0
I
A2
Al
AO
I
I
I
j
3-15
"~-'1
('
-
(
CALL is a two-word instruction that calls a subroutine from a specific location
in memory. The first word ident:ifies the instruction; the sec.ond word specifies the
address that contains the first instruction of the desired subroutine.
The CALLE, call extended subroutine address instruction, utilizes bits 0-1 of
the first word as bits A16-A17, respectively, of the extended 18 bit subrolltine
address.
The specified address may be the addreSS of any even-numbered byte from 000000
to 777176 (octal). When a CALL instruction is executed, the contents of the program
counter (which is pointing to the address following the location of the sllbroutine
address word) is pushed onto the graphic controller stack. This saves the address
of the instruction to be executed following completion of the subroutine. Bits
A16-A17 are loaded into the bits 14 and 15, respectively, of the bank register PGR.
The contents of the second word of the CALL instruction. is then loaded into the
program counter and used as the location of the next instruction to be executed by
the digitalgraphia controller.
(DSP) <- (DSP) - 2
(Top stack location)
<-
(DPC)
I
;i
\
-"
I
.....,
i
f
I
[
':"'j
I
f
IF EIM ... 0, then:
(DPC) ~- SUBROUTINE ADDRESS
(
ELSE [EIM
1]
(DSP) <- (DSP) - 2
(Top stack location) <- (PGR)
(DPC) <- SUBROUTINE ADDRESS
:II
I
END
IC~R(E)
15
0
+
(
I
CALL RELATIVE
i
I
I
14
0
A14
13
I .
12
I
I
0
0
I
I
11
10
9
8
0
1
a
a
Octal code:
,
7
6
5
1
0
1{
4
X
SUBROUTINE INCREMENT (IN EVEN
3
X
0022XX dddddd
2
X
1
0
X
x
Al
AO
BY~S)
CALR is a two-word instruction that calls a subroutine from a relative location
in memory. The first 'Nora identifies the instruction;. the second word specifies an
even number of bytes by which the program counter must be incremented to obtain the
address that contains the firs tins truction of the deSired subroutine. The
specified increment may be any even number of bytes from -100000 to 77776 (octal).
When a C.\LR instruction is executed, the contents oithe program counter (which is
pointing to the address following the location of the subroutine increment word) is
pushed onto the digital graphic controller stack. This saves the address of the
instruction to be executed folloWing completion of the subroutine. The contents of
the second word of the CALR instruction is then added modulo 2 16 (any carry is
-ignored) to the contents of the program CQllnter and the result used as the location
of the next instruction to be executed by the graphic controller.
3-16
I
(
I
I
(
I
(I
I
.-
If ElM" 1, then the CALRE instruction utilizes IS-bit addressing. If the
increment causes the 16-bit program counter to overflow, the bank. register PGR is
incremented or decremented appropriately.
IF (EL.'! .. 1) then:
.. (DSP) <- (DSP) - 2
Operation:
(Top stack lo~ation) <- (PGR)
(DSP) <-- (DSP) - 2
(Top stack location) <- (DPC)
(DPC) <- (DPC) + SUBROUTINE INCREMENT
ELSE [ElM'"" 0J
(DSP) <- (DSP) - 2
(Top stack location) <- (DPC)
(DPC) <- (DPC) + SUBROUTINE INCREMENT
END
IRTItN~E)1
Octal code:
ItE'l'URN
0023XX
,-.
15
i
I
. I:..,....
0
r
..
I
I
I
14 . . 13
0
0
12 .11
0
I
I
I
0
,10 ..
.
1
9
0
,
8
I
I 0
I
7
I'
6
1
I
S
t
.
I X
I
4
X
2
1
I
X I X
0
X
X
3.
"
A RTRN instruction is normally the last instruction of a subroutine called by a
instruction. It causes program control to return. from the subroutirte to the
main program. Whel1 a RtRN instruction is executed, the COl1tents of the location .
indicated by the digital graphic controller stack pointer is popped from the stack,
loaded into the program counter, and used as the address of the next instruction to
be executed by the digital graphic controller.
CALL(E)
,.
Operation:
!F (ElM" 1) then:
(FGR) ~ (Top stack location)
(DSP) <- (DSF) + 2
(DPC) <- (Top stack location)
(DSP) <- (DSP) + 2
ELSE [ElM" 01
(DPC) <- (Top stack location)
(DSP) <- (DSP) + 2
END
. _.i
, !
u.l
}
:.,-1
!
3-17
r
~,
r
IJ~1'!(.~~ I
15
JUMJ? AND MARK
14
13
II
I a I 0 0
I
I
I I J
I CAIS) IA14
I
I
Octal code:
0020XX dddddd
I
f
-\
r
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
a
a
x
x
x
x
x
xI
JUMP ADDRESS (IN EVEN BYTES)
Al
~
AO
I
I
JMPM is a t'Wo"'word instruction used for direct 07: indirect calls to subroutines. The first word identifies the instruction; the second specifies a direc.t
or indirect address to be used for storage of a return address from the subroutine
being called. The specified address m,ay be the address of any even-numbered byte
from 00000 to 77776 (octal). If hit 15 of the second word is set to 0 and EL.'1 "'" 0
(direct addressing), the return address is stored in the location specified by bi ts
0-14. If bit 15 is a 1 and EIM .= 0 (indirect addressing), bits 0-14 specify the
memory address that contains the required data. In this case, the contents of the
specified address are used to designate the location in which the return address
will be stored. When a JMPH instruction is exec.uted, the contents of the program
counter (which is pointing to the address followng the loca.tion of the jump address
word) is stored in the direct or indirect a.ddress specified. This saves the
location of the ir4struction to be executed follOwing completion of the subroutine.
Exec.ution of the called subroutine then begins at the address immediately following
the location in which the return address is stored. When the subrOutine is
c.ompleted, return to the main program is effected by an indirect JUMP instruction
that references the return address stor?-ge location. Nate that the JMPM instruction
cannot be used for direct addressing of addresses greater than 77776 (octal).
Multilevel indirect addressing may be used.
Note that for EIM "" 1 bit 15 of the second word represents
(A15) rather than the indirect bit I.
Operation:
j~p
address bi t
Direct:
(JUMl' ADDRESS) <- (DPC)
(D PC) <-JUMP ADDRESS +
2
Indirect:
(Address contained in JUMP AD-DRESS) <- (DPC)
(DPC) <- (Address c.ontained in JUMP ADDRESS) + 2
I
~'-:
[
(
1
;, .J
r
r
(
(
I
[
I
(
(:
I:
rI
3-1,9
:1
I
i
"
'r;
3.3.2.4 Linkage Instruction. A linkage instrut.ction is provided so that synchronized linkage can be effected between a progra~ being executed by the digital
,graphic controller and a program being executed; by the display processor. This
enables the additional power of the display processor to be used to mod.i£y or
process refresh file data as required. Details concerning applications of the
linkage instruction are contained in Section 7.,:
ILINK(E) I
15
0
SYNCHRONIZED LINKAGE
14
I
13
12
0
0
,I 0
I I I
I (A15) I
I
I
I
I
I
Octal code:
0040}{.'{ dddddd
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
X
X
X
X
X
X
LINK ADDRESS
0
LINK is a two-word instruction. The first word identifies the instruction; the
second word specifies a direct or indirect aiidress to be used for storage of the
address that follows the location of the LINK instruction. The specified address
may be the address of any even-numbered byte from 00000 to 77776 (octal). If bit 15
of the second word is set to 0 (direct addressing), the storage address' is the
location specified by bits 0-14. If bit 15 is a 1 (indirect addressing), bits 0-14
specify the memory address that contains the required data. !n this case, the
contents of the specified address designate the location to be used for storage.
When a LINK instruction is executed, the contents of the program counter (which is
pointing to the address following the location of the link address word) is stored
in the direct or indirect address specified. This saves!:he address of the
instruction that immediately follows the LINK instruction. The graphic controller
then halts and interrupts the display processor. . Restarting of the graphic controller is controlled by a command from the di.splay processor as described in
Section 7. Note that the LINK instruction cannot be used for direct addressing of
addresses greater than 77776 (octal). Multilevel indirect addressing 111ay be used.
All indirect addresses 'are accessed in the bank defined by the bank register.
(See PGR in Section 4.) The direct link address is accessed in bank O.
Note that for ElM'" 1 bit 15 of the second word represents the LINK address bit
(AIS) rather than indirect bit I.
Operation:
Direct:
(LINK ADDRESS) (- (DPC)
Indirect:
(Address contained in LINK ADDRESS) (- (DPC)
'-
,
J
... ""
3-19
.1
I
3.3 • .2.5 Halt and Wait Instructions. One halt, one wait a.nd update instruction are
inc.luded in the digital graphic. controller sequence c.ontrol instructions. The halt
instruction is used for debugging ,vhile the ,,,ait instruction ensures that the
displayed image is synchronized lilith the update of mapping memory.
(
I'
.,\
IHREFI
.
HALT REFRESH
15
0
14
13
12
0
0
0
I
I
I
11
10
9
•8
0
0
a
0
I
I
I
Oct: al code:
OOOOXX
7
6
5
4
3
.2
1
a-_. !
a
0
x
x
x
x
x
xl
I
The HREF instruction causes the graphic controller to halt and to send an
interrupt to the display processor. This instruction is normally used for debugging
purposes. Whether the interrupt is enabled and the manner in which it is processed
are determined by the software being executed by the display processor. Restarting
of. the digital graphic controller is controlled by a command from the display
processor as described in Section 7.
0Eexation:
Digital graphic controller:
Halt
,
Process interrupt (if enabled)
"'1
i
, I
f
I
r
(
r
I
I
I
r
3-20
l
r
I
r
r . ,'
Send inten"Uptto display proc.essor
Display processor:
:1
[
I
-.. -
WAIT
IWATEI
15
I
I
I
0
I
I
I
14
13
12
0
0
0
I
I
I
Octal code:
0070XX
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
0
0
0
X
X
X
X
X
X
The WAn: instruction is used to control the. displaying of a refresh file each
time a frame sync pulse is generated. One and only one WAI! instruction is used in
each refresh file. The mapping memory is cleared each time the WAtE instruction is
accessed by the digital graphic controller. The mapping memory being displayed is
swapped and then the second (non- displayed) mapping memory is cleared when WATE is
encountered. The second mapping memory then becomes the displayed memory_ This
process is repeated each time the WATE instruction is accessed by the digital
graphic con troller •.
-
IWiltl
UPDAT! VIDEO CONTROLLER REGISTERS (EIM)
14
1S
I
I
I
0
I
I
I
0
13 . , 12. 11
10
9
8
7
1
1
1
0
1
0
0
I
I
I
Octal code:
6
5
4
1
X
X
3
X
2
I
I x:
I
0073XX
1
0
X
:{
The UPDT instruction is used to update the selected video controller registers
frau t.he corresponding RAM register without effecting pixel memot"y. It is used, for
example, to display the full screen cross hair cursor, display a split screen, or
change video controller status •
..
..
Change 1
_.J
!
3-21
I
(
-f·..-;
3.3.3 REGISTER INSTRUCTIONS. Register instructions are used to modify the c.ontents
of general purpose registers of the digital graphic controller (display registers)
and to control graphic eonttoller stack operations ..
LOAD DISl'tAY REG.tSTER IMMEDIATE
I
15
I
14
.
,..
13
I 0 I 0
I I
12
I
II
I
10
0 1···1
0
I
I
I
J
6..
..1
a
1
I·
7
8
9
0
1
0
.
,
Octal code:
I
5.
I ....
Q061dd dddddd
o
'., .
f··
nRJ;
I
I
i i ..
"
DATA
I
I
,I .
I
I
(
r
(
---------------------------------------------,
two-word i9tructiOn. used to load data into one of the display
LDD! 1s a
registe.rs of the lliigital graphic controller. The first word identifi.es the
insttuct:lon and the d:lsplay tegister into W'hieh data is. to be loaded. 'The second
word contairut the data to be loacled into the designated register. Bits Oto 5 of
the first word specify, in binary form, the number of the .register to be loaded.
General purpose registers DRO through DR3 are designated by 00, 01,10, and 11
relpec.tively.. See table A"'6 for the complete list of registers that c.an be loaded •
.
1S
14
I' I
I 0 I 0
I I
I
13
0
12
°
11
10
9
11
I
1
0
I
,
8
1
0
1
6
0
I
5
I X
I
AJ:)DRESS
IA.15
Octal code:
006ZXd dddddd
I '~
,i
[~
"'~
I)
3
2
1
0
x:
X
A17
I
X
A16 I
[,"
AO
I
I
I
,{
Al
1$
controller stack pointe:r. The fiI."st word identifie:s the instruction. The seco·nd
word contains the memory address to be loaded into the digital graphic controller
stack pointer.
The LOSPE, Load Stack Pointer Extended instruction, utilizes bits 0 and 1 of
the first W'Ord a$ bits A16 and A17, respec.tively, of the 18 bit extended address to
be loaded into the stack. pointer (for EIM bit on). The graphic controller stack. is
acee.sled in the bank. defined by the bank. register. (See PG'R in Section 4.)
(l)SP)
:1
4
-I·
I
1-----------------------------------------------LDSP
a twO"'"word instruction used to 10a4 an address into the digital graphic
OJ!eration:
J
[J
[ i
LOAD STACK PO INTER
~]
;1
<- ADDRESS
NOTE
Thebaginning of stack may be defined in any bank..
The stack must not transcend bank boundaries.
.~
I
I
I
I
(
J,
f :;
LOAD DEVICE REGISTER lMMEDIATE
!LDRI!
14
15
!
l' 0
I
I
I X
I
''''f~ _
13
I
11
10
9
8
7
6
0 I 1
1
0
0
0
0
12
I
I
I
0
I
I
X
0
Octal code:
5
3
1
2
DEVlf
0
REG if
I
I
I
X
·X I
DATA
1
LDRI is ftmctionally equivalent to NOOP.
the GRAPH IC 7 sy s tern.
It is included for c.ompatibiE ty with
ADD TO DISPLAY REGISTER IMMEDIATE
15
4
0060dd XXdddd
14
13
12
11
10
9
8
7
6
Octal code: 0043dd dddddd
5
4
3
o
1
2
!
I
I
I
DRIP
I 0 I 0 0 0 I 1 0 0 I 0 1 1
I
!
I
I
II--~--------~------~--------~----------------DATA
1+ !
I
!--~--------------------------------------------
ADD! is a two-word instruction that enables a numerical value to be added to or
subtracted from the contents of a display register. The first word identifies the
display register that contains the data to be modified. The second word, in two's
complement form, contains the numerical value to be added (or subtracted from) the
designated register. Bits 0-5 of the first word identify, in binary form, the
number of the register containing the data to be modified. Genera.l purpose
registers DRO through DR3 are designated by 00, 01, 10, and 11, respectively. See
table A-6 for a complete list of display registers.
Operation:
(DRif)
<- (DRlf) +
DATA
LOAD CHARACTER GE NEUTOR
15
13
12
I
I
I
I 0 I 0 0 0 I
I
I
I
I
I BASE ADDRESS
I
,
.J
"
14
set.
1_1•
10
9
8
Octal code:
7
6
5
4
3
0047dd dddOOO
0
0
1
1
1
X
X
X
X
0
0
0
0
0
0
0
0
0
I
I
I A171A161
I I
I
I
0
0 I
I
1
1
0
1
2
LDCG is a two-word instruction that loads the base address of the RAM character
The c.haracter table must be based at 4K botmdaries in memory.
Change 1
3-23
r
ISAvpl~)J
SAVE DISPLAY REGISTER
15
I
I
!
14
13
0
!
I
0
0
11
12
I
0
I
I
10
9
8
7
I
1
0
0
0
_....6- .
0
Octal code:
5
4
.3
2
1
r
0041dd
I.
I'..
0
1
nai;
1
._\
I
}
"
The SAVD instruction causes the contents of the display register identified by
bits 0-5 to be pushed onto the top of the graphic controller stack. Before the push
operation, the graphic controller stack pointer is decremented by two. Bits 0-5
identify the number of the register in binary form. General purpose registers DRO
through DR3 are designated by 00, 01, 10, and 11, respectively_ If ElM: = 1, then an
18-bit stack address is used.
Operatil.:m:
(nSP)
<-
(nSP) - 2.
(Top stack location)
I
I
i
0
I
I
I
14
13
0
0
12
0
I
I
I
11
10
9
8
7
6
(
Octal code:
,5
4
3
2.
1
0042dd
0
(DRIi)
(nSF)
(
I'
1
0
0
0
1
0
DRii
The RESD instruction causes the contents of the top oithe graphic controller
stack to be popped and placed into the display register identified by bits 0-5.
Following the pop operation, the graphic controller stack pointer is incremented by
two. Bits 0-5 identify the number of the register in Mnary form. General purpose
registers ORO through OR3 are designated by 00, 01, 10, and 11, respectively. If
ElM = 1, then an l8-bit stack. address is used.
Operation:
r
<<-
(Top stack location)
(OSP) + 2
J
(I
I
<,
(
(
(
(
[
3-24
<.1
~~~~
(DR#)
RESTORE DISPLAY REGISTER
lRESD(E)/
15
<-
r
"]
r
fi
<;1'"
3.3.4 DISPLAY CONTROL INSTRUCTIONS. Display control instructions are used to
establish and/or change various display parameters as required. An initialized
instruction is also included to permit definite hardware conditions to be
established before a refresh file is processed.
ILDDPI
LOAD DISPLAY PARAMETER REGISTER
15
14
I
I
I
I
0
I
I
0
13
0
11
12
I
1
10
9
8'
7
6
014ddd
Octal code:
5
4
3
2
1
0
"I
I 1 !
I I
DISPLAY PARAMETERS
LDDP is used to modify the contents of the display parameter register.
action of individual bits is as follows:
The
Action
0,1
Character 9ize:*
1 0
0 0 ... size 0 (smallest)
0 1
= size
1 (same as size 0)
1 0 == size 2 (2.0 times size 0)
1 1 "" size 3 (3.0 times size 0)
2
"
Character orientation:
o
:=
normal
1 "" rotate 90° ccw
3
,.
Character parameter change enable:
o = no
change
1 = change character size and/or orientation status to that indicated by bits
0-2
4-10
,
Not used but are always zero
"
J
*See table A-12, page A-70 for character size descriptions.
~-i
\
3-25
,"','.
-
ii
!LDDzl
15
14
13
I I
I 0 I 0
I I
0
Octal code:
LOAD OISPLAY Z REGISTER
1:2
11
I
Jf:' I
'" I
I
10
9
7
4
5
6
I
!
I
0
8
1
2
3
' I
01dddd
0
t
"
DISPLAY Z PA.1W1En:RS
I
I
I
'
~
. ,j
,,'
(
....,;
-
LODZ is used to IlIOa1fy tb.econtents o:! the display Z register.
individual b:i,ts is as fo110WfH
The action of
r
':1,
,!
'"I,
Bit(s)
, .
action
0-2
., Gt'ay level selae t (mode 0 only; no1: mode 1)
,
210
000,..
intensity level 0 (off)
1 .. intensity level 1
thru
thru
, 1 1 1 .. intensity ,level 7 (brightest)
o0
The gray level is also written into the Pixel Data Registel:'
(:~DR)
f
(bits 1-7).
Une structure select:
-o
4 3
0 ,..
..
1 0 ..
1 1 ,.
o1
5
so 11d: vector
dotted vector
dashed vector
dot-dashed vee tor
(3 on, 5 off)
(5 on, 3 off)
(4 on, 4 off t 20 on t 4 off)
Blink. ,select:
o ,..
steady
1 '" blink.
The bUnk. bit is also writt~n into the MSB of the Pixel Data Register.
rate is 1.5 hertz.
The blink
O1sp1ay select:
_ -9 .........
8 1 6
1 X X X '" Display no. 1 enabled
X 1 X X .. Display no. 2 enabled
X X 1 X .. Display no. 3 enabled
X X Xl.. Dis play no. 4 enabled
10
Dis play select change enable:
o ..
no change
1 .. change select status to that indicated by bits 6-9
0pel:'a.tion:
(DZR.)
<-
I
I
I
(
I
I -'
(
I
DISPlAY Z PAR.AMltTERS
,,(
Change 1
(I"
, - - -
15
I
I
I
Octal code:
LOAD TEXT INCREMENT REGISTERS
ILDT!l
1
!
14
I
I
1
I
13
I
I
12
11
10
9
8
LINE INCREMeNT
7
6
o
1
5
4
3
2
1
1401dd
o
TEXT INCREMENT
LDTI is used in conjunction wi th the TXT (draw t"NO tabular characters) to
specify the amount by which each line and each character is incremented. For normal
characters, the contents of the X-position register is incremented. For rotated
characters, the contents of the '[-position register is incremented. The text
increment specified by bits 0 through 5 replaces the contents of the text increment
register. The line increment is specified in bits 8 through 13. See table A-12 for
the recommended line and text increments for character sizes 1 through 3.
Operation:
Normal characters:
J
<- TEXT INCREMENT
<- LINE INCREMENT
<- (OXR) + TEXT INCREMENT
(DTI)
(OLI)
(DXR)
I'
, ',-1'
(followng display of each character)
Rotated characters:
',J
,
,
-'
(DTI)
<- TEXT
(DLI)
(DY'R)
<-
I IZPRI
Octal code:
INITIALIZE
15
I
I
I
INCREMENT
INCREMENT
(DY'R) + TEXT INCREMENT
(following display or each character)
<- LINE
0
!
I
I
14
13
12
0
0
0
11
10
9
8
7
6
0
1
1
0
0
0
I
!
I
I
IZPR is functionally equivalent to a NOOP.
with the GRAPHIC 7.
I
I
0030XX
5
4
3
2
1
0
X
X
X
X
X
X
It is inc.luded for c.ompatibility
,
,
'
3-27
r
··l
f
LOAD PIXEL DATA REG ISTER
ILDFUI
15
I
I
I
0
I
I
I
14
13
12
0
1
1
11
10
9
8
I 1
I
it
X
X
'·1
7
6
(ED1) Octal code:
5
4
3
1
2
034Xddd
I
0
V4~UE
---
15
I
I
I
~10DE
LOAD INSTRUCTION
0
I
I
I
14
0
13
·0
12
0
I
I
I
11
10
9
7
8
Octal code:
6
5
4
:3
1
1
0
1
1
2
-
I
1
See
0072dd
0
I·
I
I
ED1
0
1
The MJDE is used to ll10dify the Extended Instruction Mode (ElM) bits 0-5. The
En! detetmines which set of instructions will be recognized by the digital graphic
controll~r with the. Same opcode. When mode'" 0, the standard instruction set is
used. When mode"" 1, the Extended Instruction Set is used. If bits 1-5 are set, no
mode change results. See table A-2 for a summary of these instruction sets.
INITIALIZE
IINI'!l
,
15
I
I
!
14
I
° II
0
13
0
(EIM)
11
10
9
8
7
6
5
4
I
0 I 1
I
1
1
0
0
1
X
X
12
Octal code:
3
2
X
X
.
I
0071x..'t
1
0
X
X
IN!Tis used to res tore the digi tal graphic controller to power up conditions.
I
!J.'HT resets the split screen function and crosshair cursor on the v'ideo
controller, loads the look ...up table to initial values (see page 7-21), and selects
the color White.
IctRMI
15
!
I
I
(EIM) Octal code:
CLEAR MAP FING MEMORY
0
14
I
I
I
0
,.13
12
11
10
9
8
7
6
0
0
I
I 1
I
1
0
1
1
1
CLRM clears the selected mapping memory.
5
4
X
X
3
2
X
X
.
067XX
1
0
X
X
I
1
.,
,.
f
I
:1
r
I
I
~'l
r
(
...
I
I
I
r
(
Change 1
·~:l
f ~~
I
3-28
1
r
'the L.DPD instruction is used to modify the Pixel Data Regi:ter (bits 0-7).
Section 4.3.2 for a description of the Pixel Data Register (PDR) •.
IMODE I
::-:1
I
."
(ELM) Octal code:
063dd
I I
I
I
I 0 I 0 0 0
1 I X X X X A17 Al61
I__~I______~______~____~l_'__~__~_____ I
I
I
IAIS •
GRAPHIC 8 MEMORY' ADDRESS
AO I
I
I
I
:,..'
I I In I I
lAM lRELllNCIDIR\
,0
..
J
.J
I
I
I I I I I
I
I
I
I
INITIAL X VALUE
I
I
I
I
I
I
INITIAL Y VALUE
I
I
I
I
I
I
~X~
I
I
I
I
I
I
~y~
I
I
I
MVPD controls the transfer of data between the' selected mapping (Pixel) memory
and the display processor memory. The data is defined ~y the GRAPHIC 8 memory
address (bits AO to AI7). The Initial X and Y values and the Final X and Y values
represent the rectangular array of pixels involved in the transfer.
Word I
Word 3
-
Bits
12
Description
GRAPHIC 8 memory address bits A16, Al7
.. 0 Data transfer occurs from mapping memory to GRAPHIC 8
memory
.. 1 Data transfe·r occurs from Graphic 8 memory to mapping
memory
3-29
r
13
'" 0 The XY pixel scan is left to right mO'ling from 'bottom
to top.
'" 1 The XY pixel scan is bottom eo top moving across from
left to right.
14
J
Description
Bits
'" 0 Initial X and Y values are abs"olutepixel addresses of
the lower left corner of the rectangular pixel array.
The final X and Yvalues are absolute pixel addresses
of the upper right corner of the rectangular pixel
array.
'" 1 Initial X and Y values represent pi~cel increments from
the c.urrent X, Y pixel address to the lower left corner"
of the pixel array.
r
l
•
f
I '"
r
The final X and Y values are the pixel increments from
the current X,Y pixel address to the upper right corner
of the rectangular pixel array.
15
Addressing mode
"" 0 GRAPHIC 8 absolute address
:III
1 GRAPHIC 8 memory displacement from the display program
counter (lst word after word 7)
Each pixel array corresponds to an array of co"nsec:utive 1'1. hi t hyt~s in the
GRAPHIC 8 memory. n (= 4,8) is the number of bits per pixel including the MSB or
blink bi t. The va.lue in the n bi t byte represents the gray level of the corresponding pixel.
f
(
I
J
I
I
[
i·
..--1
~,
, ..
-
IMDLiiI
15
I
I
~,
MOD!FY LOOK-UP TABLE
14
13
0
I
oI
11
10
0
0 I 1
1
0
0
0
0
12
I
I I
I
IAl'
I
I I
lAM I
I
I
I I
I 0 I 0
I I
I I
I 0 I 0
I
I
I,
(ElM) Octal code:
066Xd
8
7
6
5
4
3
2
0 I 1
1
0
X
X
X
X A17 A161
9
I
1
-
0
I
I
I
I
GRAPHIC 8 MEMORY'ADDRESS
AO I
I
I
NUMBER OF GRAPHIC a a-BIT BYTES
I
I
VIDEO
I
I
0
0
0 0
0 I 0 0
0
CONTROLLERS I
I
I
I I
I
0
0
0 I 1 I
LOOKUP TABLE ADDRESS
I
I
I
,
MDLU is ,used to modify the 1fideo controller look""Up table. The look-up table
defines the manner in which the data in mapping memory is presented to the display
without modifying the refresh data itself.
Each video controller contains a 256 x a-bit word RAM look-up table (LOT)
(starting at video controller memory 400 (octal») which permits pseudo-color or gray
level transformations.
, .J
The GRAPHIC 8 memory address specifies the beginning of n consecutive 8-bit
bytes (where n is the number of GRAPHIC 8 bytes, word 3). If the addressing mode
(AM) bit is 0, then this address is absolute. If the (AM) bit is 1, then the value
represents a displacement from the program counter (1st word after word 5). The
contents of each byte is the desired new gray level (or color) for each
corresponding gray level (or color) in mapping memory.
The Video Controller number is assigned as follows:
..
I
Controller
Number
Word 4, value for bit:
3
2
1
0
1
2
3
0
0
0
0
0
1
1
0
0
4
1
0
0
1
0
0
0
Any combination of controllers can be assigned with the same MOLU instruction
by setting any combination of these bits.
; ..
The LUT beginning video controller address is 4008. Addresses greater than
4008 but less than or equal to 7778 may be specified to modify a portion of the
LUT.
j
3-31
I
The useable portion of the LUI is Ii- function of the number of bits per pixel
and the blink capabill ty of the configuration. If bUnk. is not enabled t then all
bits per pixel (number P) are used for pseudo gray level (or color). Therefore,
with no blink, the useable po rtioi'l., of the LUT is fro~4008 to 4008 + Zp - l .
If the conf:tgura,tion has blink, then the MSJ3 is used so only P... l bits are used
for the pseudo gray level (or color). Therefore, with bllnk.,·the useable po rt i.on of
the LOT is . rtOUl 4008 to 4008 + 2P"' 1 .. 1.
For e:ua;ple, suppose the com igurationhas 4 bits per puel w:t,th blink for
video controller number 1. InitiallY, the ;r..U'I' loot<.s like:
VideQ Controller Address (octal)
Contents,
..
,
o
400
401
402
1
2.
--
406
407
6
7
We wish to modify the LUT to reverse the roles of gray. levels 0 and 7 (reverse
video). The MIlL!] inst'l'U(!tion is:
I
• WORD
6600
the MDLU opcode
• WOE {;ADR
G8 metl101:'1 address or d,isplacement (1£ AM • 1)
LO
f;of 13-'01 t bytes
controller 11
1
400
j,
Ltl'!' address, in video controller RAM
where
ADR:
Location 0 of the LUI defines the background
color. Blinking is be tween the defined
color and black, regardless of the back....
ground eolor.
Change 1
I '. :.
'
,
'
:~
'.;:,.8
f'
f:
f
,,_ ..
I
".
,;1
f
I
/>
I
,
..
• BnE 7, 1, 2,3, 4, 5, 6, 0
NOTE
3-32
r
I ,~
(EIM) Octal code:
FILL A CONVEX POLYGON
15:
I . I
101
I ~. I
I . I
14
0
13
0
12
11
I
0 I 1
I
I
lAM
I
10
9
8
7
6
5
4
3
1
1
1
0
1
X
X
X I X Al7 Al61
I
IA151 •
I
I I
lULl
I I
0075XX
I
.1
ADDRESS FOR LIST OF. VERTICES
NUMBER OF VERTICES
2
1
0
I
I
I
AO I
I
I
I
I
where the address contains:
Xl
11 Xl
Yl
AYI
•
"
I
OR
i
I
..
~
"Yn
Yn
Third word bit 15 • 0 for absolute address of list
- 1 for displacement from the program counter (first
word after word 3)
and
bit 14 • 0 for absolute
~ertices
I
bit 14 • 1 for relative ~ertices. Each vertex is relative to
the current X and Y pOSition, not to other vertices.
The adjacent vertices are Usted in either the clockwise or counterclockwise
direction. The last vertex is adjacent to the first in the list. A previous LDDZ
or LDPD instruction is used to specify the gray or color level for the filling
algorithm.
The fill algorithm is based on the geometric shape of the convex polygon.
convex polygon has all its interior angles less than 180°.
Change 1
A
3-33
f;
.{ '. !i
There is no limit to the number of vertices that can be specified except the
size of read/write memory. If a non-convex polygon is specified unpredictable
results will occur. Maximum execution speed is obtain·ed· if the vertices are
specified in the clockwise direction starting with Y maximum.
NOTE'
The on and un relllain \1nchanged. The beginning'
ofth:e vertex list can be in any bank. Ro'Wever,
the vertex Ust must not transcend bank
bounda.ries ..
. (., "1
,
I."j.
I
f;
f ,"
\{
( I:,.::
'
{
,,~;"
t";
·f;
'I:
{.
I,
,.
[.'
3--34
(:
,
..
SECTION 4
GRAPHIC 8 REGISTERS
4.1
GENERAL
GRAPHIC 8 registers fall into three major categories! display processor
registers, digital graphic cant roller registers, and interface registers. This
section describes the application and format of each register in each category and
identifies the address assigned to each. A summary of the data contained in this
section is provided in Appendix A.
4.2
, ,
DISPLAY PROCESSOR REGISTERS
The display processor contains eight general registers designated RO through
R7. These registers function in a manner similar to the corresponding registers in
a minicomputer of the PDP-ll type manufactured by Digital Equipment Corporation
(DEC). Details concerning the applications and formats of these registers are contained in the DEC PDP-ll/04/34/45/55/60 Processor Handbook which should be used as a
supplement to this manual. Note, however, that addresses are not assigned to the
display processor registers.
An 8-bit switch register is program readable (used by GCP) from octal location
177774.
4.3
DlaITAL GRAPHIC CONTROLLER REGISTERS
Digital graphic controller registers can be divided into six groups: processor
registers, function registers, sense and mask registers, function control registers,
display control registers, and configuration register. The following paragraphs
provide details concerning the application, format, and address of each register of
each group. The RAM register address, RRn, refers to a Rk~ address in the digital
graphic controller. The register is accessible by program control only if it is
also assigned an octal memory address: nnnnnn. Refer to Appendix A for a summary
of the data applicable to digital graphic controller registers and their display
register numbers (DRn).
NOTE
Except for the sense. and mask, and the function
control registers, all graphic controller
registers a~e 16-bit registers. In several cases,
however, fewer than 16 bits are used. The
descriptions in the following paragraphs consider
the size of each register to be equal to the
number of bits used •
.".)
4-1
1
4.3.1 PROCESSOR REGISTERS. Processor register's of the digital graphic controller
comprise four general purpose registers, a st,ack pointer t a program counter, and an
instruction register. These registers are the general working registers of the
graphic controller. Each has an octal adciress and, when the graphic controller is
halted, the contents of each can be read by the display processor using programmed
data transfers.
Oc tal address:
GENER.ALPURPOSE REG!STE:Rn
thru
165002 (nRO)
165004 (DRl)
I
-
If .,
I
165032 (DR2)
165034 (DR3)
IDR31
14
15
l3
l2
11
lO
7
8
9
5
6
43
2
1
o
Ea'ch of the fo·ur general purpose registers (display registers) in the digital
graphic controller is a l6-bit register that can be used as required for general'
operaUons or for te.llporary storage of data. Additionally, the contents of DRO can
be tested and a jump executed if the value is not equal to zero. Pata is' written
into the general purpose registers using graphic controller instructions.
PRO thru DR3:
Associated. instructions:
LDDI
ADD I
DROonly:
-17
IDS]? I
,"'
I
I
JPRZ
Octal addtess: 165000
STACK POINTER
15
16
I
I
I
14
13
l2
11
10
9
I
I
I
7
8
I
6
.5
4
3
2
1
. I
a
The stack pointer is a 16-bit register that contains the address of the top
loca tion in the memory s tack. It is loaded by the graphic con troller LPSP (E)
instrtlc tion. ~.then ill SAVD(E) instruc tlon is used to push data onto the stack, the
contents of the stack pointer is autdlllatically decremented by two before the push
opera.t:f.on Occurs. When a RESD(E) instruction is used to POP data from the stack,
the contents of the stack point;e.r if a'utOO1atically incremented by two following the
pop operation. Call and return inst'ructions make similar use of the stack pointer
to save and restore the contents of the program counter when a subroutine is
performed.
Associated instructions:
4-2
tDSP
SAVD
CALL
CALR
RESD
RTRN
,
,';
SAVD
RESD
JMPZ
'),
II
f
I\
f
I
I:
I'
f
f-
PROGR&'1
COUNTER
."
15
14
13
12
11_ 10
9
8
Octal address: 165006
7
6
5
• I
4
3
2
1
o
.1
The program counter is a 16-bi t register that contains the address .of the next
instruction to be ~~ecuted by the graphic controller. The program counter is
initially loaded by the display processor with the starting address of a refresh
file. This automatically starts the digital graphic controller. As instructions
are executed by the graphic controller, the contents of the program comter is
incremented automatically. A. one-word instruction causes the contents to be incremented by two while a two-word instruction causes the contents to be incremented by
four (bit 0 is always zero). For this reason, increments used for relative jumps or
calls must be calculated from the address immediately following the location of the
jump or call instruction.
A$sociated instructions:
All
DISPLAY INSTRUCTION REGISTER
IDIRI
15
14
13
12
11
10
9
8
7
6
Octal code: 165010
5
4
3
2
1
o
The display instruction register is a 16-bit register into which each
instruction or data word fetched by the graphic controller is placed.
Associated instruct;:ions:
All
, .._....
4-3
4.3.2 FUNCTION REGlSTERS. These function registers are loaded by the digital
graphic controller instructions as required to control the functions performed by
the m.icrocode. Each function register has an octal address so that, ","hen the
digital graphic. controller is halted, the contents of the registers can be read by
the display processor using programmed data transfers,.
IDnl
X POSITrON REGISTER
15
1L.
13 '12
I
I
I
11
I
I
I
10
I
I
I
I
9
7
8
x:
I
I
[
'~.
I
~~
Octal address: 165020
6
5
4
3
,
2
1
0
COORDINATE VALUE
(
I
l__SIGN/OVERFLOW
BIT
1
_ _--:SIGN BIT
The position register is a 12-bit register that contains the value of the X
coordinate of the screen position~ When a digital graphic controller loads absolute
data into the X position register, the 11 bits that specify the value of the X
coordinate are sign, extended to fUl the 12 bi t8 of the register. When an
instruction specifying relati,re X position data is executed, the speCified data is
added to the con-tents of the X position register. Bit 10 serves as an indicatol;' of
overflow conditi¢n. Whenever the addition of relative data causes the value in the
X position register to exceed programmable limits, bit 10 will differ from bit 1l.
Under thesec.ondit1ons, if the X/Y overflow bit in the mask. register (MKlt) is set
and the interrupt is enabled, the graphic cont:roller will halt and interrupt the
display proceSsor. If the X/Y overflow bit is not: set, relative data wUl still
modify the register contents but the screen will be blanked ut'ltil bits 10 and 11 are
no longer different. Coordinate values are expressed to two's complement form and
may range from 17778 (+1023) to 20008 (-1024). The zero X coordinate defines
the vertical center line of the CRT screen. Positive coordinates are to the right
of center; negative coordinates are to the left of center. Note that only the
ITalues from 07778 (+511) to 30008 (-.512) fall into the displayable area of the
CRT. Values outside these limits cause the display to be blanked (see figure 4-1).
Associated
instructio~q:
LDXA
LDXR
DR.."{A
DRXR
PPTA
PPYA
MVXA
PPLR
MVXR
TXT (for normally oriented
DRSR
MVSR
I
(
1:
,I
I:
t,
characters)
PPTR
PPYR
I:
4-4
-1
r'
.-'~
~
-
. _- +
............
-
v
..... _--IlOOO
Y - 3717
I
I
I
I
I
NOTE
Coordinate designations are in octal format
0
.
Figure 4-1.
Addressable vs. Displayable Mapping Memory Areas
for 1024 x 1024 Screen
4-5
.--~
~.
I
..
!f,.1.
-.
loyal
..
Octal address: 165022
Y POSITION REGISTER
f~'
:~~
'W'.
10 . 9
8
I fl
I
~I
7
5
6
4
3.
I
1
o
y COORDINATE VALtrE
IH.,
}
$:-
--.i-.i, . . stcm
..
:SIT
" .... bit register that contains the value of the Y
'The Yposition register is 11::t2
coordinate of the screen polition~ This register is identic.al to the X position
register and perfo~s the $ame functions .for Y coordinate data that the X position
register performs f,or X coordinate data. The XlY overflow bit in the lllask register
(MKR).is applicable to the Y as well as the X position register. '!hezaro Y coordinate defines the hodzontal center line of the CRT screen. Positive coordinates are
above the center; negative coordinates are below the center.
A$sociated 1%).struetions:DRYA
011YR
-
MVYA
DRSR
MVSR
PPUt
MVYl
'tXT (for rotated charac.ters)
DISPLAY CHARACTER REGISTER
IOCRI
15
14
q
13
f
11
PPTA
PPT~
PPYA
PPYR
Octal addre$S; 165024
10
9 8 1.' 6 5 4 3 2. 1 0
"'_I',
ASCII CHARACTER CODE
The displaY character register is a se'V'en-bit register that contains the c04e
of the c'haraetet or symbol to be displayed.. A.SCI! codes are used for standard and
optional cha,rac:.teu:s and symbols as shown in AppendiX A.
Assoeiated instructions:
'.
I
f ::1
.....,
,-'I
'_~
I ;.
I...,....
,~ SIGN/OVERFLOW BIT
:_.-;
,-~,
:',,'
1. ,
I,
,(
I
,,f, .
I ','
t"4
f
l~
(:
',1,
4-6
"I
I
f ,. ".. ,
I
f
..
~
TEXT INCREMENT REGISTER
IDTII
..
14
15
13
12
I
I
I
11
0
I
I
I
10
0
9
8
7
6
0
0
0
0
I
I
I
Octal address: 165012
5
4
3
2
1
0
TEXT INCREMENT'
The text increment register is a 12-bit register that contains the value by
which the screen position is to be incremented after each tabular character is displayed. Bits 0-5 may be programmed as required; bits 6-11 are always zero. After a
normally oriented character is drawn, the value in the text increment register is
added to the value in the X position register. After a rotated character is drawn,
the text increment value is added to the value in the Y position register. Note
that this register is associated only with the TXT (draw two tabular characters)
instruction. No automatic incrementing of the screen position occurs when the CF~
(draw single character) is used.
Associated,instructions:
TXT
LotI
-I
i
-
101.11
LINE INCREMENT REGISTER
I
I
L
15
i
14
13
12
I
I
I
11
0
I
10
I a
I
8
7
6
I
a I a
0
0
.9.
Ram address: RR126
5
4
3
2
1
0
LINE INCREMENT
I
The line increment register is a 12-bit Ram Register that contains the number
screen coordinate units that are advanced after the control character, Line Feed, is
encountered in the TXT or CHAR instruction. For horizontally oriented characters,
the line increment value is decremented from the Y position register. For
vertically oriented characters, the line increment value is incremented to the X
pOSition register.
Associ.;ttedinstructions:
TX'!' CHAR LDTI
...,.;.
,
••.Jl
iJ
4-7
r
CONIC X DATA REGISTER (OPTIONAL)
IK:{!I
Octal code: 165026
" I
II
I
"1
11..
15
I ....I
I
12
13
""
10
11
,- j
8
9
I
I
I
I
I
6
5
4
3
2
1
0
"j
I
IQIIII QI
7
J
X SEMI-AXIS LENGTH
The conic X data register is an II-bit register that contains the value of the
length of the X semi-axis (distance from the ellipse center to its perimeter on the
X axis) for an ellipse to be displayed. The X semi-axis length is contained in bits
0-8. Bits 9 and 10, respectively, designate unblanking for quadrants I (upper
right) and III (lower left). A zero indicates the image in the quadrant: is to be
blanked while a one indicates the image is to be unblanked. Loading this register
dloes not change the current screen position. Not"lllally, this register is loaded by a
(load conic X register) instruction. If a DRKY (draw conic Y register)
instruction is not preceded by a LDKX instruction, the data spedfted by the LDKY
instruction will be loaded into both the conic X and the conic Y data registers.
I
I
':".~,
:
f-.'
LD~X
Associated instructions:
IKYRI
LDKX
DRK"! (when not preceded by LDKX)
CONIC Y DATA REGISTER (OPTIONAL)
15
14
, I
13
, I
12
11
I
10
9
8
I
I
!
I
!QlvIQII!
I,
7
6
4
3
2
1
o
YSEMI -AXIS LENGTH
The conic Y register is associated rNith the optional conic generator card. 1t
is an 11-b.i t register that contains the value of the length of the Y semi-axis
(distance from the ellipse center to its perimeter on the Y axis) for an ellipse to
be displayed. The Y semi-axis length is contained in bits 0-8. Bits 9 and 10,
respectively, designate unblanking for quadrants II (upper left) and IV (lower
right). A zero indicates blanking while a one indicates unblanking. Loading this
register changes the current: screen position in accordance with the data in the
conic X and the conic Y data registers (the ellipse center is defined by data in the
X and Y position registers). Data is loaded into the conic Y data register using a
DRKY instruction.
Associated instructions:
DRKY
{
,(
l'
f
I
(
I
I:
4-8
\
'I
Octal address: 165030
5
f
"'I
..
,
;..,.,;
DISPLAY Z REGISTER
IDZRI
-I
I
I
15
14
13
12
11
I
10
9
8
Octal address: 165016
t,
7
6
5
{4
I····
2
3
0
I'
I
I
I
-,
I
I
DISPLAY SELECT CHANGE ENABLE ___ I
l __
1
DISPLAY SELECT _ _ _ _ _ _ _ _ _ _ _
1
BLINK SELECT
I
LINE STRUCTURE-=-S==E=L-=E-=:CT=-------------1
GRAY LEVEL SELECT ________________________ 1
The display Z register is an II-bit register containing data that controls the
Z-axis parameters of the associated display indicators. The action of the
individual bits is as follows:
L: .
Bit(s)
0-2
Action .
Gray level select:
..
210
--000 ... intensity level 0 (off)
001 = intensity level 1
thru
1 1 1
= intensity
level 7 (brightest)
This gray level is also wri~ten into bits 1 to 7 in
the Pixel Data Register (PDR). See the Note.
3,4
Line structure select:
! .
4 3
o 0 = solid vector
o 1 - dotted vector
1 0 = dashed vector
1 1 = dot-dashed vector
5
Screen Coordinates On/OH*
3 ON, 5 OFF
5 ON, 3 OFF
4 ON, 4 OFF, 20 ON, 4 OFF
Blink. select!
o ""
1
::0
steady
blink.
This blink. bit is also written into the Pixel Data
Register as the MSB. The blink rate is 1.5 hertz •
..J
*For a 512 x 512 screen, one pixel represents
t~o
screen coordinate units.
4-9
1
I
If
Action
Display select:
987 6
~
1 X X X ,.. Display No.1
X 1 X X .. Display No. 2
X X 1 X .. Display No.. 3
X X Xl'" Display No. 4
enabled
enabled
enabled
enabled
The Display S.elect bits 9-6 are ma.pped to bits 0-3 of
the Display Select Register (DSR).
Display select change enable:
10
o ...
no change
1 ,.. change display select status to that indicated by
bits 6.,.9
~~sociated
instructions:
tDDZ
NOTE
The DZR bit 5 (blink) and bits 0-2 at'e mapped to
the PDR register as follows:
Bits per
Pixel
4
8
76543
2
f -,
_'.1
l
f
,
t
(
1 0
521 0
210
5
1
In llide 0 the intend ty bits are witten through
the DZR for compatibility with the GRAPHIC 7
systems.
In Mode 1 the LDPD instruction is used to specify
intensities.
I"
I
t
...
-1
f
I,
I,
I:
It
-,-,
Octal code: 165014
DISPLAY PARAMETER REGISTER
iDPRI
15
14
13
12
11
I
I
I
10
9
8
7
6
5
4
0
0
0
0
0
0
0
3
2
1
0
CHA.R.ACTER PARAMETER CHANGE ENABLE
CHARACTER ORIENTATION
--------CHARACTER SIZE
----------------------------------------------
The display parameter register is an ll-bit register containing data that
controls various parameters of the associated display indicators. The action of the
individual hi ts is as follows:
Bit(s)
0,1
Ac1;ion
Character size:
(Also see table A-12)
1 0
a0
= size
0 (smallest)
- size 1 (same as size 0)
1 0 = size 2 (2.0 times size 0)
1 1 = size 3 (3.0 times size 0)
o1
,
.'
2
Character orientation:
o = normal
1 - rotate 90° ccw
3
Character parameter change enable:
o = no
1
4-10
change
= change
character size and/or orientation status to
that indicated by bits 0-2
Not used, but are always zero
.,J
4-11
1I,
LEFT MARGIN REGISTER
15
14
13
12
I
9
8
6-
7
5
2
3
4
1
I
I
I
I
-I
10
11
Ram address: RR108
I
X (or Y)
1'.
f
0
COORDINATE VALUE
I,.
I
I______--____~~--~~-----------------------------
I
SIGN
SIGN ~O~VF~1.~
.. - - - -
The left marg:in register contains the X position value (or Y position value if
rotated te.."tt) that defines the position at which the next character will be
presented whenever a CRcontrol character is encountered. The margin value is
stored when an STX: cha:!;"acter is specified in a CHAR or TXl' instruction as the
current DXll (or DYR.).
.
Associated instructitrns!
PIXEL" DATA REGISTER
IPDil
•
CH.AR TXT
15
14
13
12
11
10
9
8
Octal addre$s: 165044
6
7
4
5
2
o
1
The Pixel data register is an eight-bit register that contains a value
specifies an index into the lookup table and the blink status. If blink is
the MSB of this value represents the blink bit:. '!'he remaining bits are the
into the lookup table. Bits 8 to IS are not used. The blink bit is set by
instruction only.
A$sociated instructions:
-.,.....p+
LDPR
The following summarizes the use of the FDR for
various bits per pi.:te1 and blink (*).
-
Blink
Bits per Pixel
Yes
3
No
4
7
8
Yes
No
7
6
1
0
2
2
2
2
1
1
1
1
0
0
0
0
'*
'*
7
6
6
5
5
4
4
3
3
3
J
l
f
I
II
I
l:
NOTE
PDR Bits
5 4 3 2
that
enabled,
index
the t.DDZ
I
I
..
f:
,.
II
I:,
1.
-1
!
Octal address:
GRAPHIC CONTiOLLE..tt BAl.'iK. REGISTER
15
14
I
13
12
11
10
9
7
8
5
6
3
4
2
1
~<65014
o
MEMORY I
I
BANK
1,-.,
The graphic controller bank register is a two-bit register used to extend the
memory addressing capability of the graphic controller up to a total of 131,072
(l28K) words.
Ipazl
DISPLAY PROCESSOR PAGE REGISTERS
Iml
I
I
IpRJI I
Octal address: 172342
15
14
13
12
11
10
9
7
B
I
6
I
4
I
I
I
-
3
2
1
I
MAPPED
PAGE:
°II Octal address:
172344
I Octal address: 172346
The display processor page registers are 5-bit registers that are used to
extend the memory addressing capability of the display processor up to a total of
131,072 (IZeK) words •
11
.
5
'~.
NOTE
,j -
t~
Refer to Sanders publication H-78-o40B for
detailed information on programming the page
registers of the GRAPHIC B.
. ;
;.
,to
..
~
..... j
,
4.3.3 SENSEAND.M4\.SKREGISTERS.
One sense and one mask register are a sso,cj, a ted
with the digital graphic cout'roller. Both registers are as.signed octal addresses
and may be read at any t:1me by the display processor using programmed data
t'ransfers. Programmed data transfers may also be used by the display processor at
any time to write data into the mask register.
SENSE REGISTEl
15
14
13
12
11
10
.~
8
I
I
I
PP2 SYIIen ACTIVE
Octal address: Ih660
7
6·
"
I
I
I
I
I,
PPI SWI'tC11 ActIVE _ __
1W..TEP
5
4
I
I
I
.I
I
I
3
I
I
I
2
1
I
0
I
I
I
---
The seMe recister isa one-bit register that ind.icates t1;1e halt status of the
digital graphic controller. the remaining bit.$ are not used. !he condition
indicated by bit 4 when·it is set tol is as follows:
--
•
Bit
4
Condition. In4icated. When Se'1:; to ~
Digital graphic controller is halted for one of t,he
folloWi ng rea sons:
1)
O:l.splay processor sends stop function code (165040) to
graphic controller
2)
Display processor executes RESE'tinsttuction to
initialize devices on controller bus
3)
BREi' instruction executed by graphic controller
4)
LINK instruction executed by graphic controller
5)
Bus timeout (mea;rry fails to respond to a fetch
ccmmand)
6)
X or Y position overflow (bits 10 and 11 in the X
poSition or the Y poSitiotlregister are different and
the X/Y overflow bit in the mask register is set to 1)
I
4-14
6
P110TOPEN swi tah 1 :£. s act ive
1
PRO'I'OP!N swi teh 2 is active
Change 1
I
I,
f
I ,~'J:
f ':]:
J'~
,I
_:-:1
f
:~I
{--'
{
{'
I
I:
I
I
IMKRI
MASK REGISTER
15
14
13
12
11
10
9
8
7
Octal address: 177662
6
5
4
3
2
1
o
PP2 SWITCR:...-_ _ _ _ _ _ _ __
PP2 STRIKE
PPI SWITCH·------........- - - - PPI STRIKE
REAL TIME ~CL~O~C=K~-------------------------
X/Y Ov"ERFLOW
HALT
--------------------------------------
The mask register is a seven-bit regist~r on the ROM and Status card that
enables the digital graphic controller to report condi tions to the display processor
on an interrupt basis. An interrupt occurs when the condition is met and the corresponding bit in the mask register is set to 1. Bits in the mask register can be
set or cleared as required by the display processor using programmed data transfers.
Addi tionally t programmed data transfers may be used at any time by the display
processor to read the contents of the mask register. Seven different interrqpts are
enabled or inhibited by bits 1 through 7 (bits 0 and 8-15 are not used). The
interrupt and the interrupt vector address associated with each bit are as follows:
Bit
t'._
Interrupt
Vector
Address
(octal)
Associated Interrupt
1
Graphic controller halted by HREF instruction
000140
2
X or Y position overflow (bits 10 and 11 in X position
or Y position register are dif ferent)
000144
3
Real time clock (interrupts at rate of 60 Hz)
000100
4
PHOTOPEN 1 strike
000150
5
PHOTOPEN 1 switch activated
000160
6.
PHOTOPEN 2 strike
000154
7
PHOTOPEN 2 swi tch activated
I
NOTE
Refer to H-82-1319 (Vistagraphic Series PICK
Routine User's Manual) for PHOTOPEN usage.
Associated instructions:
Display processor programmed data transfers
(read or write)
Change 1
4-15
4. 3. L~ FUNCTION CONTROL REGISTERS. Two function control registers are associated
with the digital graphic controller. These registers are actually only addresses
that may be accessed by the display processor. Simply by ace,essing function control
register addresses, the d:i.spl.ay processor can halt or restart the graphic controller
as required.
-
I FUNS I
, FUNCTION CONTROL STOP REGIS'l'ER
15
14
13
12
11
10
9
8
7
6
Octal address: 165040
5
4
3
2
1
o
The function control stop register is a function control register used to halt
the digital graphic controller. The HALT bit 4 in the sense regist~.r SENS must be
checked for the digital graphic controller being halted before pro~,eeding with code
that assumes the c.ontroller is halted. Whenever the display processor accesses the
address assigned to this register, the gra.phic controller halts.
A.ssQciated instructions:
,
-
IFuNcI
Io::pcca
AcceSsing address 165040 by display processor
FUNCTION CONTROL CONTINUE REGISTER-
15
14
13
12
11
10
9
8
7
6
5
Octal address: 165036
4
3
2
1
.0
The function control continue register is a function control register used to
restart the graphic controller after it has been halted. The HALT bit 4 in the
sense register SENS must be checked whether the digital graphic controller has
started before proceeding With code that assumes the graphic controller is running.
When~~er the display processor accesses the address aSSigned to this register, the
graphic controller resumes processing from the point at which it last halted. ~ote
that this register should not be accessed unless the graphic controller is halted.
Associated il'l.st1:Uctio!!,s.=
4-16
Accessing address 165036 by display processor
4.3.5 DISPLAY CONTROL REGISTERS. Any ccmbination of four video controllers'tnay be
selected by the LDDZ instruction. Twelve display control registers are asso-'---·--~-·1·
I(SX1,SYl)..;.//
I
: :+
i
I
I
.
I (5)(2, SY2~ -'
II
-,"/
I.
~I.~aI
I
t
--
-
-
-
-
,.}- - - - - ... - - ... - -.-
I
+
I
I.
..
I
f
l.N2
I
+
---------+f----,
1"""'1
I
I
lN3
,
I_-.....______-'*!o.....---.1
I
I
NOTE
The system sets up SX1, SY.l, LNl to display
the complete screen ,..men sp11 t screen is not
being used.
Change 1
1
I
--I
I
4-20
I
:1-----------1:1-.
!
I
tI":1.N3- II
I.
00
I
I
1
/
'""
- _ .... r l
I
If'-- , - - - I
~3,m) .....
2048
PIXELS
-
,,"7r -:- - - - - -- - - - - .J -'
-------i"'l!.;---,
SCREEN
-
I
I
I
I.
I
t
I
f
I
I
I
I,
4.3.6 CONFIG1.J'RATION REGISTERS. Three types of regi stersareavallable to determine
the configuration of the present GRAPHIC 8 installation.
locrl
DISPLAY CONFIGURATION REGISTER
15
14
13
12
11
10
9
8
7
Octal address: 165052
6
5
4
3
2
1
0
Display meni tor number n (1-4) is configured into the system wthen bit n-l of
the Display Configuration register is set.
Octal address: 165046
VI DEO CONTROLLER DmECTORY REG ISTER
15 _ 14
13
12
11
6 _ 5
10
4
3
Video controller number n (1-4) is configured into the
set in the Video Controller Directory register.
14
13
i
12
11
'10
9
8
syst~
1
o
when bit n-l is
Octal address: 165070
CHARActER FONT REGISTER
15
2
.7
6
5
4
3 .. 2
1
0
VALUE
This register contains a value indicating the character font present in the
current coI1figuration.
I
Value .. 377 for 7 x 9 font
.. 371 fo r 5 x 7 fon t
.
.,
-.1
Change 1
4-21
-
Isal
System Configuration Register
15
I
I
I,
I
I
14
I
I
13
.11
NOT USEl)
BLINK STATUS
RESERVED Foa
aumwAD
SCmN lUSOLoTION
12
11
I II
I' I I
I
L
10
8
1
7
6
I' I
5
4
I I
II
I
I
I
OCtal address:
.3
I
I
I
2
1
I
I
J
o
,
f"'~
I
NUMBER OF VIDEO CO~NTR:::e:.~O~LU~·:'!:'R"!:"'S"""--MEMORY FUtD SIZE _ _ _ _ _- _ _ _ _ _ _ _ __
BITS PER PIXEL
USE'RVED FOR BAlU)~":=:w.'.;':'ffi~::r.'_.- - - - - - - - - - - - - - - -
,,',
(
B:t't(S2
VALUE
1...2
Bits per pixel:
2
I
I
165050
l
I
I -,
1"::
f ,-"
1
0'
T
1
1
0"
1..
- 2 bits per pixel,
4 bits per pixel
8 bits per pixel
:(
"
Memory field size:
5
0'
I
0
0
1
1
1
1
4
.3
a
T
1
1
0
1
0
1
1
1
0
0
0
1
....
..
.
III
'III
X
2048
Y
'It
lola
1024 'It 2048
2048 :It 1024
1024 11: 1024
512 x .1024
1024 11: 512
512 x 512
I
I ...
Nu'!l1.ber of Video Con troller
7
6
0"
'0 ..
1
1 .. 2
0.. .3
1
1"
o
1
4
Screen RIa so lution:
9
8.
'0 0'
0 1
1 0
1 1
.
...
'III
512 x 512
640 x 480
1024 'It 768
1024 'It 1024
.
I: , -
Blink/No BUnk:
12
0- ..
1
..
MSB or PDa is blink bit
MSD or PDR is part of pixel data.
f,
r
Change 1
I"
4.-4
INTERFACE REGISTERS
Interface registers are associated with the various serial aud parallel interface ports of the GRAPHIC 8. The following paragraphs provide details concerning
the format and the address assigned to each interface register. Refer to Appendix A
for a summary of the data applicable to the interface registers.
4.4.1 SERIAL INTERFACE REGISTERS. Up to thirteen serial interface ports are available for external devices to communicate with the GRAPHIC 8. One is located on the
ROM and status logic card and four are located on each multipart serial interface
card (three multiport serial interface cards may be installed in the terminal
controller). The designations of these ports and the associated devices for 4
keyboards and 4 PEDs are as follows (note that ports 1, 5 and 9 can be used either
as basic serial interface ports or as full RS-232C interface ports):
Port
Desianat!on
..
.'.:
-
1 (RS-232C)
2
,.;"
3
.
~.,
Associated
Device
-,
Location
Has t computer
Alphanumeric/Function Keyboard no. 3 I Multipart serial
Alphanumeric/Function Keyboard no. 1 , - interface card no. 1
PED no • 1
I
-
4
5 (RS-232C)
6
7
8
-I
Unused
,
Multipart serial
PED no. 3
Alphanumeric/Function Keyboard no. 2 , - interface card no. 2
PED no. 2
_I.
12
Alphanumeric/Function Keyboard no. 4-'
PED no. 4
I Multipart serial
, - interface carcino. 3
Unused
Unused
I
TTY
Teletypewriter
9
(RS...232C)
10
11
-
ROM and status logic
card
Bits 0-3 of the Display P~ocessorrs 8-bit switch register (octal location
177774) represent the port assignments for keyboards and PEDS. When LOCAL or system
mode is entered, GCP connects the corresponding device interrupt routines to the
proper ports.
The follOwing describes the assignment of serial interface ports 2, 3, 4, 6", 7,
8, 9 and 10 for different GRAPHIC 8 configurations. Port 1 is reserved for the
host. Port 5 is unused •
..........
i
i
L.:':'::
4-23
.;
I
I
Value in bits 0-3 of the I I
sw:i,tch register represent II
I the number of keyb(lards
II
I....:::;.in::.;.._t;.;::h;,;::;e...;s;;..y~s;..;;t_em;;;:;.~:;........-.-_ _ _ l I
I
I
I
I
I
I
I
I
I
I
I
I.
I
I
I
I
II
I
II 3 7 2 9 10 6 S 4 I
11"""-17 2. 9 10 6 8 4 I
II 3 rl2 9 10 6 8 4 I
II 3 7 rig 10 6 8 4 I
II :3 7 2 9T106 S 41
II 3 7 2 9 10 16 a 4 I
II 3 7 2. 9 10 rl8 4 I
II 3 7 2. 9 10 6 TI4 I
II 3 7 2. 9 10 6 8 7+1
II
.I
II 1·· i 34 5 6· 7 . ·8 I
I I I
II Ports for Keyboard No.. I
0
1
2.
3
4
5
6
7
8
I
.
I
I
Ports left for PEDno.
I
I .1.
8
7
, ..
6
5
4
3
2
. . i.
1
NOTE
With respec:tto sedal interface registers,
receive I1een the GRAPHIC 8 and the
host: c.omputer. This address lll\.lSt be the address of an even-numbered byte. Each
time the parallel interface completes a DMA word transfer. the address in the memory
address register is incremented by two bytes.
4-32
I
f
f
(
f
I
{
I
STATUS REGISTER n
ISTRn!
15
14
I
I
I
13
I
I
I
12
I
I
I
11
Octal address : 1 i2414 (STRl)
172434 (STR2)
10
9
7
8
6
I
5
4
3
2
1
o
I
I
INPUT NOT READY
INPUT INTERRUPT EN'ABLE
INPUT WORD REQUEST _ _ __
SPARE INPUT NO. 2
ATTENTION INTERlUJl?T"'--E~NA~BL~E~-ATTENTION NO. 2 _ _---.;_ _ _ _ _ __
ATTENTION NO. 1
WORD COUNT';' ZER.-::"'O--------------
OtJ'l'PUT CONTROL
OUTPUT
INTERRUP·-=:T-=E=-=N':'?A~B~LE~-------------
OUTPUT WORD RECEIVED _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
DMA COMPLEtE
DM..<\' I/O MODE - - - - - - - - - - - - - - - - - - - - - - ADDRESS BIT 17 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
ADDRESS BIT 16
SPARE INPUT N O . - - : . " " l - - - - - - - - - - - - - - - - - - - - - - - - - - -
The status register contains the necess'ary control and status bits to operate
the parallel interface in either a DMA mode or a program control mode. The function
of each bit is as follows:
-o
Bit
1
Remarks
Function
Spare input no. 1
Address bi t 16
1.
Program read/write
2.
Cleared by controller bus reset
3.
The status of this bit is directly
presented to the host c~puter for
programming as required
1.
Program read/write
2.
Cleared by controller bus reset
3.
This bit and address bit 17 (bit 2) are
used in conjunction with the address in
the memory address register (MARn) to
expand the DMA addressing capability to
128K words
.
4-33
[
2
Remarks
Function
Bit
Program read/write
Address bit 17
2
:3
3
4
DMA
rio
mode
DMA complete
Cleared by controller bus reset
This bit and address bit 16 (bit 1) are
used in conjunction with the address in the
... memory address register (MARn) to expand
~. the Dt-1.A addressing capability to 128K
words
1
Program read/write
2.
CJ,.ear~d
3.
set, indicates DHAinput operation
(transfer of words from GRAPHIC 8 to host;:
computer). ~en cleared, indicates DM..<\'
output operating (transfer of words
from host computer to GRAPHIC 8)
by contz'oller bus reset
~oJhen
4.
This bit iSW'I'itten by the program prior
to a DMA operation; it lllUSt not be changed
until the DMA operation is complete
1.
Program read only
2.
Cleared by controller bus reset
3.
Cleared when DMA operation is initiated
4.
This bit is set at the completion of a
DMA operation
5
Output word
received
f
I
I
f
I
f,·e
(
I
I
t
I
1.
Program read/write (set only)
2.
Cleared by controller bus reset
3.
Cleared whenever output control (bit 7) is
cleared
I
4.
This bit iasent to the host computer to
indicate that data has been received. It
is set by the program either when a data
ready interrupt occurs or-when output
c!)ntrol (bit 7) is sensed as being set
(,
5.
During a DMA output operation, this bit
is set by the interface
{
I
I
r
4-34
I
.-
Bit
Function
6
Output interrupt
enable
Remarks
1.
Program read/write
2.
Cleared by controller bus reset
3.
Setting this bit enables the interface
to generate a data rea~y or a DMA complete
interrupt
4.
Interrupt trap address (octal) for each
regist.er is:
STRl - 000124
STR2 - Unassigned
7
Output control
1.
Program read only
2.
This bit, when set, interrupts the display
processor to indicate that output data
is available from the host computer. It
reflects the status of the output. control
signal from the host computer
1.
Program read only
2.
Cleared by controller bus reset
3.
Cleared when value in word count register
(WCRn) equals zero
4.
Set when WCRn contains non-zero value
1.
Program read only
2.
This bit reflects status of attention no. 1
signal from host computer. If attention
interrupt enable (bit 11) is set, a high
attention no. 1 input will cause an optional
interrupt to the display processor to be
generated
1.
Program read only
2.
This bit re,tlects status of attention no. 2
signal from host computer. If attention
interrupt enable (bit 11) is set, a high
attention no. 2 input will cause an optional
interrupt to the display processor to be
generated
I. ,
8
9
10
Word count .;
zero
Attention no. 1
Attention no. 2
.. J
4-35
r
Bit
Function
11
Attention interrupt enable
Remarks
1.
Program readhl1ri te
2.
Cleared by controller bus reset
3.
This bit, when se.t t aliows the interface
to generate an optional interrupt to the
display processor when either attention
no. 1 (bit 9) or attention no. 2 (bit 10)
goes high
4.
Interrupt trap address (octal) for each
register is:
I
I
I
I
I
stRl - 000130
SIR2 - Unassigned
12
13
Spare input no. 2.
Input word request
1.
Program read/write
2.
Cleared by controller bus reset
f
3.
The status of this bH is directly
presented to th!; host computer for
prograIllm.ing as required
{
1.
Program read/write (set only)
I
2.
Cleared by controller bus reset
3.
If a single word ,transfer to the host
computer is de.sired~ the program loads the
input data register (IDRn) wi th the word
and then sets this bit to indicate that
the da ta is available. Either an input
i.nterl"upt or sensing i;:ha t input not ready
(hi t IS) is cleared indicates tha t the
transfer is complete.
4.
During a. DMA input operation, the interface
loads data from memory into the IDRn and·
then sets this bit. The bit is cleared
whenever a new d;~ta ready (NDRY) pulse
occurs (the interface generates an NDRY
pulse for the host computer whenever the
input: control signal from the host computer
goes high).
,f
I
(
I
(
I
I
{
4-36
I
-Bit
Function
Input interrupt
enable
Remarks
1.
Programread/write
2.
Cleared by controller bus reset
3.
This bit, when set, enables the interfac.e
to generate an interrupt to the display
processor to indicate either that data
has been accepted by the host computer or
that a DMA transfer of data to the host
computer is complete
•
o
4.
Interrupt trap address (octal) for each
register is:
J-
snu ...
000120
STR2 - Unassigned
15
.~
Input not ready
1.
Program read only
2.
When set, this bit indicates that a transfer
of data to the has t computer is in process.
It is cleared when input word request
(bit 13) is cleared and the input control
signal from the host computer is low
.j
4-37
~J
r
.,
(
IOORn!
OUTl?TJ1' DATA REGISTER
or
or
I IPRnl
Oc.tal a.ddress:
172416 (ODR1 or IDRl)
172436 (ODR2 or 1DR2)
f
r
INPUT DATA REGISTER
15
i
14
13
12
11
10
9
8
7
6.
5
4
3
2
1
o
OUTPUT OR INPUT DATA
The data register is a dUal-purpose register referred to as an output data
register (OORn) when data is being transferred from the has t computer to the GRAPHIC
8 and as an input data register (IDRn) when data is being transferred from the
GRAPH.IC 8 to the host computer.
When used as an OoRxl., the register is a program read only register the contents
of which reflect the states of the data lines from the host computer. The program
reads the contents of the register either when a data ready interrupt occurs or when
output cOfitrol (status reg.ister bi t 7) is sensed as being set. During an output DMA
operation (tra.nsferring data from the host c.omputer to the GRAPHIC 8) the interfac·e
loads the ODRn contents Lntothe GRAPHIC 8 memory.
wnenused as an IDRn, the register is a program write only register the
contentS of which are directly presented to the host computer. It is cleared by a.
controller bus reset. During an input DMA operation (transferring data from the
GRAPHIC 8 to the host computer) the interface lQads the IORn with data from the
GRAPHIC 8 to memory. Puring transfers of $ingle words, the program loads the data
into the IDRn and then sets input word request (status register bit 13).
NOTE
The parallel interface will provide either hig11true or low-true data to the host computer.
Similarly t the interface will acc.ept either hightrue or low-true data from the host computer.
I
I
[I
f
l:
f
f
I
(
f
I
f
I
{
4-38
[
~-,,:..
.~
•
SECTION 5
GRAPHIC CONTROL PROGRAM (GCP)
5.1
DESCRIPTION AND PURPOSE
..
The Graphic Control Program (GCP), a program in read only memory (ROM), is the
central intelligence of the GRAPHIC 8. GCP allows the user to easily control the
interactions between the h~man and Graphic system responses. This program handles
all the tasks for the GRAPH!C 8 that must normally be programmed for other display
systems. The soft'Ware engineer, therefore, need only be concerned with the
generation of software for the host computer. Specific tasks performed by GCP with
no requirement for host intervention include:
•
Rou.tine housekeeping
•
Handling of all operator inputs
•
Handling of trackball/forcestick or data tablet manipulations
•
Handling of all graphic controller interrupts
•
Insertion of keyboard data directly into a refresh file
•
Formatting of messages for GRAPHIC a-to-host communicat!ons
L·
.', .....
. : ....
.
When the GRAPHIC 8 is initialized in the system mode (refer to Section 2), all
peripheral devic.es are automatically initialized without any action by the host and
GCP is able to accept messages from the host. As detetinined by the host application
program, the GaAPHIC 8 is also enabled to format and transm.i.t various types of
messages to the host. The host application program determ.i.nes the manner in which
data in messages from the GRAPHIC 8 will be processed and the type of data that will
be returned in messages to the GRAPHIC 8. For controlling these operations, the
application programmer has full access to all control registers of the terminal
controller.
Generations of all display instruction codes and management of the refresh file
must be accomplished by the application program resident in the host computer or by
software down-loaded into the GRAPHIC 8. For most computers, display instruction
macros can be used to simplifY,this task. Extended macro assemblers that contain
the display instruction macros already exist for some computers (refer to Appendix
B). Other methods of generating display instruction codes include host-resident
graphic suport packages and data statements. A package of this type available as an
option for the GRAPHIC 8 is the host-based FORTRAN support package (FSP) •
.•• J.
5-1
r
J
--
5.2
HOST/GRAPHIC 8 COMMUNICATIONS .
All communications between the host computer and the GRAPHIC 8 are handled by
GCl?
Transm,issionsin either direction are referred to as messages. Each message
begins with a command header that contatne two ASCII characters to define the
message typ'El. The heClder is then followed by as many 16-bit words as are required
to transmit the associated data. The general fot'tl1 of all messages is as follows:
MSB
15
I
I 0
LSB
..
I
14
13
12 ,.11 . ., 10
ASCII caARACTER
1
,
9
7
8
NO. 1
0
6
I
I
I
5
4
"
I
1
I
ASCII CH.A.aACTER NO.2' Command header
I--~----------------~--~------------------I
1
l
1-'
I
I
I
I·
WORD 1
I
I
,'I
t
. ". "
,
,
t "".
'f
. . 'f
f
WOlUl 2
•
WORD n
I
1
I
II
I
I
I
'I
I
--~----------~-----------------------------------•
•
I
1
1-
Associated
data
(i£ any)
1
.., ,
.
I
I
~
1
I
_I
5.2.1 SERIAL INTElFACE COMMUN!CATION:S. When communications with the host: computer
are. handled over a serial· interfac.e, the da.ta portion of ea;eh rneSSf,ge must be .
converted to ~ ASCII forntat. This translation is required for· rneesages tTansmitted
in either direction. For GUPKIC 8-to"'host rnessages ,the translation is accom....
plished by GCl?
For h01;lt-to"'GltAPH:!C 8 m~s$ages, the translation must be ac¢om'"
pl1shedby th~hQst cottltluter and GCl' is used to resto.re the data to its original
format:. The resulting lllessages, regartlle$s of cont~!mt, eonsisten:t:irely of the
alphanumeric ASCtI characten A through Z and 0 through 9 terminated with the ASCII
code for a carriage return. The reason for the translation is to ensure that no
ASCI! code is transmitted th.!:l.t might interfere with a host operating system or with
the serial interface itself.
ASC!I. characters used in message cOllUl1S.nd headers are limited to G throu.gh Z.
Since these headers are originally generated in ASCII format, no trC!-nslation is
requirftd. Transll,ttion iii required only for the information c"9ntainftd in the
associated data words. The information in these words is translated into ASCI!
characters 0 through 9 and A through F. Each data word is translated in the
following ~nner:
f
f
"'1
."~.
,
[:
I,
f
I
(
f
(
r
[
(
5-2
.. ,
."
I,~
1
,
.""
[
J
21 . . 0
.3
I
I
.-
a.
The data word is divided into four 4-bit nibbles.
b.
Beginning at the left (the most significant nibble), each nibble is
considered as if it represented its hexadecimal equivalent (0 through F).
c.
The ASCII code for the hexadecimal number is transmitted over the serial
interface (all ASCII codes are transmitted as eight-bit codes with a 0 in
the most significant bit position) •
•
After all data words have been translated and transmitted, the ASCII code for a
carriage return is transmitted as an end-of-message indicator. Table 5-1 shows all
possible bit combinations for nibbles and the resulting ASCII character codes into
which they are translated •
.J
As an example of the translation process, consider the host-to-GRAPHIC 8
message GI 0137008 0007468_ This message instructs the GRAPHIC 8 to transmit
486 decimal words of data in its memory to the host c01D.puter beginning at octal
address 013700. As originally constituted, the message would have the following
form:
MSB
I
I
1,',.
I
15
LSB
14
13
12 .11
,.
10
9
8
ASCII
CODE
I____________________
7
6
5.
4
3
2
.. ,
ASCII I CODE
G
1
oI
I Command header
~---------------------I
. I
BEGINNING ADDRESS
NUMBER OF WORDS REQUESTED
Word 2
!t..._..J!\
!
5-3
[
~
Table 5.... 1.
Data Word Translation Codes
ASCII CODE FOR
HEXADECIMAL EQUIVALENT
RE,XADECIMAL
NIB8LE
EQUIVALENT
0000
0001
0010
0011
0100
0101
OUO
0111
1000
1001
1010
1011
1100
a
00110000
00110001
00110010
00110011
00110100
001:10101
00110110
1
2
3
4
5
6
7
9
C
D
1101
1110
1111
r
00111000
00111001
0100QOOt
01000010
A
B
14
01000100
01000101
010001.10
F
I
I
I
"
1
0
I
I 0
I
0
,I'
o
"
0
i
0
1
9
1
7
8
'I
1
"
5, \ 4
6
a
1
0
'i
0
3
1
1
1
1
1
2
I
1
r '
0
'
1
",
0
(
1
J.•
it'
0
0
0
0
0
1
1
0
0
1
0
a
0
0
0
1
0
0
1
1
0
'
1
1
I Gl
I
I
0 I 01370°8
I
0
i· . .
"
, :~ .
i'
I! ~
I
1
0
0
t
0
0
'
(.
f
I
I
I 0007468
I
I
(
I
{'
5-4
"
OlOOnOn
E
12 11 10
13
o
J
(
Which, in. bina:t:Y fom is:
15
(
[,
,
OOllOUl
8
r
(
The command header, which is already in ASCII form, is transmitted as is in two
bytes with the high-order byte being transmitted first. The two data words are then
divided into eight nibbles and translated into ASCII codes as follows:
Hexadecimal
Equivalent
1
7
00110001
00110111
01000011
00110000
C
o
":'"
ASCII
Translation
I
000
1
0
1
1
1
1
1
000
0
0
0
1
·1
--------------~------------~------------~------------
o
00110000
00110001
01000101
00110110
1
E
6
o
0
000
0
0
1
1
1
1
0
0
1
1
0
After the ASCII code for a carriage return has been added at the end, the final
message resulting from this example would appear as follows to be transmitted one
byte at a time over a serial interface:
1- I ASCII
Command
header
Starting
address
data word
o
G CODE
<
1_ 1 ASCII I CODE
o 100
,,-
o
I
, ASCII 1 CODE
0 1 1 000 1
00110 1 1 1
1
ASCII C CODE
o 100 a a 1 1
!
1_
ASCII 0 CODE
<
,- , ASCI! 0 CODE
1
a 0 1 1 000 0
aa
1 1 000 0
I
I ASCII 1 CODE
I
I
ASCII E CODE
a
ASCII 6 CODE
00110110
ASCII CR CODE
00001101
<
,_
Terminator
100 1
ASCII 7 CODE
or
Ending
address
data word
1 000 1 1 1
00110001
1 0
a0
101
5-5
(
5.2.2 PARALLEL INTERFACE COMMUNICATIONS. l,fuen communications bet'ween the host
computer and the GRAPHIC 8 are hand.led over a parallel interface, messages in both
directions are transmitted in the binary 16-bit word format in which they are
originally constituted. No translation of the data words is necessary and no
end-of-mess.age indicator is required. Note, however J that ASCII codes are used for
the two characters in the command header regardless of whether the message is
handled over a parallel or a serial interface.
5.3
f
I
f
HO$T/GWFJ.IC.'3 -MESSAGES
,
There ate nine different groups of messages tra.nsmitted betwaenthe host
computer and the GRAPHIC 8. These groups are listed below:
f
1.
Itlitialize and error messages
2.
Establish I/O transmission mode (polling/non-polling)
3.
Memory relatEld messages
4.
Interrupt rEliated messages
s.
Keyboard related messages
6.
Positional entry device related messages
7.
FOR.'1'R.A"'\~
8.
Option messages
9.
3D coordinate converter massages
support (FSP) n'lessages
5.3.1 IN!TIALIZE AND ERR.OR. MESSAGES.
followin.g messages:
f
The initialize and error group consist of the
HOST-to-GRAPRIC 8 (H.-)G8)
IZ
I
I
L
Initialize
GRAPHIC a-to-HOST (GS-)H)
x:x:
The follOWing paragraphs discuss these messages and give details concerning the
format and application of each.
I
(
(
(
(
I
f
5-6
I
;
I
I
0
I
I
I
14
.
, 13
Command h~der code (octal):
INI!L\LIZE
IIZl (H->G8)
. 15
I
~:
12
11
10
ASCII I CODE
9
8
7
0
I
6
I
I
5
d:
3
2
1
044532
0
AS,CII Z CODE
Command header
. .;
The initialize m,ssage is a single-word message ~hat causes the GRAPHIC 8 to
initialize in the system operating mode (refer to Section 2). Initialization in the
system mode results in the following:
a.
Associated display indicator(s) goes blank.
b.
Associated keyboard(s) and PEDIs are enabled.
Built-in diagnostic tests are performed.
d.
The results of the diagnostic tests are sent in an XX message to the host
computer.
NOTES
1.
An IZ message is recognized by the GRAPHIC 8
only when the GRAPHIC 8 is operating in the
system mode. If the GRAPHIC 8 is operating in
the local mode, the host computer ntUst first
generate a hard-Wired INI! Signal (if a
parallel interface is used) or a RING+ signal
(if a serial interface is used). or the
operator must press the SYSTEM switch on the
GRAPHIC 8 front panel.
2.
After an IZ message has been sent, no further
message should be sent from the host computer
to the GRAPHIC 8 until an XX message has been
sent from the. GRAPHIC 8 to the host computer.
3.
When the GRAPHIC 8 is operated in the teletypewriter emulation mode (refer to, Section
2), initialization in the system mode can be
accomplished by sending the code for ASCII
character group separator (octal code 035)
from the host computer to the GRAPHIC 8.
5-7
{
f";
Igi
ERROR STATUS
(G8->H)
15
I. I
I 0 I
I I
13
14
12
11
10
ASCII X CODE
9
Command header code (octal):
8
7
6
4
5
3
2
1
,
"I
Co Illlll-and Header
" 'f
"
ERROR B:r:rS
i~otd
!
!
BIB
I
1
i-lord 2
I'P"'~
I
0
000
o o o o
0
I
.
ADDITIONAL INFORMATION
I
.I
I
I
0
ASCII X CODE
0
054130
o
o o o
o
Word 3
Whenever the GRAPH1C 8 is initialized in the system mode (refer to paragraph
2.3), an x.."{ message is automatically sent to the host computer to indicate the
results of the diagnostic tests performed and the ROM checksum calculated during the
initialization routine: When the GRAPH.IC 8 is operating in the system mode t x..'{mess.a.ges at'.€! also automatic:;ally sent to the host computer (pro\rided that error detection has been enabled via the 1M message) whenever an error condition is sensed by
Gel?
There are four casiccategories of xx. messages, each of which has a slightly
different format for words 1 and 2. 'The make-up of ~"ords 1 and 2 for each category
is as follows (a 1 in aoit position marked .. X" indicates an error condition or
failure of a diagnostic test):
(
{
L
I
(
I
I
I
a.
Initialization XX message:
15
I
14
11
10
9
8
7
6
5
4
3
2
1
o
010
o
o
o
o
x
o
x
o x
x
x
12
13
I
I
11100
I
I
I
Word 1
Word 2
ROM CHECKSUM
Bits in word 1 indicate the following:
Bit
Bit
Bit
Bit
Bit
Bi t
0
- results of interface diagnostic test
1
2
4
- results of graphic controller diagnostic test
- results of display processor diagnostic test
- results of 3-D Converter diagnostic test
6
- results of read/write memory diagnostic test
set to 1 indicates initialization XX message
15 -
.,
;
All other bits are always zero.
Any possible combination of test results can be indicated.
Word 2 contains the result of the ROM checksum calculation.
b.
Normal running XX message:
15
14
I I
101
I I
X
a
a
13,
12
11
10
9
8
7
o
6
5
4
3
2
1
0
a
o
x
o
o a
Word 1
o
Word 2
0
!
oI
I
X
x
o
a
x
o
o
0
a
a
o
o a
I"
o o o o
o
Bits in word 1 indicate the following (when set to 1):
I
- incorrect message format sent by host computer
- unidentified internal interrupt detected by display
processor
Bit 10 - GCP serial interface buffer is full
Bit 11 - GCP serial interface buffer is 7/8 full
Bit 14 - Command header not recognized by GCP
Bit 3
Bit 7
All other bits are always zero.
Any combination of errors can be indicated.
Word 2 contains all zeros for bit 3, la, 11 and 14 type errors. For bit 7
errors, word 2 contains the address plus 4 bytes to identify the address
of the unidentified internal interrupt.
Change 1
5-9
c.
r
r
Buffer XX message:
15
I I
I 0 I
I I
0
I
0
13
14
12
0
I
I
I
I
0
'
I
0
0
,
'
10
11
I
9
8
7
6-
0
1
0
0
'
I
I
ASC'II CHAR NO. 1
I
I
I
I
5
4
3
2
1
0
0
0
0
0
0
0
,
I
i
"
I
(
Word 2
~,
A buffer xx. message is sent when no output buft'er is ava:!.lahle to Gel? for a
messlilge to be sent to 'che host c.Qntputer. Bit 8 in word 1 identifies the meuage as
. a buffer XX message; all other bits in W'o1;d 1 are always zero:. W01;d 2 is the
command header £01; the meuage that could not be sent to the host cODlputer.
d.
14
I I
I 0 I 0
I 1
I
I
I
12 ,11
13
0
"
0
!
,
0
I
0
0
0
4,"
I
I
r
I
I
10
9
' I
0
1
0
f
0
0
0
I
I
I
7
8
I 0
I
0
0
0
I
6
,
,
,
'i
0
I
I
I
5
'
0
0
I
I
4
3
0
0
,
,
'I
'
,
0
,
0
I
I
I
I
2
1
0
0
0 I 0
,
0
Word 1
,
,
0
1
-
- -
14
0
0
1
1
0
o
1
1
2
3
0
1
:',:'"
"
..
Word 2
J
Bits 14 and 15 of word 3 contain the bank number aSsociated with the XX
Message. Bits 14 and. 15 are defined as follow,s:
Bank.NllIllber
(
( 1'-
For all XX messages:
15
r
'
0
A characte1; ove1'1;ua XX messagl! is sent whenever a character overrun condition
or padty error is c1eteet ed at the serial intedace port used for communications
with the host eom:puter (normally port 1). Bit 9 in 'word 1 ident1fielilthe XX message
as a character oV'er1:'Un XX m.essage; all other bits in word 1 are always zero. Word 2
identifies the port on Which the overrun WaS detected (GCl? assum.es sedal communications With the host c013lputer are. handledV'i$. port 1. Therefore, word 2 of a
character Qverrun x.tm.essage always has a binary value equal to 1).
Bits
I'"~
r
Character overrun XX meuage:
15
'·1
Word 1
"
ASCII CHAR 00. 2
0
[
(
[~
,
.. :
I
r ':~
I
[
I,
[;
5-10
I '"
The eatablish I/O
5.3.2 ESTABLISH I/O TRANSMISSION MODE (POLLING/NON-POLLING).
transmission group consists of the following messages:
HOST-to-GRAPH~~
--.-
8
1M
Initialize I/O message formats
PL
Poll GRAPHIC 8 for next message
NO
No operation
GRAPHIC 8-to-HOST
NM
i,
The following paragraphs discuss these messages and give details concerning the
format and application of each.
-
11M1
I
I
I
I
0
I
I
0
I
I
14
13
12
11
, 10
9
8
I
I
I
ASCII I CODE
I
'\
INITIALIZE I/O MESSAGE FORMATS
(H-)G8)
Command header code (octal): 044515
15
·1_
No messages ready
D
D
D
D
D
D
7
6
5
4
3
2
1
I
I COnml.and Header
I
ASCII M CODE
0
0
I
D
0
0
0
0
D
D
D
D I Word 1
I
The 1M message is used to activate or de-activate error detection and to
initialize GCP to operate in either a polling or non-polling mode.
',=:t'
5-11
'!
;.---~
r
:\'>
1:
A detailed description of the meaning of all bits i& WORD 1 is given below:
~{
:ill
o
Polling
o
1
1
Rost to GltAl?'f!IC 8
data not packed
{
Descr~pt:ton
GCl? operates in non-polling mode (i.e.,
messages ar~· automatically sent to HOST
when a message fsready.)
Gep operates in a polling mode (i.e.,
the HOST must issue a poll (pt).. message
each time the 'f{oSt wants the nelCt
message from the GRAPHIC 8.)
In this mode, Gel? does not respond eo
polls until a message is ready for
transmissiori to the iost.
Send poll
message back
1
2
~
Value
0
1
In this mode, if the Gel? output buffer
is empty,' a dUllUl1Y NM me$Sage is sent
back to the HoISt to indicate that the
GCl? output buffer :i.a empty.
GCP i1,lterprets all data wPrcls sent from
the HOST to be in packed format·.
Gel' interprets all data words sent from
the HOST to· be in :t:ntag e fo mat.
3
Ac.tivate enol'
detect1c>n
a
Gep ignores all command header errors.
This pel:'lDi ts the operatiQft. of GeP in
serial full .. duplex mode. Messages
eChoed back to GRAPHIC 8 frtlUl Host are
ignored.
1 .
Gel? validates all conmxand headers; when
er1::'ors are deteeted, an appropriate XX
error messa.ge is sent to the HOst.
,I
I
(
(
-~1
I
lI
(
,<
(
r
( 1-
(
( ~.
I
"
I,:
(
(
r
I
[I
"
-~
•••
these b1ts are reserved for future
expansion.
... '"
r
Description
Bit
8-14
These bits operate in conjunction with
bits 0 and 1.
Special poll
character
If bits 8-14 are all zeroes, GCP sends
messages back to the Host anytime a PL
message is received.
If bits 8-14 contain any non-zero
value, then GCP does not send a message
to the Host until the Host sends a PL
message followed by the special poll
character. Effectively, when GCP
receives the PL message, it prepares a
message for transmission to the Host.
It then waits for the special poll
character before the message is sent to
the Host. The special poll character
is sent by the Host to indicate that it
is ready to receive the next GRAPHIC 8
message. The special poll cha:racter
permits operation with operating
systems that use a special character to
turn around (change direction) a serial
communications line from output to
input.
NOTE
By default, GCP is initialized so that all bits
(functions) represented by word 1 of the 1M
message are set to o.
When GCP is initialized by the IZ message, it is set up to operate in a
non-polling mode. In this mode, whenever GCP has a message stored in its output
buffer, the message is automatically sent to the host computer (i.eo, GCP is
operating in an asynchronous or non-polling environment).
~.
By setting bit 0 of word 1 of the 1M message to a 1, GCP can be set up to
operate in a polling mode. In this mode GCP only sends a message to the host
computer when the following two conditions exist.
1.
GCP has a message stored in its output buffer.
2.
The host has issued a PL message. The PL message tells GCP that the host
computer is ready to receive the next message and that GCP should send it.
If a message is stored in the output buffer, GCP immediately sends it to
the host computer. If no message is stored in the output buffer, GCP
waits until a message gets stored in the output buffer, then it sends the
message to the host computer.
, ..,
~,"":;J
I
5-13
r
Bit 1 of word 1 works in conjunction with the way bit 0 has been set up. When
bit. a is set up for non-polling mode (bit 0 "" 0), the value of bit 1 is ignored.
\fuen b:i,t 0 is set up for polling mode (bit 0 :=: 1), GCP operates as follows:
1.
2.
When bit 1 is 0, GCP
previous paragraph.
ope~ates
in a polling mode as described in. the
When bit 1 is 1, GCP operates in a. polling mode that is slightly different. In this mode, after GCP receives the PL message, it does one of
the following:
( 1)
If a message is stored in' the output buffer, GCP immediately sends i. t
to the has t COttlput er.
(2)
It the output buffer is empty, GCP immediately sends a NM dummy
message to the host computer. The NM message indi~ates 'to the host
computer that the GCP output buffer is empty and that the conununications line between the GRAPHIC 8 and the host computer is still
act:i.ve.
The special poll character is applicable to serial. communications only. This
character i i defined in bits 8 t.hrough 14 of word 1. The special character poll
mode jol'orks inconjunctiortw:i.th the way bits a and 1 have b!';!en set. up. When bit 0 is
0, the spe<::ial poll character is ignored by GCP. Setting bit 0 to a. 1 activates the
special poll cnatacter bits. If t.he special poll character is set up for 0 (i.e.,
bits 8 through 14 are 0), the polling lllodes previously described are in effect. U
the special poll character is set up with non-zero value, then the following special
p()lling mode is activated.
1.
Host computer sends aiL message to Gep.
2.
Host computer sends the special poll character to GCP.
3.
After GCP receives the PL message followed by the special poll character,
the ne.~t message :1.$ sent t.o ttte host computer.. The sending of this
tnessage is based on whether the output bll,ffe.r has a mess.age and the ,oI'ay
bit 1 has been set; up.
Bit 3 of word 1 of the 1M message. is used to .activate the detection of command
header errors. By default, Gel' is initialized to ignore all conunand header errors.
By setting bit 3 toa 1, GCl? can be activated to validate all command headers. Tilhen
GCP detects that the host computer has sent an invalid GCP message, it stores an
appropriate XX error message in its output buffer.
I-
I
[
I
I
I
\
-)..t'l
(
.'-',,",
L
I
I.
f
I
I
I,
I
I
I!
5-14
,,~-
I
The recommended values for word 1 of the 1M message are given below:
Type of Interface
Polling Mode
Non-Polling Mode
Parallel
9 or 11
8
Serial half-duplex
9 or 11
8
Serial full-duplex
(echoing enabled)
1 or 3
0
Serial full-duplex
(echoing disabled)
9 or 11
8
POLL GRAPHIC 8 FOR NEXT MESSAGE .
Command header code (octal): 050114
'':.
15
II
I
I
0
I
I
14
13
12
11
10
ASC!I P
9
8
7
o
6
5
4
3
ASCII L'
2
1
o
Command Header
The poll message is sent by the Host to request that the GRAPHIC 8 send the
next message. This command works in conjunction with the way the 1M command has
initialized GCP.
5-15
[
"
I :~
(
._ ... ,
':
II
(:~i
,
I
,·"",1
. ,"
,,
( ":
.,1
( '1
'.;:J
,
(
j
:
....
.:....
I
I
r"
--.;.,..
(,
I
II
I
The NO message is a single-word meuage that eauses llO operation to be
perfor'llled by GCP. NO ussages are used primarily .as fillers when t;.he host computer
application program requires that all messages sent to the GRAl'H!C 8 be of constant
length.
5.3.3 MEMORY RELATED MlSSAGES.
following:
MS
Memory bank select
MU
Memory
SU
Selective update
RU
SP
HP
Register update
Start picture
lialt picture
Continue pic.ture
Transfer control
KP
n<
GI
GR
The memory related m.essages consist of the
(,
u:p~te
I
(.' -
Give image
Give register
.[
5-16
•
\
r
..
GRAPHIC 8-to-Host
RI
VL
RR
Return image
Variable length
Return register
The following paragraphs discuss these messages and give details concerning the
format and,application of each.
I~I (H-)G8)
MEMORY BANK SELECT
Command header code (octal): 046523
15
I I
I 0 I
I I
X
t. _
14
12
13
11
10
9
8
ASCII M CODE
X
X
X
X
X
7
6
X
X
3
1
2
0
I
I Command Header
I
ASCII S CODE
0
X
4
5
X
X
X
X
X
I
I
I
BANK
Word 1
The MS message is used to select the desired memory bank. This message should
be issued prior to such commands as MD, SU t GU ,and GI if a large memory system is in
use. Sits 2 through 15 in word 1 are ignored by GCP. Bits 0 and 1 represent the
bank" number selected as· given below:
Bits
o
o
o
1
1
BANK NUMBER SELECTED
1
0
o
1
0
1
1
2
3
Below is a table showing the relation of virtual addresses (i.e.; addresses
specified in :tU t SU, GU, and GI messages) to physical addresses when different
memory banks are selected.
BANK ,NUMBER
VIRTUAL ADDRESS
PHYSICAL ADDRESS
RAM PAGES
o
000000-177777
000000-137777
00-05
1
000000-177777
200000-377777
10-17
,2
000000-177777
400000-577777
20-27
3
000000-177777
600000-777777
30-37
. .'i
<--J
5-17
"
1'.
(~'~
[ "",'
,
~
,
NOTE
When GCP is in~tialized by default,. bank. 0 is
selected. Memory bank selection should be taken
into account fQ,r the following Rost-to-GRAPIUC 8
~
messages:
MO, SU, 51','G1. MS, IP, IT, TK., ZR~ ZT, MI, GU
Mem.ory b4nk selection should be taken into account
for the following GWHIC S'"'to-Rost messages:
RI, XX, lII, ,:,XI
"
-
(H->GS)
I
I
IMOI
I
I
15
0
MEMORY UPPAl:!
12 11
14 ,13
1 '
I
I
,'t
10
9
, '.
,7
I
I
I
ASCU M CODE
I
0
I
I
i'
5
6
' t
,
4
3
Z
1
,
,
I
I
I
"
,",1
t
f
' I
I
..
'"
,
'
I
Command Header
r
f·
.",
,
0
"
,t"
ASCII U CODE
LOAD ADDlti!!
,
I
I
[
'Wor<:i 1
0
",:'
'f.,':
(
"
NllMBER OF DATA WORDS TO BE LOAI)EP
,'Word 2
[
t'
"
DATA WORD
'Word 3
•
•
•
I '
'"
DATA WORD
'f
,,'
i
i
I
I
I
'Word n
The MU message is a V'ariable"'length message used to load data into the
t'ead/wri te memory of the GRAPHIC 8. the load address specifie4 in wot'd 1 tells GCP
the address at which loading of the data should begin. !his address must be the
address of an eVen-num\:tfu:ed byte. An odd. add.ress will result in an XX (error
status) me,seage being returned by the GRAPHIC 8 and data will not be loaded.
I
,
( ,
(
5-18
..
COlDll1Snd header code (octal):" 046525
8
l
.. ;
,<
Word 2 specifies the total number of data words that are to be loaded into
successive read/write memory locations. This word is then followed by the data
words to be loaded.
When a memory update message is sent from the host computer to the GRAPHIC 8,
CCP halts the graphic controller (this blanks the display indicator). The GRAPHIC 8
then remains halted until a KP (continue picture) or SP (start picture) is sent by
the host computer. For lengthy memory update messages, thi.s can result in
noticeable blanking on the display indicator.
!~I
15
14
13
12
11
10
9
8
I
ASCII S CODE
I1__
0 I __________________
1
~I
Command header code (octal): 051525
SELECTIVE UPDATE
(H-)G8)
7
6
5
4
3
2
1
o
o ________________
Ascn U CODE
___
~~
LOAD ADDRESS
o
Command Header
Word 1
NUMBER OF DATA WORDS TO BE LOADED
Word 2
DATA WORD
Word 3
DATA WORD
Word n
The SU message is a variable-length message that operates in exactly the same
manner as the MU (memory update) message except that the digital graphic controller
is not halted. Therefore, if an SU message is used to update a refresh file
currently being processed by the graphic. controller, the file must remain 'lalid as
each data word is replaced •
.. ~.j
5-19
f
~1ore
commonly, an SD message is used to loa.d a new refresh file into a
different area of memory while an older file is being processed by the gra.phic
controller. After loading of the new file is complete, an SF (start picture.)
message from the host c,omputer causes the graphic controller to process the new
file. This assures that the display will not be blanked while the data is being
transferred as occurs when an MD (memory update) message is used.
IRUI
15
REGISTER UPDATE
(&->G8)
14
13
12
11
10
9
I I
I1___
0 I __________________
ASCII R CODE
I~
Command header code (octal):
8
~~
7
6
0
__
ASCII U CODE
I Command Header
____________________
,__ 1
~
5
4
3
2
1
OS1l2~
0
--;--1
r'
ADDRESS
I1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _REGISTER
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
Word 1
[
[
(
r
t'iord 3.
I
I
Word n
f
. The RU message is a variable length message that is used to update a series of
registers in the!/O address area of the hardware. Word 1 contains the address of
the first register to be updated.. Valid register addresses are in the range of
160000-177777 (octal). Word 2 contains the register count indicating the number of
succ.essive registers to be updated. Words 3 through 1'1 contain the data values to be
loaded into each register.
NOTE
!he au message does not change the current memory
bank. selection. It is also possible to interpret
registeraddre$s as memory address in the above
message. When updating memory address, the llaer
must take into account memory mapping. Memory
addresses inche range of 020000 to 077777 are
subject to memory mapping.
.~~
;1
:j
.. j
(
r
REGISTER DATA
.')
r ",
REGISTER COUNT
REGISTER DATA
I
i'
-!
I·
I
I
I
I
[
r
Isp I
15
J
"O-
,
J
0
START PICTURE
(H:-)G8)
14
13
I
I
I
12
11
10
9
Command header code (octal): 051520
8
ASCII S CODE
7
6
5
4
3
2
1
0
ASCII P CODE
0
Command Header
STARTING ADDRESS OF REFRESH FILE
Word 1
The SP message is a two-word message that causeS the digital graphic controller
to begin processing a refresh file starting at the address specified in word 1. The
specified starting address should be the address of an even-numbered byte. If,
however, an odd address.is specified, the low order bit is ignored by GCP and no XX
(error status) message is generated. If the graphic controller is running, it is
halted and restarted at the specified refresh file address.
IHPI (H-)G8)
15
I
I
I
0
14
I
I
I
13
HALT PICTURE
12
11
10
ASCII H CODE
9
Command header code (octal): 044120
8
7
0
6
5
4
3"
2
ASCII P CODE
1
o
I
I Command Header
-'
The HP message is a Single-word message that causes GCP to halt the digital
graphic controller. The refresh file is not altered and the graphic controller
program counter remains pointing at the location of the next instruction to be
processed. Following an HP message, the digital graphic controller remains halted
until an SP (start picture) or KP (continue picture) message is sent by the host
computer.
5-21
r
r
t~
,:j
Igi
I
15
~'
CONTINUE PICTURE
(H:->G8{;
I
14
13
12
11
10
9
8
Command header code (octal): 045520
7
6
.,
5
4
3
2
1
(
o
ASCII P CODE
ASCII K CODE
a
Command Header
I 0 I
I___I __________--------~--~----~--~--------
I
I
The K.1' message is. a single-TNord message used to restart the d.igital graphic
controller at· the instruc.tion following the one at which it halted. Conditions
causing the digital graphic controlle~ to halt include:
a.
,.
b.Rast computer sends MU (memory update) message to GRAPHIC 8
Display processo;r: sends stop function code (165040) to digital graphic
controller
d.
Display processQr executes RESET instruction
e.
HREF instruction executed by digital graphic controller
f.
LINK instruction executed by digita.l graphic controller
g.
Invalid il'l.struction executed by digital graphic contl;'oller
h.
Bl,ls timeout (memory £.ai1sI:0 respond to a fetch .colllPland)
1.
X or ~i position overflow (if interrupt to display processor is enabled)
If the digital graphic controller is running when
a KP message is sent by the host computer, GCP .
returns an xx (error status) messa.ge to the host
computer.
..
JI
.
NOTE
..
(
Host computer sends HI' (halt picture) message to GRAPHIC 8
c.
"'-,
(
I
1
(
I
(,
I
I
I
I
I)
[
5-2:2
i/
(I
"
ITKI (H-)G8)
TRANSFER
Command header code (octal): 052113
CONTR~L
~~\,
15
I
I
,-_ .....
!
I
0
14
13
I
I
I
12
11
10
9
7
8
ASCII T CODE
6
5
4
3
2
1
0
ASCII K CODE
0
Command Header
--'
STARTING ADDRESS OF PROGRAM
0
Word 1
The TK message is a two-word message that causes the display processor to stop
processing GCP and begin processing the program that begins at the address specified
in word 1. This message is intended for advanced applications to permit a program
other than GCP to be processed by the display processor. Normally, such a program
would be down-loaded from the host computer using an MU (memory update) message and
then started by using a TK messag4a. After control has been transferred·, no further
communications via GCP are possible unless the new program deliberately returns to
GCP with an RIS PC instruction.
0
IG!l (H-)G8)
15
I
I
I
0
I
I
I
14
13
GIVE IMAGE
12
11
10
9
ASCII G CODE
Command header code (octal): 043511
8
J
I
I
7
6
5
0
4
3
2
ASCII 1 CODE
1
o
Command Header
STARTING ADDRESS
Word 1
NTJ'MBER OF WORDS REQUESTED
Word 2
The GI message is a three-word message that causes GCP to send back to the host
computer the contents of the GRAPHIC 8 memory beginning at the specified starting
address and ending ,..hen the requested number of words have been sent. The specified
starting address should be the address of an even-numbered byte. If, however, an
odd address is specified, the low order bit is ignored by GCP and no XX (error
status) message is generated.
In response to a GI message, GCP sends an RI (return image) and a VL (variable
length) message to the host computer. The RI message indicates the length of the VL
message while the VL message contains the requested data.
5-23
r
r'-~
.• J
r
[
.1'
" - ... 1
(
~:--I
,'"
(_.GCP retu:rns aa 1U message to the hose computer lnrespanse to aGI (gi.ve image)
messag. frQ1ll the host eOlllputer. Word. 1 specifies the s.tarting address of the data
to be transferred and word 2 speeifies tlie aumber of 16"'b,it words to be transferred.
The data in words 1 and 2 are always the sal\1ll as thedaeain the corresponding words
of the requesting Gt message. a:t.ts 14 and 15 catttain the bartk rtumber that the R.I
message is related to. Ea<:.h Il! message is immediatuy follo'tle-d by a til.. (variable
length) message that eontainsthe data requested by the he,at computer.
~ \.,:
r)
(
(/
[;
I):
( 'i
5-24
IVLI
15
I
I
0
VARIABLE LENGTH
(G8-)H)
!
I
14
13
12
11
10
ASCII V CODE
9
8
Command header code (octal): 053114
7
6
4
5
o
3
2
1
o
ASCII L CODE
I--~I------------------~~~---------------NUMBER'OF DATA WORDS TO BE TRANSFERRED
DATA WORD
Command Reade r
Word 1
Word 2
.,
DATA WORD
Word n
The VL message is the only GRAPHIC 8-to-host message that does not nec.essarily
contain four words.. Its length is determined by the number of data words to be
transferred. In response to a GI (give image) message from the host: computer, GCP
returns an RI (return image) message that is immediately followed by a VL message.
The RI message informs the host computer that a VL message is to follow. 'The I1'L
message contains the data requested by the host computer. Word 1 of each VL message always contains the same data as word 2 of the prec.eding RI message. Words 2
through n of each VL message contain the requested data.
NOTE
Normally, after receiving the RI message, the host
sets up to read in the VL message. For host DMA
operations, the word count speCified to read in
the VL message should be set equal to the number
of words to be transferred (i.e., word 2 of the RI
message), plus two.
5-25
.
,
)
r
GIVE REGISTER
IGRI (H.->G8)
14
15
I
I
I
13
I
0
-
I
12
11
10
ASCII G CODE
9
Command header code (octal): 043522
8
7
6
5
t+
,
"
.;)
2
1
Command Header
I
,
REGISTER (OR MEMORY) ADDRESS
0
I
[
0
ASCII RGODE
0
Word 1
The GR message is a two-THord message used by the host computer to obtain the
contents of the GR...:\.PHIC 8 register specified by the register address in word 1. The
contents of any register having an assigned address may be obtained in this manner.
If required, Gel? automatically halts the graphic controller before the data is
obtained and then restarts it at the completion of the operation. In response to a
GR message, GCl? sends an RR (return register) message to the host computer.
Although the intent of the GR message is to peI"lP.it the contents of registers to
be read, it can also be used to read the contents of GRAPHIC 8 memory addresses.
When it is used to read a memory address, the specified address in word 1 must be
that of an even-numbered byte. If the address of an odd-numbered .byte is specified,
GCP causes an XX (error status) message to he sent to the host computer.
r
1
r
I
.. J
r
J
NOTE
1.
Addresses in the range .of 000000-017776 are
directly addressable.
2.
Addresses in the range of 020000-077776 are
subje.ct to memory mapping.
3.
Addresses in the range of 100000"'117776 are
directly addressable.
I
r
I
I
4.
Addresses in the range of 120000-177776 are
related to ROM and I/O device registers.
I·
When the GR message is used on a large memory
system, the .following restrictions must be taken
into account.
I
I
I
I
5-2.6
, .1
[
I
I
!RR! (G8->H)
15
I
I
I
14
13
Command header code (octal): 051122
RETURN REGISTER
12
11
10
9
8
7
6
5
I
0
I
I
ASCII R CODE
4
3
2
1
0
ASCII R CODE
0
Command Header
REGISTER (OR MEMORY) ADDRESS
0
Word 1
I
CONTENTS OF REGISTER (OR MEMORY ADDRESS)
I1____________________________________________
__ Word 2
II 0
o
o
o
o
o o o
0
o
o
o
o o
o
o
Word 3
I----------~--------~------~------~--------
An RR message is sent by GCP to the host computer in response to a GR (give
register) message from the host computer. Word 1 of an RR message is aiways the
same as word 1 of the requesting GR message. The requested data is returned to the
host computer in word 2. Word 3 always contains all zeros.
5.3.4 INTERRUPT REL.'~TED MESSAGES.
following messages:
The interrupt related group cons ist of the
Host-to-GRAPHIC 8
IK
Interrupt control
IS
Enable selected interrupts
ZI
Disable selected interrupts
GRAPHIC 8-to-Host
HI
Halt interrupt
XI
X or Y position overflow interrupt
The folloWing paragraphs discuss these messages and give details concerning the
format and application of each.
'0-...3
5-27
(
[.
Inl
-.. (a->G8)
15
I
I
I
I
I
14 . j 13
Command header code (octal): 044513
INTERRUPT CONTROL
12
10
11
9
8
I
ASCII I CODE
7
6
2
543
'I
I
a
1
I
I Command Header
I
.1
ASCII KCaDE
0
I
,
I'
I
I
"f i f
" f'·
SELEC'l'ED MASK BITS,
j'
"
""I
I Word 1
I
I____--__~------.-,-.------------------------------
The IX. message is a two-word message used to enable or disable certain GCP
f'U11ctions and to detet'lDine conditions under which thedigi tal graphic controller can
interrupt the display processor. When an IX m.essage is sent, the contents of bits
1... 3 of the word 1 di::t'ectly replaces ,the contents of the graphic controller t!lS.sk.
register ('MXR). The remaining bits of the word are decoded and used to enable or
disabl" associated interface ports. The function or interrupt condition associated
wi th each bi tis as fo llows :
-
BIt
I
FUNCTIONOl lNTERaupt CONDITION
SElUAL. INTEUA,Ci .l?ORT
0
PED no. 4
10
1
Digi1!al Graphic COtttt'oller halt
a
X or Y p():si tion o'\1et'flow
3
Real time cloek
N/A
N/A
N/A
4
Unused
5
Unused
6
Unused
7
Unus.ed
8
unused
9
AlphanuJner ie/f unction keyboard no" 4
a
\
O{"
l.
I
9
10
PEP no.
11
Alphanutlleric/func'tion keyboard. no. 2
7
12
PED no. 3
6
13
PED no. 1
4
14
Alphanutlleric/function keyboard no. 3
2
15
Alphanumeric/function keyboard no. 1
3
8
Note the serial interface ports to dedce aSSignments l11a.y vary for d1fferent
configurations. See section 4.4.1 fot' 11101"e it1£ot'lllati·on on port assigtlments.
I
5-28
Chanse 1
I
Irsl
ENABLE SELECTED INTERRUPTS
(H-)G8)
Command header code (octal): 044523
t· .
15
I
I
I
0
I
14
1.3
I
I
12
10
11
7
8
9
ASCI! 1 CODE
X
X
X
X
I
I
X
3
4
2
SELECTED MASK BITS
X
X
5
.ASCII S CODE
0
I
X
6
1
°
Command Header
Word 1
The IS message is a two word message used to selectively enable mask register
(MKR) associated intert'tlpts. 1£ a ma.sk bit is set to 1, then the interrupt
associated with that bit is enabled. If a mask bit is set to 0, then the interrupt
associated with that bit remains unchanged after the IS message is processed by GCl'.
,
'-
the function or interrupt associated with each bit is as follows:
1.
~_A
-BITo
,F,UNCTION OR INTERRUPT CONDITION
1
Digita.l· graphic controller halt
2
X or Y position overflow
3
Real time clock
••
•
••
_ . .
. . . .
t,
••
Not used
These bits are ignored by GCl'
<
• ~ •...l
5-29
lal
I
I
DISABLE SELECTED INTERRUPTS
(&->G8)
Command haader code (octal): 055111
15
I
I
I
I
14
T
13
aI
11
, 12
10
9
8
I
ASCII Z CODE·
I X
I_
X
X
X
"
, ..
X
7
5.
6
4
X
a
1
2
ASCII I CODE
0
i
I
X
3
f
II
I
,.
I
X
I
Comma.nd Header
.
"
SELECTED MASK BITS
I
I Viord 1,
I
The ZI message is a two word message used to selectively d,isable mask register
(MKR) associated interrupts. If a mask bit is set to I, then the interrupt
associated with that bit is disabled. If a mask bit 1s set to 0, then the interrupt
associated with thllt bit remains unchanged after the ZI message is processed by GCt'.
.·,,1
[
I
'f
{,
"j
".1
''''';1
'
·~"1
.!
I
..',,,,
(
..
.
,'';'':
'the function or interrupt associated with each bit is as follows:
-o
BIT
• FUNCTION
'."
oa
.'.
INTERRUPT CONDITION
t
.'
.' .
'"
.
Not used
1
Digital graphic controller halt
2
X or Y pOSition ovarflow
3
Real 1;:1m,e clock
4-15
It
.-
v_:
l
1
.,
,"
'these bits are ignored by GCP
NOTE
If a data tablet is operating in the auto/tracking
mode, the real time cloek shouldn't be disabled.
f
f
I
f. .
Ii
5... 30
f,
I HI I
15
HALT INTERRUPT
(G8-)H)
I I
I 0 I
I I
14
1.3 • 12
11
9
10
8
ASCII H CODE
Command header code (octal): 044111
7
I
I
I
0
4
5
6
I
I
3
2
1
o
ASCII I CODE
Command Header
I
1
I
.
CONTENTS OF GRAHPIC CONTROLLER PROGRAM
I__________________________
1
I
I
COUNTER (DPC)
.
0
1
I
Word 1
~------------~I
I
I
CONTENTS OF GRAPHIC CONTROLLER INSTRUCTION REGISTER (DIR)
Word 2
1--------------------------------------------I
,.
B
B
o
0
o
. I
0
0
I
1
0
o
I
o o o o o
010
I
.
!it
Word 3
."
When the digital graphic controller halt interrupt to the display processor is
enabled (by a host-to-GRAPHIC 8 IK or IS message), GCP sends an HI message to the
host computer each time that a RREF instruction is executed by the digital graphic
controller. Word 1 of the Ht message contains the contents of the graphic
controller program couIiter (DPC) which is the address of the instruction following
the HUF instruction. Word 2 contains the contents of the graphic controller
instruction register (DrR) which, in turn, is the contents of the address pointed to
by the program counter. Bits 14 and 15 of word 3. contain the bank number associated
with the HI interrupt.
5-31
'I
{
Igl
L
X OR Y POSItION OVERFLOW INTERRUPT
(G8->H)
Command header code (octal): 054111
15
1--1
I 0 I
! I
14
13
12
11
10
ASCII X CODE
9
8
7
I
!
I
6
4
5
3
2
1
0
ASCII I CODE
0
"'I
CONTENTS OF GRAPHIC CONTROLLER PROGRAM COUNTER (DPC)
1
0
1.-I B
I
I
I
0
I
0
0
0
CONTENTS OF X POSITION REGISTER
(Dn)
,1
B
0
0
. I
CONTENTS OF Y POSITION REGISTER (DYR)
I
I Command Header
I
I
'I
I Word 1
I
f
I
I Word 2
I
When an X or Y position overflow condition is
detected by the graphic controller, an interrupt
to the display processor is generated and the
graphic controller halts. Gel' also disables
further X, Y overflow interrupts.
5-32
1_:
I'
','
( I.···i
-I
1 Word 3
I
When the graphic controller X or Y position overflow interrupt to the display
processor is enabled (by a host-to-GRAPHIC 8 IK or IS message), Gel' sends an XI
message to the host computer whenever the graphic controller determines that an X or
Y position overflow condition has been created. An overflow condition e~dsts if the
two's complement value in either the X or the Y position register (DXR or DYR) of
the graphic controller exceeds 17778 (+1023) or 20008 (-1024). An overflow
condition is detected when bits 10 and 11 of the X positionreg:i.ster or the Y
position register are not the same. Word 1 of €m Xl message contains the contents
of the graphic controller program counter (Dpe). This is the address of the second
instruction follo~.ing the instruction that caused the interrupt. Words 2 and 3,
respectivel:y, contain the contents of the graphic controller it and Y position
registers (following execution of the instruction that c.aused the interrupt). Also
bits 14 and 15 or word 3 contains the bank number associated with the Xl message.
NOTE
f,
I
t
·1
I
f
1
I
5.3.5 KEYBOARD RELATED MESSAGES.
following messages:
The keyboard related group consists of the
HOST-to-GRAPHIC 8
ZR
Initialize scratchpad for alphanumeric keyboard no. 1
ZT
Initialize scratchpad for alphanumeric keyboard no. 2
ZS
Zero out scratchpad no. 1
ZU
Zero out scratchpad no. 2
LK
Light keys on function keyboard no. 1
LT
Light keys on function keyboa.rd no. 2
GRAPHIC a-to-HOST
ret
Alphanumeric keyboard no. 1
Kl'
Alphanumeric keyboard no. 2
XR
Scratchpad ready for alphanumeric keyboard no. 1
XT
Scratchpad ready for alphanumeric keyboard no. 2
R...'T{
Function keyboard no. 1
RL
Function keyboard no. 2
The following paragra.phs discuss these messages and give details concerning the
format and application of each.
5-33
INITIALIZE SCRATCHPAD FOR ALPHANUMERU1 KEYBOARD
(H->G8)
IZRj
no. 1
Command heJ'der code (octal): 055122
lEI
no,. 2
055124
14
15
13
II
I
I
0
I
I
12
-
11
10
ASCII Z CODE
9
8
7
6
5
4
3
2
1
o·
I
I
I
1IiII . .
I' .
I
o' I
I Command Header
ASCIIR CODE
--~----------------~~I------~----------I
II
f
II
·t
I
STARTING ADDRESS IN REFRESH FILE
o
Word!
I
NUMBER OF CEARACTERS IN LINE
Word 2
This three word Initialize Scratchpa4 message is used to establish parameters
for handling alphanumeric characters on a line basis frOllt the keyboard. It is used
in conjunction ~'ith a rehesh fU,e that contains an area reserved ,for stora.ge of
cha.racters typed in by the operator. This area, called a scratchpad, typically
consistso£ a sequence of TXt' (draw two tabular characters) irts truction$ with ASCII
codes for spaces.
When an Initialize Scratchpad message is sent by the host computer, GCP begins
collecting characters from the alphanumeric keyboard, and stores them in the refresh
file starting at the address specified in word 1. This .address must be even. Word
2 specifies the total number of characters that may be collected. This number may
be equal to or less than the ca,pacity of the scratchpad.
(
f/
f
'I -',
f
II
Characters are collected in the scratchpad until the total count spec:Uied in
word 2 is reached. At that point, .GCP sends a Scratchpad for Alphanumeric K.eyboard
Ready message to the host computer. RE"l'tmN, which may be typed at any time,
terminates collection of characters and causes GCP to send a Scratch pad for
All'hanumeric Keyboard Ready message to the host computer. The host computer can
then obtain the contents of the scratchpad by sending a GI (give image) message to
the GRAPHIC 8. Hote that typing RETURN only causes the Ready message to be
generated and has no effect on the scratchpad itself. Additional inputs from the
keyboard are simply added to the scratchpad if space is available or ignored if
space is not available.
5-34
:_1
f
\
Characters collected in the scratchpad remain there until a) they are cleared
by a Zero Scratchpad, a SU (selective update), or MU (memory update) message from
the host computer; b) they are replaced when another Initialize Scratchpad message
from the host computer causes the scratchpad to be reused; or c) RUB OUT is typed.
Typing RUB OUT deletes the last character in the scratchpad and permits it to be
replaced with'a different character. Repeated typing of RUB OUT deletes successive
characters in the reverse order of input.
NOTE
When processing on a line basiS is no longer
required, the host computer can cause keyboard
inputs to be handled on a single character basis
by sending an Initialize Scratchpad message to the
GRAPHIC 8 in which words 1 and 2 (address and
character count) are all zeros.. GCP then sends a
JC{ (alphanumeric keyboard 110. 1) bssage to the
host cOtllputereaCh time a character is typed.
ZERO SCRA'rCHPAD
(R-)G8)
t~1
no. 1
Command header code (octal): 055123
1![1
no. 2
055125
15
I I
I 0 I
I I
14
13
12
11
10
9
____________________
,
,
ASCII Z CODE
8
I
7
6
I 0
5
4
3
2
1
o
ASCII S CODE
"
I Command Header
~I--~--~--------------I
The Zero Scratchpad message is normally sent after an Initialize Scratchpad
message has been processed. The Zero Scratchpad message ~auses GCP to replace all
characters in the scratchpad with spaces. After the scratchpad is set to spaces,
the scratchpad input poitlter is positioned to the beginning of the scratchpad area.
NOTE
The Initialize Scratchpad message is used first to
define the starting address and size of the
scratchpad in the refresh memory.
5-35
(
LIGH.T l{E"1S ON FUNCTION KEYBOARD
(H->G8)
(~I
no. 1
Command header code (octal): 046113
lui
no. 2
046124
15
I
I
0
I
12
13
14
11
10
9
8
7
6
5
4
!.
I
o
ASCII L CODE
3
2
o
1
I·
ASCII K CODE
Command Header
I--~I--~,_--~----------~~-------------------
I
I
I
.... ,
I Word
MASK FOR FUNCTION KEY LIGHTS
1
1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1
--,
I
I
f
MASK FOR UATRIX K.E"'i LIGHTS
Word 2
1-------------------The three-word Light keys message is used to light func.tion and/or matrix keys
on a keyboard. B:it 0 through 15 of word 1 are assoc.iated with function k.eys 0
through 15, respecti.vely. Similarly, bits 0 through 15 of word 2 are associated
with matrix keys 0 through 15, respec.tively. If a bit is set to 1, the corresponding key lights; if a bit is set to OJ the corresponding key does not light. The
layout of the function and matrix keys is as follows:
FUNCTION KEYS
I- I •
I
0
!
I
1
- .
I
2
3
4
5
I
I
6
I 7
I
I
8
I
1
I
9 110
!
I
I
i
I
I
III 112 113 114 115
I
I I I I
~:!ATRIX
I 7 I
I 4 I
I 1 !
I 10 .. ,
8
5
2
0
KEYS
9
6
3
11
r 15
I
I
I
14
13
12
I
5-36
(G8-)H)
15
ALPHANUMERIC KEYBOARD
no. 1
Comll1a.nd header code (octal): 045531
no. 2
045524
I
I
I
14
13
12
11
10
9
8
7
6
5
4
3
2
1
o
I'
o
ASCII K CODE
ASCII Y CODE
Command Header
I
I
'
I
ASCII CHAR CODE
Word 1
I 0 I 0 000 0 0 I 0
I
I__________~--------I~~-------------------I
I
I
010
I
I
I
I
0
I
I
I
o
0 100
'I
0
o
010
I
I
I'
0 I 0
I
0
o
0
o o
o
0
o
010
o
I
I
0
i
0
I
I
I
0
o o
Word 2
0
o
o
Word 3
{
'.
..~.
Alphanumeric ley board messages are associated with alphanumeric inputs from a
keyboard. Ea.ch time an alphanumeric key is typed, GCl' sends the message to the host
computer if the following conditions are met:
a.
The keyboa.rd is enabled (refer to host-to-GRAPHIC 8 IK messages).
b.
The keyboard is not bEling operated in the scratchpad mode (refer to
host-to-GRAPHIC 8 Initialize Scratchpad message).
If thekeyboa.rd is not enabled, typed inputs are ignored. If the keyboard is
being operated in the scratchpad mode, inputs are sent to the host computer in RI
(return image) messages. Each Alphanumeric Keyboard message sent to the host
computer contains the ASCII code for a single alphanumeric character (refer to
Appendix A for a summary of keyboard codes). This code is contained in the low
order byte (bits 0-7) of word 1. Words 2 and 3 always contain all zeros.
NOTE
Keyboards are automatically enabled by GCP when
the GRAPHIC 8 is initialized in the system mode.
I
.,J
5-37
1
(
SCRATCHPAD READY FOR ALPHA.NUMERIC KEYBOARD
(G&->H)
lXiI
no. 1
Command header code (octal): 054122
Ix'!l
no. 2
054124
IS
II
14
I
13
12
11
9
10
8
7
5
6
4
3
2
1
·t
,(
0
I
I
I 0 I
I
I
ASCII X CODE
I
I
I
ASCII R COPE
0
NUMBER OF CHARACTERS IN
II 0
I
0
0
0
0
00000
0
0
0
0
0
0
0
0
Command Header
Wor.d 1
SC~4..TCHPAD
0
o
0
0
0
0
0
0
0
0
0
0
0
0
Word 2
Word 3
I
I,
"1
t '.
I
",
Scratchpad Ready 1.1lessages at'e generated by GCP to inform. the host computer that
data in the scratchpad for the alphanumeric keyboard is ready to be transferred.
GCE sends a.Scratchpad Ready message to the host computer whenever an alphanumeric
keyboard is operated in the scratchpad mode and the RETUEN k.ey is typed. GCE also
sends this message to the host computer when the scratchpad 1s full. Word 1
contains the character count indicating theo,umber of characters entered into the
scratchpad by the operatot'. Words 2 and 3 always contain all zeros. Normally, the
host computer 1."asponds ,lith a GI (give image) message to obain the qontents of the
scratchpad.
I.
I
I:
f
I
f
r
1:
I'
5-38
{.
FUNCTION KEYBOARD
(G8->H)
·...i
I
I
I
15
0
no. 1
.. Command header code (octal): 051113
no. 2
051114
I
14
13
I
12
11
10
987
6543210
o
ASCII R. CODE
ASCI! K CODE
Command Header
1
I
I
I
FUNCTION OR MATRIX KEY CODE I WQrd 1
I 0 0 0 0 I 00 0 0
1_"'"--_ _ _...
1 _ _ _....:.-.______________ 1
1...,
....,~
I
I
I
I
'
I 0 0 O. 0 I 0 0 0 I 0 0 0 I 0 0 0 0 0 0
I__~______....
I ______~1_______._1__--------------
Word 2
I'"~
d
i
I
i
~
..
~.
-
I
I 0 I
II
t
0
o
I
0 I 0
I
0
I
010
I
'
0
o
0
0
0
0
0
0
Word 3
Function Keyboard messages are associated With the·function or matrix keys on
the keyboard. Ifa function keyboard has been enabled (refer to host-eo-GRAPHIC 8
IK message), GCP sends a Function Keyboard message to the host computer each time a
key is typed. Each message contains the code for a single function or matrix key
(refer to Appendix A\. for a swnma.ry of codes). This code is contained in the low
order byte (bits 0... 7) of word 1. Words 2 and 3 always contain all zeros.
'_.,.j
5-39
5.3.6
POSITIONAL ENTRY DEVicE RELATED MESSAGES*.
related group consist of th~ following messages:
Host-to-GRAPHIC 8
The pOsitional entry device
tM
Assign data t,ablet as E'ED no. 1
nr
Assign data tablet as PED
IP
InitialiZe PED no. 1
IT
Initialize PEDna. 2
GS
Get status
-~'
o~
"'.,"
I.
,~~
no~·
2
E'EDs .,.
r
1'2
1
f ,";
,j
j~:
G1'
Give PED no. ,.1
GT
Give PED no. 2
aT
aeturn PED status
RP
Return PEP no. 1
aw
J.etu;r'll PlU)
:f
no.
2
The fo110w11'18 paragt'aphs discuss these messages and give de taUs concerning the
format and application of each.
I
I
I ".
t ~,
t'. .
I
•.
I'.'·:.:"
I".':
{
-.
f
I. ~'
*SeeSection 5.3.7 for tllessages for device numbers greater than 2.
Ii
1:
5-40
(
.
"
...
ASSIGN DATA TABLET AS PED
(H:->G8)
I
I
15
0
no. 1
Command header code (octal): 052115
no. 2
052116
14
I-
I
13
12
11
10
ASCII T CODE
9
8
7
6
5
4
3
2
1
0
ASCII M CODE
0
I
!
Command'Header
I--~I----------------~--~-----------------I
The Assign Data Tablet message is used to .inform GCP that all messages received
on ports 4 and 8 should be interpreted as data tablet type messages. By default GCP
is initialized to interpret all messages received on ports 4 and 8 as
trackball/forcestick type messages.
NOTE
Refer to Initialize PED message for more information on the data tablet message format.
1
I·
. .J
..
.)
5-41
INITIALIZE PED
(H-)G8)
ITII
rIPI
no. 1
Command header code (octal): 044520
-
no. 2
044524
I,tl
I
0
DELAY TIMe V!LUi
I
I
I
I
.t
I
I'
0
0
I
O·
I
0
0
If'
1
•
f
I
MEMORY ADDRESS (FOR MODE 0 AND 3 OPERA'UON)
0
I
.I
f:;\;
I
f '· ',
I
MODE
I
I Word 1
i
.I
I
"
I 0 I Word 2
I
I
The Initialhe Pil) message is a three-word message used ta establish the
aperating mode for the PEl) (trackball/forcestick or data tablet). Bits 1 and 0 of
word 1 sp,.c1fy the op. rat ing mode in binary form as follows: automatic tracking
mode (mode 0) ,. 00; automatic mode (mode 1) .. 01; request mode (mode 2)
10;
track1.11g mode (mode 3) .. 11. Bits 8 through 14 of word 1 select the delaytint;e When
mode 0 isseleeted. !'or al,l other modes, bitsS through 14 of word 1 are· set to
zeroes. All retnain1t18 bits in word 1 are always set to lEeros. Wben mode 0 or .3 is
specified, word 2 eonta~nsa memory address to be used for the sto1:'age of associated
data. the address should be that of an even-numbered byte_ If an odd address 1$
specified. the low-order bit is ignored by GCP and no XX (error status) message is
generated if an addressQf 0 is speeif1ed. the symbol is "detached'· from PEn action
and. furtherP:E:D interrupts are disable4..
0;11
Mode 0, 2 and 3 are applicable to data tablet type PlDs and modes 1 ~ 2, and 3
a::e applicable to trackball/forcestick type PEDa.
.
In the autom.atic tracking mode (mode 0), absolute displacement data received
from the data tablet is used to upl'late the memory address spec.ified .in word 2 each
timl! a data tab.let mes;sage is received, tQ refll!ct the last positioll of the data
tablet pl!a.entry. This updat11l8 is done by gl!lleraeing an t.DXA (load X absolute) and
an. MVYA (move Y absolute) instr1lct1Qn to replace the ones already in the refresh
file. Wbenmode 0 operatiQn fora PED is specified, word 2 of the IP or 11' message
from the host C011lputer contains the address of the LDXA instruction to be replaced.
The new MVYA instruction then replaces the old 1::NYA instruction at the next higher
adtlress.
I
t
. . i·~
.'.~
{,
f','.'
I,
I'
I ;"-.
-.
( ,\~:
The delay time' values in word ~ associated with mode 0 are given below:
:(.:
-
BIT
8
9
10
11
12
13
14,
DELAY TIME VALOE (seconds)
1/60
2,/60
4/60
8/60
16/60
32/60
64/60
(or
(or
(or
(or
(or
(or
(or
1/50)*
2/50)
4/50)
8/50)
16/50)
32/50)
64/50)
The delay time applies to all PED's in mode
a
on the same GRAPHIC 8 controller.
When the bit is set to 1, the \associated delay factor is activated.
bit is set to 0, a zero delay factor is associated with the bit.
When the
Each time the data tablet pen switch is pressed, the data tablet sends coordinate information to GCP at the rate of approximately 100 messages per second.
As each 1l1t!ssage is received, Gel? does a data tablet-eo-display coordinate system
conversion and updates the memory address specified in word 2..
As soon as the pen switch is released, the delay time mechanism is activated.
GCP then waits for whatever time the delay is set for and then sends a Return PED
message to the host to reflect the latest position of the last data tablet entry.
If the delay time :is set for 0 seconds, then each time a data tablet message is
received, a Return PED message is sent to the host computer. With a delay time of a
seconds, the host computer could be overloaded with a series of identical Return PED
messages. (E.g., if the data tablet pen switch remains pressed for 2. seconds, then
200 Return PED message~ would have to be processed by the host computer.) The
recommended delay time should be approximately 1/4 second.
,i.
i
,
"
,
Each time the data tablet pen switch is pressed, the delay time mechanism is
restarted. If the data tablet pen switch is re-pressed before the delay time
expires, then no Return PEn message is sent to the host computer until the new delay
time expires.
When the automatic tracking mode is selected for the PED, the Give PED message
must not be sent from the host computer to the GRAPHIC 8. If a message is sent to
th~ GRAPHIC 8 when the PED is operating in the automatic tracking mode, GCP responds
'by sending an XX message back to the host computer.
In the automatic mode (mode 1), relative displacement data received from the
trackball/forcestick is sent to the host computer in a Return PED message. This
message is sent each time the display processor is interrupted by the PED. When the
automatic mode is selected for the PED, the Give PED message must not be sent from
the host computer to the GRAPHIC 8. If a GP message is sent to the GRAPHIC 8 when
the PED is operating in the automatic mode, GCP responds by sending an XX message
back to the host computer.
,!
:.J
j
*
For 50 cps power frequency
5-43
"
-.'
I
In th~ request mode (mode 2), GCPmaintains the absolute coordinates of the PED
position i~terna11y.. Then, when a GPrnessage is sent by the host computer, GCP
returns th~; latest absolute position data to the host computer in an RP message.
" ute PED posi tion data and
In the tracking mode (mode 3), GCP maintains abaol
sends it teJ the host computer in the same man.ner as for mode 2 operation. In
addition, ~p continuously updates the refr.esh file to reflect the latest positio;n
of the PEDat all twes.; Mov_ants of the PED is indicated by generating an LDXA
(load X absolute) and an MVYA (move Y absolute) instruction to replace the ones
already in the ref:resb file. When modeS operation for the PED' is specified, wid :2
of the IP or I'l' message from the host c.omputer contains the address of the LPXA 7
instruction to be replaced. The ne.w MVY.~ instruction then replac.es the old MVYA
instruction at the next higher address.
o·
Note that relative position data is returned automatically to the host computer
in mode 1 operation while absolute position data is returned in mode 0, mode 2, and
mode 3 operation, but 01:11y upon request of the host message (GP or at).
When mode 3 operation for the PED is specified, word 2 of the initializePED
message ·(IF, IT, or IV) from the host computer contains the address of an LDXA or
LDDI instruction. !he LDXA is used to define (by user) a symbol or cursor in
refresh as follows :
•
II •
•
,
LPXA :it;
MVYA Yi
.
-.' .. " .. ,
specify x
and y position of symbol
gr<:lph:!.c orderi9 defining a symbol
cursor (e.g., CHAR < *
»
A LDDI graphic order is used to define (by the user) a hardwarecrosshair cursor
control :routine as follows:
LOPI
LDDI
LDOI
..... .
< XCRn,
< YCRn,
< STAn,
0
0
>
>
1040
2 words, opcode + XCRn data
)
2 words, opcode + YCRn data
2 words to enable crosshair cursor
'
NOn:
The ct'oss hair cursor can be dis.abled (removed
from the screen) by using the graphic cIrder:
LDDI
< STAn, 1000 >
The GCP input PEP handler (in mode 3 or 0) tests for the presenc.e of LDXA. or
LDDI (pointed to by wrd 2) and updates the X and Y position in refresh correc tly
for either c.ase • If the GCP input PED handler does n.ot recognize the LDXA or LPOI,
the X and Y POsitiOt1 in refresh file ienot updated.
II
t
I..
I,
.,
f
l
f
r
"
,,
.'
J
I
·f
Ii
f
{I
f ,.
I
I,
5-44
:,'j
I
(!
,,~..J
In summary:
Trackball
Forcestick
---Mode
Data Tablet
a
\ ..
.••..1
Update internal X~ Y position
and X, Y position in refresh file.
Return X, Y when pen is released.
Automatic mode (1)
Send relative X, Y
to host
Request mode (2)
Update internal
X, Y position only
Update internal X, Y position
Tracking mode (3)
Update internal
X, Y position and
X, Y position in
user refresh file.
Update internal X, Y position
and X, Y position in user
refresh file.
lesl
15
I
(H->G8)
14
I
I 0 I
I
I
13
GET STATUS OF PEDS
12
11
10
ASCII G CODE
9
8
Command header code (octal): 043523
7
6
o
5
4
3
2
1
o
ASCII S CODE
Command Header
The GS message is used to request the 'current status of each PED. An RT
message is sent by ~l' to the host computer in response to the GS message.
NOTE
The GS and RT messages are maintenance type
messages. Normally the GCF application programmer
won't process the GS and RT messages but they can
be used to validate the modes and PED types
established by the IF, IT, TM and TN messages.
"'r
5-45
(G8-·>H)
IRTI
15
I
I
I
0
14
RETURN
12
13
I
I
I
11
PED STATUS
9
10
8.
Coml1lJ3.nd header code (octal): 051124
1
I
I
ASCII R CODE
PED
7
5
':-r-6
0
4
2
3
0
1
i
!
I
ASCII T CODE
>
Command Header
.......
PED 1
2
~
0
0
0
0
0
MODE
0
TYPE
PED 6
I ..·.,.
I 0 ! MODE
I I
I
0
0
-
I
-
I
I
MODE
TYPE
0
-
r
I
a
0
0
0
0
MODE
TYPE
-
I
~
"'I
I Word 2
I
I
a
I
I
HODE
TYPE
I
I
t"
f
PED 7
I
I
I
-I
HObE
TYPE
PED 8
0
I
1
PED 3
PED 4
.
0
MODE
TYPE
0
'l"'lPE
0
I
MODE
I
0
I
PED 5
0
TYPE
-
0
0
I
I Word
I
I ,II'.,
Word 3
f
I
-
I
The RT message is sent by Gel' to the host computer in response to a GS message.
Word 1 cO'!'ltains the software status of each PED.
Bits 0, 1, and 2 are associated with PED 1 (PED connected to port 4 on serial
multiport interface 1). Bits 8, 9 and 10 are associated With PED 2 (PED connected.
to port 8 on serial multiport int"erface 2). ,The meaning o,f the TYPE and MODE bits
are given below:
-Bits
0 or 8 word 1
0 or 8 word 2
-Value
-I
-
I
>
1,2 or 9,10 rNord 1.-1
1~2
5-46
or 9,10 word 2
-I
>
Type PED
o
Trackball/forcestick
1
Data tablet
00
Automatic tracking mode (data tablet only)
01
Automatic mode
10
Request mode
11
Tracking mode
1
GIVE PED
(Hr-)G8)
IGPI
no. 1
Command header code (octal): 043520
IGTI
no. 2
043524
15
I
I
I
0
14
.1
I
I
13
12
11
10
ASCII G CODE
9
8
7
o
6
5
4
3
2
. ASCII P CODE
1
o
Command Header
The Give PED message is a single-word message used to request the current
absolute coordinate data for the PED (trackball/forcestick or data tablet).
Requested data is returned by GCP to the host computer using a Return PED message.
A Give PED message ~an be used only when the PED is operating in mode 2 (request
mode) or mode 3 (tracking mode). If this message is sent when the PED is . operating
in mode 0 (automatic tracking mode) or in mode 1 (automatic mode), GCl? responds with
an x.'{ (error status) message •
•
j
5-47
r
RETURN PED
(G8->l:l)
-
liP!
no. 1
Command header code (octal): 051120
1!R 1
no. 2
051127
I
I ',
i"
15
I
I
I
0
I
I
14
, 12
11
8
9
10
t .
I,
' r
0
I
0
'
f'
I 0
I
0
0
I
I
I
ASCII R CODE
I
I
I
I 0 I
I J
I
I
I
13
'" T
0
,
I a
I
7
,
0
6
{.
I
5
4
I
"
"
t '
0
I
I
I
.0.
1
0
I'
'
0
0
"
' l '.
i
r
MODE
0
. f
"
'
,
f
Y POSITION DATA
I"
, t.
'I
I Command. Header
I
I
0
,.
,I
"
",
!
X POSITION DATA
.
2
ASO!.I' P CODE
I'
, t ' , , "f'
3
I'
.
,
I
I
I Word 2
I
f
f
I
I Word
I
When the Pin :is operating in mode 1, GCP sends this message to the host
computer eV'ery time the PED generates an interrupt to the display proc.essor. PED
interruptS are enabled or inhibited by host.... to...G1tAPHIC 8 IK messages. In this tIlode,
words 2 and 3 conta:i.n relatiV'e X and Y position data, respectively, for the PEl)
(direction and distance moved since last RP message WaS sent). The relatiV'e data in
each word consists of eight bits in two's complement form nth the sign b:it (bit: 7)
extended to tUl the complete 16-bit word.
When the PEDh operating in mode 2 or mode 3, Gep sends Rfiturn PED messages to
the host computer in response to a GiV'E! PED message from the host computer, I'll
these modes, words 2 and :3 contain absolute X and Y pos:ition data for the PED. The
absolute data in each word cons:ists of 12 bUs in two's complement form with the
s:i.gn bit (b:it 11) extended to fill the complete 16-bil: word. Note that PED interrupts are not used to initiate RP messages in mode 2 or mode 3.
PEl) I S are automcftically enabled 'by GCP when the
GRAPHIC 8 is initialized in the system mode.
5-48
'~.,
3
the PED is operating in the request or tracking tl10de (modin 2 and 3, respectiV'ely)>>
these messages are seat in response to Give PED messages from the host computer.
The operating mode for PEDis established. by a corresponding Initialize PEl) 'message
frolll the host computer. For all Return PEI) messages, the operating mode of the PEl)
is :i.dentified by bits 1 and 0 of word 1 (00, 01, lOt and 11 indicate t!I.Odes 0, 1, 2,
and 3, respectively). B:its 2. through 15 of word 1 are always zeros. When the PED
is operat1ngin mode 0 (data tablet otlly) GCP sendSi a Return PED message to the host
computer every time the aata tablet pensw.:itc:h i,a pressed. III this mode words 2 and
3 conta.1nabsolute X. and Y position data, respectively, for the PEl).
-
f :')
I Word 1
I
The Return PED messages areassoc.1ated with the 1?ED (trackball/forcestick. or
data tablet). When t'he PEl) is operating in the auto1l1atic trackingt!l.Ode (mode 0) or
in the automaticllOde (mO,de 1) tthese Illes sages are $.ElInt automatically by GCP. When
NOTE
I",
-";' • .1
'( ,-':
.,.1
1',
.." i
r,
1:',
{.;,.,
l~
I, "
f:
J,
5.3.7 EXTENDED DEVICE CONTROL MESSAGE. The four Extended Device Control messages
extend the functions described in Sections 5.3.5 and 5.3.6 to eight peripheral
devices of 1;he same device type. I
HOST-to-GRAPHIC 8
U: - Enter Extended Device Control (EDC) mode
IV - Initialize a peripheral device
OU
~
Output or Request to Device
GRAPHIC 8-eo-HOST
IN - Input from device
: ... i
'1
\.
Refer to table 5"'2 for the device types and the corresponding functions. Refer
to the messages that the EDe mesu.ges functional replace for a cOUlplete description
o.f the function.
.
.J,
5-49
...-...:
r
Ii
t.;
Table 5-2. Gel' E:ttended Device Control*
(Functional Replacement)
..
DEVICE 'MESSAGE
I
TYPE
1
(OCTAL)
""
...... I
:::.:z-l
I
I Initialize
I Scratch pad
I en, ZT)
I
I
I
I
I Zero·
I
I Sera tch pad
I
I (ZS, ZU)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
•
I
I
I
fU1'1ctiolt
Light
I
I
I
I keys
I
I
·1 (IJ(, LT)
I
I
1
I
I
I
1
I
I Initialize
I iequest
I
I PSD
I Pos Uion data I
I (!P,IT)
I (Gl', GT)
I
I
I
I
I
I
I
I Ini tialize PED ' I iequest
I
I a.$ Ta.blet
I Pos1tioll data I
I (Il' t IT)+('I'M, TN) I (GP. GT)I
1
I
I
0
Alphanumeric
Keyboard
1
Fuact:icOn
Keyboard
2
Track'ball/
FOl'eestiek
:3
Tablet
15
14 13
I I
I 0 I
I
I .. /
I oI
I I
I
I
I
I
I
!
I ·OU'IPUT OR
I
I REQUEST DEVICE I
OT
I
I
I
I
INITIAlIZE
DEVICE
IV
1.2
II
10
I
.
9
8
IN (4 WORIlS)
,:,j
1
7
ASCII CODE
Q
DELAY TIME
MODE
5
6
4
3
2
. t
1
ASCII CODE
Mode .. 0,
ScratehpadReady
(Xli, XT)
Mode" .1,
Character data
(n,
lCT)
Function or
Matrix Kay Code
en;
RL)
-'I
"
1DEVICE
I
mE
DEVICE**
NUMBER
,'_..... J
I :.~
r
:~l
U
'{',.
...
,
X and. Yposition
data
(U, RW)
i
{
and Y pOSition
data
X
(RP , iW)
1
,
._'
r'
t: ~.
0
COOlma.nd Reader
.t.:'·
I
Word 1
DATA
Word 2
DATA
Word :3
"'Enter ltxtended Devies Control (EnC) mode via an IX message.
in system mode is in non EDC mode.
**Keyboard or PED is device no. n-l.
5-50
INP ur DEVI CE
...,
GCP initialization
I:
I
The format of words I, 2, and 3 for each device type and message are
below.
sho~m
IIVI -- Initialize Device Command Header (octal 44126)
•
Initialize Scratchpad
Word 1 - device type"" 0; device number"" 0-7
Word 2 - starting address of scratchpad in refresh file
Word 3 - number of characters in line in scratchpad
Initialize PED
Word 1 - delay time; mode = 1, 2, or 3; type = 2; number = 0-7
Word 2 - address of LDXA of PED symbol in refresh file if software symbol
- address of LDD! if hardware cursor
•
=
Word 1 - delay time; mode '"' 0, 2, or 3; type"" 3, number
0-7
Word 2 - address of LDXA of tablet symbol in refresh file if software
symbol
address of LDDI i f hardware curosr
r',
-
.-~
\
-
Initialize PED as data tablet
lOTI
•
Output or Request Device Command Header (octal 47524)
Zero Scratchpad
Word 1 - type
•
~
0; device number
= 0-7
tight Function Keys
Word 1 - type = 1; device number = 0-7
Word 2 - mask for function key lights
Word 3 - mask for matrix key lights
•
Request FED Position Data
Word 1 - Mode 2 or 3, type "" 2, number "" 0-7
Request Tablet Position Data
Word 1 - Mode 2 or 3, type
= 3,
number
= 0-7
IINI -- Input Device Command Header (octal 44516)
•
Scratchpad Ready
Word 1 - mode = 0; type = 0; number = 0-7
Word 2 ... number of characters in the scratchpad
Word 3 - 0
5-51
r"
Character Data
Word 1 ..., mode'" 1, type == 0; device number == 0-7
Word 2 ~ ASCII character code in bits 0-7
'(>lord 3 ... 0
Function or Matrix Key
D~ta
Word 1 - type" 1; -device number 0-7
Word 2 - Function key code in bits 0-7
Word 3
0
X and Y PEn Position Data
f
,I
I
t
L
f
-'
•.• J
Word 1 - mode'" 1, 2, <)r 3; ,type"" 2; number'" 0-7
Word 2 - X position coordinate
Word 3 - Y position coordinate
•
j{
and Y Tablet Position Data
Word 1 ... 1Jlode '"
e,
2, or 3; type .. 3; number" 0-7
Word 2 -. X position coordinate
Word 3 - Y position coordinate
{
t
.• --j
I
I
""1
r
(
I
II
I,
t:
I.·'
II
5-52
(
-
5.3.8 FORTRAN SlJPPORT (FSP) MESSAGES.
the following messages:
The Fortran support (FSP) group consists of
Hos t- t o-GRAPHI C 8
IG
Init~alize
GU
Graphic update
MI
Move image
NP
Enable box display
21'
Disable box display
NN
Enable error number
ZN
Disable error number
PV
Packed vector
GCP to support FSP
GRAPHIC 8-to-Host
RG
Return FSP table address
The following paragraphs discuss these messages and give details concerning the
format and application of each.
I
,-_J
5-53
.
~.1
I
1lE.1
(H-->G8)
INITIALIZE FSP
r
Command header code (octal): 044507
SUPPO~T
!
15
1--- I
I
I)
I
I
14
13 .. 12
"i'~-
11
10
..-9
g
ASCII I CODE
8
7
6
5
4
3
2
1
o
f
,.,
G
ASCII G CODE
Command Header
I~~~~-------------~--~--~------------------------------The IG lll,essage is used to initialize Gel" to operate in the Fortran support
program (FSP) env:i.ronment. ASSOCiated with this environment is a Sanders-developed
Fortran Graphic Support program,. This program is host resident and consists of a.
collection of Fortran callable subrou#ines. This program simplifies the task of
generating a graphic program by enabling the appl,ication programmer to write all
application programs in Fortran. The'task of fOrIllatting Gel" messages is performed
by the FSP.
The execution of the IG message results in a full screen box and an error code
being displayed on all d.isplay indicators. This gives the application programmer a
visual indicat10n that Gel' is nowopetating in an FS1' environment. In response to
the IG lUessage, Gel' sends G8)
15
I• I
I 0 I
I I
14
13
Command header code (octal) : 053120
DISABLE BOX DISPLAY
12
11
10
9
8
7
r
6
i
5
I
a I
I
ASCII Z CODE
X
X
X
i
I
X
X
X
X.
X.
2
3
I -
1
X
X
..
A
0
- I
ASCII P CODE
t
X
4
_u
Hi'DIeATOR
Command Header
t~ord
.
3 210
..............
--
1 000
Remove box from indicator 1
0 100
Remove box from indicator 2
o0
1 0
000 1
Remove box from indicator 3.
Remove box from indicat()r 4
If all bits are set to 1, then the box will be removed from all four
indicators.
r.'
,:1
I
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I '1
IJ
t
,
{
I
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r
r
l.
5-60
'"",
....
1
The Z2 message is used to disable the box display on selected indicators when
operating in the FSP environment. Bits 4 through 15 in word 1 are ignored by GCP.
Bits 0 through 3 specify which indicators the box should be removed from. These
bits are defined as follows.
BITS
f
r
f
I
(
',-
,,
I
.l"
!NN!
15
I
I
I
0
-~.
13
14
I
I
I
I I
I x'i
I I
.'
ENABLE ERROR 0lUMBER
(H->G8)
12
11
10
9
8
ASCII N CODE
7
Command header code (octal): 047116
6
4
5
3
2
1
ASCII N CODE
0
0
Command Header
I
X
X
X
X
X
X
X
X
X
X
I
I
X
INDICATOR
Word 1
The ~N message is used to enable the error number display on selected
indicators when operating in the FSP environment. These error numbers are updated
by FSP to give the user a visual indication that an error has occurred.
Bits 4
through 15 are ignored by GCP. Bits 0 through 3 specify which indicators the error
number should be displayed on. These bits are defined as follows:
BITS
~·r
I
111..2.
1 000
Display error number on indicator 1
0 1 0 0
Display error number on indicator 2
0 0 1 0
Display error number on indicator 3
aa
Display error nUlilber on indicator 4
t .•
0
1
If all bits are set to it then the error number is displayed on all four
indicators.
5-61
fIZ'NI
(H-)G8)
-
15
I
I
I
0
14
I
.
Command header code (octal): 055116'
DISA.BLE ERROR NUMBER
12
--
11
9
10
8
ASCII Z CODE
7
6
X
X
X
X
4
5*4,--
I
'U'
.'\0
G8)
14
I
I
I
13
12
11
10
9
8
Command header code (octal):
7
ASCII P CODE
0
BYTE COUNT ( B)
X
6
5
4
2
1
0
ASCII V CODE
I
1
3
X
I
X
I
I
I
X
X
X
050126
Command Header
Word 1
X
MODE
-
,
STARTING ADDRESS
Word 2
i
DATA BYTE 1
DATA
BYTE B-1
DATA BYTE 2
I Word 3
I
LAST DATA BYTE B
Word N
5-63
,;
__ .l
I
'-,
Bits 8 through 14 in word 1 contain the b~e count indicating the number (B) of
data bytes contained in the PV message. Bit 0 in word 1 selects th~ mode. Iraen bit
o is set to O. add mode is selected. For add mode, an RTRN, return instruction is
added to the end of the refresh code created from the data bytes contained in the PV
message.
When bit 0 is set: to 1, edit mode is selected. For edit mode, no return
instruction is added to refresh. Bits 1 through 7 in word 1 are ignored by GCP.
Word 2 contains the starting address of where the first LDXA instruction should be
stored.
NOTE
When word 1 and word 2 are sent from the host
computer to the GRAPHIC 8, they must be sent
according to the algorithm. de~cr1bed in paragraph
5.2.1 for serial transmission of binary words
(Le.,4 I(!harac tel'S for each binary word).
Words 3 through ncontain the data bytes for the
PV message. The format of the data bytes given
below:
BITS 15 nmOUGH 8
AND 7 THROUGH 0
x 001
x0 1 n
DESClUl'TION
1 1 1 1
CrlSate move instead of dra'(¥'
n n n n
HI 5 bits of it or Y value
it IOn n n n n
LO 5 bits of X val ue
Xllnnnnn
LO 5 'bits of Y value
Table 5-3 relates the number of bytes that change
at the host computer to the nt.1Illber o.f bytes
required for transmission to ge.nerate the appropriate LD.XA., MVYA, or DRYA instructions in the
refresh file.
(I
;1
)
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I
I
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,
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, I
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Byte 'lXansmission Requirements
Table 5-3.
,
I
I
BYTES ImleH CHANGE
I
0",
I
BnE TRANSMISSION REQ.
I
LO Y
HI X
LO X
II
HI Y
LO Y
HI X
La X
II
II
**
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
1
0
0
,-~
0
0
0
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
0
""
II
II
II
II
II
II
II
II
II
II
II
II
II
II
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
1
1
0
1
0
1
1
1
0
0
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
II
.J
,
.~
1ft OF
BYTES
SENT*
I
II
I
II
HI Y
I
o '"
no transmission
1= transit the byte containing that field
"
II
II
II
II
II
"
II
II
II
II
"
II
I!
II
"
"
II
II
!I
4
4
:3
:3
:3
3
2
2
:3
:3
2
2
3
:3
1
1
* 1 extra byte
** HI Y defzned
will be sent on a MOVE to set to move mode.
as bits 5-9 of user Y on a scale from 0 - 1023
La Y de·fined as bits 0-4 of USer Y on a scale from 0 - 1023
To change a HI X, y!?U must send at least one LO Y.
NOTE
The host coordinate syste~ is from 0,0 (lower
left) to 1023, 1023 (upper right) and the display
coordinate system is from -512, -512 (lower left)
to +511, +511 (upper right). GCP maps 0,0 into
-512, -512 and 1023, 1023 into +511, +511.
,.:.. .~
5-65
I
Below is a brief description of how thePV message functions:
1.
The normal case (also initial value is):
X01AAAAA XII131313BB
xorccccc XI0DDDDD
GCP compares each byte as sent
If same, do nothing until La x
DRY! commands wi th the 10 bits
since 4 bytes Were sent, all 4
all repl,;!.ced with new values.
'OIith old value (except on initial value).
value is sent, then create LOY. and MVY! or
of X and Y data. In the case shown above,
data values changed so old X, Y values are
BEFORE
(OLD VALUES)
BY Y
OOOlOOQ"J<
OOOAA.u.A
La Y
OOOLLLLI.
0001313131313
HI X
OOOMMHMM
OOONNNNN
OOOCCCCC
OOODDDnD
La
x
As soon as La X byte is
received, create LlJXA with
AIIB data and MVYA with
c/ /n data.
2.
The concatenated data (A//a or C/lD) is in the displayable range of the
screen (with values from 0 ....1023). The data is converted to screen
coordinates -512 to +511 before creati~ LPXA, HVYA, or DRY! instructions.
3.
After commands have been created, they ar~ added to the user refresh file.
GCP checks the 1110de specified in the PV message to see whether a re:turn
must be added in addition to the MOVE and DRAH' command sequence.
4.
A LO- X byte (bits 6 and 7 ... 10) initiates creation of graphic
instruc tiona.
5.
(
I
I
(
('
I
I
f.
Review table 5-3 for further clarificaUon of meaning of bytes sent. A 0
in the byte transmission col'l.lttln impU,es byte is not sent • (E."C. If only
the lower .5 bits of Y value change • the following bytes are sent LO Y and
I
La X).
[I'
I
(
(
I
(
5-66
f
NOTE
All data bytes are valid ASCII characters (i.e.,
range is between 037 and 177 in octal). When the
data bytes are transmitted from the host computer
to the GRAPHIC 8, there is no need to code these
bytes according to the algorithm previously
described for serial transmission of binary words
(Le., words 3 through n are transznitted directly
without any conversion performed at the host computer). PVmessages can also be used on parallel
interface systems but it is strongly recommended
that PV messages not be used on parallel systems.
No ASCII code conversion is required for parallel
transmissions and the use of PV messages on such
systems will probably re~ult in a decrease of
speed. For serial users who are using applications that require the generation of large amounts
of absolute moves and draws, the PV mode feature
can be very useful. The routines needed at the
host computer for PV mode are quite involved and
as such are not included in this manual. On
request, Sanders will provide additional information on the host routines needed to perform pack
vector mode functions.
j
5.3.9 OPTION SUPPORT. So ftware options allow the GRAPHIC 8 to e.."!:pand into a more
specialized system while maintaining a common firmware program (1 .e., Gel?). Gel?
includes a method for the user to load, test, initialize, and link several options
together to enhance system requirements. There are a variety of option types that
can be supported. Some general types of options are listed below:
1.
Sanders-developed softwar~ ~ support a present or future option (e.g.,
additional GeP messages to provide sophisticated 3-D coordinate converter
support at the GRAPHIC 8 end).
2.
Customer-developed software to meet a unique requirement (e.g., additional
Gel? messages to permit local editing of text at the GRAPHIC 8 end) •
3.
Sanders-developed control program (e.g., GET-2 emulator control program to
effectively replace the Gel' program).
. ,-
5-67
(
4.
Customer-developed control program (e.g •• a special control program that
effectively replaces the Gel? program).
Noxmally, the option softw,are is stored on the expansion module.
support the downloading of options from a host computer.
GCPa.lso can
NOTE
The opUonsupport provided by GC·p is quite
extens ive a.nd as sw:;:h is not included in this
ma.nual. R.eferto Sanders Publication H-79-03S7
for a detailed description of all option support.
This publication also contains information on
writing customer-developed options.
5.3.9.1
Opt:ion Messages.
The option group consist of thefo.llowing messages:
Host-to-GRAl?aIC 8
'Of _ _
IY
Initialize 2
GO
Give option status
au
Option upda.te (host downloading - described in option manual,
H-79-Q357)
RO
Return option
The follOwing paragraphs discuss these messages' and give details c.oncerningthe
format and application of each.
(
(
(
I
I
t
(
f.
I
f:
I
(
I
(
(
5-68
I
I
l'
.',.'
IIY!
14
15
13
I
I
I 0 I
I
I
I
I
I
INITIALIZE 2
(H->G8)
11
10
9
0
7
8
6
5
I
I 0
.. I
ASCII I CODE
0
0
12
Command header code (octal) : 044531
4
3
2
1
0
ASCII Y CODE
Command Header
12 BIT OPTION FIELD
0
Word 1
The initialize 2 message is a two word message that performs one of the
following actions:
(OCTAL)
OPTION FIELD
ACTION
o
Load all system automatic load options
4000
Unload a11 options
1 to 3777
Load specified option (if unloaded),
initialize option, and update option status
4001 to 7777
I~I
14
15
I
I
I
(
.
GIVE OPTION STATUS
(tI,->G8 )
13
12
11
10
I
0
o
I
I
A:SCII G CODE
o
o
o
9
8
Command header code (octal): 043517
7
o
6
5
4
3
2
1
o
ASCII 0 CODE
Command Head er
12 BIT OPTION FIELD
Word 1
The give option status message is a two word message which allows the host to
verify an option's status. One or two messages will be returned to the host as
specified below.
OPTION FIELD
ACTION
o
Return status of all options via RO, VL
Non-zero
Return status of specified
opt~on
via RO
Two styles of RO option messages are returned to the host in response to the GO
(give option) message: the single option status message and multiple option status
message.
t
;l
5-69
,
..
(
[
I Rq, I
R..1:!:TURN OPTION
(G8->H)
Command
code (octal): 051117
I
Single option status return.
14
15
I
I
13
I
!
I
0
12
11
10
9
8
7
6
5
2
:3
1
0
I
a
ASCII R CODE
4
J
I Command Header
I
ASCII 0 CODE
------------~-----------------------------------I
I Word 1
12 BIT OPT!ON ID
OPTION
I
--------------------------------------------~-----II
STATUS
OPTION INITIALIZATION ADDRESS
(
, Word 2
!
---------------------------------------------,
I Word :3
OPTION LAST ADDRESS + 2
------------------------------------------------,
I
.
(
1!9..1
Command
RETURN OPTION
(G&-)H)
header code (oc tal): 051117
Mul tiple opt1onstatus return.
14 ,13
15
I
!
I.
I
I
I
I
I
I
I
0
12
11
10
9
8
0
0
0
0
0
0
0
0
6
7
0
ASCII R CODE
a
5
I
I
I
4
a
ASCII
0
0
0
2
:3
a
1
f
0
I
I Command
I
I
I Word 1
I
CODE'
a
0
0
Header
"
NUMBER OF WORDS TO BE TRANSFERRED
I
I
I
I a
I
15
I
,
I
,
,
0
I Word 2
I
0
0
0
0
0
0
0
0
a
0
0
a
d
0
0
14
13
12
11
10
9
8
7
6
5
4
:3
...
1
0
I
!
I
ASCI! V CODE
0
I
I
,
Word :3
I
I Command Header
I
-,
I
I
I
[
I
,
Word 1
(
r
I
I
I
I
/
Word 2
OPTION ID
I
Word n
I
I
f
(
OPTION ID
STA'l't1S
/
I
I OPTION
I STATUS
"
ASCII L CODE
NUMBER OF WORDS TO BE TRANSFERRED
I
I
I OPTION
I
/
I
(
f
._,
o.
; i- ,
The number of words to be transmitted equal the option limit. A limit of zero
prevents any VL message being returned. The option ID is returned in bits 0 through
11 of words 2 through n. Option ID values of zero shall be interpreted to mean
that no option is loaded for that reserved area. The option status code is returned
in bits 12 through 15 words of 2 through n. The meaning associated with the option
status code are given in the following table:
•
(OCTAL)
BIT
12
15 14 13 ..........
--_
;\".?
r
'
0
0
0
0
Local detected option
,unloaded
0
0
0
1
Local checksum error
,unloaded
0
0
1
0
Local hardware not present ,unloaded
0
0
1
1
Local self test • NOGO
,unloaded
0
1
0
0
Local Self Test ,. GO
,loaded
0
1
0
1
Unfound option (for single RO message only)
-
:
.,
,~
,.'1'
0;., .....
oJ
...
~
'. J
1
.--<:..
5-71
5.4
PROGRAMMING THE 3-D COORDINATE COt-."VERTER
By using the register update (RU) and the give register (GR) commands, the
programmer may read and write all registers associated with the 3-D coordinate
converter.
'Ibis allows complete host control to perform such functions as:
$
Set matrix parameters
•
Set viewbox parameters
•
Set perspective parameters:
•
Set various control parameters
Depth cueing select
Scale select
Refresh
l~its
select
Source/destination of conversion process
Homogeneous/non-homogeneous select
2D /3D salee t
Perspective/no-perspective select
•
Start 3-D coordinate converter
•
Selectively establish the desired interrupt control
When 3-D interrupts are generated, an appropriate TS message is returned to the
host computer.
NOTE
Please refer to Sanders Publication H-79-0305 for
more information on the 3-D coordinate converter.
\.,",...,-
Its I
2-D/3-D COORDINATE CONVERTER STATUS
(G8-)H)
Command header code (octal): 052123
I
15
I
13
14
I a I
12
11
10
9
8
7
6
5
o
ASCII T CODE'
4
3
2
1
a
ASCII S CODE
Command Header
I--~I--------------------~-------------------
I
I
Word 1
STATUS
,----------------------------------------------CPC
B
o
B
o
o
a
o
a
Word 2
a
a
a
,0
a
a
o
-,o I
word 3
-------------~-----------------------------------I
The 2-0/3~0 coordinate converter can generate 16 interrupt conditions. provided
that the corresponding mask bits are enabled. The TS message is returned 'to the
host computer when a 3D coordinate converter interrupt condition occurs.
Word 1 contains the contents of the 2-0/3-0 coordinate converter status
register. Each bit in this register corresponds to an interrupt condition. One or
more of these bits sets to indicate the type of interrupt condition detected.
Word 2 is the value of 2-D/3-0 coordinate converter program counter.
Word 3 contains two bits of the 2-D/3-D coordinate converter block register
corresponding to the bank in which the coordinate converter was executing at the
time of the interrupt condition. Bits 14 and 15 are defined as followed:
Bits
15 14
-'
-0 a
a 1
1 a
1
1
Bank Number
0
1
2
3
5-73/5-74
,.,
[
..
._. ...,
I :'
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(
• ~:. :J
(1
( -J
I :J
~1
(
,"~J
[ :l
',_ i
,.-';
[
.
-:
I' ..
(
(
(
(
.
.
'~'
..
,
"
I
I:
--
....
r:1
{<
SECTION 6
GRAPHIC CONTROL PROGRAM USAGE
6.1
GENERAL
This section contains information concerning basic usage of the Graphic Contrdl
Program (GCP). Included are startup procedures) procedures for generating and
manipulating .a refresh file, and information for using optional GRAPHIC 8 equipment.
6.2
ST.~TUP
PROCEDURES
Startup procedures consist of initializing the GRAPHIC 8 in the system mode and
ensuring that an XX (error status) message indicating zero errors is sent by GCP to
the host cOmputer. In certain cases, these operations are performed automatically.
In other cases, action must be initiated by the host computer. The following
paragraphs describe startup procedures for typical operating conditions.
6.2.1 GRAPHIC 8 TURNED ON AFTER HOST COMPUTER. When power is applied to the
GRAPHIC 8 it is automatically initialized in the system mode and an XX message is
sent to the host computer. If the host computer application program is running at
the time and no errors are indicated by the XX message (bit 15 should be one and
bits 0 through 14 should be zeros), no further action is required and startup is
cOll1ple teo
NOTE
On systems that do not have a 3-D coordinate
converter option installed, bit 4 of the XX
message is set to 1 to indicate failure of the 3-D
self-test.
6.2.2 GRAPHIC 8 TURNED ON BEFORE HOST COMPUTER. If the GRAPHIC 8 is turned on
before the host computet, any XX message sent to the host computer is lost. In this
case, action must be initiated by the host computer to obtain another XX message
from the GRAPHIC 8. This is done by sending an 1Z (initialize) message to the
GRAPHIC 8 which causes GCP to return an initialization XX message to the host
c.omputer.
6.2.3 POWER FAILURE STARTUP. To ensure proper startup following power failure, i t
should be a~umed that the power failure affected both the GRAPHIC 8 and the host
c.omputer and that power is first restored to the GRAPHIC 8. This condition is
similar to that described in paragraph 6.2.2 in that the XX message automatica.lly
generated by the GRAPHIC 8 is lost. To ensure proper startup, therefore, the power
recovery routine in the host computer should 'cause an IZ messa.ge to be sent to the
GRAPHIC 8 causing GCP to respond by sending an initialization ~~ message to the host
computer. In this way, an initialization XX message is guaranteed to be received by
the hast computer regardless of the order in which power is restored to the various
equipments.
6-1
(:
6.2.4 STARTUP WITH GRAPHIC 8 r~ TELETYPEWRITER EMULATION MODE. A special startup
procedure is required when the de1etypewriter emulation capability of the GRAPHIC 8
is used for communications with the host computer. This capability is used when the
host computer is a time-sharin.gjsystem or when loading and running the host
application program must be accomplished from a conso1e... tY1'e device. Refer to
Section 2 for the procedure used.i to estal:!lish the teletY1'ewritar emulation Illode.
1
(
"
I
-l
[
When all proced.ures requ1ri,n.g the teletypewriter emulation capability have been
completed, the host computer shouldinit::i.ate the startup procedure by send;ing the
single ASCII character as (group, separator; octal code 035) to the GRAPHIC"S. This
character causes the aWHre 8 to exit from the teletypewriter emulation mode and
respond as if an IZ message had been sent from the host computer (an 1,Z message
would not be recognized when the\ GRAl?HIC 8 is in the teletypewriter emulation mode).
The reSUlting initiali,aiton XX;raessage to the host computer thencotltl'letesthe
startu.p p r o c e d u r e . '
E:d. t frOln the t;e1etY.peWl':I. ter ell1uladon 1]1od$,
in.iUali,ation in the system lIlo(ie J and .sending of
the XX message can also be accomplished by typing
function key 113 (this causes octal code 035 to be
geullll:'at.ed.h However, 1:1\1.8 operation would not be
synchronized w:1.th !:1.omal host cOll1pllter operations
and.lQ1ght res\;l.lt in anill1proper startup sequence.
6.3 UFRESH F!LES
.
.
The follOWing paragt'aphsdeset"ibe the gener.ation, transmission, and alteration
of refresh files to be processed by the digital graphic controller. Table 6... 1 is an
example of a simple ·t'eiresh file that is used to illustrate various parts of the
discussions. 'Figure 6-1 shoW'S the display that .t'es\;l.lts .when the refresh file in
table 6-1 is processed.
6.3.1 WUSR f'ta GlNERATION. After startup proced.ures have been completed, the
host contputer applieation program must generate a refresh file to send to the
GRAl'HIC 8 so that the desired image can be displayed. The refresh file may be
included in the appl:!.cat10n program itself or _y be generated dyna.mically by the
application progrp.
Table 6-1 is the liI!Jting for a simple refresh file that could be genet"ated for
display by the GRAPIUC 8. The. first part of the file (before the la.bel RLOOl?)
initializes param$tersas required to ensure th.e proper intetpretation of the
instructiot'l$ that follQw.
FollOwing the WA'!E instrU.ction is the seque.nce of instructions USed to displa.y
the t",oIO large sql,Ulres and the four vectors that intersect in the center of the
screen. The neltt instNctionsestabli.sh a seratchpadarea by inset-ting ten spaces
following the word "INPUT:" at the lOwer left of the screen. Note that the size and
spacing of these characters was established by th$ 1nitial.1zation instructions at
the beginning of the listing. The actual scratchpad is definQd by the memory
locations in which the spaceS are located ..
6-2
I
i
,~.o.- j
NOTE
1
.F'1.
(
(:
lNt'Vf
GA· 77·419·07
Figure 6-1.
Display Created by Sample Refresh File No. 1
6-3
(:
Table 6-1.
00100
00200
00300
00400
00500
00600
00700
00800
00900
01000
01100
01200
01300
01400
01500
01600
01700
01800
01900
02000
02100
02200
02300
02400
02500
02600
02700
02800
02900
Fil~
No.1
003000 013701
003002 014010
003004 140114
lLOOP:
003006
003006 005000
00:3010 0200.00
003012 '. 060000 .
003014 007000
[
('
SET DISPLAY PARAMETERS
LDDZ
LDDP
LDT! 14
NOOP
LDXA 0
MVYA 0
; CEN'1'ER AT 0, 0
WA'l'E
DRAW DIAGONALS
003016
003020
003022
003024
003026
003030
003032
003034
003036
003040
19030,42
003044
020777
060771
023000
043000
050777
023000
040777
050000
04.3000
020777
060000
033000
•
003046 063000
03100 003050 030777
03200 003052 040777
03300 003054 033.000
03400 003056 043000
03500
03600
03700
03800 003060 023076
03900 003062 063076
04000 003064 04S6D4
04100 003066 035604
042.00 003010 046174
04300 003072 036114
04400
04500
04700 003074 023200
04800 003076 063HO
04900 003100 147311
05000 003102 152720
05100 003104 135324
03000
Sample Refresh
tDU 177
LDXA -1000
;MOVE TO
; UPPER RIGHT
;DRAW DIAGONAL
DRYA -1000
; TO LOW! LEFT
MVY! 777
MVXA 177
LDX! "'1000
DRYA 771
MV~ 0
ORtA -1000
LJ)XA. 777
MVYA 0
DRXA ....1000
;MOVE TO LOWER RIGHT
;DUW DIAGONAL·
; 1'0 OPPERLE1T
jMOVE TO TOP CE.N'tER
;DRAW STRAIGHT DOWN
;.MOVETO FAR
; 1U011'1' CENTER
;DRAW HORIZONTAL TO LEFT-
;
; DRAW INS!D! SQUARE
.
MVYA -1000
DRU 777
. DRY! 177
DRXA
-1000
DRYA -1000
MVYA -702
DRn. 1604
DRn. 1604
DRU.-1604
DiXR ";1604
SCRATCHP!]) PROMPTER
LDXA ...600
MVYA -670
T::cr' I,N
Tn 1',0"
Tl'l' T,:
I.
( ,'"
;MOVE TO BOTTOM LEFT
jDRAW STRAIGHT UP
jDRAW TOP EDG! TO RIGHT
; DRAW RIGHT EDGE DOWN
; DMW BOTTOM EDGE TO LEFT
DRAW INNER SQUAlU!:
LDX! -702
( I'
I
( .,
jSET INSIDE !>OINT
; AT LOWER UF'!'
;DltAW STRAIGM' UP
;DRAW TOP EDGE TO RIGHT
;DRAW STRAIGHT DOWN
BOTTOM EDGE TO LEFT
;DR.~W
04600
;
jPOSITtON INSIDE INNER
; SQUARE AT LOWER LEFT
; INSERT I INPUT: I
t
I
Table 6-1..;; Sample.Refresh File ,No. 1 (Cone)
.
~~-
.,.,.'
"
-
05200
05300
05400
05500
05600
05700
05800
05900
06000
06100
'06200
06300
06400
06500
06600
06700
06800
06900
07000
,.
'~:'
; SCRATCHPAD
;
003106
003106
003110
003112
003114
003116
SCRPD:
:;
120240
120240
~.
.
120240
120240
120240
TXT
TXT
TXT
TXT
TXT
< >,<
< >,<
< >,<
< >,<
< >,<
>
>
>
>
>
; TEN
SPACES
FOR
SCRATCHPAD
AREA
FED CONTROLLED MOVING CIRCLE·
;
003120
003120
003122
003124
003126
003130
003132
020000
060000
073020
077020
001000
002006
MCR'CU:
".'
MVYAO
CONTROLLED
.,; PEDPOSITION
OF
LDKX 3,20
DRKY 3,20
.,
LDXA 0
JUMP RLOOP.
SMALL
CIRCLE
; REPEAT
.'
•
,
.-.,,.
~
,- -;
6-5
[,
[
The four !nstructions following the sc.ratchpad instructions define the small
circ.le tha t is ;ldr awn a t the center of the dis play. Thi s circle is used to
illustrate PEDIoperation. Note that, if a conic generator card is not installed in
the terminal con troller, a small squa:re is drawn in place ()f the small circle.
<
(
,,'
~he
Finally,
refresh file is te~tnated with a JUMP instruction. The JUMP
instruction causes the digieal graphic. controller to loop back to the point in the
file labeled RLOOP and reprocess the entire file except for the parameter
initialization instructions.
I
('C
-.~,
Thus table 6-1 represents a ccmplete refresh file that can be processed by the
digital graphic controller. The listing specifies that 46 words are required and
that they are to be loade~ into read/write memo:-y beginning at octal locatio~ 3000
and endi11g at octal locatl.on 3132. Figure 6-1 l.llustrates the display that :'is
created TN'hen this refresh file is processed by the digital graphic controller.
6.3.2 UFRESH FILE TRANSMISSION. After a refresh fUe has been generated, it lUust
be transmitted trom the host computer to the GRAPHIC 8 using a GCP message.
Following transmission of the fUe, another Gel? message must be sent to the host
computer to start processing of the file. For the example refresh file shown in
table 6-1, the following sequence of Gel' messages would be used (it is assumed that
an 1Z message from the host compllter has prevJ.oosly been sent to initialize the
GRAPHIC 8):
Host-to-GRAPHIC 8 MU (memory update) message:
I
046525 - MU command header
003000 - load address for first data word
000056 - number of data words to be loaded
I
(
.
1
(
(,
(:
.I
(I
013007 - first data word to be loaded
014010
second data word to be loaded
(
(
002006 - last data word to be loaded
b.
Host-to-G'R,APH1C 8 SF (start picture) message:
051520 - SF ccmmand header
002000
.~ter
starting address of refresh file
this message is sent, a display similar to that illustrated in figure 6-1
appears on 'display indica tor no. 1.
,
I
I
f,
f
(
6-6
Change 1
,
"
..
NOTE
For purposes of development or debugging, refresh
files may also be loaded into read/write memory
manually or from paper tape. These methods employ
local mode commands for the GRAPHIC 8 as ~escribed
in Section 2.
,
I
.'
'.
6.3.3 REFRESH FILE ALTERAtION. After a refresh file has been loaded into
read/write memory, i t can be altered by the application program of the host computer
using various GCP messages. Suppose for example, it is desired that the word
"READY" be displayed in the scratchpad area for a specific period of time, after
which spaces will be. reinserted into the display. This can be accomplished by using
GCP messages as follows:
a.
Host-to-GRAPRIC 8 IS (enabled selec.ted interrupts) message:
044523 - IS command header
000002 - enable halt interrupt
This message enables the digital graphic controller to interrupt the display
processor whenever the digital graphic. controller executes a HALT instruction.
b.
Host-to-GRAPHIc 8 SU (selective update) message:
051525 - SU command header
002100
load address (beginning of scratchpad)
000004 - number of da ta words to be loaded
142722 - first data word (text "RE")
142301 - second data word (text "AD").
120331 - third data word (text "Y")
000000 - fourth data word (HREF)
After the refresh file has been altered in accordance with this message,
"READY" is displayed in the scratchpad area each time the file is processed. After
displaying "READY", the digital graphic controller halts and interrupts the display
processor. This causes GCP to send a HI massage to the host computer.
c.
GRAPHIC 8-to-host HI (halt interrupt) message:
•
044111 - HI command header
002116 - contents of graphic controller program counter
120240 - contents of graphic controller instruction register
000000 - filler
6-7
•
(:
This message is sent to the host computer each time the HREF instruction is
executed by the g-.caphic con troller.
d.
l'
('
Host-to-GRAPH,IC 8 KP (continue picture) message.:
045520 - KP command header
"!
Each time an HI message isrecei''1ed from the GRAPHIC 8, the host computer must
respond with a KP message to restart the graphic controller.
e.
f
Host-to-GRAPIUC 8 MU (memory update) messages:
046525 - MU command header
(
002100 - load address (beginning of scratchpad)
000004 '''!lumber of data words to be loaded
120240 - fil'st data ftlol;'d (text"
120240 - second data word (text"
120240 ... third da'ta word (text"
120240 - fourth data word (text"
I
")
(
")
")
I:
Of)
This message. is sent after "1\E,ADY" has been diSPlayed in the scratchpad area
for the desired period of time. Altering the refr1:ash file in accordance with this
message restores the file to its original content and fotmat.
f.
I~
I
[
Host-to-GR.APHIC 8 KP (continue picture) message:
045520 - KP conmand header
Following restoration of the refresh file to its original content,
computer should send a KP message to the GRAPHIC 8.
6. 4
t~he
has t
(
OPTIONAl. EQUIP]ENT USAGE
Optional GRA!'HIC 8
equip~nt
automatically enabled. Follo\ldng initialization, these devices a.re enabled and
di sabled as :t'eq ui red by IK (interrupt control) messages from the has t computer to
the GRAPHIC 8. The hard copy unit is controlled only by pressing the start button
on the hardcopy uni t. The following paragraphs provide examples of how to control
each... type of optional equip~nt (unless otherwise stated, the examples are assumed
to refer to alphanumeric keyboard no. 1, and PE.D no. 1, in non-EDC mode).
6.4.1 'KEYBOARDS. After a keyboard has been enabed, Gep sends each character to the
host computer in a KY (alphanumeric keyboard no. 1) message. for the refresh file
listed in table 6-1, this feature might be used by the host computer to collect
characters for the scratchpad a.rea on an individual basis. The host c.omputer could
then use SU (selective update) messages to echo each c.haracter as i t is typed by the
operator.
Change 1
"
includes keyboards, PEDs, and a hard copy unit.
At the time the GRAPHIC 8 is initialized ill the system mode, keyboards and PEDs are
6-8
I
f
I
Li
f:
Ii
I,
,
"'1\
Such operations have the advantage that the host computer can maintain complete
control over what is displayed in the scratchpad area and can perform any editing or
character conversion routines that may be required (e.g., lower case to upper case).
For simple applications, however, the scratchpad feature available in GCP can be
used to relieve the host computer of many processing tasks. For example, assume
that the scratch pad feature is to be used for the scratchpad area defined in the
table 6-1 refresh file. The scratchpad mode of operation would be established by
the following host-co-GRAPHIC 8 ZR (initialize scratchpad for alphanumeric keyboard
no. 1) message:
055122 - ZR command header
002100 - starting address (first address of scratchpad)
000012 - number of characters in line (ten)
Once this message has been received by the GRAPHIC 8, GCP enables the keyboard
and enters the scratchpad 1llOde of processing keyboard inputs. The host computer is
then free to proceed to other tasks as necessary while GCP collects keyboard inputs
in the scratchpad area. GCP collects characters in the scratc.hpad area and echos
them on the display completely independent of any operations being performed by the
host computer. The RUB OUT key can also be used, if req'uired, to delete any
erroneous entries that may be made. When the operator is through typing characters
into the scratchpad, he types RETURN at which time communications are reestablished
with the host computer by means of the following GRAPHIC 8-to-host XR (scratchpad
ready for alphanumeric keyboard no. 1) message:
;1
054122 - XR command header
XXXXXX - number of characters in the scratchpad
000000 - filler
000000
filler
After receiving the XR message, the host computer responds with the following
host-to-GRAPHIC 8 message:
043511 - GI command header
002100
starting address (first address of scratchpad)
000005 - number of words requested
The GI message would, in turn, cause GCP to respond with the following two
messages to the host computer:
6-9
..
For large sc.ratchpad sizes, the number of integer
words requested for the G1 message could be
calculated as follows!
I
I
number of words = (nUIllber of characters in the
sc,-ra tchpad +1) /2
r
NOTE
.
a.
GRAPHIC 8-co-hostRI (return image) message:
051111 - RI c.ommand header
002100 - starting address (first address··of sCl;'atchpad)
I
f
000005 - number of words to be transferred
000000 - filler
b.
G.'RAPKIC 8-to-host VL (varia.ble length) message:
053114 - VI. command header
OOOOOS - number of words to be transferred
147723 - first
~ta
wo"rd (teXt "SO")
140640 - second data "lord (text " A")
120315 ... third data word (text "M ")
120311 - fourth data wQrd (text "I ")
120240 - fifth data word (tex'I:"
")
This message indicates that the operator typed "SO AM I" into the
scratchpad and then typed RETURN.
After the requested data has been returned to the host computer in a VL
message, the host computer sands the following message to theGRA.PHIC 8 to clear the
scratc.hpad area:
Host-eo-GRAPHIC 8 ZS message:
055123 - ZS command header
/I
This message Causes GCP to space £ill the whole scratc.hpad area and
reposition the sc.ratchpad pointer to the beginning of the scratchpad
area.
6.4.2 PEDs. There are four modes of operation that can be established for PEDs.
These are the automatic track (mode 0)) the automatic. mode (mode 1), the request
mode (mode 2), and the tracking mode (mode 3). The desired operating mode is
established by a host-eo-GRAPHIC 8 11.' (initialize PED no. 1) message, a detailed
discussion of r,.rhic.h is contained in paragraph 5.3.6. In the £ollowi ng paragraphs,
6-10
II
f
I
I
I
I
I
the small circle in figure 6-1 is used as an example of
element.
.j
)
PED-controlled display
Mode 0 is applicable only to data tablet type PEDs and is not discussed in this
example. Mode 1 is applicable only to trackball/forcestick type PEDs. Modes 2 and
3 are applicable to all types of PEDs. Uses of modes 1,i 2, and 3 are described in
the following paragraphs.
wnen mode 1 is used, RP (return PED no. 1) messages are sent automatically from
the GRAPHIC 8 to the host computer to indicate changes in the relative position of
the PED. The host computer then processes this data and, whenever required by the
application program, sends an SU (selective update) message to update the
instructions that define the center of the circle (these are the LDXA and MVYA
instructions at addresses 2120 and 2122 respectively).
:
,
",
When mode 2 is used, absolute PED position coordinates are maintained at all
times by GCP but the refresh file is not altered and the cia ta is not sent to the
host computer. In this mode, if the host c.omputer application desires to know the
position of the PED, a GP (give PED no. 1) message must be sent to the GRAPHIC 8.
GCP responds by returning the latest absolute PED position data to the host computer
in an RP (return PED no. 1) message. If desired, the host computer can then send
the data back to the GRAPHIC 8 in an SU message to update the instructions that
define the center of the circle.
"
When mode 3 is used, the position of the circle can be controlled by
manipulating the PED completely independently of the host computer. This mode would
be established for the circle by the follOWing hosc-to-GRAPHIC 8 IP message:
044520 - IP command header
000003
establish PED operating mode 3
002120 - address of LDXA instruction (that defines circle center)
After mode 3 operation has been established for the PED, GCP automatically
updates the instructions in the ref~esh file that qefine the center of the circle
and the circle follows PED motions without any further action on the part of the
host computer.
NOTE
Whenever an IP message is sent from the host
computer to the GRAPHIC 8, GCP automatically
enables the interrupt associated with the PED.
6.5
MULTISTATION USAGE
In the discussions in paragraphs 6.3 and 6.4, it Was assumed that identical
images were desired on any display monitor or hard copy unit that might be enabled.
It is possible, however, to send different images to eac.h display indicator if
required. The images may have elements in common or may be entirely different.
6-11
I
Table 6-2 is a listing for a refresh file that causes an image similar to that
shown in figure 6-1 to appear on each of two display monitor (no. 1 and 2 are
assumed for purposes of illustration). This re£-r:esh file causes the squares and the
intersecting vectors to be drawn simultaneously on both displays. Then, only
display monitor no. 1 is enabled while "INPUT:" is drawn, the scratchpad for
keyboard no. 1 is initial~zed, and the circle for PED no. 1" is drawn. Finally, only
display monitor no. 2 is enabled while the corresponding elements are drawn for its
display.
At this point, the images on both display monitors should appear to be
identical. The scratchpad, and circle of each display, however, can be controlled
separately by the associated peripheral devices. Ii: is only necessary for the host
c.omputer application program to rec.ognize the disc.rete inter1:Upts caused by eac.h
peripheral deVice. Messages similar to those discussed in paragraph 6.4 would be
used by GCP and the host computer but data for each display indicator would be
transmitted itl separate messages. Thus it would be po.ssible for the c.ircle to
appear in different positions on each display and for different text to appear in
each scratchpad area.
[
I
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. '1
-~
:-::1
•( I
r
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1'1
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II
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•
<-
Table 6-2.
""'1"......
rr;-'-
·
~
......
~
' .J
'"
i
J~''''
:
.,
,
~,
1f
.,J
r.~
1
I.-.. j "
J
--'
.~
.. ".
•
>
~j
I
00100
00200
00300
00400
00500
00600
00700
00800
00900
01000
01100
01200
01300
01400
01500
01600
01700
01800
01900
02000
02100
02200
02300
02400
02500
02600
02700
02800
02900
03000
03100
03200
03300
03400
03500
03600
03100
03800
03900
04000
04100
04200
04300
04400
04500
04600
04700
04800
04900
05000
05100
05200
Sample Refresh File No. 2
SET DISPLAY PARAMETERS
003000
00:j002
003004
003004
003006
003010
003012
003014
LDDP
LDTI 14
014010
140114
RLOOP:
005000
013407
020000
060000
007000
NOOP
LDDZ
;CENTER AT 0,0
LDX! 0
MVYA 0
WATE
DRAW DIAGONALS
003016
003020
003022
003024
003026
003030
003032
003034
003036
003040
003042
003044
020777
060777
023000
043000
050777
023000
040777
050000
043000
020777
060000
033000
lOX!
MVYA
LDX!
DRYA
MVXA
LOXA
DRYA
MVXA
DRYA
LDXA
MVYA
DRXA
777
177
-1000
-1000
777
-1000
717
0
-1000
777
0
-1000
.
jMOVE TO
; UPPER RIGHT
;DRAW DIAGONAL
; TO LOWER LEFT
;MOVE TO LOWER RIGHT
; DRAW DIAGONAL
; TO UPPER LEFT
;MOVE TO TOP CENTER
;DRAW STRAIGHT DOWN
;MOVE TO FAR
; RIGHT CENTER
;DRAW HORIZONTAL TO LEFT
DRAW INSIDE SQUARE
003046
0030S0
003052
003054
003056
063000
030777
040777
033000
043000
MVYA
DRXA
DRYA
DiX!
DRtA
-1000
777
777
-1000
-1000
iMOVE
;DRAW
;DRAW
; DRAW
; DRAW
To BOTT~~ LEFT
STRAIGHT UP
TpP EDGE TO RIGHT
RIGRT EDGE DOWN
B01'T(ltf lDGE TO. LEFT
DRAW INNER SQUARE
003060
003062
003064
003066
003010
003072
023076
063076
045604
035604
046174
036174
LDX!.
MVYA
DRn.
DRXR
DRYR
DRXR
-702
-702
1604
1604
-1604
-1604
;SET INSIDE POINT
; AT LOWER LEFT
jDRAW STRAIGHT UP
;DRAW TOP EDGE TO RIGHT
;DRAW STRAIGHT DOWN
;DRAW BOTTOM EDGE TO LEFT
SCRATCHPAD PROMPl'ER III
003074
003076
003100
003102
003104
003106
013007
023200
063110
147311
152720
135324
LDDZ
lOX!. -600
MVYA -670
TXT I,N
TXT P, U
TXT T.:
; SELECT DISPLAY "1
jPOSITION INSIDE INNER
; SQUARE AT LOWER LEFT
; INSERT 'INPUT: t
, '1~
...,
j
_~:l
6-13
Table 6-2.
f
Ii (
Sample Refresh File No. Z (Cant)
05300
.." 1
~
05500
05600
05700
05800
003110
003110
003112
05900
003114
06000
06100
06200
06300
06400
06500
06600
06700
06800
06900
07000
07100
07200
003116
003120
07300
003132
003134
003136
003140
003142
003144
07400
07500
07600
07700
07800
07900
08000
08100
08200
08300
08400
08500
08600
08700
08800
08900
09000
09100
09200
09300
09400
09500
09600
09700
[I ,t
SCRATCHPAD FOR DISPLAY til
05400
;
SCRPD1:
TXT < >,< >
l"XT < >,< >
TXT < >,< >
TXT < >~< >
TXT < >,< >
120240
120240
120240
120240
1:20240
..
; TEN
SPACES
FOR
SCRATCRPAD
AREA
II
-:':1
(
!
.•.. J
MOVING CIRCLE IH
003122
003122
003124
003126
003130
MCRCL1:
MVYA
0
LDl{,,'{ 3, 20
DRKY 3,20
.., SCRATOOAD
MVYA -670
TXT I,N
TXT F,U
jSELECT DISPLAY #2
;POSITION INSIDE INNER
; SQUARE AT LOWER LEFT
; INSERT I INPUT: I
TXT T,:
SCRATCHPAD FOR DISPLAY 112
SCRPD2:
120240
120240
120240
12.0240
.120240
TXT < >,<
TXl' < >,<
TXT < >,<
TX'l"< >,<
TXT < ),<
>
>
>
)
>
; TEN
SPACES
FOR
SCR.ATCHP AD
AREA
PED CONTROLLED MOVING CIRCLE 1F2
003160
003160
003162
003164
003166
003170
003172
;
aCRCL2:
020000
060000
073020
077020
001000
002004
LDU 0
MVYAO
LDKX 3,20
DRKY 3)20
JUMP RLOOP
L'
,,
,,;\
f
i
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(
PROMPTER IF2
LDDZ
LDXA -600
012407
023200
063110
147311
152720
135324
.,
003146
003146
003150
003152
003154
003156
; PED CONTROLLED
POSITION OF
SMALL
CIRCLE
LPXA 0
020000
060000
073020
077020
;PED CONTROLLED
; POSITION OF
SMALL
CIRCLE
;
; REPEAT.
,.
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"
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II
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(
6-14
I
It is also possible for a refresh file to contain entirely different }images for
each display monitor. Normally, such a file would contain a main program:loop that
calls t~.;o subroutines, each subroutine being the instructions associated wi th a
particular display monitor. The following is an example of how such a refresh f He
might be structured:
MAIN:
WATE
; SWAP PIXEL MEMORIES
CALL RFRSl
; DRAW DfAGE' ON DISPLAY MONITOR NO. 1
CALL RFRS2
;DRAW DfAGE ON DISPLAY MONITOR NO. 2
JUMP MAIN
;LOOP BACK TO BEGINNING
.0
RFRS1:
LDDZ
LDDP
; S"ELECT DISPLAY MONITOR NO. 2
'):,
AND ESTABLISH:
DESIRED P.l\.RAMETERS
LDTI nn
;~NSTRUCTIONS
; , FOR
..
I
I
I
I
,'~"
DRAWING
I~GE
ON
DISPLAY
MONITOR NO. 2
RTRN
; RETU'Rl.'i TO HAIN LOO P
NO'rE
In the example presented, SOlUe a4dil:ion;11 software
considerations should be taken into account if it
is desired to generate hard copies of each display
presentation. The LDDZ instruction performs
several functions in addition to enabling each
display monitor. (Refer to paragraph 2.3.4 for a
description of the LDDZ :Lllstruction.) In the
example, the refresh instructions contained in the
body of code designated as instructions for
drawing image on display monitor no. 1 or no. 2
could 'contain several LDDZ instructions. To
simplify hardcopy generation, all LDDZ
instructions, contained in the body of code
mentioned previously , should be set up so that the
display change enable bit (hit 10) is set to O.
When these LDDZ instructions are e}(.ec:uted, the
displayse1ected remains unchanged (Le., the
display selected defaults to the display selected
via the first LDDZ instruction contained in the
refresh .files allocated to each display monitor).
In the example, a hardcopy of display monitor
no. 1 could be generated as follows:
1.
Send an SU message to modify the first LDDZ
in RFRS2 to select display monitor no. 2.
r
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6-16
~.
I,
2.
Send an SU message to modify the first LDDZ
in RFRS1 to select display monitor no. 1 and
no. 4.
3.
Press the hardcopy button on the hardcopy
unit.
A hardcopy of display monitor no. 2 could be
generated as follows:
1.
Send an SU message to modify the first LDDZ
in RFRSl to select display monitor no. 1.
2.
Send an SU message to mo~ify the first LLDZ
in RFRS2 to select display monitor no. 2 and
no. 4.
3.
Press the hardcopy button on the hardcopy
unit.
.,
'.-"
6-17/6-18
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I
SECTION 7
.
;
~'.
ADV&1CED GRAPHIC CONTROL
7.1
!
,. ; -
I~~
, '
~
'"
!
• ...1
USAGE
INTRODUGT!QN
For certain applications, the GRAPHIC 8 may be required to operate in a stand
alone mode or to provide processing capabilities beyond those available in the
standard graphic control program. As previously discussed~ the display processor
and the digital graph1c controller can operate independently, each executing a
separate program located in the GRAPHIC 8 memory. It is also possible for the two
microprocessors to intera.ct by using the LINK instruction to synchronize the
operations. Programs to be executed by the display processor are loaded into the
read/write memory of the GRAPHIC 8 in the same manner that refresh files to· be
processed by the digital graphic controller are loaded (refer to the descriptions of
the host .... to ..GRAPH!C 8 MU and TK messages in paragraph 5.3.3).
.
Th1.s section describes the manner in which special instructions and prograt1Ulling
techniques can be used to expand the processing capabilities of the GRAPHIC 8. The
discussions assume that the reader is thoroughly familiar with the display processor
instruction set (paragraph 3.2). It is also recommended that. before using any of
the techniques described in this section, the user study a listing of the Graphic
Control Program (Sanders publication H-81-0022) and familiarize himself with the
details of its operation.
7.2
",
PROGR&~
RAM
~I~GES
There are three different linkages by which Gel' can exit to a user-defined
progratl1 in the Glll'HIC 8 memory. Each linkage can be enabled separately by placing
an address, to which GCl' should transfer control, into a specified memory location.
These memory locations and the associated GCp exit points are as follows:
Memoq Location
Associat.ed GCp Exit Point
000710
Unknown command header sent by host computer
000712
Beginning of GCp executive loop
000714
Message ready to send to host computer
Normally, the contents of the linkage locations are zero. If, however, the
user places a non-zero value in any of the locations, its contents will be
interpreted by GCP as a subroutine address to which control of the display processor
should be transferred. That is, a non-zero value in any linkage location will cause
the following instruction to be performed by GCP:
JSR
PC,address
7-1
Ttfnen GCP does not rec.ognize a
command header sent by the host computer, it checks location 710 for a possible
linkage to a user program. If the contents of the location is non-ze 1'0, GCP loads
the command header into register RO of the display processor and performs a JSR PC
instruction to the spec.ifiedaddress.
7.2.1
UNKN'OWN Cm1MAND HEADER SENT BY HOST COMPUTER.
At this point, GCP is operating within an interrupt handling process if
communications with the host computer are being handled over a parallel interface.
If communicationlil with the host cO\llputer are beirJ.8 handled over a serial interface,
GCP operates under simulated interrupt conditions. The basic difference is that the
true interrupt process is nOTl"'interruptible, whereas the simulated interrupt process
can be interrupted.
Regardless oithe interface used, additionalprocessillg required by a user
program should be completed as quickly as possible. GeP expects the user program
either to recognize the command header and process it or to make an error return.
If the cbm.llli!tnd header is recognized and/or processed,the normal return is simply:
RIS
PC
If the command header is not recognized, the error return is:
ADD
R.TS
tn,(SP)
PC
whic.h eventually causes GCP to send an XX m.essage to the host computer with bit 14
of wO'rd 1 set to one. Bit 14 indicates that the command header was not recognized
by GCP.
During the processing of a user-defined command header sent by the hos t
com.puter, the following subroutines of GCP may be useful:
,.
REAP
- readsaddi tional de. ta from the host computer over a parallel or
serial interface (serial data is coded ,4 bytes per word, as
described in paragraph 5.2.1)
RElillH
- reads data in c·ommand header s'ent by the host computer
REQUST - tequests a send buffer for returnirtg data to the host c.ompute r
FULL
- this subroutine should be called if REQUST indicates that no send
buffer is available
Hethods of employing these subrQutines are as follows:
a.
READ
1.
Single word read:
CLR
JS R
7-2
RS
PC , @READ
;SE! as ... 0
; READ ONE \>/'0 RD
; WORD IS IN RO
I
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I:
,I
H
u
NOTE
For a word read over the parallel interface,
the word is placed directly in RO. For a
word read over the serial interface, the
word is decoded and then placed in RO.
2.
DM..I\
mode:
Set RS "" word count
Set R4 = start address
JSR PC,@READ ;RE.ill RS WORDS
;INTO ADDRESS STARTING AT R4
NOTE
On return, the DMA 1s done.
b.
READH
READH is always called by:
CLB.
JSB.
R5
PC,@READH
;SET R5 "" 0
; GET COMMAND HEADER
;COMMAND HEADER IS IN RO
NOTE
For a word read over the parallel interface,
READH is the same as READ. For a word read
over the serial interface, READH places the
word, undec.oded, in RO.
c.
REQUST
The following sequence requests a send buffer:
JSB.
tST
PC,REQUST
R3
BNE GOTIT
;BUFFER ADDRESS
RETURNED IN R3
UNLESS
R3 = a (NONE AVAILABLE)
GOTlT:
~..,.J
7-3
I
I'
NOTE
The send buffer is 4 words (8 bytes) long.
The first word should consist of 2 alphanumeric (A-Z or 0 ... 9) ASCII characters .ri th
the MSB (8th hi t) of each set to one. Any
desired information may be placed in the
remaining three words. The a{!·tion of REQUST
ls to queue the selected buffe'r so that GCP
can eventually send its contents to the host
compu.tar.
d.
I,
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FULL
If REQUST returns R3 "" 0, FULL should be called as follows:
Set R3 .. first word intended for send buffer
JSR PC,FULL
f
NOTE
Calling FULL c.\luses' Gep to send a buf fer XX
message to the host cOtllputer as described in
paragraph 5.3.1.
7.2.2 BEGlNNING OF GCP EnCtI'I'IW LOOP. Gel? operates constantly in an interruptible
executive loop that performs the follOWing steps as shown in figure 7-1.
Anyaddition.;tl proceSSeS that the user may wallt to include in the GCP executive
loop can be included by Wl'iting an appropriate subroutine and placing the starting
address of the subroutine in linkage location 712. GeP then performs a JSR PC to
the specified address as the first step in its e:1l;:ecutive routine. Note that the
contents of registers RO through as are meaningless at this point in the execution
of the program.
".
The Gel? subroutines listed in paragraph 7.2.1 may also be useful in userdefined programs to which GCP exists via linkage location 712. Two additional GCP
subroutitleS that tttay be useful are:
EMEIN'! - enables interrupts on interface to host computer
DISINT - disables interrupts on interface to host computer
These subroutines are called by JSR PC,@E.NlUNT and JSR PC,@DISTNT, respectively.
7.2 • .3 MESSAGE READY TO SENU TO HOST COMPUTER. As described in paragraph 7.2.2, GCP
automatically checks linkage location 714 whenever a message is ready to ,be sent
from the GRAPHIC 8 to the host comp'l.tter. If the content of location 714 is zero,
the message is sent to the host compt,lter. If the content of location 714 is
non-zero, GCPperfoI'llls a JSR PC to the user-defined program at the specified
I
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7-4
f
,~",':;'
-"
;:",
~"'l
o
LOAO all' BUFFER
MESSAGE
WITH
OR BUFFER
FULL MESSAGE
xx
JSR PC. @712
YES
ENABLE INPUT
I NTCflRUPTS
(JSR PC. @ ENBINT)
GO TO START
YES
SET PflOCSSSOR
PRIORITY TO
o TO eNABLE ALL.
INTERRUPTS
(PSW+-ill
,
LOAD all'
BUFFER WITH
NMMESSAGE
J'
NO
JSR PC.@714
NO
Figure 7-1.
GCP Executive Loop Flowchart (Sheet 1 of 2)
7-5
I
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(I-
t
-."
YES
OIS.A!lillS AU.
INTERRUPTS
(I'SW=7)
NO
"
UPOATE a/I" BUFFeR
TO NEXT MeSSAGe
SLOT
f
f
f
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,]
l~
NO
ENABl.l!ALL
INTERRtJP'tS
lP$W .. OI
l
t
GO TO START
1..._ _ _ _-t1Pi
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YES
TRY TO SENt)
Ne;1(T MESSAGE
TO HOST
{
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.Figure 7-1.
7-6
Gel? Executive Loop Flowchart (Sheet 2 of 2)
..•
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address. One purpose of this linkage is to permit standard messages to be
intercepted and, if necessary, modified before being sent to the host computer. A
second purpose is to permit the data in certain messages to be processed locally by
user-defined routines within the GR.4.PHIC 8 and thereby relieve the host computer of
many of its processing tasks.
7.3
LINK INSTRUCTION
The graphic controller LI~l{ instruction provides an efficient means of timesharing the capabilities of the digital graphic controller and the display
processor. Use of the LINK instruction permits:
..
..
<; •• , ....
,
Peripheral and optional equipment to be slaved to requirements of the
refresh file.
Parallel processing to be accomplished by the digital graphic contrOller
and the display processor without having to maintain a separate work copy
of the refresh file and without harmful interference to the displayed
image.
.j
7.3.1 BASIC INSTRUCTION OPERATION. When the digital graphic controller encounters
a LINK instruction in the refresh file, the follo~ng operations occur:
a.
The digital graphic controller fetches the address portion of the LINK
instruction and then performs a jump and mark to that address.
b.
The digital graphic controller stops fetching words from the refresh file,
halts, and interrupts the display' processor.
c.
The contents of a few graphic controller registers are made available to
the program being run by the display processor.
Several features of the display processor contribute to the efficiency of
operations using the LINK instruction:
,
a.
The display processor allows a unique trap vector to be assigned to the
LINK interrupt (the hardwired trap address is 170). Therefore, a lengthy
and time-consuming interrupt handler is not required to sort out the LINK
interrupt from all other possible types of interrupts.
b.
The display processor hardware automatically stores its program parameters
when an interrupt occurs.
c.
Almost all display processor instructions can be performed using
references to memory locations instead of registers. This means that, for
many routines, the contents of the general purpose registers need not be
stored.
d.
If the LINK interrupt routine requires the use of one or more general
purpose registers, their contents can easily be saved on the interrupt
push down stack and recalled upon completion of the interrupt routine.
,:;
7-7
I
,.-;;.
e.
Upon completion of the LINK interrupt routine, a single instruction (RTl)
returns the display processor to the task. i t was performing at the time of
the interrupt.
f.
'the interrupt nesting feature of the display processor (using the stack
pointer) allows the LINK interrupt routine to be interrupted, if
necessary, and returned to in an Emtirely transparent manner.
To restart the dtgitalgraphic contro1141:' after a LINK irlSt1'\1ct10n has been
it is only necessary to write the desired starting address into the
i graphic controller program counter (DPC).
The digital graph1c controller
: automatically starts fetching refresh file instructions from that location. It is
:~ possible for a given LINK interrupt routine to have several ~its, each specifying a
'different restart address as determined by decisions made in the interrupt routine.
t executed,
{ :~~
r -}
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,.1
There are threebas1c methods of using the LINK instruction. They are referred
to as synchronized l1nk.age, sync .Unk, and super sync. Paragraphs 7.3.2 through
7.3.4 de$cr1.bla thEtse methods in <1etail a.nd givla a coding exampl, and a. flow chart
for each.
7.3.2 SYNCltR.ON1:ZED LINKAGE. Synchl:'onized linkage is the straigntfot'Wardra.ethod of
using the LINK instruction. Figure 7-2 is an eX4ll'1ple of program cod1ng using the'
synchl:'onued linkage method. Figure 7....3 is a flow chart for the coQing example.
The following features of the synchroni;;!:ed link.age method of using the LINt<.
instruction should. be noted:
a.
Tne intel:'tupt t'out1.ne can be used sevet'al times ina refresh file. This
is PQss1.ble because each c,alling rO\J.tine autoUl8.t1.cally writes
unique
LINK. return add:ress into memory to provide the required steering back to
the routine that called it.
b.
If two or UlOl:'e differant image problems must be solved in the same r·efresh
file, the synenronized linkage tlllathod usually requires the beginning
portion of the LINK interrupt routine to ccmtain an 1;.nterrupt handler.
This handler is used, to identify which of the image problem$ is to be
solved. Such identification can be based on the LINK return address, the
contents of the gra.phic control,.'lel:' progra.m counter,orthe contents of
other graphic controller reg1sters.
c.
a
If the refresh. file and image problem-solving sequence is well ordered, an
interrupt h.andler m.ay not be required. Instead, the routine !.lsad to solve
one image problem can load the trap addr$$s (location 170) with the
starting addr$ss of the next L!NK interrupt routine in the refresh file.
7.3.3 SYNC LINK. The sync link method illlprovesthe efficienc;.y and ease of udng
the LINK. inStruction by meanS .of a simple techn:J.que.When a sync link 0ptaration is
performed, the LUll inst');Uction causes the LINK return address to be placed in the
LINK trap address (location 170). This. in turn, causes the display proceSSor to
trap to the next instruction in the refresh file. Figure 7 ....4 is an example of
program coding using the sync link method. Figure 7-5 is a flow chart for the
coding example.
7-8
t
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Trap Coding
I ~5~~~
170
172
I
Word CAT+2 ;Trap pointer
Word +0340 ;New priority assigned
Refresh Coding
·..
·..
·..
1000
1002
1004
1006
DOG
5000
1012
·..
·..
Graphic Controller
Instr~ctions
LINK CAT
4000
1000
1014
}
}
Graphic Controller Instructions
r(
Interrupt Coding
5000
CAT
·..
Normal LINK return address
5002
5004
Interrupt
Routine
5010
... .i
5012
5014
5016.
5020
13737
5022
5000
5024
165006
5026
2
MOV @i,CAT, @{JDPC
RTI
.- ..}
GA-77 -419-08
Figure 7-2.
Synchronized Linkage Program Coding Example
7-9
.
j
GRAPHIC CONTROLLER
I
l
f;
DISI'L\Y PROCESSOR
Prepare crap locations 170 and 172
'~ith
LINK interrupt ~outine location and
scatus and priority respilctively
(Le., CA,):+2, priority i)
0.801
'" [start thil graphic ctt1':Ollel.'
,
]
Fetch and process graphic controller
ins,!;'t'uctipMJ:: controller)
!ntart'Upt: dis\llay prccessot' chrougl\ crap
address 170
Detect interrupt
Push old PC and stacus onto stack
Gtl.t ne'" PC and status hom l.ocaciol;s
170 and 172
Stare performing inter1':upt at location
CAT+:;!
Do interrupt routine
S tart fetching graph,ic oon1':1:'ol1"r
inst1':ucl;1on5
.[
-
Loed the LINK
the DPC.
ratu~
,'
f
I
Return from interrupt, by Loading PC and
status regis,er from the top of the stack.
!
f
G t i n u e bacl<;ground
7-10
f
{
.f
Fetch and procilsil ,sraphic cont1':oller
instructions
Figure 7-3.
saaress 000+4 into
COntents (CAT) DPe
I
(aSkS
Syuchronized Linkage Flow Chart Example
I
I
I
,
.J
The result of using the sync link method is that display processor instructions
can be placed directl, in a refresh file. When the digital graphic controller
encounters the LINK iristruction, the interrupt routine (immediately following the
LINK instruction in the refresh file) is processed by the display processor •
Return to processing of refresh file instructions by the digital graphic
controller is accomplished by means of a relink command. The form of this command,
which is shown in figure 7-4, never changes. Thus the assembler can generate the
necessary coding with a single macro instruction.
The reI ink operation need not always be ~o the next sequential group of
instructions in the refresh file. Several relinks can be provided for each LINK
operation. Each relink can jump to any appropriate location in the refresh file as
detennined by decisions made in the interrupt routine. All that is necessary to
jump anywhere in memory is to change the second word of the reI ink command to
reflect the desired location.
Using the sync: link method enables the capabilities of the digital graphic
controller and the display processor to be time shared to solve a problem in a
manner that is practically transparent to the programmer. Note that no interrupt
handler is required if the sync link method is used for several LINK instruc tions in
a refresh file. The sync link method uses the display processor interrupt trapping
mechanism as an automatic interrupt handler to establish the required return paths.
7.3.4 SUPER SYNC. The main feature of the super sync method is that the LINK
instruction identifies to the display processor a location in the refresh file.
This permits parallel processing by the display processor and the digital graphic
controller that is synchronized with the displayed image. Figure 7-6 is an e~ample
of program coding using. the super sync method. Figure 7-7 is a flow chart for the
coding example.
An obvious advantage of using the super sync method is that the digital graphic
controller is required to be halted for a minimum amount of time. Therefore, the
m~~imum data load that can be handled by the digital graphic controller is not
reduced significantly. If data internal to the digital graphic controll'er is
required by the display processor, i t can be read before the digital graphic
controller is restarted and then processed while the digital graphic controller is
running.
The super sync method can be used to perform both simple and intricate
functions.
7-11
Trap Coding
170
Word +0340 ;new priority assignment
172
I
I
f
f
I
1
"I
::~
:"'1
f
Refresh Coding
·..
1000
·..
1002
Graphic controller instructions
1004
1006
DOG
4000
LINK +01791
110
1010
·..
1012
1024
·..
·..
·..
·..
·..
1026
12737
1030
1036
1032
1650116
1034
2
1014
1016
1020
1022
·..
·..
1036
1040
(
Display Processor Instructipns
MOV #.++010.@#DPC }
Relink
Command·
RTI
}
Graphic controller instructions
GA.. 77-419-10
Figure 7-4.
I
I
Sync Link Program Coding Example
I
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f
I
7-12
(
GRAPHIC
DISPLAY PROCESSOR
CDNTROL~-a
Prepare crap location 172 with appropriate
new status and priority (i.e., priority 7)
Fetch and process graphic controller
instructions
LL~
Start ehe graphic controller
Do background casks
Fetch location DOG
Decode
...
instruction (0004XX)
Fetch LINK address froll! location 000+2
(-110)
Store LI."IlC return address DOG+4 in
link address
Seop fetching (halt graphic controller)
Interrupt display processor through ehs
trap address 170
Detect intarrupt
'• • J
Push old PC and status onto stack
Get new PC and status from locations liO
and 172
j
Start performing interrupt routine at
location DOG+4
~_n_.O___in_t_e_r_r_u_p_c__r_o_u_C_i_n_er-________________... ~
t
Start fetching graphic controller
instructions
t
Load the present PC ... lOS into the DPC
t
Fetch and process graphic controller
instructions
Return from interrupt by loaning PC and
status r~gister from the cOp of the stack
i
Continue background tasks
Figure 7-5.
Sync Link Flow Chart Example
7-13
,
'{
"
f····
170
Word t0340;new priority assignment
172
Re·£:resh Coding
·..
·..
1000
1002
}
Graphic controller i""tructions
1004
1006
DOG
4000
1010
170
1012
12737
1014
1024
1016
165006
1020
137
1022
5000
LnlK +0179.1 .
MOV 11.++012, @iiDPC
.JMP @1/CAT
·..
1024
·..
·..
1026
1030
Graphic controller instructions
Parallel Process Coding
5000
CAT
5002
•
•
o!i'
·..
5004
f,
I,~
,
J .-
I,
I
t,
L
L
I
t
{
2
ItT!
I
{
Figure 7-6.
7-14
Super Sync Program Coding Example
I
I
~tAPH!C
DISPLAY PROCESSOR
CONTROLLER
Prepare trap location 172 with appropriate
new status and priority (i.e •• priority 7)
Fetch and process graphic controller
instructions
III
Start graphic
Fetch location DOG
Do background tasks or wait
Fetch LINlC address fro\1l location DOG+2
("'170)
Store LINlC return address DOG+4 in
link acidress
Stop fetching (halt graphic controller)
b__
trap
address
r - - - - - - -..
I_n...t ...e...
rru_p.t_"
..d_i.s...p170
...l.a.y_pr_o_c
..e_s_s_o_r_t_h.r_o_U_gh_t...h_"e__....'
Start fetching graphic controller
instructions
Fetch and process graphic controller
instructions
I
b---_-____
Detect interrupt
.:·
"-1r-"_....._ _ _ _ _ _ _..J1
I Push old PC and status• onto stack
I
I
Get new PC and status from locations 170
and 172
I
I
Load the present PC + 128 into the DPC
I
I
jump to routine to be processed in parallel
I
I
Perform parallel processing with the
refresh file
I
Return. from interrupt by loading PC and
status register from the eop of che stack
I
I
Do backgroufid tasks or wait
Figure 7-7.
Super Sync Flow Chart Example
7-15
I
I
7.4 THE DIGITAL GRAPHIC CONTROLLER AS A DEVICE
"
-
Although the digital graphic controller. operates independently of the display
processor, it is under the control of the d,isplay processor at all times. The
digital graphic controller can be hal ted and restarted at any time by the display
processor and the graphic controller registers are at all times available to the
display processor for purposes of reading. writing, or testing data as required. As
far as the display processor is concerned, therefore. the digital graphic controller
can be considered as a device connected to the controller bus.
Sectiou 4 coutains complete descriptions of all graphic controller registers
and lists the address that is assigned to each. With the exception of the function
control stop register (FUNS), the sense register (SENS), and the mask register
(MKR) , data should not be read fran or written into any graphic controller registers
unless the digital graphic controller is halted. With the digital graphic
controller running, such operations normally result in an error interrupt to the
display processor through location 10.
7 .5
THE PARALLEt
INTElU'ACE AS A DEVICE
..........
.
As previously discussed, i f a parallel interface is installed in the terminal
cQntroller, Gel' assumes that communications with the host computer are to be haRdled
via this interface (parallel interface no. 1).
The parallel interface can operate in either a DMA
~ode
or a single-word
transferrnode. The DMA mode is in1 tinted when a non-zero value (two! s compleme\'l.t of
the nUtllber of wot'cls to be transferred) is written into the ~rd count register
(WeRl) and continues until the speCified number of words has been transferred. Bit
2 in the statu.s register (STR1) determines the direction of transfer and the value
in the memory address register (MARl) determines the starting memory address to be
used for the DMA oper.ation.
i~en the parallel interface is operated in the single-word transfer mode, data
sent from the host computer to the GRAPHIC 8 is read from the l)utput data register
(ODRl) while data to be sent from the GRAPHIC 8 to the host computer is written into
the input data register (IDRl). In act1.lality. the anRl and IDR1 are a single dualpurpose register and, therefore, the same address is used for both. The direction
of datat:ransfer is determined by control signals to or from the host computer as
appropriate (refer to paragraph 4.4.2).
7.5.1
PROGRAMMING EXAMPLES. Proper handling of the parallel interface requires
knowledge of the handshaking requirements of the communication-s ~yith the host
computer. The following codil'lg examples illustrate methods for handling the
parallel interface in its Various operating modes.
I
I
I
f. :
(,
f.
f
I
I,
f:
I
f
f
7-16
I
I
.".
.""
a.
To transfer a single word from the host computer (output data transfer):
WAIT:
.'
ACKNLG:
bs
MOV
BIS
TST
BMI
RO,@IFIDRI
#20000,@#STRl
@i#STRI
WAIT
;MOVE DATA WORD INTO IDRI
;SET 'INPUT WORD REQUEST' BIT IN STRI
;WAIT FOR HOST TO ACKNOWLEDGE BY
CLEARING 'INPUT NOT READY' BIT OF STRI
To set up a DMA transfer from the host computer (output data transfer):
WAIT:
-,
,-."
COMFL:
d.
1'40, @ffSTRl
ACKNLG
;TEST 'OUTPUT CONTROL' BIT OF STRl
UNTIL SET BY HOST
;MOVE DATA WORD INTO RO
;SET 'OUTPUT WORD RECEIVED' BIT IN STRI
;WAIT FOR ACKNOWLEDGE
BY HOST CLEARING THE BIT
;
To transfer a single word to the host computer (input data transfer):
WAIT:
c.
@{FSTRI
WAIT
@!!ODRl,RO
#40, @ftSTRl
TSTB
BPL
MOV
BIS
BIT
BNE
@{/STRI
WAIT
TST'S
BPt
BIC
MOV'
MOV
BIT
BEQ
InO,@iISTRl
IIDATABF , @tfoMARl
1'-IOOe ,@tFWCRl
1,20,@iFSTRI
COMPL
;TEST 'OUTPUT CONTROL' BIT OF STRl
UNTIL SET BY HOST
jENABLE DMA OUTPUT MODE
. ; SET MARL TO INTERNAL BUFFER ADDR
; START DMA TRANSFER OF 100 WORDS
;TEST 'OMA COMPLETE' BIT IN STRl
(BIT IS SET WHEN DMA COMPLETE)
To set up a DMA transfer to the host computer (input data transfer):
WAIT:
BIS
MOV
MOV
BIT
BNE
~
I/I0,@i}STRl
#OATABF,@#MARI
#-lOO.,@#WCRl
tF20,@fISTRl
IvAIT
;tNABLE OMA INPUT MODE
; SET MARL TO INTERNAL BUFFER ADDR
;START DMA TRANSFER OF 100 WORDS
;TEST 'DMA COMPLETE' BIT IN STRI
(BIT IS SET WHEN DMA IS COMPLETE)
7.5.2 INTERRUPT OPERATION. The coding examples in paragraph 7.5.1 assumed that the
interrupt capabilities provided by the parallel interface were not used. An
interrupt capability is provided for both input and output data transfers. These
interrupts can be enabled or disabled separately as required by changing the status
of bit 14 (input interrupt enable) and bit 6 (output interrupt enable) in the status
register. Setting a bit enables the associated interrupt while clearing a bit
disables it.
When the input interrupt enable bit is set, an interrupt to the display
processor occurs when the host computer acknowledges that data has been taken or
when an input DMA operation is complete. When the output interrupt enable bit is
set, an interrupt to the display processor occurs when output data is available from
the host computer or when an output DMA operation is complete.
An attention interrupt is also prOVided by the parallel interface for special
applications. This interrupt is enabled when bit 11 (attention interrupt enable) of
the status register is set and disabled when bit 11 is cleared. The attention
interrupt is associated with status register bits 9 (attention no. 1) and 10
J
7-17
,.
I
I
(attention no. 2 ) which reflect the states of the two attention signals from!: the
host c.omputer. When the attention interrupt is enabled~ an interrupt to the'display
processor occurs whenever one of the two attention signals changes from a lo'W to a
high state.
Bits 0 (spare input no. 1) and 12 (spare input no. 2) of the status register
are provided to enable. special signals to be sent from the display processor' to the
host computer via the parallel interface. These bits may be programmed as r~quired.
7.6
TEE SERIAL INTERFACE AS A DEVICE
•
:pi ..
Up to nine serial interface ports can be associa..ted with one GRAPHIC 8 system.
One port i$ contained on the ROM and status logic· card and four ports are contained
on each multipart serial interface card (up to three multiportserial interface
cards may be installed in a termini:11 controller). All serial interface port:s
operate at speeds up to 9600 baud. The following paragraphs describe the use of the
ports pro'lf:!'ded by each type of card.
ROM AND STATUS LOGIC G...<\RD PORT. The serial interface port on the ROM and
status logic card is used to interface a teletypewriter to the GRAPHIC 8 for
maintenance and diagnostiC purposes • This interface operates in a manner similar to
the standard teletypewriter interfac'e used in conjunction with minicomputers of the
PDP-ll type manufactured by Digital Equipment Corporation (DEC). Instructions for
its use are contained in the DEC PDP-ll/04/34/1+5/55/60 P:rocessor Handbook which
should be used as a supplement totMs manual. Registers associated wit:h this port
are described in paragraph 4.4.1. Note that the register formats are the same as
the formats for corresponding registers associated with the mul l;1port serial
interface porta.
7.6.1
7.6.2 MULTIFOR.T SERIAL INTERFACE PORTS. ports on the mul tipO'i~·t serial interfac.e
cards are the ports through which peripheral devices (keyboards ~and PEO f s)
communic.ate with the display processor. The host cOI!lputer also communicates with
the display processor through a multipart serial interface port ,...hen a parallel
interface is not used for the purpose. All four ports on each multipart serial
interface card can function as basic Serial interface ports. Additionally, the
first port on each card is provided with full RS-2::32C capabilities for the purpose
of cowmunicating with a host c.omputer or driving a modem. Refer to paragraph 4.4.1
for a list of the devices' assigned to each port and a description of . each type of
register associated with the ports.
Using a mul tiport serial interface port is somewhat dependent upon the device
to whic.h the port is connected. The follOwing paragraphs, therefore, discuss ea.ch
type of device separately and give examples of how the associa.ted port is used.
7.6 • .2.1
Host Computer. When commtUlications with the host computer are handled via
a serial interface. the host computer is connected to serial interface port 1.
Examples of representative coding sequences used to handle these communications are
as follows:
{:
I
j
r,
I
{, (
I'
I
f
I
I
I
l',
"
II
..
7-18
r
(
i
i
a.
To receive data from the host c.omputer:
'JAIT:
'0.
TSTH
BPL
@ffRSRl
WAIT
MOV
@RDB1, RO
;TESt 'RECEIVE DONE' BIT OF RSRI
(DONE INDICATES CHARACTER RECEIVED
FROM HOST)
;PUT CHAR IN LOW ORDER BYTE OF RO
To send data to the host computer:
WAIT:
MOV
T5TH
BPt
Rot@trrDBl
@iFTSRl
WAIT
;MOVE CHAR FROM LOW ORDER BYTE OF RO TO TDB1
;TEST 'TRANSMITTER READY' BIT OF TSR1
UNTIL SET BY SERL~ INTERFACE
;(READY INDICATES CHARACTER SENT TO HOST)
NOTE
The 'preceding examples. do not use the
interrupt capabilities provided by the
serial interface port. If desired,
interrupt processing techniques may also be
used.
7.6.2.2
Keyboards. Gel' accepts inputs from. alphanumeric/funct'ion keyboards via
serial interface ports. All inputs from port 3 are identified as inputs from
keyboard No. 1 and inputs from port 7 are identified as inputs from keyboard No.2.
'- "
An example of a c.oding sequence used to accept keyboard irtputs is as follows:
To obtain an alpha character from. a keyboard:
WAIT:
BIC
@#RSR3
WAIT
@1/ROB3,RO
fH77600,RO
JTBST 'RECEIVER DONE' BIT OF RSR3
UNTIL SET BY KEYSTROKE
;PU'! CHAR IN LOW ORDER BYTE OF RO
; CI..E.A..~ RO EXCEPT FOR 7 -BIT ASCII CHAR CODE
BIT
IflOO,RO
BEQ
1$
; SEE IF FUNCTIO N
;OR MATRIX KEY
jBRANCH FOR FUNCTION
;OR MATRIX KEY
TSTH
BPI..
t10V
;CODE TO PROCESS CHARACTER
1$:;CODE TO PROCESS FUNCTION OR MATRIX KEY
The lighting of function or matrix keys on a keyboard requires that five bytes
be sent to the keyboard via the associated interface. The first byte (2248) sets
up the keyboard to accept the data in the four bytes that follow. Bytes 2 and 3
contain data for lighting function keys 0 through 7 and 8 through 15 respectively.
Bytes 4 and 5 contain data for lighting matrix keys 0 through 7 and 8 through 15
respectively. A key is lighted when its corresponding bit is set and not lighted
when its corresponding bit is cleared. Fooction and matrix keys on a keyboard are
designated as follows:
7-19
f
I
IJ
FUNCTION KEYS
I
0
r1
2
r 4·1
3
!
5
6
17 I
8
I
9
I lo"TIil12 113 .0 4 111J
"
HATIUX KEYS
71819/ls
4 I 5\ 6 114
1 IzT3 \13
10
1'0\11
\12
An example of coding that could be used to light function keys 1, 3, and 10 and
matrix keys 5, 12, and 13 is as follows:
MOV
11224,RO
;8ET UP KEYBOARD
JSR
PC, OUT
;
MOV
JSR
MOV
JSR
MOV
JSR
MOV
i#12,RO
JUGaT FUNCTION
PC, OUT
f/4,RO
PC, om
{140,RO
KEXS 1 AND 3
;LIGHT FUNCTION
;
1160,RO
JSR
PC,OTJT
OUT:
MOV
WAIT:
TSTB
RO,@4ITDB3
@#FTSR3
WA.IT
PC
BPI.
RTS
TO ACCEPT LAMP DATA
KEY 10
jLIGHT MATRIX
KEY 5
;LIGHT MATRIX
KEYS 12 AND 13
PC,OUT
;MOVE BYTE FROM
ao
TO !DB3
;TE5T 'TRANSMITTER READY' BIT OF TSR3
; UNTIL SET BY INTERFACE (BYTE TAKEN)
; RETURN FROM SUBROUTINE
7.6.2.3 PEDIs. PED's (e.g., trackball, forcestick or 4ata tablet) are assigned to
serial interface ports 4 and 8. Inputs tram port 4 are identified by Gep as coming
from PED no. 1 while inputs from port 8 are identified as coming from PED no. 2.
Inputs from trackball/fol;'cestick t'epresent coordinate displacement data in the form
of two successive 8 ... bit bytes that are updated at a maximum rate of 37.5 Hz. No
inputs are generated unless the PED is moved. The format of each byte is as follows
(110te tha.t the coordinate data in each byte is in two I s complement form):
7
6
5
..
4
-
0
+
{
X COORD
3
2
DATA
1
0
X coordinate displacement byte
I
1
7-20
-+
Y COORD DATA
Yc.oordinate displacement byte
'.
-
t
I
I
r
f
I,
I
f
I
I
I
I
I
'('i
(
,J
'
.
~
The handling of PED data is similar to the handling of inp~~s from a keyboard.
Refer to paragraph 7.6.2.2 for examples of coding that can be u~ed.
7.7
...
'
PROGRAMMING EXAMPLES
7.7.1 PROGRAMMING THE COLOR DISPLAY MONITOR. Three primary colors are available
for the color display monitor. They are Red (R), Green (G), and Blue (B). The
displays are selected by the LDDZ instruction. The color is specified by the use of
the Load Pixel Data Register (LDPD) instruc tion ,or the LDDZ instruc tions (for
configurations with 3 bits per pixel plus blinkf.
The value in the Pixel Data Register (without the MSB i f blink on) is the index
into the lookup table (LUI). Each 8-bit entry in the lookup table has a value that
represents the actual color seen on the screen (written to pixel memory). The
format of the entry is:
\ -
7
n
.
B,O
5
G2
4
q1
3
GO
2
R2
1
ttl
0
RO
were:
r.'
,i
'I.
6
,
Rn
is the nth intensity bit of Red,
on is the nth intensity bit of Green,
Bn is the nth intensity bit of Blue.
For a 3 plus blink (*)configurations any 8 colors can be selected from a
choice of 256 colors by the use of the Lookup Table and the Modify Lookup Table
(MOLU) instruction. For example, the following LOT values will give a reasonable
set of COlors.
LUT BYTE INDEX
0,
1
2
3
4
5
6
7
LUT VALUE (OCTAL)
'0
7
70
77
300
307
COLOR
BLACK
RED
GREEN
YELLOW
BLUE
MEGENTA
370
CYAN
377
WHITE
7.7.2 USE OF BLINK AND LUT. The size (8 bit bytes) of the mapped portion of the
Lookup Table (LUT) is the number of simultaneous intensities or colors available for
a given configuration. (See Table 7-1.) The blink bit acts on the data independent
of the contents of the LUI.
:.4-
7-21
..
Table 7-1.
I
Mapped LUT Size
SIMULTANEOUS INTENSITIES
OR COLORS
BITS/
PIXEL
2 plus blink
4
8 plus blink
2
2
4
4
8
8
t
BYTE SIZE
2
4
8
16
128
'J.V
t:.
128 plus blink.
256
256
For example, a blinking blue vector on the screen with a con.figuration of 4
bits/pixel fN'ith blink as the MSB could be p'roduced by the following refresh.
REFRESH:
f
I
I '"
IN!T
LD01' ••
LDDZ ••
MDLU
LOOP:
ADR, 10,1,400 ., where ADR: BYTE 0,0,0,,0,300,0,0,0
WA'rE
LDPD
LDXA
•
blink + intensity = 14
center of screen
14
°o
YlT[A
draw vector
200
'DRYA
JUMP
LOOP
INDEX
+0"
-_... _ - -... ) Intensity = 4
P;t:tel Data Register
I
I
7
I"
I 0
I
6
I
0
!
I
5
4
3
0
0
1
2
1
0
1
o
0
I
I.
I
I
I
I
I
-->
+1
+2
+3
+4
I
I
I
,-
I
I
I
I
I
0
0
0
0
!
I
0
Screen
'\'
I
Blink
----~:-,...-......
-,....--------..-..
Figure 7-8.
)
Relationship
I
bet1i~een
( ..........
'1
I
I
I
I
!
,I
I"
I
I
I
_-_ _------....
I
PDR and LUI
To stop the vector from blinking, rem.ove the blink bit from the LDPD
instruction and execute the refresh file.
7-22
I
300·', BLUE
I_~__.....I
+7
,
LUI
I
(
APPENDIX A
SUMMARY INFORMATION
,"
!
i .
A-l
177777 r - - - - : - -........- - - - -
~
DATA AND
STATUS
fiEGISTERS
AND
DEVICE
ADDRESSES
~
GCP 'IS ALSO LOCATED
IN SECTIONS IN
160000-177777 AREA.
160000
f
I
I
f
I
'1
" i
,I
-r------------~----~
157777
r
GRAPHIC
CONTROL
ROM
PROGRAM
OCTAL
BYTE
ADDRESSES
I
I
{1
140000
~------------------~
··~J1
137777
ROM
OPTIONAl.
MEMORY
AND/OR
READ/WRITE
MEMORY
EXPANSION
f
I
f
040000
I
-r--------------------~
037777
AVAILABl.E
TO
USER
READ/WRITE
MEMORY
003000
002777-+-------------1
L
000000
RESERVED FOR USE BY GC?
H-79-0348·~1
Figure A-l.
.1-·2
~APH!C
'-""""....
8 System Memory Map
i
I
I
I
,
('
I-
Table A-I.
GRAPHIC 8 Local Mode Command Summary
KEYBOARD
ENTRY
--
RETURN
Execute local mode command or returns system to local monitor level.
nnnnnn/
Display contents of memory address nnnnnn (octal),
I
Increment memory address counter by two and displays address contents.
or
.'
L_.
OPERATION
Decrement memory address counter by two and displays address contents.
(BO 0-3ZK; BI 32-64K; HZ 64-96K; B3 96-128K;
Bn
Select memory bank.
and B4 16-32K R..A.'1).
S
Transfer GRAPHIC 8 to system mode operation.
T RETURN
Transfer to the verification test pattern.
L RE'lURN
Load memory from paper tape reader.
nnnnL
Load selected option from expansion module.
RETURN
U
RETUR."i
Unload all options.
o
RETURN
Display status of all options loaded.
Q
Decrement contents of display processor Q register by two and displays
result. Used with diagnostics to indicate address at which display
processor halted.
nnnnnnD
RETURN
Direct graphic controller to display refresh file beginning at address
nnnnnn (octal).
nnnnnnG
RETURN
Transfer control of display processor to program beginning at memory
address nnnnnn (octal).
Y RETURN
or
P RETURN
Call teletypewriter emulation program. 'After entering emulation
program, function key FO clears CRT screen. Function key Fl selects
full or half duplex operation; receipt of octal code 035 from the host
computer or pressing function key F13 transfers GRAPHIC 8 to system
operating mode. (Y ~ serial, P = parallel)
RUB OUT
Delete last octal entry from keyboard.
Change 1
A-3
I".
Table A-2.
GRAI'HIC 8 Controller Instruction Summary
NUMERICAL LIST
.',1
Legend:
f '.
°2 co<:1e word
The opcodeword contains bits in one ,of three' c$tegories:
Numeric represen.ts actual opcode bits.
necessarily adjacent.,
1.
Note. that opcod.ebits are not
A thruG representV'ariable bits tl) (either binaryuro or one) that
effect the function of the instruction.
B .. O(J)O
C .. 0(1)(1)
D .. alOa
3.
=
-
!
14C~
1.
G 00
1 I
II
I I I
I I I
I I I
I
I
.
I I
I 1 I UOI
I I
'I
GG
II
II
I
I
I
I
,- -,
I
I moo
I
0
2
1
I
I
I
I
I
I
I
I
I
aI
I
I-
I
I
I
I
I
i
I
yinc
0
,-,-
...'
(\)!I'Hf) I
Q)(\)tl)
PIlLR xinc,
2.
('"
I
I
I
-1
Q)ID(D
( ' '1
.-.J
For example:
I
j
X means any bits le.ft '(up to 3) are ignQred by the instruct:!.on.
D2A .. (Dl(J) binal.'»,
XC
XID(I) binary
I
[,
G .. d)(\)(I)
Underline ( ) means a com.bination of V'ariable and left c'\fer bits that
fit into t~ee bits as:
.
1
f.
E ... IJ)O(J)
F .. Q)d)O
A .. oOID
I
000 I 010 I 001
xc
I r
I I
-I
I
I
xxx 1 xO)(\)1
I
I
X
-,
l-rl
I
CALLE bank, adr
A-4
I,"
I ')
rI:~
I
,.
I'
I
r
I
Table A-2.
GR1<.PHIC8 Controller Instruction Summary (Cant)
MNEMONICS
adr
=16 bit address
bank
=2
bit bank 0-3 (if absent, bank 0 is assumed)
vcnum ... video controller number 1-4
ix
... initial x value
iy
... initial y value
fx
= final
fy
... final y value
D
... adr is displacement (if absent, adr is absolute address)
DR II
:oil
I
... indirect address bit
F
... final bit 15 of data word
x value
display registlr number
•• _.J
A-5
:1
f
[
"
Table A-2.
GRAPHIC
$ Controller Instruction
Summa~J
(Cont)
·1
i
1
NUMERICAL LIST
PAGE
OPCODE
MNm-10NICS
ooooxx
EREF
3-20
OOlon
Jm1P adr, I (I for mode 0 only)
3-12
JUMPE bank., adt"
3-12
OOHXX
JRMP inc
3-13
*OOllXX
JR.MPl!! inc
3-13
Jl1PZ adt', I (I for mode 0 only)
3-14
JMPZE bank, edr
3-14
-
*0010XXC
0012XX
--
*0012XXC
0013XX
*0013XX
oozon
JPRZ
JPRZE
inc
in(.~
JMPM aar,! (I for mode 0 only)
*0020n
0021XX
3-15
3-15
3-18
3-18
CALL adr
3-15
CALLE bank.,adr
3-15
CALR inc
3-16
CALRE inc
3-16
0023XX
RTlill
3-17
*0023XX
RTRNE
3-17
0030n
IZPR (G7 only)
3-27
0040XX
LINK adr, I (1 for mode 0 only)'
3-19
*0040XX
LINKE adr
3-19
0041GG
SAVD DFJI
3-24
*002lxxe
0022XX
*0022XX
*0041GG
SAVDE
DR/I
*Exte;uled instruction only.
A-6
NUMBER
3-24
I
(
~'.:
I
'
":1
,.
f
·r
.I
I
I
I
I
f
I
r
f
f'
I
"~
.-'1
,
. i
Table A-2.
GRAPHIC 8 Controller Instruc tion Summary (Cont)
NUMERICAL LIST
MNEMONICS
OPCODE
PAGE
NUMBER
0042GG
RESD nRiF
3-24
*0042GG
RESDE nR/F
3-24
0043GG
ADDI DRII,dat(See 3D instruction set in manual H-79-0350)
0066XXC
If
.
,
MOLU bank,adrl,0,bytes,vcnum,adr2
3-31
*0067XX
CL..1U1
3-28
0070XX
WATE
3-21
*0071XX
INIT
3-28
MODE mode
3-28
*0 o73X,."{
UPDT
3-21
*007SXXC
FLPG
0072GG
IABSI
bank,adr ,D,n
3-32
IRELI
*Extended instruction only.
A-7
(
Table A-2.
(
GRAPHIC 8 Controller Instruc tion Summary (Cont)
NUMERICAL LIST
OPCODE
*0076GG
MNEMONICS
PPTA ROT, TAB INC . '
I
PAGE
NUMBER
.3-7
COOR.l
(
.....,
I
,J
j
'I
,.j
.'"
["
CDORn,F
*007700
pm
ROT, TABtNC
3-8
(
INCl
....
INCn,F
-
D10CGCG
-
014CGGG
-
LDDP dparm
3-26
f
3-25
( o;:j
f
, •. _!
LPXR 'ltine
3-3
I,
030CGGG
DRIA 'lteoor (mode 0 only)
3-5
r: ..
034 COOl;
DRXR 'ltine (mode 0 only)
3-5
LDtlD data
3-28
Dan
3-6
-
024CGOO
--
*0 34XXCGG
...,.~
-
040CGGG
-
.:"1
yeoor
044CGGG
DRYR yine
3-6
050CGGG
.....,;
.
MV'U xeoor (mode 0 only)
3-4
*0 50 CGGG
-'
OS4CGGG
?PYA yeoo1'
3-7
*OS4CGGG
MVXR xine (mode 0 only),
3-4
PPY! yine
3-7
MVYA yeoot'
3-4
MVYR y1n<:
3-4
-
o64CGGG
060CGGG
*Extenced instruction only.
A...8
~,~.~ ~
3.... 3
020CGGG
"
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~~;'J
~~).<~
I
.. ,
I
(
'.-
I'
I
f'
>: ,"
'.
(
r
f
-.....
Table A-2.
GRAPHIC 8 Controller Instl:'Uction Summary (Cont)
NUMERICAL LIST
}1NEMONICS
OPCODE
~~
PAGE
NUMBER
070CGGG
LDKX
q
xlen
3-11
074CGGG
DRKY
q
ylen
3-11
10CGDOGG
--
DRSR
xinc, yinc
3-6
lOCGDIGG
----
MVSR
nne, yinc
3-5
IGGD2AGG
TXT
116AD2AGG
- ............
CRA.It
B,S~chr
3-9
14CGDOGG
PPLR
xinc,yinc
3-6
14CG.ElGG
LD'1'I
l:tnc,tinc
3-27
-_.
chrl,chr2
3-10
-,... .J
.
l,.
__ ..l
,._1.1
*Extended instruction only.
A-9
'. t
r
A-2.
[i
GRAPHIC 8 Controller Instruction Surnmary(Gont)
--,
I
ALPFIAllE'l'ICAL LIST
DESCRIPTION
FORMAT
MNEMONICS
'-'OJ
PAGE NUMBER
(,
~
14
15
I
I
ADDI
I 0 I 0
I
I
I ..'"
I+
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0
12
11
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8
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DATA
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10
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1 I
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SU!lROIlTI~1E
x
I
;or
I
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I
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DISPLAY
RJ1;GIsttR
l'MHEDIA'r'S
3-23
CALL
SmUlOllTINE
3~15
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! EmNDED
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3-15
SUlUtOIlTINE
I
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I CALL
I RELATIVE
x x xIx x xI
3-16
I
I
I
1 CHARACTER ASCII CODE
I
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I
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I
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x xI x
I
SINGLE
cw.AC'rER
x
I CLEAR
x I MAPPINt'l
I MFHORY
'! S~U-UlS LENGTH
DR.I\.W
(OR cncu: RADIUS)
CONIC
y
'Ii
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3-9
3-28
3-11
I
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,
(
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.
I- I
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smlROtl'Tlm: Al)DRESS
I
"ruM
I
I
I
L·
I
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f
I
(,
I
I
I
I
Table A-2.
GRAPHIC 8 Controller Instruction Summary (Cant)
ALPHABETICAL LIST
FOBMAT
MNII:!!ONICS
15
14
I
13
I
1-
10
11
12
9
DESCRIPTION
7
8
I
I
0
1
1 I 0/+1 X-COORDINATE
I I
I 0 I 0
I
/
1
1
0
I i I
o 1 01+1
Y-COOIDINATE
I I I
o11 I + I
Y"INatHEN'l'
I
oI
1 I' 1
I
,-
oI oI
Y-INCREMEN'l'
1 1
I
, ,
I
01+
DRSR
!i
6
+
4
3
2
1
PAGE NUMBER
0
DRAW SB:ORT
RELATIVE
X-INClU:MEN'l'
3-6
.._'
--r.',
\,.
....
I
oI
DRXA
I
I
I
I
I
I
1- I
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,
/
DUll
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3-5
I ULATIVE
I
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3-6
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I I
../
0
0
I
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1
1
I
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1 I
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I
x
I
x x I
,
I
0
I
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I
o I
I
0
1
I
1
1
I
I
I
oI x
I
J
0
0
I
1
I
I
I FILL A
AO I CONVEX
I POLYGON
3-32
I
I
I
NIlM!!R Of VEltUCES
010
3-6
X AI7 A161
ADDRESS Of LIST OF VERTICES
I
0
I DRAW Y
I RELATIVE
I
I
I
I
X
xix
I
I
x xI
JW.T REFRESH
3-20
INITIALIZE
3-28
I
I
I
I
I
x x xI x x xI
to.!
_..J
..J
A-ll
I
Table A-2.
(:
GR.,t\PHIC 8 Controller Instruction Summary (Cont)
I
ALPHABETICAL LIST
lS 14 13 12 11 10
I
IZPR
JMl'M
JMl'R
J'Ml'Z
*JMPZl
DESCRIP'!ION
FQ'&.'iA'l'
MNEMONICS
I
I 0 I 0
I I
a
I ... ",
I a I 0
I I
0
I
I
I I. I
I
I
I
I
,
I
I
I
I
I
I
1. I
I
0
I 0
6
a
a
0 I
I
I
aI
0
0
0
I
I
:;
2
1
0
x x
x
Ix.
I
x
xl IN!l'!A1. IZl!;
--.. I
E~lE~t
lx
I
i
I
I
I
1.
4
5
lC
xix.
I
I 0
I a
I
i
I
0
o I 1
I
0
a
,,
0
1 I 0
T
a
I
I
I
I
1
I
it
I
1
xix
I
I
I
0
a
I
I
0
0
1
I
I
0
1
0
I
I x:
x:
I
I
x: I x
I
I
I
0
..
0
I
a I a
I
I
0
1
I a
I
1
I
.roM!' tNCi.l.EMlNT (IF EV1!:N Bm3)
L
I x.
I
x:
I
x I x:
I
x
IF DISPLAY
REGISTER 0
CONTlurrs fa 0
AO
3-14
,
xl JUMP RELATIVE
-,
I
I
I
f
(
JT1Ml> EXTENDED
A17 .\16
I
JUMP ADDRESS
I-I
I
3-14
I
I
,
f
I
JUMP ADDUSS
! I
! a I 0
I I
I 0 I
JUMP IrDIS'"
PLA! REGISTER 0
I CONTE~rrs fa a
I
IF DISP!",,-y
REGISTER a
CONTENTS fa 0
3-15
(
I
I
(
!
I
(
(:
A-12
"i
i
"
i
3-13
I
x xl
~,
:~:, ~'1
(
Jt:1fP SHOR'!'
x;
3-18
I
I
I
mATtV!
EVEN mES)
I
0
AND tlARK
I
I
+. Jl1MP . I;NClW1!N't
1
3-2'7
-,
x xI
I JUMP
1
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I - (UI
I
a
I
Ius A14
I
JPU
I
-
I
I
7
I
I
I
0
I
1.
JUMP ADDRESS (IN
I
0
I
a Ia
8
<}
f;
PAGE NT;'}! llER
I
-~'"
GRAPHIC 8 Controller Instruction Summary (Cont)
Table A-2.
ALPHABETICAL LIST
MNEMONICS
DESCRIPTION
FO~.AT
PAGE NlJMBER
-{ .
14
13
I
a I a
0
15
12
11
10
I
o I a
a
9
8
7
6
a
0
1 I
S
4
2
1
0
xix
x
I
x I
3
,.~.~-
I
I
JR...l>!P
I
1 I
i,
I
I
x x
I
I
I .roMP RELATIVE
JUMP INCREMENT (IN EVEN BnES)
I
I
I 0 I 0
I",
JUMP
·1
}.
I
I
I
0
I
I
I
I
I
I
I
I
I
I
0
010
I
1 1'0
I
0
3-13
I
I
I
I
a I x
x:
I
xix
I
lC
I
I
xl
I
JUMP
3-L2
1
.roMP ADDRESS
I
I
• ':...iI'
.
-'
.
*JUMP!
I 010
I I
I
IA15
I
LDD!
.
"
LDDP
LDDZ
I
0
I
010
0
I
I
I 0 I 0
I
I
JUMP
I
0
I
1
I
oIx
x
I
!
010
I
0
1 I
I
I
I
I
I
1 I 1 I
I
0
1
I
I
0
I
DR.#
I
A17 A161
.
AO
I .roMP EXTENDED
I ADDRESS
I
3-12
I
LOAD DISPLAY
REGISTER
IMMED lATE
3-22
,.
DATA
0
I
xix
ADDRESS
I
011
I
I
010
0
I
I
Al4 •
I
I
I a I a
I
I
I
I
I
1 I 0
DISPLAY PARAMETERS
DISPLAY Z PARAMETERS
LOAD DISPLAY
PARA.'1ETER
REGISTER
3-25
LOAD
DISPLAY
Z REGISTER
3-26
,- .
A-13
I
(!
GRAPHIC 8 Controller Instruction Summary (Cont)
Table A··2.
"''''1
(
ALl'RABE'l'IC.u, LIST
FORMAT
MNEMONICS
DESCRIPTION
PAGE N1JM!ER
~,
is 14
0
LDKX
I
I
13
.
1
,__ 1. _
1
...
i
oI 0
I
-
I xl
I
I
x
I
!
1
x
xl xl
I I
I 1
I
1
0
I
1
I
LDRI
01
0
I
....,
I
0
I
0
:5
4
5
3
2
I
xl
!
I
I
I
I
GlAY LEVEL
0
0
I
I DlVI
I
0
LOAD
CONIC
I X REGISTER
3-11
I LOAD PIXEt.
I DATA
! REGI.STER
3-28
-
I
0
1
"",I
X SEMI-AlIS LE.NG'l'R
I
I
1
7
""
I QIlI
I
I
0
~
I
I
1
1
oI
*LDPD
10
11
1.2
(
,--
I REGI
LOAD DEVICE
FAGE
I EXTENDED
AO I
I
3-19
•
A-15
(,
Tabla A-2.
GR..!'I.'pHIC 8 Controller Instruction Summary (Cont)
.. --MNEMONICS
15
1.4
13
l2
1-""'·"-I
I
"'MDLU
MODE
*MVPD
DESCRIl'TION
FORMA!
I 0 I 0
I 1
I
IAU
I
I I
lAM I
I
I
I I
I 0 I 0
I I
I I
I 0 !0
I I
I
I
I
I
I
10
9
1
1
0
0
I
8
i
6
5
1
0
1
,Ix
iI
!
()
I
I
I
I
4
3
1
2
I
A11 Al61
XODl"
I
:r.OOKtlP
I
.
I
I
0
0
0
0
I 0
I
0
0
I 0
0
0
I
I
1
I
I
0
0
0
I
I
0
I
I
I
I
I
I
I
1
1
I
1
I 0
I
I
1
0
I
I
l!OOE
x:
I
.
I
I
I
I
I 0 1+
I I-
Y-INCREMENT
r
I
I
I
--"I
I
,
I
0
3":29
I
I
I
I
I
FINAL Y 'l Al.UE
1
lion
I PIUt
I DATA
AO I
1
I
I
"I
I
I
1
1INAI. X VALUE
I
3-28
I
I
rnTIM Y: VALUE
I
I
I
I
I
I
I
I LOAD
I INSTRUCTION
! :-lOOE REGIS'l"ER
x Ix A1.7 A1,61
Ul!TIAL X VALUE
1--I
I
I
I
I
-"I
I
LITr ADDRESS
I
I
I I
i
I 0 I 0 0 0 I 1 1 0 I 0 1 1 I :t
I
I
I
I I
I
GaAiRIC 8 MEMORY ADDRESS
l..us
I
I I I :( I I
lAM. IRELI Y Inul
IINCl
I
I
I
I
I
AO
I
I
VIDEO CONTROLLER(S)
I 1 I
I I
3... 31
I TABLE
I
I
I
Ni1M:BEll 0' GRAPHIC 8 a-BIT Bms
.
MVSR
0
I
x x Ix
GRApH!C 8 ~liORY ,IDDRESS
I
0
tl
PAGE mlMBER
1
I +
1-
X-INCFl..EMEN'l'
MOVE
SHORl'
UW.TIVE
3-5
r
I
r
(,
A-16
(
GRAPHIC 8 Controller Instruction Summary (Cont)
Table A-2.
ALPHABETICAL LIST
FORMAT
~ONICS
14
13
011.
0
15
I
MVXA.
12
I
0
011
I
I
~A
~L,
o I 1.
I
1
I
I
I
,- ,
I
!
I
I
1- ,
I
7
8
9
5
6
4
2
3
1
1. 1 01+1 X-COORDINATE
I
MlTXlt
10
11
DESCRIPTION
1 I 1 I + I X-!NCREMENT
I
a I
i
I
01+1 Y-COORDINA'I'E
I
1-'
I
I
PAGE mlliBER
0
MOVE X A.BSOLU'l'E
3-4
MOVE X RELATIVE
3-4
MOVE Y ABSOLU'l'E
3-4
MOVE
3-4
.
I
M.VYR
a I
1.
o I 1 I + I Y-!NCREMENt
I
I I
I a , 0
I I
0
Oil
!
NOOP
PPtlt
*PPTA
I
1.
I
1
1-'
I
0
I
I
'l- !NCl.U:M1l;m:
I
I
a I
0
I
I
F I
I
x
x
I
I
I
1
I
0
010
I
I I
a I a 1+
I
I
1.
1.
1
1
1
I
x
I
0
I
I 1. \+
I I-
a ,a
!
1. \ 0
I
010
I.
0
'l
RELATIVE
!
o I NO OPERATION
I
3-13
PO IN'!'
X-!NCREMEN'!'
1-
PLOT
3-6
RELATIVE
I
I
!
\
o I ROT I TAB. INCA.
POIN'!' PLOT
tABULAR
3-7
ABSOLU'l'E
I
xl+ COORDINATE
1-
A-17
(
Table A-2.
GR.APRIC 8 Cont.roller Ins tructionSummary (Cont)
.~lRAS!tICAL
14
13
I I
I 0 I 0
I I
0
I 'I
"IX
I I
x
15
I
,
*PPnt
I I
I0 I 1
I I
I 0 I 1
I
I
I
I 0 I 0
I I
I I
I 0 I 0
I !
R'!lm
tl.
12
10
,
It
1
7
6
1 I 1
1
1 1apt I TAJ. INCR.
I
I
,-
3
2.
1
I
I
I POINt PLOT
,
, TABU1.A&
RELAtIVE ..,
.,
..
I
,-
I !?OINT
I PT.O'!
I
I
0
11 1 1+ Y"'INCUlG:NT
I
I
011
0
I
010
1
I
I
I
oI
1
I
1
I
I
, I
1 I
1.
.
.
3~7
I
POINT
~OT
YanAtm
3-7
I
I RESTOR!!
, DISPUl'
I REGISTER
Dill
I
I
010
~
, t ASSOt-un:
I-
I
010
3"'8
I,
I 0 I + l'--f..ARGIN
REGISTER
PRESENT X OR Y MARGIN POSITION
L.'1R
15
14
13
12
10
11
9
8
7
6
PDR
5
4
3
2
1
0
PIXEL
DATA
REGISTER
GRAY LEVEL BItS
15
14
13
12
10
11
9
8
.. 6
7
I
15
14
13
12
11
5
4
3
2
1
0
St.A.RT
.I
I
SXl-3
X ADDRESS
X
REGISTER
10
9
8
7
SY1-3
6
5
4
3
2
1
0
ST.A.RT
Y
REGISTER
Y ADDRESS
15
LNl-3
5
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NUMBER OF LINES PER SECTOR
0
LINE
REGISTER
A-23
(
IS
Table A.,.3.
Graphic Controller Register Format Summary ( Cent)
14
11
13
12
-
I.
STAl-3 I
I_-
10
7
8
9
!
I
I
I
6
5
I
r
I
I.• I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
CHANGE ENABLE
3
1
2
1-1
I
~
4
I
I
I
I
r
0
'-I STATUS
I
I
1
1
I
I
I
MEM.
I
I
REGISTER
(
SELECT, ENABLE
I
I
SELECT AlB
CURSOR ENABLE
CURSOR BLINK ENABLE
(
-',
".~-~;
,
"
.:S
15
14
13
11
12
10
7
8
9
I
5
4
3
2.
1
I"
0
"
I
XCR
6
X
CURSOR
ADDRESS
X CURSOR ADDRESS
I.
SIGN OV1i'L
SIGN
15
yca
14
13
12
10
11
7
8
9
5
6
4
3
2
1
0
i'
,"
I
I
y
I
I
Y CURSOR ADDRESS
CURSOR
ADDRESS
SIGN OVFL
SIGN
15
1
DL1
1
I
14
13
12-
11
10
9
0
0
I
I
0"
0
I
I
8
I
I
7
6
0
0
I
0
I
I
-
5
I
I
I
4
3
2
1
0
I
LINE INCREMENT
-I LINE
I INCREMENT
I REGISTER
[
....,--
I
I
I
L
I
I
(,
('
(
A-24
(
.
Graphic Controller Register Format Summary ( Cont)
Table
15
14
11
13
10
9
8
6
7
5
4
3
2
1
,
,
I
I
I
I
I
I,
I
!
I
-
I
I
I
1
I
I.
I
I
I
I
I
I
I
,
I
I
I
I
I
1
",
-,
11
I
SCF
I
0
I
RESERVED FOR
- . HARDWARE
-
,
SYSTEM
CONFIGURATION
REGISTER
BITS PER PIXEL
MEMORY FIELD SIZE
NUMBER OF VIDEO CONTROLLERS
SCREEN RESOLUTION
RESERVED FOR HARDWARE
BLINI{ STATUS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
.0
CHARACTER
CFR
VALUE
FONT
REGISTER
A-25
15
Table A...4.
Serial Interface Register Format Summary
13
10
14
11
12
I
I
l
I
II
I
I
I
I
I
I
I
I
I
I
I
I
!
I
I
I
I
I
I
I
I
I
I . ' *CAR,R.
, ,
I
I
I
I
I
I
I
I
I
I
,
I
I
I
I
I
I
I
-
4
5
3
I
.1,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
,
I
I
I
I
I.
I
I
I
I
-
!
I
I
RECEIVE
STATUS
REGISTER n
'-
I
I
RDR. ENBL
, _ *DATA. TEBM ROY
,
-
I
,
-
I.
'-
,I
I
I
I
0
1
2
*REQ .TO SEND
(I
RCVRINTRP'1' ENBL
RCVa DONE
*DAtA SET ROY
*CLEAR TO SEND
1-
~
I
I
6
7
I
I
I"
I
RSRn
8
9
(
*lUNG IND
*Used on full RS...232C interface ports 1, 5 and 9
15
12
13
14
11
10
9
8
7
I
6
.
I
I
I
I
I
I
I
,15
-
0
RECEIVE
DA.TA
BUFFER n
- .....
~
(.
*p ARI TY ERRO R
(,
OVERRUN ERRO R
13
12
11
10
9
8
7
6
,
I
I
I
I
-
I
. I
3
,
2
.
I
I
-
I
4
5
I
TSRn
A-26
1
ERROR
14
,
2
RECEIVE DATA
I..
-
I
I
3
,
I
ROEn
4
5
I
I i':
XMTR IN'l'RP ENBL
XMTR lU>Y
1
I
0
I'
.
I TRANSMIT
I STATUS
I .REGIStER
(
n
(
(
,'".
I
I '.~
Table A-4.
15
14
13
12
Serial
11
10
InterfaceRegiste~
9
8
7
6
5
Format Summary (Cont)
4
TRliliSMIT DATA
TDBn
NOtE:
3
2
1
o
TRANSMIT
DATA
BUFFER n
Unidentified bits not used.
,-
'..
'
L
.
A-27
J~
Table A-5.
15
14
12
13
11
(
Parallel Interface Register Format Summary
9
10
8
7
5
6
4
3
1
2
0
TWO's COHPLEMENT OF DM..<\. WORD COUNT
WCRn
TtlORD
(
COUNT
REGISTER n
r. .
.".
~
__ • .1
15
MAB.n
13
14
12
1-'"
I
I
11
10
9
8
7
5
6
4
3
2
~
14
12
13
11
10
9
8
7
5
6
4
3
I
-
I
I
INPUT INntP
ENBL
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
......'
INPUT WORD REQ _
SP. <\R.E
.
INPU'l' NO. 2
-
I
I
I
I
I
I
I
I
I
I
ATTEN INTR?T ENBL
I
I
I
I
I
I
I
I
I
I
I
I
_I
to
ATTEN NO. Z
-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Al'TEN NO. I
-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I·
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1
2
-I
STRn
0
I
I
STARTING ADDRESS FOR DMA OPERATION
15
INPUT
NOT
READY
1
0
I MEMORY
I ADDRESS
I REGISTER n
0
I
i
I
!
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
i
I
I
I
-
I
I
I
I
I
I
I
I
I
-
,
r
I
I
STATUS
REGISTER
I
I
I
I
I
rI
-
SPARE INPUT
NO. I
I
I
I
I
I
ADRS BIT 17
DMA
I/O MODE
-
-
Ii
ADRS BIT 16
-
IDRn/
OnRn
A-28
1-
14
j
13
12
11
10
9
8
7
6
5
4
3
2
1
I
I
0
INPUT/
UlPUT OR OUTPUT DATA
I
OUTPUT DATA
I______________________~--------------------- REGISTER n
:-~
I
f
f'
WORD COUN! rf. 0
15
r
I
DMA COMPL
I
OUTPUT WORD RCVD
I
I
OUTPUT INTR?T ENBL
I
I
I_ . OUTPUT CONT
'-
(
I
I
I
f
Ii
I
I
Table A-6.
Register Designations and Address Assignments
REGISTER
DEVICE
DISPLAY PROCESSOR
Processor Sta.tus Word
MNEMONIC
ADDRESS
PSW
177776
Reserved
"'~r
ROM AND STATUS LOGIC
SERIAL INTERFACE PORT
a-bit switch register
SWT
TTY
tTY
TTY
Tn
TTYRSR
TTYRDB
T'1'YTSR
TT'iTDB
Receive Status Register
Receive Data Buffer
Transmit Status Register
Transmit Data Buffer
1177760
thru
1177772
177774
I-
177560
177562
177564
177566
Word Count RegiSter 1
Memory Address Register 1
Status Register 1
Input/Output Data Register 1
waCl
MARl
IDRl/ODRl
172410
172412
172414
172416
PARALLEL INTERFACE
C.ARD NO. 2 (OPTIONAL)
Word Count Register 2
Memory Address Register 2
Status Register 2.
Input/Output Datil. Register 2
WCR2
MAR2
STR2
IDR2/0DR2
172430
172432172434
172436
MULTIPORT SERIAL
INTERFACE CARD NO. 1
Port No. 1 (Host Computer)
Receive Status Register 1
Receive Data Buffer 1
Transmit Status Register 1
Transmit Data Buffer 1
Port No. 2 (Keyboard No. 3 or PED No.6)
Receive Status Register 2
Receive Data Buffer 2
Transmit Status Register 2
Transmit Data Buffer 2
Port No. 3 (Keyboard No~ 1 or PED No.8)
Receive Status Register 3
Receive Data Buffer 3
Transmit Status Register 3
Transmit Data Buffer 3
Port No. 4 (Keyboard No. 8 or PED No.1)
Receive Status Register 4
Receive Data Buffer 4
Transmit Status Register 4
Transmit Data Buffer 4
RSRI
RDB1
TSR1
!DBl
176500
176502
176504
176506
RSR2
RDB2
TSR2
TDBZ
176510
176512
176514
176516
RSR3
RDB3
TSR3
TOB3
176520
176522
176524
176526
RSR4
RDB4
TSR4
TDB4
176530
176532
176534
176536
RSR5
ROBS
TSR5
TDB5
176540
176542
176544
176546
PARALLEL INTERFACE
CARD NO. 1 (OPTIONAL)
MULTIPORT SERIAL
INTERFACE CARD NO. 2
(OPTIONAL)
Port No. 5 (unused)
Receive Status Register 5
Receive Data Buffer 5
Transmit Status Register 5
Transmit Data Buffer 5
STRl
A-29
I
I' -;
"1?.
Table A-6.
ReglsterDesignations and Address Assignments (Cant)
REGISTER
DEVICE
MNEMONIC
ADDRESS
I, ~J
'"",,
'J MULl'IPOR'l' S!lUAL.
" INTER.FACE CARP NO. 2
- (OPTIONAL) (Cant)
MULtIPORT SEnAL
INttRFACE CARD NO. 3
Pot't No. 6 (Keyboa.rd No. 6 or PED No.3)
Re~eive Status Register 6
R5R6
Rece:1 va Da ta Buf fa r 6 '
ROB6
Transmt Status Register 6
TSa6
l'DB6
'transm1 t Da ta :auf £a r 6
Port No. 7 (Keyboard No. 2 orPED No. 7)
Receive Status Register 7
RSR7
WB7
Receive Data Buffer 7
1'51\7
'transmit Status Register 7
'TDB7
'tran.sflit Data Buffer 7 .
Port No. a (Keyboard No~7 or PED No. 2)
Receive Status Register 8
aSR8
Receive Data. Buffer 8
ROBS
'l'ransflit Status Register 8
TSa8
Transmit Data Buffer 8
l'DB8
Port No. 9 (Keyboard No.4 or PED No.5)
Receive Status Register 9
Receive Data ,Buffer 9
Transmit: Status Register 9
Transtlli t Data Bu,f£er9
Port No. 10 (Keyboard No. 5 or PED No.4)
Reee:f,ve Status 'R.eg~ster 10
Receive Data BuffarlO,
_
Transmi tS tatusRegis ter 10
'transm1t Data Buffer 10
Port
MULTIPaRT
SERI.~
Port No. 13 (Spare)
!~TERFACE
CAaD NO. 4
Receive Status ltegister 13
Receive Data Buffer 13
'trans'Q1it Status Register 13
'transtn1t Data Buffer 13
Port No. 14 (Spare)
Receive Status Register 14
Receive Data Buffer 14
'transmit Status Register 14
Transmit Data Buffer 14
A-30
176556
176566
176570
176572
176574
176576
176600
RDa9
176602
'tSR9
176604
m89
176606
R.SR10
176610
ROBI0
176612
TSRIO
176614
176616
aSRll
176620
RD811
176622
TSR11
176624
176626
l'D811
l~,
176562
176564
RSR9
TOBIO
I 'T}
176560
No. 11 (Spare)
B.eceive Status B.egister 11
lteceive De. t NO. 1
'.
I
Tn:
PARALLEL INUU ACE
4
10
14
24
30
34
60
64
ROM AND STATUS LOGIC Co\BDt
GRAPHIC CON'.l:ROLLER
T'R.A.P ADORES S
I
I
I
I
.,
--1
f
Port 5 ... (unused)
'!nput
Output
Port 6 - Keyboard No. 6 or PED No. :3
Input
Output
Port 7 - Keyboard No. 2 or PED No. 7
Input
Output
Port 8"- Keyboard No.7 or PED No.2
Input
Output
~.
300
304
310
314
320
324
,I'
I ,~,:
I:
."
340
344
f
l
350
354
Jt
330
334
-.~
360
364
370
374
I
I:
.1\-34
I
Table A-7.
Display Processor Trap
MULTIPORT SERIAL
INTERFACE CARD NO. 3
.-......
·MULTIPORT SERIAL
INTERFACE CARD NO. 4
;
I
_
d .......
(Cont)
INTERRUPT
INTERRUPTION DEVICE
.... _'.
Addres~es
Port 9 - Keyboard No. 4 or PED No. S
Input
Output
Port 10 - Keyboard No • S or PED No. 4
Input
Output
Port 11 - Spare
Input
Output
Port 12 ... Spare
Input
Output
Port 13 Input
Output
Port 14 Input
Output
Port 15 Input
Output
Port 16 Input
Output
TR.l\.P ADDRESS
400
404
410
414
420
424
430
434
Spare
440
444
Spare
450
454
Spare
460
464
Spare
470
474
._,1
.,.J
A-35
Ii
",~
I
"1
,]
.,:.1
'~'
I.
,
I
Material formerly on pages A... 36 through A... 66 has been deleted.
"
1
j
I -'i
't,
I
•• w ••• )
t,'
f 1'1
I
{
.._)
v
~
II
I
I
I
~.
A-36
Change 1
[
.,..;...i.
A-67
Table A-lO.
Multipart Seri,al Interf
14&
006
MI4
015
005
001
IIIl2
143
003
1413
Olli
MIG
MIl
000
Mil
OtJ
1412
Ot4
Ml
01-2
M2
~ NOINTERRUPTORCODEGENERATEO
STANDARD KEY
MARKINoSHOWN
ON LEFT Of KEY
l
. . ,C,
CODES GENERATED
BYItA£Ii KEY SHOWN
~
JU
20,,3,
203 '
f~~~~~TOF
K£Y
CODE
NDRMA~
SHlfTEDCODE
CONTiIOL COOE
Non
A§l;!llll§.
MOST KEYS GENERATE TUREE CODE$
DEPENDING ON THE POSITION Of
THE SHIFT AND CONTROL KEYS.
SOME KEYS GENERATE ONE CODE
ONLY. NOT AFfECTED BY SHIfT
OR CONTROL KEYS.
CODE MARKINGS DO NOT
APPEAR ON KEY CAPS
iTANDARD KEY
MARKINUS'"OWN
ABOVE CODE
....
COOl< OEN£RAUD
BY EACH KEY SHOWN
AT BOTTOM OF KEY
tocTALI
CONTROL. SHlfnD,"
NORMAL CODES s _
:r
"'-I
.....
Figure A-2.
Model 5784 Keyboard Layout and Code Assignments
..:' .r'.'
007
M1
~ MOOIFIES ASCII KEY CODES
~?'.,:
,1.,
Table Af13.
I
I
I
CHAR.
CODE
DEC.
NUL
000
o
SOH
001
1
STX
002
ETX.
OCTAL
10=
DEC.
ocf..u:---I
SHF
I
10=
DEC.
I
li-~
7-Bit ASCII Code
OCTAL
SHF
OCTAL
I
I
I
CHAR.
CODE
DEC.
---.--~~--~----~~--~----~~--~~--~~--~~--~~.--~~---O~'
0
US
037
31
17400
7936
400
2.'56
SF
040
32
20000
8192
2
1000
512
041
33
20400
8448
003
3
1400
768
042
34
21000
8960
EO'!
004
4
2000
1024
II
043
35
21400
8960
ENQ
ACK
BEL
BS
HI
LF
005
5
2400
1280
$
044
36
22000
9216
006
6
3000
1536
%
045
37
22400
9472
007
7
3400
1792
&
046
38
23000
9728
010
8
4000
2048
047
39
23400
9984
011
9
4400
·2304
(
050
40
24000
10240
012
10
5000
2560
)
051
41
24400
10496
VT
013
11
5400
2816
if
052
42
25000
10752
FF
CR
SO
014
12
6000
3072
053
43
25400
11008
015
13
6400
3328
0.54
44
26000
11264
016
14
7000
. 3584
I +
I
I -
055
45
26400
11520
S!
017
15
7400
3840
056
46
27000
11776
OLE
020
1~-
10000
4096
I
057
'+7
27400
12032
DCl
021
17
10400
4352
o
060
48
30000
12288
OC2.
022
18
11000
4608
1
061
49
30400
12544
DC3
023
19
11400
4864
2.
062
50
31000
12800
OC4
024
12000
5120
13056
12400
5376
063
064
31400
52
32000
13312
SYN
025
026
3
4
51
NAK
20
21
22
13000
5632
5
065
53
32400
13568
ETB
027
23
13400
5888
6
066
S4
33000
13824
C..lli
030
24
14000
. 6144
7
067
55
33400
14080
EM
25
14400
6400
8
070
56
34000
14336
SUB
031
032
26
15000
6656
9
071
57
34400
14592
ESC
033
27
15400
6912
072
58
35000
14848
FS
034
28
16000
7168
073
S9
35400
15104
GS
035
29
16400
7424
014
60
36000
15360
RS
036
30
17000
7680
075
61
36400
15616
I <
I ""
f·-· '· ,'
(;
I,
I,
I
f
I
r
I
I'
I
I
I
I
I
I
Table A-13.
7-Bit ASCII Code (Cont)
I
OCTAL
10=
DEC.
>
076
62
?
017
15872
16128
@
100
101
102
63
64
65
66
67
37000
37400
40000
40400
16384
16640
I A
I
I ,
41000
16896
a
A
B
F
G
101
71
H
110
!
III
J
112
72
73
74
K
113
D
E
70
75
76
'114
M
115
116
17
117
120
121
79
80
o
p
Q
R
S
T
122
123
124
V
125
126
W
127
X
130
Y
131
Z
132
U
\
133
134
41400 17152
42000 17408
42400 17664
43000 17920
68
69
L
N
"
SHE'
103
104
105
106
C
'J
OCTAL
DEC.
CHAR.
','.i'
I
I
OCTAL
CODE
78
I
43400
44000
44400
45000
45400
46000
46400
47000
18176
18432
1868,8
18944
19200
19456
19712
19968
CHAR.
b ,',
c
d
e
f
g
I
h
i
j
I k
I 1
I m
20224 I n
20480 I 0
20736 I p
20992 I q
21248 I r
21504 I s
81
82
47400
50000
50400
51000
83
84
85
86
51400
52000
52400
53000
21760
22016
87
88
89
53400
54000
54400
22272
22528
22784
90
91
55000
55400
56000
23040
23296
23552
92
I
I
I
I
OCTAL
t
I
I
I
I
I
u
SHE'
CODE
DEC.
10=
135
136
137
140
141
93
94
56400
23808-,
57000
57400
60000
60400
24064
24320
24576
24832-
100
101
61000
61400
62000
62400
25088
25344
25600
25856
102
103
104
105
63000
63400
64000
64400
26112
106
107
108
109
65000
65400
66000
142
143
144
145
146
147
150
151
153
153
154
155
156
157
160
161
162
163
164
165
v
w
x
166
167
170
y
171
z
172
173
95
96
97
98
~9
110
111
112
113
114
115
116
117
118
119
120
121
122
123
66400
67000
67400
70000
70400
DEC.
26368
26624
26880
27136
27392
27648
27904
71000
71400
28160
28416
28672
28928
29184
29440
72000
72400
29696
29952
73000
73400
74000
74400
75000
75400
30208
30464
30720
30976
31232
31488
,
L-J
A-73
r
,~
'.
Table. A-l3.
CHAR.
7-Bit ASCII Code. (Cant)
OCTAL
SHF
OCT.AL
CODE
DEC.
10=
DEC.
174
124
31744
175
125
76000
76400
-
32000
CHAR.
DEL
OCTAL
SHF
OCT.AL
CODE
DEC.
10=
176
126
77000
177
127
77400
DEC.
32256
32512
f
f,
r
(
,
-,
I'"
f
I
I
I
I
I
I
I"
,
I
(
A-74
I
I
.-
Table A-14.
GR..L\PHlC 8 Registers
I
MEMORY
I/O
I
I/O
I
I_______________RE~G~I~ST_E~R______________~-AD~D-RE~W~S~S--~~RE~AD~~I---WR~IT~E~___ I
I
I
I
I
SENSE WORD (SENS)
177660
Yes
I
No
I
I
I
I
MASK REGISTER (MKR)
177662
Yes
I
Yes
I
I
I
I
I
I
STACK POINTER (DSP)
165000
Yes
I
'*
I
I
I
I
I
GENERAL PURFOSE REGISTER (DRO)
165002
Yes
I
*
I
I
I
I
I
GENERAL PURPOSE REGISTER (DR1)
165004
Yes
I
*
I
I
I
I
I
PROGRAM COUNTER (DPC)
165006
Yes
I
Yes
I
I
I
I
I
DISPLAY INSTRUCTION REGISTER (DlR)
165010
Yes
I
'*
I
I
I
I
I
TEXT INCREMENT REGISTER (DTt)
165012
Yes
I
I
DISPLAY PARAMETER REGISTER (D?R)
165014
Yes
I
BANK REGISTER (PGR)
165014
**
DISPLAY Z REGISTER (DZR)
165016
Yes
X REGISTER CDXR)
165020
Yes
Y REGISTER (DYR)
165022
Yes
!.
I
I
I
I
I
I
I
I
•• _.J
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
CHARACTER REGISTER (DCR)
165024
Yes·1
(Optional)
165026
Yes
Y CONIC REGISTER (KYR) (Optional)
165030
Yes
GENERAL PURPOSE REGISTER (DRZ)
165032
Yes
GENERAL PURFOSE REGISTER (DR3)
165034
Yes
X
CONI~
REGISTER
(~~)
I
I
I
I
I
I
I
I
*
'*
Yes
*
'*
*
'*
'*
*
*
'*
*These registers are written by refresh commands and read by programmed
data transfers.
**The 2 bit Bank Register is read as bits 14 and 15 of the DPR.
***These registers are written by the I/O and refresh commands.
#A write to FUNC register while the digital graphic controller is
running will cause an error trap through address 4 (error trap).
I
I
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I
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A-75
r
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~,;
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Table A-14.
:,', 1 ':],!
GRAPHIC 8 Registers (Cont)
,
..'
::
,
,
MEMORY
ADDRESS
"FUNCTION CqNTROL CONTINUE (FUNe)
165036
FUNCTION COmaOL STOl?(FUNS)
165040 ..
E~ORREGISnR
165312
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170
READ
No
No
I
(EiR)
I
YeS
I
I
I
I
I
I
I
I
r/o
WRITE
Yes
Yes
Yes
**-kThese registers are W't'itten by the .1/0 and refreshcom.mands. "
/FA write to.FUNe register while the digital gl'aphiccontt'olleris
rurminswill cause an en'or trap throushaddress 4 }error trap). ,
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A-76
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Table A-14.
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SERIAL
INTERFACE
(SINGU
PORT)
- 1-
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SERIAL
INTERFACE
(4 PORTS)
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GRAPHICS~
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+ 1.5 u.see.1 pixel
Charaeter Wdte Times (SDla.tJ, Size)
'"
A.
O"erh~
t•
2.
B.
CttAR instruc: tion
'!'It IT ins true don
"L" Character (15 pixels)
"E" Chataeeer (24 pixels)
4.5 u.see
8.4 usee
. 37.2 usee (5 2 7)
38.7 usee (5 x 7)
46.2 usee (7 x 9)
52 • 2 usee (7 x 9)
Data Move
Configuration:
1.
a bits/pixel
2.
4 bits/pixel
Point Plots
PPTA
PP'l'R
PPYA/PPYR
PPLR
3.9 usee/ptxel
S.1 usee/ pixel
512 2
-
2.4 usee/pu$!
2.7 usee/pixel
2.1 usee/pixel
3.0 usee/pixel
2.1 usee/ pixel
2.7 usee/pixel
1 • 8 useel pix el
2.7 usee/piXel
PolZ.klon Fill
FLPG
600 nseelpiJc:el average.
Range i$ 100 nsl pixel
to 1.0 us/pixel depending on the length and
position of the horizontal pixel lines
composing the fill.
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Conics
LDU. ·}
DRKY
2.5 useel pixel
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APPENDIX B
GRAPHIC 8 MACRO DESCRIPTIONS
B-I.
GENERAL
This appendix describes the GRAPHIC 8 display macros that have been developed
by Sanders for Software Engineers who use the MACRO-II assembly language for their
applications programs. Table B-I lists the macros in alphabetical order. Table B-2
describes the macros and defines the arguments accepted by each. Table B-3 shows
the program structures for two typical refresh files that use the macros.
The following conventions are used in table B-2 to define macro arguments.
1.
All numbers are octal unless otherwise specified.
2.
Lower case letters indicate variable argu~ents. With the exception of the
following, each letter represents a single octal digit (leading zeros are not
required for arguments shorter than the specified field):
,--
a.
"a" and "b" each represents a single ASCII character.
b.
"ars" represents a specific argument identified in the macro
description.
c.
"label" represents a label assigned by the aplications programmer or
an absolute or relative value.
d.
"character string" represents any string of ASCII characters as
determined by the applications programmer.
,
3.
Upper case letters indicate specific arguments as discussed in the macro
descriptions.
NOTES
1.
Standard graphic controller instructions
referenced in this appendix are described in
detail in Section 3. Coordinate converter
instructions are described in Sanders publication
79-0350.
2.
All register mnemonics listed in table A-6 are
defined in the GRAPHIC 8 macros and may be used as
arguments for MACRO-II instructions.
B-1
(
3.
The following labels are used within the GRAPHIC 8
macros and lXlust not be duplicated in any user
written program that employs these macros:
(
-
"
:
,"-'
.... ,
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'.
AR.G. OK
CR.
DISLOP
D2R.
nza. ... '
TI.
'IMP $
TX!.
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B-2
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Table B-I.
MACRO
FUNCTION
ADD!
ADR
AMV"
CALL (E)
CALR (E)
CHAR
CIRCLE
CLRM
COLOR
CR
CRLF
DISEND
DISI}/"'T
DRKY
DRSR
DRXA
DRXR
DRYA
ORYR
ELLIPSE
ENTR
FILL
HREF
IN1T
IZPR
JMPM (E)
JMPR
.D!PZ
JPRZ
(E)
(E)
Jru1P (E)
JUMP (E)
LDOI
LDDP
LDOZ
LDKX
LDPD
LORI
LDSP
LDTI
(E)
LDXA
LDXR
LF
-..
LINK
MOLU
MODE
GRAPH1C 8 Display Macros
(E)
Add to display register immediate
Absolute draw
Absolute move
Call (Extended) subroutine
Call relative
Draw single character
Draw circle
Clear pixel memory
Select c.olor
Carriage return control character
Carriage return line feed control characters
Display end
Display initialize
Draw conic Y
Draw short relative
Draw X absolute
Draw X relative
Draw Y absolute
Draw Y relative
Draw ELLIPSE
Provide subroutine entry point
Fill a convex polygon
Halt a refresh
Initialize
Initialize the ramp generator (Graphic 7 only)
Jump and mark
Jump short relative
Jump (Extended) if display register 0 contents ~ 0
Jump relative i f display register 0 contents '1 0
Jump relative
Jump (Extended)
Load d"isplay register immediate
Load display parameter register
Load display Z register
Load conic X register
Load pL~el data register
Load device register immediate (Graphic 7 only)
Load (Extended) stack pointer
Load text and line increment registers
Load X absolute
Load X relative
Line feed control character
Synchronized linkage
Modify look-up table
Load mode register
B-3
(
Table B-1.
MACRO
MVPD
MVSR
MVXA
MVXR
HV'IA
MVYR
NEWL
NEWLR
NOOP
PPLR
PPTA
PPTR
PPYA
PPYR
RDR
RESD (E)
RL!NK
RMV
RnN (E:)
SAVD (E)
SE1'LF
SET'MRG
SETT!
5TX
TEXT
TXT
UPDT
WAT'E
GRAPH.IC 8 Display Macros (Cont)
r
FUNCtION
Move pixel cia ta
Move short relative
Move x: absolute
MO'ITe X relative
Move Y absolute
Move Y relative
New line
New line relati va
No operation
Point plot relative
Point plot tabular absolute
Point plot tabular relative
Point plot Y absolute
Poiu'!: plot Y relative
Relative draw
Restore d,isplay reg,iater
Relink.
Relative move
Return (Extended)
Save (Extended) display register
Set line feed
Set left Il'Jargin
Set t~t inerem.ent
Set left lX18.rgin coutrol character
Draw tabular character string
Draw two tabular characters
Upda te 'video controller register( s)
1;"Jait
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Table B-2.
£-IACRO CALL
Detailed Macro Descriptions
DESCRIPTION
ADDI r,nnnnnn
Inserts an ADDI (add to display register immediate)
instruction into the refresh file. Argument "r", which must
be "0" through "63", specifies one of the display registers
(DRO through DR63) of the digital graphic controller.
Argument "nnnnnn" spe,cities the value (-100000 to 77777) to be
added to the register.
ADR xxxx, yyyy
Causes an absolute draw to position X, Y by inserting two
instructions into the refresh file. The first is an LDXA
(load X absolute) instruction with the X coordinate defined by
argument "xxxx". The second is a DYRA (draw Y absolute)
instruction with the Y coordinate defined by argument "Y11Y".
Both arguments can vary from -2000 to 1777.
AWl XX:lCt ,yyyy
Causes an absolute move to position X, Y by inserting two
instruction into the refresh file. The first is an tDX! (load
X absolute) instruction with the X coordinate defined by
argument "xx:ct". The second is a MVYA (move Y absolute)
instruction with the Y coordinate defined by argument "Y1YY".
Both arguments can vary from ... 2000 to 1777.
CALL label
Inserts a CALL (call subroutine) instruction into the refresh
file wi th the subroutine address - defined by argument
·'label;'. Argument "label" may define any even location in
memory bank O.
CALLE label, bank
Inserts a CALLE (call subroutine extended) instruction into
the refresh file with the subroutine address specified by the
combination of "bank" and "label". The subroutine address may
be any even address in memory.
CAtR (E) label
Inserts a CALR (E), call relative, instruction into the
refresh file with the subroutine address specified by argument
"label". Argument "label" may define any even location in
memory bank O.
CHAR a.,
Inserts a CHAR (draw single character) into the refresh file.
Argument "a" specifies· the ASCII character to be drawn. If
the character to be drawn is a space, it must be enclosed in
angle brackets: < >. If argument "BOO is absent, the
character will be displayed steadily; if argument "En is
present, the character will blink. No tabular text increment
move is made following the drawing of the character. If "0"
argument is present, the argument "a" is interpreted as an
octal equivalent number. If .. s .. argument is present, a shift
out is applied to argument
"Ia~t.
B-S
Table B-2.
MACRO CALL
Detailed Macro Descriptions (Cont)
DESCRIPTION
------------"------------------------------------------
LDDZ (con t:)
Octal
BR3
BR4
BR5
BR6
BR7
Select
Select
Select
Select
Select
intensity
intensity
intensity
intensity
intensity
level
level
level
level
level
3
4
5
6
7 (brightest)
3
4
5
6
7
Inserts an LDKX (load conic X register) instruction into the
refresh file. Argument "q" specifies unblanking of quadrants
I (upper right) and III (lower left) as follows:
s
qlJ;adrants unblanked
o
neither
1
2
I
III
I and III
Argument "nnn" (which may vary from 0 to 777) specifies the
semi-axis dimension of an ellipse in terms of coordinates
along the X axis.
MODE mode
LDPD level
II
~1
Value
Description
LDKX q, nnn
i'
[I
Inserts a MODE (load mode register) instruction into the
refresh file. ..mode" .. 0 indicates normal mode. "m.ode"::t 1
indicates extended instruc tion !!lode. If "mode" is greater
than 1, no change in mode will be made.
Inserts an LDPD (load pixel data reg.ister) instruction into
the refresh file. Arg'Ulllent "level" which varies from 0 to 377
represents the gray level or color that is to be stored in the
FDR (pixel data register) and used a.s the intensity of the
pixels written by subsequent refresh instructions.
LDRI
Inserts an LDRI instruction (no operation for GRAPH!C 8).
LDSP nnnnno
Inserts an LDSP (load stack pointer) instruction into the
refresh file. Argument "nnnnnn" specifies the stack address
that is to be loaded into the graphic controller stack
pointer.
']1
[I
r;;l
i
If
{[
If
Il,!
(
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(
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B-12
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Table B-2.
MACRO CALL
)
t'etailed Macro Descriptions (Cont)
DESCRIPTION
L DS PE n nnnnn •ba nk.
Inserts an LDSPE (load stack pointer extended) into the
refresh file. The combination of "bank" and "nnnnnn"
specifies the address to be loaded onto the stack in two
successive words.
1DTI nn,11
Inserts an LDTI (load tex.t and line incremen-t register)
instruction into the refresh file. Argument "nn", which may
vary from 0 to 77, specifies the text increment to be used for
tabular characters contained in the arguments of TXT (draw two
tabular characters) and TEXT (draw tabular character string)
macros. Argument "11" which may vary from 0 to 77, specifies
the line increment to be used for the CR control character.
If both argume,nts "nn" and "11" are not present and increments
have previously been established, the established increments
will be used. If argument "II" is not present and an
increment has not previously been established, a default
increment of "II" :0 22. will be used.
1DXA nnnn
Inserts an LDX.A (load X absolute) instruction into the refre-sh
file. The argument "nnnn" which may vary from -2000 to 1777
defines the value or the x coordinate to be loaded in the
current X Position Register.
LDXR nnnn
Inserts an LDXR (load X relative) instruction into the refresh
file. The relative distance, in terms of coordinates, that is
to be added to the Current X Position Register is specified by
argument "nnnn". Argument "nnnn" may vary from -2000 to 1777.
LF
Inserts CHAR 012,0 (line feed) into the refresh file.
LINK label, I
Inserts a LINK (synchronized linkage) instruction into the
refresh file. The link address is speCified by argument
"label" • If argument "!" is absent, the link will be direct
(to the link address); if argument "!" is present, the link
will be :tnd! rect (to the address contained in the link
address). Direct links cannot be made to address higher than
77776. If argument "label" is absent, the LI~ instruction
inserted into the refresh file will specify a direct link to
address 170.
LINK label
If EIM = 1, then LINKE is used.
Note"!" is not allowed.
Change 1
B-13
I
Table B-2.
MACRO
.
DESCRIPTION
-
CALL
,
'
~IDLU
adr 1, banks, bytes,
vcnum, adr2, D
I
MVPD
adr ,bank, ix tiy,
fx,fy,D,a,b,c
~lVS R
xx, yy
TI1S data stored in sequential bytes starting at the GRAPHIC 8
memory address defined in the argumen t .. adrl" is used to
replace data in sequential bytes in the video controller
look-up table starting at the address defined in "ad r2" • T'ne
combination of bank and adrl is an absolute address if
argument "D" is absent. ad'rl is a relative address from the
program. couIlter if "D" is present. The video controller
selected is defined by the value 1-4 in the argument "vcnum"
and the number of bytes to be replaced is defined in the
a rgumell t "b yee s" •
Inserts an MVPD (move pixel data) instruction into the refresh
flle. If argument >Oa" ... nABS" the vertices are expressed as
abl$Olute coordinates if "a" ... "REL" the vertices are defined
by the deltas from the current X and Y position. If argument
"0" .. "FROMFM", the traus fer ·will be from mapping memory to
G1tA1'H.IC 8 memory. If "bOO - "TOPM", the transfer will be
from GRAPHIC 8 memory· to mapping memory. If argument "c" ...
"VER'!" the scan will be bot tom to top - left to right i f .. c.. ...
"ROa" the scan will be left to right - bottom to top.
If
argument "u" is present the displacement (in even bytes) to
•• APR" will be calculated and stored in the address word. If
"0" is absent, the combination of "bank" and "ADR" will be
stored. "ix" and "1y" indicate the initial va!t;tes for X and
Y,respectively. .
<.NOaOTATE.CSO>
1%
toop
tDTI
.,l,,';
AGAIN:
o
o
WAT!
i
1-- ,
:...
IZPB.
LDXA
b!V!A
,-r
I1BEGIN,SP
@#FUNS
CUt
BIt #20, @#SENS BEQ HUT
MOV
"
30
-.
;BEGIN ASSEMBLY
; AT ADDRESS 2000
iSAVE SPACE FOR DISPLAY PROCESSOR SUCK
jct!AR PROCESSOR BUS
:LOAD DISPLAY PROCESSOR STACK POINTER
:HALT GRAPHIC CONTROLLER
;WAIT FOR !W.T
;START GRAPRIC CONTaoLLER
;DISPLAY PROCESSOR WAIT
;WAIT LOOP
iSET Z PAlW!!i:TERS
;SET P PAlW!ETERS
;SET TEXT INClI.~NT TO 12
:INITIALIZE GUlHIC CONTROLL!lI.
;MOV! caT BEAMeS)
; TO CLvrER.
iWAIT
SODY
or
USER
WIttEN
.•
..,..-
DISPLAy
PROGL\M
GOES
liEU
-'
AGAIN
BeGIN
;SHOW THE PICTURE AGAIN
j
iSAMPLi PROGR.AM NO.2. A SIMPU: DRIVER, USING THE DISINT
; AND DISENO MACaoS, WITH A PLACE FOR DISPLAY INSTltUCTIONS.
;
•TITLE
• SB1'TL
SAMFL%
SAMP!.% DRIVEl.
\""
•ASECT
,-2000
BEGIN:
BiGIN ASSEMBLY
, AT ADDUSS 2000
;SAVE SPACE FOR DISPLAY PROCESSOR STACK
;CLEAR PROCESSOR BUS
JLOAD DISPLAY PROCESSOR STACK t'OINTER
;SET PARAMETERS AND START GRAPHIC CONTROLLER
j
.BLKW-
30
RESET
MOV
i!BiGIN, SP
DIS IN!
BODY
OF
USER
IJRITTEN
DISPLAY
l?ROGRAM
GOES
liERE
o ISEND
.END
BEGIN
,SHOW THE PICTURE AGAIN
B-19/B-20
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"APPENDIX C
GeP PROGRAMMING CAUTIONS
C-l •. When Gep is initialized the command header error detection is disabled.
Normally, the user should send an 1M message to activate error detection.
NOTE
I.:
All previously developedGCP programs should still
tun with Gel'.
,r·
',.:
C-2.
No user refresh programs should start below address 3000 (octal).
NOT!
Any previously developed GCl' prog1;'am should still
run ~ith GCl' provided that the user refresh
program doesn't start below address 3000.
C-3. When ~riting refresh programs, the user should ensure that the 32-word depth
or limit of the graphic controller stack. is not exceeded.
C-4. When MU, SU, and GU messages are sent from the host to GCl', the user should
ensure that the words counts associated with these messages are correct •
.. .J
C-l/C-2
I ..
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Name: __________________________________
CalCom~ Equipment
Company:~
______________________________
Address: _______- - -_ _ _ _ _ _ _ __
------------
."..
P3rt N1inber
____________
,...__
SO'ftwa~/Firmware
System _ _ _ _ _ _ _ __
Venio'l _______....;.._ _ _ _ _ _ _ __
TelePhone: ....[__.....]_ _ _ _ _ _ _ _ _ __
Host ccmputer______________
Date! _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Host OPann:in9 system _ _ _ _ _ Venion _ _ __
Host-Vistagraphtc interface _______......_ __
My problem is: hardware:J so'ftware
Oescription of prociem (0; suggestion for improvement)':
,,
f"
.•
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Related tech manual number ___________
, .J
L...;3
firmwa·re Cl manual
CJ
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'THE INTENT AND PURPOSE OFTHIS PUBllCAT10N ISTO PROVID!$ACCURATE
AND M£:;ANINGFUL INFORMATION TO SUPPOR"r EQUIPMENT"MANUFACTUREO BY CALCOMP/SANDERS. YOUR COMMENTS AND SUGGEST1.ONS
ARE REQUESTED.
PLEASE USE THE FORM ON THE REVERSE saoe TO REPORT ANY PROBLEMS
YOU HAVE HAD WITH THIS PUBLICATiON ORTHS EQUIPMENT IT DESCRIBes.
---- -- - - -- - ------------- FOI..O
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FIRST CLASS
PERMIT NO. 568
NASHUA, N.H.
BUSINESS REPLY MAIL
NO POSTAGE STAMP NECeSSARY IF MAiLSD IN THE UNITED STATES
.....-
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CalComp
Display Products Division
Daniel Webster Highway, South
P.O. Sox 868
Nashua, NH 03061
mtt.
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·-1
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