HD6301_HD6303_Series_Handbook_1989 HD6301 HD6303 Series Handbook 1989
User Manual: HD6301_HD6303_Series_Handbook_1989
Open the PDF directly: View PDF 
.
Page Count: 1338
| Download | |
| Open PDF In Browser | View PDF |
-, .
jo,;-: ~ .
.'
;~':
,-.
" .
:..
.
HD6301 iHD6303 SERIES HANDBOOK
• USER'S MANUALS:
o
t!)
(1)
@
HD6301 V1 IHD6303R
HD63701V
HD6301XO/HD6303X/HD63701XO
HD6301 YO/HD6303Y IHD63701 YO
III SOFTWARE APPLICATION NOTES
til HARDWARE APPLICATION NOTES
II C LANGUAGE PROGRAMMING TECHNIOUES
III APPENDIX:
o
(£)
CD
#U07
HD6301 V IHD6303R Q and A
HD6301XO/HD6303X OSCILLATOR CIRCUIT
WIDE TEMPERATURE RANGE SPECIFICATIONS
-40°C to +85°C (J VERSION)
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without
notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in
any form, the whole or part of this document without Hitachi's permission.
3. Hitachi will not be held responsible for any damage to the user that may
result from accidents or any other reasons during operation of the user's
unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims
or other problems that may result from applications based on the examples
described herein.
5. No license is granted by implication or otherwise under any patents or
other rights of any third party or Hitachi, Ltd.
6.
ii
MEDICAL APPLICATIONS: Hitachi's products are not authorized for
use in MEDICAL APPLICATIONS without the written consent of the
appropriate officer of Hitachi's sales company. Such use includes, but is
not limited to, use in life support systems. Buyers of Hitachi's products are
requested to notify the relevant Hitachi sales offices when planning to use
the products in MEDICAL APPLICATIONS.
September 1989
©Copyright 1989, Hitachi America, Ltd.
Printed in U.S.A.
INDEX
Quick Reference Guide
Addressing Modes, CPU Architecture, and Instruction Set
HD6301 V1 /HD6303R User's Manual
HD63701 V User's Manual
HD6301X0!HD6303X1HD63701XO User's Manual
HD6301 YO/HD6303Y/HD63 701 YO User's Manual
Software Application Notes
Hardware Application Notes
C Language Programming 1echniques
APPENDIX:
HD6301 V11HD6303R Q and A-HD6301XO/HD6303X Oscillation Circuit
Wide 1emperature Range Specifications, -40°C to +85°C, (J Version)
Hitachi Sales Offices
Section 10, Page 1318
iii
I
~HITACHI
iv
TABLE OF CONTENTS
Section 1
Quick Reference Guide
Page
QUICK REFERENCE GUiDE ......................................... .
PACKAGE REFERENCE GUIDE ......... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 2
Addressing Modes, CPU Architecture, and Instruction Set
1.
ASSEMBLY LANGUAGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Page
17
1.1
Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
1.2
CPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
1.3
Instruction Set Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
Section 3
HD6301V1/HD6303R User's Manual
Page
Notice on HD6301 V1 and HD6303R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
126
1.
128
OVERViEW....................................................
1.1
Features of HD6301V1 ... '............... ......................
128
1.2
Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
128
1.3
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
129
INTERNAL ARCHITECTURE AND OPERATIONS......................
130
2.1
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
2.2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
135
2.
2.3
Registers ..................................... '. . . . . . . . . . . . . .
140
2.4
1/0 Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
142
2.5
Programmable Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
146
2.6
Serial Communication Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
150
2.7
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
157
2.8
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
159
2.9
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
161
2.10
Strobe Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
161
2.11
RAM Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
162
2.12
Low Power Consumption Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
163
2.13
TRAP Function ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
167
~HITACHI
v
3.
INSTRUCTIONS................................................
168
3.1
Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
168
3.2
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
170
3.3
Instryction Execution Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
175
3.4
System Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
181
4.
PIN ARRANGEMENT AND PACKAGE INFORMATION. . . . . . . . . . . . . . . . . .
183
5.
ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
186
6.
APPLICATIONS.................................................
191
6.1
Use of External Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
191
6.2
Standby Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
195
6.3
Address Trap, OP-Code Trap Application. . . . . . . . . . . . . . . . . . . . . . . . ..
198
6.4
Slow Memory Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
199
6.5
Interface to HN61256.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
200
6.6
Interface to the Realtime Clock (HD146818). . . . . . . . . . . . . . . . . . . . . . ..
205
6.7
Reference Data of Battery Service Life .............. . . . . . . . . . . . ..
208
PRECAUTIONS.................................................
209
7.1
Write-Only Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
209
7.2
Address Strobe (AS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
209
7.
7.3
Mode
o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
209
7.4
Trap Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
209
7.5
Power-on Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
211
7.6
Precaution to the Board Design of Oscillation Circuit . . . . . . . . . .. . . . ..
211
7.7
Application Note for High Speed System Design Using the HD6301V1 ..
212
APPENDIX
I.
EPROM on Package HD63P01 M1
218
II.
Program Development Procedure and Support System ............. .
226
III.
Q&A ..................................................... .
233
Section 4
HD63701 V User's Manual
1.
Page
OVERViEW ............................................... ;....
251
1.1
Features of HD63701VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
251
1.2
Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
251
1.3
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
252
~HITACHI
vi
2.
INTERNAL ARCHITECTURE ..................................... .
253
2.1
2.2
Mode Selection ............................................. .
Memory Map ............................................... .
2.3
CPU Registers .............................................. .
253
258
,263
2.4
Ports ......, ................................................ .
265
2.5
2.6
Timer ............................................. ; ....... .
Serial Communication Interface ................................ .
269
273
2.7
Interrupts .................................................. .
281
2.8
Reset ..................................................... .
283
2.9
2.10
Oscillator .................................................. .
Strobe Signals .............................................. .
285
286
2.11
RAM Control Register ........................................ .
287
2.12
Low Power Consumption Mode ................................. .
287
2.13
TRAP Function ............................................. .
292
3.
.EPROM (PROM) PROGRAMMING AND TECHNICAL SPECIFICATIONS .. .
293
3.1
3.2
PROM Mode ............................................... .
ProgramminglVerification ..................................... .
293
294
3.3
Erasure ................................................... .
3.4
On-Chip PROM Characteristics and Application ................... .
295
296
3.5
Instruction Set Overview ....................... : .............. .
3.6
Addressing Modes ........................................... .
300
300
3.7
3.8
Instruction Set .............................................. .
Instruction Execution Cycles ................................... .
302
307
3.9
System Flowchart ........................................... .
313
3.10
Pin Arrangement and Package Information ....................... .
315
3.11
Electrical Characteristics ...................................... .
316
APPLiCATIONS ................................................ .
322
4.
4.1
Use of External Expanded Mode ............................... .
322
4.2
Standby Mode .............................................. .
327
4.3
Address Trap, OP-Code Trap Application ......................... .
4.4
Slow Memory Interface ....................................... .
330
331
4.5
Interface to HN61256 ......................................... .
332
4.6
Interface to the Realtime Clock (HD146818) ....................... .
337
4.7
Reference Data of Battery Service Life .......................... .
340
5. PRECAUTIONS ................................................ .
5.1
Write Only Register .......................................... .
341
341
5.2
Address Strobe (AS) ......................................... .
341
5.3
5.4
Mode 0 .................................................... .
Trap Interrupt ............................................... .
341
341
~HITACHI
vii
5.5
Precaution to the Board Design of Oscillation Circuit . . . . . . . . . . . . . . . .
343
5.6
Application Note for High Speed System Design Using the HD63701VO.
343
5.7
Differences between HD6301V and HD63701V. . . . . . . . . . . . . . . . . . . ..
347
APPENDIX
I.
Support Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
353
II.
Q &A......................................................
355
Section 5
HD6301XO/HD6303X/HD63701XO User's Manual
1.
Page
OVERViEW....................................................
375
1.1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
375
1.2
Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
377
1.3
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
380
INTERNAL ARCHITECTURE AND OPERATION. . . . . . . . . . . . . . . . . . . . . ..
383
2.1
Operation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
383
2.2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
386
2.
2.3
Function Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
388
2.4
Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
393
2.5
RAM/Port 5 Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
397
CPU FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
399
3.
3.1
CPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .
399
3.2
Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
400
3.3
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .
402
3.4
CPU Instruction Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
408
3.5
Low Power Dissipation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
410
3.6
Trap Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
413
3.7
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
414
3.8
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
415
TIMER 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
418
4.1
Free-Running Counter (FRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
419
4.2
Output Compare Registers (OCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
419
4.3
Input Compare Register (ICR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
420
4.4
Timer Control/Status Register 1 (TCSR1). . . . . . . . . . . . . . . . . . . . . . . . ..
420
4.5
Timer Control/Status Register 2 (TCSR2). . . . . . . . . . . . . . . . . . . . . . . . ..
421
4.6
Timer Status Flags .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .
423
4.7
Precautions on Cleaning the OCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
423
4.
~HITACHI
viii
5.
TIMER 2 ...................................................... .
425
5.1
Timer 2 Upcounter (T2CNT) ................................... .
425
5.2
Timer Constant Register (TCONR) .............................. .
426
5.3
Timer Control/Status Register 3 (TCSR3) ......................... .
426
5.4
Timer Status Flags .......................................... .
428
SERIAL COMMUNICATIONS INTERFACE. .......................... .
429
6.
6.1
Initialization ................................................ .
429
6.2
Asynchronous Mode ......................................... .
430
6.3
Clock Synchronous Mode ..................................... .
431
6.4
Transmit/Receive Control Status Register (TRCSR) ................. .
433
6.5
Transmit Rate/Mode Control Register (RMCR) ..................... .
434
6.6
SCI Receiving Margin ........................................ .
438
6.7
Timer, SCI Status Flags ....................................... .
438
6.8
Precaution for Clock-Synchronous Serial Communication Interface .... .
439
7.
HD63701XO PROGRAMMABLE ROM (EPROM) ...................... .
441
7.1
Programming and Verification .................................. .
443
7.2
Erasing (Window Package) .................................... .
444
7.3
Characteristics and Applications ................................ .
444
8.
APPLICATIONS ................................................ .
447
8.1
HD6301XO or HD63701XO in Expanded Mode ..................... .
447
8.2
HD6301XO or HD63701XO in Single-Chip Mode ................... .
448
8.3
Timer Applications ........................................... .
448
8.4
SCI Applications ............................................ .
452
8.5
Lowering Operating Current ................................... .
454
8.6
Memory Ready Application .................................... .
457
8.7
Halt Application ............................................. .
458
8.8
RD, WR Application .......................................... .
459
8.9
LCD-II Interface Application ................................... .
460
8.10
Oscillation Board Design ...................................... .
461
APPENDIX I. ELECTRICAL CHARACTERISTICS ........................ .
463
APPENDIX II. INSTRUCTION EXECUTION CYCLES ...................... . 485
APPENDIX III. QUESTIONS AND ANSWERS ........................... .
491
111.1
Parallel Ports ............................................... .
491
111.2
Serial Ports ................................................ .
492
111.3
Timer/Counter .............................................. .
495
~HITACHI
ix
lilA
Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
497
111.5
Interrupt Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
500
111.6
Oscillation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
502
III. 7
Reset.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
502
111.8
Low Power Dissipation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
505
111.9
Software......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
507
111.10 Others.....................................................
508
APPENDIX IV. THE DIFFERENCES BETWEEN HD63701XO and HD6301XO . . .
509
APPENDIX V. PROGRAM DEVELOPMENT PROCEDURE
AND SUPPORT SySTEM....... .................... .....
510
Section 6
HD6301 YO/HD6303YIHD63701 YO User's Manual
1.
OVERViEW....................................................
519
1.1
Features ..... ;......... .....................................
519
1.2
Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
520
104
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
523
INTERNAL ARCHITECTURE AND OPERATION. . . . . . . . . . . . . . . . . . . . . ..
526
2.1
Operation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
526
2.2
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
527
2.3
Function Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
528
2.4
Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
531
2.5
RAM/Port 5 Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
543
2.6
Port 6 Control/Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
546
2.
3.
CPU FUNCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
548
3.1
CPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
548
3.2
Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
549
3.3
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
551
304
CPU Instruction Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
557
3.5
Low Power Dissipation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
559
3.6
Trap Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
562
3.7
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
563
3.8
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
564
4.
TIMER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
567
4.1
Free-Running Counter (FRG) . . . .. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .
568
4.2
Output Compare Registers (OCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
568
~HITACHI
x
Page
4.3
Input Compare Register (ICR) .................................. .
569
4.4
. Timer Control/Status Register 1 (TCSR1) ......................... .
569
4.5
Timer Control/Status Register 2 (TCSR2) ....................... , ..
570
4.6
Timer Status Flags .......................................... .
572
4.7
Precautions on Cleaning the OCF .............................. .
572
TIMER 2 ...................................................... .
574
5.1
Timer 2 Upcounter (T2CNT) ................................... .
574
5.2
Timer Constant Register (TCONR) ............ '.................. .
575
5.3
Timer Control/Status Register 3 (TCSR3) ......................... .
575
5.4
Timer Status Flags .......................................... .
576
5.5
Precaution for Toggle Pulse Function of HD6301YO/HD6303Y/
5.
HD63701YO Timer 2 ......................................... .
577
SERIAL COMMUNICATIONS INTERFACE. .......................... .
578
6.1
Initialization ................................................ .
578
6.2
Asynchronous Mode ......................................... .
579
6.3
Clock Synchronous Mode ..................................... .
580
6.4
Transmit/Receive Control Status Register (TRCSR) ................. .
582
6.5
Transmit Rate/Mode Control Register (RMCR) ..................... .
583
6.6
SCI Receiving Margin ........................................ .
586
6.7
SCI Status Flags ............................................ .
587
6.8
Precaution for Clock-Synchronous Serial Communication Interface .... .
588
HD63701Y0 Programming ROM (EPROM) ........................... .
589
Programming and Verification .................................. .
590
6.
7.
7.1
7.2
Erasing (Window Package) .................................... .
591
7.3
Characteristics and Applications ................................ .
591
APPLICATIONS ................................................ .
593
HD6301 YO in Expanded Mode ................................. .
593
8.2
HD6301 YO in Single-Chip Mode ................................ .
594
8.3
Timer Applications ........................................... .
594
8.4
SCI Applications ............................................ .
598
8.5
Lowering Operating Current ................................... .
600
603
8.
8.1
8.6
Memory Ready Application .................................... .
8.7
Halt Application ............................................. .
604
8.8
RD, WR Application .......................................... .
605
8.9
LCD-II Interface Application ................................... .
605
8.10
Oscillation Circuit Board Design ................................ .
606
~HITACHI
xi
APPENDIX I. ELECTRICAL CHARACTERISTICS ........................ ,
608
APPENDIX II. INSTRUCTION EXECUTION CYCLES . . . . . . . . . . . . . . . . . . . . ..
630
APPENDIX III. QUESTIONS AND ANSWERS . . . . . . . . . . . . . . . . . . . . . . . . . . ..
636
111.1
parallel Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
636
111.2
Serial Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
639
111.3
Timer/Counter.......................................... . . . ..
644
111.4
Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
647
111.5
Interrupt Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
650
111.6
Oscillation Circuit .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
653
111.7
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
653
111.8
Low Power Dissipation Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ...
657
111.9
Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
660
111.10 Others.....................................................
661
APPENDIX IV. THE DIFFERENCES BETWEEN HD63701YO and HD6301Y0 ...
663
APPENDIX V. PROGRAM DEVELOPMENT PROCEDURE AND SUPPORT
SySTEM..................... .....................................
664
V.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
664
V.2
Single Chip Microcomputer ROM Ordering Procedure .... ; . . . . . . . . ..
666
Section 7 Software Application Notes
1.
Page
HOW TO USE APPLICATION NOTES ........ " . . . . . . . . . . . . . . . . . . . . .675
1.1
Formats ................................... ·..................
675
1.1 .1
Specification Format (Format 1) ............ ; . . . . . . . . . .. . . .... .
677
1.1 .2
Description Format (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . ..
683
1.1.3
Flowchart Format (Format 3). . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . ..
686
1.1.4
Program Listing Format (Format 4). . . . . . . . . . . . . . . . . . . . . . . . . . .. .
688
1.2 How to Execute Programs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
690
1.3 Symbols.....................................................
692
PROGRAM APPLICATION EXAMPLES
Program Application Table. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .
693
MOVING DATA
1.
Filling Constant Values (Fill) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
694
2,
Moving Memory Blocks (Move) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
698
~HITACHI
xii
3.
Moving Strings (Moves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
703
BRANCHING FROM TABLE
4.
Branching From Table (CCASE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
708
HANDLING ASCII
5.
Converting ASCII Lowercase Into Uppercase (TPR) ......... . . . . . . . . . ..
714
6.
Converting ASCII Into 1-Byte Hexadecimal (Nibble). . . . . . . . . . . . . . . . . . . . .
719
7.
Converting 8-Bit Binary Data Into ASCII (CO BYTE) . . . . . . . . . . . . . . .. . . . . .
724
BIT MANIPULATION
8.
Counting Number of Logical "1" Bits In 8-Bit Data (HCNT). . . . . . . . . . . . . ..
729
9.
Shifting 32-Bit Data (SHR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
733
COUNTER
10.
4-Digit BCD Counter (DECNT) ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . .
738
COMPARISON
11.
Comparing 32-Bit Binary Data (CMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
743
ARITHMETIC OPERATION
12.
Adding 32-Bit Binary Data (ADD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
749
13.
Subtracting 32-Bit Binary Data (SUB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
755
14.
Multiplying 16-Bit Binary Data (MUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
761
15.
Dividing 16-Bit Binary Data (DIV). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
768
16.
Adding 8-Digit BCD (ADDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
774
17.
Subtracting 8-Digit BCD (SUBD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
780
18.
16-Bit Square Root (SQRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
786
CONVERTING BCD INTO HEXADECIMALS
19.
Converting 2-Byte Hexadecimals Into 5-Digit BCD (HEX) .............. .
791
20.
Converting 5-Digit BCD Into 2-Byte Hexadecimals (BCD) .............. .
796
SORTING
21.
Sorting (SORT) ................................................ .
Section 8 Hardware Application Notes
803
Page
APPLICATION NOTES GUIDE. ....................................... .
815
1.
Symbols ...................................................... .
815
2.
Application Example Configuration ................................. .
817
~HITACHI
xiii
3.
1st Section (Hardware) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
819
4.
2nd Section (Software). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
823
5.
3rd Section (Program Module) .....................................
825
5.1
Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
826
5.2
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
832
5.3
Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
836
6.
4th Section (Subroutine) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
837
7.
5th Section (Program Listing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ..
840
8.
Program Module Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
845
SYSTEM APPLICATION EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
848
System Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
848
I/O PORT APPLICATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
849
1.
HD61830 (LM200) Graphic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
849
2.
Darlington Transistor Drive (LED Dynamic Display) . . . . . . . . . . . . . . . . . . . ..
883
TIMER APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
896
3.
Duty Control of Pulse Output and DA Conversion . . . . . . . . . . . . . . . . . . . . ..
896
4.
Pulse Width Measurement .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
912
5.
Input Pulse Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
922
6.
8 x 4 Key Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
932
INTERRUPT APPLICATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
947
7.
947
A/D Converter (HA 16613A) Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PARALLEL HANDSHAKE APPLICATIONS ... , . . . . . . . . . . . . . . . . . . . . . . . . . ..
956
8.
Standard Keyboard Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
956
9.
Centronics Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
970
SCI APPLICATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
982
10.
Data Transfer With Asynchronous SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
982
11.
Liquid Crystal Drived (HD61100A) Control. . . . . . . . . . . . . . . . .. . . . . . . . . ..
998
EXTERNAL EXPANSION APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1010
12;
External Expansion ............................................. 1010
13.
Slow Device Interface ........................................... 1043
LOW POWER DISSIPATION/FAIL-SAFE APPLICATIONS ................... 1057
14.
Low Power Dissipation Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1057
15.
HA1835P Control and Error Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1074
~HITACHI
xiv
Section 9
C Language Programming Techniques
1.
1.1
Page
HOW TO USE APPLICATION NOTES .............................. . 1105
Hardware Section ............................................. . 1107
1.1.1 Function ................................................... . 1107
1.1.2 Microcontroller Applications ................................... . 1107
1.1.3 Circuit Diagram ............................................. . 1108
1.1.4 Memory Map ............................................... . 1109
1.1.5 Pin Functions ............................................... . 1110
1.1.6 Hardware Operation ......................................... . 1111
1.2
Software Section .............................................. . 1112
1.2.1 Program Module Configuration ................................. . 1112
1.2.2 Program Module Functions .................................... . 1113
1.2.3 Program Module Sample Application (Main Program) ............... . 1114
1.3
Program Module Section ........................................ . 1116
1 .3.1
Page Heading .............................................. . 1117
1 .3.2 Function ................................................... . 1117
1.3.3 Arguments ................................................. . 1117
1.3.4 Libraries Required for Program Execution ........................ . 1118
1 .3.5 Specifications .............................................. . 1119
1 .3.6 Description .................................................. . 1120
1.3.7 PAD ...................................................... . 1123
1.4
Subroutine Section ............................................ . 1124
1.4.1 Page Heading .............................................. . 1125
1.4.2 Function ................................................... . 1125
1.4.3 Basic Operation ............................................. . 1125
1.4.4 Program Modules That Use This Function ........................ . 1126
1.4.5 PAD ...................................................... . 1126
1.5
Program Listing Section ........................................ . 1127
1.5.1 Page Heading .............................................. . 1127
1.5.2 Function ................................................... . 1128
1.5.3 Output Object Listing of C Compliler ............................ . 1131
1.5.4 Linkage Listing .............................................. . 1132
1.6
Program Module Use ........................................... . 1135
~HITACHI
xv
1.7 Pad Symbols Description .......................................•. 1137
1.8
Symbols...................................................... 1138
2.
DARLINGTON TRANSISTOR DRIVE (LED DYNAMIC DISPLAY) . . . . . . . . .. 1139
2.1
Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1139
2.1.1 Function ....................·................................ 1139
2.1.2 Microcontroller Applications ... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1139
2.1.3 Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. 1139
2.1.4 PinFunctions ................................................ 1140
2.1.5 Hardware Operation .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1141
2.2
Software Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. 1142
2.2.1 Program Module Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1142
2.2.2 Program Module Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1142
2.2.3 Program Module Sample Application (Main Program). . . . . . . . . . . . . . .. 1143
2.3
Program Module Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1144
2.4
Program Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1152
2.4.1 Main Program Listing .............................
1152
,
2.4.2 C Source Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. 1153
o• • •
0
•••••••
,
2.4.3 Output Object Listing of C Complier. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1154
2.4.4 Linkage Listing .............................................. , 1157
3.
8x4 KEY MATRiX ............................................... 1159
3.1
Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1159
,
I
3.1.1 Function ........................................
J • • • • • • • • • ••
1159
3.1.2 Microcontroller Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1159
3.1.3 Circuit Diagram .................................. : . . . . . . . . . .. 1160
3.1.4 Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1161
3.1.5 Hardware Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1161
3.2
Software Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1162
3.2.1' Program Module Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1162
3.2.2 Program Module Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1162
3.2.3 Program Module Sample Application (Main Program). . . . . . . . . . . . . . .. 1163
3.3
Program Module Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1165
3.4
Program Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1177
3.4.1 Main Program Listing ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1177
~HITACHI
xvi
3.4.1
Main Program Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1177
3.4.2 C Source Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1178
3.4.3 Output Object Listing of C Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1180
3.4.4 Linkage Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1185
4. - EXTERNAL EXPANSION ......................................... 1187
4.1
Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1187
4.1.1
Function.................................................... 1187
4.1.2 Microcontroller Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1187
4.1.3 Circuit Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1187
4.1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1188
4.1.5 Hardware Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1189
4.2
Software Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1190
4.2.1
Program Module Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1190
4.2.2 Program Module Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1190
4.2.3 Program Module Sample Application (Main Program). . . . . . . . . . . . . . .. 1192
4.3
Program Module Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1194
4.4
Program Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1220
4.4.1
Main Program Listing ... . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1220
4.4.2 C Source Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1222
4.4.3 Output Object Listing of C Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1226
4.4.4 Linkage Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1232
APPENDIXA.
C Program and Assembly Program Comparison .......................... 1235
Section 10-Appendix
HD6301V1/HD6303R Q & A-HD6301XO/HD6303X Oscillation Circuit
Wide Temperature Range Specifications, -40°C to + 85°C, (J Version)
1.
Page
HD6301V1/HD6303R Q & A ...................................... . 1239
(a)
Parallel Port
(1) Process to Use a Port as an Output ............................. . 1241
(b~
Serial Port
(1) Relation between Writing into the FRC and SCI Operation ........... . 1242
(2) Writing into the FRC during Serial Receive/Transmit ................ . 1243
(3) RDRF State When SCI Receiving ............................... . 1244
(4) Serial I/O Operation .......................................... . 1245
(5) Serial I/O Register Read ...................................... . 1246
(6) Detection of the HD6301 V1 Serial Start Bit ....................... . 1247
~HITACHI
xvii
(c)
Timer/Counter
(1) Free Running Counter Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1249
(2) Preset Method of the Free Running Counter. . . . . . . . . . . . . . . . . . . . . .. 1250
(d)
BUS Interface
(1) Output of Address Strobe (AS) in the Multiplexed Mode. . . . . . . . . . . . .. 1252
Interrupt
(1) IRQ1 Acceptance .............................................
(2) Timer Interrupt and External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(3) IRQ1 Interrupt and Other Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(4) CLilnstruction and Interrupt Operation. . . . . . . . . . . . . . . . . . . . . . . . . ..
(e)
1253
1254
1255
1257
(f)
Oscillator
(1) Relation between the External Clock (EXTAL Clock) and Enable Clock
(E Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1258
(g)
Reset
(1) Constants of the Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(2) Schmitt Trigger Circuit of RES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(3) I/O Port State on Resetting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(4) SCI (Pin 39) State on Resetting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(5) Port Output after Resetti ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1259
1260
1261
1262
1263
(h)
Low Power Consumption
(1) Schmitt Trigger Circuit of STBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(2) I/O Port State During Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(3) Return from Standby Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(4) Going into the Standby Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(5) Timing for the Standby Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1264
1265
1266
1267
1268
(i)
EPROM-on-Package
(1) Usage of EPROM Socket Pins for the HD63P01 M (No.1). . . . . . . . . . . .. 1269
(2) Usage of EPROM Socket Pins for the HD63P01 M (No.2). . . . . . . . . . . .. 1270
(3) Usage of EPROM Socket Pins for the HD63P01 M (No.3). . . . . . . . . . . .. 1271
0)
Software
(1) Usage of Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . .. 1272
(2) Usage of Bit Manipulation Instructions to the Port. . . . . . . . . . . . . . . . . .. 1274
(k)
Others
(1) RAM Access Disable during Program Execution. . . . . . . . . . . . . . . . . . .. 1275
2.
HD6301XO/HD6303X OSCILLATOR CIRCUIT .......................... 1276
3.
Wide Temperature Range Specifications -40°C to + 85°C (J Version) ....... 1283
HD6301V1, HD63A01V1, HD63B01V1 .................................... 1284
HD6301XO, HD63A01XO, HD63B01XO .................................... 1289
HD6301YO, HD63A01YO, HD63B01YO, HD63C01YO ........................ 1294
HD6303R, HD63A03R, HD63B03R ...................................... 1300
HD6303X, HD63A03X, HD63B03X ...................................... 1305
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y ............................. 1310
[
HITACHI SALES OFFICES
~HITACHI
xviii
PAGE 1318
HD6301/HD6303 SERIES HANDBOOK
Section One
• Ouick
Reference
Guide
-and
• Package Reference
Guide·
~HITACHI
QUICK REFERENCE G U I D E - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8-BIT SINGLE-CHIP MICROCOMPUTER
• CMOS a-BIT SINGLE-CHIP MICROCOMPUTER HD6301 SERIES
Type No.
Bus Timing (MHz)
LSI
Characteristics
HD6301Vl
HD63A01Vl
HD63B01Vl
HD6301XO
HD63A01XO
HD63B01XO
1.0 (HD6301Vl)
1.5 (HD63A01Vl)
2.0 (HD63B01V1)
1.0 (HD6301XO)
1.5 (HD63A01XO)
2.0 (HD63B01XO)
Supply Voltage (V)
5.0
0- +70. 3 .*.
Operating Temperature (C)
Package t
Memoty
---
DP-40. FP-54. CG-40. CP-44. CP-52
ROM (k byte)
RAM (byte)
Input Port
4
128
192
Functions
24
29
-
29
Output Port
Interrupt
DP-64S. FP-80. CP·68
4
I/O Port
I/O Port
5.0
0- +70. 3
53
8
21
External
2
3
Soft
2
2
Timer
3
4
Serial
1
1
Timer
16-bit xl
16-bit xl
( Free running counter X l ) ( Free running counter Xl)
Output compare register x 1
Output compare register x2
Input capture register xl
Input capture register xl
8-bit xl
(8-bit up counter
Time constant register x 1
Asynchronous/Synchronous
Asynchronous
XI)
SCI
External Memory Expansion
Other Features
.1
• 4
65k bytes
65k bytes
o Error detection
oLow power dissipation
modes (sleep and standby)
oError detection
oLow power dissipation
modes (sleep and standby)
oSlow memory interface
oHalt
EPROM on Chip Type
HD63701VOC
HD637A01VOC
HD637B01VOC
EPROM on the Package Type
HD63P01Ml
HD63701XOC
HD637A01 XOC
HD637BOl XOC
--
Preliminarv
.2 Under development
.3 Wide temperature range (-40 - +85°C) version is available .
Wide temperature range (-40 - +12So C) version is available.
tOP; Plastic DIP, FP; Plastic Flat Package. CG; Glass-sealed Ceramic leadless Chip Carrier. CP; Plastic leaded Chip Carrier (J-bend leads)
~HITACHI
2
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Q U I C K REFERENCE GUIDE
HD6301YO
HD63A01Y0
HD63B01YO
HD63C01YO
HD6303R
HD63A03R
HD63B03R
HD6303X
HD63A03X
HD63B03X
1.0 IfD6301YO)
1.5 HD63AOI YO)
1.0 (HD6303R)
1.5 (HD63A03R)
2.0 (HD63B03R)
1.0 (HD6303X)
1.5 (HD63A03X)
2.0 (HD63B03X)
19i ~g~~~g, ~g)
5.0
0- +70"
DP-64S. FP-64. FP-64A. CP-68
5.0
0-- +70·),· ..
Dp·40. Fp·54. CG·40. CP·52
16
256
-
DP·64S. FP·80. CP·68
-
-
-
12B
192
256
13
48
53
5.0
0-+70"
HD6303Y
HD63A03Y
HD63B03Y
HD63C03Y
1.0 rD6303Y~
1.5 H D63A03 )
2.0 HD63B03Yj
3.0 HD63C03Y
5.0
0- +70"
DP-64S. Fp·64. FP-64A. CP-68
-
13
16
a
24
-
-
5
24
-24. _ - -
3
2
3
3
2
4
2
2
2
3
4
4
1
1
1
1
16·bit x 1
16·bit x 1
16·bit xl
16·bit x 1
(Free running counter xl
) (Free running counter x 1 ) (Free running counter x 1
) (Free running counter x 1 )
Output compare register x 2
Output compare register x 1
Output compare register x 2
Output compare register x 2
Input capture register x 1
Input capture register x I
Input capture register x 1
Input capture register x 1
8·bit x 1
a·bit x I
a·bit xl
(8-bit up counter x 1
)
( 8·bit up 'counter x 1
) (B.bit up counter x 1
)
Time constant register x 1
Time constant register x 1
Time constant register x 1
Asynchronous/Synchronous
Asynchronous/Synchronous
Asynchronous
Asynchronous/Synchronous
65k bytes
65k bytes
65k bytes
65k bytes
- Error detection
- Low power dissipation
modes (sleep and standby)
oSlow memory interface
oHalt
HD6370lYOC
HD637A01YOC
HD637B01YOC
-
- Error detection
-Low power dissipation
modes (sleep and standby)
-Error detection
oLow power dissipation
modes (sleep and standby)
.Slow memory interface
-Halt
oError detection
oLow power dissipation
modes (sleep and standby)
.Slow memory interface
oHalt
-
-
-
-
-
-
~HITACHI
3
PACKAGE REFERENCE GUIDE
Hitachi microcomputer devices include various types of
package which meet a lot of requirements such as ever smaller,
thinner and more versatile electric appliances. When selecting a
package suitable for the customers' use, please refer 10 the
following for Hitachi microcompu ter packages.
multi-function types, applicable to each kind of mounting
method. Also, plastic and ceramic materials are offered according to use.
Fig. I shows the package classification according to the
mounting types on the Printed Circuit Board (PCB) and the
materials.
1. Package Classification
There are pin insertion types, surface mounting types and
Standard Outtine.
Pin Insertion Type
Plastic DIP
Ceramic DIP
Shrink Outline
Shrink Typel Plastic DIP
Shrink Type 'Ceramic DIP
Package Classification
Flat Package
SOP IPlastic)
FPP (Plastic)
Surface Mounting Type
Multi-function Type
Ch ip Carrier
PLCC (Plastic)
EPROM on the Package
LCC
IGlass Sealed Ceramic)
Type
DIP; DUAL IN LINE PACKAGE
S·DIP;SHRINK DUAL IN LINE PACKAGE
PGA: PIN GRID ARRAY
FLAT-DIP; FLAT DUAL IN LINE PACKAGE
FLAT·QUIP; FLAT QUAD IN LINE PACKAGE
CC: CHIP CARRIER
SOP;SMALL OUTLINE PACKAGE
FPP; FLAT PLASTIC PACKAGE
PLCC; PLASTIC LEADED CHIP CARRIER
LCC ; LEADLESS CHIP CARRIER
Fig. 1 Package Classification according to the Mounting Type on the Printed Circuit Board and the Materials.
~HITACHI
4
PLASTIC DIP
Unit: mm(inch)
Scale: 1/1
• Dp·40
52812079)
54.0mlx.(2.126ma...)
'0
21
;
-$-
~
20
10.047)
~-I ~!
..
15.24
10.600)
0.4810.1
.~~
(0.019:0.004) :; gO ... IS·
N~
2.54:0.25
<0.100:0.010)
Unit: mmlf,ch)
CERAMIC DIP
Scale: 1/1
• DC·40
..
r--·----1~~9~:1--------i
o
Unit: mm(inch)
SHRINK TYPE PLASTIC
Scale: 1/1
• DP·64S
..
576(2'268)
SB.6ma •.(Z.301mad
"
o
~HITACHI
5
I CERAMIC SHRINK TYPE
Unit: mm(inch)
I
Scale: 1/1
• DC-64S
t:~:::IQI:::::::1~ .
I
II
0.9(0.035)
-=
.. E
..
~~~HFI
-I~5'1.11
(o.DlO:tIll)
~HITACHI
6
'\
FLAT PACKAGE
Unit: mm(inch)
Scale: 3/2
• FP-54
2.9max.
(O.114max.)
JL
O.IS±O.OS
(0006 ±0.0021
• FP-64
Z.9max.
(Q.lljmu.)
-k,
O,\!IotO,O!lZ)
lO.OOo"O.OO
..AiUUUI)lilUU)l)lIIIIliIlii)l)liLi~
~'Q.OIZ.).
D"-I5"
1.11: 0.')(0.
• FP-64A
17 ao 3(0 677±0 012)
.
.
.~~
-;;;
C!
~
-Ii -
49
.= I
..
=
=:...
14.0(0.SSI)
8
3
3
I 2.90(0.1I4)max
0.1 (0.004)
(STANO OFF)
=
~
Ci'<=:
~
-Ii -
~
64
o 3S+0.0S
0.014 ± 0.002
r.=r.;c-;-::;=-==
I
II 1+IO.IS(o.oo~f@1
I
O.IS±O.OS
(0.006±o.o02)
(0.03!)
~HITACHI
7
I
• FP-80
4£~(OOI~;~i~miW!iiB OIS:l:O.OS
I!!.:.!
_L
(0.006:1:0.ooZ)
~
.J
~UUUllUUUUUDUUUUUjlJmUU~ 0·- lS1.7 :1:0.3(0.067:1:0.01 Z)
172:1:03(0677:1:0012)
• FP-80A
I 2.90(0.114)max
14.0(0.551)
41
60
U
0.1 (0.004)
4
(STANO OFF)
BO
o 3P+!I.lIS II
.012±0.002)
0.15:1:0.05
(0.006:1:0.002)
,+, 0.13(0.OOS~20 I
~~ ~0"-5"
O.B
=-0;;-;
0.100.004)
(0.031)
~HITACHI
8
• FP·80B
2,9max.
(O,114ma".)
~UUUOUUUUUUU~.l-
L
~
,2:l:.0.•
O·-IO·t
(O.o;'1:l:.0.00S)01 0.1510.00611
Unit: mm(inch)
PLASTIC LEADED CHIP CARRIER
Scale: 3/2
• CP·44
..
n.S3±O 12(0 6!O±O OOS)
1'44
§
...ci
1
"
0
~
l<
d
...
,.
~Il
~
"
/I
::I~
... I'!
:~
16.51(0.&53)
!...
~
~ci
...
~
15.SO±O.5O(O.6ID±O.020)
ZOO7:t:O 12
(O.190.tO.OO5)
1
• CP·52
I
".
"
0
~
~
zo
"
J3
19.12
(0.753)
::I!
~;:I Innni
... ~....,.
'TTl.2lo:omr
11.~±O.5
(O.7IDiD.ozal
~HITACHI
9
J
~
0
~
q
'"
5P44
.u
43
27
o
0.10(0.004)
( SEATING PLANE)
(0.910±0.020)
~HITACHI
10
Unit: mm(inch)
LEADLESS CHIP CARRIER
Scale: 3/2
• CG·40
a.75m•••
(a.030m •••)
1
110 gonno non n=#Ff=Tl ~
..ui18~~
6
15
...;
~
N
~
16
~HITACHI
11
I
•
12
HITACHI
I
HD63011HD6303 SERIES HANDBOOK
Section Two
Addressing Modes,
CPU Architecture,
and
Instruction Set
~HITACHI
13
~HITACHI
14
Section 2
Addressing Modes, CPU Architecture, and Instruction Set
Table of Contents
Page
1. ASSEMBLY LANGUAGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
17
1.1
Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
1.2
CPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
1.3
Instruction Set Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
~HITACHI
15
~HITACtil
16
ADDRESSING MODES, CPU ARCHITECTURE, AND INSTRUCTION SET
ASSEMBLY LANGUAGE
1.
1.1
Addressing Modes
The assembler determines the addressing mode by referencing
the operator and operand fields.
There are seven different
addressing modes available.
(1) Accumulator addressing
(2) Implied addressing
(3) Immediate addressing
(4) Direct addressing
(5) Extended addressing
(6) Indexed addressing
(7) Relative addressing
~HITACHI
17
Before going into details about individual addressing modes,
we explain the dual operand mode in which an instruction has
two operands.
For eight instructions AIM, OIM, ElM, TIM, BCLR, BSET, BTGL
and BTST, the operand .field requires two operands (the first
and second operands).
The first operand includes the immediate
data (constant) for AIM, OIM and TIM; and the bit number for
bit operation for BCLR, BSET, BTGL and BTST. The second
operand specifies a memory address in either indexed or
direct addressing mode·
(1) Accumulator Addressing
Thirteen instructions allow Accumulator A or B as an operand.
They are:
ASL, ASR, CLR, COM, DEC, INC, LSR, NEG, PSH, PUL,
ROL, ROR and TST.
In this case, an ~ or ~ between the
operator and the operand may be omitted.
Each accumulator
addressing instructions is converted into a one-byte machine
code by the assembler.
Example:
Instruction code
(2)
Machine code (Hexadecimal)
ASL A or ASLA
48
ASR B or ASRB
57
Implied Addressing
In the implied addressing mode, the instruction contained in
the operator field permits the address for operation to be
clear-cut.
The operand is therefore unnecessary.
This implied addressing includes 31 instructions:
ABA, ABX,
ASLD, CBA, CLC, CLI, CLV, DAA, DES, DEX, INS, lNX, LSRL,
MUL, NOP, PSHX, PULX, RTI, RTS, SBA, SEC, SEl, SEV, SWI,
TAB, TAP, TBA, TPA, TSX, TXS and WAI.
Each instruction
is converted into a one-byte machine code by the assembler.
~HITACHI
18
(3) Immediate Addressing
There are 16 instructions that allow immediate addressing.
They are:
ADC, ADD, AND, BIT, CMP, CPX, EOR, LDA, LDS,
I
LDX, ORA, SBC, SUB, LDD, ADDD and SUBD.
The operand field starts with #, followed by numerical data
in decimal, hexadecimal, octal or binary, symbols (labels)
that will take specific values during assembling, expressions
and ASCII constants.
In any case, the assembler converts the immediate data
(operand) into an unsigned 8-bit binary, or 16-bit binary
for CPX, LOS, LOX, LOO, AOO and SUBO.
The resulting immediate
data range from 0 to 255, or 0 to 65535 for 16-bit operand
instructions.
Example:
Statement
rilachine code (Hexadecimal)
Label = 100
Byte 1
Byte 2
Byte 3
LDA A #25
86
19
-
LOA A #LABEL
86
64
-
LOA A #LABEL + 25
86
7D
LDA A # 'A
86
41
-
CPX
8C
01
00
#256
In this case, the characters following "'" are converted into
7-bit ASCII data. The #'conversion is not generally used with
CPX, LOS
~nd
LOX instructions.
If it is used, however, the
converted ASCII,data is stored into byte 3.
The assembler
enables each immediate addressing instruction to be converted
into 2 bytes in machine code (3 bytes in the case of CPX,
LDS, LOX, LOO, ADOO and SUBO).
Figure 1-1-1 shows how data flows in immediate addressing mode.
~HITACHI
19
CPU
CPU
ACCA
[E
O_~r¢:
--3 AM
RAM
<=
...Program memory
PC
Pr ogram memory
Instruction
Data
pc- 5002
25
Outline flowchart
Fig. 1-1-1
I.OA A
--
.....
~
Example
Data Activity in Immediate Addressing Mode
(4) Direct Addressing and Extended Addressing
In direct addressing mode, the assembler converts the instruction into 2 bytes of machine code.
The second byte, after
conversion, includes an unsigned a-bit binary address.
In extended addressing mode,
the assembler converts the
instruction into 3 bytes of machine code.
The second byte
includes the upper a bits of the address; and the third byte
includes the lower a bits.
Both of them are unsigned a-bit
in binary notation.
The assembler permits both direct addressing and extended
addressinq to be translated into absolute addresses.
The assembler automatically selects direct addressing if the
address is within 0 - 255; and extended addressing if the
address is greater than 255.
~HITACHI
20
Example:
Machine code (Hexadecimal)
Label address = 100
Statement
LOA A 100
LOA A LABEL
LOA A LABEL + 200
Byte 1
Byte 2
Byte 3
96
64
96
B6
64
-
01
2C
I
Figures 1-1-2 and 1-1-3 show how data flows in direct
addressing and extended addressing modes, respectively.
CPU
CPU
ACCA
r<==--
QJ <-=
RAM
_RAM . /
f<=
Data
Address
Address
~
100
---
-
Pr ogram memory
Pr ogram memory
PC
-
Instruction
~
PC=5004
~
Address
-
Address= 0 s:: 2S S
Outline flowchart
Fig. 1-1-2
<=
35
LDA A.
100
-'-
.....
-
Example
Data Activity in Direct Addressing Mode
~HITACHI
21
CPU
CPU
ACCS
~
f--..=:
-
RAM
,--Address
f<;:=
Data
Pr ogram memory
Program memory
Instruction
.c'--::
Address
PC
LOA
P C-500
S
300
Address
Address ::?; 256
Outline flowchart
Fig. 1-1-3
Example
Data Activity in Extended Addressing Mode
(5) Indexed Addressing
In Indexed addressing mode, the assembler converts the operand
into an unsigned 8-bit displacement "Disp".
The displacement
"Disp" is added to the contents of the Index Register to
determine the effective address M.
M = Disp + (X)
As other addressing modes, the operand may contain symbols
(labels) and expression that are
~valuated
They must range from 0 to 255.
~HITACHI
22
during assembling.
Example:
Machine code (Hexadecimal)
Label address = 100
Byte 1
Byte 2
Statement
LOA B X
E6
00
LOA B, X
E6
00
LOA B 5, X
LOA B LABEL, X
E6
05
E6
64
LOA B LABEL + 5, X
E6
69
I
Figure 1-1-4 shows how data flows in indexed addressing mode.
CPU
I
CPU
ACCS
OTI
~-
Ind ex register
EJ
RAM
Address=Index
register+
Displacement
~====::::::==l
Data
RA ~
Address a 405
f::;=
59
Pr ogram memory
Program memory
PC
Instruction
Displacement
Displacement s:: 256
Outline flowchart
Fig. 1-1-4
PC
a
500 6
--
LOA B
5
¢-
Example
Data Activity in Indexed Addressing Mode
~HITACHI
23
(6) Relative Addressing
This mode is limited to branch instructions.
A relative addressing instruction is converted into 2 bytes of
machine code by the assembler.
The second byte indudes an
a-bit relative address (ReI., used as two's complement).
On execution, the relative address (ReI.), the contents of
the Program Counter (PC), and 2 are added to obtain the
absolute address (D) of the branch destination as follows.
D
(PC) + 2 + Rel.
D
absolute address of branch destination
Rel
relative address
Therefore, the branch destination is within -126 and +129 from
the OP-code address.
Example:
Statement
BEQ *+17
BEQ LABEL
BEQ LABEL - 105
Machine code (Hexadecimal)
Label address - (PC) -2 = 100
Byte 1
Byte 2
27
OF
27
27
64
FB
If, however, the branch destination is more than -126 to +129
away, JMP and JSR instructions can be used as shown below.
~HITACHI
24
Example:
Machine code (Hexadecimal)
Statement
Byte 1
I Byte
2
Byte 3
JMP 300
7E
01
2C
JSR 300
BD
01
2C
Figure 1-1-5 shows how data flows in relative addressing mode.
CPU
CPU
HINZVC
~
-
r---.;=
RAM
RAM
~
.-..
.......-
.-"\.
-.......r-
-
-
Pr ogram memory
Pro gram memory
-
Instruction
PC
<".....
SEQ
PC= 5008
Dis~lace-
men
Next 1nstruction
(PC+2)
~
15
Next in-
PC- 5010 struction
(Z)!o;O
r--
Next
1n(PC+ 2) + struction
PC
a
in5025 Next
struction
(Z)=o
Displacement
.......
Fig. 1-1-5
-
~
Data Activity in Relative Addressing Mode
~HITACHI
25
1.2
CPU Registers
The CPU has three 16.;bit registers and three 8-bit registers. The
register configuration of the CPU is shown in Fig. 1-2-1.
is shown in Fig. 1-2-1.
0
7
I
7
.~CC
B
15
0
IX
0
PC
15
0
I
SP
I
Accumulator B
I
I
Index Register
Program Counter
I
Stack Pointer
0
7
CCR
Accumulator A
0
I
I
15
I
I
ACCA
Condition Code Register
Carry-borrow, from bit 7
Overflow
Zero
Negative
Interrupt mask
Half-carry, from bit 3
11111BI rlNlzlvlcl
L
-
Fig. 1-2-1
(l)
CPU Registers
Accumulators (ACCA & ACCB)
The CPU has two a-bit accumulators that store the result of
arithmetic and logical operation.
If a double accumulator is specified, a pair of registers ACCA
and ACCB can be functions as an l6-bit register.
87
15
I
Fig. 1-2-2
(2)
ACCA
0
ACCB
I
ACCAB (Double Accumulator)
Index register (IX)
The index register is a 2-byte (l6-bit) register that stores
a l6-bit memory address used in indexed addressing mode or a
l6-bit immediate data.
~HITACHI
26
(3)
Program counter (PC)
The program counter is a 2-byte (l6-bit) register that indicates the address of the instruction being executed by the
After the instruction execution, the program counter is
cpu.
I
automatically incremented, indicating the address of the
next instruction.
(4)
Stack pointer (SP)
The stack pointer is a 2-byte (l6-bit) register that indicates the next available location in the memory pushdown/
popup stacks.
Any area of memory may serve as stacks; and
random access (read/write) memory is generally used as stacks.
In an application system which must hold data in stacks even
an application system which must hold data in stacks even
when power supply is off, the stacks normally use batterybacked CMOS memory.
(5)
Condition code register (CCR)
The condition code register indicates the result of arithmetic
operation, etc.
It consists of six bits: zero (Z), negative
(N), overflow (V), carry-borrow from bit 7 (C), half-carry
from bit 3 (H), and interrupt mask (I).
These bits may be
tested by a variety of conditional branch instructions, which
is limited to relative addressing.
It should be noted that
the upper two bits of the contition code register cannot be
used.
~HITACHI
27
1.3
Instruction Set Details
l-1eanings of symbols and mnemonics:
(1) Operation symbols
()
Contents
Direction of data transfer
From stack
To stack
AND operation
o
$
OR operation
Exclusive-OR operation
-
NOT operation
(2) Registers within MPU
ACCA
Accumulator
~.
ACCB
ACCX
= Accumulator
B
Accumulator A or B
ACCD
Double accumulator (ACCA + ACCB)
Condition-code register
CC
IX
Index register, 16 bits
IXH
IXL
=
MSB 8 bits of index register
LSB 8 bits of index register
PC
PCH
Program counter, 16 bits
MSB 8 bits of program counter
PCL
LSB 8 bits of program counter
SP
SPH
SPL
Stack pointer, 16 bits
MSB 8 bits of stack pointer
LSB 8 bits of stack pointer
(3) Memory and addressing modes
M
MH
ML
M+l
Imm
liJemory address
MSB 8 bits of memory address
LSB 8 bits of memory address
Memory addres.s of memory address M + 1
Immediate data
~HITACHI
28
ImmH
Im.'TIL
MSB 8 bits of immediate value
LSB 8 bits of immediate value
Disp
Displacement
ReI
ACCX
IMMED
DIRECT
INDEX
=
M -
(IX)
I
Branch destination absolute
Accumulator addressing
Immediate addressing
Direct addressing
Index addressing
EXTEND
Extended addressing
RELATIVE
Relative addressing
IMPL
=
Relative addressing
address - (PC) - 2
Implied addressing
(4) Meaning of bits 0 through 5 of condition-code register
C
Carry and borrow; bit 0
V
Overflow for 2's complement; bit 1
Z
Zero; bit 2
N
Negative; bit 3
I
Interrupt mask; bit 4
Half carry from bit 3 to bit 4 ; bit 5
H
(5) Bit status before run of instruction
An
Bn
Dn
IXn
Bit n of ACCA (n
Bit n of ACCB (n
=
=
7, 6, 5,
... ,
7, 6, 5,
Bit n of double accmulator (n
Bit n of IX (n
IXHn
Bit n of IXH (n
IXLn
Bit n of IXL (n
=
0)
••• I
=
0)
15, 14, 13, ... , 0)
15, 14, 13, ... , 0)
7, 6, 5 , ... , 0)
7, 6, 5, ... , 0)
SPHn
Bit n of M (n = 15, 14, 13, ... , 0)
7, 6, 5, ... , 0)
Bit n of SPH (n
SPLn
Bit n of SPL (n
Mn
Xn
Bit n of ACCX (n
7, 6, 5, ... , 0)
=
7, 6, 5, ... , 0)
(6) Bit status after run of instruction
Rn
Bit n of result (n
=
15, 14, 13, ... , 0)
RHn
Bit n of resulting high-order byte
(n = 7, 6, 5, ..• , 0)
RLn
Bit n of resulting low-order byte
(n = 7,6,5, ... ,0)
~HITACHI
29
Add accumulator B to accumulator A
L
ABA
Function
Category
"
Arithmetic
operation
(Two
operands)
ACCA
-
(ACCA) + (ACCB)
Adds the contents of ACCB to the contents of ACCA,
and stores the result into the ACCA.
I,
Effects on the condition codes
H
=
A3'B3@B3'R~R3'A3:
Set i f a carry from bit 3 is generated;
cleared otherwise.
I : Not affected.
Z
=
=
V
=
A7·B7·R70A7.B7·R7:
otherwise.
Set if the result overflows; cleared
C
=
A7·B70B7·R70R7·A7:
Set if a carry from the MSB is generated
N
R7:
Set i f the result's HSB is "l"i cleared otherwise.
R7·R6·R5·R4·R3·R2·Rl·RO:
cleared otherwise.
Set i f the result is zero;
cleared otherwise.
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
IMPL
ABA
Operand
format
1st
byte
IB
~HITACHI
30
2nd
byte
3rd
byte
Bytes
of
instr.
code
CPU
cycles
1
1
/
Add accumulator B to indeX register
ABX
Function
category
Arithmetic
operation
IX -
I
(IX) + (ACCB)
Adds the unsigned contents of ACCB to the contents of
the IX taking into account a carry from the low-order
byte of the IX, and stores the result into the IX.
Effects on the condition codes
H :
I :
N :
Not affected.
"
"
V :
"
"
C :
"
Z :
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
IMPL
ABX
Operand
format
1st
byte
3A
2nd
byte
3rd
byte
Bytes
of
instr.
code
CPU
cycles
1
1
~HITACHB
31
L
ADd with Carry
Function
Category
Arithmetic
operation
(Two
operands)
ADC
-
ACCX
(ACCX) + (M) + (C)
Adds the contents of ACCX, memory M, and carry bit C,
and stores the result into the ACCX.
Effects on the condition codes
H
=
X3·M39M3·R39R3·X3:
Set i f a carry from bit 3 is generated;
cleared otherwise.
I : Not affected.
Z
=
=
Set if the result's MSB is "III; cleared otherwise.
R7·R6·R5·R4·R3·R2·Rl·RO: Set i f the result is zero;
V
=
X7·M7·R79X7·M7·R7:
otherwise.
Set i f the result overflows; cleared
C
=
X7·M79M7·R79R7·X7:
Set if a carry from the MSB is generated;
N
R7:
cleared otherwise.
cleared otherwise.
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
IMMED
ADC
DIRECT
ADC
EXTND
ADC
INDEX
ADC
Operand
format
1st
byte
2nd
byte
Unun
89
Inun
2
2
A
M
99
M
2
3
A
A
M
Disp,X
B9
MH
3
4
A9
Disp
2
4
2
A
ML
IMMED
ADC
B
#Inun
C9
Inun
2
DIRECT
ADC
B
M
09
~1
2
3
EXTND
ADC
B
M
F9
MH
3
4
INDEX
ADC
B
Disp,X
E9
Disp
2
4
~HITACHI
32
3rd
byte
Bytes
of
CPU
instr.
cycles
code
ML
/
ADD without carry
category
Aritrunetic
operation
(Two
operand)
ADD
Function
ACCX
-
I
(ACCX) + (M)
Adds the contents of memory M to the contents of ACCX
and stores the result into the ACCX_
Effects on the condition codes
Set i f a carry from bit 3 is generated;
H = X3-M38M3-R38R3-X3:
cleared otherwise_
I : Not affected_
Set i f the result's MSB is "l"i cleared otherwise_
N = R7:
Z = R7-R6-RS-R4-R3-R2-Rl-RO:
Set i f the result is zero;
cleared otherwise_
V = X7-M7-R78X7-M7-R7:
Set i f the result overflows;
cleared
otherwise_
Set i f a carry from the MSB 16 generated;
C = X7-M78M7-R7GR7-X7:
cleared otherwise_
..
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
Operand
format
1st
byte
2nd
byte
3rd
byte
Bytes
of
instr_
code
CPU
cycles
IMMED
ADD
A
#Inun
8B
I nun
2
2
DIRECT
ADD
A
M
9B
M
2
3
EXTND
ADD
A
M
BB
MH
3
4
INDEX
ADD
Disp
2
4
ADD
Disp,X
#Inun
AB
IMMED
A
B
CB
Inun
2
2
2
3
3
4
2
4
DIRECT
ADD
B
M
DB
M
EXTND
ADD
B
M
FB
MH
INDEX
ADD
B
Disp,X
EB
Disp
ML
ML
~HITACHI
33
Double ADD without carry
/
Category
Arithmetic
operation
ADDD
Function
-
ACCD
(ACCD)
+ (M:M+l)
Adds the contents of memories M and M+l to the contents
of ACCD, and stores the result into the ACCD.
Effects on the condition codes
H : Not affected.
I : Not affected.
N : N=R1S; Set i f the result's MSB is Ill"; cleared otherwise.
Z = R1S·R14·R13·········RO:
Set i f the result is zero; cleared
otherwise.
V
=
AB1S·M1S·R1S0AB1S·M1S·R1S:
cleared otherwise.
C
=
AB1S·M1S0M1S·R1S0R1S·AB1S: Set if a carry from the MSB is
generated; cleared otherwise.
Set i f the result overflows;
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
IMMED
ADDD
DIRECT
ADDD
EXT NO
ADDD
INDEX
ADDD
-
Operand
format
1st
byte
2nd
byte
ImmH
#Imm
C3
M
D3
M
Disp,X
F3
MH
E3
Disp
ImmL
M
@HITACHI
34
3rd
byte
ML
Bytes
of
instr.
code
CPU
cycles
3
3
--
2
4
3
5
5
2
/
And IMmediate
Category
Logic
operation
AIM
Function
M-
1M
-
(M)
I
ANDs the immediate data and the contents of the memory
M, and stores the result into the meory M_
Effects on the condition codes
H :
I
N
Z
:
=
=
Not affected_
Not affected_
R7: Set i f the result's MSB is "1"; cleared otherwise_
R7-R6-RS-R4-R3-R2-Rl-RO: Set if the "resul t is zero; cleared
otherwise_
=
0: Cleared_
C : Not affected_
V
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
DIRECT
INDEX
AIM
AIM
Operand
format
iImm,M
iImm,Disp,X
Instruction code
1st
byte
2nd
byte
71
Imm
Imm
61
3rd
byte
M
Disp
Bytes
of
instr_
code
3
3
CPU
cycles
6
7
~HITACHI
35
/
logical AND
AND
Function
Category
Logic
operation
-
ACCX
(ACCX)
.
(M)
ANDs the contents of ACCX and the memory M, and stores
the results into the ACCX.
Effects on the condition codes
H : Not affected_
I : Not affected.
N = R7:
Set i f the result's MSB is "I"; cleared otherwise.
Z = R7-R6-RS-R4·R3-R2-Rl·RO:
Set i f the result is zero; cleared
otherwise.
V =
0:
Cleared.
C : Not affected.
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
IMMED
AND
A
DIRECT
AND
A
Operand
format
Umm
M
CPU
cycles
1st
byte
2nd
byte
84
Imm
2
2
94
M
2
3
ML
3
4
EXTND
AND
A
M
B4
MH
INDEX
AND
A
Disp,X
A4
Disp
2
4
IMMED
AND
B
C4
Imm
2
2
2
3
3
4
2
4
DIRECT
AND
B
Umm
M
D4
M
EXTND
AND
B
M
F4
MH
INDEX
AND
B
Disp,X
E4
Disp
~HITACHI
36
3rd
byte
Bytes
of
instr_
code
ML
/
Arithmetic Shift Left
Category
Shift &
rotation
ASL
Function
[D-l
I
b,
I I I I I I I I -0
b.
Shifts ACCX or memory M by one bit to the left. Bit 0
takes "0". The original value of bit 7 moves into the
carry bit C.
Effects on the condition codes
H : Not affected.
I : Not affected.
N == R7: Set if the result's MSB is "1"; cleared otherwise.
Z == R7'R6'~'R4'R4'R3'~'Rl'RO: Set if the result is zero;
cleared otherwise.
V == NEIlC:
Set if either N=l and C=O or N==O and C=l after the
shift operation; cleared otherwise.
Note: The Nand Care those. obtained after operation.
C == M7: Set if the MSB of ACCX or the memory is "1" before the
shift operation; cleared otherwise.
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
ACCX
ACCX
EXTND
INDEX
ASL
ASL
ASL
ASL
Operand
format
A
B
M
Disp,X
Instruction code
1st
byte
48
58
78
68
2nd
byte
MH
Disp
3rd
byte
ML
Bytes
of
instr.
code
1
1
3
2
CPU
cycles
1
1
6
6
~HITACHI
37
/
Arithmetic Double Shift Left A:B
Category
ASLD
Function
Shift &
rotation
0-1 I I I I I I I I I I I I I I I I-@]
bo
b"
Shifts ACCD by one bit to the left. Bit 0 takes "0".
The original value of bit 15 moves into carry bit C.
Effects on the condition codes
H :
I
:
N
Z
=
=
V
=
C =
Not affected.
II
R15: Set if the result's MSB is "1"; cleared otherwise.
R15·R14·R13··········RO: Set if the result is zero;
cleared otherwise.
Nec: Set if either N=l and C=O or N=O and C=l after the
shift operation; cleared otherwise.
Note: The N and C are those obtained after operation.
A B15 : Set i f the MSB of ACCAB is "I" before the shift
operation; cleared otherwise.
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
IMPL
ASLD
Operand
format
Instruction code
1st
byte
2nd
byte
1
05
I
~HITACHI
38
3rd
byte
Bytes
of
instr.
code
CPU
cycles
1
Arithmetic Shift Right
category
Shift &
rotation
L
Function
ASR
I
Y":I I I I I I I• r-@]
b,
bo
Shifts the contents of ACCX or nlemory M by one bit to
the right. Bit 7 is not affected. The original value of
bit 0 moves into carry flag.
Effects on the condition codes
Not affected.
I I Not affected.
N = R7: Set if the result's MSB is IIl"i cleared otherwise.
X ::: ~'M'~'M'R3'R2'~'RO: Set i f the result is zero; cleared
otherwise.
V '" N$C: Set if either N=l and C=O or N=O and Col after the
shift operation; cleared otherwise.
Note: The Nand Care those obtained after operation.
C = MO: Set if the LSB is '''1'' before the shift operation;
cleared otherwise.
H :
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
ACCX
ACCX
EXTND
INDEX
ASR
ASR
ASR
ASR
Operand
format
Instruction code
1st
byte
2nd
byte
3rd
byte
47
57
A
B
M
Disp,X
77
67
MH
Disp
ML
Bytes
of
instr.
code
CPU
cycles
1
1
1
1
3
2
6
6
-
~HITACHI
39
/
Branch if Carry Clear
Category
Conditional
branch
(PC) + 0002 + Rel
PC -
BCC
Function
If (C) = 0
Tests the state of carry bit C and causes a branch
i f C = O.
Effects on the condition codes
H
.
Not affected.
I :
N :
"
Z :
"
V :
C :
"
"
"
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
RELATIVE
BCC
Operand
format
Rel
Instruction code
1st
byte
2nd
byte
24
Rel
$HITACHI
40
3rd
byte
Bytes
of
instr.
code
2
CPU
cycles
3
/
Bit CLeaR
Category
Logic
operation
BCLR
Function
0
Mi Clears bit i (i=O to 7) of the memory M. Other
bits are not affected.
* The machine code of this instruction is the same as
AIM.
Effects on the condition codes
I
Not affected.
I : Not affected.
N = R7: Set i f the result's MSB is "1"; cleared otherwise.
Set i f the result is zero; cleared
Z = R7 • R6 • RS • R4 • R3 • R2 • Rl • RO :
otherwise.
V = 0: Cleared.
C : Not affected.
H :
Addressing modes and CPU cycles
Instruct'ion code
Addressing
mode
DIRECT
"
"
"
"
"
"
"
INDEX
"
"
"
"
"
"
"
Mnemonic
BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
BCLR
Operand
format
O,M
1,M
2,M
3,M
4,M
5,M
6,M
7,M
O,Disp,X
1,Disp,X
2,Disp,X
3,Disp,X
4,Disp,X
5,Disp,X
6,Disp,X
7,Disp,X
1st
byte
2nd
byte
3rd
byte
Bytes
of
instr.
code
71
FE
FD
FB
F7
EF
DF
BF
7F
FE
FD
FB
F7
EF
DF
BF
7F
M
3
6
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
3
7
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
61
"
"
"
"
"
"
"
"
"
Disp
"
"
"
"
"
"
"
"
"
"
"
"
CPU
cycles
"
"
~HITACHI
41
/
Branch if Carry Set
BCS
Function
Category
Conditional
branch
PC -
(PC) + 0002 + ReI
If
(C) = 1
Tests the state of carry bit C and causes a branch
ifC=l.
I
Effects on the condition codes
H :
I :
N :
Not affected.
V :
"
"
"
"
C :
"
Z
:
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
Operand
format
RELATIVE
BCS
ReI
1st
byte
2nd
byte
25
ReI
1-"
~HITACHI
42
3rd
byte
Bytes
of
instr.
code
2
CPU
cycles
3
/
Branch if EQual
BEQ
Function
Category
Conditional
branch
PC -
(PC) + 0002 + Rel
I
I f (Z) = 1
Tests the state of bit Z and causes a branch
i f Z=l.
Effects on the condition codes
H :
Not affected.
I :
II
N :
II
Z :
II
V :
II
C :
·11
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
Operand
format
RELATIVE
BEQ
Rel
1st
byte
27
2nd
byte
Rel
3rd
byte
I
Bytes
of
'
instr.II
code
2
CPU
cycles
3
~HITACHI
43
Branch i f Greater than or Equal to zero
Category
/
BGE
Function
(PC) + 0002 + ReI
i f (N) $ (V) = 0
PC that is, (ACCX) > (M) ; in the case of two's complement
Conditional
branch
Branches if N=l and V=l or if N=O and V=O.
When a BGE instruction is executed immediately after
an instruction such as CBA, CMP, SBA or SUB has been
executed, a branch occurs if the minuend (ACCX) as a
two's complement is greater than, or equal to, the
subtracter (M) as a two's complement.
Effects on the condition codes
H :
Not affected.
I :
"
N :
"
"
Z :
V :
C :
"
"
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
Operand
format
RELATIVE
BGE
ReI
1st
byte
2nd
byte
2C
ReI
I
~HITACHI
44
3rd
byte
Bytes
of
instr.
code
CPU
cycles
2
3
/
Branch i f Greater Than zero
Category
Conditional
branch
BGT
Function
I
(PC) + 0002 + Rel I f (Z)0[ (N)€D(V) 1 = 0
PC that is, (ACCX) > (M) ; in the case of two's complement
Branches i f z=O and N&V=l or i f Z=O and N&V=O.
When a BGT instruction is executed immediately
after an instruction such as CBA, CMP, SBA or SUB
has been executed, a branch occurs i f the minuend
(ACCX) as a two's complement is greater than the
subtracter (M) as a two's complement.
Effects on the condition codes
H : Not affected.
I :
N :
Z :
V :
C :
"
"
"
"
"
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
Operand
format
RELATIVE
BGT
Rel
1st
byte
2nd
byte
2E
Rel
3rd
byte
Bytes
of
instr.
code
2
CPU
cycles
3
~HITACHI
45
/
Branch if HIgher
BHI
Function
Category
(PC) + 0002 + Rel
I f (C)0(Z) = 0
PC That is, (ACCX) > (M) ; in the case of unsigned binary
Conditional
branch
Branches i f C=O and z=o.
When a BHI instruction
is executed immediately after an instruction such
as CBA, CMP, SBA or SUB has been executed, a branch
occurs i f the minuend (ACCX) as a unsigned binary
is greater than the subtracter (M) as a unsigned
binary.
Effects on the condition codes
H :
Not affected.
I :
N :
Z :
"
"
"
V :
"
C :
"
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
Operand
format
RELATIVE
BHI
Rel
1st
byte
2nd
byte
22
Rel
~HITACHI
46
3rd
byte
Bytes
of
instr.
code
CPU
cycles
2
3
I
BIt Test
Function
Category
Logic
operation
.
(ACCX)
BIT
-_._-
I
(M)
Performs the logical "AND" operation between
the contents of ACCX and those of memory (M) .
Then, the condition codes reflect the result_
The contents of the ACCX and those of memory M remain
unchanged_
Effects on the condition codes
H : Not affected.
I
: Not affected.
N = R7:
Z
=
Set i f the result's MSB is "111; cleared otherwise.
R7'R6-R5-R4'R3-R2'Rl'RO:
Set i f all bits of the result are
zeros; cleared otherwise.
V
=
0:
Cleared.
C : Not affected.
modes and CPU cycles
Address~ng
Addressing
mode
Instruction code
Operand
format
Mnemonic
1st
byte
2nd
byte
3rd
byte
Bytes
of
instr.
code
CPU
cycles
IMMED
BIT
A
# Irnrn
85
Irnrn
2
2
DIRECT
BIT
A
M
95
1-1
2
3
EXTND
BIT
A
M
B5
MH
3
4
INDEX
BIT
A
Disp,X
AS
Disp
2
4
ML
IMMED
BIT
B
# Irnrn
C5
Irnrn
2
2
DIRECT
BIT
B
M
05
M
2
3
EXTND
BIT
B
M
F5
MH
3
4
INDEX
BIT
B
Disp, X
E5
Disp
2
4
ML
~HITACHI
47
/
Branch. if Less than or Equal to zero
BLE
Function
Category
Conditional
branch
PC
-
(PC) + 0002 + Rel
I f (Z) 0 [ (N) ED (V) 1 = 1
(ACCX) ~ (M) ; in the case of two's complement
That is,
Branches i f Z=l or N=l & v=o or N=O & V=l.
When aBLE instruction is executed immediately
after an instruction such as CBA, CMP, SBA or SUB
has been executed, a branch occurs i f the minuend
(ACCX) as a two's complement is smaller than, or
equal to, the subtracter (M) as a two's complement.
Effects on the condition codes
H :
Not affected.
I :
N :
Z :
V :
C :
"
"
"
"
"
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
Operand
format
RELATIVE
BLE
Rel
1st
byte
2nd
byte
2F
Rel
i
~HITACHI
48
3rd
byte
Bytes
of
instr.
code
CPU
cycles
2
3
/
Branch i f Lower or Same
Category
BLS
Function
,_.
---
-
(PC) + 0002 + Rel I f (C) e (Z) = 1
That is, (ACCX) ~ (M) ; in the case of unsigned binary
PC
Conditional
branch
Branches i f C=l or Z=l.
When a BLS instruction is executed immediately
after an instruction such as CBA, CMP, SBA or SUB
has been executed, a branch occurs i f the minuend
(ACCX) as a unsigned binary is smaller than, or
equal to, the subtracter (M) as a unsigned binary.
Effects on the condition codes
H :
Not affected.
:
It
N :
It
Z :
It
V :
It
C :
It
I
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
Operand
format
RELATIVE
BLS
Rel
1st
byte
2nd
byte
23
Rel
3rd
byte
Bytes
of
instr.
code
2
CPU
cycles
3
~HITACHI
49
/
Branch if Less Than zero
BLT
Function
Category
Conditional
branch
(PC) + 0002 + ReI
I f (N) 61 (V) = 1
PC That is, (ACCX) < (M) 1 in the case of two's complement
Branches if N=l
&
V=O or N=O
&
V=l.
When a BLT instruction is executed immediately
after an instruction such as CBA, CMP, SBA or SUB
has been executed, a branch occurs if the minuend
(ACCX) as a two's complement is smaller than the
substracter (M) as a two's complement.
Effects on the condition codes
H :
Not affected.
I :
N :
Z :
V :
C :
"
"
"
"
"
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
Operand
format
RELATIVE
BLT
ReI
1st
byte
2nd
byte
20
ReI
~HITACHI
50
3rd
byte
Bytes
of
instr.
code
2
CPU
cycles
3
/
Branch if MInus
BMI
Function
Category
Conditional
branch
PC -
(PC) + 0002 + Rel
I
If (N) = 1
Tests the state of negative bit N and causes a branch
i f N=l.
Effects on the condition c0des
H :
Not affected.
I :
N :
"
"
Z :
"
"
"
V :
C :
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
Operand
format
RELATIVE
BNI
Rel
Instruction code
1st
byte
2nd
byte
2B
Rel
3rd
byte
Bytes
of
instr.
code
CPU
cycles
2
3
~HITACHI
51
/
Branch if Not Equal
BNE
Function
Category
Conditional
branch
PC -
(PC) + 0002 + ReI
I f (Z)
=
0
Tests the state of zero bit Z and causes a branch
if
z=o.
-
Effects on the condition codes
H :
I :
N :
Z :
V :
C :
Not affected.
"
"
"
"
"
Addressing modes and CPU cycles
Addressing
mode
RELATIVE
Mnemonic
BNE
Operand
format
ReI
$
52
Instruction code
1st
byte
2nd
byte
26
ReI
HITACHI
3rd
byte
Bytes
of
instr.
code
2
CPU
cycles
3
/
Branch if PLus
Category
BPL
Function
Conditiona1
branch
PC
-
(PC) + 0002 + Rel.
I
I f (N) = 0
Tests the state of negative bit N and causes a branch
i f N=O.
Effects on the condition codes
H :
I
Not affected
:
N :
Z :
V :
C :
"
"
"
"
"
Addressing modes and CPU cycles
Addressing
mode
RELATIVE
Instruction code
Mnemonic
BPL
Operand
format
Re1
1st
byte
2nd
byte
2A
Re1
3rd
byte
Bytes
of
instr.
code
2
CPU
cycles
3
~HITACHI
53
/
BRanch Always
Category
BRA
Function
P C - (PC) + 0002 + Rel
Unconditional
branch &
jump
Branches unconditionally to the address resulting
from the above expression. "Rel" is the relative
address stored as a two's complement in the second
byte of the machine code of a branch instruction.
Effects on the condition codes
H :
Not affected.
I :
N :
Z :
V :
C :
"
"
"
"
"
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
Operand
format
RELATIVE
BRA
Rel
Instruction code
1st
byte
2nd
byte
20
Rel
~HITACHI
54
3rd
byte
Bytes
of
instr.
code
2
CPU
cycles
3
I
BRanch Never
Category
BRN
Function
Unconditional
branch &
jump
I
P C - (PC) + 0002
A two-byte 3-cycle instruction that is equivalent to
NOP instruction. As a feature of the HD6301,
this instruction provides a function opposite to the
BRA instruction.
Note:
The second byte of the instruction code takes
an arbitrary value (0 to $FF) at which a
branch may occur.
Effects on the condition codes
H
I
N
:
Not affected.
:
II
:
II
Z
:
II
V
C
:
II
:
II
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
Operand
format
RELATIVE
BRN
Rel
Instruction code
1st
byte
2nd
byte
21
Rel
3rd
byte
Bytes
of
instr.
code
2
CPU
cycles
3
~HITACHI
55
I
Bit SET
BSET
Function
Category
Logic
operi'\tion
Mi --- 1
Sets bit i of the memory.
are not affected.
*
(i = 0 to 7)
Other bits
The machine code of this instruction is the same as
OIM.
Effects on the condition codes
H : Not affected.
I : Not affected.
N = R7: Set i f the result's MSB is "1"i cleared otherwise.
Z = R7 • R6 • R5 • R4 • R3 • R2 • Rl . RO :
Set i f the result is zero; cleared
otherwise.
V = 0:
Cleared.
C : Not affected.
Addressing modes and CPU
~ycles
Instruction code
Addressing
mode
Mnemonic
DIRECT
BSET
"
Operand
format
CPU
cycles
1st
byte
2nd
byte
3rd
byte
o ,M
72
01
M
3
6
BSET
1,M
"
"
2,M
04
"
"
"
"
"
"
"
"
BSET
3,M
BSET
4,M
"
"
"
"
02
BSET
BSET
5,M
6,M
BSET
7,M
"
80
INDEX
BSET
O,Disp,X
62
01
"
"
"
"
"
"
"
BSET
1,Disp,X
02
BSET
2,Disp,X
BSET
08
"
"
"
"
10
"
"
"
20
"
40
"
"
"
"
"
"
"
"
"
"
3
7
"
"
"
"
"
"
"
I
I
Disp
BSET
3,Disp,X
BSET
4,Disp,X
BSET
5,Disp,X
"
"
"
"
"
BSET
6,Disp,X
"
40
"
"
"
"
"
"
BSET
7,Disp,X
"
80
"
~HITACHI
56
Bytes
of
instr.
code
04
08
10
20
"
"
"
"
"
"
"
"
/
Branch to SubRoutine
BSR
Function
Category
Subroutine
control
PC
I
SP
I
-
(PC) + 0002
(PCL)
-
(SP)
-
0001
(PCH)
SP
-
(SP) - 0001
(PC) + Rel
PC -
I
1. Increments the PC by two.
2. Saves the low-order byte of the
program counter into the stack.
3. Decrements the SP by one.
4. Saves the high-order byte of
the PC into the stack.
5. Decrements the SP by one.
6. Branches to the address
indicated by the program.
Effects on the condition codes
H :
Not affected.
I :
N :
Z
:
V :
C :
.
..
.
.
.
Addressing modes and CPU cycles
Instruction code
Addressing'
mode
Mnemonic
Operand
format
RELATIVE
BSR
Rel
1st
byte
80
2nd
byte
Rel
3rd
byte
Bytes
of
instr.
code
2
CPU
cycles
5
~HITACHI
57
/
Bit ToGgLe
BTGL
Function
Category
Logic
operation
Mi MI
Inverts bit i of the memory M.
(i = 0 to 7)
Other
bits are not affected.
NOTE) BTGL has the same instruction code as ElM.
Effects on the condition codes
H : Not affected.
I
: Not affected.
Set i f the result's MSB is "l"; cleared otherwise.
Z = R7 . R6 . R5 • R4 . R3 • R2 • Rl . RO :
Set i f the result is zero; cleared
otherwise.
N : R7:
V = 0:
Cleared.
C : Not affected.
Addressing modes and CPU cycles
Instruction code
Operand
format
CPU
cycles
Mnemonic
DIRECT
BTGL
D,M
75
01
M
3
6
"
"
"
"
"
"
BTGL
I,M
02
BTGL
2,M
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
3
7
"
"
"
"
"
------,.
"
"
"
"
"
"
1st
byte
2nd
byte
"
BTGL
7,M
"
"
"
"
"
"
"
INDEX
BTGL
O,Disp,X
65
01
"
"
"
"
"
BTGL
1,Disp,X
"
02
BTGL
2,Disp,X
04
BTGL
3,Disp,X
"
"
BTGL
4,Disp,X
5,Disp,X
"
"
BTGL
.6,Disp,X
BTGL
7,Disp,X
"
"
"
"
10
BTGL
BTGL
3,M
BTGL
4,M
BTGL
5,M
BTGL
6,M
04
08
10
20
40
80
08
20
40
80
~HITACHI
58
Bytes
of
instr.
code
Addressing
mode
3rd
byte
Disp
"
"
"
"
" " - -"
..
II
"
"
/
Bit TeST
Category
.
Logic
operation
BTST
Function
Mi
1
Performs the logical "AND" operation between bit i
I
(i=O to 7) of the memory M and Ill".
Then, the condition codes reflect the result.
NOTE)
BTST has the same instruction code as TIM.
Effects on the condition codes
H : Not affected.
I : Not affected.
N = R7:
Set i f the result's MSB is "l"i cleared otherwise.
Set i f the result is zero; cleared
otherwise.
Z = R7·R6·RS·R4.R3·R2·Rl·RO:
V =
0:
Cleared.
C : Not affected.
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
DIRECT
BTST
o,M
BTST
1,M
2,M
i,
II
II
II
II
II
II
BTST
Operand
format
3rd
byte
7B
01
M
3
"
02
II
II
04
II
II
08
II
II
10
20
II
II
II
"
40
II
II
II
II
II
II
3,M
4,M
II
BTST
S,M
II
BTST
6,M
II
80
01
BTST
II
BTST
7,M
II
INDEX
BTST
O,Disp,X
6B
1,Disp,X
II
2,Disp,X
II
II
II
BTST
BTST
CPU
cycles
2nd
byte
1st
byte
II
BTST
Bytes
of
instr.
code
Disp
4
II
II
II
II
II
3
5
02
II
II
II
04
II
II
II
II
II
II
II
BTST
3,Disp,X
II
08
II
II
BTST
4,Disp,X
II
10
II
II
II
BTST
S,Disp,X
II
20
II
II
II
40
II
II
II
80
II
II
II
II
BTST
6,Disp,X
II
II
BTST
7,Dis: ,X
II
~HITACHI
59
/
Branch if oVerflow Clear
Category
BVe
Function
Conditional
branch
(PC) + 0002 + Rel
PC -
If (V)
=
0
Tests the state of overflow bit V and causes a branch
i f V = o.
Effects on the condition codes
H :
Not affected.
I :
N :
Z :
V :
C :
"
"
"
"
"
Addressing modes and· CPU cycles
Addressing
mode
Mnemonic
Operand
format
RELATIVE
BVC
Rel
Instr\lction code
1st
byte
2nd
byte
28
Rel.
~HITACHI
60
3rd
byte
Bytes
of
instr.
code
2
CPU
cycles
3
/
Branch i f oVerflow Set
BVS
Function
Category
Conditional
branch
(PC) + 0002 + ReI
PC -
If
(V)
=
1
Tests the state of overflow bit V and causes a branch i f
V
=
l.
Effects on the condition codes
H :
I
Not affected.
:
N :
"
"
Z :
"
V :
"
"
C :
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
Operand
format
RELATIVE
BVS
ReI
1st
byte
2nd
byte
29
ReI
3rd
byte
Bytes
of
instr.
code
2
CPU
cycles
3
~HITACHI
61
/
Compare Accumulators
Function
Category
Compare
test
CBA
(ACCA)
&
-
(ACCB)
Compares the contents of ACCA to those of ACCB and
sets the condition codes according to the result.
Used for a conditional branch in arithmetic or
logical operation.
Both operands are not
affected.
Effects on the condition codes
H : Not affected.
I
: Not affected.
N
=
=
Z
Set i f the MSB of the result is "1"; cleared otherwise.
R7· R6. R5· R4. R3· R2. Rl. RO:
Set i f the result is zero; cleared
R7:
otherwise.
V
=
A7·B7·R7GA7·B7·R7:
otherwise.
Set i f the result overflows;
C
=
A7·B70B7·R7GR7·A7:
Set if a borrow is generated; cleared
cleared
otherwise.
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
CBA
IMPL
Operand
format
1st
byte
11
I
~HITACHI
62
2nd
byte
3rd
byte
---
Bytes
of
instr.
code
1
CPU
cycles
1
/
CLear Carry
CLC
Function
Category
Bit
control
Bit C -
0
Clears carry bit C.
Effects on the condition codes
H :
Not affected.
N :
"
"
Z :
"
I :
V :
C=O :
"
Cleared.
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
IMPL
CLC
Operand
format
1st
byte
OC
2nd
byte
3rd
byte
Bytes
of
instr.
code
CPU
cycles
1
1
~HITACHI
63
/
CLear Interrupt mask
CLI
Function
Category
Bit I
Bit
control
-
0
Clears the interrupt mask bit I of the condition code.
When an interrupt occurs in response to an interrupt
request from a peripheral, this instruction enables
the microprocessor to receive the interrupt request.
Effects on the condition codes
H :
Not affected.
I=O :
N :
Z :
V :
C :
Cleared.
Not affected.
"
"
"
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
IMPL
CLI
Operand
format
1st
byte
OE
~HITACHI
64
2nd
byte
3rd
byte
Bytes
of
instr.
code
CPU
cycles
1
1
/
CLeaR
Category
CLR
Function
Arithmetic
operation
(One
operand)
I
ACCX --- 00 or M --- 00
Cleares the contents of ACCX or those of memory M
to zero.
Effects on the condition codes
H :
Not affected.
I :
"
N=O :
Z=l :
Cleared.
Set·
v=o :
Cleared.
c=o :
Cleared.
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
ACCX
CLR
A
4F
ACCX
CLR
B
SF
EXTND
CLR
M
7F
MH
INDEX
CLR
Disp,X
6F
Disp
Operand
format
1st
byte
2nd
byte
3rd
byte
ML
Bytes
of
instr.
code
CPU
cycles
1
1
1
3
S
2
S
1
~HITACHI
65
:
/
CLear two's complement oVerflow bit
Category
CLV
Function
Bit
control
Bit V -
0
Clears the overflow bit V of the condition code.
Effects on the condition codes
H :
Not affected.
I :
N :
"
Z :
"
V=O :
Cleared.
C :
"
Not affected.
Addressing modes and CPU cycles
Instruction code
Addr.essing
mode
Mnemonic
IMPL
CLV
Operand
format
1st
byte
OA
~HITACHI
66
2nd
byte
3rd
byte
Bytes
of
instr.
code
CPU
cycles
1
1
/
CoMPare
Function
Category
Compare
CMP
-
(ACCX)
(M)
.&
Test
Compares the contents of ACCX to those of memory M
and changes the condition codes 'according to the
result.
The contents of the condition codes may
be referenced by the following conditional branch
instruction.
Both operands are not affected.
Effects on the condition codes
H : Not affected.
I
:
Not affected.
Set if the MSB of the result is "111; cleared otherwise.
Set i f the result is zero; cleared
Z = R7· R6· R5· R4· R3· R2 ·Rl· RO:
N = R7:
otherwise.
Set i f the result overflows; cleared
V = X7·M7·R7@X7·M7·R7:
otherwise.
C = X7·M78M7·R7@R7·X7: Set if the absolute value of the memory
is greater than those of the accumulator; cleared otherwise.
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
Operand
format
1st
byte
2nd
byte
3rd
byte
Bytes
of
instr.
code
CPU
cycles
IMMED
CMP
A
iImm
81
Imm
2
2
DIRECT
CMP
A
M
91
M
2
3
EXTND
CMP
A
M
B1
MIl
3
4
INDEX
CMP
A
Disp,X
A1
Disp
2
4
ML
IMMED
CMP
B
iImm
C1
Imm
2
2
DIRECT
CMP
B
M
D1
M
2
3
EXTND
CMP
B
M
F1
MH
3
4
INDEX
CMP
B
Disp,X
E1
Disp
2
4
ML
~HITACHI
67
/
COMplement
Function
Category
Logic
operation
COM
ACCX -(ACCX) = FF
M-_(M) = FF - (M)
-
(ACCX) or
Takes one's complement of each bit in ACCX or
memory M.
Effects on the condition codes
Not affected.
I : Not affected.
N = R7: Set i f the result's MSB is "1"; cleared otherwise.
Z = R7'R6'R5'R4'R3'R2'Rl'RO: Set i f the result is zero; cleared
otherwise.
V = 0:
Cleared.
C = 1: Set.
,
H :
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
ACCX
ACCX
EXTND
INDEX
COM
COM
COM
COM
Operand
format
Instruction code
1st
byte
2nd
byte
43
53
A
B
M
Disp,X
73
63
MH
Disp
~HITACHI
68
3rd
byte
ML
Bytes
of
instr.
code
CPU
cycles
1
1
1
3
6
6
2
1
/
ComPare indeX register
Category
CPX
Function
Index
register
control
-
(IX)
I
(M : M + 1)
Compares the contents of the IX to those
of memories M and M+l.
Effects on the condition codes
H : Not affected.
I
: Not affected.
N
=
=
Z
R1S:
(RlS· Rl4 . R13· R12· RH· RIO· R9· RB . R7· R6· R5· R4 . R3 . R2· RI· RO)
:
V
=
Set i f the MSB of the result is "lili cleared otherwise.
Set i f the result is "0"; cleared otherwise.
IXIS·MlS·R1S@IXlS·MlS·RIS:
Set i f the result overflows; and
cleared otherwise.
C
=
IXIS·MIS@MlS·R1S@RlS·IXIS:
Set i f the absolute value of the
memory is greater than that of the index register; cleared
otherwise.
Addressing modes and CPU cycles
Addressing
mode
IMMED
Instruction code
Operand
format
Mnemonic
CPX
#Imm
1st
byte
2nd
byte
BC
ImmH
DIRECT
CPX
M
9C
M
EXTND
CPX
M
BC
MH
INDEX
CPX
Disp,X
AC
Disp
3rd
byte
ImmL
ML
Bytes
of
instr.
code
3
CPU
cycles
3
2
4
3
S
2
S
@HITACHI
69
/
Decimal Adjust ACCA
DAA
Function
Category
Bit C before
OAA
High-order
4 bits
IBits 4 - 71
Ini tial bi t H
(Half carry)
Low-order
4 bits
i(Bits 0 - 3)
Hex. data
added to
ACCX by OAA
Bit c after
OAA
0
0
0
0
0
0
I
I
I
0-9 0-8 0-9 A-F 9-F A-F 0-2 0-2 0-3
0
0
I
0
0
I
0
0
I
0-9 A-F 0-3 0-9 A-F 0-3 0-9 A-F 0-3
I
00
06
06
60
66
66
60
66
66
0
0
0
I
I
I
I
I
I
Adds the hexadecimal data,
00, 06, 60 and
66, to ACCA
according to
the table.
For BCO(binarycoded decimal)
addition by an
instruction
such as ABA,ADD
or ADC, OAA
executes this
function if the
result is in
bits C and H of
ACCA.
Effects on the condition codes
Not affected.
I : Not affected.
N : R7: Set if the MSB of the result is "1", cleared otherwise.
Z m~·R·B·u·n·U·n·Mr Set i f the result is zero, cleared
otherwise.
V : Not affected.
C : Set or cleared as shown in the above table.
H :
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
IMPL
DAA
Operand
format
Instruction code
1st
byte
19
~HITACHI
70
2nd
byte
3rd
byte
Bytes
of
instr.
code
CPU
cycles
1
2
/
DECrement
DEC
Function
Category
Arithmetic
operation
(ACCX)
ACCX M-
(M)
-
- 01
or
I
01
Subtracts 1 from the contents of ACCX or those
of memory M.
Bits N, Z and V are set according
to the result.
Bit C is not affected.
Effects on the condition codes
H : Not affected.
I : Not affected.
Z
=
=
V
=
N
R7:
Set i f the MSB of the result is 111"; cleared otherwise.
R7·R6·RS·R4·R3·R2·R1·RO:
otherwise.
Set i f the result is zero; cleared
= R7·R6·RS·R4·R3·R2·R1·RO
Set i f the result overflows; cleared otherwise.
X7·X6·XS·X4·X3·X2·X1·XO
:
An over-
flow occurs i f the contents of ACCX or those of the memory
before operation are 80.
C : Not affected.
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
ACCX
DEC
A
ACCX
DEC
B
EXTND
DEC
M
7A
MH
INDEX
DEC
Disp,X
6A
Disp
Operand
format
1st
byte
2nd
byte
3rd
byte
4A
SA
ML
Bytes
of
instr.
code
CPU
cycles
1
1
1
1
3
6
2
6
~HITACHI
71
/
DEcrement Stack pointer
DES
Function
Category
S P - (SP) - 0001
Stack
pointer
control
Subtracts 1 from the SP.
Effects on the condition codes
H :
I
.
Not affected.
II
N :
II
Z :
II
V :
II
C :
II
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
IMPL
DES
Operand
format
Instruction code
1st
byte
34
~HITACHI
72
2nd
byte
3rd
byte
Bytes
of
instr.
code
1
CPU
cycles
1
/
DEcrement indeX register
Function
category
Index
register
control
DEX
( IX)
IX -
-
I
0001
Subtracts 1 from the IX_
Bit Z is set or reset according to the result_
Effects on the condition codes
H : Not affected_
I : Not affected_
N : Not affected_
Z =
(RH7-RH6·RHS·RH4-RH3-RH2-RH1-RHO)· (RL7·RL6·RLS·RL4·RL3·RL2·
RLl.RLO) :
Set i f the result is zero; cleared otherwise_
V : Not affected ...
C : Not affected.
Addressing modes and CPU cycles
Addressing
mode
IMPL
Instruction code
Mnemonic
DEX
Operand
format
1st
byte
09
2nd
byte
3rd
byte
Bytes
of
instr.
code
1
CPU
cycles
1
~HITACHI
73
I
E-or IMmediate
category
Logic
operation
Function
M - 1M
$
ElM
--
(M)
Performs the logical exclusive "OR" operation
between the immediate data and the contents of
memory M, and stores the result into the memory M.
Effects on the condition codes
Not affected.
I : Not affected.
N = M7: Set i f the M's MSB is "1"; cleared otherwise.
Z = M7 ·M6 ·M5 ·M4 ·M3 ·M2 ·Ml·MO:
Set i f the contents of M is zero,
cleared oth~rwise.
V = 0:
Cleared.
C : Not affected.
H :
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
DIRECT
INDEX
ElM
ElM
Operand
format
#Imm,M
#Imm,Disp,X
Instruction code
1st
byte
2nd
byte
3rd
byte
75
65
Imm
Imm
M
Disp
Bytes
of
instr.
code
CPU
cycles
3
6
3
7
--
~HITACHI
74
L
Exclusive OR
Category
Logic
operation
EOR
Function
(ACCX)
ACCX -
(Jl
I
(M)
Performs the logical exclusive "OR" operation between
the contents of ACCX and those of memory M, and stores
the result into the ACCX.
Effects on the condition codes
H : Not affected.
I
:
N
= R7 : Set i f the MSB of the result is
= R7 . R6 . RS . R4 . R3 . R2 . Rl . RO : Set i f the
Z
Not affected.
'.1 11
i
cleared otherwise.
result is zero; cleared
otherwise.
V
=
0:
Cleared.
C : Not affected.
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
IMMED
EOR
A
Umm
Operand
format
1st
byte
2nd
byte
88
Imm
3rd
byte
Bytes
of
instr.
code
CPU
cycles
2
2
DIRECT
EOR
A
M
98
M
EXTND
EOR
A
M
B8
MH
INDEX
EOR
A
Disp,X
A8
Disp
2
4
IMMED
EOR
B
C8
Imm
2
2
DIRECT
EOR
B
Umm
M
D8
M
2
3
EXTND
EOR
B
M
F8
MH
INDEX
EOR
B
Disp,X
E8
Disp
ML
ML
2
3
3
4
3
4
2
4
@HITACHI
75
/
INCrement
Function
Catego.ry
Arithmetic
operation
INC
ACCX M-
(ACCX) + 01 or
(M) + 01
Adds 1 to the contents of ACCX or those of
memory M. Bits N, Z and V are set according to
Bit C is not affected.
the result.
Effects on the condition codes
H : Not affected.
I : Not affected.
Z
=
=
set i f the MSB of the result is "111; cleared otherwise.
R7·R6·RS·R4·R3·R2·Rl·RO: Set i f the result is zero; cleared
V
=
X7'X6-XS-X4-X3'X2-Xl'XO
N
R7:
otherwise.
= R7 - R6 - RS . R4 - R3 - R2 - Rl . RO
cleared otherwise_ An overthe
result
overflows;
:
Set i f
flow occurs i f the contents of ACCX or those of the memory
before operation are 7F.
C : Not affected.
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
ACCX
INC
A
ACCX
INC
B
EXTND
INC
M
7C
MH
INDEX
INC
Disp,X
6C
Disp
Operand
format
1st
byte
2nd
byte
4C
1
SC
~HITACHI
76
3rd
byte
Bytes
of
instr.
code
ML
CPU
cycles
1
1
1
3
6
2
6
/
INcrement Stack pointer
INS
Function
Category
Stack
pointer
control
SP -
I
(SP) + 0001
Adds 1 to the SP.
Effects on the condition codes
H :
Not affected.
N :
"
"
I
:
Z :
"
V :
"
C :
"
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
IMPL
INS
Operand
format
1st
byte
31
2nd
byte
3rd
byte
Bytes
of
instr.
code
1
CPU
cycles
1
~HITACHI
77
/
INcrement indeX register
Function
category
Index
register
control
INX
I X - (IX) + 0001
Adds 1 to the IX. Only bit Z is set
or reset according to the result.
Effects on the condition codes·
H : Not affected.
I : Not affected.
N : Not affected.
Z = (RH7·RH6·RHS·RH4·RH3·RH2·RH1·RHO)· (RL7·RL6·RLS·RL4·RL3·RL2·
RL1·RLO) : set i f the result ·is zero; cleared
otherwise.
V : Not affected.
C : Not affected.
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
IMPL
INX
Operand
format
Instruction code
1st
byte
2nd
byte
3rd
byte
Bytes
of
instr.
code
1
08
CPt}
cycles
1
i
I
I
~HITACHI
78
--
/
JuMP
JMP
Function
category
PC -
Unconditional
branch &
jump
I
address
Branches to the instruction at the specified address.
The branch destination is computed by using extended
addressing or indexed addressing modes.
Effects on the condition codes
H :
I :
N :
Z
:
V :
C :
Net affected.
"
"
"
"
"
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
EXTND
JMP
INDEX
JMP
Operand
format
1st
byte
2nd
byte
3rd
byte
M
7E
MH
ML
Disp,X
6E
Disp
Bytes
of
instr.
code
~PQ
cycles
._-
3
3
2
3
~HBTACHI
79
/
Jump to SubRoutine
Category
JSR
Function
Subroutine
control
PC
t
SP
I
SP
PC
Increments the program counter
(PC)+OOO3(EXTND)
PC or
-
-
by two or three according to
(PC)+OOO2(INDEX)
the addressing mode, saves .it
(PCL)
in the 2-byte stack, and
(SP)-OOOl
updates the stack pointer.
Then branches to the specified
(PCH)
address. The branch destination is computed by using
(SP)-OOOl
numeric address
extended addressing or indexed
addressing.
Effects on the condition codes
H :
I
Not affected.
:
N :
Z :
V :
C
:
"
"
"
"
.,
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
EXTND
JSR
INDEX
DIRECT
Operand
format
1st
byte
2nd
byte
3rd
byte
M
BD
MH
ML
JSR
Disp,X
AD
Disp
JSR
M
90
M
Bytes
of
instr.
code
C!>y
cycles
3
6
2
5
2
5
--~HITACHI
80
/
LoaD Accumulator
Function
category
Transfer
LOA
I
(M)
ACCX -
Loads the contents of memory M into the ACCX.
Effects on the condition codes
H : Not affected.
I
: Not affected.
Set i f the MSB of the result is "111; cleared otherwise.
Z = R7· R6· RS· R4 . R3· R2· Rl· RO:
Set if the result is zero; cleared
N = R7 :
otherwise.
V =
0:
Cleared.
C : Not affected.
Addressing modes and CPU cycles
Instruction code
Bytes
of
instr.
code
CPU
cycles
Addressing
mode
Mnemonic
IMMED
LOA
A
#Imm
86
Imm
2
2
DIRECT
LOA
A
M
96
M
2
3
EXTND
LOA
A
M
B6
MH
3
4
INDEX
LOA
A
Disp,X
A6
Disp
2
4
IMMED
LOA
B
#Imm
C6
Imm
2
2
DIRECT
LOA
B
M
06
M
2
3
EXTND
LOA
B
M
F6
MH
3
4
INDEX
LOA
B
Disp,X
E6
Disp
2
4
Operand
format
1st
byte
2nd
byte
3rd
byte
ML
ML
~HITACHI
81
Doubl~
/
LoaD accumulator A:B
Function
Category
-
ACeD
Load &
store
LDD
(M:M+l)
Loads the 2-byte contents of memories M and M+l
into ACCD.
Effects on the condition codes
H : Not affected.
I : Not affected.
N = R1S:
Set i f the result's MSB is "1"; cleared otherwise.
Z = R1S·R14·R13 .......... RO: Set i f the result is zero; cleared
otherwise.
V = 0:
C :
Cleared.
Not affected.
Addressing modes and CPU cycles
Addressing
mode
Instruction code
Mnemonic
Operand
format
1st
byte
2nd
byte
3rd
byte
CC
ImmH
ImmL
IMr-1ED
LDD
DIRECT
LDD
Umm
M
DC
M
EXTND
LDD
M
FC
MH
INDEX
LDD
Disp,X
EC
Disp
~HITACHI
82
HL
-Bytes
of
instr.
code
3
CPU
cycles
3
2
4
3
5
2
5
/
LoaD Stack pointer
category
Stack
pointer
control
LOS
Function
--
SPH
SPL
(M)
(M+l)
I
Loads the contents of memory M into the upper byte
of the SP.
Then, loads the contents of memory M+l (which results
when memory address M is incremented by one) into the
Lower byte of the SP.
,
Effects on the condition codes
H : Not affected.
I : Not affected.
N = RH7: Set. i f the MSB of the SP is "111; cleared otherwise.
Z = (RH7'RH6'RHS'RH4'RH3'RH2'RH1'RHO)' (RL7'RL6'RLS'RL4'RL3'RL2'
RLl.RLO) : Set i f the SP contents is zero after the load;
cleared otherwise.
cleared.
0:
=
C : Not affected.
V
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
IMMEO
DIRECT
EXTNO
INDEX
LOS
LOS
LOS
LOS
Operand
format
ItImm
M
M
Oisp,X
Instruction code
1st
byte
2nd
byte
3rd
byte
BE
9E
BE
AE
ImmH
M
MH
Oisp
ImmL
ML
Bytes
of
instr.
code
3
2
3
2
CPU
cycles
3
4
5
5
~HITACHI
83
/
LoaD indeX register
LDX
Function
Category
Ind"ex
register
control
-
IXH
-
IXL
(M)
(M+l)
Loads the contents of memory M into the upper
byte of the IX.
Then, loads the contents of
memory M+I into the lower byte of the IX.
Effects on the condition codes
H : Not affected.
I : Not affected.
N
Z
=
=
RH7:
Set i f the MSB of the IX is "I"; cleared otherwise.
(RH7·RH6.RHS·RH4·RH3·RH2·RHI·RHO)· (RL7·RL6·RLS·RL4·RL3·RL2·
RLI·RLO) : Set if the IX contents is zero after the load;
cleared otherwise.
= 0: Cleared.
C : Not affected.
V
Addressing modes and CPU cycles
I
Addressing
mode
Instruction code
Mnemonic
Operand
format
1st
byte
2nd
byte
3rd
byte
CE
ImmH
ImmL
DE
M
IMMED
LDX
DIRECT
LDX
Umm
M
EXTND
LDX
M
FE
MH
INDEX
LDX
Disp,X
EE
Disp
ML
-
~HITACHI
84
Bytes
of
instr.
code
CPU
cycles
2
3
4
3
5
2
5
3
/
Logical Shift Right
Category
LSR
Function
Shift &
rotation
0-\ I I I I
bT
I
I
I
I
i
i
I
I
r:I
I-~
ila
Shifts the contents of ACCX or memory M by one bit
to the right.
Bit 7 takes O.
The bit C is loaded from the LSB of
~CCX
or memory M.
Effects on the condition codes
H : Not affected.
I : Not affected.
N = 0:
Z
=
Cleared.
....
R15'R14'R13
RO;
Set if the result is zero; cleared
otherwise.
Set if either N=l and C=O or N=O and C=l; cleared
otherwise.
V = NEIIC:
Note:
The N and Care those obtained after operation.
C = ABO: Set if the LSB of ACCX or M is a 1 before the
instruction is executed; cleared otherwise.
Addressing modes and CPU cycles
Addressing
mode
'Instruction code
Mnemonic
Operand
format
1st
byte
2nd
byte
3rd
byte
Bytes
of
instr.
code
CPU
cycles
ACCX
LSR
A
44
1
1
ACCX
LSR
B
54
1
3
1
6
2
6
EXTND
LSR
M
74
MH
INDEX
LSR
Disp,X
64
Disp
ML
~HITACHI
85
/
Logical Double Shift Right A:B
LSRD
Function
category
Shift &
rotation
0-1 I I i I I I I I
I I
I
I I I I
1-0
bo
b..
Shifts the contents of ACCD by one bit to the right.
Bit 15 takes O.
The bit C is loaded from the LSB of the AceD.
Effects on the condition codes
H : Not affected.
I
: Not affected.
N
=
0: Cleared.
----- ...... M;
Z = R15· R14. R13
:
Set i f the result is zero; cleared
otherwise.
V
= N61C:
Set i f either N=l and C=O or N=O and C=l; cleared
otherwise.
Note: The N and C are those obtained after operation.
C = ABO: Set i f the LSB of ACCD is "I" before the instruction
is executed; cleared otherwise.
--
Addressing modes and CPU cycles
Addressing
mode
IMPL
Instruction code
Mnemonic
LSRD
Operand
format
1st
byte
04
~HITACHI
86
2nd
byte
3rd
byte
------Bytes
of
instr.
code
CPU
cycles
1
1
/
MULtiply unsigned
Category
MUL
Function
Arithmetic
operation
ACCD
-
(ACCA)
* (ACCB)
I
Multiplies the contents of ACCA by those of ACCB,
and stores the resulting unsigned 16 bits into
ACCD.
The highest-order byte of the result is
stored into the ACCA.
I
Effects on the condition codes
H : Not affected.
I :
N :
"
"
Z
:
n
V
:
"
C = R7:
Set if the result's bit 7 is 11111; cleared otherwise.
Addressing modes and CPU cycles
Addressing
mode
IMPL
Instruction code
Mnemonic
MUL
Operand
format
1st
byte
3D
2nd
byte
3rd
byte
Bytes
of
instr.
code
CPU
cycles
1
7
~HITACHI
87
I
/
NEGate
Function
Category
Arithmetic
operation
NEG
ACCX -(ACCX) = OO-(ACCX) or
M - -(M) = OO-(M)
Takes two's complement of the contents of ACCX
or memory M, and stores the result into ACCX or
memory M.
No change is caused if the contents of
ACCX or memory M is $80(-128).
Effects on the condition codes
H : Not affected.
I : Not affected.
N = R7: Set i f the result's MSB is "1"; cleared otherwise.
Z = R1·Rb·R3"·R4·R3·R2·RT·RO: Set i f the result is zero; cleared
otherwise.
V = R7·R6·R3"·R4·R3·R2·R[·RO:
Set i f the result overflows;
cleared otherwise. The bit is set only when the contents of
ACCX or M is $80.
C = R79R69RS9R49R39R29R19RQ:
Set if a borrow is generated
cleared otherwise. The bit is set only when the contents of
ACCX or M is not zero.
Addressing modes and CPU cycles
Addressing
mode
ACCX
ACCX
EXTND
INDEX
Mnemonic
NEG
NEG
NEG
NEG
Operand
format
A
B
M
Disp,X
Instruction code
1st
byte
40
5.0
70
60
2nd
byte
MH
Disp
~HITACHI
88
3rd
byte
ML
Bytes
of
instr.
code
CPU
cycles
1
1
1
1
3
2
6
6
!
No OPeration
Category
NOP
Function
-~----
Unconditional
branch &
jump
I
Updates the program counter only and has no effect
on other registers.
I
Effects on the condition codes
H :
Not affected.
I :
II
N :
II
:
II
:
II
C :
II
Z
V
Addressing modes and CPU cycles
Addressing
mode
IMPL
Instruction code
l-1nemonic
NOP
Operand
format
1st
byte
01
2nd
byte
3rd
byte
Bytes
of
instr.
code
1
GfY
cycles
1
--
-~HITACHI
89
/
Or IMmediate
Category
OIM
Function
Logical
operation
M
-
1M 0 (M)
Ors the immediate data and the contents of
memory M, and stores the result into the
memory M.
Effects on the condition codes
H : Not affected.
I : Not affected.
Set i f the result's MSB is Ill"; cleared otherwise.
Z = R7·R6·R5·R4·R3·~·fl·RO:
Set i f the result is zero; cleared
otherwise.
N = R7"
V
= 0:
Cleared.
C : Not affected.
Addressing modes and CPU cycles
Addressing
mode
Instruction code
Mnemonic
Operand
format
1st
byte
2nd
byte
DIRECT
OIM
#Imm,M
72
Imm
INDEX
OIM
#Imm,Disp,X
62
Imm
3rd
byte
M
Disp
Bytes
of
instr.
code
3
3
CPU
cycles
6
7
"--
--
~HITACHI
90
/
inclusive OR
Logical
operation
ORA
Function
Category
ACCX
-
(ACCX) 0
(M)
I
Performs logical OR between the contents of ACCX
and the contents of memory M, and stores the
result into the ACCX,
Effects on the condition codes
H : Not affected,
I : Not affected,
Z
=
=
V
=
N
R7:
Set i f the result's MSB is 11111; cleared if not,
R7'R6'RS'R4'R3'R2'Rl'RO: Set i f all the bits of the result
are zero's; cleared otherwise,
0: Cleared,
C : Not affected.
Addressing modes and CPU cycles
Addressing
mode
Instruction code
Operand
format
Mnemonic
IMl4ED
ORA
A
1st.
byte
2nd
byte
#Imm
SA
Imm
3rd
byte
-Bytes
of
instr,
code
2
CPU
cycles
~
2
DIRECT
ORA
A
M
9A
M
EXTND
ORA
A
M
BA
MH
INDEX
ORA
A
Disp,X
AA
Disp
2
4
IMMED
ORA
B
#Imm
CA
Imm
2
2
DIRECT
ORA
B
M
DA
M
2
3
EXTND
ORA
B
M
FA
MH
3
4
INDEX
ORA
B
Disp,X
EA
I Disp
2
4
ML
ML
2
3
3
4
~HITACH8
91
/
PuSH data onto stack
PSH
Function
Category
Transfer
(ACCX)
f
SP
-
(SP) - 0001
Pushes the contents of ACCX onto the stack indicated
by the SP.
The SP is decremented by one.
Effects on the condition codes
H :
I
:
N :
Z
:
V
:
C :
Not affected.
"
.
"
"
"
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
ACCX
PSH
A
ACCX
PSH
B
Operand
format
Bytes
of
instr.
code
CPU
cycles
36
1
4
37
1
4
1st
byte
2nd
byte
i
~HITACHI
92
3rd
byte
/
PuSH indeX register onto stack
Category
Function
-
Transfer
PSHX
l
(IXL) , SP
I
(IXH), SP
-
-
(SP) - 0001
(SP) - 0001
I
PU$hes the contents of the IX onto the stack
indicated by the SP.
The SP is decremented by two.
I
Effects on the condition codes
H :
Not affected.
I :
"
N :
V :
"
"
"
C :
"
Z :
Addressing modes and CPU cycles
Addressing
mode·
IMPL
Instruction code
Mnemonic
PSHX
Operand
format
1st
byte
3C
2nd
byte
3rd
byte
Bytes
of
instr.
code
1
f;JlU
cycles
5
~HITACHI
93
/
PULl data from stack
PUL
Function
Category
Transfer
-
SP
t
(SP) + 0001
ACCX
Increments the SP by one, and pulls ACCX from
the stack.
Effects on the condition codes
H :
I
Not affected.
"
"
"
"
"
:
N :
Z :
V :
C :
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
PUL
ACCX
ACCX
Instruction code
-
PUL
Operand
format
1st
byte
A
32
B
33
3rd
2nd
byte; byte
I
Bytes
of
instr.
code
CPU
cycles
1
3
1
3
1
--
-
~HITACHI
94
/
PULl indeX register from stack
Category
PULX
Function
Transfer
SP
SP
-
-
(SP) + 0001 ;
(SP) + 0001 ;
t
I
IXH
t IXL
Increments the SP by one, and pulls the IX from
the stack.
The SP is incremented by two in total.
Effects on the condition codes
H :
I
:
N :
Z :
V :
C :
Not affected.
"
"
"
"
"
Addressirig modes and CPU cycles
Addressing
mode
IMPL
Instruction code
Mnemonic
PULX
Operand
format
1st
byte
38
2nd
byte
3rd
byte
Bytes
of
instr.
code
1
9..~g
cycles
4
~HITACHI
95
/
ROtate Left
Category
Shift &
rotation
ROL
Function
!
•
0-1 I I
I I,
I I I
b7
b.
1-0
Shifts the contents of ACCX or memory M by one bit
to the left.
The original value of bit C is moved
into bO, and the original value bit b7 to the bit C.
Effects on the condition codes
H : Not affected.
I
: Not affected.
N : R7:
Set if the MSB of the result is "111; cleared otherwise.
Set if all bits of the result are
zero's; cleared otherwise.
Z = R7·R6·RS·R4·R3·R2·Rl·RO:
V = N6lC:
Set if either N=l and C=O or N=O and C=l after the
instruction is executed; cleared otherwise.
Note: The N anc Care those obtained after operation.
C = M7: Set if the MSB of ACCX or M is "1" before the instruction
is executed; cleared otherwise.
Addressing modes and CPU cycles
Addressing
mode
Instruction code
Mnemonic
Operand
format
1st
byte
2nd
byte
ROL
A
ACCX
ROL
B
EXTND
ROL
M
79
l-m
INDEX
ROL
Disp,X
69
Disp
~HITACHI
1
1
49 _.
59
ACCX
1
I
96
3rd
byte
Bytes
of
, CPU
cycles
instr.
code
ML
-
1
3
6
2
6
/
ROtate Right
ROR
Function
Category
Shift &
rotation
p
@]-I i I I I I I I I-@]
bo
b.
Shifts the contents of ACCX or memory M by one bit
to the right.
The original value of bit C is
moved into bit 7 and the original value bit 0 to
the bit C.
Effects on the condition codes
H : Not affected.
I : Not affected.
N = R7: Set i f the MSB of the result is "1"; cleared otherwise.
Z = R1. g.Rs-.R'4. R!·iU·Rl·RO:
Set if the result is zero; cleared
otherwise.
Set if either N=l and c=o or N=O and C=l after the
V = NIIIC:
instruction is executed; cleared otherwise.
Note: The N and C are those obtained after operation.
C = MO: Set if the LSB of ACCX or M is "1" before the instruction
is executed; cleared otherwise.
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
ACCX
ACCX
EXTND
INDEX
ROR
ROR
ROR
ROR
Operand
format
Instruction code
1st
byte
2nd
byte
3rd
byte
46
A
B
56
M
Disp,X
76
66
MH
Disp
ML
Bytes
of
instr.
code
1
1
3
2
CPU
cycles
1
1
6
6
~HITACHI
97
I
ReTurn from Interrupt
Interrupt
control
RTI
Function
Category
--
SP
SP
SP
SP
SP
SP
SP
Pulls the
--
--
(SP) + 0001, fCC
(SP) + 0001, t ACCB
(SP) + 0001, f ACCA
(SP) + 0001, t IXH
(SP) + 0001, f IXL
(SP) + 0001, t PCH
(SP) + 0001, I PCL
CCR, ACCB, ACCA, IXH, IXL, PCH and from the
stack sequentially with incrementing SP by one at
a time.
Note that I=O results if the interrupt
mask bit I of CCR having been saved in the stack
is zero.
Effects on the condition codes
H : Set or cleared according to the bit pulled from the stack.
I :
"
N :
"
Z :
"
"
"
V :
C
:
Addressing modes and CPU cycles
Addressing
mode
IMPL
Mnemonic
RTI
Operand
format
Instruction code
1st
byte
3B
2nd
byte
3rd
byte
Bytes
of
instr.
code
CPU
cycles
1
10
--~HITACHI
98
/
ReTurn from Subroutine
RTS
Function
Category
Subroutine
control
-
SP
, PCH
(SP) + 0001
SP
(SP) + 0001
-
I
t PCL
Increments the SP by one and pulls the upper
byte of the PC from the stack.
Again increments
the SP by one, and pulls the lower byte of the
SP from the stack.
Effects on the condition codes
H :
I
Not affected.
:
"
N :
V :
"
"
"
C :
"
Z
:
Addressing modes and CPU cycles
Addressing
mode
IMPL
Instruction code
Mnemonic
Operand
format
1st
byte
2nd
byte
39
RTS
3rd
byte
Bytes
of
instr.
code
CPU
cycles
1
5
-
$
HITACHI
99
/
SuBtract Accumulators
Function
Category
Arithmetic
operation
SBA
ACCA -
(ACCA)
-
(ACCB)
Subtracts the contents of ACCB from those of ACCA,
and stores the result into the ACCA. The contents
of the ACCB remain unchanged.
Effects on the condition codes
Not affected.
I : Not affected.
N = R7: Set i f the result's MSB is "I"; cleared otherwise.
Z = R7·R6·R5·R4·R3·~·~·RO:
Set i f the result is zero~ cleared
otherwise.
V = A7 ·Bi·R10A1· B7· R7:
Set i f the result overflows: cleared
otherwise.
C = A7·B70B7·R70R7·A1: Set i f the absolute value of ACCB is
greater than that of ACCA: cleared otherwise.
H :
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
IMPL
SBA
Operand
format
Instruction code
1st
byte
10
2nd
byte
3rd
byte
_._Bytes
of
instr.
code
CPU
cycles
1
1
-
~HITACHI
100
/
SuBtract with Carry
Category
Arithmetic
operation
SBC
Function
-
ACCX
(ACCX)
-
(M)
-
I
(C)
Subtracts the contents of memory M and the contents
of bit C from those of ACCX, and stores the result
into the ACCX.
Effects on the condition codes
H : Not affected.
I
: Not affected.
N
Z
=
=
R7: Set i f the result's MSB is IIl"i cleared otherwise.
R'j.R'00goRi·R3oR2·Rl·RO: Set i f the result is zero; cleared
otherwise.
V
=
X7·M7·R76X7oM7oR7:
Set i f the result overflows;
.
cleared otherwise °
C
=
X7·M76M7·R70R7·Xi:
Set i f the absolute value of M contents
plus e is greater than that of Aeex contents; cleared
otherwise.
Addressing modes and epu cycles
Addressing
mode
Instruction code
Operand
format
Mnemonic
1st
byte
2nd
byte
3rd
byte
Bytes
of
instr.
code
CPU
cycles
IMMED
SBe
A
ltImm
82
Imm
2
2
DIRECT
SBe
A
M
92
M
2
3
EXTND
SBC
A
M
B2
MH
3
4
INDEX
SBe
A
Disp,X
A2
Disp
2
4
IMMED
SBe
B
Umm
B
M
Imm
M
;2
SBe
e2
D2
2
DIRECT
2
3
EXTND
SBe
B
M
F2
MH
3
4
INDEX
SBe
B
Disp,X
E2
Disp
2
4
ML
ML
~HITACHI
101
/
SEt Carry
SEC
Function
Category
Bit C
Bit
control
-
1
Sets the carry bit C of the CCR.
Effects on the condition codes
H :
Not affected.
V :
"
"
"
"
C=l :
Set
I :
N :
Z :
Addressing modes and CPU cycles
Addressing
mode
IMPL
Instruction code
Mnemonic
SEC
Operand
format
1st
byte
00
~HITACHI
102
2nd
byte
3rd
byte
Bytes
of
instr.
code
CPU
cycles
1
1
I
SEt Interrupt mask
Category
....
Bit
control
Bit I
.
SEI
Function
- ---- ---.------ - ---------_. ._-----
__
-
I
1
Sets the interrupt mask bit of the CCR.
When the I bit is set, all maskable interrupts
are inhibited. and the MPU will recognize only a NonMaskable Interrupt (NMI) request.
Effects on the condition codes
H :
Not affected.
I=l :
N :
Z
:
V
:
C :
Set
Not affected.
.
.
.
Addressing modes and CPU cycles
Addressing
mode
IMPL
Instruction code
Mnemonic
SEI
Operand
format
1st
byte
OF
2nd
byte
3rd
byte
Bytes
of
instr.
code
CPU
cycles
1
1
~HITACHI
103
/
SEt two's complement oVerflow bit
Category
SEV
Function
Bit
control
Bit V
-
1
Sets the overflow bit V of the CCR.
Effects on the condition codes
H :
Not affected.
I :
"
N :
II
Z :
"
V=l :
Set
C :
Not affected.
Addressing modes and CPU cycles
Addressing
mode
Instruction code
Mnemonic
Operand
format
1st
byte
2nd
byte
3rd
byte
Bytes
of
instr.
code
CPU
cycles
1
1
f----
SEV
IMPL
OB
--- 1------ -------- ------_.
-
i
-- - r--
~HITACHI
104
-
---
.
/
SLeeP
SLP
Function
Category
Low power
dissipatior:
mode
Brings the CPU to a halt. All the internal register
states are held as they are. The timer, serial
communication interface and interrupt control are
not affected by this instruction. I f a CPU inter-
I
rupt request occurs, the SLEEP mode is released.
After releasing, following instructions are executed
when bit I has been set by a maskable interrupt.
When bit I has not been set by either maskable or
non-maskable interrupt, the MCU sets bit I and
loads the interrupt vectoring address into the
program counter to start execution.
Effects on the condition codes
H :
I :
N :
Z :
V :
C :
Not affected.
"
"
"
"
"
Addressing modes and CPU cycles
Addressing
mode
IMPL
Instruction code
Mnemonic
Operand
format
1st
byte
2nd
byte
3rd
byte
lA
SLP
---
'-------- ' - - - - -
-----
Bytes
of
instr.
code
CPU
cycles
1
4
1----
~HITACHI
105
/
STore Accumulator
STA
Function
---_._---------_._---
Category
Load &
store
-
M
(ACCX)
Stores the contents of ACCX into the memory M.
The contents of the ACCX remains unchanged.
Effects on the condition codes
H : Not affected.
I : Not affected.
N = X7:
Set i f the MSB of ACCX is "1"; cleared otherwise.
Set i f the contents of ACCX is zero;
cleared otherwise.
Z = X7·X6·XS·X4·X3·X2·Xl·XO:
V = 0:
Cleared.
C : Not affected.
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
Operand
format
1st
byte
3rd
byte
2nd
byte
Bytes
of
instr.
code
CPU
cycles
I-----------t---
DIRECT
STA
A
M
EXTND
STA
A
M
.
.------
M
2
97
-- - - - --_.._--ML
3
MH
B7
-_.- -- ----,. - .. -- "-_ .._- . -------.-2
A7
Disp
INDEX
STA
DIRECT
STA
D7
M
EXTND
STA
B
M
F7
MH
STA
B
Disp,X
E7
--'--
1------
--f--
ML
4
2
3
3
4
-- r---- -2
Disp
~HITACHI
106
4
-
Disp,X
A
_._------M
B
INDEX
3
4
/
Double STore accwnulator A:B
category
Load &
store
..
M:M+l
STD
Function
--,-------_._- .._ ......
-
__ ._---
I
(ACCD)
Stores the contents of ACCD into the memories M
and M+l.
The contents of the ACCD remains unchanged.
Effects on the condition codes
Not affected.
I : Not affected.
N = AB15: Set if the MSB of ACCD is "111; cleared otherwise.
Z = ABlS·ABl4 ·AB13·
·ABO: Set i f the contents of ACCD
is zero; cleared otherwise.
V = 0: Cleared.
C = Not affected.
H :
.......
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
Operand
format
Instruction code
1st
byte
2nd
byte
DD
M
3rd
byte
Bytes
of
instr.
code
CPU
cycles
1-----
DIRECT
EXTND
INDEX
STD
STD
STD
M
M
---_._._
.._Disp,X
FD
ED
-- --
I-MB--Disp
ML
1---
2
3
2
4
5
5
$HITACHI
107
STore Stack pointer
STS
Function
Category
Stack
pointer
control
/
M
M+1
--
"-----_... _-_.._._---- --_._._--_. __... _----_._--------_._------
(SPH)
(SPL)
Stores the upper byte of the SP into the memory M,
and then the lower byte of the SP into the memory
M+1_
Effects on the condition codes
H : Not affected_
I
: Not affected_
N = SPH7:
Set i f the MSB of the stack pointer is "1" ;' cleared
otherwise_
Z =
(SPH7-SPH6-SPHS-SPH4-SPH3-SPH2-SPH1-SPH0)- (SPL7-SPL6-SPLS.
SPL4-SPL3·SPL2·SPL1-SPLO) :
Set i f the contents of the
stack pointer is zero; cleared otherwise.
Cleared_
V = 0:
C : Not affected.
Addressing modes and CPU cycles
Addressing
mode
Instruction code
Mnemonic
Operand
format
1st
byte
2nd
byte
3rd
byte
._------,
Bytes
of
instr_
code
CPU
cycles
1--.
DIRECT
STS
EXTND
STS
INDEX
STS
2
4
3
--_._-- t-- ..------_._---"---- - - - 2
AF
Disp
Disp,X
5
M
M
M
9F
BF
MH
...... _._._-
-
~HITACHI
108
ML
5
/
STore indeX register
Category
Index
register
control
STX
Function
-- .._--_._---_._--.-----M
M+l
-
I
(IXH)
-
(IXL)
Stores the upper byte of the IX into the memory M,
then the lower byte of the IX into the memory M+l.
Effects on the condition codes
H : Not affected.
I
: Not affected.
N
=
IXH7:
Set if the MSB of the index register is 11111; cleared
otherwise.
Z
=
(IXH7·IXH6·IXHS·IXH4·IXH3·IXH2·IXH1·IXH0)· (IXL7·IXL6·IXLS·
IXL4·IXL3·IXL2·IXL1·IXLO):
V
=
Set i f the contents of the
index register is zero; cleared otherwise.
0: Cleared.
C : Not affected.
Addressing modes and CPU cycles
Addressing
mode
Instruction code
Operand
format
Mnemonic
1st
byte
2nd
byte
3rd
byte
Bytes
of
instr.
code
CPU
cycleS
I---
DIRECT
STX
EXTND
STX
INDEX
STX
2
4
ML
3
FF
MH
._---- ---.--..... ... _---- - ..-.- .--.. - ---.-.2
Disp
Disp,X
EF
5
M
DF
__
M
.----.
M
5
'----_.
.---.----
.- .
..
~HITACHI
109
SUBtract
/
Category
Arithmetic
operation
SUB
Function
-----_.------------_.__..
ACCX
-
-
(ACCX)
eM)
Subtracts the contents of memory M from those of
ACCX, and stores the result into the ACCX.
Effects on the condition codes
H : Not affected.
I : Not affected_
=
=
R7:
Z
V
=
X7-M7-R70X7-M7-R7:
otherwise_
C
=
X7-M70M7-R70R7-X7: Set i f the absolute value of memory
contents is greater than that of ACCX contents: cleared
otherwise.
N
Set i f the result's MSB is "1"; cleared otherwise_
Set i f the result's contents is zero;
cleared otherwise_
R7·M-~-R4-R3-R2-Rl·RO:
Set i f the result overflows; cleared
Addressing modes and CPU cycles
Addressing
mode
;Eerand
Instruction code
fo:~a~
Mnemonic
1st
byte
3rd
byte
2nd
byte
Bytes
of
instr.
code
CPU
cycles
1-----
IMMED
SUB
A
DIRECT
SUB
A
EXTND
SUB
A
M
--.!NDEX
IMMED
SUB
A
Disp,X
SUB
B
SUB
B
Umm
M
DIRECT
EXTND
SUB
B
INDEX
SUB
B
ltImm
M
--
-----_._-
M
.
__ .,- ------
80
Imm
--------
----.-
M
90
BO
HH
AD
: Disp
.----_ ......
-- f---
ML
~-~~
D°ti
---_.- _~O_
Disp,X
EO
2
2
2
3
4
------ - -----. ----_._-
~H
ID~sp
~HITACHI
110
-
ML
3
4
2
2
2
2
3
3
4
2
4
--
/
Double SUBtract without carry
SUBD
Function
_._--_._-,._-----------
Category
-
ACCD
Aritlunetic
operation
(ACCD)
-
(M:M+1)
I
Subtracts the contents of memories M: M+l from the
contents of ACCD, and stores the result into the
ACCD.
Effects on the condition codes
H : Not affected.
I : Not affected.
N = RlS: Set i f the Result's MSB is 11111; cleared otherwise.
• RO: Set i f the result's contents
Z = R1S·R14·ID·
is zero; cleared otherwise.
V = DlS·MlS·R1S·D1S-M1S·R1S: Set i f the result overflows;
cleared otherwise.
C = D1S-M1S·M1S-R1S·R1S-D1S: Set if the absolute value of
memory contents is greater than that of ACCD contents;
cleared otherwise_
..........
A~dressing
Addressing
mode
Mnemonic
modes and CPU cycles
Operand
format
-_._-----IMMED
DIRECT
EXTND
INDEX
#Inun
SUBD
M
SUBD
-- ---------.. ---M
SUBD
Disp,X
SUBD
Instruction code
1st
byte
2nd
byte
3rd
byte
83
InunH
M
93 ._._---MH
B3
Disp
A3
ImmL
ML
Bytes
of
instr.
code
3
2
3
2
CPU
cycles
3
4
5
5
-
~HITACHI
111
/
SoftWare Interrupt
Function
category
Interrupt
control
-
PC
..
----.--------.----~--.------.-
-- ..
(PC) + 0001
(PCL) , SP
(SP)-OOOI
I
t (PCH) ,
t (IXL) ,
SP
SP
-
---
Increments PC by one and pushes
it onto the stack in the order
of PCL, PCH, IXL, IXH, ACCA,
ACCB and CCR. The stack pointer
SP is decremented by 1 after
each byte of data is stored on
the stack. Concerning CCR,
transfers bit 0 through bit 5
as they are and bits b6 and b7
as being set. Then sets the
interrupt mask bit I, and loads
the contents of the memory
highest-order address minus 5
($FFFA) and those minus 4
($FFFB) into the PC.
(SP)-OOOI
(SP)-OOOI
t (IXH) , S P - (SP)-OOOI
t(ACCA),SP
t(ACCB),SP
-
J(CC),SP
I
--
PCL
(SP) -0001
(SP) -0001
(SP)-OOOI
1
-
PCH
SWI
(Highest-order address
(Highest-order address
-
0005)
- 0004)
Effects on the condition codes
H :
Not affected.
I=l :
N :
Z :
V :
C :
Set
Not affected.
"
"
"
---Addressing modes and CPU cycles
Addressing
mode
I
Instruction code
Mnemonic
Operand
format
r------ -------1 - - - - - - - - - - - IMPL
1st
byte
2nd
byte
3F
SWI
~-------
- - - - - - - - - - - - - - - - - - - - - - - - -----
f - - - - - - - - - - - - - - ---- --._.-_., --.
.....
---
---- --- ------
-- ------------------- - - - ---.
1 - - - - - - - - - - - - ----------..- - - - - - - . -
------- - -1 - - - - - - - - - - - - - - - - - -
3rd
byte
Bytes
of
instr.
code
CPU
cycles
1
12
_.-.--- f----- --- . ---,--
--
..."', ..
--_._-
- - - - - - ------- f---
---=r-----
------- - - -
--- ---- ------.-.-- f------
~HITACHI
112
-------
- - . - - - - - - r-
/
Transfer from accumulator A to accumulator B
Function
Category
Transfer
TAB
ACCB
-
(ACCA)
Transfers the contents of ACCA into ACCB.
The contents of the ACCA remains unchanged.
Effects on the condition codes
H : Not affected.
I : Not affected.
\
N = R7: Set i f the MSB of ACCA is "1"; cleared otherwise.
Set i f the contents of ACCA is
Z = R7·R6·R5·M·RJ·~·m·M:
zero; cleared otherwise.
Cleared.
V = 0:
C : Not affected.
Addressing modes and CPU cycles ..
Addressing
mode
IMPL
Mnemonic
Operand
format
.TAB
------..
-
Instruction code
1st
byte
2nd
byte
3rd
byte
Bytes
of
instr.
code
1
16 •..- ----_.
----- ..--- .-----..--- ..- ..----. .- ..----- --.
CPU
cycles
1
=4----=
~HITACHI
113
Transfer fran aceurW.ator A to Processor condition codes register
Category
Function
.- ---- --.---- -------" ..... ---_.
Transfer
CC
I
-
/
TAP
__ ._-_._---
(ACCA)
7 6 5 4 3 2 1 0
I I I I I I I
I
ACCA
t t \ t , \
IHIIINlzlvlcl
cc
E
Carry- Borrow
Over flow
Zero
Negati ve
Interrupt Mask
Half Carry
Transfers bits 0 through 5 of ACCA to the corresponding bits of the CCR. The contents of the ACCA
remains unchanged.
Effects on the condition codes
Bit
I : Bit
N : Bit
Z : Bit
V : Bit
C : Bit
H :
5 of ACCA
4 of ACCA
3 of ACCA
2 of ACCA
1 of ACCA
0 of ACCA
---.-------Addressing modes and CPU cycles
Addressing
mode
Mnemonic
Operand
format
- - - - - - - f----.---- .--- ..- - ..-----TAP
IMPL
- - - - _ ... ---_ .. -----_ .._----
.
_ . _ - - ._-_... _--......... -... --
Instruction code
1st
byte
Bytes
of
instr.
code
3rd
byte
2nd
byte
1
06
----- - - - - --.------ - _ .
._-_._- .. --.-- --_._- --
1--'-'--'
---------- - - - - - - - - _ . _ - ----,_._- - - - -I--'
-_._--------_... ----- - - - - . - ----- ..-- . - - .-.------ ..-.--.--.--.. - - - -
~HITACHI
114
..-
-.
-
.
CPU
cycles
1
Transfer from accumulator B to accumulator A
Category
Function
_.. _-_._-------------_...
Transfer
ACCA
-
_-_
L
TBA
...
(ACCB)
I
Transfers the contents of ACCB into ACCA.
The contents of the ACCB remains unchanged.
I
Effects on the condition codes
Not affected.
I : Not affected.
N = R7: Set i f the MSB of ACCB is 111"; cleared otherwise.
Z = ~·R6·e·M·~·~·n·RO:
Set i f the contents of ACCB
is zero; cleared otherwise.
V = 0:
Cleared.
C : Not affected.
H :
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
Operand
format
Instruction code
1st
byte
2nd
byte
3rd
byte
Bytes
of
instr.
code
CPU
cycles
1----
IMPL
17
TBA
-_ "- -- - - -
f----
..
1
'-----
1
- - - ----
----
,
--
~HITACHI
115
Test
/
~Mmediate
Function
Category
Logical
operation
TIM
IM ·(M)
ANDs the immediate data and the contents of memory M
to change the condition codes.
The contents of the CCR can be referenced by the
following branch instruction. Both operands remain
unchanged.
Effects on the condition codes
Not affected.
I : Not affected.
N = R7: Set i f the result's MSB is "1"; cleared otherwise.
Set i f the result is zero~ cleared
Z = R1·~·B·R4·R3·R2·Rl·RO:
otherwise.
V = Cleared.
C : Not affected.
H :
\
Addressing modes and CPU cycles
Addressing
mode
Operand·
format
Mnemonic
-.
DIRECT
INDEX
TIM
TIM
#Imm,M
#Imm,Disp,X
- ._....- ... _----
Instruction code
1st
byte
2nd
byte
3rd
byte
7B
6B
Imm
Imm
M
Disp
-_._-
------
f-----
--
I
~HITACHI
116
Bytes
of
instr.
code
3
3
,....----
CPU
cycles
4
5
Transfer fran Processor condition codes register to accunrulator A
Category
Transfer
ACCA
/
TPA
Function
-
(CC)
I
7 6 5 4 3 2 1 0
~I I ! ! I ; ~
1
t I f 1 If.
1
ACCA
l§cmy. "".
IH!IIN!Z!v!ci
I
I ' II I
cc
Overflow
I I
I
Zero
Negati ve
Interrupt Mask
Half Carry
Transfers bits 0 through 5 of the CCR to the corresponding bits of ACCA. The contents of CCR remains
unchanged.
Effects on the condition codes
H :
I :
N :
Z
:
V :
C :
Not affected.
"
"
"
"
"
Addressing modes and CPU cycles
Instruction code
Addressing
mode
Mnemonic
IMPL
TPA
Operand
format
1st
byte
2nd
byte
07
------
3rd
byte
Bytes
of
instr.
code
CPU
cycles
1
1
- - - ----- -
~HITACHI
117
/
TeST
Function
category
Comparison
& test
(ACCA)
(M)
-
-
TST
-
00
00
Sets bits Nand Z of the CCR according to the contents
of ACCX or memory M.
Effects on the condition codes
H : Not affected.
I : Not affected.
N : M7: Set if the MSB of ACCX or M is "l"; cleared otherwise.
Set i f the contents of ACCX or M
Z = Wf·M"b·M5"·M4 ·M3 ·M2 ·Ml·MO:
is zero; cleared otherwise.
V = 0:
Cleared.
C = 0: Cleared.
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
ACCX
ACCX
EXTND
INDEX
TST
TST
TST
TST
Operand
format
A
B
M
Disp,X
Instruction code
Bytes
of
3rd
instr.
1st
2nd
byte byte byte code
-- c----1
4D
---- 1------ ----1
5D
-- -,----- r------ --_ .._._----_.
3
MH
ML
7D
2
Disp
6D
~HITACHI
118
CPU
cycles
1
1
4
4
/
Transfer from Stack pointer to indeX register
TSX
Function
.Category
Transfer
IX
-
(SP) + 0001
Increments the contents of the SP by one, and loads
it into the IX.
The contents of the SP remain
unchanged.
1
Effects on the condition codes
Not affected.
H :
I :
"
N :
"
Z
"
"
"
:
V :
C :
1----------Addressing modes and CPU cycles
I
Addressing
mode
Instruction code
Mnemonic
Operand
format
1--------_. --.--. --- ---+--
IMPL
TSX
i--------------- ----,-------~-
..
--- .. - -----
1st
byte
2nd
byte
30
r--.--------------- r-----
3rd
byte
-------._-.
-_ ..... _-
Bytes
of
instr.
code
CPU
cycles
1
1
_._._--.
--
------_ .._---
-
--
------
--c----
- -----
_.
- - --------
~HITACHI
119
/
Transfer from indeX register to Stack pointer
TXS
Function
Categ'ory
._._-_.---------
Transfer
-
SP
(I}{)
- 0001
Decrements the contents of the IX by one, and loads
i t into the SP.
The contents of the IX remain
unchanged.
Effects on the condition codes
H :
I :
N :
Z :
V :
C :
Not affected.
"
"
"
"
"
Addressing modes and CPU cycles
Addressing
mode
Instruction code
Mnemonic
Operand
format
-
1---
IMPL
TXS
---
--
I
1st
byte
35
- - - - -----
CPU
cycles
1
1
---.. ----- "'"--"- ---------- --------- ------- -_.__ ._-"
-------
--
~HITACHI
120
2nd
byte
3rd
byte
Bytes
of
instr.
code
/
WAit for Interrupt
WAI
Function
--r-------------- - - - -----------Increments PC by one and pushes
Interrupt
PC
(PC) + 0001
it onto the stack in the order
control
(SP)-OOOI
I (PCL) ,SP
of PCL, PCH, IXL, IXH, ACCA,
ACCB and CCR.
I (PCH) , SP
(SP)-OOOI
The SP is decremented by
I (IXL),SP
(SP)-OOOI
1 after each byte of data is
I (IXH) , SP
(SP)-OOOI
pushed onto the stack.
I (ACCA) ,SP
(SP)-OOOI
Concerning CCR, transfers bits 0
through 5 as they are and bits 6
I (ACCB) , SP
(SP)-OOOI
and 7 as being set.
(SP)-OOOI
t (CC) ,SP category
- -
I
-
The program execution stops
temporarily until interrupt from
a peripheral device occurs.
I f bit I is a 0 before an interrupt occurs, the following
processings takes place when the interrupt has occurred. That
is: sets bit I; and loads the interrupt vectoring address to
the PC.
Effects on the condition codes
H : Not affected.
I : Not affected until an interrupt occurs and set i f bit I is a
0 when the interrupt has occurred.
N : Not affected.
"
"
"
Z :
V
:
C :
Addressing modes and CPU cycles
Addrming
mode
r-----IMPL
I Mnemonic
WAI
r----
Instruction code
Operand
format
1st
byte
2nd
byte
3rd
byte
CPU
cycles
1
9
3E
---- - - - - f-----
-.---
- - - - - - - - - -- - - - - -1-------- f------
-
Bytes
of
instr.
code
-_.-
-
~HITACHI
121
/
eXchanGe accD and iX
Category
Function
Exchange
IX
-
XGDX
-
ACCD
Exchanges the contetns of IX with those of ACCD.
Effects on the condition codes
H :
I :
N :
Not affected.
V :
"
"
"
"
C :
"
Z :
Addressing modes and CPU cycles
Addressing
mode
Mnemonic
IMPL
XGDX
Operand
format
Instruction· code
1st
byte
2nd
byte
3rd
byte
1
18
-.- r---- 1-----
---.~*
--
~HITACHI
122
Bytes
of
instr.
code
-------
CPU
cycles
2
HD6301/HD6303 SERIES HANDBOOK
Section Three
HD6301Vl/HD6303R
User's Manual
~HITACHI
123
Section 3
HD6301 V1/HD6303R User's Manual
Table of Contents
Page
Notice on HD6301 V and HD6303R . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .
126
1. OVERViEW....................................................
128
1.1
Features of HD6301V1 ........................................
128
1.2·
Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
128
1.3
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
129
INTERNAL ARCHITECTURE AND OPERATIONS. . . . . . . . . . . . . . . . . . . . . .
130
2.1
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
2.2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
135
2.3
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
140
2.4
1/0 Ports. . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
142
2.5
Programmable Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
146
2.6
Serial Communication Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
150
2.7
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
157
2.8
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
159
2.9
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
161
2.10
Strobe ,Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
161
2.11
RAM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
162
2.12
Low Power Consumption Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
163
2.13
TRAP Function .:.......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
167
INSTRUCTIONS................................................
168
3.1
Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
168
3.2
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
170
3.3
Instruction Execution Cycles ....... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
3.4
System Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
181
PIN ARRANGEMENT AND PACKAGE INFORMATION..................
183
2.
3.
4.
~HITACHI
124
5.
ELECTRICAL CHARACTERISTICS ................................ .
186
6.
APPLICATIONS ................................................ .
191
6.1
Use of External Expanded Mode ............................... .
191
6.2
Standby Mode .............................................. .
195
6.3
Address Trap, OP-Code Trap Application ......................... .
198
6.4
Slow Memory Interface ....................................... .
199
6.5
Interface to HN61256 ......................................... .
200
6.6
Interface to the Realtime Clock (HD146818) ....................... .
205
6.7
Reference Data of Battery Service Life ................ ; ......... .
208
PRECAUTIONS ................................................ .
209
7.1
Write-Only Register .......................................... .
209
7.2
Address Strobe (AS) ......................................... .
209
7.3
Mode
o.................................................... .
209
7.4
Trap Interrupt ............................................... .
209
7.5
Power-on Reset ............................................. .
211
7.6
Precaution to the Board Design of Oscillation Circuit ............... .
211
7.7
Application Note for High Speed System Design Using the HD6301V1 ..
212
7.
APPENDIX
I.
EPROM on Package HD63P01 M1
218
II.
Program Development Procedure and Support System. . . . . . . . . . . . ..
226
III.
Q & A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
233
~HITACHI
125
I
"Notice on HD630iVi"
The HD6301VO (including A and B version)
was
upgraded to the HD6301Vl series in early 1983.
The spec. deviation between the HD6301VO series and the
HD6301Vl series is as follows.
Please refer to the data
sheet for detailed spec. of the HD6301Vl series.
Table.
Items
Spec. Deviation between the
HD6301VO and the HD6301Vl
HD6301VO
Mode 2 : Not defined
Operating Mode
Mode 3 : Not defined
Electrical
Characteristics
Timer
Mode 2 ; Expanded Multiplexed Mode
(equivalent to
Mode 4)
Mode 3 ; Not defined
The electrical characteristics of
2MHz version
(B version) are
not specified.
The 2MHz version is
guaranteed.
Has problem in output
compare function.
(Can be avoided by
software.)
Fixed
~HITACHI
126
HD6301Vl
HD6303Rl
HD63P01Ml
HD6303R
HD6301Vl
GND Noise
R!W~~_ _ _ _ _~r
Ai
Di
==:x
I
x:::
A Noise
-C==)~_--J>-
Noise is
reduced by
33%.
If load capacitance in each data
line and GND impedance are
large, noise may appear on
address bus during MCU write
cycle and data won't be written
into RAM correctly. The noise
is caused by GND impedance
which becomes large when large
transient current flows into
GND at High to Low transition of
data line.
HD 6301Vl
SCI
HD6303R
HD63P01Ml
HD6303Rl
When framing error occurs,
receive data is not
transferred from the
Receive Shift Register to
Receive Data Register (RDR) •
I
P
23
RDR
I).
- \ Receive Shift
Register
I
Receive data is
transferred fram
Receive Shift
Register to RDR
even if framing
error occurs.
I
"Notice on HD6303R"
The HD6303R is the same die as the HD6301Vl. The on-chip Mask ROM is disabled by mask option; Therefore not all modes of
operation are available on the HD6303R. Please note that wherever HD6301Vl is referenced, the information also applies to the
HD6303R.
"Notice on HD6303Rl"
The HD6303R has been upgraded to HD6303Rl. Refer to the following figures for differences between the devices. All other
characteristics remain the same.
~HITACHD
127
1.
OVERVIEW
1.1
Features of HD6301Vl
The HD6301Vl provides the following features:
- Expanded instruction set of the HD6801 family
- Abundant on-chip functions compatible with the HD6801
family:
4k-byte of ROM, 128-byte of RAM, 29 parallel
I/O Lines, 2 data strobe Lines, 16-bit timer, serial
communication interface
- Low power consumption mode:
sleep/standby mode
- Minimum instruction execution time:
0.67~s
(f=1.5MHz),
0.5~s
l~s
(f = IMHz),
(f=2MHz)
- Bit manipulation and bit test instruction
- Error detection:
Address trap and operation code trap
- Address space up to 65k words
- Wide operation range:
Vee = 3 to 6V (f
f = 0.1 to 2.0MHz (Vee = 5V
±
0.1
'V
10%)
- TTL compatible input/output
1.2
Block Diagram
A block diagram of HD6301Vl is given in Fig. 1-2-1
Fig. 1-2-1
Block Diagram of HD6301Vl
~HITACHI
128
O. 5MHz) ,
Functional Pin Description
1.3
Table 1-3-1 lists the pin functions.
Refer to "2. INTERNAL
ARCHITECTURE AND OPERATIONS" for more details.
Table 1-3-1
Pin
VCC' VSS
XTAL
EXTAL
Pin Functions
Crystal connection pin. When external clock is used, input it to
EXTAL, and XTAL should be open.
When this pin is in "Law ll state, MCU is set to
RES
Reset input pin.
reset state.
STBY
Standby input pin.
to standby state.
NMI
Nonmaskable interrupt input pin for edge detection (Negative
edge) .
IRQ 1
E
P 2 0/TIN
a
Function
Power supply and GND pins
When this pin is in "Low ll state, MCU is set
Interrupt input pin for level detection (Active Low)
System clock output pin.
oscillator frequency.
5-bit I/O port
The frequency is 1/4 of the crystal
Timer input-capture input pin
Timer output-compare output pin
P 2 l/TOUT
P 22 /SCLK
SCI clock I/O port
P 23 /RX
SCI receiving pin
SCI transmitting pin
P 2 4/ TX
Following pins function depending on each operation mode
Mode 6
Mode 1
Mode 5
Mode 0,2,4
PORT 1
8-bit
I/O port
PORT 3
Data (D 0"'D7)
Lower address
(Ao"'A7)
Mul tiplexed
Bus
P,ORT 4
upper address
(Aa"'A1S)
SCI
Address strobe
(AS) output
pin
SC 2
Read/write
signal
(R/W) output
pin
Lower address 8-bit
(Ao",A 7 )
I/O port
Data Bus
Do"'D7
..
~
-
-
-
Data (Do"'D7 )
Lower address
(Ao"'A7)
Multiplexed
Bus
-
Mode 7
-
Lower address
(Ao"'A7) or
Input-only
pin
Upper address
(Aa"'Als) or
Input-only
pin
I/O strobe
(lOS) output
pin
Address strobe I~t strobe
(AS) output
(IS3) output
pin
pin
-
-
8-bit
I/o port
Output strobe
(053) output
pin
~HITACHI
129
2.
INTERNAL ARCHITECTURE AND OPERATIONS
This section describes the internal architecture of the
HD6301Vl and its operation.
2.1
Mode Selection
After the MCU is reset, a user must determine the operation
mode of the HD6301Vl by strapping three pins 8, 9 and
10 which are connected by hardware externally.
These
pins correspond to P 20 , P 21 and P 22 respectively.
Individual signals on the above three pins are latched
and loaded into the program control bits PCO, PCl and PC2,
the most significant three bits of I/O port 2 register,
when the RES signal goes "High".
The bit assignment of
the port 2 data register is shown below.
Port 2
$0003
Data Register
7
6
5
4
3
2
1
0
Ipc2lpcllpcolI/0 41I/0 31I/0 21I/0 lII/O 01
An example of an external hardware for mode selection is
shown in Fig. 2-1-1. The HD14053B may be used to separate
the MCU from its peripheral devices during reset (Data
confliction should be avoided between the peripheral devices
and mode generator circuit).
Because bits 5, 6 and 7 of
port 2 are for read only, so the operation mode cannot be
altered by software.
The mode selection in the HD6301Vl is
summarized in Table 2-1-1.
The HD6301Vl has three basic operation modes:
1)
Single chip mode
2)
Expanded multiplexed mode
(Compatible Bus with HMCS6800 peripheral LSIs)
3)
Expanded non-multiplexed mode
(Compatible Bus with HMCS6800 peripheral LSIs)
@HITACHI
130
Truth Table
Control Input
Binary to 1 ·of·2
Decoder with
Inhibit
On Switch
SelecI
Inh,b,'
C B A
Xo
X,
YO
Y,
ZoO
Z,
X
Y
Z
HDI405JB
0
0 0
0
Z. V. X.
0
0
0
I
Z. V. X,
- o~~1
-0 I
0
Z. V, X.
I
Z. V, X,
0
1 0
0
Z, V. X.
0
1 0
1
Z, V. X,
0
I
I
0
Z, V, X.
0
1
1
1
Z, V, X,
1
X X X
I
-
HD14053B Multiplexers/De-Multiplexers
Vee
(
~
R
R, R, R,
U
R
ABC
V.
'X
p,.
Z.
X,
V
P"
V,
~
P"
Z,
(
I
???
~
Mode
Control
Sw,tch
Fig, 2-1-1
B
9
10
Z
Inh
RES
HD6301Vl
X.
4
C
6
-
p,. (PCOI
P" (PCII
P" (PC2)
HD14053B
Jr
Note 1) Figure of Mode 7
2) AC""Aeset Constant
3) A, =10kn
Recommended Circuit for Mode Selection
~HITACHI
131
Table 2-1-1
Mode
p..
p..
(PC2)
P21
(PC1)
(PCO)
ROM
Mode Selection Summary
Interrupt
Vectors
RAM
Bus
Mode
Operating
Mode
7(4)
H
H
H
I
I·
I
I
6(4)
H
H
L
I
I
I
MUX3)
5(4)
H
L
H
I
I
I
NMUX3 )
4
H
L
L
E'I
I
E
MUX
~
L
H
H
-
-
-
-
2
1
L
H
L
Ell
I
E
MUX
Multiplexed/RAM
L
L
H
E'I
I
E
NMUX
Non·Multiplexed
0(4)
L
L
L
I
I
121
MUX
Multiplexed Test
LEGEND:
I -Internal
E - External
MUX
- Multiplexed
NMUX
- Non-Multiplexed
L - Logic "0"
H - Logic "I"
Single Chip
Multiplexed/Partial Decode
Non·Multiplexed/Partial Decode
Multiplexed/RAM
Not Used
(NOTES)
11 Internal ROM is disabled.
2) Reset vector is external for 3 or 4 cvcles after
FjES goes "h igh".
3) Idle lines of Port 4 address outputs can
be assigned to Input Port.
4) Not available on HD6303R or HD6303R1
(1) Single Chip Mode
In the Single Chip Mode, all ports will become I/O.
is shown in figure 2-1-2.
This
In this mode, SCI, SC2 pins are
configured for control. lines of Port 3 and can be used as
input strobe (IS3) and output strobe (OS3) for handshaking
data.
(2) Expanded Multiplexed Mode
In this mode, Port 4 is configured for I/O (inputs only)
or address lines.
The data bus and the lower order address
bus are multiplexed in Port 3 and can be separated by an
output called Address Strobe.
Port 2 is configured for 5 parallel I/O or Serial I/O, or
Timer, or any combination thereof.
for 8 parallel I/O.
Port 1 is configured
In this mode HD630lVI is expandable
to 65k words (See Fig. 2-1~3).
Since the data bus is multiplexed with the lower order
address bus in Port 3 in the expanded multiplexed mode,
address bits must be latched outside.
74LS373 (Octal-
D type transparent latches) is required for address latch.
Latch connection of the HD630lVI is shown in Fig. 2-1-4.
~HITACHI
132
Vee
Enable
Port 3
Port 1
8 110 Lones
8110 Lones
Port 4
Port 2
8110 Lones
5110 lines
SCI
Timer
Fig. 2-1-2
HD6301Vl MCU Single-Chip Mode
Vcc
Enable
Port 1
8 Lines
8 I/O Lines
Multiplexed
Data/Address
Port 2
5 I/O Lines
SCI
Timer
VSS
Port 4
To 8 Address
Lines or To
8 I/O Lines
(Inputs Only)
Fig. 2-1-3 HD6301Vl MCU Expanded Multiplexed Mode
~Hn'TACH6
133
GND
AS
IM_~-',
II
0,
Port 3
G DC
D,
74LS373
Addre~s/Data
l-
0,
C,
0>
j "''', -.
Function Table
Enable
Output
Control
Output
G
0
0
L
L
L
H
H
H
H
H
X
L
X
X
L
0,
Z
L
Fig. 2-1-4 Latch Connection
(3) Expanded Non Multiplexed Mode
In this mode, the HD6301Vl can directly address HMCS6800
peripherals with no address latch.
comes a data bus.
In mode 5, Port 3 be-
Port 4 becomes Ao to A7 address bus or
partial address bus and I/O (inputs only).
Port 2 is con-
figured for a parallel I/O, Serial I/O, Timer or any
combination.
Port 1 is configured as a parallel I/O
only.
In this mode, HD6301Vl is expandable to 256 locations.
In
the application system with fewer addresses, idle pins of
Port 4 can be used as I/O lines (inputs only)
(See Fig.
2-1-5) .
In mode 1, Port 3 becomes a data bus and Port 1 becomes
Ao to A7 address bus, and Port 4 becomes As to A15 address
bus.
Port 2 is configured for a parallel I/O, Serial I/O,
Timer or any combination.
In this mode, the HD6301Vl is
expandable to 65k words with no address latch.
2-1-5) .
~HITACHI
134
(See Fig.
Vee
Vee
Port 1
B Parallel 1/0
Port 3
B Data Lines
Port 2
5 Parallel I/O
SCI
Timer
Port 4
To B Address
Lines or To
81/0 Lines
(Inputs Onlv)
VSS
POri 1
Port 3
B Data Lines
To B Address Lines
Pan 2
5 Parallel I/O
SCI
Timer
Port 4
To 8 Address
Lines
Vss
(a) Mode 5
(b) Mode 1
Fig. 2-1-5
HD6301Vl MCU Expanded Non Multiplexed Mode
(4) Mode and Port Summary MCU Signal Description
This section gives a description of the MCU signals for
the various modes.
SC 1 and SC2 are signals which vary
with the chip mode.
Table 2-1-2
PORT 1
Eight Lines
MODE
SINGLE CHIP
1---
PORT 2
Five Lines
PORT
3
Eight Lines
PORT 4
Eight Lines
SC,
I/O
I/O
IS3 (I)
ADDRESS BUS
(Ao-A,)
DATA BUS
ADDRESS BUS'
(A.-A,,)
AS(O)
R/W(O)
ADDRESS BUS'
(Ao-A,)
10S(0)
R/W(O)
---ADDRESS BUSNot Used
(A.-A,,)
R/WiO)
I/O
I/O
EXPANDED MUX
Feature of each mode and Lines
I/O
I/O
SC,
I
OS3(0)
(00-0,)
EXPANDED
NON-MUX
i
i
Mode 5
i
Mode I
ADDRESS BUSI
(Ao-A,)
I/O
DATA BUS
I/O
I/O
(00-0,)
I
I
DATA BUS
(00- 0,)
*These lines can be substituted for I/O (Input Only) starting with the MSB
(except Mode 0, 2, 4). When they are not used as address lines.
I
= Input
= Output
o
R/iN
2.2
=
Read!WrOie
is:!
= Input Strobe
SC
Strobe Control
053
= Output Strobe
= 1/0 Select
AS
Address Strobe
105
Memory Map
The MCU can address up to 65k bytes depending on the
operating mode.
Fig. 2-2-1 shows a memory map for each
operating mode.
The first 32 locations of each map are
for the MCU's internal register only, as shown in Table
2-2-1.
~HITACHI
135
a
Table 2-2-1
Internal Register Area
Register
Address
Port 1 Data Direction Register
$00*1
Port 2 Data Direction Register
$01
Port 1 Data Register
$02*1
Port 2 Data Register/Mode Register
$03
Port 3 Data Direction Register
$04*2
Port 4 Data Direction Register
$05*3
Port 3 Data Register
$06*2
Port 4 Data Register
$07*3
Timer Control and Status Register
$08
Counter (High Byte)
$09
Counter (Low Byte)
$OA
Output Compare Register (High Byte)
SOB
Register (Low Byte)
SOC
Input Capture Register (High Byte)
SOD
Input Capture Register (Low Byte)
$OE
Port 3 Control and Status Register
$OF*2
Rate and Mode Control Register
$10
Transmit/Receive Control and
Status Regi ster
$11
Receive Data Register
$12
Transmit Data Register
$13
RAM Control Regi ster
$14
Output
Co~pare
Reserved
$l~$lF
R/W*4/Initialize at RESET
7 6 5 4 3 2 1 0
W
$00
W
$00
R/W *5
Undefined
R *6
R/W *5
Undefined
P22 P21 P20
W
$00
W
$00
R/W *5
Undefined
R/W *5
Undefined
R R R R/W R/W R/W R/W R/W
a a 0 a a a a 0
R/W
$00
R/W
$00
R/W
$FF
R/W
$FF
R
$00
R
$00
R R/W Unused
a a 1
Unused
1 1 1
R R R
a a 1
Unused
1 1 1
W W W W
1 a a a 0
R/W R/W R/W R/W R/W
0 a a a a
R
$00
W
$00
Unused
R/W R/W
*7 1 1 1 1 1 1 1
R/W R/W
a
a
~
(*1 through 8 are shown in the next page.)
~HITACHI
136
*1
External address in mode 1.
*2
External address in modes 0, 1, 2, 4, 5, 6; cannot be accessed
in mode 5.
*3
External address in modes 0, 1, 2, 4.
*4
R: Read-only register, W
Write-only register,
R/W : Read/Write register.
*5
The pin state is read instead of the data of the register when
*6
The values of program control bit (PCo
reading Ports.
P20
*7
~
(Refer to "2.4 I/O Ports" for I/O Port 3.)
~
PC2) depend on
I
P21 during reset.
Refer to "2.12 Low Power Consumption Mode" for standby mode.
HD6301V1
Mode
HD6301V10
Mode
Non-Multiplexed
Multiplexed Test mode
$OOoolt)
$001 F
~~~~~
~
1
$0000
Internal Registers
Internal Registers
$OOlF
External Memory Space
External Memory Space
$0080
$0080
m,'77T."",
$00 F F
t"''''''''"'''
Internal RAM
Internal RAM
$OOFF
External Memory Space
External Memory Space
$FOOO
Internal ROM
12
$FFFF ' - - - - - '
INOTE]
INOTES]
1) Excludes the following addresses which may be
used externally: $04, $05, $06, $07 and $OF.
2) Addresses $FFFE and $FFFF are considered
Excludes the following addresses which may be
used externally; $00, $02, $04, $05, $06, $07
and $OF,
external if accessed within 3 or 4 cycles after a
positive edge of RES and internal at all other times.
3) After 3 or 4 MPU cycles, there must be no overlapping
of internal and external memory spaces to avoid
driving the data bus with more than one device.
4) This mode is the only mode which is used for
testing.
(to be continued)
Fig. 2-2-1
HD6301V1 Memory Maps
~HITACHI
137
HD6301V1
Mode
2
HD6301V14
Mode
Multiplexed/RAM
HD6301V15
Mode
Non-Multiplexed/Partial Decode
$0000
Internal Registers
$OOlF
External Memory Space
S0080
) Internal RAM
Internal RAM
SOOFF
S0100
} External Memory Space
SOlFF
'-_...,...._.......1
External Memor.y Space
$FOOO
Internal ROM
$FFFF ' -_ _ _..... ,
$FFFF
[NOTE!
Excludes the following address which
may be used externally; $04, $05, $06,
$07, $OF.
[NOTE!
Excludes $04, $06, $OF.
These address cannot be used
externally.
(to be continued)
Fig. 2-2-1
HD6301 V1 Memory Maps
~HITACHI
138
HD6301V16
Mode
HD6301V17
Mode
Single Chip
Multiplexed/Partial Decode
$OOOO~)
Internal Registers
Internal Registers
$001 F ~=.<¥"='"
$OOlF
External Memory Space
I
Unusable
$0080 """""~"""..
$0080
Internal RAM
$OOFF~=~='-I
$OOFF
E xt~rnal Memory Space
$FOOO
Internal ROM
$FFF F
[NOTE)
Excludes the following address which may be
used externally: $04, $06, $OF.
Fig. 2-2-1
HD6301V1 Memory Maps
~HITACHI
139
2.3
Registers
The followings describe
operations.
fIS----"'- --_0:U~
the HD6301Vl internal architectures and
- - -
~-
-
0
-
3
:
8·8itAccumulatonAand8
Or 16·Bi, Doubla Accumulator D
1. 5
X
01
Index Register (XI
1. 5
s.
01
Stack .Pointer (SP)
1.
PC
01
0
5
7
~
Fig. 2-3-1
Program Counter (PC)
Condition Code Register (eCR)
Carry/Borrow from MSa
Overflow
Zero
Negative
Interrupt
Half carry (From Bit 3)
Registers of HD6301V1
(1) Accumulators (A & B, or D)
Two 8-bit registers (ACCA and ACCB) that store the/
result of arithmetic/logical operation and data.
When
combined, they make up a l6-bit register (ACCD) used
for l6-bit operations.
Note that the contents of ACCA
and ACCB are destroyed after an ACCD-based operation.
(2) Index Register (IX)
A 16-bit register that stores either l6-bit data intended
for use. in indexed addressing mode or ordinary 16-bit
data.
(3) Stack Pointer (SP)
A l6-bit register whose contents indicate the address of
a stack operation.
This may be used also as a register
for ordinary l6-bit data.
(4) Program Counter (PC)
A l6-bit register whose contents indicate the address of
the program being currently executed.
cannot access to this register •
•
140
HITACHI
Note that software
(5) Condition Code Register (CCR)
A register consisting of the following bits:
carry (C),
overflow (V), zero (Z), negative (N), interrupt mask (I),
and half-carry (H).
After an instruction is executed,
these bits change its states depending on the result of
operation and are tested by different conditional branch
instructions. The upper 2 bits of this register cannot
be used.
Individual bits are detailed below. Refer to
the following description of each instruction for more
I
details.
(a) Half-carry (H)
This bit is set to "1" if a carry from bit 3 to bit 4
occurs during execution of an ADD, ABA or ADC instruction;
it is cleared if no carry takes place.
(b) Interrupt mask (I)
When set at "1", this bit disables any maskable interrupt (IRQl, IRQ2).
(c) Negative (N)
After an instruction is executed, this bit is set to
"1" if the MSB as the result of operation is "1"; it is
cleared if the MSB is "0".
(d) Zero (Z)
After an instruction is executed, this bit is set to
"1" if the result of operation is "0"; otherwise, it is
cleared.
(e) Overflow (V)
After an instruction is executed, this bit is set if
the result of operation shows a 2's complement overflow;
it is cleared if no overflow occurs.
(f) Carry (C)
After an instruction is executed, this bit is set to
"1" if a carry or a borrow generates from MSB; it is
cleared in any other case.
~HgTACHO
141
2.4
I/O Ports
There are four I/O ports on HD6301Vl MCU (three 8-bit ports
and one 5-bit port).
the 8-bit port.
2 control pins are connected to one of
Each port has an independent write-only data
direction register to program individual I/O pins for input
or output.*
When the bit of associated Data Direction Register is "1",
I/O pin is programmed for output, if "0", then programmed for
an input.
There are four ports; Port 1, Port 2, Port 3, and Port 4.
Addresses of each port and associated Data Direction Register
are shown in Table 2-4-1.
* Only one exception is bit 1 of Port 2 which becomes either
a data input or a timer output.
It cannot be used as an
output port.
Table 2-4-1
Ports
Port and Data Direction Register Addresses
Port Address
Data Direction
Register Address
I/O Port 1
~0002
~OOOO
I/O Port 2
~0003
~OOOI
I/O Port 3
~0006
~0004
I/O Port 4
$0007
$0005
(1) I/O Port 1
This is an 8-bit port, each bit being defined individually
as inputs or outputs by associated Data Direction Register.
The 8-bit output buffers have three-state capability,
maintaining in high impedance state when they are used for
input.
In order to be read accurately, the voltage on the
input lines must be more than 2.0V for logic "1" and less
than 0.8V for logic "0".
These are TTL compatible.
After the MCU has been reset,
I
all I/O lines are configured as inputs in all modes except
mode 1.
In all modes other than expanded non multiplexed
mode 1, Port 1 is always parallel I/O.
In mode 1, Port 1
will be output line for lower order address lines
(Ao
to A7) •
~HITACHI
142
(2) I/O Port 2
This port has five lines, whose I/O direction depends on
its data direction register.
The 5-bit output buffers
have three-state capability, going high impedance state
when used as inputs.
In order to be read accurately, the
voltage on the input pins must be more than 2.0V for
logic "1" and less than 0.8V for logic "0".
After the
MCU has been reset, I/O pins are configured as inputs.
These pins on Port 2 (pins 10, 9, 8 of the chip) are used
to program the operating mode during reset.
The values of
these three pins during reset are latched into the upper 3
bits (bit 7,6 and 5).
Refer to "2.1 Mode Selection" for
more details.
In all modes, Port 2 can be configured as I/O lines.
This
port also provides access to the Serial I/O and the Timer.
However, note that bit 1 (PZl) is the only pin restricted
to data input or Timer output.
(3) I/O Port 3
This is an 8-bit port which can be configured as I/O lines,
a data bus, or an address bus multiplexed with data bus.
Its function depends on hardware operation mode programmed
by the user using 3 bits of Port 2 during Reset.
as a data bus is bi-directional.
Port 3
For an input from
peripherals, regular TTL level must be supplied, that is
greater than 2.0V for a logic "1" and less than 0.8V for
a logic "0".
This TTL compatible three-state buffer can
drive one TTL load and 90pF capacitance.
In the expanded
Modes, data direction register will be inhibited after Reset
and data flow will be dependent on the state of the R/W signal.
Function of Port 3 for each mode is explained below.
Single Chip Mode (Mode 7):
Parallel Inputs/Outputs as
programmed by its corresponding Data Direction Register.
There are two control lines associated with this port in
this mode, an input strobe (IS3) and an output strobe
(053), both being used for handshaking.
They are
~HITACHI
143
controlled by I/O Port 3 Control/Status Register.
Additional 3 characteristics of Port 3 are summarized as
follows:
(1)
Port 3 input data can be latched using IS3 (SCI)
as a control signal.
(2)
(3)
OS3 (SC 2 ) can be generated by MPU read or write to
Port 3's data register.
IRQl interrupt can be generated by an IS3 falling
edge.
Port 3 strobe and latch timings are shown in Figs. 5-5 and
5-6, respectively.
I/O Port 3 Control/Status Register
Bit 0 Not used.
Bit 1 Not used.
Bit 2 Not used.
Bit 3 LATCH ENABLE.
Bit 3 is used to control tbe input latch of Port 3.
If
t6e bit is set to "1", the input data on Port 3 is latched
by the falling edge of IS3.
The latch is cleared by the
MCU read to Port 3;
it can be latched again.
is cleared by a reset.
Bit 4
ass
Bit 3
(Output Strobe Select)
This bit identifies the cause of output strobe generation:
a write operation or read operation to I/O Port 3.
When
the bit is cleared, the strobe will be generated by a read
operation to Port 3. When the bit ~s not cleared, the
strobe will be generated by a write operation. Bit 4 is
cleared by reset.
Bit 5 Not used.
Bit 6 IS3 ENABLE.
If the IS3 flag (bit 7) is set with bit 6 set, an interrupt
~HITACHI
144
is enabled.
disabled.
Clearing the flag causes the interrupt to be
The bit is cleared by reset.
Bit 7 IS3 FLAG.
Bit 7 is a read-only bit which is set by the falling edge
of IS3 (SCI)'
It is cleared by a read of the Control/
Status Register followed by a read/write of I/O Port 3.
The bit is cleared by reset.
I
Expanded Non Multiplexed Mode (mode 1, 5)
In this mode, Port 3 becomes the data bus.
Expanded Multiplexed Mode (mode 0, 2, 4, 6)
Port 3 becomes both the data bus (Do
bits of the address bus
(Ao
~
A 7 ).
~
An
0 7 ) and lower 8
address strobe
output is "High" when the address is on the port.
(4)
I/O Port 4
This is an 8-bit port that becomes either I/O or address
output depending on the operation mode selected.
In order
to be read accurately, the voltage at the input lines must
be greater than 2.0V for a logic "I", and less than 0.8V
for a logic "0".
For outputs, each line is TTL compatible
and can drive one TTL load and 90pF capacitance.
reset, this port becomes inputs.
After
To use these pins as
addresses, they should be programmed as outputs.
Function of Port 4 for each mode is explained below.
Single Chip Mode (Mode 7):
Parallel Inputs/Outputs as
programmed by its associated data direction register.
Expanded Non Multiplexed Mode (Mode 5):
In this mode,
Port 4 becomes the lower address lines (Ao to A7) by
writing "l"s on the data direction register.
When all of the eight bits are not required as addresses,
the remaining lines can be used as I/O lines (Inputs only).
Expanded Non Multiplexed Mode (Mode 1):
In this mode,
Port 4 becomes output for upper order address lines (As
to Al 5) •
~HITACHI
145
Expanded Multiplexed Mode (Mode 0, 2, 4):
In this mode,
Port 4 becomes output for upper order address lines (As
to A1S) regardless of the value of data direction register.
The relation between each mode and I/O port 1 to 4 is
summarized in Table 2-1-2.
2.5
Programmable Timer
The HD6301Vl provides 16-bit programmable timer which can
measure input waveform and generate an output waveform.
The pulse width of both input/output may vary from microseconds to seconds.
microseconds to many seconds.
The timer hardware consists of
an 8-bit control and status register
a 16-bit free running counter
a 16-bit output compare register, and
a 16-bit input capture register
A block diagram of the timer is shown in Figure 2-5-1.
Bill
PO'12
"R
j---
OIl1;pll'Comput" Pulse
Fig. 2-5-1
-
-
-
:
- _I
Input
Bit 1
Port2
BilO
Port2
~I
Edge
Programmable Timer Block Diagram
~HITACHI
146
--
OuIPUt
(1) Free Running Counter ($0009:000A)
The key timer element is a l6-bit free running counter,
that is driven by an E (Enable) clock to increment its
values.
The counter value is readable by the MPU soft-
ware at any time with no effects on the counter.
The
counter is cleared during reset.
When writing to the upper byte ($09), the CPU writes the
preset value ($FFF8)
into the counter (address $09, $OA)
regardless of the write data value.
But when writing to
the lower byte ($OA) after the upper byte writing, the
CPU writes not only the lower byte data into lower 8 bit,
but also the upper byte data into higher 8 bit of the FRC.
The counter value written to the counter using the double
store instruction is shown in Figure 2-5-2.
($5AF3 written to the counter)
Fig. 2-5-2
*
Counter Write Timing
To write to the counter can disturb serial operations, so it should be inhibited during using the
SCI.
(2) Output Compare Register
(~OOOB:$OOOC)
This is a l6-bit read/write register which is used to
control an output waveform.
The data of this register is
constantly compared with the free running counter.
When the data matches, a flag (OCF) in the timer controll
status register (TCSR) is set and the current value of an
output level Bit (OLVL) in the TCSR is transferred to Port
2 bit 1.
is "1"
Port 2.
When bit 1 of the Port 2 data direction register
(output)
the OLVL value will appear on the bit 1 of
Then, the value of Output Compare Register and
Output level bit should be changed to control an output
level again on the next compare values.
~HITACHI
147
The output compare register is set to $FFFF during reset.
The compare function is inhibited at the cycle of writing
to the upper bytes of the output compare register and at
the cycle just after that.
It is also inhibited in same
manner at the cycle of writing to the free running counter.
*
For the data write to The OCR (Output Compare Register) ,
2-byte transfer instructions such as STD, STX are available.
(3) Input Capture Register
($OOOD:~OOOE)
The input capture register is a 16-bit read-only register
used to store the FRC's value obtained when the proper
transition of an external input signal occurs.
The input transition change required to trigger the
counter transfer is controlled by the input Edge bit
(IEDG) .
To allow the external input signal to gate in the edge
detector, the bit of the Data Direction Register
corresponding to bit 0 of Port 2 must have been cleared
(to zero) .
To insure input capture in all cases, the width of an
input pulse requires at least 2 Enable cycles.
(4) Timer Control/Status Register (TCSR)
This is an 8-bit register.
($0008)
All 8 bits are readable and
the lower 5 bits may be written.
The upper 3 bits are
read-only, indicating the timer status information below.
(a) Defined transition of the timer input signal
causes the counter to transfer its data to the
ICR.
(b) A match has been found between the value in the free
running counter and the output compare register (OCF).
(c) The counter value reached to $0000 as a result of
counting-up (TOF).
Each flag may contain an individual enable bit in TCSR
which controls whether or not an interrupt request may be
~HITACHI
148
output to internal interrupt signal (IRQz).
If the I-bit
in Condition Code Register has been cleared, a priority
vectored address occurs corresponding to each flag being
set.
Each bit is described as follows.
Timer Control/Status Register
7
654
3
2
1
0
LI_IC_F~I_o_C_F~I_T_O_F-L_E_I~C_I~I_E_O_C_I-LI_E_T_O_I-L_I_E_D_G~_O_LV_L~ $0008
Bit 0
OLVL (Output Level);
I
When a match is found in the
value between the counter and the output compare
register, this bit is transferred to the Port 2 bit 1.
If the DDR corresponding to Port 2 bit 1 is set to "1",
the value will appear on the output pin of Port 2
bit 1.
Bit 1 IEDG (Input Edge);
This bit control which transition
of an input of Port 2 bit 0 will trigger the data
transfer from the counter to the input capture
register.
The DDR corresponding to Port 2 bit 0
must be cleared in advance of using this function.
When IEDG
=
0, trigger takes place on a falling
edge ("High"-to-"Low" transition).
When IEDG = 1,
trigger takes place on a rising edge ("Low"-to"High" transition).
Bit 2 ETOI (Enable Timer Overflow Interrupt);
When set,
this bit enables TOF interrupt to generate the interrupt request (IRQ2) but when cleared, the interrupt is
inhibited.
Bit 3 EOCI (Enable Output Compare Interrupt);
When set,
this bit enables OCF interrupt to generate the
interrupt request (IRQ2), when cleared, the interrupt
is inhibited.
~HITACHI
149
Bit 4 EICI (Enable Input Capture Interrupt);
When set,
this bit enables ICF interrupt to generate the
interrupt reguest (IRQ2) but when cleared, the interrupt is inhibited.
Bit 5 TOF (Timer Overflow Flag);
This read-only bit is
set'-'when the counter value is $0000.
It is cleared
by CPU read of TCSR (with TOF set) followed by an CPU
read of the counter ($0009).
Bit 6
OCF (Output Compare Flag);
This read-only bit is
set when a match is found in the value between the
output compare register and the counter.
It is clear-
ed by a read of TCSR (with OCF set) followed by an CPU
write to the output compare register ($OOOB or ~OOOC) .
Bit 7
ICF (Input Capture Flag);
The read-only bit is,set
when an input signal to edge detector makes a transition as defined by IEDG, and is cleared by a read of
TCSR (with ICF set) followed by an CPU read of Input
Capture Register ($OOOD).
Each bit of Timer Control and Status Register is cleared
during reset.
2.6
Serial Communication Interface
The HD6301Vl contains a full-duplex asynchronous Serial
Communication Interface (SCI).
SCI may select the several
kinds of the data transmit rate and comprises a transmitter
and a receiver which operate independently on each other
but at the same data transmit rate.
Both of transmitter
and receiver communicate with the CPU by the data bus, and
with the outside through Port 2 bit 2, 3 and 4.
Descrip-
tion of hardware, software register is as follows.
(1) Wake-Up Function
In typical multiprocessor applications the software
protocol has the destination address at the initial
byte of the message.
The purpose of Wake-Up function
is to have the non-selected MCU neglect the remainder
of the message.
Thus the non-selected MCU can inhibit
~HITACHI
150
the all further interrupt process until the next
message begins.
Wake-Up function is triggered by a ten consecutive "l"s
which indicates an idle transmit line.
Therefore soft-
ware protocol needs an idle period between the messages.
With this hardware feature, the non-selected MPU is reenabled (or "wakes-up") for the appearing next message.
(2) Programmable option
I
The HD6301Vl has the following optional features provided
for its Serial I/O. They are all programmable.
data format; standard mark/space (NRZ) start bit +
8 bit data + 1 stop bit
Clock source; external or internal
baud rate; one of 4 rates per given MCU E clock frequency
or 1/8 of external clock
wake-up function; enabled or disabled
• Interrupt requests; enabled or masked individually for
transmitter and receive data
registers
Clock Output; internal clock enabled or disabled to
Port 2 bit 2
• Port 2 (bits 3,4); dedicated or not dedicated to serial
I/O individually for receiver and
transmitter
(3) Serial Communication Hardware
The serial communications hardware is controlled by 4
registers as shown in Figure 2-6-1.
The registers include:
an 8-bit control/status register
a 4-bit rate/mode control register (write-only)
an 8-bit read-only receive data register
an 8-bit write-only transmit data register
Besides these 4 registers, Serial I/O utilizes Port 2 bit
3 (input) and bit 4 (output). Port 2 bit 2 can be used
when an option is selected for the internal-clack-out or
the external-clack-in.
(4) Transmit/Receive Control Status Register (TRCSR)
TRCS Register consists of 8 bits which all may be read
@HHTACHU
151
while only bits 0 to 4 may be written.
initialized to $20 on RES.
are defined as follows.
I
The register is
The bits of the TRCS register
Transmit/Receive Control Status Register
76543
210
ADDR:
RDRF I ORFE I TORE I RIE I RE I TIE I TE I WU I
$0011
Bit 0
WU (Wake Up);
Set by software and cleared by hard-
ware on receipt of ten consecutive "l"s.
It should be
noted that RE flag has already set in advance of WU
flag's set.
Bit 1
TE (Transmit Enable);
Set to produce preamble of
ten consecutive "l"s and to enable the data of transmitter to output subsequently to the Port 2 bit 4
independently of its corresponding DDR value.
When
cleared, serial I/O affects nothing on Port 2 bit 4.
Bit 2
TIE (Transmit Interrupt Enable);
When this bit is
set with TORE (bit 5) set, it will permit an IRQ2
interrupt.
Bit 3
When cleared, TORE interrupt is masked.
RE (Receive Enable);
When set, gates Port 2 bit 3
to input of receiver regardless of DDR value for this
bit.
When cleared, the serial I/O affects nothing on
Port 2 bit 3.
Bit 4
RIE (Receive Interrupt Enable);
When this bit is
set with bit 7 (RDRF) or a bit 6 (ORPE) set, it will
permit an IRQz.
Bit 5
When cleared, IRQ2 interrupt is masked.
TORE (Transmit Data Register Empty);
When the data
transfer is made from the Transmit Data Register to
Output Shift Register, it is set by hardware.
The bit
is cleared by reading the status register (with TORE
set) and followed by writing the next new data into the
Transmit Data Register.
Bit 6
TORE is initialized to 1 by RES.
ORFE (Over Run Framing Error);
When overrun or
framing error occurs (receive only), it is set by
hardware.
Over Run Error occurs if the attempt is
made to transfer the new byte to the receive data
~HITACHI
152
register with theRDRF set.
Framing Error occurs
when the bit counters are not synchronized with the
boundary of the byte in the bit stream.
The bit is
cleared by reading the status register (with ORFE set)
followed by reading the receive data register, or
by RES.
Bit 7 RDRF (Receive Data Register Full); It is set by
hardware when the data transfer is made from the
receive shift register to the receive data register.
It is cleared by reading the status register (with
RDRF set) and followed by reading the receive data
register, or by RES.
Bit 7
Rate and Mode Control Register
I
Bit 0
I eel Ieeol
I I I Iwu
55115501$10
Transmit/Receive Control and Status Register
IADAFjOAFE1TDAEl AlE
AE
TIE
TE
1$11
Receive Data Register
$12
Port2
I~~ ~___
I_I____
Clock
B~t
~_________A_ec_._ive_S~h_ift_A_.9_is_t._r______
-J
10
1----------------1
I+-----E
'--_-,-_....J
Transmit Shift Register
$13
Transmit Oats Register
SCI Register
Fig. 2-6-1
x
I
6
5
x
x
3
4
I
x
I
eel
I
ceo
I
1
0
SSl
SSO
AD DR
$0010
Rate I Mode Control Register
Table 2-6-1
551
550
0
0
SCI Bit Times and Transfer Rates
XTAL
2.4576 MHz
4.0 MHz
E
614.4 kHz
1.0MHz
E.;- 16
26 1'5/38,400 8aud
16
1'5/62,500 8aud
4.9152MHz
1.2288MHz
13
1'5 I 76,8ooBaud
0
1
E.;- 128
2081'5/4,800 Baud
128 1'5/7812.58aud
104.21'5 I 9,600Baud
1
0
E.;- 1024
1.67m5/6oo Baud
1.024m5/976.6 Baud
833.31'$ I 1,200Baud
1
1
E.;- 4096
6.67m5/150 Baud
4.096m5/244.1 Baud
3.333m$
I
300Baud
~HITACHI
153
Table 2-6-2 SCI Format and Clock Source Control
CC1,CCO
Format
Clock Source
Port 2 Bit2
Port 2 Bit3
Port 2 Bit4
00
-
-
-
01
NRZ
Internal
Not Used"·
10
NRZ
Internal
Output·
11
NRZ
External
Input
....
..
......
-
.. Clock output is available regardless of values for bits R E and TE .
... Bit 3 is used for serial input if RE = "1" in TReS.
_._Bit 4 is used for serial output if TE = "1" in TReS.
It can be used as I/O port.
(5) Transmit Rate/Mode Control Register (RMCR)
The register controls the following serial I/O variables:
·clock source
·Baud rate
·Port 2, bit 2 function
It is 4-bit write-only register, cleared by RES.
bits are considered as a pair of 2-bit fields.
The 4
The lower
2 bits control the bit rate of internal clock while the
upper 2 bits control the clock select logic.
Bit 0 sso
Bit 1 SSI
1
J
Speed Select
These bits select the Baud rate for the internal clock.
The selectable 4 rates are function of E clock frequency
within the MCU.
Table 2-6-1 lists the available Baud
Rates.
Bit 2 cco
Bit 3 CCI
1
f Clock
Control/Format Select
These bits control the clock select logic.
Table 2-6-2 defines the bit field.
(6) Internally Generated Clock
When using the internal clock for the SCI externally, the
followings should be noted.
• The values of RE and TE have no effect.
• CCl, CCO must be set to "10".
• The maximum clock rate is E/16.
• The clock is once the bit rate.
(7) Externally Generated Clock
When supplying an external clock for the SCI, the
followings should be noted.
~HITACHI
154
• The CC1, CCO, in the Rate and Mode Control Register
must be set to "11" (See Table 2-6-2).
• The external clock frequency must be set to 8 times
the desired baud rate.
The maximum external clock frequency is half of E
clock.
(8) Serial Operations
I
The serial I/O hardware must be initialized by the HD6301Vl
software prior to operation.
The sequence is normally
as follows .
• Writing the desired operation control bits to the Rate
and Mode Control Register .
• writing the desired operation control bits to the TRCS
Register.
If using Port 2 bit 3, 4 for serial I/O exclusively, TE,
RE bits may be preserved set.
When TE, RE bit cleared
during SCl operation, and subsequently set again, it
should be noted that the setting of TE, RE must refrain
for at least one bit time of the current baud rate.
If
set within one bit time, there may be the case where the
initializing of internal function for transmit and
receive does not take place.
(9) Transmit Operation
Data transmission is enabled by the TE bit in the TRCS
register.
When set,
outpu~s
the data of the serial
transmit shift register to Port 2 bit 4 which is unconditionally configured as an output irrespectively of
corresponding DDR value.
Following RES, the user should configure both the RMC
~egister
and the TRCS register for desired operation.
Setting the TE bit during this procedure causes a transmission of ten-bit preamble of "l"s.
Following the
preamble, internal synchronization is established and the
transmitter section is ready to operate.
Then either of
the followings operates.
~HITACHI
155
(a) If the transmit data register is empty (TDRE
=
1) ,
the consecutive "l"s are transmitted indicating an
idle lines.
(b)
If the data has been loaded into the Transmit Data
Register (TDRE
=
0), it is transferred to the output
shift register and data transmission begins.
During the data transfer, the "0" start bit is first
transferred.
Next the 8-bit data (beginning at bit 0)
and the "1" stop bit.
When the transmit data register
has been empty, the hardware sets the TDRE flag bit:
If the CPU fails to respond to the flag within the
proper time, TDRE is preserved set and then a "1" will
be sent (instead of a "0" at start bit time) and more "l"s
will be set consecutively until the data is supplied to
the data register.
While the TDRE remains a "1", no "0"
will be sent.
(10) Receive Operation
The receive operation is enabled by the RE bit.
serial input is connected with Port 2 bit 3.
The
The receive
operation is determined by the contents of the TRCS and
RMC register.
The received bit stream is synchronized
by the first "0"
(space).
During 10-bit time, the data
is strobed approximately at the center of each bit.
If the tenth bit is not "1"
(stop bit), the system
assumes a framing error and the ORFE is set.
(RDRF is
not set.)
If the tenth bit is "1", the data is transferred to the
receive data register, with the interrupt flag set(RDRF).If
the tenth bit of the next data is received, however, still
RDRF is preserved set, then ORFE is set indicating that
an overrun error has occurred.
After the CPU read of the status register as a response
to RDRF flag or ORFE flag followed by the CPU read of
the receive data. register, RDRF or ORFE will be cleared.
(11) Timer, SCI Status Flag
The set and reset condition of each status flag of timer
and SCI is shown in Table 2-7.
~HITACHI
156
2.7
Interrupts
The H06301Vl has two external interrupt pins (NMI, IRQ1)
and 8 internal interrupt source (Soft-TRAP, SWI, Timer-ICF,
OCF, TOF, SCI-RDRF, ORFE, TORE).
The features of these
interrupt are detailed in the following paragraphs.
(1) Non maskable Interrupt (NMI)
When the input signal of this pin is recognized to fall,
NMI sequence starts. The current instruction is continued
to the last if NMI signal is detected as well as the following IRQl interrupt.
Interrupt mask bit in Condition Code
I
Register has no effect on NMI interrupt.
In response to NMI
interrupt, the contents of Program Counter, Index Register
Accumulators, and Condition Code Register are stored on the
stack.
On completion of this sequence, vectoring address
$FFFC and $FFFO will occur to load the contents to the program
counter and branch to a non maskable interrupt service routine.
Inputs IRQ!, and NMI are hardware interrupt lines sampled by
internal clock.
After the execution of instructions, start
the interrupt routine in synchronization with E.
(2) Interrupt Request (IRQ1)
This is the level-sensitive pin which requests an internal
interrupt sequence to the
cpu
cpu.
At interrupt request, the
will complete the current instruction before the
acceptance of the request.
Unless the interrupt mask in
the condition code register is set,
the CPU starts an
,
interrupt sequence; if set, the interrupt request will be
ignored.
When the sequence starts, the contents of Program Counter,
Index Register, Accumulator, Condition Code Register are
stored on the stack.
Then the CPU sets the interrupt mask
bit and will not acknowledge the maskable request.
At the end of the cycle, the CPU generates 16 bit vectoring
addresses indicating memory addresses ~FFF8 and ~FFF9, and
locates the contents in Program Counter to branch to an
interrupt service routine.
~Il-IIDTACHD
157
(3) Internal interrupts
For an internal interrupt requested from the timer or SCI,
an internal interrupt signal IRQ2 is activated.
This
interrupt is identical to IRQ! except that it uses vector
addresses $FFFO through $FFF7. The IRQl has the priority
to the IRQ2 when interrupt requests have taken place at
the same time.
When the interrupt mask bit in the condi-
tion code register is set, both interrupts are inhibited.
The SWI is an instruction which requests an interrupt by
software.
the SWI.
The state of CCR mask bit doesn't influence
If an address error or operation code error
(see "2.13 Error Processing") occurs, TRAP takes place
whose priority is next to the reset.
In the case of
TRAP, CPU starts the interrupt sequence regardless of the
state of the mask bit.
The vectors corresponding to this
interrupt are $FFEE and $FFEF.
The memory map for inter-
rupt vectors is shown in Table 2-7-1 and the interrupt
sequence are shown in Fig. 2-7-1.
Fig. 2-7-2 shows the
logic of the interrupt circuit.
Table 2-7-1
Interrupt Vectoring Memory Map
Vector
Highest
Priority
Lowest
Priority
Interrupt
MSB
LSB
FFFE
FFFF
FFEE
FFEF
TRAP
FFFC
FFFD
NMI
FFFA
FFFB
RES
Software Interrupt (SWI)
IRQl
(or IS3)
FFF8
FFF9
FFF6
FFF7
FFF4
FFF5
rCF (Timer Input Capture)
OCF (Timer Output Compare)
FFF2
FFF3
TOF (Timer Overflow)
FFFO
FFFl
SCI (RDRF+ORFE+TDRE)
~HITACHI
158
Interrupt
Test
Internal
-_J\..+~~=~~,.d"-=.,A-::S"'p.J\""S""P""olJ."'S"'P"'o2.,.Jl.."SP""o""3A...Sp""o...JL..,.SP-o""SA""S""Po""6.AV-ec-to-,Av-eo-.to-,AN-eW-pJciL_J.....
Address Bus
NMi.
~::ress k~~ress
IRQI. IR02
Address
Internal
Data au. _ _.A_.....J~=A=~"l-..-.J\___~_J'--_A_-lL_A_-lL_A_
~~:~nal
~g~5
Internal
Write
:~~-
:~~;
ACCA
ACCa
CCR
_____~I
\
Fig. 2-7-1
I
Interrupt Sequence
ICF------r-~------------~IC~I~
EICI
OCI
TOF
RDRF-----"',--...
OR FE - - - - z . - "
Interrupt
Request
Signal
TORE-----------r~
iS3 FLAG------r-....
fS3 ENABLE
Sleep
Release
Signal
NMI
TRAP
SWI----------------------------------------~
Fig. 2-7-2
2.8
Logic of Interrupt Circuit
Reset (RES)
This input is used to reset the MCU and start it from a
power-off condition.
During Power-on, RES pin must be
held "Low" for at least 20ms.
To reset the MCU during
system operation, it must be held "Low" at least 3 system
clock cycles.
At the 3rd cycle during "Low" level, all
address buses become "High impedance" while RES is "Low".
Detecting "High" level, MCU operates as followings.
~HITACHI
159
a
(1)
Latch I/O Port 2 bits 2, 1,
pca of mode register.
into bits PC2, PC1,
(2)
Put the contents (=start address) of the last two
addresses ($FFFE, $FFFF) into the program counter
and start the program from this address.
(Refer to
Table 2-7-1)
(3)
Set the interrupt mask bit.
For the CPU to
recognize the maskable interrupts IRQl and IRQ2, this
bit should be cleared in advance.
Fig. 2-8-1 shows
the reset timing, and Table 2-8-1 shows the pin condition during reset.
:&\\\Wl~\\\\\\\\\\\\\
,:=:c:l.f----\r-I- - - -
~'''n.. _~\\\\\\§\§\\\\\\\\\
:~r------II-\- - - - - -
:;""n.' _
~\\\\\\\\\\§§\\\\\\\\II
RIW _
~:·_~\\\\\\\\\\\§\\\§\\\\\\\\§\\\t----------i'r"- - - -
Fig. 2-8-1
Table 2-8-1
~
Pin
Port 1
P1O'VP17
port 2
P2 OII
..
..
..
..
.
..
..
"1" output
~HITACHI
160
7
6
..
..
..
"1" output
E, "1" output
High impedance
E,High impedance
(input)
2.9
Oscillator
XTAL, EXTAL pins interface with an AT-cut parallel resonant
crystal.
Divide-by-four circuit is on chip, so if 4 MHz
crystal oscillator is used, the system clock is 1 MHz for
example.
EXTAL pin can be drived by the external clock with
45% to 55% duty.
The system clock which is one fourth
frequency of the external clock is generated in the LSI.
When using the external clock, XTAL pin should be open.
Fig. 2-9-1 shows examples of connection circuit.
AT Cut Parallel Resonance Crystal
Co = 7 pF max
Rs = 60 n max
XTAL
EXTAL
~
T
Fig. 2-9-1
2.10
C Ll = C L2 = 10-22pF
±
20%
(3.2 -SMHz)
±"t"
Crystal Interface
Strobe Signals
Two pins, SCI (39 pin) and SC2
(38 pin) are used as
the strobe signals in each mode.
Followings are applied
only to Port 3 in single. chip mode.
(1) Input Strobe (IS3)
(SCI)
This signal controls IS3 interrupt and the latch of Port
3.
When the falling edge of this signal is detected, the
flag of Port 3 Control Status Register is set.
For respective bits of Port 3 Control Status Register,
see the "2.4 I/O Ports" section.
(2)
output Strobe (OS3) (SCz)
This signal is used by the processor to strobe an external
device, indicating effective data is on the I/O pins.
The timing chart for Output Strobe are shown in figure 5-5.
The following pins are available for Expanded Modes.
~HITACHI
161
(3) Read/Write (R/W)
(SC2)
This TTL compatible output signal indicates peripheral
and memory devices whether the CPU is in Read (nHigh"),
or in Write ("Low").
The normal stand-by state of this
signal is Read ("High").
This output can drive one TTL
load and 90pF capacitance.
(4) I/O Strobe (lOS)
(SCi)
In expanded non multiplexed mode 5 of operation, lOS
becomes "Low" when Ag through A15 are "O"s and As is
"1".
This allows external access of 256 addresses from
$0100 to $OlFF in memory.
The timing chart is shown in
Figure 5-2.
(5) Address Strobe (AS)
(SCI)
In the expanded multiplexed mode of operation, address strobe
is output to this pin.
This signal is used to latch the i',
lower 8 bits addresses multiplexed with data at Port 3 and to
control the 8-bit latch by address strobe as shown in Figure
2-1-4.
Thereby, I/O Port 3 can become data bus during E
pulse.
The timing chart of this signal is shown in Figure
5-1.
2.11
RAM Control Register
The register assigned to the address $0014 gives a status
information about standby RAM.
RAM Control Register
6
7
$0014
Bit
Bit
Bit
Bit
Bit
Bit
Bit
5
4
3
STBY
PWR
2
1
o
x
x
x
0 Not used.
1 Not used.
2 Not used.
3 Not used.
4 Not used.
5 Not used.
6 RAM Enable.
USing this control bit, the user can disable the RAM.
RAM Enable bit is set on the positive edge of RES and RAM
is enabled.
With the program control, it is capable of
writing "I" or "0'''.
With the disabled RAM (logic "0"),
$HITACHI
162
the RAM address becomes external address and the CPU may
read the data from the outside memory.
Bit 7 Standby Bit
This bit is cleared when VCC is not provided in standby
mode.
This bit is a read/write status flag that user can
read.
If this bit is preserved set, indicating that VCC
voltage is applied and the data in the RAM is valid.
2.12
Low Power Consumption Mode
The HD6301Vl has two low power consumption modes; sleep
and standby.
(1)
Sleep Mode
On execution of SLP instruction, the CPU is brought to
the sleep mode.
In the sleep mode, the CPU stops its
operation, but the contents of the register in the CPU
are retained.
In this mode, the peripherals of MPU
will remain operational.
So the operations such as
transmit and receive of the SCI data and counter may
keep on functioning.
In this mode, the power consump-
tion is one-sixth that of operating condition.
The MCU returns from this mode by interrupt, RES, STBY.
The RES resets the MCU and the STBY brings it into the
standby mode (This will be mentioned later).
When the
CPU acknowledges an interrupt request, it cancels the
sleep mode, returns to the operation mode and branches
to the interrupt routine.
When the CPU masks the
interrupt, it cancels the sleep mode and executes the
next instruction.
However, for example, if the timer
1 or 2 prohibits a timer interrupt, the CPU doesn't
cancel the sleep mode because of no interrupt request.
This sleep mode is available to reduce the power consumption for a system with no need of the HD6301Vl's
consecutive operation.
Please refer to Table 2-12-1 for other pins except VCC,
clock pin, input-only pin, E clock pin (their function
are the same as operating condition) .
~HITACHI
163
(2) Standby Mode
The HD6301Vl stops all the clocks and goes into the
reset state with STBY "Low".
In this~mode, the power
consumption is reduced conspicuously.
In the standby mode, the power is supplied to the
HD6301Vl, so the contents of RAM are retained. The
standby mode should escape by bringing
ST'BY "High".
Transitions among the active mode, sleep mode, standby
mode and reset are shown in Fig. 2-12-2.
Table 2-12-1
-::----::e
Pin
0
Function
I/O Port
Port 1
PiO vP 17
P20'VP24
Function
Port 3
P 30'VP37
I/O Port
Keep the conCondition dition just
before sleep
Lower Address
Bus
..
..
E:Lower
Address Bus Data Bus
E:Data Bus
E:Output "1"
Condition E:High impe-
Upper Address
5
..
I/O Port
..
..
Keep the condition just
before sleep
..
..
...
E:Lower
Address Bus
Condition Output "1"
..
.
..
.
..
.
..
..
I/O Port
E:Output "1"
E:Output "1"
High impedanc e E:High impe-
High impedance E : High impe-
Keep the condition just
before sleep
dance
dance
..
..
..
.
..
..
SC2
Output "1"
(Read Condition)
..
SCI
Output Address Strobe
.
~HITACHI
164
7
E:Lower
Data-Bus
E:Data Bus
Port 4
P"O"'P47
6
Address Bus
E:Data Bus
dance
Function
2.4
1
Keep the conCondition dition just
Output "1"
before sleep
Function
Port 2
Pin Condition in Sleep Mode
LoWer Address
Bus or Input
Port
Address Bus:
Output 11111
Port: Keep the
condition
just before
sleep
..
Output "1"
Upper Address
Bus or Input
I/O Port
Port
.
Keep the condition just
before sleep
..
Output "1"
Output Address Strobe
Input Pin
Internal
E clock
I
Stop in sleep
mode clock
~
Sleep cleared
Address
bus
-
::E:
~
(')
Data
bus
L-I
~
~~l
@i+l
I
:I
\.§;+2
I Interrupt
Sleep
instruction
~
1--J
PCn-l
Interrupt
occurs
PCn
PCn+l
PCn+2
PCn+3
sleep is
cleared without
interrupt masked
Sleep Instruction Timing Chart
......
ffi
save routine
Address
--+ PCn+l
bus where
~~~~~~~~~~~-J~~~~____
program
Fig. 2-12-1
Sleep is cleared
with interrupt
masked
--
Fig. 2-12-2 Transitions among Active Mode, Standby Mode
Sleep Mode, and Reset
~HITACHI
166
2.13
TRAP Function
The CPU generates an interrupt with the highest priority
(TRAP) when fetching an undefined instruction or an instruction from non-memory space.
The TRAP prevents the system-
burst caused by noise or a program error.
(1) Op-Code Error
When fetching an undefined op-code, the CPU saves register
as well as a normal interrupt and branches to the TRAP
($FFEE, $FFEF).
I
This has the priority next to reset.
(2) Address Error
When an instruction is fetched from excluding internal
ROM, RAM, or an external memory area, the MCU generates
the same interrupt as op-code error.
If the instruction
is fetched from external memory area without memory devices,
this function is not applicable.
Table 2-13-1 shows addresses where an address error occurs
to each mode.
This function is available only for the
instruction fetch, and is not applicable to the access of
normal data read/write.
Table 2-13-1
Addresses Applicable to Address Errors
Mode
0
1
4
5
6
7
$0000
I
$OOIF
$0000
I
$OOIF
$0000
I
Address
$0000
I
$OOIF
$0000
I
$OOIF
$0000
I
~007F
0100
I
$EFFF
~007F
0200
I
$EFFF
~HITACHI
167
3.
INSTRUCTIONS
The HD6301Vl Provides object code upward.
Besides having
object code compatible with the HD6801 series, the HD6301Vl
the predecessor with additional instructions; enhances bit
control instructions (AIM, ElM, aIM, TIM), index/accumulator
exchange instruction (XGDX), and sleep instruction (SLP).
These new instructions improve programming efficiency.
3.1
Addressing Modes
The HD6301Vl provides seven addressing modes.
The adequate
selection of these addressing mode will permit to implement
an efficient and easy programming.
The addressing mode is determined by an instruction type and
code.
The addressing mode for each instruction is shown in
Table 3-2-1 to 3-2-4 with execution time counted by the
machine cycles.
When the clock frequency is 4 MHz, the
machine cycle time will be microseconds.
Accumulator (ACCX) Addressing
Only an accumulator is addressed.
B is selected.
Either accumulator A or
This is a one-byte instruction.
Immediate Addressing
In this mode, the data is stored in the second byte of the
instruction except that LDS and LDX, store a data in the
second and the third byte exceptionally.
These are two or
three-byte instructions.
Direct Addressing
In this mode, the second byte of an instruction indicates
the address where the data is stored.
256 bytes ($0
through $255) can be addressed directly.
Execution times
can be reduced by storing data in these locations.
In
configurating system, it is recommended that these locations
should be RAM for users' data area.
These are two-byte
instructions, while the AIM, aIM. ElM and TIM are threebyte.
~HITACHI
168
Extended Addressing
In this mode, the second byte indicates the upper 8 bits
addresses where the data is stored, and the third byte
indicates the lower 8 bits.
These are three-byte instruc-
tions.
Indexed Addressing
In this mode, the contents of the second byte and the
lower 8 bits in the Index Register are added.
As for AIM,
I
OIM, ElM and TIM instructions, the contents of the third
byte and the lower 8 bits in the Index Register are added.
In addition, this carry is added to the upper 8 bits in
the Index Register.
memory.
The result is used for addressing
The modified address is held in the Temporary
Address Register, so there is no change to the contents of
the Index Register.
These are two-byte instructions, while
AIM, OIM, ElM and TIM are three-byte.
Implied Addressing
In this mode, the instruction itself gives the address.
That is, the instruction addresses an accumulator,
stack pointer, index register, etc.
This is a one-byte
instruction.
Relative Addressing
In this mode, the contents of the second byte and the
lower 8 bits in the program counter are added.
carry or borrow is added to the upper 8 bits.
The
So
addressing from -126 to +129 bytes of the current
instruction is enabled.
These are two-byte instructions.
~HITACHI
169
3.2
Instruction Set
TheHD6301Vl has an upward object code compatible with the
HD6801 to utilize all instruction sets of the HMCS6800.
The execution time of the key instruction is reduced to
increase the system through-put.
In addition, the bit
manipulation instruction, the exchange instruction of the
index and the accumulator, the sleep instruction are added.
The followings are described here.
• Accumulator and memory manipulation instructions (See
Table 3-2-l).
Additional instructions.
• Index register and stack manipulation instructions (See
Table 3-2-2).
• Jump and branch instructions (See Table 3-2-3).
• Condition code register manipulation instructions (See
Table 3-2-4).
• Op-code map (See Table 3-2-S).
~HITACHI
170
Accumulator, Memory Manipulation Instructions
Table 3-2-1
ConditIon Code
Addressing Modes
Operation,
-
OP
-
2
2
9B
3 2 A8 4
C8
2
2
DB
3
C3
3
3
03
4
8B
ADDB
Add Double
ADDD
Add Accumulltors
A8A
Add Wit" Carry
ADCA
ADC8
AND
ANDA
AN DB
C4
Bit Test
BIT A
85
2
BIT B
C5
2
Compare
INDEX
#
ADDA
Clear
DIRECT
IMMED
DP
Add
Register
.-
Mnemonic
OP
#
2
2
-
EXTEND
IMPLIED
OP
-
#
2 88
4
3
A +
#
OP
2
2
99
C9
2 2
09
84
2
-
#
M.... A
EB
4
2
FB
4
3
8+M-e
E3
5
2
F3
5
3
A
lB
89
Boolean/
Arithmetic Operation
3
2 A9
3 2 E9
4
2
89
4
1
1
B + M: M ... 1- A :B
A + B- A
A+MtC-A
3
4
2
F9
4
3
B+M+C-B
2 94
3
2
A4
4
2 B4
4
3
A·M-A
2 2 04
2 95
3
2
2
E4
4
2
F4
4
3
B·M- B
3
AS
4
2
B5
4
3
A·M
05
3
2
E5
4
2
F5
4
3
B·M
6F
5
2
7F
5
3
2
CLR
00 - M
CLRA
4F
1
1 00 - A
CLRB
SF
1
1 00 - B
CMPA
81
2
CMPB
Cl
2
Compare
Accumulators
CeA
Complement, ,'s
COM
2 91
2 01
2
3 .2
3
Al
4
2
Bl
4
3
A-M
El
4
2
Fl
4
3
B-M
63
6
2
73
6
3
11
1
1
A-B
M-M
A -A
COMA
43
1
1
COMB
53
1
1 8 -B
Complement, 2',
NEG
(Nega.a'
NEGA
40
1
NEGB
50
1
Oec:mal Adjust. A
DAA
19
2 1
Oecrement
DEC
DECA
4A
1
1 A-I - A
DEC8
5A
1
1 B-l-B
Exclusive OR
Increment
60
6A
EORA
88
EORB
CB
2 2 98 3 2
2 DB 3 2
2
INC
6
6
2
2
70
7A
2
88
4
3
A@M-A
2
F8
4
3
B@M- 8
6C
6
2
7C
6
3
M+l-M
INCA
4C
1
1
A + 1 .... A
INCB
5C
1
1
B ... 1- B
LDAA
M-A
4
3
M-B
FC
5
3
M + 1- B. M- A
2
2
06
3
2
E6
4
3
3
DC
4
2
EC
5
2
Multiply Unsigned
MUL
OR, Inclusive
ORAA
ORAB
2 2 96
3
2
4
3
C6
86
A6
4
CC
3D
8A
2
CA 2
2 9A 3 2 AA 4
2 DA 3 2 EA 4
2
2
BA
4
3
FA
4
3
7
1
A +M- A
B ... M- B
36
4
1 A - MoP. SP - 1 - SP
PSH8
37
4
1
PULA
32
3
1 SP+ l-SP,Msp- A
33
3
1 SP + 1 ...... SP, Msp - B
ROLA
49
1
1
ROLB
59
1
1
RORA
46
1
1
RORB
56
1
1
ROL
ROR
69
66
6
6
2 79
2
76
6
6
3
3
Note) Condition Code Register will be
explained in Note of Table 3-2-4.
$
B - Mop. SP - 1 - SP
.
.,
~}?IIIIII
4
3
H
I
N Z
V
C
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
:
I
I
I
I
I
I
I
I
I
I
I
I
R
I
I
R
I
I
R
··
·
"·
S R R
R
S R R
R
S R R
I
I
I
I
I
I
I
I
I
I
I
I
I
I
R S
I
I
R S
I
I
R
I
I
(i)'2)
··
· ··
··
·· ··
·· ··
·· ··
··· ···
·· ··
·· ··
·· ··
··· ···
··· ···
·· ··
2
1 0
R
I
S
I
I
(T) '2)
I
I
(I)
I
I
1,2)
I @
·.
I
I
(~
I
I
@ •
I
I
(,,~,
I
I
R
I
I
R
I
I
® •
@ •
··
·· ··
··· ··· ···
·· ·· · · · ·
·· ·· · · · ··
·· ·· ·· ·· ·· ··
·· ·· · · · ·
·· ··
·· ··
··
I
I
I
I
@ •
I
I
R
I
I
R
I
I
R
I
I
R
I
I
R
I
I
@
I
I
I
(~
I
I
I
@ I
I
I
I
I
@ I
(8) I
I
I
'0, I
@
A x 8 .... A :B
PSHA
PULB
Rotate Right
M-l -M
3
4
LDAB
Rotate Le't
Converts btnary add of BCD
characters into BCD format
4
LDD
Pull Data
1 00 - A - A
1 oo-B-B
E8
Load Oouble
Accumulator
Push Data
6
oo-M-M
3
A8
2 B6
2 F6
Load
Accumulator
6
5
1,:1
bO
:l?,' 1 I I I 1 If)
bO
(to be continued)
HITACHI
171
Table 3-2-1
Accumulator, Memory Manipulation Instructions
I
Mnemonic
IMME-Olol-RECT
Double Shift
~thmetic
48
1
1
A
[)--!1111111t-o
ASL8
sa
1 1
B
C
ASLo
05
1 1 ~
-
#
Arithmetic
Double Shift
Right Logical
#
68
6
2
78
6
3
6
2
77
6
Mj
3
_
:1
b1
bO
1
57
1 1
LSRA
44
1
LSRB
54
1 1
.
LSRo
04
1 1
0--0{
-
----~
-
6
2
74
6
3
1
B
b7
~
.,
97
3
2
A7
4
2
B7
4
3
A_ M
07
3
2
E7
4
2
F7
4
3
------Ace a
Ace AI
AO
DO 4
2
ED
5
2
Fo
5
3
2
2
90
3
2
AO
4
2
BO
4
3
A -M_A
SU88
CO
2
2
DO
3
2
EO
4
2
FO
4
3
Double Subtract
SU80
83
3 3
93
4
2
A3
5
2
B3
5
3
8 -M-8
A:8-M : M
Subtract
SBA
Accumulators
Subtract
With Carrv
STo
10
1 1
87
SBCA
82
2
2
92
3
2
A2
4
2
82
4
3
A-M-C-A
rsscB
C2
2
2
02
3
2
E2
4
2
F2
4
3
B-M-C-B
TAB
16
T8A
17
Test Zero or
TST
Minus
TSTA
40
1
1
TSTB
50
1
1 B - 00
60
---
And Immediate
AIM
OR Immediate
OIM
EOR Immediate
ElM
Test Immediate
TIM
3 61
3 62
75 6 3 65
78 4 3 68
4
71
6
7
72
6
7
7
5
2
70
4
1 1 A-B
1 1 B_A
M -00
3
A -00
3
3
M·IMM-M
3
3
M+'IMM-·M
M+IMM-M
M·IMM
~
80
+ 1- A: 8
A- 8- A
Accumulators
funsfer
f..9
:j0-oi.,I IIIIIIJ~
80
Accumulator
Subtract
BO
bO
SU8A
Store Double
B l-O
AO 87
B-M
A_M
B _ M+ 1
STAB
Ace
ACe AI
CCII® I
47
ASR8
64
1
5
H
ASRA
STAA
Accumulator
-
A7
-~-~
Store
OP
67
LSR
Shift Right
Logical
#
Arithmetic Operation
ASLA
OP
-
IMPLIED
#
#
ASR
Shift Right
EXTEND
INDEX
-
-
OP
Booleanl
OP
OP
ASL
Shift Left
Arithmetic
Condition Code
Register
Addressing Modes
I
Operations
4
3
2
1 0
I N Z V C
··• ··•
•·
·· ·•
·· ·•
·· ···
·
·· ··
•·
•
··• ·•
·· ··
·· ··
·· ··
·· ··
••
••
••
••
I
I
I
I @I
I @I
I
I
I
I 6 I
I 6 I
~
I
I I 6 I
I 6 I
I 6 I
I @I
I @I
I
R
R
R
R I @I
R
•
•
I
I
I
I
R
I
I
R
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I I I
I R
I
·
I
I
I
I
I
I I R
··
I
I
I
I
I
I
R R
R R
R R
:
:
:
:
:
:
:
:
R
R
R
R
•
•
•
•
Note) Condition Code Register will be
explained in Note of Table 3-2-4.
Additional Instructions
In addition to the HD6801 Instruction Set, the HD630lVl
has the following new instructions:
AIM
(M) • (IMM)
(M)
->-
Executes "AND" operation to the immediate data and
the memory contents and stores the result in the
memory.
aIM --- (M) + (IMM)
->-
(M)
Executes "OR" operation to the immediate data and
the memory contents and stores the result in the
memory_
ElM --- (M) Ef) (IMM)
-+
(M)
Executes "EaR" operation to the immediate data and
the memory contents and stores the result in the
memory.
~HITACHI
172
TIM --- (M) • (IMM)
Executes "AND" operation to the immediate data and
the memory contents and changes the flag of
associated condition code register.
Each instruction has three bytes; the first. is op-code, the
second is immediate data, the third is address
modifier.
XGDX
(ACCD) ...... (IX)
Exchanges the contents of accumulator and the
index register.
SLP --- The MCU goes to the sleep mode.
Refer to "Low
Power Dissipation Mode" for more details of the
sleep mode.
Table 3-2-2
Index Register, Stack Manipulation Instructions
Condition Code
Register
Addressing Modes
POinter Operations
MnemoniC
Booleanl
IMMED.
OP
1---------Pull Data
PULX
Exchange
XGDX
-
#
DIRECT
OP -
#
INDEX
OP -
#
EXTEND
IMPLIED
OP
OP
-
#
18
-
Arithmetic Operation
#
1
ACCD··IX
5
4
J
1 0
H
I
N Z
V
C
••••••
Note) Condition Code Register will be
explained in Note of Table 3-2-4.
~HITACHI
173
Table 3-2-3 Jump, Branch Instruction
MnemonIC
Operations
BRN--t-2'-1--t-322W_.l__
. ii',
B hN
Branc,", Alwavs
BRA
20
3
rane
ever
.._- ~Branch If Carrv Clear
BCe
24
Branch If Carry Set
BCS
25
BBGHT,
2 2f3.-L1:2
BlE
2F
3
J
2
Branch If > Zero
Branch If Higher
Branch If..;; Zero
E
3
I
t-- N -
!
i
•
•
.~_
.-.
• .'.
l i e " ,0
-~-
1--:c::-:-~:-:-"'::-':-z:Cz:':'rr°":o--t---::C:~-'~:--+I":~C.~-+I-~:-+!~
i:~t. .
;"1 ••
one .-----+-+-.- t--+
t ~-
None·
--:-
C" 1
•
•
•
.-+A f-;-
•
-t- __+-+-+_1-+-+_1-__·1-j- _- _I-j-":.::~=~:+=1V==.=o========~~=~=t=:~:=:~:=:~t-f;--1
Z+- (N 0 VI '" 0
• • I- i· :. •
C +- Z " 0
• • I . • i. •
2+--+-f---+--t--1-f--+ -t-I-++-+-=Z-:+-":'N-:G,)i+C'CCVC"I-_""'I--+.+.-+'-.+0-1,1-.+0--1
Branch If low--er-:o:Cr-+-~L~ 2-;tj3-i"1'-2+--1.-- -
~e.,-c:--::-_-jI---_'C"':=--·I-=+c:-t·L-::-i-t-.
Branch If < Zero
elT
2D
12
•• I. ,.-t-:i.
++ L+_
C+Z 1
-I-- -. -- t---t--.
=
-
N
3
v'" 1
•
•
I. .'.
1-1-=-_~_~_;.~: . :_:_:_:_~_~n_;-~_E': '$Q~U~a_,~ ~ ~:_-:=:=__~-j-~_:~:~_~:';_2~_t:i=_-~ j-i:=_-I:=_'-:~I- ~ :~=_t:=_-I:=_-~:;_-~: ~: ~ ~:~ :~=~:~ O~_:-~:~_o-I~=~ =~ =~ =~ =~ =~:i"~ ~:~f'I-:~ ,~t:-:
Branch If Overflow
Clear
BVC
28
Branch If Overflow Set
BVS
29
BPl
2A 3 2
1--'------:----1--
~~f:~~~routine
t--.,-Jum--p---- ___,_ _ _
r---;-~mp To Subroutine
V• 0
-
+--cB~S~R.-_+8-~_I_~~_JMP
I
JSR
i
90
5
-
_+_ __
- "'SE ~'2' 7'E- 3-'
~- AD
•
N· 0
'
I•
+-
0
~t-;~;.-
.~ .:° 1;. °1·- •
_~ __ ~_ I- i - ~_
1
0
-2-~D
5
~.
j. • , •
_ __ __ V '" ' _ _ _ _ _ _ro+0-r0'-j-04.:c0-t-'._
•
•
_
r;-r;- I
!
- - I- • L~L_
..
.
,
..
.
"1-- ----
5 1
3F 12 1
3E 9 1
lA 4 1
;" S
,,-
SlP
Sleep
~~=-·ttr
~t.-0.-~~
_ 39
o
® ~l.t;l;0
•
e I_ •
Note) *WAI puts R/W high; Address Bus goes to FFFF; Data Bus goes
to the three state level.Condition Register will be explained
in Note of Table 3-2-4.
Table 3-2-4
Condition Code Register Manipulation Instructions
!Addressing Modes
Operations
Mnemonic
ClC
Cli
ClV
SEC
SEI
SEV
TAP
TPA
Clear Carry
Clear Interrupt Mask
Clear Overflow
Set Cerry
Set Interrupt Mask
Set Overflow
Accumulator A -
eeR -
eeR
Accumulator A
IMPLIED
OP OC 1 1
OE 1 1
OA 1 1
00 1 1
OF 1 1
OB 1 1
OS 1 1
07 1 1
Condition Code Register
Boolean Operation
#
O-C
0-1
O-V
1- C
1-1
I-V
A- CCR
CCR- A
5
4
HI
R
3 2 1 0
VC
° R
R
1-t-s
S
N
Z
· · ·· · · ·
· ·· ··· ··· ·· ··
···· ·
···
0
°
0
5
0
~-@--
• I • I·
[NOTE] Condition Code Register Notes: (Bit set if test is true and cleared otherwise)
CD
@
@
@
@
(Bit
(Bit
(Bit
(Bit
(Bit
V)
C)
C)
V)
V)
Test:
Test:
Test:
Test:
Test:
Result = 10000000?
Result'" OOOOOOOO?
BCD Character of high-order byte greater than 10? (Not cleared if previously sed
Operand = 10000000 prior to execution?
Operand = 01111111 prior to execution?
®
(Bit V)
Test: Set equal to N@C=1 after the execution of instructions
(])
(Bit N)
(All)
(Bit I)
Test: Result less than zero? (Bit 15=1)
Load Condition Code Register from Stack,
@
tID
(All Bit)
(Bit C)
Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exist the wait
state.
Set according to the contents of Accumulator A.
Result of Multiplication Bit 7=1? (ACeB)
~HITACHI
174
Table 3-2-5
OP
ACC
CODE
A
~
LO
INO
OO~I
0010
0011
0100 I 0101
0110
0
I
2
-----
6
ODOO
0
~
SB!I
BRA
0001
1
NOP
CBA
BRN
INS
/
BHI
PULA
0011
3
/
/
~
BLS
PULB
DIDO
4
LSRD
/
BCC
DES
0101
5
ASLD
~'BCS
TXS
0110
6
TAP
TAB
BNE
PSHA
01 !1
7
TPA
TBA
BEQ
PSHB
1000
B
INX
XGDX BVC
PULX
1001
9
DEX
DAA
BVS
RTS
1010
A
CLV
SLP
BPL
ABX
1011
B
SEV
ABA
BMI
RTI
1100
C
CLC
BGE
PSHX
1101
0
SEC
1110
E
CLI
1111
F
SEI
0
/
/
--------1
BLT
MUL
BGT
WAI
BLE
SWI
2
3
5
4
~
IMM
0111
1000
7
B
DIR
0000
3
TSX
0010' 2
1 A~C
OP-Code Map
AIM
DIM
COM
- - ----
ROR
2
3
AD DO
AND
4
BIT
5
6
~'I
STA
STA
7
EOR
ASL
-
L
TIM
CPX
_B':;~_ I
TST
LOS
STS
------------I
6
1
9
9 RA
A
ADD
B
7
B
J
9
j
At
I
-----·--LDo------c
- -STD
- - - - -. ._-
L1
JSR
JMP
B
ADC
. -------------
INC
1
I
SBC
LOA
/'
ASR
DEC
5
F
0
I
ElM
CLR
:
1111
CMP
SUBD
-
LSR
~i/I
4
EXT
SUB
NEG
ROL
---
ACCB or X
ACCA or SP
1 OIR 1-iNO~XT 'IMM ToiRTiNO 1
1 1001 ! 1010 1011 1100 1 1101 1 1110 L
A
C 1 o 1 E !
! 9
i B
---------
LOX
""'------1
STX
C
E
B
1 o .1
0_.
E
F
.1
F
UNDEFINED OP CODE c;;::::::J
• Only each instructions of AIM, OIM, ElM, TIM
3.3
Instruction Execution Cycles
In the HMCS6800 series, the executLon cycle of each
instruction is counted from the start of the op-code
fetch.
The HD630lVl employs a mechanism of the pipeline control for
the instruction fetch and the subsequent instruction fetch
is performed during the current instruction being executed.
Therefore, the method to count instruction cycles used in
the HMCS6800 series cannot be applied to the instruction
cycles such as MULT, PULL, DAA and XGDX in
th~
HD630lVl.
Table_3-3-l, provides the information about the relationship
among each data on the Address Bus, Data Bus,and R/W
status in cycle by cycle basis during the execution of each
instruction.
$HHTACHB
175
Table 3-3-1
Address Mode
Cycles
&
Instructions
Cycle
#
Cycle by Cycle Operation
Address Bus
-
Data Bus
R!W
IMPLIED
ADC
AND
CMP
LDA
SBC
ADD
BIT
EOR
ORA
SUB
2
ADDD
LDD
LDX
CPX
LDS
SUBD
3
1
2
1
2
3
Op Code Address + 1
Op Code Address + 2
1
1
Operand Data
Next Op Code
Op Code Address + 1
Op Code Address + 2
Op Code Address + 3
1
1
1
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Op Code Address + 1
Address of Operand
Op Code Addresf; + 2
1
1
1
Address of Operand (LSB)
Operand Data
Next Op Code
Op Code Address + 1
Destination Address
Op Code Address + 2
1
0
1
Destination Address
Accumulator Data
Next Op Code
Op Code
Address
Address
Op Code
1
1
1
1
Address
Operand
Operand
Next Op
Op Code Address + 1
Destination Address
Destination Address + 1
Op Code Address + 2
1
0
0
1
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Jump Address
1
1
0
0
1
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Op Code
Op Code
Address
Op Code
Address + 1
Address + 2
of Operand
Address + 3
1
1
1
1
Immediate Data
Address of Operand (LSB)
Operand Data
Next Op Code
Op Code
Op Code
Address
FFFF
Address
Op Code
Address + 1
Address + 2
of Operand
1
1
1
1
0
1
Immediate Data
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
(to be cont1nued)
DIRECT
ADC
AND
CMP
LDA
SBC
ADD
BIT
EOR
ORA
SUB
1
3
STA
1
3
ADDD CPX
LDD
LDS
LDX
SUBD
STD
STX
2
3
2
3
1
4
STS
2
3
4
1
4
JSR
2
3
4
1
5
2
3
4
5
TIM
1
4
AIM
OIM
ElM
2
3
4
1
6
2
3
4
5
6
Address + 1
of Operand
of Operand + 1
Address + 2
of Operand
Address + 3
~HITACHI
176
of Operand (LSB)
Data (MSB)
Data (LSB)
Code
Address Mode
Cycles
&
Instructions
Cycle
#
Address Bus
Data Bus
R/W
INDEXED
JMP
1
3
2
3
ADC
AND
CMP
LOA
SBC
TST"
ADD
BIT
EOR
ORA
SUB
1
2
4
STA
3
4
1
2
4
ADDD
CPX
LOS
SUBD
STD
STX
3
4
1
LDD
LOX
2
5
STS
3
4
5
1
2
5
JSR
3
4
5
1
2
5
ASL
COM
INC
NEG
ROR
ASR
DEC
LSR
ROL
3
4
5
1
2
6
3
4
5
6
TIM
1
2
5
CLR
3
4
5
1
2
5
AIM
aIM
ElM
3
4
5
1
2
7
3
4
5
6
7
Op Code Address + 1
FFFF
Jump Address
1
1
1
Offset
Restart Address (LSB)
First Op Code of Jump
Routine
Op Code Address + 1
FFFF
IX + Offset
Op Code Address + 2
1
1
1
1
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Op Code Address + 1
FFFF
IX + Offset
Op Code Address + 2
1
1
0
1-
Offset
Restart Address (LSB)
Accumulator Data
Next Op Code
1
1
1
1
1
Offset
Restart
Operand
Operand
Next Op
Op Code Address + 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address + 2
1
1
0
0
1
Offset
Restart Address (LSB)
.Register Data (MSB)
Register Data (LSB)
Next Op Code
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
IX + Offset
1
1
0
0
1
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Op Code Address + 1
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address + 2
1
1
1
1
0
1
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Op Code Address + 1
Op Code Address + 2
FFFF
IX + Offset
Op Code Address + 3
1
1
1
1
1
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Op Code Address + 1
FFFF
IX + Offset
IX + Offset
Op Code Address + 2
1
1
1
0
1
Offset
Restart Address (LSB)
Operand Data
Op Code Address + 1
Op Code Address + 2
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address + 3
1
1
1
1
1
0
1
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
next Op Code
(to be cont1nued)
Op Cede Address + 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address + 2
..
~
I
Address (LSB)
Data (MSB)
Data (LSB)
Code
00
Next Op Code
~HITACHI
177
Address Mode
&
Cycles
Instructions
Cycle
#
-
Address Bus
R/W
Data Bus
EXTEND
3
1
2
3
Op Code Address + 1
Op Code Address + 2
Jump Address
1
1
1
Jump Address (MSB)
Jump Address (LSB)
Next Op Code
4
1
2
3
4
Op Code
Op Code
Address
Op Code
Address + 1
Address + 2
of Operand
Address + 3
1
1
1
1
Address
Address
Operand
Next OP
4
1
2
3
4
Op Code Address + 1
OP ·Code Address + 2
Destination Address
Op Code Address + 3
1
1
1
Destination Address (MSB)
Destination Address (LSB)
Accumulator Data
Next Op Code
5
1
2
3
4
5
Op Code
Op Code
Address
Address
Op Code
1
1
1
1
1
Address
Address
Operand
Operand
Next Op
Op Code Address + 1
Op Code Address + 2
Destination Address
Destination Address + 1
Op Code Address + 3
1
1
5
1
2
3
4
5
Destination Address (MSB)
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next OP Code
1
2
3
4
5
6
Op Code Address + 1
Op Code Address + 2
FFFF
Stack Pointer
Stack Pointer - 1
Jump Address
1
1
1
1
2
3
4
5
6
Op Code
Op Code
Address
FFFF
Address
Op Code
Address + 1
Address + 2
of Operand
1
1
1
1
1
2
3
4
5
Op Code
Op Code
Address
Address
Op Code
Address + 1
Address + 2
of Operand
of Operand
Address + 3
JMP
ADC
AND
CMP
LDA
SBC
ADD TST
BIT
EOR
ORA
SUB
STA
ADDD
CPX
LDS
SUBD
STD
STX
LDD
LDX
STS
JSR
6
ASL
COM
INC
NGE
ROR
ASR
DEC
LSR
ROL
6
CLR
5
Address + 1
Address + 2
of Operand
of Operand + 1
Address + 3
of Operand
Address + 3
0
0
0
1
0
0
1
of Operand (MSB)
of Operand (LSB)
Data
Code
of Operand (MSB)
of Operand (LSB)
Data (MSB)
Data (LSB)
Code
Jump Address (MSB)
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
1
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
1
1
1
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
0
0
00
1
Next Op Code
(to be continued)
~HITACHI
178
Address Mode
Cycles
&
Instructions
Cycle
#
-
Address Bus
R/W
Op Code Address + 1
1
Data Bus
IMPLIED
ABA
ASL
ASR
CLC
CLR
COM
DES
INC
INX
LSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
ABX
ASLD
CBA
CLI
r.LV
DEC
DEX
INS
LSR
ROL
NOP
SEC
SEV
TAP
TPA
TSX
DAA
XGDX
PULA
PULB
PSHA
1
Next Op Code
I
1
2
1
2
Op Code Address + 1
FF'FF
1
1
Next Op Code
Restart Address (LSB)
3
1
2
3
00 Code Address + 1
FFFF
Stack Pointer + 1
1
1
1
Next Op Code
Restart Address (LSB)
Data from Stack
4
1
2
3
4
Op Code Address + 1
FFFF
Stack Pointer
Op Code Address + 1
1
1
1
Next Op Code
Restart Address (LSB)
Accumulator Data
Next Op Code
1
2
3
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
1
1
1
1
Next 00 Code
Restart Address (LSB)
Data from Stack (MSB)
Data from Stack (LSB)
1
1
4
5
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Op Code Address + 1
Next Op Code
Restart Address (LSB)
Index Register (LSB)
Index Register (MSB)
Next Op Code
5
1
2
3
4
5
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Return Address
1
1
1
1
1
Next Op Code
Restart Address (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of
Return Routine
7
1
2
3
4
5
6
7
Op Code Address + 1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
1
1
1
1
1
1
1
Next Op
Restart
Restart
Restart
Restart
Restart
Restart
PSHB
PULX
4
4
PSHX
5
RTS
MUL
1
2
3
0
0
0
1
Code
Address
Address
Address
Address
Address
Address
(LSB)
(LSB)
(LSB)
(LSB)
(LSB)
(LSB)
(to be continued)
~HITACHI
179
Address Node
&
Cycles
Instructions
Cycle
#
-
Address Bus
R/W
Data Bus
IMPLIED
WAI
9
1
2
3
4
5
6
7
8
9
RTI
10
1
2
3
4
0
0
0
10
1
1
0
0
0
0
0
0
0
1
11
Vector Address FFFB
1
12
Address of SWI Routine
1
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine
(MSB)
Address of SWI Routine
(LSB)
First Op Code of SWI
Routine
Op Code Address + 1
FFFF
FFFF
1
1
10
1
2
3
4
5
6
7
8
9
4
+ 1
0
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (HSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Vector Address FFFA
9
SLP
Op.Code Address
FFFF
Stack Pointer +
Stack Pointer +
Stack Pointer +
Stack Pointer +
Stack Pointer +
Stack Pointer +
Stack Pointer +
Return Address
1
2
3
4
5
6
1
1
0
0
0
Next Op Code
Restart Address (LSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index Register (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of
Return Routine
6
7
8
12
+ 1
1
1
1
1
1
1
1
1
1
1
5
SWI
Op Code Address
FFFF
Stack Pointer
Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack Pointer -
1
2
i
1
1
2
3
4
5
6
7
Sleep
3
4
FFFF
Op Code Address + 1
Next Op Code
Restart Address (LSB)
High Impedance - Non
MPX Mode
Address Bus - MPX Mode
!
Restart Address (LSB)
Next Op Code
(to be continued)
~HITACHI
180
Address Mode
Cycles
&
Instructions
Cycle
-
Address Bus
R/W
Op Code Address + 1
FFFF
1
1
1
Branch Offset
Restart Address (LSB)
First Op Code of Branch
Routine
Next Op Code
1
1
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Op Code of
Subroutine
#
Data Bus
RELATIVE
BCC
BEQ
BGT
BLE
BLT
BNE
BRA
BVC
BCS
BGE
BHI
BLS
BMT
BPL
BRN
BVS
3
1
2
3
Addreaa
Test = "1"
Op Code Address
Test =
BSR
1
2
5
3
4
5
3.4
rranCh
110 11
Op Code Address + 1
FFFF
Stack Pointer
S~ack Pointer - 1
Branch Address
0
0
1
I
System Flowchart
A system flow of the HD6301Vl is given in Fig. 3-4-1.
~HRTACHI
181
VECTORIN
A
FFFE·FFFF
PCL~
MSP
~MSP·1
PCH
IXL
~
MSP·2
IXH
-~
MSP-3
ACCA ·.MSP-4
AceB
CCR
Fig. 3-4-1
HD6301Vl System Flowchart
~HITACHI
182
-+
MSP·5
~MSP-6
4.1.1
PIN ARRANGEMENT AND PACKAGE INFORMATION
• HD6301V1P, HD63A01V1P
HD63B01 V1 P (DP-40)
• HD6301V1FG, HD63A01V1F
HD63B01 V1 FG (FP-54)
se,
se.
p ..
P"
P"
P"
P ..
I
p ...
PH
P"
Po>
P..
POI
POI
p ..
P ..
P ..
PI'
~
__________
~~
P"
Vee
• HD6301V1CG, HD63A01V1CG
HD63B01V1CG (CG-40)
•
f f ~ ~ t f l ~ f ~
t~J l;J L8J :"~J ~C:;J ~~ t~ t~J t~l L~l
P31
~
P30
37]
[~s
~~
P4!>
SC2
3~J
(2)
P4a
SC, 3!J
[2~
[~1
~~
Vee
E
{oJ
Vss
1]
P44
[Ij
PHI
PH
r1'7
PI4
[.01 [;'1 r~l f0.1 r~1 r:=1 r~l r~l f;!1
r~1
mEcE~~ffa:i.~
P"
P"
p..
P"
p..
NC
P"
p"
P"
NC
PI7
~=8
IRa, ~J
P"
p ..
NC
P" I
~J
~]
NMI
NC
P"
P.7
XTAL ~]
EXTAL
HD6301V1CP, HD63A01V1CP
HD63B01V1CP (CP-52)
~~ P". HD6301V1 L, HD63A01V1 L
,P.,.
p"
NC
p ..
NC
'1""!9"I;I"!!rE!I'1!!I"'I;;rB!JlI!"1IrE""'.,....-J
HD63B01 V1 L (CP-44)
~ f l.l J. i. ~ ~ l 2 l f !if
loe~o~gJ -~fillOi
!!;Iz w:!:.x > w ~
rtJ Do Do
l
P32
l
POl
l
P34
(NO)
l
l
P35
P36
l P37
l
(NC)
31
P40
1
P41
P42
1T0pView)
Fig. 4-1-1
Pin Arrangement (Tbp View)
~HITACHI
183
4.1.2
•
PIN ARRANGEMENT AND PACKAGE INFORMATION
•
HD6303RP, HD63A03Rp,
HD63B03RP (DP-40)
0
HD6303RF, HD63A03RF,
HD63B03RF (FP-54)
•
..s
~:gJ L;J L8l :"~J ~;:;~ ~~.! t~~ t~J ~~J L~J
Rm
OoIAo
HD6303RCG, HD63A03RCG
HD63B03RCG (CG-40)
w«CI:OOV
'RES
STi'iY
D,/A,
4 DJ/AJ
D4/A.
1
P21
4
p"
P"
p,.
9
AtD
Fig. 4-1-2
D./A.
D./A.
D7/A7
As
AD/PtD
A,/P"
A,/P12
Pin Arrangement (Top View)
~HITACHI
184
Vc
Vss
0,111.,
",
[2~ AI
t2_2 A,
AJj
PACKAGE
Un.lt·. mm (i nch)
DIMENSIONS
DP-40
52.8(2.079)
54.0mox. (2. I 26mox.)
• CG·40
12.19±0.3
(0.480±0.012)
D
~ ~
~O
+I ~
~~
•
0:5:0X
(0.030mox.)
j
,- -=n=n;::nn;:;n;:;;:n~ll
Ilnnnn
_ ~~ ~ ~
26
. a
-.9
NO
.......
1.0~~==~~~--:-~~~~~II~nff~ormation
----------- 0.(
Fig. 4- 2 Package
(to be continued)
~HITACHI
185
Unit: mm(inch)
~CP-44
17S3±D 12(0 690±O 005)
40
I'••
~r;t,~~~~~~39 Y-7'f'_-~
~
0
I...
o
9"
-~§~I8~~~~H~~~~~~
1"4~
.
~
~~
1651(0653)
.~
j
I
1
'J L 1.27 O.DSO
IS.50±O.50(O.610±O.020l
.CP-52
2001±O 12
(0.790 ± Q.OOS)
"
'"
0
!
~
~
a
"
"
33
21
1912
10.153)
:;:!I
......
::~
j
lflAm
i
.;; II
...11f,;...
J LLlli!ill!!lI
18.04+0.5
(O.7IUtC.OlD)
~
::l!!
a
Fig. 4-2 Package Information
5.
ELECTRICAL CHARACTERISTICS
•.ABSOLUTE MAXIMUM RATINGS
Item
Symbol
V
V in
-0.3 -
V
Operating Temperature
T opr
(NOTE)
Tstg
Vee+0.3
0 - +70
-55 -+150
°c
°c
This product has protection circuits in input pin from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection
circuits. To assure the normal operation, we recommend Vin, V out : Vss :a; (V in or Voutl ;;;; Vee.
~HITACHI
186
Unit
Vee
Input Voltage
Storage Temperature
Value
-0.3 -+7.0
Supply Voltage
•
ELECTRICAL CHARACTERISTICS (HD6301V1 and HD6303R)
• DC CHARACTERISTICS (Vee = 5.0V ± 10%, f = 0.1 - 2.0 MHz, Vss = OV, Ta = 0 - +70°C, unless otherwise noted.)
Item
Symbol
Test Condition
Input "High" Voltage
EXTAL
typ
min
RES, STBY
V IH
Vee-0•5
-
Vee xO.7
-
2.0
-
Other Inputs
max
Unit
Vee
+0.3
V
Input "Low" Voltage
All Inputs
V IL
-0.3
-
O.B
V
Input Leakage Current
NMI, IRQ!, RES, STBY
II in I
V in = 0.5-V ee -0.5
-
-
1.0
p.A
Three State (off-state)
Leakage Current
PIO -P I1 , P20 -P 24 ,
P30 -P 37 , P40 -P47 , IS3
II T51 1
V in = 0.5-V ee -0.5
-
-
1.0
Output "High" Voltage
All Outputs
V OH
Output "Low" Voltage
All Outputs
VOL
10L = 1.6mA
-
Input Capacitance
All Inputs
Cin
Vin=OV,.f= 1.0MHz,
Ta = 25°C
Standby Current
Non Operation
lee
p.A
2.4
-
-
V
Vee- 0.7
-
V
0.55
V
-
-
12.5
pF
-
2.0
15.0
pA.
Operating (f=lMHz**)
-
6.0
10.0
Sleeping (f = 1MHz' ')
-
1.0
2.0
2.0
-
-
10H = -200p.A
10H = -10p.A
V IL (STBY)=0-0.6V
V IH (RES) =Vee-05Vee V
V IL (RES) =0-0.6V
Current Dissipation"
lee
RAM Stand-By Voltage
V RAM
rnA
V
V IH min = Vee -1.0V, VI L max = O.BV A 11 output pins have no load.
Current Dissipation of the operating or sleeping condition is proportional to the
operating frequency. So the typo or max. values about Current Dissipations at X
MHz operation are decided according to the following formulas.
typo valua (f = X MHz) = typo value (f = 1MHz) xX
max. value (f = X MHz) = max. value (f =1MHz) xX
(both the sleeping and operating)
PERIPHERAL PORT TIMING
Item
Symbol
Test
Condition
HD6301V11
HD63A01Vll ,
HD63B01VlI
H063B03R
HD6303R
HD63A03R
Unit
min typ max min typ max min typ max
Peripheral Data.
Set-up Time
Port 1, 2, 3, 4
tp05U
Fig.
5-3
200
-
-
Peripheral Data
Hold Time
Port 1, 2, 3, 4
tpOH
Fig.
5-3
200
-
-
Delay Time, Enable Positive
Transition to 0S3 Negative
Transition
t0501
Fig.
5-5
-
-
Delay Time, Enable Positive
Transition to
Positive
Transition
t0502
Fig.
5-5
4 tpWO
m
Delay Time, Enable Nega-I Port 1
tive Transition to Peri2· 3
pheral Data Valid
' ,
Input Data Setup Time
• Except P21
I
I
-
200
-
-
ns
200
-
-
200
-
-
ns
300
-
-
300
-
-
300
ns
- -
300
- -
300
-
-
300
ns
Fig.
5-4
- -
300
-
-
300
-
-
300
ns
-
200
-
-
200
-
-
ns
tpWI5
F~26
200
Port 3
tlH
F.t26
150
Port 3
tl5
F~~~
0
Input Strobe Pulse Width
Input Data Hold Time
-
-
-
200
150
0
- -
150
0
ns
ns
~HITACHI
187
a
• AC CHARACTERISTICS (\t:C = 5.0V ± 10%, f = 0.1 - 2.0 MHz, Vss .OV, Ta = 0 - +70·C, unless otherwise noted.)
BUS TIMING
Item
Symbol
Cycle Time
teye
Address Strobe Pulse Width
"High"
PW ASH
Address Strobe Rise Time
tAS,
Address Strobe Fall Time
tASf
Address Strobe Delay Time
Enable Rise Time
tASD
tE,
Enable Fall Time
tEf
Enable Pulse Width "High" Level
PWEH
Enable Pulse Width "Low" Level
PWEL
Address Strobe to Enable Delay
Time
t ASED
Address Delay Time
Address Delay Time for Latch
Data Set-up Time
Data Hold Time
Write
Read
tAD1
tAD2
tADL
t Dsw
tHR
Write
tHW
Address Hold Time for latch
Address Hold Time
typ
220
typ
max min
-
1
-
60 - 40
- - 20 - - 20 450 - 300
450 - 300
60 - 40
- - 260 - - 250 - - 250 230 - 150
80 - 60
0 - 0
20 - 20
60 - 40
20 - 20
20 - 20
200 - 110
- - 650 - .,.. 650 -
Fig.
5-1,
Fig.
5-2
tASL
tAHL
tAH
Ao - A, Set·up Time Before E
tASM
Non-Multiplexed
(tACCN)
Peripheral Read Bus
Access Time
Multiplexed Bus (tACCM)
Fig_
Oscillator, stabilization Time
tRC
2-7-1,
Processor Control Set-up Time
~:i:l
tpcs
20
20
-
-
20
200
- 10
110
- 20 - 20
20 - 20
- 20 - 20 - 20
20 - 20
- 220 - - 220 - - 20 - 190 - 160
190 - 160
190 - 160
- 100 - - 50 - - 0 - - 20 - - 20 - - 20 - - 20 - - 60 - 395 - 270
395 - 270
20 - 200 - -
-
-
20
200
max
10 0.5
-
150
HD63B03R
max min typ
-
10 0.666
- - -
tDSR
Read
Address Set·up Time for Latch
min
-. HD63B01Vll
HD63A01V1I
HD63A03R
HD6301Vll
HD6303R
Test
Con·
dition
Unit
III
ns
ns
ns
ns
ns
ns
ns
n.
ns
ns
ns
ns
ns
n.
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
TIMER, SCI TIMING
Item
Timer Input Pulse Width
Test
Symbol Condition
tPWT
Delay Time, Enable Positive
Transition to Timer Out
SCI Input Clock Cycle
t Scye
SCI Input Clock Pulse Width
tpwSCK
tTOD
Fig.
5-7
HD6301Vl1
HD6303R
HD63A01Vll
HD63A03R
HD63B01Vll
HD63B03R
min
typ
max min
typ
max min
typ
max
2.0
-
-
2.0
-
-
2.0
-
-
teye
400
-
-
400
-
-
400
ns
-
2.0
- -
teye
0.6
0.4
-
tScye
2.0
0.4
-
2.0
0.6
0.4
,
0.6
Unit
MODE PROGRAMMING
Item
RES "Low" Pulse Width
Mode Programming Set·up Time
Mode Programming Hold Time
Test
Symbol Condition
PWR;TL
Fig.
t MPS
5-8
tMPH
min typ
3
2
150
-
max min
typ
max min typ
-
-
-
3
-
-
-
2
150
~HITACHI
188
HD63B01Vll
HD63B03R
HD63A01VlI
HD63A03R
HD6301Vll
HD6303R
3
2
150
-
max
-
Unit
teve
t,;.,c
ns
-
2.4V
Address Strobe
(AS)
O.8V
II--------PWEH------__l\
Enable
tEl
'E,
'Ef
I
tA01
RM,
AI-An
(SC1 1IPort4)
MCUWrite
Do-D"Ao-A.
(Port 3)
MCU Read
0 0 -0" Ao-A,
(Port 31
~
Fig. 5-1
NotValid
Expanded Multiplexed Bus Timing
tcyc
!I----PWEH
Enable
IE)
\1-------- PWEL
Ao -A1 (Port4)
R/w (SC,)
105 (Sed
MCUWrite
00-01
2.4V
Address Valid
O.BV
------r--------+----------~~
(Port 3)
MCU Read
------1-------------------------------a1'-________-+-'1
0 0 -0 1
IPort 3)
A o -A1 (Port 1)
A. -Au (Port 4)
~
Fig. 5-2
Not Valid
Expanded Non-Multiplexed Bus Timing
~HITACHI
189
r-MCURead
PIO -
Pl7
PIG - P,..
p.O - p.,
rMCUWrite
2.0V
O.8V
Inputs
p)O -
All Data
Port Outputs
P}1
Inpuls·
)
24V
O~BV Data Valid
_ _ _ _ _....J
Note) Port 2: Except P, I
·Port 3 Non-Latched Operation
Fig. 5-4 Port Data Delay Times
(MCU Write)
Fig. 5-3 Port Data Set-up and Hold Times
(MCU Read)
.ov
Add,." - - - "
8u.
,.-+----.... ,.-+----
' .. -'n-::.=f'-,.,.__.,-_->/.......
053------....:.:.,
...::;~
Inpun
___
• Access matches Output Strobe Select (055 = 0, a read;
055 = I, a write)
Fi g. 5-6 Port 3 Latch Timing
(Single Chip Mode)
Fig. 5-5 Port 3 Output Strobe Timing
(Single Chip Mode)
'.4V
Timer
Counter
I:'~~~l'~~~:: )-----=-<1
O.SV
Data Valid
~2;;.;'O..;.V_ _
1"'=~-------r O.SV
P"
Output
Fig. 5-8 Mode Programming Timing
Fig. 5-7 Timer Output Timing
m
Vee
RL =2.2kn
Test POint
(4.0kfl for E)
152074 ,j..t,
or Equ,v
C
C
90pFforP Io -P3?P. O
30 pF for PIO - P17, P10
'"
R
Fig. 5-9
R
-
p."SC\,SC 2
P,..
40pFforE
,2 kn
Bus Timing Test Loads (TTL Load)
~HITACHI
190
6.
6.1
APPLICATIONS
Use of External Expanded Mode
The HD630lVl supports five operation modes 1, 2, 4, 5 and 6 as
external expanded modes.
the following
Usage of these modes is detailed in
parag~aphs.
(1) Non-multiplexed modes
(a) Mode 1 (New Mode)
In this mode, port 3 works as data bus, port 1 as
lower address bus
address bus
I
(Ao - A7), and port 4 as upper
(As - AlS).
Since l6-bit addresses are
sent out in parallel, the HD630lVl can access to a
65k memory space with no address latch externally
under this mode.
HD630lVl Meu
Ao"vA7 As"vAl
8
EtDo"vD7 R/W
5
8
8
ROM
RAM
PIA
GPIA
PTM
Address Address
Bus
Bus
(LSB)
(MSB)
I
I
I
I
I
Data
Bus
Fig. 6-1-1 HD6301V1, Mode 1
~HITACHI
191
In the case when a write operation is performed to
the internal memory including I/O and registers, the
same data is also written into the external memory
located by the same address if a memory exists.
In the case when a read operation is performed to the
internal memory, however, only a data of the internal
memory is read and no external data pointed by the
same address is read.
Read/write operation to the
internal/external memory with the internal memory
address range is also applied to the mode 2, 4, 5 and
6.
Under this mode, the internal mask ROM of which
location is $FOOO through $FFFF to address is no more
access able and an external memory can be accessed
with this address range.
After reset, Port 1 is a lower addiess bus (Ao A7), Port 4 is a upper address bus (Ae - A1s).
(b) Mode 5 (Equivalent to Mode 5 of HD6801V)
Port 3 works as data bus; and port 4 as address bus
(Ao - A7) or input pin by DDR.
In this mode, pin
39 provides the result of the following decoding:
This output signal may be used as a chip select or
chip enable signal permits to access an external
memory up to 256 byte locations ($0100 - $OlFF).
The pin function of Port 4 can be changed from an
address line to an input port in the case that
the system does not need all of the 8 address lines
by writing zero into the corresponding bit of Port
4 DDR.
An example of connection with PIA (HD6821, HD6321)
is shown in Fig. 6-1-2.
192
Do'VD7
8/
Ao
Al
HD630lVl Az
=:q~ddres~1
decoder
A7
"
IRQ
E
I
Do'VD7
8
PA o'V PA 7
8
RSo PBo'VPB7
RS 1
CSo HD6821
CSI HD6321
vee
CAl
CB I
CA z
~ IRQA
CBz
IRQB
lOS
R/W
CSz
I
Fig. 6-1-2
E
R/W
I
I
t
Connection of HD6301V1 with PIA
(2) Multiplex Modes (Modes 2, 4 & 6)
Any mUltiplex mode provides a time multiplexed address
and data on port 3.
Therefore, an address latch is
required externally.
AS (pin 39) signal is used for an
address latch strobe.
An example is illustrated in
Fig. 6-1-3 to show how CMOS latch is used with the HD6301V1.
It should be noted, however, that the output address from this latch
is delayed.
~HITACHI
193
HD14508B
7fr[l
P3)
P 31
P32
P33
HD6301Vl
P~
P35
p$
P37
AS
I
MR DIS
Do Qo
D1 Q1
D2 Q2
D3 Q3
Do Qo
D1 Q1
D2 Q2
D3 Q3
STASTB
Address buses
Ao to A7
~
Data buses
Do to D7
c
Fig. 6-1-3
CMOS Latch
For high-speed operation, 74LS373 or high speed CMOS
latch (74HC373) is desirable to minimize the delay time.
(a) Mode 2, 4 (Equivalent to Mode 2 of HD6801V)
In this mode, the internal mask ROM
(~FOOO
through
$FFFF) is disabled and external memory becomes valid
instead.
Port 4 works as the upper address bus.
(b) Mode 6 (Equivalent to Mode 6 of HD6801V)
In this mode, the internal mask ROM is enabled.
Port 4 works as address bus
(As
-
A1S)
input.
Since Port 4 becomes input mode after reset,
"I" must be written into DDR by program if it
is required to use the port as address buses.
~HITACHI
194
I
Address
Bus
Fig. 6-1-4
6.2
Data
Bus
HD6301V1 MCU Expanded Multiplex Mode
Standby Mode
Bringing STBY "Low", the HD6301V1 goes into the Standby
mode. In this mode, the CPU becomes reset and all
clocks of the HD6301V1 become inactive.
The contents of the internal RAM is retained as long as VCC
is supplied (VCC ~ 2V). Under Standby Mode, memory back-up
is possible with only a few \lA of leakage current. With "1"
level at STBY pin, the MCU exits from Standby Mode.
When "1" level is 'detected at STBY pin, a clock
generator begins to oscillate and the internal reset
condition is released.
At this time, RES signal should be
set at "0" level for at least OSC stabilization time (t RC )
before the CPU operation restarts. Otherwise, the normal
operation is not guaranteed.
A typical flowchart to use a Standby Mode is shown in Fig. 6-2-1.
~HITACHI
195
l.Store the contents
of registers into
RAM (if necessary)
aSet each bit in
RAM Control Status
Register to
RAME="O", STBY="l"
PWR
3. SLP executed
Restart Routine
Test and judge STBY
bit in RAM Control
Status Register
" l" : VCC was supplied.
"O":V was not
CC
supplied.
Fig. 6-2-1
Flowchart of Standby Mode Application
$
196
HITACHI
The timing relationship shown in Fig. 6-2-2 must be satisfied.
,
NMI
,,,
,
IS
~
,
,
15
1*
(\
t--k
II
RES'
RESl
I
STBY
I
:
STBYl
I
I
I
I
'
1*,
NMI:Routine
0
0
I
Register Save
RAM Control Status
Register Bits set
Restart
.----
,
,
I
I
:
I
Oscillator Stabilization Time
Fig. 6-2-2
*
,
~I:
.----.
,,
I
I
II
I
I
I
Timing Chart of Each Signal
Either RESl or STBYl can become "a" level as long as
the execution time of NMI routine is guaranteed.
Fig. 6-2-3 shows an example of a circuit to implement the timing
sequence shown in the Fig. 6-2-2.
System power line
To other device
of the system
~----------------~NMI
STBYI
Switc~
1
HD6301Vl
Rl« R2.
R . C »20ms
r
Fig. 6-2-3
r
Example of Circuit Diagram for a Standby Operation
~
~HITACHI
197
The Standby power bit in the RAM control status register
detects that VCC is supplied or not.
time is equal or less than
may not be cleared.
be more than
100~s,
100~s,
When the VCC rise
the Standby power bit
To avoid this, the VCC rise time should
for example, by using the larger
bypass capasitor.
6.3
Address Trap, OP-Code Trap Application
The H06301Vl facilitates two trap functions, the operation
code trap and the address trap, to protect the H06301Vl to
proceed an erroneous operation.
The operation code trap is
a trap when an operation code currently fetched is illegal
or undefined.
Therefore, when undefined codes listed below
are fetched, a trap is caused and the H06301Vl avoids further
erroneous operation.
The priority level of the interrupt
caused by this operation code trap is next to the RESET.
Undefined codes of the H06301Vl are: $00, $02,
~03,
$12, $13,
$14, $15, $lC, $10, $lE, $lF, $41, $42, $45, $4B, $4E, $51,
$52, $55, $5B, $5E, $87, $8F, $C7, $CO and $CF.
The address trap is a TRAP when an operation code is fetched
from the memory area shown in Table 2-3-1.
It should be
noted, however, this function works only under op-code fetch
(not for data access).
Under the support of error processing
program in trap service routine, the user can protect the
system from further erroneous operation.
If RTI instruction
is executed at the end of the trap service routine, the
program control returns to the location where the trap is
caused previously and then another trap may be caused again.
So, please take special care when a programmer uses this trap
function.
~HITACHI
198
6.4
Slow Memory Interface
Here described is the example of clock width cantrall circuit
and its timing chart, where E-clock high time is extended
to assure enough access time.
The expanded enable high pulse width (PW'EH)' which is
implemented by using the circuit shown below, is calculated
as follows:
where
I
n
t 4-
l
AS
4D
30
20
ti.r--'~ 10
R/W
E
40
30
20
10
~
CE
r - I-- Gl-GZ CK
7T
$OOOO'V$7FFF
HN6l256
CS: Active-high
CE: Active-low
HD6301Vl (Mode 6)
LS173
* The detail of this circuit is described in
Fig. 6-4-1.
Fig. 6-5-4
PW'EH
Fig; 6-5-5
HN61256 Read Timing
~HITACHI
204
In this example, PW EH of which timing is extended by using
the clock control circuit (Fig. 6-4-1) must be at least
4
~s.
The LS173 is to assure enough address set up time
(t AS ) of HN6l256.
6.6
Interface to the Realtime Clock (HD1468l8)
The HD1468l8 (realtime clock + RAM : RTC) isa CMOS micro-
I
computer peripheral LSI that incorporates the clock and
calendar functions to compute year, month, day, day of week,
and time.
When this HD1468l8 is interfaced to the HD6301Vl,
this LSI provides a real time clock information to be
displayed.
In addition to the real time clock function of the HD1468l8,
this device also be utilized as a system interval timer and
a square waves generator.
An example of the interface
between the HD146818 and the HD6301V1 is shown in Fig. 6-6-1.
It can be interfaced under the expanded multiplexed mode
(mode 4 or 6) of the HD6301Vl.
~HITACHI
205
.nr
SQWt----;
Port 4
8 I/O
Portl
.-I
~
.-I
Lines
B bits
o
CS
SC2
CV')
~
Cl
5 I/O
Port 2 :r:
SCI
Timer
E
A<
co
R/W
R/W .-i
co
\0
,
6
DAY OF WK
06
H
C\l
7
DATE OF MON
07
8
MONTH
08
9
YEAR
09
50-byte
user RAM
10
,,
631
13F
\E
13
Control register A
OA
1""1 .... _"- _ _ 1
~:
\"..vu .... .L..U..L
register B
Control register C
Control register D
~-----------------------------------------------------------
Fig. 6-6-2
HD146818 Built-in RAM Address Map
~HITACHI
206
Cl
III
s::
-r!
III
I
~
Table 6-6-1.
Address
0
HD146818 Time, Calendar, & Alarm Data Display
Data range
(Decimal)
Function
Data range (Hexadecimal)
Binary data
BCD data
mode
mode
00 to 3B
00 to 59
SECONDS
0 to 59
1
SECONDS ALARM
MINUTES
0 to 59
0 to 59
00 to 3B
2
00 to 3B
00 to 59
00 to 59
3
MINUTES ALARM
0 to 59
00 to 3B
00 to 59
4
HOURS
12-hour
mode
1 to 12
01 to OC/
81 to 8C*
01 to 12/
81 to 92*
24-hour
mode
0 to 23
00 to 17
00 to 23
12-hour
mode
1 to 12
01 to oci
81 to 8C*
01 to 12/
81 to 92*
24-hour
mode
0 to 23
00 to 17
00 to 23
1 to 7**
7
DAY OF THE WEEK
DAY OF THE MONTH
1 to 31
01 to 07
01 to lF
01 to 07
01 to 31
8
MONTH
YEAR
1 to 12
0 to 99***
01 to DC
9
00 to 63
01 to 12
00 to 99
5
6
HOURS
ALARM
-
[Notes]
*:
The most significant bit differentiates bet.ween AM
and PM.
**:
1
5
***:
That is, 0
Sunday,
=
Thursday,
2
=
AM and 1
=
PM.
= Monday, 3 = Tuesday, 4 = Wednesday,
6 = Friday, and 7 = Saturday
This takes the lower two digits of the calendar year.
The information of the calendar and the time are stored on
the built-in RAM and updated every second.
The built-in RAM
includes not only the display RAM but also 50-byte user RAM
which stores data necessary for the system.
The HD6301Vl gets the calendar and time information by reading
the built-in RAM of the HD146818.
The HD146818 generates
three different types of interrupts, update interrupt, alarm
interrupt and periodic interrupt, to the HD6301Vl. The
HD6301Vl proceedes a service for each of these interrupt
requests by a software control.
~HITACHI
207
Such a combination of the HD6301Vl and the HD1468l8 easily
implements a compact real time system with reduced power
dissipation.
Note: For details of the HD1468l8, refer to "HD1468l8 Data
Sheet" .
6.7
Reference Data of Battery Service Life
Fig. 6-7-1 shows the battery service life taken from a
silver oxide battery: SR44w (by Hitachi Maxe11).
3000
2590
----------
,
I"
'"
'"
H
;::l
~
Estimated
1'\
720
o
.r::
:
.....
,
300
,,
,,
,
,
(!)
4.;
·ri
H
(!)
.~ 100
:>
,,
,,
,,
,,
,
H
(!)
U)
,
,,
"
30
10
I
I
6070
Fig. 6-7-1
I
Battery Service Life (Maxe11 SR44w)
~HITACHI
208
I
250
600
Current (]JA)
,
,
I
6000
I
7.
7 .1
PRECAUTIONS
Write-Only Register
When a write-only register such as the DDR of the port is
read by the MPU, "$FF" always appears on the data bus.
Note that when an instruction which reads the memory
contents and does some arithmetic operation on the contents
of the write-only register, it always gets $FF as the
arithmetic and logical results.
AIM, OIM and ElM instruc-
tions are unable to apply especially for the bit manipulation of the DDR of the I/O port.
7.2
Address Strobe (AS)
The AS signal is used as an address latch strobe and is
always accompanied with the E-clock.
This means the AS is
available in both Operation and Sleep Mode whenever the
E-clock is generated.
The AS signal is disabled in Mode 5,
7 or under Standby Mode and the Pin 39 is used for other
purposes in these cases.
7.3
Mode 0
This mode is used for the test purpose only.
It is not
recommended to use this mode for the other purposes.
7.4
Trap Interrupt
When executing an RTI instruction at the end of the interrupt routine, trap interrupt different from other interrupts returns to the address where the trap interrupt was
generated.
Attention is necessary when using several trap
interrupts in the program.
See Fig. 7-4-1 and 7-4-2 for details.
~HITACHI
209
B
OPn
FFOl
FF02
Operand
FF03 Undefinition
"'"
C
OPn+l
FF04
~
Fig. 7-4-'1
Fetching an Undefined Op-code
After executing OPn instruction, the HD6301Vl fetches and
decodes an undefined op-code inside to generate a trap
interrupt.
When RTI instruction is executed in this trap
interrupt servicing routine, the HD6301Vl will set $FF03
in PC, fetch the undefined code again, generate a trap
interrupt and repeat ABC endless-loop.
FF02
BSR
FF03
01
FF04
OPn
Fig. 7-4-2
Fetching Erroneously
After performing BSR instruction, the branch destination
address is output on an address bus to fetch the first
op-code of a subroutine.
If $0001 is output as an
address by some mistake the HD6301Vl decodes it inside
and generates a trap interrupt.
When RTI instruction is
performed in this trap interrupt servicing routine, the
HD6301Vl will set $0001 in PC and start from this address,
which causes a trap interrupt again and repeat this
endless-loop.
~HITACHI
210
7.5
Power-on Reset
At power-on it is necessary to hold RES "low" to reset the
internal state of the device and to provide sufficient time
for the oscillator to stabilize.
Pay attention to the
following.
*
Just after power-on, the MPU doesn't enter reset state
until the oscillation starts.
This is because the reset
signal is input internally, with the clocked synchronization as shown below.
RES pin
~
~
1
D
D
Q
Internal reset signal
Q
Inside the LSI
Fig. 7-5-1
Reset Circuit
Thus, just after power-on the LSI state (I/O port, mode
condition etc.) is unstable until the oscillation starts.
If it is necessary to inform the LSI state to the external devices during this period, it needs to be done
by the external circuits.
7.6
Precaution to the Board Design of Oscillation Circuit
As shown in Fig. 7-6-1 there is a case that the crosstalk disturbs the normal oscillation if signal lines are
put near the oscillation circuit.
board, pay attention to this.
When designing a
Crystal and CL must be
put as near the HD6301Vl as possible.
@HITACHI
211
.. ..
.'" .'"
CL
~
~
c
c
iii iii,
:
~~i
,pel
,,
,,,
XTAL
EXTAL
H06301Vl
Do not use this kind of print board design.
Fig. 7-6-1
30-----'
Precaution to the Board
Design of Oscillation Circuit
HD6301Vl
(Top view)
Fig. 7-6-2
Example of Oscillation
Circuits in Board Design
Application Note for High Speed System Design Using the HD6301V1
7.7
This note describes the solutions of the potential problem
caused by noise generation in the system using the HD6301V1.
The CMOS ICs and LSls featured by low power consumption and
high noise immunity are generally considered to be enough
with simply designed power source and the GND line.
But this does not apply to the applications configured of
high speed system or of high speed parts.
Such high speed
system may have a chance to work incorrectly because of the
noise by the transient current generated during switching.
The noise generation owing to the over current (Sometimes it
may be several hundreds rnA for peak level.) during switching
may cause data write error.
This noise problem may be observed only at the Expanded Mode
(Mode 1, 2, 4, 5 and 6) of the HD6301V1.
The Single Chip
Mode (Mode 7j of the HD6301Vl has no such a problem.
Assuming the HD6301V1 is used as CPU in a system.
7.7.1
Noise Occurrence
If the HD6301V1 is connected to high speed RAM, a write error
~HITACHI
212
may
occu~
As shown in Fig. 7-7-1 the noise is generated in
address bus during write cycle and data is written into an
unexpected address from the HD6301Vl.
This phenomenon causes
random failures in systems whose data bus load capacitance
exceeds the specification value (90 pF max.) and/or the impedance of the GND line is high.
E
AS
\
/
/
\
Rm
/
\
(SC, 1
I
X
A. -Au
(Port 41
Do-D,
<
(Port 31
Fig. 7-7-1
\
A-- Noise
----_'X
X
>--
Noise Occurrence in Address Bus During Write Cycle
If the data bus Do
~
0 7 changes from "FF" to "00", extremely
large transient current flows through the GND line.
Then the
noise is generated on the LSI's VSS pins proportioning to the
transient current and to the impedance (Zg) of the GND line.
Do-~-;I-<
,
I 63~2
HD
_ _---I
Fig. 7-7-2 Noise Source
This noise level, Vnl appears on all output pins on the LSI
including the address bus.
Fig. 7-7-3 shows the dependency of the noise voltage on the each
parameter.
~HITACHI
213
Vn: Noise Voltage Zg: GND Impedance
Cd: Data bus load capacitance
N: Number of data bus lines switching from H to L
Fig. 7-7-3
7.7.2
Dependency of the Noise Voltage on each Parameter
Noise Protection
To avoid the noise on the address bus during the system
operation mentioned before, there are two solutions as
follows:
The one method is to isolate the HD6301Vl from peripheral
devices so that peripherals are not affected by the noise.
The other is to reduce noise level to the extent of not affecting peripherals using analog method.
(1)
Noise Isolation
Addresses should be latched at the negative edge of the AS
signal or at the positive edge of the E signal.
is often used in this case.
r---------~-.Do-D,
LS373
Ao - A,
G
HD6301Vl
P 40
-
P471------1---+1':/
A----/ AI -- Au
AS
' " Additional Latch
174LS373 for
noise isolation)
~HITACHI
214
The 74LS373
2.
Noise Reduction
As the noise level depends on each parameter such Cd, VCC'
Zg, the noise level can be reduced to the allowable level by
controlling those analog parameters.
(a) Transient Current Reduction
(i)
Reduce the data bus load capacitance.
If large load
capacitance is expected, a bus buffer should be inserted.
(ii) Lower the power supply voltage VCC within specification.
(iii) Increase a time constant at transient state by inserting a resistor (100
~
200~)
to Data Buses in series
to keep noise level down.
Table 8-1 shows the relationship between a series
resistors and noise level or a resistor and DC/AC
characteristics.
R
Di~~----
f'O '/0'8V~:
o
>
I
------------
5:
R=100n
~R=200n
'0
Z
1----
R=O
0.5
~
~~ng
:
V~
:
R: Series Resistor
OL-------.-----~.--------
50
100
Cd (pF)
Data bus load capacitance
Fig. 7-7-4
*Note:
The value of series resistor should be carefully
selected because it heavily depends on each parameter
of actual application system.
Fig. 7-7-5 shows the typical wave form of the noise.
E pin
A. pin
Fig. 7-7-5
~HITACHI
216
(b) Reduction of GND line impedance
(i) Widen the GND line width on the pe board.
(ii) Place the HD630lVl close by power source.
(iii) Insert a bypass capacitor between the Vee line and
the GND of the HD630lVl.
O.l~F)
A tantalum capacitor (about
I
is effective on the reduction.
~~------'--------'------'---~'r----
Power
Source
~~-------L------~~------~~r-----
(Recommendedi
Power
Source
~~
________
~
________L -______
~~
recommended)
Fig. 7-7-6
Layout of the HD6301Vl on the PC Board
~HITACHI
217
APPENDIX
I.
EPROM ON PACKAGE HD63POIM1
1.
(1)
•
•
•
•
•
•
•
Overview
The HD63P01M1 is an 8-bit CMOS single-chip microcomputer unit, which
can use 4k bytes or 8k bytes of EPROM on the package instead of
internal ROM. The HD63P01M1 can be used to debug or emulate the
HD6301V1 for software development. And also it can be used in
low-volume production.
Features
Pin Compatible with HD6301V1
On Chip Function Compatible with HD6301V1
128 Bytes of RAM
29 Parallel I/O
2 Lines of Data Strobe
16 Bit Programmable Timer
Serial Communiction Interface
2 Interrupt Pins
Low Power Consumption Mode
Sleep Mode, Standby Mode
Minimum Instruction cycle Time
lp.s (f=1MHz)
Bit Manipulation, Bit Test Instruction
Protection from System Upset
Address Trap, Op-Code Trap
Applicable to 4k or 8k Bytes of EPROM
4096 Bytes
HN482732A
8192 Bytes : HN482764, HN27C64
II. 1.5 MHz & 2 MHz Operation in Single Chip Mode of HD63P01M1
HD63P01M1 now in mass production is guaranteed to be operated in 1 MHz.
But if it satisfies the conditions belo~ it can be operated in up to 2
MHz.
Note (1)
Note (2)
Note (3)
Note (4)
Only single chip mode (mode 7) is available.
The access time is limited when the operating frequency is more than 1
MHz. So, use the EPROM which satisfies the condition belo~
While operating in 1.5 MHz, the access time must be less than or
equal to 400 ns.
While operating in 2 MHz, the access time must be less than or
equal to 250 ns.
Temperature Range : Ta=ooC-70oC
Operating Voltage : Vcc=5V±10%
This data is only for reference, and does not guarantee this
characteristic.
~HITACHI
218
(2)
Pin Arrangement
o
OVcc
OA 12
OA,
OA.
OA.
OA.
OA 3
OA2
OA,
OA.
00.
00,
002
OVss
I
Al1 0
Vss 0
A,. 0
CE
0,
O.
O.
O.
03
0
0
0
0
0
0
(Top View)
(NOTE) EPROM is nol included.
(3)
Dimensional Outline
eDC-40P
50.28
(1.980)
I
20
e
O.25~:~
(O.OIO~:::::)
Note)
Inch value indicated for your reference
~HITACHI
219
(4)
Block Diagram
p ••
P"
p..
P"
P"
p ..
P..
P"
r------------1
A<>
AI
I
As
As
As
As
Ai
A,
EPROM
HN482732AJ
HN482764
HN27C64
Ai
Ai
A,.
A"I
Alii
llE"1
I
I
I
0.1
0,1
0. 1
0.1
0. '
Data
Input
0. '
0.1
I
O'I--~____~
IL _ _ _ _ _ _ _ _ _ _ ...II
~HITACHI
220
(5)
Memory Map and Operation Mode
The operation mode of the HD63P01Ml is similar to the HD6301Vl.
As for the memory map, EPROM address space is 8k Bytes
($EOOO
to $FFFF) in the HD63P01Ml, while ROM address space is 4k
Bytes ($FOOO to $FFFF) in the HD6301Vl.
HD63P01Ml0
Mode
Multiplexed Test mode
HD63P01Ml
Mode
Non-Multiplexed ;Partial Decode
$0000 11 I
$0000
Internal Registers
Internal Registers
$001 F
1
F"'=""'="9
$001F
External Memory Space
External Memory Space
$0080
$0080
Internal RAM
Internal RAM
$OOFF
$OOFF
External Memory Space
External Memory Space
EPROM
$FFFF L-________,;
[NOTES]
1 J Excludes the following addresses which may be
used externally: $04, $05, $06, $07 and $OF.
21 Addresses $FFFE and $FFFF are considered
external if accessed within 4 cycles after a
INOTE]
Exctudes the follOWing addresses which may be
used externally; $00, $02, $04, $05, $06, $07
and $OF.
positive edge of RES and internal at all other
times.
3) After 4 CPU cycles, there must be no overlapping of internal and external memory spaces to
avoid driving the data bus with more than one
device.
4) This mode is the only mode which is used for
testing.
(to be continued)
~HITACHI
221
HD63P01M12
Mode
HD63P01M15
Mode
HD63P01M14
Mode
Multiplexed/RAM
Non·Multlplexed/Partial Decode
$0000
Internal Registers
Internal Registers
SOOIF
E xter nat Memory Space
S0080
$0080
) Internal RAM
Internal RAM
SOOFF
SOIOO
SooFF
-"T'"--
} External Memory Space
SOl F F ......
External Memory Space
$EOOO
EPROM
SFFFF
~
_ _ _..... ,
Internal Interrupt Vectors
SFFFF
(NOTEI
Excludes the following address which
may be used externally: $04, $05, $06,
$07,$OF.
(NOTEI
Excludes S04, S06, SOF.
These address cannot be used
externally.
(to be continued)
~HITACHI
222
HD63P01M16
Mode
HD63P01M17
Mode
Single Chip
Multiplexed/Partial Decode
Internal RegLsters
$OO1F
Internal Registers
External Memory Space
S0080
Internal RAM
$OOFF
External Memory Space
$EOOO
$EOOO
EPROM
EPROM
Internal Interrupt Vectors
Internal Interrupt Vectors
$FFFF
$FFFF
[NOTE[
Excludes the followmg address which may be
used externally: $04, $06, $OF.
~HITACHI
223
2.
Precautions to Use the HD63P01Ml
(1)
Precaution to Emulate the HD6301Vl by HD63P01Ml
Please use 4k bytes of EPROM address space located from $FOOO
through $FFFF.
But do not use 4k bytes from $EOOO through
$EFFF because these addresses are internal for the HD63P01Ml,
while these are external for the HD6301Vl.
(2)
Precaution to Use the EPROM On-Package 8-bit Single Chip
Microcomputer
Please pay attention to the followings, since this MCU has
special structure with pin socket on the package.
(a) Don't apply high static voltage or surge voltage over
MAXIMUM RATINGS to the socket pins as well as the LSI
pins.
If not, that may cause permanent damage to the
device.
(b) When using 32k EPROM (24 pin), insert it on the mark side
and let the four above pins open.
/
4 Pins (On index side) open.
24 Pin EPROM should be inserted
on the mark side with 4 above open.
(C) When using this in production like mask ROM type single
chip microcomputer, pay attention to the followings to
keep the good contact between the EPROM pins and socket
pins.
(i) When soldering the LSI on a print circuit board, the
recommended condition is
Temperature : lower than 250°C
Time
: within 10 sec.
(ii) Note that the detergent or coating will not get in
the socket during flux washing or board coating after
soldering, because that may cause bad effect on
socket contact.
~HITACHI
224
(iii) Avoid permanent application of this under the condition of vibratory place and system.
(iv) The socket, inserted and pulled repeatedly loses its
contactability.
It is recommended to use new one
when applied in production.
Ask our sales agent about anything unclear.
~HITACHI
I
225
II PROGRAM DEVELOPMENT PROCEDURE AND SUPPORT SYSTEM
1.
Overview
The cross assembler and the hardware emulator using various
types of computer are prepared by the company as supporting
systems to develop user's programs. User's programs are mask
programmed into the ROM and delivered as the LSI by the
company.
Fig. II-1 shows the typical program design procedure and
Table II-l shows the system development support tool for
the HD6301Vl which are used in these processes.
Text Editor/CRT Editor
Host computer
Cross Assembler
Host computer
Emulator
EPROM on-chip LSI, H06,3701VOC
EPROM on-package LSI,
H06,3P01Ml
Fig. 11-1
Program Design Procedure
(Explanation)
Q)
When the user programs the system using the HD6301Vl
series, a functional assignment of each I/O pin and an
allocation of RAM area should be specified adjusting to
designed system before actual programming.
GD
A flowchart is designed to implement the functions and
it is coded by using the HD6301Vl mnemonic code.
~HITACHI
226
GD
Write the software coded according to the flowchart on a
floppy disk to make a source program.
QD
Assemble the source program to generate an object program
using a computer.
I
Assembly errors are also detected.
~ Verify the program through hardware emulation with an
emulato~
EPROM on-chip or EPROM on-package type
microcomputer.
~ Send the completed program to the company in the form of
EPROM.
tion"
G)
Send "Single-chip microcomputer order specificaand "Mask option list" at that time.
ROM and mask option are masked by the company.
LSI is
testatively produced and the sample is handed in to the
user.
If a user doesn't see any problem in programming,
mass production can be started.
~HITACHI
227
Table II-l
Part
Emulator
No.
EPROM onchip LSI
HD6301Vl,
H31MIX4
HD6303R,
(HS31VEML04H)
HD63701VOC
Support Tools
Pro~ram-
EPROM on-
IBM PC
IBM PC
ming Socket Adapter
package LSI
cross assembler
C Compiler
H31VSAOIA
HD63POIMl
S31IBMPC
US31PCLI1SF
EPROM on-chip LSI
HD6303Rl
HD6301Vl and HD6303R Development Tools
~HITACHI
228
2.
Single Chip Microcomputer ROM Ordering Procedure
(1)
Development Flowchart
Single chip microcomputer device is developed according to
the following flowchart after program development.
(DROM code *1
@ Mask Option List *2
Q)ordering Specifications *3
V
OK
submitted
*5 Send it back after
approving
I~ Verification Listing
*5
I
Sample
I
microcomputers
*4 The same ROM code as
ROM code for confirmation of ROM fabricating
specifications *4
Mask
*1 2 sets of EPROM
*2 Part specific
*3 Generic for Hitachi
I
Computer processing
t
Remarks
Customer
Hitachi
I
*6 3 pcs
*7 Start the following
flowchart after approving
*8 Send back signed working
sample approval form
I
*9 10 pcs
Working Sample (WS)
*6
l
I
!
® Confirmation
of function, characteristics
*7, *8
+
Engineering
OK
Sample (ES) l
I
*9
I
Confirmation of function, characteristics,
quality
1
Commercial Sample (CS)
I
(E~)
(Note)
Please send in CD
, ®,
and
® at
ROM ordering, and send back ~ ,
®
after approvin·;J.
Device Development Flowchart
~HaTACHI
229
(2)
Data you send and precautions
(a) Ordering specifications ----- Common style for all Hitachi
single chip microcomputer
devices.
Please enter as
for the followings.
The
format is shown in the next
page.
o
Basic ITEM
o
Environment Check List
o
Check List of attached data
o
Customer
(b) ROM code
Please send in the ordering ROM code by 2
sets of EPROM the same contents are written.
Enter ROM code No. in them.
It is de-
sirable to send in program list for easy
confirmation of the program contents.
(3)
Change of ROM code
Note that if you change the ROM code once sended in or other
specification, the ROM must be developed from the beginning.
The cost of mask charge should be provided again in this case.
(4)
Samples and Mass production
(Working Sample) ----------- Sample for confirmation of the
contents of ROM code and that
of mask option. Normally 3 samples
are sent, but not guarante~d as for
reliability. Please evaluate and
approve immediately because the
following sample making and mass
production are set about after
obtaining your evaluation.
(Engineering Sample) ------- Sample for evaluating also reliability.
10 pcs are included
in mask charge.
~HITACHI
230
(Conunercial Sample) -------- Samples for pre-production which
maybe purchased separately.
(Mass Product) ------------- Products for actual mass production. Please enter the plan of
mass production in full.
I
~HITACHI
231
II
2.5.
HD6301Vl
ORDERING SPECIFICATIONS
(1) GENERAL CHARACTERISTICS (Fill in blank space or check appropriate box 0.)
Customer
Package Outline
(See page 183.)
Device
Type
Application
(be specific)
Customer
ROMCodeID
ZTAT TM
Conversion
DDP-40
D
CP-44
DFP-54
D
CP-52
DCG-40
Options/Remarks:
DYes
ROM Code
Media
DEPROM
Operating
Temperature
o
Remask
DYes
D
OZTATTM
No
Must Specify: Customer Programmed Start Address
Customer Programmed Stop Address
Standard D
0
J (-40· C to +85· C) version if offered
No
Previous Hitachi PIN
(2) OPERATING CHARACTERISTICS (Fill in blank space or appropriate box
LSI
Ambient
Temperature
LSI
Ambient
Humidity
Typical
Power On
Duration
Typical
Range
Typical
Range
Power
Maximum Applied Suoolv
Voltage To LSI
I/O
·C-
·C Target Level
Of Reliability
·C
D
D
% Acceptable Electrical
Quality
Major
%% Level
Vi.",,, 1
LSI
Operating
Speed
Hours/Day
(SJl~cifyMHz or KHz)
Remarks:
Max.
V
Max.
0.)
1000 Fit
D(
)
l J
500 Fit
D
0.25%
<
)
D
0.65% D<
)
V
(3) ELECTRICAL CHARACTERISTICS (Fill in blank space or check appropriate box 5J .)
o
Purchasing Specifications
o
Hitachi's Standard Specifications
Refer To Data Sheet:
( For Hitachi Use Only)
(4) CUSTOMER APPROVAL
(5) ROM CODE VERIFICATION
Customer Name,_ _ _ _ _ _ _ _ _ _ _ _ _ __
PO# _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
LSI Type No.
Approved By (print),_ _ _ _ _ _ _ _ _ _ _ ___
Shipping Date of
ROM To Customer
Approved By (signature)
Approved Date of
ROM From Customer
Date
~HITACHI
232
III
Q & A
Theme
QUllstion
Answer
Process to Use
a Port as an
Outputs
When using an I/O port as an output,
is the data stored to the Data
Register or is the Data Direction
Register (DDR) set at first?
Store the data to the Data Register at first and then set
DDR (DDR=l); if not, unknown data is output from the
port.
Relation between
Writing into the
FRC and SCI
Operation
How are writing into the timer Free
Running Counter(FRC) and the Serial
Communication Interface(SCI) related?
The source of the clock input to the SCI Shift Registers
is the timer FRC.
Therefore, if new data is written into the FRC, SCI
operations are disturbed.
See the following diagram.
$09,$OA
/W
~
:I
~
E
I
JL FRC ...J1.. Baud Rate
-
o
~
Receive Shift]
Register
- - Genera tor
Transmit Shift1
Register
:I
* A write into the FRC is prohibited during SCI operations.
Writing into the
FRC during Seria
Receive/Transmit
N
(,)
(,)
Is it prohibited to write data into
the Free Running Counter (FRC) during
serial receive/transmit?
Yes. If data is wri~ten into the FRC during serial
receive/transmit, the FRC stops counting up and the baud
rate changes.
In condition other than serial receive/transmit, it's
possible to write.
..
I\)
~
Question
Theme
Answer
$09, $OA
~te
EJL
_
,JcIJl
Receive Shift
Register
Baud Rate
Generator
I
------l
~
:I
~
(')
:I
RDRF State When
SCI Receiving
I
When the wake-up flag is set (WU=l) the RDRF flag
cannot be set. (RDRF=O)
What is the state of the Receive Data
Register Full(RDRF) flag when the
HD6301Vl/HD6303R SCI can receive
signals (RE=l) and the wake-up flag
(WU bit) is set?
TRCSR
765
432
1
0
$0011 I RDRFIORFEITDREIRIE IRE ITIE I TE I wu I
+
?
t1
Transmit Shift
Register
1
I
II
n
r1' - - i~
L...-...J
The counter stops
and the baud rate
changes.
+
1
Theme
Serial I/O
Operation
Question
The serial I/O does not operate
satisfactorily. Initialization does
not seem to be wrong, but the data is
not transmitted. What is wrong?
Initialize by User Program
(1) Set the Rate/Mode Control Register
(RMCR) to the desired operation.
(2) Set the Transmit/Receive Control
Status Register (TRCSR) to the
desired operation.
Answer
Just after the initialization of serial I/O, the data
transmit is not operative during 10 cycles of Baud Rate
after setting the TE. The reason is as follows.
Setting the transmit enable bit (TE bit) causes ten
consecutive "I" of preamble and makes the transmitter
section operative. In other words, the transmitter
section gets ready after one frame (10 bits) transmitting time according to the Baud rate.
(ex.) When the Baud rate is set to 9600 Baud (104.2vs
at 1 bit) ,
Set the Baud rate
Set TE
Transmit OK
'7hfi//Il//T~/lITfl//////Zl ____
~104.2vs x
•
~
~
:I
~
Preamble Causing Period
1.042ms after setting the TE, the transmitter section
is operative.
I:
(')
u o ____
10=1.042ms:~: Transmit Inoperative Period
Serial I/O
Register Read
When transmitting the data, is reading
the Transmit/Receive Control Register
(TRCSR) required?
When the transfer interval is long enough
compared with the Baud rate, Transmit
Oata Register Empty (TORE) will be set.
In that case, are there any problems
when transmitting data without checking
the TORE flag in the TRCSR?
The TORE flag shows if the TORE register is empty or
not. When writing a data to the TOR with TORE=l, it's
not necessary to check the TORE. But reading the TORE
flag tells us the contents of TOR. For example, when
new data is written to the TOR with TORE "0" (TOR
already has a data); the old data will be erased.
When the transfer interval is long enough compared with
the Baud rate, there's no problem. However, check
TRCSR if possible.
I\)
W
01
--
~
Q)
Theme
Detection of the
HD6301Vl Serial
Start Bit
Question
(1) What is the relation between the
HD6301Vl serial sampling clock
frequency and the baud rate ?
(2) What does "Sampling error" mean ?
Answer
(1) The serial sampling clock frequency is eight times the
baud rate.
(2) "Sampling error" means receive margin at the serial
operation time.
Receive
The
bit
The
•
margin:
HD6301Vl detects the start bit and samples the data
using the falling edge of the sampling clock.
general equation is shown as follows.
1.) General equation
M= [(0.5-1/N) - (D-0.5)/N- (L-0.5)F] x 100 (%)
M: Receive margin
N: Ratio of baud rate to sampling clock (0 to 0.5)
D: Duty of the longer sampling clock of "B", and
"LII
:r:
L: Frame length (7 to 12 bits)
F: Absolute value of deviation of sampling clock
~
(')
:r:
fr~uency
2.) Abbreviated equation
M = (0.5-1/N) x 100 (%)
Conditions: D = 0.5, F
8
N
M
37.5
(%)
16
32
43.75 46.875
(Fig.l)
0
64
48.4375
Note
In the HD6301Vl, N=8.
Figure 1
12345678
Clock
I
Rx
I!----J--'- - - - - - l
{
r
:
:
50%
Start bit
lIN
Tr~er
r
Start bit sampling
0.5
J
1
Theme
Free Running
Counter Read
Question
Answer
When the FRC of the HD6301Vl/HD6303R is
read with the double byte load instructions (2 cycle execution for FRC reading), is it read correctly?
Double byte load instructions require
two cycles to be executed and the cycle
to read the low byte of FRC becomes the
next cycle of the high byte.
Is it OK ?
The FRC of the HD6301Vl/HD6303R contains a parallel
temporary register. When the high byte of the FRC is
read, the low byte is set in the temporary register.
The Low byte data in the temporary register is set to
the AccD at the next cycle. Therefore, it is possible
to read the FRC correctly.
,IHlg
. h Read'I
E
(EX)
I
I
,
I
I
I
:(1 cycle)
: $F7FF
: (2 cycle):
: $F800
FRC
: High Read: Low Read:
E
FRC
($09, $OA)
'T
~
AccD
'::::t..I
Read Data
F7 00
:I
I $F7 FF
'FF,
:
(When reading $F7FF from the counter)
--,,
$F8 00
!
1---
I
I
,
I
I
'
I $F7
,
AccD
~
"
Temporaly
Register
,----,
I
Low Read'I
$FF :
t
*,
1F7 : FFI',
(When reading $F7FF from the counter)
:I
Preset Method of
the Free Running
Counter
What is the difference between the
HD6801V and HD6301Vl in writing data
into the free running counter ?
The FRC preset method of the HD6801V is different from
the HD6301Vl.
Type
Preset Method
HD6801V
The FRC is always preset to "$FFF8".
HD6301Vl
1. Writing to the high byte presets the FRC
to $FFF8.
2. The FRC is set to desirable data by a
double byte store instruction.
rv
CAl
-..J
--
~
Question
Theme
Q)
Answer
(1) The HD6801V Preset Method
I
I
I$09Write I $OAWrite:
:.. ($5A) -:.. ($F3)-'
I
#$5AF3
$09
E
I
I
FRC
$FFF8
$FFF9
$FFFAl-
The FRC is always preset to $FFF8.
(2) The HD6301Vl Preset Method
1. $FFF8
~
$09Write
($5A) ..I
I..
E
I
J:
~
(')
...
..
I
PRC
I
LDD #$5AF3
-STAA $09
I
I
$FFF8
,I
$FFF9:
I
$FFFAlI
Writing to the high byte presets the FRC to $FFF8.
J:
2. Optional valve (In this case$5AF3)
~09write
I
,
($5A)
..:...$OAWrit5:
,
($F3) I
I
_LDD
STD
I
#$5AF3
$09
E
I
PRC
$FFF8
$5AF3
I
I
$5AF41-
The FRC is set to desirable data ($5AF3) by a double
byte store instruction.
I
Output of Address Is AS always output when using the
Strobes (AS) in
HD6301Vl in the expanded multiplexed
the Multiplexed
mode (mode 2, 4, 6)?
Mode
Yes. AS is always output in the expanded multiplexed
mode, even when the MPU accesses the internal RAM, ROM,
etc.
Theme
IRQl Acceptance
Answer
Question
(1) Is IRQl ignored when the Condition
Code Register I mas~ is set?
(1) If the Condition Code Register I mask is set, IRQl
is completely ignored.
(2) After the I mask is reset, will
the interrupt sequence start by
the interrupt request flag having
been latched?
(2) With the I mask set, the interrupt request flag will
not be latched.
(2)
(1)
Reset starts
Reset starts
CLI
1=1
SEI
IRQl
~
IRQl
:I
~
C')
:I
IRQl is ignored.
Timer Interrupt
and External
Interrupt
In the routine below, when is the
next timer interrupt accepted?
Main
Routine
Timer (OCI)
External
Routine
Interrupt
(Execution time
(IRQ) Routine
=1.5ms) (Execution
time=3ms)
Read the TCSR
Store 2.6ms at timer
per iod to the OCR
Next
V
Timer
Inter-
l\.
rupt
Request
Execution time
is longer than
r---.....
.1 •
timer in terrupt per iod.
I=1
IRQl is ignored.
The next timer interrupt is accepted in the main routine
just after RTI instruction execution.
Main
Timer (OCI)
Routine Routine
External Interrupt
(IRQ) Routine
Interrupt
Request
Next Timer
(OCI) Routine
RTI
I\)
w
(0
--
I\)
Theme
t)
Answer
Question
IRQl Interrupt
and Other
Interrupts
IRQl pin (pin 5) is held at low for
but an interrupt does not occur.
What should be done to generate an
interrupt sequence?
lO~s
E
IRQl
~J--lL-1
I
I
:I'I~·
I
:;
lO~s
:I
I
I
(1) IRQl is a level sensitive interrupt pin which needs
a minimum of 2 machine cycles (2~s at IMHz) to accept an
interrupt. However, if another interrupt has been
already generated, no interrupt request is accepted with
IRQ! at low for lO~s.
In such a case, IRQ! should be held at low until the
request is accepted.
E
IRQl
.
~2
P:
machine
I
cycles~
I
I
(2) In this case, as a timer interrupt is executed the
interrupt mask is automatically set. So IRQl is ignored.
~
:I
~
See the followings for the illustration of IRQ 1 and other
interrupts and a countermeasure.
IRQl and Other Interrupts
Main
Routine
o
:I
IRQ! Interrupt
Request
Timer
Routine
IRQl
Routine
~",""'1.
I
~
IRQ! is
. . . . . . .1
ignored.
Countermeasure
Clear the I mask at the beginning of the timer
interrupt routine.
Timer
Main
IRQl
Routine
Routine
Routine
~
~
IRQl is acceptable.
*CLI : Clears the interrupt mask {I=O}.
Wi th this method, note the following ;
(1) IRQl may be ignored when the request occurs during
timer interrupt vectoring.
(2) Interrupts form NMI or SWI are excluded.
~I=l
Theme
CLI Instruction
and Interrupt
Operation
Question
Answer
In the HD6301Vl, a timer interrupt
is not accepted in the following
program. Is there any problem?
To accept an interrupt, two machine cycles are necessary
between CLI and SEI. That is, in this program, two NOP
instructions are necessary. The same thing can be said
when using TAP for CLI and SEI.
--~---:--I
Maln Routlne
LOl CLI
NOP
SEI
I
I-LOl
I
I
I
I
BRA
LOl
I
1_ _ _ _ _ _ _ 1
Using TAP
Using CLI
I
1
I
TAP (Clears the I mask)
NOP
NOP
TAP (Sets the I mask)
CLI
NOP
NOP
SEI
1
I
I
BRA LOl
1
~
1:
~
(")
Relation between
the External
Clock (EXTAL
Clock) and
Enable Clock
(E Clock)
With which edges of the EXTAL clock
does the E clock change synchronously,
rising edge (tl or falling edge (.)?
It changes synchronously with the falling edge
EXTAL clock.
q)
of the
~XTAL~
J:
Constants of the iDoes the capacitor of the recommended
Reset Circuit
reset circuit in the HD6303R (HD6301Vl)
have an upper limit?
Capacitor Cr does not have upper limit because of the
Schmitt trigger circuit provided with the RES.
Available if Rr.Cr»20ms
To the system power supply
~
~;;;
+
f
Vee
Rr
+
m
.... ,
I\)
~
STBY
~
RS
I r;:,....
STBYl
IV--
mCS
RESI~l
P"
Rr
To
peripherals
INMI
l
J
f
~I
-14
...L. C r
HD6301V
..
RIC: R2,RroCr»20ms
I~
III~
t
Theme
•
%
~
Answer
\Question
Port Output
After Resetting
What data does a port output when the
Data Direction Register(DDR)=1
after resetting?
After resetting, since the Data Register of a port is
undefined, undefined data is output when the DDR=I.
Input definite data by programming in the Data Register
before setting the DDR=I.
Schmitt Trigger
Circui t of STBY
Is the Schmitt trigger circuit
provided with the HD630lVI STBY?
Yes.
Return from
Standby Mode
What occurs when returning from the
standby mode without using RES?
The CPU does not operate normally because the contents
of each register are not definite.
Therefore, always use the RES when returning from the
standby mode.
Going into the
Standby Mode
Does the CPU go into the standby mode
after current instruction execution
is completed?
No. Because there is no connection between the instruction execution sequence and the standby mode. That is,
when the STBY pin goes into "Low", the state is latched
at the next rising edge of E clock. Then the internal
registers are reset at the next falling edge.
C)
%
! - - Internal registers
:
E
I
I
I
STBY
I
I
t
are reset.
Theme
Question
Timing for the
Standby Mode
The timing for the standby mode is
shown in the HD630lV user's manual.
TI is not defined. How long is TI?
©
'2"
NMI~
-RE-S
:-,- ,_ _ _ _---J
STBY
I
'
,
I
j+-
II
~
RAM
Control
Register set
T2
J:
o~
J:
After the RAM Control Register is set in the NMI routine,
either STBY or RES can be in the low state with no
priority.
....;r-
I,~ T I L.......
L-'-_
== _ _ _ _ _
ICJ
®
~
Answer
~
I
~T2~
I -
,IReset Start
Oscillation Stabilization Time
Usage of EPROM
Socket Pins for
the HD63POIM
(No.!)
Are the data buses of the EPROM
socket pins for the HD63POIM bidirectional in order to access not
only the EPROM but the RAM?
The data bus output from EPROM socket pins for the
HD63POIM is Read only.
Usage of EPROM
Socket Pins for
the HD63POIM
(No.2)
In EPROM socket pins for the HD63POIM,
what is CE composed of?
CE is a NAND circuit of the address bus (A13 to A15) and
the MCU internal R/W signal.
(Refer below.)
Therefore, CE does not output in the dummy cycle.
(When not accessing EPROM of HD63POIM)
I-~rw-I-
I
I
I
Ao
I
I
I
I
Au
I
Al .. l~
,I___A1S !I .
~
r---I
I
I
I
I
I
I
I
I
I
I
CE
I
I____ J
--
t
Theme
Question
Answer
Usage of EPROM
Socket Pins for
the HD63POlM
(No.3)
With EPROM socket pins for the
HD63P01M,
(1) Can pins drive one TTL load or
more?
(2) If not, what can pins drive?
(1) The current of each pin is too little to drive one
TTL load.
(2) Each pin can drive one NMOS load.
Usage of Bit
Manipulator
Instructions
How the bit manipulation instructions
of the HD6301V should be written?
They are written as follows;
OIM
OIM
# $ 0 4 ,
# $ 0 4 ,
T
Immediate Data
•
l:
~
(')
l:
$ 1 0
$ 1 0 , X
(Direct Addressing)
(Index Addressing)
T~
Address
Index Register
This is an example of OR operation of the immediate data
and the memory and storing the result in the memory.
The HD6301V has the following bit manipulation
instructions.
OIM
(IMM) • (M) - (M)
AIM
(IMM) + (M) - (M)
ElM
(IMM)
(M) -(M)
(IMM) • (M)
TIM
These instructions are written in the same way.
e
The following bit manipulations have different mnumonics
in the same OP code.
OP code
I
Bit Manipulation Instruction
.
Mnumonics
Function
o "Mi
71161
A I M
B C L R 1 The memory bit i(i=O to 7) is
cleared and the other bits
don't change.
o I M
The memory bit i(i=O to 7) is
set and the other bits don't
change.
l .. Hi'
72 1 62
B SET
Theme
Question
Answer
75 I 65
E I M
B T G L
Mi +Mi
The memory bit i(i=O to 7) is
inverted and the other bits
don I t change.
B T S T
1 . Mi
operation test of the
memory bit i(i=O to 7) and
"1" is executed and its
corresponding condition code
is changed.
AND
7B I 6B
t
TIM
_____
Direct
Addressing
~
:I
~
C')
:I
Index
Addressing
The mnumonics mentioned above can be written as follows.
BCLR
BCLR
BSET
BSET
3,$10
~AIM
3,$10,X~AIM
3,$10
~OIM
3,$10,X~OIM
TT~
Bit Address
#$F7,
#$F7,
$10
$lO,X
(Direct Addressing)
(Index Addressing)
#$08,
#$08,
$10
$lO,X
(Direct Addressing)
(Index Addressing)
Index Register
I\)
..,..
01
~
I\)
Theme
-I>Ol
Usage of Bit
Manipulation
Instructions to
the Port
Question
Are the bit manipulation instructions
(AIM, OIM, ElM, TIM) executable when
a port is in the output state
(DDR=l)?
Answer
It can be used if the port is in the output state
(DDR=l). However, the bit manipulation instruction
is executed as follows
1
2
3
Reads specified address.
Executes logical operation.
Writes the result into the specified address.
Since the specified address(l) reads the pin state of
the port, the data is influenced by the pins even if
any data is output from the port.
~
:I
~
(')
:I
RAM Access
Disable during
Program
Execution
When executing a program with the RAME
bit of the RAM Control Register
disabled,
(1) The external RAM can be accessed; the internal RAM
is neither readable nor writable when the RAME bit
is disabled.
(1) What occurs if the internal RAM
address is accessed?
(2) What occurs if the interrupt
requests are generated?
(2) If there is no stacking area other than the internal
RAM, the MPU will burst when returning from the
interrupt sequence.
HD6301 iHD6303 SERIES HANDBOOK
Section Four
I
HD63701V
User's Manual
~HITACHI
247
~HITACHI
248
Section 4
HD63701 V User's Manual
Table of Contents
Page
1. OVERViEW ................................................... .
1.1
Features of HD63701 VO ...................................... .
1.2
Block Diagram .............................................. .
1.3
Functional Pin Description .................................... .
251
251
251
252
2. INTERNAL ARCHITECTURE ..................................... .
2.1
Mode Selection ............................................. .
2.2
Memory Map ............................................... .
2.3
CPU Registers .............................................. .
2.4
Ports ...................................................... .
2.5
Timer ..................................................... .
2.6
Serial Communication Interface ................................ .
2.7
Interrupts .................................................. .
2.8
Reset ..................................................... .
2.9
Oscillator .................................................. .
2.10 Strobe Signals .............................................. .
2.11 RAM Control Register ........................................ .
2.12 Low Power Consumption Mode ................................. .
2.13 TRAP Function ............................................. .
253
253
258
263
265
269
273
281
283
285
286
287
287
292
3. EPROM (PROM) PROGRAMMING AND TECHNICAL SPECIFICATIONS .. .
3.1
PROM Mode ................................................ .
3.2
ProgrammingNerification ..................................... .
3.3
Erasure ................................................... .
3.4
On-Chip PROM Characteristics and Application ................... .
3.5
Instruction Set Overview ...................................... .
3.6
Addressing Modes ........................................... .
3.7
Instruction Set .............................................. .
Instruction Execution Cycles ................................... .
3.8
3.9
System Flowchart ........................................... .
3.10 Pin Arrangement and Package Information ....................... .
3.11 Electrical Characteristics ...................................... .
293
293
294
295
296
300
300
302
307
313
315
316
~HITACHI
I
249
4. APPLICATIONS.................................................
4.1
Use of External Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
Standby Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
4.3
Address Trap, OP-Code Trap Application. . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
Slow Memory Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .
4.5
Interface to HN61256. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.6
Interface to the Realtime Clock (HD146818). . . . . . . . . . . . . . . . . . . . . . . .
4.7
Reference Data of Battery Service Life ....................... . . ..
322
322
327
330
331
332
337
340
5. PRECAUTIONS.................................................
5.1
Write Only Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.2
Address Strobe (AS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.3
Mode O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.4
Trap Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.5
Precaution to the Board Design of Oscillation Circuit . . . . . . . . . . . . . . ..
5.6
Application Note for High Speed System Design Using the HD63701 VO .
5.7
Differences between HD6301V and HD63701V . . . . . . . . . . . . . . . . . . . ..
341
·341
341
341
341
343
343
347
APPENDIX
I.
Support Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
II.
Q & A............................. ................. ........
353
355
~HITACHI
250
1.
OVERVIEW
1.1
Features of HD63701VO
The HD63701VO provides the following features:
- Compatible with the HD6301V
- Expanded instruction set of the HD6801 family
- Abundant on-chip functions compatible witth the HD6801/
HD6301 family: 4k-byte of EPROM, 192-byte of RAM, 29
parallel I/O Lines, 2 data strobe Lines, 16-bit time~
serial communciation interface
- Low power consumption mode: sleep/standby mode
- Minimum instruction execution time: l~s (f = 1MHz) ,
0.67~s (f=1.5MHz)! 0.5~s (f=2MHz)
- Bit manipulation and bit test instruction
- Error detection: Address trap and op-code trap
- Address space up to 65k words
- Wide operation range:
f = 0.1 to 2.0MHz (Vee = 5V ± 10%)
- TTL compatible input/output
1.2
I
Block Diagram
A block diagram of HD63701VO is given in Fig. 1-2-1.
PROM MODE
Fig. 1-2-1
HD63701VO Block Diagram
~HITACHI
251
1.3
Functional Pin Description
Table 1-3-1 lists the pin functions.
Refer to "2. INTERNAL
ARCHITECTURE" for more details.
Table 1-3-1
Pin
Vec, VSS
XTAL
EXTAL
Pin Functions
Function
Power supply and GND pins
Crystal connection pin. When external clock is used, input it to
EXTAL, and XTAL should be open.
When this pin is asserted "Low", MCU is set to
RES
Reset input pin.
reset state.
STBY
Standby input pin. When this pin is asserted "Low", MCU is set
to standby state.
Edge sensitive (negative edge) non-maskable interrupt input pin.
NMI
IRQ 1
E
P,o/TIN
Level sensitive maskable interrupt input pin (active Low).
The frequency is 1/4 of the crystal
System clock output pin.
oscillator frequency.
5-bit I/O port
Timer input-capture input pin
P,,/TOUT
Timer output-compare output pin
P'2/SCLK
SCI clock I/O port
P, ,/RX
SCI receiving pin
SCI transmitting pin
P'4/ TX
Following pins function depending on each operation mode
Mode 0,2
PORT 1
8-bit
I/O port
PORT 3
Data (00",0, )
Lower address
(Ao"'A,)
Mul tiplexed
Bus
PORT 4
Upper address
(As"'AlS)
SC l
Address strobe
(AS) output
pin
SC 2
Read/write
signal
(R!W) output
pin
Mode 1
Mode 5
Lower address 8-bit
(Ao"'A,)
I/O port
Data Bus
00",0,
..
~
~
-
Oata (Do"'O, )
Lower address
(Ao",A,)
Multiplexed
Bus
-
Mode 7
-
Lower address
(Ao"'A,) or
Input-only
pin
Upper address
(As"'A,S) or
Input-only
pin
I/O strobe
(TIiS) output
pin
Address strobe I!!E,!!t strobe
(AS) output
(IS3) output
pin
pin
-
~HITACHI
252
-
Mode 6
-
8-bit
I/o port
O~ut
strobe
(OS) output
pin
2.
INTERNAL ARCHITECTURE
This section describes the HD63701VO internal architecture.
2.1
Mode Selection
After the MCU is reset, a user must determine the operation
mode of the HD63701VO by strapping three pins and which are
connected by hardware externally.
Individual signals on the above three pins are latched into the
program control bits PC2, PCl and PCO of I/O port 2 Data
register, when the RES signal goes "High".
I
The bit assignment
of the Port 2 Data Register is shown below.
Port 2
$0003
Data Register
7
6
5
4
3
2
1
0
IpC2lpCllpcolI/0 411/0 311/0 211/0 111/0 01
An example of an external circuit for mode selection is
shown in Fig. 2-1-1.
The HD14053B may be used to separate
the MCU from its peripheral devices during reset (Data
confliction should be avoided between the peripheral devices
and mode selection circuit).
Because bits 5, 6 and 7 of
port 2 are for read only, so the operation mode cannot be
altered by software.
The mode selection in the HD63701VO is
summarized in Table 2-1-1.
The HD63701VO has three basic operation modes:
1)
Single chip mode
2)
Expanded multiplexed mode
(Bus Compatible with HMCS6800 peripheral LSls)
3)
Expanded non-multiplexed mode
(Bus Compatible with HMCS6800 peripheral LSls)
~HITACHI
253
Truth Table
Control Input
Binary to 1-of-2
Decoder with
Inhibit
On Switch
SeI.cl
Inhibit
C B A HD14053B
xoo---------------~~~~~__,
x
X,o-----------------~~~~~
yocr------------------~~+_r__.
y
y,cr--------------------~~~~
Zocr--------------------~~+__,
Z
Z,o-----------------------~--J
0
0 0 0
Za Yo
0
0 0
1
Zo Yo
0
0
I
0
Zo VI
0
0
1 1
Zo V"'
0
I
0 0
0
1 0
Z. Yo
1
Z, Yo
0
1 1 0
Z,VI
0
1 1
Z,V I
1
X X X
I
X.
X,
X.
X,
X.
X,
X.
X,
-
HD14053B Multiplexers/De-Multiplexers
Vee
~
R
RI RI R,
6
R
J
~
... 8
X.
C
V.
·x
8
Z.
V
9
Z
P,.
X,
P"
v,
P"
Z,
C
I
1- ??
~
Mode
Conltol
SWitch
Fig. 2-1-1
Inh
RES
HD6370,VO
p,.
10 P" (PC21
HOl40538
Jr
Note 1) Figure of Mode 7
2) RC"'Reset Constant
3) R, =10kn
Recommended Circuit for Mode Selection
~HITACHI
254
(PCOI
P" (PC"
Table 2-1-1
Mode
Pn
(PC2)
P"
(PCI)
P,.
(PCO)
ROM
Mode Selection Summary
RAM
Interrupt
Vectors
Bus
Mode
Operating
Mode
7
H
H
H
I
I-
I
I
6
H
H
L
I
I
I
5
H
L
H
I
I
I
MUX'"
NMUX31
4
H
L
L
-
3
L
H
H
-
-
-
-
2
L
H
L
E'l
I
E
MUX
I
L
L
H
E'l
I
Non·Multiplexed
L
L
L
I
I
E
121
NMUX
0
MUX
Multiplexed Test
LEGEND:
I - Internal
E - External
MUX
- Multiplexed
NMUX - Non·Multiplexed
L - Logic "0"
H - Logic "1"
Single Chip
Multiplexed/Partial Decode
Non·Multiplexed/Partial Decode
Not Used
Not Used
Multiplexed/RAM
(NOTES)
1) Internal ROM is disabled.
2) Reset vector is external for 3 or 4 cycles after
fj3 goes "high".
I
3) Idle lines of Port 4 address outputs can
be assigned to I"put Port.
(1) Single Chip Mode
In the Single Chip Mode, all ports will function as I/O.
This
is shown in figure 2-1-2. In this mode, SCi, SCz pins are
configured as Port 3 control lines and functions as input
strobe (IS3) and output strobe (OS3) for handshaking data
respectively.
(2) Expanded Multiplexed Mode
In this mode, Port 4 is configured as I/O (inputs only) Port
or address lines.
Port 3 functions as multiplexed lower
address/data bus and Address Strobe (AS) selects the function
of Port 3.
Port 2 is configured as a 5-bit parallel I/O port or Serial
I/O, or Timer, or any combination thereof.
configured as an 8-bit parallel I/O port.
Port 1 is
In this mode
HD63701VO is expandable to 65k words (See Fig. 2-1-3).
Since the data bus is multiplexed with the lower address bus
in Port 3 in the expanded multiplexed mode, address bits must
be latched outside. 74LS373 (Octal-D type transparent latches)
is required for address latch.
Latch connection to the HD63701VO is shown in Fig. 2-1-4.
~HITACHI
255
Vee
Enable
=
Port 3
8110 Lines
Port 1
8110 LInes
Port 2
Port 4
51/0 Line.
8 I/O Line,
SCI
Vss
Fig. 2-1-2
Timer
HD63701VO MCU Single-Chip Mode
Vee
Enable
Port 3
8 Lines
Multiplexed
Data/Address
Port 1
8 I/O lines
Port 2
51/0 lines
SCI
Timer
Vss
Port 4
To 8 Address
Lines or To
8 I/O lines
(Inputs Only)
Fig. 2-1-3 HD63701VO MCU Expanded Multiplexed Mode
~HITACHI
256
GND
AS
,
11
.
Pon J
Addreu/D.la
GDe
D,
r
74LS373
l-
D,
]-'.".- ..
0,
0,
-
.
~
]~,.-.
Function Table
OutPUt
Control
L
L
L
H
En.ble
OutptJt
G
D
0
H
H
L
H
X
X
0,
H
L
X
L
Z
.
I
Fig. 2-1-4 Latch Connection
(3) Expanded Non Multiplexed Mode
In this mode, the HD63701VO can directly address HMCS6800
peripherals with no address latch. In mode 5, Port 3
functions as a data bus. Port 4 is configured as Ao to A7
address bus or partial address bus and I/O (inputs only) port.
Port 2 is configured as a parallel I/O port, Serial I/O
port, Timer or any combination.
Port 1 is configured as a
parallel I/O port only.
In this mode, the HD63701VO can access up to 256 bytes of
external address space.
In the application system with fewer
addresses, idle pins of Port 4 can be used as I/O lines
(inputs only)
(See Fig. 2-1-5).
In mode 1, Port 3 functions as a data bus, Port 1 functions as
Ao to A7 address bus, and Port 4 is configured as As to A15
address bus.
Port 2 is configured as a parallel I/O port,
Serial I/O port, Timer or any combination.
In this mode,
the HD63701VO is expandable up to 65k words with no address
latch.
(See Fig. 2-1-5).
~HITACHI
257
Vee
Vee
POrt 1
8 Parallel flO
Pori 3
8 Oala Lmes
Port 2
5 Parallel I/O
Pon 4
Ponl
To 8 Address lines
Port 2
5 Parallel 1/0
To 8 Address
Lines or To
81/0 Lines
flnputs Only,
SC'
Timer
Port 3
8 Data Lines
Port 4
To SAddre"
Lines
Se'
Timer
Vss
(al Mode 5
(b) Mode 1
Fig. 2-1-5 HD63701VO MCU Expanded Non Multiplexed Mode
(4) Mode and Port Summary MCU Signal Description
This section gives a description of the MCU signals for
the various modes.
SCI and SC2
function depending on the
operating mode.
Table 2-1-2 Feature of each mode and Lines
MODE
PORT
3
Eight Lines
PORT 4
Eight Lines
SC,
SC,
I/O
I/O
I/O
IS3 (I)
OS3(01
I/O
I/o
ADDRESS BUS
(A.-A,I
DATA BUS
(0.-·0,1
ADDRESS BUS'
(A.-A"I
AS(OI
RM(OI
I/O
I/o
DATA BUS
(0.-0,1
ADDRESS BUS'
(A.-A;)
10S(0)
R/W(OI
I/O
DATA BUS
(0.-0,1
ADDRESS BUS
(A,-A"I
Not Used
R/WiOI
PORT 1
Eight Lines
PORT 2
Five Lines
I/o
SINGLE CHIP
EXPANDED MUX
EXPANDED
Mode 5
NON-MUX
Mode 1 ADDRESS BUS
(A.-A,I
*These I ines can be substituted for I/O (Input Only) starting with the MSB
(except Mode 0,2,4). When they are not used as address lines.
I
o
A/iiii
2.2
• Input
= Output
Aead/Wrl'ii
=
153
053
105
= I nput Strobe
= Output Strobe
= 1/0 Select
SC
AS
= Strobe Control
=
Address Strobe
Memory Map
The MCU can address up to 65k bytes depending on the
operating mode.
Fig. 2-2-1 shows a memory map for each
operating mode.
The first 32 locations of eacb map are
reserved for the MCU's internal register as shown in Table
2-2-1.
~HITACHI
258
Table 2-2-1
Internal Register Area
Register
Address
Port 1 Data Direction Register
$00*1
Port 2 Data Direction Register
$01
Port 1 Data Register
$02*1
Port 2 Data Register/Mode Register
$03
Port 3 Data Direction Register
$04*2
Port 4 Data Direction Regi ster
$05*3
Port 3 Data Register
$06*2
Port 4 Data Register
$07*3
Timer Control and Status Regi ster
$08
Counter (High Byte)
$09
Counter (Low Byte)
$OA
Output Compare Regi ster (Hi gh Byte)
SOB
Output Compare Register (Low Byte)
SOC
Input Capture Register (High Byte)
SOD
Input Capture Register (Low Byte)
$OE
Port 3 Control and Status Register
$OF*2
Rate and Mode Control Register
$10
Transmit/Receive Control and
Status Register
$11
Receive Data Register
$12
Transmit Data Register
$13
RAM Control Register
$14
Reserved
R/W*4/Initialize at RESET
7 6 5 4 3 2 1 0
W
$00
W
$00
R/W *5
Undefined
R *6
R/W *5
Undefined
P2 2 PZ1 P20
W
$00
W
$00
R/W ~o
Undefined
R/W *5
Undefined
$l!Yv$lF
R
0
R
0
I
R R/W R/W R/W R/W R/W
0 0 0 0 0 0
R/W
$00
R/W
$00
R/W
$FF
R/W
$FF
R
$00
R
$00
R R/W Unused
0 0 1
Unused
1 1 1
R R R
0 0 1
R/W R/W Unused
0 0 1 1 1
W W W W
1 0 0 0 0
R/W R/W R/W R/W R/W
0 0 0 0 0
R
$00
W
$00
Unused
R/W R/W
*7 1 1 1 1 1 1 1
~
(*1 through 8 are shown in the next page.)
$HITACHI
259
*1
External address in mode 1.
*2
External address in modes 0, 1, 2, 5, 6; cannot be accessed
*3
External address in modes 0, 1, 2,
*4
R: Read-only register, W
*5
The pin state is read instead of the data of the register when
*6
The values of program control bit (PCo '" PC2) depend on
in mode 5.
Write-only register,
R/W : Read/Write register.
reading Ports.
(Refer to "2.4 I/O Ports" for I/O Port 3.)
P20 '" P21 during reset.
*7
Refer to "2.12 Low Power Consumption Mode" for standby mode.
HD63701VOQ
HD63701VO
Mode
Mode
1
Non-Multiplexed
Multiplexed Test mode
$0000 111
Internal Registers
Internal Registers
SOOIF
SOOIF
External Memory Space
EICternal Memory Space
Inlernal RAM
Interna' RAM
SOO8O
SOOFF
EIe tern.1 Memory Space
External Memorv Space
Internal PROM
12
[NOTES)
11 Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and
$OF.
21 R_t vectors $FFFE and $FFFF are located in external memory address space. However,
if $FFFE and $FFFF are accessed by software, Internal addresses will be accessad.
31 If internal address is read, the data in the
address is output through the data bus_
41 This mode is used only for testing.
SFFFF .....- - _... '
[NOTEI
Exclude. Ihe following .delre.... which may be
u..d exlern.lly; $00. S02. $04. S05. $06. S07
and SOF_
(to be conlinued)
Fig. 2-2-1
HD63701VO Memory Maps
~HITACHI
260
HD63701VO
Mode
2
Multiplexed/RAM
HD63701VO
Mode
5
Non·Mulliplexed/Partial Decode
$0000
$0000 . .)
Internal Registers
SOOlF
SOOlF
t::.-="i''''':.:<..:1
Un
External Memory Space
$0040
S0040
Internal RAM
SOOFF
I
~~~~~ In.emal RAM
~
SOlOO
SooFF
Internal Registers
)
External Memory Space
SOl F F L - - - r - -....
I
External Memor.y Space
SFOOOra
Internal PROM
SFFFF L-_ _ _... ,
$FFFF
{NOTEI
Excludes the following address which
may be used externally; S04, S05, S06,
S07, $OF.
{NOTEI
Excludes $04, S06, SOF.
These address cannot be used
externally.
(to be continued)
Fig. 2-2-1
HD63701VO Memory Maps
~HITACHI
261
HD63701VO
Mode
6
HD63701V07
Mode
Single Chip
Multiplexed/Partial Decode
$0000
50000
Internal Registers
Internal Registers
SOOIF
SOOIF
External Memory Space
$0040
S0040
Inlernal RAM
Internal RAM
SOOFF
SOOFF
EXlernal Memory Space
SFOOD
SFOOD
Internlll PROM
SFFFF
Internlll PROM
$FFFF
[NOTE]
Excludes Ihe following address which may be
used externally: $04, $06, SOF.
Fig. 2-2-1
HD63701VO Memory Maps
~HITACHI
262
2.3
CPU Registers
The followings describe the HD6370lVO internal architectures
and operations.
~
15- - -
°U
A
- -
- -
-
0
7
•
- - -
- -
-
-
-
3
$L
B·BI, Aceumul.,." A .nd •
Or 16·BItDoubl. Accumulator 0
x
01
Index Ragilter (XI
lIS
so
01
Stack Pointer ISPI
115
PC
01
0
Program Counter (PC)
I"
7
~
Fig. 2-3-1
I
Condition Code Register (CCRI
Carry/Borrow from MSa
Overflow
Z.ro
Negative
Interrupt
Half carry (From Bit 3)
HD63701VO CPU Registers
(I) Accumulators (A & B, or D)
Two a-bit registers (ACCA and ACCB) store the
result of arithmetic/logic.al operation and data. When
combined, they make up a 16-bit register (ACCD) used
for 16-bit operations. Note that the contents of ACCA
and ACCB are modified after an ACCD-based operation.
(2) Index Register (IX)
The 16-bit register IX stores a 16-bit data for use in
indexed addressing mode or for general purpose.
(3) Stack Pointer (SP)
The 16-bit register SP indicates the address of the next
available location in the stack.
This can also be used as
a general purpose register.
(4) Program Counter (PC)
The 16-bit register PC indicates the address of the instruction
being currently executed.
Note that the PC cannot be
accessed by software.
~HITACHI
263
(5) Condition Code Register (CCR)
The CCR consists of the following bits: carry (C),
overflow (V), zero (Z), negative (N), interrupt mask (I),
and half-carry (H). After an instruction is executed-,
these bits reflect the result of operation. They can be tested by
different conditional branch instructions.
of this register cannot be used.
detailed below.
The upper 2 bits
Individual bits are
Refer to the following description of each
instruction for more details.
(a) Half-carry (H)
This bit is set to "1" if a carry occurs between bit 3 and
bit 4 during execution of an ADD, ABA or ADC instruction;
cleared otherwise.
(b) Interrupt mask (I)
When set to "1", this bit disables any maskable interrupt (IRQI, IRQ2).
(c) Negative (N)
After an instruction is executed, this bit is set to
"1" if the MSB of the result is "1"; cleared otherwise.
(d) Zero (Z)
After an instruction is executed, this bit is set to
"1" if the result is "0"; cleared otherwise.
(e) Overflow (V)
After an instruction is executed, this bit is set if
the result of operation shows a 2's complement overflow;
cleared otherwise.
(f) Carry (C)
After an instruction is executed, this bit is set to
"1" if a carry or a borrow generates from MSB; it is
cleared cleared otherwise.
~HITACHI
264
2.4
Ports
The HD63701VO has four I/O ports (three 8-bit ports
and one 5-bit port).
the a-bit port.
2 control pins are connected to one of
Each port has an independent write-only Data
Direction Register to program individual I/O pins for input
or output.*
When the bit of associated Data Direction Register is "1",
I/O pin is programmed for output, if "0", then programmed for
an input.
I
Addresses of each port and associated Data Direction Register
are shown in Table 2-4-1.
* Only one exception is bit 1 of Port 2 which becomes either
a data input or a timer output.
It cannot be used as an
output.
Table 2-4-1
Port and Data Direction Register Addresses
Ports
Data Direction
Register Address
Port Address
Port 1
$0002
$0000
Port 2
$0003
~0001
Port 3
~0006
Port 4
$0007
$0004
I
$0005
(1) Port 1
Port 1 is an 8-bit I/O port, each bit being individually
defined as inputs or outputs by the Port 1 Data Direction
Register. The 8-bit output buffers have three-state
capability, maintaining in high impedance state when they
are used for input.
These are TTL compatible and can drive one
~TL
load and
90pF capacitance. After the MCU has been reset, all I/O
pins are configured as inputs in all modes except mode 1.
In all modes other than expanded non multiplexed mode 1,
Port 1 is always parallel I/O.
In mode 1, Port 1 is
configured as output lines for lower order address lines
(Ao
to A7).
~HBTACHI
265
(2)
Port 2
Port 2 has five lines, whose I/O direction depend on its
Data Direction Register.
The 5-bit output buffers have
three-state capability, going high impedance state when
used as inputs.
After the MCU has been reset, Port 2
I/O pins are configured as inputs.
P20 - P22 (pins 10 -
8) are used to program the operating mode. during reset.
r
The values of P20 - P22 during reset are latched into the
upper 3 bits (bit 7, 6 and 5) of Port 2 Data Direction
Register.
Refer to "2.1 Mode Selection" for more details.
In all modes, Port 2 can be configured as I/O lines.
This
port can also function as I/O pins for the SCI and the
Timer.
However, note that bit 1 (P21) is the only pin
restricted to data input or Timer output.
(3)
Port 3
Port is an 8-bit port which can be configured as I/O Port,
a data bus, or an address bus multiplexed with data bus.
Its function depends on operation mode, determined by
user using 3 bits of Port 2 during Reset.
Mode Selection.)
(Refer to 2.1
Port 3 as a data bus is bi-directiona1.
This TTL compatible three-state buffer can drive one TTL
load and 9 OpE; capacitance.
In the expanded Modes, Data
Direction Register is inhibited after Reset and data flow
is contro1ed by the state of the R/W signal.
Function of
Port 3 for each mode is explained below.
(a) Single Chip Mode (Mode 7):
Parallel I/O Port, whose
I/O direction are programmed by the Port 3 Data
Direction Register.
There are two control lines associated with this port in
this mode, an input strobe (IS3) and an output strobe
(OS3), both being used for handshaking. They are
266
$
HITACHI
controlled by I/O Port 3 Control/Status Register.
Additional 3 characteristics of Port 3 are summarized as
follows:
(1)
Port 3 input data can be latched using IS3 (SCI)
as a control signal.
(2)
5Sl (SC 2 ) can be generated by MPU read or write to
Port 3's data register.
(3)
IRQl interrupt can be generated by an YS1 falling
edge.
Port 3 strobe and latch timings are shown in Figs. 5-5 and
5-6, respectively.
I/O Port 3 Control/Status Register
Bit 0 Not used.
Bit 1 Not used.
Bit 2 Not used.
Bit 3 LATCH ENABLE.
Controls the input latch of Port 3.
If the bit is
set, the input data on Port 3 is latched by the
falling edge of IS3.
The latch is cleared by the
MCU read to Port 3; it can be latched again.
Bit 3
is cleared by a reset.
Bit 4
ass
(Output Strobe Select)
Determines the cause of output strobe generation: a
write operation or read operation to I/O Port 3.
When the bit is cleared, the strobe will be generated
by a read operation to Port 3.
When the bit is set,
the strobe will be generated by a write operation.
Bit 4 is cleared by reset.
Bit 5 Not used.
~HITACHI
267
Bit 6 IS3 ENABLE.
If the IS3 flag (bit 7) is set with bit 6 set, an
interrupt is enabled.
Clearing the flag causes the
interrupt to be disabled.
The bit is cleared by reset.
Bit 7 IS3 FLAG.
Bit 7 is a read-only bit which is set by the falling
edge or IS3 (SCI).
It is cleared by a read of the
Control/Status Register followed by a read/write of
I/O Port 3.
The bit is cleared by reset.
(b) Expanded Non Multiplexed Mode (mode 1, 5)
In this mode, Port 3 is configured as data bus.
(c) Expanded Multiplexed Mode (mode 0, 2, 6)
Port 3 is configured as either data bus (Do to 07) or lower
a bits of the address bus (Ao to A7).
An address strobe
output is "High" when the address is on the port.
(4)
Port 4
Port 4 is an a-bit port that becomes either I/O Port or
address bus depending on the operation mode selected.
Each
line is TTL compatible and can drive one TTL load and 90pF
capacitance.
After reset, this port becomes inputs.
To use
Port 4 as address bus, Port 4 pins should be programmed as
outputs.
Function of Port 4 for each mode is explained below.
(a) Single Chip Mode (Mode 7):
Parallel I/O Port, whose I/O
direction is programmed by the Port 4 Data Direction
Register.
(b) Expanded Non Multiplexed Mode (Mode 5):
In this mode,
Port 4 becomes the lower address lines (Ao to A7) by
writing "l"s on the Data Direction Register.
When all of the eight bits are not required as addresses,
~HITACHI
268
the remaining lines can be used as I/O lines (Inputs only).
(c) Expanded Non Multiplexed Mode (Mode 1):
In this mode,
Port 4 becomes output for upper address lines (As to A1S).
(d) Expanded Multiplexed Mode (Mode 0, 2):
In this mode,
Port 4 becomes output for upper address lines (As to A1S)
regardless of the value of Data Direction Register.
The relation between each mode and ports 1 to 4 is
summarized in Table 2-1-2.
2.5
I
Timer
The HD63701VO provides 16-bit programmable timer which can
measure input waveform and generate an output waveform.
The pulse widths of both input/output can vary from microseconds to seconds.
microseconds to many seconds.
The timer hardware consists of
an a-bit Control and Status Register
a 16-bit Free Running Counter
a 16-bit Output Compare Register, and
a 16-bit Input Capture Register
A block diagram of the timer is shown in Figure 2-5-1.
..."
8il1
DO.
r-·- -- - - - _I
ellnp.. ,
~
1_,
~':'O
""'12 """2
Fig. 2-5-1
Programmable Timer Block Diagram
~HITACHI
269
(l)
Free Running Counter (FRC)
($0009:$000A)
The key timer element is a l6-bit Free Running Counter (FRC),
that is driven by E (Enable) clock to increment its values.
The FRC value is readable by software at any time with no
effects on the FRC.
The FRC is cleared during reset.
When writing to the upper byte of the FRC ($09), the CPU
writes the preset value
($FFF8) into the FRC (address $09,
$OA) regardless of the write data. But when writing to
the lower byte ($OA) after the upper byte writing, the
CPU writes not only the lower byte data into lower byte
of the FRC, but also the upper byte data into upper byte
of the FRC.
The FRC value written by the double store instruction is
shown in Figure 2-5-2.
($5AF3 written to ~he counter)
Fig. 2-5-2 Counter Write Timing
*
A write to the counter can disturb serial operations, so it should be inhibited during the SCI
operation.
(2) Output Compare Register (OCR)
(~OOOB:
$OOOC)
The Output Compare Register (OCR) is a l6-bit read/write
register which is used to control an output waveform.
The
data of the OCR is constantly compared with the FRC.
When the data matches, a flag (OCF) in the Timer Controll
Status Register (TCSR) is set and the current value of an
output level Bit (OLVL) in the TCSR is transferred to Port
2 bit 1.
is "1"
When bit 1 of the Port 2 Data Direction Register
(output) the OLVL value will appear on the bit 1 of
Port 2. Then, the value of the OCR and Output level bit
should be changed to control an output level again on the
next compare values.
@HITACHI
270
The OCR is initialized to $FFFF during reset.
The compare
function is inhibited at the cycle of writing to the upper
bytes of the OCR and at the cycle just after that.
It is
also inhibited at the cycle of writing to the Free Running
Counter.
* For the data write to the OCR, 2-byte transfer instructions such as STD, STX should be used.
(3)
Input Capture Register ($OOOD:$OOOE)
The Input Capture Register (ICR) is a l6-bit read-only
I
register used to store the FRC's value when the proper
transition of an external input signal occurs as defined
by the input edge bit (IED1) in the TCSR.
The input transition change required to trigger the
counter transfer is controlled by the input Edge bit
(IEDG) •
To allow the external input signal to gate in the edge
detector, the bit of the Port 2 Data Direction Register
corresponding to bit 0 of Port 2 must have been cleared
(to zero) .
To insure input capture in all cases, the width of an
input pulse requires at least 2 E clock cycles.
(4) Timer Control/Status Register (TCSR)
This is an 8-bit register.
($0008)
All 8 bits are readable and
the lower 5 bits can be written.
The upper 3 bits are
read-only, indicating the timer status information below.
(a) Defined transition of the timer input signal
causes the counter to transfer its data to the
ICR.
(b)
A match has occurred between the value in the FRC
and the OCF.
(c) The counter value reached to $0000 by counting-up (TOF).
@HHTACHI
271
Each of the upper three flags can generate an IRQ2 interrupt
and is controlled by an corresponding enable bit in the
TCSR.
If the I-bit in the CCR has been cleared, a priori-
tized vectored address occurs corresponding to each flag
being set.
Each bit is described as follows.
Timer Control/Status Register (TCSR)
432
765
[!cF
Bit 0
I OCF I TOF
EICI
I EOCI I ETOI
OLVL (Output Level):
0
1
IEDG
I OLVL] $0008
When a match occurs
between the FRC and the OCR, this bit is transferred
to the Port 2 bit 1.
If the DDR corresponding to
Port 2 bit 1 is set to "1", the value will appear on
the output pin of Port 2 bit 1.
Bit 1 IEDG (Input Edge):
This bit control which transition
of Port 2 bit 0 input (P20) will trigger the data
transfer from the FRC to the ICR.
The DDR correspond-
ing to Port 2 bit 0 must be cleared in advance of using
this function.
When IEDG = 0, data transfer is
triggered on a falling edge ("High"-to-"Low" transition)
of P20.
When IEDG
=
1, data transfer is triggered on
a rising edge ("Low"-to-"High" transition) of P20.
Bit 2 ETOI (Enable Timer Overflow Interrupt):
When set,
this bit enables TOF interrupt to generate the interrupt request (IRQ2); when cleared, the interrupt is
inhibited.
Bit 3 EOCI (Enable Output Compare Interrupt):
When set,
this bit enables OCF interrupt to generate the
interrupt request (IRQz); when cleared, the interrupt
is inhibited.
~HITACHI
272
Bit 4 EICI (Enable Input Capture Interrupt): When set,
this bit enables ICF interrupt to generate the
interrupt reguest (IRQ2); when cleared, the interrupt is inhibited.
Bit 5 TOF (Timer Overflow Flag): This read-only bit is
set when the counter value is $0000. It is cleared
by CPU read of TCSR (with TOF set) followed by CPU
read of the counter ($0009).
Bit 6 OCF (Output Compare Flag): This read-only bit is
set when a match occurs between the OCR and the FRC.
I
It is cleared by read of TCSR (with OCF set) followed
by CPU write to the OCR ($OOOB or $OOOC).
Bit 7 ICF (Input Capture Flag): The read-only bit is set
when an input signal to edge detector makes a transition as defined by IEDG. It is cleared by read of
TCSR (with ICF set) followed by CPU read of the ICR
($0000).
Each bit of TCSR is cleared during reset.
2.6
Serial Communication Interface
(SCI)
The HD63701VO contains a full-duplex asynchronous Serial
Communication Interface (SCI). The SCI can select the several
kinds of the data transmit rate and comprises a transmitter
and a receiver which operate independently on each other
but at the same data transmit rate. Both of transmitter
and receiver communicate with the CPU by the data bus, and
with the outside. through Port 2 bit 2,3 and 4. Descriptions of hardware, software, and the SCI registers are
as follows.
(1) Wake-Up Function
In typical multiprocessor applications the software
protocol has the destination address at the initial
byte of the message. The purpose of Wake-Up function
is to have the non-selected MCU ignore the remainder
of the message. Thus the non-selected MCU can inhibit
~HITACHI
273
the all further interrupt process until the next
message begins.
Wake-Up function is triggered by a ten consecutive "l"s
which indicates an idle transmit line.
Therefore soft-
ware protocol needs an idle period between the messages.
With this hardware feature, the non-selected MPU is reenabled (or "wakes-up") for the appearing next message.
(2) Programmable Options
The HD63701VO SCI has the following programmable features.
data format; standard mark/space (NRZ) start bit +
8 bit data + 1 stop bit
Clock source; external or internal
baud rate; one of 4 rates per given MCU E clock frequency
or 1/8 of external clock
• wake-up function; enabled or disabled
• Interrupt requests; enabled or masked individually for
transmitter and receive data
registers
Clock Output; internal clock enabled or disabled to
Port 2 bit 2
• Port 2 (bits 3,4); dedicated or not dedicated to serial
I/O individually for receiver and
transmitter
(3)
SCI Hardware
The SCI hardware is controlled by 4 registers as shown in
Figure 2-6-1.
The registers include:
• an 8-bit Transmit/Receive Control Status Register (TRCSR)
• a 4-bit write-only Transmit Rate/Mode Control Register (RMCR)
• an 8-bit read-only Receive Data Register (RDR)
• an 8-bit write-only Transmit Data Register (TDR)
Besides these 4 registers, the SCI utilizes Port 2 bit
3 (input) and bit 4 (output). Port 2 bit 2 can be used
when an option is selected for the internal-clack-out or
the external-clack-in.
(4) Transmit/Receive Control Status Register (TRCSR)
TRCSR consists of 8 bits which all may be read
@HITACHI
274
while only bits 0 to 4 may be written. The register is
initialized to $20 during RES. The bits of the TRCSR
are defined as follows.
Transmit/Receive Control Status Register (TRCSR)
765
I RDRF I ORFE I TORE
Bit 0
WU (Wake Up):
432
RIE
RE
TIE
1
0
TE
WU
ADOR:
$0011
Set by software and cleared by hard-
ware on receipt of ten consecutive "l"s.
It should be
noted that RE flag has already set in advance of WU
flag's set.
Bit 1
TE (Transmit Enable):
I
Set to produce preamble of
ten consecutive "l"s and to enable the data of transmitter to output subsequently to the Port 2 bit 4
independently of its corresponding ODR value.
When
cleared, the SCI affects nothing on Port 2 bit 4.
Bit 2
TIE (Transmit Interrupt Enable):
When set with
TORE (bit 5) set, an IRQz interrupt is enabled.
When cleared, IRQz interrupt is masked.
Bit 3
RE (Receive Enable):
When set, gates Port 2 bit 3
to input of receiver regardless of DDR value for this
bit.
When cleared, the
SCI affects nothing on Port 2
bit 3.
Bit 4
RIE (Receive Interrupt Enable):
When set with
bit 7 (RDRF) or bit 6 (ORFE) set, IRQ2 interrupt
is enabled.
Bit 5
When cleared, IRQz interrupt is masked.
TORE (Transmit Data Register Empty):
When the data
is transmitted from the Transmit Data Register to
Output Shift Register, it is set by hardware.
The bit
is cleared by reading the TRCSR (with TDRE set)
and followed by writing the next new data into the Transmit
Data Register.
Bit 6
TDRE is initialized to 1 during RES.
ORFE (Over Run Framing Error):
When overrun or
framing error occurs (receive only), it is set by
hardware.
Over Run Error occurs if the attempt is
made to transmit the new byte to the receive data
~HITACHI
275
register with the RDRF still set.
Framing Error occurs
when the bit counters are not synchronized to the
byte boundaries of the bit stream.
The bit is
cleared by reading the TRCSR (with ORFE set)
followed by reading the RDR, or by RES.
Bit 7
It is set by
RDRF (Receive Data Register Full):
hardware when the data is transmitted from the RSR
It is cleared by reading the TRCSR
to the RDR.
(with RDRF set) and followed by reading the RDR,
<;>r by RES.
B,I 1
Rate end Mode Control Regluer
I
Bit 0
I I I I
eel
eeo SSI SSO 1$10
Transmit/Receive Control end Status Register
IRDRFEAFEITDREI AlE
I I I
RE
TIE
TE I WU
1$11
Receive Date Register
$12
Port2
I~~ ~___
I_I____
Clock
Bit
2
~________~A~~~.I~W~S~h;~ft~R~••~;.~t.~,______.J
10
I-----E
k---------------~
.x
~
B't
4
12 _ _ _ _ _ _ _ _
Transmit Data Register
Fig. 2-6-1
6
SCI Register
o
5
eel
eeo
5S1
SSO
AD DR
$0010
Rate I Mode Control Register
Table 2-6-1
SSI
SSO
0
0
SCI Bit Times and Transfer Rates
XTAL
2.4576 MHz
4.0 MHz
E
614.4 kHz
1.0MHz
E.;. 16
26 1',/38,400 Baud
16
1.2288MHz
13
jJ.S /76,800Baud
0
1
E.;. 128
208)J,/4,800 Baud
128 )Js/7812.5 Baud
1
0
E.;. 1024
1.67ms/600 8aud
1.024m,/976.6 Baud
104.2jJ.' / 9,600Baud
833,3jJ.s / 1,200Baud
1
1
E.;. 4096
6.67m,/150 8aud
4.096m,/244.1 Baud
3.333ms /
~HITACHI
276
1',/62,500 Baud
4.9152MHz
300Baud
Table 2-6-2 SCI Format and Clock Source Control
CC1, CCO
10
11
•
Cloc~
Format
00
01
Source
Port 2 Bit 2
Port 2 Bit 3
-
-
-
-
NRZ
NRZ
NRZ
Internal
Not Used •••
Internal
Output*
External
Input
..
..
..
Port 2 Bit 4
-
..
..
..
Clock output is available regardless of values for bits RE and TE .
•• Bit 3 is used for serial input If RE == "1" in TACS.
Bit 4 is used for serial output if TE = "1" in TReS.
con be used as 110 port.
···'t
(5) Transmit Rate/Mode Control Register (RMCR)
Transmit Rate/Mode Control Register
following SCI variables:
·Baud rate
·Port 2 bit 2 function
(RMCR) controls the
·clock source
The RMCR is a 4-bit write-only register, cleared by RES . . The
4 bits are considered as a pair of 2-bit fields.
The lower
2 bits control the bit rate of internal clock while the
upper 2 bits control the clock select logic.
Bit 0 sso
Bit 1 SSl
1
J
Clock Speed Select
These bits select the Baud rate for the internal clock.
The selectable 4 rates are function of E clock frequency
within the MCU.
Table 2-6-1 lists the available Baud
Rates.
Bit 2 CCOI
Bit 3 CCI J Clock Control/Format Select
These bits control the clock select logic.
Table 2-6-2 defines the bit field.
(6) Internally Generated Clock
When using the SCI internal clock for external devices, the
followings should be noted.
The values of RE and TE have no effect •
• CCl, CCO must be set to "10".
The maximum clock rate is E/16.
The clock is equal to the bit rate.
(7) Externally Generated Clock
When supplying an external clock for the SCI, the
followings should be noted.
~HITACHU
277
The CCl, and CCO in the RMCR must be set to "11"
(See Table 2-6-2).
The external clock frequency must be set to 8 times
the desired baud rate.
• The maximum external clock frequency is half of E
clock.
(8) Serial Operations
The SCI hardware must be initialized by the HD6370lVO
software prior to operation. The sequence is normally
as follows.
Writing the desired operation control bits to the RMCR.
Writing the desired operation control bits to the TRCSR.
If using Port 2 bits 3 and 4 for the SCI exclusively, TE and
RE bits may be preserved set. WhenTE and RE bits are cleared
during the SCI operation, and subsequently set again, it
should be noted that the setting of TE, RE must refrain
for at least one bit time of' the current baud rate. If
set within one bit time, internal function for transmit
and receive may not occur.
(9) Transmit Operation
Data transmission is enabled by the TE bit in the TRCSR.
When TE is set, outputs the data of the SCI Transmit Shift
Register to Port 2 bit 4 which is unconditionally configured
as an output irrespectively of the corresponding DDR value.
Following RES, the user should program both the RMCR
and the TRCSR for desired operation.
Setting the TE bit during this procedure causes a transmission of ten-bit preamble of "l"s. Following the
preamble, internal synchronization is established and the
transmitter section is ready to operate. Then either of
the followings operates.
~HITACHI
278
(a) If the TOR is empty (TORE = 1), the consecutive "l"s
are transmitted indicating an idle lines.
(b) If the data has been loaded into the TOR (TORE
0) ,
it is transferred to the Transmit Shift Register and
data transmission begins.
During the data transfer, the "0" start bit is first
transferred.
Next the 8-bit data (beginning at bit 0)
and the "1" stop bit.
When the TOR has been empty, the TORE
flag bit is set.
If the CPU fails to respond to the flag within the
a
proper time, TORE is preserved set and then a "1" will
be sent (instead of a "0" at start bit time) consecutively
until the data is supplied to the Transmit Oata
Register. While the TORE remains a "1", no "0"
will be sent.
(10) Receive Operation
The receive operation is enabled by the RE bit.
serial input is connected with Port 2 bit 3.
The
The receive
operation is determined by the contents of the TRCSR RMCR.
The received bit stream is synchronized by the first "0"
(space). During 10-bit time, the data is strobed
approximately at the center of each bit.
If the tenth bit is not "1" (stop bit), the system
assumes a framing error and the ORFE is set.
(RDRF is
not set.)
If the tenth bit is "1", the data is transferred to the
RDR, with the interrupt flag set (RDRF).
If the tenth bit
of the next data is received, however, still RORF is preserved
set, then ORFE is set indicating that an overrun error has
occurred.
After the CPU read of the TRCSR as a response to RDRF flag
or ORFE flag followed by the CPU read of the ROR, RDRF or
ORFE will be cleared.
(11) Timer, SCI Status Flag
The set and reset condition of each status flag of timer
and SCI is shown in Table 2-6-3.
~HITACHI
279
Table 2-6-3 Timer and SCI Status Flag
Status Flag
Set Condition
Reset Condition
ICF
FRC + ICR by edge input to
OCF
OCR=FRC
l.
2.
RES=O
TOF
FRC=$FFFF+l cycle
l.
Read the TCSR then FRCH,
when TOF=l
2.
RES=O
l.
Read the TRCSR then RDR,
when RDRF=l
Read the TCSR then ICRH,
when ICF=l
RES=O
l.
P20.
2.
Read the TCSR then write to
the OCRH or OCRL, when
OCF=l
Timer
RDRF
Receive Shift Register + RDR
ORFE
l.
rnT
2.
RES=O
Framing Error (Async hronous
Mode)
Stop Bit = 0
Ov~rrun Error (Asynchronous
Mode)
Receive Shift Register +
RDR when RDRF=l
l.
Read the TRCSR then RDR,
when ORFE=l
?,
RES=O
l.
TDR + Transmit Shift
Register
Read the TRCSR then write to
the TDR, when TDRE=l
2.
RES=O
2.
TDRE
The receive margin of the HD63701VO SCI is shown below.
START
Ideal
Waveform
1
I
2
3
4
5
6
7
8
STOP
Bit length
~Character
length
TO------------------~.~I
Real
Waveform
~-----------------T--------------------~
Bit distortion tolerance
(t-to) Ito
Character distortion tolerance
{T-To)/To
±3 7.5%
+3.75%
-2.5%
~HITACHI
280
2.7
Interrupts
The HD63701VO has two external interrupt terminals (NMI, IRQ1)
and 8 internal interrupt sources (Soft-TRAP, SWI, Timer-ICF,
OCF, TOF, SCI-RDRF, ORFE, TDRE).
The features of these
interrupt are detailed in the following paragraphs.
(1) Non maskable Interrupt (NMI)
When the high-to low transition of NMI is detected, NMI
acknowledge sequence starts. The current instruction is
completed if NMI signal is detected as well as the following IRQl interrupt.
Interrupt mask bit in the Condition Code
Register has no effect on NMI interrupt.
In response to NMI
interrupt, the contents of Program Counter, Index Register
I
Accumulators, and Condition Code Register are pushed onto the
stack.
On completion of this sequence, the CPU generates
vecotr addresses $FFFC and $FFFD, and loads the contents
into the Program Counter and branch to a non maskable
interrupt service routine.
(2) Interrupt Request (IRQ1)
IROl is the level-sensitive pin which requests an IRO,
interrupt to the CPU.
When IRQl interrupt request occurs,
the: CPU will complete the current instruction before the
acceptance of the request.
If the I bit of the Condition
Code Register is cleared, the CPU starts an interrupt
acknowledge sequence; if set, the interrupt request will be
ignored.
When the IRQl acknowledge sequence starts, the contents of
Program Counter, Index Register, Accumulator, and Condition
Code Register are pushed onto the stack.
Then the CPU sets
the I bit to ignore another IRQl or IRQ2 interrupt request.
At the end of the cycle, the CPU generates l6-bit vector
addresses $FFFB and $FFF9, and loads the contents into the
Program Counter to branch to an interrupt service routine.
~HITACHI
281
(3) Internal interrupts (IRQ2)
When an internal interrupt is requested from the timer or
SCI, an internal interrupt signal IRQ2 is activated.
This
interrupt is identical to IRQl except that it uses vector
addresses $FFFO through $F~F7. The IRQl has the priority
to the IRQ2 when interrupt requests occurs at the same time.
When the interrupt mask bit in the condition code register is
set, both interrupts are inhibited.
The SWI is an instruction which requests an interrupt by
software.
the SWI.
The state of CCR mask bit doesn't influence
If an address error or op-code error
(see "2.13 Error Processing") occurs, TRAP occurs
whose priority is next to the reset.
In the case of
TRAP, CPU starts the interrupt sequence reqardless of the
state of the mask bit.
are $FFFE and $FFEF.
The vector for the TRAP interrupt
The interrupt sources and their
corresponding vector are listed in Table 2-7-1 and the
interrupt sequence are shown in Fig. 2-7-1.
Fig. 2-7-2
shows the interrupt generation circuit.
Table 2-7-1
Interrupt Vector
Vector
Highest
Priority
Lowest
Priority
Lower
Upper
Byte
Byte
Interrupt Source
FFFE
FFFF
RES
FFEE
FFEF
TRAP
FFFC
FFFD
NMI
Software Interrupt (SWI)
FFFA
FFFB
FFF8
FFF9
FFF6
FFF7
ICF (Timer Input Capture)
FFF4
FFFS
OCF (Timer Output Compare)
FFF2
FFF3
TOF (Timer Overflow)
FFFO
FFFI
SCI (RDRF+ORFE+TDRE)
IRQl
~HITACHI
282
(or IS3)
Interrupt
Test
Intern.1
Addr~~--
__~-r~~~~~~~~~~~~~~~~h_
__
~~
__ __ ____ __ ___J'-__ __
~
~
~
~
~
~~
NMI. IRQ,. IRQJ
Intern.1
D.t.&n ----v--'r---v--,r--v--'"....---v----Ir"--"""----..,...--"""----..,...---v--,~--_v----..,...
____ __
__
__
__
___ J ' ___
____h___
____h___
____h___
__
__
____
~
_J~
~
~~
~
~
PC8PC1S
Intern.1
Reod
~
IXOIX7
IX8IX15
~
ACCA
Acca
~
I
Internel
Write
~'_
~
~
CCA
\
Fig. 2-7-1
Interrupt Sequence
I
ICI
ICF
EICI
OCI
IlceR bit 5)
TOF
ETO'
RORF
ORFE
Interrupt
Request
Signal
RIE
TORE
TIE
iS3
FLAG
IRQ,
IRQ I
Sleep
Release
Signal
NMI
NMI
TRAP
SWI-----------------------------------------J
Fig. 2-7-2
2.8
Interrupt Generation Circuit
Reset (RES)
This input is used to reset the MCU and start it from a
power-off condition.
During Power-on, RES pin must be
held "Low" for at least 20ms.
To reset the MCU during
system operation, RES must be held "Low" for at least 3
system
clock cycles.
All address buses become "High
impedance" state while RES is "Low". When RES is brought
"high" again, the MCU operates as followings.
@HRTACHI
283
(1)
Latch I/O Port 2 bits 2, 1, and a into bits PC2, PC1,
and pca of the Port 2 Data Register.
(2)
Load the contents (=start address) of the last two
addresses ($FFFE, $FFFF) into the program counter
and start the program from this address.
(Refer to
Table 2-7-1)
(3)
Set the interrupt mask bit. For the CPU to
recognize the maskable interrupts IRQl and IRQz, this
bit should be cleared in advance. Fig. 2-8-1 shows
the reset timing, and Table 2-8-1 shows the pin condition during reset.
When RES is asserted "Low", all I/O pins enters into
reset mode (high impedance state) asynchronously to the
E clock while the MCU enters into the reset mode
synchronously to the E clock.
Both the MCU and I/O pins recover from reset mode
synchronously
to the E clock.
:;'...... _~\\\\'Wl\\\\\\\\\\\\\\\
'>---v---\
'~~~l---------
...
:;'.' -~\\\\\\\\\\\\\\\\\\\\\\
:~~I
~1II:J~I$~tllMl~~m~MmI~II~'~----------------'~~r;---------
Fig. 2-8-J
Reset Timing
~HITACHI
284
Table 2-8-1
~
0
Pin
Port 1
PIO""P17
port 2
P2 O"'P2 It
Port 3
P30"'P3'
Port 4
Pit O"'PIt 7
2.9
High impedance
(input)
High impedance
(input)
E:"l" output
E:"l" output
(High impedance)
High impedance
(input)
SC2
"1" output (READ)
SC,
E:"l" output I
E : High impedance
Pin Condition during RESET
2
1
.
.
5
..
..
.
.
E: "1'1 output
High impedance E:"l" output
(High impedance)
of
..
.
..
•
..
6
.
..
E:"l" output
High impedance E:"l" output
(High impedance)
..
..
.
..
"1" output
E: "1" output
E: High impedance
7
..
.
High impedance
(input)
.
"1" output
High impedance
(input)
I
Oscillator
XTAL and EXTAL pins interface with either an AT-cut parallel
resonant crystal or external clock.
The on-chip divide-by-
four circuit internally divides the input frequency by four
to produce the system clock.
For example, 4MHz of a crystal
or external clock input corresponds to lMHz of system clock.
When using a crystal, a 10-22 pF ± 20% capacitor should be
tied from each crystal pin to ground.
Alternately, EXTAL
can be driven by external clock with 45% to 55% duty cycle.
When external clock is input to EXTAL, XTAL should be left
open.
Fig. 2-9-1 shows an example of crystal interface and crystal
spec if ica tion.
~HITACHI
285
AT Cut Parallel Resonance Crvstal
Co
R,
= 7 pF max
= 60!l max
XTAL
ck
C LI • C L2 -10-22pF ± 20%
13.2-SMHzl
T
EXTAL
lCL2 -
Cll
J;Jr
Fig. 2-9-1
2.10
Crystal Interface
Strobe Signals
Two pins, SCl (39 pin) and Se2 (38 pin) are used as
the strobe signals in each mode. Followings are applied
only to Port 3 in single chip mode.
(1) Input Strobe (IS3)
(SCI)
This signal controls IS3 interrupt and the latch of Port 3.
When the falling edge of this signal is detected, the IS3
flag of Port 3 Control Status Register is set.
For respective bits of Port 3 Control Status Register,
see the "2.4 Ports" section.
(2) Output Strobe (OS3) (SC2)
This signal is used by the processor to strobe an external
device, indicating effective data is on the I/O pins.
The timing chart for Output Strobe are shown in figure 6-5.
The following pins are available for Expanded Modes.
(3) Read/Write (R/W)
(SC2)
This TTL compatible output signal indicates peripheral
and memory devices whether the CPU is in Read ("High"),
or in Write ("Low").
The normal stand-by state of this
signal is Read ("High").
This output can drive one TTL
load and 90pF capacitance.
(4) I/O Strobe (lOS) (SCI)
In expanded non multiplexed mode 5 lOS
becomes "Low" when A9 through A1S are "O"s and As is
"1". This allows external device access located in $0100
through $OlFF in memory.
The timing chart is shown in
Figure 6-2.
~HITACHI
286
(5) Address Strobe (AS)
(SCI)
In the expanded multiplexed mode, address strobe
is output to this pin.
This signal is used to latch the J.',
lower 8 bits addresses multiplexed with data at Port 3.
The 8-bit latch is controlled by address strobe as shown in
Figure 2-1-4.
Thereby, I/O Port 3 can functions as data
bus while E is "high".
The timing chart of this signal is
shown in Figure 6-1.
2.11
RAM Control Register
The register located in the memory address $0014 gives a status
I
information about standby RAM.
RAM Control Register
7
$0014
Bit
Bit
Bit
Bit
Bit
Bit
6
5
4
3
2
STBY
PWR
1
o
x
x
0 Not used.
1
2
3
4
5
Not
Not
Not
Not
Not
used.
used.
used.
used.
used.
Bit 6 RAM Enable.
Using this control bit, the user can disable the RAM.
RAME bit is set on the positive edge of RES and RAM is
enabled.
RAME can be program to "1" or "0".
If RAME
is cleared (logic "0"), any access to a RAM address is
external.
Bit 7 Standby Bit
This bit is cleared when VCC is not provided in standby
ca~
mode.
This bit is a read/write status flag that user
read.
If this bit is preserved set, indicating that VCC
voltage is applied and the data in the standby RAM is valid.
2.12
Low Power Consumption Mode
The HD6370lVO has two low power consumption modes; sleep
and standby.
~HITACHI
287
(1) Sleep Mode
On execution of SLP instruction, the CPU is brought to
the sleep mode.
In the sleep mode, the CPU stops its
operation, but the contents of the register in the CPU
are retained. In this mode, on-chip peripherals such as
the SCI and Timer continue their operations.
In this mode,
the power consumption is one-sixth that of normal operation
mode.
The MCU returns from this mode by interrupt, RES, or STBY.
The RES resets the MCU and the STBY brings it into the
standby mode (This will be mentioned later).
When the
CPU acknowledges an interrupt request, it cancels the
sleep mode, returns to the operation mode and branches
to the interrupt routine.
When the CPU masks the
interrupt, it cancels the sleep mode and executes the
next instruction.
However, for example, if the timer
1 or 2 prohibits a timer interrupt, the CPU doesn't
cancel the sleep mode because of no interrupt request.
The sleep mode is available to reduce the power consumption for a system with no need of the HD63701VO's
consecutive operation.
Please refer to Table 2-12-1 for other pins except VCC,
clock pin, input-only pin, E clock pin (their function
are the same as normal operating condition) .
(2) Standby Mode
The HD63701VO stops all the clocks and goes into the
reset state with STBY "LoW".
In this mode, the power
consumption is reduced conspicuously.
In the standby mode, the power is supplied to the
HD63701VO, so the contents of RAM are retained.
The
MCU returns from the standby mode by bringing STBY "High"
and restarts execution at the same restart address as reset.
If external clock is used during standby mode, EXTAL
must be brought "High" not increase standby current by
5-10~A.
If the increase of standby current does not
~HITACHI
288
affect the MCU, EXTAL can be held either "Low" or "High".
Transitions among the active mode, sleep mode, standby mode
and reset are shown in Fig. 2-12-2.
::-----,,-:e
Table 2-12-1
Pin Condition in Sleep Mode
5
2
1
0
Pin
Function
I/O Port
Port 1
Lower Address
Bus
I/O Port
Output "1"
Keep the condition just
before sleep
Keep the con-
P lO"P1?
Condition dition just
before sleep
Function
Port 2
r/o Port
..
Keep the con-
P2.0""P2lj
Condition dition just
before sleep
Function
Port 3
~30"'P37
E:Lower
Address Bus Data Bus
E:Data Bus
E:Output "1
Condition E :High impedance
11
Function
CI
Upper Address
Port 4
PlfO",p,,?
.,
-
E:Lower
Address Bus
--- -
dance
•
SC2
Output "1"
(Read Condition)
SCi
Output Address Strobe
.
.
..
oil
CI
..
•
---
----
7
..
I
•
..
.
E:Lower
Data Bus
E : Data Bus
E :OutP1.tt '11"
High impedance E : High impe-
Condition Output "1"
•
6
Address Bus
E:Data Bus
E:Output "1"
High impedance E:High impedance
Lower Address
Upper Address
Bus or Input
Port
Bus or Input
Port
I/O Port
Keep the condition just
before sleep
I/O Port
Address Bus:
Output "I"
Port: Keep the
condition
just before
sleep
.
Output "1"
•
Keep the condition just
before sleep
.
Output "1"
Output Address Strobe
Input Pin
~HITACHI
289
~
o
Internal
E clock
~
:I
t
/
Stop in sleep
mode clock
~
(')
Address
bus
:I
Data
bus
Sleep cleared
n
n+
FFFF FFFF
+
L.J~1---
PCn-l
PCn
PCn+l
PCn+2
PCn+3
1----J
SLP
OPn+l
OPn+2
OPn+3
Sleep is recovered
with interrupt
masked
~l-- ~2
I
Sleep
instruction
-
n+2
I Interrupt
~
Interrupt
occurs
Address - PC + PC +2 FF
bus where
sleep is
cleared without
interrupt masked
Program
Fig. 2-12-1 Sleep Instruction Timing Chart
SP
save routine
SP-
I
Fig. 2-12-2 Transitions among Active Mode, Standby Mode
Sleep Mode, and Reset
~HITACHI
291
2.13
TRAP Function
The CPU generates a TRAP interrupt with the highest priority
when fetching an undefined op-code or an instruction from non-memory space. The TRAP prevents the systemburst caused by noise or a program error.
(1) Op-Code Error
When fetching an undefined op-code, the CPU saves register
as well as a normal interrupt and branches to the TRAP service
routine (vector address=$FFEE, $FFEF). This has the priority
next to reset.
(2) Address Error
When an instruction is fetched from excluding internal
ROM, RAM, or an external memory area, the MCU qenerates
a TRAP interrupt as op-code error. If the instruction
is fetched from external memory area without memory devices,
this function is not applicable.
Table 2-13-1 shows addresses where an address error occurs
to each mode. This function is available only for the
instruction fetch, and is not applicable to the normal
data read/write.
Table 2-13-1
Mode
Address
Address Applicable to Address Errors
0
$0000
1
$0000
2
5
6
$0000
$0000
I
$0000
I
I
$OOlF
$OOlF
I
$OOlF
~007F
0200
I
$EFFF
~HITACHI
292
I
$OOlF
7
$0000
I
:007F
0100
I
$EFFF
3.
EPROM (PROM) PROGRAMMING AND TECHNICAL SPECIFICATIONS
3.1
PROM Mode
In PROM mode, on-chip EPROM can be programmed while other MCU functions
stop operating.
The HD63701VO can be configured in the PROM mode by connecting P20 to Vee, P21 to VSS' P22 to GND, XTAL, STBY and NMI to GND,
and EXTAL to Vee respectively.
See Figure 3-2.
The on-chip EPROM can be programmed and read in the same way
as the 27256.
Therefore, general purpose PROM programmer can
perform programming the on-chip PROM.
I
At this time, a
socket adaptor which changes the number of pins from 40-pin
to 28-pin is necessary.
Note that the address range must be
$0000 through $OOFF because the on-chip EPROM is 4k bytes.
Fill
remainder of EPROM area with FFFF for PROM programmer to correctly
verify.
The Memory map in PROM mode is shown in Figure 3-3.
GND
1
40
NC
GND
2
39
NC
Vee
3
38
NC
GND
4
37
00
A9
5
36
01
VPP
6
35
02
EXTAL
GND
7
34
03
P20
Vee
8
33
O.
P2l
Vee
9
32
05
31
OG
30
07
NC 12
29
Aa
AO 13
28
Al.
Al 14
27
A10
A2 15
26
All
A3 16
25
A12
17
24
Al3
As 18
23
OE
A6 19
22
CE
A7 20
21
Vee
GND 10
NC II
A"
Fig. 3-1
Vee
HD63701VO
Vee
Port 3 PROM
HD63701VO
MCU
Data 00 '" 07
Ae/ p 40
l"~
Address
Port 1
PROM
Address
(Ao '\,A7)
HD63701VO Pin Assignment
in PROM Mode
h
Control Line
(OE. CEI
Fig. 3-2 Symbolical Pin Configuration
in PROM Mode
~HITACHI
293
I
MCU mode
HD63701VO
PROM Mode
I
PROM Mode
"1 "
*NOTE
- - - - __ J
*NOTE:
$7FFF
If an address in this
area is read in PROM
mode, it is always
read as $FF.
Fig. 3-3 Memory Map in PROM Mode
3.2
Programming/Verification
The on-chip EPROM can be programmed in high speed programming scheme,
which allows the on-chip EPROM to be programmed effectively without
damaging the device by voltage and provides high reliability.
The basic programming flow is shown in Figure 3-4.
~HITACHI
294
SET PROG. /VERIFY MODE
Vpp=12.5±O.3V, VCC =6.0::0.25V
Address+l + Address
NO
5=25
Vcc =5.0±O.SV Vpp=Vcc ±O.6V
FAIL
OOGO
Fig. 3-4 Programming Flow
Table 3-1
00
07
CE
OE
Vpp
Read
L
L
Vee
D out
Output Disable
L
H
Vee
High Z
L
H
Vpp
D in
H
L
Vpp
D out
H
H
Vpp
High Z
_Pin
Mode
High performance Program
Verify
Program Inhibit
3.3
Mode Selection
'V
Erasure (with window package type)
The EPROM is erased by exposing an LSI to ultraviolet light.
All erased bits are in the "1" state.
The conditions for erasing are:
ultraviolet light with wavelength
of 2573A, and a minimum irradiation of 15W·sec/cm 2 .
These condi-
tions are satisfied by exposing the LSI to an ultraviolet lamp
rated at 12,000~w/cm2 for 20 minutes, at a distance of about one
~HITACHI
295
inch.
Dust of the cap must be removed by a solvent which does not
damage the package, because the dust reduces the transmittance of
the ultraviolet light.
3.4
On-chip .PROM Characteristics and Application
(1)
Principles of programming/erasure
The HD63701VO's memory cells are the same as the EPROM's.
Therefore, they are programmed by applying high voltage to
control gates and drains, which injects hot electrons into
the floating gate.
The condensed electrons in the floating
gate are stable, surrounded by an energy barrier of Si02
film, and the proper bit becomes "0" due to the memory
threshold voltage change.
Electrons in memory devices decrease as time goes by.
This is caused by the following:
CD
Ultraviolet light, discharged by photo emitting
electrons (erasure principle) ;
(2) Heat, discharged by thermal emitting electrons;
CD
High voltage; discharged by a high electric field,
control gate or drain.
If the oxide film covering a floating gate is defective,
the erasure becomes great.
Normally electron erasing
does not occur because defective devices are removed.
The proper bit for a memory device whose floating gate
does not condense electrons is "1".
~HITACHI
296
.
S~02
~ Control Gate
I
~
le3'::*.x;*W~"
/
Source
.
Control
Gate
Si02
Floa t~ng Gate
----
Gate
Drain
Programming ( "0")
Erasure ("1")
Fig. 3-5 Cross Section of EPROM Memory Cell
(2)
I
Precautions on programming
The higher the program voltage VPP or the longer program
pulse width (tpW)' better the programming because many
electrons flow.
However, data should be programmed
under specific'j voltage and timing conditions.
If over-
voltage is applied to Vpp , the p-n junction may be
damaged and permanent damage may occur.
Pay particularly
attention to PROM programmer overshoot.
Minus voltage
noise causes a parasitic transistor effect, which may
cause apparent breakdown voltage.
The HD63701VO is connected electrically to the PROM
programmer through a socket adapter, so also pay attention
to the followings:
G)
Confirm before programming that the socket adapter
is firmly fixed on the PROM writer.
GD
Do not touch the socket adapter or the LSI during
programming because writing malfunction may occur
from bad contacts.
~HITACHI
297
(3)
Precautions for using the window package type after
programming
(NOTES)
Q)
Transient current may cause permanent damage to the device
if the socket adaptor and the device are not installed in
the PROM programmer correctly.
Care must be taken to install the socket adaptor and the
device in the PROM programmer correctly before programming
the PROM.
QD
Note that the HD6370lVO programming voltage VPP must be
l2.5V, not 2lV.
If the VPP is set to 2lV, it may cause
permanent damage to the device.
Select the Intel 27256
mode in the PROM programmer to apply l2.5V to the Vpp.
(a) Glass window for erasure
If the glass window comes in contact with plastic or
something else with a statick charge, the LSI may
malfunction due to electrostatic charge on the surface
of the window.
If this occurs, exposing the LSI to ultraviolet light
for a few minutes neutralizes the charge and restores
it to normal function.
However, charge weight
stored in the floating gate decreases at the same
time, so re-programming is recommended.
Electrostatic charge buildup on the window is a fundamental
cause of malfunction.
Measurement for its prevention are
the same as those for preventing electrostatic break-down:
CD
Operators should be grounded when handling
equipment.
GD
CD
Do not rub the glass window with plastics.
Be careful of coolant sprays, which may
include a few ions.
~ The ultraviolet shading label (which includes
conductive material) is effective for
neutralizing the charge.
~HITACHI
298
(b) Precautions after programming the EPROM
If the device is exposed to fluorescent light or sun
light, its memory contents may be reversed because
they include a small quantity of ultraviolet light.
In strong light the MCU may malfunction under the
influence of photo-current.
To prevent these
problems, it is recommended that the device be used
with the glass window for erasure covered with the
ultraviolet shading label after programming.
A special label is on the market for this purpose.
Labels made with metal are effective because they
I
absorb ultraviolet light.
Note the following when selecting a shading label.
G)
Adhesion (mechanical intenSity) ---- Adhesion
is reduced with re-use or dust.
When peeling
the label, static electricity may occur.
As a
result, erasure and rewriting by ultraviolet
light are recommended after peeling.
(Sticking
a new label above the old one can be done to
change labels.)
GD
Allowable temperature range ---- The allowable
temperature range and environment temperature of
the shading label should be noted.
If it is
used under conditions exceeding this range, the
paste may stiffen or adhere to the label, causing paste to remain on the window after peeling.
GD
Moisture resistance ---- The allowable moisture
range and environment conditions of the label
should be noted.
It is difficult to find a
shade label applicable to all allowable environmental conditions of the MCU.
The proper label
should be selected depending on use.
~HITACHI
299
3.5
INSTRUCTION SET OVERVIEW
Besides having object code compatible with the HD6801 series,
the HD63701VO adds 6 new instructions; enhances bit control
instructions (AIM, ElM, aIM, TIM), index/accumulator exchange
instruction (XGDX), and sleep instruction (SLP).
These new
instructions improve programming efficiency.
3 .6
Address ing Modes
The HD63701VO provides seven addressing modes. The adequate
selection of these addressing mode will permit to implement
an efficient and easy programming.
The addressing mode is determined by an instruction type and
code.
The addressing mode for each instruction is shown in
Table 3-7 to 3-7-4 with execution time counted by the machine
cycles. When the clock frequency is 4 MHz, the machine cycle time
will be microseconds.
(1)
Accumulator (ACCX) Addressing
Operand is contained in either accumulator A or B.
(2)
Immediate Addressing
Operand is contained in the second byte of the instruction
except LDS and LDX which contain operand in the second
and the third bytes.
These are two or three-byte
instruc tions.
(3) Direct Addressing
The second byte of an instruction contains an effective
address of operand.
256 byte area $0 through $255
can be addressed directly.
Execution times can be
reduced by storing operand in these locations.
In
configurating system, it is recommended that these locations
should be RAM for users' data area.
These are two-byte
instructions, while the AIM, aIM, ElM and TIM are threebyte instructions.
~HITACHI
300
(4)
Extended Addressing
The second and third bytes of the instruction contain
the effective address of the operand.
These are
three-byte instructions.
(5) Indexed Addressing
The effective address of the operand is the sum of the
contents of the second byte and the lower byte of the Index
Register.
As for AIM, OIM, ElM and TIM instructions, the
effective address is calculated by adding the contents of
the third byte and the lower byte of the Index Register.
The effective address is held in the Temporary Address
Register, so the contents of the Index Register is not changed.
These are two-byte instructions, while AIM, OIM, ElM and
TIM are three-byte.
(6) Implied Addressing
The instruction itself gives the address.
That is, the instruction addresses an Accumulator,
Stack Pointer, Index Register, etc. This is a one-byte
instruction.
(7) Relative Addressing
Relative addressing mode is only used in branch instructions.
The branch address is calculated by adding the
contents of the second byte and the lower byte of the Program
Counter.
At this time, a carry or borrow is added to the
upper byte of the Program Counter.
The span of relative
addressing is from -126 to +129 from the op-code address.
These are two-byte instructions.
~HITACHI
301
3.7
Instruction Set
The HD63701VO has an upward object code compatible with the
HD6801 to utilize all instruction sets of the HMCS6800.
The execution time of the key instruction is reduced to
increase the system through-put.
In addition, the bit
manipulation instruction, the exchange instruction of the
index and the accumulator, the sleep instruction are added.
The followings are described here.
• Accumulator and memory manipulation instructions (See
Table 3-7).
Additional instructions.
• Index register and stack manipulation instructions (See
Table 3-7-2).
• Jump and branch instructions
(See Table 3-7-3).
• Condition code register manipulation instructions (See
Table 3-7-4).
• Op-code map (See Table 3-7-5).
~HITACHI
302
Table 3-7
Accumulato~
Memory Manipulation Instructions
Condition Cod_
Addressing Modes
Oper'tions
Add
Mnemonic
OIRECr-T-iNOEX
IMMEO
-
OP
-• -
# OP
AOOA
88
2 2 9B
2 AB 4
AOOB
C8
2 2 08 J
CJ
3 3 OJ
OP
J
2
EB
4 2 E3
A.gistt,
EXTEND
Bool .. nl
IMPLIED
Arithmetic Oper.tion
OP
-
#
2 88
4
J
A+M- A
FB
4 J
8+M-O
2 FJ
5 3
•
4 2
OP
-•
A: B + M: M+l-A:8
Add Doabl,
AOOO
Add Accumulators
ABA
Add Wi.n Carry
AOCA
89
2 2 99
J
2
A9
4
2 B9
4 3
A+M+C-A
AOCB
C9
2 2
09
J
2
E9
4
2 F9
4
8+M+C-B
AND
ANOA
84
2 2 94
J
2
A4
4
4 J
AN DB
C4
2 2 04
J
2
E4
4
2 B4
2 F4
Bit Tilt
81TA
B5
2 2 95
3
2
A5
4
4 J
A·M
BIT B
C5
2 2 05
3
2 E5
4
2 B5
2 F5
4 3
8·M
5 2 7F
5 3
oo-M
CI.1f'
Compl'.
Compar.
Aecumul.tors
Compliment, t',
5
IB
6F
CLR
4
J
A·M-A
8·M-8
J
CLRA
4F
CLR8
5F
4
3
4
2 81
2 FI
4
3
8-M
6
2 73
6
3
6
2 70
81
2 2 91
3
2
AI
4
CMPB
Cl
2 2 01
3 .2
El
63
CeA
11
53
1
A-8
I 1 A -A
1 1 8 -8
OO-M-M
NEG
tNogotl)
NEGA
NEGB
40
1 1 00 - A- A
50
Oed",,! Adjust. A
OAA
19
1 1 00-8-8
Converts bln.ry 8dd of BCD
2 1 characters into BCD format
Decrement
DEC
OECA
4A
I
OECB
5A
I
ExcluliYII OR
Increment
2 2 98
3
2
AS
4
A (!I M-A
2 2 08
3
2 E8
4
B (!IM- B
INC
1 1 A + 1 .... A
INCB
5C
I
3
2 A6 4 2 B6 4 3
M....,A
C6
2 2 06
3
2 E6
CC
3 3 OC 4 2
4
EC 5
4 3
M-B
5 3
M + 1 ..... B. M- A
3D
MUL
OR, IncluliYII
ORAA
8A
ORAB
CA 2 2 OA 3
2
2 9A
3 2
AA 4
2 EA 4
2 8A 4
2 FA 4
7 1 AxB-A:B
3
A+M-A
3
B + M- B
37
4
4
PULA
32
3
1 B - Mil>. SP - 1 - SP
1 SP+l-SP,MtP- A
PULB
33
3
1 SP+l-SP.M.. -B
ROLA
49
ROLS
59
1
1 1
ROR
RORA
RORS
66
6
6
2 79
2 76
6 3
I
6 3
46
I
1
56
1
1
Note) Condition Code Register will be
explained in Note of Table 3-7-4.
I
I
I
I
I
I
I
I
I
I
:
I
I
I
I
I
I
R
I
I
R
I
I
I
R
I
I
I
I
F.
I
I
··
•
R
··
•
R
•
R
I
0
0
S R R
S R R
S R R
I
I
I
I
I
I
I
I
I
I
I
R S
I
I
I
I
I
I
I
R S
I
I Ii)
I
I
(i) t}J
I
I
I (j)
I
I
@ •
I
I
I
@ •
I
I
R S
(i)~
:~
I (4) 0
I R
I R
I @ •
I
I
I
I
I
I
R
@ •
I
I
R
I
I
R
I
I
I
R
I
R
I
I
@ I
I
I
I
I
• ®
1 A .... Map. SP - 1 .... SP
36
PSHB
69
I
1 0
I
I
I
I
0
PSHA
ROL
I
I
I
FC
2
I
I
2 F6
2
··
· ··
··
·· ··
·· ··
J
I
0
1 B + 1- B
2 2 96
B6
I N Z V C
0
M+l-M
4C
Multiply Unsigned
Rotl" Right
2 88 4 3
2 F8 4 3
6C 6 2 7C 6 3
INCA
LOO
Rotlt. Left
1 A-I - A
1 8 - l-B
C8
LOAS
Pul) O.t.
M-l -M
3
88
Accumulator
Push D,tl
6
EOR8
LOAA
Accumulator
7A
EORA
L_
L_Ooublo
6 2
3
H
··
·· ·
·· ··
··· ···
·· ··
····
···· ·
······ '" ·.
···· ·
··· ··· · · ··
·· ··· · · · ···
·· ·· ·· ·· ·· ··
· · · ···
U; ·· ··
··
P ··
····
ComplIment. 2"
SA
6
I
4
I
M-M
43
COMB
60
1 1 00- A
1 1 00-8
A-M
CMPA
COM
COMA
1 1 A + 8- A
5
:1 ~.J I I I I
=} 4i1' ,,
I I I I
8
b1
bO
I
I
(<<> I
CIl I
I @ I
I (4) I
I "i) I
I
ho be continued)
~HITACHI
303
Table
3-7-1
Accumulato~
I
I
Operations
Memory Manipulation Instructions
Condition Code
Addressing Modes
Mnemonic
f-;"MMEo
oP
Shih Left
ASl
Arithmetic
ASlA
- ..
10lAECT
OP
- ..
INDEX
Register
EXTEND
OP
- . - .. -
68
6
OP
OP
2
78
6
Double Shih
~thmetic
ASlo
Arithmetic Operation
M\
_
I(111111111--0
48
58
1 1
05
1 1 ~
1 1
A
•
b7
2 77
Shift Right
ASA
Arithmetic
ASAA
47
1 1
ASA8
57
1 1
1 1
lSAB
44
54
1 1
lSAo
04
1 1 0....(
64
lSA
Shift Right
Logial
6
6
2 74
6
6
3
-
_S!~
STA8
Store
Accumulator
2
E7
4
2 F7
4
3
2
ED 5
2 Fo 5
3
A_M
B _ M+ 1
AO
4
2 80
4
3
A-M _A
2 EO
4
2
FO
4
3
8 -M_8
2
5 2 83
2
80
2 2 90
SU88
CO
83
2 2 DO 3
3 3 93 4
3
A3
Doubl. Subtract
SU80
SubtrKt
Accumulators
SOA
Subtract
With ear,v
S8CA
82
2 2 92
3
A2
4
S8C8
C2
2 2 02
3 2 E2
4
I--
Tr.nsf.,
Accumulators
TA8
T8A
Test Zero or
TST
Minus
~
ACCA~ .~cc II 80~
'7
A-M
8_M
3
SUBA
-
3
2
A: 8
5 3
10
2
2 82
2 F2
3
A-M-C-A
4
3
8 -M-C-8
16
60
-'41: M+l-A:
1 1 A -8- A
4
17
4 2 70 4
1 1 A- 8
1 1 8- A
M -00
3
TSTA
40
1
1 A cOO
TST8
50
1
1 8 - 00
And Immediate
AIM
OR Immec:fiate
M·IMM-M
OIM
7 3
72 6 3 62 7 3
EOR Immediate
ElM
75
6
3 65
7
3
MllIMM_M
Test Immediate
TIM
78
4
3 68
5
3
M·IMM
Note)
71
6
3 61
K;l
bO
Alo..j
• .7I IIIIIU~
4
07
Subtract
b7
2 81
DO 4
STo
CCI I I I I I I
A
II
4
3
Store Double
Accumulator
_
A7
97
Ace' 801-0
AO .7
M
3
lSAA
Double Shih
Right logical
MI
bO
Ace;y
11.7
67
5
H
It
3
ASlB
Boole.nl
IMPLIED
M+IMM-M
I
0
I N Z V
C
4
3
2
·· ··
·· ··
··· ···
·· ··
··· ··· ·
·· ·· ··
·· ··
·· ··
··· ··· ·
·· ·· ·
I I @I
I I @I
I I 6 I
I
I~
I
I I 6 I
I I 6 I
I I 6 I
R I~I
R I@I
R II
.....".PU-II--=O..- . - - - - Exchange
I
Index Register, Stack Manipulation Instructions
PULX
38
4 I SP + I - SP, Moo. - XH
sP +1- SP,M.. - XL
XGDX
18
2 1 ACCD"IX
R
R
R
R
••••••
Note) Condition Code Register will be
explained in Note of Table 3-7-4.
~HITACHI
305
Table 3-7-3
Jump, Branch Instruction
ConCtil ion Code
Aegister
Addressing Modes
Mnemonic
Operations
I - - - - - r - - - - r----,--- - - , - RELATIVE DIRECT INDEX EXTEND IMPLIED
OP -
tI.
OP -
" OP -
" OP -
" OP -
Branch Test
~B~r~.n~<~h~A~lw~.~y~.____~~B~R~A~~~2~0~3~2~--~~+-_r_t_+--+_~~- __
None
21
3 2
None
24
3
2
SCS
25
3
2
C'O
C·l
Zero
BEQ
27
3
2
Z- 1
Branch If ;> Zero
aGE
2C
3
2
Branch If > Zero
SGT
2E
3
2
Branch If Higher
BHI
22
3
2
2
Branch If
Sranch If
II
< Zero
:::h If Lower Or
Branch If
< Zero
BlE
2F
3
SLS
23
3 2
BLT
20
3
2
Branch If Minus
8MI
28
3
2
~~~Ch If Not Equal
SNE
26
3
2
1 0
H INZVC
II
I-B=r.::.nc;<~h~N:.:.-,..=-r__~-1!--CBAN
Branch If Carry Clear
BCC
Branch If Carry Set
5 4 3 2
:::::~
Z + IN VI- 0
c+z-o
Z + IN VI- 1
•
••
•
i-
•
~B~r=-.n~<-h-lf~D~..
~rf~~-w--~--B-V-C--~-2-B~3-r2-r--~t-+--r-t-+--+-~~-+~--~V-_--O-----------ro-to-t-o+.- ~~
Cle.r
Branch If Overflow Set
If Plus
r-s-";~ch
avs
aPL
29
2A
-=--'!-________
3 2
3 2
V
N ..
-""1f-'0'-f0'-f0'-f0'-f0"-f0=-j
0
~hT~~S"Ub-r-ou-,-;n-.~~BS~A~--+=-8~D~5~2-r~--~t--r-r-t--t-+-+--r-+--+-~~--------~ro-ro-ro-to-to-to-i
Jump
---------t~J~M~P~--~--r-t-+--t-+-~6E.t~3~2~7E.+~3~3-~--+-~--1
Jump To Subroutine
JSA
No Operation
NOP
~o~o~o~~o~o+-.-
90 5 2 AD 5 2 BO 6- j
01
~- From Interrupt
RTI
~iurn F~m---'----'-+-------I--+-t-+--t-+-+-·
Subroutine
RTS
Software Interrupt
SWI
--
r---. -
1
Advances Prog. entr.
Only
· . .. . .
®
1--- - -- - -
r--+-- _. -
~W::.::'It::'f=o'-'r'-'ln~,.:':r:';'ru"'po.:
••'---r-W~;':A"-I---1f-~-+-+--I-t-+---+-
39
3F
~--t--I-+-;E
t-~Sl~"~p~----~---t-'S"L~P~--I--+-+-+--+-+-~-+~
1
38 10 1
5
1
12'-
-;- 5 ; I-;-f;-f;• ® ••••
-g-,
lA 4 1
• •••••
Note) *WAI puts R!W high; Address Bus goes to FFFF; Data Bus goes
to the three state level. Condi tion Code Register will be explained
in Note of Table 3-7-4.
Table 3-7-4
Condition Code Register Manipulation Instructions
~ddr."lngMod..
Oper~tionl
Clor Carry
Clear Interrupt Malt
Cle.rOwrflow
Set Carry
Set Interrupt Malt
Set Overflow
Accvmulator A - CCR
CCR - Accumulator A
Mnemonic
ClC
Cli
ClV
SEC
SEI
SEV
TAP
TPA
IMPLIED
OP
OC
1
1
oe 1
OA 1 1
00 1 1
OF
1
DB
1
06
1
07
1
-
•
,
,
,
,
,
Condition Cod!' Register
Boolean Operation
O-C
0-1
O-V
I-C
1-1
I-V
A- CCA
CCA-A
[NOTE) Condition Code
(j)
(Bit V)
@
(Bit C)
@
(Bit C)
@
(Bit V)
@
(Bit V)
® (Bit V)
(l)
(Bit N)
® (All)
@
tBit I)
@J
J-...:=_ _ __
0, a read;
Port 3 Output Strobe Timing
(Single Chip Mode)
Fig. 3-11-6
Port 3 Latch Timing
(Single Chip Mode)
~HnTACH8
319
E
Timer
Counll' _ _ _ _-1 ...
_+=..;.;;._" , ____
P"
Output
Timer Output Timing
Fig. 3-11-7
1.4V
-=::.:.((
Mode InpulS _ _ _ _
IP ul • p". P12)
O.8V
Fig. 3-11-8
Dala Valid
2.0V
~;"'------;If"" O.BV
Mode Programming Timing
RL ·2.2kn
Test POlnl -
.UI
., 152074
®
or Equn,.
R
~
I
C
•
90 pF fo, p.o - PI1. ">0
•
30pF for PXI - P",
R
•
,2 kn
Fig. 3-11-9
-
P3'. p.. - P4,. SCI. 5C,. E
Bus Timing Test Loads (TTL Load)
~HITACHI
320
• PROGRAMMING ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vee a 6.0V ± O.25V. Vpp = 12.5V ± O.3V.
Symbol
Item
Input "High" Voltage
Input "Low" Voltage
Output "High" Voltage
Output "Low" Voltage
Input Leakage Current
Vss a
OV. Ta
0 0 -0,. A o-A I4 • OE. CE
0 0 -0,. A o-A I4 • OE. CE
VIH
Vil
°0-°7
°0-°7
VOH
IOH - - 200,.A
VOL
IOl - 1.6mA
III
VIN .- 5.25V10.5V
0 0 -0,. Ao-A I4 • OE. CE
Vee Current
a
Test Condition
25°C ± 5°C unless otherwise noted.)
min
typ
max
Unit
2.2
-
Vee +0.3
V
0.8
V
-
V
-0.3
2.4
-
Icc
Ipp
Vpp Current
-
-
0.45
V
2
,.A
30
mA
30
mA
• AC CHARACTERISTICS (Vee = 6.0V±O.25V. Vpp = 12.5V±O.3V. Vss = OV. Ta = 25°C±5°C unless otherwise noted.)
Test
condition
Symbol
Item
min
ty
Address Set-up Time
tAs
2
CE Set-up Time
tOES
2
Data Set-up Time
2
Address Hold Time
los
tAH
0
Data Hold Time
tOH
2
Data Output Disable Time
tOF
Vpp Set-up Time
2
-
Program Pulse Width (High Speed Writing)
tvps
tpw
0.95
Program Pulse Width
topw
2.85
Vee Set-up Time
tvcs
2
Data Output Delay Time
tOE
0
"
Fig.6-10'-'
-
-
-
max
Unit
-
,.s
-
-
,.s
,.s
,.s
,.s
130
ns
-
,.s
1.0
1.05
ms
-
78.75
ms
-
,.s
150
ns
Inpul Pulse level- 0.8-2.2V
Inpul Rise Time/Fall Time ~ 20no.
Tuning Reference level
Inpul: '.OV. 2.0V.
Oulpul: O.BV. 2.0V.
Ven'fy
P rogram
-
Address
Data
r---
'---
Data Out Valid
Data In Stable
tos
Vpp
r
tAS
~
IOH
Vpp
Vee
Ivps
Vee
Vee
GND
Ives
~
tOES
-I
tOE
1
~.
Fig. 3-11-10 PROM ProgramNerify Timing
~HITACHI
321
4.
4.1
APPLICATIONS
Use of External Expanded Mode
The HD63701VO supports four operation modes 1, 2, 5 and 6 as
external expanded modes.
Usage of these modes is detailed in
the following paragiaphs.
(1) Non-multiplexeQ modes
(a) Mode 1 (New Mode)
In this mode, Port 3 functions as data bus, Port 1
as lower address bus (AD - A7), and Port 4 as upper
address bus
(As - A1S).
Since l6-bit addresses are
sent out in parallel, the HD63701VO can access up to
65k memory space with no address latch externally
in this mode.
~HITACHI
322
HD63701VO MCU
E
Ao""A7 Aa""Al
8
f--
Do""D7 R/W
5
, 8
I
8
ROM
-,
-1
I
RAM
_L
,
PIA
GPIA
PTM
Address Address
Bus
Bus
(LSB)
(MSB)
Fig. 4-1-1
Data
Bus
HD63701VO, Mode 1
~HITACHI
323
If an internal memory address and an external memory
address are overlapped, the memory address can be
accessed as follows.
When writing, the same data can
be written into both internal and external memories
simultaneously.
When reading, only internal memory can be read while
the external memory can not be read.
The same operations can be applied to modes 2, 5,
and 6.
In mode 1, external memory addresses range from $OOFF
to $FFFF and so internal mask ROM located in $FOOO
through $FFFF can not be accessed.
After reset, Port 1 functions as lower address bus (Ao A7), Port 4 is a upper address bus (As - A1S).
(b) Mode 5 (Equivalent to Mode 5 of HD6801V)
Port 3 works as data bus; and Port 4 as address bus
(Ao - A7) or input pin by programming the DDR.
In this
mode, pin 39 provides the result of the following decoding:
This output signal may be used as a chip select or
chip enable signal permitting to access an external
memory up to 256 byte locations ($0100 - $OlFF).
The pin function of Port 4 can be changed from an
address line to an input port if the system does not
need all of the 8 address lines by writing zero into
the corresponding bit of Port 4 DDR.
An example of connection with PIA (HD6821, HD6321)
is shown in Fig. 4-1-2.
~HITACHI
324
Do'VD7
8
Ao
Al
HD63701VO A2
p:j~ddres~1
decoder
A7
"
IRQ
Do'VD7
8
PA o'VPA7
8
RSo PB o'V PB 7
RS I
CSo HD6821
CSI HD6321
vee
CAl
CB I
CA 2
~ IRQA
CB2
IRQB
lOS
R/W
E
I
CS2
Fig. 4-1-2
E
t
I
I
R/W
J
I
Connection of HD63701VO with PIA
(2) Multiplex Modes (Modes 2 & 6)
Any multiplex mode provides a time multiplexed address
and data on port 3. Therefore, an address latch is
required externally to access external devices. As
(Pin 39) signal is used for an address latch strobe.
An example of HD63701VO and CMOS latch interface is
shown in Fig. 4-1-3.
It should be noted, however,. that the HD6370lVO can
not operate at more than 500 kHz when interfaced with
the latch.
~HITACHB
325
HD14508B
-m=tl
MR DIS
Pso
P31
P32
P33
Do Qo
Dl Ql
D2 Q2
D3 Q3
Do Qo
Dl Ql
D2 Q2
3 Q3
S...TASTB
HD63701VO p ,.
p
Pas
p.,
AS
Y
I
Fig. 4-1-3
Address buses
Ao to A,
Data buses
Do to D,
CMOS Latch
For high-speed operation, 74LS373 or high speed CMOS
latch (74HC373) is desirable to minimize the delay time.
(a) Mode 2 (Equivalent to HD680lV Mode 2)
In this mode, the internal mask ROM (~FOOO through
$FFFF) is disabled and external.memory becomes valid
instead. Port 4 functions as the upper address bus.
(b) Mode 6 (Equivalent to HD680lV Mode 6)
In this mode, the internal mask ROM is enabled.
Port 4 functions as address bus (As - A1S) •
Since Port 4 becomes input mode after reset,
the DDR must be programmed to "I" to use the port as
address bus.
~HITACHI
326
I
Address
Bus
Fig. 4-1-4
4.2
Data
Bus
HD63701VO MCU Expanded Multiplexed Mode
Standby Mode
Bringing STBY "Low", the HD63701VO goes into the Standby
mode.
In this mode, the
epu
becomes reset and all
clocks of the HD63701VO become inactive.
The contents of the internal RAM is retained as long as Vee
is supplied (Vee;;; 2V). Under Standby Mode, memory back-up
is possible with only a few ~A of leakage current. When
STBY is brought "High", the MCU exits from Standby Mode.
When "1" level is 'detected at STBY pin, a clock
generator begins to oscillate and the internal reset
condition is released.
At this time, RES signal must be
held "Low" for at least OSC stabilization time (tRC )
before the CPU operation restarts. Otherwise, the normal
operation is not guaranteed.
Fig. 4-2-1.
~HITACHI
327
I.Store the contents
of registers into
RAM (if necessary)
~Set each bit in
RAM Control Status
Register to
RAME="O", STBY="I"
PWR
3. SLP executed
Restart Routine
Test and judge STBY
bit in RAM Control
Status Register
"I" : VCC was supplied.
"O":V was not
CC
supplied.
Fig. 4-2-1
Flowchart of Standby Mode Application
~HITACHI
328
The timing relationship shown in Fig. 4-2-2 must be satisfied.
,,
NMI
RES
,I
,'
,
II
I
:~
RESl
I
I
:
I
I
I
I
I
I
1*
~
STBY
:
II
S\
I
I
I
STBYl
~
Ij
1*,
II
I
Restart
.---
I
I
I
NMI:Routine
I
.----.
,
I
,
o
o
t---I
Register Save
RAM Control Status
Register Bits set
Fig. 4-2-2
*
Ii
I
I
I
Oscillator Stabilization Time
Timing Chart of Each Signal
Either RESl or STBYl can become "0" level as long as
the execution time of NMI routine is quaranteed.
Fig. 4-2-3 shows an example of a circuit to implement the timing
sequence shown in the Fig. 4-2-2.
.
System power line
....
~
"
To other device
of the system
~
i
Vee
NMI
R2
7Ir
'I>---;h.
I
...
I ..
R
r
RS
STBY
STBYI
1
l cs
RES J>.,.RESl
sWitc~l
V
ICr
1
HD6370lVO
Rl« Rz,
R.C »20ms
r
r
Fig. 4-2-3
Example of Circuit Diagram for a Standby Operation
~HITACHI
329
The Standby power bit in the RAM control status register
detects that VCC is supplied or not. When the VCC rise
time is equal or less than lOO~s, the Standby power bit
may not be cleared. To avoid this, the VCC rise time should
be more than lOO~s, for example, by using the larger
bypass capasitor.
4.3
Address Trap, OP-Code Trap Application
The HD6370lVO facilitates two trap functions, the op-code
trap and the address trap, to protect the HD6370lVO to
proceed an erroneous operation. The op-code trap is
generated when an illegal or undefined op-code is fetched.
Therefore, when undefined codes listed below are fetched,
a trap is caused and the HD6370lVO avoids further erroneous
operation. The priority level of the op-code trap interrupt
is next to the RESET. Undefined codes of the HD6370lVOare:
$00, $02, $03, $12, $13, $14, $15, $lC, $10, $lE, $lF, $41,
$42, $45, $4B, $4E, $51, $52, $55, $5B, $5E, $87, $8F, $C7,
$CO and $CF.
The address trap is generated
from the memory area shown in
noted, however, this function
(not for data access). Under
when an op-code is fetched
Table 2-3-1. It should be
works only under op-code fetch
the support of error processing
program in trap service routine, the user can realize the
proper error processing for the application system.
An
example of restarting from the trap service routine is shown
below. If RTI instruction is ex'~cuted at the end of the
trap service routine, the program is restarted at the
location where the trap interrupt is generated and then
another trap may occur again.
So, special care must be taken when a programmer uses trap function.
TRAP Service Routine
Main Routine
START
LOS
STACK
~HITACHI
330
JMP
START
4.4
Slow Memory Interface
Here described is the example of clock width cantrall circuit
and its timing chart, where E-clock high time is extended
to assure enough access time.
The expanded enable high pulse width (PW'EH)' which is
implemented by using the circuit shown below, is calculated
as follows:
where
n
t 4 ¢cyc:
4~
PWEH
Enable High pulse width
PWEL
Enable Low pulse width
tw
clock cycle time (~s)
I
(~s)
(~s)
approx. 0.45 • Cext(pF)
• Rext(kn) x 10- 3 (~s)
The circuit shown is for a reference purpose.
that users will refine it for actual design.
It is assumed
416
N.C.
C
EXTAL E
XTAL
address
HD63701VO
Rex
Address
decoder
CK
ext\ VCC
Jc ext
Bj
Al
QI
Q2
D2
CLR
HD74LS123*
To CS, etc.
Fig. 4-4-1
CLR
HD74LS174*
* Equivalent CMOS gates
are available.
Clock Control Circuit
~HITACHI
331
4¢
EXTAL
Input
E
Address
Oata
Fig. 4-4-2
4.5
Clock Timing
Interface to HN61256
An examples of the interface to a slow memory device,
HN6l256 (CMOS 256k bit Mask programmable ROM), is described
here.
The AC characteristics and the access timing of the HN6l256
is shown in Fig. 3-5-1.
Item
Symbol
t RC
t AACC
Read Cycle Time
Address Access Time
Chip Enable Access Time
Oata Hold Time from Address
max
Unit
4.0
-
)Js
-
3.5
)JS
3.0
)JS
0.05
0.5
)JS
-
)Js
t EACC
Address Set-up Time
tOF
t AS
0.5
Address Hold Time
tAH
0
Chip Enable ON Time
tCE
3.0
Chip Enable OFF Time
tCE
0.5
Fig. 4-5-1
)JS
)JS
)JS
AC Characteristics and Access Timing of HN61256
~HITACHI
332
min
4.5.1
Use of Two Latches
Two HD14508Bs are used in order to latch 16 bit address.
An example of the program and its access timing are shown
in Table 4-5-1 amd Fig. 4-5-3, respectively.
P40 "'P 47
B
B
Do"'D7
B
P 30
D Q
STI
7
1
I
As"'AI4
CS
r--
P 31
P32
II
B
,srz
D
B
Q
HD1450BB
I
Ao"'A7
CE
HN61256
HD63701VO
(Single Chip Mode)
Fig. 4-5-2
HD63701VO and HN61256 Interface by Two Latches
~HITACHI
333
Table 4-5-1
Mnemonic
LDAA
An Example of the Program
Cycles
STAA
#$FF
P4DDR
3
Port 4 is the output port.
LDD
#$ADDRSI
3
Data that is the address's upper 8
2
bits including CS signal and changes
STI into high and ST2 into low.
STD
PORT3
4
Enables STl, disables ST2, and
moves the address's upper 8 bits
into Port 4.
LDD
#$ADDRS2
3
Data that is the address's lower
8 bits and changes STI into low
and ST2 into high.
STD
PORT3
4
Disables STl, enables ST2, and
stores the address's lower 8 bits
into Port 4.
LDAA
#IMMI
2
Data that changes STI and ST2 into
STAA
PORT3
3
Disables STI and ST2 and enables
LDAB
#$00
2
STAB
P4DDR
3
LDAA
PORT4
low and CE into active.
CEo
Port 4 becomes the input port.
Reads data.
~HITACHI
334
Port 4 Read
E
Address
~
I
Ae'VAI4'CS
Address
Ao'VA7
:I
~
(')
STz
:I
CE
STI
_____...J)(
A e'VAI4,CS
--x
----------------------~
----1~
\~
_ _ _ _ _ _ _ _ _ _ _ _ _ __
c.>
c.>
\~-----------------
/
\
-----.(X XXXXXX
Data
01
A o'VA7
Fig. 4-5-3
Access Timing
--
Data Valid
4.5.2
Extending E clock
Fig. 4-5-4 is an example circuitry to extend the E clock.
The operation mode of the HD63701VO is in mode 6; and the clock
frequency of 4¢ is 4 MHz.
)J-*
.-t~WCK
CONTRa
4¢
-
EXTAL
P 30 'V P 37
8
,
8
I
~LATCH:
Do'VD7
8
Ao'VA7
7
P40'VP~{;
As'VA 14
CS
P 47 -/)
l
AS
R/W
~rf
E
4D
30
20
40
30
20
10
10
~
m·"'CK
77
LS173
HD63701VO (Mode 6)
CE
$OOOO'V$7FFF
HN6l256
CS: Active-high
CE: Active-low
*The detail of this circuit is described in Fig. 4-4-1.
Fig. 4-5-4
HD63701VO and HN61256 Interface by extending
E clock cycle
PW'EH
Fig. 4-5-5
HN61256 Read Timing
~HITACHI
336
In this example, PW EH of which timing is extended by using
the clock control circuit (Fig. 4-4-1) must be at least
4
~s.
The LSl73 is to assure enough address set up time
(t AS ) of HN6l256.
4.6
Interface to the Realtime Clock (HDl468l8)
The HDl468l8 (realtime clock + RAM : RTC)
is a 010S micro-
computer peripheral LSI that incorporates the clock and
calendar functions to compute year, month, day, day of week,
and time.
When this HDl468l8 is interfaced to the HD6370lVO,
this LSI provides a real time clock information to be
displayed.
I
In addition, the HDl468l8 can be also utilized as a system
interval timer and a square waves generator. An example of
the HD146818 and the HD63701VO interface is shown in Fig 4-6-1.
It can be interfaced under the expanded multiplexed mode
(mode 6) of the HD6370lVO.
~HITACHI
337
Jl..f
SQW
AddS bits
cs
III
R/W
.-t
DS
....-t
(Y)
\0
5 I/O Port 2 ~
::r:
SCI
Timer
00
00
ID
Q
:t:
SCI Address Strobe
NMI
AS
X-tal
4.l94304MHz
S bits
Fig. 4-6-1
HD63701VO and HD146818P Interface
(MCU Expanded Multiplexed Mode)
The calendar and clock display functions of HD146818 are
shown below.
0
00
14 bytes
0
SECONDS
00
1
SEC ALARM
01
MINUTES
02
13
00
2
14
OE
3
MIN ALARM
03
4
HOURS
04
u
5
HR ALARM
05
">.
6
DAY OF WK
06
I1l
7
DATE OF MON
07
8
MONTH
08
9
YEAR
09
50-byte
user RAM
63
3F
Fig. 4-6-2
Control register A
OA
11
Control register B
OB
12
Control register C
OC
13
Control register 0
00
~HITACHI
338
~
10
HD146818 On-chip RAM Address Map
~
~
c
• .-j
~
Table 4-6-1
HD146818 Time, Calendar, & Alarm Data Display
-
-
Address
Data range (H exadec ima l)
Data range
(Decimal)
Function
Binary data
mode
BCD data
mode
0
SECONDS
0 to 59
00 to 3B
00 to 59
1
0 to 59
00 to 3B
00 to 59
2
SECONDS ALARM
MINUTES
0 to 59
00 to 3B
00 to 59
3
MINUTES ALARM
0 to 59
00 to 3B
4
HOURS
12-hour
mode
1 to 12
01 to OC/
81 to 8C*
00 to 59
01 to 12/
81 to 92*
24-hour
mode
0 to 23
00 to 17
00 to 23
12-hour
mode
1 to 12
01 to oci
81 to 8C*
01 to 12/
81 to 92*
0 to 23
00 to 17
00 to 23
1 to 7**
01 to 07
1 to 31
01 to 07
01 to lF
01 to 31
5
HOURS
ALARM
7
24-hour
mode
DAY OF THE WEEK
DAY OF THE MONTH
8
MONTH
1 to 12
01 to DC
01 to 12
9
YEAR
0 to 99***
00 to 63
00 to 99
J
6
I
[Notes]
*:
The most significant bit differentiates bet.ween AM
and PM.
**:
***:
That is, 0
1
Sunday,
5
Thursday,
2
=
=
AM and 1
=
Monday,
6
=
3
=
PM.
Tuesday,
Friday, and 7
=
4
=
Wednesday,
Saturday
This takes the lower two digits of the calendar year.
The information of the calendar and the time are stored on
the on-chip RAM and updated every second.
The on-chip RAM
includes not only the display RAM but also 50-byte user RAM
which stores data necessary for the system.
The HD63701VO gets the calendar and time information by
reading the on-chip RAM of the HD146818.
The HD146818
generates three interrupts, update interrupt, alarm interrupt, and periodic interrupt, to the HD63701VO.
The HD63701VO
can service proper routine for the application system by
accepting the HD146818 three interrupts.
~HITACHI
339
Such a combination of the HD63701VO and the HD146818 easily
implements a compact real time system with reduced power
dissipation.
Note: Refer to "HD146818 Data Sheet" for details.
4.7
Reference Data of Battery Service Life
Fig. 4-7-1 shows the battery service life taken from a
silver oxide battery: SR44w (by Hitachi Maxell).
-3000
2590
--
:
Estimated
"-
,""'-
"
'"
720
H
;:l
o
..c:
~
,
300
,,
,,
OJ
,
,
'H
OM
..:I
OJ
o~ 100
:>
,,
,,
,,
,,
,
H
OJ
U)
,
,,
,,
30
10
6070
250
600
6000
Current (\lA)
Fig. 4-7-1
Battery Service Life (Maxell SR44w)
~HITACHI
340
,
5.
PRECAUTIONS
5 .1
Write-Only Register
When a write-only register such as the DDR of the port is
read by the MPU, "$FF" always appears on the data bus.
Note that when an instruction which reads the memory
contents and does some arithmetic operation on the contents
of the write-only register, it always gets $FF as the
arithmetic and logical results.
AIM, OIM and ElM instruc-
tions can not be used for the bit manipulation of the DDR
of the I/O port.
5.2
Address Strobe (AS)
The AS signal is used as an address latch strobe and is
always accompanied with the E-clock.
This means the AS is
available in both Normal Operation Mode and Sleep Mode
whenever the E clock is generated.
5.3
Mode 0
This mode is used for the test purpose only.
It is not
recommended to use this mode for the other purposes.
5 .4
Trap Interrupt
When executing an RTI instruction at the end of the interrupt routine, trap interrupt different from other interrupts returns to the address where the trap interrupt was
generated.
Care must be taken when using trap interrupts
in the program.
See Fig. 5-4-1 and 5-4-2 for details.
~HITACHI
341
B
$FFOl
OPn
$FF02
Operand
$FF03
Undefined
op-code
$FF04
OPn+l
C
Fig. 5-4-1
Undefined Op-code Trap
After executing OPn instruction, the HD63701VO fetches and
decodes an undefined op-code to generate a trap interrupt.
When RTI instruction is executed at the end of the trap
interrupt service routine, the HD63701VO will set $FF03
in PC, fetch the undefined code again, generate a trap
interrupt and repeat ABC endless-loop.
$FF02
BSR
$FF03
01
$FF04
OPn
Fig. 5-4-2
Address Trap
After performing BSR instruction, the branch destination
address is output on an address bus to fetch the first
op-code of a subroutine.
If $0001 is output as an
address by some mistake, the HD63701VO internally decodes
it
executed at the end of this trap interrupt servicing
routine, the HD63701VO will set $0001 in PC and restart
from this address, which causes a trap interrupt again and
repeat this
endless-loop.
~HITACHI
342
5.5
Precaution on the Board Design of Oscillation Circuit
As shown in Fig. 5-5-1, the cross talk disturbs the normal
oscillation if signal lines are put near the oscillation
circuit.
that.
When designing a board, pay attention not to do
In addition, crystal and CL must be put as close to
the HD63701VO as possible.
OJ OJ
I=:
r---~----Power
I=:
.,-l.,-l
source
.-l.-l
I
.-l.-l
I\J I\J
I=: I=:
0'0'
.,-l
.,-l
UJ UJ
EXTAL
HD63701VO
Do not use this kind of print board design.
Fig. 5-5-1
5.6
Precaution to the Board Design of Oscillation Circuit
Application Note for High Speed System Design Using the HD63701VO
When interfacing the HD63701VO to the high speed memory
(ex. HM6264) in expanded multiplexed mode, noise may appear
on the address bus.
Therefore, the following countermeasure
must be taken to prevent this noise from occurring.
However,
when using the HD63701VO in single chip mode, no problem of
this sort occur in the bus.
5.6.1
Problem
If load capacitance of the data bus exceeds th'
specification
~HITACHI
343
and the GND impedance is high in HD63701VO application system,
noise may appear on the address bus during the write cycle and
a write error may
E
/
\
I
AS
\
I
\
I
\
R/W
(SC 2)
X
As '" A15
(Port 4)
Do '" D7
<
(Port 3)
Fig. 5-6-1
5.6.2
The timing is shown in Fig. 5-6-1.
occu~
X
___ Noise
J\.
uu)(
~
Noise Occurrence in Address Bus During Write Cycle
Cause
If the data bus changes from "High" to "Low" (from FFB to OOB) ,
extremely large transient current flows through the GND and
noise may appear on the GND because of the GND impedance.
This noise level appears on all outputs including address bus.
(See Fig. 5-6-2.)
Fig. 5-6-3 shows the dependency of the noise level on each parameter•
ml. •
'"~
Vee
Cd
..
l~:: "~
DO-.....-;~-<
Cd,-'d
."~
E'd
~l. '-A-
Im :::> :::> :::> :::> :::> I
RAM
$OOFF
Opera tion Mode
~
J:
o~
I Mode 4: Expanded Multiplexed Mode
Mode 2
After providing supply voltage, output level
is undefined (0 or 1) unless the contents of
the Output Compare Register matches with those
of the Free Running Counter. The Output
Level Register is not initialized by reset.
I:::
o
-.-I
.j.l
U
§
r<
< < < <
<1
HD63701VO does not have Mode 4
The Output Level Register is initialized
to 0 by reset.
r..
J:
Timer
8.11
'OIl'
Bit 1
I"on2
DDR
om;
DOR
:--rr
_____1 OutPUt flIP'll
..........
8111
'on2
•. ,0
Port 2
Fig. 20 Programmable Timer Block Diagram
~
"-.I
iRQ,
c-·-nI;::
___ . . _:
~I
1.11
1,10
Port2
I'tIrt2
Fig. 20 Programmable Timer Block Diagram
..
(,)
....
(Xl
HD 6301Vl
SCI
~
:I
~
o
§
•.-1
+l
Port Reset
()
~
;:J
r..
HD63701VO
HD6301V
Item
HD6303R
HD63P01Ml
When framing error occurs,
receive data is not
transferred from the
Receive Shift Register to
Receive Data Register (RDR).
HD6303Rl
Receive data is
transferred from
Receive Shift
Register to RDR
even if framing
error· occurs.
The DDR of port is reset synchronously
with E clock. I/O state is undefined from
providing power supply till oscillation start
(max. 20ms).
Heu internal reset
Receive data is transferred from Receive
Shift Register to RDR even if framing
error occurs.
The DDR of port is reset asynchronously
with E clock. CPU enters into high
impedance state (input state) by bringing
RES Low.
Reset release and MCU internal reset is
performed synchronously with E clock.
J:
RES
E
!"
STBY signal is latched synchronously with E
clock.
STBY signal is latched asynchronously
with E clock. CPU enters into standby
state by bringing STBY Low.
Standby Mode
STBY
STBY
--19>--1>0--
STBY
HD63P01Ml
E~
1 output
~
1:
~
o
:I
w
~
<0
§
.....
.j..l
u
C
;::!
f<.
HD6301Vl
HD6303R
HD6303Rl
Ei
L
E,
l
HI-Z
--1 :L ___________ _r-
AS __ - '
AS
( Address)
Strobe
HD63701VO
HD6301V
Item
AS~
During reset, AS
In Expanded Multifunctions normally.
plexed Mode (mode
0, 2, 4 or 6), AS
becomes high impedance
state for a half E
clock cycle during
reset.
Therefore, I/O Port 3
functions as data bus
during reset.
AS
During reset, AS functions normally.
I
t.)
01
o
H06370lVO
HD630lV
Item
HD630lVl
HD6303R
The SCI receive margin is shown below.
HD6303Rl
Ho63pOlMl
The SCI receive margin
The SCI receive
margin is shown below. is shown below.
SCI Receive
Margin
•
:I
~
"
:I
Bit distortion
±37. 5~
tolerance
(t-to) Ito
Bit distortion
±25%
tolerance
(t-to)/to
Character
distor-tion
tolerance
(T-To)/To
Character
distortion
tolerance
(T-To) /To
+3.75~
-2.5%
START
1
2
3
I
I
Ideal
waveform,
5
6
7
8
STOP
to
.1
To
I
±3.75%
4
Real
1
waveform.
~
.1
T
§
-.-I
.jJ
0
t:
::l
'"
HD630lVl
HD6303R
H06303Rl
Bit distortion tolerance
(t-to) Ito
±37.5%
Character distortion
tolerance (T-To)/To
±3.75%
i
HD63pOlMl
VCC =5V±10% (f=O.l'V2MHz)
Supply Voltage
VCC=5V±10%(f=0.1'V2MHZ)
VCC=5V±10%(f=0.1'VlMHz)
=3'V6V(f=0.1'V0.5MHz)
tAH = 20 ns min
Address/Data
Hold Time
(tAH,tHW )
tHW = 20 ns min
tAH and tHW are constant independently of
operating frequency.
t AH , tHW = 60 ns (f=lMHz)
= 40 ns ( =1.5MHz)
= 30 ns ( =2MHz)
tAH and tHW are proportion
to l/f.
(f= operating frequency)
~~
0
1
2
'IMB&>
(1)
tADl and tAD2 are constant independently
of operating frequency. In HD63BOlV
(B version of HD630lV), tADl and tAD2 are
160 ns max. at O.lMHz through 2MHz
operation.
(2)
tADL is related to operating frequency.
(tADL is in proportion to lifo
f: operating frequency)
Address Delay
Time
•
l:
~
()
l:
lin and Cin
of RES
lin = 1.0]JA max.
Load
Capacitance
u
(IJ
a. of E
2 - LSTTL + 40pF
Load
Capacitance
of Port 1
Storage
Temperature
CAl
t1I
IOL = 0.8
Cin = l2.5pF max.
rnA
t ADl , tAD2 and tADL are related to
operating frequency (They are in
proportion to lifo f: operating frequency).
Therefore, if HD637BOlV operates at lower
operating frequency, tADl' tAD2 and tADL
will become 160 ns or more. tADl' tAD 2
and tADL are calculated as follows.
1
tAD (f MHz)
250 ns (1 MHz) x i(MHz)
*
lin = 10]JA max. Cin = 50pF max.
Since RES is multiplexed with Vpp, Cin
and lin are larger than those of HD6301V.
1 - TTL + 90pF
IOH = -200]JA
IOL = 1.6mA
IOH = -200]JA
III
Spec. of
Crystal
Oscillator
...
HD6370lVO
HD630lV
Item
1 - TTL + 30pF
1 - TTL + 90pF
Spec.
Spec.
Rs = 601l max.
Tstg = -55 - +150 o C
II Clock frequency
IrRs max. (Ill
I 8.0 I
I 500 1120 I 80 I 60 I
(MHz) 1 2.51 4 . o [ 6.0
Tstg = -55 - +125°C
I
I
c.>
(J1
(\)
HD6370lvO
HD630lV
Item
E
"""\
HD6303Rl
HD63POlMl
HD6303R
H0630lVl
GND Noise
'--
/
AS~
r
R/W~
Ai
~
:I
~
o
D1
~
A Noise
---c::.::)
x:
>-
c:
.....o
Noise is
reduced by
33%.
Noise is reduced by 50%.
+J
~
If load capacitance in each data
line and GND impedance are
large, noise may appear on
address bus during MCU write
cycle and data won't be written
into RAM correctly. The noise
is caused by GND impedance
which becomes large when large
transient current flows into
GND at High to Low transition of
data line.
:I
Miscellaneous
Chip design and manufacturing process of the H0630lV differ from those of the HD6370lVO.
Therefore, actual spec. and margin are different between the HD630lV and the H06370lVO.
Please carefully examine your system before applying HD630lV or H06370lVO to your system.
APPENDIX
General purpose PROM programmer corresponding to the 27256 can
perform programming to the HD63701VO.
When programming, a
socket adaptor which changes the number of pins, 40 pins to 28 pins,
is necessary.
~HITACHI
353
PROM Programmer and Socket Adaptor
Products name
PROM Programmer
HD63701VO
PROM Programmers for 27256
Socket Adaptor
H31VSA01A
~HITACHI
354
II
Q&A
Category
Question
Answer
Process to Use
a Port as an
Outputs
When using an I/O port as an output,
is the data stored to the Data
Register or is the Data Direction
Register (DDR) set at first?
Store the data to the Data Register at first and then set
DDR (DDR=I); if not, unknown data is output from the
port.
Relation between
Wri ting into the
FRC and SCI
Operation
How are writing into the timer Free
Running Counter(FRC) and the Serial
Communication Interface(SCI) related?
The source of the clock input to the SCI Shift Registers
is the timer FRC.
Therefore, if new data is written into the FRC, SCI
operations are disturbed.
See the following diagram.
$09,$OA
/W
~
~
:I
~
Receive Shift]
Register
I
E J"L FRC -IL Baud Rate
- - Generator
(')
:I
Transmi t Shift
Register
* A write into the FRC is prohibited during SCI operations.
Writing into the
FRC during Serial
Receive/Transmit
Is it prohibited to write data into
the Free Running Counter (FRC) during
serial receive/transmit?
Yes. If data is written into the FRC during serial
receive/transmit, the FRC stops counting up and the baud
rate changes.
In condition other than serial receive/transmit, it's
possible to write.
W
01
01
~
~
0)
Category
Question
Answer
1$09
fOA,
1 Write
Receive Shiftl
Register
E:&~l\l:n~=
I
-----J
1
L.jTransmit Shit,
Register
((
•
l:
~
(')
I:
n
Ir-------'
The counter stops
r-l
'----'
'---
and the baud rate
changes •
RDRF State When
SCI Receiving
When the wake-up flag is set (WU=l) the RDRF flag
cannot be set. (RDRF=O)
What is the state of the Receive Data
Register Full (RDRF) flag when the
HD6370lVO SCI can receive signals
(RE=l) and the wake-up flag (WO bit)
is set?
TRCSR
76543210
$0011 I RDRFIORFEITDREIRIE IRE ITIE I TE I wu I
+
?
J1
+
1
Category
Serial I/O
Operation
Question
The serial I/O does not operate
satisfactorily. Initialization does
not seem to be wrong, but the data is
not transmittred. What is wrong?
Initialize by User Program
(1) Set the Rate/Mode Control Register
(RMCR) to the desired operation.
(2) Set the Transmit/Receive Control
Status Register (TRCSR) to the
desired operation.
Answer
Just after the initialization of serial I/O, the data
transmit is not operative during 10 cycles of Baud Rate
after setting the TE. The reason is as follows.
Setting the transmit enable bit (TE bit) causes ten
consecutive "1" of preamble and makes the transmitter
section operative. In other words, the transmitter
section gets ready after one frame (10 bits) transmitting time according to the Baud rate.
(ex.) When the Baud rate is set to 9600 Baud (104.2~s
at 1 bit) ,
Set the Baud rate
Set TE
Transmit OK
~/I////ff~2lT/l/lJ//zJ. _________~
~104.2~s
~
~
Preamble Causing Period
1.042ms after setting the TE, the transmitter section
is operative.
:I
~
"
:I
x 10=1.042ms:I'J:I: Transmit Inoperative Period
Serial I/O
Register Read
When transmitting the data, is reading
the Transmit/Receive Control Register
(TRCSR) required?
When the transfer interval is long enough
compared with the Baud rate, Transmit
Oata Register Empty (TORE) will be set.
In that case, are there any problems
when transmitting data without checking
the TDRE flag in the TRCSR?
The TDRE flag shows if the TDRE register is empty or
not. When writing a data to the TDR with TDRE=l, it's
not necessary to check the TORE. But reading the TORE
flag tells us the·contents of TDR. For example, when
new data is written to the TDR with TDRE "0" (TDR
already has a data), the old data will be erased.
When the transfer interval is long enough compared with
the Baud rate, there's no problem. However, check
TRCSR if possible.
w
(1l
-..j
~
CAl
C11
-
lO~s
I
I
I
.:
IRQl
:+-2 machine cycles"':
I
I
I
(2) In this case, as a timer interrupt is executed the
interrupt mask is automatically set. So IRQl is ignored.
~
:I
~
(')
:I
See the followings for the illustration of IRQ l and other
interrupts and a countermeasure.
~
and Other Interrupts
Main
Routine
Timer
IRQ,
Routine
Routine
,1
IliQ," Interrupt
cfIc··' •• '. .
Request
'
IRQl is
ignored.
.... , :
~~~
Countermeasure
Clear the I masJc at the beginning of the timer
interrupt routine.
Timer
IRQ,
Hain
Routine
Routine
Routine
IRQ1 is acceptable.
OCLI , Clears the interrupt mask (I:().
With this method, note the follovinq ;
(1) IRQl may be ignored when the request occurs during
timer interrupt vectoring.
(2) Interrupts form. NiiI or SWI are excluded.
~I=l
Category
Question
CLI Instruction
and Interrupt
Operation
In theHD63701VO, a timer interrupt
is not accepted in the following
program. Is there any problem?
-
Answer
~.: ~utine-l
WI
CLI
SEI
I-WI
I
I
B~
Using CLI
I
NOP
I
To accept an interrupt, two machine cycles are necessary
between CLI and SEI. That is, in this program, two NOP
instructions are necessary. The same thing can be said
when using TAP for CLI and SEI.
I
LOI
I
1_ _ _ _ _ _ _ 1
eLI
-
Using TAP
- -
NOP
NOP
1
I
4Z)
1:
~
C')
With which edges of the EXTAL clock
does the E clock change synchronously,
rising edge (t) or falling edge (~)?
Constants of the
Reset Circui t
Does the capacitor of the recommended
reset circuit in the HD6370lVO have an
upper limit?
~k)
I
I ::
I
SEI
I
TAP (Sets the I mask)
:
I
1
I
I
I
I
BRA LOI
1
Relation between
the External
Clock (EXTAL
Clock) and
Enable Clock
(E Clock)
- , TAP- (Cle-;;r;- the I
I
I
I
I
J
(P
It changes synchronouslY with the falling edge
EXTAL clock.
of the
:XTAL
:t
Capacitor Cr does not have upper limit because of the
Schmitt trigger circuit provided with the ~.
Available if Rr.Cr»20ms
~I
To the system power supply
'I~
1
Rr
r
r
T.
Rr
!
To
peripherals
-iY
...L.C r
Rl« R2 ,Rr "C r »20m,s
w
OJ
W
~
f
I~
Vee
[:trrl~"
RS
ifTCS
Iml:I
~ RESl
~
HD6370lVO
III~
c.>
~
Category
~
J:
Question
Answer
Port Output
After Resetting
What data does a port output when the
Data Direction Register(DDR)=1
after resetting?
After resetting, since the Data Register of a port is
undefined, undefined data is output when the DDR=l.
Input definite data by programming in the Data Register
before setting the DDR=I.
Schmitt Trigger
Circuit of STBY
Is the Schmitt trigger c,ircuit
provided with the HD6370lVO STBY?
Yes.
Return from
Standby Mode
What occurs when returning from the
standby mode without using RES?
The CPU does not operate normally because the contents
of each register are not definite.
Therefore, always use the RES when returning from the
standby mode.
Going into the
Standby Mode
Does the CPU go into the standby mode
after current instruction execution
is completed?
Because there is no connection between the instruction execution sequence and the standby mode. That is,
when the STBY pin goes into "low", the state is latched
at the next rising edge of E clock. Then the internal
registers are reset at the next falling edge.
~
o
J:
No.
' - - Internal registers
:
are reset.
E
I
I
I
STBY
I
I
t
Answer
Question
Category
Timing for the
Standby Mode
The timing for the standby mode is
shown in the HD63701VO user's manual.
Tl is not defined. How long is Tl?
©
®
®
NMI
--"I!-______
REs
:- . j Tl b'-
I
I
--
I
I
I
I
I
I
STBY
.....,
j4-
RAM Control
Register Set
T2
After the RAM Control Register is set in the NMI routine,
either STBY or RES can be in the low state with no
priority.
r--
I
I
I
I
I---
,.T2~
Reset Start
Oscillation Stabilization Time
~
:I
~
(')
:I
Usage of Bit
Manipulator
Instructions
How the bit manipulation instructions
of the HD63701VO should be written?
They are written as follows;
OIM
OIM
# $ 0 4 ,
# $ 0 4 ,
I
Immediate Data
$ 1. 0
$ 1 0 ,X
(Direct Addressing)
(Index Addressing)
T~
Address
Index Register
This is an example of OR operation of the immediate data
and the memory and storing the result in the memory.
The HD63701VO has the following bit manipulation
instructions.
(IMM) • (M)~(M)
OIM
(IMM) + (M) ~ (M)
AIM
ElM
(IMM)
(M) ~ (M)
(IMM) • (M)
TIM
These instructions are written in the same way.
e
The following bit manipulations have different mnumonics
in the same OP code.
w
en
01
..
to)
0)
0)
Category
Answer
Question
I
OP code
Bit Manipulation Instruction
Mnumonics
Function
o -Mi
71161
A I M 1 B C L R 1 The memory bit i(i=O to 7) is
cleared and the other bits
don't change.
l-m
72 1 62
o I M
B SET
The memory bit i(i=O to 7) is
set and the other bits don't
change.
Hi -Hi
~
75165 1 ElM
BTGL
:x
~
C')
:x
BTST
7B 1 6B 1 TIM
,
----
Direct
Addressing
The memory bit i(i=O to 7) is
inverted and the other bits
don't change.
1 . m
AND operation test of the
memory bit i (i=O to 7) and
"1" is executed and its
corresponding condition code
is changed.
Index
Addressing
The mnumonics mentioned above can be written as follows.
BCLR
BCLR
3,$10 -AIM
3,$10,X_AIM
#$F7,
#$F7,
$10
$lO,X
(Direct Addressing)
(Index Addressing)
BSET
BSET
~OIM
3,$10,X~OIM
#$08,
#$08,
$10
$lO,X
(Direct Addressing)
(Index Addressing)
3,$10
TT~
Bit Address
Index Register
Category
Usage of Bit
Manipulation
Instructions to
the Port
Question
Are the bit manipulation instructions
(AIM, DIM, ElM, TIM) executable when
a port is in the output state
(DDR=l)?
Answer
It can be used if the port is in the output state
(DDR=l). However, the bit manipulation instruction
is executed as follows
~@
Reads specified address.
Executes logical operation.
Writes the result into the specified address.
Since the specified address CD reads the pin state of
the port, the data is influenced by the pins even if
any data is output from the port.
~
:I
~
C')
RAM Access
Disable during
Program
Execution
When executing a program with the RAME
bit of the RAM Control Register
disabled,
(i) The external RAM can be accessed; the internal RAM
is neither readable nor writable when the RAME bit
is disabled.
(1) What occurs if the internal RAM
address is accessed?
(2) What occurs if the interrupt
requests are generated?
(2) If there is no stacking area other than the internal
RAM, the MPU will burst when returning from the
interrupt sequence.
:I
cu
(J)
......
~
~HITACHI
368
HD6301/HD6303 SERIES HANDBOOK
Section Five
HD6301XO/
HD6303X/
HD63701XO
User s Manual
9
~HnTACHn
369
~HITACHI
370
Section 5
HD6301 XO/HD6303X/HD63701 XO User's Manual
Table of Contents
Page
1.
OVERViEW ................................................... .
375
Features ................................................... .
375
1.2
Block Diagrams ............................................. .
377
1.3
Pin Description ............................................. .
380
INTERNAL ARCHITECTURE AND OPERATION ...................... .
383
2.1
Operation Modes ............................................ .
383
2.2
Memory Map ............................................... .
386
2.3
Function Pin Description ...................................... .
388
2.4
Ports ...................................................... .
393
2.5
RAM/Port 5 Control Register ................................... .
397
CPU FUNCTION ............................................... .
399
3.1
CPU Registers .............................................. .
399
3.2
Addressing Modes ........................................... .
400
3.3
Instruction Set .............................................. .
402
3.4
CPU Instruction Flow ......................................... .
408
3.5
Low Power Dissipation Modes ................................. .
410
3.6
Trap Function ............................................... .
413
3.7
Reset ..................................................... .
414
3.8
Interrupts .................................................. .
415
TIMER 1 ...................................................... .
418
4.1
Free-Running Counter (FRC) .................................. .
419
4.2
Output Compare Registers (OCR) .............................. .
419
1.1
2.
3.
4.
4.3
Input Compare Register (lCR) .................................. .
420
4.4
Timer Control/Status Register 1 (TCSR1) ......................... .
420
4.5
Timer Control/Status Register 2 (TCSR2) ......................... .
421
4.6
Timer Status Flags .......................................... .
423
4.7
Precautions on Cleaning the OCF .............................. .
423
5.
TIMER 2 ...................................................... .
425
5.1
Timer 2 Upcounter (T2CNT) ................................... .
425
5.2
Timer Constant Register (TCONR) .............................. .
426
5.3
Timer Control/Status Register 3 (TCSR3) ......................... .
426
5.4
Timer Status Flags .......................................... .
428
I
~HRTACHH
371
6.
SERIAL COMMUNICATIONS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . ..
429
6.1
Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
429
6.2
Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
430
6.3
Clock Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
431
6.4
Transmit/Receive Control Status Register (TRCSR). . . . . . . . . . . . . . . . ..
433
6.5
Transmit Rate/Mode Control Register (RMCR). . . . . . . . . . . . . . . . . . . . ..
434
6.6
SCI Receiving Margin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
438
6.7
Timer, SCI Status Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
438
6.8
Precaution for Clock-Synchronous Serial Communication Interface. . . ..
439
HD63701XO PROGRAMMABLE ROM (EPROM). . ..... . ... ..... . . .. ...
441
7.1
Programming and Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
443
7.2
Erasing (Window Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
444
7.3
Characteristics and Applications ................................ ,
444
7.
8.
APPLICATIONS.................................................
447
8.1
HD6301XO or HD63701XO in Expanded Mode.. ..... .. . .. ... .. . ....
447
8.2
HD6301 XO or HD63701 XO in Single-Chip Mode . . . . . . . . . . . . . . . . . . ..
448
8.3
Timer Applications ........................................... ,
448
8.4
SCI Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
452
8.5
Lowering Operating Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
454
8.6
Memory Ready Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
457
8.7
Halt Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
458
8.8
RD, WR Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
459
8.9
LCD-II Interface Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
460
8.10
Oscillation Board Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
461
APPENDIX I. ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . ..
463
APPENDIX II. INSTRUCTION EXECUTION CYCLES. . . . . . . . . . . . . . . . . . . . ..
485
~HITACHI
372
APPENDIX III. QUESTIONS AND ANSWERS ........................... .
491
111.1
Parallel Ports ............................................... .
491
111.2
Serial Ports ................................................ .
492
111.3
Timer/Counter .............................................. .
493
111.4
Bus Interface ............................................... .
497
111.5
Interrupt Control. ............................................ .
500
111.6
Oscillation Circuit ........................................... .
502
III. 7
Reset ..................................................... .
502
111.8
Low Power Dissipation Mode .................................. .
505
111.9
Software ................................................... .
507
111.10 Others .................................................... .
508
APPENDIX IV. THE DIFFERENCES BETWEEN HD63701XO and HD6301XO ...
509
APPENDIX V. PROGRAM DEVELOPMENT PROCEDURE
AND SUPPORT SYSTEM ............................... .
510
I
~HITACHI
373
~HITACHI
374
Section 1. Overview
The HD6301 XO, HD6303X, and the HD63701 XO are high-performance CMOS, 8-bit, single-chip
microcomputer units (MCU s) which are object-code compatible with the HD6301 V.
In addition to the CPU, these MPUs contain 192 bytes of RAM, a 16-bit 4-function timer, an a-bit
reload able timer, a serial communications interface (SCI), and 53 parallel lines. The HD6301XO has
4k bytes of masked ROM. The HD63701XO has 4k bytes of EPROM sometimes referred to as
programmable ROM or PROM in this handbook. The HD6303X has no ROM. The MPUs' halt and
memory ready functions enable them to release external buses and perform low-speed external
memory access.
The HD63701XO's programmable ROM is programmed by the same method as the standard
2732A EPROM. It is available in ceramic packages. The ceramic package with window is erasable
for use in the debugging development stage.
1.1 Features
The HD6301XO, HD6303X, and HD63701XO provide the following features.
Instruction set compatible with the HD6301 V1
On-board ROM
- 4k bytes programmable (HD63701 XO)
- 4k bytes masked (HD6301 XO)
192 bytes RAM
53 parallel I/O lines
- 24 common I/O lines (ports 2, 3, and 6)
- 21 output only lines (ports 1, 4, and 7)
- 8 input only lines (port 5)
Darlington transistor direct drive lines (ports 2 and 6)
16-bit programmable timer
- 1 input capture register
- 1 free-running counter
- 2 output compare registers
8-bit reloadable counter
- External event counter
- Square-wave generator
~HITACHI
375
Serial communications interface (SCI)
- Asynchronous mode/clocked synchronous mode
- 3 transmit formats (asynchronous mode)
- 6 clock sources
Memory-ready function for low-speed memory access
Halt function
Error detection function (address trap. opcode trap)
Interrupts
-3 external
-7 internal
MCU operation modes
- Mode 1: expanded mode (internal ROM inhibited)
- Mode 2: expanded mode (internal ROM valid)
- Mode 3: single chip mode
PROM mode (HD63701XO)
Address space up to 6Sk bytes
Low power modes
-Sleep mode
- Standby mode
Minimum instruction time 0.5 J.1S (f = 2.0 MHz)
~HITACHI
376
1.2 Block Diagrams
Figures 1-1 ,1-2, and 1-3 are block diagrams for HD6301XO, HD6303X, and HD63701XO respectively.
'"
--
cc
Vss
Vss
o
P2o(Tinl
N
C.
a:
C
C
~
t: C
P~I(Tout1)
P22(SCLK)
it.
C
t-15'"
P23(Rx)
~~l!lllt
-'
«
~
-'
;5
x
w
~¥~a:I:;
g;a:
!::E ~
~
::;;
~
....--
CPu
p,JRD
p,/WR
'"
').
P"/R/W
P,iOR
~
PulTout2)
P,iBA
L...--
P21(TCLK)
lL!
l...-
-,§
t-- P3r10
t: C
it. c
r--L.,
t-- P310
f---
U
r-- P3a/De
'--
2
.
0
L-
I-- P,t/As
I-- P,s/A,
~.---
m
I-- PH/A,
!11
IRQ 21
Ps,fiRO:
PS2(MR)
'--
r--
on
15
c.
C
P"
L--
P eo - - PSI - - - - -
P82~
P63~
HITACHI
379
1.3 Pin Description
Figure 1-4 shows the pin arrangemen's for the various packages.
Table 1-1 lists pin functions for the HD6301XO, HD6303X, and the HD63701XO in modes 1, 2, and 3.
Table 1-2 lists pin functions for the HD63701 XO in PROM mode. For further pin description, see 2.3
Functional Pin Description, and 2.4 Ports.
• HD6301XOp, HD63A01XOp, HD63B01XOP (DP-64S)
• HD6303Xp, HD63A03Xp, HD63B03XP (DP-64S)
• HD63701XOC, HD637A01XOC, HD637B01XOC (DC-64S)
Vss
XTAL
EXTAL
MPa
MP,
RESNpp
STBY
NMI/EA.
P2o/Tin
P2,/Toutl
P22/SCLK
P2./Rx
P2./Tx
P2./Tout2
P2o/Tout3
P2,/TCLK
PSo/IRO,
PS,/IRO,
PS./MR
PS./HALT
.
,0
E
liD/P7o
WR/P7,
R/W/P72
UR/P7.
BA/P7.
Do/P30/EOo
D,jP3,/EO,
D2IP32/E02
Do/P3./EO•
D./P34/EO.
D5/P35/EO.
Do/P3./EO.
D,/P3,/EO,
AoIPlo/EAo
A,/Pl,/EAi
A2/Pl21EA2
A2/Plo/EA.
A./Pl./EA.
A./Pl5/EA.
Ao/Ple/EA.
A,/Ph/EA,
Vpp/OE
Ae/P40/EA.
A./P4,/EA.
A,o/P42/EA,o
A,,/P4./EA,,
A12/P40
A,./P4.
A,./P4.
A,5/P4,
Vee
e.
.,••
80
5.
58
"••
••
ps./iS
PS./05
PS.
PS,
PBo
PB,
PB2
P6.
PB.
P6.
PB.
PB,
• HD6301XOF, HD63A01XOF, HD63B01XOF (FP-80)
• HD6303XF, HD63A03XF, HD63B03XF (FP-80)
D,/P3,/EO,
NC
A7/P1,/EA,
Vpp/OE
Aa/P4olEA,
NC
4'
24
• HD6301XOCp, HD63A01XOCp, HD63B01XOCP (CP-68)
• HD6303XCp, HD63A03XCp, HD63B03XCP (CP-68)
..
>-
~
2
~~~f~~f
;t.J
~~~"E~'~will@i~i
~C~OO.~N_~~~~~~2;
P2~~~ ~~
P2 2/SClK
P23/Rx
P2.1T.
P2 6!ToutZ
P2e/Tovt3
P2,/TCLK
:: ~:~:!:;~:
0
12
13
14
15
16
17
58
57
56
55
54
53}::
D~P34/E04
Ds/P3 5/EOa
OIl/P3a1EOe
D7/P3 7/EO,
NC
AoI P1 01 EAo
P501IR~~ ~:
p:~~:~
~~
:~F ::~:~ :~:::
P5yHALl
PS..,'rs
22
::F :;::~::
::F ~:~~~EA7
P6~~
2:
P5,
26
50,= AyP1VEA3
47,= Ae!P1 e1 EA a
~~~gM~~~~~~~~~;~:
As/ P401 EAa
Note: NC; No connection
Figure 1-4. Pin Arrangement
~HITACHI
380
Table 1-1. Pin Functions
Number
DP-64S FP-80 CP-68
73
2
Function
Name
VSS
Ground
2,3
74,75 3,4
XTAL,EXTAL
Crystal connections. Connect external clock to EXTAL
4,5
77,78 5,6
MPO, MP1
Operation mode
6
79
7
RES
Reset input
7
80
8
STBY
Standby input
9
NMI
Nonmaskable interrupt
8
9
5
10
Tin/P20 *
Timer 1 capture input
10
6
11
Tout1/P21 *
Timer 1 OCR1 output
11
7
12
SCLK/P22 *
SCI clock input or output
12
8
13
Rx/P23 *
SCI receive input
13
9
14
Tx/P24 *
SCI transmit input
14
10
15
Tout2/P25 *
Timer 1 OCR2 output
15
11
16
Tout3/P26 •
Timer 2 output
16
12
17
TCLK/P27,
Timer 2 external clock input
17,18
14,15 19,20
IR01/P50'*
IR02/P51
Level-detect interrupt inputs
19
16
21
MR/P52*
Memory ready input
20
17
22
HALT/P53 *
Halt request input
21-24
18-21 23-26
P54-P57
25-32
25-32 27-34
P60-P67
Port 6
33
33
VCC
Power supply
34-41
34-40, 37 -44
A15 /P4y-*
A8 /P4 0 *
Address bus, bits15-8
\iss *
Ground
36
43
42
44
45
Port 2
Port 5
PortA
* Mode 1 or Mode 21M ode 3
~HITACHI
381
Table 1-1. Pin Functions (continued)
Number
Function
DP-64S FP-80 CP-68
Name
43-50
45-52 46-53
A7/P1 7- •
AO/P1 0 •
Address bus, bits 7-0
Port 1
51-58
55-59, 55-62
62,64,
65
D7/P3r ·
DO/P30 •
Data bus
Port 3
59
66
63
BA/P74
Bus available output
Port 7
60
67
64
LlR/P73
61
69
65
R/W/P72
Reacllwrite output
62
70
66
WR/P71
Write cycle output
63
71
67
RD/P70·
Read cycle output
64
72
68
E
External clock output
·
·
.
·
Opcode fetch cycle output
·Mode 1 or Mode 2/Mode 3
Table 1-2. Pin Functions for HD63701 XO PROM Mode
Number
Name
Function
7
STBY
PROM mode input
38-41
EA11-EA8
Address input bus, bits 11-8
42
Vpp/OE
Programming power supply
43-50
EArEAo
Address input bus, bits 7-0
51-58
EOrEOo
Data input bus
DP-64S
Note: Ground all other HD63701 XO pins in PROM mode.
Table 1-3. Relationship of HD6301XO, HD6303X, and HD63701XO Operating Modes
Mode
Device Type
HD6301XO
X
HD6303X
HD63701XO
X
X
2
3
X
X
X
X
EPROM
X
~HITACHI
382
Section 2. Internal Architecture and Operation
2.1 Operation Modes
The HD6301XO and HD63701XO operate in three MCU modes. The HD63701XO also operates in
PROM mode. The HD6303X only operates in MCU mode 1. The mode program pins MPO and MP1,
and the STBY pin select the mode (table 2-1).
•
MCU 1 (expanded): external memory access enabled, internal ROM disabled
•
MCU 2 (expanded): external memory access enabled, internal ROM enabled
•
MCU 3 (single-chip): external memory access disabled
•
PROM prgramming: MCU disabled, PROM programming enabled
Table 2-1. Mode Selection
MP1
MPO
STBY
ROM
RAM
Interrupt Vector
Operation Mode
Low
High
X
External
Internal
External
MCU 1 (expanded)
High
Low
X
Internal
Internal
Internal
MCU 2 (expanded)
High
High
X
Internal
Internal
Internal
MCU 3 (single-chip)
Low
Low
Low
Internal
X
X
PROM programming
I
Note: X = Don't care
~HITACHI
383
2.1.1 MCU Mode 1 (Expanded)
In MCU mode 1, port 3 is the data bus, port 1 is the lower address bus, and port 4 is the upper address
bus. They can directly interface with HD6800 buses. Port 7 supplies signals such as R/W. See table
2-2. In mode 1, the ROM is disabled and the external address space is 65k bytes (figure 2-1). Since the
HD6303X has no internal ROM, it only operates in mode 1.
Vee
E
_RD
'-WR
Rm
DR
RES
STBY
NMI
PortZ
8 I/O Lines
Timer 1. Z
SCI
Port 5
8 Input Lines
IRQ•• IRCh
MR.HALT
Port 6
8 I/O Lines
BA
MCU
Port 3
8 Data Bus
Port 1
8 Address Bus
Port 4
8 Address Bus
Figure 2-1. MCU Mode 1
2.1.2 MCU Mode 2 (Expanded)
MCU mode 2 is the same as mode 1, except that the ROM is enabled. The external address space is
61 k bytes (figure 2-2)..
E
An
WR
c:::::J
R/W
RES
STBY
LlR
BA
NMT
Port 2
8110 Lines
Timer 1. 2 SCI
Port 5
8 Input Lines
IRQ ,. IRQ, MR. HALT
Port 1
8 Address Bus
Port 6
81/0 Lines
Port 4
8 Address Bus
Port 3
8 Data Bus
Figure 2-2. MCU Mode 2
~HITACHI
384
2.1.3 MCU Mode 3 (Single-Chip)
In MCU mode 3, all ports are I/O ports. There is no interface to external buses (figure 2-3).
E
Port 7
5 Output Lines
RES
STBY
NMI
Port 2
8110 Lines
Timer 1, 2 SCI
Port 5
8 Input Lines
IRO"IRO,
Port 3
8110 Lines
Port 1
8 Output Lines
Port 6
Port 4
8 Output Lines
8110 Lines
I
Figure 2-3, MCU Mode 3
2.1.4 PROM Mode
In PROM mode, the HD63701XO's EPROM can be programmed (figure 2-4, table 2-2). Refer to Section
7, Programmable ROM, for details.
Vee
MP,
MP,
STBY
Port 3
8 Data Bus
Port 1
8 Address Bus
Port 4
4 Address Bus
Figure 2-4. PROM Programming Mode
~HITACHI
385
Table 2-2. Port Signals
MCU Mode 1
MCU Mode 2
MCU Mode 3
PROM Mode
Address bus (AO-A7)
Address bus ( AO-A7)
Output port
Address bus (EAO-EA7)
2
110 port
I/O port
I/O port
Connect to ground
3
Data bus (DrDo).
Data bus (07-00)
I/O port
Data bus (E07-EOO)
4
Address bus (Aa-A1S)
Address bus ( Aa-A1S)
Output port
Address bus
Port
(EAa-EA11, pins
P40-P43 only)
S
Input port
Input port
Input port
CE (PS7 only)
6
I/O port
I/O port
I/O port
Connect to ground
7
RD, WR, RIW, LlR, SA
RD, WR, RIW, LlR, SA
Output port
Connect to ground
2.2 Memory Map
The HD6301XO, HD6303X, and HD63701XO can access up to 6Sk bytes of external memory,
depending on the operating mode. Figure 2-S shows a memory map for each mode. The first 32
locations of each map, from $00 to $1 F, are reserved for the MCU's internal register area (table 2-3).
PROM Mode
MCU Mode
Expanded Mode
Mode 1
Internal·
Register
External
Memory
Space
Expanded Mode
Mode 2
Internal*
Register
$ O O O O . } Internal
$OOIF
External
Memory
Space
$OOlF
$0040
Register
$0040
Internal
RAM
Internal
RAM
$OOFF
$OOFF
External
Memory
Space
$FOOO
Internal
ROM
$FFFF '--_ _~,
• Excludes the following addresses
which may be used externally:
$02, $04, $06, $07, $18.
$FFFF~~~..:J)
Internal
ROM
$FFFF
• Excludes the following addresses
which may be used externally:
$02, $04, $06, $07, $18.
Figure 2-S. Memory Maps
~HITACHI
386
Mode 3
$0000
Internal
RAM
External
Memory
Space
Single-chip Mode
HD63701XO
Table 2-3. Internal Register Area
Address
Register
RfW
State at RESET
01
Port 2 data direction register
W
$FC
02
Port 1
RNJ
Undefined
03
Port 2
RNJ
Undefined
04
Port 3 data direction register
W
$FE
06
Port 3
RIW
Undefined
07
Port 4
RNJ
Undefined
08
Timing controVstatus register 1
RNJ
$00
09
Free-running counter (upper byte)
RIW
$00
OA
Free-running counter (lower byte)
RNJ
$00
08
Output compare register 1 (upper byte)
RNJ
$FF
OC
Output compare register 1 (lower byte)
RNJ
$FF
00
Input capture register (upper byte)
R
$00
OE
Input capture register (lower byte)
R
$00
OF
Timer controVstatus register 2
RIW
$10
10
Rate, mode control register
RIW
$00
11
Tx/Rx control status register
RNJ
$20
12
Receive data register
R
$00
13
Transmit data register
W
$00
14
RAM/port 5 control register
RNJ
$7C or$FC
15
Port 5
R
16
Port 6 data direction register
W
00
05
I
$00
~HITACHI
387
Table 2-3. Intemal Register Area (continued)
Address
Register
RIW
State at RESET
17
Port 6
RIW
Undefined
18
Port 7
RIW
Undefined
19
Output capture register 2 (upper byte)
RIW
$FF
1A
Output capture register 2 (lower byte)
RIW
$FF
1B
Timer controVstatus register 3
RIW
$20
1e
Timer constant register
W
$FF
10
Timer 2 upcounter
RIW
$00
1E
Reserved
1F
Reserved
2.3 Functional Pin Description
2.3.1 Power (Vec, VSS)
Vee and VSS are the power supply pins. Apply +5 V ± 10% to Vee. Tie VSS to ground.
2.3.2 Clock OCTAL, EXTAL)
XTAL and EXTAL connect to an AT-<:ut parallel resonant crystal. The chip has a divide-by-four circuit.
For example, if a 4 MHz crystal is used, the system clock will be 1 MHz.
Figure 2-6 is an example of the crystal oscillator connection. The crystal and CL 1 and CL2 should be
located as close as possible to the XTAL and EXTAL pins. No line must cross the lines between the
crystal oscillator and the XTAL and EXTAL pins.
The EXTAL pin can be driven by an extemal clock with a 45% to 55% duty cycle.· The LSI divides the
extemal clock frequency by four. The extemal clock should therefore be less than four times the
maximum clock frequency. When using an extemal clock, the XTAL pin should be left open.
~HITACHI
388
AT Cut Parallel Resonant Crystal Oscillator
Co=7 pF max
Rs=60 II max
XTAL 1---........- - - ,
~
CU =C L2
T
_-,
=10 pF-22 pF±20%
(3.2-8 MHz)
EXTALI--
1
J-JCL2 -
Cu
(a) Crystal Interface
XTAL
I--- N.C.
EXTAL ~ External Clock
(b) External Clock
Figure 2-6. Recommended Crystal Oscillator Connection
2.3.3 Standby (STBY)
I
The STBY pin puts the MCU in standby mode. When STBY is low, the oscillation stops, and the internal
clock is stabilized to put the MCU in a reset condition. To retain the contents of RAM during standby,
write 0 to the RAM enable bit (RAM E). RAME is bit 6 of the RAM/port 5 control register at address
$0014. RAM is disabled, and its contents are sustained. Refer to 3.5 Low Power Dissipation Mode for
details on the standby mode.
When STBY, MPO, and MP1 are low, the MCU is in PROM mode. Refer to Section 7, Programmable
ROM for details.
2.3.4 Reset (RES)
This pin resets the MCU's internal state and provides a startup procedure. The RES input must be held
low for at least 20 ms during power-on.
The CPU registers accumulator, index register, stack pointer, condition code register except for mask
bit, RAM, and the data registers of the ports are not initialized during reset, so their contents are
undefined.
2.3.5 External Clock (E)
E provides a TTL-compatible system clock to external circuits. Its frequency is one-fourth that of the
crystal oscillator or external clock. E can drive one TTL load and 90 pF.
~HITACHI
389
2.3.6 Nonmaskable Interrupt (NMI)
When CPU detects a falling edge at the NMI input, it begins the internal nonmaskable interrupt
sequence. The instruction being executed when the NMI is detected will proceed to completion. The
interrupt mask bit of the condition code register does not affect the nonmaskable interrupt.
In response to an NMI interrupt, the contents of the program counter, index register, accumulators, and
condition code register will be saved onto the stack. After they are saved, a vector is fetched from
$FFFC and $FFFD to the program counter, and the nonmaskable interrupt service routine starts.
Note: After reset, the stack pointer should be initialized to an appropriate memory location before any
NMI input.
2.3.7 Interrupt Requests (IR01. IR02)
The interrupt requests are level-sensitive inputs which request an internal interrupt sequence from the
CPU.
2.3.8 Mode Program (MPO. MP1)
These pins determine the operation mode. Refer to 2.1 Operation Mode for details.
Note: The following signals, RD, WR, AIW, L1R, MR, HALT, and SA, are only used in modes 1 and 2.
2.3.9 ReadIWrite (RIW; P72)
The readlwrite signal shows whether the MCU is in read (RIW high) or write (RIW low) state to the
peripheral or memory devices. It is usually high, in read state. R/W can drive one TTL load and 30 pF.
2.3.10 Read and Write (RD; P70. WR; P71)
The read and write outputs show active low outputs to peripherals or memories when the CPU is reading
or writing. This enables the CPU to access LSI peripherals with RD and WR inputs easily. These pins
can drive one TTL load and 30 pF.
2.3.11 Load Instruction Register (UR; P73)
The L1R output low shows that the instruction opcode is on the data bus. L1R can drive one TTL load
and 30 pF.
~HITACHI
390
2.3.12 Memory Ready (MR; P52)
The memory ready control input lengthens the system clock's high period to allow access to low-speed
memory. When MR is high, the system clock operates normally. But when MR is low, the high period
will be lengthened depending on its low time in integral multiples of its cycle time. It can be lengthened
up to 91JS.
During internal address or invalid memory access, MR is prohibited internally from decreasing operation
speed. Even in the halt state, MR can lengthen the high period of the system clock to allow peripheral
devices to access low-speed memories. MR is also used as P52. The function is chosen by the enable
bit in the RAM/port 5 control register (bit 2) at $0014. See 2.5 RAM/Port 5 Control Register for details.
2.3.13 Halt (HALT; P53)
The halt control input stops instruction execution and releases the buses. When HALT switches low,
the CPU finishes the current instruction, then stops and enters the halt state. When entering the halt
state, the CPU sets BA (P74) high, and sets the address bus, data bus, RD, WR, and RlW to high
impedance. When an interrupt occurs in the halt state, the CPU cancels the hall, and executes the
interrupt service routine.
Note: When the CPU is in the interrupt wait state, executing the WAI instruction, HALT should be held
high. If halt turns low, the CPU may fetch the incorrect vector after releasing the halt state (figure 2-7). If
a halt is expected, a loop should be used instead of WAI (figure 2-8) .
.
..
..
HALT input
WAI
Waiting
interrupt
~;::;
l
(Accept interrupt)
(
Incorrect Vector (MSB)
Fetch Vectors
Incorrect Vector (LSB)
Opcode Fetch
..
• Execute interrupt routine
II
..
• Branch destination undefined (CPU burst)
Figure 2-7. HALT AfterWAI
~HITACHI
391
•
•
•
•
CLI
BRA
LOOP
CLI
LOOP
WAI
•
•
•
Error Occurs
•
•
•
Recommended Example
Figure 2-8. Branch Replacement for WAI
2.3.14 Bus Available (BA; P74)
The bus available output control signal goes high when the CPU accepts HALT and releases the buses.
It is normally low. The HD6800and HD6802 bring BA high and release the buses at WAI execution, but
the HD6301 XO and HD63701 XO don't. But if HALT goes low when the CPU is in the interrupt wait state
after having executed a WAI, the CPU sets BA high and releases the buses. When HALT goes high,
the CPU returns to the interrupt wait state.
The following signals, CE and Vpp/OE, are only used in the HD63701 XO PROM programming
mode.
2.3.15 Chip Enable (CE; P57)
The chip enable input enables PROM programming and verifying. When this signal is low, the PROM is
enabled. The PROM cannot be programmed or verified with CE high.
2.3.16 Program Voltage/Output Enable (Vpp/OE)
The program voltage/output enable pin is the input for the program voltage for programming the PROM,
and the control for data verification output.
To program data from port 3 (EOO-E07) into the PROM, apply 21 V ± 0.5 V to Vpp while holding CE
low. Set the PROM address on port 1 and 4 (EAO-EA11). To verify, bring the OE pin low. The data
addressed by EAO-EA11 will be output at EOO-E07. When OE is high, port 3will be high impedance.
In the MCU modes, connect this pin to VSS.
~HITACHI
392
2.4 Ports
The HD63701XO provides seven ports (six 8-bit ports and a 5-bit port). Some pins have other uses, as
shown in table 2-2. Table 2-5 shows the addresses of the ports and their data direction registers. Figure
2-9 shows block diagrams of each port. Table 2-6 shows the state of eachport at reset.
Table 2-5. Port and Data Direction Register Address
Port
Port Address
Data Direction Register
$0002
2
$0003
$0001
3
$0006
$0004
4
$0007
5
$0015
6
$0017
7
$0018
$0016
I
~HITACHI
393
Data Bus
Data Bus
Tri-state
Control
Mode I, 2
Mode I, 2
..L
Address Bus,
Control Signal _ _...r""1.._ _ _ _ _--.J
...L
Address Bus,
Control Signal--..;-..--------l
PROM Mode
Port 4 (Bit 4 to 7), Port 7
:~~~ss Bus _ _ _ _ _r-L---,___-<
(HD637D1 XD only)
Port 1, Port 4 (Bit 0 to 3)
Data Bus
Port 5
Data Bus
Data Bus _ _ _---J-'\......_~
PROM Mode
CPU Internal Bus _I-----------J
PROM Mode
~
..L
...L
_ _-r,-_
(HD63701 XO only)
PROM Data Bus _ _ _ _ _ _ _ _...J
Port 5 (Bit 7)
(HD63701 XO only)
Port 3
Port Write Signal
Data Bus
Data Bus
Timer I, 2,
SCI Output
_+-____
~'____'
Port Read Signal
Trl-state
Control
~
Timer I, 2 , _ - - - - - - - -____C
SCI Input
Timer 1 Input
(P2 0 only) --------~
Port 6, Port 2 (Bit 0)
Port 2
Figure 2-9. Port Block Diagrams
~HITACHI
394
Table 2-6. Port at Reset (Modes 1 and 2)
Port
State at Reset
1 (AO-A7)
High
2
High impedance
3 (00-07)
High impedance
4 (AS-A15)
High
5
High impedance
6
High impedance
7
RD, WR, R1W, LlR
SA
=
=
High
Low
Note: All ports are high impedance after reset in mode 3.
2.4.1 Port 1
In the MCU modes, port 1 is an S-bit output port. In mode 3 (single-chip), port 1 is high impedance
during reset, and stays high impedance after reset is released. When the CPU writes to the port 1 data
register, the data written will appear at port 1. Once port 1 is in the output state, it operates as an output
until reset. The CPU can read the port 1 data register for bit manipulation instructions.
In modes 1 and 2, port 1 is used for the lower byte of the address bus. Port 1 can drive 1 TTL load and
30 pF.
In the PROM mode, port 1 is the lower byte of the PROM address (EAQ-EA7)'
2.4.2 Port 2
Port 2 is an S-bit input/output port. The port 2 data direction register (DDR) controls the VO state (figure
2-10). Bit 0 controls the I/O direction of P20, and bit 1 controls the direction of P21-P27' A 1 specifies
input, 0 specifies output.
Figure 2-10. Port 2 Data Direction Register
Port 2 is also used as I/O pins for the timers and SCI. In this case, port 2 pins except P20 automatically
become inputs or outputs regardless of the data direction register's value.
~HITACHI
395
A reset clears the port 2 DDR and configures port 2 as an input port. Port 2 can drive 1 TIL load and 30
pF. In addition, it can produce 1 mA at VOUT = 1.5 V to directly drive the base of Darlington transistors.
When a write-only register like a DDR is read by the MCU, $FF always appears on the internal data bus.
Whenever the MCU performs an arithmetic or logic operation between memory, and a write-only register,
the resun will be $FF. AIM, OIM, and ElM instructions cannot be applied to the DDR.
2.4.3 Port 3
Port 3 is an a-bit I/O port. The port 3 DDR controls its direction. If bit 0 of the DDR is 1, port 3 is an input
port. If it is 0, port 3 is an output (figure 2-11). The DDR is cleared during reset. In modes 1 and 2, port 3
is the data bus (DO-D7). In the HD63701XO PROM mode, port 3 is the PROM data bus (EOO-E07). In
the PROM mode, port 3's direction is controlled by OE, not the DDR. Port 3 can drive 1 TIL load and 90
pF.
765432
0
I - - I - I - I- I -I - I~oDrt~ I
$0004
Figure 2-11. Port 3 Data Direction Register
2.4.4 Port 4
Port 4 is an a-bit output-only port like port 1. In modes 1 and 2, it outputs the upper byte of the address
(Aa-A15). In the HD63701XO PROM mode, P40-P43 are used as the upper PROM address bits
(EAa- EA 11)·
2.4.5 Port 5
Port 5 is an a-bit input-only port. The lower four bits (P50-P53) are also used for interrupt, MR and HALT
input. In the HD63701XO PROM mode, P57 is used as CE to control the PROM.
2.4.6 Port 6
Port 6 is an a-bit I/O port. Each bit in the port 6 data direction register controls the direction of the
corresponding bit of port 6. A 1 specifies input, 0 speCifies output. Port 6 ~an drive 1 TIL load and 30
pF. In addition, it can produce 1 mA at VOUT = 1.5 V to directly drive the base of Darlington transistors.
A reset clears the port 6 DDR.
~HITACHI
396
2.4.7 Port 7
Port 7 is a 5·bit output port. In mode 3, port 7 is high impedance during and after reset. When the CPU
writes to the port 7 register, the data will appear at port 7. Once port 7 is in the output state, it will be an
output until reset. The CPU can read the port 7 data register for bit manipulation instructions. Bits 5-7
will be read as 1.
In modes 1 and 2, port 7 is used for control signals (RD, WR, RNI, LlR, and BA). Port 7 can drive 1 TTL
load and 30 pF.
2.5 RAM/Port 5 Control Register
The control register (figure 2-15) located at $0014 controls on-chip RAM and port 5.
Figure 2-15. RAM/Port 5 Control Register
2.5.1 IRQ Enable (IRQ1E, IRQ2E)
When IRQ1 E and IRQ2E are 1, P50 and P51 are interrupt pins IRQ1 and IRQ2' When these bits are 0,
the CPU doesn't accept external interrupts. External interrupts won't cancel the sleep state. These bits
are 0 after reset. Bits 0, 1.
2.5.2 Memory Read Enable (MRE)
When MRE is 1, P52 is used as the memory ready (MR) signal. When it is 0, the MR signal is inhibited. In
mode 3, the MR signal is inhibited regardless of MRE. MRE becomes 1 after reset. Bit 2.
2.5.3 Halt Enable (HL TE)
When HLTE is 1, P53 is used as the HALT input. When 0, the halt function is inhibited. In mode 3, the
HALT signal is inhibited regardless of the value of HLTE. HLTE becomes 1 after reset.
Note: When using P52 and P53 for port bits in modes 1 and 2, clear MRE and HLTE after reset. If P52 or
P53 is brought low before MRE or HLTE are cleared, a memory ready or halt will be accepted. Bit 3.
~HBTACHI
397
2.5.4 RAM Enable (RAME)
RAME controls on-chip RAM. When RAME is 0, on-chip RAM is disabled, and the CPU can read from
external memory at addresses $0040-$OOFF in modes 1 and 2. RAME is 1 after reset and on-chip RAM
is enabled. RAME should be set to 0 at the beginning of standby mode to protect on-chip RAM. Bit 6.
2.5.5 Standby Power (STBV PWR)
When Vee is not provided in standby mode, STBY PWR is cleared. The STBY PWR flag can be read
and written by software. If it is set to 1 before standby mode and remains set after returning from standby
mode,
Vee has been provided during standby, and on-chip data is valid.
Dissipation Mode. Bit 7.
~HITACHI
398
Refer to 3.5 Low Power
Section 3. CPU Function
3.1 CPU Registers
The CPU has three 16-bit registers and three 8-bit registers (figure 3-1).
7
0
~ ____ ! _____
7
U_____ ~ ____
0
0
15
15
I
X
15
I
I
8 -Bit Accumulators A and B
Or 16-Bit Double Accumulator D
D
I
1
0
Index Register (X)
0
I
SP
15
Stack Pointer (SP)
0
I
PC
7
11
r
Program Counter (PC)
0
I Iz IV IC ICondition Code Register (CCR)
1 1H 1 I N
~ Carry/Borrow from
MSB
Over flow
Zero
Negative
Interrupt
Half Carry (From Bit 3)
Figure 3-1. CPU Registers
3.1.1 Accumulators (ACCA, ACCs, ACCD)
Two 8-bit accumulators, ACCA and ACCB, store the result of arithmetic/logic operations and data. When
combined, these make up the i6-bit accumulator ACCD used for 16-bit operations. Note that the
contents of ACCA and ACCB are destroyed by an ACCD operation.
3.1.2 Index Register (IX)
The i6-bit register IX stores 16-bit data for use in indexed addressing or for general purposes.
3.1.3 Stack Pointer (SP)
The contents of the16-bit register SP indicate the address of a stack. SP can also be used as a
general-purpose register.
3.1.4 Program Counter (PC)
The contents of the 16-bit PC indicate the address of the instruction being executed. Note that
software cannot access this register.
@HITACHU
399
3.1.5 Condition Code Register (CCR)
The CCR register consists of the carry (C), overflow (V), zero (Z), negative (N), interrupt mask (I), and
half-carry (H) bits. After an instruction is executed, the CCR bits change state depending on the result of
the operation. They can be tested by conditional branch instructions. The upper two bits of this register
are not used.
Half-Carry (H):H is set to 1 if a carry at bit 3 or bit 4 occurs during an ADD, ABA, or ADC instruction. It
is cleared if no carry occurs.
Interrupt Mask (I) :When I is set to 1, it. disables all maskable interrupts (IR01, IR02, and IR03)'
Negative (N): N is set to 1 if the MSB of the result of an operation is 1. N is cleared if it is O.
Zero (Z): Z is set to 1 if the result of an operation is zero. Z is cleared if it is not zero.
Overflow (V): V is set to 1 if the result of an operation shows a two's complement overflow. It is
cleared if there is no overflow.
Carry (C): C is set to 1 if a carry or borrow is generated from the MSB. If there is no carry or borrow, it is
cleared.
3.2 Addressing Modes
The HD6301XO, HD6303X, and HD63701XO instructions have seven addressing modes.
3.2.1 Accumulator Addressing (ACCX)
The instruction addresses an accumulator and ACCA or ACCB is selected. Accumulator addressing
instructions take one byte.
3.2.2 Immediate Addressing
Immediate addressing places the data in the second byte of an instruction, except LOS and LOX, which
use the second and third bytes. An immediate instruction causes the CPU to address this operand.
Immediate instructions take 2 or 3 bytes.
3.2.3 Direct Addressing
In direct addressing, the second byte of an instruction holds the address where the data is stored. 256
¢!)HITACHI
400
bytes ($OO-$FF) can be addressed directly. Storing data in this area reduces instruction time, .so
configuring $OO-$FF as user's RAM is recommended. Direct addressing instructions take 2 bytes, or 3
bytes for AIM, OIM, ElM, or TIM.
3.2.4 Extended Addressing
In extended addressing, the second byte of an instruction holds the upper eight bits of the absolute
address of the stored data, and the third byte holds the lower eight bits. Extended addressing
instructions take 3 bytes.
3.2.5 Indexed Addressing
In indexed addressing, the second byte of the instruction (third byte for AIM, OIM, ElM, or TIM
instructions) is added to the lower eight bits of the index register. The carry is added to the upper eight
bits of the index register, and the 16-bit sum is the memory location of the data. The modified address is
held in the temporary address register, so the index register doesn't change. Indexed addressing
instructions take 2 bytes, or 3 bytes for AIM, OIM, ElM, or TIM.
3.2.6 Implied Addressing
In implied addressing, the instruction itself specifies the address. For example, the instruction
addresses the stack pointer or index register. Implied addressing instructions take 1 byte.
3.2.7 Relative Addressing
In relative addressing, the second byte of the instruction and the lower eight bits of the program counter
are added. The carry or borrow is added to the upper eight bits of the program counter. Locations from
-126 to +129 bytes from the current location can be addressed. Relative addressing instructions take 2
bytes.
~HITACHI
401
3.3 Instruction Set
The HD6301XO, HD6303X, and HD63701XO are object-code upwardly compatible with the HD6801 to
use all instructions of the HMCS6800. The instruction time of key instructions has been reduced,
improving throughput.
3.3.1 Additional Instructions
Bit manipulation, index register and accumulator exchange, and sleep instructions have also been
added to the HD6801 instruction set. AIM, OIM, EOM, and TIM are 3 byte instructions. The first byte is
the opcode, second byte is the immediate data, and the third byte is the address modifier.
AIM: ANDs the immediate data with the memory contents and stores the result in memory. (M) AND
(IMM) -. (M).
OIM: ORs the immediate data with the memory contents and stores the result in memory. (M) OR (IMM)
-. (M).
ElM: EORs the immediate data with the memory contents and stores the result in memory. (M) EOR
(IMM) -, (M).
TIM: ANDs the immediate data with the memory contents and changes the related flag in the condition
code register. (M) AND (IMM).
XGDX: Exchanges the contents of the accumulator with the contents of the index register. (ACCD) .-,
(IX).
SLP: Puts the MCU into sleep mode. Refer to 3.5 Low Power Dissipation Mode for details.
3.3.2 Instruction Set Summary
Tables 3-1 to 3-5 summarize the instruction set.
Accumulator and memory manipulation instructions: table 3-1
•
Index register and stack manipulation instructions: table 3-2
•
Jump and branch instructions: table 3-3
•
Condition code register manipulation: table 3-4
•
Opcode map: table 3-5
~HITACHI
402
Table 3-1. Accumulator and Memory Manipulation Instructions
Condition Code
Register
Addressing Modes
IMMED
DIRECT·
EXTEND
IMPLIED
-
4
3
2
1
0
H
I
N
Z
V
C
I
•
I
I
I
I
•
• •
J
J
:
J
J
J
!
J
•
•
•
J
J
J
J
J
J
J
J
J
J
J
!
J
I
R
J
J
R
Boolean/
5
Arithmetic Operation
-
#
-
#
ADDA
8B
2
2 9B 3
2 AB 4
2 BB 4
3
A+M~A
ADDB
CB
2
2 DB 3
2 EB 4
2 FB
4
3
B+M~B
Add Double
ADDD
C3
3
3
D3
4
2 E3
5
2 F3
5
3
A:B+M:
A:B
Add Accumulators
ABA
A+B~A
J
Add With Carry
ADCA
89
2
2 99
3
2 A9
4
2 B9 4
3
A+M+C~A
J
ADCB
C9
2
2 D9 3
2
E9
4
2 F9
3
B+M+C~B
J
4
Operations
Add
AND
Bit Test
Clear
Compare
Mnemonic OP
OP
-
INDEX
#
OP
-
#
OP
OP
IB
4
1
#
1
I
M+l~
ANDA
84
2
2 94
3
2 A4
2 B4 4
3
A· M-·B
• •
ANDB
C4
2
2 D4
3
2 E4 4
2 F4
3
B· M-B
BIT A
85
2
2 95
3
2 A5
4
2 B5
4
3
A·M
BIT B
C5
2
2 D5
3
2 E5
4
2 F5
4
3
B·M
• •
•
• •
6F
5
2 7F
5
3
4
0
OO~M
• •
R
5
R
1
1
OO~A
0
R
5
R
R
CLRB
5F
1
1
OO~B
• •
R
5
R
R
• •
•
J
J
J
J
0
J
J
J
J
A-B
• •
J
J
J
J
M~M
0
J
J
R
S
CMPA
81
2
2 91
3
2 Al
4
2 Bl
4
3
A-M
CMPB
Cl
2
2 Dl
3
2
4
2 Fl
4
3
B-M
Complement, 1's
COM
El
11
63
6
2 73
6
1
1
3
43
1
1
A~A
0
0
J
I
R
5
53
1
1
B~B
0
•
I
I
R
5
OO-M~M
0
•
I
J
CD (V
(Negate)
NEGA
40
1
1
OO-A~A
NEGB
50
1
1
OO-B~B
Oecimal Adjust. A
DAA
19
2
1
Converts binary
add of BCD characters into BCD
format
Decrement
DEC
DECA
4A
1
1
DECB
5A
1
1
B-l~B
•
Load Double
Multiply Unsigned
OR,lnciusive
Push Data
0
R
COMB
NEG
Accumulator
0
COMA
Complement, 2'5
Load
Accumulator
R
R
4F
CLR
CBA
Increment
J
J
CLRA
Compare
Accumulators
Exclusive OR
J
J
•
•
•
•
60
6A
EORA
88
2
2 98
EORB
C8
2
2 D8 3
3
6
6
6
2 7A 6
3
3
J
J
CD
I
I
CD
m
m
• •
J
I
I
0)
M-l···M
• •
I
I
®
•
A-l~A
0
•
I
J
@
I
I
@
R
•
•
•
2 B8
4
3
AEBM~A
E8
4
2 F8
4
3
BEBM~B
6C
6
2 7C
6
3
M+l~M
2 A8 4
2
INC
2 70
INCA
4C
1
1
A+l~A
INCB
5C
1
1
B+l~B
LDAA
86
2
2 96
3
2 A6 4
2 B6
4
3
M~A
LDAB
C6
2
2 D6
3
2
E6
4
2 F6
4
3
M-B
LDD
CC
3
3
4
2
EC
5
2
5
3
DC
FC
MUL
M+l~B.M~A
3D
7
1
AXB-·A: B
ORAA
8A
2
2
9A
3
2
AA
4
2 BA 4
3
A+M~A
ORAB
CA
2
2 DA
3
2 EA
4
2 FA
3
a+M~B
4
PSHA
36
4
1
PSHB
37
4
1
A~Msp,
SP-l~SP
B~Msp,
SP-l~SP
• •
• •
.
•
• •
0
• •
• •
• •
•
•
•
•
•
J
I
I
!
R
•
J
!
®
•
•
•
J
I
®
:
I
®
•
I
J
R
•
I
J
R
•
I
!
R
•
• • • •
Ijj)
.1
•
!
!
R
•
•
•
• • • • • •
• • • • • •
• •
J
I
R
Note: Condition Code Register will be explained in Note of table 3-4.
$HITACHD
403
Table 3-1. Accumulator and Memory Manipulation Instructions (Cont.)
Condition Code
Addressing Modes
IMMED
Operations
-
Mnemonic OP
Pull Data
Rotate Left
DIRECT
INDEX
-
-
# OP
# OP
Shift Right
Arithmetic
Accumulator
1
ROLB
59
1
1
•
•
•
"2
•
•
• •
"3
• •
• •
"4
• •
• •
"5
• •
• •
• •
"6
• •
• •
"7
• •
A-M
• •
B-M
• •
A-M
• •
B-M+1
A-M···A
• •
B-M-B
• •
A:8-M: M+1• •
A:B
. - f-t-A-B-A
• •
A-M-C-A
• •
B-M-C-B
• •
• •
B-A
• •
M-OO
• •
A-OO
• •
B-OO
• •
M·IMM-M
• •
M+IMM-M
• •
MEBIMM-M
• •
M·IMM
• •
66
6
2
2
79
76
6
6
3
RORA
46
1
1
RORB
56
1
1
68
6
2
78
6
3
ASLA
48
1
1
ASLB
58
1
1
ASLD
05
1
1
ASRA
47
1
1
ASRB
57
1
1
67
6
64
6
2
2
77
74
6
6
3
3
44
1
1
LSRB
54
1
1
LSRD
04
1
1
STAA
97
3
2
A7
4
2
B7
4
3
STAB
D7
3
2
E7
4
2
F7
4
3
4
2
ED
5
2
FD 5
3
90
3
2
AO
4
2
BO
4
3
SUBB
CO
2
2
DO
3
2
EO
4
2
FO
4
3
SUBD
83
3
3
93
4
2
A3
5
2
B3
5
3
Subtract
Accumulators
SBA
Sabtract
SBCA
82
2
2
92
3
2
A2
4
2
B2
4
3
SBCB
C2
2
2
D2
3
2
E2
4
2
F2
4
3
10
1
1
With Carry
TAB
16
1
1
TBA
17
1
1
TSTA
4D
1
1
TSTB
5D
1
1
TST
2
And Immediate
AIM
71
6
3
61
7
3
OR Immediate
OIM
72
6
3
62
7
3
EOR Immediate
ElM
75
6
3
65
7
3
Test Immediate
TIM
78
4
3
6B
5
3
"2
M
"4
ll.o-1 I
C
04
A7
C
If--l
A
B
bO
b7
Ace A I Ace 8
AO
87
"5
\--0
80
"7
o--l
A7
Ace A I Ace
AO .87
8
7D
4
3
ll..Q.l I
C
If-l
b7
bO
I-[]
80
C
"1
•
A~B
"3
-
M
I
I
lID
I
I
I
lID
I
I
I
lID
I
I
I
lID
I
I
I
lID
I
I
I
lID
I
I
I
lID
I
I
I
lID
I
I
I
lID
I
I
I
tID
I
I
I
lID
I
I
I
lID
I
I
I
lID
I
R
I
lID
I
R
I
lID
I
R
I
lID
I
R
I
lID
!
I
I
R
I
I
R
R
•
•
•
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
j
I
I
I
I
I
I
I
R
I
I
R
•
•
r
I
R
R
I
I
R
R
I
I
R
R
I
I
R
I
I
R
I
I
R
I
I
R
•
•
•
•
bO
b7
~l[{1 I I I I I I I-[]
8
404
4
6D
Msp'~A
3
DD
B
• • • • •
• • • • •
1
6
2
A
•
•
•
•
•
•
•
•
49
69
2
"1
C
ROLA
80
M
V
SP+1-SP.
STD
_.
Z
SP+1·.. SP.
Msp-B
SUBA
Test Zero or
Minus
0
N
1
Subtract
Transfer
Accumulators
1
I
1
Store Double
Accumulator
Double Subtract
2
H
3
LSRA
Store
3
Arithmetic Operation
3
LSR
Double Shift
Right Logical
#
4
33
ASR
Shift Right
Logical
-
# OP
5
PULB
ASL
Double Shift
Left, Arithmetic
-
# OP
Boolean/
32
ROR
Shift Left
Arithmetic
IMPLIED
PULA
ROL
Rotate Right
Register
EXTEND
~HITACHI
C
"6
l
~ o--l I I I I I I I I-[]
B
b7
bO
C
Table 3-2. Index Register and Stack Manipulation Instructions
Condition Code
Addressing Modes
IMMED
Pointer
Operations
Compare Index Reg
Mnemonic OP
CPX
8C
DIREC'F
-
#
OP
3
3
9C
INDEX
-, -,
OP
4
2 AC
5
2
Register
EXTEND
IMPLIED
OP
-
, -,
BC
5
3
OP
5
4
3
2
I
0
Arilhmetic Operation
H
I
N
Z
V
C
I
I
X-M:Mtl
• •
I
I
I
X-I-X
• • •
I
I
SP-I-'SP
I
I
Xtl··X
I
I
SPt I--SP
•
•
•
Decrement Index
Reg
DEX
09
I
Decrement Stack Pntr
DES
34
I
Increment Index Reg
INX
08
Increment Stack Pntr
INS
31
Load Index Reg
LOX
CE
3
3
DE
4
2
EE
5
2
FE
5
3
Load Stack Pntr
LOS
8E
3
3 9E
4
2 AE
5
2
BE
5
3
Store I ndex Reg
STX
OF
4
2
EF
5
2
FF
5
3
Store Stack Pntr
STS
9F
4
2
AF
5
2
BF
5
3
Index Reg - Stack
Pntr
Stack Pntr-Index
Reg
Boolean/
M-··XH.
(Mtl) ··XL
M-,SPH.
(Mt I) -SPL
Xw-M,
XL- (Mtl)
SPH -M,
SPL -(Mtl)
TXS
35
I
I
X-I-SP
TSX
30
I
I
SPtl-X
Add
ABX
3A
I
I
BtX-X
Push Data
PSHX
3C
5
I
Pull Data
PULX
38
4
I
XL ··Msp, SP I-SP
XH -Msp. SP-I-'SP
SPtl-SP,Msp-XH
SPt I-SP, MSp-XL
Exchange
XGDX
18
2
I
ACCD-IX
•
• • • •
• • I •
• • • •
• (ZJ I R
•
• •
(ZJ
• •
(ZJ
• •
(ZJ
•
•
•
•
• •
• •
• •
• •
•
• • •
0
0
•
•
•
•
•
R •
I
R •
I
R •
I
• • •
• • •
• • •
• • •
• •
• • •
0
Note: Condition Code Register will be explained in Note of table 3-4.
~HITACHI
405
I
Table 3-3. Jump and Branch Instructions
Condition Code
Register
Addressing Modes
RELATIVE
Operations
Mnemonic OP
- ,
DIRECT
OP
-
INDEX
EXTEND
OP
OP
5
4
3
2
1
0
Branch Test
H
I
N
Z
V
C
•
•
•
•
•
• • •
• • •
• • •
• • •
•
•
•
•
• •
• •
• •
• •
•
•
IMPLIED
, -, -, -,
OP
Branch Always
'BRA
20
3
2
None
Branch Never
BRN
21
3
2
None
Branch if Carry
Clear
BCC
24
3
2
C=O
Branch if Carry Set
BCS
25
3
2
C=l
Branch if = Zero
BEQ
27
3
2
Z=l
if~Zero
BGE
2C
3
2
NEfW=O
Branch if> Zero
BGT
2E
3
2
Z + (NEf'JVl = 0
Branch if Higher
BHI
22
3
2
C+Z=O
BlE
2F
3
2
Z+(NE!1V)=1
BlS
23
3
2
C+Z=l
Branch
Branch
i1~Zero
Branch if lower Or
Same
Branch if < Zero
BlT
20
3
2
NE!1V= 1
Branch if Minus
BMI
2B
3
2
N=!
Branch if Not Equal
Zero
Branch if Overflow
Clear
Branch if Overflow
Set
BNE
26
3
2
Z=O
BVC
28
3
2
V=O
BVS
29
3
2
V=I
N=O
Branch if Plus
BPl
2A
3
2
Branch To Subroutine
BSR
80
5
2
Jump
JMP
f---6E
3
2
7E
3
3
AD
5
2
BD
6
3
t--
Jump To Subroutine
JSR
No Operation
NOP
01
1
1
Return from Interrupt
RTI
3B 10
1
Return From
Subroutine
RTS
39
Software Interrupt
SWI
Wait for Interrupt'
WAI
Sleep
SlP
90
5
- - I--
-1-
2
5
3F 12
1-- - I-3E 9
--_.- t-- . - --- I-lA 4
Note: 'WAI puts R/W high; Address Bus goes to FFFF; Data Bus goes to the three state.
Condition Code Register will be explained in Note of table 3-4.
~HITACHI
406
1
1
1
-1
Adva nces Prog.
Cntr. Only
• •
• • •
• • •
• • •
•
•
•
•
• • •
• • •
• • •
• • •
.. • • .
• • • •
• • • •
• • • •
• • • •
• • • •
-1-• • • •
• • • ..
•
•
•
•
•
•
• •
• •
• •
• •
.. ..
• •
• •
• •
• •
• •
• •
.. •
---@I---
• •
•
•_.• •
I - I-S
@
•
•
•
•
• • •
• • •
• r-• -•
• • •
.- r-
Table 3-4. Condition Code Register Manipulation Instructions
i
: Addressing
J.~;~;~;r:1
i Mnemonic
Operations
1 CLC
Clear Carry
Modes :
i
OC
1
: Condition Code Register
I0
1
r*iH-H+~
Boolean Operation
'C
..
1 •
I •
1 •
_____.. __ J._~_
~~Pt Ma~~_+s_~
: OD; 1 iIi 1 ·C
~~~_~_~_l_i~~:'-
_____ ~ ___ l
i
~
r:T: :
~:_~S~Ma~~___ .___ .-~-+~!- i--~_T'lIT~~' .- ---------=E± : ::
~~Carry
i• I•
.1. I •
I •
'.
S
_____________ +;-+2.~+;_~_~_
Set Overflow -----i-c~~V------- __ __l_o~~--.1-LLl.!---~-----~----_t.!J..4IIl!-L4IIL~
Accumulator A-'CCR
i TAP
I 06
1 : 1 ! A 'CCR
i
------ @----
i
CCR·Accumulator A
I TPA
, i : CCR
I 07
·A
Legend
OP Operation Code (Hexadecimal)
Number of MCU Cycles
Msp Contents of memory location pointed to by Stack Pointer
#
Number of Program Bytes
+ Arithmetic Plus
Arithmetic Minus
•
Boolean AND
Boolean Inclusive OR
EB Boolean Exclusive OR
M
Complement of M
Transfer into
OBit = Zero
00 Byte = Zero
Condition Code
(Bit V)
CII (Bit C)
® (Bit C)
® (Bit V)
® (Bit V)
® (Bit V)
!J) (Bit N)
® (All Bit)
® (Bit I)
® (AI Bit)
(jJ) (Bit C)
I. •
1•
Condition Code Symbols
H
Half-carry from bit 3 to bit 4
I
Interrupt mask
N
Negative (sign bit)
Z
Zero (byte)
V
Overflow. 2's complement
C
Carry IBorrow from/to bit 7
R
Reset Always
S
Set Always
I Set if true after test or clear
•
Not Affected
+
Note:
I•
i • I •
Register Notes: (Bit set if test is true and cleared otherwise)
Test: Result = 10000000?
Test: Result = OOOOOOOO?
Test: BCD Character of high-order byte greater than 10? (Not cleared if previously set)
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
Test: Set equal to N + C = 1 after the execution of instructions
Test: Result less than zero? (Bit 15= 1)
Load condition code register from stack.
Set when interrupt occurs. If previous set, a non-maskable interrupt is required to exist the wait state.
Set according to the contents of accumulator A.
Result of multiplication bit 7= 1? (ACCB)
(i)
Table 3-5. Memory Map
OP
ACC
ACC
CODE
A
B
IND
~
0000 0001
0010 0011
~L
OIR'i IMM
0100 0101
0110 0111
IND
100011001
i
ACCB or X
ACCAorSP
I DIR
i
IMM
EXT
1010 1011
DIR
IND
1100 1101
I EXT
111011111
0
1
2
3
0000
0
/'
SBA
BRA
TSX
NEG
0001
1
Nap
CBA
BRN
INS
i
0010
2
/
BHI
PULA
0011
3
BLS
PULB
0100
4
LSRD
/
BCC
DES
0101
5
ASLD
BCS
TXS
0110
6
TAP
TAB
BNE
PSHA
ROR
0111
7
TPA
TBA
BEQ
PSHB
ASR
1000
8
INX
XGDX
BVC
PULX
ASL
EaR
8
1001
9
DEX
DAA
BVS
RTS
ROL
ADC
9
1010
A
CLV
SLP
BPL
ABX
DEC
ORA
A
lOll
B
SEV
ABA
BMI
RTI
ADD
B
1100
C
CLC
BGE
1101
0
SEC
1110
E
CLI
Illl
F
SEI
La
/
/
/
0
IZI UNDEFINED
V
L
4
6
5
-------------
8
PSHX
INC
BLT
MUL
TST
BGT
WAI
BLE
SWI
I
2
3
D
E
I
F
0
i
CMP
1
aiM
I
SBC
2
:
SUBD
ElM
ADDD
3
AND
4
BIT
5
6
LDA
/1
/1
STA
TIM
CPX
BSR
i
6
i
VI
/1
7
8
I
C
STD
D
E
A
/1
C 1 DiE 1
STX
STS
9
7
LOX
LOS
CLR
STA
LOD
JSR
JMP
5
C
AIM
LSR
~
4
B
SUB
~:
-------
A
9
COM
/
/'
/'
OP CODE
• Only AIM, OIM, ElM, TIM instructions
7
I
B
F
F
~HITACHI
407
3.4 CPU Instruction Flow
When operating, the CPU fetches an instruction from memory and executes the required function. This
sequence starts from RES high, and repeats itself continuously if not affected by a special instruction or
control signal. SWI, RTI, WAI, and SLP instructions change this operation, and NMI, IR01, IR02, IR03,
HALT, and STBY control it. Figure 3-2 shows the CPU mode transitions, and figure 3-3 is the CPU
system flowchart. Table 3-6 shows the CPU operating states and port states.
Figure 3-2. CPU Operation Mode Transitions
~HITACHI
408
PC-1
PC-1
VECTORING
STACK
PC, IX
ACCA
Aces
GGR
Notes; 1. The program sequence will come to the RES start from
any place of the flow during RES. When STBY=O, the
sequence will go into the standby mode regardless of the CPU
condition.
2. Refer to 3.8 Interrupts for more details of interrupts.
~
J:
~
o
:I
-l'-
o
<0
Figure 3-3. System Flowchart
--
Table 3-6. CPU Operating States and Port States
Halt4
Port
Mode
Reset
Standby 3
1 (AO-A7)
1,2
High
High impedance High impedance High
3
High impedance High impedance·
Keep
1,2
High impedance High impedance Keep
Keep
3
High impedance High impedance
Keep
1,2
High impedance High impedance High impedance High impedance
3
High impedance High impedance
1,2
High
3
High impedance High impedance
1,2
High impedance High impedance High impedance High impedance
3
High impedance High impedance
High impedance
1,2
High impedance High impedance Keep
Keep
3
High impedance High impedance
Keep
1,2
Note 1
Note 1
3
High impedance High impedance
2
3 (00-07)
4 (Aa-A1S)
S
6
7
Sleep
Keep
High impedance High impedance High
High impedance Note 2
Keep
Keep
Notes:
1.
RO, WR, R1W, LlR =high; BA =low
2.
RO, WR, RfW = high impedance; LlR, BA = high
3.
E is high impedance in standby state.
4.
HALT cannot be accepted in mode 3.
3.5 Low Power Dissipation Modes
The MCU has two low power dissipation modes, sleep and standby. Table 3-7 shows the MCU staie in
sleep and standby modes.
~HITACHI
410
Table 3-7. Sleep and Standby Modes
Sleep Mode
Standby Mode
Oscillation circuits
Continue operation
Stop
CPU
Stop
Stop
CPU registers
Hold
Undefined
RAM
Hold
Hold
I/O pins
Hold
High impedance
Timers
Continue operation
Stop
SCI
Continue operation
Stop
Internal Registers
Hold
Reset
How to release
Interrupt
STBY= low
Reset start
STBY = high before reset start
(Hold RES low after STBY high until
oscillator stabilizes, 20 ms min)
3.5.1 Sleep Mode
The MCU goes into sleep mode when the SLP instruction is executed. In the sleep mode, the CPU
stops operation while maintaining the registers' contents. Peripherals such as the timers and the SCI
continue their functions. One-fifth as much power is dissipated in sleep mode as in the operating mode.
The sleep mode is terminated by an interrupt, or a RES or STBY signal. RES causes the MCU to reset,
STBY causes it to go into standby mode. When the CPU receives an interrupt request, it returns to
operating mode. If the interrupts are enabled, it branches to the interrupt service routine. If they are
masked, it executes the next instruction. However, if timer 1 or 2 prohibits a timer interrupt, the CPU
won't cancel the sleep mode because there is no interrupt request to the CPU.
The sleep mode reduces power dissipation for a system that doesn't need the CPU's continuous
operation. Figure 3-4 is the sleep instruction timinQ chart.
f--~------';J-"''''''-~-.
Internal
EcIOCk.~
Stop In
Sleep
mode clock
DATA
BUS
Sleep IS cleared
with Interrupt
masked
LJ'T1E2
Sleep Inslructlon
~",,,".".p'.2,.""~e
/
Address
bUSWhe.re
--~
sleep ,s cleared
Interrupt occurs
without Interrupt
masked
Program
Figure 3-4. Sleep Instruction Timing
$HITACHI
411
3.5.2 Standby Mode
When the STBY input goes low, the MPU stops a" clocks and goes to the reset state. In this mode,
power dissipation is greatly reduced. All pins except VCC' VSS' STBY, and XTAL (outputs 0) are
detached from the MCU internally, and go to high impedance.
In standby mode, power is supplied to the MCU, so that the contents of RAM are retained. The MCU
returns from this mode with a reset.
An example of the use of this mode follows. First, save the CPU state and SP contents in RAM by an
NMI routine. Then disable the RAME bit in the RAM control register and set the STBY PWR bit to go to
standby mode. If the STBY PWR bit is still set after reset start, power has been supplied to the MCU and
the RAM contents have been retained properly. The system can restore itself by returning the
pre-standby information to the SP and registers. Figure 3-5 shows the timing at the NMI, RES and STBY
pins.
Note: In standby mode, the mode program pins, MPO and MP1, should be held according to the
operation mode. If they are opened, the standby current will increase over the specified value.
vee
CD
CD
NMI
@
RES
Ir----l
NM1
MCU
111111
I
I
~I
I
I
I
I
I
I
I
CV
RES
STSY
IIIIII
I
@
I
I
H
Save Registers
RAM/Port 5 Control
Register Set
Figure 3-5. Standby Mode Timing
$HITACHI
412
\r-fT
I
I
I
I
~
Oscillator
Start Time
f-----
Restart
3.6 Trap Function
The CPU generates an interrupt with the highest priority (TRAP) when it fetches an undefined
instruction or an instruction from outside of memory space. The trap function prevents system
malfunctions caused by noise or program error.
3.6.1 Opcode Error
When the CPU fetches an undefined opcode, it saves the CPU registers as well as performing the
normal interrupt procedure and branches to TRAP ($FFEE, $FFEF). This has the highest priority next to
reset.
3.6.2 Address Error
When an instruction is fetched from outside the intemal ROM, RAM, and external memory area, the MCU
generates an address interrupt as well as an opcode error. But on a system with no external memory, a
trap is not generated if an instruction is fetched from the external memory area. Table 3-8 shows the
I
addresses where an address error occurs in each mode. This function is available only for an instruction
fetch, and does not apply to data read/write.
Table 3-8. Address Error Addresses
Mode
Address
$0000-$001 F
2
$0000-$001 F
·3
$0000-$003F,
$0100-$EFFF
3.6.3 Caution
The trap function has a retry function other interrupts do not have. The program flow returns to the
address where the trap occured when RTI returns the CPU to the main routine from the TRAP routine.
The retry can prevent problems caused by noise, etc. However, if another trap occurs, the program can
repeat the retryITRAP cycle forever. Consideration is necessary in programming.
In figure 3-6, after executing instruction OPn, the MPU fetches and decodes an undefined opcode and
generates a trap interrupt. When the RTI is executed in the trap interrupt servicing routine, the MPU will
put $FF03 in the PC, fetch the same opcode, and generate the trap again. The MPU will endlessly
repeat loop ABC.
~HITACHI
413
,
In figure 3-7, after executing the BSR, the branch destination address is output to the address bus to
fetch the first instruction of the subroutine. If $0001 is erroneously output as the address, the MPU will
decode it and generate a trap interrupt. When the RTI is executed in the trap interrupt servicing routine,
the MPU will put $0001 in the PC, and start from this address. This will generate another trap, in an
endless loop.
$FF01
OPn
$FF02
BSR
$FF02
Operand
$FF03
01
$FF03
Undefinition
$FF04
OPn
$FF04
OPn+1
c
Figure 3-6. Executing an Undefined Opcode
Figure 3-7. Erroneous Fetch
3.7 Reset
To reset the MCU during operation, hold RES low for at least 3 system-clock cycles. At the third cycle,
when the clock signal is low, all the address buses become high. While RES is low, the buses remain
high. When RES goes high, the MCU starts the following operations.
1.
Latches the value of the mode program pins, MP1 and MPO.
2.
Initializes the internal registers (see table 2-3).
3.
Sets the interrupt mask bit. For the CPU to recognize the maskable interrrupts IR01, IR02, and
IR03, this bit should be cleared in advance.
4.
Puts the contents (= start address) of the last two addresses ($FFFE, $FFFF) into the program
counter and starts the program from this address. See table 2-4.
The MCU cannot accept a reset input until the clock oscillation is stable after power-on (20 ms maximum).
This is because the reset signal is internally synchronized to the clock as shown in figure 3-8. Until
oscillation starts, the MCU and I/O pins are undefined. External devices that need to know the MPU's
state during this period must be informed by external circuits. Refer to 2.4 Ports for the state of the ports
rluring reset. Figure 3-9 shows reset timing.
Internal reset signal
RES pin
Inside the LSI
Figure 3-8 Reset Circuit
~HITACHI
414
Internal A
_~\\\\\\\\\\\\\\\\\\\\
Internal W
_~\\\\~\\\\\\\\\\\~
RIW
_~\\\~\\\\\\\\\\W
AD
_!\\~\\\\\\\\\\\\\\\\W
\VA
_*\\\\\\\\\\~\\\W
Data Bus
j~
~-----~r---------ij-
I
~r---------irj---------H~~~j
jjv
\O:}->~i
.~\\\\'\\\\\\\\\\\\\\\'\\\\\\~)---------y--Q-;~r---------ijj-----PCB
pelS
peo
PCl
First
Instruction
I
Figure 3-9 Reset Timing
3.8 Interrupts
The CPU will complete the current instruction before accepting the request. If the interrupt mask bit in
the condition code register is set, the request will be ignored. When the interrupt sequence starts, the
contents of the program counter, index register, accumulators, and condition code register will be saved
onto the stack. Then the CPU sets the interrupt mask bit and will not respond to further mask able
interrupt requests. In the last cycle of the interrupt, the CPU fetches the vectors shown in table 3-9,
transfers their contents to the program counter and branches to the interrupt service routine.
The external interrupt pins IR01 and IR02 are also used as P50 and P51. The function is chosen by the
enable bits in the RAM/port 5 control register (bits 0 and 1) at $0014. See 2.5 RAM/Port 5 Control
Register for details.
When one of the internal interrupts, ICI, OCI, TOI, CMI, or SIO is generated, the CPU produces the
internal interrupt signal, IR03. IR03 functions just the same as IR01 or IR02, except for its vector
address. Table 3-9 is an interrupt vector map, figure 3-10 is the interrupt sequence, and figure 3-11 is
the interrupt circuit block diagram.
~HITACHD
415
Table 3-9. Interrupt Vector Memory Map
)l~~!;U
Priority
MSB
Highest
Lowest
!.a"ilIiao
LSB
Interrupt
FFFE
FFFF
RES
FFEE
FFEF
TRAP
FFFC
FFFD
NMI
FFFA
FFFB
SWI (Software interrupt)
FFF8
FFF9
IRQ1
FFF6
FFF7
ICI (Timer 1 input capture)
FFF4
FFF5
OCI (Timer 1 output compare 1, 2)
FFF2
FFF3
TOI (Timer 1 overflow)
FFEC
FFED
CMI (Timer 2 counter match)
FFEA
FFEB
IRQ2
FFFO
FFF1
SIO (RDRF + ORFE + TORE)
Interrupt
Test
E
SP-1
Internal
Read
Internal
Write
\~
SP-2
SP-3 SP-4
Vector
MSB
Address
SP-6
______________________________--JI
__________........1
\
Figure 3-10. Interrupt Sequence
~HITACHI
416
sp-5
Vector
LSB
Addrss
New
PC
Address
Each Status Register's Interrupt
Enable Flag
1 ; Enable, 0; Disable
IRQ,
IRQ,
ICF
Condition
Code
Register
I-MASK
---..-.
ICI
o ;Enable
1 ;Disable
OCF1
~o-
OCF2
---0-
TOF
IRQ 3
CMF
RDRF
---.
----
TOI
...0--0
~
CMI
---0ORFE
TORE
~
-cr--
Interrupt
Request
Signal
~
.--
Edge
Detective
Circuit
)
Sleep
Cancel
Signal
I
j;ddreSS Error
TRAP
Op Code Error
Detective Circuit
SWI
Figure 3-11, Interrupt Circuit Block Diagram
The SEI instruction sets the interrupt mask bit, inhibiting interrupts. The CLI instruction clears the
interrupt mask bit, allowing interrupts. The TAP instruction can set and clear the interrupt mask bit also.
There must be at least two cycles between clearing the interrupt mask bit and setting it again, or an
interrupt which occurs between setting and clearing the bit cannot be accepted (figure 3-12).
CLI
SEI
CLI
NOP
SEI
CLi
NOP
NOP
SEI
No
No
Yes
Figure 3-12. CLI and SEI Timing
~HITACHI
417
Section 4. Timer 1
The 16-bit programmable timer, timer 1, can measure an input waveform and independently generate
two independent waveforms. The pulse widths of the input and output waveforms can vary from
microseconds to seconds.
Timer 1 has the following components (figure 4-1).
ControVstatus register 1 (8 bits)
•
ControVstatus register 2 (7 bits)
•
Output compare register 1 (16 bits)
•
Output compare register 2 (16 bits)
Free-running counter (16 bits)
Input capture register (16 bits)
~
Internal Data Bus
::[ } : $OB. $OC
::[J:$19.$lA
Output Compare
Register 2
I
I
Output Compare
Register 1
I I
I
~
";1'
J1
Output Compare 2
~J:$09.$OA
Free Running
16 Bit Counter
II$OD. $OE
Input Capture
Register
I
D
I
~
~
I
Overflow Detect
Output Compare 1
I
-
transmit shift register
with TDRE = 1, TDRE is cleared.
(asynchronous)
2. Transmit shift register is empty.
(clock·synchronous)
3. RES = 0)
If transmit data is written to TDR, and then TE bit is cleared with TDRE = 0 to stop
I
transmitting, TDRE remains "0".
In this case, even if TE bit is set and transmit data is written again, the TDR data is not
transmitted.
Please note that TE bit must be cleared after the last data has been transmitted.
(This caution is not applied to asynchronous serial communication interface.)-
~HITACHI
439
~HITACHI
440
Section 7. HD63701 XO Programmable ROM (EPROM)
The HD63701XO's on-chip EPROM is programmed in the chip's PROM mode. When MPO, MP1,
and STBY are low (table 2-2), the HD63701XO doesn't operate as an MCU. It can be programmed
by the same procedure as a standard 2732A EPROM. In the PROM mode, P30-P37 are the data
bus, P10-P17 and P40-P43 are the address bus, and P57 is the CE input. See figures 7-1 and 7-2,
table 7-1.
Port 3
a Data Bus
I
Port 1
a Address aus
Port 4
4 Address Bus
Figure 7-1. PROM Mode
Table 7-1. Pin Conditions in PROM Mode
Pin Name
Pin No.
Programming
Verification
PROM Inhibit
VCC
33
+5V
+5V
+5V
GND
GND
GND
VSS
Vpp/OE
42
Vpp
Low
Don't care
CE
24
Low
Low
High
P30-P37
51-58
Data input
Data output
High impedance
P10-P17
P40-P43
43-50
38-41
Address input
Address input
Don't care
MPO, MP1,
STBY
4,5,7
Low
Low
Low
GND
GND
GND
Other pins
~HITACHI
441
Vss
G
EOo
E01
E02
E03
E04
E05
EOs
E07
15
50
EAo
1SHD63701 XOC49
EA1
(DC-64S)
EA2
EA3
EA4
EA5
EAs
EA7
Vpp/OE
EAs
EA9
EAlO
EA"
31
"""1i...32_____......:~VCC
G: Ground (V 55 level)
Figure 7-2. PROM Mode Pin Arrangement
~HITACHI
442
Table 7-2 shows the recommended combinations of PROM programmers and socket adapters for
programming the HD63701 XO. The socket adapter converts the pin assignment of the necessary 24
pins to the same assignment as the standard EPROM.
Table 7-2. PROM Programmers and Socket Adapters
Programmer
Data 1/0
Socket Adapter
121N121.B,22A1228,
DataVO
HD63701XO (for 29A1298)
29A1298
Hitachi
H67PWA01A
7.1 Programming and Verification
When the CE pin is held low after the programming voltage (Vpp) is applied, data can be programmed in
PROM one byte at a time through port 3. To verify the data, hold the Vpp/OE and CE pins low after
programming, and the programmed data will be output from port 3.
When CE is returned high, port 3 will be high impedance, and PROM programming/verification will be
inhibited.
Programming precautions: The PROM memory cells should be programmed under specific voltage and
timing conditions. The higher the program voltage and the longer the program pulse is applied, the
more electrons will be injected into the floating gate. However, if an overvoltage is applied to Vpp, the
p-n junction may be permanently damaged. Pay particular attention to PROM programmer overshot.
Negative voltage noise will cause a parasitic transistor effect, which may reduce breakdown voltage.
The HD63701 XO is connected electrically to the PROM programmer through a socket adapter.
Therefore, pay attention to the following:
1.
Confirm that the socket adapter is firmly fixed on the PROM programmer.
2.
Do not touch the socket adapter or the LSI during programming. Mis-programming can be caused
by poor contacts.
~HITACHI
443
7.2 Erasing (Window Package)
The EPROM is erased by exposing the LSI to ultraviolet light. All erased bits are in 1's.
The conditions for erasing are: ultraviolet light with wavelength of 2537 A, and a minimum irradiation of
15 W . sfcm 2 . These conditions are satisfied by exposing the LSI to an ultraviolet light rated at 12,000
IlW/cm2 for 15-20 minutes, at a distance of 1 inch.
7.3 Characteristics and Applications
7.3.1 Principles of Programming/Erasing
The HD63701 XO's memory cells are the same as an EPROM's. Therefore they are programmed by
applying high voltage to control gates and drains, which injects hot electrons into the floating gate
(figure 7-3) .The condensed electrons in the floating gate are stable, surrounded by an energy barrier of
Si02 film. Such a cell becomes a 0 bit due to the memory threshold voltage change. A cell with no
condensed electrons at its floating gate appears as a 1 bit.
• . / Control gate
---r
Si02~~1_____
...J./ Floating gate
§E5i988ff
Orain
Source \
~
/
( ,
J . [,' \
The erased cell (1)
The programmed cell (0)
Figure 7-3. Cross-Section of EPROM Memory Cell
The electron charge in memory cells may decrease as time goes by. This can be caused by:
1.
Ultraviolet light, discharged by photo-emitting electrons (erasure principle)
2.
Heat, discharged by thermal emitting electrons
3.
High voltage, discharged by a high electric field at the control gate or drain
If the oxide film covering a floating gate is defective, the erasure rate is great. Normally, electron erasure
does not occur, because such defective devices are found and removed during testing.
~HITACHI
444
7.3.2 Window-Type Package Precautions
Glass Erasure Window: If the glass window comes in contact with plastic or anything with a static
charge, the LSI may malfunction due to the electrostatic charge on the surface of the window. If this
occurs, exposing the LSI to ultraviolet light for a few minutes neutralizes the charge, and restores the
LSI to normal operation. However, charge stored in the floating gate decreases at the same time, so
reprogramming is recommended.
Electrostatic charge buildup on the window is a fundamental cause of malfunctions. Measures for its
prevention are the same as those for preventing electrostatic breakdown:
1.
Operators should be grounded when handling equipment.
2.
Do not rub the glass window with plastics.
3.
Be careful of coolant sprays, which may contain a few ions.
4.
The ultraviolet shading label (which includes conductive material) effectively neutralizes charge.
I
~HITACHI
445
Ultraviolet Shading Label: If the LSI is exposed to fluorescent light or sunlight, its memory
contents may be erased by the small quantity of ultraviolet light in these sources. In strong light, the
MCU may fail under the influence of photocurrent. To prevent these problems, it is recommended that
the device be used with an ultraviolet shading label covering the erasure window after programming.
Special labels are sold for this purpose. They contain metal to absorb ultraviolet light. When choosing a
label, note the following:
1.
Adhesion (mechanical intensity)-Re-use and dust reduce adhesion. Peeling off a label may cause
slatic electricity. Therefore, erasing and rewriting is recommended after peeling. Sticking a new
label over the old one is better than replacing a label.
2.
Allowable temperature range-The allowable environmental temperature range of the label should
be noted. If it is used under conditions outside this range, the paste may stiffen or adhere to the
label, causing paste to remain on the window when the label is removed.
3.
Moisture resistance-The allowable moisture range and environmental conditions of the label
should be noted. It is difficult to find a shade label applicable to all conditions. The proper label
should be selected depending on the intended use of the MCU.
~HITACHI
446
Section 8. Applications
8.1 HD6301XO or HD63701XO in Expanded Mode
Figure 8-1 shows a microcomputer system using all CMOS peripheral LSI's as an application
example of the HD6301XO or HD63701XO in the expanded mode (modes 1,2).
Ports 1 and 4 are used for address output, and port 3 is used for data 1/0. The system is controlled by
directly connecting RD and WR as memory control signals and RIW and E as peripheral controls.
Address decoder
A 03
-----v;;
Y
r-"'-- A
~B
L
'
~cy,-
~OSPIA
CS,
Y37'4HC13S
HD6321
MCU
CMOS ACIA
~}IIO
L . CS,
HD6350
E
R/W
~
Ao
r?-
r-
E
i-
R/W
r-r-
Do-D,
Ao
....:..". RS
o
iA RS
RS,
~
E
RIW I--
Do-D7
ii-
h
.
Serial
interface
I
r-
16
Address bus
Ao-A'5
S
0 0 -0 7
Data bus
RD
WR
,
CE
CS,
A,s
r-
OE
CS
OE
OE
WE
13
4-
13
~
4- Ao-A'2
Ao-A'2
-+-
S
--+- 1/0,-1/0,
HM6264
Sk byte of S-RAM
Ao-A'4
S
0 0 -0 7
'-----+- Do-D,
HN27C64
Sk byte of EPROM
HN613256
32k byte of Mask ROM
Figure 8-1. All CMOS Microcomputer System
~HITACHI
447
8.2 HD6301XO or HD63701XO in Single-Chip Mode
Figure 8-2 shows a printer controller using the HD6301XO or HD63701XO in the single-chip mode
(mode 3).
The HD6301XO or HD63701XO controls a 16-dot printer using 1/0 lines as its ports. Data from the host is
transferred to the MCU through the serial interface or through a Centronics interface at port 3.
,
Centronics
interface
Latch
I
Port 1
8
Port 4
8
Port 3
V
STRDB
~
~!
Head driver
t
Tout1
(Timer)
MCU
Host
computer
system
2
Serial interface
Rx
Port 7
I
Tx
I
Tout2
(Timer)
Panel
switch
display
CR Motor driver
LF Motor driver
II.
2
Port 6
Port 5
v
Position detector
..
Figure 8-2. Printer Controller
8.3 Timer Applications
8.3.1 Timer 1
Timer 1 is a 16-bit programmable timer with the same architecture as the timer on the HD6301V1, but
with an output compare register added. Timer 1 can perform the following four operations:
1.
Waveform generation or interval timing using output compare register 1 (OCR1)
2.
Waveform generation or interval timing using output compare register 2 (OCR2)
3.
Pulse width or pulse cycle measurement using the input capture register
4.
Interval timing with overflow interrupt
~HITACHI
448
Wavefonn Generation. The values of the output compare registers (OCR1, OCR2) are compared
with the free-running counter (FRC) at every E cycle. When a match occurs, an output compare flag
(OCF1, OCF2) is set. When an output enable bit (OE1 E, OE2E) is set, the value of the output level bit
(OLVL1, OLVL2) is output at port 2 (Tout1: P21, Tout2: P25). Figure 9-3 is a flowchart for OCR1
waveform generation.
Set P2 , to timer output pin
----------Set timer output. 1 toOLVLl
'-----'---',-_---J ----------Set O-interval-time B to OCRI
'--_--,,-_---J ---------Clear OCFl and add l-interval-time A to OCRI
I
'--_--,;-_---' - - - - - - - - - Clear OCFl and add O-Interval-time B to OCRI
Output Waveform (P2,).
" Start
i
..
/
B
I
I
-/- A -/-
B
I
+.
L~
A-j
Figure 8-3. OCR1 Waveform Generation
Pulse Width Measurement. The input capture register (lCR) latches the free-running counter value
at the transition of the external input signal, measuring the pulse width or cycle. Figure 8-4 is a
flowchart of pulse width measurement.
~HITACHI
449
'-----r---..J
'-----r---..J
- - - - - - - - - Detect input rising edge
- - - - - - - - - Store the ICR to M,_and clear ICF
- - - - - - - - Detect Input falling edge
- - - - - - - - - Store the ICR to M, and clear ICF
' - -_ _' - -_ _..J
--- -
-
-
-
-
Pulse width A= (M,J- (M,)
-
In_p_ut_w_a_v_ef_or_m~f
__
1~_______
~A--1
Figure 8-4. ICR Pulse Width Measurement
8.3.2 Timer 2
The 8-bit reloadable timer provides such functions as an external event counter, interval timer, waveform
generator, and SCI baud rate generator.
External Event Counter_ Operate timer 2 as an external event counter by setting input clock select,
CKSO and CKS1 , to external clock and writing 1 into T2E. The timer 2 upcounter is incremented by the
external clock's rising edge. Figure 9-5 shows the routine that generates an interrupt after N extemal
events occur (where N is an integer between 1 and 256).
~HITACHI
450
Interrupt routine
- - - - Write 0 into CMF.
External clock input
Interrupt enable
- - - - . Set TCONR
- - - - Timer 2 enable
Input signal
T2CNT
CMF--------------------~H~--------~
L-
Generates CMI
• Sets N-1 in the TCONR when the external event counter
value which generates the interrupt is N.
Figure 8-5. External Event Counter
Square-Wave Generator. Timer 2 can generate a continuous square wave without software
supervision. Figure 8-6 shows this routine.
----- Select input clock
' -_ _- ,_ _ _--' ----- Set toggle output
'-----r--~
'-------~
----- • Set TCONR
• Set N-1 in the TCONR, when the half cycle
of square waveform is N.
- - --- Timer 2 enable
Figure 8-6. Square-Wave Generator
~HITACHI
451
8.4 SCI Applications
8.4.1 Timer 2 Baud Rate Generator
The SCI can use six kinds of clock source: timer 1's FRC (four kinds), timer 2, and an external clock. The
timer 1 baud rate clocks are not adjustable, but timer 2 can provide any baud rate. Figure 8-7
shows how time 2 can provide the baud rate.
CKSI and CKS2 select E or E/a according to the baud rate.
Value of n to TCONR is
f
f: input clock frequency
n
32 x baud rate
n: 0 to 255
Set CKSI,CKSO
TCONR=N
T2E=1
SS2=1
Set CC2, CCI,
CCO
_______ Select timer 2 as a clock source.
Select transfer format.
_______ To initialize the SCI, set TE and RE after more than
I bit cycle at the required baud rate.
Figure 8-7. Timer 2 as Baud Rate Generator
8.4.2 Interface between HD6301 XO/HD63701 XO and HD6305XO
An HD6301XO/HD63701XO can interface to an HD6305XO in the clock synchronous mode. This gives
99 110 lines, suitable for systems requiring many 110 lines. Figure 9-8 shows an example of this interface.
Rx
Tx
Rx
Tx
SCLK
CK
P60
P6,
l"
'-'
C,
C,
Hand Shake Line
HD630IXO/
HD6370lXO
HD6305XO
Figure 8-8. HD6301XO/HD63701XO to HD6305XO Interface
Employing the clock synchronous mode enables the HD6301 XO/HD63701 XO to interface easily to
peripheral devices (AID converter, real-time clock, etc) whic:h use a clock synchronous interface, as well
as to the HD6305XO.
~HITACHI
452
8.4.3 110 Expansion
The SCI can be used in the clock synchronous mode to supplement the available parallel 110 ports. Use
an external shift register to perform the serial-to-parallel conversion. Figure 8-9 shows this kind of
I/O expansion.
.
Output Data
'MSB
LSB'
Vee
PORT
GND
MCU
P2,
74LS164
CK
B
P2,
Output Ports
I
Input Data
MSB'
'LSB
MCU
PORT
P2 3
74LS165
QH
CLKINH
CK
GND
P2,
Input Ports
Figure 8.9 I/O Expansion in Clock Synchronous Mode
8.4.4 SCI Multiplexer
Use an analog multiplexer as shown in figure 8-10 to use the SCI with both an asynchronous and a
clock synchronous device, such as an HD6305XO and an RS-232C.
~HITACHI
453
HD14503
Analog MPXer
ClK
HD6305XO
Rx
etc.
X
P2,
Zo
Y
P2,
X,
Y,
Z
P2 4
Xo
Yo
Tx
Rx
MCU
Tx
Z,
Inhi.r1
ABC
I 11
~
RS-232C
etc.
PORT PIN
J
Figure 8-10. Multiplexed SCI
8.5 Lowering Operating Current
8.5.1 Lowering Operating Frequency
The HD6301 XO/HD6303X1HD63701 XO operating current is approximately proportional to the operating
frequency (figure 8-11). Therefore, if the system does not require a high-speed MCU, power can be
reduced by lowering the operating frequency.
14
C(
.s
"
-Y
c:
10.5
0
li
E
::.
7
CI)
c:
0
"
1:
~
::.
()
0.7
0.1
1.0
1.5
2.0
Operating Frequency (MHz)
Figure 8-11. Operating Frequency and Current (Typical)
~HITACHI
454
8.5.2 Sleep Mode
The SLP instruction puts the MCU into the sleep roode. In the sleep mode, current consumption is
reduced to one-fourth to one-fifth of that in the operating state.When the CPU acknowledges an
interrupt request, it cancels the sleep mode. The average power consumption can be reduced by
putting the CPU in sleep mode whenever it doesn't actually execute any instructions, such as in
interrupt wait state or polling. Figure 8-12 shows a routine which wakes the CPU up every 65 ms,
using the overflow interrupt of the timer 1 FRC.
_______ Set the Timer 1 as the 65-ms interval
timer using FRC overflow interrupt.
L -_ _- , -_ _...J- - - - - --
Interrupt wait state.
When the main routine processing time is 1 ms.
average operating current Icc is 1.58mA (1= 1MHz).
I
I - 1.5x65+7xl
cc 66
= 1 .58 [mAl (1= 1 MHz)
Figure 8-12. Low Power Consumption Using the Sleep Mode
8.5.3 Standby Mode
Bringing STBY (pin 7) low puts the MCU·into standby mode. In standby mode, the oscillator stops and
the MCU goes into the reset state. The contents of RAM are maintained as long as VCC is greater than
or equal to 2 V. In standby mode, current consumption is reduced to a few 1lA. RAM can be maintained
by battery.
Bringing STBY high cancels standby mode. The MCU releases the reset state and starts oscillation.
RES (pin 6) should be held low for at least the oscillation stabilization time (tRC) after S"i'BY high. Figure
8-13 gives an example of a circuit that sets standby from software. Figure 8-14 shows the timing for
this circuit, and figure 8-15 is an operating flowchart.
~HITACHI
455
MCU
.---------~~~~ST8'V
Rr
.-+---tRES
cr~
Standby mode cancel
L------~--~PORT
Rr· Cr
(External input)
>
20ms
Figure 8-13. Standby Circuit Example
PORT
Standby mode
cancel
(External input)
----·r~--------~rrl-----------------
------------1,,)--------.U
r----
SrBY
fS
I
I
I
I
L---------ff~
.......
Oscillation stability
• PORT goes to the high-impedance state with STBY low, so it is pulled high by the pull-up resistor.
Figure 8-14. Standby Timing
Standby mode
(20ms)
Figure 8-15. Standby Circuit Flowchart
~HITACHI
456
8.6 Memory Ready Application
The memory ready function allows the MCU to access low-speed memories or low-speed devices.
Figure 8-16 shows a circuit example, and figure 8-17 is its timing chart.
L
4~(4MHz)
*
AD
MP ,
CE
MP o
V
~
.A
Data Bus
0 0 -0'1\
/
"
A
EXTAL
Ao-A14
-'\
Address Bus
~
-V
LA"
Ao-A"
CS
4-Bit binary
counter HD74LS161
MCU
~~'~CKJ
A15
0 0 -0,
Low-speed
mask ROM
HN61256
Clear
..J..
MR
--yo
E
®
....
.....
I
The HN61256 is located
In $4000 to $BFFF.
Figure 8-16. Low-Speed Memory Access Circuit
E
ADB
CS
J(I......_----JX'__ _
~
C~---JX'---C
x==:
r
®--------rl-~
MR
I
If
·
I
~-------
I
Data
Figure 8-17. Memory Ready Bus Timing
~HITACi-il
457
8.7 Halt Application
The halt function enables the MCU in the expanded mode to interface with a DMAC (HD6844) and
execute DMA (figure 8-18).
1
---.
r---
Ao-A"
~
r
A
0 0 -0,
H
r---v
...
E
MCU
r-
..
.
r
...
I"
~
Ao-A"
0 0 -0,
I---
R/W
I---
IRQ
I--
r-
Memory Unit
RES
BA
HALT
U)
::>
to
U)
::>
U)
U)
DGRNT
DRQH
.....
A
Ao-A"
l
I"
0 0 -0,
RES
0
H
f---
ci>2DMA
a
RiW
CSlTxAKB
i'l
TxSTB
TxRQ o
H
1/0 Device Controller
~
"0
"0
«
r---v
...
HD6844
to
~
I---
L
.....
..
I"
0 0 -0,
E
R/W
' - - - IRQ
I---
RES
I--I---
TxRQ
TxAK
~~~~ es
Figure 8-18. One-Channel DMAC Interface Example
~HITACHI
458
8.8 RD, WR Application
RD and WR, as well as E and RlW, can act as external interface signals. RD and WR allow the MCU to
easily interface with the 80xx family peripherals as well as with the 6800 series. Figure 8-19 shows
an example of an interface between the MCU and an 8255.
8255
RDr-------------------~
RD
WRr--------------------i WR
MCU
0 0 -0,
Aor--------------------i Ao
A,r-------------------~
A,-A15 r-______---.
A,
~
I
Address Decoder
RES
RES -----~------------_f :>o----------~
Figure 8-19. HD6301XO/HD63701XO and 8255 Interface
~HITACHI
459
8.9 LCD-II Interface Application
Figure 8-20 and 8-21 show examples of interfaces between an HD6301XO/HD63701XO and a liquid
crystal driver (LCD-II). The interface lines are TTL compatible. The HD6301XO/HD63701XO in the
expanded mode in figure 8-20 interfaces with the LCD-II directly through the external bus lines. Port 3
connects to the LCD-II data bus,
RJW connects to RIW, AO connects to RS, and the rest of the address
bus is decoded and ANDed with E to connect with E on the LCD-II.
The HD6301XO/HD63701XO in the single-chip mode in figure 8-21 interfaces with the LCD-II
through the I/O port. The read/write operation should be performed with care for the timing of the
LCD-II E signal and others.
E
A,s-A,
E
COM,-COM,.
MCl)
Ao
R/W
RS
LCD-II (HD44780)
R/W
Connecting
to the liquid
crystal display
SEG,-SEG. o
Port 3
DBo-DB,
Figure 8-20. LCD-II Interface, Expanded Mode
P3.
E
P3 s
RS
COM,-COM,.
LCD-II (HD44780)
MCU
P3.
Port 1
R/W
DBo-DB,
SEG,-SEG. o
Figure 8-21. LCD-II Interface, Single-Chip Mode
~HITACHI
460
Connecting
to the liquid
crystal display
8.10 Oscillation Circuit Board Design
Keep the following rules in mind whefl designing the circuit to connect the crystal resonator with the
XTAL and EXTAL pins (figures 8-22, 8-23).
1.
The crystal and load capacitors should be as close to the LSI as possible. External noise at the
XTAL and EXTAL pins will disturb normal oscillation.
2.
Keep the lines from XTAL and E as far apart as possible. Avoid parallel wiring. Interference from E
to XTAL will disturb normal oscillation.
3.
Do not allow Signal or power lines to cross or run closely parallel to the oscillator lines (signals A, S, C
in figure 8-22). They will disturb normal oscillation. Keep the resistance between XTAL and EXTAL
pins and the next nearest pins greater than 10 MQ.
Avoid these lines
/~
I
Signal C
The figures in this characteristics represent those when teyc is minimum (=10
the highest speed operation).
~HITACHI
464
Peripheral Port Timing
HD63A01XO
HD6301XO
Item
Symbol
Min
Typ
Max
Typ
Min
HD63B01XO
Typ
Min
Max
Max
Unit
Peripheral data
set-up time
(Ports 2, 3
5,6)
tpDSU
200
200
200
ns
Peripheral data
hold time
(Ports 2, 3
5,6)
tpDH
200
200
200
ns
(Ports I, 2, 3
4,6, 7)
tpWD
Delay time (From
enable fall edge to
peripheral output)
300
300
ns
300
~:~~itlon
Fig. 1·5
Fig." 1·6
Timer, SCI Timing
HD630lXO
Item
Symb
01
Min
Timer 1 input pulse width
tPWT
2.0
Delay time (enable positive
transition to timer output)
SCI input
clock cycle
(Async. mode)
tScyc
SCI transmit data delay
time (Clock sync. mode)
tTXD
SCI receive data set-up
time (Clock sync. mode)
Max
Min
Typ
HD63B01XO
Max
2.0
Min
Typ
Max
2.0
Unit
tcyc
400
400
400
tTOD
(Clock syno)
Typ
HD63A01XO
ns
1.0
1.0
teyc
Fig. 1·9
2.0
teyc
Fig. 1·4
ns
Fig. 1·4
200
200
200
290
290
ns
tHRX
100
100
100
ns
SCI input clock pulse width
tpWSCK
0.4
Timer 2 input clock cycle
ttcyc
2.0
2.0
2.0
Timer 2 input clock pulse width
tPWTCK
200
200
200
fall time
Figs. 1·7,
1·8
2.0
290
Timer 1 • 2, SCI input clock
Fig. 1·9
1.0
tSRX
rise time
Condition
2.0
SCI receive data hold time
(Clock sync. mode)
Timer 1 • 2, SC I input clock
Test
0.6
0.4
0.6
0.4
0.6
I
tScyc Fig. 1·9
tcyc
ns
tCKr
100
100
100
ns
tCKf
100
100
100
ns
~HITACHI
465
tcyc
~
E
V
2.4V
PW;L
\
OBV
1\ .
\
vi
}
\
PW;H
~
tAH __
!--tAD_
)<
tEo
tE'
K
2.4V
~O.BV
I--tRWO
PWRw
'\
V
2.4V
O.BV
~tDDW_
I--tHW -
2.4V
MCU IMite
00-0,
~
O.BV
4-tDSR_
I----
tHR
2.0V
MCU Read
00-07
O.BV
'"
O.BV
Figure 1-1. Mode 1, Mode 2 Bus Timing
~HITACHI
E
I---- tHLR
!--tDLR __
466
tHRW
,V
1 - - - - - - PW'MR --------<»1
24V
\
\
\
~+-+
__
\L
O.BV
___ _
tHMR
tSMR
MR
Figure 1-2. Memory Ready and E Clock Timing
Last Instruction
Instruction Execution
Cycle
HALT Cycle
lBA
SA
O.BV
Figure 1-3. HALT and SA Timing
2.0VI2.4V)·
Synchronous Clock
i<>----t-+-tscyc
2.4V
Transmit Data
O.BV
Receive Data
-<~____ ~~t~~~X__tH_"1-<~___
-2.0V is high level when clock input.
2.4V is high level when clock output.
Figure 1-4. SCI Clocked Synchronous Timing
<@)HOTACHD
467
rMCUWrite
E
P1o-Ph, P2o-P2, ------,..6:-:;~;--
P30-P3" P4o-P4,
P6o-P6" P7o-P74 _ _ _ _ _J
1"----
P30-P3,
(Inputs)
(Outputs)
Figure 1-5. Port Data Set-up and Hold
Times (MCU Read)
Figure 1-6. Port Data Delay Times
(MCU Write)
E~
Output
Timer 1
FAC
~
_ _ _..JXy~';'.!h"':
tTO,D
X...___
T2CNT
r-=
P2" P2s------!.-;..,V-k2...."'4V".--Outputs _ _ _ _ _ _ _..J,l'l'L:;.:.·""SV'--_ _
P2 6
Output
Figure 1-7. Timer 1 Output Timing
:~
•*
teK'
; tScye
••
AL =2.2kQ
Test Point
1S207<\®
C
R
or equiv.
{
C=90pF for Port 1, Port3, Port 4, E
"Timer 1; tPWT
=30pF for Port 2, Port 6, Port 7
TImer 2; tPWTCK
SCI
; tPWSCK
Figure 1-9. Timer 1'2, SCI Input Clock
Timing
A=12kQ for Port 1-Port4, Port 6, Port 7, E
Figure 1-10. Bus Timing Test Loads
(TTL Load)
~HITACHI
468
m
Vee
1 ?-
'Timer 2; ttcyc
SCI
Figure 1-8. Timer 2 Output Timing
Internal Bus
Address
:=)(j:JC=X:=)(=:JC=X=J==X::=X=)(==)C=:X:=~;:::J<;;:=X:=)(:
SP
SP- 1 SP-2
SP-3
SP-4
SP-5 SP-6 ~sll'r ~'i:0r ~~w
AddressAddressAddress
Internal
OamBus----~--~--~'---~--~--~'---~--~~~~--~--~--~'---~--~--~~--A. Op OperandlrrelsvsntPCQ- PCB- IXO- IXB - ACCA ACeS CCR Vector Vector First Inst. of
CodeOp CodeO.t.
Internal
PC7
PC1S
IX7
IX1S
MSB
LSB
Interrupt Routine
\~-------------------------------'-----------------
Read
Internal
\Mite
\'--------
------'/
Figure 1-11. Interrupt Sequence
_ _ s.sv
VcC~'6V tRC-----<~
-------ff-------1f-+-------------------i
VcJ-o.sv
Sffi
Vcc-O.5V
m
~S-S-------11------'
I
:~:r.ss _"-=~:::X::=x;;;f..::x:::x;::::x.~~
FFFF FFFF FFFF FFFF FFFF FFFE FFFF New PC
FFFF
FFFF FFFF
II
I
R/W._""
...
\~_
I!ll • •
WR • •_ _
Data
Bus
~"
~~
~~~---,-------------~~~.
pe1S
PC7
Instruction
Figure 1-12. Reset Timing
~HITACHI
469
1.2 HD6303X, HD63A03X, HD63B03X Electrical Characteristics
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Supply voltage
Vee
-0.3 to +7.0
V
Input voltage
Vin
-0.3·to Vee+0.3
V
Operating temperature
Topr
o to
+70
"C
Storage temperature
Tstg
-55 to +150
'C
Note:
This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection circuits. To assure the
normal operation, we recommend VI~' VOU\: Vss;:;;' (V In or Vout) ~Vcc'
Electrical Characteristics
DC Characteristics
(Vee=5.0 V
±
10%, 1=0.1 to 2.0 MHz, Vss=O V, Ta=O to + 70"C, unless otherwise noted.)
Item
Input high voltage
RES, STBY
Symbol
Min
VIH
Vee-O.S
Vee+0.3
Unit
V
VeeXO.7
2.0
Vee+0.3
V
Vee+0.3
0.8
V
EXTAL
Other inputs
Typ
Max
Test Condition
Input low voltage
All other inputs
VIL
Input leakage current
RES, PortS
Il;nl
1.0
p.A
Vin=O.S to Vee-O.S V
Ilrsti
1.0
p.A
Vin=O.S to Vee-O.S V
2.4
V
IOH--200p.A
Vee-0.7
V
IOH=-10p.A
-0.3
V
NMI, STBY, MPo, MP!
Three state
leakage current
Ao-A15,Do-D7,RD
WR,R/W',Ports 2,6
Output high voltage
VOH
Output low voltage
VOL
0.4
V
IOL=1.6 mA
10.0
mA
Vout=I.S V
12.S
pF
Vin=OV, 1=1 MHz
Ta=2S'C
Darlington drive
current
Ports 2, 6
-IOH
Input capacitance
All other inputs
Cin
Standby current
Not operating
ISTB
3.0
15.0
p.A
ISLP
1.5
3.0
mA
Sleeping
(1-1 MHz2)
2.3
4.5
mA
Sleeping
(1=1.5 MHz2)
3.0
6.0
mA
Sleeping
(1-2 MHz2)
7.0
10.0
mA
Operating (1=1 MHz2)
10.5
15.0
mA
Operating (1=1.5 MHz2)
14.0
20.0
mA
Operating (1-2 MHz2)
Current dissipation!
1.0
lee
RAM standby voltage
VRAM
2.0
V
Notes:
I. VIII min=Vcc-l.OV, VEL max=O.8V (AU output terminals are at no load.)
2. Current dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max. values about
current dissipations at x MHz operation are decided according to the following formula:
(f=x MHz)
=typ. value (f=1 MHz) Xx
tyPo value
(f=x MHz)
max. value
=max. value (f=1 MHz) Xx
(both the sleeping and operating)
~HITACHI
470
AC Characteristics
(Vcc=5.0
v ±10 %,1=0.1
to 2.0
MHz,
Vss=O
v, Ta=O to +70
'C,
unless otherwise noted.)
Bus Timing
HD6303X
Item
Symbol
Cycle time
Min
Typ
HD63A03X
Typ
HD63B03X
Max
Unll
10
~s
25
25
ns
25
25
ns
Max
Min
Max
Min
10
0.5
Typ
tcyc
10
0.666
Enable rise time
lEt
25
Enable fall time
IEf
25
Enable pulse width high level l
PWEH
450
300
220
ns
Enable pulse width low level l
PWEL
450
300
220
ns
lAD
250
190
160
ns
Data delay time
(Write)
loow
200
160
120
ns
Data set· up time
(Read)
toSR
70
70
70
ns
Address, R/W delay
time l
tAH
80
50
35
ns
(Wrile)I
tHW
80
50
40
ns
(Read)
IHR
Address, R/W hold lime l
Data hold time
RD.
WR pulse widlh l
PWRW
0
0
450
300
Fig. 1·13
ns
220
ns
RD,
WR delay time
tRWo
40
40
40
ns
RD,
WR hold time
tHRW
30
30
25
ns
120
ns
160
200
Test
Condilion
LlR delay lime
tOLR
LlR hold lime
tHLR
10
10
10
ns
MR set-up timel
tSMR
400
280
230
ns
MR hold lime l
tHMR
90
40
0
ns
E clock pulse width al MR
PWEMR
9
9
9
~s
Processor control set-up time
tpcs
Processor control rise time
tPCr
100
100
100
ns
Processor control fall time
tpCf
100
100
100
ns
SA delay time
teA
250
190
160
ns
Fig.I·15
Oscillator stabilization time
tRC
ms
Fig. 1·24
Reset pulse width
PWRST
200
20
200
ns
200
20
3
20
I
Fig. 1·14
Fig~ 1-15,.
1·23,1·24
Fig~
1·14,
1·15
tcyc
Note: 1. These timings change in approximate proportion to tcyc. The figures in this characteristics represent those when tcyc is minimum (;;::;in
the highest speed operation).
~HITACHI
471
Peripheral Port Timing
Item
Peripheral data
set-up time
(Ports 2, 5,
Peripheral data
hold time
(Ports 2, 5
Min
Max
Symbol
Min
tpDSU
200
200
tpDH
200
200
6)
6)
Typ
flD63B03X
HD63A03X
HD6303X
Max
Typ
Unit
~:~!ition
200
ns
Fi9. 1-17
200
ns
Min
Max
Typ
Delay time (From
(Ports 2, 6)
enable fall edge to
300
tPWD
300
300
ns
Fig. 1·18
peripheral output)
Timer, SCI Timing
HD6303X
5ymb
Item
01
Timer 1 input pulse width
tPWT
Delay time (enable positive
transition to timer output)
tTOD
SCI input
clock cycle
(Async mode)
tScyc
(Clock sync.)
SCI transmit data delay
time (Clock sync. mode)
SCI receive data set-up
Min
Typ
HD63A03X
Max
2.0
Min
Typ
HD63B03X
Max
2.0
400
Min
Typ
Max
2.0
400
Unit
tcyc
400
ns
Condition
Fig. 1·21
Figs. 1·19,
1·20
1.0
1.0
1.0
tcyc
Fig. 1·21
2.0
2.0
2.0
tcyc
Fig. 1·16
ns
Fig. 1·16
200
tTXD
time (Clock sync. mode)
tSRX
290
SCI receive data hold time
(Clock sync. mode)
tHRX
100
SCI input clock pulse width
tPWSCK
0.4
200
290
290
100
0.6
0.4
200
ns
100
0.6
0.4
ns
0.6
tS cyc Fig. 1·21
Timer 2 input clock cycle
ttcyc
2.0
2.0
2.0
tcyc
Timer 2 input clock pulse width
tPWTCK
200
200
200
ns
Timer 1 • 2, SCI input clock
rise time
tCKr
100
100
100
ns
Timer 1 • 2, SCI input clock
fall time
tCKf
100
100
100
ns
~HITACHI
472
Test
tCYC
~
E
V
2.4V
\
PV\h
O.8V
\
~V
V
<>-tAD-<=-
Ao-Al!'>
R!W
)<
\
\
PWeH
1\
tE,
tEl
tAH-<>
-K
2.4V
O.8V
f<>---'>
tRwn
P\NRw
'\
f<>- tDDW
tHAW
V
2.4V
O.8V
--<=0
.J
MCU Write
00-07
"\
f<'-tHW ""'"
r
2.4V
O.8V
fco- t os R-<=>
~ tHR
f£2.0V
MGU Read
00-07
1\
~~O.8V
~
-<>-tDLR-Qoo
'"
[!'
O.8V
tHLR
V
Figure 1-13. Bus Timing
~HITACHU
473
"'~
~/
______
J~~~·2-'4-V-----\-\-~-~::----------~ ~O_._8V
____
__+-+_IHMR
tSMR
MR
Figure 1-14. Memory Ready and E Clock Timing
Last Instruction
Instruction Execution
Cycle
HALT Cycle
IBA
2.4V
8A
O.8V
Figure 1-15. HALT and BA Timing
Synchronous Clock
Transmit Data
Receive Data
·2.0V is high level when clock input.
2.4V is high level when clock output.
Figure 1-16. SCI Clocked Synchronous Timing
~HITACHI
474
r-
MCU Write
P20-P2,
P60-P6,
P30-P3,
(Inputs)
(Outputs)
Figure 1-17. Port Data Set-up and
Hold Times (MCU Read)
Figure 1-18. Port Data Delay Times
(MCU Write)
E~
____~x;;.~~~
Output
Timer 1
FRC
X~
_____
T2CNT
~ tTOD t-------''----.V;1.::2''"."''4V,.,-----
P2" P2 5
Outputs
P2 6
,"}f2-"'·"'BV.::......_ __
Figure 1-19. Timer 1 Output Timing
Output
I
Figure 1-20. Timer 2 Output Timing
Vee
j k
O.BV
tCKr
••
tCKf
-Timer 2; tteye
SCI
; tSeye
••
r
Test Point
1rl
C
C~90pF
"Timer 1 ; tPWT
Timer 2; tPWTCK
SCI
; tPWSCK
R
RL~2'2kQ
1S207<\®
or equiv.
for 00-0" Ao-A", E
~30pF for Port2, Port 6,
RD,
WR, R;W, BA,TiR
R~12kQ
Figure 1-21, Timer 1-2, SCI Input Clock
Timing
Figure 1-22. Bus Timing Test Loads
(TTL Load)
~HITACHI
475
Interrupt
Test
Internal Bus
Address
:=:x:t::C=X=:X=::C=X="::Jc:=x::=)(=::::>c::=x::=x.=:J!~::~=X="::JC
SP
SP-1
SP-2
SP-3
SP-4
SP-5 SP-6 ~§ll" r~'i:0r ~~w
AddressAddressAddress
Internal
DataBus ____A-__
~
__
_J~
__ A-__~___J~__~__~~-J''___~___A_ __ J ' __ _ A __ _
Op OperandlrrelevantPCQ- PCBCodeOp CodeData
PC7 pe15
Internal
IXOIX7
Ixa-
ACCA
ACee eCR
IX15
J, __
_''~
__I ' _
Vector Vector First Inst. of
MSB LSB
Interrupt Routine
,~------------------------------------~-------------------
Read
Internal
Wite
------',
,~---------------
Figure 1-23. Interrupt Sequence
Address
Bus
_~Il~I\IlOC:=X::"y"="y"=:J=:JC=:JC=~=:t;~r----C~
FFFF
FFFF FFFF FFFF FFFF FFFE FFFF New PC
FFFF
FFFF FFFF
~~r-----r!!--------
I
!;.:~;;·,_.tt'~\,
R/W
_~\\\\,\\t\\\\\\\\W
All
.I-\~\\~~\\\\~~~W
"'.\\~.
15
;~!------f'>-'-------
If
l~~i--l- - - - -
WR • •
~~:.
~J_ _~.~~)-,_ __
~0'--------pc~Y.~'-------------;'
PC15
PC7
Instruction
Figure 1-24. Reset Timing
@HITACHI
476
1.3 HD63701 XO, HD637 A01 XO, HD637B01 XO Electrical Characteristics
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Supply voltage
Vee
-0.3 to +7.0
V
Vpp voltage
Vpp
-0.3 to +22
V
I nput voltage
Vin
-0.3 to Vee+0.3
V
Operating temperature
Topr
o to
+70
'C
Storage temperature
Tstg
-55 to +125
'C
Note:
This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply Qvervoltage more than maximum ratings to these high input impedance protection circuits. To assure the
normal operation, we recommend Vtn. VOU.I: Vss ;;;! (V In or VOu.,) ;;;aVec.
Electrical Characteristics
DC Characteristics
(Vee = 5.0 V
± 10%. 1=0.1 to 2.0 MHz. Vss=OV. Ta=-20 to +70'C. unless otherwise noted.)
Item
Input high voltage
RES, STBY, MPo, MPl
EXTAL
Typ
Symbol
Min
VIH
Vee-0.5
Vee+0.3
Unit
V
VeexO.7
2.4
Vee+0.3
V
Vee+0.3
V
2.0
-0.3
Vee+0.3
O.B
V
Pzz(SCLK)3
Other inputs
Max
Test Condition
Input low voltage
All other inputs
VIL
Input leakage current
R§ Port 5
Ilinl
1.0
JlA
Vin=0.5 to Vee-0.5 V
IITsd
1.0
JlA
Vin=0.5 to Vee-0.5 V
2.4
V
IOH=-200 JlA
Vee-0.7
V
IOH=-10JlA
0.5
V
IOL-1.6 rnA
0.4
V
NMI, STBY. MPo. MPl
Three state
leakage current
Ports 1. 2, 3, 4,
6,7
Output high voltage
Output low voltage
VOH
Ports 2,6
VOL
Other outputs
Darlington drive
current
Ports 2. 6
Input capacitance
All inputs (except Vpp/OE)
-IOH
1.0
Cin
VpplOE
Standby current
Current dissipation l
Not operating
RAM standby voltage
10.0
rnA
Vout=1.5 V
6.5
pF
12.5
pF
Vin=OV, 1-1 MHz,
Ta=25'C
ISTB
3.0
15.0
ISLP
1.5
3.0
JlA
rnA
Sleeping
2.3
4.5
rnA
Sleeping
(1-1.5 MHzZ)
3.0
6.0
rnA
Sleeping
(1-2 MHzZ)
7.0
10.0
15.0
rnA
10.5
rnA
Operating (1-1 MHzZ)
Operating (1=1.5 MHzZ)
14.0
20.0
rnA
Operating (1-2 MHzZ)
lee
VRAM
2.0
I
V
(1-1 MHzZ)
V
Notes:
1.
2.
Vm min=Vcc -1.0V, V1L max=O.8V (All output terminals are at no load)
Current dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max. values about
current dissipations at x MHz operation are decided according to the following formula:
typo value
(I=x MHz)
=Iyp. value (1=1 MHz) Xx
(I=x MHz)
max. value
=max. value (1=1 MHz) Xx
(bolh Ihe sleeping and opera ling)
3.
Only serial clock use.
~HITACHI
477
AC Characteristics
(Vee-5.0
v ±1O%, 1-0.1 to 2.0 MHz, Vss-O v, Ta--20 to +70 'C, unless otherwise noted.)
Bus Timing
HD63701YO
Typ
Typ
HD637BOIYO
Typ
Max
Unit
10
~s
25
25
ns
25
25
ns
Max
Min
tcyc
10
0.666
Enable rise time
tEr
25
Enable fall time
tEf
25
Enable pulse width high level l
PWEH
450
300
220
ns
Enable pulse width low level l
PWEl
450
300
220
ns
Address, R/W delay time!
tAO
250
190
160
ns
Data delay time
(Write)
toow
200
160
120
ns
Data set·up time
(Read)
toSR
80
70
70
ns
Address, R/W hold time l
tAH
70
45
30
ns
Data hold time
(Write)l
tHw
70
50
35
ns
(Read)
tHR
0
0
0
ns
450
300
220
ns
Item
Symbol
Cycle time
Min
HD637AOIYO
Max
Min
10
0.5
RO, WR pulse widthl
PWRW
RD,
WR delay time
tRWo
40
40
40
ns
RD,
WR hold time
tHRW
30
30
25
ns
LfR delay time
tOlR
200
160
120
ns
LlR hold time
tHlR
30
30
25
ns
MR set·up time l
tSMR
400
280
230
ns
MR hold time!
tHMR
E clock pulse width at MR
PWEMR
Processor control set-up time
tpes
Processor control rise time
tPCr
100
100
100
Processor control fall time
tpCf
100
100
100
SA delay time
tSA
250
190
160
Oscillator stabilization time
tRe
Reset pulse width
PWRST
Note: I.
40
90
9
200
20
200
20
Condition
Fig. 1·25
Fig. 1·26
ns
~s
200
ns
ns
Figs. 1·27,
1·35,1·36
Figs. 1·26,
1·27
ns
Fig. 1·27
20
ms
Fig. 1·36
3
tcyc
These timings change in approximate proportion to tcyc. The figures in this characteristics represent those when tcyc is minimum (=in
the highest speed operation).
~HITACHI
478
0
Test
Peripheral Port Timing
HD637A01XO
HD63701XO
Item
Peripheral data
Symbol
Min
Unit
~::~ition
tpDSU
200
200
200
ns
Fig. 1·29
tpDH
200
200
200
ns
(Ports 2, 3
set-up time
5,6)
Peripheral data
(Ports 2, 3
hold time
5,6)
Delay time (From
(Ports I, 2, 3
enable fall edge to
4,6, 7)
peripheral output)
HD637B01XO
Max
Typ
Max
Typ
Min
300
tpWD
Min
Max
Typ
300
300
ns
Fig.I·30
Timer, SCI Timing
HD63701XO
5ymb
Item
01
Timer 1 input pulse width
tPWT
Min
SCI input
clock cycle
(Async. mode)
(Clock sync)
time (Clock sync. mode)
SCI receive data hold time
Max
2.0
Min
Typ
Max
2.0
400
400
Unit
Test
Condition
tcyc
Fig. 1·33
ns
teyc
Fig. 1·33
2.0
2.0
2.0
teyc
Fig. 1·28
ns
Fig. 1·28
200
tSRX
290
200
290
200
ns
290
tHRX
100
IpWSCK
0.4
Timer 2 input clock cycle
ttcyc
2.0
2.0
2.0
teyc
Timer 2 input clock pulse width
IpWTCK
200
200
200
ns
Timer 1 • 2, SCI input clock
rise time
fall time
100
0.6
0.4
0.4
I
ns
100
0.6
0.6
tscyc
tCKr
100
100
100
ns
leK!
100
100
100
ns
Timer 1 "2, SCI input clock
1·32
1.0
SCI input clock pulse width
(Clock sync. mode)
Figs 1·31
1.0
tTXD
SCI receive data set-up
Typ
HD637B01XO
1.0
SCI tra nsmit data delay
time (Clock sync. mode)
Min
400
tTOD
tScyc
Max
2.0
Delay time (enabl~ positive
transition to timer output)
Typ
HD637A01XO
Fig. 1·33
~HITACHI
479
toy.
~
E
V·
2.4V
\
PWel
I\O.BV
,1/
/
!--tAD_
Ao-A'!5
RIW
)<
\
\
PWeH
tEr
tE'
i<-2.4V
1\
tAH_
>C
I
Ic-O.BV
I - - tHRW
tRWD
PlIVRw
"
Jl!C2.4V
O.BV
!--tHW _
I---tDDW_
MCU It'.+ite
00-0,
./
~ O.BV
4-tDSR_
I--- tHR
2.0V
MC;U Read
00-0,
"-
O.BV
__ tDlR_
"
I--
O.BV
Figure 1-25. Mode 1, Mode 2 Bus Timing
~HITACHI
480
>-
2.4V
tHlR
r
1 - - - - - - - PW'MR - - - - - - 1
2.4V
\
\
\
\
O.BV
'-----
tSMR
MR
O.BV
Figure 1-26. Memory Ready and E Clock Timing
last Instruction
Instruction Execution
Cycle
SA
I
Figure 1-27. HALT and SA Timing
Synchronous Clock
Transmit Data
Receive Data
"2.0V is high level when clock input.
2.4V is high level when clock output.
Figure 1-28. SCI Clocked Synchronous Timing
~HITACHI
481
t
j
MCU Aead
MCU Write
P2o-P2,
~~~=~~; "'2"".O::-V,u~-----:L...:..u.----(Inputs) :::.O:..::.8:,,:,V-'l~_ _--'1<""""_---,___
Plo-Ph, P2o-P2, - - - - - - \.....,,-;;,,-P30-P3,. P4o-P4,
P6o-P6,. P7o-P7, _ _ _ _ _......J ......._ __
(Outputs)
Figure 1-29. Port Data Set-up and
Hold Times (MCU Read)
Figure 1-30. Port Data Delay Times
(MCU Write)
E~
Timer 1 - - - - - .
FAC
___
r-.~O~u:;:tP;,;;U,;-t- , r - - - -
......JX~~J,~
~
troo
X,-___
T2CNT
r--
P2,. P2 5------'--'""""V;r"
2'.""'4"'V--Outputs
f"}}o~::.·"'8.!.V _ __
Figure 1-31. Timer 1 Output Timing
P2 6
Output
Figure 1-32. Timer 2 Output Timing
Vee
Test Point
1rl
C
R
Al~2.2kQ
lS2074ift
or equiv.
C=90pF for Port 1. Port 3, Port 4, E
-Timer 2; tteye
SCI
; tSeye
"Timer 1; tpWT
Timer 2; tPWTCK
SCI
=30pF for Port 2. Port 6. Port 7
A=12kQ for Port l-Port4. Port 6. Port 7. E
; tpWSCK
Figure 1-33. Timer 1 '2, SCI Input Clock
Timing
Figure 1-34. Bus Timing Test Loads
(TTL Load)
~HITACHI
482
Interrupt
Test
Internal
Address Bus
_-i\....L_"--_.A.._...A_--P'--~"-_"-_..A_-"_..../''-~''-_;:.,.._.A,-_J':-:---''_-J'
SP
SP-l
SP-2
SP-3
SP-4
SP-5 SP-6 ~S~r ~siior ~Cw
AddressAddressAddress
Internal
DataBus_-J"-_~_~_~_-E'-~"-_~_~_-"'---''-~''-_J~_J~_J'_-'1,---J'-
Op OperandlrrelevantPCO- PC8CodeOp CodeData
PC7 PC15
Internal
Read
IXOIX7
IX8- ACCA ACCB CCA Vector Vector First Inst. of
IX15
MSB LSB Interrupt Routine
\'-------------------~----------
\~----------------
I
Internal
Wite
Figure 1-35. Interrupt Sequence
E
Vce
_.---u-u--4~~r-----{I{lULfUl
=£:t~
.1
tllC
S
___
Vcc- 0 5V
:t~'
f
f
STBY
~~)~~---------Vce- 0 SV
--
-
tpcs ~
tpcs
Vcc-O.SV
RES
----is
~;:~n"._~\
O.8V
5f
1-------1;f---------
I
/
~~:;;" -.\~\~\\~\\R/W
.~~\\.,\~~\W
I!1l
_~~\~,_
WR • •\\\\\\\\t\'
.•
~~:
i~~l
5f
---
~.".~~~~)t--.
PCB- PCO- FIrst
PC 1 S
PC7
Instruction
Figure 1-36. Reset Timing
~HITACHI
483
Programming Electrical Characteristics
DC Characteristics
(Vcc=5 v ± 5%, Vpp=21
v±
0.5
v,
Vss=O
v,
Ta=25 'C ± 5 'C, unless otherwise notes.)
Item
Symbol
Min
Max
Unit
Input high voltage
V,H
2.2
Typ
Vcc+ 1.0
V
0.8
Input low voltage
V,L
-0.1
Output high voltage
VOH
2.0
Output low voltage
VOL
V
0.45
Input leakage current
IllIl
Vpp voltage
Vpp
Vpp current
Ipp
20.5
21
Test Condition
V
IOH~-200!lA
V
IOL+1.6mA
V;n~5.25V/0.4V
10
!lA
21.5
mA
30
mA
Vpp-21V,
CE~V,v
AC Characteristics
(Vcc=5V± 5%, Vpp=12.5V± 0.3 V, Ta=25'C ± 5'C, unless otherwise noted.)
Item
Symbol
Min
Address set-up time
tAS
2
!-Is
!-Is
DE set-up time
tOES
2
DE hold time
tOEH
2
Typ
Max
Unit
Data set-up time
tDS
2
Address hold time
tAH
0
Data hold time
tDH
2
Output disable delay time
tDr
0
Data Valid from CE
tDV
CE pulse width
tpw
45
OE pulse rise time
tpRT
50
ns
Vpp recovery time
tVR
2
!-Is
Note:
Test Condition
!-Is
!-Is
50
130
ns
55
ms
tOF is defined when output becomes open because output level can not be refered.
Input Pulse level
O.B-2.2V
Input rising/falling time:a!20ns
{ input
Timing reference level
output
: l.OV, 2.0V
: O.BV, 2.0V
EAo-EA"
Program Verify
Program
~
Address
Ess
j--tAS_
EOo-EO,
--<
Data in Stable
I--tDS--
-- -- -tDH
Data Out Valid
tDY I--
tAH-
1\
Vpp/OE
tPRTCE
-- - tOES
tpw
tOEH
t:.
~
I'--'
Figure 1-37. PROM ProgramminglVerify Timing
~HITACHI
484
"
J
I>- tDF
Appendix II. Instruction Execution Cycles
11.1 Instruction Execution Cycles
By the pipeline control of the HD6370lXO, MULT, PUL, DAA and XGDX instructions etc. pre fetch the next
instruction. So attention is necessary to the counting of the instruction cycles because it is different from the
existent one······ op-code fetch to the next instruction op-code.
Address Mode &
Instructions
Address Bus
Data Bus
IMMEDIATE
1
2
Op Code Address + 1
Op Code Address + 2
1
1
0
0
1
1
1
0
Operand Data
Next Op Code
1
2
Op Code Address + 1
Op Code Address + 2
Op Code Address + 3
1
1
1
0
0
0
1
1
1
1
1
0
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Op Code Address + 1
Address of Opera nd
Op Code Address + 2
1
1
1
0
0
0
1
1
1
2
3
1
1
0
Address of Operand (LSB)
Operand Data
Next Op Code
1
2
3
Op Code Address + 1
Destination Address
Op Code Address + 2
1
0
1
0
1
0
1
0
1
1
1
0
Destination Address
Accumulator Data
Next Op Code
1
2
3
4
Op Code Address + 1
Address of Opera nd
Address of Opera nd + 1
Op Code Address+2
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
4
1
2
3
4
Op Code Address + 1
Destination Address
Destination Address + 1
Op Code Address + 2
1
0
0
1
0
1
1
0
1
0
0
1
1
1
1
0
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
5
1
2
3
4
5
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer-l
Jump Address
1
1
0
0
1
0
1
1
1
0
1
1
0
0
1
1
1
1
1
0
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
4
1
2
3
4
Op Code Address+ 1
Op Code Address+2
Address of Opera nd
Op Code Address + 3
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
Immediate Data
Address of Operand (LSB)
Operand Data
Next Op Code
Op Code Address + 1
Op Code Address + 2
Address of Operand
FFFF
Address of Operand
Op Code Address+3
1
6
1
2
3
4
5
6
0
0
0
1
1
0
1
1
1
1
1
0
Immediate Data
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
ADC
AND
CMP
LDA
SBC
ADD
BIT
EOR
ORA
SUB
2
ADDD
LDD
LDX
CPX
LDS
SUBD
3
3
DIRECT
ADC
AND
CMP
LDA
SBC
ADD
BIT
EOR
ORA
SUB
1
3
STA
3
ADDD
LDD
LDX
CPX
LDS
SUBD
STD
STX
STS
4
JSR
TIM
AIM
OIM
ElM
1
1
1
0
1
1
1
1
1
1
0
1
(conltnued)
~HITACHI
485
Address Mode &
Instructions
Address Bus
Data Bus
INDEXED
JMP
3
ADC
AND
CMP
LDA
SBC
TST
ADD
BIT
EOR
ORA
SUB
4
STA
4
ADDD
LDD
LOX
ADD
CPX
LDS
SUBD
STD
STX
STS
Op Code Address+ 1
FFFF
i
1
0
1
1
1
1
1
Offset
Restart Address (LSB)
3
Jump Address
1
0
1
0
First Op Code of Jump
Routine
1
2
Op Code Address + 1
FFFF
IX+Offset
Op Code Address + 2
1
1
1
1
0
1
1
1
1
1
1
1
Offset
Restart Address (LSB)
Opera nd Data
Next Op Code
Op Code Address + 1
FFFF
IX+Offset
Op Code Address+ 2
1
1
0
3
4
1
2
3
4
1
2
5
3
4
5
1
2
5
JSR
3
4
5
1
2
5
ASL
COM
INC
NEG
ROR
1
2
ASR
DEC
LSR
ROL
3
4
5
1
2
6
TIM
3
4
5
6
1
2
5
3
4
5
CLR
5
1
2
3
4
5
AIM
OIM
ElM
1
2
3
7
4
5
6
7
1
0
0
0
1
1
0
1
1
1
1
0
1
0
Op Code Address + 1
FFFF
IX+Offset
IX+Offset+ 1
Op Code Address + 2
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
Op Code Address + 1
FFFF
IX+Offset
IX+Offset+l
Op Code Address+ 2
1
1
0
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
1
0
1
1
0
0
1
1
1
1
1
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer-l
IX+Offset
Op Code Address+ 1
FFFF
IX + Offset
FFFF
IX+Offset
Op Code Address+ 2
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
1
1
1
0
1
0
1
0
Op Code Address+ 1
Op Code Address+ 2
FFFF
IX + Offset
Op Code Address + 3
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
Op Code Address + 1
FFFF
IX + Offset
IX + Offset
Op Code Address + 2
1
0
1
1
1
Op Code Address+ 1
Op Code Address + 2
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address+3
1
0
0
0
Offset
Restart Address (LSB)
Accumulator Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Offset
Restart Address (LSB)
Opera nd Data
Restart Address (LSB)
New Opera nd Data
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Opera nd Da ta
Next Op Code
0
1
1
1
0
1
0
1
1
1
1
1
0
1
0
Next Op Code
1
1
1
1
1
0
0
1
1
1
1
1
Immediate Data
Offset
Restart Address (LSB)
Opera nd Da ta
Restart Address (LSB)
New Opera nd Data
Next Op Code
0
1
1
0
1
1
1
1
1
1
1
0
1
0
1
0
Offset
Restart Address (LSB)
Operand Data
00
(continued)
~HITACHI
486
Address Mode &
Instructions
Address Bus
Data Bus
EXTEND
JMP
3
ADC
AND
CMP
LDA
SBC
ADD TST
BIT
EOR
ORA
SUB
4
STA
4
ADOO
CPX
LOS
SUBD
STD
STX
LOO
LOX
5
STS
5
1
2
3
Op Cope Address + 1
Op Code Address + 2
Jump Address
1
1
1
0
0
0
1
1
1
1
2
3
4
Op Code Address + 1
Op Code Address + 2
Address of Operand
Op Code Address + 3
1
1
1
1
0
0
0
0
1
1
1
1
1
2
3
4
Op Code Address + 1
Op Code Address + 2
Destination Address
Op Code Address + 3
1
1
0
0
1
1
0
1
0
1
1
1
1
0
1
0
1
2
Op Code Address+ 1
Op Code Address + 2
Address of Opera nd
Address of Operand+ 1
Op Code Address + 3
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
Op Code Address+ 1
Op Code Address + 2
Destination Address
Destination Address + 1
Op Code Address+3
1
1
0
0
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
1
1
0
0
1
1
1
1
3
4
5
1
2
3
4
5
JSR
1
6
ASL
COM
INC
NEG
ROR
ASR
DEC
LSR
ROL
6
2
3
4
5
6
1
2
3
4
5
6
CLR
1
2
5
3
4
5
Op Code Address + 1
Op Code Address + 2
FFFF
Stack Pointer
Stack Pointer-l
Jump Address
Op Code Address + 1
Op Code Address + 2
Address of OP.l!rand
FFFF
Address of Operand
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Opera nd
Op Code Address + 3
1
1
1
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
1
1
1
0
1
0
1
1
1
1
0
0
0
1
1
1
1
Jump Address (MSB)
Jump Address (LSB)
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Next Op Code
Destination Address (MSB)
Destination Address (LSB)
Accumulator Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (MSB)
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (MSB)
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
0
1
1
0
1
1
1
1
1
1
0
1
0
1
1
1
0
0
0
1
1
1
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
0
1
0
1
1
1
1
1
0
1
0
Next Op Code
I
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Opera nd Data
Next Op Code
00
(continued)
~HITACHI
487
Address Mode &
Instructions
Address Bus
Data Bus
IMPLIED
ABA
ASL
ASR
CLC
CLR
COM
DES
INC
INX
LSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
ABX
ASLD
CBA
CLI
eLV
DEC
DEX
INS
LSR
ROL
NOP
SEC
SEV
TAP
TPA
TSX
DAA
XGDX
PULA
PSHA
1
Op Code Address + 1
1
0
1
0
Next Op Code
2
1
2
Op Code Address + 1
FFFF
1
1
0
1
1
0
Next Op Code
Restart Address (LSB)
1
2
3
Op Code Address + 1
FFFF
Stack Pointer+ 1
1
1
1
0
1
1
1
0
3
1
2
Op Code Address + 1
FFFF
Stack Pointer
Op Code Address + 1
1
1
0
1
1
1
1
1
1
PULB
PSHB
4
PULX
4
PSHX
3
4
1
2
3
4
1
2
5
RTS
3
4
5
1
2
5
MUL
3
4
5
1
2
7
3
4
5
6
7
0
1
1
1
0
1
1
0
0
Op Code Address + 1
FFFF
Stack Pointer+ 1
Stack Pointer+2
1
1
1
1
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer-l
Op Code Address + 1
1
1
0
0
1
Op Code Address + 1
FFFF
Stack Pointer+ 1
Stack Pointer+ 2
Return Address
1
1
1
1
1
0
1
Op Code Address + 1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
1
1
1
1
1
1
1
0
1
1
1
0
0
Next Op Code
Restart Address (LSB)
Data from Stack
Next Op Code
Restart Address (LSB)
Accumulator Data
Next Op Code
1
1
1
Next Op Code
Restart Address (LSB)
Data from Stack (MSB)
Data from Stack (LSB)
1
1
0
0
1
1
1
1
1
0
Next Op Code
Restart Address (LSB)
Index Register (LSB)
Index Register (MSB)
Next Op Code
1
1
1
1
0
Next Op Code
Restart Address (LSB)
Return Address (MSB)
Return Address (LSB)
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
Next Op Code
Restart Address
Restart Address
Restart Address
Restart Address
Restart Address
Restart Address
1
0
0
0
1
1
1
0
0
0
1
1
1
1
1
First Op Code of Return Routine
(LSB)
(LSB)
(LSB)
(LSB)
(LSB)
(LSB)
(continued)
~HITACHI
488
Address Mode &
Instructions
Address Bus
Data Bus
IMPLIED
WAI
9
1
2
3
4
5
6
7
8
9
RTI
10
1
2
3
4
5
6
7
8
9
10
SWI
12
SLP
Op Code Address + 1
FFFF
Stack
Stack
Stack
Stack
Stack
Stack
Stack
Pointer
Pointer-1
Pointer-2
Pointer-3
Pointer-4
Pointer- 5
Pointer-6
Op Code Address + 1
FFFF
Stack Pointer+ 1
Stack Pointer+2
Stack Pointer+3
Stack Pointer+4
Stack Pointer+ 5
Stack Pointer+6
Stack Pointer+ 7
Return Address
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
1
1
1
1
1
1
1
1
1
0
Next Op Code
Restart Address (LSB)
Conditional Code Register
Accumulator A
Accumulator B
Index Register (MSB)
Index Register (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
1
1
1
1
1
1
1
1
1
1
1
8
9
FFFF
Stack
Stack
Stack
Stack
Stack
Stack
Stack
10
Vector Address FFFA
11
Vector Address FFFB
1
0
1
1
12
Address of SWI Routine
1
0
1
0
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine
(MSB)
Address of SWI Routine
(LSB)
First Op Code of SWI Routine
1
2
Op Code Address + 1
FFFF
1
1
0
1
1
1
1
1
Next Op Code
Restart Address (LSB)
1
1
1
1
I
1
0
1
FFFF
Op Code Address + 1
1
1
1
0
1
2
3
4
5
6
7
Op Code Address + 1
1
1
0
0
0
0
0
0
0
Pointer
Pointer-1
Pointer-2
Pointer- 3
Pointer-4
Pointer- 5
Pointer-6
1
1
1
1
1
1
4
Sleep
1
3
4
1
Restart Address (LSB)
Next Op Code
(continued)
~HITACHI
489
Address Mode &
Instructions
Address Bus
Data Bus
RELATIVE
BCC
BEQ
BGT
BlE
BlT
BNE
BRA
BVC
BCS
BGE
BHI
BlS
BMT
BPl
BRN
BVS
1
2
3
BSR
5
3
1
2
3
4
5
Op Code Address +.1
FFFF
{Branch Address .. ·Test="J"
Op Code AddresS+2.. ·Test="Q"
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer-l
Branch Address
1
1
0
1
1
1
1
1
1
0
1
0
1
1
0
0
1
0
1
1
1
0
1
1
0
0
1
1
1
1
1
0
~HITACHI
490
Branch Offset
Restart Address (lSB)
First Op Code of Branch Routine
Next Op Code
Offset
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
First Op Code of Subroutine
Appell1ldOJ{
~~t
Questioll1ls all1ld Answers
This appendix contains saine frequently asked questions about the HD6301 XO, HD63701 XO, and
HD6303X.
111.1 Parallel Ports
111.1.1 DDR and Data Register
Question: Should the data or DDR (data direction register) be set first, when an I/O port functions as
an output port?
Answer: Output data should be stored in the data register first, then DDR should be set (DDR
= 1). If
DDR is set first, unknown data will be output from the port .
.Supplement: DDR (data direction register)
DDR programs I/O port as an input or output.
= 1:
DDR = 0:
DDR
output
input
DDR is initialized to 0 during reset.
111.1.2 Port 7 Upper Bits
Question: What is the state of the upper 3 bits in port 7 (5-bit output port) when reading port 7 in
mode 3 (single chip mode)?
Answer: The upper 3 bits in port 7 are all set to 1. Port 7 DDR can read the contents of the data
register by using the bit manipulation instruction.
Supplement: Ports 1 and 4 can also be read with bit manipulation instructions.
111.1.3 SCLKlP22 Pin
Question: How do you use the P22 (SCLKlP22 multiplexed pin) as an I/O port?
Answer: To use the P22 as an I/O port, set bit 1 in the port 2 DDR (data direction register), and CCO,
CC1, and CC2 in the RMCR (rate/mode control register) as in table 111-1.
~HBTACHD
491
Table 111-1. P22 I/O Settings
Bit
Setting
Bit 1 of port 2 DDR
(Note1 )
o (Input port)
1 (Output port)
CCO (Note 2)
CC1
o
CC2
Oar 1
Notes:
1. Bit 1 of the port 2 DDR selects the direction of 7 bits P21 - P27.
2. During reset, CCO, CC1 and CC2 are cleared to 0 and the P22 functions as SCLK pin.
Supplement: The CCO, CC1, and CC2 (clock control format select) program the SCI data format and
the SCI clock direction.
The DDR (data direction register) programs the direction of the 1/0 port.
DDR = 0: Input
DDR = 1: Output
111.1.4 P5a/HALT Pin
Question: How can P53 (P53/HALT multiplexed pin) be used as an input-only port in expanded
mode (modes 1 and 2)?
Answer: In expanded mode, P53 functions as HALT pin with HLTE bit = 1 during reset. To use P53
as an input port, hold it high until 0 is written in the HLTE after reset, inhibiting HALT input.
111.2 Serial Port
11.2.1 RDRF in Wake-Up Mode
Question: When using the SCI in the asynchronous mode with the receive enable bit (RE) of the
transmiVreceive control status register (TRCSR) = 1 and wake-up bit (WU)
= 1, what is the state of the
receive data register full bit (RDRF)?
7
TRCSR
6
5
4
I RDRF I ORFE I TORE I RIE
o
3
RE
2
TIE
1
o
TE
wu
1
Figure 111-1. Transmit/Receive Control Status Register in Wake-Up Mode
492
~HITACHI
Answer: When the wake-up flag is set (WU = 1), the RDRF flag is not set (RDRF = 0).
111.2.2 SCLK Direction and DDR
Question: When using the P22 (SCLKJbit 2 of 1/0 port 2) as the SCI clock 1/0, is the clock direction
determined by CCO, CC1 and CC2 (clock controVform select) in the RMCR (rate/mode control register)
regardless of bit 2 of the port 2 DDR?
Answer: Yes, it is determined by CCO, CC1 and CC2 independently of the port 2 DDR. When used as
an 1/0 port, its 1/0 direction is determined by bit 2 of the port 2 DDR. In this case, CCO, CC1 and CC2
should be set to a mode where P22 is not used as SCI clock (CCO, CC1, and CC2 set to 101, or 100).
CCO, CC1, and CC2 are cleared to
a at reset (table 111-2).
Table 111·2. P22 Direction
Port 2 DDR
P22
SCLK
Input or output
No effect
I
CCO, CC1, CC2 determine
CCO
CC1
0
CC2
oor 1
clock form, direction
Supplement: The CCO, CC1, and CC2 (clock control format select) program the SCI data format and
the SCI clock direction.
The DDR (data direction register) programs the direction of the 1/0 port.
DDR =0: Input
DDR =1: Output
111.2.3 Receive Sampling Clock
Question: What is the relation between the receive data sampling clock at the SCI receive, and the
data transfer rate?
Answer: The sampling clock is sixteen times as fast as the transfer rate.
~HITACHI
493
111.2.4 Sampling Error
Question: What does "sampling error" mean?
Answer: "Sampling error" means receive margin in SCI operation. The HD63701 XO detects a start bit
at the negative edge of the sampling clock, and samples the start bit and data bit at the positive edge of
the sampling clock.
The general equation of the receive margin is shown as follows (figure 111.2).
M = {(0.5 - 1/2N) - (D - 0.5)/N - (L - 0.5)Fl x1 00 (%)
M: Receive margin
N: Baud rate ratio to sampling clock
D: Duty of the longer sampling clock of high and low (0.5 - 1)
L: Frame Length (7 - 12)
F: Absolute value of deviation of sampling clock frequency
An abbreviated version is:
M = (0.5 -1/2N) x 100 (%) (Condition: D = 0.5, F =0)
N
8
16
32
M
(%)
43.75
46.875
48.4375
o
2
3
Note
64
HD63701XO:
N=16
49.21875
4
5
6
7
7.5,8
Clock
1 i
I
Rx
1TlL-+iI_______________ I
~, i
!
I
1/N
,.
..~.
I
Start Bit 0.5
50%
! 46.875%
r::
I
Start bit activates
11/2N
Start bit sampling
Figure 111-2. Sampling Error
~HITACHI
494
I
r--t-i4-6.8-75%
111.3 Timer/Counter
111.3.1 Reading the FRC
Question: When you read the free-running counter (FRC) of the timer 1 by a double-byte load
instruction, is the read value correct?
Answer: It is correct. In the first cycle, the high byte of the FRC is read, when the low byte is set in a
temporary register. At the next cycle, the data stored in the temporary register is read (figure 111-3).
, high byte read
I
I
I
I
I
low byte read
I
I
E
FRC
$.EZ
Temporary
register
FF
T
I
$F8
00
fFFl
t.. __ J
Read data
$FF
$F7
I
Accumulator D
(When reading $F7FF from the FRC)
F7
FF
Figure 111-3. FRC Double-Byte Read
Supplement: To read the timer FRC correctly, use double-byte load instructions (LDD,LDX).
11.3.2 Reading the FRC in the HD6801V
Question: How is FRC writing in the HD6301XO, HD6303X, and HD63701XO different from the
HD6801V?
Answer: The difference is shown in table 111-3.
Table 111-3. HD6301 XO/HD6303X1HD63701 XO and HD6801V Write Differences
Type
How to Write (Preset)
HD6801V
The FRC is always preset to $FFF8.
HD6301XO, HD6303X,
HD63701XO
Writing to the high byte presets the FRC to $FFF8.
Data is always set in the FRC by a double-byte store instruction.
See figure 111-4 for an example.
~HITACHO
495
(I) The H06801 V preset method
-
E
I
FRC
$FFFB
I
II
LOO #$5AF3
STO$09
I
$FFF9
I
$FFFA
1
i-
The FRC Is always preset to $FFFB.
(2) The H06301 XO/H06303X1H063701 XO preset method ($5FA3)
$FFFB
LOO #$5AF3
-STAA$09
E
$FFFB
FRC
$FFF9
$FFFA
Writing to the high by1e $09 the FRC to $FFFB.
-
Optional value (In this case $5AF3)
LOO #$5AF3
-STO$09
E
FRC
$FFFB ,
$5AF3
$5AF4
-
A double-by1e store instruction presets the FRC to optional ($5AF3) value
Figure 111-4. FRC Writing for HD6301XOIHD6303X1HD63701XO and HD6801V
111.3.3 ECMllnterrupt
Question: Timer 2 is used by writing 0 to enable counter match interrupt (ECMI) of the timer
controVstatus register 3 (TCSR3). When a counter match flag (CMF) of TCSR3 becomes 1, 1 is written
to ECMI. Does this generate an interrupt?
Answer: Yes. When the time constant register (TCONR) matches the timer 2 counter, the CMF is set
to 1 and kept at 1 unless 0 is written in by software. An interrupt will occur if ECMI = 1 after CMF = 1.
Supplement: A timer 2 interrupt is generated with CMF = 1 and ECMI = 1.
ECMI defines internal interrupt (lRQ3) enable/disable.
ECMI
=0:
disable
ECMI = 1: enable
111.3.4 SCI and Writing to Timers
Question: When the SCI is operating, can data be written into the timer 1 FRC or timer 2 T2CNT?
Answer: If the SCI is using an extemal clock, the timer 1 FRC and the timer 2 T2CNT can be written
~HITACHI
496
into. In the case of an internal clocl<, either the FRC or the T2CNT is used as a clock-source counter
(note 1). No clocl<-source counter can be written to. Note that there are some restrictions, as follows:
1. External clock operation
a. Timer 1 FRC can be written to
b. Timer 2 T2CNT can be written to
2. Internal clock operation
a. Using timer 1 FRC as an internal clock
- Don't write to the timer 1 FRC during SCI operation.
- Timer 2 T2CNT can be written to.
b. Using timer 2 T2CNT as an internal clock
- The timer 1 FRC can be written to, except when input clock to T2CNT is El8 or El128. El8,
El128 come from the timer 1 FRC. If these clocks are selected as T2CNT input clocks, writing to
the FRC will delay them.
- Don't write to timer 2 T2CNT during SCI operation.
Supplement: When an internal clock is operating the SCI, writing to the clock-source counter will
delay the SCI transfer rate.
111.4 Bus Inter1ace
111.4.1 E and Memory Ready
Question: What is the internal E clocl< state when the CPU uses the memory ready function?
Answer: Internal E clock operates at normal frequency (figure 111-5). Since the timer count and the SCI
transfer rate are set by the internal E clocl<, they are not also affected by the memory ready function.
Internal E
External E
MR
(Memory ready signal)
Figure 111-5. Internal and External E Clocks
Supplement: It is impossible to examine the internal E clock from an external pin when using the
memory ready function.
@IHWiiACHll
497
111.4.2 Memory Ready and Halt After Reset
Question: After reset, are memory ready and halt functions enabled or disabled?
Answer: Both are enabled. MR and HALT in three operating modes is shown in table 111-4.
Table·III-4. Operating Modes
Operating Mode
Memory Ready
Halt
Expanded mode
Enabled (note)
Enabled
Enabled (note)
Enabled
No memory ready function
No halt function
2
Single-chip mode
Note: Invalid when accessing internal address space
Supplement: In the expanded mode (modes 1, 2), the memory ready bit (MRE) and halt enable bit
(HLTE) of the RAM/port 5 control register are set to 1 during reset, enabling memory ready and halt
functions.
111.4.3 Buses at Internal Address Access
Question: When you access internal memory space, what states are the address buses, data buses,
and control lines in?
Answer: Address buses and control lines (RD, WR, R/W) are always output regardless of internal or
external address space accessing. During writes to the internal address space, the same data is output
from the data bus. During reads, the data buses become high impedance.
111.4.4 External Access to Register Addresses
Question: When using external memory at the addresses shown below in expanded modes (modes
1,2), some addresses overlap internal registers and RAM addresses (figure 111-6). In such a case, are
there any problems?
~HITACHI
498
Internal Memory Map
Internal
register
External Memory Map
r7'7'T7'7'T7'77'T'1'TT7TT7'r
~o
.p
7jj
I
I
Internal reset signal
0
Q
0
Q
Internal
Figure 111-12. Reset Circuit
111.7.4 Reset Circuit Capacitance
Question: Does Cr in the reset circuit shown in figure 111-13 (Rr x Cr > 20 rns), have an upper limit?
r--------------------+--~--_;STBY
Rr
crJ;
'--------------+-------...., PORT
Release Standby
mode
(External input)
Rr· Cr
Figure 111-13. Reset Input Circuit
Answer: No, because RES is provided with a Schmitt trigger circuit (figure 111-12).
~HITACHI
504
>
20ms
111.8 Low Power Dissipation Mode
111.8.1 Standby During Instruction Execution
Question: Does the CPU wait until the current instruction is executed to enter the standby mode?
Answer: No. The CPU enters standby mode regardless of the current instruction; the CPU goes into
reset condition and the oscillator stops with STBY low (figure 111-14).
~ Oscillator Stop Internal reset
I
I
E
I
STBY ----------------------~
Figure 111-14. E During Standby
111.8.2 Standby Timing
Question: The timing for the standby mode is shown in figure 111-15 (see also figure 3-5). Is T1 in the
figure defined?
Vcc
r-----..,
CDNMll~-------_jI~
I
CD
I
I
NMI
I
I
i T,I
I.......,
@RES--I-i:11..m11.LL..li-------iJIf--~1
MCU
STBY
CD
I
I
I
I
I
I
I
I
I
I--tl
CD STBY--....
J,tl
!
1 f t ". . ,
I11111
RES
I
®
1
Oscillator
I
1
:
I
I
I
I
I
:
' • • 1.
Standby Mode
_I.I
I
o Register Save
o RAM/Port 5 Control Register Set
J I Stabilization
I
I
Time
1
~
Restart
Figure 111-15. Standby Mode Timing
Answer: It is not, but if the time for nonmaskable interrupt (NMI) is guaranteed, either RES or STBY
can go low with no priority.
Supplement: The CPU goes to the standby mode independently of instruction execution
sequence. Use the NMI routine before entering standby mode.
~HITACHI
505
111.8.3 Ports at Standby
Question: What is the state of each I/O port during standby?
Answer: Each I/O port and E pin during standby is high impedance.
111.8.4 Return from Standby Without Reset
Question: What occurs when the CPU returns from the standby mode without using reset start?
Answer: The CPU does not operate normally because the contents of each register are not defined.
Therefore, always use the reset start when returning from the standby mode.
111.8.5 Sleep and. Standby Internal States
Question: What are the internal states in the sleep or standby mode?
Answer: They are as shown in table 111-7.
Table 111-7. Sleep and Standby Mode States
Sleep Mode
Standby Mode
Oscillation circuit
Continues
Stops
CPU (register)
Stops (retained)
Stops (undefined)
RAM
Retained
Retained
I/O
Retained
High impedance
Timer
Continues
Stops
Serial communications
Continues
Stops
Internal registers
Retained
Reset
Cancel
Interrupt
STBY = low
Reset start
Reset start after STBY
= high
Supplement: Internal states in the standby mode are the same as those in reset start. Use the reset
start when returning from the standby mode. In this case RES should be kept low from STBY = high
during oscillation stabilization time (20 ms minimum).
@HITACHI
506
111.9 Software
111.9.1 Bit Manipulation Instructions
Question: How should the bit manipulation instructions of the HD6301 XO, HD6303X, and
HD63701 XO be written?
Answer: They are written as shown in figure 111-16.
aiM # $
aiM # $
°°
4 . $ 1
4 . $ 1
°°.
(Direct Addressing)
X (Index Addressing)
I~~
Immediate Data
Address
Index Register
Figure 111-16. aiM Example
This is an example of OR operation between the immediate data and the memory which stores the result in
the memory. The AIM, ElM, and TIM instructions are
wr~ten
in the same way.
The bit manipulations in table 111-8 have different mnemonics with the same opcode.
Table 111-8. Shared Opcodes
Bit Manipulation
Instruction
Instructions Having the Same Opcode
Mnemonic
Function
AIM
BCLR
OAND Mi
The memory bit i (i = 0 to 7) is cleared and the other
bits don't change
aiM
BSET
10RMi
The memory bit i (i = 0 to 7) is set and the other bits
don't change
ElM
BTGL
Mi EaR Mi
The memory bit i (i = 0 to 7) is inverted and the other
bits don't change
TIM
BTST
1 ANDMi
AND operation test of the memory b~ i (i =0 to 7) and
1 is executed and its corresponding condition code
is changed.
The mnemonics mentioned above can be written as in figure 111-17.
BCLR
BCLR
- - - AIM
3,$10
3,$10,X
AIM
#$F7,
#$F7,
$10
$10,X
(Direct Addressing)
(Index Addressing)
BSET
BSET
3,$10
3,$10,X
aiM
aiM
#$08,
#$08,
$10
$10,X
(Direct Addressing)
(Index Addressing)
~f
Bit Address Index Register
Figure 111-17. Shared Opcode Instruction Format
~HITACHI
507
111.10 Others
111.10.1 RAME Disabled
Question: When executing a program with the RAM enable bit (RAME) of the RAM/port 5 control
register disabled (RAME = 0),
1. What occurs if the internal RAM address is accessed?
2.
What occurs if interrupt requests are generated?
Answer:
1. The intemal RAM cannot be accessed. lfis neither readable nor writable with RAME = 0, so in mode
1 or 2, the external memory is readlwritten into.
2. Interrupts are accepted, but the CPU will burst when returning from the interrupt with no stacking
area other than the internal RAM.
Supplement:
1. RAME = 0; internal RAM is invalid. In modes 1 or 2, data can be read from the external memory.
2. RAME = 1; internal RAM is enabled.
111.10.2 RAME at Reset
Question: Is the RAM enable bit (RAME) set to 1 on reset at RES low or the rising edge of RES?
Answer: It is set at the rising edge of RES (figure 111-18).
Internal RAM
Disable
(RAME=O)
-tI
I
Internal RAM
Enable
(RAME=l)
I
Figure 111-18. RAME at Reset
Supplement: RAME is seVcleared by the software.
1. RAME = 0; Internal RAM is invalid. In mode 1 or 2, data can be read from the external memory.
2. RAME = 1; Intemal RAM is enabled.
~HITACHI
508
Appendix IV. The Differences Between HD63701 XO and
HD6301XO
IV.1 The Differences Between HD63701 XO and HD6301 XO
Item
HD63701XO
Vpp/OE pin
Vpp/OE
MCU mode; Connected to VSS voltage Connected to VSS Voltage
function
HD6301XO
Vss
PROM mode; Input for the
programming voltage
Input
capacitance
Vpp/OE
All other inputs
Input high
VIH = VSS -
25pF max
All inputs
12.5pF max
1 2.5pF max
VIH = 2.0V min
O.5V min
voltage of
MPO, MP1
Bus Timing
. Address,
tAH
tHw
HD63701XO
70
70
HD637A01XO HD637B01XO
45
30
50
35
R/W, hold
HD6301XO
80
80
tAH
tHW
HD63A01XO
50
50
Unit:ns
HD63B01XO
35
40
Unit: ns
timing
. Data hold
timing
Crystal
Internal resistance of crystal oscillator Internal resistance of crystal oscillator
oscillator
RS
RS
characteristics
Frequency (MHz)
RS
RS max (n)
Storage
T stg = - 55 to 125°C
=
T stg
60n max
= - 55 to 150°C
temperature
Caution
The HD63701 XO differs from HD6301 XO in chip deSign and manufacturing
process. When applying the HD63701 XO system to HD6301 XO, and
HD6301 XO system to HD63701 XO, note that characteristic values are not
exactly the same even if guaranteed values are the same.
@HITACHI
509
I
Appendix V. Program Development Procedure and
Support System
V.1 Overview
The cross assembler and the hardware emulator using various types of computer are prepared by
the company as supporting systems to develop user's programs. User's programs are mask
programmed into the ROM and delivered as the LSI by the company.
Figure V-1 shows the typical program design procedure and Table V-1 shows the system
development support tool for HD6301XO and HD6303X which are used in these processes.
Text Edi tor fCRT Editor
Host Computer
Host Computer
Emulator EPROM
On-Chip LSI.
HD63701YOC
Figure V-1. Program Design Procedure
~HITACHI
510
(Explanation)
1.
When the user programs the system using the HD6301 XO series, a functional assignment
of each I/O pin and an allocation of RAM area should be specified adjusting to designed
system before actual programming.
2.
A flowchart is designed to implement the functions and it is coded by using the HD6301 XO
mnemonic code.
3.
Write the software coded according to the flowchart on a floppy disk to make a source
program.
4.
Assemble the source program to generate an object program using a computer. Assembly
5.
Verify the program through hardware emulation with an emulator or EPROM on-chip type
errors are also detected.
microcomputer.
6.
Send the completed program to the company in the form of EPROM. Send Single-chip
microcomputer order specification and Masl< option list at that time.
7.
ROM and mask option are masked by the company. LSI is testatively produced and the
sample is handed in to the user. If a user doesn't see any problem in programming, mass
production can be started.
I
Table V-l Support Tools
Part
Emulator
EPROM on-
No.
HD6J01XO,
HD6JOJX
EPRO~! on-chip LSI
Programming Socket Adapter
IBM PC
IBM PC
chip LSI
Cross Assembler
C Compiler
HD6J701XOC
H67PWAOl
SJlIBMPC
USJ1PCLIlSF
HJ1MIX2
(HSJ1XEML02H)
HD6301XO and HD6303X Development Tools
~HITACHI
511
V.2 Single Chip Microcomputer ROM Ordering Procedure
V.2.1 Development Flowchart
Single chip microcomputer device is developed according to the following flowchart after
program development.
Device Development Flowchart
Customer
Hitachi
1
ROM code *1
2
Mask Option List *2
3
Ordering Specifications
Remarks
*1 2 sets of EPROM
*2 Part specific
*3
*3 Generic for Hitachi
microcomputers
,
Computer processing
ROM code for confirmation
*4 The same ROM code
as submitted.
of ROM fabricating
specifications *4
OK
4
Verification Listing
*5 Send it back after
approving
Mask
Sample
Working Sample (WS) *6
*6 3 pes.
1
15
*7 Start the following
flowchart after
approving
Confirmation of function,
characteristics *7, *8
*8 Send back signed
working sample
approval form.
OK
*9 10 pes.
+
Engineering Sample (ES) *9
t
IConfirmation of function,
Icharacteristics, quality
Commercial Sample (CS)
1
j
(E~D)
Note. Please send In 1 , 2, and 3 at ROM ordenng, and send back 4, 5 after approving.
~HITACHI
512
V.2.2 Data you send and precautions
(a) Ordering specifications .................... Common style for all Hitachi single chip
microcomputer devices. Please enter as for the
followings. The format is shown in the next page.
Basic ITEM
Environment Check List
Check List of attached data
Customer
(b) ROM code ................................ Please send in the ordering ROM code by 2 sets
of EPROM the same contents are written. Enter
ROM code No. in them. It is desirable to send in
program list for easy confirmation of the program
contents.
V.2.3 Change of ROM code
Note that if you change the ROM code once sended in or other specification, the ROM must be
developed from the beginning. The cost of mask charge should be provided again in this case.
V.2.4 Samples and Mass production
(Working Sample) ........................... .
Sample for confirmation of the contents of ROM
code and that of mask option. Normally samples
are sent but not guaranteed as for reliability. Please
evaluate and approve immediately because the
following sample making and mass production are
set about after obtaining your evaluation.
(Engineering Sample) ........................ .
(Commercial Sample) ........................ .
(Mass Product) .............................. .
Sample for evaluating also reliability. 10 pcs are
included in mask charge.
Samples for pre-production which may be
purchased separately.
Products for actual mass production. Please enter
the plan of mass production in full.
~HITACHI
513
I
V.2.5
HD6301XO
ORDERING SPECIFICATIONS
(1) GENERAL CHARACTERSITICS (Fll'
1 In blank space or c heck appropnate ox
Customer
Package Outline
(See page 380.)
Device
Type
Application
(be specific)
Customer
ROM Code ID
ZTAT TM
Conversion
ROM Code
Media
o
DP-64S
D
CP-68
DFP-80
OptionslRemarks:
DYes
DNo
DEPROM
DZTATTM
Operating
Temperature
D
Remask
DYes
Must Specify: Customer Programmed Start Address
Customer Programmed Stop Address
Standard D
o
J (-40· C to +85·C) version if offered
No
Previous Hitachi PIN
(2) OPERATING CHARACTERISTICS (Fill in blank space or check appropriate box
LSI
Ambient
Temperature
LSI
Ambient
Humidity
Typical
Power On
Duration
Typical
Range
Typical
Range
Power
Maximum Applied Supply
Voltage To LSI
1/0
·C-
·C Target Level
Of Reliability
·C
0
0
% Acceptable Electrical
Quality
Major
%% Level
Visual
Hours/Day LSI Operating Speed
(Specify MHz or KHz)
Remarks:
Max.
V
Max.
m.)
D(
)
0.25% D (
)
D.0.65% D (
)
1000 Fit
500 Fit
D
V
(3) ELECTRICAL CHARACTERISTICS (Fill in blank space or check appropriate box [KJ.)
D
Purchasing Specifications
D
Hitachi's Standard Specifications
Refer To Data Sheet:
( For Hitachi Use Only)
(4) CUSTOMER APPROVAL
(5) ROM CODE VERIFICATION
Customer Namec....-_ _ _ _ _.....;.._ _ _-.-,;_ __
PO# ________________________________
LSI Type No.
Approved By (print) _ _ _ _ _ _ _ _ _ _ _ __
Shipping Date of
ROM To Customer
Approved By (signature)_--'-_ _ _ _ _ _ _ __
Date
514
~HITACHI
Approved Date of
ROM From Customer
HD6301/HD6303 SERIES HANDBOOK
Section Six
HD6301YO/
HD6303Y/HD63701YO
User s Manual
'
~..••
. I
,
9
~HUIlACHU
515
Section 6
HD6301 YO/HD6303YIHD63701 YO User's Manual
Table of Contents
Page
1.
OVERVIEW....................................................
519
1.1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
519
1.2
Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
520
1.3
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
523
INTERNAL ARCHITECTURE AND OPERATION. . . . . . . . . . . . . . . . . . . . . ..
526
2.1
Operation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
526
2.2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
527
2.3
Function Pin Description ...................................... ,
528
2.4
Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
531
2.5
RAM/Port 5 Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
543
2.6
Port 6 Control/Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
546
CPU FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
548
3.1
CPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
548
3.2
Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
549
3.3
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
551
3.4
CPU Instruction Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
557
3.5
Low Power Dissipation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
559
3.6
Trap Function ................... " . . . . . . . . . . . . . . . . . . . . . . . . . ..
562
3.7
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
563
3.8
Interrupts .................................................. ,
564
TIMER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
567
4.1
Free-Running Counter (FRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
568
4.2
Output Compare Registers (OCR) ......... . . . . . . . . . . . . . . . . . . . . ..
568
4.3
Input Compare Register (ICR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
569
4.4
Timer Control/Status Register 1 (TCSR1) ......................... ,
569
4.5
Timer Control/Status Register 2 (TCSR2). . . . . . . . . . . . . . . . . . . . . . . . ..
570
4.6
Timer Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
572
4.7
Precautions on Cleaning the OCF .............................. ,
572
TIMER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
574
5.1
Timer 2 Upcounter (T2CNT) ................................... ,
574
5.2
Timer Constant Register (TCONR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
575
2.
3.
4.
5.
~HITACHI
516
5.3
Timer Control/Status Register 3 (TCSR3). . . . . . . . . . . . . . . . . . . . . . . . ..
575
5.4
Timer Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
576
5.5
Precaution for Toggle Pulse Function of
HD6301YO/HD6303Y/HD63701YO Timer 2 .. . . . . . . . . . . . . . . . . . . . . ..
577
SERIAL COMMUNICATIONS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . ..
578
6.1
Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
578
6.2
Asynchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
579
6.3
Clock Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
580
6.4
Transmit/Receive Control Status Register (TRCSR) ................ "
582
6.5
Transmit Rate/Mode Control Register (RMCR). . . . . . . . . . . . . . . . . . . . ..
583
6.6
SCI Receiving Margin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
586
6.7
SCI Status Flags .........................'. . . . . . . . . . . . . . . . . . ..
587
6.8
Precaution for Clock-Synchronous Serial Communication Interface. . . . .
588
HD63701YOProgrammabie ROM (EPROM). . . . . . . . . . . . . . . . . . . . . . . . . . .
589
7.1
Programming and Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
590
7.2
Erasing (Window Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
591
7.3
Characteristics and Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
591
APPLICATIONS.................................................
593
HD6301YO in Expanded Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
593
6.
7.
8.
8.1
8.2
HD6301YO in Single-Chip Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
594
8.3
Timer Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
594
8.4
SCI Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
598
8.5
Lowering Operating Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
600
8.6
Memory Ready Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
603
8.7
Halt Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
604
8.8
RD, WR Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
605
8.9
LCD-II Interface Application '" . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . .
605
8.10
Oscillation Circuit Board Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
606
APPENDIX I. ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . ..
608
APPENDIX II. INSTRUCTION EXECUTION CYCLES . . . . . . . . . . . . . . . . . . . . . .
630
~H8TACHI
517
APPENDIX III. QUESTIONS AND ANSWERS . . . . . . . . . . . . . . . . . . . . . . . . . . ..
636
II 1.1
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
636
111.2
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
639
111.3
Timer/Counter..................... . . . . . . . . . . . . . . . . . . . . . . . . . .
644
111.4
Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .647
111.5
Interrupt Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
650
111.6
Oscillation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
653
111.7
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
653
111.8
Low Power Dissipation Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
657
111.9
Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
660
111.10 Others.....................................................
661
APPENDIX IV. THE DIFFERENCES BETWEEN HD63701YO AND HD6301YO...
663
APPENDIX V. PROGRAM DEVELOPMENT PROCEDURE AND
SUPPORT SYSTEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
664
V.2
Single Chip Microcomputer ROM Ordering Procedure. . . . . . . . . . . . . . .
666
~HITACHI
518
664
Section 1. Overview
The HD6301YO, HD6303Y, and HD63701YO are high-performance CMOS, 8-bit, single-chip
microcomputer units (MCUs) which are object-code compatible with the HD6301V.
In addition to the CPU, these MPUs contain 256 bytes of RMA, a 16-bit 4-function timer, an
8-bit reloadable timer, a serial communications interface (SCI), and 53 parallel lines. The
HD6301YO has 16k bytes of masked ROM. The HD6303Y has no ROM. The HD63701YO
has 16k bytes of EPROM. The MPU's halt and memory ready functions enable them to
release external buses and perform low-speed external memory access.
The HD63701YO's programmable ROM is programmed by the same method as the standard
27256 EPROM. It is available in ceramic packages. The ceramic package with window is
erasable for use in the debugging development stage.
1.1 Features
The HD6301YO, HD6303Y, and HD63701YO provide the following features.
o Instruction set compatible with the HD6301V1
o On-board ROM
-16k bytes programmable (HD63701YO)
-16k bytes masked (HD6301YO)
o 256 bytes RAM
o 53 parallel I/O lines
-48 commori I/O lines (ports 1, 2, 3, 4, 5, 6)
-5 output only lines (port 7)
o Darlington transistor direct drive lines (ports 2 and 6)
o 16-bit programmable timer
-1 input capture register
-1 free-running counter
-2 output compare register
o 8-bit reloadable counter
-External event counter
-Square-wave generator
-2 output compare registers
o Serial communications interface (SCI)
-Asynchronous mode/clocked synchronous mode
-3 transmit formats (asynchronous mode)
-6 clock sources
o Memory-ready function for low-speed memory access
• Halt function
o Error detection function (address trap, opcode trap)
o Interrupts
-3 external
-7 internal
• MCU operation modes
-Mode 1: expanded mode (internal ROM inhibited)
-Mode 2: expanded mode (internal ROM valid)
-Mode 3: single-chip mode
• Address space up to 65k bytes
.. Low power modes
-Sleep mode
-Standby mode
• Minimum instruction time O.33JL (f = 3.0MHz)
• Wide operating range
-Vee = 3 to 5.5V (f = 0.1 to O.5MHz)
-Vee = 5V ±10%: HD6301Y0 (f=O.1 to 1.0MHz)
HD63A01Y0 (f=O.1 to 1.5MHz)
HD63B01YO (f=O.1 to 2.0MHz)
HD63C01Y0 (f=O.1 to 3.0MHz)
I
~HITACHI
519
1.2 Block Diagrams
Figures 1-1, 1-2, and 1-3, are block diagrams for HD6301YO, HD6303Y, and HD63701YO,
respectively.
N
VSS~
P2olnn)
...J
P2tlTout1 )
X
_
N
a:
I-
0
0
0
N
a:
0..
" 15"
~
+ +
RD /P7o
WR /P7,
RNV/P7,
LlR /P7,
BA /P74
CPu
w ~
89:)9:)9:::;
doa:
I
"a:l-
j~
0..
A
0
0..
V
P2,(TCLK)
l4
f4f4-
0..0
I------'
'-~
f
SCI
:1
0
1
'"a:
I-
P5.(iS)
0
0..
--"
CD
III:
0
0..
f4f4-
I---f4:---
- f--
"
It
I
1~7
Ao/Plo
A,/P1,
A,/Ph
A,/P13
,--I---
r--
A4/P14
As/Pls
A6/Pl.
A,/Ph
r--
Aa/P4o
I---
A./P4,
AlO/P4,
A,,/P4,
~
HAND
SHAKE
CONTROL
I---
Do/P3o
D,/P3,
D,fP3,
D,/P3,
D4/ P34
Ds/P3s
D6/P36
D,/P3,
~
0
~m
"c'"
"C:::>
«m
P5.(lRQ,)
P5,(lRO,)
P5,(MR)
P5,(HALTI
A.
As
A.
A,
A.
P5.(iS)
P5s(OS)
P5.
P5,
.
",:!:
A.
A, •
'" :::>
Au
"c'"
"C:::>
A"
~m
«m
P6.
P6,
P6,
P6,
P6.
P6s
P6.
P6,
A.
A,
A,
A,
A"
A,.
A15
ce
n.
RAM
256 Bytes
Figure 1-2. HD6303Y Block Diagram
~HBTACHI
521
~
~ ~ I~ I~I~
Vccvss~
r
VSS-
1!
X
P2dToutl )
P22(SCLK)
P23(Rx)
P24(Tx)
P2s(Tout2)
P2.(Tout3)
a::
N
-
a
a
N
a.
f-
a::
0
a.
HITACHI
524
Table 1-1. -Pin Functions (continued)
Pin No.
Mode 3
Mode 1, Mode 2
Pin
DP·64S FP-64 FP-64ACP·68 Name
25
Function
Pin
Name
Function
Port 6, bits 0-7
P60
Pori 6, bits 0-7
18
17
27
P60
26
19
18
28
P61
P61
27
20
19
29
P62
P62
28
21
20
30
29
22
21
31
30
23
22
32
P65
P65
31
24
23
33
P66
P66
32
25
24
34
33
26
25
36
Vcc
+ 5V power supply
34
27
26
37
A15
Address bus,
bits 15-8
35
28
27
38
36
29
28
39
Vcc
+ 5V
power supply VCC
Port 4, bits 7-0
P46
Function
+ 5 V power supply
_C_E_ _ _ _ _C_h...:ip_e_n_a_b_le_ _ __
EA 14
P45
A13
PROM Mode
Pin
Name
Address bus.
-::-EA,...1.:.:3,-_ _ bits 14-10
EA12
37
30
29
40
A12
38
31
30
41
All
39
32
31
42
AlO
P42
40
33
32
43
A9
P41
DE
Output enable
41
34
33
44
A8
P40
EA8
Address bus.
42
35
34
45
Vss
Vss
Ground
43
36
35
46
44
37
36
47
A6
45
38
37
48
A5
46
39
38
49
47
40
39
50
48
41
40
49
42
41
50
43
42
53
51
44
43
55
Ground
Vss
Ground
Address bus,
bits 7-0
P17
Pori 1. bits 7-0
P16
_E:-A,...7-,-_ _ Address bus, 8 bit
_E_A...;6:.-_ _ bits 7-0
P15
EA5
51
P12
EA2
52
Pll
AO
P10
Data bus,
bits 7-0
EAO
Port 3, bits 7-0
_E-,0:-7-,-__ 0 ata bus,
52
45
44
56
D6
53
46
45
57
D5
P35
E05
54
47
46
58
P32
E02
P30
EOo
55
48
47
59
56
49
48
60
D2
57
50
49
61
01
58
51
50
62
DO
_E__0_6::.....___ bits 7-0
P36
EOl
59
52
51
63
BA
Bus available output
60
53
52
64
LlR
Load instruction
register output
61
54
53
65
R/W
Read/Write output
62
55
54
66
WR
Write output
63
56
55
67
RD
Read output
P70
64
57
56
68
E
External
clock output ~
E
Pori 7, bits 4-0
External
clock output
~HITACHI
525
Section 2. Internal Architecture and Operation
2.1 Operation Modes
The HD6301YO and HD63701YO operate in three MCU modes. The HD6303Y only operates in
MCU mode 1. The mode program pins MPo and MP 1 , and the STBY pin select the mode (table 2-1).
• MCU 1 (expanded): external memory access enabled, internal ROM disabled
• MCU 2 (expanded): external memory access enabled, internal ROM enabled
• MCU 3 (single-chip): external memory access disabled
Table
~-1.
Mode Selection
MP 1
MPo
STBY
ROM
RAM
Interrupt Vector
Operation Mode
Low
High
X
External
Internal
External
MCU 1 (expanded)
High
Low
X
Internal
Internal
Internal
MCU 2 (expanded)
High
High
X
Internal
Internal
Internal
MCU 3 (single-chip)
Note: X = Don't care
2.1.1 MCU Mode 1 (Expanded)
In MCU mode 1, port 3 is the data bus, port 1 is the lower address bus, and port 4 is the upper
address bus. They can directly interface with HD6800 buses. Port 7 supplies signals such as RIW.
See table 2-2. In mode 1, the ROM is disabled and the external address space is 65k bytes (figure
2-1). Since the HD6303Y has no internal ROM, it only operates in mode 1.
~AD
~WR
A/Vii
RES-"
SfBY
NMIPort 2
8 I/O lines
Timer 1,2 SCI
PortS
81/0 line<;
IRQ"
iRili
MR. HALT is, OS
Port 6
lines
8
va
DR
BA
Port 3
B Data Bus
Port 1
8 Address Bus
Port 4
8 Address Bus
Figure 2-1. MCU Mode 1
2.1.2 MCU Mode 2 (Expanded)
MCU mode 2 is the same as mode 1, except that the ROM is enabled. The external address space
is 48k bytes (figure 2-2).
I"ili
WR
R/W
RES
S'f8Y
NMI
Pori 2
a 1/0 Lines
Timer 1, 2 SCI
Port 5
a I/O Lines
IRQ" IAQ 1 MA,HALT
1S,05
DR
BA
Pori 3
8 Dala Bus
Port!
B Address Bus
Pori 4
B Address Bus
Figure 2-2. MCU Mode 2
~HITACHI
526
2.1.3 MCU Mode 3 (Single-Chip)
In MCU mode 3, all ports are 110 ports. There is no interface to external buses (figure 2-3).
Port 7
5 Output Lines
JI£ll
STliV
Pori 3
NMI
a I/D lines
Port 2
B I/O Lines
Timer I, 2 SCI
Port 5
6 Input Lines
Port 1
8 Output Lines
nm;,1Allj MR, HAU
Ill. OS
Pori 4
Pori 6
8 Output Lines
B 110 Lines
Figure 2-3. MCU Mode 3
Table 2-2. Port Signals
Port
MCU Mode 1
MCU Mode 2
MCU Mode 3
1
Address bus (Ao-A7)
Address bus (Ao-A7)
110 port
2
110 port
110 port
110 port
3
Data bus (D7"Do)
Data bus (D7"Do)
110 port
4
Address bus (Aa-A15)
Address bus (Aa-A15)
110 port
5
I/O port
110 port
110 port
6
110 port
110 port
110 port
7
R'D,
RD, WR, RIW, LlR, BA
Output port
WR, RIW, LlR, BA
2.2 Memory Map
The HD6301Y0, HD6303Y, and HD63701Y0 can access up to 65k bytes of external memory,
depending on the operating mode. Figure 2-4 shows a memory map for each mode. The first 40
locations oj each map, from $00 to $27, are reserved for the MCU's internal register area (table 2-3).
MCU Mode
expanded Mode
Expanded Mode
Model
Inlerna'$0027
f"''''''''='1<
$0000
Inlernal-
$0027
External
$0040
Memory
Space
Register
Register
External
Memory
Space
Single-chip Mode
Register
$0027
Internal
RAM
RAM
$013F
1'"'''"'''''"''1
Mode 3
$ O O O O _ } Inlernal
Internal
Internal
RAM
S013F
Mode 2
$013F
External
Memory
Space
External
Memory
Space
Internal
ROM
Internal
ROM
SFFFF ' - -_ _JJ
• Excludes the following addresses
which may be used externally:
• Excludes the following addresses
which may be used exlemally:
$00. $02. $04. $05, $06. $07. $18.
$00. $02, $04. $06, $07, $18.
Figure 2-4. Memory Maps
~HITACHI
527
Table 2-3. Internal Register Area
Address
Register
R/W
00
Port 1 data direction register
W
$FE
01
Port 2 data direction register
W
$00
State at RESET
02
Port 1
R/W
Undefined
03
Port 2
RIW
Undefined
04
Port 3 data direction register
W
$FE
05
Port 4 data direction register
W
$00
06
Port 3
RIW
Undefined
07
Port 4
RIW
Undefined
08
Timing control/status register 1
R/W
$00
09
Free-running counter (upper byte)
RIW
$00
OA
Free-running counter (lower byte)
RIW
$00
OB
Output compare register 1 (upper byte)
R/W
$FF
OC
Output compare register 1 (lower byte)
RIW
$FF
00
Input capture register (upper byte)
R
$00
OE
Input capture register (lower byte)
R
$00
OF
Timer control/status register 2
RIW
$10
10
Rate, mode control register
RIW
$CO
11
Tx/Rx control status register 1
RIW
$20
12
Receive data register
R
$00
13
Transmit data register
W
$00
14
RAM/port 5 control register
RIW
$F8 or $78
15
Port 5
R
Undefined
16
Port 6 data direction register
W
$00
17
Port 6
R/W
Undefined
18
Port 7
RIW
Undefined
19
Output capture register 2 (upper byte)
R/W
$FF
1A
Output capture register 2 (lower byte)
RIW
$FF
1B
Timer control/status register 3
RIW
$20
1C
Timer constant register
W
$FF
10
Timer 2 upcounter
RIW
$00
1E
Tx/Rx control status register 2
RIW
$28
1F
Test register
20
Port 5 data direction register
W
$00
21
Port 6 control/status register
RIW
$07
2.3 Functional Pin Description
2.3.1 Power (Vcc, V ss)
Vce, V 55 are the power supply pins. Apply + 5V ± 10% to Vee. Tie V5S to ground.
2.3.2 Clock (XTAL, EXTAL)
XTAL and EXTAL connect to an AT-cut parallel resonant crystal. The chip has a divide-by-four
circuit. For example, if a 4 MHz crystal. i5 used, the system clock will be 1 MHz.
528
~HITACHI
Figure 2-5 is an example of the crystal oscillator connection. The crystal and CL1 and C L2 should be
located as close as possible to the XTAL and EXTAL pins. No line must cross the lines between the
crystal oscillator and the XTAL and EXTAL pins.
The EXTAL pin can be driven by an external clock with a 45% to 55% duty cycle. The LSI divides
the external clock frequency by four. The external clock should therefore be less than four times the
maximum clock frequency. When using an external clock, the XTAL pin should be left open.
AT Cut Parallel Resonant Crystal Oscillator
Co=7 pF max
Rs=BO II max
Cl1 =C L2
= 10 pF-22 pF±20%
(3.2-12 MHz)
EXTAL
(a) Crystal Interface
XTAL~N.C.
EXT AL
t---<
External Clock
(b) External Clock
Figure 2-5. Recommended Crystal Oscillator Connection
2.3.3 Standby (STBV)
The STBV pin puts the MCU in standby mode. When STBV is low, the oscillation stops, and the
internal clock is stabilized to put the MCU in a reset condition. To retain the contents of RAM during
standby, write 0 to the RAM enable bit (RAM E). RAME is bit 6 of the RAM/port 5 control register at
address $0014. RAM is disabled, and its contents are sustained. Refer to 3.5 Low Power Dissipation
Mode for details on the standby mode.
2.3.4 Reset (RES)
This pin resets the MCU's internal state and provides a startup procedure. The RES input must be
held low for at least 20 ms during power·on.
The CPU registers accumulator, index register, stack pointer, condition code register except for
mask bit, RAM, and the data registers of the ports are not initialized during reset, so their contents
are undefined.
2.3.5 External Clock (E)
E provides a TTL·compatible system clock to external circuits. Its frequency is one-fourth that of the
crystal oscillator or external clock. E can drive one TTL load and 90 pF.
2.3.6 Nonmaskable Interrupt (NMI)
When CPU detects a falling edge at the NMI input, it begins the internal nonmaskable interrupt
sequence. The instruction being executed when the NMI is detected will proceed to completion.
The interrupt mask bit of the condition code register does not affect the nonmaskable interrupt.
In response to an NMI interrupt, the contents of the program counter, index register, accumulators,
and condition code register will be saved onto the stack. After they are saved, a vector is fetched
from $FFFC and $FFFD to the program counter, and the nonmaskable interrupt service routine
starts.
Note: After reset, the stack pOinter should be initialized to an appropriate memory location before
any NMI input.
2.3.7 Interrupt Requests (IRQ1' IRQ2)
The interrupt requests are level-sensitive inputs which request an internal interrupt sequence from
the CPU.
eH1TACHI
529
I
2.3.8 Mode Program (MP o• MP 1)
These pins determine the operation mode. Refer to 2.1 Operation Mode for details.
Note: The following signals RD, WR, R/W, L1R, MR, HALT, and BA, are only used in modes 1 and 2.
2,3.9 Read/Write (R/W; P72 )
The read/write signal shows whether the MCU is in read (R/W high) or write (R/W low) state to the
peripheral or memory devices. It is usually high, in read state. RIW can drive one TTL load and 30
pF.
2.3.10 Read and Write (RD; P70 ' WR; P7 1)
The read and write outputs show active low outputs to peripherals or memories when the CPU is
reading or writing. This enables the CPU to access LSI peripherals with RD and WR inputs easily.
These pins can drive one TTL load and 30 pF.
2.3.11 Load Instruction Register (LlR; P73)
The L1R output low shows that the instruction opcode is on the data bus. L1R can drive one TTL
load and 30 pF.
2.3.12 Memory Ready (MR; P5 2 )
The memory ready control input lengthens the system clock's high period to allow access to
low-speed memory. When MR is high, the system clock operates normally. But when MR is low, the
high period will be lengthened depending on its low time in integral multiples of its cycle time. It
can be lengthened up to 9 ""s.
During internal address or invalid memory access, MR is prohibited internally from decreasing
operation speed. Even in the halt state, MR can lengthen the high period of the system clock to
allow peripheral devices to access low-speed memories. MR is also used as P5 2 . The function is
chosen by the enable bit in the RAM/port 5 control register (bit 2) at $0014. See 2.5 RAM/Port 5
Control Register for details.
2.3.13 Halt (HALT; P5 3)
The halt control input stops instruction execution and releases the buses. When HALT switches low,
the CPU finishes the current instruction, then stops and enters the halt state. When entering the
halt state, the CPU sets BA (P74 ) high, and sets the address bus, data bus, RD, WR, and R/W to
high impedance. When an interrupt occurs in the halt state, the CPU cancels the halt, and executes
the interrupt service routine.
Note: When the CPU is in the interrupt wait state, executing the WAI instruction, HALT should be
held high. If halt turns low, the CPU may fetch the incorrect vector after releasing the halt state
(figure 2-6). If a halt is expected, a loop should be used instead of WAI (figure 2-7).
•
•
·
"RAI.T input
WAr
Waiting
interrupt
:::
~
(Accept interrupt)
(
Incorrect Vector (MSB)
Fetch Vectors
Incorrect Vector (LSB)
Opcode Fetch
•
•
• Execute interrupt routine
·
• Branch destination undetined (CPU burst)
Figure 2:6 HALT WAI
530
~HITACHI
•
•
•
•
CLI
BRA
LOOP
CLI
WAI
LOOP
•
•
•
•
•
•
Error Occurs
Recommended Example
Figure 2-7. Branch Replacement for WAI
2.3.14 Bus Available (BA; P74)
The bus available output control signal goes high when the CPU accepts HALT and releases the
buses. It is normally low. The HD6800 and HD6802 bring BA high and release the buses at WAI
execution, but the HD6301YO, HD6303Y, and HD63701YO, don't. But if HALT goes low when the
CPU is in the interrupt wait state after having executed a WAI, the CPU sets BA high and releases
the buses. When HALT goes high, the CPU returns to the interrupt wait state.
2.4 Ports
I
The HD6301YO, HD6303Y, and HD63701YO provides seven ports (six 8-bit ports and a 5-bit port).
Some pins have other uses, as shown in table 2-2. Table 2-4 shows the addresses of the ports and
their data direction registers. Figure 2-9 shows block diagrams of each port. Table 2-5 shows the
state of each port at reset.
Table 2-4. Port and Data Direction Register Address
Port
Port Address
Data Direction Register
$0002
$0000
2
$0003
$0001
3
$0006
$0004
4
$0007
$0005
5
$0015
$0020
6
$0017
$0016
7
$0018
~HITACHI
531
Table 2-5. Port at Reset (Modes 1 and 2)
Port
State at Reset
High
2
High impedance
High impedance
High (Mode 1 only)
5
High impedance
6
High impedance
7
RD, WR, RIW, LlR = High
BA = Low
Note: Port 4 is high impedance in Mode 2.
All ports are high impedance after reset in Mode 3.
2.4.1 Port 1
Port 1 is an 8-bit I/O port (figure 2-8). The LSB of the DDR ($0000) selects the data direction
of the whole port(figure 2-9). In the expanded modes (1 and 2) port 1 is the lower address bus
(A7-AO). Port 1 can drive one TTL load and 90 pF capacitance.
WPID
s ••C
Mode 1
Mode2
R
RES
D
Q
P1 DDR·
!!l
'"
Dt--+--~ ~
o
Q
P1n Data
Mode 2
C
---L-
WPI
(ij
E
.'!l
.E
RES
WPI D
WPI
RPI
RPI
-L
* a-bit
Common Register
* *Priority: Set > reset
Figure 2-8. Port 1 Block Diagram
~HITACHI
532
Reset Signal
DDR Write Signal
Port Write Signal
Port Read Signal
LSB
MSB
1
1
1
1
1
1 PI> 1 ,,·1 ,,·1 ,,·1
1
Ph
1
1
;~R 1
1 '" 1 '" 1 "0 1
Pl DDR ($0000)
(Write only, bit 0
is cleared during
reset.)
PORT! ($0002)
(R/W, not initialized during
reset.)
Figure 2-9, Port 1 Register and Data Direction Register
2.4.2 Port 2
Port 2 is an 8-bit 1/0 port (figure 2-10), Each bit of the DDR ($0001) defines the data direction
of the corresponding bit of port 2 (figure 2-11). Port 2 can drive one TTL load and 30 pF
capacitance, It can produce 1 rnA when VOUT
=
1.5 V to directly drive the base of a
Darlington transistor.
Port 2 pins are also used as 1/0 pins by timers 1, 2, and the SCI (table 2-6). The pin functions
are controlled by registers in timers 1, 2, and the SCI.
~HITACHI
533
RES
R
Q
0
P20DDR
C
"'"
WP2D
ED
..
B
Q
.~
C
0
P20 Data
.5
C
WP2
RP2
WP2D: DDR Write Signal
WP2: Port Write Signal
RP2: Port Read Signal
....L
Tomer 1
Input Capture Input
P2o/Tin
R
0
Q
P2.DDR
C
WP2D
Q
0
SCI, Tomer 1, Tomer 2
P2. Data
C
WP2
r--------I
I
I
I
1-1-----------+----'L--- Output Data
Output Enable Signal
WP2D: DDR Write Signal
WP2 : Port Write Signal
RP2 : Port Read Signal
P2,/Toutl, P24/Tx, P2,/Tout2, P2./Tout3
Figure 2-10, Port 2 Block Diagram
~HITACHI
534
RES
P2, DDR
C
WP2D
r---,r-...._-r-r--.
D t----j--i
Q
SCI
..----------
P2, Data
C
WP2
'--j------,----Clock Input Enable
Signal
'L-f------------+-----;---- Output Clock
----------+-----t---- Clock Output Enable
L -.....
Signal
RP2
r-~-~-Input
--L
Clock
WP2D: DDR Write Signal
WP2: Port Write Signal
RP2: Port Read Signal
P2,/SCLK
RES
Rl
I
R2
o I----!---;
r-------------~Q
00
~
CD
P2" DDR
C
~
o
WP2D
"iii
1------------1 Q
E
0
1------1--;
~
SCI, Timer 2
,----------
P2" Data
C
WP2
I
I
I
L-l------7---- Input Enable signal
r-+---e~SCI
Receive Data,
Timer 2 External Clock
WP2D: DDR Write Signal
WP2: Port Write Signal
RP2: Port Read Signal
P2,/Rx, P2,/TCLK
Figure 2-10. Port 2 Block Diagram (Cont)
~HITACHI
535
P2DDR ($0001)
(Write only, $00
during reset.)
P27
P26
P25
P24
P23
P22
P21
P20
PORT2 ($0003)
(R/W, not initialized
during reset.)
Figure 2-11. Port 2 Register and Data Direction Register
Table 2-6. Port 2 Pin Functions
Port 2 Pin
Alternate Function
Description
P20
Tin
Timer 1 input
P21
Tout1
Timer 1 output 1
P22
SCLK
SCI clock
P23
Rx
SCI receive input
P24
Tx
SCI transmit output
P25
Tout2
Timer 1 output 2
P26
Tout3
Timer 2 output 3
P27
TCLK
Timer 2 clock
~HITACHI
536
2.4.3 Port 3
Port 3 is an 8-bit 1/0 port (figure 2-12). The LSB of the DDR ($0004) selects the data direction
of the whole port (figure 2-13). In the expanded modes (1 and 2) port 3 is the lower data bus
(D7-DO). Port 3 can drive one TTL load and 90 pF capacitance.
WP3D
RES
D
Mode3
Mode 1
Mode 2
DI-4---4
P3" Data
e
Mode 1
More 2
WP3
WP3D: DDR Write Signal
WP3: Port Write Signal
RP3: Port Read Signal
* a-Bit Common
Register
Figure 2-12. Port 3 Block Diagram
MSB
LSB
P3DDR ($0004)
(Write only. bit 0
is cleared during
reset.)
I I I I I I I I;;, I
I~I~I~I~I~I~I~I~I
PORT3 ($0006)
(R/W. not ini·
tialized during
reset.)
Figure 2-13. Port 3 Register and Data Direction Register
~HITACHI
537
2.4.4 Port 4
Port 4 is an a-bit I/O port (figure 2-14). Each bit of the DDR ($0005) defines the data direction
of the corresponding bit of port 4 (figure 2-15). In the expanded modes (1 and 2), port 4 is the
upper address bus (A15-Aa). In mode 1 (expanded mode with no external ROM), the DDR is
set automatically and port 4 outputs addresses. In mode 2 (expanded mode with external
ROM), the DDR must be set to 1 for port 4 to function as the address bus. Pins that are not
needed for the address bus can be used as input pins. Port 4 can drive one TTL load and 90
pF capacitance.
Model
RES
S·
R
0
Q
!!
ID
P4, DDR
;
]
c
0
WP4D
Mode3
~
-LQ
"
::!
~
"0
"0
<{
'1ii
E
~
0
.E
P4, Data
~
0.
0.
C
Mode 1
Mode2
en
ID
::>
WP4
-LRP4
---L
WP4D: DDR Write Signal
WP4: Port Write Signal
RP4: Port Read Signal
* Priority: set> reset
Figure 2-14. Port 4 Block Diagram
P4DDR ($0005)
(Write only, $00
during reset.)
P46
P45
P44
P40
PORT4 ($0007)
(R/W, not initialized
during reset.)
Figure 2-15. Port 4 Register and Data Direction Register
~HITACHI
538
2.4.5 Port 5
Port 5 is an 8-bit I/O port (figure 2-16). Each bit of the DDR ($0020) defines the data direction of the
corresponding bit of port 5 (figure 2-21). Port 5 can drive one TTL load and 30 pF capacitance.
P5s-P5 0 are also used as control pins (table 2-7). The function of these pins is determined by the
RAM/port 5 control register (RP5CR), except for P5 4/IS and P5s/0S, which are controlled by the
port 6 control/status register (P6CSR).
P55-P50 are also used as control pins (table 2-7). The function of these pins is determined by
the RAM/port 5 control register (RP5CR), except for P541IS and P55/0S, which are controlled
by the port 6 control/status register (P6CSR).
RES
R,
R2
Q
D
P5. DDR
C
WP5D
Q
WP5D: DDR Write Signal
WP5: Port Write Signal
RP5: Port Read Signal
D
P5. Data
C
RP5
*
WP5
RAM/Port
5 Control
-L-
Register
IRQ,
)--_ _ _... IRa.
~
__________-+____
~~/
MR
HALT
*Value after reset;
IRQ' E=O. IRQ2E=O. MRE=O". HLTE='"
* * P52 and P5, can be used as I/O ports
in spite of the value of this register in Mode 3.
P5o!lmIi. P51/'Ilm2. P52/MR. P5,/HALT
RES
R
.-------10
0/----+
P5. DDR
C
WP50
~
/-----10
Dr---~ iij
0
P5. Data
E
~
C
WP5D: DDR Write Signal
WP5: Port Write Signal
RP5: Port Read Signal
WP5
>---,'"::s--------+---- Port 6 Control Status Register
P5./fS
Figure 2-16. Port 5 Block Diagram
~IHIHTACHO
539
RES
!
P5.DDR
C
III
..
S
WP5D: DDR Write Signal
WP5: Port Write Signal
RP5: Port Read Signal
C
WP5D
Q
0
P5. Data
co
E
l!l
.5
Port 6 Control/Status Registar
r--------I
C
WP5
I
I
OS
aSE
RP5
C0::OS
OS output
)
output disable
-L-
P5.IOS
RES
R
Q
0
P5,DDR
C
WP5D
Q
0
P5, Data
C
!
III
..
S
c
co
E
l!l
.5
WP5
RP5
~
P5"
P5,
Figure 2-16, Port 5 Block Diagram (Cont)
~HITACHI
540
WP5D: DDR Write Signal
WP5 : Port Write Signal
RP5: Port Read Signal
2.4.6 Port 6
Port 6 is an 8-bit 1/0 port (figure 2-17). Each bit of the DDR ($0016) defines the data direction
of the corresponding. bit of port 6 (figure 2-18). Port 5 can drive one TTL load and 30 pF
capacitance. In addition, it can drive the base of Darlington transistors directly.
Port 6 can function as a parallel handshake interface under the control of the port 6 controll
status register (P6CSR: $0021). Port 6 has a data latch for input data (is LATCH).
RES
R
r-------l0
0 1 - - - -.. !g
P6,OOR
CD
C
~
o
WP60
m
E
/------10
0 / - - - -...
P6, Data
C
WP6
RP6
RES
o
~
WP6D: DDR Write Signal
WP6: Port Write Signal
RP6: Port Read Signal
-L
R
0
IS Latch
C
Port 6
L.--------------Control/Status Register
I
Figure 2-17. Port 6 Block Diagram
P60DR ($0016)
(Write only, $00
during reset.)
I I I I ,~ I I I I I
P6,
eG,
eG,
P6,
P6,
P6,
P6,
PORT6 ($0017)
(R/W, not ini·
tialized during
reset.)
Figure 2-18. Port 6 Register and Data Direction Register
~HITACHI
541
2.4.7 Port 7
Port 7 is a 5-bit output only port (figures 2-19, 2-20). In the expanded modes (1 and 2), port 7
outputs control signals from the CPU. Port 7 goes to high-impedance state during reset. Port 7
can drive one TTL load and 30 pF capacitance.
RE5
R
WP7
5,
Mode 1. Mode 2
Q
52
!!I
Mode 3
III
----L-
0 1----+---+
Q
P7, Data
;
..
c
E
~
C
WP7
RP7
WP7: Pon Write Signal
RP7: Pon Read Signal
--L
Mode 1
Mode 2
---L
' - - - - - - - - - - - - - / - + - - - ~rs~fontrol
• Priority: S2>R.
5,
Figure 2-19. Port 7 Block Diagram
MSB
LSB
P70
Figure 2-20. Port 7 Register
~HITACHI
542
PORT7: $0018
(R/W. not deter·
mined during rese!.)
2.5 RAM/Port 5 Control Register
The RAM port 5 control register (RP5CR:$0014) controls onchip RAM and port 5 (figure 2-22).
2.5.1 IRQ1 E, IRQ2E
Setting IRQ1 E and IRQ2E to 1 selects P50 and P51 as the IRQ1 and IRQ2 interrupt inputs.
These bits are cleared at reset.
2.5.2 MRE, AMRE
When MRE or AMRE is set to 1. P52 becomes the MR input. When both are 0, memory ready
is inhibited (table 2-8). In mode 3, memory ready is always inhibited, regardless of these bits.
MRE is cleared at reset. AMRE is set to 1.
2.5.3 HLTE
When HLTE is set to 1, P53 becomes the HALT input. When 0, HALT is inhibited. In mode 3,
HALT is always inhibited, regardless of HLTE. This bit is set to 1 at reset.
2.5.4 STBY FLAG
Clearing STBY FLAG by software puts the MCU into standby mode. This flag is set to 1 at
reset, so reset cancels the standby mode. If the STBY pin is low, this flag cannot be cleared.
2.5.5 RAME
When RAME is set to 1, on-chip RAM is enabled. When 0, it is disabled. RAME is set to 1 at
reset. This bit should be set to
a before going into standby state to protect on-chip RAM data.
2.5.6 STBY PWR
When Vcc is not provided in standby mode, STBY PWR is cleared. If STBY PWR is set before
the MCU goes to standby, and remains set after standby Vcc was continuously supplied, and
the contents of on-chip RAM are valid.
~HITACHR
543
MSB
LSB
P57
DDR
P5G
DDR
P55
DDR
P54
DDR
P55
P54
P53
DDR
P52
DDR
P51
DDR
P50
DDR
P5DDR ($0020)
(Write only, $00
during reset.)
P50
PORT5 ($0015)
(R/W, not initialized
during reset.)
Figure 2-21, Port 5 Register and Data Direction Register
Table 2-7. Port 5 Pin Functions
Port 5 Pin
Alternate Function
Description
P50
IRQ1
Interrupt input 1
P51
IRQ2
Interrupt input 2
P52
MR
Memory ready input
P53
HALT
Halt input
P54
IS
Input Strobe
P55
OS
Output strobe
RAM/Port 5 Control Register (RP5CR)
6
5
4
RAME
I i~:~ I
AMRE
7
~~:
I
3
I
HLTE
o
2
I
MRE
I
IR~2
I
IR~I
I
$0014
I.
IRQI Enable
0-P50 is an I/O port
I-P50 is IRQI
IRQ2 Enable
0-P51 is an I/O port
I-P51 is IRQ2
MR Enable
O-Memory ready disa bled
I-P52 is MR, memory ready function enabled
HALT Enable
0-P53 is an I/O port
I-P53 is HALT input
Auto Memory Ready Enable
O-Automatic memory ready disabled
I-P52 is MR, auto memory ready enabled
Standby Flag
O-Setting this flag to 0 puts MCU in standby mode
I-STBY FLAG is set to I by reset, releasing standby mode
RAM Enable
O-On·chip RAM disabled
I-On·chip RAM enabled
~~~f>ower
O-Vee has not been provided during standby mode
I-Vee has been provided in standby mode
Figure 2-22. RAM/Port 5 Control Register
~HITACHI
544
Table 2-8. Memory Ready Function
MRE
AMRE
Function
o
o
0
Memory ready inhibited.
Auto memory ready. When the CPU accesses the external address
regardless of MR, E clock automatically stays high one-cycle longer.
This state is retained during reset.
o
Memory ready. MR pin controls E clock high time.
When the CPU accesses the external address space with the P52 (MR)
pin low the auto memory ready operates. This function useful if there is
both high-speed memory and slow memory outside. Input CS signal of
slow memory to MR pin.
~HITACHD
545
2.6 Port 6 Control/Status Register
The port 6 control/status register (P6CSR: $0021) controls and holds the status of the port 6
handshake interface (figure 2-23). The handshake interface functions as follows.
• Latches the data input at port 6 on the falling edge of IS (P54).
• Outputs
as
(P55) when reading or writing to port 6.
• When IS FLAG is set by the falling edge of IS, an interrupt occurs (figure 2-24).
2.6.1 LATCH ENABLE
The LATCH ENABLE bit controls the port 6 input latch (IS LATCH). When it is set, the input
data at port 6 will be latched in at the falling edge of IS (P54). Reading port 6 clears the latch.
If LATCH ENABLE is 0, the input latch is disabled, and P54 acts as an ordinary I/O port.
LATCH ENABLE is cleared at reset.
2.6.20SS
When
ass
is set, writing to port 6 initiates an output strobe signal (OS/P55). When
cleared, reading port 6 initiates an
as. ass
ass
is
is cleared at reset.
2.6.30SE
When OSE is set, P55 is the output strobe,
as.
When cleared, it is a normal I/O port.
2.6.4 IS IRQ1 ENABLE
When IS IRQ1 ENABLE is set, IS FLAG set causes an IRQ1 interrupt. When cleared, IS FLAG
does not cause an interrupt. This bit is cleared during reset.
2.6.5 IS FLAG
The IS FLAG is set by the falling edge of IS. It is a read-only flag. It is cleared by reading or
writing to port 6 after reading the P6CSR. IS FLAG is cleared during reset.
Table 2-9 shows the conditions that set and reset the port 6 control/status register flags.
~HITACHI
546
o
$0021
Latch Enable
O-Port 6 latch disabled
I-Port 6 input la tched by IS
Output Strobe Select
0-05 output on port 6 read
1-05 output on port 6 write
Output Strobe Enable
0-P55 is I/O port
l-P55 is output strobe (OS)
Input Strobe Interrupt Enable
O-Interrupt on IS FLAG inhibited
l-fRQ! interrupt on IS FLAG enabled
Input Strobe Flag
O-No IS
I-IS falling edge detected
Figure 2-23. Port 6 Control/Status Register
HD63D1YO
Port 6 Control/Status Register
) - - - - - - 1 : > iAQ,
Figure 2-24. Input Strobe Interrupt Block Diagram
Table 2-9. Port 6 Control Status Register Status Flags Set and Reset Conditions
Flag
Set Condition
Clear Condition
IS FLAG
Falling edge input to P54 (IS)
Read the P6CSR then read or write the
port 6, when IS FLAG = 1
RES = 0
ICF
FRC - ICR by rising or falling
edge input to P20. (Selected by
IEDG)
Read the TCSR1 or TCSR2 then ICRH,
when ICF = 1
RES = 0
~HITACHB
547
Section 3. CPU Function
3.1 CPU Registers
The CPU has three 16-bit registers and three 8-bit registers (figure 3-1).
7
0
~ ____ ! _____
7
U_____ ~ ____
0
18-Bit Accumulators A and B
D
Or 16-Bit Double Accumulator D
15
15
I
I
I
0
0
I Index Register (X)
X
15
0
IStack Pointer (SP)
SP
15
0
I Program Counter (PC)
PC
0
7
11 11 I H II I N I Z
Iv-Tcl Condition Code Register (CCR)
~ Carry/Borrow from MSB
Over flow
Zero
Negative
Interrupt
Half Carry (From Bit 3)
Figure 3-1. CPU Registers
3.1.1 Accumulators (ACCA, ACCe, ACCD)
Two 8-bit accumulators, ACCA and ACCS, store the result of arithmetic/logic operations and data. When
combined, these make up the 16-bit accumulator ACCD used for 16-bit operations. Note that the
contents of ACCA and ACCS are destroyed by an ACCD operation.
3.1.2 Index Register (IX)
The 16-bit register IX stores 16-bit data for use in indexed addressing or for general purposes.
3.1.3 Stack Pointer (SP)
The contents of the16-bit register SP indicate the address of a stack. SP can also be used as a
general-purpose register.
3.1.4 Program Counter (PC)
The contents of the 16-bit PC indicate the address of the instruction being executed. Note that
software cannot access this register.
548
~HITACHI
3.1.5 Condition Code Register (CCR)
The CCR register consists of the carry (C), overflow (V), zero (Z), negative (N), interrupt mask (I), and
half-carry (H) bits. After an instruction is executed, the CCR bits change state depending on the result of
the operation. They can be tested by conditional branch instructions. The upper two bits of this register
are not used.
Half-Carry (H):H is set to 1 if a carry at bit 3 or bit 4 occurs during an ADD, ABA, or ADC instruction. It
is cleared if no carry occurs.
Interrupt Mask (I):When I is set to 1, it disables all maskable interrupts (IRQ1' IRQ2, and IRQ3)'
Negative (N): N is set to 1 if the MSB of the result of an operation is 1. N is cleared if it is O.
Zero (Z): Z is set to 1 if the result of an operation is zero. Z is cleared if it is not zero.
Overflow (V): V is set to 1 if the result of an operation shows a two's complement overflow. It is
cleared if there is no overflow.
Carry (C): C is set to 1 if a carry or borrow is generated from the MSB. If there is no carry or borrow, it is
cleared.
I
3.2 Addressing Modes
The HD6301YO, HD6303Y and HD63701YO instructions have seven addressing modes.
3.2.1 Accumulator Addressing (ACCX)
The instruction addresses an accumulator and ACCA or ACCB is selected. Accumulator addressing
instructions take one byte.
3.2.2 Immediate Addressing
Immediate addressing places the data in the second byte of an instruction, except LDS and LDX, which
use the second and third bytes. An immediate instruction causes the CPU to address this operand.
Immediate instructions take 2 or 3 bytes.
3.2.3 Direct Addressing
In direct addressing, the second byte of an instruction holds the address where the data is stored. 256
~HITACHI
549
bytes ($OO-$FF) can be addressed directly. Storing data in this area reduces instruction time, so
configuring $OO-$FF as user's RAM is recommended. Direct addressing instructions take 2 bytes, or 3
bytes for AIM, OIM, ElM, orTIM.
3.2.4 Extended Addressing
In extended addressing, the second byte of an instruction holds the upper eight bits of the absolute
address of the stored data, and the third byte holds the lower eight bits. Extended addressing
instructions take 3 bytes.
3.2.5 Indexed Addressing
In indexed addressing, the second byte of the instruction (third byte for AIM, OIM, ElM, or TIM
instructions) is added to the lower eight bits of the index register. The carry is added 10 the upper eight
bits of the index register, and the 16-bit sum is the memory location of the data. The modified address is
held in the temporary address register, so the index register doesn't change., Indexed addressing
instructions take 2 bytes, or 3 bytes for AIM, OIM, ElM, or TIM.
3.2.6 Implied Addressing
In implied addressing, the instruction itself specifies the address. For example, the instruction
addresses the stack pointer or index register. Implied addressing instructions take 1 byte.
3.2.7 Relative Addressing
In relative addressing, the second byte of the instruction and the lower eight bits of the program counter
are added. The carry or borrow is added to the upper eight bits of the program counter. Locations from
-126 to +129 bytes from the current location can be addressed. Relative addressing instructions take 2
bytes.
550
3.3 Instruction Set
The HD6301YO, HD6303Y, and HD63701YO are object-code upwardly compatible with the HD6801
to use all instructions of the HMCS6800. The instruction time of key instructions has been reduced
improving throughput.
3.3.1 Additional Instructions
Bit manipulation, index register and accumulator exchange, and sleep instructions have also been
added to the HD6801 instruction set. AIM, OIM, EOM, and TIM are 3 byte instructions. The first byte is
the opcode, second byte is the immediate data, and the third byte is the address modifier.
AIM: ANDs the immediate data with the memory contents and stores the result in memory. (M) AND
(IMM) -. (M).
OIM; ORs the immediate data with the memory contents and stores the result in memory. (M) OR (IMM)
-. (M).
ElM: EORs the immediate data with the memory contents and stores the result in memory. (M) EOR
(IMM) -. (M).
I
TIM: ANDs the immediate data with the memory contents and changes the related flag in the condition
code register. (M) AND (IMM).
XGDX: Exchanges the contents of the accumulator with the contents of the index register. (ACCD) .-,
(IX).
SLP: Puts the MCU into sleep mode. Refer to 3.5 Low Power Dissipation Mode for details.
3.3.2 Instruction Set Summary
Tables 3-1 to 3-5 summarize the instruction set.
Accumulator and memory manipulation instructions: table 3-1
•
Index register and stack manipulation instructions: table 3-2
•
Jump and branch instructions: table 3-3
•
Condition code register manipulation: table 3-4
•
Opcode map: table 3-5
~HITACHI
551
Table 3-1. Accumulator and Memory Manipulation Instructions
Condition Code
Register
Addressing Modes
IMMED
DIRECT
INDEX
-
-
EXTEND
IMPLIED
-
-
Boolean/
5
4
3
2
I
0
ArithmetiC Operation
H
I
N
Z
V
C
•
•
1
:
:
:
;
1
:
:
1
I
;
:
:
:
;
:
:
:
1
1
:
;
1
I
R
I
;
R
:
;
R
:
1
R
•
•
•
•
R
5
R
R
R
5
R
R
0
5
R
R
:
I
:
:
I
I
r
:
1
:
j
I
I
:
R
5
-
g OP
ADDA
8B
2
2 9B 3
2 AB 4
2 BB 4
3
A+M~A
:
AD DB
CB
2
2 DB 3
2 EB 4
2 FB 4
3
B+M--B
:
Add Double
AD DO
C3
3
3
4
2 E3 5
2
F3
3
A:B+M:M+I~
Add Accumulators
ABA
• •
: •
Add With Carry
ADCA
89
2
2
99
3
2 A9 4
2
B9
4
3
A+M+C~A
:
ADCB
C9
2
2 09
3
2 E9 4
2
F9
4
3
B+M+C~B
1
ANDA
B4
2
2 94 3
2 A4 4
2
B4
4
3
A'M~B
ANDB
C4
2
2 04
3
2
E4
4
2
F4
4
3
B·M~B
BIT A
B5
2
2
95
3
2 A5 4
2
B5
BIT B
C5
2
2 05
3
2
Operations
Add
AND
Bit Test
Clear
Compare
Compare
Mnemonic OP
03
# OP
# OP
5
# OP
A:B
IB
CLR
#
I
I
A+B~A
4
3
A·M
E5
4
2 F5 4
3
B·M
6F
5
2
7F
3
OO~M
5
CLRA
4F
I
I
OO~A
CLRB
5F
I
I
OO~B
CMPA
81
2
2
91
3
2
Al
4
2
BI
4
3
A-M
CMPB
CI
2
2 01
3
2
EI
4
2
FI
4
3
B-M
Accumulators
CBA
Complement. l' s
COM
II
63
6
2
73
6
I
I
A-B
M~M
3
COMA
43
I
I
A~A
COMB
53
I
I
B~B
6
70
6
OO-M~M
NEG
(Negate)
NEGA
40
I
I
OO-A~A
NEGB
50
I
I
OO-B~B
Decimal Adjust, A
60
2
Complement, 2'5
3
DAA
19
2
I
Converts binary
add of BCD char·
acters into BCD
format
Decrement
DEC
6A
6
2
7A
6
M-I~M
3
DECA
4A
I
I
DECB
SA
I
I
Exclusive OR
EORA
B8
2
2
9B
3
2
EORB
CB
2
2
08
3
2
Increment
INC
AB
4
2
E8
4
2
F8
6C
6
2
7C
BB
A-I~A
B-I~B
3
AEBM~A
4
3
BEBM~B
6
3
4
INCA
INC8
M+I~M
4C
I
I
A+I~A
5C
I
I
8+1~8
LDAA
86
2
2
96
3
2
A6
4
2
B6
4
3
M~A
LDAB
C6
2
2
06
3
2
E6
4
2
F6
4
3
M~8
Load Double
Accumulator
LDD
CC
3
3
DC
4
2
EC
5
2
FC
5
3
Multiply Unsigned
MUL
OR,lnclusive
ORAA
8A
2
2 9A
3
2
AA
4
2
BA
4
3
A+M-A
ORAB
CA
2
2 DA
3
2
EA
4
2
FA
4
3
s+M-B
load
Accumulator
Push Data
M+I-B.M~A
3D
I
PSHA
36
4
I
PSHB
37
4
I
Note: Condition Code Register will be explained in Note of table 3-4.
~HITACHI
552
7
AX8~A:8
A-Msp.
SP-I~SP
B-Msp.
SP-I~SP
•
•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
;
I
I
R
5
1
1
R
5
1
I
ct ;g;
i
1
CD
~
• •
I
I
ffi
~
• •
I
I
I
@
• • I I @ •
• • I I @J •
• • I I @J •
• • 1 I R •
• • I I R •
• • I I @ •
• • I I @ •
• • I I @ •
• • I I R •
• • I I R •
• • I I R •
• • • • •@
• • I I R •
• • I I R •
• • • • • •
• • • • • •
Table 3-1. Accumulator and Memory Manipulation Instructions (Cont.)
Condition Code
Addressing Modes
I
Operations
-
MnemonIc OP
Pull Data
DIRECT
IMMED
#
OP
-
INDEX
#
OP
-
Register
EXTEND
#
OP
-
IMPLIED
#
PULA
PULB
Rotate Left
ROL
69
Shilt Left
2
79
6
-
#
32
3
1
33
3
1
49
1
1
ROLB
59
1
1
RORA
46
1
1
RORB
56
1
1
66
ASL
6
68
76
2
6
2
78
6
6
Arlthmettc Operation
Shift Right
Arithmetic
3
1
1
ASLB
08
1
1
ASLD
05
I
I
77
2
6
6
ASRB
LSR
Double Shift
Right Logical
64
6
2
74
6
'3
'4
3
ASRA
Shift Right
Logical
2
1
0
H
I
N
Z
V
C
I
(Q)
I
I
I
@
I
I
I
'@
I
I
I
\:Ql
I
I
:
'@
r
I
I
f§)
I
• •
r
J
,6)
J
•
0
:
I
'lll
I
0
0
I
I
,§)
I
0
0
I
r
~l?)
r
0
0
J
I
@
I
0
0
0
48
67
3
• •
• •
'2
3
ASLA
ASR
4
• •
• •
• •
'1
Arithmetic
Double Shift
Left, Arithmetic
5
• • • • • •
• • • • • •
• • I I (6) I
SP+l-SP.
Msp-A
SP+l-SP.
Msp-B
3
ROLA
ROR
Rotate Right
6
OP
8001ean/
47
1
1
57
1
1
·s
3
LSRA
44
1
1
LSRB
54
1
1
LSRD
04
1
1
'6
'7
0
I
I
J
@
I
• •
R
J
@
I
0
0
R
J
@
J
0
0
R
I
@
J
•
0
R
I
@
I
J
I
R
,
•
I
R
0
I
I
R
•
I
I
J
I
• •
• •
• •
STAA
97
3
2
A7
4
2
B7
4
3
A-M
STAB
D7
3
2
E7
4
2
F7
4
3
8-M
Store Double
Accumulator
STD
DD
4
2
ED
5
2
FD
5
3
A-M
8-M+l
Subtract
SU8A
80
2
2
90
3
2
AD
4
2
80
4
3
A-M-A
• •
SU88
CO
2
2
DO
3
2
EO
4
2
FO
4
3
8-M-B
0
0
I
I
J
I
Double Subtract
SU8D
83
3
3
93
4
2
A3
5
2
B3
5
3
A: 8-M: M+lA:8
0
0
I
I
I
I
Subtract
Accumulators
S8A
A-8-A
•
0
Sabtract
SBCA
82
2
2
92
3
2
A2
4
2
82
4
3
A-M-C-A
S8CB
C2
2
2
D2
3
2
£2
4
2
F2
4
3
8-M-C-8
Store
Accumulator
10
1
1
• •
• .
• •
•
• •
With Carry
Transfer
Accumulators
TAB
T8A
Test Zero or
TST
6D
4
2
7D
4
16
1
1
17
I
I
A-8
8-·A
0
M-OO
3
Minus
TSTA
4D
1
1
A-DO
TSTB
5D
1
1
B-OO
And Immediate
AIM
71
6
3
61
7
3
M·IMM-M
OR Immediate
OIM
72
6
3
62
7
3
M+IMM-M
EOR Immediate
ElM
75
6
3
65
7
3
ME!lIMM-M
Test Immediate
TIM
78
4
3
68
5
3
M·IMM
'2
M
'1
M
A
B
'4
l ~,
C
Q-j
C
I~
b7
Ace A / Ace
A7
A
bO
AO
8
87
B
·s
1-0
80
11cH
C
IrJ
I
b7
b7
f-{]
bO
C
'6
J
I
I
I
I
I
I
I
I
I
I
I
R
0
I
I
R
•
I
I
R
R
I
I
R
R
I
I
R
R
•
• • I I R •
• • I : R •
J I R
• •------J
I
R
0
Alo-a ~ Io---l I I I I I I I ~
M
8
bO
~1C?1 I I I I I I
8
'3
• •
• •
• •
r
I
B
C
b7
b7
I 1--0
....L.....L.....L...L..-'-.L..:'bO
bO
'7
0--1
A7
ACC
A /
Ace
AO ,87
8
1-0
80
C
~HITACHI
553
Table 3-2. Index Register and Stack Manipulation Instructions
Condition Code
Register
Addressing Modes
Operations
DIRECT
IMMED
Pointer
Mnemonic OP
8C
- , OP
4
OP
EXTEND
IMPLIED
-, -, -,
OP
2 AC 5
OP
2 BC 5
Boolean/
5
4
3
2
1
0
Arilhmelic Operation
H
I
N
Z
V
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
I
I
I
I
X-M:Mtl
Compare Index Reg
CPX
Decrement Index
Reg
DEX
09
1
1
X-I-X
Decremenl Stack Pntr
DES
34
1
1
SP-l-'SP
3
3
9C
I
INDEX
3
Increment Index Reg
INX
08
1
1
Xtl··X
Increment Stack Pntr
INS
31
1
1
SPtl-'SP
Load Index Reg
LDX
CE
3
3
DE
4
2 EE
Load Stack Pntr
LOS
8E
3
3
9E
4
Store Index Reg
STX
DF
STS
9F
Store Stack Pntr
Index Reg - Stack
Pntr
Stack Pntr-Index
Reg
2 FE
5
3
2 AE 5
2 BE 5
3
4
2
5
2
FF
5
3
4
2 AF 5
2
BF
5
3
EF
5
TXS
M"'XH,
(Mtll,·XL
M"SPH,
(Mtll-SPL
Xw-M,
XL-(Mtll
SPH-M,
SPL-(Mtll
35
1
1
X-I-SP
TSX
30
1
1
SPtl-X
Add
ABX
3A
1
1
BtX-X
Push Data
PSHX
3C
5
1
Pull Data
PULX
38
4
1
Exchange
XGDX
18
2
1
Note: Condition Code Register will be explained In Note of table 3-4.
~HITACHI
554
XL "Msp, SP I-SP
XH-Msp.SP-l-·SP
SPt 1 -SP, MSp-XH
SPtl-SP,MsP-XL
ACCD-IX
• • •
• • • •
• • I •
• • • •
• CZ> I R
• CZ> I R
• CZ> I R
• CZ> I R
• • • •
• • • •
• • • •
• • • •
• • • •
• • • • •
I
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Table 3-3. Jump and Branch Instructions
Condition Code
Register
Addressing Modes
RELATIVE
Op-".tions
Mnemonic OP
-,
DIRECT
op
-
INDEX
EXTEND
, -, -,
op
OP
IMPLIED
OP
-
,
Branch Test
Branch Always
BRA
20
3
2
None
Branch Never
BRN
21
3
2
None
Branch if Carry
Clear
BCC
24
3
2
C=O
Branch if Carry Set
BCS
25
3
2
C=I
Branch if=Zero
BEQ
27
3
2
Z=I
Branch if?;Zero
BGE
2C
3
2
NE!ON=O
Branch if> Zero
BGT
2E
3
2
Z+ (NEElY) =0
Branch if Higher
BHI
22
3
2
C+Z=O
if~Zero
BLE
2F
3
2
Z+ (NElON) =1
Branch if Lower Or
Same
BLS
23
3
2
C+Z=I
Branch if < Zero
BLT
20
3
2
NEfJV=1
Branch if Minus
BMI
2B
3
2
N=I
BNE
26
3
2
Z=O
BVC
28
3
2
V=O
BVS
29
3
2
V=I
N=O
Branch
Branch if Not Equal
Zero
Branch if Overflow
Clear
8ranch if Overflow
Set
Branch if Plus
BPL
2A
3
2
Branch To Subroutine
BSR
80
5
2
Jump
JMP
Jump To Subroutine
JSR
No Operation
Nap
01
Relurn From Inlerrupt
RTI
3B 10
I
Return From
Subroutine
RTS
39
5
I
Software Interrupt
SWI
3F 12
I
Wait for Interrupt·
WAI
3E
9
)
Sleep
SLP
IA
4
I
90
5
6E
3
2
7E
3
3
2 AD
5
2
BD
6
3
I
I
Advances Prog.
Cntr. Only
5
4
3
2
I
0
H
I
N
Z
V
C
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
•
•
•
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
•
•
•
•
•
•
•
•
•
•
• •
•
• •
•
•
•
•
•
•
-• • • • • •
• • • • • •
--@--
• • • • •
• S • • •
• (9J • • •
• • • • •
•
•
•
•
Note: • WAI puts R/W high; Address Bus goes to FFFF; Data Bus goes to the three state.
Condition Code Register will be explained in Note of table 3-4.
~HITACHI
555
Table 3-4. Condition Code Register Manipulation Instructions
Addressing Modes
Condition Code Register
Implied
5
4
3
2
1
0
Boolean Operation
H
I
N
Z
V
C
1
O-C
1
0-1
1
1
O-V
1
1
1-C
OF
1
1
1-1
SEV
OB
1
1
1-V
Accumulator A-CCR
TAP
06
1
1
A-CCR
CCR-Accumulator A
TPA
07
1
1
CCR-A
• • • • • R
• R • • • •
• • • • R •
• • • • • S
• S • • • •
• • • • S •
--@J-• • • • • •
-
#
1
OE
1
ClV
OA
SEC
00
Set Interrupt Mask
SEI
Set Overflow
Operations
Mnemonic
Clear Carry
ClC
OC
Clear Interrupt Mask
CLI
Clear Overflow
Sat Carry
OP
Legend
OP Operation Code (Hexadecimal)
Number of MCU Cycles
Msp Contents of memory location pOinted to by Stack Pointer
#
Number of Program Bytes
+ Arithmetic Plus
Arithmetic Minus
•
Boolean AND
Boolean Inclusive OR
E9 Boolean Exclusive OR
M Complement of M
Transfer into
a Bit = Zero
00 Byte = Zero
Condition Code Symbols
H
Half-carry from bit 3 to bit 4
I
Interrupt mask
N
Negative (sign bit)
Z
Zero (byte)
V
Overflow, 2's complement
C
Carry/Borrow from/to bit 7
R
Reset Always
S
Set Always
1 Set if true after test or clear
•
Not Affected
+
Note:
Condition Code
(Bit V)
(Bit C)
CIl (Bit C)
® (Bit V)
® (Bit V)
'® (Bit V)
rJ) (Bit N)
® (All Bit)
® (Bit I)
(AI Bit)
Ij]) (Bit C)
CD
(2)
19
Register Notes: (Bit set if test is true and cleared otherwise)
Test: Result = 10000000?
Test: Result = OOOOOOOO?
Test: BCD Character of high-order byte greater than 10? (Not cleared if previously set)
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
Test: Set equal to N + C = 1 after the execution of instructions
Test: Result less than zero? (Bit 15= 1)
load condition code register from stack.
Set when interrupt occurs. If previous set, a non-maskable interrupt is required to exist the wait state.
Set according to the contents of accumulator A.
Result of multiplication bit 7= 1? (ACCB)
Table 3-5. Memory Map
OP
ACC
ACC
CODE
A
B
0011
0100
alaI
3
4
0000 0001
0000
0
0001
I
0010
2
0011
3
0100
4
/
NOP
0010
XT
~-~-'--'---r--r~~~~~~
~
DIR' IMM
DIR
IND
EXT
IMM
OIR
IND
EXT
INO
OlIO
alII
ACCA or SP
1000
1001
lOla
lOll
1100
1101
A
B
C
o
8
6
ACCB or X
SBA
BRA
TSX
CBA
BRN
INS
______
AIM
CMP
I
BHI
PULA
__________
DIM
SBC
2
BLS
PULB
COM
BCC
DES
LSR
L L
~L
LSRO L::::::
NEG
lila 1111
_______
I
SUB
SUBD,
AOOD
3
AND
4
BIT
5
0101
5
ASLD /
BCS
TXS
OlIO
6
TAP
TAB
BNE
PSHA
ROR
0111
7
TPA
TBA
BEQ
PSHB
ASR
1000
8
INX
XGDX
BVC
PULX
ASL
EOR
1001
9
DEX
OAA
BVS
RTS
ROL
ADC
9
lOla
A
CLV
SLP
BPL
ABX
DEC
ORA
A
lOll
B
SEV
ABA
BMI
RTI
AOD
B
_______,
ElM
a
LOA
/
!
STA
TIM
1/ i
6
STA
7
8
~~II~O~O-+~C-+~C~L~C~~~~~B~G~E~'-P~S~H-X~~-----INLC--------~------c~p~x~------rl------~L~O~D~-------~I
~-II-O-I-+--D-+-S-E-C~L~~-B-L-T1-M-U~L-+-------=TS~T~------~B~SR~----~JS~R~-~i~--~r:-----S-T-D--lila
E
CLI
/
BGT
WAI
1111
F
SEI
/
BLE
SWI I
------I
CLR
JMP
LOS
1/1
STS
I
~,
LOX
I 0
I
STX
L.::.0--.l--=I__L.::.2J--=3__L 4__-LI--=5__!L6~-L1__7---.-J:L8~ll__9---1,__A
__l!'__
B---1i__C__.L
i __D~__E_---,--F_j
OP CODE
• Only AIM, OIM, ElM, TIM instructions
IZI UNDEFINED
~HITACHI
556
E
1
3.4 CPU Instruction Flow
When operating, the CPU fetches an instruction from memory and executes the required function. This
sequence starts from RES high, and repeats itself continuously if not affected by a special instruction or
control signal. SWI, RTI, WAI, and SLP instructions change this operation, and NMI,IR01, IR02, IR03,
HALT, and STBY control it. Figure 3-2 shows the CPU mode transitions, and figure 3-3 is the CPU
system flowchart. Table 3-6 shows the CPU operating states and port states.
Figure 3·2. CPU Operation Mode Transitions
~HITACHI
557
(J1
(J1
(Xl
PC-1
pc.,
v:~~~o~~~~
STACK
PC, IX
ACCA
Acee
CCR
Notes; 1. The program sequence will come to the RES start from
any place of the flow during RES. When STBY=O, the
sequence will go into the standby mode regardless of the CPU
condition.
2. Refer to 3.8 Interrupts for more details of interrupts.
~
:I
~
(')
:I
N
Figure 3-3. System Flowchart
Table 3-6. CPU Operating States and Port States
Halt4
Port
Mo~e
Reset
Standby3
1 (AO-A7)
1,2
High
High impedance High impedance High
3
High impedance High impedance
Keep
1,2
High impedance High impedance Keep
Keep
3
High impedance High impedance
Keep
1,2
High impedance High impedance High impedance High impedance
3
High impedance High impedance
2
3 (DO-D7)
5
6
7
High impedance High impedance
High
4 (Ae-Als)
Sleep
Keep
High
2
High impedance High impedance High impedance
NoteS
3
High impedance
Ke~p
1,2
High impedance High impedance Keep
Keep
3
High impedance High impedance
Keep
1,2
High impedance High impedance Keep
Keep
3
High impedance High impedance
Keep
1,2
Note 1
Note 1
3
High impedance High impedance
High impedance
High impedance .Note 2
I
Keep
Notes:
1. RD, WR, R/W, LlR
2. RD, WR, R/W
= high;
SA
= low.
= high impedance; LlR, SA = high.
3. E is high impedance in standby state.
4. HALT cannot be accepted in mode 3.
5. Address output pin
= high; Input port = high impedance.
3.5 Low Power Dissipation Modes
The MCU has two low power dissipation modes, sieep and standby. Table 3-7 shows the MCU state in
sleep and standby modes.
~HITACHI
559
Table 3-7. Sleep and Standby Modes
Sleep Mode.
Standby Mode
Oscillation circuits
Continue operation
Stop
CPU
Stop
Stop
CPU registers
Hold
Undefined
RAM
Hold
Hold
I/O pins
Hold
High impedance
Timers
Continue operation
Stop
SCI
Continue operation
Stop
Internal Registers
Hold
Reset
How to release
Interrupt
STBY=low
Reset start
STBY = high before reset start
(Hold RES low after STBY high until
oscillator stabilizes, 20 ms min)
3.5.1 Sleep Mode
The MCU goes into sleep mode when the SLP instruction is executed. In the sleep mode, the CPU
stops operation while maintaining the registers' contents. Peripherals such as the timers and the SCI
continue their functions. One-fifth as much power is dissipated in sleep mode as. in the operating mode.
The sleep mode is terminated by an interrupt, or a RES or STBY signal. RES causes the MCU to reset,
STBY causes it to go into standby mode. When the CPU receives an interrupt request, it retums to
operating mode. If the interrupts are enabled, it branches to the interrupt service routine. If they are
masked, it executes the next instruction. However, Htimer 1 or 2 prohibits a timer interrupt, the CPU
won't cancel the sleep mode because there is no interrupt request to the CPU.
The sleep mode reduces power dissipation for a system that doesn't need the CPU's continuous
operation. Figure 3-4 is the sleep instruction timing chart.
PCn
PCn+ 1
FFFF
PCn 1 PCn+2
FFFF
BUS
Sleep Instruction
I'nlerrupt save rou~ne
/
Address
bus where
-~ SP ISP
sleep is cleared
Pen
SLP
PCn"
OP.+1
Interrupt occurs
::~~~interrupt
Program
Figure 3-4. Sleep Instruction Timing
@HITACHI
560
Sleep Is cleared
wHh interrupt
masked
LJ'T eY
DATA
'C=:
3.5.2 Standby Mode
When the STBY input goes low, the MPU stops all clocks and goes to the reset state. In this mode,
power dissipation is greatly reduced. All pins except VCC, VSS, STBY, and XTAL (outputs 0) are
detached from the MCU internally, and go to high impedance.
In standby mode, power is supplied to the MCU, so that the contents of RAM are retained. The MCU
returns from this mode with a reset.
An example of the use of this mode follows. First, save the CPU state and SP contents in RAM by an
NMI routine. Then disable the RAME bit in the RAM control register and set the STBY PWR bit to go to
standby mode. If the STBY PWR bit is still set after reset start, power has been supplied to the MCU and
the RAM contents have been retained properly. The system can restore itself by returning the
pre-standby information to the SP and registers. Figure 3-5 shows the timing at the NMI, RES and STBY
pins.
Note: In standby mode, the mode program pins, MPO and MP1, should be held according to the
operation mode. If they are opened, the standby current will increase over the specified value.
vee
I
CDI
I
I
I
NMl
MCU
I
@IRES
I
I
I
I
I
I
I
I
CVI STBY
RES
I
I
I
I
I
I
~
\~
CD NM~
111111
I
I
I
I
111111
I
I
I
HSave Registers
RAM/Port 5 Control
Register Set
))
I
I
I
I
I
1r----fT
I
I
f------l
Oscillator
Start Time
I------
Restart
Figure 3-5. Standby Mode Timing
~HITACHI
561
3.6 Trap Function
The CPU generates an interrupt with the highest priority (TRAP) when it fetches an undefined
instruction or an instruction from outside of memory space. The trap function prevents system
malfunctions caused by noise or program error.
3.6.1 Opcode Error
When the CPU fetches an undefined opcode, it saves the CPU registers as well as performing the
normal interrupt procedure and branches to TRAP ($FFEE, $FFEF). This has the highest priority next to
reset.
3.6.2 Address Error
When an instruction is fetched from outside the intemal ROM, RAM, and extemal memory area, the MCU
generates an address interrupt as well as an opcode error. But on a system with no extemal memory, a
trap is not generated if an instruction is fetched from the external memory area. Table 3-8 shows the
addresses where an address error occurs in each mode. This function is available only for an instruction
fetch, and does not apply to data read/write.
Table 3-8. Address Error Addresses
Mode
Address
$0000-$001 F
2
$0000-$001 F
3
$0000-$003F,
$0100-$EFFF
3.6.3 Caution
The trap function has a retry function other interrupts do not have. The program flow returns to the
address where the trap occured when RTI retums the CPU to the main routine from the TRAP routine.
The retry can prevent problems caused by noise, etc. However, if another trap occurs, the program can
repeat the retryITRAP cycle forever. Consideration is necessary in programming.
In figure 3-6, after executing instruction OPn, the MPU fetches and decodes an undefined opcode and
generates a trap interrupt. When the RTI is executed in the trap interrupt servicing routine, the MPU will
put $FF03 in the PC, fetch the same opcode, and generate the trap again. The MPU will endlessly
repeat loop ABC.
~HITACHI
562
In figure 3-7, after executing the BSR, the branch destination address is output to the address bus to
fetch the first instruction of the subroutine. If $0001 is erroneously output as the address, the MPU will
decode it and generate a trap interrupt. When the RTI is executed in the trap interrupt serviCing routine,
the MPU will put $0001 in the PC, and start from this address. This will generate another trap, in an
endless loop.
$FF01
OPn
$FF02
BSR
$FF02
Operand
$FF03
01
$FF03
Undefinition
$FF04
OPn
$FF04
OPn+ 1
c
Figure 3-6. Executing an Undefined Opcode
Figure 3-7. Erroneous Fetch
3.7 Reset
To reset the MCU during operation, hold RES low for at least 3 system-clock cycles. At the third cycle,
when the clock signal is low, all the address buses become high. While RES is low, the buses remain
high. When RES goes high, the MCU starts the following operations.
1.
Latches the value of the mode program pins, MP1 and MPO'
2.
Initializes the internal registers (see table 2-3).
3.
Sets the interrupt mask bit. For the CPU to recognize the maskable interrrupts IR01, IR02, and
IR03, this bit should be cleared in advance.
4.
Puts the contents (= start address) of the last two addresses ($FFFE, $FFFF) into the program
counter and starts the program from this address. See table 2-4.
The MCU cannot accept a reset input until the clock oscillation is stable after power-on (20 ms maximum).
This is because the reset signal is internally synchronized to the clock as shown in figure 3-8. Until
oscillation starts, the MCU is undefined. As the I/O ports are controlled directly by the RES pin,
they are reset after power-on reset. At this time, the data registers of these ports don't change.
Refer to 2.4 Ports for the state of the ports during reset. Figure 3-9 shows reset timing.
Internal reset signal
RES pin
Inside the LSI
Figure 3-8 Reset Circuit
~HITACHB
563
E
_
Internal R
_~\\\\\\\\\\\\\\\\~\\\
Internal W
_~\\\\\\\\\\\\\\\\\\\
Riw
_~\\\\\\\~\\\\\\\\Wy
I
~~~j---------55
AD _:""~~""'~tm~\m1&\\tm~\\\m1~\rn'f/~l~"CfD--;~l
VIR
Data Bus
_~\\~\\\~\\\\\\\\\}'
_~\\\\\\\\\\\\\\\\\\\~\\\\\\\~
O-O--O-~;l-l- - - PCB
PC15
pea
PC7
First
Instruction
Figure 3-9 Reset Timing
3.8 Interrupts
The CPU will complete the current instruction before accepting the request. If the interrupt mask bit in
the condition code register is set, the request will be ignored. When the interrupt sequence starts, the
contents of the program counter, index register, accumulators, and condition code register will be saved
onto the stack. Then the CPU sets the interrupt mask bit and will not respond to further maskable
interrupt requests. In the last cycle of the interrupt, the CPU fetches the vectors shown in table 3-9,
transfers their contents to the program counter and branches to the interrupt service routine.
The extemal interrupt pins IR01 and IR02 are also used as P50 and P51' The function is chosen by the
enable bits in the RAM/port 5 control register (bits 0 and 1) at $0014. See 2.5 RAM/Port 5 Control
Register for details.
When one of the intemalinterrupts.lCl.OCl.TOl.CMl. or SIO is generated, the CPU produces the
internal interrupt signal, IR03' IR03 functions just the same as IR01 or IR02, except for its vector
address. Table 3-9 is an interrupt vector map, figure 3-10 is the interrupt sequence, and figure 3-11 is
the interrupt circuit block diagram.
~HITACHI
564
Table 3-9. Interrupt Vector Memory Map
Ve~JQ[ LQ~£!tiQD
Priority
MSB
LSB
Interrupt
Highest
FFFE
FFFF
RES
FFEE
FFEF
TRAP
FFFC
FFFO
NMI
FFFA
FFFB
SWI (Software interrupt)
FFF8
FFF9
IRQ1. ISF (Port 6 input strobe)
FFF6
FFF7
ICI (Timer 1 input capture)
FFF4
FFF5
OCI (Timer 1 output compare 1. 2)
FFF2
FFF3
TOI (Timer 1 overflow)
FFEC
FFEO
CMI (Timer 2 counter matCh)
FFEA
FFEB
IRQ2
FFFO
FFF1
SIO (RORF
Lowest
+
ORFE
+
TORE
+
PER)
Interrupt
Test
E
Internal
Address Bus
NMI. IRO,.
_-'\...1.-'''---,I\-_J\.._J\.._...J\._..J\_..J'~-'''--'''-~''-_''-_''-_.r..._.J\.._-''-
SP-1
SP-2
SP-3 SP-4
sp-5
:~~~: A£~:SS
SP-6
IRO,.IR0 3
Internal
Data Bus
_-'''-~~_''-_J\.._...J\.
Op Code Operand 'Irrelevant
Op Code Data
Internal
Read
Internal
Write
\~
__
..J\_~~-J~-J~--'''-_A-_n-_J~_~_~~-'~
PCO- PC8- IXO- IX8- ACCA ACeS eCR
PC?
PC15 IX7
IX15
vMecS,.or
Vector
LSB
First Insf. 01
Interrupt Routine
_______________--JI
\~---------
I
Figure 3-1 O. Interrupt Sequence
~H8TACHI
565
Each Status Register's Interrupt
Enable Flag
1 ; Enable, 0; Disable
ISF
---.
-0
TAO,
iRa,
ICF
OCF1
-0-
OCF2
~--o-
TOF
IRQ,
CMF
RDRF
PER
ORFE ---1
TDRE
1.
--
-0-
--0-
1
Condition
Code
Register
I-MASK
ICI
o ;Enable
1 ;DisablE
~
TOI
r-v--
--rr:u--
CMI
Interrupt
Request
Signal
~
-J
Edge
Detective
Circuit
Sleep
Cancel
Signal
Ifddress Error
TRAP
Op Code Error
Detective Circuit
SWI
Figure 3-11, Interrupt Circuit Block Diagram
The SEI instruction sets the interrupt mask bit, inhibiting interrupts, The CLI instruction clears the
interrupt mask bit, allowing interrupts, The TAP instruction can set and clear the interrupt mask bit also.
There must be at least two cycles between clearing the interrupt mask bit and setting it again. or an
interrupt which occurs between setting and clearing the bit cannot be accepted (figure 3-12).
CLI
SEI
CLI
NOP
SEI
CLI
NOP
NOP
SEI
No
No
Yes
Figure 3-12. CLI and SEI Timing
~HITACHI
566
Section 4. Timer 1
The 16-bit programmable timer, timer 1, can measure an input waveform and independently generate
two independent waveforms. The pulse widths of the input and output waveforms can vary from
microseconds to seconds.
Timer 1 has the following components (figure 4-1).
ControVstatus register 1 (8 bits)
ControVstatus register 2 (7 bits)
Free-running counter (16 bits)
•
Output compare register 1 (16 bits)
Output compare register 2 (16 bits)
Input capture register (16 bits)
Internal Data Bus
~):$19,$IA
Output Compare
Register 2
I
I
.
7
l~
Output Compare 2
~
: : [ } SOB, SOC
Output Com pare
Register 1
I
I I
I
il$OD,$OE'
$09,$OA
Free Running
16 Bit Counter
Input Capture
Register
I
~~
I
~I
I
~
}
I
Overflow Detect
Output Compare 1
I
Edge Detect
r-RES
!
l~:~ 1~~~
...--.
I
I
i
I
I
I
I
I
-
I TOF I EICI IEOCilI ETOI IIEDG IOLVLll
:
I
I
I
CLK
R
TCSRI
$08
I
I
Or-
D
I
IRQ,
0
D
I
I
~;F- ;c~jOCF2{
-
[EOc1TlVl21 OE21 OEI
I
---n:=
I.
TCSR2
$OF
ClK
R
f-~--
n-
t
:
P25
-P21
P 20
f Block Diagram
~HITACHI
Figure 4-1, Timer
567
4.1 Free-Running Counter (FRC)
The key element of timer 1 is the 16-bit free-running counter. It is incremented by the system clock.
The counter value can be read by software without affecting the counter. Reset clears the counter.
The free-running counter is located at addresses $0009 and $OOOA. When the CPU writes to the high
byte of the FRC ($0009), a preset value ($FFF8) is actually written to both bytes of the counter,
regardless of the write data value. When the CPU writes to the low byte ($OOOA) after the high byte,
both the low and high byte of the write data value are written to the FRC. See figure 4-2. The counter
operates this way when written to by double-byte store instructions (STD, STX, etc).
Counter value
$FFF8
$5AF3
Writing $5AF3 to the FRC.
Figure 4-2. Counter Write Timing
4.2 Output Compare Registers (OCR)
The output compare registers are 16-bit readlwrite registers that control the output waveforms. They are
located at $0008, $OOOC (OCR1) and $0019, $001A (OCR2).
The OCR's are constantly compared to the FRC. When the data matches, the output compare flag
(OCF) in the timer conlroVstatus register (TCSR) is set. If an output enable bit (DE) in TCSR2 is set to 1,
an output level bit (OLVL) will be output to bit 1 (Tout1) and bit 5 (Tout2) of port 2. To determine the
output level for the next compare match, change OCR and OLVL.
The OCR is set to $FFFF after reset. The compare function is inhibited for a cycle just after a write to the
OCR or the upper byte of the FRC. This is so that the 16-bit value will be valid in the OCR, and because
$FFF8 is set after the FRC's upper byte is written.
To write to the OCR, use a 2-byte transfer instruction, such as STX.
~HITACHI
568
4.3 Input Capture Register (ICR)
The input capture register is a 16-bit read-only register located at $OOOD, $OOOE. It stores the FRC's
value when an external input signal transition at P20 generates an input capture pulse. Which transition
generates the pulse is defined by the input edge bit (IEDG) in TCSR1.
To input an edge bit to the edge detector, clear bit 0 of port 2's DDR. When an input transition occurs at
the next cycle of the CPU's ICR upper-byte read, the input capture pulse will be delayed one cycle. To
ensure input capture, the CPU must read the ICR with a 2-byte transfer instruction. The ICR is cleared to
all zeros during reset.
4.4 Timer Control/Status Register 1 (TCSR1)
The timer control/status register 1 is an 8-bit register located at $0008 (figure 4-3). All of the bits can be
read and the lower 5 can be written to. The 3 upper read-only bits indicate the timer status.
76543210
I'CF 1 OCF11 TOF 1 EICII EOCI11 ETOIIIEDG IOLVL 11 $0008
Figure 4-3. Timer Control/Status Register 1
4.4.1 Output Level 1 (OLVL 1)
OLVL 1 is transferred to port 2, bit 1 when a match occurs between the counter and OCR1. If OE1, bit 0
of TCSR2 is set to 1, OLVL 1 will be output at port 2 bit 1. Bit O.
4.4.2 Input Edge (IEDG)
IEDG determines whether the rising edge or the falling edge of P20 will trigger data transfer from the
counter to the ICA. IEDG = 0 specifies a falling edge (high to low); IEDG = 1 specifies a rising edge (low
to high). Bit 0 of port 2's DDR must be cleared for this function to operate. Bit 1.
4.4.3 Enable Timer Overflow Interrupt (ETOI)
Setting ETOI to 1 enables timer overflow interrupt (Tal) to trigger an internal interrupt (IR03)' When
ETOI is cleared, the interrupt is inhibited. Bit 2.
4.4.4 Enable Output Compare Interrupt 1 (EOCI1)
Setting EOCI1 to 1 enables output compare interrupt 1 (OCI1) to trigger an internal interrupt ( IR03)'
When EOCI1 is cleared, the interrupt is inhibited. Bit 3.
~HBTACHI
569
4.4.5 Enable Input Capture Interrupt (EICI)
Setting EICI to 1 enables input capture interrupt (ICI) to trigger an internal interrupt (IRQ3)' When EICI is
cleared, the interrupt is inhibited. Bit 4.
4.4.6 Timer Overflow Flag (TOF)
TOF is set when the counter value increments from $FFF to $0000. TOF is cleared when CPU reads
the TCSR1, then the counter's upper byte (at $0009). Bit 5, read only.
4.4.7 Output Compare Flag 1 (OCF1)
OCF1 is set when a match has occurred between the FCR and OCR1. Writing to OCR1 ($OOOB or
$OOOC) after reading the TCSR1 or TCSR2 clears OCF1. Bit 6, read only.
4.4.8 Input Capture Flag (ICF)
ICF is set when the transition of the P20 input signal selected by IEDG causes the counter to transfer its
data to the ICR. Reading the high byte of the ICR ($OOOD) after reading TCSR1 or TCSR2 clears ICF. Bit
7, read only.
4.5 Timer Control/Status Register 2 (TCSR2)
The timer control/status register 2 is a 7-bit register located at $OOOF (figure 4-4). All of the bits can be
read and the lower 4 can be written to. The 3 upper read-only bits indicate the timer status.
Both TCSR1 and TCSR2 are cleared during reset.
76543210
IICF IOCF110CF21 - IEOCI21oLVL21 OE21 OE1 I $OOOF
Figure 4-4. Timer Control/Status Register 2
4.5.1 Output Enable 1 (OE1)
Setting OE1 to 1 enables OLVL 1 to appear at P21 when a match has occurred between the counter
and the output compare register 1 (OCR1). Clearing OE1 makes P21 an I/O port. Bit O.
~HITACHI
570
4.5.2 Output Enable 2 (OE2)
Setting OE2 to 1 enables OLVL2 to appear at P25 when a match occurs between the counter and the
output compare register 2 (OCR2). Clearing OE2 makes P2S an 1/0 port. Bit 1.
Note: If OE1 or OE2 is set to 1 before the first output compare match after reset, P21 or P2S will output
O.
4.5.3 Output Level 2 (OLVL2)
OLVL2 is transferred to P2S when a match occurs between the counter and OCR2. If OE2 (bit 1 of
TCSR2) is set to 1, OVLV2 will be output at P2S' Bit 2.
4.5.4 Enable Output Compare Interrupt 2 (EOCI2)
Setting EOCI2 to 1 enables output compare interrupt 2 (OCI2) to trigger an internal interrupt (IRQ3).
When EOCI2 is cleared, the interrupt is inhibited. Bit 3.
4.5.5 Output Compare Flag 2 (OCF2)
I
OCF2 is set when a match has occurred between the FCR and OCR2. Writing to OCR2 ($0019 or
$001A) after reading TCSR2 clears OCF1. Bit 6, read only.
4.5.6 Output Compare Flag 1 (OCF1) and Input Capture Flag (ICF)
The OCF1 and ICF addresses are partially decoded. The CPU reading TCSR1ITCSR2 makes it possible
to read OCF1 and ICF into bits 6 and 7.
~HITACHI
571
4.6 Timer Status Flags
Table 4-1 shows set and clear conditions of each status flag in timer 1.
If flag set and clear conditions occur at the same time, timer 1 flags will be set.
Table 4-1 Timer 1 Status Flags
Flag
Timer 1
Clear Condition
Set Condition
ICF
. FRC ~ ICR at edge of P20
. Read TRCSR1 or TRCSR2, then ICRH
· RES = 0
OCF1
. OCR1 = FRC
· Read TRCSR1 or TRCSR2, then write
OCR1 H or OCR1 L .
· RES = 0
OCF2
. OCR2 = FRC
· Read TRCSR2, then write OCR2H or
OCR2L
· RES = 0
TOF
. FRC=$FFFF+ 1 cycle
· Read TRCSR, then FRCH
· RES = 0
4.7 Precautions on Clearing OCF
Writing to the OCR after reading the TCSR when the OCF is 1 clears the OCF. However, the OCF is not
cleared under the following conditions.
1.
A compare match is found before the CPU writes to the OCR after reading the TCSR with OCF = O.
2.
A compare match is found at the same time as the CPU writes to the OCR after reading the TCSR
with OCF = 1.
See figure 4-5.
The OCF will always be cleared if you assure that a compare match does not occur between the TCSR
read and the OCR write. In example 1, figure 4-6, the OCR is loaded with the contents of the
free-running counter (FRC) before the TCSR is read. A compare match will not occur until the FRC is
counted up. In example 2, an OCR write cycle is executed immediately before and after TCSR read. A
compare match will not occur until a match occurs between the contents of the FRC and the OCR write
data.
~HITACHI
572
1. When OCF is not cleared
(1) case 1
E clock
TCSR re,ad
OCF clear signal
OCRH write OCRL write
i
r---r--'
1
I
I I :
-------------+----~,5r_-------.L'_.+.:_..1.'______
I
I
______________
OCF
~_ _ _ _~~~-oc-F-set------~lf
OCF is not cleared.
(2) case 2
E clock
TCSR read
OCF set signal
OCF
At conflict. ---J
prior set
1..------------
Figure
4-5.
OCF Clearing Timing on Condition
Iprogram example]
I
[program example]
LDD
STD
I
I
I
I
LDD IOCR
ADD ~T
FRC
OCR
LDAA
TCSR
LDD
ADD
STD
OCR
STD
LDAA
OCR
TCSR
LDD
STD
OCR
OCR
CLEAR
CLEAR
OCT
+
~T~
OCR
Figure
~T
OCR
4-6 Clearing
the OCF
<€}HRTACHI
573
Section 5. Timer 2
In addition to timer 1, the HD6301Y0, HD6303Y, and HD63701Y0, have an 8-bit reloadable
timer for counting external events, timer 2. Timer 2 has a timer output, so the MCU can
generate three independent waveforms.
Timer 2 has the following components (figure 5-1).
•
ControVstatus register 3 (7 bits)
Upcounter (8 bits)
•
Time constant register (8 bits)
r---Timer1 FRC
J----+-- Port 2
Bit 7
r-r---+--------r_e_Port2
Bit 6
TCSR3
$OOlB
IRQ,
Figure 5-1. Timer 2 Block Diagram
5.1 Timer 2 Upcounter (T2CNT)
The 8-bit upcounter is located at $001 D. It operates from the clock input selected by CKSO and CKS1
of TCSR3. The counter can always be read without being affected. In addition, it can be written to at any
time, even during counting.
The counter is cleared when the counter value matches the time constant register (TCONR) value, or
during reset.
~HITACHI
574
If the CPU writes to the counter during a cycle when it is being cleared, it will not be cleared, but will take
the value written by the CPU.
5.2 Time Constant Register (TCONR)
The 8-bit write-only time constant register is located at $001 C. It is always being compared to the
upcounter.
When it matches, the counter match flag (CMF) of the timer controVstatus register 3 (TCSR3) is set. P26
will then output the value selected by TOSO and TOS1 of the TCSR3. When the CMF is set, the
counter will be cleared simultaneously and start counting from $00. This enables regular interrupts and
waveform output without any software attention. TCONR is set to $FF during reset.
When a write-only register like TCONR is read by the MCU, $FF always appears on the data bus.
Whenever the MCU performs an arithmetic or logic operation between memory, and a write-only register,
the resuh will be $FF.
5.3 Timer Control/Status Register 3 (TCSR3)
The 7-bit timer controVstatus register is located at $001 B (figure 5-2). All bits can be read and all bits can
be written except CMF (bit 7). TCSR3 is cleared at reset.
76543210
ICMFIECMII
-
I T2E I TOS1ITOSoICKS1ICKSOI$001B
Figure 5-2. Timer ControVStatus Register 3
5.3.1 Input Clock Select 0 and 1 (CKSO, CKS1)
CKSO and CKS1 select the counter clock as shown in table 5-1. When the external clock is selected,
the (ising edge of P27 increments the counter. The external clock's frequency can be up to one-half
the system clock frequency. If the E clock divided by 8 or 128 is selected, the clock comes from timer 1,
so do not write to the FRC. Bits 0 and 1.
~HITACHI
575
Table 5-1. Input Clock Select
CKS1
CKSO
Input Clock
o
o
o
Eclock
El8
o
El128
External clock (P27)
5.3.2 Timer Output Select 0 and 1 (TO SO, TOS1)
When the upcounter matches TCONR, timer 2 will output to P26 as selected by TOSO and TOS1 (table
5-2). When TOSQ and TOS1 are 0, P26 will be an I/O port. When toggle output is selected, the P26
output level reverses each time the upcounter and TCONR match. This produces a 50% duty cycle
square wav!! at P26 without software support. Bits 2 and 3.
Table 5-2. Timer 2 Output Select
TOS1
TOSO
Timer Output
o
o
Timer output inhibited
o
Toggle output
o
Output 0
Output 1
5.3.3 Timer 2 Enable (T2E)
When T2E is cleared to 0, the clock input to the upcounter is inhibited, and the upcounter stops. When
T2E'is set, the clock selected by CKSO and CKS1 is input to the upcounter. Bit 4.
Note: P2S outputs 0 when T2E bit is 0 and timer 2 is enabled by TOSO and TOS1. It also outputs 0
when T2E is 1 and timer 2 is output enabled before the first match occurs.
5.3.4 Enable Counter Match Interrupt (ECMI)
Selling ECMI to 1 enables CMI to trigger an internal interrupt (IRa3)' When ECMI is cleared, the interrupt
is inhibited. Bit 6.
5.3.5 Counter Match Ftag (CMF)
The read-only CM F bit is set when the upcounter matches the TCONA. It is cleared by writing a zero to it.
Bit 7.
5.4 Timer Status Flag
Table 5-3 shows set and clear condition of each status flag in timer 2.
If flag set and clear condition occurs at the same time, timer 2 flag will be set.
Tabie 5-3. Timer 2 Status Flag
Flag
Set Condition
Clear Condition
CMF
. T2CNT = TCONR
. Write 0 to CMF
• RES = 0
~HITACHI
576
5.5 Precaution for toggle pulse function of HD6301YO/HD6303Y/HD63701YO Timer 2
Please pay attention to the following items when using Timer 2 as Toggle pulse output
function.
PHENOMENAN
Just when T2CNT's content equals a TCR's content, after writing "1" to T2E bit of TCSR3 to
output toggle pulses from P26, the abnormal rising edge occurs at P26 and the first pulse
width will be 1/2 E clock cycle.
Therefore, in the application which needs off-and-on pulse groups, you can't get 50%-duty
output pulse at anytime.
Timing chart of Timer 2 and P26 is shown in Fig. 1 when TCR = Nand CKS = 0 CKS1
= 0 to
select E-clock as input pulse.
Case -_T_E......._W_u....1 $0011
Figure 6-3. Transmit/Receive Control Status Register
6.4.1 Wake-Up (WU)
In a typical multiprocessor configuration, the software protocol provides the destination address as the
first byte of a message. The wake-up function allows uninterested MCU's to ignore the rest of the
message. When the WU bit is set, the SCI stops receiving data until the next message.
The wake-up function is triggered by one frame length of consecutive 1's (10 bits for 8-bit data, 11 bits
for 9-bit data). This function is only available in asynchronous mode. Do not set WU in clock
synchronous mode. Receiving these consecutive 1's wakes up the SCI and clears WU. The SCI starts
receiving data. The RE flag should be set before WU is set. Bit o.
6.4.2 Transmit Enable (TE)
When TE is set, tran!"mit data will appear at P24 after a 1-frame preamble in asynchronous transmission,
or immediately in clock :;ynchronous transmission. P24 will be the serial output regardless of the state of
bit 4 of port 2's DDR. If TE is cleared, serial 110 doesn, affect P24' Bit 1.
6.4.3 Transmit Interrupt Enable (TIE)
Setting TIE enables TDRE to trigger an internal interrupt (IR03)' Clearing TIE inhibits the interrupt. Bit 2.
6.4.4 Receive Enable (RE)
Setting RE inputs the signal at P23 regardless of the state of bit 3 of port 2's DDR. When RE is cleared,
serial 110 doesn't affect P23. Bit 3.
~HITACHI
582
6.4.5 Receive Interrupt Enable (RIE)
Setting RIE enables RDRF or ORFE (lRCSR b~ 6 or 7) to trigger an intemal interrupt (IRQ3)' Clearing
RIE inhibits the interrupt.
B~
4.
6.4.6 Transmit Data Register Empty (TORE)
In asynchronous mode, the SCI sets lDRE when the lDR is transferred to the lDSA. In the clock
synchronous mode, SCI sets lDRE when the lDSR is empty. lDRE is reset by reading the lRCSR
and writing new transm~ data to the transmit data register. lDRE is set to 1 at reset. Bit 5, read only.
6.5.7 Overrun/Framing Error (ORFE)
The SCI sets ORFE when an overrun or framing error is generated during data receive. An overrun error
occurs when new receive data is ready to be transferred to the RDR, and RDRF is still set. A framing
error occurs when a stop bit is not O. OR FE is only affected in asynchronous mode. Reading the RDR
after reading the TRCSR clears the ORFE. It is cleared at reset. Bit 6, read only.
6.4.8 Receive Data Register Full (RDRF)
RDRF is set when the RDSR is transferred to the RDA. Reading the RDR after reading the lRCSR
clears the RDRF. It is cleared at reset. Bit 7, read only.
Note: When more than 1 of bits 5, 6, and 7 are set, one lRCSR read will clear them all. It is not necessary
to read theTRCSR once for each bit.
6.5 Transmit Rate/Mode Control Register (RMCR)
lhe RMCR (figure 6-4) controls the following for serial 110:
•
Baud rate
•
Clock source
•
Operation mode
•
Data fo rrnat
•
P22 function
In addition, if the 9-bit asynchronous format is used, RMCR holds the ninth bit. All bits can be read, and
all bits can be wr~ten to, except bit 7 (RD8).
~HITACHI
583
76543210
-
1 -
1 552 1 CC21 CC1
I I I I
cco
551
550
$0010
Figure 6-4. Transfer Rate/Mode Control Register
6.5.1 Speed Select (SSO, SS1, SS2)
SSO-SS2 control the baud rate used for the SCI. Table 6-1 lists the available baud rates. The timer 1
FRC (882 =0) and the timer 2 upcounter (882 = 1) provide the internal clock to the SCI. When SS2 is
set, timer 2 functions as the baud rate generator. Timer 2 generates a baud rate dependent on TCONR
as shown in table 6-2. Bits 0, 1, and 5.
Table 6-1. SCI Bit Times and Transfer Rates
Asynchronous
XTAL
SSO
SS1
SS2
E
2.4576 MHz
614.4 kHz
4.0 MHz
1_0 MHz
4.9152 MHz
1.2288 MHz
0
0
0
El16
26 J1S/38400 baud
16 (.1SI62500 baud
13 (.1SI76800 baud
0
0
El128
208 (.1SI4800 baud
128 (.1SI7812.5 baud
104.2 (.1SI9600 baud
El1024
1.67 msl600 baud
1.024 ms/976.6 baud
833.3 msl1200 baud
El4096
6.67 msl150 baud
4.096 msl244.1 baud
3.333 msl300 baud
Note 1
Note 1
Note 1
0
0
0
X
X
Note:
1.
When SS2 = 1, timer 2 is the SCI clock. The baud rate is as follows:
Baud rate = fI[32(TCONR +1))
Where:
f = timer 2 input clock frequency
TCONR = contents of timer constant register, 0-255
~HITACHI
584
Table 6-1. SCI Bit Times and Transfer Rates (cont.)
Clock Synchronous (Note 1)
SS2
SS1
SSO
XTAL
E
4.0 MHz
1.0 MHz
6.0 MHz
1.5 MHz
8.0 MHz
2.0 MHz
12.0 MHz
3.0 MHz
0
0
0
El2
2~/bit
1.33 ~lbit
1 ~/bit
0.667 fLs/bit
0
0
El16
16~bit
10.7 ~/bit
8 ~/bit
5.33 fLs/bit
El128
128 ~lbit
85.3 ~lbit
64 ~/bit
42.7 fLs/bit
El512
512
256~bit
171 fLs/bit
Note 2
Note 2
0
0
0
X
~lbit
341
Note 2
Note 2
X
~/bit
Notes:
1.
Bit rates for internal clock operation. External clock can operate from DC to 1/2 system clock
frequency.
2.
When SS2 is 1, timer 2 is the SCI clock. The bit rate is as follows:
Bit rate (jJ.sIbit)= 4(TCONR + 1)/f
Where:
f = timer 2 input clock frequency
TCONR = contents of timer constant register, 0-255
Table 6-2. Baud Rate and Time Constant Register Example
Baud Rate
2.4576 MHz
3.6864 MHz
XTAL Frequency
4.0 MHz
4.9152 MHz
110 (note 1)
21
32
35
43
70
106
150
127
191
207
255
51
77
300
63
95
103
127
207
38
600
31
47
51
63
103
155
1200
15
23
25
31
51
77
2400
7
11
12
15
25
38
4800
3
5
7
12
19
2
3
9600
19200
8.0 MHz 12.0 MHz
9
0
38400
0
Note:
1.
Et8 is used as the clock for 110 baud, E is used for all other baud rates.
~HITACHB
585
6.5.2 Clock Control/Format Select (CCO, CC1, CC2)
CCO, CC1, and CC2 control the clock source and data format (table 6-3). They are cleared during reset,
so the MCU will be in clock synchronous mode with extemal clock. Therefore, P22 starts out as a clock
input. To use P22 as an output port, set bit 2 of the port 2 DDR to 1 and set CC1 and CCO to 0, 1. Bits 2,
3, and 4.
Table 6-3. SCI Format and Clock Source Control
CC2 CC1
ceo
Format
Mode
Clock Source
P22
0
0
0
8-bitdata
Clock synchronous
External
Clock input
0
0
8-bit data
Asynchronous
Internal
Not used
8-bit data
Asynchronous
Internal
Clock output (note 1)
8-bitdata
Asynchronous·
External
Clock input
8-bit data
Clock synchronous
Internal
Clock output
7-bit data
Asynchronous
Internal
Not used
7-bit data
Asynchronous
Internal
Clock output (note 1)
7-bit data
Asynchronous
External
Clock input
0
0
0
0
0
0
0
Note:
1.
Clock output regardless of bits TE and RE of TRCSA.
6.6 SCI Receiving Margin
The receiving margin for the SCI is as follows.
Allowable deviation of bit error (t - to)ItO = ±43.7%
Allowable deviation of character error (T-TO)/TO = ±4.37%
T, TO, t, and to are defined in figure 6-5. When a modem is used for communication, waveform distortion
may exceed the allowable value, depending on the modem and channel.
~HITACHI
586
START
2
r------,
3
5
4
7
Ideal Waveform
Real Waveform
f - - -_ _
T~_t~
_ _
___I-I
Figure 6-5. Bit and Character Error
6.7 SCI Status Flags
Table 6-4 shows set and clear conditions of each status flag in the SCI.
If flag set and clear conditions occur at the same time, the SCI flags will be cleared.
Table 6-4. SCI Status Flags
Flag
SCI
Set Condition
RDRF
ORFE
. RDSR -
Clear Condition
Read TRCSR1 or TRCSR2, then
RDR
RES = 0
RDR
Framing error (async mode).
Stop bit = 0
Overrun error (async mode).
RDSR - ROR when RDRF = 1
TORE
TDR - TDSR (async mode)
TDSR is empty (clock sync
mode)
PER
PEN
=
1
~
Read TRCSR1 or TRCSR2, then
RDR
RES = 0
Read TRCSR1 or TRCSR2, then
write to TDR
Read TRCSR2, then ROR
RES = 0
~HITACHI
587
6.8 Precaution for clock-synchronous serial communication interface
When transmitting through clock-synchronous serial communication interface, TE bit should
not be cleared with TORE of TRCSR ($11) is "0".
The TORE set and clear conditions of SCI are shown as follows.
Set Condition
Clear Condition
1. TOR
When writing to TOR after TRCSR read,
-+
transmit shift register
with TORE = 1, TORE is cleared.
(asynchronous)
TORE
2. Transmit shift register is empty.
(clock-synchronous)
3. RES
=0
If transmit data is written to TOR, and then TE bit is cleared with TORE = 0 to stop
transmitting, TORE remains "0".
In this case, even if TE bit is set and transmit data is written again, the TOR data is not
transmitted.
Please note that TE bit must be cleared after the last data has been transmitted.
(This caution is not applied to asynchronous serial communication interface.)
~HITACHI
588
Section 7. HD63701 YO Programmable ROM (EPROM)
Programmable ROM Operation
The HD63701 YO's on-chip EPROM is programmed in
the PROM mode (figures 37 and 38). PROM mode is set
by bringing MPo, MP" and STBY low. In PROM mode,
the MeV doesn't operate. It can be programmed like a
standard 27256 EPROM using a standard PROM
programmer and a socket adapter. Table 18 lists
recommended PROM programmers and socket adapters.
Vee
Addresses
in PROM mode
Addresses
in MCU mode
MP,
Vpp
~
~
MPo
$COOO V / / /.1' / >' / /I
Dala
STBV
$0000
EI)o-EO,
Internal PROM
' - - - - - { RES/V"
Address
EAo-EA7
$FFFF I
$3FFF
I
Address
EAe-EAI4
:
(Note)
I
'1'
I
I
I
I
IL_______ .1I
$7FFF
P4,i---ct
Note: When reading this
address space,
$FF is output.
Figure 7.1 PROM Mode Functional Diagram and Memory Map
Table 7.1 PROM Programmers and Socket Adapters
PROM Programmer
Socket Adapter
Type Name
Maker
DATA I/O
Type Name
. 1218
228
298
Maker
DP-64S. DC-64S
Fp·64
CP·68
Hitachi
HS31YESSIIH
HS31 YESFOI H
HS31YESCOIH
Table 7.2 PROM Mode Selection
Pin
Mode
CE
OE
Vpp
EOo-E07
Programming
Low
High
Vpp
Data input
Verify
High
Low
Vpp
Data output
Programming inhibited
High
High
Vpp
High impedance
~HITACHI
589
G
G
Vpp
G
:~HD63701YOC::
,.(DC-64S)
EOo
EO,
EO,
E03
EO.
E05
E06
EO,
EAo
EA,
EA,
EA3
EA.
EA5
EA6
EA,
Vss
EA.
6E
EAIO
EAl1
EA"
EA'3
EA,.
CE
G
G
Vee
(Top View)
Figure 7-2. PROM Mode Pin Arrangement
7.1 Programming and Verification
When the CE pin is held low after the programming voltage (Vpp) is applied, data can be programmed in
PROM one byte at a time through port 3. To verify the data, hold the Vpp/OE and CE pins low after
programming, and the programmed data will be output from port 3.
When CE is returned high, port 3 will be high impedance, and PROM programming/verification will be
inhibited.
Programming precautions: The PROM memory cells should be programmed under specific voltage and
timing conditions. The higher the program voltage and the longer the program pulse is applied, the
more electrons will be injected into the floating gate. However, if an overvoltage is applied to Vpp, the
p-n junction may be permanently damaged. Pay particular attention to PROM programmer overshot.
Negative voltage noise will cause a parasitic transistor effect, which may reduce breakdown voltage.
The address range must be $000 through $3FFF because the on-chip EPROM is 16K bytes. Fill remainder
of EPROM area with FFFF for PROM programmer to correctly verify.
The HD63701 YO is connected electrically to the PROM programmer through a socket adapter. Therefore,
pay attention to the following:
1.
2.
Confirm that the socket adapter is firmly fixed on the PROM programmer.
Do not touch the socket adapter or the LSI during programming. Mis-programming can be caused
by poor contacts.
590
~HITACHI
7.2 Erasing (Window Package)
The EPROM is erased by exposing the LSI to ultraviolet light. All erased bits are in 1 'so
The conditions for erasing are: ultraviolet light with wavelength of 2537 A, and a minimum irradiation of
15 W' s/cm 2 . These conditions are satisfied by exposing the LSI to an ultraviolet light rated at 12,000
IlW/cm2for 15-20 minutes, at a distance of 1 inch.
7.3 Characteristics and Applications
7.3.1 Principles of Programming/Erasing
The HD63701YO's memory cells are the same as an EPROM's. Therefore they are programmed by
applying high voltage tq,control gates and drains, which injects hot electrons into the floating gate (figure
7-3). The condensed electrons in the floating gate are stable, surrounded by an energy barrier of Si0 2 film.
Such a cell becomes a 0 bit due to the memory threshold voltage change. A cell with no condensed
electrons at its floating gate appears as a 1 bit.
r------(
SiO,~
~
~
EX3888er
/
source\
( "J
Control gate
Floating gate
/orain
[" \
The erased cell (1)
The programmed cell (0)
Figure 7-3. Cross-Section of EPROM Memory Cell
The electron charge in memory cells may decrease as time goes by. This can be caused by:
1.
Ultraviolet light, discharged by photo-emitting electrons (erasure principle)
2.
Heat, discharged by thermal emitting electrons
3.
High voltage, discharged by a high electric field at the control gate or drain
If the oxide film covering a floating gate is defective, the erasure rate is great. Normally, electron erasure
does not occur, because such defective devices are found and removed during testing.
@HITACHI
591
7.3.2 Window-Type Package Precautions
Glass Erasure Window: If the glass window comes in contact with plastic or anything with a static
charge, the LSI may malfunction due to the electrostatic charge on the surface of the window. If this
occurs, exposing the LSI to ultraviolet light for a few minutes neutralizes the charge, and restores the
LSI to normal operation. However, charge stored in the floating gate decreases at the same time, so
reprogramming is recommended.
Electrostatic charge buildup on the window is a fundamental cause of malfunctions. Measures for its
prevention are the same as those for preventing electrostatic breakdown:
1.
Operators should be grounded when handling equipment.
2.
Do not rub the glass window with plastics.
3.
Be careful of coolant sprays, which may contain a few ions.
4.
The ultraviolet shading label (which includes conductive material) effectively neutralizes charge.
Ultraviolet Shading Label: If the LSI is exposed to fluorescent light or sunlight, its memory
contents may be erased by the small quantity of ultraviolet light in these sources. In strong light, the
MCU may fail under the influence of photocurrent. To prevent these problems, it is recommended that
the device be used with an ultraviolet shading label covering the erasure window after programming.
Special labels are sold for this purpose. They contain metal to absorb ultraviolet light. When choosing a
label, note the following:
1.
Adhesion (mechanical intensity)-Re-use and dust reduce adhesion. Peeling off a label may cause
static electricity. Therefore, erasing and rewriting is recommended after peeling. Sticking a new
label over the old one is better than replacing a label.
2.
Allowable temperature range-The allowable environmental temperature range of the label should
be noted. If it is used under conditions outside this range, the paste may stiffen or adhere to the
label, causing paste to remain on the window when the label is removed.
3.
Moisture resistance-The allowable moisture range and environmental conditions of the label
should be noted. It is difficult to find a shade label applicable to all conditions. The proper label
should be selected depending on the intended use of the MCU.
$HITACHI
592
Section 8. Applications
8.1 HD6301 YO in Expanded Mode
Figure 8-1 shows a microcomputer system using all CMOS peripheral LSI's as an application
example of the HD6301 YO in the expanded mode (modes 1, 2).
Ports 1 and 4 are used for address output, and port 3 is used for data I/O. The system is controlled by
directly connecting RD and WR as memory control signals and RIW and E as peripheral controls.
Address decoder
~~
A
Y,
~B
A,.
r-"'-- c
L
Y,I-·Y
cs,
31--
7'4'HC13B
HD6321
MCU
CMOS ACIA
CMOS PIA
±}"0
1....0.
r?--
A.-:-
;
~
E
R/W l -
0.-0,
Ie>-
IHD6350
E
R/W
cs,
--?-
r--
R/W
--
RS,
n
16
A.-A,.
B
0.-0,
Serial
Interface
:---
0.-0,
Ar- RS
RS.
:--
E
Ad dress bus
Data bus
RD
WR
t
CE
CS,
DE
A,.
.-.. cs
DE
TIE
WE
13
~
+- A.-A"
+
B
L.r- 1/0,-1/0.
HM6264A
Bk byte of S-RAM
A.-A"
0.-0,
HN27C64
Bk byte of EPROM
4:
A.-A ..
~ 0.-0,
HN613256
32k byte o'-Mask ROM
Figure 8-1. All CMOS Microcomputer System
~HaTACH8
593
8.2 HD6301 YO in Single-Chip Mode
Figure 8-2 shows a printer controller using the HD6301 YO in the single-chip mode (mode 3).
The HD6301 YO controls a 16-dot printer using I/O lines as its ports. Data from the host is
transferred to the MCU through the serialinterface or through a Centronics interface at port 3.
1\
,
Centronics
Interface
Latch
I
"j
Port 1
8
Port3
~
y
Port 4
8
Head driver
v
STROB
t
Tout1
(TImer)
MCU
Host
computer
system
2
Serial Interface
Rx
Port 7
I
Tx
I
L
Tout2
(Timer)
Panel
switch
display
LF Motor driver
2
Port 6
Port 5
y
CR Motor driver
Position detector
Figure 8-2. Printer Controller
8.3 Timer Applications
8.3.1 Timer 1
Timer 1 is a 16-bit programmable timer with the same architecture as the timer on the HD6301 V1, but
with an output compare register added. Timer 1 can perform the following four operations:
1.
Waveform generation or interval timing using output compare register 1 (OCR1)
2.
Waveform generation or interval timing using output compare register 2 (OCR2)
3.
Pulse width or pulse cycle measurement using the input capture register
4.
Interval timing with overflow interrupt
~HITACHI
594
Waveform Generation. The values of the output compare registers (OCR1, OCR2) are compared
with the free-running counter ~FRC) at every E cycle. When a match occurs, an output compare flag
(OCF1, OCF2) is set. When an output enable bit (OEl E, OE2E) is set, the value of the output level bit
(OLVL 1, OLVL2) is output at port 2 (Toutl: P21, Tout2: P25)' Figure 9-3 is a flowchart for OCR1
waveform generation.
Set P2, to timer output pin
- - - - - - - - - - Set timer output. I to OLVL I
'-----,,.-----'
- - - - - - - - - - Set O-interval-lime B to OCRI
' - _ - - - , , . - - _ - - ' ---------Clear OCFI and add 1-lntervaHime A to OCR 1
'----,-----'
Output Waveform (P2,)
Start
~
I-
B
I
.+
I
- - - - - - - - - Clear OCFl and add O-interval-time B to OCRI
I
I
A
.+
B
Lr-
"I" A--1
Figure 8-3. OCRl Waveform Generation
Pulse Width Measurement. The input capture register (ICR) latches the free-running counter value
at the transition of the external input signal, measuring the pulse width or cycle. Figure 8-4
is a flowchart of pulse width measurement.
~HITACHI
595
- - - - - - - - - Detect Input rising edge
'----'-r-----'
- - - - - - - - - Store the ICA to M, and clear ICF
- - - - - - - - Detect Input falling edge
'----'-r---'
'---""";"--'--'
- - - - - - - - - Store the ICA to M2 and clear ICF
- - - - - - - - - Pulse width A=(M 2)-(M,)
__
In_pu_t_w_av_e_fo_rm--,f
1~___________
~A-1
Figure 8-4. ICR Pulse Width Measurement
8.3.2 Timer 2
The a-bit relDadable timer provides such functions as an external event counter, interval timer, waveform
generator, and SCI baud rate generator.
External Event Counter. Operate timer 2 as an external event counter by setting input clock select,
CKSO and CKS1, to external clock and writing 1 into T2E. The timer 2 upcounter is incremented by the
external clock's rising edge. Figure 9-5 shows the routine that generates an Interrupt after N extemal
events occur (where N is an integer between 1 and 256).
~HITACHI
596
8.3.2 Timer 2
The a-bit reloadable timer provides such functions as an external event counter, interval timer, waveform
generator, and SCI baud rate generator.
External Event Counter. Operate timer 2 as an external event counter by setting input clock select,
CKSO and CKS1, to extemal clock and writing 1 into T2E. The timer 2 upcounter is incremented by the
external clock's rising edge. Figure 9-5 shows the routine that generates an interrupt after N extemal
events occur (where N is an integer between 1 and 256).
Interrupt routine
External clock input
Interrupt enable
~--.-----'
~--r-----I
- - - - Write 0 into CMF.
----. Set TCONR
- - - - Timer 2 enable
N-l~
I
02
CMF--------------------;.,----------~\
'--- Generates CMI
• Sets N-l In the TCONR when the external event counter
value which generates the interrupt is N.
Figure 8-5. External Event Counter
Square-Wave Generator. Timer 2 can generate a continuous square wave without software
supervision. Figure 8-6 shows this routine.
----- Select input clock
L -____- . -____--I
'----;-----'
'-------1
----- Set toggle output
-----. Set TCONR
• Set N- 1 In the TCONR, when the half cycle
of square waveform Is N.
- - --- Timer 2 enable
Figure 8-6. Square-Wave Generator
~HITACHI
597
8.4 SCI Applications
8.4.1 Timer 2 Baud Rate Generator
The SCI can use six kinds of clock source: timer 1's FRC (four kinds), timer 2, and an external clock. The
timer 1 baud rate clocks are not adjustable, but timer 2 can provide any baud rate. Figure 8-7 shows how
timer 2 can provide the baud rate.
CKS1 and CKS2 select E or Eta according to the baud rate.
Value of n to TCONR Is
Set CKS1,CKSO
TCONR=N
T2E=1
------- n
SS2=1
Set CC2. CC1,
CCO
_______ Selectlimer 2 as a clock source.
Select transfer formal.
f
_ 1
32 x baud rate
f: Input clock frequency
n: 0 to 255
_______ To Initialize the SCI, set TE and RE after more than
1 bit cycle at the required baud rate.
Figure 8-7. Timer 2 as Baud Rate Generator
8.4.2 Interlace between HD6301YO and HD6305XO
An HD6301 YO can interface to an HD6305XO in the clock synchronous mode. This gives 99
I/O lines, suitable for systems requiring many I/O lines. Figure 8-8 shows an example of this
interface.
Tx
Rx
Rx
Tx
ICK
SCLK
P6 0
P6,
f'
\'--'
c
3
C,
Hand Shake Line
HD6301YO
HD6305XO
Figure 8-8. HD6301 YO to HD6305XO Interface
Employing the clock synchronous mode enables the HD6301 YO to interface easily to
peripheral devices (A/D converter, real-time clock, etc) which use a clock synchronous
interface, as well as to the HD6305XO.
~HITACHI
598
8.4.3 I/O Expansion
The SCI can be used in the clock synchronous mode to supplement the available parallel I/O ports. Use
an external shift register to perform the serial-to-parallel conversion. Figure 8-9 shows this kind of I/O
expansion.
.
Output Data
'MSB
PORT ......-
......- - - { >
GND
MCU
P 2 . t - - - - -........-t
74LS164
CK
B
P2 2 ......- - - - - - - - -......
Output Ports
.
I
Input Data
'LSB
MSB\
MCU
PORT
P2 3
74LS165
QH
CLKINH
CK
GND
P2,
Input Ports
Figure 8-9. I/O Expansion in Clock Synchronous Mode
8.4.4 SCI Multiplexer
Use an analog multiplexer as shown in figure8-1 oto use the SCI with both an asynchronous and a clock
synchronous device, such as an HD6305XO and an RS-232C.
~HITACHI
599
HD14503
Analog MPXer
ClK
HD6305XO
X
Xo
Rx
etc.
MCU
P2,
Yo
Tx
Rx
Tx
Zo
Y
X,
Y,
Z
P2 3
I
P2,
Z,
Inhl.r1
A
B
C
lJ J
I
RS-232C
etc.
PORT PIN
J
Figure 8-10. Multiplexed SCI
8.5 Lowering Operating Current
8.5.1 Lowering Operating Frequency
The HD6301 YO/HD6303Y operating current is approximately proportional to the operating
frequency (figure 8-11). Therefore, if the system does not require a high-speed MCU, power
can be reduced by lowering the operating frequency.
21r-------------____________________~
14
~
s
Jl
10.5
c
~
E
::>
III
7
c
8
~
::>
U
0.7
0.1
1.0
1.5
2.0
Operallng Frequency (MHz)
. Figure 8-11. Operating Frequency and Current (Typical)
~HITACHI
600
3.0
8.5.2 Sleep Mode
The SLP instruction puts the MCU into the sleep mode. In the sleep mode, current consumption is
reduced to one-fourth to one-fifth of that in the operating state.When the CPU acknowledges an
interrupt request, it cancels the sleep mode. The average power consumption can be reduced by
putting the CPU in sleep mode whenever it doesn't actually execute any instructions, such as in
interrupt wait state or polling. Figure8-12shows a routine which wakes the CPU up every 65 rns, using
the overflow interrupt of the timer 1 FRC.
_______ Set the Timer 1 as the 65-ms interval
timer using FRC overflow interrupt.
'-----r---..J------- Interrupt wait state.
When the main routine processing time is 1 ms,
average operating current Icc is 1.58mA (1= 1MHz).
_1.5X65+7 X l
66
= 1.58 [mAl (1= 1MHz)
I
cc -
I
Figure 8-1 2. Low Power Consumption Using the Sleep Mode
8.5.3 Standby Mode
Bringing STBY (pin 7) low puts the MCU into standby mode. In standby mode, the oscillator stops and
the MCU goes into the reset state. The contents of RAM are maintained as long as VCC is greater than
or equal to 2 V. In standby mode, current consumption is reduced to a few J,1A. RAM can be maintained
by battery.
Bringing STBY high cancels standby mode. The MCU releases the reset state and starts oscillation.
RES (pin 6) should be held low for at least the oscillation stabilization time (tRC) after srnY high. Figure
8-13 gives an example of a circuit that sets standby from software. Figure 8-14 shows the
timing for this circuit, and figure 8-15 is an operating flowchart.
~HITACHI
601
MCU
r-----------------~~~__1ST!3'Y
Rr
+-........--1 RES
cr;J;
Standby mode cancel
L-----------~-------IPORT
Rr· Cr
(External Input)
> 20ms
Figure 8-13. Standby Circuit Example
PORT
Standby mode
cancel
(External Input)
r
II
fl
u
STBY
f5
RES
I
I
f
.......
I
I
Oscillation stability
• PORT goes to the high-impedance state with STBY low, so it is pulled high by the pull-up resistor.
Figure 8-14. Standby Timing
Standby mode
(20ms)
Figure 8-15. Standby Circuit Flowchart
~HITACHI
602
8.6 Memory Ready Application
The memory ready function allows the MCU to access low-speed memories or low-speed
devices. Figure 8-16 shows a circuit example, and figure 8-17 is its timing chart.
L
4~(4
MHz)
*
Rr.i
MP ,
CE
MP o
~
A
0 0 -0,
AO-A,.-
Dala Bus
.
EXTAL
/
"
/
-I\
/
Address Bus
0 0 -0,
AO-A,.
lA,.
CS
,----
4-BII binary
counler HD74LS161
MCU
i~'~OKI
A"
Low-speed
mask ROM
HN61256
Clear
.,..t
MR
Ao
®
E
"'"
The HN61 256 Is localed
In $4000 10 $BFFF.
Figure 8-16. Low-Speed Memory Access Circuit
~
ADB ::x'------'X~_x==:;
E
CS
r
@------------~I--~
MR
.
X=::r-:_----'X'---_L
~~
I
~------
~I__~~~
Dala
Figure 8-17. Memory Ready Bus Timing
~HITACHI
603
8.7 Halt Application
The halt function enables the MCU in the expanded mode to interface with a DMAC (HD6844) and
execute DMA (figure 8-18).
r-
",
rI--
A.-A,.
r--
I'
A
H
0.-0,
I"Y
..
R/W
t-t--
IRQ
I--
-
'f
E
MCU
;
A
0.-0,
"
Memory Unit
REs
BA
A.-A"
HALT
II)
::l
m
II)
.. ..:e
II)
DGRNT
DRQH
.(
Il
"
.
D._D,V
~
0
~
-
Riw
-
TxSTB
TxRQ.
H
HITACHI
611
~---------P~MR--------~~
2.4V
E
\
\
\
\
O.8V
\.._---
tSMR
MR
Figure 1-2. Memory Ready and E Clock Tirring
Instruction Execution
Cycle
HALT Cycle
tB'
8A
O.8V
Figure 1-3. HALT and SA Timing
Synchronous Clock
Transmit Data
Receive Data
*2.0V is high level when clock input.
2.4V is high level when clock output.
Figure 1-4. SCI Clocked Synchronous Timing
~HITACHI
612
t
Plo-P1,
r--
MCU Read
MCU Write
Iposu
P2o-P21~~~______~~~_________
P4o-P4, 2.0V
P50-P51~O~.S~VJjF-____~~~__~~____
P6 o-P6, (Inputs)
P30-P3,
(Inputs)
Figure 1-5. Port Data Set-up and Hold
Times (MCU Read)
Figure 1-6. Port Data Delay Times
(MCU Write)
E~
;~er 1
Output
--IX &~~a.:
______
~
!Too
x
T2CNT
L _____
f-
P2,. P25------------''-"'''''~.r2"....,.4'''V------
Figure 1-7. Timer 1 Output Timing
j 1
o.sv
tCKr
P2 6
'1"f2-;;.;·"'SV.::....._____
OulpulS
••
tCKI
-Timer 2; ttcyc
SCI
; ISeye
••
r
Output
Figure 1-8. Timer 2 Output Timing
P5 4 (is)
Port 6
r
Data
(lnpul)
··Timer 1; tPWT
Timer 2; tPWTCK
; IPWSCK
SCI
Figure 1-9. Timer 1·2, SCI Input Clock
Timing
Figure 1-10. Port 6 Input Latch Timing
Vee
Test Point
1rl
C
C~90pF
R
RL~2'2kQ
1S207<\®
or equiv.
for Port 1, Port 3. Port 4, E
= 30pF for
Port 2, Port 5, Port 6, Port 7
R=12kQ for Port 1- Port 7, E
Figure 1-11. Output Strobe Timing
Figure 1-12. Bus Timing Test Loads
(TTL Load)
~HITACHI
613
Interrupt
Test
Internal Bus
Address
:=:xi::)c::::Jc=X:=X=:)(=:::)C=X:=X=:X=:JC::::J~=~:;:X;:::::X=:J::
SP
SP·l
SP·2
SP·3
SP·4 SP·5 SP·6 ~§ll" ~'i:0r ~~
AddressAddressAddress
Internal
D8t8Bus __~~__~__~__-A__-J~__~__~__-A__-J~~~__~__~__~__-A~-J~__A-
Op' Operandlrrele.anIPCO- PCSCodeOp CodeData
PC7 PC15
,
Intemal
Read
IXOIX7
IXS- ACCA ACCa CCR Veclor VeclorFirsl In.,. of
IX15
MSa LSa Inlerrupl Rouline
\~-----------------
I
Intemal
W~e
Figure 1-13. Interrupt Sequence
_ _ 5.5V
\kc~'5V ,.c------I
----Ifr.---i-I----------!
Ikj-O.5V
!lfiiY
~~~S----------ir_--~
::~n.I._~
R/W.__'\\\W
II
I
~~f----I;r------
fl
~f
fl
\~_w
1m • •
tw
WR • •
Data
Bus
..~~~~------~~'l~~r--~------------_
PC8-
PCO-
pelS
PC7
First
Instruction
Figure 1-14. Reset Timing
~HITACHI
614
1.2 HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y Electrical Characteristics
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Supply voltage
Vee
-0.3 to + 7.0
V
Input voltage
Vin
-0.3 to Vee+0.3
V
Operating temperature
Topr
-20 to +70
·C
Storage temperature
Tstg
-55 to +150
·C
NQte:
This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection circuits. To assure the
normal operation, we recommend V,n, Vou,: Vss::l (V In or You,) :fiVer.
Electrical Characteristics
DC Characteristics
(Vee; 5.0
V ± 10%, f; 0.1 to 3.0 MHz, Vss; 0 V, Ta; -20 to + 70°C)
Item
Input high voltage
RES, STSY
Symbol
Min
Max
Unit
VtH
Vee-0.5
Vee+0.3
V
Vee X O.7
2.0
Vee+ 0.3
V
Vee+0. 3
V
-0.3
O.S'
EXTAL
Other inputs
Typ
Test Condition
Input low voltage
All other inputs
V,L
Input leakage current
RES, NMI, STBY,
MPQ, MP1
Il'nl
1.0
pA
V'n;0.5 to Vee-0.5 V
Three state
leakage current
Ao-A". 00-0 7• RO
WR. R/W. Ports 2. 5. 6
IITSd
1.0
pA
V'n;0.5 to Vee-0.5 V
Output high voltage
VOH
Output low voltage
Ports 2, 6
-IOH
Input capacitance
All other inputs
Cin
Siandby current'
Not operating
Current dissipation*
2.4
V
IOH=-200 pA
V
IOH--10pA
1.0
0.4
V
IOL=1.6 rnA
10.0
rnA
Vout= 1.5 V
12.5
pF
V'n=OV, 1= 1 MHz
Ta=2S'C
ISTB
3.0
15.0
pA
ISLP
I.S
3.0
rnA
Sleeping (1= 1 MHz")
2.3
4.5
rnA
Sleeping (1= 1.5 MHz")
3.0
6.0
rnA
Sleeping (1=2 MHz")
Sleeping (1=3 MHz")
Icc
RAM standby voltage
V
Vee-0.7
VOL
Darlington drive
current
00
VRAM
4.5
9.0
mA
7.0
10.0
rnA
Operating (1= 1 MHz")
10.S
IS.O
rnA
Operating (1= 1.5 MHz")
14.0
20.0
rnA
Operating (1=2 MHz")
21.0
30.0
mA
Operating (1=3 MHz")
2.0
a
V
Notes:
V,H min=Vcc-1.OV, VII. max=O.8V (All output terminals are at no load.)
Current dissipation of the operating or sleeping condition is proportional to the operating frequency. So the
current dissipations at x MHz operation are decided according to the following formula:
(I;x MHz)
;tyfl value (1;1 MHz) Xx
typo value
(f;x MHz)
max. value
=max. value (1"=1 MHz) Xx
(both the sleeping and operating)
In case 01 SCLK Input. V1L
= O.6V (- 20°C -
typo or max. values about
OOe)
~HITACHI
615
AC Characteristics
(Vcc=5.0 V ± 10%,1=0.1 to 3.0 MHz, Vss =0 V, Ta=-20 to + 70°C)
Bus Timing
HD6303Y
Symbol
Item
Typ
Max
Min
0.666
Typ
Max
Min
10
0.5
Typ
HD63C03Y
Max
MOo
10
0.333
Typ
Max
Unit
Cycle time
tcyc
10
10
pS
Enable rise time
t.,
25
25
25
20
ns
Enable fall time
tEl
25
25
25
20
ns
Enable pulse width high level l
PWEH
450
300
220
i40
Enable pulse width low level I
PWEl
450
300
220
140
Address, R/W delay time 1
tAD
250
190
160
120
ns
toow
200
160
120
100
ns
Data delay time
(Write)
Data set-up time
(Read)
Address, R/W hold timel
Data hold time
(Write)l
(Read)
RD, WR
pulse widthl
RD, WR delay time
RD, WR
hold time
DR delay
DR
time
hold time
80
70
60
50
ns
80
50
40
20
ns
tHW
70
50
40
20
ns
0
0
ns
220
140
tHR
450
300
ns
tRWD
40
40
40
40
ns
tHRW
20
20
20
20
ns
tOlR
200
160
120
80
ns
tHlR
tAce
10
10
Fig. i-IS
ns
tOSR
PWRW
Test
Condition
ns
tAH
Peripheral read access time 1
10
ns
ns
t80
MR set-up timet
tSMR
MR hold timet
tHMR
E clock pulse width at MR
PWEMR
Processor control set-up time
tpcs
Processor control rise time
tPCr
100
100
100
50
ns
Processor control fall time
tpCf
100
100
100
50
ns
SA delay time
tSA
160
120
ns
Fig. i-17
ms
Fig. i-28
Oscillator stabilization time
tRe
Reset pulse width
PWRST
Note: 1.
616
Min
HD63B03Y
HD63A03Y
400
280
100
230
170
50
70
ns
25
9
200
250
20
200
200
190
20
20
pS
100
ns
20
tCyc
These timings change in approximate proportion to tcyc. The figures in this characteristics represent those when tcyc is minimum (=in
the highest speed operation).
~HITACHI
Fig. i-16
ns
Figs. 1-17,
i-27,1-28
Figs. i-16,
i-17
Peripheral Port Timing
Item
HD63B03Y
HD63A03Y
HD6303Y
HD63C03Y
Symbol
Test
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit Condition
Peripheral data
set-up time
(Ports 2, 5,
6)
tpDSU
200
200
200
200
ns
Peripheral data
hold time
(Ports 2, 5,
6)
tpDH
200
200
200
200
ns
Delay time (From (Ports 2, 5,
enable fall edge to 6 7)
peripheral output) ,
tPWD
Input strobe pulse
width
tpWIS
200
200
200
(Port 6)
tlH
150
150
Input data set-up
(Port 6)
time
tiS
100
100
Output strobe
time
tOSD1
Input data hold
time
300 ns
Fig. 1-20
200
ns
Fig. 1-35
150
150
ns
100
100
ns
300
300
200
Fig. 1-19
300
200
200
Fig. 1-25
200 ns
tOSD2
Timer, SCI Timing
HD63D3Y
Item
Symbol
Min
Timer 1 input pulse width
tPWT
2.0
Delay time (enable positive
transition to timer output)
SCI input
clock cycle
(Async. mode)
(Clock sync,)
SCt transmit data delay
time (Clock sync. mode)
Max
Min
Typ
Max
2.0
400
troD
tS cyc
Typ
HD63C03Y
HD63BD3Y
HD63A03Y
Min
Typ
Max
2.0
400
Min
Typ
Max
2.0
400
Unit
teyc
400
ns
Test
Condition
Fig. 1-23
Figs. 1-21,
1-22
1.0
1.0
1.0
1.0
tcyc
Fig. 1-23
2.0
2.0
2.0
2.0
teyc
Fig. 1-18
ns
Fig. 1-18
220
trxD
220
220
220
SCI receive data set-up
time (Clock sync. mode)
tSRX
260
SCI receive data hold time
(Clock sync. mode)
tHRX
100
SCI input clock pulse width
tPWSCK
0.4
Timer 2 input clock cycle
ttcyc
2.0
2.0
2.0
2.0
Timer 2 input clock pulse width
tpWTCK
200
200
200
200
Timer 1 • 2, SCI input clock
rise time
tCKr
100
100
100
50
ns
Timer 1 • 2, SCI input clock
fall time
tCKf
100
100
100
50
ns
260
260
100
0.6
0.4
100
0.6
0.4
ns
260
ns
100
0.6
0.4
0.6
tS cyc Fig. 1-23
teyc
ns
~HITACHI
617
I
tcyc
~
E
\
Ao-A15
R!W
~V
j
PIJl.tL
I\O.8V
r--
~
V
2.4V
tE,
tAO -
~
PIJl.tH
tAH __
tEl
2.4V
.... O.8V
tRWO
P",,"w
~
-
JK
tHAW
/~2.4V
O.8V
~
--tHw _
!--toow_
/
'I
MCU Vlkite
00-0,
O.8V
tOSR--
2.0V
MC;U Read
00-0,
O.8V
!--tOLR--
'"
k. 0 .8V
Figure 1-15. Bus Timing
~HITACHI
>-
2.4V
I+--- tACC
618
1\1\
-
tHR
::!I~
~
tHLR
V
~----------PW£MR----------~
2.4V
\
\
\
\
O.BV
\.._---
---<+--+-_tHMR
tSMR
MR
IpCI
Figure 1-16. Memory Ready and E Clock Timing
Last Instruction
Instruction Execution
HALT Cycle
Cycle
tBA
2.4V
BA
O.BV
Figure 1-17 . HALT and SA Timing
I
Synchronous Clock
Transmit Data
Receive Data
·2.0V is high level when clock input.
2.4V is high level when clock output.
Figure 1-18. SCI Clocked Synchronous Timing
~HITACHI
619
rMCUWrite
P2 a-P2 7
P5a-P5 7
P6a-P67
(Outputs)
Figure 1-19. Port Data Set-up and
Hold Times (MCU Read)
Figure 1-20. Port Data Delay Times
(MCU Write)
E~
Timer 1
FRC
Output
______~X~~i:~
::::J
trOD
X~
I-
______
T2CNT
P2,. P2 s---------'--.....yr.i....4""V.,.....----
P2 6
Outputs _ _ _ _ _ _ _-',l-f-'~"'.S""V'--___
Output
Figure 1-21. Timer 1 Output Timing
:~
**
1r
tCKf
'Timer 2; ttcyc
SCI
; tScyc
••
Figure 1-22. Timer 2 Output Timing
Port 6
2.0V
Date
O.SV
(Input)
• -Timer 1; tPWT
Timer 2; tPWTCK
SCI
; tPWSCK
Figure 1-23. Timer 1'2, SCI Input Clock
Timing
Figure 1-24. Port 6 Input Latch Timing
Vee
-~'.1Fi:;;
C=90pF far 00-07. Ao-A'6. E
=30pF for Port 2, Port 5, Port 6. RD,WR.
Am, SA.
Iiii
R=12kQ
Figure 1-25. Output Strobe Timing
Figure 1-26. Bus Timing Test Loads
(TTL Load)
~HITACHI
620
Interrupt
Test
Internal
Address Bus _ _"-1-J\._--''-_''-_J\._...JI...._A.._...A_-I'\...._A.._..J\~-'~_0,-_J~c-...J'-_J'-
SP
SP-l
SP-2
SP-3
SP-4
SP-5 SP-6 ~~lfr ~~'1i0r ~~W
AddressAddressAddress
Internal
DataBus ___A.._~_-J'\...._A.._..J\_-I'\...._~_-r'-_''-_~_-'''--'''-_~_J\_...J'-_J'Op OperandlrrelevantPCQ- PC8- IXO- IX8- ACCA ACCS CCR Vector Vector First Inst, of
CodeOp CodeData
PC7 PC15 IX7
IX15
MSB L,SS Interrupt Routine
Internal
Read
\~------------------------------------~--------------------
________--J/r----------------------~\L______________
Internal
Wite
Figure 1-27. Interrupt Sequence
'~~~~
Vee
\
STBY
RES
f
Vcc- 0 5V
tpcs
Vcc-O,5V
---i\
:~:'ess_
~
tpes
a.BV
FFFF
FFFF
-•..
FFFF
FFFF
FFFF
FFFE
FFFF New PC
i-------I,I-'________
FFFF
FFFF
FFFF
~~f-------f»)-- - - - - - - - - - -
/
\\~\\\\\W
RD • •
Bu,
Vcc- 0 5V
••~~~~~~~~~~
jj
Data
~~r)-------------
5f
I
----
.~_~~r-'
PCSPC15
PCO-
PCl
First
Instruction
Figure 1-28, Reset Timing
~HITACHI
621
1.3 HD63701YO, HD637A01YO, HD637B01YO Electrical Characteristics
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Supply voltage
Vee
-0.3 to +7.0
V
Vpp voltage
Vpp
-0.3 to +13.0
V
Input voltage
Yin
-0.3 to Vee+0.3
V
Operating temperature
Topr
o to
+70
·C
Storage temperature
Tstg
-55 to +125
·C
Note:
This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection circuits. To assure the
normal operation, we recommend VIII, VOU!: Vss:i (V ln or Vou.) :aVl'Co
Electrical Characteristics
DC Characteristics
(Vee = 5.0 V ± 10%, 1=0.1 to 2.0 MHz, Vss=O V, Ta=O to + 70 ·C, unless otherwise noted.)
Item
Input high voltage
Input low voltage
Min
VIH
Vee-0.5
Vee+0.3
Unit
V
EXTAL
VeeXO.7
Vee+0.3
V
Other inputs
2.0
Vee+0.3
V
-0.3
0.6
V
-0.3
0.8
V
10.0
pA
1.0
pA
1.0
pA
Vin=0.5 to Vee-0.5 V
2.4
V
IOH=-200pA
Vee-0.7
V
IOH=-10pA
RES, MPo, MP), SCLK (P22)3
VIL
All other inputs
Input leakage current
RES
Typ
Ilinl
NMI, STBY, MPo. MP)
Three state
leakage current
Ports 1, 2, 3, 4,
5,6,7
Output high voltage
VOH
Output low voltage
Darlington drive
current
Input capacitance
liTSI!
VOL
Ports 2, 6
-IOH
RES
Cin
1.0
All other inputs
Standby current
Current dissipation)
Not operating
Vin=0.5 to Vee-0.5 V
0.4
V
IOL=1.6 mA
10.0
mA
Vout=1.5 V
65
pF
12.5
pF
Vin=OV, 1=1 MHz,
Ta=25'C
ISTB
3.0
15.0
pA
ISLP
1.5
3.0
mA
Sleeping
(1=1 MHz2)
2.3
4.5
mA
Sleeping
(1= 1.5 MHz2)
(1=2 MHz2)
lee
RAM standby voltage
Max
Test Condition
Symbol
RES, STBY, MPo, MP)
VRAM
3.0
6.0
mA
Sleeping
7.0
10.0
mA
Operating (1=1 MHz2)
10.5
15.0
mA
Operating (1=1.5 MHz2)
14.0
20.0
mA
Operating (1=2 MHz2)
2.0
V
Notes:
l. V"' min=V",·-l.OV. V". max=O.8V (All output terminals are at no load.)
2. Current dissiPation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max. values about
current dissipations at x MHz operation are decided according to the following formula:
(f=xMHz)
tyPo value
=typ. value (1=1 MHz) Xx
max. value
(f=x MHz)
= max. value (1=1 MHz)Xx
(both the sleeping and operating)
3. Only seria I clock use.
~HITACHI
622
AC Characteristics
(Vcc=5.0 V ± 10 %, f=0.1
to
2.0 MHz, Vss=O V, Ta=O to
+ 70
·C, unless otherwise noted.)
Bus Timing
HD63701YO
Item
Symbol
Cycle time
HD637A01YO
Max
Min
teye
10
0.666
Enable rise time
tEr
25
Enable fall time
tEl
25
Enable pulse width high level I
PWEH
450
300
220
ns
Enable pulse width low level I
PWEL
450
300
220
ns
Address, R/'ii delay time l
tAD
250
190
160
ns
Data delay time
(Write)
tDDW
200
160
120
ns
Data set·up time
(Read)
tDSR
80
70
60
ns
tAH
80
50
40
ns
(Write) I
tHW
80
50
40
ns
(Read)
tHR
0
0
0
ns
450
300
220
ns
Address, R/'ii hold time l
Data hold time
Min
Typ
Typ
HD637B01YO
Max
Min
10
0.5
Typ
Max
Unit
10
",5
25
25
ns
25
25
ns
Test
Condition
Fig. 40
RD, WR pulse widthl
PWRW
RD, WR delay time
tRWD
40
40
40
ns
RD, WR hold time
tHRW
20
20
20
ns
L1R delay time
tDLR
200
160
120
ns
L1R hold time
tHLR
10
10
10
ns
MR set·up time l
tSMR
400
280
230
ns
MR hold time l
tHMR
100
70
50
ns
E clock pulse width at MR
PWEMR
9
9
9
",5
Processor control set·up time
tpcs
Processor control rise time
tPCr
100
100
100
ns
Processor control fall time
tpCI
100
100
100
ns
BA delay time
tOA
250
190
160
ns
Fig. 42
Oscillator stabilization time
tRC
Fig. 53
Reset pulse width
PWRST
ns
200
200
200
20
20
20
ms
3
3
3
teye
I
Fig. 41
Figs. 42,
52,53
Figs. 41, 42
Note: l. These timings change in approximate proportion to teye. The figures in this characteristics represent those when teye is minimum (=in
the highest speed operation).
~HITACHI
623
Peripheral Port Timing
HD637A01YO
HD6370lYO
Item
Peripheral data
Symbol
Min
Typ
Max
Min
Typ
HD637B01YO
Max
Min
Typ
Max
• Test
Unot Condition
set·up time
(Ports 1, 2, 3
4,5,6)
tposu
200
200
200
ns
Peripheral data
hold time
(Ports 1, 2, 3
4,5,6)
tpOH
200
200
200
ns
Delay time (From
enable fall edge to
(Ports 1, 2, 3
4,5,6,7)
peripheral output)
300
tPWD
Input strobe pulse
300
300
ns
Fig. 45
Fig. 49
tPWIS
200
200
200
ns
Input data hold time
(Port 6)
IIH
150
150
150
ns
Input dala sel·up lime
(Pori 6)
115
100
100
100
ns
width
Oulpul
slrobe
delay
200
200
10501
lime
200
Fig. 44
ns
Fig. 50
10502
Timer, SCI Timing
HD63701YO
Item
Symbol
Min
Timer 1 inpul pulse widlh
IpWT
2.0
Delay lime (enable posilive
Iransition 10 limer oulput)
SCI input
clock cycle
(Async. mode)
(Clock sync.)
Typ
Max
2.0
Min
Typ
Max
2.0
400
400
Unit
Tesl
Condition
tcyc
Fig. 48
ns
1.0
Icyc
Fig. 48
2.0
2.0
2.0
Icyc
Fig. 43
ns
Fig. 43
220
220
220
ISRX
260
260
260
ns
SCI receive dala hold lime
(Clock sync. mode)
IHRX
100
100
100
ns
SCI input clock pulse width
IpWSCK
0.4
Timer 2 input clock cycle
Itcyc
2.0
2.0
2.0
Timer 2 inpul clock pulse width
tPWTCK
200
200
200
lime (Clock sync. mode)
Timer 1 • 2, SCI inpul clock
rise lime
fall time
0.6
0.4
0.4
0.6
15cyc Fig. 48
Icyc
ns
tCKr
100
100
ICKf
100
100
100
@HITACHI
624
0.6
100
Timer 1 • 2, SCI input clock
Figs. 46, 47
1.0
ITXO
SCI receive dala set·up
Min
HD637B01YO
1.0
SCI Iransmit dala delay
time (Clock sync. mode)
Max
400
1100
IScyc
Typ
HD637A01YO
ns
ns
~-----------tcyc------------t
E
PVVEL
PWoH
tEl
tEr
Ao-A ...
2.4V
A!W
O.BV
tAH
tAWD ~-_.-----
O.BV
to OW
--<
MCU Vllrite, __________________________________t-______
00-07
-<
MCU Read __________________________________t-__________
00-07
Figure 1-29. Mode 1, Mode 2 Bus Timing
~HITACHI
625
'-------PWEMR -----~
2.4V
E
\
\
\
\
O.BV
'-----
--<~-II--tHMR
MR
tSMR
2.0V
O.BV
Figure 1-30. Memory Ready and E Clock Timing
Instruction Execution
HALT Cycle
Cycle
E
BA
O.BV
Figure 1-31. HALT and BA Timing
Synchronous Clock
Transmit Data
Receive Data
• 2. OV is high level when clock input.
2.4V is high level when clock output.
Figure 1-32. SCI Clocked Synchronous Timing
~HITACHI
626
r
r--
MCU Read
MCU Write
E
E
P1o-Ph
P2o-P2, ~~~~____~~~~__________
P4o-P4, 2.0V
P50-P5, ~O~.B~V~~______~~~__~~_____
P6o-P6,
(Inputs)
P30-P3,
(Inputs)
OBV\!'-_ _..J
tPWD
P1o-Ph. P2o-P2,
P3o-P3,. P4o-P4, - - - - - - - - " ...:-:;-.,.,.,.-P5o-P5,. P6o-P6,
) ~:~~ Data Valid
P7o-P74
(Outputs)
Figure 1-33. Port Data Set-up and Hold Times
(MCU Read)
Figure 1-34. Port Data Delay Times (MCU Write)
E
E
Timer 1
FRC
_______-'x ~~1~
~
troD
T2CNT
X"-_______
t"--
P2,. P25-----------~--~\t~~2~.4~V,------Outputs
P2 6
Output
'tf2.-""·.;;:8..;.V_______
Figure 1-35. Timer 1 Output Timing
Figure 1-36. Timer 2 Output Timing
~;~
::4 .. \-r
if ..
'Timer 2; tteye
SCI
; tSeye
Port 6
Data
(Input)
"Timer 1 ; tpWT
Timer 2; tpWTCK
SCI
; tpWSCK
Figure 1-37. Timer 1, 2 SCI Input Clock Timing
Figure 1-38. Port 6 Input Latch Timing
Vee
RL=2.2kQ
Test POint o--~..-M--;
C
lS2074¢~~~~~:4~B~~~_-_-_-_-_-_-_-_--_-_
CMF
Figure 111-7. Timing for Timer 2 Output and CMF
~HITACHI
646
~
N+l
N
111.4 Bus Interface
111.4.1 E and Memory Ready
Question: What is the internal E clock state when the CPU uses the memory ready function?
Answer: Internal E clock operates at normal frequenCY(figure 111-8) .Since the timer count and the SCI
transfer rate are set by the internal E clock, they are not also affected by the memory ready function.
Internal E
External E
MR
(Memory ready signal)
Figure 111-8. Internal and External E Clocks
Supplement: It is impossible to examine the internal E clock from an external pin when using the
memory ready function.
111.4.2 Memory Ready and Halt After Reset
I
Question: After reset, are memory ready and halt functions enabled or disabled?
Answer: Both are enabled. MR and HALT in three operating modes is shown in table 111-6.
Table 111-6. Operating Modes
Operating Mode
Memory Ready
Halt
Expanded mode
Enabled (note)
Enabled
Enabled (note)
Enabled
No memory ready function
No halt function
2
Single·chip mode
Note: Invalid when accessing internal address space
Supplement: In the expanded mode (modes 1, 2), the memory ready enable bit (MRE) and halt
enable bit (HLTE) of the RAM/port 5 control register are set to 1 during reset, enabling memory
ready and halt functions.
~HITACHI
647
111.4.3 Buses at Internal Address Access
Question: When you access internal memory space, what states are the address buses, data buses,
and control lines in?
Answer: Address buses and control lines (RD, WR, 'R/W) are always output regardless of internal or
extemal address space accessing. During writes to the intemal address space, the same data is output
from the data bus. During reads, the data buses become high impedance.
111.4.4 External Access to Register Addresses
Question: When using extemal memory at the addresses shown below in expanded modes (modes
1,2), some addresses overlap internal registers and RAM addresses (figure 111-9). In such a case, are
there any problems?
Internal Memory Map
External Memory Map
$0000
Internal "..,.,,..,..,.,,..,..,..rrrrrrrrr-rr- - - - - - - - - - -
"""'M<7'<""""""""""'' ' ' ' ' '
register .......U-4U-4L.t..LL.t..L......."'+-~~~~ _____ _
Internal
"""'Tr7Tr7T77"TT>'"T""n"'+-~0.?~~ -
- - - - -
-b""""",,,,~:I'I."
RAM
$0140
Internal 1Tr.17T.17T.17T.17T.1"17r:l $COOO
ROM
~
= overlapped address space
$FFFF
(mode 2)
Figure 111-9. Overlapping Addresses
Answer: There are no problems, but the overlapped addresses in the external memory space should
not be used. When writing to the overlapping addresses, the same data is written into the internal and
external address space. When reading, data is read fror:n the internal, and the external address data is
ignored.
Supplement: If the RAM enable bit (RAME) of the RAM/port 5 control register is D, a readlwrite
from/lo the internal RAM space is invalid, and both operations are executed to the overlapped external
address space.
111.4.5 Buses During WAI
Question: What states are address buses, data buses, and control lines in after WAI instruction
execution?
~HITACHI
648
Answer: They are as in table 111-7.
Table 111-7. WAI State
Line
State
Address bus
FFFF (High)
Data bus
High impedance
RJW
High
RD
High
WR
High
111.4.6 Timing for Memory Ready and E Clock
Question: What do tHMR (memory ready hold time) and tSMR (memory ready set up time)
mean in the timing for "memory ready" and E clock? See figure 111-10.
Answer:
tHMR: When MR becomes low within tHMR from the E clock rising edge, the E clock is
extended (max setting).
tSMR: When MR becomes high within tSMR before the E clock falling edge (point A), E clock
becomes low in the cycle (minimum setting)
Integer times of cycle time
PW EMR
E
___J
,,
\
\
'-----''
,
MR
Figure 111-10 Timing for Memory Ready and E Clock
~HITACHI
649
111.4.7 Limit of Halt Time
Question: Is the halt time limited?
Answer: No. If the halt pin has been low before a restart, the halt functions after a reset vector
has been output and after the first instruction has been fetched.
Supplement: When the halt signal is set to low, the CPU stops after an instruction being
executed finishes, and goes to the halt state. The halted CPU sets the bus available (SA) to
high and the RD, WR and R/W to high impedance.
111.5 Interrupt Control
1II.5.1IRQ1 During Standby
Question: When the CPU is returning from standby mode (RES = low, STBY = low) with IRQ1 low, can
the interrupt be accepted if IRQ110w continues after return?
Answer: It cannot. Interrupts can be accepted when IRQ1 E = 1 and I = O. After the CPU returns from
standby, it has IRQ1 E = 0 and I = 1. To accept the interrupt, the software should make IRQ1 E = 1, 1=0
after resetting.
Supplement: IRQ1 E is the IRQ1 interrupt enable bit of the RAM/port 5 control register. When IRQ1 E
= 1, P50 can be used as an interrupt pin. I is the interrupt mask b~. When I = 0, the CPU accepts
interrupts.
111.5.2 Trap Interrupt
Question: How does the trap interrupt differ from other interrupts (NMI, IRQ1, IRQ2 and IRQ3)?
Allswer: The differences are:
Return address (figure 111-11)
Interrupt sequence (figure 111-12)
~HITACHI
650
@ Trap
CD NMi. IRQ" IRQ, and IRQ.
Main routine
Interrupt routine
Interrupt
Main routine
Interrupt routine
(Trap Interrupt)
(iiIMT. TAO ,. 1RC:i,. IRQ.)
·1
·1
·1: Return address = 1PC+ 11
·1: Return address =
~
Figure 111-11. Return Address
E
NMI.IRQ,.
IRQ,. IRQ.
- r. .________-t_ _ _ _ _ _ _ _ _ _ _ _ _ __
·2
CDNMI.IRQ,
Address Bus
® Trap interrupt
......- Interrupt sequences are different (·3)
I
I
Address Bus
®
·2: CD = Op code address.
= Op code address
·3: Trap interrupt has one more
cycle (UFFFFU).
®
+
1.
®=
uFFFFu
I
Figure 111-12. Interrupt Sequence
~HITACHI
651
111.5.3 LIR During Interrupt
Question: What is the output state of load instruction register (LlR) in the interrupt sequence?
Answer: The output state of LlR is low in the following cycles:
1. Prefetch cycle of the last instruction cycle opcode just before interrupt sequence
2. Fetch cycle of the first opcode of the interrupt routine
The output state of LlR in the interrupt sequence is shown below.
1. Last instruction execution cycle just before the interrupt sequence (figure 111-13).
E
Instruction execute cycle
,
--t--
Interrupt sequence
NMI, IRQ" _ _ _.,
IRQ" IRQ 3
Internal
Data Bus _ _---'''-_---'''-_---'''-"._---='''-:-.....,...---J~__"~,....."..,,.__..J'---.J
u
Figure 111-13. Last Cycle Before Interrupt
a. LlR output is low at the last instruction execution cycle just before interrupt sequence
opcode prefetch.
b. The first cycle of the interrupt sequence (b in figure 111-13) is a dummy fetch cycle. In this
cycle, there are two cases; an
oper~nd
is on the data bus, or an opcode is on the bus. In
both cases, LlR output is not low.
2. First opcode fetch cycle in the interrupt routine (figure 111-14).
E
-IL...f
--t- Interrupt routine
NMI,IRQ"
IRQ" IRQ 3
ylr---------------------
Internal
Data Bus
First
Op Code
------~)rlr--------------------.,LJ~----
Figure 111-14. First Cycle in Interrupt
LlR output is low when the first opcode of the/interrupt routine is fetched.
~HITACHI
652
Supplement: Load instruction register (UR) low shows that instruction opcode is on Jhe data bus.
111.5.4 Accepting an IS Interrupt
Question: Is an input strobe (IS) interrupt accepted during the execution of the IRQ1 interrupt
routine?
Answer: Yes. When an IS interrupt is generated during the execution of the IRQ1 interrupt
routine, with the input strobe enable (IS IRQ1 ENABLE) being set, and the IS flag is set;
1. It is accepted if the interrupt mask bit (I) of condition code register (CCR) has been cleared.
However, in this case, the interrupt factor of the IRQ1 must have been cleared before
clearing the I bit, that is, by setting the IRQ1 pin low and clearing IRQ1 E.
2. If the I bit of the CCR is set, it is accepted after the IRQ1 interrupt routine finishes.
Supplement: Since the IRQ1 and IS share an interrupt vector, levels of the input strobe flag (IS
FLAG) and IRQ1 pin are checked to determine which interrupt is generated, by reading P50
(bit 0 of port 5).
111.6 Oscillation Circuit
111.6.1 E Clock Triggering
I
Question: With which edge of the EXTAL clock does the E clock change, the rising or falling edge?
Answer: It changes synchronously with the falling edge (figure 111-15).
Figure 111-15. E Clock Timing
111.7 Reset
111.7.1 Ports at Reset
Question: What is the state of each port at reset?
Answer: It is as shown in table 111-8.
~HITACHI
653
Table 111-8. Port State at Reset
Port
Mode
Reset
1 (AO-A7)
1,2
High
3
High impedance
1,2
High impedance
3
High impedance
1,2
High impedance
3
High impedance
2
3 (00-07)
High
4 (Aa-A15)
5
6
7
2, 3
High impedance
1,2
High impedance
3
High impedance
1,2
High impedance
3
High impedance
1,2
Note 1
3
High impedance
/
Note:
1. RD, WR, R/W, LlR = high; SA = low
Supplement: E clock at reset is output at normal frequency after oscillation stabilization time.
111.7.2 I/O Port Output After Reset
Question: What data does an I/O port output when the data direction register '(DDR)
=1 after reset?
Answer: After reset, undefined data is output from the I/O port, since the data register of an I/O port is
undefined. For the output state, put data in the data register before setting the DDR = 1.
~HITACHI
654
111.7.3 RES Schmitt Trigger
. Question: Is a Schmitt trigger circuit provided with RES?
Answer: Yes (figure 111-16).
q,
1>
I
I
RES pin
o
Ol----ID
Internal reset signal
Internal
Figure 111-16. Reset Circuit
111.7.4 Reset Circuit Capacitance
Question: Does Cr in the reset circuit shown in figure 111-17 (Rr x Cr
>
20 ms), have an upper
limit?
I
STSY
Rr
RES
Cr
;J;
L-------~---~PORT
Release Standby
mode
(External input)
Rr· Cr
>
20 ms
Figure 111-17. Reset Input Circuit
Answer: No, because RES is provided with a Schmitt trigger circuit (figu re 111-1 6).
~HITACHB
655
111.7.5 State of I/O Ports during the 20 rns after a Power-on Reset
Question: What state are I/O ports in for the 20 ms after a power-on reset during which time
the oscillation is unstable?
Answer: The 1/0 ports are in the reset state immediately after a power-on reset because it is
directly controlled by the RES pin. However, at this time, the contents of the data register of
each port are undefined (figure 111-18).
Internal
reset
signal
I/O port
Inside of the LSI
Figure 111-18 Reset Circuit
111.7.6 State of Port 4 after a Reset
Question: What is the state of port 4 (8 bit 1/0 port) of the HD6301 YO after a reset?
Answer: Table 111-9 shows the state of port 4 after a reset.
Table 111-9. Port 4 After Reset
Mode
Extended modes
Single chip mode
State of port 4
Mode 1
Address bus high-order output (*1)
Mode 2
Input port
Mode 3
Input port
*1: In mode 1, the data direction register (DDR) is forcibly set and port 4 outputs high-order
addresses.
~HITACHI
656
111.7.7 State of Address Bus if Reset during Operation
Question: If reset occurs during operation, when does the address bus become $ FFFF?
Answer: Timing of RES and the address bus are as follows (figure 111-19).
E
Address
Bus
Mode 2
Port 4
Address
Bus
High impedance
Figure 111-19. Timing of RES and the address bus
111.8 Low Power Dissipation Mode
111.8.1 Standby During Instruction Execution
Question: Does the CPU wait until the current instruction is executed to enter the standby mode?
Answer: No. The CPU enters standby mode regardless of the current instruction; the CPU
goes into reset' condition and the oscillator stops with STBY low (figure 111-20).
I-- Oscillator Stop Internal reset
I
I
E
r
Figure 111-20. E During Standby
•
HITACHI
657
111.8.2 Standby Timing
Question: The timing for the standby mode is shown in figure 111-21 (see also figure 3-5). Is T1
in the figure defined?
vcc
vcc
CD
CDNMll
I
I
NMI
I
I
®
MCU
RES
STBY
0
RES
®
o STBY
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
'I ...
I
I
I
Tt
I
I
I
r---t
I
I
~~"fo-I
111111
I
I
I
I
I
7/
I
I11111
I
I
I
I
,{I
stoscillator
:
Stabilization
I
I
Time
f
I
I
.1 ..
• 1.I
I
I
I
I
Standby Mode
o Register Save
o RAM/port 5 control register set
I
I
Restart
Figure 111-21. Standby Mode Timing
Answer: It is not, but if the time for nonmaskable interrupt (NMI) is guaranteed, either RES or STBY
can go low with no priority.
Supplement: The CPU goes to the standby mode independently of instruction execution
sequence. Use the NMI routine before entering standby mode.
111.8.3 Ports at Standby
Question: What is the state of each I/O port during standby?
Answer: Each I/O port and the E pin during standby are high impedance.
111.8.4 Return from Standby Without Reset
Question: What occurs when the CPU returns from the standby mode without using reset start?
Answer: The CPU does not operate normally because the contents of each register are not defined.
Therefore, always use the reset start when returning from the standby mode.
~HITACHI
658
111.8.5 Sleep and Standby Internal States
Question: What are the internal states in the sleep or standby mode?
Answer: They are as shown in table 111-10.
Table 111-10. Sleep and Standby Mode States
Sleep Mode
Standby Mode
Oscillation circuit
Continues
Stops
CPU (register)
Stops (retained)
Stops (undefined)
RAM
Retained
Retained
1/0
Retained
High impedance
Timer
Continues
Stops
Serial communications
Continues
Stops
Internal registers
Retained
Reset
Cancel
Interrupt
STBY= low
Reset start
Reset start after STBY = high
(at hardware standby)
Reset start (at software standby)
Supplement: Internal states in the standby mode are the same as those in reset. Use the reset
start when returning from the standby mode. In this case RES should be kept low from STBY
=
high during oscillation stabilization time (20 ms minimum).
111.8.6 Sequence of Going to Standby Mode by Software
Question: How can the CPU go to the standby mode using software?
Answer: The CPU can go to the standby mode using software by clearing the standby flag
(STBY FLAG) of the RAM/port 5 control register. In this case, before going to the standby
mode, the standby power bit (STBY PWR) of the RAM/port 5 control register must be set and
the RAM enable bit (RAM E) should be cleared. Below is shown an example of the method of
going to the standby mode by software.
o
OIM #$80, $14 - - - (Setting STBY PWR)
AIM #$9F, $14 - - - (Clearing RAME, STBY FLAG)
~HnTACHH
659
111.8.7 Timing of Going to the Standby Mode by Software
Question: In the case that the CPU goes to the standby mode by clearing the standby flag
(STBY FLAG) of the RAM/port 5 control register, how many cycles after clearing does the
oscillator stop and does the CPU go into the standby mode?
Answer: The oscillator stops and the CPU goes to the standby mode at E clock's low level of
the first cycle after the STBY FLAG is cleared (figure 111-22).
Clearing STBY FLAG
-----------~
E
STBY FLAG
Standby mode
Figure 111-22 Timing of Standby Mode by Software
111.8.8 Writing to STBY PWR
Gluestion: Is it possible to write "0" into the standby power bit (STBY PWR) of the RAM/port 5
control register?
Answer: Yes. The STBY PWR can be used as a normal read/write flag.
111.9 Software
111.9.1 Bit Manipulation Instructions
Question: How should the bit manipulation instructions of the HD6301Y0, HD6303Y, and
HD63701Y0, be written?
Answer: They are written as shown in figure 111-23.
OIM # $ 0 4. $ 1 0
(Direct Addressing)
OIM # $ 0 4 • $ 1 0 • X (Index Addressing)
I+~
Immediate Data
Address
Index Register
Figure 111-23 OIM Example
This is an example of an OR operation between the immediate data and the memory which
stores the result in the memory. The AIM, ElM, and TIM instructions are written in the same
way.
~HITACHI
660
The bit manipulations in table 111-11 have different mnemonics with the same opcode.
Table 111-11. Shared Opcodes
Instructions Haying the Same QDcode
Mnemonic
Function
Bit Manipulation
Instruction
AIM
BCLR
OANDMi
The memory bit i (i = 0 to 7) is cleared and the other
bits don't change
OIM
BSET
10RMi
The memory bit i (i = 0 to 7) is set and the other bits
don't change
ElM
BTGL
MiEORMi
The memory bit i (i = 0 to 7) is inverted and the other
bits don't change
TIM
BTST
1 AND Mi
AND operation test of the memory bit i (i = 0 to 7) and
1 is executed and its corresponding condition code
is changed.
The mnemonics mentioned above can be written as in figure 111-24.
BelR
BClR
3,$10
- - AIM
3,$10,X - - AIM
#$F7.
#$F7,
$10
$10,X
(Direct Addressing)
(Index Addressing)
BSET
BSET
3,$10
3,$10,X
#$08,
#$08,
$10
$10,X
(Direct Addressing)
(Index Addressing)
~f
OIM
OIM
I
Bit Address Index Register
Figure 111-24. Shared Opcode Instruction Format
111.10 Others
111.10.1 RAME Disabled
Question: When executing a program with the RAM enable bit (RAME) of the RAM/port 5 control
register disabled (RAME
=0),
1. What occurs Hthe internal RAM address is accessed?
2. What occurs if Interrupt requests are generated?
Answer:
1. The Internal RAM cannot be accessed, It Is neither readable nor writable with RAME
= 0,
so In mode 1 or 2, the external memory Is read/written Into,
2. Interrupts are accepted, but the CPU will fall when returning from the Interrupt with no
~HITACHI
661
stacking area other than the internal RAM.
Supplement:
1. RAME = 0; internal RAM is invalid. In modes 1 or 2, data can be read from the extemal memory.
2. RAME
= 1; internal RAM is enabled.
111.10.2 RAME at Reset
Question: Is the RAM enable bit (RAME) set on reset at RES low or the rising edge of RES?
Answer: It is set at the rising edge of RES (figure 111-25).
Internal RAM
Disable
(RAME=O)
--r-I
:
Internal RAM
Enable
(RAME=1)
I
I
Figure 111-25. RAME at Reset
Supplement: RAME is seVcleared by the software.
1. RAME = 0; Internal RAM is invalid. In mode 1 or 2, data can be read from the external memory.
2. RAME = 1; Intemal RAM is enabled.
662
~HITACHI
Appendix IV: The Differences Between HD63701 YO
and HD6301YO
Item
HD63701YO
HD6301YO
Input low
voltage of RES,
VIL = 0.6 V max
VIL = 0.8 V max
lin and Cin
of RES
lin = 10 pA max
Cin = 65 pF max
lin and Cin are larger than HD6301 YO because RES is also
used as VPP.
lin = 1.0 pA max
Cin = 12.5 pF max
Crystal
oscillator
characteristics
Internal resistance
of crystal oscillator Rs
Internal resistance
of crystal oscillator Rs
MPo, MPI
Rs = 60n max
Frequency (MHz)
Rs max (0)
Storage
temperature
TsIg = -55 to 125'C
TsIg = -55 to 150'C
Caution
The HD63701 YO differs from HD6301 YO in chip design and manufacturing process. When
applying the HD63701 YO system to HD6301 YO, and HD6301 YO system to HD63701 YO,
note that characteristic values are not exactly the same even if guaranteed values are the
same.
I
•
HITACHI
663
Appendix V: Program Development Procedure and
Support System
.
V.1 Overview
The cross assembler and the hardware emulator using various types of computer are prepared by
the company as supporting systems to develop user's programs. User's programs are mask
programmed into the ROM and delivered as the LSI by the company.
Figure V-1 shows the typical program design procedure and table V-1 shows the system
development support tool for the HD6301YO which are used in these processes.
Text Editor/CRT Editor
Host Computer
Cra .. Auembler
Host Computer
Emulator,
EPROM On-Chip LSI,
HD63701VOC
Figure V-1. Program Design Procedure
~HITACHI
664
(Explanation)
1.
When the user programs the system using the HD6301 YO series, a functional assignment
of each I/O pin and an allocation of RAM area should be specified adjusting to designed
system before actual programming.
2.
A flowchart is designed to implement the functions and it is coded by using the HD6301 YO
3.
Write the software coded according to the flowchart on a floppy disk to make a source
4.
Assemble the source program to generate an object program using a computer. Assembly
mnemonic code.
program.
errors are also detected.
S.
Verify the program through hardware emulation with an emulator, H68SDS/SA, H680SD200 or
EPROM on-chip type microcomputer.
6.
Send the completed program to the company in the form of EPROM. Send Single-chip
microcomputer order specification and Mask option list at that time.
7.
ROM and mask option are masked by the company. LSI is testatively produced and the
sample is handed in to the user. If a user doesn't see any problem in programming, mass
production can be started.
Table V-1. Support Tools
Part No.
Emulator Set
EPROM
On-Chip LSI
EPROM On-Chip LSI
Programming
Socket Adaptor
IBM PC' Cross
Assembler
IBM PC
C Compiler
HD6301YO
HD6303Y
H31MIX3
(HS31 YEML03H)
HD63701YOC
HS31 YESS11 H
S311BM PC
US31 PCLl1 SF
Notes: IBM PC
IS
I
a trademark of International Business Machine Corporation.
CCompllor _ _ _ _ __
HD6301YO and HD6303Y Development Tools
~HITACHI
665
V.2 Single Chip Microcomputer ROM Ordering Procedure
V.2.1 Development Flowchart
Single chip microcomputer device is developed according to the following flowchart after
program development.
Device Development Flowchart
Hitachi
Customer
1
ROM code *1
2
Mask Option List *2
3
Ordering Specifications
*3
IComputer processing
,
Remarks
----
*1 2 sets of EPROM
*2 Part specific
*3 Generic for Hitachi
Microcomputer
ROM code for confirmation
of ROM fabricating
* 4 The same ROM code as
submitted
specifications *4
OK
4
Verification Listing *5
*5 Send it back after
approving
I Mask
I Sample
IWorking Sample (WS) *6
*6 3 pcs.
+
Confirmation of function,
15
Characteristics *7, *8
*7 Start the following
flowchart after
approving
*8 Send back signed
working sample approval
form.
OK
*9 10 pcs.
t
l Engineering Sample (ES) *9
IConfirmation of function,
l characteristics, quality
ICommercial Sample (CS)
(E~D)
Nole: Please send in 1 , 2, and 3 at ROM ordering, and send back 4, 5 after approving.
@HITACHI
666
V.2.2 Data you send and precautions
(a) Ordering specifications .................... Common style for all Hitachi single cnip
microcomputer devices. Please enter as for the
followings. The format is shown in the next page.
Basic ITEM
Environment Check List
Check List of attached data
Customer
(b) ROM code ................................ Please send in the ordering ROM code by 2 sets
of EPROM the same contents are written. Enter
ROM code No. in them. It is desirable to send in
program list for easy confirmation of the program
contents.
V.2.3 Change of ROM code
Note that if you change the ROM code once sended in or other specification, the ROM must be
developed from the beginning. The cost of mask charge should be provided again in this case.
V.2.4 Samples and Mass production
(Working Sample) ............................ Sample for confirmation of the contents of ROM
code and that of mask option. Normally 3 samples
are sent, but not guaranteed as for reliability.
Please evaluate and approve immediately because
the following sample making and
m~ss
production
are set about after obtaining your evaluation.
(Engineering Sample) ......................... Sample for evaluating also reliability. 10 pcs are
included in mask charge.
(Commercial Sample) ......................... Samples for pre-production which may be
purchased separately.
(Mass Product) ............................... Products for actual mass production. Please enter
the plan of mass production in full.
~HITACHI
667
V.2.5
HD6301YO
ORDERING SPECIFICATIONS
(1) GENERAL CHARACTERISTICS (Fill in blank space or check appropriate box
Customer
o
Package Outline
(See page 523.)
Device
Type
Application
(be specific)
0 .)
DP-64S
OCP-68
DFP-64
Options/Remarks:
Customer
ROMCodelD
ZTAT™
Conversion
ROM Code
Media
Operating
Temperature
Remask
DYes
o
o
o
D
DNo
EPRO~
ZTAT
Standard
Yes
Must Specify: Customer Programmed Start Address
Customer Programmed Stop Address
0
D
------1
J (-40· C to +85· C) version if offered
No
Previous Hitachi PIN
-----------
(2) OPERATING CHARACTERISTICS (Fill in blank space or check appropriate box [i].)
LSI
Ambient
Temperature
LSI
Ambient
Humidity
Typical
Power On
Duration
Typical
Range
·C-
Typical
Range
Power
Maximum Applied Supplv
Voltage To LSI
I/O
·C Target Level
Of Reliability
·C
o
o
% Acceptable Electrical
Quality
Major
%% Level
Visual
Hours/Day LSI Operating Speed
I (Specify MHz or KHz)
Remarks:
Max.
V
Max.
O(
)
]
(
)
0 (
)
lOOOFit
500Fit
[ ] 0.25% [
D
0.65%
V
(3) ELECTRICAL CHARACTERISTICS (Fill in blank space or check appropriate box [Xl.)
o
Purchasing Specifications
(0 Hitachi's Standard Specifications
Refer To Data Sheet:
( For Hitachi Use Only)
(4) CUSTOMER APPROVAL
(5) ROM CODE VERIFICATION
Customer Name'--_ _ _ _ _ _ _ _ _ _ _ __
PO# _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
LSI Type No.
Approved By (print),_ _ _ _ _ _ _ _ _ _ _ __
Shipping Date of
ROM To Customer
Approved By (signature)_ _ _ _ _ _ _ _ _ __
Date
~HITACHI
668
Approved Date of
ROM From Customer
HD6301/HD6303 SERIES HANDBOOK
Section Seven
Software
Application Notes
I
~HITACHI
669
~HITACHI
670
FOREWORD
The HD630l/HD6303 is a family of 8-bit single chip CMOS microcomputers
controlled by microprogramming.
This family aids high speed data process by
adding bit operation instruction, logical operation instruction, lower power
consumption mode instruction, and accumulator and index register swapping
instructions and adoping pipeline control, compared with the NMOS HD680l/HD6803
FAMILY.
APPLICATION NOTES summarize typical programs for the HD630l/6303 FAMILY
to help users better understand instruction set and to provide them with
references for making more customized programs.
Programs described in APPLICATION NOTES have already been debugged.
However, please be sure to check the operation in actual use.
I
~HITACHI
671
Section 7
Software Application Notes
Table of Contents
Page
1.
1.1
HOW TO USE APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
675
Formats.....................................................
675
1.1.1
Specification Format (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
677
1.1.2
Description Format (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
683
1.1 .3
Flowchart Format (Format 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
686
1.1.4
Program Listing Format(Format 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . .
688
1.2 How to Execute Programs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
690
1.3 Symbols.....................................................
692
PROGRAM APPLICATION EXAMPLES
Program Application Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
693
MOVING DATA
1.
Filling Constant Values (Fill) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
694
2.
Moving Memory Blocks (Move) . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . ..
698
3.
Moving Strings (Moves) .<
.........................................
703
Branching From Table (CCASE) ................. '. . . . . . . . . . . . . . . . . ..
708
BRANCHING FROM TABLE
4.
HANDLING ASCII
5.
Converting ASCII Lowercase Into Uppercase (TPR) .. . . . . . . . . . . . . . . . . ..
714
6.
Converting ASCII Into 1-Byte Hexadecimal (Nibble). . . . . . . . . . . . . . . . . . . ..
719
7.
Converting 8-Bit Binary Data Into ASCII (COBYTE) . . . . . . . . . . . . . . . . . . . ..
724
BIT MANIPULATION
8.
Counting Number of Logical "1" Bits In 8-Bit Data (HCNT). . . . . . . . . . . . . ..
729
9.
Shifting 32-Bit Data (SHR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
733
COUNTER
10.
4-Digit BCD Counter (DECNT)
738
COMPARISON
11.
Comparing 32-Bit Binary Data (CMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
@HITACHI
672
743
ARITHMETIC OPERATION
12.
Adding 32-Bit Binary Data (ADD)'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
749
13.
Subtracting 32-Bit Binary Data (SUB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
755
14.
Multiplying 16-Bit Binary Data (MUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
761
15.
Dividing 16-Bit Binary Data (DIV). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
768
16.
Adding 8-Digit BCD (ADDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
774
17.
Subtracting 8-Digit BCD (SUBD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
780
18.
16-Bit Square Root (SQRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
786
CONVERTING BCD INTO HEXADECIMALS
19.
Converting 2-Byte Hexadecimals Into 5-Digit BCD (HEX) . . . . . . . . . . . . . ..
791
20.
Converting 5-Digit BCD Into 2-Byte Hexadecimals (BCD) . . . . . . . . . . . . . ..
796
SORTING
21.
Sorting (SORT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
803
I
~HITACHI
673
~HITACHI
674
1.
How to Use APP.LICATION NOTES
1.1
Formats
APPLICATION NOTES consist of Formats 1 to 4, shown in Fig. 1.1.
FUNCTION
ARGUMENTS
CHANGES IN CPU
REGISTERS AND
FLAGS
,I
Format 1
Format 1
I
i'CU/MPU
IHD6)OI/~D6)Ol
FAMILY
LABEL
I
SPECIFICATIONS
SHR
PROGRAMLISTlIIG
/
L..I
I ~U/Hl'U
InOllClIART
11ID6l01/IID6JOl FAMILY
ILAIlEL
I
DESCRIPTION
,HR
I
)I£U/KPU
iHD6JOI/HD6l0lFAH1LY
ILABEL
I
lFun"inn
SIIR
DESCRIPTION
I
n;UfMPlJ
11lD6)OI/IW6JOl fAMILY
ILNIEL
I
Details
SIIR
fu:;-cnON
User Notes
CRANGESINCPU
RECISTERSANDFLACS
ARGlW:NTS
--I
10
"I
I'''dt J~
Byt~
~~:~~~:~
CUL1'~nt.
. ' Not affected
I.gth .
I
:Ile.ult
~'"
~"
i""
Moo
LJ
SPECIFICATIONS
I
SPECIFICATIONS NOTES
ROt-: (Ilytu)
• : Undefined
,
1
I
I
I
I
~"
,
"
,
"
RAH(llytea)
----;-;;~k(lly~~
Format 2_DESCRIPTION
No.ofcy<:les
RAM
Description
ReentT
~
SHIFTING 32-BIT DATA
~-l---------l
(2)
Item number
MCU/MPU:
O[
Program name
Indicates names of microcomputer and microprocessor family
applicable to a program.
)DB ~101nm6303 F~ILY O(
~Microcomputer and microprocessor family
name:
(3)
HD630l/HD6303 FAMILY
LABEL:
Indicates the name identifying program entry point.
When using a program as it is, call the label "SHR".
)~8~
Entry point label:
(4)
SHR
FUNCTION:
Explains program functions.
FUNCTION
I
(a) Shifts 32-bit binary data in IX and ACCD to right.
(b) Permits number of shifts to be freely determined.
(c) Permits easy multiplication of 32-bit binary data by 2-n . (n:number of shifts)
~HITACHI
678
(5)
ARGUMENTS:
Explains entry arguments which must be set before execution of a
program, and return arguments after execution.
(a)
Contents:
Explains meanings of arguments.
(b)
Storage Location:
Indicates registers and RAMs in which arguments are to be
set.
(c)
The RAM is presented as a labe 1 fo llowed by "(RAM)".
Byte length:
Indicates byte length of the arguments.
I
ARGUMENTS
Storage
Location
Contents
Upper 16
bits of
32-bit
binary
Byte
Lgth.
IX
2
ACCD
'2
data to
Entry
be shifted to
right
Lower 16
bi ts of
32-bit
binary
Arguments
data to
be shifted to
right
Number of SFCNTR
(RAM)
shifts
Upper 16
bits of
IX
2
ACeD
2
shift
Returns
I
result
Lower 16
bi ts of
shift
resul t
(6)
1
CHANGES IN CPU REGISTERS AND FLAGS:
Explains changes in CPU registers after executing a program
and flag changes of condition code register.
Meanings of ab-
breviations and symbols in the table are given as follows:
(a)
CPU register
ACCA:
Accumulator A
ACCB:
Accumulator B
ACCD:
Double accumulator (ACCA:ACCB)
IX:
Index register
~HITACHI
679
(b)
Flags of condition code register
(c)
C:
Carry/borrow flag (carry and borrow)
Y:
Overflow flag (Indication in case of 2's complement
operation) .
Z:
Zero flag (Indication in case of 0)
N:
Negative flag (Indication in case of negative)
I:
Interrupt flag (Interrupt mask)
H:
Half carry flag (Carry from bit 3 to bit 4)
State of CPU registers and condition code register flags
.:
Not affected:
Maintains previous values after executing
a program.
x:
Does not maintain previous values after
Undefined
executing a program.
;:
Be set with the result of executing a
Result
program
CHANGES IN CPU
REGISTERS AND FLAGS
•
: Not affected
x : Undef ined
I
(Notes)
In the example, after executing a program,
contents of index register (IX), condition
: Result
code register (CCR), bit
ACCD
ACCA
ACCB
I
I
bit Z will be destroyed.
c,
bit V, bit Nand
Thus, register
contents which will be destroyed should be
IX
~
\.....-.!-
saved before executing a program.
C
V
x
x
Z
N
x
x
I
H
• •
(7)
SPECIFICATIONS:
Explains program specifications.
(a)
ROM
(Bytes):
Indicates ROM capacity used in a program.
(b)
RAM
(Bytes):
Indicates RAM capacity used in a program.
(c)
Stack
(Bytes):
Indicates stack size used in a program.
The
RAM capacity in this table does not include
the stack size.
~HITACHI
680
When the program is executed,
it is necessary to reserve the stack size in
RAM.
(d)
No. of cycles
Indicates maximum number of execution cycles
when MCU executes a program.
Calculate the
execution time of the program as follows:
Execution time (sec)
= Cycle number x cycle
time
Cycle time (sec)
(e)
Reentrant
4/(External oscillator (Hz»
Indicates whether a program has a structure
which can be called from two or more routines
at the same time.
(f)
Relocation
Indicates whether a program can be located in
any memory space.
(g)
Interrupt
Indicates whether MCU executes a program
normally after serving an interrupt routine
during program execution.
If impossible,
inhibit interrupt before the program is
called.
SPECIFICATIONS
ROM (Bytes)
11
I
RAM (Bytes)
1
Stack (Bytes)
0
No. of eye les
261
Reentrant
No
Relocation
No
Interrupt
Yes
@HITACHI
681
(8)
DESCRIPTION:
Explains function details and user
notes of a program.
(a)
(b)
Function
Gives an execution example and detailed func-
Details
tions of a program.
User Notes
Explains notes and limitations when executing
a program.
,~
Be sure to read these items when using the
programs without change.
DESCRIPTION
(1) Function Details
(a) Argument details
IX
Holds upper 16 bits of 32-bit binary data to be shifted to right.
After SHR execution, contains upper 16 bits of shift result.
ACeD
Holds lower 16 bits of 32-bit binary data to be shifted to right.,
After SHR execution, contains lower 16 bits of shift result.
SFCNTR: Holds number of shifts.
(RAM)
(b) Fig. 1 shows example of SHR execution.
in part
Q) of
@of Fig. 1.
If entry arguments are held as shown
Fig. 1, 32-bit binary data is shifted to right as shown in part
In this case, "0" in upper 2 bits.
b7
b31
SFCNTR
bO
IX
ACCD
bO
CD ~:~~::ntst ~~~~~~~ B3) 101011111010 1110101110 10101110111010101110111+1110111110101111 I
Fig. 1 Example of SHR execution
(2) User Notes
Number of shifts should be held within range of $01 to $lF, otherwise
ACCD and IX become "0".
(9)
SPECIFICATIONS NOTES: Explains notes on data process written in
SPECIFICATIONS (7).
SPECIFICATIONS NOTES
I
"No. of cyc les" in "SPECIFICATIONS" represents the number of cycles needed to
shift 32-bit binary data 16 bits right.
682
~HITACHI
1.1.2 DESCRIPTION Format (Format 2)
The DESCRIPTION Format is represented in Fig. 1.3.
It gives remaining
Function Details, User Notes, RAM Description. Sample Application and
Basic Operation.
Each item in the format is described using Fig. 1.3.
ITEM NUMBER AND PROGRAM NAME
DESCRIPTION
I
MCU/MPU
I
HD630l/HD6303 FAMILY
I
LABEL
I
1
(3) RAM Description
(4) Sample Application
(5) Basic Operation
I
Fig. 1.3 DESCRIPTION Format
(1)
(2)
ITEM NUMBER AND PROGRAM NAME }
MCU/MPU
Same as SPECIFICATION Format
(3)
LABEL
~HITACHI
683
(4)
DESCRIPTION:
Gives RAM Description, Sample Application, and Basic Operation.
(a)
RAM Description:
Explains label and meaning of the RAM used
in a program.
9.
SHIFTING
HD630l/HD6303 FAMILY
SHR
DESCRIPTION
(3) RAM description
Description
RAM
Label
b7
SFCNTR
(b)
bO
Number of shifts is stored.
Ll_______--'l
Sample Application: Gives a sample application in
actual use.
(4) Sample Application
Subroutine SHR is called after number of shifts and 32-bit binary data to be
shifted to right are held.
wORln
RMB
4 ----------- Reserves memory byte for 32-bit binary data.
WORR2
RMB
1 ----------- Reserves memory byte for number of shifts.
WORR3
RMB
4 ----------- Reserves memory byte for shift result.
LDM
WORK2
STM
SFCNTR
LDX
WORKl
LDD
WORK 1+2 ~
L____
r
Stores number of shifts into
entry argument (SFCNTR).
~ ____ Loads 32-bit binary data to be shifted to
right into entry argument (IX, ACCD) •
"II_J_S_R_ _ _S_H_R_.J.JII----- Calls subroutine SHR.
SIX
WORK 3
SID
WORR3+2
}
Stores shift result (return argument
(IX, ACCD» in RAM.
~HITACHI
684
(c)
Basic Operation:
Indicates operating principles
of a program.
(5) Basic Operation
(a) Uses 16-bit shift instruction (LSRD) provided in the HD6301/HD6303 FAMILY.
(b) Upper 16 bits in 32-bit binary data are shifted to right.
rotated to bit
c.
Lower 16 bits are rotated to right.
Here LSB is
At this time, LSB
in bit C Is rotated to MSB of lower 16 bits.
(c) SFCNTR(RAM) is used to keep track of number of shifts.
SFCNTR(RAM) is
decremented every time (b) is executed.
(d) Loops (b) to (c) until SFCNTR (RAM) is "0".
/
I
~HITACHI
685
1.1.3 FLOWCHART Format (Format 3)
The FLOWCHART Format is represented in Fig. 4.
flowchart.
9.
HD6301/HD6303 FAMILY
SHIFTING
SHR
FLOWCHART
___ {
Exchanges upper 16 bits with lower 16 bits
in 32-bit binary data.
___ {
Shifts upper 16 bits in 32-bit binary data
to right, and shifts LSB to bit C.
--- {
Exchanges upper 16 bits with lower 16 bits
in 32-bit binary data.
--f
data to right.
Rotates LSB of upper 16 bits
to MSB of lower 16 bi ts.
'-------r---------l ---{
---{
Rotates lower 16 bits in 32-bit binary
Decrements shift counter.
Tests if shift is completed.
I
~HITACHI
687
1.1.4 PROGRAM LISTING Format (Format 4)
The PROGRAM LISTING Format is represented in Fig. 1.5.
Each item
in the format is described using Fig. 1.5.
(1)
~
ITEM NUMBER AND PROGRAM NAME
( 4 )--
PROGRAM LI STING
I
HeU IMPU
11ID6301/1lD6303 FAMILY
I
LABEL
I
I
Fig. 1.5 PROGRAM LISTING Format
(1)
ITEM NUMBER AND PROGRAM NAME }
(2)
MCU/MPU
(3)
LABEL
Same as SPECIFICATION Format
~HITACHI
688
(4)
PROGRAM LISTING
9.
I
SHIFTING 32-BIT DATA
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
Q0015A
00016
OOOl7A
00018
00019A
00020
00021
00022A
00023A
00024A
00025A
00026A
00027A
00028A
00029A
MCU/MPU
11ID6301/1ID6303 FAMILY
I
LABEL
I
SHR
I
PROGRAM LISTING
(al
NAME
SHIFTING 32-8IT DATA
(SHR)
(b) ~:* ole '" "'II< *** "'>Ie'" '" "''''II< "''''''''''lie''''''''''''''''''", "'."''''lI< *********** "'II< "':
~: IX
( l
c
'"
*
~*
RETURNS
IX
~-P-U-S-H-'-(-I-X-)-~
---I
---{
~::::::r:::=:~ - --I
L-(_A_C_C_A_)r-->_~_(
_I_X_]----I
---I
'--_(_1_X_)_+_1->_I_X_---l - - - {
1-(_I_X_)_->_D_ErA_:_D_E_A_+_1...J
PULL
IX
Loads source data into ACCA.
Increments source address.
Saves source address.
Loads destination address into IX.
Transfers data in source area to destination
area.
Increments destination address.
---I
Saves destination address.
---{
Restores source address in IX.
L-..--~---{
---I
Decrements counter indicating byte length
to be moved.
I
Tests if move is completed.
L
R T S
~HITACHI
701
2.
MOVING MEMORY BLOCKS
I
LABEL
I
MOVE
************************************************
'"
'"
NAME : MOVING MEMORY BLOCKS (MOVE)
'"
'"
'"
'*******************~****************************d
"
,.
'"
(SOURCE ADDR)
IX
ENTRY
'"
'"
DEA (DESTINATION ADDR)
'"
'"
ACCB (TRANSFER COUNTER)
'"
'" RETURNS : NOTHING
,.
'"
'"
'"
************************************************
'"
,.
ORG
$80
A DEA
RMB
2
ORG
$FOOO
EQU
LDAA
INX
PSHX
LDX
STAA
INX
STX
PULX
DECB
BNE
RTS
'O.X
"
OOBO
0080
0002
FOOO
FOOO
F002
F003
F004
F006
F008
F009
FOOB
FOOC
FOOD
FOOF
A6
08
3C
DE
A7
08
OF
38
SA
26
39
FOOO
00
'"
'"
A MOVE
A
80
00
A
A
60
A
Fl FOOO
•
702
!lID630l/HD6303 FAMILY
I
PROGRAM LISTING
00001
00002
00003
00004
00005
00006
00007
OOOOB
00009
00010
00011
00012
00013
00014A
00015
00016A
00017
00018A
00019
00020
00021A
00022A
00023A
00024A
0002SA
00026A
00027A
00028A
00029A
00030A
00031A
! MCU/MPU
DEA
O.X
DEA
MOVE
HITACHI
Destination ADDR
Entry point
Load transfer data
Increment source ADDR
Push source ADDR
Load destination ADDR
Store transfer data
Increment destination ADDR
Store destination ADDR
Pull sorce ADDR
Decrement transfer counter
Loop until transfer counter
0
3.
I MCU/MPU I HD630l/HD6303
MOVING STRINGS
I
FUNCTION
ILABEL I MOVES
FMIlLY
(a) Moves data block in memory to RAM.
(b) Terminates moving process when terminator $00 is found in data block.
(c) Permits source and destination addresses to be freely selec ted in memory.
CHANGES IN CPU
REGISTERS AND FLAGS
I
ARGUMENTS
•
Entry
Byte
Lgth.
IX
2
Source
starting
address
Destination
starting
address
Arguments
Storage
Location
I
DESCRIPTION
-
RAM (Bytes)
: Result
2
ACCD
Stack (Bytes)
ACCB
ACCA
•
IX
2
No. of cycles
507
x
2
Reentrant
V
No
•
x
Relocation
Z
N
No
x
x
Interrupt
I
H
Yes
•
•
C
Returns
-
-
1
["
CD
1 Entry
(1) Function Details
F
arguments P~~~~~ff) I
: 0
DfJVl
0
:
in 2-byte hexadecimal number.
Oest in.1t ion ..... $OO~Hl
stArling
;tddre,c:~
DEAS(RAM): Holds destination starting
OEAS
(RAM)
hexade@Result
cimal number.
(b) Fig. 1 shows example of MOVES execution.
If entry arguments are as shown in part
0
I OFASII
:0 I
I • :0 I
0
+
Address space
: Holds source starting address
address in 2-byte
bO
IX
bIS
I
($Fooo)
(a) Argument details
IX
17
: Undefined
x
DEAS(RAH)
ROM (Bytes)
: No t aff ec ted
x
Contents
SPECIFICATIONS
CD of
Fig. 1, data in source ($FOOO) is moved to
destination ($0090) as shown
Sourc .. III ortins"'$r-ooo
nddtells IX
~
$FF
$ 2
(I
I
I
I
} De"i""cio"
data block
~
$FF
$ Z I)
I
I
I
}OOU'
block"" d","
Terminator;
.- indica ting
the end of
~
data block
$H •
$OU
Fig. 1 Example of MOVES execution
I
SPECIFICATIONS NOTES
"No. of cycles" in "SPECIFICATIONS" represents the number of cycles needed, when
terminator is put at the 16th byte.
~HITACHI
703
I
3.
MCU/MPU
MOVING STRINGS
MOVES
HD6301/HD6303 FAMILY
DESCRIPTION
in part(1)of Fig. 1.
When it loads terminator $00, MCU terminates moving
process.
(2) User Notes
(a) Source data block is 64k bytes long or
less.
Last byte contains $00 as
termina tor.
(b) Source data must not contain any $00
function other than terminator.
(c) Holds entry arguments so that source
Address space
Source start~ .. o_~~~~~ __
address
--}
Destination
®
starting
®
}
address
-- _ I<
NAME :
BRANCHING FROM TABLE
(CCASE)
*
*
***************************************************
*
*
ACCA (COMMAND )
ENTRY
*
*
IX
(TABLE ADDR)
*
IX
(MODULE ADDR)
RETURNS
CARRY(C=l:TRUE,CcO:FALES) *
*
*
****************************************************
*
ORG
$FOOO
*
Entry point
A CCASE EQU
*O.X
Command 0+ teble cO? (0 ->
TST
A
FOOO
00
00 F011
00
A
05 FOOD
F3 FOOO
00
CCASl
A
CCAS2
BEQ
CMPA
BEQ
INX
INX
INX
BRA
INX
LOX
SEC
RTS
CCAS2
O.X
CCASl
CCASE
O.X
carry)
Branch 1+ command 0+ table c 0
Commend c command of table?
Brench 1+ sQuel
Increment pointer of table ADDR
Branch CeASE
Increment pointer of table ADDR
Load module ADDR
Set carry bit to "1"
I
~HITACHI
713
5.
I
CONVERTING ASCII LOWERCASE
TNTO TlPPF,Rr.ASF
I HD6301/HD6303 FAMILY 1LABEL I TPR
MCU/MPU
I
FUNCTION
(a) Converts ASCII lowercase data in ACCA into uppercase and loads result into
ACCA.
(b) Utilizes 7-bit ASCII in arguments.
CHANGES IN CPU
SPEC IFICATIONS
ARGUMENTS
REGISTERS AND FLAGS
ROM (Bytes)
: Not affected
I
•
x :
Storage
Location
Contents
t
Byte
Lgth.
Entry
~
ACCA
1
Arguments
Returns
Uppercase
(ASCII)
I
DESCRIPTION
ACCA
11
RAM (Bytes)
0
ACCD
ACCA
Lowercase
(ASCII)
Undefined
: Result
1
j
IX
Stack (Bytes)
ACCB
•
0
No. of cycles
•
17
Reentrant
C
V
Yes
x
x
Relocation
Z
N
Yes
x
x
Interrupt
I
H
•
•
Yes
(1) Function Details
(a) Argument details
ACCA: Holds ASCII lowercase data.
After TPR execution, contains theCD Entry
argument
corresponding uppercase data.
(b) Fig. 1 shows example of TPR execution.
If lowercase
'a' ($61)
is held in ACCA as shown in partG)
@ Return
CD
of Fig. 1.
J
<€)HITACHI
714
bO
ACCA
•
I
I
bO
I
'A' $41
Fig. 1 Example of TPR execution
uppercase 'A' ($41), and the result
SPECIFICATIONS NOTES
b7
I
:
{(,L~wercase)
a $61
1
b7
ACCA
{
ACCA
I • :
(uppercase)
argument
of Fig. 1, it is converted into
is contained in ACCA as shown in part
ACCA
I
5.
CONVERTING ASCII LOWERCASE
INTO UPPERCASE
DESCRIPTION
I
MCU/MPU
I HD630l/HD6303
FAMILY
ILABEL I TPR
I
.
(2) User Notes
Lowercase data should be held into ACCA, otherwise lowercase data is saved and
not converted into uppercase.
(3) RAM Description
RAM is not used during TPR execution.
(4) Sample Application
Subroutine TPR is called after lowercase data is held into ACCA.
WORIn
RMB
I
----- Reserves memory byte for lowercase data.
WORK2
RMB
2
----- Reserves memory byte for uppercase data.
I
I
J
I
I
LDAA
Loads lowercase data into entry argument
WORK I
(ACCA) .
II
JSR
TPR
STAA
WORK2
II
Calls subroutine TPR.
Stores uppercase data (return argument
(ACCA)) in RAM.
I
(5) Basic Operation
(a) A compare instruction (CMP) is used to test if entry argument in ACCA is
lowercase or not.
(b) Entry argument and $DF are ANDed using logical AND instruction (AND), and
lowercase is converted into uppercase by clearing bit 5 of lowercase as
shown in Fig. 2.
(c) If entry argument is other than in lowercase, subroutine TPR does not execute
any operation, and entry argument is saved.
@>HITACHI
715
5.
CONVERTING ASCII LOWERCASE
INTO UPPERCASE
DESCRIPTION
MCU/MPU
I HD6301/HD6303 FAMILY
I LABEL
I
bi t 7 6 5 4 3
2
1
~
~
~
0
~
~
~.J
~
a($61)
0
1
1
0
0
0
0
1
b ( $ 6 2 )
0
1
1
0
0
0
1
0
c($63)
0
1
1
0
0
0
1
1
z($7A)
0
1
1
1
1 0
1
0
A($41)
0
1
0
0
0
0
0
1
B($42)
0
1 0
0
0
0
1
0
C($43)
0
1 0
0
0
0
1
1
0
1
1
1
0
1
0
Lowercase (bit 5="1")
I
'==
Q
Uppercase (bit 5="0")
I
Z($5A)
0
!:::
Fi g. 2 Lowercase and uppercase of 7-bit ASCII
~HITACHI
716
I1!PR
CONVERTING ASCII LOWERCASE
MCU/MPU
TPR
HD630l/HD6303 FAMILY
INTO UPPERCA.~SE~.-__________~________~__________________~____~____~
FLOWCHART
5.
TPR
(ACCA)<'a'
(ACCA»
'z'
Tests if entry argument is within range
of ASCII lowercase 'a' to ASCII
lowercase 'z'.
Clears bit 5 of lowercase and converts
it into uppercase.
I
~HITACHI
717
5.
CONVERTING ASCII LOWERCASE
INTO UPPERCASE
MCU/MPU
I HD6301/HD6303
ILABEL I TPR
************************************************
**
*
NAME : CONVERTING ASCII LOWERCASE INTO
UPPERCASE
(TPR)
*
**
*
*
************************************************
*
ACCA (ASCII LOWERCASE)
ACCA (ASCII UPPERCASE)
*
*
ENTRY
RETURNS
*
ORG
$FOOO
EQU
CMPA
BCS
CMPA
BHI
ANOA
RTS
*lI'a
*
*
*
*
*
************************************************
FOOO
FOOO A *TPR
FOOO
F002
F004
F006
F008
FOOA
81
25
81
22
84
39
61
A
06 FOOA
7A
A
02 FOOA
OF
A
TPR1
TPR1
!I'z
TPR1
Ij$OF
Entry paint
ACCA-'a' ?
Branch If ACCA('a'
ACCA-'z' ?
Branch If ACCA)'z'
Convert Lowercase Into Uppercase
~HITACHI
718
FAMILY
I
PROGRAM LISTING
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013A
00014
00015
00016A
00017A
D0018A
00019A
00020A
D0021A
I
6.
CONVERTING ASCII INTO I-BYTE
HEXADECIMAL
FUNCTION
/ MCU/MPU
/lID6301/HD6303 FAMILY
/ LABEL / NIBBLE
I
(a) Converts ASCII '0' to ' 9' and 'A' to 'F' in ACCA into I-byte hexadecimal
number and loads result into ACCA.
(b) Utilizes 7-bit ASCII in arguments.
CHANGES IN CPU
REGISTERS AND FLAGS
ARGUMENTS
/
•
Storage
Location
Contents
: Not affected
:
I
: Result
Byte
Lgth.
ASCII
ACCA
Arguments
0
•
I
I
Returns
Conversion/not
conversion
bit C
(CCR)
I
0
No. of cycles
28
Reentrant
C
1
V
I
x
Relocation
N
Yes
x
x
Interrupt
I
H
Yes
•
Function Details
(a) Argument details
Yes
Z
f---
I
DESCRIPTION
Stack (Bytes)
ACCB
•
ACCA
20
RAM (Bytes)
ACCD
IX
I-byte
hexadecimal
number
ROM (Bytes)
Undefined
x
ACCA
Entry
SPECIFICATIONS
x
(1)
ACCA: Holds ASCII.
After NIBBLE
execution contains I-byte
hexadecimal number.
bO
ACCA bitC b7 AceA
" I
{(ASCII
argument 'F' $46
Undefined
bitC b7 AeCA
bO
if' ' :j
CD Entry
e
r
:
F
"
(] Returns (AeGA
b:r te hexaarguments dec~mal
number $OF
bit C=l : Shows entry argument was ASCII Fig.
Example
of NIBBLE execution
1
bit C : Shows state when NIBBLE is
(CCR)
executed.
I
other than '0' to '9' or 'A' to 'F' .
bit C=O : Shows subroutine NIBBLE is
executed nomally.
(b) Fig. I shows example of NIBBLE execution. If entry argument is as shown in
partG)of Fig. l, $OF, data converted from ASCII into l-byte hexadecimal
number, is contained in ACCA as shown in partG)of Fig. 1.
SPECIFICATIONS NOTES
I
~HITACHI
719
I
6.
~~~~~6i~LASCII
INTO I-BYTE
I MCU/MPU
~
. HD6301/HD6303 FAMILY
I
LABEL
I NIBBLE
I
DESCRIPTION
'(2) User Notes
Entry argument (ASCII) should be held within range of '0' to '9' or 'A' to
'F', otherwise data in ACCA is destroyed after NIBBLE execution.
(3) RAM Description
RAM is not used during NIBBLE execution.
(4) Sample Application
Subroutine NIBBLE is called after ASCII is held.
WORKI
RMB
I
WORK 2
RMB
I
----- Reserves memory byte for I-digit ASCII.
Reserves memory byte for I-byte hexadecimal
number.
LDM
WORK 1
Loads ASCII into entry argument
(ACCA).
II
JSR
NIBBLE
BCS
SKIP
11----- Calls subroutine NIBBLE.
If ASCII is other than '0' to '9' or 'A'
to 'F', branches to service
STM
WORK2
routine.
Stores I-byte hexadecimal number
(return argument (ACCA) ) in RAM.
SKIP
Service
routine for
ASCII other than
'0' to '9 ' or
, A' to 'F'
~HITACHI
720
6.
CONVERTING ASCII INTO I-BYTE
HEXADECIMAL
MCU/MPU
HD6301/HD6303 FAMILY
NIBBLE
DESCRIPTION
(5) Basic Operation
(a) Bit C, resulting from comparison and subtraction of data in ACCA, is used to
test if the data is within range of '0' to 'F' in ASCII table
(note:
II II blocked
area in table).
(b) Addition continues between '0' and '@' . Then '.' to '@' (note:~cross
hatched area in table) is delected.
(c) In cases other than between '0' and '9' or 'A' and 'F', bit C is set during
(a) or (b) above.
Table 1.
o0
LSD
0
00 1
o1
ASCII Table
1 0 1
0
0
o 000
NUL
DLE
1
o
0 0 1
SOH
DCI
A
Q
2
o
0 1 0
STX
DC2
B
R
8
o
0 1 1
ETX
DC3
•
o1
0 0
EaT
-J)
5
o
1 0 1
ENG
NAK
%
6
o
1 1 0
ACK
SYN
&
7
OIL 1
BEL
ETB
W
B
1 0 0 0
BS
CAN
X
9
1 0 0 1
HT
EM
Y
A
1 0 1 0
LF
SUB
Z
B
1 0 1 1
VT
ESC
c
1 1 0 0
FF
FS
D
1 1 0 1
CR
GS
E
1 1 1 0
SO
RS
11Ll
S[
VS
III
SP
•
C 4
F
1 1 U
C
D
T
E
U
V
I
+
"
/
DEL
~HITACHI
721
6.
CONVERTING ASCII INTO I-BYTE
HEXADECIMAL
MCU/MPU
HD6301/HD6303 FAMILY
FLOWCHART
NIBBLE
Tests if entry argument (ASCII)
is '0' or less.
(bit C)=l
Tests if entry argument (ASCII)
is 'G' or more.
(bit C)=l
Tests if entry argument (ASCII)
is 'A' or more.
bitN=O
'A'to'F'
bi t N = I : ' 0' to '@'
Tes~s if entry argument (ASCII)
is within range of ':' to '@'.
bit C = 0
'0' to '9'
bitC=I:':'to'@'
(bit C)=l
---{
Converts ASCII into I-byte
hexadecimal number.
- - - { Clears bit C•
•
722
HITACHI
6.
CONVERTING ASCII INTO l-BYTE
HEXADEC IMAL
I HD630l/HD6303 FAMILY
ILABEL
I'INIBBLE
I
PROGRAM LISTING
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013A
00014
00015
00016A
OOOl7A
00018A
00019A
00020A
00021 A
00022A
00023A
00024A
00025A
00026A
I MCU/MPU
************************************************
*
*
NAME : CONVERTING ASCII INTO
*
*
I-BYTE HEXADECIMAL (NIBBLE>
*
*
*
*
************************************************
*
*
ENTRY
ACCA (ASCII )
*
*
RETURNS
ACCA
(BINARY
DATA)
*
*
CARRY(C=l;TRUE,C=O;FALES)
*************************************************
*
*
FOOD
ORG
*
EQU
A NIBBLE
FOOD
F002
F004
F006
F008
FOOA
FOOC
FOOE
FOlD
F012
FOl3
80
25
86
25
8B
2A
8B
25
8B
OC
39
FOOO
30
A
OF F013
E9
A
DB FOl3
A
06
04 F010
07
A
03 FOl3
OA
A NIBl
NIB2
SUBA
BCS
ADDA
BCS
ADDA
BPL
AODA
BCS
ADDA
CLC
RTS
$FOOO
*
11'0
NIB2
II$E9
NIB2
116
NIBl
117
NI82
11M
Entry point
ACCA( ASCII code) - '0' ?
Branch if ACCA<'O'
ACCA - 'G' -> ACCA
Branch if ACCA>='G'
Test 'O'_I@' or 'A'-IF'
Branch if ACCA='A'-'F'
Test '0'-'9' or I: '_I@'
Branch i f ACCA=':' - , @ ,
Convert ASCII into binary data
CLear carry
I
~HITACHI
723
7.
I HD630l/HD6303
CONVERTING 8-BIT BINARY DATA I MCU/MPU
INTO ASCII
FAMILY
ILABEL
ICOBYTE
1
FUNCTION
(a) Converts 8-bit binary data in ACCA into two ASCII characters and stores
result in RAM.
(b) Utilizes 7-bit ASCII in arguments.
1
ARGUMENTS
•
Storage
Location
Contents
Entry
CHANGES IN CPU
REGISTERS AND FLAGS
8-bit
binary
data
ACCB
Byte
Lgth.
1
: Not affected
x
: Undefined
I
: Result
2 ASCII
Returns characters
ACCD
2
23
RAM (Bytes)
0
ACCA
ACCB
I
I
Stack (Bytes)
2
No. of cycles
IX
57
Reentrant
Yes
C
V
x
x
Relocation
Z
N
Yes
x
x
Interrupt
I
H
Yes
•
DESCRIPTION
ROM (Bytes)
ACCD
•
Arguments
SPECIFICATIONS
•
I
(1) Function Details
(a) Argument details
ACCB: Holds 8-bit binary data to be
converted into ASCII.
ACCB
b7 ACCU bO
CD Entry
{(8-bit binary) I f' : 3 I
argument
$F3
~
~
ACCD
b15
ACCIl
ACCD: Contains data converted, from
upper and lower 4 bits of
CD Return {0-digit ASCII ~~. : • I .•
.
.
argument 'F'=$46,'3'=$33
8-bit bLnary data Lnto 2 ASCII
bO
: .• I
Fi g. 1 Example of COBYTE execution
characters.
(b) Fig. 1 shows example of COBYTE
execution. If entry argument is as
shown in partCDof Fig. I, data converted from 8-bit binary data into ASCII is
contained to ACCD as shown in part@of Fig. l.
I
SPECIFICATIONS NOTES
"No. of cycles" in "SPECIFICATIONS" represents the number of cycles needed to
convert $AA into ASCII.
~HITACHI
724
7.
CONVERTING 8-BIT BINARY DATA
INTO ASCII
I MCU/MPU
1
HD630l/HD6303 FAMILY
I
LABEL lCOBYTE
1
DESCRIPTION
(2) User Notes
8-bit binary data stored in ACCB is destroyed after COBYTE execution.
If 8-bit binary data in ACCB needs to be retained after COBYTE execution, it
should be saved in memory before execution.
(3) RAM Description
RAM is not used during COBYTE execution.
(4) Sample Application
Subroutine COBYTE is called after 8-bit binary data is held.
WORK 1
RMB
1
----- Reserves memory byte for 8-bit binary data.
WORK 2
RMB
2
----- Reserves memory byte for 2 ASCII characters.
LDAB
WORK 1
Loads 8-bit binary data into
COBYTE
entry argument (ACCB) .
Calls COBYTE subroutine.
II JSR
STD
WORK 2
I~----
Stores 2 ASCII characters (return argument
(ACCD)) in RAM.
I
~HITACHI
725
7.
CONVERTING 8-BIT BINARY DATA
INTO ASCII
I
MCU/MFU
HD630l/HD6303 FAMILY
ILABEL
I COBYTE
I
DESCRIPTION
(5) Basic Operation
(a) 8-bit binary data in ACCB is divided into 4 upper and 4 lower bits.
(b) Divided data is then checked by a comparison instruction (CMF).
$30 is added.
added.
II:
(H
between $00 and $09
blocked area in ASCII table as shown in Table 1),
(C===J in Table
If data is between $OA and $OF
Result is converted into ASCII.
Table 1 ASCII Table
~
LSD
o00
o0 I
oI 0
SP
0
o0
00
NUL
OLE
I
o0
0 1
SOH
DCI
•
oI I
'"iI
I 00
, "-
I 0 I
Q
B
n
o0
10
STX
DC.
a o0
1 1
ETX
OCa
•
o1
0 0
EOT
DC4
0
T
5
o 10
1
ENG
NAK
%
E
U
6
o
1 1 0
ACK
SYN
&
F
7
o
1 1 1
BEL
ETB
-G
IV
8
10 0 0
BS
CAN
H
X
•
1 0 0 1
liT
EM
A
1 0 1 0
LF
SUB
*
B
1 0 1 1
VT
ESC
+
C
1 1 0 0
FF
FS
0
1 1 0 1
en
GS
E
1 1 1 0
SO
RS
F
1111
SI
VS
•
I 10
III
P
A
C
==•
V
Y
Z
K
<
L
"-
M
/
>
N
?
0
~HITACHI
726
If data is
DEL
1), $37 is
7.
CONVERTING 8-BIT BINARY DATA
INTO ASCII
MCU/MPU
HD630l/HD6303 FAMILY
COBYTE
FLOWCHART
___ {
Saves 8-bit binary data
(entry argument).
___ {
Shifts upper 4 bits of 8-bi t binary data
into lower 4 bits.
---{ Converts upper 4 bits into ASCII.
___ {
~tores result of ASCII conversion
l.n ACCA.
___ {
Restores 8-bit binary data
(entry argument).
--- {
Clears upper 4 bits of 8-bit binary
data.
---{ Converts lower 4 bits into ASCII.
Converts entry argument between $00 and
$09 into ASCII.
Tests if data is $09 or less, or $OA
or more.
Converts data between $OA and $OF into
ASCII.
@HITACHI
727
I
7.
CONVERTING 8-BIT BINARY DATA
INTO ASCII
MCU/MPU
I
HD6301/HD6303 FAMILYjLABEL
************************************************
'"
''""
'"
'"
'"
'"
'************************************************
"
'"
'"
ACCB (8-BIT BINARY DATA)
ENTRY
'"
'"
ACCD (2-BYTE ASCII)
RETURNS
'"
''""
'"
************************************************
'"
$FOOO
ORG
FOOO
37
54
54
54
54
8D
17
33
C4
8D
39
CB
C1
23
CB
39
07
OF
01
30
39
02
07
'"
A COBYTE EQU
PSHB
LSRB
LSRB
LSRB
LSRB
BSR
FOOE
TBA
PULB
ANDB
A
BSR
FOOE
RTS
A CONIB ADDB
CMPB
A
BLS
F016
ADDB
A
CONIB1 RTS
FOOO
FOOO
FOOl
F002
F003
F004
F005
F007
F008
F009
FOOB
FOOD
FOOE
F010
F012
F014
F016
NAME : CONVERTING 8-BIT BINARY DATA
INTO ASCII
(COBYTE)
'"
Entry point
Push 8-bit binary data
Shift upper 4 bits to Lower 4 bits
CONIB
Ii$OF
CONIB
Convert upper 4 bits into ASCII
Transfer ASCII to ACCA
PuLL 8-bit binary data
Mask upper 4 bits
Convert Lower 4 bits to ASCII
1i'0
1i'9
CONIB1
1i$07
Convert into ASCII ('0'-'9')
ACCB= '0'-'9' or 'A'-'F' ?
Branch if ACCB='0'-'9'
Convert into ASCII ('A'-'F')
~HITACHI
728
jCOBYTE
J
PROGRAM LISTING
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013A
00014
00015
00016A
00017A.
00018A
00019A
00020A
00021A
00022A
00023A
00024A
00025A
00026A
00027A
00028A
00029A
00030A
00031A
I
8.
COUNTING NUMBER OF LOGICAL
"1" BITS IN 8-BIT DATA
FUNCTION
I
1
1
MCU/MPU
HD6JOl/HD6JOJ FAMILY
1LABEL ·1 HCNT
(a) Counts number of logical "1" bits in 8-bit data in ACCA, and loads
resu1t in ACCB.
(b) Permits easy parity checking.
ARGUMENTS
CHANGES IN CPU
REGISTERS AND FLAGS
I
•
Storage
Location
: Undefined
I
Byte
Lgth.
ACCA
13
RAM (Bytes)
: Result
0
ACCD
ACCA
8-bit
Entry data
ROM (Bytes)
: Not affec ted
x
Contents
SPECIFICATIONS
•
1
Stack (Bytes)
ACCB
0
I
No. of cycles
IX
82
x
Arguments
Reentrant
Number of
Relogical
turns
"1" bits
ACCB
V
x
Relocation
Z
N
Yes
•
1
x
x
Interrupt
I
H
Yes
•
DESr.RIPTION
Yes
C
•
I
(1) Function Details
(a) Argument details
ACCA: Holds 8-bit data whose number
of logical "1" bits is counted.
CD
I
There are 5 number l' s.
ACCB: Contains number of logical "1"
bits in 8-bit data.
(b) Fig. 1 shows example of HCNT execution.
b7
bO
ACCA
ACCA
Entry
{(8-bit
10 1'1.1'1 0 1'1'1 0 1
argument data $76) \
I
CD
If entry argument is as shown in
ACCB
hi,
Return
number
argument $05 of
I
logical "1")
((The
1
b)
ACe"
0
bO
: , I
part(Dof Fig. I, number of logical
"1" bits in 8-bit data is contained
in ACCB as shown in part 00f Fig. 1.
(c) Contents of ACCA are saved after HCNT
execution.
SPECIFICATIONS NOTES
Fig. 1 Example of HCNT execution
I
"No. of cycles" in "SPECIFICATIONS" represents the number of cycles needed to
count number of logical "1" bits in $FF data.
~HITACHI
729
I MCU/MPU I HD630l/HD6303
8.
COUNTING NUMBER OF LOGICAL
"1" BITS IN 8-JUT DATA
DESCRIPTION
FAMILY
ILABEL I HCNT
I
(2) User Notes
When counting number of logical "0" bits, take I's complement of ACCA before
HCNT execution.
(3) RAM Description
RAM is not used during HCNT execution.
(4) Sample Application
Subroutine HCNT is called after 8-bit data is held.
WORI{1
RMB
1
WORK2
RMB
1
----- Reserves memory byte for 8-bit data.
Reverse memory byte for number of logical
"1" bits.
PSHX
Saves register contents that will be
LDAA
'Loads 8-bit data into entry argument
destroyed by executing HCNT.
WORK1
(ACCA).
II
JSR
STAB
PULX
HCNT
II
Calls subroutine HCNT.
Stores number of logical "1" bits
(return argument (ACCB) ) in RAM.
WORK 2
----- Restores register.
(5) Basic Operation
(a) IX is used to indicate number of 8-bit data rotations.
(b) Using rotate instruction (ROL) , data in ACCA is loaded into bit C one by one.
(c) Bit C is checked.
If "1", ACCB is incremented. If "0", no operation applied.
(d) IX is decremented each time (b) and (c) is executed.
(e) Loops (b) to (d) until IX is "0".
~HITACHI
730
8.
COUNTING NUMBER OF LOGICAL
"1" BITS IN 8-BIT DATA
MCU/MPU
H0630l/HD6303 FAMILY
HCNT
FLOWCHART
HeNT
~-----' ---{ 8-bit processing.
Loads "8" in counter for execution of
---{
Clears counter (HI bit counter) that
keeps track of number of logical "1"
bits.
Rotates MSB of 8-bit data to bit C.
'----r-------' ---{
___
{
. 8- b·1t d ata 1S
. "1" or "0".
Tests 1f
--- {
. 1og1ca
. 1 "1",
When 8-bit data 1S
increments HI bit counter.
---{
D,or'~nt' countor.
___ {
L-------r-----' - - - {
I
Tests if 8-bit processing
is completed.
R,"ore, "-bit data.
R T S
~HITACHI
731
8.
COUNTING NUMBER OF LOGICAL
"1" BITS IN 8-BIT DATA
IlID630l/lID6303 FAMILY
************************************************
*
*
*
'"
*
'"
************************************************
'"
'"
NAME
'"
'"
:
COUNTING NUMBER OF LOGICAL "~"
(HCNT)
BITS IN 8-BIT DATA
ENTRY
RETURNS
'"
'"
'"
ACCA (8-BIT DATA)
ACCB (HIGH BIT COUNTER) *'"
*
************************************************
FOOO
'"
A *HCNT
FOOO
F003
F004
FOOs
F007
F008
F009
FOOB
FOOC
FOOO
CE OOOB A
SF
HCNTl
49
24 01 FOOB
SC
HCNT2
09
26 F9 F004
49
39
ORG
$FOOO
EQU
LOX
CLRB
ROLA
BCC
INCB
DEX
BNE
ROLA
RTS
*l=IB
HCNT2
HCNTl
~HITACHI
732
IWEL I HCNT
I
PROGRAM LISTING
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013A
00014
00015
00016A
00017A
0001BA
00019A
00020A
00021A
00022A
00023A
00024A
MCU/MPU
I
Entry point
Set rotate counter
Clear high bit counter
Rotate B-bit data left
Branch if carry=O
Increment high bit counter
Decrement rotate counter
Loop until rotate counter=O
Replace 8-bit data
9.
I MCU/MPU I HD6301/HD6303
SHIFTING 32-BIT DATA
I
FUNCTION
ILABEL I
FAMILY
SHR
(a) Shifts 32-bit binary data in IX and ACCD to right.
(b) Permits number of shifts to be freely determined.
Permits easy multiplication of 32-bit binary data by 2- n . (n:number of shifts)
(c)
I
ARGUMENTS
Storage
Location
Contents
Entry
Upper 16
bits of
32-bit
binary
data to
be shifted to
right
Lower 16
bits of
32-bit
binary
data to
be shifted to
right
Arguments
Returns
CHANGES IN CPU
REGISTERS AND FLAGS
Byte
Lgth.
•
: Not affected
x
:
Undefined
:
Result
I
SPEC IFICATIONS
ROM (Bytes)
11
RAM (Bytes)
1
ACCD
IX
2
ACCA
ACCB
I
I
Stack (Bytes)
0
No. of cycles
IX
261
!
Reentrant
ACCD
2
Number of SFCNTR
(RAM)
shifts
1
Upper 16
bits of
shift
result
IX
2
Lower 16
bi ts of
shift
result
ACCD
2
C
V
No
x
x
Relocation
Z
N
No
x
x
Interrupt
I
H
Yes
•
•
I
I
DESCRIPTION
(1) Func tion Details
(a) Argument details
IX
: Holds upper 16 bits of 32-bit binary data to be shifted to right.
ACCD
After SHR execution, contains upper 16 bits of shift result.
: Holds lower 16 bits of 32-bit binary data to be shifted to right.
After SHR execution, contains lower 16 bits of shift result.
SPECIFICATIONS NOTES
I
"No. of cycles" in "SPECIFICATIONS" represents the number of cycles needed to
shift 32-bit binary data 16 bits right.
~HITACHI
733
9.
SHIFTING 32-BIT DATA
MCU/MPU
HD630l/HD6303 FAMILY
SHR
DESCRIPTION
SFCNTR: Holds number of shifts.
(RAM)
(b) Fig. 1 shows example of SHR execution.
If entry arguments are held as shown
in part (Dof Fig. 1, 32-bit binary data is shifted to right as shown in part
@ of Fig.
{
CD Entry
1.
In this case, "0" in upper 2 bits.
SF~~:~~RAM)
arguments
IX:ACCD
($C91456CF)
b7
I
SFCNTR
0
:
b3l
bO
2
I X
~~~~-r~~~~~~~~~~~~~~~-r~~~~
11 00100
J
b3l
IX
AC C D
bO
® ~::~::ntsl( ~~~ ~~~~ B3) JoI ol1111o 101110101 110101011101110101 011101 1101 111101 11110101 111I
Fig. 1 Example of SHR execution
(2) User Notes
Number of shifts should be held within range of $01 to $lF, otherwise
ACCD and IX become "0".
(3) RAM description
Label
SFCNTR
Description
RAM
b7
bO
I~________________~I
Number of shifts is stored.
~HITACHI
734
9.
I MCU/MPU I HD630l/HD6303
SHIFTING 32-BIT DATA
FAMILY
ILABEL I
SHR
I
DESCRIPTION
(4) Sample Application
Subroutine SHR is called after number of shifts and 32-bit binary data to be
shifted to right are held.
worun
RMB
4 ----------- Reserves memory byte for 32-bit binary data.
WORK 2
RMB
1 ----------- Reserves memory byte for number of shifts.
WORK3
RMB
4 ----------- Reserves memory byte for shift result.
LDAA
WORK 2
STAA
SFCNTR
r----
entry argument (SFCNTR).
LDX
WORK 1
1
Loads 32-bit binary data to be shifted to
LDD
WORK1+2f
1
Stores number of shifts into
right into entry argument (IX, ACCD).
ullL-_J_S_R______S_H_R__-wI'1 ----- Calls subroutine SHR.
STX
STD
WORK 3
WORK3+2
I
Stores shift result (return argument
(IX, ACCD»
in RAM.
I
(5) Basic Operation
(a) Uses l6-bit shift instruction (LSRD) provided in the HD6301/HD6303 FAMILY.
(b) Upper 16 bits in 32-bit binary data are shifted to right.
rotated to bit C.
Lower 16 bits are rotated to right.
Here LSB is
At this time, LSB
in bit C is rotated to MSB of lower 16 bits.
(c) SFCNTR(RAM) is used to keep track of number of shifts.
SFCNTR(RAM) is
decremented every time (b) is executed.
(d) Loops (b) to (c) until SFCNTR (RAM) is "0".
~HITACHI
735
9.
SHIFTING 32-BIT DATA
MCU/MPU
HD6301/HD6303 FAMILY
SHR
FLOWCHART
___ {
Exchanges upper 16 bits with lower 16 bits
in 32-bit binary data.
___ {
Shifts upper 16 bits in 32-bit binary data
to right, and shifts LSB to bit C.
--- {
Exchanges upper 16 bits with lower 16 bits
in 32-bit binary data.
Rotates lower 16 bits in 32-bit binary
data to right. Rotates LSB of upper 16 bits
to MSB of lower 16 bits.
---~
Decrements shift counter.
---{ r""
if ,hift i, comp10 Before
{DCNTIt(ItAM)
execution ("""")
When DECNT is executed,
bit C
4-digit BCD counter completes counting CD Re turn { llCN'rH(llAM)
(ooou)
arguments
up as shown in partCDf'f Fig. l.
I
0 I : I
0
0
o
:
0
I
Fi g. 2 Example of counter overflow
SPECIFICATIONS NOTEsl
~HITACHI
738
10.
1
4-DIGIT BCD COUNTER
MCU/MPU
I HD630l/HD6303
FAMILY
ILABEL 1DECNT
I
DESCRIPTION
(2) User Notes
If counter overflows as shown in Fig. 2, counter is cleared.
(3) RAM Description
Label
Description
RAM
b7
bO
DCNTR
Upper byte
-
}
4-digit BCD councer "
"ored.
Lower byte
L -________________~
(4) Sample Application
WORIn
II
RMB
2
PSHA
PSHB
PSHX
}
JSR
DECNT
BCS
OVER
LDD
STD
WORIn
PULX
PULB
PULA
OVER
DCNTR
Reserves memory byte for result of
counting by 4-digit BCD counter.
Saves register contents that will be
destroyed by DECNT execution.
Calls subroutine DECNT.
II
When BCD counter overflows, branches to
service routine.
} ____ _ Stores result of counting by 4-digit BCD
counter (return argument (DCNTR) in RAM.
} }
-----
Restores register.
Service routine
in case of counter
overflow.
~HITACHI
739
I
10.
4-DIGIT BCD COUNTER
DESCRIPTION
I MCU/MPU I HD6301/HD6303 FAMILY ILABEL I DECNT
I
(5) Basic Operation
(a) IX is used to indicate address of BCD counter and is also used to keep track
of number of addition.
(b) Set bit C for counting "l"s.
(c) Executes (Formula 1) using index addressing mode.
(Bit C is set at the first a-dition.
When a carry is generated after
(Formula 1) execution, bit C is also set.)
o + « DCNTR
- 1 + IX» + (bi t C)
ACCA ------- (Formula 1)
(d) Decrements IX.
(e) Loops addition of upper byte and bit C until IX is "0".
~HITACHI
740
10.
4-DIGIT BCD COUNTER
MCU/MPU
HD630l/HD6303 FAMILY
DECNT
FLOWCHART
DECNT
---{
Loads "2" into pointer indicating address
of 4-digit BCD counter and counter
indicating number of addition.
---{
Bit C is set and ACCA is cleared in
order to count up by 4-digit BCD
counter.
In the first loop, counts up lower 2
digits in 4-digit BCD counter.
In the second loop, adds bit C
to value of upper 2 digits.
---{
Adjust result of addition into decimal
number and stores it in 4-digit BCD
counter DCNTR (RAM).
---{
Decrements pointer indicating address
of 4-digit BCD counter and counter
indicating number of additions.
---{
Tests if counting up
is completed.
I
~HITACHI
741
10.
I MCU/MPU
4-DIGIT BCD COUNTER
************************************************
* NAME : 4-DIGIT BCD COUNTER (DECNT)
*
*
*
*
*
************************************************
**
ENTRY
NOTHING
**
* RETURNS
DCNTR (BCD COUNTER)
*
*
CARRY (C-0;TRUE.C c 1;OVER FLOW) *
*
*
************************************************
OOBO
0002
OOBO
FOOO
FOOO
F003
F004
F006
FOOB
F009
FOOB
FOOC
FOOE
CE
00
B6
A9
19
A7
09
26
39
7F
F6
*
*
ORG
SBO
RMB
2
ORG
SFOOO
EQU
LOX
SEC
A DECNTl LDAA
ADCA
A
DAA
\STAA
A
DEX
F004
BNE
RTS
FOOO
0002
00
7F
*
A*
DCNTR
A DECNT
A
•
742
ILABEL I DECNT
I
PROGRAM LISTING
00001
00002
00003
00004
00005
00006
00007
OOOOB
00009
00010
00011
00012
00013A
00014
OOOlSA
00016
00017A
0001B
00019
00020A
00021A
00022A
00023A
00024A
0002SA
00026A
00027A
0002BA
IlID6301/HD6303 FAMILY
BCD counter
Entry point
Loed ADDR pointer (eddltlon counter)
Set cerry bit
MO
Cleer ACCA
DCNTR-l.X Increment BCD counter
Convert Into BCD
DCNTR-1.X Store BCD counter
Decrement ADDR pointer
DECNTl
Loop until ADDR pointer c 0
*M2
HITACHI
11.
COMPARING 32-BIT BINARY DATA
I
I HD6301/HD6303 FAMILY ILABEL I
MCU/MPU
CMP
I
FUNCTION
(a) Determines larger than / smaller than relationship ( >,=,<) of 32-bit binary
data of 2 groups, and loads result into bit C and bit Z of CCR.
(b) Utilizes unsigned integers in arguments.
I
ARGUMENTS
CHANGES IN CPU
REGISTERS AND FLAGS
SPECIFICATIONS
Not affected
ROM (Bytes)
.:
x : Undefined
Storage
Location
Contents
Byte
Lgth.
!:
9
RAM (Bytes)
Result
4
Upper 16
bits of
First
value
Lower 16
bits of
Entry First
Arguvalue
ments
Second
value
-r
DESCRIPTION
ACCD
IX
2
ACCA
•
•
IX
ACCD
CMT
(RAM)
CompaReturns rison
result
Stack (Bytes)
bit C
bit Z
(CCR)
2
4
1
0
ACCB
•
No. of cycles
20
Reentrant
No
C
V
Relocation
I
x
No
Z
N
Interrupt
I
x
Yes
I
H
•
•
I
(1) Function Details
(a)
Argument details
IX
: Holds upper 16 bits of the first 32-bit binary value.
ACCD: Holds lower 16 bits of the first 32-bit binary value.
CMT : Holds the second 32-bit binary value.
(RAM)
bit C, bit Z: Bit C and bit Z of CCR are contains according to comparison result.
(CCR)
(b) Table 1 shows example of CMP execution.
If entry arguments are as shown in Table 1, bit C and bit Z of CCR are set
accordingly.
SPECIFICATIONS NOTES
I
"No. of cycles" in "SPECIFICATIONS" represents the number of cycles needed
when comparand and comparative number are equal.
~HITACHI
743
11.
COMPARING 32-BIT BINARY DATA
I MCU/MPU I HD630l/HD6303 FAMILY ILABEL I
I
DESCRIPTION
(c) After CMP execution, entry arguments are retained.
Example of CMP execution
Table 1.
Entry arguments
First value
IX:ACCD
Return argument
CCR
Second value
Large / small
relationship
CMr :CMr+l :CMr+2 :CMr+3
Bit C
Bit Z
$F2FDC621
>
$101F17DA
0
0
$20012002
co
$20012002
1
$4F7B563D
<
$D677FBAC
0
1
0
(2) User Notes
When not using upper byte, the upper byte should be held to "0", otherwise
comparison result will not correct, because comparison is performed with
undefined data in the upper byte.
(3) RAM Description
Label
Description
RAM
b7
bO
Upper byte
CMr
I-
-
-
-
-
Lower byte
-
The second 32-bit binary value
is stored.
~HITACHI
744
CMP
11.
COMPARING 32-BIT BINARY DATAl
MCU/MFU
I HD6301/HD6303
FAMILY
I LABEL
1
CMF
I
DESCRIPTION
(4) Sample Application
Subroutine CMF is called after the first value and the second value are held.
WORKl
RMB
4
Reserves memory byte for the first
WORK 2
RMB
4
Reserves memory byte for the second
32-bit binary value.
32-bit binary value.
LDD
STD
}
LDD
~~~2+2
STD
CMT+2
LDX
WORKl
}
WORKl+2
LDD
II
WORK2
Loads the first 32-bit binary value
into entry argument (IX, ACCD).
Calls subroutine CMF.
JSR
BEQ
Stores the second 32-bit binary value
into entry argument (CMT).
SKIP2
Branches to service routine in case of
SKIPl
Branches to service routine in case of
first value=second value.
BCC
first value>second value.
Service routine in case of
first valuesecond value.
User program
~HITACHI
745
11.
COMPARING 32-BIT BINARY DATA
DESCRIPTION
I MCU/MPU I HD6301/HD6303 FAMILY ILABEL I CMP
I
(5) Basic Operation
(a) Uses 16-bit comparison instruction (CPX) comparing IX with 2-byte memory,
provided in the HD6301/HD6303 FAMILY.
(b) Bit C and bit Z of CCR are determined as return argument, after 16-bit
comparison instruction (CPX) is executed.
(c) Upper 16 bits are compared using 16-bit comparison instruction (CPX).
When equal, lower 16 bits are compared.
When not equal, subroutine CMP is terminated.
~HITACHI
746
11.
COMPARING 32-BIT BINARY DATA
MCU/MPU
CMP
HD630l/HD6303 FAMILY
FLOWCHART
CMP
CDO;lo(CMf:CMf+l)
lower
- - - { Compares lower 16 bits.
--- {
Exchange's lower 16 bits with upper
16 bits of the first value.
CMPI
RTS
I
~HITACHI
747
11.
COMPARING 32-BIT BINARY DATA
PROGRAM LISTING
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014A
00015
00016A
00017
00018A
00019
00020
00021A
00022A
00023A
00024A
0002SA
00026A
I
MCU/MPU
I
HD6301/HD6303 FAMILY
LABEL
I
I
************************************************
** NAME: COMPARING 32-BIT BINARY DATA (CMP) **
*
*
************************************************
**
**
ENTRY
IX
(UPPER 16-BIT COMPARANO)
*
ACCD (LOWER 16-BIT COMPARANO)
*
*
CMT (32-BIT COMPARATIVE NUMBER) *
*
0080
0080
FOOO
FOOO
F002
F004
FOOS
F007
F008
RETURNS: CARRY & BIT Z (COMPARISON RESULT)
*
*
*
************************************************
*
$80
ORG
*
Comparative number
CMT
RMB
4
0004 A
*
ORG
$FOOO
*
EQU
Entry point
FOOO A CMP
*
Compare IX with CMT+2:CMT+3
9C 80
A
CPX
CMT
26 04 F008
18
9C 82
A
18
CMP1
39
BNE
XGOX
CPX
XGDX
RTS
CMP1
CMT+2
~HITACHI
748
I
Branch if IX equal CMT+2: CMT+3
Exchange ACCD & IX
Compare IX with CMT:CMT+1
CMP
12.
ADDING 32-BIT BINARY DATA
I
FUNCTION
I MCU/MPU I HD6301/HD6303
FAMILY
ILABEL I
ADD
(a) Performs addition of 32-bit binary number and loads addition result into IX
and ACCD.
(b) Utilizes unsigned integers in arguments.
I
ARGUMENTS
CHANGES IN CPU
REGISTERS AND FLAGS
.:
Not affected
SPECIFICATIONS
ROM (Bytes)
X : Undefined
Storage
Location
Contents
Upper 16
bits of
augend
Lower 16
Entry bits of
augend
Returns
t : Result
9
RAM (Bytes)
4
IX
ACCA
4
Upper 16
bits of
addition
result
IX
2
Lower 16
bi ts of
addition
result
ACCD
Carry or
no carry
Bit C
(CCR)
0
ACCB
t
2
ACCD
Stack (Bytes)
ACCD
2
ADER
(RAM)
Addend
Arguments
Byte
Lgth.
t
No. of cycles
IX
19
t
Reentrant
No
2
C
V
Relocation
l
x
No
Z
N
Interrupt
x
x
Yes
I
H
•
1
x
I
I
DESCRIPTION
(1) Function Details
(a) Argument details
IX
: Holds upper 16 bits of augend.
bits of addition
After ADD execution, contains upper 16
r~su1t.
ACCD: Holds lower 16 bits of augend.
After ADD execution, contains lower 16
bits of addition result.
ADER: Holds 32-bit binary addend.
(RAM)
PECIFICATIONS
-----_.. _-- NOTES
I
~HITACHI
749
12.
I MCU/MPU IHD630l/HD6303 FAMILY
ADDING 32-BIT BINARY DATA
ILABEL I ADD
I
DESCRIPTION
bit C (CCR)
Indicates whether carry is generated or not after ADD
execution.
bit C
=1
: Carry is generated in addition result.
(see Fig. 2)
bit C = 0 : No carry is generated in addition result.
(b) Fig. 1 shows example of ADD execution.
If entry arguments are as shown in
partCDof Fig. 1, addition result is contained in IX and ACCD as shown in
part ®of Fig. 1.
~
b3l
A
I
Entry
IX
1
0
ADER
{
arguments
1
+)
® Return
{
arguments
:
: I
A
8
:
:
6
ADERH
D
D
:
:
1 C
bO
ACCD
D 1 F
ADERt2
2
C
2
1_ Augend
ADERts
1
F
1- Addend
:
bitCFb~3~1-r__~ITX~~__~~__r-~A~CTC~D~~~b~0
o1
B
:
11
B
Fig.
:
3
F
A
11
..
1_ !::~~ ~on
1
Example of ADD execution
(2) User Notes
(a) As shown in Fig. 3, when not using
F
upper byte, the upper byte should be
:
A
B :
F
I
:
0
c :
B
+)
bi t
I •: I
I •: I
I
D :
I
I
I ,:•I
:
F :
F
I
0
I
I
I
Carry
Fig. 2 Example of addition when
addition is performed with undefined
carry is generated.
data in the upper byte.
(b) After ADD execution, augend is
destroyed because addition result
is contained in IX and ACCD.
If
augend needs to be retained after
ADD execution, it should be saved
in memory before execution.
$
750
c£:QS
c
I
held to "0", otherwise addition
result will not be correct, because
:•I o:
:
:
bit c01 :
0
0
I
0
0
0
I
0
0
0
I
0
+)
:
:
:
:
0
I
I
0
I
F :
I
I
F
I •:D I
D
I • :•I
:c I •:
0
I
Fig. 3 Example of addition when
upper byte is not used.
HITACHI
12.
ADDING 32-BIT BINARY DATA
I
MCU /MPU
I HD6301/HD6303
FAMILY
I LABEL I
ADD
I
DESCRIPTION
(3) RAM Description
Label
Description
RAM
bO
b7
Upper byte
ADER
-
f--
-
f-f--
Lower byte
32-bit binary addend is stored.
(4) Sample Application
Subroutine ADD is called after augend and addend are held.
WORK 1
RMB
4
-----
WORK 2
RMB
4
-----
Reserves memory byte for 32-bit binary
augend.
Reserves memory byte for 32-bit
4
-----
binary addend.
Reserves memory byte for 32-bit
RMB
WORK 3
binary addition result.
I
I
I
I
I
I
I
I
I
LDD
STD
LDD
STD
LDX
LDD
WORK 2
ADER
WORK 2+2
ADER+2
JSR
AD
__D
__--u11
OVER
"
STX
STD
entry argument (ADER).
Loads 32-bit binary augend into
WORKI
}
WORK 1+2
entry argument (IX, ACCD) .
-----
Calls subroutine ADD.
----- If carry is generated in addition result,
branches to service routine.
WORK3
Stores addition result (return arguments
WORK3+2 J
(IX,ACCD» in RAM.
UL_________
BCS
}-----
Stores 32-bit binary addend into
1-----
I
I
OVER
routine
Il.n~ervice
case of carry
I
I
I
I
I
I
I
I
I
~HITACHI
751
I
12.
ADDING 32-BIT BINARY DATA
I
MCD /MPD
1 HD630l/HD6303 FAMILY
ILABEL I
ADD
I
DESCRIPTION
(5) Basic Operation
(a) Uses l6-bit addition instruction (ADDD) provided in the HD630l/HD6303 FAMILY.
(b) (Formula 1) shows addition of lower 16 bits using 16-bit addition instruction
(ADDD).
When carry is generated after performing (Formula 1), bit C is set.
-. ACCD ------- (Formula 1)
(ACCD) + (ADER+2:ADER+3)
(c) Upper 16 bits are added using 8-bit addition instruction shown in (Formula 2)
and (Formula 3) (ADC) considering bit C.
(ACCB) + (ADER+l) + (bit C)
ACCB --------- (Formula 2)
(ACCA) + (ADER) + (bit C)
ACCA --------- (Formula 3)
Bit C is taken into consideration because there is carry involved with the
addition result by executing (b).
~HITACHI
752
12.
ADDING 32-BIT BINARY DATA
MCU/MPU
HD6301 /HD6303F AMILY
ADD
FLOWCHART
---{
---{
Adds lower 16 bits and loads addition result
into augend (ACCD).
Exchanges lower 16 bits of addition result
with upper 16 bits of augend.
Adds upper 8 bits considering carry
which is generated by lower l6-bits
addition, and stores result in addend
for upper 16 bits area.
---{
Exchanges upper 16 bits with lower 16 bits of
addition result.
I
~HITACHI
753
12.
ADDING 32-BIT BINARY DATA
I
PROGRAM LISTING
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016A
00017
0001SA
00019
00020A
00021
00022
00023A
00024A
0002SA
00026A
00027A
0002SA
I
MCU/MPU
I HD6301/HD6303
ILABEL I
************************************************
OOSO
0080
0004
FOOD
FOO~
F002
F003
FOOS
F007
FOOS
FOOD
03 S2
18
09 81
99 SO
lS
39
'"
'"
NAME : ADDING 32-BIT BINARY DATA (ADD)
'"
'"
'"
************************************************'"
'"
'"
ENTRY
(UPPER 16-BIT AUGEND)
IX
'"
'
(LOWER
16-BIT
AUGEND)
ACCD
'""
'"
ADER (32-BIT ADDEND)
'"
'"
(UPPER 16-BIT SUM)
IX
'"
''"" RETURNS ACCD
(LOWER 16-BIT SUM)
'"
CARRY(C=O;TRUE.C=l;OVER FLOW)
'"
'"
'"
'"
************************************************
'"
$SO
ORG
'
"
RMB
4
Addend
A ADER
'"
$FOOO
ORG
"
EQU
Entery point
A 'ADD
'ADER+2
"
A
Add ACCD and ADER+2:ADER+3
ADDD
A
A
XGDX
ADCB
ADCA
XGDX
RTS
ADER+l
ADER
~HITACHI
754
FAMILY
Exchange
Add ACCB
Add ACCA
Exchange
ACCD & IX
and ADER+l
and ADER
ACCD & IX
ADD
13.
SUBTRACTING 32-BIT BINARY
DATA
FUNCTION
I
I MCU/MPU I HD6301/HD6303
FAMILY
ILABEL I
SUB
(a) Performs subtraction of 32-bit binary data and loads subtraction result
into IX and ACCD.
(b) utilizes unsigned integers in arguments.
I
ARGUMENTS
CHANGES IN CPU
REGISTERS AND FLAGS
•
: Not affected
x :
Storage
Location
Contents
Upper 16
bits of
minuend
Lower 16
Entry bits of
minuend
Subtrahend
Upper 16
bits of
subtraction
result
Arguments
Returns
Byte
Lgth.
t
SPECIFICATIONS
ROM (Bytes)
Undefined
9
RAM (Bytes)
: Result
4
IX
ACCD
SBER
(RAM)
IX
2
2
4
Stack (Bvtes)
ACCD
ACCA
ACCB
t
t
0
No. of cycles
IX
19
~
Reentrant
No
2
Lower 16
bits of
subtraction
result
ACCD
2
Borrow or
no borrow
bit C
(CCR)
1
C
V
Relocation
t
x
No
Z
N
Interrupt
x
x
Yes
I
H
•
•
I
I
DESCRIPTION
(1) Function Details
(a) Argument details
IX
: Holds upper 16 bits of minuend.
Contains upper 16 bits of subtraction
result after SUB execution.
ACCD: Holds lower 16 bits of minuend.
Contains lower 16 bits of subtraction
result after SUB execution.
SBER: Holds 32-bit binary subtrahend.
(RAM)
SPECIFICATIONS NOTES
I
~HITACHI
755
13.
SUBTRACTING 32-BIT BINARY
DATA
DESCRIPTION
I MCU/MPU
I HD630l/HD6303
FAMILY
ILABEL
I SUB
1
bit C (CCR): Indicates whether borrow is generated or not after SUB execution.
bi t C
Borrow is generated in subtraction result.
= 1
(see Fig. 2)
bit C
0 : No borrow is generated in subtraction result.
=
(b) Fig. 1 shows example of SUB execution.
If entry arguments are as shown in
partCDof Fig. 1, subtraction result is contained in IX and ACCD as shown
in part 00f Fig. 1.
CD
b3l
:~~~~ents{
o arguments
Return
{
bO
ACCD
IX
_F__'--C-.JI~9---,:__3---L1__
6--L__
C--LI__
D-,-__
A--lI-
LI
SBER
SBER+ 1
SBER+Z
Mi nuend
SBER+a
--L:~B=--L..:.A.:..........:_5---L1_5--,-:_A~I- Subtrahend
E
C---L_
_6--1:--,:,
L...I
--~)------------------------------------bit C b3l
01
8
:
F
1 A
bO
o
ACCD
IX
C
7
8
1
1- Subtrac tion
:
result
Fig. 1 Example of SUB execution
(2) User Notes
(a) When subtraction result is negative,
(Minuend ·I.;'.I-Multi~
MJ:II MEIHI
x)
1.
RI
b3l
P l.er
\bI Return {
PIIIlCT(IIA.\I)
bO
arguments ($13B"."C) 11:a IB;'1-:, I,:c I~ Product
contained in PRDCT (RAM) as
shown in part®of Fig. 1.
},lOn "WCT'I 1'1U1C'T'2 rIllCT,,1
(c) Table 1 shows result when "0" is
Fig. 1 Example of MUL execution'
held as entry arguments.
Table 1. Product when holding "0" as entry arguments
Return argument
Entry arguments
Multiplicand
(MCAND :MCAND+ 1 )
,*
Multiplier
(MER:MER+l)
o
Product
(PRDCT:PRDCT+l:PRDCT+2:PRDCT+3)
000
$ 0 0 0 0 0 000
$ 000 0
$ * * * * *1
$ 0 0 0 0 0 000
$ o 0 0 0
$ 000 0
$ 0 0 0 0 000 0
$
* * * *1
$
(NOTE) *1
$**** indicates hexadecimals
(2) User Notes
(a) As shown in Fig. 2, when not using
upper byte, the upper byte should
be held to "0", otherwise product
10:0 I F:AI-Multiplicand
~x~)____~I~o=:o=I='=:B=I~-Multiplier
will not be correct, because
multiplication is performed with
undefined data in the upper byte.
10:010;'1,:·lo:EI-Product
Fig. 2 Multiplication example when
upper byte is not used
..
~HITACHI
762
14.
MULTIPLYING l6-BIT BINARY
DATA
DESCRIPTION
I MCU/MPU I HD630l/HD6303
FAMILY
ILABEL I
MUL
J
(3) RAM Description
Label
bO
b7
Upper byte
MCAND
t--
MER
Description
RAM
Lower byte
-
} 16-bi< binary multiplicand is stored.
-
} 16-bi , binary multiplier is stored.
Upper byte
-
Lower byte
Upper byte
PRDCT
t--
-
t--
-
32-bit binary product is stored.
-
t--
Lower byte
I
~HITACHI
763
14.
MULTIPLYING l6-BIT BINARY
DATA
DESCRIPTION
I MCU/MPU
I HD630l/HD6303 FAMILY
ILABEL I MUL
I
(4) Sample Application
Subroutine MUL is called after multiplicand and multiplier are held.
WORK 1
RMB
2
Reserves memory byte for l6-bit binary
multiplicand.
WORK 2
RMB
2
Reserves memory byte for l6-bit binary
multiplier.
WORK 3
RMB
4
Reserves memory byte for product.
PSHA
PSHB
STD
LDD
WORKl
MCAND
WORK 2
STD
MER
JSR
MUL
LDD
II
)
}
}
II
LDD
STD
PRDCT
LDD
::~:+2
STD
WORK 3+2
PULB
PULA
Saves register contents that will be
destroyed by MUL execution.
Stores l6-bit binary multiplicand into
entry argument (MCAND).
Stores l6-bit binary multiplier into
entry argument (MER) .
Calls subroutine MUL.
1
Stores 32-bit binary product
(return argument (PRDCT))
in RAM.
)-----
Restores register.
~HITACHI
764
14.
I MCU/MPU I HD630l/HD6303
MULTIPLYING l6-BIT BINARY
DATA
FAMILY
ILABEL
I
MUL
I'
DESCRIPTION
~--------------~
(5) Basic Operation
(a) Uses 8-bit binary multiplication instruction (MUL) provided in the HD6301/
HD6303 FAMILY.
(b) Multiplication of l6-bit binary data is executed by obtaining partial products
(as shown in Fig. 3 Q)
, CD, G) and ®),
I
and
adding them to product (Fig. 3 (£»
.
II MCAND+1 1----- Multiplicand
R II ME R+ 11----- Multiplier
M CAN D
1M
E
x)
(MCAND) x (MER+1)
-----®
(MCAND+1)x(MER)
-----®
Partial products
(MCAND)x(MER)
P RDCT
-----@
IPRDCT+1 II PRDCT+2 IPRDCT+3
-----@
Product (=(!)+®+®+@)
Fig. 3 Multiplication
I
~HRTACHI
765
MULTIPLYING 16-BIT BINARY
DATA
FLOWCHART
I
14.
I MCU/MPU I HD6301/HD6303
FAMILY
ILABEL I
MUL
Clears RAM for product.
Obtains partial product, that is, (lower byte of
mUltiplicand) x (lower byte of multiplier),
and stores it in RAM for product.
Requires partial product of
(upper byte of multiplicand) x
(lower byte of multiplier).
Adds partial product and stores it in RAM
for product.
Requires partial product of
(lower byte of multiplicand) x
(upper byte of multiplier)
Adds partial product and stores it in RAM
for product.
As carry may be generated, executes carry
process.
Requires partial product of
(upper byte of multiplicand) x
(upper byte of multiplier)
Adds partial product and stores it in RAM
for product.
~HITACHI
766
14.
I MCU/MPU I HD6301/HD6303
MULTIPLYING 16-BIT BINARY
DATA
ILABEL
I
PROGRAM LISTING
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013A
00014
00015A
00016A
00017A
00018
00019A
00020
00021
00022A
00023A
00024A
00025A
00026A
00027A
00028A
00029A
00030A
00031A
00032A
00033A
00034A
00035A
00036A
00037A
00038A
00039A
00040A
00041A
00042A
00043A
00044A
00045A
FAMILY
I
MDL
************************************************
,.
,.
'" NAME : MULTIPLYING 16-BIT BINARY DATA
(MUl) ''""
'"
'"
'"
ENTRY
MCAND (MULTIPLICAND)
'"
'"
(MUL TIPLIER)
MER
'"
'"
RETURNS
PRDCT (PRODUCT)
'"
"
'"
************************************************'"
'"
$80
ORG
'
"
MuLtipLicand
A MCAND RMB
2
************************************************
0080
0080
0082
0084
0002
0002
0004
FOOO
'"
"
A 'MUL
84
81
83
A
A
A
86
80
83
A
A
A
85
85
96 81
D6 82
3D
03 85
DO 85
79 0084
96 80
06 82
3D
03 84
DD 84
39
A
A
A
A
FOOO
FOOO
FOOl
F002
F004
F006
F008
F009
FOOS
FOOD
FOOF
F010
F012
F014
F016
F018
F019
F01S
FOlD
F020
F022
F024
F025
F027
F029
A MER
A PRDCT
4F
SF
DO
96
D6
3D
DD
96
D6
3D
D3
DD
A
A
A
A
A
A
A
MuLtipLier
Product
RMB
RMB
2
4
ORG
$FOOO
EQU
CLRA
CLRB
STD
LDAA
LDAB
MUL
STD
LDAA
LDAS
MUL
ADDD
STD
LDAA
LDAB
MUL
ADDD
STD
ROL
LDAA
LDAS
MUL
ADDD
STD
RTS
'"
Entry point
CLear product area
PRDCT
MCAND+l
MER+1
(MCAND+l) '" (MER+1) -) PRDCT
PRDCT+2
MCAND
MER+1
(MCAND) '" (MER+l) -) ACCD
PRDCT+l
PRDCT+l
MCAND+l
MER
ACCD + (PRDCT) -) PRDCT
PRDCT+l
PRDCT+1
PRDCT
MCAND
MER
ACCD + (PRDCT) -) PRDCT
PRDCT
PRDCT
ACCD + PRDCT -) PRDCT
(MCAND+1) '" (MER) -) ACCD
(MCAND) '" (MER) -) ACCD
I
~HITACHI
767
15.
DIVIDING l6-BIT BINARY DATA
I
FUNCTION
I
I MCU/MPU I
HD630l/HD6303 FAMILY LABEL
I
DIV
(a) Performs divisions of l6-bit binary data and stores result (quotient and
residual) in l6-bit binary.
(b) Stores dividend and divisor in IX and RAM.
(e) Utilizes unsigned integers in arguments.
I
ARGUMENTS
CHANGES IN CPU
REGISTERS AND FLAGS
: Not affected
SPEC IFICATIONS
•
ROM (Bytes)
;
RAM (Bytes)
x : Undefined
Storage
Byte
Location Lgth.
Contents
: Result
25
3
Dividend
IX
ACCD
2
ACCA
Entry
Divisor
DVS
(RAM)
2
1
ACCB
t
476
Reentrant
IX
;
Arguments
Quotient
IX
Residual
ACCD
No
2
Returns
2
C
V
Relocation
x
x
No
Z
N
Interrupt
x
x
Yes
I
H
•
DESCRIPTION
Stack (Bytes)
0
No. of cycles
x
I
(1) Function Details
(a) Argument details
IX: Holds 16-bit binary dividend. Contains quotient after DIV execution.
DVS (RAM): Holds 16-bit binary divisor.
ACCD: Contains 16-bit binary residual.
e
SPECIFICATIONS NOTES
I
~HITACHI
768
15.
I MCU/MPU I HD630l/HD6303 FAMILY
DIVIDING l6-BIT BINARY DATA
I
DESCRIPTION
DIV
ILABEL
@ Return
arguments
(b) Fig. 1 shows example of DIV execution.
blS
If entry arguments are as shown in
bO
blS
bO
1,,:01 0 :.1 ... 10 :1'1,,:1>1
partCDof Fig. 1, division result
IX
($000.)
is contained in IX and ACCD as shown in
blS
bO )blS
[!"":!iJ1i:oJ
part@ of Fig. l.
DVS DVS+l
($1000)
(c) Table 1 shows result when "0" is held
A('('I>
($" F"ll)
a:x bO1
14 >. 1
II
I
($4F3D)
CD Entry' arguments
as entry arguments.
Fig. 1 Example of DIV execution
Table 1 Result when holding "0" as entry arguments
Entry arguments
Dividend (IX)
$ * * * * *
$
o
0 0 0
$ 000 0
Return arguments
Divisor (DVS)
$ 0 0
o
o
Residual (ACCD)
$ F F F F
$ * * * * *
0
$ * * * *
$ 0
Quotient (IX)
*
0 0
$
o
0 0 0
$ F F F F
$ 000 0
$
o
0 0 0
(NOTE) * $**** indicates hexadecimals.
(2) User Notes
(a) When not using upper byte as shown in
I
Fig. 2, the upper byte should be held
to "0", otherwise division result
will not be correct, because division
is performed with underfined data
in the upper byte.
(b) After DIV execution, dividend is
destroyed because quotient is contained
in IX.
If dividend needs to be
Fig. 2 DIV example when upper
byte is not used
retained after DIV execution, it
should be saved in memory before
execution.
~HITACHI
769
15.
DIVIDING l6-BIT BINARY DATA
I MCU/MPU
I HD630l/HD6303 FAMILY ILABEL IIHV
I
DESCRIPTION
(3) RAM Description
Label
Description
RAM
bO
b7
Upper byte
DVS
-
f--
Lower byte
DICNTR
(4) Sample
I
l6-bit binary divisor is stored.
Dividend shift counter is stored.
Appli~ation
Subroutine DIV is called after dividend and divisor are held.
worun
2
Reserves memory byte for 16-bit binary
2
dividend.
Reserves memory byte for 16-bit binary
RMB
2
divisor.
Reserves memory byte for 16-bit binary
RMB
2
RMB
RMB
WORK 2
WORK3
quotient.
WORK 4
Reserves memory byte for 16-bit binary
residual.
I
I
I
WORK 1
Loads l6-bit binary dividend into
STD
WORK2 }
DVS
Stores l6-bit binary divisor into
JSR
DIV
STX
WORK3} _____ Stores division result in RAM.
WORK 4
LDX
entry argument (IX).
LDD
II
STD
II
entry argument (DVS).
Calls subroutine DIV.
~HITACHI
770
15 .. DIVIDING l6-BIT BINARY DATA
I MCU/MPU
I HD630l/HD6303 FAMILY ILABEL
I DIV
I
DESCRIPTION
(5) Basic Operation
(a) In binary code divison, quotient and residual are obtained by repeated
subtraction.
Fig. 3 shows example of division ($OD 7 $03).
®®
Divisor
--+
1
Quotient
Dividend
·.... ·CD
...... ®
1
0
0
+--
1
1
0
1
+--
-) 1
1
d
-)
-
+)
0
0
1
1
...... @
0
1
...... ®
1
1
...... 0)
0
0
1
1
1
-)
-
+)
0
1 0
1
1
0
1
+--
Residual
Fig. 3 Division example ($00
7
$03)
(b) Refering to Fig. 3, the program is explained as follows:
(i) Loads number of shifts in shift counter (DICNTR) and clears ACCD in
which residual will be loaded.
(ii) Shifts dividend (IX) and ACCD left 1 bit, then shifts MSB of IX to LSB of
ACCD.
This is because when performing subtraction, the upper bits are
fetched one by one from dividend.
(iii) Subtracts divisor (DVS:DVS+l) from ACCD.
If subtraction result is
positive, sets LSB of IX to "1".
(Fig. 3
®-@--G».
If subtraction result is negative, clears LSB of IX, adds divisor to
subtraction result and restores the pevious subtraction result.
(Fig. 3
G>-®-0.
(iv) Decrements shift counter.
(v) Loops (ii) to (iv) until shift counter is "0".
~.----------------------------------------------~
~HITACHI
771
I
15.
DIV
MCU/MPU
DIVIDING l6-BIT BINARY DATA
FLOWCHART
D I V
___ { Loads number of shifts into shift
counter.
___ {
Clears work area where division
result will be stored.
Shifts MSB of dividend to LSB of
Shift (ACCD)
1 bit left
work area.
(ACCD)-( IX)
Rotate (ACCD)
1 bit left
---~
Subtracts divisor from work area.
___ {
Sets LSB of IX to "1" where residual
will be stored.
___ {
Tests if subtraction result is
positive.
___ { Adds divisor to subtraction result
and returns contents of work area.
___ {
Clears LSB of IX where residual
will be stored.
___ {
(DICNTR)+0
Decrements shift counter.
---{: Te't' if ,hift i, oompleted.
R
$
772
HITACHI
15.
DIVIDING 16-BIT BINARY DATA
MCU/MPU
I
HD6301/HD6303 FAMILY
ILABEL I
DIV
I
PROGRAM LISTING
00001
00002
00003
00004
00005
00006
00007
OOOOS
00009
00010
00011
00012
00013
00014A
00015
00016A
00017A
0001S
00019A
00020
00021
00022A
00023A
00024A
00025A
00026A
00027A
0002SA
00029A
00030A
00031A
00032A
00033A
00034A
00035A
00036A
00037A
00038A
I
************************************************
*
OOSO
OOSO
00S2
0001
A DICNTR RMB
*
FOOO A *DIV
FOOO
FOOO
F002
F004
FOOS
F006
F007
FOOS
F009
FOOA
FOOB
FOOD
FOOE
F010
F012
F013
F016
F01S
*
* NAME : DIVIDING 16-BIT BINARY DATA (DIV) *
*
*
************************************************
**
ENTRY
IX
(DIVIDEND)
**
*
DVS (DIVISOR)
*
*
RETURNS
ACCD (QUOTIENT)
*
*
IX
(RESIDUAL)
*
*
*
************************************************
*
ORG
$SO
*
Divisor
RMB
2
0002 A DVS
S6
97
4F
SF
lS
05
lS
59
49
93
08
24
D3
09
7A
26
39
10
S2
A
A
DIV1
80
A
03 FOl3
SO
A
00S2 A DIV2
EE F006
1
ORG
$FOOO
EQU
LDAA
STAA
CLRA
CLRB
XGDX
ASLD
XGDX
ROLB
ROLA
SUBD
INX
BCC
ADDD
DEX
DEC
BNE
RTS
*1=116
DICNTR
Shift counter
Entry point
Set shift counter
Clear work (Set quotient afterword)
Shift dividend and set MSB of-dividend to LSB of work
DVS
DIV2
DVS
DICNTR
DIV1
Work - Divisor -) Work
Set hi9h to LSB of residual area
Branch if work)=divisor
Work + Divisor -) Work
Clear LSB of residual area
Decrement shift counter
Loop until shift counter = a
I
~HITACHI
773
I
FUNCTION
I
I MCU/MPU I
ADDING 8-DIGIT BCD
16.
lID6301/HD6303 FAMILY LABEL
I ADDD
(a) Performs addition of 8-digit BCD number in RAM, and stores result in 8-digit
BCD number in RAM.
(b) Utilizes unsigned integers in arguments.
I
ARGUMENTS
CHANGES IN CPU
REGISTERS AND FLAGS
e:
Storage
Location
Contents
Not affected
ROM (Bytes)
15
X: Undefined
Result
Byte
Lgth.
SPEC IF ICAT ION S
t:
RAM (Bytes)
8
ABD
Augend
(RAM)
Entry
ACD
Addend
(RAM)
Stack (Bytes)
ACCD
4
4
ACCA
ACCB
x
x
0
No. of cycles
81
IX
Arguments
Reentrant
x
Addition
result
ABD
(RAM)
No
4
Returns
Carry or
no carry
bit C
(CCR)
1
C
V
Relocation
t
x
No
Z
N
Interrupt
x
x
Yes
I
H
•
x
I
DESCRIPTION
(1) Function Details
(a) Argument details
ABD : Holds 8-digit BCD augend.
(RAM)
[-~
CD
0 ..' ....)
1 Entry
After ADDD execution, contains
ACD(RAM)
arguments ('.000.01)
addition result.
ACD : Holds 8-digit BCD added.
(RAM)
b3l
bO
II : '1- : ' I. : 0I' : 'I-Augend
ABD AIIDH ABD+HBD13
0Return {ABD(RAM)
(884088938)
arguments
+)
1,:.1 0: 01 0:.1 0: II~ Addend
ACD ACD+-I ACIl+O ACDi3
bitCb31
bO· .
01-: 01-: 01 ·1·:SI_Add~twn
ABD ABDH ABD13 ABDI3 res u 1 t
a:
Fig. 1 Example of ADDD execution
SPECIFICATIONS NOTES
I
~HITACHI
774
16.
I MCU/MPU I HD6301/HD6303
ADDING 8-DIGIT BCD
FAMILY ILABEL
IADDD
I
DESCRIPTION
bit C: Indicates whether a carry is
(CCR)
generated or not after ADDD
execution.
1':'1";, I ,:nl';" I-Augend
1,>I">In:"I<,,I-Addend
+i
bit C=l: Carry is generated in
bit C CQJ<"I.:nI,:OI, >1_Addition
carry
result
addition result.
(See Fig. 2)
bit C=O: No carry is generated
in addition result.
Fig. 2 Addition example when carry
is generated
(b) Fig. 1 shows example of ADDD execution.
If entry arguments are as
sho~1
in
+)
partCDof Fig. 1, addition result is
bit
I" : " I" : " I, :' I:I : • I~ Augend
I';"I";"I';,E::J-Addend
cG lo:"IU:"I<'I-:'I~Addition
result
contained in ABD(RAM) as shown in part
Fig. 3 Addition example when upper
byte is not used
@of Fig. 1.
(2) User Notes
(a) As shown in Fig. 3, when not using upper byte, the upper byte should be
held to "0", otherwise addition result will not be correct, because
addition is performed with undefined data in the upper byte.
(b) After ADDD execution, augend is destroyed because addition result is containd
in ABD(RAM).
If augend needs to be retained after ADDD execution, it should
be saved in memory before execution.
(c) BCD number should be held in augend and addend, otherwise addition result
will not be correct.
I
(3) RAM Description
Label
Description
RAM
b7
ABD
bO
Upper byte
-
-
-
-
ACD
Lower byte
Upper byte
-
I--
-
f--
-
f--
Lower byte
8-digit BCD augend is stored before
execution.
8-digit BCD addition result is stored
after execution.
8-digit BCD addend is stored.
-
~HITACHI
775
16.
ADDING 8-DIGIT BCD
I MCU/MPU
I HD630l/HD6303 FAMILY ILABEL
1
ADDD
I
DESCRIPTION
(4) Sample Application
Subroutine ADDD is called after augend and addend are held.
WORIn
RMB
4
Reserves memory byte for 8-digit BCD
augend.
WORK2
RMB
4
Reserves memory byte for 8-digit BCD
WORK 3
RMB
4
Reserves memory byte for 8-digit BCD
addend.
addition results.
PSHA
PSHB
PSHX
LDD
STD
LDD
STD
LDD
II
}----:~:l
WORKl+2
ABD+2
STD
:~:K2
LDD
STD
WORK2+2
ACD+2
JSR
ADDD
Bes
OVER
LDD
STD
LDD
STD
ABD
WORK3
ABD+2
WORK3+2
}
Saves register contents that will be
destroyed by ADDD execution.
Stores 8-digit BCD augend into
entry argument (ABD).
}
Stores 8-digit BCD addend into
entry argument (ACD).
II
Calls subroutine ADDD.
If carry is generated in addition result,
branches to service routine.
}
-----
Stores addition result (return arguments
(ABD)) in RAM.
PULX
PULB
PULA
OVER
I
~ervice routine
1n case of carry
J
~HITACHI
776
16.
ADDING 8-DIGIT BCD
DESCRIPTION
I MCU/MPU
I HD6301/HD6303 FAMILY ILABEL
I
ADDD
I
(5) Basic Operation
(a) When addition of more than 2 bytes are executed, addition result can be
obtained by repeating addition for each byte.
(b) IX is used to indicate augend and addend addresses and is also used to count
number of additions.
(c) Clears bit C at first.
(d) Performs (Formula 1) on each byte of augend and addend using index addressing
mode.
Augend + Addend + (bit C)--'ACCA --------------- (Formula 1)
Bit C is added in (Formula 1) because addition result of lower bytes generate
carry.
(e) Adjusts addition result of (d) to decimal value using decimal adjust ACCA
instruction (DAA), and holds it in augend ABD (RAM).
(f) Decrements IX every time (d) to (e) is executed.
(g) Loops (d) to (f) until IX is "0".
I
~HITACHI
777
16.
ADDING 8-DIGIT BCD
MCU/MPU
ADDD
FLOWCHART
ADDD
Loads "4" in pointer indicating augend
address and counter indicating number of
addition.
Clears bit C for carry operation.
~-----' ---{
---{
~-----' ---{
~-----' ---{
---{
Adds addend and bit C to augend.
Adjusts addition result to decimal.
Stores decimal-adjusted result in augend
RAM.
Decrements pointer indicating augend
address and counter indicating number of
addition.
Tests if addition in all digits is
completed or not.
R T S
~HITACHI
778
16.
I MCU/MPU I
ADDING 8-DIGIT BCD
I
PROGRAM LISTING
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014A
00015
00016A
00017A
00018
00019A
00020
00021
00022A
00023A
00024A
00025A
00026A
00027A
00028A
00029A
00030A
HD6301/HD6303 FAMILY
ILABEL I ADDD
************************************************
*
*
*
************************************************
*
*
ABO (AUGEND)
ENTRY
*
*
ACD (ADDEND)
*>I<
* RETURNS
ABO (SUM)
*
CARRY (C~O;TRUE.e~l;OVER FLOW) *
*
>I<
*************************************************
*
$80
ORG
*
Augend -) sum
4
RMB
A ABO
*>I<
NAME
:
ADDING 8-DIGIT 8CD
(ADDD)
>I<
0080
0080
0084
0004
0004
FOOO
FOOO
F003
F004
F006
F008
F009
FOOB
FOOe
FOOE
CE
OC
A6
A9
19
A7
09
26
39
FOOO
0004
A ACD
*
*
A ADDD
A
7F
83
A ADDDl
A
7F
A
F6 F004
RMB
4
ORG
$FOOO
EQU
LOX
CLC
LOA A
ADCA
DAA
STAA
DEX
BNE
RTS
*114
Addend
Entry point
Set ADDR pointer(addition counter)
CLear carry bit
ABD-l. X Augend+addend
ACD-l.X
Convert into BCD
ABD-l, X Store in augend area
Decrement ADDR pointer
Loop untiL ADDR pointer
0
ADDDl
I
~HITACHI
779
17.
SUBTRACTING 8-DIGIT BCD
FUNCTION
I
MCU/MPU
I
ILABEL I SUBD
HD630l/HD6303 FAMILY
I
(a) Performs subtraction of 8-DIGIT BCD number in RAM and stores result in
8-digit BCD number in RAM.
(b) Uti lizes unsigned integers in arguments.
ARGUMENTS
1
CHANGES IN CPU
REGISTERS AND FLAGS
•
Storage
Location
Contents
Byte
Lgth.
: Not affected
x
: Undefined
t
: Result
SPECIFICATIONS
ROM (Bytes)
29
RAM (Bytes)
8
ACCD
Minuend
SUBEDS
(RAM)
ACCA
4
x
Entry
Arguments
Returns
DESCRIPTION
ACCB
Subtrahend
Subtraction
result
SUBEDS
(RAM)
Borrow
or no
borrow
bit C
(CCR)
0
x
No. of cycles
IX
SUBERS
(RAM)
Stack (Bytes)
120
x
4
Reentrant
4
1
C
V
No
t
x
Relocation
Z
N
No
x
x
Interrupt
H
Yes
I
•
x
I
(1) Function Details
( ",.m'''~
(90123456)
(a) Argument details
CD
b3l
bO
I:,,:,,~ 1,,1,,';':,1,,3,,;,,:1,,~,;,,~,1_ Minuend
Entry
.
ar uments SIJREICS(RAM) I;,:,; t~,:,,', I,',L~,I,~,:",~ ,1J ': 'J'-Subtraction
result
Fig. 3 Subtraction example when
not using upper byte
(2) User Notes
(a) As shown in Fig. 3, when not using upper byte, the upper byte should by held to
"0", otherwise subtraction result will not be correct, because subtraction
result is performed with undefined data held in the upper byte.
(b) After SUBD execution, minuend
stored in SUBEDS (RAM).
LS
destroyed because subtraction result is
If minuend needs to be retained after SUBD
execution, it should be saved in memory before execution.
(c) BCD number should be held in minuend and subtrahend, otherwise subtraction
result will not be correct.
I
(3) RAM Description
Label
Description
RAM
bO
b7
Upper byte
SUBEDS
f--
-
f--
-
f--
-
Lower byte
8-digit BCD minuend is stored before
execution.
8-digit BCD subtraction result is
stored after execution.
,
SUBERS
f--
Upper byte
-
f--
8-digit BCD subtrahend is stored.
-
f--
Lower byte
~HITACHI
781
17.
I
SUBTRACTING 8-DIGIT BCD
MCU/MPU
I
HD6301/HD6303 FAMILY
I
LABEL
I
SUBD
I
DESCRIPTION
(4) Sample Application
Subroutine SUBD is called after minuend and subtrahend are held.
WORI
Adds "1" in the
next step by setting bit C (See Formula
2 in "(5) Basic Operation").
----f
Loads "4" in pointer indicating minuend
address and counter indicating number
of subtraction.
____ [
Adds la's complement of subtrahend and
bit C to minuend.
____ {
____ {
Adjusts addition result to decimal.
Stores decimal-adjusted result in
minuend RAM.
Decrements pointer indicating minuend
----
{
____ {
( IX)+O
:~~::::t~:~.counter indicating number of
Tests if subtraction in all digits is
completed or not.
R T S
~HITACHI
784
17.
SUBTRACTING a-DIGIT BCD
I
PROGRAM LISTING
00001
00002
00003
00004
OOOOS
00006
00007·
00008
00009
00010
00011
00012
00013
00014A
OOOlS
00016A
00017A
0001S
00019A
00020
00021
00022A
00023A
00024A
0002SA
00026A
00027A
00028A
00029A
00030A
00031A
00032A
00033A
00034A
0003SA
00036A
00037A
I
MCU/MPU
I
I
HD6301/HD6303 FAMILY LABEL
I SUBD
..
************************************************
*
(SUBD)
* NAME : SUBTRACTING 8-DIGIT BCD
*
*
*
************************************************
*
*
ENTRY
SUBEDS (MINUEND)
*
*
SUBERS (SUBTRAHEND)
*
*
SUBEDS (RESIDUAL>
* RETURNS
*
CARRY (C=l:TRUE.C=O:BDRROW)
*
*
*
*
************************************************
*
$80
ORG
*
0004 A SUBEDS RMB
4
Minuend -> Residual
0080
0080
0084
0004
A SUBERS RMS
*
*
FOOO
FOOO
F003
F006
FOOS
FOOA
FOOS
FOOC
FOOE
FOOF
F012
F014
F016
F017
F019
FOIA
F01C
CE
CC
A3
ED
09
09
26
00
CE
A6
A9
19
A7
09
26
39
FOOO
0004
9999
82
S2
A SUSD
A
A SUSD1
A
A
FS F003
0004
7F
83
A
A SUSD2
A
7F
A
F6 F012
4
ORG
$FOOO
EQU
LOX
LDD
SUSD
STD
DEX
DEX
SNE
SEC
LOX
LDAA
ADCA
DAA
STAA
DEX
BNE
RTS
*
Subtrahend
Entry point
114
99999999-Subtrahend -) SUSERS
1:1$9999
SUSERS-2.X
SUSERS-2.X
SUSD1
Set carry bit
Set ADDR pointer (subtraction counter)
1:14
SUSEDS-l.X Minuend+nesstive of subtrahend
SUSERS-l.X
Convert into BCD
SUSEDS-1.X Store in SUSEDS area
Decrement ADDR pointer
Loop until ADDR pointer
SUSD2
0
I
~HITACHI
785
18.
I MCU /MPU
16-BIT SQUARE ROOT
I SQRT
IHD6301 /HD6303 FAMILY ILABEL
I
FUNCTION
(a) Obtains square root of 16-bit binary data in IX, and stores result in RN1.
(b) Utilizes unsigned integers in arguments.
CHANGES IN CPU
REGISTERS AND FLAGS
I
ARGUMENTS
•
ROM (Bytes)
: Not affected
x : Undefined
Storage
Location
Contents
Byte
Lgth.
t
54
RAM (Bytes)
: Result
ACCD
Data
Entry to be
squared
ACCA
IX
2
x
I
SPECIFICATIONS
3
Stack (Bytes)
ACCB
0
x
No. of cycles
IX
478
x
Arguments
Reentrant
SANS+l
Square
Returns root
1
(RAM)
C
V
No
x
x
Relocation
Z
N
No
x
x
Interrupt
I
H
Yes
•
I
DESCRIPTION.
b15
(1) Function Details
I
III;XIJ
b19
HEXD+I
1
bO
I -I
@Return U5\'%llo: 51 z : '
argument
DECIJ D~;CIJ+ I
a :
D~;CD+Z
(b) Fig. 1 shows example of HEX execution.
If entry argument is as shown in part
CD
Fig. 1 Example of HEX execution
of Fig. I, 5-digit BCD number, in this case
"52734" is held in DECD (RAM) (see part
@of Fig. 1) .
SPECIFICATIONS NOTES\
~HITACHI
791
19.
I MCU/MPU
CONVERTING 2-BYTE HEXADECIMALS INTO S-DIGIT BCD
I
HD630l/HD6303 FAMILY ILABEL I HEX
I
DESCRIPTION
(2) User Notes
"0" is always stored in MS (the 6th digit) of return argument.
(3) RAM Description
Description
RAM
Label
bO
b7
HEXD
-}
Upper byte
f.-
Lower byte
2-byte hexadecimal number is stored.
Upper byte
DECD
f.-
=1
f.-
Lower byte
(4) Sample Application
S-digit BCD number is stored.
Subroutine HEX is called after 2-byte hexadecimal number is held.
WORK 1
RMB
2
Reserves memory byte for 2-byte
hexadecimal number.
WORK 2
RMB
3
Reserves memory byte for S-digit BCD
number.
PSHA
}-----
PSHB
PSHX
/I
LDD
WORK 1
STD
HEXD
JSR
HEX
LDD
STD
LDM
STM
}----/I
DECD
WORK2
:~~:::2
Saves register contents that will be
destroyed by HEX execution.
Stores 2-byte hexadecimal number into
entry argument (HEXD).
Calls subroutine HEX.
}
Stores S-digit BCD number (return
argument (DEGD»
in RAM.
PULX
PULB
} ----- . . "'"'"' I<
CONVERTING 5-D!GIT BCD INTO
(BCD)
2-BYTE HEXADECIMALS
NAM::
>i'
>I<
>I<
>I<
*
************************************************
'"
'"
>I<
(5-DIGIT BCD)
DEC
HDATA (2-BYTE HEXADECIMALS)
ENTRY
RETURNS
'"
'"
'"
************************************************
>I<
>I<
>I<
OOBO
ORG
$80
RMB
RMB
RMB
3
2
1
ORG
$FOOO
EQU
LDX
LDAA
STAA
CLR
CLR
BTST
BEQ
LDAB
ANDB
CLRA
ADDD
STD
DEC
BNE
RTS
LDAB
LSRB
LSRB
LSRB
LSRB
BRA
BTST
BNE
INX
LDD
ASLD
STD
ASLD
ASLD
ADDD
STD
8RA
*'IlDEC
>I<
0080
0083
0085
0003
0002
0001
A DEC
A HDATA
A BCNTR
5-digit BCD
2-byte Hexadecimals
Digit counter
>I<
FOOO
>I<
FOOD
F003
F005
F007
FOOA
FOOD
F010
F012
F014
F016
FOl7
F019
F01B
F01E
F020
F021
F023
F024
F025
F026
F027
F029
F02C
F02E
F02F
F031
F032
F034
F035
F036
F038
F03A
CE
86
97
7F
7F
78
27
E6
C4
4F
D3
DD
7A
26
39
E6
54
5"
54
54
20
7B
26
08
DC
05
DD
05
05
D3
DD
20
FOOO A BCD
OOBO A
A
05
85
A
00B3 A
0084 A
01 B5
BCD1
OF F021
A
00
OF
A
BCD2
83
A
83
A
00B5 A
09 F029
00
A BCD4
ED F016
01 85
BCD5
01 F02F
83
A BCD3
B3
A
B3
A
83
A
D1 FOOD
115
BCNTR
HDATA
HDATA+1
O,BCNTR
BCD4
O,X
Il$OF
HDATA
HDATA
BCNTR
BCD5
Entry ooint
Load BCD data ADDR
Set figure counter
Clear Hex area
Test bitO of BCNTR
Branch i'f bitO ; 0
Set lower 4 bits of BCD data
Clear ACCA for work use
ACCD + HDATA:HDATA+1 - ) HDATA:HDA
Decrement digit counter
Loop until figure counter; 0
O,X
Set upper 4 bits of BCD data
BCD2
O,BCNTR
BCD3
Branch BCD2
Test bitO of BCNTR
Branch if bitO ; 1
Increment BCD data ADDR
HDATA:HDATA+1 '" 2 -) ACCD
HDATA
HDATA
ACCD -) HDATA:HDATA+1
HDATA:HDATA+1 '" 4 -) ACCD
HDATA
HDATA
BCD1
ACCD + HDATA:HDATA+1 -) ACCD
ACCD -) HDATA:HDATA+1
Branch BCD1
~HITACHI
802
ILABEL I
BCD
21-
I MCU/MPU
SORTING
FUNCTION
I
ILABEL I SORT
HD630l/HD6303 FAMILY
I
(a) Sorts unsigned byte oriented data in RAM in descending order.
(b) Permits number of bytes to be sorted to be freely selected.
(c) Utilizes unsigned integers in arguments.
I
ARGUMENTS
CHANGES IN CPU
REGISTERS AND FLAGS
Storage
Location
Contents
No. of
bytes to
be
sorted
•
Byte
Lgth.
I
Returns
ACCD
ACCA
ACCA
1
7
ACCB
x
Stack (Bytes)
x
2
No. of cycles
400
x
IX
Reentrant
2
C
-
-
22
RAM (Bytes)
IX
Starting
address
of data
to be
sorted
ROM (Bytes)
Undefined
: Result
Entry
Arguments
: Not affected
x :
SPECIFICATIONS
-
V
No
x
x
Relocation
Z
N
No
x
x
Interrupt
I
H
Yes
• •
DESCRIPTION
I
blS
(1) Function Details
I X ( S 00 • 0 )
I
0
IX
:
n : •
AccA bO
: •I
bO
: n I
I
RAM
(a) Argument details
ill
ACCA: Holds number of bytes to be
sorted; (No. of bytes to be sorted
- 1) in I-byte hexadecimal number.
IX
b7
I n
ACCA($O.)
Entry
argu Starting address ~
-ments of data to be~$no.o $1.
$".
sorted (IX)
$AO
s I'
~.
$ • 6
: Holds starting address of data
~
to be sorted in I-byte hexadecimal
number.
·0
Result
Sorted
data
['"""~
SA"
$-.0
S I 6
$ 0 8
Fig. 1 Example of SORT execution
"='"
SPECIFICATIONS NOTESI
"No. of cycles" in :'SPECIFICATIONS" represen ts the number of cycles needed to
sort S-byte ascending data to descending.
~HITACHI
803
21.
I MCU/MPU I HD6301/HD6303
SORTING
I
FAMILY LABEL
I SORT
I
DESCRIPTION
(b) Fig. I shows example of SORT execution.
CD
in part
If entry arguments are as shown
of Fig. 1, sorted data is stored from address $90 in descending
order (see part @ of Fig. 1).
As data to be sorted is 5-byte, $04 (No. of bytes to be sorted ($05) - 1) is
held in ACCA.
(2) User Notes
When loading number of bytes to be sorted, hold "No. of bytes to be sorted
- 1"
to ACCA for effective loop processing.
(3) RAM Description
Label
Description
RAM
b7
SCNT
SCNT
bO
~I
Counter showing how many bytes remain to
be sorted is stored.
Counter showing how many bytes remain to
be compared is stored.
(4) Sample Application
Subroutine SORT is called after starting address and number of bytes to be
sorted are held.
RMB
WORK 1
Reserves memory byte for number of
I
bytes to be sorted.
WORK 2
RMB
Reserves memory byte for starting
2
address to be sorted.
LDAA
Loads number of bytes to be sorted into
WORK 1
entry argument (ACCA).
LDX
Loads starting address of data to be
WORK 2
sorted into entry argument (IX).
II
JSR
SORT
II
Calls subroutine SORT.
~HITACHI
804
21.
J MCU/MPU J HD6301/HD6303
SORTING
FAMILY
ILABEL I SORT
I
DESCRIPTION
(5) Basic Operation
(a) Fig. 2 shows how 3-byte values are sorted in descending order.
LI_5____1__
0 ____8~1
Input data
First
c~mparison
times
[IX,.
---,III
5
8
·········CD
H
......... @
..,.,.---- .......
(n-l=2)
I II
Second.
[
5
H
I 1\
(Note)
I
shows
comparison
......... @
·········0
.........
c~mparl.son·
tl.mes
(n=2=1)
Number of bytes
n=3
~
X
shows
data exchange
Fig. 2 Example of sorting
(i) Finds largest value among three and puts it into left position.
(See Fig. 2
CD @
and
G»
(ii) Compares middle and right values and puts larger one in middle.
(See Fig. 2 (0,~)
(6) Program Processing
0) Uses IX as two pointers; one shows memory address where data
is stored,
the other shows memory address where the largest data after comparison
is stored.
(ii) First, uses IX as pointer showing memory address where data is stored.
(iii) Loads this data into ACCA to be compared.
Increments address where data
is stored using index addressing mode and compare new value with value
in ACCA.
(iv) If value is larger than compared value in ACCA, exchange them.
(v) Loop (iii) to (iv) untill counter SCNT2 (RAM), showing number of
remaining bytes, reaches "0".
(vi) When SCNT 2 (RAM) reaches "0", the largest data compared with RAM is
loaded into ACCA.
(vii) Then use IX as pointer to indicate where the largest data will be stored.
(viii) Stores contents of ACCA in address IX points, and load next address, at
which the second largest data is to be stored, into IX.
(ix) Decrements counter SCNTI (RAM) showing how many bytes remain to be
sorted.
(x) Loops (ii) to (ix) untill SCNTl (RAM) is "0".
~HITACHI
805
I
21.
SORTING
SORT
MCU/MPU
FLOWCHART
----{
Stores number of bytes to be sorted in
SCNTl.
2
----{
----{
Stores number of bytes to be sorted in
SCNT2.
~---{
Loads the first data to be sorted into
ACCA.
----{
Increments address pointer.
----{
Saves starting address of data to be
sorted in RAM.
Compare contents of ACCA with value of
data pointed by IX.
Exchanges data in ACCA with that
pointed by IX.
----{
---{
Decrements number of bytes to' be
compared.
Tests if all comparisons are
completed.
Continued on next page
~HITACHI
806
21.
MCU/MPU
SORTING
HD6301/HD6303 FAMILY
SORT
FLOWCHART
~~~~{
----{
----{
----{
~~~~1
Stores the largest data in RAM in
descending order.
Indicates address where the second
largest number will be stored.
Decrements counter indicating number
of bytes remaining to be stored.
Loads number of bytes remaining to
be compared.
Tests if all data is sorted.
previous page
RTS
I
~HITACHI
807
21.
I
SORTING
I
HD630l/HD6303 FAMILY
****************************************************** **~*****
*
*>I<
NAME
SORTING
(SORT)
*
*>I<
***************************************************************
>I<
>I<
ENTRY
*>I<
>I<
RETURNS
ACCA (VOLUME OF SORTING DATA)
(TOP ADDR OF SORTING DATAS)
IX
NOTHING
>I<
>I<
>I<
>I<
>I<
***************************************************************
>I<
ORG
0080
$80
>I<
0001
0001
0080
0081
A SCNT1
A SCNT2
Counter tor sorting data
Counter tor comparing data
RMB
RMB
>I<
ORG
FOOO
$FOOO
>I<
FOOO
F002
F004
FOOS
F007
F008
FOOA
FOOC
FOOE
F010
FOll
F014
F016
F017
F019
F01A
FOlD
F01F
F021
97
97
3C
A6
08
A1
24
E6
A7
17
7A
26
38
A7
08
7A
96
26
39
FOOO
80
81
A SORT
A
A SORTl
00
A
SORT2
A
00
05 FOll
A
00
A
00
0081 A SORB
Fl F007
00
A
0080 A
80
A
El F002
EQU
STAA
STAA
PSHX
LDAA
INX
CMPA
BCC
LDAB
STAA
TBA
DEC
BNE
PULX
STAA
INX
DEC
LDAA
BNE
RTS
>I<
SCNT1
SCNT2
O.X
O,X
SORB
O.X
O,X
SCNT2
SORT2
O,X
SCNTl
SCNTl
SORTl
Entry point
Sto re reste of sorting data
Store reste of comparing data
Push sorting data AoDR
Load sorting data
Set next sorting data ADDR
Compare comparing data with sorting data
Branch if comparing data> sorting data
Exchange each data
Transfer exchanged data
Decrement comparing data counter
Loop untiL comparing data counter
0
PuLL sorting data ADDR
Store max data
Increment sorting data ADDR
Decrement soting data counter
Loop untiL sorting data counter
0
~HITACHI
808
ILABEL I SORT
I
PROGRAM LISTING
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013A
00014
00015A
00016A
00017
00018A
00019
00020
00021A
00022A
00023A
00024A
0002SA
00026A
00027A
00028A
00029A
00030A
00031A
00032A
00033A
00034A
0003SA
00036A
00037A
00038A
00039A
MCU/MPU
HD63011HD6303 SERIES HANDBOOK
Section Eight
Hardware
Application Notes
I
~HITACHI
809
FOREWORD
The HD6301/HD6303 are CMOS 8-bit single chip microcomputers controlled by
microprogramming. The HD6301/HD6303 provide 8-bit parallel handshake
interfacing, pipeline control, halt and memory-ready functions for various kinds
of data processing.
APPLICATION NOTES are written to help users design hardware systems using
examples of simple application functions with circuit diagrams, timing charts
and program examples.
Application examples in APPLICATION NOTES used in actual systems should
be tested for proper operation.
~HITACHI
810
NOTE
The following hardware application notes were prepared for HD6301YO/HD6303Y
devices. The applications, howeve~ are generic in nature and also apply to
HD6301Vl/HD6303R and HD630lXO/HD6303X devices.
I
~HITACHI
811
Section 8
Hardware Application Notes
Table of Contents
Page
APPLICATION NOTES GUIDE.........................................
815
1.
Symbols.......................................................
815
2.
Application Example Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
817
3.
1st Section (Hardware) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
819
4.
2nd Section (Software). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
823
5.
3rd Section (Program Module) .....................................
825
5.1
Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
826
5.2
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
832
5.3
Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
836
6.
4th Section (Subroutine) ............................... , . . . . . . . . . .
837
7.
5th Section (Program Listing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
840
8.
Program Module Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
845
SYSTEM APPLICATION EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
848
System Application Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
848
1/0 PORT APPLICATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
849
1.
HD61830 (LM200) Graphic Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
849
2.
Darlington Transistor Drive (LED Dynamic Display) . . . . . . . . . . . . . . . . . . . ..
883
TIMER APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
896
3.
Duty Control of Pulse Output and DA Conversion . . . . . . . . . . . . . . . . . . . . . .
896
4.
Pulse Width Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
912
5.
Input Pulse Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
922
6.
8 x 4 Key Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
932
INTERRUPT APPLICATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
947
7.
AID Converter (HA16613A) Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
947
PARALLEL HANDSHAKE APPLICATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
956
8.
Standard Keyboard Interlace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
956
9.
Centronics Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
970
SCI APPLICATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
982
10. Data Transfer With Asynchronous SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
982
11. Liquid Crystal Drived (HD61100A) Control. . . . . . . . . . . . . . . . . . . . . . . . . . . .
998
$
812
HITACHI
EXTERNAL EXPANSION APPLICATIONS ............................... 1010
12.
External Expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1010
13.
Slow Device Interface ........................................... 1043
LOW POWER DISSIPATION/FAIL-SAFE APPLICATIONS ................... 1057
14.
Low Power Dissipation Mode ...................................... 1057
15.
HA1835P Control and Error Detection .............................. 1074
I
~HITACHg
813
~HITACHI
814
1.
Symbols
Symbols and abbreviations used in APPLICATION NOTES are described below.
1.1
Operation
(
)
c
Contents
«()
Index addressing
a+b
Data transfer from a to
Addition
+
Subtraction
1.2
1.3
x
= Multiplication
/
= Division
1\
= AND
v
= OR
<±)
Exclusive OR
X
NOT
Register Symbols in MCU/MPU
ACCA
Accumulator A
ACCB
Accumulator B
ACCD
Double accumulator (ACCA
CCR
Condition code register
I X
a-bit, 16-bit index register
IXH
Upper a bits of index register
IXL
Lower a bits of index register.
ACCB)
Description of bits 0 through 5 of condition code register
C
Carry or borrow
bit 0
V
Overflow in 2's complement operation
bit 1
Z
Zero
bit 2
N
Negative
bit 3
I
Interrupt mask
bit 4
H
Half carry
bit 5
I
~HITACHI
815
1.4
Others
Equal sign
Not-equal sign
Greater than
Less than
Greater than or equal
Less than or equal
• •
$
= Delineates
ASCII characters
Hexadecimal data
Labels of successive addresses
SCI
Serial communication interface
DDR
Data direction register
FRC
Free running counter
OCRl
Output compare register 1
OCR2
Output compare:oregister 2
ICR
Input capture register
TCSRl
Timer control/status register 1
TCSR2
Timer control/status register 2
TCSR3
Timer control/status register 3
RMCR
Transfer rate/mode control register
TRCSR
TX/Rx contIDol status register
RDR
Receive data register
TDR
Transmit data register
RPSCR
RAM/port 5 control register
TCONR
Time constant register
T2CNT
Timer 2 up counter
$HITACHI
816
Application Example Configuration
This chapter explains the configuration of each system application example
following this chapter.
Each application example in APPLICATION NOTES is divided into 5 sections,
as shown in figure 1.
,------------ - - 1st SECTION------~.~IHARDWARE DESCRIPTION
(HARDWARE)
I
I
-
- -------- - - ---
~
FUNCTION
MICROCOMPUTER
OPERATION
PERIPHRAL DEVICES
CIRCUIT DIAGRAM
I
PIN FUNCTIONS
L _ _ _ _ _ _ _ _ _ _ _ _ _ HARDWARE
_____
_______ _
1
OPERATION
r- - -
- -
- - - - - - - - - - - - -
- - - - - - - - -
I
_-.l
- --,
2nd SECTION ------......,1 SOFTWARE DESCRIPTIONf PROGRAM MODULE
(SOFTWARE):
CONFIGURATION
I
PROGRAM MODULE
I
FUNCTIONS
PROGRAM MODULE PROCESS
FLOW (Main Program)
I
-------------------~
,---------------------- -----,
3rd SECTION ------.....~
(PROGRAM MODULE)
L
I
PROGRAM MODULE
FUNCTION
I
DESCRIPTION-- ARGUMENTS
I
CHARGES IN CPU
I
REGISTERS AND FLAGS
SPECIFICATIONS
DESCRIPTION --.-Function
Details
SPECIFICATIONS
- User Notes
NOTES
-RAM
Allocation
I
FLOWCHART
-Sample
:
Application I
-Basic
I
Operation
I
____________ _
r
--- - - -
4th SECTION------.....""ii-S~B;Ot7T~N1~- - - - - - - -F~C-;I;N- - - - - - - - - (SUBROUTINE)
I
I
I
I
L
--~
-
-1
DESCRIPTION
BASIC OPERATION
:
PROGRAM MODULES USING
I
THIS SUBROUTINE
:
FLOWCHART
_____________
______________ 1
L
~
2.
r--------------------------~
5th SECTION - - - - - - - t•..J1 PROGRAM LISTING
(PROGRAM LISTING) :
I
I
MAIN PROGRAM LISTING
PROGRAM MODULE
LISTING
SUBROUTINE LISTING
~------------------
Figure 1.
1
:
I
~
Application Example Configuration
~HITACHI
817
(I)
1st Section (Hardware)
Describes functions, circuit diagram, hardware operation for each hardware
application example and making specific use of HD6301YO/HD6303Y's
characteristic functions.
(2)
2nd Section (Software)
Describes program module configuration which controls hardware application
example explained in the 1st Section.
Also shows main program of sample
application.
(3)
3rd Section (Program Module)
Describes program modules except main program, presented in the 2nd
Section, in detail.
Each program module is described in the same format
so that users can use them independently.
(4)
4th Section (Subroutine)
Describes subroutine used by each program module.
When using program
modules explained in the 3rd Section, refer to these subroutines, if
necessary.
(5)
5th Section (Program Listing)
Provides program listings for sample application explained in the 1st
section.
,A detailed explanation of all five sections follows.
~HITACHI
818
3.
1st Section (Hardware)
3.1
Function
Describes system specifications for the hardware used in a particular
application.
Example:
1. 1.1
Function
Initializes graphic mode and displays dot graphics on the LM200 liquid
crystal IJlOdule.
3.2
Microcomputer Operation
Describes typical functions of the microcomputer used in a particular
application.
Example:
1.1.2
Microcomputer Operation
The HD630lYO transfers display data to the dot matrix liquid crystal
graphic display controller LSI HD6l830 (LCTC) from port 3 onto the LCTC
data bus (DBO
~
through port 1.
3.3
DE7), and transmits control signals E, R/W, and RS
Ports 1 and 3 are controlled by softWare.
Peripheral Devices
Describes typical functions of the peripheral devices used in a particular
application.
I
Example:
1.1.3
Peripheral Devices
HD6l830 LCTC:
Receives control signals and display data from the
HD630lYO and in turn controls the HM6ll6 Display RAM and LM200.
LM200 Liquid Crystal Module:
Receives graphic display data and control
signals from the HD6l830 LCTC.
A resolution of 64 x 240 pixels is
provided in LM200 graphic mode.
In this application, the figures
"sn",
meaning HITACHI, are displayed.
~HITACHI
819
3.4
Circuit Diagram
Describes the circuit diagram for the hardware example.
Note) All microcomputers described in APPLICATION NOTES use the plastic
DIP type package.
Example:
1.1.4
Circuit Diagram
LCTC control circuit is shown in figure 1-1.
MCU
HDeSOIYO
+&V
..
140
.f
LCTC
HD81880
~
R~S
.0 GND
15C§
I. E
17 I\IW
18 RS
pF
'
..
~L~
5
Liquid crystal module
D .7
D'I '8
eL z 11
LM200
-5V
nM 10
:: DBa
• XTAL
26 08 1
MAo :
28 DB4
22 DBs
MAs 80
2& DBa
u DBa
tMfbCJ
8 EXTAL
BBpF
21
3Ukfl
g::
7 R
·C
8 CR
15pF
MA, •
MA'~I~________~~~~~~~~~
MA459
MAs 58
MAIIS'1
..
MA, 58
MAI5S
MA. 540
MAl 8'1
MOo !HI
MOl 85
MOl S40
MO, 83
~g:~.~'~
MD.
MD,
__________-L~~~~L-I
:~
wg13
Figure 1-1.
$
820
LCTC Control Circuit
HITACHI
HV
3.5
Pin Functions
Describes interface between microcomputer and the external circuit using
a table.
Example:
1.1.5
Pin Functions
Pin functions at the interface between the HD6301YO and LCTC are shown
in table 1-1.
Table 1-1.
Pin Functions
Active Level
Pin Name
(HD6301YO) Input/Output (High or LoW) Function
Pin Name Program
(LCTC)
Label
P 10
Pll
P12
Output
Output
Output
High
Enables signal
E
High
Reads data
R/W
Low
Writes data
High
Selects instruction register RS
Selects data register
Low
Pao
P1DTR
Data Lines
Input/Output
DBa
PH
Input/Output ----
DBl
P32
Input/Output
DB2
P33
Input/Output
DB3
P3~
Input/Output
DB4
P35
Input/Output
DBs
P 36
Input/Output
DB6
P37
Input/Output ----
DB?
P3DTR
"Active Level" in the table indicates the following:
High
Logical 1
Low
Logical 0
I
Logical 1 or 0
~HITACHI
821
3.6
Hardware Operation
Describes hardware operation for controlling an external circuit using a
timing chart.
Example:
1.1.6
Hardware Operation
The timing chart for interfacing between the HD6301VO and each signal
is shown in figure 1-2. Q) and
® in
figure 1-2 show timing for read and
write.
Q;) Data from LCTC can be read duringQ)period.
GD
Data can be written to LCTC at the falling edge of signal E.
LCTC pin names _ _ _ _.,.
RS. R/W
E
DBo - DB.
(HD8801YO .... LCTC)
______________________- J
DB. -DB.
(HD6801YO-LCTC)
Figure 1-2.
HD6301YO~LCTC
~HITACHI
822
Interface
4.
2nd Section (Software)
4.1
Program Module Configuration
Describes program module configuration to control the hardware application
example.
Each program module is numbered.
No. of main program is "0",
and the other program modules 'are numbered from 1 to N.
Example:
1.2.1
Program Module Configuration
The program module configuration for graphic display on the liquid
crystal module is shown in figure 1-3.
LZHMN
LZHINT
INITIALIZE
LCTe
MOVE
DISPLAY
Figure 1-3.
4.2
Program Module Configuration
Program Module Functions
Describes function of each program module using a table.
"No." in the
table matches "No." in the Program Module Configuration.
Example:
1.2.2
Program Module Functions
Program module functions are summerized in table 1-2.
Table 1-2.
I
Program Module Functions
Label
Function
MAIN PROGRAM
L2HMN
Demonstrates graphic display on LM200.
INITIALIZE LCTC
L2HINT
Initializes LCTC for graphic mode.
2
CLEAR DISPLAY RAM
L2HDCR' Clears display RAM to clear display.
3
DISPLAY DOT
L2HDST
Turns on and off 1 dot specified by row or
column coordinate.
4
MOVE DISPLAY
L2HMVE
Moves dot display up, down, left, or right.
No.
Program Module Name
0
1
~HITACHI
823
4.3
Program Module Process Flow (Main Program)
Describes sample main program to execute program modules, explained in
(l) Program Module Configuration.
Note) Stack pointer is initialized only in the main program.
Example:
1.2.3
Program Module Process Flow (Main Program)
The following flowchart (figure 1-4) demonstrates the process for
displaying graphics on the LM200 liquid crystal display, using the
modules described above.
Figure 1-5 shows this applications display.
Main Program
+_.__.___-[ =;C~~~~I~~ initialize
LC'l'C
----[ Execute L2HDCR to clear display RNI.
---{ =:. s:~::~:; ::::: ~!o=:,~!:a~~e,
---{load display data
inta ACC".
___ -{::~:. data table address of display
---{Test if display data is cocnpleted.
---{'rest 1f 1 dot 1s turned on or off.
----{'l'Ilrn on 1 dot.
---{store instruction to turn off 1 dot.
----{Tum off 1 dot.
Fiqurs 1-4.
=--
Main Program Flowchart
~~
[ .... •••••
•
••
..••
n ••••••
'"
.g
•••• 1• ••••1
l'dot·1
5 dots
1 dot
Figure 1-5.
Example of L2f101N Execution
~HITACHI
824
5.
3rd Section (Program Module)
The 3rd Section consists of the parts as shown in figure 2.
PART 1 ------~-FUNCTION
(SPECIFICATION)
~ARGUMENTS
CHANGES IN CPU REGISTERS AND FLAGS
SPECIFICATIONS
SPECIFICATIONS NOTES
PART 2 ---------DESCRIPTION lFunction Details
(DESCRIPTION)
User Notes
RAM Allocation
Sample Application
Basic Operation
PART 3 - - - - - - - - FIDWCHART
(FLOWCHART)
I' ' ' -
I
rnow.=
II~
II~
.roil!:" Nodul. . . . . ,
I
II~
II~
Modul. '00. ,
I
I
D. .eripti.n,
II~
II~
'<·0'_ Nodul• •oo.,
I~
ArlJUll!enta:
Contents
Seaclf1cation8.
Chan2sa in CPU
Storaqe
Location
No. of
Byte.
I
I
ReSl1stera and FIlli_:
I
Entry
""COAces
IICCA
I
ROM (Bytes):
I
DC
CJ
I
I
I
Re-
turns
C
Z
I
I
I
I
RAM (Bytes) I
Stack (Byte.) I
No, of cycles.
Reentrant:
v
.
H
I
I
I
Relocatablel
Interrupt Olt? I
• I Not affected
" I Undefined
t ; Result
I
Descriptionl
I-
I-
I
'p.elfie.tion. Not•• ,
Figure 2.
Program Module Section
~HITACHI
825
5.1
Specification
The Specification Part is shown in figure 3
figure 3).
([
===J:
blocked off area in
This part explains function, arguments, changes in CPU registers
and flags, specifications and specifications notes.
Each numbered item in
the figure is described below.
C(2)
1(3)
r - -- - - - - - - - - - - - - --------------r------------- i --------- j
(1)1 ,=,<~
Mod.', N~,
I
II''''I~"'
L-L_a_b_e_l-_:_ _ _ _ _ _...
(4) ~ Function:
L(6)
L(7)
L
(5)
-+
I
Specifications:
Changes in CPU
Arguments:
Contents
L
Storage
Location
No. of
Bytes
Re<;!isters and Flags:
ACCD
ACCA ACCB
I
Entry
IX
I
I
I
I
•
Returns
x
t
Z
I
I
I
I
C
ROM (Bytes) :
(Bytes) :
Stack (Bytes) :
No. of cycles:
Reentrant:
V
I
I
I
RAM
N
I
I
Relocatable:
Interrupt OK?:
H
I
: Not affected
: Undefined
: Result
________ J
Description:
1.
Function Details
2.
User Notes
(S'--r-I 'P'o"'oo",o,
L
~
N.""
___________________________________________________________
Figure 3.
Specification Part
~HITACHI
826
~
(1)
PROGRAM MODULE NAME:
Example:
Program Module Name:
(2)
MCUjMPU:
DISPLAY DOT
Indicates microcomputer and microprocessor applicable to
the progr am.
Example:
MCU/MPU: HD630lYO
(3)
LABEL:
Indicates the name identifying program entry point.
When
using the program without modification, use this label to call the
program.
Example:
~L2HDST
(4)
FUNCTION:
Describes program function.
Example:
Function:
Turns on or off 1 dot specified by row and column coordinates in entry arguments.
I
~HITACHI
827
(5)
ARGUMENTS:
Describes entry arguments necessary to execute a program,
and return arguments resulting from Program execution.
(a)
Contents:
Describes contents of entry and return arguments.
(b)
Storage Location:
Describes registers and RAM in which entry
and return arguments are set.
In case of
RAM, the storage location is denoted by a
label followed by "(RAM)".
(c)
No. of Bytes:
Describes number of bytes for entry and return
arguments.
Example:
Arguments:
Contents
Storage
Location
Entry TUrn on/off DOT SET
Returns
(6)
indicator
(RAM)
Dot column
DTX
No. of
Bytes
1
1
coordinate
(RAM)
Dot row
coordinate
DTY
(RAM)
1
---
--
-
CHANGES IN CPU REGISTERS AND FLAGS:
Describes changes in CPU registers
and flags after program execution.
Symbols and abbreviations in
the table are shown below.
(a)
CPU registers.
ACCA:
Accumulator A
ACCB:
Accumulator B
ACCD:
Double accumulator (ACCA
IX:
ACCB)
Index register
~HITACHI
828
(b)
(c)
Flags in condition code register
C
Carry or borrow
V
OVerflow in 2's complement operation
Z
Zero
N
Negative
I
Interrupt mask
H
Half carry
Status of CPU registers and condition code flags
•
: NJt affected : Previous values retained after program
execution.
x
Undefined
Previous values destroyed after program
execution.
Program result contained.
Result
Example:
Changes in CPU
Registers and Flags:
ACCD
ACCA ACCB
x
I
x
~
•
x
In this example, ACCA, ACCB, IX and bit
C, bit V, bit N, bit Z of CCR are
IX
C
x
Note)
destroyed after program execution.
V
Thus, registers and flags, which will
x
be destroyed, should
N
execution, if necessary.
x
x
I
H
•
•
be saved before
Not affected
: Undefined
Result
I
~HITACHI
829
(7)
SPECIFICATIONS:
(a)
ROM
Describes program module specifications.
(By~es):
Indicates amount of ROM used in.the program
module.
(b)
RAM (Bytes):
Indicates amount of RAM used in the program
module.
RAM used by the stack, however, is not
included.
(c)
Stack (Bytes):
Indicates stack size used in the program module.
Stack size used by called subroutines however,
is not included.
When executing a program
module, the total stack size must be reserved.
(d)
No. of cycles:
Indicates the maximum number of cycles when
executing a program module.
Execution time of
the program module can be calculated using No.
of cycles as follows.
Execution time (sec)=No. of cycles x Cycle time
Cycle time (sec)=4/(External oscillator
(e)
Reentrant
(Hz»
Indic.ates whether or not the program module can
be called by two or more programs at the same
time.
(f)
Relocatable
Indicates whether or not the program module can
be located in other memory space.
(g)
Interrupt OK?:
Indicates whether or not the program module can
be interrupted by other programs.
If "No",
disable interrupts before program execution and
enable them after.
~HITACHI
830
Example:
Specifications:
ROM (Bytes): 134
RAM (Bytes): 9
Stack (Bytes): 6
No. of cycles: 513
Reentrant: No
Relocatable: No
Interrupt OK?: Yes
(8)
SPECIFICATIONS NOTES:
Describes notes on items listed in"(7)
SPECIFICATIONS".
Example:
Specifications Notes:
1. Values in "Specifications" include values for subroutines called by L2HDST.
2. "No. of cycles" in "Specifications" indicates the number of cycles required
when L2HBSY is executed in the minimum number of cycles (no waiting for LM200).
I
~HITACHI
831
5.2
Description
~hown
The Description Part is
in figure 4.
r - - -,
( ~ __ J : blocked off area in
This part explains function details, user notes, RAM allocation,
figure 4).
sample application and basic operation.
Each numbered item in the figure
is described below.
(1)
(2)
L__________________1________________ J___________,
r-- --- -- - - ___
iI
,"09<"
Moo"'e N~e,
II ~
L . _ _ _ _ _ _ .____________
_______
_____
_________
I
No. of
Bytes
AceD
"cell ACeB
I
ROM
3.
RN-1 Allocation
4.
Sample IIpplicfltion
S.
Basic Operation
(Bytes):
RAM (Bytes):
Stack
(Bytes):
No. of cycles:
Relocatable:
Interrupt OK?:
Re-
turns
•
~
: Not Affected
: Undefined
Result
t :
f-~~:C~~~~i-O~~---------------------------------
r
1.
- ------------ ----- -1
l
Function Details
!
I
I
,
(4)1--
!
2.
User Notes
:
,
L_______________________________ _______________ _
,,
,
I
I
I'peo1fioo"o._ Note..
__________ • .J
Figure 4.
(1)
PROGRAM MODULE NAME }
(2)
MCU/MPU
(3)
LABEL
Description Part
Same as "5.1 Specification"
~HITACHI
832
(3)
IIMCUIMPU'
IILObel'
_ ____ .J
__
Registers and Flags:
Entry
(2)
1____________________1__________________l__ ---------,
Spec! fications:
Changes in CPU
Storage
Lo,<,ation
r- ________________
Ii IP
*
*
*
************************************************
(a) *
*
*
ENTRY
DTX(DOT COLUMN COORDINATE)
*
DTY(DOT ROW COORDINATE)
*
*
DOTSEHTURN ON/OFF INDICATOR)
*
*
RETURNS
NOTHING
*
*
(b)
*
*
~
************************************************
96 4~ ~ LDAA
DTX
Load coLumn coordinate
84 F8
A
ANDA
"$F8
DTX AND $F8-)DTWK
97 4A
A
STAA
DTWI<
44
LSRA
(DTX AND $F8)/8-)CCNT
44
LSRA
44
LSRA
97 47
A
STAA
CCNT
96 49
A
LDAA
DTY
DTY*30->IX
C6 lE
A
LDAB
"$1E
3D
MUL
18
XGDX
A
LDAB
CCNT
06 47
IX+CCNT-)CURH:CURL
3A
ABX
18
XGDX
97 43
A
STAA
CURH
07 42
A
STAB
CURL
BD C12S A
JSR
L2HCST
Store cursor address
96 48
A
LDAA
DTX
D6 4A
A
LDAB
DTWI<
10
SBA
DTX-DTWK->DATAR
97 41
A
STAA
DATAR
96 4B
A
LDAA
DOT SET
Store turning on/off data
97 40
A
STAA
INSTR
BD C103 A
JSR
L2HIST
Turn on/off 1 dot
39
RTS
Program module title is always followed by the entry point label
in parenthesis and description of entry and return arguments.
(b)
Entry point label.
$HITACHI
842
(5)
Subroutine:
Gives subroutine listing.
Example:
00217
00218
00219
00220
00221
00222A
00223A
00224A
00225A
00226A
00227A
00228A
00229A
00230A
00231A
00232A
00233A
00234A
00235A
00236A
00237A
CI03
CI06
CI08
CI0A
CI0C
CI0E
ClIO
C112
Cl14
Cl16
C119
Cl18
ClIO
CIIF
C121
C124
(a)
1************************************************
*
*
(a) *
NAME: L2HIST (STORE DISPLAY INSTRUCTION) *
(b
*
*
) " , l**~*********************************************
COEA ~ JSR
L2H8SY
Check LCTC busy fLag
04
A
LOAA
~$04
Set RS=l,R/W=O,E=O
02
A
STAA
PIOTR
05
A
LOAA
~$05
Set E=l
02
A
STAA
PIOTR
40
A
LOAA
INSTR
Output 1nstruct1on through port3
06
A
STAA
P30TR
04
A
LOAA
~$04
Set E=O
02
A
STAA
PIOTR
0002 A
CLR
PIOTR
Set RS=O
01
A
LOAA
~$01
Set E=l
02
A
STAA
PIOTR
41
A
LOAA
OATAR
Output data through port3
06
A
STAA
P30TR
0002 A
CLR
PIOTR
Set E=O
RTS
80
86
97
86
97
96
97
86
97
7F
86
97
96
97
7F
39
Subroutine title is followed by the entry point label in
parenthesis.
(b)
(6)
Entry Point label.
Data Table:
Describes data table used in the main program, program
modules and subroutines.
Example:
00254
00255
00256
00257
00258
00259A
00260A
00261A
00262A
00263A
00264A
00265A
00266A
00267A
00268A
00269A
00270A
************************************************
(a)
Cl3C
Cl3E
C140
C142
C144
C146
C148
C14A
C14C
C14E
C14F
C150
1**
DATA TA8LE
**
(b)", l:**********************************************:
00
01
02
03
04
08
09
OA
OB
01
01
01
~
FCB
A
FCB
A
FCB
A
FCB
A
FCB
A
FCB
A
FCB
A
FCB
A
FCB
A OTOATA FCB
A
FCB
A
FCB
$0,$32
$1,$07
$2,$10
$3,$lF
$4, $00
$8, $00
$9, $00
$A, $00
$B, $00
$01
$01
$01
*Instruct1on and datato 1n1tiaLize LCTC
*01spLay data
(a)
The title is always "DATA TABLE".
(b)
Data table label.
~HITACHI
843
(7)
vector Address:
Describes vector address allocation.
Example:
00311
00312
00313
00314
00315
00316
00317A
0031B
00319A
00320A
00321A
00322A
00323A
00324A
00325A
00326A
00327A
0032BA
00329A
00330
00331
FFEA
FFEA
FFEC
FFEE
FFFO
FFF2
FFF4
FFF6
FFFB
FFFA
FFFC
FFFE
COOO
COOO
COOO
COOO
COOO
COOO
COOO
COOO
COOO
COOO
COOO
1················································
*
*
*
VECTOR ADDRESSES
*
**************************************************
*
$FFEA
ORG
*
IRQ2
A
FOB
L2HMN
(a)
A
A
A
A
A
A
A
A
A
A
*
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
(b) FOB
L2HMN
L2HMN
L2HMN
L2HMN
L2HMN
L2HMN
L2HMN
L2HMN
L2HMN
L2HMN
CMI
TRAP
SID
TOI
DCI
ICI
IRQlIISF
SWI
NMI
RES
~
(a)
The title is always "VECTOR ADDRESSES".
(b)
Indicates the end of a program.
This can be moved, if necessary.
~HITACHI
844
8.
Program Module Execution
The programs
~ ..
APPLICATION NOTES have been written considering efficiency
and portability.
The following shows row to execute these programs and how
to modify them according to user requirements.
The procedure for calling programs in APPLICATION NOTES from user programs
is shown in figure 7.
All programs in APPLICATION NOTES are written as
subroutines and should be called as shown.
An example of a user program in
which a program in APPLICATION NOTES is called as a subroutine is shown in
figure 8.
USER PROGRAM
I
(1)
Initialize
before
execution
(2)
Program Module
(3)
(4)
Call
subroutine
(5)
(6)
I
necessary
registers
Figure 7.
Procedure for Calling Program Module in
APPLICATION NOTES
~HITACHI
845
User Program
I
I
I
I
I
LDAA
STAA
STAA
LDAA
STAA
JSR
#$00
PlDTR
P3DTR
) --- Init1a1izes before executing program module.
#$01
P3DDR
L2HINT
LDAA #$OF
STAA OOTSET
LDAA #$08
STAA DTX
LDAA#$02
STAA DTY
II JSR
If ---
L2HDST
BOlds entry arguments.
---- Calls program module.
Figure 8.
Example of
How
to Execute a Program Module
Explanation of figure 7.
(1) Initialize
Examples of items requiring initialization are input/output ports,
control registers and counters used by the program module.
Refer to
Program Module Sample Application for data details.
(2)
Save registers
The program modules use CPU registers for arithmetic operations
destroying the original contents.
saved if needed.
Thus register contents should be
Refer to the "CHANGES OF CPU REGISTERS AND FLAGS"
column in "SPECIFICATIONS" (Part 1 in the 3rd SECTION-PROGRAM MODULE
DESCRIPTION) for register status after a program module is executed.
(3)
Hold entry arguments
Holds entry arguments in CPU registers or
program module in the user program.
m~mory
before calling a
Refer to "ARGUMENTS" in
SPECIFICATIONS (FOrmat 1 in 3RD SECTION - Program Module) for details.
(4)
Call subroutine
Program module is called.
(5)
Process result
After a program module is executed, the results returned in the return
arguments must be processed as required.
~HITACHI
846
Refer to "ARGUMENTS" in
SPECIFICATIONS (Format I in 3RD SECTION - Program Module) for details.
(6)
Restore necessary registers
Registers saved in (2) should be restored here.
Note that when a
program module is used as a subroutine, the stack area shown in
SPECIFICATIONS (Format I in 3RD SECTION - Program Module) is necessary
in addition to the stack area required by the subroutine calls in the
user program.
When any subroutine is called, this stack area must be
reserved.
I
~HITACHI
847
System Application Examples
No. Item
Microcomputer
Function
HD6301YO
I/O Port
1
HD61830 (LM200)
Graphic Mode
2
Darlington
HD6301YO
Transistor Drive
(LED Dynamic Display)
3
Duty Control of
Pulse Output and
DA Conversion
4
Device
Page
HD6301YO
HD61830
MM6116
LM200
39
I/O Port (Portl)
Port6
HD6301YO
8-digi t X 8-seg ment LED
73
HD6301YO
(HD6303Y)
Timer2
Tout 3 pin
HD6301YO
86
Pulse width
Measurement
HD6301YO
(HD6303Y)
Timer 1
Tin Pin
HD6301YO
102
S
Input Pulse Count
HD6301YO
(HD6303Y)
Timer 2
TCLK pin
HD6301YO
112
6
8 x 4 Key Matrix
HD6301YO
I/O Port
( Port 3)
Port4
HD6301YO
8 x 4 key matrix
122
7
A/D Converter
(HA16613A) Control
HD6301YO
port3)
( portS
HD6301YO
HA16613A
137
( portl)
Port3
Timer 1
I/O port
IRQl pin
8
Standard Keyboard
Interface
HD6301YO
(HD6303Y)
I/O port (port6)
IS pin
HD6301YO
ASCII keyboard
146
9
Centronics
Interface
HD6301YO
(HD6303Y)
I/O port (port6)
IS pin, as pin
HD6301YO
Centronics interface
printer
160
10
Data Transfer with
Asynchronous SCI
HD6301YO
(HD6303Y)
I/O port (portS)
Asynchronous SCI
HD6301YO
Console typewriter
172
11
Liquid Crystal
Drived (HD61100A)
Control
HD6301YO
(HD6303Y)
I/O port (port2) HD6301YO
Clock synchronous HD61100A
SCI
10-digit X 8-segment LCD
12
External Expansion
HD6301YO
(HD6303Y)
External expansion function
HD6301YO
HD6321, HN27C64
HD63S0, HM6264
H2S71
200
13
Slow Device
Interface
HD63B01YO
MR pin
External expansion function
HD6301YO
HN482764G-3
HM6264LP
233
14
Low Power
Dissipation Mode
HD6301YO
Low power dissipation
mode (standbY)
\sleep
HD6301YO
247
188
I/O port (Portl)
port3
port6
lS
HA183SP Control
and Error Detection
HD6301YO
Trap function
HD6301YO
I/O port (PortS)HA183SP
port7
~HITACHI
848
264
SECTION 1.
1.1
HD61830 (IM200) GRAPHIC MODE
HARDWARE DESCRIPTION
1.1.1
Function
Initializes graphic mode and displays dot graphics on the LM200 liquid
crystal module.
1.1.2
Microcomputer Operation
The HD6301YO transfers display data to the dot matrix liquid crystal
graphic display controller LSI HD61830 (LCTC) from port 3 onto the LCTC
data bus (DBO
~
through port 1.
1.1.3
DE7), and transmits control signals E, R/W, and RS
Ports 1 and 3 are controlled by software.
Peripheral Devices
HD61830 LCTC:
Receives control signals and display data from the
HD6301YO and in turn controls the HM6116 Display RAM and LM200.
LM200 Liquid Crystal Module:
Receives graphic display data and control
signals from the HD61830 LCTC.
A resolution of 64 x 240 pixels is
provided in LM200 graphic mode.
In this application, the figures
"sn",
meaning HITACHI, are displayed.
~HITACHI
849
1.1.4
Circuit Diagram
LCTC control circuit is shown in figure 1-1.
MCU
HD680lYO
L C T C
: : Vee
RES
8 NMI
20 GND
15 CS
16 E
17 IVW
18 RS
7 STBY
88 Vee
f
:t-_2_:~"""--2'XTAL
8 EXTAL
22pF
Liquid crystal module
HD61880
o MPo
5 MP,
P,o
P"
P 12
P,.
PSI
P"
P"
P"
P"
P"
P"
50
09
08
58
57
56
55
5.
58
52
51
:~
26
25
20
28
22
21
89kO
DBo
DB,
DB,
DB,
DB.
DB,
DB,
DB,
7 R
6 C
8 CR
15pF
MAo
MA,
2
Display RAM
MA'r7I~-----------r~~~~__-r~~
MA, 60
MA. 59
MA, 58
MAo 57
MA, 56
MA, 55
MA·54
MA,
MDo
MD,
MD,
MD,
37
36
35
34
33
~g!E372~____________L-~~-L~~-/
MD, :~
MD,
WE" 13
Figure 1-1.
LCTC Control Circuit
~HITACHI
850
1.1.S
Pin Functions
Pin functions at the interface between the HD630lYO and LCTC are shown
in table 1-1.
Table 1-1.
Pin Functions
Pin Name
Active Level
(HD630lYO) Input/Output (High or Low) Function
Pin Name Program
(LCTC)
Label
P 10
Output
Pll
Output
High
Enables signal
E
High
Reads data
R/W
P12
Output
High
Selects instruction register RS
Pao
Pn
Input/Output
Input/Output ----
DBl
P32
Input/Output ----
DB2
P3 3
Input/Output
DB3
P34
Input/Output
DB ..
P3 s
Input/Output
DBs
P 36'
Input/Output ----
DB6
P37
Input/Output ----
DB7
-------------------------------------------Writes data
Low
Low
1.1.6
PlDTR
Selects data register
Data Lines
DBO
P3DTR
Hardware Operation
The timing chart for interfacing between the HD630lYO and each signal
is shown in figure 1-2.
@ and ® in
figure 1-2 show timing for read and
write.
(y Data from LCTC can be read during(yperiod.
@
Data can be written to LCTC at the falling edge of signal E.
I
~HITACHI
851
LCTC pin names _ _ _ _~
RS. R/W
E
DBo - DB7
(lID6 3 0 1YO-+ LCTC)
DBD - DB7
(HD63 01 YO+--LCTC)
HD6301YO~LCTC
Figure 1-2.
1.2
Interface
SOFTWARE DESCRIPTION
1.2.1
Program Module Configuration
The program module configuration for graphic display on the liquid
crystal module is shown in figure 1-3.
L2HMN
MAIN
PROGRAM
L 2HINT
I
L2HDCR
l2..
INITIALIZE
LCTC
I
I
L:...
CLEAR
DISPLAY RAM
Figure 1-3.
~.
"
/
L2HDST
I
DISPLAY
DOT
L:...
Program Module Configuration
~HITACHI
852
L2HMVE
I
MOVE
DISPLAY
~
1.2.2
Program Module Functions
Program module functions are summerized in table 1-2.
Table 1-2.
Program Module Functions
Program Module Name
Label
Function
0
MAIN PROGRAM
L2HMN
Demonstr ate s graphic display on LM200.
1
INITIALIZE LCTC
L2HINT
Initializes LCTC for graphic mode.
2
CLEAR DISPLAY RAM
L2HDCR
Clears display RAM to clear display.
No.
3
DISPLAY DOT
L2HDST
Turns on and off 1 dot specified by row or
column coordinate.
4
MOVE DISPLAY
L2HMVE
Moves dot display up, down, left, or right.
1.2.3
Program Module Process Flow (Main Program)
The following flowchart (figure 1-4) demonstrates the process for
displaying graphics on the LM200 liquid crystal display, using the
modules described above.
Figure 1-5 shows this applications display.
I
~HITACHI
853
Main Program
----{ Initialize stack pointer.
Initialize port 1 and port 3.
Clear internal RAM.
____ [ Execute L2HINT to initialize LCTC
for graphic mode.
----I
Execute L2HDCR to clear display RAM.
____{LOad starting address of the data table,
where display data is stored, into IX.
----[ Load display data into ACCA.
____{save data table address of display
data.
----{Test if display data is completed.
----{Test if 1 dot is turned on or off.
----{Turn on 1 dot.
U-_--,,-_-'-'
----{store instruction to turn off 1 dot.
----{ Turn off 1 dot.
____{ Restore data table address of
display data.
____ { Increment data table address of
display data.
Figure 1-4.
Main Program Flowchart
~HITACHI
854
~
I~~
[.... .
11
.g
•
• •••••
•••• • •
LO
••••
•••••.1
14 dot~1 .I.
•
•
••
5 dots
1 dot
Figure 1-5.
Example of L2HMN Execution
I
•
HITACHI
855
1.3
PROGRAM MODULE DESCRIPTION
Program Module Name: INITIALIZE LCTC
Label: L2HINT
MCU/MPU: HD6301YO
Function:
Initializes LCTC for graphic mode.
Arguments:
Changes in CPU
Speci fica tions.:
Registers and Flags:
None
ACCD
ACCA ACCB
x
I •
IX
x
ROM (Bytes) : 90
RAM
(Bytes) : 2
Stack (Bytes) : 4
No. of cycles: 123
Reentrant: No
C
x
V
x
Z
N
x
x
•
x :
I
H
•
•
Relocatable: No
Interrupt OK?: Yes
Not affected
Undefined
Resul t
Description:
1.
Function Details
a.
L2HINT has no arguments.
b.
Instruction and data in table 1-3 are written to LCTC to initialize LCTC
for graphic mode.
Specifications Notes:
1-
2.
Values in "Specifications" include values for subroutines called by L2HINT.
"No. of cycles" in "Specifications" indicates the number of cycles required
when L2HBSY is executed in the minimum number of cycles (no waiting for LM200).
~HITACHI
856
Program Module Name: INITIALIZE LCTC
~M_C_U_/_M_P_U_:_HD
__6_3_0_1_Y_0______
~ I~L_a_b_e_l_:
__L_2_H_I_NT
______
~
Description:
Table 1-3.
Instruction and Data to initialize LCTC.
Instruction
Data
Function
$00
$32
Selects display on, master mode, graphic mode.
$01
$07
Displays 8-bit data sent from RAM.
$02
$lD
Defines number of horizontal bytes.
$03
$lF
Defines duty rate as 1/32.
$04
$00
Selects cursor position. (Note)
$08
$00
Selects display starting address to $0000.
$09
$00
$OA
$00
$OB
$00
Note:
c.
Display initialized £or graphic mode, cursor is not displayed.
L2HINT calls subroutines shown in table 1-4.
Table 1-4.
2.
Selects cursor address to $0000.
Subroutines Called by L2HINT
Subroutine Name
Label
Function
Stores Display
Instruction
L2HIST
Writes data LCTC instruction register and data
register.
Check Busy
Flag
L2HBSY
Checks LCTC busy flag.
User Notes
The following procedure must be executed be£ore L2HDCR execution.
3.
a..
Reserve instructions and data in a data table.
b.
Select DDR of port 1 and port 3 as output.
I
RAM Allocation
RAM
Label b7
bO
INSTRIr-----------,
Description
DATAR
Data to be written to LCTC data register
~.
__________
~
Data to be written to LCTC instruction register
~HITACHI
857
I. .
Program Module Name: INITIALIZE LCTC
....M_C_U_I_M_P_U_:_HD_6_3_0_1_Y_O_ _---' L_a_b_e_l_·:_L_2_H_I_NT
_ _ _......
Description:
4.
Sample Application
I
I
I
I
CLRA
STAA
STAA
LDAA
STAA
STAA
P1DTR
P3DTR
#$01
P1DDR
P3DDR
J S R
L2HINT
I
LCTCl FCB
I
I
5.
$0, $32
}.....
Initialize port 1 and port 3.
••••• Call L2HINT
I
•••.• Reserve data table
Basic Operation
a.
To initialize graphic mode, instructions and data in table 1-3 are written
to LCTC instruction register and data register, respectively.
b.
Instruction register and data register are used in pairs, and are selected
by RS signal.
c.
Instruction and data in table 1-3 are held in INSTR(RAM) and DATAR(RAM)
using index addressing mode. I~ L2HIST is called, data is written to LCTC
instruction register and data register.
d.
In L2HINT, port 1 controls R/W, E, and RS signals •
•
858
HITACHI
C~
L-p_r_o_g_r_a_m__M_o_d_u_l_e__N_am
__e__:_I_N_I_T_I_AL
__I_Z_E__L_CT
__
LM
__
C_U_/_M_P_U_:_HD
__6_3_0_l_Y_o______
_
~I~L
ab
__
e_l_:_L_2_H_I_NT
________
~
Flowchart:
Load starting address of data table,
-- { where instructions code and data are
stored, into address pointer.
__ {store instruction code in L2HIST
entry argument.
- - {Increment address pointer of data table.
---[store data in L2HIST entry argument.
__ {Execute L2HIST to write instruction code
and data to LCTC and initialize it.
---[Increment address pointer of data table.
--{ Test if LCTC initializing is completed.
$HITACHI
859
Program Module Name: CLEAR DISPLAY
RAM
MCU/MPU: HD6301YO
Label: L2HDCR
Function:
Stores $00 in display RAM to clear display on LM200.
Arguments:
Changes in CPU
Specifications:
Registers and Flags:
None
ACCD
ACCA ACCB
x
I •
ROM (Bytes): 133
RAM (Bytes): 6
Stack (Bytes): 6
IX
•
No. of cycles: 211474
Reentrant: No
•
x
t
:
C
v
x
x
Z
x
N
x
I
H
•
•
Relocatable: No
Interrupt OK?: Yes
Not affected
Undefined
Result
Description:
1.
Function Details
a.
L2HDCR has no arguments.
b.
After L2HDCR execution, display or LM200 is cleared.
c.
L2HDCR calls subroutines shown in table 1-5.
Specifications Notes:
1.
2.
Values in "Specifications" include values for subroutines called by L2HDCR.
"No. of cycles" in "Specifications" indicates the number of cycles required
when L2HBSY is executed in the minimum number of cycles (no waiting for LM200).
~HITACHI
860
Program Module Name: CLEAR DISPLAY
MCU/MPU:
HD6301YO
RAM
IL O b01'
L2HDCR
Description:
Table 1-5.
2.
Subroutines called by L2llDCR
Subroutine Name
Label
Function
Store Cursor
Address
L2HCST
Stores LCTC cursor address.
Continuous
Display
L2HDSP
Continuously displays on LM200.
Store Display
Instruction
L2HIST
Stores data in LCTC instruction register
and data register.
Check Busy
Flag
L2HBSY
Checks LCTC busy flag.
User Notes
The following procedure must be executed before L2HDCR execution.
3.
a.
Select DDR of port 1 and port 3 as output.
b.
Initialize LCTC display mode.
RAM Allocation
RAM
Label
Description
bO
b7
}
CURL
CURH
DCOUNT
-
Upper
Lower
DATA
4.
-
Lower byte of cursor address
}
Upper byte of cursor address
}
Counter for repeated
}
Display data
I
Sample Application
"
CLRA
STAA
STAA
LDAA
STAA
STAA
JSR
PIDTR
P3DTR
#$01
PIDDR
P3DDR
L2HINT
JSR
L2HDCR
~
II
•.... Initialize port 1 and port 3.
Call L2HINT to initialize LCTC.
Call L2HDCR
~HITACHI
861
Program Module Name: CLEAR DISPLAY
MCU/MPU: HD630lYO
RAM
I
Label ,
L2HDCR
Description:
5.
Basic Operation
a.
When displaying graphics on LM200, cursor address and display data are
written to LCTC.
b.
L2HCTS is called to store $0000 in cursor address.
c.
LM200 uses 1920 bytes in 1 display screen.
d.
L2HDSP is called to store $00 throughout RAM so that display on.LM200
can be cleared. L2HDSP uses auto-increment function for cursor address.
~HITACHI
862
Program Module Name: CLEAR DISPLAY
MCU/MPU:
RAM
lID6301YO
I~
L2lIDCR
Flowchart:
__ Jclear L2HCST entry arguments to initialize
llcursor address to $0000.
__ {Execute L2HCST and initialize cursor
address to $0000.
Store 1920 in L2lIDSP entry argument to
-- { repeat writing 1920 byte data in display
RAM.
__ {store "$00" in L2lIDSP entry argument
to clear display RAM.
---[Execute L2lIDSP to Clear'LM200 Display.
I
~HITACHI
863
Program Module Name:
Label: L2HDST
MCU/MPU: HD6301YO
DISPLAY DOT
Function:
Turns on or off 1 dot specified by row and column coordinates in entry arguments.
Arguments:
Changes in CPU
Storage
Location
contents
Entry Turn on/off DOT SET
(RAM)
indicator
No. of
Bytes
ACCD
ACCA ACCB
1
Dot column
coordinate
DTX
(RAM)
1
Dot row
coordinate
DTY
(RAM)
1
Specifications:
Registers and Flags:
x
x
ROM (Bytes): 134
RAM (Bytes): 9
Stack (Bytes): 6
IX
No. of cycles: 513
x
Reentrant: No
Returns
---
--
•
x
:
c
v
Relocatable: No
x
x
Interrupt OK?: Yes
Z
N
x
x
I
H
•
•
Not affected
Undefined
Result
Description:
1.
Function Details
a.
Argument details
DOTSET(RAM): Data to indicate turning on or off 1 dot.
DOTSET(RAM)=$OE : Turn off 1 dot.
DOTSET(RAM)=$OF : Turn on 1 dot.
DTX(RAM)
Dot column coordinate
in hexadecimal number.
Dot row coordinate in
DTY(RAM)
hexadecimal number.
Specifications Notes:
1. Values in "Specifications" include values for subroutines called by L2HDST.
2. "No. of cycles" in "Specifications" indicates the number of cycles required
when L2HBSY is executed in the minimum number of cycles (no waiting for LM200).
~HITACHI
864
Program Module Name:
DISPLAY DOT
---I1\. .
LM_C_U_I_M_P_U_:_HD_6_3_0_1_Y_O_ _
L_a_b_e_l_:_L_2_HD_S_T_ __
Description:
b.
Example of L2HDST execution is shown in figure 1-6. If entry arguments
are as shown in partQ) of figure 1-6, 1 dot is displayed as shown in part
@ of figure 1-6.
DOTSET (RAM)
b7 DOTSET bO
( Turn on/Off)
data ($OF)
DTX (RAM)
CD Entry
I
Dot cOlumn)
( coordinate
arguments
°DTX:
F
I
($03)
DTY (RAM)
Dot row ~
( coordinate
($02)
10:
2
+
@
Result
Figure 1-6.
c.
L2HDST calls subroutines shown in table 1-6.
Table 1-6.
2.
Example of L2HDST Execution
Subroutines Called by L2HDST
Subroutine Name
Label
Function
Store Cursor
Address
L2HCST
Stores LCTC cursor address.
Continuous
Display
L2HIST
Stores data in LCTC instruction register and data
register.
Check Busy Flag
L2HBSY
Checks LCTC busy flag.
User Notes
The following procedure must be executed before L2HDST execution.
a.
Select DDR of port 1 and port 3 as output.
b.
Initialize LCTC display mode.
c.
Store entry arguments.
~HITACHI
865
L-p_r_o_g_r_arn
__
M_o_d_ll_l_e_N_arn_e_:_D_I_S_P_LA_Y_D_O_T_ _...J ..M_C_U_I_M_P_U_:_HD_6_3_0_l_Y_0_ _---' 1
...L_a_b_e_l_:_L_2_HD_S_T_ _---'
Description:
3.
RAM Allocation
Label
Description
RAM
bO
b7
INSTR
DATAR
DTX
DTY
CURH
CURL
Data to be written to LCTC instruction register
}
}
Dot column coordinate
}
}
Upper byte of cursor address
}
}
}
CCNT
DTWK
DOTSET
4.
}
}
Data to be written to LCTC data register
Dot row coordinate
Lower byte of cursor address
Work area for calculating cursor address based
on column coordinate
Work area for obtaining 1 dot to be turned
on/off
Data to indicate turning on/off 1 dot
Sample Application
I
I
I
I
CLRA
STAA
STAA
LDAA
STAA
STAA
JSR
IDAA
STAA
LDAA
STAA
IDAA
STAA
I
JSR
PlDTR
P3DTR
#$01
PlDDR
P3DDR
L2HINT
}
Call L2HINT to initialize LCTC
'$OFSET )
DOT
#$08
DTX
#$02
DTY
L2HDST
Initialize port 1 and port 3.
II
•••.. Store entry arguments
.•••• Call L2HDST
~HITACHI
866
Program Module Name: DISPLAY DOT
MCU/MPU:HD6301YO
Label: L2HDST
Description:
5.
Basic Operation
a.
The formula below calculates cursor address and dot to be turned on/off,
based on column and row coordinates.
Row coordinate x 30 + I (Column coordinate /I $FS) /sl
Cursor address ..•••.••.••..•.••.• (Formula 1)
Column coordinate - (Column coordinate /I $FS)
Number of bits •.••••..••••.•.•..• (Formula 2)
b.
After cursor address is calculated by Formula 1, upper byte and lower
byte of cursor address are held in CURH(RAM) and CURL(RAM), respectively.
If L2HCST is executed, cursor address is written to LCTC.
c.
If number of bits obtained by Formula 2 is held in DATAR(RAM) , L2HIST
execution turns on or off 1 dot.
I
~HITACHI
867
Program Module Name: DISPLAY DOT
MCU/MPU: HD630lYO
---
/
Label: L2HDST
Flowchart:
Calculate cursor address using
(formula 1) in (5) Basic Operation.
(ACCD)-( IX)
(ACCD)-+
CURH:CURL
--{
Execute L2HCST to store cursor address
in LCTC register.
(DTX)-+ACCA
Calculate bit location using
(formula 2) in (5) Basic Operation
and store result in L2HIST entry
argument.
(DTWK)-+ACCB
(ACCA)-(ACCB)
-+DATAR
--{
--{
Store turn on/off instruction in L2HIST
entry argument.
Execute L2HIST to turn on/off 1 dot.
~HITACHI
868
MCU/MPU: HD6301YO
Program Module Name: MOVE DISPLAY
Label:L2HMVE
Function:
Moves current displayed dot up, down, left, or right 1 dot.
Changes in CPU
Arguments:
Storage
Location
Contents
Entry
Moving
direction
No. of
Bytes
ACCA
Specifications:
Registers and Flags:
ACCD
ACCA ACCB
x
x
1
IX
x
ROM (Bytes): 200
RAM (Bytes):
8
No. of cycles:
560
Reentrant:
Returns
•
x
:
c
v
x
x
z
N
x
x
I
H
•
•
9
Stack (Bytes):
No
Relocatable: No
Interrupt OK?:
Yes
Not affected
Undefined
Resul t
Description:
1.
Function Details
a.
Argument details
ACCA : Data indicatinq which direction 1 dot will be moved.
ACCA=$Ol
ACCA=$02
ACCA=$03
ACCA=$04
Specifications Notes:
2.
Move
Move
Move
Move
1.
1
1
1
1
dot
dot
dot
dot
I
right.
left.
down.
up.
Values in "Specifications" include values for other
program modules and subroutines called by L2HMVE.
"No. of cycles" in "Specifications" indicates the number of cycles required when
L2HBSY is executed in the minimum number of cycles (no waiting for LM200).
~HITACHI
869
Program Module Name: MOVE DISPLAY
L2
....M_C_U_/_M_P_U_:_HD_6_3_0_1_Y_O_ _---' 1
....L_a_b_e_l_:__ HM_VE
_ _ _.....J
Description:
b.
c.
Example of L2HMVE execution is shown in figure 1-7. If entry argument
is as shown in part
of figure 1-7, dots are displayed as shown in part
® of figure 1-7.
CD
L2HDST calls other program modules and subroutines shown in table 1-7.
LM200 display before
L2HMVE
execution
(1,3)
CD
Entry argument
ACCA b 7 ACCA bO
{ (Moving~
dir~:~ion~l
@
IM200
display
Result
after
L2HMVE
execution
(2,3)
Figure 1-7.
Table 1-7.
2.
Example of L2HMVE Execution
Program !-1odules and Subroutines Called by L2HMVE
Program Module/
Subroutine Name
Label
Function
Display Dot
L2HDST
Turns on/off 1 dot.
Store Cursor
Address
L2HCST
Stores LCTC cursor address.
Continuous
Display
L2HIST
Stores data in LCTC instruction register and
data register.
Check Busy
Flag
L2HBSY
Checks LCTC busy flag.
User Notes
The following procedure must be executed before L2HMVE execution.
a.
Select DDR of port 1 and port 3 as output.
b.
Initialize LCTC display mode.
c.
Load entry argument.
~HITACHI
870
~p_r_o_g_r_am
___M_o_d_u_l_e__N_a_m_e_'_'_M_O_VE
___D
__
I_S_P_LA
__
Y__
~ ~M
__
C_U_/_M_P_U_:_HD
__6_3_0_l_y_0______
~1~L_a_b_.
e__
l_:__L_2_HM
__VE
______
~
Description:
3.
RAM Allocation
Description
RAM
Label
bO
b7
INSTR
DATAR
DTX
DTY
CURH
CURL
Data to be written to LCTC instruction register
}
}
}
Dot row coordinate
}
}
}
CCNT
DTWK
DOT SET
4.
}
}
}
Data to be written to LCTC data register
Dot column coordinate
upper byte of cursor address
Lower byte of cursor address
Work area for calculating cursor address based
on column coordinate
Work area for obtaining 1 dot to be turned
on/off
Data to indicate turning on/off 1 dot
Sample Application
I
I
II
5.
CLRA
STAA
STAA
LDAA
STAA
STAA
JSR
LDAA
P1DTR
P3DTR
#$01
PlDDR
P3DDR
L2HINT
#$01
JSR
L2HMVE
1
II
..... Initialize port 1 and port 3.
Call L2HINT to initialize LCTC.
Load entry argument
Call L2HMVE
Basic Operation
a.
After moving determined direction, DTX(RAM) pointing to dot column
coordinate or DTY(RAM) pointing to row coordinate are incremented or
decremented.
b.
L2HDST is called to display 1 dot specified in (a).
~HITACHI
871
L-p_r_o_g_r_a_m__M_o_d_u_l_e__N_am
__e__
:_M_O_V_E__D_I_S_P_LA
__y____
--{
--{
~ ~M
__
C_U_/M
__P_U_:_H_D_6_3_0_l_y_O______
~ ~IL__
ab
__
e_l_:__L_2_HM
__V_E______
Test if move 1 dot to right.
Test if row coordinate is right
most.
--{ Increment row coordinate.
Test if move 1 dot to left.
Test if row coordinate is left.
--{ most.
---{ Decrement row coordinate.
Test if move 1 dot down.
--{
Test if column coordinate is
down most.
--{ Increment column coordinate.
Test if move 1 dot
up.
Test if column
coordinate
is up most.
Decrement column
coordinate.
L2HME4~--------~-----------L----------~
__ {
~HITACHI
872
Execute L2HDST
to rutn on 1 dot.
~
1.4
SUBROUTINE DESCRIPTION
Subroutine Name:
CONTINUOUS DISPLAY
MCULMPU:
Label:
HD6301YO
L2HDSP
Function:
Displays specified bytes continuously from the present cursor address.
Basic Operation:
1.
DCOUNT(RAM) is used as a counter to execute L2HIST, writing display data to
LcrC until counter is "0".
2.
L2HDSP uses auto-increment function of cursor address.
Program Module Using This Subroutine: L2HDCR
Flowchart:
__ { Store instruction to store display
data in L2HIST entry argument.
__ { Store display data in L2HIST entry
argument.
__ {Execute L2HIST to write display data
in LCTC.
(ACCD)-$Ol
DCOUNT : DCOUNT+1
-+
Decrement counter for continuous
display.
I
(DCOONf : DCOUNT
+1)#0
display is
~HITACHI
873
Subroutine Name: STORE CURSOR
ADDRESS
MCULMPU: HD630lYO
Label: L2HCST
Function:
Writes upper and lower bytes of cursor address to LCTC.
Basic Operation:
L2HIST is called twice since lower byte of cursor address is written to LCTC first,
and then upper byte to LCTC.
Program Module Using This Subroutine:
L2HDCR, L2HDST, L2HMVE
Flowchart:
__ {store instruction data for loading lower
cursor address.
- - {stores lower cursor address.
__ {write instruction and ,address into
LCTC register.
__ { Store instruction data for loading upper
cursor address.
"
--{store upper cursor address.
__ {write instruction and address into
LCTC register.
~HITACHI
874
Subroutine Name:
MCULMPU:
STORE DISPLAY
INSTRUCTION
HD630lYO
Label: L2HIST
Function:
Writes instruction and data to LCTC.
Basic Operation:
1.
LCTC busy flag is checked.
2.
Data is written to LCTC through port 1 controlling DS, R/W, E signals of LCTC.
Program Module Using This Subroutine:
L2HINT, L2HDCR, L2HDST, L2HMVE
Flowchart:
- - { Execute L2HBSY to check busy flag.
__ { Set signal RS to High to select
instruction register of LCTC.
- - { Set signal E to High.
__ {output instruction from port 3 to
LCTC register.
- - { Set signal E to low.
__ { Set signal RS to Low to select data
register of LCTC.
I
--{ Set signal E to High.
__ {output data from port 3 to LCTC
register.
- - { Seg signal E to Low.
~HITACHI
875
Subroutine" Name:
McuLMPU: !ID6301YO
CHECK BUSY FLAG
Label: L2HBSY
Function:
Tests if LCTC is in operation, and waits until LCTC is ready.
Basic Operation:
1.
Since the microcomputer cannot access LCTC when LCTC is in operation,
microcomputer determines LCTC condition by checking busy flag.
2.
Busy flag is read through port 1 controlling RS, R/W, E signals.
Program Module Using This Subroutine: L2HINT, L2HDCR, L2HDST, L2HMVE
Flowchart:
--{ Select port 3 as input to read busy flag.
--{ Set signals
RS
and R/W to High.
--{ Set signal E to High.
( P8DTR)-ACCA
- - { Read busy flag.
$06-PIDTR
--{ Set signal E to Low.
(ACCA)
--1
Check bu'Y flag.
--{ Select port 3 as output.
~HITACHI
876
1.5
PROGRAM LISTING
00001
00002
00003
00004A
00005
00006A
00007A
OOOOBA
00009A
00010A
OOOllA
00012A
>I<
>1<>1<>1<>1<
RAt·1 ALLOCATION
>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<
>I<
0040
0040
0041
0042
0043
0044
0046
0047
00013~) 004B
00014A 0049
0001SA 004A
00016A 004B
00017
0001B
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030A COOO
00031
00032A COOO
00033A C003
00034A C004
0003SA C006
00036A C008
00037A COOA
; 00038A COOC
00039A COOF.
00040A COOF
00041A C012
00042A C014
00043A C01S
00044A C017
0004SA COlA
00046A COlD
00047A C020
00048A C022
00049A C023
00050A C02S
OOOSlA C027
000S2A C029
00053A C02B
000S4A C02D
OOOSSA C02F
000S6A C032
000S7A C033
ORG
$40
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
1
1
1
1
2
1
1
1
1
1
1
>I<
0001
0001
0001
0001
0002
0001
0001
0001
0001
0001
0001
A
A
A
A
A
A
A
A
A
A
A
INSTR
DATAR
CURL
CURH
DCOUNT
DATA
CCNT
DTX
DTY
DTWI<
DOT SET
LCTC instruction register data
LCTC data register data
Lower byte of cursor address
Upper byte of cursor address
Counter for continuous dispLay
DispLay data
Wor!< area for cursor address
Dot coLumn coordinate
Dot row coordinate
Wor'!< area for turning onloff data
Turning onloff data
>I<
>1<>1<>1<>1<
SYMBOL DEFINITTIONS
>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<
>I<
0000
0002
0004
0006
A
A
A
A
PlDDR
PIOTR
P3DOR
P3DTR
EDU
EQU
EDU
EDU
$00
$02
$04
$06
Pod
data
Por't
data
Pod 3 data
POl't 3 data
dir'ection register
register
dir'ection register
r'eg i ster'
***********~:***~:*:k**********~;~:******************
>I<
>I<
MAIN PROGRAM
>I<
:
L2HMN
>I<
>I<
>I<
***********~:**~;~;*:I(***~C***:~****~:k**~***********~*
>I<
ORG
$COOO
LOS
CLRA
STAA
STA(-)
LOM
jj$13F
InitiaLize stac!< pointer
PIOTR
P30TR
jj$Ol
P10DR
P3DDR
InitiaLize por't 1
InitiaLize pod 3
Select pod ::; as output
>I<
8E
4F
97
97
86
97
9'(
4F
CE
013F
A L2HMN
02
06
01
00
04
A
A
A
A
A
STA!~
STA(~
CLRA
LOX
OOCO A
~\'( 3F
A L2HMNl STAA
DEX
09
BNE
26 F8 C012
SD C052 A
JSR
JSR
SD C030 A
LDX
CE C14E A
A6 00
A L2HMN2 LDAA
PSHX
3C
CMPA
81 FF
A
27 14 C03B
SED
A
CMPA
81 00
BNE
26 OB C036
A
LDAA
86 OE
97 4B
STAA
A
JSR
BO C068 ~\
L.2HMN3 PULX
38
INX
08
jj$CO
$3F,
CLea,' RAM
X
L2H~1N1
L2HINT
L2HDCR
jjDTDATA
O.X
jj$FF
PEND
jjOO
L2HMN4
jj$OE
DOTSET
L2HOST
CLear display RAM
InitiaLize LCTC
Load data table starting address
Load dispLay data into ACCA
Save data tabLe address
loop until dispLay is cOlilPLeted
Test if 1 dot is tUI'I"led on/off
Br'anc!'l i f tUI'lled on
Stor'e instr'uction to lu,'n off
I
Turn off 1 dot
Restore data table addr'ess
Increment data tab Le addr'ess
~HITACHI
877
000S8A
000S9A
00060A
00061A
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072A
00073A
00074A
0007SA
00076A
00077A
00078A
00079A
OOOBO
00081
000B2
00083
00084
00085
00086
00087
0008B
00089
00090A
00091A
00092A
00093A
00094A
00095A
00096A
00097A
00098A
00099A
00100A
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110
00111
00112
00113A
00114A
C034
C036
C039
C038
20
BD
20
20
BRA
EA C020
C093 A L2HMN4 JSR
[~HA
F7 C032
FE C03B PEND
BRA
*>I<
L2HMN2
L2HMVE
Turn on 1 dot
L2Ht~N3
PEND
End of program
NAME : L2HDCR (CLEAR RAM)
>I<
*
*********~******************l~********:k****)~***~;*
>I<
>I<
>I<
C03D
C040
C043
C046
C049
C04B
C04E
COS1
7F
7F
BD
CC
DD
7F
BD
39
*
*
*
ENrRY : NOTHING
RETURNS: NOTHING
********:k*********************************)k***)~.~*
0043
0042
C12S
0780
44
0046
CODS
A L2HDCR CLR
A
CLR
A
JSR
A
LDD
A
STD
A
CLR
A
JSR
RTS
CURH
CURL
L2HCST
Load SOOOO into cursor address
~1920
Wr'He SOOOO to cur'SOl' addl'ess
Load data to repeat writing 1920 bytes
DCOUNT
DATA
L2HDSP
Load SOO
CLear display
******************~(***:~****************'~)k******:~
*>I<
*
*
*
*
COS2
COS5
COS7
COS9
COSA
COSC
COSE
C061
C062
C065
C067
CE
A6
97
08
A6
97
BD
08
8C
26
39
Cl3C
00
40
'I'
NAME: L2HINT (INITIALAIZE LCTC)
'"
'"
*
"*
ENTRY : NOTHING
RETURNS : NOTHING
******************************************~(*******
A L2HINT LOX
A L2HITl LDAA
STAA
A
INX
A
LDAA
00
41
STAA
A
JSR
C103 A
INX
C14E A
CPX
EE COSS
BNE
RTS
IILCTCI
O.X
INSTR
O.X
DATAR
L2HIST
Load data tabLe star't' ng addr'ess
Store LCTC instruction·
Increment data tabLe address
Store LCTC data
Write instructin and data to LCTC
Increment data tabLe address
IlLCTCl+18 Test if LCTC is initialized
L2HIT1
************************************************
*
*
NAME : L2HDST (DISPLAY DOT)
*
*
**************************************************
*
*
DTX(DOT COLUMN COORDINATE)
ENTRY
C068 96 48
C06A 84 F8
*
*
DTY(DOT ROW COORDINATE)
*
*
DOTSET(TURN ON/OFF INDICATOR)
*
*
RETURNS
NOTHING
*
*
*
*
************************************************
A L2HDST LDAA
A
ANDA
DTX
IISF8
Load coLumn coordinate
DTX AND SF8->DTWK
~HITACHI
878
*
*
00115A
OO1l6A
00117A
001l8A
00119A
00120A
00121A
00122A
00123A
00124A
00125A
00126A
00127A
00128A
00129A
00130A
00131A
00132A
00133A
00134A
00135A
00136A
00137A
00138
00139
00140
00141
00142
00143
00144
00145
00146
00147
00148A
00149A
00150A
00151A
00152A
00153A
00154A
00155A
00156A
00157A
00158A
00159A
00160A
00161A
00162A
00163A
00164A
00165A
00166A
00167A
00168A
00169A
00170A
00171A
C06C
C06E
C06F
C070
C071
C073
C075
C077
C078
C079
C078
C07C
C070
C07F
C081
C084
C086
COB8
COB9
C088
C080
COBF
C092
97
44
44
44
97
96
C6
30
18
06
3A
18
97
07
80
96
06
10
97
96
97
80
39
4A
A
47
49
IE
A
A
A
47
A
43
42
C125
48
4A
A
A
A
A
A
41
48
40
C103
A
A
A
A
STAA
LSRA
LSRA
LSRA
STAA
LDAA
LDA8
MUL
XGOX
LDA8
A8X
XGDX
STAA
STA8
JSR
LDAA
LDA8
SBA
STAA
LDAA
STAA
JSR
RTS
DTWI(
(OTX AND $F8)/B-)CCNT
CCNT
DTY
lI$lE
DTY>I<30-)IX
CCNT
IX+CCNT-)CURH:CURL
CURH
CURL
L2HCST
DTX
DTWI(
Store cursor address
DATAR
DOT SET
INSTR
L2HIST
Store turning on/off data
DTX-DTWI(-)DATAR
Turn on/off 1 dot
>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<******
**
>I<
NAME : L2HMVE (MOVE DISPLAY)
**
*
****>1<*****>1<*>1<*>1<>1<****>1<*****************>1<*********
>I<
C093
C095
C097
C099
C098
C090
C09E
COAO
COA2
COA4
COA6
COA8
COAA
COAC
COAO
COAF
COB1
C083
C08S
C087
C089
C088
C08C
C08E
BIOI
26 08
06 48
C1 EF
27 37
5C
07 48
20 28
81 02
26 08
06 48
C1 00
27 28
SA
07 48
20 1C
B1 03
26 08
06 49
C1 3F
27 19
5C
07 49
20 00
>I<
ENTRY : ACCA (MOVING DIRECTION)
*
*
RETURNS : NOTHING
*
*
*
*
****>1<*************>1<****>1<******>1<********>1<*******>1<
A L2HMVE CMPA
BNE
COA2
LDAB
A
CMPB
A
BEQ
C004
INC8
STAB
A
BRA
COCO
A L2HMEl CMPA
BNE
C081
LDAB
A
CMPB
A
BEQ
C004
OECB
STAB
A
BRA
COCO
A L2HME2 CMPA
BNE
COCO
LDAB
A
CMP8
A
BEQ
COD4
INCB
STAB
A
BRA
COCO
11$01
L2HMEl
DTX
11239
L2HMES
DTX
L2HME4
11$02
L2HME2
OTX
1100
L2HMES
DTX
L2HME4
11$03
L2HME3
OTY
1163
L2HMES
Test if move 1 dot right
Test if DTX is right most
Increment DTX
Test if move 1 dot Left
Test if OTX is Left most
Decrement DTX
Test if move 1 dot down
Test if DTY is bottom
Increment DTY
I
DTY
L2HME4
~HITACHI
879
00172A
00173A
00174A
00175A
00176A
00177A
00178A
00179A
00180A
00181A
00182A
00183
00184
00185
00186
00187
00188A
00189A
00190A
00191A
00192A
00193A
00194A
00195A
00196A
00197A
0019B
00199
00200
00201
00202
00203A
00204A
00205A
00206A
00207A
00208A
00209A
00210A
00211A
00212A
00213A
00214A
00215A
00216A
00217
00218
00219
00220
00221
00222A
00223A
00224A
00225A
00226A
00227A
00228A
COCO
COC2
COC4
COC6
COC8
COCA
COCB
COCD
COCF
CODI
COD4
81
26
D6
C1
27
5A
D7
86
97
BD
39
04
A L2HME3 CMPA
10 COD4
BNE
49
A
LDAB
A
CMPB
00
BEQ
OA COD4
DECB
49
A
STAB
OF
A L2HME4 LDAA
4B
STAA
A
C068 A
JSR
L2HME5 RTS
t\$04
L2HME5
DTY
t\00
L2HME5
DTY
t\$OF
DOTSET
L2HDST
Test if move 1 dot UP
Test if DTY is top
Dec r'ement DTY
Stot'e tur'n i ng on instruction
Turn on 1 dot
************************************************
*
*
NAME : L2HDSP (CONTINUOUS DISPLAY)
*
*
*
*
COD5
COD7
COD9
CODB
CODD
COEO
COE2
COE5
COE7
COE9
86
97
96
97
BD
DC
B3
DD
24
39
****~*******************************************
OC
A L2HD5P LDAA
STAA
40
A
LOAA
46
A
STAA
41
A
C103 A L2HDW1 JSR
LDD
44
A
SUBD
0001 A
A
STD
44
BCC
F4 CODD
RTS
t\$OC
INSTR
DATA
DATAR
L2HIST
DCOUNT
t\$01
DCOUNT
L2HDP1
Store instruction
Store dispLay data
Write dispLay data to LCTC
Decrement counter
Test if dispLay is compLeted
********~***************************************
COEA
COEB
COED
COEF
COFI
COF3
COF5
COF?
COF9
COFB
COFC
COFE
C100
C102
4F
97
86
97
86
97
96
C6
D7
48
25
86
97
39
*
*
NAME : L2HBSY (CHECK BUSY FLAG)
*
*
******~*******************************************
L2HBS,Y CLRA
A
STAA
LDAA
A
STAA
A
A L2HBY1 LDAA
STAA
A
A
LDAA
A
LDAB
A
STAB
ASLA
F3 COF!
BCS
01
A
LDAA
STAA
04
A
RTS
04
06
02
07
02
06
06
02
P3DDR
t\$06
P1DTR
t\$07
PlDTR
P3DTR
11$06
PlDTR
L2HBYl
t\$01
P3DDR
SeLect port 3 as input
Set RS=l.R/W=l.E=O
Read LCTC busy fLag
Set E=O
Set busy fLag to bit C
Test if busy fLag=O ?
SeLect port 3 as output
************************************************
C103
C106
C108
C10A
ClOC
C10E
CllO
BD
86
97
86
97
96
97
COEA
04
02
05
02
40
06
** NAME: L2HIST (STORE DISPLAY INSTRUCTION) **
*
*
************************************************
A L2HIST JSR
A
LDAA
A
STAA
A
LDAA
A
STAA
A
LDAA
A
STAA
L2HBSY
t\$04
PIDTR
t\$05
P1DTR
INSTR
P3DTR
Check LCTC busy fLag
Set RS=l.R/W=O.E=O
Set E=l
Output instruction through port3
~HITACHI
880
00229A
00230A
0023lA
00232A
00233A
00234A
0023SA
00236A
00237A
00238
00239
00240
00241
00242
00243A
00244A
0024SA
00246A
00247A
00248A
00249A
00250A
002S1A
002S2A
002S3A
00254
00255
00256
00257
00258
002S9A
00260A
00261A
00262A
00263A
00264A
0026SA
00266A
00267A
00268A
00269A
00270A
00271A
00272A
00273A
00274A
0027SA
00276A
00277A
00278A
00279A
00280A
0028lA
00282A
00283A
00284A
0028SA
Cll2
Cll4
Cll6
C1l9
Cll8
CllD
C11F
C121
C124
86
97
7F
86
97
96
97
7F
39
04
02
0002
01
02
41
06
0002
C12S
C127
C129
C12B
C12D
C130
C132
C134
C136
C138
C13B
86
97
96
97
BD
86
97
96
97
BD
39
OA
40
42
41
C103
OB
40
43
41
C103
C13C
C13E
C140
C142
C144
C146
C148
C14A
C14C
C14E
C14F
C1S0
C1Sl
ClS2
C1S3
ClS4
ClSS
C156
C1S7
ClS8
C1S9
C15A
ClSB
C1SC
ClSD
C15E
C1SF
00
01
02
03
04
08
09
OA
OB
01
01
01
03
03
03
03
02
02
02
04
04
04
04
03
03
01
01
A
A
A
A
A
A
A
A
LDAA
11$04
Set E=O
STAA
PlDTR
CLR
PlDTR
Set RS=O
11$01
LDAA
Set E=l
STAA
P1DTR
LDAA
Output data through port3
DATAR
STAA
P3DTR
CLR
P1DTR
Set E=O
RTS
************************************************
*
*
NAME : L2HCST (STORE CURSOR ADDRESS)
*
*
*
*
************************************************
Store instruction
A L2HCST LDAA
Il$OA
A
STAA
INSTR
A
Store data
LDAA
CURL
A
STAA
DATAR
A
JSR
L2HIST
Write lower cursor ADDR to LCTC
A
Il$OB
Store instruction
LDAA
A
STAA
INSTR
A
Store datil
LDAA
CURH
A
STAA
DATAR
A
Write upper cursor ADDR to LCTC
JSR
L2HIST
RTS
************************************************
*
*
DATA TABLE
*
*
*
*
************************************************
$0,$32
A LCTC1 FCB
*Instruction and data$1,$07
A
FCB
to initialize LCTC
$2,$lD
A
FCB
$3,$lF
A
FCB
$4,$00
A
FCB
$8,$00
A
FCB
$9,$00
A
FCB
$A,$OO
A
FCB
$B,$OO
A
FCB
A DTDATA FCB
$01
*Display data
A
$01
FCB
A
$01
FCB
$03
A
FCB
A
$03
FCB
A
$03
FCB
$03
A
FCB
A
FCB
$02
$02
A
FCB
A
FCB
$02
$04
A
FCB
A
$04
FCB
$04
A
FCB
A
$04
FCB
A
$03
FCB
$03
A
FCB
A
$01
FCB
$01
A
FCB
I
~HITACHI
881
00286A
00287A
00288A
00289A
00290A
00291A
00292A
00293A
00294A
00295A
00296A
00297A
0029BA
00299A
00300A
00301A
00302A
00303A
00304A
00305A
00306A
00307A
0030BA
00309A
00310A
00311
00312
00313
00314
00315
00316
00317A
0031B
00319A
00320A
00321A
00322A
00323A
00324A
00325A
00326A
00327A
00328A
00329A
00330
00331
C160
C161
C162
C163
C164
C165
C166
C167
C168
C169
C16A
C16B
C16C
C16D
C16E
C16F
C170
C171
C172
C173
C174
C175
C176
C177
C178
01
01
00
01
00
04
01
01
04
03
01
01
02
03
03
03
01
02
02
02
02
01
04
04
FF
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
$01
$01
$00
$01
$00
$04
$01
$01
$04
$03
$01
$01
$02
$03
$03
$03
$01
$02
$02
$02
$02
$01
$04
$04
$FF
************************************************
*
*
VECTOR ADDRESSES
*
*
*
*
************************************************
*
FFEA
FFEA
FFEC
FFEE
FFFO
FFF2
FFF4
FFF6
FFFB
FFFA
FFFC
FFFE
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
COOO
COOO
COO a
COOO
COOO
COOO
COOO
COOO
COOO
COOO
COOO
A
A
A
A
A
A
A
A
A
A
A
*
*
ORG
$FFEA
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
L2HMN
L2HMN
L2HMN
L2HMN
L2HMN
L2HMN
L2HMN
L2HMN
L2HMN
L2HMN
L2HMN
IRQ2
CMI
TRAP
SID
Tor
OCI
ICI
IRQlIISF
SWI
NMI
RES
END
~HITACHI
SECTION 2.
2.1
DARLINGTON TRANSISTOR DRIVE (LED DYNAMIC DISPLAY)
HARDWARE DESCRIPTION
2.1.1
Function
Drives LEDs by amplifying signals from the HD6301YO, displaying
"76543210" on the LED display.
2.1.2
Microcomputer Operation
The HD6301YO executes output compare interrupt 1 every 1.25 ms using
timer 1 to drive LEDs by outputting segment data through port 1 and
digit data through port 6.
Darlington transistor are driven directly
through port 6.
2.1.3
Peripheral Devices
LEDs:
Driven dynamically at a frame frequency of 100 Hz and duty rate
of l/S.
2.1.4
Circuit Diagram
S-digit x S-segment LED control circuit is shown in figure 2-1.
Meu
HD 6 3 0 1 Yo
+5V
4
5
8
50
MP.
MPI
NMI
PII
49
P12
48
STBY
Pu
47
Vee
XTAL
PI.
46
,
33
f~
4MHzC1
3
22pF
LED
PIO
Pu
EXTAL
+5V
Vss
Vss
n
I I
RD
DlG8 DlG7 DiG6 DIG5 DlG4 DIG3 DlG2 DIGl
45
®
Pu
44
PI1
43
POT
P••
(8-digit x 8-segment)
I
32
31
p ••
Po.
P••
29
28
p ••
27
P.I
26
o
lq~
®W
p •• 25
Figure 2-1.
B.-digit x B-segment LED Control Circuit
~HITACHI
883
2.1.5
Pin Functions
Pin functions at the interface between the HD6301YO and LED are shown
in table 2-1.
Table 2-1-
2.1.6
Pin Functions
Pin Name
(HD6301YO)
Input/
Output
Active
Level
(High or
low)
P!H
P S1
Output
High
Output
High
P S2
Output
High
DIG 3
P S3
Output
High
DIG4
Function
Outputs digit data
to LED.
Pin Name
(LED)
Program
Label
DIGl
P6DTR
DIG2
P S4
Output
High
DIGS
Pss
Output
High
DIG6
P ss
Output
High
DIG7
P S7
Output
High
PlO
P ll
Output
Low
Output
low
P 12
Output
Low
PH
P 14
Output
Low
Output
low
P 1S
Output
Low
P 1S
Output
Low
P 17
Output
Low
DIGS
Outputs segment data
to LED. l1a-vh" in
Pin Name (LED)
corresponds .co
segment pattern
a
below.
e, 'c
f'- 'b
-
Segment Pattern
P1DTR
b
c
d
e
g
d
a
f
~h
g
h
Hardware Operation
The timing chart for segment signals and digit signals is shown in
figure 2-2.
~HITACHI
884
100 digit ON
P. o
P. 1 --t---;
Segment
Signals
P••
-+----r---~--~----+_--~--~
digit ON
P.7-1----+----r--~r_--;_--_+----~--~
Digit {p
'VP
Signals 10
17
17 p. s
P••
10ms(lOOHz)
P87--~--------~
10 6 digit
X
10 7 digit
/
Figure 2-2.
2.2
Timing Chart of Segment Signals
and Digit Signals
SOFTWARE DESCRIPTION
2.2.1
Program Module Configuration
The program module configuration for displaying digits on LED is shown
in figure 2-3.
I
LEDMN
l'!.
MAIN
PROGRAM
L EDSP
I
I
MOVE
L..!.
DRIVE LED
Figure 2-3.
I
STORE
DISPLAY
DATA
l.!
Program Module Configuration
~HITACHI
885
2.2.2
Program Module Functions
Program module functions are summarized in table 2-2.
Table 2-2.
2.2.3
Program Module Functions
No.
Program Module Name
Label
Function
o
MAIN PROGRAM
LEDMN
Demonstrates display data on LED.
1
DRIVE LED
LEDSP
Displays digits on LED using
dynamic drive.
2
STORE DISPLAY DATA
MOVE
Stores display data in display RAM.
Refer to MOVE in HD6301/HD6303
FAMILY APPLICATION NOTES (SOFTWARE)
for details.
Program Module Process Flow (Main Program)
The flowchart in figure 2-4 is an example of the a-digits x a-segment
LED display performed by the program module in figure 2-3.
The main
program in figure 2-4 demonstrates the display on LED shown in figure
2-5.
~HITACHI
886
Main Program
--1[Initialize stack pointer.
--1[Initialize digit data output from port 6.
$ 0 l--+DECD
--~'nitiali"O
O--+DSCNTR
data table pointer.
---{:Select port 1 and port 6 ao output.
___ [Initialize timer control/status register 1
for enabling output compare interrupt 1.
o
---I
--+ Bit I
Enable interrupts.
$FIOO--+IX
Execute MOVE to move segment data, in data
table, to display RAM. Refer to MOVE in
HD6301/HD6303 APPLICATION NOTES (SOFTWARE)
for details.
SEGD--+DEA
8--+ACC13
OCIl Interrupt Routine
---{ Display digits on LED using dynamic drive.
Figure 2-4.
Program Module Flowchart
LED (8-digit x 8-segment)
Figure 2-5.
Example of 8-digit x 8-segment LED Display
~HITACHI
887
2. 3
PROGRAM MODULE DESCRIPTION
Program Module Name: DRIVE LED
Label:LEDSP
MCU/MPU: HD6301YO
Function:
Displays digits on a-digit x 8-segment LED using dynamic drive.
Arguments:
contents
Entry
Display
data
Changes in CPU
Storage
Location
No. of
Bytes
SEGD
(RAM)
8
Specifications:
Registers and Flags:
ACCD
ACCA ACCB
x
x
ROM (Bytes) : 48
RAM (Bytes) : 11
Stack (Bytes) : 0
IX
No. of cycles: 69
x
Reentrant: No
Returns
•
x
:
C
V
x
x
Z
N
x
x
I
H
•
•
Relocatable: No
Interrupt OK?: No
Not affected
Undefined
Result
Description:
1.
Function Details
a.
Argument details
SEGD(RAM) : Holds display data.
b.
Example of LEDSP execution is shown in figure 2-6.
If entry arguments
are as shown in part 1 of figure 2-6, data is displayed on LED as shown
in part 2 of figure 2-6. Table 2-3 shows relation between segment data
and display.
c.
LEDSP calls no subroutines.
Specifications Notes:
"No. of cycles" in "Specifications" indicates the number of cycles required to
display the 10 0 digit (rightmost) on LED.
~HITACHI
888
Program Module Name: DRIVE LED
MCU/MPU: HD6301YO
ILabe"
LEDSP
~--------------~
Description:
Address Space
~
SEGD(RAM)r-__$_D_8__~
(segment)
$ 82
data
r---'-$-9-2--~
Q)
Entry
argument
$ 99
$BO
$A4
$F9
$CO
Figure 2-6.
Table 2-3.
Relation between Segment Data and Display
Segment Data
Display
n
Segment Data
$CO
U
$92
$F9
I
I
$82
2
3
$A4
$BO
Y
$99
2.
Example of LEDSP Execution
$D8
$80
$90
Display
5
5
..,
I
8
g
I
User Notes
The following procedure must be performed before LEDSP execution.
a.
Initialize digit data.
b.
Initialize display RAM pointer.
c.
Select port 1 and port 6 as output.
~HITACHI
889
~p_r_o_g_r_am
___M_o_d_u_l_e__N_a_m_e_:__D_R_I_VE
___L_E_D______
~ ~M_C_U_/_M_P_U
__: __HD
__6_3_0_1_Y_0____
~ I~L_a_b_e_l
__
: __
LE_D
__
S_P______
Description:
3.
d.
Initialize timer control/status register 1 so that output compare
interrupt 1 can be enabled.
e.
Enable interrupts.
f.
Store entry arguments.
RAM Allocation
RAM
Label
Description
bO
b7
SEGD
I-I-I-I-I-I-l--
Digit
Digit
Digit
Digit
Digit
Digit
Digit
Digit
10 7 - 10 6 10 5
10 4 10 3 10 2 lOl10 0 -
-
DSCNTR I-DECD
4.
B-digit segment data
}
}
Used as a pointer indicating display RAM
Digit data
Sample Application
I
I
I
LDAA
STAA
CLR
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
CLI
LDX
LDAA
STAA
LDAB
JSR
#$01
DECD
DSCNTR
#$07
DSCNTR+l
#$01
P1DDR
#$FF
P6DDR
#$OB
TCSRl
#$F100
#SEGD
DEA
#B
MOVE
} .....
Initialize digit data
} .....
Initialize display RAM pointer
..... Select port 1 and port 3 as output.
J
}
}
..... Enable output compare interrupt.
.....
Enable interrupts.
.....
Load entry arguments.
I
I
I
ORG
FCB
$F100
$DB, $82, $92, $99, $BO, $A4, $F9, $CO ...•• Display data
I
I
~HITACHI
890
~
Program Module Name: DRIVE LED
LM_C_U_/_M_P_U_:__HD
__6_3_0_1_Y_O____
~
LIL_a_b_e_l_:__LE
__D_S_P______
~
Description:
5.
Basic Operation
a.
Each digit is dynamically displayed one by one from the 10 0 digit every
interrupt.
b.
In the interrupt routine, the procedure below is performed.
i.
ii.
iii.
A specific digit signal is set to Low to turn off its display.
Segment data for next digit is read from display RAM and output
to ports.
Digit signal is set to High to turn on display.
c.
DSCNR(RAM) is used as a pointer to display RAM, and incremented every
interrupt. After 10 7 digit displayed, DSCNR(RAM) is cleared.
d.
DECO (RAM) contains digit data, and is shifted 1 bit left to indicate next
display digit.
I
~HITACHI
891
Program Module Name: DRIVE LED
MCU/MPU: HD630lYO
I
Label, LEDSP
Flowchart:
Enable output compare interrupt l.
___ { Initialize output compare register 1
to execute interrupt every 1.25 ms
hereafter.
___{set digit signal to Low to turn off
display.
----[Load pointer to display RAM.
---{ Output segment data to port l.
---{output digit data to port 6.
---{ Decrement pointer to display RAM.
(7. DECD)=l
---{ Test if 8 digits have been displayed,
digit data for next interrupt.
---{Initialize digit data.
---{Initialize pointer to display RAM.
LEDSP2
~HITACHI
892
2.4
SUBROUTINE DESCRIPTION
This application example calls no subroutines.
2.5
PROGRAM LISTING
00001
00002
00003
00004A
00005
00006A
00007A
00008A
00009A
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026A
00027
00028A
00029A
00030A
00031A
00032A
00033A
00034A
00035A
00036A
00037A
00038A
00039A
00040A
00041A
00042A
00043A
00044A
00045A
00046A
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057
*****
0040
0040
0048
004A
004B
0008
0002
0001
0002
RAM ALLOCATION
*
A*
SEGD
ORG
RMB
A DSCNTR RMB
RMB
A DECD
A DEA
RMB
*************************
$40
8
2
1
2
8-digit segment data
DispLay RAM pointer
Digit data
Destination address
*
SYMBOL DEFINITIONS
********************
*
Port 1 data direction register
$00
0000 A PlDDR EQU
****
0002
0008
0009
obOB
0016
0017
A
A
A
A
A
A
Port 1 data register
$02
PIOTR EQU
Timer controL/status register 1
$08
TCSR1 EQU
Free running counter
EQU
$09
FRC
Output compare register 1
EQU
$OB
OCR1
Port 6 data direction register
$16
P6DDR EQU
Port 6 data register
$17
P6DTR EQU
************************************************
*
*
MAIN PROGRAM : LEDMN
*
*
*
*
************************************************
*
COOO
COOO 8E
C003 86
COOS 97
C007 7F
COO A 86
COOC 97
COOE 86
COlO 97
C012 86
C014 97
C016 86
C018 97
COlA OE
C01B CE
COlE CC
C021 DO
C023 C6
C025 80
C027 20
013F
01
4A
004B
07
49
01
00
FF
16
08
08
ORG
$COOO
A *LEDMN
A
A
A
A
A
A
A
A
A
A
A
FIOO A
0040 A
4B
A
08
A
02 C029
FE C027
InitiaLize stack pointer
LOS
1l$l3F
1l$01
InitiaLize digit data
LDAA
STAA
DECO
InitiaLize dispLay RAM pointer
DSCNTR
CLR
LDAA
117
STAA
DSCNTR+l
1l$01
SeLect port 1 and port 6 as out~ut
LDAA
STAA
PlDDR
Il$FF
LDAA
P6DDR
STAA
EnabLe OCI interrupt
1l$08
LDAA
TCSRI
STAA
EnabLe interrupts
CLI
Load source address
LOX
Il$FIOO
Load destination address
LDD
IlSEGD
STD
DEA
LDAB
118
Load no. of bytes to be moved
BSR
MOVE
Move segment data to dispLay RAM
PEND
BRA
PEND
End of program
************************************************
*
*
NAME : MOVE (MOVE MEMORY BLOCII<
FFEA
FFEC
FFEE
FFFO
FFF2
FFF4
FFF6
FFF8
FFFA
FFFC
FFFE
COOO
COOO
COOO
COOO
COOO
C039
COOO
COOO
COOO
COOO
COOO
A
A
A
A
A
A
A
A
A
A
A
IR02
CMI
TRAP
SID
TOI
OCI
ICI
IROllISF
SWI
NMI
RES
>I<
END
~HITACHI
895
SECTION 3.
3.1
DUTY CONTROL OF PULSE OUTPUT AND DA CONVERSION
HARDWARE DESCRIPTION
3. 1. 1
Function
Outputs pulse with 0-100% duty rate and performs digital-to-analog
conversion of output pulse with an external integration circuit.
3.1.2
Microcomputer Operation
The HD6301YO increases duty rate by 4% every 0.3s.
This increase in
duty rate changes the output voltage from 0 to 5 V in 0.2 V increments.
High or Low is output from the Tout3 pin by executing the counter
match interrupt routine with timer 2.
In addition, the High and Low
Period of the pulse is controlled by changing values in the time
constant register.
3.1.3
Peripheral Devices
Integration circuit:
Performs level conversion of the output pulse
through the HD14050B, and converts the result from digital to
analog.
The operational amplifier here prevents the fluctuation
of analog output voltage caused by the load in the user system.
3.1.4
Circuit Diagram
Pulse output circu.it is shown in figure 3-1.
Meu
HD6301Yo
(HD6S0SY)
+5V
4
8
MPo
MPI
NMI
STBY
33
f:" :
Vee
+l2V
XTAL
22pF
EXTAL
+5V
P 2s /Tout
15
IS2076
-12V
Vss
'--+--='-1 V ss
Figure 3-1.
Pulse Output Circuit
~HITACHI
896
3.1.5
Pin Function
Pin function for output pulse is shown in Table 3-1.
Table 3-1.
Pin Function
Pin Name
(HD6301YO)
Input/
Output
Active Level
(High or Low)
Output
3.1.6
Program
Label
Function
Outputs pulse
Hardware Operation
Pulse output and DA conversion is shown in figure 3-2.
100
60
40
Tout3
n IL
I--
(Duty 40%)1 2. 8 rns
Output after
DA conversion
5.0V
1 2. 8 rns
-----------------------------------------~
I
r---'
I
4.6 V
------------------------------~
I
m1---~//
o 2V
OV
Figure 3-2.
---
I
I
)
n
I
I
I
I
I
I
I
I
I
I
I
r-
I
I
I
I
I
I
r---'
I
I
t
Pulse Output and Output State after DA Conversion
~HITACHI
897
3.2
SOFTWARE DESCRIPTION
3.2.1
Program Module Configuration
The program module configuration for pulse output .is shown in figure 3-3.
DUMN
.~
MAIN
PROGRAM
DUSET
I
I
DUOUT
I
~
l.:.
OUTPUT PULSE
SET DUTY
Figure 3-3.
3.2.2
Program Module Configuration
Program Module Functions
Program module functions are summarized in table 3-2.
Table 3-2.
3.2.3
Program Module Functions
No.
Program Module Name
Label
Function
a
MAIN PROGRAM
DUMN
1
SET DUTY
DUSET
Sets duty rate of pulse.
2
OUTPUT PULSE
DUOUT
Outputs pulse.
. Outputs pulse.
Program Module Process Flow (Main Program)
The flowchart in figure 3-4 is an example of controlling pulse output
and digital-to-analog conversion, using the program module in figure
3-3.
898
~HITACHI
Main Program
---~Initialize stack pointer.
---~Initialize
RAM for work area.
Initialize timer control register 3 to enable
___ { counter match interrupt, enable clock input to
timer 2 up counter, and select E clock/128.
---~Enable
interrupt.
---{Load entry argument of DUSET.
---{Execute DUSET to set duty rate of pulse.
Increment duty rate for next pulse output.
Execute 0.3s software timer.
I
eMI Interrupt Routine.
---~Execute
Figure 3-4.
DUOUT to output pulse.
Program Module Flowchart
~HITACHI
899
3.3
PROGRAM MODULE DESCRIPTION
Program Module Name: SET DUTY
MCU/MPU:
HD630lYO/
Label: DUSET
HD6303Y
Function:
Defines pulse status, which is output in DUOUT, based on duty rate.
Arguments:
Changes in CPU
Contents
Entry
Duty
rate
Storage
Location
No. of
Bytes
VCOUNT
(RAM)
1
Specifications:
Registers and Flags:
ACCD
ACCA ACCB
x
x
ROM (Bytes): 55
RAM (Bytes): 4
Stack (Bytes): 0
IX
No. of cycles: 49
x
Reentrant: No
Returns
High
period of
pulse
HTIME
(RAM)
1
Low period LTIME
(RAM)
of pulse
1
Pulse
status
flag
1
HIDUT
(RAM)
•
x
:
C
V
x
x
Z
N
x
x
I
H
•
x
Relocatable: No
Interrupt OK?: Yes
Not affected
Undefined
Result
Description:
1.
Function Details
a.
Argument details
VCOUNT (RAM) : Duty rate as a hexadecimal number.
(Duty rate=1/4 actual duty rate. See "2. User Notes".)
HTIME(RAM)
High period of pulse.
LTIME(RAM)
Low period of pulse.
Flag indicating which output is performed: Low consecutive
HIDUT(RAM)
output, High consecutive output, or pulse output.
Table 3-3 shows flag functions.
Specifications Notes:
"No. of cycles" in "Specifications" represents the number of cycles required when
duty rate is other than 0% or 100%.
~HITACHI
900
o~d_U_le
_p_r_o_g_r_am
__M
__
L.
__N_a_rn_e_:___
SE_T
__D_UT
__Y
______
~
LM_C_U_I_M_P_U_:__HD
__6_3_0_l_Y_0_1____-J lL_a_h_e_l_:__D_U_S_E_T______-J
HD6303Y
.
Description:
Table 3-3.
Flag Functions
Label
bit 1
bit 0
Function
HLOUT
0
0
Outputs Low consecutively from Tout3 pin.
1
0
Outputs Pulse from Tout3 pin.
1
1
Outputs High consecutively from Tout3 pin.
b.
c.
VCOUNT
b7
bO
Entry
{VCOUNT(RAM) 0
argument
($ OA).
A
Example of DUSET execution is
shown in figure 3-5. If entry
argument is as shown in part Q)
of figure 3-5, High and Low
period of duty 40% pulse are
stored as shown in part @ of
figure 3-5.
I
b7
HTI~E$(:f)')1
DUSET calls neither the program
modules nor subroutines.
Return
arguments
2.
User Notes
I
HLOUT(RAM) I
($02).
The following procedure must be
executed before DUSET execution.
Figure 3-5.
3.
LTI~E$(:~~O
HTIME
bO
2
: 7
LTIME
3 : B
HLOUT
0 :
.
I
I
2
Example of DUSET
Execution
a.
Re serve the High and Low
period of pulse in a data table.
b.
Load entry argument.
c.
When specifying duty rate, load the actual duty rate divided by 4, since
duty rate is defined every 4%.
d.
Data in VCOUNT(RAM) must be within the range $0~VCOUNT~$16, otherwise
neither the High nor Low period of pulse can be obtained.
I
RAM Allocation
b7
HTIME
Description
RAM
Label
bO
}
High period of pulse
}
}
Low period of pulse
HLOUT
VCOUNT
}
Duty rate
LTIME
Pulse status flag
~HITACHI
901
Program Module Name:
MCU/MPU: HD6301YOI
SET DUTY
HD6303Y
ILab.,'
DUSET
Description:
4.
Sample Application
I
I
I
I
LDAA
STAA
II JSR
5.
#$10 }
VCOUNT
Load entry argument.
DUSET
Call DUSET.
Basic Operation
a.
b.
DUSET executi'on stores High and Low period of pulse in HTIME
LTIME (RAM)
from a data table based on duty rate
Data in data table contains actual High and Low periods less 1 as shown
in Formula l.
Cycle of pulse= I (High period of pulse +1) + (Low period of pulse +1)\
x 128~s = 12.8 ms • • • • • • •• (Formula 1)
i.
ii.
VCOUNT(RAM) is used as a pointer to data table.
Duty rate is checked and:
If duty rate is 0% or 100%, define pulse status flag to output Low
or High consecutively. Next, hold High and Low period of pulse so
that counter match interrupt is executed at a duty rate of 50%.
If duty rate is 4 ~ 96%, load High and Low period of pulse using
index addressing mode, and then define flag to output pulse.
~HITACHI
902
MCU/MPU: HD6301YO!
Program Module Name: SET Dory
HD6303Y
I~
DUSET
Flowchart:
--{ "'"t if duty rate i" " .
__ { Define flag to output Low
consecutively from TOut 3 pin.
--{ Test if duty rate is 100%.
__ { Define flag to output High
consecutively from Tout 3 pin.
Define High and Low period of pulse to
--{ execute interrupt at a duty rate of 50%.
--{ Load duty rate.
__I
Load pointer in data table for High
period into IX.
I
__ { store High period of pulse.
__{ Load pointer in data table for Low
period,into IX;
--{ Store Low period of pulse.
0->0, HLOUT
l->l,HLOUT
__ { Define flag to output pulse from
Tout 3 pin.
~HITACHI
903
Program Module Name: OUTPUT PULSE
MCU/MPU: HD630lYO/
HD6303Y
Label: DUOUT
Function:
Output pulse from Tout3 pin.
Arguments:
Changes in CPU
Registers and Flags:
Contents
Storage
Location
No. of
Bytes
Entry High
period of
pulse
HTIME
(RAM)
1
Low period LTIME
(RAM)
of pulse
1
•
Pulse
status
flag
1
C
V
•
x
Returns
_."---
ACCD
ACCA ACCB
ROM (Bytes): 35
I
RAM (Bytes): 3
x
•
Stack (Bytes): 0
IX
HLOUT
(RAM)
--
Specifications:
No. of cycles: 41
Reentrant: No
-
•
x
t
:
Z
N
x
x
I
H
•
•
Relocatable: No
Interrupt OK?: No
Not affected
Undefined
Result
Description:
1.
Function Details
a.
Argument details
HTIME(RAM): High period of pulse.
LTIME(RAM): Low period of pulse.
HLOUT(RAM): Flag indicating which output is performed:
Low consecutive output, High consecutive output, or pulse
output.
Table 374 shows flag functions.
Specifications Notes:
~HITACHI
904
Program Module Name: OUTPUT PULSE
MCU/MPU:
lID6301YO/
lID6303Y
IL.b'"
DUOUT
Description:
Table 3-4.
Label
bit 1
bit 0
Function
HLOUT
0
0
Output Low consecutively from Tout3 pin.
1
0
Output Pulse from Tout3 pin.
1
1
Output High consecutively from Tout3 pin.
b.
c.
2.
Example of DUOUT execution is
shown in figure 3-6. If
entry arguments are as shown
in part CD of figure 3-6 I duty
rate 40% pulse is output as
shown in part @ of figure 3-6.
b7
HT1ME
bO
HT 1ME ( RAM) -...:2=---L-_~...J1
($27)
b7
LT1ME
bO
LI
CD
Entry
argument
8:
LT1ME(RAM)1
($86)
b7
HLOUT
I
bO
HLOUT(RAM)I-i-I-I-I-i-11Iol
DUOUT calls neither the program
modules nor subroutines.
User Notes
a.
3.
Flag Functions
40.1 .. 60. 1
1..
Initialize timer control
register to enable counter match
interrupt, enable clock input to
timer 2 up counter, select E
clock 1/128.
b.
Enable interrupts.
c.
Store entry arguments.
@
Result { Tout 3 ~
Duty 40%
Figure 3-6.
Example of DUOUT
Execution
RAM Allocation
Label
b7
HTIME
LTIME
HLOUT
Description
RAM
bO
§~
High period of pulse
Low period of pulse
Pulse status flag
~HITACHI
905
Program Module Name:
OUTPUT PULSE
MCU/MPU:HD6301YO/
HD6303Y
\Lab
O
DUOUT
"
Description:
4.
Sample Application
WORKl
RMB
.....
1
I
Reserve memory for duty rate.
I
I
LDAA
STAA
#$5A
TCSR3
}
Initialize timer control register.
Enable interrupt.
CLI
LDAA
STAA
JSR
5.
IDRKl }
VCOUNT
DUSET
.....
Load entry argument of DUSET.
Basic Operation
a.
Data in HTIME(RAM), LTIME(RAM) is loaded in time constant register, and
pulse output'.
b.
i.
ii.
Output status is checked and converted (High + Low or Low + High) at
every timer interrupt. At this time, High and Low period of pulse
is loaded into time constant register.
If duty rate is 0% or 100%, define time constant register at a duty
rate of 50%, and maintain output status (High + High or Low + Low) .
~HITACHI
906
Program Module Name: OUTPUT PULSE
MCU/MPU:
HD6301YO/
HD6303Y
ILab.',
DUOUT
Flowchart:
__ { Clear counter match interrupt
request flag.
__ { Test if previous output is High
or Low.
DUOTI
(2, TCSR3);6o
__ {
Load Low period of pulse into time
constant register.
- - { Test if duty rate is 0%.
__ {
If duty rate is not 0%, output
High from Tout 3 pin.
__ { Load High period of pulse into time
constant register.
- - { Test if duty rate is 100%.
__ { I f duty rate is not 100%, output
Low from Tout 3 pin.
I
~HITACHI
907
3.4
SUBROUTINE DESCRIPTION
This application example calls no subroutines.
3.5
PROGRAM LISTING
00001
00002
00003
00004A
00005
00006A
00007A
OOOOBA
00009A
00010A
00011A
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023~)
00024
00025A
00026A
00027A
00028A
00029A
00030A
00031A
00032A
00033A
00034A
00035A
00036A
00037A
00038A
00039A
00040A
00041A
00042A
00043A
00044A
00045A
00046A
00047A
00048A
00049
00050
00051
00052
00053
00054
00055
00056
00057
*
****
*
0040
0040
0041
0042
0043
0044
0045
0001
0001
0001
0001
0001
0001
001B
001C
A
A
A
A
A
A
*************************
$40
ORG
Duty data
Duty rate
High period of puLse
Low period of puLse
PuLse status fLag
Work area for entry argument
DATA
VCOUNT
HTIME
LTIME
HLOUT
WORK
RMB
RMB
RMB
RMB
RMB
RMB
*
****
*
SYMBOL DEFINITIONS **********************
Timer controL/status register3
$lB
A TCSR3 EOU
$lC
Time constant register
A TCONR EQU
*********************************)k**************
*
*
MAIN PROGRAM : DUMN
*
*
*
*
************************************************
*
COOO
COOO
C003
C004
C006
C008
COOA
COOB
COOD
COOF
COlI
C013
C014
C016
C018
COlA
C018
COlD
C01F
C022
C024
C025
C027
C028
C02A
*
RAM ALLOCATION
8E
4F
97
86
97
OE
96
97
8D
96
4C
97
81
26
4F
97
97
CE
86
4A
26
09
26
20
*
013F
A DUMN
45
SA
1B
A
A
A
45
A DUMN1
41
A
3E C04F
41
A
41
A
1A
A
03 COlD
41
45
OOFF
FF
A
A DUMN2
A
A DUMN3
DUMN4
FD C024
F8 C022
DF COOB
ORG
$COOO
LOS
CLRA
STAA
LDAA
STAA
CLI
LDAA
STAA
BSR
LDAA
INCA
STAA
CMPA
BNE
CLRA
STAA
STAA
LDX
LDAA
DEC A
BNE
DEX
BNE
BRA
1:I$13F
InitiaLize stack pointer
CLear RAM for work area
WORK
1:I$5A
TCSR3
InitiaLize TCSR3
WORK
VCOUNT
DUSET
VCOUNT
EnabLe Interrupt
Load entry argument of DUSET
Execute DUSET
Increment duty for next puLse
DUTY+4%-)entry argument
VCOUNT
1:126
DUMN2
DUTY=104% ?
VCOUNT
WORK
I:I$FF
I:I$FF
Store 0% duty
Store duty in entry argument
Execute 0.3s software timer
DUMN4
DUMN3
DUMN1
**************~(*********************************
*
*
*
NAME
:
DUOUT (OUTPUT PULSE)
************************~(***********************
*
*
*
*
ENTRY : HTIME (HIGH PERIOD OF PULSE)
LTIME (LOW PERIOD OF PULSE)
HLOUT (PULSE STATUS FLAG)
~HITACHI
908
*
*
*
*
*
*
*
00058
00059
00060
00061A C02C
00062A C02F
00063A C032
00064A C034
00065A C036
00066A C038
00067A C03B
00068A C03D
00069A C040
00070A C042
00071A C044
00072A C046
00073A C049
00D74A C04B
00075A C04E
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088A C04F
00089A C051
00090A C053
00091A C056
00092A C059
00093A COSB
00094A COSO
0009SA COSF
00096A C062
00097A C065
00098A C067
00099A C069
00100A C06B
00101A C060
00102A C06F
00103A C072
00104A C073
00105A C07S
00106A C077
00107A C07A
00108A C07B
00109A C07D
OOllOA C07F
00111A·C082
00112A C085
00113
00114
>I<
RETURNS : NOTHING
>I<
>I<
>I<
71
7B
27
96
97
7B
26
71
20
96
97
7B
27
72
3B
7F
04
OE
42
1C
01
11
FB
OC
43
1C
02
03
04
*********************************~:'k**~C****~:*****
1B
DUOUT
1B
C042
A
A
44
C04E
1B
C04E
A DUOT1
A
44
C04E
1B
DUOT2
BCLR
BTST
BEQ
LDAA
STAA
BTST
BNE
BCLR
BRA
LDAA
STAA
BTST
BEQ
BSET
RTI
CLear 1nterrupt request fLag
Output Is HIgh or Low?
Branch 1f Low output
Store H1gh perIod In TCONR
7.TCSR3
2.TCSR3
DUOT1
HTIME
TCONR
O.HLOUT
DUOT2
2.TCSR3
DUOT2
LTIME
TCONR
1. HLOUT
DUOT2
2.TCSR3
DUTY=100% ?
Output Low
Store Low per10d In TCONR
DUTY=O% ?
Output High
>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<
>I<
>I<
>I<
NAME
:
DUSET (SET DUTY)
>I<
>I<
>I<
>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<
>I<
>I<
>I<
>I<
>I<
>I<
ENTRY
RETURNS
:
VCOUNT
HTIME
LTIME
HLOUT
(DUTY RATE)
(HIGH PERIOD OF PULSE)
(LOW PERIOD OF PULSE)
(PULSE STATUS FLAG)
>I<
>I<
>I<
>I<
96 41
A
26 08 C05B
71 FE 44
71 FD 44
20 OA C065
81 19
A
26 OE C06D
72 01 44
72 02 44
86 31
A
97 42
A
97 43
A
20 18 COBS
06 41
A
CE C085 A
3A
A6 00
A
A
97 42
CE C090 A
3A
A6 00
A
A
97 43
71 FE 44
72 02 44
39
>I<
>I<
************************************************
VCOUNT
DUSET LDAA
DUSETl
Test if duty=O%
BNE
O.HLOUT Define fLag to output Low
BCLR
1. HLOUT
BCLR
BRA
DUSET2
Test if duty=100%?
1l2S
DUSETl CMPA
BNE
DUSET3
O.HLOUT DefIne fLag to output Hlgil
BSET
1.HLOUT
BSET
Set 50% duty rate
1149
DUSET2 LDAA
HTIME
STAA
LTIME
STAA
DUSET4
BRA
VCOUNT
DUSET3 LOAB
IlHTDATA-1 Load duty rate
LOX
ABX
Load HIgh period poInter into IX
LDAA
O.X
S t 0 t'e HIgh perIod of puLse
STAA
HTIME
tiLTOATA-1 Load Low perIod pointer Into IX
LOX
ABX
LOAA
O.X
Store Low perIod of puLse
STAA
LTIME
O.HLOUT DefIne fLag to output puLse
BCLR
1.HLOUT
BSET
DUSET4 RTS
I
>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<
>I<
>I<
~HDTACHI
909
00115
00116
00117
0011BA
00119A
00120A
00121A
00122A
00123A
00124A
00125A
00126A
00127A
00128A
00129A
00130A
00131A
00132A
00133A
00134A
00135A
00136A
00137A
00138A
00139A
00140A
00141A
00142A
00143A
00144A
00145A
00146A
00147A
00148A
00149A
00150A
00151A
00152A
00153A
00154A
00155A
00156A
00157A
00158A
00159A
00160A
00161A
00162A
00163A
00164A
00165A
00166
00167
00168
00169
00170
00171
C086
C087
C088
C089
C08A
C08B
C08C
C08D
C08E
C08F
C090
C091
C092
C093
C094
C095
C096
C097
C098
C099
C09A
C09B
C09C
C09D
C09E
C09F
COAO
COAl
COA2
COA3
COM
COA5
COA6
COA7
COA8
COA9
COAA
COAB
COAC
COAD
COAE
COAF
COBO
COB1
COB2
COB3
COB4
COBS
03
07
OB
OF
13
17
1B
IF
23
27
2B
2F
33
37
3B
3F
43
47
4B
4F
53
57
5B
SF
SF
5B
57
53
4F
4B
47
43
3F
3B
37
33
2F
2B
27
23
IF
IB
17
13
OF
OB
07
03
DATA TABLE
*
*
*
*************************************************
*High period of puLse
3
A HTDATA FCB
A
FCB
7
FCB
A
11
A
FCB
15
A
FCB
19
A
FCB
23
A
FCB
27
A
FCB
31
FCB
35
A
39
A
FCB
43
A
FCB
A
FCB
47
FCB
51
A
A
FCB
55
A
FCB
59
FCB
63
A
FCB
67
A
FCB
71
A
75
A
FCB
FCB
79
A
A
FCB
83
A
FCB
87
91
A
FCB
FCB
95
A
*Low perid of puLse
95
A LTDATA FCB
A
FCB
91
A
FCB
87
83
FCB
A
A
FCB
79
A
FCB
75
A
FCB
71
FCB
67
A
FCB
63
A
A
FCB
59
55
A
FCB
FCB
51
A
47
A
FCB
FCB
43
A
FCB
39
A
A
FCB
35
A
FCB
31
FCB
27
A
A
FCB
23
19
A
FCB
FCB
15
A
FCB
11
A
FCB
7
A
FCB
A
3
************************************************
*
*
VECTOR ADDRESSES
*
*
*
*
************************************************
*
~HITACHI
910
OOl72A
00173
00174A
00175A
00176A
OOlnA
00178A
00179A
00180A
00181A
00182A
00183A
00184A
00185
00186
FFEA
FFEA
FFEC
FFEE
FFFO
FFF2
FFF4
FFF6
FFF8
FFFA
FFFC
FFFE
COOO
C02C
COOO
COOO
COOO
COOO
COOO
COOO
COOO
COOO
COOO
A*
A
A
A
A
A
A
A
A
A
A
*
oRG
$FFEA
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
OUMN
OUOUT
OUMN
OUMN
OUMN
OUMN
OUMN
OUMN
OUMN
OUMN
OUMN
IRQ2
CMI
TR(~P
SID
TOI
oCI
ICI
IRQlIISF
SWI
NMI
RES
ENO
I
~HITACHI
911
SECTION 4.
4.1
PULSE WIDTH MEASUREMENT
HARDWARE DESCRIPTION
4.1.1
Function
Measures the High period of a pulse to determine pulse width in the
range from
lOO~s
to
65535~s
x with an accuracy of plus or minus
l~s;
stores result as a binary coded decimal (BCD) number.
4.1.2
Microcomputer Operation
The HD6301YO uses the input capture interrupt function of timer 1 to
fetch values in the free running counter on the rising and falling
edges of the Tin pin, using the difference between these values to
measure the pulse width.
4.1.3
Circuit Diagram
Pulse width measurement circuit is shown in figure 4-1.
Meu
HD6301YO
(HD6303Y)
4 MPo
5 MP,
8 NMI
7 STBY
f: :.: ::::L
33 Vee
22pF
Pulse input
+5V
1S207
Figure 4-1.
Pulse Width Measurement Circuit
~HITACHI
912
4.1.4
Pin Functions
Pin functions for pulse width measurement is shown in table 4-1.
Table 4-1.
Pin Functions
Pin Name
(HD6301YO)
Input/
Output
Active level
(High or Low)
Input
4.1.5
Program
Label
Function
Detects rising and falling
edges.
Hardware Operation
Figure 4-2 shows pulse width measurement.
is 4 MHz, E clock cycle is
l~s.
Since oscillator frequency
In figure 4-2, pulse width is
Value counted by
free running counter=N
4~s.
N=4
E clock
--------~I
------.l.r
Pulse width
I
\4----"
Figure 4-2.
Measure Pulse Width
~HITACHI
913
4.2
SOFTWARE DESCRIPTION
4.2.1
Program Module Configuration
The program module configuration for pulse width measurement and BCD
conversion is shown in figure 4-3.
PWMN
l.2..
MAIN
PROGRAM
P WeNT
I
I
HEX
~
4.2.2
l!.
CONVERT
HEXADECIMALS
INTO BCD
MEASURE
PULSE WIDTH
Figure 4-3.
I
Program Module Configuration
Program Module ,Functions
Program module functions are summarized in table 4-2.
Table 4-2.
Program Module Functions
No.
Program Module Name
Label
Function
o
1
MAIN PROGRAM
PWMN
Measures pulse width as a BCD number.
MEASURE PULSE WIDTH
PWCNT
Obtains pulse width as a 2-byte
hexadecimal number.
2
CONVERT HEXADECIMALS
IN'IO BCD
HEX
Converts 2-byte hexadecimal number
into BCD number.
(Refer to HEX in
HD630l/HD6303 FAMILY APPLICATION
NOTES (SOFTWARE) for details.
~HITACHI
914
4.2.3
Program Module Process Flow (Main Program)
The flowchart in figure 4-4 is an example of the pulse width measurement
performed by the program module in figure 4-3.
Main program
- --{ Initialize stack pointer.
{
Initialize flag indicating whether or
not pulse width measurement is completed.
---{ Select port 2 as input.
Initialize timer control/status register I
---{ to enable input capture interrupt and
trigger on rising edge of Tin pin.
---{ Enable interrupts.
___ {Test if pulse width measurement is
completed.
___ {Load 2-byte hexadecimal pulse width into
entry argument of HEX.
___ {Clear flag indicating pulse width
measurement is completed.
Call HEX to convert 2-byte hexadecimal
--- [ pulse width into BCD number.
Refer to HEX in HD630l/HD6303 FAMILY
)
(
APPLICATION NOTES (SOFTWARE) for details.
I
Input Capture Interrupt Routine
___ {Obtain Pulse width as a 2-byte hexadecimal
number.
Figure 4-4.
Program Module Flowchart
~HITACHI
915
PROGRAM MODULE DESCRIPTION
4.3
Program Module Name: MEASURE PULSE
WIDTH
MCU/MPU: HD6301YO/
Label:PWCNT
.HD6303Y
Function:
Obtains pulse width as a 2-byte hexadecimal number, and stores result in PWDAT
(RAM) •
Arguments:
Chan~es
Storage
No. of
Location Bytes
Contents
in CPU
Re9:isters and
Entry
Specifications:
Fla~s:
ACCD
ACCA ACCB
ROM (Bytes): 29
I·
RAM (Bytes): 5
x
x
Stack (Bytes): 0
IX
•
No. of cycles: 400
. Reentrant: No
Returns
Pulse
width
PWDATA
(RAM)
2
Flag indicating
completion
of measurement
ENDF
(RAM)
1
•
x
t
C
V
x
x
Z
x
N
x
I
H
•
•
Relocatable: No
Interrupt OK?: No
Not affected
Undefined
Result
Description:
1.
Function Details
a.
Argument details
PWDATA(RAM): Contains pulse width as a 2-byte hexadecimal number.
ENDF(RAM)
Contains flag indicating whether or not pulse width
measurement is completed.
Table 4-3 shows flag function.
Specifications Notes:
~HITACHI
916
Program Module Name: MEASURE PULSE
WIDTH
MCU/MPU:
HD6301YO/
HD6303Y
IL'bel'
PWCNT
Description:
Table 4-3.
b.
Flag Functions
Label
bit 0
Function
ENDF
o
Indicates pulse width measurement is not completed.
1
Indicates pulse width measurement is completed.
Example of PWCNT execution is shown in figure 4-5. If pulse, whose High
period of pulse is 150 I1s, is input as shown in part Q) of figure 4-5,
measurement result is ~tored in PWCNT(RAM) as a hexadecimal number and
"1" is stored in ENDF(RAM).
CD
j
'L
1501's
f'
Input pulse Tin
p..:,jl------i
1
@
2 Return
blS PWDATA PWDATA+l bO
arguments p~t6~~~)1
0
: 0
I
9
:
6
ENDF(RAM) b7 ENDF bO
($01)
Figure 4-5.
c.
2.
I0
: 1
I
Example of PWCNT Execution
PWCNT calls neither the program modules nor subroutines.
I
User Notes
The following procedure must be performed before PWCNT execution.
a.
Initialize flag indicating whether or not pulse width measurement is
completed.
b.
Select bit 0 of port 2 as input.
c.
Initialize timer control/status register 1 to enable input capture
interrupt and trigger or rising edge of Tin pin.
d.
Enable interrupts.
@HITACHI
917
Program. Module Name: MEASURE PULSE
WIDTH
.M_C_U_/_M_P_U_:_HD_6_3_0_l_Y_O_/
HD6303Y _ _
I-
~ I. Label, PWCNT
Description:
3.
RAM Allocation
Label
4.
LCRUP
Values in input capture register or rising
edge of input pulse.
PWDATA
2-byte hexadecimal pulse width.
ENDF
Flag indicating whether or not pulse width
measurement is completed.
Sample Application
PWMNl
BCLR
O,ENDF
CLRA
STAA
LDAA·
STAA
CLI
P2DDR
#$12
TCSRl
BTST
BEQ
LDD
STD
o ,ENDF}
PWMNl
PWDATA}
HEXD
I
I
I
5.
Description
RAM
Clear flag indicating whether or not pulse
width measurement is completed.
}
Select port 2 as input.
}
Initialize timer control/status register.
Enable interrupts.
Test if pulse width measurement is
completed.
Store return arguments of PWCNT in RAM.
Basic Operation
a.
Input pulse to Tin pin is evaluated as to whether input capture interrupt
is generated on rising edge of pulse or on falling edge.
b.
If rising edge, value in input capture register is stored in ICRUP(RAM)
and timer control/status register 1 is defined to generate next
interrupt on falling edge of pulse.
c.
If falling edge, value in ICR(RAM) is subtracted from value in input
capture register to obtain pulse width. Then, timer control/status
register 1 is defined to generate next interrupt on rising edge of pulse.
~HITACHI
918
Program Module Name: MEASURE PULSE
WIDTH
M_C_U_I_M_P_U_:_HD_6_3_0_I_Y_O_/
_ _ _ _...
.
HD6303Y _ _...J lL_a_b_e_l_:_PW_C_NT
L..
Flowchart:
__ {Clear input capture interrupt request
flag.
(l,TCSRl) =
°
__ {
Test whether in'terrupt is generated on
rising edge of pulse or falling edge.
(1, TCSR1) ,,0
--
{
Store value in input capture register on
rising edge of pulse.
Define timer control/status register I
- - { to generate next interrupt on falling
edge of pulse.
__ { Obtain pulse width by calculating
difference between rising edge and falling
edge of input capture register.
__ {store n 1 n in flag to indicate pulse width
measurement is completed.
__ { Define timer control/status register I
to generate next interrupt or rising
edge of pulse.
PWCT2
~HITACHI
919
4.4
SUBROUTINE DESCRIPTION
This application example calls no subroutines.
4.5
PROGRAM LISTING
00001
00002
00003
00004A
00005
00006A
00007A
00008A
00009A
00010A
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023A
00024
00025A
00026A
00027A
00028A
00029A
00030A
00031A
00032A
00033A
00034A
0003SA
00036A
00037A
00038A
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050A
00051A
000S2A
00053A
000S4A
000S5A
00056A
000S7A
*
****
*
0040
0040
0042
0044
0045
0047
0002
0002
0001
0002
0003
A *ICRUP
A
A
A
A
PWDATA
ENDF
HEXD
DECD
*
****
0001
0008
OOOD
A*
P2DDR
A TCSR1
A ICR
RAM ALLOCATION
ORG
$40
RMB
RMB
RMB
RMB
RMB
2
2
1
2
3
*************************
ICR data on
PuLse width
Measurement
PuLse width
PuLse width
SYMBOL DEFINITIONS **********************
EQU
EQU
EQU
$01
$08
$OD
Port 2 data dlrctlon register
Timer controL/status reglster1
Input capture register
************************************************
**
MAIN PROGRAM : PWMN
**
*
*
************************************************
*
*
COOO
COOO
C003
C006
C007
C009
COOB
COOD
COOE
COlI
C013
C01S
C017
COlA
COlD
8E
71
4F
97
86
97
OE
7B
27
DC
DD
71
BD
20
013F A PWMN
FE 44
01
12
08
A
A
A
01 44
PWMN1
FB COOE
42
A
45
A
FE 44
C038 A
FE COlD PEND
ORG
$COOO
LDS
BCLR
CLRA
STAA
LDAA
STAA
CLI
BTST
BEQ
LDD
STD
BCLR
JSR
BRA
1I$13F
O.ENDF
InitiaLize stack pointer
CLear flag
P2DDR
11$12
TCSR1
InitiaLize TCSR1
O.ENDF
PWMN1
PWDATA
HEXD
O.ENDF
HEX
PEND
EnabLe interrupts
Test If measure puLse width end?
Branch If not
Load puLse width In HEX data
CLear flag
Convert HEX data Into BCD data
End of program
*****************************************>1<**********
*
*
*
NAME: PWCNT (MEASURE PULSE.WIDTH)
*
*
*
****************************************************
*
*
*
ENTRY
NOTHING
*
*
RETURNS: PWDATA (PULSE WIDTH)
*
*
ENDF
(MEASUREMENT COMPLETION FLAG) >I<
*
*
COIF
C021
C024
C026
C028
C02B
C02D
C02F
DC
7B
27
DD
71
20
93
DD
OD
02
07
40
FD
OA
40
42
****************************************************
A PWCNT
08
C02D
A
08
C037
A PWCT1
A
LDD
BTST
BEQ
STD
BCLR
BRA
SUBD
STD
ICR
1.TCSR1
PWCT1
ICRUP
1,TCSRl
PWCT2
ICRUP
PWDATA
CLear' ICF
Branch If IEDG=O
Define TCSR1
CaLcuLate puLse width
store puLse width In PWDATA
~HITACHI
920
rising edge
data
compLetion flag
In HEX data
In BCD data
00058A
00059A
00060A
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072A
00073A
00074A
00075A
00076A
00077A
00078A
00079A
00080A
00081A
00082A
00083A
00084A
000B5A
00086A
00087A
00088A
00089
00090
00091
00092
00093
00094
00095A
00096
00097A
00098A
00099A
00100A
00101A
00102A
00103A
00104A
00105A
00106A
00107A
OOIOB
00109
Set fl ag
BSET
O.ENDF
1.TCSRI Def1ne TCSR1
BSET
PWCT2 RTI
***************************************************
C031 72 01 44
C034 72 02 OB
C037 38
*
*
*
*
:I<
NAME : HEX (CONVERT 2-BYTE HEXADECIMAL
*
NUMBER INTO 5-DIGIT BCD NUMBER)*
*
*
>I<
***************************************************
*
C038
C039
C03A
C03C
C03E
C040
C043
C046
C049
C04B
C04D
C04E
C05D
C051
C053
C054
C056
4F
SF
DD
97
C6
7B
79
CE
A6
A9
19
A7
09
26
SA
26
39
ENTRY : ACCD (2-BYTE HEXADECIMAL NUMBER)
* RETURNS
: DECD (5-DIGIT BCD NUMBER)
*
*
*****************************************************
HEX
CLear' ACCA
CLear ACCB
CLear 5-dlglt BCD
DECD
DECD+2
STAA
Store shlft counter
LDAB
tH6
HEXD+l
Shlft MSB of HEXD to carry
A HEX2
ASL
A
ROL
HEXD
A
LDX
113
Set addlt10n counter ADDR
DECD-l.X DE CD * 2 + C -) ACCA
A HEXI
LDAA
A
ADCA
DECD-l.X
Convert 1nto BCD data
DAA
46
A
STAA
DECD-l.X Store 5-dlglt BCD area
Decrement AD DR polnter
DEX
F6 C049
BNE
LOOD unt1L ADDR Dolnter=O
HEXI
Decrement shlft counter
DECB
EA C040
BNE
HEX2
LOOD untlL sh1ft counter=O
RTS
************************************************
47
49
10
0046
0045
0003
46
46
A
A
A
STD
*
*
VECTOR ADDRESSES
*
*
*
*
************************************************
*
$FFEA
ORG
FFEA
FFEA
FFEC
FFEE
FFFO
FFF2
FFF4
FFF6
FFF8
FFFA
FFFC
FFFE
CLRA
CLRB
COOO
COOO
COOO
COOO
COOO
COOO
COIF
COOO
COOO
COOO
COOO
A
A
*
A
A
A
A
A
A
A
A
A
*
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
PWMN
PWMN
PWMN
PWMN
PWMN
PWMN
PWCNT
PWMN
PWMN
PWMII!
PWMrJ
IRQ2
CMI
TRAP
SID
TOI
OCI
ICI
IRQlIISF
SWI
NMI
RES
END
I
~HITACHI
921
SECTION 5.
5.1
INPUT PULSE COUNT
HARDWARE DESCRIPTION
5. 1. 1
Function
Counts input pulses up to 255 pulses; the count value is returned as a
binary coded decimal (BCD) number.
5.1.2
Microcomputer Operation
The HD6301YO uses TCLK pin to input pulses and timer 2 up counter to
count the input pulses.
Beginning and ending of pulse counting is
performed by setting and clearing timer 2 enable bit in timer control/
status register 3.
5.1.3
Circuit Diagram
Input pulse measurement circuit is shown in figure 5-1.
MCU
HD6301YO
(HD6303Y)
4,
MPo
MP1
NMI
f
STBY
33 Vee
i-=2::!2pF~-=2-l X TAL
4MHzD
3--1 EXT A L
1--+_
22pF
HV
1S2076
~+----=--lR
ES
Pulse input
Vss
P 27 / TCLK 1-'1,.,6'--_ _ _ _ _ _ _ _ _ _-0
Figure 5-1.
Input Pulse Measurement Circuit
~HITACHI
922
5.1.4
Pin Functions
Pin functions of HD6301YO for counting pulses is shown in Table 5-1.
Table 5-1.
5.1.5
Pin Functions
Pin Name
(HD6301YO)
Input/
Output
P27/TCLK
Input
Active Level
(High or Low)
Program
Label
Function
Inputs pulse event
Hardware Operation
Figure 5-2 shows input pulse count using TCLK pin of the HD6301YO.
To set start/end timing for counting input pulses, the procedure
below must be performed in the main program.
i.
ii.
iii.
Set flag in STRTF(RAM).
Execute 200 ms software timer.
Clear flag is STRTF(RAM).
TCLK pin
Pulse count start
(N=O)
Figure 5-2.
End
(N=5)
N: Number of
Pulses
Input Pulses Count
/
$
HITACHI
923
5.2
SOFTWARE DESCRIPTION
5.2.1
Program Module Configuration
The program module configuration for input pulse count is shown in
figure 5-3.
PLSMN
~
MAIN
PROGRAM
PLSCNT
COUNT
PULSES
Figure 5-3.
5.2.2
I
I
HEX
~
I
L:.
CONVERT
HEXADECIMALS
INTO BCD
Program Module Configuration
Program Module Functions
Program module functions are summarized in table 5-2.
Table 5-2.
Program Module Functions
No.
Program Module Name
Label
Function
o
MAIN PROGRAM
PLSMN
Counts input pulses as a BCD numbers.
1
COUNT PULSES
PLSCNT
Counts input pulses as a hexadecimal
number.
2
CONVERT HEXADECIMALS HEX
IN'ID BCD.
Converts 2-byte hexadecimal number
into BCD number. Refer to HEX in
HD630l/HD6303 FAMILY APPLICATION
NOTES (SOFTWARE) for details.
~HITACHI
924
5.2.3
Program Module Process Flow (Main Program)
The flowchart in figure 5-4 is an example of counting input pulses,
performed by the program module in figure 5-3.
Main program
--{ Initialize stack pointer.
Initialize timer control/status register 3
- - { to input external clock and disable clock
input to timer 2 up counter.
--{ Set "1" in start/stop request flag.
--1[Execute PLSCNT to count input pulse.
Execute 200ms software timer.
__ {Clear start/stop request flag to stop
input pulse count.
__ {Execute PLSCNT to obtain input pulse
count result.
I
__ { Load input pulse count result into entry
arguments of HEX.
- -
Figure 5-4.
i
call HEX to convert hexadecimal count
result into a BCD number.
Refer to HEX in HD6301/HD6303 FAMILY
APPLICATION NOTES (SOFTWARE) for
details.
Program Module Flowchart
~HITACHI
925
5.3
PROGRAM MODULE DESCRIPTION
Program Module Name: COUNT PULSES
MCU/MPU:HD630lYO/
HD6303Y
Label: PLSCNT
Function:
Counts pulses input from TCLK pin, and loads count result into ACCA.
Changes in CPU
Arguments:
Contents
Entry Start/stop
request
flag
Storage
Location
No. of
Bytes
STRTF
1
Specifications:
Registers and Flags:
ACCD
ACCA ACCB
x
•
(RAM)
ROM (Bytes) : 20
RAM (Bytes) : 1
Stack (Bytes) : 0
IX
•
No . of cycles:
30
Reentrant: No
RePulse count ACCA
turns result
1
•
x
:
C
x
V
Z
x
N
x
I
H
•
•
x
Relocatab1e: No
Interrupt OK?: Yes
Not affected
Undefined
Result
Description:
1.
Function Details
a.
Argument details
STRTF(RAM): Holds flag indicating whether input pulse count will start
or stop. Table 5-3 shows flag functions.
ACCA:
Contains input pulse count result as a l-byte hexadecimal
number.
Specifications Notes:
"No. of cycles" in "Specifications" indicates the number of cycles required to
start input pulse count.
~HITACHI
926
Program Module Name: COUNT PULSES
MCU/MPU: HD6301YO/
HD6303Y
ILabe"
PLSCNT
.Description:
b.
Example of PLSCNT execution is shown in figure 5-5.
i.
ii.
If bit 0 of entry argument STRTF(RAM) is set to "1", input pulse
count starts as shown in port 1<>1<>1<>1<
A *TCSR3
1
3
*************************
Start/stop request flag
Count result in HEX data
Count result in BCD data
SYMBOL DEFINITIONS **********************
EQU
$IB
Timer control/status register 3
$10
Timer 2 UP counter
A T2CNT EQU
************************************************
"
*
MAIN PROGRAM : PLSMN
*
*
**************************************~**********"
*
COOO
COOO
C003
C005
C007
COOA
COOC
COOF
COIl
C012
C014
C015
C017
COlA
COl C
COIF
CO~? \
C02)
8E
86
97
72
80
CE
86
4A
A"
PLSMN
013F
A
03
IB
A
01 40
19 C025
00C8 A
C8
A PLSMNl
PLSMN2
26 FD CO 11
09
26 F8 COOF
71 FE 40
80 09 C025
.?~ 0041
A
9/ 42
A
8U I?
C03(~
20 FE [023 PEND
ORG
$COOO
LOS
LDAA
STAA
BSET
BSR
LDX
LOAA
tl$13F
tl$03
TCSR3
O.STRTF
PLSCNT
tl200
tl200
Initialize stack pointer
Initialize TCSR3
Set flag to request starting
Start pulse count
Execute 200ms software timer
OEcr~
BNE
DEX
BNE
BCLR
BSR
CL.R
STAA
BSR
BRA
PLSMN2
PLSMNI
O.STRTF
PLSCNT
HEXD
HEXD+l
HEX
PEND
Clear flag to request stop~in9
Stop pulse count
Clear u~per byte of HEXD
Load count result Into lower byte
Convert count result Into BCD data
End of program
*********)k:~****~*'k*************************~*)kl,t
~
>I<
*
NAME : PLSCNT (COUNT PULSE)
***M(******************************************~~(*
~
>I<
*
ENTRY: STRTF (START/STOP REQUEST FLAG)
RETURNS : ACCA (PULSE COUNT RESULT)
*
***********M~:****************~:*****~C:k*********~C**"
C025
C028
C02A
C02D
C02F
C031
C033
C035
C037
PLSCNT BTST
7B 01 40
BEQ
27 09 C033
CLR
7F OOlD A
LDAA
A
86 13
97 IB
A
STAA
BRA
20 06 C039
86 03
A PLSCTI LDAA
STAA
97 IB
A
LDAA
96 10
A
O.STRTF
PLSCTl
12CNl
tlS13
TCSR3
PLSC T2
Test if count start or stop?
Branch if stop
Clear T2CNT
Start pulse count
~$03
Stop pulse count
TCSR3
T2CNT
load pulse count result Into ACCA
~HITACHI
930
*
*
00058A
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070A
00071A
00072A
00073A
00074A
00075A
00076A
00077A
00078A
00079A
00080A
00081A
00082A
00083A
00084A
00085A
00086A
00087
00088
00089
00090
00091
00092
00093A
00094
00095A
00096A
00097A
00098A
00099A
OOlOOA
00101A
00102A
00103A
00104A
00105A
00106
00107
C039 39
PLSCT2 RTS
**********************)k*****~'*******~(****~C******~: **
**
** NAME : HEX (CONVERTING ?-BYTE HEXADECIMALS
>\<
INTO S--DIGlT BCD)
"
>\<
*
*********************M;ll:***~)ki;~***:k*~:*A:***'I(** :k******
*
*
>\<
>\<
C03A
C038
C03C
C03E
C040
C042
C045
C048
C048
C04D
C04F
COSO
C052
C053
C055
C056
C058
>\<
ENTRY : HEXD (2-BYTE HEXADECIMAL NUMBER)>\<
RETURNS : DECD (5-DIGIl 8CD NUMBER)
*
4F
HEX
CLear- ACCA
CLRA
SF
CLRB
CLeat' ACCB
DD 43
A
STD
DECD
CLear 5-digit BCD are~
97 45
STAA
DECD+2
A
C6 10
A
LDAB
IH6
Set shift counter
78 0042 A HEX2
HEXD+1
Shift MSB of HEXD to carry
ASL
79 0041 A
RoL
HEXD
CE 0003 A
Set ADDR pointer(addition counter)
LDX
~3
A6 42
LDAA
DECD-I. X DE CD >I< 2 + C -) ACCA
A HEX1
A9 42
A
ADCA
DECD-1, X
19
DAA
Convert into BCD
A7 42
DECD-1, X Store 5-digit BCD area
A
STAA
09
Decrement AD DR pointer
DEX
26 F6 C04B
BNE
HEX1
Loop untiL ADDR polnter=O
SA
Decrement shift counter
DECB
26 EA C042
Loop untiL shift counter=O
BNE
HEX2
39
RTS
************************************************
*
>\<
VECTOR ADDRESSES
>I<
>I<
>I<
*
************************************************
*
FFEA
oRG
$FFEA
FDB
FDB
FDB
FDB
FD8
FDB
FDB
FDB
FDB
FDB
FDB
PLSMN
PLSMN
PLSMN
PLSMN
PLSMN
PLSMN
PLSMN
PLSMN
PLSMN
PLSMN
PLSMN
>I<
FFEA
FFEC
FFEE
FFFO
FFF2
FFF4
FFF6
FFF8
FFFA
FFFC
FFFE
COOO
COOO
COOO
COOO
COOO
COOO
COOO
COOO
COOO
COOO
COOO
A
A
A
A
A
A
A
A
A
A
A
IR02
CMI
TRAP
SID
TOI
oCI
ICI
IROliISF
SWI
NMI
RES
>I<
END
~HITACHI
931
SECTION 6.
6.1
8 x 4 KEY MATRIX
HARDWARE DESCRIPTION
6.1.1
Function
Performs key scan of 8 x 4 key matrix, invalidating simultaneous
depression of more than 2 keys by software, and converting valid key
data into ASCII characters (AIV Z or 1 IV 6) •
6.1.2
Microcomputer Operation
The HD6301YO uses timer 1 to execute output compare interrupt 1 every
Bms.
Key scan is performed by an output strobe signal through port 4,
controlling DDR (data direction register) of port 4.
Since all parts
except port 4 are input ports (high impedance state), diodes for
preventing output signal collision are not necessary.
is fetched through port 3 during the interrupt routine.
6.1.3
Peripheral Devices
8 x 4 Key matrix : Keys to be depressed.
6.1.4
Circuit Diagram
Key scan control circuit is shown in figure 6-1.
~HITACHI
932
Key scan data
+5V
MCU
HD6301 YO
4 MPo
5
MP1
8 NMI
f
7 STBY
33
2 Vee
f--!P:""---I XT AL
22 F
4MHzCJ
41
KRO
P40 I----="'-{
P411-4_0_ _K_R-{1
3 EXTAL 1'.2 r3_9_-,K=R2:q
38
KR3
1'.31---~~
22pF
+5V
IS2076
KCo
P
Vss
KCl KCZ
KC3
KC4
KC5
KC6
""'5.:;;.8_ _ _-'
30
57
P 31 1 - - -_ _ _ _----'
P 5_6 _ _ _ _ _ _ _ _-l
r
32 55
P3SI------------~
P
----l
1"5..:.4_ _ _ _ _ _ _ _ _ _ _ _
S4 53
P35~--------------~
P
r5~Z
36
_________________
~
51
P 37 r------------------------l
Figure 6-1.
Key Scan Control Circuit
I
~HITACHI
933
6.1.5
Pin Functions
Pin functions at the interface between the HD6301YO and the key matrix
are shown in table 6-1.
Table 6-1-
Pin Functions
Pin Name
(HD6301YO)
Input!
Output
Active Level
(High or Low)
P40
Input!
Output
Input!
Output
Input/
Output
Input/
Output
Low
P41
P42
P43
6.1.6
Pin Name
(Key matrix)
Program
Label
KRo
P4DTR
Function
Outputs strobe
signal
Low
KRl
Low
KR2
Low
KR3
P 30
Input
P 31
Input
P 32
Input
KC2
P 33
Input
KC3
P 34
Input
KC4
P 3S
Input
KCs
P 36
Input
KCG
P 37
Input
KC7
Inputs key
data
P3DTR
KCo
KCl
Hardware Operation
The timing chart for key scan is shown in figure 6-2.
OFF
:~n:~pression ON
____________ _Vyj\:.....L...______O
_ N__
----...--.-'
Chatter
Key fetch
timing
(Timer interrupt)
CD
®
CD
CD First key data
® Second key data
®
®
®
® Third key data
ON
Key data
valid timing
OFF
I
r
Key data is valid
Figure 6-2. Chatter Prevention Timing
Key depression signal is checked every 8 ms. If key data is the same 3
consective times, it will then be valid, and invalid otherwise.
~HITACHI
934
6. 2
SOFTVIARE DESCRIPTION
6.2.1
Program Module Configuration
The program module configuration for key scan of 8 x 4 key matrix is
shown in figure 6-3.
K84.MN
MAIN
PROGRAM
84. SCN
K
~
I
~
KEY SCAN
Figure 6-3.
6.2.2
Program Module Configuration
Program Module Functions
Program module functions are summarized in table 6-2.
Table 6-2.
Program Module Functions
No.
Program Module Name
Label
Function
o
MAIN PROGRAM
K84MN
Performs key scan of 8X4 key matrix
and converts key data into ASCII.
1
KEY SCAN
K84SCN
Performs key scand of 8x4 key
matrix.
I
~HITACHI
935
6.2.3
Program Module Process Flow (Main Program)
The Flowchart in figure 6-4 is an example of a key scan of the 8 x 4 key
matrix performed by the program module in fiqure 6-3.
Main program
--- {Ini tialize stack pointer.
---I
C1e= .... uoed by KB4SCN.
___ {Initialize timer control/status register
1 to enable output compare interrupt.
---1[Initialize port 4.
----[Enable interrupt.
depressed.
valid key number into ACCS.
---{ Clear flag to indicate key is depressed.
---{Load starting address of data table into IX.
---{Load data table pointer into IX.
---{store ASCII in RAM.
OCI interrupt routine
. - - {Execute I 1, key scan is completed since i t
indicates two keys are pressed at the same time.
~HITACHI
939
I
I
Progr= Module Name: KEY SCAN
MCU/MPU: HD630lYO
Label: K84SCN
Description:
d.
Key data (NEWKEY(RAM)) obtained in (C) is compared with previous key data
(OLDKEY(RAM)). If they are the same, chatter counter (CHATEL(RAM)) is
counted up. When chatter counter becomes "3", key data is valid. If
key data is valid, MSB of CHATFL(RAM) is set to "1" to indicate key data
is valid. CHATFL(RAM) includes both a counter and a flag. CHATFL(RAM)
is cleared, when NEWKEY(RAM) data differs from OLDKEY(RAM) data or no key
is depressed.
~HITACHI
940
Program Module Name: KEY SCAN
MCU/MPU: HD6301YO
~ K84SCN
Flowchart:
- -
1
Reinitialize output compare register 1 to enable
output compare 1 and generate interrupt 8 ms
later.
__ {Test if key data has been processed in main
program.
- - { Initialize data for output strobe signal.
- - { Initialize RAM for key number.
- - { Initialize RAM for number of depressed keys.
- - { Initialize RAM for new key number.
- - { Output strobe signal.
- - { Load key scan data into ACCA.
Test if a key is depressed everY time
- - { strobe signal is output.
I
key is depressed, store next starting
~HITACHI
941
Program Module Name: KEY SCAN
MCU/MPU: HD630lYO
~ K84SCN
Flowchart:
--
{
Initialize shift counter to test which
key is depressed.
--{ Shift key scan data 1 bit right.
--{ Test if key is depressed.
--Il
Test if key chatter is generated.
If so, complete key scan.
__ {store depressed key number in RAM as
key data.
--{ Increment RAM indicating key number.
- - {Decrement shift counter.
__ {Test if all keys have been checked
whether or not they are depressed.
__ {Load strobe signal data to perform key
scan for next column.
{
Test if key scan for all columns have been
completed.
- - { Test if a key is depressed this time.
__ {compare current key data and previous
key data.
Store current key data in RAM for next key
__ [ scan. Clear RAM indicating number of key
scan.
~HITACHI
942
Program Module Name: KEY SCAN
MCU/MPU: HD6301YO
Label: K84SCN
Flowchart:
---[Test if key data is valid.
Test if key scan has been executed 3
times.
___[Increment RAM indicating number of
key scan.
__ {set flag to "1" to indicate key data
is valid.
__ 1r
Store valid key number in return
argument.
'-
Set fl'3.g to "1" to indicate a key is
{ depressed.
I
~HITACHI
943
6.4
SUBROUTINE DESCRIPTION
This application example calls no subroutines.
6.5
PROGRAM LISTING
00001
00002
00003
00004A
00005
00006A
00007A
00008A
00009A
00010A
OOOllA
00012A
OOOBA
00014A
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
0002B
00029
00030
00031A
00032
00033A
00034A
00035A
00036A
00037A
0003BA
00039A
00040A
00041A
00042A
00043A
00044A
00045A
00046A
00047A
0004BA
00049A
00050
00051
00052
00053
00054
00055
00056
00057
*
****
*
ORG
A *I1<>1<>1<>1<**
*
MAIN PROGRAM : ADMN
>I<
>I<
>I<
*
>I<
************************************************
013F
*
*
A AD~lN
40
E2
14
02
15
20
A
A
A
A
A
A
COOO
COOO
C003
C004
C006
C008
COOA
COOC
COOE
COlO
COll
C014
C017
C019
COlC
COlD
COIF
C021
C023
C026
8E
4F
97
86
97
86
97
97
OE
71
7B
27
71
4F
97
96
97
BD
20
FD 15
ADMNI
01 40
FB C014
FE 40
42
A
(.,
41
43
A
C036 A
EC C014
ORG
$COOO
LDS
CLRA
STAA
LDAA
STAA
LDAA
STAA
STAA
CLI
BCLR
BTST
BEQ
BCLR
CLRA
STAA
LDM
STAA
,JSR
BRA
tI$13F
ADEND
tI$E2
RP5CR
tI$02
P5DTR
P5DDR
1,P5DTR
O,ADEND
ADMN1
O,ADEND
HEXD
ADDM
HEXD+1
HEX
ADMNI
InitiaLize stacl< pointer
CLear' RAM
InitiaLize RAM/Pod 5 contr'oL
EnabLe i nter-rupts
Set ADS to Low
Test if AID conversion compLete
CLear' compLete Hag
Load AID COllver's ;on r'esu Lt in HEX data
Conver't HEX data into BCD data
******************~(~::K******~:***~::k*:k***********~!*
NAME : ADIN (INPUT AID CONVERSION
RESULT)
***~****************~(*~c*******************~~*****
**
*
>I<
*
ENTRY
NOTHING
*
RETURNS : ADDAT (AID CONVERSION RESULT) *
ADEND (AID CONVERSION COMPLETE*
FLAG)
*
C028 72 02 15
*
********=K~~************************~C***********~:*
ADIN
BSET
1,P5DTR
r'8g i ster'
InitiaLize port 5
Set ADS to High
~HITACHI
954
conversion
conver'sion
conversion
conversion
00058A
00059A
00060A
00061A
00062A
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074A
00075A
00076A
00077A
00078A
00079A
00080A
0008lA
00082A
00083A
00084A
00085A
00086A
00087A
00088A
00089A
00090A
00091
00092
00093
00094
00095
00096
00097A
00098
00099A
OOlOOA
OOlOlA
00102A
00103A
00104A
00105A
00106A
00107A
00108A
00109A
00110
00111
C02B
C02D
C02F
C032
C035
96
97
72
71
3B
LDAA
S TAA
SSET
BCLR
RTI
06
A
41
A
01 40
FE 15
P3DTR
Load AID conversion result
(~DDAT
O.ADEND
O.PSOTR
Set AID conver'slon complete flag
Set ADS to Low
NAME : HEX (CDNVERT 2-BYTE HEXAOECIMALS
INTO 5-DIGIT BCD)
*
*
"*
ENTRY : HEXD (2-BYTE HEXADECIMAL NUMBER)
RETURNS : DECD (S-DIGIT BCD NUMGER)
*
*******************~(~(***~·l.,)k~*:k*:I:*:k*~·~I,::~:~*~(**~(******'k
C036
C037
C038
C03A
C03C
C03E
C041
C044
C047
C049
C04B
C04C
C04E
C04F
C051
C052
C054
4F
SF
DD
97
C6
78
HEX
CLRA
CLI~B
44
46
10
0043
79 0042
CE 0003
A6 43
(W 43
19
A
A
A
A HEX2
A
A
A HEXI
A
43
~\
09
26 F6 C047
SA
26 E(\ CaSE
39
f\?
STD
ST(~A
LDAB
ASL
RDl_
LOX
LO~,A
ADCA
DAA
STAA
DEX
BNE
DECe
BNE
RTS
DECD
DECD+2
tj16
HEXD+l
CLear ACeA
Clea" ~\CCB
Clear 5-dlglt BCD
Store shift counter
Sh 1 ft M:=S of HEXD to r.a'TY
!-IDCD
tj3
Set AODR ~ointer (addition counter)
JECD-l. X DECD * 2 j C -) ACCA
DECD- l • X
Conve,'t Into BCD data
DECD-l. X Store 5-dlglt BCD area
Dec"ernellt (-\aDR PO i nte"
Loop until ADDR polnter=O
HEX:
DeCI'elllE'llt sll 1 ft CDLm te"
loop until shift cQunter=O
HEX2
,I'
>I>
VECmR ADDrlESSES
)1,
'k
~
*t~*********************:k:lc:I:)k***~(*~:i;*:~':iC*~'~~·'~~·~·:!;:I·k
'I'
FFEA
ORG
U:FEA
FDB
FOB
rCDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
ADr1N
'I<
FFEA
FFEC
FFEE
FFFO
FFF2
FFF4
FFF6
FFF8
FFFA
FFFC
FFFE
COOO
COOO
(000
COOO
COOO
COOO
COOO
C028
COOO
COOO
COOO
A
A
A
A
A
A
A
A
A
A
A
"
AD~1N
ADI'IN
e\aMI~
ADMN
ADMN
ADMN
ADIN
ADMN
ADMN
ADMN
IR02
CMI
TRAP
SID
TOI
OCI
ICI
IRQI/ISF
SWI
NMI
RES
END
~HITACHI
955
SECTION 8.
8.1
STANDARD KEYBOARD INTERFACE
HARDWARE DESCRIPTION
8.1.1
Function
Receives key data from a standard ASCII keyboard.
8.1.2
Microcomputer Operation
The HD6301YO accesses data from an ASCII keyboard using a First InFirst Out roll buffer.
Port 6 control/status register is selected to
perform parallel handshaking between the IS pin and port 6.
Input data
is read at the falling edge of the STROBE signal and data is written to
the roll buffer by input strobe interrupt.
8.1.3
Peripheral Devices
Outputs ASCII codes and STIillBE signal.
ASCII keyboard:
8.1.4
Circuit Diagram
The interface circuit for reading data from an ASCII keyboard is shown
in figure 8-1.
U
HD6301YO
(HD6303y)
+5V
~ MP.
~ MP,
~ NMI
~ STBY
22 pI"
4.\"Iz~
.......ll Vee
XTAL
3 EXTAL
pi"
r-IS2 076 ~~
4.71«
6
~
p••
p.,
PM
p..
p••
p.,
'ItES
lid-'
~
40Z
Vss
Po.
Vss
1<'7
31
Ian
29
128
27
26
25
P"./IS 21
II
STROBE B, B. B. B.B,B. £I.,
I
IIII III I
ASCII Keyboard
Figure 8-1.
Reading Data from ASCII Keyboard
$
956
HITACHI
1m
8.1.5
Pin Functions
Pin functions at the interface between the HD6301YO and ASCII keyboard
are shown in table 8-1.
Table 8-1.
8.1.6
Pin Functions
Pin Name
(HD6301YO)
Input/
Output
Active
Level
(High
or Low)
PS4/IS
Input
Low
P 60
Input
P 61
Input
B2
P 62
Input
B3
Function
Pin Name
(Keyboard)
STROBE signal
STROBE
Key data input signal
Bl
P 63
Input
B4
P 64
Input
Bs
P 6S
Input
B6
P 66
Input
B7
Program
Label
P6DTR
Hardware Operation
The timing chart for the ASCII keyboard is shown in figure 8-2.
If a
key in ASCII keyboard is depressed, data and STROBE signal are output
as shown in figure 8-2.
ASCII keyboard
pin names
key data
(Bl~B7) ________~(~______________~)~------------------
STROEiE signal (STROBE)
--------------.....,U
f
Input sErobe interrupt generated
Figure 8-2.
ASCII Keyboard Timing Chart
~HITACHI
957
8.2
SOFTWARE DESCRIPTION
8.2.1
Program Module Configuration
The program module configuration for reading key data from ASCII
keyboard is shown in figure 8-3,
KEYMN
MAIN
PROGRAM
I.!
I
K EYIN
I
KEYOUT
RECEIVE
KEY DATA
Figure 8-3.
8.2.2
l!.
I
READ
KEY DATA
I.!.
Program Module Configuration
Program Module Functions
Program module functions are summarized in table 8-2.
Table 8-2.
Program Module Functions
No.
Program Module Name
Label
Functions
0
MAIN PROGRAM
KEYMN
Receives key data from ASCII keyboard
and accesses roll buffer.
I
RECEIVE KEY DATA
KEY IN
Receives key data and write s then to
roll buffer.
2
READ KEY DATA
KEYour
Reads data in roll buffer.
~HITACHI
958
8.2.3
Program Module Process Flow (Main Program)
The flowchart in figure 8-4 is an example of key data input from ASCII
keyboard performed by the program module in figure 8-3.
Main Program
'--__. . . __--.J----[
' -_ _-,-_ _--1
'--_ _........_ _--1
o -. Bit I
Initialize stack pointer.
----fIni tialize pointers to valid data addresses "
in roll buffer.
____{ Initialize port 6 control/status register
to enable latch and input strobe interrupt.
----{Enable interrupts.
-U----{
u.._ _-,-_ _
Read key data in roll buffer.
(Bit
---[Te,t if there i, key data in roll buffer.
C)tl
....._ _....L._ _- . , ___ {
Store roll buffer data in RAM.
Input strobe interrupt routine.
L-~~~~~~
______ [Receive key data and write them to roll
buffer.
Figure 8-4.
Program Module Flowchart
~HITACHI
959
8.3
PROGRAM MODULE DESCRIPTION
Program Module Name: RECEIVE KEY
DATA
MCU/MPU:
HD6301YOI
HD6303Y
Label: KEYIN
Function:
Receives key data from ASCII key board and writes them to roll buffer.
Arguments: None
Changes in CPU
Specifications:
Registers and Flags:
ACCD
ACCA ACCB
x
x
I
ROM (Bytes): 27
RAM (Bytes): 20
Stack (Bytes):O
IX
No. of cycles: 48
x
Reentrant: No
•
x
t
:
C
V
x
x
Z
N
x
x
I
H
•
•
Relocatable: No
Interrupt OK?: No
Not affected
Undefined
Result
Description:
1.
Function Details
a.
KEYIN has no arguments.
b.
Example of KEYIN execution is shown in figure 8-5. If "A" in ASCII
keyboard is pressed as shown in part
of figure 8-5, key data'is
written to roll buffer as shown in part @ of figure 8-5.
c.
KEYIN calls neither the program modules nor subroutines.
Q)
Specifications Notes:
NIA
~HITACHI
960
Program Module Name! RECEIVE KEY
DATA
M_C_U_I_M_P_U_!_HD_6_3_0_l_Y_O_/
_ _ _.......
HD6303Y _ _..... 1L..L_a_b_e_l_!_KE_Y_I_N
.
L..
Description!
Press
"A" key
b7 PS+l bO
Before
PS+l (RAM) ($ 0 0)
execution
I
I
PE+l (RAM)($ 0 0)
0
: 0
PE+l
0
: 0
I
I
PH
)
t
KEYBUF(RAM)
*'*
16
byte
16
byte
J
~
b7 PS+-l bO
PS+ 1 (RAM) ($ 0 0)
I
execution PE+l (RAM) ($ 01)
I
@ After
(
KEYBUF(RAM)
0 : 0
PE+l
0 : 1
I
I
~
~
* *: Undefined hexadecimal data
Figure 8-5.
2.
*'*
J
Example of KEYIN Execution
User Notes
a.
Both KEYIN and KEYOUT must use the same roll buffer.
b.
The following procedure must be performed before KEYIN execution.
i.
ii.
iii.
iv.
3.
1
}
Initialize pointers to valid data addresses.
Initialize port 6 control/status register to enable latch and
input strobe interrupt.
Enable interrupts.
Press a key in ASCII keyboard.
RAM Allocation
Label
Description
RAM
b7
bO
PS
r-
-
PE
r-
-
KEYBUF
r-
:j
:f--
T
}
}
Starting pointer indicating start address of
valid data in roll buffer.
End pointer indicating last address of valid
data in roll buffer.
16 bytes roll buffer to which key data will
be written.
l'
~HITACHI
961
Program Module Name: RECEIVE KEY
DATA
MCU/MPU: BD630lYO/
BD6303Y
ILabel'
KEYIN
Description:
4.
Sample Application
I
I
I
CLRA
CLRB
STD
STD
IDAA
STAA
CLI
PS
PE
#$48
P6CSR
}
}
----- Initialize pointers.
Initialize port 6 control/status register.
Enable interrupts.
I
I
I
5.
Basic Operation
a.
Roll buffer operation
i.
ii.
When data is written to roll buffer, data is stored in the address
indicated by PE (RAM); PE (RAM) is .then incremented.
iii.
When data is read from roll buffer, data is loaded from the address
indicated by PS(RAM); PS(RAM) is then incremented.
iv.
v.
b.
Data in roll buffer is accessed using starting pointer PS(RAM),
indicating start address, and e~d pointer PE(RAM), indicating
the last address.
When increment of PS(RAM) and PE(RAM) generates overflow, data is
stored from the start address again.
Roll buffer in this program can store I'\, 15 bytes of data.
KEYIN Operation
i.
ii.
iii.
PE(RAM) is incremented and checked if it equals PS(RAM).
If equal, data cannot be written to roll buffer since roll buffer
cannot store more data.
If not equal, data can written to roll buffer and PE(RAM) is
incremented.
~HITACHI
962
Program Module Name: RECEIVE KEY
DATA
MCU/MPU: HD6301YO/
HD6303Y
I
cabel, KEY IN
Flowchart:
--l
fClear input strobe interrupt request flag
to enable interrupts.
--[Load end pointer to last address.
__ {Increment end pointer to last address.
(If over "$F", it becomes "0".)
~-[Teet
if roll buffer ie full.
--[store end pointer.
--{store key data in roll buffer.
I
~HITACHI
963
Program Module Name: READ KEY DATA
Label: KEYOUT
MCU/MPU: HD630lYO/
HD6303Y
Function:
Reads key data from roll buffer.
'Arguments:
Changes in CPU
Storage
Location
Contents
No. of
Bytes
Specifications:
Registers and Flags:
ACCD
ACCA ACCB
x
x
I
Entry _ _
RAM
(Bytes): 18
Stack (Bytes): 0
IX
x
I
ROM (Bytes): 20
No. of cycles: 34
Reentrant: No
Returns
ACCB
Data in
roll buffer
1
Valid data Bit C
indicator (CCR)
1
C
x
V
Z
N
x
x
I
H
•
•
x
t
:
•
Relocatable: No
Interrupt OK?: Yes
•
Not Affected
Undefined
Result
Description:
1.
Function Details
a.
Argument details
ACCB: Contains data read from roll buffer.
bit C(CCR): Contains valid data indicator which shows whether or not
there are valid data in roll buffer.
bit C=O: Indicates data is read from roll buffer.
Specifications Notes:
N/A
~HITACHI
964
IID6303Y _ _..... IL_a_b_e_I_:_KE_Y_O_UT
_
_p_r_o_g_r_am_M_o_d_u_le_N_a_m_e_:_RE_AD
__KE_Y_D_A_T_A_...J ...M_C_U_I_M_P_U_:_IID_6_3_0_I_Y_O_I
_ _ _......J
..
Description:
bit C=l: Indicates there is no data in roll buffer.
b.
Example of KEYOUT execution is shown in fi)lure 8-6. If KEYOUT is
~xecuted with the condition shown in part\1jof figure 8-6, data is stored
in ACCB as shown in part@of figure 8-6.
b7 PS+l
PS+l (RAM)
($01)
Before
$03
execution KEYB UF
(RAM)
PS+1
I
0
I
o :
:
bO
1
PE+1
3
47
40
30
32
PE+1
1 Hbytes
I
I
T
b7
I
[PS+' (RAM)
($02)
G)
After
execution
PE+1(RAM)
($03) Bit C
ACCB
Figure 8-6.
c.
2.
m
I
I
4H
,I
r
PS+l bO
0 : 2
I
PE+l
0
3
:
:
ACCB
0
4
Example of KEYOUT Execution
KEYOUT calls neither the program modules nor subroutines.
I
User Notes
Both KEYIN and KEYOUT must use the same roll buffer and must be executed in
pairs.
~HITACHI
965
Program Module Name: READ KEY DATA
MCU/MPU: HD6301YO/
HD6303Y
I
Label,
KEYOUT
Description:
3.
RAM Allocation
RAM
Label
b7
PS
PE
bO
f-
-
f-
-
}
}
=}
KEYBUP tt1:
4.
Description
T
Starting pointer indicating start address of
valid data in roll buffer.
End pointer indicating last address of valid
data in roll buffer.
16 bytes roll buffer to which key data will be
written.
Sample Application
I
I
I
LOOP
II
JSR
KEYOUT
BCS
STAB
LOOP
WORK
II
----- Call KEYOUT.
---- Test if there is data in roll buffer.
---- Store return argument in RAM.
I
I
I
I
5.
Basic Operation
a.
Contents of starting pointer PS(RAM), indicating starting data address
in roll buffer, is compared with contents of end pointer PE(RAM) ,
indicating last data address in roll buffer.
b.
If equal, bit C is set to "1" since there is no data in roll buffer.
c.
If not equal, data is read from the address indicated by PS+l(RAM) and
PS+l(RAM) is incremented. Bit C is cleared to indicate data is read
from roll buffer.
~HITACHI
966
MCU/MPU: lID6301YO/
lID6303Y
Program Module Name: READ KEY DATA
I~
KEYOUT
Flowchart:
_______ [ Load starting pointer into IX.
______ [
Test if there is data in roll buffer.
______ [Load data in roll buffer into return
argument.
....--_ _.L......_---,- - - - -
O-+Bit C
--
Increment starting pointer to start
address.
_______ [ Clear valid data indicator showing
data is read from roll buffer.
-------
{
Set valid data indicator showing
there is no data in roll buffer.
KEYOT2
R T S
I
~HITACHI
967
8.4
SUBROUTINE DESCRIPTION
This application example calls no subroutines.
8.5
PROGRAM LISTING
00001
00002
00003
00004A
00005
00006A
00007A
00008A
00009A
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022A
00023
00024A
00025A
00026A
00027A
00028A
00029A
00030A
00031A
00032A
00033A
00034A
0003SA
00036A
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048A
00049A
00050A
00051A
000S2A
00053A
00054A
00055A
OOOSM
000S7A
*
0040
************
RAM ALLOCATION
*
$40
ORG
0002 (4 *PS
0040
0042
0044
0054
0002
0010
0001
RMB
A PE
RMB
A II<
COlA
C01C
COlE
C020
C022
C024
C025
C027
C029
ENTRY
NOTHING
RETURNS : ACCB(DATA IN ROLL BUFFER)
CARRY(C=O:TRUE,C=l:FALES)
40
A KEYOUT LOX
42
A
CPX
DC C02C
BEQ
44
LDAB
A
LDAA
A
41
INCA
OF
ANDA
A
41
STAA
A
CLC
01 C02D
BRA
PS
PE
KEYOT1
KEYBUF,X
PS+1
Load starting pointer
Check data in roLL buffer
Branch if no data
Load key data
Increment starting pointer
Il$OF
PS+1
CLear carr'y
II<
NAME: KEYIN (RECEIVE KEY DATA)
*
*
*
***********************************************
*
*
ENTRY : NOTHING
*
RETURNS : NOTHING
>I<
*
*
C02E
C030
C032
C034
C036
C037
C039
C038
C03D
C03F
C041
96
96
DE
D6
5C
C4
D1
27
D7
A7
3B
21
17
42
43
OF
41
04
43
44
.iC
************************************************
A KEYIN LDAA
P6CSR
CLear Interrupt request fLag
A
LDAA
P6DTR
Load end pointer
A
LDX
PE
A
LDAA
PE+l
Increment end pointer
INCB
II$OF
ANDB
A
PS+l
CMPB
A
Test If roLL buffer Is fuLL?
BEQ
II<
RAM ALLOCATION
****
********:k**************
>I<
0040
ORG
$40
RMB
2
>I<
0002
0040
A DATIX
"****
Start address of data table
SYMBOL DEFINITIONS
*******'k***********
>I<
0016
0017
0021
A P6DDR
A P6DTR
A P6CSR
EDU
EDU
EDU
Port 6 data direction register
Port 6 data register
Port 6 control/status register
$16
$17
$21
****~;********************************
>I<
>I<
MAIN PROGRAM : SENMN
>I<
'"
>I<
>I<
*************************************
COOO
ORG
$COOO
tl$13F
H$FF
P6DDR
tl$70
P6CSR
>I<
COOO
C003
COOS
C007
C009
COOB
COOC
COOF
COlI
C013
C015
8E
86
97
86
97
OE
CE
DF
A6
97
20
OUF
FF
16
70
21
C02B
40
00
17
A SENMN
LOS
A
LD~\(~
A
S T(~n
A
A
LO(~I~
STA(-\
eLI
A
LOX
A
STX
LOAA
STAA
A
A
FE C015 PEND
8R~\
tlDMA
DATIX
O.X
Initialize stack pointer
Select por't 6 as output
Initialize P6CSR
EnabLe interrupts
Load data t~ble pointer
Stole data table pointer
Load data
P6DrR
PEND
>I<
'"
'**
" **
C017
C019
C01B
C01C
COlE
C020
C022
C024
C026
C028
C02A
96
DE
08
DF
A6
81
27
97
20
96
3B
21
40
NAME : SEOUT (SEND DATA)
>I< '* >1<>1<* * >I< 'I< *** >I<
*>1<>1< *' ** ** *:k ** * **>1 ·+::t;:I(*
*
'"
>I<
ENTRY
NOTHIG
* RETURNS
NOTING
*
*
*
***************************"'******"''''*'''*'"
>I<
>I<}\(
A SEOUT
A
A
40
A
00
FF
A
04 C028
A
17
02 C02A
A
17
LDAA
P6CSR
Clear interrupt request flag
LDX
DATIX
Increment data table pointer
INX
STX
DATIX
Load data
LDAA
O.X
Test if data=$FF
tl$FF
CMPA
Branch if data=$FF
BED
SEOUTl
Store
data
P6DTR
STAA
Branch always to SEOUT2
BRA
SEOUT2
Dummy read Port 6
P6DTR
SEOUTl LDAA
SEOUT2 RTI
*******************Ht*******************
'"*
I
**
********************************~c********
DATA TABLE
~HITACHI
979
000s8A
000s9A
00060A
0006lA
00062A
00063A
00064A
0006sA
00066A
00067A
00068A
00069A
00070A
00071A
00072A
00073A
00074A
0007SA
00076A
00077A
00078A
00079A
00080A
0008lA
00082A
00083A
00084A
0008sA
00086A
00087A
00088A
00089A
00090A
0009lA
00092A
00093A
00094A
0009sA
00096A
00097A
00098A
00099A
OOlOOA
OOlOlA
00102A
00103A
00104A
OOlOsA
00106A
00107A
00108A
00109A
OOlIOA
OOlllA
001I2A
00113A
001l4A
C02B
C03l
C037
C03D
C040
C046
C04C
COs2
COs8
COsE
C062
C068
C06E
C070
C076
C07C
C082
C08S
C08B
C091
C097
C09D
COA3
COA7
COAD
COB3
COBS
COBB
COCI
COC7
COCA
CODO
COD6
CODC
COE2
COE8
COEC
COF2
COF8
COFA
ClOO
Cl06
ClQC
ClOF
Clls
C11B
C12l
C127
C12D
C13l
C137
C13D
C13F
Ct45
C14B
C1sl
Cls4
4D
20
55
20
48
44
20
33
20
20
59
20
OD
4D
43
55
20
48
44
20
20
30
31
59
30
OD
4D
43
55
20
48
44
36
20
30
20
20
30
OD
4D
43
55
20
48
44
36
20
30
20
20
30
OD
4D
A DATA
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
~~
A
A
A
<;3
p
55
20
48
A
A
A
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCB
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCB
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCB
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCC
FCB
FCC
FCC
FCC
FCC
FCC
/M
M / >1<1 coLumn data
/ CCC /
/U
U/
/
/
/H
1-1 /
/DDD
/
/
66 /
/33333 /
/ 000 /
/ 1 /
/y
Y /
/ 000 /
$OD.$OA
/MM MM / >1<2 coLumn data
C /"
/C
/U
U /
/
/
H/
/D D /
/
/ 6
/
3 /
/0
0 /
/1-1
/
y /
/11
/y
/0
o/
$OD.$OA
/M M M / >1<3 coLumn data
/C
/
/U
U/
/
/
/H
/D
/6
H
D
/
/
/
/
/
3
/0 00
/ 1 /
/ YY /
/0 00 /
$OD.$OA
/M M M / >1<4 coLumn data
/C
/
/U
U /
/
/
/
/HHHHH /
/D
D/
/6666 /
/
3 /
/0 0 0 /
/ 1 /
/
y
/
/0 0 0 /
$OD.$OA
/M
M / >1<5 coLumn data
/C
/
/U
U/
/
/H
/
H/
~HITACHI
980
00115A
00116A
00117A
00118A
00119A
00120A
00121A
00122A
00123A
00124A
00125A
00126A
00127A
00128A
00129A
00130A
00131A
00132A
00133A
00134A
00135A
00136A
00137A
00138A
00139A
00140A
00141A
00142A
00143A
00144A
00145A
00146A
00147A
00148A
00149
00150
00151
00152
00153
00154
00155A
00156
00157A
00158A
00159A
00160A
00161A
00162A
00163A
00164A
00165A
00166A
00167A
00168
00169
05(-\
C160
C166
C16C
Cl72
C176
C17C
C182
C184
C18A
C190
C196
C199
C19F
C1AS
C1AB
C1B1
C187
C1BB
C1C1
C1C7
C1C9
C1CF
C105
ClOB
C10E
C1E4
C1EA
C1FO
C1F6
C1FC
C200
C206
C20C
44
36
20
30
20
20
30
00
40
43
55
20
48
44
36
33
30
20
20
30
00
40
20
20
20
48
44
20
20
20
31
20
20
00
A
A
(-\
A
A
A
~\
A
~\
!-\
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
FCC
10
0 I
FCC
16
6 I
FCC
I
3 I
FCC
100 0 I
FCC
I 1 I
FCC
I
I y
FCC
100 o I
$OO.$OA
FCB
FCC
1M
M I *6 coLumn data
FCC
IC
C I
FCC
III
U I
I
I
FCC
FCC
IH
H I
FCC
ID 0 I
FCC
16
6 I
FCC
13
3 I
FCC
10
0 I
FCC
I 1 I
FCC
Y
I
I
FCC
10
oI
$OO.$OA
FCB
FCC
1M
M I *7 coLumn data
I CCC I
FCC
FCC
I UUU I
I
FCC
/
FCC
IH
H I
FCC
1000
I
FCC
I 666 I
FCC
I 333 I
FCC
I 000 I
FCC
1111 I
FCC
I y
/
FCC
I 000 I
$OO.$OA,$FF
FCB
*********"'*****",****",*********>1<",>1<",,,,***>1<>1<
*
*
VECTOR ADDRESSES
*
*
>I<
'"
****************************************
*
$FFEA
oRG
FFEA
>I<
FFEA
FFEC
FFEE
FFFO
FFF2
FFF4
FFF6
FFF8
FFFA
FFFC
FFFE
COOO
COOO
COOO
COOO
COOO
COOO
COOO
C017
COOO
COOO
COOO
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
A
A
A
A
A
A
A
A
A
A
A
SENMN
SENMN
SENMN
SENMN
SENMN
SENMN
SENMN
SEoUT
SENMN
SENMN
SENMN
IRQ2
CMI
TRAP
SID
TOI
oCI
ICI
IRQlIISF
SWI
NMI
RES
>I<
END
I
~HITACHI
981
SECTION 10.
10.1
DATA TRANSFER WITH ASYNCHRONOUS SCI
HARDWARE DESCRIPTION
10.1.1
Function
Receives ASCII from the console typewriter as asynchronous serial data,
and sends ASCII to the console typewriter converting lower case letters
into uppercase letters.
10.1.2
Microcomputer Operation
The HD6301YO sends/receives data to/from the console typewriter by
asynchronous SCI (serial communication interface), defining the band
rate as 4800 BPS.
RS232C level for data transfer should be selected.
Transfer format is defined as 1 start bit + 8 bits of data + 1 stop
bit by the rate/mode control register.
Signals CTS and RTS of the
console typewriter are controlled through bits 0 and 1 of port 5.
10.1.3
Peripheral Devices
Console Typewriter:
10.1.4
Sends/Receives data to/from the microcomputer.
Circuit Diagram
Asynchronous SCI circuit is shown in figure 10-1.
+5V
4
5
33
7
8
22pF
F"-~
22pF
M C U
HD6301YO
(HD6303Y)
MPo
MPI
~
STBY
17
NMI
Pso
XTAL
Console typewriter
HD75188
):)-_ _ _-\ CTS
HD75189
18
PSI 1=-------0;:;..1-------; RTS
27k
EXTAL
+5V
HD 75188
Pa/Tx
13
b------iRx
HD75189
6
RES
12
P2S/ RX.~--------~~II___--------~Tx
SG
1tLF
42
Vss
Vss
Figure 10-1.
-12V
Asynchronous SCI Circuit
~HITACHI
982
10.1.5
Pin Functions
Pin functions at the interface between the HD6301YO and the console
typewriter are shown in Table 10-1.
Table 10-1.
Pin Functions
Pin Name
(Console
Typewriter)
Pin Name
(HD6301YO)
Input/
Output
Active Level
(High or Low)
Pso
Output
Low
Outputs sending data CTS
request signal to
the console typewriter.
Input
Low
Inputs sending data
request signal from
the console typewriter.
10.1.6
Function
Program
Label
PsDTR
RTS
Input
Receives serial data Tx
from the console
typewriter.
Output -
Sends serial data
back to the console
typewriter.
Rx
Hardware Operation
The timing chart for sending/receiving data and control signals are
shown in figure 10-2.
This application example generates the timing
by software.
HD6 8 0 1 YO O)~=F-4S
POI(CTS)
Sending (
data
_ _-+.,
Tx
Start bit
I
Stop bit
Receiving
data
Rx
Start bit
Figure 10-2.
Timing Chart for Sending/Receiving Data
~HITACHI
983
10.2
SOFTWARE DESCRIPTION
10.2.1
Program Module Configuration
The program module configuration for sending/receiving data to/from
the console typewriter is shown in figure 10-3.
SCMN
MAIN
PROGRAM
I
SCI I N
RECEIVE
SCIOUT
~
12.
DATA
Figure 10-3.
10.2.2
~
SEND DATA·
J
TPR
CONVERT
~
ASCII
LOWERCASE INTO
UPPERCASE
Program Module Configuration
Program Module Functions
Program module functions are summarized in table 10-2.
Table 10-2.
Program Module Functions
No.
Program Module Name
Label
Function
0
MAIN PROGRAM
SCMN
Send/Receive data to/from the console
typewriter using asynchronous SCI.
1
RECEIVE DATA
SCIIN
Receive data from the console typewriter.
2
SEND DATA
SCIOUT
Send data back to the console typewriter.
3
CONVERT ASCII
IDWERCASE INTO
UPPERCASE
TPR
Converts ASCII lowercase into uppercase.
Refer to TPR in HD630l/HD6303 FAMILY
APPLICATION NOTES (SOFTWARE) for details.
~HITACHI
984
10.2.3
Program Module Process Flow (Main Program)
The flowchart in figure 10-4 shows the procedure for sending/receiving
data to/from the console typewriter, using the program module in figure
10-3.
If ASCII lowercase characters are received, the main program
converts them into uppercase.
Main Program
---{ Initialize stack pointer.
L..-_ _, - - _ - - '
---[Clear RAM.
L..-_ _, - - _ - - '
-.l----[
Set signal RTS to High.
L-_ _-,-_ _
- - - [Initialize port 5.
1..---,-----'
Initialize rate/mode control register to
input the SCI clock from timer 2 and to
[
---- define transfer format as 1 start bit +8
~---,---~
bit data.
___ [Initialize TX/RX control status register
2 to no parity bit and 1 stop bit.
,...-_---J
L..-_ _
Initialize timer control/status register
- - - [ 3 to start E clock input into timer 2 up
counter.
Initialize Tx/Rx control status register
- - - [ 1 to enable receiving interrupts and
start receiving.
,...-_---J
L..-_ _
___ [Define time constant register as 4800
BPS.
L-_ _.....,._ _ _...1 - - -
I
Gbable interrupts.
Figure 10-4.
Program Module Flowchart
~HITACHI
985
signal RTS to Low.
Test if data is received from the console
- - - [ typewriter.
receiving data into AOCA.
indicating data is
L-_ _...,.._ _---l---[set
signal
RTS to Low.
Execute TPR to convert ASCII lowercase
_ __ [ into uppercase. Refer to TPR in
HD630l/HD6303 FAMILY APPLICATION NOTES
(SOFTWARE) for details.
--LJ---[
u..__-.-__
selIN
Send data back to the console typewriter.
SCI Interrupt Routine
DATA ___ [Receive data from the console typewriter
using SCI interrupts.
L...._ _....-_--'
Figure 10-4.
Program Module Flowchart (Cont.)
~HITACHI
986
10.3
PROGRAM MODULE DESCRIPTION
Program Module Name: RECEIVE DATA
MCU/MPU:HD6301YO/
HD6303Y
Label: SCIIN
Function:
Receives serial data from the console typewriter.
Arguments:
Contents
Entry
--
Changes in CPU
Storage
Location
No. of
Bytes
---
--
ACCD
ACCA ACCB
x
•
IX
Receiving
complete
flag
SCIDAT
(RAM)
1
INFLG
(RAM)
1
•
x
t
:
ROM (Bytes) : 22
RAM (Bytes) : 2
Stack (Bytes) : 0
No • of cycles: 41
•
ReData
turns received
Specifications:
Registers and Flags:
Reentrant: No
C
V
•
x
Z
x
N
x
I
H
•
•
Relocatable: No
Interrupt OK?: Yes
Not affected
Undefined
Result
Description:
1.
Function Details
a.
Argument details
SCIDAT(RAM): Holds data received.
INFLG(RAM)
Used as flag indicating whether or not receiving is
completed.
Table 10-3 shows flag functions.
b.
I
Example of SCIIN execution is shown in figure 10-5. If bit 0 of portS
(signal RTS) is set to Low, data sent from the console typewriter is
stored in SCIDAT(RAM).
Specifications Notes:
"No. of cycles" in "Specifications" indicates the number of cycles required to
receive data.
~HITACHI
987
Program Module Name: RECEIVE DATA
M_C_U_/_M_P_U_:__
HD_6_3_0_l_Y_0_/
HD6303Y ____
L_
~IL_L_a_b_e_l_:_sc
.
__I_I_N______
Description:
Table 10-3.
Flag Functions
Label
bit 0
Function
INFLG
o
Indicates data is not received.
1
Indicates data is received.
(j) Input
::tn. . . . '--'----'mJt
1LtB
MSB
Start bit
®
SCIDAT (RAM) b7 SCIDAT bO
(Data received
6 : 1
( $61»
INFLG
INFLG (RAM)
(Receiving
o :
complete flag
($01»
ReSUlt!
Figure 10-5.
c.
2.
f
Stop bit
Example of SCIIN Execution
SCIIN calls neither the program modules nor subroutines.
User Notes
The following procedure must be performed before SCI IN execution.
3.
a.
Select DDR of bit 0 of port 5 as output.
b.
Initialize SCI since asynchronous SCI is used.
c.
Enable interrupts for SCI interrupts.
RAM Allocation
Label
RAM
b7
SCIDAT
INFLG
B
Description
bO
} Data sent from the console typewriter.
lUsed as flag indicating whether or not data
f is received.
~HITACHI
988
~
Program Module Name: RECEIVE DATA
HD6303Y _ _.-.
M_C_U_I_M_P_U_:_H_D6_3_0_1_Y_0_/
_
lL_a_b_e_l_:_S_C_I_IN
_ _ _---'
L..
Description:
4.
Sample Application
~
CLRA
STAA
LDAA
STAA
STAA
LDAA
STAA
CLRA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
BCLR
BTST
BEQ
BCLR
LDAA
BCLR
SCMNl
5.
INFLG
#$01
P5DTR
P5DDR
#$24
RMCR
TRCSR2
#$14
TCSR3
#$18
TRCSRl
#$07
TCONR
O,P5DTR
O,INFLG
SCMNl
O,INFLG
SCIDAT
O,PSDTR
}
Clear RAM.
}
Set signal RTS to High.
t
Initialize rate/mode control register.
}
}
}
}
}
Initialize Tx/Rx control register 2.
Initialize timer control/status
register 3.
Initialize Tx/Rx control status
register l.
Initialize time constant register to
4800 BPS.
Set signal RTS to Low.
Test if receiving data is completed.
Clear receiving complete flag.
Load data received.
Set signal RTS to Low.
Hardware Operation
a.
If data is received in receive data register, an SCI interrupt is
generated and SCIIN is executed.
b.
Signal RTS is set to high to disable the console typewriter from sending
data.
c.
Tx/Rx control status register detects whether or not overrun/framing
error is generated.
i.
ii.
I
If overrun/framing error is generated, receive data register is
dummy read and error indicator is cleared.
If error is not generated, received data is stored in SCIDAT(RAM).
~HITACHI
989
Program Module Name: RECEIVE DATA
I
MCU/MPU: HD630lYO/
Lab,l, SCIIN
HD6303Y
Flowchart:
•
L -____
~----~---[ Clear
SCI interrupt request flag.
error is
received data into entry argument.
' - -____...._ _-..J - - - [
Set receiving complete flag.
SCIINl
(RDR)"':'ACCA
___ [ Dummy read receive data register and clear
flag indicating overrun/framing error.
~HITACHI
990
MCU/MPU:
Program Module Name: SEND DATA
Label: SCIOUT
HD6301YO/
HD6303Y
Function:
Sends data, loaded into ACCA, back to the console typewriter.
Arguments:
Storage
Location
Contents
Entry
Changes in CPU
Data to be ACCA
sent
No. of
Bytes
Specifications:
Registers and Flags:
ACCD
ACCA ACCB
•
I
•
ROM (Bytes): 16
RAM (Bytes): 0
Stack (Bytes): 0
IX
•
No. of cycles: 28
Reentrant: No
v
C
•
Returns
•
x
:
x
z
N
x
x
I
H
•
•
Relocatable: No
Interrupt OK?: Yes
Not affected
Undefined
Resul t
Description:
1.
Function Details
a.
Argument details
ACCA: Holds data to be sent back to the console typewriter.
b.
Example of SCIOUT execution is shown in figure 10-6.
If entry argument is as shown in part
of figure 10-6, data is
sent to the console typewriter as shown in part Q) of figure 10-6.
c.
SCIOUT calls neither the program modules nor subroutines.
I
CD
Specifications Notes:
N/A
~HITACHI
991
Program Module Name: SEND DATA
LM_C_U_/_M_P_U_:
__
HD_6_3_0_1_Y_0_/____
_
HD6303Y
~lL_a_b_e_l_:_._SC
.
__IO_UT
______
Description:
fi'
Entry
{ ACCA
~
argument
b7 ACCA bO
I 6 3
I..__~__~
r
@ Result {
r r'T' ,-.-rT'-'-.-r r- rr T'-
: ! i :! !: : : I : : : : ! : : i
P51
pZ-I./Tx
Start bit
Figure 10-6.
2.
MSB
Stop bit
Example of SCIOUT Execution
User Notes
Initialize SCI for asynchronous SCI.
3.
RAM Allocation
RAM is not used during SCIOUT execution.
4.
Sample Application
LDAA
STAA
#$24
RMCR
} -----
}----- Initialize Tx/Rx control status register 2.
} ----- Initialize timer control/status register 3.
CLRA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
II JSR
TRCSR2
#$14
TCSR3
#$18
TRCSRl
#$07
TCONR
#$30
SCIOUT
Initialize rate/mode control register.
} -----
Initialize Tx/Rx control status register 2.
Initialize time constant register and define
}----- baud
rate to 4800 BPS.
Load data to be sent.
II
Execute SCIOUT.
$
992
HITACHI
~
Program Module Name: SEND DATA
MCU/MPU: BD6301YO/
HD6303Y
Label:
--
SCIOUT
Description:
5.
Basic Operation
a.
Whether or not there is a sending data request from the console typewriter
is determined by signal CTS.
b.
If signal CTS is Low, data can be sent to the console typewriter.
If signal CTS is High, wait until signal CTS is Low.
c.
Whether or not transmit data register is empty is tested by transmit
data register empty bit (bit 5) of TX/Rx control status register 1.
d.
Transmit enable bit (bit 1) of Tx/Rx control status register 1 is set
to "1" and data sending is started.
e.
Data to be sent is stored in transmit data register.
I
~HITACHI
993
Program Module Name: SEND DATA
MCU/MPU: HD630lYO/
HD6303Y
[~
Flowchart:
transmit data register is
1.-_ _,..-_---1
~--r-----'
- - - [start sending data.
___ [Load data to be sent into transmit
data register.
~HITACHI
994
SCIOUT
10.4
SUBROUTINE DESCRIPTION
This application example calls no subroutines.
10.5
PROGRAM LISTING
00001
00002
00003
00004A
00005
00006A
00007A
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026A
00027
00028A
00029A
00030A
00031A
00032A
00033A
00034A
0003SA
00036A
00037A
00038A
00039A
00040A
00041A
00042A
00043A
00044A
0004SA
00046A
00047A
00048A
00049A
OOOSOA
OOOSlA
000S2A
000S3A
00054
00055
00056
00057
*
************ RAM ALLOCATION *******************
*
0040
0040
0041
0001
0001
$40
ORG
A *INFLG
Receiving compLete fLag
Data received
RMB
A SCIDAT RMB
*
SYMBOL DEFINITIONS ****************
************
0010
0011
0012
0013
0015
001B
OOlC
001E
0020
A
A
A
A
A
A
A
A
A
*RMCR
TRCSRl
RDR
TOR
PSDTR
TCSR3
TCONR
TRCSR2
PSDDR
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$10
$11
$12
$13
$15
$lB
$lC
$lE
$20
RATE/MODE CRTL REG
Tx/Rx CRTL REG 1
RECEIVE DATA REG
TRANSMIT DATA REG
PORTS DATA REG
TIMER CRTL REG 3
TIME CONSTANT REG
Tx/Rx CRTL REG 2
PORTS DDR
*********************************************
**
MAIN PROGAM : SCMN
**
*
*
*********************************************
*
*
COOO
COOO
C003
C004
C006
C008
CODA
COOC
CODE
COlO
COlI
C013
C01S
C017
C019
C01B
COlD
COIF
C020
C023
C026
C028
C02A
C02D
C030
C033
C036
8E
4F
97
86
97
97
86
97
4F
97
86
97
86
97
86
97
OE
71
7B
27
96
71
71
BD
BD
20
ORG
$COOO
1:I$13F
A
LDS
CLRA
STAA
LOAA
STAA
STAA
LDAA
STAA
CLRA
STAA
LDAA
STAA
LDAA
STAA
LDAA
A
STAA
013F
A SCMN
40
01
IS
20
24
10
A
A
IE
14
1B
18
11
07
1C
A
A
A
A
A
A
A
A
A
FE IS
SCMNI
01 40
FB C023
41
A
FE 40
FE 15
C038 A
COS9 A
EB C023
INFLG
1:1$01
PSDTR
PSDDR
1:1$24
RMCR
TRCSR2
1:1$14
TCSR3
1:1$18
TRCSR1
1:107
TCONR
CLI
BCLR
BTST
BEQ
LDAA
BCLR
BCLR
JSR
JSR
BRA
O.PSDTR
O.INFLG
SCMNI
SCIDAT
O. INFLG
O.PSDTR
TPR
serOUT
SCMNI
InitiaLize stack pointer
CLear RAM
InitiaLize port 5
InitiaLize RMCR
InitiaLize TRCSR2
InitiaLize TCSR3
InitiaLize TRCSRI
Set 4BOOBPS
EnabLe interrupts
Set RTS=O
Test if data is received
I
Load SCI data
CLear SCI flag
Set RTS=O
Convert Lowercase into uppercase
Send data
*********************************************
**
*
NAME : TPR (CONVERT B BIT BINARY INTO
ASCII)
•
*
*
*
HITACHI
995
00058
00059
00060
00061
00062
00063
00064
00065
00066A
00067A
00068A
00069A
00070A
00071A
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084A
00085A
00086A
00087A
OOOSSA
00089A
00090A
00091A
00092A
00093A
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104A
00105A
00106A
00107A
00108A
00109A
00l10A
00111
00112
00113
00114
*
**
*
*********************************************
*
C038
C03A
C03C
C03E
C040
C042
81
25
81
22
84
39
61
A
06 C042
7A
A
02 C042
DF
A
***********************************************
*TPR
CMPA
ACCA-'a'
tI'a
BCS
TPRI
Branch if ACCA<'a'
CMPA
ACCA-'z'
tI'z
BHI
TPRI
Branch if ACCA)'z'
ANDA
tI$DF
Convert Lowercase into uppercase
TPRI
RTS
********************************************
*
*
*
*
*
RETURNS : SCIDAT (DATA RECEIVED)
*
INFLG (RECEIVING COMPLETE*
FLAG)
*
*
*
NAME : SCIIN (RECEIVE DATA)
*
*
**********************************************
**
**
ENTRY
NOTHING
C043
C045
C048
C04B
C04D
C04F
C051
C054
C056
C058
96
72
7B
26
96
97
72
20
96
38
11
01
40
09
12
41
01
02
12
********************************************
TRCSRI
CLear interrupt request flag
A SCIIN LDAA
15
BSET
0.P5DTR Set RTS='l'
BTST
6.TRCSRl ORFE bit='O' or '1'
11
C056
BNE
SCIINI
Branch if ORFE='l'
A
LDAA
RDR
Set receiving compLete flag
A
STAA
SCIDAT
BSET
O.INFLG Set SCI fLag
40
C058
BRA
SCIIN2
A SCIIN1 LDAA
RDR
CLear error fLag
SCIIN2 RTI
*****************************************
*
*
NAME : SCIOUT (SEND DATA)
*
**********************~(*******************
**
ENTRY : ACCA (DATA TO BE SENT) *
*
*
*
C059
C05C
C05E
C061
C063
C066
C068
7B
26
7B
27
72
97
39
02
FB
20
FB
02
13
RETURNS : NOTHING
•
*
*
*:k****:~:k:k:~*:~**;k******:k*******************
SCIOUT BTST
15
C059
BNE
SCIOTI BTST
11
BEQ
C05E
BSET
11
A
STAA
RTS
1.P5DTR
serOUT
5.TRCSRI
SCIOll
1.TRCSRl
TDR
Loop untiL CTS=O
Loop untiL TDRE=O
Start sending data
Load data to be sent
************************************~:****
*
*
*
VECTOR ADDRESSES
~HITACHI
996
**
*
ENTRY: ACCA (8 BIT BINARY)
RETURNS: ACCA (8 BIT BINARY)
*
*
*
00115
00116
001l7A
00118
001l9A
00120A
00121A
00122A
00123A
00124A
0012SA
00126A
00127A
00128A
00129A
00130
00131
FFEA
FFEA
FFEC
FFEE
FFFO
FFF2
FFF4
FFF6
FFF8
FFFA
FFFC
FFFE
COOO
COOO
COOO
C043
COOO
COOO
COOO
cooe
COOO
cooo
COOO
A
A
A
A
A
A
*****************************************
*
$FFEA
ORG
*
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
A
A
A
A
A
*
SCMN
SCMN
SCMN
SCIIN
SCMN
SCMN
SCMN
SCMN
SCMN
SCMN
SCMN
IRQ2
CMI
TRAP
SID
TO!
OCI
rCI
IRQl/ISF
SWI
NMI
RES
ENO
I
~HITACHI
997
SECTION 11.
11.1
LIQUID CRYSTAL DRIVED (HD6ll00A) CONTROL
HARDWARE DESCRIPTION
11.1.1
Function
Controls the HD6ll00A liquid crystal driver and displays "9876543210"
on an LCD display.
11.1.2
Microcomputer Operation
The HD630lYO sends display data and control signals to the HD6ll00A
to display graphics on the LCD.
Signals M and CLI of the HD6ll00A and
signal COMMON of the liquid crystal are controlled through port 2.
In addition, the HD6ll00A control signals (signals CL2, DL) are
controlled using the clock synchronous SCI (serial communication
interface) of port 2 to enable sending of display data to the HD6ll00A.
11.1.3
Peripheral Devices
HD6ll00A LCD Driver:
Performs static drive on an 8-segment x 10-digit
LCD.
11.1.4
Circuit Diagram
LCD driver (HD6ll00A) control circuit is shown in figure 11-1.
MCV
+sv
HD6301YO
(HD6308Y)
881~11I401481
VZL VZR V,LlVSK
!
821501851411
V1L VIR V4L V4R
VEE
~
Vee 1415
~r.===C=O=MM==O=N============~
mID
~ ~HL ~l~~~~er Y/I---ao----'-'\ I CI CI 000 C10DO D I
.!!. FCS
Y
U U IJ U U U U U U U
B•
p..
~
..~
M
CL.
P2I I"::-g----I
p •• 1-:-:-_-;-;-;::-;;--:-;-;,.,....,,....,..._-=8.:...J1!
I'
~,L
P •• /SCLK~1~1_~H~D~1_+~H~C~0_+~~~_ _~
P.~/Txfm~
'~LLI
-
Liquid crystal
(8-segments x lO-digits)
______v_ _ _ _~
Figure 11-1.
LCD Driver (HD6ll00A) Control Circuit
~HITACHI
998
-V
11.1.5
Pin Functions
Pin functions at the interface between the HD6301YO and the HD61100A
are shown in table 11-1.
Table 11-1.
Pin Functions
Pin Name
(HD61100A
LCD)
Program
Label
Outputs alternate
signal for LCD
driving output.
M
P2DTR
Output
Resets counter,
outputs synchronous
signal of latch
clock for display
data.
CLl
PZ3
Output
Outputs common
signal to LCD.
COMMON
Pzz/SCLK
Output
Outputs shift clock
for display data.
CL2
P2'>/'l'x
Output
Inputs display data.
DL
Pin Name
(HD6301YO)
Input/
Output
PZl
Output
Pzo
11.1.6
Active Level
(High or Low)
Function
Hardware Operation
Timing chart of the HD6301YO, LCD, and the HD61100A is shown in figure
11-2.
LCD and HD61100A
pin names
COMMO~L___________________________________
Controlled
by I/O ports
----------,L
M
CLI
Controlled {
by clock
synchronous
SCI
______---'1
JlL....-_________________
__________IL
--------~
CL ,
--------~
DL
1..J1..J'~~o\..uJt\..P..JU\..t--8JOl..Jb\..iJt\..SJ\..(J1'-OJ\..dJi\..gJi'-t-S) -- --- --
Figure 11-2.
.1
Timing Chart of HD6301YO, LCD, and HD61100A
@>HITACHI
999
I
11.2
SOFTWARE DESCRIPTION
11.2.1
Program Module Configuration
The program module configuration for character display on LCD is
shown in figure 11-3.
H61MN
MAIN
PROGRAM
H 61 DSP
I
I
MOVE
II
11.2.2
I
l!.
MOVE
DISPLAY DATA
DISPLAY
CHARACTER
Figure 11-3..
~
Program Module Configuration
Program Module Functions
Program module functions are summarized in table 11-2.
Table 11-2.
Program Module Functions
No.
Program Module Name
Label
Function
o
MAIN PROGRAM
H61MN
Initializes control registers and data
addresses used for the interface between
the HD6301YO and the HD6ll00A.
1
DISPLAY CHARACTER
H61DSP
Performs static drive of LCD using the
HD6ll00A and displays numerals.
2
MOVE DISPLAY DATA
MOVE
Moves display data in data table to
display RAM. Refer to MOVE in HD6301/
HD6303 FAMILY APPLICATION NOTES
(SOFTWARE) for details.
~HITACHI
1000
11.2.3
Program Module Process Flow (Main Program)
The flowchart in figure 11-4 shows the procedure for displaying numerals
on an LCD as performed by the program module in figure 11-3.
Main Program
___[ Initialize stock pointer.
___ [ Set signals CLI and M to Low and signal
COMMON to High.
---[ Select port 2 as output.
Initialize rate/mode control register to 8-bit
--- data format, clock synchronous SCI mode,
[ internal clock source, bit 2 of port 2 clock
output and baud rate 16~s/bit.
Initialize transmit/receive c9ntrol status
- - { register I to enable data transfer and enable
interrupts.
___ [Initialize counter indicating the number of
interrupts.
---[Enable interrupts.
Load starting address of display data,
- - - [ contained in data table, into entry
argument of MOVE.
___[ Load starting address of display RAM into
entry argument of MOVE.
___[ Load number of bytes to be moved into entry
argument of MOVE.
Execute MOVE to move display data to display
--_ [ RAM. Refer to MOVE in HD630l/HD6303 FAMILY
APPLICATION NOTES (SOFTWARE) for details.
I
TDRE Interrupt Routine
L..;==:;;:::=::""....I- - { Execute H6lDSP to display numerals on LCD.
Figure 11-4.
Program Module Flowchart
~HITACHI
1001
g8l55Y32
Figure 11-5.
Example of H61MN Execution
@HITACHI
1002
In
IU
11.3
PROGRAM MODULE DESCRIPTION
Program Module Name: DISPLAY
CHARACTER
MCU/MPU:
HD6301YO/
HD6303Y
Label: H61DSP
Function:
Sends display data to the HD61100A and displays characters on an LCD.
Arguments:
contents
Entry
Display
data
Changes in CPU
Storage
Location
No. of
Bytes
DDATA
(RAM)
10
Specifica tions:
Registers and Flags:
ACCD
ACCA ACCB
x
•
ROM (Bytes) : 41
RAM
(Bytes) : 12
Stack (Bytes) : 0
IX
No. of cycles: 61
x
Reentrant: No
C
•
Returns
Z
x
I
x
•
x
:
V
x
Relocatable: No
Interrupt OK? : No
N
x
H
•
Not affected
Undefined
Result
Description:
1.
Function Details
a.
Argument details
I
DDATA(RAM): Holds 10 bytes of display data.
b.
Example of H61DSP execution is shown in figure 11-6.
If entry
argument is as shown in part 1 of figure 11-6, characters are
displayed as shown in part 2 of figure 11-6.
c.
H61DSP calls neither the program modules nor subroutines.
Specifications Notes:
N/A
~HITACHI
1003
Program Module Name: DISPLAY
CHARACTER
MCU/MPU: HD6301YO/
HD6303Y
Label: H61DSP
Description:
Address Space
DDATA
(RAM)
Q)
Entry
argtmlent
Display data
(9,B,7,6,5,4,
3,2,1,0)
LCD
'2'
\Y
Result{
Figure 11-6.
2.
~~
$77
$14
$B3
$B6
$D4
$E6
$E7
$74
$F7
$F6
~
--
OD'lCOSU=O
In
...JU I I
I _1'- I U
Example of H61DSP Execution
User Notes
The following procedure must be performed before H61DSP execution.
3.
a.
Select data direction register (DDR) of port 2 as output.
b.
Initialize clock synchronous SCI to send display data.
e.
Clear bit I to enable TORE interrupts.
d.
Store display data in TOR to generate TORE interrupts.
RAM Allocation
Label
Description
b7
CNTR
DDATA
bO
Used as a pointer to display RAM and as a
counter indicating number of interrupts.
lI~
--
10°
10 1
10 2
10 3
10"
10 5
10 6
10 7
10 8
10 9
digit
digit
digit _
digit _
digit
digit
digit
digit.
digit.
digit
Display data
$
1004
..
.
HITACHI
Program Module Name: DISPLAY
CHARACTER
MCU/MPU: HD6301YO/
HD6303Y
Label:
--
H61DSP
Description:
4.
Sample Application
LDAA
STAA
LDAA
STAA
IDAA
STAA
IDAA
STAA
IDX
STX
CLI
IDX
IDD
STD
IDAB
JSR
5.
#$08
P2DTR
#$FF
P2DDR
#$11
RMCR
#$06
TRCSRl
#$0001
CNTR
}----}----}---------
#$F100
#DDATA
DEA
#$OA
MOVE
}-----
Initialize port 2.
Initialize synchronous SCI.
Initialize pointer to display RAM and counter
for number of interrupts.
Enable interrupts.
Execute MOVE to load display data into
entry argument of H61DSP.
(Refer to MOVE in HD6301/HD6303 FAMILY
APPLICATION NOTES (SOFTWARE) for details.)
Basic Operation
a.
10 bytes of display data are sent to the HD61100A to display numerals on
an 8 segments x 10 digits LCD. Shift clock and data signal are controlled
by the clock synchronous SCI of the HD6301YO.
b.
Display data is stored in display RAM before execution.
interrupt executes display of 1 byte of data.
c.
Pointer to display RAM and counter for number of interrupts are
decremented every interrupt. CNTR(RAM) is reinitialized each time 10
interrupts are executed.
d.
The first enabling interrupts are performed by the main program.
From then on, TDRE interrupts are generated automatically each time
display data are outputted.
Each TDRE
~HITACHa
1005
MCU/MPU: HD6301YO/
HD6303Y
Program Module Name: DISPLAY
CHARACTER
~ H61DSP
Flowchart:
__ {Decrement pointer to display RAM and
counter for number of interrupts.
- --[ Load pointer to display RAM.
__ { Test if interrupt has been executed 10
times.
,
- - { Reini tialize pointer to display RAM.
__ {Reinitialize counter for number of
interrupts.
1-+1, P2DTR
__ { Set ,ignal
eL,
to High.
--{ Test if signal M is High.
__ {
Set signal CLl to Low, signal M to Low,
and signal COMMON to High.
__ {
Set signal CLl to Low, signal M to High,
and signal COMMON to Low.
H61DP1
--{ Load TRCSRl to clear TDRE flag.
--{ Store display data in TDR.
~HITACHI
1006
11.4
SUBROUTINE DESCRIPTION
This application example calls no subroutines.
11.5
PROGRAM LISTING
00001
00002
00003
00004
00005A
00006
00007A
00008A
00009A
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024A
00025
00026A
00027A
00028A
00029A
00030A
00031A
00032A
00033A
00034A
00035A
00036A
00037A
00038A
00039A
00040A
00041A
00042A
00043A
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054A
00055A
00056A
00057A
*
RAM ALLOCATION
*****************
****************
*
*
0040
0040
004A
004C
ORG
$40
*
RMB
OOOA A DDATA
10
0002
0002
2
2
A CNTR
A DEA
RMB
RMB
*
***************
0003
0001
0010
0011
0013
DispLay data
Counter for dispLay data
Destination address
SYMBOL DEFINITIONS
**************
A*
P2DTR
A
A
A
A
$03
Port 2 data register
EQU
Port 2 data direction register
$01
P2DDR EQU
Rate/mode controL register
$10
RMCR
EQU
$11
Tx/Rx controL status register!
TRCSRI EQU
Transmit data register
$13
TOR
EQU
**************************************************
*
MAIN PROGRAM : H61MN
>I<
>I<
>I<
>I<
>I<
***>1<**>1<*>1<***************>1<****>1<*************>1<**>1<**>1<
*
ORG
*
COOO 8E 013F A H61MN LDS
COOO
C003
COOS
C007
C009
COOB
COOD
COOF
COIl
C013
C016
C018
C019
COIC
COIF
C021
C023
C026
86
97
86
97
86
97
86
97
CE
DF
OE
CE
CC
DD
C6
BD
20
08
03
FF
01
11
10
06
11
0001
4A
A
A
A
A
A
A
A
A
A
A
F100 A
0040 A
4C
A
OA
A
C04D A
FE C026
$COOO
InitiaLize stack pointer
1oI$13F
Set CL1=0.M=0.COMMON=1
LDAA
ta08
STAA
P2DTR
IoI$FF
SeLect port 2 as output
LDAA
STAA
P2DDR
101$11
InitiaLize RMCR
LDAA
RMCR
STAA
InitiaLize TRCSR1
101$06
LDAA
STAA
TRCSR1
InitiaLize counter
101$0001
LDX
STX
CNTR
EnabLe interrupts
CLI
Load source address
IoI$F100
LDX
Load destination address
LDD
IoIDDATA
[)E~)
STO
InItiaLize transfer counter
H$OA
LDAB
Move data tabLe to dispLay RAM
JSR
MOVE
End of pr'ogram
PEND
PEND
BRA
**************************************************
*
>I<
NAME : H61DSP (DISPLAY CHRACTER)
>I<
I
*
*
>I<
*
ENTRY : DDATA (DISPLAY DATA)
*
*
RETURNS
:
NOTHING
*
*
*
*
************************************>1<*********>1<***
>I<
**************************************************
C028
C02B
C02D
C02F
7A
DE
26
CE
004B A H61DSP DEC
LOX
4A
A
BNE
11 C040
LDX
OOOA A
CNTR+1
CNTR
H61DPI
IoI$OOOA
Decrement counter
Test it CNTR=O ?
Branch it not CNTR=O
ReinitiaLize counter
@HITACHI
1007
00058A
00059A
00060A
00061A
00062A
00063A
00064A
00065A
00066A
00067A
00068A
00069A
00070A
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083A
00084A
0008SA
00086A
00087A
00088A
00089A
00090A
0009 H·'
00092A
00093A
00094
00095
00096
00097
00098
00099
OOlOOA
00101
00102A
00103A
00104
C032
C034
C037
C03A
C03C
C03E
C040
C042
C044
C046
C047
C049
C04B
OF
72
7B
26
86
97
96
A6
97
3B
86
97
20
C04D
C04F
COSO
C051
C053
C055
C056
C058
C059
COSA
C05C
A6
08
3C
DE
A7
08
OF
38
SA
26
39
FlOO
FlOO
F105
*
*
001~
00106
00107
00108
00109
OOllOA
00111
00112A
00113A
00114A
4A
A
STX
CNTR
BSET
1, P2DTR Set CL1=l
02 03
2,P2DTR Branch If M=l
BTST
04 03
H6lDP2
Branch to H61DP2 If M=l
OB C047
BNE
tjS02
Set CL1=0.M=1.COMMON=Q
02
A
LDAA
03
A
STAA
P2DTR
Clear' TORE
TRCSRI
11
A H61DPl LDAA
DDATA-l,X Store display data In TOR
3F
A
LOAA
13
A
STAA
TOR
RTI
tjS08
Set CL1=0,M=O,COMMON=1
08
A H61DP2 LDAA
03
A
STAA
P2DTR
F3 C040
BRA
H61DP1
**************************************************
*
*
*
NAME : MOVE (MOVING MEMORY BLOCKS)
*
*
*
**************************************************
*
*
*
ENTRY
IX
(SOURCE ADDRESS)
*
*
DEA (DESTINATION ADDRESS)
*
*
ACCB (TRANSFER COUNTER)
*
*
RETURNS: NOTHING
*
*
*
**************************************************
00
A MOVE
LDAA
O,X
Load transfer data
INX
Increment source address
PSHX
Push sou,'ce addr'ess
4C
A
LOX
DEA
Load destination address
00
A
STAA
O,X
Store transfer data
INX
Increment destination address
4C
A
STX
DEA
Store destination address
PULX
Pull source address
DECB
Decr'ement tr'ansfer' counter'
Fl C04D
BNE
MOVE
Branch until transfer counter
RTS
************************************************
*
*
*
DATA TABLE
'"
*
*
*************************************"'**********
*
ORG
SFlOO
*
E7
A
FCB
SE7,$F7,S43,SF6,SE6 *Segment data
CS
A
FCB
SCS,$E3,$B3,$41,$77
****************************************"'*********
FFEA
FFEA
FFEC
FFEE
COOO
COOO
COOO
*
VECTOR ADDRESSES
*
*
*
**************************************************
"
ORG
SFFEA
*
A
FOB
H61MN
IRQ2
A
FOB
H61MN
CMI
A
FOB
H61MN
TRAP
~HITACHI
1008
0
OOllSA
001l6A
00ll7A
001l8A
001l9A
00120A
00121A
00122A
00123
00124
FFFO
FFF2
FFF4
FFF6
FFF8
FFFA
FFFC
FFFE
C02B
COOO
COCO
COOO
COOO
COOO
COOO
COCO
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
A
A
A
A
A
A
A
A
*
H6IDSP
H61MN
H61MN
H61MN
H61MN
H61MN
H61MN
H61MN
SID
TOI
OCI
ICI
IRQlIISF
SWI
NMI
RES
END
I
~HITACHI
1009
SECTION 12.
12.1
EXTERNAL EXPANSION
HARDWARE DESCRIPTION
12.1.1
Function
Receives data from the console typewriter, displays it on the H2S7l
liquid crystal module, and echoes the same data back to the console
typewriter.
12.1.2
Microcomputer Operation
The HD6301YO controls the HM6264 RAM, HN27C64 EPROM, HD63S0 ACIA and
HD6321 PIA using external expansion mode (mode 1 of this MCU).
In this
mode, PSO is employed as the IRQl pin to receive interrupts from the
ACIA.
The MCU converts ASCII lowercase, sent from the console type-
writer, into uppercase through software.
12.1.3
Peripheral Devices
HD63S0 ACIA:
Performs asynchronous SCI with the console typewriter,
controlling signals RTS and CTS at a baud rate of 4800.
HD6321 PIA:
Drives the liquid crystal module through ports A and B
after receiving control information from the HD6301YO.
HD74HC183 Address decoder:
Decodes address signals from the MCU for
control of the RAM, EPROM, PIA, and ACIA.
12.1.4
Circuit Diagram
External expansion circuit is shown in figure 12-1.
~HITACHI
1010
ROM
5
t1
2
~
Vee
~pp
LEv
PGM~
+5V
IS2~ 4?kD HD ?4HCI4
'l ~_ ~
~
6- RES
1:
B
~
(')
1:
35
2
~::~
~
.. MP,
22~TAL
~ ~EXTAL
1. I
Cl
22 F
5IP'
~
Vss
42
t-#--
gl
V
• A"
5 A,
~
16
cell
B
Y,
A
,10
4 G A Y'r-;;---
F Y,~
G;B
8 GND Y7
24!"
1--.12 II
r~ A,
or- -.A7
20
CEr.
OE
07~19.
tH-
0,
04~
0,
HD?4HC04
GND
0,
~15
HD?4HCOI
r.1
~ r<
I/O,~
i
l/O,~
..----:-::
I/O,ttf----.i
,-!1 GND l/01~11111
til----
~
TIT
'---
t-#-t-#-A, t1}-
HDHHCOI
~~g"16
~ r.'
0, f:-':'-.
01 ~
l/O.-H---,
1/07~
tlr---{'~
~I~S
Itt--
9 A,
A,
10 A,
OE:JZ
~A"
A,
O,~
A.
HA3
,t-±
-
WE 2'
r
HD?4HC04
A
vee
, STBY
4Iill-{z
3
Au 36
AI!
A"tE--
W
HD?4HCI 38 +5V
6'---
A" 34
"'.
As
+5V
33
~
4?kD
'J A,
' A7
CS 1
~AI2
I~
r21 All
"
25 AfJ
+5V
MCU
HD630lYO
(HD6303Y)
-20
~ CC~2
~ All
f. A"
~!Yt2 6~
+5V
HV~oRHN2'C6~,~;V
~
A3
A. 1---7::I-f,-
A,
AI
~o
23 _
~
.l6 (,S,
~ RS,
/ :35 HS
l.l Du I
32
D,
r.:50
58
57
D. I-';'-;;-'
D2
I'-fi
~
~
28 D4
D,
-H-
~
i'-,g D,
D,
D, -""---'
-¥.--
E
64
1)2
fjji D,
D, ~
D. ~
D,
D7
Liquid Crystal Module H2571
PIA
IID6.l21
S
rI
R/W 61
2.J E
~~ H/IV
HES
ss
if+5V
V c 22
20
c§,
24
CS I
Ir--;--a
: 2
~
II 8, DBo
I 9 DB,
PB z 13
10 DBz
PB,
PB.
PB,
PH,
PB,
14
15
II DB,
12 DB.
16
13 DB,
DBo
14 DB,
p~
PA,
PA,
HD
~ Vss
I
2
_i
!
L
22 D
21
0
V.
CC
12
6
t-..
....I
!VW
g'
;;:::~
5
18 D: RxDATA
:~ D,
15 D~
II D,
HD441 0 0
"
4
_ /
V
____________
RS
-.l
,-----,
HD75188
: ORxDATA;
I
I
IITS
I
.-----f-oSG
11r
I
HD?51891
ers
I
I
:
I
I
I
TXDA'rAj
L ____ J
HD?4HC04 lMO
HD"HCO~
9~
L~==================~1~4
~1"l3 CSz
E HxCIK
L___________
'-_____________--','li:HJW!!W~T:..X:.:C:.:IKJ
4
IIQ
o
UI52MHz
Of;J;2OpF
-'"
Figure 12-1.
----~-
External Expansion Circuit
I
I
I
Console Typewriter
20 1)1 TxDATA 24
19
;:::,
40
ACIA
liD 6350
I
......
40
):;
I RQ.f-l!--
I
--I
LCD
6 E
!
Vss~
4.'kD
Y:' "'80 ~I
11
V
PB 0 10
II
PB, 12
+5V
m'
10kD
,
I'
r"-
+5Vr--Lcn..:-i---- - - - - - - - - - - -
;J; 20pF
12.1.5
Memory Map
Memories and peripheral LSIs are allocated to external address space
using an address decoder (HD74HC138).
Address buses A13 and A14 are connected to pins A and B of the HD74HC138.
Address space
$8000~$FFFF
is divided into 8-byte units.
System Address
decoding is shown in Table 12-1.
Table 12-1.
System Address Decode
HD74HC138
Input
Output
Gl GzA G·2B
C
B
A
Address
space
Allocation
Yo Yl Y2 Yg Y" Ys Y6 Y7
A1S Al" Au
L
L
H
L
L
H H H H L
H
H H
$8000 ~ $9FFF
RAM
H L
L
H
L
H
H H H H H L
H H
$AOOO ~ $BFFF
PIA
H
L
L
H
H
L
H H H H H H L
H
$COOO ~ $DFFF
ACIA
H
L
L
H
H
H
H H H H H H H L
$EOOO ~ $FFFF
ROM
H
System memory map is shown in figure 12-2.
$0000
~
$OOIF
I/O Ports
TIMER
SCI
HD6301YO internal re gisters and internal
address space
Not Used
$004.0
)
$OOFF
RAM
(192 Byte)
Not Used
$8~00
$9FFF
O
$Ar
RAM
DDRA/PORTA $AnOO
CRA
$AOOI
DDRB/PORTB $A002
$A008
CRB
Not Used
(HM6264.)
PIA
(HD6821)
$BFFF
$BFFF
$Cooo
~
ACIA
(HD6850)
$E~OO
EPROM
CTRL/STS $COOO
TDR/RDR $COOl
$DFFF
Not Used
(HN2~C64.)
$OFFF
$FFFF
Figure 12-2.
System Memory Map
~HITACHI
1012
The relation between HD6301YO specified addresses and
selected PIA
Table 12-2.
re~isters
is shown in table 12-2.
HD6301YO addresses and Selected PIA Registers
Address
(HD6301YO)
Program
Label
$AOOO
DDRA
Selected PIA Register
Pin Name
(LCD-II·)
Note
Whpn bit 2. of
Data direction
register A
control register
A=O.
Peripheral interface
register A
$AOOl
CRA
Control register A
$A002
DDRB
Data direction
register B
In case of bit 2
of control
register B=O
PIRB
Peripheral interface
register B
In case of bit 2
of control
register B=l
CRB
Control register B
$A003
Bit O:signal E
Bit l:signal R/W
Bit 2:signal RS
In case of bit 2
of control
register A=l
PlRA
Note:
The timing chart between PIA and LCD-II is shown in figure 12-3.
CD:
Write timing
®:
Read timing
LCD-II Pin names
----..,.
RS. R/W ____J~+_-----------------J
E
I
DBo-DB.
(P IA--+ LCD- D'-!)_ _ _ _ _ _ _ _- . J lI----4,.J '-_ ___
DBo-DB.
( PIA+- LCD- D
•..L.._ _ _ _ _ _ _ _...J l\..____- J
Figure 12-3.
'-----
PIA--LCD-II Timing Chart
~HITACHI
1013
The relation between the address of the HD6301YO and the selected ACIA
register is shown in table 12-3.
Table 12-3.
Relation between the Address of the HD6301YO and the Selected
ACIA Register
Address
(HD6301YO)
Program Label
Selected ACIA Register
Note
$COOO
CR
Control register
In case of signal R/W=O
SR
Status register
In case of signal R!W=l
$COOl
TDR
Transmit data register
In case of signal R/W=O
RDR
Receive data register
In case of signal R/W=l
~HITACHI
1014
12.1.6
Hardware Operation
The interface timing chart between the HD6301YO and memories (HN27C64,
HM6264) is shown in figure 12-4.
E
HDGSOIYO
-,
\
ADDR ESS
I
J
tAO
\
Decoder delay time
\
teo
HN27CG40
l.
t.ce
I Dsa
'Og
~
~
DATA
(OUT)
Decoder delay time
I-
Dsa
"'01
IIR
10E
\
DE
HM82640
Data {
read
t ..
DATA
~
(OUT)
IwP
lAS
II
WE
D,lta
write{
I DW
1
DATA
(IN)
\
tAD
HD6301YO
tDBR
tn
tow
HN27C64
t ••
too
tACO
tOB
tAA
teo 1
HM6264
Figure 12-4.
100
I.
tAB
twp
tDW
tDB
too
Address delay time
Data set-up time
Data hold time
Data delay time
output CE delay time
Output OE delay time
Access time
Data output hold time
Address access time
Chip select access time
Address set-up time
write pulse width
Input data set time
Input data hold time
Output enable access time
I
Interface Timing Chart between HD6301YO and Memories
~HITACHI
1015
12.2
SOFTWARE DESCRIPTION
12.2.1
Program Module Configuration
The program module configuration for receiving key data from the console
typewriter and displaying data on both the console typewriter and H2571
is shown in figure 12-5.
EXPMN
l£.
MAIN
PROGRAM
EXPINT
I
EXPDSpl
EXPOUT
~
12..
Figure 12-5.
12.2.2
~
DISPLAY
CHARACTERS
INITIALIZE
LCD-II
EXPINP
SEND DATA
I
I
~
RECEIVE
DATA
TPR
CONVERT
ASCII
LOWERCASE
IN'IO
UPPERCASE
U.
Program Module Configuration
Program Module Functions
Program module functions are summarized in table 12-4.
Table 12-4.
Program Module Functions
No.
Program Module Name
Label
Functions
o
MAIN PROGRAM
EXPMN
Displays key data, received from the
console typewriter, on both the H2571
and console typewriter.
1
INITIALIZE LCD-II
EXPINT
Initializes LCD-II contained in the
H257l.
2
DISPLAY CHARACTERS
EXPDSP
Displays characters on the H2571.
3
SEND DATA
EXPOUT
Sends display data to the console typewriter.
4
RECEIVE DATA
EXPINT
Receives display data from the console
typewriter.
5
CONVERT ASCII
IDWERCASE IN'IO
UPPERCASE
TPR
Converts ASCII lowercase into uppercase.
Refer to TPR in HD6301/HD6303 FAMILY
APPLICATION NOTES (SOFTWARE).
~HITACHI
1016
12.2.3
Program Module Process Flow (Main Program)
The flowchart in figure 12-6 demonstrates the procedure for displaying
key data received from the console typewriter on both the H257l and
console typewriter, as performed by the program module in figure 12-5.
Main Program
EXPMN
$18F--+SP
--{
$04--+CRA
--{ Select peripheral interface register A of PIA.
$OO--+PIRA
--{ Set signals RS, R/W, and E of LCD-II to Low.
$OO--+CRA
--{ Select DDRA of PIA.
$FF--+DDRA
--{ Select port A of PIA as output.
$04--+CRA
---[ Select peripheral interface register A of PIA.
$OO--+CRB
--{ Select DDRB of PIA.
$FF--+DDRB
- -{ Select Port B of PIA as output.
04--+CRB
-- {
Select port B register of PIA.
---[
Initialize LCD-II.
--{
x
PBS
x
PIN S
--{
--{
97--+CR
--{
Y
Initialize stack pointer.
--{
--{
--{
--{
Load display ON instruction into entry
argument of EXPINS.
Check busy flag.
Store instruction in LCD-II.
Initialize transmit control bit of ACIA control
register to set RTS=Low, disable interrupts, and
master reset ACIA.
Initialize ACIA control register to set counter
divide bit to 16, word select bit as 8 bit data
+1 stop bit, and enable interrupts.
Clear key data receiving flag.
Initialize RAM/port 5 control register of the
HD6301YO to define P50 to IRQl pins.
Enable interrupts.
Figure 12-6.
Program Module Flowchart
~HITACHI
1017
I
data is received from the console
---[ Load key data into entry argument of TPR.
--{ Clear key data receiving flag.
--{ Set signal RTS of ACIA to Low.
Convert ASCII lowercase into uppercase.
-- { Refer to TPR in HD6301/HD6303 FAMILY
APPLICATION NOTES (SOFTWARE).
--{
--{
--{
Load ASCII uppercase into entry argument
of EXPOUT and EXPDSP.
Display characters on H2571.
Send display data to the console
typewriter.
IRQ Interrupt Routine
--~ Receive data from the con'ole typewriter.
Figure 12-6.
Program Module Flowchart (Cont.)
~HITACHI
1018
12.3
PROGRAM MODULE DESCRIPTION
Proqram Module Name: INITIALIZE
MCU/MPU: HD6301YO/
HD6303Y
ICD-II
Label: EXPINT
Function:
Initializes LCD-II contained in the H2571 liquid crystal module.
Arguments:
Changes in CPU
None
Re~isters
ACCD
ACCA ACCB
x
x
•
x
t
:
ROM (Bytes) : 37
RAM (Bytes) : 1
Stack' (Bytes) : 2
No. of cycles: 45637
IX
•
Specifications:
and Flags:
Reentrant: No
C
V
x
x
Z
N
x
x
I
H
•
•
Relocatable: No
Interrupt OK?: Yes
Not affected
Undefined
Result
Description:
1.
Function Details
a.
EXPINT has no arguments.
b.
LCD-II is reset by instruction. Data in table 12-5 is sent to initialize
display mode.
Specifications Notes:
1.
"Specifications" includes those used by called subroutines.
2. "No. of cycles" in "Specifications" indicates the number of cycles required
when EXPBSY is executed a minimum number of cycles.
@HITACHI
1019
I
Program Module Name: INITIALIZE
LCD-II
M_C_U_/_M_P_U_:__HD_6
__
30_1_Y_0_/____
HD6303Y
L..
~lL_a_b_e_l_:
.
__
EX_P_I_NT
______
Description:
Table 12-5.
c.
Data
Function
$30
Interface length: 8 bits
Display Font: 5 x 7 dots
Display OFF, Cursor OFF, Blink OFF
$01
Clear display, set DDRAM address to $00
$06
Increment DDRAM address, No display shift
EXPINT calls other subroutines as shown in table 12-6.
Subroutines Called by EXPINT
Subroutine Name
Label
Function
STORE INSTRUCTION
EXPINS
Store instruction in LCD-II.
CHECK BUSY FLAG
EXPBSY
Check LCD-II busy flag.
The following procedure is required before EXPINT execution.
i.
ii.
iii.
Initialize control signals (signals RS, R/W, E) of LCD-II.
Select ports A and B as output.
Initialize control register of PIA to select peripheral interface
registers A and B.
b.
Instruction data shown in Table 12-5 must be reserved as data table.
RAM
Allocation
Label
Description
RAM
b7
INSDAT
bO
} Instruction data
~HITACHI
1020
1
User Notes
a.
3.
Columns:
$08
Table 12-6.
2.
Initialize Data for Display Mode
~
Program Module Name: INITIALIZE
LCD-II
MCU/MPU: HD6301YO/
HD6303Y
I
Label,
EXPINT
Description:
4.
Sample Application
I
I
I
II
DMODE
5.
LDAA
STAA
LDAA
STAA
CLR
STAA
LDAA
STAA
LDAA
STAA
CLR
STAA
LDAA
STAA
LDAA
STAA
#$04
CRA
#$02
PIPA
A
CRA
#$FF
DDRA
#$04
CRA
A
CRB
#$FF
DDRB
#$04
CRB
JSR
EXPINT
FCB
$30,$08,$01,$06 ----- Reserve data table
}
Select peripheral interface register A of
PIA.
}
}
}
}
}
Initialize LCD-II control signal.
Select data direction register A of PIA.
Select port A of PIA as output.
Select peripheral interface register A of
PIA.
Select data direction register B of PIA.
}
Select port B of PIA as output.
Select peripheral register B of PIA.
}
II ----- Execute EXPINT to initialize LCD-II.
Basic Operation
a.
If peripheral control pin is not used, read/write operation of PIA is
executed as described below. The procedure for initializing port A and
read operation is as follows.
[ Clear bit 2 of port A control register to select
data direction register.
_____[~elect port A data direction register as
~-----r----~
~nput.
~-----r----~
_____[Set bit 2 of port A control register to select
peripheral interface register A.
~-----T----~
_____ [Load peripheral interface register A and input
from port A.
Figure 12-7.
Read Operation
~HITACHI
1021
Program Module Name:
INITIALIZE
MCU/MPU:
LCD-II
HD630lYO/
HD6303Y
Label:
--
EXPINT
Description:
The procedure for initializing port A and write operation is as follows:
[ Clear bit 2 of port A control register to select
port A data direction register.
_____ [Select port A data direction register as
output.
_____[set bit 2 of port A control register to select
peripheral interface register A.
_____[store peripheral interface register A and output
port A.
Figure 12-8.
b.
Write Operation
LCD-II is software reset by the following procedure:
Reset
LCD-II
Wai t for ISms
just after
power on
Figure 12-9.
Reset LCD-II
~HITACHI
1022
Program Module Name: INITIALIZE
LCD-II
MCU/MPU: HD630lYO/
HD6303Y
I
Label ,
EXPINT
Description:
c.
Software controls the LCD-II control signal using port A of PIA, and
the data bus using port B.
d.
Programming notes
i.
ii.
iii.
iv.
Both a lSms wait by software timer and transfer of $30 to the data
bus three times is needed reset LCD-II.
Index register is used both as a pointer to the instruction data
table and as a counter of the number of data transfers.
LCD-II busy flag is checked before outputting instruction data.
After process (iii) is executed four times, display mode is
initialized.
~HITACHI
1023
Program Module Name: INITIALIZE
LCD-II
MCU/MPU: HD630lYO/
HD6303Y
I~
EXPINT
Flowchart:
L _ _-.-_ _---.J
- - -{
Initialize counter for three loops.
Execute ISms software timer.
~----..l
--{
Load instruction of function set into
entry argument of EXPINS.
--{
Write instruction to LCD-II.
---[
Decrement loop counter.
--{
Test if LCD-II reset is complete.
--{
Load starting address of data table
where display mode data is stored.
--{
Load display mode instruction into
entry argument of EXPINS.
1..L..--....,-----l.I - - - (
1..L..--....,-----l.I - - {
Check busy flag.
Write instruction to LCD-II.
--{
Increment pointer to data table of
display mode.
---{
Test if all display mode data has been
written.
~HITACHI
1024
Program Module Name: RECEIVE DATA
MCU/MPU:
~
HD6301YO/
HD6303Y
EXPINP
Function:
Receives key data from the console typewriter and stores it in RAM.
Arguments:
Storage
Location
Contents
Entry
Specifications:
Changes in CPU
No. of
Bytes
Registers and Flags:
ACCD
ACCA ACCB
x
--
ROM (Bytes) : 26
I •
RAM
Stack (Bytes) : 0
IX
•
Received
Returj'lS data
(ASCII)
KEYDAT
(RAM)
1
Received
flag
KEYDRF
(RAM)
1
•
x
:
No • of cycles: 43
Reentrant: No
C
x
V
Z
N
x
x
(Bytes) : 2
Relocatable: No
x
I
H
•
•
Interrupt OK?: Yes
Not affected
Undefined
Result
Description:
1.
CD
Function Details
a.
Entry
{
Press "a"
C' a ' = $ 6 1)
Argument details
KEYDAT(RAM): Holds key data from
the console typewriter
in ASCII.
KEYDRF(RAM): Key data receive Flag.
Table 12-7 shows flag
functions.
b7
Result
{
KEYDATCRAM)
C ' a '=$ 61)
KEY~~;CRAM)
Figure 12-10.
I
KEYDAT
6
:
1
bO
I
b7 KEYDRF bO
I
0
:
1
I
Example of EXPINP
Execution
Specifications Notes:
~HITACHI
1025
I
Program Module Name: RECEIVE DATA
MCU/MPU:
HD6301YO/
HD6303Y
I
Label ,
EXPINP
Description:
b.
Example of EXPINP execution is shown in figure 12-10. If "a" is
depressed in console typewriter as shown in partQ) of figure 12-10,
key data is stored in KEYDAT(RAM) and $01 is set in KEYDRF(RAM).
Table 12-7.
c.
2~
Flag Functions
Label
bit 0
Function
KEYDRF
o
Indicates key data is not received.
1
Indicates key data is received.
EXPINP calls neither the program modules nor subroutines.
User Notes
The following procedure must be executed before EXPINP execution.
3.
a.
Initialize ACIA since ACIA must interface with peripheral device
(receives data from the console typewriter).
b.
Initialize RAM/port 5 control register since IRQl pin is used.
c.
Clear bit I to enable interrupts since IRQl interrupt is used.
RAM Allocation
RAM
Label
Description
b7
KEYDAT
KEYDRF
4.
bO
1----11 t
Key data
Used as a flag indicating whether or not key
data is received.
Sample Application
LDAA
STAA
LDAA
STAA
BCLR
LDAA
STAA
CLI
#$97
CR
#$95
CR
O,KEYDRF
#$7D
RP5CR
}
Master-reset ACIA.
}
Initialize control register of ACIA.
Initialize received flag.
}
Initialize RAM/port 5 control register.
Enable interrupts
~HITACHI
1026
Program Module Name: RECEIVE DATA
MCU/MPU: HD6301YO/
HD6303Y
Label:
EXPINP
Description:
5.
Basic Operation
a.
Example of initializing ACIA is shown in figure 12-11.
Note:
For master-reset, "11" is stored in bits 0 and 1 of control register.
Bits 5 and 6 must be defined to obtain specified RTS output.
Master-reset ACIA.
[
----- (RTS=Low and disable sending interrupts).
Initialize control register of ACIA.
_____ [ (Selecting counter devide select bit"'" 16, start
bit +8 bits data +1 stop bit, and enable receiver
interrupts. )
Figure 12-11.
b.
Example of Initializing ACIA
Programming notes
i.
ii.
iii.
iv.
Received data is checked for any errors.
If an error has ocurred, received data is ignored.
If an error has not ocurred, received data is stored in
KEYDAT(RAM) and received flag is set.
Receive data register of ACIA is read and interrupts are enabled.
I
~HITACHI
1027
_p_r_o_g_r_a_m_M_o_d_u_l_e_N_am_e_:_R_E_C_E_I_VE
__D_Pi_T_A_--, L.M_C_U_I_M_P_U_:_HD_6_3_0_l_Y_O_I
_E_X_P_I_NP
_ _ _....J
HD6303Y _ _- I lL_a_b_e_l_:
.
L.
Flowchart:
Test if framing error or receiver
[ overrun error has occurred.
- - { Set signal RTS of ACIA to High.
___ [ Clear receive data register
full bit.
__ { Store data from the console
typewriter.
- - { Set received flag.
EXPIPI
___[ Clear receiver overrun bit and
receive data register full bit.
EXPIP2
_ _. 1 . . - -.....
~HITACHI
1028
Program Module Name: DISPLAY
CHARACTERS
Label:
MCU/MPU: HD6301YO/
HD6303Y
EXPDSP
Function:
Stores ASCII in display RAM(DDRAM) and displays characters on the LCD.
Arguments:
Contents
Entry
Display
data
Changes in CPU
Storage
Location
No. of
Bytes
DSPDAT
(RAM)
1
Specifications:
Registers and Flags:
ACCD
ACCA ACCB
x
x
ROM (Bytes): 78
RAM
(Bytes):
1
stack (Bytes): 2
IX
•
No. of cycles: 106
Reentrant: No
Returns
---
---
C
v
x
x
Z
N
x
x
I
H
•
•
-
•
Relocatable: No
Interrupt OK?:
Yes
Not affected
x : Undefined
Resul t
Description:
1.
Function Details
a.
Argument details
DSPDAT(RAM): Holds display data in
1 byte ASCII.
b.
Example of EXPDSP execution is
shown in figure 12-12. If entry
argument is as shown in part
of figure 12-12, a character is
displayed on the LCD as shown in
part@of figure 12-12.
CD
Figure 12-12.
Example of EXPDSP
Execution
Specifications Notes:
L,
2.
Values in "Specifications" include those used by subroutines called by EXPDSP.
"No. of cycles" in "Specifications" indicates the number of cycles required
when EXPBSY is executed the minimum number of cycles.
@HITACHI
1029
Program Module Name: DISPLAY
CHARACTERS
MCU/MPU: HD6301YO/
HD6303Y
Label:
EXPDSP
---
Description:
c.
EXPDSP calls an other subroutine as shown in table 12-8.
Table 12-8.
2.
Subroutine Called by EXPDSP
Subroutine Name
Label
Function
CHECK BUSY FLAG
EXPBSY
Checks LCD-II busy flag.
User Notes
The following procedure must be executed before EXPDSP execution.
3.
a.
Initialize PIA since PIA must interface with peripheral devices
(LCD-II is controlled by ports of PIA).
b.
Initialize LCD-II by executing EXPINT.
RAM Allocation
RAM
Label
b7
bO
DSPDAT
4.
Description
}
Display data in ASCII
Sample Application
I
I
I
LDAA
STAA
LDAA
STAA
CLR
STAA
LDAA
STAA
LDAA
STAA
CLR
STAA
LDAA
STAA
LDAA
STAA
BSR
LDA
STA
II JSR
#$04
CRA
#$02
PlRA
A
CRA
#$FF
DDRA
#$04
CRA
A
CRB
#$FF
DDRB
#$04
CRB
EXPINT
#$41
DSPDAT
}
}
}
EXPDSP
II
Select peripheral interface register A of PIA.
Initialize LCD-II control singal.
Select data direction register A of PIA.
}
Select port A of PIA as output.
}
Select peripheral interface register A of PIA.
}
Select data direction register B of PIA.
}
Select port B of PIA as output.
}
Sele.ct peripheral interface register B of PIA.
Execute EXPINT to initialize LCD-II.
}
Load entry argument of EXPDSP.
----- Execute EXPDSP.
~HITACHI
1030
Program Module Name: DISPLAY
CHARACTERS
M_C_U_/_M_P_U_:__HD
__
6_30_l_Y_O_/____
HD6303Y
....
.
~I
EX_P_D_S_P____
. L_a_b_e_l_:__
~
Description:
5.
Basic Operation
a.
LCD-II busy flag is checked by EXPBSY execution.
b.
Control signal of LCD-II is controlled by port A of PIA and display data
is output from port B.
~HITACHI
1031
Program Module Name: DISPLAY
CHARAcrERS
MCU/MPU: HD630lYO/
HD6303Y
I~
Flowchart:
- - { Execute EXPBSY to check busy flag.
__ {set signal RS to High, signal R/W
to Low.
- - { Set signal E to High.
__ {write display data to port B and
display characters on LCD.
- - { Set signal E to Low.
__ {set signal RS to Low, signal R/W
to High, and signal E to Low.
~HITACHI
1032
EXPDSP
Program Module Name: SEND DATA
Label: EXPOUT
MCU/MPU:HD6301YO/
HD6303Y
Function:
Sends data to the console typewriter.
Arguments:
Contents
Entry
Sending
data
Speci fica tions:
Changes in CPU
Storage
Location
No. of
Bytes
OUTDAT
(RAM)
1
Registers and Flags:
ACCD
ACCA ACCB
x
ROM (Bytes):
13
RAM (Bytes):
1
Stack (Bytes): 0
IX
No. of cycles: 21
Reentrant:
C
v
o
x
Returns
z
N
x
x
I
x
:
Relocatable:
No
Interrupt OK?:
Yes
H
o
Q
No
I)
Not affected
Undefined
Result
Description:
1.
Function Details
a.
{ OUI'DA~(RA'v!)
En try
argument Sendlng
data
Argument details
OUTDAT(RAM): Holds data to be sent
to the console typewriter in ASCII.
b.
Example of EXPOUT execution is
shown in figure 12-13. If entry
argument is as shown in part Q) of
figure 12-13, a character is
printed as shown in part@of
fiqure 12-13.
(' A'
b7 OUTDAT bO
I
$41)
Type A
r--
@
Result
0:
~!
01
Figure 12-13.
4
:
1
I
tI
~
----_._~IJ
Q.
Example of EXPOUT
Execution
Specifications Notes:
"No. of cycles" in "Specifications" indicates the number of cycles required when
the transmit data register is empty.
~HITACHI
1033
I
Program Module Name: SEND DATA
M_C_U_/_M_P_U_:__HD
__6_3_0_1_Y_O/____
HD6303Y
I-
~lL_a_b_e_l_: ~
.
_____O_UT
______
Description:
c.
2•
EXPOUT calls neither the program modules nor subroutines.
User Notes
a.
The following procedure must be executed before EXPOUT execution.
i.
3.
Initialize ACIA since ACIA must interface with peripheral devices
(data is sent to the console typewriter).
b.
If data has been previously stored in the transmit data register, EXPOUT
waits until it is empty so as not to destroy this data.
RAM
Allocation
Label
Description
RAM
bO
b7
Character data to be sent to the console
typewri ter.
OUTDAT
4.
Sample Application
II
5.
LDAA
STAA
IDAA
STAA
LDAA
STAA
#$97
#$95
CR
#$41
OUTDAT
JSR
EXPOUT
CR
}-----
Master-reset ACIA.
}----- Initialize control register of ACIA.
}
II
Load output data into entry argument.
----- Execute EXPOUT.
Basic Operation
a.
Transmit data register empty flag of ACIA is tested for 1 or O.
"1", load output data into the transmit data register of ACIA.
b.
Instruction BTST of the HD6301YO is replaced by instruction ANDA since
instruction BTST cannot be used in extended addressing.
~HITACHI
1034
If it is
~
Program Module Name: SEND DATA
MCU!MPU: HD630lYO/
HD6303Y
I~
EXPOUT
Flowchart:
EXPOUT
__ {Test if transmit data register is
empty.
Write output data to the transmit
-- { data register of ACIA and send it
to the console typewriter.
I
~HITACHI
1035
12 4
SUBROUTINE DESCRIPTION
Subroutine Name:
MCULMPU:
STORE INSTRUCTION
HD6301YO/
HD6303Y
Label:
EXPINS
Function:
Stores instruction data in LCD-II instruction register.
Basic Operation:
Signals RS, R/W, and E are controlled by port A of PIA, and instruction data
is output from port B.
Program Module Using This Subroutine:
EXPINT
Flowchart:
- - {
Set signal R/W to Low.
- - {
Set signal E to High.
---[ Output instruction data to port B.
- - {
Set signal E to Low.
__ { Set signal RS to Low I signal R/W
to High, and signal E to Low.
~HITACHI
1036
MCU(MPU: HD6301YOj
HD6303Y
Subroutine Name: CHECK BUSY FLAG
Labe 1: EXPBSY
Function:
Checks whether or not LCD-II is in operation and waits until i t is ready.
Basic Operation:
1.
If LCD-II is in operation, the HD6301YO cannot access if the LCD-II busy
flag indicates whether or not it is in operation.
2.
Signals RS, RjW, and E are controlled by port A of PIA, and the busy flag is
read by port B.
Program Module Using This Subroutine:
EXPINT, EXPDSP
Flowchart:
--{
--{
--{
Select data direction register of port B.
Select port B as input to read busy flag.
Select peripheral interface register of
port·B.
--{
Set signal E to High.
--{
Read LCD-II busy flag.
--{
Set signal RS to Low, signal R/W to High,
and signal E to Low.
I
LOOp until busy flag=O.
(Bit
r-_ _-'---'-_..,C)?' 1
--{
Select data direction register of port B.
--{
Select port B as output.
--{
Select peripheral interface register of
port B.
~HITACHI
1037
12.5
PROGRAM LISTING
00001
00002
00003
00004A
00005
00006A
00007
00008A
00009A
00010A
OOOllA
00012A
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033A
00034
00035A
00036A
00037A
00038A
00039A
00040A
00041A
00042A
00043A
00044A
00045A
00046A
00047A
00048A
00049A
00050A
00051A
00052A
00053A
00054A
00055A
00056A
00057A
*
****
*
0040
0040
0001
0001
0001
0001
0001
0014
AOOO
AOOl
A002
A003
AOOO
A002
COOO
COOO
COOl
COOl
ALLOCf~TION
Existence of r'eceive data
A I(EYDRF RMB
A
A
A
A
~********~;I:'I~*******~:~:****
$40
ORG
*
*
8000
8000
8001
8002
8003
RAM
$8000
INSDAT
OUTDAT
DSPDAT
I(EYDAT
ORG
RMB
RMB
RMB
RMB
*
****
SYMBOL DEFINITIONS **********************
1
1
1
1
Instruction data
Data to be sent
Display data
Receive data
A *RP5CR
A
A
A
A
A
A
A
A
A
A
EQU
$14
Por't 5 control register
EQU
DDRA
Data dir'ection register A(PIA)
lAOOO
EQU
Control register' A(PIA)
CRA
$AOOI
EQU
$A002
Data direction register' B(PIA)
DDRB
EQU
Contr'ol register B(PIA)
$A003
CRB
EQU
Per' i pher'al r'egister' A(PIA)
PIRA
$AOOO
EQU
$A002
Pe r' i pller'a l reg i ster' B(PIA)
PIRB
EQU
Contr'ol register'(ACIA)
CR
$COOO
EQU
$COOO
Status r'eg i ster'(ACIA)
SR
EQU
$COOI
Receive data r'eg i ster(ACIA)
RDR
EQU
TDR
$C001
Tr'ansmit data r'eg i ster'(ACIA)
******************************************f.*****
*
COOO
COOO
C003
COOS
C008
C009
COOC
COOF
COlI
C014
C016
C019
COlA
COlD
COIF
C022
C024
C027
C02A
C02C
C02F
C031
C034
C036
>I<
>I<
MAIN PROGRAM : EXPMN
*
***************************~:****************~,****>I<
*
ORG
$COOO
8E
86
87
4F
87
B7
86
87
86
87
4F
B7
86
87
86
B7
BD
86
B7
8D
BD
86
B7
*
013F
04
AOOI
A EXPMN
A
A
AOOO
AOOI
FF
AOOO
04
AOOI
A
A
A
A
A
A
A003 A
FF
A
A002 A
A
04
A003 A
COAE A
OE
A
8000 A
52 C083
COD3 A
97
A
COOO A
LDS
LDAA
STAA
CLRA
STAA
STAA
LDAA
STAA
LDAA
STAA
CLRA
STAA
LDAA
STAA
LDAA
STAA
JSR
LDAA
STAA
BSR
JSR
LDAA
STAA
FI$13F
FI$04
CRA
Initialize stack pointer
Select peripheral register' A
Set RS=O.R/W=O.E=O
PIRA
CRA
FI$FF
DDRA
FI$04
CRA
CRB
FI$FF
DDRB
FI$04
CRB
EXPINT
FI$OE
INSDAT
EXPBSY
EXPINS
FI$97
CR
Select port A as output
Select per' i pheral register A
Select data direction register 8
Select port B as output
Select peripher'al register B
Initialize LCD-II
Store LCD display data
Checl< busy flag
Store instruction
Master-reset ACIA
.HITACHI
1038
00058A
00059A
00060A
00061A
00062A
00063A
00064A
00065A
00066A
00067A
00068A
00069A
00070A
00071A
00072A
00073A
00074A
00075A
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086A
00087A
00088A
00089A
00090A
00091A
00092A
00093A
00094A
00095A
00096A
00097A
00098
00099
OOlDO
00101
00102
00103A
00104A
00105A
00106A
00107A
00108A
00109A
00110A
OOlllA
00112A
00113A
00114A
C039
C03B
C03E
C041
C043
C045
C046
C049
C04B
C04E
C051
C053
C056
C059
C05C
C05F
C061
C064
86
B7
71
86
97
OE
7B
27
B6
71
C6
F7
BD
B7
B7
80
BD
20
LDAA
STAA
BCLR
LDAA
STAA
CLI
EXPMN1 BTST
01 40
BEQ
FB C046
LDAA
8003 A
BCLR
FE 40
LDA8
95
A
STAB
COOO A
COFA A
JSR
STAA
8001 A
STAA
8002 A
05 C066
BSR
JSR
COEC A
BRA
EO C046
95
A
COCO A
FE 40
A
70
14
A
11$95
Initial.ize ACIA
CR
O.I:ecute softwaer' timer'
EXPIT2
tl1;30
HJSDIH
EXF'INS
Store function data
ExrIll
HDMLlDE
O.X
INSDAT
EXPBSY
EXF'lN:,
>1"
Wr' i te i nstr'act i on to LCD-II
Decr'ement counter'
Loop untiL TNCNT=O
Load stat'tins ADOR of dispLay mode data tabL
Store i n~;tt'uct i on data
Checi< busy flas
Stor'e instr'uction
Decrirnent po inter'
flDMODE+4 Loop until. IX=IWMOOE+4
EXPIT3
**********)k****:k:k*~(*****~(***********************
*
"
NAME
EXPINS (STORE INSTRUCTION)
:
"
COD3
COD4
C007
COD9
CODC
CODF
COE2
COE3
COE6
COE8
COEB
4F
B7
86
B7
B6
B7
4F
B7
86
B7
39
"
"
*
~(**+*********~(****~;lk**~~I~*~:**********~(**~:***** ***
AOOO
01
AOOO
8000
A002
A
A
A
A
A
AOOO
02
AOOO
A
A
A
EXPINS CLRA
STAA
LDAA
STAA
LDAA
STAA
CLRA
STAA
LDAA
STAA
RTS
PIRA
fI$Ol
PIRA
INSDAT
PIRB
PIRA
11$02
PIRA
Set R/W=O
Set E=l
Store instruction
Set E=O
Set RS=O.R/W=l.E=O
************~(***********************************
>I<
*
>I<
>I<
NAME
:
EXPOUT (SEND DATA)
*
"
****************~*******************************
@HITACHI
1040
*
*
00172
00173
00174
00175
00176
00177A
00178A
00179A
00180A
00181A
00182A
>I<
*
COEC
COEE
COFI
COF3
COF6
COF9
86
B4
27
B6
B7
39
Tn
A,
BE SEN1)
*
>I<
*
*
***********>V*****:I'***'I:'j":""W'1 I' j"'I':I"I'*'I'***"'**'I"I'**)I:**~'
02
A EXPoUT
COOO A
F9 COEC
8001 A
COOl A
LDAA
ANOA
BEQ
LOAA
STAA
RTS
H$02
SR
EXPOUT
oUTDAT
TOR
Te3t If TORE-I
Loop untiL TDRE=O
Store send data
***~***.'*~*****>V************.******************
00183
00184
00185
00186
00187
00188
00189
00190
00191
00192
00193
00194A
00195A
00196A
00197A
00198A
00199A
00200
00201
00202
00203
00204
00205
00206
00207
00208
00209
00210
00211A
00212A
00213A
00214A
00215A
00216A
00217A
00218A
00219A
00220A
00221A
00222
00223
00224
00225
00226
00227A
00228
ENTRY: OUTonT (DATA
RETURNS: NoTIlING
*
*
*
*
NAME: TPR (CONVERT ASCII LOWERCASE
INTO UPPERCASE)
*
>I<
*
*
**********************>1<*************************
0;:
*
*
*
COFA
COFC
COFE
C100
C102
C104
81
25
81
22
84
39
ENTRY : ACCA (ASCII LOWERCASE)
RETURNS: ACCA (ASCII UPPERCASE)
*
*
*
*
************************************************
CMPA
a'a
ACCA - 'a' ?
BCS
TPR1
Branch if ACCA < 'a'
61
A TPR
06 C104
7A
A
02 C104
OF
A
TPR1
CMPA
BHI
ANDA
RTS
"'z
TPR1
"$DF
ACCA - 'z' ?
Branch if ACCA > 'z'
Convert Lowercase into uppercase
************************************************
*
*
*
NAME : EXPINP (RECEIVE OATh)
*
*
*
************************************************
*
*
*
*.
*
C105
C107
C10A
C10C
C10E
C111
C114
Cl17
C11A
C11B
C11E
86
B4
26
86
B7
B6
B7
72
3B
B6
20
ENTRY
NOTHING
RETURNS: KEYDAT (RECEIVED DATA)
II<
C120
30
*
*
*
'"
"'***********************************************
A DMoDE
FCB
I
$30.$08.$01.$06
************************************************
~HITACHI
1041
00229
00230
00231
00232
00233
00234A
00235
00236A
00237A
00238A
00239A
00240A
00241A
00242A
00243A
00244A
00245A
00246A
00247
00248
*
*
VECTOR ADDRESSES
*
*
*
*
************************************************
*
FFEA
FFEA
FFEC
FFEE
FFFO
FFF2
FFF4
FFF6
FFF8
FFFA
FFFC
FFFE
COOO
COOO
COOO
COOO
COOO
COOO
COOO
Cl05
COOO
COOO
COOO
A
A
A
A
A
A
A
A
*
A
A
A
*
ORG
$FFEA
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
EXPMN
EXPMN
EXPMN
EXPMN
EXPMN
EXPMN
EXPMN
EXPINP
EXPMN
EXPMN
EXPMN
IRQ2
CMI
TRAP
SID
TOI
OCI
ICI
IRQ1/ISF
SWI
NMI
RES
END
~HITACHI
1042
SECTION 13.
13.1
SLOW DEVICE INTERFACE
HARDWARE DESCRIPTION
13.1.1
Function
Compares a check sum, obtained from a data block in external memory,
with a check sum stored beforehand in the data block and indicates
whether or not they are the same using an LED.
13.1.2
Microcomputer Operation
The HD63B01YO accesses slow devices using the auto-memory-ready function.
Signal cSl of the slow devices is input directly to the memory-ready
pin by setting both the enable bit of memory-ready and the enable bit
of auto-memory-ready to "1".
13.1.3
Peripheral Devices
HN482764G-3 EPROM:
Used as an external memory.
Its maximum access
time is 300ms.
13.1.4
Circuit Diagram
Memory-ready circuit is shown in figure 13-1.
I
~HITACHI
1043
MCU
HD68BOIYO
+5V
EPROM
HN482764G-8
MP,
8 NMI
7
8TBY
88
Vee
22pF
XTAL
[WhO
EXTAL
22pF
56
55
54
58
52
Do 51
D.
A., 50
A 49
47kO
6
RE8
y'~
VBS
4
42
MP.
VBS
O.
0,
A. 47
A. 46
At 45
A. 44
A., 48
A. 41
A.
A.
89
A,. 88
All 87
A,.
86
A,. 85
A,. 84
A"
P.,/MR
~!
o.
O.
O.
0,
O.
O.
20
CE
19
22
RI> 68
WR 62
+5V
+5V
D,
D.
D.
D.
D.
'408
+5V
182076
Do 57
OE
GND
14
RAM
HM6264LP-I0
Uk0 25
A.,
p ••
A,
A.
A.
At
A,
A.,
A.
A.
21 A.
A,.
28
All
2
An
20
22
27
Figure 13-1.
Memory-ready Circuit
~HITACHI
1044
I/O,
I/O.
I/O.
I/O.
I/O,
I/O.
I/O.
I/O.
15
16
11
18
19
+5V
28
Vee
26
C8.
C8,
OE
E
GND
14
13.1.5
Pin Fqnctions
Pin functions for control of LED connection pins and slow device pins
are shown in table 13-1.
13.1.6
Table 13-1-
Pin Functions
Pin Name
(HD63B01YO)
Input!
Output
Active Level
(High or Low)
Function
Program
Label
P60
Output
Low
Turns on LED.
P6DTR
PS2!MR
Input
Low
Memory-ready pin.
Memory Map
Address decoding for this application example is shown in table 13-2.
A slow memory device, the HN482764G-3, is allocated as external
memory by the HD74HC138 address decoder.
Address buses A13 , A14 and
A15 are connected to A, Band C pins, respectively, of the HD74HC138.
Address space $8000'" $FFFF is divided into 8k-byte sections.
Table 13-2.
Address Decoding
Address
HD74HC138
Allocation
Output
Input
Gl G2A G2B
C
B
A
Yo Yl Y2 Y3 Y4 Ys Y6 Y7
A1S A14 A13
H L
L
H
L
L
H H H H L
H L
L
H
L
H
H H H H H L
H L
L
H
H
L
H H
H L
L
H
H
H
H H H H H H H L
$
H H H 8000'" 9FFF
H H AOOO"'BFFF
H H H H L
H COOO"'DFFF
EOOO'" FFFF
EPROM
Not Used
Internal ROM
Internal ROM
HITACHI
1045
I
Memory map for this application example is shown in figure 13-2.
Internal Registers
Not Used
Internal RAM (256 bytes)
Not Used
EPROM HN482764G-3
Not Used
Internal ROM (16k-bytes)
Figure 13-2.
13.1.7
Memory Map
Hardware Operation
Timing chart for the HD63B01YO and slow device HN482764G-3 is shown
in figure 13-3.
E
Address Bus )(_ _---1X'-__...JX EPROM address
MR
(CS signal of slow device)
\
Data Bus
Figure 13-3.
Memory-Ready Bus Timing
~HITACHI
1046
13.2
SOFTWARE DESCRIPTION
13.2.1
Program Module Configuration
The program module configuration for determing check sum is shown in
figure 13-4.
MRMN
~
MAIN
PROGRAM
MRCHK
I
l2.
CHECK SUM
Figure 13-4.
13.2.2
Program Module Configuration
Program Module Functions
Program module functions are summarized in table 13-3.
Table 13-3.
Program Module Functions
No.
Program Module Name
Label
Function
o
MAIN PROGRAM
MRMN
Displays result of comparing check
sums.
1
CHECK SUM
MRCHK
Obtains check sum of data block in
external memory.
~HITACHI
1047
13.2.3
Program Module Process Flow (Main Program)
The flowchart in figure 13-5 shows the procedure for testing check
sums as performed by the program module in figure 13-4.
Main Program
- - - { Ini tialize stack pointer.
___ {select port 4 as output for upper address
output.
----(Initialize RAM/port 5 control register.
___ {Load the starting address of external ROM
into entry argument (IX) of MRCHK.
---{Execute MRCHK to obtain check sum.
(Bit e) = 1
Test whether or not check sum obtained
- - --[ in this program and check sum stored
beforehand are the same.
Bit
ell
LED
Figure 13-5.
___ {
If these two check sums are the same,
turn on LED.
---{If not the same, make LED blink on and off.
Program Module Flowchart
@HITACHI
1048
13.3
PROGRAM MODULE DESCRIPTION
Program Module Name: CHECK SUM
Label: MRCHK
MCU/MPU: HD630lYO/
HD6303Y
Function:
Obtains check sum of data block and compares check sum obtained with check sum
stored beforehand.
Changes in CPU
Arguments:
Storage
Location
Contents
Entry
Data table IX
starting
address
No. of
Bytes
Specifications:
Registers and Flags:
ACCD
ACCA ACCB
2
x
x
ROM (Bytes) : 23
RAM
(Bytes) : 2
Stack (Bytes) : 0
IX
No. of cycles: 137
x
Reentrant: No
Returns
Check sum
result
indicator
bit C
(CCR)
1 bit
•
C
V
~
x
Z
N
x
x
I
H
•
x
Relocatable: No
Interrupt OK?: Yes
Not Affected
x : Undefined
Result
Description:
1.
Function Details
a.
Argument details
IX: Holds the starting address of data table:
bit C(CCR): Used as a flag indicating whether or not contents of external
memory are correct, determined by check sum result. Table
13-4 shows flag functions.
b.
Example of MRCHK execution is shown in figure 13-6. If entry argument
is as shown in part Q) of figure 13-6, bit C is set to "I" as shown in
part @ of figure 13-6 when the two check sums are the same.
Specifications Notes:
"No. of cycles" in "Specifications" indicates the number of cycles required to
obtain a check sum for 9 bytes.
@HITACHI
1049
_p_r_o_g_r_am
__M_o_d_u_l_e_N_a_m_e_:_C_H_E_C_K_S_UM
_ _ _ _....J L.M_C_U_/M_P_U_:_IID_6_3_0_1_Y_0_I
_MR_C_H_K_ _ _--I
HD6303Y _ _---I lL_a_b_e_l_:
.
L.
Description:
Table 13-4
Flag Functions
Register
bit C
Function
CCR
0
Indicates contents of external memory is not
correct.
1
Indicates contents of external memory is
correct.
Q;)
Entry
argument
{~~8000)
blS IX
bO
I8 : 0 I 0 : 0 I
Data Block
b7
$8000
$80
$8006
$06
$11
$12
$13
$14
$4A
Address of
check sum
Data for which
check sum is
to be computer
Check sum
l
@
Return {
argument
Figure 13-6.
c.
Bit C
(CCR)
Bit C
IT]
Example of MRCHK Execution
MRCHK calls neither the program modules nor subroutines.
~HITACHI
1050
Program Module Name: CHECK SUM
L-M_C_U_/_M_P_U_:
__HD
__6_3_0_1_Y_O_/____
_
HD6303Y
~
ILL_a_b_e_1_:
__MR
__
C_HK
______
_
~
Description:
2.
User Notes
a.
Initialize RAM/port 5 control register since the auto-memory-ready
function is used.
b.
To check the contents of external memory, data, shown in figure 13-7,
must be stored in memory.
External ROM
b7
bO
Starting address _ $ 8 0 0 0 f 3 9 8 0
of external
$OC
memory, allocated
by users.
} Address in which LSD of
check sum is stored.
Data
r
$800C [
Figure 13-7.
3.
Check sum of data above.
External ROM
RAM Allocation
Label
CHEND
Description
RAM
b7
bO
Address in which correct check sum is
stored.
~HITACHI
1051
Program Module Name: CHECK SUM
M_C_U_/_M_P_U_:_HD
__
6_3_0_l_Y_0_/____
HD6303Y
L-
~lL_a_b_e_l_:
_
__
MR_C_HK
________
Description:
4.
Sample Application
LDAA
STAA
LDX
5.
}
Initialize RAM/port 5 control register.
Load starting address of external memory
into entry argument of MRCHK.
II BSR
MRCHK
BCC
ERROR
Test whether or not contents of memory
is correct.
ROUTINEII
Execute service routine if contents of
memory are correct.
II SERVICE
ERROR
#$F4
RP5CR
#8000
II ERROR PROGRAM
II
1/
Call MRCHK.
Execute error program if contents of
memory are incorrect.
Basic Operation
a.
IX is used as a pointer to data table.
b.
Sum of data is obtained by adding to ACCA.
c.
Data in data table is added to ACCA in sequence using index addressing
mode. Carry generation is ignored.
d.
If contents of IX equals the address following the last byte of data,
addition is terminated.
e.
LSD of addition result is compared with check sum stored beforehead.
f.
If these two strings of data are the same, bit C is set. If not the
same, bit C is cleared and MRCHK execution is terminated.
~HITACHI
1052
~
_p_r_o_g_r_a_m__M_o_d_U_l_e__N_am
__e__
:_C_HE
__C
__
K__S_UM
______
l...
~
LM
__
C_U_/M
__P_U_:__HD6303Y
HD
__6_3_0_l_Y_O_/____
~
lL_a_b_e
__
l_:__
MR
__
C_HK
________
.
~
Flowchart:
MRCHK
(( IX»)---( CHEND
:CHEND+l)
__ {store address in which check sum
is stored in data table.
--{ Clear register for addition.
_ _ { Load starting address of data table
into data table pointer.
(ACCA)+{IX)
---ACCA
- - { Add data to ACCA.
---[Increment data table pointer.
--{Test if addition of data is completed.
__ { Compare LSD of addition result with
check sum stored beforehand.
(ACCA) = ((IX) _ _ { If these two strings of data are not
the same, clear bit C.
l+Bit C
_ _ { If these two strings of data are the
same, set bit C.
MRCHK3
~HITACHI
1053
13.4
SUBROUTINE DESCRIPTION
MCULMPU: HD630lYO/
HD6303Y
Subroutine Name: DISPLAY LED
Function:
Turns LED on and off, and executes software timer for 0.5s intervals (blinking LED)
Basic Operation:
1.
2.
output condition of P60 is tested.
If Low, output IHigh to turn off LED.
If High, output Low to turn on LED.
Software timer for· 0.5s intervals is executed.
I Program Module Using This
Subroutine:
Flowchart.:
---{ Test bit 0 of port 6.
r----~~"""'Io.(+o
MRLEDI
..._ _
r--$-F-~--PL..6-D-TR-""'"
......,~
_ _...J - - - {
Output Low to turn on LED.
---{ Output High to turn off LED.
Execute software timer for 0.5s
intervals.
~HITACHI
1054
13.5
PROGRAM LISTING
00001
00002
00003
00004A
00005
00006A
00007
OOOOS
00009
00010
00011
00012
00013
00014
00015
00016
00017
0001S
00019
00020
00021
00022A
00023
00024A
00025A
00026A
00027A
0002SA
00029A
00030A
00031A
00032A
00033A
00034A
0003SA
00036A
00037A
0003SA
00039
00040
00041
00042
00043
00044
00045
00046
00047
0004S
00049
OOOSOA
OOOSlA
000S2A
000S3A
000S4A
OOOSSA
000S6A
000S7A
0040
0002
0040
0006
OOOS
0014
0017
0016
*************
RAM ALLOCATION
*
ORG
$40
RMS
2
A*
CHEND
*************
A*
P3DTR EQU
A
A
A
A
P4DDR
RPSCR
P6DTR
P6DDR
EQU
EQU
EQU
EQU
******************
Address of check sum
SMYBOL DEFINITIONS
$06
$OS
$14
$17
$16
**************
Port 3 data register
Port 4 data direction register
RAM/portS controL register
Port 6 data register
Port 6 data direction register
*
************************************************
*
*
MAIN PROGRAM : MRMN
*
*
**************************************************
*
ORG
$COOO
COOO
*
InitiaLize stack pointer
1I$13F
A
MRMN
LDS
013F
COOO SE
C003
COOS
C007
C009
COOB
COOD
COOF
COlI
C014
C016
COlS
COlA
C01C
COlE
S6
97
S6
97
S6
97
97
CE
SO
25
SO
20
SO
20
FF
A
OS
A
F4
A
14
A
01
A
17
A
16
(-\
SOOO A
OA C020
04 C01C
lD C037 MRMN1
FC C01S
19 C037 MRMN2
FE COlE PEND
LDAA
STAA
LDAA
STAA
LDAA
STAA
STAA
LDX
SSR
SCS
BSR
BRA
BSR
BRA
II$FF
P4DDR
II$F4
RPSCR
InitiaLize port4 DDR
InitiaLize RAM/portS controL REG
1101
InitiaLize port6
P6DTR
P6DDR
II$SOOO
MRCHI(
MRMN2
MRLED
MRMNI
MRLED
PEND
Load strating ADDR of data tabLe
Execute MRCHI<
Branch if bit C = 1
Execute LED
Branch MRMN1
Execute LED
End of program
*
************************************************
C020
C022
C024
C02S
C026
C027
C029
C02A
EC
DD
4F
OS
OS
AS
OS
9C
00
40
00
40
*
*
NAME : CHECK SUM (MRCHK)
*
*
**************************************************
**
ENTRY: IX (DATA TABLE STARTING ADDR) **
*
RETURNS: BIT C (C=l:TRUE.C=O:FALSE)
*
**************************************************
A MRCHK
A
LDD
STD
CLRA
INX
INX
A MRCHII<
>I<
>I~
7B
27
4F
97
20
86
97
CE
86
4A
26
09
26
39
01 17
MRLED
05 C041
BTST
BEQ
CLRA
17
A
STM
04 C045
BRI-)
01
A MRLED1 LDAA
17
A
STAA
03E8 A MRLE02 LOX
FA
A MRLED3 LOAA
MRLE04 DECA
FD C04A
BNE
OEX
F8 C048
BNE
RTS
0.P6DTR
MRLED1
P60TR
MRLE02
~SOl
P6DTR
"1000
H2S0
Test if LED on or off
Branch if on
Load data to turn on LED
Branch to LED2
Load data to turn off LED
Execute software timer for 0.55
MRLED4
MRLED3
>I<
*
*
VECTOR ADDRESSES
~,
*
'"
ORG
$FFEI~
>I<
COOO
COOO
COOO
COOO
COOO
COOO
COOO
COOO
COOO
COOO
COOO
FOB
FDB
FOB
FO[,
FOB
FOB
FOB
FDB
FDB
FDB
FOB
A
A
~)
A
A
A
A
A
A
A
A
*
~mMN
m02
~IR'1N
eMI
TRAP
MRI~N
SID
MRMN
MRMN
MRMN
MRMN
MRMN
MRMN
MRMN
TOI
OCI
ICI
IROlliSF
SWI
NMI
RES
Mfll1N
END
~HITACHI
1056
*
*
SECTION 14.
14.1
LOW POWER DISSIPATION MODE
HARDWARE DESCRIPTION
14.1.1
Function
Executes a test program for two low power dissipation mode:
sleep mode
and standby mode, and displays current mode and an 8-bit counter on
LEDs.
14.1.2
Microcomputer Operation
The HD6301YO executes standby mode by clearing standby flag of RAMI
port 5 control register during NMI interrupt routine; and executes
sleep mode by instruction SLP execution corresponding to switch input.
~e
MCU returns from standby mode by reset; returns from sleep mode by
timer 2 interrupt.
14.1.3
Peripheral Devices
Switches and LEDs:
SWl and SW2 are used to execute sleep mode and
standby mode, respectively, and LED1-LED3 indicate the current
operating state of the HD6301YO.
are shown in table 14-1.
Switch and LED setting for each mode
In addition, LED4-LEDll are used to display
an 8-bit counter during sleep mode.
Table 14-1.
Test Mode
Switch Setting and Display for Each Mode
Switch Setting
Display
SWl
SW2
LEDl
LED2
LED3
Active Mode
OFF
OFF
OFF
OFF
ON
Sleep Mode
ON
OFF
OFF
ON
OFF
Standby Mode
OFF
ON
ON
OFF
ON (Note)
I
Note:
In standby mode, LEDl is displayed after returned from standby mode.
~HITACHI
1057
14.1.4
Circuit Diagram
Low power dissipation mode circuit is shown in figure 14-1.
+5V
Mev
HD6a01YO
4 MP o
5
MP I
aa
Vee
7
STBY
f.
4MHz ,r.
c::::J
8
LED1 2000
PI
LED2 2000
XTAL
EXTAL
22pF
\EDU ".0
+5V
PS7
51
+5V
6
RES
1pF
4.7kO
SW8
Vss
42
PM
8
SW2
Low Power Dissipation Mode Circuit
~HITACHI
1058
~~
.4.7kO
Vss
NMI
Figure 14-1.
26
Pin Functions
14.1.5
Pin functions at the interface between the HD6301YO and the switches
and LEDs are shown in table 14-1.
Table 14-1.
Pin Functions
Pin Name
(HD6301YO)
Input/
Output
Active Level
(High or Low)
P 10
Output
High
P 12
Output
P 13
Pin Name
(SW, LED)
Program
Label
Drives LED indicating active
mode operation.
LED3
P1DTR
High
Drives LED after
exiting standby
mode.
LED2
Output
High
Drives LED indicating sleep
mode.
LEDl
P 30
Output
High
LED4
P 31
Output
High
Drives LEDs used
as 8-bit binary
counter.
P 32
Output
High
LED6
P33
Output
High
LED7
P
Output
High
LED8
P 35
Output
High
LED9
P 36
Output
Hi<,Jh
LED10
P 37
Output
High
LEDll
P 61
Input
Low
Sleep mode switch
input
SW1
NMi
Input
Low
Standby mode
swi tch input
Sw2
RES
Input
Low
Standby mode reset SW3
input
34
Function
P3DTR
LED5
P6DTR
I
~HITACHI
1059
14.1.6
Hardware Operation
a.
Standby mode
The timing chart for entering and exiting standby mode by the STBY
flag is shown in figure 14-2.
'LS
RES
,
I
,,
I
Clear
STBY flag
,
,,
,
t-----
Standby mode
'Restart
(Active model
Oscillation
stabilization
time
Figure 14-2.
b.
Timing Chart for Standby Mode
Sleep mode
The timing chart for sleep mode is shown in figure 14-3.
OFF - - - - - ,
Sleep mode switch
ON
----JI----------!
,
Executing---------;
Program execution
Sleep
--------'--I
,
,,
I
-
I
Timer interrupt timing
Figure 14-3.
,,,
'---I
I
I
I
I
I
Timing Chart for Sleep Mode
~HITACHI
1060
,,
,
'--I
'--
14.2
SOFTWARE DESCRIPTION
14.2.1
Program Module Configuration
The program module configuration for low power dissipation mode is
shown in figure 14-4.
LWPMN
MAIN
PROGRAM
LWPSP
I
I
LWPST
L.:
14.2.2
I
STANDBY
MODE
SLEEP MODE
Figure 14-4.
l..!
L:
Program Module Configuration
Program Module Functions
Program module functions are summarized in table 14-2.
Table 14-2.
Program Module Functions
No.
Program Module Name
Label
Function
o
MAIN PROGRAM
LWPMN
Executes low power dissipation mode.
1
SLEEP MODE
LWPSP
Tests sleep mode operation.
2
STANDBY MODE
LWPST
Tests standby mode operation.
~HITACHI
1061
14.2.3
Program Module Process Flow (Main Program)
The flowchart in figure 14-5 shows the procedure for performing low
power dissipation mode, using the program module in figure 14-4.
Main Program
---[
---{
Test if power is re-supplied during standby
mode execution.
Test if reset from standby mode or power
ON.
Turn on LED indicating standby mode and
active mode.
value of stack pointer before entering
----[ Load
standby mode.
---{ Turn on LED indicating active mode.
---{ Turn off LEDs for binary counter.
---{ Initialize stack pointer.
---{
Select ports land 3 as output.
----[
Initialize timer control status register 3.
----[ Enable
~---{
interrupts.
Clear RAM.
---{
Test for sleep mode request.
---{
Enter sleep mode.
---{
Activate LEDs for binary counter.
NMl Interrupt Routine
----[ Enter standby mode.
Figure 14-5.
Program Module Flowchart
~HITACHI
1062
14.3
PROGRAM MODULE DESCRIPTION
Program Module Name: SLEEP MODE
Label: LWPSP
MCU/MPU:HD630lYO
Function:
Tests sleep mode operation.
Arguments:
Changes in CPU
Specifications:
Registers and Flags:
None
ACCD
ACCA ACCB
x
•
ROM (Bytes) : 10
RAM (Bytes) : 0
Stack (Bytes) : 0
IX
•
No . of cycles: 19
Reentrant: No
•
x
:
C
V
•
x
Z
N
x
x
I
H
•
•
Relocatable: No
Interrupt OK?: Yes
Not affected
Undefined
Resul t
Description:
1.
2.
Function Details
a.
LWPSP has no arguments.
b.
Sleep mode is entered by switch 1 input.
c.
LWPSP calls neither the program modules nor subroutines.
I
User Note
The following procedure must be executed before LWPSP execution.
a.
Select DDR of port 1 as output.
Specifications Notes:
N/A
~HITACHI
1063
Program Module Name:
~M_C_U_/_M_P_U_:
SLEEP MODE
__HD
__6_3_0_1_Y_O____
~
LIL_a_b_e_l_:__L_WP
__S_P______
Description:
3.
RAM Allocation
RAM is not used during LWPSP execution.
4.
Sample Application
II
5.
WAA
STAA
WAA
STAA
#$FF
P1DTR
#$01
P1DDR
JSR
LWPSP
t
----- Initialize port 1.
II
----- Call LWPSP.
Basic Operation
a.
The LED indicating sleep mode is turned on and sleep mode is entered
by the sleep instruction(SLP).
b.
Timer 2 interrupt executes return from sleep mode, and the LED
indicating sleep mode is turned off.
~HITACHI
1064
~
Program Module Name: SLEEP MODE
MCU/MPU: HD630lYO
I~
LWPSP
Flowchart:
------[
Turn off LED indicating active mode, and turn
on LED indicating sleep mode.
------[
Enter sleep mode.
-----[
Turn off LED indicating sleep mode, and turn
on LED indicating active mode.
I
~HITACHI
1065
Program Module Name:
MCU/MPU: HD6301YO
STANDBY MODE
Label:
LWPST
Function:
Tests standby mode operation.
Arguments:
Changes in CPU
Storage
Location
Contents
No. of
Bytes
Specifications:
Registers and Flags:
ACCD
ACCA ACCB
•
•
Entry
ROM (Bytes) :
16
RAM (Bytes) :
0
Stack (Bytes) : 0
IX
•
No. of cycles: 31
Reentrant:
C
•
Returns
Value of
stack
EO inter
STACK
2
Z
x
N
x
1
I
H
•
•
(RAM)
LWPST
NMIF
execution (RAM)
flag
V
x
•
x
t
:
No
Relocatable:
No
Interrupt OK?:
Yes
Not affected
Undefined
Result
Description:
1.
Function Details
a.
Argument details
STACK(RAM): Value of stack pointer when NMI interrupt is executed.
NMIF(RAM):
b.
Used as flag indicating LWPST execution, i.e., standby
mode.
Example of LWPST execution is shown in figure 14-6. Contents of CPU
registers, before NMI interrupt by switch 2 input, are saved and LWPST
is executed. Value of stack pointer is saved in STACK(RAM) and $01 is
stored in NMIF(RAM).
Specifications Notes:
N/A
~HITACHI
1066
I
L..p_r_o_g_r_aIlI_M_od_u_le_N_aIlI_e_._._S_T_AND_B_:'i_M_O_D_E_---' LM_C_U_I_M_P_U_:__
HD_6_30_l_Y_0_ _----I Label, LIiPST
Description:
CD Input { SW2 ON.
RAM
$129
(i)
Result
$180
B1S
STt~1)1 0
($129)
C C R
ACCB
ACCA
I XH
I XL
P C H
P C L
STACK
:
b7
~m~1
Figure 14-6.
c.
2.
bO
STACK+1
:
NMIF
0
:
9
I
bO
I
Example of LWPST Execution
LWPST calls neither the program modules nor subroutines.
User Notes
The following procedure must be executed before LWPST execution.
a.
3.
Initialize stack pointer since NMI interrupt is executed.
RAM Allocation
RAM
Label
g
b7
STACK
NMIF
4.
Description
I
bO
} Value of stack pointer
rFlag indicating LWPST execution.
Sample Application
IDS
#$130
----- Initialize stack pointer.
~HITACHI
1067
Program Module Name:
STANDBY MODE
L-M_C~U_I_M_P_U_:_HD_6_3_0_l_Y_O ~ I
__
Label, LWPST
Description:
5.
Basic Operation
a.
Set flag NMIF(RAM) indicating LWPST execution.
b.
Save stack pointer in STACK(RAM).
c.
Set standby power bit of RAM/port 5 control register.
d.
Clear RAM enable bit of RAM/port 5 control register and disable
RAM access to protect RAM data.
e.
Clear standby flag and enter standby mode.
~HITACHI
1068
MCU/MPU: HD630lYO
Program Module Name: STANDBY MODE
1Lobel, LWPST
Flowchart:
L---r----' - --{
Set flag indicating LWPST execution.
Save value of stack pointer in STACK
L..---,-------..J - - - [
L---r-o-----I ---{
L..---,-------..J - - - {
(RAM) •
Set standby power bit.
Disable RAM access I moved this to
"Basic Operation".
Clear standby flag and execute standby
L - - - r - - - - ' - - - [ mode.
~HITACHI
1069
14 . 4
SUBROUTINE DESCRIPTION
Subroutine Name:
INCREMENT COUNTER
MCULMPU: HD6301YO
[ L.bel,
LWPCN
Function:
Increment counter for LED binary display.
Basic Operation:
1. This subroutine is executed at every 32ms interrupt.
2.
3.
Two counters are used to count one second.
LED counter is incremented at every interrupt.
l-second counter is counted up.
When this counter is "31"
Program Module Using This Subroutine:
Flowchart:
- - - - - [ Clear interrupt request flag.
Count up and turn on LED binary
counter every second during sleep
mode execution.
- - - - - - [ Increment l-second counter.
L------=====::r----I
~HITACHI
1070
I
14.5
PROGRAM LISTING
00001
00002
00003
00004A
00005
00006A
00007A
00008A
00009A
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029A
00030
00031A
00032A
00033A
00034A
00035A
00036A
00037A
00038A
00039A
00040A
00041A
00042A
00043A
00044A
00045A
00046A
00047A
00048A
00049A
00050A
00051A
00052A
00053A
00054A
00055A
00056A
00057A
*
******* RAM ALLOCATION **********************
0040
0040
0041
0042
0043
0001
0001
0001
0002
*
A*
CNTRD
A CNTRI
A NMIF
A STACK
*.
ORG
$40
RMB
RMB
1
1
1
2
R~lB
RMB
I-second counter
LED counter
LWPST execution fLag
VaLue of stack pointer
******* SYMBOL DEFINItIONS ******************
0000
0002
0004
0006
0016
0017
OOlB
OOlC
001D
0014
A*
P1DDR
A
A
A
A
A
A
A
A
A
P1DTR
P3DDR
P3DTR
P6DDR
P6DTR
TCSR3
TCONR
T2CNT
RP5CR
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$00
$02
$04
$06
$16
$17
$lB
$IC
$lD
$14
Portl data direction register
Portl data register
Port3 data direction register
Port3 data register
Port6 data direction register
Port6 data register
Timer controL register3
Time constant register
Timer2 up counter
RAM/portS controL register
******************************************>1<****
*>I<
MAIN PROGRAM : LWPMN
>I<
*
***>1<***>1<*****************************************
COOO
COOO
C003
COOS
C007
C009
COOB
COOD
COlO
C012
C015
C017
C019
C01B
COlD
COIF
C021
C023
C025
C027
C028
C029
C02B
C02D
C02F
C032
C034
C037
7B
26
86
97
86
97
8E
20
7B
27
86
97
9E
86
97
97
86
97
OE
4F
97
97
97
7B
27
BD
20
*
ORG
*LWPMN BTST
80 14
OD C012
FE
A LWPMN1
02
A
FF
A
06
A
013F A
DB COlD
01 42
LWPMN2
EE COOS
F6
A
02
A
43
A
01
A LWPMN3
00
A
04
A
52
A
1B
A
BNE
LDAA
STAA
LDAA
STAA
LDS
BRA
BTST
BEQ
LDAA
STAA
LDS
LDI4A
STAA
STAA
LDAA
STAA
CLI
CLRA
A
STAA
42
STAA
40
A
STAA
A
41
LWPMN4 BTST
02 17
BEQ
OS C039
C040 A
JSR
BRA.
F6 C02F
$COOO
7.RP5CR
LWPMN2
Ii$FE
PlDTR
Ii$FF
P3DTR
1i$13F
LWPMN3
O.NMIF
LWPt1N1
Ii$F6
PlDTR
STACI<
11$01
P1DDR
P3DDR
Ii$S2
TCSR3
NMIF
CNTRD
CNTRI
1.P6DTR
LWPMNS
LWPSP
LWPMN4
Test standby power bit
Turn on active mode LED
InitiaLize stack pointer
Test if standby mode execution
Turn on standby mode LED
Load stack pointer
SeLect pdrts 1 and 3 as output
Initialize TCSR3
EnabLe interrupts
CLear RAM
Test if sLeep mode execution
Execute sLeep mode
~HITACHI
1071
00058A
00059A
00060A
00061A
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072A
00073A
00074A
00075A
00076A
00077A
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089A
00090A
00091A
00092A
00093A
00094A
00095
00096
00097
00098
00099
OOlOOA
00101A
00102A
00103A
00104A
00105A
00106A
00107A
00108A
00109A
00110
00111
00112
00113
00114
C039
C03B
C03C
C03E
CNTRD
96 40
A LWPMNs LDAA
43
COMA
Turn on LED binary counter
97 06
A
STAA
P3DTR
20 EF C02F
BRA
LWPMN4
*******************************************
*
*
NAME : LWPSP (SLEEP MODE)
*
*
*
********************************************
*
C040
C042
C044
C045
C047
C049
C04A
C04D
C04F
COs2
COss
COs8
86
97
1A
86
97
39
72
9F
72
71
71
20
FB
02
A LWPSP
A
LDAA
n$FB
STAA
P1DTR
Turn on sLeep mode LED
Execute sLeep mode
SLP
n$FE
A
LDAA
Turn on active mode LED
PlDTR
A
STAA
RTS
********************************************
FE
02
01
43
80
FD
DF
FE
*
ENTER : NOTHING
*
*
'RETURNS: NOTHING
*
*
*********************************************
42
*
*
NAME : LWPST (STANDBY MODE)
*
*
*
*
********************************************
*
ENTER
NOTHING
**
*
RETURNS : STACK (STACK POINTER)
*
*
NMIF (LWPST EXECUTION FLAG)*
*
*
*
********************************************
LWPST BSET
O.NMIF
Set LWPST execution fLag
STS
STACK
Store stacK pointer
A
14
BSET
7.RPsCR Set standby power bit
14
BCLR
1.RPsCR CLear RAM enabLe bit
14
BCLR
s.RPsCR CLear standby fLag
CO 58 LWPST1 BRA
LWPST1
*******************************************
*
COsA
COsD
C060
C062
C064
C066
C067
C068
C06A
C06D
71
7C
96
81
27
3B
4F
97
7C
20
*
NAME : LWPCN (INCREMENT COUNTER)
*
*
*********************************************
LWPCN
7F 1B
0041 A
41
A
IF
A
01 C067
LWPCN2
LWPCN1
41
A
0040 A
F7 C066
BCLR
INC
LDAA
CMPA
BEQ
RTI
CLRA
STAA
INC
BRA
7.TCSR3
CNTRI
CNTRI
1131
LWPCNI
CLear Interrupt request fLag
Increment LED counter
CNTRI
CNTRD
LWPCN2
Turn on LED binary counter
Increment I-second counter
********************************************
*
*
*
VECTOR ADDRESSES
~HITACHI
1072
*
*
*
00115
00116
00117A
00118A
00119A
00120A
00121A
00122A
00123A
00124A
00125A
00126A
00127A
00128A
00129
00130
FFEA
FFEA
FFEC
FFEE
FFFO
FFF2
FFF4
FFF6
FFF8
FFFA
FFFC
FFFE
*******************************************
*
COOO
COs A
COOO
COOO
COOO
COOO
COOO
COOO
COOO
C04A
COOO
ORG
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
A
A
A
A
A
A
A
A
A
A
A
*
$FFEA
LWPMN
LWPCN
LWPMN
LloJPMN
LWPMN
LWPMN
LWPMN
LWPMN
LWPMN
LWPST
LWPMN
lRQ2
CMI
TRAP
SIO
TOl
DCI
ICI
IRQI/ISF
SWI
NMI
RES
ENO
I
~HITACHI
1073
SECTION 15.
15.1
HA1835P CONTROL AND ERROR DETECTION
HARDWARE DESCRIPTION
15.1.1
Function
Executes test program of MCU runaway error and trap error detection
(operation code error and address error), and displays result on LED.
15.1.2
Microcomputer Operation
The HD6301YO sends pulse to the HA1835P voltage regulator controlling
bit 0 of port 7 and detects watchdog timer error.
In addition,
detects operation code error and address error using the trap
function.
15.1.3
Peripheral Devices
Switches and LEDS:
Switches SWl-SW3 are used to indicate the above
three errors for testing.
The generation of those errors and
subsequent error handling is indicated by LED1-LED3.
The
relationship between switch settings and LED display is shown in
table 15-1.
Table 15-1.
SWitch Setting and Display for Each Mode
Switch Setting
Display
SWl
SW2
SW3
LEDl
LED2
LED3
Normal Operation
OFF
OFF
OFF
OFF
OFF
OFF
Watchdog Timer Error
ON
OFF
OFF
ON
OFF
OFF
Operation Code Error
OFF
ON
OFF
OFF
ON
OFF
Address Trap Error
OFF
OFF
ON
OFF
OFF
ON
Test Mode
@HITACHI
1074
15.1.4
Circuit Diagram
HA183SP and Error Detection Circuit is shown in figure 15-1.
f_o
22pF
22pF
MCU
HD6301YO
2
XTAL
3 EXTAL
+5V
SW1 4.7kn
I'
17
18
:r-
P so
HV
HDH05/
PSt
P n 62
4o.7kn
200.0
HV
LED!
IO
P'2
P 72
61
42
LE!}
Vss
Vss
Figure 15-1.
#
P'3
60
200.0
200.0
LED8
HAI83SP-and Error Detection Circuit
I
~HITACHI
1075
15.1.5
Pin Functions
Pin functions at the interface between the HD6301YO and switches, LEDs,
and the HA183sP are shown in table 15-2.
Table 15-2.
Pin Functions
Pin Name
(SW, LED,
HA183sP)
Program
Label
Watchdog timer error
generation switch
SW1
PsDTR
Low
Operation code trap
error generation switch
SW2
Low
Address trap error
generation switch
SW3
Outputs pulse to CLK
pin of HA183sP
CLK
High
Drives LED indicating
watchdog timer error
generation
LED 1
Output
High
Drives LED indicating
operation code trap
error generation
LED2
P 73
Output
High
Drives LED indicating
address trap error
generation
LED3
REs'
Input
Low
Inputs reset.
RES
Pin Name
(HD6301YO)
Input/
Output
Active Level
(High or Low)
Pst
Input
Low
PSI
Input
P S2
Input
P 70
Output
P 7l
Output
P 72
15.1.6
Function
P7DTR
Hardware Operation
The timing chart for the watchdog timer function using the HAl83sP is
shown in figure 15-2.
HAl835>
pin
eLK
n~:
e\,
J't~
="':1
JUUUI
I
~
180m·l ~
Automatic
reset signal
watchdog timer
error generation
SW input
----------------~
Figure 15-2.
Timing Chart for Watchdog Timer
~HITACHI
1076
I
15.2
SOFTWARE DESCRIPTION
15.2.1
Program Module Configuration
The program module configuration for the HA1835P control and error
detection function is shown in figure 15-3.
FSMN
MAIN
PROGRAM
~
I
FSWD
I
FSOP
l!..
DETECT
WATCHDOG
TIMER ERROR
FSADDR
L:..
I
DETECT ~
ADDRESS
ERROR
DETECT
OPERATION
CODE ERROR
Figure 15-3.
15.2.2
I
FSTRP
I
RETURN
~
FROM ERROR
BY TRAP
Program Module Configuration
Program Module Functions
Program module functions are summarized in table 15-3.
Table 15-3.
Program Module Functions
No.
Program Module Name
Label
Functions
0
MAIN PROGRAM
FSMN
Perform HA1835p control and error
detection.
1
DETECT WATCHDOG
TIMER ERROR
FSWD
2
DETECT OPERATION
CODE ERROR
FSOP
3
DETECT ADDRESS ERROR FSADDR
Fetch instruction from other than
ROM, RAM and check address error.
4
RETURN FROM ERROR
BY TRAP
Return from operation code error and
address error.
Stop pulse output to HA1835p and check
input.
RES
FSTRP
Execute undefined operation code and
check operation code error generation.
~HITACHI
1077
I
15.2.3
Program Module Process Flow (Main Program)
The flowchart in figure 15-4 demonstrates the procedure for detecting
watchdog timer error, operation code error, and address error by SWl-3,
using the program module in figure 15-3.
Main Program
L-______, -______
~
-----{rnitialize stack pointer.
SW1: ON, detect watchdog timer error.
---- { SW1: OFF, output pulse having a 20ms
cycle.
SW2' ON, detect operation code error .
[ SW2; OFF, cci nothing.
....______, -______..u - - - - -
.....- - - r - - - - " "
SW3: ON, detect address error.
Co nothing •
- --- { : sw 3: OFF,
Trap Routine
~~~
__,-______'"
____ [ Return from operation code error and
address error.
Figure 15-4.
Program Module Flowchart
$
1078
HITACHI
15.3
PROGRAM MODULE DESCRIPTION
Label: FSWD
MCU/MPU: HD630lYO/
HD6303Y
Program Module Name: DETECT WATCHDOG
TIMER ERROR
Function:
When SWI is ON, detect watchdog timer error.
When SWI is OFF, output pulse to bit 0 of port 7 every 20ms.
Arguments:
None
Changes in CPU
Specifications:
Registers and Flags:
ACCD
ACCA ACCB
ROM (Bytes):
64
I
RAM (Bytes):
2
x
•
Stack (Bytes): 0
IX
•
No. of cycles: 10041
Reentrant:
•
x
t
:
C
V
x
x
Z
N
x
x
I
H
•
•
No
Relocatable:
No
Interrupt OK?: Yes
Not affected
Undefined
Result
Description:
1.
Function Details
ON
SWl OFF
a.
FSWD has no arguments.
b.
PYa
Example of FSWD execution is shown
in figure 15-5. When SWI is OFF,
output pulse to bit 0 of port 7
RES
ON
every 20ms.
LEDlOFF
When SWl is ON, stop pulse output
and turn on LEDI after reset.
When SWI is OFF again, output pulse
to bit 0 of port 7 and turn off LEDI.
Figure 15-5.
"LExample of FSWD
Execution
Specifications Notes:
~HITACHI
1079
I
Program Module Name: DETECT WATCHDOG
TIMER ERROR
MCU/MPU:
HD6301YO/
HD6303Y
IL..."
FSWD
Description:
c.
2.
FSWD calls neither the program modules nor subroutines.
User Notes
Use SWI independently of other switches.
3.
RAM Allocation
Label
RAM
b7
4.
bO
~
f
CMRAM
} Comparison data for watchdog timer error
detection.
Sample Application
FSWD 1/
5.
Description
----- Call FSWD.
Basic Operation
a.
b.
When
S~l
is ON, the following operations are performed.
i.
After power ON, data is stored in CMRAM(RAM) , an infinite loop is
executed, and pulse output to the HA1835P is stop.
ii.
The HAl835P determines this status as system runaway and sets RES
pin to LOW.
iii.
After reset, data in CMRAM(RAM) is compared with data previously
stored. If these are the same, LEDI is turned on.
When SWI is OFF, 10 ms software timer is executed and the output to bit
o of port 7 is inversed.
~HITACHI
1080
Program Module Name:
DETECT WATCHDOG
TIMER ERROR
MCU/MPU:
HD6301YO/
HD6303Y
I
Label,
FSWD
Flowchart:
---{ Teet i f SWI ie ON.
'----""t'"----' - - - { Turn off LEDl.
___ {
Initialize RAM for comparison
data.
'----""t'"----' - - - -
Execute 10 ms software timer.
~--~--~
'----r-----i
----[ Teet if bit 0 of port 7 ie 1.
I
'----""t'"--....J - - - { Output High to bit 0 of port 7.
- - - { Output Lew to bit 0 of port 7.
2
FSWD3
R T S
~HITACHI
1081
Program Module Name: DETEcr WATCHDOG
TIMER ERROR
MCU/MPU: BD6301YO/
BD6303Y
I~
FSWD
( CMRAM)#$ 5 5
Test if return from watchdog timer
error.
(CMRAM+l)#$
(CMRAMt 1) =$AA
Store comparison data which tests
------[ return from watchdog timer error.
____ { Turn off LED I to indicate watchdog
timer error handled.
~HITACHI
1082
MCU/MPU:
Program Module Name: DETECT
OPERATION CODE
ERROR
Label: FSOP
HD6301YO/
HD6303Y
Function:
When SW2 is ON, execute an undefined operation code and generate an operation
code error.
If operation code error is detected, turn 'on LED2. When Sw2 is
turned OFF, turn off LED2.
Arguments:
Storage
Location
Contents
Specifications:
Changes in CPU
No. of
Bytes
Registers and Flags:
ACCD
ACCA ACCB
x
x
Entry
ROM (Bytes) : 27
RAM
(Bytes) : 1
Stack (Bytes) : 0
IX
x
No. of cycles: 85
Reentrant: No
Returns
Error
mode
TRMD
(RAM)
1
•
x
:
C
V
•
x
Z
x
N
x
I
H
•
•
Relocatab1e: No
Interrupt OK?:
Yes
Not affected
Undefined
Resul t
Description:
1.
Function Details
a.
Argument details
TRMD(RAM): Contains data indicating
operation code error.
SW2 OFF - - ,
r-ON
L---..J
b.
Example of FSOP execution is shown
in figure 15-6. When operation
error is generated, turn on LED2.
c.
FSOP calls an other program module
as shown in Table 15-4.
I
ON~
LED20FF~
-
Operation code
error generation
Figure 15-6.
Example of
FSOP Execution
Specifications Notes:
"No. of cycles" in "Specifications" indicates the number of cycles required to
handle an operation code error.
~HITACHI
1083
Program Module Name: DETECT
OPERATION CODE
ERROR
MCU/MPU: ED6301YO/
ED6303Y
ILabelo FSOF
Description:
Table 15-4.
2.
Program Module Called by FSOP
Program Module Name
Label
Function
RETURN FROM ERROR
BY TRAP
FSTRP
Return from operation code error or address
error.
User Notes
Use SW2 independentry.
3.
RAM Allocation
RAM
Label
bO
b7
} Data indicating operation code error.
T.RMD
4.
Sample Application
1/ JSR
5.
Description
FSOP
II
----- Call FSOP.
Basic Operation
a.
When SW2 is ON, execute operation as follows;
i.
ii.
iii.
b.
TRMD(RAM) is cleared to indicate operation code error.
Undefined operation code "$87" is executed.
LED2 is turned on after returning from trap interrupts.
When sw2 is turned OFF, turn off LED2.
~HITACHI
1084
MCU/MPU: HD6301YO/
HD6303Y
Program Module Name: DETECT
OPERATION CODE
ERROR
I
Label, FSOP
Flowchart:
---{
Test if SW2 is ON.
TRMD (RAM) and indicate
---{ Clear
operation code error.
~-----r----~ ---{ Execute
undefined operation code.
interrupts are generated.
{ Turn on LED2 to indicate operation
code error generation.
Test if SW2 is OFF.
L.----,:::===~
--{ Turn off LED2.
I
~HITACHI
1085
Label:
MCU/MPU: HD6301YO/
HD6303Y
Program Module Name: DETECT ADDRESS
ERROR
FSADDR
Function:
When SW3 is ON, jump to address for I/O ports and generate address error.
If address error is detected, turn on LED3. When SW3 is turned OFF, turn off LED3.
Arguments:
Storage
Location
Contents
Specifications:
Changes in CPU
No. of
Bytes
Registers and Flags:
ACCD
ACCA ACCB
Entry
ROM (Bytes) : 30
•
x
RAM (Bytes) :
1
Stack (Bytes) : 0
IX
•
No • of cycles: 78
Reentrant: No
Error
Returns mode
TRMD
1
(RAM)
•
x
t
C
V
•
x
z
N
x
x
I
H
•
•
Relocatable: No
Interrupt OK?:
Yes
Not affected
Undefined
Result
Description:
1.
Function Details
a.
SW3
Argument details
TRMD(RAM): Contains data indicating
address error.
b.
OFF - - ,
rON
L--.....J
I I-
ON
LED8 OFF ----,
Address error
generation
Example of FSADDR execution is
shown in figure 15-7. When
address error is generated,
turn on LED3.
Figure 15-7.
Example of FSADDR
Execution
Specifications Notes:
"No. of cycles" in "Specifications" indicates the number of cycles required
when address error is generated.
~HITACHI
1086
Program Module Name:
DETECT ADDRESS
ERROR
M_C_U_/_M_P_U_:_HD
__6_3_0_1_YO_/
____
HD6303Y
L_
~IL_L_a_b_e_l_:
.
__F_SAD
__D_R____
~
Description:
c.
FSADDR calls an other program module as shown in Table 15-5.
Table 15-5.
2.
Program Module Called in FSADDR
Program Module Name
Label
Functions
RETURN FROM ERROR
BY TRAP
FSADDR
Return from operation code error or
address error.
User Notes
Use SW3 independently of other switches.
3.
RAM
Allocation
Label
bO
b7
} Data indicating address error.
TRMD
4.
Sample Application
II JSR
5.
Description
RAM
FSADDR
II
----- Call FSADDR.
Basic Operation
a.
When SW3 is ON, execute operations as follows;
1.
i1.
iii.
b.
Store "1" in TRMD(RAM) to indicate address error.
Execute "JMP 3" to jump to port 3 data register.
I
Turn on LED3 after returning from trap interrupts.
When SW3 is turned OFF, turn off LED3.
~HITACHI
1087
S_S~
_p_r_o_g_r_a_m__
M_od__
U_le__N_am
__e__
: __
D_E_TE_C_T
__D_RE
__
ERROR__AD
'-
~
'-M_C_U_/_M_P_U_:___
HD_6__
30_1_Y_O_/____ I'-L_a_b_e_l_:___F_S_AD_D_R
______
HD6303Y.
Flowchart:
(2.P5DTR)=1
----[ Test if Sw3 is ON.
"1" in TRMD (RAM)
---{ Store
indicate address error.
----{ Jump to address $3.
(TRMD) =1
and
____ { Test if trap interrupts are
generated.
_____ [ Turn on LED3 to indicate address
error generation.
if sw3 is OFF.
--{ Turn off LED3.
$HITACHI
1088
~
MCU/MPU: HD6301YOj
HD6303Y
Program Module Name: RETURN FROM
ERROR BY TRAP
Label:
FSTRP
Function:
When operation code error or address error is generated, return to the program
where interrupts are generated by controlling the program counter.
Arguments:
Changes in CPU
Storage
Location
Contents
Entry Error Mode
TRMD
No. of
Bytes
Speci fica tions:
Registers and Flags:
ACCD
ACCA ACCB
1
x
x
(RAM)
ROM (Bytes): 30
RAM (Bytes): 1
Stack (Bytes): 0
IX
No. of cycles: 4S
x
Reentrant: No
Returns
•
x :
c
v
x
x
z
N
x
x
I
H
•
•
Relocatable:
No
Interrupt OK?:
No
Not affected
Undefined
Result
Description:
1.
Function Details
a.
Argument details
TRMD(RAM): Holds data indicating what error is generated.
Table lS-6 shows flag functions.
b.
I
Example of FSTRP execution is shown in figure lS-S. If entry
argument is as shown in parte!) of figure lS-S, data for program
counter in stack area is changed as shown in part@ of figure lS-S.
Specifications Notes:
"No of cycles" in "Specifications" indicates the number of cycles
required when operation code error is generated.
"HITACHI
1089
Program Module Name: RETURN FROM
ERROR BY TRAP
MCU/MPU:
HD630lYO/
HD6303Y
Description:
\
Table 15-6.
Flag Functions
Label
bit 0
Function
TRMD
o
Execute routine for operation code error
generation.
1
Execute routine for address error generation.
I<
RAM ALLOCATION
****
>I<
0040
ORG
$40
RMB
RMB
2
************************
>I<
0002
0001
0040
0042
A CMRAM
A TRMD
1
Data for comparing
En'or' mode
>I<
001B
0014
0015
0020
A
A
A
A
****
>I<
SYMBOL DEFINITION
P7DTR
RP5CR
P5DTR
P5DDR
EQU
EQU
EQU
EQU
$lB
$14
$15
$20
Port 7 data register
RAM/PORTS control register
Port 5 data register
Port 5 data direction register
*********~(**************************************
>I<
>I<
>I<
MAIN PROGRAM : FSMN
>I<
>I<
>I<
************************************************
>I<
ORG
COOO
$COOO
>I<
COOO
C003
COOS
C007
C009
8E
BD
BD
80
20
Initialize stack pointer
1I$13F
013F A FSMN
LOS
Check watchdog timer error
FS~ID
06 COOB FSMNI BSR
Check operation error
43 C04A
BSR
FSOP
Check address error
FSADDR
SA C063
BSR
FSMNI
FB C003
BRA
************************************************
>I<
>I<
>I<
NAME: FSWD (DETECT WATCHDOG TIMER ERROR)
>I<
>I<
>I<
**********************************~(******~*****M
>I<
>I<
>I<
>I<
ENTRY
: NOTHING
RETURNS : NOTHING
7B
27
71
7F
7F
CC
83
26
7B
27
71
20
72
39
B6
91
26
B6
91
26
01 15
IF C02F
FD 1B
0040 A
0041 A
06B2 A
0001 A
FB COIC
01 1B
05 C02B
FE 18
03 C02E
01 18
A
55
40
A
DB C040
AA
A
41
A
05 C040
*
>I<
>I<
COOB
CODE
COlO
COl3
C016
C019
COIC
COIF
C021
C024
C026
C029
C02B
C02E
C02F
C031
C033
C035
C037
C039
>I<
************************************************
FSWD
BTST
0.P5DTR Test if SWl=ON
BEQ
FSWD4
Branch if SWl=ON
BCLR
1.P7DTR Turn off LEDI
CLR
CMRAM
Clear CMRAM
CLR
CMRAM+l
Execute 10 ms software timer
LDD
1I$6B2
FSWDI SUBD
III
BNE
FSWDI
BTST
0.P7DTR Test if P70 =
BEQ
FSWD2
Branch if P70
0
BCLR
0.P7DTR Output Low to P70
BRA
FSWD3
0.P7DTR Output High to P70
FSWD2 BSET
FSWD3 RTS
11$55
Test if CMRAM=$55
FSWD4 LDAA
CMPA
CMRAM
Branch if not equal
BNE
FSWD5
Test if CMRAM+l=$AA
LDAA
liMA
CMRAM+l
CMPA
Branch if not equal
FSWD5
BNE
I
~HITACHI
1093
00058A
00059A
00060A
00061A
00062A
00063A
00064A
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074
00075A
00076A
00077A
00078A
00079A
00080A
00081A
00082A
00083A
00084A
00085A
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096A
00097A
00098A
00099A
00100A
00101A
00102A
00103A
00104A
00105A
00106A
00107A
00108
00109
00110
00111
00112
00113
00114
C03B
C03E
C040
C042
C044
C046
C048
C04A
C04D
C04F
C052
C053
C055
C057
C05A
C05D
C05F
C062
72
20
86
97
86
97
20
02 18
EE C02E
55
A FSWD5
A
40
AA
A
41
A
FE C048 FSWD6
BSET
BRA
LDAA
STAA
LDAA
STAA
BRA
1.P7DTR
FSWD3
11$55
CMRAM
II$AA
CMRAM+1
FSWD6
Turn on LED1
InitiaLize CMRAM:CMRAM+1
************************************************
7B 02 15
26 10 CO SF
7F 0042 A
87
A
96 42
A
27 03 C05A
72 04 18
7B 02 15
27 03 C062
71 FB 18
39
* NAME : FSOP (DETECT OPERATION CODE ERROR) *
*
*
**************************************************
*
*
ENTRY
: NOTHING
*
*
RETURNS : TRMD (ERROR MODE)
*
*
*
*
************************************************
FSOP
FSOP1
FSOP2
FSOP3
BTST
BNE
CLR
FCB
LDAA
BEQ
BSET
BTST
BEQ
BCLR
RTS
1.P5DTR
FSOP2
TRMD
$87
TRMD
FSOP1
2.P7DTR
1.P5DTR
FSOP3
2.P7DTR
Test if SW2=ON
Branch if SW2=ON
CLear TRMD
Execut undefined op-code
Test if TRMD=l?
Branch if TRMD=O
Turn on LED2
Test if SW2=OFF
Branch if SW2=OFF
Turn off LED2
************************************************
*
*
NAME : FSADDR (DETECT ADDRESS ERROR)
**
ENTRY: NOTHING
*
**
*
************************************************
C063
C066
C068
C06A
C06C
C06F
C071
C073
C076
C079
C07B
C07E
7B
26
86
97
7E
96
26
72
7B
26
04 15
13 C07B
01
A
A
42
0003 A
42
A
03 C076
08 18
04 15
03 C07E
71 F7 18
39
*
RETURNS : TRMD (ERROR MODE)
*
**************************************************
FSADDR BTST
BNE
LDAA
STAA
JMP
LDAA
BNE
FSADR1 BSET
FSADR2 BTST
BNE
FSADR3 BCLR
FSADR4 RTS
2.P5DTR
FSADR3
111
TRMD
3
TRMD
FSADR2
3.P7DTR
2.P5DTR
FSADR4
3.P7DTR
Test if SW3=ON
Branch if SW3=ON
Store 1 in TRMD
Execute address error mode
Test if TRMD=O?
Branch if TRMD=L
Turn on LED3
Test if SW3=OFF
Branch if SW3=ON
Turn off LED3
************************************************
*
*
NAME : FSTRP (RETURN FROM ERROR BY TRAP)
*
*
**************************************************
*
*
ENTRY
: TRMD (ERROR MODE)
$HITACHI
1094
*
*
*
*
00115
00116
00117
00118A
001l9A
00120A
00121A
00122A
00123A
00124A
00125A
00126A
00127A
00128A
00129A
00130A
0013lA
00132A
00133
00134
00135
00136
00137
00138
00139A
00140
00141A
00142A
00143A
00144A
00145A
00146A
00147A
00148A
00149A
00150A
0015lA
00152
00153
C07F
C080
C081
C084
C085
C087
C089
C08B
C08D
C08F
C092
C094
C097
C09A
C09C
RETURNS : NOTHING
*
*
*
*
************************************************
FSTRP
30
18
C3
18
96
26
86
97
EC
C3
20
7F
FC
TSX
XGDX
0005 A
ADDD
XGDX
42
A
LDAA
OB C094
BNE
01
A
LDAA
42
A
STM
A
LOD
00
0001 A
ADDD
06 C09A
8RA
0042 A FSTRP1 CLR
C073 A
LOD
ED 00
A FSTRP2 STD
3B
RTI
1i$5
CaLcurate program counter
TRMD
FSTRP1
Test 1f op-code or address error?
Br~lnch if address error
Store 1 1n TRMD
iiI
TRt~D
O.X
Increment program counter
iiI
FSTRP2
TRMO
FSAOR1
O.X
CLear TRMD
Store program counter
************************************************
*
**
VECTOR ADDRESSES
*
*
*************************************************
*
FFEA
FFEA
FFEC
FFEE
FFFO
FFF2
FFF4
FFF6
FFF8
FFFA
FFFC
FFFE
Load stack po1nter 1nto ACCD
COOO
COOO
C07F
COOO
COOO
COOO
COOO
COOO
COOO
COOO
COOO
A
A
A
A
A
A
A
A
A
A
A
*
*
ORG
$FFEA
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FDB
FOB
FSMN
FSMN
FSTRP
FSt1N
FSMN
FSMN
FSMN
FSMN
FSMN
FSMN
FSMN
IR02
CMI
TRAP
SID
TOI
OCI
ICI
IROI/ISF
SWI
NMI
RES
END
I
~HITACHI
1095
~HITACHI
1096
HD63011HD6303 SERIES HANDBOOK
Section Nine
C Language
Programming
Thchniques
I
~HITACHI
1097
~HITACHI
1098
Section 9
C Language Programming Techniques
Table of Contents
Page
1.
1.1
HOW TO USE APPLICATION NOTES .............................. . 1105
Hardware Section ............................................. . 1107
1.1.1
Function ................................................... . 1107
1.1.2 Microcontroller Applications ................................... . 1107
1.1.3 Circuit Diagram ............................................. . 1108
1.1.4 Memory Map ............................................... . 1109
1.1.5 Pin Functions ............................................... . 1110
1.1.6 Hardware Operation ......................................... . 1111
1.2
Software Section .............................................. . 1112
1.2.1 Program Module Configuration ................................. . 1112
1.2.2 Program Module Functions .................................... . 1113
1.2.3 Program Module Sample Application (Main Program) ............... . 1114
1.3
Program Module Section ........................................ . 1116
1.3.1 Page Heading .............................................. . 1117
1.3.2 Function ................................................... . 1117
1.3.3 Arguments ................................................. . 1117
1.3.4 Libraries Required for Program Execution ........................ . 1118
1.3.5 Specifications .............................................. . 1119
1.3.6 Description ................................................. . 1120
1.3.7 PAD ...................................................... . 1123
1.4
Subroutine Section ............................................ . 1124
1.4.1
Page Heading .............................................. . 1125
1.4.2 Function ................................................... . 1125
1.4.3 Basic Operation ............................................. . 1125
1.4.4 Program Modules That Use This Function ........................ . 1126
1.4.5 PAD ...................................................... . 1126
1.5
Program Listing Section .......... , ............................. . 1127
1.5.1 Main Program Listing ........................................ . 1127
1.5.2 C Source Listing ............................................. . 1128
1.5.3 Output Object Listing of C Com pliler ............................ . 1131
1.5.4 Linkage Listing .............................................. . 1132
~HITACHI
1099
I
1.6 Program Module Use. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1135
1.7 Pad Symbols Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1137
1.8 Symbols...................................................... 1138
2.
DARLINGTON TRANSISTOR DRIVE (LED DYNAMIC DISPLAY) . . . . . . . . .. 1139
2.1
Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1139
2.1.1 Function.................................................... 1139
2.1.2 Microcontroller Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1139
2.1.3 Circuit Diagram .............................................. 1139
2.1.4 Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1140
2.1.5 Hardware Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1141
2.2 Software Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1142
2.2.1 Program Module Configuration ................................ "
1142
2.2.2 Program Module Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1142
2.2.3 Program Module Sample Application (Main Program). . . . . . . . . . . . . . .. 1143
2.3
Program Module Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1144
2.4
Program Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1152
2.4.1 Main Program Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1152
2.4.2 C Source Listing . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1153
2.4.3 Output Object Listing of C Complier. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1154
2.4.4 Linkage Listing ............................................. "
1157
3.
8x4 KEY MATRiX ............................................... 1159
3.1
Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1159
3.1.1 Function .................................................... 1159
3.1.2 Microcontroller Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1159
3.1.3 Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1160
3.1.4 Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1161
3.1.5 Hardware Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1161
3.2
Software Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1162
3.2.1 Program Module Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1162
3.2.2 Program Module Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1162
3.2.3 Program Module Sample Application (Main Program). . . . . . . . . . . . . . .. 1163
~HITACHI
1100
3.3
Program Module Description .................................... "
3.4
Program Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1177
3.4.1
1165
Main Program Listing .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1177
3.4.2 C Source Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1178
3.4.3 Output Object Listing of C Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1180
3.4.4 Linkage Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1185
4.
4.1
EXTERNAL EXPANSION ......................................... 1187
Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1187
4.1.1
Function.................................................... 1187
4.1.2 Microcontroller Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1187
4.1.3 Circuit Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1187
4.1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1188
4.1.5 Hardware Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1189
4.2
Software Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1190
4.2.1
Program Module Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1190
4.2.2 Program Module Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1190
4.2.3 Program Module Sample Application (Main Program). . . . . . . . . . . . . . .. 1192
4.3
Program Module Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1194
4.4
Program Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 1220
4.4.1
Main Program Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1220
4.4.2 C Source Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1222
4.4.3 Output Object Listing of Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1226
4.4.4 Linkage Listing ............................................. "
1232
APPENDIX A.
C Program and Assembly Program Comparison .......................... 1235
~HITACHI
1101
~HITACHI
1102
FOREWORD
The HD6301 series is composed of 8-bit single chip CMOS microprogrammed microcontrollers.
The HD6301 series provides pipeline Control, halt, and memory-ready functions for processing data.
This apprication note contains C language programs which are described using application functions
routines as examples. In general, it is difficult to write a program in a high-level language like C
which carries out low level functions, such as controling ports, timer interrupts, etc.
However, this application note's program have been written in C, using mainly the hardware control
functions listed above, and have been written to help users design hardware systems, employing
specific circuit diagrams, timing charts and program modules.
This application note also contains assembly language program descriptions, with functions
equivalent to the C language programs.
Please use these descriptions to compare the two languages.
Caution:
Test the application examples, in this application note for proper results before
incorporating them into production operations systems.
I
~HITACHI
1103
REFERENCES
• HD6301 Series Application Notes
(C Language) (ADJ-502-003)
• HD6301XO, HD6303X Application Notes
• V AXNMS630 1C Compiler User's Manual
(HS31VCLVIS)
• C Language Manual
(S999CLLlM)
(Hardware) (68-3-11)
~HITACHI
1104
SECTION 1. HOW TO USE APPLICATION NOTES
This chapter describes the configuration for all system application examples in this application note.
Each application example in this application note is divided into 5 sections, as shown in Figure 1-1.
, ................. L
Hardware
----;1
§
................................................................................................................................................................. ~
Hardware Description
:
:
:
:
:
Function
Microcontrolier Applications
Circuit Diagram
Memory Map
Pin Functions
Hardware Operation
t
1
:
:
1
:
:
t ..............................................................................................................................................................................................................................................!
............................................................................................................................................................................................................................................................................................ ,
Software
------!~
Software Description
:
Program Module
1
Configuration:
Program Module
1
Functions:
Program Module Sample
1
Application (MAIN PROGRAM)
:
1
:
:
:
·............................................................................................................................................................................................................................. ...
'
.......................................................................................................................................................................................,
Program
Module~
:
:
:
Program Module
Description
t-t--
·
I--
t-t--
'-
Function
1
Arguments
:
Libraries Required for
:
Program Execution
:
Specifications
Description
- r- Function
:
Notes
Detans'
f- User Notes
.
~tgWCHART
r- Variable
:
r-
:
sa~~:riPtions
Application
--Basic
Operation
:
•
:
'....................................................................................................................................................................................................................... ..
Subroutine
---~··s~·b~~~i;~~·····································
DeSCription
-C
...................................
Function
Basic Operation
Pad Flowchart
~
:
·, .......................................................................................................................................................................................................................
. ...
~
Program Listing
--1
E
.................................................................................................................................................................................... .
Program Listing
Main Program Listing
C Source Listing
1
Output Object Listing of C Compiler
:
Linkage Listing
, ................................................................................................................................................................................................................ . .
:
Figure 1-1.
I
Application Example Configuration
@HITACHI
1105
I. Hardware
Describes the function, circuit diagram, and hardware operation of the HD6301 hardware
example.
2. Software
Describes the program module which controls the hardware in the hardware section example and
shows the main program using all program modules.
3. Program Module
Describes the program modules presented in the software section in detail program written in
modular format allow more efficient system use.
4. Subroutine
Describes the subroutines used in the above program modules.
Refer to this section when necessary while using the program modules.
5. Program Listing
Presents the sample application program listings for the above modules.
A detailed explanation of all five sections follows.
~HITACHI
1106
1.1 Hardware Section
1.1.1 Function
"Function" describes system specifications for the hardware used in the particular application (figure
1-2).
4.1.1 Function
The external expansion application controls external memory and peripheral LSls using the
HD6301 YO. It uses the HD6350 (ACIA) as an asynchronous serial interface with a console
typewriter, It also controls a liquid crystal module H2571 and displays console typewriter input
characters using the HD6321 (PIA).
Figure 1-2.
Function Section
1.1.2 Microcontroller Applications
"Microcontroller Applications" describe the functions of the microcontroller, in the particular
application (figure 1-3).
4.1.2 Microcontroller Applications
This application interfaces with external LSls through an address bus, data bus, and control signals
(RiW and E) using the HD6301 YO external expansion function.
Figure 1-3.
I
Microcontroller Applications
@HITACHI
1107
1.1.3 Circuit Diagram
"Circuit Diagram" shows the circuit diagram for the hardware specified above (figure 1-4).
Note: All the microcontrollers described in the application note use plastic DIPs.
4.1.3 Circuit Diagram
Figure 4-1 is the application circuit diagram.
Figure 4-1. External Expansion Circuit Diagram
Figure 1-4. Circuit Diagram Section
~HITACHI
1108
1.1. 4 Memory Map
Describes address decoding and system memory map for the application system (figure 1-5). (used in
Section 4, "External Expansion" only.)
4.1.4 Memory Map
Memories and peripheral LSls are allocated in external address space using an address decoder
(HD74HCI38).
Address lines A13, AI4 and AI5 are connected to pins A, B and C of the HD74HC138.
Address space $8000-$FFFF is divided into 8k-byte units. Table 4-1 shows the system address
decoding.
Table 4-1.
System Address Decoding
HD74HC138
Input
Output
Gl G2A G2BC
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
B
A14
L
L
H
A
A13
L
H
L
H
H
Y4
L
H
YS
Y6
Y7
H
H
H
L
H
H
H
H
L
L
H
H
H
H
Address
$8000-$9FFF
$AOOO-$BFFF
$COOO-$DFFF
$EOOO -$FFFF
Allocation
RAM
PIA
ACIA
ROM
Figure 4-2 shows system memory map.
$0000
$OOlF
$0040
$OOFF
$7FFF
$8000
$9FFF
$ACOO
$BFFF
$COOO
$OFFF
$EOOO
$FFFF
1/0 Ports
TIMER
SCI
Not Used
RAM
(192 Bytes)
Not Used
RAM
(HM6117)
H06301XO internal register and
internal address space.
J
PIA
(H06321)
OORNPORTA
CRA
OORBIP RTB
RB
Not Used
$ACOO
$AOOl
$AC02
$A003
ACIA
(HD6350)
CTRUSTS
TDR/RDR
$COOO
$COOl
EPROM
(HN27C64)
Not Used
$BFFF
$OFFF
Figure 4-2.
System Memory Map
Figure 1-5. Memory Map Section
I
~HITACHI
1109
1.1.5 Pin Functions
A table describes the pin functions for interfacing with external circuits (figure 1-6).
2.1. 4
Pin Functions
Table 2-1 shows the pin functions at the interface between the HD6301XO and an 8-digit x 8-segment
LED.
Table 2-1.
Pin Functions
Pin Name
(HD6301XO)
P60
Active
Input/ Level
Output (High or
Low)
Output
Pin name Program
(LED)
Label
Function
High
Outputs digit data to
DIOl
8-digit x 8-segment LED.
DIG2
P61
Output
High
P62
Output
High
DIG3
P63
Output
High
DIG4
P64
Output
High
DIGS
P65
Output
High
DIG6
High
DIG7
P66
Output
P67
Output
High
PlO
Output
Low
Outputs segment data to
8-digit x 8-segment LED.
DIG8
--
Pll
Output
Low
P12
Output
Low
P13
Output
Low
P14
Output
Low
PIS
Output
Low
ell c
P16
Output
Low
P17
Output
Low
d
Segment Pattern
a
c
a
fl
g
b
Ib
d
e
h
•
f
g
h
• " Active lever' in table 1 indicates the following:
High
logical 1
Low
logical 0
logical 1 or logical 0
Figure 1-6. Pin Functions Section
~HITACHI
1110
P6DTR
PlDTR
1.1. 6 Hardware Operation
Timing charts describe hardware operations required to control external circuits (figure 1-7).
4.1. 5 Hardware Operation
Figure 4-3 shows the interface timing chan for the HD6301 YO and external memory (HN27C64,
HM6117).
--;
E
ADDRESS
HD6301YO
-
X
\
R/IT
-~ Decoder delay time
~ lCE
tCE
HN27C64
DE
tACC
l
DSR
&
...:HIt
DATA
(OUT)
I-~coder
delay time
[~,.a,
Data
read
COl 2
tACC
tDSR
tHR
DATA
(OUT)
HM6117
Data
~
[~
twp
f ( ~
tl1W
write
DATA
(IN)
HD6301YO
tAD:
tDSR:
tHR:
IOW~
HN27C64
HM6117
tCE:
tOE:
IACC:
tOH:
tAA:
tC01,2:
tWP:
tOW:
tDH:
tDR } -
Address delay time
Data set-up time
Data hold time
Data delav time
CEOutput delay time
OE Outout delay time
Access time
Data output hold time
Address access time
CE1 ,CE2 Output delay time
WrHe pulse width
Input data set time
Input data hold time
I
Figure 4-3. Interface Timing Chart for HD6301YO and External Memory
Figure 1·7. Hardware Operation
~HITACHI
1111
1.2 Software Section
1.2.1 Program Module Configuration
"Program Module Configuration" describes the program modules for controlling the hardware
specified in the hardware section (figure 1-8). Each module in the program module configuration
figure has module number (1-N) in the upper right hardcorner. The module number of the main
assembly language program is O.
4.2.1 Program Module Configuration
Figure 4-4 shows the program module configuration which displays data input from a console
typewriter. using the circuit in Figure 4-1.
EXPMN
Main program 0
(Assembler
language)
Figure 4-4.
Program Module Configuration
Refer to Section 4.3 "Program Module Description" discusses these modules for details.
Figure 1-8. Program Module Configuration Section
~HITACHI
1112
1.2.2 Program Module Functions
"Program Module Functions" explains the functions of each program module presented in the
program module configuration. "No." in the table matches the module number in the program module
configuration (figure 1-9).
4.2.2 Program Module Functions
Table 4-2 summaries the program module functions.
Table 4·2.
Program Module Functions
Program Module Library
No. Name
Function
Function
Language
o
Initializes instructions, such as ORO,
ASM
Main program
EXPMN
LOS, and CLI, which do not exist in C.
Calls expin function and main function
Interrupt
EXPINP
Receives and processes IRQ interrupt
ASM
Initializes global variables, t-IA, ACIA,
C
reception
2
Initialization
expin
andLCD·II
3
Data processing
main
Displays key data, input from console
C
typewriter, on liquid crystal display (H2571)
and prints the data on the console typewriter
4
Receive data
expip
Receives key data from the console
C
typewriter through an IRQ interrupt
5
LCD·II initialization expint
Initializes LCD·II
C
6
Display Character
expdsp
Displays characters on LCD
C
7
Send data
expout
Sends data to console typewriter
C
Note:
C: C Language Program
ASM: Assembly Language Program
Figure 1·9. Program Module Functions Section
I
~HITACHI
1113
1.2.3 Program Module Sample Application (Main Program)
"Program Module Sample Application (Main Program)" explains a sample program in flowchart
format using the program module described in the program module configuration (figure 1-10).
4.2.3 Program Module Sample Application (Main Program)
The flowchan in Figure 4-5 is an example of the execution sequence of the program module in Figure
4·4 when it displays key data input from a console typewriter on a liquid crystal display and prints the
data on the console typewriter.
(
EXPMN)
Main program
#$ FF ... SP
I···············..··{
Initialize stack pointer
f·········, ..······{
Inijialize PIA. ACIA, LCD·II, and
global variables
f-L--I_eXPin---'-II
o
. . . bit 1
1-'--11
1.. ·················-[
II[
ma-----,-,'"
(
(
END
EXPINP)
~II
IRQ interrupt routine
11.................. -[
eXP---LJi
P
(
Enable interrupt
After converting the key data input from the
console typewrijer into ASCII code,
display the resuH on the liquid crystal
display (H2571) and print the resun on
the console typewrijer
Execute 'expip' to receive data from the
console typewriter and store it in
global variable 'keydat'
Return
Figure 4-5.
Program Module Flowchart
Figure 1-10. Program Module Sample Application (Main Program)
~HITACHI
1114
Further figures described the flow of program modules shown in general flowchart of main program
(figure 1-11).
Figure 4·6 shows the execution sequence of C language program 'expin'. In 'expin', key data input
from console typewriter is displayed on the liquid crystal display (H2571) and printed on the console
typewriter.
(
expin
)
1
Clear global variable (0)
Select DORA of PIA
Ox 00 -+ * CRA
Select part A of PIA
as output
o x If -+- CRA
I
Store function data in
entry argument func
o x 30 -+ tunc
I
Store entry mode data
In entry argument
entry
o x 06 ..... entry
I
expint function
Select port A register
Ox04-+*CRA
Set H2571 control
signal
Ox 02-+*PIRA
Select OOR B of PIA
Ox 00-+- CRB
Select port B of PIA
as output
o x If -+* OORB
I
I
Master reset ACIA
Ox 97 -+*CR
I
Innialize ACIA
Ox95-+-CR
1 startbn + 8bns 1
data + 1 stop bH, 16
RTS+O, TIE-O, RIE 31
I
Select port 5 bit 0
as IRa pin
PSCR
1
o x 7d -+ *
(
Figure 4·6.
Figure 1-11.
Retum
Program Module Flowchart
I
Sample Application (Other Routines)
~HITACHI
1115
1.3 Program Module Section
The program module detailed description format is shown in figure 1-12.
/
Library Function:
PAn
Libn.fl Function:
Description
Librarv Function:
Function
Arguments
Storage Locntion
Conlcnts
No.
or
n,.l~s
Eo""
Retum
Libraries Required for Program Execution
Required/Not Required
l.ibrary
Smndard library Function
C31.lm.OBJ
NOlrequired
Run-Time Routine
C31RUN. ODI
Required
C3IRUNF. OBI
Notrcquired
Specifications
ROM (bytes):
RAM (bytes):
Slack (bytes):
No of cycles:
Reentrant:
Relocatnble:
Inlt'mlplible:
NOIe:
Description
1Function Details
Argument Details:
Example:
Figure 1-12. Program Module Format
~HITACHI
1116
1.3.1 Page Heading
Each page in this section is headed by the program modules name and the library function by which it
is called (figure 1-12).
1.3.2 Function
"Function" describes the program module functions (figure 1-13).
Function
The receive data module receives data from console typewriter and stores key data in global variable
'keydat'.
Figure 1-13.
Function Section
1.3.3 . Arguments
"Arguments" describe both entry and return arguments for the program module (figure 1-14).
• Contents: The contens of the arguments.
• Storage location: Location of arguments (global variables).
• No. of bytes: The argument length.
Contents
Storage Location
No. of Bytes
Received data
keydat
2
(ASCII code)
(global variable)
Received data flag
keydrf
Entry
Returns
2
(global variable)
Figure 1-14.
I
Arguments Section
~HITACHI
1117
1.3.4 Libraries Required for Program Execution
"Libraries Required for Program Execution" describes the libraries which must be linked for the
program to execute (figure 1-15).
Standard Library Functions (C31Lffi. OBI): Prior to using a program, the library functions and the
subroutines used by the library functions must be linked. The library functions are stored in
"C31Lffi, OBI".
Run-Time Routines (C31RUN. OBI, C31RUNF. OBI): Run-time routines are called from the object
programs, generated by the compiler, during execution.
The following two mes are supplied:
•
C31RUN. OBI
•
C31RUNF. OBI
Link "C31RUN. OBI" when only integers are used in the module or "C31RUNF. OBI" when
integers and floating point numbers are used. These files should not both be linked.
The module in this example does not use the
standard library functions.
C31Lffi. OBJ should not be linked,
but run-time routine, C31RUN. OBJ
should be linked. since it uses only integers.
Library
Required/Not Required
Standard Library Function
C31UB. OBI
Not required
Run-Time Routine
C31RUN. OBI
C31RUNF. OBI
Not required
Required
Figure 1·15. Libraries Required for Program Execution Section
~HITACHI
1118
1.3.5 Specifications
"Specifications" describes the program module specifications as follows (figure 1-16):
• ROM (bytes): Amount of ROM used by thr program module.
• RAM (bytes): Amount of RAM used by the program module. RAM used for stack is not included.
• Stack (bytes): Size of the stack used by the program module. The stack area used by a subroutine
called from a user program is not included. When a program module is executed. memory for the
stack must be reserved in RAM.
• No. of cycles: Maximum number of execution cycles required by the program module, calculated
as follows:
Execution time (s) = Number of cycles x Cycle time
Cycle time (s) =4/(Extemal oscillator
• Reentrant: Indicates whether a program module has a structure which can be called from two or
more routines at the same time.
• Relocatable: Indicates whether a program module can be located in any memory space.
• Interruptible: Indicates whether the CPU will continue with normal execution after servicing an
interrupt routine. If not, inhibit interrupts before and after the program module is called.
(Hz»
Specifications
ROM (bytes):
RAM (bytes):
48
4
No of cycles:
0
63 (Note)
Reentrant:
No
Stack (bytes):
Relocatable:
No
Interruptible:
No
Note: Ox indicates a hexadecimal number in C.
Figure 1-16.
Specifications Section
I
~HITAaHI
1119
1. 3.6 Descri ption
"Description" described the functions of the program module in detail and the precautions to follow
(figure 1-17).
Function Details: "Function Details" gives an execution example and detailed functions of the program
module.
User Notes: "User Notes" explains notes and limitations on executing the program module.
Be sure to read these notes when using the program modules.
Argument details: Global variable 'keydat' contains I-byte of key data (ASCII) from the console
typewriter. Global variable 'keydrf is a flag indicating that data has been received. Table 4-3 shows
flag functions.
Example: Figure 4-8 shows an example of program module 'expip' execution. If key "a" on the
CD, the received data is put in the key data buffer and oxff
console typewriter is pressed as shown in
is stored in 'keydrf as shown in (i).
~
='a' && keydat<='z')
keydat-=Ox20; f. Change lower case to upper *f
keydrf=O;
f. Clear flag of receive data *f
.CR=Ox95;
f. Set RTS=low .f
outdat=dspdat=keydat;
f. Set output data In area .f
expout();
f. Transmit data to console .f
expdsp();
f. Display characters on LCD-II .f
Figure 1·30. C Language Module
I
~HITACHI
1129
Program Module: The program module listing is divided into separate functions (figure 1-31):
(a)
(b)
Program module title
Library Function
I·····················································........................*,/
I·····················································......................../
1*
NAME: EXPIP
j.
(RECEIVE DATA)
.j
1*
II
j.
j.
.j
.j
(a)
ENTRY
NOTHING
RETURNS: KEYDAT
(RECEIVED DATA)
: KEYDRF
(RECEIVED FLAG)
j.
j.
.j
.j
I····················································· ........................ /
1*
*1
(b)~
II Test if data Is received _/
j. Set RTS·hiCh .f
II Set receive data */
1* Oxft if receive data Is set */
II Set RTS-low */
if «.SRLl)!·O) (
.CR-OxdS;
keydat • IRDR:
keydrf·Oxff:
·CR-Ox95 :
Figure 1·31.
Program Module
Common Subroutine: Next, common subroutines used in the program module are listed (figure 132):
(a)
(b)
Subroutine title
Library Function
I ••••••••••••••••••••••••••••••••••••••••••••••••••• •••••••••••••••••••••••••• /
*/
{ /-
r.............................................................................,
(a)~:
:~
NAME: EXPIN (INITIALIZE PIA.ACrA AND LCD-Z)
/
(b)
Pin ()
outdat-dspdnt .. keydrr .. keydn t-tncnt .. func"cntry.O:
/_ Int tlal1ze ./
.eRA "OxOO;
II Select data direction register A II
IOOnA-Oxff:
·,eRA "Ox04:
.PIRA .. Ox02:
/. Select port A os output . /
/. Select peripheral register A II
/. Set RS .. O, R/W-I, E-O .1
.cnn "OxOO:
IODRO .. Oxff:
.CRu .Ox04:
fUnc·Ox30:
entry"Ox06:
explnt():
setins(OxOe);
.CR .. Ox97;
'CR.Ox95:
.PSCR .. Ox7d;
Select peripheral register D
II Set function data ' /
Set entry mode data II
II Initialize LCD-II ./
II Set instructlon to LCD-II -/
I' Master reset of ACIA II
II Initialize AeIA -/
II Initialize port 6 II
Figure 1·32.
1130
*,
/* Select data direction register 0 -/
II Select port n as output
,*
'I
Common Subroutines
~HITACHI
It
1.5.3 Output Object Listing of C Compiler
6301 C compiler outputs an object code listing in 6301 assembler language (figure 1-33):
(a)
(b)
Macro definition generated by the compiler
Global variable definition
(c)
Compilation result (assembly language output listing) of a C language source program
CP/M-6SK 6301/6801/6800 CROSS MACROASSEMBLER
ERR
SEQ
LaC
OBJECT
00001.
00002
00003
00004
00005
MSEX
NAM
EXPC
OPT
MACR
REL
CLRA
T5TB
8PL \.0
00006
00007
COMA
\.0 EQU •
ENDM
MLBRA MACR
JMP \0
00008
00009
00010
00011
00012
00013
00014
00015
ENDM
MLBSR MACR
JSR \0
ENDM
MLBEQ MACR
BNE \. a
JMP \0
\.0 EQU •
00016
00017
00018
00019
000'10
E~DM
OOOS'l
00062
MLBCS
MACR
Bce \.0
00063
00064
00065
000668 0000
0002
000678 0000
00068R 0002
000698 0002
000708 0004
000718 0004
0002
0002
000720 0006
000738 aD06
000748 0008
000758 0008
000768 DODA
000778
0007B8
000798
OOOBOP
OOOB1P
OOOB2P
00083P
OOOB4P
OOOBSP
000B6P
00087P
DOOSBP
OOOS9P
00090P
VI.2 •••
PROGRAM EXPC
(a)
J
JMP \0
\.0 EQU •
ENDM
BSCT
A OUTDAT BSZ
RSCT
A DSPDAT BSZ
BSCT
A KEYDRF BSZ
BSCT
0002
A KEYOAT BSZ
0002
A TNCNT
0002
A FUNC
0002
A
BSCT
BS2
(b)
BSCT
OODA
OOOC
OOOC
0000
0000
0002
0004
0006
OOOB
0008
0000
OOOF
0012
0014
20
DC
27
DE
8C
20
DE
BC
2E
DC
nnn'll0 nn,o:I
0'1
31 0033
B
O'
20 0033
06
B
0061
A
OE 0018
06
B
007A A
07 0018
06
B
BS2
8SCT
ENTRY BS2
PSCT
BRA
. SA003 lOD
BEQ
LOX
CPX
BLT
LDX
CPX
BGT
LDD
· $A002l
KEYORF
· SA004
KEYDAT
#97
C
.$AOOS , ( )
KEYDAT I
#122
:
· SAOOS I
KEYDAT :
Figure 1-33. Output Object Listing of C Compiler
~HITACHI
1131
1.5.4 Linkage Listing
Linkage Command Listing: The linkage command listing is a sample command main assembly
program and a C language sequence for linking and executing a program (figure 1-34):
Divide into sections, taking the system memory map into consideration
a>
• STRP
Program Section
• STRB
• STRD
Base Section
Data Section
Output map listing and symbol listing using OPT command
@ Input EXEC command to execute linkage editor
••• HMCS6800 CROSS LINKAGE EDITOR
VER 1.2
LOAD=B: EXPMN. OBJ • B: EXPC. OBJ • C31RUN. OBJ .....•.••. I<
TCSR1
>I<
OCR1 + 1250 - - .
OCR1
>I<
Turn off the entire display for a
fixed period before displaying
the next data.
o ~* P6DRT
Output segment data to port 1
segd (count) -------
*
P1DTR
Output digit data to port 6
deed (count)
~
>I<
P6DTR
Initialize counter
indicating segment
data and digit data
pair7 ~ count
Test if counter indicating
segment data and digit
data pair equals 0
count = 0
Decrement counter indicating
segment data and digit data
pair
Return
Figure 2-12. Drive LED Module PAD
~HITACHI
1151
2.4 Program Listing
2.4.1 Main Program Listing
•••
ERR
V1.2 •••
CP/M-68K 6301/6801/6800 CROSS MACROASSEMBLER
SEQ
LOC
OBJECT
PROGRAM
.................................................... _- ......
00001
00002
•
00003
•
00004
•_
00005
00006
00007
00008P 0000 8E OOFF A LEDMN
00009P 0003 BD 0000 A
00010P 0006 OE
OOOllP 0007 20 FE 0007 PEND
00012
00013
•
00014
•
00015
•
00016
00017
•
00018
•
00019
•
00020
•
00021
0000
A
LEDSP
00022P 0009 BD
00023P OOOC 3B
00024
00025
•
00026
•
00027
•
00028
00029
•
00030A FFEA
00031
•
00032A FFEA
0000 P
00033A FFEC
0000 P
00034A FFEE
0000 P
00035A FFFO
0000 P
0000 P
00036A FFF2
0009 P
00037A FFF4
00038A FFF6
0000 P
0000 P
00039A FFF8
0000 P
00040A FFFA
00041A FFFC
0000 P
0000 P
00042A FFFE
00043
•
00044
TOTAL ERRORS 00000--00000
MAIN PROGURAM : LEDMN
•
•
... _--_ ...... -.. -•.............• __ ........ _-_ ....... -......•
OPT
XREF
LDS
JSR
CLI
BRA
REL
PSCT:MAIN,PSCT:LEDINT
#$FF
Set stack pointer
Initialize variables
LEDINT
Enable interrupt
End of program
PEND
......................... __ .................... __ ...........
......
•
•
•
_.................... _- ...............................
•
NAME : MAIN
(DRIVE LED)
SEGD (DISPLAY DATA)
NOTHING
ENTRY
RETURNS
•
•
•
.........................................................*....•.....•....•...•...........................•*------......•
JSR
RTI
Drive LED
MAIN
VECTOR ADDRESS
•
....•............................ -....................... _--•
.-.-
ORG
$FFEA
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FDB
FOB
LEDMN
LEDMN
LEDMN
LEDMN
LEDMN
LEDSP
LEDMN
LEDMN
LEDMN
LEDMN
LEDMN
END
~HITACHI
1152
IRQ2
CMI
TRAP
SIO
TOI
OCIl
ICI
IRQ1
SWI
NMI
RES
2.4.2 C Source Listing
*1
I********************DECLARATION OF DEFINE--------_._._ ••••
*1
1*
#define PIDTR
«char*)Ox2)
I*Port 1 data register*1
I*Timer control status register*1
#define TCSRl
«char*)Ox8)
I*Output compare register*1
#define OCRI
«int*)Oxb)
#define PBDDR
I*Port B data direction register*1
«char*)OxlB)
( ( char- ) Oxl 7)
#define PBDTR
I*Port B data register*1
1*
/*****.* ••• **********DECLARATION OF GLOBAL VARIABLES**************************I
*1
1*
static direct char decd[8)={l28,B4,32,lB,8,4,2,l};
I.Digit data*1
I*Segment data*1
static direct char segd[8)={Oxf8,Ox82,Ox92,Ox99,OxbO,Oxa4,Oxf9,OxcO};
static direct int
count;
I*Segment,Dlgit counter.1
_--*-------_._-----/
1-*···_· __ ····_------------_·-·_----*------_· __ ······- ._._._-_._._----_._ .. _._/* I
1*
1*
1*
MAIN ROUTINE
: MAIN
(DRIVE LED)
*1
*1
1----·_·_----------------------------------·-·_---_·_· ._._--------------------/
*1
1*
1*
ENTRY
RETURNS
I.
SEGD
(DISPLAY DATA)
NOTHING
1*
*1
*I
*1
1·-·-····_-_·_·_---------------_·_·_--_·_·_-------_·_· -*------_.-.--_._._._._-/
main( )
{
char
work;
work= *TCSRl;
.OCR1 +=1250;
*PBDTR = OxO;
*PlDTR =segd[count);
*PBDTR=decd[count);
if(count==O)
count=7;
else
count--;
I*Timer controller access only *1
I*Set interrupt every 1.25 ms*1
I*Turn off display*1
I*Output segment data*1
I*Output digit data*1
I*Display 8-digit data?*1
I*Initialaize counter*1
I*Decrement segment,digit counter*1
/** •• **********.**********.*.*.**.**.****.**.***~***** -----------_.-._._--_._-/
1*
*1
1*
NAME: LEDINT (INITIALIZE)
*1
1*
*1
1--···-------*_···_-_···_--_·
__ ···_···········_-****·· .. **** •••••• * •• ** •• **.*./
ledint ()
{
count=7;
*PBDDR=Oxff;
*TCSRl=Ox8;
*OCRl=l250;
I*Initialaize digit,segment counter*1
I*Select portB as output*1
I*Set timer*1
I*Set 0 in portB*1
I
~HITACHI
1153
2.4.3 Output Object Listing of C Compiler
••• CP/M-68K 6301/6801/6800 CROSS MACROASSEMBLER
ERR
SEQ
LOC
OBJECT
PROGRAM LEDSP
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
NAM
OPT
MACR
MSEX
CLRA
TSTB
BPL \.0
COMA
\.0 EQU •
ENDM
MLBRA MACR
JMP \0
ENDM
MLBSR MACR
JSR \0
ENDM
MLBEQ MACR
BNE \.0
JMP \0
\.0 EQU •
ENDM
MLBNE MACR
BEQ \.0
JMP \0
\.0 EQU •
ENDM
MLBGT MACR
BLE \.0
JMP \0
\.0 EQU •
ENDM
MLBGE MACR
BLT \.0
JMP \0
\.0 EQU •
ENDM
MLBLT MACR
BGE \.0
JMP \0
\.0 EQU •
ENDM
MLBLE MACR
BGT \.0
JMP \0
\.0 EQU •
ENDM
MLBHI MACR
BLS \.0
JMP \0
\.0 EQU •
ENDM
MLBLS MACR
BHI \.0
JMP \0
\.0 EQU •
ENDM
MLBCC MACR
•
1154
HITACHI
LEDSP
REL
V1.2 •••
... CP/M-68K 6301/6801/6800 CROSS MACROASSEMBLER
ERR
SEQ
00057
00058
00059
00060
00061
00062
00063
00064
00065
000661'
00067P
000681'
000691'
000701'
000711'
000721'
000731'
000741'
00075P
00076P
000771'
000781'
000791'
00080P
000811'
000821'
000831'
00084B
00085B
00086P
00087P
000881'
000891'
00090P
000911'
000921'
000931'
00094P
000951'
000961'
000971'
00098P
000991'
00100P
00101P
00102P
001031'
00104P
001051'
001061'
001071'
00108P
00l09P
OOllOP
001111'
001121'
LOC
0000
0000
0001
0002
0003
0004
0005
0006
0007
0008
0008
0009
OOOA
OOOB
OOOC
OOOD
OOOE
OOOF
0000
0000
0010
0010
0011
0014
0016
0017
0019
001C
001E
0021
0023
0026
0027
0028
002A
0020
002E
0031
0033
0034
0036
0037
0039
003C
0030
0040
0042
OBJECT
34
CE
E6
30
E7
CE
EC
C3
ED
CE
4F
5F
E7
CE
3C
CC
D3
18
E6
38
E7
CE
3C
CC
03
18
Vl. 2 •••
PROGRAM LEDSP
80
40
20
10
08
04
02
01
A
A
A
A
A
A
A
A
F8
82
92
99
BO
A4
F9
CO
A
A
A
A
A
A
A
A
0002
A
0008
00
A
A
00
OOOB
00
04E2
00
0017
A
A
A
A
A
A
00
0002
A
A
0008
00
P
B
00
A
00
0017
A
A
0000
00
P
B
BCS \.0
JMP \0
\.0 EQU *
ENOM
MLBCS MACR
BCC \.0
JMP \0
\.0 EQU *
ENOM
PSCT
FCB
DECD
FCB
FCB
FCB
FCB
FCB
FCB
FCB
PSCT
SEGO
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
BSCT
COUNT BSZ
PSCT
MAIN
DES
LOX
LOAB
TSX
STAB
LOX
LOO
AOOO
STO
LOX
CLRA
CLRB
STAB
LOX
PSHX
LOO
AODO
XGOX
LOAB
PULX
STAB
LDX
PSHX
LOD
AODD
XGOX
-128
64
32
16
8
4
2
1
-8
-126
-110
-103
-80
-92
-7
-64
2
#8
O,X
O,X
#11
O,X
#1250
O,X
#23
O,X
#2
#SEGD
COUNT
O,X
O.X
#23
#OECD
COUNT
I
~HITACHI
1155
*** CP/M-68K 6301/6801/6800 CROSS MACROASSEMBLER
ERR
**_.
SEQ
LOC
OBJECT
PROGRAM LEOSP
001l3P 0043 E6 00
A
001l4P 0045 38
001l5P 0046 E7 00
A
001l6P 0048 OC 00
B
001l7P 004A 26 05 0051
001l8P 004C CC 0007 A
001l9P 004F 20 05 0056
00120P 0051 DC 00
B .SA002
00121P 0053 C3 FFFF A
00122P 0056 DO 00
B .. 1
.$A003
00123P 0058 31
00124P 0059 39
00125P 005A
00126P 005A CC 0007 A LEDINT
00127P 005D DO 00
B
00128P 005F CE 0016 A
00129P 0062 CC OOFF A
00130P 0065 E7 00
A
00131P 0067 CE 0008 A
00132P 006A CC 0008 A
A
00133P 006D E7 00
00134P 006F CE OOOB A
00135P 0072 CC 04E2 A
A
00136P 0075 ED 00
00137P 0077 39
00138
00139
00140
TOTAL ERRORS 00000--00000
LOAB
PULX
STAB
LOO
BNE
LDD
BRA
LOD
AOOO
STD
INS
RTS
PSCT
LDO
STO
LDX
LOO
STAB
LDX
LDD
STAB
LDX
LDD
STO
RTS
XDEF
XOEF
END
O,X
O,X
COUNT
.$A002
#7
.. 1
COUNT
#-1
COUNT
#7
COUNT
#22
#255
O,X
#8
#8
O,X
#11
#1250
O,X
LEOINT
MAIN
~HITACHI
1156
V1.2 ***
2.4.4 Linkage Listing
*** IIMCS6800 CROSS LINKAGE EDITOR
LOAD=B:LEDMN.OBJ,B:LEDSP.OBJ,C31RUN.OBJ
STRP=$FOOO
STRB=$60
STRD=$40
OPT=MAP,SYM
EXEC
VER 1. 2 ***
*** HMCS6800 CROSS LINKAGE EDITOR
*** UNDEFINED SYMBOLS ***
VER 1.2 ***
NAME
SECTION
.ERROR
UNDEFINED SYMBOL = 1 (Note)
MODULE NAME
(
)
Note: There is an UNDEFINED SYMBOL=l (library function, ERROR) in the link infonnation but
it does not influence the execution of this program. The library function or run-time routines
call the ERROR service routine when 0 is used as a divisor in division or modulo operations.
Strictly speaking, the user should create an ERROR function. However it is never used in this
program, so it is just displayed as an UNDEFINED SYMBOL.
*** HMCS6800 CROSS LINKAGE EDITOR
*** MAP LIST ***
** SECTION LOAD MAP
SECTION
A
B
C
D
P
** MODULE LOAD MAP
NAME
LEDSP
VER 1. 2 ***
SIZE
0016
0002
0000
0004
0657
START
FFEA
0060
END
FFFF
0061
COMMON-SIZE
0040
1'000
0043
F656
0000
0000
BSCT
DSCT
0040
PSCT
FOOO
FOOD
F085
SIZE
START
0060
** COMMON LOAD MAP
SECTION
NAME
COMMON =
0
0000
I
~HITACHI
1157
*** HMCS6800 CROSS LINKAGE EDITOR
VER 1. 2
DEFINED SYMBOLS ***
NAME
SECTION START MODULE NAME
.$DADD
(
)
P
F656
)
(
.$DCMP
P
F656
.$DDEC
(
)
P
F656
)
.$DDIV
(
P
F656
(
)
.$DINC
P
F656
(
)
.$DMOV
P
F656
)
.$DMUL
(
P
F656
(
)
.$DNEG
P
F656
(
)
.$DSTK
P
F656
)
.$DSUB
(
P
F656
(
)
.$DTOF
P
F656
(
)
.$DTOI
F656
P
)
.$DTOL
(
P
F656
)
.$DTST
(
F656
P
)
.$FDEC
(
P
F656
)
.$FINC
(
P
F656
(
)
.$FMOV
F656
P
.$FREG
(
)
D
0040
.$FTOD
(
)
P
F656
)
.$FTST
(
P
F656
(
)
.$IASL
FOFA
P
(
)
.$IASR
F10F
P
)
. $IDIV
(
FOBC
P
)
.$IMOD
(
P
F139
(
)
.$IMUL
F085
P
)
.$lTOD
(
P
F656
(
)
.$ITOL
P
F39A
)
.$LADD
(
P
F1AC
(
)
.$LAND
P
F2AF
)
.$LBIT
(
F47D
P
)
.$LCMP
(
F33C
P
(
)
.$LCPL
P
F37E
(
)
.$LDEC
P
F3C8
)
.$LDIV
(
P
F260
)
.$LINC
(
P
F3B8
.$LMOD
(
)
F287
P
(
)
.$LMOV
P
F188
)
.$LMUL
(
P
FlOE
(
)
.$LNEG
P
F369
)
.$LOR
(
P
F2CA
)
.$LSHL
(
P
F300
)
.$LSHR
(
F31E
P
(
)
.$LSTK
P
F3D8
)
.$LSUB
(
P
F1C5
.$LTOD
(
)
F656
P
)
.$LTST
(
P
F3F3
.$LXOR
(
)
P
F2E5
)
.$SBIT
(
P
F5AO
)
(
.$SW1
P
F5E8
(
)
.$SW2
P
F617
(
)
.$UDIV
P
FOD8
(
)
.$ULSR
P
F124
)
(
.$UMOD
F167
P
VER 1.2
*** HMCS6800 CROSS LINKAGE EDITOR
NAME
SECTION START MODULE NAME
(
)
.$UTOD
P
F656
)
.$UTOL
(
P
F3AB
)
( LEDSP
LEDINT
P
F067
)
( LEDSP
MAIN
P
FOlD
DEFINED SYMBOL = 57
***
***
~HITACHI
1158
--*
SECTION 3. 8 X 4 KEY MATRIX
3.1 Hardware Description
3.1.1 Function
The key matrix routine scans an 8 x 4 key matrix using the HD6301XO. It converts the key data into
ASCII (A-Z, 1-6).
If two keys are pressed simultaneously, the data is invalid.
3.1.2 Microcontroller Applications
1. The interrupt routine is executed every 8 ms by the built-in 16-bit programmable timer (timer 1)
and output compare interrupt 1 (OCIl).
2. The interrupt routine executes a key scan outputting a strobe signal from port 6.
3. The interrupt routine prevents key chatter errors.
4. The key scan strobe signal is controlled by changing the I/O direction of the port 6 data direction
register (DDR). A diode is not necessary to prevent output signal collision since all ports that do
not output a strobe signal are input ports (high-impedance state).
~HITACHI
1159
3.1. 3 Circuit Diagram
Figure 3-1 is the application circuit diagram.
MCU
HD6301XO
+5 V
+5 V
4 MPO
5 MPI
8 NMI
7 STBY
33
22 pF 2 Vce
XTAL
f~'D 3
22 pF
+5 v
EXTAL
25
KRO
26
KRI
P62 27
KR2
P63 28
KR3
P60
P61
B
C
E
F
G
H
' =_ ____'KCO KCl KC2 KG3 KG4 KG5 KG6
P30,.?8
P31r=5:..!.7_ _ _ ____'
P32r5~6~---______~
P331-"5~5~______________~
P34~5~4~------------------~
P35r5~3~--------_________________'
P36r5~2~-----------------------------'
P37~5~1~------------------------------~
Figure 3-1. Key Scan Control Circuit
~HITACHI
1160
KG~/
3 .1.4 Pin Functions
Table 3-1 shows the pin functions at the interface between the HD6301XO and the key matrix.
Table 3-1.
Pin Functions
Pin Name
(HD630IXO)
P63
Input/
Output
Active Level
(High or Low)
8W~~t
Function
Low
Pin Name Program
(Key matrix) Label
Outputs strobe for
8 x 4 key matrix
retrieval.
KR3
bntPtut/
tgut
utJ
bntPttQul
Low
Low
KR1
P60
lrJl~~t
Low
KRO
P62
P61
P6DTR
KR2
P30
InEut
P31
InEut
P32
In~ut
KC2
P33
InEut
KC3
P34
KCO
Inputs 8 x 4 key
matrix key data.
P3DTR
KC1
In~ut
KC4
P35
In~ut
KC5
P36
InEut
KC6
P37
Input
KC7
3.1.5 Hardware Operation
The program prevents errors caused by key chatter (figure 3-2).
Key input
signal
'1M
'-y--J
Chatter
Key fetch
timing
(Timer interrupt)
Key input
decision
~
OFF
I I I
G)
® G)
CD®
G)
r
CD
First key data
®
Second key data
G) Third key data
+
Test for key input
Figure 3-2.
I
Chatter Prevention Timing
The key input signal is sampled every 8 ms.
If three consecutive key input signals are the same, the key input data is defmed. If two or fewer
signals are the same, the key input data is not defined, assuming that chatter has occurred.
~HITACHI
1161
3.2 Software Description
3.2.1 Program Module Configuration
Figure 3-3 shows the program module configuration for executing a key scan of an 8 x 4 key matrix.
K84MN
Main program 0
(Assembler
language)
Figure 3-3.
Program Module Configuration
Refer to Section 3.3, "Program Module Description" discusses these modules for details.
3 .2.2 Program Module Functions
Table 3-2 summaries the program module functions.
Table 3-2.
Program Module Functions
Program Module Library
No. Name
Function
Function
Language
0
Main program
K84MN
Initializes instructions, such as ORG,
LDS, and CLI, which do not exist in C.
Calls K84int function
ASM
1
Interrupt
reception
K84SCN
Receives and process OCI 1 interrupt
ASM
2
Initialization
K84int
Initializes global variables, port, and
timer
C
3
Key scan
K84san
Converts key data from 8 x 4 key matrix
into ASCII
C
Note:
C:
ASM:
C Language Program
Assembly Language Program
~HITACHI
1162
3.2.3 Program Module Sample Application (Main Program)
The flowchart in figure 3-4 is an example of an 8 x 4 key matrix key scan performed by the program
module in figure 3-3. The main program in Figure 3-4 calls the C language module and demonstrates
storing ASCII in global variable 'keyset'
main program
~#_$_F_F_.
__
S_P-l''''''''''''''''''''''''''''[ Initi.alize stack pointer
1-I-__k_8_4_in_t_....L.J ............................ [
Initialize global variables and timer used
in program module 'main', K84SCN
t-_O_.
__B_it_I-.-I............................ {
Enable interrupt
main
..... {
Convert key data from 8 x 4 key matrix
into ASCII
OCI 1 interrupt routine
k84san
.............. [
C Language program, 'k84 san' using the
OCI 1 interrupt
Execute 8 x 4 key matrix key scan in k84san
Fugure 3·4.
I
Program Module Flowchart
~HITACHI
1163
The C Language Program 'K84int ' (figure 3-5) initializes the timer, port, and global variables.
(
k84int
Initialize timer and port 6
Ox8
Ox 0
ox
1f40
•
•
•
'" TCSR1
'" P6DTR
'" OCR1
Initialize global variables
(
Return
Figure 3-5. Program Module Flowchart
~HITACHI
1164
The execution sequence of the C Language Program 'main' decides whether a key has been pressed
(figure 3-6). If a key has been pressed, K84san converts the scanned data, into ASCII and store the
result in grobal variable 'keyset'.
(
main
Tes," key has
,<
been depressed
keyonf! = 1
Yes
No
Convert key
number into
ASCII
Store ASCII
code in keyset
keydat .... keyset
Return
Clear flag testing
for key press
keyonf = 0
Figure 3-6. Program Module Flowchart
3.3 Program Module Description
The following pages describe the key Scan Subroutine.
I
~HITACHI
1165
Key Scan Module
Library Function: K84san
Function
The key scan module scans an 8 x 4 key matrix and stores key scan data in global variable keydat.
Arguments
Contents
Storage Locaton
No. of Bytes
keydat
1
Entry
Returns
key data
(global variable)
key data
keyonf
Indicator
(global variable)
1
Libraries Required for Program Execution
Library
Required/Not Required
Standard Library Function
C31LIB. OBI
Not required
Run-Time Routine
C31RUN. OBI
Required
C31RUNF. OBI
Not required
Specifications
ROM (bytes):
247
RAM (bytes):
16
Stack (bytes):
8
No of cycles:
1115
Reentrant:
No
Relocatable:
No
Interruptible:
Yes
@HITACHI
1166
Key Scan Module
Library Function: K84san
Description
Function Details
Argument Details: Global variable 'keydat' contains key scan data. Global variable 'keyonf
indicates that program module K84san is done. Flag functions are shown in table 3-3.
Table 3-3.
Keyonf Flag
Variable Name
Condition
Keyonf
o
Key scan data is not stored in global variable 'keydat'
1
Key scan has executed correctly and the key scan data has been
Indicates
stored in global variable 'keydat'
I
~HITACHI
1167
Key Scan Module
Library Function: K84san
o
®
Figure3-7.
Key ",essed {
Return
arguments
{
Key No.4 has been pressed
(In Figure 3-1 of
Hardware Description)
b15
keydat
bO
1-: - : 0: 41
b15
keyonf
keydat
keydat
1-: -:
0 : 1
bO
1
Program Module 'K84san' Execution Example
Example: Figure 3-7 showns an example of program module 'K84san' stoves execution.
If a key in
-
HD6301 XO internal register and
internal address space.
Not Used
$0040
$OOFF
$7FFF
$8000
$9FFF
$AOOO
$BFFF
$COOO
$DFFF
$EOOO
$FFFF
RAM
(192 Bytes)
Not Used
RAM
(HM6117)
PIA
(HD6321)
DORA/PORTA
CRA
DDRB/PORTB
CRB
Not Used
ACIA
(HD6350)
CTRUSTS
TDR/RDR
EPROM
(HN27C64)
Not Used
$BFFF
$COOO
$C001
$DFFF
Figure 4-2. System Memory Map
~HITACHI
1188
$AOOO
$A001
$A002
$A003
Allocation
RAM
PIA
ACIA
ROM
4.1. 5 Hardware Operation
Figure 4-3 shows the interface timing chart for the HD6301 YO and external memory (HN27C64,
HM6117).
~
E
ADDRESS
HD6301YO
R/TJ
tAD Decoder delay time
CE
tCE
RN27C64
'{
DE
tOR
"DSR
"OF.
tACC
~
DATA
(OUT)
Decoder delay time
I---
Data
read
{"PC<,
cCOl 2
tAce
DATA
(OUT)
1IM6117
}
'.c" {
write
DATA
(IN)
HN27C64
HM6117
[HR
~
VIE
HD6301YO
tDSR
tAD:
tDSR:
tHR:
tOW·
tCE:
tOE:
tACC:
tOH:
tAA:
tC01,2:
tWP:
tDW:
tDH:
twp
,"J
tDR
}-
Address delay time
Data set-up time
Data hold time
Data delav time
CE Output delay time
OE Outout delay time
Access time
Data output hold time
Address access time
CE1 ,CE 2 Output delay time
Write pulse width
Input data set time
Input data hold time
Figure 4-3. Interface Timing Chart for HD6301YO and External Memory
@HITACHI
1189
4.2 Software Description
4.2.1 Program Module Configuration
Figure 4-4 shows the program module configuration which displays data input from a console
typewriter, using the circuit in Figure 4-1.
EXPMN
Main program 0
(Assembler
language)
expin
Initialization
,
,,
expip
Receive
data
\.
.............................................................................................................................................................................................................................................................. .
Figure 4-4. Program Module Configuration
Refer to Section 4.3 "Program Module Description" discusses these modules for details.
4.2.2 Program Module Functions
Table 4-2 summaries the program module functions.
~HITACHI
1190
Table 4·2.
Program Module Functions
Program Module Library
No. Name
Function
Function
Language
0
Main program
EXPMN
Initializes instructions, such as ORG,
LDS, and CLI, which do not exist in C.
Calls expin function and main function
ASM
1
Interrupt
reception
EXPINP
Receives and processes IRQ interrupt
ASM
2
Initialization
expin
Initializes global variables, PIA, ACIA,
and LCD-II
C
3
Data processing
main
Displays key data, input from console
C
typewriter, on liquid crystal display (H2571)
and prints the data on the console typewriter
4
Receive data
5
expip
Receives key data from the console
typewriter through an IRQ interrupt
C
LCD-II initialization expint
Initializes LCD-II
C
6
Display Character
expdsp
Displays characters on LCD
C
7
Send data
expout
Sends data to console typewriter
C
Note:
C: C Language Program
ASM Assembly Language Program
I
~HITACHI
1191
4.2.3 Program Module Sample Application (Main Program)
The flowchart in Figure 4-5 is an example of the execution sequence of the program module in Figure
4-4 when it displays key data input from a console typewriter on a liquid crystal display and prints the
data on me console typewriter.
Main program
#$ FF .... SP
................... {
Initialize stack pointer
expin
.................. {
Initialize PIA, ACIA, LCD-II, and
global variables
.................... [
Enable interrupt
o ....
bit 1
~~;"
..... ..
"
,,[
After converting the key data input from the
console typewriter into ASCII code,
display the result on the liquid crystal
display (H2571) and print the result on
the console typewriter
IRQ interrupt routine
l-'---exP_i
P ---L.J • • •
Figure 4-5.
• • • • • •• {
Execute 'expip' to receive data from the
console typewriter and store it in
global variable 'keydat'
Program Module Flowchart
~HITACHI
1192
Figure 4-6 shows the execution sequence of C language program 'expin'. In 'expin', key data input
from console typewriter is displayed on the liquid crystal display (H2S71) and printed on the console
typewriter.
expin
1
Store function data in
entry argument func
x 30 ~ lunc
Clear global variable (0)
o
Select DORA of PIA
00 ~ * CRA
Store entry mode data
in entry argument
entry
x 06 ~ entry
ox
o
Select part A of PIA
as output
x If ~* CRA
o
expint function
Select port A register
Ox 04 ~*CRA
Set H2571 control
Signal
Ox 02 ~ * PIRA
Master reset ACIA
Ox97~*CR
Select OOR B of PIA
OO~ * CRB
ox
Initialize ACIA
Ox95~*CR
1 start bit + 8 bits 1
rr
data + 1 stop bit,
RTS +0, TIE= 0, RIE = 1
Select port B of PIA
as output
x If ~* OORB
o
Select port 5 bit 0
as IRQ pin
x 7d ~ * PSCR
1
o
I
Return
Figure 4·6. Program Module Flowchart
~HITACHI
1193
Figure 4-7 shows the execution sequence of C language program 'main'.
In 'main', key data input from console typewriter is displayed on the liquid crystal display (H2571)
and printed on the console typewriter.
main
Yes
¢O
Loop while input
data is found
while (1)
Test' k"l' dala (
~
has been
received
keydrf ! = 0
=0
Test if input data
is lowercase or
uppercase
keydat > = 'a' &&
keydat < = 'z'
e
No
Return
Clear key data
received flag
keydrf = 0
-
Set signal RTS of
ACIAlow
Ox 95 ~
* CR
Store outdat in
dspdat and keydat
outdat-C:dsPdat
keydat
expout function
expdsp function
Figure 4-7. Program Module Flowchart
4.3 Program Module Description
The following pages describle the external expansion modules.
~HITACHI
1194
Convert lowercase
into uppercase
keydat -= 20
1. Receive Data Module
Library Function: expip
Function
The receive data module receives data from console typewriter and stores key data in global variable
'keydat'.
Arguments
Contents
Storage Location
No. of Bytes
Received data
keydat
2
(ASCII code)
(global variable)
Received data flag
keydrf
Entry
Returns
2
(global variable)
Libraries Required for Program Execution
Library
Required/Not Required
Standard Library Function
Run-Time Function
C31LIB. OBJ
Not required
C31RUN.OBJ
Required
C31RUNF. OBJ
Not required
Specifications
Stack (bytes):
48
4
0
ROM (bytes):
RAM (bytes):
No of cycles:
63 (Note)
Reentrant:
No
Relocatable:
No
Interruptible:
No
I
Note: Ox indicates a hexadecimal number in C.
~HITACHI
1195
1. Receive Data Module
Library Function: expip
Description
Function Details
Argument details: Global variable 'keydat' contains I-byte of key data (ASCII) from the console
typewriter. Global variable 'keydrf is a flag indicating that data has been received. Table 4-3 shows
flag functions.
Example: Figure 4-8 shows an example of program module 'expip' execution. If key nan on the
console typewriter is pressed as shown in
CD, the received data is put in the key data buffer and oxff
is stored in 'keydrf as shown in (i).
~HITACHI
119!;l
1.
Receive Data Module
Library Function: expip
Q ______ 0 x 61
a: press
~
b15
®
Result
Global variable 'keydat'
1 byte data
('a' : 0 x 61)
Global variable 'keydrf'
o x ff
{
Figure 4-8.
keydat
1-: -:
b15
6 :
bO
11
keydrf
1-: -:
f : f
bO
I
Program Module expip Execution Example
Table 4-3. Flag Functions
Variable Name
Flag
Indicates
Keydrf
OxOO
No data has been received
Oxff
Data has been received and stored in buffer
User Notes
1. Initialize ACIA because ACIA is controlled by the microcontroller external extension. After
initialization ACIA can receive data from the console typewriter.
2. Clear bit I and enables interrupt for IRQ interrupt.
Variable Description
The global variables are stored in static memory (figure 4-9).
Variable name
Description
RAM
b15
keydat
keydrf
bO
IJ . ---I~
Figure 4-9.
Contains key data buffer for received data
Contains received data flag
Global Variable Storage
~HITACHI
1197
1. Receive Data Module
Library Function: expip
Sample Application
After ACIA is initialized and the interrupt is enabled, an IRQ, interrupt initiates program module
'expip' execution (figure 4-10),
*
*
*
CR
Ox 97;
CR
Ox 95;
P5CR
Ox 7d;
}
...... Initialize ACIA
}
Select bit 0 of port 5 as the IRQ,
...... interrupt pin
Figure 4-10.
Sample Application
Basic Operation
Figures 4-11 and 4-12 show ACIA control. Figure 4-11 shows ACIA initialization. Figure 4-12
shows now received data is read after an interrupt.
Note that this control method applies to the system in Figure 4-1 and memory map in Figure 4-2 .
....O_x_97_--._ _*_C_R........................... [
ACIA Master reset
....o_x_95_--._ _*_C_R........................... [
Initialize ACIA
(4800 bps, 1 start bit + 8 data bits + 1 stop bit,
enables interrupt during data reception)
Figure 4-11.
ACIA Control (Initialization)
~HITACHI
1198
1. Receive Data Module
Library Function: expip
Test bit 0 (RDRF) of status register to determine whether the
ACIA has received data or not (RDRF = 1: data has been received).
=1
Test if bit
(
o or status
register
(SR) is 1
o x d5
~
* CR
I [
I. . . . [ Re~d
. ......
/--------'
¢
1
Figure 4-12.
* RDR ~
keydat
Set signal RTS of ACIA to high to
prohibit sending data from console
typewriter
input data from received data
register
ACIA Control (Receiving Serial Data)
When data reception has been completed, set signal RTS to high to prohibit next data transfer.
Finally, store received data from RDR of ACIA in key data buffer.
~HITACHI
1199
1. Receive Data Module
Library Function: expip
PAD
C
ex pip
*0
T.s," data ,,,,.pHon (
has been completed
( * SR & 1) ! = 0)
=0
Set signal RTS to
high
x d5 --.- * CR
o
Store received data
in key data buffer
* RDR --.- keydat
Set flag indicating
data received
keydrf
Ox ff
--.-
Set signal RTS to
low
Ox95.- * CR
(
Return
Figure 4-13. Receive Data PAD
~HITACHI
1200
2. Send Data Module
Library Function: expout
Function
The send data module sends data to console the typewriter.
Arguments
Contents
Entry
Data to be sent
Storage Location
No. of Bytes
outdat
(global variable)
2
Returns
Libraries Required for Program Execution
Required/Not Required
Library
Standard Library Function
C31LIB. OBJ
Not required
Run-Time Routine
C31RUN.OBJ
Required
C31RUNF.OBJ
Not required
Specifications
ROM (bytes):
15
RAM (bytes):
2
Stack (bytes):
0
No of cycles:
30 (Note)
Reentrant:
No
Relocatable:
No
Interruptible:
Yes
Note: "No. of cycles" indicates the number of cycles required when TDR is empty.
~HITACHI
1201
2. Send Data Module
Library Function: expout
,Description
Function Details
Argument Details: Global variable 'outdat' holds data to be sent in ASCII to a console typewriter.
Example: Figure 4-14 shows an example of program module 'expout' execution. If entry argument
is as shown in CD. the console typewriter prints it as shown in (2) •
~HITACHI
1202
2. Send Data Module
Library Function: expout
External Routine: Program module 'expout' does not call any other program modules or
subroutines.
User Notes
1. Initialize ACIA because ACIA is controlled by the microcontroller. After initialization the ACIA
can transfer data to the console typewriter.
2. If previous data remains in TDR, program module 'expout' will not be executed until TDR is
cleared, so as not to destroy the remaining data.
CD
G[ob~ variable
{
'outdat'
(sending data
'A')
Before execution
entry argument
b15
1-:-:
TvpeA
®
Figure 4-14.
{
After execution
0
0
0
0
0
outdat
"
.,
A
4
:
bO
1
1
0
0
0
0
0
Program Module 'expout' Execution Example
Variable Description
The global variable is stored in static memory (figure 4-15).
Variable
Name
RAM
b15
outdat
Description
bO
1'----_ _---'1 }
Figure 4-15.
Contains character data to be sent to
console typewriter
Global Variable Storage
I
~HITACHI
1203
2. Send Data Module
Library Function: expout
Sample Application
Program module 'expout' is called after ACIA is initialized and data to be sent is stored (figure 4-16).
*
*
CR
Ox 97;
CR
Ox 95;
}
Initialize ACIA
outdat
Ox 41;
}
Store data to be send in entry argument
II
);
expout
II ...... ·.. ·
Figure 4-16.
Call expout
Sample Application
Basic Operation
1. Figure 4-17 shows how to control ACIA to send data.
,,,
,
,,,
....... {
:
Check bit 1 of status register (TORE) to test if
transmit register is empty (TORE = 1 : empty)
+
while ((
* SR & 2) ! =1)
: outdat
~ * TOR
f,
,,
,,
,,
I
:....... {
Load data to be sent into
transmit register
~
figure 4-17.
ACIA Control (Sending Serial Data)
2. Test if bit 1 of status register (TDRE) is "0" or "1". When TDRE is "1", store data to be sent in
TDR. When TDRE is "0" ,wait until TDRE becomes "1", because TDRE = 0 means data remains
in TDR.
~HITACHI
1204
2. Send Data Module
Library Function: expout
PAD
expout
Store data to be sent in
Test if TOR is empty
(TORE = 1)
TOR in ACIA and send data
while (( .. SR & 2) ! = 0)
outdat --..- .. TOR
Return
Figure 4-18. Send Data Module PAD
I
~HITACHI
1205
3.
Diagram Characters Module
Library Function: expdsp
Function
The display characters module stores ASCII in (DDRAM) LCD-II display RAM, and displays
characters on liquid crystal display.
Arguments
Contents
Entry
Storage Location
No. of Bytes
Display data
dspdat
2
(ASCII)
(global variable)
Returns
Libraries Required for Program Execution
Required/Not Required
Library
I
Standard Library Function
C31LIB. OBI
Not required
Run-Time Routine
C31RUN. OBI
Required
C31RUNF. OBI
Not required
Specifications
ROM (bytes):
144
RAM (bytes):
2
Stack (bytes):
0
No of cycles:
189 (Note)
Reentrant:
No
Relocatable:
No
Interruptible:
Yes
Note: "No. of cycles" in "Specifications" indicates the number of cycles when subroutine expbsy
executes in the minimum cycles.
~HITACHI
1206
3. Display Characters Module
Library Function: expdsp
Description
Function Details
Argument Details: Global variable 'dspdat' holds display data as 1 ASCII byte.
Example: Figure 4-19 shows an example of program module 'expdsp' execution. If entry argument
is as shown in -'a' && keydat<-'z')
keydat--Ox20;
f* Change lower case to upper *f
keydrf-O;
f* Clear flag of receive data *f
*CR-Ox95;
f* Set RTS=low *f
outdat=dspdat=keydat;
f* Set output data in area *f
expout();
f* Transmit data to console *f
expdsp();
f* Display characters on LCD-II *f
/*******************************.* ••••• *****.*.*.***** ••• ********.*.* •••• * •••• /
f*
f*
f*
NAME : EXPIN (INITIALIZE PIA,ACIA AND LCD-2)
*f
*f
*f
1··*******····*******···***·**······**·***··**····**** *** •• ****.*** ••• *.*****./
expin()
{
outdat=dspdat=keydrf=keydat=tncnt=func=entry=O;
f* Initialize *f
*CRA =OxOO;
f* Select data direction registcr A *f
*DDRA=Oxff;
f* Select port A as output *f
*CRA =Ox04;
f* Select peripheral register A *f
*PIRA=Ox02;
f* Set RS=O, RfW=l, E=O *f
-CRB =OxOO;
f* Select data direction register B *f
*DDRB=Oxff;
f* Select port B as output *f
*CRB =Ox04;
f* Select peripheral register n *f
func=Ox30;
f~ Set function data *f
entry=Ox06;
f* Set entry mode data *f
expint();
f* Initialize LCD-II *;
setins(OxOe);
f* Set instruction to LCD-II *f
*CR=Ox97;
f* Master reset of ACIA *f
*CR=Ox95;
f* Initialize ACIA *f
*P5CR=Ox7d;
f* Initialize port 5 *f
~HITACHI
1222
/*******************.******************************************.**************/
f*
f*
f*
NAME : EXPIP
*f
*f
*f
(RECEIVE DATA)
/.**************************************************************.**.**.*******/
f*
f*
f*
f*
f*
ENTRY
HETUHNS
*f
*f
*f
*f
*f
NOTHING
KEYDAT (RECEIVED DATA)
KEYDRF (RECEIVED FLAG)
/**.* •• ***.********************************.* •••• ***** ****·*****·*****·*******1
expip()
{
f*
f*
f*
f*
f*
i f «*SR&l) !=O)
*CR=Oxd5;
keydat = *RDR;
keydrf=Oxff;
*CR=Ox95;
Test if data is received *f
Set RTS=high *f
Set receive data *f
Oxff if receive data is set
Set RTS=low *f
*f
/******************************************.**********************************/
f*
f*
f*
NAME: EXPINT
*f
*f
*f
(INITIALIZE LCD-2)
/*****.***********************************************************************/
f*
f*
ENTRY
f*
f*
f*
RETURNS
*f
*f
FUNC
(FUNCTION DATA)
ENTRY (ENTRY MODE DATA)
NOTHING
*f
*f
*f
/ ••••••• *.** ••••• *******.*.***.** •• ***.******.******.**.***.****.*************/
expint()
{
for(tncnt=0;tncnt<3;tncnt++)
expit();
expins(Ox30) ;
*PIRA=Ox02;
setins(func) ;
setins(Ox08) ;
setins(OxOI);
setins(entry) ;
{
f* Reset LCD-II three times *f
f* Execute I5ms software timer *f
f* Write function data to LCD-II *f
f*
f*
f*
f*
f*
Set
Set
Set
Set
Set
RfW=1 *f
function data to LCD-II *f
instruction (display off) *f
instruction (display clear) *f
entry mode data *f
/*.**************************************.************************************/
f*
f*
f*
NAME: EXPDSP
(DISPLAY CHARACTERS)
*f
*f
*f
/*.*****.*********************.******.***************.************************/
f*
f*
f*
ENTRY
RETURNS
DSPDAT (DISPLAY DATA)
NOTHING
f*
*f
*
*f
*f
/**************************************************.**.*** •• ******************/
I
~HITACHI
1223
expdsp ()
(
1*
1*
1*
1*
1*
1*
expbsy() ;
*PIRA=Ox04;
*PIRA=Ox05;
*PIRB=dspdat;
*PIRA=Ox04;
*PIRA=Ox02;
Check busy flag *1
Set RS=l, R/W=O, E=O *1
Set E=l *1
Output data to LCD-II *1
Set E=O *1
Set R/W=l *1
, •••• *** •• ** ••••• **.*******.**.**.***.****.*** •• ***.** ************************1
1*
1*
1*
*1
*1
*1
NAME : EXPOUT(SEND DATA)
/.**** •• ********** ••• *.**.******* ••• ***.*.*.*.****** •• ***** •••• *.*.*******.*.*/
1*
1*
1*
1*
ENTRY
RETURNS
*1
*1
*1
*1
OUTDAT (DATA TO BE SENT)
NOTHING
1·***************************·*·***********·****·*·***·***********************1
expout()
(
while«*SR&2)!=O)
*TDR=outdat;
1* Transmission has been completed *1
1* Set transmit data in TDR *1
/****** ••• ********** •• ***********************************************.********/
/*
*1
/*
NAME : EXPBSY
/*
;*.****************** ••
*1
*1
(CHECK BUSY FLAG)
******* •• *** ••• *********** ••• ********.*****************/
expbsy( )
{
int
acca=Ox80;
*CRB=OxOO;
*DDRB=OxOO;
*CRB=Ox04;
*PIRA=Ox02;
1*
1*
1*
1*
Set data direction register B *1
Select port B as input *1
Select peripheral register B *1
Set RS=O, R/W=l, E=O *1
1*
1*
1*
1*
Set E=l *1
Set PIRB in working area
Set E=O *1
Read busy flag *1
do {
*PIRA=Ox03;
acca=*PIRB;
*PIRA=Ox02;
acca &= Ox80;
while (acca==Ox80);
*CRB=OxO;
*DDRB=Oxff;
*CRB=Ox04;
*1
1* Select data direction register B *1
1* Select port B as output *1
1* Select peripheral register B *1
}
/*.******.** •• **** •••••• ********** ••••• ****.* •••••• ********.**************** •• /
1*
1*
1*
NAME : EXPINS
(STORE INSTRUCTION)
*1
*1
*1
/*** •• ** ••••• **.******* •• ****** ••• * ••••••• ** •• * ••••• ** ••• ** ••••• * •• *.* •• ****.*/
expins(insdat)
lnt
insdat;
{
*PIRA=OxOO;
*PIRA=OxOl;
*PIRB=insdat;
*PIRA=OxOO;
1* Set RS=O, R/W=O, E=O *1
1* Set E=l *1
1* Set instruction in peripheral B *1
I*Set E=O *1
~HITACHI
1224
j ••••••••••••••••••••••••••••••••••••••••••••••••••••• •••••••••••••••.•• * •••••• ,
/*
/*
/*
NAME: SETINS
(SET INSTRUCTION TO LCD-2)
*/
*/
*/
,.............................................................................. ,
setins(lnsdat)
int
insdat:
(
expbsy{) :
expins(insdat):
I
~HITACHI
1225
4.4.3 Output Object Listing of C Compiler
••• CP/M-68K 6301/6801/6800 CROSS MACROASSEMBLER
ERR
SEQ
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
LOC
OBJECT
PROGRAM EXPC
NAM
OPT
MACR
EXPC
REL
MSEX
CLRA
TSTB
BPL \.0
COMA
\.0 EQU •
ENDM
MLBRA MACR
JMP \0
ENDM
MLBSR MACR
JSR \0
ENDM
MLBEQ MACR
BNE \.0
JMP \0
\.0 EQU •
ENDM
MLBNE MACR
BEQ \.0
JMP \0
\.0 EQU •
ENDM
MLBGT MACR
BLE \.0
JMP \0
\.0 EQU •
ENDM
MLBGE MACR
BLT \.0
JMP \0
\.0 EQU •
ENDM
MLBLT MACR
BGE \.0
JMP \0
\.0 EQU •
ENDM
MLBLE MACR
BGT \.0
JMP \0
\.0 EQU •
ENDM
MLBUI MACR
BLS \.0
JMP \0
\.0 EQU •
ENDM
MLBLS MACR
BUI \.0
JMP \0
\.0 EQU •
ENDM
MLBCC MACR
~HITACHI
1226
V1.2 •••
*** CP/M-68K 6301/6801/6800 CROSS MACROASSEMBLER
ERR
SEQ
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066B
00067B
00068R
00069B
00070B
00071B
00072B
00073B
00074B
00075B
00076B
00077B
00078B
00079B
00080P
00081P
00082P
00083P
00084P
00085P
00086P
00087P
00088P
00089P
00090P
00091P
00092P
00093P
00094P
00095P
00096P
00097P
00098P
00099P
00100P
00101P
00102P
00103P
00104
00105
00106P
00107P
00l08P
00l09P
OOllOP
OOlllP
OO1l2P
LOC
0000
0000
0002
0002
0004
0004
0006
0006
0008
0008
OOOA
OOOA
OOOC
OOOC
0000
0000
0002
0004
0006
0008
OOOB
0000
OOOF
0012
0014
0016
0019
001B
001C
0010
001F
0022
0025
0027
0029
002B
0020
0030
OBJECT
20
OC
27
OE
8C
20
OE
8C
2E
OC
83
00
4F
5F
00
CE
CC
E7
OC
00
00
0002
A
0002
A
0002
A
0002
A
0002
A
0002
A
0002
A
31 0033
04
B
20 0033
06
B
0061 A
OE 001B
06
B
007A A
07 001B
06
B
0020 A
06
B
04
COOO
0095
00
06
02
00
V1.2 ---
PROGRAM EXPC
B
A
A
A
B
B
B
0033 P
0033 P
0033 20 CO 0002
0035 39
0036
0036 4F
0037 5F
0038 00 OC
B
003A 00 OA
B
Bes \.0
JMP \0
\.0 EQU ENOM
MLBCS MACR
BCC \.0
JMP \0
\.0 EQU *
EN OM
BSCT
OUTOAT BSZ
RSr.1'
DSPOAT BSZ
BSCT
KEYORF BSZ
BSCT
KEYOAT BSZ
BSCT
TNCNT BSZ
BSCT
FUNC
BSZ
BSCT
ENTRY BSZ
PSCT
BRA
.SA003 LOO
BEQ
LOX
CPX
BLT
LOX
CPX
BGT
LOO
SUBO
STO
.SA005 CLRA
CLRB
STO
LOX
LOO
STAB
LOO
STO
STO
MLBSR
MLBSR
.SA004 EQU
MAIN
EQU
.SA002 BRA
RTS
PSCT
EXPIN CLRA
CLRB
STO
STO
2
2
2
2
2
2
2
.SA002
KEYORF
.SA004
KEYOAT
#9J
.$A005
KEYOAT
#122
.SA005
KEYOAT
#32
KEYOAT
KEYORF
#-16384
#149
O,X
KEYOAT
OSPOAT
OUTOAT
EXPOUT
EXPOSP
-*
.SA003
ENTRY
FUNC
I
~HITACHI
1227
•••
ERR
CP/M-68K 6301/6801/6800 CROSS MACROASSEMBLER
SEQ
00113P
00114P
00115P
00116P
00117P
00118P
00119P
00120P
00121P
00122P
00123P
00124P
00125P
00126P
00127P
00128P
00129P
00130P
00131P
00132P
00133P
00134P
00135P
00136P
00137P
00138P
00139P
00140P
00141P
00142P
00143P
00144P
00145P
00146P
00147~
00148
00149P
00150P
00151P
00152P
00153P
00154P
00155P
00156P
00157P
00158P
00159P
00160P
00161P
00162P
00163P
00164P
00165P
00166P
00167P
00168P
PROGRAM EXPC
LOC
OBJECT
003C
003E
0040
0042
0044
0046
0049
004B
004E
0051
0053
0056
0059
005B
005E
0061
0063
0066
0067
0068
006A
006D
0070
0072
0075
0078
007A
007D
007F
0082
0084
0087
008A
008D
0090
0093
0095
0098
009B
009D
OOAO
00A3
00A5
00A6
00A6
00A9
OOAB
OOBO
00B1
00B3
00B5
00B8
OOBB
OOBD
OOCO
00C2
DD 08
DD 06
DD 04
DD 02
DD 00
CE A001
E7 00
CE AOOO
CC OOFF
E7 00
CE A001
CC 0004
E7 00
CE AOOO
CCOO02
E7 00
CE A003
4F
5F
E7 00
CE A002
CC OOFF
E7 00
CE A003
CC 0004
E7 00
CC 0030
DD OA
CC 0006
DD OC
B
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
CC OOOE
A
CE
CC
E7
CE
CC
E7
CE
CC
E7
39
A
A
A
A
A
A
A
A
A
COOO
0097
00
COOO
0095
00
0014
007D
00
CE COOO
E6 00
4F
C4
27
CE
CC
E7
CE
E6
A
A
A
A
A
A
A
A
B
A
B
A EXPIP
A
01
A
21 00D6
COOO A
00D5 A
00
A
COOl A
00
A
TNCNT
STD
KEYDAT
STD
STD
KEYDRF
STD
DSPDAT
OUTDAT
STD
#-24575
LDX
O,X
STAB
#-24576
LDX
#255
LDD
O,X
STAB
LDX
#-24575
#4
LDD
O,X
STAB
#-24576
LDX
#2
LDD
O,X
STAB
#-24573
LDX
CLRA
CLRB
O,X
STAB
#-24574
LDX
#255
LDD
O,X
STAB
#-24573
LDX
LDD
#4
O,X
STAB
#48
LDD
FUNC
STD
LDD
#6
STD
ENTRY
MLBSR EXPINT
#14
LDD
MLBSR SETINS
LDX
#-16384
LDD
#151
,O,X
STAB
#-16384
LDX
LDD
#149
O,X
STAB
#20
LDX
LDD
#125
O,X
STAB
RTS
PSCT
LDX
#-16384
LDAB
0,"
MSEX
CLRA
#1
ANDB
BEQ
.SA008
#-16384
LDX
LDD
#213
O,X
STAB
#-16383
LDX
O,X
LDAB
MSEX
*
HITACHI
1228
V1.2 •••
*** CP/M-68K 6301/6801/6800 CROSS MACROASSEMBLER
ERR
SEQ
00169P
00170P
00171P
00172P
00173P
00174P
001.75P
00176P
00177P
0017BP
00179P
OOlBOP
00181P
001B2P
001B3P
001B4P
001B5P
001B6P
001B7P
001BBP
001B9P
00190P
0019lP
00192P
00193P
00194P
00195P
00196P
00197P
0019BP
00199P
00200P
00201P
00202P
00203P
00204P
00205P
00206P
00207P
0020BP
00209P
00210P
00211P
00212P
00213P
00214P
00215P
00216P
00217P
00218P
00219P
00220P
00221P
00222P
00223P
00224
LOC
OBJECT
00C7
00C9
OOCC
OOCE
OODI
00D4
00D6
00D7
00D7
OODB
00D9
OODB
OODE
OOEI
00E4
00E6
00E9
OOEB
OOED
OOFO
00F2
00F5
OOFB
OOFA
OOFC
OOFF
0102
0105
010B
010B
010D
0110
0111
0111
0114
0117
011A
011C
011F
0122
0124
0127
0129
012B
012E
0131
0133
0136
0139
013B
013C
013C
013E
0141
0143
DD
CC
DD
CE
CC
E7
39
06
OOFF
04
COOO
0095
00
B
A
B
A
A
A
.$A008
4F
EXPINT
5F
20 OE 00E9
.$AOlO
CC 0030 .A
DC
C3
DD
DE
BC
2D
CE
CC
E7
DC
Vl.2 ***
PROGRAM EXPC
OB
B
0001 A
DB
B .. 1
OB
B .$AOll
0003 A
E9 OODB
AOOO A
0002 A
00
A
OA
B
CC 0008
A
CC 0001
A
DC DC
B
39
EXPDSP
CE
CC
E7
CE
CC
E7
CE
DC
E7
CE
CC
E7
CE
CC
E7
39
AOOO
0004
00
AOOO
0005
00
A002
02
00
AOOO
0004
00
AOOO
0002
00
20
CE
DC
E7
07 0145
COOl A .$A015
00
B
00
A
0145 P EXPOUT
A
A
A
A
A
A
A
B
A
A
A
A
A
A
A
STD
LDD
STD
LDX
LDD
STAB
RTS
PSCT
CLRA
CLRB
BRA
MLBSR
LDD
MLBSR
LDD
ADDD
STD
LDX
CPX
BLT
LDX
LDD
STAB
LDD
MLBSR
LDD
MLBSR
LDD
MLBSR
LDD
MLBSR
RTS
PSCT
MLBSR
LDX
LDD
STAB
LDX
LDD
STAB
LDX
LDD
STAB
LDX
LDD
STAB
LDX
LDD
STAB
RTS
PSCT
BRA
LDX
LDD
STAB
EQU
KEYDAT
#255
KEYDRF
#-163B4
#149
O,X
.. 1
EXPIT
#4B
EXPINS
TNCNT
#1
TNCNT
TNCNT
#3
.$AOlO
#-24576
#2
O,X
FUNC
SETINS
#B
SETINS
#1
SETINS
ENTRY
SETINS
EXPBSY
#-24576
#4
O,X
#-24576
#5
O,X
#-24574
DSPDAT
O,X
#-24576
#4
O,X
#-24576
#2
O,X
.$A014
#-16383
OUTDAT
O,X
*
I
~HITACHI
1229
•••
ERR
CP/M-68K 6301/6801/6800 CROSS
SEQ
00225P
00226P
00227P
00228P
00229P
00230P
00231P
00232P
00233P
00234P
00235P
00236P
00237P
00238P
00239P
00240P
00241P
00242P
00243P
00244P
00245P
00246P
00247P
00248P
00249P
00250P
00251P
00252P
00253P
00254P
00255P
00256P
-o0257P
00258P
00259P
00260P
00261P
00262P
00263P
00264P
00265P
00266P
00267P
00268P
00269P
00270P
00271P
00272P
00273P
00274P
00275P
00276P
00277P
00278P
00279P
00280P
MAC~OASSEMBLER
LOC
OBJECT
0145
0148
014A
014F
0150
0152
0154
0155
0155
0156
0159
015A
015C
015F
0160
0161
0163
0166
0168
016B
016E
0170
0173
0176
0178
017B
017E
0180
0183
0185
018A
018B
018D
0190
0193
0195
0196
0198
0199
019B
0190
019F
01A2
01A4
01A7
01A8
01A9
01AB
01AE
01B1
01B3
01B6
01B9
01BB
01BC
01BD
CE COOO
E6 00
#-16384
O,X
4F
C4
26
39
#2
.$A015
3C
CC
30
ED
CE
4F
5F
E7
CE
E7
CE
CC
E7
CE
CC
E7
CE
CC
E7
CE
E6
30
ED
CE
CC
E7
30
EC
4F
C4
ED
EE
8C
27
CE
4F
5F
E7
CE
CC
E7
CE
CC
E7
38
39
PROGRAM EXPC
A .$A014 LDX
A
LDAB
MSEX
CLRA
02
A
ANDB
EA 013E
BNE
RTS
PSCT
EXPBSY PSHX
0080 A
LDD
TSX
00
A
STD
A003 A
LDX
CLRA
CLRB
00
STAB
A
A002 A
LDX
00
A
STAB
A003 A
LDX
0004 A
LDD
00
A
STAB
AOOO A
LDX
0002 A
LDD
00
A
STAB
AOOO A .$A017 LDX
0003 A
LDD
00
A
STAB
A002 A
LDX
00
A
LDAB
MSEX
TSX
00
A
STD
AOOO A
LDX
0002 A
LDD
00
A
STAB
TSX
00
LDD
A
CLRA
80
A
ANDB
00
STD
A
00
LDX
A
0080 A
CPX
D4 0178
BEQ
A003 A
LOX
CLRA
CLRB
00
STAB
A
A002 A
LOX
OOFF A
LOD
00
A
STAB
A003 A
LDX
0004 A
LDD
00
A
STAB
PULX
RTS
PSCT
#128
O,X
#-24573
O,X
#-24574
O,X
#-24573
#4
O,X
#-24576
#2
O,X
#-24576
#3
O,X
#-24574
O,X
O,X
#-24576
#2
O,X
O,X
#128
O,X
O,X
#128
.$A017
#-24573
O,X
#-24574
#255
O,X
#-24573
#4
O,X
~HITACHI
1230
V1.2 •••
.** CP/M-68K 6301/6801/6800 CROSS MACROASSEMBLER
ERR
••••
SEQ
LOC
OBJECT
VI. 2 • **
PROGRAM EXPC
00281P 01BO 37
EXPINS PSHB
00282P 01BE 36
PSHA
00283P 01BF CE AOOO A
LDX
00284P 01C2 4F
CLRA
00285P 01C3 5F
CLRB
00286P 01C4 E7 00
A
STAB
00287P 01C6 CE AOOO A
LOX
00288P 01C9 CC 0001 A
LOO
00289P 01CC E7 00
A
STAB
00290P 01CE CE A002 A
LOX
00291P 0101 3C
PSHX
00292P 0102 30
TSX
00293P 0103 EC 02
A
LOO
00294P 0105 38
PULX
00295P 0106 E7 00
A
STAB
00296P 0108 CE AOOO A
LOX
00297P 010B 4F
CLRA
00298P 010C 5F
CLRB
00299P 0100 E7 00
A
STAB
00300P 010F 38
PULX
00301P OlEO 39
RTS
00302P 01E1
PSCT
00303P 01E1 37
SETINS,. PSHB
00304P 01E2 36
PSHA
00305P 01E3
MLBSR
00306P 01E6 30
TSX
00307P 01E7 EC 00
A
LOO
00308P 01E9
MLBSR
00309P 01EC 38
PULX
00310P OlEO 39
RTS
00311
XOEF
00312
XOEF
00313
XOEF
00314
XOEF
00315
XOEF
00316
XDEF
00317
XDEF
00318
XDEF
00319
XDEF
00320
XREF
00321
END
TOTAL ERRORS 00000--00000
#-24576
O,X
#-24576
#1
O,X
#-24574
2,X
O,X
#-24576
O,X
EXPBSY
O,X
EXPINS
EXPOSP
SETINS
EXPINS
EXPINT
EXPBSY
EXPIN
EXPOUT
MAIN
EXPIP
EXPIT
~HITACHI
1231
4.4.4
Linkage Listing
*** HMCS6800 CROSS LINKAGE EDITOR
LOAD;B:EXPMN.OBJ,B:EXPC.OBJ,C31RUN.OBJ
STRP;$FOOO
STRB;$60
STRD;$40
OPT;MAP,SYM
EXEC
VER 1.2 ***
*** HMCS6800 CROSS LINKAGE EDITOR
*** UNDEFINED SYMBOLS ***
VER 1.2 ***
NAME
SECTION
. ERROR
UNDEFINED SYMBOL; 1 (Note)
MODULE NAME
(
)
Note: There is an UNDEFINED SYMBOL = 1 (library function, ERROR) in the link information
but it does not influence the execution of this program. The library function or run-time
routine call the ERROR service routine when 0 is used as a divisor in division or modulo
operation. Strictly speaking, the user should create an ERROR funcion. However it is never
used in this program, so it is just displayed as an UNDEFINED SYMBOL.
(When the library function and run-time routine are not linked, the UNDEFINED SYMBOL is
not displayed.)
* ** HMCS6800 CROSS LINKAGE EDITOR
*** MAP LIST ***
** SECTION LOAD MAP
SECTION
A
B
C
D
P
** MODULE LOAD MAP
NAME
EXPC
SIZE
0016
OOOE
0000
0004
07DA
START
FFEA
0060
END
FFFF
006D
COMMON-SIZE
0040
FOOO
0043
F7D9
0000
0000
BSCT
DSCT
0040
PSCT
FOOO
F01A
F208
SIZE
START
0060
** COMMON LOAD MAP
NAME
COMMON ;
SECTION
0
~HITACHI
1232
VER 1.2 ***
0000
*** HMCS6800 CROSS LINKAGE EDITOR
VER 1.2
DEFINED SYMBOLS ***
NAME
SECTION START MODULE NAME
.$DADD
(
)
P
F7D9
.$DCMP
(
)
P
F7D9
.$DDEC
(
)
P
F7D9
.$DDIV
(
)
P
F7D9
.$DINC
(
)
P
F7D9
.$DMOV
(
P
)
F7D9
.$DMUL
(
)
P
F7D9
.$DNEG
(
)
P
F7D9
.$DSTK
(
)
P
F7D9
.$DSUB
(
)
P
F7D9
.$DTOF
(
)
P
F7D9
.$DTOI
(
)
P
F7D9
.$DTOL
(
)
P
F7D9
.$DTST
(
P
F7D9
)
.$FDEC
(
)
P
F7D9
.$FINC
(
)
F7D9
P
.$FMOV
(
P
)
F7D9
.$FREG
(
D
0040
)
.$FTOD
(
P
)
F7D9
.$FTST
P
(
)
F7D9
.$IASL
(
)
F27D
P
.$IASR
(
)
P
F292
.$IDIV
(
P
)
F23F
.$IMOD
(
)
P
F2BC
.$IMUL
(
)
P
F208
.$ITOD
(
)
P
F7D9
. $ITOL
(
)
P
F51D
.$LADD
(
)
P
F32F
.$LAND
(
)
P
F432
. $LBIT
(
P
F600
)
.$LCMP
(
P
)
F4BF
.$LCPL
(
)
P
F501
.$LDEC
(
~::;.:to
)
P
.$LDIV
(
)
P
F3E3
.$LINC
(
)
P
F53B
.$LMOD
(
P
)
F40A
.$LMOV
(
)
P
F30B
.$LMUL
(
)
P
F361
.$LNEG
(
)
P
F4EC
.$LOR
(
)
P
F44D
.$LSHL
(
P
)
F483
.$LSHR
(
)
P
F4A1
.$LSTK
(
)
F55B
P
.$LSUB
(
)
P
F348
.$LTOD
(
P
)
F7D9
.$LTST
(
P
)
F576
.$LXOR
(
)
P
F468
.$SBIT
(
)
P
F723
.$SW1
(
)
P
F76B
(
)
.$SW2
P
F79A
(
)
.$UDIV
P
F25B
.$ULSR
(
)
P
F2A7
.$UMOD
(
)
P
F2EA
***
I
~HITACHI
1233
VER 1.2 ***
*** HMCS6800 CROSS LINKAGE EDITOR
NAME
SECTION START MODULE NAME
(
)
.$UTOD
P
F7D9
(
)
.$UTOL
P
F52E
( EXPC
)
EXPBSY
P
F16F
( EXPC
)
EXPDSP
P
F12B
( EXPC
)
EXPIN
P
F050
( EXPC
)
EXPINS
P
F1D7
( EXPC
)
EXPINT
P
FOFl
( EXPC
)
EXPIP
P
FOCO
(
)
EXPIT
FOOA
P
( EXPC
)
EXPOUT
F15F
P
( EXPC
)
MAIN
P
F04D
( EXPC
)
SETINS
P
F1FB
65
DEFINED SYMBOL =
~HITACHI
1234
I
APPENDIX A. C Program and Assembly Program
Comparison
This appendix compares application programs previously introduced assembly language system
application examples to the C language examples in this application note.
(Assembly language programs are described in the 6301 APPLICATION NOTES (Hardware)).
In general, the size of the C language program is greater than that of the assembly language program.
These examples are hardware control programs that are difficult to write in C and show how ro use
the 6301 C language compiler. The run-time routines are not included in the C language program size
descriptions.
A.1
Darlington Transistor Drive (LED Dynamic Display)
Table A-1 compare Darlington Transistor Drive Routines written in C and assembler.
Table A-I.
Program Comparison
Item
Memory Size (Bytes)
No. of Cycles (Machine cycle)
CProgram
131
200
Assembly program
82
120
Cprogram to
1.6
1.67
assembly program ratio
I
~HITACHI
1235
A.2 8 x 4 Key Metrix
Table A-2 compares 8 x 4 key Matrix Routines written in C and assembler.
Table A-2.
Program Comparison
Item
Memory Size (Bytes)
No. of Cycles (Machine cycle)
CProgram
336
1240
Assembly program
181
373
C program to
assembly program ratio
1.86
3.32
A.3
External Expansion
Table A-3 compares External Expansion Routines written in C and assembler.
Table A-3.
Program Comparison
Item
Memory Size (Bytes)
No. of Cycles (Machine cycle)
CProgram
518
1347
Assernblyprogram
318
572
Cprogram to
assembly program ratio
1.63
2.35
@HITACHI
1236
HD6301/HD6303 SERIES HANDBOOK
Section len
APPENDIX
1. HD6301Vl/HD6303R 0. - and A
2. HD6301XO/HD6303X Oscillator Circuit
3. Wide lemperature Range Specifications
-40°C to 85°C (J Version)
@HITACHI
1237
. ~HITACHI
1238
Section 10-Appendix
1. HD6301V1/HD6303R Q and A
Table of Contents
Page
1.
HD6301V1/HD6303R Q & A ............................................. .
(a)
(1)
(b)
1239
Parallel Port
Process to Use a Port as an Output ....... ; ........................... .
1241
Serial Port
(1)
Relation between Writing into the FRC and SCI Operation ................. .
1242
(2)
Writing into the FRC during Serial Receiverfransmit ...................... .
1243
(3)
RDRF State When SCI Receiving ..................................... .
1244
(4)
Serial 110 Operation ................................................ .
1245
(5)
Serial 1/0 Register Read ............................................ .
1246
(6)
Detection of the HD6301V1 Serial Start Bit ............................. .
1247
(c)
TimerlCounter
(1)
Free Running Counter Read ......................................... .
1249
(2)
Preset Method of the Free Running Counter ............................ .
1250
(d)
(1)
(e)
BUS Interface
Output of Address Strobe (AS) in the Multiplexed Mode ................... .
1252
Interrupt
(1)
IRQ1 Acceptance ............................' ...................... .
1253
(2)
Timer Interrupt and External Interrupt. ................................. .
1254
(3)
IRQ1 Interrupt and Other Interrupts ................................... .
1255
(4)
CLilnstruction and Interrupt Operation ................................ .
1257
(f)
(1)
(g)
Oscillator
Relation between the External Clock (EXTAL Clock) and Enable Clock (E Clock)
1258
Reset
(1)
Constants of the Reset Circuit. ....................................... .
1259
(2)
Schmitt Trigger Circuit of RES ....................................... .
1260
(3)
1/0 Port State on Resetting .......................................... .
1261
(4)
SCI (Pin 39) State on Resetting ....................................... .
1262
(5)
Port Output after Resetting .......................................... .
1263
(h)
(1)
(2)
Low Power Consumption
.
1/0 Port State During Standby ........................................ .
Schmitt Trigger Circuit of STBY ....................................... .
1264
1265
~HITACHI
1239
I
· (3)
Return from Standby Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1266
(4)
Going into the Standby Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1267
(5)
Timing for the Standby Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1268
I'
EPROM-on-Package
(i)
(1 )
Usage of EPROM Socket Pins for the HD63P01M (No.1). .. . . . .. . . .. . . . . . ..
1269
(2)
Usage of EPROM Socket Pins for the HD63P01 M (No.2). . . . . . . . . . . . . . . . . ..
1270
(3)
Usage of EPROM Socket Pins for the HD63P01 M (No.3) . . . . . . . . . . . . . . . . . ..
1271
"
0)
Software
(1)
Usage of Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1272
(2)
Usage of Bit Manipulation Instructions to the Port. . . . . . . . . . . . . . . . . . . . . . . ..
1274
(k)
(1)
Others
RAM Access Disable during Program Execution . . . . . . . . . . . . . . . . . . . . . . . . ..
1275
2.
HD6301XO/HD6303X Oscillator Circuit. ...................................... 1276
3.
Wide Temperature Range Specifications -40°C to +85°C (J Version) .............. 1283
HD6301V1, HD63A01V1, HD63B01V1 ........................................... 1284
HD6301XO, HD63A01XO, HD63B01XO .......................................... 1289
HD6301Y0, HD63A01Y0, HD63B01YO, HD63C01Y0 ............................... 1294
HD6303R, HD63A03R, HD63B03R ...................... '" .................... 1300
HD6303X, HD63A03X, HD63B03X .... , ........................................ 1305
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y .................................... 1310
~HITACHI
1240
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD6301V Questions & Answers
Type
I
I
HD6301V1
Device
HD6303R
Theme Process to Use a Port as an Outputs
J
4S
8M
16M
Software
*8S
SBC
Evaluation kit Emulator, SD
24,
1983
Date Nov.
Question I
1, When using an I/O port as an output, is the data
stored to the Data Register or is the Data
Direction Register (DDR) set at first?
Answer J
1, Store the data to the Data Register at first and
then set the DDR (DDR=l) ; if not, unknown data is
output from the port.
I
Classification
* Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consm.
EPROM-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I
Semiconductor Data Book
- 8-Bit Single Chip
Microcomputer Other Data
Title I
Reference Q & A Sheet
~
Supplement I
The DDR defines an I/O port as an input or output.
DDR=l : output
DDR=O : input
@HITACHI
1241
I
HD6301 V Questions & Answers - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
I
Type
I
HD6301 VI
4S
Software
*8S
8M
16M
Device
SBC
HD6303R
Evaluation kit, Emulator
SD
Theme Relation between Writing into the FRC and SCI Date Nov. 24, 1983
Operation
Classification
Question I
Parallel Port
1, How are writing into the timer Free Running
Counter(FRC) and the Serial Communication Inter* Serial Port
face(SCI) related?
Timer/Counter
BUS Interface
Interrupt
AID Converter
Oscillator
Reset
Low Power Consm.
EPROM-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Answer I
Applicable Manual
1 , The source of the clock input to the SCI Shift
Title I
Registers is the timer FRC.
Therefore, if new data is writteri into the FRC,
SCI operations are disturbed.
See the following diagram.
I
Other Data
:Titlel
1$09 $Oj
1
J, R/W
E
JL~.FRC
I JL
Receive Shift
Register
I
Baud Rate
Generator
Transmit Shift
Register
*
A write into the FRC
operations.
~s
prohibited during SCI
Supplement I
~HITACHI
1242
I
Reference Q £. A Sheet
~
QA63l-002A
QA631-00BA
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD6301V Questions & Answers
I
I
SoftwarE
4S
8M
16M
HD6301Vl
*8S
Device
SBC
SD
Evaluation kit Emulator
HD6303R
24,
1983
ThemE Writing into the FRC during Serial
Date Nov.
Receive/Transmit
Classification
Question I
Parallel Port
1 , Is it prohibited to write data into the Free
Running Counter(FRC) during serial receive/trans- * Serial Port
Timer /Coun ter
mit?
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consm.
EPROM-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Answer I
Title I
1, Yes. If data is written into the FRC during
serial receive/transmit, the FRC stops counting
up and the baud rate changes.
In condition other than serial receive/transmit,
it's possible to write.
Type
I
I
t0 9, $Oj
Other Data
Title I
WRITE
Receive Shiftl
Register
J,
E
4J IJL
FRC
Baud Rate
Generator
1
~:rstops
Transmit Shift
Register
I
Reference Q & A Sheet
~
QA631-001A
QA631-008A
and the baud rate
changes.
Sup~lementJ
~HITACHI
1243
I
HD6301V Questions & Answers - - - - - - - - - - - - - - - - - - - - - - - - - - -
I
HD6301 VI
HD6303R
Type
Theme
Device ,.
RDRF State When SCI Receiving
4S
8M
Software
*8S
16M
Evaluation kit Emulator
SD
SBC
Date Nov. 24, 1983
I
Ques tion I
1, What is the state of the Receive Data Register
Full(RDRF) flag when the HD630lVl/HD6303R SCI
can receive signals (RE=!) and the wake-up flag
(WU bit) is set?
TRCSR
7
$0011
I RDR~
,J.
?
4
6
5
ORF§ TDR§ RIE
3
2
1
0
I RE I TIE I TE I WU I
,L.
J,
1
1
Answer I
1, When the wake-up flag is set (WU=!) the RDRF flag
cannot be set.
This is mentioned in the HD680l, HD6803 data
sheets, but not in the HD6301 and HD6303.
Classification
Parallel Port
* Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consm.
EPROM-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title J
Other Data
TitleJ
Reference Q
~
&
A Sheet
Supplement I
Transmit/Receive Control Status Register(TRCSR) controls the
transmitter, receiver, wake-up feature and two individual interrupts, and monitors the status of serial operations.
~HITACHI
1244
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD6301V Questions & Answers
Type
I Device I
HD6301Vl
HD6303R
ThemE
4S
Software
*8S
8M
16M
SD
Evaluation kit Emulator
SB~
Date Nov. 24, 1983
Serial I/O Operation
Question I
1 , The serial I/O does not operate satisfactorily.
Initialization does not seem to be wrong, but the
data is not transmitted. What is wrong?
Initialize by User P"rogram
1 Set the Rate/Mode Control Register
(RMCR) to the desired operation.
2 Set the Transmit/Receive Control
Status Register (TRCSR) to the
desired operation.
I
Classification
Parallel Port
Serial Port
* Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Con sm.
EPROM-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I
Answer I
1, Just after the initialization of serial I/O, the
data transmit is not operative during 10 cycles
of Baud Rate after setting the TE. The reason is
as follows.
Setting the transmit enable bit (TE bit) causes
ten consesutive "1" of preamble and maKes the
transmitter section operative. In other words,
Other Data
the transmitter section gets ready after one frame Title I
(10 bi ts) transmi t ting time according to the
Baud rate.
(ex.) When the Baud rate is set to 9600 Baud
(104.2)s at 1 bi t) ,
Set TE
Set the Baud rate
Transmit OK
Reference Q & A Sheet
J,
~
-l~
~~~~~~~~~~I ~~~~~~~~-----~
I
~II04.2tLS X lO=1.042m.s 1+I
I
~ : Transmit
Inoperative
Period
Preamble Causing Period
1.042ms after setting the TE, the transmitter
section is operative.
Supp lemen t I
1
~HITACHI
1245
I
HD6301V Questions & Answers - - - - - - - - - - - - - - - - - - - - - - - - - - Type
Theme
HD6301V1
HD6303R
Serial I/O Register Read
IDevice I
4S
8M
*8S
16M
Software
Evaluation kit, Emulator
SD
SBe
Date Nov. 24, 1983
I
Question I
1, When transmitting the data, is reading the Trnsmit/Receive Control Register(TRCSR) required?
*
When the transfer interval is long enough compared
with the Baud rate, Transmit Data Register
Empty (TDRE) will be set. In that case, are
there any problems when transmi,tting data wi thout
checking the TDRE flag in the TRCSR?
Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power .Consm.
EPROM-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I
Answer I
1, The TDRE flag shows if the TDRE register is empty
or not. When writing a data to the TDR with
TDRE=l, it's not necessary to check the TDRE.
But reading the TDRE flag tells us the contents
of TOR. For example, when new data is written to
the TDR with TDRE "O"(TDR already has a data),
the old data will be,erased.
Other Data
When the trans~er interval is long enough comparee Title I
with the Baud rate, there's no problem. However,
check TRCSR if possible.
Reference _Q & A Sheet
.Ji2.:J
Supplement
I
~HITACHI
1246
- - - - - - - - - - - - - - - - - - - - - - - - - - HD6301V Questions & Answers
HD6301V1
HD6303R
IDevice I
4S
Software
*8S
8M
16M
SD
SBC
Evaluation kit, Emulator
Theme Dete~tion of the HD6301Vl Serial Start Bit
Date
(No.1")
Nov. 24.1983
Classification
Question I
Parallel Port
1.
* Serial Port
(1) What is the relation between the HD6301V1
Timer/Counter
serial sampling clock frequenscy and the
BUS Interface
baud rate ?
Interrupt
A/D Converter
( 2) What does "Sampling error" mean ?
Oscillator
Reset
Low Power Consm.
EPROM-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Answer
Applicable Manual
I
Title I
Type
I
1.
(1)
The serial sampling clock frequenscy is eight
times the baud ra te.
(2)
"Sampling error" means receive margin at the
serial operation time.
Refer to the next page for details.
Other Data
Title I
Reference Q & A Sheet
~
r
Supplement I
~HITACHI
1247
I
HD6301V Questions & Answers - - - - - - - - - - - - - - - - - - - - - - - - Type
Them
Softwar
SD
SB
4S
8M
16U
*8S
Evaluation kit, Emulator
Start Bit
(No.2)
HD6301Vl
HD6303R
Detection of the HD6301Vl
Answer
Receive margin:
The HD6301Vl detects the start bit and samples the data bit using the
falling edge of the sampling clock.
The general equation is shown as follows.
1. General equation
M = [ ( 0.5-l/N ) - ( D-0.5 )/N- ( L-0.5)F
X 100 (%)
H: Receive margin'
N: Ratio of baud rate to sampling clock (0 to 0.5 )
D: Duty of the longer sampling clock of "H", and "L"
L: Frame length (7 to' 12 bits)
F: Absolute value of deviation of sampling clock frequency
2. Abbreviated equation
M = ( 0.5-1/N) X 100 (%)
Conditions: D ~ 0.5, F
N
M
16
43.75
(Fig.l)
8
37.5
(%)
32
46.875
0
64
48.4375
Note
In the HD6301 VI, ·N
=
8.
Figure 1
o
1
2
3
4
5
6
7
8
Clock
43.75 %
R.x
50 %
I~
-
.... 1\
Start bit
1[\
I1/N
I
I
Trii:~e~r------~0~.~5~-----------S-t-a-r-t-b-i-t--s-a-m~~ling
~HITACHI
1248
- - - - - - - - - - - - - - - - - - - - - - - - - - HD6301V Questions & Answers
I
I
4S
*8S
8U
16M
Software
Evaluation kit, Emulator
SD
SBC
ThemE
Date
Nov.24.1983
Question I
Classification
1. When the FRC of the HD6301Vl/HD6303R is read with
Parallel Port
~~--~~~------------~
the double byte load instructions(2 cycle
Serial Port
execution for FRC reading), is it read correctly? * Timer/Counter
Double byte load instructions require two cycles r-~~=-~~~--------~
BUS Interface
to be executed and the cycle to read the low byte r--r~I~n~t~e~r~r~u~p~t----------~
of FRC becomes the next cycle of the high byte.
A/D Converter
Is it OK ?
I
Oscillator
1
1
(EX)
I
I
I
Reset
High Readl Low Readl
Low Power Consm.
EPROtf-on-package
E
FRC
Software
(1 cycle) : (2 cycle
Evaluation Kit
($09,$OA)
I $F7FF
1 $F800
1
I T
",5 1
Emulator
SD
AccD
IF? 001
Data Buffer
(Whe reading $i7FF from the counter)
Others
Applicable }~nual
Answer I
1. The FRC of the HD6301Vl/HD6303R contains a
Title I
parallel temporary register. When the high byte
of the FRC is read, the low byte is set in the
temporaty register. The Low byte data in the
temporary register is set to the AccD at the
next cycle. Therefore, it is possible to read
the FRC correctly.
Other Data
I
I
1
Title I
I High Rea I Low
Rea I
Type
HD6301Vl
HD6303R
Device
Free Running Counter Read
l
E
FRC
$F7 FF r $F8 00
--I --I
riF" 1
Temporaly
Regist'er
Read Data
Reference Q & A Sheet
~--"~ ~
:
$F7
I
AccD
1
:
I
-!t
it
$FF
IF~ : FFI
I
I
I
(When reading $F7FF from the counter)
Supplement 1
FRC: Free Running Counter
The base counter of the timer which counts up the E clock.
~HITACHI
1249
I
HD6301V Questions & Answers - - - - - - - - - - - - - - - - - - - - - - - - - - - , -
I
J
Software
4S
8M
16M
HD6801Vl
*8S
Device
SD
SBC
HD6301Vl
Evaluation kit, Emulator
Theme Preset Method of the Free Running Counter
Date
Nov.24.1983
(No.1,)
Classification
Question I
Parallel Port
1.
Serial Port
~fuat is the difference between the HD6S01V and
* Timer/Counter
HD6301Vl in writing data into the free running
BUS Interface
Interrupt.
couter ?
A/D Converter
Oscillator
Reset
Low Power Consm.
EPROM-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Answer I
Title I
I. The FRC preset method of the HD6S0lV is different
from the HD6301VI.
Semiconductor Data Book
~ S-Bit Single Chip
Microcomputer Type
Preset Method
Other Data
HD680lV
The FRC is always preset to "$FFFS".
Title I
HD630lVI I. Writing to the high byte presets
the FRC to $FFF8.
2. The FRC is set to desirable data by
a double byte store instruction.
Reference Q & A Sheet
Type
I
~
QA631-001A
QA631-002A
Supplement I
See the next page for the example of this method.
~HITACHI
1250
HD6301V Questions & Answers
HD6801V1
HD6301V1
Preset Method of the Free
Type
Them
45
8M
16M
*85
Evaluation kit, Emulator
Counter
(No.2)
Softwar
SD
5B
Answer
(1) . The HD6a01V Preset l1ethod
· rLDD
STD
II$SAF3
$09
E
FRC
$FFF8
I
$FFF9
!
$FFFA
I
I
I
-?
I
The FRC is always preset to $FFF8.
( 2) The HD6301V1 Preset l1ethod
1. $FFF8
f-LDD II$SAF3
STAA $09
E
I
FRC
I
I
I
$FFF8
$FFF9
~
$FFFA
-?
I
Writing to the high byte presets the FRC to $FFF8.
2. Optional valve
(In this case $SAF3)
~LDD
STD
II$SAF3
$09
E
I
FRC
$FFF8
$SAF3 :
$SAF4
-7
The FRe is set to desirable data ($SAF3) by a double byte store
instruction.
~HITACHI
1251
I
HD6301V Questions & Answers - - - - - - - - - - - - - - - - - - - - - - - - - - Type
I
I
HD6301Vl
8M
4S
*8S
16M
Software
Device
HD6303R
Evaluation kit Emulator
SD
SBC
Theme Output of Address Strobes(AS) in the MultiDate Nov. 24, 1983
plexed Mode
Question I
Classification
Parallel Port
1, Is AS always output when using the HD6301Vl in
the expanded multiplexed mode (mode 2, 4, 6)?
Serial Port
Timer/Counter
BUS Interface
* Interrupt
A/D Converter
Oscillator
Reset
Low Power Consm.
1
EPROM-on-~ack~e
Answer I
2\ Yes. AS is always output in the expanded
mUltiplexed mode, even when the MPU accesses the
internal RAM, ROM, etc.
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I
Other Data
Title I
Reference ~ & A Sheet
~
Supplement I
In the expanded multiplexed mode,the data buses and lower address
buses are multiplexed and output from port 3. AS is the signal
needed to demultiplex the data buses and address busses.
Mode 2, 4 and 6 of the HD6301Vl are the expanded modes.
~HITACHI
1252
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD6301V Questions & Answers
Type
Theme
I Device I
HD6301V1
HD6303R
IRQ1 Acceptance
Software
4S
8M
16M
*8S
SD
SBC
Evaluation kit, Emulator
Date Nov. 24, lYtl3
.-
I
Question I
1, (1) Is TRQI ignored when the Condition Code
Register I mask ~s set?
(2) After the I mask is reset, will the interrupt
sequence start by the interrupt request flag
having been latched?
Answer I
1, (1) I f the Condition Code Register I mask is set,
rRQI ~s completely ignored.
(2) With the I mask set, the interrupt request
flag ~ill not be latched.
0)
(2)
Reset starts
Reset starts
~~LI
!E-I=l
Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
* A/D Converter
Oscillator
Reset
Low Power Consm.
EPROM-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I
Other Data
Title I
f::"'SEI
IRQ1
, ....
... ...
, ....
... ...
,
,-1
.... -1
I
I
I
I
f
... ... '
...
~
IRQ! is ignored.
Supplement I
IRQl
.....
/'
,~~ ...
I
f
/'
I
... ...
I
...
Reference Q & A Sheet
W!£:.J
I
I
....... 1
IRQl is ignored.
CLI : Clears the Condition Code Register I mask
SEI : Sets the Condition Code Register I mask
*
NMI is
acce~table
regardless of the I mask.
~HITACHI
1253
I
HD6301V Questions & Answers - - - - - - - , - - - - - - - - - ' - - - - - - - - - - - - - - -
I
I
45
8M
Software
HD6301 VI
16M
*8S
Device
SD
SBC
HD6303R
Evaluation kit Emulator
Theme Timer Interrupt and External Interrupt
Date Nov. 24, 1983
Type
Question I
1, In the routine below, when is the next timer
interrupt accepted?
Timer(OCI)
External Interrupt
Main
(IRQ) Routine
Routine Routine
{Execution time
(~xecution time=3ms)
/
=1. Sms)
Execution timE
Store 2.6ms as timer --; ~
-0
period to the OCR
EOCIis longer thar
Next
~.
CLI
timer interru'pt period.
Timer
,
Inter* 1=1
rupt
Request
I
,",""
...
~~
RTI
RTI
Answer]
1, The next timer interrupt is accepted in the main
routine just after RTI instruction execution.
I
Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
* A/D
Converter
Oscillator
Reset
Low Power Consm.
EPROM-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Appli ~ab Ie Manual
Title I
Timer(OCI)
Main
External Interrupt
ROU~ROU'ine
NOX' __ ~
Timer
Interrupt
Reque"
Other Data
Title I
RTI
J
Next Timer
(OCI) Routine
Reference Q & A Sheet
~
QA631-012A
Supplement I
~HITACHI
1254
I
- - - - - - - - - - - - - - - - - - - - - - - - - - - - HD6301V Questions & Answers
8M
16M
Softwan
4S
*8S
HD6301 VI
Device
SD
SBC
Evaluation kit, Emulator
HD6303R
Theme IRQl Interrupt and Other Interrupts (NO. 1)
Date Nov. 24, 1983
I
Type
I
I
Question I
Classification
1, rRQT pin (pin 5) is held at low for 1~s but an
Parallel Port
interrupt do:s not occur. Wha?t should be done to r--r~TS~~~mr~ei~ra~/l~C~Po~uo~n~r~tt-e-r------~
generate an ~nterrupt sequence.
~
BUS Interface
Interruot
* AID
Converter
Oscillator
E
1
1
1
Reset
Low Power Consm.
IRQl
II
SS
I
EPROM-on-package
I
I
I
I
Software
,
I
Evaluation Kit
l~s
">l
Emulator
SD
Data Buffer
Others
Aoplicable Manual
Answer 1
1, (1) IRQl ~s a level sens~t~ve interrupt pin which Ti tIe I'
needs a minimum of 2 machine cycles (~s at 1MHz)
to accept an interrupt. However, if another
interrupt has been already generated, no interrupt
request is accepted with IRQ1 at low for 1~s.
In such a case, IRQ1 should be held at low until
Other Data
the request ~s acceptre~d~.__,
E
Titlel
_---'I
I
1
I
~
,
W~
r::::
L - I_ - - ' ,
~I_~~~R~~~~'
~2
machine
cycles~
I
I
(2) In this case, as a timer interrupt ~s executec Reference Q & A Sheet
the interrupt mask is automatically set. SO IRQ1 .J!£:J
~s ignored.
QA63l-011A
See the next page for the illustration of IRQ1 anc
other interrupts and a countermeasure.
Supplement I
~HITACHI
1255
I
HD6301V Questions & Answers - - - - - - - - - - - - - - - - - - - - - - - - - - -
Type
Them
HD6301 VI·
45
*8S
8M
16M
HD6303R
Evaluation kit, Emulator
IRQl Interrupt and Other Interrupts (No.2)
50ftwar
5D
SB
IRQl and Other Interrupts
Main
Routine
IRQl Interrupt
Request
Timer
Routine
IRQ1
Routine
....... ....
-------------------~~~,
... ......
~
,,
IRQI is
ignored.
1=1
I
...
I
',j.
Countermeasure
Clear the I mask at the beginning of the timer interrupt routine.
Main
Timer
IRQl
Routine
Routine
Routine
IRQl is acceptable.
* CLI : Clears the interrupt mask (1=0).
With this method, note the following ;
(1) IRQl may be ignored when the request occurs during timer interrupt
vectoring.
(2) Interrupts form NMI or SWI are excluded.
~HITACHI
1256
- - - - - - - - - - - - - - - - - - - - - - - - - - HD6301V Questions & Answers
I
I
8M
16M
Software
HD6301 VI
Device
4S
*~S
HD6303R
Evaluatlon kit Emulator
SD
SBC
ThemE CLI Instruction and Interrupt Operation
Date Nov. 24, 1983
Type
I
QuestionJ
I, In the HD630lV, a timer interrupt is not accepted
in the following program. Is there any problem?
, - Main
- - -- - - - - Routine
LOI
:
CLI
NOP
SEI
I
r
:
•
~ ____ ~~ _~l__
Serial Port
Timer/Counter
BUS Interface
* Interrupt
AID Converter
Oscillator
Reset
Low Power Consm.
EPROM-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I
HD630lX Data Sheet
-.,
I
I
I
Classification
~~~P~a~r~a~l~l~e~l~P~o~r~t~------4
I
I
:
I
I
I
J
Answer I
I, To accept an interrupt, two machine cycles are
necessary between CLI and SEI. That is, in this
program, two NOP instructions are necessary. The
same thing can be said when using TAP for CLI and
SEL
Using CLI
Using TAP
r------------- - -- -- ---- - ---------,
:
I
I
I
L01
CLI
Nap
Nap
SEI
I..
I
:
I
TAP (Clears the I mask)
Nap
I
I
NOP
I
TAP (Sets the I mask) I
I
:
I
I
I
!'.
I :
I:
: - - - _BRA
r _____________
....
_ _ _L01
_ _ _ _ _ _ _ ..L..
Semiconductor Data Boo~
- 8-Bit Slngle Chip
Microcomouter Other Data
Title I
f--:---::-----,-....,..--....,..--~--_I
Reference Q & A Sheet
:~
_ _ _II
*
This is mentioned in the HD630lX data sheet but not
in the HD6301V.
Supplement I
•
HITACHI
1257
I
HD6301V Questions & Answers - - - - - ' - - - - - - - - - - - - - - - - - - - - - - - -
I
I
4S
Software
*8S
811
1611
HD6301V1
Device
SBC
Evaluation kit, Emulator
SD
HD6303R
Theme Relation between the External Clock
Date Nov. 24, 1983
(EXTAL Clock) and Enable Clock (E Clock)
Classification
Question I
Parallel Port
1, With which edges of the EXTAL clock does the
E clock change synchronously, rising edge ( t )
Serial Port
Timer/Counter
or falling edge ( .r, )7
BUS Interface
Interrupt
A/D Converter
* Oscillator
Reset
Low Power Consm.
EPROH-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Answer I
Applicable Hanual
1, It changes synchronously with the falling edge
Title I
( ,J,) of the EXTAL clock.
HD6301V User's Hanual
Type
EXTAL
E
~
I
Other Data
Ti tIe I
Reference Q
~
Supplement I
~HITACHI
1258
&
A Sheet
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD6301V Questions & Answers
I
Type
Theme
HD6301Vl
HD6303R
Device
Constants of the Reset Circuit
I
4S
*8S
8M
16M
Software
Evaluation kit, Emulator
SD
SBC
Date Nov. 24, 1983
I
Question
1, Does the capacitor of the recommended reset circuit
in the HD6303R (HD6301Vl) have an upper limit?
Answer I
1, Capacitor Cr does not have upper limit because
of the Schmitt trigger circuit provided with
the RES.
Available if Rr·Cr»2Oms
..
To the system power supply
...
-"""
I .....
I
T
rrr
Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
* Reset
Low Power Consm.
EPROM-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I
HD6301V User's Manual
Other Data
Title I
NMI
7.7
f
To
peripherals
[
Reference Q & A Sheet
~.
QA631-016A
Rr
11.
~c r
9 T
~
HD030lV
Supplement I
~HITACHI
1259
I
HD6301V Questions & Answers - - - - - - - - - - - - - - - - - - - - - - - - - Type
I Device t
HD6301V1
HD6303R
Theme
4S
Software
8M
16M
*8S
Evaluation kit, Emulator
SD
SBC
Date Nov. 24, 1983
I
-
Schmitt Trigger Circuit of RES
Question
1, Is Schmitt trigge r circuit provided with the
H.D6303R/H.D6301V1 RES?
Answer I
1, Yes.
Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
* Reset
Low Power Consm.
EPROM-an-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I
HD6301 V User 1s Hanual
(Hentioned in the HD6301V User's Manual)
..
To the system power supply
~
"..
~
I
I-
R.
rrr
f ,Lt,
..
v-
I
R.
Rr
To
peripherals
I""
vcr:
NMI
STBY ~YI
c;;--
Other Data
Titlel
I
;;rc.
'l[ES
t:>..
RES.
~
Reference Q
HDU01V
Ro«
11&
Ik. a ... Cr»20m.
~QA631-015A
QA631-020A
Supplement I
Effects of the Schmitt trigger circuit:
Even on the slow rising edge of input pulse, stable and clear
waveform can be output.
~HITACHI
1260
&
A Sheet
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD6301V Questions & Answers
I
Type
Theme
HD6301Vl
Device
HD6303R
I/O Port State on Resetting
J
4S
Software
*8S
8a
16M
Evaluation kit, Emulator
SD
SH~
Date Nov. 24, 1983
Question I
1, \Vhat is the state of each port on resetting
(RES='O')?
Answer I
1, It is as follows:
Port 1
Port 2
*
Port 3
I
Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
* Low Power Consm.
EPRm1-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Ap~).icable Hanual
Title I
High impedance state
l'
Modes
1, 5
Modes
0,2,4,6
Hode
t
E:
l'
-E:
"1" is output.
High impedance state
7
Port 4
Other Data
Title I
Hicrocomputer Technica
Information (D1-23)
t
Reference Q
* The state of Port 3 differs depending on
the mode.
&
A Sheet
~.
QA631-018A
Supplement
E: The E clock is "H u
-E:
•
The E clock is "L".
~HITACHI
1261
I
HD6301V Questions & Answers - - - - - - - - - - - - - - - - - - : - - - - - - - - -
I
Type
HD630lVl
Device
HD6303R
SCI (Pin 39) State on Resetting
Theme
I
8U
l6U
Software
4S
*8S
Evaluation kit, Emulator
SD
SBe
Date Nov. 24, 1983
Question
1, \fuat is the state of SCI (Pin 39) on resetting
(RES='O')?
Answer I
l, It is as follows:
Mode
0
I
Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
AID Converter
Oscillator
* Reset
Low Power Consm.
EPROH-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I
SCl State
The address strobe is output.
1
l'
2
4
5
6
7
l'
Other Data
Title I
l'
"1" is output.
The address strobe is output.
High impedance state
Reference Q
~.
QA63l-017A
Supplement I
SCl: Control signal of the HD630lV.
The usage differs depending on the mode.
$
1262
HITACHI
&
A Sheet
- - - - - - - - - - - - . . . . . . - . . , - - - - - - - - - - - - - - HD6301V Questions & Answers
Type
Theme
HD6301V1
HD6303R
I
Device
Port Output After Resetting
I
4S
8M
Software
*8S
16M
SD
SBC
Evaluation kit, Emulator
Date Nov. 24, 1983
Question I
1, What data does a port output when the Data
Direction Register(DDR)=l after resetting?
Answer I
1, After resetting, since the Data Register of a
port is undefined, undefined data is output when
the DDR=l.
Input definite data by programming in the Data
Register before setting the DDR=L
I
Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interruj)t
A/D Converter
Oscillator
* Reset
Low Power Consm.
EPROM-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I
Other Data
Title I
Reference Q & A Sheet
~
Supplement I
~HITACHI
1263
I
HD6301V Questions & Answers - - - - - - - - - - - - - - - - - - - - - - - - - - -
I Device I
HD6301V1
HD6303R
Type
Theme
4S
8M
16M
Software
*8S
SD
Evaluation kit, Emulator
SBC
Date Nov. 24, 1983
I
Schmitt Trigger Circuit of STBY
Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
* Low Power Consm.
EPR0!1-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I
HD6301V User's Manual
Question'
1, Is the Schmi t t trigger circuit provided with the
HD6303R STBY?
Answer I
1, Yes.
(Mentioned in the HD6303R User's Manual.)
To the system power supply
, ...
...
'"
~
I
r I"""'
VC~
R.
NMI
7.7
I
,~
...
'r
R.
fRr
Other Data
Title I
STBY _r;:;.....STBY,
1;Y"
I
;;re.
RES J'::;>....RES,
-V-
(-Ie,
..
To
peripherals
"+
HD 4:1 0 LV'
114«R. ,Rr.C:r»!Oma
Reference Q & A Sheet
~.
QA631-01SA
QA631-016A
Supplement I
Effects of the Schmitt trigge r ci rcui t :
Even on the slow rising edge of the input pulse, stable and clear
waveform can be output.
~HITACHI
1264
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD6301V Questions & Answers
Type
I
HD6301Vl
HD6303R
Device
Theme
I
4S
8M
Software
*8S
16M
SD
SBC
Evaluation kit, Emulator
Date Nov. 24, 1983
I/O Port State During Standby
Question I
1, What is. the state of each port during standby
(STBY='O')?
Answer
1, As follows:
Port
Port
Port
Port
1
High impedance state
2
'+"
+
3
4
I
Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low
Power Consm.
* EPROM-on-package
. Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I
Other Data
Ti t Ie I
Microcomputer technical
information
(D1-23)
Reference Q & A Sheet
~.
QA631-0l7A
QA63l-0l8A
Supplement
I
~HITACHI
1265
I
HD6301V Questions & Answers - - - - - - - - - - - - - - - - - - - - - - - - - - - Type
HD6301Vl
HD6303R
Theme
I Device I
4S
8M
16M
Software
*8S
SD
Evaluation kit Emulator
SBC
Date Nov. 24, 1983
Return from Standby Mode
Question I
1 , What occurs when returning from the standby mode
without using RES?
Answer I
1, The MPU does not operate normally because the
contents of. each register are not definite.
Therefore, always use the RES when returning from
the standby mode.
I
Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
* Low Power Consm.
EPROM-an-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Ti tIe I
HD6301Vl data sheet
HD6301V user's manual
Other Data
Title I
Reference Q & A Sheet
~
Supplement
I
~HITACHI
1266
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD6301V Questions & Answers
I
HD6301Vl
Device
HD6303R
Theme Going into the Standby Mode
Type
1
4S
SoftwarE
*8S
8M
16M
SD
Evaluation kit, Emulator
SBj:
Date Nov. 24, 1983
Question I
1, Does the HCU go into the standby mode after
current instruction execution is completed?
I
Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
* Low Power Consm.
EPROH-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Hanual
Title I
Answer I
1, No. Because there is no connection between the
instruction execution sequence and the standby
mode. That is, when the STBY pin goes into "Low .. ,
the state is latched at the next rising edge of E
clock. Then· the internal registers are reset at
the next falling edge.
:~ 1; nternal regis ten
,
are reset.
E
,
Other Data
,,
THIel
,
,
,
STBY
--
I
t
Reference Q & A Sheet
~.
QA631-024A
Supplement l
As standby mode detection has no connection with the instruction execution
sequence, the HCU goes into the standby mode after preparing for standby
mode with NMI routine.
~HBTACHn
1267
I
HD6301V Questions & Answers - - - - - - - - - - - - - - - - - - - - - - - - - - -
I
HD6301V1
Device
HD6303R
Theme Timing for the Standby Mode
Type
I
4S
16M
Software
*8S
8M
Evaluation kit, Emulator
SD
SBC
Datel Nov. 24, 1983
Question I
1, The timing for the standby mode is shown in the
HD6301V user's manual. Tl is not defined. How
long is Tl ?
CD NMI
!
I
I
I
I
,-'
Td",I ;I
(?) RES
,,
G) STBY
I
.
~
I
I
,~
RAH Control .
Register Set
lT2J.
I
I
I
~
Reset Start
*T2 : Oscillation Stabilization Time
Answer I
1, After the RAM Control Register is set in the NMI
routine, either STBY or RES can be in the low
state with no priority.
Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
* Low Power Consm.
EPROH-on-package
;:>OJ.Lware
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I
HD6301V User's manual
Other Data
Title I
Reference Q
&
A Sheet
~,
QA631-023A
Supplement
I
=0
STB Y P\VR bit = 1
RAM E bit = 0: Internal RAM is not accessable.
STB Y P\VR bit = 1: Indicates that the data in standby RAM is valid.
RAM Control Register Set -7 RAM E bit
~HITACHI
1268
- - - - - - - - - - - - - - - - - - - - - - - - - - HD6301V Questions & Answers
I
I
4S
Software
*8S
8M
16~1
RD6301V1
Device
Evaluation kit, Emulator
SBC
SD
RD6303R
Theme Usage of EPROt1 Socket Pins for the HD63POH1
Date Nov. 24, 1983
(No.1)
Question I
Classification
Parallel Port
1, Are the data buses of the EPROH socke t pins for
Serial Port
the HD63P01M bi-directional in order to access not
only the EPROH but the RAM?
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consm.
* EPROH-on-package
Software
Evaluation 'Kit
Emulator
SD
Data Buffer
Others
Ayplicable Hanual
Answer I
1, The data bus output from EPROM socket pins for
Title I
RD63P01H Data Sheet
the HD63POH1 is Read only.
Type
I
Other Data
Title I
Reference Q & A Sheet
~,
QA631-026A
QA631:-027A
Supplement I
~HITACHI
1269
I
HD6301V Questions & Answers - - - - - - - - - . - - - - - - - - - - - - - - - - Type
HD6301Vl
HD6303R
Theme Usage of EPROH Socket Pins for the HD63POUl
(No.2)
·QuestionJ
1, In EPROH socket pins for the HD63POUl, what is
CE composed of?
Answer I
1, CE is a NAND circuit of the address bus (A13 to
AlS) and the MCU internal R/~ signal.
(Refer below.)
Therefore, CE does not output in the dummy cycle.
(When not accessing EPROH of HD63POIM)
:
A
...
..
.
Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consm.
* EPROH-on-package
Software
Evaluation Kit
Emulator
SD
. Data Buffer
Others
Applicable Manual
Title I
0:
...
A14
---:CE
A 1S
:-..........................
Reference Q
~.
QA631-02SA
QA631-027A
Supplement I
~HITACHI
1270
I
Other Data
Title 1
~········R"/W····~
···
···
8M
16M
Software
kit, Emulator
SD
SBC
Date Nov.24, 1983
&
A Sheet
- - - - - - - - - - - - - - - - - - - - - - - - - - HD6301V Questions & Answers
I
I
4S
*8S
8M
16M
Software
HD6301Vl
Device
Evaluation kit, Emulator
HD6303R
SD
SBC
Theme Usage of EPROH Socket Pins for the HD63POll1
Date Nov. 24, 1983
(No.3)
Classification
Question I
1, Wi th EPROM socket pins for the 1ID63P01M,
Parallel Port
(1) Can pins drive one TIL load or more?
Serial Port
( 2) If not, what can pins drive?
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consm.
* EPROll-on -package
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Answer I
1, (1) The current of each pin is too little to drive Title I
one TTL load.
( 2) Each pin can drive one NHOS load.
Type
I
Other Data
Title 1
Reference Q
&
A Sheet
~.
QA631-025A
QA631-026A
Supplement
I
~HITACHI
1271
I
HD6301V Questions & Answers - - - - - - - - - - - - - - - - - - - - - - - - - - -
Type
Theme
4S
HD6301 VI
8M
16M
Software
* 8S
Device
HD6303R
Evaluation kit, Emulator
SD
SBC
Usage of Bit Manipulator Instructions (No.1)
Date Nov. 24, 1983
I
I
1
Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrt!E.t
A/D Converter
Oscillator
Reset
Low Power Consm.
Q
1- How the bit manipulation instructions of the
HD630lV should be written?
EPROM-on~ackaEe
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
AIlpl ic ab Ie Manual
Title!
*
A
1- They are written as follows;
written as follows ;
OIM
OIM
If $ 0 4
if $ 0 4
~
,
,
Immediate Data
$ 1 0
$ 1 0,
.-r
Address
X
(Direct Addressing)
(Index Addressing)
~
Index Register
This 1S an example of OR operation of the immediate
data and the memory and storing the result 1n the
memory.
The HD630lV has the following bit manipulation
instructions.
OIM .' ... (IMM)
(M) -7 (M)
AIM
(IMM) + (M) ~ (M)
ElM
(IMM) <3 (M) ~ (M)
TIM
(IMM)
(M)
These instructions are written in the same way.
* Continued on the nex t --.2.C!.Re.
Supplement I
· ...
·...
·...
.
.
~HITACHI
1272
HD6301 V Data Sheet
HD6301 V User's Manual
Other Data
TitleJ
Reference Q & A Sheet
~
QA631-029A
HD6301V Questions & Answers
Type
ThemE
HD6301V1
4S
16M
8M
* 8S
Device
Evaluation kit, Emulator
HD6303R
Usage of Bit Manipulator Instructions (No.2)
I
I
The following bit manipulations have different
code.
OP COdE
Mnumonics
71
61
A I M
BeL R
72
62
o
B SET
75
65
ElM
B T GL
7B
6B
TIM
B T S T
I M
mnumon~css
~n
Software
SD
SBC
the same OP
Bit Manipulation Insturction
Function
0 - Mi
The memory bit i(i=O to 7) ~s cleared and
the other bits don't change.
1 - Mi
The memory bit i(i=O to 7) ~s set and the
other bits don't change.
Mi - M~
The memory bit i(i=O to 7) ~s inverted and
the other bits don't change.
1
Mi
AND operation test of the memory bit i(i=O
to 7) and "I" ~s executed and its correspond
ing condition code ~s changed.
.
.i
~
D~rect
Addressing
Index
Addressing
The mnumonics mentiond above can be written as follows.
B C L R
BC L R
3, $ 1 0
BA I M
3, $ 1 0, X ~A I M
F 7 ,
1ft $ F 7 ,
$ 1 0
$ 1 0
B S E T
B S E T
3, $ 1 0
3, .LU.,
HO I M
00 I M
ift $ 0 8 ,
ift $ 0 8 ,
$ 1 0
r
Bit
t
Address
!
if $
$ 1 0
, X
(Direct Addressing)
(Index Addressing)
,
(Direct Addressing)
(Index Addressing)
X
~
Index Register
*For details, see HD6301V Users Manual.
~HITACHI
1273
I
HD6301V Questions
&Answers - - - - - - - - - - - - - - - - - - - - - - - - - - -
I
I
8M
Software
16M
* 8S
HD630lVl
4S
Device
HD6303R
Evaluation kit Emulator
SD
SBe
Theme Usage of Bit Manipulation Instructions to
Date Nov. 24, 1983
the Port
Q
Classification
1. Are the bit manipulatiori instructions (AIM, OIM,
Parallel Port
ElM, TIM) executable when a port is in the output ~-r~S~e~r~i~a~1~P~o~r~t~----4
state (DDR=l)?
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consm.
EPROM-on-package.
* Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
A
Applicable Manual
Title I
1. It can be used if the port is in the output state
(DDR=l). However, the bit manipulation instruction is executed as follows ;
Type
1
2
3
Reads specified address.
Executes logical operation
Writes the result into the specified address.
I
Other Data
Ti tIe I
Since the specified address(l) reads the pin
state of the port, ·the data is influenced by the
pins even if any dat~ is output from the port.
Reference Q & A Sheet
~
QA631-028A
Supplement I
DDR : Data Direction Register
This register selects whether in the port is the input or the output
state.
DDR = 0 : Data input
DDR = 1 : Data output
~HITACHI
1274
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD6301V Questions & Answers
I
1
8M
16M
HD6301 VI
4S
*8S
Software
Device
SD
Evaluation kit, Emulator
SBC
HD6303R
Theme RAM Access Disable during Program Execution
pate I Nov. 24, 1983
Type
Question I
1, When executing a program. with the RAME bit of the
RAM Control Register disabled,
(1) What occurs if the internal RAM address is
accessed?
(2 ) What occurs if the interrupt requests are
generated?
Answer I
1, (1) The external RAM can be accessed; the interna
RAM ~s neither readable nor writable when the
RAME bit is disabled.
(2) If there is no stacking area other than the
internal RAM, .the MPU will burst when
returning from the interrupt sequence.
Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consm.
EPROM-on-package
Software
Evaluation Kit
Emulator
SD
Data Buffer
* Others
Applicable Manual
Title I
HD6301V Data Sheet
HD6301V User's Manual
Other Data
Title I
Reference Q & A Sheet
~
Supplement
I
RAM Control Register
7 6
$0014
Ct-----=:I
----RAME bi t
*
RAME='O' : Disable the Internal RAM Address
~HITACHI
1275
I
2. HD6301XO/HD6303X OSCILLATOR CIRCUIT
.
gm
Quartz Oscillation Circuit
1. Quartz oscillation circuit and oscillation
conditions
A typical quartz oscillation circuit and its
equivalent circuit are shown in Fig. 1.
Oscillation conditions can be represented as
follows:
I -Rzi > Re .............(1)
Rz = gm/w2C 1C2 • • • • • • • • • (2)
-Rz: Quartz circuit resistance (based on
quartz)
gm:
Inverter transfer conductance
gm:
dlout/dVin
Therefore, normal oscillation can be performed if
negative resistance is sufficiently high.
However, oscillation stability is affected not only
by external capacitance C1 and C2, but also by
external factors such as floating capacitance or
resistance dependent on substrate circuit
patterns, power stability time, and interference
from other signal lines. Accordingly, sufficient
care should be taken to pattern designing of the
oscillation terminal periphery.
Regarding LSI, oscillation stability is affected by
the inverter's gm. gm changes depending on
inverter input voltage of the inverter, i.e., bias
voltage.
G: Inverter B gain
(voltage amplification ratio)
Inverter A's gm relatively reduces to (3), and load
resistance Rz of equation (2) also decreases,
which prevents or stops oscillation.
Reducing inverter B's gain G increases gm
according to (3). When resistance RL is added,
inverter B's gain G can be reduced since the
bias voltage deviates from the maximum gain
pOint.
However, applying resistance RL reduces the
gain of oscillation inverter A itself. Too small RL
results in adverse effects. A stimulation result of
RL:s optimized value is shown in Fig. 5. This is a
transfer curve showing the change of oscillation
circuit loop gain due to presence or absence of
RL. It indicates that RL from 2-100 Mohm gives
sufficient gain. However, optimum RL is 10 or
less due to substrate leak current. 2-5 Mohm is
best.
2. Oscillation halt and countermeasure
The oscillation circuit works under condition (1)
above. However, in some cases, oscillation
conditions are not satisfied because of the
mutual interference described in 1 above.
To assure oscillation start, add resistance RL to
the input (EXTAL) terminal of the oscillation
circuit to fix bias voltage. 2 to 5 Mohm resistance
is best.
3. Explanation of oscillation halt and its
countermeasure
This section explains oscillation halt based on
LSI internal circuits.
A quartz oscillation circuit built in a
microcomputer consists of inverter A used for
oscillation and inverter B providing clocks on the
LSI internal circuit.
Parasitic capacitance CM between these
inverters' output and input generates negative
feedback with a feedback ratio of CM/CI. Since
inverter B appears in the same phase as inverter
A, this negative feedback prevents oscillation.
~HITACHI
1276
Ci
= G.CM + CI gm ----- (3)
Rf
(a) Quartz oscillation circuit
C
Rz
LSI
Quartz
L
Re
(b) Equivalent circuit
Fig. 1 Quartz oscillation circuit and
equivalent circuit
EXTAL
XTAL
Fig. 2 Oscillation stop countermeasure
@HITACHI
1277
I
Cm
,-----11----,
)---~
To internal circuit
,,
1---
Ci:::::
7lT
Rf
Fig. 3 Practical oscillation circuit
Rf = 1 Mohm
R1> R2 = 500 ohm (ESD protective resistance)
Vout
Vin
Vin
Fig. 4 Inverter transfer curve
(Input/output voltage characteristics)
Bias voltage moves to the left on the
transfer curve by adding RL
~HITACHI
1278
= Vout
...J
a:
<1>
~
"E
::J
c:
0
~
"u
en
0
()
c:
CII
:::di
en
0
0<1>
~a:
(ij
E
~
w
c:
"(ij
CJ
a.
o
.3
0
\0
"
RES
STay
P,.
P,.
PH
P"
p]) ...
P"
p)'!JP"
P2I
P"
P"
p"
Ie:
P"
P"
P"
P"
P"
P"
Po>
P"
P"
P"
P"
P"
P"
P"
P"
P"
P"
P"
SC,4'
*Contact Hitachi Sales Office
P••
P.,
p.,
P"
P..
P"
P"
P"
Pori
4
~HITACHI
1285
I
HD6301V1, HD63A01V1, HD63B01V1
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO + U5°C
(J VERSION)
•
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Supply Voltage
Vee
-0.3 - + 7.0
V
Input Voltage
Vin
-0.3 - Vee +0.3
V
Operating Temperature *
Topr
-40 to +85
Storage Temperature
Tstg
-55 to +150
DC
DC
Item
(NOTE) This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection circuits. To
assure the normal operation. we recommend Vin , Vout : Vss :5 (Vin or Vouu :s Vee.
*K version (-40 to + 12SDC) available. Contact sales office.
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS IVee
=5.0V±10%, Vss = OV, Ta = -40 to
Item
Symbol
+85 D C, unless otherwise noted.)
Test Condition
Input "High" Voltage
min
All Inputs
NMI, iRQ.,
Three State loff-state)
Leakage Current
p. o-P 17 , P20 -P2.,
P30-P37 , P4Q-P'7, TS3
m, STBY
Vee
+0.3
V
-
IiTS,I
V in = 0.5-V ee -0.5V
-
-
1.0
J1.A
IOH = -200J1.A
2.4
-
Vee- 0.7
-
-
V
0.55
V
2.0
Other Inputs
Input Leakage Current
Unit
V'n =0.5-V ee -0.5V
Vee xO.7
V'H
Input "Low" Voltage
max
V'L
lI in I
Vee-0.5
EXTAL
typ
-
RES, ST8Y
-0.3
0.8
V
1.0
J1.A
V
Output "High" Voltage
All Outputs
V OH
Output "Low" Voltage
All Outputs
VOL
IOL = 1.6mA
-
C in
Vin=OV, f= 1.0MHz,
Ta = 25°C
-
-
12.5
pF
-
2.0
15.0
J1.A
Operating If=l MHz··)
-
6.0
10.0
Sleeping If=l MHz··)
-
1.0
2.0
2.0
-
Input Capacitance
Standby Current
All Inputs
Non Operation
IOH - -10J1.A
lee
Current Dissipation·
lee
RAM Stand·By Voltage
V RAM
V'L(STBY) = 0 - 0.6V
V'H(RES) = Vee- 0.5Vee V
V,dRES) = 0 - 0.6V
-
• VIH,min'" Vcc-'1.0V. VIL max = O.8V
•• Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max.
values about Current Dissipations at f = x MHz operation are decided according to the following formula;
typo value (I· x MHz) • tYP. value (I - 1 MHz) • x
max, value tf· x MHz) c max. value If • 1MHz) x x
(both the sleeping and operating)
~HITACHI
1286
mA
V
HD6301V1, HD63A01V1, HD63B01V1
•
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO + 85°C
(J VERSION)
AC CHARACTERISTICS (Vee· 5.0V±10%, Vss
=OV, Ta = -40 to + 8Soe, unless otherwise noted.)
BUS ·TIMING
Item
Symbol
Cycle Time
Address Strobe Pulse Width
"High"
Test
Can·
dition
HD6301Vl
HD63A01Vl
HD63B01Vl
Unit
min typ max min typ max min typ max
1
-
10 0.666
-
220
-
-
150
-
-
20
-
-
20
-
-
-
40
-
-
20
20
- - - - 190
- 190
- 190
- - - -
t cvc
PW ASH
Address Strobe Rise Time
tASr
Aadress Strobe Fall Time
Adpress Strobe Delay lime
tAS!
-
tASO
60
Enable Rise Time
tEr
Enable Fall Time
tEl
-
Enable Pulse Width "High" Level
PWEH
450
Enable Pulse Width "Low" Level
PWEL
450
t ASEO
60
Address Strobe to Enable Delay
Time
-
20
-
-
20
-
300
300
-
-
tosw
230
-
Read
tOSR
80
-
Read
tHR
0
Write
Address Set·up Time for Latch
tHW
t ASL
20
-
Address Hold Time for Latch
tAHL
60
30
Address Hold Time
tAH
tASM
20
200
-
-
-
-
650
-
-
650
-
-
20
-
200
~
t
Address Delay Time
A02
Address Delay Time for Latch
Write
Data Set·up Time
Data Hold Time
Ao - A, Set·up Time Before E
Peripheral Read
Access Time
I
t AOL
Fig: .5.1
Fig: .5.2
Non·Multiplexed
(tACCN)
Bus
I MUltiplexed Bus
Oscillator stabilization Time
Processor Control Set·up Time
-
-
(tACCM
Fig.2·7-1 20
tRC
,
Fig.2-B-l 200
tpcs
..
-
250
250
250
40
-
-
-
150
-
0
20
-
60
10 0.5
20
20
110
-
-
-
-
-
20
-
-
10
-
220
20
100
50
0
20
20
-
-
-
ns
20
ns
20
ns
-
-
220
IlS
20
ns
ns
20
ns
-
ns
-
ns
-
ns
160
160
ns
ns
160
-
ns
ns
-
ns
-
ns
20
110
-
-
-
-
395
-
-
270
ns
-
395
-
-
270
-
20
-
-
-
ns
ms
ns
40
20
-
20
20
60
200
-
-
ns
-
ns
ns
ns
ns
PERIPHERAL PORT TIMING
Item
Symbol
Test
Condition
HD6301Vl
min typ
..
HD63A01VI
max min typ
HD63B01VI
max min typ
max
Unit
Peripheral Data
Port 1, 2, 3, 4 tposu
Set·up Time
Peripheral Data
Port 1,2,3,4 tpOH
Hold Time
Oelay Time, Enable Positive
Transition to OSJ Negative
tOSOl
Transition
Fig. 5-3 200
-
-
200
-
-
200
-
-
ns
Fig. 5-3 200
-
-
200
-
-
200
-
-
ns
Delay Time, Enable Positive
Transition to ~ Positive
Transition
Fig. 5-5
..
-
-
300
-
-
300
-
-
300
ns
Fig. 5-5
..
-
-
300
-
-
300
-
-
300
ns
Delay Time, Enable Nega-I Port 1
tive Transition to Peri2' 3 ,; tpwo
pheral Data Valid
' ,
Fig .• ~-4
-
-
300
-
-
300
-
300
os
Input Strobe Pulse Width
-
200
-
-
-
200
150
-
0
-
Input Data Hold Time
Input Data Setup Time
·
I
I
taS02
lpwlS
Fig~;-6
Port 3
tlH
Fig~~-6
200
150
Port 3
tiS
Fig .•~-6
0
-
-
-
150
0
-
-
-
ns
ns
ns
Excopt P21
• 'Refer to Pages 189-190
••• Refer to Pages 159-160
~HITACHI
1287
I
HD6301V1, HD63A01V1, HD63B01V1
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO +85°C
(J VERSION)
TIMER, SCI TIMING
Item
Timer Input Pulse Width
Delay Time, Enable Positive
Transition to Timer Out
SCI Input Clock Cycle
SCI Input Clock Pulse Width
Test
Symbol Condition
HD6301Vl
HD63A01Vl
HD63B01Vl
Unit
min typ .max min typ max min typ max
tpWT
2_0
-
-
2_0
-
-
2.0
-
-
tTOD
-
-
400
-
-
400
-
-
400
2.0
0.4
-
-
-
-
0.6
2.0
0.4
-
tpWSCK
2.0
0.4
-
0.6
Test
Symbol Condition
HD63A01Vl
HD63B01Vl
HD6301Vl
Unit
min typ max min typ max min typ max
PW ASTL
3
2
150
FI9...S-7
t Scve
-
0.6
-
tCYC
ns
tCyc
tSeyc
MODE PROGRAMMING
Item
RES "low" Pulse Width
Mode Programming Set·up Time
Mode Programming Hold Time
tMPS
tMPH
Flg;.S-S
-
-
-
3
2
150
-
-
""Refer to Pages 189-190
~HITACHI
1288
-
3
2
150
-
-
tCYC
tCYC
ns
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO + 85°C
(J VERSION)
HD6301XO, HD63A01XO,
HD63B01XO
The HD6301XO is a CMOS single-chip microcomputer unit
(MCU) which includes a CPU compatible with the HD6301Vl,
4k bytes of ROM, 192 bytes of RAM, 53 parallel 110 pins, a
Serial Communication Interface (SCI) and two timers on chip_
• FEATURES
• Instruction Set Compatible with the HD6301V1
• Abundant On-chip Functions
4k Bytes of ROM, 192 Bytes of RAM
53 Parallel 110 Ports
16-Bit Programmable Timer
8-Bit Reloadable Timer
Serial Communication Interface
Memory Ready
Halt
Error-Detection (Address Trap, Op Code Trap)
• Interrupts ___ 3 External, 7 Internal
• Operation Mode
Mode 1 ___ Expanded (Internal ROM Inhibited)
Mode 2 ___ Expanded (Internal ROM Valid)
Mode 3 ___ Single-chip Mode
• Low Power Dissipation Mode
Sleep
Standby
• Wide Range of Operation
Vcc =5V±10%( 1=0.1 to 1.0MHz: HD6303Y )
1 = 0.1 to I.SMHz: HD63A03Y
1 = 0.1 to 2.0MHz: HD63B03Y
1 = 0.1 to 3.0MHz : HD63C03Y
• GENERIC PART NUMBER
HD6301XOPJ, HD63A01XOPJ,
HD63B01XOPJ
HD6301 XOCPJ, HD63AOl XOCPJ,
HD63B01XOCPJ
(CP-68)
HD6301XOF', HD63A01XOF*,
HD63BOl XOF'
HD6301XOPJ,HD63A01XOPJ,HD63B01XOPJ
HD6301XOCPJ,HD63A01XOCPJ,HD63B01XOCPJ
(FP-80)
• Contact Hitachi Sales Office
~HITACHI
1289
I
HD6301XO, HD63A01XO, HD63B01XO
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO +85°C
(J VERSION)
• PIN A",RANGEMENT
•
HD6301XOPJ, HD63A01XOPJ, HD63B01XOPJ
v..
XTAL
EXTAl
MP,
MP,
liES
STBY
.
.
0
• HD6301XOF·,
HD63A01XOF· ,
HD63B01XOF·
HD6301XOCPJ,HD63A01XOCPJ
HD63B01XOCPJ
ft;j{~5!l .. :':l~l'::
~
::
....
::
o
NMi
PM'
P"
P"
,
Pu I
P"
P"
PH
P"
P"
P"
P"
P"
Po.
p..
p..
".1;
~:c.
,
P"
~~~O~NM~~~~W~O_NM
p..
p..
NNNMMMMMMMMMM~~~~
P.,
P"
P"
P"
P"
P"
~~f~~~~~g~~~~~~~~
P"
P.,
P"
p..
,
P" ......_ _ _ _ _
(Top View)
P"
p..
(Top View)
(CP·6S)
(FP·SO)
~v"
·Contact Hitachi Sales Office
(Top View)
(DP.64S)
• BLOCK DIAGRAM
purr... "
P~riSClICJ
I',.rnn,
"nCR.,
P"lTx)
"nCTout21
P..tT_31
!
JI
I I
~~i~
r-"LLLLLL-,.,,;;o
'"".Nil'
P"IAIW
p'JtCiR
'-...---~- ....!8A
PIJITCllCl~-ItI+It-l
....cRftr.,
p"tIJR&l
PuCMJItI
...J(RAtT1
......'"
'"
~HITACHI
1290
HD6301XO, HD63A01XO, HD63B01XO
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO + 85°C
(J VERSION)
• ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Supply Voltage
Vee
-0.3 - + 7.0
V
Input Voltage
Vin
-0.3 - Vee +0.3
V
Operating Temperature
Topr
-40 to +85
°C
Storage Temperature
Tstg
-55 to + 150
°C
Item
(NOTE)
This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection circuits. To
assure the normal operation, we recommend Yin. Vout : VSS
.::5
(V in or Vout) .::5 Vee.
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee = 5.DV±lD%, Vss = DV, Ta = -40 to +85°C, unless otherwise noted.)
Item
Symbol
RES,STBY
EXTAL
Input "High" Voltage
Test Condition
V IH
V IH
Input "Low" Voltage
All Inputs
V IL
Input Leakage Current
NMI, RES, STBY,
MPo, MP., Port5
IIlnl
Yin = 0.5-V ee -0.5V
Three State (off·state)
Leakage Current
Ports 1,2,3,4, 6, 7
II Ts ti
Yin = 0.5- Vee-0.5V
Output "High" Voltage
All Outputs
V OH
lyp
max
Unit
-
Vee
+0.3
V
0.8
V
-
-
1.0
p.A
Vee xO.7
2.0
2.2
Other Inputs
Port 22
min
Vee- O.S
-0.3
-
V
-
-
-
1.0
p.A
IOH - -200p.A
2.4
-
-
V
IOH = -10p.A
Vee-0.7
-
V
IOL = 1.6mA
-
-
0.4
V
10.0
mA
-
12.5
pF
Output "Low" Voltage
All Outputs
VOL
Darlington Drive
Current
Ports 2, 6
-loH
Vout = 1.5V
1.0
Vin=OV,f= lMHz,
Ta = 25°C
3.0
15.0
p.A
Sleeping (f = lMHz")
Sleeping (f = 1.5MHz··)
-
1.5
2.3
3.0
4.5
mA
Sleeping (f = 2MHz")
-
3.0
mA
Operating If = lMHz")
Operating (f = 1.5MHz··)
-
7.0
6.0
10.0
10.5
15.0
mA
14.0
20.0
mA
2.0
-
-
V
Input Capacitance
All Inputs
Cin
Standby Current
Non Operation
ISTB
I SLP
Current Dissipation'
Icc
Operating (f = 2MHz")
RAM Standby Voltage
V RAM
mA
mA
·VIH min· Vcc-1.OV. VIL max" O.SV (All output terminals are at no load,)
··Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max.
values about Current Dissipations at x MHz operation are decided according to the following formula;
typo value
(I -
x
MHz) - typo valuo
(I - 1 MHz) x
x
max. value (f - x MHz) - max. value (f - 1 MHz) x x
(both the sleeping and operating)
~HITACHI
1291
HD6301XO, HD63A01XO, HD63B01XO
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO +85°C
(J VERSION)
• AC CHARACTERISTICS (Vee = S.OV±10%. Vss K OV. Ta = -40 to + as·c, unless otherwise noted.)
BUS TIMING
Item
Symbol
Cycle Time
Enable Rise Time
Enable Fall Time
Enable Pulse Width "High" Level'
Enable Pulse Width "Low" Level'
Address, R/WDelay Time'
Data Delay Time
I Write
Data Set-up Time
I Read
Address, R/WHold Time'
I Write'
Data Hold Time
I Read
RD. WR Pulse Width'
RJ:). WA Delay Time
RD, WR Hold Time
LIR Delay Time
[fR Hold Time
MR Set-up Time'
MR Hold Time'
E Clock Pulse Width at MR
Test
Condition
tcyC
-
tEr
tEf
PW EH
450
450
PWEL
tAD
toow
tOSA
tAH
tHW
tHA
PWAW
tAWO
tHAW
tOLA
tHLA
tSMA
tHMA
PWEMA
Processor Control Set-up Time
tpcs
Processo( Control Rise Time
Processor Control Fall Time
BA Delay Time
Oscillator Stabilization Time
Reset Pulse Width
tpcr
tPCf
teA
tAC
PWAST
HD6301XO
typ
max
1
10
-
min
Fig. 1-1
"
80
80
80
0
450
-
10
400
..
Fig. 1-2
Fi!,J·l:3
1-11,1-12
Fig. 1-2,
1-3'" ...
Fig. 1-3 ••
Fig. 1-12"
200
20
3
-
-
HD63A01XO
typ
min
max
0.666
10
-
40
9
25
25
-
-
25
25
-
300
300
-
-
250
200
-
-
-
-
70
50
50
0
300
-
-
-
-
-
-
-
40
30
200
-
-
-
-
-
10
280
-
HD63B01XO
min
typ
max
10
0.5
25
25
220
220
160
120
70
35
40
0
220
40
25
120
10
230
0
9
-
-
90
9
-
-
200
-
100
100
250
-
-
-
-
20
3
190
160
-
-
v
-
40
30
160
-
Unit
/JS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/.IS
-
200
-
-
ns
100
-
-
-
100
190
-
-
100
100
160
-
-
20
3
-
-
ns
ns
ns
ms
-
teyc
• These timings change in approximate proportion to tcyc. The figures in this characteristics represent those when tcyc is
minimum (- in the high ..t speed operation).
, 'Refer to Pages 466-469
PERIPHERAL PORT TIMING
Item
Peripheral Data
Set-upTime
Peripheral Data
Hold Time
Symbol
Ports 2. 3. 5. 6
tposu
.i'orts 2, 3, 5. 6
tpOH
Delay Time (Enable
Negative Transition to
Peripheral Data Valid)
I
P
orts 1,2. tpwo
3.4.6,7
Test
Condition
HD6301XO
typ
min
max
HD63B01XO
typ
max
min
Unit
Fig. 1-5
"
Fig.I-S
"
200
-
-
200
-
-
200
-
-
ns
200
-
-
200
-
-
200
-
-
ns
..
-
-
300
-
-
300
-
-
300
ns
Fig. 1-6
"Refer to Pages 466-469
~HITACHI
1292
HD63A01XO
typ
min
max
HD6301XO, HD63A01XO, HD63B01XO
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO +85°C
(J VERSION)
TIMER SCI TIMING
Item
Timer 1 Input Pulse Width
Delay Time (Enable Positive
Transition to Timer Output)
SCI Input
Clock Cycle
I Async. Mode
I
Clock Sync.
HD6301XO
typ
max
HD63A01XO
min
max
~
2.0
-
Symbol
Test
Condition
min
tPWT
Fig. 1-9* *
2.0
-
400
-
-
1.0
tTOD
tScvc
400
-
-
1.0
2.0
-
-
200
-
-
-
290
-
-
290
Flg.H,I-B**
-
Fig. 1-9* *
1.0
Fig. 1-4. 1-9"
2.0
-
-
2.0
-
-
200
290
-
SCI Transmit Data Delay
Time (Clock Sync. Mode)
tTXD
SCI Receive Data Set·up
Time (Clock Sync. Mode)
tSAX
SCI Receive Data Hold Time
(Clock Sync. Mode)
tHAX
100
-
-
100
-
-
SCI Input Clock Pulse Width
tPWSCK
0.4
0.6
0.4
-
Timer 2 Input Clock Cycle
ttcvc
2.0
tPWTCK
200
-
2.0
Timer 2 Input Clock Pulse
Width
-
Timer 1'2, SCI Input Clock
Rise Time
tCKr
-
-
Timer 1'2, SCI Input Clock
Fall Time
tCKf
-
-
• * Refer
Fig. 1-4*'
Fig. 1-9* *
HD63B01XO
typ
min
max
2.0
400
-
Unit
tcvc
ns
tcvc
tCYC
200
ns
-
-
ns
100
-
-
ns
0.6
0.4
0_6
tScyc
-
2.0
-
tCYC
200
-
200
-
-
ns
100
-
-
100
-
-
100
ns
100
-
-
100
-
-
100
ns
to Pages 466-469
~HITACHI
1293
I
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO +85°C
(J VERSION)
HD6301YO, HD63A01YO,
HD63B01YO,HD63C01YO
The HD6301 YO is a CMOS 8-bit single-chip microcomputer
unit which contains a CPU compatible with the CMOS 8-bit
microcomputer HD6jOIV, 16k bytes of ROM, 256 bytes of RAM,
53 parallel 110 pins, Serial Communication Interface (SCD and two
HD6301YOPJ, HD63A01YOPJ,
HD63B01YOPJ,HD63C01YOPJ
timers.
•
•
•
•
•
•
•
•
•
FEATURES
Instruction Set Compatible with the HD6301 VI
16k Bytes of ROM. 256 Bytes of RAM
53 Parallel 1/0 Pins
(4B 1/0 Pins. 5 Output Pins)
Parallel Handshake Interface (Port 6)
Darlington Transistor Drive (Port 2. 6)
16-Bit Programmable Timer
Input Capture Register x 1
Free Running Counter x 1
Output Compare Register x 2
8-Bit Reloadable Timer
External Event Counter
Square Wave Generation
Serial Communication Interface (SCI)
Asynchronous Mode 18 Transmit Formats. Hardware Parity)
Clocked Synchronous Mode
•
Memory Ready
3 Kinds of Memory Ready
•
•
Halt
Error Detection
(Address Error. Op-code Error)
'Interrupt - External 3. Internal 7
Operation Mode
Mode 1; Expanded Mode
Unternal ROM Inhibitedl
Mode 2; Expanded Mode
Unternal ROM lIalid)
Mode 3; Single Chip Mode
Maximum 65K Bytes Address Space
Low Power Dissipation Mode
Sleep Mode
Standby Mode (Hardware Standby. Software Standby)
Minimum Instruction Execution Time - O.5.u-s (f = 2MHz)
Wide .Range of Operation
•
•
•
•
•
•
'''''001 to 1.0MHz: HD6301YO
Vcc=5V± 10%
{
l~g~ :~~:~~~~: ~g~~~g1~g
(DP·64S)
HD6301YOCPJ, HD63A01YOCPJ,
HD63B01YOCPJ,HD63C01YOCPJ
(CP·68)
HD6301YOF*, HD63A01YOF*,
HD63B01YOF*,HD63C01YOF*
:}
f=0.1 to3.0MHz: HD63CQ1YO
(FP·64)
• GENERIC PART NUMBER
HD6301YOPJ, HD63A01YOPJ, HD63B01YOPJ, HD63C01YOPJ
'Contact Hitachi Sales Office
HD6301YOCPJ, HD63AA01YOCPJ, HD63B01YOCPJ, HD63C01YOCPJ .
~HITACHI
1294
HD6301YO,HD63A01YO,HD63B01YO,HD63C01YO
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO + 85°C
(J VERSION)
• PIN ARRANGEMENT
• HD6301YOPJ,HD63A01YOPJ,
HD63B01YOPJ,HD63C01YOPJ
V,.
• HD6301YOCPJ, HD63A01YOCPJ,
HD63B01YOCPJ,HD6301YOCPJ
1
XTAL 2
EXTAL 3
o
STBY
7
NMi •
44 P.o
M...,
~~~O_NM~~~~W~
-NM
"<1""'",
..,
(Top View)
(CP·68)
• HD6301YOF*, HD63A01YOF*,
HD63B01YOF*,HD63C01YOF*
(Top View)
;;;:;; ,
(DP.64S)
'1.
J
1!' '.
~'"
~:.:
(Top View)
(FP·64)
* Contact Hitachi Sales Office
~HITACHI
1295
HD6301YO,HD63A01YO,HD63B01YO,HD63C01YO
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO +85°C
(J VERSION)
• BLOCK DIAGRAM
N
V.I ..--.
v•• ___
'll
::&
,
,,
,
,,
p,o/Im
P,,/WA
P"/A/W
p,oIrm
P,./SA
Poo/D.
P,,/D,
P,,/D,
P,oID,
P,JD.
P../D.
P,JD.
P,,/D,
p,o/Ao
PIllA,
PIllA,
P,JlA,
p,./Ao
POI/A.
p,oIA.
P,,/A,
'"0Ii:
P.oIA.
PulA.
P../A,.
P.JlA"
P••/Au
P••/A"
PII/A,.
P"/A"
a.
I'll
'PII
OD
I'll
Po,
I'll
I'i.
•Ii:
2
'10H..-
~HITACHI
1296
::&
l l
P,.(T1n
P,,(TN,'
P"CSCllO
P,.CA.
P.. CT.
P,,(TN"
P..(TN,'
P.,CTCll!'
PIOCIIRI, ,
p.,CIIRI, ,
P.. CMA
P••C~'
P.. CIB
P..COS
p..
i::&
.i
..,
Vcc-
HD6301YO, HD63A01YO, HD63B01YO, HD63C01YO
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO + 85°C
(J VERSION)
Electrical Characteristics HD6301YO, HD63A01YO, HD63B01YO, and HD63C01YO
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Supply voltage
Vee
-0.3 to +7.0
V
Input voltage
Vin
-0.3 to Vee+0.3
V
Operating temperature
Topr
-40 to +85
'C
Storage temperature
Tstg
-55 to +150
'C
Note:
This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection circuits. To assure the
normal operatiol\ we recommend Vln •
VOU!:
Vss:i (V ln or Vou ,) ::'Vcc.
Electrical Characteristics
DC Characteristics
(Vee = 5.0 V ± 10%, f = 0.1 to 3.0 MHz, VSS = OV, Ta = -40 to +85°e, unless otherwise noted.)
Item
Input high voltage
RES, STBY,
EXTAL
Max
Symbot
Min
V,H
Vee-0.5
Vec+0.3
Unit
V
Vee X O.7
2.1
Vee+0.3
V
Vee+0.3
V
-0.3
0.8/0.6 3
V
Other inputs
Typ
Test Condition
Input low voltage
All other inputs
V,L
Input leakage current
RES, NMI, STBY,
MPO, MP,
I!;nl
1.0
J-IA
V,n=O.S to Vee-O.S V
Three state
leakage current
AO-A15, 00-07, RD,
WR, R/W, Porls2,5,6
IITsd
1.0
J-IA
V;n=O.S to Vee-O.S V
2.4
V
IOH=-200J-lA
Vee-0.7
V
IOH=-10 J-IA
Output high voltage
All Oulpuls
VOH
Output low voltage
All Outputs
VOL
Darlington drive
current
Ports 2, 6
-IOH
Input capaCitance
All other inputs
Cin
Standby current
Not operating
ISTB
ISLP
Current dissipation!
VRAM
V
IOL-1.6 mA
10.0
rnA
Vout=1.S V
12.=
pF
V;n=O V, 1=1 MHz,
Ta=2S'C
3.0
IS.0
J-IA
I.S
3.0
rnA
Sleeping
(1=1 MHz2)
2.3
4.S
rnA
Sleeping
(1=1.5 MHz2)
(1=2 MHz2)
1.0
lee
RAM standby voltage
0.4
3.0
6.0
mA
Sleeping
4.5
9.0
rnA
Sleeping (f=3 MHz»
7.0
10.0
rnA
Operating (1= 1 MHz2)
10.S
IS.0
rnA
Operating (I=I.S MHz2)
14.0
20.0
rnA
Operating (1=2 MHz2)
21.0
30.0
rnA
Operating (f=3 MHz2)
2.0
V
Notes:
1.
2.
VIII min=V,,--1.0V. VII_ max=O.8V (All output terminals are at no load,)
Current dissipation of the operating or sleeping condition is proportional to the operating frequency. So the tyPo or max. values about
current dissipations at x MHz operation are decided according to the following formula:
typo value
(1=.11' MHz)
=typ. value (f:;: 1 MHz) x x
max. value
(f=xMHz)
;:;;max. value (1=1 MHz)xJC
(both the sleeping and operating)
3. In case 01 SCLK ;nput. V,L = 0.6V (- 20°C - O'C)
~HITACHI
1297
I
HD6301YO,HD63A01YO,HD63B01YO,HD63C01YO
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO +85°C
(J VERSION)
AC Characteristics
(Vcc= 5.0V ± 100/0, f= 0.1 to 3.0 MHz, Vss =0 V, Ta =-40 to + 85°C, unless otherwise noted)
Bus Timing
HD6301YO
Item
Symbol
Min
r,p
HD63A01YO
II..
IIln
0.666
r,p
Min
10
0.5
r,p
M••
-
Unit
HDe3C01YO
HD63B01YO
M••
IIIIn
Typ
Cycle time
Icyc
10
10.
~s
Enable ris. time
tE,
25
25
25
20
ns
Enab*e fall time
tEl
25
25
25
20.
ns
Enable pulse width high level l
Enab'e pulse width low level I
Addres~ R/W delay time 1
tAO
Data delay time
(Write)
tDOW
Data set·up time
(R.. d)
Address. R/W hotd time l
(Write) I
Data hold timer
(Read)
10
0.333
PWEH
450
300
220
140
PWEl
450
300
220
140
190
250
200
160
ns
160
120
120
100
ns
ns
tOSR
70
60.
50
ns
tAH
80
50
40
20
ns
tHW
80
50
40
20
ns
tHR
0
0
0
ns
RD.
WR pulse width!
PWRW
RD,
WR delay time
tRWO
40
40
40
40
ns
RD,
WR hold time
tHRw
20.
20.
20.
20.
ns
UR delay time
IOlR
200
160
120
80
ns
UR
tHLR
hold time
Peripheral read access tbne 1
tACC
MR set·up time l
ISMR
300
220
140
ns
400
280
230
tHMR
E clock pulse width at MR
PWEMR
9
Processor con .....• "'l!t·up time
tpcs
Processor control rise time
tpc<
100
100
100
contr~
tpCf
100
100
100
tBA
250
190
160
BA delay time
Oscillator stabitization time
tRC
Reset pulse width
PWRST
ns
200
20
50
70.
ns
170.
100
fall time
ns
180
MR hold time 1
Processor
25
9
200
20
20
ns
Figs.I-3.
1·13,1-14'
50
ns
Figs. 1·2,
1-13'
50
ns
120
ns
20
ms
Ic,c
*Refer to Pages 611-614
~HITACHI
Fig. 1·2"
ns
~s
100
200
Note: 1. These timings chinge in approximate proportion to lcyc. The figures in this characteristics represent those when tcyc is minimum (=in
the hilhest .speed operation).
1298
Flg.I·P
ns
80
450
Test
Condition
Flg.I-3'
Fig. 1-14'
HD6301YO, HD63A01YO, HD63B01YO, HD63C01YO
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO +85°C
(J VERSION)
Peripheral Port Timing
HD6301Y0
Item
Peripheral data
set-up time
Peripheral data
hold time
(Ports 1, 2, 3,
4, S, 6)
(Ports 1, 2, 3,
4, S, 6)
Delay time (From
(Ports 1, 2, 3,
enable fall edge
4, S, 6, 7)
peripheral output)
Input strobe pulse
width
Input data hold
(Port 6)
time
Input data set-up
(Port 6)
time
Output strobe
time
Typ
HD63A01Y0
Max Min
Typ
HD63B01YO
Min
tposu
200
200
200
200
ns
tpoH
200
200
200
200
ns
300
Typ
300
Max Min
Typ
Test
Max Unit Condition
Symbol
tpwo
Max Min
HD63C01YO
300
300
ns
Fig. 1-6'
Fig. 1-10-
tPWIS
200
200
200
200
ns
tlH
lS0
lS0
lS0
lS0
ns
tiS
100
100
100
100
ns
200
tOS01
200
200
200
Fig. l-S'
ns
Fig. 1-11'
tOS02
• Refer to Pages 611-614
Timer, SCI Timing
HD6301Y0
Item
Symbol
Min
Timer 1 input pulse width
tPWT
2.0
Delay time (enable positive
transition to timer output)
tTOO
SCI input
clock cycle
Typ
HD63A01YO
Max Min
Typ
Max Min
2.0
400
HD63B01Y0
Typ
Max Min
Typ
Test
Max Unit Condition
2.0
2.0
400
HD63C01Y0
400
400
teye
Fig. I-g'
ns
Fig. 1-7, 1-8'
(Async. mode) tSeye
1.0
1.0
1.0
1.0
teye
Fig. I-g'
(Clock sync.)
2.0
2.0
2.0
2.0
teye
Fig. 1-4'
ns
Fig. 1-4'
SCI transmit data delay
time (Clock sync. mode)
SCI receive data set-up
time (Clock sync. mode)
SCI receive data hold time
(Clock sync. mode)
240
tTXO
240
240
240
tSRx
260
260
260
260
ns
tHRX
100
100
100
100
ns
SCI input clock pulse width
tpWSCK
0.4
Timer 2 input clock cycle
tteye
2.0
2.0
2.0
2.0
teye
Timer 2 input clock pulse width
tpWTCK
200
200
200
200
ns
Timer 10 2, SCI input clock
rise time
Timer 1 0 2, SCI input clock
fall time
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tSeye Fig. I-g'
tCKr
100
100
100
SO
ns
tCKf
100
100
100
SO
ns
• Refer to Pages 611-614
~HITACHI
1299
I
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO +85°C
(J VERSION)
HD6303R, HD63A03R,
HD63B03R
The HD6303R is an 8·bit CMOS micro processing unit
which has the completely compatible instruction set with the
HD6301VI. 128 bytes RAM, Serial Communication Interface
(SCI), parallel 1/0 ports and multi function timer are incorpora·
ted in the HD6303R. It is bus compatible with HMCS6800 and
can be expanded up. to 65k words. Like the HMCS6800 family,
1/0 levels is TIL compatible with +5.0V single power supply.
As the HD6303R is CMOS MPU, power disSipation is extremely
low. And also HD6303R has Sleep Mode and Stand.by Mode
as lower power dissipation mode. Therefore, flexible low power
consumption application is possible.
FEATURES
Object Code· Upward Compatible with the HD6BOO. HD68Dl.
HD6802
• Multiplexed Bus (Do-D,/Ao-A,l. Non Multiplexed Bus
,. Abundant On-<:hip Functions Compatible with the
HD6301Vl; 128 Bytes RAM. 13 Parallel I/O Lines. 16·bit
Timer. Serial Communication Interface (SCI)
• Low Power Consumption Mode; Sleep Mode. Stand·By Mode
HD6303RPJ, HD63A03RPJ,
HD63B03RPJ
•
•
•
Minimum Instruction Execution Time
l/A1 (t-1MHz). O.67j1$ (t-1.5MHz). O,5ps (f=2.OMHz)
•
•
Bit Manipulation. Bit Test Instruction
Error Detecting Function; Address Trap. Op Code Trap
•
Up to 65k Words Address Space
•
TYPE OF PRODUCTS
BUI Timing
Type No.
HD6303R
HD63AD3R
1.0 MHz
HD63BD3R
2.0MH.z
1.6 MHz
HD6303RCPJ, HD63A03RCPJ,
HD63B03RCPJ
(CP·52)
HD6303RF", HD63A03RF",
HD63B03RF"
• GENERIC PART NUMBER
HD6303RPJ,HD63A03RPJ,HD63B03RPJ
HD6303RCPJ,HD63A03RCPJ,HD63B03RCPJ
(Fp·54)
"Contact Hitachi Sales Office
~HITACHI
1300
HD6303R,HD63A03R,HD63B03R
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO
+85°C
(J VERSION)
•
PIN ARRANGEMENT
• HD6303RPJ, HD63A03RPJ,
HD63B03RPJ
• HD6303RF*,
HD63A03RF * ,
HD63B03RF'
• HD6303RCPJ, HD63A03RCPJ,
HD63B03RCPJ
AS
49
ANI
d~C)
.8 (Ne)
47 (NC)
.. 5 OIIA,
... OJIAI
O.jA.
..
Pll
..
"2 0.,,,,.
D!lA~
41 0'1 .....
..
DuA,
OJ/A,
NC
•
P,.
NC
Ao/P,Q
A,/PI1 1
A;./P'l
)
e,IA,
36 (Ne)
31 A.
A,
)6 AI
A,
NC
D./A..
NC
A"
35 A,g
34 (Ne,
NC
33 (Ne)
..,_ _ _ _ _ _~ Vee
(Top View)
(DP-40)
(Top View)
(FP-54)
(Top View)
(CP-52)
* Contact Hitachi Sales Office
•
BLOCK DIAGRAM
-'
-'«
~ ~;! ~ 1:!;ldl~
»Xww z~!a:
Address/
Data
t':1~:t+== P20
p"
1-1-+,,"--- P 22
I-I-++<~-
P 23
toi-++r.- P 2'
Buffers
~HITACHI
1301
HD6303R,HD63A03R,HD63B03R
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO + 85°C
(J VERSION)
•
ABSOLUTe MAXIMUM RATINGS
-0.3 -
VCC
V
+7.0
Vin
-0.3 - VCC +0.3
Operating Temperature'
Topr
-40 to +85
Storage Temperature
T stg
-55 to + 150
Input Voltage
Unit
Value
Symbol
Item
Supply Voltage
V
DC
DC
(NOTE) This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection circuits. To
assure the normal operation, we recommend Vin • Vout : Vss S (Vin or Vout) :S Vee·
OK version (-40 to + 125°C) available. Contact sales office .
•
DC CHARACTERISTICS (Vee
= 5.0V±10%, Vss = OV, To = -40 to
Item
+ BSoC, unless otherwise noted.)
Test Condition
Symbol
RES, S'fif'i'
Input "High" Voltage
EXTAL
V'H
Other Inputs
min
-
Vee xO.7
-
2.0
Input "Low" Voltage
All Inputs
V'l
Input Leakage Current
NMI, IRO., RES, STBY
lI'n I
V'n -0.5-Vee -o.5V
-
Three State (off-state)
Leakage Current
0 0 -0 7 , A.-A"
II Ts ,1
V'n =0.5-Vee -o.5V
-
IOH = -200p.A
2.4
P,o-P 17 , P'O-P'4,
typ
Vee-0.5
-0.3
max
Vee
Unit
V
-
+0.3
-
O.B
V
1.0
p.A
1.0
p.A
-
V
0.55
V
-
V
Output "High" Voltage
All Outputs
V OH
Output "Low" Voltage
All Outputs
VOL
IOl = I.SmA
-
C in
V'n=OV, f= 1.0MHz,
Ta = 25D C
-
-
12.5
pF
-
2.0
15.0
p.A
-
6.0
10.0
1.0
2.0
Input Capacitance
All Inputs
Standby Cu rrent
Non Operation
V,~Y)=0-0.6V
Ice
V'H(RES)=VCC- 0.5_ _ Vee V
V'L(RES)=0-0.6V
ioperating(f=1 MHz")
Current Dissipation *
lee
RAM Stand· By Voltage
V RAM
'V'H min
IOH - -10p.A
Sleeping (f=1 MHz")
Vee- 0.7
2.0
-
-
-
= Vcc-1 ..oV, V'l max =O.BV
•• Current Dissipation of the' operating or sleeping condition is proportional to the operating frequency. So the typo or max.
values about Current Dissipations at f = x MHz operation are decided according to the following formula;
tyP. value (I =xMHz)
max. value If =xMHz)
=typo value (I' 1MHz) xx
= max. value (f "'" 1 MHz) x x
(both the 'sleeping and operating)
~HITACHI
1302
rnA
V
HD6303R,HD63A03R,HD63B03R
•
AC CHARACTERISTICS (Vee
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO + 85°C
(J VERSION)
=5.0V±10%, Vss =OV, Ta = -40 to
+85°C, unless otherwise noted.)
BUS TIMING
Item
Symbol
Cycle Time
Address Strobe Pulse Width
"High"
PWASH
Address Strobe Rise Time,
tAs.
Address Strobe Fall Time
Address Strobe Delay Time
Enable Rise Time
Enable Fall Time
tAS!
tASD'
Enable Pulse Width "High" Level
Enable Pulse Width "Low" Level
Address Strobe to Enable Delay
Time
Address Delay Time
Address Delay Time for Latch
Write
Data Set-up Time
Read
Read
Data Hold Time
Write
Address Set-up Time for Latch
Address Hold Time for Latch
Addrtss Hold Time
Ao - A, Set·up Time Before E
I
Peripheral Read
Access Time
I
Test
Con·
'dition
1
tcyc
tE.
tEl
PWEH
PWEL
t ASED
---
~ Fig. 5·,"
tAD2
tADL
t DSW
Fig. 5-2··
Oscillator Slabil ization TIme
Pr!lcessor Control Set·up Time
(tACCM
tRC
Ipes
-
230
80
0
20
tDSR
tHR
tHW
tASL
tAHL
tAH
tASM
-
HD63A03R
HD63B03R
Unit
max min typ max min typ max
10 0.666
-
- 150
- - 20 - - 20 60 - 40
- - 20 - - - 20 - 450 - 300 450 - 300 60 - 40 - - 250 - - - 250 - 220
60
30
20
200
-
Non·Multiplexed (tACCN)
Bus
I Multiplexed Bus
HD6303R
min typ
-
-
250
-
-
150
60
0
20
650
-
- - -
650
40
20
20
110
-
-
-
10
- - 20
20 - , 20
- 20 - -
20
110
ns
-
ns
ns
ns
ns
-
- 20
- 20
- 220 - - 220 - - 20 - 190 - 160
190 - 160
190 - 160
- 100 - - 50 - 0 - 20 - - 20 - - 20 - - 20 - - 60 - 395 - 270
395 - 270
- 20 - - 200 - 20
20
ItS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
Fig. 2-1-1
20
Fig. 2-8-1
200
Test
Condition
HD63B03R
HD63A03R
HD6303R
Unit,
min typ max min typ max min typ max
.. -
20
-
10 0.5
200
PERIPHERAL PORT TIMING
Item
Symbol
Peripheral Data.
Port I, 2
IpDSU
Set·upTime
'Peripheral Data
Port 1,2
tpDH
Hold Time
Delay Time, Enable Nega-I Port 1
2'
' tPWD
tive Transition to Peri·
pheral Data Valid
Fig.s-a*·
Fig. 5-3"
Fig.5-S·'·
- 200
- 200 - - 200 - - - 300 - - 300 - - 300
200
-
-
200
- -
200
ns
ns
ns
• Except Pu
•• Refer tD Pages 189-190
••• Refer to Pages 159-160
~HITACHI
1303
I
HD6303R,HD63A03R,HD63B03R
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO +85°C
(J VERSION)
TIMER, SCI TIMING
Item
Timer Input Pulse Width
Delay Time, Enable Positive
Transition to Timer Out
SCI Input Clock Cycle
SCI Input Clock Pulse Width
Test
Symbol Condition
HD6303R
HD63A03R
HD63B03R
Unit
min typ max min typ max min typ max
tpWT
2.0
tTO O
-
Fi9...5-7
t Seve
tPWSCK
2.0
0.4
Test
Symbol Con·
dition
min
-
-
2.0
-
0.6
0.4
-
-
2.0
400
-
-
2.0
400
-
-
-
toye
400
ns
-
2.0
-
-
tCYC
0.6
0.4
-
0.6
tScye
MODE PROGRAMMING
Item
RES "low" Pulse Width
Mode Programming Set·up Time
Mode Programming Hold Time
PW RSTL
IMPS
tMPH
FI9;.5-8
HD63B03R
HD63A03R
HD6303R
Unit
typ max min typ max min typ max
3
2
150
-
-
-
3
2
150
"Refer to Pages 189-190
.HITACHI
1304
-
-
-
3
2
150
-
-
-
toye
Icye
ns
WIDE TEMPERATURE
SPECIFICATIONS
HD6303X, HD63A03X,
HD63B03X
The HD6303X is a CMOS 8-bit micro processing unit (MPU)
which includes a CPU compatible with the HD630IVI, 192
bytes of RAM, 24 parallel I/O pins, a Serial Communication
Interface (SCI) and two timers on chip.
FEATURES
Instruction Set Compatible with the HD6301Vl
II Abundant On-chip Functions
192 Bytes of RAM
24 Parallel 1/0 Ports
16-Bit Programmable Timer
B-Bit Reloadable Timer
Serial Communication Interface
Memory Ready
Halt
Error-Detection (Address Trap, Op Code Trap)
II Interrupts ... 3 External, 7 Internal
II Up to 65k Bytes Address Space
" Low Power Dissipation Mode
Sleep
Standby
II Minimum Instruction Execution Time
1115 (f = 1 MHz). 0.67 115 (f = 1.5 MHz). 0.5115 (f = 2.0
MHz)
o Wide Operating Range
VCC = 3 - 6V (f =0.1 - 0,5MHz).
f = 0.1 to 2.0 MHz (Vee = 5V ± 10%)
-40°C TO + 85°C
(J VERSION)
HD6303XPJ, HD63A03XPJ,
HD63B03XPJ
II
II
II
(DP-64S)
HD6303XCPJ, HD63A03XCPJ,
HD63B03XCPJ
TYPE OF PRODUCTS
Type No.
Bus Timing
HD6303X
1 MHz
HD63A03X
1.5 MHz
HD63B03X
2MHz
(Cp·68)
.. GENERIC PART NUMBER
HD6303XF* , HD63A03XF* ,
HD63B03XF*
HD6303XPJ,HD63A03XPJ,HD63B03XPJ
HD6303XCPJ, HD63A03XCPJ, HD63B03XCPJ
(FP-60)
*Contact HItachi Sales Office
~HITACHI
1305
HD6303X, HD63A03X, HD63B03X
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO + 85°C
(J VERSION)
•
PIN ARRANGEMENT
•
HD6303XPJ, HD63A03XPJ,
HD63B03XPJ
v.
• HD6303XCPJ, HD63A03XCPJ, HD63B03XCPJ
..
.',,
...
mv
"'""
'"' . "
'to '
_
"
o
.A
0,
0,
0,
0,
OIl
U,
0,
..
0,
0,
, 0,
'. '
'"
'"
'"
A,
A,
A,
A,
A,
A,
A,
A,
Po. 1
'".::~'
' .. 1
'"
'"
'"'"
'"
, ,e
I
u 0,
, 0,
'
'D,
p. . .
1'"
'.
1',.
H 0,
•
U
"
"
OJ
A.
P,. "
"
A,
p .. '.
Pot ••
• A,
.. A.
P" ••
P.. ot
(Top View)
(CP-68)
A"
A..
fA"
" A,
NC ..
Ne ..
A"
A..
A..
(Top View)
(Top View)
(DP-64S)
(FP-BO)
•
BLOCK DIAGRAM
'Contact Hitachi Sales Office
V(C _ _ _
'
vu--Vu _ _ _'
P,e>lTlnl
P"Houl1!
'0
Pu(SClK)
Pul Rx ,
w<
R:W
0'
P,.lhl
PnHout21
P,.lToutJI
P,,(Tclkl
D.
0,
0,
0,
0,
0,
0,
0,
A,
A,
A,
A,
A,
A,
P,o(iJRJ., -
A,
Ps,11Rill1
P"fMR)
Pu(~rTl
'.
'"
''"' ' -
A,
A,
A"
A ..
A ..
Au
A ..
'.
'"
'"
'"
'"
'"
'"
'"
A"
~HITACHI
1306
o.
" Ne
.. Ne
"
'Pot.. ..
' A,
A,
."
."''"'...
1' ..
POI "
v.
'"
'"
'"
'"
'rIO...•
,"
'"
~I~: ~:t
'ijMf •
)9 D.
54 He
'"
',,'
HD6303XF', HD63A03XF',
HD63B03XF'
~~w~igl,M_~I~!~6.
I~
0
XTAL
UTAl 1
•
HD6303X, HD63A03X, HD63B03X
•
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO + 85°C
(J VERSION)
ABSOLUTE MAXIMUM RATINGS
Unit
Symbol
Value
Supply Voltage
Vee
-0.3 - + 7.0
V
Input Voltage
Vin
-0.3 - Vee +0.3
V
Operating Temperature
Topr
-40 to +85
°C
Tstg
-55 to +150
°C
Item
Storage Temperature
(NOTE) This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection circuits. To
assure the normal operation, we recommend V in • Voul: Vss :.S (Vin or Vouu :S Vee.
•
•
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS IVee. 5.0V±10%. Vss· OV. Ta = -40 to +85°C, unless otherwise noted.)
Item
Test Condition
Symbol
RES.STBY
Input "High" Voltage
EXTAL
min
Vee-0.5
V IH
typ
max
Unit
-
Vee
+0.3
V
Port 22
Input "Low" Voltage
Pin 22
V IH
Vee xO•7
2.0
2.2
All Inputs
V IL
-0.3
-
0.8
V
Input "Low" Voltage
All Inputs
V IL
-0.3
-
0.8
V
1.0
/l.A
1.0
/l.A
-
V
Other Inputs
Input Leakage Current
Three State loff-state)
Leakage Current
Output "High" Voltage
NMI, RES, STBY,
MPo , MP.,Port 5
Ao-A". 0 0 -0,. RD.
WR. R/W.Port 2.Port 6
All Outputs
IIlnl
Vln = 0.5-V ee -0.5V
IITs"
Vin = 0.5-V ee -0.5V
V OH
-
IOH=-200/l.A
2.4
IOH =-10/l.A
Vee-O.7
Output "Low" Voltage
All Outputs
VOL
IOL ":1.6mA
-
Darlington Drive
Current
Ports 2. 6
-loH
Vout= 1.5V
1.0
I nput Capacitance
All Inputs
Cln
Vln = OV. f = lMHz.
Ta = 25°C
Standby Current
Non Operation
ISTB
-
Sleeping If = lMHz**)
IsLP
Sleeping If = ·1.5MHz**)
Sleeping If = 2MHz**)
Current Dissipation*
Operating If - lMHz**)
lee
Operating If = 1.5MHz**)
Operating If = 2MHz**)
RAM Standby Voltage
·VIH min· VCC-1.OV. VIL max
V RAM
a
-
2.0
-
V
-
V
0.4
V
10.0
mA
12.5
pF
3.0
15.0
1.5
3.0
4.5
/l.A
iliA
2.3
3.0
mA
mA
7.0
6.0
10.0
10.5
15.0
mA
14.0
20.0
mA
-
-
mA
V
C.BV • All output terminals are at no load .
•• Current Dislipation of tha operating or sleaping condition is proportional to the operating frequency. So the typo or max.
values about Current DiSSipations at x MHz operation are decided according to the following formula:
typo value (f - " MHz) - typo value If - 1MHz) • "
max. value (f = x MHz) • max. value (f == 1MHz) x x
(both the sleeping and operating)
~HITACHI
1307
I
HD6303X, HD63A03X, HD63B03X
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO +85°C
(J VERSION)
.• AC CHARACTERISTICS (Vcc·S.OV:l:10%.Vss.OV. Ta = -40 to +85°C,unlessotherwlsenoted.)
BUS TIMING
Item
Symbol
Test
Condition
min
1
Cycle Time
Enable Rise Time
tcye
tE,
linable Fall Time
Enable Pulse Width "High" Level'
Enable Pulse Width "Low" Level'
tEl
PW EH
450
PWEL
450
Address, R/WDelay Time'
Data Delay Time
Write
Data Set-up Time
Read
tAD
tDDW
tDSR
Fig. 1-13"
tAH
tHW
tHR
PWRW
tRwD
tHRW
tDLR
tHLR
tSMR
Fig. 1-14* *
tHMR
PWEMR
Fig. 1-15* *
tpcs
1-20,1-24
I
I
Address, R/WHold Time'
Write'
Data Hold Time
I Read
RD, WR Pulse Width'
RD, WR Delay Time
RD, WR Hold Time
LIR Delay Time
LIR Hold Time
MR Set-up Time'
MR Hold Time'
E Clock Pulse Width at MR
I
Processor Control Set·up Time
Processor Control Rise Time
Processor Control Fall Time
BA Delay Time
Oscillator Stabilization Time
Reset Pulse Width
tpc,
tpCI
tBA
tRC
PWRST
-
Fig. 1-14,
1-15* *
Fig. 1-15* *
Fig. 1-24**
HD6303X
typ
max
10
25
25
-
80
80
80
0
450
10
400
200
-
20
3
-
-
-
HD63A03X
min
0.666
-
-
300
250
200
-
-
70
50
50
0
300
-
40
30
200
300
-
-
10
280
90
9
-
-
200
-
100
100
250
-
-
-
20
3
-
-
-
typ
-
-.
-
-
max
10
25
25
min
0.5
-
-
220
220
190
160
-
-
-
-
-
-
-
40
-
-
30
160
-
-
-
-
70
35
40
0
220
-
-
-
10
230
40
9
-
-
200
-
100
100
190
-
-
-
-
-
-
-
20
3
HD63B03X
typ
max
..
-
10
25
25
Unit
liS
ns
0
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
liS
-
ns
-
100
-
-
ns
ns
ns
ms
-
-
160
120
-
-
-
-
-
-
-
-
-
40
25
120
-
-
-
-
100
160
tCYC
• The .. timings change in approximate proportion to teye. The figure. In thl. characteristics represent those when teye is minimum
I-In the hlghllt.peed operetionl.
* *Refer to Pages 472-476
PERIPHERAL PORT TIMING
Peripheral Data
Set·upTime
Peripheral Data
Hold Time
HD6303X
typ
max
Symbol
Test
Condition
Ports 2, 5, 6
tpDSU
Fig. 1-17* * 200
-
Ports 2, 5, 6
tpDH
Fig. 1-17* * 200
-
-
tPWD
Fig. 1-18* *
-
300
Item
Delay Time (Enable
Negative Transition to
Perlpherel Data Valid)
.1 Ports 2, 6
min
-
* *Refer to Pages 472-476
~HITACHI
1308
HD63A03X
typ
max
min
min
HD63B03X
typ
max
Unit
-
200
-
-
ns
200
-
-
200
-
-
ns
-
-
300
-
-
300
ns
200
HD6303X,HD63A03X,HD63B03X
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO + 85°C
(J VERSION)
TIMER SCI TIMING
Item
Timer 1 Input Pulse Width
Delay Time (Enable Positive
Transition to Timer Output)
SCI Input
Clock Cycle
1l Clock Sync.
Async. Mode
Symbol
tPWT
tTOO
t 5cyc
HD63A03X
HD6303X
Test
Condition
min
Fig. 1-21""
2.0
Fig. 1-19""
1-20
Fig. 1-21""
-
Fig. 1-16. 1-21"*
typ
HD63B03X
max
min
typ
-
-
2.0
-
400
-
-
1.0
-
2.0
200
-
-
-
-
290
-
-
max
min
-
-
2.0
400
-
1.0
-
-
1.0
2.0
-
-
2.0
-
-
200
-
-
290
-
-
290
~
max
Unit
-
t cvc
400
ns
-
t"yc
-
tcyc
200
ns
-
-
ns
100
-
-
ns
SCI Transmit Data Delay
Time (Clock Sync. Mode)
tTXO
SCI Receive Data Set·up
Time (Clock Sync. Mode)
tSRX
SCI Receive Data Hold Time
(Clock Sync. Mode)
tHRX
100
-
-
100
SCI Input Clock Pulse Width
tpWSCK
0.4
-
0.6
0.4
-
0.6
0.4
-
0.6
tsCYC
Timer 2 Input Clock Cycle
ttcvc
2.0
-
2.0
-
-
2.0-
-
-
tCyc
Timer 2 Input Clock Pulse
Width
tPWTCK
200
-
-
200
-
-
200
-
-
ns
Timer 1-2. SCI Input Clock
Rise Time
tCKr
-
-
100
-
-
100
-
-
100
ns
Timer 1-2, SCI Input Clock
Fall Time
tCKf
-
-
100
-
-
100
-
-
100
ns
Fig. 1-16""
Fig. 1-21""
""Refer to Pages 472-476
~HITACHI
1309
I
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO + 85°C
(J VERSION)
HD6303Y, HD63A03Y,
HD63B03Y, HD63C03Y
The HD6303Y is a CMOS 8-bit single-chip microprocessing unit
which conlains a CPU compatible with the CMOS 8-bit microcomputer HD630\V, 256 bytes of RAM, 24 parallel 110 pins, Serial
Communication Interface
CPU
WR
R/W
OR
BA
00
D.
..
::J
O.
!Ia
d.
III
0
..
....
~:s
"CIII
"c ..
«::J
III
Pso(iJm. )
PS,(iJm 2 )
P.2(MR )
PS3(RAi:T)
p •• (IS
)
PSS(OS )
PS.
PS'
p.o
P••
P02
POl
PO.
Pos
ps.
Ps,
'"tt:
l-
ID
l-
tt:
0
RAM
256Bvtes
~HITACHI
1312
D.
0,
Ao
A•
A2
A3
A.
As
As
A,
As
A.
A.o
A"
Au
A'3
A••
A,.
0
a..
a..
02
03
HD6303~HD63A03~HD63B03~HD63C03Y
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO + 85°C
(J VERSION)
1.2 HD6303Y, HD63A03Y, HD63B03Y, Electrical Characteristics
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Supply voltage
Vee
-0.3 to +7.0
V
Input voltage
Von
-0.3 to Vee+0.3
V
Operating temperature
Top'
-40 to +85
·C
Storage temperature
Tst.
-55 to +150
·C
NQte:
This product has protection circuits in input terminal from high statLc electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection circuits. To assure the
normal operation. we recommend Vln.
V,,~,: V.,~s.
(V"' or VOy ,) ;aVec_
Electrical Characteristics
DC Characteristics
(Vee = 5.0V ± 10%, f= 0.1 to 3.0 MHz, Vss = 0 V, Ta = -40 to + 85°C, unless otherwise noted)
Item
Input high voltage
Min
V,H
Vee-0.5
Vee+0.3
Unit
V
EXTAL
Vee x O.7
Vee+0.3
V
Other inputs
2.1
-0.3
Vee+0.3
V
08/0.6 3
1.0
"A
V;n=0.5 to Vee-O.5 V
1.0
Input low voltage
All other inputs
V,l
Input leakage current
RES, NMI, STBY,
MPO, MPl
lion 1
Ao-A15,Do-D7,RD
WR,R/W,Ports 2,5,6
IITsd
Three state
leakage current
Output high voltage
All outputs
VOH
Output low voltage
All outputs
VOL
Darlington drive
current
Ports 2, 6
-IOH
Input capacitance
All other Inputs
Cin
Standby current
Not operating
Current dissipation l
Max
V
"A
V;n=0.5 to Vee-O.5 V
2.4
V
IOH- -200 "A
Vee-0.7
V
IOH=-lO "A
1.0
0.4
V
IOl-1.6 mA
10.0
rnA
Vout=1.5V
12.5
pF
V;n=OV, 1=1 MHz
Ta=25'C
"A
ISTB
3.0
15.0
ISlP
1.5
3.0
mA
Sleeping
(1=1 MHz2)
2.3
4.5
rnA
Sleeping
(1=1.5 MHzZ)
(1=2 MHzZ)
lee
RAM standby vollage
Typ
Test Condition
Symbol
RES, STBY
V.AM
3.0
6.0
mA
Sleeping
4.5
9.0
mA
Sleeping (f=3MH z2)
7.0
10.0
rnA
Operating (1= 1 MHzZ)
10.5
15.0
mA
Operating (1=1.5MHzZ)
14.0
20.0
mA
Operating (1=2 MHz2)
21.0
30.0
mA
Operating (f=3MH z2)
2.0
V
Notes;
1
2.
V'H min=V« -l.OV, VII max;;;.O.8V (All output terminals are at no load.)
Current dISsipation of the operating or sleeping condition IS proportIonal to the operatmg frequency. So the tyPo or mal(. values about
current diSsipations at )( MHz operation are decided accordmg to the followmg formula:
typ. value
('= x MHz)
=typ. value (f = 1 MHz) X)(
max. value
(f=xMHz)
=max. value (f=1 MHz)xx
(both the sleeping and operatIng)
3.
In case of SCLK Input. V.l
= O.6V (- 20°C
.-. DOC)
~HITACHI
1313
I
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO +85°C
(J VERSION)
AC Characteristics
(Vee = 5.0V ±10%, 1=0.1 to 3.0 MHz, Vss=O V, Ta=-40 to +85°C, unless otherwise noted)
Bus Timing
H06303Y
Item
S,mbol
Cycle time
tcyc
Typ
Min
10
0.666
TJ'P
Max
Min
10
0.5
Typ
-
H063C03Y
H063B03Y
H063A03Y
Max
Max
10
0.333
Typ
-
Unit
10
.s
ns
ns
Enable rise time
IE.
25
25
25
20
EnabJe fall time
IE!
25
25
25
20
Enable pulse width high le.... el l
PWEH
450
300
220
140
ns
Enable pulse width low level I
PWEL
450
300
220
140
ns
Address, R/W delay time l
tAD
250
190
160
120
ns
Data delay time
(Write)
toow
200
160
120
100
ns
Data set·up time
(Read)
tOSR
80
70
60
50
ns
tAH
80
50
40
20
ns
50
40
20
ns
Address. R/W hold tlme l
Data hold time
RD,
,
Min
(Write) 1
tHW
IRead)
tHR
WR pulse widthl
PWRW
70
450
300
220
0
ns
140
ns
ffD, WR
delay time
tRWO
40
40
40
40
RD. WR
hold time
tHRW
20
20
20
20
nS
IOLR
200
160
120
80
ns
DR delay
DR
hold
time
tln'le
.Peripheral read access time I
MR set·up time!
MR hold
time l
E clock pulse width at MR
5
5
tHLR
tSMR
280
100
tHMR
230
ns
170
ns
25
9
PWEMR
200
Fig. 1-15*
ns
laO
50
70
Condition
ns
tAce
400
Test
Fig. 1-16'
ns
.s
200
200
FigS. 1-17,
Processor control set-up time
tpcs
Processor control rise time
tPCr
100
100
100
50
ns
Processor cl)ntrol fall time
tpCI
100
100
100
50
ns
SA delay time
tSA
250
190
160
120
ns
Fig. 1-17'
Oscillator stabilization time
tRe
ms
Fig. 1-28'
Reset pulse width
PWRST
Note: 1.
20
20
.20
ns
20
tcyc
These timings change in approximate proportion to leye. Tne figures in this characteristics represent those when teye IS minimum (=in
the highest speed operation).
'Refer to Pages 618-621
~HITACHI
1314
100
1-27. 1-28'
Figs.I-16.
1-17'
HD6303~HD63A03~HD63B03~HD63C03Y
WIDE TEMPERATURE
SPECIFICATIONS
-40°C TO +85°C
(J VERSION)
Peripheral Port Timing
H06303Y
Item
HD63A03Y
HD63B03Y
Symbol
Test
Min Typ Max Min Typ Max Min Typ Max Unit Condition
Peripheral data
set-up time
(Ports 2, 5,
6)
tpOSU
200
200
200
ns
Peripheral data
hold time
(Ports 2, 5,
6)
tpOH
200
200
200
ns
Delay time (From (Ports 2, 5,
enable fall edge to 6 7)
peripheral output) ,
tpwo
Input strobe pulse
width
tpWIS
200
200
tlH
150
tiS
100
Input data hold
time
(Port 6)
I~put data set-up (Port 6)
time
Output strobe
time
300
300
300 ns
Fig, 1-20'
200
ns
Fig, 1-35'
150
150
ns
100
100
ns
200
tOSOl
Fig, 1-19'
200
200 ns
Fig.I-25'
toS02
'Refer to Pages 618-621
Timer, SCI Timing
HD6303Y
Item
S""bol
Min
Timer 1 input pulse width
tPWT
2.0
Delay time (enable positive
tranSition to timer output)
tTOO
SClmput
clock cycle
~A5ync:.
mode)
lStye
(Clock sync.)
SCI transmit data delay
time (Clock sync. mode)
SCI receive data set-up
time (Clock sync. mode)
Typ
HD63B03Y
HD63A03Y
Max
Min
Typ
------Mal
2.0
400
Min
Fig.I-23'
Figs.
1~21.
'1-?_2_'_ _
1.0
1.0
!eye
Fig. 1-23'
2.0
2.0
teye
Fig. I-IS'
ns
Fig.I-1S'
240
tTXO
240
240
(Clock sync. mOde)
IHRX
100
100
100
SCI input clock pulse Width
tPWSCK
0.4
Timer 2 mput clock cycle
ttcvc
2.0
IPWTCX
200
Timer 1 • 2, SCI input clock
fall time
Condition
1.0
tSRX
nse time
ns
Test
2.0
260
Timer 1 • 2, SCI Input clock
Unit
!eye
400
400
260
Timer 2 mput clock pulse Width
Mal
2.0
260
SCI receive data hold time
Typ
0.6
0.4
0.6
0.4
ns
ns
0.6
2.0
2.0
200
tSeye
Fig. 1-23'
!eye
200
ns
leK,
100
100
100
ns
leKI
100
100
100
ns
'Refer to Pages 618-621
~HITACHI
1315
I
NOTES:
~HITACHI
1316
NOTES:
~HITACHI
1317
Hitachi America, Ltd.
SEMICONDUCTOR and IC DIVISION
Hitachi America, Ltd.
Semiconductor & IC Division
Hitachi Plaza
2000 Sierra Point Parkway
Brisbane, CA 94005-1819
Telephone: 415-589-8300
Telex: 17-1581
Twx: 910-338-2103
FAX: 415-583-4207
REGIONAL OFFICES
MID·ATLANTIC REGION
NORTHWEST REGION
SOUTHEAST REGION
Hitachi America, Ltd.
1700 Galloping Hill Rd.
Kenilworth, NJ 07033
201/245-6400
Hitachi America, Ltd.
2000 Sierra Point Parkway
Brisbane, CA 94005-1819
415/589-8300
Hitachi America, Ltd.
4901 N.W. 17th Way, Suite 302
Fort Lauderdale, FL 33309
305/491-6154
NORTHEAST REGION
SOUTH CENTRAL REGION
AUTOMOTIVE
Hitachi America, Ltd.
5 Burlington Woods Drive
Burlington, MA 01803
617/229-2150
Hitachi America, Ltd.
Two Lincoln Centre, Suite 865
5420 LBJ Freeway
Dallas, TX 75240
214/991-4510
Hitachi America, Ltd.
6 Parklane Blvd., #558
Dearborn, MI 48126
313/271-4410
NORTH CENTRAL REGION
Hitachi America, Ltd.
500 Park Blvd., Suite 415
Itasca, IL 60143
312/773-4864
SOUTHWEST REGION
Hitachi America, Ltd.
18300 Von Karman Avenue,
Suite 730
Irvine, CA 92715
714/553-8500
DISTRICT OFFICES
Hitachi America, Ltd.
3800 W. 80th Street
Suite 1050
Bloomington, MN 55431
612/896-3444
Hitachi America, Ltd.
21 Old Main Street, Suite 104
Fishkill, NY 12524
914/897-3000
Hitachi America, Ltd.
6161 Savoy Dr., Suite 850
Houston, TX 77036
713/974-0534
Hitachi (Canadian) Ltd.
2625 Queensview Dr.
Ottawa, Ontario, Canada K2A 3Y4
613/596-2777
~HITACHI®
1318
Hitachi America, Ltd.
401 Harrison Oaks Blvd.
Suite #317
Cary, NC 27513
919/481-3908
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2011:07:03 09:15:22-08:00 Modify Date : 2011:07:03 12:28:07-07:00 Metadata Date : 2011:07:03 12:28:07-07:00 Producer : Adobe Acrobat 9.43 Paper Capture Plug-in Format : application/pdf Document ID : uuid:a61c14a1-fdac-4b75-a3ce-7ad050146503 Instance ID : uuid:129aaa9d-c01b-4f52-83ca-95a11694ac49 Page Layout : SinglePage Page Mode : UseNone Page Count : 1338EXIF Metadata provided by EXIF.tools