HD64180 Users Manual Oct85

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IEC I INTEGRATED ELECTRONICS CORP.
2170 Paragon Drive
San Jose, Callfomla 95131
(408) 435-1000

HD64180
8-BIT HIGH INTEGRATION
CMOS MICROPROCESSOR
USER'S MANUAL

#U77

~HITACHI

When using this manual, the reader should keep the following in mind:
I.

This manual may, wholly or partially, be subject to change without
notice.

2.

All rights reserved: No one is permitted to reproduce or duplicate, in
any form, the whole or part ofthis manual without Hitachi's permission.

3.

Hitachi will not be responsible for any damage to the user that may result
from accidents or any other reasons during operation of his unit according to this manual.

4.

This manual neither ensures the enforcement of any industrial properties or other rights, nor sanctions the enforcement right thereof.

5.

Circuitry and other examples described herein are meant merely to
indicate characteristics and performance of Hitachi semiconductorapplied products. Hitachi assumes no responsibility for any patent infringements or other problems resulting from applications based on the
examples described herein.

October 1985

©Copyright 1985, Hitachi America Ltd.

Printed in U.S.A.

TABLE OF CONTENTS

Block Diagram ..................................................
Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Architecture. .. ... . . ... . ..... . . .. . ... . . . .... . . ... .. .. . .. . . . .
I/O Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3
4
5
6
6

HD64180 HARDWARE ARCHITECTURE................................

8

1. HD64180 OVERViEW.................................................

1.1
1.2
1.3
1.4
2.

2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15

3.

Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Bus Timing ................................................
WAIT State Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
HALT and Low Power Operation Modes. . . . . . . . .. . . . .. . . . . . . . . . . ..
Internal I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Memory Management Unit (MMU) ...............................
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Dynamic RAM Refresh Control ...................................
DMA Controller (DMAC) .......................................
Asynchronous Serial Communication Interface (ASCI) ..............
Clocked Serial I/O Port (CSIIO) ...................................
Programmable Reload Timer (PRT) ...............................
6800 Type Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
On-chip Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Miscellaneous...................................................

8
13
20
23
26
30
36
51
54
68
78
84
89
93
96

HD64180 SOFTWARE ARCHITECTURE ................................ 97

3.1
3.2
3.3

Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. 97
CPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 99
Addressing Modes ............................................... 102

4.

HD64180 PROGRAMMING NOTE ...................................... 105

5.

HD64180 ELECTRICAL CHARACTERiSTiCS ............................ 120

6.

HD64180 PACKAGE DIMENSiONS .................................... 132

APPENDIX

A
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 135
B
Instruction Summary in Alphabetical Order. . . . . . . . . . . . . . . . . . . . . . . .. 167
COp-code Map .................................................... 177
D
Bus and Control Signal Condition in each Machine Cycle ............ 181
E-l Request Acceptances in Each Operating Mode ...................... 200
E-2 Request Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
E-3 Operation Mode Transition ....................................... 202
F-l Status Signals .................................................... 2M
F-2 Pin Status during RESET and Low Power Operation Modes .......... 205
G
Internal VO Registers ............................................ 206
Hitachi Sales Offices Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

213

Figures
Figure No.

Description

1.1.1
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
2.3.1
2.4.1
2.4.2
2.5.1
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
2.6.7
2.7.1
2.7.2 (a)
2.7.2 (b)
2.7.3
2.7.4
2.7.5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Op-code Fetch Timing.... . ... . ...... .... . .. . . .. .... . . .. . . ..
Op-code Fetch Timing (with wait state) . . . . . . . . . .. . . . . . . . . . . ..
Memory ReadIWrite Timing (without wait state) .. . . . . . . . . . . ..
Memory ReadlWrite Timing (with wait state) . . . . . . . . . . . . . . . ..
1/0 ReadIWrite Timing .....................................
LD (IX + d), g Instruction Timing. . . . . . . . . . . . . . . . . . . . . . . . . . ..
RESET Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Bus Exchange Timing (1) . . .. ..... ....... .. . . ... .. .. . . . .. ...
Bus Exchange Timing (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
WAIT Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
HALT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SLEEP Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Internal 1/0 Address Relocation. . . . . . . . . . . . . . . . .. . . . . . . . . . . ..
Logical Address Mapping Examples..... .. . . . .... . . . . . ... . . ..
Logical - Physical Memory Mapping Example ................
MMU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1/0 Address Translatio,n: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Logical Memory Organization. .... .. ... .. . ... . ... . .. . . . .. .. ..
Logical Space Configuration (Example) . . . . . . . . . . . . . . . . . . . . . ..
Physical Address Generation... .. .. ... .. .. .. . . ... .. . . . .. .. . ..
Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TRAP Timing - 2nd Op-code Undefined. . . . . . . . . . . . . . . . . . . ..
TRAP Timing - 3rd Op-code Undefined .....................
NMI Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
NMI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
INTo Mode 0 Timing .......................................
(RST Instruction on the Data Bus)
INTo Mode 1 Interrupt Sequence. .. .... . . . .. . ... . .. . . . .. .. . ..
INTo Mode 1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
INTo Mode 2 Vector Acquisition. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
INTo Mode 2 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
INTl, INT2 and Internal Interrupts Vector Acquisition. . . . . . . . ..
INTl, INT2 and Internal Interrupts ;Timing . . . . . . . . . . . . . . . . . . ..
Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DMAC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Cycle Steal Mode DMA Timing .............................

2.7.6
2.7.7
2.7.8
2.7.9
2.7.10
2.7.11
2.8.1
2.9.1
2.9.2

Page
4
13
14
15
15
16
17
17
18
19
20
24
25
26
30
30
31
31
32
33
35
36
40
41
42
43
44
45
45
46
47
48
49
51
55
61

Figure No.

Description

2.9.3

CPU Operation and DMA Operation. . . . . . . . . . . . . . . . . . . . . . . ..
(DREQo is programmed for level sense)
CPU Operation and DMA Operation. . . . . . . . . . . . . . . . . . . . . . . ..
(DREQO is programmed for edge sense)
TENDo Output Timing ......................................
DMAC Interrupt Request Circuit Diagram ....................
NMI and DMA Operation ......................".............
ASCI Block Diagram .. . . . .. . . . . . . . .. .. .. . . . . . . . . .. .. . . . . ...
DCDo Timing ..............................................
RTSo Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ASCI Interrupt Request Circuit Diagram. . . . . . . . . . . . . . . . . . . . ..
ASCI Clock Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CSI/O Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CSI/O Interrupt Circuit Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Transmit Timing - Internal Clock. . . . . . . . . . . . . . . . . . . . . . . . . ..
Transmit Timing - External Clock ... . . . . . . . . . . . . . . . . . . . . . ..
Receive Timing - Internal Clock. . . . . . . . . . . . . . . . . . . . . . . . . . ..
Receive Timing - External Clock ...........................
PRT Block Diagram . .. .. .. . . . .. .. . . . .. . . . .. . . . . . .. . .. .. . ...
PRT Operation Timing ......................................
PRT Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PRT Interrupt Request Circuit Diagram. . . . . . . . . . . . . . . . . . . . . ..
E Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(During ReadlWrite Cycle and Interrupt
Acknowledge Cycle)
E Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(in BUS RELEASE Mode, SLEEP Mode)
External Clock Interface .....................................
Crystal Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Note for Board Design of the Oscillation Circuit . . . . . . . . . . . . . ..
Example of Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

2.9.4
2.9.5
2.9.6
2.9.7
2.10.1
2.10.2 (a)
2.10.2 (b)
2.10.3
2.10.4
2.11.1
2.11.2
2.11.3
2.11.4
2.11.5
2.11.6
2.12.1
2.12.2
, 2.12.3
2.12.4
2.13.1

2.13.2
2.14.1
2.14.2
2.14.3
2.14.4

Page
62
63
63
66
67
68
76
76
77
77
78
80
82
82
83
83
84
87
87
87
90

91
93
94
94
95

HD64180

HIGH INTEGRATION CMOS MPU

Based on a microcoded execution unit and advanced CMOS manufacturing
technology, the HD64180 is an 8-bit MPU which provides the benefits of high performance, reduced system cost and low power operation while maintaining compatibility with the large base of industry standard 8-bit software.
Performance is improved by virtue of high operating frequency, pipelining, enhanced instruction set and an integrated Memory Management Unit (MMU) with
512k bytes memory physical address space.
System cost is reduced by incorporating key system functions on-chip including
the MMU, two channel Direct Memory Access Controller (DMAC), wait state genera tor, dynamic RAM refresh, two channel Asynchronous Serial Communication
Interface (ASCI), Clocked Serial 1/0 Port (CSI/O), two channel 16-bit Programmable Reload Timer (PRT) , Versatile 12 source interrupt controller and a 'dual'
(68 x x, 80 x x) bus interface.
Low power consumption during normal CPU operation is supplemented by two
specific software controlled low power operation modes.
The HD64180, when combined with CMOS VLSI memories and peripherals, is
useful in system applications requiring high performance, battery power operation
and standard software compatibility.

High Performance, High Integration CPU.
Operating Frequency to 6 MHz.
On-Chip MMU Supports 512k Bytes Memory and 64k Bytes 110 Address Space.
Two Channel DMAC With Memory~ Memory, Memory~ 110 and
Memory~ Memory Mapped I/O Transfer Capability.
WAIT Input and Wait State Generator for Slow Memory and 110 Device Interface.
Programmable Dynamic RAM Refresh Addressing and Timing.
Two Channel, Full Duplex Asynchronous Serial Communication Interface
(ASCI) with Programmable Baud Rate Generator and Modem Control Handshake Signals.
Clocked Serial I/O Port (C.SIIO) with High Speed Operation (200k Bits/Second
at 4 MHz).
Two Channel 16-bit Programmable Reload Timer (PRT) for Counting, Timing
and Output Waveform Generation.
Versatile Interrupt Controller Manages Four External and Eight Internal Interrupt Sources.
'Dual Bus' Interface Compatible With All Standard Memory and Peripheral LSI.
On-chip Clock Generator.
Enhanced Standard 8-bit Software Architecture.
Fully Compatible with CP/M-80, CP/M Plus** and Existing System and Application Software.
Seven new Instructions including Multiply.
On-chip .110 Address Relocation Register for Board Level Compatibility with
Existing Systems and Software.
SLEEP mode and SYSTEM STOP mode for Low Power Operation.
VLSI CMOS Process Technology.
Low Power Operation - 75 m W at 6 MHz Operation.
19 m W SYSTEM STOP mode at 6 MHz operation
VCC = 5V + 10% - Fully TTL Compatible.

** CP/M-80 and CP/M plus are registered trademarks of Digital Research, Inc.

2

1. HD64180 OVERVIEW
1.1 Block Diagram
The HD64180 combines a high performance CPU core with many of the systems and I/O resources required by a broad range of applications.
The CPU core consists of five functional blocks.
o Clock Generator
o Bus State Controller
o Interrupt Controller
o Memory Management Unit (MMU)
o Central Processing Unit (CPU)
The integrated I/O resources comprise the remaining four functional blocks.
o DMA Controller (DMAC - two channels)
o Asynchronous Serial Communication Interface (ASCI - two channels)
o Clocked Serial I/O Port (CSI/O - one channel)
o Programmable Reload Timer (PRT - two channels)

TYPE OF PRODUCTS

Type No.
HD64A1S0ROP
HD64B1S0ROP
HD64A1S0ROF
HD64B1S0ROF
HD64A1S0ROCP
HD64B1S0ROCP

Clock Frequency (MHz)
4
6
4
6
4
6

Package
DP-64S
FP-64*
CP-6S*
* Under development

3

Timing
Generator

AldlTOUT

CPU

DREOl

16-bit
Programmable
Reload Timers

DMACs

TEND 1

(2)

(2)
II)

::;)

In

JlJ
~

TXS

TXAo
CKAo/DREOo

RXSlCTS"l

Asynchronous
SCI
(channel 0)

CKS

RXAo
RTSo
CTSo
DCDo

TXAl
MMU_

Asynchronous
SCI
(chanQel 1)

CKA1/TENDo
RXAl

-Vcc
-Vss

00-07

Figure 1.1.1 Block Diagram
4

1.2 Pin Assignment (Top View)
VSS

0
WR

nr
ME
iCE
REF
HArF

lmt),

omr;
CKS

RXS/CTS,
TXS
CKA,ITENDo
RXA,
TXA,
CKAo.76R'EOo

CTSo

WfSo
D7
D.
D.
D.
D3
D.
D,

(FP-64) • Under development

Do

33

Vss

(DP-64S)

Ao

A4
As

A6
A7
As
A9
44 D7

(CP-68) • Under development

5

1.3 CPU Architecture
The five CPU core functional blocks are described in this section.
Clock Generator

Generates the system clock (cb) from an external crystal or external clock input.
Also, the system clock is programmably prescaled to generate timing for the on-chip
I/O and system support devices.
Bus State Controller

Performs all status/control bus activity. This includes external bus cycle wait
state timing, RESET, DRAM refresh, and master DMA bus exchange. Generates
'dual-bus' control signals for compatibility with peripheral devices.
Interrupt Controller

Monitors and prioritizes the four external and eight internal interrupt sources. A
variety of interrupt response modes are programmable.
Memory Management Unit (MMU)

Maps the CPU 64k bytes logical memory address space into a 512k bytes physical memory address space. The MMU organization preserves software object code
compatibility while providing extended memory access and uses an efficient 'common area - bank area' scheme. I/O accesses (64k bytes I/O address space) bypass
the MMU.
Central Processing Unit (CPU)

The CPU is microcoded to implement an upward compatible superset of the 8bit standard software instruction set. Many instructions require fewer clock cycles for
execution and seven new instructions are added.

1.4 I/O Resources
DMA Controller (DMAC)

The two channel DMAC provides high speed memory ~ memory, memory ~ I/O and memory ~ memory mapped I/O transfers. The DMAC features edge or level sense request input, address incrementldecrementlno-change
and (for memory ~ memory transfers) programmable burst or cycle steal
transfer. In addition, the DMAC can directly access the full 512k bytes physical
memory address space (the MMU is bypassed during DMA) and transfers (up to
64k bytes in length) can cross 64k bytes boundaries. See Fig. 2.9.1 for further details.
Asynchronous Serial Communication Interface (ASCI)

The ASCI provides two separate full duplex U ARTs and includes programmable
baud rate generator, modem control signals, and a multiprocessor communication
format. The ASCI can use the DMAC for high speed serial data transfer, reducing
CPU overhead. See Fig. 2.10.1 for further details.
6

Clocked Serial I/O Port (CSI/O)

The CSI/O provides a half duplex clocked serial transmitter and receiver. This
can be used for simple, high speed connection to another microprocessor or microcomputer. See Fig. 2.11.1 for further details.
Programmable Reload Timer (PRT)

The PRT contains two separate channels each consisting of 16-bit timer data and
16-bit timer reload registers. The time base is divided by 20 (fixed) from the system
clock and PRT channel 1 has an optional output allowing waveform generation. See
Fig. 2.12.1 for further details.

7

2. HD64180 HARDWARE ARCHITECTURE
2.1 Signal Description
XTAL (IN) [2]

Crystal oscillator connection. Should be left open if an external TTL clock is
used. It is noted this input is not a TTL level input. See Table D.C. characteristics.
EXTAL (IN) [3]

Crystal oscillator connection. An external TTL clock can be input on this line.
This input is schmitt triggered.

cp

(OUT) [64]

/

System Clock. The frequency is equal to one-half of crystal oscillator.
RESET - CPU Reset (IN) [7]

When LOW, initializes the HD64I80 CPU. All output signals are held inactive
during RESET.
Ao-A17 - Address Bus (OUT, 3-STATE) [13-30]
A1s!TOUT [31]

I9-bit address bus provides physical memory addresses of up to SI2k bytes. The
address bus enters the high impedance state during RESET and when another device acquires the bus as indicated by BUSREQ and BUSACK LOW. AlB is mUltiplexed with the TOUT output from PRT channell. During RESET, the address
function is selected. TOUT function can be selected under software control.
00-07 - Data Bus (IN/OUT, 3-STATE) [34-41]

Bidirectional 8-bit data bus. The data bus enters the high impedance state during
RESET and when another device acquires the bus as indicated by BUSREQ and
BUSACKLOW.
RD -

Read (OUT, 3-STATE) [63]

Used during a CPU read cycle to enable transfer from the external memory or
I/O device to the CPU data bus.
WR - Write (OUT, 3-STATE) [62]

Used during a CPU write cycle to enable transfer from the CPU data bus to the
external memory or I/O device.
ME - Memory Enable (OUT, 3-STATE) [59]

Indicates memory read or write operation. The HD64I80 asserts ME LOW in
the following cases.
(a) When fetching instructions and operands.
(b) When reading or writing memory data.
(c) During memory access cycles of DMA.
8

(d) During dynamic RAM refresh cycles.
10E - I/O Enable (OUT, 3-STATE) [58]

Indicates 110 read or write operation. The HD64180 asserts 10E LOW in the
following cases.
(a) When reading or writing 110 data.
(b) During I/O access cycles of DMA.
(c) During INTo acknowledge cycle
WAIT -

Bus Cycle Wait (IN) [4]

Introduces wait states to extend memory and I/O cycles. If LOW at the falling
edge of T2, a wait state (Tw) is inserted. Wait states will continue to be inserted
until the WAIT input is sampled-HIGH at the falling edge of Tw, at which time the
bus cycle will proceed to completion.
E -

Enable (OUT) [60]

Synchronous clock for connection to HD63 x x series and other 6800/6500
series compatible peripheral LSIs.
BUSREQ -

Bus Request (IN) [6]

Another device may request use of the bus by asserting BUSREQ LOW. The
CPU will stop executing instructions and places the address bus, data bus, RD, WR,
ME and IOE in the high impedance state.
BUSACK -

Bus Acknowledge (OUT) [5]

When the CPU completes bus release (in response to BUSREQ LOW), it will
assert BUSACK LOW. This acknowledges that the bus is free for use by the requesting device.
HALT - Halt/Sleep Status (OUT) [56]

Asserted LOW after execution of the HALT or SLP instructions. Used with LIR
and ST output pins to encode CPU status.
LIR - Load Instruction Register (OUT) [61]

Asserted LOW when the current cycle is an op-code fetch cycle. Used with
=-=--=-=HALT and ST output pins to encode CPU status.
ST - Status (OUT) [12]

Used with the HALT and LIR output pins to encode CPU status.

9

Table 2.1.1 Status Summary

ST

HALT

LlR

0

1

0

1

1

0

CPU operation
(2nd op-code and
3rd op-code fetch)

1

1

1

CPU operation
(MC except for op-code fetch)

0

X

1

DMA operation

0

0

0

HALT mode

1

0

1

SLEEP mode (including
SYSTEM STOP mode)

NOTE

Operation
CPU operation
(1 st op-code fetch)

X: Don't care
MC: Machine cycle

REF - Refresh (OUT) [57]

When LOW, indicates the CPU is in the dynamic RAM refresh cycle and the
low-order 8 bits (Ao-A7) of the address bus contain the refresh address.
NMI - Non-Maskable Interrupt (IN) [8]

When edge transition from HIGH to LOW is detected, forces the CPU to save
certain state information and vector to an interrupt service routine at address
0066H. The saved state information is restored by executing the RETN (Return
from Non-Maskable Interrupt) instruction.
INTo - Maskable Interrupt Level 0 (IN) [9]

When LOW, requests a CPU interrupt (unless masked) and saves certain state
information unless masked by software. INTo requests service using one of three
software programmable interrupt modes.
Mode
0

Operation
Instruction fetched and executed from data bus.

1

Instruction fetched and executed from address 0038H.

2

Vector System data bus.

Low-order 8 bits vector table address fetched from

In all modes, the saved state information is restored by executing RETI (Return
from Interrupt) instruction.
INTI, INT2 - Maskable Interrupt Level 1, 2 (IN) [10,11 ]

When LOW, requests a CPU interrupt (unless masked) and saves certain state
information unless masked by software. INTI and INT2 (and internally generated interrupts) request interrupt service using a vector system similar to Mode 2 of INTo.
10

DREQo - DMA Request - Channel 0 (IN) [47]

When LOW (programmable edge or level sense), requests DMA transfer service from channel 0 of the HD64180 DMAC. DREQo is used for Channel 0 memory
~ I/O and memory ~ memory mapped I/O transfers. DREQo is not used
for memory ~ memory transfers. This pin is multiplexed with CKAo.
TENDo - Transfer End - Channel 0 (OUT) [60]

Asserted LOW synchronous with the last write cycle of channel 0 DMA transfer
to indicate DMA completion to an external device. This pin is multiplexed with
CKAl.
DREQl - DMA Request - Channel 1 (IN) [64]

When LOW (programmable edge or level sense), requests DMA transfer service from channel I of the HD64180 DMAC. Channell supports Memory ~ 1/
o transfers.
TENDl - Transfer End - Channel 1 (OUT) [66]

Asserted LOW synchronous with the last write cycle of channel I DMA transfer
to indicate DMA completion to an external device.
TXAo - Asynchronous Transmit Data - Channel 0 (OUT) [46]

Asynchronous transmit data from channel 0 of the Asynchronous Serial Communication Interface (ASCI).
RXAo - Asynchronous Receive Data - Channel 0 (IN) [46]

Asynchronous receive data to channel 0 of the ASCI.
CKAo - Asynchronous Clock - Channel 0 (IN/OUT) [47]

Clock input/output for channel 0 of the ASCI. This pin is multiplexed (software
selectable) with DREQo.
RTSo - Request to Send - Channel 0 (OOT) [42]

Programmable modem control output signal for channel 0 of the ASCI.
CTSo - Clear to Send - Channel 0 (IN) [43]

Modem control input signal for channel 0 of the. ASCI.
DCDo - Data Carrier Detect - Channel 0 (IN) [44]

Modem control input signal for channel 0 of the ASCI.
TXAl - Asynchronous Transmit Data - Channel 1 (OUT) [48]

Asynchronous transmit data from channel I of the ASCI.
RXAI - Asynchronous Receive Data - Channel 1 UN) [49]

Asynchronous receive data to channel I of the ASCI.
11

CKAt - Asynchronous Clock - Channel 1 (IN/OUT) [50]

Clock input/output for channell of the ASCI. This pin is multiplexed (software
selectable) with TENDo.
CTSI - Clear to Send - Channel 1 (IN) [52]

Modem control input signal for channel 1 of the ASCI. This pin is multiplexed
(software selectable) with RXS.
TXS - Clocked Serial Transmit Data (OUT) [51]

Clocked serial transmit data from the Clocked Serial 110 Port (CSIIO).
RXS - Clocked Serial Receive Data (IN) [52]

Clocked serial receive data to the CSI/O. This pin is multiplexed (software selectable) with ASCI channell CTSI modem control input.
CKS - Serial Clock (IN/OUT) [53]

Input or output clock for the CSIIO.
TOUT - Timer Output (OUT) [31]

Pulse output from Programmable Reload Timer channell. This pin is multiplexed (software selectable) with AlB (Address 18).
Vcc - Power Supply [32]
Vss - Ground [1,33]
Multiplexed pin descriptions

AlB/TOUT

CKAo/DREQo
CKAtlTENDo

RXS/CTSI

[31] During RESET, this pin is initialized as AlB pin. If either
TOC 1 or TOCO bit in Timer Control Register (TCR) is set
to 1, TOUT function is selected.
If TOC 1 and TOCO bits are cleared to 0, AlB function is
selected.
[47] During RESET, this pin is initialized as CKAo pin. If either
DMI or SMI in DMA Mode Register (DMODE) is set to
1, D REQo function is always selected.
[50] During RESET, this pin is initialized as CKAI pin. If
CKAID bit in ASCI control register ch 1 (CNTLAl) is set
to 1, TENDo function is selected. If CKAID bit is set to 0,
CKAI function is selected.
[52] During RESET, this pin is initialized as RXS pin. If CTSIE
bit in ASCI status register chI (STATl) is set to 1, CTSI
function is selected.
If CTS 1E bit is set to 0, RXS function is selected.

12

2.2 CPU Bus Timing
This section explains the HD64180 CPU timing for the following operations.
(1) Instruction (op-code) fetch timing.
(2) Operand and data read/write timing.
(3) 110 read/write timing.
(4) Basic instruction (fetch and execute) timing.
(5) RESET timing.
(6) BUSREQ/'=BU~SA-:-C=K= bus exchange timing.
The basic CPU operation consists of one or more "machine cycles" (MC). A
machine cycle consists of three system clocks, Tl, T2 and T3 while accessing memory or 110, or it consists of one system clock, Ti while the CPU internal operation.
The system clock (cf» is half frequency of crystal oscillation (Ex. 8 MHz crystal ~
cf> of 4 MHz, 250 nsec). For interfacing to slow memory or peripherals, optional wait
states (Tw) may be inserted between T2 and T3.
2.2.1 Instruction (op-code) fetch timing

Fig. 2.2.1 shows the instruction (op-code) fetch timing with no wait states.
An op-code fetch cycle is externally indicated when the LIR (Load Instruction
Register) output pin is LOW.
In the first half of Tl, the address bus (Ao-A18) is driven with the contents of
the Program Counter (PC). Note that this is the translated address output of the
HD64180 on-chip MMU.
In the second half of Tl, the ME (Memory Enable) and RD (Read) signals are
asserted LOW, enabling the memory.
The op-code on the data bus is latched at the rising edge of T3 and the bus cycle
terminates at the end of T3.

I"
T1

Op-code fetch cycle

T2

T3
I
I

Ao-A1i>1
00-07

===:x

_I
T1

T2

I
I

I

I

i PC
X PC + 1
i (O:p-code)>-----1

I

I

WAIT

::::::::::~::::::::::::::::

LJR

~

-

ME
RO

I
I

I
I

:

:1

i

I
I

\ :I

:

I
I

I
I

\:
i

I

I

~

1

,~_______

\~--

Figure 2.2.1 Op-Code Fetch Timing

13

Fig. 2.2.2 illustrates the insertion of wait states (Tw) into the op-code fetch cycle. Wait states (Tw) are controlled by the external WAIT input combined with an
on-chip programmable wait state generator.
At the falling edge of T2 the combined WAIT input is sampled. If WAIT input
is asserted LOW, a wait state (Tw) is inserted. The address bus, ME, RD and LIR
are held stable during wait states. When the WAIT is sampled inactive HIGH at the
falling edge of Tw, the bus cycle enters Ta and completes at the end of Ta.
Op-code fetch cycle
Tw

Ao-A 18

00-07

=:=J<____

Tw

-'x'-_____

+--_ _....L---+_ _ _

----1_ _ _

I
I

I

,...I~---...

------~---:----~:-«OP-COde)>------I

--------------

_______________

I

I

\~----~---.J

~
\

i

~--- I ~---r_+__._-I----------------------1\/
/ I \ I
I
I

I
I

I
I

I
I
I
I

I

\

I
I

"-t---------------------I

II
I
I
i

I
I
I
I

I

\ ____

I

\--.___

Figure 2.2.2 Op-Code Fetch Timing (with wait state)

2.2.2 Operand and data read/write timing

The instruction operand and data read/write timing differs from op-code fetch
timing in two ways. First, the LIR output is held inactive. Second, the read cycle
timing is relaxed by one-half clock cycle since data is latched at the falling edge of
Ta.
Instruction operands include immediate data, displacement and extended addresses and have the same timing as memory data reads.
During memory write cycles the ME signal goes active in the second half of Tl.
At the end of TI, the data bus is driven with the write data.
At the start of T2, the-WR signal is asserted LOW enabling the memory. ME
and WR go inactive in the second half of Ta followed by deactivation of the write,
data on the data bus.
Wait states (Tw) are inserted as previously described for op-code fetch cycles.
Fig. 2.2.3 illustrates the read/write timing without wait states (Tw), while Fig.
2.2.4 illustrates read/write timing with wait states (Tw).

14

+.

Read cycle

Ao-A1'~
00-07

:
I

==x

Write cycle

I
I

I

Memory address :
I

,

I

I

I

,

X""'-"'--M-e-m-Ory;-a-d-d-re-s-s---X==
:

----------t-i--<~ead ~at~

I

~rite data

(

I

)>----

,

-----------~-----T------r-----~---------------- - - _______ J
I \.. ____ '- _____ ..1 ____ J : '----------------

\

I
I

I
,

I
,

II

'
, /

I
I
\ ' - - - - t -II_ _ _-oJ/

: ,

\

I

:I

:I /

:I

I
:

I
I

I
I

\~I______~/

I

I

I

Figure 2.2.3 Memory Read/Write Timing (without wait state)

Write cycle

Read cycle
T2

T2

Tw

Tw

Ao-A1M

===x_____~---~--~:---JX~~---T----+-----,

00-07

- - - - - - - - - - , . . . ,- - - t - I-<6ead
I
I

dat~

:(

Write data

I

I

I

;

,

,

I

I

I

,

I

I

I

I

----------""\
: /----~------I-------,-----\:
r---r-h------------- -- --4----.1
I \.. _____ +
_______ }_____ ~---J
1\..------\

I , /

,\,
/
, ~--~,---~----~

I
i

I /

i
I

I

I

:I

:I

I

I

~--T-----+'---~iJ

I

\ ,-.__-+___~I---~I.

I

I
:

I
I

\:

!

Figure 2.2.4 Memory Read/Write Timing (with wait state)

15

/

~I-----~------~

2.2.3 I/O read/write timing

I/O instructions cause data read/write transfer which differs from memory data
transfer in the following three ways. The 10E (I/O Enable) signal is asserted LOW
instead of the ME signal. The 16-bit lID address is not translated by the MMU and
A16-A18 are held LOW. At least one wait state (Tw) is always inserted for I/O read
and write cycles (except internal I/O cycles).
Fig. 2.2.5 shows I/O read/write timing with the automatically inserted wait state
(Tw).
1/0 write cycle

1/0 read cycle

I-

T2

Tw

T3

I
I

Ao-A18

=X~

1

I

__I.;...IO~ad.;;;...d;,;.;.r..;..;es=s_-L-_ _-+-:____X

: 1/0 address

1

00-07

------+
---.,..-«~
I

I

I

I

:(

I

1

I

>

Write data

--------4-----~----i-----i-----t--~------- - - - - - - - - .J ____
\.---..,------r----- -1- - ----- -~~-

I

__

J:

I

I

~I---TI----~I~I
I
I
I

I

I

I

I

\

1
I
I
I

~
I
1/
\'-____~----~I----~I~

i

1

1

I

\

!:

,--

:
1

/

'--~----------~

NOTE: A16-A18 = 0 for 1/0 cycles

Figure 2.2.5 I/O ReadlWrite Timing
2.2.4 Basic instruction timing

An instruction may consist of a number of machine cycles including op-code
fetch, operand fetch and data read/write cycles. An instruction may also include cycles for internal processing in which case the bus is idle.
The example in Fig. 2.2.6 illustrates the bus timing for the data transfer instruction LD (IX + d) ,g. This instruction moves the contents of a CPU register (g) to the
memory location with address computed by adding an sign,ed 8-bit displacement (d)
to the contents of an index register (IX).
The instruction cycle starts with the two machine cycles to read the two bytes
instruction op-code as indicated by LIR LOW. Next, the instruction operand (d) is
fetched.
The external bus is idle while the CPU computes the effective address. Finally,
the computed memory location is written with the contents of the CPU register (g).

16

I.

1st op-code
fetch cycle

. I..

2nd op-code, Displacement
fetch cycle
read cycle

I
as..

.. I.

CPU internal
operation

I
.

Memory

Next instruction

'I•.• write cycle a·.I fetch cycle

t/J

Ao-A18

)(

PC
(DOH)

X

PC+1

X

PC+2

(70H-77H)

d

X

IX+d

~

g

00-01

UR
ME
RD

WR

Machine Cycle
MC1

MC7

MC3

MC2

=

NOTE: d
displacement
g = register contents

Figure 2.2.6 LO (IX + d), g Instruction Timing

2.2.5 RESET timing

Fig. 2.2.7 shows the HD64180 hardware RESET timiilg. If the RESET pin is
LOW for six or more than six clock cycles, processing is terminated and the
HD64180 restarts execution from (logical and physical) address OOOOOH.

I

RESET Start

RESET

I

I
I

'-,.1_6_o_r_m_o_re_th_a_n_6_c_IO_C_kS--t:~ 1

~

High impedance
~
--=----=--------<,
Restart address(OOOOOH)

Ao - A 1 a _ _ _ _ _ _ _ _ _-'r-'~I

Figure 2.2.7 RESET Timing
17

2.2.6 BUSREQ/BUSACK bus exchange timing

The HD64180 can coordinate the exchange of control, address and data bus
ownership with another bus master. The alternate bus master can request the bus
release by asserting the BUSREQ (Bus Request) input LOW. After the HD64180
releases the bus, it relinquishes control to the alternate bus master by asserting the
BUSACK (Bus Acknowledge) output LOW.
The bus may be released by the HD64180 at the end of each machine cycle. In
this context a machine cycle consists of a minimum of 3 clock cycles (more if wait
states are inserted) for op-code fetch, memory read/write and I/O read/write cycles.
Except for these cases, a machine cycle corresponds to one clock cycle.
When the bus is released, the address (Ao-A18), data (Do-D7) and control (ME,
IOE, RD, and WR) signals are placed in the high impedance state.
Note that dynamic RAM refresh is not performed when the HD64180 has released the bus. The alternate bus master must provide dynamic memory refreshing
if the bus is released for long periods of time.
Fig. 2.2.8 illustrates BUSREQ/BUSACK bus exchange during a memory read
cycle. Fig. 2.2.9 illustrates bus exchange when the bus release is requested during an
HD64180 CPU internal operation. BUSREQ is sampled at the falling edge of the
system clock prior to Ta, Ti and Tx (BUS RELEASE state). If BUSREQ is asserted
LOW at the falling edge of the clock state prior to Tx, another Tx is executed.

I~
T1

CPU memory read cycle

T2

Tw

-IT3

Tx

Bus release cycle

Tx

_I_ CPU cycle

Tx

T1

cp
Ao-A18

=x

c=

)

c=

0

Do-D7
ME,IOE
RD, WR
BUSREQ

)

/

\

BUSACK

\
Figure 2.2.8 Bus Exchange Timing (1)

18

I

CPu internal operation

Ti

Ti

Ti

Bus release cycle

·1-

ITi

Tx

Tx

_I_CPU

Tx

cycle

T1

cJ>

Ao-A18

)

c=

)

c=

00-07
ME,IOE
RO,WR
BUSREQ

\

/

BUSACK

\
Figure 2.2.9 Bus Exchange Timing (2)

19

/

2.3 WAIT State Generator
2.3.1 Wait state timing

To ease interfacing with slow memory and 1/0 devices, the HD64180uses wait
states (Tw) to extend bus cycle timing. A wait state (s) is inserted based on the combined (logical OR) state of the external WAIT input and an internal programmable
wait state (Tw) generator. Wait states (Tw) can be inserted in both CPU execution
and D MA transfer cycles.
2.3.2 WAIT input

When the external WAIT input is asserted LOW, wait state (Tw) are inserted
between T2 and Ta to extend the bus cycle duration. The WAIT input is sampled at
the falling edge of the system clock in T2 or Tw. If the WAIT input is asserted LOW
at the falling edge of the system clock in Tw, another Tw is inserted into the bus cycle. Note that WAIT input transitions must meet specified set-up and hold times.
This can easily be accomplished by externally synchronizing WAIT input transitions
with the rising edge of the system clock.
Dynamic RAM refresh is not performed during wait states (Tw) and thus systems designs which uses the automatic refresh function must consider the affects of
the occurrence and duration of wait states (Tw).
Figure 2.3.1 shows WAIT timing.

\ C\ I 7

\~

_ _ _ __

Figure 2.3.1 WAIT Timing

2.3.3 Programmable wait state insertion

In addition to the WAIT input, wait states (Tw) can also be programmably inserted using the HD64180 on-chip wait state generator. Wait state (Tw) timing applies for both CPU execution and on-chip DMAC cycles.
By programming the 4 significant bits of the DMA/WAIT Control Register
(DCNTL), the number of wait states (Tw) automatically inserted in memory and II
o cycles can be separately specified. Bits 4, 5 specify the number of wait states (Tw)
inserted for 110 access and bits 6, 7 specify the number of wait states (Tw) inserted
for memory access.

20

DMAIWAIT Control Register (DCNTL : 1/0 Address = 32H)
bit

6

7

4

5

51

MWI1

MWIO

IWI1

IWIO

R/W

RIW

RIW

RIW

I

II

The number of wait states (Tw) inserted in a specific cycle is the maximum of
the number requested by the WAIT input, and the number automatically generated
by the on-chip wait state generator.
OBit 7,6 : MWI1, MWIO (Memory Wait Insertion)

For CPU and DMAC cycles which access memory (including memory mapped
I/O), 0 to 3 wait states may be automatically inserted depending on the programmed
value in MWIl and MWIO.
MWI1

MWIO

The number of wait states

0
0

0

1

0

1

1

0
1
2
3

1

21

OBit 5, 4: IWI', IWIO (I/O Wait Insertion)

For CPU and DMA cycles which access external 110 (and interrupt
acknowledge cycles), 1 to 6 wait states (Tw) may be automatically inserted depending on the programmed value in IWIl and IWIO.
the number of wait states
For extemal 1/0
registers accesses

For intemal VO
registers accesses

For INTo interrupt
acknowledge cycles when UR is
LOW

1W11

IWIO

0

0

1

0

1

2

0

4

1

0

3

(Note (1))

5

1

1

4

For INTI, INT2 and
intemal interrupts
acknowledge cycles
(Note (2))

For NMI interrupt
acknowledge cycles when UR is
LOW
(Note (2))

2
2

0

6

Note:
(1) For HD64180 internal 1/0 register access (IIO addresses OOOOH-003FH), IWIl and IWIO do
not determine wait state (Tw) timing. For ASCI, CSIIO and PRT Data Register accesses, 0 to
4 wait states (Tw) will be generated. The number of wait states inserted during access to these
registers is a function of internal synchronization requirements and CPU state.
All other on-chip 110 register accesses (Le. MMU, DMAC, ASCI Control Registers, etc.)
have 0 wait states inserted and thus require only three clock cycles.
(2) For interrupt acknowledge cycles in which LIR is HIGH, such as interrupt vector table read
and PC stacking cycle, memory access timing applies.

2.3.4 WAIT input and RESET

During RESET, MWIl, MWIO, IWIl and IWIO are all set= 1, selecting the
maximum number of wait states (Tw) (3 for memory accesses, 4 for external 110
accesses).
Also, note that the WAIT input is ignored during RESET. For example, if RESET is detected while the HD64180 is in a wait state (Tw), the wait stated cycle in
progress will be aborted, and the RESET sequence initiated. Thus, RESET has higher priority than WAIT.

22

2.4 HALT and Low Power Operation Modes
The HD64180 can operate in 4 different modes. HALT mode, 10STOP mode
and two low power operation modes - SLEEP and SYSTEM STOP. Note that in
all operating modes, the basic CPU clock (XT AL, EXT AL) must remain active.
2.4.1 HALT mode

HALT mode is entered by execution of the HAL T instruction (op-code
76H) and has the following characteristics.
(1) The internal CPU clock remains active.
(2) All internal and external interrupts can be received.
(3) Bus exchange (BUSREQ and BUSACK) can occur.
(4) Dynamic RAM refresh cycle (REF) insertion continues at the programmed
interval.
(5) I/O operations (ASCI, CSI/O and PRT) continue.
(6) The DMAC can operate.
(7) The HALT output pin is asserted LOW.
(8) The external bus activity consists of repeated 'dummy' fetches of the op-code
following the HALT instruction.
Essentially, the HD64180 operates normally in HALT mode, except that instruction execution is stopped.
HALT mode can be exited in the following two ways.
RESET Exit from HALT mode

If the RESET input is asserted LOW for at least six clock cycles, HALT mode is
exited and the normal RESET sequence (restart at address: OOOOOH) is initiated.
Interrupt Exit from HALT mode

When an internal or external interrupt is generated, HALT mode is exited and
the normal interrupt response sequence is initiated.
If the interrupt source is masked (individually by enable bit, or globally by IEFl
state), the HD64180 remains in HALT mode. However, NMI interrupt will initiate
the normal NMI interrupt response sequence independent of the state of IEFl.
HALT timing is shown in Fig. 2.4.1.

23

HALT op-code fetch cycle _I_

Ao - A 18

HALT op-code address

HALT

TIR
ME
RD

Interrupt

HALT mode

_I_ acknowledge cycle

X'-___H_A_L_T_o_p_-c_od_e_a_d_d_re_ss_+_1_ _ _ __

/
\

\
\

/

I
I

/
/

\ \ -_ _ _ _ _ _- J

/

\ \ -_ _ _ _ _ _- J

\
\

Figure 2.4.1 HALT Timing
2.4.2 SLEEP mode

SLEEP mode is entered by execution of the 2 byte SLP instruction. SLEEP
mode has the following characteristics.
(1) The internal CPU clock stops, reducing power consumption.
(2) The internal crystal oscillator does not stop.
(3) Internal and external interrupt inputs can be received.
(4) DRAM refresh cycles stop.
(5) I/O operations using on-chip peripherals continue.
(6) The internal DMAC stop.
(7) BUSREQ can be received and acknowledged.
(8) Address outputs go HIGH and all other control signal output become inactive
HIGH.
(9) Data Bus, 3-state.
SLEEP mode is exited in one of two ways as shown below.
RESET Exit from SLEEP mode

If the RESET input is held LOW for at least six clock cycles, the HD64180 will
exit SLEEP mode and begin the normal RESET sequence with execution starting at
address (logical and physical) OOOOOH.
Interrupt Exit from SLEEP mode

The SLEEP mode is exited by detection of an external (NMI, INTo-INT2) or internal (ASCI, CSI/O, PRT) interrupt.
In the case of NMI, SLEEP Mode is exited and the CPU begins the normal
NMI interrupt response sequence.
In the case of all other interrupts, the interrupt response depends on the state of
24

the global interrupt enable flag (IEFl) and the individual interrupt source enable bit.
If the individual interrupt condition is disabled by the corresponding enable bit,
occurrence of that interrupt is ignored and the CPU remains in the SLEEP state.
Assuming the individual interrupt condition is enabled, the response to that interrupt depends on the global interrupt enable flag (IEFl). If interrupts are globally
enabled (IEFl= 1) and an individually enabled interrupt occurs, SLEEP mode is exited and the appropriate normal interrupt response sequence is executed.
If interrupts are globally disabled (IEFI = 0) and an individually enabled interrupt occurs, SLEEP mode is exited and instruction execution begins with the instruction following the SLP instruction. Note that this provides a technique for synchronization with high speed external events without incurring the latency imposed
by an interrupt response sequence.
Fig. 2.4.2 shows SLEEP timing.
SlP 2nd op-code
fetch cycle

Op-code fetch or interrupt
acknowledge cycle

SLEEP mode

INTj,NMI --------------------~'--I

Ao-A 18 SlP 2nd op-code address X'-__7_F_F_FF_H___

X'-_____

-----J

\~

_____--J!

__--J!

\\-----Figure 2.4.2 SLEEP Timing

2.4.3 IOSTOP mode

IOSTOP mode is entered by setting the 10STP bit of the I/O Control Register
(ICR) to 1. In this case, on-chip 110 (ASCI, CSIIO, PRT) stops operating. However, the CPU continues to operate. Recovery from 10STOP mode is by resetting
the IOSTP bit in ICR to O.
2.4.4 SYSTEM STOP mode

SYSTEM STOP mode is the combination of SLEEP and 10STOP modes. SYSTEM STOP mode is entered by setting the 10STP bit in ICR to 1 followed by execution of the SLP instruction. In this mode, on-chip I/O and CPU stop operating,
reducing power consumption. Recovery from SYSTEM STOP mode is the same as
recovery from SLEEP mode, noting that internal I/O sources (disabled by 10STOP)
cannot generate a recovery interrupt.
25

2.5 Internal I/O Registers
The HD64180 internal 110 Registers occupy 64 I/O addresses (including reserved addresses). These registers access the internal 110 modules (ASCI, CSIIO,
PRT) and control functions (DMAC, DRAM refresh, interrupts, wait state generator, MMU and I/O relocation).
To avoid address conflicts with external 110, the HD64180 internal 110 addresses can be relocated on 64 bytes boundaries within the bottom 256 bytes of the
64k bytes 110 address space.
I/O Control Register nCR)

ICR allows relocating of the internal I/O addresses. ICR also controls enabling!
disabling of the 10STOP mode.
I/O Control Register OCR : I/O Address
bit

o

7

6

5

IOA7

IOA6

IOSTP

RIW

RIW

RIW

4

3

= 3FH)

o

2

IOA7,6: I/O Address Relocation (bits 7;6)

lOA 7 and IOA6 relocate internal I/O as shown in Fig. 2.5.1. Note that the highorder 8 bits of 16-bit internal I/O addresses are always O. lOA 7 and IOA6 are
cleared to 0 during RESET.

OOFFH
IOA7 • IOA6= 1 1
l:I--------1

OOCOH
OOBFH

IOA7 ·IOA6= 1 0
l:I--------I

OOSOH
007FH

~_ _ _ _--I

0040H
003FH

IOA7 ·IOA6=O 1

IOA7 ·IOA6=O 0
\1...-_ _ _ _---1

OOOOH

Figure 2.5.1 Internal I/O Address Relocation

26

o

10STP: 10STOP Mode (bit 5)

IOSTOP mode is enabled when IOSTP is set to 1. Normal I/O operation resumes when 10STP is reset to O. 10STP is cleared to 0 during RESET.
Internal I/O Registers Address Map

The internal I/O register addresses are shown in Table 2.5.1. These addresses
are relative to the 64 bytes boundary base address specified in ICR.
Table 2.5.1 Internal I/O Register Address Map (1)

Mnemonic

Register

ASCI

CSI/O

Address
Binary

Hexadecimal
OOH

ASCI Control Register A Ch 0

CNTLAO

XXOOOOOO

ASCI Control Register A Ch 1

CNTLAl

XXOOOOOl

01H

ASCI Control Register B Ch 0

CNTLBO

XXOOOO10

02H

ASCI Control Register B Ch 1

CNTLBl

XXOOOOll

03H

ASCI Status Register Ch 0

STATO

XXOO0100

04H

ASCI Status Register Ch 1

STAT 1

XXOO010l

05H

ASCI Transmit Data Register Ch 0

TDRO

XXOO0110

06H

ASCI Transmit Data Register Ch 1

TDRl

XXOOOlll

07H

ASCI Receive Data Register Ch 0

RDRO

XXOO1000

OSH

ASCI Receive Data Register Ch 1

RDRl

XXOO1001

09H

CSI/O Control Register

CNTR

XXOO1010

OAH

CSI/O Transmit/Receive Data Register

TRDR

XXOO1011

OBH

Timer Data Register Ch OL

TMDROL

XXOO1100

OCH

Timer Data Register Ch OH

TMDROH

XXOO1101

ODH

Reload Register Ch OL

RLDROL

XXOO1110

OEH

Reload Register Ch OH

RLDROH

XXOO1111

OFH

Timer Control Register

TCR

XX010000

10H

XX01000l

11 H

Reserved
Timer

~

~

XX010011

13H

Timer Data Register Ch 1 L

TMDR1L

XX010100

14H

Timer Data Register Ch 1H

TMDR1H

XX010101

15H

Reload Register Ch 1L

RLDRl L

XX010ll0

16H

Reload Register Ch 1 H

RLDR1H

XX010111

17H

Free Running Counter

FRC

XX011000

lSH

XX011001

19H

Reserved
Others

27

~

~

XX011111

lFH

Table 2.5.1 Internal I/O Register Address Map (2)

Register

DMA

Mnemonic

Hexadecimal

DMA Source Address Register Ch OL

SAROL

XX100000

20H

DMA Source Address Register Ch OH

SAROH

XX100001

21H

DMA Source Address Register Ch OB

SAROB

XX100010

22H

DMA Destination Address Register Ch OL

DAROL

XX100011

23H

DMA Destination Address Register Ch OH

DAROH

XX100100

24H

DMA Destination Address Register Ch OB

DAROB

XX100101

25H

DMA Byte Count Register Ch OL

BCROL

XX100110

26H

DMA Byte Count Register Ch OH

BCROH

XX100111

27H

DMA Memory Address Register Ch 1L

MAR1L

XX101000

28H

DMA Memory Address Register Ch 1H

MAR1H

XX101001

29H

DMA Memory Address Register Ch 1B

MAR1B

XX101010

2AH

DMA I/O Address Register Ch 1L

IAR1L

XX101011

2BH

DMA I/O Address Register Ch 1H

IAR1H

XX101100

2CH

XX101101

2DH

Reserved

INT

Address
Binary

DMA Byte Count Register Ch 1L

BCR1L

XX101110

2EH

DMA Byte Count Register Ch 1H

BCR1H

XX101111

2FH

DMA Status Register

DSTAT

XX110000

30H

DMA Mode Register

DMODE

XX110001

31H

DMAIWAIT Control Register

DCNTL

XX110010

32H

IL Register (Interrupt Vector Low Register)

IL

XX110011

33H

INT/TRAP Control Register

ITC

XX110100

34H

XX110101

35H

Reserved

28

Table 2.5.1 Internal I/O Register Address Map (3)

Register

Refresh

MMU

Mnemonic

Refresh Control Register

RCR

Reserved

Address
Binary

Hexadecimal

XX110110

36H

XX110111

37H

MMU Common Base Register

CBR

XX111000

38H

MMU Bank Base Register

BBR

XX111001

39H

MMU Common/Bank Area Register

CBAR

XX111010

3AH

XX111011

3BH

Reserved
I/O
I/O Control Register

ICR

)

)

XX111110

3EH

XX111111

3FH

I/O ADDRESSING NOTES

The internal I/O register addresses are located in the I/O address space from
OOOOH to OOFFH 06-bit I/O addresses). Thus, to access the internal I/O registers
(using I/O instructions), the high-order 8 bits of the 16-bit I/O address must be O.
The conventional I/O instructions (OUT (m),A/ IN A,(m) / OUTI / INI/ etc.)
place the contents of a CPU register on the high-order 8 bits of the address bus, and
thus may be difficult to use for accessing internal I/O registers.
For efficient internal I/O register access, a number of new instructions have
been added, which force the high-order 8 bits of the 16-bit I/O address to O. These
instructions are INO, OUTO, OTIM, OTIMR, OTDM, OTDMR and TSTIO (See
section 3.1 Instruction Set).
Note that when writing to an internal I/O register, the same I/O write occurs on
the external bus. However, the duplicate external I/O write cycle will exhibit internal
I/O write cycle timing. For example, the WAIT input and programmable wait state
generator are ignored. Similarly, internal I/O read cycles also cause a duplicate external I/O read cycle - however, the external read data is ignored by the HD64180.
Normally, external I/O addresses should be chosen to avoid overlap with internal I/O addresses to avoid duplicate I/O accesses.

29

2.6 Memory Management Unit (MMU)
The HD64180 contains an on-chip MMU which performs the translation of the
CPU 64k bytes (16-bit addresses- OOOOH to FFFFH) logical memory address space
into a 512k bytes (19-bit addresses- OOOOOH to 7FFFFH) physical memory address
space. Address translation occurs internally in parallel with other CPU operation.
2.6.1 Logical address spaces

The 64k bytes CPU logical address space is interpreted by the MMU as consisting of up to three separate logical address areas, Common Area 0, Bank Area and
Common Area 1.
As shown in Fig. 2.6.1 a variety of logical memory configurations are possible.
The boundaries between the Common and Bank Areas can be programmed with 4k
bytes resolution.
Common Area 1

Common Area 1

Common Area 1
Common Area 1

Bank Area
Bank Area

Common Area 0

Common Area 0

Figure 2.6.1 Logical Address Mapping Examples
2.6.2 Logical to physical address translation

Fig. 2.6.2 shows an example in which the three logical address space portions are
mapped into a 512k bytes physical address space. The important points to note are
that Common and Bank Areas can overlap and that Common Area 1 and Bank
Area can be freely relocated (on 4k bytes physical address boundaries). Common
Area 0 (if it exists) is always based at physical address OOOOOH.
,.....-----,7FFFFH

z
FFFFH r__------,
Common Area 1
Bank Area
Common Area 0

OOOOH '--_ _ _L-J,.I...I

v
o

Logical Address Space

x

L - - _........._ _ _- - - '

OOOOOH

Physical Address Space

Figure 2.6.2 Logical--' Physical Memory Mapping Example

30

2.6.3 MMU block diagram

The MMU block diagram is shown in Fig. 2.6.3. The MMU translates internal
16-bit logical addresses to external 19-bit physical addresses.
Internal Address/Data Bus

Memory
anagement Unit

MMU Common Base
Register; CBR (7)
MMU Bank Base
Register; BBR (7)

7
PA12-PA18
LA: Logical Address
PA: Physical Address

Figure 2.6.3 MMU Block Diagram

Whether address translation takes place depends on the type of CPU cycle as
follows.
(1) Memory Cycles
Address Translation occurs for all memory access cycles including instruction
and operand fetches, memory data reads and writes, hardware interrupt vector fetch
and software interrupt restarts.
(2) 110 Cycles
The MMU is logically bypassed for I/O cycles. The 16-bit logical I/O address
space corresponds directly with the 16 bit physical I/O address space. The three high
order bits (Al6-AlB) of the physical address are always 0 during 110 cycles.
LAo

LA15

P~O

"000"
PA18

PA,. ;A15

I

Logical Address

Physical Address

Figure 2.6.4 I/O Address Translation

(3) DMA Cycles
When the HD64180 on-chip DMAC is using the external bus, the MMU is
physically bypassed. The 19-bit source and destination registers in the DMAC are directly output on the physical address bus (Ao-AlB).

31

2.6.4 MMU registers

Three MMU registers are used to program a specific configuration of logical and
physical memory.
(1) MMU Common/Bank Area Register (CBAR)
(2) MMU Common Base Register (CBR)
(3) MMU Bank Base Register (BBR)
CBAR is used to define the logical memory organization, while CBR and BBR
are used to relocate logical areas within the 512k bytes physical address space. The
resolution for both setting boundaries within the logical space and relocation within
the physical space is 4k bytes.
The CAR field of CBAR determines the start address of Common Area 1 (Upper Common) and by default, the end address of the Bank Area. The BAR field determines the start address of the Bank Area and by default, the end address of
Common Area 0 (Lower Common).
The CA and BA fields of CBAR may be freely programmed subject only to the
restriction that CA may never be less than BA. Fig. 2.6.5 and Fig. 2.6.6 shows example of logical memory organizations associated with different values of CA and
BA.

2
Common Area 1

3

Common Area 1

4

Common Area 1
Common Area 1

Bank Area
Common Area 0

Bank Area
Common Area 0

Common Area 1
Lower limit address

>

Common Area 1
Lower limit address

Common Area 1
Lower limit address

=

>

>
Bank Area
Lower limit address

OOOOH

Common Area 1
Lower limit address
Bank Area
Lower limit address

Bank Area
Lower limit address

=

=
Bank Area
Lower limit address

>

OOOOH

OOOOH

(RESET condition)

Figure 2.6.5 Logical Memory Organization

32

=

OOOOH

FFFFH
MMU Common/Bank Area Register

11 11 1011 I

Common Area 1

0 - - - - ~~~~~

~-----1

07060504

Bank Area
MMU Common/Bank Area Register

10 11 1010 I

4 - -..... ~~.~~~

03 0201 Do

t------'"'""""
Common Area 0

OoaOH '----_ _ _---'
Figure 2.6.6 Logical Space Configuration (Example)

MMU REGISTER DESCRIPTION
MMU Common/Bank Area Register (CBAR)

CBAR specifies boundaries within the HD64180 64k bytes logical address space
for up to three areas, Common Area 0, Bank Area and Common Area 1.
MMU Common/Bank Area Register (CBAR : I/O Address = 3AH)
bit

o

o

7

6

5

4

3

2

CA3

CA2

CA1

CAO

BA3

BA2

BA1

BAO

R/W

RIW

RIW

RIW

RIW

RIW

RIW

RIW

CA3-CAO: CA (bits 7-4)

CA specifies the start (low) address (on 4k bytes boundaries) for the Common
Area 1. This also determines the last address of the Bank Area. All bits of CA are
set to 1 during RESET.

o

BA3-BAO: BA (bits 3-0)

BA specifies the start (low) address (on 4k bytes boundaries) for the Bank Area.
This also determines the last address of the Common Area O. All bits of BA are reset to 0 during RESET.
M M U Common Base Register (CBR)

CBR specifies the base address (on 4k bytes boundaries) used to generate a 19bit physical address for Common Area 1 accesses. All bits of CBR are reset to 0
during RESET.
33

MMU Common Base Register (CBR : 1/0 Address
bit

7

= 38H)

o

6

5

4

3

2

CB6

CB5

CB4

CB3

CB2

CB1

CBO

RIW

RIW

RIW

RIW

RIW

RIW

RIW

MMU Bank Base Register (BBR)

BBR specifies the base address (on 4k bytes boundaries) used to generate a 19bit physical address for Bank Area accesses. All bits of BBR are reset to 0 during
RESET.
MMU Bank Base Register (BBR : 1/0 Address = 39H)
bit

7

o

6

5

4

3

2

BB6

BB5

BB4

BB3

BB2

BB1

BBO

R/W

RIW

RIW

RIW

R/W

RIW

RIW

2.6.5 Physical address translation

Fig. 2.6.7 shows the way in which physical addresses are generated based on the
contents of CBAR, CBR and BBR. MMU comparators classify an access by logical
area as defined by CBAR. Depending on which of the three potential logical areas
(Common Area 1, Bank Area or Common Area 0) is being accessed, the appropriate 7-bit base address is added to the high-order 4 bits of the logical address, yielding a 19-bit physical address. CBR is associated with Common Area 1 accesses.
Common Area 0 accesses use a (non-accessible, internal) base register which contains O. Thus, Common Area 0, if defined, is always based at physical address
OOOOOH.

34

o

1211

15

r-----r---------~ Logical

Address

---r_ _--' (64k)

1 . . . - _ . , - - - - - - l L . . . - -_ _ _ _ _

Comparator 1-4_ _ _ _ _-1

MMU Common Base Reg. .------........

MMU Bank Base Reg.

7

4

7
18

12 11

o

i----~--___T------......I....-~ Physical

Address
1...-_ _ _ _ _- - ' -_ _ _ _ _ _ _ _- - '

(512k)

Figure 2.6.7 Physical Address Generation
2.6.6 MMU and RESET

During RESET, all bits of the CA field of CBAR are set to 1 while all bits of
the BA field of CBAR, CBR and BBR are reset to O. The logical 64k bytes address
space corresponds directly with the first 64k bytes (OOOOH to FFFFH) of the 512k
bytes (OOOOOH to 7FFFFH) physical address space. Thus, after RESET, the
HD64180 will begin execution at logical and physical address O.
2.6.7 MMU register access timing

When data is written into CBAR, CBR or BBR, the value will be effective from
the cycle immediately following the 110 write cycle which updates these registers.
Care must be taken during MMU programming to insure that CPU program execution is not disrupted. Observe that the next cycle following MMU register programming will normally be an op-code fetch from the newly translated address. One
simple technique is to localize all MMU programming routines in a Common Area
that is always enabled.

35

2.7 Interrupts
The HD64180 CPU has twelve interrupt sources, (our external and eight internal, with fixed priority.
Higher
Priority

Lower
Priority

(1 )
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)

(11 )
(12)

TRAP (Undefined Op-code Trap) .......................... . Internal Interrupt
}
NMI (Non Maskable Interrupt)
INT 0 (Maskable Interrupt Level 0)
External Interrupt
TNT1 (Maskable Interrupt Level 1)
INT 2 (Maskable Interrupt Level 2)
Timer 0
Timer 1
DMA channel 0
DMA channel 1
Internal Interrupt
Clocked Serial I/O Port
Asynchronous SCI channel 0
Asynchronous SCI channel 1

Figure 2.7.1 Interrupt Sources

This section explains the CPU registers associated with interrupt processing, the
TRAP interrupt, interrupt response modes and the external interrupts. The detailed
discussion of internal interrupt generation (except TRAP) is presented in the appropriate hardware section (Le. PRT, DMAC, ASCI and CSI/O).
2.7.1 Interrupt control registers and flags

The HD64180 contains three registers
interrupt processing.
Name
Function
I
(1) Interrupt Vector High
IL
(2) Interrupt Vector Low
(3) Interrupt/Trap Control
ITC
(4) Interrupt Enable Flag 1,2 IEFI,IEF2

Interrupt Vector Register

and two flags which are associated with
Access Method
LD A, I and LD I, A instructions
1/0 instruction (addr= 33H)
1/0 instruction (addr=34H)
EI and DI
LD A, I
LD A, R instructions

m

Mode 2 for INTo external interrupt, INTI and INT2 external interrupts and all
internal interrupts (except TRAP) use a programmable vectored technique to determine the address at which interrupt processing starts. In response to the interrupt a
16-bit address is generated. This address accesses a vector table in memory to obtain
the address at which execution restarts.
While the method for generation of the least significant byte of the table address
differs, all vectored interrupts use the contents of I as the most significant byte of
the table address. By programming the contents of I, vector tables can be relocated
36

on 256 bytes boundaries throughout the 64k bytes logical address space.
Note that I is read/written with the LD A, I and LD I, A instructions rather
than 110 (IN, OUT) instructions.
I is initialized to OOH during RESET.
Interrupt Vector Low Register (lL)
Interrupt Vector Low Register (lL : I/O Address = 33H)
b~

7

6

5

IL7

IL6

IL5

RIW

RIW

RIW

4

3

2

0

~----~v~----~'

~------------~v~------------~

Programmable

Interrupt Source Dependent Code

This register determines the most significant three bits of the low-order byte of
the interrupt vector table address for external interrupts INTl and INT2 and all internal interrupts (except TRAP). The five least significant bits are fixed for each
specific interrupt source. By programming IL the vector table can be relocated on 32
bytes boundaries.
IL is initialized to OOH during RESET.
INT/TRAP Control Register UTC)
INT/TRAP Control Register UTC : I/O Address = 34H)
bit

5

4

o

7

6

TRAP

UFO

ITE2

ITEl

ITEO

RIW

R

RIW

R/W

RIW

3

2

ITC is used to handle TRAP interrupts and to enable or disable the external
maskable interrupt inputs INTo, INTl and INT2.

o

TRAP (bit 7)

This bit is set to 1 when an undefined op-code is fetched. TRAP can be reset
under program control by writing it with 0, however it cannot be written with 1
under program control. TRAP is reset to 0 during RESET.

o

UFO: Undefined Fetch Object (bit 6)

When a TRAP interrupt occurs (TRAP bit is set to 1), the contents of UFO
allow determination of the starting address of the undefined instruction. This is necessary since the TRAP may occur on either the second or third byte of the op-code.
UFO allows the stacked PC value (stacked in response to TRAP) to be correctly adjusted. If UFO = 0, the first op-code should be interpreted as the stacked PC -1. If
UFO = 1, the first op-code address is stacked PC-2. UFO is read-only.
37

o

ITE2,1 ,0: Interrupt Enable 2,1,0 (bits 2-0)

ITE2, ITEI and ITEO enable and disable the external interrupt inputs INT2,
INTI and INFo respectively. If reset to 0, the interrupt is masked. During RESET,
ITEO is initialized to 1 while ITEI and ITE2 are initialized to O.
Interrupt Enable Flag 1,2 (lEF 1, IEF 2)

IEFI controls the overall enabling and disabling of all internal and external
maskable interrupts (Le. all interrupts except NMI and TRAP).
If IEFI = 0, all maskable interrupts are disabled. IEFI can be reset to 0 by the
DI (Disable Interrupts) instruction and set to 1 by the EI (Enable Interrupts) instruction.
The purpose of IEF2 is to correctly manage the occurrence of NMI. During
NMI, the prior interrupt reception state is saved and all maskable interrupts are automatically disabled (lEFI copied to IEF2 and then IEFI cleared to 0). At the end of
the NMI interrupt service routine, execution of the RETN (Return from Nonmaskable Interrupt) will automatically restore the interrupt receiving state (by copying IEF2 to IEFI) prior to the occurrence of NMI.
IEF2 state can be reflected in the P/V bit of the CPU Status register by executing LD A, I or LD A, R instructions.
Table 2.7.1 shows the state of IEFI and IEF2.
Table 2.7.1 State of IEF1 and IEF2
CPU Operation
RESET

IEFl

IEF2

0

0

Inhibits the interrupt except NMI and
TRAP.
Copies the contents of IEFl to IEF2.

REMARKS

0

IEFl

IEF2

not affected

Retums from the NMI service routine.

0

0

Inhibits the interrupt except NMI and
TRAP.

RETI

not affected

not affected

TRAP

not affected

not affected

1

1

NMI
RETN
Interrupt except
NMI and TRAP

EI

0

0

LO A,I

not affected

not affected

Transfers the contents of IEF2 to PN
flag.

LD A, R

not affected

not affected

Transfers the contents of IEF 2 to PIV
flag.

01

2.7.2 TRAP interrupt

The HD64180 generates a non-maskable (not affected by the state of IEFI)
TRAP interrupt when an undefined op-code fetch occurs. This feature can be used
to increase software reliability, implement an 'extended' instruction set, or both.
TRAP may occur during op-code fetch cycles and also if an undefined op-code is
38

fetched during the interrupt acknowledge cycle for INTO' when Mode 0 is used.
When a TRAP interrupt occurs the HD64180 operates as follows.
(1) The TRAP bit in the Interrupt TRAP/Control (ITC) register is set to 1.
(2) The current PC (Program Counter) value, reflecting the location of the
undefined op-code, is saved on the stack.
(3) The HD64180 vectors to logical address O. Note that if logical address OOOOH is
mapped to physical address OOOOOH, the vector is the same as for RESET. In
this case, testing the TRAP bit in ITC will reveal whether the restart at physical
address OOOOOH was caused by RESET or TRAP.
The state of the UFO (Undefined Fetch Object) bit in IrC allows TRAP
manipulation software to correctly 'adjust' the stacked PC depending on whether
the second or third byte of the op-code generated the TRAP. If UFO = 0, the starting address of the invalid instruction is equal to the stacked PC - 1. If UFO = 1,
the starting address of the invalid instruction is equal to the stacked PC - 2. Fig.
2.7.2 shows TRAP Timing.
Note that Bus Release cycle, Refresh cycle, DMA cycle and WAIT cycle can't
be inserted just after TTP state which is inserted for TRAP interrupt sequence.

39

Restart from OOOOH
2nd op-code

I" fetch cycle
T1

T2

T3

"l

Op-code
fetch cycle

PC stacking

TP

Ti

Ti

Ti

Ti

T1

T2

T3 IT1

T2

cP
Ao-A18

PC

00-07
~

o

lIR

ME

1m
WR

Figure 2.7.2 (a) TRAP Timing - 2nd Op-code Undefined

T3

T1

T2

T3

~estart

I'
cp

T1

3rd op-code

fetch cycle

T2

T3

"I'

Memory read cycle

T1

T2

TTP

T3

'1

from OOOOH
Op-code
fetch cycle

PC stacking

Tj

Ti

Ti

Ti

T1

T2

T3

IT1

T2

Ao - A 18 -----f'
~

PC-1H

00-07
LlR

ME
RO
WR

Figure 2.7.2fb) TRAP Timing -

3rd Op-code Undefined

T3

T1

T2

T3

2.7.3 External interrupts

The HD64180 has four external hardware interrupt inputs.
(1) NMI - Non-maskable Interrupt
(2) INTo - Maskable Interrupt Level 0
(3) INTI - Maskable Interrupt Levell
(4) INT2 - Maskable Interrupt Level 2
NMI, INTI and INT2 have fixed interrupt response modes. INTo has three different software programmable interrupt response modes - Mode 0, Mode 1 and
Mode 2.
2.7.4 NMI -

Non-Maskable Interrupt

The NMI interrupt input is edge sensitive and cannot be masked by software.
When NMI is detected, the HD64180 operates as follows.
(1) DMAC operation is suspended by the clearing of the DME (DMA Main Enable) bit in DCNTL.
(2) The PC is pushed onto the stack.
(3) The contents of IEFI are copied to IEF2. This saves the interrupt reception state
that existed prior to NMI.
(4) IEFI is cleared to O. This disables all external and internal maskable interrupts
(i.e. all interrupts except NMI and TRAP).
(5) Execution commences at logical address 0066H.
The last instruction of an NMI service routine should be RETN (Return from
Non-maskable Interrupt). This restores the stacked PC, allowing the interrupted
program to continue. Furthermore, RETN causes IEF2 to be copied to IEFI, restoring the interrupt reception state that existed prior to the NMI.
Note that NMI, since it can be accepted during HD64180 on-chip DMAC operation, can be used to externally interrupt DMA transfer. The NMI service routine
can reactivate or abort the DMAC operation as required by the application.
For NMI, special care must be taken to insure that interrupt inputs do not
'overrun' the NMI service routine. Unlimited NMI inputs without a corresponding
number of RETN instructions will eventually cause stack overflow.
Fig. 2.7.3 shows the use of NMI and RETN while Fig. 2.7.4 details NMI response timing. NMI is edge sensitive and the internally latched NIVI1 falling edge is
held until it is sampled. If the falling edge of NMl is latched before the falling edge
.
main

program~

IEF,
0
PCH
PCl

-IEF2
-IEF,
-(SP-1)
-(SP-2)

NMI
NMI-

Interrupt service
program

IfII Wc.. :'(~~

PCH -(SP+ 1)

Figure 2.7.3 NMI Sequence
42

RETN

of clock state prior to T3 or Ti in the last machine cycle, the internally latched N'MI
is sampled at the falling edge of the clock state prior to T3 or Ti in the last machine
cycle and NMI acknowledge cycle begins at the end of the current machine cycle.

Last MC

NMI acknowledge cycle

T 1 T 2 T3

Ao-A18

PC is pushed onto stack Restart from 0066H
I
Op-code fetch
Ti Ti T 1 T 2 T 3 T 1 T 2 T 3 T 1 T 2 T 3 I

______~x~___P_C____~X

SP-1

X SP-2 X 0066H

x==

Instruction

(

00-07

PCH

)-(

PCL

>-0

Figure 2.7.4 NMI Timing
2.7.5 INTo - Maskable Interrupt Level 0

The next highest priority external interrupt after NMI is INTo. INTo is sampled
at the falling edge of the clock state prior to T3 or Ti in the last machine cycle. If
INTo is asserted LOW at the falling edge of the clock state prior to T3 or Ti in the
last machine cycle, INTo is accepted. The interrupt is masked if either the IEF 1 flag
or the ITEO (Interrupt Enable 0) bit in ITC are reset to O. Note that after RESET
the state is as follows.
(1) IEFI is 0, so INTo is masked.
(2) ITEO is 1, so INTo is enabled by execution of the EI (Enable Interrupts) instruction.
The INTo interrupt is unique in that three programmable interrupt response
modes are available - Mode 0, Mode 1 and Mode 2. The specific mode is selected
with the 1M 0, 1M 1 and 1M 2 (Set Interrupt Mode) instructions. During RESET,
the HD64180 is initialized to use Mode 0 for INTo.
The three interrupt response modes for INTo are ...
(1) Mode 0 - Instruction fetch from data bus.
(2) Mode 1 - Restart at logical address 0038H.
(3) Mode 2 - Low byte vector table address fetch from data bus.

43

o

INTo Mode 0

During the interrupt acknowledge cycle, an instruction is fetched from the data
bus (Do-D7) at the rising edge of Ta. Often, this instruction is one of the eight single
byte RST (RESTART) instructions which stack the PC and restart execution at a
fixed logical address. However, multibyte instructions can be processed if the interrupt acknowledging device can provide a multibyte response. Unlike all other interrupts, the PC is not automatically stacked.
Note that TRAP interrupt will occur if an invalid instruction is fetched during
Mode 0 interrupt acknowledge.
Fig. 2.7.5 shows INTo Mode 0 Timing.

Last MC

,IN,To acknowledge CYCle,
wi

RST instruction execution

•••

I_
Tl

T2 Tw· Tw· T3

Ti

Ti

PC is pushed onto stack

Tl

WIo

_~~/____________

Ao-A18

___--.Jx. . . _____pc_____-.Jx

T2

T3

SP-1

Tl

T2

T3

~

\~ ____-JI

RST instruction

00-07

-------------<0>-----«
MC: Machine Cycle
__

PCH

• Two wait states are automatically inserted.

Figure 2.7.5 INTo Mode 0 Timing
(RST Instruction on the Data Bus)

o

INTo Mode 1

When INTo is received, the PC is stacked and instruction execution restarts at
logical address 0038H. Both lEFt and IEF2 flags are reset to 0, disabling all maskable
interrupts. The interrupt service routine should normally terminate with the EI
(Enable Interrupts) instruction followed by the RETI (Return from Interupt) instruction, so that the interrupts are reenabled. Fig. 2.7.6 shows the use of INTo
(Mode 1) and RETI.
Fig. 2.7.7 shows INTo Mode 1 timing.

44

main
program

o

-IEF" IEF2

PCH
PCL

-(SP-1)
-(SP-2)

INT 0 (Mode 1)
Interrupt service
program

iNi'O
(Mode 1)

EI (1 RETI

IEF I, IEF2)

Figure 2.7.6 INTo Mode 1 Interrupt Sequence

last MC

Op-code fetch cycle

INT 0 acknowledge cycle

PC is pushed onto stack

Ao-A18 _ _~X\-_ _,;""PC~_---JX

SP-1

X

SP-2

X 0038H 'C...

,,--_r-

\. . .___.---J!

\~----,/\~~I\

I

\'--_. . .1

00-07

ST

------------c(

PCH

X

PCl

>---<==>----

\'--___----'1
• Two wait states are automatically inserted.

Figure 2.7.7 INTo Mode 1 Timing

45

o

INTo Mode 2

This method determines the restart address by reading the contents of a table
residing in memory. The vector table consists of up to 128 two-byte restart addresses stored in low byte, high byte order.
The vector table address is located on 256 bytes boundaries in the 64k bytes
logical address space as programmed in the 8-bit Interrupt Vector Register (I). Fig.
2.7.8 shows the INTo Mode 2 Vector acquisition.
During INTo Mode 2 acknowledge cycle, first, the low-order· 8 bits of vector is
fetched from the data bus at the rising edge of Ta and CPU acquires the 16-bit vector.
Next, the PC is stacked. Finally, the 16-bit restart address is fetched from the
vector table and execution commences at that address.
Note that external vector acquisition is indicated by LIR and IOE both LOW.
Two wait states (Tw) are automatically inserted for external vector fetch cycles.
During RESET the Interrupt Vector Register (I) is initialized to OOH and, if necessary, should be set to a different value prior to the occurrence of a Mode 2 INTo
interrupt. Fig. 2.7.9 shows INTo interrupt Mode 2 Timing.

Memory

l6-bit Vector
Interrupt Vector
Register I

a-bit on
Data Bus

1

High-order a bits
of starting address

Vector

Low-order a bits
of starting address

Vector

+

Offset

--

Figure 2.7.8 INTo Mode 2 Vector Acquisition

46

256 Bytes
Vector
Table

last MC

OP-code
fetch cycle

INT 0 acknowledge cycle
Vector lower
address read

I
-I

Interrupt manipulation
cycle

~C is pushed onto stack I
I
-I

T1 T2 Tw*Tw*T3 Ti T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3

Starting address
Ao-A18 ==X~_---=,P",:C:""-'_----JX

SP-1

X

SP-2

X Vector

'tYr-.-ec-to-r-'-+-1X

x=

L-r-

~'--_ _----J!

~
lower vector

00- 07

-------<

ST

PCH

Starting address Starting address
(lower address) (upper address)
PCl

---

,'--_ _ _......J!
* Two wait states are automatically inserted.

Figure 2.7.9 INTo Mode 2 Timing

2.7.6 INTI, INT2

The operation of external interrupts INTI and INT2 is a vector mode similar to
INTo Mode 2. The difference is that INTI and INT2 generate the low-order byte of
vector table address using the IL (Interrupt Vector Low) register rather than fetching it from the data bus. This is also the interrupt response sequence used for all internal interrupts (except TRAP).
As shown in Fig. 2.7.10 the low-order byte of vector table address is comprised
of the most significant three bits of the software programmable IL register while the
least significant five bits are a unique fixed value for each interrupt (INTI, INT2 and
internal) source.
INTI and INT2 are globally masked by IEFI = O. Each is also individually
maskable by respectively clearing the ITE1 and ITE2 (bits 1, 2) of the INT/TRAP
control register to O.
During RESET, IEFI, ITE1 and ITE2 bits are reset to O.
2.7.7 Internal

inter~pts

Internal interrupts (except TRAP) use the same vectored response mode as
INTI and INT2 (Fig. 2.7.10). Internal interrupts are globally masked by IEFI = O.
Individual internal interrupts are enabled/disabled by programming each individual
110 (PRT, DMAC, CSI/O, ASCI) control register. The lower vector of INTI, INT2
47

and internal interrupt are summarized in Table 2.7.2.

Memory

H

16-bit Vector

I I
.

IL

I

Fixed Code
. (5 bits)
.

r-

-

~?~~':tr::: :::Ss

ector + 1
Vector
[:

Low-o~er 8 bits
of starting address

32 Bytes

Vector
table

H
Figure 2.7.10 INT1,1NT2 and Internal Interrupts Vector Acquisition
Table 2.7.2 Interrupt Source and Lower Vector
Interrupt Source
INT1

Priority
Highest

Fixed Code

IL
b7

bs

b5

*

*

*

b4

b3

b2

b1

bo

0

0

0

0

0

0

0

1

0

1

0

0

INT2

*

*

*

0

PRT channel 0

*

*

*

0

0

PRT channel 1

*

*

*

0

0

1

1

0

DMA channel 0

*

*

*

0

1

0

0

0

1

0

1

0

1

1

0

0

DMA channel 1

*

*

*

0

CSI/O

*

*

*

0

*

*

*

0

1

1

1

0

*

*

*

1

0

0

0

0

ASCI channel 0
ASCI channel 1

Lowest

• Programmable

o

INTERRUPT ACKNOWLEDGE CYCLE TIMING

Fig. 2.7.11 shows interrupt acknowledge cycle timing for internal interrupts,
INTI and INT2. INTI and INT2 are sampled at the falling edge of clock state prior to
Ta or Ti in the last machine cycle. If INTI or INT2 is asserted LOW at the falling
edge of clock state prior to Ta or Ti in the last machine cycle, the interrupt request
is accepted.

48

Op-code
fetch cycle

INT 1, INT2, internal interrupt acknowledge cycle

Last/MC

PC Stacking

Vector Table Read

~

---U-INT 1, 2 ___
__.".
Ao-A18

LlR
.j:::o.

co

~

PC

~P-1

Vector+ 1

ME
IOE
RO
WR

~~-<

00-07
ST
MC: Machine Cycle.

PC H

~ ~CL
* Two wait states are automatically inserted.

Figure 2.7.11 INT 1, INT 2 and Internal Interrupts Timing

2.7.8 Interrupt sources and reset
Interrupt Vector Register

m

All bits reset to O.
Since I = 0 locates the vector tables starting at logical address OOOOH,· vectored
interrupts (INTo Mode 2, INTI, INT2 and internal interrupts) will overlap with fixed
restart interrupts like RESET (0), NMI (0066H), INTo Mode 1 (0038H) and RST
(OOOOH - 0038H). The vector table(s) can be built elsewhere in memory and located
on 256 bytes boundaries by reprogramming I with the LD I, A instruction.
IL Register

Bits 7 - 5 are reset to O.
The IL Register can be programmed to locate the vector table for INTI, INT2
and internal interrupts on 32 bytes sub-boundaries within the 256 bytes area specified by I.
IEFI, IEF2 Flags

Reset to O.
Interrupts other than NMI and TRAP are disabled.
ITC Register

IT EO set to 1. ITEl, ITE2 reset to O.
INTo can be enabled by the EI instruction, which sets IEFI = 1. To enable
INTI and INT2 also requires that the ITEI and ITE2 bits be respectively set = 1 by
writing to ITC.
I/O Control Registers

Interrupt enable bits reset to O.
All HD64180 on-chip I/O (PRT, DMAC, CSI/O, ASCI) interrupts are disabled
and can be individually enabled by writing to each 110 control register interrupt enable bit.

50

2.8 Dynamic RAM Refresh Control
The HD64180 incorporates a dynamic RAM refresh control circuit including 8bit refresh address generation and programmable refresh timing. This circuit generates asynchronous refresh cycles inserted at the programmable interval independent
of CPU program execution. For systems which don't use dynamic RAM, the refresh function can be disabled.
When the internal refresh controller determines that a refresh cycle should occur, the current instruction is interrupted at the first breakpoint between machine
cycles. The refresh cycle is inserted by placing the refresh address on Ao-A7 and the
REF output is driven LOW.
Refresh cycles may be programmed to be either two or three clock cycles in
duration by programming the REFW (Refresh Wait) bit in Refresh Control Register
(RCR). Note that the external WAIT input and the internal wait state generator are
not effective during refresh.
Fig. 2.8.1 shows the timing of a refresh cycle with a refresh wait (TRW) cycle.

MCi

Refresh signal
(Internal signal)

MCi+l

,'------X

___________ l

'I'

Refresh cycle

----.l

Refresh address

ME

'I'

____

X"-____

Ao - A 7

~

!

\ __

n

___ _

,'-_____-J!
NOTE: • If three refresh cycles are specified, TRW, is inserted.
Otherwise, TRW is not inserted.
MC: Machine Cycle

Figure 2.8.1 Refresh Timing

Refresh Control Register (RCR)

RCR specifies the interval and length of refresh cycles, as well as enabling or
disabling the refresh function.
51

Refresh Control Register (RCR: I/O Address = 36H)
bit

o

543

o

7

6

2

REFE

REFW

CYC1

CYCO

R/W

RIW

RIW

RIW

REFE: Refresh Enable (bit 7)

REFE = 0 disables the refresh controller while REFE
insertion. REFE is set to 1 during RESET.

o

REFW: Refresh Wait (bit 6)

o

CYC1, 0: Cycle Interval (bit 1, 0)

=

1 enables refresh cycle

REFW = 0 causes the refresh cycle to be two clocks in duration. REFW = 1
causes the refresh cycle to be three clocks in duration by adding a refresh wait cycle
(TRW). REFW is set to 1 during RESET.
CYCI and CYCO specify the interval (in clock cycles) between refresh cycles.
In the case of dynamic RAMs requiring 128 refresh cycles every 2 ms (or 256
cycles every 4 ms), the required refresh interval is less than or equal to 15.625 p.s.
Thus, the underlined values indicate the best refresh interval depending on CPU
clock frequency. CYCO and CYCI are cleared to 0 during RESET.
Table 2.8.1 Refresh Interval
eYC1

CYCO

0
0

0
1
0
1

1
1

Insertion
interval

10 states
20 states
40 states
80 states

Time interval

cf>: 10 MHz
(1.0
(2.0
(4.0
(8.0

#LS)*
#LS)*
#LS)*
#LS)*

8 MHz

6 MHz

(1.25 #LS)*
(2.5 #LS)*
(5.0 #LS)*
(10.0 #LS)*

1.66 #Ls
3.3 #Ls
6.6 J1-s
13.3 #Ls

4 MHz
2.5
5.0
10.0
20.0

JLs
JLs
JLs
JLS

2.5 MHz
4.0
8.0
16.0
32.0

#Ls
#Ls
#Ls
#Ls

* calculated interval

REFRESH CONTROL AND RESET

After RESET, based on the initialized value of RCR, refresh cycles will occur
with an interval of 10 clock cycles and be 3 clock cycles in duration.
DYNAMIC RAM REFRESH OPERATION NOTES

(1) Refresh cycle insertion is stopped when the CPU is in tbe following states.
(a) During RESET
(b) When the bus is released in response to BUSREQ
(c) During SLEEP mode
52

(d) During WAIT states
(2) Refresh cycles are suppressed when the bus is released in response to BUSREQ.
However, the refresh timer continues to operate. Thus, the time at which the
first refresh cycle occurs after the HD64180 re-acquires the bus depends on the
refresh timer, and has no timing relationship with the bus exchange.
(3) Refresh cycles are suppressed during SLEEP mode. If a refresh cycle is requested during SLEEP mode, the refresh cycle request is internally 'latched'
(until replaced with the next refresh request). The 'latched' refresh cycle is inserted at the end of the first machine cycle after SLEEP mode is exited. After
this initial cycle, the time at which the next refresh cycle will occur depending
on the refresh time, and has no timing relationship with the exit from SLEEP
mode.
(4) Regarding (2) and (3), the refresh address is incremented by 1 for each successful refresh cycle, not for each refresh request. Thus, independent of the number
of 'missed' refresh requests, each refresh bus cycle will use a refresh address incremented by 1 from that of the previous refresh bus cycles.

53

2.9 DMA Controller (DMAC)
The HD64180 contains a two channel DMA (Direct Memory Access) controller
which supports high speed data transfer. Both channels (channel 0 and channel 1) have
the following capabilities.
\

Memory Address Space
Memory source and destination addresses can be directly specified anywhere within
the 512k bytes physical address space using 19-bit source and destination memory addresses. In addition, 'memory transfers can arbitrarily cross 64k bytes physical address
boundaries without CPU intervention.
110 Address Space
liD source and destination addresses can be directly specified anywhere within the
64k bytes I/O address space 06-bit source and destination I/O addresses).

Transfer Length
Up to 64k bytes can be transferred based on a 16-bit byte count register.
DREQ Input
Level and edge sense DREQ input detection are selectable.
TEND Output
Used to indicate DMA completion to external devices.
Transfer Rate
Each byte transfer can occur every six clock cycles. Wait states can be inserted in
DMA cycles for slow memory or I/O devices. At the system clock (cp) = 6 MHz, the
DMA transfer rate is as high as 1.0 megabytes/second (no wait states).
Additional feature disc for DMA interrupt request by DMA END.
Each channel has the following additional specific capabilities.
Channel 0
Memory ~ memory, memory ~ I/O, memory
liD transfers
Memory address increment, decrement, no-change
Burst or cycle steal memory ~ memory transfers
DMA to and from both ASCI channels
Higher priority than DMAC channell

o
o
o
o
o

~

memory mapped

Channell
Memory ~ I/O transfer
Memory address increment, decrement

o
o

DMAC Registers
Each channel of the DMAC (channel 0, 1) has three registers specifically associated
54

with that channel.
Channel 0
SARO
DARO
BCRO

Source Address Register
Destination Address Register
Byte Count Register

Channell
MARl
IAR1
BCR1

Memory Address Register
110 Address Register
Byte Count Register

The two channels share the following three additional registers in common.
DSTAT - DMA Status Register
DMODE - DMA Mode Register
DCNTL - DMA Control Register
2.9.1 DMAC block diagram
Fig. 2.9.1 shows the HD64180 DMAC Block Diagram.
....

.....

Intemal Address/Data Bus
~

D

DMA Source Address
Register chO : SARO (19)

DMA Status
Register: DSTAT (8)

DMA Destination Address
Register chO : DARO (19)

DMA Mode
Register: DMODE (8)

DMA Byte Count
Register chO : BCRO (16)

...

D
Priority &
Request
Control

DMAIWAIT Control
Register : DCNTL (8)

1

DMA Memory Address
Register ch1 : MAR1 (19)
DMA I/O Address
Register ch1 : IAR1 (16)
DMA Byte Count
Register ch1 : BCR1 (16

D

DMA Control

I

Iincrementer/Decrementer (19) I

I - - - Bus & CPU

Control

~TENDO

TEND1
Request

~ Interrupt

Figure 2.9.1 DMAC Block Diagram

55

-

DREQo

-

DREQ1

2.9.2 DMAC register description
DMA Source Address Register Channel 0 (SARO: I/O Address = 20H to 22H)

Specifies the physical source address for channel 0 transfers. The register contains
19 bits and may specify up to S12k bytes memory addresses or up to 64k bytes I/O addresses. Channel 0 source can be memory, 110 or memory mapped I/O.
DMA Destination Address Register Channel 0 (DARO: I/O Address

= 23H to 25H)

Specifies the physical destination address for channel 0 transfers. The register contains 19 bits and may specify up to S12k bytes memory addresses or up to 64k bytes I/O
addresses. Channel 0 destination can be memory, 110 or memory mapped I/O.
DMA Byte Count Register Channel 0 (BCRO: I/O Address

= 26H to 27H)

Specifies the number of bytes to be transferred. This register contains 16 bits and
may specify up to 64k bytes transfers. When one byte is transferred, the register is decremented by one. If "n" bytes should be transferred, "n" must be stored before the
DMA operation.
DMA Memory Address Register Channel 1 (MAR1: I/O Address = 28H to 2AH)

Specifies the physical memory address for channel 1 transfers. This may be destination or source memory address.
This register contains 19 bits and may specify up to S12k bytes memory addresses.
DMA I/O Address Register Channel 1 (lAR1: I/O Address

= 2BH to 2CH)

Specifies the 110 address for channel 1 transfers. This may be destination or source
I/O address. This register contains 16 bits and may specify up to 64k bytes I/O addresses.
DMA Byte Count Register Channel 1 (BCR1: I/O Address = 2EH to 2FH)

Specifies the number of bytes to be transferred. This register contains 16 bits and
may specify up to 64k bytes transfers. When one byte is transferred, the register is decremented by one.
DMA Status Register (DSTAT)

DSTAT is used to enable and disable DMA transfer and DMA termination interrupts. DSTA T also allows determining the status of a D MA transfer i.e. completed or
in progress.
DMA Status Register (DSTAT: 1/0 Address = 30H)
bit

7

6

5

4

3

2

o

OE1

OEO

OWE1

OWEO

OlE1

OlEO

OME

RIW

RIW

W

W

RIW

RIW

R

56

o

DE1: DMA Enable Channel 1 (bit 7)

When DEI = 1 and DME = 1, channell DMA is enabled. When a DMA transfer
terminates (BCRI = 0), DEI is reset to 0 by the DMAC. When DEI = 0 and the
DMA interrupt is enabled (DIEI = 1), a DMA interrupt request is made to the CPU.
To perform a software write to DEI, DWEI should be written with 0 during the
same register write access. Writing DEI to 0 disables channell DMA, but DMA is
restartable. Writing DEI to 1 enables channell DMA and automatically sets DME
(DMA Main Enable) to 1. DEI is cleared to 0 during RESET.

o

DEO: DMA Enable Channel 0 (bit 6)

o

DWE1: DE1 Bit Write Enable (bit 5)

When DEO = 1 and DME = 1, channel 0 DMA is enabled. When a DMA transfer
terminates (BCRO = 0), DEO is reset to 0 by the DMAC. When DEO = 0 and the
DMA interrupt is enabled (DIEO = 1), a DMA interrupt request is made to the CPU.
To perform a software write to DEO, DWEO should be written with 0 during the
same register write access. Writing DEO to 0 disables channel 0 DMA. Writing DEO
to 1 enables channel 0 DMA and automatically sets DME (DMA Main Enable) to
1. DEO is cleared to 0 during RESET.

When performing any software write to DEI, DWEI should be written with 0
during the same access. DWEI write value of 0 is not held and DWEI is always
read as 1.

o

DWEO: DEO Bit Write Enable (bit 4)

When performing any software write to DEO, DWEO should be written with 0
during the same access. DWEO write value of 0 is not held and DWEO is always
read as 1.

o

DIE1: DMA Interrupt Enable Channel 1 (bit 3)

When DIEI is set to 1, the termination of channell DMA transfer (indicated
when DEI = 0) causes a CPU interrupt request to be generated. When DIEI = 0, the
channell DMA termination interrupt is disabled. DIEI is cleared to 0 during RESET.

o

DIEO: DMA Interrupt Enable Channel 0 (bit 2)

When DIEO is set to 1, the termination channel 0 of DMA transfer (indicated
when DEO = 0) causes a CPU interrupt request to be generated. When DIEO = 0, the
channel 0 D MA termination interrupt is disabled. D lEO is cleared to 0 during RESET.

o

DME: DMA Main Enable (bit 0)

A DMA operation is only enabled when its DE bit (DEO for channel 0, DEI for
channell) and the D ME bit are set to 1.
When NMI occurs, DME is reset to 0, thus disabling DMA activity during the
NMI interrupt service routine. To restart DMA, DEO and/or DEI should be written
with 1 (even if the contents are already 1). This automatically sets DME to 1, allowing DMA operations to continue. Note that DME cannot be directly written. It is
cleared to 0 by NMI or indirectly set to 1 by setting DEO and/or DEI to 1. DME is
cleared to 0 during RESET.
57

DMA Mode Register (DMODE)

DMODE is used to set the addressing and transfer mode for channel O.
DMA Mode Register (DMODE : 1/0 Address
bit

o

7

6

= 31 H)

a

5

4

3

2

DM1

DMa

SM1

SMa

MMOD

RIW

RIW

RIW

RIW

RIW

OM1, DMO: Destination Mode Channel 0 (bits 5, 4)

Specifies whether the destination for channel 0 transfers is memory, 110 or memory mapped 110 and the corresponding address modifier. D M 1 and D MO are cleared to 0
during RESET.
Table 2.9.1 Destination

o

DM1

DMa

MemorylllO

Address
Increment/Decrement

a
a
1
1

a
1
a
1

Memory
Memory
Memory
1/0

+1
-1
fixed
fixed

SM1, SMO: Source Mode Channel 0 (bits 3, 2)

Specifies whether the source for channel 0 transfers is memory, 110 or memory
mapped 1/0 and the corresponding address modifier. SM! and SMO are cleared to 0
during RESET.
Table 2.9.2 Source
SM1

SMa

MemorylllO

Address
Increment/Decrement

a
a
1
1

a
1
a
1

Memory
Memory
Memory
1/0

+1
-1
fixed
fixed

58

Table 2.9.3 shows all DMA transfer mode combinations of DMO, DMl, SMO,
SM 1. Since 110 ~ 110 transfers are not implemented, twelve combinations are
available.
Table 2.9.3 Combination of Transfer Mode
DM1

DMO

SM1

SMO

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

1
1
1
1
1
1
1
1

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

1
1
1
1
1
1
1
1

Transfer Mode
Memory-Memory
Memory-Memory
Memory--Memory
I/O-Memory
Memory-Memory
Memory-Memory
Memory--Memory
I/O-Memory
Memory-MemoryMemory-Memoryreserved
reserved
Memory-I/O
Memory-I/O
reserved
reserved

Address
Increment/Decrement
SARO+ 1, DARO+ 1
SARO- 1, DARO+ 1
SARO fixed, DARO+ 1
SARO fixed, DARO+ 1
SARO+ 1, DARO- 1
SARO- 1, DARO- 1
SARO fixed, DARO- 1
SARO fixed, DARO- 1
SARO+ 1, DARO fixed
SARO- 1, DARO fixed

SARO+ 1, DARO fixed
SARO- 1, DARO fixed

- : Includes memory mapped 1/0

o

MMOD: Memory Mode Channel 0 (bit 1)

When channel 0 is configured for memory ~ memory transfers, the external
D REQo input is not used to control the transfer timing. Instead, two automatic transfer
timing modes are selectable - burst (MMOD = 1) and cycle steal (MMOD = 0). For
burst memory ~ memory transfers, the DMAC will sieze control of the bus continuously until the DMA transfer completes (as shown by the byte count register = 0).
In cycle steal mode, the CPU is given a cycle for each DMA byte transfer cycle until the
transfer is completed.
For channel 0 DMA with I/O source or destination, the DREQo input times the
transfer and thus MMOD is ignored. MMOD is cleared to 0 during RESET.
=-=~,...-

DMA/WAIT Control Register (DCNTL)

DCNTL controls the insertion of wait states into DMAC (and CPU) accesses of
memory or I/O. Also, the DMA request mode for each DREQ (DREQo and DREQl) input is defined as level or edge sense. DCNTL also sets the DMA transfer
mode for channel l, which is limited to memory ~ I/O transfers.

59

DMAIWAIT Control Register (DCNTL : 1/0 Address
bit

o

= 32H)
o

7

6

5

4

3

2

MWI1

MWIO

IWI1

IWIO

DMS1

DMSO

DIM1

DIMO

RIW

RIW

RIW

RIW

RIW

RIW

RIW

RIW

MWI1, MWIO: Memory Wait Insertion (bits 7-6)

Specifies the number of wait states introduced into CPU or DMAC memory access
cycles. MWIl and MWIO are set to 1 during RESET. See section of Wait State Control
for details.

o

IWI1, IWIO: I/O Wait Insertion (bits 6-4)

Specifies the number of wait states introduced into CPU or DMAC I/O access cycles. IWIl and IWIO are set to 1 during RESET. See section of Wait State Control for
details.

o

DMS1, DMSO: DMA Request Sense (bits 3-2)

DMSI and DMSO specify the DMA request sense for channel 0 (DREQo) and
channell (DREQI) respectively. When reset to 0, the input is level sense. When set
to 1, the input is edge sense. DMSI and DMSO are cleared to 0 during RESET.

o

DIM1, DIMO: DMA Channel 1 I/O and Memory Mode (bits 1-0)

Specifies the source/destination and address modifier for channell memory
I/O transfer modes. 1M! and IMO are cleared to 0 during RESET.

~

Table 2.9.4 Channel 1 Transfer Mode
DIM1

DIMO

0

0

0
1
1

1
0
1

Address
Increment/Decrement

Transfer Mode

MAR1 + 1, IAR1 fixed
MAR1-1, IAR1 fixed
IAR 1 fixed, MAR 1+ 1
IAR 1 fixed, MAR 1- 1

Memory-I/O
Memory-I/O
I/O-Memory
I/O-Memory

2.9.3 DMA operation

This section discusses the three DMA operation modes for channel 0, memory
memory, memory ~ I/O and memory ~ memory mapped I/O. In
addition, the operation of channel 0 DMA with the on-chip ASCI (Asynchronous
Serial Communication Interface) as well as Channell DMA are described.
~

60

Memory ~ Memory - Channel 0

For memory ~ memory transfers, the external D REQo input is not used for
DMA transfer timing. Rather, the DMA operation is timed in one of two programmable modes - burst or cycle steal. In both modes, the DMA operation will automatically
proceed until termination as shown by byte count (BCRO) = O.
In burst mode, the DMA operation will proceed until termination. In this case, the
CPU cannot perform any program execution until the DMA operation is completed.
In cycle steal mode, the DMA and CPU operation are alternated after each DMA
byte transfer until the DMA is completed. The sequence ...
1 CPU Machine CYcle)
(
DMA Byte Transfer
... is repeated until DMA is completed. Fig. 2.9.2 shows cycle steal mode DMA timing.
~~~ious I

CPU cycle DMA cycle (transfer 1 byte) CPU cycle

II.

cycell·

-I·

_I"

DMA cycle

..JX'-__--..JX'--__--..JX'-__--..JX"",--__

Address~______

LDg.m

Read data

Write data •

DATA

Figure 2.9.2 Cycle Steal Mode DMA Timing

61

m

To initiate memory ~ memory DMA transfer for channel 0, perform the
following operations.
(1) Load the memory source and destination addresses into SARO and DARO.
(2) Specify memory ~ memory mode and address increment/decrement in the
SMO, SMl, DMO and DMl bits of DMODE.
(3) Load the number of bytes to transfer in BCRO.
(4) Specify burst or cycle steal mode in the MMOD bit of DCNTL.
(5) Program DEO = 1 (with DWEO = 0 in the same access) in DSTAT and the
DMA operation will start 1 machine cycle later. If interrupt occurs at the same
time, the DIEO bit should be set to 1.
Memory ~ I/O (Memory Mapped I/O) - Channel 0

For memory ~ 110 (and memory ~ memory mapped 110) the DREQo
input is used to time the DMA transfers. In addition, the TENDo (Transfer End) output is used to indicate the last (byte count register BCRO = OOH) transfer.
The D REQo input can be programmed as level or edge sensitive.
When level sense is programmed, the DMA operation begins when DREQo is
sampled LOW. IfDREQo is sampled HIGH, after the next DMA byte transfer, control
is relinquished to the HD64l80 CPU. As shown in Fig. 2.9.3. DREQo is sampled at the
rising edge of the clock cycle prior to Ta i.e. either T2 or Tw.
DMA Write Cycle

I~PU Machine CYCI~I ..DMA Read Cycle ..

1-

\_____________~I

I.

DMA Write Cycle (I/O)

..

I.

1-

\---.==~-----•• i5REOo is

Figure 2.9.3 CPU Operation and DMA Operation
(DREQo is programmed for level sense)

sampled at

1·

When edge sense is programmed, DMA operation begins at the falling edge of
If another falling edge is detected before the rising edge of the clock prior
to Ta during DMA write cycle (i.e. T2 or Tw), the DMAC continues operating. If an
edge is not detected, the CPU is given control after the current byte DMA transfer
completes. The CPU will continue operating until a DREQo falling edge is detected
before the rising edge of the clock prior to Ta at which time the DMA operation will
(re)start. Fig. 2.9.4 shows the edge sense DMA timing.

=DO-=R=-=E::-:::Q~o.

62

DMA write cycle

DMA write cycle

•• DREQo is sampled at

!.

Figure 2.9.4 CPU Operation and DMA Operation
(DREQo is programmed for edge sense)

During the transfers for channel 0, the TENDo output will go LOW synchronous
with the write cycle of the last (BCRO = OOH) DMA transfer as shown in Fig.

2.9.5.
Last DMA cycle (BeRO = OOH)
DMA read cycle

1

DMA write cycle

I

\\.-_____--JI
Figure 2.9.5 TENDo Output Timing

The DREQo and TENDo pins are programmably multiplexed with the CKAO and
CKAI ASCI clock input/outputs. However, when DMA channel 0 is programmed for
memory ~ 110 (and memory ~ memory mapped I/O) transfers, the CKAO/
DREQo pin automatically functions as input pin even if it has been programmed as output pin for CKAO. And the CKAI/TENDo pin functions as output pin for TENDo by
setting CKA 1D to 1 in CNTLA 1.
To initiate memory ~ I/O (and memory ~ memory mapped 110) DMA
transfer for channel 0, perform the following operations.
(1) Load the memory and 110 or memory mapped I/O source and destination addresses into SARO and DARO. Note that I/O addresses (not memory mapped I/O)
are limited to 16 bits (Ao-AIS). Make sure that bits A16, and A17 are 0 (AlB is a
don't care) to correctly enable the external DREQo input.
.
(2) Specify memory ~ 110 or memory ~ memory mapped I/O mode and
address increment/decrement in the SMO, SMI, DMO and DMI bits ofDMODE.
(3) Load the number of bytes to transfer in BCRO.
(4) Specify whether DREQo is edge or level sense by programming the DMSO bit of
DCNTL.
63

(5) Enable or disable DMA termination interrupt with the DIEO bit in DSTAT.
(6) Program DEO = 1 (with DWEO = 0 in the same access) in DSTAT and the

DMA operation will begin under the control of the DREQo input.
Memory ~ ASCI - Channel 0

Channel 0 has extra capability to support DMA transfer to and from the on-chip
two channel ASCI. In this case the external DREQo input is not used for DMA timing.
Rather, the ASCI status bits are used to generate an internal DREQo. The TDRE
(Transmit Data Register Empty) bit and the RDRF (Receive Data Register Full) bit
are used to generate an internal DREQo for ASCI transmission and reception respectively.
To initiate memory ~ ASCI D MA transfer, perform the following operations.
(1) Load the source and destination addresses into SARO and DARO. Specify the I/O
(ASCI) address as follows.
Bits Ao-A7 should be contain the address of the ASCI channel transmitter or receiver (I/O addresses 6H-9H).
Bits As-A15 should equal O.
Bits A17-A16 should be set according to the following table to enable use of the appropriate ASCI status bit as an internal DMA request.

Table 2.9.5 DMA Request
SAR18

SAR17

SAR16

DMA Transfer Request

X
X
X
X

0

0

DR"EOo

0

1

RDRF (ASCI channel
0)
f

1

0

RDRF (ASCI channel 1)

1

1

DAR18

DAR17

DAR16

X
X
X
X

0

0

DREQo

0

1

TDRE (ASCI channel 0)

1

0

TDRE (ASCI channel 1)

1

1

reserved

X: Don't care
DMA Transfer Request

reserved

X: Don't care

(2) Specify memory ~ I/O transfer mode and address increment/decrement in
the SMO, SMl, DMO and DMI bits of DMODE.
(3) Load the number of bytes to transfer in BCRO.
(4) The DMA request sense mode (DMSO bit in DCNTL) MUST be specified as 'edge
sense'.
(5) Enable or disable DMA termination interrupt with the DIEO bit in DSTAT.
64

(6) Program DEO = I (with DWEO = 0 in the same access) in DSTAT and the

DMA operation with the ASCI will begin under control of the ASCI generated
internal DMA request.
The ASCI receiver or transmitter being used for DMA must be initialized to allow
the first DMA transfer to begin.
The ASCI receiver must be 'empty' as shown by RDRF = O.
The ASCI transmitter must be 'full' as shown by TDRE = O. Thus, the first byte
should be written to the ASCI Transmit Data Register under program control. The remaining bytes will be transferred using DMA.
Channel 1 DMA

DMAC Channel I can perform memory ~ liD transfers. Except for different
registers and status/control bits, operation is exactly the same as described for channel
o memory ~ liD DMA.
To initiate DMA channel I memory ~ I/O transfer perform the following
operations.
(1) Load the memory address (19 bits) into MARl.
(2) Load the I/O address (16 bits) into IARI.
(3) Program the source/destination and address increment/decrement mode using the
DIMI and DIMO bits in DCNTL.
(4) Specify whether DREQt is level or edge sense in the DMSI bit in DCNTL.
(5) Enable or disable DMA termination interrupt with the DIEI bit in DSTAT.
(6) Program DEI = I (with DWEI = 0 in the same access) in DSTAT and the
D MA operation with the external liD device will begin using the external D REQt input and TENDl output.
2.9.4 DMA bus timing

When memory (and memory mapped liD) is specified as a source or destination,
ME goes LOW during the memory access. When I/O is specified as a source or destination, IDE goes LOW during the I/O access.
When I/O (and memory mapped I/O) is specified as a source or destination, the
DMA timing is controlled by the external DREQ input and the TEND output indicates
DMA termination. Note that external I/O devices may not overlap addresses with internal I/O and control registers, even using DMA.
For I/O accesses, I wait state is automatically inserted. Additional wait states can be
inserted by programming the on-chip wait state generator or using the external WAIT
input. Note that for memory mapped I/O accesses, this automatic lID wait state is not
inserted.
For memory to memory transfers (channel 0 only), the external DREQo input is
ignored. Automatic DMA timing is programmed as either burst or cycle steal.
When a DMA memory address carry/borrow between bits Al5 and Al6 of the
address bus occurs (when crossing 64k bytes boundaries), the minimum bus cycle is
extended to four clocks by automatic insertion of one internal Ti state.
2.9.5 DMAC channel priority

For simultaneous DREQo and DREQl requests, channel 0 has priority over /
65

channell. When channel 0 is performing a memory ~ memory transfer, channel 1 cannot operate until the channel 0 operation has terminated. If channel 1 is
operating, channel 0 cannot operate until channel 1 releases control of the bus.
2.9.6 DMAC and BUSREQ, BUSACK

The BUSREQ and BUSACK inputs allow another bus master to take control of the
HD64180 bus. BUSREQ and BUSACK have priority over the on-chip DMAC and will
suspend DMAC operation. The DMAC releases the bus to the external bus master at
the breakpoint of the DMAC memory or 110 access. Since a single byte DMAC transfer requires a read and a write cycle, it is possible for the DMAC to be suspended after
the DMAC read, but before the DMAC write. Even in this case, when the external
master releases the HD64180 bus (BUSREQ HIGH), the on-chip DMAC will correctly
continue the suspended DMA operation.
2.9.7 DMAC internal interrupts

Fig. 2.9.6 illustrates the internal DMA interrupt request generation circuit.
IEF1

DE1
DIE1

DMA ch 1 Interrupt
Request

DEO

DMA chO Interrupt
Request

OlEO

Figure 2.9.6 DMAC Interrupt Request Circuit Diagram

DEO and DEI are automatically cleared to 0 by the HD64180 at the completion
(byte count = 0) of a DMA operation for channel 0 and channell respectively. They
remain 0 until a 1 is written. Since DEO and DEI use level sense, an interrupt will occur
if the CPU IEFI flag is set to 1. Therefore, the DMA termination interrupt service
routine should disable further DMA interrupts (by programming the channel DIE bit
= 0) before enabling CPU interrupts (i.e. IEFI is set to 1). After reloading the DMAC
address and count registers, the DIE bit can be set to 1 to reenable the channel interrupt, and at the same time D MA can resume by programming the channel DEbit = 1.
2.9.8 DMAC and NMI

NMI, unlike all other interrupts, automatically disables DMAC operation by clearing the DME bit of DSTAT. Thus, the NMI interrupt service routine may respond to
time critical events without delay due to DMAC bus usage. Also, NMI can be effectively used as an external DMA abort input, recognizing that both channels are suspended by the clearing of D ME.
66

If the falling edge ofNMI occurs before the falling clock of the state prior to Ta (T2
or Tw) of the DMA write cycle, the DMAC will be suspended and the CPU will
start the NMI response at the end of the current cycle.
By setting a channels DEbit to I, that channels operation can be restarted, and
DMA will correctly resume from the point at which it was suspended by NMI. See Fig.
2.9.7 for details.

I.

DMA read cycle

I

DMA write cycle

'I'

CPU machine cycle

DME= "0" (DMA Stop)

Figure 2.9.7 NMI and DMA Operation

2.9.9 DMAC and RESET
During RESET the bits in DSTAT, DMODE and DCNTL are initialized as stated
in their individual register descriptions. Any DMA operation in progress is stopped
allowing the CPU to use the bus to perform the RESET sequence. However, the address register (SARO, DARO, MARl, IARl) and byte count register (BCRO, BCRl)
contents are not changed during RESET.

67

2.10 Asynchronous Serial Communication Interface (ASCI)
The HD64180 on-chip ASCI has two independent full duplex channels. Based
on full programmability of the following functions, the ASCI can directly communicate with a wide variety of standard UARTs (Universal Asynchronous Receiverl
Transmitter) including the HD6350 CMOS ACIA and the Serial Communication Interface (SCI) contained on the HD6301 series CMOS single chip controllers.
The key functions for ASCI are shown below. Each channel is independently
programmable.
o Full duplex communication
o 7- or 8-bit data length
o Program controlled 9th data bit for multiprocessor communication
o 1 or 2 stop bits
o Odd, even, no parity
o Parity, overrun, framing error detection
o Programmable baud rate generator, 116 and 164 modes
Speed to 38.4k bits per second (CPU fc = 6.144 MHz)
o Modem control signals - Channel 0 has DCDo, CTSo and RTSo Channell has
CTSI
o Programmable interrupt condition enable and disable
o Operation with on-chip DMAC
2.10.1 ASCI block diagram

Fig. 2.10.1 shows the ASCI Block Diagram.
...
Intemal Address/Data Bus

"

TXAo -

t
ASCI Transmit Data Register
ch 0: TORO

ASCI Transmit Data Regis~r
ch 1 : TOR1

~SCI Transmit Shift Register-

ASCI Transmit Shift Register- f-T XA,
ch 1 : TSR1

ch 0: TSRO
ASCI Receive Data Register
f-<
ch 0: RORO

.......

RXAo ... ASCI Receive Shift Registerch 0 : RSRO (8)

-RTSo-

...

1

Interrupt Request

ASCI Control Register A
ch 0 : CNTLAO (8)

--

-CTSo .... ASCI Control Register B
ch 0 : CNTLBO (8)

-0
- ...... ASCI Status Register
COo

-

ASCI Receive Data Register
ch 1 : ROR1
ASCI Receive Shift Registerch 1 : RSR1 (8)

ASCI
Control

i--

--

-AX

ASCI Control Register A
ch 1 : CNTLA 1 (8)
ASCI Control Register B
ch 1 : CNTLB 1 (8)

-

-

CTS

r-

ASCI Status Register
ch 1 : STAT1 (8)

ch 0: STATO (8)

CKAo-

Baud Rate
Generator 0

CKA,-

Baud Rate
Generator 1

~¢

-Not program Accessible

Figure 2.10.1 ASCI Block Diagram

68

,

2.10.2 ASCI register description
ASCI Transmit Shift Register 0, 1 (TSRO, 1)

When the ASCI Transmit Shift Register receives data from the ASCI Transmit
Data Register (TDR), the data is shifted out to the TXA pin. When transmission is
completed, the next byte (if available) is automatically loaded from TDR into TSR
and the next transmission starts. If no data is available for transmission, TSR idles
by outputting a continuous HIGH level. This register is not program accessible.
ASCI Transmit Data Register 0, 1 (TDRO, 1: I/O Address = 06H,07H)

Data written to the ASCI Transmit Data Register is transferred to the TSR as
soon as TSR is empty. Data can be written to while TSR is shifting out the previous
byte of data. Thus, the ASCI transmitter is double bufferred.
Data can be written into and read from the ASCI Transmit Data Register.
If data is read from the ASCI Transmit Data Register, the ASCI data transmit
operation won't be affected by this read operation.
ASCI Receive Shift Register 0, 1 (RSRO, 1)

This register receives data shifted in on the RXA pin. When full, data is automatically transferred to the ASCI Receive Data Register (RDR) if it is empty. If
RSR is not empty when the next incoming data byte is shifted in, an overrun error
occurs. This register is not program accessible.
ASCI Receive Data Register 0, 1 (RDRO, 1: I/O Address = OSH, 09H)

When a complete incoming data byte is assembled in RSR, it is automatically
transferred to the RDR if RDR is empty. The next incoming data byte can be
shifted into RSR while RDR contains the previous received data byte. Thus, the
ASCI receiver is double buffered.
The ASCI Receive Data Register is read-only-register.
However, if RDRF = 0, data can be written into the ASCI Receive Data Register, and the data can be read.
ASCI Status Register 0, 1 (STATO, 1)

Each channel status register allows interrogation of ASCI communication, error
and modem control signal status as well as enabling and disabling of ASCI interrupts.

ASCI Status Register 0 (STA TO : 1/0 Address
bit

7

6

5

4

3

RDRF

OVRN

PE

FE

RIE

R

R

R

R

RIW

69

2

R

= 04H)
1

o

TORE

TIE

R

RIW

ASCI Status Register 1 (STAT1 : 1/0 Address = 05H)
bit

o

7

6

5

4

3

RORF
R

OVRN
R

PE
R

FE
R

RIE
RIW

2

I

CTS1E

RIW

0

TORE
R

TIE
RIW

RDRF: Receive Data Register Full (bit 7)

RDRF is set to 1 when an incoming data byte is loaded into RDR. Note that if
a framing or parity error occurs, RDRF is still set and the receive data (which generated the error) is still loaded into RDR. RDRF is cleared to 0 by reading RDR,
when the DCDo input is HIGH, in IOSTOP mode and during RESET.

o

OVRN: Overrun Error (bit 6)

OVRN is set to 1 when RDR is full and RSR becomes full. OVRN is cleared to
(Error Flag Reset) of CNTLA is written to 0, when DCDo is
HIGH, in IOSTOP mode and during RESET.

o when the EFR bit

OPE: Parity Error (bit 6)

PE is set to 1 when a parity error is detected on an incoming data byte and
ASCI parity detection is enabled (the MODI bit of CNTLA is set to 1). PE is
cleared to 0 when the EFR bit (Error Flag Reset) of CNTLA is written to 0, when
DCDo is HIGH, in IOSTOP mode and during RESET.

o

FE: Framing Error (bit 4)

If a receive data byte frame is delimited by an invalid stop bit (i.e. 0, should be

1) , FE is set to 1. FE is cleared to 0 when the EFR bit (Error Flag Reset) of
CNTLA is written to 0, when DCDo is HIGH, in IOSTOP mode and during RESET.

o .RIE: Receive Interrupt Enable (bit 3)
RIE should be set to 1 to enable ASCI receive interrupt requests. When RIE to
1, if any of the flags RDRF, OVRN, PE, FE become set to 1 an interrupt request is
generated. For channel 0, an interrupt will also be generated by the transition of the
external DCDo input from LOW to HIGH. RIE is cleared to 0 during RESET.

o

DeDo: Data Carrier Detect (bit 2 STATO)

Channel 0 has an external DCDo input pin. The DCDo bit is set to 1 when the
DCDo input is HIGH. It is cleared to 0 on the first read of STATO following the
DCDo input transition from HIGH to LOW and during RESET. When DCDo = 1,
receiver unit is reset and receiver operation is inhibited.

o

CTS 1 E: Channel 1 CTS Enable (bit 2 STAT1)

Channel 1 has an external CTSI input (pin 52) which is multiplexed with the re70

ceive data pin (RXS) for the CSI/O (Clocked Serial I/O Port). Setting CTSIE to 1
selects the CTSI function and clearing CTSIE to 0 selects the RXS function.

o

TORE: Transmit Data Register Empty (bit 1)

TDRE = 1 indicates that the TDR is empty and the next transmit data byte can
be written to TDR. After the byte is written to TDR, TDRE is cleared to 0 until
the ASCI transfers the byte from the TDR to the TSR, at which time TDRE is
again set to 1. TDRE is set to 1 in 10STOP mode and during RESET. When the
external CTS input is HIGH, TDRE is reset to O.

o

TIE: Transmit Interrupt Enable (bit 0)

TIE should be set to 1 to enable ASCI transmit interrupt requests. If TIE = 1,
an interrupt will be requested when TDRE = 1. TIE is cleared to 0 during RESET.
ASCI Control Register AO, 1 (CNTLAO, 1)

Each ASCI channel Control Register A configures the major operating modes
such as receiver/transmitter enable and disable, data format, and multiprocessor
communication mode.

ASCI Control Register A 0 (CNTLAO : I/O Address = OOH)
bit

7

6

5

4

3

2
MOD2

MOD1

MODO

RIW

RIW

RIW

MPE

RE

TE

RTSo

MPBRI
EFR

RIW

RIW

R/W

R/W

RIW

0

ASCI Control Register A 1 (CNTLA 1 : I/O Address = 01 H)
bit

7

MPE
RIW

o

I

6

5

RE
RIW

TE
RIW

4

3

2

CKA1D

MPBRI
EFR

MOD2

MOD1

MODO

RIW

R/W

RIW

RIW

RIW

I

0

M PE: Multi Processor Mode Enable (bit 7)

The ASCI has a multiprocessor communication mode which utilizes an extra
data bit for selective communication when a number of processors share a common
serial bus. Multiprocessor data format is selected when the MP bit in CNTLB is set
to 1. If multiprocessor mode is not selected (MP bit in CNTLB = 0), MPE has no
effect. If multiprocessor mode is selected, MPE enables or disables the 'wake-up'
feature as follows. If MPE is set to 1, only received bytes in which the MPB (multiprocessor bit) = 1 can affect the RD RF and error flags. Effectively, other bytes
(with MPB = 0) are 'ignored' by the ASCI. If MPE is reset to 0, all bytes, regardless of the state of the MPB data bit, affect the RDRF and error flags. MPE is
71

cleared to 0 during RESET.

o

RE: Receiver Enable (bit 6)

When RE is set to 1, the ASCI receiver is enabled. When RE is reset to 0, the
receiver is disabled and any receive operation in progress is interrupted. However,
the RDRF and error flags are not reset and the previous contents of RDRF and
error flags are held. RE is cleared to 0 in IOSTOP mode and during RESET.

o

TE: Transmitter Enable (bit 5)

When TE is set to 1, the ASCI transmitter is enabled. When TE is reset to 0,
the transmitter is disabled and any transmit operation in progress is interrupted.
However, the TDRE flag is not reset and the previous contents of TDRE are held.
TE is cleared to 0 in IOSTOP mode and during RESET.

o

RTSo - Request to Send Channel 0 (bit 4 in CNTLAO)

When RTSo is reset to 0, the RTSo output pin will go LOW. When RTSo is set
to 1, the RTSo output immediately goes HIGH. RTSo is set to 1 during RESET.

o

\

CKA 1 D: CKA 1 Clock Disable (bit 4 in CNTLA 1)

When CKAID is set to 1, the multiplexed CKAI/TENDo pin (pin 50) is used
for the TENDo function. When CKAID = 0, the pin is used as CKAI, an external
data clock input/output for channell. CKAID is cleared to 0 during RESET.

o

MPBR/EFR: Multiprocessor Bit Receive/Error Flag Reset (bit 3)

When multiprocessor mode is enabled (MP in CNTLB = 1), MPBR, when
read, contains the value of the MPB bit for the last receive operation. When written
to 0, the EFR function is selected to reset all error flags (OVRN, FE and PE) to O.
MPBR/EFR is undefined during RESET.

o

MOD2, 1, 0: ASCI Data Format Mode 2, 1, 0 (bits 2-0)

These bits program the ASCI data format as follows.
MOD2
= 0 - 7 bit data
= 1 - 8 bit data
MODI
= 0 - No parity
= 1 - Parity enabled
MODO
= 0 - 1 stop bit
= 1 - 2 stop bits
The data formats available based on all combinations of MOD2, MODI and
MODO are shown in Table 2.10.1.

72

Table 2.10.1 Combination of Data Format
MOD2

MOD'

MODO

0
0
0
0

0
0

0

,
,
,
,

,,
,,

,,
,,

0

0
0

0
0

Data Format
Start
Start
Start
Start
Start
Start
Start
Start

+
+
+
+
+
+
+
+

7
7
7
7

8
8
8
8

bit
bit
bit
bit
bit
bit
bit
bit

data
data
data
data
data
data
data
data

+ , stop
+ 2 stop
+ parity + , stop
+ parity + 2 stop
+ , stop
+ 2 stop
+ parity + , stop
+ parity + 2 stop

ASCI Control Register BO, 1 (CNTLBO, 1)

Each ASCI channel control register B configures multiprocessor mode, parity
and baud rate selection.
ASCI Control Register B 0 (CNTLBO : 1/0 Address = 02H)
ASCI Control Register B 1 (CNTLB1 : 1/0 Address = 03H)
bit

7

6

MPBT

MP

RIW

R/W

o

4

3

2

PS

PEO

DR

SS2

S5'

SSO

RIW

RIW

RIW

RIW

RIW

RIW

5
CTSI

o

MPBT: Multiprocessor Bit Transmit (bit 7)

When multiprocessor communication format is selected (MP bit = 1), MPBT is
used to specify the MPB data bit for transmission. If MPBT = 1, then MPB = 1 is
transmitted. If MPBT = 0, then MPB = 0 is transmitted. MPBT state is undefined
during and after RESET.

o

M P: Multiprocessor Mode (bit 6)

When MP is set to 1, the data format is configured for multiprocessor mode
based on the MOD2 (number of data bits) and MODO (number of stop bits) bits in
CNTLA. The format is as follows.
Start bit + 7 or 8 data bits + MPB bit + 1 or 2 stop bits
Note that multiprocessor (MP = 1) format has no provision for parity. If MP
- 0, the data format is based on MODO, MODi and MOD2 and may include
parity. The MP bit is cleared to 0 during RESET.

o

CTS1PS: Clear to Send/Prescale (bit 5)

When read, CTS/PS reflects the state of the external CTS input. If the CTS
input pin is HIGH, CTS/PS will be read as 1. Note that when the CTS input pin is
HIGH, the TDRE bit is inhibited (Le. held at 0). For channel 1, the CTSI input is
multiplexed with RXS pin (Clocked Serial Receive Data). Thus, CTS/PS is only
valid when read if the channel 1 CTS1E bit = 1 and the CTSI input pin function is
73

selected. The read data of CTS/PS is not affected by RESET.
When written, CTS/PS specifies the baud rate generator prescale factor. If CTS/
PS is set to 1, the system clock (cp) is prescaled by 30 while if CTS/PS is cleared to
0, the system clock is prescaled by 10. CTS/PS is cleared to 0 during RESET.

o

PEO: Parity Even Odd (bit 4)

PEO selects even or odd parity. PEO does not affect the enabling/disabling of
parity (MOD 1 bit of CNTLA). If PEO is cleared to 0, even parity is selected. If
PEO is set to 1, odd parity is selected. PEO is cleared to 0 during RESET.

o

DR: Divide Ratio (bit 3)

DR specifies the divider used to obtain baud rate from the data sampling clock.
If DR is reset to 0, divide by 16 is used while if DR is set to 1, divide by 64 is
used. DR is cleared to 0 during RESET.

o

S52, 1, 0: Source/Speed Select 2, 1, 0 (bits 2-0)

Specify the data clock source (internal o,r external) and baud rate prescale factor.
SS2, SSI, SSO are all set to 1 during RESET. Table 2.10.2 shows the divide ratio
corresponding to SS2, SSI and SSO.
Table 2.10.2 Divide Ratio
552
0
0
0
0
1
1
1

551
0
0
1
1
0
0
1

1

1

550
0
1
0
1
0
1
0
1

Divide Ratio

+1
+2
+4
+8
+ 16
+32
+64
external clock

The external ASCI channel 0 data clock pins are multiplexed with DMA control
lines (CKAo/DREQo and CKAtlTENDo). During RESET, these pins are initialized
as ASCI data clock inputs. If SS2, SS 1 and SSO are reprogrammed (any other value
than SS2, SS 1, SSO = 1) these pins become ASCI data clock outputs. However, if
DMAC channel 0 is configured to perform memory ~ 110 (and memory mapped 110) transfers the CKAo/D REQo pin revert to D MA control signals regardless
of SS2, SSI, SSO programming. Also, if the CKAID bit in the CNTLA register is
set to 1, then the CKAtlTENDo reverts to the DMA Control output function
regardless of SS2, SS 1 and SSO programming.
Final data clock rates are based on CTS/PS (prescale), DR, SS2, SSI, SSO and
the HD64180 system clock (cp) frequency as shown in Table 2.10.3.

74

Table 2.10.3 Baud Rate List
Sampling
Rate

Prescaler
PS

Divide
Ratio

DR

0

0

0

0
0
1
1
0
0
1

SSO
0
1
0
1
0
1
0

Divide
Ratio
+1
2
4
8
16
32
64

4>+ 160
320
640
1280
2560
5120
10240

16

1

1

1

-

fc+16

64

0
0
0
0
1
1
1

0
0
1
1
0
0
1

0
1
0
1
0
1
0

+1
2
4
8
16
32
64

4>+640
1280
2560
5120
10240
20480
40960

1

1

1

-

fc+64

16

0
0
0
0
1
1
1

0
0
1
1
0
0
1

0
1
0
1
0
1
0

+1
2
4
8
16
32
64

4>+480
960
1920
3840
7680
15360
30720

1

1

1

-

fc+16

64

0
0
0
0
1
1
1

0
0
1
1
0
0
1

0
1
0
1
0
1
0

+1
2
4
8
16
32

4>+ 1920
3840
7680
15360
30720
61440
122880

1

1

1

-

4>+30

1

SS2 SSl

General
Divide
Ratio

0
0
0
0
1
1
1

4>+ 10

1

1

Rate

Baud Rate

64

fc+64

Baud Rate (Example)
(BPS)

CKA

4>=6.144

4>=4.608

4>=3.072

MHz

MHz

MHz

38400
19200
9600
4800
2400
1200
600

-

19200
9600
4800
2400
1200
600
300

-

-

9600
4800
2400
1200
600
300
150

-

4800
2400
1200
600
300
150
75

-

-

9600
4800
2400
1200
600
300
150

-

-

-

2400
1200
600
300
150
75
37.5

-

-

-

VO

0

Clock
Frequency
4>+ 10
20
40
80
160
320
640

I

fc

0

4>+ 10
20
40
80
160
320
640

I

fc

0

4>+30
60
120
240
480
960
1920

I

fc

0

4>+30
60
120
240
480
960
1920

I

fc

2.10.3 MODEM control signals

ASCI channel 0 has CTSo, DCDo and RTSo external modem control signals.
ASCI channell has a CTSI modem control signal which is multiplexed with RXS
pin (Clocked Serial Receive Data).
CTSo: Clear to Send 0 (input)

The CTSo input allows external control (start/stop) of ASCI channel 0 transmit
operations. When CTSo is HIGH, channel 0 TDRE bit is held at 0 regardless of
whether the TDRO (Transmit Data Register) is full or empty. When CTSo is LOW,
TDRE will reflect the state of TDRO. Note that the actual transmit operation is not
disabled by CTSo HIGH, only TDRE is inhibited.
DCDo: Data Carrier Detect 0 (input)

,

The DCDo input allows external control (start/stop) of ASCI channel 0 receive
operations. When DCDo is HIGH, channel 0 RDRF bit is held at 0 regardless of
75

whether the RDRO (Receive Data Register) is full or empty. The error flags (PE,
FE and OVRN bits) are also held at O. Even after the DCDo input goes LOW, these
bits will not resume normal operation until the status register (STATO) is read. Note
tJ:tat this first read of STATO, while enabling normal operation, will still indicate the
DCDo input is HIGH (DCDO bit = 1) even though it has gone LOW. Thus, the
STATO register should be read twice to insure the DCDO bit is reset to O.
RTSo: Request to Send 0 (output)

RTSo allows the ASCI to control (start/stop) another communication devices
transmission (for example, by connection to that devices CTS input). RTSo is essentially a 1 bit output port, having no side effects on other ASCI registers or flags.
CTSl: Clear to Send 1 (input)

Channel 1 CTSI input is multiplexed with the RXS pin (Clocked Serial Receive
Data). The CTSI function is selected when the CTS IE bit in STATI is set to 1.
When enabled, the CTSI operation is equivalent to CTSo.
Modem control signal timing is shown in Fig. 2.10.2 (a) and Fig. 2.10.2 (b).

DCDo Pin

Status Register _ _ _ _ _ _ _ _---' '--_ _ _ _ _ _ _ _ __
Read

Figure 2.10.2 (a) DCDo Timing
1/0 instruction

-I-

1/0 write cycle

'RTSOFlag

RTSo Pin

Figure 2.10.2 (b) RTSo Timing

76

-I

2.10.4 ASCI interrupts

Fig. 2.10.3 shows the ASCI interrupt request generation circuit.

DCDO
RDRFO-----

IEF1

OVRNO
ASCIO Interrupt
Request

PEO

FEO

RDRF1
PE1
FE1

ASCI1 Interrupt
Request

Figure 2.10.3 ASCI Interrupt Request Circuit Diagram

2.10.5 ASCI

~

DMAC operation

Operation of the ASCI with the on-chip DMAC channel 0 requires the DMAC
be correctly configured to utilize the ASCI flags as DMA request signals.
2.10.6 ASCI and RESET

During RESET, the ASCI status and control registers are initialized as defined
in the individual register descriptions.
Receive and Transmit operations are stopped during RESET. However, the contents of the transmit and receive data registers (TDR and RDR) are not changed by
RESET.
2.10.7 ASCI clock

In external clock input mode, the external clock is directly input to the sampling
rate (+ 16/+ 64) as shown in Fig. 2.10.4.

Internal Clock

Baud Rate Selection

q,~

+ 1 to + 64

H

Prescaler

+ 10/+ 30

Sampling Rate

~

+ 16/+ 64

I

External Clock
cP + 4 0 - - - - - - - - - - - - - - - - '

fc

s

Figure 2.10.4 ASCI Clock Block Diagram
77

I

2.11 Clocked Serial I/O Port (CSI/O)
The HD64180 includes a simple, high speed clock synchronous serial 110 port.
The CSI/O includes transmit/receive (half duplex), fixed 8-bit data and internal or
external data clock selection. High speed operation (baud rate as high as 200k bits/
second at fC = 4 MHz) is provided. The CSI/O is ideal for implementing a multiprocessor communication link between the HD64180 and the HMCS400 series (4bit) and the HD6301 series (8-bit) single chip controllers as well as additional
HD64180 CPUs. These secondary devices may typically perform a portion of the
system 110 processing such as keyboard scan/decode, LDC interface etc.
2.11.1 CSI/O block diagram

The CSI/O block diagram is shown in Fig. 2.11.1. The CSI/O consists of two
registers - the Transmit/Receive Data Register (TRDR) and Control Register
(CNTR).

Internal Address/Data Bus

TXS RXS

CKS

CSI/O Transmit/Receive
Data Register:
TRDR (8)
CSI/O Control Register:
1+--------'
CNTR (B)

Interrupt Request

Figure 2.11.1 CSI/O Block Diagram
2.11.2 CSI/O register description
CSI/O Transmit/Receive Data Register (TRDR: I/O Address

=

OBH)

TRDR is used for both CSIIO transmission and reception. Thus, the system design must insure that the constraints of half-duplex operation are met (Transmit and
receive operation can't occur simultaneously). For example, if a CSI/O transmission
is attempted at the same time that the CSI/O is receiving data, a CSIIO will not
work. Also note that TRDR is not buffered. Therefore, attempting to perform a
CSIIO transmit while the previous transmit data is still being shifted out causes the
shift data to be immediately updated, thereby corrupting the transmit operation in
progress. Similarly, reading TRD R while a transmit or receive is in progress should
be avoided.

78

CSI/O Control/Status Register (CNTR: I/O Address

=

OAH)

CNTR is used to monitor CSI/O status, enable and disable the CSIIO, enable
and disable interrupt generation and select the data clock speed and source.
CSI/O Control Register (CNTR : I/O Address = OAH)
bit

o

o

7

6

5

4

EF

EIE

RE

TE

SS2

SS1

SSO

R

RIW

RIW

RIW

RIW

R/W

RIW

3

2

EF: End Flag (bit 7)

EF is set to 1 by the CSIIO to indicate completion of an 8-bit data transmit or
receive operation. If EIE (End Interrupt Enable) bit = 1 when EF is set to I, a
CPU interrupt request will be generated. Program access of TRDR should only occur if EF = 1. The CSIIO clears EF to 0 when TRDR is read or written. EF is
cleared to 0 during RESET and IOSTOP mode.

o

EIE: End Interrupt Enable (bit 6)

EIE should be set to 1 to enable EF = I to generate a CPU interrupt request.
The interrupt request is inhibited if EIE is reset to O. EIE is cleared to 0 during RESET.
ORE: Receive Enable (bit 5)

A CSIIO receive operation is started by setting RE to 1. When RE is set to I,
the data clock is enabled. In internal clock mode, the data clock is output from the
CKS pin. In external clock mode, the clock is input on the CKS pin. In either case,
data is shifted in on the RXS pin in synchronization with the (internal or external)
data clock. After receiving 8 bits of data, the CSI/O automatically clears RE to 0,
EF is set to I and an interrupt (if enabled by EIE = 1) will be generated. Note that
RE and TE should never both be set to 1 at the same time. RE is cleared to 0 during RESET and IOSTOP mode.
Note that the RXS pin (pin 52) is multiplexed with CTSI modem control input
of ASCI channell. In order to enable the RXS function, the CTSIE bit in CNTAI
should be reset to O.

o

TE: Transmit Enable (bit 4)

A CSI/O transmit operation is started by setting TE to 1. When TE is set to 1,
the data clock is enabled. In internal clock mode, the data clock is output from the
CKS pin. In external clock mode, the clock is input on the CKS pin. In either case,
data is shifted out on the TXS pin synchronous with the (internal or external) data
clock. After transmitting 8 bits of data, the CSI/O automatically clears TE to 0, EF
is set to I and an interrupt (if enabled by EIE = 1) will be generated. Note that TE
and RE should never both be set to 1 at the same time. TE is cleared to 0 during
79

RESET and IOSTOP mode.

o

SS2, 1, 0: Speed Select 2, 1, 0 (bits 2-0)

SS2, SS 1 and SSO select the CSI/O transmit/receive clock source and speed.
SS2, SSI and SSO are all set to 1 during RESET. Table 2.11.1 shows CSUO Baud
Rate Selection.
Table 2.11.1 CSI/O Baud Rate
Selection

(

SS2

SS1

SSO

Divide
Ratio

Baud
Rate

0
0
0
0
1
1
1

0
0
1
1
0
0
1

0
1
0
1
0
1
0

+20
+40
+80
+160
+320
+640
+1280

(200000)
(100000)
(50000)
(25000)
(12500)
(6250)
(3125)

1

1

1

external Clock input
(less than + 20)

) shows the baud rate (BPS) at

t/J

= 4 MHz.

After RESET, the CKS pin is configured as an external clock input (SS2, SS 1,
SSO = 1). Changing these values causes CKS to become an output pin and the
selected clock will be output when transmit or receive operations are enabled.
2.11.3 CSI/O interrupts

The CSUO interrupt request circuit is shown in Fig. 2.11.2.

EF

CSI/O
Interrupt Request

EIE

Figure 2.11.2 CSI/O Interrupt Circuit Diagram
2.11.4 CSI/O operation

The CSI/O can be operated using status polling or interrupt driven algorithms.
Transmit - Polling

1. Poll the TE bit in CNTR until TE = O.
80

2. Write the transmit data into TRDR.
3. Set the TE bit in CNTR to 1.
4. Repeat 1 to 3 for each transmit data byte.
Transmit - Interrupts

1.
2.
3.
4.

Poll the TE bit in CNTR until TE = O.
Write the first transmit data byte into TRDR.
Set the TE and EIE bits in CNTR to 1.
When the transmit interrupt occurs, write the next transmit data byte into
TRDR.
5. Set the TE bit in CNTR to 1.
6. Repeat 4 to 5 for each transmit data byte.
Receive - Polling

1.
2.
3.
4.
5.

Poll the RE bit in CNTR until RE = O.
Set the RE bit in CNTR to 1.
Poll the RE bit in CNTR until RE = O.
Read the receive data from TRDR.
Repeat 2 to 4 for each receive data byte.

Receive - Interrupts

1.
2.
3.
4.
5.

Poll the RE bit in CNTR until RE = O.
Set the RE and EIE bits in CNTR to 1.
When the receive interrupt occurs read the receive data from TRDR.
Set the RE bit in CNTR to 1.
Repeat 3 to 4 for each receive data byte.

2.11.5 CSI/O operation timing notes
(1) Note that transmitter clocking and receiver sampling timings are different from

internal and external clocking modes. Fig. 2.11.3 to Fig. 2.11.6 shows CSIIO
Transmit/Receive Timing.
(2) The transmitter and receiver should be disabled (TE and RE = 0) when
initializing or changing the baud rate.
2.11.6 CSI/O operation notes
(1) Disable the transmitter and receiver (TE and RE = 0) before initializing or

changing the baud rate. When changing the baud rate after completion of transmission or reception, a delay of at least one bit time is required before baud rate
modification.
(2) When RE or TE is cleared to 0 by software, a corresponding receive or transmit
operation is immediately terminated. Normally, TE or RE should only be
cleared to 0 when EF = 1.
(3) Simultaneous transmission and reception is not possible. Thus, TE and RE
should not both be 1 at the same time.

81

r~

I

CKS

I
I

I
I

TXS

-x

TE

~

LSB

X

:~

X

MSB

~

EF

I

Read or write of CSI/O
Transmit/Receive
Data Register

Figure 2.11.3 Transmit Timing - Internal Clock

CKS

TXS

MSB

2.5e!>

TE

--.J
~

EF

t

Read or write of CSI/O
Transmit/Receive
Data Register

Figure 2.11.4 Transmit Timing - External Clock

82

CKS

LSB

RXS

MSB

Sampling

RE

~

EF

________________________________

~I----~L_

t

Read or write of CSI/O
T ransmitiReceive
Data Register

Figure 2.11.5 Receive Timing - Internal Clock

CKS

~'-__""'"

RXS

---f '------f

16.5cp

'-----u--' '-_ _ _~ '--_M_S_B_ _ __

16.5cp

16.5cp

16.5 + nw· «/»

1/0 Write Cycle

1st Twl -

T3l

(n w • c/J)

NMI Acknowledge 1st MC

T2l -

INT 0 Acknowledge 1st MC

1st Twl -

BUS RELEASE mode
SLEEP mode
SYSTEM STOP mode

«/>! -

NOTE) nw : the number of wait states
MC : Machine Cycle

89

T3!

(1.5c/J

(1.5c/J)

T3!

«/>!

T3!

(0.5«/>

+ nw· c/J)

(2c/J or 1c/J)

Nf\M
OP-code
fetch cycle

Memory read/
write cycle

I/O read cycle

1/0 write cycle

acknowledge
1stMC

INT0 acknowledge
1stMC

cfJ

E
co

o

LlR
ME_

10E

• Two wait states are automatically inserted.
NOTE) MC: Machine Cycle

Figure 2.13.1 E Clock Timing (During Read/Write Cycle
and Interrupt Acknowledge Cycle)

BUS RELEASE mode

Last I_
state

Tx

Tx

BUSREQ
BUSACK

E

E~

(a) E Clock Timing in BUS RELEASE Mode

SLP
instruction
2nd op-code

I_ fetch cycle _I_

Op-code
SLEEP mode or SYSTEM STOP mode

_I_ fetch cycle

00-07
~.NMI

76H

~--------~--+---------------------------~~------~

E
Ef.....--""\
E fr---""\

(b) E Clock Timing in SLEEP Mode and SYSTEM STOP Mode

Figure 2.13.2 E Clock Timing
(in BUS RELEASE mode, SLEEP mode, SYSTEM STOP mode)

91

Wait states inserted in op-code fetch, memory read/write and I/O read/write cycles extend the duration of E clock output HIGH. Note that during I/O read/write
cycles with no wait states (only occurs during on-chip I/O register accesses), E will
not go HIGH.
The correspondence between the duration of E clock output HIGH and standard
peripheral device speed selections is as follows.
Device Speed Selection Required duration of E clock output HIGH
1.0 MHz (ex: HD6321P)
500 ns min.
1.5 MHz (ex: HD63A21P)
333 ns min.
2.0 MHz (ex: HD63B21P)
230 ns min.
2.13.2 6800 type bus interfacing note

When the HD64180 is connected to 6800 type peripheral LSls with E clock, the
6800 type peripheral LSIs should be located in I/O address space.
If the 6800 type peripheral LSls are located in memory address space, WR set-up
time and WR hold time for E clock won't be guaranteed during memory read/write cycles and 6800 type peripheral LSIs can't be connected correctly.

92

2.14 On-chip Clock Generator
The HD64180 contains a crystal oscillator and system clock (cp) generator. A
crystal can be directly connected or an external clock input can be provided. In
either case, the system clock (cp) is equal to one-half the input clock. For example, a
crystal or external clock input of 8 MHz corresponds with a system clock rate of cp
= 4 MHz.
The following table shows the AT cut crystal characteristics (Co, Rs) and the
load capacitance (CL1, CL2) required for various frequencies of HD64180 operation.
Table 2.14.1 Crystal Characteristics

~

4MHz

4MHz < f

~

12MHz 12MHz < f

~

16MHz

Item

Co

<7 pF

<7 pF

<7 pF

Rs

<60n

<60n

<60n

Cl1, Cl2

10 to 22 pF ± 10%

10 to 22 pF ±10%

10 to 22 pF ±10%

If an external clock input is used instead of a crystal, the waveform (twice the cp
clock rate) should exhibit a 50% + 5% duty cycle. Note that the minimum clock
input HIGH voltage level is Vcc- 0.6V. The external clock input is connected to
the EXTAL pin, while the XTAL pin is left open. Fig. 2.14.1 shows external clock
interface.

EXTAl~3_4--

XTAl

2

JUUL External Clock Input

Open

Figure 2.14.1 External Clock Interface

Fig. 2.14.2 shows the HD64180 clock generator circuit while Fig. 2.14.3 and Fig.
2.14.4 specify circuit board design rules.

93

Cl1

EXTALI-"-3_...--i~
CJ

C~
Figure 2.14.2 Crystal Interface

HD64180

must be avoided

/~

B
A, B: Signal

Signal C ---------=---'----+-

HD64180

Figure 2.14.3 Note for Board Design of the Oscillation Circuit

94

120 mm max1

Signal line layout should
avoid areas marked with 11111.
~

HD64180

(Top View)

Figure 2.14.4 Example of Board Design

Circuit Board design should observe the followings.
(1) To prevent induced noise, the crystal and load capacitors should be physically

located as close to the LSI as possible.
(2) Signal lines should not run parallel to the clock oscillator inputs. In particular, the
clock input circuitry and the system clock c/> output (pin 64) should be separated as
much as possible.
(3) Similar to (2) , Vee power lines should be separated from the cloCk OSCllla{Or
input circuitry.
(4) Resistivity between XTAL or EXTAL and the other pins should be greater than
10M ohms.
Signal line layout should avoid areas marked with III I I.

95

2.15 Miscellaneous
Free Running Counter (110 Address = I8H)
Read only 8-bit free running counter without control registers and status registers. The contents of the 8-bit free running counter is counted down by 1 with an
interval of 10 cJ> clock cycles. The free running counter continues counting down
without being affected by the read operation.
If data is written into the free running counter, we can't guarantee the interval
of DRAM refresh cycle and baud rates of ASCI and CSIIO.
In IOSTOP mode, the free running counter continues counting down. It is
initialized to FFH during RESET.

96

3. HD64180 SOFTWARE ARCHITECTURE
3.1 Instruction Set
The HD64180 is object code compatible with standard 8-bit operating system
and application software. The instruction set also contains a number of new instructions to improve system and software performance, reliability and efficiency.

New Instructions
SLP
MLT
INO g, (m)
OUTO (m), g
OTIM
OTIMR
OTDM
OTDMR
TSTIO m
TST g
TSTm
TST (HL)

Operation
Enter SLEEP mode
8-bit multiply with 16-bit result
Input contents of immediate I/O address into register
Output register contents to immediate I/O address
Block output - increment
Block output - increment and repeat
Block output - decrement
Block output - decrement and repeat
Non-destructive AND, I/O port and accumulator
Non-destructive AND, register and accumulator
Non-destructive AND, immediate data and accumulator
Non-destructive AND, memory data and accumulator

SLP - Sleep

The SLP instruction causes the HD64180 to enter SLEEP low power consumption mode. See section 2.4 for a complete description of the SLEEP state.
MLT -

Multiply

The MLT performs unsigned multiplication on two 8 bit numbers yielding a 16
bit result. MLT may specify BC, DE, HL or SP registers. In all cases, the 8-bit operands are loaded into each half of the 16-bit register and the 16-bit result is returned
in that register.
INO g, (m) -

Input, Immediate I/O address

The contents of immediately specified 8-bit 110 address are input into the specified register. When I/O is accessed, OOH is output in high-order bits of address automatically.
OUTO (m), 9 - Output, immediate I/O address

The contents of the specified register are output to the immediately specified 8bit I/O address. When I/O is accessed, OOH is output in high-order bits of address
automatically.
OTIM, OTIMR, OTOM, OTOMR -

Block I/O

The contents of memory pointed to by HL is output to the I/O address in (C).
The memory address (HL) and I/O address (C) are incremented in OTIM and
OTIMR and decremented in OTD M and OTD MR respectively. B register is decre97

mented. The OTIMR and OTDMR variants repeat the above sequence until register
B is decremented to O. Since the 110 address (C) is automatically incremented or
decremented, these instructions are useful for block I/O (such as HD64180 on-chip
I/O) initialization. When 110 is accessed, OOH is output in high-order bits of address
automatically.
TSTIO m - Test I/O Port

The contents of the 110 port addressed by Care ANDed with immediately specified 8-bit data and the status flags are updated. The 110 port contents are not written (non-destructive AND). When 110 is accessed, OOH is output in higher bits of
address automatically.
TST g - Test Register

The contents of the specified register are ANDed with the accumulator (A) and
the status flags are updated. The accumulator and specified register are not changed
(non-destructive AND).
TST m - Test Immediate

The contents of the immediately specified 8-bit data are ANDed with the accumulator (A) and the status flags are updated. The accumulator. is not changed
(non-destructive AND).
TST (HL) - Test Memory

The contents of memory pointed to by HL are ANDed with the accumulator
(A) and the status flags are updated. The memory contents and accumulator are not
changed (non-destructive AND).

98

3.2 CPU Registers
The HD64180 CPU registers consist of Register Set GR, Register Set GR' and
Special Registers.
The Register Set G R consists of 8-bit Accumulator (A), 8-bit Flag Register (F),
and three General Purpose Registers (BC, DE, and HL) which may be treated as
16-bit registers (BC, DE, and HL) or as individual 8-bit registers (B, C, D, E, H,
and L) depending on the instruction to be executed. The Register Set GR' is alternate register set of Register Set GR and also contains Accumulator (A'), Flag Register (F') and three General Purpose Registers (BC', DE', and HL'). While the alternate Register Set GR' contents are not directly accessible, the contents can be
programmable exchanged at high speed with those of Register Set GR.
The Special Registers consist of 8-bit Interrupt Vector Register (I), 8-bit R
Counter (R), two 16-bit Index Registers (IX and IY), 16-bit Stack Pointer (SP), and
16-bit Program Counter (PC).
Fig. 3.2 shows CPU registers configuration.

Special Registers

Register Set GR
Accumulator
A

Flag Register
F

B Register

C Register

D Register

E Register

H Register

L Register

Interrupt
Vector Register
I
General
> Purpose
Registers

Flag Register
F'

B'Register

C'Register

D' Register

E'Register

H'Register

L'Register

R

Index Register

IX

Index Register

IY

Stack Pointer

SP

Program Counter PC

Register Set GR'
Accumulator
A'

R Counter

1,\

General
>- Purpose
Registers

99

3.2.1 Register description
Accumulator (A, A')

The Accumulator (A) serves as the primary register used for many arithmetic,
logical and 110 instructions.
Flag Registers (F, F')

The flag register stores various status bits (described in the next section) which
reflect the results of instruction execution.
General Purpose Registers (BC, BC', DE, DE', HL, HL')

The General Purpose Registers are used for both address and data operation.
Depending on instruction, each half (8 bits) of these registers (B, C, D, E, H, and
L) may also be used.
Interrupt Vector Register (I)

For interrupts which require a vector table address to be calculated (INTo Mode
2, INTI, INT2 and internal interrupts), the Interrupt Vector Register (I) provides

the most significant byte of the vector table address.
R Counter (R)

The least significant seven bits of the R Counter (R) serve to count the number
of instructions executed by the HD64180. R is incremented for each CPU op-code
fetch cycles (each LIR cycles).
Index Registers (IX, and IV)

The Index Registers are used for both address and data operations. For addressing, the contents of a displacement specified in the instruction are added to or subtracted from the Index Register to determine an effective operand address.
Stack Pointer (SP)

The Stack Pointer (SP) contains the memory address based LIFO stack.
Program Counter (PC)

The Program Counter (PC) contains the address of the instruction to be executed and is automatically updated after each instruction fetch.
3.2.2 Flag Register (F)

The Flag Register stores the logical state reflecting the results of instruction execution. The contents of the Flag Register are used to control program flow and instruction operation.

100

bit

7

6

s

z

5

4

3

I PN I

H

o

2
N

c

Flag Register (F)

OS: Sign (bit 7)

S stores the state of the most significant bit (bit 7) of the result. This is useful
for operations with signed numbers in which values with bit 7 = 1 are interpreted
as negative.

o

Z: Zero (bit 6)

Z is set to 1 when instruction execution results containing O. Otherwise, Z is reset to O.

o

H: Half Carry (bit 4)

H is used by the DAA (Decimal Adjust Accumulator) instruction to reflect borrow or carry from the least significant 4 bits and thereby adjust the results of BCD
addition and subtraction.

o

PN: ParitylOverflow (bit 2)

PIV serves a dual purpose. For logical operations PN is set to 1 if the number
of 1 bit in the result is even and PIV is reset to 0 if the number of 1 bit in the result is odd. For two complement arithmetic, P/V is set to 1 if the operation produces a result which is outside the allowable range (+ 127 to - 128 for 8-bit operations, + 32767 to - 32768 for 16-bit operations).
ON: Negative (bit 1)

N is set to 1 if the last arithmetic instruction was a subtract operation (SUB,
DEC, CP, etc.) and N is reset to 0 if the last arithmetic instruction was an addition
operation (ADD, INC, etc.).

o

C: Carry (bit 0)

C is set to 1 when a carry (addition) or borrow (subtraction) from the most significant bit of the result occurs. C is also affected by Accumulator logic operations
such as shifts and rotates.

101

3.3 Addressing Modes
The HD64180 instruction set includes eight addressing modes.
Implied Register
Register Direct
Register Indirect
Indexed
Extended
Immediate
Relative
10
Implied Register (IMP)

Certain op-codes automatically imply register usage, such as the arithmetic operations which inherently reference the Accumulator, Index Registers, Stack Pointer
and General Purpose Registers.
Register Direct (REG)

Many op-codes contain bit fields specifying registers to be used for the operation.
The exact bit field definition vary depending on instruction as follows.
8-bit Register
g or g' field

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1

1

1

Register

ww field

Register

B

BC

D

0 0
0 1
1 0

E

1

SP

C

1

DE
HL

H
L

-

xx field

Register

A

0 0
0 1
1 0

BC

1

SP

1

DE
IX

1 6-bit Register
zz field

Register

vy field

Register

0 0
0 1
1 0

BC

BC

HL

0 0
0 1
1 0

1

AF

1

SP

1

DE

1

DE
IV

Suffixed Hand L to ww,xx,yy,zz (ex. wwH,IXL) indicate upper and lower a-bit of the 16-bit
register respectively.

102

Register Indirect (REG)

The memory operand address is contained in one of the 16-bit General Purpose
Registers (BC, DE and HL).

Be
DE
HL

Operand
Memory

Indexed (lNDX)

The memory operand address is calculated using the contents of an Index Register (IX or IY) and an 8-bit signed displacement specified in the instruction.

op-code 1
op-code 2

Sign extended

displacement (d)

I

IX or IV

I

-.....

+

"'r-

Operand
Memory

-.....

.....

Extended (EXT)

The memory operand address is specified by two bytes contained in the instruction.

op-code
n
m
,.-

m

I

n

.....

I

-~

Operand

J

Memory
-'--

103

--

Immediate (lMMED)

The memory operands are contained within one or two bytes of the instruction.

I ~code
m

~
t=d}

I} 8-bit operand

16-bit operand

Relative (REL)

Relative addressing mode is only used by the conditional and unconditional
branch instructions. The branch displacement (relative to the contents of the program counter) is contained in the instruction.

op-code
displacement (j)

I

Sign extended

1

Program Counter (PC)

f

I

10 (10)

10 addressing mode is used only by I/O instructions. This mode specifies I/O ad-

dress (IOE = 0) and outputs them as follows.
(1) An operand is output to Ao-A7. The Contents of Accumulator is output to A8A15.
(2) The Contents of Register B is output to Ao-A7. The Contents of Register C is
output to A8-AI5.
(3) An operand is output to Ao-A7. OOH is output to A8-AI5.
(useful for internal 110 register access)
(4) The Contents of Register C is output to Ao-A7. OOH is output to As-AI5.
(useful for internal I/O register access)

104

4. HD64180 PROGRAMMING NOTE
The followings explain the symbols in programming note.
1. Register
g, g', ww, xx, YY, and zz specify a register to be used. g and g' specify an 8-bit register. ww, xx, yy, and zz specify a pair of 16-bit registers. The following tables show the
correspondence between symbols and registers.
g,g' Reg.
000
B
001
C
010 D
011
E
100 H
101
L
111
A

ww Reg.
00 BC
01 DE
10 HL
SP
11

xx

00
01
10
11

Reg.
BC
DE

IX
SP

yy

00
01
10
11

Reg.
BC
DE
IY
SP

zz

Re~

00

BC
DE
HL

01
10
11

AF

NOTE: Suffixed Hand L to ww,xx,yy,zz (ex.wwH,IXL) indicate upper and lower 8-bit of the 16-bit register respectively.

2. Bit
b specifies a bit to be manipulated in the bit manipulation instruction. The following table shows the correspondence between b and bits.
b
000
001
010
011
100
101
110
111

Bit
0
1

2
3
4

5
6
7

3. Condition
f specifies the condition in program control instructions. The following shows
the correspondence between f and conditions.

105

f

000
001
010
011
100
101
110
111

NZ
Z
NC
C
PO
PE
P
M

Condition
non zero
zero
non carry
carry
parity odd
parity even
sign plus
sign minus

4. Restart Address
v specifies a restart address. The following table shows the correspondence between v and restart addresses.
v

Address

000
001
010
011
100
101
110
111

OOH
08H
10H
I8H
20H
28H
30H
38H

5. Flag
The following symbols show the flag conditions.
not affected
1 : affected
x : undefmed
S : set to 1
R : reset to 0
P : parity
V : overflow

106

6. Miscellaneous
(
(

)M
)1

morn
mn
r
R
b o(
)M
bogr
dorj
S
D

+
Ee

data in the memory address
data in the 110 address
8-bit data
16-bit data
8-bit register
16-bit register
a content of bit b in the memory address
a content of bit b in the register gr
8-bit signed displacement
source addressing mode
destination addressing mode
AND operation
OR operation
EXCLUSIVE OR operation

NOTE) As for addressing modes, please refer to '2.1.3 Addressing Mode' for details.

107

I/O Instruction
INO

INO (INput)

I

I

Status Flags Affected

II

Format

INa

g, (m)

C
N

P/V

IOperation

II

H

Z

(OOm)1 -+ gr
The 2nd op-code=30H
: Only the flags will change

S

II

: Not affected
: Reset
: Set if parity is even ;
reset otherwise
: Reset
: Set if (OOm)1 =OOH ;
reset otherwise
: Set if (OOm)1 is negative ;
reset otherwise

(m-+ Ao-A7
)
OOH -+ As-A15

I

Description

II

Transfers the contents of the I/O device specified by (OOm)*1 into register gr.
To specify an I/O device, OOH is loaded into As-A15 and an 8·bit data m is loaded into Ao-A7.

*

NOTE : If an external I/O address corresponds to an internal I/O register address, the contents of
the internal I/O register is transferred to the gr.

Addressing Mode and the Number of Execution Cycles
Addressing Mode
Mnemonics
S

10

0

REG

Operand
Format

INO

B, (m)

INO

C, (m)

INO

0, (m)

INO

E, (m)

INO

H, (m)

INO

L, (m)

-

-

INO

A, (m)

Instruction Code
3rd Byte

,

,

,

Bytes

Machine
Cycles

4th Byte

States

1st Byte

2nd Byte

ED
ED
ED
ED
ED
ED
ED
ED

00

m

3

4

12

08

m

3

4

12
12

10

m

3

4

18

m

3

4

12

20

m

3

4

12

28

m

3

4

12

30

m

3

4

12

38

m

3

4

12

108

Arithmetic/Logical Instruction
MLT

MLT (MuLTiply unsigned)

I

Format

I

II
MLT

loperation

Status Flags Affected

II

ww

II

Not affected

wwHr X wwLr -+

WWR

IDescription II

Multiplies upper 8-bit of register pair ww (BC, DE, HL or SP) by lower 8-bit of the
16-bit result into the

WW,

and stores the

WW.

Addressing Mode and the Number of Execution Cycles
Addressing Mode

S

REG

D
REG

Mnemonics

Operand
Format

MLT

BC

MLT

DE

MLT

HL

MLT

SP

#

Instruction Code

Bytes
1st Byte

2nd Byte

ED
ED
ED
ED

4C
5C
6C
7C

109

3rd Byte

4th Byte

2
2
2
2

#
Machine
Cycles
13

#
States
17

13

17

13

17

13

17

I/O Instruction

OTOM

OTDM (OuTput Decrement Memory)

IFormat

I Status Flags Affected II

II
OTOM

C
N
p /V

loperation

II

H

(HL)M -+ (OOC)I
HLR -1 -+ HLR
Cr-l -+ Cr
Br-l -+ Br
(

Z

S

Cr -+ Ao -A7
)
DOH -+ As -AIS

: Set if a borrow occurs after Br-l ;
reset otherwise
: Set if MSB in (HL)M =1 ;
reset otherwise
~ Set if parity in Br is even after Br-l ;
reset otherwise
: Set if a borrow from bit 4 in Br occurs
after Br-l ;
reset otherwise
: Set if Br=OOH after Br-l ;
reset otherwise
: Set if Br is negative after Br-l ;
reset otherwise

Description JI
OTOM operates as follows.
Transfers the data in the memory addressed by the contents of the register pair HL into the I/O
device specified by (OOC)·I .
(2) Decrements the contents of the register pair HL., contents of the register C and the contents of
the register B.
To specify an I/O device, DOH is loaded into As -AlS, and the contents of the register C is
loaded into Ao -A7 .
(1)

*

NOTE : If an external I/O address corresponds to an internal I/O register address, the same data will
be transferred into both internal I/O register and external I/O device.

Addressing Mode and the Number of Execution Cycles
Addressing Mode
Mnemonics

S

0

REGI

10

OTOM

Operand
Format

#

Instruction Code
1st Byte

2nd Byte

ED

8B

110

3rd Byte

Bytes

Machine
Cycles

States

2

6

14

4th Byte

I
I

I/O Instruction
OTDMR

OTDMR (OuTput Decrement Memory Repeat)

IFormat

IStatus Flags Affected II

II

: Reset·
: Set if MSB of (HL)M = 1 ;
reset otherwise
P/V : Set·
H
: Reset·
Z
: Set·
S
: Reset·
If OTDMR temporally terminates by an
interrupt, C, PlY, H, Z and S flags are set the
same as those in OTDM depending on the
result of Br-1 when an interrupt occurs.

C

OTDMR

loperation

N

II
(HL)M - (DOC),
HLR - 1 - HLR
Q [ Cr-1-Cr
Br-1 - Br
Repeat Q until Br=OOH
(

Description

*

Cr - Ao --A7 )
DOH - As --A15

II

OTDMR operates as follows.
(1) Transfers the data in the memory addressed by the contents of the register pair HL into the I/O
device specified by (DOC)·,.
(2) Decrements the contents of the register pair HL, contents of the register C and the contents of
the register B.
(3) Repeats operations (1) and (2) until Br=OOH.
To specify an I/O device, DOH is loaded into As ",A15, and the contents of the register C is
loaded into Ao --A7 .
NOTE : (1) If an external I/O address corresponds to an internal I/O register address, the same data
will be transferred into both internal I/O register and external I/O device.
(2) If an interrupt occurs, OTDMR can temporally terminate its operation.
After returning from the interrupt service routine, OTDMR can also resume its
operation.

*

Addressing Mode and the Number of Execution Cycles
Addressing Mode

1

S

D

REGI

10

*

If Br:FOOH.

Mnemonics

Operand
Format

OTDMR

2

*

Instruction Code
Bytes
1st Byte

2nd Byte

ED

9B

If Br=OOH.

111

3rd Byte

4th Byte

2

#
Machine
Cycles

States

8

16

I.

6

14

2*

I/O Instruction
OTIM

OTIM (OuTput Increment Memory)
I Format

I Status Flags Affected

II
OTIM

C
, N

IOperation

P/V

II

H

(HL)M - (OOC)I
HLR +1 - HLR
Cr+l - Cr
Br-l - Br
Cr- Ao -A7 )
(
OOH -As-A15
I Description

Z
S

II

: Set if a borrow occurs after Br-l ;
reset otherwise
: Set if MSB of (HL)M=1 ;
reset otherwise
: Set if parity in Br is even after Br-l ;
reset otherwise
: Set if a borrow from bit 4 of Br occurs
after Br-l ;
reset otherwise
: Set if Br=OOH after Br-l ;
reset otherwise
: Set if Br is negative after Br-l ;
reset otherwise

II

OTIM operates as follows.
Transfers the data in the memory addressed by the contents of the register pair HL into the I/O
device specified by (OOC)·I.
(2) Increments the contents of the register pair HL and the contents of the register C, and
decrements the contents of the register B.
To specify an I/O device, OOH is loaded into As -A15, and the contents of the register C is
loaded into Ao -A7 .
NOTE : If an external I/O address corresponds to an internal I/O register address, the same data will
be transferred into both internal I/O register and external I/O device.

(1)

*

Addressing Mode and the Number of Execution Cycles
Addressing Mode

S

D

REGI

10

Mnemonics
OTIM

Operand
Format

Instruction Code
Bytes
1st Byte

2nd Byte

ED

83

112

3rd Byte

4th Byte

2

"

Machine
Cycles

States

6

14

r

I/O Instruction

I

OTIMR

OTIMR (OuTput Increment Memory Repeat)

IFormat

I Status Flags Affected II

II

: Reset*
: Set if MSB of (HL)M = 1 ;
reset otherwise
P/Y : Set*
H
: Reset*
Z
: Set*
: Reset*
S
If OTIMR temporally terminates by an
interrupt, C, PlY, H, Z and S flags are set the
same as those in OTIM depending on the
result of Br-l when the interrupt occurs.

C

OTIMR

loperation

N

II
(HL)M - (OOC)I

*

Q HLR +1 - HLR
Cr+l - Cr
Br-l - Br
Repeat Q until Br=OOH
(
Description

Cr-Ao,.."A7
)
OOH - As ""'A15

II

OTI MR operates as follows.
(1) Transfers the data in the memory addressed by the contents of the register pair HL into the I/O
device specified by (OOC)·I.
(2) Increments the contents of the register pair HL and the contents of the register C, and
decrements the contents of the register B.
(3) Repeats operations (1) and (2) until Br=OOH.
To specify an I/O device, OOH is loaded into As ,.."A15, and the contents of the register C is
loaded into Ao "",A7.
NOTE : (1) If an external I/O address corresponds to an internal I/O register address, the same
data will be transferred into both internal I/O register and external I/O device.
(2) If an interrupt occurs, OTIMR can temporally terminate its operation.
After returning from the interrupt service routine, OTIMR can also resume its operation.

*

Addressing Mode and the Number of Execution Cycles
Addressing Mode
Mnemonics

1

S

0

REGI

10

*

If Br*OOH

Operand
Format

OTIMR

2*

#

Instruction Code
Bytes
1st Byte

2nd Byte

ED

93

If Br=OOH

113

3rd Byte

4th Byte

2

Machine
Cycles

States

8

16

10

6

14

2*

I/O Instruction
OUTO

OUTO (OUTput)

IFormat

I Status Flags Affected II

II
OUTO

(m), g

IOperation II

Not affected

gr --+ (OOm)1
(m --+ Ao -A7
)
OOH --+ As -A15

Description

II

Transfers the contents of register gr into the I/O device specified by (OOm)*I.
*To specify an I/O device, OOH is loaded into As -A15, and an 8·bit data m is loaded into Ao

-A7.
NOTE : If an external I/O address corresponds to an internal I/O register address, the same data is
transferred into both internal I/O register and external I/O device.

Addressing Mode and the Number of Execution Cycles
Addressing Mode
S

REG

1st Byte

2nd Byte

3rd Byte

OUTO

(m), B

ED

01

m

3

OUTO

(m), C

ED

09

m

3

OUTO

(m),O

ED

11

m

3

OUTO

(m), E

ED

19

m

3

OUTO

(m), H

ED

21

m

3

OUTO

(m), l

ED

29

m

3

OUTO

(m), A

ED

39

m

3

0

10

#

Instruction Code

Operand
Format

Mnemonics

Bytes

114

4th Byte

#
Machine
Cycles

5
5
5
5
5
5
5

#
States
13
13
13
13
13
13
13

Special Control Instruction
SLP

SLP (SLeeP)

IFormat

I Status Flags Affected II

II
SLP

IOperation

II

Not affected

Sleep

Description

II

If 10STP bit in the I/O control register is reset to 0, the MPU enters into SLEEP mode by executing
SLP. If 10STP bit in the I/O control register is set to 1, the MPU enters into SYSTEM STOP mode
by executing SLP.
RESET or Interrupt is valid for exiting SLEEP mode or SYSTEM STOP mode.

Addressing Mode and the Number of Execution Cycles
Addressing Mode
Mnemonics

S

0
SLP

Operand
Format

Bytes

#
Machine
Cycles

States

2

2

8

Instruction Code
1st Byte

2nd Byte

ED

76

115

3rd Byte

4th Byte

I/O Instruction
TSTIO

TSTIO (TeST I/O port)
\ Format

\ Status Flags Affected

II
TSTIO

m

C
N
P/V

\Operation

II

H
Z

(OOC) , • m
Cr - Ao -A7 )
(
OOH - As -A15

Description

S

II

: Reset
: Reset
: Set if parity is even ;
reset otherwise
: Set
: Set if the result is zero ;
reset otherwise
: Set if the result is negative ;
reset otherwise

II

TSTIO m operates as follows.
Loads the contents of the register C into Ao -A7, and loads OOH into As -A15 to specify an
I/O device.
(2) Performs bitwise 10gical·AND operation between an 8·bit data m and the contents of the
specified I/O device.
(1)

NOTE : If the I/O address corresponds to an internal I/O register address, TSTIO m performs bitwise
10gical·AND operation between an 8-bit data m and the contents of the internal I/O register.

Addressing Mode and the Number of Execution Cycles
Addressing Mode
Mnemonics

S

0

IMMED/IO

-

TSTIO

,

Instruction Code

Operand
Format

1st Byte

2nd Byte

3rd Byte

m

ED

74

m

116

Bytes

Machine
Cycles

States

3

4

12

4th Byte

Arithmetic/Logical Instruction
TST

TST (TeST)
/Format

/ Status Flags Affected

II
TST

loperation

g

C

: Reset
N
: Reset
P/V : Set if parity is even ;
reset otherwise
H
: Set
Z
: Set if the result is zero ;
reset otherwise
: Set if the result is negative ;
S
reset otherwise

II
Ar· gr

Description

II

II

Performs bitwise 10gical·AND operation between the contents of the Accumulator A and the contents
of register gr.

Addressing Mode and the Number of Execution Cycles
Addressing Mode
Mnemonics
S

REG

0

-

Operand
Format

TST

B

TST

C

TST

0

TST

E

TST

H

TST

L

TST

A

1st Byte

ED
ED
ED
ED
ED
ED
ED

,

I

Instruction Code

,

Bytes

Machine
Cycles

04

2

3

OC

2

3

14

2

1C

2

3
3

2nd Byte

3rd Byte

4th Byte

24

2

3

2C

2

3C

2

3
3

117

States

7
7
7
7
7
7
7

Arithmetic/Logical Instruction

TST

TST (TeST)

IFormat

IStatus Flags Affected II

II
TST

m

C

: Reset
: Reset
N
P/V : Set if parity is even ;
reset otherwise
H
: Set
: Set if the result is zero ;
Z
reset otherwise
: Set if the result is negative ;
S
reset otherwise

IOperation II
Ar· m

IDescription II

Performs bitwise 10gical·AND operation between the contents of the Accumulator A and an 8·bit data

m

Addressing Mode and the Number of Execution Cycles
Addressing Mode
Mnemonics
S

0

IMMEO

-

TST

Instruction Code

Operand
Format

1st Byte

2nd Byte

3rd Byte

m

ED

64

m

118

,

,

,

Bytes

Machine
Cycles

States

3

3

9

4th Byte

Arithmetic/Logical Instruction

TST

TST (TeST)

IFormat

I Status Flags Affected I

II
TST

loperation

(HL)

C

: Reset
N
: Reset
P/V : Set if parity is even ;
reset otherwise
H
: Set
Z
: Set if the result is zero ;
reset otherwise
S
: Set if the result is negative;
reset otherwise

II

Ar • (HL)M

Description

JI

Performs bitwise 10gical·AND operation between the contents of the Accumulator A and the data in
the memory addressed by the contents of the register pair HL

Addressing Mode and the Number of Execution Cycles
Addressing Mode
Mnemonics

S

0

REGI

-

TST

#

Instruction Code

Operand
Format

1st Byte

2nd Byte

(HL)

ED

34

119

3rd Byte

Bytes

Machine
Cycles

States

2

4

10

4th Byte

5. HD64180 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS

•

Item

Symbol

Supply Voltage
Input Voltage

Vee
V in

Operating Temperature

Topr

Storage Temperature

T stg

Value
-0.3 -0.3 -

Unit

+7.0

V
V

Vee+0.3

°C
°C

0-+70
-55 -

+150

[NOTE] Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation
should be under recommended operating conditions. If these conditions are exceeded. it
could affect reliability of LSI.

DC CHARACTERISTICS (Vee = 5V + 10%, Vss
70°C)

•

+

Symbol

Item

VIH1

Input "H" Voltage
RESET. EXTAL. NMI

VIH2

Input "H" Voltage
Except RESET. EXTAL, NMI

Vll1

Input "L" Voltage
RESET. EXTAL. NMI

V1l2

Input "L" Voltage
Except RESET. EXTAL, NMI

VOH

Output "H" Voltage
All Outputs

III

ITl

lee

Cp

Output "L" Voltage
All Outputs
Input Leakage
Current All Inputs
Except XTAL. EXTAL
Three State Leakage
Current

typ

max

Unit

Vee -0.6

-

Vee+ 0.3

V

2.0

-

Vee+ 0 .3

V

-0.3

-

0.6

V

-0.3

-

0.8

V

Vee- 1.2

-

-

Iol = 1.6 mA

-

-

0.45

V

Vin=0.5 - Vee-0.5

-

-

1.0

/LA

Vin=0.5 - Vcc-0.5

-

1.0

/LA

10
15
2.5
3.8

20
30
5.0
7.5

-

12

IOH = - 200/LA

2.4

V

Power Dissipation
(Normal Operation)

f=4 MHz
f=6 MHz

Power Dissipation
(SYSTEM STOP mode)

f=4 MHz
f=6 MHz

-

Vin=OV. f= 1 MHz
Ta=25°C

-

Pin Capacitance

0---

min

Condition

IOH = -20/LA
VOL

OV, Ta

120

mA
mA
pF

•

AC CHARACTERISTICS

=

(Vee

5V ±10%. Vss

HD64A180RO
Symbol

Item

typ

max

-

2000

162

ns

-

-

2000

57

-

ns

-

-

110

-

-

105
125·

45
30··

-

-

10
-15··

-

-

-

-

-

-

100
115···

ns

35

-

-

ns

-

-

75

ns

75

ns

-

100

ns

-

ns

100

ns

100

ns

-

ns

tcHW

110

tcLW

Clock "L" Pulse Width

100

tef

Clock Fall Time

ter

Clock Rise Time

(ME or IOE

-

II

25
20

130·

~ED1

ME Delay Time 1

~DD1

RD Delay Time 1

-

-

tu>1

LlR Delay Time 1

-

-

105
120···

(ME or IOE II

80

-

-

~ED2

ME Delay Time 2

~D02

RD Delay Time 2

tLD2

LlR Delay Time 2

-

tORS

Data Read Set-up Time

50

tORH

Data Read Hold Time

tST01

ST Delay Time 1

tSTo2

ST Delay Time 2

-

tws

WAIT Set-up Time

80

tWH

WAIT Hold Time

70

-

tAH

Address Hold Time

0

NOTE) Each symbols shows the value at the following conditions.

=

·1. Just after RESET (Restart address
OOOOOH)
2. At the beginning of SLEEP mode or SYSTEM STOP mode
(Starting address = 7FFFFH)
3. After BUS RELEASE mode
··1. Just after RESET (Restart address = OOOOOH)
2. After BUS RELEASE mode
···1. Just after RESET (Restart address

Unit

min

250

Address Set-up Time

HD64B180RO

max

Clock Cycle Time

tAS

+70°C)

typ

Clock "H" Pulse Width

Address Delay Time

0 -

min

teyc

tAO

= OV. Ta =

= OooooH)

121

85
85

85
85
105

57

-

-

45

110

-

110

-

0

70
60

ns

25

ns

20

ns
ns

ns

75

ns

75

ns

ns

ns

(to be continued)

(Vee

= 5V ±10%. VSS = OV, Ta = 0

HD64A180RO
Symbol

Item

min

typ

max

-

100

-

-

95

-

-

80

ns

90

ns

-

-

ns

80

ns

-

ns
ns

-

75

ns

75

ns

-

ns

tWROl

WR' Delay Time

twoo

Write Data Delay Time

-

(WJf U

60

twRD2

WFr Delay Time 2

-

tWRP

WR" Pulse Width

220

tWOH

Write Data Hold Time
(WRf)

60

K5E Delay Time
K5E Delay Time

-

ljOD1
ljoD2
ljOD3
ljNTS

1
2

IOE Delay Time 3

mu

M
(4)

Set-up Time

U

Unit
max

-

Write Data Set-up Time

HD64B180RO

typ

Write Data Floating
Delay Time

twos

+70°C)

min

tWDZ

1

-

540

-

80
70

-

40

90

-

85

135
40

-

-

-

340

-

-

-

70

-

-

ns

• -

60

-

ns

120

-

-

60

-

-

ns

95

ns

~

mHold Time
(4) U

lNMIW

NMj"Pulse Width

120

-

taRS

BUSREO Set-up Time
(4) U

80

-

taRH

BUSREO Hold Time
(4) U

70

taAo1

BUSACK Delay Time 1

taAo2

~ Delay Time 2

taZD

Bus Floating Delay Time

lMEWH

ME Pulse Width
(HIGH)

200

-

lMEWL

ME Pulse Width
(LOW)

210

-

-

90
110

ns

85

100

70

-

100

-

-

130

-

-

ns
ns

95

ns

125

ns

110

-

-

ns

125

-

-

ns

(to be continued)

122

(Vee

= 5V ±10%, Vss =

HD64A180RO
Symbol

Item

max

110

-

ns

100

ns

300

-

-

100

-

-

toRas

DREQi Set-up Time

80

toRQH

DREQi Hold Time

70

TENDi Delay Time 1

tTED2

TENm Delay Time

teo-t

Enable Delay Time 1

2

Unit

typ

1HAo2

tTEDt

HD64B180RO
min

HALT Delay Time 1

1

+70°C)

max

'RArr Delay Time 2

'REF Delay Time 2

-

typ

1HAot

1m! Delay Time

=0

min

-

~FDt

tm=02

OV. Ta

110
110
110

85
85
100

60

ns
ns

-

ns

70

ns

ns

70

ns

95

ns

95

ns

300

ns

tED2

Enable Delay Time 2

tTOO

Timer Output Delay Time

tSTDI

CSVO Transmit Data
Delay Time
(Internal Clock Operation)

-

-

200

-

-

200

ns

tSTDE

CSVO Transmit Data
Delay Time
(Extemal Clock Operation)

-

-

7.5
tcyc
+300

-

-

7.5
tcyc
+300

ns

tSRSI

CSVO Receive Data
Set-up time
Ontemal Clock Operation)

1

-

-

1

-

-

tcyc

tSRHI

CSVO Receive Data
Hold Time
(lntemal Clock Operation)

1

-

-

1

-

-

tcyc

tSRSE

CSVO Receive Data
Set-up Time
(Extemal Clock Operation)

1

-

-

1

-

-

tcyc

tSRHE

CSVO Receive Data
Hold Time
(Extemal Clock Operation)

1

-

-

1

-

-

tcyc

~ES

RESET Set-up TIme

120

RESET Hold Time

80

-

80

-

-

ns

tose

Oscillator Stabilization
Time

-

-

120

~EH

20

-

-

20

ms

123

100

70

100
100

ns

ST--~-

Data

IN

---++--~4-~~

Data

---tt-------------2~

OUT

RESfl~ t_EH______
CPU Timing (1)

124

·1 Output buffer is off at this point.

Data
IN *1

REF *2
BOSREQ

BusAcK
ADDRESS ______________~~
DATA
~--------__----~1'--_ __
~ "AD'
WR, TOE

CPU Timing (2)

125

*1 during INTo acknowledge cycle
.
.
*2 during refresh cycle
*3 Output buffer is off at this point.

T1

CPU or DMA Read/write Cycle (Only DMA Write Cycle for TENDj)
T2
Tw
T3
~

II

T1

r--

cp

f5RMi
(at level sense)

.DREQI

.....

(at edge sense)
----'--'---~--

I\)

"

' 1 - - - - - - - - - _ _ _ _ _ _ _ _ _ _ _ _ _ .....

----~

_ _ __

en

*4

tTE01

tST02

tTE02
TENDi

.

*3 tST01

ST

*'

tORQS and tORQH are specified for the rising edge of clock followed by T 3.

*2 tORQS and tORQH are specified for the rising edge of clock.
*3 DMA cycle starts.
*4 CPU cycle starts.

DMA Control Signals

T1

T2

T3

c/J

E
(Memory ReadIWrite)
tEO 1

E
(VO Read)
tE02

E
I\)

tORS

(I/O Write)

.......

fORH

00-07

~

(

(C~(

E Clock Timing (1)

cp

E
BUS RELEASE mode)
( SLEEP mode

I'

E Clock Timing (2)

--J

..
CD

.sto-

«

128

SLP Instruction fetch

Next op-code fetch
T1

~

twTs. I I . twrH

INTi

:M

NUT
...a.

N

co

Ao-A1d

Mt1lf
RD

tHAo2
~LT

SLP Execution Cycle

T2

CSI/O Clock

Transmit data
(Internal Clock)

I

I

I

tSTDE

U)

0

Transmit data
(External Clock)

~

tSTDE

I

11tCYC

Receive data
(Internal Clock)

,"

I( ,

I'

"I

t SRH1 '

I

1

'1

16.5tCYC

Y

~

I' "

Receive data
(External Clock)

CSI/O ReceivelTransmit Timing

" 11.5tcyc

tSRHI

16.5tcyc

Ji

VC~L=2.2kn

Test Point

CR

C= 90pF

152074 ®

or Equiv.

R= 12k!}

Bus Timing Test Load (TTL Load)

J:

2.0V

J:

2.0V)C

2.4V

2.4V)C

0.8V
0.8V
------

-0.8V
- - - -0.8V
-

Reference Level (Output)

Reference Level (Input)

131

6. HD64180 PACKAGE DIMENSIONS
Unit: mm (inch)

64 Pin

(Scale 1/1)

I

..

57.6(2.268)
58.0ml'
(2.283max)

.,

I~: : : : : : : : : : : : : : :lf~!
...!J Yfo39)

32

5

:E

_~:----~!~l!

~~~
I I I 78±025
0.48±0.1~

1 )\'
I-

III

--l--I-f0070±00101

(0019±0.004)

(DP·64SI

132

N

19.05
(0.750)

I

I

\\

0' -IS'

o.

1f>:%~
.o~)

~.o,O-ciOO

68 Pin
9

25.15':: 0.12
( 0 . 990 -1 0 005)
168

10

(Scale 3/2)
61
60

~Index

\I")
NO
-:0

OM
N\I")

00

·en

+1+1
\I") 0

""""

NO

- . en
en

\I")
NO

26

44
27

"'.r., f.f.r.

43

~1·1

'.f.r.r...f.r.,
".
. OJ'" ...,.1·'·'.f,J.f-',l.l.l.'-'.1.1·

M.-b-----------~~~_+~I

""""!::
""""0

(CP-68)

64 Pin

(Scale 3/2)
2.9max
O.114max

64-_,-_ _

\\ 0 IS
---to.

006 )

...,6aaaaaababaaabaaaaayoo _ 15

~O.067)

0

(FP-64)

Note) Inch value indicated for you reference.

133

~l~'"\'~,,)l~t~,,)l~t~,,)l~\~,,)l~\~ll~'~

~~ APPENDIX ~~

~t~l~t~l~')t~l~t~l~t~ll~t~l~

134

A. Instruction Set
The followings explain the symbols in instruction set.
1. Register
g, g', ww, xx, yy, and zz specify a register to be used. g and g' specify an 8-bit register. ww, xx, yy, and zz specify a pair of 16-bit registers. The following tables show the
correspondence between symbols and registers.
g,g' Reg.
000 B
001
C
010 D
011
E
100 H
101
L
111 A

ww Reg.
00 BC
01 DE
10 HL
SP
11

xx
00
01
10
11

Reg.
BC
DE
IX
SP

yy
00
01
10
11

Reg.
BC
DE
IY
SP

zz
00
01
10
11

Reg.
BC
DE
HL

AF

NOTE: Suffixed Hand L to ww,xx,yy,zz (ex.wwH,IXL) indicate upper and lower 8-bit of the 16-bit register respectively.

2. Bit
b specifies a bit to be manipulated in the bit manipulation instruction. The following table shows the correspondence between b and bits.
b
000
001
010
011
100
101
110
111

Bit
0
1
2
3
4
5
6
7

3. Condition
f specifies the condition in program control instructions. The following shows
the correspondence between f and conditions.

135

f
000

Condition
non zero
zero
non carry
carry
PO parity odd
PE parity even
P sign plus
M sign minus

NZ
Z
NC
C

001
010
011
100
101
110
111

4. Restart Address
v specifies a restart address. The following table shows the correspondence between v and restart addresses.
v

Address

000
001
010
011
100
101
110
111

OOH
08H
10H
18H
20H
28H
30H
38H

5. Flag
The following symbols show the flag conditions.
· : not affected
t : affected
X : undefmed
S : set to 1
R : reset to 0
P : parity
V : overflow

136

6. Miscellaneous
(
(

)M

h

morn
mn
r
R
b-(
)M
b-gr
dorj
S
D

+

E9

data in the memory address
data in the 1/0 address
8-bit data
16-bit data
8-bit register
16-bit register
a content of bit b in the memory address
a content of bit b in the register gr
8-bit signed displacement
source addressing mode
destination addressing mode
AND operation
OR operation
EXCLUSIVE OR operation

137

1. Data Manipulation Instructions
(1) Arithmetic and Logical Instructions (8-bit)
Flag

Operation

name

Addressing

MNEMONICS

OP-code

Bytes

IMMED

ADD

ADD A.g

10000 9

ADD A.IHU

10000 110

ADOA.m

11000 110

<
ADD A. OX+d)

INO

REG

REGI

IMP

Operation

REL

2

7

6

4

1

0

S

Z

H PN N

C

V

R

t

V

R

1

Ar+m-Ar

t t t
t t t
1 t t

V

R

t

14

Ar+ OX+ dlM-Ar

1 1 1

V

R

1

3

14

Ar+ OV+dlM-Ar

t t t

V

R

t

1

4

Ar+gr+c-Ar

V

R

t

0

1

6

Ar+ IHUM+C-Ar

V

R

0

2

6

Ar+m+c-Ar

t t 1
t t t
t t t

V

R

t
t

S

0

3

14

Ar+ OX+d)M+C-Ar

1 1 1

V

R

t

S

0

3

14

Ar+ OV+ dlM+ c-Ar

t

t

t

V

R

t

t

S

P

R

R

t s
1 s

P

R

R

P

R

R

t s

P

R

R

S

0

1

4

Ar+gr-Ar

0

1

6

Ar+IHUM-Ar

0

2

6

S

0

3

S

0

0

S
S

>

m

11 011

EXT

States

101

10000 110

<
ADD A. OV+d)

>

d

11111

101

10000 110

<

-L

>

d

I

CN

(l)

ADC

ACe A.g

10001 9

ADC A.IHU

10001

110

ADC A.m

11001

110

ADC A. OX+d)

11011

101

10001

110

<

<
ACe A. OV+d)

10001

110

>

d

ANDg

10100 9

AND CHU

10100 110

ANDm

11 100 110

AND OX+d)

11011

m

!

>

d

101

<

S
S

>

m

11 111

<
AND

S

S
S
S

0

1

4

Ar· gr-Ar

0

1

6

Ar·IHUM-Ar

0

2

6

Ar· m-Ar

t
t
t

0

3

14

Ar· ax+dlM-Ar

1

>
101

S

10100 110

<

d

>
Ito be continued)

Flag
Operation

name

Addressing
MNEMONICS

OP-code

Bytes

IMMED
AND

AND OV+d)

11 111

EXT

IND

REG

REGI

S

101

IMP

Operation

7

6

4

2

1

0

S Z

H PN N

C

Ar· av+d)M--Ar

t

t

S

P

R

R

t
t

t
t
t

V

S

t

V

S

V

5

t
t

States

REl

3

14

0

1

4

Ar-gr

0

1

6

Ar- IHLlM

t
t

0

2

6

Ar-m

t t

S

0

3

14

Ar-OX+dlM

t

t t

V

5

t

5

0

3

14

Ar-OV+dlM

t t t

V

5

t

SID

1

3

Ai--Ar

1

4

gr-1--gr

1

10

3

18

0

10100 110

<
Compare

>

d

S

CPg

10 111 9

CP tHO

10111

110

CPm

11 111

110

CP (JX+d)

11 011

101

10111

110

<

<
CP OV+d)

m

d

>

11 111

101

10111

110

<

d

>

COMPlEMENT

CPt

00 101

111

DEC

DECg

OOg

101

DEC tHO

00 110 101

DEC O><+d)

11 011

S

>

~

CAl
CO

S

101

SID
SID
SID

00 110 101

<
DEC OV+dI

d

11 111

INC

d

OX+dlM-1--

5

t t t
t t t
t t t

V

5

V
V

S
S

t t t

V

S

(lX+dlM

>
101

SID

3

18

00 110 101

<

IHUM- 1--IHLlM

5

(lY+dlM-1-(lY+dlM

>

INCg

OOg

INC IHU

00 110 100

INC (JX+d)

11011

SID

100

101

00 110 100

SID
SID

1

4

1

10

(HLlM+ 1--IHUM

t
t

3

18

(JX+dlM+ 1--

t

gr+ 1--gr

t
t
t

t

V

R

t

V

R

t

V

R

OX+dlM
~-

Ito be continued)

Flag
Operation

AddnIssing

OP-code

MNEMONICS

Bytes

name
IMMEl)

<

INC
INC OY+d)

IND

REG

REGI

IMP

States

101

SID

3

18

00 110 100

<
MULT

MLTww

7

6

4

1

0

S

Z

H PN N

C

2

J J J

V

R

O-Ar-Ar

J J J

V

S

J

R

P

R

R

R

P

R

R

R

P

R

R

OV+dlM+1OV+dIM

>

d

11 101

Operation

REl

>

d

11 111

EXT

2

17

SID

2

6

0

1

4

Ar+gr-Ar

0

1

6

Ar+ IHLlM-Ar

0

2

6

Ar+m-Ar

J J
J J
J J

S

0

3

14

Ar + OX + dIM-Ar

J J

R

P

R

R

S

0

3

14

Ar+OY+dIM-Ar

J J

R

P

R

R

0

1

4

Ar-gr-Ar

S

1

6

Ar-IHWM-Ar

V

S

0

2

6

Ar-m-Ar

J J
J J J
J J J

V

0

V

S

J
J
J

0

3

14

Ar- OX+dIM-Ar

J J J

V

S

J

SID

101

wwHrX wwLr-WWR

01 ww1 100

NEGATE

NEG

11 101

101

01000 100
OR

S

ORg

10110 9

OR\HU

10110 110

ORm

11 110 110

<

~

S
S

>

m

~

o

OR OX+d)

11011

101

10110 110

<
OR OV+d)

>

d

11 111

101

10110 110

<
SUB

>

d

S

SUBg

10010 9

SUB IHU

10010 110

SUBm

11010110

<
SUB OX+d)

m

11011

S
S

-J

>
101

S

10010 110

<

d

>

(to be continued)

Flag

Operation

name

AddnIssing

MNEMONICS

OP-code

Bytes

IMMED EXT
SUB

SUB OY+d)

11 111

101

N>

REG

REG!

NP

States

REL

7

6

4

1

0

S

Z

H PN N

C

2

At- OY+dlM-At

1 1 1 v

S

1

4

Ar-gr-c-At
At- IHL1M-c-At

t 1 t v
1 1 t v

S

6

2

6

At-m-c-At

t t t

V

S

t
t
t

0

3

14

At- OX+dlM-c-At

1 1 1

V

S

1

0

3

14

At- OY+dlM-c-Ar

t t 1

V

S

t

2

7

Ar" gr

t t

S

P

R

R

2

10

At "CHUM

t t

S

P

R

R

3

9

Ar"m

1 I

s

P

R

R

R

0

3

14

0

1

0

1

0

S

S

S

Operation

10010 110

<
SUBC

sac A.g
sac A.IHU

10011 9
10011

110

sac A.m

11 011

110

<

sac A. OX+d)

......
~
......

101

10011

110

S

S

>

d

11 111 101

<

TST tHU

S

>

m

10011

TSTg

S

11011

<

sec A. OY+d)

TEST

>

d

110

>

d

11 101

101

OOg

100

11 101

101

S

S

00 110 100
TSTm

11 101

101

S

01 100 100

<
XOR

XORg

tHU

10101 9

S

10101

110

XORm

11 101

110

XOR OX+d)

11011

101

10101

110

XOR

<

<
'---------

>

m

m

d

S
S

0

1

4

At~ gr-At

t t

R

P

R

0

1

6

At E& IHLlM-At

R

P

R

R

0

2

6

At$m-At

I I
1 t

R

P

R

R

0

3

14

At EB OX + dIM-At

t t

R

P

R

R

>
S

>

--- - - - -

Ito be continued)

Flag

Operation

Addressing

Bytes

OP-code

MNEMONICS

States

Operation

7

6

4

1

0

S

Z

H PN N

C

t

t

R

R

name
IMMED
XOR

XOR (lV+d)

11111

101

10101

110

<

d

EXT

IND
S

REG

REGI

IMP
D

REl

3

14

Ar Eil (IV + d)M-Ar

2

P

R

>

~
I\)

(to be continued)

(2) Rotate and Shift Instructions
Flag

Operation
name

Addressing

MNEMONICS

Bytes

OP-code
IMMED

Rotate

RI.A

00 010 111

and

RLg

11 001 011

Shift
Data

EXT

IND

REG

REGI

IMP

SID

States

7

6

2

4

1

0

S Z H PN N C

~llllllliJ
Cbl_1IO

t t

R

P

R

t
t

13

t t

R

P

R

t

4

19

t t

R

P

R

t

4

19

t t

R

P

R

t

R

1

3

2

7

2

SID

SID

SID

Operation

REl

R

R

00 010 9

RLCHU

SID

11 001 011
00 010 110

Rl OX+d)

11 011

101

11 001

011

<

>

d

00 010 110

RL OV+dl

11 111

101

11 001 011

......

<

t>

>

d

00 010 110

RLCA

00 000 111

RlCg

11 001 011

SID

t

t

R

P

R

t
t

13

t

t

R

P

R

t

4

19

t

t

R

P

R

t

4

19

t

t

R

P

R

t

2

16

liUu t

t

R

P

R

1

3

2

7

2

SID

SID

SID

oJillllllllJ
Cbl_1IO

R

00 000 9

RLC CHU

SID

11001 011
00000 110

RLC OX+dl

11 011

101

11 001 011

<

d

>

00 000 110

RlC OV+dl

11 111

101

11 001 011

<

d

>

00000 110

RLD

11 101

101

SID

g~
bl

110

--------

(tobec:ontinuadl

Flag

Operation
name

Addrassing

MNEMONICS

OP-code

Bytes

IMMED
Rotate

01 101

111
111

and

RRA

00011

Shift

RRg

11001 011

Data

EXT

IN[)

REG

REGI

IMP

SID

States

Operation

REL

[jlllllll~
b7_bO C

2

7

6

4

1

0

S

Z

H PN N

C

R

t

t

R

P

R

t
t

1

3

2

7

2

13

t

t

R

P

R

t

SID

4

19

t

t

R

P

R

t

SID

4

19

t

t

R

P

R

t

t

t

R

P

R

t

SID

R

00 011 9

RR (HU
RR OX+d)

110

11011

101

11 001

011

<
RR OY+d)

SID

11 001 011
00011

d

>

00011

110

11 111

101

11001 011

......

d

>

00011

<

110

RRCA

00 001

111

RRC 9

11001 011

~
~

SID

1

3

2

7

2

13

t

t

R

P

R

t

SID

4

19

t

t

R

P

R

t

SID

4

19

t

t

R

P

R

1

SID

Cjlllllll~
b7_bO
C

R

Rt

00 001 9

RRC IHU
RRC OX+d)

SID

11 001 011
00 001

110

11011

101

11001 011

<
RRC OY+d)

d

>

00001

110

11 111

101

11001 011

d

>

00 001

<

110

ito be continued)

name

MNEMONICS

OP-code

Bytes

IMMED
Rotate

RRD

11 101

EXT

N>

REG

REGI

101

M"
SID

States

Operation

REl

2

16

SLAg

Data

11 001 011

SID

2

SLA CHU

~7

7

6

4

1

0

S

Z

H PN N

C

t

R

P

R

__

III

t

R

P

R

t

lHIJa. t

1-III

[H I I I I I I I

00 100 9

C

11 001 011

SID

_7

Reg

7

~7

01 100 111

and

Shift

_kl

AddnIssing

Operation

2

2

13

t

t

R

P

R

t

SID

4

19

I

t

R

P

R

I

SID

4

19

t

t

R

P

R

t

2

7

t

I

R

P

R

t

00 100 110

SLA OX+d)

11 011

101

11 001

011

<

>

d

00 100 110

SLA OY+d)

.....

11 111

101

11001 011

~

<

>

d

00 100 110

SRAg

11 001 011

SID

00 101 9

SRAtfl)

SRA OX+d)

qllTlii IIIIHJC
'7

11 001 011
00 101

110

11 011

101

SID

2

13

t t

R

P

R

I

SID

4

19

t t

R

P

R

t

SID

4

19

t I

R

P

R

I

2

7

t t

R

P

R

t

11001 011

d

>

00 101

110

11 111

101

<
SRA OY+d)

11 001 011

d

>

00 101

110

<
SRlg

11 001 011

SID

0-1.7II II II IIIIHJC

(tobec:ontinued)

-

Flag

Operation

Addressing
OP-code

MNEMONICS

Bytes

name
IMMED
Rotate
and

IND

REG

REGI

IMP

States

SRL (lX+d)

SRL (lY+d)

011

00 111

110

11011

101

11001

011

d

>

00 111

110

11111

101

11001

011

<

7

6

4

1

0

S

Z

H PN N

C

t

t

R

P

R

t

t

R

P

R

1

R

P

R

1

2

0-\ 1\ I II I I I..[]

11001

<

Operation

REL

00 111 9

SRL (HU

Shift
Data

EXT

d

>

00 111

110

SID

---

L

___

~

b7

bO

C

2

13

SID

4

19

t

SID

4

19

1 1

'-----

I

......
~

m

(to be continued)

(3) Bit Manipulation Instructions
Rag

Addressing

Operation
name

MNEMONICS

OP-code

Bytes
IMMED

Bit Set

SET b.g

11001

011

11 b

9

SET b. (HU

11001 011
11 b

SET b. (IX + d)

101

11001

011

SET b. (IV + d)
~

-...J

11111

101
011

RES b.g

RES b. (HU

RES b. (IX + d)

2

13

1-b' (HUM

SID

4

19

1-b' (lX+d)M

SID

4

19

1-b' OY+d)M

2

7

2

13

o-b' (HUM

SID

4

19

O-b' OX+d)M

SID

4

19

o-b' (IY+d)M

SID

10 b

9

11 001

011

10 b

110

11011

101

11001

011

d

11 001

<

0

S

Z

H PN N

C

1-b 'gr

SID

SID

o-b' gr

>
110

11 11 1 101

10 b

1

110

10 b

RES b. (lY+d)

REL

7

11001 011

<

IMP

2

SID

2

4

>

d

11 b

Bit Reset

REGI

6

110

11001

<

REG

7

>

d

11 b
~

IND

Operation

110

11011

<

EXT

States

d

011

>
110

(to be continued)

I

Flag
Operation

name

Addressing

MNEMONICS

OP-code

Bytes

IMMED

Bit Test

BIT b.g

BIT b. ax+d)

IN[)

REG

REG!

~

states

Operation

REl

7

6

4

1

0

S

Z

H PN N

C

2

2

6

b' gr-z

X

1 s

X

R

2

9

~""z

X

1

s

X

R

S

4

15

~z

X

1

s

X

R

S

4

15

b' OY+&;rz

X

t s

X

R

S

11 001 011
01 b

BlTb.OiU

EXT

g

S

11 001 011
01 b

110

11011

101

11 001 011

<
BIT b. OY+d)

d

>

01 b

110

11 111

101

11 001 011

<
~

~

01 b

d

>
110

CD

- - - - - - - -

(tobecontinuld)

(4) Arithmetic Instructions (16-bit)
Flag
Addressing

Operation
MNEMONICS

OP-code

Bytes

name
IMMED
ADD

IND

REG

REGI

IMP

00 ww1 001

S

0

1

7

ADDlX.xx

11011

101

S

0

2

00 xx1

001

S

0

S

ADCHL.ww

11111

101

00 yy1

001

11 101

101

Operation

REL

ADDHL.ww

ADD rf,vy

ADC

EXT

States

2

7

6

4

1

0

S

Z

H PN N

C

HLR+ WWR-HLR

X

R

10

IXA+ xXR-1XA

X

R

t
t

2

10

IYR+YYR-rfR

X

R

t

0

2

10

HLR+ WWR+ c-HLR

1

4

WWR-1-WWR

SID

2

7

1~-1-1~

SID

2

7

IYR-1-rfR

1

4

WWR+ 1-WWR

SID

2

7

1XA+1-1~

SID

2

7

IYR+1-IYR

0

2

10

t t

X

V

R

t

t t

X

V

S

t

01 ww1 010
DEC
~

DECww

90 ww1

011

DEC IX

11011

101

~

co

SID

00 101 011
DECrf

11111

101

00 101 011
INC

INCww

OOWWO 011

INC IX

11011

SID

101

00100011
INCIY

11111

101

00100011

SBC
L-_ _ _

SBCHL.ww

11 101

S

101

01 wwO 010
----

_L--....

_

----L...--..

--

L...--

- -

HLR- WWR- c-HLR

- - - - - .. - - - - I . . . . .

----

(to be continuedl

2. Data Transfer Instructions
(1) 8-Bit Load
Operation

name

Addr8ssing

MNEMONICS

OP-code
IMMED

Load

LDA.J

LDA.R

REGI

101

..

Bytes

Statas

Operation

REl

2

1

7

6

4

S

Z

H PN N

SID

2

6

Ir-Ar

t

t

R 92 R

SID

2

6

Rr-Ar

t

t

R 92 R

CBC),rAr

0

C'

111

LD A. CBC)

00 001 010

S

0

1

6

LD A. O)E)

00 011 010

S

0

1

6

U>ElM-Ar

LD A. (mn)

00 111 010

0

3

12

ImnlM-Ar

SID

2

6

Ar-Ir

SID

2

6

Ar-Rr
Ar-CBClM

<
<
LDI,A

>
>

n

m

11 101

S

101

01000 111

~

01

REG

11 101 101
01011

o

N)

01010 111

&-bit

Data

11 101

EXT

Flag

LD R.A

11 101

101

01001

111

LD CBC).A

00 000 010

0

S

1

7

LD CDEl.A

00 010 010

0

S

1

7

Ar-1OElM

LD fmnl.A

00 110 010

S

3

13

Ar-fmnlM

<
<

>
>

n

m

SID

LD go9'

01 9

g'

LD g,lHU

01 9

110

LDg.m

oog

110

LD 9. OX+d)

11 011

101

01 9

110

<

<
LD 9. OY+dl

m

d

0

1

4

1

6

lHi.lM-gr

0

2

6

m-gr

S

0

3

14

OX+dlrrgr

S

0

3

14

OY+dlM-gr

0
S

S

gr'-gr

>

>

11 111

101

01 9

110
(tobecontinuedl

Rag
Addressing

Operation
name

MNEMONICS

OP-code

Bytes

IMMED

<

Load

a-bit

LD IHU,m

LD OX+d),m

REG

REGI

IMP

States

Operation

REl

7

6

4

1

0

S

Z

H PN N

C

2

0

S

2

9

m-(HUM

>

m

11011

INO

>

d

00 110 110

<

Data

EXT

101

S

0

4

15

m-OX+d)M

S

0

4

15

m-(IY+dlM

00 110 110

<
<
LD (IY+d),m

>
>

d
m

11111

101

00 110 110

<
<
01
.......

>
>

d
m

LD (HU,g

01 110 g

LD (lX+dl.g

11011

S

101

0

1

7

0

S

3

15

gr-OX+d)M

0

S

3

15

gr-OY+d)M

gr-(HUM

01 110 g

<
LD (lY+d),g

>

d

11111

101

01 110 g

<

d

>

(to be continued)

(2) 16-Bit Load
Flag

Addressing

Operation

name

MNEMONICS

OP-code

Bytes

IMMED
load

LD_.mn

00-0001

<
<

16-bit

Data
LDlX.mn

n

m

EXT

IN[)

REG

REGI

MP

0

S

states

Operation

RB.

3

9

7

6

4

1

0

S

Z

H PN N

C

2

mn-WWR

>
>

11011 101

S

0

4

12

mn-iXA

S

0

4

12

mn-IVR

00 100 001

<
<
LD IV. mn

n

m

>
>

11 111 101
00 100 001

<
<
...a.
01
I\)

n

m

>
>

LD SP. Hl

11 111 001

SID

1

4

HL..-SPR

LD SP.IX

11 011 101

SID

2

7

~-SPR

SID

2

7

IVR-SPR

4

18

11 111 001
LD SP.IV

11 111 101
11 111 001

LD _. (mn)

11 101 101

S

0

01 _1 011

<
<
LD

Hl.1mnI

ImnI

m

n

m

ImnIM-wwlr

>
>

00 101 010

<
<
LD IX.

n

S

3

0

15

>
>

11 011 101

n
m

1mn+11u-Hr

ImnIu-lr
S

4

0

18

00 101 010

<
<

Imn+ 1tM-wwHr

Cmn+ 11u-IXHr

1mn/u-1Xlr

>
>
-1---

-~

- -

(tobecontirudl

Flag
Addressing

Operation
MNEMONICS

OP-code

Bytes

name
IMMEO
Load

11111

101

16 bit

LD IV. (mnl

00 101

010

Data

<
<
LD (mnl.ww

n
m

11101

EXT

INO

REG

S

REGI

IMP

0

States

4

18

LD Imnl.HL

LD (mnl.1X

m

n
m

11011

101

0

4

S

19

LD (mnl.1V

n
m

11 111

n

<

m

1

0

H PN N

C

2

(mn+ 1)M-+IVHr

wwHr--(mn+ 1)M
wwLr--(mn)M

0

S

3

16

>
>
101

Hr--(mn+ 1)M
Lr--(mn)M

0

S

4

19

IXHr-- (mn+ 1)M
1XLr--(mnlM

>
>
101

00 100 010

<

4

Z

>
>

00 100 010

<
<

6

>
>

00 100 010

<
<

......
01
CAl

n

7
S

ImnlM-+IYLr

01 wwO 011

<
<

Operation

REl

0

S

4

19

IYHr--(mn+ 11M
IYLr-- (mnlM

>
>
(to be continued)

(3) Block Transfer
Flag
Operation

name

Addressing

MNEMONICS

OP-code

Bytes

IMMED

EXT

INC

REG

REG!

IMP

S

S

states

Operation

REL

7

6

4

1

0

S

Z

H PN N

C

a>

Block
Transfer

CPO

s.ch

11 101

101

2

12

Ar-1JiUM

10101 001

I

a>

HL.,.-1--Hlt!
11 101

101

(i)
I

I

S

ac,.- 1--ac,.

Data
CPOR

I

2

S

S

2

10111 001

14

ac,.*0 Ar*CHWM

12

ac,.= 0 or Ar= CHI..lM
a

I

I

(i)
I

I

S

[k-_

BCtI-1--ac,.

HL.,.- 1--Hlt!
Repeat a until

a>

Ar= IJiUM or BC,t= 0
CPt
...a.

0"1

11 101

101

S

S

2

12

I

I

I



PN=O: BCtI-1=0
PN= 1 : BCtI- 1*0
Z= 1 : Ar= CHUM
Z=O: Ar*1HLlM

(to be continued)

Rag
Addressing

Operation
MNEMONICS

OP-code

name
IMMED
Block

LDDR

Transfer

11 101

101

10111

000

EXT

IND

REG

REGI
SID

IMP

Bytes

States

2

14(BCR*'0)

Operation

REL

12(B~=0)

a

[~U~_

7

6

4

1

0

S

Z

H PN N

C

R

D~-1-D~

Data

HlR-1-HlR
Repeat

101

SID

2

12

10100 000

R

a until
G)

B~=O

11 101

R

B~-1-BCR

Search

LOI

2

(HUM-IDElM

R

t

R

R

R

R

BCR-1-B~

D~+1-D~

HlR+1-HlR
LOIR

01
01

11 101

101

10110000

SID

2

14(BCR*'0)
12(B~=0)

a

[~U~_
BCR-1-BCR
D~+1-D~

HlR+ 1-HlR
Repeat

a until

BCR=O

(i)

PN=0:B~-1=0

PN=1 :

B~-1*,0

(to be continued)

(4) Stack and Exchange
!

Rag

Operation

Addressing

MNEMONICS

OP-code

Bytes

name

IMMED
PUSH

PUSH zz

11 zzO

101

EXT

IND

REG
S

REGI

IMP
D

States

Operation

REl
1

11

2

1

7

6

4

S

Z

H PN N

O!

C

zzLr-(SP- 21M
zzHr-ISP-1)M
SPR-2..... SPR

PUSH IX

11011

101

SID

2

14

11 100 101

IXI.r-+ISP- 21M
IXHr-(SP- 11M
SPR-2..... SPR

PUSH IV

11111

101

SID

2

14

11 100 101

1VLr-(SP- 21M
IYHr-(SP-1IM
SPR-2.....SPR

POP

POP zz

11 zzO

001

D

S

1

9

(SP+ 1l~zzHr
(SPIM.....zzLr
SPR+2.....SPR

~

01

POP IX

m

11011

101

SID

2

12

11 100 001

(SP+ 1IM..... IXHr
(SPIM..... IXLr
SPR+2..... SPR

POP IV

11111

101

SID

2

12

11 100 001

(SP+ 1IM..... IVHr
(SPIM-IVLr
SPR+2..... SPR

Exchange

EX Af.Af'

00 001

000

SID

1

4

AFR-AfR'

EX DE.HL

11 101

011

SID

1

3

DfR-H4I

EXX

11011 001

SID

1

3

B~-BCR'

DfR-DER'
H4I-H4I'
EX (SPI,HL

11 100 011

SID

1

16

Hr-(SP+llM

EX (SPI,IX

11011

SID

2

19

IXHr-(SP+ 11M

Lr-(SPIM
101

11 100 011

IXLr-(SPIM
(to be continued)

Flag

Operation

Addressing

MNEMONICS

OP-code

Bytes

States

2

19

name
IMMED
Exchange

EX (SP),IY

11111

101

EXT

INO

REG

REGI

IMP
SID

Operation

REl

2

7

6

4

1

0

S

Z

H PN N

C

IYH...-(SP+ 11M
1Ylr-(SP)M

11 100 011

~

0'1

......

----

'--------

(to be continued)

3. Program Control Instructions
Rag
Operation

Addressing

OP-code

MNEMONICS

Bytes

name

IMMED
Call

CAllmn

11001

<
<

n
m

101

EXT

NO

REG

REGI

IMP

States

Operation

REl
3

0

16

>
>

7

6

4

1

0

S

Z

H PN N

2

C

PCHr-ISP-1IM
PCLr-(SP- 21M
mn-PCt!
SPR-2-SPR

CAll f. mn

<
<
Jump

OJNZ j

100

11 f
n
m

3

0

>
>

16" : tnJeI

00 010 000

<

j-2

6" : falsel

0

>

2

9 (Br:;=OI

2

7(Br=01

continue:f is false

CAll mn:f is tJUe

Br-1-Br

~

C11

(X)

continue:Br= 0
PCR+ j-+PCt!:Br:;=O
JP f. mn

11 f

<
<

010
n
m

0

>
>

3

6 (f :falsel

3

9 (f : tJUel
mn-PCt!:f is tJUe
continue:f is false

JPmn

11000 011

<
<

n
m

0

3

9

mn-PCt!

>
>

JP IHU

11 101 001

0

1

3

HLR-PCt!

JPOX)

11011

101

0

2

6

1>4I-PCt!

JPOVI

11111

0

2

6

IYR-PCt!

11 101 001
101

11 101 001

(to be

continuedl

Rag

Addressing

Operation
MNEMONICS

OP-code

name

IMMED
Jump

JR j

00 011

JR C,j

00111000

<
<
JR NC,j

JR NZ,j

RET

REGI

IMP

000

11001

2

8

P4I+j-P4I

D

2

6

continue: C=O

2

8

PCR+ j-PCR: C= 1

D

D

>

00 100 000
j-2

D

Operation

REL

>

00 101
j-2

States

7

6

4

1

0

S

Z

H PN N

C

2

>

>

<
Return

REG

000

j-2

<

0'1
<0

j-2

IND

00 110 000

<
JR Z,j

j-2

EXT

Bytes

D

>
001

D

2

6

continue: C=l

2

8

P4I+ j-PCR: c=o

2

6

continue: Z= 0

2

8

P4I+ j-P4I: Z= 1

2

6

continue: Z=l

2

8

P4I+ j-P4I: Z=O

1

9

(SP)M-PCLr
(SP+ 1)M-PCHr
SPR+2-SPR

RET f

RETI

11 f

000

11 101

101

01001

101

D

D

1

5(f :false)

continue:f is false

1

10(f :true)

RET: f is true

2

12

(SP)~PCLr

(SP+ 1)M-PCHr
SPR+2-SPR
I
I

RETN

11 101

101

01 000 101

D

2

12

(SP)~PCLr

(SP+ llM-PCHr
SPR+2-SPR
IEF2-IEF,
I

(to be continued)

Flag

Addressing

Operation
MNEMONICS

Bytes

OP-code

States

Operation

7

6

4

1

0

S

Z

H PN N

C

2

name
MMED

Restart

RSTv

11 v

111

EXT

INO

REG

REGI

IMP

REL

1

0

11

PCHr--(SP-llM
PCLr-ISP- 21M
o-PCHr
v--+PCLr
SPR-2--SPR

......
0>

o

I

L-

(to be continuedl

4. I/O Instructions
Flag

Addressing

Operation
MNEMONICS

OP-code

Bytes

name
IMMED
INPUT

IN A.(ml

11011

<

m

EXT

IND

REG

REGI

011

IMP

10

D

S

2

Operation

States

9

>

7

6

4

1

0

S

Z

H PN N

C

2

(Amlr-Ar
m-Ao-A7
Ar-Ae-A'5

INg,(CI

11 101

101

01 9

000

D

S

2

9

tBClr-gr

t t

R

P

R

t t

R

P

R

g= 110: Only the
flags will

change.
Cr-Ao-A7
Br--Ae-A'5

!NO g,(ml

11101

101

oog

000

<

m

D

S

3

12

(OOm)r-gr
g= 110: Only the

>

flags win

change.

(J)
~

m-Ao-A7

@

OO-Ae-A'5
IND

11 101

101

D

S

2

12

10101 010

tBCl,-(HUM

@)

X

t

X

X

X

S

X

X

t

X

H'-R-l-H'-R
Br-l-Br
Cr-Ao-A7

@)

Br--Ae-A'5

IIIDR

11 101

101

10111 010

D

S

2

14(8'*01
12(Br=01

Q

[~H'-R-l-H'-R

t

X

Br-l-Br
Repeat Q until
Br=O
Cr-Ao-A7
Br--Ae-A'5

-

(to be continuedl

@
@)

Z=l : Br-l=O
Z=O: Br-l*O
N= 1 : MSB of Data= 1
N=O : MSB of Data=O

Flag

Addressing

Operation

MNEMONICS

OP-code

Bytes

name
IMMEO

EXT

INO

REG

REGI

IMP

Operation

States

10

7

6

4

1

0

S

Z

H PN N

C

2

X

1

X

X

@)
1

X

X

S

X

X

@)
1

X

®

INPUT
INI

11 101

101

0

S

2

12

10100 010

(BCII-IHUM
H4I+1-H4I
Br-1-Br
Cr-Ao-A7
Br-Aa-A'5

INIR

11 101

101

10110 010

0

S

2

14(Br*0)

12(Br=0)

Q

[~H4I+1-H4I
Br-1-Br

Repeat Q until
Br=0
0)
I\)

Cr-Ao-A7
Br-Aa-A'5

® Z=1
@)

: Br-1=0
Z=0:Br-1;t::0
N= 1 : MSB of Oata= 1
N= 0 : MSB of Oata= 0
(to be continued)

Flag

Addressing

Operation

name

MNEMONICS

OP-code
IMMEO

OUTPUT

OUT (m).A

EXT

INO

REG

REGI

11010 011

<

m

IMP

10

S

0

Bytes

States

2

10

>

Operation

2

7

6

4

1

0

S

Z

H PN N

C

Ar-(Am),

m-Ao-A7
A..-Aa-A15

OUT (C),g

11 101

101

01 9

001

11 101

101

OOg

001

0

S

2

10

g"-(BC~

C..-Ao-A7
Br-Aa-A15

OUTO (m),g

<
OTDM

m

11101

0

S

3

13

m-Ao-A7

>
101

g..-(OOm),

S

0

2

14

10001 011

OO-Aa-A15

@

(HUM-(OOC),

1 1 1

P

R

S

@
1 1

H~-1-H~

Cr-1-Cr

0>
W

Br-1-Br
C..-Ao-A7

@

OO-Aa-A15
OTDMR

11 101

101

10011 011

S

0

2

16(Br*0)
14(Br=0)

a

[~~I'

S

R

1

R

H~-1-H~

Cr-1-Cr
Br-1-Br
Repeat

a until

Br=0
C..-Ao-A7
OO-Aa-A15

® Z=1
@

: Br-1=0
Z=O: Br-1*0
N= 1 : MSB of Oata= 1
N= 0 : MSB of Oata= 0
(to be continued)

Flag

Operation

name

Addressing
MNEMONICS

OP-code

OUTPUT

OTIIII

11101

101

EXT

INO

REG

REG!

S

IMP

Operation

States

Bytes

IMMED

10

0

2

14

10000 011

IHU~(ODC)I

7

6

4

1

0

S

Z

H PN N

2

C

@
1 1 1

P

t

1

R

R

S

@
1

R

x

x

@

HlR+1--+HlR
Cr+ 1--+Cr
Br-1--+Br
Cr--Ao-A1
OO--As-A15

OTIIIIR

11 101

101

S

0

2

161Br*0)
14(Br=0)

10010 011

a [~OOQ
HlR+ 1--+HlR

S

Cr+ 1--+Cr
Br-1--+Br
Repeat

a unti

Br=0

~

Cr--Ao-A1
OO--Aa-A15

OUTO

11 101

101

S

0

12

2

10101 011

@

IHUM-+(BCh
HlR-1-HlR

X

t

@
t

X

Br-1--+Br
Cr--Ao-A1
Br-As-A15

-

-

® Z=1 : Br-1=0
@

Z=O: Br-1*0
N=1 : MSB of Oata=1
N= 0 : MSB of Oata=O
(to be continued)

Flag
Operation

name

Addressing

OP-code

MNEMONICS

Bytes

IMMED

EXT

IND

REG

REGI

IMP

Operation

States

10

7

6

4

1

0

S

Z

H PN N

C

X

S

X

X

t

X

X

S

X

X

1

X

1 1

S

P

R

R

2

@
OUTPUT

OTOR

11 101

101

S

D

2

10111 011

141Br*0)
12(Br=0)

[~~~
Q
H41- 1..... H41

1

X

Br-1 ..... Br
Repeat Q until
Br=O

Cr--Ao-A7
Br-Aa-A'5
OUTI

11 101

S

101

D

2

12

10100 011

(HU~(BC)I

X

®

@
1

X

H41+ 1..... H41
Br-1 ..... Br

0)

Cr--Ao-A7

01

@

Br--Aa-A'5
OTIR

11101

S

101

D

2

14(Br*,0)
12(Br=0)

10110 011

Q

[~~~
H41+ 1.....H41

X

Br-1 ..... Br
Repeat Q until
Br=0

Cr--Ao-A7
Br-Aa-A'5
TSTIO m

11 101

101

S

S

3

12

(OOC)lom

01 110 100

Cr--Ao-A7

<

OO-+Aa-A'5

m

>

@
@

Z=1 : Br-1=0
Z=O: Br-1*,0
N=1 : MSB of Data=1
N= 0 : MSB of Data= 0

Ito be continued)

5. Special Control Instructions
Flag
MNEMONICS

name

OP-code

Bytes

IMMED
Special

I

Addressing

Operation

OAA

00 100 111

EXT

INO

REG

REGI

IMP
SID

Operation

States

REL
1

4

7

6

4

S

Z

H PN N

1 1 t

Deemal

2

1

01

C

1

P

Adjust

Function

Accumulator
111

1

3

C c

R

R

1

R

R

S

Cany

CCF

00 111

Control

SCF

00 110 111

1

3

, ..... c

CPU

DI

11 110 011

1

3

0-+1EF1.0-+1EF2

Control

8

11 111

1

3

1.....IEFI. 1.....EF2

HALT

01 110 110

1

3

CPU halted

IMO

11 101

2

6

Intenupt

2

6

Interrupt

2

6

Intenupt

00 000 000

1

3

No operation

11 101

2

8

Sleep

011

101

mode 0

01000 110
WIll 1
...L

101

mode 1

01010 110

m

m

11 101

M2

NOP
SLP

11 101

101

01 011

110

101

®
®

mode 2

01 110 110

@

Interrupts are not sampled at the end of 01 or 8.

i

B. Instruction Summary in Alphabetical Order
MNEMONICS

Bytes

Machine Cycles

States

ADC A,m

2

2

6

ADC A,g

1

2

4

ADC A, (HL)

1

2

6

ADC A, (lX+d)

3

6

14

ADC A, (lY+d)

3

6

14

ADD A,m

2

2

6

ADD A,g

1

2

4

ADD A, (HL)

1

2

6

ADD A, (lX+d)

3

6

14

ADD A, (lY+d)

3

6

14

ADC HL,ww

2

6

10

ADD HL,ww

1

5

7

ADD IX,xx

2

6

10

ADD IY,yy

2

6

10

ANDm

2

2

6

AND 9

1

2

4

AND (HL)

1

2

6

AND (lX+d)

3

6

14

AND (lY+d)

3

6

14

BIT b, (HL)

2

3

9

BIT b, (lX+d)

4

5

15

BIT b, (lY+d)

4

5

15

BIT b,g

2

2

6

CALL f,mn

3

2

6
(If condition is false)

6

3

16
(If condition is true)
(to be continued)

167

MNEMONICS

Bytes

States

Machine Cycles

CALL mn

3

6

16

CCF

1

1

3

CPO

2

6

12

CPDR

2

8

14
(If BCR*O and Ar*(HUMl

2

12

6

(If BC R= 0 or Ar= (HUM)

CP (HL)

1

2

6

CPI

2

6

12

CPIR

2

8

14
(If BCR*O and Ar*(HL)M)

2

12

6

(If BC R= 0 or Ar= (HUM)

CP (lX+d)

3

6

14

CP (lY+d)

3

6

14

CPL

1

1

3

CPm

2

2

6

CP 9

1

2

4

DAA

1

2

4

DEC (HL)

1

4

10

DEC IX

2

3

DECIY

2

3

7

DEC (lX+d)

3

8

18

DEC (lY+d)

3

8

18

DEC 9

1

2

4

DEC ww

1

2

4

01

1

1

3

I

7

(to be continued)

168

MNEMONICS

Bytes

Machine Cycles

States

2

5

9 (If Br*O)

2

3

7 (If Br=O)

EI

1

1

3

EX AF,AF'

1

2

4

EX OE,HL

1

1

3

EX (SP),HL

1

6

16

EX (SP),IX

2

7

19

EX (SP),IY

2

7

19

EXX

1

1

3

HALT

1

1

3

IMO

2

2

6

1M 1

2

2

6

1M 2

2

2

6

INC 9

1

2

4

INC (HL)

1

4

10

INC (lX+d)

3

8

18

INC (lY+d)

3

8

18

INCww

1

2

4

INC IX

2

3

7

INC IY

2

3

7

INA,(m)

2

3

9

IN g,(C)

2

3

9

INI

2

4

12

INIR

2

6

14 (If Br*O)

2

4

12 (If Br=O)

INO

2

4

12

INOR

2

6

14 (If Br*O)

OJNZ j

(to be continued)

169

MNEMONICS

Bytes

Machine Cycles

States

INOR

2

4

12 Of Br=O)

INO g,(m)

3

4

12

JP f,mn

3

2

6
Of f is false)

3

3

9
Of f is true)

JP (HL)

1

1

3

JP (IX)

2

2

6

JP (ly)

2

2

6

JP mn

3

3

9

JR j

2

4

8

2

2

6

JR C,j

I

(If condition is false)
2

4

8
Of condition is true)

JR NC,j

2

2

6
(If condition is false)

2

4

8
Of condition is true)

JR Z,j

2

2

6
. (If condition is false)

2

4

8
(If condition is true)

JR NZ,j

2

2

6
(If condition is false)

2

4

8
(If condition is true)
(to be continued)

170

Bytes

Machine Cycles

States

LD A, (BC)

1

2

6

LD A, (DE)

1

2

6

LDA,I

2

2

6

LD A, (mn)

3

4

12

LDA,R

2

2

6

LD (BC),A

1

3

7

LDD

2

4

12

LD (DE),A

1

3

7

LD wW,mn

3

3

9

LD ww,(mn)

4

6

18

LDDR

2

6

14 (If BCR=1=O)

2

4

12 (If BCR=O)

LD (HL),m

2

3

9

LD HL,(mn)

3

5

15

LD (HL),g

1

3

7

LDI

2

4

12

LD I,A

2

2

6

LDIR

2

6

14 (If BC R=1=O)

2

4

12 (If BCR=O)

LD IX,mn

4

4

12

LD IX,(mn)

4

6

18

LD (lX+d),m

4

5

15

LD (lX+d),g

3

7

15

LD IY,mn

4

4

12

LD IY,(mn)

4

6

18

LD (lY+d),m

4

5

15

LD (lY+d),g

3

7

15

MNEMONICS

(to be continued)

171

MNEMONICS

Machine Cycles

Bytes

States

LD (mn),A

3

5

13

LD (mn),ww

4

7

19

LD (mn),HL

3

6

16

LD (mn),IX

4

7

19

LD (mn),IV

4

7

19

LD R,A

2

2

6

LD g,(HL)

1

2

6

LD g,(lX+d)

3

6

14

LD g,(lV+d)

3

6

14

LD g,m

2

2

6

LD g,g'

1

2

4

LD SP,HL

1

2

4

LD SP,IX

2

3

7

LD SP,IV

2

3

7

MLTww

2

13

17

NEG

2

2

6

NOP

1

1

3

OR (HL)

1

2

6

OR (lX+d)

3

6

14

OR (lY+d)

3

6

14

ORm

2

2.

6

)

OR 9

1

2

4

OTDM

2

6

14

OTDMR

2

8

16 (If Br*O)

2

6

14 (If Br=O)

2

6

14 (If Br*O)

2

4

12 (If Br:::::O)

OTDR

Ito be continued)

172

States

Bytes

Machine Cycles

OTIM

2

6

14

OTIMR

2

8

16 (If Br::f:O)

2

6

14 (If Br=O)

2

6

14 (If Br::f:O)

2

4

12 (If Br=O)

OUTO

2

4

12

OUTI

2

4

12

OUT (m),A

2

4

10

OUT (C),g

2

4

10

OUTO (m),g

3

5

13

POP IX

2

4

12

POP IY

2

4

12

POP zz

1

3

9

PUSH IX

2

6

14

PUSHIY

2

6

14

PUSH zz

1

5

11

RES b,(HL)

2

5

13

RES b,(lX+d)

4

7

19

RES b,(lY+d)

4

7

19

RES b,g

2

3

7

RET

1

3

9

RET f

1

3

5

MNEMONICS

OTIR

(If condition is false)
4

1

10
(If condition is true)

RETI

2

4

12

RETN

2

4

12
(to be continued)

173

Sytes

Machine Cycles

States

RLA

1

1.

3

RLCA

1

1

3

RLC (HL)

2

5

13

RLC (lX+d)

4

7

19

RLC (lY+d)

4

7

19

RLC 9

2

3

7

RLD

2

8

16

RL (HL)

2

5

13

RL (lX+d)

4

7

19

RL (lY+d)

4

7

19

RL 9

2

3

7

RRA

1

1

3

RRCA

1

1

3

RRC (HL)

2

5

13

RRC (lX+d)

4

7

19

RRC (lY+d)

4

7

19

RRC 9

2

3

7

RRD

2

8

16

RR (HL)

2

5

13

RR (lX+d)

4

7

19

RR (lY+d)

4

7

19

RR 9

2

3

7

RST v

1

5

11

SSC A,(HL)

1

2

6

SSC A,(lX+d)

3

6

14

SSC A,(lY+d)

3

6

14

SSC A,m

2

2

6

MNEMONICS

(to be continued)

174

MNEMONICS

Bytes

Machine Cycles

States

sec A,g
sec HL,ww

1

2

4

2

6

10

SCF

1

1

3

SET b,(HL)

2

5

13

SET b,(lX+d)

4

7

19

SET b,(lY+d)

4

7

19

SET b,g

2

3

7

SLA(HL)

2

5

13

SLA (lX+d)

4

7

19

SLA (lY+d)

4

7

19

SLA 9

2

3

7

SLP

2

2

8

SRA(HL)

2

5

13

SRA (lX+d)

4

7

19

SRA (lY+d)

4

7

19

SRA 9

2

3

7

SRL (HL)

2

5

13

SRL (lX+d)

4

7

19

SRL (lY+d)

4

7

19

SRL 9

2

3

7

SUB(HL)

1

2

6

SUB (lX+d)

3

6

14

SUB (lY+d)

3

6

14

SUB m

2

2

6

SUB 9

1

2

4

TSTIO m

3

4

12

TSTg

2

3

7
(to be continued)

175

MNEMONICS

Bytes

Machine Cycles

States

TSTm

3

3

9

TST (HL)

2

4

10

XOR (HL)

1

2

6

XOR (IX + d)

3

6

14

XOR (lY+d)

3

6

14

XORm

2

2

6

XORg

1

2

4

(to be continued)

176

C. Op-code Map
Table 1 1st op-code map
Instruction format : XX
ww(LO=ALL)
DE
SP
HL
g (LO=0-7)
(HL)
(HL)
B
0
H
B
0
H
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011
1
0
4
5
3
6
7
9
A
2
8
B
NOP DJNZj JR NZ,j JRNO,j
NOTE1)
LD wW,mn
LD(ww), A LD(rm) LD(mn)
,HL
,A
INO ww
LD g,s
ADD A SUB S AND 8 OR S
INO g
,8
: NOTE1)
DEO g
: NOTE1)
LD g,m
: NOTEI)
~~T[2I ~~T[21 NOTE2) =NQ$)
RLOA RLA DAA SOF
EXAF,AP JR j JR Z, j JR O,j
ADD HL, ww
LD A, (ww) LD HL, LD A:
BO

~
0000
LO

B

0
0

~

......

......

0001
0010

~

E
H
L
(HL)
A
B

CI)

0
0

0011
0100
0101
0110
0111
1000
1001
1010

E
H
L
(HL)
A

1011
1100
1101
1110
1111

...J
...J



()
()
I

ACr.Antable
Not acceptable
• After BUS
RELEASE cycle.
DMA cycle
begins at the
end of one
MC.

Not acceptable

1

1

CD

"2Q)
:::s

()
I

Acceptable

CD

en

:i"
m
Q)
()

Acceptable
Retum from
SYSTEM STOP
mode to nonnal
operation.
Not acceptable

Interrupt

I

CD

Intemal

1/0

NOTE)·

SYSTEM STOP
mode

1

1

:::s"

o

";

CD

a.
:::s

CQ

Acceptable
Retum from
SYSTEM STOP
mode to normal
operation.

~

o

a.

CD

E-2. Request Priority

The HD64180 has the following three types of requests.
Type 1.

To be accepted in specified state ........... WAIT
Type 2.

To be accepted in each machine cycle ...... Refresh Req.
DMA Req.
Bus Req.
Type 3.

To be accepted in each instruction ....... ; . Interrupt Req.
Type 1, Type 2, and Type 3 requests priority is shown as follows.
highest priority Type 1 > Type 2 > Type 3 lowest priority
Each request priority in Type 2 is shown as follows.,
highest priority Bus Req. > Refresh Req. > DMA Req. lowest priority
(NOTE) If Bus Req. and Refresh Req. occurs simultaneously, Bus Req. is accepted but Refresh Req. is cleared.
Refer to "2.7 Interrupts" for each request priority in Type 3.

201

E-3. Operation Mode Transition

202

NOTE)

*1
*2

*3

NORMAL: CPU executes instructions normally in NORMAL mode.
OMA request: OMA is requested in the following cases.
(1) OREQo, OREQl = 0 (memory ~ (memory mapped) I/O OMA transfer)
(2) OEO = 1 (memory ~ memory OMA transfer)
OMA end: OMA ends in the following cases.
(1) OREOo, OREO 1
1 (memory ~ (memory mapped) I/O DMA transfer)
(2) BCRO, BCR 1 = OOOOH (all OMA transfers)
(3) NMI = 0 (all OMA transfers)

=

Other operation mode transitions
The following operation mode transitions are also possible.
OMA
1. HALT
•
REFRESH
BUS RELEASE

t

10STOP ...._ __

2.

SLEEP

J

OMA
REFRESH
BUS RELEASE

t

J

BUS RELEASE

SYSTEM STOP ~ BUS RELEASE

203

F-1. Status Signals
The following table shows pin outputs in each operating mode.
Mode

CPU
operation

1

0

A

IN

1

1

1

A

IN

RD

WR

REF

Op-code Fetch
(1 st op-code)

0

0

1

0

1

1

1

Op-code Fetch
(except 1st
op-code)

0

0

1

0

1

1

HALT BUSACK

Memory Read

1

0

1

0

1

1

1

1

1

A

IN

Memory Write

1

0

1

1

0

1

1

1

1

A

OUT

VO Read

1

1

0

0

1

1

1

1

1

A

IN

1/0 Write

1

1

0

1

0

1

1

1

1

A

OUT

Internal
Operation

1

1

1

1

1

1

1

1

1

A

IN

1

0

1

1

1

0

1

1

*

A

IN

NMI

0

0

1

0

1

1

1

1

0

A

IN

INTo

0

1

0

1

1

1

1

1

0

A

IN

INT1. INT2 &
Internal Interrupts

1

1

1

1

1

1

1

1

0

A

IN

1

Z

Z

Z

Z

1

1

0

*

Z

IN

0

0

1

0

1

1

0

1

0

A

IN

1

1

1

1

1

1

0

1

1

1

IN

Memory Read

1

0

1

0

1

1

1

1

0

A

IN

Memory Write

1

0

1

1

0

1

1

1

0

A

OUT

HALT
SLEEP

VO Read

1

1

0

0

1

1

1

1

0

A

IN

1/0 Write

1

1

0

1

0

1

1

1

0

A

OUT

1

1

1

1

1

1

1

1

1

Z

IN

RESET
NOTE) 1

: HIGH

o

: LOW

A
:
Z
:
IN
:
OUT:
:

Data
BUS

10E

BUS RELEASE

Internal
DMA

Address
BUS

ME

Refresh
nterrupt
AcknowledglC
Cycle
(1 st machine
cycle)

ST

LlR

Programmable
High Impedance
Input
Output
Invalid

204

F-2. Pin Status during RESET and Low Power Operation Modes
Pin No.

Symbol

Pin status in each operation mode

Pin function

RESET

SLEEP

10STOP

SYSTEM STOP

IN (N)

IN (N)

IN (A)

IN (N)

1

OUT

OUT

OUT

IN (N)

IN (A)

IN (A)

IN (A)

7

RESET

-

0

IN (A)

IN (A)

IN (A)

8

NMI

-

IN (N)

IN (A)

IN (A)

IN (A)

9

INTo

-

IN (N)

IN (A)

IN (A)

IN (A)

10

INTl

-

IN (N)

IN (A)

IN (A)

IN (A)

11

INT2

IN (N)

IN (A)

IN (A)

IN (A)

12

ST

-

1

1

OUT

1

Z

1

A

1

4

WAIT

5

BUSACK

6

BUSREO

13-30 Ao-A17
31

34-41
42

AlllTOUT

00-07
RTSo

43

CTSo

44

DCDo

45

TXAo

46

RXAo

47

CKAo/DREOo

48

TXAl

49

RXAl

50

CKA1ITENDo

51

TXS

52

RXS/CTSl

53

CKS

54

DREOl

55

TENDl

56

HALT

57

REF

58

10E

59

ME

60

E

61

UR

62

WR

63

RD

64

c!>

\

Al,l

Z

1

A

1

TOUT

Z

OUT

H

H

-

Z

Z

A

Z

1

H

OUT

H

IN (N)

IN (A)

IN (N)

IN (N)

IN (N)

IN (A)

IN (N)

IN (N)

1

OUT

H

H

IN (N)

IN (A)

IN (N)

IN (N)

CKAo
(intemal clock mode)

Z

OUT

Z

Z

CKAo
(extemal clock mode)

Z

IN (A)

IN (N)

IN (N)

DREOo

Z

IN (N)

IN (A)

IN (N)

-

1

OUT

H

H

IN (N)

IN (A)

IN (N)

IN (N)

CKAl
(intemal clock mode)

Z

OUT

Z

Z

CKAl
(extemal clock mode)

Z

IN (A)

IN (N)

IN (N)

TENDo

Z

1

OUT

1

-

1

OUT

H

H

RXS

IN (N)

IN (A)

IN (N)

IN (N)

CTSl

IN (N)

IN (A)

IN (N)

IN (N)

CKS
(internal clock mode)

Z

OUT

1

1

CKS
(extemal clock mode)

Z

IN (A)

Z

Z

-

IN (N)

IN (N)

IN (A)

IN (N)

1

1

OUT

1

1

0

OUT

0

1

1

OUT

1

1

1

OUT

' 1

OUT

1

1

1

0

E clock output

1

1

OUT

-

-

1

1

OUT

1

1

1

OUT

1

c!> clock output

1 : HIGH
0: LOW
A: Programmable
Z: High Impedance
IN (A): Input (Active)
IN (N): Input (Not active)
OUT: Output
H: Holds the previous state
- : same as the left

205

-

-

1

-

G. Internal I/O Registers
By programming lOA 7 and IOA6 in the I/O control register, internal I/O register addresses are relocatable within ranges from OOOOH to OOFFH in the 110 address
space.
REGISTER

I

MNEMONICS

ASCI Control Register A Channel 0
: CNTLAO

REMARKS

ADDRESS

o 0
MPE

bit

RE

TE

RTSO MPBRI MOD2 MODl MODO
EFR

during RESET
0
0
0
1
invalid
0
0
0
MN
~MN--~R-AN--r-MN--+-MN---rMN---+-RAN---rMN---+-MN--~

l

ASCI Control Register A Channel 1
: CNTLA1

o

L

MODE Selection
Multi Processor Bit Receive!
Error Flag Reset
Request To Send
'- Transmit Enable
' - Receive Enable
Multi Processor Enable

1
MPE

bit

RE

TE

CKA1D

MPBRI
MOD2 MODl MODO
EFR

during RESET

0

0

0

1

invarlCl

0

0

0

MN

MN

RAN

MN

MN

MN

RAN

MN

MN

I

LMODE Selection
LMulti Processor Bit Receive!

Error Flag Reset
- CKA 1 Disable
'-Transmit Enable
'- Receive Enable
'- Multi Processor Enable
MOD2, 1,0
000
001
010
o1 1
100
101
1 1 0
1 1 1

~SCI Control Register B Channel 0
: CNTLBO

o 2

Start
Start
Start
Start
Start
Start
Start
Start

+ 7 bit Data + 1 Stop
+ 7 bit Data + 2 Stop
+ 7 bit Data + Parity + 1 Stop
+ 7 bit Data + Parity + '2 Stop
+ 8 bit Data + 1 Stop
+ 8 bit Data + 2 Stop
+ 8 bit Data + Parity + 1 Stop
+ 8 bit Data + Parity + 2 Stop

MP

C'rS1

PEO

DR

SS2

SS1

SSO

bit

MPBT

during RESET

invarlCl

0

•

0

0

1

1

1

RAN

MN

RAN

MN

MN

MN

RAN

RAN

RAN

PS

l Clock Source and
Speed Select
Ratio
-Parity Even or Odd
- Clear To Send/Prescale
' - Multi Processor
I....Multi Processor Bit Transmit
~ Divide

• CTS : Depending on the condition of CTS Pin.
PS : Cleared to O.
(to be continued)

206

REGISTER

I MNEMONICS

ASCI Control Register B Channel 1
: CNTLB1

REMARKS

ADDRESS

o

3

CTS/
PS

bit

MPBT

during RESET

invalid

0

0

0

0

1

1

1

RIW

RIW

RIW

RIW

RIW

RIW

RIW

RIW

RIW

MP

PEO

DR

SS2

SS1

SSO

L Clock Source and
Speed Select
'-Divide Ratio
I- Parity Even or Odd
'- Clear To Send/Prescale
'- Multi Processor
-Multi Processor Bit Transmit
General
divide ratio
SS2.1.0

ASCI Status Register Channel 0
: STATO

o

4

PS=O
(divide ratio= 10)

PS=1
(divide ratio= 30)

DR=O (x 16) DR=1 (x64) DR=O (X 16) DR=1 (X64)

000
001
010
01 1
100
101
110

tIJ+
+
+

160
320
640
1280
+ 2560
+ 5120
+ 10240

11 1

External clock (frequency

640
tIJ+
+ 1280
+ 2560
+ 5120
+ 10240
+20480
+40960

<

tIJ+ 480
+
960
+ 1920
+ 3840
+ 7680
+15360
+30720
tIJ

tIJ+
+
+
+
+
+
+

1920
3840
7680
15360
30720
61440
122880

+40)

bit

RDRF

OVRN

PE

FE

RIE

0

0

0

0

0

.

..

TIE

during RESET
RIW

R

R

R

R

RIW

R

R

RIW

DCDO TORE

0

I .

Transmit
Interrupt
Enable
Transmit Data
Register Empty
- Data Carrier Detect
'-- Receive Interrupt Enable
L - Framing Error
L-Parity Error
•• C'fSo Pin I TDRE
L-. Over Run Error
L
1
' - Receive Data Register Full
• DCDo : Depending on the condition of i'5CDci Pin.
H
0

I

IAscl Status Register Channel 1
: STAT1

o 5

bit

RDRF

OVRN

PE

FE

RIE

CTS 1E TORE

TIE

during RESET ~_0__+-_0__+-_0__~;_0__~_O__~_O
__~__
1__~~O~
RIW

R

R

R

R

RIWRIW

R

RIW

T!anSmit
Interrupt
Enable
Transmit Data
Register Empty
L - CTS 1 Enable
I- Receive Interrupt Enable
I-FramingError
L - Parity Error
'- Over Run Error
L.... Receive Data Register Full

(to be continued)

207

REGISTER

I MNEMONICS

ASCI Transmit Data Register Channel

o

ADDRESS

REMARKS

0 6

: TORO
ASCI Transmit Data Register Channel

0 7

1
: TOR1
ASCI Receive Data Register Channel

o

0 8

: TSRO
ASCI Receive Data Register Channel
1
: TSR1

0 9

CSVO Control Register

o

A

: CNTR

bit

EF

EIE

RE

TE

-

SS2

SS1

during RESET

0

0

0

0

1

1

1

1

RIW

R

RIW

RIW

RIW

RIW

RIW

RIW

It. . . . .

SSO

LSpeed Select

E.-

Receive Enable
- End Interrupt Enable
-End Flag
SS2,1,O

Baud Rate

000
001
010
011

o

CSVO Transmit/Receive Data
Register

SS2,1,O
100
101
110
11 1

t/J+ 20
+40
+80
+160

Baud Rate
t/J+ 320
+ 640
+1280
Extemal
(frequency < + 20)

B

: TRDR
Timer Data Register Channel OL
: TMDROL

0 C

Timer Data Register Channel OH
: TMDROH

0 D

Timer Reload Register Channel OL
: RLDROL

0 E

Timer Reload Register Channel OH
: RLDROH

0 F

Timer Control Register

1 0
: TCR

bit

TIF1

TIFO

TIE 1

TIEO

TOC1

TOCO

TDE1

TDEO

~--4----+--~~--+----r--~----+---~

during RESET 1--_0_1--0_-+-_0_-+-_0_-+-_0_-+-_0_-+-_0_-+-_0---1
RIW
R
R
RIW RIW RIW RIW RIW RIW

t=~==k=~==~~==~r===~

L

TUner Down
Count Enable 1,0
L - Timer Output Control 1,0
Timer Interrupt Enable 1,0 I
Timer Interrupt Flag 1,0

TOC1,O

00
01
10
11

A Is/TOUT

Inhibited
Toggle

o
1

(to be continued)

208

REGISTER

I MNEMONICS

ADDRESS

Timer Data Register Channel 1L
: TMDR1L

1 4

Timer Data Register Channel 1H
: TMDR1H

1 5

Timer Reload Register Channel 1L
: RLDR1L

1 6

Timer Reload Register Channel 1H
: RLDR1H

1 7

Free Running Counter

1 8

REMARKS

\

read only

: FRC
DMA Source Address Register
ChannelOL
: SAROL

2 0

DMA Source Address Register
ChannelOH
: SAROH

2 1

DMA Source Address Register
Channel 08
: SAROB

2 2

DMA Destination Address Register
ChannelOL
: DAROL

2 3

DMA Destination Address Register
ChannelOH
: DAROH

2 4

DMA Destination Address Register
ChannelOB
: DAROB

2 5

DMA Byte Count Register Channel
OL
: BCROL

2 6

DMA Byte Count Register Channel
OH
: BCROH

2 7

DMA Memory Address Register
ChannellL
: MAR1L

2 8

DMA Memory Address Register
ChannellH
: MAR1H

2 9

DMA Memory Address Register
ChannellB
: MAR1B

2 A

DMA 1/0 Address Register Channel
lL
: IAR1L

2 B

DMA VO Address Register Channel
lH
: IAR1H

2 C

Bits 0-2 are used for SAROB .
AlB, A 17, A16
X
X
X
X

0
0
1
1

0
1
0
1

DMA Transfer Request
DREQo (extemal)
RDRO (ASCIO)
RDRl (ASCll)
Not Used

Bits 0-2 are used for DAROB.
AlB, A17, A16
X
0
0
X
1
0
X
1
0
X
1
1

DMA Transfer Request
DREQo (external)
", ORO (ASCIO)
TDRl (ASCI 1)
Not Used

Bits 0-2 are used for MARl B.

(to be continued)

209

REGISTER

I

MNEMONICS

ADDRESS

DMA Byte Count Register Channel
1l
: BCR1l

2 E

DMA Byte Count Register Channel
1H
: BCR1H

2 F

DMA Status Register

3 0

REMARKS

bit

DE1

DEO

DIE 1

OlEO

-

DME

during RESET

0

0

1

1

0

0

1

0

RIW

RIW

RIW

W

W

RIW

RIW

: DSTAT

OWE 1 DWEO

R

lnMA
Master
Enable
leMA Interrupt Enable 1,0
L-DMA Enable Bit Write Enable 1,0
'-- DMA Enable ch 1,0
3 1

DMA Mode Register

bit

-

-

DM1

DMO

SM1

during RESET

1

1

0

0

0

0

0

RIW

RIW

RIW

RIW

RIW

: DMODE

RIW

SMO MMOD

L---

1

[MemOry
MODE
Select
Ch 0 Source
Mode 1,0

'-- Ch 0 Destination
Mode 1,0
DM1, 0 Destination
00
1
1 0
1 1

o

MMOD
0
1

M
M
M

VO

Address
DARO+1
DARO-1
DARO fixed
DARO fixed

SM1,O Source
M
0
M
1
M
1 0
VO
1 1

o
o

Address
SARO+ 1
SARO-1
SARO fixed
SARO fixed

Mode
Cycle Steal Mode
Burst Mode

(to be continued)

210

REGISTER

I

MNEMONICS

DMAIWAIT Control Register

ADDRESS

3 2
: DCNTL

REMARKS
bit

MWll

MWIO

1W11

IWIO

during RESET

1

1

1

1

0

0

0

0

RIW

RIW

RIW

RIW

R/W

RIW

RIW

RIW

RIW

DMSl DMSO

DIMl

DIMO

lDMA Ch 1
I/O Memory
Mode Select
L- DREQi Select, i
1,0
-I/O Wait Insertion
'-- Memory Wait Insertion

=

The number of
wait states

MWI1,O

1
0

Edge sense
Level sense

DIM 1,0

Transfer Mode

Address Increment/Decrement
MARl + 1
MAR1-l
IARl fixed
IARl fixed

M-VO
M-VO
VQ-M
I/O-M

00
01
10
11
3 3

0
2
3
4

Sense

DMSi

: IL

The number of
wait states

00
01
10
11

0
1
2
3

00
01
10
11

Interrupt Vector Low Register

IWI1,O

IARl fixed
IARl fixed
MAR1+l
MAR1-l

bit

1L7

IL6

IL5

-

-

-

-

-

during RESET

0

0

0

0

0

0

0

0

RIW

RIW

RIW

RIW

ITEO

Llnterrupt Vector Low

INT!TRAP Control Register

3 4
: ITC

bit

TRAP

UFO

-

-

-

ITE2

ITEl

during RESET

0

0

1

1

1

0

0

1

RIW

RIW

R

RIW

RIW

RIW

l

liNT Enable 2,1 ,0

Und_ Fet£h Object

'-TRAP
Refresh Control Register

3 6
: RCR

bit

REFE

REFW

-

-

-

-

CYCl

during RESET

1

1

1

1

1

1

0

0

RIW

RIW

RIW

RIW

RIW

l,

CYCO

lcycle Select

L h W•• Sta1o

Refresh Enable

CYC1,0
00
01
10
11

Interval of Refresh Cycle
10 States
20
40
80

(to be continued)

211

REGISTER

I

MNEMONICS

MMU Common Base Register

REMARKS

ADDRESS
3 8

: CBR

bit

-

CB6

CB5

CB4

CB3

CB2

CB1

during RESET

0

0

0

0

0

0

0

0

RIW

RIW

RIW

RIW

RIW

RIW

RIW

RIW

R/W

CBO

LMMU Common Base Register
39

MMU Bank Base Register
: BBR

bit

-

BB6

BB5

BB4

BB3

BB2

BB1

during RESET

0

0

0

0

0

0

0

0

R/W

R/W

RIW

RIW

R/W

RIW

RIW

RIW

RIW

"LMMU Common/Bank Area Register
: CBAR

3 A

MMU Bank Base

BBO

Regist~r

bit

CA3

CA2

CA1

CAO

BA3

BA2

BA1

during RESET

1

1

1

1

0

0

0

0

RIW

R/W

RIW

R/W

RIW

R/W

RIW

RIW

RIW

L

BAO

L MMU Bank
Area Register

MMU Convnon
Area Register

VO Control Register

3 F
: ICR

bit

IOA7

IOA6

IOSTP

-

-

-

-

-

during RESET

0

0

0

1

1

1

1

1

RIW

R/W

RIW

R/W

L

Lvo

VO Address

212

Stop

HITACHI AMERICA, LTD.
SEMICONDUCTOR AND IC DIVISION
HEADQUARTERS

U.S. SALES OFFICE

Hitachi, Ltd.
New Marunouchi Bldg., 5-1,
Marunouchi 1 chrome
Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 212-1111
Telex: J22395, J22432, J24491,
J26375 (HITACHY)
Cable: HITACHY TOKYO

Hitachi America, Ltd.
Semiconductor and IC Division
2210 O'Toole Avenue
San Jose, CA 95131
Tel: 408-942-1500
Telex: 17-1581
Twx: 910-338-2103
Fax: 408-942-8225
Fax: 408-942-8880

REGIONAL OFFICES

DISTRICT OFFICES

NORTHEAST REGION
Hitachi America, Ltd.
5 Burlington Woods Drive
Burlington, MA 01803
617/229-2150

•

Hitachi America, Ltd.
1700 Galloping Hill Rd.
Kenilworth, NJ 07033
201/245-6400

•

Hitachi America, Ltd.
3500 W. 80th Street, Suite 660
Bloomington, MN 55431
612/831-0408

•

Hitachi America, Ltd.
80 Washington St., Suite 302
Poughkeepsie, NY 12601
914/485-3400

•

Hitachi America, Ltd.
6 Parklane Blvd., #558
Dearborn, MI 48126
313/271-4410

•

Hitachi America, Ltd.
6161 Savoy Dr., Suite 850
Houston, TX 77036
713/974-0534

•

Hitachi America, Ltd.
5775 Peachtree-Dunwoody Rd.
Suite 270C
Atlanta, GA 30342
404/843-3445

•

Hitachi America, Ltd.
18300 Von Karman Avenue, Suite 730
Irvine, CA 92715
714/553-8500

•

Hitachi America, Ltd.
10300 S.W. Greenburg Rd., Suite 480
Portland, OR 97223
503/245-1825

•

Hitachi (Canadian) Ltd.
2625 Queensview Dr.
Ottawa, Ontario, Canada K2A 3Y4
613/596-2777

SOUTH CENTRAL REGION
Hitachi America, Ltd.
Two Lincoln Centre, Suite 865
5420 LBJ Freeway
Dallas, TX 75240
214/991-4510
NORTH CENTRAL REGION
Hitachi America, Ltd.
500 Park Blvd., Suite 415
Itasca, IL 60143
312/773-4864
NORTHWEST REGION
Hitachi America, Ltd.
2099 Gateway Place, Suite 550
San Jose, CA 95110
408/277-0712
SOUTHWEST REGION
Hitachi America, Ltd.
21600 Oxnard St., Suite 600
Woodland Hills, CA 91367
818/704-6500
SOUTHEAST REGION
'1

Hitachi America, Ltd.
4901 N.W. 17th Way, Suite 302
Fort Lauderdale, FL 33309
305/491-6154

213

NOTES

NOTES

NOTES



---

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