Hr60_la1811_r1 HP Pavilion Zv5000 Zx5000 COMPAL LA 1811 REV 1.0Sec
COMPAL_LA-1811_-_REV_1.0Sec
COMPAL_LA-1811-REV_1.0Sec
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A B C D E LA-1811 1 1 Compal confidential 2 2 Schematics Document DT TRANSPORT or Prescott uFCPGA with ATI-RC300M+SB200 core logic 2003-09-01 3 3 l.c om REV:1.0 f@ ho tm ai 4 in Compal Electronics, Inc. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D xa Cover Sheet Size Document Number he THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 E Sheet 1 of 66 4 A B C D E Compal confidential Fan Control File Name :LA1811 page 7 Intel Northwood/Prescott Processor uFCBGA-479/uFCPGA-478 CPU 1 1 page 4,5,6 page 7 CRT & TV-OUT Conn. page 25 PSB H_A#(3..31) LCD Conn W/EXT VGA CHIP Memory BUS(DDR) DDR-SO-DIMM X2 BANK 0, 1, 2, 3 page 14,15,16 W/O EXT VGA CHIP W/EXT VGA CHIP VGA M9 Embeded AGP BUS ATI-M9+X/M10C page 24 H_D#(0..63) ATI-RC300M W/O EXT VGA CHIP page 25 800MHz CLOCK GENERATOR ICS951402AGT Thermal Sensor ADM1032AR 868 pin u-BGA 2.5V DDR- 200/266 USB1.1 page 8,9,10,11,12,13 BT/USB KEY page 44 page 17,18,19,20,21 USB2.0 USB conn x3 page 44 VGA DDR x2 CHB VGA DDR x2 CHA page 23 2 Audio Codec ADI 1981B A-Link page 22 AMP & Audio Jack page 37 MDC & BT Conn IDSEL:AD19 (PIRQD#,GNT#1,REQ#1) USB2.0 Ctrl. IEEE 1394 NEC uPD720101 TI-TSB43AB22 page 36 page 35 IDSEL:AD23 (PIRQA/C/D#,GNT#4,REQ#4) IDSEL:AD16 (PIRQA#,GNT#0,REQ#0) Mini PCI socket page 43 ATI-SB200 IDSEL:AD20 (PIRQA,B#,GNT#2,REQ#2) LAN RTL 8101BL CardBus Controller TI PCI1520/1620 page 34 page 31 AC-LINK page 43 BGA 457 pin page 26,27,28,29 IDSEL:AD18 (PIRQC#,GNT#3,REQ#3) RJ45 CONN Slot 0,1 page 34 page 32 HDD Connector Primary IDE page 30 CDROM Connector page Secondary IDE Card slot page 44 Mini-PCI solt ATA-100 3 RJ11 CONN page 44 PCI BUS 3.3V 33 MHz 2 page 38 page 33 ATA-100 3 30 LPC BUS RTC CKT. page 26 CABLE CONN. page 41 VIA VT1211 Power OK CKT. Super I/O page 48 page 45 page 46 Touch Pad Int.KBD page 44,45 page 39 page 45 PARALLEL page 40 DC/DC Interface CKT. BIOS page 47 page 40 page 47 FIR page 49 ho tm page 45 f@ Power Circuit DC/DC Compal Electronics, Inc. in page 50,51,52,53,54,55,56,57 B C D Document Number LA-1811 Date: he DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size xa Block Diagram THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL A KEY l.c EC I/O Buffer FDD ai Power On/Off CKT. 4 *RJ45 CONN *LINE IN JACK *DC JACK *COM PORT *USB CONN x1 *SPDIF *5V INPUT *VOLUME ADJUSTMENT +TV-OUT PORT om NS 87591 Wednesday, September 24, 2003 E Sheet Rev 1.0 2 of 66 4 A Voltage Rails Power Plane Description S0-S1 VIN Adapter power supply (19V) B+ AC or battery power rail for power circuit. +VCC_CORE Core voltage for CPU +VCCVID The voltage for Processor VID select +1.25VS 1.25V switched power rail for DDR Vtt +1.2VS_VGA 1.2V I/O power rail for ATI-VGA M9+X/M10P. S3 S5 N/A N/A N/A N/A N/A ON OFF OFF ON OFF OFF ON OFF OFF ON OFF OFF N/A Symbol Note : : means Digital Ground : means Analog Ground +1.5VS 1.5V I/O power rail for ATI-RS300M/RC300M NB AGP. ON OFF OFF +1.8VS 1.8V switched power rail for ATI-RS300M/RC300M NB. ON OFF OFF @ : means just reserve , no build +2.5VALW 2.5V always on power rail ON ON ON* NAGP@ : means just build when no external AGP VGA chip build in (UMA). M10@ : means build VGA M10 M9@ : means build VGA M9+X M9-M10@ : means build VGA M9 or M10 1520@ : means build Cardbus PCI1520 1620@ : means build Cardbus PCI1620 ATI@ : means build ATI SB USB2.0 related to turn on the function . NEC@ : means build NEC USB2.0 related to turn on the function . +2.5V 2.5V system power rail for DDR ON ON OFF +2.5VS 2.5V switched power rail ON OFF OFF +3VALW 3.3V always on power rail ON ON ON* +3V 3.3V system power rail for SB,LAN,CardReader and HUB. ON ON OFF +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5V 5V system power rail . ON ON OFF +5VS 5V switched power rail ON OFF OFF +12VALW 12V always on power rail ON ON ON* RTCVCC RTC power ON ON ON Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. External PCI Devices DEVICE IDSEL # REQ/GNT # PIRQ NB Internal VGA N/A N/A A AGP BUS AGP_DEVSEL N/A A SOUTHBRIDGE AD31 (INT.) N/A N/A USB AD30 (INT.) N/A D AC97 AD31 (INT.) N/A B ATA 100 AD31 (INT.) N/A A ETHERNET AD24(INT.) N/A C 1394 AD16 0 A LAN AD19 1 D CARD BUS AD20 2 A.B Wireless LAN(MINI PCI) AD18 3 C EXT USB AD23(EXT.) 4 A,C,D 1 I2C / SMBUS ADDRESSING D2 1101001X l.c CLOCK GENERATOR (EXT.) ai 1010001X tm A2 ho 1010000X DDR SO-DIMM 1 om ADDRESS f@ A0 Compal Electronics, Inc. in HEX DDR SO-DIMM 0 Notes List xa DEVICE AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS he 1 LA-1811 Date: A Wednesday, September 24, 2003 1.0 Sheet 3 of 66 5 4 3 2 1 +VCC_CORE D D JP8A H_A#4 H_A#5 H_A#6 H_D#1 H_D#2 H_D#3 H_A#9 H_A#10 H_A#11 H_D#6 H_D#7 H_D#8 H_A#14 H_A#15 H_A#16 H_D#11 H_D#12 H_D#13 H_A#19 H_A#20 H_A#21 H_D#16 H_D#17 H_D#18 H_A#24 H_A#25 H_A#26 H_D#21 H_D#22 H_D#23 H_A#29 H_A#30 H_A#31 H_D#26 H_D#27 H_D#28 Prescott C H_D#31 H_D#32 H_D#33 H_REQ#1 H_REQ#2 H_REQ#3 <8> C H_D#36 H_D#37 H_D#38 H_ADS# H_D#41 H_D#42 H_D#43 R230 @62_0402_5% H_IERR# +VCC_CORE R231 H_D#46 H_D#47 H_D#48 51_0402_5% +VCC_CORE <8> <8> <8> H_BPRI# H_BNR# H_LOCK# <24> <24> CK_BCLK CK_BCLK# <8> <8> <8> H_HIT# H_HITM# H_DEFER# H_D#51 H_D#52 H_D#53 CK_BCLK# H_D#56 H_D#57 H_D#58 H_D#61 H_D#62 H_D#63 +5VS B +5VS R1099 R1100 47K_0402_5% 47K_0402_5% B AMP_3-1565030-1_Prescott H_BOOTSELECT <56> +VCC_CORE Reference Intel document Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0 R899 Q106 2SC2411K_SC59 22K_0402_5% Q107 Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5 MMBT3904_SOT23 Pin number Northwood Pin name Commend Prescott Pin name Commend Northwood MT Pin name Commend Northwood Prescott Northwood MT R900 100K_0402_5% Connect to PLD CPUPREF through 0ohm GHI Pop Pop Pop Pop Pop Pop Pull-up 62ohm to +VCC_CORE AA20 ITPCLKOUT0 Pull-up56ohm to +VCC_CORE TESTHI6 Pull-up 62ohm to +VCC_CORE ITPCLKOUT0 Pull-up56ohm to +VCC_CORE Pop Pop Pop AB22 ITPCLKOUT1 Pull-up 56ohm to +VCC_CORE TESTHI7 Pull-up 62ohm to +VCC_CORE ITPCLKOUT1 Pull-up 56ohm to +VCC_CORE Pop Pop Pop float VIDPWRGD Pull-up 2.43K ohm to +VCCVID NC Depop Pop Depop Pull-up1Kohm to +3VRUN & connect to PWRIC Connect to +VCCVID NC Depop Pop Depop Depop Pop Depop Pop Depop Pop Pop Depop Pop Pop Pop Pop AD3 NC NC float VID5 A AF3 float float NC float VCCVIDLB VCCA Connect to CPU Filter VCCIOPLL Connect to CPU Filter VCCA Connect to CPU Filter AE23 NC float VCCIOPLL Connect to CPU Filter VCCA Connect to CPU Filter VCCIOPLL Connect to CPU Filter AD1 VSS Connect to GND BOOTSELECT CPU determine VSS Connect to GND AE26 VSS Connect to GND OPTIMIZED/ COMPAT# float VSS Connect to GND AD20 AD25 TESTHI12 Pull-up 200ohm to +VCC_CORE TESTHI12 Pull-up 62ohm to +VCC_CORE Connect to PLD through 0ohm DPSLP ho AD2 om FERR# l.c Pull-up 62ohm to +VCC_CORE ai Pull-up 62ohm to +VCC_CORE tm FERR#/PBE# f@ TESTHI11 Pull-up 62ohm to +VCC_CORE Compal Electronics, Inc. in Pull-up 200ohm to +VCC_CORE FERR# xa TESTHI11 B6 Prescott Processor in uFCPGA478 he A6 LA-1811 Wednesday, September 24, 2003 5 4 3 2 4 1 66 A 5 4 3 2 1 +VCC_CORE Place near SB200 (U6) R514 R513 56_0402_5% R515 56_0402_5% H_THERMTRIP# @0_0402_5% JP8B <8> H_PROCHOT# D R518 H_RS#[0..2] H_RS#0 D +CPU_GTLREF 300_0402_5% H_PWRGOOD R519 56_0402_5% <26> <8> H_TRDY# <26> <26> <26> H_A20M# H_FERR# H_IGNNE# H_FERR# +VCC_CORE H_PWRGOOD <26> H_STPCLK# <26> H_INTR <26> <8,26> H_INIT# H_RESET# <8> H_TESTHI0_1 H_DRDY# <13,24> <13,24> <7> <7> H_TESTHI10 H_TESTHI11 H_DPSLP# H_TESTHI12 BSEL0 BSEL1 H_THERMDA H_THERMDC 56_0402_5% R527 56_0402_5% PIR BOM 92.09.01 H_THERMDC +VCC_CORE <7> R522 H_RESET# CPU_STP# Prescott H_THERMTRIP# H_THERMTRIP# R529 56_0402_5% H_DSTBN#0 H_DSTBN#1 ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#5 C RP137 LQG21F4R7N00_0805 33U_D2_8M_R35 H_VCCA C544 C854 <56> <8> H_DSTBP#2 H_DSTBP#3 <8> <8> C <8> H_DINV#2 H_DINV#3 <8> <8> R1017 +VCCVID 0_0402_5% H_PROCHOT# H_PROCHOT# H_VSSA <26,51> H_CPUSLP# LQG21F4R7N00_0805 <24> <24> PLL Layout note : <8> H_DINV#0 ITP_DBRESET# VCCSENSE 33U_D2_8M_R35 L37 <8> H_DSTBP#0 H_ADSTB#1 ITP_TDO ITP_TMS ITP_TRST# L36 H_DSTBN#3 56_0804_8P4R_5% Note: Please change to 10uH, DC current of 100mA parts and close to cap +VCC_CORE <8> <8> CK_ITP CK_ITP# <26> CK_ITP# COMP0 1.Place cap within 600 mils of the VCCA and VSSA pins. 2.H_VCCIOPLL,HVCCA,HVSSA trace wide 12 mils(min) R539 R540 51.1_0402_1% 51.1_0402_1% AMP_3-1565030-1_Prescott +VCCVID C932 If CPU is P4 , Change the resistor R539,R540 value to 51.1_0603_1%,or prescott 61.9_0603_1% B VID0 B +VCCVID VID3 VID4 VID5 +3VS R541 2.43K_0603_1% H_VID_PWRGD R546 ITP_TDO If CPU is P4 , Change the resistor R546 value to 75_0603_1% 4.7K_0402_5% D <55,56> R547 54.9_0603_1% VID_PWRGD Q45 G U32A S 2N7002 1N_SOT23 SN74LVC14APWLE_TSSOP14 Close to the ITP +VCC_CORE GTL Reference Voltage R550 47_0402_5% 4.7K_0402_5% Layout note : Q95 MMBT3904_SOT23 VID5 VID5 R543 1K_0402_5% RP94 1K_1206_8P4R_5% R1125 ITP_TDI <11,26,56> Q96 CPUCLK_STP# 12K_0402_5% R_A <56> <56> <56> +CPU_GTLREF 49.9_0402_1% VID3 VID2 VID1 ai If CPU is P4 , Change the resistor R556 value to 27.4_0402_5% VID3 VID2 VID1 tm ITP_TCK 47_0402_5% R558 C546 C547 ho R556 R_B f@ Close to the CPU R559 680_0603_5% in Compal Electronics, Inc. xa ITP_TRST# Between the CPU and ITP Prescott Processor in uFCPGA478 he A <56> om 150_0402_5% 2. Place R_A and R_B near CPU. 3. Place decoupling cap 220PF near CPU. l.c R552 +3VS 1. +CPU_GTLREF Trace wide 12mils(min),Space 15mils If CPU is P4 , Change the resistor R550 value to 39_0402_5% LA-1811 Thursday, September 25, 2003 5 4 3 2 5 1 66 A 5 4 3 2 1 Place 11 North of Socket(Stuff 6) C131 C132 C133 C134 C135 C136 C137 C138 C139 C140 C141 D D Place 12 Inside Socket(Stuff all) +VCC_CORE C142 22U_1206_16V4Z C143 22U_1206_16V4Z C152 C153 C144 22U_1206_16V4Z C145 22U_1206_16V4Z C146 22U_1206_16V4Z C147 22U_1206_16V4Z C148 22U_1206_16V4Z C149 22U_1206_16V4Z C150 22U_1206_16V4Z C151 22U_1206_16V4Z C C Place 9 South of Socket(Unstuff all) +VCC_CORE 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z B B Place Inside Socket around the edge +VCC_CORE C163 C164 C165 C166 C167 470U_D2_2.5VM 470U_D2_2.5VM 470U_D2_2.5VM @330U_D2E_2.5VM 470U_D2_2.5VM 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K +VCC_CORE C174 C175 C176 C177 C178 470U_D2_2.5VM 470U_D2_2.5VM @330U_D2E_2.5VM 470U_D2_2.5VM 470U_D2_2.5VM C179 C180 C181 C182 C183 470U_D2_2.5VM 470U_D2_2.5VM 470U_D2_2.5VM 470U_D2_2.5VM @470U_D2_2.5VM +VCC_CORE A A Compal Electronics, Inc. CPU Decoupling LA-1811 Wednesday, September 24, 2003 5 4 3 2 6 1 66 5 4 3 2 1 Thermal Sensor ADM1032AR +3VALW H_THERMDA H_THERMDA <5> H_THERMDC <5> 0.1U_0402_10V6K R283 @10K_0402_5% D C253 EC_SMC_2 <46> EC_SMD_2 <46> D H_THERMDC Address:1001_100X +VCC_CORE R286 300_0402_5% C256 @1U_0603_10V6K MAINPWON <5> <50,51,53> H_THERMTRIP# H_THERMTRIP# Q17 2SC2411K_SC59 C C FAN CONN.1 FAN CONN. 2 +12VALW 1SS355_SOD323 U10A <46> C EN_DFAN2 EN_FAN1 R913 B D67 C838 10U_0805_16V4Z LM358A_SO8 <46> C EN_FAN2 EN_FAN2 R914 0.1U_0402_10V6K D68 10U_0805_16V4Z B LM358A_SO8 FAN1 FMMT619_SOT23 100_0402_5% Q90 E C840 10K_0402_5% FMMT619_SOT23 100_0402_5% Q91 E C841 10K_0402_5% 0.1U_0402_10V6K FAN2 JP10 D25 R917 8.2K_0402_5% 1N4148_SOD80 C265 JP11 C855 R918 8.2K_0402_5% D26 10U_0805_10V4Z C266 1N4148_SOD80 C856 10U_0805_10V4Z ACES_85205-0300 ACES_85205-0300 1000P_0402_16V7K R919 +3VS <46> 1000P_0402_16V7K 10K_0402_5% +3VS FANSPEED1 <46> PIR BOM 92.09.01 R920 10K_0402_5% FANSPEED2 PIR BOM 92.09.01 C908 B B 1000P_0402_16V7K A A Compal Electronics, Inc. CPU Thermal Sensor&FAN CTRL LA-1811 Wednesday, September 24, 2003 5 4 3 2 7 1 66 5 4 3 2 H_A#[3..31] 1 H_A#[3..31] <4> H_REQ#[0..4] H_REQ#[0..4] <4> H_D#[0..63] H_D#[0..63] <4> U27A PART 1 OF 6 C Note: PLACE CLOSE TO RC300M, USE 10/10 WIDTH/SPACE +VCC_CORE B R383 PLACE CLOSE TO U27 Ball W28, USE 20/20 WIDTH/SPACE H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRDY# H_DBSY# H_BR0# H_LOCK# H_RESET# H_RS#2 H_RS#1 H_RS#0 <5,26> H_RESET# <5> H_RS#2 <5> H_RS#1 <5> H_RS#0 <5> <4> <4> DATA GROUP 0 H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRDY# H_DBSY# H_BR0# H_LOCK# H_TRDY# H_HIT# H_HITM# H_TRDY# H_HIT# H_HITM# 412_0402_1% <27> SUS_STAT# <17,26,39> NB_RST# <48> NB_PWRGD +VCC_CORE +1.8VS R381 24.9_0402_1%COMP_N R382 L34 49.9_0402_1%COMP_P HB-1M2012-121JT03_0805 49.9_0402_1% CPVDD 1U_0603_10V6K CPVSS C361 R384 C362 MISC. NB_GTLREF 100_0402_1% H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DINV#2 H_DSTBN#2 H_DSTBP#2 C363 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DINV#3 H_DSTBN#3 H_DSTBP#3 DATA GROUP 3 L --> 412_0402_1% R380 H_ADSTB#1 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DINV#1 H_DSTBN#1 H_DSTBP#1 DATA GROUP 2 0.1U_0402_10V6K C974 <5> <4> <4> <4> <4> <5> <5> <4> <4> ADDR. GROUP 1 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_ADSTB#1 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DINV#0 H_DSTBN#0 H_DSTBP#0 PENTIUM AGTL+ I/F DATA GROUP 1 IV H_ADSTB#0 CONTROL <5> ADDR. GROUP 0 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_ADSTB#0 D 1U_0603_10V6K 220P_0402_25V8K C363 CLOSE TO Ball W28 R385 D H_DINV#0 <5> H_DSTBN#0 <5> H_DSTBP#0 <5> C H_DINV#1 <5> H_DSTBN#1 <5> H_DSTBP#1 <5> H_DINV#2 <5> H_DSTBN#2 <5> H_DSTBP#2 <5> B H_DINV#3 <5> H_DSTBN#3 <5> H_DSTBP#3 <5> 4.7K_0402_5% 216RC300M_BGA_718 +VCC_CORE 0.1U_0402_10V6K C364 22U_1206_16V4Z_V1 C365 C366 C367 0.1U_0402_10V6K C368 C369 0.1U_0402_10V6K C370 C371 C372 0.1U_0402_10V6K A 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K A 0.1U_0402_10V6K Compal Electronics, Inc. ATI RC300M-AGTL+ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 8 of 66 5 4 3 2 PART 2 OF 6 DDRA_ADD0 DDRA_ADD1 DDRA_ADD2 DDRA_ADD3 DDRA_ADD4 DDRA_ADD5 DDRA_ADD6 DDRA_ADD7 DDRA_ADD8 DDRA_ADD9 DDRA_ADD10 DDRA_ADD11 DDRA_ADD12 DDRA_ADD13 DDRA_ADD14 DDRA_ADD15 D DDRA_DQ0 DDRA_DQ1 DDRA_DQ2 DDRA_DQ3 DDRA_DQ4 DDRA_DQ5 DDRA_DQ6 DDRA_DQ7 DDRA_DQ8 DDRA_DQ9 DDRA_DQ10 DDRA_DQ11 DDRA_DQ12 DDRA_DQ13 DDRA_DQ14 DDRA_DQ15 DDRA_DQ16 DDRA_DQ17 DDRA_DQ18 DDRA_DQ19 DDRA_DQ20 DDRA_DQ21 DDRA_DQ22 DDRA_DQ23 DDRA_DQ24 DDRA_DQ25 DDRA_DQ26 DDRA_DQ27 DDRA_DQ28 DDRA_DQ29 DDRA_DQ30 DDRA_DQ31 DDRA_DQ32 DDRA_DQ33 DDRA_DQ34 DDRA_DQ35 DDRA_DQ36 DDRA_DQ37 DDRA_DQ38 DDRA_DQ39 DDRA_DQ40 DDRA_DQ41 DDRA_DQ42 DDRA_DQ43 DDRA_DQ44 DDRA_DQ45 DDRA_DQ46 DDRA_DQ47 DDRA_DQ48 DDRA_DQ49 DDRA_DQ50 DDRA_DQ51 DDRA_DQ52 DDRA_DQ53 DDRA_DQ54 DDRA_DQ55 DDRA_DQ56 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ60 DDRA_DQ61 DDRA_DQ62 DDRA_DQ63 DDRA_DM0 DDRA_DM1 DDRA_DM2 DDRA_DM3 DDRA_DM4 DDRA_DM5 DDRA_DM6 DDRA_DM7 <14,15,16> DDRA_RAS# <14,15,16> DDRA_CAS# <14,15,16> DDRA_WE# DDRA_WE# <14> DDRA_CLK0 <14> DDRA_CLK0# <14> DDRA_CLK1 <14> DDRA_CLK1# <15> DDRA_CLK3 <15> DDRA_CLK3# <15> DDRA_CLK4 <15> DDRA_CLK4# <14,16> <14,16> <15,16> <15,16> DDRA_CKE_R0 DDRA_CKE_R1 DDRA_CKE_R2 DDRA_CKE_R3 <14,16> DDRA_CS#0 <14,16> DDRA_CS#1 <15,16> DDRA_CS#2 <15,16> DDRA_CS#3 +1.8VS MEM I/F DDRA_DQS0 DDRA_DQS1 DDRA_DQS2 DDRA_DQS3 DDRA_DQS4 DDRA_DQS5 DDRA_DQS6 DDRA_DQS7 C B DDRA_RAS# DDRA_CAS# DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1# DDRA_CLK3 DDRA_CLK3# DDRA_CLK4 DDRA_CLK4# DDRA_CKE_R0 DDRA_CKE_R1 DDRA_CKE_R2 DDRA_CKE_R3 DDRA_CS#0 DDRA_CS#1 DDRA_CS#2 DDRA_CS#3 L35 HB-1M2012-121JT03_0805 MPVDD RP27 DDRA_DQ36 DDRA_DQ32 RP28 U27B 1 DDRA_SDQ36 DDRA_SDQ32 DDRA_DQ8 DDRA_DQ12 DDRA_SDQ8 DDRA_SDQ12 DDRA_DQ9 DDRA_DQ13 0_0404_4P2R_5% RP31 DDRA_SDQ9 DDRA_SDQ13 DDRA_DQ37 DDRA_DQ33 0_0404_4P2R_5% RP30 DDRA_SDQ37 DDRA_SDQ33 DDRA_DQ10 DDRA_DQ14 0_0404_4P2R_5% RP34 DDRA_SDQ10 DDRA_SDQ14 DDRA_DQ38 DDRA_DQ34 0_0404_4P2R_5% RP33 DDRA_SDQ38 DDRA_SDQ34 DDRA_DQ39 DDRA_DQ35 0_0404_4P2R_5% RP36 DDRA_SDQ39 DDRA_SDQ35 DDRA_DQS4 R386 0_0404_4P2R_5% DDRA_SDQS4 0_0402_5% DDRA_DQ11 DDRA_DQ15 0_0404_4P2R_5% RP37 DDRA_SDQ11 DDRA_SDQ15 DDRA_DQS1 R387 DDRA_DM1 R388 0_0404_4P2R_5% DDRA_SDQS1 0_0402_5% DDRA_SDM1 0_0402_5% DDRA_DM4 R389 D DDRA_SDM4 0_0402_5% RP40 RP41 DDRA_DQ0 DDRA_DQ4 DDRA_SDQ0 DDRA_SDQ4 DDRA_DQ44 DDRA_DQ40 DDRA_SDQ44 DDRA_SDQ40 DDRA_DQ1 DDRA_DQ5 0_0404_4P2R_5% RP43 DDRA_SDQ1 DDRA_SDQ5 DDRA_DQ45 DDRA_DQ41 0_0404_4P2R_5% RP44 DDRA_SDQ45 DDRA_SDQ41 DDRA_DQ3 DDRA_DQ7 0_0404_4P2R_5% RP45 DDRA_SDQ3 DDRA_SDQ7 DDRA_DQ46 DDRA_DQ42 0_0404_4P2R_5% RP46 DDRA_SDQ46 DDRA_SDQ42 DDRA_DQ2 DDRA_DQ6 0_0404_4P2R_5% RP47 DDRA_SDQ2 DDRA_SDQ6 DDRA_DQ47 DDRA_DQ43 0_0404_4P2R_5% RP48 DDRA_SDQ47 DDRA_SDQ43 0_0404_4P2R_5% DDRA_DQS0 DDRA_SDQS0 R394 0_0402_5% 0_0404_4P2R_5% DDRA_DQS5 DDRA_SDQS5 R395 0_0402_5% DDRA_DM0 R397 DDRA_DM5 R398 DDRA_SDM0 0_0402_5% C DDRA_SDM5 0_0402_5% RP49 DDRA_DQ20 DDRA_DQ16 DDRA_SDQ20 DDRA_SDQ16 DDRA_DQ21 DDRA_DQ17 0_0404_4P2R_5% RP51 DDRA_SDQ21 DDRA_SDQ17 RP50 DDRA_DQ60 DDRA_DQ56 DDRA_SDQ60 DDRA_SDQ56 DDRA_DQ61 DDRA_DQ57 0_0404_4P2R_5% RP52 DDRA_SDQ61 DDRA_SDQ57 DDRA_SDQ18 DDRA_SDQ22 DDRA_DQ62 DDRA_DQ58 0_0404_4P2R_5% RP54 DDRA_SDQ62 DDRA_SDQ58 DDRA_DQ19 DDRA_DQ23 0_0404_4P2R_5% RP55 DDRA_SDQ19 DDRA_SDQ23 DDRA_DQ63 DDRA_DQ59 0_0404_4P2R_5% RP56 DDRA_SDQ63 DDRA_SDQ59 DDRA_DM2 R403 0_0404_4P2R_5% DDRA_SDM2 0_0402_5% DDRA_DQS7 R404 0_0404_4P2R_5% DDRA_SDQS7 0_0402_5% 0_0404_4P2R_5% RP53 DDRA_DQ18 DDRA_DQ22 Group 6 sweep Group 7 C373 0.47U_0603_16V7K C374 0.47U_0603_16V7K MEN_COMP R 4 0 5 DDRA_SDM[0..7] DDRA_DQS2 R406 DDRA_SDQS2 0_0402_5% DDRA_DM7 R407 RP57 1U_0603_10V6K DDRA_SDQS[0..7] RP58 DDRA_DQ24 DDRA_DQ28 DDRA_SDQ24 DDRA_SDQ28 DDRA_DQ52 DDRA_DQ48 DDRA_SDQ52 DDRA_SDQ48 DDRA_DQ25 DDRA_DQ29 0_0404_4P2R_5% RP59 DDRA_SDQ25 DDRA_SDQ29 DDRA_DQ53 DDRA_DQ49 0_0404_4P2R_5% RP60 DDRA_SDQ53 DDRA_SDQ49 DDRA_DQ26 DDRA_DQ30 0_0404_4P2R_5% RP61 DDRA_SDQ26 DDRA_SDQ30 DDRA_DQ50 DDRA_DQ54 0_0404_4P2R_5% RP62 DDRA_SDQ50 DDRA_SDQ54 DDRA_DQ27 DDRA_DQ31 0_0404_4P2R_5% RP63 DDRA_SDQ27 DDRA_SDQ31 DDRA_DQ51 DDRA_DQ55 0_0404_4P2R_5% RP64 DDRA_SDQ51 DDRA_SDQ55 DDRA_DQS3 R412 0_0404_4P2R_5% DDRA_SDQS3 0_0402_5% DDRA_DQS6 R413 0_0404_4P2R_5% DDRA_SDQS6 0_0402_5% <14,15,16> DDRA_SDQ[0..63] <14,15,16> DDRA_SDQS[0..7] <14,15,16> DDRA_ADD[0..15] <14,15,16> B DDRA_SDM7 0_0402_5% C375 MPVSS DDRA_SDM[0..7] DDRA_SDQ[0..63] 49.9_0402_1% DDRA_ADD[0..15] 216RC300M_BGA_718 +2.5V +2.5V C376 R408 0.1U_0402_10V6K 1K_0603_1% DDR_VREF DDR_VREF C377 0.1U_0402_10V6K +2.5V L @0.1U_0402_10V6K R409 1K_0603_1% DDRA_DM3 R415 DDR_VREF trace width of 20mils and space 20mils(min) 0.1U_0402_10V6K C858 C859 C860 C861 C378 0.1U_0402_10V6K DDRA_DM6 R416 Place these resistor closely DIMM0, all trace length Max=0.75" DDRA_SDM6 0_0402_5% +2.5V A C857 DDRA_SDM3 0_0402_5% Layout note + C379 C380 C381 0.1U_0402_10V6K C382 C383 0.1U_0402_10V6K C384 C385 0.1U_0402_10V6K C386 C387 0.1U_0402_10V6K C388 C389 A 0.1U_0402_10V6K C390 C391 @0.1U_0402_10V6K 100U_D2_10VM @0.1U_0402_10V6K @0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K Compal Electronics, Inc. ATI RC300M-DDR I/F THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 9 of 66 5 4 3 2 1 A_AD[0..31] <13,26> A_AD[0..31] A_CBE#[0..3] <13,26> A_CBE#[0..3] U27C A_AD0 A_AD1 A_AD2 A_AD3 A_AD4 A_AD5 A_AD6 A_AD7 A_AD8 A_AD9 A_AD10 A_AD11 A_AD12 A_AD13 A_AD14 A_AD15 A_AD16 A_AD17 A_AD18 A_AD19 A_AD20 A_AD21 A_AD22 A_AD23 A_AD24 A_AD25 A_AD26 A_AD27 A_AD28 A_AD29 A_AD30 A_AD31 A_CBE#0 A_CBE#1 A_CBE#2 A_CBE#3 A_PAR A_STROBE# A_ACAT# A_END# 0_0402_5% A_DEVSEL# A_OFF# <13,26> A_PAR <26> A_STROBE# <26> A_ACAT# <26> A_END# R1005 <17,26,31,35,36> PCI_PIRQA# <26> A_DEVSEL# <26> A_OFF# C <26> <26> A_SBREQ# A_SBGNT# A_SBREQ# A_SBGNT# R570 8.2K_0402_5% +3VS AGP_GNT# AGP_REQ# <17> AGP_GNT# <17> AGP_REQ# ? PCI BUS 1 / AGP Bus (GPIO , TMDS , ZVPort) PCI Bus 0 / A-Link I/F D AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31 PART 3 OF 6 NAPG@0_0402_5% R561 NAPG@0_0402_5% AGP_SBA4 R562 NAPG@0_0402_5% AGP_SBA5 R563 NAPG@0_0402_5% AGP_SBA6 R564 @0_0402_5% LVDS_SSOUT AGP_SBA7 R565 @0_0402_5% LVDS_SSIN AGP_SBA1 R994 NAPG@0_0402_5% D D C _ D A T AGP_SBA0 R995 NAPG@0_0402_5% D D C _ C L K +1.5VS AGP_SBSTB <17> AGP_SBSTB# <17> AGP_ADSTB0 <17> AGP_ADSTB0# <17> AGP_ADSTB1 <17> AGP_ADSTB1# <17> <17,25,46> D <17,27> AGP_BUSY# <17,27> D D C _ D A T <17,25> D D C _ C L K <17,25> AGP_CBE#[0..3] AGP_AD[0..31] <17> AGP_SBA[0..7] <17> AGP_CBE#[0..3] <17> AGP_ST[0..2] PIR BOM 92.06.23 AGP_ST[0..2] L38 @BLM21P300S_0805 <17> C +3VS LVDS_SSOUT C548 C549 @0_0402_5% R1086 AGP_IRDY# AGP_TRDY# AGP_STOP# AGP_PAR AGP_FRAME# AGP_DEVSEL# AGP_DBI_HI/PIPE# AGP_DBI_LO AGP_RBF# AGP_WBF# AGP_IRDY# <17> @10U_0805_6.3V6M AGP_TRDY# <17> R568 AGP_STOP# <17> AGP_PAR <17> @0_0402_5% AGP_FRAME# <17> AGP_DEVSEL# <17> AGP_DBI_HI/PIPE# <17> AGP_DBI_LO <17> AGP_RBF# <17> AGP_WBF# <17> AGP_SBA0 AGP_SBA1 AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA6 AGP_SBA7 SSOUT <17> R1144 @0_0402_5% R567 U33 R569 @0_0402_5% @0_0402_5% LVDS_SSIN R1087 S0 @0_0402_5% C952 S1 R572 SSIN <17> @10P_0402_25V8K @SM561BS_SO8 R573 @0_0402_5% LVDS SPREAD SPECTRUM @0_0402_5% R574 @0_0402_5% R1088 @0_0402_5% AGP_COMP L AGP_ST0 AGP_ST1 AGP_ST2 169_0402_1% <17,25> ENAVDD AGP_STP# @0.1U_0402_10V6K 0.1U_0402_10V6K Ra ENABLT# AGP_SBA[0..7] AGP_CBE#0 AGP_CBE#1 AGP_CBE#2 AGP_CBE#3 C550 B R560 AGP_SBA3 AGP_AD[0..31] AGP_SBSTB AGP_SBSTB# AGP_ADSTB0 AGP_ADSTB0# AGP_ADSTB1 AGP_ADSTB1# AGPREF_8X <17> VREF_8X_IN R575 AGP_SBA2 AGP8X_DET# <17> AGP8X_DET# +1.5VS AGPAND LVDS MUXED SIGNALS Note: PLACE CLOSE TO U27 (NB RC300M) R576 Rb B 324_0402_1% 216RC300M_BGA_718 +3VS AGPREF_8X PLACE CLOSE TO CONNECTOR R577 Rc 100_0402_1% R945 NAGP@47K_0402 Ra Rb Rc 8X(M9+M10@) 4X(NAGP@) 169_0402_1% 52.1_0402_1% 324_0402_1% 1K_0402_1% 100_0402_1% 1K_0402_1% AGP8X_DET# ATI request +1.5VS +3VS 0.1U_0402_10V6K C551 + C553 C554 C555 0.1U_0402_10V6K C556 C557 0.1U_0402_10V6K C558 0.1U_0402_10V6K C559 C560 C561 +1.5VS 10U_0805_10V4Z 0.1U_0402_10V6K C632 C563 C562 C564 0.1U_0402_10V6K C565 C566 0.1U_0402_10V6K C567 0.1U_0402_10V6K C568 C569 @0.01U_0402_16V7Z C947 C948 @0.01U_0402_16V7Z @0.01U_0402_16V7Z @0.01U_0402_16V7Z @0.01U_0402_16V7Z C864 C949 C950 C935 C936 C933 C934 C951 47U_B_6.3VM 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K +1.5VS C552 + 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K @0.01U_0402_16V7Z @0.01U_0402_16V7Z @0.01U_0402_16V7Z @0.01U_0402_16V7Z @0.01U_0402_16V7Z +1.5VS 0.1U_0402_10V6K A 0.1U_0402_10V6K C570 C571 0.1U_0402_10V6K C572 47U_B_6.3VM C573 0.1U_0402_10V6K C574 C575 C576 C577 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K C578 C938 C940 C942 C944 C946 C937 C939 C941 C943 C945 A 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K L 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K Note: PLACE CLOSE TO U27 (NB RC300M) Compal Electronics, Inc. ATI RC300M-AGP, ALINK BUS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 10 of 66 5 4 3 2 1 D D +3VS L58 +2.5VS FBM-11-160808-121-T_0603 C586 L59 0.1U_0402_10V6K KC FBM-L11-201209-221LMAT_0805 U27D PART 4 OF 6 TXB0-_NB <25> TXB0+_NB <25> TXB1-_NB <25> TXB1+_NB <25> TXB2-_NB <25> TXB2+_NB <25> TXBCLK-_NB <25> TXBCLK+_NB <25> C587 0.1U_0402_10V6K +1.8VS KC FBM-L11-201209-221LMAT_0805 L60 C588 0.1U_0402_10V6K L61 KC FBM-L11-201209-221LMAT_0805 C589 C 0.1U_0402_10V6K LVDS 0.1U_0402_10V6K +1.8VS TXA0-_NB <25> TXA0+_NB <25> TXA1-_NB <25> TXA1+_NB <25> TXA2-_NB <25> TXA2+_NB <25> TXACLK-_NB <25> TXACLK+_NB <25> C590 PLLVDD_18 L62 KC FBM-L11-201209-221LMAT_0805 C591 C592 C593 10U_0805_16V4Z PLLVSS_18 0.1U_0402_10V6K 0.1U_0402_10V6K RED_R GREEN_R BLUE_R HSYNC_R VSYNC_R 7 1 5 _ 0 4 0 2 _ 1 %NB_RSET R584 +1.8VS KC FBM-L11-201209-221LMAT_0805 0.1U_0402_10V6K L63 C595 C596 +1.8VS_LPVDD LPVSS C594 0.1U_0402_10V6K 10U_0805_16V4Z LVSSR +1.8VS KC FBM-L11-201209-221LMAT_0805 R585 0_0402_5% RC300M_X1 RC300M_X2 <24> REFCLK1_NB 0.1U_0402_10V6K L64 CLK_NB_BCLK CLK_NB_BCLK# R588 68_0402_5% wait 1% new part @10_0402_5% C598 COMPS_R 0.1U_0402_10V6K DDCCLK_R C601 DDCDATA_R 10U_0805_16V4Z D CPUCLK_STP# CLK_AGP_66M CLK_MEM_66M <5,26,56> PCI_RST# <26,30,31,34,35,36,43,46> +3VS B CPUCLK_STP# G <24> CLK_MEM_66M CLK_MEM_66M C600 Q97 @2N7002 1N_SOT23 @15P_0402_50V8J <24> CLK_AGP_66M C599 LUMA_R S R587 <24> CLK_NB_BCLK <24> CLK_NB_BCLK# SVID CRMA_R CLK_AGP_66M C +1.8VS_LVDDR CRT +1.8VS B X2 27M_TV R592 R591 27M_TV_R NAGP@22_0402_5% R589 CLK. GEN. @10_0402_5% R590 C602 @0_0402_5% +3VS 1K_0402_5% NAGP@27MHZ_20P_6N C603 216RC300M_BGA_718 NAGP@0.1U_0402_16V7K @15P_0402_50V8J L L Note: PLACE CLOSE TO U27 (NB CHIP) Note: PLACE CLOSE TO U27 (NB CHIP) C604 RC300M_X1 CRMA_R LUMA_R COMPS_R NAPG@0_0402_5%TV_CRMA NAPG@0_0402_5%TV_LUMA NAPG@0_0402_5%TV_COMPS R597 R598 R599 TV_CRMA <17,41,48> TV_LUMA <17,41,48> TV_COMPS <17,41,48> R593 @1M_0402_1% @18P_0402_50V8K Y4 @14.31818MHZ_20P_6X1430004201 C605 RC300M_X2 L <17,25> <17,25> <17,25> CRT_R CRT_G CRT_B Note: PLACE CLOSE TO U6 (VGA CHIP) CRT_R R594 CRT_G R595 CRT_B R596 @18P_0402_50V8K NAPG@0_0402_5%R E D _ R NAPG@0_0402_5%GREEN_R NAPG@0_0402_5%BLUE_R RP103 A <17,25> CRT_HSYNC <17,25> CRT_VSYNC CRT_HSYNC CRT_VSYNC A HSYNC_R VSYNC_R NAGP@0_4P2R_0402_5% RP104 DDCCLK_R DDCDATA_R 3VDDCCL 3VDDCDA 3 V D D C C L <17,25> 3 V D D C D A <17,25> Compal Electronics, Inc. NAGP@0_4P2R_0402_5% ATI RC300M-VIDEO I/F THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 11 of 66 5 4 3 +1.5VS 2 1 +2.5V U27E U27F PART 5 OF 6 D MEM I/F PWR CORE PWR D POWER GND C +VCC_CORE C AGP PWR CPU I/F PWR +1.5VS 216RC300M_BGA_718 +3VS M9-M10@0_0603_5% B B R418 +1.5VS ALINK PWR R419 NAGP@0_0603_5% +3VS +1.8VS 216RC300M_BGA_718 +1.8VS 0.1U_0402_10V6K C579 C580 C581 C582 10U_0805_10V4Z C583 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K A A Compal Electronics, Inc. ATI RC300M-POWER THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 12 of 66 5 4 3 R420 R422 R424 D A_AD30 R425 10K_0402_5% A_CBE#[0..3] D85 RB751V_SOD323 10K_0402_5% 4.7K_0402_5% D86 RB751V_SOD323 R427 A_AD29 R429 10K_0402_5% A_AD[31..30] : FSB CLK SPEED +3VS 4.7K_0402_5% BSEL1 <5,24> DEFAULT: 01 +3VS BSEL0 <5,24> A_AD18 R421 @4.7K_0402_5% R423 4.7K_0402_5% A_AD18 : ENABLE PHASE CALIBRATION +3VS DEFAULT: 0 00: 100 MHZ 01: 133 MHZ 10: 200MHZ 11:166 MHZ 0: DISABLE 1:ENABLE R426 @4.7K_0402_5% R428 4.7K_0402_5% A_AD29: STRAP CONFIGURATION +3VS A_AD17 @4.7K_0402_5% 1 A_AD[0..31] <10,26> A_AD[0..31] <10,26> A_CBE#[0..3] A_AD31 2 +3VS DEFAULT: 0 DEFAULT:1 00: 1.05V 01: 1.35V 11: 1.75V 10: 1.45V 0: REDUCEDE SET 1: FULL SET R430 A_AD28 R431 @10K_0402_5% A_AD28: SPREAD SPECTRUM ENABLE +3VS 4.7K_0402_5% DEFAULT:0 0: DISABLE 1: ENABLE <10,26> R434 A_AD27 R435 10K_0402_5% A_AD27: FrcShortReset# +3VS @4.7K_0402_5% A_PAR A_PAR R463 @4.7K_0402_5% R460 4.7K_0402_5% PAR: EXTENDED DEBUG MODE +3VS R438 R440 10K_0402_5% DEFAULT : 1 0: DEBUG MODE 1: NORMAL DEFAULT: 1 0: TEST MODE 1: NORMAL MODE A_AD26 D A_AD25/A_AD17 : CPU VOLTAGE[1..0] A_AD26 : ENABLE IOQ +3VS @4.7K_0402_5% DEFAULT: 1 C C 0: IOQ=1 1: IOQ=12 R443 A_AD25 R444 10K_0402_5% A_AD25/A_AD17 : CPU VOLTAGE[1..0] +3VS @4.7K_0402_5% DEFAULT: 10 00: 1.05V 01: 1.35V 11: 1.75V 10: 1.45V A_AD24 R448 10K_0402_5% AD25=1 DESTOP CPU AD25=0 MOBILE CPU AD17--DON'T CARE A_AD24 : MOBILE CPU SELECT +3VS DEFAULT: 1 0: BANIAS CPU 1: OTHER CPU R452 A_AD23 R454 10K_0402_5% A_AD23 : CLOCK BYPASS DISABLE +3VS @4.7K_0402_5% DEFAULT: 1 0: TEST MODE 1: NORMAL B B A_AD22 R457 A_AD22 : OSC PAD OUTPUT PCICLK @4.7K_0402_5% DEFAULT : 1 0:PCICLK OUT 1: OSC CLK OUT R461 A_AD21 R462 10K_0402_5% A_AD21 : AUTO_CAL ENABLE +3VS @4.7K_0402_5% DEFAULT : 1 0: DISABLE 1: ENABLE A_AD20 R464 @4.7K_0402_5% R465 4.7K_0402_5% A_AD20 : INTERNAL CLK GEN ENABLE +3VS DEFAULT : 0 0: DISABLE 1: ENABLE A_CBE#3 R466 @4.7K_0402_5% R467 @4.7K_0402_5% A_CBE#3: NOT USED +3VS A A A_CBE#0 R468 @4.7K_0402_5% R469 @4.7K_0402_5% A_CBE#0 :NO USED +3VS Compal Electronics, Inc. ATI RC300M-SYSTEM STRAP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 13 of 66 5 4 3 2 1 +2.5V JP24 <9,15,16> <9,15,16> DDRA_SDQS[0..7] <9,15,16> DDRA_ADD[0..15] <9,15,16> DDRA_SDQ[0..63] DDRA_SDQ[0..63] R472 DDRA_SDQS[0..7] DDRA_SDQ8 DDRA_SDQ12 DDRA_SDQS1 DDRA_SDQ10 DDRA_SDM1 DDRA_SDQ14 0.1U_0402_10V6K 1K_0603_1% DDRA_ADD[0..15] DDRA_SDM[0..7] R473 C412 1K_0603_1% Group 0 sweep Group 1 D <9> <9,16> C DDRA_SDQ1 DDRA_SDQS0 DDRA_SDQ5 DDRA_SDM0 DDRA_SDQ3 DDRA_SDQ7 DDRA_SDQ16 DDRA_SDQ20 DDRA_SDQS2 DDRA_SDQ18 DDRA_SDM2 DDRA_SDQ22 DDRA_SDQ25 DDRA_SDQS3 DDRA_SDQ29 DDRA_SDM3 DDRA_SDQ27 DDRA_SDQ31 DDRA_ADD12 DDRA_ADD9 DDRA_ADD11 DDRA_ADD8 DDRA_ADD5 DDRA_ADD3 DDRA_ADD1 DDRA_ADD4 DDRA_ADD2 DDRA_ADD0 DDRA_ADD13 DDRA_WE# DDRA_CS#0 DDRA_RAS# DDRA_CAS# DDRA_CS#1 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ35 DDRA_SDQ40 DDRA_SDQ39 DDRA_SDQ44 DDRA_SDQS5 DDRA_SDM5 DDRA_SDQ42 DDRA_SDQ46 DDRA_CLK0 D L Group 0 sweep Group 1 DDRA_CKE_R1 <9,15,16> <9,16> DDRA_CKE_R0 DDRA_WE# DDRA_CS#0 <9,16> DDRA_RAS# DDRA_CAS# DDRA_CS#1 B Group 6 sweep Group 7 DDRA_SDQS7 DDRA_SDQ58 DDRA_SDM7 DDRA_SDQ62 DDRA_SDQ48 DDRA_SDQ52 DDRA_SDQ49 DDRA_SDQ53 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ54 DDRA_SDQ55 C <9,15,16> <9,15,16> <9,16> DDRA_CLK1# DDRA_CLK1 <15,24,27> DDRA_VREF trace width of 20mils and space 20mils(min) <9> <9> B Group 6 sweep Group 7 SMB_CK_CLK2 AMP_1565918-1 DIMM0 REVERSE +2.5V System Memory Decoupling caps C413 C414 C415 C416 C417 C418 C419 C420 C421 C422 C423 C424 C425 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 10U_0805_6.3V6M C426 C427 C428 C429 C430 C431 C432 C433 C434 C435 C436 C437 C438 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 10U_0805_6.3V6M +2.5V A A Compal Electronics, Inc. DDR-SODIMM SLOT1 LA-1811 Wednesday, September 24, 2003 5 4 3 2 14 1 66 5 <9,14,16> DDRA_SDQ[0..63] <9,14,16> DDRA_SDQS[0..7] <9,14,16> DDRA_ADD[0..15] 4 3 2 +2.5V DDRA_SDQ[0..63] +2.5V 1 +2.5V +2.5V DDRA_SDQS[0..7] C392 DDRA_SDM[0..7] 1K_0603_1% DDRA_SDQ9 DDRA_SDQ13 DDRA_SDQS1 DDRA_SDM1 DDRA_SDQ11 DDRA_SDQ0 DDRA_SDQ15 DDRA_SDQ4 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ6 DDRA_SDQ7 DDRB_VREF R471 Group 0 sweep Group 1 C393 0.1U_0402_10V6K 1K_0603_1% D D <9> <9> L DDRB_VREF trace width of 20mils and space 20mils(min) Group 0 sweep Group 1 DDRA_CLK3 DDRA_CLK3# DDRA_SDQ17 DDRA_SDQ21 DDRA_SDQS2 DDRA_SDM2 DDRA_SDQ19 DDRA_SDQ24 DDRA_SDQ23 DDRA_SDQ28 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ30 DDRA_SDQ31 <9,16> DDRA_CKE_R3 R1122 10_0402_5% <9,16> DDRA_CKE_R2 R1121 10_0402_5% RP26 RP29 RP32 RP35 RP38 RP39 C C DDRA_CKE3 DDRA_CKE2 DDRA_SMA7 DDRA_SMA5 DDRA_SMA6 DDRA_SMA4 DDRA_SMA10 DDRA_SMA13 DDRA_SMA14 DDRA_SRAS# RP42 <9,14,16> <9,16> DDRA_SMA15 DDRA_WE# DDRA_WE# R392 DDRA_CS#2 R401 DDRA_SMA15 DDRA_SDQ32 DDRA_SDQ36 DDRA_SDQS4 DDRA_SDQ34 DDRA_SDM4 DDRA_SDQ38 DDRA_SDQ41 DDRA_SDQS5 DDRA_SDQ45 DDRA_SDM5 DDRA_SDQ43 DDRA_SDQ47 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ59 DDRA_SDQ48 DDRA_SDQ63 DDRA_SDQ52 DDRA_SDQS6 DDRA_SDM6 DDRA_SDQ50 DDRA_SDQ54 R391 DDRA_CLK4# DDRA_SWE# 10_0402_5% 10_0402_5% DDRA_ADD15 10_0402_5% <9,14,16> DDRA_RAS# <9,14,16> DDRA_CAS# <9,16> DDRA_CS#3 R390 10_0402_5% R396 DDRA_SRAS# 10_0402_5% R393 10_0402_5% R402 DDRA_SCS#3 10_0402_5% DDRA_RAS# DDRA_CS#3 <9> B B Group 6 sweep Group 7 <14,24,27> <14,24,27> SMB_CK_DAT2 SMB_CK_CLK2 +3VS +3VS DIMM1 STANDARD System Memory Decoupling caps A C394 C395 C396 C397 C398 C399 C400 C401 C402 22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 10U_0805_6.3V6M 10U_0805_6.3V6M C403 C404 C405 C406 C407 C408 C409 C410 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K A Compal Electronics, Inc. DDR-SODIMM SLOT2 LA-1811 Wednesday, September 24, 2003 5 4 3 2 15 1 66 5 4 3 2 1 DDR Termination resistors & Decoupling caps +1.25VS +1.25VS DDRA_SDQ8 DDRA_SDQ30 DDRA_SDQ13 DDRA_SDQ27 56 _0804_8P4R_5% RP68 D DDRA_SDQ32 DDRA_SDQ37 56 _0804_8P4R_5% RP69 DDRA_SDQ10 DDRA_SDM1 DDRA_SDQ14 56 _0804_8P4R_5% RP70 DDRA_CKE_R0 DDRA_CKE_R1 DDRA_CKE_R1 <9,14> <9,14> 56 _0804_8P4R_5% RP71 +2.5V 56 _0804_8P4R_5% RP73 DDRA_ADD3 DDRA_ADD7 DDRA_ADD5 DDRA_SDQ11 DDRA_SDQ15 D DDRA_SDQ34 DDRA_SDM4 DDRA_SDQ38 33_0404_4P2R_5% RP75 DDRA_SDQ35 DDRA_SDQ39 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 33_0804_8P4R_5% RP78 DDRA_ADD1 DDRA_ADD10 RP74 RP76 +1.25VS +2.5V DDRA_SDQ1 DDRA_SDQS0 DDRA_SDQ42 DDRA_SDQ43 RP81 56 _0804_8P4R_5% RP77 56 _0804_8P4R_5% RP79 DDRA_SDQ6 DDRA_SDQ7 DDRA_SDQ2 DDRA_ADD4 DDRA_ADD2 DDRA_SDQ45 DDRA_SDM5 DDRA_SDQ41 C493 C494 C495 C496 C497 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 4.7U_0805_16V6K 33_0804_8P4R_5% RP84 56 _0804_8P4R_5% DDRA_ADD0 DDRA_ADD14 DDRA_RAS# DDRA_SDQ16 DDRA_SDQ21 DDRA_SDQ57 DDRA_WE# DDRA_SDQ18 DDRA_SDM2 DDRA_SDQ22 DDRA_WE# <9,14,15> DDRA_CS#0 DDRA_CS#3 <9,14> <9,15> 56 _0804_8P4R_5% RP85 33_0404_4P2R_5% DDRA_CS#0 56 _0804_8P4R_5% RP86 DDRA_SDQ62 DDRA_SDQS7 DDRA_SDQ58 C 56 _0804_8P4R_5% RP88 33_0404_4P2R_5% DDRA_SDQ19 DDRA_SDQ23 +1.25VS DDRA_SDQ60 <9,14,15> <9,14,15> 33_0804_8P4R_5% 56 _0804_8P4R_5% RP83 C 56 _0804_8P4R_5% DDRA_RAS# DDRA_CAS# DDRA_ADD12 DDRA_SDQ63 DDRA_SDQ52 33_0402_5% RP72 DDRA_CKE_R3 DDRA_CKE_R2 DDRA_CKE_R3 DDRA_CKE_R2 DDRA_CS#1 DDRA_CS#2 DDRA_CS#1 RP90 <9,15> <9,15> RP91 33_0404_4P2R_5% RP92 DDRA_SDQ25 DDRA_SDQS3 56 _0804_8P4R_5% DDRA_SDQ49 DDRA_SDQS6 <9,14> 33_0404_4P2R_5% 56 _0804_8P4R_5% RP93 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ51 56 _0804_8P4R_5% <9,14,15> DDRA_SDQ[0..63] DDRA_SDQS[0..7] <9,14,15> B DDRA_ADD[0..15] DDRA_ADD[0..15] <9,14,15> DDRA_SDM[0..7] DDRA_SDM[0..7] B +2.5V C451 C452 C453 C454 C455 C456 C457 C458 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K +1.25VS +1.25VS C459 C460 C461 C462 C463 C464 C465 C466 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K C467 C468 C469 C470 C471 C472 C473 C474 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K C483 C484 C485 C486 C487 C488 C489 C490 +1.25VS +1.25VS A + C491 @100U_D2_10M_R45 + C492 A 100U_D2_10M_R45 Compal Electronics, Inc. DDR Termination Resistors LA-1811 Wednesday, September 24, 2003 5 4 3 2 16 1 66 5 4 AGP_ST[0..2] D C 1 8 4 @10P_0402_50V8K @10_0402_5% AGP_CBE#0 AGP_CBE#1 AGP_CBE#2 AGP_CBE#3 CLK_AGP_EXT_66M NB_RST# AGP_REQ# AGP_GNT# AGP_PAR AGP_STOP# AGP_DEVSEL# AGP_TRDY# AGP_IRDY# AGP_FRAME# <8,26,39> NB_RST# <10> AGP_REQ# <10> AGP_GNT# <10> AGP_PAR <10> AGP_STOP# <10> AGP_DEVSEL# <10> AGP_TRDY# <10> AGP_IRDY# <10> AGP_FRAME# <10,26,31,35,36> PCI_PIRQA# 0.1U_0402_10V6K AGP8X AGP_SBA0 AGP_SBA1 AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA6 AGP_SBA7 C185 <10> AGP_SBSTB <10> AGP_SBSTB# B (15mil) R264 137_0603_1% If M10+P POP 47_0603_1% <10> AGP_DBI_HI/PIPE# If M9+P POP 137_0603_1% <10> AGP_DBI_LO For 8Mx32 VGA DRAM only DRAM128M ID_Disable GPIO8 STRAP_A +3VS XTALIN_SS STRAP_R STRAP_S STRAP_G R241 R242 M10@10K_0402_5% @10K_0402_5% STRAP_H R243 R244 M10@10K_0402_5% @10K_0402_5% STRAP_J R245 R246 @10K_0402_5% @10K_0402_5% STRAP_K R247 R248 @10K_0402_5% @10K_0402_5% STRAP_O R250 @10K_0402_5% STRAP_L R252 @10K_0402_5% STRAP_M R254 @10K_0402_5% STRAP_N R255 @10K_0402_5% STRAP_R R256 @10K_0402_5% STRAP_S R257 @10K_0402_5% STRAP_T R259 R260 @10K_0402_5% @10K_0402_5% GPIO9 +3VS GPIO11 DATA D D C _ D A T <10,25> D D C _ C L K <10,25> CLK TXA0TXA0+ TXA1TXA1+ TXA2TXA2+ R253 GPIO12 10K_0402_5% TXA0TXA0+ TXA1TXA1+ TXA2TXA2+ <25> <25> <25> <25> <25> <25> TXACLKTXACLK+ TXB0TXB0+ TXB1TXB1+ TXB2TXB2+ <25> <25> <25> <25> <25> <25> <25> <25> TXBCLKTXBCLK+ <25> <25> ENAVDD <10,25,46> R829 ENABLT# M9@0_0402_5% R830 M10@0_0402_5% Divider Circuit for 1.2V/(1.5)dc XTALIN from 3.3Vdc OSC out M9+X M10-P Ra 180_0603_5% 261_0603_1% Rb 150_0402_5% 150_0402_5% R261 10K_0402_5% Ra FREQOUT R262 ENABLT# 27MHZ_15P C186 0.1U_0402_10V6K TMDS SSC DAC2 CLK AGP_RSET R274 spread sprum +3VS 0.1U_0402_10V6K Spread % Setting for Freq. Range Fin>Fout>Fin-1.25% C188 Fin>Fout>Fin-3.75% U7 R268 2.2U_0603_6.3V4Z C191 FCM2012C-800_0805 C190 0.1U_0402_10V6K XTALIN_SS 22_0402_5% +3VS R269 10K_0402_5% R270 10K_0402_5% SS% 499_0402_1% R271 @10K_0402_5% R273 3 V D D C D A <11,25> 3 V D D C C L <11,25> W180-01GT_SO8 10K_0402_5% +3VS A L Note: PLACE CLOSE TO U6 (VGA M9+X/M10-P) 1K_0603_5% Compal Electronics, Inc. SUSSTAT# R276 SA002160E00(0301021300) Leave These Pin No Connecting, When Using M10-P Internal Spread Spectrum 5 L13 C189 0.1U_0402_10V6K FREQOUT +3VS (15mil) 10K_0402_5% B @15P_0402_50V8J <10,25> SS% 0 1 CRT_R <11,25> CRT_G <11,25> CRT_B <11,25> CRT_HSYNC <11,25> CRT_VSYNC <11,25> R272 3VDDCDA 3VDDCCL C187 Rb M10_BKOFF# <25> 100K_0402_5% CRT_R CRT_G CRT_B CRT_HSYNC CRT_VSYNC XTALIN 180_0603_5% R263 150_0402_5% Selection Table For W180 R267 1.5V OSC out for M9+X 1.2V OSC out for M10-P 3.3V OSC out for W180 X1 For VGA DDR SSOUT PIR LAYOUT 92.09.01 0_0402_5% THRM 715_0603_1% TV_CRMA TV_LUMA TV_COMPS C +3VS TXACLKTXACLK+ TXB0TXB0+ TXB1TXB1+ TXB2TXB2+ ENAVDD XTALIN R275 @10K_0402_5% GPIO3 DVOMODE R258 DAC1 A @10K_0402_5% R240 GPIO2 (25mil) <10> AGP8X_DET# SSOUT R238 STRAP_F GPIO1 TXBCLKTXBCLK+ SSIN SSIN STRAP_E D GPIO0 M10@1K_0603_1% PIR LAYOUT 92.09.01 AGP_SBSTB AGP_SBSTB# (15mil) R936 <10> @4.7K_0402_5% @10K_0402_5% GPIO6 R239 M9-M10@1K_5% <10> R236 GPIO5 (25 mil) AGP_DBI_HI/PIPE# AGP_DBI_LO R266 @10K_0402_5% STRAP_D M10@1K_0603_1% 0_0402_5% VREFG R265 <11,41,48> TV_CRMA <11,41,48> TV_LUMA <11,41,48> TV_COMPS @10K_0402_5% R233 GPIO4 R234 @1K_0402_5% MCLK_SPREAD R 2 3 7 R232 STRAP_B VGA_Disable GPIO7 R955 @10K_0402_5% R235 +1.5VS AGP8X_DET# Low: AGP3.0 +3VS +3VS PIR LAYOUT 92.09.01 AGP_ST0 AGP_ST1 AGP_ST2 (Closed to M26) AGP, DAC & LVDS INTERFACE R1149 @10K_0402_5% GPIO13 AGP_STP# AGP_BUSY# AGP_RBF# AGP_ADSTB0 AGP_ADSTB1 AGP_ADSTB0# AGP_ADSTB1# <10> VREF_8X_IN 1 SUSSTAT# <10> AGP_WBF# <10,27> AGP_STP# <10,27> AGP_BUSY# <10> AGP_RBF# <10> AGP_ADSTB0 <10> AGP_ADSTB1 <10> AGP_ADSTB0# <10> AGP_ADSTB1# STRAP_G STRAP_H STRAP_J STRAP_K STRAP_D STRAP_E STRAP_F STRAP_B STRAP_A STRAP_O DRAM128M STRAP_L STRAP_M STRAP_N STRAP_T PCI/AGP <24> CLK_AGP_EXT_66M C ZV PORT / EXT TMDS / GPIO / ROM AGP_CBE#[0..3] <10> AGP_CBE#[0..3] R249 M10-P/(M9+X) (1/6) AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31 AGP_SBA[0..7] <10> AGP_ST[0..2] 2 +3VS LVDS <10> AGP_AD[0..31] <10> AGP_SBA[0..7] 3 U6A AGP_AD[0..31] 1K_0603_5% ATI M10-P & M9+X (AGP BUS) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 17 of 66 5 4 3 <22> NMAA[0..13] 1 MEMORY INTERFACE A D <22> NMDA[0..63] 2 NMDA[0..63] NMAA[0..13] D NDQMA[0..7] <22> NDQMA[0..7] <22> NDQSA[0..7] NDQSA[0..7] U6B C B M10-P/(M9+X) (2/6) NMAA0 NMAA1 NMAA2 NMAA3 NMAA4 NMAA5 NMAA6 NMAA7 NMAA8 NMAA9 NMAA10 NMAA11 NMAA12 NMAA13 C NDQMA0 NDQMA1 NDQMA2 NDQMA3 NDQMA4 NDQMA5 NDQMA6 NDQMA7 MEMORY INTERFACE A NMDA0 NMDA1 NMDA2 NMDA3 NMDA4 NMDA5 NMDA6 NMDA7 NMDA8 NMDA9 NMDA10 NMDA11 NMDA12 NMDA13 NMDA14 NMDA15 NMDA16 NMDA17 NMDA18 NMDA19 NMDA20 NMDA21 NMDA22 NMDA23 NMDA24 NMDA25 NMDA26 NMDA27 NMDA28 NMDA29 NMDA30 NMDA31 NMDA32 NMDA33 NMDA34 NMDA35 NMDA36 NMDA37 NMDA38 NMDA39 NMDA40 NMDA41 NMDA42 NMDA43 NMDA44 NMDA45 NMDA46 NMDA47 NMDA48 NMDA49 NMDA50 NMDA51 NMDA52 NMDA53 NMDA54 NMDA55 NMDA56 NMDA57 NMDA58 NMDA59 NMDA60 NMDA61 NMDA62 NMDA63 NDQSA0 NDQSA1 NDQSA2 NDQSA3 NDQSA4 NDQSA5 NDQSA6 NDQSA7 +2.5VS R475 1K_0402_1% NMRASA# NMCASA# NMWEA# NMCSA0# NMCSA1# NMCKEA NMCLKA0 NMCLKA0# NMCLKA1 NMCLKA1# NMRASA# <22> NMCASA# <22> NMWEA# <22> MVREFD (25 mil) C498 R478 0.1U_0402_10V6K 1K_0402_1% B NMCSA0# <22> NMCSA1# <22> NMCKEA <22> +2.5VS NMCLKA0 <22> NMCLKA0# <22> NMCLKA1 <22> NMCLKA1# <22> R486 M10@1K_0402_1% MVREFS (25 mil) MVREFD C503 R487 MVREFS M10@0.1U_0402_16V4Z M10@1K_0402_1% SA002160E00(0301021300) Poped for M10-P Depoped for M9+X A A Compal Electronics, Inc. ATI M10-P/M9+X DDR-A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 18 of 66 5 4 3 2 1 D D MEMORY INTERFACE B <23> NMDB[0..63] <23> NMAB[0..13] <23> NDQMB[0..7] <23> NDQSB[0..7] NMDB[0..63] NMAB[0..13] NDQMB[0..7] NDQSB[0..7] U6C C B M10-P/(M9+X) (3/6) NMAB0 NMAB1 NMAB2 NMAB3 NMAB4 NMAB5 NMAB6 NMAB7 NMAB8 NMAB9 NMAB10 NMAB11 NMAB12 NMAB13 C NDQMB0 NDQMB1 NDQMB2 NDQMB3 NDQMB4 NDQMB5 NDQMB6 NDQMB7 MEMORY INTERFACE B NMDB0 NMDB1 NMDB2 NMDB3 NMDB4 NMDB5 NMDB6 NMDB7 NMDB8 NMDB9 NMDB10 NMDB11 NMDB12 NMDB13 NMDB14 NMDB15 NMDB16 NMDB17 NMDB18 NMDB19 NMDB20 NMDB21 NMDB22 NMDB23 NMDB24 NMDB25 NMDB26 NMDB27 NMDB28 NMDB29 NMDB30 NMDB31 NMDB32 NMDB33 NMDB34 NMDB35 NMDB36 NMDB37 NMDB38 NMDB39 NMDB40 NMDB41 NMDB42 NMDB43 NMDB44 NMDB45 NMDB46 NMDB47 NMDB48 NMDB49 NMDB50 NMDB51 NMDB52 NMDB53 NMDB54 NMDB55 NMDB56 NMDB57 NMDB58 NMDB59 NMDB60 NMDB61 NMDB62 NMDB63 NDQSB0 NDQSB1 NDQSB2 NDQSB3 NDQSB4 NDQSB5 NDQSB6 NDQSB7 NMRASB# NMCASB# NMWEB# NMCSB0# NMCSB1# NMCKEB NMCLKB0 NMCLKB0# NMCLKB1 NMCLKB1# NMRASB# <23> NMCASB# <23> NMWEB# <23> B NMCSB0# <23> NMCSB1# <23> NMCKEB <23> NMCLKB0 <23> NMCLKB0# <23> NMCLKB1 <23> NMCLKB1# <23> +1.8VS R509 R510 R511 4.7K_0402_5% 4.7K_0402_5% 47_0603_1% (15mil) SA002160E00(0301021300) A A Compal Electronics, Inc. ATI M10-P/M9+X DDR-B THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 19 of 66 5 4 3 2 POWER INTERFACE U6D M10-P/(M9+X) (4/6) +2.5VS D 1 +2.5VDDRH D +3VS 0.1U_0402_10V6K C192 C193 C194 0.01U_0402_16V7K C195 C196 22U_1206_10V4Z +VDD_MEMPLL1.8 0.1U_0402_10V6K 0.01U_0402_16V7K +VDD_PLL1.8 Note: PLACE CLOSE TO U6 (VGA ATI M10P/M9+X) L +1.5VS 0.1U_0402_10V6K +3VS C197 C198 C199 0.01U_0402_16V7K C92 C200 C201 0.1U_0402_10V6K C862 0.1U_0402_10V6K C863 C865 C866 0.01U_0402_16V7K 0.1U_0402_10V6K C867 C868 C869 0.1U_0402_10V6K C870 C871 22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.01U_0402_16V7K 0.1U_0402_10V6K I/O POWER +VDD_DAC2.5 C 0.1U_0402_10V6K L15 CHB1608U301_0603 (20 mil) +2.5VS CHB1608U301_0603 C203 C202 2.2U_0603_6.3V4Z C204 0.1U_0402_10V6K +VDD_PLL1.8 L17 CHB1608U301_0603 +1.5VS M10@0_0402_5% M10@0_0402_5% R279 M10@0_0805_5% C208 C209 0.1U_0402_10V6K +1.8VS C210 10U_0805_6.3V6M 0.1U_0402_10V6K +VDD_MEMPLL1.8 Poped for M10-P L18 L19 (20 mil) +VDDC1.5 M10@0_0603_5% +LVDDR R281 M9@0_0805_5% CHB1608U301_0603 +VDD_PNLIO2.5 Poped for M9+X R282 CHB1608U301_0603 +VDD_DAC1.8 R280 +1.8VS (20 mil) +1.8VS 0.1U_0402_10V6K R277 R278 Poped for M10-P B C207 10U_0805_6.3V6M Poped for M10-P C 0.1U_0402_10V6K L16 (20 mil) +2.5VS +2.5VS C205 1U_0603_10V6K +VDD_PNLPLL1.8 C206 0.1U_0402_10V6K +2.5VDDRH L14 (20 mil) +1.5VS 0.1U_0402_10V6K M9@0_0603_5% C211 +VDD_PNLIO1.8 +VDD_PNLIO1.8 +VDD_PNLPLL1.8 (20 mil) +1.8VS C212 10U_0805_6.3V6M +1.8VS CHB1608U301_0603 2.2U_0603_6.3V4Z C931 C213 0.1U_0402_10V6K 0.1U_0402_10V6K Poped for M9+X B +VDD_PNLPLL1.8 +VDD_PNLIO1.8 L20 (20 mil) 0.1U_0402_10V6K CHB1608U301 +VDD_DAC1.8 +VDD_DAC2.5 C214 +VDD_DAC1.8 +VDD_DAC1.8 C215 C216 +1.8VS C217 10U_0805_6.3V6M As close as possible to related pin 0.1U_0402_10V6K 0.1U_0402_10V6K +VDD_PNLIO2.5 +VDDC1.5 +LVDDR L21 +VDD_PNLIO1.8 (20 mil) 0.1U_0402_10V6K CHB1608U301 +2.5VS C967 C218 C219 C968 C969 C970 C220 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 10U_0805_6.3V6M 0.1U_0402_10V6K SA002160E00(0301021300) A A Compal Electronics, Inc. ATI M10-P/M9+X POWER-A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 20 of 66 5 4 3 2 1 U6E M10-P/(M9+X) (5/6) +VGA_CORE +VGA_CORE U6F M10-P/(M9+X) (6/6) D D M10-P&M9+X COMMON +VGA_CORE_CI CORE POWER CORE POWER POWER INTERFACE M10-P ONLY C C M9+X ONLY SA002160E00(0301021300) +VGA_CORE + B C222 + C223 C224 C225 C226 C227 C228 C229 C230 C231 22U_1206_10V4Z 22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K0.1U_0402_10V6K 0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K 100U_D2_10M_R45 C221 @47U_D2_6.3VM B SA002160E00(0301021300) +2.5VS C232 C233 C234 C235 C236 C237 C238 C239 22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K0.01U_0402_16V7K 0.01U_0402_16V7K +VGA_CORE_CI L22 480MIL (20 mil) CHB1608U301 C240 +VGA_CORE C241 C242 0.1U_0402_10V6K 0.1U_0402_10V6K +2.5VS JOPEN5 PAD-OPEN 4x4m 10U_0805_6.3V6M +1.2VS_VGA As close as ppossible to related pin (12A,480mils ,Via NO.=24) C243 C244 C245 C246 C247 C248 C249 C250 22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K0.01U_0402_16V7K 0.01U_0402_16V7K A A As close as ppossible to related pin Compal Electronics, Inc. ATI M10-P/M9+X POWER-B THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 21 of 66 5 4 3 2 +2.5VS VGA DDR FOR CHANNEL A +2.5VS C504 C507 C505 C506 0.1U_0402_10V6K 0.1U_0402_10V6K 10U_0805_10V3M C510 C508 C509 0.1U_0402_10V6K 0.1U_0402_10V6K 1 C513 C511 C512 0.1U_0402_10V6K 0.1U_0402_10V6K 10U_0805_10V3M C514 C515 0.1U_0402_10V6K 0.1U_0402_10V6K D D 10U_0805_10V3M 10U_0805_10V3M As close as ppossible to related pin As close as ppossible to related pin NMAA[0..13] <18> NMAA[0..13] NMDA[0..63] <18> NMDA[0..63] NDQMA[0..7] <18> NDQMA[0..7] NDQSA[0..7] U28 <18> NDQSA[0..7] U29 NMAA0 NMAA1 NMAA2 NMAA3 NMAA4 NMAA5 NMAA6 NMAA7 NMAA8 NMAA9 NMAA10 NMAA11 NMAA12 NMAA13 C +2.5VS NMDA23 NMDA22 NMDA21 NMDA20 NMDA19 NMDA18 NMDA17 NMDA16 NMDA31 NMDA30 NMDA29 NMDA28 NMDA27 NMDA26 NMDA25 NMDA24 NMDA7 NMDA6 NMDA5 NMDA4 NMDA3 NMDA2 NMDA1 NMDA0 NMDA15 NMDA14 NMDA13 NMDA12 NMDA11 NMDA10 NMDA9 NMDA8 NDQMA2 NDQMA3 NDQMA0 NDQMA1 R488 NDQSA2 NDQSA3 NDQSA0 NDQSA1 1K_0402_1% (25mil) VREF_1 R490 1K_0402_1% C516 0.1U_0402_10V6K <18> NMRASA# <18> NMCASA# <18> NMWEA# <18> NMCSA0# <18> <18> NMCLKA0 NMRASA# NMCASA# NMWEA# NMCSA0# NMAA0 NMAA1 NMAA2 NMAA3 NMAA4 NMAA5 NMAA6 NMAA7 NMAA8 NMAA9 NMAA10 NMAA11 NMAA12 NMAA13 +2.5VS NDQMA6 NDQMA7 NDQMA4 NDQMA5 R489 NDQSA6 NDQSA7 NDQSA4 NDQSA5 1K_0402_1% (25mil) VREF_2 R491 C517 0.1U_0402_10V6K 1K_0402_1% NMRASA# NMCASA# NMWEA# NMCSA0# +2.5VS NMCKEA NMCKEA NMDA55 NMDA54 NMDA53 NMDA52 NMDA51 NMDA50 NMDA49 NMDA48 NMDA63 NMDA62 NMDA61 NMDA60 NMDA59 NMDA58 NMDA57 NMDA56 NMDA39 NMDA38 NMDA37 NMDA36 NMDA35 NMDA34 NMDA33 NMDA32 NMDA47 NMDA46 NMDA45 NMDA44 NMDA43 NMDA42 NMDA41 NMDA40 C +2.5VS NMCKEA NMCLKA0 <18> NMCLKA1 NMCLKA1 B B R625 56.2_0402_1% R626 56.2_0402_1% C628 10P_0402_50V8K <18> NMCLKA0# <18> NMCSA1# R627 56.2_0402_1% C629 10P_0402_50V8K R628 56.2_0402_1% NMCLKA0# <18> NMCLKA1# NMCLKA1# NMCSA1# NMCSA1# K4D263238A-GC K4D263238A-GC A A Compal Electronics, Inc. VGA DDR FOR CHANNEL A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 22 of 66 5 4 3 +2.5VS 2 VGA DDR FOR CHANNEL B +2.5VS C518 C519 C520 C521 C522 C523 C524 C525 C526 C527 22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.01U_0402_16V7K 0.01U_0402_16V7K 22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.01U_0402_16V7K 0.01U_0402_16V7K 1 C528 C529 C530 C531 C532 C533 C534 C535 C536 C537 22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.01U_0402_16V7K 0.01U_0402_16V7K 22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.01U_0402_16V7K 0.01U_0402_16V7K D D As close as ppossible to related pin As close as ppossible to related pin NMAB[0..13] <19> NMAB[0..13] NMDB[0..63] <19> NMDB[0..63] NDQMB[0..7] <19> NDQMB[0..7] U30 U31 NDQSB[0..7] <19> NDQSB[0..7] NMAB0 NMAB1 NMAB2 NMAB3 NMAB4 NMAB5 NMAB6 NMAB7 NMAB8 NMAB9 NMAB10 NMAB11 NMAB12 NMAB13 C +2.5VS NMDB7 NMDB6 NMDB5 NMDB4 NMDB3 NMDB2 NMDB1 NMDB0 NMDB23 NMDB22 NMDB21 NMDB20 NMDB19 NMDB18 NMDB17 NMDB16 NMDB15 NMDB14 NMDB13 NMDB12 NMDB11 NMDB10 NMDB9 NMDB8 NMDB31 NMDB30 NMDB29 NMDB28 NMDB27 NMDB26 NMDB25 NMDB24 NDQMB0 NDQMB2 NDQMB1 NDQMB3 R495 NDQSB0 NDQSB2 NDQSB1 NDQSB3 1K_0603_1% (25mil) VREF_3 R496 C538 0.1U_0402_10V6K <19> <19> <19> <19> 1K_0603_1% <19> <19> B NMRASB# NMCASB# NMWEB# NMCSB0# NMRASB# NMCASB# NMWEB# NMCSB0# +2.5VS 1K_0603_1% (25mil) C539 0.1U_0402_10V6K 1K_0603_1% NMCLKB1 <19> NMCLKB0# NMCSB1# +2.5VS NMCLKB1 B R630 56.2_0402_1% 56.2_0402_1% R632 C630 <19> NMRASB# NMCASB# NMWEB# NMCSB0# C NMCKEB R631 10P_0402_50V8K VREF_4 R497 <19> R629 NDQSB5 NDQSB7 NDQSB4 NDQSB6 NMCKEB NMCKEB NMDB47 NMDB46 NMDB45 NMDB44 NMDB43 NMDB42 NMDB41 NMDB40 NMDB63 NMDB62 NMDB61 NMDB60 NMDB59 NMDB58 NMDB57 NMDB56 NMDB39 NMDB38 NMDB37 NMDB36 NMDB35 NMDB34 NMDB33 NMDB32 NMDB55 NMDB54 NMDB53 NMDB52 NMDB51 NMDB50 NMDB49 NMDB48 NDQMB5 NDQMB7 NDQMB4 NDQMB6 R494 +2.5VS NMCLKB0 NMCLKB0 NMAB0 NMAB1 NMAB2 NMAB3 NMAB4 NMAB5 NMAB6 NMAB7 NMAB8 NMAB9 NMAB10 NMAB11 NMAB12 NMAB13 C631 10P_0402_50V8K 56.2_0402_1% NMCLKB0# <19> NMCSB1# NMCLKB1# 56.2_0402_1% NMCLKB1# NMCSB1# K4D263238A-GC K4D263238A-GC A A Compal Electronics, Inc. VGA DDR FOR CHANNEL B THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 23 of 66 A B C D E PIR BOM 92.09.01 +3VS F CLK_BCLK R193 @0_0402_5% CLK_BCLK# R194 @0_0402_5% G CK_ITP <5> CK_ITP# <5> H +3V_CLK L11 Width=40 mils 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K HB-1M2012-121JT03_0805 C118 C119 C120 C121 C122 C123 C124 C125 C126 0.1U_0402_10V6K 1 10U_0805_6.3V6M 0.1U_0402_10V6K 0.1U_0402_10V6K U5 1 0.1U_0402_10V6K PIR BOM 92.09.01 L12 +3V_VDD C127 10P_0402_50V8K XTALIN_CLK +3VS CHB2012U121_0805 C128 Y2 R963 14.318MHZ @1M_0402_5% C129 0.1U_0402_10V6K 10U_0805_6.3V6M VSSA XTALOUT_CLK 10P_0402_50V8K C130 CLK_BCLK R195 CK_BCLK 33_0402_1% R196 SMB_CK_CLK2 SMB_CK_DAT2 <14,15,27> SMB_CK_CLK2 <14,15,27> SMB_CK_DAT2 <27,46,48> VTT_PWRGD R197 CLK_BCLK# R200 33_0402_1% CLK_NB R201 33_0402_1% CK_BCLK <4> 49.9_0402_1% 49.9_0402_1% CK_BCLK# CK_BCLK# <4> CLK_NB_BCLK <11> +3VS <39> CLK_LPC_48M 2 <27> CLK_SB_48M <31> CLK_SD_48M <11> REFCLK1_NB <37> CLK_14M_CODEC <27> CLK_SB_14M <26> CLK_14M_APIC R1056 R1111 R209 R962 10K_0402_5% 10K_0402_5% 33_0402_1% 10K_0402_5% R206 R207 33_0402_1% 33_0402_1% R996 R215 R997 68_0402_5% 33_0402_1% 33_0402_1% R1068 @33_0402_1% 24/48# PCI33/66# CLK_48M CLK_SD FS2 FS1 FS0 R202 49.9_0402_1% R203 49.9_0402_1% CLK_NB# R204 33_0402_1% MEM_66M R205 33_0402_1% CLK_MEM_66M <11> AGP_66M R208 AGP_EXT_66M R 2 1 0 33_0402_1% M9_M10@33_0402_1% FS3 FS4 33_0402_1% R213 2 CLK_NB_BCLK# <11> CLK_AGP_66M <11> CLK_AGP_EXT_66M <17> CLK_ALINK_SB <26> CLK_IREF R218 475_0402_1% ICS951402AGT_TSSOP48 3 3 CLOCK FREQUENCY SELECT TABLE FS4 FS3 FS2 FS1 FS0 CPU MEM 0 0 0 1 0 200 200 0 0 0 0 1 133 133 0 0 0 0 0 100 100 With Spread Enabled… * +3V_CLK Spreaf OFF OR Center spread +/-0.3% R220 R221 R222 @10K_0402_5%@10K_0402_5% +3V_CLK R219 10K_0402_5% Note: 0 = PULL LOW 1 = PULL HIGH 4 <5,13> BSEL1 <5,13> BSEL0 D83 RB751V_SOD323 D84 RB751V_SOD323 @10K_0402_5% R223 10K_0402_5% FS1 FS0 FS2 FS3 FS4 PCI33/66# R998 R999 R224 R225 R226 R227 R228 10K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% @10K_0402_5% 4 A-LINK FREQ PCI33/66# = HIGH 66MHZ PCI33/66# = LOW 33MHZ Compal Electronics, Inc. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D E F Clock Generator Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 G Sheet 24 H of 66 5 4 3 2 LCD CONN L41 JP27 AT LEAST 60 MIL LCDVDD_A D 1 +3VS <17> <17> TXA2+ TXA2- TXA2+ TXA2- <17> <17> TXA1+ TXA1- TXA1+ TXA1- TXB0+ TXB0- <17> <17> TXB2+ TXB2- TXB2+ TXB2- TXBCLK+ TXBCLK- <17> <17> TXA0+ TXA0- TXA0+ TXA0- DISPOFF# <17> <17> TXACLK+ TXACLK- <17> <17> TXB1+ TXB1- 1000P_0402_50V8J KC FBM-L11-201209-221LMAT_0805 C618 TXB0+ TXB0- <17> <17> TXBCLK+ TXBCLK- <17> <17>10U_0805_10V3M R174 4.7K_0402_5% 0.01U_0402_50V7K <46> BKOFF# <17> M10_BKOFF# D16 RB751V_SOD323 D41 M10@RB751V_SOD323 DISPOFF# D B+ Q8 INVPWR_B+ ENABLT# L2 G <46> <46> +3VS D M9@2N7002 1N_SOT23 KC FBM-L11-201209-221LMAT_0805 S D D C _ C L K <10,17> D D C _ D A T <10,17> TXB1+ TXB1- LCDVDD C620 <10,17> ENABLT# INVT_PWM DAC_BRIG TXACLK+ TXACLK- C619 +3VS R1013 +3VS +12VALW M9@10K_5% INVPWR_B+ R175 +3VS R1007 C86 4.7U_0805_10V4Z R1008 M9-M10@JST BM40B-SRDS LCDVDD 2.2K_0402_5% 100K_0402_5% D 2.2K_0402_5% +12VALW TFT LCD CONN. +5VS +12VALW LCDVDD_A AT LEAST 60 MIL C993 TXA2+_NB TXA2-_NB TXA2+_NB TXA2-_NB <11> <11> TXA1+_NB TXA1-_NB TXA1+_NB TXA1-_NB TXB0+_NB TXB0-_NB TXB0+_NB <11> TXB0-_NB <11> <11> <11> TXB2+_NB TXB2-_NB TXB2+_NB TXB2-_NB TXBCLK+_NB TXBCLK-_NB TXBCLK+_NB <11> TXBCLK-_NB <11> TXA0+_NB TXA0-_NB TXA0+_NB TXA0-_NB DISPOFF# INVT_PWM DAC_BRIG <11> <11> C <11> TXACLK+_NB <11> TXACLK-_NB <11> <11> TXB1+_NB TXB1-_NB 1K_0402_1% C87 JP28 <11> <11> C88 27P_0402_50V8J TXACLK+_NB TXACLK-_NB R182 100K_0402_5% R181 LCDVDD D C994 0.1U_0402_10V6K D 0.1U_0402_10V6K 27P_0402_50V8J C90 Q10 2N7002_SOT23 S G G Q11 2N7002_SOT23 C91 150K_0402_5% 0.1U_0402_10V6K S 4.7U_0805_10V4Z PIR BOM & LAYOUT 92.09.01 <10,17,46> ENAVDD 22K ENAVDD Q12 22K DTC124EK_SOT23 DDC_CLK DDC_DAT TXB1+_NB TXB1-_NB G S Q9 C89 SI2302DS 1N_SOT23 0.047U_0402_16V4Z R180 DDC_CLK DDC_DAT R1115 SI2301DS: P CHANNEL VGS: -4.5V, RDS: 130 mOHM VGS: -2.5V, RDS: 190mOHM Id(MAX): 2.3A VGS(MAX): +-8V SI2302DS: N CHANNEL VGS: 4.5V, RDS: 85 mOHM VGS: 2.5V, RDS: 115mOHM Id(MAX): 2.8A VGS(MAX): +-8V C 2.2K_0402_5% INVPWR_B+ +3VS TFT LCD CONN. NAGP@JST BM40B-SRDS D21 DAN217_SOT23 D22 DAN217_SOT23 D23 DAN217_SOT23 +3VS +5VS CRT_VCC D17 CRT CONNECTOR R_CRT_VCC F1 RB411D_SOT23 FUSE_1A C97 0.1U_0402_10V6K 3VDDCDA <11,17> 3 V D D C D A 3VDDCCL <11,17> 3 V D D C C L B B JP6 M_SEN# CRT_R <46> M_SEN# <11,17> C R T _ R <11,17> CRT_G <11,17> CRT_B CRT_G 10P_0402_50V8K CRT_B L3 FCM2012C-800_0805 CRTL_R L5 FCM2012C-800_0805 CRTL_G L6 FCM2012C-800_0805 CRTL_B CRT_VCC R1150 R185 C100 R186 C101 C102 C103 C104 10P_0402_50V8K 22P_0402_25V8K C105 CRT_VCC 75_0402_5% R187 R1117 R1118 1K_0402 10P_0402_50V8K 7 5 _ 0 4 0 2 _ 5 % 22P_0402_25V8K Q13 D CRT_HSYNCRFL FBM-L10-160808-300LM-T 74AHCT1G125GW 220P_0402_25V8K L10 C107 CRT_VSYNCRFL C117 Q14 3VDDCCL 2N7002 1N_SOT23 D FBM-L10-160808-300LM-T R115420_0402_5% C108 C109 G +5VS SUYIN_7849S-15G2T-HC 3VDDCDA 2N7002 1N_SOT23 G U57 S L9 CRT_HSYNC <11,17> CRT_HSYNC 4.7K_0402_5% 4.7K_0402_5% 22P_0402_25V8K S R115320_0402_5% 75_0402_5% 10P_0402_50V8K R191 R192 C116 4.7K_0402_5% A CRT_VSYNC <11,17> CRT_VSYNC 74AHCT1G125GW U58 D42 D43 DAN217_SOT23 DAN217_SOT23 4.7K_0402_5% 10P_0402_50V8K 220P_0402_25V8K 220P_0402_25V8K A +3VS Compal Electronics, Inc. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 LCD,CRT,TV-OUT & Inverter BD CONN. Size Custom Date: Document Number Rev 1.0 LA-1811 Wednesday, September 24, 2003 1 Sheet 25 of 66 5 4 3 2 1 +3VS PCI_IRDY# PCI_TRDY# PCI_DEVSEL# PCI_STOP# Trace length of PCI_CLK_R + PCI_CLK_FB should be less than 200 mils. A_CBE#[0..3] <10,13> A_CBE#[0..3] RP14 Layout note: A_AD[0..31] <10,13> A_AD[0..31] U3A <24> CLK_ALINK_SB +VCC_CORE NBRST# R131 330_0402_5% CLK_ALINK_SB Q5 <5> MMBT3904_SOT23 H_CPUFERR# H_FERR# R134 +VCC_CORE Q98 <5,8> @10_0402_5% R1000 C77 470_0402_5% @15P_0402_50V8J @MMBT3904_SOT23 CPURSTIN# H_RESET# +3VS +3VS R946 8.2K_0402_5% A_SERR# R40 1K_0402_5% SBCLK_STP# <5,11,56> CPUCLK_STP# C +3VS <10> A_STROBE# <10> A_DEVSEL# <10> A_ACAT# <10> A_END# <10,13> A_PAR <10> A_OFF# R921 4.7K_0402_5% CLK_14M_APIC <10> <10> A_SBREQ# A_SBGNT# PCI CLKS A_AD0 A_AD1 A_AD2 A_AD3 A_AD4 A_AD5 A_AD6 A_AD7 A_AD8 A_AD9 A_AD10 A_AD11 A_AD12 A_AD13 A_AD14 A_AD15 A_AD16 A_AD17 A_AD18 A_AD19 A_AD20 A_AD21 A_AD22 A_AD23 A_AD24 A_AD25 A_AD26 A_AD27 A_AD28 A_AD29 A_AD30 A_AD31 A_CBE#0 A_CBE#1 A_CBE#2 A_CBE#3 A_STROBE# A_DEVSEL# A_ACAT# A_END# A_PAR A_OFF# A_SERR# A_SBREQ# A_SBGNT# PULL DOWN FOR S3 PCI INTERFACE 8.2K_0402_5% A-LINK INTERFACE R125 R132 470_0402_5% SB200 SB Part 1 of 3 +3VS D CLK_ALINK_SB SBCLK_STP# PCICLK_STP# R1143 @10_0402_5% PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# <10,17,31,35,36> PCI_PIRQA# <31> PCI_PIRQB# <36,43> PCI_PIRQC# <34,36> PCI_PIRQD# +3VS C973 @15P_0402_50V8J +VCC_CORE XTAL RTCX1 R169 RTCX2 330_0402_5% CPURSTIN# R1001 47K_0402_5% <5> <56> DPRSLPVR R1002 <24> CLK_14M_APIC H_A20M# C956 180P_0603_50V8J H_INIT# C617 180P_0603_50V8J H_INTR C78 180P_0603_50V8J C79 180P_0603_50V8J H_NMI PCIRST# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3 PCI_FRAME# PCI_DEVSEL# PCI_IRDY# PCI_TRDY# PCI_PAR PCI_STOP# PCI_PERR# PCI_SERR# PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3 PCI_REQ#4 PCI_GNT#0 PCI_GNT#1 PCI_GNT#2 PCI_GNT#3 PCI_GNT#4 PCI_CLKRUN# 39_0402_5% 39_0402_5% 39_0402_5% 39_0402_5% 39_0402_5% 39_0402_5% 39_0402_5% 39_0402_5% C76 H_A20M# H_CPUFERR# GPIO0 SIRQ 10K_0402_5% SB_APIC_D0 10K_0402_5% SB_APIC_D1 @300_0402_1% 1K_0402_1% RP15 PCI_PAR PCI_PERR# PCI_SERR# PCI_FRAME# @22P_0402_50V8J PCI_AD[0..31] D 8.2K _8P4R_0804_5% PCI_AD[0..31] RP16 <29,31,34,35,36,43> PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PIR BOM 92.09.01 8.2K _8P4R_0804_5% RP17 PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3 8.2K _8P4R_0804_5% RP18 PCI_GNT#0 PCI_GNT#1 PCI_GNT#2 PCI_GNT#3 8.2K _8P4R_0804_5% R137 PCI_REQ#4 8.2K_0402_5% R138 C PCI_GNT#4 PCI_CBE#[0..3] PCI_CBE#[0..3] LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 PCI_FRAME# <31,34,35,36,43> PCI_DEVSEL# <31,34,35,36,43> PCI_IRDY# <31,34,35,36,43> PCI_TRDY# <31,34,35,36,43> PCI_PAR <31,34,35,36,43> PCI_STOP# <31,34,35,36,43> PCI_PERR# <31,34,35,36,43> PCI_SERR# <31,34,35,36,43> PCI_REQ#0 <35> PCI_REQ#1 <34> PCI_REQ#2 <31> PCI_REQ#3 <36,43> PCI_REQ#4 <36,43> PCI_GNT#0 <35> PCI_GNT#1 <34> PCI_GNT#2 <31> PCI_GNT#3 <36,43> PCI_GNT#4 <36,43> PCI_CLKRUN# <31,34,35,36,43> LPC_AD0 <39,46> LPC_AD1 <39,46> LPC_AD2 <39,46> LPC_AD3 <39,46> LPC_FRAME# <39,46> 8.2K_0402_5% RP21 <31,34,35,36,43> 100K_1206_8P4R_5% RP138 SIRQ LPC_FRAME# LPC_DRQ#0 LPC_DRQ#1 10K_0804_8P4R_5% R145 PCI_CLKRUN# R 1 4 6 4.7K_0402_5% @4.7K_0402_5% R 1 1 5 5 10K_0402_5% GPIO0 H _ P R O C H O T # <5,51> D GPIO1 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_DRQ#0 LPC_DRQ#1 8.2K _8P4R_0804_5% CLK_PCI_1394 <35> CLK_PCI_LAN <34> CLK_PCI_PCM <31> CLK_PCI_MINI <43> CLK_PCI_EC <46> CLK_PCI_SIO <39> CLK_PCI_USB20 <36> S H_STPCLK# 47K_0402_5% R1064 R1065 R1066 R1067 R122 R123 R124 R126 R127 R128 R1021 R130 G <5> H _ P W R G O O D <5> H_INTR <5> H_NMI <5> H_INIT# <5> H_SMI# <5> H_CPUSLP# <5> H_IGNNE# <5> H_A20M# LPC 200_0402_5% 200_0402_5% 200_0402_5% 200_0402_5% 200_0402_5% 200_0402_5% 200_0402_5% 200_0402_5% CPU R149 R150 R151 R152 R153 R154 R156 R158 +3V Q118 @2N7002_SOT23 R1151 R 1 1 5 7 10K_0402_5% OVCUR#4 B 10K_0402_5% OVCUR#5 R1059 10K_0402_5% L P C _ D R Q # 1 <39> SIRQ R 1 1 5 6 10K_0402_5% <31,39,46> GPIO2 OVCUR#5 OVCUR#4 RTC B H_INIT# H_A20M# H_CPUSLP# H_INTR H_NMI H_SMI# H_STPCLK# H_IGNNE# PCI_1394 PCI_LAN PCI_PCM PCI_MINI PCI_EC PCI_SIO PCI_USB20 PCI_CLK_R PCI_CLK_FB GPIO2 +RTCVCC +RTCVCC +3VALW R168 South bridge SB200 1K_0402_5% C872 PLACE CLOSE TO CPU SOCKET C80 0.1U_0402_10V6K U45B JOPEN1 No short U45D + BATT1.1 W=20mils BATT1 - W=20mils RB751V_SOD323 D93 1U_0603_10V6K RTCBATT PCIRST# PCI_RST# PCI_RST# <11,30,31,34,35,36,43,46> Y1 RTCX2 W=15mils CHGRTC RTCX1 R966 SN74LVC14APWLE_TSSOP14 10K_0402_5% A 32.768KHZ_12.5P_MC-306 +3VALW R171 C81 20M_0603_5% C82 12P_0402_50V8K 12P_0402_50V8K A SN74LVC14APWLE_TSSOP14 R172 20M_0603_5% U45E NBRST# SN74LVC14APWLE_TSSOP14 +3VALW U45F NB_RST# NB_RST# <8,17,39> Compal Electronics, Inc. Title SN74LVC14APWLE_TSSOP14 SB200M(1/4)- PCI/CPU/LPC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 26 of 66 5 L 4 3 2 1 Note: Place close to U3 (ATI SB) For ATI USB2.0 only . U3B CLK_SB_48M <24> CLK_SB_48M R63 12.4K_0603_1% R64 OVCUR#0 C73 <44> USB20P5+ @15P_0402_50V8J <44> USB20P5- <41> USB20P4+ <41> USB20P4- R71 <44> USB20P3+ @10_0402_5% <44> USB20P3- C74 <44> USB20P2+ @15P_0402_50V8J <44> USB20P2- <44> USB20P1+ CLK_SB_14M <44> USB20P1- R92 <44> USB20P0+ @10_0402_5% <44> USB20P0- USB20P5+ USB20P5- ACPI / WAKE UP EVENTS AC97_BITCLK C SB_PM_BATLOW# SB_EC_SWI# SLP_S3# SLP_S5# PWRBTN_OUT# SB_PWRGD PCI_ACT_REQ# SUS_STAT# SB_TEST1 SB_TEST0 @10_0402_5% <44> USB20P4+ USB20P4USB20P3+ USB20P3- SUS_STAT# <8> USB20P0+ USB20P0- ETHERNET MII USB20P3USB20P3+ USB20P2USB20P2+ 15K_1206_8P4R_5% MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0 <29> MII_TXEN 10K_0402_5% R950 10K_0402_5% SB_EEDO SB_EECLK SB_EEDO SB_EECLK CLK_SB_14M <24> CLK_SB_14M R948 +3V 10K_0402_5% EC_FLASH# OVCUR#1 32KHZ_S5_OUT OVCUR#1 SB_SPKR <47> EC_FLASH# <29> 32KHZ_S5_OUT <44> O V C U R # 1 SB_SPKR 10K_0402_5% <37> R951 AGP_STP# D 1 1 <10,17> AGP_STP# <5> RB751V_SOD323 AGP_STP#_R @10K_0402_5% R952 AGP_BUSY#_R GHI VGATE IDERSTHD# IDERSTCD# D77 RB751V_SOD323 CPU_GHI# EC_THERM# <46> PM_BATLOW# PM_BATLOW# <46> SB_EC_SWI# D4 RB751V_SOD323 EC_SWI# SB_GA20 D5 RB751V_SOD323 GA20 SB_KBRST# D6 RB751V_SOD323 KBRST# SB_AC_IN D7 RB751V_SOD323 SB_EC_SMI# D8 RB751V_SOD323 SB_SCI# D9 RB751V_SOD323 SCI# RB751V_SOD323 LID_OUT# 0_0603_5% USB_SMI# R1003 R1062 <46> GA20 <46> KBRST# <46> ACIN ACIN <46,50,53> EC_SMI# EC_SMI# <46> SCI# <46> D LID_OUT# <46> USB_SMI# <36> +2.5V R68 10K_0402_5% SUS_STAT# R 6 9 +3V IDEIORDYB <30> IDEIRQB <30> IDESAB0 <30> IDESAB1 <30> IDESAB2 <30> IDEDACK#B <30> IDEREQB <30> IDEIOR#B <30> IDEIOW#B <30> IDECS#B1 <30> IDECS#B3 <30> IDEDB[0..15] C 4.7K_0402_5% <30> GHI AGP_STP#_R AGP_BUSY#_R SB_GA20 RP107 SB_KBRST# SB_EC_SWI# SB_EC_SMI# SB_SCI# RP108 10K_0804_8P4R_5% 10K_0804_8P4R_5% RP109 10K_0804_8P4R_5% LPC_SMI# SB_AC_IN PCI_ACT_REQ# RP110 10K_0804_8P4R_5% +3VALW PWRBTN_OUT# SLP_S3# SLP_S5# RP11 <30> 10K_0804_8P4R_5% B +3VS SMB_CK_CLK2 SMB_CK_DAT2 SMB_CK_CLK2_SB SMB_CK_DAT2_SB RP12 2.2K_0804_8P4R_5% +3V AC97_RST# R111 8.2K_0402_5% +3VS AC97_SDOUT_R R 1 1 7 33_0402_5% AC97_SYNC_R 33_0402_5% SPDIF_OUT D10 EC_SWI# SB_LID_OUT# SB_EC_THERM# SB_PM_BATLOW# LPC_PME# IDEDB0 IDEDB1 IDEDB2 IDEDB3 IDEDB4 IDEDB5 IDEDB6 IDEDB7 IDEDB8 IDEDB9 IDEDB10 IDEDB11 IDEDB12 IDEDB13 IDEDB14 IDEDB15 EC_RSMRST# <46> EC_RSMRST# 100K_0402_5% R112 AC97 <29> <29> B EEPROM R947 IDEDA[0..15] IDEIORDYB IDEIRQB IDESAB0 IDESAB1 IDESAB2 IDEDACK#B IDEREQB IDEIOR#B IDEIOW#B IDECS#B1 IDECS#B3 MII_TXEN CLK / RST 15K_1206_8P4R_5% <29> <29> <29> <29> MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0 GPIO SECONDARY ATA 66/100 USB20P1+ USB20P1USB20P0+ USB20P0- GPIO_XTRA RP113 IDEDA0 IDEDA1 IDEDA2 IDEDA3 IDEDA4 IDEDA5 IDEDA6 IDEDA7 IDEDA8 IDEDA9 IDEDA10 IDEDA11 IDEDA12 IDEDA13 IDEDA14 IDEDA15 PRIMARY ATA 66/100 15K_1206_8P4R_5% RP112 EC_THERM# RB751V_SOD323 SMB_CK_CLK2 <14,15,24> SMB_CK_DAT2 <14,15,24> PWR_STRP <29> IDEIORDYA <30> IDEIRQA <30> IDESAA0 <30> IDESAA1 <30> IDESAA2 <30> IDEDACK#A <30> IDEREQA <30> IDEIOR#A <30> IDEIOW#A <30> IDECS#A1 <30> IDECS#A3 <30> @15P_0402_50V8J USB20P4+ USB20P4USB20P5USB20P5+ RB751V_SOD323 D3 LPC_SMI# IDEIORDYA IDEIRQA IDESAA0 IDESAA1 IDESAA2 IDEDACK#A IDEREQA IDEIOR#A IDEIOW#A IDECS#A1 IDECS#A3 C75 RP111 D2 SB_PM_BATLOW# SB_LID_OUT# SMB_CK_CLK2 SMB_CK_DAT2 SMB_CK_CLK2_SB SMB_CK_DAT2_SB PWR_STRP USB20P2- USB20P1- SLP_S3# <46> SLP_S5# <46> PWRBTN_OUT# <46> SB_PWRGD <48> SB_GA20 SB_KBRST# SB_AC_IN LPC_PME# LPC_SMI# SB_EC_SMI# SB_SCI# SB_LID_OUT# USB20P2+ USB20P1+ SB_EC_THERM# SB_EC_THERM# Part 2 of 3 USB INTERFACE D SB200 SB CLK_SB_48M USB_RCOMP R119 AC97_BITCLK AC97_SDOUT AC97_SDIN0 AC97_SDIN1 AC97_SDIN2 AC97_SYNC AC97_RST# AC97_BITCLK <37,44> AC97_SDOUT <29,37,44> AC97_SDIN0 <37> AC97_SDIN1 <44> AGP_STP# AGP_BUSY# SB_TEST0 SB_TEST1 RP140 8.2K _8P4R_0804_5% AC97_SYNC <29,37,44> AC97_RST# <37,44> SPDIF_OUT <29,37> 33_0402_5% AC97_SDIN0 AC97_SDIN1 AC97_SDIN2 South bridge SB200 IDERST_HD# <30> IDERST_HD# D13 R121 IDERST_CD# <30> IDERST_CD# IDERSTHD# RB751V_SOD323 RP13 VTT_PWRGD <24,46,48> 10K_0402_5% D14 AGP_BUSY#_R Q89 +5VS AC97_BITCLK IDERSTCD# RB751V_SOD323 AGP_BUSY# 2N7002 1N_SOT23 S +3VS 10K_0402_5% R934 AGP_BUSY# 8.2K_0402_5% Compal Electronics, Inc. <10,17> Title SB200M(2/4) - IDE/USB/MII THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL 1K_0603_5% DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 8.2K _8P4R_0804_5% R1176 PIR BOM 92.09.02 G A R120 D +3VS 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 Sheet 1 27 of 66 A 5 4 3 2 +3VS 1 +3VS 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K U3C 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K SB200 SB Part 3 of 3 C23 D C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 22U_1206_16V4Z_V1 22U_1206_16V4Z_V1 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K0.1U_0402_10V6K 0.1U_0402_10V6K PIR BOM 92.09.01 +3VS ATI request +2.5VS 0.1U_0402_16V7Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K C873 C40 D 0.1U_0402_10V6K C41 C42 C43 C44 C45 C46 C47 C874 C875 C876 C877 C48 0.1U_0402_16V7Z 22U_1206_16V4Z_V1 0.1U_0402_16V7Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_16V7Z 0.1U_0402_16V7Z POWER +2.5VS +2.5VS ATI request +2.5V 0.1U_0402_16V7Z 0.1U_0402_10V6K 0.1U_0402_10V6K PIR BOM 92.09.01 C49 C50 C51 C52 C53 22U_1206_16V4Z_V1 C C878 0.1U_0402_10V6K C879 C880 C881 0.1U_0402_16V7Z 0.1U_0402_16V7Z C 0.1U_0402_10V6K 0.1U_0402_16V7Z ATI request +3V +3V +2.5V 0.1U_0402_10V6K0.1U_0402_10V6K C54 C55 C56 C57 C58 22U_1206_16V4Z_V1 C882 0.1U_0402_10V6K ATI request CLOSE TO L6,H6,J6 +2.5V C883 @0.1U_0402_16V7K @0.1U_0402_16V7K C885 C886 C966 0.1U_0402_10V6K 0.1U_0402_16V7K 0.1U_0402_16V7K +3V_AVDDC 0.1U_0402_16V7K +3V_AVDDC ATI request PIR BOM 92.09.01 R60 +3V PIR BOM 92.09.01 +3V_AVDDC 0.01U_0402_16V7Z +3V 0_0805_5% C59 C60 1U_0603_10V6K 0.1U_0402_10V6K C980 C981 C887 PIR BOM 92.09.01 B @10U_0805_10V6K +5VS PIR BOM 92.09.01 +3V_AVDDUSB B 1000P_0402_16V7K R1114 +3VS ATI request +3V_AVDDUSB D90 0_0402_5% +2.5VS +3V_AVDDUSB +3V R61 0.1U_0402_10V6K0.1U_0402_10V6K 0.1U_0402_10V6K 0_0805_5% C62 C63 C64 C65 C66 C67 RB751V_SOD323 C 8 4 3 C68 22U_1206_16V4Z_V1 C888 0.1U_0402_10V6K 1U_0603_10V6K + +2.5V_AVDDCK +2.5VALW +3VALW @47U_B_6.3VM 0.1U_0402_10V6K 0.1U_0402_10V6K South bridge SB200 C69 ATI request +2.5V_AVDDCK PIR BOM 92.09.01 C70 0.1U_0402_10V6K 0.1U_0402_10V6K +2.5V_AVDDCK 0.01U_0402_16V7Z +2.5VS R62 0_0805_5% C889 C71 C72 C982 1U_0603_10V6K 0.1U_0402_10V6K C983 @22U_1206_16V4Z_V1 A A 1000P_0402_16V7K Compal Electronics, Inc. Title SB200M(3/4) - PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 28 of 66 5 4 3 2 1 D D +3VALW C +3V +3VS +3V +3VS +3VS +3V +3V +3V +3V +3VALW +3V C R34 R35 R36 R37 R38 R39 R41 R42 R43 R44 R45 R46 10K_0402_5% @10K_0402_5% @10K_0402_5% @10K_0402_5% @10K_0402_5% @10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% R47 R48 R49 R50 R51 R52 R54 R55 R56 R57 R58 R59 @10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% @10K_0402_5% @10K_0402_5% @10K_0402_5% @10K_0402_5% @10K_0402_5% @10K_0402_5% <27> PWR_STRP <27> SB_EEDO <27> SB_EECLK <27,37,44> AC97_SYNC <27,37,44> AC97_SDOUT <27,37> SPDIF_OUT <27> MII_TXEN <27> MII_TXD3 <27> MII_TXD2 <27> MII_TXD1 <27> MII_TXD0 <27> 32KHZ_S5_OUT B REQUIRED SYSTEM STRAPS PWR_STRP MANUAL PWR ON STRAP HIGH IGN DEBUG EEDO EECK AC_SYNC USE DEBUG STRAPS ROM ON PCI BUS IGNORE DEBUG STRAPS DEFAULT SPEEDSTEP CPU_STP# AC_SDOUT SPDIF_OUT INIT ACTIVE HIGH 33MHz NB BUS SIO 24MHz ENABLE SPEED STEP ROM ON LPC BUS INIT ACTIVE LOW (PIII) HI SPEED A-LINK SIO 48MHz DISABLE SPEED STEP DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT FREQLTCH TX_EN ETHERNET TXD[3:0] DEFAULT B 32KHZ_S5 32KHZ OUTPUT FROM SB200 (INT RTC) DISABLE CPU FREQ SETTING PROCESSOR FREQ MULTIPLIER DEFAULT AUTO PWR ON STRAP LOW ENABLE CPU FREQSETTING 32KHZ INPUT TO SB200 (EXT RTC) +3VS R953 @10K_0402_5% A A <26,31,34,35,36,43> PCI_AD26 R967 10K_0402_5% Compal Electronics, Inc. Title SB200M(4/4) - STRAPS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 29 of 66 5 4 3 2 1 +5VS U1A HDD/CD-ROM Module +5VS HDD_LED# ACT_LED# <45> CDLED# 74HCT08PW_TSSOP14 C1 C2 1000P_0402_50V7K 10U_0805_16V4Z 10U_0805_16V4Z 1U_0603_10V6K 0.1U_0402_10V6K C3 C4 C5 U1B <27> IDERST_CD# SD_IDERST# <11,26,31,34,35,36,43,46> PCI_RST# 74HCT08PW_TSSOP14 D D Placea caps. near HDD CONN. U1C U1D +5VS +5VS HD_IDERST# <27> IDERST_HD# 74HCT08PW_TSSOP14 C6 C7 74HCT08PW_TSSOP14 C8 1U_0603_25V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z <27> IDEDA[0..15] IDEDA14 IDEDA1 IDEDA15 IDEDA0 RP1 IDEDA5 IDEDA10 IDEDA11 IDEDA4 RP2 IDEDA7 IDEDA8 IDEDA6 IDEDA9 RP3 IDEDA3 IDEDA12 IDEDA13 IDEDA2 RP4 C <27> IDEREQA <27> IDEIOW#A <27> IDEIOR#A <27> IDECS#A1 <27> IDEDACK#A <27> IDEIRQA IDEDA[0..15] PD_D14 PD_D1 PD_D15 PD_D0 33_0804_8P4R_5% PD_D5 PD_D10 PD_D11 PD_D4 33_0804_8P4R_5% PD_D7 PD_D8 PD_D6 PD_D9 33_0804_8P4R_5% PD_D3 PD_D12 PD_D13 PD_D2 33_0804_8P4R_5% R11 10K_0402_5% R3 JP1 HD_IDERST# R 4 33_0603_1% R18 33_0603_1% R19 R15 +5VS PD_D8 PD_D9 PD_D10 PD_D11 PD_D12 PD_D13 PD_D14 PD_D15 PD_DREQ# PD_IOW# PD_IOR# PD_IORDY PD_DACK# PD_IRQA PD_A1 PD_A0 PD_CS#1 HDD_LED# PD_DREQ# PD_IOW# PD_IOR# 33_0804_8P4R_5% PD_CS#1 PD_DACK# RP124 33_0402_5% PD_D7 PD_D6 PD_D5 PD_D4 PD_D3 PD_D2 PD_D1 PD_D0 10K_0402_5% C PCSEL R9 B IDESAA0 IDESAA1 IDESAA2 IDECS#A3 <27> <27> <27> <27> IDESAB0 IDESAB1 IDESAB2 IDECS#B3 IDESAA0 IDESAA1 IDESAA2 IDECS#A3 +5VS PD_IRQA SUYIN_200006FA044S503ZU R968 8.2K_0402_5% +3VS C11 RP5 PD_A0 PD_A1 PD_A2 PD_CS#3 33_0804_8P4R_5% RP6 SD_SBA0 SD_SBA1 SD_SBA2 SD_SCS3# 33_8P4R_0804_5% IDESAB0 IDESAB1 470_0402_5% PD_A2 PD_CS#3 +5VS 5.6K_0402_5% <27> <27> <27> <27> R8 4.7K_0402_5% R969 <27> IDEIORDYA <37> CDROM_L +3VS IDEDB5 IDEDB9 IDEDB4 IDEDB11 RP7 IDEDB0 IDEDB15 IDEDB1 IDEDB14 RP8 IDEDB6 IDEDB10 IDEDB8 IDEDB7 RP9 IDEDB3 IDEDB12 IDEDB2 IDEDB13 RP10 <27> IDEREQB IDEDB[0..15] R26 R24 <27> IDEIORDYB <27> IDEIRQB RP125 R31 +5VS SD_SIORDY 33_0402_5% CDROM_L CDROM_R SD_IDERST# SD_D7 SD_D6 SD_D5 SD_D4 SD_D3 SD_D2 SD_D1 SD_D0 SD_D8 SD_D9 SD_D10 SD_D11 SD_D12 SD_D13 SD_D14 SD_D15 SD_DREQ SD_SIOR# R1110 SD_SBA2 SD_SCS3# W=80mils +5VS R 6 1 3 @100K_0402_5% +5VS C14 C15 SD_DREQ 33_0603_1% R32 5.6K_0402_5% C16 W=100mils C17 C18 C19 1000P_0402_50V7K 10U_0805_16V4Z 1U_0603_10V6K 0.1U_0402_10V6K C20 C21 1000P_0402_50V7K 10U_0805_16V4Z Placea caps. near CDROM CONN. SD_IRQ15 +5VS +5VS +5VS C 6 1 0 0.1U_0402_10V6K CD-ROM CONN. W=100mils SD_SIOW# SD_SIOR# SD_SCS1# SD_DACK# @10K_0402_5% +5VS +5VS 10K_0402_5% +5VS 33_0804_8P4R_5% B SD_DACK# SD_CSEL 33_0603_1% C D R O M _ R <37> +5VS R614 470_0402_5% A <27> IDEIOW#B <27> IDEIOR#B <27> IDECS#B1 <27> IDEDACK#B R970 C D _ A G N D <37> JP2 SD_SIOW# SD_SIORDY SD_IRQ15 SD_SBA1 SD_SBA0 SD_SCS1# CDLED# 4.7K_0402_5% SD_D5 SD_D9 SD_D4 SD_D11 33_0804_8P4R_5% SD_D0 SD_D15 SD_D1 SD_D14 33_0804_8P4R_5% SD_D6 SD_D10 SD_D8 SD_D7 33_0804_8P4R_5% SD_D3 SD_D12 SD_D2 SD_D13 33_0804_8P4R_5% @47P_0402_25V8K C12 CD_AGND R611 10K_0402_5% PD_IORDY 33_0402_5% @10U_0805_6.3V6M R25 <27> IDEDB[0..15] C9 1U_0603_25V4Z Placea caps. near CDROM CONN. +5VCD trace to CONN W=100mils +5VCD trace to CONN W=100mils Compal Electronics, Inc. R33 8.2K_0402_5% SD_DREQ C22 33P_0402_25V8K HDD & CDROM Connector THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 A 1U_0603_10V6K 0.1U_0402_10V6K 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 30 of 66 A B C D R833 0_0402_5% <26,34,35,36,43> PCI_CLKRUN# E CLK_SD_48M <24> +3V <26,39,46> SIRQ <42> CARD_LED# <10,17,26,35,36> PCI_PIRQA# <26> PCI_PIRQB# <46> PCM_SUSP# <32> SLDATA <32> RTCCLK <32> SLATCH <37> PCM_SPK# +3V +3VS + 3 V R1018 @10K_0402_5% R633 1620@0_0402_5% R940 @0_0402_5% R939 0_0402_5% C633 0.1U_0402_10V6K JP24A1 0.1U_0402_10V6K @0.1U_0402_10V6K +S2_VCC C635 0.1U_0402_10V6K C634 C909 +S1_VCC CARDBUS HOUSING 1 +3V U37 S2_D0 S2_D1 S2_D2 S2_D3 S2_D4 S2_D5 S2_D6 S2_D7 S2_D8 S2_D9 S2_D10 S2_D11 S2_D12 S2_D13 S2_D14 S2_D15 FUNCTION S1_D0 S1_D1 S1_D2 S1_D3 S1_D4 S1_D5 S1_D6 S1_D7 S1_D8 S1_D9 S1_D10 S1_D11 S1_D12 S1_D13 S1_D14 S1_D15 POWER 1 0.1U_0402_10V6K C845 C846 0.1U_0402_10V6K 0.1U_0402_10V6K C847 C848 0.1U_0402_10V6K 0.1U_0402_10V6K C849 0.1U_0402_10V6K CARDBUS CONTROLLER PCI1520 PBGA 209 <32,33> S2_RST <32,33> S2_WE# <32> S2_IOWR# <32> S2_IORD# <32,33> S2_REG# <32,33> S2_OE# <32,33> S2_INPACK# <32,33> S2_RDY# <32,33> S2_BVD2 <32,33> S2_WAIT# <32,33> S2_BVD1 <32> S2_WP C899 C900 C901 C902 C903 0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K 2 S1_RST <32> S1_WE# <32> S1_IOWR# <32> S1_IORD# <32> S1_REG# <32> S1_OE# <32> S1_INPACK# <32> S1_RDY# <32> S1_BVD2 <32> S1_WAIT# <32> S1_BVD1 <32> S1_WP <32> 3 <32,33> <32,33> 0.1U_0402_10V6K 0.01U_0402_16V7K 0.01U_0402_16V7K C898 S1_A0 S1_A1 S1_A2 S1_A3 S1_A4 S1_A5 S1_A6 S1_A7 S1_A8 S1_A9 S1_A10 S1_A11 S1_A12 S1_A13 S1_A14 S1_A15 S1_A16 S1_A17 S1_A18 S1_A19 S1_A20 S1_A21 S1_A22 S1_A23 S1_A24 S1_A25 SLOT A SLOT B 2 C851 +3V 0.01U_0402_16V7K S2_A0 S2_A1 S2_A2 S2_A3 S2_A4 S2_A5 S2_A6 S2_A7 S2_A8 S2_A9 S2_A10 S2_A11 S2_A12 S2_A13 S2_A14 S2_A15 S2_A16 S2_A17 S2_A18 S2_A19 S2_A20 S2_A21 S2_A22 S2_A23 S2_A24 S2_A25 C850 S2_VS1 S2_VS2 <32,33> S2_CE1# <32> S2_CE2# S1_VS1 S1_VS2 <32,33> S2_CD1# <32,33> S2_CD2# S1_CE2# <32> S1_CE1# <32> PCI INTERFACE 3 <32> <32> S1_CD1# <32> S1_CD2# <32> GROUND PCI_AD20_R PCI_CBE#3 PCI_CBE#2 PCI_CBE#1 PCI_CBE#0 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI1520GHK_PBGA209 PCI_PAR <26,34,35,36,43> PCI_FRAME# <26,34,35,36,43> PCI_TRDY# <26,34,35,36,43> PCI_IRDY# <26,34,35,36,43> PCI_STOP# <26,34,35,36,43> PCI_DEVSEL# <26,34,35,36,43> PCI_AD20 R634 0_0402_5% 4 <26,34,35,36,43> PCI_CBE#[0..3] <32,33> S2_D[0..15] <32,33> S2_A[0..25] <32> S1_D[0..15] <32> S1_A[0..25] <26,29,34,35,36,43> PCI_AD[0..31] R1098 100_0402_5% PCI_CBE#[0..3] PCI_PERR# <26,34,35,36,43> PCI_SERR# <26,34,35,36,43> PCI_REQ#2 <26> PCI_GNT#2 <26> CLK_PCI_PCM <26> PCI_RST# <11,26,30,34,35,36,43,46> G_RST# <32,36,46> PCM_PME# <34,36,43,46,47> S2_D[0..15] S2_A[0..25] S1_D[0..15] S1_A[0..25] CLK_PCI_PCM R1020 @10K_0402_5% 4 C910 @0.1U_0402_10V6K Compal Electronics, Inc. PCI_AD[0..31] CardBus Controller OZ6912/CB1410 & Socket THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 E Sheet 31 of 66 <31> <31> CARDBUS SOCKET S1_D[0..15] S1_A[0..25] <31,33> S2_D[0..15] <31,33> S2_A[0..25] PCMCIA POWER CTRL. S1_D[0..15] S1_A[0..25] S2_D[0..15] S2_A[0..25] 2 +12VALW C636 R1004 1000P_0402_50V8J @0_0603_5% PIR BOM & LAYOUT 92.09.01 <31> <31> <31> <31> S1_CE1# S1_OE# S1_WE# S1_RDY# +S1_VCC +S1_VPP S1_WP S1_A16 S1_A15 S1_A12 S1_A7 S1_A6 S1_A5 S1_A4 S1_A3 S1_A2 S1_A1 S1_A0 S1_D0 S1_D1 S1_D2 S1_WP S1_A22 S1_A23 S1_A24 S1_A25 S1_VS2 S1_RST S1_WAIT# S1_INPACK# S1_REG# S1_BVD2 S1_BVD1 S1_D8 S1_D9 S1_D10 S1_CD2# S1_CD1# <31> S1_CE2# S1_VS1 S1_IORD# S1_IOWR# <31> <31> <31> <31> U38 <31> <31> SLDATA RTCCLK <31> <31,36,46> 2 S1_CD1# S1_D11 S1_D12 S1_D13 S1_D14 S1_D15 S1_CE2# S1_VS1 S1_IORD# S1_IOWR# S1_A17 S1_A18 S1_A19 S1_A20 S1_A21 R1177 47K_0402_5% +5V @2.2U_0805_10V4Z C638 4.7U_0805_10V4Z C639 4.7U_0805_10V4Z C640 4.7U_0805_10V4Z C641 4.7U_0805_10V4Z C642 4.7U_0805_10V4Z C644 4.7U_0805_10V4Z R635 4.7K_0402_5% +S1_VPP +S2_VPP +5V +S1_VCC +S2_VCC +S1_VCC +S1_VPP C645 4.7U_0805_10V4Z S1_VS2 S1_RST S1_WAIT# S1_INPACK# S1_REG# S1_BVD2 S1_BVD1 <31> <31> <31> <31> <31> <31> <31> S1_CD2# <31> C649 1000P_0402_50V7K 1 1 2 2 C643 4.7U_0805_10V4Z TPS2224A +S1_VCC +S1_VPP 1 1 2 C637 +3V SLATCH G_RST# 1 <31> S1_D3 S1_D4 S1_D5 S1_D6 S1_D7 S1_CE1# S1_A10 S1_OE# S1_A11 S1_A9 S1_A8 S1_A13 S1_A14 S1_WE# S1_RDY# 1 JP29 2 C647 0.1U_0402_10V6K 1 2 1 C646 C648 2 4.7U_0805_10V4Z 4.7U_0805_10V4Z +S2_VCC +S2_VPP 1 C650 1 C651 FOX_WZ21131-G2-P4 C652 JP30 <31,33> S2_CE1# <31,33> S2_OE# <31,33> <31,33> <31> S2_WE# S2_RDY# +S2_VCC +S2_VPP S2_WP 2 0.1U_0402_10V6K 2 4.7U_0805_10V4Z 2 1520@1000P_0402_50V7K S2_D3 S2_D4 S2_D5 S2_D6 S2_D7 S2_CE1# S2_A10 S2_OE# S2_A11 S2_A9 S2_A8 S2_A13 S2_A14 S2_WE# S2_RDY# S2_CD1# S2_D11 S2_D12 S2_D13 S2_D14 S2_D15 S2_CE2# S2_VS1 S2_IORD# S2_IOWR# S2_A17 S2_A18 S2_A19 S2_A20 S2_A21 S2_A16 S2_A15 S2_A12 S2_A7 S2_A6 S2_A5 S2_A4 S2_A3 S2_A2 S2_A1 S2_A0 S2_D0 S2_D1 S2_D2 S2_WP S2_A22 S2_A23 S2_A24 S2_A25 S2_VS2 S2_RST S2_WAIT# S2_INPACK# S2_REG# S2_BVD2 S2_BVD1 S2_D8 S2_D9 S2_D10 S2_CD2# S2_CD1# 1 C653 4.7U_0805_10V4Z <31,33> S2_CE2# <31> S2_VS1 <31,33> S2_IORD# <31> S2_IOWR# <31> +S2_VCC +S2_VPP S2_VS2 <31,33> S2_RST <31,33> S2_WAIT# <31,33> S2_INPACK# <31,33> S2_REG# <31,33> S2_BVD2 <31,33> S2_BVD1 <31,33> S2_CD2# <31,33> 1 2 C654 1520@1000P_0402_50V7K Compal Electronics, Inc. Title 1520@FOX_WZ21131-G2-P4 CARD BUS SOCKET THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 Sheet 32 of 66 10 9 8 7 6 5 4 3 2 1 +3VS +S2_VCC H H MC_WP# R636 R637 @10K_0402_5% <31,32> S2_A22 <31,32> S2_A25 S2_A22 R639 1620@0_0402_5% R638 @10K_0402_5% 1620@43K_0402_5% Q53 1620@MMBT3904_SOT23 MC_CD# D44 1620@BAT54C_SOT23~D S2_A25 R640 DQRYDRV 1620@0_0402_5% SD_WP +S2_VCC +S2_VCC R641 1620@10K_0402_5% R646 1620@0.1U_0402_10V6K C655 G C656 G R647 1620@0.1U_0402_10V6K 1620@10K_0402_5% 1620@BAT54C_SOT23~D D45 SM_CD# <31,32> S2_WAIT# <31,32> S2_INPACK# R648 R649 SD_CD# 1620@43_0402_5% RP143 1620@47K_0804_8P4R_5% 1 6 2 0 @ 0 _ 0 4 0 2 _ 5 % SQRY3 1 6 2 0 @ 0 _ 0 4 0 2 _ 5 % SQRY4 JP31 SD_CD# F <31,32> S2_D10 <31,32> S2_D9 <31,32> S2_D8 <31,32> S2_BVD1 <31,32> S2_BVD2 <31,32> S2_REG# <31,32> S2_RST <31,32> S2_A18 SD_DATA1 SD_DATA0 SD_CLK/MS_CLK SD_CMD SD_CD/DATA3 SD_DATA2 SQRY10 SQRY9 SQRY8 SQRY7 1620@0_0804_8P4R_5% SQRY6 SQRY5 SQRY2 SQRY1 1620@0_0804_8P4R_5% RP128 RP129 1620@0_0402_5% SM_D4 SM_D3/MS_BS SM_D5 SM_D2/MS_SDIO SM_D6 SM_D1/MS_RFU5 SM_D7 SM_D0/MS_RFU7 SM_LVD SM_WP# SM_WE# SM_R/B# SM_ALE SM_RE# SM_CLE SM_CE# MC_WP# E <31,32> <31,32> <31,32> SD_DATA1 SD_DATA0 SD_CLK/MS_CLK S2_A14 S2_A19 S2_A16 RP141 F R658 R665 1620@0_0804_8P4R_5% E @0_0402_5% MC_CD# D <31,32> S2_A20 <31,32> S2_RDY# <31,32> S2_A21 <31,32> S2_D11 <31,32> <31,32> <31,32> <31,32> S2_D5 S2_D12 S2_D6 S2_D13 <31,32> S2_D7 <31,32> S2_D14 <31,32> S2_CE1# <31,32> S2_D15 C <31,32> <31,32> <31,32> <31,32> S2_A10 S2_A13 S2_OE# S2_WE# <31,32> <31,32> <31,32> <31,32> S2_A8 S2_A12 S2_A24 S2_A15 SD_CMD SD_CD/DATA3 SD_DATA2 SM_D4 1620@0_0804_8P4R_5% SM_D3/MS_BS SM_D5 SM_D2/MS_SDIO SM_D6 1620@0_0804_8P4R_5% SM_D1/MS_RFU5 SM_D7 SM_D0/MS_RFU7 SM_LVD 1620@0_0804_8P4R_5% SM_WP# SM_WE# SM_R/B# SM_ALE 1620@0_0804_8P4R_5% SM_RE# SM_CLE SM_CE# MC_WP# 1620@0_0804_8P4R_5% RP130 RP131 RP132 RP133 RP134 D 1620@TAI_SOL 4 IN 1 MEMORY CONNECTOR RP144 RP145 RP146 1620@47K_0804_8P4R_5% 1620@47K_0804_8P4R_5% C 1620@47K_0804_8P4R_5% B B <31,32> S2_CD1# R987 1620@0_0402_5% <31,32> S2_CD2# R988 1620@0_0402_5% <31,32> R989 1620@0_0402_5% S2_VS2 S2_VS1 <31,32> Compal Electronics, Inc. A A Title 4 IN 1 CARD READER SOCKET AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 10 9 8 7 6 5 4 LA-1811 Wednesday, September 24, 2003 3 2 1.0 33 66 1 5 4 3 2 1 LANIO JP32 +3VALW ACTIVITY# C659 C660 C661 C662 C663 C664 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K R694 LANIO 3 0 0 _ 0 6 0 3 _ 5 % T=10mil LANIO D R1006 C665 0_0805_5% 1U_0603_10V6K D RJ45_RXX- <41> RJ45_RXX- LANVDD C666 C657 C658 0.1U_0402_10V6K 0.1U_0402_10V6K 1U_0603_10V6K <41> RJ45_RXX+ RJ45_RXX+ RJ45_TXX- <41> RJ45_TXX<41> RJ45_TXX+ LANVDD RJ45_TXX+ LINK10_100# R695 LANIO C667 3 0 0 _ 0 6 0 3 _ 5 % T=10mil AMP RJ45 with LED 10U_0805_10V4Z Close to U39 pin58 PCI_AD[0..31] PCI_CBE#[0..3] <26,31,35,36,43> PCI_CBE#[0..3] PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3 C669 LANIO LANVDD <41> R J 4 5 _ G N D LANVDD Power C R697 75_0402_1% U39 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 RJ45_GND LANGND 1000P_1206_2KV7K L43 LAN_IO C670 0.1U_0402_10V6K KC FBM_L11-201209-601LMT 0805 C672 C673 C671 4.7U_0805_10V4Z C674 0.1U_0402_10V6K Termination plane should be copled to chassis ground and also depends on safety concern 0.1U_0402_10V6K 0.1U_0402_10V6K U40 C675 0.1U_0402_10V6K EEDO EEDI EESK EECS C676 LANIO 0.1U_0402_10V6K AT93C46-10SI-2.7_SO8 Please close to LAN IC LAN_TX+ LAN_TX- R698 5.6K_0402_5% LANIO R700 49.9_0402_1% R699 49.9_0402_1% LAN_RX+ LAN_RX- U41 CLKOUT XTALFB RJ45_TXXRJ45_TXX+ C677 0.1U_0402_10V6K R701 ISOB 1:1 LAN_TXLAN_TX+ 15K_0402_5% R702 1K_0402_5% LAN_RXLAN_RX+ +3VS RJ45_RXXRJ45_RXX+ PCI_AD19 R703 100_0402_5% B R704 5.6K_0603_1% R705 75_0402_1% NS0013_16P R708 49.9_0402_1% R707 49.9_0402_1% <26,31,35,36,43> PCI_PAR <26,31,35,36,43> PCI_FRAME# <26,31,35,36,43> PCI_IRDY# <26,31,35,36,43> PCI_TRDY# <26,31,35,36,43> PCI_DEVSEL# <26,31,35,36,43> PCI_STOP# R706 75_0402_1% B RJ45_GND C678 1000P_1206_2KV7K CHASSIS GND C679 0.1U_0402_10V6K AC-Link <26,31,35,36,43> PCI_PERR# <26,31,35,36,43> PCI_SERR# <26> PCI_REQ#1 <26> PCI_GNT#1 <26,36> PCI_PIRQD# <31,36,43,46,47> ONBD_LAN_PME# <11,26,30,31,35,36,43,46> PCI_RST# <26> CLK_PCI_LAN <26,31,35,36,43> PCI_CLKRUN# Y5 CLKOUT XTALFB 25MHZ_20P_1BX25000CK1A C680 C681 27P_0402_50V8J 27P_0402_50V8J LANIO Power RTL8101L_LQFP100 R709 @22_0402_5% A C ACTIVITY# LINK10_100# PCI I/F LAN I/F <26,29,31,35,36,43> PCI_AD[0..31] R696 75_0402_1% Layout Recommend : 1. LAN_RD+, LAN_RD- should be equal length as possible 2. LAN_TD+, LAN_TD- should be equal length as possible 3. The Maximum trace length between LAN chip(U22) and Magnetic(U24) is 12cm(4.7") 4. The distance between RJ45(Conn.) and Magnetic(U24) should be as short as possible A C682 @10P_0402_50V8K Compal Electronics, Inc. LAN RealTech8101BL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 34 of 66 5 4 3 2 1 R711 1 +3VS +3VS 1 C683 1 C684 1 C685 1 C686 1 C687 1 C688 1 C689 C690 10K_0402_5% RP135 2 +3VS 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 4.7K_1206_8P4R_5% 86 96 10 11 1 L44 BLM21A601SPT_0805 1 C697 2 2 R715 2 1 C692 1000P_0402_50V7K 2 1 C693 1000P_0402_50V7K 2 1 C694 1000P_0402_50V7K 2 C695 1000P_0402_50V7K 0.01U_0402_16V7K 1K_0402_5% BIAS CURRENT C R716 6.34K_0603_1% Near 1394 IC C698 1 OSCILLATOR 22P_0402_25V8K 30ppm CLK_PCI_1394 C699 FILTER 100_0402_5% SDA_1394 EEPROM 2 WIRE BUS 1 SCL_1394 R720 1 R717 22P_0402_25V8K C700 0.1U_0402_10V6K PCI_AD16 1 R721 C701 56.2_0402_1% 2 1U_0603_10V6K Connect To Shielding GND POWER CLASS 2 XTPBIAS0 XTPA0+ XTPA0XTPB0+ XTPB0- 1 AMP_440168-2 R723 56.2_0402_1% 1 1 R727 5.11K_0402_1% 2 The connector depend on defferent project 2 C702 220P_0402_50V7K 2 TSB43AB21_PQFP128 R722 56.2_0402_1% 2 PLLGND1 REG_EN AGND AGND AGND AGND AGND AGND AGND DGND DGND REG18 DGND DGND DGND DGND DGND DGND DGND REG18 DGND 220_0804_8P4R_5% 8 9 109 110 111 117 126 127 128 17 23 30 33 44 55 64 68 75 83 93 103 SDA_1394 SCL_1394 B EEPROM cancel, need System Support RP142 R726 JP33 2 PHY PORT 1 CLK_PCI_1394 2 56.2_0402_1% G_RST# connect to PCIRST# 1 1 C696 4.7U_0805_10V4Z B 2 1000P_0402_50V7K +3VS PCI BUS INTERFACE <26,31,34,36,43> PCI_SERR# <26,31,34,36,43> PCI_PAR <26,31,34,36,43> PCI_CLKRUN# <11,26,30,31,34,36,43,46> PCI_RST# 1 1 C691 X3 24.576MHz_16P_3XG-24576-43E1 <26,31,34,36,43> PCI_FRAME# <26,31,34,36,43> PCI_IRDY# <26,31,34,36,43> PCI_TRDY# <26,31,34,36,43> PCI_DEVSEL# <26,31,34,36,43> PCI_STOP# <26,31,34,36,43> PCI_PERR# <10,17,26,31,36> PCI_PIRQA# @10_0402_5% 2 1 ID: AD16 +3VS 2 <26,31,34,36,43> PCI_CBE#3 <26,31,34,36,43> PCI_CBE#2 <26,31,34,36,43> PCI_CBE#1 <26,31,34,36,43> PCI_CBE#0 <26> CLK_PCI_1394 <26> PCI_GNT#0 <26> PCI_REQ#0 TSB43AB21 /(TSB43AB22) D +3VS CYCLEOUT/CARDBUS CNA TEST17 TEST16 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 C 87 U42 CYCLEIN PCI_AD[0..31] PCI_AD[0..31] VDDP VDDP VDDP VDDP VDDP <26,29,31,34,36,43> 20 35 48 62 78 D C703 ** GPIO2 and GPIO3 defaults as an input and if it is not implemented, it is recommended that it be pulled low to ground with a 220 ohm resistor. @10P_0402_25V8K Close Chip C704 0.1U_0402_10V6K 1 2 1 2 C705 0.1U_0402_10V6K CLOSE CHIP A A Compal Electronics, Inc. Title IEEE 1394 CONTROLLER THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 Sheet 1 35 of 66 1 2 3 +3V +3VS +3V R1060 R1061 4 +3V_USB20 NEC@0_0402_5% @0_0402_5% NEC@30MHZ_30PPM Y7 L U54 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 1 CLK_PCI_USB20 R1028 @10_0402_5% C915 @15P_0402_50V8J <26,31,34,35,43> PCI_CBE#[0..3] C964 R1105 NEC@16P_0603_50V8J N E C @ 1 0 0 _ 0 4 0 2 _ 5 % Note: PLACE CLOSE TO U54 . For NEC USB2.0 only . C965 NEC@16P_0603_50V8J PCI_AD[0..31] <26,29,31,34,35,43> PCI_AD[0..31] 2 5 1 R1024 USB 2.0 CONTROLLER uPD720101F1-EA8 FBGA144 PCI_CBE#[0..3] PCI_CBE#3 PCI_CBE#2 PCI_CBE#1 PCI_CBE#0 <26,31,34,35,43> PCI_PAR <26,31,34,35,43> PCI_FRAME# <26,31,34,35,43> PCI_IRDY# <26,31,34,35,43> PCI_TRDY# <26,31,34,35,43> PCI_STOP# PCI_AD23 R1112 <26,31,34,35,43> PCI_DEVSEL# <26,31,34,35,43> PCI_PERR# <26,31,34,35,43> PCI_SERR# <10,17,26,31,35> PCI_PIRQA# <26,43> PCI_PIRQC# <26,34> PCI_PIRQD# <26> CLK_PCI_USB20 <31,32,46> G_RST# <31,34,43,46,47> USB20_PME# <27> PCI_PAR PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# NEC@100_0402_5% PCI_DEVSEL# PCI_REQ# PCI_GNT# PCI_PERR# PCI_SERR# PCI_PIRQA# PCI_PIRQC# PCI_PIRQD# CLK_PCI_USB20 USB20_NEC_P0-_R USB20_NEC_P0USB20_NEC_P0+ USB20_NEC_P0+_R R1025 NEC@36_0603_1% R1026 NEC@36_0603_1% USB20_NEC_P1-_R USB20_NEC_P1USB20_NEC_P1+ USB20_NEC_P1+_R R1027 NEC@42.2_0603_1% R1029 NEC@42.2_0603_1% USB20_NEC_P2-_R USB20_NEC_P2USB20_NEC_P2+ USB20_NEC_P2+_R R1030 NEC@42.2_0603_1% R1031 NEC@42.2_0603_1% USB20_NEC_P3-_R USB20_NEC_P3USB20_NEC_P3+ USB20_NEC_P3+_R R1032 NEC@42.2_0603_1% R1033 NEC@42.2_0603_1% USB20_NEC_P4-_R USB20_NEC_P4USB20_NEC_P4+ USB20_NEC_P4+_R R1034 NEC@42.2_0603_1% R1035 NEC@42.2_0603_1% @0_0402_5% USB20_NEC_P0- <44> USB20_NEC_P0+ <44> USB20_NEC_P1- <44> USB20_NEC_P1+ <44> L Note: PLACE CLOSE TO U54 . For NEC USB2.0 only . USB20_NEC_P2- <44> USB20_NEC_P2+ <44> USB20_NEC_P3- <44> USB20_NEC_P3+ <44> USB20_NEC_P4- <41> USB20_NEC_P4+ <41> 2 +3V_USB20 C916 USB20_NEC_P0- R 1 0 3 6 USB20_NEC_P0+ R 1 0 3 7 @0.1U_0402_10V6K NEC@15K_0402_5% NEC@15K_0402_5% NEC@9.1K_0402_1% RP147 R1038 USB20_NEC_P1USB20_NEC_P1+ USB20_NEC_P2USB20_NEC_P2+ C917 @0.1U_0402_10V6K NEC@15K_1206_8P4R_5% RP148 OVCUR_USB20#0 OVCUR_USB20#1 OVCUR_USB20#3 OVCUR_USB20#4 USB20_NEC_P3USB20_NEC_P3+ USB20_NEC_P4USB20_NEC_P4+ OVCUR_USB20#0 <44> OVCUR_USB20#1 <44> R1039 R1040 NEC@10K_0402_5% + 3 V NEC@10K_0402_5% NEC@15K_1206_8P4R_5% USB_SMI# +3V 3 3 +3V C918 R1041 R1042 R1043 NEC@1.5K_0402_5% NEC@1.5K_0402_5% NEC@1.5K_0402_5% U55 @0.1U_0402_10V6K <11,26,30,31,34,35,43,46> PCI_RST# R 1 0 4 5 NEC@1.5K_0402_5% <26,31,34,35,43> PCI_CLKRUN# PCI_CLKRUN# R 1 0 4 7 R1048 NEC@0_0402_5% @0_0402_5% +3V @AT24C02N-10SC-2.7_SO8 R 1 0 4 6 @1.5K_0402_5% NEC@UPD720101F1-EA8_FBGA144 R1127 NEC@1.5K_0402_5% +3V +3V_USB20 R1049 NEC@0.1U_0402_10V6K NEC@0.1U_0402_10V6K NEC@10U_0805_10V4Z NEC@0.1U_0402_10V6K NEC@10U_0805_10V4Z NEC@0_0603_5% 4 <26,43> <26,43> <26,43> <26,43> PCI_REQ#3 PCI_REQ#4 PCI_GNT#3 PCI_GNT#4 PCI_REQ#3 PCI_REQ#4 PCI_GNT#3 PCI_GNT#4 R1050 R1051 R1052 R1053 @ 0 _ 0 4 0 2 _ 5 % PCI_REQ# NEC@0_0402_5% @ 0 _ 0 4 0 2 _ 5 % PCI_GNT# NEC@0_0402_5% C919 C920 C921 C922 C923 NEC@0.1U_0402_10V6K C924 C925 C926 C927 C928 C929 R1054 NEC@0_0603_5% NEC@0.1U_0402_10V6K NEC@0.1U_0402_10V6K NEC@10U_0805_10V4Z 4 NEC@10U_0805_10V4Z NEC@0.1U_0402_10V6K Compal Electronics, Inc. NEC uPD720101 - USB2.0 Controller THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 5 Sheet 36 of 66 A B C D E F G H +3VALW +3VALW +3VALW R729 +5VAMP_CODEC @100K_0402_1% 1 U18B <46> U45A 1 C712 R731 BEEP# R732 10K_0402_1% SN74LVC32APWLE_TSSOP14 1U_0603_10V6K SN74LVC14APWLE_TSSOP14 C713 R733 560_0402_5% 10K_0402_1% C714 1U_0603_10V6K VDDA_CODEC 0.22U_0603_10V7K U46 R735 W=40Mil +5VS 10K_0402_5% R736 10K_0402_1% C715 +3VALW R1063 MONO_IN MONO_IN1 39K_0603_1% R738 C719 MONO_INR C716 R956 4.7U_0805_10V4Z C720 0.1U_0402_10V6K SI9182DH-AD_MSOP8 C721 R739 PCM_SPK# C Q56 E 2SC2411K_SOT23 0.1U_0402_10V6K 10K_0402_5% B C979 C718 4.7U_0805_10V4Z R737 10K_0603_1% 1U_0603_25V4Z U32F <31> C717 30K_0603_1% 0.01U_0402_16V7K 1U_0603_10V6K 5 6 0 _ 0 4 0 2 _ 5 % SN74LVC14APWLE_TSSOP14 0.1U_0402_10V6K R740 +5VAMP_CODEC PIR BOM 92.09.01 JOPEN6 0_0805_5% +3VALW VDDA_CODEC JOPEN7 +5VAMP_CODEC U45C 2 JOPEN8 C722 <27> R741 C723 SB_SPKR 1U_0603_10V6K 5 6 0 _ 0 4 0 2 _ 5 % SN74LVC14APWLE_TSSOP14 0.1U_0402_10V6K C724 C725 0.1U_0402_10V6K 2 C726 0.1U_0402_10V6K C984 220P_0402_25V8K C985 220P_0402_25V8K C986 220P_0402_25V8K C987 470P_0402_25V8K C988 470P_0402_25V8K 10U_0805_6.3V6M D46 R742 @10K_0402 C727 0.1U_0402_10V6K RB751V_SOD323 L98 +3VS CHB1608B121_0603 C728 C729 C730 C989 470P_0402_25V8K 0.1U_0402_10V6K 0.1U_0402_10V6K 10U_0805_10V4Z C990 680P_0402_25V8K C991 680P_0402_25V8K C992 680P_0402_25V8K U47 MONO_INR <41,46> LINE_OUTL CONA# G LINE_OUTR Q101 MDMIC 2N7002_SOT23 1U_0603_25V4Z 2.2K_0402_5% +3VS R1167 0_1206_5% LINE_OUTR <38> C731 MD_MIC R746 D HPS S <38> PIR BOM & LAYOUT 92.09.01 LINE_OUTL <38> L_HP <38> R_HP <38> R1168 0_1206_5% <44> GNDA <30> CDROM_L R748 R749 4.7K_0402_5% 4.7K_0402_5% CDROM_R_L <30> CDROM_R R751 R752 4.7K_0402_5% 4.7K_0402_5% CDROM_R_R 3 C734 2.2U_0603_6.3V4Z CDROM_RC_L C735 2.2U_0603_6.3V4Z CDROM_RC_R C736 2.2U_0603_6.3V4Z CDGNDA R750 27_0402_5% R753 27_0402_5% GND AC97_BITCLK <27,44> CD_AGND R755 2.7K_0402_5% CD_GNA 3 GNDA AC97_SDIN0 <27> CLK_14M_CODEC 0_0402_5% PIR BOM 92.09.01 <30> <38,41> CLK_14M_CODEC <24> R754 R757 2.7K_0402_5% <38> MIC1 <38> MIC2 C737 1U_0603_10V6K C904 1U_0603_10V6K R758 @10_0402_5% C742 0_0402_5% <44> MD_SPK R761 R762 @0_0402_5% @4.7K_0402_5% MD_SPKR MD_SPKRC @0.1U_0402_16V4Z CODEC_REF C 7 4 3 @15P_0402_50V8J <27,44> AC97_RST# AUD_REF <27,29,44> AC97_SYNC C747 C905 <27,29,44> AC97_SDOUT C749 R763 0_0402_5% R764 0_0402_5% R766 R767 0.1U_0402_16V4Z <38,44> MUTE_LED <41> @0.1U_0402_16V4Z SPDIFO AFILT1 AFILT2 AFILT3 AFILT4 C744 270P_0402_50V7K 4.7K_0402_5% 4.7K_0402_5% L99 C750 270P_0402_50V7K C751 270P_0402_50V7K CHB1608B121_0603 C752 270P_0402_50V7K L104 @0_0402_5% C746 1U_0603_10V6K 0.1U_0402_10V6K R767 R766 X X FREQ. SEL 24.576MHZ Crystal Stuff Stuff 14.318MHZ External X Stuff 48MHZ External CHB1608B121_0603 R1103 4 C745 PIR BOM & LAYOUT 92.09.01 AD1981B_LQFP48 <27,29> SPDIF_OUT 4 R771 Compal Electronics, Inc. 4.7K_0402_5% Title AC97 CODEC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D E F Size Document Number Rev 1.0 LA-1811 Custom Date: Wednesday, September 24, 2003 G Sheet 37 H of 66 A B C +5VAMPP D +5VAMP L57 E R734 +5VS +5VAMP 0.1U_0402_10V6K 0_1206_5% 0_1206 1 JP34 SPKL+ SPKLSPKR+ SPKR- C890 C891 C892 10U_0805_10V3M L100 L101 L102 L103 C761 0.1U_0402_10V6K 10 dB 470P_0402_50V8J +5VAMP U52 C762 C763 470P_0402_50V8J BLM11A121SPT_0805 BLM11A121SPT_0805 BLM11A121SPT_0805 BLM11A121SPT_0805 1 C764 ACES_85205-0400 470P_0402_50V8J 470P_0402_50V8J R971 @100K_0402_5% C893 R972 100K_0402_5% PIR BOM & LAYOUT 92.09.01 0.047U_0603_10V7K 0.1U_0603_16V7K LINE_C_OUTR C894 SPKR+ R973 C895 SPKR0.047U_0603_10V7K C896 R974 @100K_0402_5% SPKL+ 0.1U_0603_16V7K LINE_C_OUTL SPKL- 2 <37> R_HP <37> L_HP C773 C774 + <37> LINE_OUTL 100K_0402_5% 100U_D2_10VM INTSPK_CR+ + <37> LINE_OUTR 100U_D2_10VM INTSPK_CL+ 2 R1158 R1164 R975 <46> EC_MUTE# 0_0402_5% 1K_0402_5% C897 0.47U_0603_10V7K 1K_0402_5% TI6017A2_TSSOP20 Gain Settings GAIN0 GAIN1 0 0 Av(inv) 6 dB 0 1 10 dB 1 0 15.6 dB 1 1 21.6 dB 3 3 AUDIO CONNECTOR JP41 <37> MIC1 <37> MIC2 HEADPHONE OUT/LINE OUT +5VS VOLBTN+# <41,44,46> VOLBTN-# <41,44,46> WIRELESS_BTN <42,46> CODEC_REF INTSPK_CR+ INTSPK_CL+ WIRELESS_LED# <42,43,44> MUTE_LED <37,44> <41> DOCK_LOUT_L <41> D O C K _ L O U T _ R +3VS ACES_88028-1600_16P D78 RB751V_SOD323 HPS <37> 4 4 Compal Electronics, Inc. AMP & Audio Jack THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 E Sheet 38 of 66 5 4 3 2 1 +3VS L55 HWMVCC +3VS D 0_0805_5% +3VS D C781 HWMVCC C782 0.1U_0402_10V6K 10U_0805_10V4Z R783 U51 @4.7K_0402_5% <26> +3VS <26,46> C785 C786 LPC LAD0 LAD1 LAD2 LAD3 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 0.1U_0402_10V6K GAME PORT @10K_0402 HARDWARE MONITOR RP152 R1108 +3VS PARALLEL PART R784 RP151 4.7K_0402_5% R1109 <40> <40> <40> <40> <40> <40> <40> <40> <40> <40> LPD0 LPD1 LPD2 LPD3 LPD4 LPD5 LPD6 LPD7 LPD0 LPD1 LPD2 LPD3 LPD4 LPD5 LPD6 LPD7 <40> <40> <40> <40> <40> <40> <40> <40> LPTSLCT LPTPE LPTBUSY LPTACK# LPTERR# LPTSLCTIN# LPTINIT# LPTAFD# LPTSTB# LPTSLCT LPTPE LPTBUSY LPTACK# LPTERR# LPTSLCTIN# LPTINIT# LPTAFD# LPTSTB# <40> <40> <40> <40> <40> <40> <40> <40> <40> IRRX IRTXOUT IRMODE <45> <45> <45> DCD1# DSR1# SIN1 RTS1# SOUT1 CTS1# DTR1# RI1# <41> <41> <41> <41> <41> <41> <41> <41> DSKCHG# +3VS CTS1# DSR1# DCD1# RI1# 4.7K_0804_8P4R_5% CTS2# DSR2# DCD2# RI2# 4.7K_0804_8P4R_5% SIN1 <40> FDDIR# STEP# WDATA# WGATE# TRACK0# WP# RDATA# HDSEL# DSKCHG# 3MODE# FDD TRACK0# WP# RDATA# 0.1U_0402_10V6K C <40> <40> DRV0# LFRAME# LPC_FRAME# <26,46> <26,46> <26,46> <26,46> C787 0.1U_0402_10V6K INDEX# MTR0# CLK_PCI_SIO SERIRQ LPC_DRQ#1 0.1U_0402_10V6K C784 INDEX# <8,17,26> NB_RST# <26> CLK_PCI_SIO <26,31,46> SIRQ +3VS SIN2 4.7K_0402_5% R1173 R787 4.7K_0402_5% IR 10K_0402 <44> DCD1# DSR1# SIN1 RTS1# SOUT1 CTS1# DTR1# RI1# MDC_DET# SERIAL POART 1 FIR_DET# R1174 FIR@10K_0402 C SERIAL POART 2 DCD2# SOUT2 SIN2 B +3VS +3VS +3VS CLK_LPC_48M CLK_PCI_SIO R792 R793 @10K_0402 RTS1# A Base address 1:2Eh/2Fh Base address 0:4Eh/4Fh @10K_0402 SOUT1 R796 2.2K_0402_5% 0:Normal Opreation 1:Test Mode CLK_LPC_48M <24> CLK_LPC_48M R790 R791 @33_0402 @10_0402_5% C788 C789 @15PF_0402 @10P_0402_50V8J R794 @10K_0402 DTR1# R795 10K_0402_1% B DSR2# CTS2# RI2# VT1211_LQFP128 R797 10K_0402_1% 0: Enable ROM I/F as GPIO 1:Enable Flash Rom A W +3VS R798 Super I/O strapping for VT1211 SOUT2 For Winbond 48M strapping 4.7K_0402_5% Compal Electronics, Inc. LPC SUPER I/O VIA VT1211 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Wednesday, September 24, 2003 39 1 66 5 4 3 2 Parallel Port +5V_PRN 1 FDD CONN. +5V_PRN +5VS D48 C791 D 4.7U_0805_10V4Z 2 <39> 2 C975 w=10mils +5VS 0.1U_0402_10V6K 1SS355_SOD323 R799 LPTSTB# LPTSTB# R800 33_0402_5% R801 <39> <39> <39> <39> LPTAFD# LPTAFD# 33_0402_5% LPTERR# LPTINIT# LPTSLCTIN# +5VS 1 1 LPTINIT# R802 33_0402_5% LPTSLCTIN# R803 33_0402_5% AFD/3M# FD0 LPTERR# FD1 PRNINIT# FD2 SLCTIN# FD3 C976 INDEX# 47P_0402_50V8J 220P_0402_25V8K MTR0# 220P_1206_8P4C_50V8K CP16 3MODE# STEP# WDATA# WGATE# FDDIR# 3MODE# STEP# FDDIR# 3MODE# STEP# <39> WDATA# WDATA# <39> WGATE# WGATE# <39> TRACK0# TRACK0# LPTACK# <39> LPTBUSY LPTBUSY 220P_1206_8P4C_50V8K <39> LPTSLCT DSKCHG# <39> <39> <39> LPTACK# FD7 LPTPE DRV0# DSKCHG# <39> <39> FD6 <39> INDEX# DRV0# DRV0# DSKCHG# MTR0# FDDIR# 220P_1206_8P4C_50V8K CP17 TRACK0# WP# RDATA# HDSEL# LPD[0..7] LPD[0..7] INDEX# <39> <39> FD5 <39> <39> CP15 FD4 C D JP38 220P_0402_25V8K 2.7K_0402_5% C792 PWRPRN 2 1 w=10mils C790 <39> MTR0# C WP# WP# <39> RDATA# RDATA# <39> HDSEL# HDSEL# ACES_85201-2605 PIR LAYOUT 92.09.01 LPTPE +5VS LPTSLCT +5VS 0.1U_0402_10V6K JP39 SUYIN_070536FR025S204AU C793 1 1 2 2 RP119 C794 DSKCHG# INDEX# WP# TRACK0# 0.1U_0402_10V6K 330_0804_8P4R_5% +5V_PRN RP120 CP11 FD0 FD1 FD2 FD3 B FD7 FD6 FD5 FD4 +5V_PRN 2.7K_1206_10P8R_5% +5V_PRN RP122 SLCTIN# PRNINIT# LPTERR# AFD/3M# LPTSLCT LPTPE LPTBUSY LPTACK# +5V_PRN 2.7K_1206_10P8R_5% +5VS AFD/3M# LPTERR# PRNINIT# SLCTIN# R1159 B RDATA# 220P_1206_8P4C_50V8K CP12 LPTSLCT LPTPE LPTBUSY LPTACK# 330_0402_5% R1160 WDATA# 330_0402_5% 220P_1206_8P4C_50V8K CP13 FD3 FD2 FD1 FD0 RP123 LPD3 LPD2 LPD1 LPD0 LPD7 LPD6 LPD5 LPD4 A FD3 FD2 FD1 FD0 FD7 FD6 FD5 FD4 220P_1206_8P4C_50V8K CP14 FD7 FD6 FD5 FD4 220P_1206_8P4C_50V8K A 68_1206_16P8R_5% Compal Electronics, Inc. Title Pallel port and FDD THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size B Date: Document Number LA-1811 Wednesday, September 24, 2003 Rev 1.0 Sheet 1 40 of 66 A B C D E +3VALW R879 10K_0402_5% <37,46> CONA# DOCK_PRESENT Q65 MMBT3904_SOT23 1 1 R880 470_0402_5% FM1 FM2 FM3 FM4 FM5 FM6 EMI Clip PAD SPR 36 PIN For X7 CF1 +3V JP40 USB_VCCA 1K_0603_5% R1131 +5VS @10K_0603_5% DOCK_LOUT_L DOCK_LOUT_R RJ45_GND TRACE AT LEAST 20 MIL R1141 200_0402_5% <34> <34> <34> <34> <34> RJ45_GND RJ45_RXXRJ45_RXX+ RJ45_TXXRJ45_TXX+ CF6 CF7 CF8 CF9 CF10 CF11 CF12 CF13 CF27 PIR BOM & LAYOUT 92.09.01 <39> <39> <39> <39> <39> <39> <39> <39> 2 H1 HOLEA H2 HOLEA H3 HOLEA H4 HOLEA H5 HOLEA H6 HOLEA H7 HOLEA H8 HOLEA H9 HOLEA H10 HOLEA H12 HOLEA H13 HOLEA H14 HOLEA H16 HOLEA H17 HOLEA H18 HOLEA H19 HOLEA H20 HOLEA H21 HOLEA H22 HOLEA H23 HOLEA H24 HOLEA H25 HOLEA H26 HOLEA H27 HOLEA C971 1000P_0402_50V7K <38,44,46> VOLBTN-# DOCKVIN CF5 R1161 VOLBTN+# <38,44,46> SIN1 SOUT1 DCD1# DTR1# RI1# DSR1# RTS1# CTS1# CF4 0_0805_5% R1140200_0402_5% JACK_DET# <46> SPDIFO_L TV_GND USB4USB4+ CF3 CF14 CF15 CF16 CF17 CF18 CF19 CF20 CF21 CF22 CF23 CF24 CF25 CF26 DOCK_LOUT_L <38> D O C K _ L O U T _ R <38> DOCK_PRESENT <11,17,48> TV_COMPS <11,17,48> TV_LUMA <11,17,48> TV_CRMA <48> TV_GND 2 R1139 CF2 EP1 EMI-126X142 DOCKVIN C972 FOX_QL11183-C6HQ 1000P_0402_50V7K PIR BOM & LAYOUT 92.09.01 USB20P4USB20P4+ USB20_NEC_P4USB20_NEC_P4+ <27> USB20P4<27> USB20P4+ <36> USB20_NEC_P4<36> USB20_NEC_P4+ L R1090 R1091 R1092 R1093 ATI@0_0402_5% ATI@0_0402_5% NEC@0_0402_5% NEC@0_0402_5% L USB4USB4+ <37> SPDIFO L105 SPDIFO SPDIFO_L KC FBM_L11-160808-601LMT 0603 C963 Note: PLACE CLOSE TO SPR PORT (JP40) 0.01U_0402_50V7K 3 3 Note: PLACE CLOSE TO SPR PORT (JP40) H28 HOLEA H30 HOLEA H31 HOLEA USB_VCCA @10U_0805_16V4Z_V1 C800 0.1U_0402_10V6K C798 C801 @1000P_0402_50V7K 4 4 L56 DC_IN DOCKVIN KC FBM-L18-453215-900LMA90T_1812 C804 C805 1000P_0402_50V7K 1000P_0402_50V7K Compal Electronics, Inc. SPR Connector THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 E Sheet 41 of 66 5 4 3 2 1 +5V PAV@HSMB-C172 BLUE_0805 D52 KSO16 PRES@PDTA114EK_SC59 KSI2 FOR POWER BUTTON BACKLIGHT ( PRES ) D 1 R881 KSI2 D56 PRES@HSMG-C170_GRN_0805 3 E 2 B Q117 C PAV@TC010-PS11CET_5P Q62 PWR_ACTIVE_PRES# 1 5 SW4 KSI1 PWR_ACTIVE_PRES# <46> C KSI1 PWR_ACTIVE_PAV# PWR_ACTIVE_PAV# FOR POWER BUTTON BACKLIGHT ( PAV ) <45,46> 3 FOR PROGRAMING PAV@PDTA114EK_SC59 PAV@TC010-PS11CET_5P D <46> <45,46> 3 5 SW3 KSI0 E KSI0 2 KSO16 B <46> PAV@91_0402_5% R1146 PRES@300_0402_5% <45,46> +3VS D53 PAV_LEDVCC PAV@TC010-PS11CET_5P 1 PAV@HSMB-C172 BLUE_0805 D54 PAV_LEDVCC R1014 <46> 10K_0402_5% WIRELESS_BTN PAV@HSMB-C172 BLUE_0805 D55 PAV_LEDVCC <38,46> B PAV@TC010-PS11CET_5P FOR TP ON OFF C842 C809 PDTA114EK_SC59 KSI3 <45,46> @.1UF_0402 1 2 C811 1 2 1 2 C810 1 1 2 C831 2 TC010-PS11CET_5P KSI3 @.1UF_0402 R882 27_0402_5% <46> @.1UF_0402 PRES@HSMG-C170_GRN_0805 D63 PRES_LEDVCC D57 INDICATOR PRES@HSMG-C170_GRN_0805 D58 PRES_LEDVCC NUMLED# D60 PAV_LEDVCC PRES_LEDVCC <44,46> PAV@HSMB-C172 BLUE_0805 D65 PAV_LEDVCC E B 2 D59 <44> PRES@HSMG-C170_GRN_0805 D61 PRES_LEDVCC Q71 D64 <46> 2 1 2 3 Q69 PIR BOM 92.09.01 C 1 2 2 1 R888 130_0402_5% PIR BOM 92.09.01 R1057 A 2 PAV@1K_0402_5% 2 PAV@10K_0402_5% 1 1 R1058 130_0402_5% PDTA114EK_SC59 D62 PAV@HSMB-C172 BLUE_0805 1 WIRELESS_LED# E FOR WIRLESS LED ( PAV ) R889 PAV@91_0402_5% WIRELESS_LED# B PAV_LEDVCC A PAV@HSMB-C172 BLUE_0805 130_0402_5% 10K_0402_5% R885 R890 R1138 <38,43,44> TP_OFF_LED# 1 PIR BOM 92.09.01 3 1 MMBT3904_SOT23 1K_0402_5% PAV@HSMB-C172 BLUE_0805 D92 1 Q116 CARD_LED# CARD_LED# Q70 Compal Electronics, Inc. PAV@MMBT3904_SOT23 Title 3 LED INDICATOR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 B C PDTA114EK_SC59 C 1 R1137 <31> Q68 PDTA114EK_SC59 PAV_LEDVCC PAV@HSMB-C172 BLUE_0805 3 PAV_LEDVCC PAV@HSMB-C172 BLUE_0805 E CAPSLED# 3 <46> 2 PRES_1520@12-21SYGC/S530-E1/TR8_GRN 2 PAV_LEDVCC R1136 130_0402_5% PIR BOM 92.09.01 B PRES_LEDVCC 1 FOR CARDREADER ( PAV /PRES ) C Q66 C @.1UF_0402 1 5 SW7 @.1UF_0402 FOR 3 PROGRAMING BUTTON BACKLIGHT (PAV) PAV@HSMB-C172 BLUE_0805 E 2 WIRELESS_BTN 3 2 5 SW6 C PWR_BACK# PWR_BACK# FOR WIRELESS ON OFF B 5 SW5 4 3 2 Size B Date: Document Number Rev 1.0 LA-1811 Wednesday, September 24, 2003 Sheet 1 42 of 66 A B 1 C LAN RESERVED TIP JP12 KEY <38,42,44> WIRELESS_LED# <44,46> 0.1U_0402_10V6K +3VS 0.1U_0402_10V6K D88 RB751V_SOD323 W=40mils PCI_PIRQC# <26,36> PCI_REQ#4 C280 C269 C270 C271 CLK_PCI_MINI W=40mils +3VS <26,36> PCI_REQ#3 4.7U_0805_10V4Z 1000P_0402_50V7K PCI_GNT#3 <26,36> MDM_PME# MINIPCI_PME# <26,31,34,35,36> PCI_AD31 <26,31,34,35,36> PCI_AD29 <26,31,34,35,36> PCI_AD27 <26,31,34,35,36> PCI_AD25 <44> MINIPCI_AD22 <26,31,34,35,36> PCI_CBE#3 <26,31,34,35,36> PCI_AD23 CLK_PCI_MINI R302 2 @10_0402_5% C275 @15P_0402_50V8J +5VS PCI_GNT#4 <26,36> +3VALW PCI_RST# <11,26,30,31,34,35,36,46> W=40mils <26> CLK_PCI_MINI 1 LAN RESERVED RING KEY W=30mils <26,36> PCI_PIRQC# E 1N4148_SOT23 WL_ON D89 WL_ON D MINIPCI_AD22 R301 <26,31,34,35,36> PCI_AD21 <26,31,34,35,36> PCI_AD19 PCI_AD18 100_0402_5% PCI_AD22 PCI_AD18 <26,31,34,35,36> PCI_AD17 <26,31,34,35,36> PCI_CBE#2 <26,31,34,35,36> PCI_IRDY# C272 MDM_PME# <31,34,36,46,47> MINIPCI_PME# <44> PCI_AD30 <26,31,34,35,36> C273 0.1U_0402_10V6K C281 0.1U_0402_10V6K 4.7U_0805_10V4Z 1000P_0402_50V7K PCI_AD28 <26,31,34,35,36> PCI_AD26 <26,29,31,34,35,36> PCI_AD24 <26,31,34,35,36> IDSEL : AD18 PCI_AD22 PCI_AD20 PCI_PAR PCI_AD18 PCI_AD16 <26,31,34,35,36> <26,31,34,35,36> <26,31,34,35,36> <26,31,34,35,36> <26,31,34,35,36> 2 PCI_FRAME# <26,31,34,35,36> PCI_TRDY# <26,31,34,35,36> PCI_STOP# <26,31,34,35,36> <26,31,34,35,36> PCI_CLKRUN# <26,31,34,35,36> PCI_SERR# <26,31,34,35,36> PCI_PERR# <26,31,34,35,36> PCI_CBE#1 <26,31,34,35,36> PCI_AD14 PCI_DEVSEL# <26,31,34,35,36> +5VS PCI_AD15 <26,31,34,35,36> PCI_AD13 <26,31,34,35,36> PCI_AD11 <26,31,34,35,36> <26,31,34,35,36> PCI_AD12 <26,31,34,35,36> PCI_AD10 PCI_AD9 <26,31,34,35,36> PCI_CBE#0 <26,31,34,35,36> <26,31,34,35,36> PCI_AD8 <26,31,34,35,36> PCI_AD7 PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0 <26,31,34,35,36> PCI_AD5 <26,31,34,35,36> PCI_AD3 +5VS <26,31,34,35,36> PCI_AD1 C274 W=30mils R304 1000P_0402_50V7K C276 C277 C278 4.7U_0805_10V4Z <26,31,34,35,36> <26,31,34,35,36> <26,31,34,35,36> <26,31,34,35,36> 0.1U_0402_10V6K +3VALW @10K_0402_5% 1000P_0402_50V7K C284 C285 C286 4.7U_0805_10V4Z W=30mils +5VS 3 C282 W=40mils +3VALW 3 0.1U_0402_10V6K AMP_1318644-1 @1000P_0402_50V7K 4 4 Compal Electronics, Inc. Mini PCI Slot THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 E Sheet 43 of 66 RJ11 CONN. +3VS +3VS +3V @0.1U_0402_10V6K C300 C303 C304 C954 C955 R319 MDC Conn. C301 1000P_0402_50V7K +5VMDC C298 @ 0 _ 0 8 0 5 _ 5 % +5VS C299 +3VS FOXCONN_JM34613-L002-TR 0.1U_0402_10V6K JP16 @1000P_0402_50V7K 4.7U_0805_10V4Z 0.1U_0402_10V6K 1000P_0402_50V7K 0.1U_0402_10V6K JP17 C302 R320 @1000P_0402_50V7K <37> 100K_0402_5% MD_MIC MD_SPK <37> MDC_DET# <39> JP47 R323 10K_0402_5% TIP MRING +3V +3V MOLEX_53398_0290 R325 R326 <27,29,37> AC97_SDOUT <27,37> AC97_RST# AC97_SYNC <27,29,37> AC97_SDIN1 <27> 22_0402_5% 22_0402_5% C977 AC97_BITCLK <27,37> ACES_88021-3000 C978 @220PF_3KV_1808 @220PF_3KV_1808 R327 @10_0402_5% USB_VCCA W=40mils Front Board CONNECTOR C305 @22P_0402_25V8K Pavilion only C307 + C308 C309 100U_D2_6.3VM PIR BOM 92.09.01 1000P_0402_50V7K 0.1U_0402_10V6K RIGHT USB CONNECTOR 0 +5V JP42 PAV@CHB1608B121_0603 PAV@CHB1608B121_0603 PAV@CHB1608B121_0603 <38,41,46> VOLBTN+# <45,46> BATLED_0# <38,41,46> VOLBTN-# L79 L80 L81 USB_VCCA C310 <27> USB20P0<27> USB20P0+ <36> USB20_NEC_P0<36> USB20_NEC_P0+ U13 0.1U_0402_10V6K PAV@CHB1608B121_0603 PAV@CHB1608B121_0603 PAV@CHB1608B121_0603 PAV@CHB1608B121_0603 <45> ACT_LED +5VALW +3VS <37,38> MUTE_LED C812 L83 L84 L85 L86 0.47U_0603_10V7K PAV@CHB1608B121_0603 PAV@CHB1608B121_0603 PAV@CHB1608U301_0603 JP18 USB0USB0+ ATI@0_0402_5% ATI@0_0402_5% NEC@0_0402_5% NEC@0_0402_5% suyin_020167mr004s511zu_4p Note: PLACE CLOSE TO EACH USB PORT (JP18) 330K_0402_5% AATI4610GV-T1_SOT23_5 R1071 R1072 R809 <42> PAV_LEDVCC <45,46> PMLED_1# +5VS L R893 USB20P0R976 USB20P0+ R977 USB20_NEC_P0- R 1 0 6 9 USB20_NEC_P0+ R 1 0 7 0 L87 L88 L89 4.7K_0603_1% R894 ATI@0_0402_5% NEC@0_0402_5% O V C U R # 0 <27> OVCUR_USB20#0 <36> C832 USB_VCCB W=40mils 1000P_0402_50V7K PAV@ACES_85201-1405 PIR BOM 92.09.01 C312 + PMLED_1 <45> BATLED_0 L90 +5V 0.1U_0402_10V6K C311 JP45 PRES@CHB1608B121_0603 L91 PRES@CHB1608B121_0603 L92 PRES@CHB1608B121_0603 U14 LEFT USB CONNECTOR 2 0.1U_0402_10V6K C813 <27> USB20P2<27> USB20P2+ <36> USB20_NEC_P2<36> USB20_NEC_P2+ 0.47U_0603_10V7K 330K_0402_5% L93 L94 <42,46> PRES_LEDVCC +5VS 1000P_0402_50V7K USB_VCCB R895 ACT_LED C314 100U_D2_6.3VM PRESARIO only <45> C313 560K_0402_5% Front Board CONNECTOR AATI4610GV-T1_SOT23_5 R1075 R1076 PRES@CHB1608B121_0603 PRES@CHB1608U301_0603 R810 ATI@0_0402_5% NEC@0_0402_5% R896 O V C U R # 1 <27> OVCUR_USB20#1 <36> L USB20P2R978 USB20P2+ R979 USB20_NEC_P2- R 1 0 7 3 USB20_NEC_P2+ R 1 0 7 4 JP19 ATI@0_0402_5% USB2ATI@0_0402_5% USB2+ NEC@0_0402_5% NEC@0_0402_5% suyin_020167mr004s511zu_4p Note: PLACE CLOSE TO EACH USB PORT (JP19) C833 PRES@ACES_85201-0805 4.7K_0603_1% 1000P_0402_50V7K USB_VCCB TP CONNECTOR W=40mils 560K_0402_5% L +5V Note: PLACE CLOSE TO EACH USB PORT C315 + C316 C317 100U_D2_6.3VM L95 CHB1608U301_0603JP44 BT CONNECTOR L96 <46> <46> CHB1608B121_0603 TP_DATA TP_CLK L97 LEFT USB CONNECTOR 1 +3VS CHB1608B121_0603 <27> USB20P1<27> USB20P1+ <36> USB20_NEC_P1<36> USB20_NEC_P1+ +3VS R1055 10K_0402_5% SI2301DS_SOT23 ACES_87152-0807 D <43,46> USB KEY WL_ON G Q100 2N7002_SOT23 <27> <27> USB20P3USB20P3+ R1079 R1080 L 0_0603_5% 0_0603_5% Note: Place close to JP46 PIR BOM 92.09.01 +5V USB3USB3+ ACES_85201-0405 L Q99 USB20P1USB20P1+ USB20_NEC_P1USB20_NEC_P1+ R982 R983 R1077 R1078 JP20 ATI@0_0402_5% USB1ATI@0_0402_5% USB1+ NEC@0_0402_5% NEC@0_0402_5% Note: PLACE CLOSE TO EACH USB PORT (JP20) suyin_020167mr004s511zu_4p JP43 BT_VCC S BT_VCC R981 R980 USB20P5+ USB20P5- L JP46 <27> <27> 1000P_0402_50V7K 0.1U_0402_10V6K <38,42,43> WIRELESS_LED# <43> MINIPCI_AD22 <43> MINIPCI_PME# <36> USB20_NEC_P3+ <36> USB20_NEC_P3- ATI@0_0402_5%USB5+ ATI@0_0402_5%USB5- Note: Place close to JP43 D87 1N4148_SOT23 R1083 R1084 100_0402_5% 100_0402_5% C957 10U_0805_10V3M C958 0.1U_0402_10V6K ACES_85201-0805 R1082 NEC@0_0402_5% USB5+ R1081 NEC@0_0402_5% USB5- L Note: Place close to JP43.1 Compal Electronics, Inc. MDC , Bluetooth & USB CONN. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 Sheet 44 of 66 5 4 3 2 1 SW8 PRES@TC010-PS11CET_5P INT_KBD CONN. KSI[0..7] KSO[0..15] D ACES_85201-2405 KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15 KSI[0..7] KSO[0..15] <42,46> <46> CP1 Power BTN KSI3 KSO5 KSO1 KSI0 R305 D28 100K_0402_5% ON/OFF# +3VALW D29 D27 @PSOT03C 470_0402_5% RLZ20A_LL34 22K EC_ON EC_ON R307 0 _ 0 4 0 2 _ 5 %22K Q21 DTC124EK_SOT23 100P_1206_8P4C_50V8 CP4 KSI4 KSI5 KSO0 KSI2 +5VS 1000P_0402_50V7K FIR Module WHEN R=0,Vbe=1.35V WHEN R=33K,Vbe=0.8V D +3VS Q112 @2N7002_SOT23 R308 R309 G FIR@10_1206_5% S FIR@10_1206_5% 100P_1206_8P4C_50V8 FIR@10U_0805_6.3VM KSO14 KSO11 KSO10 KSO15 SW9 C291 FIR@0.1U_0402_10V6K LID_SW# FIR@22U_1206_16V4Z <46> T = 20mil 100P_1206_8P4C_50V8 CP6 KSO6 KSO3 KSO12 KSO13 +5VS_FIR C290 CP5 JP13 C D R306 C289 <46> SW1 PAV@TC010-PS11CET_5P DAN202U_SC70 ON/OFFBTN# 100P_1206_8P4C_50V8 CP3 <46> EC_PWR_ON# <51> 100P_1206_8P4C_50V8 CP2 KSO2 KSO4 KSO7 KSO8 KSI1 KSI7 KSI6 KSO9 +3VALW ON/OFF# ON/OFFBTN# U12 C293 FIR@0.1U_0402_10V6K T = 12mil T = 12mil C294 ESE11MV9_4P + C292 T = 40mil IRTXOUT IRMODE IRTXOUT <39> IRMODE <39> FIR@0.1U_0402_10V6K T = 12mil 100P_1206_8P4C_50V8 IRRX IRRX C <39> FIR@IR_VISHAY_TFDU6101E-TR4_8P D30 @PSOT03C Touch Pad & Status LED Conn. +3VALW Q92 DTA114EK E 10K B <44,46> PMLED_1# +3VALW Q93 DTA114EK E 10K B <44,46> BATLED_0# 10K C 10K C B B R923 220_0402_5% PMLED_1 R924 <44> 220_0402_5% BATLED_0 <44> +5VS Q94 DTA114EK E 10K B <30> ACT_LED# 10K C PIR BOM 92.09.01 R925 130_0402_5% ACT_LED <44> A A Compal Electronics, Inc. KBD,ON/OFF,T/P,LED & FIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 1 Sheet 45 of 66 A B C D E +3VALW R1175 0.1U_0402_10V6K +3VALW C318 C319 C320 +3VALW +3VS C321 4.7U_0805_6.3V6K R926 R927 EC_AVCC @0_0603_5% 0_0603_5% 0.01U_0402_16V7K C323 C324 U15 0.1U_0402_10V6K * BATT1.1 1K_0402_5% C322 1U_0603_10V6K PRES_DETECT R1148 10K_0402_5% 4.7U_0805_6.3V6K EC_AVCC MURATA BLM11A20PT_0603 1 C326 BATT_TEMPA <51> <26,31,39> C327 1000P_0402_50V7K 0.1U_0402_10V6K PRES_LEDVCC <42,44> 6.2K_0402_5% L32 +3VALW R1147 L33 ECAGND MURATA BLM11A20PT_0603 R332 SIRQ 0.1U_0402_10V6K ECAGND 0.01U_0402_16V7K C325 <26,39> LPC_FRAME# <26,39> LPC_AD0 <26,39> LPC_AD1 <26,39> LPC_AD2 <26,39> LPC_AD3 <26> CLK_PCI_EC ADP_IR PRES_DETECT BID Host interface AD Input CLK_PCI_EC EC_RST# +3VALW VOLBTN-# * BATT_OVP <52> R331 ADP_I 10K_0402_5% J1 JOPEN SCI# SCI# <27> <27> R984 GA20 KBRST# GA20 KBRST# KSI[0..7] KSO[0..15] <42,45> KSI[0..7] <45> KSO[0..15] CLK_PCI_EC R337 @10_0402_5% @15P_0402_50V8J R 1 1 6 9 10K_0402_5% +5V TP_DATA TP_CLK R 1 1 7 0 10K_0402_5% R 1 1 7 1 10K_0402_5% +5VS PS2_DATA PS2_CLK EC_TINIT# EC_TCK EC_TDO EC_TDI EC_TMS +5VS R 1 1 6 2 10K_0402_5% KBD_DATA KBD_CLK R 1 1 7 2 10K_0402_5% +3VALW RP23 TP_OFF_LED# <44> TP_CLK <44> TP_DATA <45> LID_SW# <42> PWR_ACTIVE_PAV# 10K_0804_8P4R_5% SD309100200 +5VALW RP24 EC_SMD_2 EC_SMC_2 EC_SMD_1 EC_SMC_1 PORTB EC_SMC_2 EC_SMD_2 FANSPEED1 PORTC AC_IN KBD_CLK KBD_DATA PS2_CLK PS2_DATA TP_CLK TP_DATA LID_SW# PWR_ACTIVE_PAV# 20M_0603_5% 10K_0804_8P4R_5% PORTE R986 PS2 interface KBA1 LID_SW# R 3 4 2 20K_0402_5% 32.768KHZ_12.5P_MC-306 PORTI CRY2 <49> <47,49> <55> SUSP# VR_ON FRD# FWR# PORTJ-1 SELIO# <27> EC_SMI# <38> EC_MUTE# <31,32,36> G_RST# <27> EC_SWI# <44,45> BATLED_0# <42> PWR_ACTIVE_PRES# EC_SMI# VOLBTN+# PORTD-2 PORTJ-2 PWR_ACTIVE_PRES# SYSON <47> +3VS R344 FSEL# 1 0 DEV 1 0 0 PROG 1 1 0 PORTK PORTM 1 (ENV1) R333 10K_0402_5% R334 KBA2 KBA3 (BADDR1) KBA5 (SHBM) @10K_0402_5% R335 10K_0402_5% KSO16 <42> R 3 3 6 10K_0402_5% PMLED_1# <44,45> EC_SMC_1 <47,51> EEPROM/BATTERY EC_SMD_1 <47,51> R985 @0_0402_5% R113533_0402_5% PWRBTN_OUT# <27> EC_SMC_2 <7> THERMAL EC_SMD_2 <7> FANSPEED1 <7> PME_EC# <31,34,36,43,47> EC_THERM# <27> FANSPEED2 <7> +3VALW WL_ON <43,44> R338 ON/OFF# SLP_S5# M_SEN# CONA# PCI_RST# <11,26,30,31,34,35,36,43> VTT_PWRGD <24,27,48> R929 @1K_0402_5% R931 1K_0402_5% 10K_0402_5% AC_IN D36 ACIN RB751V_SOD323 <27,50,53> <45> <27> <25> <37,41> ADB[0..7] ADB[0..7] KBA[0..19] KBA[0..19] <47> <47> EC DEBUG port JP21 EC_TINIT# EC_TCK EC_TDO EC_TDI EC_TMS FRD# FWR# <47> <47> SELIO# <47> +5VALW 3 KSO16 KSO17 PMLED_1# @96212-1011S VOLBTN+# <38,41,44> NUMLED# <42> CAPSLED# <42> +3VS R959 10K_0402_5% R960 10K_0402_5% VOLBTN+# VOLBTN-# FSEL# KBA16 KBA17 KBA18 KBA19 PORTL R1123 @10K_0402_5% FSTCHG <52> 10K_0402_5% @ 10K_0402_5% 4 4 PC87591L-VPCN01 A2_LQFP176 ECAGND C911 1U_0603_10V6K Compal Electronics, Inc. KBD EC CTRL-NS PC87591L THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A 2 BID KBA8 KBA9 KBA10 KBA11 KBA12 KBA13 KBA14 KBA15 MMO_ON <42> PWR_BACK# <27> EC_RSMRST# <31> PCM_SUSP# <10,17,25> ENAVDD <25> BKOFF# 0 (BADDR0) ADB0 ADB1 ADB2 ADB3 ADB4 ADB5 ADB6 ADB7 C331 10P_0402_50V8K Y3 0 OBD SCI# @0_0402_5% ACOFF <52> PM_BATLOW# <27> EC_ON <45> LID_OUT# <27> TP_OFF_LED# <42> KBA0 KBA1 KBA2 KBA3 KBA4 KBA5 KBA6 KBA7 PORTH TRIS SHBM=1: Enable shared memory with host BIOS TRIS=1: While in IRE and OBD, float all the signals for clip-on ISE use R341 C330 10P_0402_50V8K M_SEN# R345 M_SEN# JTAG debug port 120K_0402_5% 0 +3VALW JACK_DET# <41> SLP_S3# <27> PORTD-1 CRY1 R340 +3VALW KSO16 KSO17 PMLED_1# EC_SMC_1 EC_SMD_1 Key matrix scan R 1 1 6 3 10K_0402_5% FSEL# SELIO# FRD# EC_SMI# 3 INVT_PWM <25> BEEP# <37> PWM or PORTA KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 C329 2 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 ENV1 0 DAC_BRIG <25> EN_FAN1 <7> IREF <52> EN_FAN2 <7> DA output 0_0402_5% <51,52> ENV0 IRE C328 0.22U_0603_10V7K WIRELESS_BTN <38,42> VOLBTN-# <38,41,44> 10K_0402_5% <27> I/O Address Index Data 2E 2F 4E 4F (HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1 Reserved BADDR1-0 0 0 0 1 1 0 1 1 B C D Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 E Sheet 46 of 66 <46> ADB[0..7] <46> KBA[0..19] OUTPUT ADB[0..7] KBA[0..19] +5VALW C333 @0.1U_0402_16V7K U17 +3VALW ADB0 ADB1 ADB2 ADB3 ADB4 ADB5 ADB6 ADB7 KBA2 <46> SELIO# SELIO# LARST# SN74LVC32APWLE_TSSOP14 U18A R352 @SN74HCT273PW_TSSOP20 C334 +3VALW @20K_0402_5% U19 +3VALW +3VALW +3VALW SUSP# C336 0.1U_0402_10V6K <46,49> R354 R356 4.7K_0402_5% 10K_0402_5% G +3VALW FWE# Q29 EC_FLASH# <27> S FWE# KBA17 KBA14 KBA13 KBA8 KBA9 KBA11 FRD# KBA10 FSEL# ADB7 ADB6 ADB5 ADB4 ADB3 D KBA18 KBA16 KBA15 KBA12 KBA7 KBA6 KBA5 KBA4 KBA3 KBA2 KBA1 KBA0 ADB0 ADB1 ADB2 @1U_0603_10V6K 2N7002 1N_SOT23 U18C SN74LVC32APWLE_TSSOP14 FWR# <31,34,36,43,46> PCM_PME# <31,34,36,43,46> WLAN_PME# <31,34,36,43,46> ONBD_LAN_PME# <31,34,36,43,46> MDM_PME# <31,34,36,43,46> USB20_PME# PME_EC# <31,34,36,43,46> <46> 512K8-90_PLCC32 +3VALW +3VALW +3VALW C337 U20 KBA0 KBA1 KBA2 KBA3 KBA4 KBA5 KBA6 KBA7 KBA8 KBA9 KBA10 KBA11 KBA12 KBA13 KBA14 KBA15 KBA16 KBA17 KBA18 KBA19 <46> <46> FSEL# FRD# 0.1U_0402_10V6K R357 100K_0402_5% U21 C338 ADB0 ADB1 ADB2 ADB3 ADB4 ADB5 ADB6 ADB7 0.1U_0402_10V6K RESET# R360 @100K_0402_5% FSEL# FRD# FWE# @SST39VF080-70_TSOP40 +3VALW JP22 KBA16 KBA15 KBA14 KBA13 KBA12 KBA11 KBA9 KBA8 FWE# RESET# KBA17 KBA18 KBA7 KBA6 KBA5 KBA4 KBA3 KBA2 KBA1 ADB3 ADB2 ADB1 ADB0 FRD# <46,51> EC_SMC_1 <46,51> EC_SMD_1 AT24C164-10SC_SO8 KBA19 KBA10 ADB7 ADB6 ADB5 ADB4 R358 100K_0402_5% R359 100K_0402_5% +3VALW FSEL# KBA0 @SUYIN-80065A-040G2T Compal Electronics, Inc. BIOS & EC I/O Port THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 Sheet 47 of 66 +3VS SN74LVC32APWLE_TSSOP14 R601 +3VALW +3VALW +3VALW +3VALW +3VALW VTT_PWRGD <24,27,46> 10K_0402_5% U18D R1106 R603 <56> VCORE_PWRGD 0.47U_0603_10V7K 330K_0402_5% R604 47_0603_5% SB_PWRGD <27> 330K_0603_5% U32B R605 U32C U32D C606 U32E C607 R606 SN74LVC14APWLE_TSSOP14 1M_0402_5% R1107 0.1U_0402_16V7K D 1K_0402_5% <49,55> 10K_0402_5% SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 Q111 SUSP D G S +2.5VS @2N7002_SOT23 SUSP Q110 G S @2N7002_SOT23 R608 1K_0402_5% NB_PWRGD <8> D Q52 R610 2N7002_SOT23 47K_0402_5% G S D19 D20 DAN217_SOT23 TV_OUT CONNECTOR DAN217_SOT23 +3VS JP7 <11,17,41> TV_LUMA <11,17,41> TV_CRMA <11,17,41> TV_COMPS TV_LUMA TV_CRMA TV_COMPS 75_0402_5% L4 CHB1608B121_0603 TV_LUMAL L7 @68P_0402_50V8K L8 CHB1608B121_0603 CHB1608B121_0603 TV_CRMAL TV_COMPSL SUYIN_35138S-07T1-DF R188 R189 R190 C110 C111 TV_GND 75_0402_5% R961 C113 C114 @68P_0402_50V8K @68P_0402_50V8K 75_0402_5% <41> C112 @68P_0402_50V8K C115 @68P_0402_50V8K @68P_0402_50V8K PIR BOM 92.09.01 0_0603_5% Compal Electronics, Inc. POWER GOOD & P/S2 CKT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 Sheet 48 of 66 A B C +2.5VALW to +2.5V Transfer D +2.5V to +2.5VS Transfer +1.5VSP to +1.5VS Transfer +2.5VS +2.5VALW +2.5VALW +1.5VS U56 R903 C357 R1101 C341 C358 R362 C343 C344 SI4800DY_SO8 10U_0805_6.3V6M 100K_0402_5% 100K_0402_5% 10U_0805_6.3V6M C961 68K_0402_5% SI4800DY_SO8 C960 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_10V6K Q75 2N7002 1N_SOT23 G 1 10U_0805_6.3V6M D SUSP C347 Q31 2N7002 1N_SOT23 C959 C359 SI4800DY_SO8 10U_0805_6.3V6M 0.1U_0402_10V6K D G +1.5VSP U26 U22 +12VALW SYSON# +12VALW +2.5V +12VALW 1 E D C360 C962 G 0.1U_0402_10V6K S 0.1U_0402_10V6K Q108 SUSP 2N7002 1N_SOT23 0.1U_0402_10V6K S 0.1U_0402_10V6K S L (0.5A(VGA)+0.83A(VGA_RAM)+0.14A(SB)=1.5A,60mils,) +3VALW to +3V Transfer Place close to PJP4 (6A,240mils ,Via NO.= 12) +3VALW to +3VS Transfer +3VALW +3V +3VALW +3VS U25 U23 +12VALW +12VALW +5VALW C351 R902 C354 C355 SI4800DY_SO8 10U_0805_6.3V6M 95.3K_0603_1% R363 10U_0805_6.3V6M C342 C345 SI4800DY_SO8 10U_0805_6.3V6M 95.3K_0603_1% C346 R369 10U_0805_6.3V6M 10K_0402_5% 2 2 0.1U_0402_10V6K D 0.1U_0402_10V6K D C356 SYSON# C348 SUSP Q74 2N7002 1N_SOT23 G 0.1U_0402_10V6K Q32 2N7002 1N_SOT23 G S SYSON# D 0.1U_0402_10V6K <46> S SYSON SYSON Q34 2N7002 1N_SOT23 G S +5VALW to +5V Transfer +5VALW to +5VS Transfer +5VALW +5V +5VALW U36 +5VALW +5VS U24 +12VALW +12VALW R373 10K_0402_5% C624 R904 C625 C626 SI4800DY_SO8 10U_0805_6.3V6M 47K_0402_5% R901 10U_0805_6.3V6M C350 C352 6.8K_0402_5% SI4800DY_SO8 10U_0805_6.3V6M D C844 C353 10U_0805_6.3V6M <48,55> SUSP <46,47> SUSP# SUSP D 3 0.1U_0402_10V6K D SYSON# SUSP Q76 2N7002 1N_SOT23 G 0.1U_0402_10V6K C627 0.1U_0402_10V6K Q73 2N7002 1N_SOT23 G S 3 Q38 2N7002 1N_SOT23 G S 0.1U_0402_10V6K S Discharge circuit +1.5VS +1.25VS +1.8VS R374 +2.5VS R375 470_0402_5% +3VS R376 470_0402_5% +5VS R377 470_0402_5% R378 470_0402_5% D D Q39 SUSP SUSP G D Q40 SUSP G S 2N7002 1N_SOT23 D Q41 SUSP G 470_0402_5% S 2N7002 1N_SOT23 D Q42 S 2N7002 1N_SOT23 2N7002 1N_SOT23 D Q115 SUSP G S SUSP G G S +2.5V R1094 R1095 R1102 470_0402_5% 470_0402_5% 470_0402_5% R372 470_0402_5% 470_0402_5% Q43 SUSP G +3V R1116 D 4 +5V +1.2VS_VGA S 2N7002 1N_SOT23 S D Q102 SYSON# G 2N7002 1N_SOT23 D Q103 D Q109 SYSON# 2N7002 1N_SOT23 Q36 SYSON# G S G S 2N7002 1N_SOT23 S 2N7002 1N_SOT23 4 2N7002 1N_SOT23 Compal Electronics, Inc. DC/DC Circuits THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 E Sheet 49 of 66 A B C D E Detector PJP17 PAD-OPEN 4x4m PJP18 1 ADPIN 1 PAD-OPEN 4x4m PCN1 PL1 FBM-L18-453215-900LMA90T_1812 DC_IN PD43 PC4 1000P_0402_50V7K PC2 1000P_0402_50V7K PC1 100P_0603_50V8J FOX_JDP1021 PC3 100P_0603_50V8J ADPIN SBM1040-13_POWERMITE3 PIR POWER 92.08.04 2 2 PR1 10K_0603_5% PR2 1M_0402_1% VL PD22 RB751V_SOD323 PR4 1M_0603_0.5% <27,46,53> PC10 1000P_0603_16V7K PR11 20K_0603_0.1% PACIN PACIN <52> PU1B LM393M_SO8 PZD1 ACIN Precharge detector 16.421 15.817 15.229 14.108 13.657 13.002 VL PR10 10K_0603_5% PR5 499K_0603_1% ACIN PR191 499K_0603_1% PR8 1K_0603_5% PC8 1000P_0603_16V7K VS RB751V_SOD323 PC7 0.1U_0603_16V7K PR7 10K_0603_5% PR9 15K_0603_0.5% PC9 1000P_0603_50V7K MAINPWON DC_IN DC_IN 4 PU1A LM393M_SO8 PD1 <7,51,53> PR6 82.5K_0603_0.1% PR3 432K_0603_1% PC5 0.01U_0603_50V7K <52> DCSRD 3 B+ VS 17.090 16.585 PC6 1000P_0402_50V7K Vin Detector 17.788 17.438 17.277 16.928 3 D PR192 PACIN 47K_0603_5% PQ46 G S 2N7002_SOT23 PR12 10K_0603_5% PQ47 +5VALW 100K BATT RLZ4.3B_LL34 PR14 10K_0603_5% detector 15.029 14.095 12.636 11.850 RTCVREF 3.3V DTC115EKA_SOT23 100K 4 13.187 10.860 Compal Electronics, Inc. Detector THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Size Date: Document Number Rev 1.0 Wednesday, September 24, 2003 E Sheet 50 of 66 A B C D VMB PCN2 PL2 BATT+ PC12 0.01U_0603_50V4Z PR17 VREF 1 1 S PQ1 2N7002_SOT23 2 1 2 100K_0603_1% <5,26> PC15 1000P_0603_50V7K 2 2 PR26 1K_0603_5% LM393M_SO8 PC14 1000P_0603_50V7K 2 1 PR25 D G 1 1 25.5K_0603_1% PU2A H_PROCHOT# 3 75K_0603_1% 4 VREF PR21 47K_0603_5% PC13 0.1U_0603_50V4Z P PR193 11.5K_0603_1% PR23 200K_0603_1% +3VALWP 8 ADP_I PR22 PR24 PC97 0.01U_0603_50V4Z 1 2 2 <46,52> 1 VS 1 100_0603_5% 2 SUYIN_200275MR009G130ZL 1M_0603_1% 2 2 PC11 1000P_0603_50V7K PR19 G PR18 100_0603_5% 1 2 1 1 1 TS_A EC_SMDA EC_SMCA 1 C8B BPH 853025_2P PD3 @BAS40-04_SOT23 BATT_TEMPA 2 <46> 2 EC_SMD_1 <46,47> EC_SMC_1 <46,47> 1 1 @ PD4 @BAS40-04_SOT23 PD5 @BAS40-04_SOT23 @ @ 3 2 2 3 PR27 B+ 1.5K_1206_5% DC_IN PD6 +5VALWP PH2 near main Battery CONN : BAT. thermal protection at 84 degree C Recovery at 45 degree C PR28 2 N3 1N4148_SOD80 1.5K_1206_5% PD7 PR29 VL 1 1N4148_SOD80 3 BATT+ RB751V_SOD323 1 1.5K_1206_5% 1 PD8 PR32 47K_0402_1% PR30 2.15K_0603_1% PR31 3 VS 2 PR36 16.9K_0603_1% N1 RTCVREF PR41 PU3 S-81233SGUP-T1_SOT89 200_0603_5% N2 CHGRTC 2 2 1 1 1 1 4 PC23 10U_1206_10V4Z 4 2 1 1 2 1 PC20 1U_0805_16V7K VL 150K_0402_1% PR42 150K_0402_1% 1 200_0603_5% 200_0603_5% PR40 LM393M_SO8 4 PC22 PD10 1U_0805_50V4Z RLZ16B_LL34 2 PR43 <7,50,53> 2 3.3V PR230 MAINPWON G 1 2 22K_0603_5% 2 1 EC_PWR_ON# PC21 1000P_0402_50V7K PR39 PH1 10K_TH11-3H103FT_0603_1% PC18 0.1U_0805_25V7K 2 2 0.22U_1206_25V7K 1 PC17 2 100K_0603_5% 2 1 PR38 PU2B P PQ2 TP0610T_SOT23 1 RLZ3.6B_LL34 8 CHGRTCP <45> VS 2 47_1206_5% PD9 Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED BATTERY CONN / OTP Size FROM THE CUSTODY OF THE COMPETENT DIVISION O Document Number Rev 1.0 LA-1811 Date: A B C Wednesday, September 24, 2003 D Sheet 51 of 66 A B P2 PQ3 DC_IN C PQ4 1 Iadp=0~6A 1 1 2200P_0402_50V7K 2 1 3 2 1 2200P_0603_50V7K SI4835DY_SO8 1 ACOFF# 0.1U_0805_25V7K 2 2 31.6K_0603_1% 10K_0603_1% VREF 4700P_0603_50V7K 1K_0603_1% 100K PC34 ACOFF 2 PD13 ACOFF# 1SS355_SOD323 PC36 PR59 PC37 1K_0603_1% 1500P_0603_50V7K PR60 2 DTC115EKA_SOT23 0.1U_0805_25V7K 68K_0603_5% PL4 PR62 PR63 PR61 PC38 PIR POWER 92.08.04 BATT+ 15U_SPC-1204P-150_4A_20% 1 PR65 2 1 174K_0603_1% MB3887_SSOP24 SKS30-04AT_TSMA PC42 1 2 1 PC41 2 2 100K_0603_1% 0.1U_0603_16V4Z IREF=1.1*Icharge IREF=0.73~3.3V PR66 PR67 4.2V 49.9K_0603_0.1% 150K_0603_0.1% CC=0.5~3A CV=16.8V(12 CELLS LI-ION) 3 OVP voltage : LI CHGSS 1 1 PR69 340K_0603_1% D S 2 47K_0603_5% 1 PR68 3 (BAT_OVP=0.1111 *VMB) PQ10 2 VL 1 G 1 1 100K <46> 2N7002_SOT23 PQ11 FSTCHG 2 2 PR70 499K_0603_1% PU5A 100K DTC115EKA_SOT23 3 P 8 PC43 0.1U_0603_50V4Z 3 +3VALWP VMB 4S3P : 18V--> BATT_OVP= 2.0V 3S4P/3S3P : 13.5V--> BATT_OVP= 1.5V G BATT_OVP 4 LM358A_SO8 4 1 1 4 105K_0603_0.5% 2 PR72 PC45 0.01U_0603_50V4Z 2 <46> PC40 2 PR64 IREF 2 4.7U_1210_25V6K PD14 <46> PC39 4.7U_1210_25V6K 0.02_2512_1% 1 47K_0603_1% 1500P_0603_50V7K DCSRD 1 10K_0603_1% 4.7U_1210_25V6K <50> <46> 100K PQ8 0.1U_0603_50V4Z 3 1 LXCHRG 2N7002_SOT23 S PR57 5 6 7 8 1 PC33 PC35 0.1U_0603_16V4Z 3 1 1 PC31 PR54 PR56 2 PQ9 DCSRD 2 N18 2 1 D G 2 10K_0603_5% PQ6 CHGSS PR58 3K_0603_5% PR51 2 PR52 47K_0603_1% PC32 0.1U_0603_16V4Z PACIN DC_IN 0_0603_5% 1 1 <50> PR48 PR50 ADP_I 3 PR53 150K_0603_1% @2N7002_SOT23 @ PACIN 1 AOS4407_SO8 47K_0603_5% PC30 G S @4.7U_1210_25V6K @ 2 4.7U_1210_25V6K PQ50 3 1 PC98 2 @0.1U_0603_25V7K 2 PC28 4.7U_1210_25V6K PU4 @ PC26 1 1 2 HCB4532K-800T90_1812 200K_0603_5% 1 PC29 2 0.01_2512_1%(1W) <46,51> D PQ5 PC25 1 2 PQ49 @DTC115EUA_SC70 @ 1 1 1 PR195 @47K_0402_5% 1 @ PR47 @ @ 2 @1K_0603_5% @ @0.47U_0805_25V4Z_V1 3 2 1 1 10K PC24 AOS4407_SO8 47K PQ48 PL3 1 PR44 AOS4407_SO8 @DTA144YKA_SC70 2 2 PD30 @ PR240 B++ B+ P3 PR247 15K_0603_5% @1SS355_SOD323 D Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE CHARGER Size TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION O Document Number Rev 1.0 LA-1811 Date: A B C Wednesday, September 24, 2003 D Sheet 52 of 66 A B C D B+ 1 1 PC46 1 1 4.7U_1210_25V6K 2 PL5 HCB4532K-800T90_1812 PD15 EC11FS2 PC47 PD16 DAP202U_SOT323 VS PC53 5 6 7 8 1 VL 2 2 1 1 2 PC65 47P_0402_50V8J PR82 2M_0402_1% 4 3 2 1 G S S S DL5 1 1 3 2 1 DH51 PQ15 SI4810DY_SO8 PR79 0_0402_5% 2 1 PC58 2 2 PR78 1.54K_0603_1% 2 0.47U_0603_16V7K 1 PR243 698_0402_1% 1 + 3 + PC76 2 2 PC74 2 PR100 @150U_D_6.3VM 2 SKS10-04AT_TSMA 1 PR99 47K_0402_5% 1 PD18 150U_D2_6.3VM PC75 100P_0402_50V8J 2 10.2K_0402_1% 1 1 PR96 PR95 0_0402_5% 2 2 MAX1632_SSOP28 PR94 @0_0402_5% VL +5VALWP 1 8 PC73 680P_0402_50V7K PC72 4.7U_1206_10V7K 1 2 1 2 VS 1 2 PR92 300K_0402_5% PIR POWER 92.08.04 0.47U_0603_16V7K 1 PR97 10K_0402_1% 2 1 PC68 2.5VREF 1 PC71 100P_0402_50V8J 2 PR242 620_0402_5% PR89 10K_0402_5% GND ACIN 1 2 <27,46,50> 1 PR91 1 1 SKS10-04AT_TSMA 2 2 PD17 2 150U_D2_6.3VM @150U_D_6.3VM 2 @ PC70 3.32K_0603_1% 3 + 4.7U_1210_25V6K PC57 1 2 2 PR80 0_0402_5% DH5 PIR POWER 92.08.04 + PC56 PR85 0_0402_5% PC69 1 4.7U_1210_25V6K 2 PR77 0_0402_5% 21 22 V+ 2 1 PC67 2 PR241 1.27K_0603_1% 9U_SDT-1204P-100-132A_5A_30% 5 6 7 8 S ACIN PU6 PQ13 SI4800DY D D D D 3 1 2 1 D G PR81 1.27K_0603_1% B++++ 1 1 1 2 3 4 2 2 S S S G 1 1M_0402_5% +3VALWP PQ51 PC61 2N7002_SOT23 2 PR83 DL3 1 1 47P_0402_50V8J 2 10U_SPC-1204P-100_4.5A_20% DH3 PL6 PC63 PC60 0.1U_0805_25V7K 4.7U_1210_25V6K 1 2 8 7 6 5 D D D D SI4810DY_SO8 2 0.1U_0805_25V7K 2200P_0402_50V7K PQ14 1 2 1 2 3 1SS355_SOD323 PR239 2.7K_1206_5% PD19 PR75 0_0402_5% +12VALWP PC54 4.7U_1206_10V7K 0_0402_5% 1 DH31 2 PR74 LX3 1 1 LX5 3 PQ12 SI4800DY 1 VL 1 1 PC52 2 1 4.7U_1210_25V6K PC51 2 1 2 2200P_0402_50V7K @4.7U_1210_25V6K 8 7 6 5 PT1 PC50 2 2 PR73 FLYBACK 22_1206_5% SNB 0.1U_0805_25V7K 4 BST51 3 BST31 B++++ 1 470P_0805_100V7K 2 2 PC48 10K_0402_1% 2 1 1 2 VL PC79 @0.047U_0603_16V7K PR101 2 100K_0603_1% <7,50,51> 2 1 MAINPWON PC80 0.47U_0603_16V7K 4 4 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Compal Electronics, Inc. Title 5V/3.3V/12V Size Document Number Rev 1.0 Date: Wednesday, September 24, 2003 Sheet D 53 of 66 5 4 3 2 1 PC81 2200P_0402_50V7K PL7 D B+ D +5VALWP FBM-L11-322513-151LMAT_1210 PR102 0_0603_5% PR103 0_0603_5% PD20 DAP202U_SOT323 PR104 20_0603_1% PQ16 PC88 4.7U_0805_10V4Z PQ17 SI4800DY_SO8 +2.5VALWP PU7 PC92 0.1U_0805_50V7M PL9 PR108 0_0603_5% 4.7U_SPC-1204P4R7_5.7A_20% PQ19 SI4810DY_SO8 PR107 0_0603_5% 220U_D2_4VM PC95 PR106 0_0603_5% PD23 SKS10-04AT_TSMA SKS10-04AT_TSMA PQ18 SI4810DY_SO8 VCC_MAX1845 4.7U_0805_6.3V6K PC96 + PD21 C PC94 4.7U_0805_6.3V6K 4.7U_SPC-1204P4R7_5.7A_20% PC91 PR105 0_0603_5% PL8 1U_0805_16V7K PC89 0.1U_0805_50V7M PC93 220U_D2_4VM +1.5VSP PC90 0.1U_0805_50V7M SI4800DY_SO8 PC87 4.7U_1210_25V6K 4.7U_1210_25V6K PC84 PC85 2200P_0402_50V7K PC83 4.7U_1210_25V6K C + MAX1845EEI_QSOP28 +5VALWP PIR POWER 92.04.16 0_0603_5% L The related parts will be placed close to power PU7.11 PR236 +5VALWP PR115 100K_0603_1% PR116 127K_0603_1% PR249 0_0402_5% PC99 @0_0402_5% B PJP1 PAD-OPEN 4x4m PJP16 PAD-OPEN 4x4m PJP2 PAD-OPEN 4x4m PJP3 +2.5VALW +2.5VALWP +5VALWP 0.22U_0603_16V7K PR248 VCC_MAX1845 PR117 100K_0603_1% PR114 16.9K_0603_1% B +5VALW (8A,480mils ,Via NO.=24) PAD-OPEN 4x4m PJP4 +1.25VSP +1.25VS (2A,80mils ,Via NO.= 4) +VCCVID (150mA,40mils ,Via NO.= 2) (6A,240mils ,Via NO.= 12) PJP5 PAD-OPEN 3x3m +3VALWP PJP6 +VCCVIDP PAD-OPEN 2x2m +3VALW PAD-OPEN 4x4m (6A,240mils ,Via NO.= 12) PJP8 +12VALW +12VALWP (120mA,20mils ,Via NO.= 1) PAD-OPEN 2x2m PIR POWER 92.04.16 A A PJP10 +1.8VSP +1.8VS (1.5A,120mils ,Via NO.= 6) PAD-OPEN 3x3m Compal Electronics, Inc. Title DDR POWER 2.5V & 1.5V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Size Document Number Rev 1.0 B Date: Wednesday, September 24, 2003 Sheet 1 54 of 66 A B C D E +5VS_1.2V PD24 1 1 1SS355_SOD323 PC100 22U_1210_6.3V6M PU8 PC101 0.1U_0402_10V6K PR119 0_0603_5% PQ21 SI4800DY_SO8 +1.2VS_VGA PQ23 PR122 4.64K_0603_1% PR217 0_0603_5% +3VALWP +VCCVIDP PC172 4.7U_0805_10V4Z PU27 9.09K_0603_1% PR124 PC107 + PC104 220U_D_2VM + SI4810DY_SO8 470P_0402_50V7K PC106 MAX1954 PC103 220U_D_2VM PR121 10P_0402_50V8K 180K_0603_1% 10U_0805_6.3V4Z PC102 PL10 2.2UH_SPC-1205P-2R2B_13A_30% PR202 @11.5K_0603_1% @ <5,56> VID_PWRGD <46> 2 PC171 4.7U_0805_10V4Z PR123 VR_ON MIC5258_SOT23-5 0_0603_5% 2 PR218 100K_0402_1% VGA_CORE PJP15 +5VS +5VS_1.2V M9+ 1.5V PR124//PR202 = 5.08K_0603_1% M10 1.2V PR124 = 9.09K_0603_1% PAD-OPEN 4x4m PIR POWER 92.04.16 PU16 PQ24 2SC4672_SOT89 +2.5VS PC177 0.1U_0402_10V6K PR235 0_0603_5% +2.5VS +1.8VSP +2.5VS 15_0603_5% PR127 PR126 100_0603_5% VL PC110 PU5B LM358A_SO8 +1.25VREF PC176 10U_1206_10V4Z PC179 +1.25VSP PC173 150U_D2_6.3VM PR125 5.1K_0402_5% 68P_0402_50V8J PR128 (1.25V) 5.1K_0402_5% PC184 22U_1210_6.3V6M B 3 PC178 1U_0603_10V6K E C 0.1U_0402_10V6K NE57814 PC175 0.1U_0402_10V6K + 3 PC174 0.1U_0402_10V6K PC111 560P_0402_50V7K 2.5VREF PR129 3.9K_0603_1% 10K_0603_1% PC112 0.01U_0402_16V7K PR130 D PQ25 G SUSP <48,49> S 2N7002_SOT23 4 4 Compal Electronics, Inc. Title 1.2V/1.8V/VCCVID/1.25V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Size Document Number Rev 1.0 B Date: Wednesday, September 24, 2003 Sheet E 55 of 66 PIR POWER 92.04.18 +5VS_CORE DPRSLPVR 1 FB 2 <5,55> VID_PWRGD 470P_0402_50V7K 1 3 2 S PR173 1 1 @ @0_0402_5% VCCSENSE 1k_0603_1% <5> 0_0402_5% PR245 PIR POWER 92.08.04 +CPU_B+ 0_0402_5% PC182 1000P_0402_50V7K PR244 +VCC_CORE 2 PQ40 2N7002_SOT23 2 1 1 D S G G D G 2 S D 3 OAIN+ PQ45 2N7002_SOT23 2 PC181 3 MMBT3904_SOT23 B E 1 @0_0402_5% PR139 3 CORE_REF 2N7002_SOT23 1 C PQ44 2 <57> OAIN- 1k_0603_1% 100K_0402_1% PR180 PR138 S PR171 PR167 PQ26 PU9 G 2.87K_0603_1% 30.1K_0603_1% PR137 PQ20 2N7002_SOT23 100K_0402_1% 2 2 PR227 0_0402_5% CORE_REF 1 2 100K_0402_1% 10K_0402_5% PR135 0_0402_5% PR136 PR133 <57> 1 1 SKIP# PR132 D 1 PIR POWER 92.04.16 +5VS_CORE 3 <26> PL11 FBM-L18-453215-900LMA90T_1812 SKIP# 1 CORE_REF 1 2 PC120 0.1U_0805_25V7K PC119 2200P_0402_50V7K 1 2 1 4.7U_1210_25V6K PC118 2 1 1 1 S D 2 1 3 2 1 2 2 G 2 2 OAIN- CM0_0402_5% PR163 CM+ 0_0402_5% PR166 PD29 PQ32 1 PC135 0.1U_0805_25V7K 2 PC134 2200P_0402_50V7K 1 2 4.7U_1210_25V6K 1 PC133 2 4.7U_1210_25V6K 1 PC132 2 4.7U_1210_25V6K 1 PC131 PL13 0.7U_ETQP2H0R7BFA_21A_20% +VCC_CORE 1 <57> 3 2 1 PR161 4.7U_1210_25V6K 1 PC117 2 1 1 1 2 1 2 3 2 1 PR159 OAIN+ 100K_0402_1% PQ31 2 1 2 <57> PR162 1K_0603_1% SKS30-04AT_TSMA PC141 0.47U_1206_16V7K 1. When mode control signal is high/ low, the VR will operate to Northwood/ Prescott load line. 2. VID5(12.5) should be pulled high, when the VR operates to Nothwood load line. PR160 20K_0402_1% PR164 499_0402_1% PQ43 0_0603_5% 0_0402_5% PR157 CS- PR153 499_0402_1% 2 1 2 2 0_0402_5% PC138 PR156 IRF7832_SO8 PC142 @ @100P_0603_50V8G 100P_0402_50V8J PQ30 SI7392DP_SO8 PR155 <57> IRF7832_SO8 PC140 PC180 OAIN- 100P_0603_50V8J <48> VCORE_PWRGD +VCC_CORE OAIN+ 1 MAX1546 2 1 PR15 0_0402_5% PR158 2.87K_0603_1% 3 2 1 1 2 1 1 2 PC139 DLS CS+ + 2 +CPU_B+ PC129 @4700P_0402_25V7K @ <57> <57> CM- 1 2N7002_SOT23 22.6_0402_1% 0.47U_1206_16V7K CM+ 2 PR225 PR111 3 2 1 PR224 0_0402_5% OAIN+ PR170 0_0402_5% 5 6 3 7 2 8 1 5 6 7 8 1 0_0402_5% BSTM PC128 0.22U_0402_10V4Z 5 6 7 8 VID0 PR223 PC124 PC130 100U_25V_M PD27 SKS30-04AT_TSMA H_BOOTSELECT 10.2_0402_1% 5 VID1 <5> 0_0402_5% <4> SKS30-04AT_TSMA 3 2 1 VID2 100P_0603_50V8J 0.022U_0603_50V4Z <5> PR152 @1.74K_0402_1% <5> @ PR145 0.001_2512_5% PR110 PQ29 5 6 7 8 VCCSENSE PR222 PR146 1K_0603_1% 1 2 <5> 0 _ 0 4 0 2 _ 5 % PR221 0_0402_5% PD26 IRF7832_SO8 2 VID3 2 VID4 <5> 1 <5> 1 2 PC136 470P_0402_50V7K FB @100K_0402_1% PR109 +VCCVID VID5 0 _ 0 4 0 2 _ 5 % PR220 2 2 1 1 2 PC126 1000P_0402_50V7K <5> PQ28 PC125 PR149 @0_0402_5% CHP202U_SC70 @ PR148 0_0402_5% PL12 0.7U_ETQP2H0R7BFA_21A_20% 2 1 2 PD28 0_0402_5% <5> VSSSENSE 100K_0402_1% DLM +5VS_CORE PC123 1U_0603_10V6K OAIN+ 2 12 2 1 PR147 10_0603_1% <57> PC122 IRF7832_SO8 PR246 PR154 0_0603_5% 2.2U_0805_16V4Z 270P_0402_50V7K 47K_0402_1% PC116 PR143 PR144 +5VS_CORE PQ27 SI7392DP_SO8 BSTM 0.22U_0402_10V4Z PC115 2 PR141 0_0402_5% 4.7U_1210_25V6K 5 0.22U_0603_10V7K PC114 2 PR140 100K_0402_1% 1 1 B+ CORE_REF <57> 2 150K_0402_1% 1 PR165 100K_0402_1% D PQ33 G H_BOOTSELECT=1 PRESCOTT H_BOOTSELECT=0 NORTHWOOD FB 1 PR168 9.31K_0603_1% CPUCLK_STP# <5,11,26> 3 S 2N7002_SOT23 PJP14 +5VS +5VS_CORE (120mA,20mils ,Via NO.= 1) PAD-OPEN 2x2m PIR POWER 92.04.16 Title CPU_CORE(1) Size A3 Date: Document Number LA-1811 Wednesday, September 24, 2003 Rev 1.0 Sheet 56 of 66 <56> +5VS_CORE DLM PR172 PD33 +CPU_B+ <56> CM- <56> 1 2 PC144 0.1U_0805_25V7K 2 1 PC148 2200P_0402_50V7K 1 PC147 2 4.7U_1210_25V6K 1 PC146 2 4.7U_1210_25V6K 1 2 PC145 PR181 1K_0603_1% 1 D D D D IRF7832_SO8 8 7 6 5 CM+ 2 DLS PD39 5 PR204 1K_0603_1% 1 1 2 1 2 1 PC161 2 4.7U_1210_25V6K 1 PC160 2 4.7U_1210_25V6K PC163 0.1U_0805_25V7K +VCC_CORE PC166 0.47U_1206_16V7K 2 IRF7832_SO8 D D D D S S S G 1 2 3 4 PD42 SKS30-04AT_TSMA 2200P_0402_50V7K 1 PL15 8 7 6 5 3 2 1 PQ38 1 2 3 4 CS+ IRF7832_SO8 8 7 6 5 D D D D PC169 S S S G 1 2 1 DD/ <56> MAX1980 1000P_0603_16V7K 2 13 1 2 1000P_0603_16V7K 2 PR210 49.9K_0603_1% PR206 20K_0603_1% 4.7U_1210_25V6K 2 0.7U_ETQP2H0R7BFA_21A_20% PD41 1 PC167 2200P_0402_50V7K PC159 1 0_0603_5% 0.22U_0603_16V7K PR201 0_0603_5% PC165 2 PR199 0 _ 0 6 0 3 _ 5 % PC164 PC168 200K_0603_1% 1 1 PR200 @1SS355_SOD323 PR207 PC162 PQ37 SI7392DP_SO8 2 20 TRIG 1 2 1 1 2 PR198 10_0603_1% +CPU_B+ PU11 2 2 1 PR188 0_0603_5% +VCC_CORE 0.22U_0603_16V7K 2.2U_0805_16V4Z PC158 0 _ 0 6 0 3 _1SS355_SOD323 5% PQ39 +5VS_CORE PR196 CS- <56> 2 100P_0603_50V8J S S S G 1 2 3 4 PQ36 IRF7832_SO8 S S S G PQ35 1 2 3 4 1 1000P_0603_16V7K SKIP# <56> PC170 1 3 2 1 8 7 6 5 D D D D 1 13 PC155 0.47U_1206_16V7K SKS30-04AT_TSMA MAX1980 2 1 2 1 PC156 PR189 49.9K _0402_1% PC152 2 2 1000P_0603_16V7K 2 PR183 20K_0603_1% DD/ PC153 2200P_0402_50V7K 200K_0603_1% PD36 +VCC_CORE PL14 2 1 PD35 PC154 PR184 100P_0603_50V8J 0_0603_5% 0.7U_ETQP2H0R7BFA_21A_20% 1 CORE_REF PC150 0.22U_0603_16V7K 2 PR178 0_0603_5% PC151 0.22U_0603_16V7K @1SS355_SOD323 <56> PQ34 SI7392DP_SO8 PR174 PR177 0_0603_5% 4.7U_1210_25V6K 5 PU10 TRIG 1 1 2 +VCC_CORE PR187 0_0603_5% 10_0603_1% PR176 1 2 PC149 2 2 2.2U_0805_16V4Z 1 20 0 _ 0 6 0 3 _ 5 % 1SS355_SOD323 SKIP# <56> Compal Electronics, Inc. Title +CPU_CORE(2) Size Date: Document Number Wednesday, September 24, 2003 Rev 1.0 Sheet 57 of 66 5 4 3 2 1 Version Change List ( P. I. R. List ) for Power Circuit I t e m Page# Title Date Request Owner Issue Description Solution Description Rev. D D 1 54,55, 56,57 2 56 wrong layout pad DPRSLPVR 03/25/2003 03/25/2003 03/25/2003 Compal change to correct layout pad on PU7, PU11, PU16 and PQ24 Reserve two resistors for voltage of Deep-sleeper mode Reserver PR231, PR232, PR233, PR234 for deeper-sleeper mode voltage setting Compal Reserve a jumper for power consumption measurement Add PJP14 0.2 Compal Change the netname +5VS_CORE for power consumption measurement Change Netname of +5VS_CORE 0.2 0.2 Compal PU8, PU9, PU10, 0.2 3 56 CPU VR-Cont. 4 57 CPU VR-Cont. 5 51 RTC charger 03/25/2003 Compal use two resistors for RTC charger protection Add PR230 6 55 1.2VS_VGA 03/25/2003 Compal re-layout 1.2V_VGA requested by ME 7 55 1.2VS_VGA 03/26/2003 Compal Reserve a jumper for power consumption measurement re-located both PL10 and PQ21, PQ23 as well as 1.2VS_VGA related power circitry Add PJP15 8 55 +1.25VSP 03/26/2003 Compal Change power time-sequence of 1.25VSP input power +1.5VALWP 03/27/2003 Compal Reserve Force PWM function of 1.5V/2.5V and add a PR236 for SUSP# signal 03/25/2003 0.2 wrong layout pad C C 9 54 0.2 0.2 Change VD, and VDD of PU16 from +2.5VALWP to +2.5VS; Connect PR235.2 to +2.5VS add a resistor PR235 for Stand/By pin for test Add PR237, PR238 for force PWM function control, and add PR236 for SUSP# signal 0.2 0.2 B B A A Compal Electronics, Inc. Changed-List History-1 Size Document Number Rev 1.0 LA-1811 Date: 5 4 3 2 Wednesday, September 24, 2003 1 Sheet 58 of 66 1 2 3 4 5 BHR60 from DB-1 to DB-2 STEP LA-1811 REV:0.1 -> 0.2 Modify <92.03.17.~92.03.24. > 1 2 3 4 1.Add an independent power source for VGA chip because of ATI request .92.03.17. -Add U53(SI9185),C913,R1023,C912,C914 and related net . (Modify CKT,BOM&Layout) 2.Modify the Audio related schematic for Customer request . 92.03.17. -Add Q101(2N7002);Del R948(2.2K_0402_5%);Modify R746(2.2K_0402_5%) . (Modify CKT,BOM&Layout) 3.Change the USB2.0 Controller chip from ATI to NEC and modify the net for Customer request . 92.03.18. -Add U54(NEC_uPD720101F1-EA8),R1024~R1047,R1049,R1051,R1053,R1054,C915~C929, U55(AT24C02),RP147,RP148,R102,R1059,R1062;Del RP127 . (Modify CKT,BOM&Layout) -Add R1048,R1050,R1052 . (Modify CKT&Layout) 4.Modify the Audio related schematic for Customer request . 92.03.20. -Add R1063(39K_0603_1%);Del R768(0_1206_5%) . (Modify CKT,BOM&Layout) -Change C894,C896 from 1U_0603_10V6K to 0.1U_0603_16V7K . (Modify CKT&BOM) -Change R974 from @100K_0402_5% to 100K_0402_5% . (Modify CKT&BOM) -Change R972 from 100K_0402_5% to @100K_0402_5% . (Modify CKT&BOM) -Change JP41.3 from GNDA to +5VAMP. (Modify CKT&Layout) 5.Modify the MiniPCI and BlueTooth conn related schematic for Customer request . 92.03.21. -Add R1083,R1084,R1085(@0_0402_5%) . (Modify CKT&Layout) -Change R300 from 100_0402_5% to @100_0402_5% . (Modify CKT&BOM) 6.Modify the USB2.0 related for Compal ATI/NEC Dual Layout request . 92.03.21. -Add R1069,R1070,R1072,R1073,R1074,R1076,R1077,R1078,R1092,R1093(NEC@0_0402_5%) . (Modify CKT,BOM&Layout) -Change R976,R977,R978,R979,R982,R983 from 0_0402_5% to ATI@0_0402_5% and the net . (Modify CKT,BOM&Layout) -Add R1071,R1075,R1090,R1091(ATI@0_0402_5%) . (Modify CKT&Layout) 7.Add De-coupling capacitor for AGP power pins on RC300M and VGA chip because of ATI request . 92.03.21. -Add C937~C946,C862,C863,C865~C871(0.1U_0402_10V6K) . (Modify CKT,BOM&Layout) 8. Reserve the SMBus1/2 swap Resistors for ATI request . 92.03.23. -Add RP150(0_0404_4P2R_5%) . (Modify CKT,BOM&Layout) -Add RP149(@0_0404_4P2R_5%) . (Modify CKT&Layout) 9. Add the power source +5V and +1.5VS discharge circuit for ATI request . 92.03.23. -Add R1094,R1095(470_0402_5%),Q102,Q103(2N7002 1N_SOT23) . (Modify CKT,BOM&Layout) 10. Modify the ON1 related to speed up the power sequence for ATI request . 92.03.23. -Add R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59); Del PR113(47K),PC183(0.1U) . (Modify CKT,BOM&Layout) 11. Modify power source CAP.'s value by Brian . 92.03.24. -Change C347,C360 from 0.1U_0402_10V6K to 3900P_0402_50V7K;C356,C348 from 0.01U_0402_16V7K to 2200P_0402_25V7K . (Modify CKT&BOM) -Add C956(180P_0603_50V8J) . (Modify CKT,BOM&Layout) 12. Del Via Hole on schematic for ME modify . 92.03.24. -Del H15(H_C374D295),H29(H_C197D91) . (Modify CKT,BOM&Layout) 13.Modify the MiniPCI and BlueTooth conn related for Customer request . 92.03.24. -Change R1083,R1084 from @0_0402_5% to 100_0402_5% . (Modify CKT&BOM) -Add C957(10U_0805_10V3M),C958(0.1U_0402_10V6K) . (Modify CKT,BOM&Layout) 14.Swap the USB20*P3* and USB20*P5* for Customer request . 92.03.24. A-TEST SMT BUILT -Modify R1079~R1082,JP43,R980,R981's connection . (Modify CKT&Layout) 15.Modify the schematic after rev0.1 debug by Brian . 92.03.24. -Change R1010 from @0_0603_5% to 0_0603_5%;R1011 from 0_0603_5% to @0_0603_5%; Q15 from 2SC2411K_SOT23 to @2SC2411K_SOT23;R145 from 4.7K_0402_5% to @4.7K_0402_5%; R146 from @4.7K_0402_5% to 4.7K_0402_5%;R967 from @10K_0402_5% to 10K_0402_5%; R833 from @0_0402_5% to 0_0402_5% . (Modify CKT&BOM) 16.Modify the schematic H_BOOTSELECT related by Power Team . 92.03.25. -Add Q106(2SC2411K_SC59),Q107(MMBT3904_SOT23),R1099,R1100(47K_0402_5%) . (Modify CKT,BOM&Layout) -Change R899 from 0_0402_5% to 22K_0402_5%,R900 from @0_0402_5% to 100K_0402_5% . (Modify CKT&BOM) 17.Add a power transfer circuit to fix +1.5VS leakage issue . 92.03.25. -Add U56(SI4800DY_SO8),Q108(2N7002 1N_SOT23),R1101(100K_0402_5%),C960(0.1U_0402_10V6K), C961(10U_1206_6.3V6M),C962(3900P_0402_50V7K) . (Modify CKT,BOM&Layout) 18. Modify power source Resistor and CAP.'s value for power sequence . 92.03.26. -Change C347,C360,C962 from 3900P_0402_50V7K to 0.1U_0402_10V6K;C356,C348 from 2200P_0402_25V7K to 0.1U_0402_10V6K;C627,C844 from 1000P_0402_50V7K to 0.1U_0402_10V6K . (Modify CKT&BOM) -Change R903,R362 from 100K_0402_5% to 91K_0402_5% . (Modify CKT&BOM) -Change R902,R363 from 100K_0402_5% to 95.3K_0603_1% . (Modify CKT,BOM&Layout) 19. Modify the ON1 related to speed up the power sequence for ATI request by Brian/James/CT . 92.03.26. -Del R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59) . (Modify CKT,BOM&Layout) 20. Add the power source +3VS discharge circuit by Brian . 92.03.26. -Change Q42 from @2N7002 1N_SOT23 to 2N7002 1N_SOT23 . (Modify CKT&BOM) 21. Change the Resistor's value for ATI recommend . 92.03.26. -Change R264 from 169_0603_1% to 2N7002 1N_SOT23 . (Modify CKT&BOM) 22. Correct material layout footprint and pin define . 92.03.26. -Change Y1,Y3 PCB Footprint and JP32 pin define . (Modify CKT&Layout) 23. Add the power source +3V discharge circuit for ATI request . 92.03.27. -Add R1102(470_0402_5%),Q109(2N7002 1N_SOT23) . (Modify CKT,BOM&Layout) 24. Change the power sequence related part's power source by Brian . 92.03.27. -Change U32's power source from +3VS to +3VALW . (Modify CKT&Layout) 25. Modify the power sequence related schematic for timing by Brian . 92.03.27. -Change R605 from 1M_0402_5% to @1M_0402_5%;C606 from 1U_0603_10V6K to @1U_0603_10V6K . (Modify CKT&BOM) -Add Q110(2N7002_SOT23) . (Modify CKT,BOM&Layout) 26. Modify the SPDIF related schematic for Customer request . 92.03.28. -Add R1103(0_0402_5%),C963(0.01U_0402_50V7K) . (Modify CKT,BOM&Layout) 27. Modify the NEC USB2.0 Controller Chip related schematic for Customer request . 92.03.28. -Add Y7(30MHZ_30PPM),R1105(100_0402_5%),C964(12P_0402_50V8J),C965(10P_0402_50V8K) . (Modify CKT,BOM&Layout) -Add R1104(@0_0402_5%) . (Modify CKT&Layout) -Change R1024 from 0_0402_5% to @0_0402_5% . (Modify CKT&BOM) 28. Update the material's Layout Footprint for error correction . 92.03.28. -Update JP29,JP14,SW1,SW3~SW8,JP40,Q65 . (Modify CKT&Layout) 29. Modify the related schematic after Brian Review 92.03.31. -Del R288(56_0402_5%) . (Modify CKT,BOM&Layout) 3 4 ----PLEASE SEE NEXT PAGE Compal Electronics, Inc. H/W2 EE Dept. PIR SHEET(1) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 2 30. Modify the related schematic after Layout check 92.03.31. -Modify JP16(RJ11 Conn.).5 and JP16.6 from GND to NC . (Modify CKT&Layout) 31. Update the material's Layout Footprint for error correction . 92.04.02. -Update JP40 . (Modify CKT&Layout) 32. Modify the schematic for cost down . 92.04.04. -Change to @(R1005,D79~D82,U53,C912,C913,R1023,Q98,R769,R771,) . (Modify CKT&BOM) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL 1 1 3 4 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 5 Sheet 59 of 66 1 2 BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify <92.04.08.~92.04.18. > 1.1394 Connector JP33 Pin define sequence error. 92.04.08. -Change JP33 sequence JP33.4->JP33.1, JP33.3->JP33.2, JP33.2->JP33.3, JP33.1->JP33.4. (Modify EE Circuit) 1 2.LED Circuit to Power Button(PRES)modify . 92.04.09. -Move Q66.1-R883-D56 -> Q62.1-R883-D56(PRES). (Modify EE Circuit) -Rename Q62.2 net PWR_BACK# change to PWR_ACTIVE# connect to EC U15.119. (Modify EE Circuit) 3.Add +1.2VS_VGA Discharge Circuit. 92.04.09. -Add +1.2VS_VGA Discharge Circuit(R1116 , Q115 to SUSP). (Modify EE Circuit) 4.Add 3VDDCDA & 3VDDCCL pull hing CRT_VCC circuit. 92.04.09. -Add Q13.1-R1117 to +CRT_VCC & Q14.1-R1118 to CRT_VCC. (Modify EE Circuit) 3 4 5 BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 Layout Modify <92.04.08.~92.04.18. > 1.FDD Connector JP38 PCB Footprint error. 92.04.09. -Check JP38 ACES_85201-2605_26P. (Modify Layout) 2.Power Switch U53 PCB Footprint error. 92.04.09. -Change U53 SI9185_MLP33-8->MSOP8. (Modify Layout) 1 3.Crystal Y4 PCB Footprint error. 92.04.09. -Change Y4 Y_TXC_6X1430004201_20P->KDS_DSX840GA. (Modify Layout) 4.USB Key Connector JP46 Part error. 92.04.09. -Change JP46 S W-CONN ACES 85205-0400 4P P1.25(ACES_85205-0400_4P)->S H-CONN ACES 85201-0405 4P P1.0(ACES_85201-0405_4P). (Modify Layout) 5.PCMCIA U37 NET S1_CE2# & S1_CE1# Sweep. 92.04.09. 5. Change BOM & Layout LED D57 Footprint . 92.04.15. -Change D57 HSMG-C170 to LED_12-21SYGC_S530-E1_TR8. (Modify Layout) 6. MDC(JP17) Net AC97_SData_In1/AC97_SData_In2 to AC97_Data_In. 92.04.10. -Update BOM add R326. (Modify EE Circuit) 6. Change Layout Keyboard Connector JP13 Footprint. 92.04.15. -Change JP13 ACES_85201-2402_24P -> ACES_85201_2405_24P. (Modify Layout) 7. Change NB DDR Bus Net for basic on ATI NB DDR Bus Layout rule. 92.04.11. -Add R1122(DDRA_CKE_R3), R1121(DDRA_CKE_R2). (Modify EE Circuit) -Del R399(DDRA_CS#0), R400(DDRA_CS#2). (Modify EE Circuit) 7. Change Layout FrontSideboard Connector JP42 Footprint. 92.04.15. -Change JP42 ACES_85201-1402_14P -> ACES_85201_1405_14P. (Modify Layout) 8. Check BOM USB OUVUR R893&R895 470K change to 330K. 92.04.12. 2 2 9. Add SUSP# pull Down. 92.04.14. -Add EC U15.115 to SUSP# pull Down @R1123 to GND. (Modify EE Circuit) 10. Add CPUCLK_STP# pull High Circuit. 92.04.14. -BOM Q113 -> @ , Add R1124 to Q113.1 & Q113.3. (Modify EE Circuit) -Add CPUCLK_STP# pull High @R1126 to +3VS . (Modify EE Circuit) -Add CPUCLK_STP# serial resistor R1125 to Q96.2. (Modify EE Circuit) 11. Change BOM R585 75 -> 0 & R996 33 -> 68(REFCLK1_NB). 92.04.15. 12. SIO Circuit All Power Plan +3V -> +3VS. 92.04.15. 13. Add NEC USB Corstralor U54.P19(SRMOD) pull Low. 92.04.16. -Add USB Constralor U54.P19(SRMOD) pull Low R1127 to GND. (Modify EE Circuit) -Update BOM R1046 -> @. (Modify EE Circuit) 14. Add @R1132 pull High +3V(RTS1#) & @RP153 pull High +3V(CTS1#/DSR1#/DCD1#/RI1#). 92.04.16. 3 3 15. Change BOM C364, C23, C24, C40, C798 47U -> 22U. 92.04.17. 16. Change BOM R380 430 -> 412(U27.A9/CPU_RSET#). 92.04.17. 17. Change BOM D57 HSMG-C170 -> 12-21SYGC/S530-E1, R1014 @ -> Del @. 92.04.17. 18. Change BOM C191 4.7U -> 2.2U. 92.04.17. 19. Change BOM C202,C931 10U -> 2.2U. 92.04.17. 20. Change BOM R636 100K-> @10K, R637 100K-> @10K, R665 -> @. 92.04.17. 21. Change MC_CD# - D44.3(SA_A25) -> D45.2, D44.2(SA_A22). 92.04.17. 22. Add R1135 -> VTT_PWRGD(U15.165). 92.04.18. 23. Add R1136, Q116, R1137, R1138 for pull High +3VS(CARD_LED#). 92.04.18. 24. Change BOM Q67 -> @, R884 -> @(CARD_LED#). 92.04.18. 25. Change BOM C966 22U -> 0.1U. 92.04.18. 4 4 26. Change BOM C916 -> @, C917 -> @. 92.04.18. 27. Change BOM R1019 -> @(U47.17 JS1) pull High. 92.04.18. ----PLEASE SEE NEXT PAGE 28. Change BOM R264 47 -> 137(U6.PM27 AGPTEST). 92.04.18. Compal Electronics, Inc. H/W2 EE Dept. PIR SHEET(2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 5 Sheet 60 of 66 1 2 BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify <92.04.08.~92.04.18. > 3 4 5 BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 Layout Modify <92.04.08.~92.04.18. > 29. Change U13.P1 <-> U13.P5, U14.P1 <-> U14.P5. 92.04.21. 30. Change R994.1 - AGP_DEVSEL# -> AGP_SBA1(DDC_DAT), R995.1 AGP_IRDY# -> AGP_SBA0(DDC_CLK). 92.04.21. 1 1 31. Add CLK_14M_APIC Terminte R,C @R1143 10/@C973 15P. 92.04.21. 32. Change SPR JP40 33,34 DOCKVIN -> GND , JP35,36 GND -> DOCKVIN, . 92.04.21. 33. Change BOM Q65 DTC124EK_SC59 -> MMBT3904_SOT23. 92.04.21. 34. Del @R1104, @R1089, @C953(CLK_SB_48M). 92.04.21. 35. Add @R1142 pull High(DOCK_LOUT_R). 92.04.21. 36. Add C971 & R1140 for VOLBTN+#, R1141 & C972 for VOLBTN-#, R1131 pull High +5VS, @R1139 pull High +3V. 92.04.21. 37. Add R520 @ -> Del @(JP8.AE26 COMPAT#). 92.04.23. 38. Change BOM R539, R540 61.9 -> 51.1 (JP8.L24/P1 COMP0/COMP1). 92.04.23. 39. Change BOM R553 100 -> 49.9, R558 169 -> 100. 92.04.23. 40. Change BOM R383 100 -> 49.9, R384 169 -> 100. 92.04.23. 2 2 41. Add R1001 @4.7K -> Del @, 100K pull Low(DPRSLPVR). 92.04.23. 42. Change BOM R40 @ -> Del @, R53 -> @. 92.04.23. 43. Change BOM R792 -> @, R795 @ -> Del @. 92.04.23. 44. Change BOM R230 -> @. 92.04.23. 45. EMI add R1144 for SSOUT. 92.04.24. 46. EMI change D73, D74, D75, D76 part. 92.04.24. 47. Add C974 pull Low for +NB_AGP. 92.04.24. 48. Change BOM R623 10K -> 0. 92.04.28. 49. Change BOM R622, R619 10K ->@. 92.04.28. BHR60 SI STEP LA-1811 REV:0.4 EE MEN <92.04.28. > 3 1. Change C781 SE077106M00 -> SE054106Z10. 92.04.28. 2. Change C963 -> @. 92.04.28. 3. Change C974 -> @. 92.04.28. 4. Change C742 -> (SD028000000) 0 Ohm. 92.04.28. 5. Add R771 -> (SD028470100) 4.7K Ohm. 92.04.28. 6. Add C747 -> (SE070104Z00) 0.1U. 92.04.28. 7. DEL R761,R762 92.04.28. 3 4 4 ----PLEASE SEE NEXT PAGE Compal Electronics, Inc. H/W2 EE Dept. PIR SHEET(2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 5 Sheet 61 of 66 1 2 BHR60 from SI-1 to DB(15.4") LA-1811 REV:0.4 -> 0.5 HW PIR <92.05.07.~92.05.30. > Item Fixed Issue 3 Reason for change 1 4 PAGE Prevent CPUCLK_STP# abnormal state happened 5 Modify List M.B. Ver. 5 Change R1125 from 4.7K to 12K 26 Delete R1126 29 Change R40 from 10K to 1K 0.5 2 Prevent power leakage 7 Change the power of U8 from +3VS to +3VALW 0.5 3 Power saving 7 Change the power of Fans from +5VALW to +5VS 0.5 4 ATI recommendation 8 Add C974 0.5 5 Add VGA DRAM size detect function 17 Add R1149 for 128MB VGA DRAM (un-populate for 64MB) 0.5 6 Add CS1# for Hynix 8Mx32 VGA DRAM Add Nets: NMCSA1# and NMCSB1# 0.5 7 Change M9+X VGA_CORE from +1.5VS to individual power source 21 Delete JOPEN3 0.5 8 Delete useless components 5 Delete R538 0.5 25 Delete C96 27 Delete Q114, Add R1145 1 1 18, 19, 22, 23 2 2 Update with Item23 9 Solve power leakage from CRT 25 Change R619.1 and R622.1 net from +5VS to CRT_VCC 0.5 10 Prevent DPRSLPVR abnormal state happened 26 Change R1001 from 100K to 47K, R1002 from 0 to 47K 0.5 11 Using rechargeable RTC battery for HP's request 26 Delete D66, D71 and D72; Add D91 (BAS40-04, the same as LA-1761 D30); Change BATT1 from CR1220 to ML1220 (the same as LA-1761 BATT1) 0.5 12 Prevent +5V drop while plug SPR for HP's request 41 Change JP40.3, C798.1, C800.1 and C801.1 net from +5V to USB_VCCA; Change C798 from 22u to @10u; Change C801 from 1000p to @1000p 0.5 13 Enhance brightness of blue LEDs 42, 45 Delete Q67, R883, R884, R942 and R943; Add Q117 and R1146; Change R881, R882, R885, R888, R889, R890, R925 and R1136 to 220 0.5 44 3 14 4 Solve PWR_ACTIVE LED function fail issue Change JP42.2 from BATLED_0 to BATLED_0#; Change JP42.7 from N.C. to +5VALW; Change JP42.12 from PAV_GND to PAV_LEDVCC; Change JP42.13 from PMLED_1 to PMLED_1#; Change JP42.14 from PAV_GND to +5VS; Change JP45.7 from PRES_GND to PRES_LEDVCC; Change JP45.8 from PRES_GND to +5VS 42 Change power from +3VS to +5V for PWR_ACTIVE LED (D52 and D56) 46 Add R1147 and R1148; Change U15.76 net from N.C. to PWR_ACTIVE_PRES#; Change U15.87 net from N.C. to PRES_DETECT; Change U15.119 net from PWR_ACTIVE# to PWR_ACTIVE_PAV# 3 0.5 15 Solve M10 can't power up issue 49 Change R1101 from 100K to 56K; Change R901 from 91K to 27K 0.5 16 Add discharge components 49 Add R372, R1095, R1102, Q36, Q103 and Q109 0.5 17 Material change for ME's request 44 Change JP47 from ACES_88231_0200 to MOLEX_53398_0290 (the same as LA-1761 JP2) 0.5 18 Using NEC USB2.0 to support BT for HP's request 44 Change R1082.2 net from USB3+ to USB5+; Change R1081.2 net from USB3- to USB5- 0.5 19 Increase MONO_IN voltage level 37 Change R738 from 2.4K to 10K 0.5 20 Decrease Audio AMP Gain 38 Change R971 from 100K to @100K; Change R973 from @100K to 100K 0.5 4 Compal Electronics, Inc. H/W2 EE Dept. PIR SHEET(2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 5 Sheet 62 of 66 1 2 BHR60 from SI-1 to DB(15.4") LA-1811 REV:0.4 -> 0.5 Item Fixed Issue HW PIR <92.05.07.~92.05.30. > 3 Reason for change 21 4 PAGE RTL8101L no need transistor for 3.3V to 2.5V anymore 34 REALTEK recommendation 22 5 Modify List M.B. Ver. Delete Q55, R944 and C668 0.5 Change R704 from 5.6K_0402_5% to 5.6K_0402_1% Connector Spec. change for ME's request 44 Change PCB Footprint from SUYIN_020167MR004SX01ZR_4P to suyin_020167mr004s511zu_4p for JP18, JP19 and JP20 0.5 25 Delete Q68, Q64, R619, R620, R621 and R612; Add U57, U58 and R1150 0.5 0.5 1 1 23 Solve Tr and Tf of H-sync/V-sync over Spec issue for high resolution CRT 24 Delete useless components with BOM 10 Delete R574, R1086 and C952 24 Delete R210 for UMA only 25 Add SB to control H_PROCHOT# for HP's request 26 Add Q118 and R1151 0.5 26 Add components for EMI 37 Add R1152 0.5 40 Add L65 ~ L78 40 Add L79 ~ L97 Solve DOS cold-boot shunt down issue 7 Delete C256 0.5 Decrease overshoot & undershoot 25 Add R1153 and R1154 0.6 29 Change SB GPIO0 and GPIO2 pull-down to GND 26 Delete RP126; Add R1155~ R1157 0.6 30 Only 0603 size in SAP for 5.6K_1% 34 Change component size of R704 from 0402 to 0603 0.6 31 The pin-definition of FDD conn. was error on rev0.5 M/B 40 Correct the pin-definition for JP38 0.6 32 VIA recommendation 40 Change RP119 from 1K to 330; Delete RP121; Add R? and R? 0.6 27 BHR60 from DB to SI LA-181128 REV:0.5 -> 0.6 HW PIR <92.06.20.~92.07.03. > 2 2 33 Enhance brightness of Docking LEDs 41 Change R880 from 10K to 470 0.6 34 To support wake-up function with TP 44 Change TP power from +5VS to +5V 0.6 35 Delete useless components 5 Delete R535, R536, R991 and R992 0.6 12 Delete U53, C912~C914, D79~D82, R954, R1010~R1012 and R1023 17 Delete Q15 and R251 20 Delete R1022 24 Delete R211 and R216 25 Delete C93~C95 and C930 3 4 3 26 Delete Q113, R1124 and D91; Add D93 27 Delete RP149, RP150, R1145 and Q114 29 Delete R53 37 Delete L45, R1019, Y6, R756, C740 and C741 38 Delete R1142 39 Delete RP153 and R1132 36 To improve RTC accuracy 26 Change Y1 from +/-20ppm to +/-10ppm 37 Solve Cardbus controller can't reset well issue 31 Delete R905, R941 and C906; Connect U37.C11 to G_RST# 37 Add L98 and L99 38 Add components for EMI 39 Improve Audio quality 41 Add R1161 40 Add components for ID & ME 42 Add D92 41 Modify +5V power-up timing to lead +3V 49 Change R904 from 91K to 47K 0.6 0.6 0.6 40 Add C975, C976, CP15~CP17 37 Delete C753~C756; Add R1165~R1168 and C979 38 Add R1158 and R1164; Exchange the nets of JP41.2 and JP41.3 4 0.6 Compal Electronics, Inc. H/W2 EE Dept. PIR SHEET(2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 5 Sheet 63 of 66 1 2 BHR60 from SI-1 to PV LA-1811 REV:0.6 -> 0.7 Item Fixed Issue HW PIR <92.07.03.~92.08.08. > 3 4 Reason for change 42 PAGE Correct Y1 and Y3 pin-out 5 Modify List 26 M.B. Ver. Using pin-1 and pin-2 of these crystals 0.7 46 43 ATI Product Advisory, refer to PA_218IXP0T1 Delete R65, R66, R67, R70, R72, R75, R79, R82, R86. R89, R94 and R95 44 0.7 1 1 44 Solve CD-ROM audio noise issue 30 Delete C11 0.7 45 Solve audio noise issue 37 Change R733.1 from +5VS to +5VAMP_CODEC 0.7 46 For EMI 38 Add L100, L101, L102 and L103 0.7 47 For FIR detect 39 Add R1173(no fir) and R1174(with FIR) 0.7 48 ATI recommendation 27 Change RP12 from 10K to 2.2K 0.7 46 Add R1175 49 Delete useless components 46 Delete D69 and D70 0.7 50 To support wake-up function with TP 46 Delete RP154; Add R1169, R1170, R1171 and R1172 0.7 51 Solve M10 can't power up issue 49 Delete C844 0.7 52 Improve Tr and Tf of H-sync/V-sync for high resolution CRT 25 Decrease the R,L,C value 53 Modify brightness of LEDs 42 Change R901 from 27K to 6.8K 2 2 0.7 Change Transistors from BJT to PMOS and Resisters value for Pav; Change Resisters value for Pre. 0.7 45 3 4 54 Fast power on for battery only 55 Change R306 from 100K to 470; Delete Q112 0.7 Improve contact Move JP2(CD-ROM conn.) right 0.65mm 0.7 56 Correct Caps. LED and Numl. LED placement Exchange the placement of these LEDs 0.7 57 Solve audio noise issue Cut the bridge between AGND and DGND in GND1 layer 0.7 58 Reserve for EMI 37 Add JOPEN6, JOPEN7 and JOPEN8 0.7 59 Improve USB2.0 signal quality 36 Change R1027, R1029, R1030, R1031, R1032, R1033, R1034 and R1035 to 42.2 0.7 60 Reserve VRAM detect function for ATI recommendation 17 Connect R256/R257 to ZV_DATA0/ZV_DATA1, and pull-up to +3VS 1.0 61 For EMI 38 48 36 7 24 26 28 37 41 25 Change C761~C764 to 470pF and pull-down to D-GND; Change L100~L103 to MCK2012221YZT(2A) Delete C110~C115 Change L89, R1079 & R1080 to CHB1608U301 Add C855, C856, C907 and C908 Change L11 & L12 to MBV2012301YZT Change PCI clock damping resisters to 39 ohm Add C873~C881, C980~C983; Change R60~R62 to MBV2012301YZT Delete R769 & R770; Add C984~C992 & L104 Add L105 Add C993 & C994 1.0 62 Reduce GHI# "LOW" voltage level 5 Change R527 to 300 ohm 1.0 63 Fix "Pop" sound during boot up 64 For PCBA skew reducing 45 37 42 45 Add C979 1.0 Change R885, R888, R890, R1136 and R925 to 130 1.0 65 TI recommendation 32 Add R1177 1.0 66 Solve audio L/R swap issue 37 Change R750 & R753 to 27 ohm 1.0 44 Delete R327 & C305 3 4 Compal Electronics, Inc. H/W2 EE Dept. PIR SHEET(2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1 2 3 4 Size Document Number Rev 1.0 LA-1811 Date: Wednesday, September 24, 2003 5 Sheet 64 of 66 5 4 3 2 1 Version Change List ( P. I. R. List ) for Power Circuit I t e m Page# Title Date Request Owner Issue Description Solution Description Rev. D D 1 54,55, 56,57 2 56 wrong layout pad DPRSLPVR 03/25/2003 03/25/2003 03/25/2003 Compal Compal change to correct layout pad on PU7, PU11, PU16 and PQ24 Reserve two resistors for voltage of Deep-sleeper mode Reserver PR231, PR232, PR233, PR234 for deeper-sleeper mode voltage setting Reserve a jumper for power consumption measurement Add PJP14 0.3 56 CPU VR-Cont. 4 57 CPU VR-Cont. 5 51 RTC charger 03/25/2003 Compal use two resistors for RTC charger protection Add PR230 6 55 1.2VS_VGA 03/25/2003 Compal re-layout 1.2V_VGA requested by ME 7 55 1.2VS_VGA 03/26/2003 Compal Reserve a jumper for power consumption measurement re-located both PL10 and PQ21, PQ23 as well as 1.2VS_VGA related power circitry Add PJP15 8 55 +1.25VSP 03/26/2003 Compal Change power time-sequence of 1.25VSP input power Compal 0.2 PU8, PU9, PU10, 3 03/25/2003 Compal wrong layout pad Change the netname +5VS_CORE for power consumption measurement 0.3 Change Netname of +5VS_CORE 0.3 0.3 C C 9 54 +1.5VALWP 10 54 +1.5VALWP 11 56 CPU DPRSLPVR 12 54 55 56 13 56 B 14 15 50 50 16 51 17 51 18 52 19 20 PWR JUMP CPU DPRSLPVR Vin DETECTOR Precharge Battery OTP 03/27/2003 Compal 04/16/2003 Compal 04/16/2003 Compal 04/16/2003 Compal 04/18/2003 Compal 04/30/2003 04/30/2003 Compal Compal Reserve Force PWM function of 1.5V/2.5V and add a PR236 for SUSP# signal change 1.5V time sequence 0.3 0.3 Change VD, and VDD of PU16 from +2.5VALWP to +2.5VS; Connect PR235.2 to +2.5VS add a resistor PR235 for Stand/By pin for test Add PR237, PR238 for force PWM function control, and add PR236 for SUSP# signal 0.3 0.3 Change power time-sequence of 1.5VSP input power Change DPRSLPVR design 0.4 Add two transistor PQ44,PQ45 for voltage of Deep-sleeper mode For DFX issuse 0.4 B Change power JUMP SIZE to follow new jump role to make ACIN to enable to pull low Reserve DPRSLPVR function and add a PR136 for +5VS_CORE signal Change PR8 form 10k_0603 to 0K_0603 BOM error Change PR1 from 10k_0603 to 100k_0603 Change DPRSLPVR design To change feekbeck time 0.4 0.4 0.4 0.4 Change PC20 from .22u to 1u ;PR40&PR42 from 100k to 150k; PC80 from 1u to .47u 04/30/2003 Compal 04/30/2003 Compal change component Change PU3 from S-81233SGUP-T1 Battery_OVP 04/30/2003 Compal To avoide the BATT_OVP output to oscillate Delet PC44&PR71 53 5V/3.3V/12V 04/30/2003 Compal BOM error Change PD16 from EC31Q04 53 5V/3.3V/12V 04/30/2003 Compal To improve the 3V output ripple Voltage 0.4 to S-812C33AUA-C2N 0.4 0.4 to EC11FS2 0.4 A A Delet PC77 0.4 Compal Electronics, Inc. Title Changed-List History-1 Size Document Number Rev 1.0 LA-1811 Date: 5 4 3 2 Wednesday, September 24, 2003 1 Sheet 65 of 66 5 4 3 2 1 Version Change List ( P. I. R. List ) for Power Circuit I t e m Page# Title Date Request Owner Issue Description Solution Description Rev. D D 55 1.2VS_VGA 04/30/2003 Compal BOM errors 22 50 Precharge detector 05/16/2003 Compal System can't power on by battery 23 51 21 24 56,57 25 52 26 55 Colok THROTTLING CPU_CORE(1&2) 0.4 Change PR121 from 511k to 180k;PR122 form 9.09k to 4.64k Add PR191(909K_0603),PR192(47k_0603),PRPQ46(2N7002)&PQ47(DTC115EUA_SC70) 0.5 Change PR5 from 150k to 180k 05/16/2003 05/16/2003 Compal Compal Add PR193(73.2k) ,PC97(0.01U_0603); change PR22 form 84.5K to 11.5K To modify the circuit Change the freqeuce 300k to 200k 0.5 delet PR138 ; add PR187(0_0603)&PR188(0_0603) 0.5 Add PR194(1K) ,PC98(0.1U_0603),PR195(47K),PQ48(DTA144EUA),PQ49(DTC115EUA),PQ50(2N7002),PD30(1SS355) Charger 05/16/2003 Compal To modify the charger circuit 1.2VS_VGA 05/16/2003 Compal To modify the circuit for 1.2VS_VGA &1.5VS_VGA 07/4/2003 Compal 0.5 C C 27 28 29 53 3V/5V/12V 56 CPU_CORE 56,57 CPU_CORE(1&2) 30 50 DC_in 31 52 Charger 32 53 3V/5V/12V 07/4/2003 07/4/2003 08/4/2003 08/4/2003 Compal To modify the DCR sense To improve the CPU_CORE effecient Compal For Gibson issue ,add two schottky diodes Compal To modify the Precharge circuit 33 34 56 CPU_CORE 52 Charger 08/4/2003 08/4/2003 Compal Compal Compal 0.6 Change PR158,PR180 from 2k to 3.4k 0.6 Change PL12,PL13,PL14,PL15 from TOHO to PANASONIC 0.6 add PD43(SBM1040-13_powermite3) ,PD44(SBM1040-13_powermite3) Add PD30(1SS355_SOD323) 0.7 ,PC98 (0.1U_0603),PR195(47K_0402),PQ49(DTC115EUA_SC70),PQ50(2N7002) ,de 0.7 change PR81(1.27k) ,PR78(1.54K),PR79(0_0402) ,PR85(0_0402),PC67(0.47U_0603) ,PC68(0.47U_0603);add PR241(1.24k),PR242(620 ohm),PR243(698 ohm) B 08/4/2003 0.5 Add PR81(3.4k) ,PR78(3.4K),PR79(0_0402) ,PR85(0_0402),PC67(0.1U_0603) ,PC68(0.1U_0603);delet PR86,PR88,PR90,PR93 To modify THE CPU Load line form -1.5mV/A to -2.2mV/A Compal add PR124(11.5k_0603) To solve the DCR sense for 5V OCP issue To modify THE CPU Load line form -2.2mV/A to -1.5mV/A, and senes CPU VCC and VSS To improve the charger feedback loop for charger noise issue B 0.7 Change PR158,PR180 from 3.4k to 2.2k and add PR244 (0 ohm) and PR245(0 ohm) 0.7 Change PR52 (47k_0603),PR57(1K_0603),PC36(1500P_0603) 0.7 A A Compal Electronics, Inc. Title Changed-List History-1 Size Document Number Rev 1.0 LA-1811 Date: 5 4 3 2 Wednesday, September 24, 2003 1 Sheet 66 of 66
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