Hitachi_MOS_LSI_Data_Book_LCD_Driver_LSI_Aug83 Hitachi MOS LSI Data Book LCD Driver Aug83

User Manual: Hitachi_MOS_LSI_Data_Book_LCD_Driver_LSI_Aug83

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HITACHI MoS lSI DATA BOOK·
lCD DRIVIR lSI

J

1AUG. 1983

INDEX
Page

• GENERAL INFORMATION
• QUICK REFERENCE GUIDE
• PACKAGING INFORMATION

..............................................
..............................................

1

3

• RELIABILITY AND QUALITY ASSURANCE ••••••••••••••••••••••••••••••••••

5

• RELIABILITY TEST DATA OF LCD DRIVERS •••••••••••••.•••••••••••••••••

17

• FLAT PLASTIC PACKAGE (FPP) MOUNTING METHODS ••••••••••.•••••••••••••

23

• LIQUID CRYSTAL DRIVING METHODS •••••••••••••••••••••••••••••••••••••

27

• DATA SHEET
• GENERAL PURPOSE LCD DRIVER
HD44100H (LCD DRIVER WITH 40-CHANNEL OUTPUT)
_.
• CHARACTER DISPLAY TYPE

.......................

HD43160AH (CONTROLLER WITH BUn.T-IN CHARACTER GENERATOR)

41

49

HD44780 (LCD-II) (DOT MATRIX LIQUID CRYSTAL DISPLAY CONTROLLER
& DRIVER) •••••••••••••••••••••••••••••••••••.••••••••••••••••••••••

~

65

~

HD44101H (DOT MATRIX LIQUID CRYSTAL DISPLAY CONTROLLER &
DRIVER) •••••••••••••••••••••••••••••••••••••••••••••.••••••••••••••

115

• GRAPHIC DISPLAY TYPE
HD44102CH (DOT MATRIX LIQUID CRYSTAL GRAPHIC DISPLAY
COL~

DRIVER) .....•.••..•...••........•..•...•......••...•..•.....

151

HD44103CH (DOT MATRIX LIQUID CRYSTAL GRAPHIC DISPLAY
CO~ON

DRIVER) •••••••••••••••••••••••••••••••••••••••••••••.•••.•••

HD61830 (DOT MATRIX LIQUID CRYSTAL GRAPHIC DISPLAY CONTROLLER)

173
183

• SEGMENT DISPLAY TYPE
HD61602/HD61603 (SEGMENT TYPE LCD DRIVER)

..........................

NOTICE
The example of an applied circuit or combination with other
equipment shown herein indicates characteristics and performance of a semiconductor-applied products. The Company
shall assume no responsibility for any problem involving a
patent caused when applying the descriptions in the example.

209

~

GENERAL
INFORMATION

$

HITACHI

Type
I

,

General

Type Number

1ID44100H

Process
SUDDlv Voltau
Operating
Temperature
Package
Power Dbsipation

CMOS
(V) S*l
(·C) -20--+7S"2

CMOS

CMOS

3~S*1

3~5"1

-20~+75

-20~+75

FP-60

FP-80

FP-80

(mW)

-

-

-

RAM

(bi ta)

-

51X4

64 xl

14

10

Number of
In.truc:tion
Common
Segment
LCD
Driver
Duty
8181

Dilp1ay Capability

CO\llllle n t

"1:
*2:
"3:

0.5(5V) 1. 75

(bits)

ROM IWO

-

40
Free (N)

SR type

7WU

(CO)"3
80 x8/64 ~
(CO)"3

FP-80

FP-54

FP~80

FP-60

FP-60

1. 75

10.0

2.5

4.0

30.0

672°"3
(CG)

6240
(CG)")

I-

32 x8

80)(8

200 x8

-

7360


~
(""')

-I

(T1

::0

V')

-I

n

V')

0

c:=
n
A

:::::0

rn
-n
rn
:;::0
rn
::z
n
rn

en

c:=
0

rn

PACKAGING INFORMATION
• PACKAGE INFORMATION
'the Hitachi LCD driver devices use plastic flat packages to make more compact
the equipment in which they are incorporated and provide higher density mounting by utilizing the features of their thin liquid crystal display elements •

• PACKAGE INFORMATION (UNIT: mm)

eFP-64

I

i :• J.
..J , fill iii ill III "Ii )'- ~

,
~- .

Applicable LSI

~I.!.O."
~:!.!!:! ..... ... , -:

r

HD43l60AH

eFP-60

Applicable LSI

eFP-80

Applicable LSI

HD44100H,HD44l03CH.HD61830
K ....

CH

• MARKING
.~t1ere

are two kinds of marking of the Hitachi LCD driver devices:

.,..;..th a standard type No. and the other with a ROM code.

the one

The type No. 2 with

a ROM code is applied to the HD61830 and LCD II (HD44 780) •
(1)

Standard type No.
(b)

(a)

(d)

(a)

Type No. with ROM code

(a)

(b)

D~B~fSJ

(d)

D~B~fSJ

Meaning of each mark
(a)

Hitachi mark

(b)

Lot code

(c)

Standard type No.

(d)

JAPAN mark

(e)

ROM code

RELIABILITY AND OOALITY ASSURANCE
1. VIEWS ON QUALITY AND RELIABILITY
Basic views

CJll

quality in Hitachi are to meet individual user's purchase

purpose and quality required, and to be at the satisfied quality level
sidering general marketability.

Quality required by users is specifically

clear if the contract specification is provided.
not always definite.

COll-

If not, quality required is

In both cases, efforts are made to assure the reliabi-

lity so that semiconductor devices delivered can perform their ability in
actual operating circumstances.

To realize such quality in manufacturing

process, the key points should be to establish quality control system in the
process and to enhance moral for quality.
In addition, quality required by users on semiconductor devices is going
toward higher level as performance of electronic system in the market is
going toward higher one and is expanding size and application fields.
cover the situation, actual bases Hitachi is

pe~forming

To

is as follows;

(1)

Build the reliability in design at the stage of new product development.

(2)

Build the quality at the sources of manufacturing process.

(3)

Execute the harder inspection and reliability confirmation of final
products.

(4)

Make quality level higher with field data feed back.

(5)

Cooperate with research

laborato~ies

fo~

higher quality and reliability.

With the views and methods mentioned above, utmost efforts are made for users'
requirements.

2.
2.1

RELIABILITY DESIGN OF SEMICONDUCTOR DEVICES
Reliability Targets

Reliability target is the important factor in manufacture and sales as well
as performance and price.

It is not practical to rate reliability target

with failure rate at the certain common test condition.

The reliability

target is determined corresponding to character of equ1pments taking design,
manufacture, inner process quality control, screening and test method, etc.
into consideration, and considering operating circumstances of equipments the

semiconductor device used in, reliability target of system, derating appUed
in design, operating condition, maintenance, etc.

2.2

Reliability Design

To achieve the reliability required based on

reliabi1it~

targets, timely study

and execution of design standardization, device design (including process
design, structure design), design review, reliability test are essential.
(1)

Design Standardization
Establishment of design rule, and standardization of parts, material and
process are necessary.

As for design rule, critical items on quality

and reliability are always studied at circuit design, device design,
layout design, etc.

Therefore, as long as standardized process, mate-

rial, etc. are used, reliability risk is extremely small even in new
development devices, only except for in the case special requirements
in function needed.
(2)

Device Design
It is important for device design to consider total balance of process
design, structure design, circuit 3nd layout design.

Especially in the

case new process and new material are employed, technical study is deeply
executed prior to device development.
(3)

Reliability Evaluation by Test Site
Test site is sometimes called Test Pattern.

It is useful method for

design and process reliability evaluation of IC and LSI which have complicated functions.
1.

Purposes of Test Site are as follows;
• Making clear about fundamental failure mode
• Analysis of relation between failure mode and manufacturing process
condition
• Search for failure mechanism analysis
• Establishment of QC point in manufacturing

2.

Effectiveness of evaluation by Test Site are as follows;
• Common fundamental failure mode and failure mechanism in devices can
b.e evalu~.t~A",

• Factors dominating failure mode can be picked up, and comparison can be
made with process having been experienced in field •
• Able to

anal~ze

relation between failure causes and manufacturing

factors •
• Easy to run tests.
etc.

2.3 Design Review
Design review is organized method to confirm that design satisfies the performance required including users' and design work follows the specified ways,
and whether or not technical improved items accumulated in test data of individual major fields and field data are effectively built in.

In addition,

from the standpoint of enhancement of competitive power of products, the
major purpose of design review is to ensure quality and re1:iability of the
products.

In Hitachi, design review is performed from the planning stage for

new products and even for design changed products.

Items discussed and de-

termined at design review are as follows;
(1)

Description of the products based on specified design documents.

(2)

From the standpoint of specialty of individual participants, design
documents are studied, and if unclear matter is found, sub-program of
calculation, experiments, investigation, etc. will be- carried out.

(3)

Determine contents of reliability and methods, etc. based on design
document and drawing.

(4)

Check process ability of manufacturing line to achieve design goal.

(5)

Discussion about preparation for production.

(6)

Planning and execution of sub-programs for design change proposed by
individual specialist, and for tests,

experiment~

and calculation to

confirm the design change.
(7)

Reference of past failure experiences with similar devices, confirmation
of method to prevent them, and planning and execution of test program
for confirmation of them.
/

These studies and decisions are made using

check lists made individually depending on the objects.

3.

QUALITY ASSURANCE SYS1EMGF SEMICONDUCTOR' DEVICES

3.1 Activity of Quality Assurance
"

~neral views of overall quality assurance in Hitachi are as follows;

(1)

Problems in individual process shou1d be solved in the process.

There-

fore, at final product stage, the potential failure factors have been
already removed.
(2)

Feedback of information should be made to ensure satisfied level of
process ability.

(3)

To assure reliability required as an result of the things mentioned
above is the purpose of quality assurance.

The followings are regarding device design, quality approval at mass production, inner process quality control, product inspection and reliability tests.

3.2 Quality Approval
To ensure quality and reliability required, quality approval is carried out
at trial production stage of device design and mass production stage based on
reliability design described at section 2.
The views on quality approval are as follows;
(1)

The third party performs approval objectively from the standpoint of
customers.

(2)

Fully consider past failure experiences and information from field.

(3)

Approval is needed for design change and work change.

(4)

Intensive approval is executed on parts material and process.

(5)

Study process ability and fluctuation factor, and set up control points
at mass production stage.

Considering the views mentioned above, quality approval shown in Fig. 1 is
performed.

3.3 Quality and Reliability Control at Mass Production
For quality assurance of products in mass production, quality control is
executed with organic division of functions in manufacturing, department,
quality assurance department, which are major, and other departments related.
The total function flow is shown in Fig. 2.
bel.o"i.

The main points are described

3.3.1

Quality Control oS Parts and Material

As the performance and the reliability of semiconductor devices are getting
higher, importance is increasing in quality control of material and parts,
which are crystal, lead frame, fine wire for wire bonding, package, to build
products, and materials needed in manufacturing process, which are mask pattern and chemicals.

Besides quality approval on parts and materials stated

in sect~on 3.2, the incoming inspection is, also, key in quality control of
parts and materials.

The incoming inspection is performed based on incomins

inspection specification following purchase specification and drawin!, and
sampling inspection is executed based on Mlt-STD-I05D

maink~.

The other activities of quality assurance are as follows:

Step

Contents

-

.

Target
I
Specification

I

1 Des iln Review

I
Design
Trial
Production

f--

Characteristics of Hatedal
Katerials. Parts ~
and Parts
Approval
Appearance
Dillension
Heat Resistance
Mechanical
Electrical
Others

Characteristics Approval r

Quality Approval (1)

Quality Approval (2)

Mass Production

Purpose

-

Confinaation of
Characteristics and
Reliability of Haterials
and Parts

Electrical Characteristics t-- Confinaation of Target
Spec. Hainly about
Function
Voltage
Electrical CharacteristicsL
Current
.
Tellperature
Others
Appearance. Dimension

r

I

Reliability Test
Life Test
Thet'1llal Stress
Hoisture Resistance
Hechanical Stress
Others

----l Confinaation of Quality

Reliability Test
Process Check salle as
Quality Approval (1)

I-- Confit'1ll8tion of Quality

and Reliability in Design

I

Fig~

,.

.J

r

Flow Chart
:. ,: ",,-

~

-'.

oti.ouaJ;t~.Aooro.val
".~

-.," ','.:.. •. ,",;

I.

).

and Reliability In Hass
Production

(1)

Outside Vendor Technical Information Meeting

(2)

Approval on outside vendors, and guidance of outside vendors

l3)

Physical chemical analysis and test

The typical check points of parts and materials are shown in Table 1.

3.3.2

Inner Process Quality Control

Inner process quality control is performing very important function in quality
assurance of semiconductor devices.

The following is description about con-

trol of semi-final products, final products, manufacturing facilities, measuring equipments, circumstances and sub-materials.
manufacturing process is shown in Fig. 3

The quality control in the

corresponding~to

the manufacturing

process.
(1)

Quality Control of Semi-final Products and Final Products
Potential failure factors of semiconductor devices should be removed
preventively in manufacturing process.

To achieve it, check points are

set-up in each process, and products which have potential failure factor
are not transfer to the next process.

Especially, for high reliability

semiconductor devices, manufacturing line is rigidly selected, and the
quality control in the manufacturing process is tightly executed
rigid check in each process and each lot, 100% inspection in appropriate
ways to remove failure factor caused by manufacturing fluctuation, and
execution of screening needed, such as high temperature aging and temperature cycling.

Contents of inner process quality control are as

follows;
• Condition control on.individua1 equipments and workers, and sampling
check of semifinal products.
• Proposal and carrying-out improvement of work
• Education of workers
• Maintenance and improvement of yield
• Picking-up of quality problems, and execution of counter-measures
• Transmission of information about quality
(2)

Quality Control of Manufacturing Facilities and Measuring Equipment
Equipments for manufacturing semicortductor devices have been developing
"'~""'''v...... ~l;{n!> •.,..il M".d,th"J)e.c"e~s,~ry,;;l}!&hp~r f9;rmance

devices and improvement

of production, and are important factors to determine quality and rellab1l1ty:.

In Hitachi, automatization of manufacturing equipments are

promoted to improve manufacturing fluctuation, and controls are made to
maintain proper operation of high performance equipments and periorm the
proper function.

As for maintenance inspection for quality control,

there are daily inspection which is performed daily based on specification related, and periodical inspection which is performed periodically.
At the inspection, inspection points listed in the specification are
checked one by one not to make any omission.

As for adjustment and

Qua H ty Control

Process

Haterial.
Parts

Hethod

Inspection on Haterial and
Parts for Semiconductor
Devices

Lot Sampling.
Confiraation of
quality Level

Hanufacturing Equipment.
Environment. Sub-aaterial.
Worker Control

Confiraation of
Quality Level

. Lot Sampling.
Confirmation of
Quality Level

Inner Process Quality
Control

Screening

100% Inspection on
Appearance and Electrical
Charactertstics
Products

Testing.
Insepction

Sampling Inspeciton on
Appearance and Electrical
Characteristics

I
I

I
I

IL ____ _

- -----___

Confirmation of
quality Level.
Lot Sampling

ReliabUity Test

Feedback of
Information

,------------------.,
Quality Information
I
I

I

I

Claim
I
Field Experience
I
Ceneral Quality
I
L
~
I ________________
Inforaation
I
I
I

Fig. 2 Flow Chart of Qual itY .. Control .in ,MaQul:-4c:"tur:in of several
tens to several hundreds Hz •

• MULTIPLEX DRIVING METHOD
The mUltiplex driving method is effective in reducing the number of driver
circuits, the number of connections between the circuit and the display cell,
<: .. .i

the cost vhen driving many display pic"'·.rr e.tc:ne--:t""

2 shovs the

Fj~.

comparision of the static drive with the mUltiplex drive (1/3 duty)
8-digit numeric display.

~.&

The number of liquid crystal driver circuits re-

quired is 65 for the former and 27 for the latter.
reduces the number of driver circuits.

The multiplex drive

However, the

mo~e

multiplexed, the

8f

1f

8a

8b8g

--,
I
I

Static driving
method

.. -,._,

Multiplex driving
method
(1/3 duty)

~------

-----~

Com3·------·

Fig. 2 Example of Comparision of Static Drive
~ith Multlple~ Qrive

smaller the driving voltage tolerance.

Thus. there are limits- to extent of

-

multiplexing.
.~

.

'!he.reo,,8re two_types. of. multiplex. drive waveforms:

fdiib!(1wn·\\~~'-Ftcg#:·)\tI"('·~!·~-:us~if~fo~, a~tlon
alternation in between 2 frames.

A type and B type.

in 1 frame.

A type.

B type 1s used for

B type has better display quality than A

type in high multiplex drive.

f1

rf1• rIlL
··
Segme!\t~
.·
·· ·•
CODDDon 1LJ~;LJn
n

CODDDon:

•

1-----4

Segment ...

-

Common-segment-.~~~~~r+~~

I

•
Common-segment

Ffg. 3 A Type Waveforms

(1/3

dut~,

1/3 bias)

Fig. 4 B Type Waveforms

(1/3 duty, 1/3 bias)

el/2 Bias, 1/2 Duty Drive
In the 1/2 duty drive, 1 driver circuit drives 2 segments.

Fig. 5 shows

an example of the connection in displaying '4' on the liquid crystal
display of 7-segment type, and the output waveforms.

,

Liquid Crystal Display
and Terminal Connection
COMo

~...:.----

COM,

COM,
- -...---COMo

SEG"~

c:

(!)

w

(I)

-+
c:

(!)
W
(I)

N

M

(!)
W


C\I

v.

~

>C\I

Segment 1

.-I

P-

.,...
C/)

"0
.-I

C\I
4.J
C/)

>~
u

Between segment
and common 1
(Display OFF)

"0
.,...
:l
.,...0"

1 frame

....:I

Be tween segment
and common 2
(Display ON)

Fig. 9

Example of Waveforms in 1/8 Duty Drive {A type}
(Example of HD44l00H)

el/5 Bias. 1/16 Duty Drive

Liquid Crystal Display

I

Veeo
VI
VI
COMI - V

••••

v.

0-

COM.~
COM,
COM.
COM,
COM.

COM",

,,

COMa
COMIZ
COM"
COM..

Vee
VI
V.
COM, V,
V.
V,

-DOOOII--DOOIIO-

--DOIIOO-

--a.ooo-

COM.

I

,
I
I

I

,

[

r

,

I

I

Vee
\0 1

SEG,
-~

----

I

-~~-------

COM,

I

18

II III II! L~

,

V,

COM.-a.oo.CON.-a.oo.-

I • I , I-------t I I

I

I!
!f I II~ !qI I

,

COM,

1

•

\'
V,

V.

SEQ. V,
V.
V,

III

!II

V.
V,
Vee
V,

I

I

,I
,

I

IIII!f II

II

f f

-----

I
I

,
I

VU:D

I

,

I

I

I

COM,- SEa.
V, = Vet: - Yo. VL<:D (Selected IIavefora)_ ~1 Vu:o

I

I I f I L
I "' . 1 J I

I
I

-

1 11
1

I

I

I
I

V.=Vee -~VL<:D
-~ VL<:D

VI

= Vt:e

V.

= Vee -

~ VLCD

-Vu:o

V. = Vee - VLCD
VLCO

-f---------------------T------,

I

I

COM. -SEG,
(Non-selected II.vefond- ~Vu:o

I

I
J

I

I

1
I

r

1 f

I I .,

-

r1

I

TT,

I
I

I

I

I

I
=;I~-========~~:;~=======.~I=======

- VLCD!

Fig. 10

1 frame

Example of Waveforms in 1/16 Duty Drive (A type)
(Example of LCD-II)

• 1/5 Bias, 1/32 Duty Drive

COM.
COM %
COM,

V2
Vs

-_.

I
I

,
I

~0M4

J
I

.,

COMs
COM,
COM,
COM,
COM,
COMlo
COM II
COMu
COM 13
COMu-.."" _~
COMls
.-.r-,,....
COMI6
COM 17
COM I'
COMI'
COM20
COM21
COMzz
COMu
COMz.
COMzs
COMz.
COMZ1
COMu
COMzt
COMlO
COMll
COMu

COMI

COMz

Vl
V,
VI
Vz
Vs
V.
Vl

,I

.
I

_..

I

•

·

1

L

I

V,

I

VI
Vz
Vs

,

~: ~
V,

SEGI

VI
Vz
Vs
V.
V3
V,
VI

SEG.

_._:=1
1

I

I

I

-- ·

L

I

I
I

I
I
I

..-

VU"U

·•
I

._.

I

~vu:u

COMI -SECI - ~VU:I I

(Non-selected waveform)

I

·J·
I

I

,
I
I

·

-%VlCl, 1
-

I

,

_.-

1
L

VL\:u-r-----~!-------­

Vu:., -~----,I---..-------

~VI.l"II'-""---­

COM.-SEGa

(Selected waveform)

-

~VlCJ)'-~f---->--L--

-

VlCJ)-t-'-----;..-.------l~l-

1 frame

Fig. n

of Wavefdnns in 1/32 Outy Drive
~Example of H044102CH.H04410~CH)

E~ample

• POWER SUPPlY CIRCUIT FOR LIQUID CRYSTAL DRIVE
Table 1 sh9wS the relationship between the number of driving biases and
displa, duty ratios.

Table 1 Relationship between the Number of Dispaly Duties Ratio
and the Number"of Driving Biases
Display
duty
ratio
Number of
driving
biases

Static 1/2

2

1/3

1/4

1/1

4
3
'1/2 (1/3 bias)
bias.

1/8 1/11 1/12 1/14 1/16 1/24 1/32 1/64

6
(1/5 bias)

5
(1/4 bias)

eDrive in Resistance Dividing
A driving bias is generally generated in re~istance dividing.
Vee(+5 V)

Vcc( +5V)
Vee

Veelr---'" ---....R
VI ,,"---'"

>

,?R

VI

~R

V2
R

Vleo

V3
R

V...

R
Vs

-5V

(a)

~~ R
-5V

1/4 Bias (1/8, 1/11 duty)

(b)

1/5 Bias (1/16 duty)

Fig. 12 Example of Driving Voltage Supply
The setting of resistance value is determined by considering of operation
margine and power consumption.

Since the liquid crystal display load is

capacitive, the drive waveform itself is distorted due to charge/discharge current when the liquid crystal display drive waveform is applied.
To reduce distortion, the resistance value should be decreased but the
power consumption increases because of the increase of the current through
the dividing resistors.

Since larger liquid crystal display panels have

larger capacitance, the resistance value must be decreased.

Vee( +5V)

Common/segment selected high leve

Vee

C
R
V. ~----~--~ Common non~selectedhigh level
R
C
T: Segment
r'.C'n-selected high level
V2

C

Vl ~----~---t Segment non-selected- low level
C

V. ~----~--~ Common non-selected low level
C

Vs ~----~--~ Common/segment selected low level
VR
For contrast adjustment
-5V

Large C and R cause
a level shift.

Fig .13

Example of Capacitor Connection for Improvement of
Liquid Crystal Display Drive Wavefonn Distortion
(1/5 bias) (Example of LCD-II)

It is efficient to connect a capacitor to the resistors in parallel as
shown in Fig. 13 in

orde~

the effect is limited.

to improve charge/discharge distortion.

However,

Even if it is attempted to reduce the power con-

sumption with a large resistor and improve waveform distortion with a
large capacitor, a level shift occurs and the operating margine is not
improved.
Since the liquid crystal display load is of matrix configuration, the path
of the

c~arge/discharge

current through the load is complicated.

it varies depending on display condition.

Moreover,

Thus, a value of resistance

cannot be simply determined from the load capacitance of liquid crystal
display.

It must be experimentally determined according to the demand for

the power consumption of the equipment in which the li'quid crystal display

;hI's incorporated.

Generally. R is lkO to lOkO, and VR is 5kQ to 50kO.
O.l~F

A capacitor of

No capacitor is used.

is usually used if necessary •

• Drive by Operational Amplifier"
In graphic display, the size of liqtdd crystal becomes larger and the
display. duty ratio becomes smaller. then the stability of liquid crystal
drive level is more important than small display system.
Since the liquid crystal for graphic display is large and has many pictul'e
elements. the load capacity becomes large.

Tbe high impedance of the

power supply for liquid crystal drive produces distortion in the drive
waveiorms, and deteriorates display quality..

For this reason, the liquid

crystal drive level should be low impedance with operational amplifiers.
Fig. 14 shows an example of operational amplifier

confi.guratio~.

Common/segment selected high level

(+5V)'Vcc
R

Common non-selected high level

R

Segment non-selected high level

R

Segment non-selected low level

R

Common selected low level
Common/segment selected low level

R
VR

For liquid crystal drive logic circuits

(-5V) VEE

-t>Fig. 14

Voltage follower

~y

operational amplifier

Drive by Operational Ampl'ifier (1/5 bias)

No load current flows through the dividing resistors because of the high
input impedance of operational amplifier.

A high resistance of R = lOkQ

and VR" 50kO can be used.

eGeneration of Liquid Crystal Drive Level in lSI
The power supply circuit for liquid crystal drive level may be incorporated
in the LSI such as for portable calculator with liquid crystal display..
HD6l602, H061603 for small- display system has built-in power supply circuit
for liquid crystal drive level.

• Precaution on Power Supply Circuit
The LCD driver LSI has two types of power supplies:

the one for

circuits and the other for liquid crystal display drive circuit.
~~~er

supply system is

~o~D!icated

logic~

The

because of several liquid crystal

:ive levels.
For this reason, in the power supply design, take care not to deviate
from the voltage range assured 1n the maximum rating at the rise of power
supply and from the potential sequence of each power supply.

If the input

terminal level is indefinite, through current flows and the power

cons~

~­

tion increases because of the use of CMOS process in the LCD driver.
Simultaneously, the potential sequence of each power supply becomes wrong,
and a latch-up phenomenon may be caused.

DATA SHEETS

~HITACHI

HD44100H (LCD DRIVER
WITH LIO-CHANNEL OUTPUTS)

The HD44100H has two sets of 20-bit bidirectional shift

~egisters,

20 data latch flip

flops and 20 liquid crystal display driver
circuits.

It receives serial display data

from a display control LSI, converts it into
parallel data and supplies liquid crystal
display waveforms to the liquid crystal.
The H044l00H is a liquid crystal display
driver with high generalizability, which
can drive a static drive liquid crystal and

(FP- 60)

PIN ARRANGEMENT

a dynamic drive liquid crystal, and can be
applied to a common driver or segment

~

:;

~

;:; II

»»>

:; .. ::;" k

»»»

,

driver .

• FEATURES
SHL.

• Liquid crystal display driver with serial/
parallel conversion function
• Serial transfer facilitates board design

DR.
DL.
9 GNO

• Capable of interfacing to liquid crystal

eL.

display controllers: HD43l60AH, LCTC
(HD61830), H044101H, LCD U(HD44780),
LCDnr (HD44790).

(Top View)

• Internal liquid crystal display driver
... 40 drivers
• Internal serial/parallel conversion
circuits
20-bit shift register x 2
20-bit data latch x 2
• Display bias:

Static

~

1/5

• Power supply
Internal logic:

+SV

Liquid crystal display driver circuit:

-SV

separation of internai logic from liquid crystal display driver
circuit allows applicable controllers and liquid crystal >:ypes ("
increase.
• CMOS process
• 60-pin flat plastic package

II BLOCK DIAGRAM

'1'1

VI. V2
Vl. V4

'1'20

--~____________________r--L--7;~~~~~--------~--'

LCD Drivers

Latch signal
CLI

Data
OL2'--r--r-II--r---t-:-~~
FCS---r--~~--+---1

M

__~~~~~~~~______~r-J
______________+-_
~

Shift
direction

circuit

--+-~i'---~\

LCD Drivers
ve --r----------------~--r_----~~~--~--------~~

VI. V2

VS.

'1'21

'1'40

DR2

SHU

.ABSOLUTE MAXIMUM RATINGS
Item

S:ymbo1

Logic
LCD drivers

Value

Unit

Vee

- 0.3 to + 7.0

V *1

VEE *2

Vee - 13.5 to Vee + 0.3

V

Input vo1.tage

VT1

Input voltage

VT2 *3

- 0.3 to Vee + 0.3
VCC +0.3 to VEE-0.3

V *1
V

Operating temperature

Topr

- 20 to + 15

°c

Tstg

-55 to +125

-.-

Supply
voltage

Storage temperature

.-.~

°e

*1

All voltage values are referenced to GND.

*2

Connect a protection resistor of 2200! 5% to VEE
power supply in series.

*3

Applies to Vl to V6

.ELECTRICAL CHARACTERISTICS
(VCC = 5V ! 10%, VEE = -5V ! 10%, GNO = OV, Ta = -20 to + 75°C)
.. '::.

Item
Input voltage

Output voltage

.Symbol

Applicable ter.lnal

VIII

el.l.CI.1, DI.l,III.2, ORl, DR2,

VIL

H,SIILl,SIIL2,Fe5

VOII

DI.I,DI.2,OR1,DR2

VOL
VI-V J voltllge
descending

VDI
VD2

.

Tellt condition

-

-

VI leakage
current

IVI.

*3

-I

VI - YJ

Vln • Vee to Vt;~
feL2 - 400kll&

lEE

feLl·IIlII&

-

- 5.0

.

-10.0

-

-

(Vi-t to 6. jet to 40) equivalent circuit

Vi _ .

'-

~~
Power
switch

..
--R.....
· 2....- - ' - - . Yj
-.-..;

Data
l'wltch

V

Vee - 0.4

ION - 0.05111A for each YI

*2

V

0.) Vee

1011 • -0. 4./\

'I L

ICC

Unit

Vee

10L - +0.4./\

el.l,eL2 ,DI.1 .DL2, DRl,OU,
Vln-O to Vee
H, Sill. 1 ,5111.2 ,FeS ,Ne

rower sIIrl,ly
current

ilia x

-

-

(nput leakage
current

1----.

typ

0

10N·0.IIIII\ for one of VI
*)

.In
D.7 Vee

RI- tkn typo
1l2-tOkn typo

*2

Input/output current Is excluded; when Input Is at the Inurllledlate level
with (;H05. excel',"ve current flows through the Input r.lrcult to the power
Ru!'ply. To avoid this, Input level IIIUltt be fhed at high or low.

*)

Output YI to Y40 open.

-

-

-

V

0.4

V

1.1

V

1.5

V

5.0

uA

10.0

uA

1.0

IlIA

10

uA

·TJMING CHARACTERISTICS
(VCC =5V ! 10%. VEE = -5
r tern

!

101.. GNO

=OV, Ta = -20 to + 7'5°C)

Symbol Applicable terminal

Test

condition

--~-~-----

O)ata :ih i ft frequency

-

fCI.

CL2

High level

tCWH

CLl,CL2

Low level

tCWL

CL2

Data set-up time

tSU

DLl,DL2,DRl.DR2.FLM

Clock set-up time

tSL

CLl.CL2

Clock set-up time

tLS

Data delay time
Clock rise/fall time

Clock
width

min

;"'0
..800

typ

max

- 400
_-L-=-.
-

. Un(t
kHz

"ns

300

-

-

ns

(CL2~CLl)

SOO

-

-

ns

CLl.CL2

(CLl~L2)

SOO

-

-

ns

tpd

DL1.DL2.DRl,DR2

CL

-

-

SOO

ns

tct

CLI,CL2

-

-

200

ns

=

IS pF

>

CL2 -

~-------tcWL------~

t ct

Data in
(OL1. OL2. OR1. OR2)

tsu~---------tSL-----~~

~-------tLS------~

Data out
_ _ _ _oJ
COL 1. OL2. DR 1. OR2)

CLl
tct

~------tcWH------~

FLM

Fig. 1 Timing Waveform

• TERMINAL FUNeT ION

Table 1 Fucntional Description of Terminals

I"u.b.,

SI ~nal
na_

lofIl"..

"CC

I

~S[l

lnputl
Output

Yj-\'zc

Pow~r

supply

Pover supply for

I

Pov~r

supply

OV

\',.

Po_r supply for liquid crystal display drive
Liquid crystal driver output (eh.nnel 1)

20

Output I Liquid crystal

~

\'2

2

Input

\' 10

\' ,

2

Input

\"! •

V,

2

Input

I

Power supply

Po_r supply

I

I

I

SHtl

I

Uquic! crystal

Pover supply

I

iI vce or C;I\D

Input

Selection of ch.nne} 1 shi ft re@ister in the shi ft direction

I

.

I

I

I
I

! Controller
i or HD44100H

OLl, DRl

2

Inputl
output

OL2, DR

2

Input/l Controller
output! or H044100H

~

I

Input

etl

I

Input

1

I
I

I Controller

I
!
!

Input

Vce

eND

[OUT

J I"

Fes leve I

I
I

I

Data input/output of ch.nne 1 I shift register
Data input/output of channel 2 shift register

for channel I (---- > *1
for channel 2 ..hen FeS is eND.

ChannE'1

i latch
el2

Vce

II

OUT

HadE' select signal of channe 1 2. rcs Signal exchanges the
latch signal and the shift signal of channel 2 and inverts
M for channel :1 •

\·CC or eND

I

l

[IN

latch signal for channel 1 <'I->
*1
This is used for channel 2 when res is GNO.

I

1

I

I

I Controller

o.

I

OUT

si@nal
I Shilt
This is used

Controller

I
rcs

II'

GI\O

DRI

Alternated signal for liquid crystal driver output

I

Input

lOUT

r I SH12 I 012 r DR:! t

I

C1.2

I Oll

I"
Selection of channel 2 shift register in the shift direction

or elo1>

I!

"

SHll
Vce

I

I VCC

Input

output (Channel 2)

Pover supply for liquid crystal dispdy drive
(Hon-aelect'level Cor channel 1)
, Pow~r supp})' for liquid crystal display drive
(Hon-.elect level for channel 2)
i

j

I

drlv~r

Power supply for liquid crystal display drive (Se lec t level)

I

I
SIll2

c1 rcuit

Po...,r supply
Output

\"11

lo~ie.l

Liquid crystal

20

\"

..

Funet ion

I

I

\"[[

to

Conn~et~d

GND

Signal

-

.~

L

eLl

i

.

J M polarity

~

Shi Ct signal
el!

.-

~

el~

'-

.
i

H

For co.-on d rive

I

H

For segment drive

I

*1

*1

*2

*1

Sand -'- indicate the latches at rise and Call times respectively.

*2

The output level relationship between channell an' channel
on the FeS Signal level is as follows:

Fes
Vee

Data
til"
(Select)

("I")

"0"
(~on-se

Ct>u
("0")

1ec t)
"I"
(Select)

"0"
(';on-sclect)

H

I

"1"
"0"
"1 "
"0 '
"1"
"0"

III

II

"0'

I

(\"

~

Output level
Yzo) [ 2 ("2'
V:
I

.

I

\' j

!

V;

VI

\.

J

Vf

V.
VI

\'1

I

Y.~)

\'~

V,

I

\'.1.

I

\'.

[

\';

\'.
\'

,

"I" and "0" indicate a hitth and 10'" level6, respectively.

Purpose

I

~

based

• APPLI CAT! ONS

• Segment Dri ver
When the HD44l00H is used as a segment driver, the FCS is set to GND to
':.~dnsfer

display data in the dOling sho . . :n in Fig. 2.

In this caSL. Lc_"

of channel I and channel 2 are shift data at the fall of CL2 and latch it
at the fall of CLI.

V3 and Vs ,

V~

and V6 of power supply for liquid

crystal display driver are short-circuited.
7

2

8

4

3

5

6

8

7

2

( FlM)
M
Cll
Output of
latch
(Y 1 ......Y 40)

--------- --- --~

Cll

------

_____________________________

~rl~

_______

Shift
Cl2
Dll / DR 1
Dl2 / DR2 _.___....J

,---.,,.---..,.- ' - -_ _, \ . - . _ . . I \ - _ - A ._

- ---

____ _

Fig. 2 Segment Data Waveforms (A type waveforms

1/8 duty)

• COIlInon Driver
When channel 1 is used as a segment driver and channel 2 as a common
driver.

When channel 2 of HD44100H is used as a conunon driver, the FCS is

set to VCC level to transfer display data in the timing shown in Fig. 3.
In this case, channel 2 shifts data at the rise of CLI and latches it at
,;. -he

l'l'C

~_)f

CL2.

ChaMel I has the same data as Fig. 2.
8

r--,-j

2

3

4

5

6

1

8

1

2

'Ll'~-,------------------------~Ll~------

Ol:P/OR:p.IFlMI
------~,-

, Shlft

ClI

L ~___ ~

,/

I~:~.
Y22

"
:

( Y 331

:

Enlarged \
view
"
Dl2 / DR2lFlMI -

L

II
Se lec t

r--l

L_-'_

IY391:

.)28

l

r-l

Select

Select

l

L 1 L L
~

Non-select

Se lec t

Non-select

r--r

N;n:selecl:-------.---,
~

L

i

Select

!

Select

M'

ClI
CL2

Fig. 3 Common Data Waveforms (A type waveforms of channel 2, 1/8 duty)

When both of channel 1 and channel 2 of H044100H are used a common driver-,.
the FCS is set to GND and the signals (CLI, CL2, FLM} from the controller
are connected to shown in following figure.
In this case, connection of power supply for liquid crystal display dOt:"
f.-::

di fferent from segment driver, so re fer too following figure.
Select level of segment and common
Non-select level of segment
Non-select level of common

J

en - N
eL2 ~ i i
eL1
en en

eL1

Contr oller

eL2
FlM

[

(HD431 60AH)

...
!~

OL1
OR1
Ol2
OR2

v,-

40

Common
driver

LCD

»»»

lv, -..

-.

H04410()i

o

tIS
Ul

~---

(J

>.

....tIS
='

(l,

H044100H

Segment
driver

4-4

Vz
V.
_ V.

.. ..>.
» >.. »

v,
v•

!

lI

I

1

VI-to

I

Segment
driver

- ..

fit

....

_

> > > »>

!

.1

I

.1

1
..I.

VI

• Sta tic Dr i ve
When the HD44l00H is used in the static drive, data is transferred at the
fall of CL2 and latched at the fall of CLI.

The frequency of CLI becomes

the frame frequency of liquid crystal display driver.

The signal that has

the frequency twice that of CLI synchronized at the fall of CLI is input
into terminal M.

The power supply for liquid crystal display driver is

used by short-circuiting VI' V~ and V6 , and V2 , V3 and Vs.
One of liquid crystal display driver output terminals can be used for a
common output.

In this case, the FCS is set to GND and data is trans ferre,

so that "0" can be always latched in "the latch corresponding to the l~id
crystal display driver output terminal used as the common output.

IA.ie

latch signal corresponding to the ~~gment output is "1", the. segments of
LCD- light.

They also light with COmmon side"

"I'" and segment side iIO".

HD43160AW (CONTROLL~R WITH
BU ILT- INCHARACTER GEftERATOR)
DISPLAY CONTROLLER AND CHARACTER GENERATOR
FOR DOT MATRIX LIQUID CRYSTAL DISPLAY SYSTEM
the HD,43160AHrec~ives character data written
in the ASCU code or JIS code from microcomputer and stores them in its RAM which has
80 words

capacit~.

The HD4316GAH converts these data into serial
character pattern, then transfers them to
LCD drivers.
It also generates other signals for LCD.

(FP-54)

• CHARAC1ER DISPLAY
• Alphanumeric character; A - Z" a - z, @, II, %, &, etc.
• Japanese Character (katakana)
• 160 characters

b~

internal character generator (ROM).

(Max 256 characters by external ROM)
.'

• NUMBER OF CHARACTERS
• 4, 8, 16, 24, }2, 40, 64 or 80 characters in 1 or 2 lines

• FRONT
• 5 x 7 + Cursor or 5 x 11 + Cursor

• OTHER FUNCTION CONTROLLED BY MICROCOMPUTER
• Display clear
• Cursor ON/OFF
• Cursor position preset (Character position)
• Cursor re turn

• BLOCK DIAGRAM

CSO
CSJ
';S 2

CNO

J.4

~,

Oll)
~~

CS3

DL-'

CN1~

c, fCp-400klll.
(~xter""l

clock)

-

Input/output ~urrent ill excluded. When input (II at the InterMediate level with CMOS,
current flowlI through the input circuit to the power Bupply. To avoid this,
input leve) MUllt be fixed at high or low, but CSO - eSl, RSO, R/W, 080 - 0117 are excluded •

~xce8111ve

• PIN ARRANGEMENT
I'Jn
N....

Power Slip.
OSC.
eND (-)

ruwer .. up.
OSC.

Puwer 811p.
OSC.

Output

Pin
Nu.
19

0

)7

Dill

2

X4

20

fl.H

)8

0114

)

Xl

21

4

X2

22

OSCl
OSC2

1

Input

S

Xl

2)

6

XO

24

Input

Output

.A

ItST

Pin
No.

19

OBS

40

DII6

41

DII7

42

ROHS

7

N.C.

2S

TEST

41

OS

II

N.C.

26

E

44

04

9

N.C.

27

4S

0]

R/W

46

02

RSO

47

01

10

CUltS

11

.0N°I"S

28
29

-

VeC<·)

Output

Input

DBl

l:l

OLN

)0

eso

48

y)

II

CNO

11

CSl

49

Y2

14

CNI
CN2

)2

eS2
CS)

50

))

51

Yl
yO

52

X7

n

X6

n
16

CI.Z

)4

DISO

J7

CLl

)S

I>Bl

H

)6

18

0112

.

54
~.,~~

..

~,

.'"

."XS.... .. ",
"..-

.'

• PIN FUNCTION
Pin
name

Number

Connected to

of

lines

I/O

Function

;,-

Vce
GND

~

+5V ± 107. Power supply

2

Power supply

CNO
eNl
eN2

_ 3 ---

GND or VCC

CURS

1

GND or Vee

I

DLN

1

GND or Vee

I

Display line number select.
Vee: 2 lines. '
GND: 1 line.

FNTS

1

GND or Vee

I

Font select.
Vee: j xlI + Cue :;,j;.
GND: 5 x 7 + Cursor.

RST

1

-- Vee

I

Only for test.

TEST

1

GND

I

Only for test.

E

1

MPU

I

Strobe signal.
Write mode: The HD43160AH latches the data on
DBO - DB7 at the falling edge of
this signal.
Read mode: Busy /Ready signal is active on DB7
while this signal is 'H' •

R/W

1

MPU

I

Read/Write signal
L: HD43l60AH gets the data from MPU.
H: MPU gets the Busy/Ready signal from
HD43160AH.

eso
eSl
eS2
eS3

4

MPU

I

Chip select .
When all of eso - eS3 are 'H' , HD43160AH is
selected.

RSO

1

MPU

I

DBO

8

MPU

0

1

HD44J:00H

eL2

1

HD44100H

0

Dot data shift signal for LCD drivers.

CLl

1

"nf. (,. .J'0(\).I., ._.»!_

('I,

n ...

I

I Tot;,,~ :: ,,;,,:;, Y' 1

~

I

"'umber select.
4
. ,-'.
10 L:" -; 32- "'40- 64 80
eNO GND Vee GND Vee GND Vee GND Vee
eNl GND GND Vee Vee GND GND Vee Vee
eN2 GND GND 'GND GND Vee Vee Vee Vee
Cursor select
Vee: 5 dots. •••••
GND: 1 dot.
':" h::a - :t:::-~;'~ 7.. ~ 7:, ~

;~

."j

I

DB7

,

•

,

Normally Vee
Normally GND

Register select.
HD43l60AH has 2 registers. One is for
Character code and another is for instruction
code. Each register latches the data on
DBO - DB7 at the falling edge of 'E', when
eso - eS3 are 'H' and R/w is 'L' •
H; Character code register is selected.
L; Instruction code register is selected.
I
Data bus.
I/O Inputs for Character code and Instruction
(DB7) code from MPU.
Output for Busy/Ready flag (DB7).
0

Serial dot data of characters for LCD drivers

l-i<

~

-

..'l _':

:"j'

..-#.1. _.

;'", •

"""'(h"..,-~·

.,

.-~~.

c,d.}

;

~

'. ,"';/.~,

".'

".

<

M

1

H044100H

o

Alternate signal for LCD drivers.

FLM

1

H044100H

Signal for common plates scanning.

XO

8

ROM

o
o

Character code outputs for External character
(for Ext ROM)
, " ""'- ~/,.", ftSf.t"'" '"
• 'If' •
xo; Ls'i{~ ,ex: character 'A'

,!",,;~:;,g.nera~~r.

X7

MSii1

o [If 0 rO I 0 1.0 0

YO

4

ROM

o

Yl
Y2
Y3

Lsi1
1

'l'='H'

r ·O· .. ·L·

Character row code for External character
generator.
,---5
+ Cursor
5 xII + Curso!'

x.,.

YJYzY.Y,
-+~++--o

~~f.+---ov

0 0

O--+-t+~

0 0 1-9-+~~

o

1

·A·-+~~_-ov 0 1 I-~~+-.i1 0

Ao--~H>--+­

1 1

I-~~+

101
1 0 1

I-O-+~~

......~. ._-ov 1 0 I_~~'"
v 1 1
-+-oJ.++-1---o
-+<~~_.-n"Vv

01 03 05

02 04

01

1 0
1 0

0 O---+-(~~
0 1-0-+++.0-

1

ROM

o

Clock signal'for External characte!' gene!'ator
(dynamic ROM etc.) if necessary.

5

ROM

I

Dot data inputs from External character
generator.

l(H): ON
O(L): OFF

05

ROMS

1

OSCI
OSC2

2

GNO or VCC

I

(I)
(0)

Select Internal or External ROM.
H: External ROM
L: Internal ROM
Oscillator.

5 x 7 + Cursor : Rf"200kQ (typ)

5 Xll+Cursor: Rf-130kQ (typ)

• CHARACTER DOl PATTERNS
e

5

x

7

The bottom lines of the English small characters "g. i. P. q. y." are
on the cursor line.
CharaC:-:--_ ..:.uue

o

2

3

..

5

6

7

9

A

B

c

o

E

F

2
o

e

5

x

11

Only English small character

tl

g • j, p, q, y," are displayed as below, the

others are in the same way as that of 5 x 7.

9 oj Pq Y
0

e."Cursor 5 dots: • • • • •
1 dot : •
The cursor is displayed on the 8th or 12th line.

t ....'

• APPLICATION

• Setting Up
a)

Total character number .•••• (CNO - CN2)

h)

Cur'Sial' 'pattern ••••••••••••• (CURS)

c)

Oispl.''';'tll'llt.82

DR3

IlR3

IHH

DR.

l>R5

DBS

l>86

DB6

DB7

087

HO 43160AH

In this example, the addresses of H043l60AH in the address area of the
H06800 microcomputer are
(R/W=O)

Instruction code register

II'E***'

Character code register

II'F***'
(R/W=O)
I'E***' or I'F***' (R/W-l).

Busy flag

*: don't care

b)

Example of display program

1

Read Busy flag
from 1/ 'E***'
or /I 'F***'

Check Busy or Ready

Y: Busy

Instruction

Character

RSO = 'L'

RSO

Write Inst. code
to II • E***'

c)

=

'H'

Write charact. code
to fJ 'F***'

Time length of Busy
write Inst. or Charact. code

E

a ... y

------...ISlt..-..----_ __
2 .

(Internal)

operat~on

en d

T busy

Display clear
Other function

MIN

MAX

400
--

410
-Fcp

sec

20
-Fcp

sec

Fcp
10
-fcp

HD43l60AH begins the operation from the rising edge of 'E'.
Instruction code register and Character code register latch the data
on DBO - DB7 at the falling edge of 'E'.

d)

Timing chart

Read sequence

''''rite sequence

,

(MPU-H0431&OAH I

,I-•

PWEL

•I

\

CS3
RSO

I

-I

)

r

CSO

PWEH

tAS

• I .. ,

J,
1

tH

r

R/w

..

DB '1

IR

st •
c ~rac
co
e

OBO
I
OB7

I

1•

~

PYIEH

..

,

.. I

l

J
tAS

I

I !DDR.

]

\

CS3
RSO

I
I

Write

t-

cso

[

PWEL

1

E

-'1
"

I

R/w

I-

L

'tDDW'

tcye

1-

I

1
L_

.. ,

teye

I

E

(MPU-H043180".HI

~

I

-t~H

[

:

C

Read

(!~:~J

(

e)

Timing characteristics
Symbol
Cycle time of 'E'

tcyc

typ

max

Unit

-1.0

-

-

lJS

-

25

lJs

-

lJS
ns
ns

min

H level

PWEH

0.45

L level

PWEL

0.45

Set up time of CS

Write

tAS

140

Deta delay time

Write

toow

-

-

Read

tOOR

-

-

225
300

tH

10

-

-

Pulse width of 'E'

Hold time

ns
ns

f)

Example 2

Interface to 80SSA (Intel)

r-------------------------________

51

J-----------____

IO/R

IU>~

~

I

",IS

~----

~

~

~----------------------~

I

R/w
e5J
E'

-------------......;.--______~ e52

AU ~--------e51
All H-H-------------------------_~ eso

H-l+-----------------______

AI2

SOSSA

~

HD43l60AH

~'-:_L.;;.;~L=.;.R:.__;_1'~L..:-L-K--:....I~

(MPU)

ALE

RSO

eLK~

READY ~-----------------~
ADO ~----------------------~ DBO
!
J
DB7
AD7
_ "_ _ _ _ _
_....J~----------------------~

g)

Timing chart

.,

eLK

f

f

(

I

I'--

IOIR. 51

--

A12 AI5

I--

ALE

...

-

1

~

READY

\..

\

\
T1

T2

TWAIT

T4

Pulse widths of RD and WR signals of the SOSSA are 400ns MIN, while
the pulse width of E signal of the HD43l60AH is 4S0 ns min.
Therefore, in this example, RD and WR signal pulse widths are
widened b)! using TWAIT cycle.

• DtSPlAY COMMANDS
• Display Controll Instructions
These instructions should be written into the instruction register of
HD43160AH by the controller.
a)

(RSO·'L',

R/W~'L')

Display clear
MSB

Code:

LSB

lor 0 r0 r0 [ 0 I 0 I 0 I 1 I

Operation:

The screen is cleared and the

curso~

returns to the

1st digit.
b)

Cursor return
LSB

MSB

I I I I I I I I I

Code:
0 0 0 0 0 0 1 0
Operation: The cursor returns to the 1st digit and the characters
being displayed do not change.
c)

Cursor ON/OFF
LSB

MSB

Code:

I~ f~ f ~ I~ f~ Ii I~ I~ I

Operation:
d)

(ON)
(OFF}

The cursor appears (ON) or disappears (OFF).

Set cursor position
MSB

LSD

(N-1) bin~ry
(n-1) binary
2 ll.nes L 1
ower
1
1 I (m-1) binary
N.n, m: di g it number
Operation: The cursor moves to the Nth (nth, mth) digit.
Code:

1 line

.

I upper

1

1

oI

N , the total character number;
n,m , 1/2 total character number.
ex 1

*1 1ine*
Set the cursor at 55 digit.

ex 2

The code is '10110110'.

*2 1ines*
Set the cursor at 35 digit of upper or lower line.
The code is '10100010' (upper).
'11100010' (lower),

• Display Character Command
When the character code is written into the character register of ,
HD43160AH, the character of this code appears where the cursor was displayed and the cursor moves to the next digit.

(RSO='H', R/W='L')

MSB
code:

(CHARACTER CODE)
ex 1
before
after

I ABCD
I~============~
ABCDE
~----~--------~

• Read Busy Flag
When CSO -CS3='H', R/W='H' and E='H' (RSO='don't care'), the Busy/Ready
signal appears on DB7.
DB7

'H': BUSY
'L': READY

Time Length of Busy (@OSC=200kHz)

MIN

MAX

Display clear

2.0

2.05

ms

Other operations

50

100

l1s

(depends on the operating frequency)

• Interface to External ROM
a)

Example
.
~haracter

ode

eSB XI

i

lD43l60AH
Row
code

r

xo

X2
Xl
X4
X5
X6
MSB X7
LSB YO
YI
Y2

,MSB Yl

,A
01
02
03
04

Address

!

External
ROM

J

t------- •
] Data

05
ROMS

Interface to External ROM

ROMS
1: Ext.
0: lnt.
*~A is used as the
pre charge signal for
Dynamic ROM if necessary.

b)

Row code

Row code
01 02 OJ 04 OS

o
o

Row code
01 02 03 04 OS

Y'l YIVO

)3

Y3 Y'l YI YO

0

0

0

o 0

o
000

0

0

0

000
000

o

0

000

o

0

o
o

(Cursor)

0

(Cursor)

5 x 11 + Cursor

5 x 7 + Cursor

c)

Timing chart

CL2

I

xo-X 1

VO-V3

-I
IIA

I I
_2_

\

fep

I

I

01-05
ROMS

• I

I •

I

I

I

MAX

_3_
fep

I

Effective data

r

0

o

• Interface to LCD Orivers
a)

Example

--

Common
signals

Liquid crystal display

I

I

r
Y21- V40
VI-V6
Fes
SHLI

~

~

~
,...--

¥J-Y20

HD44100H

SHL2
DLI
DL2
DR2

--

I

DR I
CL2

CLI

..

Segment
signalsf_
-.

-

~
t-C

M

VI- V40
VI-V6
FCS
SHLI
SHL2
DLI
DRI
DL2

HD44100H
CLl

CL2

M

DR2 -

FLM
D r--'

.;i::~:'

D43160AH

- -- --

ell

- --

CL2

.

'"

,~.

b)

Interface to •. .J4'dCC'a

(5 x 7 + Cursor 1 line).

Wave forms

2

8

3

4

5

6

7

8

I

F'LM

I

I

I I

CLI

I I

I I

2

M

Enlarged
F'LM
CLI
M

n

n,

~

CL2
0

One row of a character
One row of 80 characters (400 dots)

--

• DOT

MA1Rr~

LIQUID CRYSTAL DISPLAY SYSTEM

Typical Application
5 x 7 + Cursor

Lines40Character&

eND vv....,...

.,

II ,nl rr

..... ,....

"0 ..... "
.1

1.~-ril111

~

E !=

;~

r-- ~

~.l

J~

hml'l

HD44100H

;;

.. ..... ---:.""L>__

U 1UJJ

II
"'" ~ff

~

-~

- - -mlRluBl
I

11111

11111 11111

11111

.11111

HD44780 (LCD-II) (DOT MATRIX
LIQUID CRYSTAL DISPLAY CONTROLLER &DRIVER)
The LCD-II (HD44780) is a dot matrix liquid
crystal display controller & driver LSI that
displays alphanumerics, kana characters and
symbols.

It drives dot matrix liquid crystal

displa)! under 4-bit or 8-bit microcomputer
or microppocessop control.

All the functions

required for dot matPix liquid c1!'ystal display

(FP-BO~

drive are internally provided on one chip.
The user can complete dot matrix liquid

• PIN ARRANGEMENT

crystal display systems with less number of
chips by using

theLCD"';;II~(HD44 780)

•

If a

driver LSI HD44l00H is externally connected

.......•..•.....

.}}}}}}}}~}}}~}}~
-...... -....... .

to the HD44180, up to 80 characters can be
displayed.
The LCD-II is produced in the

CMO~

process.

Therefore, the combination of the LCD-II
with a CMOS microcomputer or microprocessor
can accomplish a portable battery-drive
device with lower power dissipation •

• FEATURES

~ ....
:.- ••••C""'4
.r.r: ••••••
--• • • C4

• 5 x 7 and 5 x 10 dot matrix liquid crystal
display controller driver

(Top View)

• Capable of interfacing to 4-bit or
8-bit MPU.
• Display data RAM ••• 80 x 8 bits
(80 characters, max.)
• Character generator ROM ..•
Character font 5 x7 dots:

160 characters

Character font 5 xlO dobts: 32 characters

• Both display data and character generator RAMs can be read from the MPU.
• Internal liquid crystal display driver •••.•
16 common signal drivers
14 segment signal drivers (Can be externally extended to 360 segments
by liquid crystal display

~riv~r ~pAt·~

• Duty factor selection (selected by program) •••••
l/S duty:

1 line of 5 x 7 dots + cursor

1/11 duty:

1 line of 5 x 10 dots + cursor

1/16 duty:

2 lines of 5 x 7 dots + cursor

Maximum number of display characters
"

I

No. of
display
lines

Duty
factory

I-line
display

l/S
1/11
duty·

2-line
display

1/16
duty

Extension HD447S0
Not
provided

1 pc.

provided

1 pc.

Not
provided

1 pc.

provided

1 pc.

HD44100H ,,-

-

S characters

9 pcs.
(8 characters/pc.)

-

No. of display
-- char,ac te rs
X.l.

80 characters xl line
S characters x2 lines

4 pcs.(S characters
40 characters x 2 lines
x 2 lines/pc)

• Wide range of instruction functions
Display clear, Cursor home, Display ON/OFF, Cursor ON/OFF,
Display character blink, Cursor shift, Display shift
• Internal automatic reset circuit at power ON. (Internal reset circuit)
• Internal oscillation circuit (with external resistor or ceramic filter)
(External clock operation possible)
• CMOS process
• Logic power supply:

A single + SV (excluding power for liquid crystal
display drive)

• Operation temperature range:

'---

-20 - +75°C

(Device for -40 - +SSoC
• SO-pin plastic flat package (FP-SO)

available upon request)

.
.
.

Vee
OND
OSC I

r-

.

OSC t

"'"'
~

C::H

0-

~
~

~

;j

~

8
U III f,.<-

~ (I)
~~
(I) l)Q

8

RS

c::

III

H~

R/W

~

III

£

~

~

~ III
U~

';j

71

7

c::

0

7

ir-

0

~ U
~ III
(I)~

-

7

t

:z
-t

7

~

.,!lI! ;j

;j

4

-

IQ

0

.......

"'"'
~
~

8

H

4

~

III

c:: U
..... ~

8

r-i~

8

~~

VI

ower Supply
.·or Liquid
. rysta1
isp1ay Drive V4V,

.
.
.
•
.

Busy
'-!Flag

.....

~

III

Ie

COM, -COM ..

>
c:: ....

(I)

....

o

gt:lM

l)Q

..0 III
,~

\0

8

Mi

~...c

7

8

(I)

to ....
~
00
to III

1e

....tilCIO

IQU

8

~

I--

til ~
~

~

.....

\j,.4

-

c::

~

L...-.-

o;:0

to

.,.1 ~
,t: III

(DO RAM)
80x8 bits

::e

...c

~

RAM

c::

H

.."

Display Data

r--

8

.

Timing Generation
Circuit

Address
Counter (AC)

Character
Generator
ROM
(CG RA,H)
7200 bits

~haracter

r;enerator
ROM
(CG RAH)
512 bits

o

0

::l

c::

(I) ~
~~

~

....c

u8
,.--J

~
....
~
,.ou
4,.1

r-

o' , tU:

..;t~

40

...c
to
c::

::l
U

to

~

40

CIO

....

).4

til

III

~

c::

40

....>

5£0, -5 £040

).4

1lI~

~

III

"

til

5

5

1 I

~aralle+lSex:+al ~ata

,

Conversion Circuit
(Parallel Data Serial Data)

I
o

40-bit Shift Register

,

• ELECTRICAL CHARACTERISTICS
• Absolute Maximum Ratings

I
t'

Item

Symbol

Power Supply Voltage (I) 'V ee
Power Supply Voltage (2) VI to VS

Limit

Unit

-

-0.3 to +7:0

·v

Vee-l3.5 to Vec+O.3

V

-0.3 to Vee+O.3
-20 to +75

V

Operating Temperature

VT
Topr

°e

Storage Temperature

Tstg

-55 to +125

°e

Input Voltage

Note
3

Note 1:

If LSI's are used above absolute maximum ratings, they may
be permanently destroyed. Using them within electrical
characteristic limits is strongly recommended for normal
operation. Use beyond these conditions will cause malfunction and poor reliability.

Note ..2:

All voltage values are referenced to GND-OV.

Note 3:

Applies to VI to VS.

~

VI

(high

+

Must maintain Vee

~

V2

~

V3

~

V4

~

V5

... low)

• Electrical Characteristics (VCC =5V±lOJ, Ta

=-20

to +75°C)

The conditions of VI. Vs voltages are

Vcc --.--..--

for proper operation of the LSI and not
for the LCD output level.

The LCD

drive voltage condition for the LCD
output level is specified in

'~CD

voltage VLC:e".

Item
Input '"High" Voltage (!)
'lnpue-''Lov'' Voltage (1)
Output '"High" Voltage (1) (TTL)
Output -"Low"-Voltage (1) (TTL)
Output ''High'' Voltage (2) (atOS)
Output ''Low'' ~oltage (2) (atOS)

Spbol
VIRl
VILl
VOHl

Driver Voltage Descending (COK)

VOLl
VOH 2
VoU
VCOK

Driver Voltage Deseendin, (SEC)
Input Leakage Current
Pull up HaS Current

VSEC
III.
-Ip

Power Supply Current (1)
Iccl
Power Supply Current (2)
ICC2

Test
condition

min
2.2

U.it
typ

-

- -

-0.3
2.4

-IOH -0.20SI11A
101.-1. 2111A
-IoH-D·04aA
LoL-D·041aA
Id-D.OSaA
Icl-D .OS.A.

- - - -

0.9VCC

Vin-D to Vee

-1

Vee-SV
Ceraaic filter
oscillation
VCC-SV• fo• c•
2S0kHz
I.f osc1Uatf on
External clock
operation
Vee-SV • foBcfcp-270kHz

SO

12S

Unit

Note

V

(2)

V
V

(2)

V
V
O.lVee V
V
2.9
V
3.8

(3)
(4)
. (4)

lUX

VCC
0.6

-

0.4

-

1
2S0

111.

111.

(3)

(10)
(10)
(5)

-

O.SS

0.8

mA

(6)

-

0.3S

0.6

aA

(6)
(11)

External Clock Operation
--- --------- --------- -----------------,------------External ---Clock -Frequency
2S0
3S0 kHz
l2S
fep
(7)

External Clock Duty
External Clock lise Time

Duty

4S

-

trcp

-

External Clock Fall Time
tf~
Input '"High" Voltage (2)
VIH2
Input ''Low'' Voltage (2)
VIL2
Internal Clock Operation (Rf oscillation)

VCC-I.O
-D.3

SO

-

-

55

%

(7)

0.2
0.2

lis

(7)

liS
V
V

(7)

VCC
1.0

(12)
(12)

-l-t::; Tii:;ik"n±ii-- -1190-1270 1- 3S01 kit;l-(B)Internal Clock Operation (Ceraaie filter oscillation)
_._-----... --------------------------------2SS -----kHz
(9)
Clock Oscillation Frequency
24S
Ceraaic filter
250
fose

~Cl;ck Os~iila;i~ F~;;n~-

LCD Voltage

VLCDl
VLCD2

VCC-VS liS bias
1/4 bi ..

4.6
i

3.0

-

11

11

V
V

(13)
(13)

Note 1:

fie following are I/O terminal configurations except for
liquid crystal display output.

• Input Terminal
Applicable Terminals:
(~o-

Applicable Terminals:

E

pull-up MOS)

(Wi'

RS, R/W

~

PMOS

PMOS
Pull Up MOS

NMOS

NMOS

• Output Terminal
.\tJplicable Terminals:

CLI, CL2, M, D

-.• 1

PMOS

NMOS

• I/O Terminal
Applicable Terminals:

v

cc

DBO to DB7

(Pull Up) Vee

MOS

PIDS

PMOS
Enabl e

NMOS

~

________________

PMOS

~

NMOS

1-------- Da t a
(Output Circuit)
(Tristate)

Note 2:

Input terminals and I/O terminals.

Note 3:

I/O terminals.

Note 4:

Output terminals.

Excludes OSCI terminals.

Note 5:

Current flowing through pull-up-MOS's and output drive MOS's is
excluded.

Note 6:

Input/Output current is excluded.

When input is at the inter-

mediate level with CMOS t excessive current flows through the
""inputc1rcuit to the power supp'ly.

To avoid this. inolJt It·.vel

must be fixed at high or low.
Note 7:

External clock operation.
Oscillatort---t- OSC,

Open

Th

osc.
TI

007 Vee

Du t y

005Vcc - - - f . f .

=

Th
Th

+

TI

x 100 %

OolV cc

Note 8:

Internal oscillator operation using oscillation resistor Rf.

,.----t

OS Ct
Rf :

Ql

kn±

z

%

Since oscillation frequency varies depending on OSCI and OSC2
terminal capacitYt wiring length for these terminals should be
minimized.
Note 9:

Internal oscillator operation using a ceramic filter.is used.

c.

Ceramic filter:
Rf:
CJ

~

Cz

'~--tOsCz

Rd

Ceramic filter

rnn

±lO%

Cl: 680pF±lO%
C2: 680pF±lO%
Rd: 3.3kQ±5%

CSB250A (Murata)

Note 10:

Applies to both VCOM and VSEC voltage drops.

VCOK:

From poer supply terminal VCC, VI, V4, VS to each
common signal terminal (COMl to COM16)

VSEC:

From power supply terminal VCC, V2, V3, Vs to each
.... gmc~t siernal 'E'rmim:.l. (SEh t,

Note 11:

Relation between operation frequency and current consumption
is shown in this diagram.

(VCC - SV)

1.1

1.t

I CCI

1.•

(mA)
1•

.

max

.---

'J P

j

./

1.0

/"

o.a
./

o.t
0.•
0.1

....

/

~~

7

V
~

~

:::.. ~

0
100

aoo

100
rolC

100

or fcp (kH,)

Note 12:

Applied to OSCI terminal.

Note 13:

The condition for COM pin voltage drop (VCOM) and SEC pin
voltage drop (V SEC ).

• Timing Characteristics
Write Operation

,

~'

)

v, .. ,

t ...

tn

\

K

V'''I
VI "a.,

VIL'

r--

/.,,,.

v ... ,

~
hr

pw••

I

£
t ..

-

.,.l

V,.,I

V•

V'''I

v",.
hi ..

f-

v •. , )
VI"I

v.I.,
.~

Vaild Data

KVI .. I
VII.I

t ••••

Fig. 1 Bus Write Operation Sequence
(Writing data from MPU to HD44780)
Read Operation

~

v,",

K

V'"I
V'I.I

VII.I

t ..

I ton ,

VI" I

,\IHI

pw..

VII.,
t •• -

DDe-DB

,

V'"I

I
-

'.11
r-" v,",
VII.I- .1'- t.,

V I".

'11 .. &
1----1

t ...

VOII I)
VO"I

Valid Data
J

Kvoll.
VO"I

t., ••

Fig. 2 Bus Read Operation Sequence
(Reading out data from HD44780 to MPU)

Interface Signal with Driver LSI HD44100H

Fig. 3 Sending Data to Driver LSI HD44100H

,.• ~us :-nmingtharacter1st1cs (Vec - s.OV ± lOS, GND -OV, 1a

=-20

to +75°C)

Write Operation (Writing data from MPU to HD44780)
Item

Symbol

Limit
min max

Test condition
.. -

'" '"r. r.·:;<-

PWEH

Fig. 1

450

-

tEr, t!f

Fig. 1

-

25

ns

tAS

Fig. I

140

-

ns

tAM

Fig. 1

10

-

ns

Data Set-up Time

tDSW

Fig. 1

195

Data Hold Time

tH

Fig. 1

10

Enable Cycle Time

; i··"

~

[ ''High''
level
Enable Rise/Fall Time
Enable Pulse Width

-...,

y*.
~
cyc

Unit

Address Set-up Time [ RS, R/W
-E
Address Hold Time

'lIIIiiIfP j

0'

Fig. 1·

".

1000

-

ns
ns

ns
ns

Read Operation (Reading data from HD44180 to MPU)

.
Symbol

Item

Tes t condi tion

Limit
min max
..

Enable Cycle Time

450

-

ns

Fig. 2

-

25

ns

Fig. 2

140

tcycE

Fig. 2

1000

PWEH

Fig. 2

Enable Rise/Fall Time

tEr' TEf

Address Set-up Time [~ R/W

tAS

Enable Pulse Width

Ilevel
''High''

-

.

Address Hold Time

Unit

tAH

Fig. 2

10

Data Delay Time

tOOR

Fig. 2

-

Data Hold Time

tOHR

Fig. 2

20

ns

ns
ns

.-

320

ns

-

ns

• Interface Signal with HD44100H Timing Characteristics
(VCC = 5.0V ± 10%, GND =OV, Ta = -20 to +75°C)

Item
''High~'

Clock Pulse Width

level
''High''
level

Symbol
tc""

Limit
min max

Test condition
,

<""'" • .,..

\

. .,,

"

:

Unit·'

'aoo

-

ns
ns
ns

tCWL

Fig. 3

800

Clock Set-up Time

tcsu

Fig. 3

500

-

Data Set-up Time

tsu

Fig. 3

300

-

ns

Data Hold Time

tDH

Fig. 3

300

-

ns

MDelay Time

tOM

Fig. 3

Clock Pulse Width

-1000 1000

ns

Limit
min max

Unit

• Power Supply Conditions Using Internal Reset Circuit
Symbol

Test condition

Power Supply Rise Time

trcc

-

0.1

10

ns

Power Supply OFF Time

tOFF

-

1

-

ns

Item

Since the internal reset circuit will not operate normally unless the
preceding conditions are met, initialize by instruction.
(Refer to "Initializing by Instruction")

Vcc

0.2
t

(Note)

tOFF stipulates the time of power OFf for power supply
instantaneous dip or when power supply repeats ON and OFF.

• Tenninal Function
Table 1 Functional Description of Tenminals

No. of Input I
Signal
name ...... lines. ',' Output.
as
1
Input

Connected
to
KPU

Function·
Signal to select registers
"0": Instruction register
(.for write)
Busy flag; address counter
(for read)
"1": Data register (for read and
write)

Rlw

1

Input

KPU

Signal to select read (R) and write (W)
"0": Write
"1": Read

£

1

Input

MPU

Operation start signal for data readl
write

DB4 ..

4

Inputl
Output

MPU

Higher order 4 lines data bus with
bidirectional three-state. Used for
data transfer between the KPU and
the HD44180. DB7 can be used as a
BUSY flag •
. Lower order 4 lines data bus with
bidirectional three-state. Used for
data transfer between the MPU and the
HI>44780. These four are not used
during 4-bit operation.

DB7

.-..... ----.

._"

..
4

Input I
Output

MPU

CLl

1

Output

H044100H

CL2
M

1

Output

KD44l00H

1

Output

H044looH

Switch signal to convert liquid crystal drive waveform to AC.

D

1

Output

H044100H

16

Output

Liquid
crystal
display

Character pattern data corresponding
to each common signal is serially
sent.
"ott: Non selection
"1": Selection
Common signals that are not used are
charged to non-selection waveforms.
That is, Caf9 - COK16 are in nonselection waveform at 1/8 duty factor,
and COK12 .. COK16 are in non-selection
waveform at 1/11 duty factor.

40

Output

Liquid
crystal
display
Power
supply

DB() ..
DB)

COHl ..
COH16

SECl ..
SEC 40
Vl "VS

5

VCC. CND

2

OSCl,
OSC2

2

Power
supply

Clock to latch serial data D sent to
the driver LSI HD44l00H.
Clock to shift serial data D.

Segment signal

Power supply for liquid crystal
display drive
VCC; +SV. CND; OV
Terminals connected to resister or
ceramic filter. for internal clock
os illa tion •
For external clock operation, the
clock is input to OSCI.

• FUNCTION Of EACH BLOCK
Register

(1)

The HD44780 has -two 8-bit registers, an instruction register (IR) and a
data register (DR).
The IR stores inflt;o-uctia ~..;s .such as display clear and cursor shift,
~,.d

addrt:iss information. lor dlsplcij

generator RAM (CG RAM).

C1csi:.Q;rr~~~;f "uOi\lii{)

and character-'

The IR can be written from the MPU- but not read

by the MPU.
The DR temporarily stores data to be written into the DD RAM or the CG
RAM and data to be read out from DD RAM or CG RAM.

Data written into

the DR from the MaU is automatically written into the DD RAM or the CG
RAM by internal operation.

The DR is also used for data storage when

reading data from the DD RAM or the CG RAM.
is written into the IR, data

i~

When address information

read into the DR from the DD RAM or

the CG RAM by internal operation.
completed by the MPUreading=DR.

Data transfer

b

the MPU is then

After the MPU reads the DR, data

in the DD RAM or CG RAM at the next address is sent to the DR for the
next read from the MPU.

Register selector (RS)si_ls make their

selection from these two registers.

Table 2 Register Selection

(2)

RS

R/W

Operation

0

0

IR write as internal operation. (Dlspla7 clear, etc.)

0

1

Read busy flag (DB7) and address counter (DBO - DB6)

1

0

DR write as internal operation

1

1

DR read as internal operation

(DR to •

or CG RAM)
(DD ora: RAM to DR)

Busy flag (BF)
When the busy flag is "1", the HD44780 is in the 'ildlrrnal operation mode,
and the next instruction will not be accepted.

As'llble 2 shows, the

busy flag is output to DB7 when RS-O and R/W-l.

'lhenext instruction

must be written after ensuring that the busy flag is. "0.".
(3)

Address counter (AC)
The address counter (AC) assigns addresses
instructioll;

f~r

a4dress is

sent frhUS lit' to AC.

~rit~en

Seleel::[on

.. '," '...

!. '"~.:...

'

in IR, the

6f ~it~er

(:Qnc~r:r:ent;ly by t;.he:inst,ru~t;,~;~~n.(
".' . .,',"; ~

toDD~,S:RAMs.

When an

aaa-.1nfo~ation

is

DD or CG,:lIIi,?"is also determined

After writing into (or reading from) DD or CG RAM display data, AC is
automatically incremented by +1 (or decremented by -1). AC contents
are output to DB'O .... DB6 when RS-O and R/W-l, as shown in Table 2.
(4)

Display data RAM (DD RAM)
The display data RAM (DD RAM) stores display data represented in 8-bit
character codes.

Its capacity is 80X8 bits, or 80 characters.

The

display data RAM (DD RAM) that is not used for display can be used as
a general data RAM.

Relations between DD RAM addresses and positions

on the liquid crystal display are shown below.
The DD RAM address (ADD) is set in the Address Counter (AC) and is represented in hexadecimal.
Lower Order
-+
Bits

+Upper Order
Bits

\... Hex~dec~mal
(Example)

.J ' -

Hexadecimal

..J

DD RAM address "4E"
1

1

o

' - - - 4 - - - 1 ''-- - - E _ _--I'

I-line Display (N=O)
(digit)

I

2

3

4

79

5

.....................

I-line
{a)

80

1-

1-

Display
Position
DD RAM
Address

When the display characters are less than 80, the display begins
at the head position.

For example, 8 characters using 1 HD44780

are displayed as:
(digit)
I-line

I

2

3

4

5

6

7

8

I 00 [ 01 I 02 1 03 1 04 1 05 [ 06 1 07

1-

1-

Display
Position
DD RAM
Address

When the display shift operation is performed, the DD RAM address
moves as:

(Left

Shift
, 01 [ 02 [ 03 [ 04 [05
Display)
(Right
Shift
14F [ 00 [ 01
Display)
(b)

I

06 [ 07 [ 08}

!

02 [ 03 [ 04 1 05 f 06}

l6-character dispby "'dng <:>n

HI)I.4 7e~

H0441QOH is as' "'hown

,c,1o

below:
1

(digi t)
I-line

2

34

5

6

7

8

9 10 11 12 13 14 15 16

IOOl0110210310410sl06 107 108 [0910A[OBlocIOD(OEIOFI
L--

-+-

Display
Position

-+-

DD RAM
Address

HD44780 Display---1 L - HD44100H Display-.-J

When the display shift operation is performed, the DD RAM address
moves as:
(Left

Shift
Display
(Right
Shift
Display)
(c)

The relation between display position and DD RAM address when the
number of display digits is increased through the use of one
HD44780 and two or more HD44100H's can be considered an extension
of (b).
Since the increase can be 8 digits for each additional HD44l00H,
up to 80 digits can be displayed by externally connecting 9
HD44100H's.

(digit) 1

I

8

,

5

6

7

78 H

II 10 11 12 18 I' 15 16 11 18 111 10

8

n 76 77 78 n 80

.. Displa,

Pos! tiOt!
.. DD RAM

I-line

Address

LHD44780
Diaplay

~ L HD44l00H(l)-1~4~~~~~8) JLHD44l00H(9)-1
Display

D'

lSP

1

Display

ay

2-line Display (N=l)
(digit)

1

2

3

4

5

I-line

00

01

02

03

04

. . . . . . . . . . . . . . . . . . . . . ..

2-line

40

41

42

43

44

. . .. . . . . . . . . . . . . . . . . . . .
:'""'~:

__''':

39

40

-+-

Displa4
Position:'

26

27

-+-

DD RAM
Address

66

67

:--~_,--_:'fI;-,~~

....

_~~.,.,.",

(ar

When the numbel' of display characters is less than 40 x 2 lines.
the 2 lines from the head are displayed.

Note that the first line

end address and the second line start address are not consecutive.
For examp1e, when an HD44780 is used, 8 characters x 2 lines are
displayed as:
(digit;

4

5

6

.7

8

1-11ne

00

01

02

03

04

05

06

07

2-11ne

40

41

42

43

44

45

46

47

+

Display
Position

+

DD RAM
Address

When display sh1ft is performed, the DD RAM address moves as:
(Left
Shift
Display)

01

02

03

04

05

06

07

08

41

42

43

44

45

46

47

48

(Right
Shift
Display)

27

00

01

02

03

04

05

06

67

40

41

42

43

44

45

46

(b)

16

characters~~X-

2 lines are displayed when an HD44780 and an

HD44100H are used.
9 10 11 12 13 14 15 16

+

l-lirie

00 01 02 03 04 05 06 07 08 09 OA OB OC OD OE OF

+

2-1ine

40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F

(digi t)

1

~

2

3

4

5

6

7

HD44780 Display

8

--1'--

HD44l00H- Display

Display
Position
DD RAM
Address

--1

When display shift is performed, the DD RAM address moves as
follows:
(Left
Shift
Display)

01 02 03 04 05 06 07 .08 09 OA OB OC OD OE OF 10

(Right
Shift
Display)

27 00 01 02 03 04 05 .06 07 08 09 OA OB OC OD OE

41 42 43 44 45 46 47 48 ,49 4A 4B 4C 4D 4E 4F 50

67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E

(c)

The relation between display position and DO RAM address when the
number of display digits is increased by using one H044780 and two
or more H044100H's. can be considered an extension of (b).
Since the increase can be 8 digits x2 lines for each additional
~D44100H, up to 40 digits

2 lines can be displayed by connecting

4 HD44780's externally.
1

8 D 10 11 1% 13 1+

U

08

07

08 OD M <8 CC 00

OE OF 10

2-line +0 +1 +2 .a u +:) +8 +7

+8 +D 40A 4B 4C 4D

+E +F :)0 n

(digit)1

% 3 + :) 8

I-line 00 01

L
(5)

0%

03 0+ 0:)

HD44780
Display

18 17 18 ID %0
11

33 M 3:)

12 18 ----- %0

U

22

23 U

----- 80

81

82

83 84-

:iZ :)3

---.JL H044l00H(l) --1LH044100H i
~isplay

(2) (3)
Display

Character Generator ROM (CG ROM)

38 87

8D .a ..oisplay
position
2G
11+25
DD RAM
address
8:) 88 87 (ijexadec1maJ.)

88

H044l00H(4)
Display

...J

The character generator ROM generates 5 x 7 dot or 5 x 10 dot character
patterns from 8-bit character codes.

It can generate 160 types of '5 x

7 dot character patterns and 32 types of 5 x 10 dot character patterns.
Table 3 and 4 show the relation between character codes and character
patterns in the Hitachi standard HD44780AOO.

User defined character

patterns are also available by mask-programming ROM.

For details, see

"The LCo- n (HD44780) Breadboard User's Manual".
(6)

Character Generator RAM (CG RAM)
The character generator RAM is the RAM with which the user can rewrite
character patterns by program.

With 5 x 7 dots, 8 byptes of character

patterns can be written and with 5 x 10 dots 4 types can be written.
Write the character codes in the left columns of Tables 3 and 4 to display character patterns stored in CG RAM.
Table 5 shows the relation between CG RAM addresses and data and display
patterns.
As Table 5 shows, an area that is not used for display can be used as a
general data RAM.

Table 3 Correspondence between Character Codes and Character Pattern
(Hitachi Standard HD44780AOO)
lgher

~
bit 0000
4bi t

Love

,

xxxxOOOO

xxxxOOOI

0010 0011 0100 0101 0110 0111 1010

1011 1100 1101 1110 1111

..
1'
:
'
1
::~il I::) • ,=.
..... .1:]•.I~__=
1••11
~~II~)~____~~':'mL"-L_I.mml.~'~I~~~__-L~I·__~__~~__-L~.~
~_.~ _.
~~
121

(3)

I

·
II

-.

1 1':1 I'-:-i ·=1I.

i

:

··-1 '1:--.
!-

•

1-

.••••

I · - r .el-..

:·-1 ••-, •• •
!·r

III
_.. .

••. -

~____L-____~.uu.~·~~i~.~_~:-L~i·__-~.~i~.'.~.~u,IL"__~~__~L-·JL
1L__c-_&_.-A~~·_·_·-f

'·!I':I: ..::.

I'···· I::::·

:~I
I·" ••xxxx0011 1-____........lLi...i:·....J;:..·...........I..L..J".IU.' . .'-·...L
· ....a'..'......I-L_........... . J;..J......
-...._.•JW......
xxxx0100

xxxx0101

xxxx0110

151

••!e.
.:t:.

.1 II··'·:

1-:• •
lO •• •

i

1·1

il............

·T· .. ! .!•
Ii ·I·:
I' . . . •••
••• :

is)

1I.·t=:-···::
.....
••
I :... I : : ...: I :

(7)

I::· .::

..

::

I:· i•••..
I .c·
!

I.}

.....

!
-- ~ ~
••
·I_·_·___·_r._
-Lf ::..

--I.L·
' __&......

t:1 L~· -

I i··

I

I

.11.

1

-:
..J-~••-. _.•1

I-____~·__:~;·~~·~·.......~··~:......
~.~_·••'.~
••L·"_Z~·.....&_.~·..J·.UL.·· ·i~____-L__

I':.: .I...: ,!

1__•

•

I~.
~-L~·__-A~~Lf ---

1_••..,1,.

7.-. .I"'~1•. .-

~:II .:1 1.1... :::.

-r.· · .L-.: ;..a. -.'~" I:J
~I J'.
.... .....L
I·- :··-1 'l.t: :..·"1..
I· -. ..
.. I· .1"1 ::j!:.·1
,II
r •••••
~ .~:~·.um
••~·I~ ~~~;·_·_·~I~..lLi~I~~.L-·_·_·~._·_·~i""''''''''_.'''.··
·-A_~.··__~·.
.. 1:1 • • . •.1,
-I

__
8) --"-:I-..I...•.L.... ......
!' ___.I.Io:--I...L·1..a..1-L--..-----...JL-=___.1::-...L.-..1L-·._·
xxxxOl11 ,1
r!
. .ftaa!····L.L.....
..1.. ~r

(I)
xxxx1000 1-____
__• __

xxxxlOOI

xxxxl010

x)()cxl 0 II

121

(3)

••

I

I

.......

__

•• •

.:•• .• -..••
••••

••

..:••_-

••
••
••
••

•• e.

__&''-·___

T
•••

I

;

••
:•

i

.... ..'
. I-I

.:

·r•...•:: •.:•-:•••••• .....1 •.•
•1 1

i.·

•••

•
I ::r_

...

. ..:."
· ....:"
· i :
·
••••. .
I.... ._.. ..:...
I---~---'----~~~~~~~~~~~~·M·
I~I

(51

..

:
••••
:• •

-.

.. ___•••..·__ 5.

:•

..

••
•• ••

••
•••
I : I I
• .:.!••
••• •••••
•• •••••• ... I....._.

:::::
.....

.....

5 .
.:...::
.
. .__I •. ,__ 1·-1

-1.:

r-____L-~.~··~

)(Xx)(ll 01

...-_(6__)-t_·_·_-__·.L.:-_·_-__

xXlexlllO

·~I'-·
. "II'" ••••
:
~--~~I~i-4-~
..·~LAi·--&i·~----~~i·--~i·u-----~.~.~
•• i~L-~·-ma.~-~;-L

.~~.~,.IU.,.u.,.~.'__..J:L__L_ i·.L_~_~i·~~~i·L_·~~~~~L· '__.~-.··

L-___
···~

:. . I .J l·_'_·~i.l :. _ ~ :iL_.J. I ~·_·_i·l. .L.~ L.: _·~L. .: -.~." .!.!.U<.~·~.:-_.:. J.~LJ. _·_·_·_·I_".~. . . . .~.-I-t

(7)

(8}

..
•

·•

.. ...

."...

.••. ..
!. '. ••.•• ..
...: .....
•• ••••

•...• •...•

...

•••

.•

•

1

I_I

:- :
:
•• ••

)(xxxllOO

xlexxlill

I-I
·

..

•
I • .....
...:
I · ... ... · i · ·

1.1.1

-:-.

*I·:. . •
•

.I

____;

Ill'

r-----~.-·--~--~.·~~-:.~~.I-L~.~.,.~••~.~.~
...~.~-·-.--~·~:.~:-L_.:.~.__~_._.:~~____~

••

I- I
...

...•••
:::·
···1
I...
•••
:.::::::

I ..•

*

The user can specify any pattern for character-generator ROM.

Table 4 Relation between CG RAM Addresses and Character Codes (DO RAM)
and Character Patterns (CG RAM Data)
(a)

For 5 x 7 dot character pat terns
Character Codes
(DO RAM Data)

Character Patterns
(CC RAM Data)

CC RAM
Address
5. a I 10
II i gber tOIler
Ocder " Ocder ...
..- htl
Ilt.

L-

0

0

* * *p" ~i..~l"~l'r~lrt.: 0
11· 0 0 0 0

_.

;

0

0

0

1

0

0

0

1:1

".

0

0

0

0

1

0

0

1

I~

.0

0

0

0

___ 1-1_ ~
0

_!._ ~ ___

:_!_!L

1 1* *

11

1

1

0

: 1

1

1

1

O_!_ ~_ !_~

*:* *

0

0

0

10

00

1

1 0

*

*

*

*

*

*

+

Cursor
position

I::
I

*

*

*1* *

1
-*""::::::::::::~::-I-.i.~ -l-.J:.-------Ji.-:::::;--~
10
1

------------- e---

0
0

0

I

o 0 0 0-*-1--1

0
0

~

O~O

1100
.11 1 1 0 1

.....

0

0

1

(Note)

81tl

000
0-0 1

11

~--

1

Lower
Otder _

*

*

*1

I

~

I

0

-;:::::;-

* J *:

---r:T: -r~ -- **,- *',;* *-*,-*"*
:1

0

1

0

11

1

1

0

: 1

1

1

1

*No Effect
*

*

*1* *

*

*

*

1:

Character code bits 1, 2 correspond to CG RAM address bits 4, 5
(2 bits: 4 types).

2:

CG RAM address bits 0 - 3 designate character pattern line position. The 11th line is the cursor position and display is performed in logical OR with cursor.
Maintain the 11th line data corresponding to the cursor display
position in the "0" state for cursor display. When the 11th
line data is "1", bit 1 lights up regardless of cursor existence.
Since the 12th - 16th lines are not used for display, they can
be used for the general data RAM.

3:

Character pattern row positions are the same as 5 x 7 dot character
pattern positions.

4:

CG RAM character patterns are selected when character code bits
4
7 are all "0". However, since character code bit 0 and 3 are
ineffective bits, "p" display in the character pattern example
is selected by character code "00", "01", "08" and "09" (hexadecimal).

5:

"1" for CG RAM data corresponds to selection for display and "0"
for non-selection.

(7)

Timing Generation Circuit
The timing generation circuit generates timing signals to operate interna'll
circuits such as DD RAM, CG ROM and CG RAM.

RAM read timing needed

display and internal operation timing by HPU access are separately gent . . ~ted so they do not interf.ere witll .each other.

:....

~-~ '-~

Therefore, when writin .

'--

data to the DD RAM, for example, there will be no undersirable influence,
such as flickering, in areas other than the display area.

This circuit

also generates timing signals to operate the externally connected driver
LSI HD44l00H.
(8)

Liquid Crystal Display Driver Circuit
The liquid crystal display driver circuit consists of 16 common signal
drivers and 40 segment signal drivers.

When character font and number

of lines are selected by a program, tue rt'luired common signal drivers
autom~tically

output drive waveforms, the other common signal drivers

continue to output n()n-selection waveforms.
The segment signal driver has essentially the same configuration as the
driver LSI HD44l00H.

Character pattern data is sent serially through a

40-bit shift register and latched when all needed data has arrived.

The

latched data controls the driver for generating drive waveform outputs.
The serial data is sent to the HD44l00H, externally connected in cascade,
used for display digit number extension.
Send of serial data always starts at the display data character pattern
corresponding to the last address of the display data RAM (DD RAM).
Since serial data is latched when the display data character pattern,
corresponding to the starting address, enters the internal shift
the HD44780 drives the head display.

register~

The rest displays, corresponding to

latter addresses, are added with each additional HD44l00H.
(9)

Cursor/Blink Control Circuit
This is the circuit that generates the cursor or blink.

The cursor or

the blink appear in the digit residing at the display data RAM (DD RAM)
address set in the address counter (AC).
When the address counter is (08)16, a cursor position is:

AC6 AC5 AC4 AC3 AC2 AC1 ACO

[n a I-line display
(digi t)

1

2

3

{I I
00

01 [ 02

4

!

03

5

6

7

8

104 1OS I 06

[ 07

.

9

10

11

+

Y[ !

1

09

Display
Position

+ DD RAM

OA [ (

Address
(Hexadecimal)

the cursor position

In a 2-1ine display
3

4

5

6

7

8

9

10

11

00

01 .02

0)

04

05

06

07

~

09

OA

40

41

42

4)

44

45

46

47

49

4A

2

1

(digit)
(

1st line

{
2nd line
l

~48

+

)
I

+

Display
Position
DO RAM
Address
(Hexadecimal)

the cursor position
(Note}

The cursor or blink appears when the address counter (AC}
selects the character generator RAM (CG RAM). But the cursor
and blink are meaningless.
The cursor or blink is displayed in the meaningless position
when AC is the CG RAM address •

•

INTERFAC~NG

TO MPU

In the HD44780, data can be sent in either 4-bit 2-operation or 8-bit I-operation so it can interace to both 4 and 8 bit MPU's.
(1)

When interface data is 4-bits long, data is transferred using only 4
buses:

DB4 - DB 7 •

DBO - DB) are not used.

Data trans fer be tween the

HD44780 and the MPU completes when 4-bit data is transferred twice.
Data of the higher order 4 bits (contents of DB4 -DB7 when interface
data is 8 bits long) is transferred first, then the lower order 4 bits
(content of DBO - DB) when interface data is 8 bits long) is transferred.
Check the busy flag after 4-bit data has been transferred twice (one
instruction).

A 4-bit 2-operation will then transfer the busy flag and

address counter data.

1

as ______________________________- J

a/W-------------J1
£

Instruction (IR)
Write

Busy Falg (BF) and
Address Counter (AC)
Read

Data Register (DR)
Read

Fig. 4 4-bit Data Transfer Example
(2)

When~interface

data is 8 bits long, data is transferred using the 8 data

buses of DBO ... DB7'

• RESET FUNCTION
e Initializing by Internal Reset Circuit
The HD44780 automatically initializes (resets) when power is turned on
using the internal reset circuit.
in initialization.
alization ends.

Display clear

(2)

Function ser

(3)

(4)

The busy flag (BF) is kept in busy state until initi-

(BF=I)

(1)

The following instructions are executed

The busy state is 10 ms after Vee rises to 4.5V.

................

Display ONloFF control

Entry mode set

......

..............

DL=1

8 bit long interface data

N =0

I-line display

F -0

5 x 7 dot character font

D =0

Display OFF

e =0

Cursor OFF

B =0

Blink OFF

I/D=I: +1 (increment)
5 =0 : No shift

(Note)

When conditions in "Power Supply Conditions Using Internal Reset
Cl,rcuit" are not met, the internal reset circuit with not operate
norma11~

and initialization will not be performed.

In this case

initialize by MPU according to "Initializing by Instruction" •

• 1NSTRUCT ION .·;r
• Outl ine
Onl~

two HD44780 registers, the Instruction Register (IR) and the Data

Register (DR) can be directly controlled by the HPU.

Prior to inteFnal

operation start, control information is temporarily stored in these registers, to allow interface from HD44780 internal operation to various types
of HPUs which operate in different speeds or to allow interface to peripheral control ICs.

HD44780 internal operation is determined by signals

sent from the MPU.

These signals include register selection signals (RS},

read/write signals (R/W) and data bus signals (DBO - DB7),
instructions, here.
time.

and are called

Tabl:e 5 shows the instructions and their execution

Details are explained in subsequent sections.

Instructions are of 4 types, those that,
(1)

Designate HD44780 functions such as display format, data length, etc.

(2)

Give internal RAM addresses.

(3)

Perform data transfer with internal RAM

(4)

Others

In normal use, category (3) instructions are used most frequently.

However,

automatic incrementing by +1 (or decrementing by -1) of HD44780 internal
RAM addresses after each data write lessens the MPU program load.

The dis-

play shift is especially able to perform concurrently with display data
write, enabling the user to develop systems in minimum time with maximum
programing efficiency.

For an explanation of the shift function in its

relation to display, see Table 7.
When an instruction is executing during internal operation, no instruction
ocher than the busy flag/address read instruction will be executed.
Because the busy flag is set to "1" while an instruction is being executed,
check to make sure it is on "1" before sending an instruction from the MPU.

(Note)

Make sure the HD44780 is not in the busy state (BFcO) before
ing the instruction from the MPU to the HD44780.

sen~

If the inst

:!on is sent without checking the busy flAg, the time between
first and next instruttions is much longer than the instruction
time.

See Table 5 for a list of each instruction execution time.

Table 5 Instructions
..
Code
Instruccion
RS RIW jo B7 DB6 DBS DB4 DB) DB2 OBI DBO
Clear
DlSplay

Return
Home

0

0

0

0

0

0

0

0

0

0

0

a

0

0

0

0

0

1

Description

1

Clears encire display and sets
DO RAM address 0 in address
counter.

1.64_

*

Sets DO RAM address 0 in adress
counter. Also returns dis~lay
being shifted to original
position. DO lAM contents
remain unchanged.

1.64_

Sets cursor mOve direction and
specifies shift of display.
These operations are performed
during data write and read.

40lls

'.
Entry
Hode Set

0

0

Display
ONIOFF
Control

0

0

Cursor or
Display
Shift

0

Function
Set

0

0

0

0

0

1

lID

, IExecu~io-~~-(_x)
(",hen' fcp or
fosc is 2SOkHz)

S

Sets ONIOFF of entire display
and
B (D). cursor ONloFF (C).
blink of cursor position
character (B).

0

0

a

0

0

{)

0

o.

1

0

0

0

0

I

DL

Set ce RAM
Address

0

0

0

I

Set DO RAM
Address

0

0

1

Read
Busy Flag
& Address

0

1

BF

Write Data
to ce or
DO RAM

1

0

Write Data

Writes data into DO lAM or
ce RAM.

40\.lS

Read Data
from CC or
DO RAM

1

0

Read Data

Reads data from DO RAM or
CC 1Wf.

40\.ls

-

I/O-I
110-0
S -1
S/C-l

sIc-a

R/L-l
RIL-O
DL -1
N -l
F -1
BF -1

BF -0

I

:
:
:
:
:
:
:
:
:
:
:
:

1

0

SIC R/L

N

F

C

'"
'"

'"

Moves cursor and shifts displa}t
",ithout changing DO RAM
·contents.

'"

Sets interface data le.gth
number of display lines (L)
and character font (F).

40us

4<>Us

(DL)'r

4~s

Sets CC lAM address. ce RAM
data is sent and received
after this setting.

4~s

ADD

Sets DO RAM address. DO RAM
data is sent and received after
this setting.

40lJs

AC

Reads Busy flag (BF) indicating
internal operation is being
performed and reads address
counter contents.

<>us

ACC

Increment
Decrement
Accompanies display shift.
Display shift
Cursor move
Shift to the right.
Shifts to the left.
8 bits. DL-O : 4 bits.
2 lines. N-O : 1 line
S)(lO dots. F-O : 5)(7 dots
Internally operating
Can accept ins t ruction

DO RAM :

ce RAM
Acc
ADD
AC

~isplay

data lAM

----

...

_--

Execution time

: Character generator RAM changes when
frequency changes.
: CC RAM address

: DO RAM address.

Corresponds to cursor
address.
: Address counter used
for both DD and ce IWf
address.

(Example)
\ When fcp or fosc
is 270kHz:
40\.ls )( 250 _ 37\:5
270

Description of Details
(1)

Clear Display
RS R/w D B 7 - - - - -_ _ _ _-- DBa
Code
Writes space code "20" (hexadecimal) (character pattern for character
code "20" must be blank pattern) into all DD RAM-addresses.
RAM address a in address counter.
status if it was shifted.

Sets DD

Returns display to its original

In other words, the display disappears and

the cursor or blink go to the left edge of the dispaly (the first
line if 2 lines are displayed).
Mode.
(2)

Set liD = 1 (Increment Mode) of Entry

S of Entry Mode doesn't change.

Return Home
RS R/w DB7 - - - - - - - - - - - DBa
Code

-I a 1 a 1

0

1

0

1

0 [ 0

1

0

1

0 [ 0

1* I

Sets the DD RAM address 0 in address counter.
original status if it was shifted.

*

Don't care

Returns display to its

DD RAM contents do not change.

The cursor or blink go to the left edge of the display (the first
line if 2 lines are displayed).
(3)

Entry Mode Set
RS R/w DB7 - - - - - - - - - - - DBO
Code
liD:

I I I I I
0

0

0

0

0

0

0

I

0 I/DI

S

I

Increments (1/D=I) or decrements (1/D=O) the DD RAM address by 1
when a character code is written into or read from the DD RAM.
The cursor or blink moves to the right when incremented by 1 and
to the left when decremented by 1.

The same applies to writing

and reading of CG RAM.
S

Shifts the entire display either to the right or to the left
when S is 1; to the left when I/D=l and to the right when I/D=O.
Thus it looks as if the cursor stands still and the display moves.
The display does not shift when reading from the DD RAM when
writing into or reading out from the CG RAM does it shift when
S=O.

· l4)

Display ON/OFf Control
RS R/W DB7
Code
D

0 [ 0 [ 0 [ 0

_

I I
0

0 11

DB6

I I I I
0

C

B

The display is ON when 0=1 and OFF when 0=0.
D=O, display data remains in the DD RAM.

When off due to

It can be displayed

immediately by setting 0=1.

'c

The cursor displays when C=l and does not display when C=O.
Even if the cursor disappears, the function of I/O, etc. does
not change during display data write.

The cursor is displayed

using 5 dots in the 8th line when the 5 x 7 dot characteF font
is selected and 5 dots in the 11th line when the 5

x

10 dot

character font is selected.
B

The character indicated by the cursor blinks when B=l.

The

blink is displayed by switching between all blank dots and
di~'play

characters at 409.6ms interval when fcp or fosc=2S0kMz.

The cursor and the blink can be set to display simultaneously.
(The blink frequency changes according to the reciprocal of fcp
250
or fosc. 409-.6 x 270 = 379. 2ms when fcp=270kHz.)

! I

Cursor____

5 x 7 dot character
font

5 x 10 dot character
font

(a) Cursor Display Example
(5)

Alternating display

(b) Blink Display Example

Cursor or Display Shift
RS R/W DB7 - - - - - - - - - - - - DBO
Code

*

Don't care

Shifts cursor position or display to the right or left without writing
or reading display data.
for the display.

This function' is used to correct or search

In a 2-line display, the cursor moves to the 2nd

line when it passes the 40th digit of the 1st line.

Notice that the

1st and 2nd line displays will shift at the same time.

When the dis-

played data is shifted repeatedly each line only moves horizontally.

sIc

R/L

0

0

Shifts the cursor position to the left.
(AC is decremented by one.)

0

1

SAifts the cursor position to the right.
(AC is incremented by one.)

1

0

Shifts the entire display to the left.
follows the display shift.

1

Shifts the p~tire display to the right.
follows the display shift.

The cursor

:r ':c'"

The cursor

Address counter (AC) contents do not change if the only action performed is shift display.
(6)

Function Set
RS R/W DB7 - - - - -_ _ _ _-- DBO
Code
DL:

I I I I I I I I I* I*
0

0

0

0

1

DL

N

F

Data~is

Sets interface data length.

*

(Don't care)

sent or received in 8 bit

lengths (DB7 - DBO) when DL=l and in 4 bit lengths (DB7 - DB4)
when DL=O.
When the 4 bit length is selected, data must be sent or received
twice.
N

Sets number of display lines.

F

Sets character font.
(Note) Perform the function at the head of the program before
executing all instructions (except "Busy flag/address
read"). From this point, the function set instruction
cannot be executed unless the interface data length is
change~.

Character
font

Duty
factor

NF

No. of
display lines

0 0

1

5 x 7 dots

1/8

0 1

1

5 xlO dots

1/11

*

2

5 x 7 dots

1/16

1

*

(Don~t

care)

Remarks

Cannot display 2 lines with
5 x 10 dot character font.

(7)

Set CG RAM Address
RS R/W DB7 - - - - - - - - - - - DBO
Code

o

o

r0

1

A

A

A

A

A

A

,j

'~Hlgher

Order Bits

Lower
~
Order Bits

Sets the CG RAM address into the address counter in

bina~y

AAAAAA.

Data is then written or read from the MPU for the CG RAM.
(8)

Set DO RAM Address
RS R/W DB] - - - -_ _ _ _ _-- OBO
Code

o

o

1

[AIA[A[A[AL~(AI
Lower
Order Bits

+Higher
Order Bits

~

Sets the-DO RAM address into the address counter in binary AAAAAAA.
Data is then written or read from the MPU for the DO RAM.
However. when N=O (l-line display). MAAAAA is "00" - "4F" (hexadecimal).
when N=l (2-line display), MAAAAA is "00" - "27" (hexadecimal)
for the first line, and "40" - "67" (hexadecimal) for the
second line.
(9)

Read Busy Flag and Address
RS R/W OB7 - - -_ _ _ _ _-----OBO
Code

o [1

I I
BF

A [ A

I

A

+Higher
Order Bits

A

Lower
-to
Order Bits

Reads the busy flag (BF) that indicates the system is now internally
operating by a previously received instruction.
internal operation is in progress.
accepted until BF is set to "0".

BF=l indicates that

The next instruction will not be
Check the BF status before the

next wire operation.
At the same time, the value of the address counter expressed in binary
AAAAAAA is read out.

The address counter is used by both CG and DO

RAM addresses, and its value is determined by the previous instruction.
Address contents are the same as in Items (7) and (8).

(10)

Write Oata to CG or 00 RAM
RS

Code

R!W OH7

OBO

o

1

o
Lower
....
Order Bits

+Higher
. 'rder Bi ts

Writes binary 8 bit data DDDDDDDD to the CG or the DD RAM.
Whether the CG or DO RAM is to be written into is determined by the
previous specification of CG RAM or DD RAM address setting.

After

write, the address is automatically incremented or decremented by 1
according to entry mode.

The entry mode also determines display

shift.

(11)

Read Data from CG or DO RAM
(

RS R!W DB7

Code

DBO

I I I I

1

1

D

D

D

Lower
Order Bits

+Higher
Order Bits

~

Reads binary 8 bit data DDDDDDDD from the CG or DD RAM.
The previous designation determines whether the CG or DD RAM is to be
read.

Before entering the read instruction, you must execute either

the CG RAM or DD RAM address set instruction.
first read data will be invalidated.

If you don't, the

When serially executing the

"read" instruction, the next address data is normally read from the
second read.

The "address set" iristruction need not be executed just

before the "read" instruction when shifting the cursor by cursor
shift instruction (when reading out DD RAM).

The cursor shift in

struction operation is the same as that of the DD RAM's address set
instruction.
After a read, the entry mode automatically increases or decreases the
address by 1.

However, display shift is not executed no matter what

the entry mode is.
(Note)

The address counter (AC) is automatically incremented or
decremented by 1 after "write" instructions to either CG
or DD RAM.

RAM data sele<;.ted by the AC cannot then be read

out even if "read" instructions ar~ executed.
for correct data read
;'>, ,,~

,

R!\

yut

The conditions

ar:::e:. execut:e either t;l1e address set

. Insttii~tfon of" ~b'tior"shl'ft"'TrlSt'ruc'ri'oil loiily wifh DD RAM),
just before reading out execute the "read" instruction from
the second time the "read" inst ruct 10n is ser ial.

• HOW TO USE THE HD447BO
• Interface to MPU
(1)

Interface to 8-bit MPU
RS

...-J/

\~-----

R,.IW ' _ _ _ _

E

Internal
DB,

~

No

Data

'PII/4 Busy W///ABusyW///0.Bus f7lZ);i
y

Instruction
_. Write

BUS)l Flag Busy Flag
Check
CReck

Fig_ 5 Example of

Q)

l

Internal Operation

Bus~

I,

Data

~

Busy Flag Instruction
Check
Write

Flag Check Timing Sequence

When connecting t08-bit MPU through PIA
Fig. 6-2 is an example of using a PIA or I/O port (for single chip
microcomputer) as an interface device.

Input and output of the

device is TTL compatible.
In the example, P80 to PB7 are connected to the data buses DBO to
DB7 and PAO to PA2 are connected to E. R/W and RS respectively .
.
Pay attention to the timing relation between E and other signals
when reading or writing data and using PIA as an inteFface.

All
AI.
Au

HD08800

AI
A.
RAY

VMA
sit
DB.-DB,

D8

CS ,
CS I
CS.
RS I
M.
IVW
E

PA,

RS

PAl

IVW

PAt

E

I II

COM I COM' I

UDU180
SF:G 1 SEGu

HD68Boo
PB.-rB,

e

40

Connected
to Liquid
Crystal
Display

DOo-UU,

0 0 -0,

HD68BOO: 8 bit CPU

Fi Q. 6

€~alT1p.l e

of J,",t~rf~.ce . tp

H()6~~OOtJ$ina

PlA.{ H06HH21 1



Connecting directly to the 8-bit MPH bus line

VMA

¢ •.

Au

.
..

IIDa800

'

1\

V.-

Q)

L

1Connected

HlH~180

~

R/W
J)flo -nu 1

SEG,
-SEGn

"'-~---

~9_

,

8

1.o";"'AT

- ---

"'

I

u

" "'o-in:h

COM,
1---7"--COM ..

E

Co
-C,

--

C.

®

Connected
to LCD.

ns

SEG,
-SEGn

R/W

..,

~

Example of interfacing to the HD630l

PH
Pu

RS

PH

E

COM.
-COM ••

Mv

la

-

Connected
to LCD.

110 .... ,80
1I0ea 01

J

8

1I0~"'80

IlDa 8 0 ~

.

Example of interfacing to the HD6805

I
I

1a

."".',"

Ri'W

no ..... OT

COM.
-COM ••

E

p. o
-PIT

~

"8

DBo-DB,

.. 0

SEG,
-SEGn

,L

(2)

Interface to 4-bit MPU
The HD44780 can be connected to a 4-bit MPU through the 4-bit MPU I/O
port.

If the I/O port has enough bits, data can be transferred in

8-bit lengths, but ,tf.~hebits are insufficient', the transfer is made

.i.Il, ~wo operations of 4btt~' ea c::'h , (with designation -of interface data
length for 4 bits).
somewhat complex.

In the latter case, the timing sequence becomes
(See Fig. 7)

Fig. 8 shows an example of interface to the HMCS43C.
Note that 2 cycles are needed for the busy flag check as well as the
data transfer.

4-bit operation is selected by program.

RS

____--.J/
E

,;..--------.
IInternal
.1...__________

Internal
DB,

\~-------....J

Operatl.on

No

~Busy\~Busy~
Instruction
Write
(Note)

IR7, IR3:
AC3

I

Busy Flag
Check

I

Busy Flag IInstruction
Check
Write

Instruction 7th bit, 3rd bit
Address Counter 3rd bit

Fig. 7 An Example of 4-bit Data Transfer Timing Sequence

RS

D ..

HMes
ue

DI4

RAY

Du

E

COM.COM ••

Ie

HDH780
40

4

Rlo-R"

HMCS43C:

DB.-DB,

Connected
to Liquid
Crystal
Display

SEG 1 SEG ..

Hitachi 4-bit single-chip microcomputer

Fig_ 8 Example of Interface to the HMCS43C

Intertace

The voltages must be

Table 6 shows the relati'.on.

Duty Factor and Power Supply for Liquid Crystal Display
~y-Xacto)
!,ower~

Ye. X.

Supply

Drju-~

~
~

VI

vcc -

".

Y.V LCD

vcc -

~

Vz

vcc -

~VLCD

vcc -

"V LCD

VJ

vcc -

~VLCD

vcc -

"VLCD

Vc

vce -

Yc VLCD

vce -

~vLeD

Vs

vcc -

VLCD

vec -

V LCD

VLCD

VLCD gives the peak values for liquid crystal display drive waveforms .

.-

Resistance dividing provides each voltage as shown in Fig. 13.

----

Vcc ( +SV )

--.,---

-

Vcc

Vcc
R

VI

/.

V..

1/4 Bias
(1/8, 1/11 Duty)

R

Vs

-

:;- VR

-SV
(a)

R
R

V3

R

Vs

R

V2

R

V..

~R

VI

R

V2 h
V3 W

~-.,..

._'-

/

., VR

-')V
(b)

1/5 Bias
(k/16 Duty)

Fig. 13 Drive Voltage Supply Example

• Relation between Oscillation Frequency and liquid Crystal Display Frame
Frequency
.The following examples of liquid crystal display frame frequency apply
only when oscillation frequency is 250kHz.

~400 clock

z

1

Vee
V,
COM,
VI (V, )
V.
V,

I

frame = 4

I

I
I'

I

(2 )

a

I

1------1

+

x 400 x 8

=

1

12.8

= 12800

I

1

I

2

'1

(~s)

= 12.8 (ms)

(ms)

1/11 Du t y
~

Vee
CCN,

M

v.
v,

400 clock

%

I

v,

VI(V. )

I
,.
I

IaI

1------1

+

IIII I

1

11

I

2

I

II

1

1 frame

1 frame = 4 (\Js) x 400 xl! = 17600
1

Frame frequency = 17.6 (ms)
(3)

8

= 4~s)

III I !

II II I
1 frame

(~s)

Frame frequency

I

(1 clock

=

(~s)

= 17.6 (ms)

56.8 (Hz)

1/16 Duty
/-:-- 200 clock

aN,

Vee
V,
VI
V,
V.

v,

rll

2

I

I

+

1- -- -- -I

10

I

I

I

2

I

r

I

(~s)

1

L

1------

1 frame = 4

3

1 frame

x 200 x 16 = 12800
1

(~s)

Frame frequency = 12.8 ems) = 78.1 (Hz)

= 12.8 (ms)

• Connection with Driver lSI HD44100H
You can increase the number of display digits by externally connecting a
liquid crystal display driver LSI HD44100H to the HD44780.
When connected to the HD44780, the
driver.

HD~4l00H

is used as segment signal

The HD44l00H can be connected to the HD44780 directly since it

Ysupplies CLI, CL2, M and D signals and power for liquid crystal displa~
drive.
Caution:

Fig. 14 shows a connection example.
Connection of voltage supply terminals VI through V6 for liquid

crystal display drive is complicated.
Up to 9 units of the HD44100H can be connected for I-line display (duty
factor 1/8 or 1/11) and up to 4 units for the 2-1ine display (duty factor
1/16).
digits.

RAM size limits the HD44780 to a maximum of 80 character display
The connection method in Fig. 14 remains unchanged for both

I-line and 2-line display or both 5 x; and 5 xlO dot character fonts.

~---------------------------------------.

..

-----------------,y~----

I

eoMs-coMs.

Dot Matrix Liquid Crystal Display Panel

( eOM.-COMJ

.0

D

.0

.0

HDuIOOH
HD44100H
~~~------~--~
r--~------~--~
1
Y. o DR.
~-----------f DL. Y - - Y•• DRa i - - - - - f DL. Y 1 - -

HD4A100H

r------- _

r--

~

-

~'''''."

.

DL Y1

res

SHL.
SHLt

~
e L. 1---------t---4-+t-l+H-I-++++-----t---4-++--f--H-HH-H-+_- - - - e La .--------f---+f-l+H-H-++-+---.;..+--"+--f--H-HH-H-+_- - - - -

_+----J

j'

--,il---..J

M .--------f----4-1+H-H-++-+---+---4---f--H-HH-H-+_- - - - - --.tl----..J

vcc

I--------f----~+H-'+++-+---+---......-H+J~H-+_-- -

- -

-10-----

',,,,

G N D . - - - - - - - - - 4 - - - - -.....H--+++-+---.....-----+-l+-f-+++-- - - - - - - ' - - - V, 1---------------i+-t-Y-+------------t-+--+-4-~- - - - - - - - - VJ ! - - - - - - - - - - - - - H - - 4 -......- - - - - - - - - l - + -..............- - - - - - - - - - - -

~ ~-------------~-----------~~---------------

Fig. 14

Example of Connecting HD44l00H to HD44780

",~

-

• Instruction and Display Correspondence
(1)

8-bit operation, 8-digit x I-line display (using internal reset)
Table 7 shows an example of 8-bit

x

I-line disp1ay in 8-bit operation.

The H044780 functions must be set by Function Set prior to display .
.~i~et.~_~e.displ~Y'data RAM tin store data for 80 characters, as explained before, the RAM can be used for

d1sp1a~s

like the lightening

board when combined with display shift operation.
Since the display shift operation changes

displa~

position only and

DO RAM contents remain unchanged, display data entered first can be
output when the return home operation is performed.
(2)

4-bit operation, 8-digit x I-line display (using internal reset)
The program must set functions prior to 4-bit operation.
shows an example.

Table 8

When power is turned on, 8-bit operation is auto-

matically selected and the first write is performed as an 8-bit
operation.
required.

Since nothing is connected to DBa- - OB3, a rewrite is then
However, since one operation is completed in two accesses

of 4-bit operation, a rewrite is needed as a function (see Table 8).
Thus, OB4 - OB7 of the function set is writ ten twice.
(3}

8-bit operation, 8-digit x 2-1ine display
For 2-line display, the cursor automatically moves from the first to
the second line after the 40th digit of the 1st line has been written.
Thus, if there are only 8 characters in the first line. the OD RAM
address must again be set after the 8th character is completed.
(See Table 9)

Note that the first and second lines of the display

shift are performed.

In the example, the display shift is performed

when the cursor is on the second line.

However. if shift operation

is performed when the cursor is on the first line, both the first and
second lines move together.

When you repeat the shift, the display

of the second line will not move to the first line. the same display
will only move within each line many times.
(Note)

When using the internal reset, the conditions in "Power
Supply Condition Using Internal Reset Circuit" must be
satisfied.
instructioQ.

If not, the H044780 must be initialized by
(See "Initializing by Instruction")

Table 7 8-Mt Operation. 8-digit 1-1ine Display Example(Usin9 Internal Reset}
No.
:~:'

Power supply ON (HD44780
is initialized by the
internal reset circuit)

1
[

,,-

Operation

Display

Instruction

I

I

Initialized.
appears.

"-, !~f~

"

.,

,

SC:l..b

Function Set
RS R/W DB7
0 0 0 0 1

-

2

0

1

0

Display ON/OFF Control
0 0 0 0 0 0 1 1

3

'":.\ ~"4'

I

_DBa-

I-

0

'ii';C/;"ii'

,,..

to 8-0;'(

0~"'.:3c10n

J

I

Turns on display and cursore Entire display is
in space mode because of
initia1t'zation.

I

to i"ncr ement the
address by one and to
shift the cursor to the
right at the time of write
to the DD/Ce RAM.
Display is not shifted.
Se;:~)Jlode

.'

Entry Mode Set
0 0 o ·'0 0 0

4

0

1

1

1-

0

,",

5

Write Data to CG RAM/DD RAM
1 0 0 1 0 0 1 0 0 0

IH

I

Write "H". The DD RAM has
already been selected by
initialization when the
power is turned on.
The cursor is incremented
by one and shifted to the
right.

6

Write Data to CG RAM/DD RAM
1 0 0 1 0 0 1 0 0 1

IH I_

I

Writes "I".

I

Writes "I" •

IHITACHI

I

Sets mode for display
shift at the time of
write.

I

i

··
··

7

·

····

·

8

Write Data to ce RAM/DD RAM
1 0 0 1 0 0 1 0 0 1

9

Entry Mode Set
0 0 0 0 0 0

1

1

1

10

Write Data to ce RAM/DD RAM
1 0 0 0 1 0 0 0 0 0

IITACHI

11

Write Data to ce RAM/DO RAM
1 0 0 1 0 0 1 1 0 1

ITACHI

12
,

C',

0

IHITACHI

,

,..

"
.~

"'

'.

.

,

···

~: -~'i' ~~

•

'""'I"

.

'~.'

,-,;

···

,,".

=,

Writes ''M'' •

M..

.

~.

",

",

Writes "Space" •

-.,',

,',

"'

~.~ ~

..J'

,

.:~~:.~

and selects I-line display
lines and character font.
(Number of display lines
and character fonts cannot
be changed hereafter.)

'" '"

1

No display'

13

14

Write Data to CG RAM/DO RAM
1 0 0 1 0 0 1 1 1 1
Cursor or Display Shift
0

. 1--•.

is . .

0

0

0

0

1

0

r""'-"H:":"-#~' o,-,,"',,"'.,-':"",.......,~-:~-'""- ~

.,

0

* *

, .. q.,.,

Cursor or Dispf£t~ Shift
0

0

0

0

0

1

0

0

* *

16

Write Data to CG RAM/DO RAM
1 0 0 1 0 0 0 0 1 1

17

Cursor or Display Shift
0 0 0 0 0 1 1 1

18
19

Cursor or Display Shift
0

0

0

0

0

1

0

1

* *

Write Data to CG RAM/DO RAM
1

0

0

1

-- 0

0

1

1

0

1

···

. -20

21

* *

J

·

Return H<>me
0

0

0

0

0

0

0

1

0

Writes "0" .

)

Shifts only the cursor
position to the left.

t

Shifts only the cursor
position to the left.

I

Wri.tes "c" (correction).
The display moves to the
left.

IMICROCO

I

Shifts the display and
cursor position to the
right.

IMICROCO

I

Shifts display and cursor
position to the right.

IICROCOM

~

Writes ''M'' •

IMICROKO
;.,.,

".. ".

IMICROKO

IICROC,2

···
··
·

~

0

IMICROKO]

I!!.ITACHI

-

r

Returns both display and
cursor to the original
position (Address 0).

Table 8 4-l>it Operation, a-digit l-line Display Example
(Using Internal Reset)
.,

Instruction

No.
...

1

Power supply ON (HD44780
is initialized by the
internal reset circuit)

Display

I

-,

.--, ... ]

0

0

0

0

1

0

IpH

~; ~

...

..

appears.

Function Set
2 RS R/W DB7-- DB4

I

Operation

I

I

Sets to 4-bit operation.
In this case, operation is
handled as 8 bits by initialization, and only this
instruction completes with
one write.

"'.~,-

Sets 4-bit operation and
selects l-line display and
5x7 dot character font.
3

4

5

6

Function Set
0 0 0 0 1
0 0 00.0 *

0

*

Display ON/OFF Control
0 0 0 0 0 0
0 0 1 1 1 0

Entry Mode Set
0 0 0 0 0 0
0 0 0 1 1 0

Write Data to CG RAM/DD RAM
1 0 0 1 0 0
1 0 1 0 0 0

I

I

I-

I-

Ur-~

_t1o:;

.. -

•

from this point on and
resetting is needed.
(Number of display lines
and character fonts cannot
be changed hereafter.)

I

Turns on display and cursore Entire display is in
space mode because of initialization.

I

Sets mode to increment the
address by one and to
shift the cursor to the
right, at the time of
write, to the DD/CG RAM.
Display is not shifted.

I

Writes "H".
The cursor is incremented
by one and shifts to the
right.

-

IH_

4 . ·~J.'

Hereafter, control is the same as 8-bit operation.

Table 9 8 bit Operation, 8-digit
(Usin9 Internal Reset)
No.

Instruction

Display

. Power supply ON (HD44780
is intialized by the
;" ·i";qnte'tnal~rese't cIrcuit).'

"~~.::

t ;.

Functiqn Set
2 RS R/W DB1
0 0 0 0 1

I

,i···.

3

DBO
1

1

0

Display ON/OFF Control
0 0 0 0 0 0 1 1

* *
1

Entry Mode Set
0 0 0 0 0 0

0

1

1

0

I

I

0

-

4

2 line Display Example

x

._-

..

.. .
~-

Operation

I

Initialized.
appe,ars.

t

Sets to 8-bit operation
and selects 2-line display
and 5 x7 dot character font.

f

Turns on display and cursore All dlspla~ is 1n
space mode because of
initialization.

I

. Sets mode to increment the
address by one and to
shift the cursor to the
right, at the time of
write, to the DD/CG RAM.
Display is not shifted.

-

,

I

..
-

--

5

Write Data to CG RAM/DD RAM
0 0 1 0 0 1 0 0 0
I

IH

f

·
···
·

6

Write Data to CG RAM/DD RAM
0 0 1 0 0 1 0 0 1
I

8

Set DD RAM Address
0 0 I 1 0 0 0

9

Write Data co CG RAM/DD RAM
1 0 0 1 0 0 1 1 0 I

IHITACHI

IHITACHI
0

0

0

I:ITACHI

·
···

Write Data to CG RAM/DD RAM
0 0 1 0 0 1 I 1 1

"

-

~
1
1

Writes "I".
Sets RAM address so that
the cursor is positioned
at the head of the 2nd
line.
Writes ''M'' •

··

1

Entry, Mode Set
.12. ., ..., ,,'.'" .. ...... - .. . ,,'.-. t;···-

Writes "H". The DD RAM has
has already been sele.~ted
by initialization when
the power is turned on.
The cursor is incremented
by one and shifted to th~
right.

···

·
11

-

···
··

7

10

No display

....:.,

[HITACHI
(MICROCO
IHITACHI
•

•

•

•

,'"

•

1

'\

I
I

,1,

Writes "0" •
'.

Sets mode for display
of
' sh~ft .~t the time
..
·.• .• f\

-.

"

.

"

13

Write Data to CG RAM/DO RAM ,ITACRI
1 0 0 1 0 0 1 1 0 1
ICROCOM_

--'-

··
··
·

14

15

_._- --.'"
f<

0

0

0

0

0

·

-~."..

,

,

\_~--~--"i<~-~.,-~'~..

___.""'_

.f

···

Return Home
0

--.--

I

Writes ''M'' • Display is
shifted to the right.
The first and second
lines' shift are operated
at the same time.

0

0

1

0

rHITACHI 1
IMICROCOMl

Returns both display and
cursor to the original
position (Address 0) •

I

Initializin~

•

by Instruction

If the power supply conditions for correctly operating the internal reset
circuit are not met. initialization

b~

instruction is required.

Use the following procedure for initialization.

(

.

Power ON

)

Wait more than 15 ms
after Vee rises to 4.5V.

RS
0

J3.WIBr In m, I& IE. me m. lEo
0 0 0 1 1
* * * *

[

BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)

Wait more than 4.1 ms.

.-

RS I}wIBr m IE.
0

0

0

0

1

m. ms m. m lEo
1
* * * *

Wait for more than

RS
0

0

0

1

1

BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)

lOO~s.

lJ.woo, IE. m, Il\ 00, 00z 00. ~
0

[

* * * *

[

BF cannot be checked before this instruction.
Function set (Interface is 8 bits long.)

BF can be checked after the following instructions. When BF is not checked. the waiting
time between instructions is longer than the
execution instruction time. (See Table 4-1)
RS

I}w m, In 00. 00. 00. Dar DBa lEo

0

0

0

0

1

1

N F

* *

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

1

~

S

I
Initialization ends.

0

Function Set {Interface is 8 bits long.
Specifiy the number of display lines and
character font.}
The number of display lines and character font
cannot be changed afterwards.
Display OFF
Disp1.ay ON
Entry Mode Set

(2)

l

When interface is 4 bits long;

Wait more than 15 ms
,
after Vee rises to 4.5'1. i';
RS IJWlB1
0

0

0

m. m, lB.
0

1

1

Iwait more than 4.1 ms.

RS
0

[

Function set (Interface is 8 bits long.)

1

%rIB, 00. 00. ~
0

0

0

1

BF cannot be checked before this instruction.

1

[

BF cannot be checked before this instruction.
Function set (Interface is 8 bits

lon~.)

IWait fot' -more than 100].ls.1

RS ~00r
0

0

0

RS I}wDB,
0

m. 00, 00.
0

1

1

m. 00, 00.
0

1

0

0

1

0

0

0

0

0

0

0

0

N F

* *

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

!.1>s

[

BF cannot be checked before this instruction.
Function set (Interface is 8 bits length.)
BF can be checked after the following instructions. When BF is not checked, the waiting
time between instructions is longer than the
"execution instruction time. (See Table 4-1)
Function Set (Set interface to be 4 bits long.)
Interface.is 8 bits length.
Function Set (Interface is 4 bits long. Specif~
the" number of display lines and character font.)
The number of display lines and character font
cannot be changed afterwards.
Display OFF
Display ON
Entry Mode Set

Initialization ends.

HD44101H (DOT MATRIX LIQUID
CRYSTAL DISPLAY CONTROLLER & DRIVER)
The HD44101H is a dot matrix liquid crystal display controller & driver LSI
that displays alphanumerics, kana characters and symbols.

It drives dot

matrix liquid crystal display under 4-bit or 8-bit microcomputer or microprocessor control.

All the functions required for dot matrix liquid crystal

display drive are incorporated in one chip.

The user can realize the dot

matrix liquid crystal display system of less chip configuration by using the
HD4410lH .
The H044101H is produced in the CMOS process.

Therefore, the combination of

HD44l01H with a CMOS microcomputer or microprocessor can accomplish a portable
battery-drive device making the most of its lower power dissipation.

PIN ARRANGEMENT

SEGn
SEGZI
SEGZO
SEG1'
SEGll
SEG 17
SEGll
SEG"
SEG14
SEGU
SEG12
SEGl1
SEGII
SEG'
SEGI
SEG7
SEGI
SEGS
SEG4
SEGJ
SEGZ
SEGI

(FP·SO)

-~w~~~r~~~~b- SEGJ.
i

I

II
I
"

I
"-"-

SEG40
COMHO
DONn 4

DONn 3
COM1!
c::oMl1
c::oMlO
c::oM'

COMe

COM7
, CO....
COMI
COM4
c::oMS
COM!
c::oMl
De7

081
O8S
De4

~O

083
082

OOCI

Del

(Top View)

• FEATURES
· 5x7 dot matrix liquid crystal display controller & driver
• Interfaceable to 4-bit or 8-bit MPU.
• Display data RAM ••• 32x8 bits (32 characters, max.)
• Character generator ROM, ••• 6720 bits; 192 types of Sx7 dot character
font,

• Internal liquid crystal display driver ci rcuit
15 common signal drivers
40 segment signal drivers (can be externally extended to 120 segments
by the liquid crystal display driver HD44l00H)
~uty

factor (can be selected by a program)

1/7 duty

1 line of 5x7 dots

1/14 duty:

2 lines of Sx7 dots

• Maximum number of display columns
No. of
display
lines

Duty
factor

-"

1/7
duty

I-line
display

2-line
display

--

1/14
duty

Extension

HD44l0lH

No. of
display
characters

HD4l00H

8 characters
x 1 line

Not
provided

1 pc.

Provided

1 pc.

Not
provided

1 pc.

-----

8 characters
x 2 lines

Provided

1 pc.

1 pc. (8 characters
x 2 lines/pc.)

16 characters
x 2 lines

----"""

---

-3-pcs~---

(8 chdracters/pc.)

32 characters
x 1 line

· Various instruction functions
-

Clear Display, Return Home, Display ON/OFF, Display Shift
• Internal reset circuit at power ON
• Internal oscillator (with an external resistor)
· Low power dissipation
· Logic power supply:

A single +SV (excluding power for liquid crystal
disp"lay drive)

· CMOS process
· aD-pin flat plastic package (FP-80)

VCC
GNo
OSC1
OSC2

,.....

..

CS
R/W

8

---

.

E

.~~

,...

t)

::l

~
~

~

.~

,...

til

~

::l

oBO"oB6

)wer Supply
?r Liquid
:ys tal
splay Drive

V1
V2
V3

.7

i

.

•
•
•

V~

.

V6

,

t)

,...

::l

~

"""0
0

~

00

til

t)

itS

~

-

~

8

~

~

til

C1l '.-4

~

C1l

00
~

Q~

5

ITiming Generation
Circuit

t -'-

~

I

~

.,

\
I

RAM

Busy
Flag

L~c

~
~

'.-4

.c
CI) ,...

.

~

14
,

~

I

COMNo

00
..-4
CI)

J

c ,...

~

1

COM1-14

o ~
~ .~

..-4 til
.0..-4

CIO

[8

.~~

8

I

CL1

CL2

I

Display Data

~

"8

.
i

rL

...

3

M

t

(DD RAM)
32 x 8 bits

a,...

~

•

•

rr-

~

,.....

~

0

til

0

.~

8

~~

,...
~
~

oB7

c

c~

o~

RS

Address
~ Counter(AC)

r-i

8

Character
Generator
ROM
(CCROOM)
6720 bits
"5

ParaTIel/SeriaI Data
Conversion Circuit
I(Parallel Data-Serial Data)

C1l

c00

.c
t)
4,.1

C1l

...:I

40
~

40

...
0..-4

~~

C ,...

~

t)

I

.;ru

CI)

4,.1

4,.1..-4
..-4 ::l

.0

..-4

I

I

SEG1-40

~

~~
~ ...

CI)~

I:
40-bit Shift
Register

o

• ELECTRICAL CHARACTERISTICS

.Absolute Maximum Ratings
Item

Symbol

Unit

Limit

Note

-'

Power supply voltage (1)

VCC

-0.3 to +7.0'

Power supply voltage (2)

VI to V5

VCC-13.5 to VCC+O.3

V

Input voltage

VF

-0.3 to Vcc+D.3

V.

Operating temperature

Topr

-20 to +75

°c

Storage temperature

Tstg

-55 to +125

°c

.

,,,. Note 1:

"

-- --

..

V
3

..

If LSI's are used above absolute maximum ratings, they may be
permanently destroyed. Using them within electrical characteristic limits is strongly recommended for normal operation. Use
beyond 'these conditions will cause malfunction and poor reliability.

Note 2:

All voltage values are referenced to GND=OV.

Note 3:

Applies to VI to VS.

VCC~Vl~V2~V3~V4~V5.

Must maintain

(high _

_low)

• Electrical Characteristics
(VCC-SV±IO%, VS=Ov-SV, Ta=-20 to +75°C)

Item

Symbol

Input "high" voltage (1)

VIH(l)

Input "low" voltage (1)

VII(l)

Test
condition

-

Limit
Unit Note
Min. Type Max.

.

2.0

-

VCC

V

(2)

I

0

-

0.8

V

(2)

\

Output "high" voltage

(TTL) VOH

-IOH=0.205mA

2·.4

-

-

V

(3)

Output "low" voltage

(TTL) VOL

IOL-1.6mA

-

-

0.4

V

(3)

Output "high" voltage

(CMOS) VOHC

-IOH=O.lmA

VCC-0.4

-

-

V

(4)

Output "low" voltage

(CMOS) VOLC

IOL=O.lmA

-

-

0.4

V

(4)

Driver voltage des cending (COM) Vdl

Id-O.lmA

-

-

1.0

V

Driver voltage descending(SEG) Vd2

Id=O.OlmA

-

-

0.2

V

Input leakage current

IlL

Vin=O to VCC

-

1

lJA

Pu'll up MOS current

-Ip

VCc=SV,VIN""OV
T-a.-25°C

10

20

lJA

-1
2

,..

(5)

~

.'-

,'

.

,

.

.

.. .

• ; J... .. " ; ,',

,

Item
Power supply current

External clock operation
...:.:--- -

-

 ., ...~ .....

K

"

Test
Symbol
condition
Rf oscl.llatl.on.
External clock
ICC
operation
fosc=fcp=78kHz

--- -- --- -

'-r-- - -

.-

:..,';.

>."~"

LHnit

Min.

-

Unit Note

Type Max.
0.2

mA

0.5

-------r------r---

r- - - -

(6)

--

External clock frequency

fcp

40

78

150

kHz

(7)

External clock dut}!

Dut}!

45

50

55

%

(7)

External clock rise time

trcp

-

-

0.2

lJs

(7)

External clock fall time

tfcp

-

-

0.2

lJS

(7)

Input "high" voltage (2)

VIH2

VCC-l.O

VCC

V

(8)

Input "low" voltage

VIL2

0

-

l.0

V

(8)

(2)

Internal clock operation (Rf oscillation)
-CloCk -:s-:illatio:frequ:cy - r;:c-

Note 1:

-- -- - ..

TRf=560kru2%-l-s~ -17;-ltO~

\kH: ,-(9)

The following are I/O terminal configurations except for liquid
crystal display output.

• Input Terminal
Applicable terminals:

E

Applicable terminals:

RS. R/W. CS,

DBO to DB6

(No pull up MOS)
(With pull up MOS)

Vee

Vee

PMOS

PMOS

PMOS

NMOS
(Pull up MOS)
. Output Terminal
Applicable terminals:

CLI, CL2, M. D

NMOS

"I

• I/O- Terminals
Applicable terminals:
Vee (Pull

MOS)

DB7
up

Vee

PMOS

(Input Circuit)
PMOS

NMOS

PMOS

!====~- Da t a

NMOS

(Output Circuit)
(Three-state)
~e

2:

~Lld

Input terminals

I/O t.:.rminals

Excludes OSCI terminals.
Note·3:

I/O terminals

Note 4:

Output terminals

Note 5:

Current flowing through pull-up MOS's and output drive MOS's is
excluded.

Note 6:

Input/output current is excluded.

Wh~n

input is at the inter-

mediate level with CMOS, excessive current flows through the
input circuit to the power supply.

To avoid this, input level

must be fixed at high or low.
Note~:

External clock operation.
10scillator) ----40SCl

Open

---10SC2

0.1Vee --++0.5 Vee

---1+

0.3Vee

--1'-

trep

Dutv

tfep

Th

= Th +T.

x 100"

Note 8:

Applied to OSCI terminal.

Note 9:

Internal oscillator operation using oscillation resistor Rf.
,----10SC1

c •.•• ·

Rf

'----10SC2

Rf:

560k.Sl±2%

Since oscillation frequency varies depending on OSCI and OSC2
terminal capacity, wiring length for these terminals should be
minimized.

eTiming Characteristics
Write Op'eration

RS

)

Villi

VINI
VII.'

VIIo'J
I ....

161

\

l

VIL'

VIN'
VILI
I ••

VILI

~
h,

pw••

E

K

~,

VIN'
VaL'
t ....

~

VIN'I)
VILI

ivlL'

~

-

Valid Data

KVIN'
VILI

, .,. ..

Fig. 1 Bus Write Operation Sequence
(Writing Data from MPU to H044101H)

'~..

.

.

Read Operation

~

VIH'
VILt

VIH'
VILI

tAH

t",

~

K

~

'1

V,NI

... ~----,'

l\IHt
tAH

PW..

f--

"-'

E
VILI

t. P -

J

VIHI
VILI

I-- iDul

VIN1
~t.,

-K

"-,

,

V

VON)
1\
VOL

DB7

Valid Data

--

)
,.

KVON
VOL
.~--

t .r ••

Fig. 2 Bus Read Operation Sequence
(Reading out Data from HD44101H to MPU)
Interface Signal with Driver LSI HD44l00H

O.OYce

eLI
t C1rI.

..

-f-V 1LI

t DNI

f--

tCWII

tc.v

eLI

-.:.-

---

o.o~c

tcn

D

M

Fig. 3 Sending Data to Driver LSI HD44100H

eBus Timing Characteristics

(V CC =5.0V±10%, GND-OV. Ta--20 to +75°C)
Write Operation (Writing data from MPU to HD44101H)
i

'

.

Limit
Item

Symbol

Test conditions

Min.

Max.

Unit
ns

450

-

Fig. 1

-

25

ns

t AS

Fig. 1

140

-

ns

Address hold time

tAH

Fig. 1

10

ns

Data set-up time

tDSW

Fig. 1

195

-

ns

Data hold time

tH

Fig. 1

10

-

ns

Enable cycle time
"High"
level

Enable pulse width
Enable rise/fall time
Address set-up time

RS, R/W
-E

Tcyc E

Fig. 1

1000

PWEH

Fig. 1

, tEr, tEf

ns

Read Operation (Reading data from HD44l01H to MPU)
Item

Symbol

Test conditions

Limit
Min. Max.

Unit

tcycE

Fig. 2

1000

-

ns

PWEH

Fig. 2

450

-

ns

tEr. tEf

Fig. 2

-

25

ns

tAS

Fig. 2

140

-

ns

Address hold time

tAH

Fig. 2

10

-

ns

Data delay time

tDDR

Fig. 2

-

320

ns

Data hold time

tDHR

Fig. 2

20

-

ns

Enable cycle time
"High"
level

Enable pulse width
Enable rise/fall time
Address set-up time

RS. R/W
-E

elnterface Signal with HD44l00H Timing Characteristics
(VCC-5.0V±lO%. GND-OV. Ta--20 to +15°C)

.4

•

Limit

~

Item

Symbol

Test conditions

",

"High"
level
"High"
level

Clock pulse width

"

Min.

.

Max.

Unit

tCWH

Fig. 3

800

-,

ns

tCWL

Fig. 3

800

-

ns

Clock set-up time

tcsu

Fig. 3

500

-

ns

Oata set-up time

tsu

Fig. 3

300

-

ns

tOH

Fig. 3

300

-

ns

tOM

Fig. 3

-1000

1000

ns

Clock pulse width

hold time
;J2ata
;t.~::>
'I.,. .

M delay time

• Power Supply Conditions Using Internal Reset Circuit
"

-.

-

Item

Symbol

.

Test conditions

Limit
Min • Max.

Unit

'

Power supply rise time

trcc

-

0.1

Power supply OFF time

tOFF

-

1

-

10

ms

-

ms

Since the internal reset circuit will not operate normally unless the preceding ,conditions are met, initialize by instruction.

'" uv'
tree

O.lms ~. tree ~l 0 ms

(Note)

to,,*

torr

~

Ims

tOFF stipulates the time of power OFF for power supply instantaneous
dip or when power supply repeats ON and OFF.

,

i

.TERMINAl FUNCTION
Table 1 Functional Description of Terminals
Signal Numberhnputl
of
name
.lines output
RS
1
Input

Connected
to

Function
Signal to select registers

MPU

- "0": Instruction register (for write)
Busy flag (for read)
"1": Data register (for read and write)

R/w

Input

1

Signal to select read (R) and write (W)

MPU

"0": WTite
"1": Read
E

1

OB4
"'DB 7

4

Input

MPU

Operation start signal for data read/write

Input,

MPU

Higher order 4 lines data bus.
Used for data transfer between the MPU and
the H044l01H.
OB7 can be used as-a-BUSY flag.

1/0

only
OB7
OBO
"'DB 3

4

-Input

MPU

Lower order 4 lines data bus.
Used for data transfer from the MPU to the
H044l01H. These four are not used during
4-bit operation.

CLI

1

Output

H044l00H

Clock to latch serial data 0 sent to the
driver LSI H044l00H.

CL2

1

Output

H044100H

Clock to shift serial data

M

1

Output

H044l00H

Switch signal to convert liquid crystal
drive waveform to AC.

o

1

Output

H044l00H

Character pattern data corresponding to
each common signal is serially sent.

o.

"0": Non selection
"1": Selection
COMI
"'COM 14

14

Output

Liquid
crystal
display

Common signals that are not used are
changed to non-selection waveforms. That
is, COM&VCOMl4 are in non-selection waveform at 1/7 duty factor.

SEGI
"'SEG40

40

Output

Liquid
crystal
display

Segment signal

5

Power
supply

Power supply for liquid crystal display
drive

VCC'

2

Power
supply

VCC: +SV, GNO: OV

OSCl,
OSC2

2

COMND

1

GNO

Terminals connected to resistor for internal clock oscillation. For external clock
operation, the clock is input to OSCI.
Output
.'

...

Liquid
crystal
dis~la~

",',.

,~ ...: :~,":'

"',

~ ),:~,"~~.,

Non-selected common signal.
It is applied to unused common terminals
of LCD, if necessarv.

....' .: .

~.

,:: ~

~ .'

:-,.,"

·

Signal Number Input/
of
name
lines output
Input
1
cs

'~'''''''--.",

...,...-

.......,_.....~, ......... _'..,J! ... ;~: .. -•.", "'.'''''~',''' '_

Connected
to
MPU

Function
Chip select signal
"0": Disable
"1": Enable

.FUNCTION OF EACH BLOCK
(1)

Register
The HD44l0lH has two 8-bit registers, an instruction register (IR) and
a data register (DR).
The IR stores instruction codes such as display clear and display ON/OFF,
and address information for display data RAM (DO RAM).

The IR can be

written from the MPU, but can not be read.
The DR

t~~porarily

stores data to be written into the DO RAM.

Data

written into the DR from the MPU is automatically written into the DD

RAM by internal operation.

The DR can be also written from the MPU, but

can not be read. Register selector (RS) signals make their selection
from these two registers.

Table 2 Register Selection

(2)

RS

R/W

Operation

0

0

IR write as internal operation (Display clear, etc. )

0

I

Read busy flag (DB7)

I

0

DR write as internal operation (DR to DO RAM)

-

Busy flag (BF)
When the busy flag is "1", the HD44l0lH is in the internal operation
mode, and the next instruction will not be accepted.

As Table 2 shows,

the busy flag is output to DB7, when RS=O and R/W=l.

The next instruc-

tion must be written after ensuring that the busy flag is "0".
(3)

Address counter (AC)
The address counter (AC) assigns addresses to DD RAM.

When an instruc-

tion for address is written in IR, the address information is sent from
IR to AC.

After writing into DO RAM displax data, AC is automatically increased
by +1.
(4)

Display data RAM (DO RAM)
The display data RAM (DO RAM) stores display data represented in 8-bit
character codes.

Its capacity is 32x8 bits, or 32 characters.

Relations between DO RAM addresses and positions on the liquid crystal
display are snown below.
The DD RAM address (ADD) is set in the Address Counter (AC) and is
represented in hexadecimal.

-

Upper order
bits

Lower order
~
bits

~\~----------------~I

Hexadecimal

(Example)

DO RAM address "IE"

'-1.../ '\...--- E _____~I

I-line display (N-O)
(digit)
I-11ne

(a)

1

2

100 I 01

3

4

[ 02 1 03

31

5

32 ~ Dis~l~y
pos1t10n

lIE IlF

104 1

t-

DO RAM address

When the display' characters are less than 32, the display begins at
the head position.

For example, 8 characters using 1 HD44l01H are

displayed as:
( d i gi t)
I-11ne

1

2

3

100 I 01

[ 02

4

5

103 1 04

8 _

I071-

Display position
DD RAM address

When the display shift operation is performed, the DO RAM address
moves as:

(~~!~l:~~ft 101 I 02- [ 03 [ 04 1 05 106 107 1OS/
(~~~~.~~~~iftf ~F J00 L9; .1.Q2,l 03 .. 1<.q4 J.os ./061

(b)

l6-dharacter

displa~

using an HD44l01H and an HD44l00H is as shown

below:
(digit)

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 _ DisPilaiy
pos t on

I-line 10010110++++610+81091

LUD44l0lH display

O++++EIOF I-~~d:::s

--.1L H044100H

dbplay-1

When the display shift operation is performed, the DD RAM address
moves as:

(~~!~l:~~ft I 01102103104105106[07 t08 109 1OAI OB loci 00 10EIOF 110 I
(:~::~a;~iftllFI 00 I01102103104105106107 f 08 109 fOA lOB loci 00 IOE [
The relation between display position and DO RAM address when the
number of display digits is increased through the use of one
HD44l0lH and two or more HD44l00H's can be considered an extension
of (b).

Since the increase can be 8 digits for each additional HD44l00H,
up to 32 digits can be displayed by externally connecting 3
HD44l00H's.
(digit) 1 2 3 4 5 6 7 8 910 111213141516 17 18 19 a>
l-lire

25 26 27 28 29]) 31. 32-~~:l~~~n

~~O~04H~~OFllOl~~13[·· H~~lBl~~m~I-~~d=s
(Hexa-

~HD44780 ~'-HD44l00H(~~HD44l0H~'-H044l00H(~ decimal)
display

display

(2)
. display

display

• 2-line display (N-l)
(ciigit)

1

.2

3

4

5

I-line

00

01

02

03

04

2-line

10

11

12

13

14

(a)

....................
....................

Display
position

15

16 -

OE

OF· t- DD RAM address

IE

IF

When the number of display characters is less than l6x2 lines, the
2 lines from the head are displayed.

Note that the first line

address and the second line start address are not consecutive.
For example, when an HD4410lH is used, 8 characters x2 lines are
displayed as:

en~

(digit)

1

2

3

4

5

6

7

I-line

00

0'1

02

03

04

05

06

07

2-line

10

11

12

13

14

15

16

17

8 _ Oisp1ay pos i t ion
- 00 RAM address

Wheu display shift is performed, the 00 RAM

(Left shift
disp1ay)-

(Right shift
displa,-)

(b)

01

02

03

04

05

06

07

08

11

12

13

14

15

16

17

18

OF

00

01

02

03

04

05

06

IF

10

11

12

13

14

15

16

ad~-em.;

mov<"s

16 characters x 2 lines are displayed when an H04l.101H and

:IS:

~n

H044100H are used:

.-

I-line

_Display
position
_DO RAM
00 01 02 03 04 05 06 01 08 09 OA OB OC OD OE OF
address

2-1ine

10 11 12 13 14 15 16 17 18 19 1A 1B 1C 10 1E 1F

(digit)

1

L

2

3

4

5

6

.,

H044101H display

8

9 10 11 12 13 14 15 16

--1L H0441.0H diSP1ay ---.l

When disp1a){ shift is performed, the 00 RAM address moves as
follows:
(Left shift
display)

(Right shift
display)

(5)

01 02 03 04 05 06 (}7 08

~

OA OB OC 00 OE OF 00

11 .12 13 14 15 16 11 18 19 1A 18 1C 10 1E 1F 10
OF 00 01 02 03 04 05 06 07 08 09 OA OB OC 00 OE
IF 10 11 12 13 14 15 16 17 18 19 1A 18 1C 10 IE

Character generator ROM (CG ROM)
The character generator ROM generates 5x7 dot character patterns from
8-bit character codes.
patterns.

It can generate 192 types of 5x7 dot character

Table 3 shows the relation between character codes and

character patterns in the Hitachi standard H044101AOOH.

User defined

character patterns are also available by mask-programming ROM.

Table 3 Correspondence between Character Codes and Character Patterns
(Hitach; Standard HD441frlAOOH)

~~r
Lower
4blt
"bit

0010

0011 U1UO OIUI 0110 0111

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"

.._.•

:.:

•• ••
••
•••••
•• •• •• ••• • •••
••

-

"

"""

•

•••
••••
•

.

"
:::::
.....
••••••• ......
....
••••• :::::

(6)

Timing generation circuit
The timing generation circuit generates timing signals to operate
internal circuits such as DO RAM, CG ROM.

RAM read timing needed for

display and internal operation timing by MPU access are separately
generated sa they do not interfere with each other.

Therefore, when

writing data to the DO RAM, for example, there will be no undesirable
influence, such as flickering, in areas other than the display area.
This circuit also generates timing signals to operate the externally
connected driver LSI H044100H.
(7)

Liquid crystal display driver circuit
The liquid crystal display driver circuit consists of 14 common signal
drivers and 40 segment signal drivers.

When character font and number

of lines are selected by a program, the required common signal drivers
automaticaliy output drive waveforms, the other common signal drivers
continue to output non-selection waveforms.
The segment signal driver has essentially the same configuration as the
driver LSI HD44100H.

Character pattern data is sent serially through a

40-bit shift register and latched when all needed data has arrived.

The

latched data controls the driver for generating drive waveform outputs.
The serial data is sent to the HD44l00H, externally connected in cascade,
used for display digit number extension.
Send of serial data always starts at the display data character pattern
corresponding to the last address of the display data RAM (DD RAM).
Since serial data is latched when the display data character pattern,
corresponding to the starting address, enters the internal shift register, the HD4410lH drives the head display.

The rest displays, corres-

ponding to latter addresses, are added with each additional HD44l00H.
COMND always outputs non-selected common waveform.

This signal can be

applied to unused common lines in the LCD panel, if necessary, and all
the picture element on this common are not 'visible (see Fig. 10).

·RESET FUNCTION
The H044101H automatically initializes (resets) when power is turned on using
the

~ntemal

reset circuit.

The following instructions are executed in

:'.,

initialization. The busy flag (BF) is kept In busy state until initialization ends. The busy stats is 15 ms after Vee rises to 4.0V.
-tt"":

(1) . Display clear
(2)

Function set ••••••••••••••• DL=O:
N=O

(3)

Display ON/OFF control ••••• 0=0

(Not~,)

4 bit long interface data
I-line display
Display OFF
-

'When conditions 'in "Power Supply Conditions Using Internal Reset
Circuit-ar-e·'noL'-met, the internal reset circuit will not operate
normally and initialization will not be performed •

• INSTRUCTION •.
'eOutl ine
Only two HD44l0lH registers, the Instruction Register (IR) and the Data Register (DR) can be directly controlled by the MPU.

Prior to internal operation

start, control information is temporarily stored in these registers ,to allow,
"interface from HD44l0lH internal operation" to various types of MPUs which
operate in different speeds or to allow interface to peripheral control ICs.
HD44l0lH internal operation is determined by signals sentfroni the MPU.
These signals include regis.ter selection

signa~s

(RS), read/write signals

(R/W) and data bus signals. (DBO"-DB7), and are called instructions, here.
Table 4 shows the instructions. Details are explained in subsequent
sections.

Instructions are of 4 types, those that,

(1)

Designate HD44l01H functions such as display format, data length, etc.

(2)

Give internal RAM addresses.

(3)

Perform data transfer to internal RAM.

(4)

Others

In normal use, category (3) instructions are used most frequently.
auto~.atic

increasing

However,

by +1 ofHD4410lH internal RAM addresses after each

data,,$07rite lessens the MPU program load.

The display shift is especially

able to perform concurrently with display data write, enabling the user to
develop systems

in~tt}!I!'Yl!' ~!~e..\I!th ma~~.~t;'T_p~o~~a~ing e~~iciency. ,

For an explanation of the shift function 1n its relation to display, see
Table 6.
When an instruction is executing during internal operation, no instruction
other than the busy flag read instruction will be executed.
fl~g

.,t

o(~_,

Becau&e the busy

is se:FtD til" wh·ile an instruction is being executed, check to make sure

J.t is on "0" before sending an instruction from the MPU.

Table 4 Instructions
Code

Instruction

RS R/W DB7 DB6 DBS DB4 DB) DB2 OBl DBO
Clear
display

Return
home

0

0

-

0

-

0

0

0

0

0

0

0

0

0

0

0

0

0

Display
ON/OFF
control

0

0

0

0

0

0

1

0

Display
shift

0

0

0

0

0

1

1

R/L

Function
set

0

0

0

0

1

DL

N

Set DD RAM
address

0

0

1

0

0

Read busy
flag

0

1

Write data
to
DD RAM

1

0

BF

*

*

*

0

1

*

1

Clears entire display and
sets DD RAM address 0 in
address counter.

*

Sets DD RAM address 0 in
address counter. Also
returns display being
shifted to original position. DD RAM contents
remain unchanged.

*

*

*

(Write data}B

D-l: Display on
D=O: Display off
R/L-l: Shift to the right
R/L=O: Shift to the left
DL=l: 8 bits, OL-=O: 4 bits
N=l: 2 lines, N=O: 1 line
BF-I: Internally operating
BF-O: Can accept instruction

Sets ON/OFF of entire
display (D).

* *

Shifts display without
changing DD RAM contents.

*

Sets interface data
length (DL), number of
display lines (L).

*

Sets DD RAM address.
DD RAM data is received
after this setting.

(ADO)B .

*

Description

*

*

Reads busy flag (BF) indicating internal operation is being performed.
Writes data into DD RAM.
DD RAM: Display data RAM
ADD: DD RAM address
AC : Address counter used
for DD RAM address

eDescription of Details
(1)

Clear display
RS R/W DB7 - -

Code

I

0 [0 [0

- DBO

I I I I I I 11 I
0

0

0

0

0

0

Writes space code "20" (hexadecimal) (character pattern for character
code "20" must be blank pattern) into all DD RAM addresses.
address 0 in address counter.
it was shifted.
(2)

Returns display to its original status if

In other words, the display disappears.

Return home
RS R/W DB 7
Code

Sets

I

th_~

0

____

____ DBO

1 0 10 10 10 1 0 I 01

0 11

1.1

DD RAM address 0 in -address counter.

original status if it was shifted.
(3)

Sets DD RAM

*

Don't care.

Returns display to its

DD RAM contents do not change.

Display ON/OFF control
RS R/W DB7 -

Code

D:

II II II
0

0

0

0

0

0 [ 1

__

D~O

I I· I· I
D

The display is ON when 0-1 and OFF when D-O.
display data remains in the DD RAM.

When off due to D-O,

It can be displayed immediately

by setting 1>-1.
- (4)

Display shift
RS R/W DB7 Code

10 I0

I

0

1 0 10

-- DBO

11 11

IR/L I· I· I

*

Don't care.

Shifts display to the right or left without writing display data.
This function is used to correct or search for the display.
Notice that the 1st and 2nd line displays will shift at the same time.
When the displayed data is shifted repeatedly each line only moves
horizontally.

The 2nd line display does not shift into the 1st line

position.
R/L-O:

Shifts the entire display to the left.

Address counter (AC) contents do not change if the only action performed
is shift display.
(5)

Function set
RS R/w DB7

Code
DL:

II
0

0 [ 0

_-----~
_ _ _ _--

I

0

11

I I· I· [· I
DL [, N

Sets interface data length.
lengths·
DL-O.

(DB7~BO)

DBO

D-ata is sent

01'

*

Don't care.

received in 8 bit

when DL=l and in 4 bit lengths

(D8~4)

when

When the 4 bit length is selected, data must be sent

01'

received twice.
Sets numbel' of display lines.

N

N

No. of
display lines

Duty factor

0

.. 1

5x7 dots

1/7

1

2

5x7 dots

1/14

(Note)

(6)

Character font

.Perform the function at the head of the program before
executing all instructions (except "Busy flag/address
read"). From this point, the function set instruction
cannot be executed unless the interface d~ta length is
changed.

Set DD RAM address
RS R/W DB7

__ DBO

--.

Code
Lower order
~
bits

Higher order
bits

Set the DD RAM address into the address counter in binary AAAAA.
Data is then written from the MPU for the DD RAM.
However t when N=O (I-line display)

AAAAA is "00"

'V "IF"

(hexadecimal)

When N=l (2-line display). AAAAA 1s "00"

'V "OF"

(hexadecimal)

t

for the first line, and "10"
second line.

'V "IF"

(hexadecimal) for the

(7)

React busy flag
RS R/W DB 7
Code I 0

11

____

I" BF I

_

DBO

* I* [* [* I* [*1* I

Reads the busy flag (BF) that indicates the system is now internally
operating by a previously

recp.iv~

internal operation is in progress.
accepted until BF is set to "0".

The next instruction will not be
Check the BF status before the next

write operation.
(8)

Write data to DD RAM
RS

Code

11

R/W DB7 -

II
0

D CD

-

I

DBO

D

GG I G" I

Higher order
bits

D

D

I

Lower order
-.
bits

Writes binary 8 bit data DDDDDDDD to the DO RAM.
Where the DO RAM is to be written into is determined by the preV10US
specification of DD RAM address setting.
automatically increased by 1.

*

After write, the address is

5
5
Instruction cycle time - --- or--fOCS
fCp

.HOW TO USE THE HD44101H
.Interface to MPU
(1)

Interface to 8-bit MPU
RS

,'-------

---JI

R/W _ _ _ _
E

Internal
Internal Operation
DB 7

~

No

Data

'f(//////J Busy o////////J Busy~ BusyflIII);1

Instruction
Write

Busy Flag
Check

Busy Flag
Check

Busy Flag
Check

Dete

Instruction
Write

~

Direct interface to H06800
The HD44101H can interface directly to the 8-bit MPU HD6800, having
the capability of driving one ordinary TTL through the TTL compatible interface.

The interface timing is matched with the HD6800.

pO~'!1.,~~r,J,hq,..ij~H' s

internal operation is slow,. an access must

be made while checking the busy signal.
circuit.

o and

Fig. 5 shows an example of

In the example, the HD44100H is selected with AI4-1, A15=

the timing width is obtained by VMA and

~2.

HO 44101 H

HO 6800

RAY

.A1S

~:

COM

RS
CS
R/W

AO
A1

~

r\
lJ

;2

OBO-7

,~

14

,

~

COMND

LCD
40

SEG

,

~

E

OBO-7

Fig. 5 Example of Interface to HD6800

CD

When connecting to 8-bit HPU through PIA
Fig. 6 is an example of using a PIA or I/O port (for single chip
microcomputer) as an interface device.

Input and output of the

device is TTL compatible.
In the example, PBO to PB7 are connected to the data buses DBO to
DB7 and PAO to PAJ are connected to E, R/W, RS and CS respectively.
Pay attention to the timing relation between E and other signals
when reading or writing data and using PIA as an interface.

A ..
AI.
All
A,

HD68BOO

CSt

PAl

CS

CSt

PAl

R.S

CS.

PAl

Ra,

A.

as.

IVW

IVW

V}.lA

E

II.

COM.COM ..

IVW

"av

SEG.SEG ..

HD68B21

14

1

Connected

to liquid
; crystal

'. -' J

8

PB.-PB.,

DB.-D8.,

COMNO

DB.-DB.,

D.-D.,

HD68BOO: 8 bit CPU

Fig. 6 Example of Interface to H068BOO Using PIA (H068B21)

CD

Connecting directly to Lhe 8-bit MPU bus line

.VNA

flit

HD6800

Au
AI
A.

lJ

..... ,
Do-D

QD

1\

'8

COMND
COM,
-COM,.

E

~4

CS

RS HD44101H
R/W
DB.-D8,

SEG,
-SEG. o

Connect to
LCD
+2..

Example of interfacing to the HD6805

COMND
Ao-A.,

HD6805

,~

08.-08,

HD44101H

C.
C,

E
RS

C.

R,/W

C

CS

J

COM,
-COM,.

SEG,
-SEn..

14

·9
,

Connect to
LCD

Q)

1

Example of interfacing to thO!! HD6301

:>':'

R/W

P ae

E

"irph

lID630t
.

COMND

PH
Pu

RS

~~..

a

l··· '/'...\.

-PI?

l
·f •.,

14

COM.

-em" ••

CS HD44101H

COlhh.!Ct

DBo-DB,

"8

.0
SE~.

LCD

~

7

-SE0 40

(2}

"0

Interface to 4-bit MPU
The H044l01H can be connected to a 4-bit MPU through the 4-bit HPU I/O
If the I/O port has enough bits, data can be transferred in 8-bit

port.

lengths, but if the bits are insufficient, the transfer is made in two
operations of 4 bits each (with designation of interface data length for
4 bits;.

In the latter case, the timing sequence becomes somewhat com-

plex (see Fig.

7;.

Fig. 8 shows an example of interface to the HMCS43C.
Note that 2 cycles are needed for the busy flag check as well as the
data transfer.

4-bit operation is selected by program.

RS

\~-------

R/W _______________~/
E

I

Internal

Internal
Operation

I

I
No

No

DB7~BuSy~BUSY~
Instruction
Write

Note:

Busy Flag
Check

IR7, IR3:

Busy Flag
Check

Instruction
Write

Instruction 7th bit, 3rd bit

Fig. 7 An Example of 4-bit Data Transfer Timing Sequence

RS

0 ..

HMCS43C

0.4

RAY

0 ..

E

Il -

COM
CO

14
Connected to
Liquid Crystal
Display

14

Hula I. I \.: • .1

u
~

DB.-DB,

Rlo-R ..

SEC.SEC ..

COMND

HMCS43C:

Hitachi 4-bit single-chip microcomputer

Fig. 8 Example of Interface to the HMCS43C

,

_ Interface to-L i qui d--€rysta l~-{)isp lay
(1)

Character. font and number of lines
The HD44l0lH can perform 5x7 dots as character font.
Up to 2 lines are displayed with 5x7 dots.

Therefore, two types of

common signals are available:
Number of
lines

Character font

Number of
common signals

1

5x7 dots

7

1/7

2

5x7 dots

14

1/14

Duty
factor

-

Number of lines and font types can be selected by program.
(See Tablelr, Instruction.)
(2)

Connection to HD4410lH and liquid crystal display
Fig. 9 (l) and (2) show connection examples.

cow.
CON,

H044l01H

SEG,

-----------------------

SEG.

Liq uid Crystal
Dis play Panel
(8 characters
xl line)

Examp}e of a 5xl dot, 8 character x 1 line display (1/4 bias, 1/7 duty)

Fig. 9 (1)

Liquid Crystal Display and Connections to H044101H

COM,

·

COM,

COMa

·
OOMI4
.-

H044l01H.
SE~,

·

----------------------

SE0 4G

Liq uid Crystal
Dis play Panel
(8 characters
x2 lines)

Example of 5x7 dot, 8 character x2 line display (1/5 bias, 1/14 duty)

Fig. 9 (2)

Liquid Crystal Display and Connection to HD44101H

Since 5 signal lines at the SEG can display one digit, one HD44l0lH can
display up to 8 digits for I-line display and 16 digits for 2-line display.
In Fig. 9 (1) (2), there are unused common signal terminals, nonselection waveforms which always output.

When the liquid crystal dis-

play panel has unused extra scanning lines, avoid undesirable influences
due to cross-talk in the floating state by connecting the extra scanning

COM.

H044101H -:
00t.f7

COMNO

W

SE~.

.

.

.

----------------------

SEOto

5x7 dot, 8 character x 1 line display (1/4 bias, 1/7 duty)

Fig. 10 Using COMND to Avoid-tross-Talk on Unneeded Scanning Line
(3)

Connection of changed matrix layout
In the preceding examples, the number of lines was matched to the number
of scanning line&.

The following display types are possible by changing

the matrix layout in the liquid crystal display panel.

COM.

·

COM 7

H044101H
SEG.

----------

-

----------

·
· o
SEG.

·

CqM,

COM14

(a)

5x7 dot, 16 character xl line display (1/5 bias, 1/14 duty)

SEO,

·
SEG u

CON,

---------ti.'

"C

·

·7
CON
HD44101H

SEG II

----------

,
SEG 40

(b)

5x7 dot, 4 character x 2 line display (1/4 bias, 111 duty.)

Fig. 11

Changed Matrix Layout Displays

In either case, the only change is the layout.

Display. characteristics

and the number of liquid crystal display characters, are dependent on the
number of common signals (or duty factor).

Note that the display data

RAM (DD RAM) addresses for 8 characters x 2 lines and 16 character x 1 line
are the same as shown in Fig. 9 •

• Power Supply for Liquid Crystal Display Drive
Various voltage levels must be applied to HD44l0lH terminals VI to V5 to
obtain liquid crystal display drive waveforms.
according to duty factor.

The voltages must be changed

Table 5 shows the relation.

Table 5 Duty Factor and Power Supply for Liquid Crystal Display Drive
Duty factor

~

1/7

1/14

1/4

115

VI

VCC - l/4VLCD

VCC - 1/5VLCD

V2

VCC - 1/2VLCD

V3

VCC - 1/2VLCD

VCC - 2/5VLCD
VCC - 3/5VLCD

V4

VCC - 3/4VLCD
V("C'< - VT('n

Power supply

V5

VCC - 4/5VLCD
l.~ .... ",

-

". "'"" .

:.

VLCD gives the peak values for liquid crystal display drive waveforms.
Resistance dividing provides each voltage as shown in Fig. 12.

Vee(+ 5V)

Vee( + 5V)
Vee

Vee
I

~

>

R

'vI

V,
Va

1- R

V3
l- R

R

Vs

Vs
~VR

,.., ~.VR
-5V

-5V

(b)

1/4 bias (1/7 duty)

Fig. 12

R
R

R

(a)

R

V.

V.

~

R

V2

1.

V3 -.l

-

1/5 bias (1/14 duty)

Drive Voltage Supply Example

• Connection with Driver LSI HD44l00H
You can increase the number of display digits by externally connecting a
liquid crystal display driver LSI HD44l00H to the HD44l0lH.
When connected to the HD44l0lH, the HD44l00H is used as segment signal
driver.

The HD44101H can be connected to the HD44100H directly since it

supplies CLI, CL2, M and D signals and power for liquid crystal display
drive.
Caution:

Fig. 13 shows a connection example.
Connection of voltage supply terminals VI through v6 for liquid

crystal display drive is complicated.
Up to 3 units of the HD44100H can be connected for I-line display (duty factor 1/7) and up to I unit for the 2-line display (duty factor 1/14).
size limits the HD4410lH to a maximum of 32 character display digits.

RAM
The

connection method in Fig. 13 remains unchanged for both I-line and 2-line
display.

_..

CO~--COMI.

14

Dot Matrix Liquid
Crystal Display Panel

)

~~
SEC.-SEC••

~~

40

40

Y
D

DL.

•

--

..-- Fes
~
~

SHLt
SHLa

HD.UoOH
Y·· DRI

DLa
DR.

~ >C!J~
~~-=»......
»

0

CJO

t

eLi
eLI
M
Vee

ONE
VI
VJ
Vs

HD44101H

I

-~~

VEE

R

.

R ... 2200

Fig. 13 Example of Connecting H044100H to H044101H

.Instruction and Display Correspondence
(1)

8-bit operation. 8-digit x I-line display
Table 6 shows an example of 8-digit

X

I-line display in 8-bit operation.

The "044101" function"

J,."i':';.

<;et" prior to display.

Since the display data RAM can s tore data for 32 characters, ras eA'
plained before, the RAM can be used for displays like the lightening
boar
"

";

'f

:. J'~

:.

Display

Instruction

Operation

'/'

S!~

o0

DD RAM address
1 000 1 1 1 1

Write data to DD RAM
100 100 1 1 0 1

I MI
I

Writes the address of next to

t

C ROC 0
,. a

"0" .

Writes "M" • but "M" can' t
seen.

I

M I CR 0 C 0

)

,

be~'

~;:

"

-

Display shift
-0 0 000 1-1

n ...

...

Shifts left, "M" appears.

I M, I

C R 0 COM--I

,
I

I
I

I

I

I
R~~turn
x,;~'.

-

""

I

home

000 0 0 000 1 0

Table"7
. Instruction

IH I

-'

Display ON/OFF control·
RS Rtw DB7
DB4
0 O· 0 0
0 0
1 1 ... ...
0 0

-

Write data to DD RAM
1 00 1 0 0
1 0 1 0 0 0
,Hereafter,contr91 is
the same as 8-bit
operation.

S-digitxl-line Display
Operation

Display ..

..

Power ON and automatic
reset

I

T ACH I

4.;;.bitOperation~

Returns both display and DD RAM
address to the original position.

I

-

Initialized.
No display appears.

I
-

..

I

Display ON.
No display appears.

I

IH

-

Writes "H".

I
-

"

Table 8 8-bit OJ'eration. 8-digit)( 2 1 ines Display
Instruction

Display

Power on and automatic
reset

o0

0 0 1 1

Function set
000 OIl I

RSR/wm7 _ _ _ _ 000
Display ON/OFF control

**
...

Sets 8-bit operation and 2-line
displa)[.

I

- 1--

J

._.

Write data to DD RAM
I 0 0 I 0 0 L.O 0 1

I

I

I
I

Write data to DD RAM
I 0 0 I 0 0 I 0 0 I

IH

Set DD RAM address
0 I 0 0 I 0 0 0 0

IH

Write data to DD RAM

I:

o

0 I 1 0 1
I

I T ACH I

Writes "I".

1-

I T A CHI

J
I T A CHI

I

I

I

I

Write data to DD RAM

Sets DD RAM address to the top
of the second line.

I

Writes "M".
.

I~

I T A CHI
I C ROC 0

~

Writes "0".

I~

I T A CHI
I C ROC 0 Mf

Writes "M".

**

Ii

T A CHI
C ROC 0 M

*

I~

I T A CHI
I C ROC 0 MI

1 0 0 100 I 1 I 1
Write data to DD RAM
100 1 0 () I I 0 I
Display shift
0 0 0 I 1 0

Return home
000 0 0 0

Write "H".

I
I

I

o0

Display ON.
No display appears.

I

I

I

100 I

1

I

IH

I

o

I

This instruction is necessary
three times at 100 ms intervals.

I

***

0 0 000 1 1

I

Initialized.
No display appears.

....... ~-"

I

****

RSRMDB7 _ _ mO

o

I
,.I

Function set

Operation

o

0 1

I

Shifts left.
Both line will be shifted.
Returns display to the original
position.

HD44102CH (DOT MATRIX LIQUID CRYSTAL
GRAPHIC DISPLAY COLU~~ DRIVER)
:1'he HD4~lO?CH is a column (segment) driver for dot matrix liquid crystal
. graphic display systems, storing the display data transferred frem a

6~blt O~

8-bit microcomputer in the internal display RAM and generating dot matrix
liquid crystal driving signals.
Each bit data of dlspla, RAM corresponds to ON/OrF of each dot of liquid
crystal display to provide more flexible display.
The HD44102CH is produced in the CMOS process.

Therefore, the combination

with a CMOS microcomputer can accomplish a portable battery drive equipment
utilizing the liquid crystal display's lower power dissipation.
The combination of HD44l02CH with the row (common) driver HD44103CH facilitates dot matri! liquid

c~stal

graphic displaJ system configuration.

(FP-80)

PIN ARRANGEMENT

VEIl
v,

VI
V.I

v.

Vto

v,•

v.. .
v .. .

Y.
Y.

V47

v...
v..,
v...

.V,.

V.,
v.,

v ..

YII

v..,

Vu
'Yu

VIIO

YIS
v,,
-

-

-

•

-

•

-

••

:

_ :

I

t

_

• FEATURES
• Dot matrix liquid crystal graphic display column driver incorporating
display RAM.
lnterfaceable to
• RAM data

directl~

~>~

4~~_~

"c

~<'--,

.••
-,

'<

displayed by internal display RAM

RAM bit data "1"

ON

RAM bit data "0"

OFF

• Display RAM capacity ••••• 50 x 8 x 4 (1600 bits)
· Internal liquid crystal display driver circuit (segment output) .••••
50 segment signal drivers
· Duty·factor (can be controlled by external input waveform)
Selectable duty factors .•.•• 1/8, 1/12, 1/16, 1/24, 1/32
• Wide range of instruction functions
Display Data, Read/Write, Display ON/OFF, Set Address, Set Display
Start Page, Set UP/DOWN, Read Status
· Low power dissipation
• Power supplies ..••• Vee 5V±107., VEE
• CMOS process
• 80-pin flat plastic package

~5V

V_V.

VI V,

VI V, Va V.

RST----------------------,

Driver circuit (50 circuits)

as -----.

Display data
E/R~P/I

-----CL

FRM

o
1 Display Data RAM
2

3

Address
data
~I­

VIa-

M

Latch (50 circuits)

CSI-~a

~,-

t:::===:=...___

50X4x8 bit

BTABLE Of PIN ASSIGNMENT

Nn

Power IUPply, Clock

1
2
3
4
5
6
7
8
9
10

Input-

, ':c

(Note)

~~]:

.-

N. C.

Y17
Y16
Y15
YI4
Y13
YI2
Yll
Y10
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
YI

N.C.:

Nn

4L
•· • . i.

Y37
Y36
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
Y25
Y24
Y23
Y22
Y21
Y20
Y19
YI8

11

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

Output

Nonconnection pin

Power Supply? Clock
'.':.~,ir/,,~,

-.

71

72
73
74
75
76
77

78
79
80

Output

vee

~:-~

43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69_
70

Input
,

~

'K

~·;i~:c,,;·t

,

CSI
CS2
CS3
E

R/w
0/1
DBo
DB.
DBz
DB3
DB.
DB,
DB,
DB?

-.

-I

DBo
D~

DBz
D~

DB.
DB,
DB,
DBT

FRM
CL

N. C.

M
GND
VEE
V.
Vz
V3

V.
Y50
Y49
Y48
Y47
Y46
Y45
Y44
Y43
Y42
Y41
Y40

• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Supply voltage (l)

.'" Vt:t:.

"',1,.."'::".i, t~,\f"':~"~·' '; .~,'"

~,'....., -ftijitit"-'VO.'·
·'\·:.~ie:.''''''' 1)
. ~r. "'-Ii(J&\\;.'

--

Input voltage

-0.3

"(

'

,

(2)

,

.

"

"\.',.,

i:

•

Unit
+7.0

V

,~r'j/~_:,t.l.~2;~_ VCC+O• 3

V

VCC

Supply voltage (2)
..

Value

'"

Note
(l)

,

VTl

-0.3

VT2

VEE -0.3

Operating temperature

Topr

-20

Storage temperature

Tstg

-55

'"
'"
'"

VCc+O·3

V

(l) (2)

VCc+O·3

V

(3)

+15

°c

'"

+125

°c

Notel:

Referenced· to GND=O.

Note 2:

Applied to input terminals (except VI, V2, V3 and V4), and I/O
common terminals.

Note 3:

Applied to terminals VI, V2, V3 and V4 •

• ELECTRICAL CHARACTERISTICS
(VCC=+5V±10%, GND-OV, VEE=Q'\,-5.5V,
Item

.. -

Symbol

Ta=-2~75°C)

{Note 4}

Test condition

Min •

Typ

Max.
VCC

Input "High" voltage(CMOS)

VIHC

0.7xVCC

-

Input "Low" voltage (CMOS)

VILC

0

-

Input "High" voltage (TTL)

VIHT

2.0

Input "Low" voltage

VILT

-

{TTL}

.

0

!

Unit Note;
V

i

5 I

0.3 xVcc· V

5

VCC

V

6

+0.8

V

6

Output "High" voltage

VOH

IOH=-250lJA

+3.5

-

-

V

7

Output "Low" voltage

VOL

IOL =+1.6mA

-

-

+0.4

V

7

Xi-Xj ON resistance

RoN

VEE=-5V±10%, Load
current 100lJA

-

-

7.5

kf2

Input leakage current (1)

IILI

VIN=VC~ND

-1

-

1

lJA

8

Input leakage current {2}

IIL2

VIN=VCevVEE

-2

2

lJA

9

Operating frequency

FCLl<

$1 $2 frequency

25

-

250

kHz

10

-

-

100

lJA

11

-

-

500

lJA

12

Dissipation current

{l}

ICCI

Dissipation current

(2)

ICC2

Fc lk=200kHz frame=
65Hz during display
Access cycle lMHz
at access

I

I

Note 4:

Specified within this range unless otherwise noted.

Note 5:

Applied to M, FRH, CL, BS, RST, $1, $2.

Note 6:

Applied to eS1 to eS3, E, OIl, R/w and DBO to DB7.

Note 7:

Applied to DBO to DB7.

: /(' t.e 8:

to input terminals. 'f YRM, GL - ,B~; RST. '4>L 412,
E. 0/1 and R/W, and 1/0 common te rm in G:;;::
~}~7

Note 9:

Applied to VI, V2, V3 and V4.

~pplied

Note 10: $1 and $2 Ae characteristics.
Symbol

Min.

Typ

Max.

Unit

Duty

20

25

30

%

tf

-

-

100

ns

Rise time

tr

-

100

ns

Phase difference time

tl2

0.8

-

lJS

Phase difference time

t21

-

-

lJS

40

lJs

Duty
Fall time
-

..

------.~---

------

..

0.8

-

'PI + Th

1

Fcuc"' T1 +Th

O.SVcc

11

Duty -lj +Th x 100 (SIS)

tr

tf

Note 11:

Measured by Vec terminal at no output load, at 1/32 duty, and frame
frequency of 65Hz, in checker pattern display. Access from the CPU
is stopping.

Note 12:

Measured by Vec terminal at no output load, 1/32 duty and frame
frequency of 65Hz.

elNTERFACE AC CHARACTERISTICS
Note

Symbol

Min.

Typ

tcyC

1000

-

-

ns

13, 14

PWEH'

450

-

ns

13, 14

E low level width

PWEL

450

-

-

ns

13, 14

E rise time

tr

-

-

25

ns

13, 14

E fall time

tf

-

25

ns

13, 14

Address setup time

tAS

140

-

-

ns

13, 14

Address hold time

tAB

10

-

-

ns

13, 14

Data setup time

tDSW

200

-

ns

13

Data delay time

tDDR

-

-

320

ns

14, 15

Data hold ti'me at write

tDHW

10

-

ns

13

Data hold time at read

tDHR

20

-

-

ns

14

Item
E c)!cle time

.go, hJ gh ,lev~ 1
,

. ,". "

: I~~

~

-:'

""'~

Note 13:

,,,,ft.

."'. . . . .

wid.tl~

...

'lie.. ~g',..

,

;.,.;

~w

4

"'

>J

Note 14:

At CPU write

~------~~======~

Max.

Unit

..-

At CPU read

i-----

tcYc~=====J

Pwm.--t-- PM2C - -

E

tf

tr

t.ut~,---

FVW
CS I _

2.0V

0/1

cs~

O.8V r-----..,...---4F-4

0/1

tosw
UN
O.4V~_ _..JI

O.8V /'"----..11

Note 15:

DBO to DB7 load circuits
RL '" 2.4kQ

Test point o-___~I-__+

R '" 11kO
C - 130pF (including jig capacity)
Diodes D1 to D4 are all lS2074 ®

Note 16:

Display OFF at initial power up.
The HD4410201 can be placed in the display OFF state by setting
terminal RST to "LOW" at initial power up.
No instruction other than the Read Status cannot be accepted while
the RST is in the "Low" level.
Min •. Typ
Reset time

tRST

Rise time

tr

- -

M~ •.

.; .,"~~ijt,

-

lJs

200

ns

1.0

"~"

O.1\b:

RST

• TERMINAL FUNCTIONS DESCRIPTION
Signal Number of
name
terminals
Yl~Y50

50

.

I/O
0

Func'tion

. Liquid crystal display drive output.
Relationship among output level, Mand display data
(D) :
M

J

D

J1 I

Output level

CSI"VCS3

3

I

1

I

VI .,. V3'" Vz

-I-

0

r

0
0

r

V•• ,

-

CS2

CS3

State

J:.

L
L
H
H
L
L
H
H

L
H

Non-selected
Non-selected
Non-selected
Selected read/write enable
Selected write enable only
Selected write enable only
Selected write enable only
Selected read/write enable

L
H

H
H
H

I

I
I

CSI

L

1

I.

Chip select

L

E

1

L

H
L
H
L
H

Enable
At write (R/W-L):
At read

(R/W-H) :

Data of DBO to DB7 is latched
at the fall of E.
Data appears at DBO to DB7
while E is in "High" level.

.

..

~.'~

Signal Number of
name
terminals
R/W

I

1

1

DII
...

III

l.

l

,"

Read/Write
Data appears at DBD to DB7 and can be read
by the CPU when E-H and CS2/CS3-"H".
DBD to DB7 can accept input when CS2/CS3=H
or CSl-H •

.\:
..
t1p{t!
. . ; ; Data/Instruction
.'. '
",'

..

Indicates that the data of DBD to DB? is
display data.
Indicates that the data of BOO to DBl is
display control data.

D/I-H:

.'

0/1-1.:

DBD'\J)B7'

8

~

Function

R/W-L:

\_~

"

I/O

R/W-H:

"'

."

I/O

Data bus, Three-state I/O conunon terminal
E

R/W

H

H
L
L

*
*

CSl

CS2

*H H
*
H
*
Others

CS3
H

*

H

State of DBD to DB7
Output state
Input state,
High impedance
High impedance

_.
M

1

1

Signal to conveFt liquid crystal display drive
output to AC

CL

1

I

Display synchronous signal

.

At the rise of CL signal, the liquid crystal display drive signal corresponding to display data
appears.
FRM

1

I

Display synchronous signal (frame signal)
This signal presets the S-bit display line counter
and synchronizes a common signal with the frame
timing when the FRM signal becomes high .

.
$1, $2

2

I

2-phase clock signal for internal operation
The $1 and $2 clocks are used to perform the
operations (input/output of display data and execution of instructions) other than display.

RST

1

I

Reset signal
The display disappears and Y address counter is set
in the UP counter state by setting the RST signal
to "Low" level. After releasing reset, the display OFF state and up mode is held until the state
is changed by the instruction.

BS

1

I

Bus select signal
BS-L:
BS=H:

DBD to DB7 operate in 8-bit len~th.
DB4 to DB7 are valid in 4-bit length only.
8-bit data is accessed twice in the high
and low order.

Signal . Number of
name
terminals

Function

1/0

Vl,V2,
:.V3, V4

4

Power supply for liquid crystal display drive.
VI and V2 : Selection voltage
V3 and V4 : Non-selection voltage

Vee
'GND
VEE

3

Power supply.
.

,.

~ "f.'-~-8\' .\,-,~.

Vee-GND':
Vee-VEE:

'

.

Power supply for internal logic
Power supply for liquid crystal display
drive circuit logic

• FUNCTION OF EACH BLOCK
• Interface Logic
The HD44l02CH can use the data bus in 4-bit or 8-bit word length to enable
the interface to a 4-bit or 8-bit epu.
(1)

4-bit mode (BS=H)
8-bit data is transferred twice for every 4 bits through the data bus
when the BS signal is high •. The data bus uses the high order 4 bits
(DB4 to DB7).

First, the high order 4 bits (DB4 to DB7 in 8-bit data

length) is transferred and then the low order 4 bits (DBO to DB3 in 8bit data length).
BuSY

Flag

0/1
R/W

E

-.J

I

L

to.----I

J

oBT

~ X,"

Y3 B B t s y .

OB6

%I lJ/D W!fJj

Xo

Y%

DB 5 ~OFf~W.

Y5

'ff/JIJ.

Yt

_

oB4 ~

Y.

'fIf/lJ.

Yo

~Resct_

m

8

03

~

0%

~

Ot

~

D. . . . Do

~

0

1

U/O _

Do

OFf.·~ . . .

05

Busy flag Add re ss
Add ress _rUS Yk flag
h k
cec
- d
- hec
(S
high or er low order(
tatus
write
write
Status
read)
I
read)

Data
high
order
write

"

'W/J.
'ff/IJ..

Data low
order write

(Note}

(2)

Execute the instructions other than Status Read in 4-blt length each.
The busy flag is set at the fall of the second E signal. The Status
Read is executed once. After the execution of the Status Read, the
first 4 bits are considered the high order 4 bits. Therefore, if the
busy flag is checked after the transfer of the high order 4 bits,
retransfer data from the higher order bits. No busy check is required
in the transfer between the high and low order bits.

8-bit mode (as=L)
If the as signal is low, the 8 data buses (DBO to DB7) are used for data
transfer.
DB7

MSB (Most significant bit)

D:sC>

LSB (Least signtficant bit)

For AC timing, refer to (Note 12) to (Note IS) of "ELECTRICAL CHARACTERISTICS" .

• Input Register
8-bit data is written into this register by the CPU.

The instruction and

display data are distinguished by the 8-bit data and D/I signal and then a
given operation is performed.

Data is received at the fall of E signal when

the CS is in the select state and R/W is write state •

• Output Register
The output register holds the data read from the display data RAM.

After

display data is read, the display data at the address now indicated is set in
this output register.

After that, the

addres~

is increased or decreased by 1.

Therefore, when an address is set, the correct data doesn't appear at the
read of the first display data.

The data at a specified address appears at

the second read of data.

0/1
R/W

E

Address.
Output

N

N±I

N±2

::::::::::::::::::::::::::::::::~I~D=a:t=a::at::a=d=d:re:s:S::N:;I=Da:t=a::a=t=a=d;d=r=e=ss::N;±;l
Busy I Wri te I Busy
Read
Busy Read
I Busy
Data read

I

I

I

I

register--------------------------------~~=-~~~~~-L~~~----------

080-1

check aNddressr check

data
(dummy)

check data at! check
address
I

N

address
N±l

• x, Y Address

Counter

The X, Y address counter holds an address for reading/writing display data RAM.
An address is set in it by the instruction.
posed of a 50-bit UP/DOWN counter.

The Y address register is com-

The address is increased or decreased by

I by. the read/write operation of.display data.
'determined by the instruction or RST signal.
the values of 0 to 49 to count.
tion. __

The UP/DOWN mode can be
The Y address" register "loops

The X address register has no count func-

e Displ ay ON/OFF Fl i p Flop
\,tThis flip flop is set to ON/OFF state by the instruction or RST signal.

In

::'the OFF state, the latch of display data RAM output is held reset and the
display data output is set to O.

Therefore, display disappears.

In the ON

state, the display data appears according to the data in the RAM and is displayed~bELdisplay

data in the RAM is independent of the display ON/OFF.

eUP/DOWN Fl ip Flop
This flip flop determines the count mode of the Y address counter.
mode, the Y address register is increased by 1.
mode, the register is decreased by 1.

0 follows

49~.-!n

In the UP
the DOWN

0 is followed by 49.

e Di'splay Page Register
The display page register holds the 2-bit data that indicates a display start
page.

This value is preset to the high order 2 bits of the Z address counter

by the FRM signal.

This value indicates the value of the display RAM page

displayed at the top of the screen.

eBusy Flag
After the instruction other than Status Read is accepted, the busy flag is
set during its effective period, and reset when the instruction is not effective.

The value can be read out on DB7 by the Status Read instruction.

The HD44l02CH cannot accept any other instructions than the Status Read in
the busy state.
struction.

Make sure the busy flag is reset before the issue of in-

E

______~r_1~______________

B:SY <---.---<---2--~r===T.~Y~~----­
F
pen
M

t ----------t
V.

V50

'----.fFRM
L.---~M

H044102CH
L.----~CL

'------+4;.
CR

R

C

L.--_ _ _ _

~

;,

No.2

IIN1ERFACE TO CPU
(1)

Example of connection to HD6800

---

Decoder

A.,

{
A,
VMA

••

I
I
I
I

.,F CSt

~
~

cS z
Vc:c._ CS)

~

0/1

R/W

R/w
HD44102CH

H06800
E

~2

Do.

I

~

I
I
I

.

0,

~Vcc

.~

RES

DBo

)
08,

~

RS7

1
Example of Connection to HD6800 Series
In the decoder given in this example, the addresses of HD44l02CH in the
address space of HD6800 are:
Read/write of display data

$'FFFF'

Write of display instruction:

$'FFFE'

Read of status

$'FFFE'

Thus, the HD44102CH can be controlled by reading/writing data at these
addresses.

(2)

Example of connection to HD6801

14LS 154

P,o
P II
P,z
P,~

( IOS)SC1

Vo
V,

A

~...

-.-

..

B
I
I
I
..,'"
I
I
C
VIS ...!0
G, G z

,;""

=.

R/W

PM

0/1

E

;

..

P~,

I
I
I

OBo
DB,

.

i
I

I
I
I

I
I

Pn

H044102CH

No.1

E

PS)

(Data bus)

CSz

Vcc~ CS~

t.Jr

CR.IW)SC2

H06801

J;" CS,

I

De,
.,

• The HD6801 is set to mode 5.

P10~P14

are used as output ports, and

P30 ~P37are-used-as data buses.
• The 74LS154 is a 4-to-16 decoder that decodes 4 bits of

P10~P13

to

select the chips.
• Therefore, the HD44102CH can be controlled by selecting the chips
through P10 ~P13 and specifying the D/l signal through P14 in advance.
and later conducting memory Read ot Write for external memory space
($0100 to $01FF) of HD6801. . The lOS signal is output to SC1, and the
RIW signal is output to SC2.
• For further details on HD6800 and HD6801, refer to each manual.

.CONNECTION TO llQUlD CRYSTAL DISPLAY

..rt-

~

-?'

~

0 ...

Xl

Mill

,0

I
2

XI

1:_
u

···
•
·••

~

-U)


~

I
X Il

:I:

32 x 150 dots

21
22

•
I
I

~
_.

(a)

.b"

VI _____ V50

VI - - V , o

HO 44102CH
No.1

H044102CH
No.2

:I:_

~ ::~
~ o_
1:

XI
X2

______

2

) 15···

X"
X"

Liquid crystal display panel
16 x 100 dots

16

VI ---..--- v.
H044102CH
No.1

V50

H044102CH
No.3

I

t -------- f

(b)

VI

Example of connection of 1/32 duty, I-screen display

0 ...
Mill
Ou
t - -(I)

'--

---------

--------

_ _ _ _ _ _ _ 0_

1------- f
VI

~V50

H044102CH
No.2

Example of connection of 1/16 duty, I-screen display

H044102CH
1108

H044102CH

V................ Y",

V.""""'-- V'"

!'IGJ

HOHI02CH
110 10

.. ---._._-

v.--Veo

1------ !

!--------l· !--------l
1
2
i3

,
0
0
0

r0-

0

:r-

X. I -

... QI
o U

X~l r-;-

O s..

. - en

~~

,

J::)1!
I
~
o
..
'-

,•

:r- "'"

•

1

:,
,
,
,

lio

121
122

132

:r
XI tOQl XI ~
,

.., > I ,
~CII

Liqui.d crystal display panel

l!:li

64 x 240 dots

,

:: r-f Xu ~

0(1.)
I-

.
0

5;
!Ill

5~

:
B'4

r--------J
(c)

r--- ---.j

1--------1

V. _ _ _V'"

v.---v.

HOHI02CH
IIot

HO HI02CH
NIl2

VI_Yeo

-----------

H044102CH
NIlS

Example of connection of 1/32 duty, 2-screen display

HDlf4103CH (DOl MATRIX LIQUID CRYSTAL
GRAPH I C D~SPLA Y COMMON DRIVER)
The HD44103CH is a common signal driver fo·r
dot matrix liquid crystal graphic display
s~stems.

It generates the timing signals

required.for displaJ with its internal
oscillator and supplies them to the column
driver (HD44102CH) to control display, also
automaticall~

scanning the common signals

of the liquid crystal according to the
display duty.

It can select 5 types of

display duties ratio:
1/24 and 1/32.
provided, and

1/8, 1/12, 1/16,

20 driver output lines are
~he

(FP- 60)

impedance is low (SOOQ

max.) to enable a large screen to be driven •

• FEATURES

• Dot matrix liquid crystal graphic display common driver incorporating the
timing generation circuit in it.
• Internal oscillator (Oscillation frequency can be selected by attaching
an oscillation resistor and an oscillation capacity)
• Generates display timing signals.
• 20-bit bidirectional shift register for generating common signals
• 20 liquid crystal driver circuits with low output impedance
• Selectable display duty ratio:

1/8, 1/12, 1/16, 1/24, 1/32

• Low power dissipation
• Power supplies:

VCC •.• +SV±lO%, VEE ••• 0 to -S.SV

• CMOS process
• 60-pin plastic flat package

20 output terminals

VI V, Vs V.

Xl

t
vsuar I - -

X 2 --------- ----------------- ----:--- -- - X 18

t

•

t

X 19

t

Xr

19

20

~

Vee
GNO
VEE

Liquid crystal display
driver circuits

~

~

OL

u

1

'"000

r~

Bidirectional shift
register

2

u

18

'"00
3

OR
1.6- ~

.

SHL

M

Timing generation circuit

Oscillator

,---.
R~

,y
R(

Crf
/I

logic

C

05 1
M/S

CL

Fs

FRM

eTERMINAL ARRANGEMENl' LIST

NIl

-

Power supply, Clock

Input

Output

1
2
3

X 14
X 13
X 12
Xll
X 10
X9

4

5
6
7
8

N. C.
X8
X7
X6
X5

9

10
11

12
13
14
15
16
17
18
19

ro

,

.-

24
2S

26
27
28

29
30

(Note)

-N: C-.
N.C.
N.C.
N. C.

"-

~

X4
X3
X2
X1

VI

21
22
23

No.

..

N. C.
N. c.

Vz
V,
V.
VEE
OL
C
VSU8
R

DL

~

31
32
33
34
35
36
37
38
39
40
41
..42
43
44
45
46
47
48
49
50
51
52
53
54
S5
56
57
58

Connect to VCC.

N.C.: Unused terminal
Connect VSUB to VCC.

59
60

Power supply, Clock
CR

Input

~"

'.

Output

;.
~

GNO

.

....

-~.

.

-

FS
OSI
N. C.
N. C.
N. C.
OS2
OS3
M

-

r-- ..

M

FRM

SHL

Vee
N. C .
N. C.
N.C.
M/S
CL
N. C.
N. C.
N. C.
DR

-

CL

DR

X 20
X 19
X 18
X 17
X 16
X 15

. i.ABSOLUTE MAXIMuM RATINGS
Item

Symbol

Supply voltage (1)

Vee

Supply voltage (2)

Rated value

Unit.

Note

i{

+7.0

V

(1)

VEE

Vee- 13 • 5 '" VeC+<>·3

V

(14)

Terminal voltage (1)

VTl

-0.3-'" Vcc+O.3

V

(1) ,

Terminal voltage (2)

VT2

V

(3)

Operating.temperature

Topr

-20

Storage temperature

Tstg

-55

-0.3

VEE -0.3

'"

'" VeC+<>·3
'" +75
'" +125

(2)

°e
°e

Note 1:

Referenced to GND-O.

Note 2:

Applied to input terminals and I/O common terminals except VI, V2,
V3 and V4.

Note 3: Applied to terminals VI, V2, V3 and V4.
Note 14: Connect a protection resistor of 220n±5% to VEE power
supply in series •

• ELECTRICAL CHARACTERISTICS
(Vee=+5V±10%, GND-OV, VEE-O to -5.5V, Ta--20 to +75°e) (Note 4)
Item

Symbol

Test condition

Unit Note

Min.

Typ

Max.

-

Vee

V

( 5)

0.3 x Vee

V

(5 )

-

V

(6)

0.4

V

(6)

500

1'2

1

lJA

(7)

2

lJA

(8)

kHz

(9)

Input "high" voltage

VIH

0. 7xVee

Input "low" voltage

VIL

0

Output "high" voltage

VOH

IOH-- 4OO lJ A

Output "low" voltage

VOL

Vi-Xj ON resistance

RON

IOL-+4OO lJA
VEE--5V±10%,Load
current ± l50lJA

Input leakage current (1)

IILI

VIN-VeC"GND

-1

Input leakage current (2)

IIL2

VIN-Vec"'VEE

-2

-

Shift frequency

fSFT

In slave mode
Rf- 7OkSl2 % ,
ef-10pF:f-5%

-

-

50

300

430

560

kHz (10)

Osc~llation

frequency

fose

Vee-0 • 4

-

.

External clock operating
frequency

fcp

50

-

560

kHz

External clock duty

Duty

45

50

55

%

(~1

External clock rise time

trcp

-

50

ns

( 11)

External clock fall time

tfco·

-

-

50

ns

(11)

,,---

-.--.~. -'~ "

,

"

~

,

Symbol

Item
Dissipation current
(master)
Dissipation current
(slave)

Pwl
Pw2

Test condition

Min.

Typ

Max.

CR oscillation=
430kHz
Frame frequency
=70Hz

-

-

4.4

mW

(12)

-

-

1.1

mW

(13)

Note 4:

Specified within this range unless otherwise noted.

Note 5:

Applied to CR, FS, DSl to DS3, H, SHL, MIS, CL, DR and DL.

Note 6:

Applied to DL, DR, H, FRM, CL,

Note 7:

Applied to input terminals CR, FS, DSl to DS3, SHL and
common terminals Dt, DR, Hand CL at high impedance.

Note 8:

Applied to VI, V2, VS and V6.

Note 9:

Shift operation timing

~l

Unit Note

and tp2.

MIs,

and 1/0

0.7Vcc

DL/DR

0.3Vcc

min

typ

max

5
5

-

-

IlS

-

-

IlS

-

-

100
100

ns
ns

tsu

tsu
CL

0.7Vcc

tr

0.3Vcc

t(

tr

Note 10:

tH

-

unit

tr

Relationship between oscillation frequency and Rf/cf
CR oscillator
The values of Rf and Cf are typical values.
The oscillation frequency varies with the
mounting condition. Adjust oscillation
frequency to a required value.

"'---~R

C

Rf

,~cc-sv
~

500

Ta = +25"(;

""''' "'---~

400
(ose 300

~

(kHz I 200

~

C(= 6pF
C(= lOpF

100

50

100

150 (kfl)

Note 11:

9.7\k.c
O.5Voc
O.3Vcc

ul1y =:

t rep

-

Note 12:
Note 13:

trep

open

C

- open

R

External clock-

Th
lh+T1 '

CR

\

Measured by VCC terminal
Cf=10pF±5%, 1/32 duty in
Measured by VCC terminal
frequency of 70Hz in the

"-

at output non-load of Rf=70kQr2% and
the master mode.
at. output non-load, 1/32 duty, frame
slave mode.

• TERMINAL FUNCTIONS
Terminal Number of
name
terminals
Xl",X20

20

Function

I/O

o

Liquid crystal display driver output.
Relationship among output level, M and data (D) in
shift register.
_
M

J

D

J

Output
level
CR, R,
C

3

Oscillator

1

1

,. VI

I

0

I

0

I

I
v. -I-

j. Vo .,

Rf

1

r
0

r

V, .,

C(

~~
R

M

1

CR

C

CR oscillator

I/O 'Signal for cqn~~rtipg liquid crystal display driver
. signal into AC
Master:

Output terminal

Terminal Number of
name
terminals

I/O

CL

I/O

1

Function
Shift register shift clock.
Master:
Slave :

Output terminal
Input terminal

FRM

I

0

Frame signal, Display synchronous signal

00 1",DS 3

3

I

Display duty ratio select.
Displa)l
1/24
duty ratio
DSl
DS2
DS3

FS

1

I

L
L
L

1/12
H
L
L

L
H
L

X

1/31::

H
H
L

L
L
H

1/16
H
L
H

L
H
H

1/8
H
H
H

Frequency select.
The relationship between the frame frequency fFRM
and the oscillation frequency fOSC is as follows:
FS="H" :

_.

FS="L":

DL, DR

2

I/O

SHL

1

I

fOSC - 6144 x fFPM
fOSC "" 3072 x fFRM

...
...

(1)
(2)

Example 1)

When FS="H", adjust Rf and Cf so that
the oscillation frequency is approx.
430kHz if the frame frequency is 70Hz.

Example 2)

When FS="L", adjust Rf and Cf so that
the oscillation is approx. 215kHz, in
order to obtain the same display waveforms as Example 1. When compared with
Example 1, the power dissipation is
reduced because of the operation at
lower frequency. However, the operating
clocks ~1 and ~2 supplied to the column
driver have lower frequencies. There- .
fore, the access time bf the column
driver HD44102CH becomes longer.

Data I/O terminals of bidirectional shift register.
Shift direction select of bidirectional shift
register.
SHL
H
L

Shift direction
DL
DL

-+
+-

DR
DR

Terminal Number of
name
terminals

M/S

1

I/O
I

Function
Master/slave select.
M/S-"H": Master mode
The oscillator and timing generation circuit
operate to supply displ~y timing slgnals to
.J

output

...... :
p . ,. . ~_<::u

,

..

:...~'~

__ .~

st~te.

M/s="L": Slave mode
The timing generation circuit stops operating.
The oscillator is not required. Connect terminal CR to VCC' Open terminals C and R.
One (determined by SHL) of DL and DR, and
terminalsM and CL are placed in the input
state. Connect M, CL and one of DL and DR of
the master to the respective terminals.
Connect FD, DS1, DS2 and DS3 to VCC.
When ~::. .. :~' .~. 'lty =3H~ "s 1/8, 1/12 or ' /16, fI'1!"
HD44l03CH is required. Use it in the master mu, _.
When display duty ratio is 1/24 or 1/32, two
HD44l03CHs are required. Use the one in the master
mode to drive common signals I to 20, and the other
in the slave mode to drive common signals 21 to 24
(32). -



(Top View)

• FEATURES
• Dot matrix liquid crystal graphic display controller
• Display control capacity
,C":"aphic mod.e ...•..• 5l2K de

.~.

;,Character mode.; ••• 4096 .,laracrers (i:'-cha« c '-rs)
• Internal character generator ROM ..••• 7360 bits
160 types of 5x7 dot character fonts

Total 192 types

32 types of 5xll dot character fonts
{Can be extended to 256 types (4K bytes max.) by external ROM)
• Interfaceable to 8-bit MPU
• Display duty (Can be selected by a program)
Static to 1/128 duty selectable
• Various instruction functions
Scr()ll, Cursor ON/OFF/blink, Character blink, Bit manipulation
• Display method •..•. Selectable A or B types
• Internal oscillator (with external resistor and capacitor)
• Low power dissipation
• Power supply:

Single +5V

· CMOS process
• 60-pin flat plastic p'ackage

•

CD

r0
n

~CLI MAMBFLM

,-::

,
...--

='Cl.~
~

4J
.~

oBO .... oB7 --+-~

~ }--+-~

='
u
~

.~

u

C1.I

u

C1.I

8

...tv

'b

1'3...t~
~ OO~

C/)_

1'3 C1.I 0

...

~

C1.I

4J

-.

~
.~

-o -

Dot registers
(DR)

•

: •

I

oJ

.I I

8

V

,Line address
I counter

1

4J",

C1.I

4J
C/)

C

~

oo~

r--- -----,
Extended II
L..,J external I
I
I
I
ROM
I

I
I

4
Cha:-acter
generator
ROM (CGROM)

I
I

L..---T----.J
I
I

I

I

______ J I

ADO .... A07

Nult1plexer

I

.~ ~

lLO........- r_ _--J

:

1

Cursor
Mode
signal
control
generator
regis- ~
Control
ter
signal
(MCR)

-.-- \.oC/)_
=' 4J
(BF)

4J

r::!

t

.~

'"----'--- ~

Busy
flag

16
rL..t...
I -

8 L---._(_CA""!C_)_ - - J r+ ~ .---o+.-.......-t---A. ...;~---... Mo 0 .... Mo 7
!

5

RAM

Po.
...t

regis-~----------+-------~~~--~----------~

c
o

4

-

CUrBor edre..
counter

0

>
en

3:

,

16 X
~ ~

~

+

C1.I

Refre.h.ddrea.
counter (2)

8

Data
output
ter
(DOR)

~

(RACt)

(R.AC2)

t

-

O~-

1'3

ReLresh address 16
counter (1).
~--;:-

Dot counter
(DC)

4J

-WE

J

C1.I_
\.0

.--

Oscillator
circuit

Paralld/l
... rUl
rlo---d..----- -

02

.

coa".rter I

Cf

-H'"
CL2

~

Rf

CPO

* When

extended external ROM is L~~d MAO~MAll
are applied to RAM, MAl2~MAl5 are applied to
extended external ROM.

• HlUCK fUNCTlafS

eRegisters
The H061830 has the five types of registers:

instruct ion register (IR), data

input register (DIR), data output register (DOR), dot registers (DR) and Il..jle
control register (MGR).
The IR is a 4-bit register,whl.ch stores the- l.nstruction codes for specifying
MeR, DR, a start address register, a cursor address register and so on.

The

lower order 4 bits DBO to DB3 of data buses are written in it.
The DIR is an 8-bit register used to temporarily store the data written intO
the external RAM, DR, HeR and so on.
The DOR is an 8-bit register used to temporarily store the data read from the
external RAM.
DIR.

Cursor address information is written into the CAC through the

When the memory read instruction is set in the IR (latched at the
\

.

,

fall~

(

ing edge of E signal), the data of external RAM Is re-ad to DOR by an in tt;.;: ~':.\1 ~
operation..

The data is tr.ansferred to theMPU by reading the DOR with the

next instruction (the contents of DOR are output to the data bus when E is at
"High" level).
The DR are registers used to store the dot informations such as character
pitches ·and . the number of
the MPU is

wri~en

v~rtical

dots and so on.

The information sent .froln

into the DR via the DIR.

The MCR is a 6-bit register used ·to store the data which specifies states of
display such as display qN/OFF and cursor ON/OFF/blink.

The information sent

from the MPU is written in it via the DIR •

• Busy Flag (BF)
With "1", the busy flag indicates the H06l830 is performing an internal
operation.

The next·· instruction cannot be accepted.

As shown in Control

Instruction(14},the busy flag is output on DB7 under the conditions of RS-I,
R/W=l and E=l.

Make sure the busy flag is "0" before writing the next in-

struction •

• Dot Counters (DC)
The dot counters are counters that generate liquid crystal display timing
according to the contents of

D~.

• Refresh Address Counters (RAC1/RAC2)
The refresh address counters are counters used to control the addresses of
external RAM, having the two types:

RACl and RAC2.

upper half of screen and the RAC2 for lower half.

The RACl is used for
In the graphic mode, 16-

bit data is output and used as the address signal of external RAM. In the
.,,.
c.haracter mode, th~ high order It bits (MAl2ivMAl5) are ignored. The It bits

0' line address counter are output and used as the address of extended ROM •
• Character Generator ROM

The character generator ROM has 1360 bits in total and stores 192 types of
character data.

A character code (8 bits) from the external RAM and a line

code (4 bits) from the line address counter are applied to its address signals, and it outputs 5-bit dot data.
The character font is 5x7 (160 types)' or 5xl1 (32 types).

The use of ex-

tended ROM allows 8x16 (256 types max.) to be used •

• Cursor Address Counter
The cursor address counter is a 16-bit counter that can be preset by the
instruction.

It is used to hold an address when the data of external RAM is

read or written (when display dot data or a character code is read or written).
The value of cursor address counter is automatically increased after the
display data is read or written and after the Set/Clear Bit instruction is
executed •

• Cursor Signal Generator
The cursor can be displayed by the instruction in the character mode.

The

cursor is automatically generated on the display specified by the cursor
address and cursor position •

• Parallel/Serial Conversion
The parallel data sent from the external RAM, character generator ROM or
extended ROM is converted into serial data by two parallel/serial conversion
circuits and transferred to the liquid crystal driver circuits for upper
screen and lower screen simultaneously.

.TERMINAl fUNCT I ONS
Function

Name
;
:

...

Data bus
Three-state I/O common terminal
Data is transferred to MPU through DBO to DB7.

DBCh.7

,-

CS

Chip select:.

R/W

Read/Write

RS

Register select

E

Enable

CRt Rt C

CR oscillator

RES

Reset

...

. ... ,.

..,ith
.~.-\~

...

R/W=l
R/W=O

...

. ..

. ..
RS=l
RS=O

"

C$=O .

MPU+ H061830
MPU ..... HD61830

. ..
...

Instruction register
Data register

.

Data is written at the fall of E.
Data can be read while E is l.

...

Reset=O results in display OFF and slave mode.
-_...
... --.
External RAM address output

MAO "'15
0-

..".,"<

In character mode t the line code for external CG is output
through MA12 to MAlS ("0": Character 1st line,
"F": Character 16th line).

...

MDCh.7

Display data bus

RD'-"'~'.'-~"".'!F~~.

--,~.,.,...,.,.~".'

,.,

.ABSOLUTE MAXIMUM RATINGS
Item

Symbol

SupplX voltage
. ,

"~,,

:,;~:.;,:" ..~,.~:~:

.. ;.

,,' .r :.~;.:-f .
, ;::.. \",'~.

Value

i,~i~ ~ G,~;;~ ,
.;

,""'"''

.

~O. 3~,,+7
.0,
..,.,.r.".

r'

,v

(1)

V

(1)

'.~~'

Terminal voltage

'vT

~0.3

'"

VCC+0 .3

Operating temperature

Topr

-20

'"

+75

Storage temperature

Tstg

-55

'" +125

Note 1:

Note

Unit

°c
°c

All voltage is referenced to GND=O.

IECECTRICAL CHARACTER I STIeS
(VCC=5V±5%, GND==OV,

Ta=-2~75°C)

Item

Symbol Test condition

Unit Note

Min.

Typ

Max.

-

VCC

V

(2)

0.8

V

(3)

VCC

V

(4)

Input "High" voltage

(TTL)

VIH

2.2

Input "Low" voltage

(TTL)

VIL

0

Input "High" voltage

VIHR

3.0

Input "High" voltage (CMOS)

VIHC

0.7VCC

-

VCC

V

(5)

Input "Low" voltage

VILC

0

-

0.3Vcc

V

(5)

VCc-0.4

-

VCC

V

(6)

0

-

0.4

V

(6)

(CMOS)

Output "High" voltage (TTL)

VOH

-I OH=0.6mA

Output "Low" voltage

VOL

IOL =1.6mA

Output "High" voltage(CMOS)

VOHC

-IOH'=O .6mA

VCC-0.4

-

VCC

V

(7)

Output "Low" voltage (CMOS)

VOLC

IOL=0.6mA

0

-

0.4

V

(7)

Leakage current

lIN

VI N= (}'\,VCC

-5

-

5

UA

(8)

Output leakage current

lOUT

-10

-

10

.UA

(9)

Power dissipation (1)

Pwl

-

10

15

mW

(10)

Power dissipation (2)

Pw2

-

20

30

mW

(10)

(TTL)

Internal
clock operation
1----________________
Clock oscillation frequency

----

fosc

-

VOUT=()vVCC
CR oscillation
fosc=500kHz
External clock
fcp=lMHz

---------- ----1------- ------Cf=15pF±5%
Rf=39kn±2%

350

500

I

650

kHz (11)

Symbol Test condition

Item
External clock operation

f-- - - - - - - - - - - - - - - - - , - - - -

I,

External clock operating
frequency

Typ

--------- ---

,---

fcp

External clock duty
,. .-.fi-.,.;,-':d',~:,-,:.~

-

~

Duty"
,.':
.~

..

".~

"

.'
"

External clock rise time

,~ .:cp

External clock fall time

tfcp

Pull-up current

IpL

Note:

Min.

.,'.~~

......

,

VIN-GND

Max.
~--

Unit Note

- -- -r---

100

500

noo

47.5

50

52.5

kHz (12.)

.,,-

%

(IT)

(l-.:u5 ' ..

"., .
'i,j';;

-

0.05

lJs

(2)

10

20

lJA

(13)

•

-

-:-

2

l!

"

'

"- ' .

.
...;,

The I/O terminals are of the following configuration:

e Shape of Output Termi na 1

eShape of Input Terminal
,~pplicable

terminal:

CS, E,

~S,

Applicable terminal:

R/W,

, RES, RDO to RD7 ~ CR

CLI, CL2,

MA, MB, F:LM, COP, Dl, D2;'

WE,

MAu

MAl5
Vee

vee

~t--::-::
eShape of I/O Common Terminal
Applicable terminal:

DBOvDB7, SYNC,

~MD7

Enable

Vee
PMOS

J---.L...cC1==~-- 0 a ta

NMOS

Note 2:
Note 3:

Applied to input terminals and I/O common terminals, except terminals
SYNC, CR and RES.
Applied to input terminals and 1/0 common terminals, except terminal!
SYNC and CR.

RES.

Note 4:

Applied to terminal

Note 5:

Applied to terminals SYNC and tR.

, Notr.,

oe.

If', ,
.".;,,' ,

-..!i--

"

~

Note 7 :

Applied to terminals SYNC, CPO, FLM, CLl, CL2, Dl, D2, MA and MD.

Note 8:

Applied to input terminals.

Note 9:

Applied to I/O common terminals. However, the current which flows
into the output drive MOS~~}~.~.~lu¥cb/

. Note
~"

.

':~

.:-:

10: The current which flows intd the input and output circuits is excluded. When the input of CMOS is in the intermediate level, current
flows through the input circuit, resulting in the increase of power
supply current. To avoid this, input must be fixed at high or low.

"'-"'-'

The relationship between the operating frequency and the power dissipation
is given below •
.......
~

.....E

50

a..•
40
/"

30
/"

20
10

/'

"

./

o

~~

./

~

V

'/

7

~

~

l/

./

~

max

typ

~
250

500

750

1000

1250

1500

fosc(kHz)

Note 11:

Applied to the operation of internal oscillator when oscillation
resistor Rf and oscillation capacity Cf are used.

...-------l R

Rf

.----1'

C

Cf

=

Rf

= 391&

l5pF ± 5i± 2%

(when fosc =
500kHz typ)

' - - - - - 4 - - 4 CR

The relationship among oscillation frequency, Rf and Cf is given below.

fose (kHz)

Ta - 251; Vee· 5V

800~~\~--~--~---+---+--~--~--~

600 f---;-'
\f-'l\~-t-_-t-_-t---t---t---t----f;

\

Note 12:

"

Applied to external clock operation.
--...j--TI

Open

IA

Ope.l

C

100cillator~L..C_R

0.7Vcc---+t0.5Vee--It
O.3Vcc

*

11---J

_ __

tfcP

trcp

Note 13:

Applied to SYNC, DBOVDB7, and

R~RD7

Outy=

.

• TIMING CHARACTERISTICS
.Bus Read/Write Operation (Interface to MPU)
!4--------tcyC------1
...---tWEH

t----tWEI..

E

tEr

CS. R/W. RS

tosw

08 0 _

2.2V

(MPU -+ HO 61830)

O.8V

tH

tOH
tOOR

2.4V

080 ..."
(MPU - H061830)

.'

o 4V

Th
Th+TI

xl0()%

Item

Symbol

Typ

Max.

Unit

tcye

1.0

-

-

~s

"High" level

tWEH

0.45

-

~s

"Low" level

tWEL

-

-

lJS

-

25

ns

25

ns

-

ns

Enable cycle time
Enable pulse width

Min.

Enable rise time
"

..;";,,,,,,,£

';"

~tV

0.45

L", "

~:d

_
,

,

tEf

-

Setup time

tAS

140

-

Data setup time

tDSW

225

-

-

ns

Data delay time

tDDR

-

-

225

ns

Data hold time

tH

10

-

ns

Address hold time

tAH

10

-

Data hold time

tDH

20

-

-

Enable fall time

Note:

,','

'

The following l.oad circuit is connected for specification:

Vec

Test
point
R

RL = 2.4 k.n
R = l1k.n
C = 130 pF

Diodes Dl to D4: 1S2014

®

Note

ns
ns

-

I

.Interface to External RAM and ROM

SYNC

MAO-IS

t ......

MDo_y

I - - - h.. o--~
R0

<>-1

-+-'-'-to--t .....,--~

twwe:

Item

Min.

Typ

Max.

Unit

tDSY

-

-

200

ns

tWSY

900
900

"High" level

tWCPOH

450

-

ns

tccPO
"Low" level

tWCPOL

450

-

-

ns

MAO to MAlS refresh delay time

tDMAR

-

-

200

ns

MAO to MAlS write address delay time
MOO to MD7 write da~ta delay time

tDMAW

-

200

ns

tDM~

-

200

ns

MOO to MD7, RDO to RD7 setup time

tSMD

900

-

-

ns

Memory

tSMAW

250

-

ns

Memory data setup time

tSMDW

250

-

-

ns

WE delay time

tDWE

-

-

200

ns

WE pulse width ("Low" level)

tWWE

450

-

-

ns

"

Symbol

--

SYNC delay time

SYNC" pulse width

"High" level

CPO cycle time
CPO pulse width

address~setup

time

Note 1:

No load is applied to all the output terminals.

Note 2:

"*" indicates the delay time of RAM a,nd ROM.

ns
ns

,

• Data Transfer to Ori ver LSI

ell

......;;.:..,.....------------

"

... --',----------

el2

1

MAo MB

-Vcc
2

tDF'--i-t+--

tOM

FlM

01

tOO-i--+oI-ts

02

Item

Symbol

Min.

Typ

Max.

Unit

Clock pulse width ("High" level)

tWCLl

450

-

-

ns

Clock delay time

tDCL2

-

-

200

ns

Clock cycle time

tWCLZ

900

-

ns

"High" level

tWCH

450

-

ns

"Low" level

tWCL

450

-

ns

Data delay time

tDM

300

ns

Data delay time

tDF

-

-

300

ns

Data delay time

tDD

-

-

200

ns

Data setup time

tSD

250

-

ns

Clock pulse width

Note:

-

No load is applied to all the output terminals (MAt HB. FLM, Dl and
D2),~

l>isplay is controlled by writing data into the instruction register and 13
data registers.

The RS signal distinguishes the instruction register from

the data registers.

8-bit data is written into the instruction register

with RS=l, and the code of data register is specified.

The 8-bit data is

;::itten in the data register and the specified instruction is executed with

During the execution of the instruction, no new instruction can be
accepted.

Since the busy flag is set during this, read the busy flag and

make sure it is 0 before writing the next instruction.
(1)

Mode control
Code $"00" (hexadecimal) written into the instruction register specifies
the mode control register.

R/W

RS

DB7

DB6

DBS

DB4

DB)

DB2

DBI

DBO

Instruction reg.

0

1

0

0

0

0

0

0

0

0

Mode control reg.

0

0

0

0

Register

~
DBS DB4 DB) DB2 DBI DBO

1/0 1/0

>.

m~
...-4~

0.0

1-4

Q)
4.J

00

0

0

1

1

0

Cursor OFF, character blink

I

1

Cursor blink

0

0

0

1

1

0

1

1

0

0

m
m...-4
~

...-4
c:Q

en

I

Cursor ON

0

Cursor OFF

0

Cursor ON

1

Cursor OFF, character blink

1

0

1-4

c:

u~

0

..

0

..... u

1-4
:l

..cmQ) 4.J

en

oM

-Q)

U

~~

-U
>(

CG
...-4
m

c:

1-4
Q)

4.J

c:

I-4..c 0 WH

0ue

1:
0:

Master mode
Slave mode

1:

D1splay 0 N

0:

Di~plav

OFF

Graphic/character
display
Charac ter display
(Character mode)

~

C:0

HU

...-4
m

e
Q)

~

>(0

wu

-------t><
----- -----

Cursor blink

1-4
~

en_ en

oMZ

Cursor OFF

0

Q)

:-

Cursor/blink

Mode data

Graphic mode

(2)

Set character pitch
Register

R/W

RS

DB7

DB6

DBS

DB4

DB3

DB2

OBI

DBO

0

1

0

0

0

0

0

0

0

1

0

0

(V p - 1) binary

0

Instruction reg.
Character pitch
, . reg.'
,,'

(Hp - 1) binary

""

"

...•

Vp indicates the number of vertical dots per character.

The space be-

tween the vertically-displayed characters is considered for determination.

This value is meaningful only during character display (in the

character mode) and becomes invalid in the graphic mode.
The Hp indicates the number of horizontal dots per character in display,
including the space between horizontally-displayed

character~.

In the

graphic mode, the Hp indicates the number of bits of I-byte display data
to be displayed.
There are three Hp values.
Hp Oil 2 DBl DBO

(3)

6

I

0

1

7

1

I

0

8

1

I

I

Horizontal character pitch 6

7

"
"

8

Set number of characters
R/W

RS

DB7

DB6

DBS

DB4

DB3

DB2

OBI

DBO

Instruction reg.

0

I

0

0

0

0

0

0

I

0

Number-of-characters
reg.

0

0

0

Register

.

(Hn - 1) binary

Hn indicates the number of horizontal characters in the character mode
or the number of horizontal bytes in the graphic mode.
of horizontal dots on the screen is taken as n,
n

=

Hp x Hn

Hn can be set with an even number of 2 to 128 (decimal).

If the sum total

(4)

Set number of time division

(inverse of display duty ratio)
,,~

R/w

RS

DB7

DB6

DBS

Instruction reg.

0

1

0

0

0

Number-of-time shares

1'.,

!'>

Register
f:

I...'_',_r_e..;..g_"_________' I

·"

DB4' DB)

,',. (
...;

,.;.11"

~

0

0

,.' "

,"'

"~,, .:;.~. ~..,

,~,

'-_--JII...'_-.A..I_';.J;r,.;..'_,.&;;.'~.;...'_ _ _ .,_

"

DB2

DBI

0

1

1.,;;

,J:-

____
'
_ , ,_ •...",.....,

Nx indicates the number of time division in multiplex display_
I/Nx is a display duty ratio.
A value of 1 to 128 (decimal) can be set to Nx.
{S)

Set cursor

~\:f':

po~ition

R/w

RS

DB7

DB6

DBS

DB4

DB)

DB2

DBI

DBO

Ins truction reg.

0

1

0

0

0

0,

0

1

0

0

Cursor position
_.
reg.

0

0

0

0

0

0

Register

(Cp - 1) binary

Cp indicates the position ina character where the cursor is displayed
in the character mode.

For example,in 5x7 dot font, the cursor is

displayed under a character by specifying Cp=8 (decimal).
ho~izontal

The cursor

length is equal to the horizontal character pitch Hp.

value of 1 to 16 (decimal) can be set to Cp_

A

If a smaller value than

the number of vertical character pitches Vp is set (Cp

~Vp),

and a

character is overlapped with the cursor, the cursor has higher priority
of display (at curspr display ON).
is displayed.
(6)

If Cp is greater than Vp, no cursor

The cursor horizontal length is equal to Hp.

Set display start . low order a'ddress
.

-_.,

.

R/w

RS

DB7

DB6

DBS

DB4

DB)

DB2

DBI

DBO

Instruction reg.

0

1

0

0

0

0

1

0

0

0

Display start address
reg. (low order byte)

0

0

Register

(Start low order address) binary

Set display start high order address

(7)

Register
Instruction reg.
.,.

...

R/w

RS

0

1

Display start address
0
r;eg". (hig~ orrl~~? .,~y..t~L,

DSr' OB6

0
"~,J'- ,~

0

0
. ';; ~ «)'.-'"

~'

DBS

DB4

0

0

DB) "OB2
1

0

DBI
0

DBa.
,

(SC1'rt high o d.fer address) bihary
..
-?:,;

,,,,-", ~:'

I

1(

'q

i

,

DaO:

1,

These instructions cause display start addresses to be written in the
display start address registers.

The display start address indicates a

RAM address at which the data displayed at the top left end on the screen
is stored.

In the graphic mode, the start address is composed of high/

low order 16 bits.

In the character display, it is composed of the lower

4 bits of, high order

ad9r~ss

arid 8 bi ts of low order address.

The upppr

4 bits of high order address are ignored.
(8).

Set cursor address {low ordeF} {RAM write low order address}
R/W

RS

DB7

DB6

DBS

DB4

DB3

DB2

OBI

DBO

Instruction reg.

0

1

0

0

0

0

I

0

1

0

Cursor address counter
{low order byte}

0

0

Register

(9)

(Cursor low order address) binary

Set cursor address {high order} {RAM write high order address}
,

R/W

RS

DB7

DB6

DBS

DB4

DB3

DB2

OBI

DBO

Instruction reg.

0

I

0

0

0

0

1

0

1

I

Cursor address counter
(high order byte)

0

0

Register

{Cursor high order address} binary

These instructions cause cursor addresses to be written 1n the cursor
address counters.

The cursor address indicates an address for sending

or receiving display data and character codes to or from the RAM.
In the character mode, the cursor is displayed at the digit specified
by the cursor address.
(10)

Write display data
R/W

RS

DB7

DB6

DBS

DB4

DB3

DB2

DBl

DBO

Instruction reg.

0

I

0

0

0

0

1

I

0

0

RAM

0

0

Register

MSB (pattern data, character code) LSB

After the code S'OC' is written into the instruction register with RS=l,
8 bit data with RS=O should be written into the data register.

This

data is transferred to the RAM specified by the cursor address.

The

cursor address is increased by I after this operation.

(11)

Read display data

:-so.

Register

,;'

R/W

RS

DB7

DB6

DBS

0&4

DBl

DB2

DB1

0

1

0

0

0

0

1

1

0

Instruction reg.
I.

~

I RA.M
,

I

1

I

{J

.' , :"..

'..

I "

",.'

'~ i!I!_"'~.," .. ~,; ,,;~,t.~;

~

DBO

. fa.··
..

""",iii.;.

, ,
~"'~'''';7
-,_" . . . ~~~~~>,.. ,1>r_ N>OI~->-I~~ _~~~ ;-~;;~:.-:~:!.i< ~
...

"

1
.' ~

,~,."..,.,..,

.'"

'":~"'I.'r'\:-

.~."-.,,.;,;,;,...;,1'I'J.~.•",'

, •.r

Data can be read from the RAM by writing code $'OD' into the instruction
register with RS-O.

~~L

The read procedure is as follows:

_______________________________________________

E

R/~~______~
RS~

.

j

LJ

, - - I- - - - '

08

Ju.y

CU~o~

C.cso~

'ua~

eMd< ""n.. 1av
cIMoek
.oe
ordor
.....
vdco
.....n ..

....,....

c..uor

!::'c

r.,i..c.~

CUnor

ill"

CUnor

.....n..
•• c
.collA_:.....

a...?

aua,

cIMock

eIMctc

"4n..
vrtco

....

(
I
--------------------------11· ...... 3
- ::".44t...
N

-Nt..

N+ 2

J_N+2, ..

This instruction outputs the contents of data outputreaisl:er on Data
Bus (DBO to DB7) and then transfers RAM data specified flya cursor
address to the data output register, also increasiDg
by 1.

the~sor

address

After setting the cursor address, correct data is.nt output at

the first read but at the second time.

Thus, make ODe . . . , read when

reading data after setting the cursor address.
(12)

Clear bit
Register
Instruction reg.
Bit clear reg.

R/W

RS

DB7

DB6

DBS

DB4

0

1

0

0

0

8

0

0

0

0

0

0

2
,,

1

1

~

.8 -

DB1

DBO

1

0

1) binary

,

.

(13)

Set bit
Register

R/W

RS

DB7

DB6

DBS

DB4

DB3

DB2

DBl

DBO

0

1

0

0

0

0

1

1

1

1

0

A·

,0

0

0

0

0

(NB

Instruction reg.
"
~.~~'

Bit" , set
reg.
,\<;Oi "
~ ~.,

,

~"~J'~ "l.

;1I;l-: ,."

,,",,""''''''

...,,,,'"

""

"

.

{~

.-T',:",:
"""i"

"

'~

•

-

1) binary

""'W!'?

The Clear/Set Bit instruction sets 1 bit in a byte of display data RAK
to 0 or 1, respectively.
by NB.

The position of the bit in a byte is specified

After the execution of the instruction, the

automatically increased by 1.

curso~

NB is a value of 1 to 8.

address 1s

ND-l and NB 8

indicates LSD and MSB, respectively.
(14)

Read busy flag
Register
Busy flag

R/W

RS

DB7

1

1

I/O

DB

61 DBS I DB41 DB3 r DB2 lOBI lOBO

When the read mode is set with RS=l, the busy flag is output to DB7.
The busy flag is set to 1 during the execution of any of instructions,:
(1) to (13).

After the execution, it is set to O.

can be accepted.

The next instruction

No instruction can be accepted when busy f1ag=1.

Before executing an instruction or writing data, perform a busy flag
check to make sure the busy flag is O.

When data is written in the

register (RS-l), no busy flag changes.

Thus, no busy flag check is

required just after the write operation into the instruction register
with RS=l.
The busy flag can be read without specifying any instruction register.

I---HP-~

ROo

RD,

STA

I

I
I
I

)(

I

I
I
I

Z

I

I
I

I
I
I.
I

nOO[)CJnnD

OiilfliODOr~

- --- - - - - - - - - - --- - - - - -- -

.ooo.ona
.ooo.ood

-l--- --------I

I

;

.000.000
.000.000

I

:

.ooo.ood

:
I

0 ••• 0000
00000000

I

--'---+lfOOOCIOOOq

;

I~---------------HN--------------~I
I
(digit)
I
Symbol

Name

Hp

Horizontal character
pitch

Lateral character pitch

6 to 8 dots

Number of horizontal
characters

Number of lateral characters per
line (number of digits) in the
character mode or number of bytes
per line in the graphic mode.

2 to 128
digits
(an even
number)

Vertical character
pitch

Longitudinal character pitch

1 to 16
dots

Cursor position

Line number on which the cursor
can be displayed

1 to 16
line

Number of time
division

Inverse of display duty ratio

1 to 128
lines

HN

Vp
Cp
Nx
Note:

Meaning

Value

If the number of vertical dots on screen is taken as m, and the
number of horizontal dots as n,
11m = l/Nx = display duty ratio
n = Up x Hn, m/Vp = No. of display lines
Cp ~Vp

Display mode

,

Display data
from MPU

RAM

. b7 b6 bs
I
1

I
1
1
1
1

Character
dispaly

Character code
(8 bits)

0

Start
~ 0
address
I

1
1

0

I
I

,

I

1

I·

I
I
I
I

1
1
1

1
1

I

I
I

0 0

,

1
1
1

1

I

I

1
1

1

I
I

1

I

I
I

I

1
1
I

I

t

I

t

I
I

1

1

I

I

I

I

I

I

I

1

1

I
I
I

I

1
I

.. :

=;

"

I

~

'<

r
B

C

!
L-,'

1

1 0
1
1
1

t
I

1
I

I

1
1

i'

I
I
1
1

"

6, 7 or 8 dots

Hp:

.
I

1

I
I

I
I
I
I
I
I
I
I

I

1

1
1

I

I
1

Graphic

Display pattern
(8 bits)

Start
address

-----

t
I
b3 bz b l bo

_ '

b~

b7 b, bs
I
I
I
I

1

I
1
1

I

I

S

:
I

I

1

I
I

1

1
1
1

1

I

I

1
1
I

I

I

1

I

1

1

I

I

1 0 1 0 1 0
1 1 1 1 1 1 1

:

I

1

1

I
I

I

I

.

I
1

1

I

I
1

I
I
I
I

I

I
1
I

I

I

I

I

• •

1
1
1

bo

b7 1

••••

Hp

I

I

1

I
1

I

8 dots

I
1

8 dots

•

0

I
I
I
I
I
I

....

Hp

I

,

Hp

11\

't:)

I

0

0

..J.

A

I

1

I

0 0 0

0

I

I

I

I

I

1

1

1

I
1

I

I
I

I

I

I

1

I

b3 bz b l bo

b~

1

1
1
1
1

I

••.....o

Liquid crystal
display panel

1
1
I

I

I

I
I

I

1

1

I

I

I

Hp:

8 dots

elntema 1 Character Generator Patterns and Character Codes
iJher

1.0...
bitOOIO
~
~

4bi 1

)()()()(OOOO

0011 o 100 0 I 01

'• ,........

01100111

1010

1011 1100 1101 1110 1111

1·-1
_.•• .----.•. ...•• -.. ... ..•
-:" •• ·.•
•••• .-.1 ...
I .!
1.-1 •••••
._.
....
: ...! :::
..
J.
· •••
_. •••••
•
• •••
I···: I···.
II
:
•··C·• ••••••• ••••••
" II:
..,
•
•
•
• •....•• I···.
.:..."" !... ! .. I...: :•
••• ...
i··· .....•:. ..... I···· ... _.
U
-_...) .. • •.-..
.:.:.
:
.•.•
• I
.....
i::: •-•
::
••••• .:::: ..... ..... .J
.:.. .: ::...I ..:.. ••••••: .E•
!
·.1.
1-:
!
:
•.. ··r •• ····1
• :• ....
I· ·
-I·- :··i· !... I ....
.:
•••••
•
••••• •••••
I ••:

• • ••• :-

.. ... I
••••• •••••
1-1 I·-....I
•• I

1:..1 • :•

,.~

• •I

I

'.

)()(x)(OOOI

Xx)(x0010

•

I

••••

•••••

••••

I

•••••

x)()(xOOll

• ·1
I.·
•

• ••• 1

T

xxxxOl00

• I

e

I;; •

I

;;

••• • .: I.

~-)(-)(-X-0-l-0-1~hl:",::r.-.:-: -'-"'P:~...-."'I"""'- -:i"':=~
' .. r[fl
~j 1'~·l~11fTf~!."lj
I::"
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.EXAMPLE OF CONFIGURATION
eGraphic Mode
Uquid crystal
display module
·MO.~,

- Character Mode (1) (I nterna 1 Character Generator)
Liquid crystal
display modu,le

H061830
"

MAo_II

-Character Mode (2) (External Character Generator)
Liquid crystal
display module

H061830

eParallelOperation
(Master)
1 - - - - - - 1 Liquid crystal

display module
(1)

CR SYNC

H061830 /21

CS(Slave)~~_~

HD61602/HD61603
(SEGMENT TYPE LCD DRIVER)
The H061602 and the H061603 ace liquid crystal display driver LSIs with TTL
and CMOS compatible interface.

Each of the LSls can be connected to various

micro<:..driver

I

a

Data
contt'oller

WE
RE

RAM write
timing
generator

I
-~ IDa ta

la tcl1

oo·o;rv' IS bit x 2
sa

--

~~

..
~/

L...t-..

......

~ode

Parallel/sedal ~
converter
Display

data RAM
Address
decoder

setting ~OPERATION
i=MODE
latch

LCD driving
voltage
generator
111

Il
IlL [T

I I
10 I/DO

1/.
1/,
1/)

Driving
voltage
selection

1

1

I

~

Common output
(4 lines)

I- ~
I- ~

Segment Idriver I--

Segment output
(51 lines)

• HD61603
SYNC

I
lI
I

1(
T

LCD driving
timing
generator

I
I

osc
fADY

'.',~~'.

'

B

I Data
I
--"controller L

WE
1(l"

I
,

RAM write
timing
generator

.

....

lPa ta la tC11
~fV' 14 bit x 4 f - I

sa

Common
driver

-,

I~

.!J
Mode

~

l

.... ~arallel/ser1alF-~converter

Address
decoder

J\..

~

setting
latch

Conunon
output

~

pisplay r~ata RAM to-

~

Segment
fdrtver

Segment
r-::) output
(64 lines)

f=
"

' ..

• ABSOLUTE MAXIMUM RATINGS
Item
.-~.--

.. -.

Symbol

-~

....

~-

._-

__ ._. __ Limi t,._.-

Unit

..

Power supply voltage*

VSS, VI, V2, V3

0.3'" -7.0

V

Terminal voltage*

VT

0.3 '" VSS-O. 3

V

Operating temperature

Topr

-20 '" +75

Storage temperature

Tstg

-55 '" +125

°c
°c

* Value referred to VDD=OV.
Note:

If LSIs are used above absolute maximum ratings, they may be permanently
destroyed. Using them within electrical characteristics limits is
strongly recommended for normal operation. Use beyond these conditions
will cause malfunction and poor reliability •

• RECOMMENDED OPERATING CONDITIONS
Item

Symbol

Power supply voltage*

-VSS
-VI, -V2, -V3

Limit
Typ

Min.
2.2
0

Terminal voltage*

-VT

0

Operating temperature

Topr

-20
'.

~'.:

Max.

Unit

-

5.5

V

5.5

V

-

-VSS
15

V

°c
,,.._ ....

-

• ELECTRICAL CHARACTERISTICS
-UC

Characteristics (l)

{VSS=OV, vnn-4.S to 5.5V, Ta=-20 to +75°C, unless otherwise noted}
-.

,

Item
Input "High" voltage
Input "Low" voltage
Output leakage
current
'Output "Low" voltage

Symbol
OSCI

VIHl

Others

VIH2

OSCI

VILI

0

READY

IOH

Vo=Vnn

REAny

VOL

IOL==0.4mA

IlL
-_.-

Limit
Min. Typ Max.
'L/

-

-.

-

,. L""

~"

'

"'"''''

Inn

During displayllo

-

Inn

At standby

-

COMO'vCOM3

Vdl

t

SEGO'vSEG50

Vd2

tld-J~

tct-1UA

;;-;';;;',!.'

;oicn 't.:.1'i

for each SEC

-

-

-1.0

VIN=(}'\,vnn
'.~

!

Uni

Vnn

V

VDn

V
V

0. 2V nn
0.8

-

0

-'-

-

•

0. 8V nn
2.0

VIL2

Power supply current

*

Test condition

Others

Input leakage current
Lcn driver voltage
drop

-

._-_..

.~

V

5
0.4

lJA
V

1 .0

lJA

1.

'4"''''':'[".

, .. Coo

.:...

' 0.3

I
:

-

0.6

V

I

-

100

lJA

-

5

l1 A

';0""

v

Except the transfer operation of display data and bit data •

• DC Characteristics (2)
{VSS=OV, VDD=2.2 to 3.8V, Ta=-20 to +75°C, unless otherwise noted}
Item

Symbol

Input "High" voltage

VIH

Input "Low" voltage
Output leakage
current
Output "Low" voltage

VIL

Power supply current

Limit
!
Min. ! Typ Max.

Unit

-

V

O.8VDD.

VnD
0.2VDD

V

5

lJA

IO.lVDD

V

-

0

-

I

VOL

VIN""VDn
IOL=0.04mA

-

I

IlL

VIN-O'vVSS

-1.0

-

1.0

l1A

COMO'vCOM3

Vdl

tld-)UA for eacb COM

-

0.3

Vd2

tld-JuA for each SEC

, 0.6

V

SEGD-vSEG50

ISS

During display"ll

50

ISS

At standby

-

l1 A
lJA

REAny

IOH

READY

Input leakage current
Lcn driver voltage
drop

Test condition
-

*.,Except the transfer operation of display data and bit data.

-

I -

I

-

I
I

5

V

• AC Characteri s t; cs (1)
(VSS-OV. VDD-4.5 to 5.5V. Ta--20 to +75°C, unless otherwise noted)
Item

Symbol

c

100

40

50

60

ts

400
10

-

ns

tH
tWH

300
400

ns

400

-

ns

tWL

-

-

-

600

ns

-

-

ns

OSCI

External clock duty

OSCI

fosc
Duty

Ros =30-0kn

.. ,,

I/O signal timIng

tWR

I"
I'

Fig. 5

tEN

400
For display
10.5
data transfer
For bit and mode
3.5
data transfer

tOP2

Input signal rise time
and fall time

-_.

tDL
tOPI

--

-

-

External clock frequency

!"~

Unit

100

fQ'~c

,.,",.) "!

Limit
Min. Typ Max.

-

OS,~2.;;·.

Oscillation frequency . ~.

Test condition

-

t r • tf

kHz
kHz
%

ns

ns

-

11.5 -G-lock

-

4.5 Clock

-

25

ns

.AC Characteristics (2)
(VSS·ov, VDD-2.2 to 3.8V. Ta--20 to +75°C. unless otherwise noted)
Item

Symbol

100

fosc

100

-

Duty

40

50

60

ts

1.5

tH

1.0

tWH

1.5

tWL

1.5

-

-

OSC2

fosc

External clock frequency

OSCI

External clock duty

OSCI

tDL

.

,

.

t

Fig. 6

1.5

tEN

2.0
For display
10.5
data transfer
For bit and mode
3.5
data transfer

tOP2
Input signal rise time

Rosc::: 330kfl

tWR
tOPI

and fall time

Limit
Min. Typ Max.

-

Oscillation frequency

I/O signal timing

Test condition

r • tf

-

-

I

2.0

-

Unit
kHz
kHz
%
~s
~s
~s
~s

~s
~s
~s

-

11.5 Clock

-

4.5 Clock

.,

5.0
. ,

~s

\\

\"':----.--

,
\

~-----tWH--------

V 1l
tWl

V 1H

V 1H

V 1L

V 1l
ts

Fi g.

1

tH

Wri te Timi ng
~RE is fixed on "High" level t and SYNC on "Low" level)
J

I

N

V 1H

'~

EN

/

"'V1H

1\ V 1l

j

tWR

~ VOL

READY
tOl

V 1l

tOl-

I

:t
V

OH

~

Fig. 2 Reset/Read Timing
(CS and SYNC are fixed on "Low" level)

READY

1---------------- t OP1. toP2 - - - - - - - - - - - \
Fig. 3 READY Timing
(When the READY output is always available)

r------------------------------------~------------------

VOH

READY

----------------1 clock
·V1H

. Fig. 4 SYNC Timing

Voo

Voo

470kQ

Measurement
terminal

Measurement
terminal

(READY)

(READY)

30pF

T

30PF

~--~----~---V~

Vss

Fig. 5 Bus Timing Load Circuit
(LS-TTL Load)

Fig. 6 Bus Timing Load Circuit
(CMOS Load)

• TERMINAL FUNCTIONS
eHD61602 Terminal Functions
:~-:::~,L;~it~~:-,:,": -,..
No. nf
Iqput/output
lines
to
_,_~r.',~"--7""

.-~

Te rmina 1
name

~ ;c,"'''''';'

"

,::~~i)'B

1

Power supply

READY

1

NMOS open
MCU
drain output

r·i.....~

EB

VDD

.

; ;.,

<,,~~~~~i<
.,. '

.,,(,,]

I

~

.~,

-side power supply

During setting data in the display
data RAM and mode setting latch in
the LSI after data transfer, "Low"
is output to the READY terminal to
inhibit the next data input. There
are two types of modes: one in
which "Low" is output only when both
of CS and RE are "Low", and the
other(in which "Low" is output
}
i
regl11.:l.1.cS.:i or CJ .:::.1 .. .
-"

CS

-

1

Input

MCU

Chip select input. Data can be
written only when this terminal is
"Low".

WE

1

Input

MCU

Write enable input. Input data of
DO to D7 is latched at the rising
edge of WE.

RE

1

Input

MCU

Resets the input data byte counter.
After both of CS and RE are "Low",
the first data is recognized as the
1st byte data.

SB

1

Input

MCU

"High" level input stops the LSI
0p.erations.

"

(i) Stops oscillation and clock
input.
(ii) Stops LCD driver.
(iii) Stops writing data into display RAM.
DOvD7

8

Input

VSS

1

Power supply

VREFl

1

Output

'''vREF2

MCU

Data input terminal from where 8-bit
x 2-byte data are input-

e
External
R

-side power supply

Reference 'voltage output. LCD driving voltage is generated by this
voltage.

..

1

Input

-',

'--'

.<

.-~,

External
R

Divides the reference voltage of
VREFI with external R to determine
LCD drivipg voltag~. VREF2;"Vl

I

Terminal
name

No. of
Input/output Connected
lines
to
2

VCl. VC2
.

Output

.-

--<
"

<"

~<~ ~.

-~

',,"

, ,-:~,,,-.-«,,.

.

Function

External
C

Connection terminals for boosting C
of LCD driving voltage generator •
.(:! X t<~t!lfL...C is connected between
Cl and VC2:

wl~~:t,~.\

VI. V2.
V3

3

Output
(Input)

External
C

LCD driving voltages are output.
An external C is connected to each
terminal.

COMO\.COM3

4

Output
(Input)

LCD

LCD common (backplate) driving
output.

51

Output

LCD

LCD segment driving output.

1

Input

MCU

Synchronous input for 2 or more
chips application. LCD driver
t-im! ng- ci-rcu i t is reset by "High'L
input. LCD is off.

External
R

Attaches external R to these terminals for oscillation. An external
clock (100kHz) can be input from ,
OSCI.

I.~EG50

SYNC
------

---

~'.

-

:t.

2--

OSCI

Input

OSC2

Note:

-

Output

Logic polarity is positive.

"1"="H"=active.

eHD61603 Tenminal Functions
Terminal
name

No. of
Connected
Input/output
to
lines

Function

® -side power supply

"DO

I

Power supply

READY

I

NMOS open
MCU
drain output

During setting data in the display
data RAM and mode setting latch in
the LSI after data transfer. "Low"
is output to the READY terminal to
inhibit the next data input. There
are two types of modes: one in
which "Low" is output only when both
of CS and RE are "Low". and the
other in which-':Low" is output
regardless of CS and RE.

CS

I

Input

MCU

Chip select input. Data can be
written only when this terminal is
"Low" •

WE

1

Input

MCU

Write enable input. Input data of
DO to OJ is latched at the rising
edge of tm.

:

,

~j

• .,1-.... , ••

Terminal
name

No. of Input/output Connected
to
lines
Input

1

RE

MCU
,

~

'.,

f
-. . ,,

Function
Reset the input data byte counter.
After both of CS and RE are "Low".
the first data is recognized as the
... '-.... ~~r!:~. "~ta I: .'
::,,,,~
~

~'

'wd

,,;

.'1.. "

,i",

'i', '

.

,~, "

,:~

SB

I

Input

MCU

"High" level input stops the LSI
operations.

'.

(i) Stops oscillation and clock
input.
(1i) Stops LCD driver.
(iii) Stops writing data into display RAM.
DQ\.D3

4

Input

VSS

I

Power supply

V3

.. I

COMO

Input

Data input terminal from where 4-bit
x4 data are input.

MCU

e -_}.2:.

':",';':r.

.(

t:."~ ~:. ;: ~": 1"', '"

:

~,.

.

Power
supply

Power supply input for LCD drive.
Voltage between VDn and V3 is used
as driving voltage.

I

Output

LCD

LCD common (backplate) driving
output.

64

Output

LCD

LCD segment driving output.

SYNC

I

Input

MCU

Synchronous input for 2 or more
chips application. LCD driver
timing circuit is reset by "High"
input. LCD is off.

OSCl

2

Input

External
R

Attaches external R to these termi!Oats for oscillation. An external
clock (100kHz) can be input from
OSCl.

SEGOvSEG63

OSC2

Note:

Output

Logic polarity is positive.

,

"l"-"H"-active.

~<

• 01 SPLAY RAM
<

HD6l602 Display RAM

>

The H061602 has an internal display RAM shown in Fig • .7.
stored in the RAM. or is read according to
i::~' , :)
~on9theLCp..
;" ,

,

" "',

'

,

,

, " .'

~;he

!

Display data is

LCD driving timing to display

One, bit of the RAM corresponds 'to the 1 segment of LCD.

Note

that some bits of the RAM cannot be displayed depending on LCD driving mode.

Common address
(COMO\.COM3) -

~(

Display RAM
~------------------------------------------------~
/

51 bits
Segment address (SEGo"-SEGso)

Fig. 7 Display RAM
eReading Data from Display RAM
A display RAM segment address corresponds to a segment output.

The data at

segment address SECn is output to segment output SEGn terminal.
A common address corresponds to the output timings of a common output and a
segment output.

The same common address data is simultaneously read.

The

data of display RAM is reproduced on the LCD panel.
When a 7-segment type LCD driver is connected, for example. the correspondence
between the display RAM and the display pattern in each mode is as follows:
(1)

Static drive
In the static drive, only the column of COMO of display RAM is output.
COM1 to COM3 are not displayed.

LCD connection

.

2

'"

(!)

(!)

V)

V)

w w

-

...

...

Display RAM

! :
(!)
w w
V)

(!)

(!)

(!)(!)

(!)

V)

CI)

V) V)

V)

w

w

ww

1/2 duty drive

(2)

LCD connection

Display RAM

a

COM 2
--- COM,
---COMo

(!)

(!)

...
(!)

V)

V)

CI)

•

w

1ft

w

(!)

a

9

c

b

COMo

f

e

d

DP

SEG. SEG s SEG e SEG 7 SEG a SEG g

,..
CI)

COM,

w

w

In the 1/2 duty drive, the columns of COMO and COMI of display RAM are
output in time sharing.
(3)

The columns of COM2 and COM3 are not displayed.

1/3 duty drive
LCD connection

Display RAM
COM 3

--- --COM,
---COMo
..,
C>
w

en

C>

...
C>

V)

V)

•

w

w

V V V L IV

COM 2

y

COM,

OJ

COMo

e

a

b

9

c

d

DP

SEG 3 SEG. SEG s SEG e

1n the III duty drive, the columns of COMO to COH2 are output in time
sharing.
(4)

No column of COM) 1s displayed.

1/4 duty drive
LCD connection
a

Display RAM

.----------COM l
·it

e
-- --COMo

...

. COM l

f

a

COMz

9

b

COM l

e

c

COMo' d

DP

...

CJ.

C)"

en

en

w

..-----'.

.J+ -.,

w

In the 1/4 duty drive, all the columns of COMO to COM3 are displayed •

• Writing Data into Display RAM
Data is written into the display RAM in the following five methods:
(1)

Bit manipulation
~.-

Data is written into any bit of RAM on a bit basis.
(2)

Static display mode
8-bit data is written on a digit basis according to the 7-segment type
LCD pattern of static drive.

(3)

1/2 duty display mode
8-bit data is written on a digit basis according to the 7-segment type
LCD pattern of 1/2 duty drive.

(4)

1/3 duty display mode
8-bit data is written on a digit basis according to the 7-segment type
LCD pattern of 1/3 duty drive.

(5)

1/4 duty display mode
8-bit data is written on a digit basis according to the 7-segment type
LCD pattern of 1/4 duty drive.

The RAM area and the allocation of the segment data for I-digit display
depend on the driving methods as described in the selection of "Reading Data
from Display RAM".

8-bit data is written on a digit basis corresponding to the above duty
driving methods.
digit).

The digits are allocated as shown Fig. 8 (allocation of

As the data can be transferred on a digit basis from a microcomputer •

.~ransfer efficiency is improved by allocating the LCD pattern according to
the allocation of each bit data of the digit in the data RAM.
rIg •.8 shows the dig1.t
of the transferred 8-bit data on a digit basis.
Fig. 9 shows the correspondence between each segment in an Adn and the 8-bit
input data.
When data is transferred on a digit basis, 8-bit display data and digit
address should be specified as described above.

Static

(1)

COMo COM, COM2

SEGo

(2)

1/2 duty
display

COMo COM, COM2

SEGo

(3)

1/3 duty
display

COMoCOMtCOMzCOM 3

AdO

COMoCOM ,COM zCOM3

SEG 3

SEG s

SEG s

SEG.

SEG.

SEG 7

SEG7

SEG7

SEG.

SEG.

SEG.

SEG s
Ad1

SEG.
Ad2

SEG 7
SEG.
SEG.

SEG.

SEG.

SEG,o

SEG,o

SEG I1

. SEG II

SEG II

SEG 12

SEG 12

SEG'3

SEG 13

f.-

Ad2

-

Ad3

-

Ad4

f.-

AdS

Ad3

t--+--t'

SEG'3

Ad6

Ad4

SEG 13

SEG'4

SEG'4

SEG 15

SEG 15
...-......- y

AdS

SEG,.
SEGI7

Ad1

~_-.....-f"

SEG.

t--+--+--f'

SEG 12

...

Ad1

SEG4

SEG 12

AdO

SEG,
SEG z

SEG 3

SEG.

1/4 duty
display

SEGo

SEGo
AdO

SEG 2

(4)

SEG u
SEG'I

Ad7

r-

Ad8

'""

Ad24

SEG 16
SEG 17

J--+----I--r
Ad6

f-

SEG,.
\

SEGso

.

SEGsoT~__A_d_2_S_--,r

(1)

Static display

(2)

1/2 duty display
COMo COM,

COMo

Bit

SEG In
"

.

._

6

SEG In +2

5

SEG'n+3

4

SEG'n+4

3

SEG'n+s

2

5

Bit
7

6

X
3

4

5

4

2

2

1

Bit
0

Bit

o

(4)

1/4 duty display
COMoCOM,COM 2 COM 3

J3JJ; """'6--

SEG'n+8
SEG In +7

COMo COM, COM 2

i':'VJ", ,,,-;:;

't-,

SEG In + ,

1/3 duty display

Bit
6
"!,;;.tt;,,,.

7
S

(3)

7

Bit ----

3

0

~

5
1

4

Bi-t-

a

Fig. 9 Bit Assignment in an Adn (HD61602)
In the bit manipulation, anyone bit of display RAM can be written.

When

data is transferred on a bit basis, I-bit display data, a segment address
(6 bits) and a common address (2 bits) should be specified.
<

HD61603 Display RAM >

The HD6l603 has an internal display RAM as shown in Fig. 10.

Display data

is stored in the RAM and output to the segment .output terminal.
1 bit

(COMO) { IL.._ _ _ _ _---.,;..._ _ _ _ _
D~_·s..:.p_l_ay::...-RA_M_ _ _ _ _ _ _ _ _ _ _~I

'----------

------------------v~----------------------------------/

64 bits
Segment address

Fig. 10 Display RAM (HD6l603)
• Reading Data from Display RAM
Each bit of the display RAM corresponds to each LCD segment.

The data at

segment address SEGn is output to segment output SEGn terminal.

Fig. 11

shows an example of the correspondence between the display RAM bit and the

LCD connection
Display RAM

SEG e SEG, SEG,o SEG" SEG u SEG I l SEG'4 SEG'5 SEG'6
--COMo

.

". C
...

C)C)

w w

U)U)

C)
w

U)

Fig. 11

Example of Correspondence between Display RAM Bit
and Display Pattern (HD6l603)

eWriting Data into Display RAM
Data is written into the display RAM in the following two methods:
(1)

Bit manipulation
Data is written into any bit of RAM on a bit basis.

(2)

Static display mode
8-bit data is written on a digit basis according to the 7-segment type
LCD pattern of static drive.

The 8-bit data is written on a digit basis into the digit address (displayed
as Adn) shown in Fig. 12.

When data is transferred from a microcomputer,

four 4 bit data are needed to specify the digit address and an 8-bit display
data.

Fig. 13 shows the correspondence between each segment in an Adn and

the transferred 8-bit data.

COMo

SEGo
SEG ,
SEG 2
SEG J AdO
SEG 4
«)EG s
SEG 6
SEG 7

COMo

SEG Sn

SEG a

Bit
7

SEGsn +1

6

SEGSn +2

5

SEGan +3

4

SEG 8n +4

3

SEGan + s

2

SEGSn +6

1

SEG 9

SEG S2
SEG S3
SEGs4

SEG '4
SEG ,S
SEG '6
SEG 17

SEG S7

Bit

SEG;s

SEG ss

0

SEG '9

Ad2 SEG S9 Ad7

SEG 20

SEG 60

SEG21

SEG 61

SEG 22

SEG 62

SEG 23

SEG6l

Fig. 13 Bit Assiqnment in an Adn
(HD61603)

SEG 24

Fig. 12 Allocation of Digit
(HD61603)
In the bit manipulation, anyone bit of display RAM can be written.

When

data is transferred on a bit basis, I-bit display data and a segment address
(6 bits) should be specified .

• Operating Modes
< HD61602 Operating Modes>
The HD61602 has the following operating modes:
(1)

LCD drive mode
Determines the LCD driving method.
(a)

Static drive mode

LCD

is

driven

sta,t~,?~~l:l.'~

(b)

1/2 duty drive mode
LCD is driven at 1/2 duty and 1/2 bias.

(c)

1/3 duty drive mode
LCD is driven at 1/3 duty and 1/3 bias.

(d)

1/4 duty drive. mode
LCD is drivp.n at

(2)

l/~

Data display mode
Determines how to write display data into the data RAM.
(a)

Static display mode
8-bit data is written into the display RAM according to the digit
in the static drive.

(b)

1/2 duty display mode
8-bit data is written into the display RAM according to the digit
in the 1/2 duty drive.

(c)

1/3 duty display mode
8-bit data is written into the display RAM according to the digit
in the 1/3 duty drive.

(d)

1/4 duty display mode
8-bit data is written into the display RAM according to the digit
in the 1/4 duty display drive.

(3)

READY output mode
Determines the READY output timing. .
After data set is transferred, the data is processed internally.
next data cannot be acknowledged during the processing period.
READY output reports the period to the MPU.

The
The

The timing when the READY

is output can be selected from the following two modes:
(a)

READY is always available.

--J/

\~-

CS_ _ _ _ _ _ _

I

READY

--~--..-.-

\~----------------------~/:
:
_____
I

Data transfer --------_.~I------------- Input inhibit
period
:I
period

~--------.~:

: Next datB
transfel

(b)

READY 1s available by CS and RE.

,----------

cs

-------/

WE~,,
'

..-.

,

.,,

'--"',--'-', ~---J(

Lt

•.

I '

REA-D-Y----------~f----------~,,~____

\

/

•

~

Data transfer _ _ _.;.-_______ lnput inhibit _________'
period
period

( 4)

'-.,

LCD OFF mo-de

: Next data
, transfer

.~

In this mode, the HD6l602 stops driving LCD and turns it off.
External driving voltage mode

(5)

A mode ..for using external driving voltage (V1, V2 and V3).

The above 5 modes are specified by mode setting data.

The modes are

dependent of each other and can be used in any combination.

in~

The bit manipu-

lation is independent of data display mode and can be used regardless of it.
<

HD61603 Operating Modes >

The HD6l603 has
(1)

~he

following modes:

READY output mode
Determines READY output timing.
After data set is transferred, the data is processed internally.
The next data cannot be acknowledged during the processing period.
The READY output reports the period to the MPU.

The timing when READY

is output can be selected from the following two modes:
(a)
CS
WE

READY is always available.

_ _ _ _ _ _ _- - - - J

/

,,~-­

~---------------.\__/

\~---------------------------/:

READY
Data transfer ______.~,__---------- Input inhibit ___________
period
.
period

Next data
transfer

(b)

READV is available by

CS

and RE.

cs ______________~

\......._ - - - - - -

.,

\~'___

"'---....-----.J/
·
V

t

I

---------~----_r--~----------~

.

t

''-_-J

__J/.; .:.

READY
Data transfer
Input inhibit
period
------~---------------- period

(2)

I

•

:Next dat,q
transfer

LCD OFF mode
In this mode, the HD6l603 stops driving LCD and turns it off •

• INPUT DATA FORMATS

HD61602 -Input Data Fonnats
Input data is composed of 8 bits x 2.

Input them as 2-byte data after READY

output is changed from "Low" to "High" or "Low" pulse is entered into

RE

terminal.
Display data (Updates display on an 8-segment basis.)

(1)

1st byte

2nd byte
Display address
(Digit address Adn)

3

4

(i)

0

2

7

6

:

D~sPla~ da~a
5

4

3

2

: I
0

Digit address Adn in accordance with each display

Display address:

mode.
(ii)

Display data

Pattern data that is written into the display RAM
according to each display mode and the address.

Bit manipulation data (Updates display on a segment basis.)

(2)

1st byte

I

0

7

(1)

I

6

2nd byte

F~:la11

x

5

4

I I I~~~~ess I I I

Display data

x

x

3

2

1

COM address

x

7

6

SEG address
5

4

3

2

0

Data that is written into 1 bit of the specified
display

(ii)

0

x

RAM.

Common address of display RAM.

(iii)

(3)

SEC address

Segment address of display RAM.

Mode setting data
taf.~.l
ro-~

, ... 1,

1st byte

I I I
0

7

(i)

(ii)
(iii)

(iv)

6

x

[

5

I
I

2nd byte

)

0
4

READY

bit

3

i

Dri Ye eode

biu

I

2

Display mode bits:

OFF/ON bit
Drive mode bits

READY bit

1

0

II I
x

7

x

,

6

x

x
5

0'

4

00;

Static display mode

01;

1/2 duty display mode

10;

1/3 duty display mode

11;

1/4 duty display mode

I

X

3

~~/,
2

D.iaPla Y
iIIOde biu

I
.

I

1

0

1;

LCD OFF ("l" is set when SYNC is entered.)

0;

LCD ON

00;

Static drive

01;

1/2 duty drive

10;

1/3 duty drive

11;

1/4 duty drive

0;

READY outputs "0" only while, CS and RE is
"0". C'O" is reset when SYNC is entered.)

(v)

(4)

External power
supply bit

1;

READY outputs "0" regardless of CS andRE.

0;

Driving voltage is generated internally.

1;

Driving voltage is supplied from external.
(" }-!!-is set when SYNC is entered.)

I-byte instruction
1st byte

7

6

5

4

3

2

o

The first data (first byte) is ignored when the bit 6 and bit 7 in the
byte are "1".
<

HD61603 Input Data Formats >

Input data is composed of 4 bits x4.

Input them as four 4 bit data after

READY output is changed from "Low" to "High" or "Low" pulse is entered into
RE terminal.

(1)

Display data

(Upda~es

display on an 8-segment basis.)
1rd hyte

2nd byte

1st byte

Ol.pJ •••• dr_we
(Ot,. lot ~14r ... ~ ! .. ~.., '
•. ~

'::,",,c.~

.•• ,.",

~";'~

•• __

"
(i)
(Ii)

Display address:

Digit address Adn shown in Fig. 12.

Display data

Pattern data that is written into the display RAM
as shown in Fig. 13.

(2)

Bit manipulation data (Updates display on a segment basis.)

(i)

3rd byte

2nd byte

1st byte

o

o

, 1

o

4th byte
SEG address
bit3 2
1

0

2

0

Data that is written into the 1 bit of the

Display data

specified display RAM.
(ii)
(3)

Segment address of display RAM (segment output).

SEG address

Mode setting data
..

-.~

I : I
0

3

x

2

(ii)

(4)

I

0

I

0

I

x

I~DYI

3

2

OFF/ON bit

(1)

..

---.-

2nd byte

1st byte

READY bit

...

4th byte

3rd byte
x

:

x

0

I

I :
x

3

x :
2

x

:

x
0

I

I

x

I~~/ONI

3

2

0

:

O·,

LCD ON

O·,

READY outputs "0" only while CS and RE are "0".
("0" is reset when SYNC is entered).

I;

READY outputs "0" regardless of CS and RE.

1S

set when SYNC is entered.)

-

o

The first data (4 bits) 1S ignored when the bit 3 and 2 1n the data
are "I".

I

LCD OFF ("1"

1st byte

2

0

l',

I-byte instruction

3

0

• HOW TO INPUT DATA
How to Input HD61602 Data >

<

Input data is composed of 8 bits x 2.
not interrupted.

Take care that the data transfer is

Because the first 8-bit data is distinguished from the

seco~d one depending on:theseqoence only.
~

If data transfer is interrupted or at the power ON the following two methods
.
can be used to reset the count of the number of bytes (count of the first
'

and second bytes}:
(1)

Set CS and RE inputs in "Low" (no display data changes).

(2)

Input 2 or more "I-byte instruction data" which bit 7 and 6 are "1"
(display data may change).

The data input method via data input terminals (CS, WE, DO to 07) is similar
to that of static RAM such as HM6116.
same bus line as ROM and RAM.

An access of the LSI can be made through

When output ports of a microcomputer are used

for an access, refer to the timing specifications and Fig. 14.
Power ON

I

' \ ' -_______1

cs/
wt/
iiE/

_------,

\.....

.6
·6

.,
_______________

. . .__--,r:;-:.::::"_-::?3

RUo7::_":~~::::"-"-:::.,----~/lI-----------'\
SV~

\
~,,~,____________________~'----\~·_2___________________

SB------------------~.-----------------------------------------------------

o.

__AX__________________~X__Is_'~X~2_M~X________

o.~~,---~~....._'_~~X~2M

Hade setting data
data

Display data

*1:

READY output is indefinite during 12 clocks after the oscillation start
when power ON (clock: OSC2 clock).

*2:

"High" pulse should be applied to SYNC terminal when using two or more
chips synchronously.

*3:

In the mode in which READY is always available, READY output is indefinite while "High" is being applied to SYNC.

*4:

Reset the byte counter after power ON.

*5:

READY output period is within 4.5 clocks in the mode setting operation
and bit manipulation or within 11.5 clocks when the display data (8 bits)
is updated.

*6:

Connect a proper pull-up resistor if WE or RE may be floating.

< How to Input HD61603 Data>
Input data is composed of 4 bits x 4.
interrupted.

Take care that data transfer is not

Because the first 4-bit data to the fourth 4-bit data are

distinguished from each other depending on the sequence only.
If data transfer is interrupted ot" .:ll.: the P",,'p.r ON. the following two methods

.

.

can be used to reset the count of the n" .. r of data (r:ount "f r-l-e' first 4,'
bit data to the fourth 4-bit data):
(1)

Set CS and RE in "Low".

(2)

Input 4 or more "I-byte instruction" data (4-blt data) which bit 3 and 2
are "1" (display data may change).

The data input method via data input tenninals (CS. WE, DO to D3) is similar
to that of static RAM such as HM6ll6.
~hrough

An access of the LSI can be made

the same bus line as ROM and RAM.

When output ports of a micro-

computer are used for an access, refer to the timing specifications and
Fig. 15.

u-,. . ______

-J/

.
,
SYNC ________________________________

READY,:--------------:·
.. _ _ _ _ _ _ _ _ _ _ _ _ _ _ J

SB
00

\....._ _ _ _-.J/

II

\

11~1-----------------------------------Jr--\~·-2-------------------------

----------------------------~III~-----------------------------------------------------------------------------

D)-------------------<:===>---~~------~(~,~s'~X[2~M~X33~'dQl~4~,h~>__<~_____________~!_I~s'~X~2~M-AX~~-d~X~4_'h~X_______
Hade setting data

Display data

*1:

READY output is indefinite during 12 clocks after the oscillation start
when power ON (clock: OSC2 clock).

*2:

"High" pulse should be applied to SYNC terminal when using two or more
chips synchronously.

*3:

In the mode in which READY is always available, READY output is indefinite while "High" is being applied to SYNC.

*4:

Reset the 4-bit data counter after power ON.

*5:

READY output period is within 4.5 clocks in the mode setting operation
and bit manipulation or within 11.5 clocks when the display data (8 bits)
is updated.

*6

Connect a proper pull-up resistor if WE or RE may be floating.

• STANDBY OPERATION
Standby operation with low power consumption can be activated when terminal
S8 is used.

Normal operation of the LSI is activated terminal S8 is "Low"

level and the LSI goes into the standby state when terminal S8 is "High"
level.

The standby state of the LSI is as follows:

(a)

LCD driver is stopped and no driving voltage is generated (LCD are off).

(b)

Display data and operating mode are held.

(c)

The operation (in which READ'I is outputting "Low") during display change
is suspended.

In this case, READY outputs "High" within 10.5 clocks or

4.5 clocks after release from the standby mode.
Cd)

Oscillation is stopped.

When this mode is not used, connect terminal S8 to VSS .

• MULTI-CHIP OPERATION
When a LCD is driven with two or more chips, the driving timing of LCD must
be synchronized. -In this case, the chips are synchronized with each other
by using SYNC input.

If SYNC

it)p~.L is

"~",,,,,,----=,,"~-,--,,~.-.-,--,,=,-..--~--,-

is reset.

"High", the LCD_driver timing circuit

Apply "High" pulse to the SYNC input after the operating mode is

set.
A "High" pulse to the SYNC input causes the change of the mode setting data
(The OFF/ON bit is set and the READY bit is reset.
in "Input Data Formats".).

See (3) mode setting data

Tran.:;fer the mode setting data into the LSI after

every SYNC operation.
If a Power ON RESET signal is applied to the SYNC terminal, the LCD can be
off-state when the Power is turned on.
When SYNC input is not used, connect terminal SYNC to VSS.

• UQUtD CRYSTAl DISPLAY ORIVtNG VOLTAGE GL:NERATION CIRCUn

eWhen Internal Driving Voltage is Used

+ s ide _--

'<:~f"

c·· ';'.

,.,-

._.'

,'",

.-~

Note:
When standby mode is
used, a transistor is
required.

Fig. 17 An Example when External
,>

~.

•

LIQ~ID

CRYSTAL DISPLAY DRIVING VOLTAGE (HD61603)

As shown in Fig. 18, apply LCD driving voltage from the external power supply.

+side power---....----'-!v
oo
, 1
supply
Vss

Note:
When standby mode is used,
a transistor is required.

SB--'-t-i

Fig. 18 Example of Driving Voltage Generator

• OSCILLATION CIRCUIT
eWhen Internal Oscillator Circuit is Used
When the internal oscillator circuit is used, attach an external resistor
Rose as shown in Fig. 19.
Rose

Rose

80

79

asc,

asc 2

80

asc,

79

asc 2

-------NC
HD14049UB

etc.

80

asc,

79

asc 2

Multi-chip operation

Fig. 19 Example of Oscillator Circuit
eWhen External Clock is Used
When an external clock of 100kHz with CMOS level is provided, terminal OSCI
can be used for the input terminal.

In this case, open terminal OSC2.

• APPlI CATI ONS

·SV-

CN

A.,'1-::~:t:::t=::1

A.•• fA

Add,",'"

:lr>--.. . - - - - - -.. - . - - - - - - - - - - - .
G

t::::==:t=.---+-----.-- -.--..

Y

I

to,: DoH-__::~-:-=:_::_-__::,._--_+_---_f_+--...------------.
D.

._-+-l!---+-+---. ----------4-+--+-I.-----{
wtA'lCSSYNC O.ose,ose
0,

V•• ,
V...

H061 102

vcc''''- ·SV

N06'602

Vnr""l
j

NMIIOt

SEGo

·SlG..

SlG. .... -- -- .. SEG,.

• SV--~~~-------_+_+i++_----~--------·~

•
LCD

'--FTg.- 20

+SVTn

CI'U

·••

A,
A,
A.

HD74lSUI

r---

~
~

A

Add,. ., Ius

Example (1)

!

~~----.----.-----------~

I-

<=-..!.

•

0

OATABUS

0.

'- -.--~/ .----=--".-. -.---.-.-.-.-.-----+-.._f_-:::-I-.-/~,...f_-=----=--=--=--=--=-~~J

0.

11

~

BA

IIW

!
HD'.04'

I.J..
COMo

HD6I09

Voo

·0,

~f"EAD'
SB

H06'&03

v..

.

SEGo

WE 11£ CSSYNC 0. )SC.OSC.

/

.!w-

'SV

v.lf

HOll&03

Vee I- +SV
V.

I

MRtCSSYNC D.Ose.Ose.
D.

SEGo

+W

llr

v,

. .• SlG..

•

/

7

+SV

J

(

I

LCD

Fig. 21

(Used as

output
ports)

---

•
SlGo

/

.
EW

SlG.
SlG •

Vcc..--Vce

V..

II

j;I.
Vcr

~

~
(

.!!:

mo'

COM.
Ye • . COM,
y,
. - .SEGo·SEG..

"OnlOS

._-_._.-

~

WE 11£ B SYNC O. ose. ~se
0.
....
V~
V.... fII ADY
S
V..
HOll102
V.

/
Vcr -

CI
SB

Standby
input

Example (2)

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HITACHI, LTD. SEMICONDUCTOR AND
INTEGRATED CIRCUITS DIVISION SALES OFFICE
HEADQUARTER
Hitachi. ltd.
5·1. Marunouchi 1-Chome. ChiVoda·ku
Tokvo 100
Telephone: Tokvo (21211111
Cable Address: "HIT ACHY" TOKYO
Telex: 2225541
US SALES OFFICES
Hitachi America ltd.
Electronic Devices
Sales and Service Division
1800 Bering Drive San Jose. Calif. 95112
Tel: 408/292-6404
Telex: 17·1581
Twx:
910-338·2103
Fax: 408·2922133
SOUTH WESTERN REGION
Hitachi America. ltd.
Western Regional Office
97oo·Reseda Blvd. Suite 208
Northridge, Calif. 91324
Tel: 213·701-6606
NORTH CENTRAL REGION
Hitachi America. Ltd.
North Central Regional Sales Office
500 Park Blvd, Suite 415
Itasca, III, 60143
Tel: 3}2·773·4864
SOUTHERN REGION
Hitachi America, Ltd.
Southern Regional Sales Office
6200 Savoy Drive, Suite 704
Houston, Tex. 77036
Tel: 713·974·0534
Twx:
910·881·7043
NORTH EASTERN REGION
Hitachi America, Ltd.
Eastern Regional Sales Office
594 Marrentt Road. Suite 22 lexington, Mass. 02173
Tel: 617-861·1642
Twx:
710·326·1413
EUROPEAN SALES OFFICES (EU)
Hitachi Electronic Components Europe GmbH
Hans·Pinsel·straBe. 38013 Harr bei Munchen
Tel: 089-46140
Telex: 5·22593 (HITEC·OI
Fax: 089·463151
Branch offices
Hitachi Electronic Components Europe GmbH
VerkaufsbUro Dusseldorf
Konigsallee 6. 4000 Dusseldolf 1
Tel: 0211-84995
Telex: 8·584536 (HIEC·D)

Hitachi Electronic Components Europe GmbH
VerkaufsbUro Stuttgart
Fabrikstral1e 17.7024 Filerstadt 4
Tel: 0711·772011
Telex: 7·255267 (HIES)
Hitachi Electronic Components Europe GmbH
Bureau de Representation en France
95·101, Rue Charles·M ichels
93200 Saint Denis
Tel: 01-8216015
Telex: 611387
Fax: 01·2436997
Hitachi Electronic Components Europe GmbH
Milano Branch Office
Via B. Oavanzati, 27
1·20158 Milano
Tel: 02·3763024
Telex: 320343
Fax: 02-683730
EUROPEAN SALES OFFICES (UK)
Hitachi Electronic Components (UK) Ltd.
221·225 Station Road,
Harrow, Middlesex, HA 1 2X L England
Tel: 01-861·1414
Telex: 936293 (HITEC-G)
Fax: 01-863-6646
Branch office
Hitachi Electronic Components (UK) Ltd.
Box 1062. 163 11 Spanga, Sweden
Tel: 08· 751"()()35
Telex: 14106 (HITECST S)
ASIAN ~AlES OFFICES
Hitachi Semiconductor (Hong Kong) Ltd.
Room 706·707, 7/F, Wing On Plaza,
Salisburv Road. Tsimshatsu.
Kowloon. Hong Kong
Tel: 3·7219218
Telex: 40815 (HISAL HX)
Branch offices
Hitachi Semiconductor (Hong Kong) Ltd.
Taiwan Branch Office
No. 73.7th Fl-l. Fu Shing N. RD.
Hsing Nan Bldg. Taipei, Taiwan
Tel: 02-773·21623
Telex: 23222 (HISEKTWN)
Hitachi Semiconductor (Hong Kong) Ltd.
Singapore Branch Office
Unit 09-07. 9th Floor, Sultan Plaza 100,
Jalan Sultan. Singapore 0719
Tel: 292·7083. - 4
Telp.lc 35534 (HISEKS·R35534)



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